diff --git a/.editorconfig b/.editorconfig index b02e738da7..4fd7122fef 100644 --- a/.editorconfig +++ b/.editorconfig @@ -19,14 +19,6 @@ trim_trailing_whitespace = false indent_style = tab indent_size = 2 -[*/freertos/**] -indent_style = tab -indent_size = 4 - -[{*/freertos/**.S,**/FreeRTOSConfig.h}] -indent_style = space -indent_size = 4 - [*.pem] insert_final_newline = false diff --git a/.flake8 b/.flake8 index 0a4be0a0f7..7fe9791683 100644 --- a/.flake8 +++ b/.flake8 @@ -149,7 +149,6 @@ exclude = components/tinyusb, components/unity/unity, components/spiffs/spiffs, - examples/peripherals/secure_element/atecc608_ecdsa/components/esp-cryptoauthlib, # autogenerated scripts components/protocomm/python/constants_pb2.py, components/protocomm/python/sec0_pb2.py, diff --git a/.github/ISSUE_TEMPLATE/01_build_install_bug.yml b/.github/ISSUE_TEMPLATE/01_build_install_bug.yml new file mode 100644 index 0000000000..5814dced92 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/01_build_install_bug.yml @@ -0,0 +1,105 @@ +name: Installation or build bug report +description: Report installation or build bugs +labels: ['Type: Bug'] +body: + - type: checkboxes + id: checklist + attributes: + label: Answers checklist. + description: Before submitting a new issue, please follow the checklist and try to find the answer. + options: + - label: I have read the documentation [ESP-IDF Programming Guide](https://docs.espressif.com/projects/esp-idf/en/latest/) and the issue is not addressed there. + required: true + - label: I have updated my IDF branch (master or release) to the latest version and checked that the issue is present there. + required: true + - label: I have searched the issue tracker for a similar issue and not found a similar issue. + required: true + - type: input + id: idf_version + attributes: + label: IDF version. + description: On which IDF version does this issue occur on? Run `git describe --tags` to find it. + placeholder: ex. v3.2-dev-1148-g96cd3b75c + validations: + required: true + - type: dropdown + id: operating_system + attributes: + label: Operating System used. + multiple: false + options: + - Windows + - Linux + - macOS + validations: + required: true + - type: dropdown + id: build + attributes: + label: How did you build your project? + multiple: false + options: + - Command line with Make + - Command line with CMake + - Command line with idf.py + - Eclipse IDE + - CLion IDE + - VS Code IDE + - Other (please specify in More Information) + validations: + required: true + - type: dropdown + id: windows_comand_line + attributes: + label: If you are using Windows, please specify command line type. + multiple: false + options: + - PowerShell + - CMD + validations: + required: false + - type: textarea + id: expected + attributes: + label: What is the expected behavior? + description: Please provide a clear and concise description of the expected behavior. + placeholder: I expected it to... + validations: + required: true + - type: textarea + id: actual + attributes: + label: What is the actual behavior? + description: Please describe actual behavior. + placeholder: Instead it... + validations: + required: true + - type: textarea + id: steps + attributes: + label: Steps to reproduce. + description: 'How do you trigger this bug? Please walk us through it step by step. If this is build bug, please attach sdkconfig file (from your project folder). Please attach your code here.' + value: | + 1. Step + 2. Step + 3. Step + ... + validations: + required: true + - type: textarea + id: debug_logs + attributes: + label: Build or installation Logs. + description: Build or installation log goes here, should contain the backtrace, as well as the reset source if it is a crash. + placeholder: Your log goes here. + render: plain + validations: + required: false + - type: textarea + id: more-info + attributes: + label: More Information. + description: Do you have any other information from investigating this? + placeholder: ex. I tried on my friend's Windows 10 PC and the command works there. + validations: + required: false diff --git a/.github/ISSUE_TEMPLATE/02_runtime_bug.yml b/.github/ISSUE_TEMPLATE/02_runtime_bug.yml new file mode 100644 index 0000000000..8996025f2c --- /dev/null +++ b/.github/ISSUE_TEMPLATE/02_runtime_bug.yml @@ -0,0 +1,125 @@ +name: Runtime bug report +description: Report runtime bugs +labels: ['Type: Bug'] +body: + - type: checkboxes + id: checklist + attributes: + label: Answers checklist. + description: Before submitting a new issue, please follow the checklist and try to find the answer. + options: + - label: I have read the documentation [ESP-IDF Programming Guide](https://docs.espressif.com/projects/esp-idf/en/latest/) and the issue is not addressed there. + required: true + - label: I have updated my IDF branch (master or release) to the latest version and checked that the issue is present there. + required: true + - label: I have searched the issue tracker for a similar issue and not found a similar issue. + required: true + - type: input + id: idf_version + attributes: + label: IDF version. + description: On which IDF version does this issue occur on? Run `git describe --tags` to find it. + placeholder: ex. v3.2-dev-1148-g96cd3b75c + validations: + required: true + - type: dropdown + id: operating_system + attributes: + label: Operating System used. + multiple: false + options: + - Windows + - Linux + - macOS + validations: + required: true + - type: dropdown + id: build + attributes: + label: How did you build your project? + multiple: false + options: + - Command line with Make + - Command line with CMake + - Command line with idf.py + - Eclipse IDE + - CLion IDE + - VS Code IDE + - Other (please specify in More Information) + validations: + required: true + - type: dropdown + id: windows_comand_line + attributes: + label: If you are using Windows, please specify command line type. + multiple: false + options: + - PowerShell + - CMD + validations: + required: false + - type: input + id: devkit + attributes: + label: Development Kit. + description: On which Development Kit does this issue occur on? + placeholder: ex. ESP32-Wrover-Kit v2 | Custom Board + validations: + required: true + - type: dropdown + id: power_supply + attributes: + label: Power Supply used. + multiple: false + options: + - USB + - External 5V + - External 3.3V + - Battery + validations: + required: true + - type: textarea + id: expected + attributes: + label: What is the expected behavior? + description: Please provide a clear and concise description of the expected behavior. + placeholder: I expected it to... + validations: + required: true + - type: textarea + id: actual + attributes: + label: What is the actual behavior? + description: Please describe actual behavior. + placeholder: Instead it... + validations: + required: true + - type: textarea + id: steps + attributes: + label: Steps to reproduce. + description: 'How do you trigger this bug? Please walk us through it step by step. Please attach your code here.' + value: | + 1. Step + 2. Step + 3. Step + ... + validations: + required: true + - type: textarea + id: debug_logs + attributes: + label: Debug Logs. + description: Debug log goes here, should contain the backtrace, as well as the reset source if it is a crash. + placeholder: Your log goes here. + render: plain + validations: + required: false + - type: textarea + id: more-info + attributes: + label: More Information. + description: Do you have any other information from investigating this? + placeholder: ex. I tried on my friend's Windows 10 PC and the command works there. + validations: + required: false diff --git a/.github/ISSUE_TEMPLATE/03_feature_request.yml b/.github/ISSUE_TEMPLATE/03_feature_request.yml new file mode 100644 index 0000000000..64037600e8 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/03_feature_request.yml @@ -0,0 +1,34 @@ +name: Feature request +description: Suggest an idea for this project. +labels: ['Type: Feature Request'] +body: + - type: markdown + attributes: + value: | + * We welcome any ideas or feature requests! It’s helpful if you can explain exactly why the feature would be useful. + * There are usually some outstanding feature requests in the [existing issues list](https://github.com/espressif/esp-idf/labels/Type%3A%20Feature%20Request), feel free to add comments to them. + * If you would like to contribute, please read the [contributions guide](https://docs.espressif.com/projects/esp-idf/en/stable/esp32/contribute/index.html). + - type: textarea + id: problem-related + attributes: + label: Is your feature request related to a problem? + description: Please provide a clear and concise description of what the problem is. + placeholder: ex. I'm always frustrated when ... + - type: textarea + id: solution + attributes: + label: Describe the solution you'd like. + description: Please provide a clear and concise description of what you want to happen. + placeholder: ex. When connecting to an Espressif chip ... + - type: textarea + id: alternatives + attributes: + label: Describe alternatives you've considered. + description: Please provide a clear and concise description of any alternative solutions or features you've considered. + placeholder: ex. Choosing other approach wouldn't work, because ... + - type: textarea + id: context + attributes: + label: Additional context. + description: Please add any other context or screenshots about the feature request here. + placeholder: ex. This would work only when ... diff --git a/.github/ISSUE_TEMPLATE/04_other_issue.yml b/.github/ISSUE_TEMPLATE/04_other_issue.yml new file mode 100644 index 0000000000..cbd4a2c2a6 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/04_other_issue.yml @@ -0,0 +1,23 @@ +name: General issue report +description: File an issue report +body: + - type: checkboxes + id: checklist + attributes: + label: Answers checklist. + description: Before submitting a new issue, please follow the checklist and try to find the answer. + options: + - label: I have read the documentation [ESP-IDF Programming Guide](https://docs.espressif.com/projects/esp-idf/en/latest/) and the issue is not addressed there. + required: true + - label: I have updated my IDF branch (master or release) to the latest version and checked that the issue is present there. + required: true + - label: I have searched the issue tracker for a similar issue and not found a similar issue. + required: true + - type: textarea + id: issue + attributes: + label: General issue report + description: Your issue report goes here. + placeholder: ex. How do I run... + validations: + required: true diff --git a/.github/ISSUE_TEMPLATE/bug_report.md b/.github/ISSUE_TEMPLATE/bug_report.md deleted file mode 100644 index 6cc07f6e17..0000000000 --- a/.github/ISSUE_TEMPLATE/bug_report.md +++ /dev/null @@ -1,92 +0,0 @@ ---- -name: Bug report -about: ESP-IDF crashes, produces incorrect output, or has incorrect behavior -title: '' -labels: '' -assignees: '' - ---- - ------------------------------ Delete below ----------------------------- - -**Reminder: If your issue is a general question, starts similar to "How do I..", or is related to 3rd party development kits/libs, please discuss this on our community forum at https://esp32.com instead.** - -INSTRUCTIONS -============ - -Before submitting a new issue, please follow the checklist and try to find the answer. - -- [ ] I have read the documentation [ESP-IDF Programming Guide](https://docs.espressif.com/projects/esp-idf/en/latest/) and the issue is not addressed there. -- [ ] I have updated my IDF branch (master or release) to the latest version and checked that the issue is present there. -- [ ] I have searched the issue tracker for a similar issue and not found a similar issue. - -If the issue cannot be solved after the steps before, please follow these instructions so we can get the needed information to help you in a quick and effective fashion. - -1. Fill in all the fields under **Environment** marked with [ ] by picking the correct option for you in each case and deleting the others. -2. Describe your problem. -3. Include [debug logs from the "monitor" tool](https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/tools/idf-monitor.html), or [coredumps](https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/core_dump.html). -4. Providing as much information as possible under **Other items if possible** will help us locate and fix the problem. -5. Use [Markdown](https://guides.github.com/features/mastering-markdown/) (see formatting buttons above) and the Preview tab to check what the issue will look like. -6. Delete these instructions from the above to the below marker lines before submitting this issue. - -**IMPORTANT: If you do not follow these instructions and provide the necessary details, your issue may not be resolved.** - ------------------------------ Delete above ----------------------------- - -## Environment - -- Development Kit: [ESP32-Wrover-Kit|ESP32-DevKitC|ESP32-PICO-Kit|ESP32-LyraT|ESP32-LyraTD-MSC|none] -- Kit version (for WroverKit/PicoKit/DevKitC): [v1|v2|v3|v4] -- Module or chip used: [ESP32-WROOM-32|ESP32-WROOM-32D|ESP32-WROOM-32U|ESP32-WROVER|ESP32-WROVER-I|ESP32-WROVER-B|ESP32-WROVER-IB|ESP32-SOLO-1|ESP32-PICO-D4|ESP32] -- IDF version (run ``git describe --tags`` to find it): - // v3.2-dev-1148-g96cd3b75c -- Build System: [Make|CMake|idf.py] -- Compiler version (run ``xtensa-esp32-elf-gcc --version`` to find it): - // 1.22.0-80-g6c4433a -- Operating System: [Windows|Linux|macOS] -- (Windows only) environment type: [MSYS2 mingw32|ESP Command Prompt|Plain Command Prompt|PowerShell]. -- Using an IDE?: [No|Yes (please give details)] -- Power Supply: [USB|external 5V|external 3.3V|Battery] - -## Problem Description - -//Detailed problem description goes here. - -### Expected Behavior - -### Actual Behavior - -### Steps to reproduce - -1. step1 -2. ... - -// If possible, attach a picture of your setup/wiring here. - - -### Code to reproduce this issue - -```cpp -// the code should be wrapped in the ```cpp tag so that it will be displayed better. -#include "esp_log.h" - -void app_main() -{ - -} - -``` -// If your code is longer than 30 lines, [GIST](https://gist.github.com) is preferred. - -## Debug Logs - -``` -Debug log goes here, should contain the backtrace, as well as the reset source if it is a crash. -Please copy the plain text here for us to search the error log. Or attach the complete logs but leave the main part here if the log is *too* long. -``` - -## Other items if possible - -- [ ] sdkconfig file (attach the sdkconfig file from your project folder) -- [ ] elf file in the ``build`` folder (**note this may contain all the code details and symbols of your project.**) -- [ ] coredump (This provides stacks of tasks.) diff --git a/.github/ISSUE_TEMPLATE/config.yml b/.github/ISSUE_TEMPLATE/config.yml index cdacd0fb50..330081d147 100644 --- a/.github/ISSUE_TEMPLATE/config.yml +++ b/.github/ISSUE_TEMPLATE/config.yml @@ -1,4 +1,4 @@ -blank_issues_enabled: false +blank_issues_enabled: true contact_links: - name: ESP-IDF Programming Guide url: https://docs.espressif.com/projects/esp-idf/en/latest/ diff --git a/.github/ISSUE_TEMPLATE/feature_request.md b/.github/ISSUE_TEMPLATE/feature_request.md deleted file mode 100644 index 89593b1a8f..0000000000 --- a/.github/ISSUE_TEMPLATE/feature_request.md +++ /dev/null @@ -1,26 +0,0 @@ ---- -name: Feature request -about: Suggest an idea for ESP-IDF -title: '' -labels: 'Type: Feature Request' -assignees: '' - ---- - -**Is your feature request related to a problem? Please describe.** - -A clear and concise description of what the problem is. Ex. I'm always frustrated when [...] - -**Describe the solution you'd like** - -A clear and concise description of what you want to happen. - -**Describe alternatives you've considered** - -A clear and concise description of any alternative solutions or features you've considered. - -Please give as many details as you can. Include suggestions for useful APIs or interfaces if relevant. - -**Additional context** - -Add any other context or screenshots about the feature request here. diff --git a/.github/workflows/pre_commit_check.yml b/.github/workflows/pre_commit_check.yml index 177d10a573..a193112a0f 100644 --- a/.github/workflows/pre_commit_check.yml +++ b/.github/workflows/pre_commit_check.yml @@ -4,6 +4,9 @@ on: pull_request: types: [opened, reopened, synchronize] +permissions: + contents: read + jobs: pre_commit_check: runs-on: ubuntu-latest diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 35ccc993c9..866512c88f 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -57,28 +57,27 @@ variables: PYTHON_VER: 3.7.10 CLANG_TIDY_RUNNER_PROJ: 2107 # idf/clang-tidy-runner - IDF_BUILD_APPS_PROJ: 2818 # fuhanxi/idf-build-apps + IDF_BUILD_APPS_PROJ: 2818 # espressif/idf-build-apps # Docker images BOT_DOCKER_IMAGE_TAG: ":latest" - ESP_IDF_DOC_ENV_IMAGE: "$CI_DOCKER_REGISTRY/esp-idf-doc-env-v5.0:2-3" - ESP_ENV_IMAGE: "$CI_DOCKER_REGISTRY/esp-env-v5.0:2" - AFL_FUZZER_TEST_IMAGE: "$CI_DOCKER_REGISTRY/afl-fuzzer-test-v5.0:2-1" - CLANG_STATIC_ANALYSIS_IMAGE: "${CI_DOCKER_REGISTRY}/clang-static-analysis-v5.0:2-1" - TARGET_TEST_ENV_IMAGE: "$CI_DOCKER_REGISTRY/target-test-env-v5.0:2" - QEMU_IMAGE: "${CI_DOCKER_REGISTRY}/qemu-v5.0:2-20220802" + ESP_ENV_IMAGE: "$CI_DOCKER_REGISTRY/esp-env-v5.1:1" + AFL_FUZZER_TEST_IMAGE: "$CI_DOCKER_REGISTRY/afl-fuzzer-test-v5.1:1-1" + CLANG_STATIC_ANALYSIS_IMAGE: "${CI_DOCKER_REGISTRY}/clang-static-analysis-v5.1:1-1" + ESP_IDF_DOC_ENV_IMAGE: "$CI_DOCKER_REGISTRY/esp-idf-doc-env-v5.1:1-1" + QEMU_IMAGE: "${CI_DOCKER_REGISTRY}/qemu-v5.1:1-20220802" + TARGET_TEST_ENV_IMAGE: "$CI_DOCKER_REGISTRY/target-test-env-v5.1:1" SONARQUBE_SCANNER_IMAGE: "${CI_DOCKER_REGISTRY}/sonarqube-scanner:3" - LINUX_SHELL_IMAGE: "${CI_DOCKER_REGISTRY}/linux-shells-v5.0:2" + + PRE_COMMIT_IMAGE: "$CI_DOCKER_REGISTRY/esp-idf-pre-commit:1" # target test config file, used by assign test job CI_TARGET_TEST_CONFIG_FILE: "$CI_PROJECT_DIR/.gitlab/ci/target-test.yml" # target test repo parameters TEST_ENV_CONFIG_REPO: "https://gitlab-ci-token:${BOT_TOKEN}@${CI_SERVER_HOST}:${CI_SERVER_PORT}/qa/ci-test-runner-configs.git" - CI_AUTO_TEST_SCRIPT_REPO_URL: "https://gitlab-ci-token:${BOT_TOKEN}@${CI_SERVER_HOST}:${CI_SERVER_PORT}/qa/auto_test_script.git" - CI_AUTO_TEST_SCRIPT_REPO_BRANCH: "ci/v4.1" # cache python dependencies PIP_CACHE_DIR: "$CI_PROJECT_DIR/.cache/pip" @@ -112,140 +111,101 @@ cache: - .cache/submodule_archives policy: pull -.setup_tools_unless_target_test: &setup_tools_unless_target_test | +.common_before_scripts: &common-before_scripts | + source tools/ci/utils.sh + is_based_on_commits $REQUIRED_ANCESTOR_COMMITS + if [[ -n "$IDF_DONT_USE_MIRRORS" ]]; then - export IDF_MIRROR_PREFIX_MAP= - fi - if [[ "$SETUP_TOOLS" == "1" || "$CI_JOB_STAGE" != "target_test" ]]; then - tools/idf_tools.py --non-interactive install ${SETUP_TOOLS_LIST:-} && eval "$(tools/idf_tools.py --non-interactive export)" || exit 1 - if [[ ! -z "$OOCD_DISTRO_URL" && "$CI_JOB_STAGE" == "target_test" ]]; then - echo "Using custom OpenOCD from ${OOCD_DISTRO_URL}" - wget $OOCD_DISTRO_URL - ARCH_NAME=$(basename $OOCD_DISTRO_URL) - tar -x -f $ARCH_NAME - export OPENOCD_SCRIPTS=$PWD/openocd-esp32/share/openocd/scripts - export PATH=$PWD/openocd-esp32/bin:$PATH - fi + export IDF_MIRROR_PREFIX_MAP= fi -.download_test_python_contraint_file: &download_test_python_contraint_file | + if echo "$CI_MERGE_REQUEST_LABELS" | egrep "^([^,\n\r]+,)*include_nightly_run(,[^,\n\r]+)*$"; then + export INCLUDE_NIGHTLY_RUN="1" + fi + + # configure cmake related flags + source tools/ci/configure_ci_environment.sh + + # add extra python packages + export PYTHONPATH="$IDF_PATH/tools:$IDF_PATH/tools/esp_app_trace:$IDF_PATH/components/partition_table:$IDF_PATH/tools/ci/python_packages:$PYTHONPATH" + +.setup_tools_and_idf_python_venv: &setup_tools_and_idf_python_venv | + # must use after setup_tools_except_target_test + # otherwise the export.sh won't work properly + + # download constraint file for dev if [[ -n "$CI_PYTHON_CONSTRAINT_BRANCH" ]]; then wget -O /tmp/constraint.txt --header="Authorization:Bearer ${ESPCI_TOKEN}" ${GITLAB_HTTP_SERVER}/api/v4/projects/2581/repository/files/${CI_PYTHON_CONSTRAINT_FILE}/raw?ref=${CI_PYTHON_CONSTRAINT_BRANCH} mkdir -p ~/.espressif mv /tmp/constraint.txt ~/.espressif/${CI_PYTHON_CONSTRAINT_FILE} fi -.download_test_python_tool: &download_test_python_tool | + # Mirror + if [[ -n "$IDF_DONT_USE_MIRRORS" ]]; then + export IDF_MIRROR_PREFIX_MAP= + fi + + # install latest python packages + # target test jobs + if [[ "${CI_JOB_STAGE}" == "target_test" ]]; then + # ttfw jobs + if ! echo "${CI_JOB_NAME}" | egrep ".+_pytest_.+"; then + run_cmd bash install.sh --enable-ci --enable-ttfw + else + run_cmd bash install.sh --enable-ci --enable-pytest + fi + elif [[ "${CI_JOB_STAGE}" == "build_doc" ]]; then + run_cmd bash install.sh --enable-ci --enable-docs + elif [[ "${CI_JOB_STAGE}" == "build" ]]; then + run_cmd bash install.sh --enable-ci --enable-pytest + else + run_cmd bash install.sh --enable-ci + fi + + source ./export.sh + + # Custom OpenOCD + if [[ ! -z "$OOCD_DISTRO_URL" && "$CI_JOB_STAGE" == "target_test" ]]; then + echo "Using custom OpenOCD from ${OOCD_DISTRO_URL}" + wget $OOCD_DISTRO_URL + ARCH_NAME=$(basename $OOCD_DISTRO_URL) + tar -x -f $ARCH_NAME + export OPENOCD_SCRIPTS=$PWD/openocd-esp32/share/openocd/scripts + export PATH=$PWD/openocd-esp32/bin:$PATH + fi + if [[ -n "$CI_PYTHON_TOOL_REPO" ]]; then git clone --quiet --depth=1 -b ${CI_PYTHON_TOOL_BRANCH} https://gitlab-ci-token:${ESPCI_TOKEN}@${GITLAB_HTTPS_HOST}/espressif/${CI_PYTHON_TOOL_REPO}.git pip install ./${CI_PYTHON_TOOL_REPO} rm -rf ${CI_PYTHON_TOOL_REPO} fi -.set_include_nightly_run: &set_include_nightly_run | - if echo "$CI_MERGE_REQUEST_LABELS" | egrep "^([^,\n\r]+,)*include_nightly_run(,[^,\n\r]+)*$"; then - export INCLUDE_NIGHTLY_RUN="1" - fi - before_script: - - source tools/ci/utils.sh - - is_based_on_commits $REQUIRED_ANCESTOR_COMMITS - - *set_include_nightly_run - - source tools/ci/setup_python.sh + - *common-before_scripts + - *setup_tools_and_idf_python_venv - add_gitlab_ssh_keys - - source tools/ci/configure_ci_environment.sh - - *setup_tools_unless_target_test - fetch_submodules - - *download_test_python_contraint_file - - $IDF_PATH/tools/idf_tools.py install-python-env - # install esptool globally, TODO: remove this, IDFCI-1207 - - pip install esptool -c ~/.espressif/${CI_PYTHON_CONSTRAINT_FILE} - - *download_test_python_tool - -# used for check scripts which we want to run unconditionally -.before_script_no_sync_submodule: - before_script: - - echo "Not setting up GitLab key, not fetching submodules" - - source tools/ci/utils.sh - - is_based_on_commits $REQUIRED_ANCESTOR_COMMITS - - *set_include_nightly_run - - source tools/ci/setup_python.sh - - source tools/ci/configure_ci_environment.sh - - *download_test_python_contraint_file - - $IDF_PATH/tools/idf_tools.py install-python-env .before_script_minimal: before_script: - - echo "Only load utils.sh" - - source tools/ci/utils.sh - - is_based_on_commits $REQUIRED_ANCESTOR_COMMITS - - *set_include_nightly_run - -.before_script_integration_test: - before_script: - # need to install esptool, needn't install idf python env - - source tools/ci/utils.sh - - is_based_on_commits $REQUIRED_ANCESTOR_COMMITS - - *set_include_nightly_run - - source tools/ci/setup_python.sh - - add_gitlab_ssh_keys - - fetch_submodules - # download the constraint file manually - - mkdir -p ~/.espressif - - wget -O ~/.espressif/${CI_PYTHON_CONSTRAINT_FILE} --header="Authorization:Bearer ${ESPCI_TOKEN}" ${GITLAB_HTTP_SERVER}/api/v4/projects/2581/repository/files/${CI_PYTHON_CONSTRAINT_FILE}/raw - - *download_test_python_contraint_file - # TODO: remove this, IDFCI-1207 - - pip install esptool -c ~/.espressif/${CI_PYTHON_CONSTRAINT_FILE} - - *download_test_python_tool + - *common-before_scripts .before_script_macos: before_script: - - source tools/ci/utils.sh - - is_based_on_commits $REQUIRED_ANCESTOR_COMMITS - - *set_include_nightly_run - - export IDF_TOOLS_PATH="${HOME}/.espressif_runner_${CI_RUNNER_ID}_${CI_CONCURRENT_ID}" - - *download_test_python_contraint_file - - $IDF_PATH/tools/idf_tools.py install-python-env + - *common-before_scripts # On macOS, these tools need to be installed + - export IDF_TOOLS_PATH="${HOME}/.espressif_runner_${CI_RUNNER_ID}_${CI_CONCURRENT_ID}" - $IDF_PATH/tools/idf_tools.py --non-interactive install cmake ninja # This adds tools (compilers) and the version-specific Python environment to PATH - - *setup_tools_unless_target_test - # Install packages required by CI scripts into IDF Python environment - - pip install -r $IDF_PATH/tools/requirements/requirements.ci.txt - - source tools/ci/configure_ci_environment.sh - # Part of tools/ci/setup_python.sh; we don't use pyenv on macOS, so can't run the rest of the script. - - export PYTHONPATH="$IDF_PATH/tools:$IDF_PATH/tools/ci/python_packages:$PYTHONPATH" + - *setup_tools_and_idf_python_venv - fetch_submodules -.before_script_pytest: - before_script: - - source tools/ci/utils.sh - - is_based_on_commits $REQUIRED_ANCESTOR_COMMITS - - *set_include_nightly_run - - source tools/ci/setup_python.sh - - add_gitlab_ssh_keys - - source tools/ci/configure_ci_environment.sh - - *setup_tools_unless_target_test - - fetch_submodules - - *download_test_python_contraint_file - # only need ci and pytest related packages, ttfw requirements would be mocked if not installed - - $IDF_PATH/tools/idf_tools.py install-python-env --features pytest,ci - - eval "$($IDF_PATH/tools/idf_tools.py export)" # use idf venv instead - .before_script_build_jobs: before_script: - - source tools/ci/utils.sh - - is_based_on_commits $REQUIRED_ANCESTOR_COMMITS - - *set_include_nightly_run - - source tools/ci/setup_python.sh + - *common-before_scripts + - *setup_tools_and_idf_python_venv - add_gitlab_ssh_keys - - source tools/ci/configure_ci_environment.sh - - *setup_tools_unless_target_test - fetch_submodules - - *download_test_python_contraint_file - # only need ci and pytest related packages, ttfw requirements would be mocked if not installed - - $IDF_PATH/tools/idf_tools.py install-python-env --features pytest,ci - - eval "$($IDF_PATH/tools/idf_tools.py export)" # use idf venv instead - export EXTRA_CFLAGS=${PEDANTIC_CFLAGS} - export EXTRA_CXXFLAGS=${PEDANTIC_CXXFLAGS} diff --git a/.gitlab/CODEOWNERS b/.gitlab/CODEOWNERS index a55dbf8495..694db59e1a 100644 --- a/.gitlab/CODEOWNERS +++ b/.gitlab/CODEOWNERS @@ -78,6 +78,7 @@ /components/driver/ @esp-idf-codeowners/peripherals /components/efuse/ @esp-idf-codeowners/system /components/esp_adc/ @esp-idf-codeowners/peripherals +/components/esp_app_format/ @esp-idf-codeowners/system @esp-idf-codeowners/app-utilities /components/esp_common/ @esp-idf-codeowners/system /components/esp_eth/ @esp-idf-codeowners/network /components/esp_event/ @esp-idf-codeowners/system @@ -96,7 +97,6 @@ /components/esp_psram/ @esp-idf-codeowners/peripherals @esp-idf-codeowners/system /components/esp_ringbuf/ @esp-idf-codeowners/system /components/esp_rom/ @esp-idf-codeowners/system @esp-idf-codeowners/bluetooth @esp-idf-codeowners/wifi -/components/esp_serial_slave_link/ @esp-idf-codeowners/peripherals /components/esp_system/ @esp-idf-codeowners/system /components/esp_timer/ @esp-idf-codeowners/system /components/esp-tls/ @esp-idf-codeowners/app-utilities @@ -197,6 +197,8 @@ /tools/test_apps/**/*.py @esp-idf-codeowners/ci @esp-idf-codeowners/tools +/tools/test_build_system/ @esp-idf-codeowners/tools @esp-idf-codeowners/build-config + /tools/unit-test-app/ @esp-idf-codeowners/system @esp-idf-codeowners/tools # sort-order-reset diff --git a/.gitlab/ci/README.md b/.gitlab/ci/README.md index 5c34d36fd6..8a8051e904 100644 --- a/.gitlab/ci/README.md +++ b/.gitlab/ci/README.md @@ -116,7 +116,7 @@ curl -X POST --header "PRIVATE-TOKEN: [YOUR PERSONAL ACCESS TOKEN]" [GITLAB_SERV ```yaml check_docs_lang_sync: extends: - - .pre_check_job_template + - .pre_check_template - .rules:build:docs script: - cd docs diff --git a/.gitlab/ci/assign-test.yml b/.gitlab/ci/assign-test.yml index 55cc6ca65c..fd616f929a 100644 --- a/.gitlab/ci/assign-test.yml +++ b/.gitlab/ci/assign-test.yml @@ -85,6 +85,8 @@ assign_integration_test: extends: - .assign_test_template - .rules:test:integration_test + - .before_script_minimal + image: ${CI_INTEGRATION_TEST_ENV_IMAGE} needs: - build_ssc_esp32 - build_ssc_esp32c3 @@ -98,12 +100,13 @@ assign_integration_test: INTEGRATION_TEST_CASE_PATH: "${CI_PROJECT_DIR}/auto_test_script/TestCaseFiles" ASSIGN_TEST_CASE_SCRIPT: "${CI_PROJECT_DIR}/auto_test_script/bin/CIAssignTestCases.py" PYTHONPATH: ${CI_PROJECT_DIR}/auto_test_script/packages - PYTHON_VER: 3.7.7 + GIT_LFS_SKIP_SMUDGE: 1 script: + - add_gitlab_ssh_keys # clone test script to assign tests - # can not retry if downing git lfs files failed, so using empty_branch first. - - retry_failed git clone ${CI_AUTO_TEST_SCRIPT_REPO_URL} -b empty_branch - - retry_failed git -C auto_test_script checkout -f ${CI_AUTO_TEST_SCRIPT_REPO_BRANCH} - - python $CHECKOUT_REF_SCRIPT auto_test_script auto_test_script --customized_only + - retry_failed git clone ${CI_AUTO_TEST_SCRIPT_REPO_URL} auto_test_script + - python $CHECKOUT_REF_SCRIPT auto_test_script auto_test_script + - cd auto_test_script + - ./tools/ci/setup_idfci.sh # assign integration test cases - python ${ASSIGN_TEST_CASE_SCRIPT} -t ${INTEGRATION_TEST_CASE_PATH} -c $CI_TARGET_TEST_CONFIG_FILE -b ${BUILD_DIR} -o $TEST_DIR/test_configs diff --git a/.gitlab/ci/build.yml b/.gitlab/ci/build.yml index 80b3ae9fec..c47cb5bad0 100644 --- a/.gitlab/ci/build.yml +++ b/.gitlab/ci/build.yml @@ -4,7 +4,6 @@ tags: - build variables: - SIZE_INFO_LOCATION: "$CI_PROJECT_DIR/size_info.txt" # Enable ccache for all build jobs. See configure_ci_environment.sh for more ccache related settings. IDF_CCACHE_ENABLE: "1" after_script: @@ -12,35 +11,103 @@ - test "$CI_CCACHE_STATS" == 1 && test -n "$(which ccache)" && ccache --show-stats || true dependencies: [] -.build_pytest_template: +.build_cmake_template: extends: - .build_template - .before_script_build_jobs - dependencies: # set dependencies to null to avoid missing artifacts issue + dependencies: # set dependencies to null to avoid missing artifacts issue needs: - job: fast_template_app artifacts: false + tags: + - build + # build only on shiny servers since shiny storage server is at the same location + - shiny artifacts: paths: - "**/build*/size.json" - "**/build*/build_log.txt" - "**/build*/*.bin" + # upload to s3 server to save the artifacts size + # - "**/build*/*.map" + # ttfw tests require elf files - "**/build*/*.elf" - - "**/build*/*.map" + - "**/build*/flasher_args.json" + - "**/build*/flash_project_args" + - "**/build*/config/sdkconfig.json" + # ttfw tests require sdkconfig file + - "**/build*/sdkconfig" + - "**/build*/bootloader/*.bin" + - "**/build*/partition_table/*.bin" + - list_job_*.json + - size_info.txt + # unit test specific + - components/idf_test/unit_test/*.yml + when: always + expire_in: 4 days + after_script: + # Show ccache statistics if enabled globally + - test "$CI_CCACHE_STATS" == 1 && test -n "$(which ccache)" && ccache --show-stats || true + # upload the binary files to s3 server + - echo -e "\e[0Ksection_start:`date +%s`:upload_binaries_to_s3_server[collapsed=true]\r\e[0KUploading binaries to s3 Server" + - shopt -s globstar + # use || true to bypass the no-file error + - zip ${CI_JOB_ID}.zip **/build*/*.bin || true + - zip ${CI_JOB_ID}.zip **/build*/*.elf || true + - zip ${CI_JOB_ID}.zip **/build*/*.map || true + - zip ${CI_JOB_ID}.zip **/build*/flasher_args.json || true + - zip ${CI_JOB_ID}.zip **/build*/flash_project_args || true + - zip ${CI_JOB_ID}.zip **/build*/config/sdkconfig.json || true + - zip ${CI_JOB_ID}.zip **/build*/sdkconfig || true + - zip ${CI_JOB_ID}.zip **/build*/bootloader/*.bin || true + - zip ${CI_JOB_ID}.zip **/build*/partition_table/*.bin || true + - mc alias set shiny-s3 ${SHINY_S3_SERVER} ${SHINY_S3_ACCESS_KEY} ${SHINY_S3_SECRET_KEY} + - mc cp ${CI_JOB_ID}.zip shiny-s3/idf-artifacts/${CI_PIPELINE_ID}/${CI_JOB_ID}.zip + - echo -e "\e[0Ksection_end:`date +%s`:upload_binaries_to_s3_server\r\e[0K" + - echo "Please download the full binary files (including *.elf and *.map files) from the following share link" + # would be clean up after 4 days + - mc share download shiny-s3/idf-artifacts/${CI_PIPELINE_ID}/${CI_JOB_ID}.zip --expire=96h + script: + # CI specific options start from "--collect-size-info xxx". could ignore when running locally + - run_cmd python tools/ci/ci_build_apps.py $TEST_DIR -v + -t $IDF_TARGET + --copy-sdkconfig + --collect-size-info size_info.txt + --collect-app-info list_job_${CI_NODE_INDEX:-1}.json + --parallel-count ${CI_NODE_TOTAL:-1} + --parallel-index ${CI_NODE_INDEX:-1} + --extra-preserve-dirs + examples/bluetooth/esp_ble_mesh/ble_mesh_console + examples/bluetooth/hci/controller_hci_uart_esp32 + examples/wifi/iperf + +.build_pytest_template: + extends: + - .build_cmake_template + - .before_script_build_jobs + artifacts: + paths: + - "**/build*/size.json" + - "**/build*/build_log.txt" + - "**/build*/*.bin" + # upload to s3 server to save the artifacts size + # - "**/build*/*.map" + # - "**/build*/*.elf" - "**/build*/flasher_args.json" - "**/build*/flash_project_args" - "**/build*/config/sdkconfig.json" - "**/build*/bootloader/*.bin" - "**/build*/partition_table/*.bin" - - $SIZE_INFO_LOCATION + - list_job_*.json + - size_info.txt when: always - expire_in: 3 days + expire_in: 4 days script: # CI specific options start from "--collect-size-info xxx". could ignore when running locally - run_cmd python tools/ci/ci_build_apps.py $TEST_DIR -v -t $IDF_TARGET --pytest-apps - --collect-size-info $SIZE_INFO_LOCATION + --collect-size-info size_info.txt --parallel-count ${CI_NODE_TOTAL:-1} --parallel-index ${CI_NODE_INDEX:-1} @@ -48,7 +115,7 @@ build_pytest_examples_esp32: extends: - .build_pytest_template - .rules:build:example_test-esp32 - parallel: 3 + parallel: 4 variables: IDF_TARGET: esp32 TEST_DIR: examples @@ -66,7 +133,7 @@ build_pytest_examples_esp32s3: extends: - .build_pytest_template - .rules:build:example_test-esp32s3 - parallel: 3 + parallel: 4 variables: IDF_TARGET: esp32s3 TEST_DIR: examples @@ -88,6 +155,14 @@ build_pytest_examples_esp32c2: IDF_TARGET: esp32c2 TEST_DIR: examples +build_pytest_examples_esp32h2: + extends: + - .build_pytest_template + - .rules:build:example_test-esp32h2 + variables: + IDF_TARGET: esp32h2 + TEST_DIR: examples + build_pytest_components_esp32: extends: - .build_pytest_template @@ -101,6 +176,7 @@ build_pytest_components_esp32s2: extends: - .build_pytest_template - .rules:build:component_ut-esp32s2 + parallel: 2 variables: IDF_TARGET: esp32s2 TEST_DIR: components @@ -109,6 +185,7 @@ build_pytest_components_esp32s3: extends: - .build_pytest_template - .rules:build:component_ut-esp32s3 + parallel: 2 variables: IDF_TARGET: esp32s3 TEST_DIR: components @@ -117,6 +194,7 @@ build_pytest_components_esp32c3: extends: - .build_pytest_template - .rules:build:component_ut-esp32c3 + parallel: 2 variables: IDF_TARGET: esp32c3 TEST_DIR: components @@ -133,19 +211,43 @@ build_non_test_components_apps: extends: - .build_cmake_template - .rules:build:component_ut + parallel: 2 script: - set_component_ut_vars # CI specific options start from "--collect-size-info xxx". could ignore when running locally - run_cmd python tools/ci/ci_build_apps.py $COMPONENT_UT_DIRS -v -t all - --collect-size-info $SIZE_INFO_LOCATION + --collect-size-info size_info.txt --collect-app-info list_job_${CI_NODE_INDEX:-1}.json --parallel-count ${CI_NODE_TOTAL:-1} --parallel-index ${CI_NODE_INDEX:-1} +.build_pytest_test_apps_template: + extends: .build_pytest_template + artifacts: + paths: + - "**/build*/size.json" + - "**/build*/build_log.txt" + - "**/build*/*.bin" + # upload to s3 server to save the artifacts size + # - "**/build*/*.map" + # pytest test apps requires elf files for coredump tests + - "**/build*/*.elf" + - "**/build*/flasher_args.json" + - "**/build*/flash_project_args" + - "**/build*/config/sdkconfig.json" + - "**/build*/bootloader/*.elf" + - "**/build*/bootloader/*.bin" + - "**/build*/partition_table/*.bin" + - "**/build*/project_description.json" + - list_job_*.json + - size_info.txt + when: always + expire_in: 4 days + build_pytest_test_apps_esp32: extends: - - .build_pytest_template + - .build_pytest_test_apps_template - .rules:build:custom_test-esp32 variables: IDF_TARGET: esp32 @@ -153,7 +255,7 @@ build_pytest_test_apps_esp32: build_pytest_test_apps_esp32s2: extends: - - .build_pytest_template + - .build_pytest_test_apps_template - .rules:build:custom_test-esp32s2 variables: IDF_TARGET: esp32s2 @@ -161,7 +263,7 @@ build_pytest_test_apps_esp32s2: build_pytest_test_apps_esp32s3: extends: - - .build_pytest_template + - .build_pytest_test_apps_template - .rules:build:custom_test-esp32s3 variables: IDF_TARGET: esp32s3 @@ -169,7 +271,7 @@ build_pytest_test_apps_esp32s3: build_pytest_test_apps_esp32c3: extends: - - .build_pytest_template + - .build_pytest_test_apps_template - .rules:build:custom_test-esp32c3 variables: IDF_TARGET: esp32c3 @@ -177,7 +279,7 @@ build_pytest_test_apps_esp32c3: build_pytest_test_apps_esp32c2: extends: - - .build_pytest_template + - .build_pytest_test_apps_template - .rules:build:custom_test-esp32c2 variables: IDF_TARGET: esp32c2 @@ -268,19 +370,17 @@ build_ssc_esp32s3: .build_esp_idf_tests_cmake_template: extends: - - .build_template + - .build_cmake_template - .before_script_build_jobs - dependencies: # set dependencies to null to avoid missing artifacts issue - needs: - - job: fast_template_app - artifacts: false artifacts: paths: - "**/build*/size.json" - "**/build*/build_log.txt" - "**/build*/*.bin" + # upload to s3 server to save the artifacts size + # - "**/build*/*.map" + # ttfw tests require elf files - "**/build*/*.elf" - - "**/build*/*.map" - "**/build*/flasher_args.json" - "**/build*/flash_project_args" - "**/build*/config/sdkconfig.json" @@ -288,12 +388,10 @@ build_ssc_esp32s3: - "**/build*/bootloader/*.bin" - "**/build*/partition_table/*.bin" - list_job_*.json - - $SIZE_INFO_LOCATION + - size_info.txt - components/idf_test/unit_test/*.yml when: always expire_in: 4 days - variables: - LDGEN_CHECK_MAPPING: 1 script: # CI specific options start from "--collect-size-info xxx". could ignore when running locally - run_cmd python tools/ci/ci_build_apps.py tools/unit-test-app -v @@ -301,7 +399,7 @@ build_ssc_esp32s3: --config "configs/*=" --copy-sdkconfig --preserve-all - --collect-size-info $SIZE_INFO_LOCATION + --collect-size-info size_info.txt --collect-app-info list_job_${CI_NODE_INDEX:-1}.json --parallel-count ${CI_NODE_TOTAL:-1} --parallel-index ${CI_NODE_INDEX:-1} @@ -344,52 +442,11 @@ build_esp_idf_tests_cmake_esp32c3: variables: IDF_TARGET: esp32c3 -.build_cmake_template: - extends: - - .build_template - - .before_script_build_jobs - dependencies: # set dependencies to null to avoid missing artifacts issue - needs: - - job: fast_template_app - artifacts: false - variables: - LDGEN_CHECK_MAPPING: 1 - artifacts: - paths: - - "**/build*/size.json" - - "**/build*/build_log.txt" - - "**/build*/*.bin" - - "**/build*/*.elf" - - "**/build*/*.map" - - "**/build*/flasher_args.json" - - "**/build*/flash_project_args" - - "**/build*/config/sdkconfig.json" - - "**/build*/sdkconfig" - - "**/build*/bootloader/*.bin" - - "**/build*/partition_table/*.bin" - - list_job_*.json - - $SIZE_INFO_LOCATION - when: always - expire_in: 4 days - script: - # CI specific options start from "--collect-size-info xxx". could ignore when running locally - - run_cmd python tools/ci/ci_build_apps.py $TEST_DIR -v - -t $IDF_TARGET - --copy-sdkconfig - --collect-size-info $SIZE_INFO_LOCATION - --collect-app-info list_job_${CI_NODE_INDEX:-1}.json - --parallel-count ${CI_NODE_TOTAL:-1} - --parallel-index ${CI_NODE_INDEX:-1} - --extra-preserve-dirs - examples/bluetooth/esp_ble_mesh/ble_mesh_console - examples/bluetooth/hci/controller_hci_uart_esp32 - examples/wifi/iperf - build_examples_cmake_esp32: extends: - .build_cmake_template - .rules:build:example_test-esp32 - parallel: 12 + parallel: 9 variables: IDF_TARGET: esp32 TEST_DIR: examples @@ -398,7 +455,7 @@ build_examples_cmake_esp32s2: extends: - .build_cmake_template - .rules:build:example_test-esp32s2 - parallel: 8 + parallel: 6 variables: IDF_TARGET: esp32s2 TEST_DIR: examples @@ -407,7 +464,7 @@ build_examples_cmake_esp32s3: extends: - .build_cmake_template - .rules:build:example_test-esp32s3 - parallel: 8 + parallel: 7 variables: IDF_TARGET: esp32s3 TEST_DIR: examples @@ -416,7 +473,7 @@ build_examples_cmake_esp32c2: extends: - .build_cmake_template - .rules:build:example_test-esp32c2 - parallel: 8 + parallel: 4 variables: IDF_TARGET: esp32c2 TEST_DIR: examples @@ -425,7 +482,7 @@ build_examples_cmake_esp32c3: extends: - .build_cmake_template - .rules:build:example_test-esp32c3 - parallel: 8 + parallel: 6 variables: IDF_TARGET: esp32c3 TEST_DIR: examples @@ -517,6 +574,21 @@ test_build_system_spaces: variables: SHELL_TEST_SCRIPT: test_build_system_spaces.py +pytest_build_system: + extends: .test_build_system_template + artifacts: + paths: + - XUNIT_RESULT.xml + - test_build_system + when: always + expire_in: 2 days + reports: + junit: XUNIT_RESULT.xml + script: + - ${IDF_PATH}/tools/ci/test_configure_ci_environment.sh + - cd ${IDF_PATH}/tools/test_build_system + - pytest --work-dir ${CI_PROJECT_DIR}/test_build_system --junitxml=${CI_PROJECT_DIR}/XUNIT_RESULT.xml + build_docker: extends: - .before_script_minimal diff --git a/.gitlab/ci/default-build-test-rules.yml b/.gitlab/ci/default-build-test-rules.yml new file mode 100644 index 0000000000..bc9930d069 --- /dev/null +++ b/.gitlab/ci/default-build-test-rules.yml @@ -0,0 +1,21 @@ +# this file support two keywords: +# - extra_default_build_targets: +# besides of the SUPPORTED_TARGETS in IDF, +# enable build for the specified targets by default as well. +# - bypass_check_test_targets: +# suppress the check_build_test_rules check-test-script warnings for the specified targets +# +# This file should ONLY be used during bringup. Should be reset to empty after the bringup process +# +# Take esp32c6 as an example: +# +#extra_default_build_targets: +# - esp32c6 +# +#bypass_check_test_targets: +# - esp32c6 +# +# These lines would +# - enable the README.md check for esp32c6. Don't forget to add the build jobs in .gitlab/ci/build.yml +# - disable the test script check with the manifest file. +# diff --git a/.gitlab/ci/dependencies/README.md b/.gitlab/ci/dependencies/README.md index c20c3373fe..db7afc5016 100644 --- a/.gitlab/ci/dependencies/README.md +++ b/.gitlab/ci/dependencies/README.md @@ -97,4 +97,4 @@ There are a few extra dependencies while generating the dependency tree graph, p ### CLI usage -`python generate_rules.py --graph OUTPUT_PATH` +`python $IDF_PATH/tools/ci/generate_rules.py --graph OUTPUT_PATH` diff --git a/.gitlab/ci/dependencies/dependencies.yml b/.gitlab/ci/dependencies/dependencies.yml index 15adcae2d4..eb8717dd59 100644 --- a/.gitlab/ci/dependencies/dependencies.yml +++ b/.gitlab/ci/dependencies/dependencies.yml @@ -21,6 +21,7 @@ patterns: - build_components - build_system + - downloadable-tools included_in: - build:target_test @@ -33,6 +34,9 @@ - docker patterns: - docker + - submodule + - build_system + - downloadable-tools "build:windows": labels: @@ -50,6 +54,7 @@ patterns: - build_system - macos + - downloadable-tools # --------------- # Build Test Jobs @@ -64,6 +69,7 @@ - build_components - build_system - build_target_test + - downloadable-tools included_in: - "build:{0}" - build:target_test @@ -77,45 +83,6 @@ build:integration_test: included_in: - build:target_test -# ------------- -# Special Cases -# ------------- -"build:{0}-esp32s3": - matrix: - - *target_test - labels: - - build - - "{0}" - - target_test - patterns: - - build_components - - build_system - - build_target_test - - "{0}" - - "build-{0}" - included_in: - - "build:{0}" - - build:target_test - -"build:component_ut-esp32s3": - matrix: - - *target_test - labels: - - build - - component_ut - - unit_test - - target_test - patterns: - - build_components - - build_system - - build_target_test - - component_ut - - unit_test - - build-component_ut - - build-unit_test - included_in: - - "build:{0}" - - build:target_test #################### # Target Test Jobs # @@ -167,6 +134,9 @@ build:integration_test: - wifi # example_test_002, example_test*wifi* - ethernet # example_test*ethernet* - sdio # UT_044, UT_045 + - usb # USB Device & Host tests + - spi_multi # UT_C2_SPI_DUAL + - adc # component_ut_pytest_esp32x_adc patterns: - "{0}-{1}-{2}" - "{0}-{2}" @@ -193,6 +163,19 @@ build:integration_test: - "build:example_test" - build:target_test +# For i154 runners +"test:example_test-i154": + patterns: + - "target_test-i154" + labels: + - target_test + - example_test + included_in: + - "build:example_test-esp32h2" + - "build:example_test-esp32s3" + - "build:example_test" + - build:target_test + # due to the lack of runners, c2 tests will only be triggered by label "test:{0}-esp32c2": matrix: @@ -214,27 +197,6 @@ build:integration_test: - "build:component_ut-esp32c2" - build:target_test -# due to the lack of runners, s3 tests will only be triggered by label -"test:{0}-esp32s3": - matrix: - - *target_test - labels: - - "{0}_esp32s3" - included_in: - - "build:{0}" - - "build:{0}-esp32s3" - - build:target_test - -# overwrite the esp32s3 component ut again -"test:component_ut-esp32s3": # component_ut will trigger by unit_test as well, since now we have 2 kinds of UT - labels: - - "component_ut_esp32s3" - - "unit_test_esp32s3" - included_in: - - build:component_ut - - "build:component_ut-esp32s3" - - build:target_test - "test:integration_test": labels: - integration_test diff --git a/.gitlab/ci/deploy.yml b/.gitlab/ci/deploy.yml index bd0eec0678..0136f5f582 100644 --- a/.gitlab/ci/deploy.yml +++ b/.gitlab/ci/deploy.yml @@ -1,5 +1,4 @@ .deploy_job_template: - extends: .before_script_no_sync_submodule stage: deploy image: $ESP_ENV_IMAGE tags: diff --git a/.gitlab/ci/docs.yml b/.gitlab/ci/docs.yml index c781c77a52..82eea28027 100644 --- a/.gitlab/ci/docs.yml +++ b/.gitlab/ci/docs.yml @@ -6,6 +6,8 @@ - "components/**/CMakeList.txt" - "components/**/sdkconfig*" - "tools/kconfig_new/**/*" + - "tools/tools.json" + - "tools/idf_tools.py" - "CONTRIBUTING.rst" .patterns-docs-preview: &patterns-docs-preview @@ -41,7 +43,7 @@ # stage: pre_check check_readme_links: extends: - - .pre_check_job_template + - .pre_check_template tags: ["build", "amd64", "internet"] allow_failure: true script: @@ -49,7 +51,7 @@ check_readme_links: check_docs_lang_sync: extends: - - .pre_check_job_template + - .pre_check_template - .doc-rules:build:docs script: - cd docs @@ -62,7 +64,6 @@ check_docs_lang_sync: dependencies: [] script: - cd docs - - pip install -U -r $IDF_PATH/tools/requirements/requirements.docs.txt - build-docs -t $DOCTGT -bs $DOC_BUILDERS -l $DOCLANG build parallel: matrix: @@ -72,11 +73,10 @@ check_docs_lang_sync: check_docs_gh_links: image: $ESP_IDF_DOC_ENV_IMAGE extends: - - .pre_check_job_template + - .pre_check_template - .doc-rules:build:docs script: - cd docs - - pip install -U -r $IDF_PATH/tools/requirements/requirements.docs.txt - build-docs gh-linkcheck # stage: build_doc @@ -148,8 +148,6 @@ build_docs_pdf: DOC_BUILDERS: "latex" .deploy_docs_template: - extends: - - .before_script_no_sync_submodule image: $ESP_IDF_DOC_ENV_IMAGE variables: DOCS_BUILD_DIR: "${IDF_PATH}/docs/_build/" @@ -161,7 +159,6 @@ build_docs_pdf: script: - add_doc_server_ssh_keys $DOCS_DEPLOY_PRIVATEKEY $DOCS_DEPLOY_SERVER $DOCS_DEPLOY_SERVER_USER - export GIT_VER=$(git describe --always ${PIPELINE_COMMIT_SHA} --) - - pip install -U -r $IDF_PATH/tools/requirements/requirements.docs.txt - deploy-docs # stage: test_deploy @@ -227,5 +224,4 @@ check_doc_links: allow_failure: true script: - cd docs - - pip install -U -r $IDF_PATH/tools/requirements/requirements.docs.txt - build-docs -t $DOCTGT -l $DOCLANG linkcheck diff --git a/.gitlab/ci/host-test.yml b/.gitlab/ci/host-test.yml index 9bc91765b6..50b5feecb5 100644 --- a/.gitlab/ci/host-test.yml +++ b/.gitlab/ci/host-test.yml @@ -125,9 +125,7 @@ test_lwip_dhcps_fuzzer_on_host: test_spiffs_on_host: extends: .host_test_template script: - - cd components/spiffs/test_spiffs_host/ - - make test - - cd ../test_spiffsgen + - cd components/spiffs/test_spiffsgen/ - ./test_spiffsgen.py test_fatfsgen_on_host: @@ -203,20 +201,29 @@ test_idf_py: script: - cd ${IDF_PATH}/tools/test_idf_py - ./test_idf_py.py + - ./test_hints.py +# Test for create virtualenv. It must be invoked from Python, not from virtualenv. +# Use docker image system python without any extra dependencies test_idf_tools: - extends: .host_test_template + extends: + - .host_test_template + - .before_script_minimal artifacts: when: on_failure paths: - tools/tools.new.json + - tools/test_idf_tools/test_python_env_logs.txt expire_in: 1 week + image: + name: $ESP_ENV_IMAGE + entrypoint: [""] # use system python3. no extra pip package installed script: - # Remove Xtensa and ULP toolchains from the PATH, tests will expect a clean environment - - export PATH=$(p=$(echo $PATH | tr ":" "\n" | grep -v "/root/.espressif/tools\|/opt/espressif" | tr "\n" ":"); echo ${p%:}) + # Tools must be downloaded for testing + - python3 ${IDF_PATH}/tools/idf_tools.py download - cd ${IDF_PATH}/tools/test_idf_tools - - ./test_idf_tools.py - # Test for create virtualenv. It must be invoked from Python, not from virtualenv. + - python3 -m pip install jsonschema + - python3 ./test_idf_tools.py - python3 ./test_idf_tools_python_env.py .test_efuse_table_on_host_template: @@ -268,7 +275,7 @@ test_espcoredump: expire_in: 1 week variables: IDF_COREDUMP_ELF_REPO: "https://gitlab-ci-token:${BOT_TOKEN}@${CI_SERVER_HOST}:${CI_SERVER_PORT}/idf/idf-coredump-elf.git" - IDF_COREDUMP_ELF_TAG: idf-20210915 + IDF_COREDUMP_ELF_TAG: idf-20220928 # install CMake version specified in tools.json SETUP_TOOLS_LIST: "all" script: @@ -316,8 +323,8 @@ test_mkuf2: - ./test_mkuf2.py test_autocomplete: - extends: .host_test_template - image: $LINUX_SHELL_IMAGE + extends: + - .host_test_template artifacts: when: on_failure paths: @@ -327,8 +334,8 @@ test_autocomplete: - ${IDF_PATH}/tools/ci/test_autocomplete.py test_detect_python: - extends: .host_test_template - image: $LINUX_SHELL_IMAGE + extends: + - .host_test_template script: - cd ${IDF_PATH} - shellcheck -s sh tools/detect_python.sh @@ -373,6 +380,15 @@ test_esp_event: - idf.py build - build/test_esp_event_host.elf +test_hello_world_linux_compatible_example: + extends: .host_test_template + script: + - cd ${IDF_PATH}/tools/test_apps/linux_compatible/hello_world_linux_compatible + - idf.py --preview set-target linux + - idf.py build + - timeout 15 build/hello_world.elf > test.log + - grep "Hello world!" test.log + test_esp_timer_cxx: extends: .host_test_template script: @@ -422,13 +438,21 @@ test_system_cxx: - idf.py build - build/test_system_cxx_host.elf -test_linux_example: +test_partition_api_host: extends: .host_test_template script: - - cd ${IDF_PATH}/examples/build_system/cmake/linux_host_app + - cd ${IDF_PATH}/components/spi_flash/host_test/partition_api_test - idf.py build - - timeout 5 ./build/linux_host_app.elf >test.log || true - - grep "Restarting" test.log + - timeout 5 ./build/partition_api_test.elf >test.log + - grep " 0 Failures" test.log + +test_spiffs_host: + extends: .host_test_template + script: + - cd ${IDF_PATH}/components/spiffs/host_test + - idf.py build + - timeout 5 ./build/host_test_spiffs.elf >test.log + - grep " 0 Failures" test.log test_gen_soc_caps_kconfig: extends: .host_test_template @@ -441,9 +465,17 @@ test_pytest_qemu: - .host_test_template - .before_script_build_jobs image: $QEMU_IMAGE + artifacts: + when: always + paths: + - XUNIT_RESULT.xml + - pytest_embedded_log/ + reports: + junit: XUNIT_RESULT.xml + expire_in: 1 week script: - run_cmd python tools/ci/ci_build_apps.py . -vv --target esp32 --pytest-apps -m qemu - - pytest --target esp32 -m qemu --embedded-services idf,qemu + - pytest --target esp32 -m qemu --embedded-services idf,qemu --junitxml=XUNIT_RESULT.xml diff --git a/.gitlab/ci/pre_check.yml b/.gitlab/ci/pre_check.yml index db724d6228..cb811ea57a 100644 --- a/.gitlab/ci/pre_check.yml +++ b/.gitlab/ci/pre_check.yml @@ -1,21 +1,15 @@ -.pre_check_base_template: +.pre_check_template: stage: pre_check image: $ESP_ENV_IMAGE tags: - host_test dependencies: [] -.pre_check_job_template: - extends: - - .pre_check_base_template - - .before_script_no_sync_submodule - .check_pre_commit_template: - extends: .pre_check_job_template - image: "$CI_DOCKER_REGISTRY/esp-idf-pre-commit:1" - before_script: - - source tools/ci/utils.sh - - export PYTHONPATH="$CI_PROJECT_DIR/tools:$CI_PROJECT_DIR/tools/ci/python_packages:$PYTHONPATH" + extends: + - .pre_check_template + - .before_script_minimal + image: $PRE_COMMIT_IMAGE check_pre_commit_master_release: extends: @@ -35,32 +29,20 @@ check_version: # Don't run this for feature/bugfix branches, so that it is possible to modify # esp_idf_version.h in a branch before tagging the next version. extends: - - .pre_check_job_template + - .pre_check_template - .rules:protected script: - export IDF_PATH=$PWD - tools/ci/check_idf_version.sh check_rom_api_header: - extends: .pre_check_job_template + extends: .pre_check_template script: - tools/ci/check_examples_rom_header.sh - tools/ci/check_api_violation.sh -check_python_style: - extends: - - .pre_check_base_template - - .rules:patterns:python-files - artifacts: - when: on_failure - paths: - - flake8_output.txt - expire_in: 1 week - script: - - python -m flake8 --config=$IDF_PATH/.flake8 --output-file=flake8_output.txt --tee --benchmark $IDF_PATH - test_check_kconfigs: - extends: .pre_check_job_template + extends: .pre_check_template artifacts: when: on_failure paths: @@ -75,7 +57,7 @@ test_check_kconfigs: - python ${IDF_PATH}/tools/ci/test_check_kconfigs.py check_blobs: - extends: .pre_check_base_template + extends: .pre_check_template tags: - build variables: @@ -90,7 +72,7 @@ check_blobs: - bash $IDF_PATH/tools/ci/check_blobs.sh check_fuzzer_compilation: - extends: .pre_check_base_template + extends: .pre_check_template image: $AFL_FUZZER_TEST_IMAGE script: - cd ${IDF_PATH}/components/lwip/test_afl_host @@ -100,7 +82,7 @@ check_fuzzer_compilation: check_public_headers: extends: - - .pre_check_base_template + - .pre_check_template - .rules:build tags: - build @@ -110,10 +92,11 @@ check_public_headers: - IDF_TARGET=esp32s3 python tools/ci/check_public_headers.py --jobs 4 --prefix xtensa-esp32s3-elf- - IDF_TARGET=esp32c3 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf- - IDF_TARGET=esp32c2 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf- + - IDF_TARGET=esp32c6 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf- check_chip_support_components: extends: - - .pre_check_base_template + - .pre_check_template - .rules:build tags: - build @@ -130,7 +113,7 @@ check_chip_support_components: check_esp_err_to_name: extends: - - .pre_check_base_template + - .pre_check_template - .rules:build tags: - build @@ -146,7 +129,7 @@ check_esp_err_to_name: check_esp_system: extends: - - .pre_check_base_template + - .pre_check_template - .rules:build tags: - build @@ -157,19 +140,19 @@ check_esp_system: # the version returned by 'git describe' check_version_tag: extends: - - .pre_check_job_template + - .pre_check_template - .rules:tag:release script: - (git cat-file -t $CI_COMMIT_REF_NAME | grep tag) || (echo "ESP-IDF versions must be annotated tags." && exit 1) check_artifacts_expire_time: - extends: .pre_check_job_template + extends: .pre_check_template script: # check if we have set expire time for all artifacts - python tools/ci/check_artifacts_expire_time.py check_commit_msg: - extends: .pre_check_job_template + extends: .pre_check_template script: - git status - git log -n10 --oneline ${PIPELINE_COMMIT_SHA} @@ -178,7 +161,9 @@ check_commit_msg: check_test_scripts_build_test_rules: extends: - - .pre_check_job_template + - .pre_check_template - .before_script_build_jobs script: + # required pytest related packages + - run_cmd bash install.sh --enable-pytest - python tools/ci/check_build_test_rules.py check-test-scripts examples/ tools/test_apps components diff --git a/.gitlab/ci/rules.yml b/.gitlab/ci/rules.yml index c356292c50..0900492745 100644 --- a/.gitlab/ci/rules.yml +++ b/.gitlab/ci/rules.yml @@ -42,14 +42,18 @@ - "components/**/*" - "examples/cxx/experimental/experimental_cpp_component/*" +.patterns-downloadable-tools: &patterns-downloadable-tools + - "tools/idf_tools.py" + - "tools/tools.json" + .patterns-build_system: &patterns-build_system - "tools/cmake/**/*" - "tools/kconfig_new/**/*" - - "tools/tools.json" - "tools/requirements.json" - "tools/ci/test_build_system*.sh" - "tools/ci/test_build_system*.py" - "tools/ci/ci_build_apps.py" + - "tools/test_build_system/**/*" .patterns-custom_test: &patterns-custom_test - "components/espcoredump/**/*" @@ -79,6 +83,14 @@ - "components/**/*" +.patterns-target_test-i154: &patterns-target_test-i154 + - "components/esp_netif/**/*" + - "components/esp_phy/**/*" + - "components/ieee802154/**/*" + - "components/lwip/**/*" + - "examples/common_components/iperf/**/*" + - "examples/openthread/**/*" + .patterns-integration_test: &patterns-integration_test - "tools/ci/python_packages/gitlab_api.py" - "tools/ci/integration_test/**/*" @@ -173,7 +185,6 @@ - "components/tinyusb/tinyusb" - "components/unity/unity" - "components/heap/tlsf" - - "examples/peripherals/secure_element/atecc608_ecdsa/components/esp-cryptoauthlib" - ".gitmodules" # for jobs: example_test*flash_encryption_wifi_high_traffic @@ -209,6 +220,7 @@ - "components/esp_wifi/**/*" - "components/esp_netif/**/*" - "components/lwip/**/*" + - "components/mbedtls/port/dynamic/*" # for cases with wifi_high_traffic marker - "examples/system/ota/**/*" @@ -221,6 +233,29 @@ - "components/driver/**/*" - "components/sdmmc/**/*" +# for jobs: example_test_pytest_esp32s3_usb_device and test_app_test_pytest_esp32s2_usb_host: +.patterns-example_test-usb: &patterns-example_test-usb + - "components/hal/usb*.c" + - "components/hal/esp32s*/include/hal/usb*.h" + - "components/tinyusb/**/**/*" + - "components/usb/**/*" + - "examples/peripherals/usb/host/**/**/**/*" + - "examples/peripherals/usb/device/**/**/*" + +# for job: unit_test-spi_multi which has only one runner +.patterns-unit_test-spi_multi: &patterns-unit_test-spi_multi + - "components/esp_serial_slave_link/**/*" + - "components/driver/**/*" + - "components/hal/**/*" + - "examples/peripherals/spi_slave*/**/*" + +# for jobs: component_ut_pytest_esp32x_adc: +.patterns-component_ut-adc: &patterns-component_ut-adc + - "components/esp_adc/**/*" + - "components/driver/**/*" + - "components/hal/**/*" + - "components/esp_hw_support/**/*" + - "components/efuse/**/*" ############## # if anchors # @@ -470,6 +505,8 @@ changes: *patterns-build_components - <<: *if-dev-push changes: *patterns-build_system + - <<: *if-dev-push + changes: *patterns-downloadable-tools .rules:build:component_ut: rules: @@ -500,7 +537,9 @@ - <<: *if-dev-push changes: *patterns-component_ut - <<: *if-dev-push - changes: *patterns-unit_test + changes: *patterns-component_ut-adc + - <<: *if-dev-push + changes: *patterns-downloadable-tools .rules:build:component_ut-esp32: rules: @@ -520,6 +559,10 @@ changes: *patterns-build_system - <<: *if-dev-push changes: *patterns-component_ut + - <<: *if-dev-push + changes: *patterns-component_ut-adc + - <<: *if-dev-push + changes: *patterns-downloadable-tools .rules:build:component_ut-esp32c2: rules: @@ -535,6 +578,10 @@ changes: *patterns-build_components - <<: *if-dev-push changes: *patterns-build_system + - <<: *if-dev-push + changes: *patterns-component_ut-adc + - <<: *if-dev-push + changes: *patterns-downloadable-tools .rules:build:component_ut-esp32c3: rules: @@ -553,24 +600,10 @@ changes: *patterns-build_system - <<: *if-dev-push changes: *patterns-component_ut - -.rules:build:component_ut-esp32h2: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build - - <<: *if-label-component_ut - - <<: *if-label-component_ut_esp32h2 - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32h2 - <<: *if-dev-push - changes: *patterns-build_components + changes: *patterns-component_ut-adc - <<: *if-dev-push - changes: *patterns-build_system - - <<: *if-dev-push - changes: *patterns-component_ut + changes: *patterns-downloadable-tools .rules:build:component_ut-esp32s2: rules: @@ -589,6 +622,10 @@ changes: *patterns-build_system - <<: *if-dev-push changes: *patterns-component_ut + - <<: *if-dev-push + changes: *patterns-component_ut-adc + - <<: *if-dev-push + changes: *patterns-downloadable-tools .rules:build:component_ut-esp32s3: rules: @@ -608,7 +645,9 @@ - <<: *if-dev-push changes: *patterns-component_ut - <<: *if-dev-push - changes: *patterns-unit_test + changes: *patterns-component_ut-adc + - <<: *if-dev-push + changes: *patterns-downloadable-tools .rules:build:custom_test: rules: @@ -631,6 +670,8 @@ changes: *patterns-build_system - <<: *if-dev-push changes: *patterns-custom_test + - <<: *if-dev-push + changes: *patterns-downloadable-tools .rules:build:custom_test-esp32: rules: @@ -648,6 +689,8 @@ changes: *patterns-build_system - <<: *if-dev-push changes: *patterns-custom_test + - <<: *if-dev-push + changes: *patterns-downloadable-tools .rules:build:custom_test-esp32c2: rules: @@ -662,6 +705,8 @@ changes: *patterns-build_components - <<: *if-dev-push changes: *patterns-build_system + - <<: *if-dev-push + changes: *patterns-downloadable-tools .rules:build:custom_test-esp32c3: rules: @@ -678,22 +723,8 @@ changes: *patterns-build_system - <<: *if-dev-push changes: *patterns-custom_test - -.rules:build:custom_test-esp32h2: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32h2 - - <<: *if-label-target_test - <<: *if-dev-push - changes: *patterns-build_components - - <<: *if-dev-push - changes: *patterns-build_system - - <<: *if-dev-push - changes: *patterns-custom_test + changes: *patterns-downloadable-tools .rules:build:custom_test-esp32s2: rules: @@ -710,6 +741,8 @@ changes: *patterns-build_system - <<: *if-dev-push changes: *patterns-custom_test + - <<: *if-dev-push + changes: *patterns-downloadable-tools .rules:build:custom_test-esp32s3: rules: @@ -726,6 +759,8 @@ changes: *patterns-build_system - <<: *if-dev-push changes: *patterns-custom_test + - <<: *if-dev-push + changes: *patterns-downloadable-tools .rules:build:docker: rules: @@ -734,8 +769,14 @@ - <<: *if-protected - <<: *if-label-build - <<: *if-label-docker + - <<: *if-dev-push + changes: *patterns-build_system - <<: *if-dev-push changes: *patterns-docker + - <<: *if-dev-push + changes: *patterns-downloadable-tools + - <<: *if-dev-push + changes: *patterns-submodule .rules:build:example_test: rules: @@ -759,14 +800,20 @@ changes: *patterns-build_components - <<: *if-dev-push changes: *patterns-build_system + - <<: *if-dev-push + changes: *patterns-downloadable-tools - <<: *if-dev-push changes: *patterns-example_test - <<: *if-dev-push changes: *patterns-example_test-bt - <<: *if-dev-push changes: *patterns-example_test-ethernet + - <<: *if-dev-push + changes: *patterns-example_test-usb - <<: *if-dev-push changes: *patterns-example_test-wifi + - <<: *if-dev-push + changes: *patterns-target_test-i154 .rules:build:example_test-esp32: rules: @@ -785,12 +832,16 @@ changes: *patterns-build_components - <<: *if-dev-push changes: *patterns-build_system + - <<: *if-dev-push + changes: *patterns-downloadable-tools - <<: *if-dev-push changes: *patterns-example_test - <<: *if-dev-push changes: *patterns-example_test-bt - <<: *if-dev-push changes: *patterns-example_test-ethernet + - <<: *if-dev-push + changes: *patterns-example_test-usb - <<: *if-dev-push changes: *patterns-example_test-wifi @@ -807,10 +858,14 @@ changes: *patterns-build_components - <<: *if-dev-push changes: *patterns-build_system + - <<: *if-dev-push + changes: *patterns-downloadable-tools - <<: *if-dev-push changes: *patterns-example_test-bt - <<: *if-dev-push changes: *patterns-example_test-ethernet + - <<: *if-dev-push + changes: *patterns-example_test-usb - <<: *if-dev-push changes: *patterns-example_test-wifi @@ -830,12 +885,16 @@ changes: *patterns-build_components - <<: *if-dev-push changes: *patterns-build_system + - <<: *if-dev-push + changes: *patterns-downloadable-tools - <<: *if-dev-push changes: *patterns-example_test - <<: *if-dev-push changes: *patterns-example_test-bt - <<: *if-dev-push changes: *patterns-example_test-ethernet + - <<: *if-dev-push + changes: *patterns-example_test-usb - <<: *if-dev-push changes: *patterns-example_test-wifi @@ -854,14 +913,20 @@ changes: *patterns-build_components - <<: *if-dev-push changes: *patterns-build_system + - <<: *if-dev-push + changes: *patterns-downloadable-tools - <<: *if-dev-push changes: *patterns-example_test - <<: *if-dev-push changes: *patterns-example_test-bt - <<: *if-dev-push changes: *patterns-example_test-ethernet + - <<: *if-dev-push + changes: *patterns-example_test-usb - <<: *if-dev-push changes: *patterns-example_test-wifi + - <<: *if-dev-push + changes: *patterns-target_test-i154 .rules:build:example_test-esp32s2: rules: @@ -878,12 +943,16 @@ changes: *patterns-build_components - <<: *if-dev-push changes: *patterns-build_system + - <<: *if-dev-push + changes: *patterns-downloadable-tools - <<: *if-dev-push changes: *patterns-example_test - <<: *if-dev-push changes: *patterns-example_test-bt - <<: *if-dev-push changes: *patterns-example_test-ethernet + - <<: *if-dev-push + changes: *patterns-example_test-usb - <<: *if-dev-push changes: *patterns-example_test-wifi @@ -902,14 +971,20 @@ changes: *patterns-build_components - <<: *if-dev-push changes: *patterns-build_system + - <<: *if-dev-push + changes: *patterns-downloadable-tools - <<: *if-dev-push changes: *patterns-example_test - <<: *if-dev-push changes: *patterns-example_test-bt - <<: *if-dev-push changes: *patterns-example_test-ethernet + - <<: *if-dev-push + changes: *patterns-example_test-usb - <<: *if-dev-push changes: *patterns-example_test-wifi + - <<: *if-dev-push + changes: *patterns-target_test-i154 .rules:build:integration_test: rules: @@ -936,6 +1011,8 @@ - <<: *if-label-macos_test - <<: *if-dev-push changes: *patterns-build_system + - <<: *if-dev-push + changes: *patterns-downloadable-tools .rules:build:target_test: rules: @@ -985,22 +1062,32 @@ changes: *patterns-build_system - <<: *if-dev-push changes: *patterns-component_ut + - <<: *if-dev-push + changes: *patterns-component_ut-adc - <<: *if-dev-push changes: *patterns-custom_test + - <<: *if-dev-push + changes: *patterns-downloadable-tools - <<: *if-dev-push changes: *patterns-example_test - <<: *if-dev-push changes: *patterns-example_test-bt - <<: *if-dev-push changes: *patterns-example_test-ethernet + - <<: *if-dev-push + changes: *patterns-example_test-usb - <<: *if-dev-push changes: *patterns-example_test-wifi - <<: *if-dev-push changes: *patterns-integration_test + - <<: *if-dev-push + changes: *patterns-target_test-i154 - <<: *if-dev-push changes: *patterns-unit_test - <<: *if-dev-push changes: *patterns-unit_test-sdio + - <<: *if-dev-push + changes: *patterns-unit_test-spi_multi .rules:build:unit_test: rules: @@ -1021,10 +1108,14 @@ changes: *patterns-build_components - <<: *if-dev-push changes: *patterns-build_system + - <<: *if-dev-push + changes: *patterns-downloadable-tools - <<: *if-dev-push changes: *patterns-unit_test - <<: *if-dev-push changes: *patterns-unit_test-sdio + - <<: *if-dev-push + changes: *patterns-unit_test-spi_multi .rules:build:unit_test-esp32: rules: @@ -1040,10 +1131,14 @@ changes: *patterns-build_components - <<: *if-dev-push changes: *patterns-build_system + - <<: *if-dev-push + changes: *patterns-downloadable-tools - <<: *if-dev-push changes: *patterns-unit_test - <<: *if-dev-push changes: *patterns-unit_test-sdio + - <<: *if-dev-push + changes: *patterns-unit_test-spi_multi .rules:build:unit_test-esp32c2: rules: @@ -1058,8 +1153,12 @@ changes: *patterns-build_components - <<: *if-dev-push changes: *patterns-build_system + - <<: *if-dev-push + changes: *patterns-downloadable-tools - <<: *if-dev-push changes: *patterns-unit_test-sdio + - <<: *if-dev-push + changes: *patterns-unit_test-spi_multi .rules:build:unit_test-esp32c3: rules: @@ -1075,27 +1174,13 @@ - <<: *if-dev-push changes: *patterns-build_system - <<: *if-dev-push - changes: *patterns-unit_test - - <<: *if-dev-push - changes: *patterns-unit_test-sdio - -.rules:build:unit_test-esp32h2: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32h2 - - <<: *if-dev-push - changes: *patterns-build_components - - <<: *if-dev-push - changes: *patterns-build_system + changes: *patterns-downloadable-tools - <<: *if-dev-push changes: *patterns-unit_test - <<: *if-dev-push changes: *patterns-unit_test-sdio + - <<: *if-dev-push + changes: *patterns-unit_test-spi_multi .rules:build:unit_test-esp32s2: rules: @@ -1110,10 +1195,14 @@ changes: *patterns-build_components - <<: *if-dev-push changes: *patterns-build_system + - <<: *if-dev-push + changes: *patterns-downloadable-tools - <<: *if-dev-push changes: *patterns-unit_test - <<: *if-dev-push changes: *patterns-unit_test-sdio + - <<: *if-dev-push + changes: *patterns-unit_test-spi_multi .rules:build:unit_test-esp32s3: rules: @@ -1128,22 +1217,14 @@ changes: *patterns-build_components - <<: *if-dev-push changes: *patterns-build_system + - <<: *if-dev-push + changes: *patterns-downloadable-tools - <<: *if-dev-push changes: *patterns-unit_test - <<: *if-dev-push changes: *patterns-unit_test-sdio - -.rules:build:windows: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build - - <<: *if-label-windows - <<: *if-dev-push - changes: *patterns-build_system - - <<: *if-dev-push - changes: *patterns-windows + changes: *patterns-unit_test-spi_multi .rules:labels-protected:lan8720: rules: @@ -1192,40 +1273,7 @@ - <<: *if-dev-push changes: *patterns-component_ut -.rules:test:component_ut-esp32-bt: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-component_ut - - <<: *if-label-component_ut_esp32 - - <<: *if-label-target_test - -.rules:test:component_ut-esp32-ethernet: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-component_ut - - <<: *if-label-component_ut_esp32 - - <<: *if-label-target_test - -.rules:test:component_ut-esp32-sdio: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-component_ut - - <<: *if-label-component_ut_esp32 - - <<: *if-label-target_test - -.rules:test:component_ut-esp32-wifi: +.rules:test:component_ut-esp32-adc: rules: - <<: *if-revert-branch when: never @@ -1235,6 +1283,8 @@ - <<: *if-label-component_ut - <<: *if-label-component_ut_esp32 - <<: *if-label-target_test + - <<: *if-dev-push + changes: *patterns-component_ut-adc .rules:test:component_ut-esp32c2: rules: @@ -1246,40 +1296,7 @@ - <<: *if-label-component_ut_esp32c2 - <<: *if-label-unit_test_esp32c2 -.rules:test:component_ut-esp32c2-bt: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-component_ut - - <<: *if-label-component_ut_esp32c2 - - <<: *if-label-target_test - -.rules:test:component_ut-esp32c2-ethernet: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-component_ut - - <<: *if-label-component_ut_esp32c2 - - <<: *if-label-target_test - -.rules:test:component_ut-esp32c2-sdio: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-component_ut - - <<: *if-label-component_ut_esp32c2 - - <<: *if-label-target_test - -.rules:test:component_ut-esp32c2-wifi: +.rules:test:component_ut-esp32c2-adc: rules: - <<: *if-revert-branch when: never @@ -1289,6 +1306,8 @@ - <<: *if-label-component_ut - <<: *if-label-component_ut_esp32c2 - <<: *if-label-target_test + - <<: *if-dev-push + changes: *patterns-component_ut-adc .rules:test:component_ut-esp32c3: rules: @@ -1305,7 +1324,7 @@ - <<: *if-dev-push changes: *patterns-component_ut -.rules:test:component_ut-esp32c3-bt: +.rules:test:component_ut-esp32c3-adc: rules: - <<: *if-revert-branch when: never @@ -1315,98 +1334,8 @@ - <<: *if-label-component_ut - <<: *if-label-component_ut_esp32c3 - <<: *if-label-target_test - -.rules:test:component_ut-esp32c3-ethernet: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-component_ut - - <<: *if-label-component_ut_esp32c3 - - <<: *if-label-target_test - -.rules:test:component_ut-esp32c3-sdio: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-component_ut - - <<: *if-label-component_ut_esp32c3 - - <<: *if-label-target_test - -.rules:test:component_ut-esp32c3-wifi: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-component_ut - - <<: *if-label-component_ut_esp32c3 - - <<: *if-label-target_test - -.rules:test:component_ut-esp32h2: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-component_ut - - <<: *if-label-component_ut_esp32h2 - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32h2 - <<: *if-dev-push - changes: *patterns-component_ut - -.rules:test:component_ut-esp32h2-bt: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-component_ut - - <<: *if-label-component_ut_esp32h2 - - <<: *if-label-target_test - -.rules:test:component_ut-esp32h2-ethernet: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-component_ut - - <<: *if-label-component_ut_esp32h2 - - <<: *if-label-target_test - -.rules:test:component_ut-esp32h2-sdio: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-component_ut - - <<: *if-label-component_ut_esp32h2 - - <<: *if-label-target_test - -.rules:test:component_ut-esp32h2-wifi: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-component_ut - - <<: *if-label-component_ut_esp32h2 - - <<: *if-label-target_test + changes: *patterns-component_ut-adc .rules:test:component_ut-esp32s2: rules: @@ -1423,40 +1352,7 @@ - <<: *if-dev-push changes: *patterns-component_ut -.rules:test:component_ut-esp32s2-bt: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-component_ut - - <<: *if-label-component_ut_esp32s2 - - <<: *if-label-target_test - -.rules:test:component_ut-esp32s2-ethernet: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-component_ut - - <<: *if-label-component_ut_esp32s2 - - <<: *if-label-target_test - -.rules:test:component_ut-esp32s2-sdio: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-component_ut - - <<: *if-label-component_ut_esp32s2 - - <<: *if-label-target_test - -.rules:test:component_ut-esp32s2-wifi: +.rules:test:component_ut-esp32s2-adc: rules: - <<: *if-revert-branch when: never @@ -1466,6 +1362,8 @@ - <<: *if-label-component_ut - <<: *if-label-component_ut_esp32s2 - <<: *if-label-target_test + - <<: *if-dev-push + changes: *patterns-component_ut-adc .rules:test:component_ut-esp32s3: rules: @@ -1474,43 +1372,15 @@ - <<: *if-protected - <<: *if-label-build-only when: never + - <<: *if-label-component_ut - <<: *if-label-component_ut_esp32s3 + - <<: *if-label-target_test + - <<: *if-label-unit_test - <<: *if-label-unit_test_esp32s3 + - <<: *if-dev-push + changes: *patterns-component_ut -.rules:test:component_ut-esp32s3-bt: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-component_ut - - <<: *if-label-component_ut_esp32s3 - - <<: *if-label-target_test - -.rules:test:component_ut-esp32s3-ethernet: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-component_ut - - <<: *if-label-component_ut_esp32s3 - - <<: *if-label-target_test - -.rules:test:component_ut-esp32s3-sdio: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-component_ut - - <<: *if-label-component_ut_esp32s3 - - <<: *if-label-target_test - -.rules:test:component_ut-esp32s3-wifi: +.rules:test:component_ut-esp32s3-adc: rules: - <<: *if-revert-branch when: never @@ -1520,6 +1390,8 @@ - <<: *if-label-component_ut - <<: *if-label-component_ut_esp32s3 - <<: *if-label-target_test + - <<: *if-dev-push + changes: *patterns-component_ut-adc .rules:test:custom_test-esp32: rules: @@ -1534,50 +1406,6 @@ - <<: *if-dev-push changes: *patterns-custom_test -.rules:test:custom_test-esp32-bt: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32 - - <<: *if-label-target_test - -.rules:test:custom_test-esp32-ethernet: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32 - - <<: *if-label-target_test - -.rules:test:custom_test-esp32-sdio: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32 - - <<: *if-label-target_test - -.rules:test:custom_test-esp32-wifi: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32 - - <<: *if-label-target_test - .rules:test:custom_test-esp32c2: rules: - <<: *if-revert-branch @@ -1587,50 +1415,6 @@ when: never - <<: *if-label-custom_test_esp32c2 -.rules:test:custom_test-esp32c2-bt: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32c2 - - <<: *if-label-target_test - -.rules:test:custom_test-esp32c2-ethernet: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32c2 - - <<: *if-label-target_test - -.rules:test:custom_test-esp32c2-sdio: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32c2 - - <<: *if-label-target_test - -.rules:test:custom_test-esp32c2-wifi: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32c2 - - <<: *if-label-target_test - .rules:test:custom_test-esp32c3: rules: - <<: *if-revert-branch @@ -1644,107 +1428,6 @@ - <<: *if-dev-push changes: *patterns-custom_test -.rules:test:custom_test-esp32c3-bt: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32c3 - - <<: *if-label-target_test - -.rules:test:custom_test-esp32c3-ethernet: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32c3 - - <<: *if-label-target_test - -.rules:test:custom_test-esp32c3-sdio: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32c3 - - <<: *if-label-target_test - -.rules:test:custom_test-esp32c3-wifi: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32c3 - - <<: *if-label-target_test - -.rules:test:custom_test-esp32h2: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32h2 - - <<: *if-label-target_test - - <<: *if-dev-push - changes: *patterns-custom_test - -.rules:test:custom_test-esp32h2-bt: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32h2 - - <<: *if-label-target_test - -.rules:test:custom_test-esp32h2-ethernet: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32h2 - - <<: *if-label-target_test - -.rules:test:custom_test-esp32h2-sdio: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32h2 - - <<: *if-label-target_test - -.rules:test:custom_test-esp32h2-wifi: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32h2 - - <<: *if-label-target_test - .rules:test:custom_test-esp32s2: rules: - <<: *if-revert-branch @@ -1758,93 +1441,7 @@ - <<: *if-dev-push changes: *patterns-custom_test -.rules:test:custom_test-esp32s2-bt: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32s2 - - <<: *if-label-target_test - -.rules:test:custom_test-esp32s2-ethernet: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32s2 - - <<: *if-label-target_test - -.rules:test:custom_test-esp32s2-sdio: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32s2 - - <<: *if-label-target_test - -.rules:test:custom_test-esp32s2-wifi: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32s2 - - <<: *if-label-target_test - .rules:test:custom_test-esp32s3: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test_esp32s3 - -.rules:test:custom_test-esp32s3-bt: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32s3 - - <<: *if-label-target_test - -.rules:test:custom_test-esp32s3-ethernet: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32s3 - - <<: *if-label-target_test - -.rules:test:custom_test-esp32s3-sdio: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32s3 - - <<: *if-label-target_test - -.rules:test:custom_test-esp32s3-wifi: rules: - <<: *if-revert-branch when: never @@ -1854,6 +1451,8 @@ - <<: *if-label-custom_test - <<: *if-label-custom_test_esp32s3 - <<: *if-label-target_test + - <<: *if-dev-push + changes: *patterns-custom_test .rules:test:example_test-esp32: rules: @@ -1905,17 +1504,6 @@ when: never - <<: *if-example_test-ota-include_nightly_run-rule -.rules:test:example_test-esp32-sdio: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-example_test - - <<: *if-label-example_test_esp32 - - <<: *if-label-target_test - .rules:test:example_test-esp32-wifi: rules: - <<: *if-revert-branch @@ -1938,56 +1526,6 @@ when: never - <<: *if-label-example_test_esp32c2 -.rules:test:example_test-esp32c2-bt: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-example_test - - <<: *if-label-example_test_esp32c2 - - <<: *if-label-target_test - - <<: *if-dev-push - changes: *patterns-example_test-bt - -.rules:test:example_test-esp32c2-ethernet: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-example_test - - <<: *if-label-example_test_esp32c2 - - <<: *if-label-target_test - - <<: *if-dev-push - changes: *patterns-example_test-ethernet - -.rules:test:example_test-esp32c2-sdio: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-example_test - - <<: *if-label-example_test_esp32c2 - - <<: *if-label-target_test - -.rules:test:example_test-esp32c2-wifi: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-example_test - - <<: *if-label-example_test_esp32c2 - - <<: *if-label-target_test - - <<: *if-dev-push - changes: *patterns-example_test-wifi - .rules:test:example_test-esp32c3: rules: - <<: *if-revert-branch @@ -2003,32 +1541,6 @@ - <<: *if-dev-push changes: *patterns-example_test -.rules:test:example_test-esp32c3-bt: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-example_test - - <<: *if-label-example_test_esp32c3 - - <<: *if-label-target_test - - <<: *if-dev-push - changes: *patterns-example_test-bt - -.rules:test:example_test-esp32c3-ethernet: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-example_test - - <<: *if-label-example_test_esp32c3 - - <<: *if-label-target_test - - <<: *if-dev-push - changes: *patterns-example_test-ethernet - .rules:test:example_test-esp32c3-include_nightly_run-rule: rules: - <<: *if-revert-branch @@ -2038,95 +1550,6 @@ when: never - <<: *if-example_test-ota-include_nightly_run-rule -.rules:test:example_test-esp32c3-sdio: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-example_test - - <<: *if-label-example_test_esp32c3 - - <<: *if-label-target_test - -.rules:test:example_test-esp32c3-wifi: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-example_test - - <<: *if-label-example_test_esp32c3 - - <<: *if-label-target_test - - <<: *if-dev-push - changes: *patterns-example_test-wifi - -.rules:test:example_test-esp32h2: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-example_test - - <<: *if-label-example_test_esp32h2 - - <<: *if-label-target_test - - <<: *if-dev-push - changes: *patterns-build-example_test - - <<: *if-dev-push - changes: *patterns-example_test - -.rules:test:example_test-esp32h2-bt: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-example_test - - <<: *if-label-example_test_esp32h2 - - <<: *if-label-target_test - - <<: *if-dev-push - changes: *patterns-example_test-bt - -.rules:test:example_test-esp32h2-ethernet: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-example_test - - <<: *if-label-example_test_esp32h2 - - <<: *if-label-target_test - - <<: *if-dev-push - changes: *patterns-example_test-ethernet - -.rules:test:example_test-esp32h2-sdio: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-example_test - - <<: *if-label-example_test_esp32h2 - - <<: *if-label-target_test - -.rules:test:example_test-esp32h2-wifi: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-example_test - - <<: *if-label-example_test_esp32h2 - - <<: *if-label-target_test - - <<: *if-dev-push - changes: *patterns-example_test-wifi - .rules:test:example_test-esp32s2: rules: - <<: *if-revert-branch @@ -2142,7 +1565,7 @@ - <<: *if-dev-push changes: *patterns-example_test -.rules:test:example_test-esp32s2-bt: +.rules:test:example_test-esp32s2-usb: rules: - <<: *if-revert-branch when: never @@ -2153,55 +1576,9 @@ - <<: *if-label-example_test_esp32s2 - <<: *if-label-target_test - <<: *if-dev-push - changes: *patterns-example_test-bt - -.rules:test:example_test-esp32s2-ethernet: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-example_test - - <<: *if-label-example_test_esp32s2 - - <<: *if-label-target_test - - <<: *if-dev-push - changes: *patterns-example_test-ethernet - -.rules:test:example_test-esp32s2-sdio: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-example_test - - <<: *if-label-example_test_esp32s2 - - <<: *if-label-target_test - -.rules:test:example_test-esp32s2-wifi: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-example_test - - <<: *if-label-example_test_esp32s2 - - <<: *if-label-target_test - - <<: *if-dev-push - changes: *patterns-example_test-wifi + changes: *patterns-example_test-usb .rules:test:example_test-esp32s3: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-example_test_esp32s3 - -.rules:test:example_test-esp32s3-bt: rules: - <<: *if-revert-branch when: never @@ -2212,9 +1589,11 @@ - <<: *if-label-example_test_esp32s3 - <<: *if-label-target_test - <<: *if-dev-push - changes: *patterns-example_test-bt + changes: *patterns-build-example_test + - <<: *if-dev-push + changes: *patterns-example_test -.rules:test:example_test-esp32s3-ethernet: +.rules:test:example_test-i154: rules: - <<: *if-revert-branch when: never @@ -2222,34 +1601,9 @@ - <<: *if-label-build-only when: never - <<: *if-label-example_test - - <<: *if-label-example_test_esp32s3 - <<: *if-label-target_test - <<: *if-dev-push - changes: *patterns-example_test-ethernet - -.rules:test:example_test-esp32s3-sdio: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-example_test - - <<: *if-label-example_test_esp32s3 - - <<: *if-label-target_test - -.rules:test:example_test-esp32s3-wifi: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-example_test - - <<: *if-label-example_test_esp32s3 - - <<: *if-label-target_test - - <<: *if-dev-push - changes: *patterns-example_test-wifi + changes: *patterns-target_test-i154 .rules:test:host_test: rules: @@ -2298,28 +1652,6 @@ - <<: *if-dev-push changes: *patterns-unit_test -.rules:test:unit_test-esp32-bt: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32 - -.rules:test:unit_test-esp32-ethernet: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32 - .rules:test:unit_test-esp32-sdio: rules: - <<: *if-revert-branch @@ -2333,17 +1665,6 @@ - <<: *if-dev-push changes: *patterns-unit_test-sdio -.rules:test:unit_test-esp32-wifi: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32 - .rules:test:unit_test-esp32c2: rules: - <<: *if-revert-branch @@ -2353,29 +1674,7 @@ when: never - <<: *if-label-unit_test_esp32c2 -.rules:test:unit_test-esp32c2-bt: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32c2 - -.rules:test:unit_test-esp32c2-ethernet: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32c2 - -.rules:test:unit_test-esp32c2-sdio: +.rules:test:unit_test-esp32c2-spi_multi: rules: - <<: *if-revert-branch when: never @@ -2386,18 +1685,7 @@ - <<: *if-label-unit_test - <<: *if-label-unit_test_esp32c2 - <<: *if-dev-push - changes: *patterns-unit_test-sdio - -.rules:test:unit_test-esp32c2-wifi: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32c2 + changes: *patterns-unit_test-spi_multi .rules:test:unit_test-esp32c3: rules: @@ -2412,111 +1700,6 @@ - <<: *if-dev-push changes: *patterns-unit_test -.rules:test:unit_test-esp32c3-bt: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32c3 - -.rules:test:unit_test-esp32c3-ethernet: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32c3 - -.rules:test:unit_test-esp32c3-sdio: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32c3 - - <<: *if-dev-push - changes: *patterns-unit_test-sdio - -.rules:test:unit_test-esp32c3-wifi: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32c3 - -.rules:test:unit_test-esp32h2: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32h2 - - <<: *if-dev-push - changes: *patterns-unit_test - -.rules:test:unit_test-esp32h2-bt: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32h2 - -.rules:test:unit_test-esp32h2-ethernet: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32h2 - -.rules:test:unit_test-esp32h2-sdio: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32h2 - - <<: *if-dev-push - changes: *patterns-unit_test-sdio - -.rules:test:unit_test-esp32h2-wifi: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32h2 - .rules:test:unit_test-esp32s2: rules: - <<: *if-revert-branch @@ -2530,84 +1713,7 @@ - <<: *if-dev-push changes: *patterns-unit_test -.rules:test:unit_test-esp32s2-bt: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32s2 - -.rules:test:unit_test-esp32s2-ethernet: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32s2 - -.rules:test:unit_test-esp32s2-sdio: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32s2 - - <<: *if-dev-push - changes: *patterns-unit_test-sdio - -.rules:test:unit_test-esp32s2-wifi: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32s2 - .rules:test:unit_test-esp32s3: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-unit_test_esp32s3 - -.rules:test:unit_test-esp32s3-bt: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32s3 - -.rules:test:unit_test-esp32s3-ethernet: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32s3 - -.rules:test:unit_test-esp32s3-sdio: rules: - <<: *if-revert-branch when: never @@ -2618,15 +1724,4 @@ - <<: *if-label-unit_test - <<: *if-label-unit_test_esp32s3 - <<: *if-dev-push - changes: *patterns-unit_test-sdio - -.rules:test:unit_test-esp32s3-wifi: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build-only - when: never - - <<: *if-label-target_test - - <<: *if-label-unit_test - - <<: *if-label-unit_test_esp32s3 + changes: *patterns-unit_test diff --git a/.gitlab/ci/static-code-analysis.yml b/.gitlab/ci/static-code-analysis.yml index 23de4fb9be..55ee95cf3e 100644 --- a/.gitlab/ci/static-code-analysis.yml +++ b/.gitlab/ci/static-code-analysis.yml @@ -1,7 +1,7 @@ # pre_check stage clang_tidy_check: extends: - - .pre_check_base_template + - .pre_check_template - .rules:patterns:clang_tidy image: ${CLANG_STATIC_ANALYSIS_IMAGE} artifacts: @@ -14,7 +14,6 @@ clang_tidy_check: RULES_FILE: ${CI_PROJECT_DIR}/tools/ci/static-analysis-rules.yml OUTPUT_DIR: ${CI_PROJECT_DIR}/clang_tidy_reports script: - - python -m pip install -U pip - internal_pip_install $CLANG_TIDY_RUNNER_PROJ pyclang - export PATH=$PATH:$(python -c "import sys; print(sys.executable.rsplit('/', 1)[0])") - dirs=$(cat ${CLANG_TIDY_DIRS_TXT} | while read line; do echo ${CI_PROJECT_DIR}/${line}; done | xargs) @@ -26,7 +25,7 @@ clang_tidy_check: check_pylint: extends: - - .pre_check_base_template + - .pre_check_template - .rules:patterns:python-files - .before_script_minimal image: $SONARQUBE_SCANNER_IMAGE diff --git a/.gitlab/ci/target-test.yml b/.gitlab/ci/target-test.yml index c4c3591d48..94c0916b45 100644 --- a/.gitlab/ci/target-test.yml +++ b/.gitlab/ci/target-test.yml @@ -15,7 +15,6 @@ .pytest_template: extends: - .target_test_template - - .before_script_pytest artifacts: when: always paths: @@ -72,6 +71,14 @@ example_test_pytest_esp32s3_generic: - build_pytest_examples_esp32s3 tags: [ esp32s3, generic ] +example_test_pytest_esp32s3_f4r8: + extends: + - .pytest_examples_dir_template + - .rules:test:example_test-esp32s3 + needs: + - build_pytest_examples_esp32s3 + tags: [ esp32s3, MSPI_F4R8 ] + example_test_pytest_esp32c2_generic: extends: - .pytest_examples_dir_template @@ -208,6 +215,54 @@ example_test_pytest_esp32c3_flash_encryption: - build_pytest_examples_esp32c3 tags: [ esp32c3, flash_encryption ] +example_test_pytest_esp32s2_usb_device: + extends: + - .pytest_examples_dir_template + - .rules:test:example_test-esp32s2-usb + needs: + - build_pytest_examples_esp32s2 + tags: [ esp32s2, usb_device ] + +example_test_pytest_esp32_sdmmc: + extends: + - .pytest_examples_dir_template + - .rules:test:example_test-esp32 + needs: + - build_pytest_examples_esp32 + tags: [ esp32, sdcard_sdmode ] + +example_test_pytest_esp32_sdspi: + extends: + - .pytest_examples_dir_template + - .rules:test:example_test-esp32 + needs: + - build_pytest_examples_esp32 + tags: [ esp32, sdcard_spimode ] + +example_test_pytest_esp32s2_sdspi: + extends: + - .pytest_examples_dir_template + - .rules:test:example_test-esp32s2 + needs: + - build_pytest_examples_esp32s2 + tags: [ esp32s2, sdcard_spimode ] + +example_test_pytest_esp32c3_sdspi: + extends: + - .pytest_examples_dir_template + - .rules:test:example_test-esp32c3 + needs: + - build_pytest_examples_esp32c3 + tags: [ esp32c3, sdcard_spimode ] + +example_test_pytest_esp32_extflash: + extends: + - .pytest_examples_dir_template + - .rules:test:example_test-esp32 + needs: + - build_pytest_examples_esp32 + tags: [ esp32, external_flash ] + .pytest_components_dir_template: extends: .pytest_template variables: @@ -221,6 +276,22 @@ component_ut_pytest_esp32_generic: - build_pytest_components_esp32 tags: [ esp32, generic ] +component_ut_pytest_esp32_generic_multi_device: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32 + needs: + - build_pytest_components_esp32 + tags: [ esp32, generic_multi_device ] + +component_ut_pytest_esp32_adc: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32-adc + needs: + - build_pytest_components_esp32 + tags: [ esp32, adc ] + component_ut_pytest_esp32_ip101: extends: - .pytest_components_dir_template @@ -245,6 +316,14 @@ component_ut_pytest_esp32_flash_encryption: - build_pytest_components_esp32 tags: [ esp32, flash_encryption ] +component_ut_pytest_esp32_flash_multi: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32 + needs: + - build_pytest_components_esp32 + tags: [ esp32, flash_mutli ] + component_ut_pytest_esp32s2_generic: extends: - .pytest_components_dir_template @@ -253,6 +332,30 @@ component_ut_pytest_esp32s2_generic: - build_pytest_components_esp32s2 tags: [ esp32s2, generic ] +component_ut_pytest_esp32s2_generic_multi_device: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32s2 + needs: + - build_pytest_components_esp32s2 + tags: [ esp32s2, generic_multi_device ] + +component_ut_pytest_esp32s2_adc: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32s2-adc + needs: + - build_pytest_components_esp32s2 + tags: [ esp32s2, adc ] + +component_ut_pytest_esp32s2_flash_multi: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32s2 + needs: + - build_pytest_components_esp32s2 + tags: [ esp32s2, flash_mutli ] + component_ut_pytest_esp32s3_generic: extends: - .pytest_components_dir_template @@ -261,6 +364,22 @@ component_ut_pytest_esp32s3_generic: - build_pytest_components_esp32s3 tags: [ esp32s3, generic ] +component_ut_pytest_esp32s3_generic_multi_device: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32s3 + needs: + - build_pytest_components_esp32s3 + tags: [ esp32s3, generic_multi_device ] + +component_ut_pytest_esp32s3_adc: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32s3-adc + needs: + - build_pytest_components_esp32s3 + tags: [ esp32s3, adc ] + component_ut_pytest_esp32s3_octal_psram: extends: - .pytest_components_dir_template @@ -285,6 +404,14 @@ component_ut_pytest_esp32s3_flash_encryption_f8r8: - build_pytest_components_esp32s3 tags: [ esp32s3, flash_encryption_f8r8 ] +component_ut_pytest_esp32s3_flash_multi: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32s3 + needs: + - build_pytest_components_esp32s3 + tags: [ esp32s3, flash_mutli ] + component_ut_pytest_esp32c2_generic: extends: - .pytest_components_dir_template @@ -293,6 +420,14 @@ component_ut_pytest_esp32c2_generic: - build_pytest_components_esp32c2 tags: [ esp32c2, generic, xtal_40mhz ] +component_ut_pytest_esp32c2_adc: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32c2-adc + needs: + - build_pytest_components_esp32c2 + tags: [ esp32c2, adc ] + component_ut_pytest_esp32c2_xtal_26mhz: extends: - .pytest_components_dir_template @@ -309,6 +444,22 @@ component_ut_pytest_esp32c3_generic: - build_pytest_components_esp32c3 tags: [ esp32c3, generic ] +component_ut_pytest_esp32c3_generic_multi_device: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32c3 + needs: + - build_pytest_components_esp32c3 + tags: [ esp32c3, generic_multi_device ] + +component_ut_pytest_esp32c3_adc: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32c3-adc + needs: + - build_pytest_components_esp32c3 + tags: [ esp32c3, adc ] + component_ut_pytest_esp32c3_flash_encryption: extends: - .pytest_components_dir_template @@ -317,6 +468,57 @@ component_ut_pytest_esp32c3_flash_encryption: - build_pytest_components_esp32c3 tags: [ esp32c3, flash_encryption ] +component_ut_pytest_esp32c3_flash_multi: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32c3 + needs: + - build_pytest_components_esp32c3 + tags: [ esp32c3, flash_mutli ] + +component_ut_pytest_esp32_sdmmc: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32 + needs: + - build_pytest_components_esp32 + tags: [ esp32, sdcard_sdmode ] + +component_ut_pytest_esp32_sdspi: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32 + needs: + - build_pytest_components_esp32 + tags: [ esp32, sdcard_spimode ] + +component_ut_pytest_esp32s2_sdspi: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32s2 + needs: + - build_pytest_components_esp32s2 + tags: [ esp32s2, sdcard_spimode ] + +component_ut_pytest_esp32c3_sdspi: + extends: + - .pytest_components_dir_template + - .rules:test:component_ut-esp32c3 + needs: + - build_pytest_components_esp32c3 + tags: [ esp32c3, sdcard_spimode ] + +example_test_pytest_openthread_br: + extends: + - .pytest_examples_dir_template + - .rules:test:example_test-i154 + needs: + - build_pytest_examples_esp32s3 + - build_pytest_examples_esp32h2 + tags: + - esp32h2 + - i154_multi_dut + .pytest_test_apps_dir_template: extends: .pytest_template variables: @@ -332,6 +534,16 @@ test_app_test_pytest_esp32_generic: variables: SETUP_TOOLS: "1" # need gdb +test_app_test_pytest_esp32_jtag: + extends: + - .pytest_test_apps_dir_template + - .rules:test:custom_test-esp32 + needs: + - build_pytest_test_apps_esp32 + tags: [ esp32, test_jtag_arm] + variables: + SETUP_TOOLS: "1" # need gdb + test_app_test_pytest_esp32s2_generic: extends: - .pytest_test_apps_dir_template @@ -374,14 +586,6 @@ test_app_test_pytest_esp32c3_generic: - build_pytest_test_apps_esp32c3 tags: [ esp32c3, generic ] -test_app_test_pytest_esp32s2_usb_host: - extends: - - .pytest_test_apps_dir_template - - .rules:test:custom_test-esp32s2 - needs: - - build_pytest_test_apps_esp32s2 - tags: [ esp32s2, usb_host ] - test_app_test_pytest_esp32s3_mspi_f8r8: extends: - .pytest_test_apps_dir_template @@ -498,7 +702,6 @@ example_test_001B_V3: example_test_001C: extends: .example_test_esp32_template - parallel: 2 tags: - ESP32 - Example_GENERIC @@ -576,24 +779,12 @@ example_test_009: SETUP_TOOLS: "1" PYTHON_VER: 3 -example_test_010: - extends: .example_test_esp32_template - tags: - - ESP32 - - Example_ExtFlash - example_test_011: extends: .example_test_esp32_template tags: - ESP32 - Example_T2_RS485 -example_test_013: - extends: .example_test_esp32_template - tags: - - ESP32 - - UT_T1_SDMODE - example_test_016: extends: .example_test_esp32_template tags: @@ -608,28 +799,15 @@ example_test_017: example_test_C3_GENERIC: extends: .example_test_esp32c3_template - parallel: 2 tags: - ESP32C3 - Example_GENERIC -example_test_ESP32_SDSPI: - extends: .example_test_esp32_template +example_test_C2_GENERIC: + extends: .example_test_esp32c2_template tags: - - ESP32 - - UT_T1_SPIMODE - -example_test_ESP32S2_SDSPI: - extends: .example_test_esp32s2_template - tags: - - ESP32S2 - - UT_T1_SPIMODE - -example_test_ESP32C3_SDSPI: - extends: .example_test_esp32c3_template - tags: - - ESP32C3 - - UT_T1_SPIMODE + - ESP32C2 + - Example_GENERIC .test_app_template: extends: .target_test_job_template @@ -679,43 +857,6 @@ test_app_test_eth: - ESP32 - ethernet_router -test_app_test_004: - extends: .test_app_esp32s2_template - tags: - - ESP32S2 - - Example_GENERIC - -test_app_test_esp32c2_generic: - extends: .test_app_esp32c2_template - tags: - - ESP32C2 - - Example_GENERIC - - xtal_40mhz - -test_app_test_esp32c2_26mhz: - extends: .test_app_esp32c2_template - tags: - - ESP32C2 - - xtal_26mhz - -test_app_test_005: - extends: .test_app_esp32c3_template - tags: - - ESP32C3 - - Example_GENERIC - -test_app_test_006: - extends: .test_app_esp32s3_template - tags: - - ESP32S3 - - Example_GENERIC - -test_app_test_esp32_generic: - extends: .test_app_esp32_template - tags: - - ESP32 - - Example_GENERIC - .unit_test_template: extends: .target_test_job_template needs: # the assign already needs all the build jobs @@ -752,7 +893,7 @@ test_app_test_esp32_generic: UT_001: extends: .unit_test_esp32_template - parallel: 50 + parallel: 42 tags: - ESP32_IDF - UT_T1_1 @@ -761,7 +902,7 @@ UT_001: UT_002: extends: .unit_test_esp32_template - parallel: 21 + parallel: 15 tags: - ESP32_IDF - UT_T1_1 @@ -794,20 +935,6 @@ UT_006: - UT_T1_SPIMODE - psram -UT_007: - extends: .unit_test_esp32_template - parallel: 2 - tags: - - ESP32_IDF - - UT_T1_1 - -UT_008: - extends: .unit_test_esp32_template - tags: - - ESP32_IDF - - UT_T1_GPIO - - psram - UT_014: extends: .unit_test_esp32_template tags: @@ -859,14 +986,13 @@ UT_033: UT_034: extends: .unit_test_esp32_template - parallel: 2 tags: - ESP32_IDF - UT_T1_ESP_FLASH UT_035: extends: .unit_test_esp32s2_template - parallel: 50 + parallel: 43 tags: - ESP32S2_IDF - UT_T1_1 @@ -880,7 +1006,6 @@ UT_036: UT_038: extends: .unit_test_esp32s2_template - parallel: 2 tags: - ESP32S2_IDF - UT_T1_ESP_FLASH @@ -916,25 +1041,37 @@ UT_045: - UT_SDIO - psram -UT_046: - extends: .unit_test_esp32_template - tags: - - ESP32_IDF - - UT_T1_GPIO - -UT_047: - extends: .unit_test_esp32s2_template - parallel: 6 - tags: - - ESP32S2_IDF - - UT_T1_1 - UT_S2_SPI_DUAL: extends: .unit_test_esp32s2_template tags: - ESP32S2_IDF - Example_SPI_Multi_device +UT_S2_SPI_QUAD: + extends: .unit_test_esp32s2_template + tags: + - ESP32S2_IDF + - Example_SPI_Quad_Multi_device + +UT_S3_SPI_QUAD: + extends: .unit_test_esp32s3_template + tags: + - ESP32S3_IDF + - Example_SPI_Quad_Multi_device + +UT_C2_SPI_QUAD: + extends: .unit_test_esp32c2_template + tags: + - ESP32C2_IDF + - Example_SPI_Quad_Multi_device + - xtal_40mhz + +UT_C3_SPI_QUAD: + extends: .unit_test_esp32c3_template + tags: + - ESP32C3_IDF + - Example_SPI_Quad_Multi_device + UT_S2_SDSPI: extends: .unit_test_esp32s2_template tags: @@ -943,12 +1080,21 @@ UT_S2_SDSPI: UT_C2: extends: .unit_test_esp32c2_template - parallel: 21 + parallel: 19 tags: - ESP32C2_IDF - UT_T1_1 - xtal_40mhz +UT_C2_SPI_DUAL: + extends: + - .unit_test_esp32c2_template + - .rules:test:unit_test-esp32c2-spi_multi + tags: + - ESP32C2_IDF + - Example_SPI_Multi_device + - xtal_40mhz + UT_C2_26M: extends: .unit_test_esp32c2_template tags: @@ -956,16 +1102,23 @@ UT_C2_26M: - UT_T1_1 - xtal_26mhz +UT_C2_FLASH: + extends: + - .unit_test_esp32c2_template + tags: + - ESP32C2_IDF + - UT_T1_ESP_FLASH + - xtal_40mhz + UT_C3: extends: .unit_test_esp32c3_template - parallel: 31 + parallel: 26 tags: - ESP32C3_IDF - UT_T1_1 UT_C3_FLASH: extends: .unit_test_esp32c3_template - parallel: 2 tags: - ESP32C3_IDF - UT_T1_ESP_FLASH @@ -996,14 +1149,14 @@ UT_C3_SDSPI: UT_S3: extends: .unit_test_esp32s3_template - parallel: 29 + parallel: 24 tags: - ESP32S3_IDF - UT_T1_1 UT_S3_QUAD_PSRAM: extends: .unit_test_esp32s3_template - parallel: 4 + parallel: 3 tags: - ESP32S3_IDF - UT_T1_1 @@ -1026,8 +1179,9 @@ UT_S3_FLASH: extends: - .target_test_job_template - .rules:test:integration_test - # needn't install idf python env - - .before_script_integration_test + - .before_script_minimal + image: ${CI_INTEGRATION_TEST_ENV_IMAGE} + cache: [] needs: # the assign already needs all the build jobs - assign_integration_test variables: @@ -1038,22 +1192,23 @@ UT_S3_FLASH: KNOWN_ISSUE_FILE: "${CI_PROJECT_DIR}/tools/ci/integration_test/KnownIssues" CI_RUNNER_SCRIPT: "${CI_PROJECT_DIR}/auto_test_script/bin/CIRunner.py" PREPARE_TEST_BIN_SCRIPT: "${CI_PROJECT_DIR}/tools/ci/integration_test/prepare_test_bins.py" - PYTHONPATH: "${CI_PROJECT_DIR}/auto_test_script/packages:${PYTHONPATH}" + PYTHONPATH: "${CI_PROJECT_DIR}/auto_test_script/packages:${CI_PROJECT_DIR}/tools/ci/python_packages:${PYTHONPATH}" INITIAL_CONDITION_RETRY_COUNT: "1" - # auto_test_script only supports python 3.7.x - PYTHON_VER: 3.7.7 + GIT_LFS_SKIP_SMUDGE: 1 script: - *define_config_file_name # first test if config file exists, if not exist, exit 0 - test -e $CONFIG_FILE || exit 0 # clone local test env configs + - add_gitlab_ssh_keys - retry_failed git clone $TEST_ENV_CONFIG_REPO - python $CHECKOUT_REF_SCRIPT ci-test-runner-configs ci-test-runner-configs # clone test bench - # can not retry if downing git lfs files failed, so using empty_branch first. - - retry_failed git clone ${CI_AUTO_TEST_SCRIPT_REPO_URL} -b empty_branch - - retry_failed git -C auto_test_script checkout -f ${CI_AUTO_TEST_SCRIPT_REPO_BRANCH} - - python $CHECKOUT_REF_SCRIPT auto_test_script auto_test_script --customized_only + - retry_failed git clone ${CI_AUTO_TEST_SCRIPT_REPO_URL} auto_test_script + - python $CHECKOUT_REF_SCRIPT auto_test_script auto_test_script + - cd auto_test_script + - ./tools/ci/setup_idfci.sh + # Merge known issues - cat ${KNOWN_ISSUE_FILE} >> ${TEST_CASE_FILE_PATH}/KnownIssues # run test - python ${PREPARE_TEST_BIN_SCRIPT} $CONFIG_FILE @@ -1080,20 +1235,16 @@ nvs_compatible_test: - *define_config_file_name # first test if config file exists, if not exist, exit 0 - test -e $CONFIG_FILE || exit 0 - # prepare test utilities - - source tools/ci/setup_python.sh - - add_gitlab_ssh_keys - - fetch_submodules # clone local test env configs + - add_gitlab_ssh_keys - retry_failed git clone $TEST_ENV_CONFIG_REPO - python $CHECKOUT_REF_SCRIPT ci-test-runner-configs ci-test-runner-configs # clone test bench - # can not retry if downing git lfs files failed, so using empty_branch first. - - retry_failed git clone ${CI_AUTO_TEST_SCRIPT_REPO_URL} -b empty_branch - - retry_failed git -C auto_test_script checkout -f ${CI_AUTO_TEST_SCRIPT_REPO_BRANCH} - - python $CHECKOUT_REF_SCRIPT auto_test_script auto_test_script --customized_only - # prepare nvs bins + - retry_failed git clone ${CI_AUTO_TEST_SCRIPT_REPO_URL} auto_test_script + - python $CHECKOUT_REF_SCRIPT auto_test_script auto_test_script - cd auto_test_script + - ./tools/ci/setup_idfci.sh + # prepare nvs bins - ./tools/prepare_nvs_bin.sh # run test - python ${PREPARE_TEST_BIN_SCRIPT} $CONFIG_FILE diff --git a/.gitlab/ci/upload_cache.yml b/.gitlab/ci/upload_cache.yml index b2ddb81bc4..191c0328a0 100644 --- a/.gitlab/ci/upload_cache.yml +++ b/.gitlab/ci/upload_cache.yml @@ -9,6 +9,7 @@ upload-pip-cache: extends: - .upload_cache_template + - .before_script_minimal - .rules:patterns:python-cache tags: - $GEO @@ -18,13 +19,9 @@ upload-pip-cache: paths: - .cache/pip policy: push - before_script: [] script: - - source tools/ci/utils.sh - - is_based_on_commits $REQUIRED_ANCESTOR_COMMITS - - source tools/ci/setup_python.sh - rm -rf .cache/pip # clear old packages - - $IDF_PATH/tools/idf_tools.py install-python-env --features pytest,ci + - bash install.sh --enable-ci --enable-pytest parallel: matrix: - GEO: [ 'shiny', 'brew' ] @@ -32,6 +29,7 @@ upload-pip-cache: upload-submodules-cache: extends: - .upload_cache_template + - .before_script_minimal - .rules:patterns:submodule tags: - $GEO @@ -41,12 +39,11 @@ upload-submodules-cache: paths: - .cache/submodule_archives policy: push - before_script: [] script: - - source tools/ci/utils.sh - - is_based_on_commits $REQUIRED_ANCESTOR_COMMITS - - source tools/ci/setup_python.sh + # use the default gitlab server + - unset LOCAL_GITLAB_HTTPS_HOST - rm -rf .cache/submodule_archives # clear old submodule archives + - add_gitlab_ssh_keys - fetch_submodules parallel: matrix: diff --git a/.gitmodules b/.gitmodules index 23c0bc2d55..c440cdcc39 100644 --- a/.gitmodules +++ b/.gitmodules @@ -51,10 +51,6 @@ path = components/tinyusb/tinyusb url = ../../espressif/tinyusb.git -[submodule "examples/peripherals/secure_element/atecc608_ecdsa/components/esp-cryptoauthlib"] - path = examples/peripherals/secure_element/atecc608_ecdsa/components/esp-cryptoauthlib - url = ../../espressif/esp-cryptoauthlib.git - [submodule "components/cmock/CMock"] path = components/cmock/CMock url = ../../ThrowTheSwitch/CMock.git diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 632952fb7a..704fb18d63 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -21,7 +21,8 @@ repos: .+test_idf_monitor\/tests\/.+| .*_pb2.py| .*.pb-c.h| - .*.pb-c.c + .*.pb-c.c| + .*.yuv )$ - id: end-of-file-fixer exclude: *whitespace_excludes @@ -30,7 +31,7 @@ repos: args: ['-f=lf'] - id: double-quote-string-fixer - repo: https://gitlab.com/pycqa/flake8 - rev: 3.9.2 + rev: 5.0.4 hooks: - id: flake8 args: ['--config=.flake8', '--tee', '--benchmark'] @@ -92,7 +93,7 @@ repos: - PyYAML == 5.3.1 - id: check-generated-rules name: Check rules are generated (based on .gitlab/ci/dependencies/dependencies.yml) - entry: .gitlab/ci/dependencies/generate_rules.py + entry: tools/ci/generate_rules.py language: python files: '\.gitlab/ci/dependencies/.+|\.gitlab/ci/rules\.yml' pass_filenames: false @@ -142,6 +143,7 @@ repos: language: python files: 'tools/test_apps/.+|examples/.+|components/.+' additional_dependencies: + - PyYAML == 5.3.1 - idf_build_apps - id: sort-build-test-rules-ymls name: sort .build-test-rules.yml files @@ -149,6 +151,7 @@ repos: language: python files: '\.build-test-rules\.yml' additional_dependencies: + - PyYAML == 5.3.1 - ruamel.yaml - repo: https://github.com/pre-commit/pre-commit-hooks rev: v4.0.1 diff --git a/Kconfig b/Kconfig index 312ea591d0..c86ebeaaef 100644 --- a/Kconfig +++ b/Kconfig @@ -13,6 +13,7 @@ mainmenu "Espressif IoT Development Framework Configuration" config IDF_ENV_FPGA # This option is for internal use only bool + default "y" if IDF_TARGET_ESP32C6 # TODO: IDF-5630 option env="IDF_ENV_FPGA" config IDF_TARGET_ARCH_RISCV @@ -90,6 +91,12 @@ mainmenu "Espressif IoT Development Framework Configuration" select FREERTOS_UNICORE select IDF_TARGET_ARCH_RISCV + config IDF_TARGET_ESP32C6 + bool + default "y" if IDF_TARGET="esp32c6" + select FREERTOS_UNICORE + select IDF_TARGET_ARCH_RISCV + config IDF_TARGET_LINUX bool default "y" if IDF_TARGET="linux" @@ -100,8 +107,9 @@ mainmenu "Espressif IoT Development Framework Configuration" default 0x0002 if IDF_TARGET_ESP32S2 default 0x0005 if IDF_TARGET_ESP32C3 default 0x0009 if IDF_TARGET_ESP32S3 - default 0x000C if IDF_TARGET_ESP32C2 default 0x000A if IDF_TARGET_ESP32H2_BETA_VERSION_1 + default 0x000C if IDF_TARGET_ESP32C2 + default 0x000D if IDF_TARGET_ESP32C6 default 0x000E if IDF_TARGET_ESP32H2_BETA_VERSION_2 # ESP32H2-TODO: IDF-3475 default 0xFFFF diff --git a/components/README.md b/components/README.md index b913c28026..40b96b5a8a 100644 --- a/components/README.md +++ b/components/README.md @@ -1,3 +1,4 @@ + # Core Components ## Overview @@ -42,7 +43,7 @@ This can also contain files provided by the architecture vendor. Example: - `xt_set_exception_handler` -- `riscv_global_interrupts_enable` +- `rv_utils_intr_enable` - `ERI_PERFMON_MAX` #### `esp_common` diff --git a/components/app_trace/sys_view/Sample/OS/SEGGER_SYSVIEW_FreeRTOS.c b/components/app_trace/sys_view/Sample/OS/SEGGER_SYSVIEW_FreeRTOS.c index 33477e26ed..43625d3d4b 100644 --- a/components/app_trace/sys_view/Sample/OS/SEGGER_SYSVIEW_FreeRTOS.c +++ b/components/app_trace/sys_view/Sample/OS/SEGGER_SYSVIEW_FreeRTOS.c @@ -142,7 +142,11 @@ static U64 _cbGetTime(void) { void SYSVIEW_AddTask(U32 xHandle, const char* pcTaskName, unsigned uxCurrentPriority, U32 pxStack, unsigned uStackHighWaterMark) { unsigned n; - if (memcmp(pcTaskName, "IDLE", 5) == 0) { + /* On multi-core we have several idle tasks with 'IDLEx' names + Not best solution, because we can filter out user tasks starting with 'IDLE'. + But we can not use 'xTaskGetIdleTaskHandle' because at the moment when this + function is called array of idle tasks handles are not initialized yet. */ + if (memcmp(pcTaskName, "IDLE", 4) == 0) { return; } @@ -176,7 +180,11 @@ void SYSVIEW_AddTask(U32 xHandle, const char* pcTaskName, unsigned uxCurrentPrio void SYSVIEW_UpdateTask(U32 xHandle, const char* pcTaskName, unsigned uxCurrentPriority, U32 pxStack, unsigned uStackHighWaterMark) { unsigned n; - if (memcmp(pcTaskName, "IDLE", 5) == 0) { + /* On multi-core we have several idle tasks with 'IDLEx' names + Not best solution, because we can filter out user tasks starting with 'IDLE'. + But we can not use 'xTaskGetIdleTaskHandle' because at the moment when this + function is called array of idle tasks handles are not initialized yet. */ + if (memcmp(pcTaskName, "IDLE", 4) == 0) { return; } diff --git a/components/app_trace/sys_view/Sample/OS/SEGGER_SYSVIEW_FreeRTOS.h b/components/app_trace/sys_view/Sample/OS/SEGGER_SYSVIEW_FreeRTOS.h index 3fd508bfde..b03fba82cd 100644 --- a/components/app_trace/sys_view/Sample/OS/SEGGER_SYSVIEW_FreeRTOS.h +++ b/components/app_trace/sys_view/Sample/OS/SEGGER_SYSVIEW_FreeRTOS.h @@ -212,63 +212,27 @@ Notes: #define apiID_UXEVENTGROUPGETNUMBER (73u) #ifdef CONFIG_FREERTOS_SMP -/* -FreeRTOS SMP has diverged from ESP-IDF FreeRTOS source quite a bit, thus Sysview is out of sync. For now, we just -define away all of the tracing macros. -*/ -#define traceTASK_NOTIFY_TAKE( uxIndexToWait ) -#define traceTASK_DELAY() -#define traceTASK_DELAY_UNTIL( xTimeToWake ) -#define traceTASK_DELETE( pxTCB ) -#define traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify ) -#define traceTASK_PRIORITY_INHERIT( pxTCB, uxPriority ) -#define traceTASK_RESUME( pxTCB ) -#define traceINCREASE_TICK_COUNT( xTicksToJump ) -#define traceTASK_SUSPEND( pxTCB ) -#define traceTASK_PRIORITY_DISINHERIT( pxTCB, uxBasePriority ) -#define traceTASK_RESUME_FROM_ISR( pxTCB ) -#define traceTASK_NOTIFY( uxIndexToNotify ) -#define traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify ) -#define traceTASK_NOTIFY_WAIT( uxIndexToWait ) -#define traceQUEUE_CREATE( pxNewQueue ) -#define traceQUEUE_DELETE( pxQueue ) -#define traceQUEUE_PEEK( pxQueue ) -#define traceQUEUE_PEEK_FROM_ISR( pxQueue ) -#define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ) -#define traceQUEUE_RECEIVE( pxQueue ) -#define traceQUEUE_RECEIVE_FAILED( pxQueue ) -#define traceQUEUE_SEMAPHORE_RECEIVE( pxQueue ) -#define traceQUEUE_RECEIVE_FROM_ISR( pxQueue ) -#define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ) -#define traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ) -#define traceQUEUE_SEND( pxQueue ) -#define traceQUEUE_SEND_FAILED( pxQueue ) -#define traceQUEUE_SEND_FROM_ISR( pxQueue ) -#define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ) -#define traceQUEUE_GIVE_FROM_ISR( pxQueue ) -#define traceQUEUE_GIVE_FROM_ISR_FAILED( pxQueue ) -#define traceTASK_CREATE(pxNewTCB) -#define traceTASK_PRIORITY_SET(pxTask, uxNewPriority) -#define traceTASK_SWITCHED_IN() -#define traceMOVED_TASK_TO_READY_STATE(pxTCB) -#define traceREADDED_TASK_TO_READY_STATE(pxTCB) -#define traceMOVED_TASK_TO_DELAYED_LIST() -#define traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST() -#define traceMOVED_TASK_TO_SUSPENDED_LIST(pxTCB) -#define traceISR_EXIT_TO_SCHEDULER() -#define traceISR_EXIT() -#define traceISR_ENTER(_n_) + +#define traceQUEUE_SEND( pxQueue ) SYSVIEW_RecordU32x4(apiFastID_OFFSET + apiID_XQUEUEGENERICSEND, SEGGER_SYSVIEW_ShrinkId((U32)pxQueue), 0, 0, 0) #else // CONFIG_FREERTOS_SMP +#if ( configUSE_QUEUE_SETS != 1 ) + #define traceQUEUE_SEND( pxQueue ) SYSVIEW_RecordU32x4(apiFastID_OFFSET + apiID_XQUEUEGENERICSEND, SEGGER_SYSVIEW_ShrinkId((U32)pxQueue), (U32)pvItemToQueue, xTicksToWait, xCopyPosition) +#else + #define traceQUEUE_SEND( pxQueue ) SYSVIEW_RecordU32x4(apiFastID_OFFSET + apiID_XQUEUEGENERICSEND, SEGGER_SYSVIEW_ShrinkId((U32)pxQueue), 0, 0, 0) +#endif + +#endif // CONFIG_FREERTOS_SMP + #define traceTASK_NOTIFY_TAKE( uxIndexToWait ) SEGGER_SYSVIEW_RecordU32x2(apiFastID_OFFSET + apiID_ULTASKNOTIFYTAKE, xClearCountOnExit, xTicksToWait) #define traceTASK_DELAY() SEGGER_SYSVIEW_RecordU32(apiFastID_OFFSET + apiID_VTASKDELAY, xTicksToDelay) -#define traceTASK_DELAY_UNTIL() SEGGER_SYSVIEW_RecordVoid(apiFastID_OFFSET + apiID_VTASKDELAYUNTIL) -#define traceTASK_DELETE( pxTCB ) if (pxTCB != NULL) { \ - SEGGER_SYSVIEW_RecordU32(apiFastID_OFFSET + apiID_VTASKDELETE, \ - SEGGER_SYSVIEW_ShrinkId((U32)pxTCB)); \ - SYSVIEW_DeleteTask((U32)pxTCB); \ - } +#define traceTASK_DELAY_UNTIL( xTimeToWake ) SEGGER_SYSVIEW_RecordVoid(apiFastID_OFFSET + apiID_VTASKDELAYUNTIL) +#define traceTASK_DELETE( pxTCB ) do { \ + SEGGER_SYSVIEW_RecordU32(apiFastID_OFFSET + apiID_VTASKDELETE, \ + SEGGER_SYSVIEW_ShrinkId((U32)pxTCB)); \ + SYSVIEW_DeleteTask((U32)pxTCB); \ + } while(0) #define traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify ) SEGGER_SYSVIEW_RecordU32x2(apiFastID_OFFSET + apiID_VTASKNOTIFYGIVEFROMISR, SEGGER_SYSVIEW_ShrinkId((U32)pxTCB), (U32)pxHigherPriorityTaskWoken) #define traceTASK_PRIORITY_INHERIT( pxTCB, uxPriority ) SEGGER_SYSVIEW_RecordU32(apiFastID_OFFSET + apiID_VTASKPRIORITYINHERIT, (U32)pxMutexHolder) #define traceTASK_RESUME( pxTCB ) SEGGER_SYSVIEW_RecordU32(apiFastID_OFFSET + apiID_VTASKRESUME, SEGGER_SYSVIEW_ShrinkId((U32)pxTCB)) @@ -291,11 +255,6 @@ define away all of the tracing macros. #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue ) SEGGER_SYSVIEW_RecordU32x3(apiFastID_OFFSET + apiID_XQUEUERECEIVEFROMISR, SEGGER_SYSVIEW_ShrinkId((U32)pxQueue), SEGGER_SYSVIEW_ShrinkId((U32)pvBuffer), (U32)pxHigherPriorityTaskWoken) #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ) SEGGER_SYSVIEW_RecordU32x3(apiFastID_OFFSET + apiID_XQUEUERECEIVEFROMISR, SEGGER_SYSVIEW_ShrinkId((U32)pxQueue), SEGGER_SYSVIEW_ShrinkId((U32)pvBuffer), (U32)pxHigherPriorityTaskWoken) #define traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ) SEGGER_SYSVIEW_RecordU32x2(apiFastID_OFFSET + apiID_VQUEUEADDTOREGISTRY, SEGGER_SYSVIEW_ShrinkId((U32)xQueue), (U32)pcQueueName) -#if ( configUSE_QUEUE_SETS != 1 ) - #define traceQUEUE_SEND( pxQueue ) SYSVIEW_RecordU32x4(apiFastID_OFFSET + apiID_XQUEUEGENERICSEND, SEGGER_SYSVIEW_ShrinkId((U32)pxQueue), (U32)pvItemToQueue, xTicksToWait, xCopyPosition) -#else - #define traceQUEUE_SEND( pxQueue ) SYSVIEW_RecordU32x4(apiFastID_OFFSET + apiID_XQUEUEGENERICSEND, SEGGER_SYSVIEW_ShrinkId((U32)pxQueue), 0, 0, xCopyPosition) -#endif #define traceQUEUE_SEND_FAILED( pxQueue ) SYSVIEW_RecordU32x4(apiFastID_OFFSET + apiID_XQUEUEGENERICSEND, SEGGER_SYSVIEW_ShrinkId((U32)pxQueue), (U32)pvItemToQueue, xTicksToWait, xCopyPosition) #define traceQUEUE_SEND_FROM_ISR( pxQueue ) SEGGER_SYSVIEW_RecordU32x4(apiFastID_OFFSET + apiID_XQUEUEGENERICSENDFROMISR, SEGGER_SYSVIEW_ShrinkId((U32)pxQueue), (U32)pvItemToQueue, (U32)pxHigherPriorityTaskWoken, xCopyPosition) #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ) SEGGER_SYSVIEW_RecordU32x4(apiFastID_OFFSET + apiID_XQUEUEGENERICSENDFROMISR, SEGGER_SYSVIEW_ShrinkId((U32)pxQueue), (U32)pvItemToQueue, (U32)pxHigherPriorityTaskWoken, xCopyPosition) @@ -338,35 +297,37 @@ define away all of the tracing macros. // // Define INCLUDE_xTaskGetIdleTaskHandle as 1 in FreeRTOSConfig.h to allow identification of Idle state. // -#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) +// SMP FreeRTOS uses unpinned IDLE tasks, so sometimes IDEL0 runs on CPU1, IDLE1 runs on CPU0 and so on. +// So IDLE state detection based on 'xTaskGetIdleTaskHandle' does not work for SMP kernel. +// We could compare current task handle with every element of the array returned by 'xTaskGetIdleTaskHandle', +// but it deos not seem to be efficient enough to be worth of making code more complex and less readabl. +// So always use task name comparison mechanism for SMP kernel. +#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 && !defined(CONFIG_FREERTOS_SMP)) #define traceTASK_SWITCHED_IN() if(prvGetTCBFromHandle(NULL) == xTaskGetIdleTaskHandle()) { \ SEGGER_SYSVIEW_OnIdle(); \ } else { \ - SEGGER_SYSVIEW_OnTaskStartExec((U32)pxCurrentTCB[esp_cpu_get_core_id()]); \ + SEGGER_SYSVIEW_OnTaskStartExec((U32)prvGetTCBFromHandle(NULL)); \ } #else #define traceTASK_SWITCHED_IN() { \ - if (memcmp(pxCurrentTCB[esp_cpu_get_core_id()]->pcTaskName, "IDLE", 5) != 0) { \ - SEGGER_SYSVIEW_OnTaskStartExec((U32)pxCurrentTCB[esp_cpu_get_core_id()]); \ + if (memcmp(prvGetTCBFromHandle(NULL)->pcTaskName, "IDLE", 4) != 0) { \ + SEGGER_SYSVIEW_OnTaskStartExec((U32)prvGetTCBFromHandle(NULL)); \ } else { \ SEGGER_SYSVIEW_OnIdle(); \ } \ } #endif - #define traceMOVED_TASK_TO_READY_STATE(pxTCB) SEGGER_SYSVIEW_OnTaskStartReady((U32)pxTCB) #define traceREADDED_TASK_TO_READY_STATE(pxTCB) -#define traceMOVED_TASK_TO_DELAYED_LIST() SEGGER_SYSVIEW_OnTaskStopReady((U32)pxCurrentTCB[esp_cpu_get_core_id()], (1u << 2)) -#define traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST() SEGGER_SYSVIEW_OnTaskStopReady((U32)pxCurrentTCB[esp_cpu_get_core_id()], (1u << 2)) +#define traceMOVED_TASK_TO_DELAYED_LIST() SEGGER_SYSVIEW_OnTaskStopReady((U32)prvGetTCBFromHandle(NULL)], (1u << 2)) +#define traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST() SEGGER_SYSVIEW_OnTaskStopReady((U32)prvGetTCBFromHandle(NULL)], (1u << 2)) #define traceMOVED_TASK_TO_SUSPENDED_LIST(pxTCB) SEGGER_SYSVIEW_OnTaskStopReady((U32)pxTCB, ((3u << 3) | 3)) #define traceISR_EXIT_TO_SCHEDULER() SEGGER_SYSVIEW_RecordExitISRToScheduler() #define traceISR_EXIT() SEGGER_SYSVIEW_RecordExitISR() #define traceISR_ENTER(_n_) SEGGER_SYSVIEW_RecordEnterISR(_n_) -#endif // CONFIG_FREERTOS_SMP - /********************************************************************* * * API functions diff --git a/components/app_update/CMakeLists.txt b/components/app_update/CMakeLists.txt index 789799ed7c..2fb1be8cdb 100644 --- a/components/app_update/CMakeLists.txt +++ b/components/app_update/CMakeLists.txt @@ -1,31 +1,8 @@ -idf_component_register(SRCS "esp_ota_ops.c" - "esp_app_desc.c" +idf_component_register(SRCS "esp_ota_ops.c" "esp_ota_app_desc.c" INCLUDE_DIRS "include" - REQUIRES spi_flash partition_table bootloader_support + REQUIRES spi_flash partition_table bootloader_support esp_app_format PRIV_REQUIRES esptool_py efuse) -# esp_app_desc structure is added as an undefined symbol because otherwise the -# linker will ignore this structure as it has no other files depending on it. -target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_app_desc") - -if(CONFIG_APP_PROJECT_VER_FROM_CONFIG) - # Ignore current PROJECT_VER (which was set in __project_get_revision()). - # Gets the version from the CONFIG_APP_PROJECT_VER. - idf_build_set_property(PROJECT_VER "${CONFIG_APP_PROJECT_VER}") -endif() - -# cut PROJECT_VER and PROJECT_NAME to required 32 characters. -idf_build_get_property(project_ver PROJECT_VER) -idf_build_get_property(project_name PROJECT_NAME) -string(SUBSTRING "${project_ver}" 0 31 PROJECT_VER_CUT) -string(SUBSTRING "${project_name}" 0 31 PROJECT_NAME_CUT) -message(STATUS "App \"${PROJECT_NAME_CUT}\" version: ${PROJECT_VER_CUT}") - -set_source_files_properties( - SOURCE "esp_app_desc.c" - PROPERTIES COMPILE_DEFINITIONS - "PROJECT_VER=\"${PROJECT_VER_CUT}\"; PROJECT_NAME=\"${PROJECT_NAME_CUT}\"") - if(NOT BOOTLOADER_BUILD) partition_table_get_partition_info(otadata_offset "--partition-type data --partition-subtype ota" "offset") partition_table_get_partition_info(otadata_size "--partition-type data --partition-subtype ota" "size") diff --git a/components/app_update/esp_ota_app_desc.c b/components/app_update/esp_ota_app_desc.c new file mode 100644 index 0000000000..70774d50e0 --- /dev/null +++ b/components/app_update/esp_ota_app_desc.c @@ -0,0 +1,21 @@ +/* + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "esp_ota_ops.h" +#include "esp_attr.h" +#include "sdkconfig.h" + +const esp_app_desc_t *esp_ota_get_app_description(void) +{ + return esp_app_get_description(); +} + +int IRAM_ATTR esp_ota_get_app_elf_sha256(char* dst, size_t size) +{ + return esp_app_get_elf_sha256(dst, size); +} diff --git a/components/app_update/esp_ota_ops.c b/components/app_update/esp_ota_ops.c index a1bfe77cc8..eda7f97260 100644 --- a/components/app_update/esp_ota_ops.c +++ b/components/app_update/esp_ota_ops.c @@ -651,8 +651,14 @@ esp_err_t esp_ota_get_partition_description(const esp_partition_t *partition, es #ifdef CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK static esp_err_t esp_ota_set_anti_rollback(void) { - const esp_app_desc_t *app_desc = esp_ota_get_app_description(); - return esp_efuse_update_secure_version(app_desc->secure_version); + const esp_partition_t* partition = esp_ota_get_running_partition(); + esp_app_desc_t app_desc = {0}; + + esp_err_t err = esp_ota_get_partition_description(partition, &app_desc); + if (err == ESP_OK) { + return esp_efuse_update_secure_version(app_desc.secure_version); + } + return err; } #endif diff --git a/components/app_update/include/esp_ota_ops.h b/components/app_update/include/esp_ota_ops.h index 355c61f2f5..1058c728ae 100644 --- a/components/app_update/include/esp_ota_ops.h +++ b/components/app_update/include/esp_ota_ops.h @@ -12,7 +12,7 @@ #include #include "esp_err.h" #include "esp_partition.h" -#include "esp_image_format.h" +#include "esp_app_desc.h" #include "esp_flash_partitions.h" #include "soc/soc_caps.h" @@ -44,20 +44,27 @@ typedef uint32_t esp_ota_handle_t; /** * @brief Return esp_app_desc structure. This structure includes app version. * + * @note This API is present for backward compatibility reasons. Alternative function + * with the same functionality is `esp_app_get_description` + * * Return description for running app. * @return Pointer to esp_app_desc structure. */ -const esp_app_desc_t *esp_ota_get_app_description(void); +const esp_app_desc_t *esp_ota_get_app_description(void) __attribute__((deprecated("Please use esp_app_get_description instead"))); /** * @brief Fill the provided buffer with SHA256 of the ELF file, formatted as hexadecimal, null-terminated. * If the buffer size is not sufficient to fit the entire SHA256 in hex plus a null terminator, * the largest possible number of bytes will be written followed by a null. + * +* @note This API is present for backward compatibility reasons. Alternative function + * with the same functionality is `esp_app_get_elf_sha256` + * * @param dst Destination buffer * @param size Size of the buffer * @return Number of bytes written to dst (including null terminator) */ -int esp_ota_get_app_elf_sha256(char* dst, size_t size); +int esp_ota_get_app_elf_sha256(char* dst, size_t size) __attribute__((deprecated("Please use esp_app_get_elf_sha256 instead"))); /** * @brief Commence an OTA update writing to the specified partition. diff --git a/components/app_update/test/test_ota_ops.c b/components/app_update/test/test_ota_ops.c index 9b283b64ed..b72142d6e1 100644 --- a/components/app_update/test/test_ota_ops.c +++ b/components/app_update/test/test_ota_ops.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,7 +13,6 @@ #include #include #include -#include "bootloader_common.h" /* These OTA tests currently don't assume an OTA partition exists on the device, so they're a bit limited @@ -91,6 +90,8 @@ TEST_CASE("esp_ota_get_next_update_partition logic", "[ota]") TEST_CASE("esp_ota_get_partition_description", "[ota]") { + extern esp_err_t bootloader_common_get_partition_description(const esp_partition_pos_t *partition, esp_app_desc_t *app_desc); + const esp_partition_t *running = esp_ota_get_running_partition(); TEST_ASSERT_NOT_NULL(running); esp_app_desc_t app_desc1, app_desc2; diff --git a/components/bootloader/Kconfig.projbuild b/components/bootloader/Kconfig.projbuild index 0318ef1063..3bfbb05d8d 100644 --- a/components/bootloader/Kconfig.projbuild +++ b/components/bootloader/Kconfig.projbuild @@ -366,7 +366,7 @@ menu "Bootloader config" # only available if both Secure Boot and Check Signature on Boot are disabled depends on !SECURE_SIGNED_ON_BOOT default n - select BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP + select BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP if SOC_RTC_FAST_MEM_SUPPORTED select BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON help Selecting this option prevents the bootloader from ever validating the app image before @@ -403,7 +403,6 @@ menu "Bootloader config" config BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE hex "Size in bytes for custom purposes" - range 0 0x10 default 0 depends on BOOTLOADER_CUSTOM_RESERVE_RTC help diff --git a/components/bootloader/project_include.cmake b/components/bootloader/project_include.cmake index 5dcb18cd48..2f3b3eb8a8 100644 --- a/components/bootloader/project_include.cmake +++ b/components/bootloader/project_include.cmake @@ -11,8 +11,9 @@ endif() # idf_build_get_property(build_dir BUILD_DIR) set(BOOTLOADER_BUILD_DIR "${build_dir}/bootloader") +set(BOOTLOADER_ELF_FILE "${BOOTLOADER_BUILD_DIR}/bootloader.elf") set(bootloader_binary_files - "${BOOTLOADER_BUILD_DIR}/bootloader.elf" + "${BOOTLOADER_ELF_FILE}" "${BOOTLOADER_BUILD_DIR}/bootloader.bin" "${BOOTLOADER_BUILD_DIR}/bootloader.map" ) diff --git a/components/bootloader/subproject/CMakeLists.txt b/components/bootloader/subproject/CMakeLists.txt index 5428ec2463..2daf4d90eb 100644 --- a/components/bootloader/subproject/CMakeLists.txt +++ b/components/bootloader/subproject/CMakeLists.txt @@ -57,7 +57,7 @@ idf_build_set_property(__COMPONENT_REQUIRES_COMMON "${common_req}") idf_build_set_property(__OUTPUT_SDKCONFIG 0) project(bootloader) -idf_build_set_property(COMPILE_DEFINITIONS "-DBOOTLOADER_BUILD=1" APPEND) +idf_build_set_property(COMPILE_DEFINITIONS "BOOTLOADER_BUILD=1" APPEND) idf_build_set_property(COMPILE_OPTIONS "-fno-stack-protector" APPEND) idf_component_get_property(main_args esptool_py FLASH_ARGS) diff --git a/components/bootloader/subproject/main/ld/esp32c6/bootloader.ld b/components/bootloader/subproject/main/ld/esp32c6/bootloader.ld new file mode 100644 index 0000000000..5702fd715c --- /dev/null +++ b/components/bootloader/subproject/main/ld/esp32c6/bootloader.ld @@ -0,0 +1,243 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/** Simplified memory map for the bootloader. + * Make sure the bootloader can load into main memory without overwriting itself. + * + * ESP32-C6 ROM static data usage is as follows: + * - 0x4086ad08 - 0x4087c610: Shared buffers, used in UART/USB/SPI download mode only + * - 0x4087c610 - 0x4087e610: PRO CPU stack, can be reclaimed as heap after RTOS startup + * - 0x4087e610 - 0x40880000: ROM .bss and .data (not easily reclaimable) + * + * The 2nd stage bootloader can take space up to the end of ROM shared + * buffers area (0x4087c610). + */ + +/* The offset between Dbus and Ibus. Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. */ +iram_dram_offset = 0x0; + +/* We consider 0x4087c610 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg, + * and work out iram_seg and iram_loader_seg addresses from there, backwards. + */ + +/* These lengths can be adjusted, if necessary: */ +bootloader_usable_dram_end = 0x4087c610; +bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */ +bootloader_dram_seg_len = 0x5000; +bootloader_iram_loader_seg_len = 0x7000; +bootloader_iram_seg_len = 0x2000; + +/* Start of the lower region is determined by region size and the end of the higher region */ +bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead; +bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len; +bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len + iram_dram_offset; +bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len; + +MEMORY +{ + iram_seg (RWX) : org = bootloader_iram_seg_start, len = bootloader_iram_seg_len + iram_loader_seg (RWX) : org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len + dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len +} + +/* Default entry point: */ +ENTRY(call_start_cpu0); + +SECTIONS +{ + + .iram_loader.text : + { + . = ALIGN (16); + _loader_text_start = ABSOLUTE(.); + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */ + *liblog.a:(.literal .text .literal.* .text.*) + *libgcc.a:(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) + *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) + *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*) + *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*) + *libspi_flash.a:*.*(.literal .text .literal.* .text.*) + *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) + *libhal.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libhal.a:cache_hal.*(.literal .text .literal.* .text.*) + *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*) + *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) + *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) + *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) + *libefuse.a:*.*(.literal .text .literal.* .text.*) + *(.fini.literal) + *(.fini) + *(.gnu.version) + _loader_text_end = ABSOLUTE(.); + } > iram_loader_seg + + .iram.text : + { + . = ALIGN (16); + *(.entry.text) + *(.init.literal) + *(.init) + } > iram_seg + + + /* Shared RAM */ + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + _dram_start = ABSOLUTE(.); + _bss_start = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + _bss_end = ABSOLUTE(.); + } > dram_seg + + .dram0.data : + { + _data_start = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + _data_end = ABSOLUTE(.); + } > dram_seg + + .dram0.rodata : + { + _rodata_start = ABSOLUTE(.); + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + *(.rodata1) + *(.sdata2 .sdata2.* .srodata .srodata.*) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + *(.eh_frame) + . = (. + 3) & ~ 3; + /* C++ constructor and destructor tables, properly ordered: */ + __init_array_start = ABSOLUTE(.); + KEEP (*crtbegin.*(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __init_array_end = ABSOLUTE(.); + KEEP (*crtbegin.*(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _rodata_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + _dram_end = ABSOLUTE(.); + } > dram_seg + + .iram.text : + { + _stext = .; + _text_start = ABSOLUTE(.); + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.iram .iram.*) /* catch stray IRAM_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + + /** CPU will try to prefetch up to 16 bytes of + * of instructions. This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + . += 16; + + _text_end = ABSOLUTE(.); + _etext = .; + } > iram_seg + +} + + +/** + * Appendix: Memory Usage of ROM bootloader + * + * 0x4086ad08 ------------------> _dram0_0_start + * | | + * | | + * | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h + * | | + * | | + * 0x4087c610 ------------------> __stack_sentry + * | | + * | | 2. Startup pro cpu stack (freed when IDF app is running) + * | | + * 0x4087e610 ------------------> __stack (pro cpu) + * | | + * | | + * | | 3. Shared memory only used in startup code or nonos/early boot* + * | | (can be freed when IDF runs) + * | | + * | | + * 0x4087f564 ------------------> _dram0_rtos_reserved_start + * | | + * | | + * | | 4. Shared memory used in startup code and when IDF runs + * | | + * | | + * 0x4087fab0 ------------------> _dram0_rtos_reserved_end + * | | + * 0x4087fce8 ------------------> _data_start_interface + * | | + * | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible) + * | | + * 0x40880000 ------------------> _data_end_interface + */ diff --git a/components/bootloader/subproject/main/ld/esp32c6/bootloader.rom.ld b/components/bootloader/subproject/main/ld/esp32c6/bootloader.rom.ld new file mode 100644 index 0000000000..239eb438b4 --- /dev/null +++ b/components/bootloader/subproject/main/ld/esp32c6/bootloader.rom.ld @@ -0,0 +1,6 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* No definition for ESP32-C6 target */ diff --git a/components/bootloader_support/.build-test-rules.yml b/components/bootloader_support/.build-test-rules.yml new file mode 100644 index 0000000000..935c7d342e --- /dev/null +++ b/components/bootloader_support/.build-test-rules.yml @@ -0,0 +1,7 @@ +# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps + +components/bootloader_support/test_apps/rtc_custom_section: + disable: + - if: IDF_TARGET == "esp32c2" + temporary: false + reason: esp32c2 does not have RTC memory diff --git a/components/bootloader_support/CMakeLists.txt b/components/bootloader_support/CMakeLists.txt index 42b8f85f49..cd2e1eac74 100644 --- a/components/bootloader_support/CMakeLists.txt +++ b/components/bootloader_support/CMakeLists.txt @@ -19,7 +19,7 @@ set(srcs if(BOOTLOADER_BUILD) set(include_dirs "include" "bootloader_flash/include" "private_include") - set(priv_requires micro-ecc spi_flash efuse) + set(priv_requires micro-ecc spi_flash efuse esp_app_format) list(APPEND srcs "src/bootloader_init.c" "src/bootloader_clock_loader.c" @@ -37,7 +37,7 @@ else() set(include_dirs "include" "bootloader_flash/include") set(priv_include_dirs "private_include") # heap is required for `heap_memory_layout.h` header - set(priv_requires spi_flash mbedtls efuse app_update heap) + set(priv_requires spi_flash mbedtls efuse heap esp_app_format) endif() if(BOOTLOADER_BUILD) @@ -86,6 +86,15 @@ idf_component_register(SRCS "${srcs}" REQUIRES "${requires}" PRIV_REQUIRES "${priv_requires}") +if(NOT BOOTLOADER_BUILD) + if(CONFIG_SECURE_SIGNED_ON_UPDATE) + if(CONFIG_SECURE_SIGNED_APPS_ECDSA_SCHEME OR CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME OR + CONFIG_SECURE_SIGNED_APPS_ECDSA_V2_SCHEME) + target_link_libraries(${COMPONENT_LIB} PRIVATE idf::app_update) + endif() + endif() +endif() + if(CONFIG_SECURE_SIGNED_APPS AND (CONFIG_SECURE_BOOT_V1_ENABLED OR CONFIG_SECURE_SIGNED_APPS_ECDSA_SCHEME)) if(BOOTLOADER_BUILD) # Whether CONFIG_SECURE_BOOT_BUILD_SIGNED_BINARIES or not, we need verification key to embed diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash.c index da282577a8..321010fba7 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash.c @@ -128,9 +128,9 @@ static const char *TAG = "bootloader_flash"; 50th block for bootloader_flash_read */ #define MMU_BLOCK0_VADDR SOC_DROM_LOW -#define MMU_SIZE (0x320000) -#define MMU_BLOCK50_VADDR (MMU_BLOCK0_VADDR + MMU_SIZE) -#define FLASH_READ_VADDR MMU_BLOCK50_VADDR +#define MMAP_MMU_SIZE (0x320000) +#define MMU_BLOCK50_VADDR (MMU_BLOCK0_VADDR + MMAP_MMU_SIZE) +#define FLASH_READ_VADDR MMU_BLOCK50_VADDR #else // !CONFIG_IDF_TARGET_ESP32 @@ -139,15 +139,15 @@ static const char *TAG = "bootloader_flash"; */ #define MMU_BLOCK0_VADDR SOC_DROM_LOW #ifdef SOC_MMU_PAGE_SIZE_CONFIGURABLE -#define MMU_SIZE (DRAM0_CACHE_ADDRESS_HIGH(SPI_FLASH_MMU_PAGE_SIZE) - DRAM0_CACHE_ADDRESS_LOW - SPI_FLASH_MMU_PAGE_SIZE) // This mmu size means that the mmu size to be mapped +#define MMAP_MMU_SIZE (DRAM0_CACHE_ADDRESS_HIGH(SPI_FLASH_MMU_PAGE_SIZE) - DRAM0_CACHE_ADDRESS_LOW - SPI_FLASH_MMU_PAGE_SIZE) // This mmu size means that the mmu size to be mapped #else -#define MMU_SIZE (DRAM0_CACHE_ADDRESS_HIGH - DRAM0_CACHE_ADDRESS_LOW - SPI_FLASH_MMU_PAGE_SIZE) // This mmu size means that the mmu size to be mapped +#define MMAP_MMU_SIZE (DRAM0_CACHE_ADDRESS_HIGH - DRAM0_CACHE_ADDRESS_LOW - SPI_FLASH_MMU_PAGE_SIZE) // This mmu size means that the mmu size to be mapped #endif -#define MMU_BLOCK63_VADDR (MMU_BLOCK0_VADDR + MMU_SIZE) +#define MMU_BLOCK63_VADDR (MMU_BLOCK0_VADDR + MMAP_MMU_SIZE) #define FLASH_READ_VADDR MMU_BLOCK63_VADDR #endif -#define MMU_FREE_PAGES (MMU_SIZE / FLASH_BLOCK_SIZE) +#define MMU_FREE_PAGES (MMAP_MMU_SIZE / CONFIG_MMU_PAGE_SIZE) static bool mapped; @@ -169,7 +169,7 @@ const void *bootloader_mmap(uint32_t src_paddr, uint32_t size) ESP_EARLY_LOGE(TAG, "tried to bootloader_mmap twice"); return NULL; /* can't map twice */ } - if (size > MMU_SIZE) { + if (size > MMAP_MMU_SIZE) { ESP_EARLY_LOGE(TAG, "bootloader_mmap excess size %x", size); return NULL; } @@ -769,10 +769,8 @@ esp_err_t IRAM_ATTR bootloader_flash_reset_chip(void) bootloader_execute_flash_command(0x05, 0, 0, 0); #if CONFIG_IDF_TARGET_ESP32 if (SPI1.ext2.st != 0) -#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 - if (SPIMEM1.fsm.st != 0) #else - if (SPIMEM1.fsm.spi0_mst_st != 0) + if (!spimem_flash_ll_host_idle(&SPIMEM1)) #endif { return ESP_FAIL; diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c new file mode 100644 index 0000000000..7220370f7b --- /dev/null +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c @@ -0,0 +1,69 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include "string.h" +#include "sdkconfig.h" +#include "esp_err.h" +#include "esp_log.h" +#include "esp32c6/rom/gpio.h" +#include "esp32c6/rom/spi_flash.h" +#include "esp32c6/rom/efuse.h" +#include "soc/gpio_periph.h" +#include "soc/efuse_reg.h" +#include "soc/spi_reg.h" +#include "soc/spi_mem_reg.h" +#include "soc/soc_caps.h" +#include "flash_qio_mode.h" +#include "bootloader_flash_config.h" +#include "bootloader_common.h" + +void bootloader_flash_update_id() +{ + esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip; + chip->device_id = bootloader_read_flash_id(); +} + +void IRAM_ATTR bootloader_flash_cs_timing_config() +{ + SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S); + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S); +} + +void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr) +{ + uint32_t spi_clk_div = 0; + switch (pfhdr->spi_speed) { + case ESP_IMAGE_SPI_SPEED_DIV_1: + spi_clk_div = 1; + break; + case ESP_IMAGE_SPI_SPEED_DIV_2: + spi_clk_div = 2; + break; + case ESP_IMAGE_SPI_SPEED_DIV_3: + spi_clk_div = 3; + break; + case ESP_IMAGE_SPI_SPEED_DIV_4: + spi_clk_div = 4; + break; + default: + break; + } + esp_rom_spiflash_config_clk(spi_clk_div, 0); +} + +void IRAM_ATTR bootloader_flash_set_dummy_out(void) +{ + REG_SET_BIT(SPI_MEM_CTRL_REG(0), /*SPI_MEM_FDUMMY_OUT |*/ SPI_MEM_D_POL | SPI_MEM_Q_POL); // TODO: IDF-5631 ESP32C6 not have SPI_MEM_FDUMMY_OUT + REG_SET_BIT(SPI_MEM_CTRL_REG(1), /*SPI_MEM_FDUMMY_OUT |*/ SPI_MEM_D_POL | SPI_MEM_Q_POL); // TODO: idf-5631 ESP32C6 not have SPI_MEM_FDUMMY_OUT +} + +void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t *pfhdr) +{ + bootloader_configure_spi_pins(1); + bootloader_flash_set_dummy_out(); +} diff --git a/components/bootloader_support/bootloader_flash/src/flash_qio_mode.c b/components/bootloader_support/bootloader_flash/src/flash_qio_mode.c index 982bd2ddf1..a448a0fb6b 100644 --- a/components/bootloader_support/bootloader_flash/src/flash_qio_mode.c +++ b/components/bootloader_support/bootloader_flash/src/flash_qio_mode.c @@ -11,6 +11,7 @@ #include "bootloader_flash_priv.h" #include "esp_log.h" #include "esp_err.h" +#include "esp_attr.h" #include "esp_rom_spiflash.h" #include "esp_rom_efuse.h" #include "flash_qio_mode.h" @@ -105,8 +106,8 @@ static void s_flash_set_qio_pins(void) const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); int wp_pin = bootloader_flash_get_wp_pin(); esp_rom_spiflash_select_qio_pins(wp_pin, spiconfig); -#elif CONFIG_IDF_TARGET_ESP32C2 - // ESP32C2 doesn't support configure mspi pins. So the second +#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5649 Add a soc_caps + // ESP32C2/ESP32C6 doesn't support configure mspi pins. So the second // parameter is set to 0, means that chip uses default SPI pins // and wp_gpio_num parameter(the first parameter) is ignored. esp_rom_spiflash_select_qio_pins(0, 0); @@ -159,47 +160,47 @@ static esp_err_t enable_qio_mode(bootloader_flash_read_status_fn_t read_status_f return ESP_OK; } -unsigned bootloader_read_status_8b_rdsr(void) +IRAM_ATTR unsigned bootloader_read_status_8b_rdsr(void) { return bootloader_execute_flash_command(CMD_RDSR, 0, 0, 8); } -unsigned bootloader_read_status_8b_rdsr2(void) +IRAM_ATTR unsigned bootloader_read_status_8b_rdsr2(void) { return bootloader_execute_flash_command(CMD_RDSR2, 0, 0, 8); } -unsigned bootloader_read_status_8b_rdsr3(void) +IRAM_ATTR unsigned bootloader_read_status_8b_rdsr3(void) { return bootloader_execute_flash_command(CMD_RDSR3, 0, 0, 8); } -unsigned bootloader_read_status_16b_rdsr_rdsr2(void) +IRAM_ATTR unsigned bootloader_read_status_16b_rdsr_rdsr2(void) { return bootloader_execute_flash_command(CMD_RDSR, 0, 0, 8) | (bootloader_execute_flash_command(CMD_RDSR2, 0, 0, 8) << 8); } -void bootloader_write_status_8b_wrsr(unsigned new_status) +IRAM_ATTR void bootloader_write_status_8b_wrsr(unsigned new_status) { bootloader_execute_flash_command(CMD_WRSR, new_status, 8, 0); } -void bootloader_write_status_8b_wrsr2(unsigned new_status) +IRAM_ATTR void bootloader_write_status_8b_wrsr2(unsigned new_status) { bootloader_execute_flash_command(CMD_WRSR2, new_status, 8, 0); } -void bootloader_write_status_8b_wrsr3(unsigned new_status) +IRAM_ATTR void bootloader_write_status_8b_wrsr3(unsigned new_status) { bootloader_execute_flash_command(CMD_WRSR3, new_status, 8, 0); } -void bootloader_write_status_16b_wrsr(unsigned new_status) +IRAM_ATTR void bootloader_write_status_16b_wrsr(unsigned new_status) { bootloader_execute_flash_command(CMD_WRSR, new_status, 16, 0); } -unsigned bootloader_read_status_8b_xmc25qu64a(void) +IRAM_ATTR unsigned bootloader_read_status_8b_xmc25qu64a(void) { bootloader_execute_flash_command(CMD_OTPEN, 0, 0, 0); /* Enter OTP mode */ esp_rom_spiflash_wait_idle(&g_rom_flashchip); @@ -208,7 +209,7 @@ unsigned bootloader_read_status_8b_xmc25qu64a(void) return read_status; } -void bootloader_write_status_8b_xmc25qu64a(unsigned new_status) +IRAM_ATTR void bootloader_write_status_8b_xmc25qu64a(unsigned new_status) { bootloader_execute_flash_command(CMD_OTPEN, 0, 0, 0); /* Enter OTP mode */ esp_rom_spiflash_wait_idle(&g_rom_flashchip); diff --git a/components/bootloader_support/include/bootloader_common.h b/components/bootloader_support/include/bootloader_common.h index 3237de61c0..6145a72ef8 100644 --- a/components/bootloader_support/include/bootloader_common.h +++ b/components/bootloader_support/include/bootloader_common.h @@ -7,7 +7,6 @@ #pragma once #include "esp_flash_partitions.h" #include "esp_image_format.h" -#include "esp_app_format.h" #ifdef __cplusplus extern "C" { @@ -151,20 +150,6 @@ int bootloader_common_get_active_otadata(esp_ota_select_entry_t *two_otadata); */ int bootloader_common_select_otadata(const esp_ota_select_entry_t *two_otadata, bool *valid_two_otadata, bool max); -/** - * @brief Returns esp_app_desc structure for app partition. This structure includes app version. - * - * Returns a description for the requested app partition. - * @param[in] partition App partition description. - * @param[out] app_desc Structure of info about app. - * @return - * - ESP_OK: Successful. - * - ESP_ERR_INVALID_ARG: The arguments passed are not valid. - * - ESP_ERR_NOT_FOUND: app_desc structure is not found. Magic word is incorrect. - * - ESP_FAIL: mapping is fail. - */ -esp_err_t bootloader_common_get_partition_description(const esp_partition_pos_t *partition, esp_app_desc_t *app_desc); - /** * @brief Get chip package * diff --git a/components/bootloader_support/include/bootloader_memory_utils.h b/components/bootloader_support/include/bootloader_memory_utils.h index f2df0ed227..988749593c 100644 --- a/components/bootloader_support/include/bootloader_memory_utils.h +++ b/components/bootloader_support/include/bootloader_memory_utils.h @@ -69,7 +69,12 @@ inline static bool esp_ptr_in_diram_dram(const void *p) { */ __attribute__((always_inline)) inline static bool esp_ptr_in_diram_iram(const void *p) { +// TODO: IDF-5980 esp32c6 D/I RAM share the same address +#if SOC_DIRAM_IRAM_LOW == SOC_DIRAM_DRAM_LOW + return false; +#else return ((intptr_t)p >= SOC_DIRAM_IRAM_LOW && (intptr_t)p < SOC_DIRAM_IRAM_HIGH); +#endif } /** diff --git a/components/bootloader_support/include/esp_app_format.h b/components/bootloader_support/include/esp_app_format.h index a6c4d9b283..7bed35186c 100644 --- a/components/bootloader_support/include/esp_app_format.h +++ b/components/bootloader_support/include/esp_app_format.h @@ -22,6 +22,7 @@ typedef enum { #elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1 ESP_CHIP_ID_ESP32H2 = 0x000A, /*!< chip ID: ESP32-H2 Beta1 */ #endif + ESP_CHIP_ID_ESP32C6 = 0x000D, /*!< chip ID: ESP32-C6 */ ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */ } __attribute__((packed)) esp_chip_id_t; @@ -106,25 +107,3 @@ typedef struct { } esp_image_segment_header_t; #define ESP_IMAGE_MAX_SEGMENTS 16 /*!< Max count of segments in the image. */ - -#define ESP_APP_DESC_MAGIC_WORD 0xABCD5432 /*!< The magic word for the esp_app_desc structure that is in DROM. */ - -/** - * @brief Description about application. - */ -typedef struct { - uint32_t magic_word; /*!< Magic word ESP_APP_DESC_MAGIC_WORD */ - uint32_t secure_version; /*!< Secure version */ - uint32_t reserv1[2]; /*!< reserv1 */ - char version[32]; /*!< Application version */ - char project_name[32]; /*!< Project name */ - char time[16]; /*!< Compile time */ - char date[16]; /*!< Compile date*/ - char idf_ver[32]; /*!< Version IDF */ - uint8_t app_elf_sha256[32]; /*!< sha256 of elf file */ - uint32_t reserv2[20]; /*!< reserv2 */ -} esp_app_desc_t; - -/** @cond */ -_Static_assert(sizeof(esp_app_desc_t) == 256, "esp_app_desc_t should be 256 bytes"); -/** @endcond */ diff --git a/components/bootloader_support/include/esp_image_format.h b/components/bootloader_support/include/esp_image_format.h index 1db6244253..4c8413befe 100644 --- a/components/bootloader_support/include/esp_image_format.h +++ b/components/bootloader_support/include/esp_image_format.h @@ -53,8 +53,14 @@ typedef struct { uint32_t crc; /*!< Check sum crc32 */ } rtc_retain_mem_t; + +_Static_assert(offsetof(rtc_retain_mem_t, crc) == sizeof(rtc_retain_mem_t) - sizeof(uint32_t), "CRC field must be the last field of rtc_retain_mem_t structure"); + #ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC _Static_assert(CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE % 4 == 0, "CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE must be a multiple of 4 bytes"); +/* The custom field must be the penultimate field */ +_Static_assert(offsetof(rtc_retain_mem_t, custom) == sizeof(rtc_retain_mem_t) - sizeof(uint32_t) - CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE, + "custom field in rtc_retain_mem_t structure must be the field before the CRC one"); #endif #if defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP) || defined(CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC) diff --git a/components/bootloader_support/private_include/bootloader_signature.h b/components/bootloader_support/private_include/bootloader_signature.h index fceb9eb49a..9bea96ff7c 100644 --- a/components/bootloader_support/private_include/bootloader_signature.h +++ b/components/bootloader_support/private_include/bootloader_signature.h @@ -21,6 +21,8 @@ #include "esp32h2/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/secure_boot.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/secure_boot.h" #endif #if !CONFIG_IDF_TARGET_ESP32 || CONFIG_ESP32_REV_MIN_3 diff --git a/components/bootloader_support/src/bootloader_clock_init.c b/components/bootloader_support/src/bootloader_clock_init.c index 35b1e08952..943b597e74 100644 --- a/components/bootloader_support/src/bootloader_clock_init.c +++ b/components/bootloader_support/src/bootloader_clock_init.c @@ -7,7 +7,16 @@ #include "soc/soc.h" #include "soc/rtc.h" #include "hal/efuse_hal.h" + +#if !CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645 #include "soc/rtc_cntl_reg.h" +#else +#include "soc/lp_wdt_reg.h" +#include "soc/lp_timer_reg.h" +#include "soc/lp_analog_peri_reg.h" +#include "soc/pmu_reg.h" +#endif + #if CONFIG_IDF_TARGET_ESP32 #include "hal/clk_tree_ll.h" #endif @@ -65,6 +74,24 @@ __attribute__((weak)) void bootloader_clock_configure(void) } #endif // CONFIG_ESP_SYSTEM_RTC_EXT_XTAL +// TODO: IDF-5645 +#if CONFIG_IDF_TARGET_ESP32C6 + // CLR ENA + CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_SUPER_WDT_INT_ENA); /* SWD */ + CLEAR_PERI_REG_MASK(LP_TIMER_LP_INT_ENA_REG, LP_TIMER_MAIN_TIMER_LP_INT_ENA); /* MAIN_TIMER */ + CLEAR_PERI_REG_MASK(LP_ANALOG_PERI_LP_ANA_LP_INT_ENA_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA); /* BROWN_OUT */ + CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_LP_WDT_INT_ENA); /* WDT */ + CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_WAKEUP_INT_ENA); /* SLP_REJECT */ + CLEAR_PERI_REG_MASK(PMU_SOC_SLEEP_REJECT_INT_ENA, PMU_SOC_SLEEP_REJECT_INT_ENA); /* SLP_WAKEUP */ + // SET CLR + SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_SUPER_WDT_INT_CLR); /* SWD */ + SET_PERI_REG_MASK(LP_TIMER_LP_INT_CLR_REG, LP_TIMER_MAIN_TIMER_LP_INT_CLR); /* MAIN_TIMER */ + SET_PERI_REG_MASK(LP_ANALOG_PERI_LP_ANA_LP_INT_CLR_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR); /* BROWN_OUT */ + SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_LP_WDT_INT_CLR); /* WDT */ + SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_WAKEUP_INT_CLR); /* SLP_REJECT */ + SET_PERI_REG_MASK(PMU_SOC_SLEEP_REJECT_INT_CLR, PMU_SOC_SLEEP_REJECT_INT_CLR); /* SLP_WAKEUP */ +#else REG_WRITE(RTC_CNTL_INT_ENA_REG, 0); REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX); +#endif } diff --git a/components/bootloader_support/src/bootloader_common_loader.c b/components/bootloader_support/src/bootloader_common_loader.c index 3d9f5c857d..53f43bd694 100644 --- a/components/bootloader_support/src/bootloader_common_loader.c +++ b/components/bootloader_support/src/bootloader_common_loader.c @@ -112,34 +112,12 @@ int bootloader_common_select_otadata(const esp_ota_select_entry_t *two_otadata, return active_otadata; } -esp_err_t bootloader_common_get_partition_description(const esp_partition_pos_t *partition, esp_app_desc_t *app_desc) -{ - if (partition == NULL || app_desc == NULL || partition->offset == 0) { - return ESP_ERR_INVALID_ARG; - } - - const uint32_t app_desc_offset = sizeof(esp_image_header_t) + sizeof(esp_image_segment_header_t); - const uint32_t mmap_size = app_desc_offset + sizeof(esp_app_desc_t); - const uint8_t *image = bootloader_mmap(partition->offset, mmap_size); - if (image == NULL) { - ESP_LOGE(TAG, "bootloader_mmap(0x%x, 0x%x) failed", partition->offset, mmap_size); - return ESP_FAIL; - } - - memcpy(app_desc, image + app_desc_offset, sizeof(esp_app_desc_t)); - bootloader_munmap(image); - - if (app_desc->magic_word != ESP_APP_DESC_MAGIC_WORD) { - return ESP_ERR_NOT_FOUND; - } - - return ESP_OK; -} - #if defined( CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP ) || defined( CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC ) #define RTC_RETAIN_MEM_ADDR (SOC_RTC_DRAM_HIGH - sizeof(rtc_retain_mem_t)) +_Static_assert(RTC_RETAIN_MEM_ADDR >= SOC_RTC_DRAM_LOW, "rtc_retain_mem_t structure size is bigger than the RTC memory size. Consider reducing RTC reserved memory size."); + rtc_retain_mem_t *const rtc_retain_mem = (rtc_retain_mem_t *)RTC_RETAIN_MEM_ADDR; #ifndef BOOTLOADER_BUILD @@ -152,17 +130,28 @@ rtc_retain_mem_t *const rtc_retain_mem = (rtc_retain_mem_t *)RTC_RETAIN_MEM_ADDR SOC_RESERVE_MEMORY_REGION(RTC_RETAIN_MEM_ADDR, RTC_RETAIN_MEM_ADDR + sizeof(rtc_retain_mem_t), rtc_retain_mem); #endif +static uint32_t rtc_retain_mem_size(void) { +#ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC + /* A custom memory has been reserved by the user, do not consider this memory into CRC calculation as it may change without + * the have the user updating the CRC. Return the offset of the custom field, which is equivalent to size of the structure + * minus the size of everything after (including) `custom` */ + return offsetof(rtc_retain_mem_t, custom); +#else + return sizeof(rtc_retain_mem_t) - sizeof(rtc_retain_mem->crc); +#endif +} + static bool check_rtc_retain_mem(void) { - return esp_rom_crc32_le(UINT32_MAX, (uint8_t*)rtc_retain_mem, sizeof(rtc_retain_mem_t) - sizeof(rtc_retain_mem->crc)) == rtc_retain_mem->crc && rtc_retain_mem->crc != UINT32_MAX; + return esp_rom_crc32_le(UINT32_MAX, (uint8_t*)rtc_retain_mem, rtc_retain_mem_size()) == rtc_retain_mem->crc && rtc_retain_mem->crc != UINT32_MAX; } static void update_rtc_retain_mem_crc(void) { - rtc_retain_mem->crc = esp_rom_crc32_le(UINT32_MAX, (uint8_t*)rtc_retain_mem, sizeof(rtc_retain_mem_t) - sizeof(rtc_retain_mem->crc)); + rtc_retain_mem->crc = esp_rom_crc32_le(UINT32_MAX, (uint8_t*)rtc_retain_mem, rtc_retain_mem_size()); } -void bootloader_common_reset_rtc_retain_mem(void) +NOINLINE_ATTR void bootloader_common_reset_rtc_retain_mem(void) { #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wstringop-overflow" diff --git a/components/bootloader_support/src/bootloader_console.c b/components/bootloader_support/src/bootloader_console.c index 85e4aa8027..d63e63a638 100644 --- a/components/bootloader_support/src/bootloader_console.c +++ b/components/bootloader_support/src/bootloader_console.c @@ -28,6 +28,9 @@ #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/ets_sys.h" #include "esp32c2/rom/uart.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/ets_sys.h" +#include "esp32c6/rom/uart.h" #endif #include "esp_rom_gpio.h" #include "esp_rom_uart.h" diff --git a/components/bootloader_support/src/bootloader_efuse.c b/components/bootloader_support/src/bootloader_efuse.c index ea22a524a6..cf3e49ed76 100644 --- a/components/bootloader_support/src/bootloader_efuse.c +++ b/components/bootloader_support/src/bootloader_efuse.c @@ -30,6 +30,9 @@ int bootloader_clock_get_rated_freq_mhz(void) #elif CONFIG_IDF_TARGET_ESP32H2 return 96; +#elif CONFIG_IDF_TARGET_ESP32C6 + return 160; + #elif CONFIG_IDF_TARGET_ESP32S2 return 240; diff --git a/components/bootloader_support/src/bootloader_init.c b/components/bootloader_support/src/bootloader_init.c index b4f112e383..511de79b40 100644 --- a/components/bootloader_support/src/bootloader_init.c +++ b/components/bootloader_support/src/bootloader_init.c @@ -58,27 +58,31 @@ void bootloader_config_wdt(void) * protect the remainder of the bootloader process. */ //Disable RWDT flashboot protection. - wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; - wdt_hal_write_protect_disable(&rtc_wdt_ctx); - wdt_hal_set_flashboot_en(&rtc_wdt_ctx, false); - wdt_hal_write_protect_enable(&rtc_wdt_ctx); +#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5653 + wdt_hal_context_t rwdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &LP_WDT}; +#else + wdt_hal_context_t rwdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; +#endif + wdt_hal_write_protect_disable(&rwdt_ctx); + wdt_hal_set_flashboot_en(&rwdt_ctx, false); + wdt_hal_write_protect_enable(&rwdt_ctx); #ifdef CONFIG_BOOTLOADER_WDT_ENABLE //Initialize and start RWDT to protect the for bootloader if configured to do so ESP_LOGD(TAG, "Enabling RTCWDT(%d ms)", CONFIG_BOOTLOADER_WDT_TIME_MS); - wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false); + wdt_hal_init(&rwdt_ctx, WDT_RWDT, 0, false); uint32_t stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000); - wdt_hal_write_protect_disable(&rtc_wdt_ctx); - wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC); - wdt_hal_enable(&rtc_wdt_ctx); - wdt_hal_write_protect_enable(&rtc_wdt_ctx); + wdt_hal_write_protect_disable(&rwdt_ctx); + wdt_hal_config_stage(&rwdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC); + wdt_hal_enable(&rwdt_ctx); + wdt_hal_write_protect_enable(&rwdt_ctx); #endif //Disable MWDT0 flashboot protection. But only after we've enabled the RWDT first so that there's not gap in WDT protection. - wdt_hal_context_t wdt_ctx = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0}; - wdt_hal_write_protect_disable(&wdt_ctx); - wdt_hal_set_flashboot_en(&wdt_ctx, false); - wdt_hal_write_protect_enable(&wdt_ctx); + wdt_hal_context_t mwdt_ctx = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0}; + wdt_hal_write_protect_disable(&mwdt_ctx); + wdt_hal_set_flashboot_en(&mwdt_ctx, false); + wdt_hal_write_protect_enable(&mwdt_ctx); } void bootloader_enable_random(void) @@ -91,6 +95,6 @@ void bootloader_print_banner(void) { ESP_LOGI(TAG, "ESP-IDF %s 2nd stage bootloader", IDF_VER); #ifndef CONFIG_APP_REPRODUCIBLE_BUILD - ESP_LOGI(TAG, "compile time " __TIME__); + ESP_LOGI(TAG, "compile time " __DATE__ " " __TIME__); #endif } diff --git a/components/bootloader_support/src/bootloader_mem.c b/components/bootloader_support/src/bootloader_mem.c index 1b45c2b5c7..397d1b47d7 100644 --- a/components/bootloader_support/src/bootloader_mem.c +++ b/components/bootloader_support/src/bootloader_mem.c @@ -12,8 +12,21 @@ #include "bootloader_mem.h" #include "esp_cpu.h" +#if CONFIG_IDF_TARGET_ESP32C6 +#include "soc/hp_apm_reg.h" +#include "soc/lp_apm_reg.h" +#include "soc/lp_apm0_reg.h" +#endif + void bootloader_init_mem(void) { +#if CONFIG_IDF_TARGET_ESP32C6 + // disable apm filter // TODO: IDF-5909 + REG_WRITE(LP_APM_FUNC_CTRL_REG, 0); + REG_WRITE(LP_APM0_FUNC_CTRL_REG, 0); + REG_WRITE(HP_APM_FUNC_CTRL_REG, 0); +#endif + #ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE // protect memory region esp_cpu_configure_region_protection(); diff --git a/components/bootloader_support/src/bootloader_panic.c b/components/bootloader_support/src/bootloader_panic.c index 77c2c55bc5..6cff254ce6 100644 --- a/components/bootloader_support/src/bootloader_panic.c +++ b/components/bootloader_support/src/bootloader_panic.c @@ -12,7 +12,11 @@ void __assert_func(const char *file, int line, const char *func, const char *expr) { + +#if !CONFIG_OPTIMIZATION_ASSERTIONS_SILENT esp_rom_printf("Assert failed in %s, %s:%d (%s)\r\n", func, file, line, expr); +#endif + while (1) { } } diff --git a/components/bootloader_support/src/bootloader_random_esp32c6.c b/components/bootloader_support/src/bootloader_random_esp32c6.c new file mode 100644 index 0000000000..378e84744e --- /dev/null +++ b/components/bootloader_support/src/bootloader_random_esp32c6.c @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "sdkconfig.h" +#include "bootloader_random.h" +#include "esp_log.h" + +static const char *TAG = "bootloader_random"; + +void bootloader_random_enable(void) +{ + // TODO: IDF-5352 + ESP_EARLY_LOGW(TAG, "bootloader_random_enable() has not been implemented yet"); +} + +void bootloader_random_disable(void) +{ + // TODO: IDF-5352 + ESP_EARLY_LOGW(TAG, "bootloader_random_enable() has not been implemented yet"); +} diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c index 5ef053ce87..7e094426bd 100644 --- a/components/bootloader_support/src/bootloader_utility.c +++ b/components/bootloader_support/src/bootloader_utility.c @@ -41,6 +41,13 @@ #include "esp32c2/rom/uart.h" #include "esp32c2/rom/gpio.h" #include "esp32c2/rom/secure_boot.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/efuse.h" +#include "esp32c6/rom/crc.h" +#include "esp32c6/rom/rtc.h" +#include "esp32c6/rom/uart.h" +#include "esp32c6/rom/gpio.h" +#include "esp32c6/rom/secure_boot.h" #else // CONFIG_IDF_TARGET_* #error "Unsupported IDF_TARGET" @@ -60,6 +67,7 @@ #include "esp_cpu.h" #include "esp_image_format.h" +#include "esp_app_desc.h" #include "esp_secure_boot.h" #include "esp_flash_encrypt.h" #include "esp_flash_partitions.h" @@ -119,6 +127,31 @@ static esp_err_t read_otadata(const esp_partition_pos_t *ota_info, esp_ota_selec return ESP_OK; } +esp_err_t bootloader_common_get_partition_description(const esp_partition_pos_t *partition, esp_app_desc_t *app_desc) +{ + if (partition == NULL || app_desc == NULL || partition->offset == 0) { + return ESP_ERR_INVALID_ARG; + } + + const uint32_t app_desc_offset = sizeof(esp_image_header_t) + sizeof(esp_image_segment_header_t); + const uint32_t mmap_size = app_desc_offset + sizeof(esp_app_desc_t); + const uint8_t *image = bootloader_mmap(partition->offset, mmap_size); + if (image == NULL) { + ESP_LOGE(TAG, "bootloader_mmap(0x%x, 0x%x) failed", partition->offset, mmap_size); + return ESP_FAIL; + } + + memcpy(app_desc, image + app_desc_offset, sizeof(esp_app_desc_t)); + bootloader_munmap(image); + + if (app_desc->magic_word != ESP_APP_DESC_MAGIC_WORD) { + return ESP_ERR_NOT_FOUND; + } + + return ESP_OK; +} + + bool bootloader_utility_load_partition_table(bootloader_state_t *bs) { const esp_partition_info_t *partitions; @@ -838,7 +871,7 @@ void bootloader_reset(void) #ifdef BOOTLOADER_BUILD bootloader_atexit(); esp_rom_delay_us(1000); /* Allow last byte to leave FIFO */ - REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); + esp_rom_software_reset_system(); while (1) { } /* This line will never be reached, used to keep gcc happy */ #else abort(); /* This function should really not be called from application code */ diff --git a/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c b/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c new file mode 100644 index 0000000000..8c104aa34a --- /dev/null +++ b/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c @@ -0,0 +1,344 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include "sdkconfig.h" +#include "esp_attr.h" +#include "esp_log.h" +#include "esp_image_format.h" +#include "flash_qio_mode.h" +#include "esp_rom_gpio.h" +#include "esp_rom_efuse.h" +#include "esp_rom_uart.h" +#include "esp_rom_sys.h" +#include "esp_rom_spiflash.h" +#include "soc/gpio_sig_map.h" +#include "soc/io_mux_reg.h" +#include "soc/assist_debug_reg.h" +#include "esp_cpu.h" +#include "soc/rtc.h" +#include "soc/spi_periph.h" +#include "soc/extmem_reg.h" +#include "soc/io_mux_reg.h" +#include "soc/pcr_reg.h" +#include "esp32c6/rom/efuse.h" +#include "esp32c6/rom/ets_sys.h" +#include "bootloader_common.h" +#include "bootloader_init.h" +#include "bootloader_clock.h" +#include "bootloader_flash_config.h" +#include "bootloader_mem.h" +#include "esp_private/regi2c_ctrl.h" +#include "soc/regi2c_lp_bias.h" +#include "soc/regi2c_bias.h" +#include "bootloader_console.h" +#include "bootloader_flash_priv.h" +#include "bootloader_soc.h" +#include "esp_efuse.h" +#include "hal/mmu_hal.h" +#include "hal/cache_hal.h" +#include "soc/lp_wdt_reg.h" +#include "hal/efuse_hal.h" + +static const char *TAG = "boot.esp32c6"; + +void IRAM_ATTR bootloader_configure_spi_pins(int drv) +{ + // TODO: IDF-5649 + const uint32_t spiconfig = 0; + uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; + uint8_t q_gpio_num = SPI_Q_GPIO_NUM; + uint8_t d_gpio_num = SPI_D_GPIO_NUM; + uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; + uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; + uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; + if (spiconfig == 0) { + + } + esp_rom_gpio_pad_set_drv(clk_gpio_num, drv); + esp_rom_gpio_pad_set_drv(q_gpio_num, drv); + esp_rom_gpio_pad_set_drv(d_gpio_num, drv); + esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv); + if (hd_gpio_num <= MAX_PAD_GPIO_NUM) { + esp_rom_gpio_pad_set_drv(hd_gpio_num, drv); + } + if (wp_gpio_num <= MAX_PAD_GPIO_NUM) { + esp_rom_gpio_pad_set_drv(wp_gpio_num, drv); + } +} + +static void update_flash_config(const esp_image_header_t *bootloader_hdr) +{ + uint32_t size; + switch (bootloader_hdr->spi_size) { + case ESP_IMAGE_FLASH_SIZE_1MB: + size = 1; + break; + case ESP_IMAGE_FLASH_SIZE_2MB: + size = 2; + break; + case ESP_IMAGE_FLASH_SIZE_4MB: + size = 4; + break; + case ESP_IMAGE_FLASH_SIZE_8MB: + size = 8; + break; + case ESP_IMAGE_FLASH_SIZE_16MB: + size = 16; + break; + default: + size = 2; + } + cache_hal_disable(CACHE_TYPE_ALL); + // Set flash chip size + esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode + cache_hal_enable(CACHE_TYPE_ALL); +} + +static void print_flash_info(const esp_image_header_t *bootloader_hdr) +{ + ESP_LOGD(TAG, "magic %02x", bootloader_hdr->magic); + ESP_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count); + ESP_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode); + ESP_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed); + ESP_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size); + + const char *str; + switch (bootloader_hdr->spi_speed) { + case ESP_IMAGE_SPI_SPEED_DIV_2: + str = "40MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_3: + str = "26.7MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_4: + str = "20MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_1: + str = "80MHz"; + break; + default: + str = "20MHz"; + break; + } + ESP_LOGI(TAG, "SPI Speed : %s", str); + + /* SPI mode could have been set to QIO during boot already, + so test the SPI registers not the flash header */ + uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0)); + if (spi_ctrl & SPI_MEM_FREAD_QIO) { + str = "QIO"; + } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) { + str = "QOUT"; + } else if (spi_ctrl & SPI_MEM_FREAD_DIO) { + str = "DIO"; + } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) { + str = "DOUT"; + } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) { + str = "FAST READ"; + } else { + str = "SLOW READ"; + } + ESP_LOGI(TAG, "SPI Mode : %s", str); + + switch (bootloader_hdr->spi_size) { + case ESP_IMAGE_FLASH_SIZE_1MB: + str = "1MB"; + break; + case ESP_IMAGE_FLASH_SIZE_2MB: + str = "2MB"; + break; + case ESP_IMAGE_FLASH_SIZE_4MB: + str = "4MB"; + break; + case ESP_IMAGE_FLASH_SIZE_8MB: + str = "8MB"; + break; + case ESP_IMAGE_FLASH_SIZE_16MB: + str = "16MB"; + break; + default: + str = "2MB"; + break; + } + ESP_LOGI(TAG, "SPI Flash Size : %s", str); +} + +static void IRAM_ATTR bootloader_init_flash_configure(void) +{ + bootloader_flash_dummy_config(&bootloader_image_hdr); + bootloader_flash_cs_timing_config(); +} + +static void bootloader_spi_flash_resume(void) +{ + bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0); + esp_rom_spiflash_wait_idle(&g_rom_flashchip); +} + +static esp_err_t bootloader_init_spi_flash(void) +{ + bootloader_init_flash_configure(); +// TODO: IDF-5649 +// #ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH +// const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); +// if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) { +// ESP_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig"); +// return ESP_FAIL; +// } +// #endif + + bootloader_spi_flash_resume(); + bootloader_flash_unlock(); + +#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT + bootloader_enable_qio_mode(); +#endif + + print_flash_info(&bootloader_image_hdr); + update_flash_config(&bootloader_image_hdr); + //ensure the flash is write-protected + bootloader_enable_wp(); + return ESP_OK; +} + +static void wdt_reset_cpu0_info_enable(void) +{ + REG_SET_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_CLK_EN); + REG_CLR_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_RST_EN); + REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN); +} + +static void wdt_reset_info_dump(int cpu) +{ + (void) cpu; + // saved PC was already printed by the ROM bootloader. + // nothing to do here. +} + +static void bootloader_check_wdt_reset(void) +{ + int wdt_rst = 0; + soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); + if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 || + rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) { + ESP_LOGW(TAG, "PRO CPU has been reset by WDT."); + wdt_rst = 1; + } + if (wdt_rst) { + // if reset by WDT dump info from trace port + wdt_reset_info_dump(0); + } + wdt_reset_cpu0_info_enable(); +} + +static void bootloader_super_wdt_auto_feed(void) +{ + REG_WRITE(LP_WDT_WPROTECT_REG, RTC_CNTL_SWD_WKEY_VALUE); + REG_SET_BIT(LP_WDT_SWD_CONFIG_REG, LP_WDT_SWD_AUTO_FEED_EN); + REG_WRITE(LP_WDT_WPROTECT_REG, 0); +} + +static inline void bootloader_hardware_init(void) +{ + // TODO: IDF-5990 copied from C3, need update + // This check is always included in the bootloader so it can + // print the minimum revision error message later in the boot + if (efuse_hal_get_minor_chip_version() < 3) { + REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 1); + REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 12); + } +} + +static inline void bootloader_ana_reset_config(void) +{ + // TODO: IDF-5990 copied from C3, need update + /* + esp32c6 has removed super wdt! + For origin chip & ECO1: only support swt reset; + For ECO2: fix brownout reset bug, support swt & brownout reset; + For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset. + */ + uint8_t chip_version = efuse_hal_get_minor_chip_version(); + switch (chip_version) { + case 0: + case 1: + //Disable BOR and GLITCH reset + bootloader_ana_bod_reset_config(false); + bootloader_ana_clock_glitch_reset_config(false); + break; + case 2: + //Enable BOR reset. Disable GLITCH reset + bootloader_ana_bod_reset_config(true); + bootloader_ana_clock_glitch_reset_config(false); + break; + case 3: + default: + //Enable BOR, and GLITCH reset + bootloader_ana_bod_reset_config(true); + bootloader_ana_clock_glitch_reset_config(true); + break; + } +} + +esp_err_t bootloader_init(void) +{ + esp_err_t ret = ESP_OK; + + bootloader_hardware_init(); + bootloader_ana_reset_config(); + bootloader_super_wdt_auto_feed(); + // protect memory region + bootloader_init_mem(); + /* check that static RAM is after the stack */ + assert(&_bss_start <= &_bss_end); + assert(&_data_start <= &_data_end); + // clear bss section + bootloader_clear_bss_section(); + // init eFuse virtual mode (read eFuses to RAM) +#ifdef CONFIG_EFUSE_VIRTUAL + ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!"); +#ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH + esp_efuse_init_virtual_mode_in_ram(); +#endif +#endif + //init cache hal + cache_hal_init(); + //reset mmu + mmu_hal_init(); + // config clock + bootloader_clock_configure(); + // initialize console, from now on, we can use esp_log + bootloader_console_init(); + /* print 2nd bootloader banner */ + bootloader_print_banner(); + // update flash ID + bootloader_flash_update_id(); + // Check and run XMC startup flow + if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) { + ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!"); + goto err; + } + // read bootloader header + if ((ret = bootloader_read_bootloader_header()) != ESP_OK) { + goto err; + } + // read chip revision and check if it's compatible to bootloader + if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) { + goto err; + } + // initialize spi flash + if ((ret = bootloader_init_spi_flash()) != ESP_OK) { + goto err; + } + // check whether a WDT reset happend + bootloader_check_wdt_reset(); + // config WDT + bootloader_config_wdt(); + // enable RNG early entropy source + bootloader_enable_random(); +err: + return ret; +} diff --git a/components/bootloader_support/src/esp32c6/bootloader_sha.c b/components/bootloader_support/src/esp32c6/bootloader_sha.c new file mode 100644 index 0000000000..716f143cb0 --- /dev/null +++ b/components/bootloader_support/src/esp32c6/bootloader_sha.c @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "bootloader_sha.h" +#include +#include +#include +#include + +#include "esp32c6/rom/sha.h" + +static SHA_CTX ctx; + +bootloader_sha256_handle_t bootloader_sha256_start() +{ + // Enable SHA hardware + ets_sha_enable(); + ets_sha_init(&ctx, SHA2_256); + return &ctx; // Meaningless non-NULL value +} + +void bootloader_sha256_data(bootloader_sha256_handle_t handle, const void *data, size_t data_len) +{ + assert(handle != NULL); + assert(data_len % 4 == 0); + ets_sha_update(&ctx, data, data_len, false); +} + +void bootloader_sha256_finish(bootloader_sha256_handle_t handle, uint8_t *digest) +{ + assert(handle != NULL); + + if (digest == NULL) { + bzero(&ctx, sizeof(ctx)); + return; + } + ets_sha_finish(&ctx, digest); +} diff --git a/components/bootloader_support/src/esp32c6/bootloader_soc.c b/components/bootloader_support/src/esp32c6/bootloader_soc.c new file mode 100644 index 0000000000..77a8d2176a --- /dev/null +++ b/components/bootloader_support/src/esp32c6/bootloader_soc.c @@ -0,0 +1,28 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include "soc/soc.h" +#include "soc/lp_analog_peri_reg.h" + +void bootloader_ana_bod_reset_config(bool enable) +{ + REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST); + if (enable) { + REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA); + } else { + REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA); + } +} + +void bootloader_ana_clock_glitch_reset_config(bool enable) +{ + REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST); + if (enable) { + REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA); + } else { + REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA); + } +} diff --git a/components/bootloader_support/src/esp32c6/flash_encryption_secure_features.c b/components/bootloader_support/src/esp32c6/flash_encryption_secure_features.c new file mode 100644 index 0000000000..3f64dbfd3d --- /dev/null +++ b/components/bootloader_support/src/esp32c6/flash_encryption_secure_features.c @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_flash_encrypt.h" +#include "esp_secure_boot.h" +#include "esp_efuse.h" +#include "esp_efuse_table.h" +#include "esp_log.h" +#include "sdkconfig.h" + +static __attribute__((unused)) const char *TAG = "flash_encrypt"; + +esp_err_t esp_flash_encryption_enable_secure_features(void) +{ +#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC + ESP_LOGI(TAG, "Disable UART bootloader encryption..."); + esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT); +#else + ESP_LOGW(TAG, "Not disabling UART bootloader encryption"); +#endif + +#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE + ESP_LOGI(TAG, "Disable UART bootloader cache..."); + esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE); +#else + ESP_LOGW(TAG, "Not disabling UART bootloader cache - SECURITY COMPROMISED"); +#endif + +#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG + ESP_LOGI(TAG, "Disable JTAG..."); + esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG); + esp_efuse_write_field_bit(ESP_EFUSE_DIS_USB_JTAG); +#else + ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED"); +#endif + + esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT); + +#if defined(CONFIG_SECURE_BOOT_V2_ENABLED) && !defined(CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS) + // This bit is set when enabling Secure Boot V2, but we can't enable it until this later point in the first boot + // otherwise the Flash Encryption key cannot be read protected + esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_RD_DIS); +#endif + + return ESP_OK; +} diff --git a/components/bootloader_support/src/esp32c6/secure_boot_secure_features.c b/components/bootloader_support/src/esp32c6/secure_boot_secure_features.c new file mode 100644 index 0000000000..9ea0f69e4b --- /dev/null +++ b/components/bootloader_support/src/esp32c6/secure_boot_secure_features.c @@ -0,0 +1,70 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_flash_encrypt.h" +#include "esp_secure_boot.h" +#include "esp_efuse.h" +#include "esp_efuse_table.h" +#include "esp_log.h" +#include "sdkconfig.h" + +static __attribute__((unused)) const char *TAG = "secure_boot"; + +esp_err_t esp_secure_boot_enable_secure_features(void) +{ + esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT); + +#ifdef CONFIG_SECURE_ENABLE_SECURE_ROM_DL_MODE + ESP_LOGI(TAG, "Enabling Security download mode..."); + esp_err_t err = esp_efuse_enable_rom_secure_download_mode(); + if (err != ESP_OK) { + ESP_LOGE(TAG, "Could not enable Security download mode..."); + return err; + } +#elif CONFIG_SECURE_DISABLE_ROM_DL_MODE + ESP_LOGI(TAG, "Disable ROM Download mode..."); + esp_err_t err = esp_efuse_disable_rom_download_mode(); + if (err != ESP_OK) { + ESP_LOGE(TAG, "Could not disable ROM Download mode..."); + return err; + } +#else + ESP_LOGW(TAG, "UART ROM Download mode kept enabled - SECURITY COMPROMISED"); +#endif + +#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG + ESP_LOGI(TAG, "Disable hardware & software JTAG..."); + esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG); + esp_efuse_write_field_bit(ESP_EFUSE_DIS_USB_JTAG); + esp_efuse_write_field_cnt(ESP_EFUSE_SOFT_DIS_JTAG, ESP_EFUSE_SOFT_DIS_JTAG[0]->bit_count); +#else + ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED"); +#endif + +#ifdef CONFIG_SECURE_BOOT_ENABLE_AGGRESSIVE_KEY_REVOKE + esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE); +#endif + + esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_EN); + +#ifndef CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS + bool rd_dis_now = true; +#ifdef CONFIG_SECURE_FLASH_ENC_ENABLED + /* If flash encryption is not enabled yet then don't read-disable efuses yet, do it later in the boot + when Flash Encryption is being enabled */ + rd_dis_now = esp_flash_encryption_enabled(); +#endif + if (rd_dis_now) { + ESP_LOGI(TAG, "Prevent read disabling of additional efuses..."); + esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_RD_DIS); + } +#else + ESP_LOGW(TAG, "Allowing read disabling of additional efuses - SECURITY COMPROMISED"); +#endif + + return ESP_OK; +} diff --git a/components/bootloader_support/src/esp_image_format.c b/components/bootloader_support/src/esp_image_format.c index 67105299ff..c46e698eed 100644 --- a/components/bootloader_support/src/esp_image_format.c +++ b/components/bootloader_support/src/esp_image_format.c @@ -34,6 +34,9 @@ #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/rtc.h" #include "esp32c2/rom/secure_boot.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/rtc.h" +#include "esp32c6/rom/secure_boot.h" #endif #define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) diff --git a/components/bootloader_support/src/flash_encrypt.c b/components/bootloader_support/src/flash_encrypt.c index 9405e5ac68..e6f789f1ef 100644 --- a/components/bootloader_support/src/flash_encrypt.c +++ b/components/bootloader_support/src/flash_encrypt.c @@ -142,7 +142,7 @@ esp_flash_enc_mode_t esp_get_flash_encryption_mode(void) if (dis_dl_enc && dis_dl_icache && dis_dl_dcache) { mode = ESP_FLASH_ENC_MODE_RELEASE; } -#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 +#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6 bool dis_dl_enc = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT); bool dis_dl_icache = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE); if (dis_dl_enc && dis_dl_icache) { @@ -191,7 +191,7 @@ void esp_flash_encryption_set_release_mode(void) esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT); esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE); esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_DCACHE); -#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 +#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6 esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT); esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE); #ifdef CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED diff --git a/components/bootloader_support/src/flash_encryption/flash_encrypt.c b/components/bootloader_support/src/flash_encryption/flash_encrypt.c index 0256a6ebdd..8ff0e27a3d 100644 --- a/components/bootloader_support/src/flash_encryption/flash_encrypt.c +++ b/components/bootloader_support/src/flash_encryption/flash_encrypt.c @@ -429,7 +429,11 @@ esp_err_t esp_flash_encrypt_region(uint32_t src_addr, size_t data_length) return ESP_FAIL; } +#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5653 + wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &LP_WDT}; +#else wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; +#endif for (size_t i = 0; i < data_length; i += FLASH_SECTOR_SIZE) { wdt_hal_write_protect_disable(&rtc_wdt_ctx); wdt_hal_feed(&rtc_wdt_ctx); diff --git a/components/bootloader_support/test/CMakeLists.txt b/components/bootloader_support/test/CMakeLists.txt deleted file mode 100644 index 16963ea6bb..0000000000 --- a/components/bootloader_support/test/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -idf_component_register(SRC_DIRS "." - PRIV_INCLUDE_DIRS "." - PRIV_REQUIRES cmock bootloader_support app_update) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/usb/device/tusb_sample_descriptor/CMakeLists.txt b/components/bootloader_support/test_apps/bootloader_support/CMakeLists.txt similarity index 59% rename from examples/peripherals/usb/device/tusb_sample_descriptor/CMakeLists.txt rename to components/bootloader_support/test_apps/bootloader_support/CMakeLists.txt index 67cc4b7d05..07ef465a67 100644 --- a/examples/peripherals/usb/device/tusb_sample_descriptor/CMakeLists.txt +++ b/components/bootloader_support/test_apps/bootloader_support/CMakeLists.txt @@ -1,6 +1,6 @@ -# The following five lines of boilerplate have to be in your project's +# The following lines of boilerplate have to be in your project's # CMakeLists in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.16) include($ENV{IDF_PATH}/tools/cmake/project.cmake) -project(tusb_sample_descriptor) +project(test_bootloader_support) diff --git a/components/bootloader_support/test_apps/bootloader_support/README.md b/components/bootloader_support/test_apps/bootloader_support/README.md new file mode 100644 index 0000000000..b5be4985c5 --- /dev/null +++ b/components/bootloader_support/test_apps/bootloader_support/README.md @@ -0,0 +1,2 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | diff --git a/components/bootloader_support/test_apps/bootloader_support/main/CMakeLists.txt b/components/bootloader_support/test_apps/bootloader_support/main/CMakeLists.txt new file mode 100644 index 0000000000..1d67beb656 --- /dev/null +++ b/components/bootloader_support/test_apps/bootloader_support/main/CMakeLists.txt @@ -0,0 +1,3 @@ +idf_component_register(SRCS "test_app_main.c" "test_verify_image.c" + INCLUDE_DIRS "." + WHOLE_ARCHIVE) diff --git a/components/bootloader_support/test_apps/bootloader_support/main/test_app_main.c b/components/bootloader_support/test_apps/bootloader_support/main/test_app_main.c new file mode 100644 index 0000000000..52a9e14b82 --- /dev/null +++ b/components/bootloader_support/test_apps/bootloader_support/main/test_app_main.c @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "unity.h" +#include "unity_test_runner.h" +#include "esp_heap_caps.h" + + +// Some resources are lazy allocated (newlib locks) in the bootloader support code, the threshold is left for that case +#define TEST_MEMORY_LEAK_THRESHOLD (-550) + +static size_t before_free_8bit; +static size_t before_free_32bit; + +static void check_leak(size_t before_free, size_t after_free, const char *type) +{ + ssize_t delta = after_free - before_free; + printf("MALLOC_CAP_%s: Before %u bytes free, After %u bytes free (delta %d)\n", type, before_free, after_free, delta); + TEST_ASSERT_MESSAGE(delta >= TEST_MEMORY_LEAK_THRESHOLD, "memory leak"); +} + +void setUp(void) +{ + before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); +} + + + +void tearDown(void) +{ + size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); + check_leak(before_free_8bit, after_free_8bit, "8BIT"); + check_leak(before_free_32bit, after_free_32bit, "32BIT"); +} + +void app_main(void) +{ + printf("Running bootloader support component tests\n"); + unity_run_menu(); +} diff --git a/components/bootloader_support/test/test_verify_image.c b/components/bootloader_support/test_apps/bootloader_support/main/test_verify_image.c similarity index 97% rename from components/bootloader_support/test/test_verify_image.c rename to components/bootloader_support/test_apps/bootloader_support/main/test_verify_image.c index a73a8d10f1..1313c03e6e 100644 --- a/components/bootloader_support/test/test_verify_image.c +++ b/components/bootloader_support/test_apps/bootloader_support/main/test_verify_image.c @@ -37,8 +37,6 @@ TEST_CASE("Verify bootloader image in flash", "[bootloader_support]") TEST_ASSERT_EQUAL(data.image_len, bootloader_length); } -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) -//IDF-5145 TEST_CASE("Verify unit test app image", "[bootloader_support]") { esp_image_metadata_t data = { 0 }; @@ -53,7 +51,6 @@ TEST_CASE("Verify unit test app image", "[bootloader_support]") TEST_ASSERT_NOT_EQUAL(0, data.image_len); TEST_ASSERT_TRUE(data.image_len <= running->size); } -#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) void check_label_search (int num_test, const char *list, const char *t_label, bool result) { diff --git a/components/bootloader_support/test_apps/bootloader_support/pytest_bootloader_support.py b/components/bootloader_support/test_apps/bootloader_support/pytest_bootloader_support.py new file mode 100644 index 0000000000..ab6afdc475 --- /dev/null +++ b/components/bootloader_support/test_apps/bootloader_support/pytest_bootloader_support.py @@ -0,0 +1,13 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +import pytest +from pytest_embedded import Dut + + +@pytest.mark.generic +@pytest.mark.supported_targets +def test_bootloader_support(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('*') + dut.expect_unity_test_output(timeout=300) diff --git a/components/bootloader_support/test_apps/rtc_custom_section/CMakeLists.txt b/components/bootloader_support/test_apps/rtc_custom_section/CMakeLists.txt new file mode 100644 index 0000000000..1950e50346 --- /dev/null +++ b/components/bootloader_support/test_apps/rtc_custom_section/CMakeLists.txt @@ -0,0 +1,6 @@ +# The following lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(test_rtc_custom_section) diff --git a/components/bootloader_support/test_apps/rtc_custom_section/README.md b/components/bootloader_support/test_apps/rtc_custom_section/README.md new file mode 100644 index 0000000000..497a93ba72 --- /dev/null +++ b/components/bootloader_support/test_apps/rtc_custom_section/README.md @@ -0,0 +1,2 @@ +| Supported Targets | ESP32 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | diff --git a/components/bootloader_support/test_apps/rtc_custom_section/main/CMakeLists.txt b/components/bootloader_support/test_apps/rtc_custom_section/main/CMakeLists.txt new file mode 100644 index 0000000000..1df31fac80 --- /dev/null +++ b/components/bootloader_support/test_apps/rtc_custom_section/main/CMakeLists.txt @@ -0,0 +1,2 @@ +idf_component_register(SRCS "test_main.c" + INCLUDE_DIRS ".") diff --git a/components/bootloader_support/test_apps/rtc_custom_section/main/test_main.c b/components/bootloader_support/test_apps/rtc_custom_section/main/test_main.c new file mode 100644 index 0000000000..116f226a00 --- /dev/null +++ b/components/bootloader_support/test_apps/rtc_custom_section/main/test_main.c @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "bootloader_common.h" +#include +#include "sdkconfig.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + +#define TEST_MAGIC_VALUE 0x42987561 + +extern rtc_retain_mem_t* bootloader_common_get_rtc_retain_mem(void); + +void app_main(void) { + rtc_retain_mem_t* mem = bootloader_common_get_rtc_retain_mem(); + uint32_t* _rtc_vars = (uint32_t*) mem->custom; + + if (_rtc_vars[0] != TEST_MAGIC_VALUE) { + /* On the first boot, set the data inside the array */ + _rtc_vars[0] = TEST_MAGIC_VALUE; + } else { + /* Second boot, the data was saved saved, success */ + printf("SUCCESS: data were saved across reboot\n"); + vTaskDelay(10000 / portTICK_PERIOD_MS); + } + + esp_restart(); +} diff --git a/components/bootloader_support/test_apps/rtc_custom_section/pytest_rtc_mem.py b/components/bootloader_support/test_apps/rtc_custom_section/pytest_rtc_mem.py new file mode 100644 index 0000000000..e00fa596ff --- /dev/null +++ b/components/bootloader_support/test_apps/rtc_custom_section/pytest_rtc_mem.py @@ -0,0 +1,14 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +import pytest +from pytest_embedded import Dut + + +@pytest.mark.generic +@pytest.mark.esp32 +@pytest.mark.esp32c3 +@pytest.mark.esp32s2 +@pytest.mark.esp32s3 +def test_rtc_reserved_memory(dut: Dut) -> None: + dut.expect_exact('SUCCESS: data were saved across reboot', timeout=10) diff --git a/components/bootloader_support/test_apps/rtc_custom_section/sdkconfig.defaults b/components/bootloader_support/test_apps/rtc_custom_section/sdkconfig.defaults new file mode 100644 index 0000000000..e10fa74582 --- /dev/null +++ b/components/bootloader_support/test_apps/rtc_custom_section/sdkconfig.defaults @@ -0,0 +1,3 @@ +CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0x10 +CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC=y +CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE=0x200 diff --git a/components/bt/CMakeLists.txt b/components/bt/CMakeLists.txt index 47d99d3cb6..9518f7b66c 100644 --- a/components/bt/CMakeLists.txt +++ b/components/bt/CMakeLists.txt @@ -687,17 +687,17 @@ idf_component_register(SRCS "${srcs}" if(CONFIG_BT_ENABLED) target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-implicit-fallthrough -Wno-unused-const-variable) if(CONFIG_IDF_TARGET_ESP32) - target_link_libraries(${COMPONENT_LIB} INTERFACE "-L${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32/esp32") + target_link_directories(${COMPONENT_LIB} INTERFACE "${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32/esp32") target_link_libraries(${COMPONENT_LIB} PUBLIC btdm_app) target_link_libraries(${COMPONENT_LIB} INTERFACE "-u ld_include_hli_vectors_bt") elseif(CONFIG_IDF_TARGET_ESP32C3) - target_link_libraries(${COMPONENT_LIB} INTERFACE - "-L${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c3_family/esp32c3") + target_link_directories(${COMPONENT_LIB} INTERFACE + "${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c3_family/esp32c3") target_link_libraries(${COMPONENT_LIB} PUBLIC btdm_app) elseif(CONFIG_IDF_TARGET_ESP32S3) - target_link_libraries(${COMPONENT_LIB} INTERFACE - "-L${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c3_family/esp32s3") + target_link_directories(${COMPONENT_LIB} INTERFACE + "${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c3_family/esp32s3") target_link_libraries(${COMPONENT_LIB} PUBLIC btdm_app) elseif(CONFIG_IDF_TARGET_ESP32H2) if(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1) diff --git a/components/bt/common/btc/core/btc_task.c b/components/bt/common/btc/core/btc_task.c index e611890904..b094e045df 100644 --- a/components/bt/common/btc/core/btc_task.c +++ b/components/bt/common/btc/core/btc_task.c @@ -218,16 +218,7 @@ static void btc_thread_handler(void *arg) static bt_status_t btc_task_post(btc_msg_t *msg, uint32_t timeout) { - btc_msg_t *lmsg; - - lmsg = (btc_msg_t *)osi_malloc(sizeof(btc_msg_t)); - if (lmsg == NULL) { - return BT_STATUS_NOMEM; - } - - memcpy(lmsg, msg, sizeof(btc_msg_t)); - - if (osi_thread_post(btc_thread, btc_thread_handler, lmsg, 0, timeout) == false) { + if (osi_thread_post(btc_thread, btc_thread_handler, msg, 0, timeout) == false) { return BT_STATUS_BUSY; } @@ -245,30 +236,37 @@ static bt_status_t btc_task_post(btc_msg_t *msg, uint32_t timeout) */ bt_status_t btc_transfer_context(btc_msg_t *msg, void *arg, int arg_len, btc_arg_deep_copy_t copy_func) { - btc_msg_t lmsg; + btc_msg_t* lmsg; - if (msg == NULL) { + // arg XOR arg_len + if ((msg == NULL) || ((arg == NULL) == !(arg_len == 0))) { return BT_STATUS_PARM_INVALID; } BTC_TRACE_DEBUG("%s msg %u %u %u %p\n", __func__, msg->sig, msg->pid, msg->act, arg); - memcpy(&lmsg, msg, sizeof(btc_msg_t)); - if (arg) { - lmsg.arg = (void *)osi_malloc(arg_len); - if (lmsg.arg == NULL) { - return BT_STATUS_NOMEM; - } - memset(lmsg.arg, 0x00, arg_len); //important, avoid arg which have no length - memcpy(lmsg.arg, arg, arg_len); - if (copy_func) { - copy_func(&lmsg, lmsg.arg, arg); - } - } else { - lmsg.arg = NULL; + lmsg = (btc_msg_t *)osi_malloc(sizeof(btc_msg_t)); + if (lmsg == NULL) { + return BT_STATUS_NOMEM; } - return btc_task_post(&lmsg, OSI_THREAD_MAX_TIMEOUT); + memcpy(lmsg, msg, sizeof(btc_msg_t)); + if (arg) { + lmsg->arg = (void *)osi_malloc(arg_len); + if (lmsg->arg == NULL) { + osi_free(lmsg); + return BT_STATUS_NOMEM; + } + memset(lmsg->arg, 0x00, arg_len); //important, avoid arg which have no length + memcpy(lmsg->arg, arg, arg_len); + if (copy_func) { + copy_func(lmsg, lmsg->arg, arg); + } + } else { + lmsg->arg = NULL; + } + + return btc_task_post(lmsg, OSI_THREAD_MAX_TIMEOUT); } diff --git a/components/bt/common/btc/profile/esp/blufi/include/esp_blufi.h b/components/bt/common/btc/profile/esp/blufi/include/esp_blufi.h index 9f17758661..ee9069059c 100644 --- a/components/bt/common/btc/profile/esp/blufi/include/esp_blufi.h +++ b/components/bt/common/btc/profile/esp/blufi/include/esp_blufi.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -40,6 +40,7 @@ void esp_blufi_gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *a /* Initialise gatt server */ int esp_blufi_gatt_svr_init(void); void esp_blufi_btc_init(void); +void esp_blufi_btc_deinit(void); #endif #ifdef CONFIG_BT_BLUEDROID_ENABLED diff --git a/components/bt/common/btc/profile/esp/blufi/nimble_host/esp_blufi.c b/components/bt/common/btc/profile/esp/blufi/nimble_host/esp_blufi.c index 7e4ea095ff..d86bb607f0 100644 --- a/components/bt/common/btc/profile/esp/blufi/nimble_host/esp_blufi.c +++ b/components/bt/common/btc/profile/esp/blufi/nimble_host/esp_blufi.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -466,4 +466,8 @@ void esp_blufi_btc_init(void) assert(rc == 0); } +void esp_blufi_btc_deinit(void) +{ + btc_deinit(); +} #endif diff --git a/components/bt/controller/esp32c2/bt.c b/components/bt/controller/esp32c2/bt.c index dbad0cc881..01a9154f0e 100644 --- a/components/bt/controller/esp32c2/bt.c +++ b/components/bt/controller/esp32c2/bt.c @@ -61,6 +61,12 @@ #define EXT_FUNC_VERSION 0x20220125 #define EXT_FUNC_MAGIC_VALUE 0xA5A5A5A5 + +#ifdef CONFIG_BT_BLUEDROID_ENABLED +/* ACL_DATA_MBUF_LEADINGSPCAE: The leadingspace in user info header for ACL data */ +#define ACL_DATA_MBUF_LEADINGSPCAE 4 +#endif + /* Types definition ************************************************************************ */ @@ -125,6 +131,8 @@ extern int ble_sm_alg_gen_dhkey(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y, const uint8_t *our_priv_key, uint8_t *out_dhkey); extern int ble_sm_alg_gen_key_pair(uint8_t *pub, uint8_t *priv); +extern int ble_txpwr_set(esp_ble_enhanced_power_type_t power_type, uint16_t handle, int power_level); +extern int ble_txpwr_get(esp_ble_enhanced_power_type_t power_type, uint16_t handle); /* Local Function Declaration ********************************************************************* @@ -163,6 +171,8 @@ static DRAM_ATTR bool s_btdm_allow_light_sleep; // pm_lock to prevent light sleep when using main crystal as Bluetooth low power clock static DRAM_ATTR esp_pm_lock_handle_t s_light_sleep_pm_lock; #define BTDM_MIN_TIMER_UNCERTAINTY_US (200) +#else +static bool s_bt_phy_enabled = false; #endif /* #ifdef CONFIG_PM_ENABLE */ #ifdef CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER @@ -175,6 +185,7 @@ static void btdm_slp_tmr_callback(void *arg); static DRAM_ATTR esp_timer_handle_t s_btdm_slp_tmr = NULL; #endif + static const struct osi_coex_funcs_t s_osi_coex_funcs_ro = { ._magic = OSI_COEX_MAGIC_VALUE, ._version = OSI_COEX_VERSION, @@ -238,6 +249,7 @@ static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status) #endif } #ifdef CONFIG_BT_BLUEDROID_ENABLED + bool esp_vhci_host_check_send_available(void) { if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) { @@ -295,11 +307,9 @@ void esp_vhci_host_send_packet(uint8_t *data, uint16_t len) } if (*(data) == DATA_TYPE_ACL) { - struct os_mbuf *om = os_msys_get_pkthdr(0, 0); + struct os_mbuf *om = os_msys_get_pkthdr(len, ACL_DATA_MBUF_LEADINGSPCAE); assert(om); - memcpy(om->om_data, &data[1], len - 1); - om->om_len = len - 1; - OS_MBUF_PKTHDR(om)->omp_len = len - 1; + os_mbuf_append(om, &data[1], len - 1); ble_hci_trans_hs_acl_tx(om); } @@ -421,7 +431,8 @@ IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg) esp_pm_lock_release(s_pm_lock); s_pm_lock_acquired = false; } - +#else + s_bt_phy_enabled = false; #endif // CONFIG_PM_ENABLE } @@ -435,6 +446,8 @@ IRAM_ATTR void controller_wakeup_cb(void *arg) s_pm_lock_acquired = true; esp_pm_lock_acquire(s_pm_lock); } +#else + s_bt_phy_enabled = true; #endif //CONFIG_PM_ENABLE } @@ -458,6 +471,8 @@ void controller_sleep_init(void) #ifdef CONFIG_PM_ENABLE s_btdm_allow_light_sleep = false; +#else + s_bt_phy_enabled = true; #endif // CONFIG_PM_ENABLE #ifdef CONFIG_BT_LE_SLEEP_ENABLE @@ -540,8 +555,21 @@ void controller_sleep_deinit(void) #ifdef CONFIG_PM_ENABLE #ifdef CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER r_ble_rtc_wake_up_state_clr(); + esp_sleep_disable_bt_wakeup(); #endif esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_AUTO); + + /*lock should release first and then delete*/ + if (s_pm_lock_acquired) { + if (s_light_sleep_pm_lock != NULL) { + esp_pm_lock_release(s_light_sleep_pm_lock); + } + + if (s_pm_lock != NULL) { + esp_pm_lock_release(s_pm_lock); + } + } + if (!s_btdm_allow_light_sleep) { if (s_light_sleep_pm_lock != NULL) { esp_pm_lock_delete(s_light_sleep_pm_lock); @@ -559,7 +587,15 @@ void controller_sleep_deinit(void) s_btdm_slp_tmr = NULL; } #endif - s_pm_lock_acquired = false; + if (s_pm_lock_acquired) { + esp_phy_disable(); + s_pm_lock_acquired = false; + } +#else + if (s_bt_phy_enabled) { + esp_phy_disable(); + s_bt_phy_enabled = false; + } #endif } @@ -708,7 +744,6 @@ esp_err_t esp_bt_controller_deinit(void) npl_freertos_mempool_deinit(); - esp_phy_disable(); esp_phy_pd_mem_deinit(); ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE; @@ -770,16 +805,120 @@ esp_bt_controller_status_t esp_bt_controller_get_status(void) /* extra functions */ esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_t power_level) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "%s not implemented, return OK", __func__); - return ESP_OK; + esp_err_t stat = ESP_FAIL; + + switch (power_type) { + case ESP_BLE_PWR_TYPE_DEFAULT: + case ESP_BLE_PWR_TYPE_ADV: + case ESP_BLE_PWR_TYPE_SCAN: + if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { + stat = ESP_OK; + } + break; + case ESP_BLE_PWR_TYPE_CONN_HDL0: + case ESP_BLE_PWR_TYPE_CONN_HDL1: + case ESP_BLE_PWR_TYPE_CONN_HDL2: + case ESP_BLE_PWR_TYPE_CONN_HDL3: + case ESP_BLE_PWR_TYPE_CONN_HDL4: + case ESP_BLE_PWR_TYPE_CONN_HDL5: + case ESP_BLE_PWR_TYPE_CONN_HDL6: + case ESP_BLE_PWR_TYPE_CONN_HDL7: + case ESP_BLE_PWR_TYPE_CONN_HDL8: + if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type, power_level) == 0) { + stat = ESP_OK; + } + break; + default: + stat = ESP_ERR_NOT_SUPPORTED; + break; + } + + return stat; +} + +esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle, esp_power_level_t power_level) +{ + esp_err_t stat = ESP_FAIL; + switch (power_type) { + case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT: + case ESP_BLE_ENHANCED_PWR_TYPE_SCAN: + case ESP_BLE_ENHANCED_PWR_TYPE_INIT: + if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { + stat = ESP_OK; + } + break; + case ESP_BLE_ENHANCED_PWR_TYPE_ADV: + case ESP_BLE_ENHANCED_PWR_TYPE_CONN: + if (ble_txpwr_set(power_type, handle, power_level) == 0) { + stat = ESP_OK; + } + break; + default: + stat = ESP_ERR_NOT_SUPPORTED; + break; + } + + return stat; } esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "%s not implemented, return OK", __func__); - return ESP_PWR_LVL_N0; + int tx_level = 0; + + switch (power_type) { + case ESP_BLE_PWR_TYPE_ADV: + case ESP_BLE_PWR_TYPE_SCAN: + case ESP_BLE_PWR_TYPE_DEFAULT: + tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); + break; + case ESP_BLE_PWR_TYPE_CONN_HDL0: + case ESP_BLE_PWR_TYPE_CONN_HDL1: + case ESP_BLE_PWR_TYPE_CONN_HDL2: + case ESP_BLE_PWR_TYPE_CONN_HDL3: + case ESP_BLE_PWR_TYPE_CONN_HDL4: + case ESP_BLE_PWR_TYPE_CONN_HDL5: + case ESP_BLE_PWR_TYPE_CONN_HDL6: + case ESP_BLE_PWR_TYPE_CONN_HDL7: + case ESP_BLE_PWR_TYPE_CONN_HDL8: + tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type); + break; + default: + return ESP_PWR_LVL_INVALID; + } + + if (tx_level < 0) { + return ESP_PWR_LVL_INVALID; + } + + return (esp_power_level_t)tx_level; } +esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle) +{ + int tx_level = 0; + + switch (power_type) { + case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT: + case ESP_BLE_ENHANCED_PWR_TYPE_SCAN: + case ESP_BLE_ENHANCED_PWR_TYPE_INIT: + tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); + break; + case ESP_BLE_ENHANCED_PWR_TYPE_ADV: + case ESP_BLE_ENHANCED_PWR_TYPE_CONN: + tx_level = ble_txpwr_get(power_type, handle); + break; + default: + return ESP_PWR_LVL_INVALID; + } + + if (tx_level < 0) { + return ESP_PWR_LVL_INVALID; + } + + return (esp_power_level_t)tx_level; +} + + #if (!CONFIG_BT_NIMBLE_ENABLED) && (CONFIG_BT_CONTROLLER_ENABLED == true) #define BLE_SM_KEY_ERR 0x17 diff --git a/components/bt/controller/esp32c3/Kconfig.in b/components/bt/controller/esp32c3/Kconfig.in index 94b31a3d84..9d409ab269 100644 --- a/components/bt/controller/esp32c3/Kconfig.in +++ b/components/bt/controller/esp32c3/Kconfig.in @@ -138,8 +138,6 @@ choice BT_CTRL_DFT_TX_POWER_LEVEL help Specify default Tx power level - config BT_CTRL_DFT_TX_POWER_LEVEL_N27 - bool "-27dBm" config BT_CTRL_DFT_TX_POWER_LEVEL_N24 bool "-24dBm" config BT_CTRL_DFT_TX_POWER_LEVEL_N21 @@ -170,26 +168,28 @@ choice BT_CTRL_DFT_TX_POWER_LEVEL bool "+15dBm" config BT_CTRL_DFT_TX_POWER_LEVEL_P18 bool "+18dBm" + config BT_CTRL_DFT_TX_POWER_LEVEL_P21 + bool "+21dBm" endchoice config BT_CTRL_DFT_TX_POWER_LEVEL_EFF int - default 0 if BT_CTRL_DFT_TX_POWER_LEVEL_N27 - default 1 if BT_CTRL_DFT_TX_POWER_LEVEL_N24 - default 2 if BT_CTRL_DFT_TX_POWER_LEVEL_N21 - default 3 if BT_CTRL_DFT_TX_POWER_LEVEL_N18 - default 4 if BT_CTRL_DFT_TX_POWER_LEVEL_N15 - default 5 if BT_CTRL_DFT_TX_POWER_LEVEL_N12 - default 6 if BT_CTRL_DFT_TX_POWER_LEVEL_N9 - default 7 if BT_CTRL_DFT_TX_POWER_LEVEL_N6 - default 8 if BT_CTRL_DFT_TX_POWER_LEVEL_N3 - default 9 if BT_CTRL_DFT_TX_POWER_LEVEL_N0 - default 10 if BT_CTRL_DFT_TX_POWER_LEVEL_P3 - default 11 if BT_CTRL_DFT_TX_POWER_LEVEL_P6 - default 12 if BT_CTRL_DFT_TX_POWER_LEVEL_P9 - default 13 if BT_CTRL_DFT_TX_POWER_LEVEL_P12 - default 14 if BT_CTRL_DFT_TX_POWER_LEVEL_P15 - default 15 if BT_CTRL_DFT_TX_POWER_LEVEL_P18 + default 0 if BT_CTRL_DFT_TX_POWER_LEVEL_N24 + default 1 if BT_CTRL_DFT_TX_POWER_LEVEL_N21 + default 2 if BT_CTRL_DFT_TX_POWER_LEVEL_N18 + default 3 if BT_CTRL_DFT_TX_POWER_LEVEL_N15 + default 4 if BT_CTRL_DFT_TX_POWER_LEVEL_N12 + default 5 if BT_CTRL_DFT_TX_POWER_LEVEL_N9 + default 6 if BT_CTRL_DFT_TX_POWER_LEVEL_N6 + default 7 if BT_CTRL_DFT_TX_POWER_LEVEL_N3 + default 8 if BT_CTRL_DFT_TX_POWER_LEVEL_N0 + default 9 if BT_CTRL_DFT_TX_POWER_LEVEL_P3 + default 10 if BT_CTRL_DFT_TX_POWER_LEVEL_P6 + default 11 if BT_CTRL_DFT_TX_POWER_LEVEL_P9 + default 12 if BT_CTRL_DFT_TX_POWER_LEVEL_P12 + default 13 if BT_CTRL_DFT_TX_POWER_LEVEL_P15 + default 14 if BT_CTRL_DFT_TX_POWER_LEVEL_P18 + default 15 if BT_CTRL_DFT_TX_POWER_LEVEL_P21 default 0 config BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP diff --git a/components/bt/controller/esp32c6/Kconfig.in b/components/bt/controller/esp32c6/Kconfig.in new file mode 100644 index 0000000000..eb432c86f0 --- /dev/null +++ b/components/bt/controller/esp32c6/Kconfig.in @@ -0,0 +1 @@ +# TODO: IDF-5727 diff --git a/components/bt/controller/esp32s3/Kconfig.in b/components/bt/controller/esp32s3/Kconfig.in index db6cb10e57..66ae91a5a3 100644 --- a/components/bt/controller/esp32s3/Kconfig.in +++ b/components/bt/controller/esp32s3/Kconfig.in @@ -153,8 +153,6 @@ choice BT_CTRL_DFT_TX_POWER_LEVEL help Specify default Tx power level - config BT_CTRL_DFT_TX_POWER_LEVEL_N27 - bool "-27dBm" config BT_CTRL_DFT_TX_POWER_LEVEL_N24 bool "-24dBm" config BT_CTRL_DFT_TX_POWER_LEVEL_N21 @@ -185,27 +183,29 @@ choice BT_CTRL_DFT_TX_POWER_LEVEL bool "+15dBm" config BT_CTRL_DFT_TX_POWER_LEVEL_P18 bool "+18dBm" + config BT_CTRL_DFT_TX_POWER_LEVEL_P18 + bool "+21dBm" endchoice config BT_CTRL_DFT_TX_POWER_LEVEL_EFF int - default 0 if BT_CTRL_DFT_TX_POWER_LEVEL_N27 - default 1 if BT_CTRL_DFT_TX_POWER_LEVEL_N24 - default 2 if BT_CTRL_DFT_TX_POWER_LEVEL_N21 - default 3 if BT_CTRL_DFT_TX_POWER_LEVEL_N18 - default 4 if BT_CTRL_DFT_TX_POWER_LEVEL_N15 - default 5 if BT_CTRL_DFT_TX_POWER_LEVEL_N12 - default 6 if BT_CTRL_DFT_TX_POWER_LEVEL_N9 - default 7 if BT_CTRL_DFT_TX_POWER_LEVEL_N6 - default 8 if BT_CTRL_DFT_TX_POWER_LEVEL_N3 - default 9 if BT_CTRL_DFT_TX_POWER_LEVEL_N0 - default 10 if BT_CTRL_DFT_TX_POWER_LEVEL_P3 - default 11 if BT_CTRL_DFT_TX_POWER_LEVEL_P6 - default 12 if BT_CTRL_DFT_TX_POWER_LEVEL_P9 - default 13 if BT_CTRL_DFT_TX_POWER_LEVEL_P12 - default 14 if BT_CTRL_DFT_TX_POWER_LEVEL_P15 - default 15 if BT_CTRL_DFT_TX_POWER_LEVEL_P18 + default 0 if BT_CTRL_DFT_TX_POWER_LEVEL_N24 + default 1 if BT_CTRL_DFT_TX_POWER_LEVEL_N21 + default 2 if BT_CTRL_DFT_TX_POWER_LEVEL_N18 + default 3 if BT_CTRL_DFT_TX_POWER_LEVEL_N15 + default 4 if BT_CTRL_DFT_TX_POWER_LEVEL_N12 + default 5 if BT_CTRL_DFT_TX_POWER_LEVEL_N9 + default 6 if BT_CTRL_DFT_TX_POWER_LEVEL_N6 + default 7 if BT_CTRL_DFT_TX_POWER_LEVEL_N3 + default 8 if BT_CTRL_DFT_TX_POWER_LEVEL_N0 + default 9 if BT_CTRL_DFT_TX_POWER_LEVEL_P3 + default 10 if BT_CTRL_DFT_TX_POWER_LEVEL_P6 + default 11 if BT_CTRL_DFT_TX_POWER_LEVEL_P9 + default 12 if BT_CTRL_DFT_TX_POWER_LEVEL_P12 + default 13 if BT_CTRL_DFT_TX_POWER_LEVEL_P15 + default 14 if BT_CTRL_DFT_TX_POWER_LEVEL_P18 + default 15 if BT_CTRL_DFT_TX_POWER_LEVEL_P21 default 0 diff --git a/components/bt/controller/lib_esp32 b/components/bt/controller/lib_esp32 index c98341759b..6ca6561fe5 160000 --- a/components/bt/controller/lib_esp32 +++ b/components/bt/controller/lib_esp32 @@ -1 +1 @@ -Subproject commit c98341759b2c152c58878db6daf22d153a75fda4 +Subproject commit 6ca6561fe525171cbb96eb9d98b7db91137982dc diff --git a/components/bt/controller/lib_esp32c2/esp32c2-bt-lib b/components/bt/controller/lib_esp32c2/esp32c2-bt-lib index 34e6a82bab..90749ea1cb 160000 --- a/components/bt/controller/lib_esp32c2/esp32c2-bt-lib +++ b/components/bt/controller/lib_esp32c2/esp32c2-bt-lib @@ -1 +1 @@ -Subproject commit 34e6a82bab1a0d09eb8d96277d8c7b4d9006071e +Subproject commit 90749ea1cbbc568bc75a673b0d50b89322066a09 diff --git a/components/bt/controller/lib_esp32c3_family b/components/bt/controller/lib_esp32c3_family index d1c2082e56..43b48d75e7 160000 --- a/components/bt/controller/lib_esp32c3_family +++ b/components/bt/controller/lib_esp32c3_family @@ -1 +1 @@ -Subproject commit d1c2082e5633a89c6fd6051c7761c1e697cb7a2e +Subproject commit 43b48d75e7e468c0cccd038721e1184dae6aabac diff --git a/components/bt/esp_ble_mesh/Kconfig.in b/components/bt/esp_ble_mesh/Kconfig.in index b7a0db84de..521d7a03ae 100644 --- a/components/bt/esp_ble_mesh/Kconfig.in +++ b/components/bt/esp_ble_mesh/Kconfig.in @@ -803,6 +803,13 @@ if BLE_MESH help Maximum number of groups to which the LPN can subscribe. + config BLE_MESH_LPN_SUB_ALL_NODES_ADDR + bool "Automatically subscribe all nodes address" + default n + help + Automatically subscribe all nodes address when friendship + established. + endif # BLE_MESH_LOW_POWER config BLE_MESH_FRIEND diff --git a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_ble.c b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_ble.c index 35c4bc64a1..978f701f2e 100644 --- a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_ble.c +++ b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_ble.c @@ -82,7 +82,7 @@ static void btc_ble_mesh_ble_callback(esp_ble_mesh_ble_cb_param_t *cb_params, ui msg.pid = BTC_PID_BLE_MESH_BLE_COEX; msg.act = act; - btc_transfer_context(&msg, cb_params, sizeof(esp_ble_mesh_ble_cb_param_t), + btc_transfer_context(&msg, cb_params, cb_params == NULL ? 0 : sizeof(esp_ble_mesh_ble_cb_param_t), btc_ble_mesh_ble_copy_req_data); } diff --git a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_config_model.c b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_config_model.c index 02fc518f8b..360b37a44b 100644 --- a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_config_model.c +++ b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_config_model.c @@ -298,7 +298,7 @@ static void btc_ble_mesh_config_client_callback(esp_ble_mesh_cfg_client_cb_param msg.pid = BTC_PID_CONFIG_CLIENT; msg.act = act; - btc_transfer_context(&msg, cb_params, sizeof(esp_ble_mesh_cfg_client_cb_param_t), + btc_transfer_context(&msg, cb_params, cb_params == NULL ? 0 : sizeof(esp_ble_mesh_cfg_client_cb_param_t), btc_ble_mesh_config_client_copy_req_data); } @@ -702,7 +702,7 @@ static void btc_ble_mesh_config_server_callback(esp_ble_mesh_cfg_server_cb_param msg.pid = BTC_PID_CONFIG_SERVER; msg.act = act; - btc_transfer_context(&msg, cb_params, sizeof(esp_ble_mesh_cfg_server_cb_param_t), NULL); + btc_transfer_context(&msg, cb_params, cb_params == NULL ? 0 : sizeof(esp_ble_mesh_cfg_server_cb_param_t), NULL); } void bt_mesh_config_server_cb_evt_to_btc(uint8_t evt_type, struct bt_mesh_model *model, diff --git a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_generic_model.c b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_generic_model.c index 6563c3ea0b..2761fa1b06 100644 --- a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_generic_model.c +++ b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_generic_model.c @@ -368,7 +368,7 @@ static void btc_ble_mesh_generic_client_callback(esp_ble_mesh_generic_client_cb_ msg.pid = BTC_PID_GENERIC_CLIENT; msg.act = act; - btc_transfer_context(&msg, cb_params, sizeof(esp_ble_mesh_generic_client_cb_param_t), + btc_transfer_context(&msg, cb_params, cb_params == NULL ? 0 : sizeof(esp_ble_mesh_generic_client_cb_param_t), btc_ble_mesh_generic_client_copy_req_data); } @@ -685,7 +685,7 @@ static void btc_ble_mesh_generic_server_callback(esp_ble_mesh_generic_server_cb_ msg.pid = BTC_PID_GENERIC_SERVER; msg.act = act; - btc_transfer_context(&msg, cb_params, sizeof(esp_ble_mesh_generic_server_cb_param_t), + btc_transfer_context(&msg, cb_params, cb_params == NULL ? 0 : sizeof(esp_ble_mesh_generic_server_cb_param_t), btc_ble_mesh_generic_server_copy_req_data); } diff --git a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_health_model.c b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_health_model.c index 8b46048b59..867b532ec3 100644 --- a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_health_model.c +++ b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_health_model.c @@ -231,7 +231,7 @@ static void btc_ble_mesh_health_client_callback(esp_ble_mesh_health_client_cb_pa msg.pid = BTC_PID_HEALTH_CLIENT; msg.act = act; - btc_transfer_context(&msg, cb_params, sizeof(esp_ble_mesh_health_client_cb_param_t), + btc_transfer_context(&msg, cb_params, cb_params == NULL ? 0 : sizeof(esp_ble_mesh_health_client_cb_param_t), btc_ble_mesh_health_client_copy_req_data); } @@ -542,7 +542,7 @@ static void btc_ble_mesh_health_server_callback(esp_ble_mesh_health_server_cb_pa msg.pid = BTC_PID_HEALTH_SERVER; msg.act = act; - btc_transfer_context(&msg, cb_params, sizeof(esp_ble_mesh_health_server_cb_param_t), + btc_transfer_context(&msg, cb_params, cb_params == NULL ? 0 : sizeof(esp_ble_mesh_health_server_cb_param_t), btc_ble_mesh_health_server_copy_req_data); } diff --git a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_lighting_model.c b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_lighting_model.c index 1c3fc68e54..ec711c5018 100644 --- a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_lighting_model.c +++ b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_lighting_model.c @@ -212,7 +212,7 @@ static void btc_ble_mesh_lighting_client_callback(esp_ble_mesh_light_client_cb_p msg.pid = BTC_PID_LIGHTING_CLIENT; msg.act = act; - btc_transfer_context(&msg, cb_params, sizeof(esp_ble_mesh_light_client_cb_param_t), + btc_transfer_context(&msg, cb_params, cb_params == NULL ? 0 : sizeof(esp_ble_mesh_light_client_cb_param_t), btc_ble_mesh_lighting_client_copy_req_data); } @@ -497,7 +497,7 @@ static void btc_ble_mesh_lighting_server_callback(esp_ble_mesh_lighting_server_c msg.pid = BTC_PID_LIGHTING_SERVER; msg.act = act; - btc_transfer_context(&msg, cb_params, sizeof(esp_ble_mesh_lighting_server_cb_param_t), + btc_transfer_context(&msg, cb_params, cb_params == NULL ? 0 : sizeof(esp_ble_mesh_lighting_server_cb_param_t), btc_ble_mesh_lighting_server_copy_req_data); } diff --git a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_prov.c b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_prov.c index 0f41e512f9..7ffe09ce63 100644 --- a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_prov.c +++ b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_prov.c @@ -368,7 +368,7 @@ static bt_status_t btc_ble_mesh_model_callback(esp_ble_mesh_model_cb_param_t *pa msg.pid = BTC_PID_MODEL; msg.act = act; - ret = btc_transfer_context(&msg, param, sizeof(esp_ble_mesh_model_cb_param_t), + ret = btc_transfer_context(&msg, param, param == NULL ? 0 : sizeof(esp_ble_mesh_model_cb_param_t), btc_ble_mesh_model_copy_req_data); if (ret != BT_STATUS_SUCCESS) { BT_ERR("btc_transfer_context failed"); @@ -528,7 +528,7 @@ static bt_status_t btc_ble_mesh_prov_callback(esp_ble_mesh_prov_cb_param_t *para msg.pid = BTC_PID_PROV; msg.act = act; - ret = btc_transfer_context(&msg, param, sizeof(esp_ble_mesh_prov_cb_param_t), NULL); + ret = btc_transfer_context(&msg, param, param == NULL ? 0 : sizeof(esp_ble_mesh_prov_cb_param_t), NULL); if (ret != BT_STATUS_SUCCESS) { BT_ERR("btc_transfer_context failed"); } diff --git a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_sensor_model.c b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_sensor_model.c index c89ff4a7d4..c33be507c0 100644 --- a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_sensor_model.c +++ b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_sensor_model.c @@ -450,7 +450,7 @@ static void btc_ble_mesh_sensor_client_callback(esp_ble_mesh_sensor_client_cb_pa msg.pid = BTC_PID_SENSOR_CLIENT; msg.act = act; - btc_transfer_context(&msg, cb_params, sizeof(esp_ble_mesh_sensor_client_cb_param_t), + btc_transfer_context(&msg, cb_params, cb_params == NULL ? 0 : sizeof(esp_ble_mesh_sensor_client_cb_param_t), btc_ble_mesh_sensor_client_copy_req_data); } @@ -817,7 +817,7 @@ static void btc_ble_mesh_sensor_server_callback(esp_ble_mesh_sensor_server_cb_pa msg.pid = BTC_PID_SENSOR_SERVER; msg.act = act; - btc_transfer_context(&msg, cb_params, sizeof(esp_ble_mesh_sensor_server_cb_param_t), + btc_transfer_context(&msg, cb_params, cb_params == NULL ? 0 : sizeof(esp_ble_mesh_sensor_server_cb_param_t), btc_ble_mesh_sensor_server_copy_req_data); } diff --git a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_time_scene_model.c b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_time_scene_model.c index fa2d4ab7ea..67862cb257 100644 --- a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_time_scene_model.c +++ b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_time_scene_model.c @@ -214,7 +214,7 @@ static void btc_ble_mesh_time_scene_client_callback(esp_ble_mesh_time_scene_clie msg.pid = BTC_PID_TIME_SCENE_CLIENT; msg.act = act; - btc_transfer_context(&msg, cb_params, sizeof(esp_ble_mesh_time_scene_client_cb_param_t), + btc_transfer_context(&msg, cb_params, cb_params == NULL ? 0 : sizeof(esp_ble_mesh_time_scene_client_cb_param_t), btc_ble_mesh_time_scene_client_copy_req_data); } @@ -401,7 +401,7 @@ static void btc_ble_mesh_time_scene_server_callback(esp_ble_mesh_time_scene_serv msg.pid = BTC_PID_TIME_SCENE_SERVER; msg.act = act; - btc_transfer_context(&msg, cb_params, sizeof(esp_ble_mesh_time_scene_server_cb_param_t), NULL); + btc_transfer_context(&msg, cb_params, cb_params == NULL ? 0 : sizeof(esp_ble_mesh_time_scene_server_cb_param_t), NULL); } void bt_mesh_time_scene_server_cb_evt_to_btc(uint8_t evt_type, struct bt_mesh_model *model, diff --git a/components/bt/esp_ble_mesh/mesh_core/beacon.c b/components/bt/esp_ble_mesh/mesh_core/beacon.c index 31d09aa05a..981f88edcd 100644 --- a/components/bt/esp_ble_mesh/mesh_core/beacon.c +++ b/components/bt/esp_ble_mesh/mesh_core/beacon.c @@ -374,9 +374,19 @@ static void secure_beacon_recv(struct net_buf_simple *buf) cache_add(data, sub); - /* If we have NetKey0 accept initiation only from it */ + /* Spec v1.0.1, Section 3.8.4: + * If a node on a primary subnet receives an update on + * the primary subnet, it shall propagate the IV update + * to all other subnets. If a node on a primary subnet + * receives an IV update on any other subnet, the update + * shall be ignored. + * If a node on a primary subnet receives an key update + * on any other subnet, the update shall not be ignored. + */ if (bt_mesh_primary_subnet_exist() && - sub->net_idx != BLE_MESH_KEY_PRIMARY) { + sub->net_idx != BLE_MESH_KEY_PRIMARY && + BLE_MESH_IV_UPDATE(flags) && + !BLE_MESH_KEY_REFRESH(flags)) { BT_WARN("Ignoring secure beacon on non-primary subnet"); goto update_stats; } @@ -390,7 +400,15 @@ static void secure_beacon_recv(struct net_buf_simple *buf) bt_mesh_beacon_ivu_initiator(false); } - iv_change = bt_mesh_net_iv_update(iv_index, BLE_MESH_IV_UPDATE(flags)); + /* If a node on a primary subnet receives an IV update on any other subnet, + * the IV update shall be ignored. And if a node on a non-primary subnet + * receives an IV update on primary subnet, the IV update shall be ignored, + * because it doesn't have a primary network key. + */ + if ((bt_mesh_primary_subnet_exist() && sub->net_idx == BLE_MESH_KEY_PRIMARY) || + (!bt_mesh_primary_subnet_exist() && sub->net_idx != BLE_MESH_KEY_PRIMARY)) { + iv_change = bt_mesh_net_iv_update(iv_index, BLE_MESH_IV_UPDATE(flags)); + } kr_change = bt_mesh_kr_update(sub, BLE_MESH_KEY_REFRESH(flags), new_key); if (kr_change) { diff --git a/components/bt/esp_ble_mesh/mesh_core/cfg_srv.c b/components/bt/esp_ble_mesh/mesh_core/cfg_srv.c index 12f910986d..2818936d91 100644 --- a/components/bt/esp_ble_mesh/mesh_core/cfg_srv.c +++ b/components/bt/esp_ble_mesh/mesh_core/cfg_srv.c @@ -197,6 +197,21 @@ static bool app_key_is_valid(uint16_t app_idx) return false; } +static bool mod_pub_app_key_bound(struct bt_mesh_model *model, + uint16_t app_idx) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(model->keys); i++) { + if (model->keys[i] == app_idx) { + return true; + } + } + + BT_ERR("Appkey(0x%02x) not bound to this model.", app_idx); + return false; +} + static uint8_t _mod_pub_set(struct bt_mesh_model *model, uint16_t pub_addr, uint16_t app_idx, uint8_t cred_flag, uint8_t ttl, uint8_t period, uint8_t retransmit, bool store) @@ -237,7 +252,11 @@ static uint8_t _mod_pub_set(struct bt_mesh_model *model, uint16_t pub_addr, return STATUS_SUCCESS; } - if (!bt_mesh_app_key_find(app_idx)) { + /* For case MESH/NODE/CFG/MP/BI-03-C, need to check if appkey + * is bound to model identified by the ModelIdentifier. + */ + if (!bt_mesh_app_key_find(app_idx) || + !mod_pub_app_key_bound(model, app_idx)) { return STATUS_INVALID_APPKEY; } @@ -3049,7 +3068,7 @@ static void heartbeat_pub_set(struct bt_mesh_model *model, goto failed; } - if (param->period_log > 0x10) { + if (param->period_log > 0x11) { status = STATUS_CANNOT_SET; goto failed; } @@ -3202,19 +3221,18 @@ static void heartbeat_sub_set(struct bt_mesh_model *model, } if (sub_src == BLE_MESH_ADDR_UNASSIGNED || - sub_dst == BLE_MESH_ADDR_UNASSIGNED || - sub_period == 0x00) { + sub_dst == BLE_MESH_ADDR_UNASSIGNED || + sub_period == 0x00) { /* Only an explicit address change to unassigned should * trigger clearing of the values according to * MESH/NODE/CFG/HBS/BV-02-C. */ if (sub_src == BLE_MESH_ADDR_UNASSIGNED || - sub_dst == BLE_MESH_ADDR_UNASSIGNED) { + sub_dst == BLE_MESH_ADDR_UNASSIGNED) { cfg->hb_sub.src = BLE_MESH_ADDR_UNASSIGNED; cfg->hb_sub.dst = BLE_MESH_ADDR_UNASSIGNED; cfg->hb_sub.min_hops = BLE_MESH_TTL_MAX; cfg->hb_sub.max_hops = 0U; - cfg->hb_sub.count = 0U; } period_ms = 0; @@ -3240,6 +3258,11 @@ static void heartbeat_sub_set(struct bt_mesh_model *model, hb_sub_send_status(model, ctx, STATUS_SUCCESS); + /* For case MESH/NODE/CFG/HBS/BV-02-C, set count_log to 0 + * when Heartbeat Subscription Status message is sent. + */ + cfg->hb_sub.count = 0U; + /* MESH/NODE/CFG/HBS/BV-01-C expects the MinHops to be 0x7f after * disabling subscription, but 0x00 for subsequent Get requests. */ diff --git a/components/bt/esp_ble_mesh/mesh_core/main.c b/components/bt/esp_ble_mesh/mesh_core/main.c index 150c458b76..01bebb04be 100644 --- a/components/bt/esp_ble_mesh/mesh_core/main.c +++ b/components/bt/esp_ble_mesh/mesh_core/main.c @@ -78,6 +78,11 @@ int bt_mesh_provision(const uint8_t net_key[16], uint16_t net_idx, memcpy(bt_mesh.dev_key, dev_key, 16); + if (IS_ENABLED(CONFIG_BLE_MESH_LOW_POWER) && + IS_ENABLED(CONFIG_BLE_MESH_LPN_SUB_ALL_NODES_ADDR)) { + bt_mesh_lpn_group_add(BLE_MESH_ADDR_ALL_NODES); + } + if (IS_ENABLED(CONFIG_BLE_MESH_SETTINGS)) { BT_DBG("Storing network information persistently"); bt_mesh_store_net(); @@ -110,6 +115,12 @@ void bt_mesh_node_reset(void) bt_mesh_tx_reset(); if (IS_ENABLED(CONFIG_BLE_MESH_LOW_POWER)) { + if (IS_ENABLED(CONFIG_BLE_MESH_LPN_SUB_ALL_NODES_ADDR)) { + uint16_t group = BLE_MESH_ADDR_ALL_NODES; + + bt_mesh_lpn_group_del(&group, 1); + } + bt_mesh_lpn_disable(true); } diff --git a/components/bt/esp_ble_mesh/mesh_core/net.c b/components/bt/esp_ble_mesh/mesh_core/net.c index a6c86b3f48..40520f2e05 100644 --- a/components/bt/esp_ble_mesh/mesh_core/net.c +++ b/components/bt/esp_ble_mesh/mesh_core/net.c @@ -1188,8 +1188,7 @@ static bool relay_to_adv(enum bt_mesh_net_if net_if) case BLE_MESH_NET_IF_LOCAL: return true; case BLE_MESH_NET_IF_ADV: - return ((bt_mesh_relay_get() == BLE_MESH_RELAY_ENABLED) || - (bt_mesh_friend_get() == BLE_MESH_FRIEND_ENABLED)); + return (bt_mesh_relay_get() == BLE_MESH_RELAY_ENABLED); case BLE_MESH_NET_IF_PROXY: return (bt_mesh_gatt_proxy_get() == BLE_MESH_GATT_PROXY_ENABLED); default: @@ -1221,9 +1220,9 @@ static void bt_mesh_net_relay(struct net_buf_simple *sbuf, } if (rx->net_if == BLE_MESH_NET_IF_ADV && + !rx->friend_cred && bt_mesh_relay_get() != BLE_MESH_RELAY_ENABLED && - bt_mesh_gatt_proxy_get() != BLE_MESH_GATT_PROXY_ENABLED && - bt_mesh_friend_get() != BLE_MESH_FRIEND_ENABLED) { + bt_mesh_gatt_proxy_get() != BLE_MESH_GATT_PROXY_ENABLED) { return; } @@ -1234,7 +1233,7 @@ static void bt_mesh_net_relay(struct net_buf_simple *sbuf, * Anything else (like GATT to adv, or locally originated packets) * use the Network Transmit state. */ - if (rx->net_if == BLE_MESH_NET_IF_ADV) { + if (rx->net_if == BLE_MESH_NET_IF_ADV && !rx->friend_cred) { transmit = bt_mesh_relay_retransmit_get(); } else { transmit = bt_mesh_net_transmit_get(); @@ -1304,6 +1303,7 @@ static void bt_mesh_net_relay(struct net_buf_simple *sbuf, */ if (IS_ENABLED(CONFIG_BLE_MESH_GATT_PROXY_SERVER) && (bt_mesh_gatt_proxy_get() == BLE_MESH_GATT_PROXY_ENABLED || + rx->friend_cred || rx->net_if == BLE_MESH_NET_IF_LOCAL)) { if (bt_mesh_proxy_server_relay(&buf->b, rx->ctx.recv_dst) && BLE_MESH_ADDR_IS_UNICAST(rx->ctx.recv_dst)) { @@ -1311,7 +1311,7 @@ static void bt_mesh_net_relay(struct net_buf_simple *sbuf, } } - if (relay_to_adv(rx->net_if)) { + if (relay_to_adv(rx->net_if) || rx->friend_cred) { #if !defined(CONFIG_BLE_MESH_RELAY_ADV_BUF) bt_mesh_adv_send(buf, NULL, NULL); #else diff --git a/components/bt/esp_ble_mesh/mesh_core/prov.c b/components/bt/esp_ble_mesh/mesh_core/prov.c index 4e9813f7c6..c18c6949cf 100644 --- a/components/bt/esp_ble_mesh/mesh_core/prov.c +++ b/components/bt/esp_ble_mesh/mesh_core/prov.c @@ -1450,18 +1450,22 @@ static void prov_msg_recv(void) return; } - if (type != PROV_FAILED && type != link.expect) { - BT_WARN("Unexpected msg 0x%02x != 0x%02x", type, link.expect); - prov_send_fail_msg(PROV_ERR_UNEXP_PDU); - return; - } - + /* For case MESH/NODE/PROV/BI-15-C, when the node receive a Provisioning PDU + * with the Type field set to the lowest unsupported or RFU value, it sends a + * Provisioning Failed PDU with the Error Code field set to Invalid PDU(0x01). + */ if (type >= ARRAY_SIZE(prov_handlers)) { BT_ERR("Unknown provisioning PDU type 0x%02x", type); prov_send_fail_msg(PROV_ERR_NVAL_PDU); return; } + if (type != PROV_FAILED && type != link.expect) { + BT_WARN("Unexpected msg 0x%02x != 0x%02x", type, link.expect); + prov_send_fail_msg(PROV_ERR_UNEXP_PDU); + return; + } + if (1 + prov_handlers[type].len != link.rx.buf->len) { BT_ERR("Invalid length %u for type 0x%02x", link.rx.buf->len, type); @@ -1666,15 +1670,30 @@ int bt_mesh_pb_gatt_recv(struct bt_mesh_conn *conn, struct net_buf_simple *buf) return -EINVAL; } - type = net_buf_simple_pull_u8(buf); - if (type != PROV_FAILED && type != link.expect) { - BT_WARN("Unexpected msg 0x%02x != 0x%02x", type, link.expect); + /* For case MESH/NODE/PROV/BI-03-C, if the link is closed, when the node receive + * a Provisioning PDU , it will send a Provisioning Failed PDU with the Error Code + * field set to Unexpected PDU(0x03). + */ + if (bt_mesh_atomic_test_bit(link.flags, LINK_INVALID)) { + BT_WARN("Unexpected msg 0x%02x on invalid link", type); prov_send_fail_msg(PROV_ERR_UNEXP_PDU); return -EINVAL; } + /* For case MESH/NODE/PROV/BI-15-C, when the node receive a Provisioning PDU + * with the Type field set to the lowest unsupported or RFU value, it sends a + * Provisioning Failed PDU with the Error Code field set to Invalid PDU(0x01). + */ + type = net_buf_simple_pull_u8(buf); if (type >= ARRAY_SIZE(prov_handlers)) { BT_ERR("Unknown provisioning PDU type 0x%02x", type); + prov_send_fail_msg(PROV_ERR_NVAL_PDU); + return -EINVAL; + } + + if (type != PROV_FAILED && type != link.expect) { + BT_WARN("Unexpected msg 0x%02x != 0x%02x", type, link.expect); + prov_send_fail_msg(PROV_ERR_UNEXP_PDU); return -EINVAL; } diff --git a/components/bt/esp_ble_mesh/mesh_core/provisioner_prov.c b/components/bt/esp_ble_mesh/mesh_core/provisioner_prov.c index 4945e1faee..60ac6c2f03 100644 --- a/components/bt/esp_ble_mesh/mesh_core/provisioner_prov.c +++ b/components/bt/esp_ble_mesh/mesh_core/provisioner_prov.c @@ -2943,6 +2943,12 @@ static void gen_prov_ack(const uint8_t idx, struct prov_rx *rx, struct net_buf_s case PROV_START: pub_key_oob = link[idx].conf_inputs[13]; send_pub_key(idx, pub_key_oob); + /* For case MESH/PVNR/PROV/BV-04-C, if using OOB public key, + * the value of expect_ack_for shall be PROV_PUB_KEY. + */ + if (pub_key_oob) { + return; + } break; case PROV_PUB_KEY: prov_gen_dh_key(idx); diff --git a/components/bt/esp_ble_mesh/mesh_core/scan.c b/components/bt/esp_ble_mesh/mesh_core/scan.c index 753f19bb9c..b840eff9d0 100644 --- a/components/bt/esp_ble_mesh/mesh_core/scan.c +++ b/components/bt/esp_ble_mesh/mesh_core/scan.c @@ -233,14 +233,11 @@ static void bt_mesh_scan_cb(const bt_mesh_addr_t *addr, buf->len = len - 1; -#if 0 - /* TODO: Check with BLE Mesh BQB test cases */ if ((type == BLE_MESH_DATA_MESH_PROV || type == BLE_MESH_DATA_MESH_MESSAGE || type == BLE_MESH_DATA_MESH_BEACON) && (adv_type != BLE_MESH_ADV_NONCONN_IND)) { BT_DBG("Ignore mesh packet (type 0x%02x) with adv_type 0x%02x", type, adv_type); return; } -#endif switch (type) { case BLE_MESH_DATA_MESH_MESSAGE: diff --git a/components/bt/host/bluedroid/Kconfig.in b/components/bt/host/bluedroid/Kconfig.in index 5c0b84c829..46e619041f 100644 --- a/components/bt/host/bluedroid/Kconfig.in +++ b/components/bt/host/bluedroid/Kconfig.in @@ -173,6 +173,13 @@ config BT_GATT_MAX_SR_PROFILES help Maximum GATT Server Profiles Count +config BT_GATT_MAX_SR_ATTRIBUTES + int "Max GATT Service Attributes" + depends on BT_GATTS_ENABLE && BT_BLUEDROID_ENABLED + range 1 500 + default 100 + help + Maximum GATT Service Attributes Count choice BT_GATTS_SEND_SERVICE_CHANGE_MODE @@ -208,6 +215,14 @@ config BT_GATTC_ENABLE help This option can be close when the app work only on gatt server mode +config BT_GATTC_MAX_CACHE_CHAR + int "Max gattc cache characteristic for discover" + depends on BT_GATTC_ENABLE + range 1 500 + default 40 + help + Maximum GATTC cache characteristic count + config BT_GATTC_CACHE_NVS_FLASH bool "Save gattc cache data to nvs flash" depends on BT_GATTC_ENABLE @@ -1030,7 +1045,7 @@ config BT_SMP_ENABLE config BT_BLE_ACT_SCAN_REP_ADV_SCAN bool "Report adv data and scan response individually when BLE active scan" - depends on BT_BLUEDROID_ENABLED && (BTDM_CTRL_MODE_BTDM || BTDM_CTRL_MODE_BLE_ONLY) + depends on BT_BLUEDROID_ENABLED && BT_BLE_ENABLED default n help Originally, when doing BLE active scan, Bluedroid will not report adv to application layer diff --git a/components/bt/host/bluedroid/api/esp_gatts_api.c b/components/bt/host/bluedroid/api/esp_gatts_api.c index 881aec7fe7..10b82a1c7d 100644 --- a/components/bt/host/bluedroid/api/esp_gatts_api.c +++ b/components/bt/host/bluedroid/api/esp_gatts_api.c @@ -85,7 +85,7 @@ esp_err_t esp_ble_gatts_create_service(esp_gatt_if_t gatts_if, esp_err_t esp_ble_gatts_create_attr_tab(const esp_gatts_attr_db_t *gatts_attr_db, esp_gatt_if_t gatts_if, - uint8_t max_nb_attr, + uint16_t max_nb_attr, uint8_t srvc_inst_id) { btc_msg_t msg = {0}; @@ -93,6 +93,11 @@ esp_err_t esp_ble_gatts_create_attr_tab(const esp_gatts_attr_db_t *gatts_attr_db ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED); + if (max_nb_attr > ESP_GATT_ATTR_HANDLE_MAX) { + LOG_ERROR("The number of attribute should not be greater than CONFIG_BT_GATT_MAX_SR_ATTRIBUTES\n"); + return ESP_ERR_INVALID_ARG; + } + msg.sig = BTC_SIG_API_CALL; msg.pid = BTC_PID_GATTS; msg.act = BTC_GATTS_ACT_CREATE_ATTR_TAB; diff --git a/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h b/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h index 9792bc2b71..57bd34e687 100644 --- a/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h +++ b/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h @@ -143,8 +143,8 @@ typedef enum { ESP_GAP_BLE_PASSKEY_NOTIF_EVT, /*!< passkey notification event */ ESP_GAP_BLE_PASSKEY_REQ_EVT, /*!< passkey request event */ ESP_GAP_BLE_OOB_REQ_EVT, /*!< OOB request event */ - ESP_GAP_BLE_LOCAL_IR_EVT, /*!< BLE local IR event */ - ESP_GAP_BLE_LOCAL_ER_EVT, /*!< BLE local ER event */ + ESP_GAP_BLE_LOCAL_IR_EVT, /*!< BLE local IR (identity Root 128-bit random static value used to generate Long Term Key) event */ + ESP_GAP_BLE_LOCAL_ER_EVT, /*!< BLE local ER (Encryption Root vakue used to genrate identity resolving key) event */ ESP_GAP_BLE_NC_REQ_EVT, /*!< Numeric Comparison request event */ #if (BLE_42_FEATURE_SUPPORT == TRUE) ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT, /*!< When stop adv complete, the event comes */ @@ -287,19 +287,19 @@ typedef enum { /* relate to BTA_DM_BLE_SEC_xxx in bta/bta_api.h */ typedef enum { ESP_BLE_SEC_ENCRYPT = 1, /*!< relate to BTA_DM_BLE_SEC_ENCRYPT in bta/bta_api.h. If the device has already - bonded, the stack will used LTK to encrypt with the remote device directly. + bonded, the stack will used Long Term Key (LTK) to encrypt with the remote device directly. Else if the device hasn't bonded, the stack will used the default authentication request used the esp_ble_gap_set_security_param function set by the user. */ - ESP_BLE_SEC_ENCRYPT_NO_MITM, /*!< relate to BTA_DM_BLE_SEC_ENCRYPT_NO_MITM in bta/bta_api.h. If the device has already - bonded, the stack will check the LTK Whether the authentication request has been met, if met, used the LTK - to encrypt with the remote device directly, else Re-pair with the remote device. - Else if the device hasn't bonded, the stack will used NO MITM authentication request in the current link instead of - used the authreq in the esp_ble_gap_set_security_param function set by the user. */ - ESP_BLE_SEC_ENCRYPT_MITM, /*!< relate to BTA_DM_BLE_SEC_ENCRYPT_MITM in bta/bta_api.h. If the device has already - bonded, the stack will check the LTK Whether the authentication request has been met, if met, used the LTK - to encrypt with the remote device directly, else Re-pair with the remote device. - Else if the device hasn't bonded, the stack will used MITM authentication request in the current link instead of - used the authreq in the esp_ble_gap_set_security_param function set by the user. */ + ESP_BLE_SEC_ENCRYPT_NO_MITM, /*!< relate to BTA_DM_BLE_SEC_ENCRYPT_NO_MITM in bta/bta_api.h. If the device has been already + bonded, the stack will check the LTK (Long Term Key) Whether the authentication request has been met, and if met, use the LTK + to encrypt with the remote device directly, else re-pair with the remote device. + Else if the device hasn't been bonded, the stack will use NO MITM authentication request in the current link instead of + using the authreq in the esp_ble_gap_set_security_param function set by the user. */ + ESP_BLE_SEC_ENCRYPT_MITM, /*!< relate to BTA_DM_BLE_SEC_ENCRYPT_MITM in bta/bta_api.h. If the device has been already + bonded, the stack will check the LTK (Long Term Key) whether the authentication request has been met, and if met, use the LTK + to encrypt with the remote device directly, else re-pair with the remote device. + Else if the device hasn't been bonded, the stack will use MITM authentication request in the current link instead of + using the authreq in the esp_ble_gap_set_security_param function set by the user. */ }esp_ble_sec_act_t; typedef enum { @@ -760,6 +760,9 @@ typedef uint8_t esp_ble_gap_sync_t; typedef uint8_t esp_ble_gap_adv_type_t; +/// Extend advertising tx power, range: [-127, +126] dBm +#define EXT_ADV_TX_PWR_NO_PREFERENCE (127) /*!< host has no preference for tx power */ + /** * @brief ext adv parameters */ @@ -1757,8 +1760,8 @@ esp_err_t esp_ble_get_bond_device_list(int *dev_num, esp_ble_bond_dev_t *dev_lis * SMP in response to ESP_GAP_BLE_OOB_REQ_EVT * * @param[in] bd_addr: BD address of the peer device. -* @param[in] TK: TK value, the TK value shall be a 128-bit random number -* @param[in] len: length of tk, should always be 128-bit +* @param[in] TK: Temporary Key value, the TK value shall be a 128-bit random number +* @param[in] len: length of temporary key, should always be 128-bit * * @return - ESP_OK : success * - other : failed diff --git a/components/bt/host/bluedroid/api/include/api/esp_gatt_defs.h b/components/bt/host/bluedroid/api/include/api/esp_gatt_defs.h index bf9546feba..3e5a9c190f 100644 --- a/components/bt/host/bluedroid/api/include/api/esp_gatt_defs.h +++ b/components/bt/host/bluedroid/api/include/api/esp_gatt_defs.h @@ -18,7 +18,7 @@ extern "C" { /// GATT INVALID HANDLE #define ESP_GATT_ILLEGAL_HANDLE 0 /// GATT attribute max handle -#define ESP_GATT_ATTR_HANDLE_MAX 100 +#define ESP_GATT_ATTR_HANDLE_MAX UC_CONFIG_BT_GATT_MAX_SR_ATTRIBUTES #define ESP_GATT_MAX_READ_MULTI_HANDLES 10 /* Max attributes to read in one request */ diff --git a/components/bt/host/bluedroid/api/include/api/esp_gatts_api.h b/components/bt/host/bluedroid/api/include/api/esp_gatts_api.h index 6215f57f7e..ae1a0245b8 100644 --- a/components/bt/host/bluedroid/api/include/api/esp_gatts_api.h +++ b/components/bt/host/bluedroid/api/include/api/esp_gatts_api.h @@ -351,7 +351,7 @@ esp_err_t esp_ble_gatts_create_service(esp_gatt_if_t gatts_if, */ esp_err_t esp_ble_gatts_create_attr_tab(const esp_gatts_attr_db_t *gatts_attr_db, esp_gatt_if_t gatts_if, - uint8_t max_nb_attr, + uint16_t max_nb_attr, uint8_t srvc_inst_id); /** * @brief This function is called to add an included service. This function have to be called between diff --git a/components/bt/host/bluedroid/bta/dm/bta_dm_api.c b/components/bt/host/bluedroid/bta/dm/bta_dm_api.c index ca1fc27a94..c00c624bc5 100644 --- a/components/bt/host/bluedroid/bta/dm/bta_dm_api.c +++ b/components/bt/host/bluedroid/bta/dm/bta_dm_api.c @@ -2820,6 +2820,7 @@ void BTA_DmBleGapExtAdvSetRemove(UINT8 instance) if ((p_msg = (tBTA_DM_API_BLE_EXT_ADV_SET_REMOVE *) osi_malloc(sizeof(tBTA_DM_API_BLE_EXT_ADV_SET_REMOVE))) != NULL) { memset(p_msg, 0, sizeof(tBTA_DM_API_BLE_EXT_ADV_SET_REMOVE)); p_msg->hdr.event = BTA_DM_API_EXT_ADV_SET_REMOVE_EVT; + p_msg->instance = instance; //start sent the msg to the bta system control moudle bta_sys_sendmsg(p_msg); } else { diff --git a/components/bt/host/bluedroid/bta/gatt/bta_gattc_cache.c b/components/bt/host/bluedroid/bta/gatt/bta_gattc_cache.c index ba232cb1d1..d8af854525 100644 --- a/components/bt/host/bluedroid/bta/gatt/bta_gattc_cache.c +++ b/components/bt/host/bluedroid/bta/gatt/bta_gattc_cache.c @@ -541,7 +541,6 @@ void bta_gattc_start_disc_char_dscp(UINT16 conn_id, tBTA_GATTC_SERV *p_srvc_cb) if (bta_gattc_discover_procedure(conn_id, p_srvc_cb, GATT_DISC_CHAR_DSCPT) != 0) { bta_gattc_char_dscpt_disc_cmpl(conn_id, p_srvc_cb); } - } void bta_gattc_update_include_service(const list_t *services) { @@ -693,7 +692,9 @@ static void bta_gattc_char_dscpt_disc_cmpl(UINT16 conn_id, tBTA_GATTC_SERV *p_sr { tBTA_GATTC_ATTR_REC *p_rec = NULL; - if (--p_srvc_cb->total_char > 0) { + /* Recursive function will cause BTU stack overflow when there are a large number of characteristic + * without descriptor to discover. So replace it with while function */ + while (--p_srvc_cb->total_char > 0) { p_rec = p_srvc_cb->p_srvc_list + (++ p_srvc_cb->cur_char_idx); /* add the next characteristic into cache */ bta_gattc_add_char_to_cache (p_srvc_cb, @@ -701,11 +702,14 @@ static void bta_gattc_char_dscpt_disc_cmpl(UINT16 conn_id, tBTA_GATTC_SERV *p_sr p_rec->s_handle, &p_rec->uuid, p_rec->property); + /* start to discover next characteristic for descriptor */ + if (bta_gattc_discover_procedure(conn_id, p_srvc_cb, GATT_DISC_CHAR_DSCPT) == 0) { + /* send att req and wait for att rsp */ + break; + } + } - /* start discoverying next characteristic for char descriptor */ - bta_gattc_start_disc_char_dscp(conn_id, p_srvc_cb); - } else - /* all characteristic has been explored, start with next service if any */ + if (p_srvc_cb->total_char == 0) /* all characteristic has been explored, start with next service if any */ { #if (defined BTA_GATT_DEBUG && BTA_GATT_DEBUG == TRUE) APPL_TRACE_ERROR("all char has been explored"); @@ -772,7 +776,7 @@ static tBTA_GATT_STATUS bta_gattc_add_srvc_to_list(tBTA_GATTC_SERV *p_srvc_cb, /* allocate bigger buffer ?? */ status = GATT_DB_FULL; - APPL_TRACE_ERROR("service not added, no resources or wrong state"); + APPL_TRACE_ERROR("service not added, no resources or wrong state, see CONFIG_BT_GATTC_MAX_CACHE_CHAR"); } return status; } @@ -814,7 +818,7 @@ static tBTA_GATT_STATUS bta_gattc_add_char_to_list(tBTA_GATTC_SERV *p_srvc_cb, } p_srvc_cb->next_avail_idx ++; } else { - APPL_TRACE_ERROR("char not added, no resources"); + APPL_TRACE_ERROR("char not added, no resources, see CONFIG_BT_GATTC_MAX_CACHE_CHAR"); /* allocate bigger buffer ?? */ status = BTA_GATT_DB_FULL; } diff --git a/components/bt/host/bluedroid/bta/gatt/include/bta_gattc_int.h b/components/bt/host/bluedroid/bta/gatt/include/bta_gattc_int.h index 06a8f5f187..4262f20b70 100644 --- a/components/bt/host/bluedroid/bta/gatt/include/bta_gattc_int.h +++ b/components/bt/host/bluedroid/bta/gatt/include/bta_gattc_int.h @@ -270,7 +270,6 @@ typedef struct { } tBTA_GATTC_ATTR_REC; -#define BTA_GATTC_MAX_CACHE_CHAR 40 #define BTA_GATTC_ATTR_LIST_SIZE (BTA_GATTC_MAX_CACHE_CHAR * sizeof(tBTA_GATTC_ATTR_REC)) #ifndef BTA_GATTC_CACHE_SRVR_SIZE @@ -305,10 +304,10 @@ typedef struct { tBTA_GATTC_ATTR_REC *p_srvc_list; UINT8 cur_srvc_idx; - UINT8 cur_char_idx; - UINT8 next_avail_idx; + UINT16 cur_char_idx; + UINT16 next_avail_idx; UINT8 total_srvc; - UINT8 total_char; + UINT16 total_char; UINT16 total_attr; UINT8 srvc_hdl_chg; /* service handle change indication pending */ UINT16 attr_index; /* cahce NV saving/loading attribute index */ diff --git a/components/bt/host/bluedroid/bta/include/bta/bta_api.h b/components/bt/host/bluedroid/bta/include/bta/bta_api.h index c3609ff16c..6eea241d77 100644 --- a/components/bt/host/bluedroid/bta/include/bta/bta_api.h +++ b/components/bt/host/bluedroid/bta/include/bta/bta_api.h @@ -1469,7 +1469,7 @@ typedef struct { tBLE_ADDR_TYPE peer_addr_type; BD_ADDR peer_addr; tBTA_BLE_AFP filter_policy; - UINT8 tx_power; + INT8 tx_power; tBTA_DM_BLE_GAP_PHY primary_phy; UINT8 max_skip; tBTA_DM_BLE_GAP_PHY secondary_phy; diff --git a/components/bt/host/bluedroid/btc/core/btc_dm.c b/components/bt/host/bluedroid/btc/core/btc_dm.c index 46417b778f..c80f47cf77 100644 --- a/components/bt/host/bluedroid/btc/core/btc_dm.c +++ b/components/bt/host/bluedroid/btc/core/btc_dm.c @@ -104,7 +104,8 @@ void btc_dm_sec_evt(tBTA_DM_SEC_EVT event, tBTA_DM_SEC *data) msg.pid = BTC_PID_DM_SEC; msg.act = event; - btc_transfer_context(&msg, (btc_dm_sec_args_t *)data, sizeof(btc_dm_sec_args_t), btc_dm_sec_arg_deep_copy); + btc_transfer_context(&msg, (btc_dm_sec_args_t *)data, + data == NULL ? 0 : sizeof(btc_dm_sec_args_t), btc_dm_sec_arg_deep_copy); } static void btc_enable_bluetooth_evt(tBTA_STATUS status) diff --git a/components/bt/host/bluedroid/btc/profile/std/a2dp/btc_a2dp_sink.c b/components/bt/host/bluedroid/btc/profile/std/a2dp/btc_a2dp_sink.c index 3482dcfee5..5b753f703d 100644 --- a/components/bt/host/bluedroid/btc/profile/std/a2dp/btc_a2dp_sink.c +++ b/components/bt/host/bluedroid/btc/profile/std/a2dp/btc_a2dp_sink.c @@ -415,7 +415,8 @@ static void btc_a2dp_sink_handle_decoder_reset(tBTC_MEDIA_SINK_CFG_UPDATE *p_msg a2dp_sink_local_param.btc_aa_snk_cb.rx_flush = FALSE; APPL_TRACE_EVENT("Reset to sink role"); status = OI_CODEC_SBC_DecoderReset(&a2dp_sink_local_param.context, a2dp_sink_local_param.contextData, - sizeof(a2dp_sink_local_param.contextData), 2, 2, FALSE, FALSE); + sizeof(a2dp_sink_local_param.contextData), a2dp_sink_local_param.btc_aa_snk_cb.channel_count, + a2dp_sink_local_param.btc_aa_snk_cb.channel_count, FALSE, FALSE); if (!OI_SUCCESS(status)) { APPL_TRACE_ERROR("OI_CODEC_SBC_DecoderReset failed with error code %d\n", status); } diff --git a/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gatts.c b/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gatts.c index 4f49c8872e..dacf03c92a 100644 --- a/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gatts.c +++ b/components/bt/host/bluedroid/btc/profile/std/gatt/btc_gatts.c @@ -127,7 +127,7 @@ void btc_gatts_arg_deep_copy(btc_msg_t *msg, void *p_dest, void *p_src) break; } case BTC_GATTS_ACT_CREATE_ATTR_TAB: { - uint8_t num_attr = src->create_attr_tab.max_nb_attr; + uint16_t num_attr = src->create_attr_tab.max_nb_attr; if (src->create_attr_tab.gatts_attr_db && (num_attr > 0)) { dst->create_attr_tab.gatts_attr_db = (esp_gatts_attr_db_t *) osi_malloc(sizeof(esp_gatts_attr_db_t) * num_attr); if (dst->create_attr_tab.gatts_attr_db) { @@ -217,7 +217,7 @@ void btc_gatts_arg_deep_free(btc_msg_t *msg) static void btc_gatts_act_create_attr_tab(esp_gatts_attr_db_t *gatts_attr_db, esp_gatt_if_t gatts_if, - uint8_t max_nb_attr, + uint16_t max_nb_attr, uint8_t srvc_inst_id) { uint16_t uuid = 0; @@ -568,24 +568,24 @@ static void btc_gatts_inter_cb(tBTA_GATTS_EVT event, tBTA_GATTS *p_data) //save the service handle to the btc module after used //the attribute table method to creat a service bta_to_btc_uuid(&btc_creat_tab_env.svc_uuid, &p_data->create.uuid); - uint8_t index = btc_creat_tab_env.handle_idx; + uint16_t index = btc_creat_tab_env.handle_idx; btc_creat_tab_env.svc_start_hdl = p_data->create.service_id; btc_creat_tab_env.handles[index] = p_data->create.service_id; break; } case BTA_GATTS_ADD_INCL_SRVC_EVT: { - uint8_t index = btc_creat_tab_env.handle_idx; + uint16_t index = btc_creat_tab_env.handle_idx; btc_creat_tab_env.handles[index] = p_data->add_result.attr_id; break; } case BTA_GATTS_ADD_CHAR_EVT: { - uint8_t index = btc_creat_tab_env.handle_idx; + uint16_t index = btc_creat_tab_env.handle_idx; btc_creat_tab_env.handles[index] = p_data->add_result.attr_id - 1; btc_creat_tab_env.handles[index+1] = p_data->add_result.attr_id; break; } case BTA_GATTS_ADD_CHAR_DESCR_EVT: { - uint8_t index = btc_creat_tab_env.handle_idx; + uint16_t index = btc_creat_tab_env.handle_idx; btc_creat_tab_env.handles[index] = p_data->add_result.attr_id; break; } diff --git a/components/bt/host/bluedroid/btc/profile/std/include/btc_gatts.h b/components/bt/host/bluedroid/btc/profile/std/include/btc_gatts.h index 35a09a5fdd..866495646c 100644 --- a/components/bt/host/bluedroid/btc/profile/std/include/btc_gatts.h +++ b/components/bt/host/bluedroid/btc/profile/std/include/btc_gatts.h @@ -55,7 +55,7 @@ typedef union { struct create_attr_tab_args{ esp_gatt_if_t gatts_if; uint8_t srvc_inst_id; - uint8_t max_nb_attr; + uint16_t max_nb_attr; esp_gatts_attr_db_t *gatts_attr_db; }create_attr_tab; @@ -149,8 +149,8 @@ typedef struct { esp_bt_uuid_t svc_uuid; bool is_tab_creat_svc; bool is_use_svc; - uint8_t num_handle; - uint8_t handle_idx; + uint16_t num_handle; + uint16_t handle_idx; uint16_t handles[ESP_GATT_ATTR_HANDLE_MAX]; } esp_btc_creat_tab_t; diff --git a/components/bt/host/bluedroid/common/include/common/bluedroid_user_config.h b/components/bt/host/bluedroid/common/include/common/bluedroid_user_config.h index e6aae09935..4362cd10fd 100644 --- a/components/bt/host/bluedroid/common/include/common/bluedroid_user_config.h +++ b/components/bt/host/bluedroid/common/include/common/bluedroid_user_config.h @@ -134,6 +134,12 @@ #endif //GATTC CACHE +#ifdef CONFIG_BT_GATTC_MAX_CACHE_CHAR +#define UC_BT_GATTC_MAX_CACHE_CHAR CONFIG_BT_GATTC_MAX_CACHE_CHAR +#else +#define UC_BT_GATTC_MAX_CACHE_CHAR 40 +#endif + #ifdef CONFIG_BT_GATTC_CACHE_NVS_FLASH #define UC_BT_GATTC_CACHE_NVS_FLASH_ENABLED CONFIG_BT_GATTC_CACHE_NVS_FLASH #else @@ -258,6 +264,11 @@ #define UC_CONFIG_BT_GATT_MAX_SR_PROFILES 8 #endif +#ifdef CONFIG_BT_GATT_MAX_SR_ATTRIBUTES +#define UC_CONFIG_BT_GATT_MAX_SR_ATTRIBUTES CONFIG_BT_GATT_MAX_SR_ATTRIBUTES +#else +#define UC_CONFIG_BT_GATT_MAX_SR_ATTRIBUTES 100 +#endif #ifdef CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MODE #define UC_BT_GATTS_SEND_SERVICE_CHANGE_MODE CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MODE diff --git a/components/bt/host/bluedroid/common/include/common/bt_target.h b/components/bt/host/bluedroid/common/include/common/bt_target.h index 66688ba13e..83abc9ba8c 100644 --- a/components/bt/host/bluedroid/common/include/common/bt_target.h +++ b/components/bt/host/bluedroid/common/include/common/bt_target.h @@ -21,7 +21,6 @@ #define BT_TARGET_H #include -#include "soc/soc_caps.h" #ifndef BUILDCFG #define BUILDCFG @@ -278,11 +277,6 @@ #define BLE_ESTABLISH_LINK_CONNECTION_TIMEOUT UC_BT_BLE_ESTAB_LINK_CONN_TOUT #endif -#ifdef SOC_BLE_DONT_UPDATE_OWN_RPA -#define BLE_UPDATE_BLE_ADDR_TYPE_RPA FALSE -#else -#define BLE_UPDATE_BLE_ADDR_TYPE_RPA TRUE -#endif //------------------Added from bdroid_buildcfg.h--------------------- #ifndef L2CAP_EXTFEA_SUPPORTED_MASK #define L2CAP_EXTFEA_SUPPORTED_MASK (L2CAP_EXTFEA_ENH_RETRANS | L2CAP_EXTFEA_STREAM_MODE | L2CAP_EXTFEA_NO_CRC | L2CAP_EXTFEA_FIXED_CHNLS) @@ -1203,15 +1197,27 @@ #endif #ifndef BTM_BLE_ADV_TX_POWER +#ifdef CONFIG_IDF_TARGET_ESP32 #define BTM_BLE_ADV_TX_POWER {-12, -9, -6, -3, 0, 3, 6, 9} +#else +#define BTM_BLE_ADV_TX_POWER {-24, -21, -18, -15, -12, -9, -6, -3, 0, 3, 6, 9, 12, 15, 18, 21} +#endif #endif #ifndef BTM_TX_POWER +#ifdef CONFIG_IDF_TARGET_ESP32 #define BTM_TX_POWER {-12, -9, -6, -3, 0, 3, 6, 9} +#else +#define BTM_TX_POWER {-24, -21, -18, -15, -12, -9, -6, -3, 0, 3, 6, 9, 12, 15, 18, 21} +#endif #endif #ifndef BTM_TX_POWER_LEVEL_MAX +#ifdef CONFIG_IDF_TARGET_ESP32 #define BTM_TX_POWER_LEVEL_MAX 7 +#else +#define BTM_TX_POWER_LEVEL_MAX 15 +#endif #endif @@ -2241,6 +2247,10 @@ The maximum number of payload octets that the local device can receive in a sing #define BTA_DM_AVOID_A2DP_ROLESWITCH_ON_INQUIRY FALSE #endif +#ifndef BTA_GATTC_MAX_CACHE_CHAR +#define BTA_GATTC_MAX_CACHE_CHAR UC_BT_GATTC_MAX_CACHE_CHAR +#endif + /****************************************************************************** ** ** Tracing: Include trace header file here. diff --git a/components/bt/host/bluedroid/hci/hci_hal_h4.c b/components/bt/host/bluedroid/hci/hci_hal_h4.c index b99bd429e5..1bf02aa1e3 100644 --- a/components/bt/host/bluedroid/hci/hci_hal_h4.c +++ b/components/bt/host/bluedroid/hci/hci_hal_h4.c @@ -598,7 +598,7 @@ ble_hs_hci_rx_evt(uint8_t *hci_ev, void *arg) if(esp_bluedroid_get_status() == ESP_BLUEDROID_STATUS_UNINITIALIZED) { return 0; } - uint8_t len = hci_ev[1] + 3; + uint16_t len = hci_ev[1] + 3; uint8_t *data = (uint8_t *)malloc(len); data[0] = 0x04; memcpy(&data[1], hci_ev, len - 1); @@ -608,22 +608,17 @@ ble_hs_hci_rx_evt(uint8_t *hci_ev, void *arg) return 0; } -static void *trans_om; -void hci_trans_free_mbuf(void) -{ - os_mbuf_free_chain(trans_om); -} + int ble_hs_rx_data(struct os_mbuf *om, void *arg) { - uint8_t len = om->om_len + 1; + uint16_t len = om->om_len + 1; uint8_t *data = (uint8_t *)malloc(len); data[0] = 0x02; - memcpy(&data[1], om->om_data, len - 1); + os_mbuf_copydata(om, 0, len - 1, &data[1]); host_recv_pkt_cb(data, len); - trans_om = om; free(data); - hci_trans_free_mbuf(); + os_mbuf_free_chain(om); return 0; } diff --git a/components/bt/host/bluedroid/stack/btm/btm_acl.c b/components/bt/host/bluedroid/stack/btm/btm_acl.c index 1fe596ada3..021a80da40 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_acl.c +++ b/components/bt/host/bluedroid/stack/btm/btm_acl.c @@ -347,10 +347,6 @@ void btm_acl_created (BD_ADDR bda, DEV_CLASS dc, UINT8 bdn[BTM_MAX_REM_BD_NAME_L btm_establish_continue (p); return; } - } else { - /* If remote features indicated secure connection (SC) mode, check the remote feautres again*/ - /* this is to prevent from BIAS attack where attacker can downgrade SC mode*/ - btm_read_remote_features (p->hci_handle); } } diff --git a/components/bt/host/bluedroid/stack/btm/btm_ble.c b/components/bt/host/bluedroid/stack/btm/btm_ble.c index 6cac0fd793..962a3ef961 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_ble.c +++ b/components/bt/host/bluedroid/stack/btm/btm_ble.c @@ -1990,7 +1990,7 @@ void btm_ble_conn_complete(UINT8 *p, UINT16 evt_len, BOOLEAN enhanced) } #if (BLE_PRIVACY_SPT == TRUE ) peer_addr_type = bda_type; - match = btm_identity_addr_to_random_pseudo (bda, &bda_type, TRUE); + match = btm_identity_addr_to_random_pseudo (bda, &bda_type, FALSE); /* possiblly receive connection complete with resolvable random on slave role while the device has been paired */ diff --git a/components/bt/host/bluedroid/stack/btm/btm_ble_addr.c b/components/bt/host/bluedroid/stack/btm/btm_ble_addr.c index 52e79692ee..036377c4a5 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_ble_addr.c +++ b/components/bt/host/bluedroid/stack/btm/btm_ble_addr.c @@ -56,8 +56,9 @@ static void btm_gen_resolve_paddr_cmpl(tSMP_ENC *p) p_cb->private_addr[5] = p->param_buf[0]; p_cb->private_addr[4] = p->param_buf[1]; p_cb->private_addr[3] = p->param_buf[2]; + /* set it to controller */ - btsnd_hcic_ble_set_random_addr(p_cb->private_addr); + btm_ble_set_random_addr(p_cb->private_addr); p_cb->exist_addr_bit |= BTM_BLE_GAP_ADDR_BIT_RESOLVABLE; memcpy(p_cb->resolvale_addr, p_cb->private_addr, BD_ADDR_LEN); @@ -66,23 +67,6 @@ static void btm_gen_resolve_paddr_cmpl(tSMP_ENC *p) p_cb->set_local_privacy_cback = NULL; } - if (btm_cb.ble_ctr_cb.inq_var.adv_mode == BTM_BLE_ADV_ENABLE){ - BTM_TRACE_DEBUG("Advertise with new resolvable private address, now."); - /** - * Restart advertising, using new resolvable private address - */ - btm_ble_stop_adv(); - btm_ble_start_adv(); - } - if (btm_cb.ble_ctr_cb.inq_var.state == BTM_BLE_SCANNING){ - BTM_TRACE_DEBUG("Scan with new resolvable private address, now."); - /** - * Restart scaning, using new resolvable private address - */ - btm_ble_stop_scan(); - btm_ble_start_scan(); - } - /* start a periodical timer to refresh random addr */ btu_stop_timer_oneshot(&p_cb->raddr_timer_ent); #if (BTM_BLE_CONFORMANCE_TESTING == TRUE) diff --git a/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c b/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c index 6976996e75..f8624b3f1b 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c +++ b/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c @@ -1018,9 +1018,7 @@ uint32_t BTM_BleUpdateOwnType(uint8_t *own_bda_type, tBTM_START_ADV_CMPL_CBACK * } } else if(*own_bda_type == BLE_ADDR_PUBLIC_ID || *own_bda_type == BLE_ADDR_RANDOM_ID) { if((btm_cb.ble_ctr_cb.addr_mgnt_cb.exist_addr_bit & BTM_BLE_GAP_ADDR_BIT_RESOLVABLE) == BTM_BLE_GAP_ADDR_BIT_RESOLVABLE) { -#if (BLE_UPDATE_BLE_ADDR_TYPE_RPA) *own_bda_type = BLE_ADDR_RANDOM; -#endif btm_cb.ble_ctr_cb.addr_mgnt_cb.own_addr_type = BLE_ADDR_RANDOM; memcpy(btm_cb.ble_ctr_cb.addr_mgnt_cb.private_addr, btm_cb.ble_ctr_cb.addr_mgnt_cb.resolvale_addr, BD_ADDR_LEN); btsnd_hcic_ble_set_random_addr(btm_cb.ble_ctr_cb.addr_mgnt_cb.resolvale_addr); @@ -3675,21 +3673,20 @@ static void btm_ble_process_adv_pkt_cont(BD_ADDR bda, UINT8 addr_type, UINT8 evt 0x04 Scan Response (SCAN_RSP) 0x05-0xFF Reserved for future use */ - //if scan duplicate is enabled, the adv packet without scan response is allowed to report to higher layer - if(p_le_inq_cb->scan_duplicate_filter == BTM_BLE_SCAN_DUPLICATE_ENABLE) { - /* - Bluedroid will put the advertising packet and scan response into a packet and send it to the higher layer. - If two advertising packets are not with the same address, or can't be combined into a packet, then the first advertising - packet will be discarded. So we added the following judgment: - 1. For different addresses, send the last advertising packet to higher layer - 2. For same address and same advertising type (not scan response), send the last advertising packet to higher layer - 3. For same address and scan response, do nothing - */ - int same_addr = memcmp(bda, p_le_inq_cb->adv_addr, BD_ADDR_LEN); - if (same_addr != 0 || (same_addr == 0 && evt_type != BTM_BLE_SCAN_RSP_EVT)) { - btm_ble_process_last_adv_pkt(); - } - } + // The adv packet without scan response is allowed to report to higher layer + /* + Bluedroid will put the advertising packet and scan response into a packet and send it to the higher layer. + If two advertising packets are not with the same address, or can't be combined into a packet, then the first advertising + packet will be discarded. So we added the following judgment: + 1. For different addresses, send the last advertising packet to higher layer + 2. For same address and same advertising type (not scan response), send the last advertising packet to higher layer + 3. For same address and scan response, do nothing + */ + int same_addr = memcmp(bda, p_le_inq_cb->adv_addr, BD_ADDR_LEN); + if (same_addr != 0 || (same_addr == 0 && evt_type != BTM_BLE_SCAN_RSP_EVT)) { + btm_ble_process_last_adv_pkt(); + } + p_i = btm_inq_db_find (bda); @@ -4121,6 +4118,59 @@ tBTM_STATUS btm_ble_stop_adv(void) return rt; } +tBTM_STATUS btm_ble_set_random_addr(BD_ADDR random_bda) +{ + tBTM_STATUS rt = BTM_SUCCESS; + + osi_mutex_lock(&adv_enable_lock, OSI_MUTEX_MAX_TIMEOUT); + osi_mutex_lock(&scan_enable_lock, OSI_MUTEX_MAX_TIMEOUT); + + if (btm_cb.ble_ctr_cb.inq_var.adv_mode == BTM_BLE_ADV_ENABLE) { + if (btsnd_hcic_ble_set_adv_enable (BTM_BLE_ADV_DISABLE)) { + osi_sem_take(&adv_enable_sem, OSI_SEM_MAX_TIMEOUT); + rt = adv_enable_status; + } else { + rt = BTM_BAD_VALUE_RET; + } + } + + if (BTM_BLE_IS_DISCO_ACTIVE(btm_cb.ble_ctr_cb.scan_activity)) { + if (btsnd_hcic_ble_set_scan_enable (BTM_BLE_SCAN_DISABLE, BTM_BLE_SCAN_DUPLICATE_DISABLE)) { + osi_sem_take(&scan_enable_sem, OSI_SEM_MAX_TIMEOUT); + rt = scan_enable_status; + } else { + rt = BTM_BAD_VALUE_RET; + } + } + + if (rt == BTM_SUCCESS) { + btsnd_hcic_ble_set_random_addr(random_bda); + } + + if (btm_cb.ble_ctr_cb.inq_var.adv_mode == BTM_BLE_ADV_ENABLE) { + if (btsnd_hcic_ble_set_adv_enable (BTM_BLE_ADV_ENABLE)) { + osi_sem_take(&adv_enable_sem, OSI_SEM_MAX_TIMEOUT); + rt = adv_enable_status; + } else { + rt = BTM_BAD_VALUE_RET; + } + } + + if (BTM_BLE_IS_DISCO_ACTIVE(btm_cb.ble_ctr_cb.scan_activity)) { + if (btsnd_hcic_ble_set_scan_enable (BTM_BLE_SCAN_ENABLE, btm_cb.ble_ctr_cb.inq_var.scan_duplicate_filter)) { + osi_sem_take(&scan_enable_sem, OSI_SEM_MAX_TIMEOUT); + rt = scan_enable_status; + } else { + rt = BTM_BAD_VALUE_RET; + } + } + + osi_mutex_unlock(&adv_enable_lock); + osi_mutex_unlock(&scan_enable_lock); + + return rt; +} + /******************************************************************************* ** @@ -4250,10 +4300,11 @@ void btm_ble_read_remote_features_complete(UINT8 *p) btsnd_hcic_rmt_ver_req (p_acl_cb->hci_handle); } else{ + uint16_t data_length = controller_get_interface()->get_ble_default_data_packet_length(); + uint16_t data_txtime = controller_get_interface()->get_ble_default_data_packet_txtime(); if (p_acl_cb->transport == BT_TRANSPORT_LE) { - if (HCI_LE_DATA_LEN_EXT_SUPPORTED(p_acl_cb->peer_le_features)) { - uint16_t data_length = controller_get_interface()->get_ble_default_data_packet_length(); - uint16_t data_txtime = controller_get_interface()->get_ble_default_data_packet_txtime(); + if (HCI_LE_DATA_LEN_EXT_SUPPORTED(p_acl_cb->peer_le_features) && + (p_acl_cb->data_length_params.tx_len != data_length)) { p_acl_cb->data_len_updating = true; btsnd_hcic_ble_set_data_length(p_acl_cb->hci_handle, data_length, data_txtime); } diff --git a/components/bt/host/bluedroid/stack/btm/btm_sec.c b/components/bt/host/bluedroid/stack/btm/btm_sec.c index c52d65a263..f99a78c899 100644 --- a/components/bt/host/bluedroid/stack/btm/btm_sec.c +++ b/components/bt/host/bluedroid/stack/btm/btm_sec.c @@ -240,12 +240,6 @@ BOOLEAN BTM_SecRegister(tBTM_APPL_INFO *p_cb_info) if (memcmp(btm_cb.devcb.id_keys.ir, &temp_value, sizeof(BT_OCTET16)) == 0) { btm_ble_reset_id(); } -#if (!BLE_UPDATE_BLE_ADDR_TYPE_RPA) - BD_ADDR peer_addr = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; - BT_OCTET16 peer_irk = {0x0}; - /* add local irk to controller */ - btsnd_hcic_ble_add_device_resolving_list (0, peer_addr, peer_irk, btm_cb.devcb.id_keys.irk); -#endif } else { BTM_TRACE_WARNING("%s p_cb_info->p_le_callback == NULL\n", __func__); } @@ -4030,7 +4024,9 @@ void btm_sec_auth_complete (UINT16 handle, UINT8 status) return; } - p_dev_rec->sec_flags |= BTM_SEC_AUTHENTICATED; + if (!(p_dev_rec->sm4 & BTM_SM4_UPGRADE)) { + p_dev_rec->sec_flags |= BTM_SEC_AUTHENTICATED; + } if (p_dev_rec->pin_code_length >= 16 || p_dev_rec->link_key_type == BTM_LKEY_TYPE_AUTH_COMB || diff --git a/components/bt/host/bluedroid/stack/btm/include/btm_ble_int.h b/components/bt/host/bluedroid/stack/btm/include/btm_ble_int.h index 3d33a3566f..12d95f97f3 100644 --- a/components/bt/host/bluedroid/stack/btm/include/btm_ble_int.h +++ b/components/bt/host/bluedroid/stack/btm/include/btm_ble_int.h @@ -419,6 +419,7 @@ tBTM_STATUS btm_ble_stop_adv(void); tBTM_STATUS btm_ble_start_scan(void); void btm_ble_create_ll_conn_complete (UINT8 status); void btm_ble_create_conn_cancel_complete (UINT8 *p); +tBTM_STATUS btm_ble_set_random_addr(BD_ADDR random_bda); /* LE security function from btm_sec.c */ #if SMP_INCLUDED == TRUE diff --git a/components/bt/host/bluedroid/stack/btu/btu_init.c b/components/bt/host/bluedroid/stack/btu/btu_init.c index aff092dc35..615fbf8019 100644 --- a/components/bt/host/bluedroid/stack/btu/btu_init.c +++ b/components/bt/host/bluedroid/stack/btu/btu_init.c @@ -48,7 +48,7 @@ #define BTU_TASK_STACK_SIZE (BT_BTU_TASK_STACK_SIZE + BT_TASK_EXTRA_STACK_SIZE) #define BTU_TASK_PRIO (BT_TASK_MAX_PRIORITIES - 5) #define BTU_TASK_NAME "BTU_TASK" -#define BTU_TASK_WORKQUEUE_NUM (2) +#define BTU_TASK_WORKQUEUE_NUM (1) #define BTU_TASK_WORKQUEUE0_LEN (0) hash_map_t *btu_general_alarm_hash_map; diff --git a/components/bt/host/bluedroid/stack/hcic/hciblecmds.c b/components/bt/host/bluedroid/stack/hcic/hciblecmds.c index 4369ecc2c8..8aaab5ea2a 100644 --- a/components/bt/host/bluedroid/stack/hcic/hciblecmds.c +++ b/components/bt/host/bluedroid/stack/hcic/hciblecmds.c @@ -1214,7 +1214,7 @@ UINT8 btsnd_hcic_ble_set_extend_rand_address(UINT8 adv_handle, BD_ADDR rand_addr UINT8 btsnd_hcic_ble_set_ext_adv_params(UINT8 adv_handle, UINT16 properties, UINT32 interval_min, UINT32 interval_max, UINT8 channel_map, UINT8 own_addr_type, UINT8 peer_addr_type, BD_ADDR peer_addr, - UINT8 adv_filter_policy, UINT8 adv_tx_power, + UINT8 adv_filter_policy, INT8 adv_tx_power, UINT8 primary_adv_phy, UINT8 secondary_adv_max_skip, UINT8 secondary_adv_phy, UINT8 adv_sid, UINT8 scan_req_ntf_enable) @@ -1244,7 +1244,7 @@ UINT8 btsnd_hcic_ble_set_ext_adv_params(UINT8 adv_handle, UINT16 properties, UIN UINT8_TO_STREAM(pp, peer_addr_type); BDADDR_TO_STREAM (pp, peer_addr); UINT8_TO_STREAM(pp, adv_filter_policy); - UINT8_TO_STREAM(pp, adv_tx_power); + INT8_TO_STREAM(pp, adv_tx_power); UINT8_TO_STREAM(pp, primary_adv_phy); UINT8_TO_STREAM(pp, secondary_adv_max_skip); UINT8_TO_STREAM(pp, secondary_adv_phy); diff --git a/components/bt/host/bluedroid/stack/include/stack/btm_api.h b/components/bt/host/bluedroid/stack/include/stack/btm_api.h index d2dd2c4038..f58b0e2207 100644 --- a/components/bt/host/bluedroid/stack/include/stack/btm_api.h +++ b/components/bt/host/bluedroid/stack/include/stack/btm_api.h @@ -1176,7 +1176,7 @@ typedef void (tBTM_ESCO_CBACK) (tBTM_ESCO_EVT event, tBTM_ESCO_EVT_DATA *p_data) #define BTM_LKEY_TYPE_UNAUTH_COMB_P_256 HCI_LKEY_TYPE_UNAUTH_COMB_P_256 #define BTM_LKEY_TYPE_AUTH_COMB_P_256 HCI_LKEY_TYPE_AUTH_COMB_P_256 -#define BTM_LTK_DERIVED_LKEY_OFFSET 0x20 /* "easy" requirements for LK derived from LTK */ +#define BTM_LTK_DERIVED_LKEY_OFFSET 0x20 /* "easy" requirements for Link Key (LK) derived from Long Term Key */ #define BTM_LKEY_TYPE_IGNORE 0xff /* used when event is response from hci return link keys request */ diff --git a/components/bt/host/bluedroid/stack/include/stack/btm_ble_api.h b/components/bt/host/bluedroid/stack/include/stack/btm_ble_api.h index f7cac0ecd8..5e4504dd88 100644 --- a/components/bt/host/bluedroid/stack/include/stack/btm_ble_api.h +++ b/components/bt/host/bluedroid/stack/include/stack/btm_ble_api.h @@ -385,7 +385,7 @@ typedef UINT8 tBTM_BLE_AD_TYPE; /* adv tx power level */ #define BTM_BLE_ADV_TX_POWER_MIN 0 /* minimum tx power */ -#define BTM_BLE_ADV_TX_POWER_MAX 7 /* maximum tx power */ +#define BTM_BLE_ADV_TX_POWER_MAX BTM_TX_POWER_LEVEL_MAX /* maximum tx power */ typedef UINT8 tBTM_BLE_ADV_TX_POWER; /* adv tx power in dBm */ @@ -767,7 +767,7 @@ typedef struct { tBLE_ADDR_TYPE peer_addr_type; BD_ADDR peer_addr; tBTM_BLE_AFP filter_policy; - UINT8 tx_power; + INT8 tx_power; tBTM_BLE_GAP_PHY primary_phy; UINT8 max_skip; tBTM_BLE_GAP_PHY secondary_phy; diff --git a/components/bt/host/bluedroid/stack/include/stack/hcimsgs.h b/components/bt/host/bluedroid/stack/include/stack/hcimsgs.h index 0286ae8a8c..ba5e66e7d9 100644 --- a/components/bt/host/bluedroid/stack/include/stack/hcimsgs.h +++ b/components/bt/host/bluedroid/stack/include/stack/hcimsgs.h @@ -962,7 +962,7 @@ UINT8 btsnd_hcic_ble_set_extend_rand_address(UINT8 adv_handle, BD_ADDR rand_addr UINT8 btsnd_hcic_ble_set_ext_adv_params(UINT8 adv_handle, UINT16 properties, UINT32 interval_min, UINT32 interval_max, UINT8 channel_map, UINT8 own_addr_type, UINT8 peer_addr_type, BD_ADDR peer_addr, - UINT8 adv_filter_policy, UINT8 adv_tx_power, + UINT8 adv_filter_policy, INT8 adv_tx_power, UINT8 primary_adv_phy, UINT8 secondary_adv_max_skip, UINT8 secondary_adv_phy, UINT8 adv_sid, UINT8 scan_req_ntf_enable); diff --git a/components/bt/host/bluedroid/stack/l2cap/l2c_api.c b/components/bt/host/bluedroid/stack/l2cap/l2c_api.c index 0c64eedc27..2db8fd539d 100644 --- a/components/bt/host/bluedroid/stack/l2cap/l2c_api.c +++ b/components/bt/host/bluedroid/stack/l2cap/l2c_api.c @@ -2342,7 +2342,15 @@ void l2ble_update_att_acl_pkt_num(UINT8 type, tl2c_buff_param_t *param) xSemaphoreGive(buff_semaphore); break; } - fixed_queue_t * queue = p_lcb->p_fixed_ccbs[L2CAP_ATT_CID - L2CAP_FIRST_FIXED_CHNL]->xmit_hold_q; + + tL2C_CCB *p_ccb = p_lcb->p_fixed_ccbs[L2CAP_ATT_CID - L2CAP_FIRST_FIXED_CHNL]; + if(p_ccb == NULL) { + L2CAP_TRACE_ERROR("%s not found p_ccb", __func__); + xSemaphoreGive(buff_semaphore); + break; + } + + fixed_queue_t * queue = p_ccb->xmit_hold_q; att_max_num = MIN(p_lcb->link_xmit_quota, L2CAP_CACHE_ATT_ACL_NUM); if (queue == NULL){ L2CAP_TRACE_ERROR("%s not found queue", __func__); diff --git a/components/bt/host/bluedroid/stack/l2cap/l2c_link.c b/components/bt/host/bluedroid/stack/l2cap/l2c_link.c index 4b81b4b3b2..5471e66bb8 100644 --- a/components/bt/host/bluedroid/stack/l2cap/l2c_link.c +++ b/components/bt/host/bluedroid/stack/l2cap/l2c_link.c @@ -87,7 +87,8 @@ BOOLEAN l2c_link_hci_conn_req (BD_ADDR bd_addr) if (p_lcb_cur->in_use) { no_links = FALSE; - p_lcb->link_role = HCI_ROLE_MASTER; + // p_lcb->link_role = HCI_ROLE_MASTER; + p_lcb->link_role = HCI_ROLE_SLAVE; break; } } diff --git a/components/bt/host/nimble/Kconfig.in b/components/bt/host/nimble/Kconfig.in index ffdedab576..8c174af5c3 100644 --- a/components/bt/host/nimble/Kconfig.in +++ b/components/bt/host/nimble/Kconfig.in @@ -240,7 +240,8 @@ config BT_NIMBLE_SVC_GAP_APPEARANCE menu "Memory Settings" config BT_NIMBLE_MSYS_1_BLOCK_COUNT int "MSYS_1 Block Count" - default 12 + default 24 if SOC_ESP_NIMBLE_CONTROLLER + default 12 if !SOC_ESP_NIMBLE_CONTROLLER help MSYS is a system level mbuf registry. For prepare write & prepare responses MBUFs are allocated out of msys_1 pool. For NIMBLE_MESH @@ -249,7 +250,8 @@ menu "Memory Settings" config BT_NIMBLE_MSYS_1_BLOCK_SIZE int "MSYS_1 Block Size" - default 256 + default 128 if SOC_ESP_NIMBLE_CONTROLLER + default 256 if !SOC_ESP_NIMBLE_CONTROLLER help Dynamic memory size of block 1 diff --git a/components/bt/host/nimble/nimble b/components/bt/host/nimble/nimble index c1cb851c85..f90ff3ae39 160000 --- a/components/bt/host/nimble/nimble +++ b/components/bt/host/nimble/nimble @@ -1 +1 @@ -Subproject commit c1cb851c8562d0f1a4d105614c336341e2a535b2 +Subproject commit f90ff3ae39a75ffef708c02cfe3b1e0b5068fc2c diff --git a/components/bt/include/esp32/include/esp_bt.h b/components/bt/include/esp32/include/esp_bt.h index fad01b97bf..f78a5a88d6 100644 --- a/components/bt/include/esp32/include/esp_bt.h +++ b/components/bt/include/esp32/include/esp_bt.h @@ -183,10 +183,10 @@ the adv packet will be discarded until the memory is restored. */ .pcm_polar = CONFIG_BTDM_CTRL_PCM_POLAR_EFF, \ .hli = BTDM_CTRL_HLI, \ .magic = ESP_BT_CONTROLLER_CONFIG_MAGIC_VAL, \ -}; +} #else -#define BT_CONTROLLER_INIT_CONFIG_DEFAULT() {0}; _Static_assert(0, "please enable bluetooth in menuconfig to use bt.h"); +#define BT_CONTROLLER_INIT_CONFIG_DEFAULT() {0}; _Static_assert(0, "please enable bluetooth in menuconfig to use esp_bt.h"); #endif /** diff --git a/components/bt/include/esp32c2/include/esp_bt.h b/components/bt/include/esp32c2/include/esp_bt.h index 3cac31b703..6489741282 100644 --- a/components/bt/include/esp32c2/include/esp_bt.h +++ b/components/bt/include/esp32c2/include/esp_bt.h @@ -76,25 +76,34 @@ typedef enum { * @brief Bluetooth TX power level(index), it's just a index corresponding to power(dbm). */ typedef enum { - ESP_PWR_LVL_N27 = 0, /*!< Corresponding to -27dbm */ - ESP_PWR_LVL_N24 = 1, /*!< Corresponding to -24dbm */ - ESP_PWR_LVL_N21 = 2, /*!< Corresponding to -21dbm */ - ESP_PWR_LVL_N18 = 3, /*!< Corresponding to -18dbm */ - ESP_PWR_LVL_N15 = 4, /*!< Corresponding to -15dbm */ - ESP_PWR_LVL_N12 = 5, /*!< Corresponding to -12dbm */ - ESP_PWR_LVL_N9 = 6, /*!< Corresponding to -9dbm */ - ESP_PWR_LVL_N6 = 7, /*!< Corresponding to -6dbm */ - ESP_PWR_LVL_N3 = 8, /*!< Corresponding to -3dbm */ - ESP_PWR_LVL_N0 = 9, /*!< Corresponding to 0dbm */ - ESP_PWR_LVL_P3 = 10, /*!< Corresponding to +3dbm */ - ESP_PWR_LVL_P6 = 11, /*!< Corresponding to +6dbm */ - ESP_PWR_LVL_P9 = 12, /*!< Corresponding to +9dbm */ - ESP_PWR_LVL_P12 = 13, /*!< Corresponding to +12dbm */ - ESP_PWR_LVL_P15 = 14, /*!< Corresponding to +15dbm */ - ESP_PWR_LVL_P18 = 15, /*!< Corresponding to +18dbm */ + ESP_PWR_LVL_N24 = 0, /*!< Corresponding to -24dbm */ + ESP_PWR_LVL_N21 = 1, /*!< Corresponding to -21dbm */ + ESP_PWR_LVL_N18 = 2, /*!< Corresponding to -18dbm */ + ESP_PWR_LVL_N15 = 3, /*!< Corresponding to -15dbm */ + ESP_PWR_LVL_N12 = 4, /*!< Corresponding to -12dbm */ + ESP_PWR_LVL_N9 = 5, /*!< Corresponding to -9dbm */ + ESP_PWR_LVL_N6 = 6, /*!< Corresponding to -6dbm */ + ESP_PWR_LVL_N3 = 7, /*!< Corresponding to -3dbm */ + ESP_PWR_LVL_N0 = 8, /*!< Corresponding to 0dbm */ + ESP_PWR_LVL_P3 = 9, /*!< Corresponding to +3dbm */ + ESP_PWR_LVL_P6 = 10, /*!< Corresponding to +6dbm */ + ESP_PWR_LVL_P9 = 11, /*!< Corresponding to +9dbm */ + ESP_PWR_LVL_P12 = 12, /*!< Corresponding to +12dbm */ + ESP_PWR_LVL_P15 = 13, /*!< Corresponding to +15dbm */ + ESP_PWR_LVL_P18 = 14, /*!< Corresponding to +18dbm */ + ESP_PWR_LVL_P21 = 15, /*!< Corresponding to +21dbm */ ESP_PWR_LVL_INVALID = 0xFF, /*!< Indicates an invalid value */ } esp_power_level_t; +typedef enum { + ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT = 0, + ESP_BLE_ENHANCED_PWR_TYPE_ADV, + ESP_BLE_ENHANCED_PWR_TYPE_SCAN, + ESP_BLE_ENHANCED_PWR_TYPE_INIT, + ESP_BLE_ENHANCED_PWR_TYPE_CONN, + ESP_BLE_ENHANCED_PWR_TYPE_MAX, +} esp_ble_enhanced_power_type_t; + typedef struct { uint8_t type; uint8_t val[6]; @@ -117,8 +126,26 @@ esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_ */ esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type); +/** + * @brief ENHANCED API for Setting BLE TX power + * Connection Tx power should only be set after connection created. + * @param power_type : The enhanced type of which tx power, could set Advertising/Connection/Default and etc + * @param handle : The handle of Advertising or Connection and the value 0 for other enhanced power types. + * @param power_level: Power level(index) corresponding to absolute value(dbm) + * @return ESP_OK - success, other - failed + */ +esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle, esp_power_level_t power_level); -#define CONFIG_VERSION 0x20220729 +/** + * @brief ENHANCED API of Getting BLE TX power + * Connection Tx power should only be get after connection created. + * @param power_type : The enhanced type of which tx power, could set Advertising/Connection/Default and etc + * @param handle : The handle of Advertising or Connection and the value 0 for other enhanced power types. + * @return >= 0 - Power level, < 0 - Invalid + */ +esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle); + +#define CONFIG_VERSION 0x20220824 #define CONFIG_MAGIC 0x5A5AA5A5 /** @@ -228,7 +255,7 @@ typedef struct { .ble_scan_classify_filter_enable = 0, \ .main_xtal_freq = CONFIG_XTAL_FREQ, \ .config_magic = CONFIG_MAGIC, \ -}; +} esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg); diff --git a/components/bt/include/esp32c3/include/esp_bt.h b/components/bt/include/esp32c3/include/esp_bt.h index 2ec3064d6e..be9de3d88b 100644 --- a/components/bt/include/esp32c3/include/esp_bt.h +++ b/components/bt/include/esp32c3/include/esp_bt.h @@ -181,10 +181,10 @@ typedef void (* esp_bt_hci_tl_callback_t) (void *arg, uint8_t status); .slave_ce_len_min = SLAVE_CE_LEN_MIN_DEFAULT, \ .hw_recorrect_en = AGC_RECORRECT_EN, \ .cca_thresh = CONFIG_BT_CTRL_HW_CCA_VAL, \ -}; +} #else -#define BT_CONTROLLER_INIT_CONFIG_DEFAULT() {0}; _Static_assert(0, "please enable bluetooth in menuconfig to use bt.h"); +#define BT_CONTROLLER_INIT_CONFIG_DEFAULT() {0}; _Static_assert(0, "please enable bluetooth in menuconfig to use esp_bt.h"); #endif /** @@ -290,22 +290,22 @@ typedef enum { * @brief Bluetooth TX power level(index), it's just a index corresponding to power(dbm). */ typedef enum { - ESP_PWR_LVL_N27 = 0, /*!< Corresponding to -27dbm */ - ESP_PWR_LVL_N24 = 1, /*!< Corresponding to -24dbm */ - ESP_PWR_LVL_N21 = 2, /*!< Corresponding to -21dbm */ - ESP_PWR_LVL_N18 = 3, /*!< Corresponding to -18dbm */ - ESP_PWR_LVL_N15 = 4, /*!< Corresponding to -15dbm */ - ESP_PWR_LVL_N12 = 5, /*!< Corresponding to -12dbm */ - ESP_PWR_LVL_N9 = 6, /*!< Corresponding to -9dbm */ - ESP_PWR_LVL_N6 = 7, /*!< Corresponding to -6dbm */ - ESP_PWR_LVL_N3 = 8, /*!< Corresponding to -3dbm */ - ESP_PWR_LVL_N0 = 9, /*!< Corresponding to 0dbm */ - ESP_PWR_LVL_P3 = 10, /*!< Corresponding to +3dbm */ - ESP_PWR_LVL_P6 = 11, /*!< Corresponding to +6dbm */ - ESP_PWR_LVL_P9 = 12, /*!< Corresponding to +9dbm */ - ESP_PWR_LVL_P12 = 13, /*!< Corresponding to +12dbm */ - ESP_PWR_LVL_P15 = 14, /*!< Corresponding to +15dbm */ - ESP_PWR_LVL_P18 = 15, /*!< Corresponding to +18dbm */ + ESP_PWR_LVL_N24 = 0, /*!< Corresponding to -24dbm */ + ESP_PWR_LVL_N21 = 1, /*!< Corresponding to -21dbm */ + ESP_PWR_LVL_N18 = 2, /*!< Corresponding to -18dbm */ + ESP_PWR_LVL_N15 = 3, /*!< Corresponding to -15dbm */ + ESP_PWR_LVL_N12 = 4, /*!< Corresponding to -12dbm */ + ESP_PWR_LVL_N9 = 5, /*!< Corresponding to -9dbm */ + ESP_PWR_LVL_N6 = 6, /*!< Corresponding to -6dbm */ + ESP_PWR_LVL_N3 = 7, /*!< Corresponding to -3dbm */ + ESP_PWR_LVL_N0 = 8, /*!< Corresponding to 0dbm */ + ESP_PWR_LVL_P3 = 9, /*!< Corresponding to +3dbm */ + ESP_PWR_LVL_P6 = 10, /*!< Corresponding to +6dbm */ + ESP_PWR_LVL_P9 = 11, /*!< Corresponding to +9dbm */ + ESP_PWR_LVL_P12 = 12, /*!< Corresponding to +12dbm */ + ESP_PWR_LVL_P15 = 13, /*!< Corresponding to +15dbm */ + ESP_PWR_LVL_P18 = 14, /*!< Corresponding to +18dbm */ + ESP_PWR_LVL_P21 = 15, /*!< Corresponding to +21dbm */ ESP_PWR_LVL_INVALID = 0xFF, /*!< Indicates an invalid value */ } esp_power_level_t; diff --git a/components/bt/include/esp32h2/include/esp_bt.h b/components/bt/include/esp32h2/include/esp_bt.h index d3efdba30c..7f9b164927 100644 --- a/components/bt/include/esp32h2/include/esp_bt.h +++ b/components/bt/include/esp32h2/include/esp_bt.h @@ -227,7 +227,7 @@ typedef struct { .coex_phy_coded_tx_rx_time_limit = DEFAULT_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF, \ .scan_classify_filter_enable = false, \ .config_magic = CONFIG_MAGIC, \ -}; +} esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg); diff --git a/components/bt/include/esp32s3/include/esp_bt.h b/components/bt/include/esp32s3/include/esp_bt.h index 7bc1f0b6e2..e72e5111b7 100644 --- a/components/bt/include/esp32s3/include/esp_bt.h +++ b/components/bt/include/esp32s3/include/esp_bt.h @@ -180,10 +180,10 @@ typedef void (* esp_bt_hci_tl_callback_t) (void *arg, uint8_t status); .slave_ce_len_min = SLAVE_CE_LEN_MIN_DEFAULT, \ .hw_recorrect_en = AGC_RECORRECT_EN, \ .cca_thresh = CONFIG_BT_CTRL_HW_CCA_VAL, \ -}; +} #else -#define BT_CONTROLLER_INIT_CONFIG_DEFAULT() {0}; _Static_assert(0, "please enable bluetooth in menuconfig to use bt.h"); +#define BT_CONTROLLER_INIT_CONFIG_DEFAULT() {0}; _Static_assert(0, "please enable bluetooth in menuconfig to use esp_bt.h"); #endif /** @@ -289,23 +289,23 @@ typedef enum { * @brief Bluetooth TX power level(index), it's just a index corresponding to power(dbm). */ typedef enum { - ESP_PWR_LVL_N27 = 0, /*!< Corresponding to -27dbm */ - ESP_PWR_LVL_N24 = 1, /*!< Corresponding to -24dbm */ - ESP_PWR_LVL_N21 = 2, /*!< Corresponding to -21dbm */ - ESP_PWR_LVL_N18 = 3, /*!< Corresponding to -18dbm */ - ESP_PWR_LVL_N15 = 4, /*!< Corresponding to -15dbm */ - ESP_PWR_LVL_N12 = 5, /*!< Corresponding to -12dbm */ - ESP_PWR_LVL_N9 = 6, /*!< Corresponding to -9dbm */ - ESP_PWR_LVL_N6 = 7, /*!< Corresponding to -6dbm */ - ESP_PWR_LVL_N3 = 8, /*!< Corresponding to -3dbm */ - ESP_PWR_LVL_N0 = 9, /*!< Corresponding to 0dbm */ - ESP_PWR_LVL_P3 = 10, /*!< Corresponding to +3dbm */ - ESP_PWR_LVL_P6 = 11, /*!< Corresponding to +6dbm */ - ESP_PWR_LVL_P9 = 12, /*!< Corresponding to +9dbm */ - ESP_PWR_LVL_P12 = 13, /*!< Corresponding to +12dbm */ - ESP_PWR_LVL_P15 = 14, /*!< Corresponding to +15dbm */ - ESP_PWR_LVL_P18 = 15, /*!< Corresponding to +18dbm */ - ESP_PWR_LVL_INVALID = 0xFF, /*!< Indicates an invalid value */ + ESP_PWR_LVL_N24 = 0, /*!< Corresponding to -24dbm */ + ESP_PWR_LVL_N21 = 1, /*!< Corresponding to -21dbm */ + ESP_PWR_LVL_N18 = 2, /*!< Corresponding to -18dbm */ + ESP_PWR_LVL_N15 = 3, /*!< Corresponding to -15dbm */ + ESP_PWR_LVL_N12 = 4, /*!< Corresponding to -12dbm */ + ESP_PWR_LVL_N9 = 5, /*!< Corresponding to -9dbm */ + ESP_PWR_LVL_N6 = 6, /*!< Corresponding to -6dbm */ + ESP_PWR_LVL_N3 = 7, /*!< Corresponding to -3dbm */ + ESP_PWR_LVL_N0 = 8, /*!< Corresponding to 0dbm */ + ESP_PWR_LVL_P3 = 9, /*!< Corresponding to +3dbm */ + ESP_PWR_LVL_P6 = 10, /*!< Corresponding to +6dbm */ + ESP_PWR_LVL_P9 = 11, /*!< Corresponding to +9dbm */ + ESP_PWR_LVL_P12 = 12, /*!< Corresponding to +12dbm */ + ESP_PWR_LVL_P15 = 13, /*!< Corresponding to +15dbm */ + ESP_PWR_LVL_P18 = 14, /*!< Corresponding to +18dbm */ + ESP_PWR_LVL_P21 = 15, /*!< Corresponding to +21dbm */ + ESP_PWR_LVL_INVALID = 0xFF, /*!< Indicates an invalid value */ } esp_power_level_t; /** diff --git a/components/bt/porting/nimble/include/nimble/ble.h b/components/bt/porting/nimble/include/nimble/ble.h index 5f47299e3e..f037d3565b 100644 --- a/components/bt/porting/nimble/include/nimble/ble.h +++ b/components/bt/porting/nimble/include/nimble/ble.h @@ -116,9 +116,10 @@ struct ble_mbuf_hdr_rxinfo struct ble_mbuf_hdr_txinfo { uint8_t flags; - uint8_t offset; + uint8_t reserve0; uint8_t pyld_len; uint8_t hdr_byte; + uint16_t offset; }; struct ble_mbuf_hdr diff --git a/components/bt/porting/npl/freertos/src/npl_os_freertos.c b/components/bt/porting/npl/freertos/src/npl_os_freertos.c index eef5153beb..7738e6e2d3 100644 --- a/components/bt/porting/npl/freertos/src/npl_os_freertos.c +++ b/components/bt/porting/npl/freertos/src/npl_os_freertos.c @@ -765,7 +765,7 @@ IRAM_ATTR npl_freertos_callout_deinit(struct ble_npl_callout *co) esp_err_t err = esp_timer_stop(callout->handle); if(err != ESP_OK) { if (err != ESP_ERR_INVALID_STATE) { // ESP_ERR_INVALID_STATE is expected when timer is already stopped - ESP_LOGW(TAG, "Timer not stopped"); + ESP_LOGD(TAG, "Timer not stopped"); } } err = esp_timer_delete(callout->handle); diff --git a/components/console/esp_console_repl.c b/components/console/esp_console_repl.c index c99e1c4b69..cb60df5452 100644 --- a/components/console/esp_console_repl.c +++ b/components/console/esp_console_repl.c @@ -174,16 +174,18 @@ esp_err_t esp_console_new_repl_usb_serial_jtag(const esp_console_dev_usb_serial_ // setup prompt esp_console_setup_prompt(repl_config->prompt, &usb_serial_jtag_repl->repl_com); + /* Fill the structure here as it will be used directly by the created task. */ + usb_serial_jtag_repl->uart_channel = CONFIG_ESP_CONSOLE_UART_NUM; + usb_serial_jtag_repl->repl_com.state = CONSOLE_REPL_STATE_INIT; + usb_serial_jtag_repl->repl_com.repl_core.del = esp_console_repl_usb_serial_jtag_delete; + /* spawn a single thread to run REPL */ if (xTaskCreate(esp_console_repl_task, "console_repl", repl_config->task_stack_size, - &usb_serial_jtag_repl->repl_com, repl_config->task_priority, &usb_serial_jtag_repl->repl_com.task_hdl) != pdTRUE) { + usb_serial_jtag_repl, repl_config->task_priority, &usb_serial_jtag_repl->repl_com.task_hdl) != pdTRUE) { ret = ESP_FAIL; goto _exit; } - usb_serial_jtag_repl->uart_channel = CONFIG_ESP_CONSOLE_UART_NUM; - usb_serial_jtag_repl->repl_com.state = CONSOLE_REPL_STATE_INIT; - usb_serial_jtag_repl->repl_com.repl_core.del = esp_console_repl_usb_serial_jtag_delete; *ret_repl = &usb_serial_jtag_repl->repl_com.repl_core; return ESP_OK; _exit: diff --git a/components/console/linenoise/linenoise.h b/components/console/linenoise/linenoise.h index 730ba9b5b1..98876104aa 100644 --- a/components/console/linenoise/linenoise.h +++ b/components/console/linenoise/linenoise.h @@ -44,6 +44,7 @@ extern "C" { #endif #include +#include typedef struct linenoiseCompletions { size_t len; diff --git a/components/console/test/CMakeLists.txt b/components/console/test/CMakeLists.txt deleted file mode 100644 index 4378949ec0..0000000000 --- a/components/console/test/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -idf_component_register(SRC_DIRS . - PRIV_INCLUDE_DIRS . - PRIV_REQUIRES cmock test_utils console) - target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/components/console/test_apps/console/CMakeLists.txt b/components/console/test_apps/console/CMakeLists.txt new file mode 100644 index 0000000000..a2cde6ec34 --- /dev/null +++ b/components/console/test_apps/console/CMakeLists.txt @@ -0,0 +1,8 @@ +# The following lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components") + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(test_console) diff --git a/components/console/test_apps/console/README.md b/components/console/test_apps/console/README.md new file mode 100644 index 0000000000..b5be4985c5 --- /dev/null +++ b/components/console/test_apps/console/README.md @@ -0,0 +1,2 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | diff --git a/components/console/test_apps/console/main/CMakeLists.txt b/components/console/test_apps/console/main/CMakeLists.txt new file mode 100644 index 0000000000..b253135b6c --- /dev/null +++ b/components/console/test_apps/console/main/CMakeLists.txt @@ -0,0 +1,4 @@ +idf_component_register(SRCS "test_app_main.c" "test_console.c" + INCLUDE_DIRS "." + PRIV_REQUIRES unity console + WHOLE_ARCHIVE) diff --git a/components/console/test_apps/console/main/test_app_main.c b/components/console/test_apps/console/main/test_app_main.c new file mode 100644 index 0000000000..cc9ee8d9cc --- /dev/null +++ b/components/console/test_apps/console/main/test_app_main.c @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "unity.h" +#include "unity_test_runner.h" +#include "esp_heap_caps.h" + + +// Some resources are lazy allocated (newlib locks) in the console code, the threshold is left for that case +#define TEST_MEMORY_LEAK_THRESHOLD (-100) + +static size_t before_free_8bit; +static size_t before_free_32bit; + +static void check_leak(size_t before_free, size_t after_free, const char *type) +{ + ssize_t delta = after_free - before_free; + printf("MALLOC_CAP_%s: Before %u bytes free, After %u bytes free (delta %d)\n", type, before_free, after_free, delta); + TEST_ASSERT_MESSAGE(delta >= TEST_MEMORY_LEAK_THRESHOLD, "memory leak"); +} + +void setUp(void) +{ + before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); +} + + + +void tearDown(void) +{ + size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); + check_leak(before_free_8bit, after_free_8bit, "8BIT"); + check_leak(before_free_32bit, after_free_32bit, "32BIT"); +} + +void app_main(void) +{ + printf("Running console component tests\n"); + unity_run_menu(); +} diff --git a/components/console/test/test_console.c b/components/console/test_apps/console/main/test_console.c similarity index 95% rename from components/console/test/test_console.c rename to components/console/test_apps/console/main/test_console.c index eab793dce7..08861a72e9 100644 --- a/components/console/test/test_console.c +++ b/components/console/test_apps/console/main/test_console.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,7 +7,6 @@ #include #include "sdkconfig.h" #include "unity.h" -#include "test_utils.h" #include "esp_console.h" #include "argtable3/argtable3.h" #include "freertos/FreeRTOS.h" diff --git a/components/console/test_apps/console/pytest_console.py b/components/console/test_apps/console/pytest_console.py new file mode 100644 index 0000000000..937a80cd67 --- /dev/null +++ b/components/console/test_apps/console/pytest_console.py @@ -0,0 +1,13 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +import pytest +from pytest_embedded import Dut + + +@pytest.mark.generic +@pytest.mark.supported_targets +def test_console(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('![ignore]') + dut.expect_unity_test_output() diff --git a/components/driver/.build-test-rules.yml b/components/driver/.build-test-rules.yml index a2f4dbc567..0521ccfeda 100644 --- a/components/driver/.build-test-rules.yml +++ b/components/driver/.build-test-rules.yml @@ -4,6 +4,10 @@ components/driver/test_apps/i2s_test_apps: disable: - if: SOC_I2S_SUPPORTED != 1 +components/driver/test_apps/i2s_test_apps/i2s_tdm: + disable: + - if: SOC_I2S_SUPPORTS_TDM != 1 + components/driver/test_apps/i2s_test_apps/legacy_i2s_adc_dac: disable: - if: SOC_I2S_SUPPORTS_ADC_DAC != 1 diff --git a/components/driver/CMakeLists.txt b/components/driver/CMakeLists.txt index 729db55b13..6315559855 100644 --- a/components/driver/CMakeLists.txt +++ b/components/driver/CMakeLists.txt @@ -4,8 +4,6 @@ set(srcs "gpio/gpio.c" "gpio/rtc_io.c" "gptimer.c" - "i2c.c" - "ledc.c" "sdspi_crc.c" "sdspi_host.c" "sdspi_transaction.c" @@ -23,6 +21,14 @@ if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target}/include") list(APPEND includes "${target}/include") endif() +if(CONFIG_SOC_LEDC_SUPPORTED) + list(APPEND srcs "ledc.c") +endif() + +if(CONFIG_SOC_I2C_SUPPORTED) + list(APPEND srcs "i2c.c") +endif() + if(CONFIG_SOC_ADC_SUPPORTED) list(APPEND srcs "deprecated/adc_legacy.c") endif() @@ -125,5 +131,3 @@ else() REQUIRES esp_pm esp_ringbuf freertos soc hal esp_hw_support LDFRAGMENTS linker.lf) endif() - -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/components/driver/Kconfig b/components/driver/Kconfig index 8def437f13..7888cd5380 100644 --- a/components/driver/Kconfig +++ b/components/driver/Kconfig @@ -352,6 +352,14 @@ menu "Driver Configurations" cache misses, and also be able to run whilst the cache is disabled. (e.g. SPI Flash write) + config MCPWM_CTRL_FUNC_IN_IRAM + bool "Place MCPWM control functions into IRAM" + default n + help + Place MCPWM control functions (like set_compare_value) into IRAM, + so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context. + Enabling this option can improve driver performance as well. + config MCPWM_SUPPRESS_DEPRECATE_WARN bool "Suppress leagcy driver deprecated warning" default n diff --git a/components/driver/deprecated/adc_legacy.c b/components/driver/deprecated/adc_legacy.c index 67d586efc5..238a9a1926 100644 --- a/components/driver/deprecated/adc_legacy.c +++ b/components/driver/deprecated/adc_legacy.c @@ -13,6 +13,7 @@ #include "freertos/semphr.h" #include "freertos/timers.h" #include "esp_log.h" +#include "esp_check.h" #include "esp_pm.h" #include "soc/rtc.h" #include "driver/rtc_io.h" @@ -36,26 +37,11 @@ #include "esp_efuse_rtc_calib.h" #endif -#define ADC_CHECK_RET(fun_ret) ({ \ - if (fun_ret != ESP_OK) { \ - ESP_LOGE(ADC_TAG,"%s:%d\n",__FUNCTION__,__LINE__); \ - return ESP_FAIL; \ - } \ -}) static const char *ADC_TAG = "ADC"; -#define ADC_CHECK(a, str, ret_val) ({ \ - if (!(a)) { \ - ESP_LOGE(ADC_TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \ - return (ret_val); \ - } \ -}) - #define ADC_GET_IO_NUM(periph, channel) (adc_channel_io_map[periph][channel]) -#define ADC_CHANNEL_CHECK(periph, channel) ADC_CHECK(channel < SOC_ADC_CHANNEL_NUM(periph), "ADC"#periph" channel error", ESP_ERR_INVALID_ARG) - //////////////////////// Locks /////////////////////////////////////////// extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate position after the rtc module is finished. @@ -121,7 +107,7 @@ static esp_err_t adc_hal_convert(adc_unit_t adc_n, int channel, int *out_raw); ---------------------------------------------------------------*/ esp_err_t adc1_pad_get_io_num(adc1_channel_t channel, gpio_num_t *gpio_num) { - ADC_CHANNEL_CHECK(ADC_UNIT_1, channel); + ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_UNIT_1), ESP_ERR_INVALID_ARG, ADC_TAG, "invalid channel"); int io = ADC_GET_IO_NUM(ADC_UNIT_1, channel); if (io < 0) { @@ -136,7 +122,7 @@ esp_err_t adc1_pad_get_io_num(adc1_channel_t channel, gpio_num_t *gpio_num) #if (SOC_ADC_PERIPH_NUM >= 2) esp_err_t adc2_pad_get_io_num(adc2_channel_t channel, gpio_num_t *gpio_num) { - ADC_CHANNEL_CHECK(ADC_UNIT_2, channel); + ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_UNIT_2), ESP_ERR_INVALID_ARG, ADC_TAG, "invalid channel"); int io = ADC_GET_IO_NUM(ADC_UNIT_2, channel); if (io < 0) { @@ -183,25 +169,24 @@ static void adc_rtc_chan_init(adc_unit_t adc_unit) esp_err_t adc_common_gpio_init(adc_unit_t adc_unit, adc_channel_t channel) { + ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(adc_unit), ESP_ERR_INVALID_ARG, ADC_TAG, "invalid channel"); + gpio_num_t gpio_num = 0; //If called with `ADC_UNIT_BOTH (ADC_UNIT_1 | ADC_UNIT_2)`, both if blocks will be run if (adc_unit == ADC_UNIT_1) { - ADC_CHANNEL_CHECK(ADC_UNIT_1, channel); gpio_num = ADC_GET_IO_NUM(ADC_UNIT_1, channel); - ADC_CHECK_RET(rtc_gpio_init(gpio_num)); - ADC_CHECK_RET(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED)); - ADC_CHECK_RET(rtc_gpio_pulldown_dis(gpio_num)); - ADC_CHECK_RET(rtc_gpio_pullup_dis(gpio_num)); - } - if (adc_unit == ADC_UNIT_2) { - ADC_CHANNEL_CHECK(ADC_UNIT_2, channel); + + } else if (adc_unit == ADC_UNIT_2) { gpio_num = ADC_GET_IO_NUM(ADC_UNIT_2, channel); - ADC_CHECK_RET(rtc_gpio_init(gpio_num)); - ADC_CHECK_RET(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED)); - ADC_CHECK_RET(rtc_gpio_pulldown_dis(gpio_num)); - ADC_CHECK_RET(rtc_gpio_pullup_dis(gpio_num)); + } else { + return ESP_ERR_INVALID_ARG; } + ESP_RETURN_ON_ERROR(rtc_gpio_init(gpio_num), ADC_TAG, "rtc_gpio_init fail"); + ESP_RETURN_ON_ERROR(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED), ADC_TAG, "rtc_gpio_set_direction fail"); + ESP_RETURN_ON_ERROR(rtc_gpio_pulldown_dis(gpio_num), ADC_TAG, "rtc_gpio_pulldown_dis fail"); + ESP_RETURN_ON_ERROR(rtc_gpio_pullup_dis(gpio_num), ADC_TAG, "rtc_gpio_pullup_dis fail"); + return ESP_OK; } @@ -223,7 +208,7 @@ esp_err_t adc_set_data_inv(adc_unit_t adc_unit, bool inv_en) esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t width_bit) { - ADC_CHECK(width_bit < ADC_WIDTH_MAX, "unsupported bit width", ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(width_bit < ADC_WIDTH_MAX, ESP_ERR_INVALID_ARG, ADC_TAG, "unsupported bit width"); adc_bitwidth_t bitwidth = 0; #if CONFIG_IDF_TARGET_ESP32 if ((uint32_t)width_bit == (uint32_t)ADC_BITWIDTH_DEFAULT) { @@ -287,8 +272,8 @@ esp_err_t adc_rtc_reset(void) *------------------------------------------------------------------------------------*/ esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten) { - ADC_CHANNEL_CHECK(ADC_UNIT_1, channel); - ADC_CHECK(atten < SOC_ADC_ATTEN_NUM, "ADC Atten Err", ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_UNIT_1), ESP_ERR_INVALID_ARG, ADC_TAG, "invalid channel"); + ESP_RETURN_ON_FALSE(atten < SOC_ADC_ATTEN_NUM, ESP_ERR_INVALID_ARG, ADC_TAG, "ADC Atten Err"); adc_common_gpio_init(ADC_UNIT_1, channel); SARADC1_ENTER(); @@ -305,7 +290,7 @@ esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten) esp_err_t adc1_config_width(adc_bits_width_t width_bit) { - ADC_CHECK(width_bit < ADC_WIDTH_MAX, "unsupported bit width", ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(width_bit < ADC_WIDTH_MAX, ESP_ERR_INVALID_ARG, ADC_TAG, "unsupported bit width"); adc_bitwidth_t bitwidth = 0; #if CONFIG_IDF_TARGET_ESP32 if ((uint32_t)width_bit == (uint32_t)ADC_BITWIDTH_DEFAULT) { @@ -375,7 +360,7 @@ esp_err_t adc1_rtc_mode_acquire(void) esp_err_t adc1_lock_release(void) { - ADC_CHECK((uint32_t *)adc1_dma_lock != NULL, "adc1 lock release called before acquire", ESP_ERR_INVALID_STATE ); + ESP_RETURN_ON_FALSE((uint32_t *)adc1_dma_lock != NULL, ESP_ERR_INVALID_STATE, ADC_TAG, "adc1 lock release called before acquire"); /* Use locks to avoid digtal and RTC controller conflicts. for adc1, block until acquire the lock. */ adc_power_release(); @@ -386,7 +371,7 @@ esp_err_t adc1_lock_release(void) int adc1_get_raw(adc1_channel_t channel) { int adc_value; - ADC_CHANNEL_CHECK(ADC_UNIT_1, channel); + ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_UNIT_1), ESP_ERR_INVALID_ARG, ADC_TAG, "invalid channel"); adc1_rtc_mode_acquire(); #if SOC_ADC_CALIBRATION_V1_SUPPORTED @@ -440,8 +425,8 @@ void adc1_ulp_enable(void) ---------------------------------------------------------------*/ esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten) { - ADC_CHANNEL_CHECK(ADC_UNIT_2, channel); - ADC_CHECK(atten <= SOC_ADC_ATTEN_NUM, "ADC2 Atten Err", ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_UNIT_2), ESP_ERR_INVALID_ARG, ADC_TAG, "invalid channel"); + ESP_RETURN_ON_FALSE(atten <= SOC_ADC_ATTEN_NUM, ESP_ERR_INVALID_ARG, ADC_TAG, "ADC2 Atten Err"); adc_common_gpio_init(ADC_UNIT_2, channel); @@ -513,9 +498,9 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int * int adc_value = 0; adc_bitwidth_t bitwidth = 0; - ADC_CHECK(raw_out != NULL, "ADC out value err", ESP_ERR_INVALID_ARG); - ADC_CHECK(channel < ADC2_CHANNEL_MAX, "ADC Channel Err", ESP_ERR_INVALID_ARG); - ADC_CHECK(width_bit < ADC_WIDTH_MAX, "unsupported bit width", ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(raw_out != NULL, ESP_ERR_INVALID_ARG, ADC_TAG, "ADC out value err"); + ESP_RETURN_ON_FALSE(channel < ADC2_CHANNEL_MAX, ESP_ERR_INVALID_ARG, ADC_TAG, "ADC Channel Err"); + ESP_RETURN_ON_FALSE(width_bit < ADC_WIDTH_MAX, ESP_ERR_INVALID_ARG, ADC_TAG, "unsupported bit width"); #if CONFIG_IDF_TARGET_ESP32 if ((uint32_t)width_bit == (uint32_t)ADC_BITWIDTH_DEFAULT) { bitwidth = SOC_ADC_RTC_MAX_BITWIDTH; diff --git a/components/driver/deprecated/driver/adc_types_legacy.h b/components/driver/deprecated/driver/adc_types_legacy.h index ec2a9fa1e3..8336bff9ba 100644 --- a/components/driver/deprecated/driver/adc_types_legacy.h +++ b/components/driver/deprecated/driver/adc_types_legacy.h @@ -61,7 +61,7 @@ typedef enum { ADC1_CHANNEL_9, /*!< ADC1 channel 9 is GPIO10 */ ADC1_CHANNEL_MAX, } adc1_channel_t; -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5310 typedef enum { ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO0 */ ADC1_CHANNEL_1, /*!< ADC1 channel 1 is GPIO1 */ @@ -86,7 +86,7 @@ typedef enum { ADC2_CHANNEL_9, /*!< ADC2 channel 9 is GPIO26 (ESP32), GPIO20 (ESP32-S2) */ ADC2_CHANNEL_MAX, } adc2_channel_t; -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5310 typedef enum { ADC2_CHANNEL_0 = 0, /*!< ADC2 channel 0 is GPIO5 */ ADC2_CHANNEL_MAX, diff --git a/components/driver/deprecated/driver/mcpwm.h b/components/driver/deprecated/driver/mcpwm.h index e8ff38778f..a85c1951bb 100644 --- a/components/driver/deprecated/driver/mcpwm.h +++ b/components/driver/deprecated/driver/mcpwm.h @@ -344,8 +344,8 @@ esp_err_t mcpwm_carrier_output_invert(mcpwm_unit_t mcpwm_num, mcpwm_timer_t time * @param mcpwm_num set MCPWM unit(0-1) * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers * @param dt_mode set deadtime mode - * @param red set rising edge delay = red*100ns - * @param fed set rising edge delay = fed*100ns + * @param red set rising edge delay = (red + 1) * MCPWM Group Resolution (default to 100ns, can be changed by `mcpwm_group_set_resolution`) + * @param fed set rising edge delay = (fed + 1) * MCPWM Group Resolution (default to 100ns, can be changed by `mcpwm_group_set_resolution`) * * @return * - ESP_OK Success diff --git a/components/driver/deprecated/driver/mcpwm_types_legacy.h b/components/driver/deprecated/driver/mcpwm_types_legacy.h index 38f94dddfe..44fd55bd09 100644 --- a/components/driver/deprecated/driver/mcpwm_types_legacy.h +++ b/components/driver/deprecated/driver/mcpwm_types_legacy.h @@ -68,7 +68,9 @@ typedef struct { */ typedef enum { MCPWM_UNIT_0, /*! 1 MCPWM_UNIT_1, /*!dir & I2S_DIR_RX) { i2s_ll_rx_set_eof_num(p_i2s[i2s_num]->hal.dev, dma_obj->buf_size); } - ESP_LOGD(TAG, "DMA Malloc info, datalen=blocksize=%d, dma_desc_num=%d", dma_obj->buf_size, buf_cnt); + ESP_LOGD(TAG, "DMA Malloc info, datalen=blocksize=%d, dma_desc_num=%"PRIu32, dma_obj->buf_size, buf_cnt); return ESP_OK; err: /* Delete DMA buffer if failed to allocate memory */ @@ -624,6 +625,7 @@ err: /*------------------------------------------------------------- I2S clock operation -------------------------------------------------------------*/ + // [clk_tree] TODO: replace the following switch table by clk_tree API static uint32_t i2s_config_source_clock(i2s_port_t i2s_num, bool use_apll, uint32_t mclk) { #if SOC_I2S_SUPPORTS_APLL @@ -644,18 +646,18 @@ static uint32_t i2s_config_source_clock(i2s_port_t i2s_num, bool use_apll, uint3 return 0; } if (ret == ESP_ERR_INVALID_STATE) { - ESP_LOGW(TAG, "APLL is occupied already, it is working at %d Hz", real_freq); + ESP_LOGW(TAG, "APLL is occupied already, it is working at %"PRIu32" Hz", real_freq); } - ESP_LOGD(TAG, "APLL expected frequency is %d Hz, real frequency is %d Hz", expt_freq, real_freq); + ESP_LOGD(TAG, "APLL expected frequency is %"PRIu32" Hz, real frequency is %"PRIu32" Hz", expt_freq, real_freq); /* In APLL mode, there is no sclk but only mclk, so return 0 here to indicate APLL mode */ return real_freq; } - return I2S_LL_BASE_CLK; + return esp_clk_apb_freq() * 2; #else if (use_apll) { ESP_LOGW(TAG, "APLL not supported on current chip, use I2S_CLK_SRC_DEFAULT as default clock source"); } - return I2S_LL_BASE_CLK; + return esp_clk_apb_freq() * 2; #endif } @@ -804,7 +806,7 @@ static esp_err_t i2s_calculate_clock(i2s_port_t i2s_num, i2s_hal_clock_info_t *c /* Calculate clock for common mode */ ESP_RETURN_ON_ERROR(i2s_calculate_common_clock(i2s_num, clk_info), TAG, "Common clock calculate failed"); - ESP_LOGD(TAG, "[sclk] %d [mclk] %d [mclk_div] %d [bclk] %d [bclk_div] %d", + ESP_LOGD(TAG, "[sclk] %"PRIu32" [mclk] %"PRIu32" [mclk_div] %d [bclk] %"PRIu32" [bclk_div] %d", clk_info->sclk, clk_info->mclk, clk_info->mclk_div, clk_info->bclk, clk_info->bclk_div); return ESP_OK; } @@ -1077,7 +1079,7 @@ esp_err_t i2s_set_clk(i2s_port_t i2s_num, uint32_t rate, uint32_t bits_cfg, i2s_ slot_mask = (slot_cfg->slot_mode == I2S_SLOT_MODE_MONO) ? 1 : 2; } ESP_RETURN_ON_FALSE(p_i2s[i2s_num]->total_slot >= (32 - __builtin_clz(slot_mask)), ESP_ERR_INVALID_ARG, TAG, - "The max channel number can't be greater than CH%d\n", p_i2s[i2s_num]->total_slot); + "The max channel number can't be greater than CH%"PRIu32, p_i2s[i2s_num]->total_slot); p_i2s[i2s_num]->active_slot = __builtin_popcount(slot_mask); } else #endif diff --git a/components/driver/deprecated/mcpwm_legacy.c b/components/driver/deprecated/mcpwm_legacy.c index 51a501563d..1d9577b8c0 100644 --- a/components/driver/deprecated/mcpwm_legacy.c +++ b/components/driver/deprecated/mcpwm_legacy.c @@ -8,7 +8,6 @@ #include "sdkconfig.h" #include "freertos/FreeRTOS.h" #include "freertos/semphr.h" -#include "freertos/xtensa_api.h" #include "freertos/task.h" #include "esp_log.h" #include "esp_err.h" @@ -104,6 +103,7 @@ static mcpwm_context_t context[SOC_MCPWM_GROUPS] = { .mcpwm_intr_handle = NULL, .cap_isr_func = {[0 ... SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER - 1] = {NULL, NULL}}, }, +#if SOC_MCPWM_GROUPS > 1 [1] = { .hal = {MCPWM_LL_GET_HW(1)}, .spinlock = portMUX_INITIALIZER_UNLOCKED, @@ -116,6 +116,7 @@ static mcpwm_context_t context[SOC_MCPWM_GROUPS] = { .mcpwm_intr_handle = NULL, .cap_isr_func = {[0 ... SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER - 1] = {NULL, NULL}}, } +#endif }; typedef void (*mcpwm_ll_gen_set_event_action_t)(mcpwm_dev_t *mcpwm, int op, int gen, int action); @@ -298,9 +299,11 @@ esp_err_t mcpwm_set_duty_in_us(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_critical_enter(mcpwm_num); int real_group_prescale = mcpwm_ll_group_get_clock_prescale(hal->dev); - unsigned long int real_timer_clk_hz = + // to avid multiplication overflow, use uint64_t here + uint64_t real_timer_clk_hz = MCPWM_GROUP_CLK_SRC_HZ / real_group_prescale / mcpwm_ll_timer_get_clock_prescale(hal->dev, timer_num); - mcpwm_ll_operator_set_compare_value(hal->dev, op, cmp, duty_in_us * real_timer_clk_hz / 1000000); + uint64_t compare_val = real_timer_clk_hz * duty_in_us / 1000000; + mcpwm_ll_operator_set_compare_value(hal->dev, op, cmp, (uint32_t)compare_val); mcpwm_ll_operator_enable_update_compare_on_tez(hal->dev, op, cmp, true); mcpwm_critical_exit(mcpwm_num); return ESP_OK; @@ -787,7 +790,7 @@ esp_err_t mcpwm_capture_enable_channel(mcpwm_unit_t mcpwm_num, mcpwm_capture_cha mcpwm_ll_capture_enable_negedge(hal->dev, cap_channel, cap_conf->cap_edge & MCPWM_NEG_EDGE); mcpwm_ll_capture_enable_posedge(hal->dev, cap_channel, cap_conf->cap_edge & MCPWM_POS_EDGE); mcpwm_ll_capture_set_prescale(hal->dev, cap_channel, cap_conf->cap_prescale); - // capture feature should be used with interupt, so enable it by default + // capture feature should be used with interrupt, so enable it by default mcpwm_ll_intr_enable(hal->dev, MCPWM_LL_EVENT_CAPTURE(cap_channel), true); mcpwm_ll_intr_clear_capture_status(hal->dev, 1 << cap_channel); mcpwm_critical_exit(mcpwm_num); diff --git a/components/driver/deprecated/rmt_legacy.c b/components/driver/deprecated/rmt_legacy.c index 53a8e6c79e..dbbc1886e6 100644 --- a/components/driver/deprecated/rmt_legacy.c +++ b/components/driver/deprecated/rmt_legacy.c @@ -586,11 +586,11 @@ static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_par s_rmt_source_clock_hz[channel] = rmt_source_clk_hz; #else if (s_rmt_source_clock_hz && rmt_source_clk_hz != s_rmt_source_clock_hz) { - ESP_LOGW(TAG, "RMT clock source has been configured to %d by other channel, now reconfigure it to %d", s_rmt_source_clock_hz, rmt_source_clk_hz); + ESP_LOGW(TAG, "RMT clock source has been configured to %"PRIu32" by other channel, now reconfigure it to %"PRIu32, s_rmt_source_clock_hz, rmt_source_clk_hz); } s_rmt_source_clock_hz = rmt_source_clk_hz; #endif - ESP_LOGD(TAG, "rmt_source_clk_hz: %d\n", rmt_source_clk_hz); + ESP_LOGD(TAG, "rmt_source_clk_hz: %"PRIu32, rmt_source_clk_hz); if (mode == RMT_MODE_TX) { uint16_t carrier_duty_percent = rmt_param->tx_config.carrier_duty_percent; @@ -625,7 +625,7 @@ static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_par } RMT_EXIT_CRITICAL(); - ESP_LOGD(TAG, "Rmt Tx Channel %u|Gpio %u|Sclk_Hz %u|Div %u|Carrier_Hz %u|Duty %u", + ESP_LOGD(TAG, "Rmt Tx Channel %u|Gpio %u|Sclk_Hz %"PRIu32"|Div %u|Carrier_Hz %"PRIu32"|Duty %u", channel, gpio_num, rmt_source_clk_hz, clk_div, carrier_freq_hz, carrier_duty_percent); } else if (RMT_MODE_RX == mode) { uint8_t filter_cnt = rmt_param->rx_config.filter_ticks_thresh; @@ -659,7 +659,7 @@ static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_par #endif RMT_EXIT_CRITICAL(); - ESP_LOGD(TAG, "Rmt Rx Channel %u|Gpio %u|Sclk_Hz %u|Div %u|Thresold %u|Filter %u", + ESP_LOGD(TAG, "Rmt Rx Channel %u|Gpio %u|Sclk_Hz %"PRIu32"|Div %u|Thresold %u|Filter %u", channel, gpio_num, rmt_source_clk_hz, clk_div, threshold, filter_cnt); } @@ -936,13 +936,9 @@ esp_err_t rmt_driver_uninstall(rmt_channel_t channel) RMT_ENTER_CRITICAL(); // check channel's working mode if (p_rmt_obj[channel]->rx_buf) { - rmt_ll_enable_interrupt(rmt_contex.hal.regs, RMT_LL_EVENT_RX_DONE(RMT_DECODE_RX_CHANNEL(channel)), false); - rmt_ll_enable_interrupt(rmt_contex.hal.regs, RMT_LL_EVENT_RX_ERROR(RMT_DECODE_RX_CHANNEL(channel)), false); -#if SOC_RMT_SUPPORT_RX_PINGPONG - rmt_ll_enable_interrupt(rmt_contex.hal.regs, RMT_LL_EVENT_RX_THRES(RMT_DECODE_RX_CHANNEL(channel)), false); -#endif + rmt_ll_enable_interrupt(rmt_contex.hal.regs, RMT_LL_EVENT_RX_MASK(RMT_DECODE_RX_CHANNEL(channel)) | RMT_LL_EVENT_RX_ERROR(RMT_DECODE_RX_CHANNEL(channel)), false); } else { - rmt_ll_enable_interrupt(rmt_contex.hal.regs, RMT_LL_EVENT_TX_DONE(channel) | RMT_LL_EVENT_TX_ERROR(channel) | RMT_LL_EVENT_TX_THRES(channel), false); + rmt_ll_enable_interrupt(rmt_contex.hal.regs, RMT_LL_EVENT_TX_MASK(channel) | RMT_LL_EVENT_TX_ERROR(channel), false); } RMT_EXIT_CRITICAL(); @@ -1001,10 +997,10 @@ esp_err_t rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, int intr } #if CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH - if (intr_alloc_flags & ESP_INTR_FLAG_IRAM ) { - ESP_LOGE(TAG, "ringbuf ISR functions in flash, but used in IRAM interrupt"); - return ESP_ERR_INVALID_ARG; - } + if (intr_alloc_flags & ESP_INTR_FLAG_IRAM ) { + ESP_LOGE(TAG, "ringbuf ISR functions in flash, but used in IRAM interrupt"); + return ESP_ERR_INVALID_ARG; + } #endif #if !CONFIG_SPIRAM_USE_MALLOC diff --git a/components/driver/deprecated/rtc_temperature_legacy.c b/components/driver/deprecated/rtc_temperature_legacy.c index eb69c7604e..965973dab7 100644 --- a/components/driver/deprecated/rtc_temperature_legacy.c +++ b/components/driver/deprecated/rtc_temperature_legacy.c @@ -145,7 +145,7 @@ esp_err_t temp_sensor_read_celsius(float *celsius) uint32_t tsens_out = 0; temp_sensor_get_config(&tsens); temp_sensor_read_raw(&tsens_out); - ESP_LOGV(TAG, "tsens_out %d", tsens_out); + ESP_LOGV(TAG, "tsens_out %"PRIu32, tsens_out); const tsens_dac_offset_t *dac = &dac_offset[tsens.dac_offset]; *celsius = parse_temp_sensor_raw_value(tsens_out, dac->offset); if (*celsius < dac->range_min || *celsius > dac->range_max) { diff --git a/components/driver/deprecated/timer_legacy.c b/components/driver/deprecated/timer_legacy.c index 6b12845e54..405d337f73 100644 --- a/components/driver/deprecated/timer_legacy.c +++ b/components/driver/deprecated/timer_legacy.c @@ -63,7 +63,7 @@ esp_err_t timer_get_counter_value(timer_group_t group_num, timer_idx_t timer_num ESP_RETURN_ON_FALSE(timer_val != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_PARAM_ADDR_ERROR); ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR); TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]); - *timer_val = timer_ll_get_counter_value(p_timer_obj[group_num][timer_num]->hal.dev, timer_num); + *timer_val = timer_hal_capture_and_get_counter_value(&p_timer_obj[group_num][timer_num]->hal); TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]); return ESP_OK; } @@ -74,7 +74,7 @@ esp_err_t timer_get_counter_time_sec(timer_group_t group_num, timer_idx_t timer_ ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR); ESP_RETURN_ON_FALSE(time != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_PARAM_ADDR_ERROR); ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR); - uint64_t timer_val = timer_ll_get_counter_value(p_timer_obj[group_num][timer_num]->hal.dev, timer_num); + uint64_t timer_val = timer_hal_capture_and_get_counter_value(&p_timer_obj[group_num][timer_num]->hal); uint32_t div = p_timer_obj[group_num][timer_num]->divider; // [clk_tree] TODO: replace the following switch table by clk_tree API switch (p_timer_obj[group_num][timer_num]->clk_src) { @@ -284,16 +284,18 @@ esp_err_t timer_isr_callback_add(timer_group_t group_num, timer_idx_t timer_num, ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR); ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR); ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR); + esp_err_t ret = ESP_OK; timer_disable_intr(group_num, timer_num); p_timer_obj[group_num][timer_num]->timer_isr_fun.fn = isr_handler; p_timer_obj[group_num][timer_num]->timer_isr_fun.args = args; p_timer_obj[group_num][timer_num]->timer_isr_fun.isr_timer_group = group_num; - timer_isr_register(group_num, timer_num, timer_isr_default, (void *)p_timer_obj[group_num][timer_num], - intr_alloc_flags, &(p_timer_obj[group_num][timer_num]->timer_isr_fun.timer_isr_handle)); + ret = timer_isr_register(group_num, timer_num, timer_isr_default, (void *)p_timer_obj[group_num][timer_num], + intr_alloc_flags, &(p_timer_obj[group_num][timer_num]->timer_isr_fun.timer_isr_handle)); + ESP_RETURN_ON_ERROR(ret, TIMER_TAG, "register interrupt service failed"); timer_enable_intr(group_num, timer_num); - return ESP_OK; + return ret; } esp_err_t timer_isr_callback_remove(timer_group_t group_num, timer_idx_t timer_num) @@ -357,9 +359,9 @@ esp_err_t timer_deinit(timer_group_t group_num, timer_idx_t timer_num) timer_hal_context_t *hal = &p_timer_obj[group_num][timer_num]->hal; TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]); - timer_ll_enable_counter(hal->dev, timer_num, false); timer_ll_enable_intr(hal->dev, TIMER_LL_EVENT_ALARM(timer_num), false); timer_ll_clear_intr_status(hal->dev, TIMER_LL_EVENT_ALARM(timer_num)); + timer_hal_deinit(hal); TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]); free(p_timer_obj[group_num][timer_num]); @@ -432,6 +434,7 @@ void IRAM_ATTR timer_group_enable_alarm_in_isr(timer_group_t group_num, timer_id uint64_t IRAM_ATTR timer_group_get_counter_value_in_isr(timer_group_t group_num, timer_idx_t timer_num) { + timer_ll_trigger_soft_capture(p_timer_obj[group_num][timer_num]->hal.dev, timer_num); uint64_t val = timer_ll_get_counter_value(p_timer_obj[group_num][timer_num]->hal.dev, timer_num); return val; } diff --git a/components/driver/esp32/touch_sensor.c b/components/driver/esp32/touch_sensor.c index 52f2219da3..3e65a7fcf2 100644 --- a/components/driver/esp32/touch_sensor.c +++ b/components/driver/esp32/touch_sensor.c @@ -15,7 +15,7 @@ #include "freertos/FreeRTOS.h" #include "freertos/xtensa_api.h" #include "freertos/semphr.h" -#include "freertos/timers.h" +#include "esp_timer.h" #include "esp_intr_alloc.h" #include "driver/rtc_io.h" #include "driver/touch_pad.h" @@ -32,8 +32,9 @@ #include "hal/touch_sensor_hal.h" typedef struct { - TimerHandle_t timer; + esp_timer_handle_t timer; uint16_t filtered_val[TOUCH_PAD_MAX]; + uint32_t filter_last_val[TOUCH_PAD_MAX]; uint16_t raw_val[TOUCH_PAD_MAX]; uint32_t filter_period; uint32_t period; @@ -97,27 +98,24 @@ esp_err_t touch_pad_set_filter_read_cb(filter_cb_t read_cb) static void touch_pad_filter_cb(void *arg) { - static uint32_t s_filtered_temp[TOUCH_PAD_MAX] = {0}; - - if (s_touch_pad_filter == NULL || rtc_touch_mux == NULL) { + if (s_touch_pad_filter == NULL) { return; } uint16_t val = 0; touch_fsm_mode_t mode; - xSemaphoreTake(rtc_touch_mux, portMAX_DELAY); touch_pad_get_fsm_mode(&mode); for (int i = 0; i < TOUCH_PAD_MAX; i++) { if ((s_touch_pad_init_bit >> i) & 0x1) { _touch_pad_read(i, &val, mode); s_touch_pad_filter->raw_val[i] = val; - s_filtered_temp[i] = s_filtered_temp[i] == 0 ? ((uint32_t)val << TOUCH_PAD_SHIFT_DEFAULT) : s_filtered_temp[i]; - s_filtered_temp[i] = _touch_filter_iir((val << TOUCH_PAD_SHIFT_DEFAULT), - s_filtered_temp[i], TOUCH_PAD_FILTER_FACTOR_DEFAULT); - s_touch_pad_filter->filtered_val[i] = (s_filtered_temp[i] + TOUCH_PAD_SHIFT_ROUND_DEFAULT) >> TOUCH_PAD_SHIFT_DEFAULT; + s_touch_pad_filter->filter_last_val[i] = s_touch_pad_filter->filter_last_val[i] == 0 ? + ((uint32_t)val << TOUCH_PAD_SHIFT_DEFAULT) : s_touch_pad_filter->filter_last_val[i]; + s_touch_pad_filter->filter_last_val[i] = _touch_filter_iir((val << TOUCH_PAD_SHIFT_DEFAULT), + s_touch_pad_filter->filter_last_val[i], TOUCH_PAD_FILTER_FACTOR_DEFAULT); + s_touch_pad_filter->filtered_val[i] = + (s_touch_pad_filter->filter_last_val[i] + TOUCH_PAD_SHIFT_ROUND_DEFAULT) >> TOUCH_PAD_SHIFT_DEFAULT; } } - xTimerReset(s_touch_pad_filter->timer, portMAX_DELAY); - xSemaphoreGive(rtc_touch_mux); if (s_filter_cb) { //return the raw data and filtered data. s_filter_cb(s_touch_pad_filter->raw_val, s_touch_pad_filter->filtered_val); @@ -334,11 +332,17 @@ esp_err_t touch_pad_init(void) esp_err_t touch_pad_deinit(void) { ESP_RETURN_ON_FALSE(rtc_touch_mux, ESP_FAIL, TOUCH_TAG, "Touch pad not initialized"); - if (s_touch_pad_filter) { - touch_pad_filter_stop(); - touch_pad_filter_delete(); - } + esp_err_t ret = ESP_OK; xSemaphoreTake(rtc_touch_mux, portMAX_DELAY); + if (s_touch_pad_filter) { + if (s_touch_pad_filter->timer) { + ESP_GOTO_ON_ERROR(esp_timer_stop(s_touch_pad_filter->timer), err, TOUCH_TAG, "failed to stop the timer"); + ESP_GOTO_ON_ERROR(esp_timer_delete(s_touch_pad_filter->timer), err, TOUCH_TAG, "failed to delete the timer"); + s_touch_pad_filter->timer = NULL; + } + free(s_touch_pad_filter); + s_touch_pad_filter = NULL; + } s_touch_pad_init_bit = 0x0000; TOUCH_ENTER_CRITICAL(); touch_hal_deinit(); @@ -347,6 +351,9 @@ esp_err_t touch_pad_deinit(void) vSemaphoreDelete(rtc_touch_mux); rtc_touch_mux = NULL; return ESP_OK; +err: + xSemaphoreGive(rtc_touch_mux); + return ret; } static esp_err_t _touch_pad_read(touch_pad_t touch_num, uint16_t *touch_value, touch_fsm_mode_t mode) @@ -419,13 +426,10 @@ esp_err_t touch_pad_set_filter_period(uint32_t new_period_ms) esp_err_t ret = ESP_OK; xSemaphoreTake(rtc_touch_mux, portMAX_DELAY); - if (s_touch_pad_filter) { - xTimerChangePeriod(s_touch_pad_filter->timer, new_period_ms / portTICK_PERIOD_MS, portMAX_DELAY); - s_touch_pad_filter->period = new_period_ms; - } else { - ESP_LOGE(TOUCH_TAG, "Touch pad filter deleted"); - ret = ESP_ERR_INVALID_STATE; - } + ESP_GOTO_ON_ERROR(esp_timer_stop(s_touch_pad_filter->timer), err, TOUCH_TAG, "failed to stop the timer"); + ESP_GOTO_ON_ERROR(esp_timer_start_periodic(s_touch_pad_filter->timer, new_period_ms * 1000), err, TOUCH_TAG, "failed to start the timer"); + s_touch_pad_filter->period = new_period_ms; +err: xSemaphoreGive(rtc_touch_mux); return ret; } @@ -453,43 +457,49 @@ esp_err_t touch_pad_filter_start(uint32_t filter_period_ms) ESP_RETURN_ON_FALSE(filter_period_ms >= portTICK_PERIOD_MS, ESP_ERR_INVALID_ARG, TOUCH_TAG, "Touch pad filter period error"); ESP_RETURN_ON_FALSE(rtc_touch_mux, ESP_ERR_INVALID_STATE, TOUCH_TAG, "Touch pad not initialized"); + esp_err_t ret = ESP_OK; xSemaphoreTake(rtc_touch_mux, portMAX_DELAY); if (s_touch_pad_filter == NULL) { s_touch_pad_filter = (touch_pad_filter_t *) calloc(1, sizeof(touch_pad_filter_t)); - if (s_touch_pad_filter == NULL) { - goto err_no_mem; - } + ESP_GOTO_ON_FALSE(s_touch_pad_filter, ESP_ERR_NO_MEM, err_no_mem, TOUCH_TAG, "no memory for filter"); } if (s_touch_pad_filter->timer == NULL) { - s_touch_pad_filter->timer = xTimerCreate("filter_tmr", filter_period_ms / portTICK_PERIOD_MS, pdFALSE, - NULL, (TimerCallbackFunction_t) touch_pad_filter_cb); - if (s_touch_pad_filter->timer == NULL) { - free(s_touch_pad_filter); - s_touch_pad_filter = NULL; - goto err_no_mem; - } + esp_timer_create_args_t timer_cfg = { + .callback = touch_pad_filter_cb, + .arg = NULL, + .dispatch_method = ESP_TIMER_TASK, + .name = "touch filter timer", + .skip_unhandled_events = true, + }; + ESP_GOTO_ON_ERROR(esp_timer_create(&timer_cfg, &(s_touch_pad_filter->timer)), + err_timer_create, TOUCH_TAG, "failed to create the filter timer"); s_touch_pad_filter->period = filter_period_ms; + touch_pad_filter_cb(NULL); // Trigger once immediately to get the initial raw value + ESP_GOTO_ON_ERROR(esp_timer_start_periodic(s_touch_pad_filter->timer, filter_period_ms * 1000), + err_timer_start, TOUCH_TAG, "failed to start the filter timer"); } - xSemaphoreGive(rtc_touch_mux); - touch_pad_filter_cb(NULL); - return ESP_OK; + xSemaphoreGive(rtc_touch_mux); + return ret; + +err_timer_start: + esp_timer_delete(s_touch_pad_filter->timer); +err_timer_create: + free(s_touch_pad_filter); + s_touch_pad_filter = NULL; err_no_mem: xSemaphoreGive(rtc_touch_mux); - return ESP_ERR_NO_MEM; + return ret; } esp_err_t touch_pad_filter_stop(void) { ESP_RETURN_ON_FALSE(s_touch_pad_filter, ESP_ERR_INVALID_STATE, TOUCH_TAG, "Touch pad filter not initialized"); ESP_RETURN_ON_FALSE(rtc_touch_mux, ESP_ERR_INVALID_STATE, TOUCH_TAG, "Touch pad not initialized"); - esp_err_t ret = ESP_OK; xSemaphoreTake(rtc_touch_mux, portMAX_DELAY); - if (s_touch_pad_filter) { - xTimerStop(s_touch_pad_filter->timer, portMAX_DELAY); - } else { - ESP_LOGE(TOUCH_TAG, "Touch pad filter deleted"); - ret = ESP_ERR_INVALID_STATE; + esp_err_t ret = esp_timer_stop(s_touch_pad_filter->timer); + if (ret != ESP_OK) { + ESP_LOGE(TOUCH_TAG, "failed to stop the timer"); } xSemaphoreGive(rtc_touch_mux); return ret; @@ -499,16 +509,16 @@ esp_err_t touch_pad_filter_delete(void) { ESP_RETURN_ON_FALSE(s_touch_pad_filter, ESP_ERR_INVALID_STATE, TOUCH_TAG, "Touch pad filter not initialized"); ESP_RETURN_ON_FALSE(rtc_touch_mux, ESP_ERR_INVALID_STATE, TOUCH_TAG, "Touch pad not initialized"); + esp_err_t ret = ESP_OK; xSemaphoreTake(rtc_touch_mux, portMAX_DELAY); - if (s_touch_pad_filter) { - if (s_touch_pad_filter->timer) { - xTimerStop(s_touch_pad_filter->timer, portMAX_DELAY); - xTimerDelete(s_touch_pad_filter->timer, portMAX_DELAY); - s_touch_pad_filter->timer = NULL; - } - free(s_touch_pad_filter); - s_touch_pad_filter = NULL; + if (s_touch_pad_filter->timer) { + ESP_GOTO_ON_ERROR(esp_timer_stop(s_touch_pad_filter->timer), err, TOUCH_TAG, "failed to stop the timer"); + ESP_GOTO_ON_ERROR(esp_timer_delete(s_touch_pad_filter->timer), err, TOUCH_TAG, "failed to delete the timer"); + s_touch_pad_filter->timer = NULL; } + free(s_touch_pad_filter); + s_touch_pad_filter = NULL; +err: xSemaphoreGive(rtc_touch_mux); - return ESP_OK; + return ret; } diff --git a/components/driver/gpio/dedic_gpio.c b/components/driver/gpio/dedic_gpio.c index 943dcdd2c4..b67217f7d8 100644 --- a/components/driver/gpio/dedic_gpio.c +++ b/components/driver/gpio/dedic_gpio.c @@ -67,7 +67,7 @@ struct dedic_gpio_bundle_t { int gpio_array[]; // array of GPIO numbers (configured by user) }; -static esp_err_t dedic_gpio_build_platform(uint32_t core_id) +static esp_err_t dedic_gpio_build_platform(int core_id) { esp_err_t ret = ESP_OK; if (!s_platform[core_id]) { @@ -196,7 +196,7 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_ dedic_gpio_bundle_t *bundle = NULL; uint32_t out_mask = 0; uint32_t in_mask = 0; - uint32_t core_id = esp_cpu_get_core_id(); // dedicated GPIO will be binded to the CPU who invokes this API + int core_id = esp_cpu_get_core_id(); // dedicated GPIO will be binded to the CPU who invokes this API ESP_GOTO_ON_FALSE(config && ret_bundle, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument"); ESP_GOTO_ON_FALSE(config->gpio_array && config->array_size > 0, ESP_ERR_INVALID_ARG, err, TAG, "invalid GPIO array or size"); @@ -233,7 +233,7 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_ } portEXIT_CRITICAL(&s_platform[core_id]->spinlock); ESP_GOTO_ON_FALSE(out_mask, ESP_ERR_NOT_FOUND, err, TAG, "no free outward channels on core[%d]", core_id); - ESP_LOGD(TAG, "new outward bundle(%p) on core[%d], offset=%d, mask(%x)", bundle, core_id, out_offset, out_mask); + ESP_LOGD(TAG, "new outward bundle(%p) on core[%d], offset=%"PRIu32", mask(%"PRIx32")", bundle, core_id, out_offset, out_mask); } // configure inwards channels @@ -255,7 +255,7 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_ } portEXIT_CRITICAL(&s_platform[core_id]->spinlock); ESP_GOTO_ON_FALSE(in_mask, ESP_ERR_NOT_FOUND, err, TAG, "no free inward channels on core[%d]", core_id); - ESP_LOGD(TAG, "new inward bundle(%p) on core[%d], offset=%d, mask(%x)", bundle, core_id, in_offset, in_mask); + ESP_LOGD(TAG, "new inward bundle(%p) on core[%d], offset=%"PRIu32", mask(%"PRIx32")", bundle, core_id, in_offset, in_mask); } // route dedicated GPIO channel signals to GPIO matrix @@ -377,7 +377,7 @@ esp_err_t dedic_gpio_bundle_set_interrupt_and_callback(dedic_gpio_bundle_handle_ { esp_err_t ret = ESP_OK; ESP_GOTO_ON_FALSE(bundle, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument"); - uint32_t core_id = esp_cpu_get_core_id(); + int core_id = esp_cpu_get_core_id(); // lazy alloc interrupt ESP_GOTO_ON_ERROR(dedic_gpio_install_interrupt(core_id), err, TAG, "allocate interrupt on core %d failed", core_id); diff --git a/components/driver/gpio/gpio.c b/components/driver/gpio/gpio.c index 0abbbeb5e0..f5644c3917 100644 --- a/components/driver/gpio/gpio.c +++ b/components/driver/gpio/gpio.c @@ -53,6 +53,7 @@ typedef struct { uint32_t isr_core_id; gpio_isr_func_t *gpio_isr_func; gpio_isr_handle_t gpio_isr_handle; + uint64_t isr_clr_on_entry_mask; // for edge-triggered interrupts, interrupt status bits should be cleared before entering per-pin handlers } gpio_context_t; static gpio_hal_context_t _gpio_hal = { @@ -64,6 +65,7 @@ static gpio_context_t gpio_context = { .gpio_spinlock = portMUX_INITIALIZER_UNLOCKED, .isr_core_id = GPIO_ISR_CORE_ID_UNINIT, .gpio_isr_func = NULL, + .isr_clr_on_entry_mask = 0, }; esp_err_t gpio_pullup_en(gpio_num_t gpio_num) @@ -149,13 +151,17 @@ esp_err_t gpio_set_intr_type(gpio_num_t gpio_num, gpio_int_type_t intr_type) portENTER_CRITICAL(&gpio_context.gpio_spinlock); gpio_hal_set_intr_type(gpio_context.gpio_hal, gpio_num, intr_type); + if (intr_type == GPIO_INTR_POSEDGE || intr_type == GPIO_INTR_NEGEDGE || intr_type == GPIO_INTR_ANYEDGE) { + gpio_context.isr_clr_on_entry_mask |= (1ULL << (gpio_num)); + } else { + gpio_context.isr_clr_on_entry_mask &= ~(1ULL << (gpio_num)); + } portEXIT_CRITICAL(&gpio_context.gpio_spinlock); return ESP_OK; } static esp_err_t gpio_intr_enable_on_core(gpio_num_t gpio_num, uint32_t core_id) { - GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); gpio_hal_intr_enable_on_core(gpio_context.gpio_hal, gpio_num, core_id); return ESP_OK; } @@ -371,7 +377,7 @@ esp_err_t gpio_config(const gpio_config_t *pGPIOConfig) gpio_pulldown_dis(io_num); } - ESP_LOGI(GPIO_TAG, "GPIO[%d]| InputEn: %d| OutputEn: %d| OpenDrain: %d| Pullup: %d| Pulldown: %d| Intr:%d ", io_num, input_en, output_en, od_en, pu_en, pd_en, pGPIOConfig->intr_type); + ESP_LOGI(GPIO_TAG, "GPIO[%"PRIu32"]| InputEn: %d| OutputEn: %d| OpenDrain: %d| Pullup: %d| Pulldown: %d| Intr:%d ", io_num, input_en, output_en, od_en, pu_en, pd_en, pGPIOConfig->intr_type); gpio_set_intr_type(io_num, pGPIOConfig->intr_type); if (pGPIOConfig->intr_type) { @@ -412,9 +418,21 @@ static inline void IRAM_ATTR gpio_isr_loop(uint32_t status, const uint32_t gpio_ status &= ~(1 << nbit); int gpio_num = gpio_num_start + nbit; + bool intr_status_bit_cleared = false; + // Edge-triggered type interrupt can clear the interrupt status bit before entering per-pin interrupt handler + if ((1ULL << (gpio_num)) & gpio_context.isr_clr_on_entry_mask) { + intr_status_bit_cleared = true; + gpio_hal_clear_intr_status_bit(gpio_context.gpio_hal, gpio_num); + } + if (gpio_context.gpio_isr_func[gpio_num].fn != NULL) { gpio_context.gpio_isr_func[gpio_num].fn(gpio_context.gpio_isr_func[gpio_num].args); } + + // If the interrupt status bit was not cleared at the entry, then must clear it before exiting + if (!intr_status_bit_cleared) { + gpio_hal_clear_intr_status_bit(gpio_context.gpio_hal, gpio_num); + } } } @@ -431,7 +449,6 @@ static void IRAM_ATTR gpio_intr_service(void *arg) if (gpio_intr_status) { gpio_isr_loop(gpio_intr_status, 0); - gpio_hal_clear_intr_status(gpio_context.gpio_hal, gpio_intr_status); } //read status1 to get interrupt status for GPIO32-39 @@ -440,21 +457,30 @@ static void IRAM_ATTR gpio_intr_service(void *arg) if (gpio_intr_status_h) { gpio_isr_loop(gpio_intr_status_h, 32); - gpio_hal_clear_intr_status_high(gpio_context.gpio_hal, gpio_intr_status_h); } } esp_err_t gpio_install_isr_service(int intr_alloc_flags) { GPIO_CHECK(gpio_context.gpio_isr_func == NULL, "GPIO isr service already installed", ESP_ERR_INVALID_STATE); - esp_err_t ret; - portENTER_CRITICAL(&gpio_context.gpio_spinlock); - gpio_context.gpio_isr_func = (gpio_isr_func_t *) calloc(GPIO_NUM_MAX, sizeof(gpio_isr_func_t)); - portEXIT_CRITICAL(&gpio_context.gpio_spinlock); - if (gpio_context.gpio_isr_func == NULL) { - ret = ESP_ERR_NO_MEM; - } else { - ret = gpio_isr_register(gpio_intr_service, NULL, intr_alloc_flags, &gpio_context.gpio_isr_handle); + esp_err_t ret = ESP_ERR_NO_MEM; + gpio_isr_func_t *isr_func = (gpio_isr_func_t *) calloc(GPIO_NUM_MAX, sizeof(gpio_isr_func_t)); + if (isr_func) { + portENTER_CRITICAL(&gpio_context.gpio_spinlock); + if (gpio_context.gpio_isr_func == NULL) { + gpio_context.gpio_isr_func = isr_func; + portEXIT_CRITICAL(&gpio_context.gpio_spinlock); + ret = gpio_isr_register(gpio_intr_service, NULL, intr_alloc_flags, &gpio_context.gpio_isr_handle); + if (ret != ESP_OK) { + // registering failed, uninstall isr service + gpio_uninstall_isr_service(); + } + } else { + // isr service already installed, free allocated resource + portEXIT_CRITICAL(&gpio_context.gpio_spinlock); + ret = ESP_ERR_INVALID_STATE; + free(isr_func); + } } return ret; diff --git a/components/driver/gptimer.c b/components/driver/gptimer.c index c8e7c1d38f..a278ee3888 100644 --- a/components/driver/gptimer.c +++ b/components/driver/gptimer.c @@ -71,16 +71,17 @@ typedef enum { struct gptimer_t { gptimer_group_t *group; int timer_id; - unsigned int resolution_hz; - unsigned long long reload_count; - unsigned long long alarm_count; + uint32_t resolution_hz; + uint64_t reload_count; + uint64_t alarm_count; gptimer_count_direction_t direction; timer_hal_context_t hal; gptimer_fsm_t fsm; intr_handle_t intr; - portMUX_TYPE spinlock; // to protect per-timer resources concurent accessed by task and ISR handler + portMUX_TYPE spinlock; // to protect per-timer resources concurrent accessed by task and ISR handler gptimer_alarm_cb_t on_alarm; void *user_ctx; + gptimer_clock_source_t clk_src; esp_pm_lock_handle_t pm_lock; // power management lock #if CONFIG_PM_ENABLE char pm_lock_name[GPTIMER_PM_LOCK_NAME_LEN_MAX]; // pm lock name @@ -164,7 +165,7 @@ esp_err_t gptimer_new_timer(const gptimer_config_t *config, gptimer_handle_t *re esp_err_t ret = ESP_OK; gptimer_t *timer = NULL; ESP_GOTO_ON_FALSE(config && ret_timer, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument"); - ESP_GOTO_ON_FALSE(config->resolution_hz, ESP_ERR_INVALID_ARG, err, TAG, "invalid timer resolution:%d", config->resolution_hz); + ESP_GOTO_ON_FALSE(config->resolution_hz, ESP_ERR_INVALID_ARG, err, TAG, "invalid timer resolution:%"PRIu32, config->resolution_hz); timer = heap_caps_calloc(1, sizeof(gptimer_t), GPTIMER_MEM_ALLOC_CAPS); ESP_GOTO_ON_FALSE(timer, ESP_ERR_NO_MEM, err, TAG, "no mem for gptimer"); @@ -176,10 +177,6 @@ esp_err_t gptimer_new_timer(const gptimer_config_t *config, gptimer_handle_t *re // initialize HAL layer timer_hal_init(&timer->hal, group_id, timer_id); - // stop counter, alarm, auto-reload - timer_ll_enable_counter(timer->hal.dev, timer_id, false); - timer_ll_enable_auto_reload(timer->hal.dev, timer_id, false); - timer_ll_enable_alarm(timer->hal.dev, timer_id, false); // select clock source, set clock resolution ESP_GOTO_ON_ERROR(gptimer_select_periph_clock(timer, config->clk_src, config->resolution_hz), err, TAG, "set periph clock failed"); // initialize counter value to zero @@ -197,7 +194,7 @@ esp_err_t gptimer_new_timer(const gptimer_config_t *config, gptimer_handle_t *re timer->fsm = GPTIMER_FSM_INIT; // put the timer into init state timer->direction = config->direction; timer->flags.intr_shared = config->flags.intr_shared; - ESP_LOGD(TAG, "new gptimer (%d,%d) at %p, resolution=%uHz", group_id, timer_id, timer, timer->resolution_hz); + ESP_LOGD(TAG, "new gptimer (%d,%d) at %p, resolution=%"PRIu32"Hz", group_id, timer_id, timer, timer->resolution_hz); *ret_timer = timer; return ESP_OK; @@ -216,6 +213,7 @@ esp_err_t gptimer_del_timer(gptimer_handle_t timer) int group_id = group->group_id; int timer_id = timer->timer_id; ESP_LOGD(TAG, "del timer (%d,%d)", group_id, timer_id); + timer_hal_deinit(&timer->hal); // recycle memory resource ESP_RETURN_ON_ERROR(gptimer_destory(timer), TAG, "destory gptimer failed"); return ESP_OK; @@ -236,7 +234,7 @@ esp_err_t gptimer_get_raw_count(gptimer_handle_t timer, unsigned long long *valu ESP_RETURN_ON_FALSE_ISR(timer && value, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); portENTER_CRITICAL_SAFE(&timer->spinlock); - *value = timer_ll_get_counter_value(timer->hal.dev, timer->timer_id); + *value = timer_hal_capture_and_get_counter_value(&timer->hal); portEXIT_CRITICAL_SAFE(&timer->spinlock); return ESP_OK; } @@ -245,7 +243,6 @@ esp_err_t gptimer_register_event_callbacks(gptimer_handle_t timer, const gptimer { gptimer_group_t *group = NULL; ESP_RETURN_ON_FALSE(timer && cbs, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - ESP_RETURN_ON_FALSE(timer->fsm == GPTIMER_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "timer not in init state"); group = timer->group; int group_id = group->group_id; int timer_id = timer->timer_id; @@ -261,6 +258,7 @@ esp_err_t gptimer_register_event_callbacks(gptimer_handle_t timer, const gptimer // lazy install interrupt service if (!timer->intr) { + ESP_RETURN_ON_FALSE(timer->fsm == GPTIMER_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "timer not in init state"); // if user wants to control the interrupt allocation more precisely, we can expose more flags in `gptimer_config_t` int isr_flags = timer->flags.intr_shared ? ESP_INTR_FLAG_SHARED | GPTIMER_INTR_ALLOC_FLAGS : GPTIMER_INTR_ALLOC_FLAGS; ESP_RETURN_ON_ERROR(esp_intr_alloc_intrstatus(timer_group_periph_signals.groups[group_id].timer_irq_id[timer_id], isr_flags, @@ -318,7 +316,7 @@ esp_err_t gptimer_enable(gptimer_handle_t timer) if (timer->pm_lock) { ESP_RETURN_ON_ERROR(esp_pm_lock_acquire(timer->pm_lock), TAG, "acquire pm_lock failed"); } - // enable interrupt interupt service + // enable interrupt service if (timer->intr) { ESP_RETURN_ON_ERROR(esp_intr_enable(timer->intr), TAG, "enable interrupt service failed"); } @@ -476,11 +474,12 @@ static esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_sou break; } timer_ll_set_clock_source(timer->hal.dev, timer_id, src_clk); + timer->clk_src = src_clk; unsigned int prescale = counter_src_hz / resolution_hz; // potential resolution loss here timer_ll_set_clock_prescale(timer->hal.dev, timer_id, prescale); timer->resolution_hz = counter_src_hz / prescale; // this is the real resolution if (timer->resolution_hz != resolution_hz) { - ESP_LOGW(TAG, "resolution lost, expect %u, real %u", resolution_hz, timer->resolution_hz); + ESP_LOGW(TAG, "resolution lost, expect %"PRIu32", real %"PRIu32, resolution_hz, timer->resolution_hz); } return ret; } @@ -497,7 +496,7 @@ IRAM_ATTR static void gptimer_default_isr(void *args) if (intr_status & TIMER_LL_EVENT_ALARM(timer->timer_id)) { // Note: when alarm event happens, the alarm will be disabled automatically by hardware gptimer_alarm_event_data_t edata = { - .count_value = timer_ll_get_counter_value(timer->hal.dev, timer->timer_id), + .count_value = timer_hal_capture_and_get_counter_value(&timer->hal), .alarm_value = timer->alarm_count, }; diff --git a/components/driver/i2c.c b/components/driver/i2c.c index 78b779858a..2889955ea4 100644 --- a/components/driver/i2c.c +++ b/components/driver/i2c.c @@ -34,8 +34,6 @@ #include "clk_ctrl_os.h" #endif - - static const char *I2C_TAG = "i2c"; /* DRAM_ATTR is required to avoid I2C array placed in flash, due to accessed from ISR */ @@ -105,6 +103,14 @@ static const char *I2C_TAG = "i2c"; #define I2C_CLOCK_INVALID (-1) +/** + * I2C bus are defined in the header files, let's check that the values are correct + */ +#if SOC_I2C_NUM >= 2 +_Static_assert(I2C_NUM_1 == 1, "I2C_NUM_1 must be equal to 1"); +#endif // SOC_I2C_NUM >= 2 +_Static_assert(I2C_NUM_MAX == SOC_I2C_NUM, "I2C_NUM_MAX must be equal to SOC_I2C_NUM"); + typedef struct { i2c_hw_cmd_t hw_cmd; union { @@ -193,7 +199,9 @@ typedef struct static i2c_context_t i2c_context[I2C_NUM_MAX] = { I2C_CONTEX_INIT_DEF(I2C_NUM_0), -#if I2C_NUM_MAX > 1 +/* Now that I2C_NUM_MAX is part of an enum (i2c_port_t), we cannot use + * it anomore in the preprocessor! */ +#if SOC_I2C_NUM > 1 I2C_CONTEX_INIT_DEF(I2C_NUM_1), #endif }; @@ -366,8 +374,8 @@ esp_err_t i2c_driver_install(i2c_port_t i2c_num, i2c_mode_t mode, size_t slv_rx_ } i2c_hw_enable(i2c_num); //Disable I2C interrupt. - i2c_hal_disable_intr_mask(&(i2c_context[i2c_num].hal), I2C_LL_INTR_MASK); - i2c_hal_clr_intsts_mask(&(i2c_context[i2c_num].hal), I2C_LL_INTR_MASK); + i2c_ll_disable_intr_mask(i2c_context[i2c_num].hal.dev, I2C_LL_INTR_MASK); + i2c_ll_clear_intr_mask(i2c_context[i2c_num].hal.dev, I2C_LL_INTR_MASK); //hook isr handler ret = esp_intr_alloc(i2c_periph_signal[i2c_num].irq, intr_alloc_flags, i2c_isr_handler_default, p_i2c_obj[i2c_num], @@ -376,7 +384,7 @@ esp_err_t i2c_driver_install(i2c_port_t i2c_num, i2c_mode_t mode, size_t slv_rx_ #if SOC_I2C_SUPPORT_SLAVE //Enable I2C slave rx interrupt if (mode == I2C_MODE_SLAVE) { - i2c_hal_enable_slave_rx_it(&(i2c_context[i2c_num].hal)); + i2c_ll_slave_enable_rx_it(i2c_context[i2c_num].hal.dev); } #endif // SOC_I2C_SUPPORT_SLAVE return ESP_OK; @@ -433,7 +441,7 @@ esp_err_t i2c_driver_delete(i2c_port_t i2c_num) ESP_RETURN_ON_FALSE(p_i2c_obj[i2c_num] != NULL, ESP_FAIL, I2C_TAG, I2C_DRIVER_ERR_STR); i2c_obj_t *p_i2c = p_i2c_obj[i2c_num]; - i2c_hal_disable_intr_mask(&(i2c_context[i2c_num].hal), I2C_LL_INTR_MASK); + i2c_ll_disable_intr_mask(i2c_context[i2c_num].hal.dev, I2C_LL_INTR_MASK); esp_intr_free(p_i2c->intr_handle); p_i2c->intr_handle = NULL; @@ -490,7 +498,7 @@ esp_err_t i2c_reset_tx_fifo(i2c_port_t i2c_num) { ESP_RETURN_ON_FALSE(i2c_num < I2C_NUM_MAX, ESP_ERR_INVALID_ARG, I2C_TAG, I2C_NUM_ERROR_STR); I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock)); - i2c_hal_txfifo_rst(&(i2c_context[i2c_num].hal)); + i2c_ll_txfifo_rst(i2c_context[i2c_num].hal.dev); I2C_EXIT_CRITICAL(&(i2c_context[i2c_num].spinlock)); return ESP_OK; } @@ -499,7 +507,7 @@ esp_err_t i2c_reset_rx_fifo(i2c_port_t i2c_num) { ESP_RETURN_ON_FALSE(i2c_num < I2C_NUM_MAX, ESP_ERR_INVALID_ARG, I2C_TAG, I2C_NUM_ERROR_STR); I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock)); - i2c_hal_rxfifo_rst(&(i2c_context[i2c_num].hal)); + i2c_ll_rxfifo_rst(i2c_context[i2c_num].hal.dev); I2C_EXIT_CRITICAL(&(i2c_context[i2c_num].spinlock)); return ESP_OK; } @@ -512,7 +520,7 @@ static void IRAM_ATTR i2c_isr_handler_default(void *arg) // On C3 and S3 targets, the I2C may trigger a spurious interrupt, // in order to detect these false positive, check the I2C's hardware interrupt mask uint32_t int_mask; - i2c_hal_get_intsts_mask(&(i2c_context[i2c_num].hal), &int_mask); + i2c_ll_get_intr_mask(i2c_context[i2c_num].hal.dev, &int_mask); if (int_mask == 0) { return; } @@ -551,25 +559,25 @@ static void IRAM_ATTR i2c_isr_handler_default(void *arg) } #if SOC_I2C_SUPPORT_SLAVE else { - i2c_hal_slave_handle_event(&(i2c_context[i2c_num].hal), &evt_type); + i2c_ll_slave_get_event(i2c_context[i2c_num].hal.dev, &evt_type); if (evt_type == I2C_INTR_EVENT_TRANS_DONE || evt_type == I2C_INTR_EVENT_RXFIFO_FULL) { uint32_t rx_fifo_cnt; - i2c_hal_get_rxfifo_cnt(&(i2c_context[i2c_num].hal), &rx_fifo_cnt); - i2c_hal_read_rxfifo(&(i2c_context[i2c_num].hal), p_i2c->data_buf, rx_fifo_cnt); + i2c_ll_get_rxfifo_cnt(i2c_context[i2c_num].hal.dev, &rx_fifo_cnt); + i2c_ll_read_rxfifo(i2c_context[i2c_num].hal.dev, p_i2c->data_buf, rx_fifo_cnt); xRingbufferSendFromISR(p_i2c->rx_ring_buf, p_i2c->data_buf, rx_fifo_cnt, &HPTaskAwoken); - i2c_hal_slave_clr_rx_it(&(i2c_context[i2c_num].hal)); + i2c_ll_clear_intr_mask(i2c_context[i2c_num].hal.dev, int_mask); } else if (evt_type == I2C_INTR_EVENT_TXFIFO_EMPTY) { uint32_t tx_fifo_rem; - i2c_hal_get_txfifo_cnt(&(i2c_context[i2c_num].hal), &tx_fifo_rem); + i2c_ll_get_txfifo_len(i2c_context[i2c_num].hal.dev, &tx_fifo_rem); size_t size = 0; uint8_t *data = (uint8_t *) xRingbufferReceiveUpToFromISR(p_i2c->tx_ring_buf, &size, tx_fifo_rem); if (data) { - i2c_hal_write_txfifo(&(i2c_context[i2c_num].hal), data, size); + i2c_ll_write_txfifo(i2c_context[i2c_num].hal.dev, data, size); vRingbufferReturnItemFromISR(p_i2c->tx_ring_buf, data, &HPTaskAwoken); } else { - i2c_hal_disable_slave_tx_it(&(i2c_context[i2c_num].hal)); + i2c_ll_slave_disable_tx_it(i2c_context[i2c_num].hal.dev); } - i2c_hal_slave_clr_tx_it(&(i2c_context[i2c_num].hal)); + i2c_ll_clear_intr_mask(i2c_context[i2c_num].hal.dev, int_mask); } } #endif // SOC_I2C_SUPPORT_SLAVE @@ -585,8 +593,8 @@ esp_err_t i2c_set_data_mode(i2c_port_t i2c_num, i2c_trans_mode_t tx_trans_mode, ESP_RETURN_ON_FALSE(tx_trans_mode < I2C_DATA_MODE_MAX, ESP_ERR_INVALID_ARG, I2C_TAG, I2C_TRANS_MODE_ERR_STR); ESP_RETURN_ON_FALSE(rx_trans_mode < I2C_DATA_MODE_MAX, ESP_ERR_INVALID_ARG, I2C_TAG, I2C_TRANS_MODE_ERR_STR); I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock)); - i2c_hal_set_data_mode(&(i2c_context[i2c_num].hal), tx_trans_mode, rx_trans_mode); - i2c_hal_update_config(&(i2c_context[i2c_num].hal)); + i2c_ll_set_data_mode(i2c_context[i2c_num].hal.dev, tx_trans_mode, rx_trans_mode); + i2c_ll_update(i2c_context[i2c_num].hal.dev); I2C_EXIT_CRITICAL(&(i2c_context[i2c_num].spinlock)); return ESP_OK; } @@ -594,7 +602,7 @@ esp_err_t i2c_set_data_mode(i2c_port_t i2c_num, i2c_trans_mode_t tx_trans_mode, esp_err_t i2c_get_data_mode(i2c_port_t i2c_num, i2c_trans_mode_t *tx_trans_mode, i2c_trans_mode_t *rx_trans_mode) { ESP_RETURN_ON_FALSE(i2c_num < I2C_NUM_MAX, ESP_ERR_INVALID_ARG, I2C_TAG, I2C_NUM_ERROR_STR); - i2c_hal_get_data_mode(&(i2c_context[i2c_num].hal), tx_trans_mode, rx_trans_mode); + i2c_ll_get_data_mode(i2c_context[i2c_num].hal.dev, tx_trans_mode, rx_trans_mode); return ESP_OK; } @@ -632,7 +640,7 @@ static esp_err_t i2c_master_clear_bus(i2c_port_t i2c_num) gpio_set_level(sda_io, 1); // STOP, SDA low -> high while SCL is HIGH i2c_set_pin(i2c_num, sda_io, scl_io, 1, 1, I2C_MODE_MASTER); #else - i2c_hal_master_clr_bus(&(i2c_context[i2c_num].hal)); + i2c_ll_master_clr_bus(i2c_context[i2c_num].hal.dev); #endif return ESP_OK; } @@ -646,36 +654,24 @@ static esp_err_t i2c_hw_fsm_reset(i2c_port_t i2c_num) // A workaround for avoiding cause timeout issue when using // hardware reset. #if !SOC_I2C_SUPPORT_HW_FSM_RST - int scl_low_period, scl_high_period, scl_wait_high_period; - int scl_start_hold, scl_rstart_setup; - int scl_stop_hold, scl_stop_setup; - int sda_hold, sda_sample; - int timeout; + i2c_hal_timing_config_t timing_config; uint8_t filter_cfg; - i2c_hal_get_scl_clk_timing(&(i2c_context[i2c_num].hal), &scl_high_period, &scl_low_period, &scl_wait_high_period); - i2c_hal_get_start_timing(&(i2c_context[i2c_num].hal), &scl_rstart_setup, &scl_start_hold); - i2c_hal_get_stop_timing(&(i2c_context[i2c_num].hal), &scl_stop_setup, &scl_stop_hold); - i2c_hal_get_sda_timing(&(i2c_context[i2c_num].hal), &sda_sample, &sda_hold); - i2c_hal_get_tout(&(i2c_context[i2c_num].hal), &timeout); - i2c_hal_get_filter(&(i2c_context[i2c_num].hal), &filter_cfg); + i2c_hal_get_timing_config(&i2c_context[i2c_num].hal, &timing_config); + i2c_ll_get_filter(i2c_context[i2c_num].hal.dev, &filter_cfg); //to reset the I2C hw module, we need re-enable the hw i2c_hw_disable(i2c_num); i2c_master_clear_bus(i2c_num); i2c_hw_enable(i2c_num); - i2c_hal_master_init(&(i2c_context[i2c_num].hal), i2c_num); - i2c_hal_disable_intr_mask(&(i2c_context[i2c_num].hal), I2C_LL_INTR_MASK); - i2c_hal_clr_intsts_mask(&(i2c_context[i2c_num].hal), I2C_LL_INTR_MASK); - i2c_hal_set_scl_clk_timing(&(i2c_context[i2c_num].hal), scl_high_period, scl_low_period, scl_wait_high_period); - i2c_hal_set_start_timing(&(i2c_context[i2c_num].hal), scl_rstart_setup, scl_start_hold); - i2c_hal_set_stop_timing(&(i2c_context[i2c_num].hal), scl_stop_setup, scl_stop_hold); - i2c_hal_set_sda_timing(&(i2c_context[i2c_num].hal), sda_sample, sda_hold); - i2c_hal_set_tout(&(i2c_context[i2c_num].hal), timeout); - i2c_hal_set_filter(&(i2c_context[i2c_num].hal), filter_cfg); + i2c_hal_master_init(&(i2c_context[i2c_num].hal)); + i2c_ll_disable_intr_mask(i2c_context[i2c_num].hal.dev, I2C_LL_INTR_MASK); + i2c_ll_clear_intr_mask(i2c_context[i2c_num].hal.dev, I2C_LL_INTR_MASK); + i2c_hal_set_timing_config(&i2c_context[i2c_num].hal, &timing_config); + i2c_ll_set_filter(i2c_context[i2c_num].hal.dev, filter_cfg); #else - i2c_hal_master_fsm_rst(&(i2c_context[i2c_num].hal)); + i2c_ll_master_fsm_rst(i2c_context[i2c_num].hal.dev); i2c_master_clear_bus(i2c_num); #endif return ESP_OK; @@ -759,28 +755,29 @@ esp_err_t i2c_param_config(i2c_port_t i2c_num, const i2c_config_t *i2c_conf) } i2c_hw_enable(i2c_num); I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock)); - i2c_hal_disable_intr_mask(&(i2c_context[i2c_num].hal), I2C_LL_INTR_MASK); - i2c_hal_clr_intsts_mask(&(i2c_context[i2c_num].hal), I2C_LL_INTR_MASK); + i2c_ll_disable_intr_mask(i2c_context[i2c_num].hal.dev, I2C_LL_INTR_MASK); + i2c_ll_clear_intr_mask(i2c_context[i2c_num].hal.dev, I2C_LL_INTR_MASK); #if SOC_I2C_SUPPORT_SLAVE if (i2c_conf->mode == I2C_MODE_SLAVE) { //slave mode - i2c_hal_slave_init(&(i2c_context[i2c_num].hal), i2c_num); - i2c_hal_set_source_clk(&(i2c_context[i2c_num].hal), src_clk); - i2c_hal_set_slave_addr(&(i2c_context[i2c_num].hal), i2c_conf->slave.slave_addr, i2c_conf->slave.addr_10bit_en); - i2c_hal_set_rxfifo_full_thr(&(i2c_context[i2c_num].hal), I2C_FIFO_FULL_THRESH_VAL); - i2c_hal_set_txfifo_empty_thr(&(i2c_context[i2c_num].hal), I2C_FIFO_EMPTY_THRESH_VAL); + i2c_hal_slave_init(&(i2c_context[i2c_num].hal)); + i2c_ll_slave_tx_auto_start_en(i2c_context[i2c_num].hal.dev, true); + i2c_ll_set_source_clk(i2c_context[i2c_num].hal.dev, src_clk); + i2c_ll_set_slave_addr(i2c_context[i2c_num].hal.dev, i2c_conf->slave.slave_addr, i2c_conf->slave.addr_10bit_en); + i2c_ll_set_rxfifo_full_thr(i2c_context[i2c_num].hal.dev, I2C_FIFO_FULL_THRESH_VAL); + i2c_ll_set_txfifo_empty_thr(i2c_context[i2c_num].hal.dev, I2C_FIFO_EMPTY_THRESH_VAL); //set timing for data - i2c_hal_set_sda_timing(&(i2c_context[i2c_num].hal), I2C_SLAVE_SDA_SAMPLE_DEFAULT, I2C_SLAVE_SDA_HOLD_DEFAULT); - i2c_hal_set_tout(&(i2c_context[i2c_num].hal), I2C_SLAVE_TIMEOUT_DEFAULT); - i2c_hal_enable_slave_rx_it(&(i2c_context[i2c_num].hal)); + i2c_ll_set_sda_timing(i2c_context[i2c_num].hal.dev, I2C_SLAVE_SDA_SAMPLE_DEFAULT, I2C_SLAVE_SDA_HOLD_DEFAULT); + i2c_ll_set_tout(i2c_context[i2c_num].hal.dev, I2C_SLAVE_TIMEOUT_DEFAULT); + i2c_ll_slave_enable_rx_it(i2c_context[i2c_num].hal.dev); } else #endif // SOC_I2C_SUPPORT_SLAVE { - i2c_hal_master_init(&(i2c_context[i2c_num].hal), i2c_num); + i2c_hal_master_init(&(i2c_context[i2c_num].hal)); //Default, we enable hardware filter - i2c_hal_set_filter(&(i2c_context[i2c_num].hal), I2C_FILTER_CYC_NUM_DEF); + i2c_ll_set_filter(i2c_context[i2c_num].hal.dev, I2C_FILTER_CYC_NUM_DEF); i2c_hal_set_bus_timing(&(i2c_context[i2c_num].hal), i2c_conf->master.clk_speed, src_clk, s_get_src_clk_freq(src_clk)); } - i2c_hal_update_config(&(i2c_context[i2c_num].hal)); + i2c_ll_update(i2c_context[i2c_num].hal.dev); I2C_EXIT_CRITICAL(&(i2c_context[i2c_num].spinlock)); return ESP_OK; } @@ -792,8 +789,8 @@ esp_err_t i2c_set_period(i2c_port_t i2c_num, int high_period, int low_period) ESP_RETURN_ON_FALSE((low_period <= I2C_SCL_LOW_PERIOD_V) && (low_period > 0), ESP_ERR_INVALID_ARG, I2C_TAG, I2C_TIMING_VAL_ERR_STR); I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock)); - i2c_hal_set_scl_timing(&(i2c_context[i2c_num].hal), high_period, low_period); - i2c_hal_update_config(&(i2c_context[i2c_num].hal)); + i2c_ll_set_scl_timing(i2c_context[i2c_num].hal.dev, high_period, low_period); + i2c_ll_update(i2c_context[i2c_num].hal.dev); I2C_EXIT_CRITICAL(&(i2c_context[i2c_num].spinlock)); return ESP_OK; } @@ -802,7 +799,7 @@ esp_err_t i2c_get_period(i2c_port_t i2c_num, int *high_period, int *low_period) { ESP_RETURN_ON_FALSE(i2c_num < I2C_NUM_MAX && high_period != NULL && low_period != NULL, ESP_ERR_INVALID_ARG, I2C_TAG, I2C_NUM_ERROR_STR); I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock)); - i2c_hal_get_scl_timing(&(i2c_context[i2c_num].hal), high_period, low_period); + i2c_ll_get_scl_timing(i2c_context[i2c_num].hal.dev, high_period, low_period); I2C_EXIT_CRITICAL(&(i2c_context[i2c_num].spinlock)); return ESP_OK; } @@ -812,8 +809,8 @@ esp_err_t i2c_filter_enable(i2c_port_t i2c_num, uint8_t cyc_num) ESP_RETURN_ON_FALSE(i2c_num < I2C_NUM_MAX, ESP_ERR_INVALID_ARG, I2C_TAG, I2C_NUM_ERROR_STR); ESP_RETURN_ON_FALSE(p_i2c_obj[i2c_num] != NULL, ESP_FAIL, I2C_TAG, I2C_DRIVER_ERR_STR); I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock)); - i2c_hal_set_filter(&(i2c_context[i2c_num].hal), cyc_num); - i2c_hal_update_config(&(i2c_context[i2c_num].hal)); + i2c_ll_set_filter(i2c_context[i2c_num].hal.dev, cyc_num); + i2c_ll_update(i2c_context[i2c_num].hal.dev); I2C_EXIT_CRITICAL(&(i2c_context[i2c_num].spinlock)); return ESP_OK; } @@ -822,8 +819,8 @@ esp_err_t i2c_filter_disable(i2c_port_t i2c_num) { ESP_RETURN_ON_FALSE(i2c_num < I2C_NUM_MAX, ESP_ERR_INVALID_ARG, I2C_TAG, I2C_NUM_ERROR_STR); I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock)); - i2c_hal_set_filter(&(i2c_context[i2c_num].hal), 0); - i2c_hal_update_config(&(i2c_context[i2c_num].hal)); + i2c_ll_set_filter(i2c_context[i2c_num].hal.dev, 0); + i2c_ll_update(i2c_context[i2c_num].hal.dev); I2C_EXIT_CRITICAL(&(i2c_context[i2c_num].spinlock)); return ESP_OK; } @@ -835,8 +832,8 @@ esp_err_t i2c_set_start_timing(i2c_port_t i2c_num, int setup_time, int hold_time ESP_RETURN_ON_FALSE((setup_time <= I2C_SCL_RSTART_SETUP_TIME_V) && (setup_time > 0), ESP_ERR_INVALID_ARG, I2C_TAG, I2C_TIMING_VAL_ERR_STR); I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock)); - i2c_hal_set_start_timing(&(i2c_context[i2c_num].hal), setup_time, hold_time); - i2c_hal_update_config(&(i2c_context[i2c_num].hal)); + i2c_ll_set_start_timing(i2c_context[i2c_num].hal.dev, setup_time, hold_time); + i2c_ll_update(i2c_context[i2c_num].hal.dev); I2C_EXIT_CRITICAL(&(i2c_context[i2c_num].spinlock)); return ESP_OK; } @@ -845,7 +842,7 @@ esp_err_t i2c_get_start_timing(i2c_port_t i2c_num, int *setup_time, int *hold_ti { ESP_RETURN_ON_FALSE(i2c_num < I2C_NUM_MAX && setup_time != NULL && hold_time != NULL, ESP_ERR_INVALID_ARG, I2C_TAG, I2C_NUM_ERROR_STR); I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock)); - i2c_hal_get_start_timing(&(i2c_context[i2c_num].hal), setup_time, hold_time); + i2c_ll_get_start_timing(i2c_context[i2c_num].hal.dev, setup_time, hold_time); I2C_EXIT_CRITICAL(&(i2c_context[i2c_num].spinlock)); return ESP_OK; } @@ -857,8 +854,8 @@ esp_err_t i2c_set_stop_timing(i2c_port_t i2c_num, int setup_time, int hold_time) ESP_RETURN_ON_FALSE((hold_time <= I2C_SCL_STOP_HOLD_TIME_V) && (hold_time > 0), ESP_ERR_INVALID_ARG, I2C_TAG, I2C_TIMING_VAL_ERR_STR); I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock)); - i2c_hal_set_stop_timing(&(i2c_context[i2c_num].hal), setup_time, hold_time); - i2c_hal_update_config(&(i2c_context[i2c_num].hal)); + i2c_ll_set_stop_timing(i2c_context[i2c_num].hal.dev, setup_time, hold_time); + i2c_ll_update(i2c_context[i2c_num].hal.dev); I2C_EXIT_CRITICAL(&(i2c_context[i2c_num].spinlock)); return ESP_OK; } @@ -867,7 +864,7 @@ esp_err_t i2c_get_stop_timing(i2c_port_t i2c_num, int *setup_time, int *hold_tim { ESP_RETURN_ON_FALSE(i2c_num < I2C_NUM_MAX && setup_time != NULL && hold_time != NULL, ESP_ERR_INVALID_ARG, I2C_TAG, I2C_NUM_ERROR_STR); I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock)); - i2c_hal_get_stop_timing(&(i2c_context[i2c_num].hal), setup_time, hold_time); + i2c_ll_get_stop_timing(i2c_context[i2c_num].hal.dev, setup_time, hold_time); I2C_EXIT_CRITICAL(&(i2c_context[i2c_num].spinlock)); return ESP_OK; } @@ -879,8 +876,8 @@ esp_err_t i2c_set_data_timing(i2c_port_t i2c_num, int sample_time, int hold_time ESP_RETURN_ON_FALSE((hold_time <= I2C_SDA_HOLD_TIME_V) && (hold_time > 0), ESP_ERR_INVALID_ARG, I2C_TAG, I2C_TIMING_VAL_ERR_STR); I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock)); - i2c_hal_set_sda_timing(&(i2c_context[i2c_num].hal), sample_time, hold_time); - i2c_hal_update_config(&(i2c_context[i2c_num].hal)); + i2c_ll_set_sda_timing(i2c_context[i2c_num].hal.dev, sample_time, hold_time); + i2c_ll_update(i2c_context[i2c_num].hal.dev); I2C_EXIT_CRITICAL(&(i2c_context[i2c_num].spinlock)); return ESP_OK; } @@ -889,7 +886,7 @@ esp_err_t i2c_get_data_timing(i2c_port_t i2c_num, int *sample_time, int *hold_ti { ESP_RETURN_ON_FALSE(i2c_num < I2C_NUM_MAX && sample_time != NULL && hold_time != NULL, ESP_ERR_INVALID_ARG, I2C_TAG, I2C_NUM_ERROR_STR); I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock)); - i2c_hal_get_sda_timing(&(i2c_context[i2c_num].hal), sample_time, hold_time); + i2c_ll_get_sda_timing(i2c_context[i2c_num].hal.dev, sample_time, hold_time); I2C_EXIT_CRITICAL(&(i2c_context[i2c_num].spinlock)); return ESP_OK; } @@ -900,7 +897,7 @@ esp_err_t i2c_set_timeout(i2c_port_t i2c_num, int timeout) ESP_RETURN_ON_FALSE((timeout <= I2C_LL_MAX_TIMEOUT) && (timeout > 0), ESP_ERR_INVALID_ARG, I2C_TAG, I2C_TIMING_VAL_ERR_STR); I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock)); - i2c_hal_set_tout(&(i2c_context[i2c_num].hal), timeout); + i2c_ll_set_tout(i2c_context[i2c_num].hal.dev, timeout); I2C_EXIT_CRITICAL(&(i2c_context[i2c_num].spinlock)); return ESP_OK; } @@ -908,7 +905,7 @@ esp_err_t i2c_set_timeout(i2c_port_t i2c_num, int timeout) esp_err_t i2c_get_timeout(i2c_port_t i2c_num, int *timeout) { ESP_RETURN_ON_FALSE(i2c_num < I2C_NUM_MAX && timeout != NULL, ESP_ERR_INVALID_ARG, I2C_TAG, I2C_NUM_ERROR_STR); - i2c_hal_get_tout(&(i2c_context[i2c_num].hal), timeout); + i2c_ll_get_tout(i2c_context[i2c_num].hal.dev, timeout); return ESP_OK; } @@ -1353,7 +1350,7 @@ static void IRAM_ATTR i2c_master_cmd_begin_static(i2c_port_t i2c_num, portBASE_T i2c_cmd_evt_t evt = { 0 }; if (p_i2c->cmd_link.head != NULL && p_i2c->status == I2C_STATUS_READ) { i2c_cmd_t *cmd = &p_i2c->cmd_link.head->cmd; - i2c_hal_read_rxfifo(&(i2c_context[i2c_num].hal), cmd->data + cmd->bytes_used, p_i2c->rx_cnt); + i2c_ll_read_rxfifo(i2c_context[i2c_num].hal.dev, cmd->data + cmd->bytes_used, p_i2c->rx_cnt); /* rx_cnt bytes have just been read, increment the number of bytes used from the buffer */ cmd->bytes_used += p_i2c->rx_cnt; @@ -1415,10 +1412,10 @@ static void IRAM_ATTR i2c_master_cmd_begin_static(i2c_port_t i2c_num, portBASE_T write_pr = (uint8_t*) &cmd->data_byte; } hw_cmd.byte_num = fifo_fill; - i2c_hal_write_txfifo(&(i2c_context[i2c_num].hal), write_pr, fifo_fill); - i2c_hal_write_cmd_reg(&(i2c_context[i2c_num].hal), hw_cmd, p_i2c->cmd_idx); - i2c_hal_write_cmd_reg(&(i2c_context[i2c_num].hal), hw_end_cmd, p_i2c->cmd_idx + 1); - i2c_hal_enable_master_tx_it(&(i2c_context[i2c_num].hal)); + i2c_ll_write_txfifo(i2c_context[i2c_num].hal.dev, write_pr, fifo_fill); + i2c_ll_write_cmd_reg(i2c_context[i2c_num].hal.dev, hw_cmd, p_i2c->cmd_idx); + i2c_ll_write_cmd_reg(i2c_context[i2c_num].hal.dev, hw_end_cmd, p_i2c->cmd_idx + 1); + i2c_ll_master_enable_tx_it(i2c_context[i2c_num].hal.dev); p_i2c->cmd_idx = 0; if (i2c_cmd_is_single_byte(cmd) || cmd->total_bytes == cmd->bytes_used) { p_i2c->cmd_link.head = p_i2c->cmd_link.head->next; @@ -1433,13 +1430,13 @@ static void IRAM_ATTR i2c_master_cmd_begin_static(i2c_port_t i2c_num, portBASE_T fifo_fill = MIN(remaining_bytes, SOC_I2C_FIFO_LEN); p_i2c->rx_cnt = fifo_fill; hw_cmd.byte_num = fifo_fill; - i2c_hal_write_cmd_reg(&(i2c_context[i2c_num].hal), hw_cmd, p_i2c->cmd_idx); - i2c_hal_write_cmd_reg(&(i2c_context[i2c_num].hal), hw_end_cmd, p_i2c->cmd_idx + 1); - i2c_hal_enable_master_rx_it(&(i2c_context[i2c_num].hal)); + i2c_ll_write_cmd_reg(i2c_context[i2c_num].hal.dev, hw_cmd, p_i2c->cmd_idx); + i2c_ll_write_cmd_reg(i2c_context[i2c_num].hal.dev, hw_end_cmd, p_i2c->cmd_idx + 1); + i2c_ll_master_enable_rx_it(i2c_context[i2c_num].hal.dev); p_i2c->status = I2C_STATUS_READ; break; } else { - i2c_hal_write_cmd_reg(&(i2c_context[i2c_num].hal), hw_cmd, p_i2c->cmd_idx); + i2c_ll_write_cmd_reg(i2c_context[i2c_num].hal.dev, hw_cmd, p_i2c->cmd_idx); } p_i2c->cmd_idx++; p_i2c->cmd_link.head = p_i2c->cmd_link.head->next; @@ -1448,8 +1445,8 @@ static void IRAM_ATTR i2c_master_cmd_begin_static(i2c_port_t i2c_num, portBASE_T break; } } - i2c_hal_update_config(&(i2c_context[i2c_num].hal)); - i2c_hal_trans_start(&(i2c_context[i2c_num].hal)); + i2c_ll_update(i2c_context[i2c_num].hal.dev); + i2c_ll_trans_start(i2c_context[i2c_num].hal.dev); return; } @@ -1503,7 +1500,7 @@ esp_err_t i2c_master_cmd_begin(i2c_port_t i2c_num, i2c_cmd_handle_t cmd_handle, #endif xQueueReset(p_i2c->cmd_evt_queue); if (p_i2c->status == I2C_STATUS_TIMEOUT - || i2c_hal_is_bus_busy(&(i2c_context[i2c_num].hal))) { + || i2c_ll_is_bus_busy(i2c_context[i2c_num].hal.dev)) { i2c_hw_fsm_reset(i2c_num); clear_bus_cnt[i2c_num] = 0; } @@ -1524,8 +1521,8 @@ esp_err_t i2c_master_cmd_begin(i2c_port_t i2c_num, i2c_cmd_handle_t cmd_handle, i2c_reset_rx_fifo(i2c_num); // These two interrupts some times can not be cleared when the FSM gets stuck. // so we disable them when these two interrupt occurs and re-enable them here. - i2c_hal_disable_intr_mask(&(i2c_context[i2c_num].hal), I2C_LL_INTR_MASK); - i2c_hal_clr_intsts_mask(&(i2c_context[i2c_num].hal), I2C_LL_INTR_MASK); + i2c_ll_disable_intr_mask(i2c_context[i2c_num].hal.dev, I2C_LL_INTR_MASK); + i2c_ll_clear_intr_mask(i2c_context[i2c_num].hal.dev, I2C_LL_INTR_MASK); //start send commands, at most 32 bytes one time, isr handler will process the remaining commands. i2c_master_cmd_begin_static(i2c_num, NULL); @@ -1606,7 +1603,7 @@ int i2c_slave_write_buffer(i2c_port_t i2c_num, const uint8_t *data, int size, Ti cnt = 0; } else { I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock)); - i2c_hal_enable_slave_tx_it(&(i2c_context[i2c_num].hal)); + i2c_ll_slave_enable_tx_it(i2c_context[i2c_num].hal.dev); I2C_EXIT_CRITICAL(&(i2c_context[i2c_num].spinlock)); cnt = size; } @@ -1630,7 +1627,7 @@ int i2c_slave_read_buffer(i2c_port_t i2c_num, uint8_t *data, size_t max_size, Ti TickType_t ticks_rem = ticks_to_wait; TickType_t ticks_end = xTaskGetTickCount() + ticks_to_wait; I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock)); - i2c_hal_enable_slave_rx_it(&(i2c_context[i2c_num].hal)); + i2c_ll_slave_enable_rx_it(i2c_context[i2c_num].hal.dev); I2C_EXIT_CRITICAL(&(i2c_context[i2c_num].spinlock)); while (size_rem && ticks_rem <= ticks_to_wait) { uint8_t *pdata = (uint8_t *) xRingbufferReceiveUpTo(p_i2c->rx_ring_buf, &size, ticks_to_wait, size_rem); diff --git a/components/driver/i2s/i2s_common.c b/components/driver/i2s/i2s_common.c index 4a3f8e75be..a985698adc 100644 --- a/components/driver/i2s/i2s_common.c +++ b/components/driver/i2s/i2s_common.c @@ -35,6 +35,7 @@ #include "esp_private/i2s_platform.h" #include "esp_private/periph_ctrl.h" +#include "esp_private/esp_clk.h" #include "driver/gpio.h" #include "driver/i2s_common.h" @@ -55,10 +56,10 @@ // If ISR handler is allowed to run whilst cache is disabled, // Make sure all the code and related variables used by the handler are in the SRAM #if CONFIG_I2S_ISR_IRAM_SAFE -#define I2S_INTR_ALLOC_FLAGS (ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_SHARED) +#define I2S_INTR_ALLOC_FLAGS (ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED) #define I2S_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT) #else -#define I2S_INTR_ALLOC_FLAGS (ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_SHARED) +#define I2S_INTR_ALLOC_FLAGS (ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED) #define I2S_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT #endif //CONFIG_I2S_ISR_IRAM_SAFE #define I2S_DMA_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA) @@ -242,7 +243,7 @@ static esp_err_t i2s_register_channel(i2s_controller_t *i2s_obj, i2s_dir_t dir, esp_err_t ret = ESP_OK; - i2s_chan_handle_t new_chan = (i2s_chan_handle_t)heap_caps_calloc(1, sizeof(struct i2s_channel_t), I2S_MEM_ALLOC_CAPS); + i2s_chan_handle_t new_chan = (i2s_chan_handle_t)heap_caps_calloc(1, sizeof(struct i2s_channel_obj_t), I2S_MEM_ALLOC_CAPS); ESP_RETURN_ON_FALSE(new_chan, ESP_ERR_NO_MEM, TAG, "No memory for new channel"); new_chan->mode = I2S_COMM_MODE_NONE; new_chan->role = I2S_ROLE_MASTER; // Set default role to master @@ -371,7 +372,7 @@ uint32_t i2s_get_buf_size(i2s_chan_handle_t handle, uint32_t data_bit_width, uin if (bufsize > I2S_DMA_BUFFER_MAX_SIZE) { uint32_t frame_num = I2S_DMA_BUFFER_MAX_SIZE / bytes_per_frame; bufsize = frame_num * bytes_per_frame; - ESP_LOGW(TAG, "dma frame num is out of dma buffer size, limited to %d", frame_num); + ESP_LOGW(TAG, "dma frame num is out of dma buffer size, limited to %"PRIu32, frame_num); } return bufsize; } @@ -436,7 +437,7 @@ esp_err_t i2s_alloc_dma_desc(i2s_chan_handle_t handle, uint32_t num, uint32_t bu if (handle->dir == I2S_DIR_RX) { i2s_ll_rx_set_eof_num(handle->controller->hal.dev, bufsize); } - ESP_LOGD(TAG, "DMA malloc info: dma_desc_num = %d, dma_desc_buf_size = dma_frame_num * slot_num * data_bit_width = %d", num, bufsize); + ESP_LOGD(TAG, "DMA malloc info: dma_desc_num = %"PRIu32", dma_desc_buf_size = dma_frame_num * slot_num * data_bit_width = %"PRIu32, num, bufsize); return ESP_OK; err: i2s_free_dma_desc(handle); @@ -444,7 +445,7 @@ err: } #if SOC_I2S_SUPPORTS_APLL -uint32_t i2s_set_get_apll_freq(uint32_t mclk_freq_hz) +static uint32_t i2s_set_get_apll_freq(uint32_t mclk_freq_hz) { /* Calculate the expected APLL */ int mclk_div = (int)((SOC_APLL_MIN_HZ / mclk_freq_hz) + 1); @@ -465,14 +466,33 @@ uint32_t i2s_set_get_apll_freq(uint32_t mclk_freq_hz) return 0; } if (ret == ESP_ERR_INVALID_STATE) { - ESP_LOGW(TAG, "APLL is occupied already, it is working at %d Hz while the expected frequency is %d Hz", real_freq, expt_freq); - ESP_LOGW(TAG, "Trying to work at %d Hz...", real_freq); + ESP_LOGW(TAG, "APLL is occupied already, it is working at %"PRIu32" Hz while the expected frequency is %"PRIu32" Hz", real_freq, expt_freq); + ESP_LOGW(TAG, "Trying to work at %"PRIu32" Hz...", real_freq); } - ESP_LOGD(TAG, "APLL expected frequency is %d Hz, real frequency is %d Hz", expt_freq, real_freq); + ESP_LOGD(TAG, "APLL expected frequency is %"PRIu32" Hz, real frequency is %"PRIu32" Hz", expt_freq, real_freq); return real_freq; } #endif +// [clk_tree] TODO: replace the following switch table by clk_tree API +uint32_t i2s_get_source_clk_freq(i2s_clock_src_t clk_src, uint32_t mclk_freq_hz) +{ + switch (clk_src) + { +#if SOC_I2S_SUPPORTS_APLL + case I2S_CLK_SRC_APLL: + return i2s_set_get_apll_freq(mclk_freq_hz); +#endif +#if SOC_I2S_SUPPORTS_XTAL + case I2S_CLK_SRC_XTAL: + (void)mclk_freq_hz; + return esp_clk_xtal_freq(); +#endif + default: // I2S_CLK_SRC_PLL_160M + return esp_clk_apb_freq() * 2; + } +} + #if SOC_GDMA_SUPPORTED static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data) { diff --git a/components/driver/i2s/i2s_pdm.c b/components/driver/i2s/i2s_pdm.c index a08d630f30..6863453d23 100644 --- a/components/driver/i2s/i2s_pdm.c +++ b/components/driver/i2s/i2s_pdm.c @@ -38,11 +38,7 @@ static esp_err_t i2s_pdm_tx_calculate_clock(i2s_chan_handle_t handle, const i2s_ clk_info->bclk = rate * I2S_LL_PDM_BCK_FACTOR * pdm_tx_clk->up_sample_fp / pdm_tx_clk->up_sample_fs; clk_info->bclk_div = 8; clk_info->mclk = clk_info->bclk * clk_info->bclk_div; -#if SOC_I2S_SUPPORTS_APLL - clk_info->sclk = (clk_cfg->clk_src == I2S_CLK_SRC_APLL) ? i2s_set_get_apll_freq(clk_info->mclk) : I2S_LL_BASE_CLK; -#else - clk_info->sclk = I2S_LL_BASE_CLK; -#endif + clk_info->sclk = i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk); clk_info->mclk_div = clk_info->sclk / clk_info->mclk; /* Check if the configuration is correct */ @@ -61,7 +57,7 @@ static esp_err_t i2s_pdm_tx_set_clock(i2s_chan_handle_t handle, const i2s_pdm_tx i2s_hal_clock_info_t clk_info; /* Calculate clock parameters */ ESP_RETURN_ON_ERROR(i2s_pdm_tx_calculate_clock(handle, clk_cfg, &clk_info), TAG, "clock calculate failed"); - ESP_LOGD(TAG, "Clock division info: [sclk] %d Hz [mdiv] %d [mclk] %d Hz [bdiv] %d [bclk] %d Hz", + ESP_LOGD(TAG, "Clock division info: [sclk] %"PRIu32" Hz [mdiv] %d [mclk] %"PRIu32" Hz [bdiv] %d [bclk] %"PRIu32" Hz", clk_info.sclk, clk_info.mclk_div, clk_info.mclk, clk_info.bclk_div, clk_info.bclk); portENTER_CRITICAL(&g_i2s.spinlock); @@ -326,11 +322,7 @@ static esp_err_t i2s_pdm_rx_calculate_clock(i2s_chan_handle_t handle, const i2s_ clk_info->bclk = rate * I2S_LL_PDM_BCK_FACTOR * (pdm_rx_clk->dn_sample_mode == I2S_PDM_DSR_16S ? 2 : 1); clk_info->bclk_div = 8; clk_info->mclk = clk_info->bclk * clk_info->bclk_div; -#if SOC_I2S_SUPPORTS_APLL - clk_info->sclk = (clk_cfg->clk_src == I2S_CLK_SRC_APLL) ? i2s_set_get_apll_freq(clk_info->mclk) : I2S_LL_BASE_CLK; -#else - clk_info->sclk = I2S_LL_BASE_CLK; -#endif + clk_info->sclk = i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk); clk_info->mclk_div = clk_info->sclk / clk_info->mclk; /* Check if the configuration is correct */ @@ -348,7 +340,7 @@ static esp_err_t i2s_pdm_rx_set_clock(i2s_chan_handle_t handle, const i2s_pdm_rx i2s_hal_clock_info_t clk_info; /* Calculate clock parameters */ ESP_RETURN_ON_ERROR(i2s_pdm_rx_calculate_clock(handle, clk_cfg, &clk_info), TAG, "clock calculate failed"); - ESP_LOGD(TAG, "Clock division info: [sclk] %d Hz [mdiv] %d [mclk] %d Hz [bdiv] %d [bclk] %d Hz", + ESP_LOGD(TAG, "Clock division info: [sclk] %"PRIu32" Hz [mdiv] %d [mclk] %"PRIu32" Hz [bdiv] %d [bclk] %"PRIu32" Hz", clk_info.sclk, clk_info.mclk_div, clk_info.mclk, clk_info.bclk_div, clk_info.bclk); portENTER_CRITICAL(&g_i2s.spinlock); diff --git a/components/driver/i2s/i2s_private.h b/components/driver/i2s/i2s_private.h index e615be0f1d..5c2369cdf0 100644 --- a/components/driver/i2s/i2s_private.h +++ b/components/driver/i2s/i2s_private.h @@ -68,7 +68,7 @@ typedef struct { int mclk; /*!< MCK out pin, shared by tx/rx*/ } i2s_controller_t; -struct i2s_channel_t { +struct i2s_channel_obj_t { /* Channel basic information */ i2s_controller_t *controller; /*!< Parent pointer to controller object */ i2s_comm_mode_t mode; /*!< i2s channel communication mode */ @@ -161,16 +161,15 @@ esp_err_t i2s_alloc_dma_desc(i2s_chan_handle_t handle, uint32_t num, uint32_t bu */ uint32_t i2s_get_buf_size(i2s_chan_handle_t handle, uint32_t data_bit_width, uint32_t dma_frame_num); -#if SOC_I2S_SUPPORTS_APLL /** - * @brief Set mclk frequency and get the actuall APLL frequency + * @brief Get the frequency of the source clock * + * @param clk_src clock source * @param mclk_freq_hz Expected mclk frequenct in Hz * @return - * - Actuall APLL frequency + * - Actual source clock frequency */ -uint32_t i2s_set_get_apll_freq(uint32_t mclk_freq_hz); -#endif +uint32_t i2s_get_source_clk_freq(i2s_clock_src_t clk_src, uint32_t mclk_freq_hz); /** * @brief Check gpio validity and attach to corresponding signal diff --git a/components/driver/i2s/i2s_std.c b/components/driver/i2s/i2s_std.c index 5b9ba1e91e..cdfb85b51f 100644 --- a/components/driver/i2s/i2s_std.c +++ b/components/driver/i2s/i2s_std.c @@ -45,11 +45,7 @@ static esp_err_t i2s_std_calculate_clock(i2s_chan_handle_t handle, const i2s_std clk_info->bclk = rate * handle->total_slot * slot_bits; clk_info->mclk = clk_info->bclk * clk_info->bclk_div; } -#if SOC_I2S_SUPPORTS_APLL - clk_info->sclk = (clk_cfg->clk_src == I2S_CLK_SRC_APLL) ? i2s_set_get_apll_freq(clk_info->mclk) : I2S_LL_BASE_CLK; -#else - clk_info->sclk = I2S_LL_BASE_CLK; -#endif + clk_info->sclk = i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk); clk_info->mclk_div = clk_info->sclk / clk_info->mclk; /* Check if the configuration is correct */ @@ -69,7 +65,7 @@ static esp_err_t i2s_std_set_clock(i2s_chan_handle_t handle, const i2s_std_clk_c i2s_hal_clock_info_t clk_info; /* Calculate clock parameters */ ESP_RETURN_ON_ERROR(i2s_std_calculate_clock(handle, clk_cfg, &clk_info), TAG, "clock calculate failed"); - ESP_LOGD(TAG, "Clock division info: [sclk] %d Hz [mdiv] %d [mclk] %d Hz [bdiv] %d [bclk] %d Hz", + ESP_LOGD(TAG, "Clock division info: [sclk] %"PRIu32" Hz [mdiv] %d [mclk] %"PRIu32" Hz [bdiv] %d [bclk] %"PRIu32" Hz", clk_info.sclk, clk_info.mclk_div, clk_info.mclk, clk_info.bclk_div, clk_info.bclk); portENTER_CRITICAL(&g_i2s.spinlock); diff --git a/components/driver/i2s/i2s_tdm.c b/components/driver/i2s/i2s_tdm.c index aaf39a6632..921d05804f 100644 --- a/components/driver/i2s/i2s_tdm.c +++ b/components/driver/i2s/i2s_tdm.c @@ -45,21 +45,20 @@ static esp_err_t i2s_tdm_calculate_clock(i2s_chan_handle_t handle, const i2s_tdm clk_info->mclk *= 2; clk_info->bclk_div = clk_info->mclk / clk_info->bclk; if (clk_info->bclk_div <= 2) { - ESP_LOGW(TAG, "the current mclk multiple is too small, adjust the mclk multiple to %d", clk_info->mclk / rate); + ESP_LOGW(TAG, "the current mclk multiple is too small, adjust the mclk multiple to %"PRIu32, clk_info->mclk / rate); } } while (clk_info->bclk_div <= 2); } else { - /* For slave mode, mclk >= bclk * 8, so fix bclk_div to 2 first */ - clk_info->bclk_div = 8; + if (clk_cfg->bclk_div < 8) { + ESP_LOGW(TAG, "the current bclk division is too small, adjust the bclk division to 8"); + clk_info->bclk_div = 8; + } else { + clk_info->bclk_div = clk_cfg->bclk_div; + } clk_info->bclk = rate * handle->total_slot * slot_bits; clk_info->mclk = clk_info->bclk * clk_info->bclk_div; } - -#if SOC_I2S_SUPPORTS_APLL - clk_info->sclk = clk_cfg->clk_src == I2S_CLK_SRC_APLL ? i2s_set_get_apll_freq(clk_info->mclk) : I2S_LL_BASE_CLK; -#else - clk_info->sclk = I2S_LL_BASE_CLK; -#endif + clk_info->sclk = i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk); clk_info->mclk_div = clk_info->sclk / clk_info->mclk; /* Check if the configuration is correct */ @@ -76,7 +75,7 @@ static esp_err_t i2s_tdm_set_clock(i2s_chan_handle_t handle, const i2s_tdm_clk_c i2s_hal_clock_info_t clk_info; /* Calculate clock parameters */ ESP_RETURN_ON_ERROR(i2s_tdm_calculate_clock(handle, clk_cfg, &clk_info), TAG, "clock calculate failed"); - ESP_LOGD(TAG, "Clock division info: [sclk] %d Hz [mdiv] %d [mclk] %d Hz [bdiv] %d [bclk] %d Hz", + ESP_LOGD(TAG, "Clock division info: [sclk] %"PRIu32" Hz [mdiv] %d [mclk] %"PRIu32" Hz [bdiv] %d [bclk] %"PRIu32" Hz", clk_info.sclk, clk_info.mclk_div, clk_info.mclk, clk_info.bclk_div, clk_info.bclk); portENTER_CRITICAL(&g_i2s.spinlock); diff --git a/components/driver/include/driver/gpio.h b/components/driver/include/driver/gpio.h index d91a56497e..ad9083e2e2 100644 --- a/components/driver/include/driver/gpio.h +++ b/components/driver/include/driver/gpio.h @@ -25,10 +25,30 @@ extern "C" { /// Check whether it can be a valid GPIO number of output mode #define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((gpio_num >= 0) && \ (((1ULL << (gpio_num)) & SOC_GPIO_VALID_OUTPUT_GPIO_MASK) != 0)) - +/// Check whether it can be a valid digital I/O pad +#define GPIO_IS_VALID_DIGITAL_IO_PAD(gpio_num) ((gpio_num >= 0) && \ + (((1ULL << (gpio_num)) & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK) != 0)) typedef intr_handle_t gpio_isr_handle_t; +/** + * @brief GPIO interrupt handler + * + * @param arg User registered data + */ +typedef void (*gpio_isr_t)(void *arg); + +/** + * @brief Configuration parameters of GPIO pad for gpio_config function + */ +typedef struct { + uint64_t pin_bit_mask; /*!< GPIO pin: set with bit mask, each bit maps to a GPIO */ + gpio_mode_t mode; /*!< GPIO mode: set input/output mode */ + gpio_pullup_t pull_up_en; /*!< GPIO pull-up */ + gpio_pulldown_t pull_down_en; /*!< GPIO pull-down */ + gpio_int_type_t intr_type; /*!< GPIO interrupt type */ +} gpio_config_t; + /** * @brief GPIO common configuration * @@ -75,8 +95,7 @@ esp_err_t gpio_set_intr_type(gpio_num_t gpio_num, gpio_int_type_t intr_type); * @note ESP32: Please do not use the interrupt of GPIO36 and GPIO39 when using ADC or Wi-Fi and Bluetooth with sleep mode enabled. * Please refer to the comments of `adc1_get_raw`. * Please refer to Section 3.11 of ESP32 ECO and Workarounds for Bugs for the description of this issue. - * As a workaround, call adc_power_acquire() in the app. This will result in higher power consumption (by ~1mA), - * but will remove the glitches on GPIO36 and GPIO39. + * * @param gpio_num GPIO number. If you want to enable an interrupt on e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); * @@ -255,7 +274,7 @@ esp_err_t gpio_pulldown_en(gpio_num_t gpio_num); esp_err_t gpio_pulldown_dis(gpio_num_t gpio_num); /** - * @brief Install the driver's GPIO ISR handler service, which allows per-pin GPIO interrupt handlers. + * @brief Install the GPIO driver's ETS_GPIO_INTR_SOURCE ISR handler service, which allows per-pin GPIO interrupt handlers. * * This function is incompatible with gpio_isr_register() - if that function is used, a single global ISR is registered for all GPIO interrupts. If this function is used, the ISR service provides a global GPIO ISR and individual pin handlers are registered via the gpio_isr_handler_add() function. * diff --git a/components/driver/include/driver/gptimer.h b/components/driver/include/driver/gptimer.h index e6fe50420d..e68273443f 100644 --- a/components/driver/include/driver/gptimer.h +++ b/components/driver/include/driver/gptimer.h @@ -31,9 +31,9 @@ typedef struct { /** * @brief Timer alarm callback prototype * - * @param[in] timer Timer handle created by `gptimer_new_timer()` + * @param[in] timer Timer handle created by `gptimer_new_timer` * @param[in] edata Alarm event data, fed by driver - * @param[in] user_ctx User data, passed from `gptimer_register_event_callbacks()` + * @param[in] user_ctx User data, passed from `gptimer_register_event_callbacks` * @return Whether a high priority task has been waken up by this function */ typedef bool (*gptimer_alarm_cb_t) (gptimer_handle_t timer, const gptimer_alarm_event_data_t *edata, void *user_ctx); @@ -91,9 +91,9 @@ esp_err_t gptimer_new_timer(const gptimer_config_t *config, gptimer_handle_t *re * @brief Delete the GPTimer handle * * @note A timer can't be in the enable state when this function is invoked. - * See also `gptimer_disable()` for how to disable a timer. + * See also `gptimer_disable` for how to disable a timer. * - * @param[in] timer Timer handle created by `gptimer_new_timer()` + * @param[in] timer Timer handle created by `gptimer_new_timer` * @return * - ESP_OK: Delete GPTimer successfully * - ESP_ERR_INVALID_ARG: Delete GPTimer failed because of invalid argument @@ -109,7 +109,7 @@ esp_err_t gptimer_del_timer(gptimer_handle_t timer); * @note This function is allowed to run within ISR context * @note This function is allowed to be executed when Cache is disabled, by enabling `CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM` * - * @param[in] timer Timer handle created by `gptimer_new_timer()` + * @param[in] timer Timer handle created by `gptimer_new_timer` * @param[in] value Count value to be set * @return * - ESP_OK: Set GPTimer raw count value successfully @@ -121,11 +121,12 @@ esp_err_t gptimer_set_raw_count(gptimer_handle_t timer, uint64_t value); /** * @brief Get GPTimer raw count value * + * @note This function will trigger a software capture event and then return the captured count value. * @note With the raw count value and the resolution set in the `gptimer_config_t`, you can convert the count value into seconds. * @note This function is allowed to run within ISR context * @note This function is allowed to be executed when Cache is disabled, by enabling `CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM` * - * @param[in] timer Timer handle created by `gptimer_new_timer()` + * @param[in] timer Timer handle created by `gptimer_new_timer` * @param[out] value Returned GPTimer count value * @return * - ESP_OK: Get GPTimer raw count value successfully @@ -138,9 +139,10 @@ esp_err_t gptimer_get_raw_count(gptimer_handle_t timer, uint64_t *value); * @brief Set callbacks for GPTimer * * @note User registered callbacks are expected to be runnable within ISR context - * @note This function should be called when the timer is in the init state (i.e. before calling `gptimer_enable()`) + * @note The first call to this function needs to be before the call to `gptimer_enable` + * @note User can deregister a previously registered callback by calling this function and setting the callback member in the `cbs` structure to NULL. * - * @param[in] timer Timer handle created by `gptimer_new_timer()` + * @param[in] timer Timer handle created by `gptimer_new_timer` * @param[in] cbs Group of callback functions * @param[in] user_data User data, which will be passed to callback functions directly * @return @@ -157,7 +159,7 @@ esp_err_t gptimer_register_event_callbacks(gptimer_handle_t timer, const gptimer * @note This function is allowed to run within ISR context, so that user can set new alarm action immediately in the ISR callback. * @note This function is allowed to be executed when Cache is disabled, by enabling `CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM` * - * @param[in] timer Timer handle created by `gptimer_new_timer()` + * @param[in] timer Timer handle created by `gptimer_new_timer` * @param[in] config Alarm configuration, especially, set config to NULL means disabling the alarm function * @return * - ESP_OK: Set alarm action for GPTimer successfully @@ -170,11 +172,11 @@ esp_err_t gptimer_set_alarm_action(gptimer_handle_t timer, const gptimer_alarm_c * @brief Enable GPTimer * * @note This function will transit the timer state from init to enable. - * @note This function will enable the interrupt service, if it's lazy installed in `gptimer_register_event_callbacks()`. + * @note This function will enable the interrupt service, if it's lazy installed in `gptimer_register_event_callbacks`. * @note This function will acquire a PM lock, if a specific source clock (e.g. APB) is selected in the `gptimer_config_t`, while `CONFIG_PM_ENABLE` is enabled. - * @note Enable a timer doesn't mean to start it. See also `gptimer_start()` for how to make the timer start counting. + * @note Enable a timer doesn't mean to start it. See also `gptimer_start` for how to make the timer start counting. * - * @param[in] timer Timer handle created by `gptimer_new_timer()` + * @param[in] timer Timer handle created by `gptimer_new_timer` * @return * - ESP_OK: Enable GPTimer successfully * - ESP_ERR_INVALID_ARG: Enable GPTimer failed because of invalid argument @@ -186,10 +188,10 @@ esp_err_t gptimer_enable(gptimer_handle_t timer); /** * @brief Disable GPTimer * - * @note This function will do the opposite work to the `gptimer_enable()` - * @note Disable a timer doesn't mean to stop it. See also `gptimer_stop()` for how to make the timer stop counting. + * @note This function will do the opposite work to the `gptimer_enable` + * @note Disable a timer doesn't mean to stop it. See also `gptimer_stop` for how to make the timer stop counting. * - * @param[in] timer Timer handle created by `gptimer_new_timer()` + * @param[in] timer Timer handle created by `gptimer_new_timer` * @return * - ESP_OK: Disable GPTimer successfully * - ESP_ERR_INVALID_ARG: Disable GPTimer failed because of invalid argument @@ -201,11 +203,11 @@ esp_err_t gptimer_disable(gptimer_handle_t timer); /** * @brief Start GPTimer (internal counter starts counting) * - * @note This function should be called when the timer is in the enable state (i.e. after calling `gptimer_enable()`) + * @note This function should be called when the timer is in the enable state (i.e. after calling `gptimer_enable`) * @note This function is allowed to run within ISR context * @note This function will be placed into IRAM if `CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM` is on, so that it's allowed to be executed when Cache is disabled * - * @param[in] timer Timer handle created by `gptimer_new_timer()` + * @param[in] timer Timer handle created by `gptimer_new_timer` * @return * - ESP_OK: Start GPTimer successfully * - ESP_ERR_INVALID_ARG: Start GPTimer failed because of invalid argument @@ -217,11 +219,11 @@ esp_err_t gptimer_start(gptimer_handle_t timer); /** * @brief Stop GPTimer (internal counter stops counting) * - * @note This function should be called when the timer is in the enable state (i.e. after calling `gptimer_enable()`) + * @note This function should be called when the timer is in the enable state (i.e. after calling `gptimer_enable`) * @note This function is allowed to run within ISR context * @note This function will be placed into IRAM if `CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM` is on, so that it's allowed to be executed when Cache is disabled * - * @param[in] timer Timer handle created by `gptimer_new_timer()` + * @param[in] timer Timer handle created by `gptimer_new_timer` * @return * - ESP_OK: Stop GPTimer successfully * - ESP_ERR_INVALID_ARG: Stop GPTimer failed because of invalid argument diff --git a/components/driver/include/driver/i2c.h b/components/driver/include/driver/i2c.h index e8da6df2de..6ce0885c21 100644 --- a/components/driver/include/driver/i2c.h +++ b/components/driver/include/driver/i2c.h @@ -24,12 +24,6 @@ extern "C" { #define I2C_APB_CLK_FREQ APB_CLK_FREQ /*!< I2C source clock is APB clock, 80MHz */ -#define I2C_NUM_MAX (SOC_I2C_NUM) /*!< I2C port max */ -#define I2C_NUM_0 (0) /*!< I2C port 0 */ -#if SOC_I2C_NUM >= 2 -#define I2C_NUM_1 (1) /*!< I2C port 1 */ -#endif - // I2C clk flags for users to use, can be expanded in the future. #define I2C_SCLK_SRC_FLAG_FOR_NOMAL (0) /*!< Any one clock source that is available for the specified frequency may be choosen*/ #define I2C_SCLK_SRC_FLAG_AWARE_DFS (1 << 0) /*!< For REF tick clock, it won't change with APB.*/ diff --git a/components/driver/include/driver/i2s_tdm.h b/components/driver/include/driver/i2s_tdm.h index 9a7db55478..00bc448f5f 100644 --- a/components/driver/include/driver/i2s_tdm.h +++ b/components/driver/include/driver/i2s_tdm.h @@ -118,6 +118,7 @@ extern "C" { .sample_rate_hz = rate, \ .clk_src = I2S_CLK_SRC_DEFAULT, \ .mclk_multiple = I2S_MCLK_MULTIPLE_256, \ + .bclk_div = 8, \ } /** @@ -150,7 +151,8 @@ typedef struct { /* General fields */ uint32_t sample_rate_hz; /*!< I2S sample rate */ i2s_clock_src_t clk_src; /*!< Choose clock source */ - i2s_mclk_multiple_t mclk_multiple; /*!< The multiple of mclk to the sample rate */ + i2s_mclk_multiple_t mclk_multiple; /*!< The multiple of mclk to the sample rate, only take effect for master role */ + uint32_t bclk_div; /*!< The division from mclk to bclk, only take effect for slave role, it shouldn't be smaller than 8. Increase this field when data sent by slave lag behind */ } i2s_tdm_clk_config_t; /** diff --git a/components/driver/include/driver/i2s_types.h b/components/driver/include/driver/i2s_types.h index 84cd39241b..3cd4ffa633 100644 --- a/components/driver/include/driver/i2s_types.h +++ b/components/driver/include/driver/i2s_types.h @@ -63,7 +63,7 @@ typedef struct { */ } i2s_event_data_t; -typedef struct i2s_channel_t *i2s_chan_handle_t; /*!< i2s channel handle, the control unit of the i2s driver*/ +typedef struct i2s_channel_obj_t *i2s_chan_handle_t; /*!< i2s channel object handle, the control unit of the i2s driver*/ /** * @brief I2S event callback diff --git a/components/driver/include/driver/mcpwm_cap.h b/components/driver/include/driver/mcpwm_cap.h index 54aa3db59b..d40ef2fd1a 100644 --- a/components/driver/include/driver/mcpwm_cap.h +++ b/components/driver/include/driver/mcpwm_cap.h @@ -134,6 +134,8 @@ typedef struct { /** * @brief Create MCPWM capture channel * + * @note The created capture channel won't be enabled until calling `mcpwm_capture_channel_enable` + * * @param[in] cap_timer MCPWM capture timer, allocated by `mcpwm_new_capture_timer()`, will be connected to the new capture channel * @param[in] config MCPWM capture channel configuration * @param[out] ret_cap_channel Returned MCPWM capture channel @@ -157,6 +159,33 @@ esp_err_t mcpwm_new_capture_channel(mcpwm_cap_timer_handle_t cap_timer, const mc */ esp_err_t mcpwm_del_capture_channel(mcpwm_cap_channel_handle_t cap_channel); +/** + * @brief Enable MCPWM capture channel + * + * @note This function will transit the channel state from init to enable. + * @note This function will enable the interrupt service, if it's lazy installed in `mcpwm_capture_channel_register_event_callbacks()`. + * + * @param[in] cap_channel MCPWM capture channel handle, allocated by `mcpwm_new_capture_channel()` + * @return + * - ESP_OK: Enable MCPWM capture channel successfully + * - ESP_ERR_INVALID_ARG: Enable MCPWM capture channel failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Enable MCPWM capture channel failed because the channel is already enabled + * - ESP_FAIL: Enable MCPWM capture channel failed because of other error + */ +esp_err_t mcpwm_capture_channel_enable(mcpwm_cap_channel_handle_t cap_channel); + +/** + * @brief Disable MCPWM capture channel + * + * @param[in] cap_channel MCPWM capture channel handle, allocated by `mcpwm_new_capture_channel()` + * @return + * - ESP_OK: Disable MCPWM capture channel successfully + * - ESP_ERR_INVALID_ARG: Disable MCPWM capture channel failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Disable MCPWM capture channel failed because the channel is not enabled yet + * - ESP_FAIL: Disable MCPWM capture channel failed because of other error + */ +esp_err_t mcpwm_capture_channel_disable(mcpwm_cap_channel_handle_t cap_channel); + /** * @brief Group of supported MCPWM capture event callbacks * @note The callbacks are all running under ISR environment @@ -168,12 +197,16 @@ typedef struct { /** * @brief Set event callbacks for MCPWM capture channel * + * @note The first call to this function needs to be before the call to `mcpwm_capture_channel_enable` + * @note User can deregister a previously registered callback by calling this function and setting the callback member in the `cbs` structure to NULL. + * * @param[in] cap_channel MCPWM capture channel handle, allocated by `mcpwm_new_capture_channel()` * @param[in] cbs Group of callback functions * @param[in] user_data User data, which will be passed to callback functions directly * @return * - ESP_OK: Set event callbacks successfully * - ESP_ERR_INVALID_ARG: Set event callbacks failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Set event callbacks failed because the channel is not in init state * - ESP_FAIL: Set event callbacks failed because of other error */ esp_err_t mcpwm_capture_channel_register_event_callbacks(mcpwm_cap_channel_handle_t cap_channel, const mcpwm_capture_event_callbacks_t *cbs, void *user_data); @@ -185,6 +218,7 @@ esp_err_t mcpwm_capture_channel_register_event_callbacks(mcpwm_cap_channel_handl * @return * - ESP_OK: Trigger software catch successfully * - ESP_ERR_INVALID_ARG: Trigger software catch failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Trigger software catch failed because the channel is not enabled yet * - ESP_FAIL: Trigger software catch failed because of other error */ esp_err_t mcpwm_capture_channel_trigger_soft_catch(mcpwm_cap_channel_handle_t cap_channel); diff --git a/components/driver/include/driver/mcpwm_cmpr.h b/components/driver/include/driver/mcpwm_cmpr.h index d539f8a220..8ebae75736 100644 --- a/components/driver/include/driver/mcpwm_cmpr.h +++ b/components/driver/include/driver/mcpwm_cmpr.h @@ -63,6 +63,8 @@ typedef struct { /** * @brief Set event callbacks for MCPWM comparator * + * @note User can deregister a previously registered callback by calling this function and setting the callback member in the `cbs` structure to NULL. + * * @param[in] cmpr MCPWM comparator handle, allocated by `mcpwm_new_comparator()` * @param[in] cbs Group of callback functions * @param[in] user_data User data, which will be passed to callback functions directly diff --git a/components/driver/include/driver/mcpwm_fault.h b/components/driver/include/driver/mcpwm_fault.h index ddc635c679..e9833c4996 100644 --- a/components/driver/include/driver/mcpwm_fault.h +++ b/components/driver/include/driver/mcpwm_fault.h @@ -97,6 +97,8 @@ typedef struct { /** * @brief Set event callbacks for MCPWM fault * + * @note User can deregister a previously registered callback by calling this function and setting the callback member in the `cbs` structure to NULL. + * * @param[in] fault MCPWM GPIO fault handle, allocated by `mcpwm_new_gpio_fault()` * @param[in] cbs Group of callback functions * @param[in] user_data User data, which will be passed to callback functions directly diff --git a/components/driver/include/driver/mcpwm_oper.h b/components/driver/include/driver/mcpwm_oper.h index 5f89f806fc..75a531f2c3 100644 --- a/components/driver/include/driver/mcpwm_oper.h +++ b/components/driver/include/driver/mcpwm_oper.h @@ -82,14 +82,14 @@ typedef struct { /** * @brief Set brake method for MCPWM operator * - * @param[in] operator MCPWM operator, allocated by `mcpwm_new_operator()` + * @param[in] oper MCPWM operator, allocated by `mcpwm_new_operator()` * @param[in] config MCPWM brake configuration * @return * - ESP_OK: Set trip for operator successfully * - ESP_ERR_INVALID_ARG: Set trip for operator failed because of invalid argument * - ESP_FAIL: Set trip for operator failed because of other error */ -esp_err_t mcpwm_operator_set_brake_on_fault(mcpwm_oper_handle_t operator, const mcpwm_brake_config_t *config); +esp_err_t mcpwm_operator_set_brake_on_fault(mcpwm_oper_handle_t oper, const mcpwm_brake_config_t *config); /** * @brief Try to make the operator recover from fault @@ -97,7 +97,7 @@ esp_err_t mcpwm_operator_set_brake_on_fault(mcpwm_oper_handle_t operator, const * @note To recover from fault or escape from trip, you make sure the fault signal has dissappeared already. * Otherwise the recovery can't succeed. * - * @param[in] operator MCPWM operator, allocated by `mcpwm_new_operator()` + * @param[in] oper MCPWM operator, allocated by `mcpwm_new_operator()` * @param[in] fault MCPWM fault handle * @return * - ESP_OK: Recover from fault successfully @@ -105,7 +105,7 @@ esp_err_t mcpwm_operator_set_brake_on_fault(mcpwm_oper_handle_t operator, const * - ESP_ERR_INVALID_STATE: Recover from fault failed because the fault source is still active * - ESP_FAIL: Recover from fault failed because of other error */ -esp_err_t mcpwm_operator_recover_from_fault(mcpwm_oper_handle_t operator, mcpwm_fault_handle_t fault); +esp_err_t mcpwm_operator_recover_from_fault(mcpwm_oper_handle_t oper, mcpwm_fault_handle_t fault); /** * @brief Group of supported MCPWM operator event callbacks @@ -119,6 +119,8 @@ typedef struct { /** * @brief Set event callbacks for MCPWM operator * + * @note User can deregister a previously registered callback by calling this function and setting the callback member in the `cbs` structure to NULL. + * * @param[in] oper MCPWM operator handle, allocated by `mcpwm_new_operator()` * @param[in] cbs Group of callback functions * @param[in] user_data User data, which will be passed to callback functions directly diff --git a/components/driver/include/driver/mcpwm_timer.h b/components/driver/include/driver/mcpwm_timer.h index 3bcec03ab5..1cb1d6d8cf 100644 --- a/components/driver/include/driver/mcpwm_timer.h +++ b/components/driver/include/driver/mcpwm_timer.h @@ -107,6 +107,9 @@ esp_err_t mcpwm_timer_start_stop(mcpwm_timer_handle_t timer, mcpwm_timer_start_s /** * @brief Set event callbacks for MCPWM timer * + * @note The first call to this function needs to be before the call to `mcpwm_timer_enable` + * @note User can deregister a previously registered callback by calling this function and setting the callback member in the `cbs` structure to NULL. + * * @param[in] timer MCPWM timer handle, allocated by `mcpwm_new_timer()` * @param[in] cbs Group of callback functions * @param[in] user_data User data, which will be passed to callback functions directly diff --git a/components/driver/include/driver/mcpwm_types.h b/components/driver/include/driver/mcpwm_types.h index d25cff5614..fcd736ae3e 100644 --- a/components/driver/include/driver/mcpwm_types.h +++ b/components/driver/include/driver/mcpwm_types.h @@ -81,12 +81,12 @@ typedef struct { /** * @brief MCPWM operator brake event callback function * - * @param[in] operator MCPWM operator handle + * @param[in] oper MCPWM operator handle * @param[in] edata MCPWM brake event data, fed by driver * @param[in] user_ctx User data, set in `mcpwm_operator_register_event_callbacks()` * @return Whether a high priority task has been waken up by this function */ -typedef bool (*mcpwm_brake_event_cb_t)(mcpwm_oper_handle_t operator, const mcpwm_brake_event_data_t *edata, void *user_ctx); +typedef bool (*mcpwm_brake_event_cb_t)(mcpwm_oper_handle_t oper, const mcpwm_brake_event_data_t *edata, void *user_ctx); /** * @brief MCPWM fault event data @@ -98,11 +98,11 @@ typedef struct { * @brief MCPWM fault event callback function * * @param fault MCPWM fault handle - * @param ev_data MCPWM fault event data, fed by driver + * @param edata MCPWM fault event data, fed by driver * @param user_ctx User data, set in `mcpwm_fault_register_event_callbacks()` * @return whether a task switch is needed after the callback returns */ -typedef bool (*mcpwm_fault_event_cb_t)(mcpwm_fault_handle_t fault, const mcpwm_fault_event_data_t *ev_data, void *user_ctx); +typedef bool (*mcpwm_fault_event_cb_t)(mcpwm_fault_handle_t fault, const mcpwm_fault_event_data_t *edata, void *user_ctx); /** * @brief MCPWM compare event data @@ -134,7 +134,7 @@ typedef struct { * @brief MCPWM capture event callback function * * @param cap_channel MCPWM capture channel handle - * @param ev_data MCPWM capture event data, fed by driver + * @param edata MCPWM capture event data, fed by driver * @param user_ctx User data, set in `mcpwm_capture_channel_register_event_callbacks()` * @return Whether a high priority task has been waken up by this function */ diff --git a/components/driver/include/driver/pulse_cnt.h b/components/driver/include/driver/pulse_cnt.h index ccaffead23..cef84b447f 100644 --- a/components/driver/include/driver/pulse_cnt.h +++ b/components/driver/include/driver/pulse_cnt.h @@ -233,7 +233,8 @@ esp_err_t pcnt_unit_get_count(pcnt_unit_handle_t unit, int *value); * @brief Set event callbacks for PCNT unit * * @note User registered callbacks are expected to be runnable within ISR context - * @note This function is only allowed to be called when the unit is in the init state (i.e. before calling `pcnt_unit_enable()`) + * @note The first call to this function needs to be before the call to `pcnt_unit_enable` + * @note User can deregister a previously registered callback by calling this function and setting the callback member in the `cbs` structure to NULL. * * @param[in] unit PCNT unit handle created by `pcnt_new_unit()` * @param[in] cbs Group of callback functions diff --git a/components/driver/include/driver/sdio_slave.h b/components/driver/include/driver/sdio_slave.h index f9ec3f9c72..6d05406bb7 100644 --- a/components/driver/include/driver/sdio_slave.h +++ b/components/driver/include/driver/sdio_slave.h @@ -48,6 +48,9 @@ typedef struct { the internal pull-ups are not sufficient for stable communication, please do connect external pull-ups on the bus. This is only for example and debug use. */ +#define SDIO_SLAVE_FLAG_DEFAULT_SPEED BIT(3) /**< Disable the highspeed support of the hardware. */ +#define SDIO_SLAVE_FLAG_HIGH_SPEED 0 /**< Enable the highspeed support of the hardware. This is the + default option. The host will see highspeed capability, but the mode actually used is determined by the host. */ } sdio_slave_config_t; /** Handle of a receive buffer, register a handle by calling ``sdio_slave_recv_register_buf``. Use the handle to load the buffer to the diff --git a/components/driver/include/driver/sdmmc_host.h b/components/driver/include/driver/sdmmc_host.h index cab4c82955..1a4beb892a 100644 --- a/components/driver/include/driver/sdmmc_host.h +++ b/components/driver/include/driver/sdmmc_host.h @@ -45,6 +45,7 @@ extern "C" { .io_int_enable = sdmmc_host_io_int_enable, \ .io_int_wait = sdmmc_host_io_int_wait, \ .command_timeout_ms = 0, \ + .get_real_freq = &sdmmc_host_get_real_freq \ } /** @@ -259,6 +260,23 @@ esp_err_t sdmmc_host_io_int_wait(int slot, TickType_t timeout_ticks); */ esp_err_t sdmmc_host_deinit(void); +/** + * @brief Provides a real frequency used for an SD card installed on specific slot + * of SD/MMC host controller + * + * This function calculates real working frequency given by current SD/MMC host + * controller setup for required slot: it reads associated host and card dividers + * from corresponding SDMMC registers, calculates respective frequency and stores + * the value into the 'real_freq_khz' parameter + * + * @param slot slot number (SDMMC_HOST_SLOT_0 or SDMMC_HOST_SLOT_1) + * @param[out] real_freq_khz output parameter for the result frequency (in kHz) + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG on real_freq_khz == NULL or invalid slot number used + */ +esp_err_t sdmmc_host_get_real_freq(int slot, int* real_freq_khz); + #ifdef __cplusplus } #endif diff --git a/components/driver/include/driver/sdmmc_types.h b/components/driver/include/driver/sdmmc_types.h index b53e85f762..8a38d792e3 100644 --- a/components/driver/include/driver/sdmmc_types.h +++ b/components/driver/include/driver/sdmmc_types.h @@ -183,6 +183,7 @@ typedef struct { esp_err_t (*io_int_enable)(int slot); /*!< Host function to enable SDIO interrupt line */ esp_err_t (*io_int_wait)(int slot, TickType_t timeout_ticks); /*!< Host function to wait for SDIO interrupt line to be active */ int command_timeout_ms; /*!< timeout, in milliseconds, of a single command. Set to 0 to use the default value. */ + esp_err_t (*get_real_freq)(int slot, int* real_freq); /*!< Host function to provide real working freq, based on SDMMC controller setup */ } sdmmc_host_t; /** @@ -202,6 +203,7 @@ typedef struct { sdmmc_ext_csd_t ext_csd; /*!< decoded EXT_CSD (Extended Card Specific Data) register value */ uint16_t rca; /*!< RCA (Relative Card Address) */ uint16_t max_freq_khz; /*!< Maximum frequency, in kHz, supported by the card */ + int real_freq_khz; /*!< Real working frequency, in kHz, configured on the host controller */ uint32_t is_mem : 1; /*!< Bit indicates if the card is a memory card */ uint32_t is_sdio : 1; /*!< Bit indicates if the card is an IO card */ uint32_t is_mmc : 1; /*!< Bit indicates if the card is MMC */ diff --git a/components/driver/include/driver/sdspi_host.h b/components/driver/include/driver/sdspi_host.h index 61f29811dd..6025b4f2e3 100644 --- a/components/driver/include/driver/sdspi_host.h +++ b/components/driver/include/driver/sdspi_host.h @@ -50,6 +50,7 @@ typedef int sdspi_dev_handle_t; .io_int_enable = &sdspi_host_io_int_enable, \ .io_int_wait = &sdspi_host_io_int_wait, \ .command_timeout_ms = 0, \ + .get_real_freq = &sdspi_host_get_real_freq \ } /** @@ -63,6 +64,7 @@ typedef struct { gpio_num_t gpio_int; ///< GPIO number of interrupt line (input) for SDIO card. } sdspi_device_config_t; +#define SDSPI_SLOT_NO_CS GPIO_NUM_NC ///< indicates that card select line is not used #define SDSPI_SLOT_NO_CD GPIO_NUM_NC ///< indicates that card detect line is not used #define SDSPI_SLOT_NO_WP GPIO_NUM_NC ///< indicates that write protect line is not used #define SDSPI_SLOT_NO_INT GPIO_NUM_NC ///< indicates that interrupt line is not used @@ -155,6 +157,18 @@ esp_err_t sdspi_host_do_transaction(sdspi_dev_handle_t handle, sdmmc_command_t * */ esp_err_t sdspi_host_set_card_clk(sdspi_dev_handle_t host, uint32_t freq_khz); +/** + * @brief Calculate working frequency for specific device + * + * @param handle SDSPI device handle + * @param[out] real_freq_khz output parameter to hold the calculated frequency (in kHz) + * + * @return + * - ESP_ERR_INVALID_ARG : ``handle`` is NULL or invalid or ``real_freq_khz`` parameter is NULL + * - ESP_OK : Success + */ +esp_err_t sdspi_host_get_real_freq(sdspi_dev_handle_t handle, int* real_freq_khz); + /** * @brief Release resources allocated using sdspi_host_init * diff --git a/components/driver/include/driver/spi_master.h b/components/driver/include/driver/spi_master.h index 3c599ae9e0..07d38d1625 100644 --- a/components/driver/include/driver/spi_master.h +++ b/components/driver/include/driver/spi_master.h @@ -43,7 +43,7 @@ extern "C" */ #define SPI_DEVICE_NO_DUMMY (1<<6) #define SPI_DEVICE_DDRCLK (1<<7) - +#define SPI_DEVICE_NO_RETURN_RESULT (1<<8) ///< Don't return the descriptor to the host on completion (use post_cb to notify instead) typedef struct spi_transaction_t spi_transaction_t; typedef void(*transaction_cb_t)(spi_transaction_t *trans); @@ -166,7 +166,8 @@ typedef struct spi_device_t *spi_device_handle_t; ///< Handle for a device on a * @param dev_config SPI interface protocol config for the device * @param handle Pointer to variable to hold the device handle * @return - * - ESP_ERR_INVALID_ARG if parameter is invalid + * - ESP_ERR_INVALID_ARG if parameter is invalid or configuration combination is not supported (e.g. + * `dev_config->post_cb` isn't set while flag `SPI_DEVICE_NO_RETURN_RESULT` is enabled) * - ESP_ERR_NOT_FOUND if host doesn't have any free CS slots * - ESP_ERR_NO_MEM if out of memory * - ESP_OK on success @@ -223,6 +224,7 @@ esp_err_t spi_device_queue_trans(spi_device_handle_t handle, spi_transaction_t * out. * @return * - ESP_ERR_INVALID_ARG if parameter is invalid + * - ESP_ERR_NOT_SUPPORTED if flag `SPI_DEVICE_NO_RETURN_RESULT` is set * - ESP_ERR_TIMEOUT if there was no completed transaction before ticks_to_wait expired * - ESP_OK on success */ @@ -331,6 +333,18 @@ esp_err_t spi_device_acquire_bus(spi_device_handle_t device, TickType_t wait); */ void spi_device_release_bus(spi_device_handle_t dev); +/** + * @brief Calculate working frequency for specific device + * + * @param handle SPI device handle + * @param[out] freq_khz output parameter to hold calculated frequency in kHz + * + * @return + * - ESP_ERR_INVALID_ARG : ``handle`` or ``freq_khz`` parameter is NULL + * - ESP_OK : Success + */ +esp_err_t spi_device_get_actual_freq(spi_device_handle_t handle, int* freq_khz); + /** * @brief Calculate the working frequency that is most close to desired frequency. * diff --git a/components/driver/include/driver/spi_slave.h b/components/driver/include/driver/spi_slave.h index 92fa600486..a0a1cd4c2f 100644 --- a/components/driver/include/driver/spi_slave.h +++ b/components/driver/include/driver/spi_slave.h @@ -23,7 +23,7 @@ extern "C" #define SPI_SLAVE_TXBIT_LSBFIRST (1<<0) ///< Transmit command/address/data LSB first instead of the default MSB first #define SPI_SLAVE_RXBIT_LSBFIRST (1<<1) ///< Receive data LSB first instead of the default MSB first #define SPI_SLAVE_BIT_LSBFIRST (SPI_SLAVE_TXBIT_LSBFIRST|SPI_SLAVE_RXBIT_LSBFIRST) ///< Transmit and receive LSB first - +#define SPI_SLAVE_NO_RETURN_RESULT (1<<2) ///< Don't return the descriptor to the host on completion (use `post_trans_cb` to notify instead) typedef struct spi_slave_transaction_t spi_slave_transaction_t; typedef void(*slave_transaction_cb_t)(spi_slave_transaction_t *trans); @@ -158,6 +158,7 @@ esp_err_t spi_slave_queue_trans(spi_host_device_t host, const spi_slave_transact * out. * @return * - ESP_ERR_INVALID_ARG if parameter is invalid + * - ESP_ERR_NOT_SUPPORTED if flag `SPI_SLAVE_NO_RETURN_RESULT` is set * - ESP_OK on success */ esp_err_t spi_slave_get_trans_result(spi_host_device_t host, spi_slave_transaction_t **trans_desc, TickType_t ticks_to_wait); diff --git a/components/driver/include/driver/uart.h b/components/driver/include/driver/uart.h index c2eada0bf4..b410d2917e 100644 --- a/components/driver/include/driver/uart.h +++ b/components/driver/include/driver/uart.h @@ -195,6 +195,18 @@ esp_err_t uart_set_parity(uart_port_t uart_num, uart_parity_t parity_mode); */ esp_err_t uart_get_parity(uart_port_t uart_num, uart_parity_t* parity_mode); +/** + * @brief Get the frequency of a clock source for the UART + * + * @param sclk Clock source + * @param[out] out_freq_hz Output of frequency, in Hz + * + * @return + * - ESP_ERR_INVALID_ARG: if the clock source is not supported + * - otherwise ESP_OK + */ +esp_err_t uart_get_sclk_freq(uart_sclk_t sclk, uint32_t* out_freq_hz); + /** * @brief Set UART baud rate. * diff --git a/components/driver/ledc.c b/components/driver/ledc.c index 27b5cea484..e62250c6e0 100644 --- a/components/driver/ledc.c +++ b/components/driver/ledc.c @@ -103,9 +103,9 @@ static bool ledc_slow_clk_calibrate(void) s_ledc_slow_clk_8M = periph_rtc_dig_clk8m_get_freq(); #if CONFIG_IDF_TARGET_ESP32H2 /* Workaround: Calibration cannot be done for CLK8M on H2, we just use its theoretic frequency */ - ESP_LOGD(LEDC_TAG, "Calibration cannot be performed, approximate CLK8M_CLK : %d Hz", s_ledc_slow_clk_8M); + ESP_LOGD(LEDC_TAG, "Calibration cannot be performed, approximate CLK8M_CLK : %"PRIu32" Hz", s_ledc_slow_clk_8M); #else - ESP_LOGD(LEDC_TAG, "Calibrate CLK8M_CLK : %d Hz", s_ledc_slow_clk_8M); + ESP_LOGD(LEDC_TAG, "Calibrate CLK8M_CLK : %"PRIu32" Hz", s_ledc_slow_clk_8M); #endif return true; } @@ -276,7 +276,6 @@ esp_err_t ledc_timer_rst(ledc_mode_t speed_mode, ledc_timer_t timer_sel) LEDC_CHECK(p_ledc_obj[speed_mode] != NULL, LEDC_NOT_INIT, ESP_ERR_INVALID_STATE); portENTER_CRITICAL(&ledc_spinlock); ledc_hal_timer_rst(&(p_ledc_obj[speed_mode]->ledc_hal), timer_sel); - ledc_ls_timer_update(speed_mode, timer_sel); portEXIT_CRITICAL(&ledc_spinlock); return ESP_OK; } @@ -288,7 +287,6 @@ esp_err_t ledc_timer_pause(ledc_mode_t speed_mode, ledc_timer_t timer_sel) LEDC_CHECK(p_ledc_obj[speed_mode] != NULL, LEDC_NOT_INIT, ESP_ERR_INVALID_STATE); portENTER_CRITICAL(&ledc_spinlock); ledc_hal_timer_pause(&(p_ledc_obj[speed_mode]->ledc_hal), timer_sel); - ledc_ls_timer_update(speed_mode, timer_sel); portEXIT_CRITICAL(&ledc_spinlock); return ESP_OK; } @@ -300,7 +298,6 @@ esp_err_t ledc_timer_resume(ledc_mode_t speed_mode, ledc_timer_t timer_sel) LEDC_CHECK(p_ledc_obj[speed_mode] != NULL, LEDC_NOT_INIT, ESP_ERR_INVALID_STATE); portENTER_CRITICAL(&ledc_spinlock); ledc_hal_timer_resume(&(p_ledc_obj[speed_mode]->ledc_hal), timer_sel); - ledc_ls_timer_update(speed_mode, timer_sel); portEXIT_CRITICAL(&ledc_spinlock); return ESP_OK; } @@ -548,7 +545,7 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n } /* The following debug message makes more sense for AUTO mode. */ - ESP_LOGD(LEDC_TAG, "Using clock source %d (in %s mode), divisor: 0x%x\n", + ESP_LOGD(LEDC_TAG, "Using clock source %d (in %s mode), divisor: 0x%"PRIx32, timer_clk_src, (speed_mode == LEDC_LOW_SPEED_MODE ? "slow" : "fast"), div_param); /* The following block configures the global clock. @@ -581,14 +578,10 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n /* The divisor is correct, we can write in the hardware. */ ledc_timer_set(speed_mode, timer_num, div_param, duty_resolution, timer_clk_src); - - /* Reset the timer. */ - ledc_timer_rst(speed_mode, timer_num); return ESP_OK; error: - ESP_LOGE(LEDC_TAG, "requested frequency and duty resolution can not be achieved, try reducing freq_hz or duty_resolution. div_param=%d", - (uint32_t ) div_param); + ESP_LOGE(LEDC_TAG, "requested frequency and duty resolution can not be achieved, try reducing freq_hz or duty_resolution. div_param=%"PRIu32, div_param); return ESP_FAIL; } @@ -603,11 +596,11 @@ esp_err_t ledc_timer_config(const ledc_timer_config_t *timer_conf) LEDC_ARG_CHECK(!((timer_conf->clk_cfg == LEDC_USE_RTC8M_CLK) && (speed_mode != LEDC_LOW_SPEED_MODE)), "Only low speed channel support RTC8M_CLK"); periph_module_enable(PERIPH_LEDC_MODULE); if (freq_hz == 0 || duty_resolution == 0 || duty_resolution >= LEDC_TIMER_BIT_MAX) { - ESP_LOGE(LEDC_TAG, "freq_hz=%u duty_resolution=%u", freq_hz, duty_resolution); + ESP_LOGE(LEDC_TAG, "freq_hz=%"PRIu32" duty_resolution=%"PRIu32, freq_hz, duty_resolution); return ESP_ERR_INVALID_ARG; } if (timer_num > LEDC_TIMER_3) { - ESP_LOGE(LEDC_TAG, "invalid timer #%u", timer_num); + ESP_LOGE(LEDC_TAG, "invalid timer #%"PRIu32, timer_num); return ESP_ERR_INVALID_ARG; } @@ -619,7 +612,12 @@ esp_err_t ledc_timer_config(const ledc_timer_config_t *timer_conf) ledc_hal_init(&(p_ledc_obj[speed_mode]->ledc_hal), speed_mode); } - return ledc_set_timer_div(speed_mode, timer_num, timer_conf->clk_cfg, freq_hz, duty_resolution); + esp_err_t ret = ledc_set_timer_div(speed_mode, timer_num, timer_conf->clk_cfg, freq_hz, duty_resolution); + if (ret == ESP_OK) { + /* Reset the timer. */ + ledc_timer_rst(speed_mode, timer_num); + } + return ret; } esp_err_t ledc_set_pin(int gpio_num, ledc_mode_t speed_mode, ledc_channel_t ledc_channel) @@ -673,9 +671,8 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf) portENTER_CRITICAL(&ledc_spinlock); ledc_enable_intr_type(speed_mode, ledc_channel, intr_type); portEXIT_CRITICAL(&ledc_spinlock); - ESP_LOGD(LEDC_TAG, "LEDC_PWM CHANNEL %1u|GPIO %02u|Duty %04u|Time %01u", - ledc_channel, gpio_num, duty, timer_select - ); + ESP_LOGD(LEDC_TAG, "LEDC_PWM CHANNEL %"PRIu32"|GPIO %02u|Duty %04"PRIu32"|Time %"PRIu32, + ledc_channel, gpio_num, duty, timer_select); /*set LEDC signal in gpio matrix*/ gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO); gpio_set_level(gpio_num, output_invert); @@ -1048,13 +1045,13 @@ static esp_err_t _ledc_set_fade_with_step(ledc_mode_t speed_mode, ledc_channel_t portENTER_CRITICAL(&ledc_spinlock); ledc_duty_config(speed_mode, channel, LEDC_VAL_NO_CHANGE, duty_cur, dir, step_num, cycle_num, scale); portEXIT_CRITICAL(&ledc_spinlock); - ESP_LOGD(LEDC_TAG, "cur duty: %d; target: %d, step: %d, cycle: %d; scale: %d; dir: %d\n", + ESP_LOGD(LEDC_TAG, "cur duty: %"PRIu32"; target: %"PRIu32", step: %d, cycle: %d; scale: %d; dir: %d\n", duty_cur, target_duty, step_num, cycle_num, scale, dir); } else { portENTER_CRITICAL(&ledc_spinlock); ledc_duty_config(speed_mode, channel, LEDC_VAL_NO_CHANGE, target_duty, dir, 0, 1, 0); portEXIT_CRITICAL(&ledc_spinlock); - ESP_LOGD(LEDC_TAG, "Set to target duty: %d", target_duty); + ESP_LOGD(LEDC_TAG, "Set to target duty: %"PRIu32, target_duty); } return ESP_OK; } diff --git a/components/driver/linker.lf b/components/driver/linker.lf index 36e884f64d..46980ee0c6 100644 --- a/components/driver/linker.lf +++ b/components/driver/linker.lf @@ -17,3 +17,5 @@ entries: gpio: gpio_intr_disable (noflash) if SDM_CTRL_FUNC_IN_IRAM = y: sdm: sdm_channel_set_duty (noflash) + if MCPWM_CTRL_FUNC_IN_IRAM = y: + mcpwm_cmpr: mcpwm_comparator_set_compare_value (noflash) diff --git a/components/driver/mcpwm/mcpwm_cap.c b/components/driver/mcpwm/mcpwm_cap.c index 94667a6f14..ef6e3b2c2a 100644 --- a/components/driver/mcpwm/mcpwm_cap.c +++ b/components/driver/mcpwm/mcpwm_cap.c @@ -112,7 +112,7 @@ esp_err_t mcpwm_new_capture_timer(const mcpwm_capture_timer_config_t *config, mc cap_timer->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; cap_timer->fsm = MCPWM_CAP_TIMER_FSM_INIT; *ret_cap_timer = cap_timer; - ESP_LOGD(TAG, "new capture timer at %p, in group (%d)", cap_timer, group_id); + ESP_LOGD(TAG, "new capture timer at %p, in group (%d), resolution %"PRIu32, cap_timer, group_id, cap_timer->resolution_hz); return ESP_OK; err: @@ -242,7 +242,6 @@ esp_err_t mcpwm_new_capture_channel(mcpwm_cap_timer_handle_t cap_timer, const mc mcpwm_hal_context_t *hal = &group->hal; int cap_chan_id = cap_chan->cap_chan_id; - mcpwm_ll_capture_enable_channel(hal->dev, cap_chan_id, true); // enable channel mcpwm_ll_capture_enable_negedge(hal->dev, cap_chan_id, config->flags.neg_edge); mcpwm_ll_capture_enable_posedge(hal->dev, cap_chan_id, config->flags.pos_edge); mcpwm_ll_invert_input(hal->dev, cap_chan_id, config->flags.invert_cap_signal); @@ -262,6 +261,7 @@ esp_err_t mcpwm_new_capture_channel(mcpwm_cap_timer_handle_t cap_timer, const mc } cap_chan->gpio_num = config->gpio_num; + cap_chan->fsm = MCPWM_CAP_CHAN_FSM_INIT; *ret_cap_channel = cap_chan; ESP_LOGD(TAG, "new capture channel (%d,%d) at %p", group->group_id, cap_chan_id, cap_chan); return ESP_OK; @@ -275,6 +275,7 @@ err: esp_err_t mcpwm_del_capture_channel(mcpwm_cap_channel_handle_t cap_channel) { ESP_RETURN_ON_FALSE(cap_channel, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + ESP_RETURN_ON_FALSE(cap_channel->fsm == MCPWM_CAP_CHAN_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "channel not in init state"); mcpwm_cap_timer_t *cap_timer = cap_channel->cap_timer; mcpwm_group_t *group = cap_timer->group; mcpwm_hal_context_t *hal = &group->hal; @@ -290,14 +291,46 @@ esp_err_t mcpwm_del_capture_channel(mcpwm_cap_channel_handle_t cap_channel) mcpwm_ll_intr_clear_status(hal->dev, MCPWM_LL_EVENT_CAPTURE(cap_chan_id)); portEXIT_CRITICAL(&group->spinlock); - // disable capture channel - mcpwm_ll_capture_enable_channel(group->hal.dev, cap_channel->cap_chan_id, false); - // recycle memory resource ESP_RETURN_ON_ERROR(mcpwm_capture_channel_destory(cap_channel), TAG, "destory capture channel failed"); return ESP_OK; } +esp_err_t mcpwm_capture_channel_enable(mcpwm_cap_channel_handle_t cap_channel) +{ + ESP_RETURN_ON_FALSE(cap_channel, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + ESP_RETURN_ON_FALSE(cap_channel->fsm == MCPWM_CAP_CHAN_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "channel not in init state"); + mcpwm_hal_context_t *hal = &cap_channel->cap_timer->group->hal; + + // enable interrupt service + if (cap_channel->intr) { + ESP_RETURN_ON_ERROR(esp_intr_enable(cap_channel->intr), TAG, "enable interrupt service failed"); + } + // enable channel + mcpwm_ll_capture_enable_channel(hal->dev, cap_channel->cap_chan_id, true); + + cap_channel->fsm = MCPWM_CAP_CHAN_FSM_ENABLE; + return ESP_OK; +} + +esp_err_t mcpwm_capture_channel_disable(mcpwm_cap_channel_handle_t cap_channel) +{ + ESP_RETURN_ON_FALSE(cap_channel, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + ESP_RETURN_ON_FALSE(cap_channel->fsm == MCPWM_CAP_CHAN_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "channel not in enable state"); + mcpwm_hal_context_t *hal = &cap_channel->cap_timer->group->hal; + + // disable channel + mcpwm_ll_capture_enable_channel(hal->dev, cap_channel->cap_chan_id, false); + + // disable interrupt service + if (cap_channel->intr) { + ESP_RETURN_ON_ERROR(esp_intr_disable(cap_channel->intr), TAG, "disable interrupt service failed"); + } + + cap_channel->fsm = MCPWM_CAP_CHAN_FSM_INIT; + return ESP_OK; +} + esp_err_t mcpwm_capture_channel_register_event_callbacks(mcpwm_cap_channel_handle_t cap_channel, const mcpwm_capture_event_callbacks_t *cbs, void *user_data) { ESP_RETURN_ON_FALSE(cap_channel && cbs, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); @@ -317,8 +350,8 @@ esp_err_t mcpwm_capture_channel_register_event_callbacks(mcpwm_cap_channel_handl // lazy install interrupt service if (!cap_channel->intr) { - // we want the interrupt servie to be enabled after allocation successfully - int isr_flags = MCPWM_INTR_ALLOC_FLAG & ~ ESP_INTR_FLAG_INTRDISABLED; + ESP_RETURN_ON_FALSE(cap_channel->fsm == MCPWM_CAP_CHAN_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "channel not in init state"); + int isr_flags = MCPWM_INTR_ALLOC_FLAG; ESP_RETURN_ON_ERROR(esp_intr_alloc_intrstatus(mcpwm_periph_signals.groups[group_id].irq_id, isr_flags, (uint32_t)mcpwm_ll_intr_get_status_reg(hal->dev), MCPWM_LL_EVENT_CAPTURE(cap_chan_id), mcpwm_capture_default_isr, cap_channel, &cap_channel->intr), TAG, "install interrupt service for cap channel failed"); @@ -337,6 +370,7 @@ esp_err_t mcpwm_capture_channel_register_event_callbacks(mcpwm_cap_channel_handl esp_err_t mcpwm_capture_channel_trigger_soft_catch(mcpwm_cap_channel_handle_t cap_channel) { ESP_RETURN_ON_FALSE(cap_channel, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + ESP_RETURN_ON_FALSE(cap_channel->fsm == MCPWM_CAP_CHAN_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "channel not enabled yet"); mcpwm_cap_timer_t *cap_timer = cap_channel->cap_timer; mcpwm_group_t *group = cap_timer->group; diff --git a/components/driver/mcpwm/mcpwm_cmpr.c b/components/driver/mcpwm/mcpwm_cmpr.c index c0f9e82aad..455198699f 100644 --- a/components/driver/mcpwm/mcpwm_cmpr.c +++ b/components/driver/mcpwm/mcpwm_cmpr.c @@ -44,13 +44,13 @@ static esp_err_t mcpwm_comparator_register_to_operator(mcpwm_cmpr_t *cmpr, mcpwm ESP_RETURN_ON_FALSE(cmpr_id >= 0, ESP_ERR_NOT_FOUND, TAG, "no free comparator in operator (%d,%d)", oper->group->group_id, oper->oper_id); cmpr->cmpr_id = cmpr_id; - cmpr->operator = oper; + cmpr->oper = oper; return ESP_OK; } static void mcpwm_comparator_unregister_from_operator(mcpwm_cmpr_t *cmpr) { - mcpwm_oper_t *oper = cmpr->operator; + mcpwm_oper_t *oper = cmpr->oper; int cmpr_id = cmpr->cmpr_id; portENTER_CRITICAL(&oper->spinlock); @@ -63,7 +63,7 @@ static esp_err_t mcpwm_comparator_destory(mcpwm_cmpr_t *cmpr) if (cmpr->intr) { ESP_RETURN_ON_ERROR(esp_intr_free(cmpr->intr), TAG, "uninstall interrupt service failed"); } - if (cmpr->operator) { + if (cmpr->oper) { mcpwm_comparator_unregister_from_operator(cmpr); } free(cmpr); @@ -105,10 +105,10 @@ err: esp_err_t mcpwm_del_comparator(mcpwm_cmpr_handle_t cmpr) { ESP_RETURN_ON_FALSE(cmpr, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - mcpwm_oper_t *operator= cmpr->operator; - mcpwm_group_t *group = operator->group; + mcpwm_oper_t *oper = cmpr->oper; + mcpwm_group_t *group = oper->group; mcpwm_hal_context_t *hal = &group->hal; - int oper_id = operator->oper_id; + int oper_id = oper->oper_id; int cmpr_id = cmpr->cmpr_id; portENTER_CRITICAL(&group->spinlock); @@ -124,12 +124,12 @@ esp_err_t mcpwm_del_comparator(mcpwm_cmpr_handle_t cmpr) esp_err_t mcpwm_comparator_set_compare_value(mcpwm_cmpr_handle_t cmpr, uint32_t cmp_ticks) { - ESP_RETURN_ON_FALSE(cmpr, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - mcpwm_oper_t *oper = cmpr->operator; + ESP_RETURN_ON_FALSE_ISR(cmpr, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + mcpwm_oper_t *oper = cmpr->oper; mcpwm_group_t *group = oper->group; mcpwm_timer_t *timer = oper->timer; - ESP_RETURN_ON_FALSE(timer, ESP_ERR_INVALID_STATE, TAG, "timer and operator are not connected"); - ESP_RETURN_ON_FALSE(cmp_ticks < timer->peak_ticks, ESP_ERR_INVALID_ARG, TAG, "compare value out of range"); + ESP_RETURN_ON_FALSE_ISR(timer, ESP_ERR_INVALID_STATE, TAG, "timer and operator are not connected"); + ESP_RETURN_ON_FALSE_ISR(cmp_ticks <= timer->peak_ticks, ESP_ERR_INVALID_ARG, TAG, "compare value out of range"); portENTER_CRITICAL_SAFE(&cmpr->spinlock); mcpwm_ll_operator_set_compare_value(group->hal.dev, oper->oper_id, cmpr->cmpr_id, cmp_ticks); @@ -142,7 +142,7 @@ esp_err_t mcpwm_comparator_set_compare_value(mcpwm_cmpr_handle_t cmpr, uint32_t esp_err_t mcpwm_comparator_register_event_callbacks(mcpwm_cmpr_handle_t cmpr, const mcpwm_comparator_event_callbacks_t *cbs, void *user_data) { ESP_RETURN_ON_FALSE(cmpr && cbs, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - mcpwm_oper_t *oper = cmpr->operator; + mcpwm_oper_t *oper = cmpr->oper; mcpwm_group_t *group = oper->group; mcpwm_hal_context_t *hal = &group->hal; int group_id = group->group_id; @@ -160,7 +160,7 @@ esp_err_t mcpwm_comparator_register_event_callbacks(mcpwm_cmpr_handle_t cmpr, co // lazy install interrupt service if (!cmpr->intr) { - // we want the interrupt servie to be enabled after allocation successfully + // we want the interrupt service to be enabled after allocation successfully int isr_flags = MCPWM_INTR_ALLOC_FLAG & ~ ESP_INTR_FLAG_INTRDISABLED; ESP_RETURN_ON_ERROR(esp_intr_alloc_intrstatus(mcpwm_periph_signals.groups[group_id].irq_id, isr_flags, (uint32_t)mcpwm_ll_intr_get_status_reg(hal->dev), MCPWM_LL_EVENT_CMP_EQUAL(oper_id, cmpr_id), @@ -180,7 +180,8 @@ esp_err_t mcpwm_comparator_register_event_callbacks(mcpwm_cmpr_handle_t cmpr, co static void IRAM_ATTR mcpwm_comparator_default_isr(void *args) { mcpwm_cmpr_t *cmpr = (mcpwm_cmpr_t *)args; - mcpwm_oper_t *oper = cmpr->operator; + mcpwm_oper_t *oper = cmpr->oper; + mcpwm_timer_t *timer = oper->timer; mcpwm_group_t *group = oper->group; mcpwm_hal_context_t *hal = &group->hal; int oper_id = oper->oper_id; @@ -192,7 +193,7 @@ static void IRAM_ATTR mcpwm_comparator_default_isr(void *args) mcpwm_compare_event_data_t edata = { .compare_ticks = cmpr->compare_ticks, - // .direction = TODO + .direction = mcpwm_ll_timer_get_count_direction(hal->dev, timer->timer_id), }; if (status & MCPWM_LL_EVENT_CMP_EQUAL(oper_id, cmpr_id)) { diff --git a/components/driver/mcpwm/mcpwm_com.c b/components/driver/mcpwm/mcpwm_com.c index 7d9e555e32..fb9975d650 100644 --- a/components/driver/mcpwm/mcpwm_com.c +++ b/components/driver/mcpwm/mcpwm_com.c @@ -129,7 +129,7 @@ esp_err_t mcpwm_select_periph_clock(mcpwm_group_t *group, mcpwm_timer_clock_sour } mcpwm_ll_group_set_clock_prescale(group->hal.dev, MCPWM_PERIPH_CLOCK_PRE_SCALE); group->resolution_hz = periph_src_clk_hz / MCPWM_PERIPH_CLOCK_PRE_SCALE; - ESP_LOGD(TAG, "group (%d) clock resolution:%uHz", group->group_id, group->resolution_hz); + ESP_LOGD(TAG, "group (%d) clock resolution:%"PRIu32"Hz", group->group_id, group->resolution_hz); } return ret; } diff --git a/components/driver/mcpwm/mcpwm_fault.c b/components/driver/mcpwm/mcpwm_fault.c index e8b21f43e1..0344d2e55d 100644 --- a/components/driver/mcpwm/mcpwm_fault.c +++ b/components/driver/mcpwm/mcpwm_fault.c @@ -196,18 +196,18 @@ esp_err_t mcpwm_soft_fault_activate(mcpwm_fault_handle_t fault) ESP_RETURN_ON_FALSE(fault->type == MCPWM_FAULT_TYPE_SOFT, ESP_ERR_INVALID_ARG, TAG, "not a valid soft fault"); mcpwm_group_t *group = fault->group; mcpwm_soft_fault_t *soft_fault = __containerof(fault, mcpwm_soft_fault_t, base); - mcpwm_oper_t *operator = soft_fault->operator; - ESP_RETURN_ON_FALSE(operator, ESP_ERR_INVALID_STATE, TAG, "no operator is assigned to the fault"); + mcpwm_oper_t *oper = soft_fault->oper; + ESP_RETURN_ON_FALSE(oper, ESP_ERR_INVALID_STATE, TAG, "no operator is assigned to the fault"); - switch (operator->brake_mode_on_soft_fault) { + switch (oper->brake_mode_on_soft_fault) { case MCPWM_OPER_BRAKE_MODE_CBC: - mcpwm_ll_brake_trigger_soft_cbc(group->hal.dev, operator->oper_id); + mcpwm_ll_brake_trigger_soft_cbc(group->hal.dev, oper->oper_id); break; case MCPWM_OPER_BRAKE_MODE_OST: - mcpwm_ll_brake_trigger_soft_ost(group->hal.dev, operator->oper_id); + mcpwm_ll_brake_trigger_soft_ost(group->hal.dev, oper->oper_id); break; default: - ESP_RETURN_ON_FALSE(false, ESP_ERR_INVALID_STATE, TAG, "unknown brake mode:%d", operator->brake_mode_on_soft_fault); + ESP_RETURN_ON_FALSE(false, ESP_ERR_INVALID_STATE, TAG, "unknown brake mode:%d", oper->brake_mode_on_soft_fault); break; } return ESP_OK; @@ -243,7 +243,7 @@ esp_err_t mcpwm_fault_register_event_callbacks(mcpwm_fault_handle_t fault, const // lazy install interrupt service if (!gpio_fault->intr) { - // we want the interrupt servie to be enabled after allocation successfully + // we want the interrupt service to be enabled after allocation successfully int isr_flags = MCPWM_INTR_ALLOC_FLAG & ~ESP_INTR_FLAG_INTRDISABLED; ESP_RETURN_ON_ERROR(esp_intr_alloc_intrstatus(mcpwm_periph_signals.groups[group_id].irq_id, isr_flags, (uint32_t)mcpwm_ll_intr_get_status_reg(hal->dev), MCPWM_LL_EVENT_FAULT_MASK(fault_id), @@ -274,7 +274,7 @@ static void IRAM_ATTR mcpwm_gpio_fault_default_isr(void *args) mcpwm_ll_intr_clear_status(hal->dev, status & MCPWM_LL_EVENT_FAULT_MASK(fault_id)); mcpwm_fault_event_data_t edata = { - // TODO + // TBD }; if (status & MCPWM_LL_EVENT_FAULT_ENTER(fault_id)) { diff --git a/components/driver/mcpwm/mcpwm_gen.c b/components/driver/mcpwm/mcpwm_gen.c index 41ec7c2f62..dc43e04c9e 100644 --- a/components/driver/mcpwm/mcpwm_gen.c +++ b/components/driver/mcpwm/mcpwm_gen.c @@ -42,13 +42,13 @@ static esp_err_t mcpwm_generator_register_to_operator(mcpwm_gen_t *gen, mcpwm_op ESP_RETURN_ON_FALSE(gen_id >= 0, ESP_ERR_NOT_FOUND, TAG, "no free generator in operator (%d,%d)", oper->group->group_id, oper->oper_id); gen->gen_id = gen_id; - gen->operator = oper; + gen->oper = oper; return ESP_OK; } static void mcpwm_generator_unregister_from_operator(mcpwm_gen_t *gen) { - mcpwm_oper_t *oper = gen->operator; + mcpwm_oper_t *oper = gen->oper; int gen_id = gen->gen_id; portENTER_CRITICAL(&oper->spinlock); @@ -58,7 +58,7 @@ static void mcpwm_generator_unregister_from_operator(mcpwm_gen_t *gen) static esp_err_t mcpwm_generator_destory(mcpwm_gen_t *gen) { - if (gen->operator) { + if (gen->oper) { mcpwm_generator_unregister_from_operator(gen); } free(gen); @@ -113,7 +113,7 @@ err: esp_err_t mcpwm_del_generator(mcpwm_gen_handle_t gen) { ESP_RETURN_ON_FALSE(gen, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - mcpwm_oper_t *oper = gen->operator; + mcpwm_oper_t *oper = gen->oper; mcpwm_group_t *group = oper->group; ESP_LOGD(TAG, "del generator (%d,%d,%d)", group->group_id, oper->oper_id, gen->gen_id); @@ -125,7 +125,7 @@ esp_err_t mcpwm_del_generator(mcpwm_gen_handle_t gen) esp_err_t mcpwm_generator_set_force_level(mcpwm_gen_handle_t gen, int level, bool hold_on) { ESP_RETURN_ON_FALSE(gen && level <= 1, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - mcpwm_oper_t *oper = gen->operator; + mcpwm_oper_t *oper = gen->oper; mcpwm_group_t *group = oper->group; mcpwm_hal_context_t *hal = &group->hal; int oper_id = oper->oper_id; @@ -151,9 +151,9 @@ esp_err_t mcpwm_generator_set_force_level(mcpwm_gen_handle_t gen, int level, boo esp_err_t mcpwm_generator_set_actions_on_timer_event(mcpwm_gen_handle_t gen, mcpwm_gen_timer_event_action_t ev_act, ...) { ESP_RETURN_ON_FALSE(gen, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - mcpwm_oper_t *operator= gen->operator; - mcpwm_group_t *group = operator->group; - mcpwm_timer_t *timer = operator->timer; + mcpwm_oper_t *oper = gen->oper; + mcpwm_group_t *group = oper->group; + mcpwm_timer_t *timer = oper->timer; ESP_RETURN_ON_FALSE(timer, ESP_ERR_INVALID_STATE, TAG, "no timer is connected to the operator"); mcpwm_gen_timer_event_action_t ev_act_itor = ev_act; bool invalid_utep = false; @@ -171,7 +171,7 @@ esp_err_t mcpwm_generator_set_actions_on_timer_event(mcpwm_gen_handle_t gen, mcp va_end(it); ESP_RETURN_ON_FALSE(false, ESP_ERR_INVALID_ARG, TAG, "UTEP and DTEZ can't be reached under MCPWM_TIMER_COUNT_MODE_UP_DOWN mode"); } - mcpwm_ll_generator_set_action_on_timer_event(group->hal.dev, operator->oper_id, gen->gen_id, + mcpwm_ll_generator_set_action_on_timer_event(group->hal.dev, oper->oper_id, gen->gen_id, ev_act_itor.direction, ev_act_itor.event, ev_act_itor.action); ev_act_itor = va_arg(it, mcpwm_gen_timer_event_action_t); } @@ -182,13 +182,13 @@ esp_err_t mcpwm_generator_set_actions_on_timer_event(mcpwm_gen_handle_t gen, mcp esp_err_t mcpwm_generator_set_actions_on_compare_event(mcpwm_gen_handle_t gen, mcpwm_gen_compare_event_action_t ev_act, ...) { ESP_RETURN_ON_FALSE(gen, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - mcpwm_oper_t *operator= gen->operator; - mcpwm_group_t *group = operator->group; + mcpwm_oper_t *oper = gen->oper; + mcpwm_group_t *group = oper->group; mcpwm_gen_compare_event_action_t ev_act_itor = ev_act; va_list it; va_start(it, ev_act); while (ev_act_itor.comparator) { - mcpwm_ll_generator_set_action_on_compare_event(group->hal.dev, operator->oper_id, gen->gen_id, + mcpwm_ll_generator_set_action_on_compare_event(group->hal.dev, oper->oper_id, gen->gen_id, ev_act_itor.direction, ev_act_itor.comparator->cmpr_id, ev_act_itor.action); ev_act_itor = va_arg(it, mcpwm_gen_compare_event_action_t); } @@ -199,13 +199,13 @@ esp_err_t mcpwm_generator_set_actions_on_compare_event(mcpwm_gen_handle_t gen, m esp_err_t mcpwm_generator_set_actions_on_brake_event(mcpwm_gen_handle_t gen, mcpwm_gen_brake_event_action_t ev_act, ...) { ESP_RETURN_ON_FALSE(gen, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - mcpwm_oper_t *operator= gen->operator; - mcpwm_group_t *group = operator->group; + mcpwm_oper_t *oper = gen->oper; + mcpwm_group_t *group = oper->group; mcpwm_gen_brake_event_action_t ev_act_itor = ev_act; va_list it; va_start(it, ev_act); while (ev_act_itor.brake_mode != MCPWM_OPER_BRAKE_MODE_INVALID) { - mcpwm_ll_generator_set_action_on_brake_event(group->hal.dev, operator->oper_id, gen->gen_id, + mcpwm_ll_generator_set_action_on_brake_event(group->hal.dev, oper->oper_id, gen->gen_id, ev_act_itor.direction, ev_act_itor.brake_mode, ev_act_itor.action); ev_act_itor = va_arg(it, mcpwm_gen_brake_event_action_t); } @@ -216,13 +216,13 @@ esp_err_t mcpwm_generator_set_actions_on_brake_event(mcpwm_gen_handle_t gen, mcp esp_err_t mcpwm_generator_set_dead_time(mcpwm_gen_handle_t in_generator, mcpwm_gen_handle_t out_generator, const mcpwm_dead_time_config_t *config) { ESP_RETURN_ON_FALSE(in_generator && out_generator && config, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - ESP_RETURN_ON_FALSE(in_generator->operator == out_generator->operator, ESP_ERR_INVALID_ARG, TAG, "in/out generator are not derived from the same operator"); + ESP_RETURN_ON_FALSE(in_generator->oper == out_generator->oper, ESP_ERR_INVALID_ARG, TAG, "in/out generator are not derived from the same operator"); ESP_RETURN_ON_FALSE(config->negedge_delay_ticks < MCPWM_LL_MAX_DEAD_DELAY && config->posedge_delay_ticks < MCPWM_LL_MAX_DEAD_DELAY, ESP_ERR_INVALID_ARG, TAG, "delay time out of range"); - mcpwm_oper_t *operator= in_generator->operator; - mcpwm_group_t *group = operator->group; + mcpwm_oper_t *oper = in_generator->oper; + mcpwm_group_t *group = oper->group; mcpwm_hal_context_t *hal = &group->hal; - int oper_id = operator->oper_id; + int oper_id = oper->oper_id; // Note: to better understand the following code, you should read the deadtime module topology diagram in the TRM // check if we want to bypass the deadtime module @@ -258,7 +258,7 @@ esp_err_t mcpwm_generator_set_dead_time(mcpwm_gen_handle_t in_generator, mcpwm_g mcpwm_ll_deadtime_set_falling_delay(hal->dev, oper_id, config->negedge_delay_ticks); } - ESP_LOGD(TAG, "operator (%d,%d) dead time (R:%u,F:%u), topology code:%x", group->group_id, oper_id, + ESP_LOGD(TAG, "operator (%d,%d) dead time (R:%"PRIu32",F:%"PRIu32"), topology code:%"PRIx32, group->group_id, oper_id, config->posedge_delay_ticks, config->negedge_delay_ticks, mcpwm_ll_deadtime_get_switch_topology(hal->dev, oper_id)); return ESP_OK; } diff --git a/components/driver/mcpwm/mcpwm_oper.c b/components/driver/mcpwm/mcpwm_oper.c index cbf3219dea..75a4f3db93 100644 --- a/components/driver/mcpwm/mcpwm_oper.c +++ b/components/driver/mcpwm/mcpwm_oper.c @@ -86,19 +86,19 @@ esp_err_t mcpwm_new_operator(const mcpwm_operator_config_t *config, mcpwm_oper_h esp_log_level_set(TAG, ESP_LOG_DEBUG); #endif esp_err_t ret = ESP_OK; - mcpwm_oper_t *operator= NULL; + mcpwm_oper_t *oper = NULL; ESP_GOTO_ON_FALSE(config && ret_oper, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument"); ESP_GOTO_ON_FALSE(config->group_id < SOC_MCPWM_GROUPS && config->group_id >= 0, ESP_ERR_INVALID_ARG, err, TAG, "invalid group ID:%d", config->group_id); - operator= heap_caps_calloc(1, sizeof(mcpwm_oper_t), MCPWM_MEM_ALLOC_CAPS); - ESP_GOTO_ON_FALSE(operator, ESP_ERR_NO_MEM, err, TAG, "no mem for operator"); + oper = heap_caps_calloc(1, sizeof(mcpwm_oper_t), MCPWM_MEM_ALLOC_CAPS); + ESP_GOTO_ON_FALSE(oper, ESP_ERR_NO_MEM, err, TAG, "no mem for operator"); - ESP_GOTO_ON_ERROR(mcpwm_operator_register_to_group(operator, config->group_id), err, TAG, "register operator failed"); - mcpwm_group_t *group = operator->group; + ESP_GOTO_ON_ERROR(mcpwm_operator_register_to_group(oper, config->group_id), err, TAG, "register operator failed"); + mcpwm_group_t *group = oper->group; int group_id = group->group_id; mcpwm_hal_context_t *hal = &group->hal; - int oper_id = operator->oper_id; + int oper_id = oper->oper_id; // reset MCPWM operator mcpwm_hal_operator_reset(hal, oper_id); @@ -113,17 +113,17 @@ esp_err_t mcpwm_new_operator(const mcpwm_operator_config_t *config, mcpwm_oper_h mcpwm_ll_deadtime_enable_update_delay_on_sync(hal->dev, oper_id, config->flags.update_dead_time_on_sync); // set the clock source for dead time submodule, the resolution is the same to the MCPWM group mcpwm_ll_operator_set_deadtime_clock_src(hal->dev, oper_id, MCPWM_LL_DEADTIME_CLK_SRC_GROUP); - operator->deadtime_resolution_hz = group->resolution_hz; + oper->deadtime_resolution_hz = group->resolution_hz; // fill in other operator members - operator->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; - *ret_oper = operator; - ESP_LOGD(TAG, "new operator (%d,%d) at %p", group_id, oper_id, operator); + oper->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; + *ret_oper = oper; + ESP_LOGD(TAG, "new operator (%d,%d) at %p", group_id, oper_id, oper); return ESP_OK; err: - if (operator) { - mcpwm_operator_destory(operator); + if (oper) { + mcpwm_operator_destory(oper); } return ret; } @@ -203,7 +203,7 @@ esp_err_t mcpwm_operator_apply_carrier(mcpwm_oper_handle_t oper, const mcpwm_car mcpwm_ll_carrier_enable(hal->dev, oper_id, real_frequency > 0); if (real_frequency > 0) { - ESP_LOGD(TAG, "enable carrier modulation for operator(%d,%d), freq=%uHz, duty=%.2f, FPD=%dus", + ESP_LOGD(TAG, "enable carrier modulation for operator(%d,%d), freq=%"PRIu32"Hz, duty=%.2f, FPD=%"PRIu32"us", group->group_id, oper_id, real_frequency, real_duty, real_fpd); } else { ESP_LOGD(TAG, "disable carrier for operator (%d,%d)", group->group_id, oper_id); @@ -233,7 +233,7 @@ esp_err_t mcpwm_operator_register_event_callbacks(mcpwm_oper_handle_t oper, cons // lazy install interrupt service if (!oper->intr) { - // we want the interrupt servie to be enabled after allocation successfully + // we want the interrupt service to be enabled after allocation successfully int isr_flags = MCPWM_INTR_ALLOC_FLAG & ~ ESP_INTR_FLAG_INTRDISABLED; ESP_RETURN_ON_ERROR(esp_intr_alloc_intrstatus(mcpwm_periph_signals.groups[group_id].irq_id, isr_flags, (uint32_t)mcpwm_ll_intr_get_status_reg(hal->dev), MCPWM_LL_EVENT_OPER_MASK(oper_id), @@ -253,13 +253,13 @@ esp_err_t mcpwm_operator_register_event_callbacks(mcpwm_oper_handle_t oper, cons return ESP_OK; } -esp_err_t mcpwm_operator_set_brake_on_fault(mcpwm_oper_handle_t operator, const mcpwm_brake_config_t *config) +esp_err_t mcpwm_operator_set_brake_on_fault(mcpwm_oper_handle_t oper, const mcpwm_brake_config_t *config) { - ESP_RETURN_ON_FALSE(operator && config, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - mcpwm_group_t *group = operator->group; + ESP_RETURN_ON_FALSE(oper && config, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + mcpwm_group_t *group = oper->group; mcpwm_fault_t *fault = config->fault; - int oper_id = operator->oper_id; + int oper_id = oper->oper_id; mcpwm_ll_brake_enable_cbc_refresh_on_tez(group->hal.dev, oper_id, config->flags.cbc_recover_on_tez); mcpwm_ll_fault_enable_cbc_refresh_on_tep(group->hal.dev, oper_id, config->flags.cbc_recover_on_tep); @@ -269,17 +269,17 @@ esp_err_t mcpwm_operator_set_brake_on_fault(mcpwm_oper_handle_t operator, const mcpwm_gpio_fault_t *gpio_fault = __containerof(fault, mcpwm_gpio_fault_t, base); mcpwm_ll_brake_enable_cbc_mode(group->hal.dev, oper_id, gpio_fault->fault_id, config->brake_mode == MCPWM_OPER_BRAKE_MODE_CBC); mcpwm_ll_brake_enable_oneshot_mode(group->hal.dev, oper_id, gpio_fault->fault_id, config->brake_mode == MCPWM_OPER_BRAKE_MODE_OST); - operator->brake_mode_on_gpio_fault[gpio_fault->fault_id] = config->brake_mode; + oper->brake_mode_on_gpio_fault[gpio_fault->fault_id] = config->brake_mode; break; } case MCPWM_FAULT_TYPE_SOFT: { mcpwm_soft_fault_t *soft_fault = __containerof(fault, mcpwm_soft_fault_t, base); - ESP_RETURN_ON_FALSE(!soft_fault->operator || soft_fault->operator == operator, ESP_ERR_INVALID_STATE, TAG, "soft fault already used by another operator"); - soft_fault->operator = operator; - soft_fault->base.group = operator->group; + ESP_RETURN_ON_FALSE(!soft_fault->oper || soft_fault->oper == oper, ESP_ERR_INVALID_STATE, TAG, "soft fault already used by another operator"); + soft_fault->oper = oper; + soft_fault->base.group = oper->group; mcpwm_ll_brake_enable_soft_cbc(group->hal.dev, oper_id, config->brake_mode == MCPWM_OPER_BRAKE_MODE_CBC); mcpwm_ll_brake_enable_soft_ost(group->hal.dev, oper_id, config->brake_mode == MCPWM_OPER_BRAKE_MODE_OST); - operator->brake_mode_on_soft_fault = config->brake_mode; + oper->brake_mode_on_soft_fault = config->brake_mode; break; } default: @@ -289,21 +289,21 @@ esp_err_t mcpwm_operator_set_brake_on_fault(mcpwm_oper_handle_t operator, const return ESP_OK; } -esp_err_t mcpwm_operator_recover_from_fault(mcpwm_oper_handle_t operator, mcpwm_fault_handle_t fault) +esp_err_t mcpwm_operator_recover_from_fault(mcpwm_oper_handle_t oper, mcpwm_fault_handle_t fault) { - ESP_RETURN_ON_FALSE(operator && fault, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - mcpwm_group_t *group = operator->group; + ESP_RETURN_ON_FALSE(oper && fault, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + mcpwm_group_t *group = oper->group; mcpwm_operator_brake_mode_t brake_mode; // check the brake mode on the fault event switch (fault->type) { case MCPWM_FAULT_TYPE_GPIO: { mcpwm_gpio_fault_t *gpio_fault = __containerof(fault, mcpwm_gpio_fault_t, base); - brake_mode = operator->brake_mode_on_gpio_fault[gpio_fault->fault_id]; + brake_mode = oper->brake_mode_on_gpio_fault[gpio_fault->fault_id]; break; } case MCPWM_FAULT_TYPE_SOFT: - brake_mode = operator->brake_mode_on_soft_fault; + brake_mode = oper->brake_mode_on_soft_fault; break; default: ESP_RETURN_ON_FALSE(false, ESP_ERR_INVALID_ARG, TAG, "unknown fault type:%d", fault->type); @@ -312,13 +312,13 @@ esp_err_t mcpwm_operator_recover_from_fault(mcpwm_oper_handle_t operator, mcpwm_ bool fault_signal_is_active = false; if (brake_mode == MCPWM_OPER_BRAKE_MODE_OST) { - fault_signal_is_active = mcpwm_ll_ost_brake_active(group->hal.dev, operator->oper_id); + fault_signal_is_active = mcpwm_ll_ost_brake_active(group->hal.dev, oper->oper_id); // OST brake can't recover automatically, need to manually recovery the operator if (!fault_signal_is_active) { - mcpwm_ll_brake_clear_ost(group->hal.dev, operator->oper_id); + mcpwm_ll_brake_clear_ost(group->hal.dev, oper->oper_id); } } else { - fault_signal_is_active = mcpwm_ll_cbc_brake_active(group->hal.dev, operator->oper_id); + fault_signal_is_active = mcpwm_ll_cbc_brake_active(group->hal.dev, oper->oper_id); // CBC brake can recover automatically after deactivating the fault signal } diff --git a/components/driver/mcpwm/mcpwm_private.h b/components/driver/mcpwm/mcpwm_private.h index b5881280f8..912b0a9c92 100644 --- a/components/driver/mcpwm/mcpwm_private.h +++ b/components/driver/mcpwm/mcpwm_private.h @@ -22,16 +22,16 @@ extern "C" { #endif -#if CONFIG_MCPWM_ISR_IRAM_SAFE +#if CONFIG_MCPWM_ISR_IRAM_SAFE || CONFIG_MCPWM_CTRL_FUNC_IN_IRAM #define MCPWM_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT) #else #define MCPWM_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT #endif #if CONFIG_MCPWM_ISR_IRAM_SAFE -#define MCPWM_INTR_ALLOC_FLAG (ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_IRAM) +#define MCPWM_INTR_ALLOC_FLAG (ESP_INTR_FLAG_LOWMED | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_IRAM) #else -#define MCPWM_INTR_ALLOC_FLAG (ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_INTRDISABLED) +#define MCPWM_INTR_ALLOC_FLAG (ESP_INTR_FLAG_LOWMED | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_INTRDISABLED) #endif #define MCPWM_PERIPH_CLOCK_PRE_SCALE (2) @@ -109,7 +109,7 @@ struct mcpwm_oper_t { struct mcpwm_cmpr_t { int cmpr_id; // comparator ID, index from 0 - mcpwm_oper_t *operator; // which operator that the comparator resides in + mcpwm_oper_t *oper; // which operator that the comparator resides in intr_handle_t intr; // interrupt handle portMUX_TYPE spinlock; // spin lock uint32_t compare_ticks; // compare value of this comparator @@ -119,7 +119,7 @@ struct mcpwm_cmpr_t { struct mcpwm_gen_t { int gen_id; // generator ID, index from 0 - mcpwm_oper_t *operator; // which operator that the generator resides in + mcpwm_oper_t *oper; // which operator that the generator resides in int gen_gpio_num; // GPIO number used by the generator portMUX_TYPE spinlock; // spin lock }; @@ -138,7 +138,7 @@ struct mcpwm_fault_t { struct mcpwm_gpio_fault_t { mcpwm_fault_t base; // base class int fault_id; // fault detector ID, index from 0 - int gpio_num; // GPIO number of fault detector + int gpio_num; // GPIO number of fault detector intr_handle_t intr; // interrupt handle mcpwm_fault_event_cb_t on_fault_enter; // ISR callback function that would be invoked when fault signal got triggered mcpwm_fault_event_cb_t on_fault_exit; // ISR callback function that would be invoked when fault signal got clear @@ -147,7 +147,7 @@ struct mcpwm_gpio_fault_t { struct mcpwm_soft_fault_t { mcpwm_fault_t base; // base class - mcpwm_oper_t *operator; // the operator where the soft fault allocated from + mcpwm_oper_t *oper; // the operator where the soft fault allocated from }; typedef enum { @@ -193,6 +193,11 @@ typedef enum { MCPWM_CAP_TIMER_FSM_ENABLE, } mcpwm_cap_timer_fsm_t; +typedef enum { + MCPWM_CAP_CHAN_FSM_INIT, + MCPWM_CAP_CHAN_FSM_ENABLE, +} mcpwm_cap_channel_fsm_t; + struct mcpwm_cap_timer_t { mcpwm_group_t *group; // which group the capture timer belongs to portMUX_TYPE spinlock; // spin lock, to prevent concurrently accessing capture timer level resources, including registers @@ -206,7 +211,8 @@ struct mcpwm_cap_channel_t { int cap_chan_id; // capture channel ID, index from 0 mcpwm_cap_timer_t *cap_timer; // which capture timer that the channel resides in uint32_t prescale; // prescale of capture signal - int gpio_num; // GPIO number used by the channel + int gpio_num; // GPIO number used by the channel + mcpwm_cap_channel_fsm_t fsm; // driver FSM intr_handle_t intr; // Interrupt handle mcpwm_capture_event_cb_t on_cap; // Callback function which would be invoked in capture interrupt routine void *user_data; // user data which would be passed to the capture callback diff --git a/components/driver/mcpwm/mcpwm_timer.c b/components/driver/mcpwm/mcpwm_timer.c index e816a7db7a..6d516a9256 100644 --- a/components/driver/mcpwm/mcpwm_timer.c +++ b/components/driver/mcpwm/mcpwm_timer.c @@ -109,7 +109,7 @@ esp_err_t mcpwm_new_timer(const mcpwm_timer_config_t *config, mcpwm_timer_handle mcpwm_ll_timer_set_clock_prescale(hal->dev, timer_id, prescale); timer->resolution_hz = group->resolution_hz / prescale; if (timer->resolution_hz != config->resolution_hz) { - ESP_LOGW(TAG, "adjust timer resolution to %uHz", timer->resolution_hz); + ESP_LOGW(TAG, "adjust timer resolution to %"PRIu32"Hz", timer->resolution_hz); } // set the peak tickes that the timer can reach to @@ -130,7 +130,7 @@ esp_err_t mcpwm_new_timer(const mcpwm_timer_config_t *config, mcpwm_timer_handle timer->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; timer->fsm = MCPWM_TIMER_FSM_INIT; *ret_timer = timer; - ESP_LOGD(TAG, "new timer(%d,%d) at %p, resolution:%uHz, peak:%u, count_mod:%c", + ESP_LOGD(TAG, "new timer(%d,%d) at %p, resolution:%"PRIu32"Hz, peak:%"PRIu32", count_mod:%c", group_id, timer_id, timer, timer->resolution_hz, timer->peak_ticks, "SUDB"[timer->count_mode]); return ESP_OK; @@ -166,7 +166,6 @@ esp_err_t mcpwm_del_timer(mcpwm_timer_handle_t timer) esp_err_t mcpwm_timer_register_event_callbacks(mcpwm_timer_handle_t timer, const mcpwm_timer_event_callbacks_t *cbs, void *user_data) { ESP_RETURN_ON_FALSE(timer && cbs, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - ESP_RETURN_ON_FALSE(timer->fsm == MCPWM_TIMER_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "timer not in init state"); mcpwm_group_t *group = timer->group; int group_id = group->group_id; int timer_id = timer->timer_id; @@ -189,6 +188,7 @@ esp_err_t mcpwm_timer_register_event_callbacks(mcpwm_timer_handle_t timer, const // lazy install interrupt service if (!timer->intr) { + ESP_RETURN_ON_FALSE(timer->fsm == MCPWM_TIMER_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "timer not in init state"); int isr_flags = MCPWM_INTR_ALLOC_FLAG; ESP_RETURN_ON_ERROR(esp_intr_alloc_intrstatus(mcpwm_periph_signals.groups[group_id].irq_id, isr_flags, (uint32_t)mcpwm_ll_intr_get_status_reg(hal->dev), MCPWM_LL_EVENT_TIMER_MASK(timer_id), @@ -273,6 +273,18 @@ esp_err_t mcpwm_timer_set_phase_on_sync(mcpwm_timer_handle_t timer, const mcpwm_ int group_id = group->group_id; int timer_id = timer->timer_id; mcpwm_sync_handle_t sync_source = config->sync_src; + // check if the sync direction is valid + bool valid_direction = true; + if (timer->count_mode == MCPWM_TIMER_COUNT_MODE_UP) { + valid_direction = config->direction == MCPWM_TIMER_DIRECTION_UP; + } else if (timer->count_mode == MCPWM_TIMER_COUNT_MODE_DOWN) { + valid_direction = config->direction == MCPWM_TIMER_DIRECTION_DOWN; + } else if (timer->count_mode == MCPWM_TIMER_COUNT_MODE_PAUSE) { + valid_direction = false; + } else { + valid_direction = true; + } + ESP_RETURN_ON_FALSE(valid_direction, ESP_ERR_INVALID_ARG, TAG, "invalid sync direction"); // enable sync feature and set sync phase if (sync_source) { diff --git a/components/driver/pulse_cnt.c b/components/driver/pulse_cnt.c index c40d9f8a9c..cd56d273bb 100644 --- a/components/driver/pulse_cnt.c +++ b/components/driver/pulse_cnt.c @@ -41,9 +41,9 @@ #endif #if CONFIG_PCNT_ISR_IRAM_SAFE -#define PCNT_INTR_ALLOC_FLAGS (ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_SHARED) +#define PCNT_INTR_ALLOC_FLAGS (ESP_INTR_FLAG_LOWMED | ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_SHARED) #else -#define PCNT_INTR_ALLOC_FLAGS (ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_SHARED) +#define PCNT_INTR_ALLOC_FLAGS (ESP_INTR_FLAG_LOWMED | ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_SHARED) #endif #define PCNT_PM_LOCK_NAME_LEN_MAX 16 @@ -81,7 +81,7 @@ typedef enum { struct pcnt_unit_t { pcnt_group_t *group; // which group the pcnt unit belongs to portMUX_TYPE spinlock; // Spinlock, stop one unit from accessing different parts of a same register concurrently - uint32_t unit_id; // allocated unit numerical ID + int unit_id; // allocated unit numerical ID int low_limit; // low limit value int high_limit; // high limit value pcnt_chan_t *channels[SOC_PCNT_CHANNELS_PER_UNIT]; // array of PCNT channels @@ -98,7 +98,7 @@ struct pcnt_unit_t { struct pcnt_chan_t { pcnt_unit_t *unit; // pointer to the PCNT unit where it derives from - uint32_t channel_id; // channel ID, index from 0 + int channel_id; // channel ID, index from 0 int edge_gpio_num; int level_gpio_num; }; @@ -283,7 +283,7 @@ esp_err_t pcnt_unit_enable(pcnt_unit_handle_t unit) if (unit->pm_lock) { ESP_RETURN_ON_ERROR(esp_pm_lock_acquire(unit->pm_lock), TAG, "acquire pm_lock failed"); } - // enable interupt service + // enable interrupt service if (unit->intr) { ESP_RETURN_ON_ERROR(esp_intr_enable(unit->intr), TAG, "enable interrupt service failed"); } @@ -366,7 +366,6 @@ esp_err_t pcnt_unit_register_event_callbacks(pcnt_unit_handle_t unit, const pcnt { ESP_RETURN_ON_FALSE(unit && cbs, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); // unit event callbacks should be registered in init state - ESP_RETURN_ON_FALSE(unit->fsm == PCNT_UNIT_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "unit not in init state"); pcnt_group_t *group = unit->group; int group_id = group->group_id; int unit_id = unit->unit_id; @@ -382,6 +381,7 @@ esp_err_t pcnt_unit_register_event_callbacks(pcnt_unit_handle_t unit, const pcnt // lazy install interrupt service if (!unit->intr) { + ESP_RETURN_ON_FALSE(unit->fsm == PCNT_UNIT_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "unit not in init state"); int isr_flags = PCNT_INTR_ALLOC_FLAGS; ESP_RETURN_ON_ERROR(esp_intr_alloc_intrstatus(pcnt_periph_signals.groups[group_id].irq, isr_flags, (uint32_t)pcnt_ll_get_intr_status_reg(group->hal.dev), PCNT_LL_UNIT_WATCH_EVENT(unit_id), diff --git a/components/driver/rmt/rmt_common.c b/components/driver/rmt/rmt_common.c index 308f5ec629..e3dc6ed448 100644 --- a/components/driver/rmt/rmt_common.c +++ b/components/driver/rmt/rmt_common.c @@ -66,7 +66,7 @@ rmt_group_t *rmt_acquire_group_handle(int group_id) _lock_release(&s_platform.mutex); if (new_group) { - ESP_LOGD(TAG, "new group(%d) at %p, occupy=%x", group_id, group, group->occupy_mask); + ESP_LOGD(TAG, "new group(%d) at %p, occupy=%"PRIx32, group_id, group, group->occupy_mask); } return group; } @@ -74,6 +74,7 @@ rmt_group_t *rmt_acquire_group_handle(int group_id) void rmt_release_group_handle(rmt_group_t *group) { int group_id = group->group_id; + rmt_clock_source_t clk_src = group->clk_src; bool do_deinitialize = false; _lock_acquire(&s_platform.mutex); @@ -88,6 +89,16 @@ void rmt_release_group_handle(rmt_group_t *group) } _lock_release(&s_platform.mutex); + switch (clk_src) { +#if SOC_RMT_SUPPORT_RC_FAST + case RMT_CLK_SRC_RC_FAST: + periph_rtc_dig_clk8m_disable(); + break; +#endif // SOC_RMT_SUPPORT_RC_FAST + default: + break; + } + if (do_deinitialize) { ESP_LOGD(TAG, "del group(%d)", group_id); } @@ -153,7 +164,7 @@ esp_err_t rmt_select_periph_clock(rmt_channel_handle_t chan, rmt_clock_source_t // no division for group clock source, to achieve highest resolution rmt_ll_set_group_clock_src(group->hal.regs, channel_id, clk_src, 1, 1, 0); group->resolution_hz = periph_src_clk_hz; - ESP_LOGD(TAG, "group clock resolution:%u", group->resolution_hz); + ESP_LOGD(TAG, "group clock resolution:%"PRIu32, group->resolution_hz); return ret; } diff --git a/components/driver/rmt/rmt_private.h b/components/driver/rmt/rmt_private.h index 19a80b028c..a5e0319a1f 100644 --- a/components/driver/rmt/rmt_private.h +++ b/components/driver/rmt/rmt_private.h @@ -34,9 +34,9 @@ extern "C" { // RMT driver object is per-channel, the interrupt source is shared between channels #if CONFIG_RMT_ISR_IRAM_SAFE -#define RMT_INTR_ALLOC_FLAG (ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_IRAM) +#define RMT_INTR_ALLOC_FLAG (ESP_INTR_FLAG_LOWMED | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_IRAM) #else -#define RMT_INTR_ALLOC_FLAG ESP_INTR_FLAG_SHARED +#define RMT_INTR_ALLOC_FLAG (ESP_INTR_FLAG_LOWMED | ESP_INTR_FLAG_SHARED) #endif // Hopefully the channel offset won't change in other targets diff --git a/components/driver/rmt/rmt_rx.c b/components/driver/rmt/rmt_rx.c index e38ab7231f..9dc3a94d5a 100644 --- a/components/driver/rmt/rmt_rx.c +++ b/components/driver/rmt/rmt_rx.c @@ -239,7 +239,7 @@ esp_err_t rmt_new_rx_channel(const rmt_rx_channel_config_t *config, rmt_channel_ // resolution loss due to division, calculate the real resolution rx_channel->base.resolution_hz = group->resolution_hz / real_div; if (rx_channel->base.resolution_hz != config->resolution_hz) { - ESP_LOGW(TAG, "channel resolution loss, real=%u", rx_channel->base.resolution_hz); + ESP_LOGW(TAG, "channel resolution loss, real=%"PRIu32, rx_channel->base.resolution_hz); } rmt_ll_rx_set_mem_blocks(hal->regs, channel_id, rx_channel->base.mem_block_num); @@ -282,7 +282,7 @@ esp_err_t rmt_new_rx_channel(const rmt_rx_channel_config_t *config, rmt_channel_ rx_channel->base.disable = rmt_rx_disable; // return general channel handle *ret_chan = &rx_channel->base; - ESP_LOGD(TAG, "new rx channel(%d,%d) at %p, gpio=%d, res=%uHz, hw_mem_base=%p, ping_pong_size=%d", + ESP_LOGD(TAG, "new rx channel(%d,%d) at %p, gpio=%d, res=%"PRIu32"Hz, hw_mem_base=%p, ping_pong_size=%d", group_id, channel_id, rx_channel, config->gpio_num, rx_channel->base.resolution_hz, rx_channel->base.hw_mem_base, rx_channel->ping_pong_symbols); return ESP_OK; @@ -405,7 +405,7 @@ static esp_err_t rmt_rx_demodulate_carrier(rmt_channel_handle_t channel, const r portEXIT_CRITICAL(&channel->spinlock); if (real_frequency > 0) { - ESP_LOGD(TAG, "enable carrier demodulation for channel(%d,%d), freq=%uHz", group_id, channel_id, real_frequency); + ESP_LOGD(TAG, "enable carrier demodulation for channel(%d,%d), freq=%"PRIu32"Hz", group_id, channel_id, real_frequency); } else { ESP_LOGD(TAG, "disable carrier demodulation for channel(%d, %d)", group_id, channel_id); } diff --git a/components/driver/rmt/rmt_tx.c b/components/driver/rmt/rmt_tx.c index b2c6bff66e..5d814a515a 100644 --- a/components/driver/rmt/rmt_tx.c +++ b/components/driver/rmt/rmt_tx.c @@ -260,7 +260,7 @@ esp_err_t rmt_new_tx_channel(const rmt_tx_channel_config_t *config, rmt_channel_ // resolution lost due to division, calculate the real resolution tx_channel->base.resolution_hz = group->resolution_hz / real_div; if (tx_channel->base.resolution_hz != config->resolution_hz) { - ESP_LOGW(TAG, "channel resolution loss, real=%u", tx_channel->base.resolution_hz); + ESP_LOGW(TAG, "channel resolution loss, real=%"PRIu32, tx_channel->base.resolution_hz); } rmt_ll_tx_set_mem_blocks(hal->regs, channel_id, tx_channel->base.mem_block_num); @@ -300,7 +300,7 @@ esp_err_t rmt_new_tx_channel(const rmt_tx_channel_config_t *config, rmt_channel_ tx_channel->base.disable = rmt_tx_disable; // return general channel handle *ret_chan = &tx_channel->base; - ESP_LOGD(TAG, "new tx channel(%d,%d) at %p, gpio=%d, res=%uHz, hw_mem_base=%p, dma_mem_base=%p, ping_pong_size=%zu, queue_depth=%zu", + ESP_LOGD(TAG, "new tx channel(%d,%d) at %p, gpio=%d, res=%"PRIu32"Hz, hw_mem_base=%p, dma_mem_base=%p, ping_pong_size=%zu, queue_depth=%zu", group_id, channel_id, tx_channel, config->gpio_num, tx_channel->base.resolution_hz, tx_channel->base.hw_mem_base, tx_channel->base.dma_mem_base, tx_channel->ping_pong_symbols, tx_channel->queue_size); return ESP_OK; @@ -380,7 +380,7 @@ esp_err_t rmt_new_sync_manager(const rmt_sync_manager_config_t *config, rmt_sync *ret_synchro = synchro; - ESP_LOGD(TAG, "new sync manager at %p, with channel mask:%02x", synchro, synchro->channel_mask); + ESP_LOGD(TAG, "new sync manager at %p, with channel mask:%02"PRIx32, synchro, synchro->channel_mask); return ESP_OK; err: @@ -797,7 +797,7 @@ static esp_err_t rmt_tx_modulate_carrier(rmt_channel_handle_t channel, const rmt portEXIT_CRITICAL(&channel->spinlock); if (real_frequency > 0) { - ESP_LOGD(TAG, "enable carrier modulation for channel(%d,%d), freq=%uHz", group_id, channel_id, real_frequency); + ESP_LOGD(TAG, "enable carrier modulation for channel(%d,%d), freq=%"PRIu32"Hz", group_id, channel_id, real_frequency); } else { ESP_LOGD(TAG, "disable carrier modulation for channel(%d,%d)", group_id, channel_id); } diff --git a/components/driver/sdio_slave.c b/components/driver/sdio_slave.c index e0e848b51e..8234716791 100644 --- a/components/driver/sdio_slave.c +++ b/components/driver/sdio_slave.c @@ -230,6 +230,7 @@ static esp_err_t init_context(const sdio_slave_config_t *config) context.hal->sending_mode = config->sending_mode; context.hal->timing = config->timing; + context.hal->no_highspeed = (config->flags & SDIO_SLAVE_FLAG_DEFAULT_SPEED) == SDIO_SLAVE_FLAG_DEFAULT_SPEED; context.hal->send_queue_size = config->send_queue_size; context.hal->recv_buffer_size = config->recv_buffer_size; //initialize ringbuffer resources @@ -312,7 +313,6 @@ static inline esp_err_t sdio_slave_hw_init(sdio_slave_config_t *config) periph_module_enable(PERIPH_SDIO_SLAVE_MODULE); sdio_slave_hal_hw_init(context.hal); - return ESP_OK; } diff --git a/components/driver/sdm.c b/components/driver/sdm.c index 435af6853c..6a0830ca3a 100644 --- a/components/driver/sdm.c +++ b/components/driver/sdm.c @@ -247,7 +247,7 @@ esp_err_t sdm_new_channel(const sdm_config_t *config, sdm_channel_handle_t *ret_ chan->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; chan->fsm = SDM_FSM_INIT; // put the channel into init state - ESP_LOGD(TAG, "new sdm channel (%d,%d) at %p, gpio=%d, sample rate=%uHz", group_id, chan_id, chan, chan->gpio_num, chan->sample_rate_hz); + ESP_LOGD(TAG, "new sdm channel (%d,%d) at %p, gpio=%d, sample rate=%"PRIu32"Hz", group_id, chan_id, chan, chan->gpio_num, chan->sample_rate_hz); *ret_chan = chan; return ESP_OK; err: diff --git a/components/driver/sdmmc_host.c b/components/driver/sdmmc_host.c index 1f2b281602..4c7fc7c4b2 100644 --- a/components/driver/sdmmc_host.c +++ b/components/driver/sdmmc_host.c @@ -171,12 +171,47 @@ static void sdmmc_host_clock_update_command(int slot) } } +void sdmmc_host_get_clk_dividers(const uint32_t freq_khz, int *host_div, int *card_div) +{ + // Calculate new dividers + if (freq_khz >= SDMMC_FREQ_HIGHSPEED) { + *host_div = 4; // 160 MHz / 4 = 40 MHz + *card_div = 0; + } else if (freq_khz == SDMMC_FREQ_DEFAULT) { + *host_div = 8; // 160 MHz / 8 = 20 MHz + *card_div = 0; + } else if (freq_khz == SDMMC_FREQ_PROBING) { + *host_div = 10; // 160 MHz / 10 / (20 * 2) = 400 kHz + *card_div = 20; + } else { + /* + * for custom frequencies use maximum range of host divider (1-16), find the closest <= div. combination + * if exceeded, combine with the card divider to keep reasonable precision (applies mainly to low frequencies) + * effective frequency range: 400 kHz - 32 MHz (32.1 - 39.9 MHz cannot be covered with given divider scheme) + */ + *host_div = (2 * APB_CLK_FREQ) / (freq_khz * 1000); + if (*host_div > 15 ) { + *host_div = 2; + *card_div = APB_CLK_FREQ / (2 * freq_khz * 1000); + if ( (APB_CLK_FREQ % (2 * freq_khz * 1000)) > 0 ) { + (*card_div)++; + } + } else if ( ((2 * APB_CLK_FREQ) % (freq_khz * 1000)) > 0 ) { + (*host_div)++; + } + } +} + +static int sdmmc_host_calc_freq(const int host_div, const int card_div) +{ + return 2 * APB_CLK_FREQ / host_div / ((card_div == 0) ? 1 : card_div * 2) / 1000; +} + esp_err_t sdmmc_host_set_card_clk(int slot, uint32_t freq_khz) { if (!(slot == 0 || slot == 1)) { return ESP_ERR_INVALID_ARG; } - const int clk40m = 40000; // Disable clock first SDMMC.clkena.cclk_enable &= ~BIT(slot); @@ -184,25 +219,10 @@ esp_err_t sdmmc_host_set_card_clk(int slot, uint32_t freq_khz) int host_div = 0; /* clock divider of the host (SDMMC.clock) */ int card_div = 0; /* 1/2 of card clock divider (SDMMC.clkdiv) */ + sdmmc_host_get_clk_dividers(freq_khz, &host_div, &card_div); - // Calculate new dividers - if (freq_khz >= SDMMC_FREQ_HIGHSPEED) { - host_div = 4; // 160 MHz / 4 = 40 MHz - card_div = 0; - } else if (freq_khz == SDMMC_FREQ_DEFAULT) { - host_div = 8; // 160 MHz / 8 = 20 MHz - card_div = 0; - } else if (freq_khz == SDMMC_FREQ_PROBING) { - host_div = 10; // 160 MHz / 10 / (20 * 2) = 400 kHz - card_div = 20; - } else { - host_div = 2; - card_div = (clk40m + freq_khz * 2 - 1) / (freq_khz * 2); // round up - } - - ESP_LOGD(TAG, "slot=%d host_div=%d card_div=%d freq=%dkHz", - slot, host_div, card_div, - 2 * APB_CLK_FREQ / host_div / ((card_div == 0) ? 1 : card_div * 2) / 1000); + int real_freq = sdmmc_host_calc_freq(host_div, card_div); + ESP_LOGD(TAG, "slot=%d host_div=%d card_div=%d freq=%dkHz (max %" PRIu32 "kHz)", slot, host_div, card_div, real_freq, freq_khz); // Program CLKDIV and CLKSRC, send them to the CIU switch(slot) { @@ -236,6 +256,22 @@ esp_err_t sdmmc_host_set_card_clk(int slot, uint32_t freq_khz) return ESP_OK; } +esp_err_t sdmmc_host_get_real_freq(int slot, int* real_freq_khz) +{ + if (real_freq_khz == NULL) { + return ESP_ERR_INVALID_ARG; + } + if (!(slot == 0 || slot == 1)) { + return ESP_ERR_INVALID_ARG; + } + + int host_div = SDMMC.clock.div_factor_p + 1; + int card_div = slot == 0 ? SDMMC.clkdiv.div0 : SDMMC.clkdiv.div1; + *real_freq_khz = sdmmc_host_calc_freq(host_div, card_div); + + return ESP_OK; +} + esp_err_t sdmmc_host_start_command(int slot, sdmmc_hw_cmd_t cmd, uint32_t arg) { if (!(slot == 0 || slot == 1)) { return ESP_ERR_INVALID_ARG; @@ -270,7 +306,7 @@ esp_err_t sdmmc_host_init(void) // Reset sdmmc_host_reset(); - ESP_LOGD(TAG, "peripheral version %x, hardware config %08x", SDMMC.verid, SDMMC.hcon); + ESP_LOGD(TAG, "peripheral version %"PRIx32", hardware config %08"PRIx32, SDMMC.verid, SDMMC.hcon); // Clear interrupt status and set interrupt mask to known state SDMMC.rintsts.val = 0xffffffff; diff --git a/components/driver/sdmmc_transaction.c b/components/driver/sdmmc_transaction.c index e4dc22e465..9c56b1c2f8 100644 --- a/components/driver/sdmmc_transaction.c +++ b/components/driver/sdmmc_transaction.c @@ -239,7 +239,7 @@ static esp_err_t handle_idle_state_events(void) evt.sdmmc_status &= ~SDMMC_INTMASK_CD; } if (evt.sdmmc_status != 0 || evt.dma_status != 0) { - ESP_LOGE(TAG, "handle_idle_state_events unhandled: %08x %08x", + ESP_LOGE(TAG, "handle_idle_state_events unhandled: %08"PRIx32" %08"PRIx32, evt.sdmmc_status, evt.dma_status); } @@ -260,13 +260,13 @@ static esp_err_t handle_event(sdmmc_command_t* cmd, sdmmc_req_state_t* state, } return err; } - ESP_LOGV(TAG, "sdmmc_handle_event: event %08x %08x, unhandled %08x %08x", + ESP_LOGV(TAG, "sdmmc_handle_event: event %08"PRIx32" %08"PRIx32", unhandled %08"PRIx32" %08"PRIx32, event.sdmmc_status, event.dma_status, unhandled_events->sdmmc_status, unhandled_events->dma_status); event.sdmmc_status |= unhandled_events->sdmmc_status; event.dma_status |= unhandled_events->dma_status; process_events(event, cmd, state, unhandled_events); - ESP_LOGV(TAG, "sdmmc_handle_event: events unhandled: %08x %08x", unhandled_events->sdmmc_status, unhandled_events->dma_status); + ESP_LOGV(TAG, "sdmmc_handle_event: events unhandled: %08"PRIx32" %08"PRIx32, unhandled_events->sdmmc_status, unhandled_events->dma_status); return ESP_OK; } @@ -347,7 +347,7 @@ static void process_command_response(uint32_t status, sdmmc_command_t* cmd) if (cmd->data) { sdmmc_host_dma_stop(); } - ESP_LOGD(TAG, "%s: error 0x%x (status=%08x)", __func__, err, status); + ESP_LOGD(TAG, "%s: error 0x%x (status=%08"PRIx32")", __func__, err, status); } } @@ -370,7 +370,7 @@ static void process_data_status(uint32_t status, sdmmc_command_t* cmd) if (cmd->data) { sdmmc_host_dma_stop(); } - ESP_LOGD(TAG, "%s: error 0x%x (status=%08x)", __func__, cmd->error, status); + ESP_LOGD(TAG, "%s: error 0x%x (status=%08"PRIx32")", __func__, cmd->error, status); } } @@ -391,7 +391,7 @@ static esp_err_t process_events(sdmmc_event_t evt, sdmmc_command_t* cmd, "BUSY" }; sdmmc_event_t orig_evt = evt; - ESP_LOGV(TAG, "%s: state=%s evt=%x dma=%x", __func__, s_state_names[*pstate], + ESP_LOGV(TAG, "%s: state=%s evt=%"PRIx32" dma=%"PRIx32, __func__, s_state_names[*pstate], evt.sdmmc_status, evt.dma_status); sdmmc_req_state_t next_state = *pstate; sdmmc_req_state_t state = (sdmmc_req_state_t) -1; diff --git a/components/driver/sdspi_host.c b/components/driver/sdspi_host.c index a09a63595d..b94f13869d 100644 --- a/components/driver/sdspi_host.c +++ b/components/driver/sdspi_host.c @@ -43,7 +43,7 @@ typedef struct { spi_host_device_t host_id; //!< SPI host id. spi_device_handle_t spi_handle; //!< SPI device handle, used for transactions - uint8_t gpio_cs; //!< CS GPIO + uint8_t gpio_cs; //!< CS GPIO, or GPIO_UNUSED uint8_t gpio_cd; //!< Card detect GPIO, or GPIO_UNUSED uint8_t gpio_wp; //!< Write protect GPIO, or GPIO_UNUSED uint8_t gpio_int; //!< Write protect GPIO, or GPIO_UNUSED @@ -120,13 +120,17 @@ static slot_info_t* remove_slot_info(sdspi_dev_handle_t handle) /// Set CS high for given slot static void cs_high(slot_info_t *slot) { - gpio_set_level(slot->gpio_cs, 1); + if (slot->gpio_cs != GPIO_UNUSED) { + gpio_set_level(slot->gpio_cs, 1); + } } /// Set CS low for given slot static void cs_low(slot_info_t *slot) { - gpio_set_level(slot->gpio_cs, 0); + if (slot->gpio_cs != GPIO_UNUSED) { + gpio_set_level(slot->gpio_cs, 0); + } } /// Return true if WP pin is configured and is low @@ -248,7 +252,9 @@ static esp_err_t deinit_slot(slot_info_t *slot) .mode = GPIO_MODE_INPUT, .intr_type = GPIO_INTR_DISABLE, }; - gpio_config(&config); + if (pin_bit_mask != 0) { + gpio_config(&config); + } if (slot->semphr_int) { vSemaphoreDelete(slot->semphr_int); @@ -289,10 +295,20 @@ esp_err_t sdspi_host_set_card_clk(sdspi_dev_handle_t handle, uint32_t freq_khz) if (slot == NULL) { return ESP_ERR_INVALID_ARG; } - ESP_LOGD(TAG, "Setting card clock to %d kHz", freq_khz); + ESP_LOGD(TAG, "Setting card clock to %"PRIu32" kHz", freq_khz); return configure_spi_dev(slot, freq_khz * 1000); } +esp_err_t sdspi_host_get_real_freq(sdspi_dev_handle_t handle, int* real_freq_khz) +{ + slot_info_t *slot = get_slot_info(handle); + if (slot == NULL) { + return ESP_ERR_INVALID_ARG; + } + + return spi_device_get_actual_freq(slot->spi_handle, real_freq_khz); +} + static void gpio_intr(void* arg) { BaseType_t awoken = pdFALSE; @@ -332,13 +348,20 @@ esp_err_t sdspi_host_init_device(const sdspi_device_config_t* slot_config, sdspi .mode = GPIO_MODE_OUTPUT, .pin_bit_mask = 1ULL << slot_config->gpio_cs, }; - - ret = gpio_config(&io_conf); - if (ret != ESP_OK) { - ESP_LOGD(TAG, "gpio_config (CS) failed with rc=0x%x", ret); - goto cleanup; + if (slot_config->gpio_cs != SDSPI_SLOT_NO_CS) { + slot->gpio_cs = slot_config->gpio_cs; + } else { + slot->gpio_cs = GPIO_UNUSED; + } + + if (slot->gpio_cs != GPIO_UNUSED) { + ret = gpio_config(&io_conf); + if (ret != ESP_OK) { + ESP_LOGD(TAG, "gpio_config (CS) failed with rc=0x%x", ret); + goto cleanup; + } + cs_high(slot); } - cs_high(slot); // Configure CD and WP pins io_conf = (gpio_config_t) { @@ -434,7 +457,7 @@ esp_err_t sdspi_host_start_command(sdspi_dev_handle_t handle, sdspi_hw_cmd_t *cm uint32_t cmd_arg; memcpy(&cmd_arg, cmd->arguments, sizeof(cmd_arg)); cmd_arg = __builtin_bswap32(cmd_arg); - ESP_LOGV(TAG, "%s: slot=%i, CMD%d, arg=0x%08x flags=0x%x, data=%p, data_size=%i crc=0x%02x", + ESP_LOGV(TAG, "%s: slot=%i, CMD%d, arg=0x%08"PRIx32" flags=0x%x, data=%p, data_size=%"PRIu32" crc=0x%02x", __func__, handle, cmd_index, cmd_arg, flags, data, data_size, cmd->crc7); spi_device_acquire_bus(slot->spi_handle, portMAX_DELAY); diff --git a/components/driver/sdspi_transaction.c b/components/driver/sdspi_transaction.c index 583c6cfc35..f60b9535d0 100644 --- a/components/driver/sdspi_transaction.c +++ b/components/driver/sdspi_transaction.c @@ -152,7 +152,7 @@ esp_err_t sdspi_host_do_transaction(int slot, sdmmc_command_t *cmdinfo) // Extract response bytes and store them into cmdinfo structure if (ret == ESP_OK) { - ESP_LOGV(TAG, "r1 = 0x%02x hw_cmd.r[0]=0x%08x", hw_cmd.r1, hw_cmd.response[0]); + ESP_LOGV(TAG, "r1 = 0x%02x hw_cmd.r[0]=0x%08"PRIx32, hw_cmd.r1, hw_cmd.response[0]); // Some errors should be reported using return code if (flags & (SDSPI_CMD_FLAG_RSP_R1 | SDSPI_CMD_FLAG_RSP_R1B)) { cmdinfo->response[0] = hw_cmd.r1; diff --git a/components/driver/spi_bus_lock.c b/components/driver/spi_bus_lock.c index 299d1b6562..eab815b8ad 100644 --- a/components/driver/spi_bus_lock.c +++ b/components/driver/spi_bus_lock.c @@ -217,6 +217,44 @@ struct spi_bus_lock_dev_t { uint32_t mask; ///< Bitwise OR-ed mask of the REQ, PEND, LOCK bits of this device }; +/** + * @note 1 + * This critical section is only used to fix such condition: + * + * define: lock_bits = (lock->status & LOCK_MASK) >> LOCK_SHIFT; This `lock_bits` is the Bit 29-20 of the lock->status + * + * 1. spi_hdl_1: + * acquire_end_core(): + * uint32_t status = lock_status_clear(lock, dev_handle->mask & LOCK_MASK); + * + * Becuase this is the first `spi_hdl_1`, so after this , lock_bits == 0`b0. status == 0 + * + * 2. spi_hdl_2: + * acquire_core: + * uint32_t status = lock_status_fetch_set(lock, dev_handle->mask & LOCK_MASK); + * + * Then here status is 0`b0, but lock_bits == 0`b10. Because this is the `spi_hdl_2` + * + * 3. spi_hdl_2: + * `acquire_core` return true, because status == 0. `spi_bus_lock_acquire_start(spi_hdl_2)` then won't block. + * + * 4. spi_hdl_2: + * spi_device_polling_end(spi_hdl_2). + * + * 5. spi_hdl_1: + * acquire_end_core: + * status is 0, so it cleas the lock->acquiring_dev + * + * 6. spi_hdl_2: + * spi_device_polling_end: + * assert(handle == get_acquiring_dev(host)); Fail + * + * @note 2 + * Only use this critical section in this condition. The critical section scope is limited to the smallest. + * As `spi_bus_lock` influences the all the SPIs (including MSPI) a lot! + */ +portMUX_TYPE s_spinlock = portMUX_INITIALIZER_UNLOCKED; + DRAM_ATTR static const char TAG[] = "bus_lock"; #define LOCK_CHECK(a, str, ret_val, ...) \ @@ -323,7 +361,11 @@ SPI_MASTER_ATTR static inline void req_core(spi_bus_lock_dev_t *dev_handle) SPI_MASTER_ISR_ATTR static inline bool acquire_core(spi_bus_lock_dev_t *dev_handle) { spi_bus_lock_t* lock = dev_handle->parent; + + //For this critical section, search `@note 1` in this file, to know details + portENTER_CRITICAL_SAFE(&s_spinlock); uint32_t status = lock_status_fetch_set(lock, dev_handle->mask & LOCK_MASK); + portEXIT_CRITICAL_SAFE(&s_spinlock); // Check all bits except WEAK_BG if ((status & (BG_MASK | LOCK_MASK)) == 0) { @@ -401,10 +443,14 @@ schedule_core(spi_bus_lock_t *lock, uint32_t status, spi_bus_lock_dev_t **out_de IRAM_ATTR static inline void acquire_end_core(spi_bus_lock_dev_t *dev_handle) { spi_bus_lock_t* lock = dev_handle->parent; - uint32_t status = lock_status_clear(lock, dev_handle->mask & LOCK_MASK); spi_bus_lock_dev_t* desired_dev = NULL; + //For this critical section, search `@note 1` in this file, to know details + portENTER_CRITICAL_SAFE(&s_spinlock); + uint32_t status = lock_status_clear(lock, dev_handle->mask & LOCK_MASK); bool invoke_bg = !schedule_core(lock, status, &desired_dev); + portEXIT_CRITICAL_SAFE(&s_spinlock); + if (invoke_bg) { bg_enable(lock); } else if (desired_dev) { diff --git a/components/driver/spi_master.c b/components/driver/spi_master.c index 0a7cac3523..71a51e90bf 100644 --- a/components/driver/spi_master.c +++ b/components/driver/spi_master.c @@ -329,6 +329,12 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa SPI_CHECK(dev_config->cs_ena_pretrans <= 1 || (dev_config->address_bits == 0 && dev_config->command_bits == 0) || (dev_config->flags & SPI_DEVICE_HALFDUPLEX), "In full-duplex mode, only support cs pretrans delay = 1 and without address_bits and command_bits", ESP_ERR_INVALID_ARG); #endif + + //Check post_cb status when `SPI_DEVICE_NO_RETURN_RESULT` flag is set. + if (dev_config->flags & SPI_DEVICE_NO_RETURN_RESULT) { + SPI_CHECK(dev_config->post_cb != NULL, "use feature flag 'SPI_DEVICE_NO_RETURN_RESULT' but no post callback function sets", ESP_ERR_INVALID_ARG); + } + uint32_t lock_flag = ((dev_config->spics_io_num != -1)? SPI_BUS_LOCK_DEV_FLAG_CS_REQUIRED: 0); spi_bus_lock_dev_config_t lock_config = { @@ -375,10 +381,16 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa //Allocate queues, set defaults dev->trans_queue = xQueueCreate(dev_config->queue_size, sizeof(spi_trans_priv_t)); - dev->ret_queue = xQueueCreate(dev_config->queue_size, sizeof(spi_trans_priv_t)); - if (!dev->trans_queue || !dev->ret_queue) { + if (!dev->trans_queue) { goto nomem; } + //ret_queue nolonger needed if use flag SPI_DEVICE_NO_RETURN_RESULT + if (!(dev_config->flags & SPI_DEVICE_NO_RETURN_RESULT)) { + dev->ret_queue = xQueueCreate(dev_config->queue_size, sizeof(spi_trans_priv_t)); + if (!dev->ret_queue) { + goto nomem; + } + } //We want to save a copy of the dev config in the dev struct. memcpy(&dev->cfg, dev_config, sizeof(spi_device_interface_config_t)); @@ -439,15 +451,17 @@ esp_err_t spi_bus_remove_device(spi_device_handle_t handle) //catch design errors and aren't meant to be triggered during normal operation. SPI_CHECK(uxQueueMessagesWaiting(handle->trans_queue)==0, "Have unfinished transactions", ESP_ERR_INVALID_STATE); SPI_CHECK(handle->host->cur_cs == DEV_NUM_MAX || handle->host->device[handle->host->cur_cs] != handle, "Have unfinished transactions", ESP_ERR_INVALID_STATE); - SPI_CHECK(uxQueueMessagesWaiting(handle->ret_queue)==0, "Have unfinished transactions", ESP_ERR_INVALID_STATE); + if (handle->ret_queue) { + SPI_CHECK(uxQueueMessagesWaiting(handle->ret_queue)==0, "Have unfinished transactions", ESP_ERR_INVALID_STATE); + } //return int spics_io_num = handle->cfg.spics_io_num; if (spics_io_num >= 0) spicommon_cs_free_io(spics_io_num); //Kill queues - vQueueDelete(handle->trans_queue); - vQueueDelete(handle->ret_queue); + if (handle->trans_queue) vQueueDelete(handle->trans_queue); + if (handle->ret_queue) vQueueDelete(handle->ret_queue); spi_bus_lock_unregister_dev(handle->dev_lock); assert(handle->host->device[handle->id] == handle); @@ -456,6 +470,19 @@ esp_err_t spi_bus_remove_device(spi_device_handle_t handle) return ESP_OK; } +esp_err_t spi_device_get_actual_freq(spi_device_handle_t handle, int* freq_khz) +{ + if ((spi_device_t*)handle == NULL || freq_khz == NULL) { + return ESP_ERR_INVALID_ARG; + } + + int dev_required_freq = ((spi_device_t*)handle)->cfg.clock_speed_hz; + int dev_duty_cycle = ((spi_device_t*)handle)->cfg.duty_cycle_pos; + *freq_khz = spi_get_actual_clock(esp_clk_apb_freq(), dev_required_freq, dev_duty_cycle); + + return ESP_OK; +} + int spi_get_actual_clock(int fapb, int hz, int duty_cycle) { return spi_hal_master_cal_clock(fapb, hz, duty_cycle); @@ -612,9 +639,13 @@ static void SPI_MASTER_ISR_ATTR spi_intr(void *arg) //cur_cs is changed to DEV_NUM_MAX here spi_post_trans(host); + + if (!(host->device[cs]->cfg.flags & SPI_DEVICE_NO_RETURN_RESULT)) { + //Return transaction descriptor. + xQueueSendFromISR(host->device[cs]->ret_queue, &host->cur_trans_buf, &do_yield); + } + // spi_bus_lock_bg_pause(bus_attr->lock); - //Return transaction descriptor. - xQueueSendFromISR(host->device[cs]->ret_queue, &host->cur_trans_buf, &do_yield); #ifdef CONFIG_PM_ENABLE //Release APB frequency lock esp_pm_lock_release(bus_attr->pm_lock); @@ -704,7 +735,9 @@ static SPI_MASTER_ISR_ATTR esp_err_t check_trans_valid(spi_device_handle_t handl SPI_CHECK(!is_half_duplex || !bus_attr->dma_enabled || !rx_enabled || !tx_enabled, "SPI half duplex mode does not support using DMA with both MOSI and MISO phases.", ESP_ERR_INVALID_ARG ); #endif #if !SOC_SPI_HD_BOTH_INOUT_SUPPORTED + //On these chips, HW doesn't support using both TX and RX phases when in halfduplex mode SPI_CHECK(!is_half_duplex || !tx_enabled || !rx_enabled, "SPI half duplex mode is not supported when both MOSI and MISO phases are enabled.", ESP_ERR_INVALID_ARG); + SPI_CHECK(!is_half_duplex || !trans_desc->length || !trans_desc->rxlength, "SPI half duplex mode is not supported when both MOSI and MISO phases are enabled.", ESP_ERR_INVALID_ARG); #endif //MOSI phase is skipped only when both tx_buffer and SPI_TRANS_USE_TXDATA are not set. SPI_CHECK(trans_desc->length != 0 || !tx_enabled, "trans tx_buffer should be NULL and SPI_TRANS_USE_TXDATA should be cleared to skip MOSI phase.", ESP_ERR_INVALID_ARG); @@ -840,6 +873,9 @@ esp_err_t SPI_MASTER_ATTR spi_device_get_trans_result(spi_device_handle_t handle spi_trans_priv_t trans_buf; SPI_CHECK(handle!=NULL, "invalid dev handle", ESP_ERR_INVALID_ARG); + //if SPI_DEVICE_NO_RETURN_RESULT is set, ret_queue will always be empty + SPI_CHECK(!(handle->cfg.flags & SPI_DEVICE_NO_RETURN_RESULT), "API not Supported!", ESP_ERR_NOT_SUPPORTED); + //use the interrupt, block until return r=xQueueReceive(handle->ret_queue, (void*)&trans_buf, ticks_to_wait); if (!r) { diff --git a/components/driver/spi_slave.c b/components/driver/spi_slave.c index 12d98d38f5..a07f83fb57 100644 --- a/components/driver/spi_slave.c +++ b/components/driver/spi_slave.c @@ -125,6 +125,11 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b #endif SPI_CHECK(slave_config->spics_io_num < 0 || GPIO_IS_VALID_GPIO(slave_config->spics_io_num), "spics pin invalid", ESP_ERR_INVALID_ARG); + //Check post_trans_cb status when `SPI_SLAVE_NO_RETURN_RESULT` flag is set. + if(slave_config->flags & SPI_SLAVE_NO_RETURN_RESULT) { + SPI_CHECK(slave_config->post_trans_cb != NULL, "use feature flag 'SPI_SLAVE_NO_RETURN_RESULT' but no post_trans_cb function sets", ESP_ERR_INVALID_ARG); + } + spi_chan_claimed=spicommon_periph_claim(host, "spi slave"); SPI_CHECK(spi_chan_claimed, "host already in use", ESP_ERR_INVALID_STATE); @@ -183,11 +188,17 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b //Create queues spihost[host]->trans_queue = xQueueCreate(slave_config->queue_size, sizeof(spi_slave_transaction_t *)); - spihost[host]->ret_queue = xQueueCreate(slave_config->queue_size, sizeof(spi_slave_transaction_t *)); - if (!spihost[host]->trans_queue || !spihost[host]->ret_queue) { + if (!spihost[host]->trans_queue) { ret = ESP_ERR_NO_MEM; goto cleanup; } + if(!(slave_config->flags & SPI_SLAVE_NO_RETURN_RESULT)) { + spihost[host]->ret_queue = xQueueCreate(slave_config->queue_size, sizeof(spi_slave_transaction_t *)); + if (!spihost[host]->ret_queue) { + ret = ESP_ERR_NO_MEM; + goto cleanup; + } + } int flags = bus_config->intr_flags | ESP_INTR_FLAG_INTRDISABLED; err = esp_intr_alloc(spicommon_irqsource_for_host(host), flags, spi_intr, (void *)spihost[host], &spihost[host]->intr); @@ -298,6 +309,9 @@ esp_err_t SPI_SLAVE_ATTR spi_slave_get_trans_result(spi_host_device_t host, spi_ BaseType_t r; SPI_CHECK(is_valid_host(host), "invalid host", ESP_ERR_INVALID_ARG); SPI_CHECK(spihost[host], "host not slave", ESP_ERR_INVALID_ARG); + //if SPI_SLAVE_NO_RETURN_RESULT is set, ret_queue will always be empty + SPI_CHECK(!(spihost[host]->cfg.flags & SPI_SLAVE_NO_RETURN_RESULT), "API not Supported!", ESP_ERR_NOT_SUPPORTED); + r = xQueueReceive(spihost[host]->ret_queue, (void *)trans_desc, ticks_to_wait); if (!r) return ESP_ERR_TIMEOUT; return ESP_OK; @@ -349,9 +363,10 @@ static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg) spicommon_dmaworkaround_req_reset(host->tx_dma_chan, spi_slave_restart_after_dmareset, host); } if (host->cfg.post_trans_cb) host->cfg.post_trans_cb(host->cur_trans); - //Okay, transaction is done. - //Return transaction descriptor. - xQueueSendFromISR(host->ret_queue, &host->cur_trans, &do_yield); + + if(!(host->cfg.flags & SPI_SLAVE_NO_RETURN_RESULT)) { + xQueueSendFromISR(host->ret_queue, &host->cur_trans, &do_yield); + } host->cur_trans = NULL; } if (use_dma) { diff --git a/components/driver/temperature_sensor.c b/components/driver/temperature_sensor.c index bb11e3148e..c0e0d9629a 100644 --- a/components/driver/temperature_sensor.c +++ b/components/driver/temperature_sensor.c @@ -185,7 +185,7 @@ esp_err_t temperature_sensor_get_celsius(temperature_sensor_handle_t tsens, floa ESP_RETURN_ON_FALSE(tsens->fsm == TEMP_SENSOR_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "tsens not enabled yet"); uint32_t tsens_out = temperature_sensor_ll_get_raw_value(); - ESP_LOGV(TAG, "tsens_out %d", tsens_out); + ESP_LOGV(TAG, "tsens_out %"PRIu32, tsens_out); *out_celsius = parse_temp_sensor_raw_value(tsens_out, tsens->tsens_attribute->offset); if (*out_celsius < tsens->tsens_attribute->range_min || *out_celsius > tsens->tsens_attribute->range_max) { diff --git a/components/driver/test/CMakeLists.txt b/components/driver/test/CMakeLists.txt index ae79c8d854..f609fd6ca1 100644 --- a/components/driver/test/CMakeLists.txt +++ b/components/driver/test/CMakeLists.txt @@ -1,5 +1,8 @@ idf_component_register(SRC_DIRS . param_test dac_dma_test PRIV_INCLUDE_DIRS include param_test/include - PRIV_REQUIRES cmock test_utils driver nvs_flash esp_serial_slave_link + PRIV_REQUIRES cmock test_utils driver nvs_flash esp_timer esp_adc esp_event esp_wifi) target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") + +# A local copy of idf-extra-components esp_serial_slave_link, for stabilities of the SDIO test +add_subdirectory(esp_serial_slave_link) diff --git a/components/driver/test/esp_serial_slave_link/CMakeLists.txt b/components/driver/test/esp_serial_slave_link/CMakeLists.txt new file mode 100644 index 0000000000..40ffefb5d9 --- /dev/null +++ b/components/driver/test/esp_serial_slave_link/CMakeLists.txt @@ -0,0 +1,11 @@ +set(srcs "essl.c" "essl_sdio.c" "essl_spi.c") +set(include "include") +set(priv_include "." "include/esp_serial_slave_link") +set(priv_req idf::sdmmc idf::driver) + +add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}") + +target_sources(${COMPONENT_LIB} PRIVATE "${srcs}") +target_include_directories(${COMPONENT_LIB} PUBLIC ${include}) +target_include_directories(${COMPONENT_LIB} PRIVATE ${priv_include}) +target_link_libraries(${COMPONENT_LIB} PRIVATE ${priv_req}) diff --git a/components/driver/test/esp_serial_slave_link/LICENSE b/components/driver/test/esp_serial_slave_link/LICENSE new file mode 100644 index 0000000000..d645695673 --- /dev/null +++ b/components/driver/test/esp_serial_slave_link/LICENSE @@ -0,0 +1,202 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/components/driver/test/esp_serial_slave_link/README.md b/components/driver/test/esp_serial_slave_link/README.md new file mode 100644 index 0000000000..f3b1e69ee7 --- /dev/null +++ b/components/driver/test/esp_serial_slave_link/README.md @@ -0,0 +1,16 @@ +# Espressif Serial Slave Link (ESSL) component + +This component used to reside in [esp-idf](https://github.com/espressif/esp-idf) project as its component. + +It's used on the HOST, to communicate with ESP chips as SLAVE via SDIO/SPI slave HD mode. + +The port layer (`essl_sdio.c/essl_spi.c`) are currently only written to run on ESP chips in master mode, but you may also modify them to work on more platforms. + +See more documentation: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/protocols/esp_serial_slave_link.html + +But it's going to be an idf-extra-component, and should be pulled-in by an idf_component.yml (See `examples/peripherals/sdio/host/main/idf_component.yml`). + +This folder is here for two purposes: + +1. Fix a version for tests, to make them stable and not affected by external factors such as network, changes in idf-extra-components, etc. +2. Build Programming Guide from ESP-IDF before ESSL actually have a place to put the documents. diff --git a/components/esp_serial_slave_link/essl.c b/components/driver/test/esp_serial_slave_link/essl.c similarity index 91% rename from components/esp_serial_slave_link/essl.c rename to components/driver/test/esp_serial_slave_link/essl.c index cfbe459f82..15944c205b 100644 --- a/components/esp_serial_slave_link/essl.c +++ b/components/driver/test/esp_serial_slave_link/essl.c @@ -1,16 +1,8 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include "essl.h" #include "essl_internal.h" diff --git a/components/esp_serial_slave_link/essl_internal.h b/components/driver/test/esp_serial_slave_link/essl_internal.h similarity index 69% rename from components/esp_serial_slave_link/essl_internal.h rename to components/driver/test/esp_serial_slave_link/essl_internal.h index 0070e53212..4c5c859e41 100644 --- a/components/esp_serial_slave_link/essl_internal.h +++ b/components/driver/test/esp_serial_slave_link/essl_internal.h @@ -1,18 +1,11 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once + #include #include diff --git a/components/esp_serial_slave_link/essl_sdio.c b/components/driver/test/esp_serial_slave_link/essl_sdio.c similarity index 99% rename from components/esp_serial_slave_link/essl_sdio.c rename to components/driver/test/esp_serial_slave_link/essl_sdio.c index 31f70313df..20c3278978 100644 --- a/components/esp_serial_slave_link/essl_sdio.c +++ b/components/driver/test/esp_serial_slave_link/essl_sdio.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/esp_serial_slave_link/essl_spi.c b/components/driver/test/esp_serial_slave_link/essl_spi.c similarity index 91% rename from components/esp_serial_slave_link/essl_spi.c rename to components/driver/test/esp_serial_slave_link/essl_spi.c index 4a6ece1a1a..93ddba0e78 100644 --- a/components/esp_serial_slave_link/essl_spi.c +++ b/components/driver/test/esp_serial_slave_link/essl_spi.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,8 +13,8 @@ #include "esp_private/periph_ctrl.h" #include "essl_internal.h" #include "essl_spi.h" -#include "essl_spi/esp32s2_defs.h" - +#include "hal/spi_types.h" +#include "hal/spi_ll.h" /** * Initialise device function list of SPI by this macro. @@ -51,51 +51,54 @@ typedef struct { } master_in; } essl_spi_context_t; - -static uint16_t get_hd_command(uint16_t cmd_i, uint32_t flags) +static uint16_t get_hd_command(spi_command_t cmd_t, uint32_t flags) { - //have no prefixes - if (cmd_i == CMD_HD_EN_QPI_REG) return cmd_i; - //doesn't support 4-line commands - if(flags & SPI_TRANS_MODE_QIO && flags & SPI_TRANS_MODE_DIOQIO_ADDR && - (cmd_i == CMD_HD_WR_END_REG || cmd_i == CMD_HD_INT0_REG || - cmd_i == CMD_HD_INT1_REG || cmd_i == CMD_HD_INT2_REG)) { - //the transaction will be sent in corresponding 1/2/4 bit mode, without address and data. - //the CMD will have no 0xA- prefix - return cmd_i; - } + spi_line_mode_t line_mode = { + .cmd_lines = 1, + }; if (flags & SPI_TRANS_MODE_DIO) { + line_mode.data_lines = 2; if (flags & SPI_TRANS_MODE_DIOQIO_ADDR) { - return cmd_i | CMD_HD_DIO_MODE; + line_mode.addr_lines = 2; } else { - return cmd_i | CMD_HD_DOUT_MODE; + line_mode.addr_lines = 1; } } else if (flags & SPI_TRANS_MODE_QIO) { + line_mode.data_lines = 4; if (flags & SPI_TRANS_MODE_DIOQIO_ADDR) { - return cmd_i | CMD_HD_QIO_MODE; + line_mode.addr_lines = 4; } else { - return cmd_i | CMD_HD_QOUT_MODE; + line_mode.addr_lines = 1; } + } else { + line_mode.data_lines = 1; + line_mode.addr_lines = 1; } - return cmd_i | CMD_HD_ONEBIT_MODE; + + return spi_ll_get_slave_hd_command(cmd_t, line_mode); } static int get_hd_dummy_bits(uint32_t flags) { - //dummy is always 4 cycles when dual or quad mode is enabled. Otherwise 8 cycles in normal mode. - if (flags & (SPI_TRANS_MODE_DIO | SPI_TRANS_MODE_QIO)) { - return 4; + spi_line_mode_t line_mode = {}; + + if (flags & SPI_TRANS_MODE_DIO) { + line_mode.data_lines = 2; + } else if (flags & SPI_TRANS_MODE_QIO) { + line_mode.data_lines = 4; } else { - return 8; + line_mode.data_lines = 1; } + + return spi_ll_get_slave_hd_dummy_bits(line_mode); } esp_err_t essl_spi_rdbuf(spi_device_handle_t spi, uint8_t *out_data, int addr, int len, uint32_t flags) { spi_transaction_ext_t t = { .base = { - .cmd = get_hd_command(CMD_HD_RDBUF_REG, flags), + .cmd = get_hd_command(SPI_CMD_HD_RDBUF, flags), .addr = addr % 72, .rxlength = len * 8, .rx_buffer = out_data, @@ -111,7 +114,7 @@ esp_err_t essl_spi_rdbuf_polling(spi_device_handle_t spi, uint8_t *out_data, int { spi_transaction_ext_t t = { .base = { - .cmd = get_hd_command(CMD_HD_RDBUF_REG, flags), + .cmd = get_hd_command(SPI_CMD_HD_RDBUF, flags), .addr = addr % 72, .rxlength = len * 8, .rx_buffer = out_data, @@ -127,7 +130,7 @@ esp_err_t essl_spi_wrbuf(spi_device_handle_t spi, const uint8_t *data, int addr, { spi_transaction_ext_t t = { .base = { - .cmd = get_hd_command(CMD_HD_WRBUF_REG, flags), + .cmd = get_hd_command(SPI_CMD_HD_WRBUF, flags), .addr = addr % 72, .length = len * 8, .tx_buffer = data, @@ -142,7 +145,7 @@ esp_err_t essl_spi_wrbuf_polling(spi_device_handle_t spi, const uint8_t *data, i { spi_transaction_ext_t t = { .base = { - .cmd = get_hd_command(CMD_HD_WRBUF_REG, flags), + .cmd = get_hd_command(SPI_CMD_HD_WRBUF, flags), .addr = addr % 72, .length = len * 8, .tx_buffer = data, @@ -157,7 +160,7 @@ esp_err_t essl_spi_rddma_seg(spi_device_handle_t spi, uint8_t *out_data, int seg { spi_transaction_ext_t t = { .base = { - .cmd = get_hd_command(CMD_HD_RDDMA_REG, flags), + .cmd = get_hd_command(SPI_CMD_HD_RDDMA, flags), .rxlength = seg_len * 8, .rx_buffer = out_data, .flags = flags | SPI_TRANS_VARIABLE_DUMMY, @@ -170,7 +173,7 @@ esp_err_t essl_spi_rddma_seg(spi_device_handle_t spi, uint8_t *out_data, int seg esp_err_t essl_spi_rddma_done(spi_device_handle_t spi, uint32_t flags) { spi_transaction_t end_t = { - .cmd = get_hd_command(CMD_HD_INT0_REG, flags), + .cmd = get_hd_command(SPI_CMD_HD_INT0, flags), .flags = flags, }; return spi_device_transmit(spi, &end_t); @@ -201,7 +204,7 @@ esp_err_t essl_spi_wrdma_seg(spi_device_handle_t spi, const uint8_t *data, int s { spi_transaction_ext_t t = { .base = { - .cmd = get_hd_command(CMD_HD_WRDMA_REG, flags), + .cmd = get_hd_command(SPI_CMD_HD_WRDMA, flags), .length = seg_len * 8, .tx_buffer = data, .flags = flags | SPI_TRANS_VARIABLE_DUMMY, @@ -214,7 +217,7 @@ esp_err_t essl_spi_wrdma_seg(spi_device_handle_t spi, const uint8_t *data, int s esp_err_t essl_spi_wrdma_done(spi_device_handle_t spi, uint32_t flags) { spi_transaction_t end_t = { - .cmd = get_hd_command(CMD_HD_WR_END_REG, flags), + .cmd = get_hd_command(SPI_CMD_HD_WR_END, flags), .flags = flags, }; return spi_device_transmit(spi, &end_t); @@ -243,7 +246,7 @@ esp_err_t essl_spi_wrdma(spi_device_handle_t spi, const uint8_t *data, int len, esp_err_t essl_spi_int(spi_device_handle_t spi, int int_n, uint32_t flags) { spi_transaction_t end_t = { - .cmd = get_hd_command(CMD_HD_INT0_REG + int_n, flags), + .cmd = get_hd_command(SPI_CMD_HD_INT0 + int_n, flags), .flags = flags, }; return spi_device_transmit(spi, &end_t); diff --git a/components/esp_serial_slave_link/include/esp_serial_slave_link/essl.h b/components/driver/test/esp_serial_slave_link/include/esp_serial_slave_link/essl.h similarity index 93% rename from components/esp_serial_slave_link/include/esp_serial_slave_link/essl.h rename to components/driver/test/esp_serial_slave_link/include/esp_serial_slave_link/essl.h index f03274a401..fca5e37aeb 100644 --- a/components/esp_serial_slave_link/include/esp_serial_slave_link/essl.h +++ b/components/driver/test/esp_serial_slave_link/include/esp_serial_slave_link/essl.h @@ -1,16 +1,8 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once diff --git a/components/esp_serial_slave_link/include/esp_serial_slave_link/essl_sdio.h b/components/driver/test/esp_serial_slave_link/include/esp_serial_slave_link/essl_sdio.h similarity index 93% rename from components/esp_serial_slave_link/include/esp_serial_slave_link/essl_sdio.h rename to components/driver/test/esp_serial_slave_link/include/esp_serial_slave_link/essl_sdio.h index c98ae0344f..8d9b7194c8 100644 --- a/components/esp_serial_slave_link/include/esp_serial_slave_link/essl_sdio.h +++ b/components/driver/test/esp_serial_slave_link/include/esp_serial_slave_link/essl_sdio.h @@ -1,16 +1,8 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ // ESP SDIO slave link used by the ESP host to communicate with ESP SDIO slave. diff --git a/components/esp_serial_slave_link/include/esp_serial_slave_link/essl_spi.h b/components/driver/test/esp_serial_slave_link/include/esp_serial_slave_link/essl_spi.h similarity index 96% rename from components/esp_serial_slave_link/include/esp_serial_slave_link/essl_spi.h rename to components/driver/test/esp_serial_slave_link/include/esp_serial_slave_link/essl_spi.h index 22721d17ec..21e9a92593 100644 --- a/components/esp_serial_slave_link/include/esp_serial_slave_link/essl_spi.h +++ b/components/driver/test/esp_serial_slave_link/include/esp_serial_slave_link/essl_spi.h @@ -1,16 +1,8 @@ -// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once diff --git a/components/esp_serial_slave_link/include/essl_spi/esp32c2_defs.h b/components/driver/test/esp_serial_slave_link/include/essl_spi/esp32c2_defs.h similarity index 90% rename from components/esp_serial_slave_link/include/essl_spi/esp32c2_defs.h rename to components/driver/test/esp_serial_slave_link/include/essl_spi/esp32c2_defs.h index 51abd189b2..0ef2000194 100644 --- a/components/esp_serial_slave_link/include/essl_spi/esp32c2_defs.h +++ b/components/driver/test/esp_serial_slave_link/include/essl_spi/esp32c2_defs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/esp_serial_slave_link/include/essl_spi/esp32h2_defs.h b/components/driver/test/esp_serial_slave_link/include/essl_spi/esp32c3_defs.h similarity index 89% rename from components/esp_serial_slave_link/include/essl_spi/esp32h2_defs.h rename to components/driver/test/esp_serial_slave_link/include/essl_spi/esp32c3_defs.h index 51abd189b2..a237137121 100644 --- a/components/esp_serial_slave_link/include/essl_spi/esp32h2_defs.h +++ b/components/driver/test/esp_serial_slave_link/include/essl_spi/esp32c3_defs.h @@ -1,10 +1,9 @@ /* - * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ - #pragma once // NOTE: From the view of master diff --git a/components/driver/test/esp_serial_slave_link/include/essl_spi/esp32s2_defs.h b/components/driver/test/esp_serial_slave_link/include/essl_spi/esp32s2_defs.h new file mode 100644 index 0000000000..d5f872f8a9 --- /dev/null +++ b/components/driver/test/esp_serial_slave_link/include/essl_spi/esp32s2_defs.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +// NOTE: From the view of master +#define CMD_HD_WRBUF_REG 0x01 +#define CMD_HD_RDBUF_REG 0x02 +#define CMD_HD_WRDMA_REG 0x03 +#define CMD_HD_RDDMA_REG 0x04 + +#define CMD_HD_ONEBIT_MODE 0x00 +#define CMD_HD_DOUT_MODE 0x10 +#define CMD_HD_QOUT_MODE 0x20 +#define CMD_HD_DIO_MODE 0x50 +#define CMD_HD_QIO_MODE 0xA0 + +#define CMD_HD_SEG_END_REG 0x05 +#define CMD_HD_EN_QPI_REG 0x06 +#define CMD_HD_WR_END_REG 0x07 +#define CMD_HD_INT0_REG 0x08 +#define CMD_HD_INT1_REG 0x09 +#define CMD_HD_INT2_REG 0x0A +#define CMD_HD_EX_QPI_REG 0xDD + +#define SPI_SLAVE_HD_BUFFER_SIZE 72 diff --git a/components/driver/test/esp_serial_slave_link/include/essl_spi/esp32s3_defs.h b/components/driver/test/esp_serial_slave_link/include/essl_spi/esp32s3_defs.h new file mode 100644 index 0000000000..a237137121 --- /dev/null +++ b/components/driver/test/esp_serial_slave_link/include/essl_spi/esp32s3_defs.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +// NOTE: From the view of master +#define CMD_HD_WRBUF_REG 0x01 +#define CMD_HD_RDBUF_REG 0x02 +#define CMD_HD_WRDMA_REG 0x03 +#define CMD_HD_RDDMA_REG 0x04 + +#define CMD_HD_ONEBIT_MODE 0x00 +#define CMD_HD_DOUT_MODE 0x10 +#define CMD_HD_QOUT_MODE 0x20 +#define CMD_HD_DIO_MODE 0x50 +#define CMD_HD_QIO_MODE 0xA0 + +#define CMD_HD_SEG_END_REG 0x05 +#define CMD_HD_EN_QPI_REG 0x06 +#define CMD_HD_WR_END_REG 0x07 +#define CMD_HD_INT0_REG 0x08 +#define CMD_HD_INT1_REG 0x09 +#define CMD_HD_INT2_REG 0x0A +#define CMD_HD_EX_QPI_REG 0xDD + +#define SPI_SLAVE_HD_BUFFER_SIZE 64 diff --git a/components/driver/test/include/test/test_common_spi.h b/components/driver/test/include/test/test_common_spi.h index 39d5bbdbbf..4c9d1ea1c2 100644 --- a/components/driver/test/include/test/test_common_spi.h +++ b/components/driver/test/include/test/test_common_spi.h @@ -298,6 +298,13 @@ void same_pin_func_sel(spi_bus_config_t bus, spi_device_interface_config_t dev, /** * This function is used to get tx_buffer used in dual-board test + * `master_send_buf` and `slave_send_buf` will be fulfilled with same random numbers with the seed of `seed`. + * + * @param seed Random number seed + * @param master_send_buf Master TX buffer + * @param slave_send_buf Slave TX buffer + * @param send_buf_size Buffer size */ void get_tx_buffer(uint32_t seed, uint8_t *master_send_buf, uint8_t *slave_send_buf, int send_buf_size); + #endif //_TEST_COMMON_SPI_H_ diff --git a/components/driver/test/test_adc2_with_wifi.c b/components/driver/test/test_adc2_with_wifi.c deleted file mode 100644 index a889592bb9..0000000000 --- a/components/driver/test/test_adc2_with_wifi.c +++ /dev/null @@ -1,343 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -/* - Tests for the adc2 device driver -*/ -#include "esp_system.h" -#include "unity.h" -#include "esp_system.h" -#include "esp_event.h" -#include "esp_wifi.h" -#include "esp_log.h" -#include "nvs_flash.h" -#include "test_utils.h" -#include "driver/gpio.h" -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "driver/gpio.h" -#define CONFIG_ADC_SUPPRESS_DEPRECATE_WARN 1 -#include "driver/adc.h" - -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C3, ESP32C2) - -static const char* TAG = "test_adc2"; - -#define DEFAULT_SSID "TEST_SSID" -#define DEFAULT_PWD "TEST_PASS" - -#if CONFIG_IDF_TARGET_ESP32 -#define ADC2_CHAN1 ADC2_CHANNEL_9 -#define ADC_WIDTH ADC_WIDTH_BIT_12 -#define ADC_HIGH 4095 -#define ADC_ERROR_THRES 20 -#elif CONFIG_IDF_TARGET_ESP32S2 -#define ADC2_CHAN1 ADC2_CHANNEL_7 -#define ADC_WIDTH ADC_WIDTH_BIT_13 -#define ADC_HIGH 8191 -#define ADC_ERROR_THRES 100 -#elif CONFIG_IDF_TARGET_ESP32C3 -#define ADC2_CHAN1 ADC2_CHANNEL_0 -#define ADC_WIDTH ADC_WIDTH_BIT_12 -#define ADC_HIGH 4095 -#define ADC_ERROR_THRES 100 -#elif CONFIG_IDF_TARGET_ESP32S3 -#define ADC2_CHAN1 ADC2_CHANNEL_0 -#define ADC_WIDTH ADC_WIDTH_BIT_12 -#define ADC_HIGH 4095 -#define ADC_ERROR_THRES 100 -#endif - -#define ADC_LOW 0 -#define TEST_NUM 8 - -#define MINUS_UNTIL_ZERO(a, b) ( ((a) > (b)) ? ((a)-(b)): 0) -#define TIME_REMAIN(start, now, timeout) ((start) >= (now) ? MINUS_UNTIL_ZERO((timeout), (now)-(start)) : -1) - - -static void wifi_event_handler(void* arg, esp_event_base_t event_base, - int32_t event_id, void* event_data) -{ - printf("ev_handle_called.\n"); - switch(event_id) { - case WIFI_EVENT_STA_START: - ESP_LOGI(TAG, "WIFI_EVENT_STA_START"); - //do not actually connect in test case - //; - break; - case WIFI_EVENT_STA_DISCONNECTED: - ESP_LOGI(TAG, "WIFI_EVENT_STA_DISCONNECTED"); - TEST_ESP_OK(esp_wifi_connect()); - break; - default: - break; - } - return ; -} - -static void ip_event_handler(void* arg, esp_event_base_t event_base, - int32_t event_id, void* event_data) -{ - ip_event_got_ip_t *event; - printf("ev_handle_called.\n"); - switch(event_id) { - case IP_EVENT_STA_GOT_IP: - event = (ip_event_got_ip_t*)event_data; - ESP_LOGI(TAG, "IP_EVENT_STA_GOT_IP"); - ESP_LOGI(TAG, "got ip:" IPSTR "\n", IP2STR(&event->ip_info.ip)); - break; - default: - break; - } - - return ; -} - -static int event_init(void) -{ - TEST_ESP_OK(esp_event_loop_create_default()); - ESP_ERROR_CHECK(esp_event_handler_register(WIFI_EVENT, ESP_EVENT_ANY_ID, &wifi_event_handler, NULL)); - ESP_ERROR_CHECK(esp_event_handler_register(IP_EVENT, ESP_EVENT_ANY_ID, &ip_event_handler, NULL)); - return ESP_OK; -} - -static int event_deinit(void) -{ - ESP_ERROR_CHECK(esp_event_handler_unregister(WIFI_EVENT, ESP_EVENT_ANY_ID, &wifi_event_handler)); - ESP_ERROR_CHECK(esp_event_handler_unregister(IP_EVENT, ESP_EVENT_ANY_ID, &ip_event_handler)); - return ESP_OK; -} - -TEST_CASE("adc2 work with wifi","[adc]") -{ - test_case_uses_tcpip(); - - //---------------------------------WiFi init-----------------------------------// - printf("nvs init\n"); - esp_err_t r = nvs_flash_init(); - if (r == ESP_ERR_NVS_NO_FREE_PAGES || r == ESP_ERR_NVS_NEW_VERSION_FOUND) { - printf("no free pages or nvs version mismatch, erase..\n"); - TEST_ESP_OK(nvs_flash_erase()); - r = nvs_flash_init(); - } - TEST_ESP_OK( r); - esp_netif_init(); - event_init(); - esp_netif_create_default_wifi_sta(); - - wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT(); - - /* Restrict the number of buffers to allocate to account for limited memory when running large number of tests */ - cfg.static_rx_buf_num = 2; - cfg.static_tx_buf_num = 2; - - TEST_ESP_OK(esp_wifi_init(&cfg)); - wifi_config_t wifi_config = { - .sta = { - .ssid = DEFAULT_SSID, - .password = DEFAULT_PWD - }, - }; - TEST_ESP_OK(esp_wifi_set_mode(WIFI_MODE_STA)); - TEST_ESP_OK(esp_wifi_set_config(WIFI_IF_STA, &wifi_config)); - - //---------------------------------ADC init-----------------------------------// - int read_raw; - int target_value; - gpio_num_t test_adc_io; - bool test_list[TEST_NUM] ={1, 1, 0, 0, 1, 0, 1, 0}; - - adc2_pad_get_io_num(ADC2_CHAN1, &test_adc_io); - TEST_ESP_OK(adc2_config_channel_atten(ADC2_CHAN1, ADC_ATTEN_DB_0)); - printf("test_adc_io is %d\n", test_adc_io); - - //---------------------------------GPIO init-----------------------------------// - gpio_config_t gpio_cfg = { - .pin_bit_mask = BIT64(test_adc_io), - .mode = GPIO_MODE_OUTPUT, - //for powersave reasons, the GPIO should not be floating, select pullup - .pull_up_en = true, - .pull_down_en = false, - .intr_type = GPIO_INTR_DISABLE, - }; - gpio_config(&gpio_cfg); - - for (int i = 0; i < TEST_NUM; i++) { - TEST_ESP_OK(gpio_set_level(test_adc_io, test_list[i])); - target_value = test_list[i] ? ADC_HIGH : ADC_LOW; - - /* ADC2 single read before WIFI start */ - TEST_ESP_OK(adc2_get_raw(ADC2_CHAN1, ADC_WIDTH, &read_raw)); - printf("Before WiFi starts, ADC read: %d (target_value: %d)\n", read_raw, target_value); - TEST_ASSERT_INT_WITHIN(ADC_ERROR_THRES, target_value, read_raw); - - /* ADC2 single read when WIFI is on */ - TEST_ESP_OK(esp_wifi_start()); - #if CONFIG_IDF_TARGET_ESP32 - TEST_ASSERT_EQUAL(adc2_get_raw(ADC2_CHAN1, ADC_WIDTH, &read_raw), ESP_ERR_TIMEOUT); - #elif SOC_ADC_ARBITER_SUPPORTED - esp_err_t ret; - int32_t start = xTaskGetTickCount(); - int32_t now; - int32_t remain_wait_ms = 0; - int32_t timeout = pdMS_TO_TICKS(10); - - do { - now = xTaskGetTickCount(); - remain_wait_ms = pdTICKS_TO_MS(TIME_REMAIN(start, now, timeout)); - - ret = adc2_get_raw(ADC2_CHAN1, ADC_WIDTH, &read_raw); - if (ret == ESP_OK) { - printf("When WiFi is ON, ADC read: %d (target_value: %d)\n", read_raw, target_value); - TEST_ASSERT_INT_WITHIN(ADC_ERROR_THRES, target_value, read_raw); - break; - } else if (ret == ESP_ERR_INVALID_STATE) { - continue; - } else { - TEST_ESP_OK(ret); - } - } while (remain_wait_ms); - #endif - - /* ADC2 single read after WIFI is off */ - TEST_ESP_OK(esp_wifi_stop()); - TEST_ESP_OK(adc2_get_raw(ADC2_CHAN1, ADC_WIDTH, &read_raw)); - printf("After WiFi is OFF, ADC read: %d (target_value: %d)\n", read_raw, target_value); - TEST_ASSERT_INT_WITHIN(ADC_ERROR_THRES, target_value, read_raw); - } - - TEST_ESP_OK(esp_wifi_deinit()); - event_deinit(); - nvs_flash_deinit(); - - TEST_IGNORE_MESSAGE("this test case is ignored due to the critical memory leak of esp_netif and event_loop."); -} - -#endif //#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C3, ESP32S3) - - -#ifdef CONFIG_IDF_TARGET_ESP32 - -#include "driver/adc.h" - -#define ADC1_CHANNEL_4_IO (32) -#define ADC_SAMPLE_RATE (36000) -#define ADC_TEST_CHANNEL ADC1_CHANNEL_4 - -static void adc_dma_init(void) -{ - adc_digi_init_config_t adc_dma_config = { - .max_store_buf_size = 1024, - .conv_num_each_intr = 256, - .adc1_chan_mask = 1 << ADC_TEST_CHANNEL, - .adc2_chan_mask = 0, - }; - TEST_ESP_OK(adc_digi_initialize(&adc_dma_config)); - - adc_digi_pattern_config_t adc_pattern = { - .atten = ADC_ATTEN_DB_0, - .channel = ADC_TEST_CHANNEL, - .unit = 0, - .bit_width = SOC_ADC_DIGI_MAX_BITWIDTH - }; - adc_digi_configuration_t dig_cfg = { - .conv_limit_en = 1, - .conv_limit_num = 250, - .sample_freq_hz = ADC_SAMPLE_RATE, - .conv_mode = ADC_CONV_SINGLE_UNIT_1, - .format = ADC_DIGI_OUTPUT_FORMAT_TYPE1, - .pattern_num = 1, - .adc_pattern = &adc_pattern - }; - TEST_ESP_OK(adc_digi_controller_configure(&dig_cfg)); - TEST_ESP_OK(adc_digi_start()); -} - -static void continuous_adc_test(void) -{ - uint16_t *adcReadBuffer = (uint16_t *)calloc(1024, sizeof(uint16_t)); - uint32_t bytesRead; - for (int loop = 0; loop < 10; loop++) { - for (int level = 0; level <= 1; level++) { - if (level == 0) { - gpio_set_pull_mode(ADC1_CHANNEL_4_IO, GPIO_PULLDOWN_ONLY); - } else { - gpio_set_pull_mode(ADC1_CHANNEL_4_IO, GPIO_PULLUP_ONLY); - } - vTaskDelay(200 / portTICK_PERIOD_MS); - // read data from adc, will block until buffer is full - adc_digi_read_bytes((uint8_t *)adcReadBuffer, 1024 * sizeof(uint16_t), &bytesRead, ADC_MAX_DELAY); - // calc average - int64_t adcSumValue = 0; - for (size_t i = 0; i < 1024; i++) { - adcSumValue += adcReadBuffer[i] & 0xfff; - } - int adcAvgValue = adcSumValue / 1024; - printf("adc average val: %d\n", adcAvgValue); - - if (level == 0) { - TEST_ASSERT_LESS_THAN(100, adcAvgValue); - } else { - TEST_ASSERT_GREATER_THAN(4000, adcAvgValue); - } - } - } - free(adcReadBuffer); -} - -static void adc_deinit(void) -{ - adc_digi_stop(); - TEST_ESP_OK(adc_digi_deinitialize()); -} - -TEST_CASE("adc1 and i2s work with wifi","[adc][ignore]") -{ - - adc_dma_init(); - //init wifi - printf("nvs init\n"); - esp_err_t r = nvs_flash_init(); - if (r == ESP_ERR_NVS_NO_FREE_PAGES || r == ESP_ERR_NVS_NEW_VERSION_FOUND) { - printf("no free pages or nvs version mismatch, erase..\n"); - TEST_ESP_OK(nvs_flash_erase()); - r = nvs_flash_init(); - } - TEST_ESP_OK(r); - esp_netif_init(); - event_init(); - esp_netif_create_default_wifi_sta(); - wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT(); - TEST_ESP_OK(esp_wifi_init(&cfg)); - wifi_config_t wifi_config = { - .sta = { - .ssid = DEFAULT_SSID, - .password = DEFAULT_PWD - }, - }; - TEST_ESP_OK(esp_wifi_set_mode(WIFI_MODE_STA)); - TEST_ESP_OK(esp_wifi_set_config(WIFI_IF_STA, &wifi_config)); - continuous_adc_test(); - //now start wifi - printf("wifi start...\n"); - TEST_ESP_OK(esp_wifi_start()); - //test reading during wifi on - continuous_adc_test(); - //wifi stop again - printf("wifi stop...\n"); - - TEST_ESP_OK( esp_wifi_stop() ); - - TEST_ESP_OK(esp_wifi_deinit()); - - event_deinit(); - - nvs_flash_deinit(); - continuous_adc_test(); - adc_deinit(); - printf("test passed...\n"); - TEST_IGNORE_MESSAGE("this test case is ignored due to the critical memory leak of esp_netif and event_loop."); -} -#endif diff --git a/components/driver/test/test_common_spi.c b/components/driver/test/test_common_spi.c index 9137253f10..0a3b7b940f 100644 --- a/components/driver/test/test_common_spi.c +++ b/components/driver/test/test_common_spi.c @@ -245,7 +245,7 @@ void get_tx_buffer(uint32_t seed, uint8_t *master_send_buf, uint8_t *slave_send_ { srand(seed); for (int i = 0; i < send_buf_size; i++) { - slave_send_buf[i] = rand(); - master_send_buf[i] = rand(); + slave_send_buf[i] = rand() % 256; + master_send_buf[i] = rand() % 256; } } diff --git a/components/driver/test/test_ledc.c b/components/driver/test/test_ledc.c index 6a3d386a5b..94b58667e5 100644 --- a/components/driver/test/test_ledc.c +++ b/components/driver/test/test_ledc.c @@ -611,6 +611,7 @@ TEST_CASE("LEDC timer pause and resume", "[ledc]") printf("reset ledc timer\n"); TEST_ESP_OK(ledc_timer_rst(test_speed_mode, LEDC_TIMER_0)); vTaskDelay(100 / portTICK_PERIOD_MS); + count = wave_count(1000); TEST_ASSERT_UINT32_WITHIN(5, count, 5000); tear_testbench(); } diff --git a/components/driver/test/test_rs485.c b/components/driver/test/test_rs485.c index b716d18da3..d2f0f5ad14 100644 --- a/components/driver/test/test_rs485.c +++ b/components/driver/test/test_rs485.c @@ -23,14 +23,20 @@ #define UART1_RTS_PIN (18) // Number of packets to be send during test -#define PACKETS_NUMBER (40) +#define PACKETS_NUMBER (30) // Wait timeout for uart driver -#define PACKET_READ_TICS (1000 / portTICK_PERIOD_MS) +#define PACKET_READ_TICS (2000 / portTICK_PERIOD_MS) +// This is for workarond to avoid master-slave syncronization issues +// when slave gets the "Master_started" signal with delay ~2-3 seconds +#define TEST_ALLOW_PROC_FAIL (10) +#define TEST_CHECK_PROC_FAIL(fails, threshold) TEST_ASSERT((fails * 100 / PACKETS_NUMBER) <= threshold) #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32H2) //No runners +static const char *TAG = "rs485_test"; + // The table for fast CRC16 calculation static const uint8_t crc_hi[] = { 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, @@ -160,7 +166,7 @@ static void rs485_init(void) .rx_flow_ctrl_thresh = 120, .source_clk = UART_SCLK_DEFAULT, }; - printf("RS485 port initialization...\r\n"); + ESP_LOGI(TAG, "RS485 port initialization..."); TEST_ESP_OK(uart_wait_tx_idle_polling(UART_NUM1)); // Configure UART1 parameters TEST_ESP_OK(uart_param_config(UART_NUM1, &uart_config)); @@ -199,9 +205,9 @@ static void rs485_slave(void) rs485_init(); uint8_t* slave_data = (uint8_t*) malloc(BUF_SIZE); uint16_t err_count = 0, good_count = 0; - printf("Start recieve loop.\r\n"); unity_send_signal("Slave_ready"); unity_wait_for_signal("Master_started"); + ESP_LOGI(TAG, "Start recieve loop."); for(int pack_count = 0; pack_count < PACKETS_NUMBER; pack_count++) { //Read slave_data from UART int len = uart_read_bytes(UART_NUM1, slave_data, BUF_SIZE, PACKET_READ_TICS); @@ -223,12 +229,12 @@ static void rs485_slave(void) err_count++; } } - printf("Test completed. Received packets = %d, errors = %d\r\n", good_count, err_count); + ESP_LOGI(TAG, "Test completed. Received packets = %d, errors = %d", good_count, err_count); // Wait for packet to be sent uart_wait_tx_done(UART_NUM1, PACKET_READ_TICS); free(slave_data); uart_driver_delete(UART_NUM1); - TEST_ASSERT(err_count < 2); + TEST_CHECK_PROC_FAIL(err_count, TEST_ALLOW_PROC_FAIL); } // Master test of multi device test case. @@ -243,7 +249,7 @@ static void rs485_master(void) // The master test case should be synchronized with slave unity_wait_for_signal("Slave_ready"); unity_send_signal("Master_started"); - printf("Start recieve loop.\r\n"); + ESP_LOGI(TAG, "Start recieve loop."); for(int i = 0; i < PACKETS_NUMBER; i++) { // Form random buffer with CRC16 buffer_fill_random(master_buffer, BUF_SIZE); @@ -276,8 +282,8 @@ static void rs485_master(void) free(master_buffer); free(slave_buffer); uart_driver_delete(UART_NUM1); - TEST_ASSERT(err_count <= 1); - printf("Test completed. Received packets = %d, errors = %d\r\n", (uint16_t)good_count, (uint16_t)err_count); + ESP_LOGI(TAG, "Test completed. Received packets = %d, errors = %d", good_count, err_count); + TEST_CHECK_PROC_FAIL(err_count, TEST_ALLOW_PROC_FAIL); } /* diff --git a/components/driver/test/test_sdio.c b/components/driver/test/test_sdio.c index 3e02bf7c18..669331dcde 100644 --- a/components/driver/test/test_sdio.c +++ b/components/driver/test/test_sdio.c @@ -5,15 +5,19 @@ */ #include "unity.h" -#include "esp_serial_slave_link/essl_sdio.h" -#include "driver/sdspi_host.h" #include "test_utils.h" #include "param_test.h" #include "esp_log.h" #include "esp_timer.h" -#include "driver/spi_common.h" #include "soc/soc_caps.h" #include "ccomp_timer.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + +#include "driver/spi_common.h" +#include "driver/sdspi_host.h" +#include "esp_serial_slave_link/essl_sdio.h" +#include "sdmmc_cmd.h" #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) diff --git a/components/driver/test/test_spi_master.c b/components/driver/test/test_spi_master.c index d62aa4c679..d6c4994073 100644 --- a/components/driver/test/test_spi_master.c +++ b/components/driver/test/test_spi_master.c @@ -17,20 +17,19 @@ #include "freertos/semphr.h" #include "freertos/queue.h" #include "unity.h" +#include "sdkconfig.h" #include "driver/spi_master.h" #include "driver/spi_slave.h" -#include "esp_heap_caps.h" -#include "esp_log.h" -#include "soc/spi_periph.h" -#include "test_utils.h" -#include "test/test_common_spi.h" +#include "driver/gpio.h" #include "soc/gpio_periph.h" -#include "sdkconfig.h" -#include "esp_private/cache_utils.h" #include "soc/soc_memory_layout.h" +#include "esp_private/cache_utils.h" #include "esp_private/spi_common_internal.h" #include "esp_private/esp_clk.h" +#include "esp_heap_caps.h" +#include "esp_log.h" #include "test_utils.h" +#include "test/test_common_spi.h" const static char TAG[] = "test_spi"; @@ -1458,3 +1457,119 @@ TEST_CASE("spi_speed", "[spi]") #endif // CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE #endif // !(CONFIG_SPIRAM) || (CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL >= 16384) + +//****************************************spi master add device test************************************// +//add dummy devices first +#if CONFIG_IDF_TARGET_ESP32 +#define DUMMY_CS_PINS() {25, 26, 27} +#else +#define DUMMY_CS_PINS() {0, 1, 4, 5, 8, 9} +#endif //CONFIG_IDF_TARGET_ESP32 + +#define CS_REAL_DEV SPI2_IOMUX_PIN_NUM_CS +#define TEST_TRANS_LEN 48 + +void test_add_device_master(void) +{ + spi_device_handle_t devs[SOC_SPI_MAX_CS_NUM] = {}; + uint8_t cs_pins[SOC_SPI_MAX_CS_NUM] = DUMMY_CS_PINS(); + + uint8_t master_sendbuf[TEST_TRANS_LEN] = {0}; + uint8_t master_recvbuf[TEST_TRANS_LEN] = {0}; + uint8_t master_expect[TEST_TRANS_LEN] = {0}; + + spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG(); + ESP_ERROR_CHECK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, SPI_DMA_CH_AUTO)); + + spi_device_interface_config_t dev_cfg = { + .clock_speed_hz = 1 * 1000 * 1000, + .queue_size = 3, + }; + + for (uint8_t i = 0; i < SOC_SPI_MAX_CS_NUM; i++) { + dev_cfg.spics_io_num = cs_pins[i]; + TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &devs[i])); + } + + spi_transaction_t trans = {}; + trans.length = sizeof(master_sendbuf) * 8; + trans.tx_buffer = master_sendbuf; + trans.rx_buffer = master_recvbuf; + + for (uint8_t i = 0; i < SOC_SPI_MAX_CS_NUM; i++) { + //1. add max dummy devices + //2. replace devs[i] as a real device, than start a transaction + //3. free devs[i] after transaction to release the real CS pin for using again by another dev, + //So it will loop to check every gpio_sigal one by one use one physical pin + spi_bus_remove_device(devs[i]); + dev_cfg.spics_io_num = CS_REAL_DEV; + TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &devs[i])); + + memset(master_recvbuf, 0, sizeof(master_recvbuf)); + get_tx_buffer(21, master_sendbuf, master_expect, TEST_TRANS_LEN); + + unity_send_signal("Master ready"); + unity_wait_for_signal("Slave ready"); + spi_device_transmit(devs[i], &trans); + + ESP_LOGI("Master", "dev %d communication:", i); + ESP_LOG_BUFFER_HEX("Tx", master_sendbuf, sizeof(master_sendbuf)); + // ESP_LOG_BUFFER_HEX("Rx", master_recvbuf, sizeof(master_recvbuf)); + spitest_cmp_or_dump(master_expect, master_recvbuf, TEST_TRANS_LEN); + + //swap self as a dummy device to free real cs line + spi_bus_remove_device(devs[i]); + dev_cfg.spics_io_num = cs_pins[i]; + TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &devs[i])); + } + + for (uint8_t i = 0; i < SOC_SPI_MAX_CS_NUM; i++) { + spi_bus_remove_device(devs[i]); + } + spi_bus_free(TEST_SPI_HOST); +} + +void test_add_device_slave(void) +{ + uint8_t slave_sendbuf[TEST_TRANS_LEN] = {0}; + uint8_t slave_recvbuf[TEST_TRANS_LEN] = {0}; + uint8_t slave_expect[TEST_TRANS_LEN] = {0}; + + spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG(); + spi_slave_interface_config_t slvcfg = { + .spics_io_num = CS_REAL_DEV, + .queue_size = 3, + }; +#if CONFIG_IDF_TARGET_ESP32 + //now esp32 runners use SPI3 pin group to test gpio matrix together on CI. + bus_cfg.miso_io_num = SPI3_IOMUX_PIN_NUM_MISO; + bus_cfg.mosi_io_num = SPI3_IOMUX_PIN_NUM_MOSI; + bus_cfg.sclk_io_num = SPI3_IOMUX_PIN_NUM_CLK; + slvcfg.spics_io_num = SPI3_IOMUX_PIN_NUM_CS; +#endif + TEST_ESP_OK(spi_slave_initialize(TEST_SPI_HOST, &bus_cfg, &slvcfg, SPI_DMA_CH_AUTO)); + + spi_slave_transaction_t slave_trans = {}; + slave_trans.length = sizeof(slave_sendbuf) * 8; + slave_trans.tx_buffer = slave_sendbuf; + slave_trans.rx_buffer = slave_recvbuf; + + for (uint8_t i = 0; i < SOC_SPI_MAX_CS_NUM; i++) { + memset(slave_recvbuf, 0, sizeof(slave_recvbuf)); + get_tx_buffer(21, slave_expect, slave_sendbuf, TEST_TRANS_LEN); + + unity_wait_for_signal("Master ready"); + unity_send_signal("Slave ready"); + spi_slave_transmit(TEST_SPI_HOST, &slave_trans, portMAX_DELAY); + + ESP_LOGI("Slave", "dev %d communication:", i); + ESP_LOG_BUFFER_HEX("Tx", slave_sendbuf, sizeof(slave_sendbuf)); + // ESP_LOG_BUFFER_HEX("Rx", slave_recvbuf, sizeof(slave_recvbuf)); + spitest_cmp_or_dump(slave_expect, slave_recvbuf, TEST_TRANS_LEN); + } + + spi_slave_free(TEST_SPI_HOST); + spi_bus_free(TEST_SPI_HOST); +} + +TEST_CASE_MULTIPLE_DEVICES("SPI_Master:Test multiple devices", "[spi_ms][test_env=Example_SPI_Multi_device]", test_add_device_master, test_add_device_slave); diff --git a/components/driver/test/test_spi_sio.c b/components/driver/test/test_spi_sio.c index 61fa57a729..37529441ee 100644 --- a/components/driver/test/test_spi_sio.c +++ b/components/driver/test/test_spi_sio.c @@ -84,7 +84,7 @@ TEST_CASE("SPI Single Board Test SIO", "[spi]") spi_transaction_t mst_trans; spi_slave_transaction_t slv_trans; - spi_slave_transaction_t* ret; + spi_slave_transaction_t *ret; for (int i = 0; i < 8; i ++) { int tlen = i * 2 + 1; @@ -143,123 +143,194 @@ TEST_CASE("SPI Single Board Test SIO", "[spi]") #endif //#if (TEST_SPI_PERIPH_NUM >= 2) -//TODO IDF-4455 -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3, ESP32S3, ESP32C2, ESP32H2) -//These tests are ESP32 only due to lack of runners /******************************************************************************** - * Test SIO Master & Slave + * Test SIO Master + * SIO Slave is not suported, and one unit test is limited to one feature, so,,, + * sio master test can be splited to singal-input and single-output + * + * for single-output: master slave + * cs-----cs ------------- cs + * clk----clk ------------- clk + * d------mosi------------- mosi + * q miso------------- miso + * master can get input on mosi pin after output finish in sio mode, but in this + * case, master can get no data from slave, so check assert on the slave. + * + * ------------------------------------------------------------------------------ + * for single-input: master slave + * cs-----cs ------------- cs + * clk----clk ------------- clk + * d-\ mosi------------- mosi + * q \\--miso------------- miso + * In this case, master can get input data from slave after output finish, but + * slave can get no data from master due to internal broke, besides output data + * from both master and slave on miso line will get conflict in master's output + * frame. ********************************************************************************/ -//if test_mosi is false, test on miso of slave, otherwise test on mosi of slave -void test_sio_master_round(bool test_mosi) -{ - spi_device_handle_t spi; - WORD_ALIGNED_ATTR uint8_t rx_buffer[320]; +#define TRANS_LEN 1024 +#define MAX_TRANS_BUFF 64 +#define TEST_NUM 8 - if (test_mosi) { - ESP_LOGI(MASTER_TAG, "======== TEST MOSI ==========="); - } else { - ESP_LOGI(MASTER_TAG, "======== TEST MISO ==========="); +WORD_ALIGNED_ATTR uint8_t sio_master_rx_buff[TRANS_LEN]; +WORD_ALIGNED_ATTR uint8_t sio_slave_rx_buff [TRANS_LEN]; + +void test_sio_master_trans(bool sio_master_in) +{ + spi_device_handle_t dev_0; + uint8_t *master_tx_max = heap_caps_calloc(TRANS_LEN * 2, 1, MALLOC_CAP_DMA); + TEST_ASSERT_NOT_NULL_MESSAGE(master_tx_max, "malloc failed, exit.\n"); + + // write somethin to a long buffer for test long transmition + for (uint16_t i = 0; i < TRANS_LEN; i++) { + master_tx_max[i] = i; + master_tx_max[TRANS_LEN * 2 - i - 1] = i; } spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG(); - if (!test_mosi) bus_cfg.mosi_io_num = bus_cfg.miso_io_num; + if (sio_master_in) { + // normally, spi read data from port Q and write data to port D + // test master input from port D (output default.), so link port D (normally named mosi) to miso pin. + bus_cfg.mosi_io_num = bus_cfg.miso_io_num; + printf("\n====================Test sio master input====================\n"); + } else { + printf("\n============Test sio master output, data checked by slave.=============\n"); + } bus_cfg.miso_io_num = -1; - TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, 0)); + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, SPI_DMA_CH_AUTO)); spi_device_interface_config_t dev_cfg = SPI_DEVICE_TEST_DEFAULT_CONFIG(); dev_cfg.flags = SPI_DEVICE_HALFDUPLEX | SPI_DEVICE_3WIRE; - dev_cfg.clock_speed_hz = 1*1000*1000; - TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &spi)); + dev_cfg.clock_speed_hz = 1 * 1000 * 1000; + TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &dev_0)); + printf("CS:CLK:MO:MI: %d\t%d\t%d\t%d\n", dev_cfg.spics_io_num, bus_cfg.sclk_io_num, bus_cfg.mosi_io_num, bus_cfg.miso_io_num); - for (int i = 0; i < 8; i ++) { - int tlen = i*2+1; - int rlen = 9-i; - spi_transaction_t t = { - .length = tlen*8, - .tx_buffer = spitest_master_send+i, - .rxlength = rlen*8, - .rx_buffer = rx_buffer+i, - }; - memset(rx_buffer, 0x66, sizeof(rx_buffer)); + unity_send_signal("Master ready"); + for (int i = 0; i < TEST_NUM; i ++) { + spi_transaction_t trans = {}; + if (sio_master_in) { + // master input only section + trans.rxlength = (i + 1) * 8 * 8; + // test a huge data for last transmition + if (i >= TEST_NUM - 1) { + trans.rxlength = TRANS_LEN * 8; + } + trans.rx_buffer = sio_master_rx_buff; + trans.length = 0; + trans.tx_buffer = NULL; + memset(sio_master_rx_buff, 0, sizeof(sio_master_rx_buff)); + } else { + // master output only section + trans.length = MAX_TRANS_BUFF / (i + 1) * 8; + // test a huge data for last transmition + if (i >= TEST_NUM - 1) { + trans.length = TRANS_LEN * 8; + } + trans.tx_buffer = master_tx_max; + trans.rxlength = 0; + trans.rx_buffer = NULL; + // use some differnt data + trans.tx_buffer += (i % 2) ? TRANS_LEN : 0; + } //get signal - unity_wait_for_signal("slave ready"); + unity_wait_for_signal("Slave ready"); - TEST_ESP_OK(spi_device_transmit(spi, &t)); - uint8_t* exp_ptr = spitest_slave_send+i; - ESP_LOG_BUFFER_HEXDUMP("master tx", t.tx_buffer, tlen, ESP_LOG_INFO); - ESP_LOG_BUFFER_HEXDUMP("exp tx", exp_ptr, rlen, ESP_LOG_INFO); - ESP_LOG_BUFFER_HEXDUMP("master rx", t.rx_buffer, rlen, ESP_LOG_INFO); - if (!test_mosi) { - TEST_ASSERT_EQUAL_HEX8_ARRAY(exp_ptr+tlen, t.rx_buffer, rlen); + TEST_ESP_OK(spi_device_transmit(dev_0, &trans)); + if (sio_master_in) { + ESP_LOG_BUFFER_HEXDUMP("master rx", trans.rx_buffer, trans.rxlength / 8, ESP_LOG_INFO); + TEST_ASSERT_EQUAL_HEX8_ARRAY(master_tx_max + i, trans.rx_buffer, trans.rxlength / 8); + } else { + printf("%d master output\n", trans.length / 8); + ESP_LOG_BUFFER_HEXDUMP("master tx", trans.tx_buffer, trans.length / 8, ESP_LOG_INFO); } } - master_free_device_bus(spi); + free(master_tx_max); + master_free_device_bus(dev_0); } -void test_sio_master(void) +void test_sio_slave_emulate(bool sio_master_in) { - test_sio_master_round(true); - unity_send_signal("master ready"); - test_sio_master_round(false); -} + uint8_t *slave_tx_max = heap_caps_calloc(TRANS_LEN * 2, 1, MALLOC_CAP_DMA); + TEST_ASSERT_NOT_NULL_MESSAGE(slave_tx_max, "malloc failed, exit.\n"); -void test_sio_slave_round(bool test_mosi) -{ - WORD_ALIGNED_ATTR uint8_t rx_buffer[320]; + // write somethin to a long buffer for test long transmition + for (uint16_t i = 0; i < TRANS_LEN; i++) { + slave_tx_max[i] = i; + slave_tx_max[TRANS_LEN * 2 - i - 1] = i; + } - if (test_mosi) { - ESP_LOGI(SLAVE_TAG, "======== TEST MOSI ==========="); + if (sio_master_in) { + printf("\n==================Test sio master input.================\n"); } else { - ESP_LOGI(SLAVE_TAG, "======== TEST MISO ==========="); + printf("\n==================Test sio master output.=================\n"); } spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG(); + spi_slave_interface_config_t slv_cfg = SPI_SLAVE_TEST_DEFAULT_CONFIG(); +#if CONFIG_IDF_TARGET_ESP32 + // esp32 use different pin for slave in current runner bus_cfg.mosi_io_num = spi_periph_signal[TEST_SLAVE_HOST].spid_iomux_pin; bus_cfg.miso_io_num = spi_periph_signal[TEST_SLAVE_HOST].spiq_iomux_pin; bus_cfg.sclk_io_num = spi_periph_signal[TEST_SLAVE_HOST].spiclk_iomux_pin; - spi_slave_interface_config_t slv_cfg = SPI_SLAVE_TEST_DEFAULT_CONFIG(); slv_cfg.spics_io_num = spi_periph_signal[TEST_SLAVE_HOST].spics0_iomux_pin; - TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &bus_cfg, &slv_cfg, 0)); +#endif + TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &bus_cfg, &slv_cfg, SPI_DMA_CH_AUTO)); + printf("CS:CLK:MO:MI: %d\t%d\t%d\t%d\n", slv_cfg.spics_io_num, bus_cfg.sclk_io_num, bus_cfg.mosi_io_num, bus_cfg.miso_io_num); - for (int i = 0; i < 8; i++) { - int tlen = 9-i; - int rlen = i*2+1; - spi_slave_transaction_t t = { - .length = (tlen+rlen)*8, - .tx_buffer = spitest_slave_send+i, - .rx_buffer = rx_buffer, - }; + unity_wait_for_signal("Master ready"); + for (int i = 0; i < TEST_NUM; i++) { + spi_slave_transaction_t trans = {}; + if (sio_master_in) { + // slave output only section + trans.length = (i + 1) * 8 * 8; + // test a huge data for last transmition + if (i >= TEST_NUM - 1) { + trans.length = TRANS_LEN * 8; + } + trans.tx_buffer = slave_tx_max + i; + trans.rx_buffer = NULL; + } else { + // slave input only section + trans.length = MAX_TRANS_BUFF / (i + 1) * 8; + // test a huge data for last transmition + if (i >= TEST_NUM - 1) { + trans.length = TRANS_LEN * 8; + } + trans.tx_buffer = NULL; + trans.rx_buffer = sio_slave_rx_buff; + memset(sio_slave_rx_buff, 0, sizeof(sio_slave_rx_buff)); + } - TEST_ESP_OK(spi_slave_queue_trans(TEST_SLAVE_HOST, &t, portMAX_DELAY)); + TEST_ESP_OK(spi_slave_queue_trans(TEST_SLAVE_HOST, &trans, portMAX_DELAY)); + unity_send_signal("Slave ready"); - ESP_LOG_BUFFER_HEXDUMP("slave tx", t.tx_buffer, tlen+rlen, ESP_LOG_INFO); + spi_slave_transaction_t *p_slave_ret; + TEST_ESP_OK(spi_slave_get_trans_result(TEST_SLAVE_HOST, &p_slave_ret, portMAX_DELAY)); - //send signal_idx - unity_send_signal("slave ready"); - - uint8_t *exp_ptr = spitest_master_send+i; - spi_slave_transaction_t* ret_t; - TEST_ESP_OK(spi_slave_get_trans_result(TEST_SLAVE_HOST, &ret_t, portMAX_DELAY)); - - ESP_LOG_BUFFER_HEXDUMP("exp tx", exp_ptr, tlen+rlen, ESP_LOG_INFO); - ESP_LOG_BUFFER_HEXDUMP("slave rx", t.rx_buffer, tlen+rlen, ESP_LOG_INFO); - if (test_mosi) { - TEST_ASSERT_EQUAL_HEX8_ARRAY(exp_ptr, t.rx_buffer, rlen); + if (sio_master_in) { + ESP_LOG_BUFFER_HEXDUMP("Slave tx", trans.tx_buffer, trans.length / 8, ESP_LOG_INFO); + } else { + ESP_LOG_BUFFER_HEXDUMP("Slave rx", trans.rx_buffer, trans.length / 8, ESP_LOG_INFO); + TEST_ASSERT_EQUAL_HEX8_ARRAY(slave_tx_max + TRANS_LEN * (i % 2), trans.rx_buffer, trans.length / 8); } } + free(slave_tx_max); spi_slave_free(TEST_SLAVE_HOST); } -void test_sio_slave(void) +void test_master_run(void) { - test_sio_slave_round(true); - unity_wait_for_signal("master ready"); - test_sio_slave_round(false); + test_sio_master_trans(false); + test_sio_master_trans(true); } -TEST_CASE_MULTIPLE_DEVICES("sio mode", "[spi][test_env=Example_SPI_Multi_device]", test_sio_master, test_sio_slave); -#endif //#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3, ESP32C2, ESP32H2) +void test_slave_run(void) +{ + test_sio_slave_emulate(false); + test_sio_slave_emulate(true); +} + +TEST_CASE_MULTIPLE_DEVICES("SPI_Master:Test_SIO_Mode_Multi_Board", "[spi_ms][test_env=Example_SPI_Multi_device]", test_master_run, test_slave_run); diff --git a/components/driver/test/test_spi_slave_hd.c b/components/driver/test/test_spi_slave_hd.c index 393811ebd0..9093644945 100644 --- a/components/driver/test/test_spi_slave_hd.c +++ b/components/driver/test/test_spi_slave_hd.c @@ -16,16 +16,14 @@ #include "soc/spi_periph.h" #include "driver/spi_master.h" #include "esp_serial_slave_link/essl_spi.h" - - -#if (TEST_SPI_PERIPH_NUM >= 2) -//These will be only enabled on chips with 2 or more SPI peripherals +#include "test/test_common_spi.h" #if SOC_SPI_SUPPORT_SLAVE_HD_VER2 #include "driver/spi_slave_hd.h" + +#if (TEST_SPI_PERIPH_NUM >= 2) //These will be only enabled on chips with 2 or more SPI peripherals + #include "esp_rom_gpio.h" -#include "unity.h" -#include "test/test_common_spi.h" #define TEST_DMA_MAX_SIZE 4092 #define TEST_BUFFER_SIZE 256 ///< buffer size of each wrdma buffer in fifo mode @@ -57,7 +55,6 @@ typedef struct { spi_slave_hd_data_t rx_data; } testhd_context_t; - static uint32_t get_hd_flags(void) { #if !defined(SLAVE_SUPPORT_QIO) @@ -595,13 +592,9 @@ TEST_CASE("test spi slave hd segment mode, master too long", "[spi][spi_slv_hd]" master_free_device_bus(spi); } -#endif //SOC_SPI_SUPPORT_SLAVE_HD_VER2 #endif //#if (TEST_SPI_PERIPH_NUM >= 2) - #if (TEST_SPI_PERIPH_NUM == 1) -#if SOC_SPI_SUPPORT_SLAVE_HD_VER2 -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) //These tests are for chips which only have 1 SPI controller /******************************************************************************** * Test By Master & Slave (2 boards) @@ -616,9 +609,6 @@ TEST_CASE("test spi slave hd segment mode, master too long", "[spi][spi_slv_hd]" * GND | GND | GND | * ********************************************************************************/ -#include "driver/spi_slave_hd.h" -#include "unity.h" -#include "test/test_common_spi.h" static void hd_master(void) { @@ -749,6 +739,148 @@ static void hd_slave(void) } TEST_CASE_MULTIPLE_DEVICES("SPI Slave HD: segment mode, master sends too long", "[spi_ms][test_env=Example_SPI_Multi_device]", hd_master, hd_slave); -#endif //!TEMPORARY_DISABLED_FOR_TARGETS(...) -#endif //#if SOC_SPI_SUPPORT_SLAVE_HD_VER2 #endif //#if (TEST_SPI_PERIPH_NUM == 1) + +/** + * TODO IDF-5483 + **/ +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2) + +#define BUF_SIZE 256 + +static void hd_master_quad(void){ + spi_bus_config_t bus_cfg = { + .miso_io_num = PIN_NUM_MISO, + .mosi_io_num = PIN_NUM_MOSI, + .sclk_io_num = PIN_NUM_CLK, + .quadwp_io_num = PIN_NUM_WP, + .quadhd_io_num = PIN_NUM_HD + }; + + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, SPI_DMA_CH_AUTO)); + + spi_device_handle_t spi; + spi_device_interface_config_t dev_cfg = SPI_DEVICE_TEST_DEFAULT_CONFIG(); + dev_cfg.flags = SPI_DEVICE_HALFDUPLEX; + dev_cfg.command_bits = 8; + dev_cfg.address_bits = 8; + dev_cfg.dummy_bits = 8; + dev_cfg.clock_speed_hz = 100 * 1000; + + TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &spi)); + + WORD_ALIGNED_ATTR uint8_t *master_send_buf = heap_caps_malloc(BUF_SIZE, MALLOC_CAP_DMA); + WORD_ALIGNED_ATTR uint8_t *master_recv_buf = heap_caps_calloc(BUF_SIZE, 1, MALLOC_CAP_DMA); + //This buffer is used for 2-board test and should be assigned totally the same as the ``hd_slave`` does. + WORD_ALIGNED_ATTR uint8_t *slave_send_buf = heap_caps_malloc(BUF_SIZE, MALLOC_CAP_DMA); + get_tx_buffer(199, master_send_buf, slave_send_buf, BUF_SIZE); + + unity_wait_for_signal("slave ready"); + essl_spi_wrdma(spi, master_send_buf, BUF_SIZE / 2, -1, SPI_TRANS_MODE_QIO); + + unity_wait_for_signal("slave ready"); + essl_spi_wrdma(spi, master_send_buf + BUF_SIZE / 2, BUF_SIZE / 2, -1, SPI_TRANS_MODE_QIO); + + unity_wait_for_signal("slave ready"); + essl_spi_rddma(spi, master_recv_buf, BUF_SIZE / 2, -1, SPI_TRANS_MODE_QIO); + + unity_wait_for_signal("slave ready"); + essl_spi_rddma(spi, master_recv_buf+ BUF_SIZE / 2, BUF_SIZE / 2, -1, SPI_TRANS_MODE_QIO); + + ESP_LOG_BUFFER_HEX("slave send", slave_send_buf, BUF_SIZE); + ESP_LOG_BUFFER_HEX("master recv", master_recv_buf, BUF_SIZE); + + TEST_ASSERT_EQUAL_HEX8_ARRAY(slave_send_buf, master_recv_buf, BUF_SIZE); + + free(master_recv_buf); + free(master_send_buf); + free(slave_send_buf); + + master_free_device_bus(spi); +} + +static void hd_slave_quad(void){ + + spi_bus_config_t bus_cfg = { + .miso_io_num = PIN_NUM_MISO, + .mosi_io_num = PIN_NUM_MOSI, + .sclk_io_num = PIN_NUM_CLK, + .quadwp_io_num = PIN_NUM_WP, + .quadhd_io_num = PIN_NUM_HD, + .max_transfer_sz = 14000 * 30 + }; + + spi_slave_hd_slot_config_t slave_hd_cfg = { + .spics_io_num = PIN_NUM_CS, + .dma_chan = SPI_DMA_CH_AUTO, + .flags = 0, + .mode = 0, + .command_bits = 8, + .address_bits = 8, + .dummy_bits = 8, + .queue_size = 10, + }; + TEST_ESP_OK(spi_slave_hd_init(TEST_SLAVE_HOST, &bus_cfg, &slave_hd_cfg)); + + WORD_ALIGNED_ATTR uint8_t *slave_send_buf = heap_caps_malloc(BUF_SIZE, MALLOC_CAP_DMA); + WORD_ALIGNED_ATTR uint8_t *slave_recv_buf = heap_caps_calloc(BUF_SIZE, 1, MALLOC_CAP_DMA); + //This buffer is used for 2-board test and should be assigned totally the same as the ``hd_master`` does. + WORD_ALIGNED_ATTR uint8_t *master_send_buf = heap_caps_malloc(BUF_SIZE, MALLOC_CAP_DMA); + get_tx_buffer(199, master_send_buf, slave_send_buf, BUF_SIZE); + + int trans_len = BUF_SIZE / 2; + spi_slave_hd_data_t slave_trans[4] = { + //recv, the buffer size should be aligned to 4 + { + .data = slave_recv_buf, + .len = (trans_len + 3) & (~3), + }, + { + .data = slave_recv_buf+BUF_SIZE/2, + .len = (trans_len + 3) & (~3), + }, + //send + { + .data = slave_send_buf, + .len = (trans_len + 3) & (~3), + }, + { + .data = slave_send_buf+BUF_SIZE/2, + .len = (trans_len + 3) & (~3), + }, + }; + + for (int i = 0; i < 2; i ++) { + TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SLAVE_HOST, SPI_SLAVE_CHAN_RX, &slave_trans[i], portMAX_DELAY)); + unity_send_signal("slave ready"); + } + for (int i = 2; i < 4; i ++) { + TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SLAVE_HOST, SPI_SLAVE_CHAN_TX, &slave_trans[i], portMAX_DELAY)); + unity_send_signal("slave ready"); + } + for (int i = 0; i < 2; i ++) { + spi_slave_hd_data_t *ret_trans; + TEST_ESP_OK(spi_slave_hd_get_trans_res(TEST_SLAVE_HOST, SPI_SLAVE_CHAN_RX, &ret_trans, portMAX_DELAY)); + } + for (int i = 2; i < 4; i ++) { + spi_slave_hd_data_t *ret_trans; + TEST_ESP_OK(spi_slave_hd_get_trans_res(TEST_SLAVE_HOST, SPI_SLAVE_CHAN_TX, &ret_trans, portMAX_DELAY)); + } + + ESP_LOG_BUFFER_HEX("master send", master_send_buf, BUF_SIZE); + ESP_LOG_BUFFER_HEX("slave recv", slave_recv_buf, BUF_SIZE); + + TEST_ASSERT_EQUAL_HEX8_ARRAY(master_send_buf, slave_recv_buf, BUF_SIZE); + + free(slave_recv_buf); + free(slave_send_buf); + free(master_send_buf); + + spi_slave_hd_deinit(TEST_SLAVE_HOST); +} + +TEST_CASE_MULTIPLE_DEVICES("SPI quad hd test ", "[spi_ms][test_env=Example_SPI_Quad_Multi_device]", hd_master_quad, hd_slave_quad); + +#endif // #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2) + +#endif //SOC_SPI_SUPPORT_SLAVE_HD_VER2 diff --git a/components/driver/test_apps/gpio/main/CMakeLists.txt b/components/driver/test_apps/gpio/main/CMakeLists.txt index c010006435..60cb6effa6 100644 --- a/components/driver/test_apps/gpio/main/CMakeLists.txt +++ b/components/driver/test_apps/gpio/main/CMakeLists.txt @@ -9,6 +9,10 @@ if(CONFIG_SOC_SDM_SUPPORTED) list(APPEND srcs "test_sigma_delta_legacy.c") endif() +if(CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED) + list(APPEND srcs "test_rtcio.c") +endif() + # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} diff --git a/components/driver/test_apps/gpio/main/test_gpio.c b/components/driver/test_apps/gpio/main/test_gpio.c index 4b0d6e150e..4fcb33db07 100644 --- a/components/driver/test_apps/gpio/main/test_gpio.c +++ b/components/driver/test_apps/gpio/main/test_gpio.c @@ -622,8 +622,10 @@ TEST_CASE("GPIO_mode_test", "[gpio]") // Outputs high level: w/ pull up, then must read high level; w/ pull down, then must read low level gpio_set_level(TEST_GPIO_EXT_OUT_IO, 1); gpio_set_pull_mode(TEST_GPIO_EXT_OUT_IO, GPIO_PULLUP_ONLY); + vTaskDelay(100 / portTICK_PERIOD_MS); TEST_ASSERT_EQUAL_INT_MESSAGE(1, gpio_get_level(TEST_GPIO_EXT_IN_IO), "direction GPIO_MODE_OUTPUT_OD with GPIO_PULLUP_ONLY set error, it outputs low level"); gpio_set_pull_mode(TEST_GPIO_EXT_OUT_IO, GPIO_PULLDOWN_ONLY); + vTaskDelay(100 / portTICK_PERIOD_MS); TEST_ASSERT_EQUAL_INT_MESSAGE(0, gpio_get_level(TEST_GPIO_EXT_IN_IO), "direction GPIO_MODE_OUTPUT_OD with GPIO_PULLDOWN_ONLY set error, it outputs high level"); // Outputs low level: must read low level gpio_set_level(TEST_GPIO_EXT_OUT_IO, 0); @@ -638,10 +640,12 @@ TEST_CASE("GPIO_mode_test", "[gpio]") #endif // Outputs high level: w/ pull up, then must read high level; w/ pull down, then must read low level gpio_set_level(TEST_GPIO_EXT_OUT_IO, 1); - gpio_set_pull_mode(TEST_GPIO_EXT_OUT_IO, GPIO_PULLUP_ONLY); - TEST_ASSERT_EQUAL_INT_MESSAGE(1, gpio_get_level(TEST_GPIO_EXT_IN_IO), "direction GPIO_MODE_INPUT_OUTPUT_OD with GPIO_PULLUP_ONLY set error, it outputs low level"); gpio_set_pull_mode(TEST_GPIO_EXT_OUT_IO, GPIO_PULLDOWN_ONLY); + vTaskDelay(100 / portTICK_PERIOD_MS); TEST_ASSERT_EQUAL_INT_MESSAGE(0, gpio_get_level(TEST_GPIO_EXT_IN_IO), "direction GPIO_MODE_INPUT_OUTPUT_OD with GPIO_PULLDOWN_ONLY set error, it outputs high level"); + gpio_set_pull_mode(TEST_GPIO_EXT_OUT_IO, GPIO_PULLUP_ONLY); + vTaskDelay(100 / portTICK_PERIOD_MS); + TEST_ASSERT_EQUAL_INT_MESSAGE(1, gpio_get_level(TEST_GPIO_EXT_IN_IO), "direction GPIO_MODE_INPUT_OUTPUT_OD with GPIO_PULLUP_ONLY set error, it outputs low level"); // Outputs low level: must read low level gpio_set_level(TEST_GPIO_EXT_OUT_IO, 0); gpio_set_pull_mode(TEST_GPIO_EXT_OUT_IO, GPIO_FLOATING); @@ -790,7 +794,7 @@ TEST_CASE_CI_IGNORE("GPIO_drive_capability_test", "[gpio]") #if SOC_USB_SERIAL_JTAG_SUPPORTED TEST_CASE("GPIO_input_and_output_of_USB_pins_test", "[gpio]") { - const int test_pins[] = {USB_DM_GPIO_NUM, USB_DM_GPIO_NUM}; + const int test_pins[] = {USB_DP_GPIO_NUM, USB_DM_GPIO_NUM}; gpio_config_t io_conf = { .intr_type = GPIO_INTR_DISABLE, .mode = GPIO_MODE_INPUT_OUTPUT, @@ -804,8 +808,8 @@ TEST_CASE("GPIO_input_and_output_of_USB_pins_test", "[gpio]") int pin = test_pins[i]; // test pin gpio_set_level(pin, 0); - // tested voltage is around 0v esp_rom_delay_us(10); + // tested voltage is around 0v TEST_ASSERT_EQUAL_INT_MESSAGE(0, gpio_get_level(pin), "get level error! the level should be low!"); gpio_set_level(pin, 1); esp_rom_delay_us(10); @@ -821,6 +825,23 @@ TEST_CASE("GPIO_input_and_output_of_USB_pins_test", "[gpio]") TEST_ASSERT_EQUAL_INT_MESSAGE(1, gpio_get_level(pin), "get level error! the level should be high!"); } } + +TEST_CASE("GPIO_USB_DP_pin_pullup_disable_test", "[gpio]") +{ + // This test ensures the USB D+ pin pull-up can be disabled + // The pull-up value of the D+ pin is controlled by the pin's pull-up value together with the USB pull-up value. + // If any one of the pull-up value is 1, the pin’s pull-up resistor will be enabled. + // USB D+ pull-up value is default to 1 (USB_SERIAL_JTAG_DP_PULLUP) + // Therefore, when D+ pin's pull-up value is set to 0, it will also clear USB D+ pull-up value to allow + // its full functionality as a normal gpio pin + gpio_config_t input_io = test_init_io(USB_DP_GPIO_NUM); + input_io.mode = GPIO_MODE_INPUT; + input_io.pull_up_en = 0; + input_io.pull_down_en = 1; + gpio_config(&input_io); + + TEST_ASSERT_EQUAL_INT(0, gpio_get_level(USB_DP_GPIO_NUM)); +} #endif //SOC_USB_SERIAL_JTAG_SUPPORTED // Ignored in CI because it needs manually connect TEST_GPIO_INPUT_LEVEL_LOW_PIN to 3.3v to wake up from light sleep diff --git a/components/driver/test/test_rtcio.c b/components/driver/test_apps/gpio/main/test_rtcio.c similarity index 87% rename from components/driver/test/test_rtcio.c rename to components/driver/test_apps/gpio/main/test_rtcio.c index 10cf1ffb0d..c6a3023309 100644 --- a/components/driver/test/test_rtcio.c +++ b/components/driver/test_apps/gpio/main/test_rtcio.c @@ -3,10 +3,6 @@ * * SPDX-License-Identifier: Apache-2.0 */ -/** - * About test environment UT_T1_GPIO: - * Please connect GPIO18 and GPIO19 - */ #include #include #include "esp_system.h" @@ -21,8 +17,6 @@ #include "esp_log.h" #include "soc/rtc_io_periph.h" -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3, ESP32C3, ESP32C2) - #define RTCIO_CHECK(condition) TEST_ASSERT_MESSAGE((condition == ESP_OK), "ret is not ESP_OK") #define RTCIO_VERIFY(condition, msg) TEST_ASSERT_MESSAGE((condition), msg) @@ -77,14 +71,41 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = { GPIO_NUM_20, //GPIO20 GPIO_NUM_21, //GPIO21 }; +#elif defined CONFIG_IDF_TARGET_ESP32S3 +#define TEST_GPIO_PIN_COUNT 21 +const int s_test_map[TEST_GPIO_PIN_COUNT] = { + // GPIO_NUM_0, //GPIO0 // Workaround: GPIO0 is strap pin, can not be used pullup/pulldown test. + GPIO_NUM_1, //GPIO1 + GPIO_NUM_2, //GPIO2 + GPIO_NUM_3, //GPIO3 + GPIO_NUM_4, //GPIO4 + GPIO_NUM_5, //GPIO5 + GPIO_NUM_6, //GPIO6 + GPIO_NUM_7, //GPIO7 + GPIO_NUM_8, //GPIO8 + GPIO_NUM_9, //GPIO9 + GPIO_NUM_10, //GPIO10 + GPIO_NUM_11, //GPIO11 + GPIO_NUM_12, //GPIO12 + GPIO_NUM_13, //GPIO13 + GPIO_NUM_14, //GPIO14 + GPIO_NUM_15, //GPIO15 + GPIO_NUM_16, //GPIO16 + GPIO_NUM_17, //GPIO17 + GPIO_NUM_18, //GPIO18 + GPIO_NUM_19, //GPIO19 + GPIO_NUM_20, //GPIO20 + GPIO_NUM_21, //GPIO21 +}; #endif /* * Test output/input function. */ -TEST_CASE("RTCIO input/output test", "[rtcio]") +TEST_CASE("RTCIO_input/output_test", "[rtcio]") { ESP_LOGI(TAG, "RTCIO input/output test"); + // init rtcio for (int i = 0; i < GPIO_PIN_COUNT; i++) { if (GPIO_IS_VALID_OUTPUT_GPIO(i) && rtc_gpio_is_valid_gpio(i)) { @@ -97,7 +118,7 @@ TEST_CASE("RTCIO input/output test", "[rtcio]") } for (int cnt = 0; cnt < TEST_COUNT; cnt++) { - uint32_t level = cnt % 2; + int level = cnt % 2; ESP_LOGI(TAG, "RTCIO output level %d", level); for (int i = 0; i < GPIO_PIN_COUNT; i++) { if (GPIO_IS_VALID_OUTPUT_GPIO(i) && rtc_gpio_is_valid_gpio(i)) { @@ -105,6 +126,7 @@ TEST_CASE("RTCIO input/output test", "[rtcio]") vTaskDelay(10 / portTICK_PERIOD_MS); if (rtc_gpio_get_level(i) != level) { ESP_LOGE(TAG, "RTCIO input/output test err, gpio%d", i); + TEST_FAIL(); } } } @@ -124,9 +146,10 @@ TEST_CASE("RTCIO input/output test", "[rtcio]") * Test pullup/pulldown function. * Note: extern circuit should not connect. */ -TEST_CASE("RTCIO pullup/pulldown test", "[rtcio]") +TEST_CASE("RTCIO_pullup/pulldown_test", "[rtcio]") { ESP_LOGI(TAG, "RTCIO pullup/pulldown test"); + // init rtcio for (int i = 0; i < TEST_GPIO_PIN_COUNT; i++) { int num = rtc_io_number_get(s_test_map[i]); @@ -140,7 +163,7 @@ TEST_CASE("RTCIO pullup/pulldown test", "[rtcio]") } for (int cnt = 0; cnt < TEST_COUNT; cnt++) { - uint32_t level = cnt % 2; + int level = cnt % 2; ESP_LOGI(TAG, "RTCIO pull level %d", level); for (int i = 0; i < TEST_GPIO_PIN_COUNT; i++) { int num = rtc_io_number_get(s_test_map[i]); @@ -155,6 +178,7 @@ TEST_CASE("RTCIO pullup/pulldown test", "[rtcio]") vTaskDelay(20 / portTICK_PERIOD_MS); if (rtc_gpio_get_level(s_test_map[i]) != level) { ESP_LOGE(TAG, "RTCIO pullup/pulldown test err, gpio%d", s_test_map[i]); + TEST_FAIL(); } } } @@ -174,9 +198,10 @@ TEST_CASE("RTCIO pullup/pulldown test", "[rtcio]") /* * Test output OD function. */ -TEST_CASE("RTCIO output OD test", "[rtcio]") +TEST_CASE("RTCIO_output_OD_test", "[rtcio]") { ESP_LOGI(TAG, "RTCIO output OD test"); + // init rtcio for (int i = 0; i < GPIO_PIN_COUNT; i++) { if (GPIO_IS_VALID_OUTPUT_GPIO(i) && rtc_gpio_is_valid_gpio(i)) { @@ -189,7 +214,7 @@ TEST_CASE("RTCIO output OD test", "[rtcio]") } for (int cnt = 0; cnt < TEST_COUNT; cnt++) { - uint32_t level = cnt % 2; + int level = cnt % 2; ESP_LOGI(TAG, "RTCIO output level %d", level); for (int i = 0; i < GPIO_PIN_COUNT; i++) { if (GPIO_IS_VALID_OUTPUT_GPIO(i) && rtc_gpio_is_valid_gpio(i)) { @@ -197,6 +222,7 @@ TEST_CASE("RTCIO output OD test", "[rtcio]") vTaskDelay(10 / portTICK_PERIOD_MS); if (rtc_gpio_get_level(i) != level) { ESP_LOGE(TAG, "RTCIO output OD test err, gpio%d", i); + TEST_FAIL(); } } } @@ -215,9 +241,10 @@ TEST_CASE("RTCIO output OD test", "[rtcio]") /* * Test rtcio hold function. */ -TEST_CASE("RTCIO output hold test", "[rtcio]") +TEST_CASE("RTCIO_output_hold_test", "[rtcio]") { ESP_LOGI(TAG, "RTCIO output hold test"); + // init rtcio for (int i = 0; i < GPIO_PIN_COUNT; i++) { if (GPIO_IS_VALID_OUTPUT_GPIO(i) && rtc_gpio_is_valid_gpio(i)) { @@ -240,11 +267,12 @@ TEST_CASE("RTCIO output hold test", "[rtcio]") vTaskDelay(10 / portTICK_PERIOD_MS); if (rtc_gpio_get_level(i) == 0) { ESP_LOGE(TAG, "RTCIO hold test err, gpio%d", i); + TEST_FAIL(); } } } - //unhold all rtcio. + // unhold all rtcio. for (int i = 0; i < GPIO_PIN_COUNT; i++) { if (GPIO_IS_VALID_OUTPUT_GPIO(i) && rtc_gpio_is_valid_gpio(i)) { RTCIO_CHECK( rtc_gpio_hold_dis(i) ); @@ -253,7 +281,7 @@ TEST_CASE("RTCIO output hold test", "[rtcio]") // check the unhold status for (int cnt = 0; cnt < 4; cnt++) { - uint32_t level = cnt % 2; + int level = cnt % 2; ESP_LOGI(TAG, "RTCIO output level %d", level); for (int i = 0; i < GPIO_PIN_COUNT; i++) { if (GPIO_IS_VALID_OUTPUT_GPIO(i) && rtc_gpio_is_valid_gpio(i)) { @@ -261,6 +289,7 @@ TEST_CASE("RTCIO output hold test", "[rtcio]") vTaskDelay(10 / portTICK_PERIOD_MS); if (rtc_gpio_get_level(i) != level) { ESP_LOGE(TAG, "RTCIO output OD test err, gpio%d", i); + TEST_FAIL(); } } } @@ -275,5 +304,3 @@ TEST_CASE("RTCIO output hold test", "[rtcio]") } ESP_LOGI(TAG, "RTCIO hold test over"); } - -#endif diff --git a/components/driver/test_apps/gptimer/main/CMakeLists.txt b/components/driver/test_apps/gptimer/main/CMakeLists.txt index 4170f3fd44..be6096026a 100644 --- a/components/driver/test_apps/gptimer/main/CMakeLists.txt +++ b/components/driver/test_apps/gptimer/main/CMakeLists.txt @@ -1,6 +1,9 @@ set(srcs "test_app_main.c" - "test_gptimer.c" - "test_gptimer_iram.c") + "test_gptimer.c") + +if(CONFIG_GPTIMER_ISR_IRAM_SAFE) + list(APPEND srcs "test_gptimer_iram.c") +endif() # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE diff --git a/components/driver/test_apps/gptimer/main/test_gptimer_iram.c b/components/driver/test_apps/gptimer/main/test_gptimer_iram.c index fcf3cce7d1..2ff59fc5fa 100644 --- a/components/driver/test_apps/gptimer/main/test_gptimer_iram.c +++ b/components/driver/test_apps/gptimer/main/test_gptimer_iram.c @@ -5,102 +5,58 @@ */ #include -#include "sdkconfig.h" -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "freertos/semphr.h" +#include #include "unity.h" +#include "unity_test_utils.h" +#include "esp_attr.h" #include "driver/gptimer.h" -#include "spi_flash_mmap.h" -#include "esp_flash.h" -#include "soc/soc_caps.h" - -#if CONFIG_GPTIMER_ISR_IRAM_SAFE - -typedef struct { - size_t buf_size; - uint8_t *buf; - size_t flash_addr; - size_t repeat_count; - SemaphoreHandle_t done_sem; -} read_task_arg_t; - -typedef struct { - size_t delay_time_us; - size_t repeat_count; -} block_task_arg_t; static bool IRAM_ATTR on_gptimer_alarm_cb(gptimer_handle_t timer, const gptimer_alarm_event_data_t *edata, void *user_ctx) { - block_task_arg_t *arg = (block_task_arg_t *)user_ctx; - esp_rom_delay_us(arg->delay_time_us); - arg->repeat_count++; + uint32_t *alarm_counts = (uint32_t *)user_ctx; + (*alarm_counts)++; return false; } -static void flash_read_task(void *varg) +static void IRAM_ATTR test_delay_post_cache_disable(void *args) { - read_task_arg_t *arg = (read_task_arg_t *)varg; - for (size_t i = 0; i < arg->repeat_count; i++) { - TEST_ESP_OK(esp_flash_read(NULL, arg->buf, arg->flash_addr, arg->buf_size)); - } - xSemaphoreGive(arg->done_sem); - vTaskDelete(NULL); + esp_rom_delay_us(1000); } -TEST_CASE("gptimer_iram_interrupt_safe", "[gptimer]") +TEST_CASE("gptimer_interrupt_iram_safe", "[gptimer]") { gptimer_handle_t gptimer = NULL; - const size_t size = 128; - uint8_t *buf = malloc(size); - TEST_ASSERT_NOT_NULL(buf); - SemaphoreHandle_t done_sem = xSemaphoreCreateBinary(); - TEST_ASSERT_NOT_NULL(done_sem); - read_task_arg_t read_arg = { - .buf_size = size, - .buf = buf, - .flash_addr = 0, - .repeat_count = 1000, - .done_sem = done_sem, - }; - - block_task_arg_t block_arg = { - .repeat_count = 0, - .delay_time_us = 100, - }; - gptimer_config_t timer_config = { .clk_src = GPTIMER_CLK_SRC_DEFAULT, .direction = GPTIMER_COUNT_UP, - .resolution_hz = 1 * 1000 * 1000, + .resolution_hz = 1 * 1000 * 1000, // 1MHz, 1 tick = 1us }; TEST_ESP_OK(gptimer_new_timer(&timer_config, &gptimer)); gptimer_event_callbacks_t cbs = { .on_alarm = on_gptimer_alarm_cb, }; + uint32_t alarm_counts = 0; + TEST_ESP_OK(gptimer_register_event_callbacks(gptimer, &cbs, &alarm_counts)); gptimer_alarm_config_t alarm_config = { .reload_count = 0, - .alarm_count = 120, + .alarm_count = 100, // 100us per alarm event .flags.auto_reload_on_alarm = true, }; TEST_ESP_OK(gptimer_set_alarm_action(gptimer, &alarm_config)); - TEST_ESP_OK(gptimer_register_event_callbacks(gptimer, &cbs, &block_arg)); TEST_ESP_OK(gptimer_enable(gptimer)); TEST_ESP_OK(gptimer_start(gptimer)); - xTaskCreatePinnedToCore(flash_read_task, "read_flash", 2048, &read_arg, 3, NULL, portNUM_PROCESSORS - 1); - // wait for task done - xSemaphoreTake(done_sem, portMAX_DELAY); - printf("alarm callback runs %d times\r\n", block_arg.repeat_count); - TEST_ASSERT_GREATER_THAN(1000, block_arg.repeat_count); + vTaskDelay(pdMS_TO_TICKS(10)); + + printf("disable flash cache and check the alarm events are still in working\r\n"); + for (int i = 0; i < 10; i++) { + unity_utils_run_cache_disable_stub(test_delay_post_cache_disable, NULL); + } + printf("alarm counts: %"PRIu32"\r\n", alarm_counts); + TEST_ASSERT_GREATER_THAN(150, alarm_counts); + // delete gptimer TEST_ESP_OK(gptimer_stop(gptimer)); TEST_ESP_OK(gptimer_disable(gptimer)); TEST_ESP_OK(gptimer_del_timer(gptimer)); - vSemaphoreDelete(done_sem); - free(buf); - // leave time for IDLE task to recycle deleted task - vTaskDelay(2); } - -#endif // CONFIG_GPTIMER_ISR_IRAM_SAFE diff --git a/components/driver/test_apps/gptimer/sdkconfig.defaults b/components/driver/test_apps/gptimer/sdkconfig.defaults index b308cb2ddd..3de1470382 100644 --- a/components/driver/test_apps/gptimer/sdkconfig.defaults +++ b/components/driver/test_apps/gptimer/sdkconfig.defaults @@ -1,2 +1,4 @@ CONFIG_FREERTOS_HZ=1000 CONFIG_ESP_TASK_WDT=n +# Disable nano printf, because we need to print the timer count in %llu format +CONFIG_NEWLIB_NANO_FORMAT=n diff --git a/components/driver/test_apps/i2s_test_apps/i2s/main/CMakeLists.txt b/components/driver/test_apps/i2s_test_apps/i2s/main/CMakeLists.txt index c7f16431cc..22bdc0d96d 100644 --- a/components/driver/test_apps/i2s_test_apps/i2s/main/CMakeLists.txt +++ b/components/driver/test_apps/i2s_test_apps/i2s/main/CMakeLists.txt @@ -4,4 +4,3 @@ set(srcs "test_app_main.c" idf_component_register(SRCS ${srcs} WHOLE_ARCHIVE) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/components/driver/test_apps/i2s_test_apps/i2s/main/test_i2s.c b/components/driver/test_apps/i2s_test_apps/i2s/main/test_i2s.c index 52cc31eed6..20d753fb64 100644 --- a/components/driver/test_apps/i2s_test_apps/i2s/main/test_i2s.c +++ b/components/driver/test_apps/i2s_test_apps/i2s/main/test_i2s.c @@ -6,6 +6,7 @@ #include #include +#include #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/queue.h" @@ -226,7 +227,7 @@ static void i2s_read_task(void *args) { while (task_run_flag) { ret = i2s_channel_read(rx_handle, recv_buf, 2000, &recv_size, 300); if (ret == ESP_ERR_TIMEOUT) { - printf("Read timeout count: %d\n", cnt++); + printf("Read timeout count: %"PRIu32"\n", cnt++); } } @@ -245,7 +246,7 @@ static void i2s_write_task(void *args) { while (task_run_flag) { ret = i2s_channel_write(tx_handle, send_buf, 2000, &send_size, 300); if (ret == ESP_ERR_TIMEOUT) { - printf("Write timeout count: %d\n", cnt++); + printf("Write timeout count: %"PRIu32"\n", cnt++); } } @@ -607,7 +608,7 @@ TEST_CASE("I2S_memory_leak_test", "[i2s]") TEST_ESP_OK(i2s_del_channel(rx_handle)); TEST_ASSERT(memory_left == esp_get_free_heap_size()); } - printf("\r\nHeap size after: %d\n", esp_get_free_heap_size()); + printf("\r\nHeap size after: %"PRIu32"\n", esp_get_free_heap_size()); } TEST_CASE("I2S_loopback_test", "[i2s]") @@ -750,7 +751,14 @@ static void i2s_test_common_sample_rate(i2s_chan_handle_t rx_chan, i2s_std_clk_c 32000, 44100, 48000, 64000, 88200, 96000, 128000, 144000, 196000}; int real_pulse = 0; - for (int i = 0; i < 15; i++) { + int case_cnt = 15; +#if SOC_I2S_HW_VERSION_2 + // Can't support a very high sample rate while using XTAL as clock source + if (clk_cfg->clk_src == I2S_CLK_SRC_XTAL) { + case_cnt = 9; + } +#endif + for (int i = 0; i < case_cnt; i++) { int expt_pulse = (int)((float)test_freq[i] * (TEST_I2S_PERIOD_MS / 1000.0)); clk_cfg->sample_rate_hz = test_freq[i]; TEST_ESP_OK(i2s_channel_reconfig_std_clock(rx_chan, clk_cfg)); @@ -762,7 +770,7 @@ static void i2s_test_common_sample_rate(i2s_chan_handle_t rx_chan, i2s_std_clk_c vTaskDelay(pdMS_TO_TICKS(TEST_I2S_PERIOD_MS)); TEST_ESP_OK(pcnt_unit_stop(pcnt_unit)); TEST_ESP_OK(pcnt_unit_get_count(pcnt_unit, &real_pulse)); - printf("[%d Hz] %d pulses, expected %d, err %d\n", test_freq[i], real_pulse, expt_pulse, real_pulse - expt_pulse); + printf("[%"PRIu32" Hz] %d pulses, expected %d, err %d\n", test_freq[i], real_pulse, expt_pulse, real_pulse - expt_pulse); TEST_ESP_OK(i2s_channel_disable(rx_chan)); // Check if the error between real pulse number and expected pulse number is within 1% TEST_ASSERT_INT_WITHIN(expt_pulse * 0.01, expt_pulse, real_pulse); @@ -788,6 +796,10 @@ TEST_CASE("I2S_default_PLL_clock_test", "[i2s]") TEST_ESP_OK(i2s_channel_init_std_mode(rx_handle, &std_cfg)); i2s_test_common_sample_rate(rx_handle, &std_cfg.clk_cfg); +#if SOC_I2S_HW_VERSION_2 + std_cfg.clk_cfg.clk_src = I2S_CLK_SRC_XTAL; + i2s_test_common_sample_rate(rx_handle, &std_cfg.clk_cfg); +#endif TEST_ESP_OK(i2s_del_channel(rx_handle)); } @@ -858,7 +870,7 @@ TEST_CASE("I2S_package_lost_test", "[i2s]") size_t bytes_read = 0; int i; for (i = 0; i < test_num; i++) { - printf("Testing %d Hz sample rate\n", test_freq[i]); + printf("Testing %"PRIu32" Hz sample rate\n", test_freq[i]); std_cfg.clk_cfg.sample_rate_hz = test_freq[i]; std_cfg.clk_cfg.sample_rate_hz = test_freq[i]; TEST_ESP_OK(i2s_channel_reconfig_std_clock(rx_handle, &std_cfg.clk_cfg)); @@ -870,7 +882,7 @@ TEST_CASE("I2S_package_lost_test", "[i2s]") } TEST_ESP_OK(i2s_channel_disable(rx_handle)); if (count > 0) { - printf("package lost detected at %d Hz\n", test_freq[i]); + printf("package lost detected at %"PRIu32" Hz\n", test_freq[i]); goto finish; } } diff --git a/examples/protocols/slip/slip_udp/CMakeLists.txt b/components/driver/test_apps/i2s_test_apps/i2s_tdm/CMakeLists.txt similarity index 86% rename from examples/protocols/slip/slip_udp/CMakeLists.txt rename to components/driver/test_apps/i2s_test_apps/i2s_tdm/CMakeLists.txt index 0a8c2f9ccd..4f993f8d1f 100644 --- a/examples/protocols/slip/slip_udp/CMakeLists.txt +++ b/components/driver/test_apps/i2s_test_apps/i2s_tdm/CMakeLists.txt @@ -3,4 +3,4 @@ cmake_minimum_required(VERSION 3.16) include($ENV{IDF_PATH}/tools/cmake/project.cmake) -project(slip_client) +project(i2s_tdm_full_duplex_test) diff --git a/components/driver/test_apps/i2s_test_apps/i2s_tdm/README.md b/components/driver/test_apps/i2s_test_apps/i2s_tdm/README.md new file mode 100644 index 0000000000..0eb37997ef --- /dev/null +++ b/components/driver/test_apps/i2s_test_apps/i2s_tdm/README.md @@ -0,0 +1,3 @@ +| Supported Targets | ESP32-C3 | ESP32-S3 | +| ----------------- | -------- | -------- | + diff --git a/components/driver/test_apps/i2s_test_apps/i2s_tdm/main/CMakeLists.txt b/components/driver/test_apps/i2s_test_apps/i2s_tdm/main/CMakeLists.txt new file mode 100644 index 0000000000..e86a24fe8e --- /dev/null +++ b/components/driver/test_apps/i2s_test_apps/i2s_tdm/main/CMakeLists.txt @@ -0,0 +1,4 @@ +idf_component_register(SRCS "test_app_main.c" "test_i2s_tdm_full_duplex.c" + INCLUDE_DIRS "." + WHOLE_ARCHIVE +) diff --git a/components/driver/test_apps/i2s_test_apps/i2s_tdm/main/test_app_main.c b/components/driver/test_apps/i2s_test_apps/i2s_tdm/main/test_app_main.c new file mode 100644 index 0000000000..ff68044bfe --- /dev/null +++ b/components/driver/test_apps/i2s_test_apps/i2s_tdm/main/test_app_main.c @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include "unity.h" +#include "unity_test_runner.h" +#include "esp_heap_caps.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + +#define TEST_MEMORY_LEAK_THRESHOLD (-300) + +static size_t before_free_8bit; +static size_t before_free_32bit; + +static void check_leak(size_t before_free, size_t after_free, const char *type) +{ + ssize_t delta = after_free - before_free; + printf("MALLOC_CAP_%s: Before %u bytes free, After %u bytes free (delta %d)\n", type, before_free, after_free, delta); + TEST_ASSERT_MESSAGE(delta >= TEST_MEMORY_LEAK_THRESHOLD, "memory leak"); +} + +void setUp(void) +{ + before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); +} + +void tearDown(void) +{ + size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); + check_leak(before_free_8bit, after_free_8bit, "8BIT"); + check_leak(before_free_32bit, after_free_32bit, "32BIT"); +} + +void app_main(void) +{ + unity_run_menu(); +} diff --git a/components/driver/test_apps/i2s_test_apps/i2s_tdm/main/test_i2s_tdm_full_duplex.c b/components/driver/test_apps/i2s_test_apps/i2s_tdm/main/test_i2s_tdm_full_duplex.c new file mode 100644 index 0000000000..3f1772a538 --- /dev/null +++ b/components/driver/test_apps/i2s_test_apps/i2s_tdm/main/test_i2s_tdm_full_duplex.c @@ -0,0 +1,326 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include +#include +#include "freertos/FreeRTOS.h" +#include "freertos/queue.h" +#include "freertos/task.h" +#include "esp_log.h" +#include "unity.h" +#include "unity_test_utils.h" +#include "driver/gpio.h" +#include "driver/i2s_tdm.h" + +static const char *TAG = "i2s_tdm_full_duplex_test"; + +#define TEST_I2S_FRAME_SIZE (128) +#define TEST_I2S_PACKET_COUNT (512) + +#define TEST_I2S_NUM (I2S_NUM_0) // ESP32-C3 has only I2S0 +#define TEST_I2S_BCK_IO (GPIO_NUM_4) +#define TEST_I2S_WS_IO (GPIO_NUM_5) +#define TEST_I2S_DO_IO (GPIO_NUM_6) +#define TEST_I2S_DI_IO (GPIO_NUM_7) // DI and DO gpio will be reversed on slave runner + +typedef struct { + TaskHandle_t maintask_handle; + QueueHandle_t tx_queue; + i2s_chan_handle_t tx_channel_handle; + i2s_data_bit_width_t tx_data_bit_width; + i2s_tdm_slot_mask_t tdm_slot_mask; +} test_i2s_tdm_write_task_args_t; + +typedef struct { + uint32_t *buffer; + uint32_t buffer_size; +} test_i2s_tdm_write_buffer_t; + +static void test_i2s_tdm_master_write_task(void *args) +{ + test_i2s_tdm_write_task_args_t *task_args = (test_i2s_tdm_write_task_args_t*)args; + + /* Allocate I2S tx buffer */ + uint32_t channel_count = 32 - __builtin_clz(task_args->tdm_slot_mask); + uint32_t tx_buffer_size = TEST_I2S_FRAME_SIZE * channel_count * (task_args->tx_data_bit_width / 8); + ESP_LOGI(TAG, "Allocating I2S TDM master tx buffer, size=%ld", tx_buffer_size); + uint32_t *tx_buffer = malloc(tx_buffer_size); + TEST_ASSERT(tx_buffer); + + uint32_t data_cnt = 0; + size_t bytes_written = 0; + ESP_LOGI(TAG, "I2S TDM master send start"); + TEST_ESP_OK(i2s_channel_enable(task_args->tx_channel_handle)); + while (xTaskNotifyWait(0, ULONG_MAX, NULL, 0) == pdFALSE) { // if main task sends terminate signal, exit the loop + /* Fill in the tx buffer */ + for (uint32_t i = 0; i < tx_buffer_size / sizeof(uint32_t); i ++) { + tx_buffer[i] = data_cnt; + data_cnt ++; + } + TEST_ESP_OK(i2s_channel_write(task_args->tx_channel_handle, tx_buffer, tx_buffer_size, + &bytes_written, portMAX_DELAY)); + TEST_ASSERT_EQUAL(tx_buffer_size, bytes_written); + } + ESP_LOGI(TAG, "I2S TDM master send stop"); + TEST_ESP_OK(i2s_channel_disable(task_args->tx_channel_handle)); + ESP_LOGI(TAG, "Freeing I2S TDM master tx buffer"); + free(tx_buffer); + + xTaskNotifyGive(task_args->maintask_handle); // notify main task that cleanup is done + vTaskSuspend(NULL); // wait to be deleted +} + +static void test_i2s_tdm_master(uint32_t sample_rate, i2s_data_bit_width_t bit_width, i2s_tdm_slot_mask_t slot_mask) +{ + i2s_chan_handle_t i2s_tdm_tx_handle = NULL; + i2s_chan_handle_t i2s_tdm_rx_handle = NULL; + + /* Create I2S tx and rx channels */ + i2s_chan_config_t i2s_channel_config = { + .id = TEST_I2S_NUM, + .role = I2S_ROLE_MASTER, + .dma_desc_num = 4, + .dma_frame_num = TEST_I2S_FRAME_SIZE, + .auto_clear = false + }; + TEST_ESP_OK(i2s_new_channel(&i2s_channel_config, &i2s_tdm_tx_handle, &i2s_tdm_rx_handle)); + + /* Configure channels to TDM mode */ + i2s_tdm_config_t i2s_tdm_config = { + .clk_cfg = I2S_TDM_CLK_DEFAULT_CONFIG(sample_rate), + .slot_cfg = I2S_TDM_PHILIP_SLOT_DEFAULT_CONFIG(bit_width, I2S_SLOT_MODE_STEREO, slot_mask), + .gpio_cfg = { + .mclk = GPIO_NUM_NC, + .bclk = TEST_I2S_BCK_IO, + .ws = TEST_I2S_WS_IO, + .dout = TEST_I2S_DO_IO, + .din = TEST_I2S_DI_IO + }, + }; + TEST_ESP_OK(i2s_channel_init_tdm_mode(i2s_tdm_tx_handle, &i2s_tdm_config)); + TEST_ESP_OK(i2s_channel_init_tdm_mode(i2s_tdm_rx_handle, &i2s_tdm_config)); + + /* Create TDM write task */ + TaskHandle_t subtask_handle = NULL; + test_i2s_tdm_write_task_args_t task_args = { + .tx_channel_handle = i2s_tdm_tx_handle, + .maintask_handle = xTaskGetCurrentTaskHandle(), + .tx_data_bit_width = bit_width, + .tdm_slot_mask = slot_mask + }; + xTaskCreate(test_i2s_tdm_master_write_task, "I2S TDM Write Task", 4096, &task_args, 5, &subtask_handle); + + /* Allocate I2S rx buffer */ + uint32_t channel_count = 32 - __builtin_clz(slot_mask); + uint32_t rx_buffer_size = channel_count * TEST_I2S_FRAME_SIZE * (bit_width / 8); + ESP_LOGI(TAG, "Allocating I2S TDM master rx buffer, size=%"PRIu32, rx_buffer_size); + uint32_t *rx_buffer = malloc(rx_buffer_size); + TEST_ASSERT(rx_buffer); + + uint8_t is_packet_valid = 0; + uint32_t good_packet_cnt = 0; + size_t bytes_read = 0; + ESP_LOGI(TAG, "I2S TDM master receive start"); + TEST_ESP_OK(i2s_channel_enable(i2s_tdm_rx_handle)); + for(uint32_t packet_cnt = 0; packet_cnt < TEST_I2S_PACKET_COUNT; packet_cnt ++) { + TEST_ESP_OK(i2s_channel_read(i2s_tdm_rx_handle, rx_buffer, rx_buffer_size, + &bytes_read, portMAX_DELAY)); + TEST_ASSERT_EQUAL(rx_buffer_size, bytes_read); + + /* Check for empty packet */ + if (rx_buffer[0] == 0) { // empty packet + if (is_packet_valid == 0) { // omit leading empty packets + packet_cnt = 0; + } else { + ESP_LOGW(TAG, "empty packet %"PRIu32, packet_cnt); + } + continue; + } + is_packet_valid = 1; + /* Check received packet */ + uint8_t is_good_packet = 1; + uint32_t last_value = rx_buffer[0]; + for (uint32_t j = 1; j < rx_buffer_size / sizeof(uint32_t); j ++) { + if (rx_buffer[j] == last_value + 1) { // increased by 1 + last_value = rx_buffer[j]; + } else { + is_good_packet = 0; + ESP_LOGW(TAG, "corrupted packet %"PRIu32, packet_cnt); + break; // corrupted packet + } + } + if (is_good_packet) { + good_packet_cnt ++; + } + } + + ESP_LOGI(TAG, "Send signal to terminate subtask"); + xTaskNotifyGive(subtask_handle); // notify subtask to exit + xTaskNotifyWait(0, ULONG_MAX, NULL, portMAX_DELAY); // wait subtask to do some cleanups + ESP_LOGI(TAG, "Deleting subtask"); + unity_utils_task_delete(subtask_handle); // delete subtask + + ESP_LOGI(TAG, "I2S TDM master receive stop"); + TEST_ESP_OK(i2s_channel_disable(i2s_tdm_rx_handle)); + + ESP_LOGI(TAG, "Freeing I2S TDM master rx buffer"); + free(rx_buffer); + ESP_LOGI(TAG, "Deleting i2s tx and rx channels"); + TEST_ESP_OK(i2s_del_channel(i2s_tdm_rx_handle)); + TEST_ESP_OK(i2s_del_channel(i2s_tdm_tx_handle)); + + if (good_packet_cnt < TEST_I2S_PACKET_COUNT-4) { // if there are enough good packets + ESP_LOGE(TAG, "Good packet count(%"PRIu32") less than threshold", good_packet_cnt); + TEST_FAIL(); + } else { + ESP_LOGI(TAG, "Good packet count: %"PRIu32, good_packet_cnt); + } +} + +static void test_i2s_tdm_slave(uint32_t sample_rate, i2s_data_bit_width_t bit_width, i2s_tdm_slot_mask_t slot_mask) +{ + i2s_chan_handle_t i2s_tdm_tx_handle = NULL; + i2s_chan_handle_t i2s_tdm_rx_handle = NULL; + + /* Create I2S tx and rx channels */ + i2s_chan_config_t i2s_channel_config = { + .id = TEST_I2S_NUM, + .role = I2S_ROLE_SLAVE, + .dma_desc_num = 4, + .dma_frame_num = TEST_I2S_FRAME_SIZE, + .auto_clear = false + }; + TEST_ESP_OK(i2s_new_channel(&i2s_channel_config, &i2s_tdm_tx_handle, &i2s_tdm_rx_handle)); + + /* Configure channels to TDM mode */ + i2s_tdm_config_t i2s_tdm_config = { + .clk_cfg = I2S_TDM_CLK_DEFAULT_CONFIG(sample_rate), + .slot_cfg = I2S_TDM_PHILIP_SLOT_DEFAULT_CONFIG(bit_width, I2S_SLOT_MODE_STEREO, slot_mask), + .gpio_cfg = { + .mclk = GPIO_NUM_NC, + .bclk = TEST_I2S_BCK_IO, + .ws = TEST_I2S_WS_IO, + .dout = TEST_I2S_DI_IO, + .din = TEST_I2S_DO_IO // on slave, swap DI and DO pin + }, + }; + if (sample_rate >= 96000) { + i2s_tdm_config.clk_cfg.bclk_div = 12; + } + TEST_ESP_OK(i2s_channel_init_tdm_mode(i2s_tdm_tx_handle, &i2s_tdm_config)); + TEST_ESP_OK(i2s_channel_init_tdm_mode(i2s_tdm_rx_handle, &i2s_tdm_config)); + + /* Allocate I2S rx buffer */ + uint32_t channel_count = 32 - __builtin_clz(slot_mask); + uint32_t rx_buffer_size = TEST_I2S_FRAME_SIZE * channel_count * (bit_width / 8); + ESP_LOGI(TAG, "Allocating I2S TDM slave buffer, size=%ld", rx_buffer_size); + uint32_t *rx_buffer = malloc(rx_buffer_size); + TEST_ASSERT(rx_buffer); + + ESP_LOGI(TAG, "I2S TDM slave receive & send start"); + TEST_ESP_OK(i2s_channel_enable(i2s_tdm_rx_handle)); + TEST_ESP_OK(i2s_channel_enable(i2s_tdm_tx_handle)); + uint32_t packet_cnt = 0; + size_t bytes_read = 0, bytes_written = 0; + while (packet_cnt < TEST_I2S_PACKET_COUNT) { + TEST_ESP_OK(i2s_channel_read(i2s_tdm_rx_handle, rx_buffer, rx_buffer_size, + &bytes_read, portMAX_DELAY)); + TEST_ASSERT_EQUAL(rx_buffer_size, bytes_read); + + TEST_ESP_OK(i2s_channel_write(i2s_tdm_tx_handle, rx_buffer, rx_buffer_size, + &bytes_written, portMAX_DELAY)); + TEST_ASSERT_EQUAL(rx_buffer_size, bytes_written); + if (rx_buffer[0]) { // packet is not empty + packet_cnt ++; + } + } + + /* Send empty buffers to flush DMA ringbuffer until timeout */ + memset(rx_buffer, 0, rx_buffer_size); + while (i2s_channel_write(i2s_tdm_tx_handle, rx_buffer, rx_buffer_size, + &bytes_written, pdMS_TO_TICKS(200)) != ESP_ERR_TIMEOUT); + + ESP_LOGI(TAG, "I2S TDM slave receive stop"); + TEST_ESP_OK(i2s_channel_disable(i2s_tdm_rx_handle)); + TEST_ESP_OK(i2s_channel_disable(i2s_tdm_tx_handle)); + + ESP_LOGI(TAG, "Freeing I2S TDM slave buffer"); + free(rx_buffer); + + ESP_LOGI(TAG, "Deleting i2s tx and rx channels"); + TEST_ESP_OK(i2s_del_channel(i2s_tdm_rx_handle)); + TEST_ESP_OK(i2s_del_channel(i2s_tdm_tx_handle)); +} + +static void test_i2s_tdm_master_48k_32bits_4slots(void) +{ + test_i2s_tdm_master(48000, I2S_DATA_BIT_WIDTH_32BIT, I2S_TDM_SLOT0 | I2S_TDM_SLOT1 | I2S_TDM_SLOT2 | I2S_TDM_SLOT3); +} + +static void test_i2s_tdm_slave_48k_32bits_4slots(void) +{ + test_i2s_tdm_slave(48000, I2S_DATA_BIT_WIDTH_32BIT, I2S_TDM_SLOT0 | I2S_TDM_SLOT1 | I2S_TDM_SLOT2 | I2S_TDM_SLOT3); +} + +TEST_CASE_MULTIPLE_DEVICES("I2S TDM full duplex multiple device test (48k, 32bits, 4slots)", "[I2S_TDM]", + test_i2s_tdm_master_48k_32bits_4slots, test_i2s_tdm_slave_48k_32bits_4slots); + + +static void test_i2s_tdm_master_48k_16bits_4slots(void) +{ + test_i2s_tdm_master(48000, I2S_DATA_BIT_WIDTH_16BIT, I2S_TDM_SLOT0 | I2S_TDM_SLOT1 | I2S_TDM_SLOT2 | I2S_TDM_SLOT3); +} + +static void test_i2s_tdm_slave_48k_16bits_4slots(void) +{ + test_i2s_tdm_slave(48000, I2S_DATA_BIT_WIDTH_16BIT, I2S_TDM_SLOT0 | I2S_TDM_SLOT1 | I2S_TDM_SLOT2 | I2S_TDM_SLOT3); +} + +TEST_CASE_MULTIPLE_DEVICES("I2S TDM full duplex multiple device test (48k, 16bits, 4slots)", "[I2S_TDM]", + test_i2s_tdm_master_48k_16bits_4slots, test_i2s_tdm_slave_48k_16bits_4slots); + + +static void test_i2s_tdm_master_48k_8bits_4slots(void) +{ + test_i2s_tdm_master(48000, I2S_DATA_BIT_WIDTH_8BIT, I2S_TDM_SLOT0 | I2S_TDM_SLOT1 | I2S_TDM_SLOT2 | I2S_TDM_SLOT3); +} + +static void test_i2s_tdm_slave_48k_8bits_4slots(void) +{ + test_i2s_tdm_slave(48000, I2S_DATA_BIT_WIDTH_8BIT, I2S_TDM_SLOT0 | I2S_TDM_SLOT1 | I2S_TDM_SLOT2 | I2S_TDM_SLOT3); +} + +TEST_CASE_MULTIPLE_DEVICES("I2S TDM full duplex multiple device test (48k, 8bits, 4slots)", "[I2S_TDM]", + test_i2s_tdm_master_48k_8bits_4slots, test_i2s_tdm_slave_48k_8bits_4slots); + + +static void test_i2s_tdm_master_48k_16bits_8slots(void) +{ + test_i2s_tdm_master(48000, I2S_DATA_BIT_WIDTH_16BIT, I2S_TDM_SLOT0 | I2S_TDM_SLOT1 | I2S_TDM_SLOT2 | I2S_TDM_SLOT3 | + I2S_TDM_SLOT4 | I2S_TDM_SLOT5 | I2S_TDM_SLOT6 | I2S_TDM_SLOT7); +} + +static void test_i2s_tdm_slave_48k_16bits_8slots(void) +{ + test_i2s_tdm_slave(48000, I2S_DATA_BIT_WIDTH_16BIT, I2S_TDM_SLOT0 | I2S_TDM_SLOT1 | I2S_TDM_SLOT2 | I2S_TDM_SLOT3 | + I2S_TDM_SLOT4 | I2S_TDM_SLOT5 | I2S_TDM_SLOT6 | I2S_TDM_SLOT7); +} + +TEST_CASE_MULTIPLE_DEVICES("I2S TDM full duplex multiple device test (48k, 16bits, 8slots)", "[I2S_TDM]", + test_i2s_tdm_master_48k_16bits_8slots, test_i2s_tdm_slave_48k_16bits_8slots); + + +static void test_i2s_tdm_master_96k_16bits_4slots(void) +{ + test_i2s_tdm_master(96000, I2S_DATA_BIT_WIDTH_16BIT, I2S_TDM_SLOT0 | I2S_TDM_SLOT1 | I2S_TDM_SLOT2 | I2S_TDM_SLOT3); +} + +static void test_i2s_tdm_slave_96k_16bits_8slots(void) +{ + test_i2s_tdm_slave(96000, I2S_DATA_BIT_WIDTH_16BIT, I2S_TDM_SLOT0 | I2S_TDM_SLOT1 | I2S_TDM_SLOT2 | I2S_TDM_SLOT3); +} + +TEST_CASE_MULTIPLE_DEVICES("I2S TDM full duplex multiple device test (96k, 16bits, 4slots)", "[I2S_TDM]", + test_i2s_tdm_master_96k_16bits_4slots, test_i2s_tdm_slave_96k_16bits_8slots); diff --git a/components/driver/test_apps/i2s_test_apps/i2s_tdm/pytest_i2s_tdm_full_duplex.py b/components/driver/test_apps/i2s_test_apps/i2s_tdm/pytest_i2s_tdm_full_duplex.py new file mode 100644 index 0000000000..1c5321a710 --- /dev/null +++ b/components/driver/test_apps/i2s_test_apps/i2s_tdm/pytest_i2s_tdm_full_duplex.py @@ -0,0 +1,41 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Unlicense OR CC0-1.0 +from typing import Tuple + +import pytest +from pytest_embedded import Dut + + +def run_multi_device_case(master: Dut, slave: Dut, case_name: str) -> None: + master.write(case_name) + slave.write(case_name) + + slave.expect(r'\t\(2\)\s+\".+\"') + slave.write('2') + master.expect(r'\t\(2\)\s+\".+\"') + master.write('1') + + master.expect_unity_test_output() + slave.expect_unity_test_output() + + master.expect_exact("Enter next test, or 'enter' to see menu") + slave.expect_exact("Enter next test, or 'enter' to see menu") + + +@pytest.mark.esp32s3 +@pytest.mark.esp32c3 +@pytest.mark.generic_multi_device +@pytest.mark.parametrize('count', [ + 2, +], indirect=True) +def test_i2s_tdm_full_duplex(dut: Tuple[Dut, Dut]) -> None: + master = dut[0] + slave = dut[1] + master.expect_exact('Press ENTER to see the list of tests') + slave.expect_exact('Press ENTER to see the list of tests') + + run_multi_device_case(master, slave, '"I2S TDM full duplex multiple device test (48k, 32bits, 4slots)"') + run_multi_device_case(master, slave, '"I2S TDM full duplex multiple device test (48k, 16bits, 4slots)"') + run_multi_device_case(master, slave, '"I2S TDM full duplex multiple device test (48k, 8bits, 4slots)"') + run_multi_device_case(master, slave, '"I2S TDM full duplex multiple device test (48k, 16bits, 8slots)"') + run_multi_device_case(master, slave, '"I2S TDM full duplex multiple device test (96k, 16bits, 4slots)"') diff --git a/components/driver/test_apps/i2s_test_apps/i2s_tdm/sdkconfig.defaults b/components/driver/test_apps/i2s_test_apps/i2s_tdm/sdkconfig.defaults new file mode 100644 index 0000000000..b308cb2ddd --- /dev/null +++ b/components/driver/test_apps/i2s_test_apps/i2s_tdm/sdkconfig.defaults @@ -0,0 +1,2 @@ +CONFIG_FREERTOS_HZ=1000 +CONFIG_ESP_TASK_WDT=n diff --git a/components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/main/CMakeLists.txt b/components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/main/CMakeLists.txt index fe200a444a..60f64e8760 100644 --- a/components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/main/CMakeLists.txt +++ b/components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/main/CMakeLists.txt @@ -3,4 +3,3 @@ set(srcs "test_app_main.c" idf_component_register(SRCS ${srcs} WHOLE_ARCHIVE) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/main/test_legacy_i2s.c b/components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/main/test_legacy_i2s.c index 4cfb4e5bab..1673c194fe 100644 --- a/components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/main/test_legacy_i2s.c +++ b/components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/main/test_legacy_i2s.c @@ -13,6 +13,7 @@ #include #include +#include #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/queue.h" @@ -444,7 +445,7 @@ TEST_CASE("I2S_TDM_loopback_test_with_master_tx_and_rx", "[i2s_legacy]") TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL)); TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config)); i2s_test_io_config(I2S_TEST_MODE_LOOPBACK); - printf("\r\nheap size: %d\n", esp_get_free_heap_size()); + printf("\r\nheap size: %"PRIu32"\n", esp_get_free_heap_size()); uint8_t *data_wr = (uint8_t *)malloc(sizeof(uint8_t) * 400); size_t i2s_bytes_write = 0; @@ -519,7 +520,7 @@ TEST_CASE("I2S_write_and_read_test_with_master_tx_and_slave_rx", "[i2s_legacy]") TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL)); TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config)); i2s_test_io_config(I2S_TEST_MODE_MASTER_TO_SLAVE); - printf("\r\nheap size: %d\n", esp_get_free_heap_size()); + printf("\r\nheap size: %"PRIu32"\n", esp_get_free_heap_size()); i2s_config_t slave_i2s_config = { .mode = I2S_MODE_SLAVE | I2S_MODE_RX, @@ -551,7 +552,7 @@ TEST_CASE("I2S_write_and_read_test_with_master_tx_and_slave_rx", "[i2s_legacy]") TEST_ESP_OK(i2s_driver_install(I2S_NUM_1, &slave_i2s_config, 0, NULL)); TEST_ESP_OK(i2s_set_pin(I2S_NUM_1, &slave_pin_config)); i2s_test_io_config(I2S_TEST_MODE_MASTER_TO_SLAVE); - printf("\r\nheap size: %d\n", esp_get_free_heap_size()); + printf("\r\nheap size: %"PRIu32"\n", esp_get_free_heap_size()); uint8_t *data_wr = (uint8_t *)malloc(sizeof(uint8_t) * 400); size_t i2s_bytes_write = 0; @@ -623,7 +624,7 @@ TEST_CASE("I2S_write_and_read_test_master_rx_and_slave_tx", "[i2s_legacy]") TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL)); TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config)); i2s_test_io_config(I2S_TEST_MODE_SLAVE_TO_MASTER); - printf("\r\nheap size: %d\n", esp_get_free_heap_size()); + printf("\r\nheap size: %"PRIu32"\n", esp_get_free_heap_size()); i2s_config_t slave_i2s_config = { .mode = I2S_MODE_SLAVE | I2S_MODE_TX, // Only RX @@ -655,7 +656,7 @@ TEST_CASE("I2S_write_and_read_test_master_rx_and_slave_tx", "[i2s_legacy]") TEST_ESP_OK(i2s_driver_install(I2S_NUM_1, &slave_i2s_config, 0, NULL)); TEST_ESP_OK(i2s_set_pin(I2S_NUM_1, &slave_pin_config)); i2s_test_io_config(I2S_TEST_MODE_SLAVE_TO_MASTER); - printf("\r\nheap size: %d\n", esp_get_free_heap_size()); + printf("\r\nheap size: %"PRIu32"\n", esp_get_free_heap_size()); uint8_t *data_wr = (uint8_t *)malloc(sizeof(uint8_t) * 400); size_t i2s_bytes_write = 0; @@ -896,7 +897,7 @@ static void i2s_test_common_sample_rate(i2s_port_t id) vTaskDelay(pdMS_TO_TICKS(TEST_I2S_PERIOD_MS)); TEST_ESP_OK(pcnt_unit_stop(pcnt_unit)); TEST_ESP_OK(pcnt_unit_get_count(pcnt_unit, &real_pulse)); - printf("[%d Hz] %d pulses, expected %d, err %d\n", test_freq[i], real_pulse, expt_pulse, real_pulse - expt_pulse); + printf("[%"PRIu32" Hz] %d pulses, expected %d, err %d\n", test_freq[i], real_pulse, expt_pulse, real_pulse - expt_pulse); // Check if the error between real pulse number and expected pulse number is within 1% TEST_ASSERT_INT_WITHIN(expt_pulse * 0.01, expt_pulse, real_pulse); } diff --git a/components/driver/test_apps/i2s_test_apps/test_inc/test_i2s.h b/components/driver/test_apps/i2s_test_apps/test_inc/test_i2s.h index cf346b3518..528a47e477 100644 --- a/components/driver/test_apps/i2s_test_apps/test_inc/test_i2s.h +++ b/components/driver/test_apps/i2s_test_apps/test_inc/test_i2s.h @@ -44,7 +44,7 @@ extern "C" { #define SLAVE_WS_IO 15 #define DATA_IN_IO 19 #define DATA_OUT_IO 18 -#elif CONFIG_IDF_TARGET_ESP32H2 +#elif CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6 #define MASTER_MCK_IO 0 #define MASTER_BCK_IO 4 #define MASTER_WS_IO 5 diff --git a/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c b/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c index c635e9d518..d877a1d661 100644 --- a/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c +++ b/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c @@ -27,14 +27,14 @@ #elif CONFIG_IDF_TARGET_ESP32S2 #define ADC_TEST_LOW_VAL 0 -#define ADC_TEST_LOW_THRESH 25 +#define ADC_TEST_LOW_THRESH 35 #define ADC_TEST_HIGH_VAL 8191 #define ADC_TEST_HIGH_THRESH 10 #elif CONFIG_IDF_TARGET_ESP32C3 #define ADC_TEST_LOW_VAL 0 -#define ADC_TEST_LOW_THRESH 50 +#define ADC_TEST_LOW_THRESH 60 //This is due to ADC2 accuracy is not as good as ADC1, and also we use weak pulldown #define ADC_TEST_HIGH_VAL 4095 #define ADC_TEST_HIGH_THRESH 10 @@ -48,17 +48,11 @@ #elif CONFIG_IDF_TARGET_ESP32C2 #define ADC_TEST_LOW_VAL 2147 -#define ADC_TEST_LOW_THRESH 50 +#define ADC_TEST_LOW_THRESH 100 #define ADC_TEST_HIGH_VAL 4095 #define ADC_TEST_HIGH_THRESH 0 -#elif CONFIG_IDF_TARGET_ESP32H2 -#define ADC_TEST_LOW_VAL 2147 -#define ADC_TEST_LOW_THRESH 50 - -#define ADC_TEST_HIGH_VAL 4095 -#define ADC_TEST_HIGH_THRESH 0 #endif //ADC Channels diff --git a/components/driver/test_apps/legacy_adc_driver/pytest_legacy_adc.py b/components/driver/test_apps/legacy_adc_driver/pytest_legacy_adc.py index 9718e7ecee..881f8e0f6b 100644 --- a/components/driver/test_apps/legacy_adc_driver/pytest_legacy_adc.py +++ b/components/driver/test_apps/legacy_adc_driver/pytest_legacy_adc.py @@ -10,7 +10,7 @@ from pytest_embedded import Dut @pytest.mark.esp32s3 @pytest.mark.esp32c3 @pytest.mark.esp32c2 -@pytest.mark.generic +@pytest.mark.adc @pytest.mark.parametrize( 'config', [ diff --git a/components/driver/test_apps/legacy_rmt_driver/main/CMakeLists.txt b/components/driver/test_apps/legacy_rmt_driver/main/CMakeLists.txt index 7acd36f508..f8bd38290a 100644 --- a/components/driver/test_apps/legacy_rmt_driver/main/CMakeLists.txt +++ b/components/driver/test_apps/legacy_rmt_driver/main/CMakeLists.txt @@ -3,4 +3,3 @@ set(srcs "test_app_main.c" idf_component_register(SRCS ${srcs} WHOLE_ARCHIVE) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/components/driver/test_apps/legacy_rmt_driver/main/test_legacy_rmt.c b/components/driver/test_apps/legacy_rmt_driver/main/test_legacy_rmt.c index 35d1e1f79d..6e7e67ecdc 100644 --- a/components/driver/test_apps/legacy_rmt_driver/main/test_legacy_rmt.c +++ b/components/driver/test_apps/legacy_rmt_driver/main/test_legacy_rmt.c @@ -13,8 +13,8 @@ #include "esp_log.h" #include "esp_cpu.h" #include "unity.h" +#include "unity_test_utils.h" #include "esp_rom_gpio.h" - #include "ir_tools.h" #include "driver/rmt.h" @@ -295,7 +295,7 @@ static void do_nec_tx_rx(uint32_t flags) // build NEC codes cmd = 0x20; while (cmd <= 0x30) { - ESP_LOGI(TAG, "Send command 0x%x to address 0x%x", cmd, addr); + ESP_LOGI(TAG, "Send command 0x%"PRIx32" to address 0x%"PRIx32, cmd, addr); // Send new key code TEST_ESP_OK(s_ir_builder->build_frame(s_ir_builder, addr, cmd)); TEST_ESP_OK(s_ir_builder->get_result(s_ir_builder, &items, &length)); @@ -315,7 +315,7 @@ static void do_nec_tx_rx(uint32_t flags) length /= 4; // one RMT = 4 Bytes if (s_ir_parser->input(s_ir_parser, items, length) == ESP_OK) { if (s_ir_parser->get_scan_code(s_ir_parser, &addr, &cmd, &repeat) == ESP_OK) { - ESP_LOGI(TAG, "Scan Code %s --- addr: 0x%04x cmd: 0x%04x", repeat ? "(repeat)" : "", addr, cmd); + ESP_LOGI(TAG, "Scan Code %s --- addr: 0x%04"PRIx32" cmd: 0x%04"PRIx32, repeat ? "(repeat)" : "", addr, cmd); } } vRingbufferReturnItem(rb, (void *) items); @@ -397,7 +397,7 @@ TEST_CASE("RMT TX stop", "[rmt]") vTaskDelay(pdMS_TO_TICKS(1000)); // build NEC codes - ESP_LOGI(TAG, "Plan to send command 0x%x~0x%x to address 0x%x", cmd, cmd + count, addr); + ESP_LOGI(TAG, "Plan to send command 0x%"PRIx32"~0x%"PRIx32" to address 0x%"PRIx32, cmd, cmd + count, addr); for (int i = 0; i <= count; i++) { TEST_ESP_OK(s_ir_builder->build_frame(s_ir_builder, addr, cmd)); cmd++; @@ -417,7 +417,7 @@ TEST_CASE("RMT TX stop", "[rmt]") length /= 4; // one RMT = 4 Bytes if (s_ir_parser->input(s_ir_parser, frames, length) == ESP_OK) { if (s_ir_parser->get_scan_code(s_ir_parser, &addr, &cmd, &repeat) == ESP_OK) { - ESP_LOGI(TAG, "Scan Code %s --- addr: 0x%04x cmd: 0x%04x", repeat ? "(repeat)" : "", addr, cmd); + ESP_LOGI(TAG, "Scan Code %s --- addr: 0x%04"PRIx32"cmd: 0x%04"PRIx32, repeat ? "(repeat)" : "", addr, cmd); num++; } } @@ -527,12 +527,14 @@ TEST_CASE("RMT TX simultaneously", "[rmt]") TEST_ESP_OK(rmt_wait_tx_done(channel0, portMAX_DELAY)); TEST_ESP_OK(rmt_wait_tx_done(channel1, portMAX_DELAY)); - ESP_LOGI(TAG, "tx_end_time0=%u, tx_end_time1=%u", tx_end_time0, tx_end_time1); + ESP_LOGI(TAG, "tx_end_time0=%"PRIu32", tx_end_time1=%"PRIu32, tx_end_time0, tx_end_time1); TEST_ASSERT_LESS_OR_EQUAL_UINT32(2000, tx_end_time1 - tx_end_time0); TEST_ESP_OK(rmt_remove_channel_from_group(channel0)); TEST_ESP_OK(rmt_remove_channel_from_group(channel1)); + rmt_register_tx_end_callback(NULL, NULL); + TEST_ESP_OK(rmt_driver_uninstall(channel0)); TEST_ESP_OK(rmt_driver_uninstall(channel1)); @@ -568,7 +570,7 @@ TEST_CASE("RMT TX loop", "[rmt]") // register callback functions, invoked when tx loop count to ceiling rmt_register_tx_end_callback(rmt_tx_loop_end, NULL); // build NEC codes - ESP_LOGI(TAG, "Send command 0x%x to address 0x%x", cmd, addr); + ESP_LOGI(TAG, "Send command 0x%"PRIx32" to address 0x%"PRIx32, cmd, addr); // Send new key code TEST_ESP_OK(s_ir_builder->build_frame(s_ir_builder, addr, cmd)); TEST_ESP_OK(s_ir_builder->get_result(s_ir_builder, &items, &length)); @@ -582,7 +584,7 @@ TEST_CASE("RMT TX loop", "[rmt]") if (s_ir_parser->input(s_ir_parser, items, length) == ESP_OK) { if (s_ir_parser->get_scan_code(s_ir_parser, &addr, &cmd, &repeat) == ESP_OK) { count++; - ESP_LOGI(TAG, "Scan Code %s --- addr: 0x%04x cmd: 0x%04x", repeat ? "(repeat)" : "", addr, cmd); + ESP_LOGI(TAG, "Scan Code %s --- addr: 0x%04"PRIx32" cmd: 0x%04"PRIx32, repeat ? "(repeat)" : "", addr, cmd); } } vRingbufferReturnItem(rb, (void *) items); @@ -593,6 +595,42 @@ TEST_CASE("RMT TX loop", "[rmt]") } TEST_ASSERT_EQUAL(10, count); + rmt_register_tx_end_callback(NULL, NULL); rmt_clean_testbench(tx_channel, rx_channel); } #endif + +static void IRAM_ATTR test_delay_post_cache_disable(void *args) +{ + esp_rom_delay_us(10000); +} + +TEST_CASE("RMT Interrupt IRAM Safe", "[rmt]") +{ + rmt_config_t tx = { + .channel = RMT_CHANNEL_0, + .gpio_num = 0, + .mem_block_num = 1, + .clk_div = 40, + .rmt_mode = RMT_MODE_TX, + }; + TEST_ESP_OK(rmt_config(&tx)); + TEST_ESP_OK(rmt_set_source_clk(tx.channel, RMT_BASECLK_APB)); + // install interrupt with IRAM safe + TEST_ESP_OK(rmt_driver_install(tx.channel, 0, ESP_INTR_FLAG_IRAM)); + + // send a large buffer, ensure the RMT hardware is still in work when we disable the flash cache afterwords + rmt_item32_t items[256] = {}; + for (int i = 0; i < 256; i++) { + items[i].level0 = 0; + items[i].duration0 = 1; + items[i].level1 = 1; + items[i].duration1 = 1; + } + rmt_write_items(RMT_CHANNEL_0, items, 256, false); + + unity_utils_run_cache_disable_stub(test_delay_post_cache_disable, NULL); + + TEST_ESP_OK(rmt_wait_tx_done(RMT_CHANNEL_0, portMAX_DELAY)); + TEST_ESP_OK(rmt_driver_uninstall(RMT_CHANNEL_0)); +} diff --git a/components/driver/test_apps/mcpwm/main/CMakeLists.txt b/components/driver/test_apps/mcpwm/main/CMakeLists.txt index 1a38f86ffa..69804189bb 100644 --- a/components/driver/test_apps/mcpwm/main/CMakeLists.txt +++ b/components/driver/test_apps/mcpwm/main/CMakeLists.txt @@ -16,4 +16,3 @@ endif() # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} WHOLE_ARCHIVE) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/components/driver/test_apps/mcpwm/main/test_mcpwm_cap.c b/components/driver/test_apps/mcpwm/main/test_mcpwm_cap.c index 2a6dd37943..911f2e8dcc 100644 --- a/components/driver/test_apps/mcpwm/main/test_mcpwm_cap.c +++ b/components/driver/test_apps/mcpwm/main/test_mcpwm_cap.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include +#include #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/event_groups.h" @@ -101,6 +102,9 @@ TEST_CASE("mcpwm_capture_ext_gpio", "[mcpwm]") uint32_t cap_value[2] = {0}; TEST_ESP_OK(mcpwm_capture_channel_register_event_callbacks(pps_channel, &cbs, cap_value)); + printf("enable capture channel\r\n"); + TEST_ESP_OK(mcpwm_capture_channel_enable(pps_channel)); + printf("enable and start capture timer\r\n"); TEST_ESP_OK(mcpwm_capture_timer_enable(cap_timer)); TEST_ESP_OK(mcpwm_capture_timer_start(cap_timer)); @@ -110,12 +114,13 @@ TEST_CASE("mcpwm_capture_ext_gpio", "[mcpwm]") vTaskDelay(pdMS_TO_TICKS(100)); gpio_set_level(cap_gpio, 0); vTaskDelay(pdMS_TO_TICKS(100)); - printf("capture value: Pos=%u, Neg=%u\r\n", cap_value[0], cap_value[1]); + printf("capture value: Pos=%"PRIu32", Neg=%"PRIu32"\r\n", cap_value[0], cap_value[1]); // Capture timer is clocked from APB by default uint32_t clk_src_res = esp_clk_apb_freq(); TEST_ASSERT_UINT_WITHIN(100000, clk_src_res / 10, cap_value[1] - cap_value[0]); printf("uninstall capture channel and timer\r\n"); + TEST_ESP_OK(mcpwm_capture_channel_disable(pps_channel)); TEST_ESP_OK(mcpwm_del_capture_channel(pps_channel)); TEST_ESP_OK(mcpwm_capture_timer_disable(cap_timer)); TEST_ESP_OK(mcpwm_del_capture_timer(cap_timer)); @@ -153,12 +158,17 @@ TEST_CASE("mcpwm_capture_software_catch", "[mcpwm]") test_soft_catch_user_data_t test_callback_data = {}; TEST_ESP_OK(mcpwm_new_capture_channel(cap_timer, &cap_chan_config, &cap_channel)); + TEST_ESP_ERR(ESP_ERR_INVALID_STATE, mcpwm_capture_channel_trigger_soft_catch(cap_channel)); + printf("register event callback for capture channel\r\n"); mcpwm_capture_event_callbacks_t cbs = { .on_cap = soft_cap_callback, }; TEST_ESP_OK(mcpwm_capture_channel_register_event_callbacks(cap_channel, &cbs, &test_callback_data)); + printf("enable capture channel\r\n"); + TEST_ESP_OK(mcpwm_capture_channel_enable(cap_channel)); + printf("enable and start capture timer\r\n"); TEST_ESP_OK(mcpwm_capture_timer_enable(cap_timer)); TEST_ESP_OK(mcpwm_capture_timer_start(cap_timer)); @@ -178,6 +188,7 @@ TEST_CASE("mcpwm_capture_software_catch", "[mcpwm]") TEST_ASSERT_UINT_WITHIN(80000, clk_src_res / 100, delta); printf("uninstall capture channel and timer\r\n"); + TEST_ESP_OK(mcpwm_capture_channel_disable(cap_channel)); TEST_ESP_OK(mcpwm_capture_timer_disable(cap_timer)); TEST_ESP_OK(mcpwm_del_capture_channel(cap_channel)); TEST_ESP_OK(mcpwm_del_capture_timer(cap_timer)); @@ -210,6 +221,7 @@ TEST_CASE("mcpwm_capture_timer_sync_phase_lock", "[mcpwm]") .sync_src = soft_sync, }; TEST_ESP_OK(mcpwm_capture_timer_set_phase_on_sync(cap_timer, &sync_config)); + mcpwm_cap_channel_handle_t cap_channel = NULL; mcpwm_capture_channel_config_t cap_chan_config = { .gpio_num = -1, // don't need any GPIO, we use software to trigger a catch @@ -223,15 +235,19 @@ TEST_CASE("mcpwm_capture_timer_sync_phase_lock", "[mcpwm]") uint32_t cap_data; TEST_ESP_OK(mcpwm_capture_channel_register_event_callbacks(cap_channel, &cbs, &cap_data)); + printf("enable capture channel\r\n"); + TEST_ESP_OK(mcpwm_capture_channel_enable(cap_channel)); + TEST_ESP_OK(mcpwm_capture_channel_trigger_soft_catch(cap_channel)); vTaskDelay(pdMS_TO_TICKS(10)); - printf("capture data before sync: %u\r\n", cap_data); + printf("capture data before sync: %"PRIu32"\r\n", cap_data); TEST_ESP_OK(mcpwm_soft_sync_activate(soft_sync)); TEST_ESP_OK(mcpwm_capture_channel_trigger_soft_catch(cap_channel)); vTaskDelay(pdMS_TO_TICKS(10)); - printf("capture data after sync: %u\r\n", cap_data); + printf("capture data after sync: %"PRIu32"\r\n", cap_data); TEST_ASSERT_EQUAL(1000, cap_data); + TEST_ESP_OK(mcpwm_capture_channel_disable(cap_channel)); TEST_ESP_OK(mcpwm_del_capture_channel(cap_channel)); TEST_ESP_OK(mcpwm_del_capture_timer(cap_timer)); TEST_ESP_OK(mcpwm_del_sync_src(soft_sync)); diff --git a/components/driver/test_apps/mcpwm/main/test_mcpwm_cmpr.c b/components/driver/test_apps/mcpwm/main/test_mcpwm_cmpr.c index 5e0404d18b..ed531a3b05 100644 --- a/components/driver/test_apps/mcpwm/main/test_mcpwm_cmpr.c +++ b/components/driver/test_apps/mcpwm/main/test_mcpwm_cmpr.c @@ -3,6 +3,7 @@ * * SPDX-License-Identifier: Apache-2.0 */ +#include #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "unity.h" @@ -14,7 +15,7 @@ TEST_CASE("mcpwm_comparator_install_uninstall", "[mcpwm]") { mcpwm_timer_handle_t timer; - mcpwm_oper_handle_t operator; + mcpwm_oper_handle_t oper; mcpwm_cmpr_handle_t comparators[SOC_MCPWM_COMPARATORS_PER_OPERATOR]; mcpwm_timer_config_t timer_config = { @@ -29,25 +30,25 @@ TEST_CASE("mcpwm_comparator_install_uninstall", "[mcpwm]") }; printf("install timer and operator"); TEST_ESP_OK(mcpwm_new_timer(&timer_config, &timer)); - TEST_ESP_OK(mcpwm_new_operator(&operator_config, &operator)); + TEST_ESP_OK(mcpwm_new_operator(&operator_config, &oper)); printf("install comparator\r\n"); mcpwm_comparator_config_t comparator_config = {}; for (int i = 0; i < SOC_MCPWM_COMPARATORS_PER_OPERATOR; i++) { - TEST_ESP_OK(mcpwm_new_comparator(operator, &comparator_config, &comparators[i])); + TEST_ESP_OK(mcpwm_new_comparator(oper, &comparator_config, &comparators[i])); } - TEST_ESP_ERR(ESP_ERR_NOT_FOUND, mcpwm_new_comparator(operator, &comparator_config, &comparators[0])); + TEST_ESP_ERR(ESP_ERR_NOT_FOUND, mcpwm_new_comparator(oper, &comparator_config, &comparators[0])); printf("connect MCPWM timer and operators\r\n"); - TEST_ESP_OK(mcpwm_operator_connect_timer(operator, timer)); + TEST_ESP_OK(mcpwm_operator_connect_timer(oper, timer)); printf("uninstall timer, operator and comparators\r\n"); // can't delete operator if the comparators are still in working - TEST_ESP_ERR(ESP_ERR_INVALID_STATE, mcpwm_del_operator(operator)); + TEST_ESP_ERR(ESP_ERR_INVALID_STATE, mcpwm_del_operator(oper)); for (int i = 0; i < SOC_MCPWM_COMPARATORS_PER_OPERATOR; i++) { TEST_ESP_OK(mcpwm_del_comparator(comparators[i])); } - TEST_ESP_OK(mcpwm_del_operator(operator)); + TEST_ESP_OK(mcpwm_del_operator(oper)); TEST_ESP_OK(mcpwm_del_timer(timer)); } @@ -61,7 +62,7 @@ static bool test_compare_on_reach(mcpwm_cmpr_handle_t cmpr, const mcpwm_compare_ TEST_CASE("mcpwm_comparator_event_callback", "[mcpwm]") { mcpwm_timer_handle_t timer; - mcpwm_oper_handle_t operator; + mcpwm_oper_handle_t oper; mcpwm_cmpr_handle_t comparator; mcpwm_timer_config_t timer_config = { @@ -75,15 +76,15 @@ TEST_CASE("mcpwm_comparator_event_callback", "[mcpwm]") .group_id = 0, }; mcpwm_comparator_config_t comparator_config = {}; - printf("install timer, operator and comparator"); + printf("install timer, operator and comparator\r\n"); TEST_ESP_OK(mcpwm_new_timer(&timer_config, &timer)); - TEST_ESP_OK(mcpwm_new_operator(&operator_config, &operator)); - TEST_ESP_OK(mcpwm_new_comparator(operator, &comparator_config, &comparator)); + TEST_ESP_OK(mcpwm_new_operator(&operator_config, &oper)); + TEST_ESP_OK(mcpwm_new_comparator(oper, &comparator_config, &comparator)); // set compare value before connecting timer and operator will fail TEST_ESP_ERR(ESP_ERR_INVALID_STATE, mcpwm_comparator_set_compare_value(comparator, 5000)); printf("connect MCPWM timer and operators\r\n"); - TEST_ESP_OK(mcpwm_operator_connect_timer(operator, timer)); + TEST_ESP_OK(mcpwm_operator_connect_timer(oper, timer)); // compare ticks can't exceed the timer's period ticks TEST_ESP_ERR(ESP_ERR_INVALID_ARG, mcpwm_comparator_set_compare_value(comparator, 20 * 1000)); TEST_ESP_OK(mcpwm_comparator_set_compare_value(comparator, 5 * 1000)); @@ -101,13 +102,13 @@ TEST_CASE("mcpwm_comparator_event_callback", "[mcpwm]") vTaskDelay(pdMS_TO_TICKS(1000)); TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_STOP_EMPTY)); - printf("compare_counts=%u\r\n", compare_counts); + printf("compare_counts=%"PRIu32"\r\n", compare_counts); // the timer period is 10ms, the expected compare_counts = 1s/10ms = 100 TEST_ASSERT_INT_WITHIN(1, 100, compare_counts); printf("uninstall timer, operator and comparator\r\n"); TEST_ESP_OK(mcpwm_timer_disable(timer)); TEST_ESP_OK(mcpwm_del_comparator(comparator)); - TEST_ESP_OK(mcpwm_del_operator(operator)); + TEST_ESP_OK(mcpwm_del_operator(oper)); TEST_ESP_OK(mcpwm_del_timer(timer)); } diff --git a/components/driver/test_apps/mcpwm/main/test_mcpwm_gen.c b/components/driver/test_apps/mcpwm/main/test_mcpwm_gen.c index 1d397bd0e2..8efb4cece2 100644 --- a/components/driver/test_apps/mcpwm/main/test_mcpwm_gen.c +++ b/components/driver/test_apps/mcpwm/main/test_mcpwm_gen.c @@ -45,11 +45,11 @@ TEST_CASE("mcpwm_generator_force_level_hold_on", "[mcpwm]") { // The operator can even work without the timer printf("create operator and generator\r\n"); - mcpwm_oper_handle_t operator = NULL; + mcpwm_oper_handle_t oper = NULL; mcpwm_operator_config_t operator_config = { .group_id = 0, }; - TEST_ESP_OK(mcpwm_new_operator(&operator_config, &operator)); + TEST_ESP_OK(mcpwm_new_operator(&operator_config, &oper)); mcpwm_gen_handle_t generator = NULL; const int gen_gpio = 0; @@ -57,7 +57,7 @@ TEST_CASE("mcpwm_generator_force_level_hold_on", "[mcpwm]") .gen_gpio_num = gen_gpio, .flags.io_loop_back = true, // loop back for test }; - TEST_ESP_OK(mcpwm_new_generator(operator, &generator_config, &generator)); + TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &generator)); printf("add force level to the generator, hold on"); for (int i = 0; i < 10; i++) { @@ -74,7 +74,7 @@ TEST_CASE("mcpwm_generator_force_level_hold_on", "[mcpwm]") printf("delete generator and operator\r\n"); TEST_ESP_OK(mcpwm_del_generator(generator)); - TEST_ESP_OK(mcpwm_del_operator(operator)); + TEST_ESP_OK(mcpwm_del_operator(oper)); } TEST_CASE("mcpwm_generator_force_level_recovery", "[mcpwm]") @@ -92,13 +92,13 @@ TEST_CASE("mcpwm_generator_force_level_recovery", "[mcpwm]") TEST_ESP_OK(mcpwm_timer_enable(timer)); printf("create operator\r\n"); - mcpwm_oper_handle_t operator = NULL; + mcpwm_oper_handle_t oper = NULL; mcpwm_operator_config_t operator_config = { .group_id = 0, .flags.update_gen_action_on_tez = true, }; - TEST_ESP_OK(mcpwm_new_operator(&operator_config, &operator)); - TEST_ESP_OK(mcpwm_operator_connect_timer(operator, timer)); + TEST_ESP_OK(mcpwm_new_operator(&operator_config, &oper)); + TEST_ESP_OK(mcpwm_operator_connect_timer(oper, timer)); printf("create generator\r\n"); mcpwm_gen_handle_t generator = NULL; @@ -107,7 +107,7 @@ TEST_CASE("mcpwm_generator_force_level_recovery", "[mcpwm]") .gen_gpio_num = gen_gpio, .flags.io_loop_back = true, // loop back for test }; - TEST_ESP_OK(mcpwm_new_generator(operator, &generator_config, &generator)); + TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &generator)); printf("add force level to the generator, and recovery by events"); TEST_ESP_OK(mcpwm_generator_set_force_level(generator, 0, false)); @@ -142,7 +142,7 @@ TEST_CASE("mcpwm_generator_force_level_recovery", "[mcpwm]") printf("delete generator, operator and timer\r\n"); TEST_ESP_OK(mcpwm_timer_disable(timer)); TEST_ESP_OK(mcpwm_del_generator(generator)); - TEST_ESP_OK(mcpwm_del_operator(operator)); + TEST_ESP_OK(mcpwm_del_operator(oper)); TEST_ESP_OK(mcpwm_del_timer(timer)); } @@ -227,9 +227,9 @@ static void mcpwm_gen_action_test_template(uint32_t timer_resolution, uint32_t p mcpwm_operator_config_t operator_config = { .group_id = 0, }; - mcpwm_oper_handle_t operator = NULL; - TEST_ESP_OK(mcpwm_new_operator(&operator_config, &operator)); - TEST_ESP_OK(mcpwm_operator_connect_timer(operator, timer)); + mcpwm_oper_handle_t oper = NULL; + TEST_ESP_OK(mcpwm_new_operator(&operator_config, &oper)); + TEST_ESP_OK(mcpwm_operator_connect_timer(oper, timer)); TEST_ESP_OK(mcpwm_timer_enable(timer)); @@ -238,8 +238,8 @@ static void mcpwm_gen_action_test_template(uint32_t timer_resolution, uint32_t p mcpwm_comparator_config_t comparator_config = { .flags.update_cmp_on_tez = true, }; - TEST_ESP_OK(mcpwm_new_comparator(operator, &comparator_config, &comparator_a)); - TEST_ESP_OK(mcpwm_new_comparator(operator, &comparator_config, &comparator_b)); + TEST_ESP_OK(mcpwm_new_comparator(oper, &comparator_config, &comparator_a)); + TEST_ESP_OK(mcpwm_new_comparator(oper, &comparator_config, &comparator_b)); TEST_ESP_OK(mcpwm_comparator_set_compare_value(comparator_a, cmpa)); TEST_ESP_OK(mcpwm_comparator_set_compare_value(comparator_b, cmpb)); @@ -248,9 +248,9 @@ static void mcpwm_gen_action_test_template(uint32_t timer_resolution, uint32_t p mcpwm_generator_config_t generator_config = { .gen_gpio_num = gpioa, }; - TEST_ESP_OK(mcpwm_new_generator(operator, &generator_config, &generator_a)); + TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &generator_a)); generator_config.gen_gpio_num = gpiob; - TEST_ESP_OK(mcpwm_new_generator(operator, &generator_config, &generator_b)); + TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &generator_b)); set_generator_actions(generator_a, generator_b, comparator_a, comparator_b); @@ -264,7 +264,7 @@ static void mcpwm_gen_action_test_template(uint32_t timer_resolution, uint32_t p TEST_ESP_OK(mcpwm_del_generator(generator_b)); TEST_ESP_OK(mcpwm_del_comparator(comparator_a)); TEST_ESP_OK(mcpwm_del_comparator(comparator_b)); - TEST_ESP_OK(mcpwm_del_operator(operator)); + TEST_ESP_OK(mcpwm_del_operator(oper)); TEST_ESP_OK(mcpwm_del_timer(timer)); } @@ -398,9 +398,9 @@ static void mcpwm_deadtime_test_template(uint32_t timer_resolution, uint32_t per mcpwm_operator_config_t operator_config = { .group_id = 0, }; - mcpwm_oper_handle_t operator = NULL; - TEST_ESP_OK(mcpwm_new_operator(&operator_config, &operator)); - TEST_ESP_OK(mcpwm_operator_connect_timer(operator, timer)); + mcpwm_oper_handle_t oper = NULL; + TEST_ESP_OK(mcpwm_new_operator(&operator_config, &oper)); + TEST_ESP_OK(mcpwm_operator_connect_timer(oper, timer)); TEST_ESP_OK(mcpwm_timer_enable(timer)); @@ -409,8 +409,8 @@ static void mcpwm_deadtime_test_template(uint32_t timer_resolution, uint32_t per mcpwm_comparator_config_t comparator_config = { .flags.update_cmp_on_tez = true, }; - TEST_ESP_OK(mcpwm_new_comparator(operator, &comparator_config, &comparator_a)); - TEST_ESP_OK(mcpwm_new_comparator(operator, &comparator_config, &comparator_b)); + TEST_ESP_OK(mcpwm_new_comparator(oper, &comparator_config, &comparator_a)); + TEST_ESP_OK(mcpwm_new_comparator(oper, &comparator_config, &comparator_b)); TEST_ESP_OK(mcpwm_comparator_set_compare_value(comparator_a, cmpa)); TEST_ESP_OK(mcpwm_comparator_set_compare_value(comparator_b, cmpb)); @@ -419,9 +419,9 @@ static void mcpwm_deadtime_test_template(uint32_t timer_resolution, uint32_t per mcpwm_generator_config_t generator_config = { .gen_gpio_num = gpioa, }; - TEST_ESP_OK(mcpwm_new_generator(operator, &generator_config, &generator_a)); + TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &generator_a)); generator_config.gen_gpio_num = gpiob; - TEST_ESP_OK(mcpwm_new_generator(operator, &generator_config, &generator_b)); + TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &generator_b)); set_generator_actions(generator_a, generator_b, comparator_a, comparator_b); set_dead_time(generator_a, generator_b); @@ -436,7 +436,7 @@ static void mcpwm_deadtime_test_template(uint32_t timer_resolution, uint32_t per TEST_ESP_OK(mcpwm_del_generator(generator_b)); TEST_ESP_OK(mcpwm_del_comparator(comparator_a)); TEST_ESP_OK(mcpwm_del_comparator(comparator_b)); - TEST_ESP_OK(mcpwm_del_operator(operator)); + TEST_ESP_OK(mcpwm_del_operator(oper)); TEST_ESP_OK(mcpwm_del_timer(timer)); } @@ -644,3 +644,82 @@ TEST_CASE("mcpwm_generator_deadtime_classical_configuration", "[mcpwm]") printf("Bypass A, RED + FED on B\r\n"); mcpwm_deadtime_test_template(1000000, 500, 350, 350, 0, 2, redfedb_only_set_generator_actions, redfedb_only_set_dead_time); } + +TEST_CASE("mcpwm_duty_empty_full", "[mcpwm]") +{ + const int gen_gpio_num = 0; + mcpwm_timer_handle_t timer; + mcpwm_oper_handle_t oper; + mcpwm_cmpr_handle_t comparator; + mcpwm_gen_handle_t gen; + + mcpwm_timer_config_t timer_config = { + .group_id = 0, + .clk_src = MCPWM_TIMER_CLK_SRC_DEFAULT, + .resolution_hz = 1 * 1000 * 1000, + .period_ticks = 50, // 50us <-> 20KHz + .count_mode = MCPWM_TIMER_COUNT_MODE_UP, + }; + mcpwm_operator_config_t operator_config = { + .group_id = 0, + }; + mcpwm_comparator_config_t comparator_config = { + .flags.update_cmp_on_tep = true, + .flags.update_cmp_on_tez = true, + }; + printf("install timer, operator and comparator\r\n"); + TEST_ESP_OK(mcpwm_new_timer(&timer_config, &timer)); + TEST_ESP_OK(mcpwm_new_operator(&operator_config, &oper)); + TEST_ESP_OK(mcpwm_new_comparator(oper, &comparator_config, &comparator)); + + printf("connect MCPWM timer and operators\r\n"); + TEST_ESP_OK(mcpwm_operator_connect_timer(oper, timer)); + TEST_ESP_OK(mcpwm_comparator_set_compare_value(comparator, 0)); + + printf("install MCPWM generator\r\n"); + mcpwm_generator_config_t gen_config = { + .gen_gpio_num = gen_gpio_num, + .flags.io_loop_back = true, // we want to read the output level as well + }; + TEST_ESP_OK(mcpwm_new_generator(oper, &gen_config, &gen)); + + printf("set generator actions on timer and compare events\r\n"); + TEST_ESP_OK(mcpwm_generator_set_actions_on_timer_event(gen, + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH), + MCPWM_GEN_TIMER_EVENT_ACTION_END())); + TEST_ESP_OK(mcpwm_generator_set_actions_on_compare_event(gen, + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, comparator, MCPWM_GEN_ACTION_LOW), + MCPWM_GEN_COMPARE_EVENT_ACTION_END())); + + printf("start timer\r\n"); + TEST_ESP_OK(mcpwm_timer_enable(timer)); + TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_START_NO_STOP)); + + // check if the output is a const low level + for (int i = 0; i < 100; i++) { + TEST_ASSERT_EQUAL(0, gpio_get_level(gen_gpio_num)); + esp_rom_delay_us(1); + } + + // set the compare equals to the period + TEST_ESP_OK(mcpwm_comparator_set_compare_value(comparator, 50)); + vTaskDelay(pdMS_TO_TICKS(10)); + // so the output should be a const high level + for (int i = 0; i < 100; i++) { + TEST_ASSERT_EQUAL(1, gpio_get_level(gen_gpio_num)); + esp_rom_delay_us(1); + } + + TEST_ESP_OK(mcpwm_comparator_set_compare_value(comparator, 49)); + vTaskDelay(pdMS_TO_TICKS(100)); + TEST_ESP_OK(mcpwm_comparator_set_compare_value(comparator, 1)); + vTaskDelay(pdMS_TO_TICKS(100)); + + printf("uninstall timer, operator and comparator\r\n"); + TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_STOP_EMPTY)); + TEST_ESP_OK(mcpwm_timer_disable(timer)); + TEST_ESP_OK(mcpwm_del_generator(gen)); + TEST_ESP_OK(mcpwm_del_comparator(comparator)); + TEST_ESP_OK(mcpwm_del_operator(oper)); + TEST_ESP_OK(mcpwm_del_timer(timer)); +} diff --git a/components/driver/test_apps/mcpwm/main/test_mcpwm_iram.c b/components/driver/test_apps/mcpwm/main/test_mcpwm_iram.c index 29ed573d50..6cd422e5c3 100644 --- a/components/driver/test_apps/mcpwm/main/test_mcpwm_iram.c +++ b/components/driver/test_apps/mcpwm/main/test_mcpwm_iram.c @@ -4,15 +4,15 @@ * SPDX-License-Identifier: Apache-2.0 */ #include +#include #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/event_groups.h" #include "unity.h" +#include "unity_test_utils.h" #include "soc/soc_caps.h" #include "esp_private/esp_clk.h" -#include "esp_private/spi_flash_os.h" -#include "driver/mcpwm_cap.h" -#include "driver/mcpwm_sync.h" +#include "driver/mcpwm_prelude.h" #include "driver/gpio.h" #include "test_mcpwm_utils.h" @@ -27,15 +27,12 @@ static bool IRAM_ATTR test_capture_callback_iram_safe(mcpwm_cap_channel_handle_t return false; } -static void IRAM_ATTR test_mcpwm_capture_gpio_simulate(int gpio_sig) +static void IRAM_ATTR test_simulate_input_post_cache_disable(void *args) { - // disable flash cache - spi_flash_guard_get()->start(); + int gpio_sig = (int)args; gpio_set_level(gpio_sig, 1); esp_rom_delay_us(1000); gpio_set_level(gpio_sig, 0); - // enable flash cache - spi_flash_guard_get()->end(); } TEST_CASE("mcpwm_capture_iram_safe", "[mcpwm]") @@ -71,20 +68,109 @@ TEST_CASE("mcpwm_capture_iram_safe", "[mcpwm]") uint32_t cap_value[2] = {0}; TEST_ESP_OK(mcpwm_capture_channel_register_event_callbacks(pps_channel, &cbs, cap_value)); + printf("enable capture channel\r\n"); + TEST_ESP_OK(mcpwm_capture_channel_enable(pps_channel)); + printf("enable and start capture timer\r\n"); TEST_ESP_OK(mcpwm_capture_timer_enable(cap_timer)); TEST_ESP_OK(mcpwm_capture_timer_start(cap_timer)); printf("disable cache, simulate GPIO capture signal\r\n"); - test_mcpwm_capture_gpio_simulate(cap_gpio); + unity_utils_run_cache_disable_stub(test_simulate_input_post_cache_disable, (void *)cap_gpio); - printf("capture value: Pos=%u, Neg=%u\r\n", cap_value[0], cap_value[1]); + printf("capture value: Pos=%"PRIu32", Neg=%"PRIu32"\r\n", cap_value[0], cap_value[1]); // Capture timer is clocked from APB by default uint32_t clk_src_res = esp_clk_apb_freq(); TEST_ASSERT_UINT_WITHIN(2000, clk_src_res / 1000, cap_value[1] - cap_value[0]); printf("uninstall capture channel and timer\r\n"); + TEST_ESP_OK(mcpwm_capture_channel_disable(pps_channel)); TEST_ESP_OK(mcpwm_del_capture_channel(pps_channel)); TEST_ESP_OK(mcpwm_capture_timer_disable(cap_timer)); TEST_ESP_OK(mcpwm_del_capture_timer(cap_timer)); } + +static bool IRAM_ATTR test_compare_on_reach(mcpwm_cmpr_handle_t cmpr, const mcpwm_compare_event_data_t *ev_data, void *user_data) +{ + uint32_t cmp_val = ev_data->compare_ticks; + cmp_val += 10; + // compare ticks can't exceed the timer's period ticks + if (cmp_val >= 50) { + cmp_val = 0; + } + mcpwm_comparator_set_compare_value(cmpr, cmp_val); + return false; +} + +static void IRAM_ATTR test_delay_post_cache_disable(void *args) +{ + esp_rom_delay_us(1000); +} + +TEST_CASE("mcpwm_comparator_iram_safe", "[mcpwm]") +{ + mcpwm_timer_handle_t timer; + mcpwm_oper_handle_t oper; + mcpwm_cmpr_handle_t comparator; + mcpwm_gen_handle_t gen; + + mcpwm_timer_config_t timer_config = { + .group_id = 0, + .clk_src = MCPWM_TIMER_CLK_SRC_DEFAULT, + .resolution_hz = 1 * 1000 * 1000, + .period_ticks = 50, // 50us <-> 20KHz + .count_mode = MCPWM_TIMER_COUNT_MODE_UP, + }; + mcpwm_operator_config_t operator_config = { + .group_id = 0, + }; + mcpwm_comparator_config_t comparator_config = { + .flags.update_cmp_on_tep = true, + .flags.update_cmp_on_tez = true, + }; + printf("install timer, operator and comparator\r\n"); + TEST_ESP_OK(mcpwm_new_timer(&timer_config, &timer)); + TEST_ESP_OK(mcpwm_new_operator(&operator_config, &oper)); + TEST_ESP_OK(mcpwm_new_comparator(oper, &comparator_config, &comparator)); + + printf("connect MCPWM timer and operators\r\n"); + TEST_ESP_OK(mcpwm_operator_connect_timer(oper, timer)); + TEST_ESP_OK(mcpwm_comparator_set_compare_value(comparator, 10)); + + printf("install MCPWM generator\r\n"); + mcpwm_generator_config_t gen_config = { + .gen_gpio_num = 0, + }; + TEST_ESP_OK(mcpwm_new_generator(oper, &gen_config, &gen)); + + printf("set generator actions on timer and compare events\r\n"); + TEST_ESP_OK(mcpwm_generator_set_actions_on_timer_event(gen, + MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH), + MCPWM_GEN_TIMER_EVENT_ACTION_END())); + TEST_ESP_OK(mcpwm_generator_set_actions_on_compare_event(gen, + MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, comparator, MCPWM_GEN_ACTION_LOW), + MCPWM_GEN_COMPARE_EVENT_ACTION_END())); + + printf("register compare event callback\r\n"); + mcpwm_comparator_event_callbacks_t cbs = { + .on_reach = test_compare_on_reach, + }; + TEST_ESP_OK(mcpwm_comparator_register_event_callbacks(comparator, &cbs, NULL)); + + printf("start timer\r\n"); + TEST_ESP_OK(mcpwm_timer_enable(timer)); + TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_START_NO_STOP)); + + printf("disable flash cache and check the compare events are still in working\r\n"); + for (int i = 0; i < 50; i++) { + unity_utils_run_cache_disable_stub(test_delay_post_cache_disable, NULL); + } + + printf("uninstall timer, operator and comparator\r\n"); + TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_STOP_EMPTY)); + TEST_ESP_OK(mcpwm_timer_disable(timer)); + TEST_ESP_OK(mcpwm_del_generator(gen)); + TEST_ESP_OK(mcpwm_del_comparator(comparator)); + TEST_ESP_OK(mcpwm_del_operator(oper)); + TEST_ESP_OK(mcpwm_del_timer(timer)); +} diff --git a/components/driver/test_apps/mcpwm/main/test_mcpwm_oper.c b/components/driver/test_apps/mcpwm/main/test_mcpwm_oper.c index 6c013e705c..455cf910bd 100644 --- a/components/driver/test_apps/mcpwm/main/test_mcpwm_oper.c +++ b/components/driver/test_apps/mcpwm/main/test_mcpwm_oper.c @@ -73,15 +73,15 @@ TEST_CASE("mcpwm_operator_carrier", "[mcpwm]") mcpwm_operator_config_t operator_config = { .group_id = 0, }; - mcpwm_oper_handle_t operator = NULL; - TEST_ESP_OK(mcpwm_new_operator(&operator_config, &operator)); - TEST_ESP_OK(mcpwm_operator_connect_timer(operator, timer)); + mcpwm_oper_handle_t oper = NULL; + TEST_ESP_OK(mcpwm_new_operator(&operator_config, &oper)); + TEST_ESP_OK(mcpwm_operator_connect_timer(oper, timer)); mcpwm_generator_config_t generator_config = { .gen_gpio_num = 0, }; mcpwm_gen_handle_t generator = NULL; - TEST_ESP_OK(mcpwm_new_generator(operator, &generator_config, &generator)); + TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &generator)); TEST_ESP_OK(mcpwm_generator_set_actions_on_timer_event(generator, MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_TOGGLE), @@ -93,7 +93,7 @@ TEST_CASE("mcpwm_operator_carrier", "[mcpwm]") .duty_cycle = 0.5, .first_pulse_duration_us = 10, }; - TEST_ESP_OK(mcpwm_operator_apply_carrier(operator, &carrier_config)); + TEST_ESP_OK(mcpwm_operator_apply_carrier(oper, &carrier_config)); TEST_ESP_OK(mcpwm_timer_enable(timer)); @@ -104,7 +104,7 @@ TEST_CASE("mcpwm_operator_carrier", "[mcpwm]") printf("remove carrier from PWM wave\r\n"); carrier_config.frequency_hz = 0; - TEST_ESP_OK(mcpwm_operator_apply_carrier(operator, &carrier_config)); + TEST_ESP_OK(mcpwm_operator_apply_carrier(oper, &carrier_config)); TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_START_NO_STOP)); vTaskDelay(pdMS_TO_TICKS(200)); TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_STOP_EMPTY)); @@ -112,17 +112,17 @@ TEST_CASE("mcpwm_operator_carrier", "[mcpwm]") TEST_ESP_OK(mcpwm_timer_disable(timer)); TEST_ESP_OK(mcpwm_del_generator(generator)); - TEST_ESP_OK(mcpwm_del_operator(operator)); + TEST_ESP_OK(mcpwm_del_operator(oper)); TEST_ESP_OK(mcpwm_del_timer(timer)); } -static bool test_cbc_brake_on_gpio_fault_callback(mcpwm_oper_handle_t operator, const mcpwm_brake_event_data_t *edata, void *user_data) +static bool test_cbc_brake_on_gpio_fault_callback(mcpwm_oper_handle_t oper, const mcpwm_brake_event_data_t *edata, void *user_data) { esp_rom_printf("cbc brake\r\n"); return false; } -static bool test_ost_brake_on_gpio_fault_callback(mcpwm_oper_handle_t operator, const mcpwm_brake_event_data_t *edata, void *user_data) +static bool test_ost_brake_on_gpio_fault_callback(mcpwm_oper_handle_t oper, const mcpwm_brake_event_data_t *edata, void *user_data) { esp_rom_printf("ost brake\r\n"); return false; @@ -145,16 +145,16 @@ TEST_CASE("mcpwm_operator_brake_on_gpio_fault", "[mcpwm]") mcpwm_operator_config_t operator_config = { .group_id = 0, }; - mcpwm_oper_handle_t operator = NULL; - TEST_ESP_OK(mcpwm_new_operator(&operator_config, &operator)); - TEST_ESP_OK(mcpwm_operator_connect_timer(operator, timer)); + mcpwm_oper_handle_t oper = NULL; + TEST_ESP_OK(mcpwm_new_operator(&operator_config, &oper)); + TEST_ESP_OK(mcpwm_operator_connect_timer(oper, timer)); printf("set brake event callbacks for operator\r\n"); mcpwm_operator_event_callbacks_t cbs = { .on_brake_cbc = test_cbc_brake_on_gpio_fault_callback, .on_brake_ost = test_ost_brake_on_gpio_fault_callback, }; - TEST_ESP_OK(mcpwm_operator_register_event_callbacks(operator, &cbs, NULL)); + TEST_ESP_OK(mcpwm_operator_register_event_callbacks(oper, &cbs, NULL)); printf("install gpio fault\r\n"); mcpwm_gpio_fault_config_t gpio_fault_config = { @@ -183,10 +183,10 @@ TEST_CASE("mcpwm_operator_brake_on_gpio_fault", "[mcpwm]") .brake_mode = MCPWM_OPER_BRAKE_MODE_CBC, .flags.cbc_recover_on_tez = true, }; - TEST_ESP_OK(mcpwm_operator_set_brake_on_fault(operator, &brake_config)); + TEST_ESP_OK(mcpwm_operator_set_brake_on_fault(oper, &brake_config)); brake_config.fault = gpio_ost_fault; brake_config.brake_mode = MCPWM_OPER_BRAKE_MODE_OST; - TEST_ESP_OK(mcpwm_operator_set_brake_on_fault(operator, &brake_config)); + TEST_ESP_OK(mcpwm_operator_set_brake_on_fault(oper, &brake_config)); printf("create generators\r\n"); const int gen_a_gpio = 0; @@ -197,9 +197,9 @@ TEST_CASE("mcpwm_operator_brake_on_gpio_fault", "[mcpwm]") .flags.io_loop_back = true, }; generator_config.gen_gpio_num = gen_a_gpio; - TEST_ESP_OK(mcpwm_new_generator(operator, &generator_config, &gen_a)); + TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &gen_a)); generator_config.gen_gpio_num = gen_b_gpio; - TEST_ESP_OK(mcpwm_new_generator(operator, &generator_config, &gen_b)); + TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &gen_b)); printf("set generator actions on timer event\r\n"); TEST_ESP_OK(mcpwm_generator_set_actions_on_timer_event(gen_a, @@ -229,7 +229,7 @@ TEST_CASE("mcpwm_operator_brake_on_gpio_fault", "[mcpwm]") // remove the fault signal gpio_set_level(cbc_fault_gpio, 0); // recovery - TEST_ESP_OK(mcpwm_operator_recover_from_fault(operator, gpio_cbc_fault)); + TEST_ESP_OK(mcpwm_operator_recover_from_fault(oper, gpio_cbc_fault)); vTaskDelay(pdMS_TO_TICKS(40)); // should recovery automatically TEST_ASSERT_EQUAL(0, gpio_get_level(gen_a_gpio)); @@ -241,14 +241,14 @@ TEST_CASE("mcpwm_operator_brake_on_gpio_fault", "[mcpwm]") vTaskDelay(pdMS_TO_TICKS(10)); TEST_ASSERT_EQUAL(1, gpio_get_level(gen_b_gpio)); // can't recover because fault signal is still active - TEST_ESP_ERR(ESP_ERR_INVALID_STATE, mcpwm_operator_recover_from_fault(operator, gpio_ost_fault)); + TEST_ESP_ERR(ESP_ERR_INVALID_STATE, mcpwm_operator_recover_from_fault(oper, gpio_ost_fault)); // remove the fault signal gpio_set_level(ost_fault_gpio, 0); vTaskDelay(pdMS_TO_TICKS(40)); // for ost brake, the generator can't recover before we manually recover it TEST_ASSERT_EQUAL(1, gpio_get_level(gen_b_gpio)); // now it's safe to recover the operator - TEST_ESP_OK(mcpwm_operator_recover_from_fault(operator, gpio_ost_fault)); + TEST_ESP_OK(mcpwm_operator_recover_from_fault(oper, gpio_ost_fault)); vTaskDelay(pdMS_TO_TICKS(40)); // should recovery now TEST_ASSERT_EQUAL(0, gpio_get_level(gen_b_gpio)); @@ -260,7 +260,7 @@ TEST_CASE("mcpwm_operator_brake_on_gpio_fault", "[mcpwm]") TEST_ESP_OK(mcpwm_del_fault(gpio_ost_fault)); TEST_ESP_OK(mcpwm_del_generator(gen_a)); TEST_ESP_OK(mcpwm_del_generator(gen_b)); - TEST_ESP_OK(mcpwm_del_operator(operator)); + TEST_ESP_OK(mcpwm_del_operator(oper)); TEST_ESP_OK(mcpwm_del_timer(timer)); } @@ -281,9 +281,9 @@ TEST_CASE("mcpwm_operator_brake_on_soft_fault", "[mcpwm]") mcpwm_operator_config_t operator_config = { .group_id = 0, }; - mcpwm_oper_handle_t operator = NULL; - TEST_ESP_OK(mcpwm_new_operator(&operator_config, &operator)); - TEST_ESP_OK(mcpwm_operator_connect_timer(operator, timer)); + mcpwm_oper_handle_t oper = NULL; + TEST_ESP_OK(mcpwm_new_operator(&operator_config, &oper)); + TEST_ESP_OK(mcpwm_operator_connect_timer(oper, timer)); printf("install soft fault\r\n"); mcpwm_soft_fault_config_t soft_fault_config = {}; @@ -296,7 +296,7 @@ TEST_CASE("mcpwm_operator_brake_on_soft_fault", "[mcpwm]") .brake_mode = MCPWM_OPER_BRAKE_MODE_CBC, .flags.cbc_recover_on_tez = true, }; - TEST_ESP_OK(mcpwm_operator_set_brake_on_fault(operator, &brake_config)); + TEST_ESP_OK(mcpwm_operator_set_brake_on_fault(oper, &brake_config)); printf("create generators\r\n"); const int gen_a_gpio = 0; @@ -307,9 +307,9 @@ TEST_CASE("mcpwm_operator_brake_on_soft_fault", "[mcpwm]") .flags.io_loop_back = true, }; generator_config.gen_gpio_num = gen_a_gpio; - TEST_ESP_OK(mcpwm_new_generator(operator, &generator_config, &gen_a)); + TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &gen_a)); generator_config.gen_gpio_num = gen_b_gpio; - TEST_ESP_OK(mcpwm_new_generator(operator, &generator_config, &gen_b)); + TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &gen_b)); printf("set generator actions on timer event\r\n"); TEST_ESP_OK(mcpwm_generator_set_actions_on_timer_event(gen_a, @@ -344,7 +344,7 @@ TEST_CASE("mcpwm_operator_brake_on_soft_fault", "[mcpwm]") // start the timer, so that operator can recover at a specific event (e.g. tez) TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_START_NO_STOP)); // recover on tez - TEST_ESP_OK(mcpwm_operator_recover_from_fault(operator, soft_fault)); + TEST_ESP_OK(mcpwm_operator_recover_from_fault(oper, soft_fault)); vTaskDelay(pdMS_TO_TICKS(40)); // the generator output should be recoverd automatically TEST_ASSERT_EQUAL(0, gpio_get_level(gen_a_gpio)); @@ -352,7 +352,7 @@ TEST_CASE("mcpwm_operator_brake_on_soft_fault", "[mcpwm]") printf("change the brake mode to ost\r\n"); brake_config.brake_mode = MCPWM_OPER_BRAKE_MODE_OST; - TEST_ESP_OK(mcpwm_operator_set_brake_on_fault(operator, &brake_config)); + TEST_ESP_OK(mcpwm_operator_set_brake_on_fault(oper, &brake_config)); printf("trigger soft fault signal, brake in OST mode\r\n"); TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_START_NO_STOP)); @@ -364,7 +364,7 @@ TEST_CASE("mcpwm_operator_brake_on_soft_fault", "[mcpwm]") vTaskDelay(pdMS_TO_TICKS(40)); // don't recover without a manual recover TEST_ASSERT_EQUAL(1, gpio_get_level(gen_b_gpio)); - TEST_ESP_OK(mcpwm_operator_recover_from_fault(operator, soft_fault)); + TEST_ESP_OK(mcpwm_operator_recover_from_fault(oper, soft_fault)); vTaskDelay(pdMS_TO_TICKS(10)); // should recovery now TEST_ASSERT_EQUAL(0, gpio_get_level(gen_b_gpio)); @@ -375,6 +375,6 @@ TEST_CASE("mcpwm_operator_brake_on_soft_fault", "[mcpwm]") TEST_ESP_OK(mcpwm_del_fault(soft_fault)); TEST_ESP_OK(mcpwm_del_generator(gen_a)); TEST_ESP_OK(mcpwm_del_generator(gen_b)); - TEST_ESP_OK(mcpwm_del_operator(operator)); + TEST_ESP_OK(mcpwm_del_operator(oper)); TEST_ESP_OK(mcpwm_del_timer(timer)); } diff --git a/components/driver/test_apps/mcpwm/sdkconfig.ci.iram_safe b/components/driver/test_apps/mcpwm/sdkconfig.ci.iram_safe index 9f7355c8cb..bf0d2b89c0 100644 --- a/components/driver/test_apps/mcpwm/sdkconfig.ci.iram_safe +++ b/components/driver/test_apps/mcpwm/sdkconfig.ci.iram_safe @@ -1,5 +1,6 @@ CONFIG_COMPILER_DUMP_RTL_FILES=y CONFIG_MCPWM_ISR_IRAM_SAFE=y +CONFIG_MCPWM_CTRL_FUNC_IN_IRAM=y CONFIG_GPIO_CTRL_FUNC_IN_IRAM=y CONFIG_COMPILER_OPTIMIZATION_NONE=y # silent the error check, as the error string are stored in rodata, causing RTL check failure diff --git a/components/driver/test_apps/pulse_cnt/main/CMakeLists.txt b/components/driver/test_apps/pulse_cnt/main/CMakeLists.txt index 4e70ee7087..3bfb46de82 100644 --- a/components/driver/test_apps/pulse_cnt/main/CMakeLists.txt +++ b/components/driver/test_apps/pulse_cnt/main/CMakeLists.txt @@ -1,7 +1,10 @@ set(srcs "test_app_main.c" "test_pulse_cnt_simulator.c" - "test_pulse_cnt.c" - "test_pulse_cnt_iram.c") + "test_pulse_cnt.c") + +if(CONFIG_PCNT_ISR_IRAM_SAFE) + list(APPEND srcs "test_pulse_cnt_iram.c") +endif() # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE diff --git a/components/driver/test_apps/pulse_cnt/main/test_pulse_cnt.c b/components/driver/test_apps/pulse_cnt/main/test_pulse_cnt.c index ff617383bf..e94944a8f3 100644 --- a/components/driver/test_apps/pulse_cnt/main/test_pulse_cnt.c +++ b/components/driver/test_apps/pulse_cnt/main/test_pulse_cnt.c @@ -281,8 +281,11 @@ TEST_CASE("pcnt_quadrature_decode_event", "[pcnt]") TEST_ASSERT_EQUAL(ESP_ERR_INVALID_STATE, pcnt_unit_add_watch_point(unit, 50)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_STATE, pcnt_unit_add_watch_point(unit, 100)); - // Clear internal counter, and make the watch points take effect +#if !SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE + // the above added watch point won't take effect at once, unless we clear the internal counter manually TEST_ESP_OK(pcnt_unit_clear_count(unit)); +#endif + // start unit should fail if it's not enabled yet TEST_ASSERT_EQUAL(ESP_ERR_INVALID_STATE, pcnt_unit_start(unit)); TEST_ESP_OK(pcnt_unit_enable(unit)); diff --git a/components/driver/test_apps/pulse_cnt/main/test_pulse_cnt_iram.c b/components/driver/test_apps/pulse_cnt/main/test_pulse_cnt_iram.c index e07c224df0..8803b17b10 100644 --- a/components/driver/test_apps/pulse_cnt/main/test_pulse_cnt_iram.c +++ b/components/driver/test_apps/pulse_cnt/main/test_pulse_cnt_iram.c @@ -10,16 +10,14 @@ #include "freertos/task.h" #include "freertos/semphr.h" #include "unity.h" +#include "unity_test_utils.h" #include "driver/pulse_cnt.h" #include "driver/gpio.h" #include "spi_flash_mmap.h" #include "esp_attr.h" #include "soc/soc_caps.h" -#include "esp_private/spi_flash_os.h" #include "test_pulse_cnt_board.h" -#if CONFIG_PCNT_ISR_IRAM_SAFE - static bool IRAM_ATTR test_pcnt_iram_safe_callback(pcnt_unit_handle_t unit, const pcnt_watch_event_data_t *event_data, void *user_data) { uint32_t *data = (uint32_t *)user_data; @@ -29,13 +27,10 @@ static bool IRAM_ATTR test_pcnt_iram_safe_callback(pcnt_unit_handle_t unit, cons return false; } -static void IRAM_ATTR test_pcnt_iram_simulation(int gpio_sig) +static void IRAM_ATTR test_simulate_input_post_cache_disable(void *args) { - // disable flash cache - spi_flash_guard_get()->start(); + int gpio_sig = (int)args; test_gpio_simulate_rising_edge(gpio_sig, 2); - // enable flash cache - spi_flash_guard_get()->end(); } TEST_CASE("pcnt_iram_interrupt_safe", "[pcnt]") @@ -83,8 +78,9 @@ TEST_CASE("pcnt_iram_interrupt_safe", "[pcnt]") printf("disable cache and check interrupt triggered\r\n"); TEST_ESP_OK(pcnt_unit_clear_count(unit)); - // the function that will disable the flash must be placed in the IRAM - test_pcnt_iram_simulation(TEST_PCNT_GPIO_A); + + // disable flash cache and run simulation + unity_utils_run_cache_disable_stub(test_simulate_input_post_cache_disable, (void *)TEST_PCNT_GPIO_A); // check if the interrupt has fired up TEST_ASSERT_EQUAL(1, num_of_event_triggered); @@ -101,5 +97,3 @@ TEST_CASE("pcnt_iram_interrupt_safe", "[pcnt]") TEST_ESP_OK(pcnt_del_channel(channelB)); TEST_ESP_OK(pcnt_del_unit(unit)); } - -#endif // CONFIG_PCNT_ISR_IRAM_SAFE diff --git a/components/driver/test_apps/rmt/main/CMakeLists.txt b/components/driver/test_apps/rmt/main/CMakeLists.txt index 84ab9ed8dd..c686daddcc 100644 --- a/components/driver/test_apps/rmt/main/CMakeLists.txt +++ b/components/driver/test_apps/rmt/main/CMakeLists.txt @@ -4,5 +4,9 @@ set(srcs "test_app_main.c" "test_rmt_rx.c" "test_util_rmt_encoders.c") +if(CONFIG_RMT_ISR_IRAM_SAFE) + list(APPEND srcs "test_rmt_iram.c") +endif() + idf_component_register(SRCS "${srcs}" WHOLE_ARCHIVE) diff --git a/components/driver/test_apps/rmt/main/test_rmt_iram.c b/components/driver/test_apps/rmt/main/test_rmt_iram.c new file mode 100644 index 0000000000..2efd2103ee --- /dev/null +++ b/components/driver/test_apps/rmt/main/test_rmt_iram.c @@ -0,0 +1,182 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include "sdkconfig.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "unity.h" +#include "unity_test_utils.h" +#include "driver/rmt_tx.h" +#include "driver/rmt_rx.h" +#include "driver/gpio.h" +#include "esp_timer.h" +#include "soc/soc_caps.h" +#include "test_util_rmt_encoders.h" + +static void IRAM_ATTR test_delay_post_cache_disable(void *args) +{ + esp_rom_delay_us(10000); +} + +static void test_rmt_tx_iram_safe(size_t mem_block_symbols, bool with_dma) +{ + rmt_tx_channel_config_t tx_channel_cfg = { + .mem_block_symbols = mem_block_symbols, + .clk_src = RMT_CLK_SRC_DEFAULT, + .resolution_hz = 10000000, // 10MHz, 1 tick = 0.1us (led strip needs a high resolution) + .trans_queue_depth = 4, + .gpio_num = 0, + .flags.with_dma = with_dma, + }; + printf("install tx channel\r\n"); + rmt_channel_handle_t tx_channel_multi_leds = NULL; + TEST_ESP_OK(rmt_new_tx_channel(&tx_channel_cfg, &tx_channel_multi_leds)); + printf("install led strip encoder\r\n"); + rmt_encoder_handle_t led_strip_encoder = NULL; + TEST_ESP_OK(test_rmt_new_led_strip_encoder(&led_strip_encoder)); + printf("enable tx channel\r\n"); + TEST_ESP_OK(rmt_enable(tx_channel_multi_leds)); + + // Mutiple LEDs (ping-pong in the background) + printf("ping pong transmission: light up 100 RGB LEDs\r\n"); + rmt_transmit_config_t transmit_config = { + .loop_count = 0, // no loop + }; + + const int test_led_num = 100; + uint8_t leds_grb[test_led_num * 3]; + // color: Material Design Green-A200 (#69F0AE) + for (int i = 0; i < test_led_num * 3; i += 3) { + leds_grb[i + 0] = 0xF0; + leds_grb[i + 1] = 0x69; + leds_grb[i + 2] = 0xAE; + } + printf("start transmission and stop immediately, only a few LEDs are light up\r\n"); + TEST_ESP_OK(rmt_transmit(tx_channel_multi_leds, led_strip_encoder, leds_grb, test_led_num * 3, &transmit_config)); + // this second transmission will stay in the queue and shouldn't be dispatched until we restart the tx channel later + TEST_ESP_OK(rmt_transmit(tx_channel_multi_leds, led_strip_encoder, leds_grb, test_led_num * 3, &transmit_config)); + + unity_utils_run_cache_disable_stub(test_delay_post_cache_disable, NULL); + + // color: Material Design Orange-900 (#E65100) + for (int i = 0; i < test_led_num * 3; i += 3) { + leds_grb[i + 0] = 0x51; + leds_grb[i + 1] = 0xE6; + leds_grb[i + 2] = 0x00; + } + TEST_ESP_OK(rmt_transmit(tx_channel_multi_leds, led_strip_encoder, leds_grb, test_led_num * 3, &transmit_config)); + TEST_ESP_OK(rmt_tx_wait_all_done(tx_channel_multi_leds, -1)); + + printf("disable tx channel\r\n"); + TEST_ESP_OK(rmt_disable(tx_channel_multi_leds)); + printf("remove tx channel and led strip encoder\r\n"); + TEST_ESP_OK(rmt_del_channel(tx_channel_multi_leds)); + TEST_ESP_OK(rmt_del_encoder(led_strip_encoder)); +} + +TEST_CASE("rmt_tx_iram_safe_no_dma", "[rmt]") +{ + test_rmt_tx_iram_safe(SOC_RMT_MEM_WORDS_PER_CHANNEL, false); +} + +#if SOC_RMT_SUPPORT_DMA +TEST_CASE("rmt_tx_iram_safe_with_dma", "[rmt]") +{ + test_rmt_tx_iram_safe(1024, true); +} +#endif + + +static void IRAM_ATTR test_simulate_input_post_cache_disable(void *args) +{ + int gpio_num = (int)args; + // simulate input signal, should only be recognized as one RMT symbol + gpio_set_level(gpio_num, 0); + esp_rom_delay_us(50); + gpio_set_level(gpio_num, 1); + esp_rom_delay_us(50); + gpio_set_level(gpio_num, 0); + esp_rom_delay_us(20000); +} + +typedef struct { + TaskHandle_t task_to_notify; + size_t received_symbol_num; +} test_nec_rx_user_data_t; + +IRAM_ATTR +static bool test_rmt_rx_done_callback(rmt_channel_handle_t channel, const rmt_rx_done_event_data_t *edata, void *user_data) +{ + BaseType_t high_task_wakeup = pdFALSE; + test_nec_rx_user_data_t *test_user_data = (test_nec_rx_user_data_t *)user_data; + test_user_data->received_symbol_num = edata->num_symbols; + vTaskNotifyGiveFromISR(test_user_data->task_to_notify, &high_task_wakeup); + return high_task_wakeup == pdTRUE; +} + +static void test_rmt_rx_iram_safe(size_t mem_block_symbols, bool with_dma, rmt_clock_source_t clk_src) +{ + rmt_rx_channel_config_t rx_channel_cfg = { + .clk_src = clk_src, + .resolution_hz = 1000000, // 1MHz, 1 tick = 1us + .mem_block_symbols = mem_block_symbols, + .gpio_num = 0, + .flags.with_dma = with_dma, + .flags.io_loop_back = true, // the GPIO will act like a loopback + }; + printf("install rx channel\r\n"); + rmt_channel_handle_t rx_channel = NULL; + TEST_ESP_OK(rmt_new_rx_channel(&rx_channel_cfg, &rx_channel)); + + // initialize the GPIO level to low + TEST_ESP_OK(gpio_set_level(0, 0)); + + printf("register rx event callbacks\r\n"); + rmt_rx_event_callbacks_t cbs = { + .on_recv_done = test_rmt_rx_done_callback, + }; + test_nec_rx_user_data_t test_user_data = { + .task_to_notify = xTaskGetCurrentTaskHandle(), + }; + TEST_ESP_OK(rmt_rx_register_event_callbacks(rx_channel, &cbs, &test_user_data)); + + printf("enable rx channel\r\n"); + TEST_ESP_OK(rmt_enable(rx_channel)); + + rmt_symbol_word_t remote_codes[128]; + + rmt_receive_config_t receive_config = { + .signal_range_min_ns = 1250, + .signal_range_max_ns = 12000000, + }; + + // ready to receive + TEST_ESP_OK(rmt_receive(rx_channel, remote_codes, sizeof(remote_codes), &receive_config)); + + // disable the flash cache, and simulate input signal by GPIO + unity_utils_run_cache_disable_stub(test_simulate_input_post_cache_disable, 0); + + TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdFALSE, pdMS_TO_TICKS(1000))); + TEST_ASSERT_EQUAL(1, test_user_data.received_symbol_num); + + printf("disable rx channels\r\n"); + TEST_ESP_OK(rmt_disable(rx_channel)); + printf("delete channels and encoder\r\n"); + TEST_ESP_OK(rmt_del_channel(rx_channel)); +} + +TEST_CASE("rmt_rx_iram_safe_no_dma", "[rmt]") +{ + test_rmt_rx_iram_safe(SOC_RMT_MEM_WORDS_PER_CHANNEL, false, RMT_CLK_SRC_DEFAULT); +} + +#if SOC_RMT_SUPPORT_DMA +TEST_CASE("rmt_rx_iram_safe_with_dma", "[rmt]") +{ + test_rmt_rx_iram_safe(128, true, RMT_CLK_SRC_DEFAULT); +} +#endif diff --git a/components/driver/test_apps/rmt/main/test_rmt_rx.c b/components/driver/test_apps/rmt/main/test_rmt_rx.c index 72559a4242..dfbcdac378 100644 --- a/components/driver/test_apps/rmt/main/test_rmt_rx.c +++ b/components/driver/test_apps/rmt/main/test_rmt_rx.c @@ -35,8 +35,8 @@ static bool test_rmt_rx_done_callback(rmt_channel_handle_t channel, const rmt_rx for (size_t i = 0; i < edata->num_symbols; i++) { esp_rom_printf("{%d:%d},{%d:%d}\r\n", remote_codes[i].level0, remote_codes[i].duration0, remote_codes[i].level1, remote_codes[i].duration1); } - vTaskNotifyGiveFromISR(test_user_data->task_to_notify, &high_task_wakeup); test_user_data->received_symbol_num = edata->num_symbols; + vTaskNotifyGiveFromISR(test_user_data->task_to_notify, &high_task_wakeup); return high_task_wakeup == pdTRUE; } @@ -100,7 +100,7 @@ static void test_rmt_rx_nec_carrier(size_t mem_block_symbols, bool with_dma, rmt 0x0440, 0x3003 // address, command }, 4, &transmit_config)); TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdFALSE, pdMS_TO_TICKS(1000))); - TEST_ASSERT_EQUAL(test_user_data.received_symbol_num, 34); + TEST_ASSERT_EQUAL(34, test_user_data.received_symbol_num); TEST_ESP_OK(rmt_receive(rx_channel, remote_codes, sizeof(remote_codes), &receive_config)); printf("send NEC frame without carrier\r\n"); @@ -108,7 +108,7 @@ static void test_rmt_rx_nec_carrier(size_t mem_block_symbols, bool with_dma, rmt 0x0440, 0x3003 // address, command }, 4, &transmit_config)); TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdFALSE, pdMS_TO_TICKS(1000))); - TEST_ASSERT_EQUAL(test_user_data.received_symbol_num, 34); + TEST_ASSERT_EQUAL(34, test_user_data.received_symbol_num); #if SOC_RMT_SUPPORT_RX_PINGPONG // ready to receive @@ -118,7 +118,7 @@ static void test_rmt_rx_nec_carrier(size_t mem_block_symbols, bool with_dma, rmt 0xFF00, 0xFF00, 0xFF00, 0xFF00 }, 8, &transmit_config)); TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdFALSE, pdMS_TO_TICKS(1000))); - TEST_ASSERT_EQUAL(test_user_data.received_symbol_num, 66); + TEST_ASSERT_EQUAL(66, test_user_data.received_symbol_num); #else // ready to receive TEST_ESP_OK(rmt_receive(rx_channel, remote_codes, sizeof(remote_codes), &receive_config)); @@ -150,7 +150,7 @@ static void test_rmt_rx_nec_carrier(size_t mem_block_symbols, bool with_dma, rmt 0x0440, 0x3003 // address, command }, 4, &transmit_config)); TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdFALSE, pdMS_TO_TICKS(1000))); - TEST_ASSERT_EQUAL(test_user_data.received_symbol_num, 34); + TEST_ASSERT_EQUAL(34, test_user_data.received_symbol_num); #if SOC_RMT_SUPPORT_RX_PINGPONG TEST_ESP_OK(rmt_receive(rx_channel, remote_codes, sizeof(remote_codes), &receive_config)); @@ -159,7 +159,7 @@ static void test_rmt_rx_nec_carrier(size_t mem_block_symbols, bool with_dma, rmt 0xFF00, 0xFF00, 0xFF00, 0xFF00 }, 8, &transmit_config)); TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdFALSE, pdMS_TO_TICKS(1000))); - TEST_ASSERT_EQUAL(test_user_data.received_symbol_num, 66); + TEST_ASSERT_EQUAL(66, test_user_data.received_symbol_num); #endif // SOC_RMT_SUPPORT_RX_PINGPONG printf("disable modulation and demodulation for tx and rx channels\r\n"); @@ -173,7 +173,7 @@ static void test_rmt_rx_nec_carrier(size_t mem_block_symbols, bool with_dma, rmt 0x0440, 0x3003 // address, command }, 4, &transmit_config)); TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdFALSE, pdMS_TO_TICKS(1000))); - TEST_ASSERT_EQUAL(test_user_data.received_symbol_num, 34); + TEST_ASSERT_EQUAL(34, test_user_data.received_symbol_num); TEST_ESP_OK(rmt_tx_wait_all_done(tx_channel, -1)); printf("disable tx and rx channels\r\n"); diff --git a/components/driver/test_apps/rmt/main/test_util_rmt_encoders.c b/components/driver/test_apps/rmt/main/test_util_rmt_encoders.c index e99bad5d53..ae69e35edb 100644 --- a/components/driver/test_apps/rmt/main/test_util_rmt_encoders.c +++ b/components/driver/test_apps/rmt/main/test_util_rmt_encoders.c @@ -6,8 +6,16 @@ #include #include #include +#include "sdkconfig.h" #include "unity.h" #include "driver/rmt_encoder.h" +#include "esp_attr.h" + +#if CONFIG_RMT_ISR_IRAM_SAFE +#define TEST_RMT_ENCODER_ATTR IRAM_ATTR +#else +#define TEST_RMT_ENCODER_ATTR +#endif typedef struct { rmt_encoder_t base; @@ -17,6 +25,7 @@ typedef struct { rmt_symbol_word_t reset_code; } rmt_led_strip_encoder_t; +TEST_RMT_ENCODER_ATTR static size_t rmt_encode_led_strip(rmt_encoder_t *encoder, rmt_channel_handle_t channel, const void *primary_data, size_t data_size, rmt_encode_state_t *ret_state) { rmt_led_strip_encoder_t *led_encoder = __containerof(encoder, rmt_led_strip_encoder_t, base); diff --git a/components/driver/test_apps/rmt/sdkconfig.ci.iram_safe b/components/driver/test_apps/rmt/sdkconfig.ci.iram_safe index 086b2260dd..3e489aef4b 100644 --- a/components/driver/test_apps/rmt/sdkconfig.ci.iram_safe +++ b/components/driver/test_apps/rmt/sdkconfig.ci.iram_safe @@ -1,5 +1,6 @@ CONFIG_COMPILER_DUMP_RTL_FILES=y CONFIG_RMT_ISR_IRAM_SAFE=y +CONFIG_GPIO_CTRL_FUNC_IN_IRAM=y CONFIG_COMPILER_OPTIMIZATION_NONE=y # silent the error check, as the error string are stored in rodata, causing RTL check failure CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT=y diff --git a/components/driver/test_apps/touch_sensor_v1/main/test_app_main.c b/components/driver/test_apps/touch_sensor_v1/main/test_app_main.c index 896caa3200..027d2b69c0 100644 --- a/components/driver/test_apps/touch_sensor_v1/main/test_app_main.c +++ b/components/driver/test_apps/touch_sensor_v1/main/test_app_main.c @@ -8,7 +8,7 @@ #include "unity_test_runner.h" #include "esp_heap_caps.h" -#define TEST_MEMORY_LEAK_THRESHOLD (-200) +#define TEST_MEMORY_LEAK_THRESHOLD (-300) static size_t before_free_8bit; static size_t before_free_32bit; diff --git a/components/driver/test_apps/touch_sensor_v1/main/test_touch_v1.c b/components/driver/test_apps/touch_sensor_v1/main/test_touch_v1.c index 350c550b47..b18a9100b5 100644 --- a/components/driver/test_apps/touch_sensor_v1/main/test_touch_v1.c +++ b/components/driver/test_apps/touch_sensor_v1/main/test_touch_v1.c @@ -209,8 +209,8 @@ TEST_CASE("Touch Sensor all channel read test", "[touch]") { #if CONFIG_PM_ENABLE esp_pm_lock_handle_t pm_lock; - esp_pm_lock_create(ESP_PM_NO_LIGHT_SLEEP, 0, "test_touch", &pm_lock); - esp_pm_lock_acquire(pm_lock); + TEST_ESP_OK(esp_pm_lock_create(ESP_PM_NO_LIGHT_SLEEP, 0, "test_touch", &pm_lock)); + TEST_ESP_OK(esp_pm_lock_acquire(pm_lock)); #endif TOUCH_REG_BASE_TEST(); test_touch_sw_read_test_runner(); @@ -218,8 +218,8 @@ TEST_CASE("Touch Sensor all channel read test", "[touch]") TEST_ESP_OK( test_touch_timer_read() ); TEST_ESP_OK( test_touch_filtered_read() ); #if CONFIG_PM_ENABLE - esp_pm_lock_release(pm_lock); - esp_pm_lock_delete(pm_lock); + TEST_ESP_OK(esp_pm_lock_release(pm_lock)); + TEST_ESP_OK(esp_pm_lock_delete(pm_lock)); #endif } @@ -237,7 +237,7 @@ static int test_touch_parameter(touch_pad_t pad_num, int meas_time, int slp_time touch_pad_set_cnt_mode(pad_num, slope, TOUCH_PAD_TIE_OPT_DEFAULT); // Initialize and start a software filter to detect slight change of capacitance. - touch_pad_filter_start(TOUCHPAD_FILTER_TOUCH_PERIOD); + TEST_ESP_OK(touch_pad_filter_start(TOUCHPAD_FILTER_TOUCH_PERIOD)); vTaskDelay(500 / portTICK_PERIOD_MS); // Start task to read values sensed by pads @@ -267,7 +267,7 @@ TEST_CASE("Touch Sensor parameters test", "[touch]") touch_val[1] = test_touch_parameter(touch_list[2], TOUCH_PAD_MEASURE_CYCLE_DEFAULT, TOUCH_PAD_SLEEP_CYCLE_DEFAULT, TOUCH_HVOLT_2V5, TOUCH_LVOLT_0V6, TOUCH_HVOLT_ATTEN_1V, TOUCH_PAD_SLOPE_DEFAULT); - touch_val[2] = test_touch_parameter(touch_list[0], TOUCH_PAD_MEASURE_CYCLE_DEFAULT, TOUCH_PAD_SLEEP_CYCLE_DEFAULT, + touch_val[2] = test_touch_parameter(touch_list[2], TOUCH_PAD_MEASURE_CYCLE_DEFAULT, TOUCH_PAD_SLEEP_CYCLE_DEFAULT, TOUCH_HVOLT_2V4, TOUCH_LVOLT_0V8, TOUCH_HVOLT_ATTEN_1V5, TOUCH_PAD_SLOPE_DEFAULT); @@ -302,7 +302,6 @@ static bool s_pad_activated[TOUCH_PAD_MAX]; static void test_touch_intr_cb(void *arg) { uint32_t pad_intr = touch_pad_get_status(); - esp_rom_printf("T%x ", pad_intr); //clear interrupt touch_pad_clear_status(); for (int i = 0; i < TEST_TOUCH_CHANNEL; i++) { diff --git a/components/driver/test_apps/touch_sensor_v1/pytest_touch_sensor_v1.py b/components/driver/test_apps/touch_sensor_v1/pytest_touch_sensor_v1.py index 86edab8560..5d1c07e26c 100644 --- a/components/driver/test_apps/touch_sensor_v1/pytest_touch_sensor_v1.py +++ b/components/driver/test_apps/touch_sensor_v1/pytest_touch_sensor_v1.py @@ -6,6 +6,13 @@ from pytest_embedded import Dut @pytest.mark.esp32 @pytest.mark.generic +@pytest.mark.parametrize( + 'config', + [ + 'release', + ], + indirect=True, +) def test_touch_sensor_v1(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests') dut.write('*') diff --git a/components/driver/test_apps/touch_sensor_v1/sdkconfig.ci.release b/components/driver/test_apps/touch_sensor_v1/sdkconfig.ci.release new file mode 100644 index 0000000000..91d93f163e --- /dev/null +++ b/components/driver/test_apps/touch_sensor_v1/sdkconfig.ci.release @@ -0,0 +1,5 @@ +CONFIG_PM_ENABLE=y +CONFIG_FREERTOS_USE_TICKLESS_IDLE=y +CONFIG_COMPILER_OPTIMIZATION_SIZE=y +CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y diff --git a/components/driver/test_apps/touch_sensor_v2/pytest_touch_sensor_v2.py b/components/driver/test_apps/touch_sensor_v2/pytest_touch_sensor_v2.py index f21311808c..18abe96fa7 100644 --- a/components/driver/test_apps/touch_sensor_v2/pytest_touch_sensor_v2.py +++ b/components/driver/test_apps/touch_sensor_v2/pytest_touch_sensor_v2.py @@ -7,6 +7,13 @@ from pytest_embedded import Dut @pytest.mark.esp32s2 @pytest.mark.esp32s3 @pytest.mark.generic +@pytest.mark.parametrize( + 'config', + [ + 'release', + ], + indirect=True, +) def test_touch_sensor_v2(dut: Dut) -> None: dut.expect_exact('Press ENTER to see the list of tests') dut.write('*') diff --git a/components/driver/test_apps/touch_sensor_v2/sdkconfig.ci.release b/components/driver/test_apps/touch_sensor_v2/sdkconfig.ci.release new file mode 100644 index 0000000000..91d93f163e --- /dev/null +++ b/components/driver/test_apps/touch_sensor_v2/sdkconfig.ci.release @@ -0,0 +1,5 @@ +CONFIG_PM_ENABLE=y +CONFIG_FREERTOS_USE_TICKLESS_IDLE=y +CONFIG_COMPILER_OPTIMIZATION_SIZE=y +CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y diff --git a/components/driver/uart.c b/components/driver/uart.c index ca67130f43..faa9677d56 100644 --- a/components/driver/uart.c +++ b/components/driver/uart.c @@ -17,8 +17,8 @@ #include "freertos/ringbuf.h" #include "hal/uart_hal.h" #include "hal/gpio_hal.h" +#include "hal/clk_tree_ll.h" #include "soc/uart_periph.h" -#include "soc/rtc_cntl_reg.h" #include "driver/uart.h" #include "driver/gpio.h" #include "driver/uart_select.h" @@ -199,6 +199,47 @@ static void uart_module_disable(uart_port_t uart_num) UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); } +esp_err_t uart_get_sclk_freq(uart_sclk_t sclk, uint32_t* out_freq_hz) +{ + uint32_t freq; + switch (sclk) { +#if SOC_UART_SUPPORT_APB_CLK + case UART_SCLK_APB: + freq = esp_clk_apb_freq(); + break; +#endif +#if SOC_UART_SUPPORT_AHB_CLK + case UART_SCLK_AHB: + freq = APB_CLK_FREQ; //This only exist on H2. Fix this when H2 MP is supported. + break; +#endif +#if SOC_UART_SUPPORT_PLL_F40M_CLK + case UART_SCLK_PLL_F40M: + freq = 40 * MHZ; + break; +#endif +#if SOC_UART_SUPPORT_REF_TICK + case UART_SCLK_REF_TICK: + freq = REF_CLK_FREQ; + break; +#endif +#if SOC_UART_SUPPORT_RTC_CLK + case UART_SCLK_RTC: + freq = RTC_CLK_FREQ; + break; +#endif +#if SOC_UART_SUPPORT_XTAL_CLK + case UART_SCLK_XTAL: + freq = esp_clk_xtal_freq(); + break; +#endif + default: + return ESP_ERR_INVALID_ARG; + } + *out_freq_hz = freq; + return ESP_OK; +} + esp_err_t uart_set_word_length(uart_port_t uart_num, uart_word_length_t data_bit) { ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error"); @@ -256,8 +297,15 @@ esp_err_t uart_get_parity(uart_port_t uart_num, uart_parity_t *parity_mode) esp_err_t uart_set_baudrate(uart_port_t uart_num, uint32_t baud_rate) { ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error"); + + uart_sclk_t src_clk; + uint32_t sclk_freq; + + uart_hal_get_sclk(&(uart_context[uart_num].hal), &src_clk); + ESP_RETURN_ON_ERROR(uart_get_sclk_freq(src_clk, &sclk_freq), UART_TAG, "Invalid src_clk"); + UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); - uart_hal_set_baudrate(&(uart_context[uart_num].hal), baud_rate); + uart_hal_set_baudrate(&(uart_context[uart_num].hal), baud_rate, sclk_freq); UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); return ESP_OK; } @@ -265,8 +313,15 @@ esp_err_t uart_set_baudrate(uart_port_t uart_num, uint32_t baud_rate) esp_err_t uart_get_baudrate(uart_port_t uart_num, uint32_t *baudrate) { ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error"); + + uart_sclk_t src_clk; + uint32_t sclk_freq; + + uart_hal_get_sclk(&(uart_context[uart_num].hal), &src_clk); + ESP_RETURN_ON_ERROR(uart_get_sclk_freq(src_clk, &sclk_freq), UART_TAG, "Invalid src_clk"); + UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); - uart_hal_get_baudrate(&(uart_context[uart_num].hal), baudrate); + uart_hal_get_baudrate(&(uart_context[uart_num].hal), baudrate, sclk_freq); UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); return ESP_OK; } @@ -688,10 +743,13 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf periph_rtc_dig_clk8m_enable(); } #endif + uint32_t sclk_freq; + ESP_RETURN_ON_ERROR(uart_get_sclk_freq(uart_config->source_clk, &sclk_freq), UART_TAG, "Invalid src_clk"); + UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); uart_hal_init(&(uart_context[uart_num].hal), uart_num); uart_hal_set_sclk(&(uart_context[uart_num].hal), uart_config->source_clk); - uart_hal_set_baudrate(&(uart_context[uart_num].hal), uart_config->baud_rate); + uart_hal_set_baudrate(&(uart_context[uart_num].hal), uart_config->baud_rate, sclk_freq); uart_hal_set_parity(&(uart_context[uart_num].hal), uart_config->parity); uart_hal_set_data_bit_num(&(uart_context[uart_num].hal), uart_config->data_bits); uart_hal_set_stop_bits(&(uart_context[uart_num].hal), uart_config->stop_bits); @@ -1084,6 +1142,9 @@ esp_err_t uart_wait_tx_done(uart_port_t uart_num, TickType_t ticks_to_wait) xSemaphoreGive(p_uart_obj[uart_num]->tx_mux); return ESP_OK; } + if (!UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX)) { + uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE); + } UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE); UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); diff --git a/components/driver/usb_serial_jtag.c b/components/driver/usb_serial_jtag.c index cdefb31469..94879aa117 100644 --- a/components/driver/usb_serial_jtag.c +++ b/components/driver/usb_serial_jtag.c @@ -8,6 +8,7 @@ #include #include "esp_log.h" #include "hal/usb_serial_jtag_ll.h" +#include "hal/usb_phy_ll.h" #include "freertos/FreeRTOS.h" #include "freertos/semphr.h" #include "freertos/ringbuf.h" @@ -112,6 +113,9 @@ esp_err_t usb_serial_jtag_driver_install(usb_serial_jtag_driver_config_t *usb_se goto _exit; } + // Configure PHY + usb_phy_ll_int_jtag_enable(&USB_SERIAL_JTAG); + usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY| USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT); usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY| diff --git a/components/efuse/efuse_table_gen.py b/components/efuse/efuse_table_gen.py index 0d6ea61394..df97626615 100755 --- a/components/efuse/efuse_table_gen.py +++ b/components/efuse/efuse_table_gen.py @@ -488,7 +488,7 @@ def main(): parser = argparse.ArgumentParser(description='ESP32 eFuse Manager') parser.add_argument('--idf_target', '-t', help='Target chip type', choices=['esp32', 'esp32s2', 'esp32s3', 'esp32c3', - 'esp32h2', 'esp32c2'], default='esp32') + 'esp32h2', 'esp32c2', 'esp32c6'], default='esp32') parser.add_argument('--quiet', '-q', help="Don't print non-critical status messages to stderr", action='store_true') parser.add_argument('--debug', help='Create header file with debug info', default=False, action='store_false') parser.add_argument('--info', help='Print info about range of used bits', default=False, action='store_true') diff --git a/components/efuse/esp32c2/esp_efuse_utility.c b/components/efuse/esp32c2/esp_efuse_utility.c index 2d3baf6d2b..37e5f4bd8a 100644 --- a/components/efuse/esp32c2/esp_efuse_utility.c +++ b/components/efuse/esp32c2/esp_efuse_utility.c @@ -42,7 +42,7 @@ const esp_efuse_range_addr_t range_write_addr_blocks[] = { // Update Efuse timing configuration static esp_err_t esp_efuse_set_timing(void) { - // no need to set special timing values + efuse_hal_set_timing(0); return ESP_OK; } #endif // ifndef CONFIG_EFUSE_VIRTUAL diff --git a/components/efuse/esp32c6/esp_efuse_fields.c b/components/efuse/esp32c6/esp_efuse_fields.c new file mode 100644 index 0000000000..ba55a94411 --- /dev/null +++ b/components/efuse/esp32c6/esp_efuse_fields.c @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_efuse.h" +#include "esp_efuse_utility.h" +#include "esp_efuse_table.h" +#include "stdlib.h" +#include "esp_types.h" +#include "esp32c6/rom/efuse.h" +#include "assert.h" +#include "esp_err.h" +#include "esp_log.h" +#include "soc/efuse_periph.h" +#include "bootloader_random.h" +#include "sys/param.h" + +static __attribute__((unused)) const char *TAG = "efuse"; + +// Contains functions that provide access to efuse fields which are often used in IDF. + +// Returns chip package from efuse +uint32_t esp_efuse_get_pkg_ver(void) +{ + uint32_t pkg_ver = 0; + esp_efuse_read_field_blob(ESP_EFUSE_PKG_VERSION, &pkg_ver, ESP_EFUSE_PKG_VERSION[0]->bit_count); + return pkg_ver; +} + + +esp_err_t esp_efuse_set_rom_log_scheme(esp_efuse_rom_log_scheme_t log_scheme) +{ + int cur_log_scheme = 0; + esp_efuse_read_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &cur_log_scheme, 2); + if (!cur_log_scheme) { // not burned yet + return esp_efuse_write_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &log_scheme, 2); + } else { + return ESP_ERR_INVALID_STATE; + } +} + +esp_err_t esp_efuse_disable_rom_download_mode(void) +{ + return esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE); +} + +esp_err_t esp_efuse_enable_rom_secure_download_mode(void) +{ + if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { + return ESP_ERR_INVALID_STATE; + } + return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); +} diff --git a/components/efuse/esp32c6/esp_efuse_rtc_calib.c b/components/efuse/esp32c6/esp_efuse_rtc_calib.c new file mode 100644 index 0000000000..4673a93995 --- /dev/null +++ b/components/efuse/esp32c6/esp_efuse_rtc_calib.c @@ -0,0 +1,95 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_efuse.h" +#include "esp_efuse_table.h" + +int esp_efuse_rtc_calib_get_ver(void) +{ + uint32_t result = 0; + esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &result, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count); // IDF-5366 + return result; +} + +uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int atten) +{ + assert(version == 1); + (void) adc_unit; + const esp_efuse_desc_t** init_code_efuse; + assert(atten < 4); + if (atten == 0) { + init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0; + } else if (atten == 1) { + init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN1; + } else if (atten == 2) { + init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN2; + } else { + init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN3; + } + + int init_code_size = esp_efuse_get_field_size(init_code_efuse); + assert(init_code_size == 10); + + uint32_t init_code = 0; + ESP_ERROR_CHECK(esp_efuse_read_field_blob(init_code_efuse, &init_code, init_code_size)); + return init_code + 1000; // version 1 logic +} + +esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t* out_digi, uint32_t* out_vol_mv) +{ + const esp_efuse_desc_t** cal_vol_efuse; + uint32_t calib_vol_expected_mv; + if (version != 1) { + return ESP_ERR_INVALID_ARG; + } + if (atten >= 4) { + return ESP_ERR_INVALID_ARG; + } + if (atten == 0) { + cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN0; + calib_vol_expected_mv = 400; + } else if (atten == 1) { + cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN1; + calib_vol_expected_mv = 550; + } else if (atten == 2) { + cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN2; + calib_vol_expected_mv = 750; + } else { + cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN3; + calib_vol_expected_mv = 1370; + } + + assert(cal_vol_efuse[0]->bit_count == 10); + + uint32_t cal_vol = 0; + ESP_ERROR_CHECK(esp_efuse_read_field_blob(cal_vol_efuse, &cal_vol, cal_vol_efuse[0]->bit_count)); + + *out_digi = 2000 + ((cal_vol & BIT(9))? -(cal_vol & ~BIT9): cal_vol); + *out_vol_mv = calib_vol_expected_mv; + return ESP_OK; +} + +esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal) +{ + uint32_t version = esp_efuse_rtc_calib_get_ver(); + if (version != 1) { + *tsens_cal = 0.0; + return ESP_ERR_NOT_SUPPORTED; + } + const esp_efuse_desc_t** cal_temp_efuse; + cal_temp_efuse = ESP_EFUSE_TEMP_CALIB; + int cal_temp_size = esp_efuse_get_field_size(cal_temp_efuse); + assert(cal_temp_size == 9); + + uint32_t cal_temp = 0; + esp_err_t err = esp_efuse_read_field_blob(cal_temp_efuse, &cal_temp, cal_temp_size); + assert(err == ESP_OK); + (void)err; + // BIT(8) stands for sign: 1: negtive, 0: positive + *tsens_cal = ((cal_temp & BIT(8)) != 0)? -(uint8_t)cal_temp: (uint8_t)cal_temp; + return ESP_OK; +} diff --git a/components/efuse/esp32c6/esp_efuse_table.c b/components/efuse/esp32c6/esp_efuse_table.c new file mode 100644 index 0000000000..a1f3859807 --- /dev/null +++ b/components/efuse/esp32c6/esp_efuse_table.c @@ -0,0 +1,1121 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include "esp_efuse.h" +#include +#include "esp_efuse_table.h" + +// md5_digest_table 5b3b6e026d28aacca6dc3b96be8bd280 +// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. +// If you want to change some fields, you need to change esp_efuse_table.csv file +// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. +// To show efuse_table run the command 'show_efuse_table'. + +static const esp_efuse_desc_t WR_DIS[] = { + {EFUSE_BLK0, 0, 32}, // Write protection, +}; + +static const esp_efuse_desc_t WR_DIS_RD_DIS[] = { + {EFUSE_BLK0, 0, 1}, // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2, +}; + +static const esp_efuse_desc_t WR_DIS_SWAP_UART_SDIO_EN[] = { + {EFUSE_BLK0, 1, 1}, // Write protection for SWAP_UART_SDIO_EN, +}; + +static const esp_efuse_desc_t WR_DIS_GROUP_1[] = { + {EFUSE_BLK0, 2, 1}, // Write protection for DIS_ICACHE DIS_USB_JTAG DIS_DOWNLOAD_ICACHE DIS_USB_SERIAL_JTAG DIS_FORCE_DOWNLOAD DIS_TWAI DIS_JTAG_SEL_ENABLE SOFT_DIS_JTAG DIS_PADJTAG DIS_DOWNLOAD_MANUAL_ENCRYPT, +}; + +static const esp_efuse_desc_t WR_DIS_GROUP_2[] = { + {EFUSE_BLK0, 3, 1}, // Write protection for WDT_DELAY_SEL, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = { + {EFUSE_BLK0, 4, 1}, // Write protection for SPI_BOOT_CRYPT_CNT, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { + {EFUSE_BLK0, 5, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE0, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { + {EFUSE_BLK0, 6, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE1, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { + {EFUSE_BLK0, 7, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE2, +}; + +static const esp_efuse_desc_t WR_DIS_KEY0_PURPOSE[] = { + {EFUSE_BLK0, 8, 1}, // Write protection for key_purpose. KEY0, +}; + +static const esp_efuse_desc_t WR_DIS_KEY1_PURPOSE[] = { + {EFUSE_BLK0, 9, 1}, // Write protection for key_purpose. KEY1, +}; + +static const esp_efuse_desc_t WR_DIS_KEY2_PURPOSE[] = { + {EFUSE_BLK0, 10, 1}, // Write protection for key_purpose. KEY2, +}; + +static const esp_efuse_desc_t WR_DIS_KEY3_PURPOSE[] = { + {EFUSE_BLK0, 11, 1}, // Write protection for key_purpose. KEY3, +}; + +static const esp_efuse_desc_t WR_DIS_KEY4_PURPOSE[] = { + {EFUSE_BLK0, 12, 1}, // Write protection for key_purpose. KEY4, +}; + +static const esp_efuse_desc_t WR_DIS_KEY5_PURPOSE[] = { + {EFUSE_BLK0, 13, 1}, // Write protection for key_purpose. KEY5, +}; + +static const esp_efuse_desc_t WR_DIS_SEC_DPA_LEVEL[] = { + {EFUSE_BLK0, 14, 1}, // Write protection for SEC_DPA_LEVEL, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = { + {EFUSE_BLK0, 15, 1}, // Write protection for SECURE_BOOT_EN, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + {EFUSE_BLK0, 16, 1}, // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE, +}; + +static const esp_efuse_desc_t WR_DIS_GROUP_3[] = { + {EFUSE_BLK0, 18, 1}, // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_PRINT DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROLFLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = { + {EFUSE_BLK0, 19, 1}, // Write protection for SECURE_BOOT_DISABLE_FAST_WAKE, +}; + +static const esp_efuse_desc_t WR_DIS_BLK1[] = { + {EFUSE_BLK0, 20, 1}, // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS, +}; + +static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = { + {EFUSE_BLK0, 21, 1}, // Write protection for EFUSE_BLK2. SYS_DATA_PART1, +}; + +static const esp_efuse_desc_t WR_DIS_USER_DATA[] = { + {EFUSE_BLK0, 22, 1}, // Write protection for EFUSE_BLK3. USER_DATA, +}; + +static const esp_efuse_desc_t WR_DIS_KEY0[] = { + {EFUSE_BLK0, 23, 1}, // Write protection for EFUSE_BLK4. KEY0, +}; + +static const esp_efuse_desc_t WR_DIS_KEY1[] = { + {EFUSE_BLK0, 24, 1}, // Write protection for EFUSE_BLK5. KEY1, +}; + +static const esp_efuse_desc_t WR_DIS_KEY2[] = { + {EFUSE_BLK0, 25, 1}, // Write protection for EFUSE_BLK6. KEY2, +}; + +static const esp_efuse_desc_t WR_DIS_KEY3[] = { + {EFUSE_BLK0, 26, 1}, // Write protection for EFUSE_BLK7. KEY3, +}; + +static const esp_efuse_desc_t WR_DIS_KEY4[] = { + {EFUSE_BLK0, 27, 1}, // Write protection for EFUSE_BLK8. KEY4, +}; + +static const esp_efuse_desc_t WR_DIS_KEY5[] = { + {EFUSE_BLK0, 28, 1}, // Write protection for EFUSE_BLK9. KEY5, +}; + +static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART2[] = { + {EFUSE_BLK0, 29, 1}, // Write protection for EFUSE_BLK10. SYS_DATA_PART2, +}; + +static const esp_efuse_desc_t RD_DIS[] = { + {EFUSE_BLK0, 32, 7}, // Read protection, +}; + +static const esp_efuse_desc_t RD_DIS_KEY0[] = { + {EFUSE_BLK0, 32, 1}, // Read protection for EFUSE_BLK4. KEY0, +}; + +static const esp_efuse_desc_t RD_DIS_KEY1[] = { + {EFUSE_BLK0, 33, 1}, // Read protection for EFUSE_BLK5. KEY1, +}; + +static const esp_efuse_desc_t RD_DIS_KEY2[] = { + {EFUSE_BLK0, 34, 1}, // Read protection for EFUSE_BLK6. KEY2, +}; + +static const esp_efuse_desc_t RD_DIS_KEY3[] = { + {EFUSE_BLK0, 35, 1}, // Read protection for EFUSE_BLK7. KEY3, +}; + +static const esp_efuse_desc_t RD_DIS_KEY4[] = { + {EFUSE_BLK0, 36, 1}, // Read protection for EFUSE_BLK8. KEY4, +}; + +static const esp_efuse_desc_t RD_DIS_KEY5[] = { + {EFUSE_BLK0, 37, 1}, // Read protection for EFUSE_BLK9. KEY5, +}; + +static const esp_efuse_desc_t RD_DIS_SYS_DATA_PART2[] = { + {EFUSE_BLK0, 38, 1}, // Read protection for EFUSE_BLK10. SYS_DATA_PART2, +}; + +static const esp_efuse_desc_t SWAP_UART_SDIO_EN[] = { + {EFUSE_BLK0, 39, 1}, // Swap pad of uart and sdio., +}; + +static const esp_efuse_desc_t DIS_ICACHE[] = { + {EFUSE_BLK0, 40, 1}, // Disable Icache, +}; + +static const esp_efuse_desc_t DIS_USB_JTAG[] = { + {EFUSE_BLK0, 41, 1}, // Disable USB JTAG, +}; + +static const esp_efuse_desc_t DIS_DOWNLOAD_ICACHE[] = { + {EFUSE_BLK0, 42, 1}, // Disable Icache in download mode, +}; + +static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG[] = { + {EFUSE_BLK0, 43, 1}, // Disable USB_SERIAL_JTAG, +}; + +static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = { + {EFUSE_BLK0, 44, 1}, // Disable force chip go to download mode function, +}; + +static const esp_efuse_desc_t DIS_TWAI[] = { + {EFUSE_BLK0, 46, 1}, // Disable TWAI function, +}; + +static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = { + {EFUSE_BLK0, 47, 1}, // Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0., +}; + +static const esp_efuse_desc_t SOFT_DIS_JTAG[] = { + {EFUSE_BLK0, 48, 3}, // Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module., +}; + +static const esp_efuse_desc_t DIS_PAD_JTAG[] = { + {EFUSE_BLK0, 51, 1}, // Disable JTAG in the hard way. JTAG is disabled permanently., +}; + +static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + {EFUSE_BLK0, 52, 1}, // Disable flash encryption when in download boot modes., +}; + +static const esp_efuse_desc_t USB_DREFH[] = { + {EFUSE_BLK0, 53, 2}, // Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse., +}; + +static const esp_efuse_desc_t USB_DREFL[] = { + {EFUSE_BLK0, 55, 2}, // Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse., +}; + +static const esp_efuse_desc_t USB_EXCHG_PINS[] = { + {EFUSE_BLK0, 57, 1}, // Exchange D+ D- pins, +}; + +static const esp_efuse_desc_t VDD_SPI_AS_GPIO[] = { + {EFUSE_BLK0, 58, 1}, // Set this bit to vdd spi pin function as gpio, +}; + +static const esp_efuse_desc_t WDT_DELAY_SEL[] = { + {EFUSE_BLK0, 80, 2}, // Select RTC WDT time out threshold, +}; + +static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = { + {EFUSE_BLK0, 82, 3}, // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable, +}; + +static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = { + {EFUSE_BLK0, 85, 1}, // Enable revoke first secure boot key, +}; + +static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = { + {EFUSE_BLK0, 86, 1}, // Enable revoke second secure boot key, +}; + +static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = { + {EFUSE_BLK0, 87, 1}, // Enable revoke third secure boot key, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_0[] = { + {EFUSE_BLK0, 88, 4}, // Key0 purpose, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_1[] = { + {EFUSE_BLK0, 92, 4}, // Key1 purpose, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_2[] = { + {EFUSE_BLK0, 96, 4}, // Key2 purpose, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_3[] = { + {EFUSE_BLK0, 100, 4}, // Key3 purpose, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_4[] = { + {EFUSE_BLK0, 104, 4}, // Key4 purpose, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_5[] = { + {EFUSE_BLK0, 108, 4}, // Key5 purpose, +}; + +static const esp_efuse_desc_t SEC_DPA_LEVEL[] = { + {EFUSE_BLK0, 112, 2}, // Configures the clock random divide mode to determine the spa secure level, +}; + +static const esp_efuse_desc_t SECURE_BOOT_EN[] = { + {EFUSE_BLK0, 116, 1}, // Secure boot enable, +}; + +static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + {EFUSE_BLK0, 117, 1}, // Enable aggressive secure boot revoke, +}; + +static const esp_efuse_desc_t FLASH_TPUW[] = { + {EFUSE_BLK0, 124, 4}, // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms, +}; + +static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 128, 1}, // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7, +}; + +static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = { + {EFUSE_BLK0, 129, 1}, // Disable direct boot mode, +}; + +static const esp_efuse_desc_t DIS_USB_PRINT[] = { + {EFUSE_BLK0, 130, 1}, // Disable USB Print, +}; + +static const esp_efuse_desc_t DIS_USB_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 132, 1}, // Disable download through USB, +}; + +static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = { + {EFUSE_BLK0, 133, 1}, // Enable security download mode, +}; + +static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { + {EFUSE_BLK0, 134, 2}, // b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print., +}; + +static const esp_efuse_desc_t FORCE_SEND_RESUME[] = { + {EFUSE_BLK0, 141, 1}, // Force ROM code to send a resume command during SPI boot, +}; + +static const esp_efuse_desc_t SECURE_VERSION[] = { + {EFUSE_BLK0, 142, 16}, // Secure version for anti-rollback, +}; + +static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK0, 160, 1}, // Disables check of wafer version major, +}; + +static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 161, 1}, // Disables check of blk version major, +}; + +static const esp_efuse_desc_t MAC_FACTORY[] = { + {EFUSE_BLK1, 40, 8}, // Factory MAC addr [0], + {EFUSE_BLK1, 32, 8}, // Factory MAC addr [1], + {EFUSE_BLK1, 24, 8}, // Factory MAC addr [2], + {EFUSE_BLK1, 16, 8}, // Factory MAC addr [3], + {EFUSE_BLK1, 8, 8}, // Factory MAC addr [4], + {EFUSE_BLK1, 0, 8}, // Factory MAC addr [5], +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_CLK[] = { + {EFUSE_BLK1, 48, 6}, // SPI_PAD_configure CLK, +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_Q_D1[] = { + {EFUSE_BLK1, 54, 6}, // SPI_PAD_configure Q(D1), +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_D_D0[] = { + {EFUSE_BLK1, 60, 6}, // SPI_PAD_configure D(D0), +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_CS[] = { + {EFUSE_BLK1, 66, 6}, // SPI_PAD_configure CS, +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_HD_D3[] = { + {EFUSE_BLK1, 72, 6}, // SPI_PAD_configure HD(D3), +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_WP_D2[] = { + {EFUSE_BLK1, 78, 6}, // SPI_PAD_configure WP(D2), +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_DQS[] = { + {EFUSE_BLK1, 84, 6}, // SPI_PAD_configure DQS, +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_D4[] = { + {EFUSE_BLK1, 90, 6}, // SPI_PAD_configure D4, +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_D5[] = { + {EFUSE_BLK1, 96, 6}, // SPI_PAD_configure D5, +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_D6[] = { + {EFUSE_BLK1, 102, 6}, // SPI_PAD_configure D6, +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = { + {EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7, +}; + +static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { + {EFUSE_BLK1, 114, 3}, // WAFER_VERSION_MINOR least significant bits, + {EFUSE_BLK1, 183, 1}, // WAFER_VERSION_MINOR most significant bit, +}; + +static const esp_efuse_desc_t PKG_VERSION[] = { + {EFUSE_BLK1, 117, 3}, // Package version 0:ESP32C3, +}; + +static const esp_efuse_desc_t BLK_VERSION_MINOR[] = { + {EFUSE_BLK1, 120, 3}, // BLK_VERSION_MINOR, +}; + +static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK1, 184, 2}, // WAFER_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { + {EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID, +}; + +static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { + {EFUSE_BLK2, 128, 2}, // BLK_VERSION_MAJOR of BLOCK2, +}; + +static const esp_efuse_desc_t TEMP_CALIB[] = { + {EFUSE_BLK2, 131, 9}, // Temperature calibration data, +}; + +static const esp_efuse_desc_t OCODE[] = { + {EFUSE_BLK2, 140, 8}, // ADC OCode, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = { + {EFUSE_BLK2, 148, 10}, // ADC1 init code at atten0, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN1[] = { + {EFUSE_BLK2, 158, 10}, // ADC1 init code at atten1, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN2[] = { + {EFUSE_BLK2, 168, 10}, // ADC1 init code at atten2, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = { + {EFUSE_BLK2, 178, 10}, // ADC1 init code at atten3, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = { + {EFUSE_BLK2, 188, 10}, // ADC1 calibration voltage at atten0, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN1[] = { + {EFUSE_BLK2, 198, 10}, // ADC1 calibration voltage at atten1, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN2[] = { + {EFUSE_BLK2, 208, 10}, // ADC1 calibration voltage at atten2, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = { + {EFUSE_BLK2, 218, 10}, // ADC1 calibration voltage at atten3, +}; + +static const esp_efuse_desc_t USER_DATA[] = { + {EFUSE_BLK3, 0, 256}, // User data, +}; + +static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = { + {EFUSE_BLK3, 200, 48}, // Custom MAC, +}; + +static const esp_efuse_desc_t KEY0[] = { + {EFUSE_BLK4, 0, 256}, // Key0 or user data, +}; + +static const esp_efuse_desc_t KEY1[] = { + {EFUSE_BLK5, 0, 256}, // Key1 or user data, +}; + +static const esp_efuse_desc_t KEY2[] = { + {EFUSE_BLK6, 0, 256}, // Key2 or user data, +}; + +static const esp_efuse_desc_t KEY3[] = { + {EFUSE_BLK7, 0, 256}, // Key3 or user data, +}; + +static const esp_efuse_desc_t KEY4[] = { + {EFUSE_BLK8, 0, 256}, // Key4 or user data, +}; + +static const esp_efuse_desc_t KEY5[] = { + {EFUSE_BLK9, 0, 256}, // Key5 or user data, +}; + +static const esp_efuse_desc_t SYS_DATA_PART2[] = { + {EFUSE_BLK10, 0, 256}, // System configuration, +}; + +static const esp_efuse_desc_t K_RTC_LDO[] = { + {EFUSE_BLK1, 135, 7}, // BLOCK1 K_RTC_LDO, +}; + +static const esp_efuse_desc_t K_DIG_LDO[] = { + {EFUSE_BLK1, 142, 7}, // BLOCK1 K_DIG_LDO, +}; + +static const esp_efuse_desc_t V_RTC_DBIAS20[] = { + {EFUSE_BLK1, 149, 8}, // BLOCK1 voltage of rtc dbias20, +}; + +static const esp_efuse_desc_t V_DIG_DBIAS20[] = { + {EFUSE_BLK1, 157, 8}, // BLOCK1 voltage of digital dbias20, +}; + +static const esp_efuse_desc_t DIG_DBIAS_HVT[] = { + {EFUSE_BLK1, 165, 5}, // BLOCK1 digital dbias when hvt, +}; + +static const esp_efuse_desc_t THRES_HVT[] = { + {EFUSE_BLK1, 170, 10}, // BLOCK1 pvt threshold when hvt, +}; + + + + + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[] = { + &WR_DIS[0], // Write protection + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = { + &WR_DIS_RD_DIS[0], // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SWAP_UART_SDIO_EN[] = { + &WR_DIS_SWAP_UART_SDIO_EN[0], // Write protection for SWAP_UART_SDIO_EN + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[] = { + &WR_DIS_GROUP_1[0], // Write protection for DIS_ICACHE DIS_USB_JTAG DIS_DOWNLOAD_ICACHE DIS_USB_SERIAL_JTAG DIS_FORCE_DOWNLOAD DIS_TWAI DIS_JTAG_SEL_ENABLE SOFT_DIS_JTAG DIS_PADJTAG DIS_DOWNLOAD_MANUAL_ENCRYPT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[] = { + &WR_DIS_GROUP_2[0], // Write protection for WDT_DELAY_SEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = { + &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // Write protection for SPI_BOOT_CRYPT_CNT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { + &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], // Write protection for SECURE_BOOT_KEY_REVOKE0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { + &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], // Write protection for SECURE_BOOT_KEY_REVOKE1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { + &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], // Write protection for SECURE_BOOT_KEY_REVOKE2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[] = { + &WR_DIS_KEY0_PURPOSE[0], // Write protection for key_purpose. KEY0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[] = { + &WR_DIS_KEY1_PURPOSE[0], // Write protection for key_purpose. KEY1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[] = { + &WR_DIS_KEY2_PURPOSE[0], // Write protection for key_purpose. KEY2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[] = { + &WR_DIS_KEY3_PURPOSE[0], // Write protection for key_purpose. KEY3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[] = { + &WR_DIS_KEY4_PURPOSE[0], // Write protection for key_purpose. KEY4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[] = { + &WR_DIS_KEY5_PURPOSE[0], // Write protection for key_purpose. KEY5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[] = { + &WR_DIS_SEC_DPA_LEVEL[0], // Write protection for SEC_DPA_LEVEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = { + &WR_DIS_SECURE_BOOT_EN[0], // Write protection for SECURE_BOOT_EN + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[] = { + &WR_DIS_GROUP_3[0], // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_PRINT DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROLFLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = { + &WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[0], // Write protection for SECURE_BOOT_DISABLE_FAST_WAKE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = { + &WR_DIS_BLK1[0], // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { + &WR_DIS_SYS_DATA_PART1[0], // Write protection for EFUSE_BLK2. SYS_DATA_PART1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[] = { + &WR_DIS_USER_DATA[0], // Write protection for EFUSE_BLK3. USER_DATA + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[] = { + &WR_DIS_KEY0[0], // Write protection for EFUSE_BLK4. KEY0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[] = { + &WR_DIS_KEY1[0], // Write protection for EFUSE_BLK5. KEY1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[] = { + &WR_DIS_KEY2[0], // Write protection for EFUSE_BLK6. KEY2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[] = { + &WR_DIS_KEY3[0], // Write protection for EFUSE_BLK7. KEY3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[] = { + &WR_DIS_KEY4[0], // Write protection for EFUSE_BLK8. KEY4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[] = { + &WR_DIS_KEY5[0], // Write protection for EFUSE_BLK9. KEY5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[] = { + &WR_DIS_SYS_DATA_PART2[0], // Write protection for EFUSE_BLK10. SYS_DATA_PART2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = { + &RD_DIS[0], // Read protection + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[] = { + &RD_DIS_KEY0[0], // Read protection for EFUSE_BLK4. KEY0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[] = { + &RD_DIS_KEY1[0], // Read protection for EFUSE_BLK5. KEY1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[] = { + &RD_DIS_KEY2[0], // Read protection for EFUSE_BLK6. KEY2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[] = { + &RD_DIS_KEY3[0], // Read protection for EFUSE_BLK7. KEY3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[] = { + &RD_DIS_KEY4[0], // Read protection for EFUSE_BLK8. KEY4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[] = { + &RD_DIS_KEY5[0], // Read protection for EFUSE_BLK9. KEY5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = { + &RD_DIS_SYS_DATA_PART2[0], // Read protection for EFUSE_BLK10. SYS_DATA_PART2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SWAP_UART_SDIO_EN[] = { + &SWAP_UART_SDIO_EN[0], // Swap pad of uart and sdio. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = { + &DIS_ICACHE[0], // Disable Icache + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = { + &DIS_USB_JTAG[0], // Disable USB JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[] = { + &DIS_DOWNLOAD_ICACHE[0], // Disable Icache in download mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[] = { + &DIS_USB_SERIAL_JTAG[0], // Disable USB_SERIAL_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = { + &DIS_FORCE_DOWNLOAD[0], // Disable force chip go to download mode function + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = { + &DIS_TWAI[0], // Disable TWAI function + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = { + &JTAG_SEL_ENABLE[0], // Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = { + &SOFT_DIS_JTAG[0], // Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = { + &DIS_PAD_JTAG[0], // Disable JTAG in the hard way. JTAG is disabled permanently. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // Disable flash encryption when in download boot modes. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[] = { + &USB_DREFH[0], // Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[] = { + &USB_DREFL[0], // Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = { + &USB_EXCHG_PINS[0], // Exchange D+ D- pins + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[] = { + &VDD_SPI_AS_GPIO[0], // Set this bit to vdd spi pin function as gpio + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = { + &WDT_DELAY_SEL[0], // Select RTC WDT time out threshold + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = { + &SPI_BOOT_CRYPT_CNT[0], // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = { + &SECURE_BOOT_KEY_REVOKE0[0], // Enable revoke first secure boot key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = { + &SECURE_BOOT_KEY_REVOKE1[0], // Enable revoke second secure boot key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = { + &SECURE_BOOT_KEY_REVOKE2[0], // Enable revoke third secure boot key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = { + &KEY_PURPOSE_0[0], // Key0 purpose + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = { + &KEY_PURPOSE_1[0], // Key1 purpose + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = { + &KEY_PURPOSE_2[0], // Key2 purpose + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = { + &KEY_PURPOSE_3[0], // Key3 purpose + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = { + &KEY_PURPOSE_4[0], // Key4 purpose + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = { + &KEY_PURPOSE_5[0], // Key5 purpose + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = { + &SEC_DPA_LEVEL[0], // Configures the clock random divide mode to determine the spa secure level + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = { + &SECURE_BOOT_EN[0], // Secure boot enable + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Enable aggressive secure boot revoke + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = { + &FLASH_TPUW[0], // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { + &DIS_DOWNLOAD_MODE[0], // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = { + &DIS_DIRECT_BOOT[0], // Disable direct boot mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_PRINT[] = { + &DIS_USB_PRINT[0], // Disable USB Print + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[] = { + &DIS_USB_DOWNLOAD_MODE[0], // Disable download through USB + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = { + &ENABLE_SECURITY_DOWNLOAD[0], // Enable security download mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = { + &UART_PRINT_CONTROL[0], // b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = { + &FORCE_SEND_RESUME[0], // Force ROM code to send a resume command during SPI boot + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = { + &SECURE_VERSION[0], // Secure version for anti-rollback + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = { + &DISABLE_WAFER_VERSION_MAJOR[0], // Disables check of wafer version major + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = { + &DISABLE_BLK_VERSION_MAJOR[0], // Disables check of blk version major + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = { + &MAC_FACTORY[0], // Factory MAC addr [0] + &MAC_FACTORY[1], // Factory MAC addr [1] + &MAC_FACTORY[2], // Factory MAC addr [2] + &MAC_FACTORY[3], // Factory MAC addr [3] + &MAC_FACTORY[4], // Factory MAC addr [4] + &MAC_FACTORY[5], // Factory MAC addr [5] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[] = { + &SPI_PAD_CONFIG_CLK[0], // SPI_PAD_configure CLK + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[] = { + &SPI_PAD_CONFIG_Q_D1[0], // SPI_PAD_configure Q(D1) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[] = { + &SPI_PAD_CONFIG_D_D0[0], // SPI_PAD_configure D(D0) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[] = { + &SPI_PAD_CONFIG_CS[0], // SPI_PAD_configure CS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[] = { + &SPI_PAD_CONFIG_HD_D3[0], // SPI_PAD_configure HD(D3) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[] = { + &SPI_PAD_CONFIG_WP_D2[0], // SPI_PAD_configure WP(D2) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[] = { + &SPI_PAD_CONFIG_DQS[0], // SPI_PAD_configure DQS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[] = { + &SPI_PAD_CONFIG_D4[0], // SPI_PAD_configure D4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[] = { + &SPI_PAD_CONFIG_D5[0], // SPI_PAD_configure D5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[] = { + &SPI_PAD_CONFIG_D6[0], // SPI_PAD_configure D6 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = { + &SPI_PAD_CONFIG_D7[0], // SPI_PAD_configure D7 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = { + &WAFER_VERSION_MINOR[0], // WAFER_VERSION_MINOR least significant bits + &WAFER_VERSION_MINOR[1], // WAFER_VERSION_MINOR most significant bit + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { + &PKG_VERSION[0], // Package version 0:ESP32C3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = { + &BLK_VERSION_MINOR[0], // BLK_VERSION_MINOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = { + &WAFER_VERSION_MAJOR[0], // WAFER_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { + &OPTIONAL_UNIQUE_ID[0], // Optional unique 128-bit ID + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { + &BLK_VERSION_MAJOR[0], // BLK_VERSION_MAJOR of BLOCK2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = { + &TEMP_CALIB[0], // Temperature calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = { + &OCODE[0], // ADC OCode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = { + &ADC1_INIT_CODE_ATTEN0[0], // ADC1 init code at atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[] = { + &ADC1_INIT_CODE_ATTEN1[0], // ADC1 init code at atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[] = { + &ADC1_INIT_CODE_ATTEN2[0], // ADC1 init code at atten2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = { + &ADC1_INIT_CODE_ATTEN3[0], // ADC1 init code at atten3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = { + &ADC1_CAL_VOL_ATTEN0[0], // ADC1 calibration voltage at atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[] = { + &ADC1_CAL_VOL_ATTEN1[0], // ADC1 calibration voltage at atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[] = { + &ADC1_CAL_VOL_ATTEN2[0], // ADC1 calibration voltage at atten2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = { + &ADC1_CAL_VOL_ATTEN3[0], // ADC1 calibration voltage at atten3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = { + &USER_DATA[0], // User data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = { + &USER_DATA_MAC_CUSTOM[0], // Custom MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = { + &KEY0[0], // Key0 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = { + &KEY1[0], // Key1 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = { + &KEY2[0], // Key2 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = { + &KEY3[0], // Key3 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = { + &KEY4[0], // Key4 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = { + &KEY5[0], // Key5 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = { + &SYS_DATA_PART2[0], // System configuration + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[] = { + &K_RTC_LDO[0], // BLOCK1 K_RTC_LDO + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[] = { + &K_DIG_LDO[0], // BLOCK1 K_DIG_LDO + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[] = { + &V_RTC_DBIAS20[0], // BLOCK1 voltage of rtc dbias20 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[] = { + &V_DIG_DBIAS20[0], // BLOCK1 voltage of digital dbias20 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[] = { + &DIG_DBIAS_HVT[0], // BLOCK1 digital dbias when hvt + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[] = { + &THRES_HVT[0], // BLOCK1 pvt threshold when hvt + NULL +}; diff --git a/components/efuse/esp32c6/esp_efuse_table.csv b/components/efuse/esp32c6/esp_efuse_table.csv new file mode 100644 index 0000000000..c7a34c4308 --- /dev/null +++ b/components/efuse/esp32c6/esp_efuse_table.csv @@ -0,0 +1,178 @@ +# field_name, | efuse_block, | bit_start, | bit_count, |comment # +# | (EFUSE_BLK0 | (0..255) | (1..-) | # +# | EFUSE_BLK1 | |MAX_BLK_LEN*| # +# | ... | | | # +# | EFUSE_BLK10)| | | # +########################################################################## +# *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128. +# !!!!!!!!!!! # +# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table" +# this will generate new source files, next rebuild all the sources. +# !!!!!!!!!!! # + +# EFUSE_RD_REPEAT_DATA BLOCK # +############################## + # EFUSE_RD_WR_DIS_REG # + WR_DIS, EFUSE_BLK0, 0, 32, Write protection + WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2 + WR_DIS.SWAP_UART_SDIO_EN, EFUSE_BLK0, 1, 1, Write protection for SWAP_UART_SDIO_EN + WR_DIS.GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_USB_JTAG DIS_DOWNLOAD_ICACHE DIS_USB_SERIAL_JTAG DIS_FORCE_DOWNLOAD DIS_TWAI DIS_JTAG_SEL_ENABLE SOFT_DIS_JTAG DIS_PADJTAG DIS_DOWNLOAD_MANUAL_ENCRYPT + WR_DIS.GROUP_2, EFUSE_BLK0, 3, 1, Write protection for WDT_DELAY_SEL + WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT + WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0, 5, 1, Write protection for SECURE_BOOT_KEY_REVOKE0 + WR_DIS.SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0, 6, 1, Write protection for SECURE_BOOT_KEY_REVOKE1 + WR_DIS.SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0, 7, 1, Write protection for SECURE_BOOT_KEY_REVOKE2 + WR_DIS.KEY0_PURPOSE, EFUSE_BLK0, 8, 1, Write protection for key_purpose. KEY0 + WR_DIS.KEY1_PURPOSE, EFUSE_BLK0, 9, 1, Write protection for key_purpose. KEY1 + WR_DIS.KEY2_PURPOSE, EFUSE_BLK0, 10, 1, Write protection for key_purpose. KEY2 + WR_DIS.KEY3_PURPOSE, EFUSE_BLK0, 11, 1, Write protection for key_purpose. KEY3 + WR_DIS.KEY4_PURPOSE, EFUSE_BLK0, 12, 1, Write protection for key_purpose. KEY4 + WR_DIS.KEY5_PURPOSE, EFUSE_BLK0, 13, 1, Write protection for key_purpose. KEY5 + WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, Write protection for SEC_DPA_LEVEL + WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, Write protection for SECURE_BOOT_EN + WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1, Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE + WR_DIS.GROUP_3, EFUSE_BLK0, 18, 1, Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_PRINT DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROLFLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION + WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE,EFUSE_BLK0, 19, 1, Write protection for SECURE_BOOT_DISABLE_FAST_WAKE + WR_DIS.BLK1, EFUSE_BLK0, 20, 1, Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS + WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART1 + WR_DIS.USER_DATA, EFUSE_BLK0, 22, 1, Write protection for EFUSE_BLK3. USER_DATA + WR_DIS.KEY0, EFUSE_BLK0, 23, 1, Write protection for EFUSE_BLK4. KEY0 + WR_DIS.KEY1, EFUSE_BLK0, 24, 1, Write protection for EFUSE_BLK5. KEY1 + WR_DIS.KEY2, EFUSE_BLK0, 25, 1, Write protection for EFUSE_BLK6. KEY2 + WR_DIS.KEY3, EFUSE_BLK0, 26, 1, Write protection for EFUSE_BLK7. KEY3 + WR_DIS.KEY4, EFUSE_BLK0, 27, 1, Write protection for EFUSE_BLK8. KEY4 + WR_DIS.KEY5, EFUSE_BLK0, 28, 1, Write protection for EFUSE_BLK9. KEY5 + WR_DIS.SYS_DATA_PART2, EFUSE_BLK0, 29, 1, Write protection for EFUSE_BLK10. SYS_DATA_PART2 + + # EFUSE_RD_REPEAT_DATA0_REG # + RD_DIS, EFUSE_BLK0, 32, 7, Read protection + RD_DIS.KEY0, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK4. KEY0 + RD_DIS.KEY1, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK5. KEY1 + RD_DIS.KEY2, EFUSE_BLK0, 34, 1, Read protection for EFUSE_BLK6. KEY2 + RD_DIS.KEY3, EFUSE_BLK0, 35, 1, Read protection for EFUSE_BLK7. KEY3 + RD_DIS.KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4 + RD_DIS.KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5 + RD_DIS.SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2 + SWAP_UART_SDIO_EN, EFUSE_BLK0, 39, 1, Swap pad of uart and sdio. + DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache + DIS_USB_JTAG, EFUSE_BLK0, 41, 1, Disable USB JTAG + DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode + DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 43, 1, Disable USB_SERIAL_JTAG + DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function + DIS_TWAI, EFUSE_BLK0, 46, 1, Disable TWAI function + JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. + SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module. + DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, Disable JTAG in the hard way. JTAG is disabled permanently. + DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, Disable flash encryption when in download boot modes. + USB_DREFH, EFUSE_BLK0, 53, 2, Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse. + USB_DREFL, EFUSE_BLK0, 55, 2, Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse. + USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, Exchange D+ D- pins + VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, Set this bit to vdd spi pin function as gpio + + + # EFUSE_RD_REPEAT_DATA1_REG # + WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, Select RTC WDT time out threshold + SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable + SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, Enable revoke first secure boot key + SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, Enable revoke second secure boot key + SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, Enable revoke third secure boot key + KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, Key0 purpose + KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, Key1 purpose + + # EFUSE_RD_REPEAT_DATA2_REG # + KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, Key2 purpose + KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose + KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose + KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose + SEC_DPA_LEVEL, EFUSE_BLK0, 112, 2, Configures the clock random divide mode to determine the spa secure level + SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable + SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke + FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms + + # EFUSE_RD_REPEAT_DATA3_REG # + DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 + DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, Disable direct boot mode + DIS_USB_PRINT, EFUSE_BLK0, 130, 1, Disable USB Print + DIS_USB_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, Disable download through USB + ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable security download mode + UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print. + FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot + SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback + + # EFUSE_RD_REPEAT_DATA4_REG # + DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major + DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major + +# MAC_SPI_SYS BLOCK# +####################### + # RD_MAC_SPI_SYS_0 - RD_MAC_SPI_SYS_2 + MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0] + , EFUSE_BLK1, 32, 8, Factory MAC addr [1] + , EFUSE_BLK1, 24, 8, Factory MAC addr [2] + , EFUSE_BLK1, 16, 8, Factory MAC addr [3] + , EFUSE_BLK1, 8, 8, Factory MAC addr [4] + , EFUSE_BLK1, 0, 8, Factory MAC addr [5] + SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK + SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1) + SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0) + SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS + SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3) + SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2) + SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS + SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4 + SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5 + + # RD_MAC_SPI_SYS_3 + SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6 + SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7 + WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, WAFER_VERSION_MINOR least significant bits + , EFUSE_BLK1, 183, 1, WAFER_VERSION_MINOR most significant bit + # WAFER_VERSION_MINOR most significant bit is from RD_MAC_SPI_SYS_5 + PKG_VERSION, EFUSE_BLK1, 117, 3, Package version 0:ESP32C3 + BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, BLK_VERSION_MINOR + + # RD_MAC_SPI_SYS_5 + # WAFER_VERSION_MINOR most significant bit + WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, WAFER_VERSION_MAJOR + +# SYS_DATA_PART1 BLOCK# - System configuration +####################### + # RD_SYS_PART1_DATA0 - rd_sys_part1_data3 + OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID + + # RD_SYS_PART1_DATA4 + BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, BLK_VERSION_MAJOR of BLOCK2 + TEMP_CALIB, EFUSE_BLK2, 131, 9, Temperature calibration data + OCODE, EFUSE_BLK2, 140, 8, ADC OCode + ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 148, 10, ADC1 init code at atten0 + ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 158, 10, ADC1 init code at atten1 + + # RD_SYS_PART1_DATA5 + ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 168, 10, ADC1 init code at atten2 + ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 178, 10, ADC1 init code at atten3 + ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 188, 10, ADC1 calibration voltage at atten0 + ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 198, 10, ADC1 calibration voltage at atten1 + ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 208, 10, ADC1 calibration voltage at atten2 + ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 218, 10, ADC1 calibration voltage at atten3 + +################ +USER_DATA, EFUSE_BLK3, 0, 256, User data +USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, Custom MAC + +################ +KEY0, EFUSE_BLK4, 0, 256, Key0 or user data +KEY1, EFUSE_BLK5, 0, 256, Key1 or user data +KEY2, EFUSE_BLK6, 0, 256, Key2 or user data +KEY3, EFUSE_BLK7, 0, 256, Key3 or user data +KEY4, EFUSE_BLK8, 0, 256, Key4 or user data +KEY5, EFUSE_BLK9, 0, 256, Key5 or user data +SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration + +# AUTO CONFIG DIG&RTC DBIAS# +################ +K_RTC_LDO, EFUSE_BLK1, 135, 7, BLOCK1 K_RTC_LDO +K_DIG_LDO, EFUSE_BLK1, 142, 7, BLOCK1 K_DIG_LDO +V_RTC_DBIAS20, EFUSE_BLK1, 149, 8, BLOCK1 voltage of rtc dbias20 +V_DIG_DBIAS20, EFUSE_BLK1, 157, 8, BLOCK1 voltage of digital dbias20 +DIG_DBIAS_HVT, EFUSE_BLK1, 165, 5, BLOCK1 digital dbias when hvt +THRES_HVT, EFUSE_BLK1, 170, 10, BLOCK1 pvt threshold when hvt diff --git a/components/efuse/esp32c6/esp_efuse_utility.c b/components/efuse/esp32c6/esp_efuse_utility.c new file mode 100644 index 0000000000..689a8ca9cb --- /dev/null +++ b/components/efuse/esp32c6/esp_efuse_utility.c @@ -0,0 +1,215 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "sdkconfig.h" +#include "esp_log.h" +#include "assert.h" +#include "esp_efuse_utility.h" +#include "soc/efuse_periph.h" +#include "hal/efuse_hal.h" + +static const char *TAG = "efuse"; + +#ifdef CONFIG_EFUSE_VIRTUAL +extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK]; +#endif // CONFIG_EFUSE_VIRTUAL + +/*Range addresses to read blocks*/ +const esp_efuse_range_addr_t range_read_addr_blocks[] = { + {EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT + {EFUSE_RD_MAC_SPI_SYS_0_REG, EFUSE_RD_MAC_SPI_SYS_5_REG}, // range address of EFUSE_BLK1 MAC_SPI_8M + {EFUSE_RD_SYS_PART1_DATA0_REG, EFUSE_RD_SYS_PART1_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA + {EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA + {EFUSE_RD_KEY0_DATA0_REG, EFUSE_RD_KEY0_DATA7_REG}, // range address of EFUSE_BLK4 KEY0 + {EFUSE_RD_KEY1_DATA0_REG, EFUSE_RD_KEY1_DATA7_REG}, // range address of EFUSE_BLK5 KEY1 + {EFUSE_RD_KEY2_DATA0_REG, EFUSE_RD_KEY2_DATA7_REG}, // range address of EFUSE_BLK6 KEY2 + {EFUSE_RD_KEY3_DATA0_REG, EFUSE_RD_KEY3_DATA7_REG}, // range address of EFUSE_BLK7 KEY3 + {EFUSE_RD_KEY4_DATA0_REG, EFUSE_RD_KEY4_DATA7_REG}, // range address of EFUSE_BLK8 KEY4 + {EFUSE_RD_KEY5_DATA0_REG, EFUSE_RD_KEY5_DATA7_REG}, // range address of EFUSE_BLK9 KEY5 + {EFUSE_RD_SYS_PART2_DATA0_REG, EFUSE_RD_SYS_PART2_DATA7_REG} // range address of EFUSE_BLK10 KEY6 +}; + +static uint32_t write_mass_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK] = { 0 }; + +/*Range addresses to write blocks (it is not real regs, it is buffer) */ +const esp_efuse_range_addr_t range_write_addr_blocks[] = { + {(uint32_t) &write_mass_blocks[EFUSE_BLK0][0], (uint32_t) &write_mass_blocks[EFUSE_BLK0][5]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK1][0], (uint32_t) &write_mass_blocks[EFUSE_BLK1][5]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK2][0], (uint32_t) &write_mass_blocks[EFUSE_BLK2][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK3][0], (uint32_t) &write_mass_blocks[EFUSE_BLK3][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK4][0], (uint32_t) &write_mass_blocks[EFUSE_BLK4][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK5][0], (uint32_t) &write_mass_blocks[EFUSE_BLK5][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK6][0], (uint32_t) &write_mass_blocks[EFUSE_BLK6][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK7][0], (uint32_t) &write_mass_blocks[EFUSE_BLK7][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK8][0], (uint32_t) &write_mass_blocks[EFUSE_BLK8][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK9][0], (uint32_t) &write_mass_blocks[EFUSE_BLK9][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]}, +}; + +#ifndef CONFIG_EFUSE_VIRTUAL +// Update Efuse timing configuration +static esp_err_t esp_efuse_set_timing(void) +{ + // efuse clock is fixed. + // An argument (0) is for compatibility and will be ignored. + efuse_hal_set_timing(0); + return ESP_OK; +} +#endif // ifndef CONFIG_EFUSE_VIRTUAL + +// Efuse read operation: copies data from physical efuses to efuse read registers. +void esp_efuse_utility_clear_program_registers(void) +{ + efuse_hal_read(); + efuse_hal_clear_program_registers(); +} + +esp_err_t esp_efuse_utility_check_errors(void) +{ + return ESP_OK; +} + +// Burn values written to the efuse write registers +esp_err_t esp_efuse_utility_burn_chip(void) +{ + esp_err_t error = ESP_OK; +#ifdef CONFIG_EFUSE_VIRTUAL + ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses"); + for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) { + int subblock = 0; + for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { + virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block); + } + } +#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH + esp_efuse_utility_write_efuses_to_flash(); +#endif +#else // CONFIG_EFUSE_VIRTUAL + if (esp_efuse_set_timing() != ESP_OK) { + ESP_LOGE(TAG, "Efuse fields are not burnt"); + } else { + // Permanently update values written to the efuse write registers + // It is necessary to process blocks in the order from MAX-> EFUSE_BLK0, because EFUSE_BLK0 has protection bits for other blocks. + for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) { + bool need_burn_block = false; + for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { + if (REG_READ(addr_wr_block) != 0) { + need_burn_block = true; + break; + } + } + if (!need_burn_block) { + continue; + } + if (error) { + // It is done for a use case: BLOCK2 (Flash encryption key) could have an error (incorrect written data) + // in this case we can not burn any data into BLOCK0 because it might set read/write protections of BLOCK2. + ESP_LOGE(TAG, "BLOCK%d can not be burned because a previous block got an error, skipped.", num_block); + continue; + } + efuse_hal_clear_program_registers(); + if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) { + uint8_t block_rs[12]; + efuse_hal_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs); +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstringop-overflow" +#pragma GCC diagnostic ignored "-Warray-bounds" + memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs)); +#pragma GCC diagnostic pop + } + unsigned r_data_len = (range_read_addr_blocks[num_block].end - range_read_addr_blocks[num_block].start) + sizeof(uint32_t); + unsigned data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t); + memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len); + + uint32_t backup_write_data[8 + 3]; // 8 words are data and 3 words are RS coding data +#pragma GCC diagnostic push +#if __GNUC__ >= 11 +#pragma GCC diagnostic ignored "-Wstringop-overread" +#endif +#pragma GCC diagnostic ignored "-Warray-bounds" + memcpy(backup_write_data, (void *)EFUSE_PGM_DATA0_REG, sizeof(backup_write_data)); +#pragma GCC diagnostic pop + int repeat_burn_op = 1; + bool correct_written_data; + bool coding_error_before = efuse_hal_is_coding_error_in_block(num_block); + if (coding_error_before) { + ESP_LOGW(TAG, "BLOCK%d already has a coding error", num_block); + } + bool coding_error_occurred; + + do { + ESP_LOGI(TAG, "BURN BLOCK%d", num_block); + efuse_hal_program(num_block); // BURN a block + + bool coding_error_after; + for (unsigned i = 0; i < 5; i++) { + efuse_hal_read(); + coding_error_after = efuse_hal_is_coding_error_in_block(num_block); + if (coding_error_after == true) { + break; + } + } + coding_error_occurred = (coding_error_before != coding_error_after) && coding_error_before == false; + if (coding_error_occurred) { + ESP_LOGW(TAG, "BLOCK%d got a coding error", num_block); + } + + correct_written_data = esp_efuse_utility_is_correct_written_data(num_block, r_data_len); + if (!correct_written_data || coding_error_occurred) { + ESP_LOGW(TAG, "BLOCK%d: next retry to fix an error [%d/3]...", num_block, repeat_burn_op); +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstringop-overflow" +#pragma GCC diagnostic ignored "-Warray-bounds" + memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)backup_write_data, sizeof(backup_write_data)); +#pragma GCC diagnostic pop + } + + } while ((!correct_written_data || coding_error_occurred) && repeat_burn_op++ < 3); + + if (coding_error_occurred) { + ESP_LOGW(TAG, "Coding error was not fixed"); + if (num_block == 0) { + ESP_LOGE(TAG, "BLOCK0 got a coding error, which might be critical for security"); + error = ESP_FAIL; + } + } + if (!correct_written_data) { + ESP_LOGE(TAG, "Written data are incorrect"); + error = ESP_FAIL; + } + } + } +#endif // CONFIG_EFUSE_VIRTUAL + esp_efuse_utility_reset(); + return error; +} + +// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values. +// This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme. +// The RS coding scheme does not require data changes for the encoded data. esp32s2 has special registers for this. +// They will be filled during the burn operation. +esp_err_t esp_efuse_utility_apply_new_coding_scheme() +{ + // start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE. + for (int num_block = EFUSE_BLK1; num_block < EFUSE_BLK_MAX; num_block++) { + if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) { + for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { + if (REG_READ(addr_wr_block)) { + int num_reg = 0; + for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) { + if (esp_efuse_utility_read_reg(num_block, num_reg)) { + ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden."); + return ESP_ERR_CODING; + } + } + break; + } + } + } + } + return ESP_OK; +} diff --git a/components/efuse/esp32c6/include/esp_efuse_chip.h b/components/efuse/esp32c6/include/esp_efuse_chip.h new file mode 100644 index 0000000000..85eb5d8362 --- /dev/null +++ b/components/efuse/esp32c6/include/esp_efuse_chip.h @@ -0,0 +1,79 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Type of eFuse blocks ESP32C6 + */ +typedef enum { + EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA */ + + EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */ + + EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ + EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ + + EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA*/ + EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA*/ + + EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */ + EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */ + + EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */ + EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */ + + EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */ + EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */ + + EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */ + EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */ + + EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */ + EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */ + + EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */ + EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */ + EFUSE_BLK_KEY_MAX = 10, + + EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ + EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ + + EFUSE_BLK_MAX +} esp_efuse_block_t; + +/** + * @brief Type of coding scheme + */ +typedef enum { + EFUSE_CODING_SCHEME_NONE = 0, /**< None */ + EFUSE_CODING_SCHEME_RS = 3, /**< Reed-Solomon coding */ +} esp_efuse_coding_scheme_t; + +/** + * @brief Type of key purpose + */ +typedef enum { + ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */ + ESP_EFUSE_KEY_PURPOSE_RESERVED = 1, /**< Reserved */ + ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, /**< XTS_AES_128_KEY (flash/PSRAM encryption) */ + ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, /**< HMAC Downstream mode */ + ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, /**< JTAG soft enable key (uses HMAC Downstream mode) */ + ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, /**< Digital Signature peripheral key (uses HMAC Downstream mode) */ + ESP_EFUSE_KEY_PURPOSE_HMAC_UP = 8, /**< HMAC Upstream mode */ + ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, /**< SECURE_BOOT_DIGEST0 (Secure Boot key digest) */ + ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */ + ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */ + ESP_EFUSE_KEY_PURPOSE_MAX, /**< MAX PURPOSE */ +} esp_efuse_purpose_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/esp32c6/include/esp_efuse_rtc_calib.h b/components/efuse/esp32c6/include/esp_efuse_rtc_calib.h new file mode 100644 index 0000000000..c8029ffc63 --- /dev/null +++ b/components/efuse/esp32c6/include/esp_efuse_rtc_calib.h @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +//This is the ADC calibration value version burnt in efuse +#define ESP_EFUSE_ADC_CALIB_VER 1 + +/** + * @brief Get the RTC calibration efuse version + * + * @return Version of the stored efuse + */ +int esp_efuse_rtc_calib_get_ver(void); + +/** + * @brief Get the init code in the efuse, for the corresponding attenuation. + * + * @param version Version of the stored efuse + * @param adc_unit ADC unit. Not used, for compatibility. On esp32c6, for calibration v1, both ADC units use the same init code (calibrated by ADC1) + * @param atten Attenuation of the init code + * @return The init code stored in efuse + */ +uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int atten); + +/** + * @brief Get the calibration digits stored in the efuse, and the corresponding voltage. + * + * @param version Version of the stored efuse + * @param atten Attenuation to use + * @param out_digi Output buffer of the digits + * @param out_vol_mv Output of the voltage, in mV + * @return + * - ESP_ERR_INVALID_ARG: If efuse version or attenuation is invalid + * - ESP_OK: if success + */ +esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t* out_digi, uint32_t* out_vol_mv); + +/** + * @brief Get the temperature sensor calibration number delta_T stored in the efuse. + * + * @param tsens_cal Pointer of the specification of temperature sensor calibration number in efuse. + * + * @return ESP_OK if get the calibration value successfully. + * ESP_ERR_INVALID_ARG if can't get the calibration value. + */ +esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal); + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/esp32c6/include/esp_efuse_table.h b/components/efuse/esp32c6/include/esp_efuse_table.h new file mode 100644 index 0000000000..f82e1c3d51 --- /dev/null +++ b/components/efuse/esp32c6/include/esp_efuse_table.h @@ -0,0 +1,144 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "esp_efuse.h" + +// md5_digest_table 5b3b6e026d28aacca6dc3b96be8bd280 +// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. +// If you want to change some fields, you need to change esp_efuse_table.csv file +// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. +// To show efuse_table run the command 'show_efuse_table'. + + +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SWAP_UART_SDIO_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SWAP_UART_SDIO_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[]; +extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_PRINT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[]; + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/esp32c6/private_include/esp_efuse_utility.h b/components/efuse/esp32c6/private_include/esp_efuse_utility.h new file mode 100644 index 0000000000..4720cb0a8f --- /dev/null +++ b/components/efuse/esp32c6/private_include/esp_efuse_utility.h @@ -0,0 +1,21 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define COUNT_EFUSE_REG_PER_BLOCK 8 /* The number of registers per block. */ + +#define ESP_EFUSE_SECURE_VERSION_NUM_BLOCK EFUSE_BLK0 + +#define ESP_EFUSE_FIELD_CORRESPONDS_CODING_SCHEME(scheme, max_num_bit) + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/esp32c6/sources.cmake b/components/efuse/esp32c6/sources.cmake new file mode 100644 index 0000000000..9dffd72008 --- /dev/null +++ b/components/efuse/esp32c6/sources.cmake @@ -0,0 +1,4 @@ +set(EFUSE_SOC_SRCS "esp_efuse_table.c" + "esp_efuse_fields.c" + "esp_efuse_rtc_calib.c" + "esp_efuse_utility.c") diff --git a/components/efuse/esp32s2/esp_efuse_rtc_table.c b/components/efuse/esp32s2/esp_efuse_rtc_table.c index 0254b17bf3..7df7f45436 100644 --- a/components/efuse/esp32s2/esp_efuse_rtc_table.c +++ b/components/efuse/esp32s2/esp_efuse_rtc_table.c @@ -97,6 +97,7 @@ int esp_efuse_rtc_table_read_calib_version(void) int esp_efuse_rtc_table_get_tag(int version, int adc_num, int atten, int extra_params) { + assert(adc_num <= ADC_UNIT_2); int index = (adc_num == ADC_UNIT_1) ? 0 : 1; int param_offset; // used to index which (adc_num, atten) array to use. if (version == 1 && extra_params == RTCCALIB_V1_PARAM_VLOW) { // Volage LOW, Version 1 diff --git a/components/efuse/esp32s3/esp_efuse_table.c b/components/efuse/esp32s3/esp_efuse_table.c index 0b71165ba9..b2a99a0b83 100644 --- a/components/efuse/esp32s3/esp_efuse_table.c +++ b/components/efuse/esp32s3/esp_efuse_table.c @@ -9,7 +9,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 8c7a031bb0def28f2123ac5ee2a48d43 +// md5_digest_table 87c5ae68b74dbafb114e14f6febff9e2 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -549,6 +549,26 @@ static const esp_efuse_desc_t SYS_DATA_PART2[] = { {EFUSE_BLK10, 0, 256}, // System configuration, }; +static const esp_efuse_desc_t K_RTC_LDO[] = { + {EFUSE_BLK1, 141, 7}, // BLOCK1 K_RTC_LDO, +}; + +static const esp_efuse_desc_t K_DIG_LDO[] = { + {EFUSE_BLK1, 148, 7}, // BLOCK1 K_DIG_LDO, +}; + +static const esp_efuse_desc_t V_RTC_DBIAS20[] = { + {EFUSE_BLK1, 155, 8}, // BLOCK1 voltage of rtc dbias20, +}; + +static const esp_efuse_desc_t V_DIG_DBIAS20[] = { + {EFUSE_BLK1, 163, 8}, // BLOCK1 voltage of digital dbias20, +}; + +static const esp_efuse_desc_t DIG_DBIAS_HVT[] = { + {EFUSE_BLK1, 171, 5}, // BLOCK1 digital dbias when hvt, +}; + @@ -1218,3 +1238,28 @@ const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = { &SYS_DATA_PART2[0], // System configuration NULL }; + +const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[] = { + &K_RTC_LDO[0], // BLOCK1 K_RTC_LDO + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[] = { + &K_DIG_LDO[0], // BLOCK1 K_DIG_LDO + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[] = { + &V_RTC_DBIAS20[0], // BLOCK1 voltage of rtc dbias20 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[] = { + &V_DIG_DBIAS20[0], // BLOCK1 voltage of digital dbias20 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[] = { + &DIG_DBIAS_HVT[0], // BLOCK1 digital dbias when hvt + NULL +}; diff --git a/components/efuse/esp32s3/esp_efuse_table.csv b/components/efuse/esp32s3/esp_efuse_table.csv index f7df89471d..8efee7c24b 100644 --- a/components/efuse/esp32s3/esp_efuse_table.csv +++ b/components/efuse/esp32s3/esp_efuse_table.csv @@ -183,3 +183,11 @@ KEY3, EFUSE_BLK7, 0, 256, Key3 or us KEY4, EFUSE_BLK8, 0, 256, Key4 or user data KEY5, EFUSE_BLK9, 0, 256, Key5 or user data SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration + +# AUTO CONFIG DIG&RTC DBIAS# +################ +K_RTC_LDO, EFUSE_BLK1, 141, 7, BLOCK1 K_RTC_LDO +K_DIG_LDO, EFUSE_BLK1, 148, 7, BLOCK1 K_DIG_LDO +V_RTC_DBIAS20, EFUSE_BLK1, 155, 8, BLOCK1 voltage of rtc dbias20 +V_DIG_DBIAS20, EFUSE_BLK1, 163, 8, BLOCK1 voltage of digital dbias20 +DIG_DBIAS_HVT, EFUSE_BLK1, 171, 5, BLOCK1 digital dbias when hvt diff --git a/components/efuse/esp32s3/include/esp_efuse_table.h b/components/efuse/esp32s3/include/esp_efuse_table.h index 2f347c4341..93be6aae49 100644 --- a/components/efuse/esp32s3/include/esp_efuse_table.h +++ b/components/efuse/esp32s3/include/esp_efuse_table.h @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table 8c7a031bb0def28f2123ac5ee2a48d43 +// md5_digest_table 87c5ae68b74dbafb114e14f6febff9e2 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -149,6 +149,11 @@ extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[]; extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[]; #ifdef __cplusplus } diff --git a/components/efuse/src/esp_efuse_fields.c b/components/efuse/src/esp_efuse_fields.c index 9898563a75..b443ff91b1 100644 --- a/components/efuse/src/esp_efuse_fields.c +++ b/components/efuse/src/esp_efuse_fields.c @@ -16,7 +16,6 @@ #include "esp_log.h" #include "soc/efuse_periph.h" #include "bootloader_random.h" -#include "soc/syscon_reg.h" #include "sys/param.h" static __attribute__((unused)) const char *TAG = "efuse"; diff --git a/components/esp-tls/esp_tls_mbedtls.c b/components/esp-tls/esp_tls_mbedtls.c index 1806757594..ad2386d7d8 100644 --- a/components/esp-tls/esp_tls_mbedtls.c +++ b/components/esp-tls/esp_tls_mbedtls.c @@ -113,11 +113,8 @@ esp_err_t esp_create_mbedtls_handle(const char *hostname, size_t hostlen, const #endif #ifdef CONFIG_MBEDTLS_SSL_PROTO_TLS1_3 - // NOTE: Mbed TLS currently supports only client-side config with TLS 1.3 - if (tls->role != ESP_TLS_SERVER) { - mbedtls_ssl_conf_min_version(&tls->conf, MBEDTLS_SSL_MAJOR_VERSION_3, MBEDTLS_SSL_MINOR_VERSION_4); - mbedtls_ssl_conf_max_version(&tls->conf, MBEDTLS_SSL_MAJOR_VERSION_3, MBEDTLS_SSL_MINOR_VERSION_4); - } + mbedtls_ssl_conf_min_tls_version(&tls->conf, MBEDTLS_SSL_VERSION_TLS1_3); + mbedtls_ssl_conf_max_tls_version(&tls->conf, MBEDTLS_SSL_VERSION_TLS1_3); #endif if ((ret = mbedtls_ssl_setup(&tls->ssl, &tls->conf)) != 0) { @@ -273,8 +270,11 @@ void esp_mbedtls_conn_delete(esp_tls_t *tls) if (tls != NULL) { esp_mbedtls_cleanup(tls); if (tls->is_tls) { - mbedtls_net_free(&tls->server_fd); - tls->sockfd = tls->server_fd.fd; + if (tls->server_fd.fd != -1) { + mbedtls_net_free(&tls->server_fd); + /* Socket is already closed by `mbedtls_net_free` and hence also change assignment of its copy to an invalid value */ + tls->sockfd = -1; + } } } } diff --git a/components/esp-tls/test/CMakeLists.txt b/components/esp-tls/test/CMakeLists.txt deleted file mode 100644 index 049495b636..0000000000 --- a/components/esp-tls/test/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -idf_component_register(SRC_DIRS "." - PRIV_REQUIRES test_utils esp-tls) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/components/esp-tls/test_apps/CMakeLists.txt b/components/esp-tls/test_apps/CMakeLists.txt new file mode 100644 index 0000000000..086455137b --- /dev/null +++ b/components/esp-tls/test_apps/CMakeLists.txt @@ -0,0 +1,7 @@ +#This is the project CMakeLists.txt file for the test subproject +cmake_minimum_required(VERSION 3.16) + +set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components") + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(esp-tls_test) diff --git a/components/esp-tls/test_apps/README.md b/components/esp-tls/test_apps/README.md new file mode 100644 index 0000000000..b5be4985c5 --- /dev/null +++ b/components/esp-tls/test_apps/README.md @@ -0,0 +1,2 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | diff --git a/components/esp-tls/test_apps/main/CMakeLists.txt b/components/esp-tls/test_apps/main/CMakeLists.txt new file mode 100644 index 0000000000..d57cfd5249 --- /dev/null +++ b/components/esp-tls/test_apps/main/CMakeLists.txt @@ -0,0 +1,3 @@ +idf_component_register(SRC_DIRS "." + PRIV_REQUIRES test_utils esp-tls unity + WHOLE_ARCHIVE) diff --git a/components/esp-tls/test_apps/main/app_main.c b/components/esp-tls/test_apps/main/app_main.c new file mode 100644 index 0000000000..050d90b205 --- /dev/null +++ b/components/esp-tls/test_apps/main/app_main.c @@ -0,0 +1,60 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "unity.h" +#include "memory_checks.h" +#include "soc/soc_caps.h" +#if SOC_SHA_SUPPORT_PARALLEL_ENG +#include "sha/sha_parallel_engine.h" +#elif SOC_SHA_SUPPORT_DMA +#include "sha/sha_dma.h" +#else +#include "sha/sha_block.h" +#endif + +#if SOC_SHA_SUPPORT_SHA512 +#define SHA_TYPE SHA2_512 +#else +#define SHA_TYPE SHA2_256 +#endif //SOC_SHA_SUPPORT_SHA512 + +/* setUp runs before every test */ +void setUp(void) +{ + // Execute esp_sha operation to allocate internal SHA semaphore memory + // which is considered as leaked otherwise + const uint8_t input_buffer[64] = {0}; + uint8_t output_buffer[64]; + esp_sha(SHA_TYPE, input_buffer, sizeof(input_buffer), output_buffer); + test_utils_record_free_mem(); + TEST_ESP_OK(test_utils_set_leak_level(0, ESP_LEAK_TYPE_CRITICAL, ESP_COMP_LEAK_GENERAL)); + TEST_ESP_OK(test_utils_set_leak_level(0, ESP_LEAK_TYPE_WARNING, ESP_COMP_LEAK_GENERAL)); + +} + +/* tearDown runs after every test */ +void tearDown(void) +{ + /* some FreeRTOS stuff is cleaned up by idle task */ + vTaskDelay(5); + + /* clean up some of the newlib's lazy allocations */ + esp_reent_cleanup(); + + /* check if unit test has caused heap corruption in any heap */ + TEST_ASSERT_MESSAGE( heap_caps_check_integrity(MALLOC_CAP_INVALID, true), "The test has corrupted the heap"); + + test_utils_finish_and_evaluate_leaks(test_utils_get_leak_level(ESP_LEAK_TYPE_WARNING, ESP_COMP_LEAK_ALL), + test_utils_get_leak_level(ESP_LEAK_TYPE_CRITICAL, ESP_COMP_LEAK_ALL)); + +} + +void app_main(void) +{ + unity_run_menu(); +} diff --git a/components/esp-tls/test/test_esp_tls.c b/components/esp-tls/test_apps/main/test_esp_tls.c similarity index 82% rename from components/esp-tls/test/test_esp_tls.c rename to components/esp-tls/test_apps/main/test_esp_tls.c index a2cf344463..e245fc7e8b 100644 --- a/components/esp-tls/test/test_esp_tls.c +++ b/components/esp-tls/test_apps/main/test_esp_tls.c @@ -11,14 +11,6 @@ #include "esp_log.h" #include "esp_mac.h" #include "sys/socket.h" -#if SOC_SHA_SUPPORT_PARALLEL_ENG -#include "sha/sha_parallel_engine.h" -#elif SOC_SHA_SUPPORT_DMA -#include "sha/sha_dma.h" -#else -#include "sha/sha_block.h" -#endif -#include "test_utils.h" const char *test_cert_pem = "-----BEGIN CERTIFICATE-----\n"\ "MIICrDCCAZQCCQD88gCs5AFs/jANBgkqhkiG9w0BAQsFADAYMRYwFAYDVQQDDA1F\n"\ @@ -67,40 +59,16 @@ const char *test_key_pem = "-----BEGIN PRIVATE KEY-----\n"\ "Aogx44Fozd1t2hYcozPuZD4s\n"\ "-----END PRIVATE KEY-----\n"; -#if SOC_SHA_SUPPORT_SHA512 -#define SHA_TYPE SHA2_512 -#else -#define SHA_TYPE SHA2_256 -#endif //SOC_SHA_SUPPORT_SHA512 - -static void test_leak_setup(const char *file, long line) +TEST_CASE("esp-tls init deinit", "[esp-tls]") { - uint8_t mac[6]; - struct timeval te; - gettimeofday(&te, NULL); // get current time - esp_read_mac(mac, ESP_MAC_WIFI_STA); - printf("%s:%ld: time=%jd.%lds, mac:" MACSTR "\n", file, line, (intmax_t)te.tv_sec, te.tv_usec, MAC2STR(mac)); - // Execute esp_sha operation to allocate internal SHA semaphore memory - // which is considered as leaked otherwise - const uint8_t input_buffer[64]; - uint8_t output_buffer[64]; - esp_sha(SHA_TYPE, input_buffer, sizeof(input_buffer), output_buffer); - test_utils_record_free_mem(); -} - - -TEST_CASE("esp-tls init deinit", "[esp-tls][leaks=0]") -{ - test_leak_setup(__FILE__, __LINE__); struct esp_tls *tls = esp_tls_init(); TEST_ASSERT_NOT_NULL(tls); int ret = esp_tls_conn_destroy(tls); TEST_ASSERT_EQUAL(0, ret); } -TEST_CASE("esp-tls global_ca_store set free", "[esp-tls][leaks=0]") +TEST_CASE("esp-tls global_ca_store set free", "[esp-tls]") { - test_leak_setup(__FILE__, __LINE__); esp_err_t ret = esp_tls_init_global_ca_store(); TEST_ASSERT_EQUAL(ESP_OK, ret); ret = esp_tls_set_global_ca_store((const unsigned char *)test_cert_pem, strlen(test_cert_pem) + 1); @@ -109,9 +77,8 @@ TEST_CASE("esp-tls global_ca_store set free", "[esp-tls][leaks=0]") } #ifdef CONFIG_ESP_TLS_SERVER -TEST_CASE("esp_tls_server session create delete", "[esp-tls][leaks=0]") +TEST_CASE("esp_tls_server session create delete", "[esp-tls]") { - test_leak_setup(__FILE__, __LINE__); struct esp_tls *tls = esp_tls_init(); TEST_ASSERT_NOT_NULL(tls); esp_tls_cfg_server_t cfg = { @@ -126,5 +93,6 @@ TEST_CASE("esp_tls_server session create delete", "[esp-tls][leaks=0]") TEST_ASSERT_LESS_THAN_INT(0, ret); // free the allocated memory. esp_tls_server_session_delete(tls); + } #endif diff --git a/components/esp-tls/test_apps/pytest_esp-tls.py b/components/esp-tls/test_apps/pytest_esp-tls.py new file mode 100644 index 0000000000..d1ea54c669 --- /dev/null +++ b/components/esp-tls/test_apps/pytest_esp-tls.py @@ -0,0 +1,12 @@ +# SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +import pytest +from pytest_embedded import Dut + + +@pytest.mark.supported_targets +@pytest.mark.generic +def test_esp_tls(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('*') + dut.expect_unity_test_output() diff --git a/components/esp-tls/test_apps/sdkconfig.defaults b/components/esp-tls/test_apps/sdkconfig.defaults new file mode 100644 index 0000000000..c1398bba5f --- /dev/null +++ b/components/esp-tls/test_apps/sdkconfig.defaults @@ -0,0 +1,10 @@ +# General options for additional checks +CONFIG_HEAP_POISONING_COMPREHENSIVE=y +CONFIG_COMPILER_WARN_WRITE_STRINGS=y +CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y +CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y +CONFIG_COMPILER_STACK_CHECK_MODE_STRONG=y +CONFIG_COMPILER_STACK_CHECK=y + +CONFIG_ESP_TASK_WDT=n +CONFIG_ESP_TLS_SERVER=y diff --git a/components/esp_adc/CMakeLists.txt b/components/esp_adc/CMakeLists.txt index 48939d92ac..b52dffa1d0 100644 --- a/components/esp_adc/CMakeLists.txt +++ b/components/esp_adc/CMakeLists.txt @@ -27,8 +27,16 @@ if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/deprecated/${target}/esp_adc_cal_legacy.c list(APPEND srcs "deprecated/${target}/esp_adc_cal_legacy.c") endif() +# ESP32C6-TODO +if(CONFIG_IDF_TARGET_ESP32C6) + list(REMOVE_ITEM srcs + "adc_cali_curve_fitting.c" # TODO: IDF-5312 + "adc_oneshot.c" # TODO: IDF-5310 + "adc_common.c" + ) +endif() + idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${includes} PRIV_REQUIRES driver efuse LDFRAGMENTS linker.lf) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/components/esp_adc/Kconfig b/components/esp_adc/Kconfig index 87a8fbe567..4d8e4205e8 100644 --- a/components/esp_adc/Kconfig +++ b/components/esp_adc/Kconfig @@ -41,7 +41,19 @@ menu "ADC and ADC Calibration" This option will allow the ADC calibration component to use Lookup Tables to correct for non-linear behavior in 11db attenuation. Other attenuations do not exhibit non-linear behavior hence will not be affected by this option. - endmenu + config ADC_DISABLE_DAC_OUTPUT + depends on SOC_DAC_SUPPORTED + bool "Disable DAC when ADC2 is in use" + default y + help + By default, this is set. The ADC oneshot driver will disable the output of the + corresponding DAC channels: + ESP32: IO25 and IO26 + ESP32S2: IO17 and IO18 + + Disable this option so as to measure the output of DAC by internal ADC, for test usage. + + endmenu diff --git a/components/esp_adc/adc_cali_curve_fitting.c b/components/esp_adc/adc_cali_curve_fitting.c index 9b80e47b2c..1d575c1464 100644 --- a/components/esp_adc/adc_cali_curve_fitting.c +++ b/components/esp_adc/adc_cali_curve_fitting.c @@ -174,7 +174,7 @@ static void calc_first_step_coefficients(const adc_calib_info_t *parsed_data, ca { ctx->chars_first_step.coeff_a = coeff_a_scaling * parsed_data->ref_data.ver1.voltage / parsed_data->ref_data.ver1.digi; ctx->chars_first_step.coeff_b = 0; - ESP_LOGV(TAG, "Calib V1, Cal Voltage = %d, Digi out = %d, Coef_a = %d\n", parsed_data->ref_data.ver1.voltage, parsed_data->ref_data.ver1.digi, ctx->chars_first_step.coeff_a); + ESP_LOGV(TAG, "Calib V1, Cal Voltage = %"PRId32", Digi out = %"PRId32", Coef_a = %"PRId32"\n", parsed_data->ref_data.ver1.voltage, parsed_data->ref_data.ver1.digi, ctx->chars_first_step.coeff_a); } static void calc_second_step_coefficients(const adc_cali_curve_fitting_config_t *config, cali_chars_curve_fitting_t *ctx) @@ -224,7 +224,7 @@ static int32_t get_reading_error(uint64_t v_cali_1, const cali_chars_second_step term[i] = term[i] / (*param->coeff)[atten][i][1]; error += (int32_t)term[i] * (*param->sign)[atten][i]; - ESP_LOGV(TAG, "term%d is %llu, error is %d", i, term[i], error); + ESP_LOGV(TAG, "term%d is %llu, error is %"PRId32, i, term[i], error); } return error; diff --git a/components/esp_adc/adc_oneshot.c b/components/esp_adc/adc_oneshot.c index 681166bf07..f88e5a1bf7 100644 --- a/components/esp_adc/adc_oneshot.c +++ b/components/esp_adc/adc_oneshot.c @@ -107,7 +107,7 @@ esp_err_t adc_oneshot_new_unit(const adc_oneshot_unit_init_cfg_t *init_config, a adc_power_acquire(); - ESP_LOGD(TAG, "new adc unit%d is created", unit->unit_id); + ESP_LOGD(TAG, "new adc unit%"PRId32" is created", unit->unit_id); *ret_unit = unit; return ESP_OK; @@ -193,13 +193,13 @@ esp_err_t adc_oneshot_del_unit(adc_oneshot_unit_handle_t handle) { ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); bool success_free = s_adc_unit_free(handle->unit_id); - ESP_RETURN_ON_FALSE(success_free, ESP_ERR_NOT_FOUND, TAG, "adc%d isn't in use", handle->unit_id + 1); + ESP_RETURN_ON_FALSE(success_free, ESP_ERR_NOT_FOUND, TAG, "adc%"PRId32" isn't in use", handle->unit_id + 1); _lock_acquire(&s_ctx.mutex); s_ctx.units[handle->unit_id] = NULL; _lock_release(&s_ctx.mutex); - ESP_LOGD(TAG, "adc unit%d is deleted", handle->unit_id); + ESP_LOGD(TAG, "adc unit%"PRId32" is deleted", handle->unit_id); free(handle); adc_power_release(); diff --git a/components/esp_adc/deprecated/esp32c3/esp_adc_cal_legacy.c b/components/esp_adc/deprecated/esp32c3/esp_adc_cal_legacy.c index b6374113a6..e35e00dfbc 100644 --- a/components/esp_adc/deprecated/esp32c3/esp_adc_cal_legacy.c +++ b/components/esp_adc/deprecated/esp32c3/esp_adc_cal_legacy.c @@ -101,7 +101,7 @@ static esp_err_t prepare_calib_data_for(int version_num, adc_unit_t adc_num, adc */ static void calculate_characterization_coefficients(const adc_calib_parsed_info_t *parsed_data, esp_adc_cal_characteristics_t *chars) { - ESP_LOGD(LOG_TAG, "Calib V1, Cal Voltage = %d, Digi out = %d\n", parsed_data->efuse_data.ver1.voltage, parsed_data->efuse_data.ver1.digi); + ESP_LOGD(LOG_TAG, "Calib V1, Cal Voltage = %"PRId32", Digi out = %"PRId32, parsed_data->efuse_data.ver1.voltage, parsed_data->efuse_data.ver1.digi); chars->coeff_a = coeff_a_scaling * parsed_data->efuse_data.ver1.voltage / parsed_data->efuse_data.ver1.digi; chars->coeff_b = 0; @@ -147,7 +147,7 @@ esp_adc_cal_value_t esp_adc_cal_characterize(adc_unit_t adc_num, } calculate_characterization_coefficients(&efuse_parsed_data, chars); - ESP_LOGD(LOG_TAG, "adc%d (atten leven %d) calibration done: A:%d B:%d\n", adc_num, atten, chars->coeff_a, chars->coeff_b); + ESP_LOGD(LOG_TAG, "adc%d (atten leven %d) calibration done: A:%"PRId32" B:%"PRId32, adc_num, atten, chars->coeff_a, chars->coeff_b); // Initialize remaining fields chars->adc_num = adc_num; diff --git a/components/esp_adc/deprecated/esp32s2/esp_adc_cal_legacy.c b/components/esp_adc/deprecated/esp32s2/esp_adc_cal_legacy.c index eeeb61c7f6..dd007d10a6 100644 --- a/components/esp_adc/deprecated/esp32s2/esp_adc_cal_legacy.c +++ b/components/esp_adc/deprecated/esp32s2/esp_adc_cal_legacy.c @@ -178,7 +178,7 @@ esp_adc_cal_value_t esp_adc_cal_characterize(adc_unit_t adc_num, assert(res); res = calculate_characterization_coefficients(&efuse_parsed_data, chars); assert(res); - ESP_LOGD(LOG_TAG, "adc%d (atten leven %d) calibration done: A:%d B:%d\n", adc_num, atten, chars->coeff_a, chars->coeff_b); + ESP_LOGD(LOG_TAG, "adc%d (atten leven %d) calibration done: A:%"PRId32" B:%"PRId32"\n", adc_num, atten, chars->coeff_a, chars->coeff_b); // Initialize remaining fields chars->adc_num = adc_num; diff --git a/components/esp_adc/deprecated/esp32s3/esp_adc_cal_legacy.c b/components/esp_adc/deprecated/esp32s3/esp_adc_cal_legacy.c index b9e11e6c23..1f98689ec3 100644 --- a/components/esp_adc/deprecated/esp32s3/esp_adc_cal_legacy.c +++ b/components/esp_adc/deprecated/esp32s3/esp_adc_cal_legacy.c @@ -121,7 +121,7 @@ static void calculate_characterization_coefficients(const adc_calib_info_t *pars { chars->coeff_a = coeff_a_scaling * parsed_data->ref_data.ver1.voltage / parsed_data->ref_data.ver1.digi; chars->coeff_b = 0; - ESP_LOGV(LOG_TAG, "Calib V1, Cal Voltage = %d, Digi out = %d, Coef_a = %d\n", parsed_data->ref_data.ver1.voltage, parsed_data->ref_data.ver1.digi, chars->coeff_a); + ESP_LOGV(LOG_TAG, "Calib V1, Cal Voltage = %"PRId32", Digi out = %"PRId32", Coef_a = %"PRId32"\n", parsed_data->ref_data.ver1.voltage, parsed_data->ref_data.ver1.digi, chars->coeff_a); } esp_adc_cal_value_t esp_adc_cal_characterize(adc_unit_t adc_num, diff --git a/components/esp_adc/deprecated/esp_adc_cal_common_legacy.c b/components/esp_adc/deprecated/esp_adc_cal_common_legacy.c index 83b889275e..a990466394 100644 --- a/components/esp_adc/deprecated/esp_adc_cal_common_legacy.c +++ b/components/esp_adc/deprecated/esp_adc_cal_common_legacy.c @@ -6,6 +6,7 @@ #include #include +#include "inttypes.h" #include "sdkconfig.h" #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 @@ -85,7 +86,7 @@ int32_t esp_adc_cal_get_reading_error(const esp_adc_error_calc_param_t *param, u term[i] = term[i] / (*param->coeff)[atten][i][1]; error += (int32_t)term[i] * (*param->sign)[atten][i]; - ESP_LOGV(TAG, "term%d is %llu, error is %d", i, term[i], error); + ESP_LOGV(TAG, "term%d is %llu, error is %"PRId32, i, term[i], error); } return error; diff --git a/components/esp_adc/esp32c6/include/adc_cali_schemes.h b/components/esp_adc/esp32c6/include/adc_cali_schemes.h new file mode 100644 index 0000000000..cfdd5ad0d5 --- /dev/null +++ b/components/esp_adc/esp32c6/include/adc_cali_schemes.h @@ -0,0 +1,15 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file adc_cali_schemes.h + * + * @brief Supported calibration schemes + */ + +//Now no scheme supported diff --git a/components/esp_adc/esp32s2/adc_cali_line_fitting.c b/components/esp_adc/esp32s2/adc_cali_line_fitting.c index 93f509020a..9826b73860 100644 --- a/components/esp_adc/esp32s2/adc_cali_line_fitting.c +++ b/components/esp_adc/esp32s2/adc_cali_line_fitting.c @@ -114,7 +114,7 @@ esp_err_t adc_cali_create_scheme_line_fitting(const adc_cali_line_fitting_config assert(success); success = calculate_characterization_coefficients(&efuse_parsed_data, chars); assert(success); - ESP_LOGD(TAG, "adc%d (atten leven %d) calibration done: A:%d B:%d\n", config->unit_id, config->atten, chars->coeff_a, chars->coeff_b); + ESP_LOGD(TAG, "adc%d (atten leven %d) calibration done: A:%"PRId32" B:%"PRId32"\n", config->unit_id, config->atten, chars->coeff_a, chars->coeff_b); chars->unit_id = config->unit_id; chars->atten = config->atten; diff --git a/components/esp_adc/test_apps/adc/main/CMakeLists.txt b/components/esp_adc/test_apps/adc/main/CMakeLists.txt index e599f6328a..b545b3fc48 100644 --- a/components/esp_adc/test_apps/adc/main/CMakeLists.txt +++ b/components/esp_adc/test_apps/adc/main/CMakeLists.txt @@ -3,10 +3,10 @@ set(srcs "test_app_main.c" "test_adc_performance.c" "test_adc_driver.c" "test_adc_driver_iram.c" + "test_adc2_wifi.c" "test_common_adc.c") # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} WHOLE_ARCHIVE) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/components/esp_adc/test_apps/adc/main/test_adc.c b/components/esp_adc/test_apps/adc/main/test_adc.c index b8896853e1..04a4e610df 100644 --- a/components/esp_adc/test_apps/adc/main/test_adc.c +++ b/components/esp_adc/test_apps/adc/main/test_adc.c @@ -6,7 +6,6 @@ #include #include #include -#include "unity.h" #include "esp_log.h" #include "soc/adc_periph.h" #include "esp_adc/adc_oneshot.h" @@ -44,7 +43,7 @@ TEST_CASE("ADC oneshot high/low test", "[adc_oneshot]") adc_oneshot_unit_handle_t adc1_handle; adc_oneshot_unit_init_cfg_t init_config1 = { .unit_id = ADC_UNIT_1, - .ulp_mode = false, + .ulp_mode = ADC_ULP_MODE_DISABLE, }; TEST_ESP_OK(adc_oneshot_new_unit(&init_config1, &adc1_handle)); @@ -53,7 +52,7 @@ TEST_CASE("ADC oneshot high/low test", "[adc_oneshot]") adc_oneshot_unit_handle_t adc2_handle; adc_oneshot_unit_init_cfg_t init_config2 = { .unit_id = ADC_UNIT_2, - .ulp_mode = false, + .ulp_mode = ADC_ULP_MODE_DISABLE, }; TEST_ESP_OK(adc_oneshot_new_unit(&init_config2, &adc2_handle)); #endif //#if (SOC_ADC_PERIPH_NUM >= 2) @@ -135,7 +134,7 @@ static void s_adc_oneshot_with_sleep(adc_unit_t unit_id, adc_channel_t channel) adc_oneshot_unit_handle_t adc_handle; adc_oneshot_unit_init_cfg_t init_config = { .unit_id = unit_id, - .ulp_mode = false, + .ulp_mode = ADC_ULP_MODE_DISABLE, }; TEST_ESP_OK(adc_oneshot_new_unit(&init_config, &adc_handle)); @@ -217,11 +216,11 @@ static void s_adc_oneshot_with_sleep(adc_unit_t unit_id, adc_channel_t channel) //Compare int32_t raw_diff = raw_expected - raw_after_sleep; - ESP_LOGI(TAG, "ADC%d Chan%d: raw difference: %d", unit_id + 1, channel, raw_diff); + ESP_LOGI(TAG, "ADC%d Chan%d: raw difference: %"PRId32, unit_id + 1, channel, raw_diff); if (do_calibration) { int32_t cali_diff = cali_expected - cali_after_sleep; - ESP_LOGI(TAG, "ADC%d Chan%d: cali difference: %d", unit_id + 1, channel, cali_diff); + ESP_LOGI(TAG, "ADC%d Chan%d: cali difference: %"PRId32, unit_id + 1, channel, cali_diff); } //Test Calibration registers diff --git a/components/esp_adc/test_apps/adc/main/test_adc2_wifi.c b/components/esp_adc/test_apps/adc/main/test_adc2_wifi.c new file mode 100644 index 0000000000..ae1fa35f82 --- /dev/null +++ b/components/esp_adc/test_apps/adc/main/test_adc2_wifi.c @@ -0,0 +1,210 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include "esp_log.h" +#include "soc/adc_periph.h" +#include "esp_adc/adc_oneshot.h" +#include "driver/gpio.h" +#include "driver/rtc_io.h" +#include "nvs_flash.h" +#include "esp_event.h" +#include "esp_wifi.h" +#include "test_common_adc.h" +#include "test_utils.h" + +#if (SOC_ADC_PERIPH_NUM > 1) + +static const char* TAG = "test_adc2"; + +#define DEFAULT_SSID "TEST_SSID" +#define DEFAULT_PWD "TEST_PASS" + +#if CONFIG_IDF_TARGET_ESP32 +#define TEST_ADC2_CHAN0 ADC_CHANNEL_9 +#elif CONFIG_IDF_TARGET_ESP32S2 +#define TEST_ADC2_CHAN0 ADC_CHANNEL_0 +#elif CONFIG_IDF_TARGET_ESP32C3 +#define TEST_ADC2_CHAN0 ADC_CHANNEL_0 +#elif CONFIG_IDF_TARGET_ESP32S3 +#define TEST_ADC2_CHAN0 ADC_CHANNEL_0 +#endif + +#define ADC_ERROR_THRES 100 +#define TEST_NUM 8 + +#define MINUS_UNTIL_ZERO(a, b) ( ((a) > (b)) ? ((a)-(b)): 0) +#define TIME_REMAIN(start, now, timeout) ((now) >= (start) ? MINUS_UNTIL_ZERO((timeout), (now)-(start)) : -1) + + +static void wifi_event_handler(void* arg, esp_event_base_t event_base, + int32_t event_id, void* event_data) +{ + printf("ev_handle_called.\n"); + switch(event_id) { + case WIFI_EVENT_STA_START: + ESP_LOGI(TAG, "WIFI_EVENT_STA_START"); + //do not actually connect in test case + //; + break; + case WIFI_EVENT_STA_DISCONNECTED: + ESP_LOGI(TAG, "WIFI_EVENT_STA_DISCONNECTED"); + TEST_ESP_OK(esp_wifi_connect()); + break; + default: + break; + } + return ; +} + +static void ip_event_handler(void* arg, esp_event_base_t event_base, + int32_t event_id, void* event_data) +{ + ip_event_got_ip_t *event; + printf("ev_handle_called.\n"); + switch(event_id) { + case IP_EVENT_STA_GOT_IP: + event = (ip_event_got_ip_t*)event_data; + ESP_LOGI(TAG, "IP_EVENT_STA_GOT_IP"); + ESP_LOGI(TAG, "got ip:" IPSTR "\n", IP2STR(&event->ip_info.ip)); + break; + default: + break; + } + + return ; +} + +static int event_init(void) +{ + TEST_ESP_OK(esp_event_loop_create_default()); + ESP_ERROR_CHECK(esp_event_handler_register(WIFI_EVENT, ESP_EVENT_ANY_ID, &wifi_event_handler, NULL)); + ESP_ERROR_CHECK(esp_event_handler_register(IP_EVENT, ESP_EVENT_ANY_ID, &ip_event_handler, NULL)); + return ESP_OK; +} + +static int event_deinit(void) +{ + ESP_ERROR_CHECK(esp_event_handler_unregister(WIFI_EVENT, ESP_EVENT_ANY_ID, &wifi_event_handler)); + ESP_ERROR_CHECK(esp_event_handler_unregister(IP_EVENT, ESP_EVENT_ANY_ID, &ip_event_handler)); + return ESP_OK; +} + +TEST_CASE("adc2 work with wifi","[adc]") +{ + test_case_uses_tcpip(); + + //---------------------------------WiFi init-----------------------------------// + printf("nvs init\n"); + esp_err_t r = nvs_flash_init(); + if (r == ESP_ERR_NVS_NO_FREE_PAGES || r == ESP_ERR_NVS_NEW_VERSION_FOUND) { + printf("no free pages or nvs version mismatch, erase..\n"); + TEST_ESP_OK(nvs_flash_erase()); + r = nvs_flash_init(); + } + TEST_ESP_OK( r); + esp_netif_init(); + event_init(); + esp_netif_create_default_wifi_sta(); + + wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT(); + + /* Restrict the number of buffers to allocate to account for limited memory when running large number of tests */ + cfg.static_rx_buf_num = 2; + cfg.static_tx_buf_num = 2; + + TEST_ESP_OK(esp_wifi_init(&cfg)); + wifi_config_t wifi_config = { + .sta = { + .ssid = DEFAULT_SSID, + .password = DEFAULT_PWD + }, + }; + TEST_ESP_OK(esp_wifi_set_mode(WIFI_MODE_STA)); + TEST_ESP_OK(esp_wifi_set_config(WIFI_IF_STA, &wifi_config)); + + //---------------------------------ADC init-----------------------------------// + int read_raw; + int target_value; + int test_adc_io; + bool test_list[TEST_NUM] = {1, 1, 0, 0, 1, 0, 1, 0}; + + TEST_ESP_OK(adc_oneshot_channel_to_io(ADC_UNIT_2, TEST_ADC2_CHAN0, &test_adc_io)); + printf("test_adc_io is %d\n", test_adc_io); + + //-------------ADC2 Init---------------// + adc_oneshot_unit_handle_t adc2_handle; + adc_oneshot_unit_init_cfg_t init_config2 = { + .unit_id = ADC_UNIT_2, + .ulp_mode = ADC_ULP_MODE_DISABLE, + }; + TEST_ESP_OK(adc_oneshot_new_unit(&init_config2, &adc2_handle)); + + //-------------ADC2 TEST Channel 0 Config---------------// + adc_oneshot_chan_cfg_t config = { + .bitwidth = ADC_BITWIDTH_DEFAULT, + .atten = ADC_ATTEN_DB_11, + }; + TEST_ESP_OK(adc_oneshot_config_channel(adc2_handle, TEST_ADC2_CHAN0, &config)); + + for (int i = 0; i < TEST_NUM; i++) { + /* Tune test ADC channel level */ + test_adc_set_io_level(ADC_UNIT_2, TEST_ADC2_CHAN0, test_list[i]); + target_value = test_list[i] ? ADC_TEST_HIGH_VAL : ADC_TEST_LOW_VAL; + + + /* ADC2 single read before WIFI start */ + TEST_ESP_OK(adc_oneshot_read(adc2_handle, TEST_ADC2_CHAN0, &read_raw)); + printf("Before WiFi starts, ADC read: %d (target_value: %d)\n", read_raw, target_value); + TEST_ASSERT_INT_WITHIN(ADC_ERROR_THRES, target_value, read_raw); + + + /* ADC2 single read when WIFI is on */ + TEST_ESP_OK(esp_wifi_start()); +#if CONFIG_IDF_TARGET_ESP32 + TEST_ASSERT_EQUAL(ESP_ERR_TIMEOUT, adc_oneshot_read(adc2_handle, TEST_ADC2_CHAN0, &read_raw)); +#else + esp_err_t ret = ESP_FAIL; + int32_t start = xTaskGetTickCount(); + int32_t now; + int32_t remain_wait_ms = 0; + int32_t timeout = pdMS_TO_TICKS(10); + + do { + now = xTaskGetTickCount(); + remain_wait_ms = pdTICKS_TO_MS(TIME_REMAIN(start, now, timeout)); + ret = adc_oneshot_read(adc2_handle, TEST_ADC2_CHAN0, &read_raw); + if (ret == ESP_OK) { + printf("When WiFi is ON, ADC read: %d (target_value: %d)\n", read_raw, target_value); + TEST_ASSERT_INT_WITHIN(ADC_ERROR_THRES, target_value, read_raw); + break; + } else if (ret == ESP_ERR_TIMEOUT) { + continue; + } else { + TEST_ESP_OK(ret); + } + } while (remain_wait_ms); +#endif + + + /* ADC2 single read after WIFI is off */ + TEST_ESP_OK(esp_wifi_stop()); + TEST_ESP_OK(adc_oneshot_read(adc2_handle, TEST_ADC2_CHAN0, &read_raw)); + printf("After WiFi is OFF, ADC read: %d (target_value: %d)\n\n", read_raw, target_value); + TEST_ASSERT_INT_WITHIN(ADC_ERROR_THRES, target_value, read_raw); + } + + TEST_ESP_OK(esp_wifi_deinit()); + event_deinit(); + nvs_flash_deinit(); + TEST_ESP_OK(adc_oneshot_del_unit(adc2_handle)); + + TEST_IGNORE_MESSAGE("this test case is ignored due to the critical memory leak of esp_netif and event_loop."); +} + +#endif //#if (SOC_ADC_PERIPH_NUM > 1) diff --git a/components/esp_adc/test_apps/adc/main/test_adc_driver.c b/components/esp_adc/test_apps/adc/main/test_adc_driver.c index c5e2c4dfb4..a1e8a3e56c 100644 --- a/components/esp_adc/test_apps/adc/main/test_adc_driver.c +++ b/components/esp_adc/test_apps/adc/main/test_adc_driver.c @@ -72,7 +72,7 @@ TEST_CASE("ADC oneshot fast work with ISR", "[adc_oneshot]") //-------------ADC1 Init---------------// adc_oneshot_unit_init_cfg_t init_config1 = { .unit_id = ADC_UNIT_1, - .ulp_mode = false, + .ulp_mode = ADC_ULP_MODE_DISABLE, }; TEST_ESP_OK(adc_oneshot_new_unit(&init_config1, &isr_test_ctx.adc_handle)); diff --git a/components/esp_adc/test_apps/adc/main/test_adc_driver_iram.c b/components/esp_adc/test_apps/adc/main/test_adc_driver_iram.c index bfdf8822bf..c48fc746a1 100644 --- a/components/esp_adc/test_apps/adc/main/test_adc_driver_iram.c +++ b/components/esp_adc/test_apps/adc/main/test_adc_driver_iram.c @@ -78,7 +78,7 @@ TEST_CASE("ADC oneshot fast work with ISR and Flash", "[adc_oneshot]") //-------------ADC1 Init---------------// adc_oneshot_unit_init_cfg_t init_config1 = { .unit_id = ADC_UNIT_1, - .ulp_mode = false, + .ulp_mode = ADC_ULP_MODE_DISABLE, }; TEST_ESP_OK(adc_oneshot_new_unit(&init_config1, &oneshot_handle)); @@ -215,14 +215,12 @@ TEST_CASE("ADC continuous work with ISR and Flash", "[adc_oneshot]") }; TEST_ESP_OK(adc_continuous_register_event_callbacks(handle, &cbs, &isr_test_ctx)); -#if CONFIG_IDF_TARGET_ESP32 - //This may need to be bigger, when the sampling freq is low - uint32_t overhead_us = 150; -#else - uint32_t overhead_us = 50; -#endif - uint32_t wait_time_us = (1000 * 1000 / ADC_TEST_FREQ_HZ * ADC_TEST_PKG_SIZE / SOC_ADC_DIGI_RESULT_BYTES) + overhead_us; - printf("period is %d us\n", wait_time_us); + /** + * Ideal time consumption for one conversion_frame done is `(1000 * 1000 / ADC_TEST_FREQ_HZ * ADC_TEST_PKG_SIZE / SOC_ADC_DIGI_RESULT_BYTES)` + * Here we just wait for 1 second + */ + uint32_t wait_time_us = 1 * 1000 * 1000; + printf("period is %"PRId32" us\n", wait_time_us); //ADC IO tile low test_adc_set_io_level(ADC_UNIT_1, ADC1_TEST_CHAN0, 0); @@ -233,6 +231,7 @@ TEST_CASE("ADC continuous work with ISR and Flash", "[adc_oneshot]") //Checks TEST_ASSERT_INT_WITHIN(ADC_TEST_LOW_THRESH, ADC_TEST_LOW_VAL, isr_test_ctx.adc_raw_low); esp_rom_printf("callback runs %d times when $ disabled\n", isr_test_ctx.cb_exe_times_low); + //At least 1 time conv_done callback happens during this period is ok TEST_ASSERT_GREATER_OR_EQUAL(1, isr_test_ctx.cb_exe_times_low); vTaskDelay(10); @@ -245,8 +244,9 @@ TEST_CASE("ADC continuous work with ISR and Flash", "[adc_oneshot]") s_test_cache_disable_period_us(&isr_test_ctx, wait_time_us); TEST_ESP_OK(adc_continuous_stop(handle)); //Checks - // TEST_ASSERT_INT_WITHIN(ADC_TEST_HIGH_THRESH, ADC_TEST_HIGH_VAL_DMA, isr_test_ctx.adc_raw_high); + TEST_ASSERT_INT_WITHIN(ADC_TEST_HIGH_THRESH, ADC_TEST_HIGH_VAL_DMA, isr_test_ctx.adc_raw_high); esp_rom_printf("callback runs %d times when $ disabled\n", isr_test_ctx.cb_exe_times_high); + //At least 1 time conv_done callback happens during this period is ok TEST_ASSERT_GREATER_OR_EQUAL(1, isr_test_ctx.cb_exe_times_high); TEST_ESP_OK(adc_continuous_deinit(handle)); diff --git a/components/esp_adc/test_apps/adc/main/test_adc_performance.c b/components/esp_adc/test_apps/adc/main/test_adc_performance.c index bf4bbecdd4..8b4b1cebf5 100644 --- a/components/esp_adc/test_apps/adc/main/test_adc_performance.c +++ b/components/esp_adc/test_apps/adc/main/test_adc_performance.c @@ -134,7 +134,7 @@ TEST_CASE("ADC1 oneshot raw average / std_deviation", "[adc_oneshot][ignore][man adc_oneshot_unit_handle_t adc1_handle; adc_oneshot_unit_init_cfg_t init_config1 = { .unit_id = ADC_UNIT_1, - .ulp_mode = false, + .ulp_mode = ADC_ULP_MODE_DISABLE, }; TEST_ESP_OK(adc_oneshot_new_unit(&init_config1, &adc1_handle)); @@ -254,7 +254,7 @@ static void s_adc_cali_speed(adc_unit_t unit_id, adc_channel_t channel) adc_oneshot_unit_handle_t adc_handle; adc_oneshot_unit_init_cfg_t init_config = { .unit_id = unit_id, - .ulp_mode = false, + .ulp_mode = ADC_ULP_MODE_DISABLE, }; TEST_ESP_OK(adc_oneshot_new_unit(&init_config, &adc_handle)); diff --git a/components/esp_adc/test_apps/adc/main/test_common_adc.h b/components/esp_adc/test_apps/adc/main/test_common_adc.h index 05a270bf1d..99b80a0eb1 100644 --- a/components/esp_adc/test_apps/adc/main/test_common_adc.h +++ b/components/esp_adc/test_apps/adc/main/test_common_adc.h @@ -10,6 +10,7 @@ #include #include #include "sdkconfig.h" +#include "unity.h" #include "esp_log.h" #include "soc/soc_caps.h" #include "esp_private/adc_private.h" @@ -71,7 +72,7 @@ void test_adc_calibration_deinit(adc_cali_handle_t handle); #elif CONFIG_IDF_TARGET_ESP32C3 #define ADC_TEST_LOW_VAL 0 -#define ADC_TEST_LOW_THRESH 60 +#define ADC_TEST_LOW_THRESH 60 //This is due to ADC2 accuracy is not as good as ADC1, and also we use weak pulldown #define ADC_TEST_HIGH_VAL 4095 #define ADC_TEST_HIGH_VAL_DMA 4095 @@ -87,7 +88,7 @@ void test_adc_calibration_deinit(adc_cali_handle_t handle); #elif CONFIG_IDF_TARGET_ESP32C2 #define ADC_TEST_LOW_VAL 2147 -#define ADC_TEST_LOW_THRESH 50 +#define ADC_TEST_LOW_THRESH 100 #define ADC_TEST_HIGH_VAL 4095 #define ADC_TEST_HIGH_THRESH 0 diff --git a/components/esp_adc/test_apps/adc/pytest_adc.py b/components/esp_adc/test_apps/adc/pytest_adc.py index 6bbeb4d5fa..bf7d2fb093 100644 --- a/components/esp_adc/test_apps/adc/pytest_adc.py +++ b/components/esp_adc/test_apps/adc/pytest_adc.py @@ -7,10 +7,10 @@ from pytest_embedded import Dut @pytest.mark.esp32 @pytest.mark.esp32s2 -@pytest.mark.esp32c3 @pytest.mark.esp32s3 +@pytest.mark.esp32c3 @pytest.mark.esp32c2 -@pytest.mark.generic +@pytest.mark.adc @pytest.mark.parametrize('config', [ 'iram_safe', 'release', diff --git a/components/esp_adc/test_apps/adc/sdkconfig.ci.iram_safe b/components/esp_adc/test_apps/adc/sdkconfig.ci.iram_safe index 45fabc5404..3e348d1911 100644 --- a/components/esp_adc/test_apps/adc/sdkconfig.ci.iram_safe +++ b/components/esp_adc/test_apps/adc/sdkconfig.ci.iram_safe @@ -1,8 +1,9 @@ CONFIG_COMPILER_DUMP_RTL_FILES=y CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM=y CONFIG_GPTIMER_ISR_IRAM_SAFE=y +CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM=y CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE=y -CONFIG_COMPILER_OPTIMIZATION_NONE=y +CONFIG_COMPILER_OPTIMIZATION_SIZE=y # silent the error check, as the error string are stored in rodata, causing RTL check failure CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT=y CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y diff --git a/components/esp_app_format/CMakeLists.txt b/components/esp_app_format/CMakeLists.txt new file mode 100644 index 0000000000..5a0d7460bb --- /dev/null +++ b/components/esp_app_format/CMakeLists.txt @@ -0,0 +1,26 @@ +idf_component_register(SRCS "esp_app_desc.c" + INCLUDE_DIRS "include") + +# esp_app_desc structure is added as an undefined symbol because otherwise the +# linker will ignore this structure as it has no other files depending on it. +if(NOT BOOTLOADER_BUILD) + target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_app_desc") +endif() + +if(CONFIG_APP_PROJECT_VER_FROM_CONFIG) + # Ignore current PROJECT_VER (which was set in __project_get_revision()). + # Gets the version from the CONFIG_APP_PROJECT_VER. + idf_build_set_property(PROJECT_VER "${CONFIG_APP_PROJECT_VER}") +endif() + +# cut PROJECT_VER and PROJECT_NAME to required 32 characters. +idf_build_get_property(project_ver PROJECT_VER) +idf_build_get_property(project_name PROJECT_NAME) +string(SUBSTRING "${project_ver}" 0 31 PROJECT_VER_CUT) +string(SUBSTRING "${project_name}" 0 31 PROJECT_NAME_CUT) +message(STATUS "App \"${PROJECT_NAME_CUT}\" version: ${PROJECT_VER_CUT}") + +set_source_files_properties( + SOURCE "esp_app_desc.c" + PROPERTIES COMPILE_DEFINITIONS + "PROJECT_VER=\"${PROJECT_VER_CUT}\"; PROJECT_NAME=\"${PROJECT_NAME_CUT}\"") diff --git a/components/app_update/Kconfig.projbuild b/components/esp_app_format/Kconfig.projbuild similarity index 100% rename from components/app_update/Kconfig.projbuild rename to components/esp_app_format/Kconfig.projbuild diff --git a/components/app_update/esp_app_desc.c b/components/esp_app_format/esp_app_desc.c similarity index 86% rename from components/app_update/esp_app_desc.c rename to components/esp_app_format/esp_app_desc.c index ae3325b1c3..edb22d0893 100644 --- a/components/app_update/esp_app_desc.c +++ b/components/esp_app_format/esp_app_desc.c @@ -1,17 +1,18 @@ /* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include #include -#include "esp_ota_ops.h" +#include "esp_app_desc.h" #include "esp_attr.h" #include "sdkconfig.h" + // Application version info -const __attribute__((section(".rodata_desc"))) esp_app_desc_t esp_app_desc = { +const __attribute__((weak)) __attribute__((section(".rodata_desc"))) esp_app_desc_t esp_app_desc = { .magic_word = ESP_APP_DESC_MAGIC_WORD, #ifdef CONFIG_APP_EXCLUDE_PROJECT_VER_VAR .version = "", @@ -50,7 +51,7 @@ _Static_assert(sizeof(IDF_VER) <= sizeof(esp_app_desc.idf_ver), "IDF_VER is long _Static_assert(sizeof(PROJECT_NAME) <= sizeof(esp_app_desc.project_name), "PROJECT_NAME is longer than project_name field in structure"); #endif -const esp_app_desc_t *esp_ota_get_app_description(void) +const esp_app_desc_t *esp_app_get_description(void) { return &esp_app_desc; } @@ -64,18 +65,18 @@ static inline char IRAM_ATTR to_hex_digit(unsigned val) return (val < 10) ? ('0' + val) : ('a' + val - 10); } -__attribute__((constructor)) void esp_ota_init_app_elf_sha256(void) +__attribute__((constructor)) void esp_init_app_elf_sha256(void) { - esp_ota_get_app_elf_sha256(NULL, 0); + esp_app_get_elf_sha256(NULL, 0); } /* The esp_app_desc.app_elf_sha256 should be possible to print in panic handler during cache is disabled. * But because the cache is disabled the reading esp_app_desc.app_elf_sha256 is not right and * can lead to a complete lock-up of the CPU. - * For this reason we do a reading of esp_app_desc.app_elf_sha256 while start up in esp_ota_init_app_elf_sha256() + * For this reason we do a reading of esp_app_desc.app_elf_sha256 while start up in esp_init_app_elf_sha256() * and keep it in the static s_app_elf_sha256 value. */ -int IRAM_ATTR esp_ota_get_app_elf_sha256(char* dst, size_t size) +int IRAM_ATTR esp_app_get_elf_sha256(char* dst, size_t size) { static char s_app_elf_sha256[CONFIG_APP_RETRIEVE_LEN_ELF_SHA / 2]; static bool first_call = true; diff --git a/components/esp_app_format/include/esp_app_desc.h b/components/esp_app_format/include/esp_app_desc.h new file mode 100644 index 0000000000..8f8241ba42 --- /dev/null +++ b/components/esp_app_format/include/esp_app_desc.h @@ -0,0 +1,61 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define ESP_APP_DESC_MAGIC_WORD (0xABCD5432) /*!< The magic word for the esp_app_desc structure that is in DROM. */ + +/** + * @brief Description about application. + */ +typedef struct { + uint32_t magic_word; /*!< Magic word ESP_APP_DESC_MAGIC_WORD */ + uint32_t secure_version; /*!< Secure version */ + uint32_t reserv1[2]; /*!< reserv1 */ + char version[32]; /*!< Application version */ + char project_name[32]; /*!< Project name */ + char time[16]; /*!< Compile time */ + char date[16]; /*!< Compile date*/ + char idf_ver[32]; /*!< Version IDF */ + uint8_t app_elf_sha256[32]; /*!< sha256 of elf file */ + uint32_t reserv2[20]; /*!< reserv2 */ +} esp_app_desc_t; + +/** @cond */ +_Static_assert(sizeof(esp_app_desc_t) == 256, "esp_app_desc_t should be 256 bytes"); +/** @endcond */ + +/** + * @brief Return esp_app_desc structure. This structure includes app version. + * + * Return description for running app. + * @return Pointer to esp_app_desc structure. + */ +const esp_app_desc_t *esp_app_get_description(void); + +/** + * @brief Fill the provided buffer with SHA256 of the ELF file, formatted as hexadecimal, null-terminated. + * If the buffer size is not sufficient to fit the entire SHA256 in hex plus a null terminator, + * the largest possible number of bytes will be written followed by a null. + * @param dst Destination buffer + * @param size Size of the buffer + * @return Number of bytes written to dst (including null terminator) + */ +int esp_app_get_elf_sha256(char* dst, size_t size); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_app_format/test_apps/CMakeLists.txt b/components/esp_app_format/test_apps/CMakeLists.txt new file mode 100644 index 0000000000..3ec91ae10d --- /dev/null +++ b/components/esp_app_format/test_apps/CMakeLists.txt @@ -0,0 +1,8 @@ +# This is the project CMakeLists.txt file for the test subproject +cmake_minimum_required(VERSION 3.16) + +# "Trim" the build. Include the minimal set of components, main, and anything it depends on. +set(COMPONENTS main) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(esp_app_format_test) diff --git a/components/esp_app_format/test_apps/README.md b/components/esp_app_format/test_apps/README.md new file mode 100644 index 0000000000..b5be4985c5 --- /dev/null +++ b/components/esp_app_format/test_apps/README.md @@ -0,0 +1,2 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | diff --git a/components/esp_app_format/test_apps/main/CMakeLists.txt b/components/esp_app_format/test_apps/main/CMakeLists.txt new file mode 100644 index 0000000000..9c31d04cdf --- /dev/null +++ b/components/esp_app_format/test_apps/main/CMakeLists.txt @@ -0,0 +1,3 @@ +idf_component_register(SRCS "test_app_desc.c" + PRIV_INCLUDE_DIRS . + PRIV_REQUIRES esp_app_format unity) diff --git a/components/app_update/test/test_app_desc.c b/components/esp_app_format/test_apps/main/test_app_desc.c similarity index 67% rename from components/app_update/test/test_app_desc.c rename to components/esp_app_format/test_apps/main/test_app_desc.c index c37fbe614b..99992702f0 100644 --- a/components/app_update/test/test_app_desc.c +++ b/components/esp_app_format/test_apps/main/test_app_desc.c @@ -1,13 +1,26 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ +#include #include -#include "esp_ota_ops.h" -#include "unity.h" -TEST_CASE("esp_ota_get_app_elf_sha256 test", "[esp_app_desc]") +#include "esp_app_desc.h" +#include "unity.h" +#include "unity_fixture.h" + +TEST_GROUP(esp_app_format); + +TEST_SETUP(esp_app_format) +{ +} + +TEST_TEAR_DOWN(esp_app_format) +{ +} + +TEST(esp_app_format, esp_app_get_elf_sha256_test) { const int sha256_hex_len = CONFIG_APP_RETRIEVE_LEN_ELF_SHA; char dst[sha256_hex_len + 2]; @@ -16,17 +29,17 @@ TEST_CASE("esp_ota_get_app_elf_sha256 test", "[esp_app_desc]") size_t len; char ref_sha256[sha256_hex_len + 1]; - const esp_app_desc_t* desc = esp_ota_get_app_description(); + const esp_app_desc_t* desc = esp_app_get_description(); for (int i = 0; i < sizeof(ref_sha256) / 2; ++i) { snprintf(ref_sha256 + 2*i, 3, "%02x", desc->app_elf_sha256[i]); } ref_sha256[sha256_hex_len] = 0; - printf("Ref: %s\n", ref_sha256); + printf("\nRef: %s\n", ref_sha256); memset(dst, fill, sizeof(dst)); len = sizeof(dst); - res = esp_ota_get_app_elf_sha256(dst, len); + res = esp_app_get_elf_sha256(dst, len); printf("%d: %s (%d)\n", len, dst, res); TEST_ASSERT_EQUAL(sha256_hex_len + 1, res); TEST_ASSERT_EQUAL(0, memcmp(dst, ref_sha256, res - 1)); @@ -35,7 +48,7 @@ TEST_CASE("esp_ota_get_app_elf_sha256 test", "[esp_app_desc]") memset(dst, fill, sizeof(dst)); len = 9; - res = esp_ota_get_app_elf_sha256(dst, len); + res = esp_app_get_elf_sha256(dst, len); printf("%d: %s (%d)\n", len, dst, res); TEST_ASSERT_EQUAL(9, res); TEST_ASSERT_EQUAL(0, memcmp(dst, ref_sha256, res - 1)); @@ -44,7 +57,7 @@ TEST_CASE("esp_ota_get_app_elf_sha256 test", "[esp_app_desc]") memset(dst, fill, sizeof(dst)); len = 8; - res = esp_ota_get_app_elf_sha256(dst, len); + res = esp_app_get_elf_sha256(dst, len); printf("%d: %s (%d)\n", len, dst, res); // should output even number of characters plus '\0' TEST_ASSERT_EQUAL(7, res); @@ -53,3 +66,13 @@ TEST_CASE("esp_ota_get_app_elf_sha256 test", "[esp_app_desc]") TEST_ASSERT_EQUAL_HEX(fill, dst[7]); TEST_ASSERT_EQUAL_HEX(fill, dst[8]); } + +TEST_GROUP_RUNNER(esp_app_format) +{ + RUN_TEST_CASE(esp_app_format, esp_app_get_elf_sha256_test) +} + +void app_main(void) +{ + UNITY_MAIN(esp_app_format); +} diff --git a/components/esp_app_format/test_apps/pytest_esp_app_format.py b/components/esp_app_format/test_apps/pytest_esp_app_format.py new file mode 100644 index 0000000000..6c10ccd929 --- /dev/null +++ b/components/esp_app_format/test_apps/pytest_esp_app_format.py @@ -0,0 +1,11 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +import pytest +from pytest_embedded import Dut + + +@pytest.mark.supported_targets +@pytest.mark.generic +def test_esp_app_format(dut: Dut) -> None: + dut.expect_unity_test_output() diff --git a/components/esp_app_format/test_apps/sdkconfig.defaults b/components/esp_app_format/test_apps/sdkconfig.defaults new file mode 100644 index 0000000000..a3253f171f --- /dev/null +++ b/components/esp_app_format/test_apps/sdkconfig.defaults @@ -0,0 +1,11 @@ +# General options for additional checks +CONFIG_HEAP_POISONING_COMPREHENSIVE=y +CONFIG_COMPILER_WARN_WRITE_STRINGS=y +CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y +CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y +CONFIG_COMPILER_STACK_CHECK_MODE_STRONG=y +CONFIG_COMPILER_STACK_CHECK=y + +# Enable Unity fixture support +CONFIG_UNITY_ENABLE_FIXTURE=y +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=n diff --git a/components/esp_common/CMakeLists.txt b/components/esp_common/CMakeLists.txt index 827c6ead46..ba77a6b87f 100644 --- a/components/esp_common/CMakeLists.txt +++ b/components/esp_common/CMakeLists.txt @@ -1,9 +1,11 @@ idf_build_get_property(target IDF_TARGET) if(${target} STREQUAL "linux") - # Header only library for linux - idf_component_register(INCLUDE_DIRS include) - return() + set(ldfragments) + set(srcs "src/esp_err_check_linux.c") +else() + set(ldfragments common.lf soc.lf) + set(srcs) endif() list(APPEND srcs "src/esp_err_to_name.c") @@ -11,7 +13,7 @@ list(APPEND srcs "src/esp_err_to_name.c") # Note: esp_ipc, esp_pm added as a public requirement to keep compatibility as to be located here. idf_component_register(SRCS "${srcs}" INCLUDE_DIRS include - LDFRAGMENTS "common.lf" "soc.lf") + LDFRAGMENTS ${ldfragments}) set_property(TARGET ${COMPONENT_LIB} APPEND PROPERTY LINK_INTERFACE_MULTIPLICITY 4) diff --git a/components/esp_common/project_include.cmake b/components/esp_common/project_include.cmake index e7b1d65448..2665404c50 100644 --- a/components/esp_common/project_include.cmake +++ b/components/esp_common/project_include.cmake @@ -2,9 +2,12 @@ # Warn if the toolchain version doesn't match # if(NOT (${target} STREQUAL "linux" OR CMAKE_C_COMPILER_ID MATCHES "Clang")) - get_expected_ctng_version(expected_toolchain expected_gcc) - gcc_version_check("${expected_gcc}") - crosstool_version_check("${expected_toolchain}") + execute_process( + COMMAND ${CMAKE_C_COMPILER} -dumpmachine + OUTPUT_VARIABLE toolchain_name + OUTPUT_STRIP_TRAILING_WHITESPACE + ERROR_QUIET) + check_expected_tool_version(${toolchain_name} ${CMAKE_C_COMPILER}) endif() if(NOT ${target} STREQUAL "linux" AND CMAKE_C_COMPILER_ID MATCHES "Clang") diff --git a/components/nvs_flash/test_nvs_host/esp_error_check_stub.cpp b/components/esp_common/src/esp_err_check_linux.c similarity index 54% rename from components/nvs_flash/test_nvs_host/esp_error_check_stub.cpp rename to components/esp_common/src/esp_err_check_linux.c index 34d8704e7b..fec85070db 100644 --- a/components/nvs_flash/test_nvs_host/esp_error_check_stub.cpp +++ b/components/esp_common/src/esp_err_check_linux.c @@ -1,4 +1,14 @@ -#include "catch.hpp" +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + * + * This file provides a simple version of _esp_error_check_failed which is used on Linux target. + * For chip targets, esp_system component provides an implementation which uses esp_rom_printf and + * takes the possibility of the cache being disabled into account. + */ +#include +#include #include "esp_err.h" #include "sdkconfig.h" diff --git a/components/esp_common/src/esp_err_to_name.c b/components/esp_common/src/esp_err_to_name.c index 2001b036d2..b8352c4d0e 100644 --- a/components/esp_common/src/esp_err_to_name.c +++ b/components/esp_common/src/esp_err_to_name.c @@ -7,6 +7,10 @@ //Do not edit this file because it is autogenerated by gen_esp_err_to_name.py #include +#if __has_include() +// for strlcpy +#include +#endif #include "esp_err.h" #if __has_include("soc/soc.h") #include "soc/soc.h" diff --git a/components/esp_common/src/esp_err_to_name.c.in b/components/esp_common/src/esp_err_to_name.c.in index 56a48ee28f..389600d536 100644 --- a/components/esp_common/src/esp_err_to_name.c.in +++ b/components/esp_common/src/esp_err_to_name.c.in @@ -7,6 +7,10 @@ @COMMENT@ #include +#if __has_include() +// for strlcpy +#include +#endif #include "esp_err.h" #if __has_include("soc/soc.h") #include "soc/soc.h" diff --git a/components/esp_event/host_test/esp_event_unit_test/CMakeLists.txt b/components/esp_event/host_test/esp_event_unit_test/CMakeLists.txt index e5f85c0de4..a013fc3920 100644 --- a/components/esp_event/host_test/esp_event_unit_test/CMakeLists.txt +++ b/components/esp_event/host_test/esp_event_unit_test/CMakeLists.txt @@ -3,6 +3,5 @@ cmake_minimum_required(VERSION 3.16) include($ENV{IDF_PATH}/tools/cmake/project.cmake) set(COMPONENTS main) -idf_build_set_property(COMPILE_DEFINITIONS "-DNO_DEBUG_STORAGE" APPEND) list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/mocks/freertos/") project(test_esp_event_host) diff --git a/components/esp_event/include/esp_event.h b/components/esp_event/include/esp_event.h index 47e21ca966..fcf61dc09f 100644 --- a/components/esp_event/include/esp_event.h +++ b/components/esp_event/include/esp_event.h @@ -108,9 +108,6 @@ esp_err_t esp_event_loop_run(esp_event_loop_handle_t event_loop, TickType_t tick /** * @brief Register an event handler to the system event loop (legacy). * - * @note This function is obsolete and will be deprecated soon, please use esp_event_handler_instance_register() - * instead. - * * This function can be used to register a handler for either: (1) specific events, * (2) all events of a certain event base, or (3) all events known by the system event loop. * @@ -144,9 +141,6 @@ esp_err_t esp_event_handler_register(esp_event_base_t event_base, /** * @brief Register an event handler to a specific loop (legacy). * - * @note This function is obsolete and will be deprecated soon, please use esp_event_handler_instance_register_with() - * instead. - * * This function behaves in the same manner as esp_event_handler_register, except the additional * specification of the event loop to register the handler to. * @@ -252,9 +246,6 @@ esp_err_t esp_event_handler_instance_register(esp_event_base_t event_base, /** * @brief Unregister a handler with the system event loop (legacy). * - * @note This function is obsolete and will be deprecated soon, please use esp_event_handler_instance_unregister() - * instead. - * * Unregisters a handler, so it will no longer be called during dispatch. * Handlers can be unregistered for any combination of event_base and event_id which were previously registered. * To unregister a handler, the event_base and event_id arguments must match exactly the arguments passed to @@ -280,9 +271,6 @@ esp_err_t esp_event_handler_unregister(esp_event_base_t event_base, /** * @brief Unregister a handler from a specific event loop (legacy). * - * @note This function is obsolete and will be deprecated soon, please use esp_event_handler_instance_unregister_with() - * instead. - * * This function behaves in the same manner as esp_event_handler_unregister, except the additional specification of * the event loop to unregister the handler with. * diff --git a/components/esp_event/test/test_event.c b/components/esp_event/test/test_event.c index bea936eb9e..4e60673273 100644 --- a/components/esp_event/test/test_event.c +++ b/components/esp_event/test/test_event.c @@ -22,8 +22,6 @@ #include "test_utils.h" -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) -//IDF-4035 static const char* TAG = "test_event"; #define TEST_CONFIG_ITEMS_TO_REGISTER 5 @@ -2021,4 +2019,3 @@ TEST_CASE("can post events from interrupt handler", "[event]") } #endif // CONFIG_ESP_EVENT_POST_FROM_ISR -#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) diff --git a/components/esp_gdbstub/esp32c6/gdbstub_esp32c6.c b/components/esp_gdbstub/esp32c6/gdbstub_esp32c6.c new file mode 100644 index 0000000000..34f3c687e5 --- /dev/null +++ b/components/esp_gdbstub/esp32c6/gdbstub_esp32c6.c @@ -0,0 +1,140 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include "soc/uart_periph.h" +#include "soc/gpio_periph.h" +#include "soc/soc.h" +#include "soc/usb_serial_jtag_struct.h" +#include "hal/usb_serial_jtag_ll.h" +#include "esp_gdbstub_common.h" +#include "sdkconfig.h" + +#define UART_NUM CONFIG_ESP_CONSOLE_UART_NUM + +#define GDBSTUB_MEM_REGION_COUNT 9 + +#define UART_REG_FIELD_LEN 0x84 + +typedef struct { + intptr_t lower; + intptr_t upper; +} mem_bound_t; + +static const mem_bound_t mem_region_table [GDBSTUB_MEM_REGION_COUNT] = +{ + {SOC_DROM_LOW, SOC_DROM_HIGH}, + {SOC_IROM_LOW, SOC_IROM_HIGH}, + {SOC_IRAM_LOW, SOC_IRAM_HIGH}, + {SOC_DRAM_LOW, SOC_DRAM_HIGH}, + {SOC_IROM_MASK_LOW, SOC_IROM_MASK_HIGH}, + {SOC_DROM_MASK_LOW, SOC_DROM_MASK_HIGH}, + {SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH}, + // RTC DRAM and RTC DATA are identical with RTC IRAM, hence we skip them + // We shouldn't read the uart registers since it will disturb the debugging via UART, + // so skip UART part of the peripheral registers. + {DR_REG_UART_BASE + UART_REG_FIELD_LEN, SOC_PERIPHERAL_HIGH}, + {SOC_DEBUG_LOW, SOC_DEBUG_HIGH}, +}; + +static inline bool check_inside_valid_region(intptr_t addr) +{ + for (size_t i = 0; i < GDBSTUB_MEM_REGION_COUNT; i++) { + if (addr >= mem_region_table[i].lower && addr < mem_region_table[i].upper) { + return true; + } + } + + return false; +} + +void esp_gdbstub_target_init() +{ +} + +#if CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG + +int esp_gdbstub_getchar() +{ + uint8_t c; + //retry the read until we succeed + while (usb_serial_jtag_ll_read_rxfifo(&c, 1)==0) ; + return c; +} + +void esp_gdbstub_putchar(int c) +{ + uint8_t cc=c; + //retry the write until we succeed + while (usb_serial_jtag_ll_write_txfifo(&cc, 1)<1) ; +} + +void esp_gdbstub_flush() +{ + usb_serial_jtag_ll_txfifo_flush(); +} + + +#else + +//assume UART gdbstub channel + +int esp_gdbstub_getchar() +{ + while (REG_GET_FIELD(UART_STATUS_REG(UART_NUM), UART_RXFIFO_CNT) == 0) { + ; + } + return REG_READ(UART_FIFO_AHB_REG(UART_NUM)); +} + +void esp_gdbstub_putchar(int c) +{ + while (REG_GET_FIELD(UART_STATUS_REG(UART_NUM), UART_TXFIFO_CNT) >= 126) { + ; + } + REG_WRITE(UART_FIFO_AHB_REG(UART_NUM), c); +} + +void esp_gdbstub_flush() +{ + //not needed for uart +} + +#endif + +int esp_gdbstub_readmem(intptr_t addr) +{ + if (!check_inside_valid_region(addr)) { + /* see esp_cpu_configure_region_protection */ + return -1; + } + uint32_t val_aligned = *(uint32_t *)(addr & (~3)); + uint32_t shift = (addr & 3) * 8; + return (val_aligned >> shift) & 0xff; +} + +int esp_gdbstub_writemem(unsigned int addr, unsigned char data) +{ + if (!check_inside_valid_region(addr)) { + /* see esp_cpu_configure_region_protection */ + return -1; + } + + int *i = (int *)(addr & (~3)); + if ((addr & 3) == 0) { + *i = (*i & 0xffffff00) | (data << 0); + } + if ((addr & 3) == 1) { + *i = (*i & 0xffff00ff) | (data << 8); + } + if ((addr & 3) == 2) { + *i = (*i & 0xff00ffff) | (data << 16); + } + if ((addr & 3) == 3) { + *i = (*i & 0x00ffffff) | (data << 24); + } + return 0; +} diff --git a/components/mqtt/host_test/mocks/include/local_FreeRTOS_config.h b/components/esp_gdbstub/esp32c6/gdbstub_target_config.h similarity index 76% rename from components/mqtt/host_test/mocks/include/local_FreeRTOS_config.h rename to components/esp_gdbstub/esp32c6/gdbstub_target_config.h index e7e1014beb..e9b4a08c59 100644 --- a/components/mqtt/host_test/mocks/include/local_FreeRTOS_config.h +++ b/components/esp_gdbstub/esp32c6/gdbstub_target_config.h @@ -3,4 +3,5 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#define configUSE_TRACE_FACILITY 1 + +#pragma once diff --git a/components/esp_gdbstub/src/gdbstub.c b/components/esp_gdbstub/src/gdbstub.c index 7ce49c63ac..bd859faa14 100644 --- a/components/esp_gdbstub/src/gdbstub.c +++ b/components/esp_gdbstub/src/gdbstub.c @@ -114,7 +114,11 @@ static uint32_t gdbstub_hton(uint32_t i) return __builtin_bswap32(i); } +#if !CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5653 static wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; +#else +static wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &LP_WDT}; +#endif static wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0}; static wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1}; @@ -847,7 +851,7 @@ static bool get_task_handle(size_t index, TaskHandle_t *handle) static eTaskState get_task_state(size_t index) { eTaskState result = eReady; - TaskHandle_t handle; + TaskHandle_t handle = NULL; get_task_handle(index, &handle); if (gdb_debug_int == false) { result = eTaskGetState(handle); @@ -858,7 +862,9 @@ static eTaskState get_task_state(size_t index) static int get_task_cpu_id(size_t index) { TaskHandle_t handle; - get_task_handle(index, &handle); + if (!get_task_handle(index, &handle)) { + return -1; + } BaseType_t core_id = xTaskGetAffinity(handle); return (int)core_id; } diff --git a/components/esp_hid/src/ble_hidh.c b/components/esp_hid/src/ble_hidh.c index a76febfbf1..f4daf07148 100644 --- a/components/esp_hid/src/ble_hidh.c +++ b/components/esp_hid/src/ble_hidh.c @@ -104,6 +104,8 @@ static void read_device_services(esp_gatt_if_t gattc_if, esp_hidh_dev_t *dev) ESP_LOGE(TAG, "malloc report maps failed"); return; } + /* read characteristic value may failed, so we should init report maps */ + memset(dev->config.report_maps, 0, dev->config.report_maps_len * sizeof(esp_hid_raw_report_map_t)); for (uint16_t s = 0; s < dcount; s++) { suuid = service_result[s].uuid.uuid.uuid16; diff --git a/components/esp_hid/src/esp_hidh.c b/components/esp_hid/src/esp_hidh.c index c871ee9881..b052cc472f 100644 --- a/components/esp_hid/src/esp_hidh.c +++ b/components/esp_hid/src/esp_hidh.c @@ -657,7 +657,10 @@ static void esp_hidh_dev_resources_free(esp_hidh_dev_t *dev) free((void *)dev->config.manufacturer_name); free((void *)dev->config.serial_number); for (uint8_t d = 0; d < dev->config.report_maps_len; d++) { - free((void *)dev->config.report_maps[d].data); + /* data of report map maybe is NULL */ + if (dev->config.report_maps[d].data) { + free((void *)dev->config.report_maps[d].data); + } } free((void *)dev->config.report_maps); esp_hidh_dev_report_t *r; diff --git a/components/esp_http_client/esp_http_client.c b/components/esp_http_client/esp_http_client.c index 221cc64526..e97291331a 100644 --- a/components/esp_http_client/esp_http_client.c +++ b/components/esp_http_client/esp_http_client.c @@ -670,6 +670,10 @@ esp_http_client_handle_t esp_http_client_init(const esp_http_client_config_t *co if (config->skip_cert_common_name_check) { esp_transport_ssl_skip_common_name_check(ssl); } + + if (config->common_name) { + esp_transport_ssl_set_common_name(ssl, config->common_name); + } #endif if (_set_config(client, config) != ESP_OK) { diff --git a/components/esp_http_client/include/esp_http_client.h b/components/esp_http_client/include/esp_http_client.h index 586b38f6fe..e5e91650fc 100644 --- a/components/esp_http_client/include/esp_http_client.h +++ b/components/esp_http_client/include/esp_http_client.h @@ -129,6 +129,9 @@ typedef struct { bool is_async; /*!< Set asynchronous mode, only supported with HTTPS for now */ bool use_global_ca_store; /*!< Use a global ca_store for all the connections in which this bool is set. */ bool skip_cert_common_name_check; /*!< Skip any validation of server certificate CN field */ + const char *common_name; /*!< Pointer to the string containing server certificate common name. + If non-NULL, server certificate CN must match this name, + If NULL, server certificate CN must match hostname. */ esp_err_t (*crt_bundle_attach)(void *conf); /*!< Function pointer to esp_crt_bundle_attach. Enables the use of certification bundle for server verification, must be enabled in menuconfig */ bool keep_alive_enable; /*!< Enable keep-alive timeout */ diff --git a/components/esp_http_client/test/CMakeLists.txt b/components/esp_http_client/test/CMakeLists.txt deleted file mode 100644 index a89a0394e6..0000000000 --- a/components/esp_http_client/test/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -idf_component_register(SRC_DIRS "." - PRIV_INCLUDE_DIRS "." - PRIV_REQUIRES cmock test_utils esp_http_client) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/components/esp_http_client/test_apps/CMakeLists.txt b/components/esp_http_client/test_apps/CMakeLists.txt new file mode 100644 index 0000000000..e26a96a791 --- /dev/null +++ b/components/esp_http_client/test_apps/CMakeLists.txt @@ -0,0 +1,7 @@ +#This is the project CMakeLists.txt file for the test subproject +cmake_minimum_required(VERSION 3.16) + +set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components") + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(esp_http_client_test) diff --git a/components/esp_http_client/test_apps/README.md b/components/esp_http_client/test_apps/README.md new file mode 100644 index 0000000000..27995c13b2 --- /dev/null +++ b/components/esp_http_client/test_apps/README.md @@ -0,0 +1,3 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | + diff --git a/components/esp_http_client/test_apps/main/CMakeLists.txt b/components/esp_http_client/test_apps/main/CMakeLists.txt new file mode 100644 index 0000000000..0c7a34fc19 --- /dev/null +++ b/components/esp_http_client/test_apps/main/CMakeLists.txt @@ -0,0 +1,3 @@ +idf_component_register(SRC_DIRS "." + PRIV_INCLUDE_DIRS "." + PRIV_REQUIRES esp_http_client test_utils unity) diff --git a/components/esp_http_client/test/test_http_client.c b/components/esp_http_client/test_apps/main/test_http_client.c similarity index 99% rename from components/esp_http_client/test/test_http_client.c rename to components/esp_http_client/test_apps/main/test_http_client.c index dc92075efa..f4b1e081f8 100644 --- a/components/esp_http_client/test/test_http_client.c +++ b/components/esp_http_client/test_apps/main/test_http_client.c @@ -145,3 +145,8 @@ TEST_CASE("esp_http_client_init() should return NULL if configured with wrong ur TEST_ASSERT_NULL(client); esp_http_client_cleanup(client); } + +void app_main(void) +{ + unity_run_menu(); +} diff --git a/components/esp_http_client/test_apps/pytest_esp_http_client_ut.py b/components/esp_http_client/test_apps/pytest_esp_http_client_ut.py new file mode 100644 index 0000000000..30db4a6348 --- /dev/null +++ b/components/esp_http_client/test_apps/pytest_esp_http_client_ut.py @@ -0,0 +1,13 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +import pytest +from pytest_embedded import Dut + + +@pytest.mark.supported_targets +@pytest.mark.generic +def test_esp_http_client(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('*') + dut.expect_unity_test_output() diff --git a/components/esp_http_client/test_apps/sdkconfig.defaults b/components/esp_http_client/test_apps/sdkconfig.defaults new file mode 100644 index 0000000000..ec826a5a16 --- /dev/null +++ b/components/esp_http_client/test_apps/sdkconfig.defaults @@ -0,0 +1,9 @@ +# General options for additional checks +CONFIG_HEAP_POISONING_COMPREHENSIVE=y +CONFIG_COMPILER_WARN_WRITE_STRINGS=y +CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y +CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y +CONFIG_COMPILER_STACK_CHECK_MODE_STRONG=y +CONFIG_COMPILER_STACK_CHECK=y + +CONFIG_ESP_TASK_WDT=n diff --git a/components/esp_http_server/include/esp_http_server.h b/components/esp_http_server/include/esp_http_server.h index be9d0d9cd3..9523918c1b 100644 --- a/components/esp_http_server/include/esp_http_server.h +++ b/components/esp_http_server/include/esp_http_server.h @@ -40,6 +40,8 @@ initializer that should be kept in sync .global_user_ctx_free_fn = NULL, \ .global_transport_ctx = NULL, \ .global_transport_ctx_free_fn = NULL, \ + .enable_so_linger = false, \ + .linger_timeout = 0, \ .open_fn = NULL, \ .close_fn = NULL, \ .uri_match_fn = NULL \ @@ -185,6 +187,9 @@ typedef struct httpd_config { */ httpd_free_ctx_fn_t global_transport_ctx_free_fn; + bool enable_so_linger; /*!< bool to enable/disable linger */ + int linger_timeout; /*!< linger timeout (in seconds) */ + /** * Custom session opening callback. * diff --git a/components/esp_http_server/src/httpd_sess.c b/components/esp_http_server/src/httpd_sess.c index dea8e67d1a..2681ca19f6 100644 --- a/components/esp_http_server/src/httpd_sess.c +++ b/components/esp_http_server/src/httpd_sess.c @@ -204,6 +204,9 @@ esp_err_t httpd_sess_new(struct httpd_data *hd, int newfd) session->send_fn = httpd_default_send; session->recv_fn = httpd_default_recv; + // increment number of sessions + hd->hd_sd_active_count++; + // Call user-defined session opening function if (hd->config.open_fn) { esp_err_t ret = hd->config.open_fn(hd, session->fd); @@ -214,10 +217,8 @@ esp_err_t httpd_sess_new(struct httpd_data *hd, int newfd) } } - // increment number of sessions - hd->hd_sd_active_count++; - ESP_LOGD(TAG, LOG_FMT("active sockets: %d"), hd->hd_sd_active_count); + ESP_LOGD(TAG, LOG_FMT("active sockets: %d"), hd->hd_sd_active_count); return ESP_OK; } @@ -353,6 +354,13 @@ void httpd_sess_delete(struct httpd_data *hd, struct sock_db *session) } ESP_LOGD(TAG, LOG_FMT("fd = %d"), session->fd); + if (hd->config.enable_so_linger) { + struct linger so_linger = { + .l_onoff = true, + .l_linger = hd->config.linger_timeout, + }; + setsockopt(session->fd, SOL_SOCKET, SO_LINGER, &so_linger, sizeof(struct linger)); + } // Call close function if defined if (hd->config.close_fn) { diff --git a/components/esp_http_server/test/CMakeLists.txt b/components/esp_http_server/test/CMakeLists.txt deleted file mode 100644 index 616c9a94fe..0000000000 --- a/components/esp_http_server/test/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -idf_component_register(SRC_DIRS "." - PRIV_INCLUDE_DIRS "." - PRIV_REQUIRES cmock test_utils esp_http_server) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/components/esp_http_server/test_apps/CMakeLists.txt b/components/esp_http_server/test_apps/CMakeLists.txt new file mode 100644 index 0000000000..3d62a12c41 --- /dev/null +++ b/components/esp_http_server/test_apps/CMakeLists.txt @@ -0,0 +1,7 @@ +#This is the project CMakeLists.txt file for the test subproject +cmake_minimum_required(VERSION 3.16) + +set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components") + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(esp_http_server_test) diff --git a/components/esp_http_server/test_apps/README.md b/components/esp_http_server/test_apps/README.md new file mode 100644 index 0000000000..b5be4985c5 --- /dev/null +++ b/components/esp_http_server/test_apps/README.md @@ -0,0 +1,2 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | diff --git a/components/esp_http_server/test_apps/main/CMakeLists.txt b/components/esp_http_server/test_apps/main/CMakeLists.txt new file mode 100644 index 0000000000..eb7ca6e23c --- /dev/null +++ b/components/esp_http_server/test_apps/main/CMakeLists.txt @@ -0,0 +1,3 @@ +idf_component_register(SRC_DIRS "." + PRIV_INCLUDE_DIRS "." + PRIV_REQUIRES esp_http_server test_utils unity) diff --git a/components/esp_http_server/test/test_http_server.c b/components/esp_http_server/test_apps/main/test_http_server.c similarity index 99% rename from components/esp_http_server/test/test_http_server.c rename to components/esp_http_server/test_apps/main/test_http_server.c index 9a1e49f571..0acb8c9ed4 100644 --- a/components/esp_http_server/test/test_http_server.c +++ b/components/esp_http_server/test_apps/main/test_http_server.c @@ -243,3 +243,8 @@ TEST_CASE("Max Allowed Sockets Test", "[HTTP SERVER]") config.max_open_sockets += 1; TEST_ASSERT(httpd_start(&hd, &config) != ESP_OK); } + +void app_main(void) +{ + unity_run_menu(); +} diff --git a/components/esp_http_server/test_apps/pytest_esp_http_server_ut.py b/components/esp_http_server/test_apps/pytest_esp_http_server_ut.py new file mode 100644 index 0000000000..fa02ded114 --- /dev/null +++ b/components/esp_http_server/test_apps/pytest_esp_http_server_ut.py @@ -0,0 +1,13 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +import pytest +from pytest_embedded import Dut + + +@pytest.mark.supported_targets +@pytest.mark.generic +def test_esp_http_server(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('*') + dut.expect_unity_test_output() diff --git a/components/esp_http_server/test_apps/sdkconfig.defaults b/components/esp_http_server/test_apps/sdkconfig.defaults new file mode 100644 index 0000000000..ec826a5a16 --- /dev/null +++ b/components/esp_http_server/test_apps/sdkconfig.defaults @@ -0,0 +1,9 @@ +# General options for additional checks +CONFIG_HEAP_POISONING_COMPREHENSIVE=y +CONFIG_COMPILER_WARN_WRITE_STRINGS=y +CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y +CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y +CONFIG_COMPILER_STACK_CHECK_MODE_STRONG=y +CONFIG_COMPILER_STACK_CHECK=y + +CONFIG_ESP_TASK_WDT=n diff --git a/components/esp_https_ota/CMakeLists.txt b/components/esp_https_ota/CMakeLists.txt index cee9eb7620..ef037f8b0f 100644 --- a/components/esp_https_ota/CMakeLists.txt +++ b/components/esp_https_ota/CMakeLists.txt @@ -1,6 +1,6 @@ idf_component_register(SRCS "src/esp_https_ota.c" INCLUDE_DIRS "include" - REQUIRES esp_http_client bootloader_support + REQUIRES esp_http_client bootloader_support esp_app_format PRIV_REQUIRES log app_update) target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/components/esp_https_ota/include/esp_https_ota.h b/components/esp_https_ota/include/esp_https_ota.h index 9dee205c5b..ba13ad619e 100644 --- a/components/esp_https_ota/include/esp_https_ota.h +++ b/components/esp_https_ota/include/esp_https_ota.h @@ -8,6 +8,7 @@ #include #include +#include "esp_app_desc.h" #include #ifdef __cplusplus diff --git a/components/esp_https_ota/src/esp_https_ota.c b/components/esp_https_ota/src/esp_https_ota.c index 76dc53cace..9d162c6387 100644 --- a/components/esp_https_ota/src/esp_https_ota.c +++ b/components/esp_https_ota/src/esp_https_ota.c @@ -254,6 +254,14 @@ esp_err_t esp_https_ota_begin(const esp_https_ota_config_t *ota_config, esp_http goto failure; } + if (ota_config->http_client_init_cb) { + err = ota_config->http_client_init_cb(https_ota_handle->http_client); + if (err != ESP_OK) { + ESP_LOGE(TAG, "http_client_init_cb returned 0x%x", err); + goto http_cleanup; + } + } + if (https_ota_handle->partial_http_download) { esp_http_client_set_method(https_ota_handle->http_client, HTTP_METHOD_HEAD); err = esp_http_client_perform(https_ota_handle->http_client); @@ -286,14 +294,6 @@ esp_err_t esp_https_ota_begin(const esp_https_ota_config_t *ota_config, esp_http esp_http_client_set_method(https_ota_handle->http_client, HTTP_METHOD_GET); } - if (ota_config->http_client_init_cb) { - err = ota_config->http_client_init_cb(https_ota_handle->http_client); - if (err != ESP_OK) { - ESP_LOGE(TAG, "http_client_init_cb returned 0x%x", err); - goto http_cleanup; - } - } - err = _http_connect(https_ota_handle->http_client); if (err != ESP_OK) { ESP_LOGE(TAG, "Failed to establish HTTP connection"); diff --git a/components/esp_https_server/include/esp_https_server.h b/components/esp_https_server/include/esp_https_server.h index e6111db6fa..9fbfe4c250 100644 --- a/components/esp_https_server/include/esp_https_server.h +++ b/components/esp_https_server/include/esp_https_server.h @@ -143,6 +143,7 @@ typedef struct httpd_ssl_config httpd_ssl_config_t; .port_secure = 443, \ .port_insecure = 80, \ .session_tickets = false, \ + .use_secure_element = false, \ .user_cb = NULL, \ } diff --git a/components/esp_hw_support/.build-test-rules.yml b/components/esp_hw_support/.build-test-rules.yml new file mode 100644 index 0000000000..01b0ede9a7 --- /dev/null +++ b/components/esp_hw_support/.build-test-rules.yml @@ -0,0 +1,7 @@ +# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps + +components/esp_hw_support/test_apps/dma: + disable_test: + - if: IDF_TARGET in ["esp32"] + temporary: false + reason: Neither GDMA nor CPDMA is supported on ESP32 diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index 71e063471c..d002f21150 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -45,6 +45,13 @@ if(NOT BOOTLOADER_BUILD) list(APPEND srcs "port/${target}/systimer.c") endif() + # ESP32C6-TODO + if(CONFIG_IDF_TARGET_ESP32C6) + list(REMOVE_ITEM srcs + "adc_share_hw_ctrl.c" # TODO: IDF-5312 + ) + endif() + else() # Requires "_esp_error_check_failed()" function list(APPEND priv_requires "esp_system") diff --git a/components/esp_hw_support/Kconfig b/components/esp_hw_support/Kconfig index 640a3cda96..34db231dec 100644 --- a/components/esp_hw_support/Kconfig +++ b/components/esp_hw_support/Kconfig @@ -40,7 +40,7 @@ menu "Hardware Settings" config ESP_SLEEP_GPIO_RESET_WORKAROUND bool "light sleep GPIO reset workaround" - default y if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 + default y if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 # TODO: IDF-5641 (esp32c6) select PM_SLP_DISABLE_GPIO if FREERTOS_USE_TICKLESS_IDLE help esp32c2, esp32c3 and esp32s3 will reset at wake-up if GPIO is received a small electrostatic @@ -114,12 +114,24 @@ menu "Hardware Settings" depends on ESP_CONSOLE_USB_SERIAL_JTAG || ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG default y help - When the chip goes sleep or software reset, the clock source would change to XTAL - and switch off the BBPLL clock for saving power. However, this might make the - USB_SERIAL_JTAG down which depends on BBPLL as its unique clock source. - Therefore, this is used for keeping bbpll clock always on when USB_SERIAL_JTAG PORT is using. - If you want to use USB_SERIAL_JTAG under sw_reset case or sleep-wakeup case, you shoule select - this option. But be aware that this might increase the power consumption. + When software switches the CPU clock source from BBPLL clock to XTAL, usually the BBPLL will be + switched off. This helps to save some power consumption in sleep modes. However this may also happen + during the software reset, resulting in the inactive (disconnected from host) of the USB_SERIAL_JTAG + device during software reset. + + When USB_SERIAL_JTAG is being used, whether to turn off the clock source during software reset and in + sleep modes is determined by RTC_CLOCK_BBPLL_POWER_ON_WITH_USB. + + - When RTC_CLOCK_BBPLL_POWER_ON_WITH_USB is enabled, the clock will be kept, so that the + USB_SERIAL_JTAG will keep alive during software reset. The side-effect is the increasing of power + consumption during sleep modes, even though USB_SERIAL_JTAG will not work in sleep modes. + + - When RTC_CLOCK_BBPLL_POWER_ON_WITH_USB is disabled, the clock will be turned off. USB_SERIAL_JTAG + will be inactive during software reset and in sleep modes. This saves some power consumption in + sleep modes. + + When USB_SERIAL_JTAG is not being used, software will always turn off BBPLL regardless of + RTC_CLOCK_BBPLL_POWER_ON_WITH_USB is set or not. endmenu menu "Peripheral Control" @@ -153,6 +165,7 @@ menu "Hardware Settings" config MMU_PAGE_MODE string + default "8KB" if MMU_PAGE_SIZE_8KB default "16KB" if MMU_PAGE_SIZE_16KB default "32KB" if MMU_PAGE_SIZE_32KB default "64KB" if MMU_PAGE_SIZE_64KB @@ -164,6 +177,7 @@ menu "Hardware Settings" # use of small flash sizes (reducing the wasted space due to alignment), we # need to use the smallest possible MMU page size for the given flash size. hex + default 0x2000 if MMU_PAGE_SIZE_8KB default 0x4000 if MMU_PAGE_SIZE_16KB default 0x8000 if MMU_PAGE_SIZE_32KB default 0x10000 if MMU_PAGE_SIZE_64KB diff --git a/components/esp_hw_support/adc_share_hw_ctrl.c b/components/esp_hw_support/adc_share_hw_ctrl.c index e3c0591e9e..ca6645efe9 100644 --- a/components/esp_hw_support/adc_share_hw_ctrl.c +++ b/components/esp_hw_support/adc_share_hw_ctrl.c @@ -97,7 +97,7 @@ void adc_power_release(void) static inline uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int atten) { - int tag = esp_efuse_rtc_table_get_tag(version, adc_unit + 1, atten, RTCCALIB_V2_PARAM_VINIT); + int tag = esp_efuse_rtc_table_get_tag(version, adc_unit, atten, RTCCALIB_V2_PARAM_VINIT); return esp_efuse_rtc_table_get_parsed_efuse_value(tag, false); } #endif diff --git a/components/esp_hw_support/cpu.c b/components/esp_hw_support/cpu.c index fb67935002..929aa32ff5 100644 --- a/components/esp_hw_support/cpu.c +++ b/components/esp_hw_support/cpu.c @@ -9,7 +9,17 @@ #include #include "soc/soc.h" #include "soc/soc_caps.h" + +// TODO: IDF-5645 +#if CONFIG_IDF_TARGET_ESP32C6 +#include "soc/lp_aon_reg.h" +#include "soc/pcr_reg.h" +#define SYSTEM_CPU_PER_CONF_REG PCR_CPU_WAITI_CONF_REG +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON PCR_CPU_WAIT_MODE_FORCE_ON +#else #include "soc/rtc_cntl_reg.h" +#endif + #include "hal/soc_hal.h" #include "hal/mpu_hal.h" #include "esp_bit_defs.h" @@ -81,6 +91,9 @@ void esp_cpu_unstall(int core_id) void esp_cpu_reset(int core_id) { +#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645 + SET_PERI_REG_MASK(LP_AON_CPUCORE0_CFG_REG, LP_AON_CPU_CORE0_SW_RESET); +#else assert(core_id >= 0 && core_id < SOC_CPU_CORES_NUM); #if SOC_CPU_CORES_NUM > 1 /* @@ -93,6 +106,7 @@ void esp_cpu_reset(int core_id) int rtc_cntl_rst_m = RTC_CNTL_SW_PROCPU_RST_M; #endif // SOC_CPU_CORES_NUM > 1 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, rtc_cntl_rst_m); +#endif } void esp_cpu_wait_for_intr(void) @@ -100,6 +114,7 @@ void esp_cpu_wait_for_intr(void) #if __XTENSA__ xt_utils_wait_for_intr(); #else + // TODO: IDF-5645 (better to implement with ll) C6 register names converted in the #include section at the top if (esp_cpu_dbgr_is_attached() && DPORT_REG_GET_BIT(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON) == 0) { /* when SYSTEM_CPU_WAIT_MODE_FORCE_ON is disabled in WFI mode SBA access to memory does not work for debugger, so do not enter that mode when debugger is connected */ @@ -125,7 +140,13 @@ static bool is_intr_num_resv(int intr_num) { // Workaround to reserve interrupt number 1 for Wi-Fi, 5,8 for Bluetooth, 6 for "permanently disabled interrupt" // [TODO: IDF-2465] - const uint32_t reserved = BIT(1) | BIT(5) | BIT(6) | BIT(8); + uint32_t reserved = BIT(1) | BIT(5) | BIT(6) | BIT(8); + + // int_num 0,3,4,7 are inavaliable for PULP cpu +#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5728 replace with a better macro name + reserved |= BIT(0) | BIT(3) | BIT(4) | BIT(7); +#endif + if (reserved & BIT(intr_num)) { return true; } @@ -501,6 +522,86 @@ void esp_cpu_configure_region_protection(void) PMP_ENTRY_CFG_SET(14, NONE); PMP_ENTRY_CFG_SET(15, PMP_TOR | NONE); } +#elif CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5642 +void esp_cpu_configure_region_protection(void) +{ + /* Notes on implementation: + * + * 1) Note: ESP32-C6 CPU doesn't support overlapping PMP regions + * + * 2) Therefore, we use TOR (top of range) entries to map the whole address + * space, bottom to top. + * + * 3) There are not enough entries to describe all the memory regions 100% accurately. + * + * 4) This means some gaps (invalid memory) are accessible. Priority for extending regions + * to cover gaps is to extend read-only or read-execute regions or read-only regions only + * (executing unmapped addresses should always fault with invalid instruction, read-only means + * stores will correctly fault even if reads may return some invalid value.) + * + * 5) Entries are grouped in order with some static asserts to try and verify everything is + * correct. + */ + const unsigned NONE = PMP_L | PMP_TOR; + const unsigned RW = PMP_L | PMP_TOR | PMP_R | PMP_W; + const unsigned RX = PMP_L | PMP_TOR | PMP_R | PMP_X; + const unsigned RWX = PMP_L | PMP_TOR | PMP_R | PMP_W | PMP_X; + + // 1. Gap at bottom of address space + PMP_ENTRY_SET(0, SOC_DEBUG_LOW, NONE); + + // 2. Debug region + PMP_ENTRY_SET(1, SOC_DEBUG_HIGH, RWX); + _Static_assert(SOC_DEBUG_LOW < SOC_DEBUG_HIGH, "Invalid CPU debug region"); + + // 3. Gap between debug region & IROM + PMP_ENTRY_SET(2, SOC_IROM_MASK_LOW, NONE); + _Static_assert(SOC_DEBUG_HIGH < SOC_IROM_MASK_LOW, "Invalid PMP entry order"); + + // 4. ROM + PMP_ENTRY_SET(3, SOC_DROM_MASK_HIGH, RX); + _Static_assert(SOC_IROM_MASK_LOW < SOC_DROM_MASK_HIGH, "Invalid ROM region"); + + // 5. Gap between ROM & RAM + PMP_ENTRY_SET(4, SOC_IRAM_LOW, NONE); + _Static_assert(SOC_DROM_MASK_HIGH < SOC_IRAM_LOW, "Invalid PMP entry order"); + + // 6. RAM + PMP_ENTRY_SET(5, SOC_IRAM_HIGH, RWX); + _Static_assert(SOC_IRAM_LOW < SOC_IRAM_HIGH, "Invalid RAM region"); + + // 7. Gap between DRAM and I_Cache + PMP_ENTRY_SET(6, SOC_IROM_LOW, NONE); + _Static_assert(SOC_IRAM_HIGH < SOC_IROM_LOW, "Invalid PMP entry order"); + + // 8. I_Cache (flash) + PMP_ENTRY_SET(7, SOC_IROM_HIGH, RWX); + _Static_assert(SOC_IROM_LOW < SOC_IROM_HIGH, "Invalid I_Cache region"); + + // 9. D_Cache (flash) + PMP_ENTRY_SET(8, SOC_DROM_HIGH, RW); + _Static_assert(SOC_DROM_LOW < SOC_DROM_HIGH, "Invalid D_Cache region"); + + // 10. Gap between D_Cache & LP_RAM + PMP_ENTRY_SET(9, SOC_RTC_IRAM_LOW, NONE); + _Static_assert(SOC_DROM_HIGH < SOC_RTC_IRAM_LOW, "Invalid PMP entry order"); + + // 16. LP memory + PMP_ENTRY_SET(10, SOC_RTC_IRAM_HIGH, RWX); + _Static_assert(SOC_RTC_IRAM_LOW < SOC_RTC_IRAM_HIGH, "Invalid RTC IRAM region"); + + // 17. Gap between LP memory & peripheral addresses + PMP_ENTRY_SET(11, SOC_PERIPHERAL_LOW, NONE); + _Static_assert(SOC_RTC_IRAM_HIGH < SOC_PERIPHERAL_LOW, "Invalid PMP entry order"); + + // 18. Peripheral addresses + PMP_ENTRY_SET(12, SOC_PERIPHERAL_HIGH, RW); + _Static_assert(SOC_PERIPHERAL_LOW < SOC_PERIPHERAL_HIGH, "Invalid peripheral region"); + + // 19. End of address space + PMP_ENTRY_SET(13, UINT32_MAX, NONE); // all but last 4 bytes + PMP_ENTRY_SET(14, UINT32_MAX, PMP_L | PMP_NA4); // last 4 bytes +} #endif /* ---------------------------------------------------- Debugging ------------------------------------------------------ diff --git a/components/esp_hw_support/esp_clk.c b/components/esp_hw_support/esp_clk.c index 0fd5deec93..752a3e987e 100644 --- a/components/esp_hw_support/esp_clk.c +++ b/components/esp_hw_support/esp_clk.c @@ -8,6 +8,7 @@ #include #include +#include "freertos/FreeRTOS.h" #include "esp_attr.h" #include "soc/rtc.h" #include "soc/soc_caps.h" @@ -34,6 +35,9 @@ #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/rtc.h" #include "esp32c2/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/rtc.h" +#include "esp32c6/rtc.h" #endif #define MHZ (1000000) @@ -46,7 +50,7 @@ extern uint32_t g_ticks_per_us_app; #endif #endif -static _lock_t s_esp_rtc_time_lock; +static portMUX_TYPE s_esp_rtc_time_lock = portMUX_INITIALIZER_UNLOCKED; // TODO: IDF-4239 static RTC_DATA_ATTR uint64_t s_esp_rtc_time_us = 0, s_rtc_last_ticks = 0; @@ -75,7 +79,7 @@ int IRAM_ATTR esp_clk_xtal_freq(void) return rtc_clk_xtal_freq_get() * MHZ; } -#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C2 +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 void IRAM_ATTR ets_update_cpu_frequency(uint32_t ticks_per_us) { /* Update scale factors used by esp_rom_delay_us */ @@ -94,7 +98,7 @@ uint64_t esp_rtc_get_time_us(void) //IDF-3901 return 0; #endif - _lock_acquire(&s_esp_rtc_time_lock); + portENTER_CRITICAL_SAFE(&s_esp_rtc_time_lock); const uint32_t cal = esp_clk_slowclk_cal_get(); const uint64_t rtc_this_ticks = rtc_time_get(); const uint64_t ticks = rtc_this_ticks - s_rtc_last_ticks; @@ -115,7 +119,7 @@ uint64_t esp_rtc_get_time_us(void) ((ticks_high * cal) << (32 - RTC_CLK_CAL_FRACT)); s_esp_rtc_time_us += delta_time_us; s_rtc_last_ticks = rtc_this_ticks; - _lock_release(&s_esp_rtc_time_lock); + portEXIT_CRITICAL_SAFE(&s_esp_rtc_time_lock); return s_esp_rtc_time_us; } @@ -143,3 +147,13 @@ uint64_t esp_clk_rtc_time(void) return 0; #endif } + +void esp_clk_private_lock(void) +{ + portENTER_CRITICAL(&s_esp_rtc_time_lock); +} + +void esp_clk_private_unlock(void) +{ + portEXIT_CRITICAL(&s_esp_rtc_time_lock); +} diff --git a/components/esp_hw_support/esp_memory_utils.c b/components/esp_hw_support/esp_memory_utils.c index 1c8917418d..cf12a11f6a 100644 --- a/components/esp_hw_support/esp_memory_utils.c +++ b/components/esp_hw_support/esp_memory_utils.c @@ -23,10 +23,7 @@ bool esp_ptr_dma_ext_capable(const void *p) return false; #endif //!SOC_PSRAM_DMA_CAPABLE #if CONFIG_SPIRAM - intptr_t vaddr_start = 0; - intptr_t vaddr_end = 0; - esp_psram_extram_get_mapped_range(&vaddr_start, &vaddr_end); - return (intptr_t)p >= vaddr_start && (intptr_t)p < vaddr_end; + return esp_psram_check_ptr_addr(p); #else return false; #endif //CONFIG_SPIRAM @@ -44,10 +41,7 @@ bool esp_ptr_byte_accessible(const void *p) r |= (ip >= SOC_RTC_DRAM_LOW && ip < SOC_RTC_DRAM_HIGH); #endif #if CONFIG_SPIRAM - intptr_t vaddr_start = 0; - intptr_t vaddr_end = 0; - esp_psram_extram_get_mapped_range(&vaddr_start, &vaddr_end); - r |= (ip >= vaddr_start && ip < vaddr_end); + r |= esp_psram_check_ptr_addr(p); #endif return r; } @@ -58,10 +52,7 @@ bool esp_ptr_external_ram(const void *p) return false; #endif //!SOC_SPIRAM_SUPPORTED #if CONFIG_SPIRAM - intptr_t vaddr_start = 0; - intptr_t vaddr_end = 0; - esp_psram_extram_get_mapped_range(&vaddr_start, &vaddr_end); - return (intptr_t)p >= vaddr_start && (intptr_t)p < vaddr_end; + return esp_psram_check_ptr_addr(p); #else return false; #endif //CONFIG_SPIRAM @@ -70,10 +61,7 @@ bool esp_ptr_external_ram(const void *p) #if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY bool esp_stack_ptr_in_extram(uint32_t sp) { - intptr_t vaddr_start = 0; - intptr_t vaddr_end = 0; - esp_psram_extram_get_mapped_range(&vaddr_start, &vaddr_end); - //Check if stack ptr is in between SOC_EXTRAM_DATA_LOW and SOC_EXTRAM_DATA_HIGH, and 16 byte aligned. - return !(sp < vaddr_start + 0x10 || sp > vaddr_end - 0x10 || ((sp & 0xF) != 0)); + //Check if stack ptr is on PSRAM, and 16 byte aligned. + return (esp_psram_check_ptr_addr((void *)sp) && ((sp & 0xF) == 0)); } #endif diff --git a/components/esp_hw_support/gdma.c b/components/esp_hw_support/gdma.c index cd2e6cf62c..6ffa28fc8b 100644 --- a/components/esp_hw_support/gdma.c +++ b/components/esp_hw_support/gdma.c @@ -764,7 +764,7 @@ static esp_err_t gdma_install_rx_interrupt(gdma_rx_channel_t *rx_chan) // pre-alloc a interrupt handle, with handler disabled int isr_flags = GDMA_INTR_ALLOC_FLAGS; #if SOC_GDMA_TX_RX_SHARE_INTERRUPT - isr_flags |= ESP_INTR_FLAG_SHARED; + isr_flags |= ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED; #endif intr_handle_t intr = NULL; ret = esp_intr_alloc_intrstatus(gdma_periph_signals.groups[group->group_id].pairs[pair->pair_id].rx_irq_id, isr_flags, @@ -791,7 +791,7 @@ static esp_err_t gdma_install_tx_interrupt(gdma_tx_channel_t *tx_chan) // pre-alloc a interrupt handle, with handler disabled int isr_flags = GDMA_INTR_ALLOC_FLAGS; #if SOC_GDMA_TX_RX_SHARE_INTERRUPT - isr_flags |= ESP_INTR_FLAG_SHARED; + isr_flags |= ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED; #endif intr_handle_t intr = NULL; ret = esp_intr_alloc_intrstatus(gdma_periph_signals.groups[group->group_id].pairs[pair->pair_id].tx_irq_id, isr_flags, diff --git a/components/esp_hw_support/include/esp_chip_info.h b/components/esp_hw_support/include/esp_chip_info.h index 8f92e226b1..227d55a0fa 100644 --- a/components/esp_hw_support/include/esp_chip_info.h +++ b/components/esp_hw_support/include/esp_chip_info.h @@ -26,6 +26,7 @@ typedef enum { CHIP_ESP32C3 = 5, //!< ESP32-C3 CHIP_ESP32H2 = 6, //!< ESP32-H2 CHIP_ESP32C2 = 12, //!< ESP32-C2 + CHIP_ESP32C6 = 13, //!< ESP32-C6 } esp_chip_model_t; /* Chip feature flags, used in esp_chip_info_t */ diff --git a/components/esp_hw_support/include/esp_fault.h b/components/esp_hw_support/include/esp_fault.h index 910ba59d06..19b0a9e0cf 100644 --- a/components/esp_hw_support/include/esp_fault.h +++ b/components/esp_hw_support/include/esp_fault.h @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ #include "sdkconfig.h" -#include "soc/rtc_cntl_reg.h" #include "esp_rom_sys.h" #pragma once @@ -70,9 +69,9 @@ extern "C" { */ #ifndef ESP_FAULT_ASSERT_DEBUG -#define _ESP_FAULT_RESET() do { \ - REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); \ - _ESP_FAULT_ILLEGAL_INSTRUCTION; \ +#define _ESP_FAULT_RESET() do { \ + esp_rom_software_reset_system(); \ + _ESP_FAULT_ILLEGAL_INSTRUCTION; \ } while(0) #else // ESP_FAULT_ASSERT_DEBUG diff --git a/components/esp_hw_support/include/esp_mac.h b/components/esp_hw_support/include/esp_mac.h index 6a7224a317..e4eb06cd09 100644 --- a/components/esp_hw_support/include/esp_mac.h +++ b/components/esp_hw_support/include/esp_mac.h @@ -41,6 +41,8 @@ typedef enum { #define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32H2_UNIVERSAL_MAC_ADDRESSES #elif CONFIG_IDF_TARGET_ESP32C2 #define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32C2_UNIVERSAL_MAC_ADDRESSES +#elif CONFIG_IDF_TARGET_ESP32C6 +#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32C6_UNIVERSAL_MAC_ADDRESSES #endif /** @endcond */ diff --git a/components/esp_hw_support/include/esp_memory_utils.h b/components/esp_hw_support/include/esp_memory_utils.h index e66e917b87..330fc114bf 100644 --- a/components/esp_hw_support/include/esp_memory_utils.h +++ b/components/esp_hw_support/include/esp_memory_utils.h @@ -69,7 +69,12 @@ inline static bool esp_ptr_in_diram_dram(const void *p) { */ __attribute__((always_inline)) inline static bool esp_ptr_in_diram_iram(const void *p) { +// TODO: IDF-5980 esp32c6 D/I RAM share the same address +#if SOC_DIRAM_IRAM_LOW == SOC_DIRAM_DRAM_LOW + return false; +#else return ((intptr_t)p >= SOC_DIRAM_IRAM_LOW && (intptr_t)p < SOC_DIRAM_IRAM_HIGH); +#endif } /** diff --git a/components/esp_hw_support/include/esp_private/esp_clk.h b/components/esp_hw_support/include/esp_private/esp_clk.h index 8462b032ee..01b2849f8a 100644 --- a/components/esp_hw_support/include/esp_private/esp_clk.h +++ b/components/esp_hw_support/include/esp_private/esp_clk.h @@ -82,6 +82,19 @@ int esp_clk_xtal_freq(void); */ uint64_t esp_clk_rtc_time(void); +/** + * @brief obtain internal critical section used esp_clk implementation. + * + * This is used by the esp_light_sleep_start() to avoid deadlocking when it + * calls esp_clk related API after stalling the other CPU. + */ +void esp_clk_private_lock(void); + +/** + * @brief counterpart of esp_clk_private_lock + */ +void esp_clk_private_unlock(void); + #ifdef __cplusplus } #endif diff --git a/components/esp_hw_support/include/esp_private/esp_sleep_internal.h b/components/esp_hw_support/include/esp_private/esp_sleep_internal.h index ee0b72953f..359c3f5f75 100644 --- a/components/esp_hw_support/include/esp_private/esp_sleep_internal.h +++ b/components/esp_hw_support/include/esp_private/esp_sleep_internal.h @@ -6,6 +6,7 @@ #pragma once #include +#include "sdkconfig.h" #ifdef __cplusplus extern "C" { @@ -20,6 +21,15 @@ extern "C" { */ void esp_sleep_enable_adc_tsens_monitor(bool enable); +// TODO: IDF-6051, IDF-6052 +#if !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C6 +/** + * @brief Isolate all digital IOs except those that are held during deep sleep + * + * Reduce digital IOs current leakage during deep sleep. + */ +void esp_sleep_isolate_digital_gpio(void); +#endif #ifdef __cplusplus } diff --git a/components/esp_hw_support/include/esp_sleep.h b/components/esp_hw_support/include/esp_sleep.h index 286ccc76de..3fd106cc67 100644 --- a/components/esp_hw_support/include/esp_sleep.h +++ b/components/esp_hw_support/include/esp_sleep.h @@ -75,7 +75,7 @@ typedef enum { ESP_SLEEP_WAKEUP_TIMER, //!< Wakeup caused by timer ESP_SLEEP_WAKEUP_TOUCHPAD, //!< Wakeup caused by touchpad ESP_SLEEP_WAKEUP_ULP, //!< Wakeup caused by ULP program - ESP_SLEEP_WAKEUP_GPIO, //!< Wakeup caused by GPIO (light sleep only) + ESP_SLEEP_WAKEUP_GPIO, //!< Wakeup caused by GPIO (light sleep only on ESP32, S2 and S3) ESP_SLEEP_WAKEUP_UART, //!< Wakeup caused by UART (light sleep only) ESP_SLEEP_WAKEUP_WIFI, //!< Wakeup caused by WIFI (light sleep only) ESP_SLEEP_WAKEUP_COCPU, //!< Wakeup caused by COCPU int @@ -107,10 +107,8 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source); #if SOC_ULP_SUPPORTED /** * @brief Enable wakeup by ULP coprocessor - * @note In revisions 0 and 1 of the ESP32, ULP wakeup source - * cannot be used when RTC_PERIPH power domain is forced - * to be powered on (ESP_PD_OPTION_ON) or when - * ext0 wakeup source is used. + * @note On ESP32, ULP wakeup source cannot be used when RTC_PERIPH power domain is forced, + * to be powered on (ESP_PD_OPTION_ON) or when ext0 wakeup source is used. * @return * - ESP_OK on success * - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT) is enabled. @@ -133,10 +131,8 @@ esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us); /** * @brief Enable wakeup by touch sensor * - * @note In revisions 0 and 1 of the ESP32, touch wakeup source - * can not be used when RTC_PERIPH power domain is forced - * to be powered on (ESP_PD_OPTION_ON) or when ext0 wakeup - * source is used. + * @note On ESP32, touch wakeup source can not be used when RTC_PERIPH power domain is forced + * to be powered on (ESP_PD_OPTION_ON) or when ext0 wakeup source is used. * * @note The FSM mode of the touch button should be configured * as the timer trigger mode. @@ -184,11 +180,13 @@ bool esp_sleep_is_valid_wakeup_gpio(gpio_num_t gpio_num); * configured in esp_deep_sleep_start/esp_light_sleep_start, * immediately before entering sleep mode. * - * @note In revisions 0 and 1 of the ESP32, ext0 wakeup source - * can not be used together with touch or ULP wakeup sources. + * @note ESP32: ext0 wakeup source can not be used together with touch or ULP wakeup sources. * - * @param gpio_num GPIO number used as wakeup source. Only GPIOs which are have RTC - * functionality can be used: 0,2,4,12-15,25-27,32-39. + * @param gpio_num GPIO number used as wakeup source. Only GPIOs with the RTC + * functionality can be used. For different SoCs, the related GPIOs are: + * - ESP32: 0, 2, 4, 12-15, 25-27, 32-39; + * - ESP32-S2: 0-21; + * - ESP32-S3: 0-21. * @param level input level which will trigger wakeup (0=low, 1=high) * @return * - ESP_OK on success @@ -218,8 +216,11 @@ esp_err_t esp_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level); * kept enabled using esp_sleep_pd_config function. * * @param mask bit mask of GPIO numbers which will cause wakeup. Only GPIOs - * which have RTC functionality can be used in this bit map: - * 0,2,4,12-15,25-27,32-39. + * which have RTC functionality can be used in this bit map. + * For different SoCs, the related GPIOs are: + * - ESP32: 0, 2, 4, 12-15, 25-27, 32-39; + * - ESP32-S2: 0-21; + * - ESP32-S3: 0-21. * @param mode select logic function used to determine wakeup condition: * - ESP_EXT1_WAKEUP_ALL_LOW: wake up when all selected GPIOs are low * - ESP_EXT1_WAKEUP_ANY_HIGH: wake up when any of the selected GPIOs is high @@ -270,8 +271,7 @@ esp_err_t esp_deep_sleep_enable_gpio_wakeup(uint64_t gpio_pin_mask, esp_deepslee * wakeup level, for each GPIO which is used for wakeup. * Then call this function to enable wakeup feature. * - * @note In revisions 0 and 1 of the ESP32, GPIO wakeup source - * can not be used together with touch or ULP wakeup sources. + * @note On ESP32, GPIO wakeup source can not be used together with touch or ULP wakeup sources. * * @return * - ESP_OK on success diff --git a/components/esp_hw_support/include/soc/esp32c6/esp_crypto_lock.h b/components/esp_hw_support/include/soc/esp32c6/esp_crypto_lock.h new file mode 100644 index 0000000000..67a08741b5 --- /dev/null +++ b/components/esp_hw_support/include/soc/esp32c6/esp_crypto_lock.h @@ -0,0 +1,68 @@ +/* + * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Acquire lock for HMAC cryptography peripheral + * + * Internally also locks the SHA peripheral, as the HMAC depends on the SHA peripheral + */ +void esp_crypto_hmac_lock_acquire(void); + +/** + * @brief Release lock for HMAC cryptography peripheral + * + * Internally also releases the SHA peripheral, as the HMAC depends on the SHA peripheral + */ +void esp_crypto_hmac_lock_release(void); + +/** + * @brief Acquire lock for DS cryptography peripheral + * + * Internally also locks the HMAC (which locks SHA), AES and MPI peripheral, as the DS depends on these peripherals + */ +void esp_crypto_ds_lock_acquire(void); + +/** + * @brief Release lock for DS cryptography peripheral + * + * Internally also releases the HMAC (which locks SHA), AES and MPI peripheral, as the DS depends on these peripherals + */ +void esp_crypto_ds_lock_release(void); + +/** + * @brief Acquire lock for the SHA and AES cryptography peripheral. + * + */ +void esp_crypto_sha_aes_lock_acquire(void); + +/** + * @brief Release lock for the SHA and AES cryptography peripheral. + * + */ +void esp_crypto_sha_aes_lock_release(void); + + +/** + * @brief Acquire lock for the mpi cryptography peripheral. + * + */ +void esp_crypto_mpi_lock_acquire(void); + +/** + * @brief Release lock for the mpi/rsa cryptography peripheral. + * + */ +void esp_crypto_mpi_lock_release(void); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hw_support/include/soc/esp32c6/esp_ds.h b/components/esp_hw_support/include/soc/esp32c6/esp_ds.h new file mode 100644 index 0000000000..6393edda6b --- /dev/null +++ b/components/esp_hw_support/include/soc/esp32c6/esp_ds.h @@ -0,0 +1,220 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_hmac.h" +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ESP32C6_ERR_HW_CRYPTO_DS_HMAC_FAIL ESP_ERR_HW_CRYPTO_BASE + 0x1 /*!< HMAC peripheral problem */ +#define ESP32C6_ERR_HW_CRYPTO_DS_INVALID_KEY ESP_ERR_HW_CRYPTO_BASE + 0x2 /*!< given HMAC key isn't correct, + HMAC peripheral problem */ +#define ESP32C6_ERR_HW_CRYPTO_DS_INVALID_DIGEST ESP_ERR_HW_CRYPTO_BASE + 0x4 /*!< message digest check failed, + result is invalid */ +#define ESP32C6_ERR_HW_CRYPTO_DS_INVALID_PADDING ESP_ERR_HW_CRYPTO_BASE + 0x5 /*!< padding check failed, but result + is produced anyway and can be read*/ + +#define ESP_DS_IV_BIT_LEN 128 +#define ESP_DS_IV_LEN (ESP_DS_IV_BIT_LEN / 8) +#define ESP_DS_SIGNATURE_MAX_BIT_LEN 3072 +#define ESP_DS_SIGNATURE_MD_BIT_LEN 256 +#define ESP_DS_SIGNATURE_M_PRIME_BIT_LEN 32 +#define ESP_DS_SIGNATURE_L_BIT_LEN 32 +#define ESP_DS_SIGNATURE_PADDING_BIT_LEN 64 + +/* Length of parameter 'C' stored in flash, in bytes + - Operands Y, M and r_bar; each 3072 bits + - Operand MD (message digest); 256 bits + - Operands M' and L; each 32 bits + - Operand beta (padding value; 64 bits +*/ +#define ESP_DS_C_LEN (((ESP_DS_SIGNATURE_MAX_BIT_LEN * 3 \ + + ESP_DS_SIGNATURE_MD_BIT_LEN \ + + ESP_DS_SIGNATURE_M_PRIME_BIT_LEN \ + + ESP_DS_SIGNATURE_L_BIT_LEN \ + + ESP_DS_SIGNATURE_PADDING_BIT_LEN) / 8)) + +typedef struct esp_ds_context esp_ds_context_t; + +typedef enum { + ESP_DS_RSA_1024 = (1024 / 32) - 1, + ESP_DS_RSA_2048 = (2048 / 32) - 1, + ESP_DS_RSA_3072 = (3072 / 32) - 1 +} esp_digital_signature_length_t; + +/** + * Encrypted private key data. Recommended to store in flash in this format. + * + * @note This struct has to match to one from the ROM code! This documentation is mostly taken from there. + */ +typedef struct esp_digital_signature_data { + /** + * RSA LENGTH register parameters + * (number of words in RSA key & operands, minus one). + * + * Max value 127 (for RSA 3072). + * + * This value must match the length field encrypted and stored in 'c', + * or invalid results will be returned. (The DS peripheral will + * always use the value in 'c', not this value, so an attacker can't + * alter the DS peripheral results this way, it will just truncate or + * extend the message and the resulting signature in software.) + * + * @note In IDF, the enum type length is the same as of type unsigned, so they can be used interchangably. + * See the ROM code for the original declaration of struct \c ets_ds_data_t. + */ + esp_digital_signature_length_t rsa_length; + + /** + * IV value used to encrypt 'c' + */ + uint32_t iv[ESP_DS_IV_BIT_LEN / 32]; + + /** + * Encrypted Digital Signature parameters. Result of AES-CBC encryption + * of plaintext values. Includes an encrypted message digest. + */ + uint8_t c[ESP_DS_C_LEN]; +} esp_ds_data_t; + +/** + * Plaintext parameters used by Digital Signature. + * + * This is only used for encrypting the RSA parameters by calling esp_ds_encrypt_params(). + * Afterwards, the result can be stored in flash or in other persistent memory. + * The encryption is a prerequisite step before any signature operation can be done. + */ +typedef struct { + uint32_t Y[ESP_DS_SIGNATURE_MAX_BIT_LEN / 32]; //!< RSA exponent + uint32_t M[ESP_DS_SIGNATURE_MAX_BIT_LEN / 32]; //!< RSA modulus + uint32_t Rb[ESP_DS_SIGNATURE_MAX_BIT_LEN / 32]; //!< RSA r inverse operand + uint32_t M_prime; //!< RSA M prime operand + uint32_t length; //!< RSA length in words (32 bit) +} esp_ds_p_data_t; + +/** + * @brief Sign the message with a hardware key from specific key slot. + * The function calculates a plain RSA signature with help of the DS peripheral. + * The RSA encryption operation is as follows: + * Z = XY mod M where, + * Z is the signature, X is the input message, + * Y and M are the RSA private key parameters. + * + * This function is a wrapper around \c esp_ds_finish_sign() and \c esp_ds_start_sign(), so do not use them + * in parallel. + * It blocks until the signing is finished and then returns the signature. + * + * @note This function locks the HMAC, SHA, AES and RSA components during its entire execution time. + * + * @param message the message to be signed; its length should be (data->rsa_length + 1)*4 bytes + * @param data the encrypted signing key data (AES encrypted RSA key + IV) + * @param key_id the HMAC key ID determining the HMAC key of the HMAC which will be used to decrypt the + * signing key data + * @param signature the destination of the signature, should be (data->rsa_length + 1)*4 bytes long + * + * @return + * - ESP_OK if successful, the signature was written to the parameter \c signature. + * - ESP_ERR_INVALID_ARG if one of the parameters is NULL or data->rsa_length is too long or 0 + * - ESP_ERR_HW_CRYPTO_DS_HMAC_FAIL if there was an HMAC failure during retrieval of the decryption key + * - ESP_ERR_NO_MEM if there hasn't been enough memory to allocate the context object + * - ESP_ERR_HW_CRYPTO_DS_INVALID_KEY if there's a problem with passing the HMAC key to the DS component + * - ESP_ERR_HW_CRYPTO_DS_INVALID_DIGEST if the message digest didn't match; the signature is invalid. + * - ESP_ERR_HW_CRYPTO_DS_INVALID_PADDING if the message padding is incorrect, the signature can be read though + * since the message digest matches. + */ +esp_err_t esp_ds_sign(const void *message, + const esp_ds_data_t *data, + hmac_key_id_t key_id, + void *signature); + +/** + * @brief Start the signing process. + * + * This function yields a context object which needs to be passed to \c esp_ds_finish_sign() to finish the signing + * process. + * The function calculates a plain RSA signature with help of the DS peripheral. + * The RSA encryption operation is as follows: + * Z = XY mod M where, + * Z is the signature, X is the input message, + * Y and M are the RSA private key parameters. + * + * @note This function locks the HMAC, SHA, AES and RSA components, so the user has to ensure to call + * \c esp_ds_finish_sign() in a timely manner. + * + * @param message the message to be signed; its length should be (data->rsa_length + 1)*4 bytes + * @param data the encrypted signing key data (AES encrypted RSA key + IV) + * @param key_id the HMAC key ID determining the HMAC key of the HMAC which will be used to decrypt the + * signing key data + * @param esp_ds_ctx the context object which is needed for finishing the signing process later + * + * @return + * - ESP_OK if successful, the ds operation was started now and has to be finished with \c esp_ds_finish_sign() + * - ESP_ERR_INVALID_ARG if one of the parameters is NULL or data->rsa_length is too long or 0 + * - ESP_ERR_HW_CRYPTO_DS_HMAC_FAIL if there was an HMAC failure during retrieval of the decryption key + * - ESP_ERR_NO_MEM if there hasn't been enough memory to allocate the context object + * - ESP_ERR_HW_CRYPTO_DS_INVALID_KEY if there's a problem with passing the HMAC key to the DS component + */ +esp_err_t esp_ds_start_sign(const void *message, + const esp_ds_data_t *data, + hmac_key_id_t key_id, + esp_ds_context_t **esp_ds_ctx); + +/** + * Return true if the DS peripheral is busy, otherwise false. + * + * @note Only valid if \c esp_ds_start_sign() was called before. + */ +bool esp_ds_is_busy(void); + +/** + * @brief Finish the signing process. + * + * @param signature the destination of the signature, should be (data->rsa_length + 1)*4 bytes long + * @param esp_ds_ctx the context object retreived by \c esp_ds_start_sign() + * + * @return + * - ESP_OK if successful, the ds operation has been finished and the result is written to signature. + * - ESP_ERR_INVALID_ARG if one of the parameters is NULL + * - ESP_ERR_HW_CRYPTO_DS_INVALID_DIGEST if the message digest didn't match; the signature is invalid. + * This means that the encrypted RSA key parameters are invalid, indicating that they may have been tampered + * with or indicating a flash error, etc. + * - ESP_ERR_HW_CRYPTO_DS_INVALID_PADDING if the message padding is incorrect, the signature can be read though + * since the message digest matches (see TRM for more details). + */ +esp_err_t esp_ds_finish_sign(void *signature, esp_ds_context_t *esp_ds_ctx); + +/** + * @brief Encrypt the private key parameters. + * + * The encryption is a prerequisite step before any signature operation can be done. + * It is not strictly necessary to use this encryption function, the encryption could also happen on an external + * device. + * + * @param data Output buffer to store encrypted data, suitable for later use generating signatures. + * The allocated memory must be in internal memory and word aligned since it's filled by DMA. Both is asserted + * at run time. + * @param iv Pointer to 16 byte IV buffer, will be copied into 'data'. Should be randomly generated bytes each time. + * @param p_data Pointer to input plaintext key data. The expectation is this data will be deleted after this process + * is done and 'data' is stored. + * @param key Pointer to 32 bytes of key data. Type determined by key_type parameter. The expectation is the + * corresponding HMAC key will be stored to efuse and then permanently erased. + * + * @return + * - ESP_OK if successful, the ds operation has been finished and the result is written to signature. + * - ESP_ERR_INVALID_ARG if one of the parameters is NULL or p_data->rsa_length is too long + */ +esp_err_t esp_ds_encrypt_params(esp_ds_data_t *data, + const void *iv, + const esp_ds_p_data_t *p_data, + const void *key); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hw_support/include/soc/esp32c6/esp_hmac.h b/components/esp_hw_support/include/soc/esp32c6/esp_hmac.h new file mode 100644 index 0000000000..635834d594 --- /dev/null +++ b/components/esp_hw_support/include/soc/esp32c6/esp_hmac.h @@ -0,0 +1,92 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ESP_HMAC_H_ +#define _ESP_HMAC_H_ + +#include +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * The possible efuse keys for the HMAC peripheral + */ +typedef enum { + HMAC_KEY0 = 0, + HMAC_KEY1, + HMAC_KEY2, + HMAC_KEY3, + HMAC_KEY4, + HMAC_KEY5, + HMAC_KEY_MAX +} hmac_key_id_t; + +/** + * @brief + * Calculate the HMAC of a given message. + * + * Calculate the HMAC \c hmac of a given message \c message with length \c message_len. + * SHA256 is used for the calculation (fixed on ESP32S2). + * + * @note Uses the HMAC peripheral in "upstream" mode. + * + * @param key_id Determines which of the 6 key blocks in the efuses should be used for the HMAC calcuation. + * The corresponding purpose field of the key block in the efuse must be set to the HMAC upstream purpose value. + * @param message the message for which to calculate the HMAC + * @param message_len message length + * return ESP_ERR_INVALID_STATE if unsuccessful + * @param [out] hmac the hmac result; the buffer behind the provided pointer must be a writeable buffer of 32 bytes + * + * @return + * * ESP_OK, if the calculation was successful, + * * ESP_ERR_INVALID_ARG if message or hmac is a nullptr or if key_id out of range + * * ESP_FAIL, if the hmac calculation failed + */ +esp_err_t esp_hmac_calculate(hmac_key_id_t key_id, + const void *message, + size_t message_len, + uint8_t *hmac); + +/** + * @brief Use HMAC peripheral in Downstream mode to re-enable the JTAG, if it is not permanently disabled by HW. + * In downstream mode, HMAC calculations performed by peripheral are used internally and not provided back to user. + * + * @param key_id Determines which of the 6 key blocks in the efuses should be used for the HMAC calculation. + * The corresponding purpose field of the key block in the efuse must be set to HMAC downstream purpose. + * + * @param token Pre calculated HMAC value of the 32-byte 0x00 using SHA-256 and the known private HMAC key. The key is already + * programmed to a eFuse key block. The key block number is provided as the first parameter to this function. + * + * @return + * * ESP_OK, if the key_purpose of the key_id matches to HMAC downstread mode, + * The API returns success even if calculated HMAC does not match with the provided token. + * However, The JTAG will be re-enabled only if the calculated HMAC value matches with provided token, + * otherwise JTAG will remain disabled. + * * ESP_FAIL, if the key_purpose of the key_id is not set to HMAC downstream purpose + * or JTAG is permanently disabled by EFUSE_HARD_DIS_JTAG eFuse parameter. + * * ESP_ERR_INVALID_ARG, invalid input arguments + * + * @note Return value of the API does not indicate the JTAG status. + */ +esp_err_t esp_hmac_jtag_enable(hmac_key_id_t key_id, const uint8_t *token); + +/** + * @brief Disable the JTAG which might be enabled using the HMAC downstream mode. This function just clears the result generated + * by calling esp_hmac_jtag_enable() API. + * + * @return + * * ESP_OK return ESP_OK after writing the HMAC_SET_INVALIDATE_JTAG_REG with value 1. + */ +esp_err_t esp_hmac_jtag_disable(void); + +#ifdef __cplusplus +} +#endif + +#endif // _ESP_HMAC_H_ diff --git a/components/esp_hw_support/include/soc/esp32c6/rtc.h b/components/esp_hw_support/include/soc/esp32c6/rtc.h new file mode 100644 index 0000000000..dec61ee9cf --- /dev/null +++ b/components/esp_hw_support/include/soc/esp32c6/rtc.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file esp32c6/rtc.h + * + * This file contains declarations of rtc related functions. + */ + +/** + * @brief Get current value of RTC counter in microseconds + * + * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute + * + * @return current value of RTC counter in microseconds + */ +uint64_t esp_rtc_get_time_us(void); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hw_support/include/soc/esp32c6/soc_memprot_types.h b/components/esp_hw_support/include/soc/esp32c6/soc_memprot_types.h new file mode 100644 index 0000000000..c45dc31dc9 --- /dev/null +++ b/components/esp_hw_support/include/soc/esp32c6/soc_memprot_types.h @@ -0,0 +1,175 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +////////////////////////////////////////////////////////// +// ESP32-C6 PMS memory protection types +// + +#pragma once + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Memory types recognized by PMS + */ +typedef enum { + MEMPROT_TYPE_NONE = 0x00000000, + MEMPROT_TYPE_IRAM0_SRAM = 0x00000001, + MEMPROT_TYPE_DRAM0_SRAM = 0x00000002, + MEMPROT_TYPE_IRAM0_RTCFAST = 0x00000004, + MEMPROT_TYPE_ALL = 0x7FFFFFFF, + MEMPROT_TYPE_INVALID = 0x80000000, + MEMPROT_TYPE_IRAM0_ANY = MEMPROT_TYPE_IRAM0_SRAM | MEMPROT_TYPE_IRAM0_RTCFAST +} esp_mprot_mem_t; + +/** + * @brief Splitting address (line) type + */ +typedef enum { + MEMPROT_SPLIT_ADDR_NONE = 0x00000000, + MEMPROT_SPLIT_ADDR_IRAM0_DRAM0 = 0x00000001, + MEMPROT_SPLIT_ADDR_IRAM0_LINE_0 = 0x00000002, + MEMPROT_SPLIT_ADDR_IRAM0_LINE_1 = 0x00000004, + MEMPROT_SPLIT_ADDR_DRAM0_DMA_LINE_0 = 0x00000008, + MEMPROT_SPLIT_ADDR_DRAM0_DMA_LINE_1 = 0x00000010, + MEMPROT_SPLIT_ADDR_ALL = 0x7FFFFFFF, + MEMPROT_SPLIT_ADDR_INVALID = 0x80000000, + MEMPROT_SPLIT_ADDR_MAIN = MEMPROT_SPLIT_ADDR_IRAM0_DRAM0 +} esp_mprot_split_addr_t; + +/** + * @brief PMS area type (memory space between adjacent splitting addresses or above/below the main splt.address) + */ +typedef enum { + MEMPROT_PMS_AREA_NONE = 0x00000000, + MEMPROT_PMS_AREA_IRAM0_0 = 0x00000001, + MEMPROT_PMS_AREA_IRAM0_1 = 0x00000002, + MEMPROT_PMS_AREA_IRAM0_2 = 0x00000004, + MEMPROT_PMS_AREA_IRAM0_3 = 0x00000008, + MEMPROT_PMS_AREA_DRAM0_0 = 0x00000010, + MEMPROT_PMS_AREA_DRAM0_1 = 0x00000020, + MEMPROT_PMS_AREA_DRAM0_2 = 0x00000040, + MEMPROT_PMS_AREA_DRAM0_3 = 0x00000080, + MEMPROT_PMS_AREA_IRAM0_RTCFAST_LO = 0x00000100, + MEMPROT_PMS_AREA_IRAM0_RTCFAST_HI = 0x00000200, + MEMPROT_PMS_AREA_ALL = 0x7FFFFFFF, + MEMPROT_PMS_AREA_INVALID = 0x80000000 +} esp_mprot_pms_area_t; + +/** +* @brief Memory protection configuration +*/ +typedef struct { + bool invoke_panic_handler; /*!< Register PMS violation interrupt for panic-handling */ + bool lock_feature; /*!< Lock all PMS settings */ + void *split_addr; /*!< Main I/D splitting address */ + uint32_t mem_type_mask; /*!< Memory types required to protect. See esp_mprot_mem_t enum */ +} esp_memp_config_t; + +#define ESP_MEMPROT_DEFAULT_CONFIG() { \ + .invoke_panic_handler = true, \ + .lock_feature = true, \ + .split_addr = NULL, \ + .mem_type_mask = MEMPROT_TYPE_ALL \ +} + +/** + * @brief Converts Memory protection type to string + * + * @param mem_type Memory protection type + */ +static inline const char *esp_mprot_mem_type_to_str(const esp_mprot_mem_t mem_type) +{ + switch (mem_type) { + case MEMPROT_TYPE_NONE: + return "NONE"; + case MEMPROT_TYPE_IRAM0_SRAM: + return "IRAM0_SRAM"; + case MEMPROT_TYPE_DRAM0_SRAM: + return "DRAM0_SRAM"; + case MEMPROT_TYPE_IRAM0_RTCFAST: + return "IRAM0_RTCFAST"; + case MEMPROT_TYPE_IRAM0_ANY: + return "IRAM0_ANY"; + case MEMPROT_TYPE_ALL: + return "ALL"; + default: + return "INVALID"; + } +} + +/** + * @brief Converts Splitting address type to string + * + * @param line_type Split line type + */ +static inline const char *esp_mprot_split_addr_to_str(const esp_mprot_split_addr_t line_type) +{ + switch (line_type) { + case MEMPROT_SPLIT_ADDR_NONE: + return "SPLIT_ADDR_NONE"; + case MEMPROT_SPLIT_ADDR_IRAM0_DRAM0: + return "SPLIT_ADDR_IRAM0_DRAM0"; + case MEMPROT_SPLIT_ADDR_IRAM0_LINE_0: + return "SPLIT_ADDR_IRAM0_LINE_0"; + case MEMPROT_SPLIT_ADDR_IRAM0_LINE_1: + return "SPLIT_ADDR_IRAM0_LINE_1"; + case MEMPROT_SPLIT_ADDR_DRAM0_DMA_LINE_0: + return "SPLIT_ADDR_DRAM0_DMA_LINE_0"; + case MEMPROT_SPLIT_ADDR_DRAM0_DMA_LINE_1: + return "SPLIT_ADDR_DRAM0_DMA_LINE_1"; + case MEMPROT_SPLIT_ADDR_ALL: + return "SPLIT_ADDR_ALL"; + default: + return "SPLIT_ADDR_INVALID"; + } +} + +/** + * @brief Converts PMS Area type to string + * + * @param area_type PMS Area type + */ +static inline const char *esp_mprot_pms_area_to_str(const esp_mprot_pms_area_t area_type) +{ + switch (area_type) { + case MEMPROT_PMS_AREA_NONE: + return "PMS_AREA_NONE"; + case MEMPROT_PMS_AREA_IRAM0_0: + return "PMS_AREA_IRAM0_0"; + case MEMPROT_PMS_AREA_IRAM0_1: + return "PMS_AREA_IRAM0_1"; + case MEMPROT_PMS_AREA_IRAM0_2: + return "PMS_AREA_IRAM0_2"; + case MEMPROT_PMS_AREA_IRAM0_3: + return "PMS_AREA_IRAM0_3"; + case MEMPROT_PMS_AREA_DRAM0_0: + return "PMS_AREA_DRAM0_0"; + case MEMPROT_PMS_AREA_DRAM0_1: + return "PMS_AREA_DRAM0_1"; + case MEMPROT_PMS_AREA_DRAM0_2: + return "PMS_AREA_DRAM0_2"; + case MEMPROT_PMS_AREA_DRAM0_3: + return "PMS_AREA_DRAM0_3"; + case MEMPROT_PMS_AREA_IRAM0_RTCFAST_LO: + return "PMS_AREA_IRAM0_RTCFAST_LO"; + case MEMPROT_PMS_AREA_IRAM0_RTCFAST_HI: + return "PMS_AREA_IRAM0_RTCFAST_HI"; + case MEMPROT_PMS_AREA_ALL: + return "PMS_AREA_ALL"; + default: + return "PMS_AREA_INVALID"; + } +} + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hw_support/intr_alloc.c b/components/esp_hw_support/intr_alloc.c index e97adc0953..314fe9db7d 100644 --- a/components/esp_hw_support/intr_alloc.c +++ b/components/esp_hw_support/intr_alloc.c @@ -801,6 +801,7 @@ esp_err_t IRAM_ATTR esp_intr_enable(intr_handle_t handle) } else { //Re-enable using cpu int ena reg if (handle->vector_desc->cpu != esp_cpu_get_core_id()) { + portEXIT_CRITICAL_SAFE(&spinlock); return ESP_ERR_INVALID_ARG; //Can only enable these ints on this cpu } ESP_INTR_ENABLE(handle->vector_desc->intno); diff --git a/components/esp_hw_support/linker.lf b/components/esp_hw_support/linker.lf index c63173bf35..005ecf9198 100644 --- a/components/esp_hw_support/linker.lf +++ b/components/esp_hw_support/linker.lf @@ -13,9 +13,10 @@ entries: cpu: esp_cpu_compare_and_set (noflash) esp_memory_utils (noflash) rtc_clk (noflash) - rtc_init:rtc_vddsdio_set_config (noflash) - rtc_pm (noflash_text) - rtc_sleep (noflash_text) + if IDF_TARGET_ESP32C6 = n: # TODO: IDF-5645 + rtc_init:rtc_vddsdio_set_config (noflash) + rtc_pm (noflash_text) + rtc_sleep (noflash_text) rtc_time (noflash_text) if IDF_TARGET_ESP32 = y || IDF_TARGET_ESP32S2 = y: rtc_wdt (noflash_text) diff --git a/components/esp_hw_support/mac_addr.c b/components/esp_hw_support/mac_addr.c index 803e1bdfaf..0278df30cb 100644 --- a/components/esp_hw_support/mac_addr.c +++ b/components/esp_hw_support/mac_addr.c @@ -87,7 +87,12 @@ esp_err_t esp_efuse_mac_get_custom(uint8_t *mac) uint8_t version; esp_efuse_read_field_blob(ESP_EFUSE_MAC_CUSTOM_VER, &version, 8); if (version != 1) { - ESP_LOGE(TAG, "Base MAC address from BLK3 of EFUSE version error, version = %d", version); + // version 0 means has not been setup + if (version == 0) { + ESP_LOGD(TAG, "No base MAC address in eFuse (version=0)"); + } else if (version != 1) { + ESP_LOGE(TAG, "Base MAC address version error, version = %d", version); + } return ESP_ERR_INVALID_VERSION; } diff --git a/components/esp_hw_support/port/esp32/rtc_time.c b/components/esp_hw_support/port/esp32/rtc_time.c index 96d64a6d32..a92b88041f 100644 --- a/components/esp_hw_support/port/esp32/rtc_time.c +++ b/components/esp_hw_support/port/esp32/rtc_time.c @@ -115,10 +115,22 @@ uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) return ratio; } +static inline bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles) +{ + uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768 + uint64_t delta = expected_xtal_cycles / 2000; // 5/10000 + return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta)); +} + uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); + + if ((cal_clk == RTC_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid(xtal_freq, slowclk_cycles, xtal_cycles)) { + return 0; + } + uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles; uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider; uint32_t period = (uint32_t)(period_64 & UINT32_MAX); diff --git a/components/esp_hw_support/port/esp32c2/rtc_init.c b/components/esp_hw_support/port/esp32c2/rtc_init.c index a3740c788e..5c9124d132 100644 --- a/components/esp_hw_support/port/esp32c2/rtc_init.c +++ b/components/esp_hw_support/port/esp32c2/rtc_init.c @@ -165,7 +165,7 @@ static void calibrate_ocode(void) soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX; if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { - cal_clk = RTC_CAL_EXT_CLK; + cal_clk = RTC_CAL_EXT_32K; } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { cal_clk = RTC_CAL_8MD256; } diff --git a/components/esp_hw_support/port/esp32c2/rtc_time.c b/components/esp_hw_support/port/esp32c2/rtc_time.c index 600f0d16cb..e634eaaf2d 100644 --- a/components/esp_hw_support/port/esp32c2/rtc_time.c +++ b/components/esp_hw_support/port/esp32c2/rtc_time.c @@ -40,14 +40,14 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) if (cal_clk == RTC_CAL_RTC_MUX) { soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { - cal_clk = RTC_CAL_EXT_CLK; + cal_clk = RTC_CAL_EXT_32K; } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { cal_clk = RTC_CAL_8MD256; } } /* Enable requested clock (150k clock is always on) */ bool dig_ext_clk_enabled = clk_ll_xtal32k_digi_is_enabled(); - if (cal_clk == RTC_CAL_EXT_CLK && !dig_ext_clk_enabled) { + if (cal_clk == RTC_CAL_EXT_32K && !dig_ext_clk_enabled) { clk_ll_xtal32k_digi_enable(); } @@ -57,23 +57,28 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) rtc_clk_8m_enable(true, true); clk_ll_rc_fast_d256_digi_enable(); } - /* Prepare calibration */ - REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk); /* There may be another calibration process already running during we call this function, * so we should wait the last process is done. */ - if (!GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) { - if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) { - while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)); - } + if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) { + /** + * Set a small timeout threshold to accelerate the generation of timeout. + * The internal circuit will be reset when the timeout occurs and will not affect the next calibration. + */ + REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, 1); + while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY) + && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)); } + + /* Prepare calibration */ + REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk); CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING); REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles); /* Figure out how long to wait for calibration to finish */ /* Set timeout reg and expect time delay*/ uint32_t expected_freq; - if (cal_clk == RTC_CAL_EXT_CLK) { + if (cal_clk == RTC_CAL_EXT_32K) { REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles)); expected_freq = SOC_CLK_OSC_SLOW_FREQ_APPROX; } else if (cal_clk == RTC_CAL_8MD256) { @@ -104,7 +109,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); /* if dig_ext_clk was originally off and enabled due to calibration, then set back to off state */ - if (cal_clk == RTC_CAL_EXT_CLK && !dig_ext_clk_enabled) { + if (cal_clk == RTC_CAL_EXT_32K && !dig_ext_clk_enabled) { clk_ll_xtal32k_digi_disable(); } @@ -124,10 +129,22 @@ uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) return ratio; } +static inline bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles) +{ + uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768 + uint64_t delta = expected_xtal_cycles / 2000; // 5/10000 + return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta)); +} + uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); + + if ((cal_clk == RTC_CAL_EXT_32K) && !rtc_clk_cal_32k_valid(xtal_freq, slowclk_cycles, xtal_cycles)) { + return 0; + } + uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles; uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider; uint32_t period = (uint32_t)(period_64 & UINT32_MAX); diff --git a/components/esp_hw_support/port/esp32c3/rtc_init.c b/components/esp_hw_support/port/esp32c3/rtc_init.c index 1ee73d879c..6884aff4d1 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_init.c +++ b/components/esp_hw_support/port/esp32c3/rtc_init.c @@ -321,8 +321,8 @@ static void set_rtc_dig_dbias() if (chip_version >= 3) { dig_dbias = get_dig_dbias_by_efuse(chip_version); if (dig_dbias != 0) { - if (dig_dbias + 4 > 28) { - dig_dbias = 28; + if (dig_dbias + 4 > 31) { + dig_dbias = 31; } else { dig_dbias += 4; } diff --git a/components/esp_hw_support/port/esp32c3/rtc_time.c b/components/esp_hw_support/port/esp32c3/rtc_time.c index 8e9d9e7872..beaa4965e1 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_time.c +++ b/components/esp_hw_support/port/esp32c3/rtc_time.c @@ -133,10 +133,21 @@ uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) return ratio; } +static bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles) +{ + uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768 + uint64_t delta = expected_xtal_cycles / 2000; // 5/10000 + return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta)); +} + uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); + + if ((cal_clk == RTC_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid(xtal_freq, slowclk_cycles, xtal_cycles)) + return 0; + uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles; uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider; uint32_t period = (uint32_t)(period_64 & UINT32_MAX); diff --git a/components/esp_hw_support/port/esp32c6/CMakeLists.txt b/components/esp_hw_support/port/esp32c6/CMakeLists.txt new file mode 100644 index 0000000000..95caea4b5e --- /dev/null +++ b/components/esp_hw_support/port/esp32c6/CMakeLists.txt @@ -0,0 +1,25 @@ +set(srcs "rtc_clk_init.c" + "rtc_clk.c" + # "rtc_init.c" // TODO: IDF-5645 + # "rtc_pm.c" // TODO: IDF-5645 + # "rtc_sleep.c" // TODO: IDF-5645 + "rtc_time.c" + "chip_info.c" + ) + +if(NOT BOOTLOADER_BUILD) + # list(APPEND srcs "esp_hmac.c" // TODO: IDF-5355 + # "esp_crypto_lock.c" + # "esp_ds.c") // TODO: IDF-5360 + + if(CONFIG_ESP_SYSTEM_MEMPROT_FEATURE) + list(APPEND srcs "esp_memprot.c" "../esp_memprot_conv.c") + endif() + +endif() + +add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}") + +target_sources(${COMPONENT_LIB} PRIVATE "${srcs}") +target_include_directories(${COMPONENT_LIB} PUBLIC . private_include) +target_include_directories(${COMPONENT_LIB} PRIVATE ../hal) diff --git a/components/esp_hw_support/port/esp32c6/Kconfig.hw_support b/components/esp_hw_support/port/esp32c6/Kconfig.hw_support new file mode 100644 index 0000000000..a47942369f --- /dev/null +++ b/components/esp_hw_support/port/esp32c6/Kconfig.hw_support @@ -0,0 +1,15 @@ +choice ESP32C6_REV_MIN + prompt "Minimum Supported ESP32-C6 Revision" + default ESP32C6_REV_MIN_0 + help + Minimum revision that ESP-IDF would support. + + Only supporting higher chip revisions can reduce binary size. + + config ESP32C6_REV_MIN_0 + bool "Rev 0" +endchoice + +config ESP32C6_REV_MIN + int + default 0 if ESP32C6_REV_MIN_0 diff --git a/components/esp_hw_support/port/esp32c6/Kconfig.mac b/components/esp_hw_support/port/esp32c6/Kconfig.mac new file mode 100644 index 0000000000..2556598e5f --- /dev/null +++ b/components/esp_hw_support/port/esp32c6/Kconfig.mac @@ -0,0 +1,43 @@ +choice ESP32C6_UNIVERSAL_MAC_ADDRESSES + bool "Number of universally administered (by IEEE) MAC address" + default ESP32C6_UNIVERSAL_MAC_ADDRESSES_FOUR + help + Configure the number of universally administered (by IEEE) MAC addresses. + + During initialization, MAC addresses for each network interface are generated or derived from a + single base MAC address. + + If the number of universal MAC addresses is four, all four interfaces (WiFi station, WiFi softap, + Bluetooth and Ethernet) receive a universally administered MAC address. These are generated + sequentially by adding 0, 1, 2 and 3 (respectively) to the final octet of the base MAC address. + + If the number of universal MAC addresses is two, only two interfaces (WiFi station and Bluetooth) + receive a universally administered MAC address. These are generated sequentially by adding 0 + and 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethernet) + receive local MAC addresses. These are derived from the universal WiFi station and Bluetooth MAC + addresses, respectively. + + When using the default (Espressif-assigned) base MAC address, either setting can be used. When using + a custom universal MAC address range, the correct setting will depend on the allocation of MAC + addresses in this range (either 2 or 4 per device.) + + Note that ESP32-C6 has no integrated Ethernet MAC. Although it's possible to use the esp_read_mac() + API to return a MAC for Ethernet, this can only be used with an external MAC peripheral. + + config ESP32C6_UNIVERSAL_MAC_ADDRESSES_TWO + bool "Two" + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_BT + + config ESP32C6_UNIVERSAL_MAC_ADDRESSES_FOUR + bool "Four" + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_WIFI_AP + select ESP_MAC_ADDR_UNIVERSE_BT + select ESP_MAC_ADDR_UNIVERSE_ETH +endchoice + +config ESP32C6_UNIVERSAL_MAC_ADDRESSES + int + default 2 if ESP32C6_UNIVERSAL_MAC_ADDRESSES_TWO + default 4 if ESP32C6_UNIVERSAL_MAC_ADDRESSES_FOUR diff --git a/components/esp_hw_support/port/esp32c6/Kconfig.rtc b/components/esp_hw_support/port/esp32c6/Kconfig.rtc new file mode 100644 index 0000000000..4dcb829249 --- /dev/null +++ b/components/esp_hw_support/port/esp32c6/Kconfig.rtc @@ -0,0 +1,40 @@ +choice RTC_CLK_SRC + # TODO: IDF-5346 + prompt "RTC clock source" + default RTC_CLK_SRC_INT_RC + help + Choose which clock is used as RTC clock source. + + config RTC_CLK_SRC_INT_RC + bool "Internal 136kHz RC oscillator" + config RTC_CLK_SRC_EXT_CRYS + bool "External 32kHz crystal" + select ESP_SYSTEM_RTC_EXT_XTAL + config RTC_CLK_SRC_EXT_OSC + bool "External 32kHz oscillator at 32K_XP pin" + select ESP_SYSTEM_RTC_EXT_OSC + config RTC_CLK_SRC_INT_8MD256 + bool "Internal 17.5MHz oscillator, divided by 256" +endchoice + +config RTC_CLK_CAL_CYCLES + int "Number of cycles for RTC_SLOW_CLK calibration" + default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 + default 1024 if RTC_CLK_SRC_INT_RC + range 0 27000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 + range 0 32766 if RTC_CLK_SRC_INT_RC + help + When the startup code initializes RTC_SLOW_CLK, it can perform + calibration by comparing the RTC_SLOW_CLK frequency with main XTAL + frequency. This option sets the number of RTC_SLOW_CLK cycles measured + by the calibration routine. Higher numbers increase calibration + precision, which may be important for applications which spend a lot of + time in deep sleep. Lower numbers reduce startup time. + + When this option is set to 0, clock calibration will not be performed at + startup, and approximate clock frequencies will be assumed: + + - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. + - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. + In case more value will help improve the definition of the launch of the crystal. + If the crystal could not start, it will be switched to internal RC. diff --git a/components/esp_hw_support/port/esp32c6/chip_info.c b/components/esp_hw_support/port/esp32c6/chip_info.c new file mode 100644 index 0000000000..4be74f04bf --- /dev/null +++ b/components/esp_hw_support/port/esp32c6/chip_info.c @@ -0,0 +1,18 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_chip_info.h" +#include "hal/efuse_hal.h" + +void esp_chip_info(esp_chip_info_t *out_info) +{ + memset(out_info, 0, sizeof(*out_info)); + out_info->model = CHIP_ESP32C6; + out_info->revision = efuse_hal_chip_revision(); + out_info->cores = 1; + out_info->features = CHIP_FEATURE_WIFI_BGN | CHIP_FEATURE_BLE; +} diff --git a/components/esp_hw_support/port/esp32c6/esp_crypto_lock.c b/components/esp_hw_support/port/esp32c6/esp_crypto_lock.c new file mode 100644 index 0000000000..34f307b54c --- /dev/null +++ b/components/esp_hw_support/port/esp32c6/esp_crypto_lock.c @@ -0,0 +1,75 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include "esp_crypto_lock.h" + +/* Lock overview: +SHA: peripheral independent, but DMA is shared with AES +AES: peripheral independent, but DMA is shared with SHA +MPI/RSA: independent +HMAC: needs SHA +DS: needs HMAC (which needs SHA), AES and MPI +*/ + +/* Lock for DS peripheral */ +static _lock_t s_crypto_ds_lock; + +/* Lock for HMAC peripheral */ +static _lock_t s_crypto_hmac_lock; + +/* Lock for the MPI/RSA peripheral, also used by the DS peripheral */ +static _lock_t s_crypto_mpi_lock; + +/* Single lock for SHA and AES, sharing a reserved GDMA channel */ +static _lock_t s_crypto_sha_aes_lock; + +void esp_crypto_hmac_lock_acquire(void) +{ + _lock_acquire(&s_crypto_hmac_lock); + esp_crypto_sha_aes_lock_acquire(); +} + +void esp_crypto_hmac_lock_release(void) +{ + esp_crypto_sha_aes_lock_release(); + _lock_release(&s_crypto_hmac_lock); +} + +void esp_crypto_ds_lock_acquire(void) +{ + _lock_acquire(&s_crypto_ds_lock); + esp_crypto_hmac_lock_acquire(); + esp_crypto_mpi_lock_acquire(); +} + +void esp_crypto_ds_lock_release(void) +{ + esp_crypto_mpi_lock_release(); + esp_crypto_hmac_lock_release(); + _lock_release(&s_crypto_ds_lock); +} + +void esp_crypto_sha_aes_lock_acquire(void) +{ + _lock_acquire(&s_crypto_sha_aes_lock); +} + +void esp_crypto_sha_aes_lock_release(void) +{ + _lock_release(&s_crypto_sha_aes_lock); +} + +void esp_crypto_mpi_lock_acquire(void) +{ + _lock_acquire(&s_crypto_mpi_lock); +} + +void esp_crypto_mpi_lock_release(void) +{ + _lock_release(&s_crypto_mpi_lock); +} diff --git a/components/esp_hw_support/port/esp32c6/esp_ds.c b/components/esp_hw_support/port/esp32c6/esp_ds.c new file mode 100644 index 0000000000..7d9228c0a6 --- /dev/null +++ b/components/esp_hw_support/port/esp32c6/esp_ds.c @@ -0,0 +1,224 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "esp_private/periph_ctrl.h" +#include "esp_crypto_lock.h" +#include "hal/ds_hal.h" +#include "hal/ds_ll.h" +#include "hal/hmac_hal.h" +#include "esp32c6/rom/digital_signature.h" +#include "esp_timer.h" +#include "esp_ds.h" + +struct esp_ds_context { + const esp_ds_data_t *data; +}; + +/** + * The vtask delay \c esp_ds_sign() is using while waiting for completion of the signing operation. + */ +#define ESP_DS_SIGN_TASK_DELAY_MS 10 + +#define RSA_LEN_MAX 127 + +/* + * esp_digital_signature_length_t is used in esp_ds_data_t in contrast to ets_ds_data_t, where unsigned is used. + * Check esp_digital_signature_length_t's width here because it's converted to unsigned using raw casts. + */ +_Static_assert(sizeof(esp_digital_signature_length_t) == sizeof(unsigned), + "The size of esp_digital_signature_length_t and unsigned has to be the same"); + +/* + * esp_ds_data_t is used in the encryption function but casted to ets_ds_data_t. + * Check esp_ds_data_t's width here because it's converted using raw casts. + */ +_Static_assert(sizeof(esp_ds_data_t) == sizeof(ets_ds_data_t), + "The size of esp_ds_data_t and ets_ds_data_t has to be the same"); + +static void ds_acquire_enable(void) +{ + esp_crypto_ds_lock_acquire(); + + // We also enable SHA and HMAC here. SHA is used by HMAC, HMAC is used by DS. + periph_module_enable(PERIPH_HMAC_MODULE); + periph_module_enable(PERIPH_SHA_MODULE); + periph_module_enable(PERIPH_DS_MODULE); + + hmac_hal_start(); +} + +static void ds_disable_release(void) +{ + ds_hal_finish(); + + periph_module_disable(PERIPH_DS_MODULE); + periph_module_disable(PERIPH_SHA_MODULE); + periph_module_disable(PERIPH_HMAC_MODULE); + + esp_crypto_ds_lock_release(); +} + +esp_err_t esp_ds_sign(const void *message, + const esp_ds_data_t *data, + hmac_key_id_t key_id, + void *signature) +{ + // Need to check signature here, otherwise the signature is only checked when the signing has finished and fails + // but the signing isn't uninitialized and the mutex is still locked. + if (!signature) { + return ESP_ERR_INVALID_ARG; + } + + esp_ds_context_t *context; + esp_err_t result = esp_ds_start_sign(message, data, key_id, &context); + if (result != ESP_OK) { + return result; + } + + while (esp_ds_is_busy()) + vTaskDelay(ESP_DS_SIGN_TASK_DELAY_MS / portTICK_PERIOD_MS); + + return esp_ds_finish_sign(signature, context); +} + +esp_err_t esp_ds_start_sign(const void *message, + const esp_ds_data_t *data, + hmac_key_id_t key_id, + esp_ds_context_t **esp_ds_ctx) +{ + if (!message || !data || !esp_ds_ctx) { + return ESP_ERR_INVALID_ARG; + } + + if (key_id >= HMAC_KEY_MAX) { + return ESP_ERR_INVALID_ARG; + } + + if (!(data->rsa_length == ESP_DS_RSA_1024 + || data->rsa_length == ESP_DS_RSA_2048 + || data->rsa_length == ESP_DS_RSA_3072)) { + return ESP_ERR_INVALID_ARG; + } + + ds_acquire_enable(); + + // initiate hmac + uint32_t conf_error = hmac_hal_configure(HMAC_OUTPUT_DS, key_id); + if (conf_error) { + ds_disable_release(); + return ESP32C6_ERR_HW_CRYPTO_DS_HMAC_FAIL; + } + + ds_hal_start(); + + // check encryption key from HMAC + int64_t start_time = esp_timer_get_time(); + while (ds_ll_busy() != 0) { + if ((esp_timer_get_time() - start_time) > SOC_DS_KEY_CHECK_MAX_WAIT_US) { + ds_disable_release(); + return ESP32C6_ERR_HW_CRYPTO_DS_INVALID_KEY; + } + } + + esp_ds_context_t *context = malloc(sizeof(esp_ds_context_t)); + if (!context) { + ds_disable_release(); + return ESP_ERR_NO_MEM; + } + + size_t rsa_len = (data->rsa_length + 1) * 4; + ds_hal_write_private_key_params(data->c); + ds_hal_configure_iv(data->iv); + ds_hal_write_message(message, rsa_len); + + // initiate signing + ds_hal_start_sign(); + + context->data = data; + *esp_ds_ctx = context; + + return ESP_OK; +} + +bool esp_ds_is_busy(void) +{ + return ds_hal_busy(); +} + +esp_err_t esp_ds_finish_sign(void *signature, esp_ds_context_t *esp_ds_ctx) +{ + if (!signature || !esp_ds_ctx) { + return ESP_ERR_INVALID_ARG; + } + + const esp_ds_data_t *data = esp_ds_ctx->data; + unsigned rsa_len = (data->rsa_length + 1) * 4; + + while (ds_hal_busy()) { } + + ds_signature_check_t sig_check_result = ds_hal_read_result((uint8_t*) signature, (size_t) rsa_len); + + esp_err_t return_value = ESP_OK; + + if (sig_check_result == DS_SIGNATURE_MD_FAIL || sig_check_result == DS_SIGNATURE_PADDING_AND_MD_FAIL) { + return_value = ESP32C6_ERR_HW_CRYPTO_DS_INVALID_DIGEST; + } + + if (sig_check_result == DS_SIGNATURE_PADDING_FAIL) { + return_value = ESP32C6_ERR_HW_CRYPTO_DS_INVALID_PADDING; + } + + free(esp_ds_ctx); + + hmac_hal_clean(); + + ds_disable_release(); + + return return_value; +} + +esp_err_t esp_ds_encrypt_params(esp_ds_data_t *data, + const void *iv, + const esp_ds_p_data_t *p_data, + const void *key) +{ + if (!p_data) { + return ESP_ERR_INVALID_ARG; + } + + esp_err_t result = ESP_OK; + + esp_crypto_ds_lock_acquire(); + periph_module_enable(PERIPH_AES_MODULE); + periph_module_enable(PERIPH_DS_MODULE); + periph_module_enable(PERIPH_SHA_MODULE); + periph_module_enable(PERIPH_HMAC_MODULE); + periph_module_enable(PERIPH_RSA_MODULE); + + ets_ds_data_t *ds_data = (ets_ds_data_t*) data; + const ets_ds_p_data_t *ds_plain_data = (const ets_ds_p_data_t*) p_data; + + ets_ds_result_t ets_result = ets_ds_encrypt_params(ds_data, iv, ds_plain_data, key, ETS_DS_KEY_HMAC); + + if (ets_result == ETS_DS_INVALID_PARAM) { + result = ESP_ERR_INVALID_ARG; + } + + periph_module_disable(PERIPH_RSA_MODULE); + periph_module_disable(PERIPH_HMAC_MODULE); + periph_module_disable(PERIPH_SHA_MODULE); + periph_module_disable(PERIPH_DS_MODULE); + periph_module_disable(PERIPH_AES_MODULE); + esp_crypto_ds_lock_release(); + + return result; +} diff --git a/components/esp_hw_support/port/esp32c6/esp_hmac.c b/components/esp_hw_support/port/esp32c6/esp_hmac.c new file mode 100644 index 0000000000..99a7d95088 --- /dev/null +++ b/components/esp_hw_support/port/esp32c6/esp_hmac.c @@ -0,0 +1,182 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// TODO: IDF-5355 Copy frome C3 + +#include +#include "esp_private/periph_ctrl.h" +#include "esp32c6/rom/hmac.h" +#include "esp32c6/rom/ets_sys.h" +#include "esp_efuse.h" +#include "esp_efuse_table.h" +#include "esp_hmac.h" +#include "esp_log.h" +#include "esp_crypto_lock.h" +#include "soc/hwcrypto_reg.h" + +#include "hal/hmac_hal.h" + +#define SHA256_BLOCK_SZ 64 +#define SHA256_PAD_SZ 8 + +static const char *TAG = "esp_hmac"; + +/** + * @brief Apply the HMAC padding without the embedded length. + * + * @note This function does not check the data length, it is the responsibility of the other functions in this + * module to make sure that \c data_len is at most SHA256_BLOCK_SZ - 1 so the padding fits in. + * Otherwise, this function has undefined behavior. + * Note however, that for the actual HMAC implementation on ESP32C6, the length also needs to be applied at the end + * of the block. This function alone deosn't do that. + */ +static void write_and_padd(uint8_t *block, const uint8_t *data, uint16_t data_len) +{ + memcpy(block, data, data_len); + // Apply a one bit, followed by zero bits (refer to the ESP32C6 TRM). + block[data_len] = 0x80; + bzero(block + data_len + 1, SHA256_BLOCK_SZ - data_len - 1); +} + +esp_err_t esp_hmac_calculate(hmac_key_id_t key_id, + const void *message, + size_t message_len, + uint8_t *hmac) +{ + const uint8_t *message_bytes = (const uint8_t *)message; + + if (!message || !hmac) { + return ESP_ERR_INVALID_ARG; + } + if (key_id >= HMAC_KEY_MAX) { + return ESP_ERR_INVALID_ARG; + } + + esp_crypto_hmac_lock_acquire(); + + // We also enable SHA and DS here. SHA is used by HMAC, DS will otherwise hold SHA in reset state. + periph_module_enable(PERIPH_HMAC_MODULE); + periph_module_enable(PERIPH_SHA_MODULE); + periph_module_enable(PERIPH_DS_MODULE); + + hmac_hal_start(); + + uint32_t conf_error = hmac_hal_configure(HMAC_OUTPUT_USER, key_id); + if (conf_error) { + esp_crypto_hmac_lock_release(); + return ESP_FAIL; + } + + if (message_len + 1 + SHA256_PAD_SZ <= SHA256_BLOCK_SZ) { + // If message including padding is only one block... + // Last message block, so apply SHA-256 padding rules in software + uint8_t block[SHA256_BLOCK_SZ]; + uint64_t bit_len = __builtin_bswap64(message_len * 8 + 512); + + write_and_padd(block, message_bytes, message_len); + // Final block: append the bit length in this block and signal padding to peripheral + memcpy(block + SHA256_BLOCK_SZ - sizeof(bit_len), + &bit_len, sizeof(bit_len)); + hmac_hal_write_one_block_512(block); + } else { + // If message including padding is needs more than one block + + // write all blocks without padding except the last one + size_t remaining_blocks = message_len / SHA256_BLOCK_SZ; + for (int i = 1; i < remaining_blocks; i++) { + hmac_hal_write_block_512(message_bytes); + message_bytes += SHA256_BLOCK_SZ; + hmac_hal_next_block_normal(); + } + + // If message fits into one block but without padding, we must not write another block. + if (remaining_blocks) { + hmac_hal_write_block_512(message_bytes); + message_bytes += SHA256_BLOCK_SZ; + } + + size_t remaining = message_len % SHA256_BLOCK_SZ; + // Last message block, so apply SHA-256 padding rules in software + uint8_t block[SHA256_BLOCK_SZ]; + uint64_t bit_len = __builtin_bswap64(message_len * 8 + 512); + + // If the remaining message and appended padding doesn't fit into a single block, we have to write an + // extra block with the rest of the message and potential padding first. + if (remaining >= SHA256_BLOCK_SZ - SHA256_PAD_SZ) { + write_and_padd(block, message_bytes, remaining); + hmac_hal_next_block_normal(); + hmac_hal_write_block_512(block); + bzero(block, SHA256_BLOCK_SZ); + } else { + write_and_padd(block, message_bytes, remaining); + } + memcpy(block + SHA256_BLOCK_SZ - sizeof(bit_len), + &bit_len, sizeof(bit_len)); + hmac_hal_next_block_padding(); + hmac_hal_write_block_512(block); + } + + // Read back result (bit swapped) + hmac_hal_read_result_256(hmac); + + periph_module_disable(PERIPH_DS_MODULE); + periph_module_disable(PERIPH_SHA_MODULE); + periph_module_disable(PERIPH_HMAC_MODULE); + + esp_crypto_hmac_lock_release(); + + return ESP_OK; +} + +static ets_efuse_block_t convert_key_type(hmac_key_id_t key_id) { + return ETS_EFUSE_BLOCK_KEY0 + (ets_efuse_block_t) key_id; +} + +esp_err_t esp_hmac_jtag_enable(hmac_key_id_t key_id, const uint8_t *token) +{ + int ets_status; + esp_err_t err = ESP_OK; + + if ((!token) || (key_id >= HMAC_KEY_MAX)) + return ESP_ERR_INVALID_ARG; + + /* Check if JTAG is permanently disabled by HW Disable eFuse */ + if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_PAD_JTAG)) { + ESP_LOGE(TAG, "JTAG disabled permanently."); + return ESP_FAIL; + } + + esp_crypto_hmac_lock_acquire(); + + ets_status = ets_jtag_enable_temporarily(token, convert_key_type(key_id)); + + if (ets_status != ETS_OK) { + // ets_jtag_enable_temporarily returns either ETS_OK or ETS_FAIL + err = ESP_FAIL; + ESP_LOGE(TAG, "JTAG re-enabling failed (%d)", err); + } + + ESP_LOGD(TAG, "HMAC computation in downstream mode is completed."); + + ets_hmac_disable(); + + esp_crypto_hmac_lock_release(); + + return err; +} + +esp_err_t esp_hmac_jtag_disable() +{ + esp_crypto_hmac_lock_acquire(); + + REG_SET_BIT(HMAC_SET_INVALIDATE_JTAG_REG, HMAC_SET_INVALIDATE_JTAG); + + esp_crypto_hmac_lock_release(); + + ESP_LOGD(TAG, "Invalidate JTAG result register. JTAG disabled."); + + return ESP_OK; +} diff --git a/components/esp_hw_support/port/esp32c6/esp_memprot.c b/components/esp_hw_support/port/esp32c6/esp_memprot.c new file mode 100644 index 0000000000..8bb37b54c4 --- /dev/null +++ b/components/esp_hw_support/port/esp32c6/esp_memprot.c @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// TODO: IDF-5684 +// ESP32C6 has no memory permission management mechanism based on dividing lines, +// TEE-based implementation can be added here diff --git a/components/esp_hw_support/port/esp32c6/rtc_clk.c b/components/esp_hw_support/port/esp32c6/rtc_clk.c new file mode 100644 index 0000000000..fe7aa35b84 --- /dev/null +++ b/components/esp_hw_support/port/esp32c6/rtc_clk.c @@ -0,0 +1,226 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include "sdkconfig.h" +#include "esp32c6/rom/ets_sys.h" +#include "esp32c6/rom/rtc.h" +#include "soc/rtc.h" +#include "esp_hw_log.h" +#include "esp_rom_sys.h" +#include "hal/usb_serial_jtag_ll.h" +#include "hal/clk_tree_ll.h" +#include "hal/regi2c_ctrl_ll.h" +#include "soc/lp_clkrst_reg.h" + +static const char *TAG = "rtc_clk"; + +void rtc_clk_32k_enable(bool enable) +{ + // TODO: IDF-5645 +} + +void rtc_clk_32k_enable_external(void) +{ + // TODO: IDF-5645 +} + +void rtc_clk_32k_bootstrap(uint32_t cycle) +{ + // TODO: IDF-5645 +} + +bool rtc_clk_32k_enabled(void) +{ + // TODO: IDF-5645 + return 0; +} + +void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en) +{ + // TODO: IDF-5645 +} + +bool rtc_clk_8m_enabled(void) +{ + // TODO: IDF-5645 + return 0; +} + +bool rtc_clk_8md256_enabled(void) +{ + // TODO: IDF-5645 + return 0; +} + +void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src) +{ + // TODO: IDF-5645 +} + +soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void) +{ + // TODO: IDF-5645 + return REG_GET_FIELD(LP_CLKRST_LP_CLK_CONF_REG, LP_CLKRST_SLOW_CLK_SEL); +} + +uint32_t rtc_clk_slow_freq_get_hz(void) +{ + // TODO: IDF-5645 + switch (rtc_clk_slow_freq_get()) { + case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K; + case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K; + case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256; + default: return 0; + } +} + +void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src) +{ + // TODO: IDF-5645 +} + +soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void) +{ + // TODO: IDF-5645 + return 0; +} + +#if 0 +static void rtc_clk_bbpll_disable(void) +{ + // TODO: IDF-5645 +} + +static void rtc_clk_bbpll_enable(void) +{ + // TODO: IDF-5645 +} + +static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq) +{ + // TODO: IDF-5645 +} + +/** + * Switch to one of PLL-based frequencies. Current frequency can be XTAL or PLL. + * PLL must already be enabled. + * @param cpu_freq new CPU frequency + */ +static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) +{ + // TODO: IDF-5645 +} +#endif + +bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config) +{ + // TODO: IDF-5645 + return 0; +} + +void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config) +{ + // TODO: IDF-5645 +} + +void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config) +{ + // TODO: IDF-5645 +} + +void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config) +{ + // TODO: IDF-5645 +} + +void rtc_clk_cpu_freq_set_xtal(void) +{ + ESP_EARLY_LOGW(TAG, "rtc_clk_cpu_freq_set_xtal() has not been implemented yet"); + // TODO: IDF-5645 +} + +#if 0 +/** + * Switch to XTAL frequency. Does not disable the PLL. + */ +static void rtc_clk_cpu_freq_to_xtal(int freq, int div) +{ + // TODO: IDF-5645 +} + +static void rtc_clk_cpu_freq_to_8m(void) +{ + // TODO: IDF-5645 +} +#endif + +rtc_xtal_freq_t rtc_clk_xtal_freq_get(void) +{ + ESP_EARLY_LOGW(TAG, "rtc_clk_xtal_freq_get() has not been implemented yet"); + // TODO: IDF-5645 + return 40; +} + +void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq) +{ + // TODO: IDF-5645 +} + +void rtc_clk_apb_freq_update(uint32_t apb_freq) +{ + // TODO: IDF-5645 +} + +uint32_t rtc_clk_apb_freq_get(void) +{ + ESP_EARLY_LOGW(TAG, "rtc_clk_apb_freq_get() has not been implemented yet"); + // TODO: IDF-5645 + return 0; +} + +void rtc_clk_divider_set(uint32_t div) +{ + // TODO: IDF-5645 +} + +void rtc_clk_8m_divider_set(uint32_t div) +{ + // TODO: IDF-5645 +} + +void rtc_dig_clk8m_enable(void) +{ + // TODO: IDF-5645 +} + +void rtc_dig_clk8m_disable(void) +{ + // TODO: IDF-5645 +} + +bool rtc_dig_8m_enabled(void) +{ + // TODO: IDF-5645 + return 0; +} + +#if 0 +static bool rtc_clk_set_bbpll_always_on(void) +{ + // TODO: IDF-5645 + return 0; +} +#endif + +/* Name used in libphy.a:phy_chip_v7.o + * TODO: update the library to use rtc_clk_xtal_freq_get + */ +rtc_xtal_freq_t rtc_get_xtal(void) __attribute__((alias("rtc_clk_xtal_freq_get"))); diff --git a/components/esp_hw_support/port/esp32c6/rtc_clk_init.c b/components/esp_hw_support/port/esp32c6/rtc_clk_init.c new file mode 100644 index 0000000000..73a950930f --- /dev/null +++ b/components/esp_hw_support/port/esp32c6/rtc_clk_init.c @@ -0,0 +1,84 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include "esp32c6/rom/ets_sys.h" +#include "esp32c6/rom/rtc.h" +#include "esp32c6/rom/uart.h" +#include "soc/rtc.h" +#include "soc/efuse_periph.h" +#include "esp_cpu.h" +#include "hal/regi2c_ctrl_ll.h" +#include "esp_hw_log.h" +#include "sdkconfig.h" +#include "esp_rom_uart.h" + +static const char *TAG = "rtc_clk_init"; + +void rtc_clk_init(rtc_clk_config_t cfg) +{ + ESP_HW_LOGW(TAG, "rtc_clk_init() has not been implemented yet"); +#if 0 // TODO: IDF-5645 + rtc_cpu_freq_config_t old_config, new_config; + + /* Set tuning parameters for 8M and 150k clocks. + * Note: this doesn't attempt to set the clocks to precise frequencies. + * Instead, we calibrate these clocks against XTAL frequency later, when necessary. + * - SCK_DCAP value controls tuning of 150k clock. + * The higher the value of DCAP is, the lower is the frequency. + * - CK8M_DFREQ value controls tuning of 8M clock. + * CLK_8M_DFREQ constant gives the best temperature characteristics. + */ + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap); + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq); + + /* Configure 150k clock division */ + rtc_clk_divider_set(cfg.clk_rtc_clk_div); + + /* Configure 8M clock division */ + rtc_clk_8m_divider_set(cfg.clk_8m_clk_div); + + /* Reset (disable) i2c internal bus for all regi2c registers */ + regi2c_ctrl_ll_i2c_reset(); // TODO: This should be move out from rtc_clk_init + /* Enable the internal bus used to configure BBPLL */ + regi2c_ctrl_ll_i2c_bbpll_enable(); // TODO: This should be moved to bbpll_set_config + + rtc_xtal_freq_t xtal_freq = cfg.xtal_freq; + esp_rom_uart_tx_wait_idle(0); + rtc_clk_xtal_freq_update(xtal_freq); + rtc_clk_apb_freq_update(xtal_freq * MHZ); + + /* Set CPU frequency */ + rtc_clk_cpu_freq_get_config(&old_config); + uint32_t freq_before = old_config.freq_mhz; + bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config); + if (!res) { + ESP_HW_LOGE(TAG, "invalid CPU frequency value"); + abort(); + } + rtc_clk_cpu_freq_set_config(&new_config); + + /* Re-calculate the ccount to make time calculation correct. */ + esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * cfg.cpu_freq_mhz / freq_before ); + + /* Slow & fast clocks setup */ + // We will not power off RC_FAST in bootloader stage even if it is not being used as any + // cpu / rtc_fast / rtc_slow clock sources, this is because RNG always needs it in the bootloader stage. + bool need_rc_fast_en = true; + bool need_rc_fast_d256_en = false; + if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { + rtc_clk_32k_enable(true); + } else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { + need_rc_fast_d256_en = true; + } + rtc_clk_8m_enable(need_rc_fast_en, need_rc_fast_d256_en); + rtc_clk_fast_src_set(cfg.fast_clk_src); + rtc_clk_slow_src_set(cfg.slow_clk_src); +#endif +} diff --git a/components/esp_hw_support/port/esp32c6/rtc_init.c b/components/esp_hw_support/port/esp32c6/rtc_init.c new file mode 100644 index 0000000000..8a5daa4517 --- /dev/null +++ b/components/esp_hw_support/port/esp32c6/rtc_init.c @@ -0,0 +1,7 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// TODO: IDF-5645 diff --git a/components/esp_hw_support/port/esp32c6/rtc_pm.c b/components/esp_hw_support/port/esp32c6/rtc_pm.c new file mode 100644 index 0000000000..8a5daa4517 --- /dev/null +++ b/components/esp_hw_support/port/esp32c6/rtc_pm.c @@ -0,0 +1,7 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// TODO: IDF-5645 diff --git a/components/esp_hw_support/port/esp32c6/rtc_sleep.c b/components/esp_hw_support/port/esp32c6/rtc_sleep.c new file mode 100644 index 0000000000..8a5daa4517 --- /dev/null +++ b/components/esp_hw_support/port/esp32c6/rtc_sleep.c @@ -0,0 +1,7 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// TODO: IDF-5645 diff --git a/components/esp_hw_support/port/esp32c6/rtc_time.c b/components/esp_hw_support/port/esp32c6/rtc_time.c new file mode 100644 index 0000000000..b5bfa6e7d2 --- /dev/null +++ b/components/esp_hw_support/port/esp32c6/rtc_time.c @@ -0,0 +1,103 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp32c6/rom/ets_sys.h" +#include "soc/rtc.h" +// #include "soc/rtc_cntl_reg.h" +#include "hal/clk_tree_ll.h" +#include "soc/timer_group_reg.h" +#include "esp_rom_sys.h" + +/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. + * This feature counts the number of XTAL clock cycles within a given number of + * RTC_SLOW_CLK cycles. + * + * Slow clock calibration feature has two modes of operation: one-off and cycling. + * In cycling mode (which is enabled by default on SoC reset), counting of XTAL + * cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled + * using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed + * once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is + * enabled using TIMG_RTC_CALI_START bit. + */ + +/** + * @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio + * @param cal_clk which clock to calibrate + * @param slowclk_cycles number of slow clock cycles to count + * @return number of XTAL clock cycles within the given number of slow clock cycles + */ +// TODO: IDF-5645 +static const char *TAG = "rtc_time"; + +uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) +{ + // TODO: IDF-5645 + ESP_EARLY_LOGW(TAG, "rtc_clk_cal_internal() has not been implemented yet"); + return 0; +} + +uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) +{ + // TODO: IDF-5645 + ESP_EARLY_LOGW(TAG, "rtc_clk_cal_ratio() has not been implemented yet"); + return 0; +} + +uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) +{ + // TODO: IDF-5645 + ESP_EARLY_LOGW(TAG, "rtc_clk_cal() has not been implemented yet"); + return 0; +} + +uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period) +{ + // TODO: IDF-5645 + ESP_EARLY_LOGW(TAG, "rtc_time_us_to_slowclk() has not been implemented yet"); + return 0; +} + +uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period) +{ + // TODO: IDF-5645 + ESP_EARLY_LOGW(TAG, "rtc_time_slowclk_to_us() has not been implemented yet"); + return 0; +} + +uint64_t rtc_time_get(void) +{ + // TODO: IDF-5645 + ESP_EARLY_LOGW(TAG, "rtc_time_get() has not been implemented yet"); + return 0; +} + +uint64_t rtc_light_slp_time_get(void) +{ + // TODO: IDF-5645 + ESP_EARLY_LOGW(TAG, "rtc_light_slp_time_get() has not been implemented yet"); + return 0; +} + +uint64_t rtc_deep_slp_time_get(void) +{ + // TODO: IDF-5645 + ESP_EARLY_LOGW(TAG, "rtc_deep_slp_time_get() has not been implemented yet"); + return 0; +} + +void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more +{ + // TODO: IDF-5645 + ESP_EARLY_LOGW(TAG, "rtc_clk_wait_for_slow_cycle() has not been implemented yet"); +} + +uint32_t rtc_clk_freq_cal(uint32_t cal_val) +{ + // TODO: IDF-5645 + ESP_EARLY_LOGW(TAG, "rtc_clk_freq_cal() has not been implemented yet"); + return 0; +} diff --git a/components/esp_hw_support/port/esp32c6/systimer.c b/components/esp_hw_support/port/esp32c6/systimer.c new file mode 100644 index 0000000000..d5ea58b1aa --- /dev/null +++ b/components/esp_hw_support/port/esp32c6/systimer.c @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_private/systimer.h" + +/** + * @brief systimer's clock source is fixed to XTAL (40MHz), and has a fixed fractional divider (2.5). + * So the resolution of the systimer is 40MHz/2.5 = 16MHz. + */ + +uint64_t systimer_ticks_to_us(uint64_t ticks) +{ + return ticks / 16; +} + +uint64_t systimer_us_to_ticks(uint64_t us) +{ + return us * 16; +} diff --git a/components/esp_hw_support/port/esp32h2/rtc_time.c b/components/esp_hw_support/port/esp32h2/rtc_time.c index 6c817b6315..88563ebc8b 100644 --- a/components/esp_hw_support/port/esp32h2/rtc_time.c +++ b/components/esp_hw_support/port/esp32h2/rtc_time.c @@ -126,10 +126,22 @@ uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) return ratio; } +static inline bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles) +{ + uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768 + uint64_t delta = expected_xtal_cycles / 2000; // 5/10000 + return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta)); +} + uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); + + if ((cal_clk == RTC_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid(xtal_freq, slowclk_cycles, xtal_cycles)) { + return 0; + } + uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles; uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider; uint32_t period = (uint32_t)(period_64 & UINT32_MAX); diff --git a/components/esp_hw_support/port/esp32s2/rtc_time.c b/components/esp_hw_support/port/esp32s2/rtc_time.c index 3fd21be81b..c8e22bf8bf 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_time.c +++ b/components/esp_hw_support/port/esp32s2/rtc_time.c @@ -194,11 +194,22 @@ uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) return ratio; } +static inline bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles) +{ + uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768 + uint64_t delta = expected_xtal_cycles / 2000; // 5/10000 + return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta)); +} + uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles, RTC_TIME_CAL_ONEOFF_MODE); - uint32_t period = rtc_clk_xtal_to_slowclk(xtal_cycles, slowclk_cycles); - return period; + + if ((cal_clk == RTC_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid(rtc_clk_xtal_freq_get(), slowclk_cycles, xtal_cycles)) { + return 0; + } + + return rtc_clk_xtal_to_slowclk(xtal_cycles, slowclk_cycles); } uint32_t rtc_clk_cal_cycling(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) diff --git a/components/esp_hw_support/port/esp32s3/rtc_clk.c b/components/esp_hw_support/port/esp32s3/rtc_clk.c index 39c33ec6ec..d595ca20e2 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_clk.c +++ b/components/esp_hw_support/port/esp32s3/rtc_clk.c @@ -30,10 +30,15 @@ static uint32_t s_cur_pll_freq; static uint32_t s_apb_freq; -static void rtc_clk_cpu_freq_to_xtal(int freq, int div); +void rtc_clk_cpu_freq_to_xtal(int freq, int div); static void rtc_clk_cpu_freq_to_8m(void); static bool rtc_clk_set_bbpll_always_on(void); +extern uint32_t g_dig_dbias_pvt_240m; +extern uint32_t g_rtc_dbias_pvt_240m; +extern uint32_t g_dig_dbias_pvt_non_240m; +extern uint32_t g_rtc_dbias_pvt_non_240m; + void rtc_clk_32k_enable(bool enable) { if (enable) { @@ -94,18 +99,6 @@ bool rtc_clk_8md256_enabled(void) return clk_ll_rc_fast_d256_is_enabled(); } -static void wait_dig_dbias_valid(uint64_t rtc_cycles) -{ - soc_rtc_slow_clk_src_t slow_clk_freq = rtc_clk_slow_src_get(); - rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX; - if (slow_clk_freq == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { - cal_clk = RTC_CAL_32K_XTAL; - } else if (slow_clk_freq == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { - cal_clk = RTC_CAL_8MD256; - } - rtc_clk_cal(cal_clk, rtc_cycles); -} - void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src) { clk_ll_rtc_slow_set_src(clk_src); @@ -182,17 +175,45 @@ static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq) */ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) { - int dbias = (cpu_freq_mhz == 240) ? DIG_DBIAS_240M : DIG_DBIAS_80M_160M; - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dbias); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, dbias); - wait_dig_dbias_valid(2); + /* cpu_frequency < 240M: dbias = pvt-dig + 2; + cpu_frequency = 240M: dbias = pvt-dig + 3; + */ + if (cpu_freq_mhz != 240) { + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m); + } else { + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_240m); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_240m); + } + esp_rom_delay_us(40); - clk_ll_cpu_set_freq_mhz_from_pll(cpu_freq_mhz); - clk_ll_cpu_set_divider(1); - /* switch clock source */ - clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL); - rtc_clk_apb_freq_update(80 * MHZ); - ets_update_cpu_frequency(cpu_freq_mhz); + /* There are totally 6 LDO slaves(all on by default). At the moment of swithing LDO slave, LDO voltage will also change instantaneously. + * LDO slave can reduce the voltage change caused by switching frequency. + * CPU frequency <= 40M : just open 3 LDO slaves; CPU frequency = 80M : open 4 LDO slaves; CPU frequency = 160M : open 5 LDO slaves; CPU frequency = 240M : open 6 LDO slaves; + * + * LDO voltage will decrease at the moment of switching from low frequency to high frequency; otherwise, LDO voltage will increase. + * In order to reduce LDO voltage drop, LDO voltage should rise first then fall. + */ + int pd_slave = cpu_freq_mhz / 80; + rtc_cpu_freq_config_t cur_config; + rtc_clk_cpu_freq_get_config(&cur_config); + if (cpu_freq_mhz > cur_config.freq_mhz) { + REG_SET_FIELD(RTC_CNTL_DATE_REG, RTC_CNTL_SLAVE_PD, DEFAULT_LDO_SLAVE >> pd_slave); + clk_ll_cpu_set_freq_mhz_from_pll(cpu_freq_mhz); + clk_ll_cpu_set_divider(1); + /* switch clock source */ + clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL); + rtc_clk_apb_freq_update(80 * MHZ); + ets_update_cpu_frequency(cpu_freq_mhz); + } else { + clk_ll_cpu_set_freq_mhz_from_pll(cpu_freq_mhz); + clk_ll_cpu_set_divider(1); + /* switch clock source */ + clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL); + rtc_clk_apb_freq_update(80 * MHZ); + ets_update_cpu_frequency(cpu_freq_mhz); + REG_SET_FIELD(RTC_CNTL_DATE_REG, RTC_CNTL_SLAVE_PD, DEFAULT_LDO_SLAVE >> pd_slave); + } } bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config) @@ -336,30 +357,33 @@ void rtc_clk_cpu_freq_set_xtal(void) /** * Switch to XTAL frequency. Does not disable the PLL. + * Public function for testing only. */ -static void rtc_clk_cpu_freq_to_xtal(int freq, int div) +void rtc_clk_cpu_freq_to_xtal(int freq, int div) { + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m); + esp_rom_delay_us(40); ets_update_cpu_frequency(freq); - /* set digital voltage for different cpu freq from xtal */ - int dbias = (freq <= 2) ? DIG_DBIAS_2M : DIG_DBIAS_XTAL; - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dbias); - wait_dig_dbias_valid(2); /* Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first. */ clk_ll_cpu_set_divider(1); clk_ll_cpu_set_divider(div); /* switch clock source */ clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL); rtc_clk_apb_freq_update(freq * MHZ); + REG_SET_FIELD(RTC_CNTL_DATE_REG, RTC_CNTL_SLAVE_PD, DEFAULT_LDO_SLAVE); } static void rtc_clk_cpu_freq_to_8m(void) { ets_update_cpu_frequency(20); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, DIG_DBIAS_XTAL); - wait_dig_dbias_valid(2); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m); + esp_rom_delay_us(40); clk_ll_cpu_set_divider(1); clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST); rtc_clk_apb_freq_update(SOC_CLK_RC_FAST_FREQ_APPROX); + REG_SET_FIELD(RTC_CNTL_DATE_REG, RTC_CNTL_SLAVE_PD, DEFAULT_LDO_SLAVE); } rtc_xtal_freq_t rtc_clk_xtal_freq_get(void) diff --git a/components/esp_hw_support/port/esp32s3/rtc_init.c b/components/esp_hw_support/port/esp32s3/rtc_init.c index 266e330c15..b4e364594f 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_init.c +++ b/components/esp_hw_support/port/esp32s3/rtc_init.c @@ -24,7 +24,7 @@ #include "esp_efuse.h" #include "esp_efuse_table.h" #include "esp_private/spi_flash_os.h" - +#include "hal/efuse_hal.h" #define RTC_CNTL_MEM_FORCE_NOISO (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO) @@ -32,6 +32,13 @@ static const char *TAG = "rtcinit"; static void set_ocode_by_efuse(int calib_version); static void calibrate_ocode(void); +static void rtc_set_stored_dbias(void); + +// Initial values are used for bootloader, and these variables will be re-assigned based on efuse values during application startup +uint32_t g_dig_dbias_pvt_240m = 28; +uint32_t g_rtc_dbias_pvt_240m = 28; +uint32_t g_dig_dbias_pvt_non_240m = 27; +uint32_t g_rtc_dbias_pvt_non_240m = 27; void rtc_init(rtc_config_t cfg) { @@ -89,6 +96,12 @@ void rtc_init(rtc_config_t cfg) } } + //LDO dbias initialization + rtc_set_stored_dbias(); + + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m); + if (cfg.clkctl_init) { //clear CMMU clock force on CLEAR_PERI_REG_MASK(EXTMEM_CACHE_MMU_POWER_CTRL_REG, EXTMEM_CACHE_MMU_MEM_FORCE_ON); @@ -301,3 +314,116 @@ static void calibrate_ocode(void) spi_timing_change_speed_mode_cache_safe(false); #endif } + +static uint32_t get_dig_dbias_by_efuse(uint8_t pvt_scheme_ver) +{ + assert(pvt_scheme_ver == 1); + uint32_t dig_dbias = 28; + esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_DIG_DBIAS_HVT, &dig_dbias, ESP_EFUSE_DIG_DBIAS_HVT[0]->bit_count); + if (err != ESP_OK) { + dig_dbias = 28; + ESP_HW_LOGW(TAG, "efuse read fail, set default dig_dbias value: %d\n", dig_dbias); + } + return dig_dbias; +} + +static uint32_t get_rtc_dbias_by_efuse(uint8_t pvt_scheme_ver, uint32_t dig_dbias) +{ + assert(pvt_scheme_ver == 1); + uint32_t rtc_dbias = 0; + signed int k_rtc_ldo = 0, k_dig_ldo = 0, v_rtc_bias20 = 0, v_dig_bias20 = 0; + esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_K_RTC_LDO, &k_rtc_ldo, ESP_EFUSE_K_RTC_LDO[0]->bit_count); + esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_K_DIG_LDO, &k_dig_ldo, ESP_EFUSE_K_DIG_LDO[0]->bit_count); + esp_err_t err2 = esp_efuse_read_field_blob(ESP_EFUSE_V_RTC_DBIAS20, &v_rtc_bias20, ESP_EFUSE_V_RTC_DBIAS20[0]->bit_count); + esp_err_t err3 = esp_efuse_read_field_blob(ESP_EFUSE_V_DIG_DBIAS20, &v_dig_bias20, ESP_EFUSE_V_DIG_DBIAS20[0]->bit_count); + if ((err0 != ESP_OK) | (err1 != ESP_OK) | (err2 != ESP_OK) | (err3 != ESP_OK)) { + k_rtc_ldo = 0; + k_dig_ldo = 0; + v_rtc_bias20 = 0; + v_dig_bias20 = 0; + ESP_HW_LOGW(TAG, "efuse read fail, k_rtc_ldo: %d, k_dig_ldo: %d, v_rtc_bias20: %d, v_dig_bias20: %d\n", k_rtc_ldo, k_dig_ldo, v_rtc_bias20, v_dig_bias20); + } + + k_rtc_ldo = ((k_rtc_ldo & BIT(6)) != 0)? -(k_rtc_ldo & 0x3f): (uint8_t)k_rtc_ldo; + k_dig_ldo = ((k_dig_ldo & BIT(6)) != 0)? -(k_dig_ldo & 0x3f): (uint8_t)k_dig_ldo; + v_rtc_bias20 = ((v_rtc_bias20 & BIT(7)) != 0)? -(v_rtc_bias20 & 0x7f): (uint8_t)v_rtc_bias20; + v_dig_bias20 = ((v_dig_bias20 & BIT(7)) != 0)? -(v_dig_bias20 & 0x7f): (uint8_t)v_dig_bias20; + + uint32_t v_rtc_dbias20_real_mul10000 = V_RTC_MID_MUL10000 + v_rtc_bias20 * 10000 / 500; + uint32_t v_dig_dbias20_real_mul10000 = V_DIG_MID_MUL10000 + v_dig_bias20 * 10000 / 500; + signed int k_rtc_ldo_real_mul10000 = K_RTC_MID_MUL10000 + k_rtc_ldo; + signed int k_dig_ldo_real_mul10000 = K_DIG_MID_MUL10000 + k_dig_ldo; + uint32_t v_dig_nearest_1v15_mul10000 = v_dig_dbias20_real_mul10000 + k_dig_ldo_real_mul10000 * (dig_dbias - 20); + for (rtc_dbias = 15; rtc_dbias < 31; rtc_dbias++) { + uint32_t v_rtc_nearest_1v15_mul10000 = 0; + v_rtc_nearest_1v15_mul10000 = v_rtc_dbias20_real_mul10000 + k_rtc_ldo_real_mul10000 * (rtc_dbias - 20); + if (v_rtc_nearest_1v15_mul10000 >= v_dig_nearest_1v15_mul10000 - 250) { + break; + } + } + return rtc_dbias; +} + +static uint32_t get_dig1v3_dbias_by_efuse(uint8_t pvt_scheme_ver) +{ + assert(pvt_scheme_ver == 1); + signed int k_dig_ldo = 0, v_dig_bias20 = 0; + esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_K_DIG_LDO, &k_dig_ldo, ESP_EFUSE_K_DIG_LDO[0]->bit_count); + esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_V_DIG_DBIAS20, &v_dig_bias20, ESP_EFUSE_V_DIG_DBIAS20[0]->bit_count); + if ((err0 != ESP_OK) | (err1 != ESP_OK)) { + k_dig_ldo = 0; + v_dig_bias20 = 0; + ESP_HW_LOGW(TAG, "efuse read fail, k_dig_ldo: %d, v_dig_bias20: %d\n", k_dig_ldo, v_dig_bias20); + } + + k_dig_ldo = ((k_dig_ldo & BIT(6)) != 0)? -(k_dig_ldo & 0x3f): (uint8_t)k_dig_ldo; + v_dig_bias20 = ((v_dig_bias20 & BIT(7)) != 0)? -(v_dig_bias20 & 0x7f): (uint8_t)v_dig_bias20; + + uint32_t v_dig_dbias20_real_mul10000 = V_DIG_MID_MUL10000 + v_dig_bias20 * 10000 / 500; + signed int k_dig_ldo_real_mul10000 = K_DIG_MID_MUL10000 + k_dig_ldo; + uint32_t dig_dbias =15; + for (dig_dbias = 15; dig_dbias < 31; dig_dbias++) { + uint32_t v_dig_nearest_1v3_mul10000 = 0; + v_dig_nearest_1v3_mul10000 = v_dig_dbias20_real_mul10000 + k_dig_ldo_real_mul10000 * (dig_dbias - 20); + if (v_dig_nearest_1v3_mul10000 >= 13000) { + break; + } + } + return dig_dbias; +} + +static void rtc_set_stored_dbias(void) +{ + /* + 1. a reasonable dig_dbias which by scaning pvt to make 240 CPU run successful stored in efuse; + 2. also we store some value in efuse, include: + k_rtc_ldo (slope of rtc voltage & rtc_dbias); + k_dig_ldo (slope of digital voltage & digital_dbias); + v_rtc_bias20 (rtc voltage when rtc dbais is 20); + v_dig_bias20 (digital voltage when digital dbais is 20). + 3. a reasonable rtc_dbias can be calculated by a certion formula. + 4. save these values for reuse + */ + uint8_t blk_minor = efuse_ll_get_blk_version_minor(); + uint8_t blk_major = efuse_ll_get_blk_version_major(); + uint8_t pvt_scheme_ver = 0; + if ( (blk_major <= 1 && blk_minor == 1) || blk_major > 1 || (blk_major == 1 && blk_minor >= 2) ) { + /* PVT supported after blk_ver 1.2 */ + pvt_scheme_ver = 1; + } + + if (pvt_scheme_ver == 1) { + uint32_t dig1v3_dbias = get_dig1v3_dbias_by_efuse(pvt_scheme_ver); + uint32_t dig_dbias = get_dig_dbias_by_efuse(pvt_scheme_ver); + if (dig_dbias != 0) { + g_dig_dbias_pvt_240m = MIN(dig1v3_dbias, dig_dbias + 3); + g_dig_dbias_pvt_non_240m = MIN(dig1v3_dbias, dig_dbias + 2); + g_rtc_dbias_pvt_240m = get_rtc_dbias_by_efuse(pvt_scheme_ver, g_dig_dbias_pvt_240m); + g_rtc_dbias_pvt_non_240m = get_rtc_dbias_by_efuse(pvt_scheme_ver, g_dig_dbias_pvt_non_240m); + } else { + ESP_HW_LOGD(TAG, "not burn core voltage in efuse or burn wrong voltage value in blk version: 0%d\n", pvt_scheme_ver); + } + } else { + ESP_HW_LOGD(TAG, "core voltage not decided in efuse, use default value."); + } +} diff --git a/components/esp_hw_support/port/esp32s3/rtc_time.c b/components/esp_hw_support/port/esp32s3/rtc_time.c index 5e9bb8faf8..9c07e6a9d6 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_time.c +++ b/components/esp_hw_support/port/esp32s3/rtc_time.c @@ -131,10 +131,22 @@ uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) return ratio; } +static inline bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles) +{ + uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768 + uint64_t delta = expected_xtal_cycles / 2000; // 5/10000 + return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta)); +} + uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); + + if ((cal_clk == RTC_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid(xtal_freq, slowclk_cycles, xtal_cycles)) { + return 0; + } + uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles; uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider; uint32_t period = (uint32_t)(period_64 & UINT32_MAX); diff --git a/components/esp_hw_support/rtc_module.c b/components/esp_hw_support/rtc_module.c index 640f4c1db6..8a8637c9e3 100644 --- a/components/esp_hw_support/rtc_module.c +++ b/components/esp_hw_support/rtc_module.c @@ -27,6 +27,12 @@ #endif #include "sys/queue.h" +#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645 +static const char *TAG = "rtc_module"; +#endif + +#if !CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645 + #define NOT_REGISTERED (-1) portMUX_TYPE rtc_spinlock = portMUX_INITIALIZER_UNLOCKED; @@ -90,9 +96,14 @@ out: portEXIT_CRITICAL(&s_rtc_isr_handler_list_lock); return err; } +#endif // !CONFIG_IDF_TARGET_ESP32C6 TODO: IDF-5645 esp_err_t rtc_isr_register(intr_handler_t handler, void* handler_arg, uint32_t rtc_intr_mask, uint32_t flags) { +#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645 + ESP_LOGW(TAG, "rtc_isr_register() has not been implemented yet"); + return ESP_OK; +#else esp_err_t err = rtc_isr_ensure_installed(); if (err != ESP_OK) { return err; @@ -115,10 +126,15 @@ esp_err_t rtc_isr_register(intr_handler_t handler, void* handler_arg, uint32_t r SLIST_INSERT_HEAD(&s_rtc_isr_handler_list, item, next); portEXIT_CRITICAL(&s_rtc_isr_handler_list_lock); return ESP_OK; +#endif } esp_err_t rtc_isr_deregister(intr_handler_t handler, void* handler_arg) { +#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645 + ESP_LOGW(TAG, "rtc_isr_deregister() has not been implemented yet"); + return ESP_OK; +#else rtc_isr_handler_t* it; rtc_isr_handler_t* prev = NULL; bool found = false; @@ -141,8 +157,10 @@ esp_err_t rtc_isr_deregister(intr_handler_t handler, void* handler_arg) } portEXIT_CRITICAL(&s_rtc_isr_handler_list_lock); return found ? ESP_OK : ESP_ERR_INVALID_STATE; +#endif } +#if !CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645 /** * @brief This helper function can be used to avoid the interrupt to be triggered with cache disabled. * There are lots of different signals on RTC module (i.e. sleep_wakeup, wdt, brownout_detect, etc.) @@ -160,19 +178,25 @@ static void s_rtc_isr_noniram_hook_relieve(uint32_t rtc_intr_mask) { rtc_intr_cache &= ~rtc_intr_mask; } +#endif + IRAM_ATTR void rtc_isr_noniram_disable(uint32_t cpu) { +#if !CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645 if (rtc_isr_cpu == cpu) { rtc_intr_enabled |= RTCCNTL.int_ena.val; RTCCNTL.int_ena.val &= rtc_intr_cache; } +#endif } IRAM_ATTR void rtc_isr_noniram_enable(uint32_t cpu) { +#if !CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645 if (rtc_isr_cpu == cpu) { RTCCNTL.int_ena.val = rtc_intr_enabled; rtc_intr_enabled = 0; } +#endif } diff --git a/components/esp_hw_support/sleep_gpio.c b/components/esp_hw_support/sleep_gpio.c index ae4cede0f0..ff4d47cfdf 100644 --- a/components/esp_hw_support/sleep_gpio.c +++ b/components/esp_hw_support/sleep_gpio.c @@ -12,11 +12,13 @@ #include "esp_attr.h" #include "esp_sleep.h" #include "esp_log.h" +#include "esp_memory_utils.h" #include "soc/soc_caps.h" #include "sdkconfig.h" #include "driver/gpio.h" +#include "hal/gpio_hal.h" #include "esp_private/gpio.h" #include "esp_private/sleep_gpio.h" #include "esp_private/spi_flash_os.h" @@ -94,3 +96,44 @@ void esp_sleep_enable_gpio_switch(bool enable) } #endif // SOC_GPIO_SUPPORT_SLP_SWITCH + +// TODO: IDF-6051, IDF-6052 +#if !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C6 +IRAM_ATTR void esp_sleep_isolate_digital_gpio(void) +{ + gpio_hal_context_t gpio_hal = { + .dev = GPIO_HAL_GET_HW(GPIO_PORT_0) + }; + + /* no need to do isolate if digital IOs are not being held in deep sleep */ + if (!gpio_hal_deep_sleep_hold_is_en(&gpio_hal)) { + return; + } + + /** + * there is a situation where we cannot isolate digital IO before deep sleep: + * - task stack is located in external ram(mspi ram), since we will isolate mspi io + * + * assert here instead of returning directly, because if digital IO is not isolated, + * the bottom current of deep sleep will be higher than light sleep, and there is no + * reason to use deep sleep at this time. + */ + assert(esp_ptr_internal(&gpio_hal) && "If hold digital IO, the stack of the task calling esp_deep_sleep_start must be in internal ram!"); + + /* isolate digital IO that is not held(keep the configuration of digital IOs held by users) */ + for (gpio_num_t gpio_num = GPIO_NUM_0; gpio_num < GPIO_NUM_MAX; gpio_num++) { + if (GPIO_IS_VALID_DIGITAL_IO_PAD(gpio_num) && !gpio_hal_is_digital_io_hold(&gpio_hal, gpio_num)) { + /* disable I/O */ + gpio_hal_input_disable(&gpio_hal, gpio_num); + gpio_hal_output_disable(&gpio_hal, gpio_num); + + /* disable pull up/down */ + gpio_hal_pullup_dis(&gpio_hal, gpio_num); + gpio_hal_pulldown_dis(&gpio_hal, gpio_num); + + /* make pad work as gpio(otherwise, deep sleep bottom current will rise) */ + gpio_hal_func_sel(&gpio_hal, gpio_num, PIN_FUNC_GPIO); + } + } +} +#endif diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 58caee9b3e..3a6b94b3c1 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -12,6 +12,7 @@ #include "esp_attr.h" #include "esp_memory_utils.h" #include "esp_sleep.h" +#include "esp_private/esp_sleep_internal.h" #include "esp_private/esp_timer_private.h" #include "esp_private/system_internal.h" #include "esp_log.h" @@ -23,6 +24,7 @@ #include "soc/soc_caps.h" #include "driver/rtc_io.h" #include "hal/rtc_io_hal.h" +#include "hal/rtc_cntl_ll.h" #include "driver/uart.h" @@ -47,6 +49,7 @@ #include "esp_private/sleep_retention.h" #include "esp_private/esp_clk.h" #include "esp_private/startup_internal.h" +#include "esp_private/esp_task_wdt.h" #ifdef CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/cache.h" @@ -76,6 +79,10 @@ #include "esp32c2/rom/cache.h" #include "esp32c2/rom/rtc.h" #include "soc/extmem_reg.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/cache.h" +#include "esp32c6/rom/rtc.h" +#include "soc/extmem_reg.h" #endif // If light sleep time is less than that, don't power down flash @@ -105,6 +112,9 @@ #elif CONFIG_IDF_TARGET_ESP32C2 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (118) #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (9) +#elif CONFIG_IDF_TARGET_ESP32C6 +#define DEFAULT_SLEEP_OUT_OVERHEAD_US (118)// TODO: IDF-5348 +#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (9) #endif #define LIGHT_SLEEP_TIME_OVERHEAD_US DEFAULT_HARDWARE_OUT_OVERHEAD_US @@ -499,13 +509,10 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags) uint32_t result; if (deep_sleep) { - /* Disable interrupts in case another task writes to RTC memory while we - * calculate RTC memory CRC - * - * Note: for ESP32-S3 running in dual core mode this is currently not enough, - * see the assert at top of this function. - */ - portENTER_CRITICAL(&spinlock_rtc_deep_sleep); +// TODO: IDF-6051, IDF-6052 +#if !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C6 + esp_sleep_isolate_digital_gpio(); +#endif #if SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY extern char _rtc_text_start[]; @@ -531,8 +538,6 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags) result = rtc_deep_sleep_start(s_config.wakeup_triggers, reject_triggers); #endif #endif // SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY - - portEXIT_CRITICAL(&spinlock_rtc_deep_sleep); } else { result = call_rtc_sleep_start(reject_triggers, config.lslp_mem_inf_fpu); } @@ -662,15 +667,39 @@ static inline bool can_power_down_vddsdio(const uint32_t vddsdio_pd_sleep_durati esp_err_t esp_light_sleep_start(void) { +#if CONFIG_ESP_TASK_WDT_USE_ESP_TIMER + esp_err_t timerret = ESP_OK; + + /* If a task watchdog timer is running, we have to stop it. */ + timerret = esp_task_wdt_stop(); +#endif // CONFIG_ESP_TASK_WDT_USE_ESP_TIMER + s_config.ccount_ticks_record = esp_cpu_get_cycle_count(); static portMUX_TYPE light_sleep_lock = portMUX_INITIALIZER_UNLOCKED; portENTER_CRITICAL(&light_sleep_lock); + /* + Note: We are about to stall the other CPU via the esp_ipc_isr_stall_other_cpu(). However, there is a chance of + deadlock if after stalling the other CPU, we attempt to take spinlocks already held by the other CPU that is. + + Thus any functions that we call after stalling the other CPU will need to have the locks taken first to avoid + deadlock. + + Todo: IDF-5257 + */ + /* We will be calling esp_timer_private_set inside DPORT access critical * section. Make sure the code on the other CPU is not holding esp_timer * lock, otherwise there will be deadlock. */ esp_timer_private_lock(); + /* We will be calling esp_rtc_get_time_us() below. Make sure the code on the other CPU is not holding the + * esp_rtc_get_time_us() lock, otherwise there will be deadlock. esp_rtc_get_time_us() is called via: + * + * - esp_clk_slowclk_cal_set() -> esp_rtc_get_time_us() + */ + esp_clk_private_lock(); + s_config.rtc_ticks_at_sleep_start = rtc_time_get(); uint32_t ccount_at_sleep_start = esp_cpu_get_cycle_count(); uint64_t high_res_time_at_start = esp_timer_get_time(); @@ -763,7 +792,11 @@ esp_err_t esp_light_sleep_start(void) rtc_vddsdio_config_t vddsdio_config = rtc_vddsdio_get_config(); // Safety net: enable WDT in case exit from light sleep fails +#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5653 + wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &LP_WDT}; +#else wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; +#endif bool wdt_was_enabled = wdt_hal_is_enabled(&rtc_wdt_ctx); // If WDT was enabled in the user code, then do not change it here. if (!wdt_was_enabled) { wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false); @@ -793,6 +826,7 @@ esp_err_t esp_light_sleep_start(void) } esp_set_time_from_rtc(); + esp_clk_private_unlock(); esp_timer_private_unlock(); esp_ipc_isr_release_other_cpu(); if (!wdt_was_enabled) { @@ -802,6 +836,14 @@ esp_err_t esp_light_sleep_start(void) } portEXIT_CRITICAL(&light_sleep_lock); s_config.sleep_time_overhead_out = (esp_cpu_get_cycle_count() - s_config.ccount_ticks_record) / (esp_clk_cpu_freq() / 1000000ULL); + +#if CONFIG_ESP_TASK_WDT_USE_ESP_TIMER + /* Restart the Task Watchdog timer as it was stopped before sleeping. */ + if (timerret == ESP_OK) { + esp_task_wdt_restart(); + } +#endif // CONFIG_ESP_TASK_WDT_USE_ESP_TIMER + return err; } @@ -851,7 +893,6 @@ esp_err_t esp_sleep_enable_ulp_wakeup(void) #ifndef CONFIG_ULP_COPROC_ENABLED return ESP_ERR_INVALID_STATE; #endif // CONFIG_ULP_COPROC_ENABLED - #if CONFIG_IDF_TARGET_ESP32 #if ((defined CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT) || (defined CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT_V2)) ESP_LOGE(TAG, "Failed to enable wakeup when provide current to external 32kHz crystal"); @@ -917,6 +958,7 @@ static void touch_wakeup_prepare(void) esp_err_t esp_sleep_enable_touchpad_wakeup(void) { +#if CONFIG_IDF_TARGET_ESP32 #if ((defined CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT) || (defined CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT_V2)) ESP_LOGE(TAG, "Failed to enable wakeup when provide current to external 32kHz crystal"); return ESP_ERR_NOT_SUPPORTED; @@ -925,6 +967,8 @@ esp_err_t esp_sleep_enable_touchpad_wakeup(void) ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0"); return ESP_ERR_INVALID_STATE; } +#endif //CONFIG_IDF_TARGET_ESP32 + s_config.wakeup_triggers |= RTC_TOUCH_TRIG_EN; return ESP_OK; } @@ -961,10 +1005,13 @@ esp_err_t esp_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level) if (!esp_sleep_is_valid_wakeup_gpio(gpio_num)) { return ESP_ERR_INVALID_ARG; } +#if CONFIG_IDF_TARGET_ESP32 if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) { ESP_LOGE(TAG, "Conflicting wake-up triggers: touch / ULP"); return ESP_ERR_INVALID_STATE; } +#endif //CONFIG_IDF_TARGET_ESP32 + s_config.ext0_rtc_gpio_num = rtc_io_number_get(gpio_num); s_config.ext0_trigger_level = level; s_config.wakeup_triggers |= RTC_EXT0_TRIG_EN; @@ -1191,6 +1238,9 @@ esp_err_t esp_sleep_disable_bt_wakeup(void) esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void) { +#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645 + return ESP_SLEEP_WAKEUP_UNDEFINED; +#else if (esp_rom_get_reset_reason(0) != RESET_REASON_CORE_DEEP_SLEEP && !s_light_sleep_wakeup) { return ESP_SLEEP_WAKEUP_UNDEFINED; } @@ -1238,6 +1288,7 @@ esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void) } else { return ESP_SLEEP_WAKEUP_UNDEFINED; } +#endif } esp_err_t esp_sleep_pd_config(esp_sleep_pd_domain_t domain, @@ -1290,28 +1341,18 @@ static uint32_t get_power_down_flags(void) #if SOC_PM_SUPPORT_RTC_PERIPH_PD // RTC_PERIPH is needed for EXT0 wakeup and GPIO wakeup. - // If RTC_PERIPH is auto, and EXT0/GPIO aren't enabled, power down RTC_PERIPH. + // If RTC_PERIPH is left auto (EXT0/GPIO aren't enabled), RTC_PERIPH will be powered off by default. if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] == ESP_PD_OPTION_AUTO) { -#if SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP - uint32_t wakeup_source = RTC_TOUCH_TRIG_EN; -#if SOC_ULP_SUPPORTED - wakeup_source |= RTC_ULP_TRIG_EN; -#endif if (s_config.wakeup_triggers & (RTC_EXT0_TRIG_EN | RTC_GPIO_TRIG_EN)) { s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_ON; - } else if (s_config.wakeup_triggers & wakeup_source) { - // In both rev. 0 and rev. 1 of ESP32, forcing power up of RTC_PERIPH + } +#if CONFIG_IDF_TARGET_ESP32 + else if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) { + // On ESP32, forcing power up of RTC_PERIPH // prevents ULP timer and touch FSMs from working correctly. s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_OFF; } -#else - - if (s_config.wakeup_triggers & RTC_GPIO_TRIG_EN) { - s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_ON; - } else { - s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_OFF; - } -#endif // SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP +#endif //CONFIG_IDF_TARGET_ESP32 } #endif // SOC_PM_SUPPORT_RTC_PERIPH_PD diff --git a/components/esp_hw_support/test/test_dport.c b/components/esp_hw_support/test/test_dport.c index 97a971aefe..02975e42ea 100644 --- a/components/esp_hw_support/test/test_dport.c +++ b/components/esp_hw_support/test/test_dport.c @@ -17,6 +17,7 @@ #include "freertos/task.h" #include "freertos/semphr.h" #include "freertos/xtensa_timer.h" +#include "driver/uart.h" #include "unity.h" #include "test_utils.h" #include "esp_rom_uart.h" @@ -140,7 +141,10 @@ void run_tasks_with_change_freq_cpu(int cpu_freq_mhz) esp_rom_uart_tx_wait_idle(uart_num); rtc_clk_cpu_freq_set_config(&new_config); uart_ll_set_sclk(UART_LL_GET_HW(uart_num), UART_SCLK_DEFAULT); - uart_ll_set_baudrate(UART_LL_GET_HW(uart_num), uart_baud); + + uint32_t sclk_freq; + TEST_ESP_OK(uart_get_sclk_freq(UART_SCLK_DEFAULT, &sclk_freq)); + uart_ll_set_baudrate(UART_LL_GET_HW(uart_num), uart_baud, sclk_freq); /* adjust RTOS ticks */ _xt_tick_divisor = cpu_freq_mhz * 1000000 / XT_TICK_PER_SEC; vTaskDelay(2); @@ -153,7 +157,10 @@ void run_tasks_with_change_freq_cpu(int cpu_freq_mhz) esp_rom_uart_tx_wait_idle(uart_num); rtc_clk_cpu_freq_set_config(&old_config); uart_ll_set_sclk(UART_LL_GET_HW(uart_num), UART_SCLK_DEFAULT); - uart_ll_set_baudrate(UART_LL_GET_HW(uart_num), uart_baud); + + uint32_t sclk_freq; + TEST_ESP_OK(uart_get_sclk_freq(UART_SCLK_DEFAULT, &sclk_freq)); + uart_ll_set_baudrate(UART_LL_GET_HW(uart_num), uart_baud, sclk_freq); _xt_tick_divisor = old_config.freq_mhz * 1000000 / XT_TICK_PER_SEC; } diff --git a/components/esp_hw_support/test/test_rtc_clk.c b/components/esp_hw_support/test/test_rtc_clk.c index 57a149c017..c45357ede3 100644 --- a/components/esp_hw_support/test/test_rtc_clk.c +++ b/components/esp_hw_support/test/test_rtc_clk.c @@ -83,7 +83,7 @@ TEST_CASE("RTC_SLOW_CLK sources calibration", "[rtc_clk]") CALIBRATE_ONE(RTC_CAL_8MD256); #if CONFIG_IDF_TARGET_ESP32C2 - uint32_t cal_ext_slow_clk = CALIBRATE_ONE(RTC_CAL_EXT_CLK); + uint32_t cal_ext_slow_clk = CALIBRATE_ONE(RTC_CAL_EXT_32K); if (cal_ext_slow_clk == 0) { printf("EXT CLOCK by PIN has not started up"); } else { @@ -93,7 +93,7 @@ TEST_CASE("RTC_SLOW_CLK sources calibration", "[rtc_clk]") CALIBRATE_ONE(RTC_CAL_RTC_MUX); CALIBRATE_ONE(RTC_CAL_8MD256); - CALIBRATE_ONE(RTC_CAL_EXT_CLK); + CALIBRATE_ONE(RTC_CAL_EXT_32K); } #else uint32_t cal_32k = CALIBRATE_ONE(RTC_CAL_32K_XTAL); @@ -116,7 +116,7 @@ TEST_CASE("RTC_SLOW_CLK sources calibration", "[rtc_clk]") CALIBRATE_ONE(RTC_CAL_RTC_MUX); CALIBRATE_ONE(RTC_CAL_8MD256); #if CONFIG_IDF_TARGET_ESP32C2 - CALIBRATE_ONE(RTC_CAL_EXT_CLK); + CALIBRATE_ONE(RTC_CAL_EXT_32K); #else CALIBRATE_ONE(RTC_CAL_32K_XTAL); #endif diff --git a/components/esp_hw_support/test_apps/dma/CMakeLists.txt b/components/esp_hw_support/test_apps/dma/CMakeLists.txt new file mode 100644 index 0000000000..349909489f --- /dev/null +++ b/components/esp_hw_support/test_apps/dma/CMakeLists.txt @@ -0,0 +1,7 @@ +# This is the project CMakeLists.txt file for the test subproject +cmake_minimum_required(VERSION 3.16) + +set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components") + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(dma_test) diff --git a/components/esp_hw_support/test_apps/dma/README.md b/components/esp_hw_support/test_apps/dma/README.md new file mode 100644 index 0000000000..b5be4985c5 --- /dev/null +++ b/components/esp_hw_support/test_apps/dma/README.md @@ -0,0 +1,2 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | diff --git a/components/esp_hw_support/test_apps/dma/main/CMakeLists.txt b/components/esp_hw_support/test_apps/dma/main/CMakeLists.txt new file mode 100644 index 0000000000..0fb8a69f50 --- /dev/null +++ b/components/esp_hw_support/test_apps/dma/main/CMakeLists.txt @@ -0,0 +1,14 @@ +set(srcs "test_app_main.c") + +if(CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED) + list(APPEND srcs "test_async_memcpy.c") +endif() + +if(CONFIG_SOC_GDMA_SUPPORTED) + list(APPEND srcs "test_gdma.c") +endif() + +# In order for the cases defined by `TEST_CASE` to be linked into the final elf, +# the component can be registered as WHOLE_ARCHIVE +idf_component_register(SRCS ${srcs} + WHOLE_ARCHIVE) diff --git a/components/esp_hw_support/test_apps/dma/main/test_app_main.c b/components/esp_hw_support/test_apps/dma/main/test_app_main.c new file mode 100644 index 0000000000..311f7bbb72 --- /dev/null +++ b/components/esp_hw_support/test_apps/dma/main/test_app_main.c @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "unity.h" +#include "unity_test_runner.h" +#include "esp_heap_caps.h" + +// Some resources are lazy allocated in pulse_cnt driver, the threshold is left for that case +#define TEST_MEMORY_LEAK_THRESHOLD (-300) + +static size_t before_free_8bit; +static size_t before_free_32bit; + +static void check_leak(size_t before_free, size_t after_free, const char *type) +{ + ssize_t delta = after_free - before_free; + printf("MALLOC_CAP_%s: Before %u bytes free, After %u bytes free (delta %d)\n", type, before_free, after_free, delta); + TEST_ASSERT_MESSAGE(delta >= TEST_MEMORY_LEAK_THRESHOLD, "memory leak"); +} + +void setUp(void) +{ + before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); +} + +void tearDown(void) +{ + size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); + check_leak(before_free_8bit, after_free_8bit, "8BIT"); + check_leak(before_free_32bit, after_free_32bit, "32BIT"); +} + +void app_main(void) +{ + // ____ __ __ _ _____ _ + // | _ \| \/ | / \ |_ _|__ ___| |_ + // | | | | |\/| | / _ \ | |/ _ \/ __| __| + // | |_| | | | |/ ___ \ | | __/\__ \ |_ + // |____/|_| |_/_/ \_\ |_|\___||___/\__| + printf(" ____ __ __ _ _____ _\r\n"); + printf("| _ \\| \\/ | / \\ |_ _|__ ___| |_\r\n"); + printf("| | | | |\\/| | / _ \\ | |/ _ \\/ __| __|\r\n"); + printf("| |_| | | | |/ ___ \\ | | __/\\__ \\ |_\r\n"); + printf("|____/|_| |_/_/ \\_\\ |_|\\___||___/\\__|\r\n"); + unity_run_menu(); +} diff --git a/components/esp_hw_support/test/test_async_memcpy.c b/components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c similarity index 97% rename from components/esp_hw_support/test/test_async_memcpy.c rename to components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c index 60e84cca79..8d05e7ae6e 100644 --- a/components/esp_hw_support/test/test_async_memcpy.c +++ b/components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c @@ -1,11 +1,12 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include #include #include +#include #include #include "esp_heap_caps.h" #include "esp_rom_sys.h" @@ -19,14 +20,12 @@ #include "soc/soc_caps.h" #include "hal/dma_types.h" -#if SOC_CP_DMA_SUPPORTED || SOC_GDMA_SUPPORTED - #define ALIGN_UP(addr, align) (((addr) + (align)-1) & ~((align)-1)) #define ALIGN_DOWN(size, align) ((size) & ~((align) - 1)) typedef struct { uint32_t seed; - uint32_t buffer_size; + size_t buffer_size; uint8_t *src_buf; uint8_t *dst_buf; uint8_t *from_addr; @@ -41,7 +40,7 @@ static void async_memcpy_setup_testbench(memcpy_testbench_context_t *test_contex { srand(test_context->seed); printf("allocating memory buffer...\r\n"); - uint32_t buffer_size = test_context->buffer_size; + size_t buffer_size = test_context->buffer_size; uint8_t *src_buf = NULL; uint8_t *dst_buf = NULL; uint8_t *from_addr = NULL; @@ -75,7 +74,7 @@ static void async_memcpy_setup_testbench(memcpy_testbench_context_t *test_contex to_addr += test_context->offset; buffer_size -= test_context->offset; - printf("...size %d Bytes, src@%p, dst@%p\r\n", buffer_size, from_addr, to_addr); + printf("...size %zu Bytes, src@%p, dst@%p\r\n", buffer_size, from_addr, to_addr); printf("fill src buffer with random data\r\n"); for (int i = 0; i < buffer_size; i++) { from_addr[i] = rand() % 256; @@ -332,5 +331,3 @@ TEST_CASE("memory copy performance test 4KB", "[async mcp]") { memcpy_performance_test(4 * 1024); } - -#endif //SOC_CP_DMA_SUPPORTED || SOC_GDMA_SUPPORTED diff --git a/components/esp_hw_support/test/test_gdma.c b/components/esp_hw_support/test_apps/dma/main/test_gdma.c similarity index 98% rename from components/esp_hw_support/test/test_gdma.c rename to components/esp_hw_support/test_apps/dma/main/test_gdma.c index 6dc447ddcb..8d4e74fd6f 100644 --- a/components/esp_hw_support/test/test_gdma.c +++ b/components/esp_hw_support/test_apps/dma/main/test_gdma.c @@ -7,8 +7,6 @@ #include "esp_private/gdma.h" #include "soc/soc_caps.h" -#if SOC_GDMA_SUPPORTED - TEST_CASE("GDMA channel allocation", "[gdma]") { gdma_channel_alloc_config_t channel_config = {}; @@ -69,5 +67,3 @@ TEST_CASE("GDMA channel allocation", "[gdma]") } #endif } - -#endif diff --git a/components/esp_hw_support/test_apps/dma/pytest_dma.py b/components/esp_hw_support/test_apps/dma/pytest_dma.py new file mode 100644 index 0000000000..d15a0ea289 --- /dev/null +++ b/components/esp_hw_support/test_apps/dma/pytest_dma.py @@ -0,0 +1,23 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +import pytest +from pytest_embedded import Dut + + +@pytest.mark.esp32s2 +@pytest.mark.esp32s3 +@pytest.mark.esp32c2 +@pytest.mark.esp32c3 +@pytest.mark.generic +@pytest.mark.parametrize( + 'config', + [ + 'release', + ], + indirect=True, +) +def test_dma(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('*') + dut.expect_unity_test_output() diff --git a/components/esp_hw_support/test_apps/dma/sdkconfig.ci.release b/components/esp_hw_support/test_apps/dma/sdkconfig.ci.release new file mode 100644 index 0000000000..22bd3f16c0 --- /dev/null +++ b/components/esp_hw_support/test_apps/dma/sdkconfig.ci.release @@ -0,0 +1,6 @@ +# set compilier optimization level +CONFIG_COMPILER_OPTIMIZATION_SIZE=y +CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y + +# we can silent the assertion to save the binary footprint +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y diff --git a/components/esp_hw_support/test_apps/dma/sdkconfig.defaults b/components/esp_hw_support/test_apps/dma/sdkconfig.defaults new file mode 100644 index 0000000000..b308cb2ddd --- /dev/null +++ b/components/esp_hw_support/test_apps/dma/sdkconfig.defaults @@ -0,0 +1,2 @@ +CONFIG_FREERTOS_HZ=1000 +CONFIG_ESP_TASK_WDT=n diff --git a/components/esp_lcd/CMakeLists.txt b/components/esp_lcd/CMakeLists.txt index 4382f91ec1..a77acae0d9 100644 --- a/components/esp_lcd/CMakeLists.txt +++ b/components/esp_lcd/CMakeLists.txt @@ -21,7 +21,6 @@ idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${includes} PRIV_REQUIRES ${priv_requires} LDFRAGMENTS linker.lf) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") if(CONFIG_SPIRAM) idf_component_optional_requires(PRIVATE esp_psram) diff --git a/components/esp_lcd/include/esp_lcd_panel_io.h b/components/esp_lcd/include/esp_lcd_panel_io.h index 9d0196eb71..f702a9251e 100644 --- a/components/esp_lcd/include/esp_lcd_panel_io.h +++ b/components/esp_lcd/include/esp_lcd_panel_io.h @@ -208,7 +208,7 @@ esp_err_t esp_lcd_del_i80_bus(esp_lcd_i80_bus_handle_t bus); */ typedef struct { int cs_gpio_num; /*!< GPIO used for CS line, set to -1 will declaim exclusively use of I80 bus */ - unsigned int pclk_hz; /*!< Frequency of pixel clock */ + uint32_t pclk_hz; /*!< Frequency of pixel clock */ size_t trans_queue_depth; /*!< Transaction queue size, larger queue, higher throughput */ esp_lcd_panel_io_color_trans_done_cb_t on_color_trans_done; /*!< Callback invoked when color data was tranferred done */ void *user_ctx; /*!< User private data, passed directly to on_color_trans_done's user_ctx */ diff --git a/components/esp_lcd/include/esp_lcd_panel_rgb.h b/components/esp_lcd/include/esp_lcd_panel_rgb.h index 1c48856128..b23090693b 100644 --- a/components/esp_lcd/include/esp_lcd_panel_rgb.h +++ b/components/esp_lcd/include/esp_lcd_panel_rgb.h @@ -79,7 +79,7 @@ typedef struct { /** * @brief RGB LCD VSYNC event callback prototype * - * @param[in] panel LCD panel handle, returned from `esp_lcd_new_rgb_panel()` + * @param[in] panel LCD panel handle, returned from `esp_lcd_new_rgb_panel` * @param[in] edata Panel event data, fed by driver * @param[in] user_ctx User data, passed from `esp_lcd_rgb_panel_register_event_callbacks()` * @return Whether a high priority task has been waken up by this function @@ -89,6 +89,7 @@ typedef bool (*esp_lcd_rgb_panel_vsync_cb_t)(esp_lcd_panel_handle_t panel, const /** * @brief Prototype for function to re-fill a bounce buffer, rather than copying from the frame buffer * + * @param[in] panel LCD panel handle, returned from `esp_lcd_new_rgb_panel` * @param[in] bounce_buf Bounce buffer to write data into * @param[in] pos_px How many pixels already were sent to the display in this frame, in other words, * at what pixel the routine should start putting data into bounce_buf @@ -115,7 +116,7 @@ typedef struct { lcd_clock_source_t clk_src; /*!< Clock source for the RGB LCD peripheral */ esp_lcd_rgb_timing_t timings; /*!< RGB timing parameters, including the screen resolution */ size_t data_width; /*!< Number of data lines */ - size_t bits_per_pixel; /*!< Color depth, in bpp, specially, if set to zero, it will default to `data_width`. + size_t bits_per_pixel; /*!< Frame buffer color depth, in bpp, specially, if set to zero, it will default to `data_width`. When using a Serial RGB interface, this value could be different from `data_width` */ size_t bounce_buffer_size_px; /*!< If it's non-zero, the driver allocates two DRAM bounce buffers for DMA use. DMA fetching from DRAM bounce buffer is much faster than PSRAM frame buffer. */ @@ -156,7 +157,7 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf /** * @brief Register LCD RGB panel event callbacks * - * @param[in] panel LCD panel handle, returned from `esp_lcd_new_rgb_panel()` + * @param[in] panel LCD panel handle, returned from `esp_lcd_new_rgb_panel` * @param[in] callbacks Group of callback functions * @param[in] user_ctx User data, which will be passed to the callback functions directly * @return @@ -175,7 +176,7 @@ esp_err_t esp_lcd_rgb_panel_register_event_callbacks(esp_lcd_panel_handle_t pane * @note This function doesn't cause the hardware to update the PCLK immediately but to record the new frequency and set a flag internally. * Only in the next VSYNC event handler, will the driver attempt to update the PCLK frequency. * - * @param[in] panel LCD panel handle, returned from `esp_lcd_new_rgb_panel()` + * @param[in] panel LCD panel handle, returned from `esp_lcd_new_rgb_panel` * @param[in] freq_hz Frequency of pixel clock, in Hz * @return * - ESP_ERR_INVALID_ARG: Set PCLK frequency failed because of invalid argument @@ -183,10 +184,28 @@ esp_err_t esp_lcd_rgb_panel_register_event_callbacks(esp_lcd_panel_handle_t pane */ esp_err_t esp_lcd_rgb_panel_set_pclk(esp_lcd_panel_handle_t panel, uint32_t freq_hz); +/** + * @brief Restart the LCD transmission + * + * @note This function can be useful when the LCD controller is out of sync with the DMA because of insufficient bandwidth. + * To save the screen from a permanent shift, you can call this function to restart the LCD DMA. + * @note This function doesn't restart the DMA immediately but to set a flag internally. + * Only in the next VSYNC event handler, will the driver attempt to do the restart job. + * @note If CONFIG_LCD_RGB_RESTART_IN_VSYNC is enabled, you don't need to call this function manually, + * because the restart job will be done automatically in the VSYNC event handler. + * + * @param[in] panel panel LCD panel handle, returned from `esp_lcd_new_rgb_panel` + * @return + * - ESP_ERR_INVALID_ARG: Restart the LCD failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Restart the LCD failed because the LCD diver is working in refresh-on-demand mode + * - ESP_OK: Restart the LCD successfully + */ +esp_err_t esp_lcd_rgb_panel_restart(esp_lcd_panel_handle_t panel); + /** * @brief Get the address of the frame buffer(s) that allocated by the driver * - * @param[in] panel LCD panel handle, returned from `esp_lcd_new_rgb_panel()` + * @param[in] panel LCD panel handle, returned from `esp_lcd_new_rgb_panel` * @param[in] fb_num Number of frame buffer(s) to get. This value must be the same as the number of the following parameters. * @param[out] fb0 Returned address of the frame buffer 0 * @param[out] ... List of other frame buffer addresses @@ -201,7 +220,7 @@ esp_err_t esp_lcd_rgb_panel_get_frame_buffer(esp_lcd_panel_handle_t panel, uint3 * * @note This function should only be called when the RGB panel is working under the `refresh_on_demand` mode. * - * @param[in] panel LCD panel handle, returned from `esp_lcd_new_rgb_panel()` + * @param[in] panel LCD panel handle, returned from `esp_lcd_new_rgb_panel` * @return * - ESP_ERR_INVALID_ARG: Start a refresh failed because of invalid argument * - ESP_ERR_INVALID_STATE: Start a refresh failed because the LCD panel is not created with the `refresh_on_demand` flag enabled. @@ -209,6 +228,39 @@ esp_err_t esp_lcd_rgb_panel_get_frame_buffer(esp_lcd_panel_handle_t panel, uint3 */ esp_err_t esp_lcd_rgb_panel_refresh(esp_lcd_panel_handle_t panel); +/** + * @brief LCD color conversion profile + */ +typedef struct { + lcd_color_space_t color_space; /*!< Color space of the image */ + lcd_color_range_t color_range; /*!< Color range of the image */ + lcd_yuv_sample_t yuv_sample; /*!< YUV sample format of the image */ +} esp_lcd_color_conv_profile_t; + +/** + * @brief Configuration of YUG-RGB conversion + */ +typedef struct { + lcd_yuv_conv_std_t std; /*!< YUV conversion standard: BT601, BT709 */ + esp_lcd_color_conv_profile_t src; /*!< Color conversion profile of the input image */ + esp_lcd_color_conv_profile_t dst; /*!< Color conversion profile of the output image */ +} esp_lcd_yuv_conv_config_t; + +/** + * @brief Configure how to convert the color format between RGB and YUV + * + * @note Pass in `config` as NULL will disable the RGB-YUV converter. + * @note The hardware converter can only parse a "packed" storage format, while "planar" and "semi-planar" format is not supported. + * + * @param[in] panel LCD panel handle, returned from `esp_lcd_new_rgb_panel` + * @param[in] config Configuration of RGB-YUV conversion + * @return + * - ESP_ERR_INVALID_ARG: Configure RGB-YUV conversion failed because of invalid argument + * - ESP_ERR_NOT_SUPPORTED: Configure RGB-YUV conversion failed because the conversion mode is not supported by the hardware + * - ESP_OK: Configure RGB-YUV conversion successfully + */ +esp_err_t esp_lcd_rgb_panel_set_yuv_conversion(esp_lcd_panel_handle_t panel, const esp_lcd_yuv_conv_config_t *config); + #endif // SOC_LCD_RGB_SUPPORTED #ifdef __cplusplus diff --git a/components/esp_lcd/include/esp_lcd_panel_vendor.h b/components/esp_lcd/include/esp_lcd_panel_vendor.h index 2503adeb7e..7dfeda7671 100644 --- a/components/esp_lcd/include/esp_lcd_panel_vendor.h +++ b/components/esp_lcd/include/esp_lcd_panel_vendor.h @@ -18,7 +18,10 @@ extern "C" { */ typedef struct { int reset_gpio_num; /*!< GPIO used to reset the LCD panel, set to -1 if it's not used */ - esp_lcd_color_space_t color_space; /*!< Set the color space used by the LCD panel */ + union { + lcd_color_rgb_endian_t color_space; /*!< @deprecated Set RGB color space, please use rgb_endian instead */ + lcd_color_rgb_endian_t rgb_endian; /*!< Set RGB data endian: RGB or BGR */ + }; unsigned int bits_per_pixel; /*!< Color depth, in bpp */ struct { unsigned int reset_active_high: 1; /*!< Setting this if the panel reset is high level active */ diff --git a/components/esp_lcd/include/esp_lcd_types.h b/components/esp_lcd/include/esp_lcd_types.h index 7d4953247f..e0b2c330bf 100644 --- a/components/esp_lcd/include/esp_lcd_types.h +++ b/components/esp_lcd/include/esp_lcd_types.h @@ -1,10 +1,12 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once +#include "hal/lcd_types.h" + #ifdef __cplusplus extern "C" { #endif @@ -12,14 +14,22 @@ extern "C" { typedef struct esp_lcd_panel_io_t *esp_lcd_panel_io_handle_t; /*!< Type of LCD panel IO handle */ typedef struct esp_lcd_panel_t *esp_lcd_panel_handle_t; /*!< Type of LCD panel handle */ +/** @cond */ /** - * @brief LCD color space type definition + * @brief LCD color space type definition (WRONG!) + * @deprecated RGB and BGR should belong to the same color space, but this enum take them both as two different color spaces. + * If you want to use a enum to describe a color space, please use lcd_color_space_t instead. */ typedef enum { ESP_LCD_COLOR_SPACE_RGB, /*!< Color space: RGB */ ESP_LCD_COLOR_SPACE_BGR, /*!< Color space: BGR */ ESP_LCD_COLOR_SPACE_MONOCHROME, /*!< Color space: monochrome */ -} esp_lcd_color_space_t; +} esp_lcd_color_space_t __attribute__((deprecated)); + +// Ensure binary compatibility with lcd_color_rgb_endian_t +_Static_assert((lcd_color_rgb_endian_t)ESP_LCD_COLOR_SPACE_RGB == LCD_RGB_ENDIAN_RGB, "ESP_LCD_COLOR_SPACE_RGB is not compatible with LCD_RGB_ENDIAN_RGB"); +_Static_assert((lcd_color_rgb_endian_t)ESP_LCD_COLOR_SPACE_BGR == LCD_RGB_ENDIAN_BGR, "ESP_LCD_COLOR_SPACE_BGR is not compatible with LCD_RGB_ENDIAN_BGR"); +/** @endcond */ #ifdef __cplusplus } diff --git a/components/esp_lcd/src/esp_lcd_panel_io_i2s.c b/components/esp_lcd/src/esp_lcd_panel_io_i2s.c index e57d3303fb..22b20499c4 100644 --- a/components/esp_lcd/src/esp_lcd_panel_io_i2s.c +++ b/components/esp_lcd/src/esp_lcd_panel_io_i2s.c @@ -95,7 +95,7 @@ struct lcd_panel_io_i80_t { esp_lcd_panel_io_t base; // Base class of generic lcd panel io esp_lcd_i80_bus_t *bus; // Which bus the device is attached to int cs_gpio_num; // GPIO used for CS line - unsigned int pclk_hz; // PCLK clock frequency + uint32_t pclk_hz; // PCLK clock frequency size_t clock_prescale; // Prescaler coefficient, determined by user's configured PCLK frequency QueueHandle_t trans_queue; // Transaction queue, transactions in this queue are pending for scheduler to dispatch QueueHandle_t done_queue; // Transaction done queue, transactions in this queue are finished but not recycled by the caller @@ -170,7 +170,7 @@ esp_err_t esp_lcd_new_i80_bus(const esp_lcd_i80_bus_config_t *bus_config, esp_lc i2s_ll_tx_reset_fifo(bus->hal.dev); // install interrupt service, (I2S LCD mode only uses the "TX Unit", which leaves "RX Unit" for other purpose) // So the interrupt should also be able to share with other functionality - int isr_flags = LCD_I80_INTR_ALLOC_FLAGS | ESP_INTR_FLAG_SHARED; + int isr_flags = LCD_I80_INTR_ALLOC_FLAGS | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED; ret = esp_intr_alloc_intrstatus(lcd_periph_signals.buses[bus->bus_id].irq_id, isr_flags, (uint32_t)i2s_ll_get_intr_status_reg(bus->hal.dev), I2S_LL_EVENT_TX_EOF, lcd_default_isr_handler, bus, &bus->intr); @@ -263,7 +263,7 @@ esp_err_t esp_lcd_new_panel_io_i80(esp_lcd_i80_bus_handle_t bus, const esp_lcd_p // because we set the I2S's left channel data same to right channel, so f_pclk = f_i2s/pclk_div/2 uint32_t pclk_prescale = bus->resolution_hz / 2 / io_config->pclk_hz; ESP_GOTO_ON_FALSE(pclk_prescale > 0 && pclk_prescale <= I2S_LL_BCK_MAX_PRESCALE, ESP_ERR_NOT_SUPPORTED, err, TAG, - "prescaler can't satisfy PCLK clock %u", io_config->pclk_hz); + "prescaler can't satisfy PCLK clock %"PRIu32"Hz", io_config->pclk_hz); i80_device = heap_caps_calloc(1, sizeof(lcd_panel_io_i80_t) + io_config->trans_queue_depth * sizeof(lcd_i80_trans_descriptor_t), LCD_I80_MEM_ALLOC_CAPS); ESP_GOTO_ON_FALSE(i80_device, ESP_ERR_NO_MEM, err, TAG, "no mem for i80 panel io"); // create two queues for i80 device @@ -302,7 +302,7 @@ esp_err_t esp_lcd_new_panel_io_i80(esp_lcd_i80_bus_handle_t bus, const esp_lcd_p gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[io_config->cs_gpio_num], PIN_FUNC_GPIO); } *ret_io = &(i80_device->base); - ESP_LOGD(TAG, "new i80 lcd panel io @%p on bus(%d), pclk=%uHz", i80_device, bus->bus_id, i80_device->pclk_hz); + ESP_LOGD(TAG, "new i80 lcd panel io @%p on bus(%d), pclk=%"PRIu32"Hz", i80_device, bus->bus_id, i80_device->pclk_hz); return ESP_OK; err: diff --git a/components/esp_lcd/src/esp_lcd_panel_io_i80.c b/components/esp_lcd/src/esp_lcd_panel_io_i80.c index a015148e31..f5e42e0836 100644 --- a/components/esp_lcd/src/esp_lcd_panel_io_i80.c +++ b/components/esp_lcd/src/esp_lcd_panel_io_i80.c @@ -153,7 +153,7 @@ esp_err_t esp_lcd_new_i80_bus(const esp_lcd_i80_bus_config_t *bus_config, esp_lc ESP_GOTO_ON_ERROR(ret, err, TAG, "select periph clock %d failed", bus_config->clk_src); // install interrupt service, (LCD peripheral shares the same interrupt source with Camera peripheral with different mask) // interrupt is disabled by default - int isr_flags = LCD_I80_INTR_ALLOC_FLAGS | ESP_INTR_FLAG_SHARED; + int isr_flags = LCD_I80_INTR_ALLOC_FLAGS | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED; ret = esp_intr_alloc_intrstatus(lcd_periph_signals.buses[bus_id].irq_id, isr_flags, (uint32_t)lcd_ll_get_interrupt_status_reg(bus->hal.dev), LCD_LL_EVENT_TRANS_DONE, lcd_default_isr_handler, bus, &bus->intr); @@ -249,7 +249,7 @@ esp_err_t esp_lcd_new_panel_io_i80(esp_lcd_i80_bus_handle_t bus, const esp_lcd_p // check if pixel clock setting is valid uint32_t pclk_prescale = bus->resolution_hz / io_config->pclk_hz; ESP_GOTO_ON_FALSE(pclk_prescale > 0 && pclk_prescale <= LCD_LL_PCLK_DIV_MAX, ESP_ERR_NOT_SUPPORTED, err, TAG, - "prescaler can't satisfy PCLK clock %u", io_config->pclk_hz); + "prescaler can't satisfy PCLK clock %"PRIu32"Hz", io_config->pclk_hz); i80_device = heap_caps_calloc(1, sizeof(lcd_panel_io_i80_t) + io_config->trans_queue_depth * sizeof(lcd_i80_trans_descriptor_t), LCD_I80_MEM_ALLOC_CAPS); ESP_GOTO_ON_FALSE(i80_device, ESP_ERR_NO_MEM, err, TAG, "no mem for i80 panel io"); // create two queues for i80 device diff --git a/components/esp_lcd/src/esp_lcd_panel_nt35510.c b/components/esp_lcd/src/esp_lcd_panel_nt35510.c index 8a66a5a77b..0f4a446483 100644 --- a/components/esp_lcd/src/esp_lcd_panel_nt35510.c +++ b/components/esp_lcd/src/esp_lcd_panel_nt35510.c @@ -42,7 +42,7 @@ typedef struct { bool reset_level; int x_gap; int y_gap; - unsigned int bits_per_pixel; + uint8_t fb_bits_per_pixel; uint8_t madctl_val; // save current value of LCD_CMD_MADCTL register uint8_t colmod_cal; // save surrent value of LCD_CMD_COLMOD register } nt35510_panel_t; @@ -66,11 +66,11 @@ esp_err_t esp_lcd_new_panel_nt35510(const esp_lcd_panel_io_handle_t io, const es ESP_GOTO_ON_ERROR(gpio_config(&io_conf), err, TAG, "configure GPIO for RST line failed"); } - switch (panel_dev_config->color_space) { - case ESP_LCD_COLOR_SPACE_RGB: + switch (panel_dev_config->rgb_endian) { + case LCD_RGB_ENDIAN_RGB: nt35510->madctl_val = 0; break; - case ESP_LCD_COLOR_SPACE_BGR: + case LCD_RGB_ENDIAN_BGR: nt35510->madctl_val |= LCD_CMD_BGR_BIT; break; default: @@ -78,15 +78,20 @@ esp_err_t esp_lcd_new_panel_nt35510(const esp_lcd_panel_io_handle_t io, const es break; } + uint8_t fb_bits_per_pixel = 0; switch (panel_dev_config->bits_per_pixel) { - case 16: + case 16: // RGB565 nt35510->colmod_cal = 0x55; + fb_bits_per_pixel = 16; break; - case 18: + case 18: // RGB666 nt35510->colmod_cal = 0x66; + // each color component (R/G/B) should occupy the 6 high bits of a byte, which means 3 full bytes are required for a pixel + fb_bits_per_pixel = 24; break; - case 24: + case 24: // RGB888 nt35510->colmod_cal = 0x77; + fb_bits_per_pixel = 24; break; default: ESP_GOTO_ON_FALSE(false, ESP_ERR_NOT_SUPPORTED, err, TAG, "unsupported pixel width"); @@ -94,7 +99,7 @@ esp_err_t esp_lcd_new_panel_nt35510(const esp_lcd_panel_io_handle_t io, const es } nt35510->io = io; - nt35510->bits_per_pixel = panel_dev_config->bits_per_pixel; + nt35510->fb_bits_per_pixel = fb_bits_per_pixel; nt35510->reset_gpio_num = panel_dev_config->reset_gpio_num; nt35510->reset_level = panel_dev_config->flags.reset_active_high; nt35510->base.del = panel_nt35510_del; @@ -207,7 +212,7 @@ static esp_err_t panel_nt35510_draw_bitmap(esp_lcd_panel_t *panel, int x_start, (y_end - 1) & 0xFF, }, 2); // transfer frame buffer - size_t len = (x_end - x_start) * (y_end - y_start) * nt35510->bits_per_pixel / 8; + size_t len = (x_end - x_start) * (y_end - y_start) * nt35510->fb_bits_per_pixel / 8; esp_lcd_panel_io_tx_color(io, LCD_CMD_RAMWR << 8, color_data, len); return ESP_OK; diff --git a/components/esp_lcd/src/esp_lcd_panel_ssd1306.c b/components/esp_lcd/src/esp_lcd_panel_ssd1306.c index 494f319483..86d73bfde8 100644 --- a/components/esp_lcd/src/esp_lcd_panel_ssd1306.c +++ b/components/esp_lcd/src/esp_lcd_panel_ssd1306.c @@ -66,7 +66,6 @@ esp_err_t esp_lcd_new_panel_ssd1306(const esp_lcd_panel_io_handle_t io, const es esp_err_t ret = ESP_OK; ssd1306_panel_t *ssd1306 = NULL; ESP_GOTO_ON_FALSE(io && panel_dev_config && ret_panel, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument"); - ESP_GOTO_ON_FALSE(panel_dev_config->color_space == ESP_LCD_COLOR_SPACE_MONOCHROME, ESP_ERR_INVALID_ARG, err, TAG, "support monochrome only"); ESP_GOTO_ON_FALSE(panel_dev_config->bits_per_pixel == 1, ESP_ERR_INVALID_ARG, err, TAG, "bpp must be 1"); ssd1306 = calloc(1, sizeof(ssd1306_panel_t)); ESP_GOTO_ON_FALSE(ssd1306, ESP_ERR_NO_MEM, err, TAG, "no mem for ssd1306 panel"); diff --git a/components/esp_lcd/src/esp_lcd_panel_st7789.c b/components/esp_lcd/src/esp_lcd_panel_st7789.c index eb9364dd26..60ea7ec40b 100644 --- a/components/esp_lcd/src/esp_lcd_panel_st7789.c +++ b/components/esp_lcd/src/esp_lcd_panel_st7789.c @@ -42,7 +42,7 @@ typedef struct { bool reset_level; int x_gap; int y_gap; - unsigned int bits_per_pixel; + uint8_t fb_bits_per_pixel; uint8_t madctl_val; // save current value of LCD_CMD_MADCTL register uint8_t colmod_cal; // save surrent value of LCD_CMD_COLMOD register } st7789_panel_t; @@ -66,11 +66,11 @@ esp_err_t esp_lcd_new_panel_st7789(const esp_lcd_panel_io_handle_t io, const esp ESP_GOTO_ON_ERROR(gpio_config(&io_conf), err, TAG, "configure GPIO for RST line failed"); } - switch (panel_dev_config->color_space) { - case ESP_LCD_COLOR_SPACE_RGB: + switch (panel_dev_config->rgb_endian) { + case LCD_RGB_ENDIAN_RGB: st7789->madctl_val = 0; break; - case ESP_LCD_COLOR_SPACE_BGR: + case LCD_RGB_ENDIAN_BGR: st7789->madctl_val |= LCD_CMD_BGR_BIT; break; default: @@ -78,12 +78,16 @@ esp_err_t esp_lcd_new_panel_st7789(const esp_lcd_panel_io_handle_t io, const esp break; } + uint8_t fb_bits_per_pixel = 0; switch (panel_dev_config->bits_per_pixel) { - case 16: + case 16: // RGB565 st7789->colmod_cal = 0x55; + fb_bits_per_pixel = 16; break; - case 18: + case 18: // RGB666 st7789->colmod_cal = 0x66; + // each color component (R/G/B) should occupy the 6 high bits of a byte, which means 3 full bytes are required for a pixel + fb_bits_per_pixel = 24; break; default: ESP_GOTO_ON_FALSE(false, ESP_ERR_NOT_SUPPORTED, err, TAG, "unsupported pixel width"); @@ -91,7 +95,7 @@ esp_err_t esp_lcd_new_panel_st7789(const esp_lcd_panel_io_handle_t io, const esp } st7789->io = io; - st7789->bits_per_pixel = panel_dev_config->bits_per_pixel; + st7789->fb_bits_per_pixel = fb_bits_per_pixel; st7789->reset_gpio_num = panel_dev_config->reset_gpio_num; st7789->reset_level = panel_dev_config->flags.reset_active_high; st7789->base.del = panel_st7789_del; @@ -191,7 +195,7 @@ static esp_err_t panel_st7789_draw_bitmap(esp_lcd_panel_t *panel, int x_start, i (y_end - 1) & 0xFF, }, 4); // transfer frame buffer - size_t len = (x_end - x_start) * (y_end - y_start) * st7789->bits_per_pixel / 8; + size_t len = (x_end - x_start) * (y_end - y_start) * st7789->fb_bits_per_pixel / 8; esp_lcd_panel_io_tx_color(io, LCD_CMD_RAMWR, color_data, len); return ESP_OK; diff --git a/components/esp_lcd/src/esp_lcd_rgb_panel.c b/components/esp_lcd/src/esp_lcd_rgb_panel.c index 61abf5f1a9..9979b2fbcc 100644 --- a/components/esp_lcd/src/esp_lcd_rgb_panel.c +++ b/components/esp_lcd/src/esp_lcd_rgb_panel.c @@ -83,7 +83,8 @@ struct esp_rgb_panel_t { int panel_id; // LCD panel ID lcd_hal_context_t hal; // Hal layer object size_t data_width; // Number of data lines - size_t bits_per_pixel; // Color depth, in bpp + size_t fb_bits_per_pixel; // Frame buffer color depth, in bpp + size_t output_bits_per_pixel; // Color depth seen from the output data line. Default to fb_bits_per_pixel, but can be changed by YUV-RGB conversion size_t sram_trans_align; // Alignment for framebuffer that allocated in SRAM size_t psram_trans_align; // Alignment for framebuffer that allocated in PSRAM int disp_gpio_num; // Display control GPIO, which is used to perform action like "disp_off" @@ -114,6 +115,7 @@ struct esp_rgb_panel_t { uint32_t no_fb: 1; // No frame buffer allocated in the driver uint32_t fb_in_psram: 1; // Whether the frame buffer is in PSRAM uint32_t need_update_pclk: 1; // Whether to update the PCLK before start a new transaction + uint32_t need_restart: 1; // Whether to restart the LCD controller and the DMA uint32_t bb_invalidate_cache: 1; // Whether to do cache invalidation in bounce buffer mode } flags; dma_descriptor_t *dma_links[2]; // fbs[0] <-> dma_links[0], fbs[1] <-> dma_links[1] @@ -220,13 +222,13 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf #endif // bpp defaults to the number of data lines, but for serial RGB interface, they're not equal - size_t bits_per_pixel = rgb_panel_config->data_width; + size_t fb_bits_per_pixel = rgb_panel_config->data_width; if (rgb_panel_config->bits_per_pixel) { // override bpp if it's set - bits_per_pixel = rgb_panel_config->bits_per_pixel; + fb_bits_per_pixel = rgb_panel_config->bits_per_pixel; } // calculate buffer size - size_t fb_size = rgb_panel_config->timings.h_res * rgb_panel_config->timings.v_res * bits_per_pixel / 8; - size_t bb_size = rgb_panel_config->bounce_buffer_size_px * bits_per_pixel / 8; + size_t fb_size = rgb_panel_config->timings.h_res * rgb_panel_config->timings.v_res * fb_bits_per_pixel / 8; + size_t bb_size = rgb_panel_config->bounce_buffer_size_px * fb_bits_per_pixel / 8; if (bb_size) { // we want the bounce can always end in the second buffer ESP_GOTO_ON_FALSE(fb_size % (2 * bb_size) == 0, ESP_ERR_INVALID_ARG, err, TAG, @@ -278,7 +280,7 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf rgb_panel->lcd_clk_flags |= LCD_HAL_PCLK_FLAG_ALLOW_EQUAL_SYSCLK; } // install interrupt service, (LCD peripheral shares the interrupt source with Camera by different mask) - int isr_flags = LCD_RGB_INTR_ALLOC_FLAGS | ESP_INTR_FLAG_SHARED; + int isr_flags = LCD_RGB_INTR_ALLOC_FLAGS | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED; ret = esp_intr_alloc_intrstatus(lcd_periph_signals.panels[panel_id].irq_id, isr_flags, (uint32_t)lcd_ll_get_interrupt_status_reg(rgb_panel->hal.dev), LCD_LL_EVENT_VSYNC_END, lcd_default_isr_handler, rgb_panel, &rgb_panel->intr); @@ -297,7 +299,8 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf memcpy(rgb_panel->data_gpio_nums, rgb_panel_config->data_gpio_nums, SOC_LCD_RGB_DATA_WIDTH); rgb_panel->timings = rgb_panel_config->timings; rgb_panel->data_width = rgb_panel_config->data_width; - rgb_panel->bits_per_pixel = bits_per_pixel; + rgb_panel->fb_bits_per_pixel = fb_bits_per_pixel; + rgb_panel->output_bits_per_pixel = fb_bits_per_pixel; // by default, the output bpp is the same as the frame buffer bpp rgb_panel->disp_gpio_num = rgb_panel_config->disp_gpio_num; rgb_panel->flags.disp_en_level = !rgb_panel_config->flags.disp_active_low; rgb_panel->flags.no_fb = rgb_panel_config->flags.no_fb; @@ -360,6 +363,19 @@ esp_err_t esp_lcd_rgb_panel_set_pclk(esp_lcd_panel_handle_t panel, uint32_t freq return ESP_OK; } +esp_err_t esp_lcd_rgb_panel_restart(esp_lcd_panel_handle_t panel) +{ + ESP_RETURN_ON_FALSE(panel, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + esp_rgb_panel_t *rgb_panel = __containerof(panel, esp_rgb_panel_t, base); + ESP_RETURN_ON_FALSE(rgb_panel->flags.stream_mode, ESP_ERR_INVALID_STATE, TAG, "not in stream mode"); + + // the underlying restart job will be done in the `LCD_LL_EVENT_VSYNC_END` event handler + portENTER_CRITICAL(&rgb_panel->spinlock); + rgb_panel->flags.need_restart = true; + portEXIT_CRITICAL(&rgb_panel->spinlock); + return ESP_OK; +} + esp_err_t esp_lcd_rgb_panel_get_frame_buffer(esp_lcd_panel_handle_t panel, uint32_t fb_num, void **fb0, ...) { ESP_RETURN_ON_FALSE(panel, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); @@ -387,6 +403,57 @@ esp_err_t esp_lcd_rgb_panel_refresh(esp_lcd_panel_handle_t panel) return ESP_OK; } +esp_err_t esp_lcd_rgb_panel_set_yuv_conversion(esp_lcd_panel_handle_t panel, const esp_lcd_yuv_conv_config_t *config) +{ + ESP_RETURN_ON_FALSE(panel, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + esp_rgb_panel_t *rgb_panel = __containerof(panel, esp_rgb_panel_t, base); + lcd_hal_context_t *hal = &rgb_panel->hal; + bool en_conversion = config != NULL; + + // bits per pixel for different YUV sample + const uint8_t bpp_yuv[] = { + [LCD_YUV_SAMPLE_422] = 16, + [LCD_YUV_SAMPLE_420] = 12, + [LCD_YUV_SAMPLE_411] = 12, + }; + + if (en_conversion) { + if (memcmp(&config->src, &config->dst, sizeof(config->src)) == 0) { + ESP_RETURN_ON_FALSE(false, ESP_ERR_INVALID_ARG, TAG, "conversion source and destination are the same"); + } + + if (config->src.color_space == LCD_COLOR_SPACE_YUV && config->dst.color_space == LCD_COLOR_SPACE_RGB) { // YUV->RGB + lcd_ll_set_convert_mode_yuv_to_rgb(hal->dev, config->src.yuv_sample); + // Note, the RGB->YUV conversion only support RGB565 + rgb_panel->output_bits_per_pixel = 16; + } else if (config->src.color_space == LCD_COLOR_SPACE_RGB && config->dst.color_space == LCD_COLOR_SPACE_YUV) { // RGB->YUV + lcd_ll_set_convert_mode_rgb_to_yuv(hal->dev, config->dst.yuv_sample); + rgb_panel->output_bits_per_pixel = bpp_yuv[config->dst.yuv_sample]; + } else if (config->src.color_space == LCD_COLOR_SPACE_YUV && config->dst.color_space == LCD_COLOR_SPACE_YUV) { // YUV->YUV + lcd_ll_set_convert_mode_yuv_to_yuv(hal->dev, config->src.yuv_sample, config->dst.yuv_sample); + rgb_panel->output_bits_per_pixel = bpp_yuv[config->dst.yuv_sample]; + } else { + ESP_RETURN_ON_FALSE(false, ESP_ERR_NOT_SUPPORTED, TAG, "unsupported conversion mode"); + } + + // set conversion standard + lcd_ll_set_yuv_convert_std(hal->dev, config->std); + // set conversion data width + lcd_ll_set_convert_data_width(hal->dev, rgb_panel->data_width); + // set color range + lcd_ll_set_input_color_range(hal->dev, config->src.color_range); + lcd_ll_set_output_color_range(hal->dev, config->dst.color_range); + } else { + // output bpp equals to frame buffer bpp + rgb_panel->output_bits_per_pixel = rgb_panel->fb_bits_per_pixel; + } + + // enable or disable RGB-YUV conversion + lcd_ll_enable_rgb_yuv_convert(hal->dev, en_conversion); + + return ESP_OK; +} + static esp_err_t rgb_panel_del(esp_lcd_panel_t *panel) { esp_rgb_panel_t *rgb_panel = __containerof(panel, esp_rgb_panel_t, base); @@ -425,7 +492,7 @@ static esp_err_t rgb_panel_init(esp_lcd_panel_t *panel) // configure blank region timing lcd_ll_set_blank_cycles(rgb_panel->hal.dev, 1, 1); // RGB panel always has a front and back blank (porch region) lcd_ll_set_horizontal_timing(rgb_panel->hal.dev, rgb_panel->timings.hsync_pulse_width, - rgb_panel->timings.hsync_back_porch, rgb_panel->timings.h_res * rgb_panel->bits_per_pixel / rgb_panel->data_width, + rgb_panel->timings.hsync_back_porch, rgb_panel->timings.h_res * rgb_panel->output_bits_per_pixel / rgb_panel->data_width, rgb_panel->timings.hsync_front_porch); lcd_ll_set_vertical_timing(rgb_panel->hal.dev, rgb_panel->timings.vsync_pulse_width, rgb_panel->timings.vsync_back_porch, rgb_panel->timings.v_res, @@ -444,7 +511,7 @@ static esp_err_t rgb_panel_init(esp_lcd_panel_t *panel) if (rgb_panel->flags.stream_mode) { lcd_rgb_panel_start_transmission(rgb_panel); } - ESP_LOGD(TAG, "rgb panel(%d) start, pclk=%uHz", rgb_panel->panel_id, rgb_panel->timings.pclk_hz); + ESP_LOGD(TAG, "rgb panel(%d) start, pclk=%"PRIu32"Hz", rgb_panel->panel_id, rgb_panel->timings.pclk_hz); return ret; } @@ -500,7 +567,7 @@ static esp_err_t rgb_panel_draw_bitmap(esp_lcd_panel_t *panel, int x_start, int y_end = MIN(y_end, v_res); } - int bytes_per_pixel = rgb_panel->bits_per_pixel / 8; + int bytes_per_pixel = rgb_panel->fb_bits_per_pixel / 8; int pixels_per_line = rgb_panel->timings.h_res; uint32_t bytes_per_line = bytes_per_pixel * pixels_per_line; uint8_t *fb = rgb_panel->fbs[rgb_panel->cur_fb_index]; @@ -862,7 +929,7 @@ static esp_err_t lcd_rgb_panel_select_clock_src(esp_rgb_panel_t *panel, lcd_cloc static IRAM_ATTR bool lcd_rgb_panel_fill_bounce_buffer(esp_rgb_panel_t *panel, uint8_t *buffer) { bool need_yield = false; - int bytes_per_pixel = panel->bits_per_pixel / 8; + int bytes_per_pixel = panel->fb_bits_per_pixel / 8; if (panel->flags.no_fb) { if (panel->on_bounce_empty) { // We don't have a frame buffer here; we need to call a callback to refill the bounce buffer @@ -943,16 +1010,15 @@ static esp_err_t lcd_rgb_panel_create_trans_link(esp_rgb_panel_t *panel) } } -#if CONFIG_LCD_RGB_RESTART_IN_VSYNC // On restart, the data sent to the LCD peripheral needs to start LCD_FIFO_PRESERVE_SIZE_PX pixels after the FB start // so we use a dedicated DMA node to restart the DMA transaction + // see also `lcd_rgb_panel_try_restart_transmission` memcpy(&panel->dma_restart_node, &panel->dma_nodes[0], sizeof(panel->dma_restart_node)); int restart_skip_bytes = LCD_FIFO_PRESERVE_SIZE_PX * sizeof(uint16_t); uint8_t *p = (uint8_t *)panel->dma_restart_node.buffer; panel->dma_restart_node.buffer = &p[restart_skip_bytes]; panel->dma_restart_node.dw0.length -= restart_skip_bytes; panel->dma_restart_node.dw0.size -= restart_skip_bytes; -#endif // alloc DMA channel and connect to LCD peripheral gdma_channel_alloc_config_t dma_chan_config = { @@ -977,9 +1043,31 @@ static esp_err_t lcd_rgb_panel_create_trans_link(esp_rgb_panel_t *panel) return ESP_OK; } -#if CONFIG_LCD_RGB_RESTART_IN_VSYNC -static IRAM_ATTR void lcd_rgb_panel_restart_transmission_in_isr(esp_rgb_panel_t *panel) +// reset the GDMA channel every VBlank to stop permanent desyncs from happening. +// Note that this fix can lead to single-frame desyncs itself, as in: if this interrupt +// is late enough, the display will shift as the LCD controller already read out the +// first data bytes, and resetting DMA will re-send those. However, the single-frame +// desync this leads to is preferable to the permanent desync that could otherwise +// happen. It's also not super-likely as this interrupt has the entirety of the VBlank +// time to reset DMA. +static IRAM_ATTR void lcd_rgb_panel_try_restart_transmission(esp_rgb_panel_t *panel) { + bool do_restart = false; +#if CONFIG_LCD_RGB_RESTART_IN_VSYNC + do_restart = true; +#else + portENTER_CRITICAL_ISR(&panel->spinlock); + if (panel->flags.need_restart) { + panel->flags.need_restart = false; + do_restart = true; + } + portEXIT_CRITICAL_ISR(&panel->spinlock); +#endif // CONFIG_LCD_RGB_RESTART_IN_VSYNC + + if (!do_restart) { + return; + } + if (panel->bb_size) { // Catch de-synced frame buffer and reset if needed. if (panel->bounce_pos_px > panel->bb_size) { @@ -1002,7 +1090,6 @@ static IRAM_ATTR void lcd_rgb_panel_restart_transmission_in_isr(esp_rgb_panel_t } } } -#endif static void lcd_rgb_panel_start_transmission(esp_rgb_panel_t *rgb_panel) { @@ -1056,16 +1143,8 @@ IRAM_ATTR static void lcd_default_isr_handler(void *args) lcd_rgb_panel_try_update_pclk(rgb_panel); if (rgb_panel->flags.stream_mode) { -#if CONFIG_LCD_RGB_RESTART_IN_VSYNC - // reset the GDMA channel every VBlank to stop permanent desyncs from happening. - // Note that this fix can lead to single-frame desyncs itself, as in: if this interrupt - // is late enough, the display will shift as the LCD controller already read out the - // first data bytes, and resetting DMA will re-send those. However, the single-frame - // desync this leads to is preferable to the permanent desync that could otherwise - // happen. It's also not super-likely as this interrupt has the entirety of the VBlank - // time to reset DMA. - lcd_rgb_panel_restart_transmission_in_isr(rgb_panel); -#endif + // check whether to restart the transmission + lcd_rgb_panel_try_restart_transmission(rgb_panel); } } diff --git a/components/esp_lcd/test_apps/i2c_lcd/main/test_i2c_lcd_panel.c b/components/esp_lcd/test_apps/i2c_lcd/main/test_i2c_lcd_panel.c index 52d9fe95e6..f0653a286a 100644 --- a/components/esp_lcd/test_apps/i2c_lcd/main/test_i2c_lcd_panel.c +++ b/components/esp_lcd/test_apps/i2c_lcd/main/test_i2c_lcd_panel.c @@ -50,7 +50,6 @@ TEST_CASE("lcd_panel_with_i2c_interface_(ssd1306)", "[lcd]") esp_lcd_panel_handle_t panel_handle = NULL; esp_lcd_panel_dev_config_t panel_config = { .bits_per_pixel = 1, - .color_space = ESP_LCD_COLOR_SPACE_MONOCHROME, .reset_gpio_num = -1, }; TEST_ESP_OK(esp_lcd_new_panel_ssd1306(io_handle, &panel_config, &panel_handle)); diff --git a/components/esp_lcd/test_apps/i80_lcd/main/test_i80_lcd_panel.c b/components/esp_lcd/test_apps/i80_lcd/main/test_i80_lcd_panel.c index b06da4e986..91d743b698 100644 --- a/components/esp_lcd/test_apps/i80_lcd/main/test_i80_lcd_panel.c +++ b/components/esp_lcd/test_apps/i80_lcd/main/test_i80_lcd_panel.c @@ -299,7 +299,7 @@ TEST_CASE("lcd_panel_i80_io_test", "[lcd]") esp_lcd_panel_handle_t panel_handle = NULL; esp_lcd_panel_dev_config_t panel_config = { .reset_gpio_num = TEST_LCD_RST_GPIO, - .color_space = ESP_LCD_COLOR_SPACE_RGB, + .rgb_endian = LCD_RGB_ENDIAN_RGB, .bits_per_pixel = 16, }; @@ -419,7 +419,7 @@ TEST_CASE("lcd_panel_with_i80_interface_(st7789, 8bits)", "[lcd]") esp_lcd_panel_handle_t panel_handle = NULL; esp_lcd_panel_dev_config_t panel_config = { .reset_gpio_num = TEST_LCD_RST_GPIO, - .color_space = ESP_LCD_COLOR_SPACE_RGB, + .rgb_endian = LCD_RGB_ENDIAN_RGB, .bits_per_pixel = 16, }; TEST_ESP_OK(esp_lcd_new_panel_st7789(io_handle, &panel_config, &panel_handle)); diff --git a/components/esp_lcd/test_apps/rgb_lcd/CMakeLists.txt b/components/esp_lcd/test_apps/rgb_lcd/CMakeLists.txt index 1993e30336..15771966a0 100644 --- a/components/esp_lcd/test_apps/rgb_lcd/CMakeLists.txt +++ b/components/esp_lcd/test_apps/rgb_lcd/CMakeLists.txt @@ -4,6 +4,9 @@ cmake_minimum_required(VERSION 3.16) include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(rgb_lcd_panel_test) +target_add_binary_data(rgb_lcd_panel_test.elf "resources/pictures/hello.yuv" BINARY) +target_add_binary_data(rgb_lcd_panel_test.elf "resources/pictures/world.yuv" BINARY) + if(CONFIG_COMPILER_DUMP_RTL_FILES) add_custom_target(check_test_app_sections ALL COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py diff --git a/components/esp_lcd/test_apps/rgb_lcd/main/CMakeLists.txt b/components/esp_lcd/test_apps/rgb_lcd/main/CMakeLists.txt index f694abfeab..3f1453be33 100644 --- a/components/esp_lcd/test_apps/rgb_lcd/main/CMakeLists.txt +++ b/components/esp_lcd/test_apps/rgb_lcd/main/CMakeLists.txt @@ -1,8 +1,11 @@ set(srcs "test_app_main.c" "test_rgb_panel.c") +if(CONFIG_SOC_LCD_SUPPORT_RGB_YUV_CONV) + list(APPEND srcs "test_yuv_rgb_conv.c") +endif() + # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} WHOLE_ARCHIVE) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/components/esp_lcd/test_apps/rgb_lcd/main/test_rgb_panel.c b/components/esp_lcd/test_apps/rgb_lcd/main/test_rgb_panel.c index 687d5077a5..a10d2e215c 100644 --- a/components/esp_lcd/test_apps/rgb_lcd/main/test_rgb_panel.c +++ b/components/esp_lcd/test_apps/rgb_lcd/main/test_rgb_panel.c @@ -5,6 +5,7 @@ */ #include #include +#include #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "unity.h" @@ -213,6 +214,31 @@ TEST_CASE("lcd_rgb_panel_update_pclk", "[lcd]") free(img); } +TEST_CASE("lcd_rgb_panel_restart", "[lcd]") +{ + uint8_t *img = malloc(TEST_IMG_SIZE); + TEST_ASSERT_NOT_NULL(img); + + printf("initialize RGB panel with stream mode\r\n"); + esp_lcd_panel_handle_t panel_handle = test_rgb_panel_initialization(16, 16, 0, false, NULL, NULL); + printf("flush one clock block to the LCD\r\n"); + uint8_t color_byte = esp_random() & 0xFF; + int x_start = esp_random() % (TEST_LCD_H_RES - 100); + int y_start = esp_random() % (TEST_LCD_V_RES - 100); + memset(img, color_byte, TEST_IMG_SIZE); + esp_lcd_panel_draw_bitmap(panel_handle, x_start, y_start, x_start + 100, y_start + 100, img); + printf("The LCD driver should keep flushing the color block in the background (as it's in stream mode)\r\n"); + vTaskDelay(pdMS_TO_TICKS(1000)); + + printf("Restart the DMA transmission in the background\r\n"); + TEST_ESP_OK(esp_lcd_rgb_panel_restart(panel_handle)); + vTaskDelay(pdMS_TO_TICKS(1000)); + + printf("delete RGB panel\r\n"); + TEST_ESP_OK(esp_lcd_panel_del(panel_handle)); + free(img); +} + TEST_CASE("lcd_rgb_panel_rotate", "[lcd]") { const int w = 200; @@ -281,7 +307,7 @@ TEST_CASE("lcd_rgb_panel_iram_safe", "[lcd]") printf("disable the cache for a while\r\n"); test_disable_flash_cache(); printf("the RGB ISR handle should keep working while the flash cache is disabled\r\n"); - printf("callback calls: %d\r\n", callback_calls); + printf("callback calls: %"PRIu32"\r\n", callback_calls); TEST_ASSERT(callback_calls > 2); printf("delete RGB panel\r\n"); diff --git a/components/esp_lcd/test_apps/rgb_lcd/main/test_yuv_rgb_conv.c b/components/esp_lcd/test_apps/rgb_lcd/main/test_yuv_rgb_conv.c new file mode 100644 index 0000000000..ce219a030a --- /dev/null +++ b/components/esp_lcd/test_apps/rgb_lcd/main/test_yuv_rgb_conv.c @@ -0,0 +1,105 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "unity.h" +#include "esp_lcd_panel_rgb.h" +#include "esp_lcd_panel_ops.h" +#include "esp_random.h" +#include "esp_timer.h" +#include "esp_attr.h" +#include "spi_flash_mmap.h" +#include "test_rgb_board.h" + +#define TEST_IMG_SIZE (320 * 320 * sizeof(uint16_t)) + +// YUV images are embedded in the firmware binary +extern const uint8_t image_hello_yuv_start[] asm("_binary_hello_yuv_start"); +extern const uint8_t image_hello_yuv_end[] asm("_binary_hello_yuv_end"); +extern const uint8_t image_world_yuv_start[] asm("_binary_world_yuv_start"); +extern const uint8_t image_world_yuv_end[] asm("_binary_world_yuv_end"); + +TEST_CASE("lcd_rgb_panel_yuv422_conversion", "[lcd]") +{ + esp_lcd_panel_handle_t panel_handle = NULL; + esp_lcd_rgb_panel_config_t panel_config = { + .data_width = 16, + .psram_trans_align = 64, + .bits_per_pixel = 16, // YUV422: 16bits per pixel + .clk_src = LCD_CLK_SRC_DEFAULT, + .disp_gpio_num = TEST_LCD_DISP_EN_GPIO, + .pclk_gpio_num = TEST_LCD_PCLK_GPIO, + .vsync_gpio_num = TEST_LCD_VSYNC_GPIO, + .hsync_gpio_num = TEST_LCD_HSYNC_GPIO, + .de_gpio_num = TEST_LCD_DE_GPIO, + .data_gpio_nums = { + TEST_LCD_DATA0_GPIO, + TEST_LCD_DATA1_GPIO, + TEST_LCD_DATA2_GPIO, + TEST_LCD_DATA3_GPIO, + TEST_LCD_DATA4_GPIO, + TEST_LCD_DATA5_GPIO, + TEST_LCD_DATA6_GPIO, + TEST_LCD_DATA7_GPIO, + TEST_LCD_DATA8_GPIO, + TEST_LCD_DATA9_GPIO, + TEST_LCD_DATA10_GPIO, + TEST_LCD_DATA11_GPIO, + TEST_LCD_DATA12_GPIO, + TEST_LCD_DATA13_GPIO, + TEST_LCD_DATA14_GPIO, + TEST_LCD_DATA15_GPIO, + }, + .timings = { + .pclk_hz = TEST_LCD_PIXEL_CLOCK_HZ, + .h_res = TEST_LCD_H_RES, + .v_res = TEST_LCD_V_RES, + .hsync_back_porch = 68, + .hsync_front_porch = 20, + .hsync_pulse_width = 5, + .vsync_back_porch = 18, + .vsync_front_porch = 4, + .vsync_pulse_width = 1, + }, + .flags.fb_in_psram = 1, // allocate frame buffer in PSRAM + }; + + printf("Create RGB LCD panel\r\n"); + TEST_ESP_OK(esp_lcd_new_rgb_panel(&panel_config, &panel_handle)); + TEST_ESP_OK(esp_lcd_panel_reset(panel_handle)); + + printf("Set YUV-RGB conversion profile\r\n"); + esp_lcd_yuv_conv_config_t conv_config = { + .std = LCD_YUV_CONV_STD_BT601, + .src = { + .color_range = LCD_COLOR_RANGE_FULL, + .color_space = LCD_COLOR_SPACE_RGB, + }, + .dst = { + .color_range = LCD_COLOR_RANGE_FULL, + .color_space = LCD_COLOR_SPACE_RGB, + }, + }; + TEST_ESP_ERR(ESP_ERR_INVALID_ARG, esp_lcd_rgb_panel_set_yuv_conversion(panel_handle, &conv_config)); + + conv_config.src.color_space = LCD_COLOR_SPACE_YUV; + conv_config.src.yuv_sample = LCD_YUV_SAMPLE_422; + TEST_ESP_OK(esp_lcd_rgb_panel_set_yuv_conversion(panel_handle, &conv_config)); + + TEST_ESP_OK(esp_lcd_panel_init(panel_handle)); + + printf("Draw YUV images\r\n"); + for (int i = 0; i < 4; i++) { + TEST_ESP_OK(esp_lcd_panel_draw_bitmap(panel_handle, 0, 0, 320, 320, image_hello_yuv_start)); + vTaskDelay(pdMS_TO_TICKS(1000)); + TEST_ESP_OK(esp_lcd_panel_draw_bitmap(panel_handle, 0, 0, 320, 320, image_world_yuv_start)); + vTaskDelay(pdMS_TO_TICKS(1000)); + } + + TEST_ESP_OK(esp_lcd_panel_del(panel_handle)); +} diff --git a/components/esp_lcd/test_apps/rgb_lcd/resources/README.md b/components/esp_lcd/test_apps/rgb_lcd/resources/README.md new file mode 100644 index 0000000000..3c6ead6942 --- /dev/null +++ b/components/esp_lcd/test_apps/rgb_lcd/resources/README.md @@ -0,0 +1,5 @@ +# How to generate the YUV image from the PNG image + +```bash +ffmpeg -i hello.png -pix_fmt uyvy422 hello.yuv +``` diff --git a/components/esp_lcd/test_apps/rgb_lcd/resources/pictures/hello.png b/components/esp_lcd/test_apps/rgb_lcd/resources/pictures/hello.png new file mode 100644 index 0000000000..380298e8e4 Binary files /dev/null and b/components/esp_lcd/test_apps/rgb_lcd/resources/pictures/hello.png differ diff --git a/components/esp_lcd/test_apps/rgb_lcd/resources/pictures/hello.yuv b/components/esp_lcd/test_apps/rgb_lcd/resources/pictures/hello.yuv new file mode 100644 index 0000000000..73582c5f7c --- /dev/null +++ b/components/esp_lcd/test_apps/rgb_lcd/resources/pictures/hello.yuv @@ -0,0 +1 @@ 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\ No newline at end of file diff --git a/components/esp_lcd/test_apps/rgb_lcd/sdkconfig.ci.iram_safe b/components/esp_lcd/test_apps/rgb_lcd/sdkconfig.ci.iram_safe index 8f2476a932..d37073719a 100644 --- a/components/esp_lcd/test_apps/rgb_lcd/sdkconfig.ci.iram_safe +++ b/components/esp_lcd/test_apps/rgb_lcd/sdkconfig.ci.iram_safe @@ -1,5 +1,6 @@ CONFIG_COMPILER_DUMP_RTL_FILES=y CONFIG_LCD_RGB_ISR_IRAM_SAFE=y +CONFIG_GDMA_CTRL_FUNC_IN_IRAM=y CONFIG_COMPILER_OPTIMIZATION_NONE=y # silent the error check, as the error string are stored in rodata, causing RTL check failure CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT=y diff --git a/components/esp_lcd/test_apps/spi_lcd/main/test_spi_lcd_panel.c b/components/esp_lcd/test_apps/spi_lcd/main/test_spi_lcd_panel.c index 8a9a561e0b..382e2bc9ad 100644 --- a/components/esp_lcd/test_apps/spi_lcd/main/test_spi_lcd_panel.c +++ b/components/esp_lcd/test_apps/spi_lcd/main/test_spi_lcd_panel.c @@ -150,7 +150,7 @@ TEST_CASE("lcd_panel_with_8-line_spi_interface_(st7789)", "[lcd]") test_spi_lcd_common_initialize(&io_handle, NULL, NULL, 8, 8, true); esp_lcd_panel_dev_config_t panel_config = { .reset_gpio_num = TEST_LCD_RST_GPIO, - .color_space = ESP_LCD_COLOR_SPACE_RGB, + .rgb_endian = LCD_RGB_ENDIAN_RGB, .bits_per_pixel = 16, }; TEST_ESP_OK(esp_lcd_new_panel_st7789(io_handle, &panel_config, &panel_handle)); @@ -164,7 +164,7 @@ TEST_CASE("lcd_panel_with_8-line_spi_interface_(nt35510)", "[lcd]") test_spi_lcd_common_initialize(&io_handle, NULL, NULL, 16, 16, true); esp_lcd_panel_dev_config_t panel_config = { .reset_gpio_num = TEST_LCD_RST_GPIO, - .color_space = ESP_LCD_COLOR_SPACE_RGB, + .rgb_endian = LCD_RGB_ENDIAN_RGB, .bits_per_pixel = 16, }; TEST_ESP_OK(esp_lcd_new_panel_nt35510(io_handle, &panel_config, &panel_handle)); @@ -179,7 +179,7 @@ TEST_CASE("lcd_panel_with_1-line_spi_interface_(st7789)", "[lcd]") test_spi_lcd_common_initialize(&io_handle, NULL, NULL, 8, 8, false); esp_lcd_panel_dev_config_t panel_config = { .reset_gpio_num = TEST_LCD_RST_GPIO, - .color_space = ESP_LCD_COLOR_SPACE_RGB, + .rgb_endian = LCD_RGB_ENDIAN_RGB, .bits_per_pixel = 16, }; TEST_ESP_OK(esp_lcd_new_panel_st7789(io_handle, &panel_config, &panel_handle)); diff --git a/components/esp_netif/CMakeLists.txt b/components/esp_netif/CMakeLists.txt index 663a41648a..6eb4d85911 100644 --- a/components/esp_netif/CMakeLists.txt +++ b/components/esp_netif/CMakeLists.txt @@ -19,11 +19,6 @@ set(srcs set(include_dirs "include") set(priv_include_dirs "lwip" "private_include") -if(CONFIG_LWIP_SLIP_SUPPORT) -list(APPEND srcs - "lwip/esp_netif_lwip_slip.c") -endif() - if(CONFIG_PPP_SUPPORT) list(APPEND srcs "lwip/esp_netif_lwip_ppp.c") diff --git a/components/esp_netif/esp_netif_defaults.c b/components/esp_netif/esp_netif_defaults.c index 950772a720..a49c69d85b 100644 --- a/components/esp_netif/esp_netif_defaults.c +++ b/components/esp_netif/esp_netif_defaults.c @@ -32,5 +32,3 @@ const esp_netif_inherent_config_t _g_esp_netif_inherent_ap_config = ESP_NETIF_IN const esp_netif_inherent_config_t _g_esp_netif_inherent_eth_config = ESP_NETIF_INHERENT_DEFAULT_ETH(); const esp_netif_inherent_config_t _g_esp_netif_inherent_ppp_config = ESP_NETIF_INHERENT_DEFAULT_PPP(); - -const esp_netif_inherent_config_t _g_esp_netif_inherent_slip_config = ESP_NETIF_INHERENT_DEFAULT_SLIP(); diff --git a/components/esp_netif/include/esp_netif_defaults.h b/components/esp_netif/include/esp_netif_defaults.h index fdf7f32a76..90fbca16dd 100644 --- a/components/esp_netif/include/esp_netif_defaults.h +++ b/components/esp_netif/include/esp_netif_defaults.h @@ -72,18 +72,7 @@ extern "C" { }; -#define ESP_NETIF_INHERENT_DEFAULT_SLIP() \ - { \ - .flags = ESP_NETIF_FLAG_IS_SLIP, \ - ESP_COMPILER_DESIGNATED_INIT_AGGREGATE_TYPE_EMPTY(mac) \ - ESP_COMPILER_DESIGNATED_INIT_AGGREGATE_TYPE_EMPTY(ip_info) \ - .get_ip_event = 0, \ - .lost_ip_event = 0, \ - .if_key = "SLP_DEF", \ - .if_desc = "slip", \ - .route_prio = 16, \ - .bridge_info = NULL \ -}; + #define ESP_NETIF_INHERENT_DEFAULT_BR() \ { \ @@ -140,17 +129,6 @@ extern "C" { .stack = ESP_NETIF_NETSTACK_DEFAULT_PPP, \ } -/** -* @brief Default configuration reference of SLIP client -*/ -#define ESP_NETIF_DEFAULT_SLIP() \ - { \ - .base = ESP_NETIF_BASE_DEFAULT_SLIP, \ - .driver = NULL, \ - .stack = ESP_NETIF_NETSTACK_DEFAULT_SLIP, \ - } - - /** * @brief Default base config (esp-netif inherent) of WIFI STA */ @@ -173,11 +151,6 @@ extern "C" { */ #define ESP_NETIF_BASE_DEFAULT_PPP &_g_esp_netif_inherent_ppp_config -/** - * @brief Default base config (esp-netif inherent) of slip interface - */ -#define ESP_NETIF_BASE_DEFAULT_SLIP &_g_esp_netif_inherent_slip_config - #define ESP_NETIF_NETSTACK_DEFAULT_ETH _g_esp_netif_netstack_default_eth #define ESP_NETIF_NETSTACK_DEFAULT_BR _g_esp_netif_netstack_default_br @@ -186,7 +159,6 @@ extern "C" { #define ESP_NETIF_NETSTACK_DEFAULT_WIFI_AP _g_esp_netif_netstack_default_wifi_ap #endif #define ESP_NETIF_NETSTACK_DEFAULT_PPP _g_esp_netif_netstack_default_ppp -#define ESP_NETIF_NETSTACK_DEFAULT_SLIP _g_esp_netif_netstack_default_slip // // Include default network stacks configs @@ -201,7 +173,6 @@ extern const esp_netif_netstack_config_t *_g_esp_netif_netstack_default_wifi_sta extern const esp_netif_netstack_config_t *_g_esp_netif_netstack_default_wifi_ap; #endif extern const esp_netif_netstack_config_t *_g_esp_netif_netstack_default_ppp; -extern const esp_netif_netstack_config_t *_g_esp_netif_netstack_default_slip; // // Include default common configs inherent to esp-netif @@ -214,7 +185,6 @@ extern const esp_netif_inherent_config_t _g_esp_netif_inherent_ap_config; #endif extern const esp_netif_inherent_config_t _g_esp_netif_inherent_eth_config; extern const esp_netif_inherent_config_t _g_esp_netif_inherent_ppp_config; -extern const esp_netif_inherent_config_t _g_esp_netif_inherent_slip_config; #ifdef CONFIG_ESP_WIFI_SOFTAP_SUPPORT extern const esp_netif_ip_info_t _g_esp_netif_soft_ap_ip; diff --git a/components/esp_netif/include/esp_netif_slip.h b/components/esp_netif/include/esp_netif_slip.h deleted file mode 100644 index 5cad14ea28..0000000000 --- a/components/esp_netif/include/esp_netif_slip.h +++ /dev/null @@ -1,82 +0,0 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// - -#ifndef _ESP_NETIF_SLIP_H_ -#define _ESP_NETIF_SLIP_H_ - -#include "esp_netif.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @brief Configuration structure for SLIP network interface - * - */ -typedef struct esp_netif_slip_config { - esp_ip6_addr_t ip6_addr; /* Local IP6 address */ - -} esp_netif_slip_config_t; - - -/** @brief Sets common parameters for the supplied esp-netif. - * - * @param[in] esp_netif handle to slip esp-netif instance - * @param[in] config Pointer to SLIP netif configuration structure - * - * @return ESP_OK on success, ESP_ERR_ESP_NETIF_INVALID_PARAMS if netif null or not SLIP - */ -esp_err_t esp_netif_slip_set_params(esp_netif_t *netif, const esp_netif_slip_config_t *config); - -#if CONFIG_LWIP_IPV6 -/** @brief Sets IPV6 address for the supplied esp-netif. - * - * @param[in] netif handle to slip esp-netif instance - * @param[in] ipv6 IPv6 address of the SLIP interface - * - * @return ESP_OK on success, ESP_ERR_ESP_NETIF_INVALID_PARAMS if netif null or not SLIP - */ -esp_err_t esp_netif_slip_set_ipv6(esp_netif_t *netif, const esp_ip6_addr_t *ipv6); -#endif - -/** - * @brief Data path API to write raw packet ous the SLIP interface - * - * This API is typically used when implementing user defined methods - * - * @param[in] esp_netif handle to slip esp-netif instance - * @param[in] buffer pointer to the outgoing data - * @param[in] len length of the data - * - * @return - * - ESP_OK on success - */ -void esp_netif_lwip_slip_raw_output(esp_netif_t *netif, void *buffer, size_t len); - -/** - * @brief Fetch IP6 address attached to the SLIP interface - * - * @param[in] esp_netif handle to slip esp-netif instance - * @param[in] address index (unused) - * - * @return - * - pointer to the internal ip6 address object - */ -const esp_ip6_addr_t *esp_slip_get_ip6(esp_netif_t *slip_netif); - -#ifdef __cplusplus -} -#endif -#endif //_ESP_NETIF_SLIP_H_ diff --git a/components/esp_netif/include/esp_netif_types.h b/components/esp_netif/include/esp_netif_types.h index 3268f4732b..de7f7579fc 100644 --- a/components/esp_netif/include/esp_netif_types.h +++ b/components/esp_netif/include/esp_netif_types.h @@ -159,8 +159,7 @@ typedef enum esp_netif_flags { ESP_NETIF_FLAG_GARP = 1 << 3, ESP_NETIF_FLAG_EVENT_IP_MODIFIED = 1 << 4, ESP_NETIF_FLAG_IS_PPP = 1 << 5, - ESP_NETIF_FLAG_IS_SLIP = 1 << 6, - ESP_NETIF_FLAG_IS_BRIDGE = 1 << 7, + ESP_NETIF_FLAG_IS_BRIDGE = 1 << 6, } esp_netif_flags_t; typedef enum esp_netif_ip_event_type { diff --git a/components/esp_netif/include/lwip/esp_netif_net_stack.h b/components/esp_netif/include/lwip/esp_netif_net_stack.h index e908b96a60..52790d72ac 100644 --- a/components/esp_netif/include/lwip/esp_netif_net_stack.h +++ b/components/esp_netif/include/lwip/esp_netif_net_stack.h @@ -9,7 +9,6 @@ #include "esp_netif.h" #include "lwip/netif.h" #include "esp_netif_ppp.h" -#include "esp_netif_slip.h" #if defined(CONFIG_ESP_NETIF_TCPIP_LWIP) @@ -26,12 +25,6 @@ struct esp_netif_netstack_lwip_ppp_config { esp_netif_ppp_config_t ppp_events; }; -struct esp_netif_netstack_lwip_slip_config { - init_fn_t init_fn; - input_fn_t input_fn; - esp_netif_slip_config_t slip_config; -}; - // LWIP netif specific network stack configuration struct esp_netif_netstack_config { union { diff --git a/components/esp_netif/loopback/esp_netif_loopback.c b/components/esp_netif/loopback/esp_netif_loopback.c index 8418e9d28b..c328a37e5e 100644 --- a/components/esp_netif/loopback/esp_netif_loopback.c +++ b/components/esp_netif/loopback/esp_netif_loopback.c @@ -6,7 +6,6 @@ #include -#include "esp_netif_lwip_internal.h" #include "esp_netif.h" #include "esp_netif_private.h" diff --git a/components/esp_netif/lwip/esp_netif_lwip.c b/components/esp_netif/lwip/esp_netif_lwip.c index 049fd55e69..22f770869e 100644 --- a/components/esp_netif/lwip/esp_netif_lwip.c +++ b/components/esp_netif/lwip/esp_netif_lwip.c @@ -41,7 +41,6 @@ #endif // CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT #include "esp_netif_lwip_ppp.h" -#include "esp_netif_lwip_slip.h" #include "dhcpserver/dhcpserver.h" #include "dhcpserver/dhcpserver_options.h" #include "netif/dhcp_state.h" @@ -64,7 +63,7 @@ /** * @brief macros to check netif related data to evaluate interface type */ -#if CONFIG_PPP_SUPPORT || CONFIG_LWIP_SLIP_SUPPORT +#if CONFIG_PPP_SUPPORT #define _IS_NETIF_ANY_POINT2POINT_TYPE(netif) (netif->related_data && netif->related_data->is_point2point) #else #define _IS_NETIF_ANY_POINT2POINT_TYPE(netif) false @@ -255,7 +254,7 @@ static esp_netif_t* esp_netif_is_active(esp_netif_t *arg) */ static void esp_netif_set_default_netif_internal(esp_netif_t *esp_netif) { - if (_IS_NETIF_POINT2POINT_TYPE(esp_netif, PPP_LWIP_NETIF)) { + if (ESP_NETIF_IS_POINT2POINT_TYPE(esp_netif, PPP_LWIP_NETIF)) { #if CONFIG_PPP_SUPPORT esp_netif_ppp_set_default_netif(esp_netif->netif_handle); #endif @@ -450,7 +449,7 @@ esp_netif_t* esp_netif_get_handle_from_netif_impl(void *dev) void* esp_netif_get_netif_impl(esp_netif_t *esp_netif) { // get impl ptr only for vanilla lwip impl (ppp_pcb not supported) - if (esp_netif && !_IS_NETIF_POINT2POINT_TYPE(esp_netif, PPP_LWIP_NETIF)) { + if (esp_netif && !ESP_NETIF_IS_POINT2POINT_TYPE(esp_netif, PPP_LWIP_NETIF)) { return esp_netif->lwip_netif; } return NULL; @@ -577,23 +576,6 @@ static esp_err_t esp_netif_init_configuration(esp_netif_t *esp_netif, const esp_ esp_netif->netif_handle = esp_netif->related_data; #else LOG_NETIF_DISABLED_AND_DO("PPP", return ESP_ERR_NOT_SUPPORTED); -#endif - } else if (cfg->base->flags & ESP_NETIF_FLAG_IS_SLIP) { -#if CONFIG_LWIP_SLIP_SUPPORT - esp_netif->related_data = esp_netif_new_slip(esp_netif, esp_netif_stack_config); - if (esp_netif->related_data == NULL) { - return ESP_ERR_ESP_NETIF_INIT_FAILED; - } - if (esp_netif_stack_config->lwip.init_fn) { - esp_netif->lwip_init_fn = esp_netif_stack_config->lwip.init_fn; - } - if (esp_netif_stack_config->lwip.input_fn) { - esp_netif->lwip_input_fn = esp_netif_stack_config->lwip.input_fn; - } - // Make the netif handle (used for tcpip input function) the esp_netif itself - esp_netif->netif_handle = esp_netif; -#else - LOG_NETIF_DISABLED_AND_DO("SLIP", return ESP_ERR_NOT_SUPPORTED); #endif } else { if (esp_netif_stack_config-> lwip.init_fn) { @@ -786,13 +768,9 @@ static esp_err_t esp_netif_lwip_add(esp_netif_t *esp_netif) static void esp_netif_destroy_related(esp_netif_t *esp_netif) { - if (_IS_NETIF_POINT2POINT_TYPE(esp_netif, PPP_LWIP_NETIF)) { + if (ESP_NETIF_IS_POINT2POINT_TYPE(esp_netif, PPP_LWIP_NETIF)) { #if CONFIG_PPP_SUPPORT esp_netif_destroy_ppp(esp_netif->related_data); -#endif - } else if (_IS_NETIF_POINT2POINT_TYPE(esp_netif, SLIP_LWIP_NETIF)) { -#if CONFIG_LWIP_SLIP_SUPPORT - esp_netif_destroy_slip(esp_netif->related_data); #endif } } @@ -945,11 +923,7 @@ static esp_err_t esp_netif_start_api(esp_netif_api_msg_t *msg) #endif } struct netif *p_netif = esp_netif->lwip_netif; - if (_IS_NETIF_POINT2POINT_TYPE(esp_netif, SLIP_LWIP_NETIF)) { -#if CONFIG_LWIP_SLIP_SUPPORT - esp_netif_start_slip(esp_netif); -#endif - } + if (esp_netif->flags&ESP_NETIF_FLAG_AUTOUP) { ESP_LOGD(TAG, "%s Setting the lwip netif%p UP", __func__, p_netif); netif_set_up(p_netif); @@ -1011,7 +985,7 @@ static esp_err_t esp_netif_start_api(esp_netif_api_msg_t *msg) esp_err_t esp_netif_start(esp_netif_t *esp_netif) { - if (_IS_NETIF_POINT2POINT_TYPE(esp_netif, PPP_LWIP_NETIF)) { + if (ESP_NETIF_IS_POINT2POINT_TYPE(esp_netif, PPP_LWIP_NETIF)) { #if CONFIG_PPP_SUPPORT // No need to start PPP interface in lwip thread esp_err_t ret = esp_netif_start_ppp(esp_netif); @@ -1066,7 +1040,7 @@ static esp_err_t esp_netif_stop_api(esp_netif_api_msg_t *msg) esp_err_t esp_netif_stop(esp_netif_t *esp_netif) { - if (_IS_NETIF_POINT2POINT_TYPE(esp_netif, PPP_LWIP_NETIF)) { + if (ESP_NETIF_IS_POINT2POINT_TYPE(esp_netif, PPP_LWIP_NETIF)) { #if CONFIG_PPP_SUPPORT // No need to stop PPP interface in lwip thread esp_err_t ret = esp_netif_stop_ppp(esp_netif->related_data); @@ -1074,15 +1048,6 @@ esp_err_t esp_netif_stop(esp_netif_t *esp_netif) esp_netif_update_default_netif(esp_netif, ESP_NETIF_STOPPED); } return ret; -#endif - } else if (_IS_NETIF_POINT2POINT_TYPE(esp_netif, SLIP_LWIP_NETIF)) { -#if CONFIG_LWIP_SLIP_SUPPORT - // No need to stop SLIP interface in lwip thread - esp_err_t ret = esp_netif_stop_slip(esp_netif); - if (ret == ESP_OK) { - esp_netif_update_default_netif(esp_netif, ESP_NETIF_STOPPED); - } - return ret; #endif } return esp_netif_lwip_ipc_call(esp_netif_stop_api, esp_netif, NULL); diff --git a/components/esp_netif/lwip/esp_netif_lwip_internal.h b/components/esp_netif/lwip/esp_netif_lwip_internal.h index 0737f79c3c..332a4f822d 100644 --- a/components/esp_netif/lwip/esp_netif_lwip_internal.h +++ b/components/esp_netif/lwip/esp_netif_lwip_internal.h @@ -8,7 +8,6 @@ #include "esp_netif.h" #include "esp_netif_ppp.h" -#include "esp_netif_slip.h" #include "lwip/netif.h" #include "dhcpserver/dhcpserver.h" @@ -39,10 +38,10 @@ typedef struct esp_netif_ip_lost_timer_s { /** * @brief Check the netif if of a specific P2P type */ -#if CONFIG_PPP_SUPPORT || CONFIG_LWIP_SLIP_SUPPORT -#define _IS_NETIF_POINT2POINT_TYPE(netif, type) (netif->related_data && netif->related_data->is_point2point && netif->related_data->netif_type == type) +#if CONFIG_PPP_SUPPORT +#define ESP_NETIF_IS_POINT2POINT_TYPE(netif, type) (netif->related_data && netif->related_data->is_point2point && netif->related_data->netif_type == type) #else -#define _IS_NETIF_POINT2POINT_TYPE(netif, type) false +#define ESP_NETIF_IS_POINT2POINT_TYPE(netif, type) false #endif /** @@ -51,12 +50,11 @@ typedef struct esp_netif_ip_lost_timer_s { enum netif_types { COMMON_LWIP_NETIF, PPP_LWIP_NETIF, - SLIP_LWIP_NETIF }; /** * @brief Related data to esp-netif (additional data for some special types of netif - * (typically for point-point network types, such as PPP or SLIP) + * (typically for point-point network types, such as PPP) */ typedef struct netif_related_data { bool is_point2point; diff --git a/components/esp_netif/lwip/esp_netif_lwip_ppp.c b/components/esp_netif/lwip/esp_netif_lwip_ppp.c index 2c6c1c1248..67175df4d9 100644 --- a/components/esp_netif/lwip/esp_netif_lwip_ppp.c +++ b/components/esp_netif/lwip/esp_netif_lwip_ppp.c @@ -203,7 +203,7 @@ static uint32_t pppos_low_level_output(ppp_pcb *pcb, uint8_t *data, uint32_t len esp_err_t esp_netif_ppp_set_auth(esp_netif_t *netif, esp_netif_auth_type_t authtype, const char *user, const char *passwd) { - if (!_IS_NETIF_POINT2POINT_TYPE(netif, PPP_LWIP_NETIF)) { + if (!ESP_NETIF_IS_POINT2POINT_TYPE(netif, PPP_LWIP_NETIF)) { return ESP_ERR_ESP_NETIF_INVALID_PARAMS; } #if PPP_AUTH_SUPPORT diff --git a/components/esp_netif/lwip/esp_netif_lwip_slip.c b/components/esp_netif/lwip/esp_netif_lwip_slip.c deleted file mode 100644 index 6d59370f4e..0000000000 --- a/components/esp_netif/lwip/esp_netif_lwip_slip.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - - - -#include "esp_netif.h" -#include "esp_log.h" -#include "esp_netif_slip.h" -#include "esp_netif_lwip_internal.h" -#include "esp_netif_net_stack.h" -#include "lwip/esp_netif_net_stack.h" - -#ifdef CONFIG_ESP_NETIF_TCPIP_LWIP - -#include "lwip/dns.h" -#include "lwip/opt.h" -#include "lwip/ip6_addr.h" -#include "lwip/netif.h" -#include "netif/slipif.h" -#include "lwip/sio.h" - -#include - -static const char *TAG = "esp-netif_lwip-slip"; - -/** - * @brief LWIP SLIP context object extends esp-netif related data - */ -typedef struct lwip_slip_ctx { - //! Generic esp-netif related data - netif_related_data_t base; - - //! SLIP interface IP6 address - esp_ip6_addr_t addr; - -} lwip_slip_ctx_t; - -/** - * @brief Create a new lwip slip interface - */ -netif_related_data_t * esp_netif_new_slip(esp_netif_t *esp_netif, const esp_netif_netstack_config_t *esp_netif_stack_config) -{ - ESP_LOGD(TAG, "%s", __func__); - - // Fetch netif and create context - struct netif *netif_impl = esp_netif->lwip_netif; - - lwip_slip_ctx_t *slip_ctx = calloc(1, sizeof(lwip_slip_ctx_t)); - if (slip_ctx == NULL) { - ESP_LOGE(TAG, "%s: cannot allocate lwip_slip_ctx_t", __func__); - return NULL; - } - // Setup the generic esp-netif fields - slip_ctx->base.is_point2point = true; - slip_ctx->base.netif_type = SLIP_LWIP_NETIF; - - ESP_LOGD(TAG, "%s: Initialising SLIP (esp_netif %p, lwip_netif %p)", __func__, esp_netif, netif_impl); - - ESP_LOGI(TAG, "%s: Created SLIP interface (netif %p, slip_ctx: %p)", __func__, esp_netif, slip_ctx); - - return (netif_related_data_t *)slip_ctx; -} - -/** - * @brief Stops the SLIP interface - */ -esp_err_t esp_netif_stop_slip(esp_netif_t *esp_netif) -{ - lwip_slip_ctx_t *slip_ctx = (lwip_slip_ctx_t *)esp_netif->related_data; - assert(slip_ctx->base.netif_type == SLIP_LWIP_NETIF); - - ESP_LOGI(TAG, "%s: Stopped SLIP connection: %p", __func__, slip_ctx); - - // Stop interface - netif_set_link_down(esp_netif->lwip_netif); - - return ESP_OK; -} - -/** - * @brief Starts the SLIP interface - */ -esp_err_t esp_netif_start_slip(esp_netif_t *esp_netif) -{ - lwip_slip_ctx_t *slip_ctx = (lwip_slip_ctx_t *)esp_netif->related_data; - assert(slip_ctx->base.netif_type == SLIP_LWIP_NETIF); - - ESP_LOGI(TAG, "%s: Starting SLIP interface: %p", __func__, slip_ctx); - - // Set the netif up - netif_set_up(esp_netif->lwip_netif); - netif_set_link_up(esp_netif->lwip_netif); -#if CONFIG_LWIP_IPV6 - int8_t addr_index = 0; - - netif_ip6_addr_set(esp_netif->lwip_netif, addr_index, (ip6_addr_t *)&slip_ctx->addr); - netif_ip6_addr_set_state(esp_netif->lwip_netif, addr_index, IP6_ADDR_VALID); -#endif - return ESP_OK; -} - - -/** - * @brief Sets paramaters for the supplied netif - */ -esp_err_t esp_netif_slip_set_params(esp_netif_t *netif, const esp_netif_slip_config_t *slip_config) -{ - - lwip_slip_ctx_t *slip_ctx = (lwip_slip_ctx_t *)netif->related_data; - assert(slip_ctx->base.netif_type == SLIP_LWIP_NETIF); - - ESP_LOGD(TAG, "%s (slip_ctx: %p)", __func__, slip_ctx); - - if (netif_is_link_up(netif->lwip_netif)) { - ESP_LOGE(TAG, "Cannot set parameters while SLIP interface is running"); - return ESP_ERR_INVALID_STATE; - } - - memcpy(&slip_ctx->addr, &slip_config->ip6_addr, sizeof(esp_ip6_addr_t)); - - - return ESP_OK; -} - -#if CONFIG_LWIP_IPV6 -esp_err_t esp_netif_slip_set_ipv6(esp_netif_t *netif, const esp_ip6_addr_t *ipv6) -{ - lwip_slip_ctx_t *slip_ctx = (lwip_slip_ctx_t *)netif->related_data; - assert(slip_ctx->base.netif_type == SLIP_LWIP_NETIF); - - ESP_LOGV(TAG, "%s (slip_ctx: %p)", __func__, slip_ctx); - - if (netif_is_link_up(netif->lwip_netif)) { - ESP_LOGE(TAG, "Cannot set parameters while SLIP interface is running"); - return ESP_ERR_INVALID_STATE; - } - memcpy(&slip_ctx->addr, ipv6, sizeof(ip6_addr_t)); - int8_t addr_index = 0; - - netif_ip6_addr_set(netif->lwip_netif, addr_index, (ip6_addr_t *)&slip_ctx->addr); - netif_ip6_addr_set_state(netif->lwip_netif, addr_index, IP6_ADDR_VALID); - - return ESP_OK; -} -#endif - -/** - * @brief Write incoming serial data to the SLIP interface - */ -void esp_netif_lwip_slip_input(void *h, void *buffer, unsigned int len, void *eb) -{ - esp_netif_t *netif = h; - lwip_slip_ctx_t *slip_ctx = (lwip_slip_ctx_t *)netif->related_data; - assert(slip_ctx->base.netif_type == SLIP_LWIP_NETIF); - - ESP_LOGD(TAG, "%s", __func__); - ESP_LOG_BUFFER_HEXDUMP(TAG, buffer, len, ESP_LOG_DEBUG); - - // Update slip netif with data - const int max_batch = 255; - int sent = 0; - while(sent < len) { - int batch = (len - sent) > max_batch ? max_batch : (len - sent); - slipif_received_bytes(netif->lwip_netif, buffer+sent, batch); - sent += batch; - } - - // Process incoming bytes - for (int i = 0; i < len; i++) { - slipif_process_rxqueue(netif->lwip_netif); - } -} - -/** - * @brief Write raw data out the SLIP interface - */ -void esp_netif_lwip_slip_raw_output(esp_netif_t *slip_netif, void *buffer, size_t len) -{ - struct netif *lwip_netif = slip_netif->lwip_netif; - - ESP_LOGD(TAG, "%s", __func__); - - struct pbuf p = { - .next = NULL, - .payload = buffer, - .tot_len = len, - .len = len, - }; - - // Call slip if output function to feed data out slip interface -#if CONFIG_LWIP_IPV6 - lwip_netif->output_ip6(lwip_netif, &p, NULL); -#else - lwip_netif->output(lwip_netif, &p, NULL); -#endif -} - -/** - * @brief Destroys the SLIP context object - */ -void esp_netif_destroy_slip(netif_related_data_t *slip) -{ - ESP_LOGD(TAG, "%s", __func__); - - // Free base object - free(slip); -} - -const esp_ip6_addr_t *esp_slip_get_ip6(esp_netif_t *slip_netif) -{ - lwip_slip_ctx_t *slip_ctx = (lwip_slip_ctx_t *)slip_netif->related_data; - assert(slip_ctx->base.netif_type == SLIP_LWIP_NETIF); - return &slip_ctx->addr; -} - -/** @brief Get esp-netif object corresponding to registration index - */ -static esp_netif_t * get_netif_with_esp_index(int index) -{ - esp_netif_t *netif = NULL; - int counter = 0; - while ((netif = esp_netif_next(netif)) != NULL) { - if (counter == index) { - return netif; - } - counter++; - } - return NULL; -} - -/** @brief Return list registration index of the supplied netif ptr - */ -static int get_esp_netif_index(esp_netif_t * esp_netif) -{ - esp_netif_t *netif = NULL; - int counter = 0; - while ((netif = esp_netif_next(netif)) != NULL) { - if (esp_netif == netif) { - return counter; - } - counter++; - } - return -1; -} - -err_t esp_slipif_init(struct netif *netif) -{ - esp_netif_t *esp_netif = netif->state; - int esp_index = get_esp_netif_index(esp_netif); - if (esp_index < 0) { - return ERR_IF; - } - - // Store netif index in net interface for SIO open command to abstract the dev - netif->state = (void *)esp_index; - - return slipif_init(netif); -} - -static const struct esp_netif_netstack_config s_netif_config_slip = { - .lwip = { - .init_fn = esp_slipif_init, - .input_fn = esp_netif_lwip_slip_input, - } -}; - -const esp_netif_netstack_config_t *_g_esp_netif_netstack_default_slip = &s_netif_config_slip; - - -/*** - * @brief Open a serial device for communication - */ -sio_fd_t sio_open(uint8_t devnum) -{ - ESP_LOGD(TAG, "Opening device: %d\r\n", devnum); - - esp_netif_t *esp_netif = get_netif_with_esp_index(devnum); - if (!esp_netif) { - ESP_LOGE(TAG, "didn't find esp-netif with index=%d\n", devnum); - return NULL; - } - - // Return SIO handle - return esp_netif; -} - -/*** - * @brief Send a single character to the serial device (blocking) - */ -void sio_send(uint8_t c, sio_fd_t fd) -{ - esp_netif_t *esp_netif = fd; - - ESP_LOGD(TAG, "%s", __func__); - ESP_LOG_BUFFER_HEX_LEVEL(TAG, &c, 1, ESP_LOG_DEBUG); - - esp_err_t ret = esp_netif_transmit(esp_netif, &c, 1); - if (ret != ESP_OK) { - // Handle errors - ESP_LOGD(TAG, "%s: uart_write_bytes error %i", __func__, ret); - } -} - -#endif /* CONFIG_ESP_NETIF_TCPIP_LWIP */ diff --git a/components/esp_netif/lwip/esp_netif_lwip_slip.h b/components/esp_netif/lwip/esp_netif_lwip_slip.h deleted file mode 100644 index e8f9ae3264..0000000000 --- a/components/esp_netif/lwip/esp_netif_lwip_slip.h +++ /dev/null @@ -1,58 +0,0 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#ifndef _ESP_NETIF_LWIP_SLIP_H_ -#define _ESP_NETIF_LWIP_SLIP_H_ - -/** - * @brief Creates new SLIP related structure - * - * @param[in] esp_netif pointer esp-netif instance - * @param[in] stack_config TCP/IP stack configuration structure - * - * @return - * - pointer to slip-netif object on success - * - NULL otherwise - */ -netif_related_data_t * esp_netif_new_slip(esp_netif_t *esp_netif, const esp_netif_netstack_config_t *esp_netif_stack_config); - -/** - * @brief Destroys the slip netif object - * - * @param[in] slip pointer to internal slip context instance - */ -void esp_netif_destroy_slip(netif_related_data_t *slip); - -/** - * @brief Stop the esp slip netif - * - * @param[in] esp_netif handle to slip esp-netif instance - * - * @return - * - ESP_OK on success - */ -esp_err_t esp_netif_stop_slip(esp_netif_t *esp_netif); - -/** - * @brief Start the esp slip netif - * - * @param[in] esp_netif handle to slip esp-netif instance - * - * @return - * - ESP_OK on success - */ -esp_err_t esp_netif_start_slip(esp_netif_t *esp_netif); - - -#endif // _ESP_NETIF_LWIP_SLIP_H_ diff --git a/components/esp_phy/CMakeLists.txt b/components/esp_phy/CMakeLists.txt index 10550e7fd8..46e9abde13 100644 --- a/components/esp_phy/CMakeLists.txt +++ b/components/esp_phy/CMakeLists.txt @@ -1,5 +1,10 @@ idf_build_get_property(idf_target IDF_TARGET) +if(IDF_TARGET STREQUAL "esp32c6") + # TODO : IDF-5680 + return() +endif() + set(srcs "src/phy_override.c" "src/lib_printf.c") if(CONFIG_APP_NO_BLOBS) @@ -39,13 +44,13 @@ idf_component_register(SRCS "${srcs}" set(target_name "${idf_target}") if(IDF_TARGET STREQUAL "esp32h2") if(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2) - target_link_libraries(${COMPONENT_LIB} PUBLIC "-L \"${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}/rev2\"") + target_link_directories(${COMPONENT_LIB} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}/rev2") endif() if(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1) - target_link_libraries(${COMPONENT_LIB} PUBLIC "-L \"${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}/rev1\"") + target_link_directories(${COMPONENT_LIB} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}/rev1") endif() else() - target_link_libraries(${COMPONENT_LIB} PUBLIC "-L \"${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}\"") + target_link_directories(${COMPONENT_LIB} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}") endif() # Override functions in PHY lib with the functions in 'phy_override.c' diff --git a/components/esp_pm/include/esp32c6/pm.h b/components/esp_pm/include/esp32c6/pm.h new file mode 100644 index 0000000000..6255cccad1 --- /dev/null +++ b/components/esp_pm/include/esp32c6/pm.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +#pragma once +#include +#include +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief Power management config for ESP32C6 + * + * Pass a pointer to this structure as an argument to esp_pm_configure function. + */ +typedef struct { + int max_freq_mhz; /*!< Maximum CPU frequency, in MHz */ + int min_freq_mhz; /*!< Minimum CPU frequency to use when no locks are taken, in MHz */ + bool light_sleep_enable; /*!< Enter light sleep when no locks are taken */ +} esp_pm_config_esp32c6_t; + + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_pm/include/esp_pm.h b/components/esp_pm/include/esp_pm.h index 64ef7b36ff..32f711e520 100644 --- a/components/esp_pm/include/esp_pm.h +++ b/components/esp_pm/include/esp_pm.h @@ -21,6 +21,8 @@ #include "esp32h2/pm.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/pm.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/pm.h" #endif #ifdef __cplusplus diff --git a/components/esp_pm/linker.lf b/components/esp_pm/linker.lf index 88489039eb..95e8b48069 100644 --- a/components/esp_pm/linker.lf +++ b/components/esp_pm/linker.lf @@ -21,8 +21,9 @@ entries: esp_clk:esp_rtc_get_time_us (noflash) if GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL = y: sleep_gpio:gpio_sleep_mode_config_apply (noflash) - if IDF_TARGET_ESP32 = n && IDF_TARGET_ESP32S2 = n: + if SOC_PM_SUPPORT_CPU_PD = y || SOC_PM_SUPPORT_TAGMEM_PD = y: sleep_retention:sleep_enable_memory_retention (noflash) + if SOC_PM_SUPPORT_CPU_PD = y: sleep_retention:cpu_domain_pd_allowed (noflash) [mapping:esp_system_pm] @@ -32,16 +33,24 @@ entries: freertos_hooks:esp_vApplicationIdleHook (noflash) if PM_SLP_IRAM_OPT = y: task_wdt:idle_hook_cb (noflash) - task_wdt:reset_hw_timer (noflash) + task_wdt:task_wdt_timer_feed (noflash) task_wdt:find_entry_and_check_all_reset (noflash) task_wdt:find_entry_from_task_handle_and_check_all_reset (noflash) task_wdt:esp_task_wdt_reset (noflash) task_wdt:esp_task_wdt_reset_user (noflash) + if ESP_TASK_WDT_USE_ESP_TIMER = y: + task_wdt_impl_esp_timer:esp_task_wdt_impl_timer_feed (noflash) + else: + task_wdt_impl_timergroup:esp_task_wdt_impl_timer_feed (noflash) [mapping:esp_timer_pm] archive: libesp_timer.a entries: if PM_SLP_IRAM_OPT = y: + # esp_timer_feed is called from task_wdt_timer_feed, so put it + # in IRAM if task_wdt_timer_feed itself is in IRAM. + if ESP_TASK_WDT_USE_ESP_TIMER = y: + esp_timer:esp_timer_feed (noflash) if ESP_TIMER_IMPL_TG0_LAC = y: esp_timer_impl_lac:esp_timer_impl_lock (noflash) esp_timer_impl_lac:esp_timer_impl_unlock (noflash) diff --git a/components/esp_pm/pm_impl.c b/components/esp_pm/pm_impl.c index d00f24a9aa..0d4094aceb 100644 --- a/components/esp_pm/pm_impl.c +++ b/components/esp_pm/pm_impl.c @@ -20,6 +20,7 @@ #include "soc/rtc.h" #include "hal/uart_ll.h" #include "hal/uart_types.h" +#include "driver/uart.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" @@ -55,6 +56,9 @@ #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/pm.h" #include "driver/gpio.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/pm.h" +#include "driver/gpio.h" #endif #define MHZ (1000000) @@ -84,13 +88,15 @@ #define REF_CLK_DIV_MIN 2 #elif CONFIG_IDF_TARGET_ESP32S3 /* Minimal divider at which REF_CLK_FREQ can be obtained */ -#define REF_CLK_DIV_MIN 2 +#define REF_CLK_DIV_MIN 2 // TODO: IDF-5660 #elif CONFIG_IDF_TARGET_ESP32C3 #define REF_CLK_DIV_MIN 2 #elif CONFIG_IDF_TARGET_ESP32H2 #define REF_CLK_DIV_MIN 2 #elif CONFIG_IDF_TARGET_ESP32C2 #define REF_CLK_DIV_MIN 2 +#elif CONFIG_IDF_TARGET_ESP32C6 +#define REF_CLK_DIV_MIN 2 #endif #ifdef CONFIG_PM_PROFILING @@ -227,6 +233,8 @@ esp_err_t esp_pm_configure(const void* vconfig) const esp_pm_config_esp32h2_t* config = (const esp_pm_config_esp32h2_t*) vconfig; #elif CONFIG_IDF_TARGET_ESP32C2 const esp_pm_config_esp32c2_t* config = (const esp_pm_config_esp32c2_t*) vconfig; +#elif CONFIG_IDF_TARGET_ESP32C6 + const esp_pm_config_esp32c6_t* config = (const esp_pm_config_esp32c6_t*) vconfig; #endif #ifndef CONFIG_FREERTOS_USE_TICKLESS_IDLE @@ -337,6 +345,8 @@ esp_err_t esp_pm_get_configuration(void* vconfig) esp_pm_config_esp32h2_t* config = (esp_pm_config_esp32h2_t*) vconfig; #elif CONFIG_IDF_TARGET_ESP32C2 esp_pm_config_esp32c2_t* config = (esp_pm_config_esp32c2_t*) vconfig; +#elif CONFIG_IDF_TARGET_ESP32C6 + esp_pm_config_esp32c6_t* config = (esp_pm_config_esp32c6_t*) vconfig; #endif portENTER_CRITICAL(&s_switch_lock); @@ -732,7 +742,11 @@ void esp_pm_impl_init(void) while(!uart_ll_is_tx_idle(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM))); /* When DFS is enabled, override system setting and use REFTICK as UART clock source */ uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), clk_source); - uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), CONFIG_ESP_CONSOLE_UART_BAUDRATE); + + uint32_t sclk_freq; + esp_err_t err = uart_get_sclk_freq(clk_source, &sclk_freq); + assert(err == ESP_OK); + uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), CONFIG_ESP_CONSOLE_UART_BAUDRATE, sclk_freq); #endif // CONFIG_ESP_CONSOLE_UART #ifdef CONFIG_PM_TRACE @@ -777,6 +791,8 @@ void esp_pm_impl_init(void) esp_pm_config_esp32h2_t cfg = { #elif CONFIG_IDF_TARGET_ESP32C2 esp_pm_config_esp32c2_t cfg = { +#elif CONFIG_IDF_TARGET_ESP32C6 + esp_pm_config_esp32c6_t cfg = { #endif .max_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, .min_freq_mhz = xtal_freq_mhz, diff --git a/components/esp_pm/test/test_pm.c b/components/esp_pm/test/test_pm.c index ca4b913f99..83f4d8bcd8 100644 --- a/components/esp_pm/test/test_pm.c +++ b/components/esp_pm/test/test_pm.c @@ -54,6 +54,8 @@ static void switch_freq(int mhz) esp_pm_config_esp32c3_t pm_config = { #elif CONFIG_IDF_TARGET_ESP32H2 esp_pm_config_esp32h2_t pm_config = { +#elif CONFIG_IDF_TARGET_ESP32C6 + esp_pm_config_esp32c6_t pm_config = { #endif .max_freq_mhz = mhz, .min_freq_mhz = MIN(mhz, xtal_freq_mhz), @@ -109,6 +111,8 @@ static void light_sleep_enable(void) esp_pm_config_esp32c3_t pm_config = { #elif CONFIG_IDF_TARGET_ESP32H2 esp_pm_config_esp32h2_t pm_config = { +#elif CONFIG_IDF_TARGET_ESP32C6 + esp_pm_config_esp32c6_t pm_config = { #endif .max_freq_mhz = cur_freq_mhz, .min_freq_mhz = xtal_freq, @@ -133,6 +137,8 @@ static void light_sleep_disable(void) esp_pm_config_esp32c3_t pm_config = { #elif CONFIG_IDF_TARGET_ESP32H2 esp_pm_config_esp32h2_t pm_config = { +#elif CONFIG_IDF_TARGET_ESP32C6 + esp_pm_config_esp32c6_t pm_config = { #endif .max_freq_mhz = cur_freq_mhz, .min_freq_mhz = cur_freq_mhz, diff --git a/components/esp_psram/CMakeLists.txt b/components/esp_psram/CMakeLists.txt index bbff893900..0fe5d6a60c 100644 --- a/components/esp_psram/CMakeLists.txt +++ b/components/esp_psram/CMakeLists.txt @@ -14,7 +14,8 @@ set(srcs) if(CONFIG_SPIRAM) list(APPEND srcs "esp_psram.c" "mmu.c" - "mmu_psram.c") + "mmu_psram_flash.c" + "ext_mem_layout.c") if(${target} STREQUAL "esp32") list(APPEND srcs "esp32/esp_psram_extram_cache.c" diff --git a/components/esp_psram/esp32/esp_psram_impl_quad.c b/components/esp_psram/esp32/esp_psram_impl_quad.c index c06e329a78..5f65464354 100644 --- a/components/esp_psram/esp32/esp_psram_impl_quad.c +++ b/components/esp_psram/esp32/esp_psram_impl_quad.c @@ -133,11 +133,14 @@ typedef enum { } psram_cache_speed_t; #if CONFIG_SPIRAM_SPEED_40M && CONFIG_ESPTOOLPY_FLASHFREQ_40M -#define PSRAM_SPEED PSRAM_CACHE_F40M_S40M +#define PSRAM_SPEED PSRAM_CACHE_F40M_S40M +#define PSRAM_CS_HOLD_TIME 0 #elif CONFIG_SPIRAM_SPEED_40M && CONFIG_ESPTOOLPY_FLASHFREQ_80M -#define PSRAM_SPEED PSRAM_CACHE_F80M_S40M +#define PSRAM_SPEED PSRAM_CACHE_F80M_S40M +#define PSRAM_CS_HOLD_TIME 0 #elif CONFIG_SPIRAM_SPEED_80M && CONFIG_ESPTOOLPY_FLASHFREQ_80M -#define PSRAM_SPEED PSRAM_CACHE_F80M_S80M +#define PSRAM_SPEED PSRAM_CACHE_F80M_S80M +#define PSRAM_CS_HOLD_TIME 1 #else #error "FLASH speed can only be equal to or higher than SRAM speed while SRAM is enabled!" #endif @@ -680,7 +683,7 @@ void psram_set_cs_timing(psram_spi_num_t spi_num, psram_clk_mode_t clk_mode) if (clk_mode == PSRAM_CLK_MODE_NORM) { SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_CS_HOLD_M | SPI_CS_SETUP_M); // Set cs time. - SET_PERI_REG_BITS(SPI_CTRL2_REG(spi_num), SPI_HOLD_TIME_V, 1, SPI_HOLD_TIME_S); + SET_PERI_REG_BITS(SPI_CTRL2_REG(spi_num), SPI_HOLD_TIME_V, PSRAM_CS_HOLD_TIME, SPI_HOLD_TIME_S); SET_PERI_REG_BITS(SPI_CTRL2_REG(spi_num), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S); } else { CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_CS_HOLD_M | SPI_CS_SETUP_M); diff --git a/components/esp_psram/esp_psram.c b/components/esp_psram/esp_psram.c index e068edf58d..ce23e4f933 100644 --- a/components/esp_psram/esp_psram.c +++ b/components/esp_psram/esp_psram.c @@ -23,9 +23,10 @@ #include "hal/cache_ll.h" #include "esp_private/esp_psram_io.h" #include "esp_private/esp_psram_extram.h" -#include "esp_private/mmu.h" +#include "esp_private/mmu_psram_flash.h" #include "esp_psram_impl.h" #include "esp_psram.h" +#include "mmu.h" #if CONFIG_IDF_TARGET_ESP32 #include "esp32/himem.h" @@ -43,8 +44,14 @@ #define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL #endif - -#if CONFIG_SPIRAM +/** + * Two types of PSRAM memory regions for now: + * - 8bit aligned + * - 32bit aligned + */ +#define PSRAM_MEM_TYPE_NUM 2 +#define PSRAM_MEM_8BIT_ALIGNED 0 +#define PSRAM_MEM_32BIT_ALIGNED 1 #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY extern uint8_t _ext_ram_bss_start; @@ -56,13 +63,33 @@ extern uint8_t _ext_ram_noinit_start; extern uint8_t _ext_ram_noinit_end; #endif //#if CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY -//These variables are in bytes -static intptr_t s_allocable_vaddr_start; -static intptr_t s_allocable_vaddr_end; -static intptr_t s_mapped_vaddr_start; -static intptr_t s_mapped_vaddr_end; +typedef struct { + intptr_t vaddr_start; + intptr_t vaddr_end; + size_t size; //in bytes +} psram_mem_t; -static bool s_spiram_inited; +typedef struct { + bool is_initialised; + /** + * @note 1 + * As we can't use heap allocator during this stage, we need to statically declare these regions. + * Luckily only S2 has two different types of memory regions: + * - byte-aligned memory + * - word-aligned memory + * On the other hand, the type number usually won't be very big + * + * On other chips, only one region is needed. + * So for chips other than S2, size of `regions_to_heap[1]` and `mapped_regions[1]`will always be zero. + * + * If in the future, this condition is worse (dbus memory isn't consecutive), we need to delegate this context + * to chip-specific files, and only keep a (void *) pointer here pointing to those chip-specific contexts + */ + psram_mem_t regions_to_heap[PSRAM_MEM_TYPE_NUM]; //memory regions that are available to be added to the heap allocator + psram_mem_t mapped_regions[PSRAM_MEM_TYPE_NUM]; //mapped memory regions +} psram_ctx_t; + +static psram_ctx_t s_psram_ctx; static const char* TAG = "esp_psram"; @@ -86,26 +113,28 @@ static void IRAM_ATTR s_mapping(int v_start, int size) } #endif //CONFIG_IDF_TARGET_ESP32 + esp_err_t esp_psram_init(void) { - if (s_spiram_inited) { + if (s_psram_ctx.is_initialised) { return ESP_ERR_INVALID_STATE; } - esp_err_t ret; + + esp_err_t ret = ESP_FAIL; ret = esp_psram_impl_enable(PSRAM_MODE); if (ret != ESP_OK) { #if CONFIG_SPIRAM_IGNORE_NOTFOUND - ESP_EARLY_LOGE(TAG, "SPI RAM enabled but initialization failed. Bailing out."); + ESP_EARLY_LOGE(TAG, "PSRAM enabled but initialization failed. Bailing out."); #endif return ret; } - s_spiram_inited = true; + s_psram_ctx.is_initialised = true; uint32_t psram_physical_size = 0; ret = esp_psram_impl_get_physical_size(&psram_physical_size); assert(ret == ESP_OK); - ESP_EARLY_LOGI(TAG, "Found %dMB SPI RAM device", psram_physical_size / (1024 * 1024)); + ESP_EARLY_LOGI(TAG, "Found %dMB PSRAM device", psram_physical_size / (1024 * 1024)); ESP_EARLY_LOGI(TAG, "Speed: %dMHz", CONFIG_SPIRAM_SPEED); #if CONFIG_IDF_TARGET_ESP32 ESP_EARLY_LOGI(TAG, "PSRAM initialized, cache is in %s mode.", \ @@ -155,99 +184,168 @@ esp_err_t esp_psram_init(void) ESP_EARLY_LOGV(TAG, "after copy .rodata, used page is %d, start_page is %d, psram_available_size is %d B", used_page, start_page, psram_available_size); #endif //#if CONFIG_SPIRAM_RODATA + /** + * For now, + * - we only need to use MMU driver when PSRAM is enabled + * - MMU driver isn't public + * + * So we call `esp_mmu_init()` here, instead of calling it in startup code. + */ + esp_mmu_init(); //----------------------------------Map the PSRAM physical range to MMU-----------------------------// - intptr_t vaddr_start = mmu_get_psram_vaddr_start(); - if (vaddr_start + psram_available_size > mmu_get_psram_vaddr_end()) { - psram_available_size = mmu_get_psram_vaddr_end() - vaddr_start; - ESP_EARLY_LOGV(TAG, "Virtual address not enough for PSRAM, map as much as we can. %dMB is mapped", psram_available_size / 1024 / 1024); - } + /** + * @note 2 + * Similarly to @note 1, we expect HW DBUS memory to be consecutive. + * + * If situation is worse in the future (memory region isn't consecutive), we need to put these logics into chip-specific files + */ + size_t total_mapped_size = 0; + size_t size_to_map = 0; + size_t byte_aligned_size = 0; + ret = esp_mmu_get_largest_free_block(MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_8BIT | MMU_MEM_CAP_32BIT, &byte_aligned_size); + assert(ret == ESP_OK); + size_to_map = MIN(byte_aligned_size, psram_available_size); + + const void *v_start_8bit_aligned = NULL; + ret = esp_mmu_find_vaddr_range(size_to_map, MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_8BIT | MMU_MEM_CAP_32BIT, &v_start_8bit_aligned); + assert(ret == ESP_OK); #if CONFIG_IDF_TARGET_ESP32 - s_mapping(vaddr_start, psram_available_size); + s_mapping((int)v_start_8bit_aligned, size_to_map); #else uint32_t actual_mapped_len = 0; - mmu_hal_map_region(0, MMU_TARGET_PSRAM0, vaddr_start, MMU_PAGE_TO_BYTES(start_page), psram_available_size, &actual_mapped_len); - ESP_EARLY_LOGV(TAG, "actual_mapped_len is 0x%x bytes", actual_mapped_len); + mmu_hal_map_region(0, MMU_TARGET_PSRAM0, (intptr_t)v_start_8bit_aligned, MMU_PAGE_TO_BYTES(start_page), size_to_map, &actual_mapped_len); + start_page += BYTES_TO_MMU_PAGE(actual_mapped_len); + ESP_EARLY_LOGV(TAG, "8bit-aligned-region: actual_mapped_len is 0x%x bytes", actual_mapped_len); - cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, vaddr_start, actual_mapped_len); + cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, (uint32_t)v_start_8bit_aligned, actual_mapped_len); cache_ll_l1_enable_bus(0, bus_mask); #if !CONFIG_FREERTOS_UNICORE - bus_mask = cache_ll_l1_get_bus(1, vaddr_start, actual_mapped_len); + bus_mask = cache_ll_l1_get_bus(1, (uint32_t)v_start_8bit_aligned, actual_mapped_len); cache_ll_l1_enable_bus(1, bus_mask); #endif #endif //#if CONFIG_IDF_TARGET_ESP32 + s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].size = size_to_map; + s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].vaddr_start = (intptr_t)v_start_8bit_aligned; + s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].vaddr_end = (intptr_t)v_start_8bit_aligned + size_to_map; + s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].size = size_to_map; + s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].vaddr_start = (intptr_t)v_start_8bit_aligned; + s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].vaddr_end = (intptr_t)v_start_8bit_aligned + size_to_map; + ESP_EARLY_LOGV(TAG, "8bit-aligned-range: 0x%x B, starting from: 0x%x", s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].size, v_start_8bit_aligned); + total_mapped_size += size_to_map; + +#if CONFIG_IDF_TARGET_ESP32S2 + /** + * On ESP32S2, there are 2 types of DBUS memory: + * - byte-aligned-memory + * - word-aligned-memory + * + * If byte-aligned-memory isn't enough, we search for word-aligned-memory to do mapping + */ + if (total_mapped_size < psram_available_size) { + size_to_map = psram_available_size - total_mapped_size; + + size_t word_aligned_size = 0; + ret = esp_mmu_get_largest_free_block(MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT, &word_aligned_size); + assert(ret == ESP_OK); + size_to_map = MIN(word_aligned_size, size_to_map); + + const void *v_start_32bit_aligned = NULL; + ret = esp_mmu_find_vaddr_range(size_to_map, MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT, &v_start_32bit_aligned); + assert(ret == ESP_OK); + + mmu_hal_map_region(0, MMU_TARGET_PSRAM0, (intptr_t)v_start_32bit_aligned, MMU_PAGE_TO_BYTES(start_page), size_to_map, &actual_mapped_len); + ESP_EARLY_LOGV(TAG, "32bit-aligned-region: actual_mapped_len is 0x%x bytes", actual_mapped_len); + + cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, (uint32_t)v_start_32bit_aligned, actual_mapped_len); + cache_ll_l1_enable_bus(0, bus_mask); + + s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].size = size_to_map; + s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].vaddr_start = (intptr_t)v_start_32bit_aligned; + s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].vaddr_end = (intptr_t)v_start_32bit_aligned + size_to_map; + s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].size = size_to_map; + s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].vaddr_start = (intptr_t)v_start_32bit_aligned; + s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].vaddr_end = (intptr_t)v_start_32bit_aligned + size_to_map; + ESP_EARLY_LOGV(TAG, "32bit-aligned-range: 0x%x B, starting from: 0x%x", s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].size, v_start_32bit_aligned); + total_mapped_size += size_to_map; + } +#endif // #if CONFIG_IDF_TARGET_ESP32S2 + + if (total_mapped_size < psram_available_size) { + ESP_EARLY_LOGW(TAG, "Virtual address not enough for PSRAM, map as much as we can. %dMB is mapped", total_mapped_size / 1024 / 1024); + } + /*------------------------------------------------------------------------------ * After mapping, we DON'T care about the PSRAM PHYSICAL ADDRESSS ANYMORE! *----------------------------------------------------------------------------*/ - s_mapped_vaddr_start = vaddr_start; - s_mapped_vaddr_end = vaddr_start + psram_available_size; - s_allocable_vaddr_start = vaddr_start; - s_allocable_vaddr_end = vaddr_start + psram_available_size; //------------------------------------Configure .bss in PSRAM-------------------------------------// #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY //should never be negative number uint32_t ext_bss_size = ((intptr_t)&_ext_ram_bss_end - (intptr_t)&_ext_ram_bss_start); ESP_EARLY_LOGV(TAG, "ext_bss_size is %d", ext_bss_size); - s_allocable_vaddr_start += ext_bss_size; + s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].vaddr_start += ext_bss_size; + s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].size -= ext_bss_size; #endif //#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY #if CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY uint32_t ext_noinit_size = ((intptr_t)&_ext_ram_noinit_end - (intptr_t)&_ext_ram_noinit_start); ESP_EARLY_LOGV(TAG, "ext_noinit_size is %d", ext_noinit_size); - s_allocable_vaddr_start += ext_noinit_size; + s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].vaddr_start += ext_noinit_size; + s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].size -= ext_noinit_size; #endif #if CONFIG_IDF_TARGET_ESP32 - s_allocable_vaddr_end -= esp_himem_reserved_area_size() - 1; + s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].size -= esp_himem_reserved_area_size() - 1; #endif - ESP_EARLY_LOGV(TAG, "s_allocable_vaddr_start is 0x%x, s_allocable_vaddr_end is 0x%x", s_allocable_vaddr_start, s_allocable_vaddr_end); return ESP_OK; } -/** - * Add the PSRAM available region to heap allocator. Heap allocator knows the capabilities of this type of memory, - * so there's no need to explicitly specify them. - */ + esp_err_t esp_psram_extram_add_to_heap_allocator(void) { - ESP_EARLY_LOGI(TAG, "Adding pool of %dK of external SPI memory to heap allocator", (s_allocable_vaddr_end - s_allocable_vaddr_start) / 1024); - return heap_caps_add_region(s_allocable_vaddr_start, s_allocable_vaddr_end); -} + esp_err_t ret = ESP_FAIL; -esp_err_t IRAM_ATTR esp_psram_extram_get_mapped_range(intptr_t *out_vstart, intptr_t *out_vend) -{ - if (!out_vstart || !out_vend) { - return ESP_ERR_INVALID_ARG; + uint32_t byte_aligned_caps[] = {MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}; + ret = heap_caps_add_region_with_caps(byte_aligned_caps, + s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].vaddr_start, + s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].vaddr_end); + if (ret != ESP_OK) { + return ret; } - if (!s_spiram_inited) { - return ESP_ERR_INVALID_STATE; + if (s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].size) { + assert(s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].vaddr_start); + uint32_t word_aligned_caps[] = {MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_32BIT}; + ret = heap_caps_add_region_with_caps(word_aligned_caps, + s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].vaddr_start, + s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].vaddr_end); + if (ret != ESP_OK) { + return ret; + } } - *out_vstart = s_mapped_vaddr_start; - *out_vend = s_mapped_vaddr_end; + ESP_EARLY_LOGI(TAG, "Adding pool of %dK of PSRAM memory to heap allocator", + (s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].size + s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].size) / 1024); + return ESP_OK; } -esp_err_t esp_psram_extram_get_alloced_range(intptr_t *out_vstart, intptr_t *out_vend) + +bool IRAM_ATTR esp_psram_check_ptr_addr(const void *p) { - if (!out_vstart || !out_vend) { - return ESP_ERR_INVALID_ARG; + if (!s_psram_ctx.is_initialised) { + return false; } - if (!s_spiram_inited) { - return ESP_ERR_INVALID_STATE; - } - - *out_vstart = s_allocable_vaddr_start; - *out_vend = s_allocable_vaddr_end; - return ESP_OK; + return ((intptr_t)p >= s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].vaddr_start && (intptr_t)p < s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].vaddr_end) || + ((intptr_t)p >= s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].vaddr_start && (intptr_t)p < s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].vaddr_end); } + esp_err_t esp_psram_extram_reserve_dma_pool(size_t size) { if (size == 0) { @@ -276,9 +374,9 @@ esp_err_t esp_psram_extram_reserve_dma_pool(size_t size) return ESP_OK; } -bool IRAM_ATTR esp_psram_is_initialized(void) +bool IRAM_ATTR __attribute__((pure)) esp_psram_is_initialized(void) { - return s_spiram_inited; + return s_psram_ctx.is_initialised; } size_t esp_psram_get_size(void) @@ -302,45 +400,68 @@ uint8_t esp_psram_io_get_cs_io(void) true when RAM seems OK, false when test fails. WARNING: Do not run this before the 2nd cpu has been initialized (in a two-core system) or after the heap allocator has taken ownership of the memory. */ -bool esp_psram_extram_test(void) +static bool s_test_psram(intptr_t v_start, size_t size, intptr_t reserved_start, intptr_t reserved_end) { -#if CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY - const void *keepout_addr_low = (const void*)&_ext_ram_noinit_start; - const void *keepout_addr_high = (const void*)&_ext_ram_noinit_end; -#else - const void *keepout_addr_low = 0; - const void *keepout_addr_high = 0; -#endif - - volatile int *spiram = (volatile int *)s_mapped_vaddr_start; + volatile int *spiram = (volatile int *)v_start; size_t p; - size_t s = s_mapped_vaddr_end - s_mapped_vaddr_start; - int errct=0; - int initial_err=-1; - for (p=0; p<(s/sizeof(int)); p+=8) { - const void *addr = (const void *)&spiram[p]; - if ((keepout_addr_low <= addr) && (addr < keepout_addr_high)) { + int errct = 0; + int initial_err = -1; + for (p = 0; p < (size / sizeof(int)); p += 8) { + intptr_t addr = (intptr_t)&spiram[p]; + if ((reserved_start <= addr) && (addr < reserved_end)) { continue; } - spiram[p]=p^0xAAAAAAAA; + spiram[p] = p ^ 0xAAAAAAAA; } - for (p=0; p<(s/sizeof(int)); p+=8) { - const void *addr = (const void *)&spiram[p]; - if ((keepout_addr_low <= addr) && (addr < keepout_addr_high)) { + for (p = 0; p < (size / sizeof(int)); p += 8) { + intptr_t addr = (intptr_t)&spiram[p]; + if ((reserved_start <= addr) && (addr < reserved_end)) { continue; } - if (spiram[p]!=(p^0xAAAAAAAA)) { + if (spiram[p] != (p ^ 0xAAAAAAAA)) { errct++; - if (errct==1) initial_err=p*4; + if (errct == 1) { + initial_err = p * 4; + } } } if (errct) { - ESP_EARLY_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %X\n", errct, s/32, initial_err + s_mapped_vaddr_start); + ESP_EARLY_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %X\n", errct, size/32, initial_err + v_start); return false; } else { ESP_EARLY_LOGI(TAG, "SPI SRAM memory test OK"); return true; } + } -#endif //#if CONFIG_SPIRAM +bool esp_psram_extram_test(void) +{ + bool test_success = false; +#if CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY + intptr_t noinit_vstart = (intptr_t)&_ext_ram_noinit_start; + intptr_t noinit_vend = (intptr_t)&_ext_ram_noinit_end; +#else + intptr_t noinit_vstart = 0; + intptr_t noinit_vend = 0; +#endif + test_success = s_test_psram(s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].vaddr_start, + s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].size, + noinit_vstart, + noinit_vend); + if (!test_success) { + return false; + } + + if (s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].size) { + test_success = s_test_psram(s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].vaddr_start, + s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].size, + 0, + 0); + } + if (!test_success) { + return false; + } + + return true; +} diff --git a/components/esp_psram/ext_mem_layout.c b/components/esp_psram/ext_mem_layout.c new file mode 100644 index 0000000000..1a5a61dc89 --- /dev/null +++ b/components/esp_psram/ext_mem_layout.c @@ -0,0 +1,77 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include "sdkconfig.h" +#include "soc/ext_mem_defs.h" +#include "ext_mem_layout.h" +#include "mmu.h" + + +#if CONFIG_IDF_TARGET_ESP32 +/** + * These regions is referring to linear address + * The start addresses in this list should always be sorted from low to high, as MMU driver will need to + * coalesce adjacent regions + */ +const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = { + + /*linear start linear end bus size bus ID, bus capabilities */ + + //Can be used for text + {SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW, SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH, BUS_SIZE(SOC_MMU_IRAM0_LINEAR), CACHE_BUS_IBUS0, MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT}, + //Can be used for text + {SOC_MMU_IRAM1_LINEAR_ADDRESS_LOW, SOC_MMU_IRAM1_LINEAR_ADDRESS_HIGH, BUS_SIZE(SOC_MMU_IRAM1_LINEAR), CACHE_BUS_IBUS1, MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT}, + //Can be used for text + {SOC_MMU_IROM0_LINEAR_ADDRESS_LOW, SOC_MMU_IROM0_LINEAR_ADDRESS_HIGH, BUS_SIZE(SOC_MMU_IROM0_LINEAR), CACHE_BUS_IBUS2, MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT}, + //Can be used for rodata + {SOC_MMU_DROM0_LINEAR_ADDRESS_LOW, SOC_MMU_DROM0_LINEAR_ADDRESS_HIGH, BUS_SIZE(SOC_MMU_DROM0_LINEAR), CACHE_BUS_DBUS0, MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT}, + //Can be used for PSRAM + {SOC_MMU_DRAM1_LINEAR_ADDRESS_LOW, SOC_MMU_DRAM1_LINEAR_ADDRESS_HIGH, BUS_SIZE(SOC_MMU_DRAM1_LINEAR), CACHE_BUS_DBUS1, MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT}, +}; + + +#elif CONFIG_IDF_TARGET_ESP32S2 +/** + * These regions is referring to linear address + * The start addresses in this list should always be sorted from low to high, as MMU driver will need to + * coalesce adjacent regions + */ +const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = { + + /*linear start linear end bus size bus ID, bus capabilities */ + + //Can be used for text + {SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW, SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH, BUS_SIZE(SOC_MMU_IRAM0_LINEAR), CACHE_BUS_IBUS0, MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT}, + //Can be used for text + {SOC_MMU_IRAM1_LINEAR_ADDRESS_LOW, SOC_MMU_IRAM1_LINEAR_ADDRESS_HIGH, BUS_SIZE(SOC_MMU_IRAM1_LINEAR), CACHE_BUS_IBUS1, MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT}, + //Can be used for Flash rodata, connected by IBUS + {SOC_MMU_DROM0_LINEAR_ADDRESS_LOW, SOC_MMU_DROM0_LINEAR_ADDRESS_HIGH, BUS_SIZE(SOC_MMU_DROM0_LINEAR), CACHE_BUS_IBUS2, MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT}, + //Can be used for PSRAM + {SOC_MMU_DPORT_LINEAR_ADDRESS_LOW, SOC_MMU_DPORT_LINEAR_ADDRESS_HIGH, BUS_SIZE(SOC_MMU_DPORT_LINEAR), CACHE_BUS_DBUS2, MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT}, + //Can be used for PSRAM + {SOC_MMU_DRAM1_LINEAR_ADDRESS_LOW, SOC_MMU_DRAM1_LINEAR_ADDRESS_HIGH, BUS_SIZE(SOC_MMU_DRAM1_LINEAR), CACHE_BUS_DBUS1, MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT}, + //Can be used for PSRAM + {SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH, BUS_SIZE(SOC_MMU_DRAM0_LINEAR), CACHE_BUS_DBUS0, MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT}, +}; + + +#elif CONFIG_IDF_TARGET_ESP32S3 +/** + * The start addresses in this list should always be sorted from low to high, as MMU driver will need to + * coalesce adjacent regions + */ +const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = { + + /*linear start linear end bus size bus ID, bus capabilities */ + + /** + * Can be used for Flash text, rodata, and PSRAM + * IRAM0 linear address should be always the same as DRAM0 linear address + */ + {SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW, SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH, BUS_SIZE(SOC_MMU_IRAM0_LINEAR), CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0, MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT}, +}; +#endif diff --git a/components/esp_psram/ext_mem_layout.h b/components/esp_psram/ext_mem_layout.h new file mode 100644 index 0000000000..539b3cc520 --- /dev/null +++ b/components/esp_psram/ext_mem_layout.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once +#include +#include +#include +#include "sdkconfig.h" +#include "soc/soc_caps.h" +#include "hal/cache_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +typedef struct { + intptr_t start; + intptr_t end; + size_t size; + cache_bus_mask_t bus_id; + uint32_t caps; +} mmu_mem_region_t; + +//These regions is referring to linear address +extern const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM]; + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_psram/include/esp_private/esp_psram_extram.h b/components/esp_psram/include/esp_private/esp_psram_extram.h index a05a371c76..5cd7e52a15 100644 --- a/components/esp_psram/include/esp_private/esp_psram_extram.h +++ b/components/esp_psram/include/esp_private/esp_psram_extram.h @@ -15,32 +15,15 @@ extern "C" { #endif /** - * @brief Get the psram mapped vaddr range + * @brief Check if the pointer is on PSRAM * - * @param[out] out_vstart PSRAM virtual address start - * @param[out] out_vend PSRAM virtual address end - * - * @note [out_vstart, out_vend), `out_vend` isn't included. + * @param[in] p The pointer to check * * @return - * - ESP_OK On success - * - ESP_ERR_INVALID_STATE PSRAM is not initialized successfully + * - False: the pointer isn't on PSRAM, or PSRAM isn't initialised successfully + * - True: the pointer is on PSRAM */ -esp_err_t esp_psram_extram_get_mapped_range(intptr_t *out_vstart, intptr_t *out_vend); - -/** - * @brief Get the psram alloced vaddr range - * - * @param[out] out_vstart PSRAM virtual address start - * @param[out] out_vend PSRAM virtual address end - * - * @note [out_vstart, out_vend), `out_vend` isn't included. - * - * @return - * - ESP_OK On success - * - ESP_ERR_INVALID_STATE PSRAM is not initialized successfully - */ -esp_err_t esp_psram_extram_get_alloced_range(intptr_t *out_vstart, intptr_t *out_vend); +bool esp_psram_check_ptr_addr(const void *p); /** * @brief Add the initialized PSRAM to the heap allocator. diff --git a/components/esp_psram/include/esp_private/mmu.h b/components/esp_psram/include/esp_private/mmu_psram_flash.h similarity index 74% rename from components/esp_psram/include/esp_private/mmu.h rename to components/esp_psram/include/esp_private/mmu_psram_flash.h index 1925f388ed..9c0b62ee2b 100644 --- a/components/esp_psram/include/esp_private/mmu.h +++ b/components/esp_psram/include/esp_private/mmu_psram_flash.h @@ -5,13 +5,16 @@ */ /** - * This file will be redesigned into MMU driver, to maintain all the external - * memory contexts including: - * - Flash - * - PSRAM - * - DDR + * @Backgrounds * - * Now only MMU-PSRAM related private APIs + * This file contains 2 parts: + * 1. Feature: Copy Flash content to PSRAM. Related APIs are private: + * - mmu_config_psram_text_segment() + * - mmu_config_psram_rodata_segment() + * + * 2. Private APIs used by `flash_mmap.c` and `cache_utils.c` + * APIs in 2 are due to lack of MMU driver. There will be an MMU driver to maintain vaddr range. + * APIs in 2 will be refactored when MMU driver is ready */ #pragma once @@ -32,21 +35,9 @@ extern "C" { #define BYTES_TO_MMU_PAGE(bytes) ((bytes) / MMU_PAGE_SIZE) #endif -/** - * @brief Get the vaddr start for PSRAM - * - * @return PSRAM vaddr start address - */ -intptr_t mmu_get_psram_vaddr_start(void); - -/** - * @brief Get the vaddr end for PSRAM - * - * @return PSRAM vaddr end address - */ -intptr_t mmu_get_psram_vaddr_end(void); - - +/*---------------------------------------------------------------------------- + Part 1 APIs (See @Backgrounds on top of this file) +-------------------------------------------------------------------------------*/ #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS /** * @brief Copy Flash texts to PSRAM @@ -56,7 +47,24 @@ intptr_t mmu_get_psram_vaddr_end(void); * @param[out] out_page Used pages */ esp_err_t mmu_config_psram_text_segment(uint32_t start_page, uint32_t psram_size, uint32_t *out_page); +#endif //#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS +#if CONFIG_SPIRAM_RODATA +/** + * @brief Copy Flash rodata to PSRAM + * + * @param[in] start_page PSRAM physical start page + * @param[in] psram_size PSRAM available size + * @param[out] out_page Used pages + */ +esp_err_t mmu_config_psram_rodata_segment(uint32_t start_page, uint32_t psram_size, uint32_t *out_page); +#endif //#if CONFIG_SPIRAM_RODATA + + +/*---------------------------------------------------------------------------- + Part 2 APIs (See @Backgrounds on top of this file) +-------------------------------------------------------------------------------*/ +#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS /** * @brief Init other file requested MMU variables * @@ -90,17 +98,7 @@ uint32_t instruction_flash_end_page_get(void); int instruction_flash2spiram_offset(void); #endif // #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS - #if CONFIG_SPIRAM_RODATA -/** - * @brief Copy Flash rodata to PSRAM - * - * @param[in] start_page PSRAM physical start page - * @param[in] psram_size PSRAM available size - * @param[out] out_page Used pages - */ -esp_err_t mmu_config_psram_rodata_segment(uint32_t start_page, uint32_t psram_size, uint32_t *out_page); - /** * @brief Init other file requested MMU variables * diff --git a/components/esp_psram/linker.lf b/components/esp_psram/linker.lf index eee8cda0f5..f290b41bea 100644 --- a/components/esp_psram/linker.lf +++ b/components/esp_psram/linker.lf @@ -14,4 +14,4 @@ entries: esp_psram_impl_octal (noflash) if IDF_TARGET_ESP32S2 = y || IDF_TARGET_ESP32S3 = y: - mmu_psram (noflash) + mmu_psram_flash (noflash) diff --git a/components/esp_psram/mmu.c b/components/esp_psram/mmu.c index 3953c6bc91..74d9a488fc 100644 --- a/components/esp_psram/mmu.c +++ b/components/esp_psram/mmu.c @@ -15,157 +15,253 @@ */ #include +#include #include #include "sdkconfig.h" #include "esp_attr.h" #include "esp_log.h" -#include "soc/ext_mem_defs.h" -#include "esp_private/mmu.h" - -#if CONFIG_IDF_TARGET_ESP32S2 -#include "soc/extmem_reg.h" -#include "esp32s2/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32S3 -#include "soc/extmem_reg.h" -#include "esp32s3/rom/cache.h" -#endif +#include "esp_check.h" +#include "soc/soc_caps.h" +#include "ext_mem_layout.h" +#include "freertos/FreeRTOS.h" +#include "hal/cache_types.h" +#include "hal/cache_ll.h" +#include "hal/mmu_types.h" +#include "hal/mmu_ll.h" +#include "mmu.h" #define ALIGN_UP_BY(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) -__attribute__((unused)) static const char *TAG = "mmu"; +#define MMU_PAGE_SIZE CONFIG_MMU_PAGE_SIZE + +//This flag indicates the memory region is merged, we don't care about it anymore +#define MEM_REGION_MERGED -1 + +static const char *TAG = "mmu"; extern int _instruction_reserved_start; extern int _instruction_reserved_end; extern int _rodata_reserved_start; extern int _rodata_reserved_end; +typedef struct mmu_linear_mem_ { + cache_bus_mask_t bus_id; + intptr_t start; + intptr_t end; + size_t pool_size; + intptr_t free_head; + size_t free_size; + int caps; +} mmu_linear_mem_t; -intptr_t mmu_get_psram_vaddr_start(void) +typedef struct { + /** + * number of memory regions that are available, after coalescing, this number should be smaller than or equal to `SOC_MMU_LINEAR_ADDRESS_REGION_NUM` + */ + uint32_t num_regions; + /** + * This saves the available MMU linear address regions, + * after reserving flash .rodata and .text, and after coalescing. + * Only the first `num_regions` items are valid + */ + mmu_linear_mem_t mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM]; +} mmu_ctx_t; + +static mmu_ctx_t s_mmu_ctx; + + +static void s_reserve_irom_region(mmu_linear_mem_t *hw_mem_regions, int region_nums) { -#if CONFIG_IDF_TARGET_ESP32S3 + /** + * We follow the way how 1st bootloader load flash .text: + * + * - Now IBUS addresses (between `_instruction_reserved_start` and `_instruction_reserved_end`) are consecutive on all chips, + * we strongly rely on this to calculate the .text length + */ + size_t irom_len_to_reserve = (uint32_t)&_instruction_reserved_end - (uint32_t)&_instruction_reserved_start; + assert((mmu_ll_vaddr_to_laddr((uint32_t)&_instruction_reserved_end) - mmu_ll_vaddr_to_laddr((uint32_t)&_instruction_reserved_start)) == irom_len_to_reserve); - intptr_t rodata_end_aligned = ALIGN_UP_BY((intptr_t)&_rodata_reserved_end, MMU_PAGE_SIZE); - ESP_EARLY_LOGV(TAG, "rodata_end_aligned is 0x%x bytes", rodata_end_aligned); - return rodata_end_aligned; + irom_len_to_reserve = ALIGN_UP_BY(irom_len_to_reserve, MMU_PAGE_SIZE); + cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, (uint32_t)&_instruction_reserved_start, irom_len_to_reserve); -#elif CONFIG_IDF_TARGET_ESP32S2 - return DPORT_CACHE_ADDRESS_LOW; -#else //CONFIG_IDF_TARGET_ESP32 - return DRAM1_CACHE_ADDRESS_LOW; + for (int i = 0; i < SOC_MMU_LINEAR_ADDRESS_REGION_NUM; i++) { + if (bus_mask & hw_mem_regions[i].bus_id) { + if (hw_mem_regions[i].pool_size <= irom_len_to_reserve) { + hw_mem_regions[i].free_head = hw_mem_regions[i].end; + hw_mem_regions[i].free_size = 0; + irom_len_to_reserve -= hw_mem_regions[i].pool_size; + } else { + hw_mem_regions[i].free_head = hw_mem_regions[i].free_head + irom_len_to_reserve; + hw_mem_regions[i].free_size -= irom_len_to_reserve; + } + } + } +} + +static void s_reserve_drom_region(mmu_linear_mem_t *hw_mem_regions, int region_nums) +{ + /** + * Similarly, we follow the way how 1st bootloader load flash .rodata: + */ + size_t drom_len_to_reserve = (uint32_t)&_rodata_reserved_end - (uint32_t)&_rodata_reserved_start; + assert((mmu_ll_vaddr_to_laddr((uint32_t)&_rodata_reserved_end) - mmu_ll_vaddr_to_laddr((uint32_t)&_rodata_reserved_start)) == drom_len_to_reserve); + + drom_len_to_reserve = ALIGN_UP_BY(drom_len_to_reserve, MMU_PAGE_SIZE); + cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, (uint32_t)&_rodata_reserved_start, drom_len_to_reserve); + + for (int i = 0; i < SOC_MMU_LINEAR_ADDRESS_REGION_NUM; i++) { + if (bus_mask & hw_mem_regions[i].bus_id) { + if (hw_mem_regions[i].pool_size <= drom_len_to_reserve) { + hw_mem_regions[i].free_head = hw_mem_regions[i].end; + hw_mem_regions[i].free_size = 0; + drom_len_to_reserve -= hw_mem_regions[i].pool_size; + } else { + hw_mem_regions[i].free_head = hw_mem_regions[i].free_head + drom_len_to_reserve; + hw_mem_regions[i].free_size -= drom_len_to_reserve; + } + } + } +} + +void esp_mmu_init(void) +{ + mmu_linear_mem_t hw_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {}; + + for (int i = 0; i < SOC_MMU_LINEAR_ADDRESS_REGION_NUM; i++) { + hw_mem_regions[i].start = g_mmu_mem_regions[i].start; + hw_mem_regions[i].end = g_mmu_mem_regions[i].end; + hw_mem_regions[i].pool_size = g_mmu_mem_regions[i].size; + hw_mem_regions[i].free_size = g_mmu_mem_regions[i].size; + hw_mem_regions[i].free_head = g_mmu_mem_regions[i].start; + hw_mem_regions[i].bus_id = g_mmu_mem_regions[i].bus_id; + hw_mem_regions[i].caps = g_mmu_mem_regions[i].caps; +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 + assert(__builtin_popcount(hw_mem_regions[i].bus_id) == 1); #endif + assert(hw_mem_regions[i].pool_size % MMU_PAGE_SIZE == 0); + } + + //First reserve memory regions used for irom and drom, as we must follow the way how 1st bootloader load them + s_reserve_irom_region(hw_mem_regions, SOC_MMU_LINEAR_ADDRESS_REGION_NUM); + s_reserve_drom_region(hw_mem_regions, SOC_MMU_LINEAR_ADDRESS_REGION_NUM); + + if (SOC_MMU_LINEAR_ADDRESS_REGION_NUM > 1) { + //Now we can coalesce adjacent regions + for (int i = 1; i < SOC_MMU_LINEAR_ADDRESS_REGION_NUM; i++) { + mmu_linear_mem_t *a = &hw_mem_regions[i - 1]; + mmu_linear_mem_t *b = &hw_mem_regions[i]; + if ((b->free_head == a->end) && (b->caps == a->caps)) { + a->caps = MEM_REGION_MERGED; + b->bus_id |= a->bus_id; + b->start = a->start; + b->pool_size += a->pool_size; + b->free_head = a->free_head; + b->free_size += a->free_size; + } + } + } + + //Count the mem regions left after coalescing + uint32_t region_num = 0; + for (int i = 0; i < SOC_MMU_LINEAR_ADDRESS_REGION_NUM; i++) { + if(hw_mem_regions[i].caps != MEM_REGION_MERGED) { + region_num++; + } + } + ESP_EARLY_LOGV(TAG, "after coalescing, %d regions are left", region_num); + + //Initialise `s_mmu_ctx.mem_regions[]`, as we've done all static allocation, to prepare available virtual memory regions + uint32_t available_region_idx = 0; + s_mmu_ctx.num_regions = region_num; + for (int i = 0; i < SOC_MMU_LINEAR_ADDRESS_REGION_NUM; i++) { + if (hw_mem_regions[i].caps == MEM_REGION_MERGED) { + continue; + } + + memcpy(&s_mmu_ctx.mem_regions[available_region_idx], &hw_mem_regions[i], sizeof(mmu_linear_mem_t)); + available_region_idx++; + } + + assert(available_region_idx == region_num); } -intptr_t mmu_get_psram_vaddr_end(void) +esp_err_t esp_mmu_get_largest_free_block(int caps, size_t *out_len) { -#if CONFIG_IDF_TARGET_ESP32S3 - return DRAM0_CACHE_ADDRESS_HIGH; -#elif CONFIG_IDF_TARGET_ESP32S2 - return DRAM0_CACHE_ADDRESS_HIGH; -#else //CONFIG_IDF_TARGET_ESP32 - return DRAM1_CACHE_ADDRESS_HIGH; -#endif + ESP_RETURN_ON_FALSE(out_len, ESP_ERR_INVALID_ARG, TAG, "null pointer"); + if (caps & MMU_MEM_CAP_EXEC) { + if ((caps & MMU_MEM_CAP_8BIT) || (caps & MMU_MEM_CAP_WRITE)) { + //None of the executable memory are expected to be 8-bit accessible or writable. + return ESP_ERR_INVALID_ARG; + } + } + *out_len = 0; + + size_t max = 0; + + for (int i = 0; i < s_mmu_ctx.num_regions; i++) { + if ((s_mmu_ctx.mem_regions[i].caps & caps) == caps) { + if (s_mmu_ctx.mem_regions[i].free_size > max) { + max = s_mmu_ctx.mem_regions[i].free_size; + } + } + } + + *out_len = max; + + return ESP_OK; } -//------------------------------------Copy Flash .text to PSRAM-------------------------------------// -#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS -static uint32_t instruction_in_spiram; -static uint32_t instr_start_page; -static uint32_t instr_end_page; -static int instr_flash2spiram_offs; - -/** - * - These logics are abstracted from the PSRAM driver - * - These functions are only required by `flash_mmap.c` for converting paddr to vaddr, and vice versa - * - The `flash_mmpa.c` will be rewritten into MMU driver - * - * Therefore, keep the APIs here for now - */ -void instruction_flash_page_info_init(uint32_t psram_start_physical_page) +esp_err_t esp_mmu_find_vaddr_range(size_t size, uint32_t caps, const void **out_ptr) { -#if CONFIG_IDF_TARGET_ESP32S2 - uint32_t instr_page_cnt = ((uint32_t)&_instruction_reserved_end - (uint32_t)&_instruction_reserved_start + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE; - uint32_t instr_mmu_offset = ((uint32_t)&_instruction_reserved_start & MMU_VADDR_MASK) / MMU_PAGE_SIZE; - instr_start_page = ((volatile uint32_t *)(DR_REG_MMU_TABLE + PRO_CACHE_IBUS0_MMU_START))[instr_mmu_offset]; -#elif CONFIG_IDF_TARGET_ESP32S3 - uint32_t instr_page_cnt = ((uint32_t)&_instruction_reserved_end - SOC_IROM_LOW + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE; - instr_start_page = *((volatile uint32_t *)(DR_REG_MMU_TABLE + CACHE_IROM_MMU_START)); -#endif - instr_start_page &= MMU_VALID_VAL_MASK; - instr_end_page = instr_start_page + instr_page_cnt - 1; - instr_flash2spiram_offs = instr_start_page - psram_start_physical_page; - instruction_in_spiram = 1; - ESP_DRAM_LOGV("mmu_psram", "Instructions from flash page%d copy to SPIRAM page%d, Offset: %d", instr_start_page, psram_start_physical_page, instr_flash2spiram_offs); + ESP_RETURN_ON_FALSE(out_ptr, ESP_ERR_INVALID_ARG, TAG, "null pointer"); + if (caps & MMU_MEM_CAP_EXEC) { + if ((caps & MMU_MEM_CAP_8BIT) || (caps & MMU_MEM_CAP_WRITE)) { + //None of the executable memory are expected to be 8-bit accessible or writable. + return ESP_ERR_INVALID_ARG; + } + caps |= MMU_MEM_CAP_32BIT; + } + + size_t aligned_size = ALIGN_UP_BY(size, MMU_PAGE_SIZE); + bool is_match = false; + uint32_t laddr = 0; + + for (int i = 0; i < s_mmu_ctx.num_regions; i++) { + if ((s_mmu_ctx.mem_regions[i].caps & caps) == caps) { + if (s_mmu_ctx.mem_regions[i].free_size < aligned_size) { + continue; + } else { + laddr = (uint32_t)s_mmu_ctx.mem_regions[i].free_head; + s_mmu_ctx.mem_regions[i].free_head += aligned_size; + s_mmu_ctx.mem_regions[i].free_size -= aligned_size; + is_match = true; + break; + } + } + } + ESP_RETURN_ON_FALSE(is_match, ESP_ERR_NOT_FOUND, TAG, "no such vaddr range"); + ESP_EARLY_LOGV(TAG, "found laddr is 0x%x", laddr); + + if (caps & MMU_MEM_CAP_EXEC) { + laddr = mmu_ll_laddr_to_vaddr(laddr, MMU_VADDR_INSTRUCTION); + } else { + laddr = mmu_ll_laddr_to_vaddr(laddr, MMU_VADDR_DATA); + } + *out_ptr = (void *)laddr; + + return ESP_OK; } -uint32_t esp_spiram_instruction_access_enabled(void) +esp_err_t esp_mmu_dump_region_usage(void) { - return instruction_in_spiram; + for (int i = 0; i < s_mmu_ctx.num_regions; i++) { + ESP_EARLY_LOGI(TAG, "bus_id: 0x%x", s_mmu_ctx.mem_regions[i].bus_id); + ESP_EARLY_LOGI(TAG, "start: 0x%x", s_mmu_ctx.mem_regions[i].start); + ESP_EARLY_LOGI(TAG, "end: 0x%x", s_mmu_ctx.mem_regions[i].end); + ESP_EARLY_LOGI(TAG, "pool_size: 0x%x", s_mmu_ctx.mem_regions[i].pool_size); + ESP_EARLY_LOGI(TAG, "free_head: 0x%x", s_mmu_ctx.mem_regions[i].free_head); + ESP_EARLY_LOGI(TAG, "free_size: 0x%x", s_mmu_ctx.mem_regions[i].free_size); + ESP_EARLY_LOGI(TAG, "caps: 0x%x\n", s_mmu_ctx.mem_regions[i].caps); + } + + return ESP_OK; } - -int instruction_flash2spiram_offset(void) -{ - return instr_flash2spiram_offs; -} - -uint32_t instruction_flash_start_page_get(void) -{ - return instr_start_page; -} - -uint32_t instruction_flash_end_page_get(void) -{ - return instr_end_page; -} -#endif //CONFIG_SPIRAM_FETCH_INSTRUCTIONS - - -#if CONFIG_SPIRAM_RODATA -//------------------------------------Copy Flash .rodata to PSRAM-------------------------------------// -static uint32_t rodata_in_spiram; -static int rodata_flash2spiram_offs; -static uint32_t rodata_start_page; -static uint32_t rodata_end_page; - -/** - * - These logics are abstracted from the PSRAM driver - * - These functions are only required by `flash_mmap.c` for converting paddr to vaddr, and vice versa - * - The `flash_mmpa.c` will be rewritten into MMU driver - * - * Therefore, keep the APIs here for now - */ -void rodata_flash_page_info_init(uint32_t psram_start_physical_page) -{ -#if CONFIG_IDF_TARGET_ESP32S2 - uint32_t rodata_page_cnt = ((uint32_t)&_rodata_reserved_end - (uint32_t)&_rodata_reserved_start + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE; - uint32_t rodata_mmu_offset = ((uint32_t)&_rodata_reserved_start & MMU_VADDR_MASK) / MMU_PAGE_SIZE; - rodata_start_page = ((volatile uint32_t *)(DR_REG_MMU_TABLE + PRO_CACHE_IBUS2_MMU_START))[rodata_mmu_offset]; -#elif CONFIG_IDF_TARGET_ESP32S3 - uint32_t rodata_page_cnt = ((uint32_t)&_rodata_reserved_end - ((uint32_t)&_rodata_reserved_start & ~ (MMU_PAGE_SIZE - 1)) + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE; - rodata_start_page = *(volatile uint32_t *)(DR_REG_MMU_TABLE + CACHE_DROM_MMU_START); -#endif - rodata_start_page &= MMU_VALID_VAL_MASK; - rodata_end_page = rodata_start_page + rodata_page_cnt - 1; - rodata_flash2spiram_offs = rodata_start_page - psram_start_physical_page; - rodata_in_spiram = 1; - ESP_DRAM_LOGV("mmu_psram", "Rodata from flash page%d copy to SPIRAM page%d, Offset: %d", rodata_start_page, psram_start_physical_page, rodata_flash2spiram_offs); -} - -uint32_t esp_spiram_rodata_access_enabled(void) -{ - return rodata_in_spiram; -} - -int rodata_flash2spiram_offset(void) -{ - return rodata_flash2spiram_offs; -} - -uint32_t rodata_flash_start_page_get(void) -{ - return rodata_start_page; -} - -uint32_t rodata_flash_end_page_get(void) -{ - return rodata_end_page; -} -#endif //#if CONFIG_SPIRAM_RODATA diff --git a/components/esp_psram/mmu.h b/components/esp_psram/mmu.h new file mode 100644 index 0000000000..98dab60230 --- /dev/null +++ b/components/esp_psram/mmu.h @@ -0,0 +1,76 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * This file will be moved out of `esp_psram` component. And will be + * future MMU driver, to maintain all the external memory contexts including: + * - Flash + * - PSRAM + * - DDR + * + * Now only support ESP32, ESP32S2, ESP32S3 virtual address maintenance, and is internal + */ + + +#define MMU_MEM_CAP_EXEC (1<<0) +#define MMU_MEM_CAP_READ (1<<1) +#define MMU_MEM_CAP_WRITE (1<<2) +#define MMU_MEM_CAP_32BIT (1<<3) +#define MMU_MEM_CAP_8BIT (1<<4) + +/** + * @brief Initialise the MMU driver + * + * This is called once in the IDF startup code. Don't call it in applications + */ +void esp_mmu_init(void); + +/** + * @brief Get largest consecutive free external virtual memory block, with given capabilities + * + * @param[in] caps Bitwise OR of MMU_MEM_CAP_* flags indicating the memory block + * @param[out] out_len Largest free block length, in bytes. + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid arguments, could be null pointer + */ +esp_err_t esp_mmu_get_largest_free_block(int caps, size_t *out_len); + +/** + * @brief Find a consecutive external virtual memory range, with given capabilities and size + * + * @param[in] size Size, in bytes, the amount of memory to find + * @param[in] caps Bitwise OR of MMU_MEM_CAP_* flags indicating the memory block + * @param[out] out_ptr Pointer to the memory range found + * + * @return + * - ESP_OK: On success + * - ESP_ERR_INVALID_ARG: Invalid arguments, could be wrong caps makeup, or null pointer + * - ESP_ERR_NOT_FOUND: Didn't find enough memory with give caps + */ +esp_err_t esp_mmu_find_vaddr_range(size_t size, uint32_t caps, const void **out_ptr); + +/** + * @brief Dump internal memory region usage + * + * @return + * - ESP_OK: On success + */ +esp_err_t esp_mmu_dump_region_usage(void); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_psram/mmu_psram.c b/components/esp_psram/mmu_psram_flash.c similarity index 50% rename from components/esp_psram/mmu_psram.c rename to components/esp_psram/mmu_psram_flash.c index 3f690bf68c..beff0fa0ac 100644 --- a/components/esp_psram/mmu_psram.c +++ b/components/esp_psram/mmu_psram_flash.c @@ -3,15 +3,17 @@ * * SPDX-License-Identifier: Apache-2.0 */ - /** - * This file will be redesigned into MMU driver, to maintain all the external - * memory contexts including: - * - Flash - * - PSRAM - * - DDR + * @Backgrounds * - * Now only MMU-PSRAM related private APIs + * This file contains 2 parts: + * 1. Feature: Copy Flash content to PSRAM. Related APIs are private: + * - mmu_config_psram_text_segment() + * - mmu_config_psram_rodata_segment() + * + * 2. Private APIs used by `flash_mmap.c` and `cache_utils.c` + * APIs in 2 are due to lack of MMU driver. There will be an MMU driver to maintain vaddr range. + * APIs in 2 will be refactored when MMU driver is ready */ #include @@ -21,7 +23,7 @@ #include "soc/ext_mem_defs.h" #include "hal/cache_types.h" #include "hal/cache_ll.h" -#include "esp_private/mmu.h" +#include "esp_private/mmu_psram_flash.h" #if CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/cache.h" @@ -29,7 +31,9 @@ #include "esp32s3/rom/cache.h" #endif - +/*---------------------------------------------------------------------------- + Part 1 APIs (See @Backgrounds on top of this file) +-------------------------------------------------------------------------------*/ #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS || CONFIG_SPIRAM_RODATA //page_size - 1, where page_size on s2 and s3 is always 0x10000. To be refactored by MMU driver #define INVALID_PHY_PAGE 0xffff @@ -144,3 +148,117 @@ esp_err_t mmu_config_psram_rodata_segment(uint32_t start_page, uint32_t psram_si return ESP_OK; } #endif //#if CONFIG_SPIRAM_RODATA + + +/*---------------------------------------------------------------------------- + Part 2 APIs (See @Backgrounds on top of this file) +-------------------------------------------------------------------------------*/ +extern int _instruction_reserved_start; +extern int _instruction_reserved_end; +extern int _rodata_reserved_start; +extern int _rodata_reserved_end; + +//------------------------------------Copy Flash .text to PSRAM-------------------------------------// +#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS +static uint32_t instruction_in_spiram; +static uint32_t instr_start_page; +static uint32_t instr_end_page; +static int instr_flash2spiram_offs; + +/** + * - These logics are abstracted from the PSRAM driver + * - These functions are only required by `flash_mmap.c` for converting paddr to vaddr, and vice versa + * - The `flash_mmpa.c` will be rewritten into MMU driver + * + * Therefore, keep the APIs here for now + */ +void instruction_flash_page_info_init(uint32_t psram_start_physical_page) +{ +#if CONFIG_IDF_TARGET_ESP32S2 + uint32_t instr_page_cnt = ((uint32_t)&_instruction_reserved_end - (uint32_t)&_instruction_reserved_start + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE; + uint32_t instr_mmu_offset = ((uint32_t)&_instruction_reserved_start & MMU_VADDR_MASK) / MMU_PAGE_SIZE; + instr_start_page = ((volatile uint32_t *)(DR_REG_MMU_TABLE + PRO_CACHE_IBUS0_MMU_START))[instr_mmu_offset]; +#elif CONFIG_IDF_TARGET_ESP32S3 + uint32_t instr_page_cnt = ((uint32_t)&_instruction_reserved_end - SOC_IROM_LOW + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE; + instr_start_page = *((volatile uint32_t *)(DR_REG_MMU_TABLE + CACHE_IROM_MMU_START)); +#endif + instr_start_page &= MMU_VALID_VAL_MASK; + instr_end_page = instr_start_page + instr_page_cnt - 1; + instr_flash2spiram_offs = instr_start_page - psram_start_physical_page; + instruction_in_spiram = 1; + ESP_DRAM_LOGV("mmu_psram", "Instructions from flash page%d copy to SPIRAM page%d, Offset: %d", instr_start_page, psram_start_physical_page, instr_flash2spiram_offs); +} + +uint32_t esp_spiram_instruction_access_enabled(void) +{ + return instruction_in_spiram; +} + +int instruction_flash2spiram_offset(void) +{ + return instr_flash2spiram_offs; +} + +uint32_t instruction_flash_start_page_get(void) +{ + return instr_start_page; +} + +uint32_t instruction_flash_end_page_get(void) +{ + return instr_end_page; +} +#endif //CONFIG_SPIRAM_FETCH_INSTRUCTIONS + + +#if CONFIG_SPIRAM_RODATA +//------------------------------------Copy Flash .rodata to PSRAM-------------------------------------// +static uint32_t rodata_in_spiram; +static int rodata_flash2spiram_offs; +static uint32_t rodata_start_page; +static uint32_t rodata_end_page; + +/** + * - These logics are abstracted from the PSRAM driver + * - These functions are only required by `flash_mmap.c` for converting paddr to vaddr, and vice versa + * - The `flash_mmpa.c` will be rewritten into MMU driver + * + * Therefore, keep the APIs here for now + */ +void rodata_flash_page_info_init(uint32_t psram_start_physical_page) +{ +#if CONFIG_IDF_TARGET_ESP32S2 + uint32_t rodata_page_cnt = ((uint32_t)&_rodata_reserved_end - (uint32_t)&_rodata_reserved_start + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE; + uint32_t rodata_mmu_offset = ((uint32_t)&_rodata_reserved_start & MMU_VADDR_MASK) / MMU_PAGE_SIZE; + rodata_start_page = ((volatile uint32_t *)(DR_REG_MMU_TABLE + PRO_CACHE_IBUS2_MMU_START))[rodata_mmu_offset]; +#elif CONFIG_IDF_TARGET_ESP32S3 + uint32_t rodata_page_cnt = ((uint32_t)&_rodata_reserved_end - ((uint32_t)&_rodata_reserved_start & ~ (MMU_PAGE_SIZE - 1)) + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE; + rodata_start_page = *(volatile uint32_t *)(DR_REG_MMU_TABLE + CACHE_DROM_MMU_START); +#endif + rodata_start_page &= MMU_VALID_VAL_MASK; + rodata_end_page = rodata_start_page + rodata_page_cnt - 1; + rodata_flash2spiram_offs = rodata_start_page - psram_start_physical_page; + rodata_in_spiram = 1; + ESP_DRAM_LOGV("mmu_psram", "Rodata from flash page%d copy to SPIRAM page%d, Offset: %d", rodata_start_page, psram_start_physical_page, rodata_flash2spiram_offs); +} + +uint32_t esp_spiram_rodata_access_enabled(void) +{ + return rodata_in_spiram; +} + +int rodata_flash2spiram_offset(void) +{ + return rodata_flash2spiram_offs; +} + +uint32_t rodata_flash_start_page_get(void) +{ + return rodata_start_page; +} + +uint32_t rodata_flash_end_page_get(void) +{ + return rodata_end_page; +} +#endif //#if CONFIG_SPIRAM_RODATA diff --git a/components/esp_psram/test_apps/psram/main/CMakeLists.txt b/components/esp_psram/test_apps/psram/main/CMakeLists.txt index 2b91168afb..7fa3034028 100644 --- a/components/esp_psram/test_apps/psram/main/CMakeLists.txt +++ b/components/esp_psram/test_apps/psram/main/CMakeLists.txt @@ -11,4 +11,3 @@ endif() # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} WHOLE_ARCHIVE) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/components/esp_psram/test_apps/psram/main/test_himem.c b/components/esp_psram/test_apps/psram/main/test_himem.c index 369b9e7b9e..6f0d658f1f 100644 --- a/components/esp_psram/test_apps/psram/main/test_himem.c +++ b/components/esp_psram/test_apps/psram/main/test_himem.c @@ -7,6 +7,7 @@ #include #include #include +#include "inttypes.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "esp_system.h" @@ -36,7 +37,7 @@ static bool check_mem_seed(int seed, void *mem, int len) for (int i = 0; i < len / 4; i++) { uint32_t ex = rand_r(&rseed); if (ex != *p) { - printf("check_mem_seed: %p @ %p has 0x%08x expected 0x%08x\n", mem, p, *p, ex); + printf("check_mem_seed: %p @ %p has 0x%08"PRIx32" expected 0x%08"PRIx32"\n", mem, p, *p, ex); return false; } p++; diff --git a/components/esp_psram/test_apps/psram/main/test_psram.c b/components/esp_psram/test_apps/psram/main/test_psram.c index 1bb8b587ec..3b2e730726 100644 --- a/components/esp_psram/test_apps/psram/main/test_psram.c +++ b/components/esp_psram/test_apps/psram/main/test_psram.c @@ -7,6 +7,7 @@ #include "sdkconfig.h" #include #include +#include "inttypes.h" #include "esp_log.h" #include "esp_attr.h" #include "freertos/FreeRTOS.h" @@ -20,35 +21,24 @@ __attribute__((unused)) const static char *TAG = "PSRAM"; -#if CONFIG_SPIRAM_MODE_OCT -#define TEST_ALLOC_SIZE (4 * 1024 * 1024) -#else -#define TEST_ALLOC_SIZE (1 * 1024 * 1024) -#endif - -static bool s_check_valid_psram_alloced_range(const void *p) -{ - intptr_t vaddr_start = 0; - intptr_t vaddr_end = 0; - esp_psram_extram_get_alloced_range(&vaddr_start, &vaddr_end); - return (intptr_t)p >= vaddr_start && (intptr_t)p < vaddr_end; -} - TEST_CASE("test psram heap allocable","[psram]") { - uint32_t *ext_buffer = (uint32_t *)heap_caps_calloc(TEST_ALLOC_SIZE, 1, MALLOC_CAP_SPIRAM); + size_t largest_size = heap_caps_get_largest_free_block(MALLOC_CAP_SPIRAM); + ESP_LOGI(TAG, "largest size is %zu", largest_size); + + uint32_t *ext_buffer = (uint32_t *)heap_caps_calloc(largest_size, 1, MALLOC_CAP_SPIRAM); TEST_ASSERT(ext_buffer); - uintptr_t start = (uintptr_t)ext_buffer; - uintptr_t end = (uintptr_t)ext_buffer + TEST_ALLOC_SIZE; - ESP_LOGI(TAG, "test ext buffer start addr is 0x%x, end addr is 0x%x", start, end); - TEST_ASSERT(s_check_valid_psram_alloced_range((void *)start) && s_check_valid_psram_alloced_range((void *)end)); + intptr_t start = (intptr_t)ext_buffer; + intptr_t end = (intptr_t)ext_buffer + largest_size; + ESP_LOGI(TAG, "test ext buffer start addr is 0x%"PRIxPTR", end addr is 0x%"PRIxPTR, start, end); + TEST_ASSERT(esp_psram_check_ptr_addr((void *)start) && esp_psram_check_ptr_addr((void *)end)); - for (int i = 0; i < TEST_ALLOC_SIZE / sizeof(uint32_t); i++) { + for (int i = 0; i < largest_size / sizeof(uint32_t); i++) { ext_buffer[i] = (i + 1) ^ 0xaaaaaaaa; } - for (int i = 0; i < TEST_ALLOC_SIZE / sizeof(uint32_t); i++) { + for (int i = 0; i < largest_size / sizeof(uint32_t); i++) { TEST_ASSERT(ext_buffer[i] == ((i + 1) ^ 0xaaaaaaaa)); } @@ -92,7 +82,7 @@ TEST_CASE("test spi1 flash operation after putting .text and .rodata into psram" { //Get the partition used for SPI1 erase operation const esp_partition_t *part = s_get_partition(); - ESP_LOGI(TAG, "found partition '%s' at offset 0x%x with size 0x%x", part->label, part->address, part->size); + ESP_LOGI(TAG, "found partition '%s' at offset 0x%"PRIx32" with size 0x%"PRIx32, part->label, part->address, part->size); //Erase whole region TEST_ESP_OK(esp_flash_erase_region(part->flash_chip, part->address, part->size)); @@ -117,8 +107,8 @@ TEST_CASE("test spi1 flash operation after putting .text and .rodata into psram" TEST_ESP_OK(gptimer_register_event_callbacks(gptimer, &cbs, NULL)); esp_rom_spiflash_result_t ret; - size_t start = part->address; - ESP_LOGI(TAG, "test data partition: 0x%x", start); + uint32_t start = part->address; + ESP_LOGI(TAG, "test data partition: 0x%"PRIx32, start); uint32_t sector_num = start / SECTOR_LEN; TEST_ESP_OK(gptimer_enable(gptimer)); @@ -132,10 +122,69 @@ TEST_CASE("test spi1 flash operation after putting .text and .rodata into psram" TEST_ESP_OK(gptimer_stop(gptimer)); TEST_ASSERT(s_timer_cb_exe_times > 0); - printf("timer callback runs %d times\n", s_timer_cb_exe_times); + printf("timer callback runs %"PRId32" times\n", s_timer_cb_exe_times); ESP_LOGI(TAG, "Finish"); TEST_ESP_OK(gptimer_disable(gptimer)); TEST_ESP_OK(gptimer_del_timer(gptimer)); } #endif //CONFIG_SPIRAM_FETCH_INSTRUCTIONS && CONFIG_SPIRAM_RODATA + + +TEST_CASE("test psram unaligned access", "[psram]") +{ + size_t largest_size = heap_caps_get_largest_free_block(MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT); + ESP_LOGI(TAG, "largest size is %zu", largest_size); + + uint8_t *ext_buffer = (uint8_t *)heap_caps_calloc(largest_size, 1, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT); + for (int i = 0; i < largest_size; i++) { + ext_buffer[i] = i & 0xff; + } + + for (int i = 0; i < largest_size - 4; i += 4) { + + uint8_t *ptr_base = (uint8_t *)(ext_buffer + i); + + for (int j = 1; j < 4; j++) { + uint8_t *unaligned_ptr = (uint8_t *)(ptr_base + j); + ESP_LOGV(TAG, "i is %d, j is %d, unaligned_ptr addr is %p", i, j, unaligned_ptr); + + uint8_t val_8bit = *unaligned_ptr; + ESP_LOGV(TAG, "i is %d, j is %d, val_8bit val is 0x%"PRIx8, i, j, val_8bit); + uint8_t first_byte = (i + j) & 0xff; + uint8_t expected_val_8bit = first_byte; + TEST_ASSERT(val_8bit == expected_val_8bit); + + /** + * If the vaddr doesn't support unaligned access, below codes will generate `LoadStoreAlignment` error. + * + * This is because below lines includes 16-bit load and 32-bit load: + * - l16ui + * - l32i.n + * + * Whereas we use an `add.n` to adding an offset (from 0 to 3) to the original buffer address. + * + * Therefore we get unaligned access + */ + + uint16_t val_16bit = *(uint16_t *)unaligned_ptr; + ESP_LOGV(TAG, "i is %d, j is %d, val_16bit val is 0x%"PRIx16, i, j, val_16bit); + uint32_t val_32bit = *(uint32_t *)unaligned_ptr; + ESP_LOGV(TAG, "i is %d, j is %d, val_32bit val is 0x%"PRIx32, i, j, val_32bit); + + + uint8_t second_byte = ((i + j) & 0xff) + 1; + uint8_t third_byte = ((i + j) & 0xff) + 2; + uint8_t fourth_byte = ((i + j) & 0xff) + 3; + + uint16_t expected_val_16bit = (second_byte << 8) | first_byte; + ESP_LOGV(TAG, "i is %d, j is %d, expected_val_16bit val is 0x%"PRIx16, i, j, expected_val_16bit); + TEST_ASSERT(val_16bit == expected_val_16bit); + uint32_t expected_val_32bit = (fourth_byte << 24) | (third_byte << 16) | (second_byte << 8) | first_byte; + ESP_LOGV(TAG, "i is %d, j is %d, expected_val_32bit val is 0x%"PRIx32"\n", i, j, expected_val_32bit); + TEST_ASSERT(val_32bit == expected_val_32bit); + } + } + + heap_caps_free(ext_buffer); +} diff --git a/components/esp_psram/test_apps/psram/pytest_psram.py b/components/esp_psram/test_apps/psram/pytest_psram.py index e000de1434..c08f4718b1 100644 --- a/components/esp_psram/test_apps/psram/pytest_psram.py +++ b/components/esp_psram/test_apps/psram/pytest_psram.py @@ -37,7 +37,7 @@ def test_psram_esp32s2(dut: Dut) -> None: @pytest.mark.esp32s3 -@pytest.mark.quad_psram +@pytest.mark.generic @pytest.mark.parametrize( 'config', [ diff --git a/components/esp_psram/test_apps/psram/sdkconfig.defaults b/components/esp_psram/test_apps/psram/sdkconfig.defaults index b308cb2ddd..95033f3fc2 100644 --- a/components/esp_psram/test_apps/psram/sdkconfig.defaults +++ b/components/esp_psram/test_apps/psram/sdkconfig.defaults @@ -1,2 +1,3 @@ CONFIG_FREERTOS_HZ=1000 CONFIG_ESP_TASK_WDT=n +CONFIG_SPIRAM=y diff --git a/components/esp_ringbuf/ringbuf.c b/components/esp_ringbuf/ringbuf.c index cbd58e3622..1ff2d8d9f5 100644 --- a/components/esp_ringbuf/ringbuf.c +++ b/components/esp_ringbuf/ringbuf.c @@ -1354,11 +1354,12 @@ BaseType_t xRingbufferAddToQueueSetRead(RingbufHandle_t xRingbuffer, QueueSetHan BaseType_t xReturn; portENTER_CRITICAL(&pxRingbuffer->mux); //Cannot add semaphore to queue set if semaphore is not empty. Temporarily hold semaphore - BaseType_t xHoldSemaphore = xSemaphoreTake(rbGET_RX_SEM_HANDLE(pxRingbuffer), 0); + BaseType_t result = xSemaphoreTake(rbGET_RX_SEM_HANDLE(pxRingbuffer), 0); xReturn = xQueueAddToSet(rbGET_RX_SEM_HANDLE(pxRingbuffer), xQueueSet); - if (xHoldSemaphore == pdTRUE) { + if (result == pdTRUE) { //Return semaphore if temporarily held - configASSERT(xSemaphoreGive(rbGET_RX_SEM_HANDLE(pxRingbuffer)) == pdTRUE); + result = xSemaphoreGive(rbGET_RX_SEM_HANDLE(pxRingbuffer)); + configASSERT(result == pdTRUE); } portEXIT_CRITICAL(&pxRingbuffer->mux); return xReturn; @@ -1380,11 +1381,12 @@ BaseType_t xRingbufferRemoveFromQueueSetRead(RingbufHandle_t xRingbuffer, QueueS BaseType_t xReturn; portENTER_CRITICAL(&pxRingbuffer->mux); //Cannot remove semaphore from queue set if semaphore is not empty. Temporarily hold semaphore - BaseType_t xHoldSemaphore = xSemaphoreTake(rbGET_RX_SEM_HANDLE(pxRingbuffer), 0); + BaseType_t result = xSemaphoreTake(rbGET_RX_SEM_HANDLE(pxRingbuffer), 0); xReturn = xQueueRemoveFromSet(rbGET_RX_SEM_HANDLE(pxRingbuffer), xQueueSet); - if (xHoldSemaphore == pdTRUE) { + if (result == pdTRUE) { //Return semaphore if temporarily held - configASSERT(xSemaphoreGive(rbGET_RX_SEM_HANDLE(pxRingbuffer)) == pdTRUE); + result = xSemaphoreGive(rbGET_RX_SEM_HANDLE(pxRingbuffer)); + configASSERT(result == pdTRUE); } portEXIT_CRITICAL(&pxRingbuffer->mux); return xReturn; diff --git a/components/esp_rom/.build-test-rules.yml b/components/esp_rom/.build-test-rules.yml index 1ed5faae8e..8a19709b18 100644 --- a/components/esp_rom/.build-test-rules.yml +++ b/components/esp_rom/.build-test-rules.yml @@ -4,3 +4,9 @@ components/esp_rom/host_test/rom_test: enable: - if: IDF_TARGET == "linux" reason: only test on linux + +components/esp_rom/test_apps: + disable_test: + - if: IDF_TARGET in ["esp32", "esp32c2"] + temporary: false + reason: lack of memory for testing miniz compressing diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt index 04d5cc0cd9..8861f70abb 100644 --- a/components/esp_rom/CMakeLists.txt +++ b/components/esp_rom/CMakeLists.txt @@ -18,9 +18,14 @@ else() "patches/esp_rom_sys.c" "patches/esp_rom_uart.c" "patches/esp_rom_spiflash.c" - "patches/esp_rom_tjpgd.c" "patches/esp_rom_regi2c.c" "patches/esp_rom_efuse.c") + + if(CONFIG_HEAP_TLSF_USE_ROM_IMPL AND CONFIG_ESP_ROM_TLSF_CHECK_PATCH) + # This file shall be included in the build if TLSF in ROM is activated + list(APPEND sources "patches/esp_rom_tlsf.c") + endif() + list(APPEND private_required_comp soc hal) endif() @@ -64,6 +69,16 @@ if(target STREQUAL "linux") else() target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/${ld_folder}/${target}.rom.ld") rom_linker_script("api") + + # esp32c6.rom.api.ld has been split to several lds by components + if(target STREQUAL "esp32c6") + rom_linker_script("phy") + rom_linker_script("coexist") + rom_linker_script("net80211") + rom_linker_script("pp") + # rom_linker_script("spiflash") # TODO: IDF-5632 (Supports more rom components) + endif() + if(CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB) rom_linker_script("libgcc") else() @@ -99,6 +114,9 @@ if(BOOTLOADER_BUILD) elseif(target STREQUAL "esp32c2") rom_linker_script("newlib") rom_linker_script("mbedtls") + + elseif(target STREQUAL "esp32c6") + rom_linker_script("newlib") endif() else() # Regular app build @@ -212,9 +230,21 @@ else() # Regular app build endif() endif() - if(CONFIG_HEAP_TLSF_USE_ROM_IMPL) - rom_linker_script("heap") + elseif(target STREQUAL "esp32c6") + rom_linker_script("newlib") + rom_linker_script("version") + endif() + + if(CONFIG_HEAP_TLSF_USE_ROM_IMPL) + # After registering the component, set the tlsf_set_rom_patches symbol as undefined + # to force the linker to integrate the whole `esp_rom_tlsf.c` object file inside the + # final binary. This is necessary because tlsf_set_rom_patches is a constructor, thus, + # there as no explicit reference/call to it in IDF. + if(CONFIG_ESP_ROM_TLSF_CHECK_PATCH) + target_link_libraries(${COMPONENT_LIB} PRIVATE "-u tlsf_set_rom_patches") endif() + + rom_linker_script("heap") endif() if(CONFIG_IDF_TARGET_ARCH_XTENSA) diff --git a/components/esp_rom/esp32/Kconfig.soc_caps.in b/components/esp_rom/esp32/Kconfig.soc_caps.in index ff6d589121..4707ff484e 100644 --- a/components/esp_rom/esp32/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32/Kconfig.soc_caps.in @@ -18,3 +18,7 @@ config ESP_ROM_HAS_JPEG_DECODE config ESP_ROM_SUPPORT_MULTIPLE_UART bool default y + +config ESP_ROM_NEEDS_SWSETUP_WORKAROUND + bool + default y diff --git a/components/esp_rom/esp32/esp_rom_caps.h b/components/esp_rom/esp32/esp_rom_caps.h index 6188ef52a7..1d19be8571 100644 --- a/components/esp_rom/esp32/esp_rom_caps.h +++ b/components/esp_rom/esp32/esp_rom_caps.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -18,3 +10,4 @@ #define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian #define ESP_ROM_HAS_JPEG_DECODE (1) // ROM has JPEG decode library #define ESP_ROM_SUPPORT_MULTIPLE_UART (1) // ROM has multiple UARTs available for logging +#define ESP_ROM_NEEDS_SWSETUP_WORKAROUND (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing diff --git a/components/esp_rom/esp32/ld/esp32.rom.api.ld b/components/esp_rom/esp32/ld/esp32.rom.api.ld index bc6fa83390..749977e845 100644 --- a/components/esp_rom/esp32/ld/esp32.rom.api.ld +++ b/components/esp_rom/esp32/ld/esp32.rom.api.ld @@ -1,12 +1,6 @@ /** * ROM APIs */ - -/* user may provide newer version of tjpgd */ -/* so here directly assign the symbols with the ROM API address to make sure one from rom is correctly linked */ -PROVIDE ( esp_rom_tjpgd_decomp = 0x400613e8 ); -PROVIDE ( esp_rom_tjpgd_prepare = 0x40060fa8 ); - PROVIDE ( esp_rom_crc32_le = crc32_le ); PROVIDE ( esp_rom_crc16_le = crc16_le ); PROVIDE ( esp_rom_crc8_le = crc8_le ); @@ -39,6 +33,9 @@ PROVIDE ( esp_rom_md5_init = 0x4005da7c ); PROVIDE ( esp_rom_md5_update = 0x4005da9c ); PROVIDE ( esp_rom_md5_final = 0x4005db1c ); +PROVIDE ( esp_rom_software_reset_system = software_reset ); +PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); + PROVIDE ( esp_rom_printf = ets_printf ); PROVIDE ( esp_rom_delay_us = ets_delay_us ); PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf ); diff --git a/components/esp_rom/esp32c2/Kconfig.soc_caps.in b/components/esp_rom/esp32c2/Kconfig.soc_caps.in index b6e13da822..295c811d1c 100644 --- a/components/esp_rom/esp32c2/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c2/Kconfig.soc_caps.in @@ -38,3 +38,15 @@ config ESP_ROM_HAS_HAL_SYSTIMER config ESP_ROM_HAS_HEAP_TLSF bool default y + +config ESP_ROM_TLSF_CHECK_PATCH + bool + default y + +config ESP_ROM_HAS_LAYOUT_TABLE + bool + default y + +config ESP_ROM_HAS_SPI_FLASH + bool + default y diff --git a/components/esp_rom/esp32c2/esp_rom_caps.h b/components/esp_rom/esp32c2/esp_rom_caps.h index eee69daaaa..39db7a94f6 100644 --- a/components/esp_rom/esp32c2/esp_rom_caps.h +++ b/components/esp_rom/esp32c2/esp_rom_caps.h @@ -15,3 +15,6 @@ #define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver #define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver #define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library +#define ESP_ROM_TLSF_CHECK_PATCH (1) // ROM does not contain the patch of tlsf_check() +#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table +#define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld index 4c39a51332..b214d50155 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld @@ -34,6 +34,9 @@ PROVIDE ( esp_rom_mbedtls_md5_starts_ret = mbedtls_md5_starts_ret ); PROVIDE ( esp_rom_mbedtls_md5_update_ret = mbedtls_md5_update_ret ); PROVIDE ( esp_rom_mbedtls_md5_finish_ret = mbedtls_md5_finish_ret ); +PROVIDE ( esp_rom_software_reset_system = software_reset ); +PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); + PROVIDE ( esp_rom_printf = ets_printf ); PROVIDE ( esp_rom_delay_us = ets_delay_us ); PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason ); diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.ld index 82275d2481..950a08afae 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.ld @@ -720,7 +720,6 @@ r_ble_ll_conn_cth_flow_have_credit = 0x40000d6c; r_ble_ll_conn_cth_flow_is_enabled = 0x40000d70; r_ble_ll_conn_cth_flow_process_cmd = 0x40000d74; r_ble_ll_conn_cth_flow_set_buffers = 0x40000d78; -r_ble_ll_conn_enqueue_pkt = 0x40000d7c; r_ble_ll_conn_ext_master_init = 0x40000d84; r_ble_ll_conn_find_active_conn = 0x40000d88; r_ble_ll_conn_get_active_conn = 0x40000d8c; @@ -752,7 +751,6 @@ r_ble_ll_conn_master_init = 0x40000df8; r_ble_ll_conn_module_reset = 0x40000e04; r_ble_ll_conn_next_event = 0x40000e08; r_ble_ll_conn_num_comp_pkts_event_send = 0x40000e0c; -r_ble_ll_conn_prepare_tx_pdu = 0x40000e10; r_ble_ll_conn_process_conn_params = 0x40000e14; r_ble_ll_conn_req_peer_sca = 0x40000e18; r_ble_ll_conn_rx_data_pdu = 0x40000e1c; @@ -904,7 +902,6 @@ r_ble_ll_hw_err_timer_cb = 0x400010a0; r_ble_ll_hw_error = 0x400010a4; r_ble_ll_init_alloc_conn_comp_ev = 0x400010ac; r_ble_ll_init_get_conn_comp_ev = 0x400010b0; -r_ble_ll_init_rx_pkt_in = 0x400010b4; r_ble_ll_is_addr_empty = 0x400010b8; r_ble_ll_is_controller_busy = 0x400010bc; r_ble_ll_is_on_resolv_list = 0x400010c0; @@ -914,7 +911,6 @@ r_ble_ll_is_valid_adv_mode = 0x400010cc; r_ble_ll_is_valid_own_addr_type = 0x400010d0; r_ble_ll_is_valid_public_addr = 0x400010d4; r_ble_ll_is_valid_random_addr = 0x400010d8; -r_ble_ll_mbuf_init = 0x400010dc; r_ble_ll_misc_options_set = 0x400010e0; r_ble_ll_modify_sca = 0x400010e4; r_ble_ll_modify_sca_action = 0x400010e8; @@ -934,7 +930,6 @@ r_ble_ll_read_local_p256_pub_key = 0x4000111c; r_ble_ll_read_rf_path_compensation = 0x40001120; r_ble_ll_read_supp_features = 0x40001124; r_ble_ll_read_supp_states = 0x40001128; -r_ble_ll_read_tx_power = 0x4000112c; r_ble_ll_reset = 0x40001130; r_ble_ll_resolv_clear_all_pl_bit = 0x40001134; r_ble_ll_resolv_clear_all_wl_bit = 0x40001138; @@ -1007,7 +1002,6 @@ r_ble_ll_scan_record_new_adv = 0x40001250; r_ble_ll_scan_refresh_nrpa = 0x40001254; r_ble_ll_scan_reset = 0x40001258; r_ble_ll_scan_rx_pkt_in = 0x4000125c; -r_ble_ll_scan_rx_pkt_in_on_legacy = 0x40001264; r_ble_ll_scan_rx_pkt_in_restore_addr_data = 0x40001268; r_ble_ll_scan_rxed = 0x4000126c; r_ble_ll_scan_send_adv_report = 0x40001270; @@ -1072,7 +1066,6 @@ r_ble_ll_trace_u32 = 0x40001384; r_ble_ll_trace_u32x2 = 0x40001388; r_ble_ll_trace_u32x3 = 0x4000138c; r_ble_ll_tx_flat_mbuf_pducb = 0x40001390; -r_ble_ll_tx_mbuf_pducb = 0x40001394; r_ble_ll_tx_pkt_in = 0x40001398; r_ble_ll_update_max_tx_octets_phy_mode = 0x4000139c; r_ble_ll_usecs_to_ticks_round_up = 0x400013a0; @@ -1144,7 +1137,6 @@ r_ble_lll_aux_scan_cb = 0x400014b8; r_ble_lll_aux_scan_drop = 0x400014bc; r_ble_lll_aux_scan_drop_event_cb = 0x400014c0; r_ble_lll_calc_us_convert_tick_unit = 0x400014c4; -r_ble_lll_conn_append_tx_buffer = 0x400014c8; r_ble_lll_conn_can_send_next_pdu = 0x400014cc; r_ble_lll_conn_check_opcode_matched = 0x400014d0; r_ble_lll_conn_coex_dpc_process = 0x400014d4; @@ -1154,7 +1146,6 @@ r_ble_lll_conn_coex_dpc_update_on_event_end = 0x400014e0; r_ble_lll_conn_coex_dpc_update_on_event_scheduled = 0x400014e4; r_ble_lll_conn_coex_dpc_update_on_event_started = 0x400014e8; r_ble_lll_conn_cth_flow_alloc_credit = 0x400014ec; -r_ble_lll_conn_cth_flow_free_credit = 0x400014f0; r_ble_lll_conn_current_sm_over = 0x400014f4; r_ble_lll_conn_env_deinit = 0x400014fc; r_ble_lll_conn_env_init = 0x40001500; @@ -1167,24 +1158,18 @@ r_ble_lll_conn_free_rx_mbuf = 0x40001518; r_ble_lll_conn_get_addr_info_from_rx_buf = 0x4000151c; r_ble_lll_conn_get_ce_end_time = 0x40001520; r_ble_lll_conn_get_next_sched_time = 0x40001524; -r_ble_lll_conn_get_rx_mbuf = 0x40001528; r_ble_lll_conn_halt = 0x4000152c; r_ble_lll_conn_master_common_init = 0x40001530; r_ble_lll_conn_master_new = 0x40001534; r_ble_lll_conn_module_deinit = 0x40001538; r_ble_lll_conn_module_reset = 0x40001540; -r_ble_lll_conn_no_mem_evt_pre_cb = 0x40001544; r_ble_lll_conn_pre_process = 0x40001548; r_ble_lll_conn_process_acked_pdu = 0x4000154c; -r_ble_lll_conn_process_in_isr = 0x40001550; r_ble_lll_conn_recv_ack = 0x40001554; r_ble_lll_conn_recv_valid_packet = 0x40001558; r_ble_lll_conn_reset_pending_sched = 0x4000155c; -r_ble_lll_conn_rx_pkt_isr = 0x40001560; r_ble_lll_conn_sched_next_anchor = 0x40001564; r_ble_lll_conn_sched_next_event = 0x40001568; -r_ble_lll_conn_set_slave_flow_control = 0x4000156c; -r_ble_lll_conn_slave_new = 0x40001570; r_ble_lll_conn_sm_new = 0x40001574; r_ble_lll_conn_sm_npl_deinit = 0x40001578; r_ble_lll_conn_sm_npl_init = 0x4000157c; @@ -1210,7 +1195,6 @@ r_ble_lll_dtm_rx_sched_cb = 0x400015cc; r_ble_lll_dtm_rx_start = 0x400015d0; r_ble_lll_dtm_rx_test = 0x400015d4; r_ble_lll_dtm_set_next = 0x400015d8; -r_ble_lll_dtm_tx_create_ctx = 0x400015dc; r_ble_lll_dtm_tx_done = 0x400015e0; r_ble_lll_dtm_tx_sched_cb = 0x400015e4; r_ble_lll_dtm_tx_test = 0x400015e8; @@ -1237,21 +1221,14 @@ r_ble_lll_per_adv_coex_dpc_update_on_scheduled = 0x4000163c; r_ble_lll_per_adv_coex_dpc_update_on_start = 0x40001640; r_ble_lll_reset = 0x40001644; r_ble_lll_rfmgmt_controller_sleep_en = 0x40001648; -r_ble_lll_rfmgmt_deinit = 0x4000164c; -r_ble_lll_rfmgmt_disable = 0x40001650; -r_ble_lll_rfmgmt_enable = 0x40001654; r_ble_lll_rfmgmt_enable_now = 0x40001658; -r_ble_lll_rfmgmt_init = 0x4000165c; r_ble_lll_rfmgmt_is_enabled = 0x40001660; r_ble_lll_rfmgmt_release = 0x40001664; r_ble_lll_rfmgmt_release_ev = 0x40001668; -r_ble_lll_rfmgmt_reset = 0x4000166c; r_ble_lll_rfmgmt_scan_changed = 0x40001670; r_ble_lll_rfmgmt_sched_changed = 0x40001674; r_ble_lll_rfmgmt_set_sleep_cb = 0x40001678; r_ble_lll_rfmgmt_ticks_to_enabled = 0x4000167c; -r_ble_lll_rfmgmt_timer_exp = 0x40001680; -r_ble_lll_rfmgmt_timer_reschedule = 0x40001684; r_ble_lll_rx_pdu_in = 0x40001688; r_ble_lll_rx_pkt_in = 0x4000168c; r_ble_lll_rx_pkt_isr = 0x40001690; @@ -1278,7 +1255,6 @@ r_ble_lll_scan_period_timer_cb = 0x400016e0; r_ble_lll_scan_process_adv_in_isr = 0x400016e4; r_ble_lll_scan_req_backoff = 0x400016ec; r_ble_lll_scan_restart = 0x400016f0; -r_ble_lll_scan_rx_pkt_isr = 0x400016fc; r_ble_lll_scan_sched_next_aux = 0x40001700; r_ble_lll_scan_sched_remove = 0x40001704; r_ble_lll_scan_start = 0x40001708; @@ -1350,7 +1326,6 @@ r_ble_phy_get_packet_status = 0x40001818; r_ble_phy_get_pyld_time_offset = 0x4000181c; r_ble_phy_get_rx_phy_mode = 0x40001820; r_ble_phy_get_seq_end_st = 0x40001824; -r_ble_phy_isr = 0x4000182c; r_ble_phy_max_data_pdu_pyld = 0x40001830; r_ble_phy_mode_config = 0x40001834; r_ble_phy_mode_convert = 0x40001838; @@ -1379,9 +1354,7 @@ r_ble_phy_set_conn_ind_pdu = 0x40001890; r_ble_phy_set_conn_mode = 0x40001894; r_ble_phy_set_dev_address = 0x40001898; r_ble_phy_set_rx_pwr_compensation = 0x4000189c; -r_ble_phy_set_rxhdr = 0x400018a0; r_ble_phy_set_scan_mode = 0x400018a4; -r_ble_phy_set_sequence_mode = 0x400018a8; r_ble_phy_set_single_packet_rx_sequence = 0x400018ac; r_ble_phy_set_single_packet_tx_sequence = 0x400018b0; r_ble_phy_set_tx_rx_transition = 0x400018b4; @@ -1427,7 +1400,6 @@ r_get_peer_irk_offset = 0x40001958; r_get_peer_rpa_offset = 0x4000195c; r_hal_rtc_intr_init = 0x40001960; r_hal_rtc_irq_handler = 0x40001964; -r_hal_timer_deinit = 0x40001968; r_hal_timer_disable_irq = 0x4000196c; r_hal_timer_env_init = 0x40001970; r_hal_timer_process = 0x40001978; @@ -2051,7 +2023,6 @@ ieee80211_encap_amsdu = 0x400020f0; ieee80211_output_raw_process = 0x400020f4; ieee80211_raw_frame_sanity_check = 0x400020fc; ieee80211_crypto_aes_128_cmac_encrypt = 0x40002100; -ieee80211_crypto_aes_128_cmac_decrypt = 0x40002104; ieee80211_alloc_tx_buf = 0x40002108; ieee80211_output_do = 0x4000210c; ieee80211_send_nulldata = 0x40002110; diff --git a/components/esp_rom/esp32c3/Kconfig.soc_caps.in b/components/esp_rom/esp32c3/Kconfig.soc_caps.in index c6beb32f11..7c5297eaae 100644 --- a/components/esp_rom/esp32c3/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c3/Kconfig.soc_caps.in @@ -34,3 +34,15 @@ config ESP_ROM_HAS_ERASE_0_REGION_BUG config ESP_ROM_GET_CLK_FREQ bool default y + +config ESP_ROM_NEEDS_SWSETUP_WORKAROUND + bool + default y + +config ESP_ROM_HAS_LAYOUT_TABLE + bool + default y + +config ESP_ROM_HAS_SPI_FLASH + bool + default y diff --git a/components/esp_rom/esp32c3/esp_rom_caps.h b/components/esp_rom/esp32c3/esp_rom_caps.h index 151fb44e08..e8b86ff7e5 100644 --- a/components/esp_rom/esp32c3/esp_rom_caps.h +++ b/components/esp_rom/esp32c3/esp_rom_caps.h @@ -14,3 +14,6 @@ #define ESP_ROM_HAS_RETARGETABLE_LOCKING (1) // ROM was built with retargetable locking #define ESP_ROM_HAS_ERASE_0_REGION_BUG (1) // ROM has esp_flash_erase_region(size=0) bug #define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency` +#define ESP_ROM_NEEDS_SWSETUP_WORKAROUND (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing +#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table +#define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld index 9c7d0903c1..98888d17a4 100644 --- a/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld +++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld @@ -1,11 +1,6 @@ -/** ROM APIs +/** + * ROM APIs */ - -/* user may provide newer version of tjpgd */ -/* so here directly assign the symbols with the ROM API address to make sure one from rom is correctly linked */ -PROVIDE ( esp_rom_tjpgd_decomp = 0x40000108 ); -PROVIDE ( esp_rom_tjpgd_prepare = 0x40000104 ); - PROVIDE ( esp_rom_crc32_le = crc32_le ); PROVIDE ( esp_rom_crc16_le = crc16_le ); PROVIDE ( esp_rom_crc8_le = crc8_le ); @@ -37,6 +32,9 @@ PROVIDE ( esp_rom_md5_init = MD5Init ); PROVIDE ( esp_rom_md5_update = MD5Update ); PROVIDE ( esp_rom_md5_final = MD5Final ); +PROVIDE ( esp_rom_software_reset_system = software_reset ); +PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); + PROVIDE ( esp_rom_printf = ets_printf ); PROVIDE ( esp_rom_delay_us = ets_delay_us ); PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason ); diff --git a/components/esp_rom/esp32c6/Kconfig.soc_caps.in b/components/esp_rom/esp32c6/Kconfig.soc_caps.in new file mode 100644 index 0000000000..abb7f8fe10 --- /dev/null +++ b/components/esp_rom/esp32c6/Kconfig.soc_caps.in @@ -0,0 +1,48 @@ +##################################################### +# This file is auto-generated from SoC caps +# using gen_soc_caps_kconfig.py, do not edit manually +##################################################### + +config ESP_ROM_HAS_CRC_LE + bool + default y + +config ESP_ROM_HAS_CRC_BE + bool + default y + +config ESP_ROM_HAS_JPEG_DECODE + bool + default y + +config ESP_ROM_UART_CLK_IS_XTAL + bool + default y + +config ESP_ROM_USB_SERIAL_DEVICE_NUM + int + default 3 + +config ESP_ROM_HAS_RETARGETABLE_LOCKING + bool + default y + +config ESP_ROM_GET_CLK_FREQ + bool + default y + +config ESP_ROM_HAS_HEAP_TLSF + bool + default y + +config ESP_ROM_HAS_LAYOUT_TABLE + bool + default y + +config ESP_ROM_HAS_RVFPLIB + bool + default y + +config ESP_ROM_HAS_SPI_FLASH + bool + default y diff --git a/components/esp_rom/esp32c6/esp_rom_caps.h b/components/esp_rom/esp32c6/esp_rom_caps.h new file mode 100644 index 0000000000..4305caa9a0 --- /dev/null +++ b/components/esp_rom/esp32c6/esp_rom_caps.h @@ -0,0 +1,19 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian +#define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian +#define ESP_ROM_HAS_JPEG_DECODE (1) // ROM has JPEG decode library +#define ESP_ROM_UART_CLK_IS_XTAL (1) // UART clock source is selected to XTAL in ROM +#define ESP_ROM_USB_SERIAL_DEVICE_NUM (3) // UART uses USB_SERIAL_JTAG port in ROM. +#define ESP_ROM_HAS_RETARGETABLE_LOCKING (1) // ROM was built with retargetable locking +#define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency` +#define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library +#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table +#define ESP_ROM_HAS_RVFPLIB (1) // ROM has the rvfplib +#define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld new file mode 100644 index 0000000000..4d26da2720 --- /dev/null +++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/** ROM APIs + */ + +PROVIDE ( esp_rom_crc32_le = crc32_le ); +PROVIDE ( esp_rom_crc16_le = crc16_le ); +PROVIDE ( esp_rom_crc8_le = crc8_le ); +PROVIDE ( esp_rom_crc32_be = crc32_be ); +PROVIDE ( esp_rom_crc16_be = crc16_be ); +PROVIDE ( esp_rom_crc8_be = crc8_be ); + +PROVIDE ( esp_rom_gpio_pad_select_gpio = gpio_pad_select_gpio ); +PROVIDE ( esp_rom_gpio_pad_pullup_only = gpio_pad_pullup ); +PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv ); +PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold ); +PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in ); +PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out ); + +PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 ); +PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled ); + +PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush ); +PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char ); +PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle ); +PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char ); +PROVIDE ( esp_rom_uart_rx_string = UartRxString ); +PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); + +PROVIDE ( esp_rom_md5_init = MD5Init ); +PROVIDE ( esp_rom_md5_update = MD5Update ); +PROVIDE ( esp_rom_md5_final = MD5Final ); + +PROVIDE ( esp_rom_software_reset_system = software_reset ); +PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); + +PROVIDE ( esp_rom_printf = ets_printf ); +PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf ); +PROVIDE ( esp_rom_delay_us = ets_delay_us ); +PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason ); +PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set ); +PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency ); + +PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock ); +PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable ); +PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea ); + +PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix ); +PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs); +PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction ); +PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command ); + +PROVIDE ( esp_rom_regi2c_read = rom_i2c_readReg ); +PROVIDE ( esp_rom_regi2c_read_mask = rom_i2c_readReg_Mask ); +PROVIDE ( esp_rom_regi2c_write = rom_i2c_writeReg ); +PROVIDE ( esp_rom_regi2c_write_mask = rom_i2c_writeReg_Mask ); diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.coexist.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.coexist.ld new file mode 100644 index 0000000000..cec4b9f6e8 --- /dev/null +++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.coexist.ld @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32c6.rom.coexist.ld for esp32c6 + * + * + * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group rom_coexist + ***************************************/ + +/* Functions */ +esp_coex_rom_version_get = 0x40000afc; +coex_bt_release = 0x40000b00; +coex_bt_request = 0x40000b04; +coex_core_ble_conn_dyn_prio_get = 0x40000b08; +coex_core_event_duration_get = 0x40000b0c; +coex_core_pti_get = 0x40000b10; +coex_core_release = 0x40000b14; +coex_core_request = 0x40000b18; +coex_core_status_get = 0x40000b1c; +coex_core_timer_idx_get = 0x40000b20; +coex_event_duration_get = 0x40000b24; +coex_hw_timer_disable = 0x40000b28; +coex_hw_timer_enable = 0x40000b2c; +coex_hw_timer_set = 0x40000b30; +coex_schm_interval_set = 0x40000b34; +coex_schm_lock = 0x40000b38; +coex_schm_unlock = 0x40000b3c; +coex_status_get = 0x40000b40; +coex_wifi_release = 0x40000b44; +esp_coex_ble_conn_dynamic_prio_get = 0x40000b48; +/* Data (.data, .bss, .rodata) */ +coex_env_ptr = 0x4087ffc4; +coex_pti_tab_ptr = 0x4087ffc0; +coex_schm_env_ptr = 0x4087ffbc; +coexist_funcs = 0x4087ffb8; +g_coa_funcs_p = 0x4087ffb4; +g_coex_param_ptr = 0x4087ffb0; diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.eco3.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.eco3.ld new file mode 100644 index 0000000000..c7f10134f2 --- /dev/null +++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.eco3.ld @@ -0,0 +1,138 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* +ESP32C6 ECO3 ROM address table +Version 3 API's imported from the ROM +*/ + +esf_buf_alloc_dynamic = 0x400015c0; +esf_buf_recycle = 0x400015c4; +/*lmacTxDone = 0x4000162c;*/ +/*ppMapTxQueue = 0x400016d8;*/ +rcGetSched = 0x40001764; +wDevCheckBlockError = 0x400017b4; +/*ppProcTxDone = 0x40001804;*/ +sta_input = rom_sta_input; + +/*************************************** + Group rom_phy + ***************************************/ + +/* Functions */ +rom_index_to_txbbgain = 0x40001964; +rom_pbus_xpd_tx_on = 0x400019b0; +rom_set_tx_dig_gain = 0x400019f0; +rom_set_txcap_reg = 0x400019f4; +rom_txbbgain_to_index = 0x40001a0c; +rom_agc_reg_init = 0x40001a54; +rom_bb_reg_init = 0x40001a58; +rom_set_pbus_reg = 0x40001a70; +rom_phy_xpd_rf = 0x40001a78; +rom_write_txrate_power_offset = 0x40001a8c; +rom_temp_to_power = 0x40001ab4; +rom_open_i2c_xpd = 0x40001af8; +rom_tsens_read_init = 0x40001b00; +rom_tsens_code_read = 0x40001b04; +rom_tsens_dac_cal = 0x40001b10; +rom_pll_vol_cal = 0x40001b28; + +/*************************************** + Group eco3_wifi + ***************************************/ + +/* Functions */ +wdev_is_data_in_rxlist = 0x40001b2c; +ppProcTxCallback = 0x40001b30; +ieee80211_gettid = 0x40001b34; + + +/*************************************** + Group eco3_bluetooth + ***************************************/ + +/* Functions */ +r_lld_legacy_adv_dynamic_pti_get = 0x40001b38; +r_lld_legacy_adv_dynamic_pti_process = 0x40001b3c; +r_lld_ext_adv_dynamic_pti_get = 0x40001b40; +r_lld_ext_adv_dynamic_aux_pti_process = 0x40001b44; +r_lld_ext_adv_dynamic_pti_process = 0x40001b48; +r_lld_adv_ext_pkt_prepare_set = 0x40001b4c; +r_lld_adv_ext_chain_none_construct = 0x40001b50; +r_lld_adv_ext_chain_connectable_construct = 0x40001b54; +r_lld_adv_ext_chain_scannable_construct = 0x40001b58; +r_lld_adv_pkt_rx_connect_post = 0x40001b5c; +r_lld_adv_start_init_evt_param = 0x40001b60; +r_lld_adv_start_set_cs = 0x40001b64; +r_lld_adv_start_update_filter_policy = 0x40001b68; +r_lld_adv_start_schedule_asap = 0x40001b6c; +r_lld_con_tx_prog_new_packet_coex = 0x40001b70; +r_lld_con_tx_prog_new_packet = 0x40001b74; +r_lld_per_adv_dynamic_pti_get = 0x40001b78; +r_lld_per_adv_evt_start_chm_upd = 0x40001b7c; +r_lld_ext_scan_dynamic_pti_get = 0x40001b80; +r_lld_scan_try_sched = 0x40001b84; +r_lld_sync_insert = 0x40001b88; +r_sch_prog_ble_push = 0x40001b8c; +r_sch_prog_bt_push = 0x40001b90; +r_lld_init_evt_end_type_set = 0x40001b94; +r_lld_init_evt_end_type_get = 0x40001b98; +r_lld_adv_direct_adv_use_rpa_addr_state_set = 0x40001b9c; +r_lld_adv_direct_adv_use_rpa_addr_state_get = 0x40001ba0; +r_lld_init_evt_end_type_check_state_set = 0x40001ba4; +r_lld_init_evt_end_type_check_state_get = 0x40001ba8; + + +/*************************************** + Group eco3_phy + ***************************************/ + +/* Functions */ +rom_wrtie_pll_cap = 0x40001bac; +rom_set_tx_gain_mem = 0x40001bb0; +rom_bt_tx_dig_gain = 0x40001bb4; +rom_bt_get_tx_gain = 0x40001bb8; +rom_get_chan_target_power = 0x40001bbc; +rom_get_tx_gain_value = 0x40001bc0; +rom_wifi_tx_dig_gain = 0x40001bc4; +rom_wifi_get_tx_gain = 0x40001bc8; +rom_fe_i2c_reg_renew = 0x40001bcc; +rom_wifi_agc_sat_gain = 0x40001bd0; +rom_i2c_master_reset = 0x40001bd4; +rom_bt_filter_reg = 0x40001bd8; +rom_phy_bbpll_cal = 0x40001bdc; +rom_i2c_sar2_init_code = 0x40001be0; +rom_phy_param_addr = 0x40001be4; +rom_phy_reg_init = 0x40001be8; +rom_set_chan_reg = 0x40001bec; +rom_phy_wakeup_init = 0x40001bf0; +rom_phy_i2c_init1 = 0x40001bf4; +rom_tsens_temp_read = 0x40001bf8; +rom_bt_track_pll_cap = 0x40001bfc; +rom_wifi_track_pll_cap = 0x40001c00; +rom_wifi_set_tx_gain = 0x40001c04; +rom_txpwr_cal_track = 0x40001c08; +rom_tx_pwctrl_background = 0x40001c0c; +rom_bt_set_tx_gain = 0x40001c10; +rom_noise_check_loop = 0x40001c14; +rom_phy_close_rf = 0x40001c18; +rom_phy_xpd_tsens = 0x40001c1c; +rom_phy_freq_mem_backup = 0x40001c20; +rom_phy_ant_init = 0x40001c24; +rom_bt_track_tx_power = 0x40001c28; +rom_wifi_track_tx_power = 0x40001c2c; +rom_phy_dig_reg_backup = 0x40001c30; +chip726_phyrom_version_num = 0x40001c34; +/* Data (.data, .bss, .rodata) */ +phy_param_rom = 0x3fcdf830; + +/*************************************** + Group eco3_esp_flash + ***************************************/ + +/* Functions */ +PROVIDE( esp_flash_read_chip_id = 0x40001c38 ); +PROVIDE( detect_spi_flash_chip = 0x40001c3c ); +PROVIDE( esp_rom_spiflash_write_disable = 0x40001c40 ); diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.heap.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.heap.ld new file mode 100644 index 0000000000..1e95388383 --- /dev/null +++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.heap.ld @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32c6.rom.heap.ld for esp32c6 + * + * + * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group heap + ***************************************/ + +/* Functions */ +tlsf_create = 0x400003fc; +tlsf_create_with_pool = 0x40000400; +tlsf_get_pool = 0x40000404; +tlsf_add_pool = 0x40000408; +tlsf_remove_pool = 0x4000040c; +tlsf_malloc = 0x40000410; +tlsf_memalign = 0x40000414; +tlsf_memalign_offs = 0x40000418; +tlsf_realloc = 0x4000041c; +tlsf_free = 0x40000420; +tlsf_block_size = 0x40000424; +tlsf_size = 0x40000428; +tlsf_align_size = 0x4000042c; +tlsf_block_size_min = 0x40000430; +tlsf_block_size_max = 0x40000434; +tlsf_pool_overhead = 0x40000438; +tlsf_alloc_overhead = 0x4000043c; +tlsf_walk_pool = 0x40000440; +tlsf_check = 0x40000444; +tlsf_check_pool = 0x40000448; +tlsf_poison_fill_pfunc_set = 0x4000044c; +tlsf_poison_check_pfunc_set = 0x40000450; +multi_heap_get_block_address_impl = 0x40000454; +multi_heap_get_allocated_size_impl = 0x40000458; +multi_heap_register_impl = 0x4000045c; +multi_heap_set_lock = 0x40000460; +multi_heap_mutex_init = 0x40000464; +multi_heap_internal_lock = 0x40000468; +multi_heap_internal_unlock = 0x4000046c; +multi_heap_get_first_block = 0x40000470; +multi_heap_get_next_block = 0x40000474; +multi_heap_is_free = 0x40000478; +multi_heap_malloc_impl = 0x4000047c; +multi_heap_free_impl = 0x40000480; +multi_heap_realloc_impl = 0x40000484; +multi_heap_aligned_alloc_impl_offs = 0x40000488; +multi_heap_aligned_alloc_impl = 0x4000048c; +multi_heap_check = 0x40000490; +multi_heap_dump = 0x40000494; +multi_heap_free_size_impl = 0x40000498; +multi_heap_minimum_free_size_impl = 0x4000049c; +multi_heap_get_info_impl = 0x400004a0; +/* Data (.data, .bss, .rodata) */ +heap_tlsf_table_ptr = 0x4087ffd8; + +PROVIDE (multi_heap_malloc = multi_heap_malloc_impl); +PROVIDE (multi_heap_free = multi_heap_free_impl); +PROVIDE (multi_heap_realloc = multi_heap_realloc_impl); +PROVIDE (multi_heap_get_allocated_size = multi_heap_get_allocated_size_impl); +PROVIDE (multi_heap_register = multi_heap_register_impl); +PROVIDE (multi_heap_get_info = multi_heap_get_info_impl); +PROVIDE (multi_heap_free_size = multi_heap_free_size_impl); +PROVIDE (multi_heap_minimum_free_size = multi_heap_minimum_free_size_impl); +PROVIDE (multi_heap_get_block_address = multi_heap_get_block_address_impl); +PROVIDE (multi_heap_aligned_alloc = multi_heap_aligned_alloc_impl); +PROVIDE (multi_heap_aligned_free = multi_heap_aligned_free_impl); +PROVIDE (multi_heap_check = multi_heap_check); +PROVIDE (multi_heap_set_lock = multi_heap_set_lock); +PROVIDE (multi_heap_os_funcs_init = multi_heap_mutex_init); +PROVIDE (multi_heap_internal_lock = multi_heap_internal_lock); +PROVIDE (multi_heap_internal_unlock = multi_heap_internal_unlock); diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.ld new file mode 100644 index 0000000000..d43d88553c --- /dev/null +++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.ld @@ -0,0 +1,476 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32c6.rom.ld for esp32c6 + * + * + * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group common + ***************************************/ + +/* Functions */ +rtc_get_reset_reason = 0x40000018; +analog_super_wdt_reset_happened = 0x4000001c; +rtc_get_wakeup_cause = 0x40000020; +rtc_unhold_all_pads = 0x40000024; +ets_printf = 0x40000028; +ets_install_putc1 = 0x4000002c; +ets_install_putc2 = 0x40000030; +ets_install_uart_printf = 0x40000034; +ets_install_usb_printf = 0x40000038; +ets_get_printf_channel = 0x4000003c; +ets_delay_us = 0x40000040; +ets_get_cpu_frequency = 0x40000044; +ets_update_cpu_frequency = 0x40000048; +ets_install_lock = 0x4000004c; +UartRxString = 0x40000050; +UartGetCmdLn = 0x40000054; +uart_tx_one_char = 0x40000058; +uart_tx_one_char2 = 0x4000005c; +uart_rx_one_char = 0x40000060; +uart_rx_one_char_block = 0x40000064; +uart_rx_intr_handler = 0x40000068; +uart_rx_readbuff = 0x4000006c; +uartAttach = 0x40000070; +uart_tx_flush = 0x40000074; +uart_tx_wait_idle = 0x40000078; +uart_div_modify = 0x4000007c; +ets_write_char_uart = 0x40000080; +uart_tx_switch = 0x40000084; +roundup2 = 0x40000088; +multofup = 0x4000008c; +software_reset = 0x40000090; +software_reset_cpu = 0x40000094; +ets_clk_assist_debug_clock_enable = 0x40000098; +clear_super_wdt_reset_flag = 0x4000009c; +disable_default_watchdog = 0x400000a0; +esp_rom_set_rtc_wake_addr = 0x400000a4; +esp_rom_get_rtc_wake_addr = 0x400000a8; +send_packet = 0x400000ac; +recv_packet = 0x400000b0; +GetUartDevice = 0x400000b4; +UartDwnLdProc = 0x400000b8; +GetSecurityInfoProc = 0x400000bc; +Uart_Init = 0x400000c0; +ets_set_user_start = 0x400000c4; +/* Data (.data, .bss, .rodata) */ +ets_rom_layout_p = 0x4004fffc; +ets_ops_table_ptr = 0x4087fff8; +g_saved_pc = 0x4087fffc; + + +/*************************************** + Group miniz + ***************************************/ + +/* Functions */ +mz_adler32 = 0x400000c8; +mz_free = 0x400000cc; +tdefl_compress = 0x400000d0; +tdefl_compress_buffer = 0x400000d4; +tdefl_compress_mem_to_heap = 0x400000d8; +tdefl_compress_mem_to_mem = 0x400000dc; +tdefl_compress_mem_to_output = 0x400000e0; +tdefl_get_adler32 = 0x400000e4; +tdefl_get_prev_return_status = 0x400000e8; +tdefl_init = 0x400000ec; +tdefl_write_image_to_png_file_in_memory = 0x400000f0; +tdefl_write_image_to_png_file_in_memory_ex = 0x400000f4; +tinfl_decompress = 0x400000f8; +tinfl_decompress_mem_to_callback = 0x400000fc; +tinfl_decompress_mem_to_heap = 0x40000100; +tinfl_decompress_mem_to_mem = 0x40000104; + + +/*************************************** + Group tjpgd + ***************************************/ + +/* Functions */ +jd_prepare = 0x40000108; +jd_decomp = 0x4000010c; + + +/*************************************** + Group spiflash_legacy + ***************************************/ + +/* Functions */ +esp_rom_spiflash_wait_idle = 0x40000110; +esp_rom_spiflash_write_encrypted = 0x40000114; +esp_rom_spiflash_write_encrypted_dest = 0x40000118; +esp_rom_spiflash_write_encrypted_enable = 0x4000011c; +esp_rom_spiflash_write_encrypted_disable = 0x40000120; +esp_rom_spiflash_erase_chip = 0x40000124; +_esp_rom_spiflash_erase_sector = 0x40000128; +_esp_rom_spiflash_erase_block = 0x4000012c; +_esp_rom_spiflash_write = 0x40000130; +_esp_rom_spiflash_read = 0x40000134; +_esp_rom_spiflash_unlock = 0x40000138; +_SPIEraseArea = 0x4000013c; +_SPI_write_enable = 0x40000140; +esp_rom_spiflash_erase_sector = 0x40000144; +esp_rom_spiflash_erase_block = 0x40000148; +esp_rom_spiflash_write = 0x4000014c; +esp_rom_spiflash_read = 0x40000150; +esp_rom_spiflash_unlock = 0x40000154; +SPIEraseArea = 0x40000158; +SPI_write_enable = 0x4000015c; +esp_rom_spiflash_config_param = 0x40000160; +esp_rom_spiflash_read_user_cmd = 0x40000164; +esp_rom_spiflash_select_qio_pins = 0x40000168; +esp_rom_spi_flash_auto_sus_res = 0x4000016c; +esp_rom_spi_flash_send_resume = 0x40000170; +esp_rom_spi_flash_update_id = 0x40000174; +esp_rom_spiflash_config_clk = 0x40000178; +esp_rom_spiflash_config_readmode = 0x4000017c; +esp_rom_spiflash_read_status = 0x40000180; +esp_rom_spiflash_read_statushigh = 0x40000184; +esp_rom_spiflash_write_status = 0x40000188; +spi_cache_mode_switch = 0x4000018c; +spi_common_set_dummy_output = 0x40000190; +spi_common_set_flash_cs_timing = 0x40000194; +esp_rom_spi_set_address_bit_len = 0x40000198; +SPILock = 0x4000019c; +SPIMasterReadModeCnfig = 0x400001a0; +SPI_Common_Command = 0x400001a4; +SPI_WakeUp = 0x400001a8; +SPI_block_erase = 0x400001ac; +SPI_chip_erase = 0x400001b0; +SPI_init = 0x400001b4; +SPI_page_program = 0x400001b8; +SPI_read_data = 0x400001bc; +SPI_sector_erase = 0x400001c0; +SelectSpiFunction = 0x400001c4; +SetSpiDrvs = 0x400001c8; +Wait_SPI_Idle = 0x400001cc; +spi_dummy_len_fix = 0x400001d0; +Disable_QMode = 0x400001d4; +Enable_QMode = 0x400001d8; +spi_flash_attach = 0x400001dc; +spi_flash_get_chip_size = 0x400001e0; +spi_flash_guard_set = 0x400001e4; +spi_flash_guard_get = 0x400001e8; +spi_flash_read_encrypted = 0x400001ec; +/* Data (.data, .bss, .rodata) */ +rom_spiflash_legacy_funcs = 0x4087fff0; +rom_spiflash_legacy_data = 0x4087ffec; +g_flash_guard_ops = 0x4087fff4; + + +/*************************************** + Group hal_wdt + ***************************************/ + +/* Functions */ +wdt_hal_init = 0x40000394; +wdt_hal_deinit = 0x40000398; +wdt_hal_config_stage = 0x4000039c; +wdt_hal_write_protect_disable = 0x400003a0; +wdt_hal_write_protect_enable = 0x400003a4; +wdt_hal_enable = 0x400003a8; +wdt_hal_disable = 0x400003ac; +wdt_hal_handle_intr = 0x400003b0; +wdt_hal_feed = 0x400003b4; +wdt_hal_set_flashboot_en = 0x400003b8; +wdt_hal_is_enabled = 0x400003bc; + + +/*************************************** + Group hal_systimer + ***************************************/ + +/* Functions */ +systimer_hal_init = 0x400003c0; +systimer_hal_deinit = 0x400003c4; +systimer_hal_set_tick_rate_ops = 0x400003c8; +systimer_hal_get_counter_value = 0x400003cc; +systimer_hal_get_time = 0x400003d0; +systimer_hal_set_alarm_target = 0x400003d4; +systimer_hal_set_alarm_period = 0x400003d8; +systimer_hal_get_alarm_value = 0x400003dc; +systimer_hal_enable_alarm_int = 0x400003e0; +systimer_hal_on_apb_freq_update = 0x400003e4; +systimer_hal_counter_value_advance = 0x400003e8; +systimer_hal_enable_counter = 0x400003ec; +systimer_hal_select_alarm_mode = 0x400003f0; +systimer_hal_connect_alarm_counter = 0x400003f4; +systimer_hal_counter_can_stall_by_cpu = 0x400003f8; + + +/*************************************** + Group cache + ***************************************/ + +/* Functions */ +Cache_Get_ICache_Line_Size = 0x40000628; +Cache_Get_Mode = 0x4000062c; +Cache_Address_Through_Cache = 0x40000630; +ROM_Boot_Cache_Init = 0x40000634; +MMU_Set_Page_Mode = 0x40000638; +MMU_Get_Page_Mode = 0x4000063c; +Cache_Invalidate_ICache_Items = 0x40000640; +Cache_Op_Addr = 0x40000644; +Cache_Invalidate_Addr = 0x40000648; +Cache_Invalidate_ICache_All = 0x4000064c; +Cache_Mask_All = 0x40000650; +Cache_UnMask_Dram0 = 0x40000654; +Cache_Suspend_ICache_Autoload = 0x40000658; +Cache_Resume_ICache_Autoload = 0x4000065c; +Cache_Start_ICache_Preload = 0x40000660; +Cache_ICache_Preload_Done = 0x40000664; +Cache_End_ICache_Preload = 0x40000668; +Cache_Config_ICache_Autoload = 0x4000066c; +Cache_Enable_ICache_Autoload = 0x40000670; +Cache_Disable_ICache_Autoload = 0x40000674; +Cache_Enable_ICache_PreLock = 0x40000678; +Cache_Disable_ICache_PreLock = 0x4000067c; +Cache_Lock_ICache_Items = 0x40000680; +Cache_Unlock_ICache_Items = 0x40000684; +Cache_Lock_Addr = 0x40000688; +Cache_Unlock_Addr = 0x4000068c; +Cache_Disable_ICache = 0x40000690; +Cache_Enable_ICache = 0x40000694; +Cache_Suspend_ICache = 0x40000698; +Cache_Resume_ICache = 0x4000069c; +Cache_Freeze_ICache_Enable = 0x400006a0; +Cache_Freeze_ICache_Disable = 0x400006a4; +Cache_Set_IDROM_MMU_Size = 0x400006a8; +Cache_Get_IROM_MMU_End = 0x400006ac; +Cache_Get_DROM_MMU_End = 0x400006b0; +Cache_MMU_Init = 0x400006b4; +Cache_MSPI_MMU_Set = 0x400006b8; +Cache_Travel_Tag_Memory = 0x400006bc; +Cache_Get_Virtual_Addr = 0x400006c0; +/* Data (.data, .bss, .rodata) */ +rom_cache_op_cb = 0x4087ffcc; +rom_cache_internal_table_ptr = 0x4087ffc8; + + +/*************************************** + Group clock + ***************************************/ + +/* Functions */ +ets_clk_get_xtal_freq = 0x400006c4; +ets_clk_get_cpu_freq = 0x400006c8; +ets_clk_apb_wait_ready = 0x400006cc; +ets_clk_mspi_apb_wait_ready = 0x400006d0; + + +/*************************************** + Group gpio + ***************************************/ + +/* Functions */ +gpio_input_get = 0x400006d4; +gpio_matrix_in = 0x400006d8; +gpio_matrix_out = 0x400006dc; +gpio_output_disable = 0x400006e0; +gpio_output_enable = 0x400006e4; +gpio_output_set = 0x400006e8; +gpio_pad_hold = 0x400006ec; +gpio_pad_input_disable = 0x400006f0; +gpio_pad_input_enable = 0x400006f4; +gpio_pad_pulldown = 0x400006f8; +gpio_pad_pullup = 0x400006fc; +gpio_pad_select_gpio = 0x40000700; +gpio_pad_set_drv = 0x40000704; +gpio_pad_unhold = 0x40000708; +gpio_pin_wakeup_disable = 0x4000070c; +gpio_pin_wakeup_enable = 0x40000710; +gpio_bypass_matrix_in = 0x40000714; + + +/*************************************** + Group interrupts + ***************************************/ + +/* Functions */ +esprv_intc_int_set_priority = 0x40000718; +esprv_intc_int_set_threshold = 0x4000071c; +esprv_intc_int_enable = 0x40000720; +esprv_intc_int_disable = 0x40000724; +esprv_intc_int_set_type = 0x40000728; +PROVIDE( intr_handler_set = 0x4000072c ); +intr_matrix_set = 0x40000730; +ets_intr_lock = 0x40000734; +ets_intr_unlock = 0x40000738; +ets_isr_attach = 0x4000073c; +ets_isr_mask = 0x40000740; +ets_isr_unmask = 0x40000744; + + +/*************************************** + Group crypto + ***************************************/ + +/* Functions */ +md5_vector = 0x40000748; +MD5Init = 0x4000074c; +MD5Update = 0x40000750; +MD5Final = 0x40000754; +crc32_le = 0x40000758; +crc16_le = 0x4000075c; +crc8_le = 0x40000760; +crc32_be = 0x40000764; +crc16_be = 0x40000768; +crc8_be = 0x4000076c; +esp_crc8 = 0x40000770; +ets_sha_enable = 0x40000774; +ets_sha_disable = 0x40000778; +ets_sha_get_state = 0x4000077c; +ets_sha_init = 0x40000780; +ets_sha_process = 0x40000784; +ets_sha_starts = 0x40000788; +ets_sha_update = 0x4000078c; +ets_sha_finish = 0x40000790; +ets_sha_clone = 0x40000794; +ets_hmac_enable = 0x40000798; +ets_hmac_disable = 0x4000079c; +ets_hmac_calculate_message = 0x400007a0; +ets_hmac_calculate_downstream = 0x400007a4; +ets_hmac_invalidate_downstream = 0x400007a8; +ets_jtag_enable_temporarily = 0x400007ac; +ets_aes_enable = 0x400007b0; +ets_aes_disable = 0x400007b4; +ets_aes_setkey = 0x400007b8; +ets_aes_block = 0x400007bc; +ets_aes_setkey_dec = 0x400007c0; +ets_aes_setkey_enc = 0x400007c4; +ets_bigint_enable = 0x400007c8; +ets_bigint_disable = 0x400007cc; +ets_bigint_multiply = 0x400007d0; +ets_bigint_modmult = 0x400007d4; +ets_bigint_modexp = 0x400007d8; +ets_bigint_wait_finish = 0x400007dc; +ets_bigint_getz = 0x400007e0; +ets_ds_enable = 0x400007e4; +ets_ds_disable = 0x400007e8; +ets_ds_start_sign = 0x400007ec; +ets_ds_is_busy = 0x400007f0; +ets_ds_finish_sign = 0x400007f4; +ets_ds_encrypt_params = 0x400007f8; +ets_mgf1_sha256 = 0x400007fc; +/* Data (.data, .bss, .rodata) */ +crc32_le_table_ptr = 0x4004fff8; +crc16_le_table_ptr = 0x4004fff4; +crc8_le_table_ptr = 0x4004fff0; +crc32_be_table_ptr = 0x4004ffec; +crc16_be_table_ptr = 0x4004ffe8; +crc8_be_table_ptr = 0x4004ffe4; + + +/*************************************** + Group efuse + ***************************************/ + +/* Functions */ +ets_efuse_read = 0x40000800; +ets_efuse_program = 0x40000804; +ets_efuse_clear_program_registers = 0x40000808; +ets_efuse_write_key = 0x4000080c; +ets_efuse_get_read_register_address = 0x40000810; +ets_efuse_get_key_purpose = 0x40000814; +ets_efuse_key_block_unused = 0x40000818; +ets_efuse_find_unused_key_block = 0x4000081c; +ets_efuse_rs_calculate = 0x40000820; +ets_efuse_count_unused_key_blocks = 0x40000824; +ets_efuse_secure_boot_enabled = 0x40000828; +ets_efuse_secure_boot_aggressive_revoke_enabled = 0x4000082c; +ets_efuse_cache_encryption_enabled = 0x40000830; +ets_efuse_download_modes_disabled = 0x40000834; +ets_efuse_find_purpose = 0x40000838; +ets_efuse_force_send_resume = 0x4000083c; +ets_efuse_get_flash_delay_us = 0x40000840; +ets_efuse_get_mac = 0x40000844; +ets_efuse_get_uart_print_control = 0x40000848; +ets_efuse_direct_boot_mode_disabled = 0x4000084c; +ets_efuse_security_download_modes_enabled = 0x40000850; +ets_efuse_set_timing = 0x40000854; +ets_efuse_jtag_disabled = 0x40000858; +ets_efuse_usb_print_is_disabled = 0x4000085c; +ets_efuse_usb_download_mode_disabled = 0x40000860; +ets_efuse_usb_device_disabled = 0x40000864; +ets_efuse_secure_boot_fast_wake_enabled = 0x40000868; + + +/*************************************** + Group secureboot + ***************************************/ + +/* Functions */ +ets_emsa_pss_verify = 0x4000086c; +ets_rsa_pss_verify = 0x40000870; +ets_secure_boot_verify_bootloader_with_keys = 0x40000874; +ets_secure_boot_verify_signature = 0x40000878; +ets_secure_boot_read_key_digests = 0x4000087c; +ets_secure_boot_revoke_public_key_digest = 0x40000880; + + +/*************************************** + Group usb_device_uart + ***************************************/ + +/* Functions */ +usb_serial_device_rx_one_char = 0x40000a80; +usb_serial_device_rx_one_char_block = 0x40000a84; +usb_serial_device_tx_flush = 0x40000a88; +usb_serial_device_tx_one_char = 0x40000a8c; + + +/*************************************** + Group lldesc + ***************************************/ + +/* Functions */ +lldesc_build_chain = 0x40000a90; + + +/*************************************** + Group sip + ***************************************/ + +/* Functions */ +sip_after_tx_complete = 0x40000a94; +sip_alloc_to_host_evt = 0x40000a98; +sip_download_begin = 0x40000a9c; +sip_get_ptr = 0x40000aa0; +sip_get_state = 0x40000aa4; +sip_init_attach = 0x40000aa8; +sip_install_rx_ctrl_cb = 0x40000aac; +sip_install_rx_data_cb = 0x40000ab0; +sip_is_active = 0x40000ab4; +sip_post_init = 0x40000ab8; +sip_reclaim_from_host_cmd = 0x40000abc; +sip_reclaim_tx_data_pkt = 0x40000ac0; +sip_send = 0x40000ac4; +sip_to_host_chain_append = 0x40000ac8; +sip_to_host_evt_send_done = 0x40000acc; + + +/*************************************** + Group slc + ***************************************/ + +/* Functions */ +slc_add_credits = 0x40000ad0; +slc_enable = 0x40000ad4; +slc_from_host_chain_fetch = 0x40000ad8; +slc_from_host_chain_recycle = 0x40000adc; +slc_has_pkt_to_host = 0x40000ae0; +slc_init_attach = 0x40000ae4; +slc_init_credit = 0x40000ae8; +slc_reattach = 0x40000aec; +slc_send_to_host_chain = 0x40000af0; +slc_set_host_io_max_window = 0x40000af4; +slc_to_host_chain_recycle = 0x40000af8; diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.libgcc.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.libgcc.ld new file mode 100644 index 0000000000..b434970400 --- /dev/null +++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.libgcc.ld @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32c6.rom.libgcc.ld for esp32c6 + * + * + * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group libgcc + ***************************************/ + +/* Functions */ +__absvdi2 = 0x40000884; +__absvsi2 = 0x40000888; +__adddf3 = 0x4000088c; +__addsf3 = 0x40000890; +__addvdi3 = 0x40000894; +__addvsi3 = 0x40000898; +__ashldi3 = 0x4000089c; +__ashrdi3 = 0x400008a0; +__bswapdi2 = 0x400008a4; +__bswapsi2 = 0x400008a8; +__clear_cache = 0x400008ac; +__clrsbdi2 = 0x400008b0; +__clrsbsi2 = 0x400008b4; +__clzdi2 = 0x400008b8; +__clzsi2 = 0x400008bc; +__cmpdi2 = 0x400008c0; +__ctzdi2 = 0x400008c4; +__ctzsi2 = 0x400008c8; +__divdc3 = 0x400008cc; +__divdf3 = 0x400008d0; +__divdi3 = 0x400008d4; +__divsc3 = 0x400008d8; +__divsf3 = 0x400008dc; +__divsi3 = 0x400008e0; +__eqdf2 = 0x400008e4; +__eqsf2 = 0x400008e8; +__extendsfdf2 = 0x400008ec; +__ffsdi2 = 0x400008f0; +__ffssi2 = 0x400008f4; +__fixdfdi = 0x400008f8; +__fixdfsi = 0x400008fc; +__fixsfdi = 0x40000900; +__fixsfsi = 0x40000904; +__fixunsdfsi = 0x40000908; +__fixunssfdi = 0x4000090c; +__fixunssfsi = 0x40000910; +__floatdidf = 0x40000914; +__floatdisf = 0x40000918; +__floatsidf = 0x4000091c; +__floatsisf = 0x40000920; +__floatundidf = 0x40000924; +__floatundisf = 0x40000928; +__floatunsidf = 0x4000092c; +__floatunsisf = 0x40000930; +__gcc_bcmp = 0x40000934; +__gedf2 = 0x40000938; +__gesf2 = 0x4000093c; +__gtdf2 = 0x40000940; +__gtsf2 = 0x40000944; +__ledf2 = 0x40000948; +__lesf2 = 0x4000094c; +__lshrdi3 = 0x40000950; +__ltdf2 = 0x40000954; +__ltsf2 = 0x40000958; +__moddi3 = 0x4000095c; +__modsi3 = 0x40000960; +__muldc3 = 0x40000964; +__muldf3 = 0x40000968; +__muldi3 = 0x4000096c; +__mulsc3 = 0x40000970; +__mulsf3 = 0x40000974; +__mulsi3 = 0x40000978; +__mulvdi3 = 0x4000097c; +__mulvsi3 = 0x40000980; +__nedf2 = 0x40000984; +__negdf2 = 0x40000988; +__negdi2 = 0x4000098c; +__negsf2 = 0x40000990; +__negvdi2 = 0x40000994; +__negvsi2 = 0x40000998; +__nesf2 = 0x4000099c; +__paritysi2 = 0x400009a0; +__popcountdi2 = 0x400009a4; +__popcountsi2 = 0x400009a8; +__powidf2 = 0x400009ac; +__powisf2 = 0x400009b0; +__subdf3 = 0x400009b4; +__subsf3 = 0x400009b8; +__subvdi3 = 0x400009bc; +__subvsi3 = 0x400009c0; +__truncdfsf2 = 0x400009c4; +__ucmpdi2 = 0x400009c8; +__udivdi3 = 0x400009cc; +__udivmoddi4 = 0x400009d0; +__udivsi3 = 0x400009d4; +__udiv_w_sdiv = 0x400009d8; +__umoddi3 = 0x400009dc; +__umodsi3 = 0x400009e0; +__unorddf2 = 0x400009e4; +__unordsf2 = 0x400009e8; +__extenddftf2 = 0x400009ec; +__trunctfdf2 = 0x400009f0; diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.net80211.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.net80211.ld new file mode 100644 index 0000000000..7ce7b8309f --- /dev/null +++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.net80211.ld @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32c6.rom.net80211.ld for esp32c6 + * + * + * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group rom_net80211 + ***************************************/ + +/* Functions */ +esp_net80211_rom_version_get = 0x40000b4c; +ampdu_dispatch = 0x40000b50; +ampdu_dispatch_all = 0x40000b54; +ampdu_dispatch_as_many_as_possible = 0x40000b58; +ampdu_dispatch_movement = 0x40000b5c; +ampdu_dispatch_upto = 0x40000b60; +chm_is_at_home_channel = 0x40000b64; +cnx_node_is_existing = 0x40000b68; +cnx_node_search = 0x40000b6c; +ic_ebuf_recycle_rx = 0x40000b70; +ic_ebuf_recycle_tx = 0x40000b74; +ic_reset_rx_ba = 0x40000b78; +ieee80211_align_eb = 0x40000b7c; +ieee80211_ampdu_reorder = 0x40000b80; +ieee80211_ampdu_start_age_timer = 0x40000b84; +ieee80211_encap_esfbuf = 0x40000b88; +ieee80211_is_tx_allowed = 0x40000b8c; +ieee80211_output_pending_eb = 0x40000b90; +ieee80211_output_process = 0x40000b94; +ieee80211_set_tx_desc = 0x40000b98; +sta_input = 0x40000b9c; +wifi_get_macaddr = 0x40000ba0; +wifi_rf_phy_disable = 0x40000ba4; +wifi_rf_phy_enable = 0x40000ba8; +ic_ebuf_alloc = 0x40000bac; +ieee80211_classify = 0x40000bb0; +ieee80211_copy_eb_header = 0x40000bb4; +ieee80211_recycle_cache_eb = 0x40000bb8; +ieee80211_search_node = 0x40000bbc; +ieee80211_crypto_encap = 0x40000bc0; +ieee80211_crypto_decap = 0x40000bc4; +ieee80211_decap = 0x40000bc8; +wifi_is_started = 0x40000bcc; +ieee80211_gettid = 0x40000bd0; +ieee80211_encap_esfbuf_htc = 0x40000bd4; +/* Data (.data, .bss, .rodata) */ +net80211_funcs = 0x4087ffac; +g_scan = 0x4087ffa8; +g_chm = 0x4087ffa4; +g_ic_ptr = 0x4087ffa0; +g_hmac_cnt_ptr = 0x4087ff9c; +g_tx_cacheq_ptr = 0x4087ff98; +s_netstack_free = 0x4087ff94; +mesh_rxcb = 0x4087ff90; +sta_rxcb = 0x4087ff8c; +g_itwt_fid = 0x4087ff88; +esp_test_tx_addba_request = 0x4087ff84; diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.newlib-nano.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.newlib-nano.ld new file mode 100644 index 0000000000..ceb70b0fd5 --- /dev/null +++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.newlib-nano.ld @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32c6.rom.newlib-nano.ld for esp32c6 + * + * + * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum ff3b116f1987b5a5433645b8f7947f32 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group newlib_nano_format + ***************************************/ + +/* Functions */ +__sprint_r = 0x400005c8; +_fiprintf_r = 0x400005cc; +_fprintf_r = 0x400005d0; +_printf_common = 0x400005d4; +_printf_i = 0x400005d8; +_vfiprintf_r = 0x400005dc; +_vfprintf_r = 0x400005e0; +fiprintf = 0x400005e4; +fprintf = 0x400005e8; +printf = 0x400005ec; +vfiprintf = 0x400005f0; +vfprintf = 0x400005f4; diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.newlib-normal.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.newlib-normal.ld new file mode 100644 index 0000000000..0a7101b10b --- /dev/null +++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.newlib-normal.ld @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32c6.rom.newlib-normal.ld for esp32c6 + * + * + * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group newlib_normal_format + ***************************************/ + +/* Functions */ +__sprint_r = 0x400005d4; +_fiprintf_r = 0x400005d8; +_fprintf_r = 0x400005dc; +_vfiprintf_r = 0x400005e0; +_vfprintf_r = 0x400005e4; +fiprintf = 0x400005e8; +fprintf = 0x400005ec; +printf = 0x400005f0; +vfiprintf = 0x400005f4; +vfprintf = 0x400005f8; +asprintf = 0x400005fc; +sprintf = 0x40000600; +snprintf = 0x40000604; +siprintf = 0x40000608; +sniprintf = 0x4000060c; +vprintf = 0x40000610; +viprintf = 0x40000614; +vsnprintf = 0x40000618; +vsniprintf = 0x4000061c; +sscanf = 0x40000620; +siscanf = 0x40000624; diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.newlib-time.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.newlib-time.ld new file mode 100644 index 0000000000..27734ced89 --- /dev/null +++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.newlib-time.ld @@ -0,0 +1,15 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* These are the newlib functions and the .bss/.data symbols which are related to 'time_t' + or other structures which include 'time_t' (like 'struct stat'). + These ROM functions were compiled with sizeof(time_t) == 4. + When compiling with sizeof(time_t) == 8, these functions should be excluded from the build. + */ + +_isatty_r = 0x40000380; +PROVIDE( __smakebuf_r = 0x4000046c ); +PROVIDE( __swhatbuf_r = 0x40000470 ); +PROVIDE( __swsetup_r = 0x4000047c ); diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.newlib.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.newlib.ld new file mode 100644 index 0000000000..fcc63288a8 --- /dev/null +++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.newlib.ld @@ -0,0 +1,99 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32c6.rom.newlib.ld for esp32c6 + * + * + * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group newlib + ***************************************/ + +/* Functions */ +esp_rom_newlib_init_common_mutexes = 0x400004a4; +memset = 0x400004a8; +memcpy = 0x400004ac; +memmove = 0x400004b0; +memcmp = 0x400004b4; +strcpy = 0x400004b8; +strncpy = 0x400004bc; +strcmp = 0x400004c0; +strncmp = 0x400004c4; +strlen = 0x400004c8; +strstr = 0x400004cc; +bzero = 0x400004d0; +_isatty_r = 0x400004d4; +sbrk = 0x400004d8; +isalnum = 0x400004dc; +isalpha = 0x400004e0; +isascii = 0x400004e4; +isblank = 0x400004e8; +iscntrl = 0x400004ec; +isdigit = 0x400004f0; +islower = 0x400004f4; +isgraph = 0x400004f8; +isprint = 0x400004fc; +ispunct = 0x40000500; +isspace = 0x40000504; +isupper = 0x40000508; +toupper = 0x4000050c; +tolower = 0x40000510; +toascii = 0x40000514; +memccpy = 0x40000518; +memchr = 0x4000051c; +memrchr = 0x40000520; +strcasecmp = 0x40000524; +strcasestr = 0x40000528; +strcat = 0x4000052c; +strdup = 0x40000530; +strchr = 0x40000534; +strcspn = 0x40000538; +strcoll = 0x4000053c; +strlcat = 0x40000540; +strlcpy = 0x40000544; +strlwr = 0x40000548; +strncasecmp = 0x4000054c; +strncat = 0x40000550; +strndup = 0x40000554; +strnlen = 0x40000558; +strrchr = 0x4000055c; +strsep = 0x40000560; +strspn = 0x40000564; +strtok_r = 0x40000568; +strupr = 0x4000056c; +longjmp = 0x40000570; +setjmp = 0x40000574; +abs = 0x40000578; +div = 0x4000057c; +labs = 0x40000580; +ldiv = 0x40000584; +qsort = 0x40000588; +rand_r = 0x4000058c; +rand = 0x40000590; +srand = 0x40000594; +utoa = 0x40000598; +itoa = 0x4000059c; +atoi = 0x400005a0; +atol = 0x400005a4; +strtol = 0x400005a8; +strtoul = 0x400005ac; +fflush = 0x400005b0; +_fflush_r = 0x400005b4; +_fwalk = 0x400005b8; +_fwalk_reent = 0x400005bc; +__smakebuf_r = 0x400005c0; +__swhatbuf_r = 0x400005c4; +__swbuf_r = 0x400005c8; +__swbuf = 0x400005cc; +__swsetup_r = 0x400005d0; +/* Data (.data, .bss, .rodata) */ +syscall_table_ptr = 0x4087ffd4; +_global_impure_ptr = 0x4087ffd0; diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.phy.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.phy.ld new file mode 100644 index 0000000000..6dba9fd819 --- /dev/null +++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.phy.ld @@ -0,0 +1,249 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32c6.rom.phy.ld for esp32c6 + * + * + * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group rom_phy + ***************************************/ + +/* Functions */ +phy_param_addr = 0x40001104; +phy_get_romfuncs = 0x40001108; +chip761_phyrom_version = 0x4000110c; +chip761_phyrom_version_num = 0x40001110; +get_rc_dout = 0x40001114; +rc_cal = 0x40001118; +rom_enter_critical_phy = 0x4000111c; +rom_exit_critical_phy = 0x40001120; +rom_set_chan_cal_interp = 0x40001124; +rom_loopback_mode_en = 0x40001128; +rom_bb_bss_cbw40 = 0x4000112c; +abs_temp = 0x40001130; +get_data_sat = 0x40001134; +phy_byte_to_word = 0x40001138; +set_chan_reg = 0x4000113c; +i2c_master_reset = 0x40001140; +rom_set_chan_freq_sw_start = 0x40001144; +freq_module_resetn = 0x40001148; +freq_chan_en_sw = 0x4000114c; +write_chan_freq = 0x40001150; +get_freq_mem_param = 0x40001154; +get_freq_mem_addr = 0x40001158; +bt_txpwr_freq = 0x4000115c; +wr_rf_freq_mem = 0x40001160; +read_rf_freq_mem = 0x40001164; +freq_i2c_mem_write = 0x40001168; +freq_num_get_data = 0x4000116c; +freq_i2c_num_addr = 0x40001170; +freq_i2c_write_set = 0x40001174; +pll_dac_mem_update = 0x40001178; +pll_cap_mem_update = 0x4000117c; +get_rf_freq_cap = 0x40001180; +get_rf_freq_init = 0x40001184; +phy_en_hw_set_freq = 0x40001188; +phy_dis_hw_set_freq = 0x4000118c; +rom_pwdet_sar2_init = 0x40001190; +rom_en_pwdet = 0x40001194; +rom_get_sar_sig_ref = 0x40001198; +rom_pwdet_tone_start = 0x4000119c; +rom_pwdet_wait_idle = 0x400011a0; +rom_read_sar_dout = 0x400011a4; +get_tone_sar_dout = 0x400011a8; +get_fm_sar_dout = 0x400011ac; +txtone_linear_pwr = 0x400011b0; +linear_to_db = 0x400011b4; +get_power_db = 0x400011b8; +meas_tone_pwr_db = 0x400011bc; +pkdet_vol_start = 0x400011c0; +read_sar2_code = 0x400011c4; +get_sar2_vol = 0x400011c8; +get_pll_vol = 0x400011cc; +tx_pwctrl_bg_init = 0x400011d0; +phy_pwdet_always_en = 0x400011d4; +phy_pwdet_onetime_en = 0x400011d8; +esp_tx_state_out_rom = 0x400011dc; +ant_dft_cfg_rom = 0x400011e0; +ant_wifitx_cfg_rom = 0x400011e4; +ant_wifirx_cfg_rom = 0x400011e8; +ant_bttx_cfg_rom = 0x400011ec; +ant_btrx_cfg_rom = 0x400011f0; +phy_chan_dump_cfg_rom = 0x400011f4; +phy_enable_low_rate = 0x400011f8; +phy_disable_low_rate = 0x400011fc; +phy_is_low_rate_enabled = 0x40001200; +phy_dig_reg_backup_rom = 0x40001204; +phy_chan_filt_set_rom = 0x40001208; +phy_rx11blr_cfg = 0x4000120c; +set_cca_rom = 0x40001210; +set_rx_sense_rom = 0x40001214; +rx_gain_force_rom = 0x40001218; +rom_rfpll_set_freq = 0x4000121c; +mhz2ieee = 0x40001220; +chan_to_freq = 0x40001224; +restart_cal = 0x40001228; +write_rfpll_sdm = 0x4000122c; +wait_rfpll_cal_end = 0x40001230; +set_rf_freq_offset = 0x40001234; +set_rfpll_freq = 0x40001238; +set_channel_rfpll_freq = 0x4000123c; +rfpll_cap_correct = 0x40001240; +rfpll_cap_init_cal = 0x40001244; +write_pll_cap = 0x40001248; +read_pll_cap = 0x4000124c; +chip_v7_set_chan_ana = 0x40001250; +freq_set_reg = 0x40001254; +gen_rx_gain_table = 0x40001258; +bt_txdc_cal = 0x4000125c; +bt_txiq_cal = 0x40001260; +txiq_cal_init = 0x40001264; +txdc_cal_init = 0x40001268; +txdc_cal = 0x4000126c; +txiq_get_mis_pwr = 0x40001270; +txiq_cover = 0x40001274; +rfcal_txiq = 0x40001278; +get_power_atten = 0x4000127c; +pwdet_ref_code = 0x40001280; +pwdet_code_cal = 0x40001284; +rfcal_txcap = 0x40001288; +tx_cap_init = 0x4000128c; +rfcal_pwrctrl = 0x40001290; +tx_pwctrl_init_cal = 0x40001294; +tx_pwctrl_init = 0x40001298; +bt_tx_pwctrl_init = 0x4000129c; +rom_i2c_enter_critical = 0x400012a0; +rom_i2c_exit_critical = 0x400012a4; +rom_get_i2c_read_mask = 0x400012a8; +rom_get_i2c_mst0_mask = 0x400012ac; +rom_get_i2c_hostid = 0x400012b0; +rom_chip_i2c_readReg_org = 0x400012b4; +rom_chip_i2c_readReg = 0x400012b8; +rom_i2c_readReg = 0x400012bc; +rom_chip_i2c_writeReg = 0x400012c0; +rom_i2c_writeReg = 0x400012c4; +rom_i2c_readReg_Mask = 0x400012c8; +rom_i2c_writeReg_Mask = 0x400012cc; +rom_set_txcap_reg = 0x400012d0; +i2c_paral_set_mst0 = 0x400012d4; +i2c_paral_set_read = 0x400012d8; +i2c_paral_read = 0x400012dc; +i2c_paral_write = 0x400012e0; +i2c_paral_write_num = 0x400012e4; +i2c_paral_write_mask = 0x400012e8; +i2c_sar2_init_code = 0x400012ec; +rom_pbus_force_mode = 0x400012f0; +rom_pbus_rd_addr = 0x400012f4; +rom_pbus_rd_shift = 0x400012f8; +rom_pbus_force_test = 0x400012fc; +rom_pbus_rd = 0x40001300; +rom_pbus_set_rxgain = 0x40001304; +rom_pbus_xpd_rx_off = 0x40001308; +rom_pbus_xpd_rx_on = 0x4000130c; +rom_pbus_xpd_tx_off = 0x40001310; +rom_pbus_xpd_tx_on = 0x40001314; +rom_set_loopback_gain = 0x40001318; +rom_txcal_debuge_mode = 0x4000131c; +pbus_debugmode = 0x40001320; +pbus_workmode = 0x40001324; +pbus_set_dco = 0x40001328; +txcal_work_mode = 0x4000132c; +rom_start_tx_tone_step = 0x40001330; +rom_stop_tx_tone = 0x40001334; +disable_agc = 0x40001338; +enable_agc = 0x4000133c; +phy_disable_cca = 0x40001340; +phy_enable_cca = 0x40001344; +write_gain_mem = 0x40001348; +bb_bss_cbw40_dig = 0x4000134c; +cbw2040_cfg = 0x40001350; +mac_tx_chan_offset = 0x40001354; +tx_paon_set = 0x40001358; +pwdet_reg_init = 0x4000135c; +i2cmst_reg_init = 0x40001360; +bt_gain_offset = 0x40001364; +fe_reg_init = 0x40001368; +mac_enable_bb = 0x4000136c; +bb_wdg_cfg = 0x40001370; +fe_txrx_reset = 0x40001374; +set_rx_comp = 0x40001378; +agc_reg_init = 0x4000137c; +bb_reg_init = 0x40001380; +open_i2c_xpd = 0x40001384; +txiq_set_reg = 0x40001388; +rxiq_set_reg = 0x4000138c; +set_txclk_en = 0x40001390; +set_rxclk_en = 0x40001394; +bb_wdg_test_en = 0x40001398; +noise_floor_auto_set = 0x4000139c; +read_hw_noisefloor = 0x400013a0; +iq_corr_enable = 0x400013a4; +wifi_agc_sat_gain = 0x400013a8; +phy_bbpll_cal = 0x400013ac; +phy_ant_init = 0x400013b0; +phy_set_bbfreq_init = 0x400013b4; +wifi_fbw_sel = 0x400013b8; +bt_filter_reg = 0x400013bc; +phy_rx_sense_set = 0x400013c0; +tx_state_set = 0x400013c4; +phy_close_pa = 0x400013c8; +phy_freq_correct = 0x400013cc; +set_pbus_reg = 0x400013d0; +wifi_rifs_mode_en = 0x400013d4; +nrx_freq_set = 0x400013d8; +fe_adc_on = 0x400013dc; +phy_force_pwr_index = 0x400013e0; +rom_iq_est_enable = 0x400013e4; +rom_iq_est_disable = 0x400013e8; +rom_bb_gain_index = 0x400013ec; +rom_rfrx_gain_index = 0x400013f0; +dc_iq_est = 0x400013f4; +set_cal_rxdc = 0x400013f8; +rxiq_get_mis = 0x400013fc; +rxiq_cover_mg_mp = 0x40001400; +rfcal_rxiq = 0x40001404; +get_rfcal_rxiq_data = 0x40001408; +get_dco_comp = 0x4000140c; +pbus_rx_dco_cal = 0x40001410; +rxdc_est_min = 0x40001414; +pbus_rx_dco_cal_1step = 0x40001418; +set_lb_txiq = 0x4000141c; +set_rx_gain_cal_iq = 0x40001420; +set_rx_gain_cal_dc = 0x40001424; +spur_reg_write_one_tone = 0x40001428; +spur_cal = 0x4000142c; +spur_coef_cfg = 0x40001430; +tsens_power_up = 0x40001434; +tsens_read_init = 0x40001438; +code_to_temp = 0x4000143c; +tsens_index_to_dac = 0x40001440; +tsens_index_to_offset = 0x40001444; +tsens_dac_cal = 0x40001448; +tsens_code_read = 0x4000144c; +tsens_temp_read = 0x40001450; +temp_to_power = 0x40001454; +get_temp_init = 0x40001458; +txbbgain_to_index = 0x4000145c; +index_to_txbbgain = 0x40001460; +bt_index_to_bb = 0x40001464; +bt_bb_to_index = 0x40001468; +bt_get_tx_gain = 0x4000146c; +dig_gain_check = 0x40001470; +wifi_get_tx_gain = 0x40001474; +wifi_11g_rate_chg = 0x40001478; +bt_chan_pwr_interp = 0x4000147c; +get_rate_fcc_index = 0x40001480; +get_chan_target_power = 0x40001484; +get_tx_gain_value = 0x40001488; +wifi_get_target_power = 0x4000148c; +/* Data (.data, .bss, .rodata) */ +phy_param_rom = 0x4087fce8; diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.pp.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.pp.ld new file mode 100644 index 0000000000..b29b5f95ce --- /dev/null +++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.pp.ld @@ -0,0 +1,459 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32c6.rom.pp.ld for esp32c6 + * + * + * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group rom_pp + ***************************************/ + +/* Functions */ +esp_pp_rom_version_get = 0x40000bd8; +ppCalTxopRTSThreshold = 0x40000bdc; +RC_GetBlockAckTime = 0x40000be0; +ebuf_list_remove = 0x40000be4; +esf_buf_alloc = 0x40000be8; +esf_buf_alloc_dynamic = 0x40000bec; +esf_buf_recycle = 0x40000bf0; +GetAccess = 0x40000bf4; +hal_mac_is_low_rate_enabled = 0x40000bf8; +hal_mac_tx_get_blockack = 0x40000bfc; +hal_mac_tx_set_ppdu = 0x40000c00; +ic_get_trc = 0x40000c04; +ic_mac_deinit = 0x40000c08; +ic_mac_init = 0x40000c0c; +ic_interface_enabled = 0x40000c10; +is_lmac_idle = 0x40000c14; +lmacAdjustTimestamp = 0x40000c18; +lmacDiscardAgedMSDU = 0x40000c1c; +lmacDiscardMSDU = 0x40000c20; +lmacEndFrameExchangeSequence = 0x40000c24; +lmacIsIdle = 0x40000c28; +lmacIsLongFrame = 0x40000c2c; +lmacMSDUAged = 0x40000c30; +lmacPostTxComplete = 0x40000c34; +lmacProcessAllTxTimeout = 0x40000c38; +lmacProcessCollisions = 0x40000c3c; +lmacProcessRxSucData = 0x40000c40; +lmacReachLongLimit = 0x40000c44; +lmacReachShortLimit = 0x40000c48; +lmacRecycleMPDU = 0x40000c4c; +lmacRxDone = 0x40000c50; +lmacSetTxFrame = 0x40000c54; +lmacTxDone = 0x40000c58; +lmacTxFrame = 0x40000c5c; +mac_tx_set_duration = 0x40000c60; +mac_tx_set_plcp0 = 0x40000c64; +mac_tx_set_plcp1 = 0x40000c68; +mac_tx_set_plcp2 = 0x40000c6c; +pm_check_state = 0x40000c70; +pm_disable_dream_timer = 0x40000c74; +pm_disable_sleep_delay_timer = 0x40000c78; +pm_dream = 0x40000c7c; +pm_mac_wakeup = 0x40000c80; +pm_mac_sleep = 0x40000c84; +pm_enable_active_timer = 0x40000c88; +pm_enable_sleep_delay_timer = 0x40000c8c; +pm_local_tsf_process = 0x40000c90; +pm_set_beacon_filter = 0x40000c94; +pm_is_in_wifi_slice_threshold = 0x40000c98; +pm_is_waked = 0x40000c9c; +pm_keep_alive = 0x40000ca0; +pm_on_beacon_rx = 0x40000ca4; +pm_on_data_rx = 0x40000ca8; +pm_on_tbtt = 0x40000cac; +pm_parse_beacon = 0x40000cb0; +pm_process_tim = 0x40000cb4; +pm_rx_beacon_process = 0x40000cb8; +pm_rx_data_process = 0x40000cbc; +pm_sleep = 0x40000cc0; +pm_sleep_for = 0x40000cc4; +pm_tbtt_process = 0x40000cc8; +ppAMPDU2Normal = 0x40000ccc; +ppAssembleAMPDU = 0x40000cd0; +ppCalFrameTimes = 0x40000cd4; +ppCalSubFrameLength = 0x40000cd8; +ppCalTxAMPDULength = 0x40000cdc; +ppCheckTxAMPDUlength = 0x40000ce0; +ppDequeueRxq_Locked = 0x40000ce4; +ppDequeueTxQ = 0x40000ce8; +ppEmptyDelimiterLength = 0x40000cec; +ppEnqueueRxq = 0x40000cf0; +ppEnqueueTxDone = 0x40000cf4; +ppGetTxframe = 0x40000cf8; +ppMapTxQueue = 0x40000cfc; +ppProcTxSecFrame = 0x40000d00; +ppProcessRxPktHdr = 0x40000d04; +ppProcessTxQ = 0x40000d08; +ppRecordBarRRC = 0x40000d0c; +ppRecycleAmpdu = 0x40000d10; +ppRecycleRxPkt = 0x40000d14; +ppResortTxAMPDU = 0x40000d18; +ppResumeTxAMPDU = 0x40000d1c; +ppRxFragmentProc = 0x40000d20; +ppRxPkt = 0x40000d24; +ppRxProtoProc = 0x40000d28; +ppSearchTxQueue = 0x40000d2c; +ppSearchTxframe = 0x40000d30; +ppSelectNextQueue = 0x40000d34; +ppSubFromAMPDU = 0x40000d38; +ppTask = 0x40000d3c; +ppTxPkt = 0x40000d40; +ppTxProtoProc = 0x40000d44; +ppTxqUpdateBitmap = 0x40000d48; +pp_coex_tx_request = 0x40000d4c; +pp_hdrsize = 0x40000d50; +pp_post = 0x40000d54; +pp_process_hmac_waiting_txq = 0x40000d58; +rcGetAmpduSched = 0x40000d5c; +rcUpdateRxDone = 0x40000d60; +rc_get_trc = 0x40000d64; +rc_get_trc_by_index = 0x40000d68; +rcAmpduLowerRate = 0x40000d6c; +rcampduuprate = 0x40000d70; +rcClearCurAMPDUSched = 0x40000d74; +rcClearCurSched = 0x40000d78; +rcClearCurStat = 0x40000d7c; +rcGetSched = 0x40000d80; +rcLowerSched = 0x40000d84; +rcSetTxAmpduLimit = 0x40000d88; +rcTxUpdatePer = 0x40000d8c; +rcUpdateAckSnr = 0x40000d90; +rcUpdateRate = 0x40000d94; +rcUpdateTxDone = 0x40000d98; +rcUpdateTxDoneAmpdu2 = 0x40000d9c; +rcUpSched = 0x40000da0; +rssi_margin = 0x40000da4; +rx11NRate2AMPDULimit = 0x40000da8; +TRC_AMPDU_PER_DOWN_THRESHOLD = 0x40000dac; +TRC_AMPDU_PER_UP_THRESHOLD = 0x40000db0; +trc_calc_duration = 0x40000db4; +trc_isTxAmpduOperational = 0x40000db8; +trc_onAmpduOp = 0x40000dbc; +TRC_PER_IS_GOOD = 0x40000dc0; +trc_SetTxAmpduState = 0x40000dc4; +trc_tid_isTxAmpduOperational = 0x40000dc8; +trcAmpduSetState = 0x40000dcc; +wDevCheckBlockError = 0x40000dd0; +wDev_AppendRxBlocks = 0x40000dd4; +wDev_DiscardFrame = 0x40000dd8; +wDev_GetNoiseFloor = 0x40000ddc; +wDev_IndicateAmpdu = 0x40000de0; +wDev_IndicateFrame = 0x40000de4; +wdev_mac_reg_load = 0x40000de8; +wdev_mac_reg_store = 0x40000dec; +wdev_mac_special_reg_load = 0x40000df0; +wdev_mac_special_reg_store = 0x40000df4; +wdev_mac_wakeup = 0x40000df8; +wdev_mac_sleep = 0x40000dfc; +hal_mac_is_dma_enable = 0x40000e00; +wDev_ProcessFiq = 0x40000e04; +wDev_ProcessRxSucData = 0x40000e08; +wdevProcessRxSucDataAll = 0x40000e0c; +wdev_csi_len_align = 0x40000e10; +ppDequeueTxDone_Locked = 0x40000e14; +ppProcTxDone = 0x40000e18; +pm_tx_data_done_process = 0x40000e1c; +config_is_cache_tx_buf_enabled = 0x40000e20; +ppMapWaitTxq = 0x40000e24; +ppProcessWaitingQueue = 0x40000e28; +ppDisableQueue = 0x40000e2c; +pm_allow_tx = 0x40000e30; +wdev_is_data_in_rxlist = 0x40000e34; +ppProcTxCallback = 0x40000e38; +mac_tx_set_hesig = 0x40000e3c; +ppCalPreFecPaddingFactor = 0x40000e40; +mac_tx_set_tb = 0x40000e44; +mac_tx_set_mplen = 0x40000e48; +hal_get_tsf_timer = 0x40000e4c; +ppTxPktForceWaked = 0x40000e50; +lmacProcessLongFrameSuccess = 0x40000e54; +lmacProcessShortFrameSuccess = 0x40000e58; +lmacDiscardFrameExchangeSequence = 0x40000e5c; +lmacProcessTBSuccess = 0x40000e60; +lmacProcessTxSuccess = 0x40000e64; +lmacProcessAckTimeout = 0x40000e68; +lmacProcessTxComplete = 0x40000e6c; +ppRemoveHTC = 0x40000e70; +get_estimated_batime = 0x40000e74; +is_use_muedca = 0x40000e78; +hal_mac_tx_clr_mplen = 0x40000e7c; +hal_mac_get_txq_state = 0x40000e80; +hal_mac_clr_txq_state = 0x40000e84; +hal_mac_get_txq_complete = 0x40000e88; +ht_get_min_subframe_len = 0x40000e8c; +rx11ACRate2AMPDULimit = 0x40000e90; +pwr_hal_clear_intr_status = 0x40000e94; +pwr_hal_clear_mac_modem_beacon_miss_intr_filter = 0x40000e98; +pwr_hal_clear_mac_modem_rx_beacon_info = 0x40000e9c; +pwr_hal_clear_mac_modem_rx_beacon_miss_counter = 0x40000ea0; +pwr_hal_clear_mac_modem_rx_beacon_sleep_counter = 0x40000ea4; +pwr_hal_clear_mac_modem_state_wakeup_protect_signal = 0x40000ea8; +pwr_hal_get_intr_raw_signal = 0x40000eac; +pwr_hal_get_intr_status = 0x40000eb0; +pwr_hal_get_mac_modem_beacon_miss_limit_exceeded_status = 0x40000eb4; +pwr_hal_get_mac_modem_rx_beacon_location_state = 0x40000eb8; +pwr_hal_get_mac_modem_rx_beacon_valid_state = 0x40000ebc; +pwr_hal_get_mac_modem_state_sleep_limit_exceeded_status = 0x40000ec0; +pwr_hal_set_beacon_filter_abort_disable = 0x40000ec4; +pwr_hal_set_beacon_filter_abort_enable = 0x40000ec8; +pwr_hal_set_beacon_filter_abort_length = 0x40000ecc; +pwr_hal_set_beacon_filter_broadcast_wakeup_disable = 0x40000ed0; +pwr_hal_set_beacon_filter_broadcast_wakeup_enable = 0x40000ed4; +pwr_hal_set_beacon_filter_disable = 0x40000ed8; +pwr_hal_set_beacon_filter_enable = 0x40000edc; +pwr_hal_set_beacon_filter_force_dump_disable = 0x40000ee0; +pwr_hal_set_beacon_filter_force_dump_enable = 0x40000ee4; +pwr_hal_set_beacon_filter_force_dump_limit = 0x40000ee8; +pwr_hal_set_beacon_filter_force_sync_disable = 0x40000eec; +pwr_hal_set_beacon_filter_force_sync_enable = 0x40000ef0; +pwr_hal_set_beacon_filter_force_sync_limit = 0x40000ef4; +pwr_hal_set_beacon_filter_frame_crc_state = 0x40000ef8; +pwr_hal_set_beacon_filter_soc_wakeup_and_intr_disable = 0x40000efc; +pwr_hal_set_beacon_filter_soc_wakeup_and_intr_enable = 0x40000f00; +pwr_hal_set_beacon_filter_unicast_wakeup_disable = 0x40000f04; +pwr_hal_set_beacon_filter_unicast_wakeup_enable = 0x40000f08; +pwr_hal_set_lpclk_cycle_time = 0x40000f0c; +pwr_hal_set_lpclk_sync_disable = 0x40000f10; +pwr_hal_set_lpclk_sync_enable = 0x40000f14; +pwr_hal_set_mac_modem_beacon_miss_intr_disable = 0x40000f18; +pwr_hal_set_mac_modem_beacon_miss_intr_enable = 0x40000f1c; +pwr_hal_set_mac_modem_beacon_miss_limit = 0x40000f20; +pwr_hal_set_mac_modem_beacon_miss_limit_exceeded_wakeup_disable = 0x40000f24; +pwr_hal_set_mac_modem_beacon_miss_limit_exceeded_wakeup_enable = 0x40000f28; +pwr_hal_set_mac_modem_beacon_miss_timeout = 0x40000f2c; +pwr_hal_set_mac_modem_state_sleep_limit = 0x40000f30; +pwr_hal_set_mac_modem_state_sleep_limit_exceeded_wakeup_disable = 0x40000f34; +pwr_hal_set_mac_modem_state_sleep_limit_exceeded_wakeup_enable = 0x40000f38; +pwr_hal_set_mac_modem_state_wakeup_protect_disable = 0x40000f3c; +pwr_hal_set_mac_modem_state_wakeup_protect_early_time = 0x40000f40; +pwr_hal_set_mac_modem_state_wakeup_protect_enable = 0x40000f44; +pwr_hal_set_mac_modem_tbtt_auto_period_disable = 0x40000f48; +pwr_hal_set_mac_modem_tbtt_auto_period_enable = 0x40000f4c; +pwr_hal_set_mac_modem_tbtt_auto_period_interval = 0x40000f50; +pwr_hal_set_modem_state_interface = 0x40000f54; +hal_tsf_clear_soc_wakeup_request = 0x40000f58; +tsf_hal_clear_mac_modem_rf_power_state = 0x40000f5c; +tsf_hal_clear_soc_wakeup_request = 0x40000f60; +tsf_hal_get_counter_value = 0x40000f64; +tsf_hal_get_mac_modem_rf_power_state = 0x40000f68; +tsf_hal_get_tbtt_interval = 0x40000f6c; +tsf_hal_get_time = 0x40000f70; +tsf_hal_get_timer_target = 0x40000f74; +tsf_hal_is_tsf_enabled = 0x40000f78; +tsf_hal_map_tbtt_target_to_rx_frame = 0x40000f7c; +tsf_hal_map_tsf_to_bssid = 0x40000f80; +tsf_hal_set_counter_value = 0x40000f84; +tsf_hal_set_modem_wakeup_early_time = 0x40000f88; +tsf_hal_set_rx_beacon_abort_tsf_time_deviation_sync_disable = 0x40000f8c; +tsf_hal_set_rx_beacon_abort_tsf_time_deviation_sync_enable = 0x40000f90; +tsf_hal_set_rx_beacon_fail_tsf_time_deviation_sync_disable = 0x40000f94; +tsf_hal_set_rx_beacon_fail_tsf_time_deviation_sync_enable = 0x40000f98; +tsf_hal_set_rx_beacon_success_tsf_time_deviation_sync_disable = 0x40000f9c; +tsf_hal_set_rx_beacon_success_tsf_time_deviation_sync_enable = 0x40000fa0; +tsf_hal_set_tbtt_disable = 0x40000fa4; +tsf_hal_set_tbtt_early_time = 0x40000fa8; +tsf_hal_set_tbtt_enable = 0x40000fac; +tsf_hal_set_tbtt_interval = 0x40000fb0; +tsf_hal_set_tbtt_intr_disable = 0x40000fb4; +tsf_hal_set_tbtt_intr_enable = 0x40000fb8; +tsf_hal_set_tbtt_modem_wakeup_disable = 0x40000fbc; +tsf_hal_set_tbtt_modem_wakeup_enable = 0x40000fc0; +tsf_hal_set_tbtt_rf_ctrl_disable = 0x40000fc4; +tsf_hal_set_tbtt_rf_ctrl_enable = 0x40000fc8; +tsf_hal_set_tbtt_rf_ctrl_wait_cycles = 0x40000fcc; +tsf_hal_set_tbtt_soc_wakeup_disable = 0x40000fd0; +tsf_hal_set_tbtt_soc_wakeup_enable = 0x40000fd4; +tsf_hal_set_tbtt_start_time = 0x40000fd8; +tsf_hal_set_time = 0x40000fdc; +tsf_hal_set_timer_disable = 0x40000fe0; +tsf_hal_set_timer_enable = 0x40000fe4; +tsf_hal_set_timer_intr_disable = 0x40000fe8; +tsf_hal_set_timer_intr_enable = 0x40000fec; +tsf_hal_set_timer_modem_wakeup_disable = 0x40000ff0; +tsf_hal_set_timer_modem_wakeup_enable = 0x40000ff4; +tsf_hal_set_timer_rf_ctrl_disable = 0x40000ff8; +tsf_hal_set_timer_rf_ctrl_enable = 0x40000ffc; +tsf_hal_set_timer_rf_ctrl_wait_cycles = 0x40001000; +tsf_hal_set_timer_soc_wakeup_disable = 0x40001004; +tsf_hal_set_timer_soc_wakeup_enable = 0x40001008; +tsf_hal_set_timer_target = 0x4000100c; +tsf_hal_set_tsf_disable = 0x40001010; +tsf_hal_set_tsf_enable = 0x40001014; +tsf_hal_set_tsf_time_deviation = 0x40001018; +tsf_hal_set_tsf_time_deviation_sync_disable = 0x4000101c; +tsf_hal_set_tsf_time_deviation_sync_enable = 0x40001020; +tsf_hal_unmap_tbtt_target_to_rx_frame = 0x40001024; +ppSelectTxFormat = 0x40001028; +ppCertSetRate = 0x4000102c; +ppHEAMPDU2Normal = 0x40001030; +ppCalTxHEAMPDULength = 0x40001034; +ppCalTxHESMPDULength = 0x40001038; +rcGetRate = 0x4000103c; +rcGetDCMMaxRate = 0x40001040; +rcGetSMPDURate = 0x40001044; +ppDirectRecycleAmpdu = 0x40001048; +ppCheckTxHEAMPDUlength = 0x4000104c; +rx11AXRate2AMPDULimit = 0x40001050; +ppRegressAmpdu = 0x40001054; +ppCalDeliNum = 0x40001058; +ppAdd2AMPDUTail = 0x4000105c; +esp_test_disable_tx_statistics = 0x40001060; +esp_test_enable_tx_statistics = 0x40001064; +esp_test_clr_tx_statistics = 0x40001068; +esp_test_get_tx_statistics = 0x4000106c; +esp_test_clr_tx_tb_statistics = 0x40001070; +esp_test_get_tx_tb_statistics = 0x40001074; +test_tx_fail_statistics = 0x40001078; +test_tx_succ_statistics = 0x4000107c; +esp_test_tx_process_complete = 0x40001080; +esp_test_tx_process_txq_state = 0x40001084; +esp_test_tx_enab_statistics = 0x40001088; +esp_test_tx_tb_complete = 0x4000108c; +esp_test_tx_count_retry = 0x40001090; +esp_test_tx_count_collision = 0x40001094; +esp_test_tx_count_timeout = 0x40001098; +hal_enable_tx_statistics = 0x4000109c; +test_rx_process_complete_noeb = 0x400010a0; +test_rx_process_complete_retry = 0x400010a4; +esp_test_rx_process_complete = 0x400010a8; +esp_test_clr_rx_statistics = 0x400010ac; +esp_test_get_rx_statistics = 0x400010b0; +test_free_rx_statistics = 0x400010b4; +esp_test_set_rx_error_occurs = 0x400010b8; +esp_test_get_rx_error_occurs = 0x400010bc; +esp_test_clr_rx_error_occurs = 0x400010c0; +esp_test_disable_rx_statistics = 0x400010c4; +esp_test_enable_rx_statistics = 0x400010c8; +hal_enable_rx_statistics = 0x400010cc; +get_user_num = 0x400010d0; +mumimo_spatial_cfg_get_nsts = 0x400010d4; +mumimo_spatial_cfg_get_nsts_tot = 0x400010d8; +test_mumimo_get_heltf_num = 0x400010dc; +test_mimo_update_user_info = 0x400010e0; +test_parse_rx_mu_mimo = 0x400010e4; +test_nonmimo_update_user_info = 0x400010e8; +test_parse_rx_mu_nonmimo = 0x400010ec; +esp_test_rx_parse_mu = 0x400010f0; +esp_test_get_rx_mu_statistics = 0x400010f4; +esp_test_clr_rx_mu_statistics = 0x400010f8; +esp_test_enable_rx_mu_statistics = 0x400010fc; +esp_test_disable_rx_mu_statistics = 0x40001100; +/* Data (.data, .bss, .rodata) */ +our_instances_ptr = 0x4004ffe0; +pTxRx = 0x4087ff80; +lmacConfMib_ptr = 0x4087ff7c; +our_wait_eb = 0x4087ff78; +our_tx_eb = 0x4087ff74; +pp_wdev_funcs = 0x4087ff70; +g_osi_funcs_p = 0x4087ff6c; +wDevCtrl_ptr = 0x4087ff68; +g_wdev_last_desc_reset_ptr = 0x4004ffdc; +wDevMacSleep_ptr = 0x4087ff64; +g_lmac_cnt_ptr = 0x4087ff60; +our_controls_ptr = 0x4004ffd8; +pp_sig_cnt_ptr = 0x4087ff5c; +g_eb_list_desc_ptr = 0x4087ff58; +s_fragment_ptr = 0x4087ff54; +if_ctrl_ptr = 0x4087ff50; +g_intr_lock_mux = 0x4087ff4c; +g_wifi_global_lock = 0x4087ff48; +s_wifi_queue = 0x4087ff44; +pp_task_hdl = 0x4087ff40; +s_pp_task_create_sem = 0x4087ff3c; +s_pp_task_del_sem = 0x4087ff38; +g_wifi_menuconfig_ptr = 0x4087ff34; +xphyQueue = 0x4087ff30; +ap_no_lr_ptr = 0x4087ff2c; +rc11BSchedTbl_ptr = 0x4087ff28; +rc11NSchedTbl_ptr = 0x4087ff24; +rcLoRaSchedTbl_ptr = 0x4087ff20; +BasicOFDMSched_ptr = 0x4087ff1c; +trc_ctl_ptr = 0x4087ff18; +g_pm_cnt_ptr = 0x4087ff14; +g_pm_ptr = 0x4087ff10; +g_pm_cfg_ptr = 0x4087ff0c; +g_esp_mesh_quick_funcs_ptr = 0x4087ff08; +g_txop_queue_status_ptr = 0x4087ff04; +g_mac_sleep_en_ptr = 0x4087ff00; +g_mesh_is_root_ptr = 0x4087fefc; +g_mesh_topology_ptr = 0x4087fef8; +g_mesh_init_ps_type_ptr = 0x4087fef4; +g_mesh_is_started_ptr = 0x4087fef0; +g_config_func = 0x4087feec; +g_net80211_tx_func = 0x4087fee8; +g_timer_func = 0x4087fee4; +s_michael_mic_failure_cb = 0x4087fee0; +wifi_sta_rx_probe_req = 0x4087fedc; +g_tx_done_cb_func = 0x4087fed8; +g_per_conn_trc = 0x4087fe8c; +s_encap_amsdu_func = 0x4087fe88; +rx_beacon_count = 0x4087fe84; +rx_beacon_sw_parse = 0x4087fe80; +rx_beacon_hw_parse = 0x4087fe7c; +rx_beacon_tim_count = 0x4087fe78; +rx_beacon_tim_udata = 0x4087fe74; +rx_beacon_tim_udata_bitmap = 0x4087fe70; +rx_beacon_tim_bdata = 0x4087fe6c; +rx_beacon_tim_bdata_bitmapctl = 0x4087fe68; +rx_beacon_tim_bdata_bitmap_trans = 0x4087fe64; +rx_beacon_tim_bdata_bitmap_mbssid_self = 0x4087fe60; +rx_beacon_tim_bdata_bitmap_mbssid_other = 0x4087fe5c; +rx_beacon_dtim_tim = 0x4087fe58; +rx_beacon_dtim_tim_mcast = 0x4087fe54; +amdpu_delay_time_ms = 0x4087fd08; +ampdu_delay_packet = 0x4087fd04; +ampdu_delay = 0x4087fe51; +first_ampdu = 0x4087fe50; +s_ht_ampdu_density_us = 0x4087fd02; +s_ht_ampdu_density = 0x4087fd01; +s_running_phy_type = 0x4087fd00; +complete_ena_tb_seqno = 0x4087fe4c; +complete_ena_tb_final = 0x4087fe48; +complete_ena_tb_count = 0x4087fe44; +s_itwt_state = 0x4087fe40; +g_dbg_interp_tsf = 0x4087fe3c; +g_dbg_interp_tsf_end = 0x4087fe38; +g_dbg_closrf_tsf = 0x4087fe34; +g_dbg_closrf_idx = 0x4087fe30; +g_dbg_closrf_blk = 0x4087fe2c; +s_he_min_len_bytes = 0x4087fdf0; +s_he_dcm_min_len_bytes = 0x4087fdd0; +s_mplen_low_bitmap = 0x4087fdc0; +s_mplen_high_bitmap = 0x4087fdb0; +s_mplen_vi_bitmap = 0x4087fdac; +s_mplen_bk_bitmap = 0x4087fda8; +esp_wifi_cert_tx_mcs = 0x4087fcfc; +esp_wifi_cert_tx_bcc = 0x4087fcf8; +esp_wifi_cert_tx_ltf = 0x4087fcf4; +esp_wifi_cert_tx_gi = 0x4087fcf0; +esp_wifi_cert_tx_nss = 0x4087fcec; +esp_test_tx_statistics_aci_bitmap = 0x4087fda4; +esp_test_tx_statistics = 0x4087fd94; +esp_test_tx_tb_statistics = 0x4087fd84; +esp_test_tx_fail_statistics = 0x4087fd24; +esp_test_rx_statistics = 0x4087fd1c; +esp_test_rx_mu_statistics = 0x4087fd18; +esp_test_mu_print_ru_allocation = 0x4087fd14; +sigb_ru_allocation_user_num = 0x4004ffc8; +sigb_common_ru_allocation = 0x4004ff38; +mu_mimo_special_cfg_user_num_2 = 0x4004fee8; +mu_mimo_special_cfg_user_num_3 = 0x4004fe80; +mu_mimo_special_cfg_user_num_4 = 0x4004fe28; +mu_mimo_special_cfg_user_num_5 = 0x4004fdf0; +mu_mimo_special_cfg_user_num_6 = 0x4004fdd0; +mu_mimo_special_cfg_user_num_7 = 0x4004fdc0; +mu_mimo_special_cfg_user_num_8 = 0x4004fdb8; +esp_test_rx_error_occurs = 0x4087fd10; +g_pp_tx_pkt_num = 0x4087fd0c; +he_max_apep_length = 0x4004fd40; diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.rvfp.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.rvfp.ld new file mode 100644 index 0000000000..26a82ad1c7 --- /dev/null +++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.rvfp.ld @@ -0,0 +1,118 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32c6.rom.rvfp.ld for esp32c6 + * + * + * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group rvfplib + ***************************************/ + +/* Functions */ +__adddf3 = 0x400009f4; +__addsf3 = 0x400009f8; +__eqdf2 = 0x400009fc; +__eqsf2 = 0x40000a00; +__extendsfdf2 = 0x40000a04; +__fixdfdi = 0x40000a08; +__fixdfsi = 0x40000a0c; +__fixsfdi = 0x40000a10; +__fixsfsi = 0x40000a14; +__fixunsdfsi = 0x40000a18; +__fixunssfdi = 0x40000a1c; +__fixunssfsi = 0x40000a20; +__floatdidf = 0x40000a24; +__floatdisf = 0x40000a28; +__floatsidf = 0x40000a2c; +__floatsisf = 0x40000a30; +__floatundidf = 0x40000a34; +__floatundisf = 0x40000a38; +__floatunsidf = 0x40000a3c; +__floatunsisf = 0x40000a40; +__gedf2 = 0x40000a44; +__gesf2 = 0x40000a48; +__gtdf2 = 0x40000a4c; +__gtsf2 = 0x40000a50; +__ledf2 = 0x40000a54; +__lesf2 = 0x40000a58; +__ltdf2 = 0x40000a5c; +__ltsf2 = 0x40000a60; +__muldf3 = 0x40000a64; +__mulsf3 = 0x40000a68; +__nedf2 = 0x40000a6c; +__nesf2 = 0x40000a70; +__subdf3 = 0x40000a74; +__subsf3 = 0x40000a78; +__truncdfsf2 = 0x40000a7c; + +/*************************************** + Group libgcc +***************************************/ + +/* Functions */ +__absvdi2 = 0x40000884; +__absvsi2 = 0x40000888; +__addvdi3 = 0x40000894; +__addvsi3 = 0x40000898; +__ashldi3 = 0x4000089c; +__ashrdi3 = 0x400008a0; +__bswapdi2 = 0x400008a4; +__bswapsi2 = 0x400008a8; +__clear_cache = 0x400008ac; +__clrsbdi2 = 0x400008b0; +__clrsbsi2 = 0x400008b4; +__clzdi2 = 0x400008b8; +__clzsi2 = 0x400008bc; +__cmpdi2 = 0x400008c0; +__ctzdi2 = 0x400008c4; +__ctzsi2 = 0x400008c8; +__divdc3 = 0x400008cc; +__divdf3 = 0x400008d0; +__divdi3 = 0x400008d4; +__divsc3 = 0x400008d8; +__divsf3 = 0x400008dc; +__divsi3 = 0x400008e0; +__ffsdi2 = 0x400008f0; +__ffssi2 = 0x400008f4; +__gcc_bcmp = 0x40000934; +__lshrdi3 = 0x40000950; +__moddi3 = 0x4000095c; +__modsi3 = 0x40000960; +__muldc3 = 0x40000964; +__muldi3 = 0x4000096c; +__mulsc3 = 0x40000970; +__mulsi3 = 0x40000978; +__mulvdi3 = 0x4000097c; +__mulvsi3 = 0x40000980; +__negdf2 = 0x40000988; +__negdi2 = 0x4000098c; +__negsf2 = 0x40000990; +__negvdi2 = 0x40000994; +__negvsi2 = 0x40000998; +__paritysi2 = 0x400009a0; +__popcountdi2 = 0x400009a4; +__popcountsi2 = 0x400009a8; +__powidf2 = 0x400009ac; +__powisf2 = 0x400009b0; +__subvdi3 = 0x400009bc; +__subvsi3 = 0x400009c0; +__ucmpdi2 = 0x400009c8; +__udivdi3 = 0x400009cc; +__udivmoddi4 = 0x400009d0; +__udivsi3 = 0x400009d4; +__udiv_w_sdiv = 0x400009d8; +__umoddi3 = 0x400009dc; +__umodsi3 = 0x400009e0; +__unorddf2 = 0x400009e4; +__unordsf2 = 0x400009e8; +__extenddftf2 = 0x400009ec; +__trunctfdf2 = 0x400009f0; diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.spiflash.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.spiflash.ld new file mode 100644 index 0000000000..3e35d56c60 --- /dev/null +++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.spiflash.ld @@ -0,0 +1,166 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32c6.rom.spiflash.ld for esp32c6 + * + * + * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group spi_flash_cache + ***************************************/ + +/* Functions */ +spi_flash_disable_cache = 0x400001f0; +spi_flash_restore_cache = 0x400001f4; +spi_flash_cache_enabled = 0x400001f8; +spi_flash_enable_cache = 0x400001fc; +esp_enable_cache_flash_wrap = 0x40000200; + + +/*************************************** + Group spi_flash_mmap + ***************************************/ + +/* Functions */ +spi_flash_mmap_os_func_set = 0x40000204; +spi_flash_mmap_page_num_init = 0x40000208; +spi_flash_mmap = 0x4000020c; +spi_flash_mmap_pages = 0x40000210; +spi_flash_munmap = 0x40000214; +spi_flash_mmap_dump = 0x40000218; +spi_flash_check_and_flush_cache = 0x4000021c; +spi_flash_mmap_get_free_pages = 0x40000220; +spi_flash_cache2phys = 0x40000224; +spi_flash_phys2cache = 0x40000228; + + +/*************************************** + Group esp_flash + ***************************************/ + +/* Functions */ +esp_flash_chip_driver_initialized = 0x4000022c; +esp_flash_read_id = 0x40000230; +esp_flash_get_size = 0x40000234; +esp_flash_erase_chip = 0x40000238; +esp_flash_erase_region = 0x4000023c; +esp_flash_get_chip_write_protect = 0x40000240; +esp_flash_set_chip_write_protect = 0x40000244; +esp_flash_get_protectable_regions = 0x40000248; +esp_flash_get_protected_region = 0x4000024c; +esp_flash_set_protected_region = 0x40000250; +esp_flash_read = 0x40000254; +esp_flash_write = 0x40000258; +esp_flash_write_encrypted = 0x4000025c; +esp_flash_read_encrypted = 0x40000260; +esp_flash_get_io_mode = 0x40000264; +esp_flash_set_io_mode = 0x40000268; +spi_flash_boot_attach = 0x4000026c; +esp_flash_read_chip_id = 0x40000270; +detect_spi_flash_chip = 0x40000274; +esp_rom_spiflash_write_disable = 0x40000278; +esp_flash_suspend_cmd_init = 0x4000027c; +/* Data (.data, .bss, .rodata) */ +esp_flash_default_chip = 0x4087ffe8; +esp_flash_api_funcs = 0x4087ffe4; + + +/*************************************** + Group spi_flash_chips + ***************************************/ + +/* Functions */ +spi_flash_chip_generic_probe = 0x40000280; +spi_flash_chip_generic_detect_size = 0x40000284; +spi_flash_chip_generic_write = 0x40000288; +spi_flash_chip_generic_write_encrypted = 0x4000028c; +spi_flash_chip_generic_set_write_protect = 0x40000290; +spi_flash_common_write_status_16b_wrsr = 0x40000294; +spi_flash_chip_generic_reset = 0x40000298; +spi_flash_chip_generic_erase_chip = 0x4000029c; +spi_flash_chip_generic_erase_sector = 0x400002a0; +spi_flash_chip_generic_erase_block = 0x400002a4; +spi_flash_chip_generic_page_program = 0x400002a8; +spi_flash_chip_generic_get_write_protect = 0x400002ac; +spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x400002b0; +spi_flash_chip_generic_read_reg = 0x400002b4; +spi_flash_chip_generic_yield = 0x400002b8; +spi_flash_generic_wait_host_idle = 0x400002bc; +spi_flash_chip_generic_wait_idle = 0x400002c0; +spi_flash_chip_generic_config_host_io_mode = 0x400002c4; +spi_flash_chip_generic_read = 0x400002c8; +spi_flash_common_read_status_8b_rdsr2 = 0x400002cc; +spi_flash_chip_generic_get_io_mode = 0x400002d0; +spi_flash_common_read_status_8b_rdsr = 0x400002d4; +spi_flash_common_write_status_8b_wrsr = 0x400002d8; +spi_flash_common_write_status_8b_wrsr2 = 0x400002dc; +spi_flash_common_set_io_mode = 0x400002e0; +spi_flash_chip_generic_set_io_mode = 0x400002e4; +spi_flash_chip_generic_read_unique_id = 0x400002e8; +spi_flash_chip_generic_get_caps = 0x400002ec; +spi_flash_chip_generic_suspend_cmd_conf = 0x400002f0; +spi_flash_chip_gd_get_io_mode = 0x400002f4; +spi_flash_chip_gd_probe = 0x400002f8; +spi_flash_chip_gd_set_io_mode = 0x400002fc; +/* Data (.data, .bss, .rodata) */ +spi_flash_chip_generic_config_data = 0x4087ffe0; +spi_flash_encryption = 0x4087ffdc; + + +/*************************************** + Group memspi_host + ***************************************/ + +/* Functions */ +memspi_host_read_id_hs = 0x40000300; +memspi_host_read_status_hs = 0x40000304; +memspi_host_flush_cache = 0x40000308; +memspi_host_erase_chip = 0x4000030c; +memspi_host_erase_sector = 0x40000310; +memspi_host_erase_block = 0x40000314; +memspi_host_program_page = 0x40000318; +memspi_host_read = 0x4000031c; +memspi_host_set_write_protect = 0x40000320; +memspi_host_set_max_read_len = 0x40000324; +memspi_host_read_data_slicer = 0x40000328; +memspi_host_write_data_slicer = 0x4000032c; + + +/*************************************** + Group hal_spiflash + ***************************************/ + +/* Functions */ +spi_flash_hal_poll_cmd_done = 0x40000330; +spi_flash_hal_device_config = 0x40000334; +spi_flash_hal_configure_host_io_mode = 0x40000338; +spi_flash_hal_common_command = 0x4000033c; +spi_flash_hal_read = 0x40000340; +spi_flash_hal_erase_chip = 0x40000344; +spi_flash_hal_erase_sector = 0x40000348; +spi_flash_hal_erase_block = 0x4000034c; +spi_flash_hal_program_page = 0x40000350; +spi_flash_hal_set_write_protect = 0x40000354; +spi_flash_hal_host_idle = 0x40000358; +spi_flash_hal_check_status = 0x4000035c; +spi_flash_hal_setup_read_suspend = 0x40000360; +spi_flash_hal_setup_auto_suspend_mode = 0x40000364; +spi_flash_hal_setup_auto_resume_mode = 0x40000368; +spi_flash_hal_disable_auto_suspend_mode = 0x4000036c; +spi_flash_hal_disable_auto_resume_mode = 0x40000370; +spi_flash_hal_resume = 0x40000374; +spi_flash_hal_suspend = 0x40000378; +spi_flash_encryption_hal_enable = 0x4000037c; +spi_flash_encryption_hal_disable = 0x40000380; +spi_flash_encryption_hal_prepare = 0x40000384; +spi_flash_encryption_hal_done = 0x40000388; +spi_flash_encryption_hal_destroy = 0x4000038c; +spi_flash_encryption_hal_check = 0x40000390; diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.version.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.version.ld new file mode 100644 index 0000000000..ad4d15d00f --- /dev/null +++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.version.ld @@ -0,0 +1,13 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM version variables for esp32c6 + * + * These addresses should be compatible with any ROM version for this chip. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ +_rom_chip_id = 0x40000010; +_rom_eco_version = 0x40000014; diff --git a/components/esp_rom/esp32h2/Kconfig.soc_caps.in b/components/esp_rom/esp32h2/Kconfig.soc_caps.in index c6beb32f11..b11f70e542 100644 --- a/components/esp_rom/esp32h2/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32h2/Kconfig.soc_caps.in @@ -34,3 +34,7 @@ config ESP_ROM_HAS_ERASE_0_REGION_BUG config ESP_ROM_GET_CLK_FREQ bool default y + +config ESP_ROM_HAS_LAYOUT_TABLE + bool + default y diff --git a/components/esp_rom/esp32h2/esp_rom_caps.h b/components/esp_rom/esp32h2/esp_rom_caps.h index 151fb44e08..60660e37a2 100644 --- a/components/esp_rom/esp32h2/esp_rom_caps.h +++ b/components/esp_rom/esp32h2/esp_rom_caps.h @@ -14,3 +14,4 @@ #define ESP_ROM_HAS_RETARGETABLE_LOCKING (1) // ROM was built with retargetable locking #define ESP_ROM_HAS_ERASE_0_REGION_BUG (1) // ROM has esp_flash_erase_region(size=0) bug #define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency` +#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table diff --git a/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld b/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld index 2bc1ceb462..96c5a68190 100644 --- a/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld +++ b/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld @@ -6,9 +6,6 @@ /** ROM APIs */ -PROVIDE ( esp_rom_tjpgd_decomp = 0x40000104 ); -PROVIDE ( esp_rom_tjpgd_prepare = 0x40000100 ); - PROVIDE ( esp_rom_crc32_le = crc32_le ); PROVIDE ( esp_rom_crc16_le = crc16_le ); PROVIDE ( esp_rom_crc8_le = crc8_le ); @@ -40,6 +37,9 @@ PROVIDE ( esp_rom_md5_init = MD5Init ); PROVIDE ( esp_rom_md5_update = MD5Update ); PROVIDE ( esp_rom_md5_final = MD5Final ); +PROVIDE ( esp_rom_software_reset_system = software_reset ); +PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); + PROVIDE ( esp_rom_printf = ets_printf ); PROVIDE ( esp_rom_delay_us = ets_delay_us ); PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason ); diff --git a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld index 2bc1ceb462..96c5a68190 100644 --- a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld +++ b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld @@ -6,9 +6,6 @@ /** ROM APIs */ -PROVIDE ( esp_rom_tjpgd_decomp = 0x40000104 ); -PROVIDE ( esp_rom_tjpgd_prepare = 0x40000100 ); - PROVIDE ( esp_rom_crc32_le = crc32_le ); PROVIDE ( esp_rom_crc16_le = crc16_le ); PROVIDE ( esp_rom_crc8_le = crc8_le ); @@ -40,6 +37,9 @@ PROVIDE ( esp_rom_md5_init = MD5Init ); PROVIDE ( esp_rom_md5_update = MD5Update ); PROVIDE ( esp_rom_md5_final = MD5Final ); +PROVIDE ( esp_rom_software_reset_system = software_reset ); +PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); + PROVIDE ( esp_rom_printf = ets_printf ); PROVIDE ( esp_rom_delay_us = ets_delay_us ); PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason ); diff --git a/components/esp_rom/esp32s2/Kconfig.soc_caps.in b/components/esp_rom/esp32s2/Kconfig.soc_caps.in index aee161608b..2b753e7e0d 100644 --- a/components/esp_rom/esp32s2/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32s2/Kconfig.soc_caps.in @@ -10,3 +10,7 @@ config ESP_ROM_HAS_CRC_LE config ESP_ROM_SUPPORT_MULTIPLE_UART bool default y + +config ESP_ROM_NEEDS_SWSETUP_WORKAROUND + bool + default y diff --git a/components/esp_rom/esp32s2/esp_rom_caps.h b/components/esp_rom/esp32s2/esp_rom_caps.h index 0f63dfb542..1078ff8997 100644 --- a/components/esp_rom/esp32s2/esp_rom_caps.h +++ b/components/esp_rom/esp32s2/esp_rom_caps.h @@ -1,18 +1,11 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once #define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian #define ESP_ROM_SUPPORT_MULTIPLE_UART (1) // ROM has multiple UARTs available for logging +#define ESP_ROM_NEEDS_SWSETUP_WORKAROUND (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing diff --git a/components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld b/components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld index 078a648338..ca3488174c 100644 --- a/components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld +++ b/components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld @@ -34,6 +34,9 @@ PROVIDE ( esp_rom_md5_init = 0x4000526c ); PROVIDE ( esp_rom_md5_update = 0x4000528c ); PROVIDE ( esp_rom_md5_final = 0x4000530c ); +PROVIDE ( esp_rom_software_reset_system = software_reset ); +PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); + PROVIDE ( esp_rom_printf = ets_printf ); PROVIDE ( esp_rom_delay_us = ets_delay_us ); PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf ); diff --git a/components/esp_rom/esp32s3/Kconfig.soc_caps.in b/components/esp_rom/esp32s3/Kconfig.soc_caps.in index b4e07adfd5..7383c90099 100644 --- a/components/esp_rom/esp32s3/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32s3/Kconfig.soc_caps.in @@ -42,3 +42,15 @@ config ESP_ROM_GET_CLK_FREQ config ESP_ROM_HAS_HAL_WDT bool default y + +config ESP_ROM_NEEDS_SWSETUP_WORKAROUND + bool + default y + +config ESP_ROM_HAS_LAYOUT_TABLE + bool + default y + +config ESP_ROM_HAS_SPI_FLASH + bool + default y diff --git a/components/esp_rom/esp32s3/esp_rom_caps.h b/components/esp_rom/esp32s3/esp_rom_caps.h index e5fe2017ff..88d85003a4 100644 --- a/components/esp_rom/esp32s3/esp_rom_caps.h +++ b/components/esp_rom/esp32s3/esp_rom_caps.h @@ -16,3 +16,6 @@ #define ESP_ROM_HAS_ERASE_0_REGION_BUG (1) // ROM has esp_flash_erase_region(size=0) bug #define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency` #define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver +#define ESP_ROM_NEEDS_SWSETUP_WORKAROUND (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing +#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table +#define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld index 72156b74c2..6355190a6c 100644 --- a/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld +++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld @@ -1,12 +1,6 @@ /** * ROM APIs */ - -/* user may provide newer version of tjpgd */ -/* so here directly assign the symbols with the ROM API address to make sure one from rom is correctly linked */ -PROVIDE ( esp_rom_tjpgd_decomp = 0x40000864 ); -PROVIDE ( esp_rom_tjpgd_prepare = 0x40000858 ); - PROVIDE ( esp_rom_crc32_le = crc32_le ); PROVIDE ( esp_rom_crc16_le = crc16_le ); PROVIDE ( esp_rom_crc8_le = crc8_le ); @@ -39,6 +33,9 @@ PROVIDE ( esp_rom_md5_init = MD5Init ); PROVIDE ( esp_rom_md5_update = MD5Update ); PROVIDE ( esp_rom_md5_final = MD5Final ); +PROVIDE ( esp_rom_software_reset_system = software_reset ); +PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); + PROVIDE ( esp_rom_printf = ets_printf ); PROVIDE ( esp_rom_delay_us = ets_delay_us ); PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf ); diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.ld index 20f0464b19..2b01287b07 100644 --- a/components/esp_rom/esp32s3/ld/esp32s3.rom.ld +++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.ld @@ -1804,7 +1804,7 @@ RC_GetBlockAckTime = 0x4000525c; ebuf_list_remove = 0x40005268; esf_buf_alloc = 0x40005274; esf_buf_alloc_dynamic = 0x40005280; -esf_buf_recycle = 0x4000528c; +/*esf_buf_recycle = 0x4000528c;*/ GetAccess = 0x40005298; hal_mac_is_low_rate_enabled = 0x400052a4; hal_mac_tx_get_blockack = 0x400052b0; diff --git a/components/esp_rom/include/esp32/rom/md5_hash.h b/components/esp_rom/include/esp32/rom/md5_hash.h index f116f1e670..6092546033 100644 --- a/components/esp_rom/include/esp32/rom/md5_hash.h +++ b/components/esp_rom/include/esp32/rom/md5_hash.h @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2003-2005, Jouni Malinen + * + * SPDX-License-Identifier: BSD-3-Clause + */ /* * MD5 internal definitions * Copyright (c) 2003-2005, Jouni Malinen diff --git a/components/esp_rom/include/esp32/rom/miniz.h b/components/esp_rom/include/esp32/rom/miniz.h index 7661f80446..5fefa84999 100644 --- a/components/esp_rom/include/esp32/rom/miniz.h +++ b/components/esp_rom/include/esp32/rom/miniz.h @@ -760,7 +760,7 @@ typedef struct // Initializes the compressor. // There is no corresponding deinit() function because the tdefl API's do not dynamically allocate memory. -// pBut_buf_func: If NULL, output data will be supplied to the specified callback. In this case, the user should call the tdefl_compress_buffer() API for compression. +// pBut_buf_func: If **not** NULL, output data will be supplied to the specified callback. In this case, the user should call the tdefl_compress_buffer() API for compression. // If pBut_buf_func is NULL the user should always call the tdefl_compress() API. // flags: See the above enums (TDEFL_HUFFMAN_ONLY, TDEFL_WRITE_ZLIB_HEADER, etc.) tdefl_status tdefl_init(tdefl_compressor *d, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags); diff --git a/components/esp_rom/include/esp32c2/rom/md5_hash.h b/components/esp_rom/include/esp32c2/rom/md5_hash.h index 63ce15857b..3c5e10d1bf 100644 --- a/components/esp_rom/include/esp32c2/rom/md5_hash.h +++ b/components/esp_rom/include/esp32c2/rom/md5_hash.h @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2003-2005, Jouni Malinen + * + * SPDX-License-Identifier: BSD-3-Clause + */ /* * MD5 internal definitions * Copyright (c) 2003-2005, Jouni Malinen diff --git a/components/esp_rom/include/esp32c2/rom/miniz.h b/components/esp_rom/include/esp32c2/rom/miniz.h index ded9570b2b..5671d84e34 100644 --- a/components/esp_rom/include/esp32c2/rom/miniz.h +++ b/components/esp_rom/include/esp32c2/rom/miniz.h @@ -734,7 +734,7 @@ typedef struct { // Initializes the compressor. // There is no corresponding deinit() function because the tdefl API's do not dynamically allocate memory. -// pBut_buf_func: If NULL, output data will be supplied to the specified callback. In this case, the user should call the tdefl_compress_buffer() API for compression. +// pBut_buf_func: If **not** NULL, output data will be supplied to the specified callback. In this case, the user should call the tdefl_compress_buffer() API for compression. // If pBut_buf_func is NULL the user should always call the tdefl_compress() API. // flags: See the above enums (TDEFL_HUFFMAN_ONLY, TDEFL_WRITE_ZLIB_HEADER, etc.) tdefl_status tdefl_init(tdefl_compressor *d, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags); diff --git a/components/esp_rom/include/esp32c2/rom/tlsf.h b/components/esp_rom/include/esp32c2/rom/tlsf.h index 516822190e..347ef5eddd 100644 --- a/components/esp_rom/include/esp32c2/rom/tlsf.h +++ b/components/esp_rom/include/esp32c2/rom/tlsf.h @@ -18,6 +18,15 @@ extern "C" { */ void tlsf_poison_fill_pfunc_set(void *pfunc); +/*! + * @brief Set the function to call for checking memory region when + * poisoning is configured. + * + * @param pfunc The callback function to trigger for checking + * the content of a memory region. + */ +void tlsf_poison_check_pfunc_set(void *pfunc); + #ifdef __cplusplus } #endif diff --git a/components/esp_rom/include/esp32c3/rom/md5_hash.h b/components/esp_rom/include/esp32c3/rom/md5_hash.h index 63ce15857b..3c5e10d1bf 100644 --- a/components/esp_rom/include/esp32c3/rom/md5_hash.h +++ b/components/esp_rom/include/esp32c3/rom/md5_hash.h @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2003-2005, Jouni Malinen + * + * SPDX-License-Identifier: BSD-3-Clause + */ /* * MD5 internal definitions * Copyright (c) 2003-2005, Jouni Malinen diff --git a/components/esp_rom/include/esp32c3/rom/miniz.h b/components/esp_rom/include/esp32c3/rom/miniz.h index 4c8cb7a421..aaef48c14a 100644 --- a/components/esp_rom/include/esp32c3/rom/miniz.h +++ b/components/esp_rom/include/esp32c3/rom/miniz.h @@ -729,7 +729,7 @@ typedef struct { // Initializes the compressor. // There is no corresponding deinit() function because the tdefl API's do not dynamically allocate memory. -// pBut_buf_func: If NULL, output data will be supplied to the specified callback. In this case, the user should call the tdefl_compress_buffer() API for compression. +// pBut_buf_func: If **not** NULL, output data will be supplied to the specified callback. In this case, the user should call the tdefl_compress_buffer() API for compression. // If pBut_buf_func is NULL the user should always call the tdefl_compress() API. // flags: See the above enums (TDEFL_HUFFMAN_ONLY, TDEFL_WRITE_ZLIB_HEADER, etc.) tdefl_status tdefl_init(tdefl_compressor *d, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags); diff --git a/components/esp_rom/include/esp32c6/rom/aes.h b/components/esp_rom/include/esp32c6/rom/aes.h new file mode 100644 index 0000000000..82c263522b --- /dev/null +++ b/components/esp_rom/include/esp32c6/rom/aes.h @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_AES_H_ +#define _ROM_AES_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define AES_BLOCK_SIZE 16 + +enum AES_TYPE { + AES_ENC, + AES_DEC, +}; + +enum AES_BITS { + AES128, + AES192, + AES256 +}; + +void ets_aes_enable(void); + +void ets_aes_disable(void); + +void ets_aes_set_endian(bool key_word_swap, bool key_byte_swap, + bool in_word_swap, bool in_byte_swap, + bool out_word_swap, bool out_byte_swap); + +int ets_aes_setkey(enum AES_TYPE type, const void *key, enum AES_BITS bits); + +int ets_aes_setkey_enc(const void *key, enum AES_BITS bits); + +int ets_aes_setkey_dec(const void *key, enum AES_BITS bits); + +void ets_aes_block(const void *input, void *output); + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_AES_H_ */ diff --git a/components/esp_rom/include/esp32c6/rom/apb_backup_dma.h b/components/esp_rom/include/esp32c6/rom/apb_backup_dma.h new file mode 100644 index 0000000000..08c98eff64 --- /dev/null +++ b/components/esp_rom/include/esp32c6/rom/apb_backup_dma.h @@ -0,0 +1,17 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +void ets_apb_backup_init_lock_func(void(* _apb_backup_lock)(void), void(* _apb_backup_unlock)(void)); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/include/esp32c6/rom/bigint.h b/components/esp_rom/include/esp32c6/rom/bigint.h new file mode 100644 index 0000000000..ef82674b33 --- /dev/null +++ b/components/esp_rom/include/esp32c6/rom/bigint.h @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_BIGINT_H_ +#define _ROM_BIGINT_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +void ets_bigint_enable(void); + +void ets_bigint_disable(void); + +int ets_bigint_multiply(const uint32_t *x, const uint32_t *y, uint32_t len_words); + +int ets_bigint_modmult(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, uint32_t len_words); + +int ets_bigint_modexp(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, bool constant_time, uint32_t len_words); + +void ets_bigint_wait_finish(void); + +int ets_bigint_getz(uint32_t *z, uint32_t len_words); + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_BIGINT_H_ */ diff --git a/components/esp_rom/include/esp32c6/rom/cache.h b/components/esp_rom/include/esp32c6/rom/cache.h new file mode 100644 index 0000000000..8f030f207a --- /dev/null +++ b/components/esp_rom/include/esp32c6/rom/cache.h @@ -0,0 +1,630 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "esp_bit_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup cache_apis, cache operation related apis + * @brief cache apis + */ + +/** @addtogroup cache_apis + * @{ + */ +#define MIN_ICACHE_SIZE 16384 +#define MAX_ICACHE_SIZE 16384 +#define MIN_ICACHE_WAYS 8 +#define MAX_ICACHE_WAYS 8 +#define MAX_CACHE_WAYS 8 +#define MIN_CACHE_LINE_SIZE 32 +#define TAG_SIZE 4 +#define MIN_ICACHE_BANK_NUM 1 +#define MAX_ICACHE_BANK_NUM 1 +#define CACHE_MEMORY_BANK_NUM 1 +#define CACHE_MEMORY_IBANK_SIZE 0x4000 + +#define MAX_ITAG_BANK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MIN_CACHE_LINE_SIZE) +#define MAX_ITAG_BLOCK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MAX_ICACHE_WAYS / MIN_CACHE_LINE_SIZE) +#define MAX_ITAG_BANK_SIZE (MAX_ITAG_BANK_ITEMS * TAG_SIZE) +#define MAX_ITAG_BLOCK_SIZE (MAX_ITAG_BLOCK_ITEMS * TAG_SIZE) + +typedef enum { + CACHE_SIZE_HALF = 0, /*!< 8KB for icache and dcache */ + CACHE_SIZE_FULL = 1, /*!< 16KB for icache and dcache */ +} cache_size_t; + +typedef enum { + CACHE_4WAYS_ASSOC = 0, /*!< 4 way associated cache */ + CACHE_8WAYS_ASSOC = 1, /*!< 8 way associated cache */ +} cache_ways_t; + +typedef enum { + CACHE_LINE_SIZE_16B = 0, /*!< 16 Byte cache line size */ + CACHE_LINE_SIZE_32B = 1, /*!< 32 Byte cache line size */ + CACHE_LINE_SIZE_64B = 2, /*!< 64 Byte cache line size */ +} cache_line_size_t; + +typedef enum { + CACHE_AUTOLOAD_POSITIVE = 0, /*!< cache autoload step is positive */ + CACHE_AUTOLOAD_NEGATIVE = 1, /*!< cache autoload step is negative */ +} cache_autoload_order_t; + +#define CACHE_AUTOLOAD_STEP(i) ((i) - 1) + +typedef enum { + CACHE_AUTOLOAD_MISS_TRIGGER = 0, /*!< autoload only triggered by cache miss */ + CACHE_AUTOLOAD_HIT_TRIGGER = 1, /*!< autoload only triggered by cache hit */ + CACHE_AUTOLOAD_BOTH_TRIGGER = 2, /*!< autoload triggered both by cache miss and hit */ +} cache_autoload_trigger_t; + +typedef enum { + CACHE_FREEZE_ACK_BUSY = 0, /*!< in this mode, cache ack busy to CPU if a cache miss happens*/ + CACHE_FREEZE_ACK_ERROR = 1, /*!< in this mode, cache ack wrong data to CPU and trigger an error if a cache miss happens */ +} cache_freeze_mode_t; + +typedef enum { + MMU_PAGE_MODE_64KB = 0, + MMU_PAGE_MODE_32KB = 1, + MMU_PAGE_MODE_16KB = 2, + MMU_PAGE_MODE_8KB = 3, + MMU_PAGE_MODE_INVALID, +} mmu_page_mode_t; + +struct cache_mode { + uint32_t cache_size; /*!< cache size in byte */ + uint16_t cache_line_size; /*!< cache line size in byte */ + uint8_t cache_ways; /*!< cache ways, always 4 */ + uint8_t ibus; /*!< the cache index, 0 for dcache, 1 for icache */ +}; + +struct icache_tag_item { + uint32_t valid:1; /*!< the tag item is valid or not */ + uint32_t lock:1; /*!< the cache line is locked or not */ + uint32_t fifo_cnt:3; /*!< fifo cnt, 0 ~ 3 for 4 ways cache */ + uint32_t tag:13; /*!< the tag is the high part of the cache address, however is only 16MB (8MB Ibus + 8MB Dbus) range, and without low part */ + uint32_t reserved:14; +}; + +struct autoload_config { + uint8_t order; /*!< autoload step is positive or negative */ + uint8_t trigger; /*!< autoload trigger */ + uint8_t ena0; /*!< autoload region0 enable */ + uint8_t ena1; /*!< autoload region1 enable */ + uint32_t addr0; /*!< autoload region0 start address */ + uint32_t size0; /*!< autoload region0 size */ + uint32_t addr1; /*!< autoload region1 start address */ + uint32_t size1; /*!< autoload region1 size */ +}; + +struct tag_group_info { + struct cache_mode mode; /*!< cache and cache mode */ + uint32_t filter_addr; /*!< the address that used to generate the struct */ + uint32_t vaddr_offset; /*!< virtual address offset of the cache ways */ + uint32_t tag_addr[MAX_CACHE_WAYS]; /*!< tag memory address, only [0~mode.ways-1] is valid to use */ + uint32_t cache_memory_offset[MAX_CACHE_WAYS]; /*!< cache memory address, only [0~mode.ways-1] is valid to use */ +}; + +struct lock_config { + uint32_t addr; /*!< manual lock address*/ + uint16_t size; /*!< manual lock size*/ + uint16_t group; /*!< manual lock group, 0 or 1*/ +}; + +struct cache_internal_stub_table { + uint32_t (* icache_line_size)(void); + uint32_t (* icache_addr)(uint32_t addr); + uint32_t (* dcache_addr)(uint32_t addr); + void (* invalidate_icache_items)(uint32_t addr, uint32_t items); + void (* lock_icache_items)(uint32_t addr, uint32_t items); + void (* unlock_icache_items)(uint32_t addr, uint32_t items); + uint32_t (* suspend_icache_autoload)(void); + void (* resume_icache_autoload)(uint32_t autoload); + void (* freeze_icache_enable)(cache_freeze_mode_t mode); + void (* freeze_icache_disable)(void); + int (* op_addr)(uint32_t start_addr, uint32_t size, uint32_t cache_line_size, uint32_t max_sync_num, void(* cache_Iop)(uint32_t, uint32_t)); +}; + +/* Defined in the interface file, default value is rom_default_cache_internal_table */ +extern const struct cache_internal_stub_table* rom_cache_internal_table_ptr; + +typedef void (* cache_op_start)(void); +typedef void (* cache_op_end)(void); + +typedef struct { + cache_op_start start; + cache_op_end end; +} cache_op_cb_t; + +/* Defined in the interface file, default value is NULL */ +extern const cache_op_cb_t* rom_cache_op_cb; + +#define ESP_ROM_ERR_INVALID_ARG 1 +#define MMU_SET_ADDR_ALIGNED_ERROR 2 +#define MMU_SET_PASE_SIZE_ERROR 3 +#define MMU_SET_VADDR_OUT_RANGE 4 + +#define CACHE_OP_ICACHE_Y 1 +#define CACHE_OP_ICACHE_N 0 + +/** + * @brief Initialise cache mmu, mark all entries as invalid. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_MMU_Init(void); + +/** + * @brief Set ICache mmu mapping. + * Please do not call this function in your SDK application. + * + * @param uint32_t senitive : Config this page should apply flash encryption or not + * + * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In + * esp32c6, external memory is always flash + * + * @param uint32_t vaddr : virtual address in CPU address space. + * Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address. + * Should be aligned by psize. + * + * @param uint32_t paddr : physical address in external memory. + * Should be aligned by psize. + * + * @param uint32_t psize : page size of ICache, in kilobytes. Should be 64 here. + * + * @param uint32_t num : pages to be set. + * + * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. + * + * @return uint32_t: error status + * 0 : mmu set success + * 2 : vaddr or paddr is not aligned + * 3 : psize error + * 4 : vaddr is out of range + */ +int Cache_MSPI_MMU_Set(uint32_t sensitive, uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); + +/** + * @brief Set DCache mmu mapping. + * Please do not call this function in your SDK application. + * + * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In + * esp32c6, external memory is always flash + * + * @param uint32_t vaddr : virtual address in CPU address space. + * Can be DRam0, DRam1, DRom0, DPort and AHB buses address. + * Should be aligned by psize. + * + * @param uint32_t paddr : physical address in external memory. + * Should be aligned by psize. + * + * @param uint32_t psize : page size of DCache, in kilobytes. Should be 64 here. + * + * @param uint32_t num : pages to be set. + + * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. + * + * @return uint32_t: error status + * 0 : mmu set success + * 2 : vaddr or paddr is not aligned + * 3 : psize error + * 4 : vaddr is out of range + */ +int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); + +/** + * @brief Count the pages in the bus room address which map to Flash. + * Please do not call this function in your SDK application. + * + * @param uint32_t bus : the bus to count with. + * + * @param uint32_t * page0_mapped : value should be initial by user, 0 for not mapped, other for mapped count. + * + * return uint32_t : the number of pages which map to Flash. + */ +uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped); + +/** + * @brief Get cache mode of ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the pointer of cache mode struct, caller should set the icache field + * + * return none + */ +void Cache_Get_Mode(struct cache_mode * mode); + +/** + * @brief check if the address is accessed through ICache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : the address to check. + * + * @return 1 if the address is accessed through ICache, 0 if not. + */ +uint32_t Cache_Address_Through_ICache(uint32_t addr); + +/** + * @brief check if the address is accessed through DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : the address to check. + * + * @return 1 if the address is accessed through DCache, 0 if not. + */ +uint32_t Cache_Address_Through_DCache(uint32_t addr); + +/** + * @brief Set cache page mode. + * + * @param mmu_page_mode_t + * + * @return None + */ +void MMU_Set_Page_Mode(mmu_page_mode_t pg_mode); + +/** + * @brief Get cache page mode. + * + * @param None + * + * @return page mode + */ +mmu_page_mode_t MMU_Get_Page_Mode(void); + +/** + * @brief Invalidate the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to invalidate + * + * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Invalidate_ICache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Invalidate the Cache items in the region from ICache or DCache. + * If the region is not in Cache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : invalidated region start address. + * + * @param uint32_t size : invalidated region size. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Invalidate_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Invalidate all cache items in ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Invalidate_ICache_All(void); + +/** + * @brief Mask all buses through ICache and DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Mask_All(void); + +/** + * @brief Suspend ICache auto preload operation, then you can resume it after some ICache operations. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : 0 for ICache not auto preload before suspend. + */ +uint32_t Cache_Suspend_ICache_Autoload(void); + +/** + * @brief Resume ICache auto preload operation after some ICache operations. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : 0 for ICache not auto preload before suspend. + * + * @return None. + */ +void Cache_Resume_ICache_Autoload(uint32_t autoload); + +/** + * @brief Start an ICache manual preload, will suspend auto preload of ICache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of the preload region. + * + * @param uint32_t size : size of the preload region, should not exceed the size of ICache. + * + * @param uint32_t order : the preload order, 0 for positive, other for negative + * + * @return uint32_t : 0 for ICache not auto preload before manual preload. + */ +uint32_t Cache_Start_ICache_Preload(uint32_t addr, uint32_t size, uint32_t order); + +/** + * @brief Return if the ICache manual preload done. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : 0 for ICache manual preload not done. + */ +uint32_t Cache_ICache_Preload_Done(void); + +/** + * @brief End the ICache manual preload to resume auto preload of ICache. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : 0 for ICache not auto preload before manual preload. + * + * @return None + */ +void Cache_End_ICache_Preload(uint32_t autoload); + +/** + * @brief Config autoload parameters of ICache. + * Please do not call this function in your SDK application. + * + * @param struct autoload_config * config : autoload parameters. + * + * @return None + */ +void Cache_Config_ICache_Autoload(const struct autoload_config * config); + +/** + * @brief Enable auto preload for ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Enable_ICache_Autoload(void); + +/** + * @brief Disable auto preload for ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Disable_ICache_Autoload(void); + +/** + * @brief Config a group of prelock parameters of ICache. + * Please do not call this function in your SDK application. + * + * @param struct lock_config * config : a group of lock parameters. + * + * @return None + */ + +void Cache_Enable_ICache_PreLock(const struct lock_config *config); + +/** + * @brief Disable a group of prelock parameters for ICache. + * However, the locked data will not be released. + * Please do not call this function in your SDK application. + * + * @param uint16_t group : 0 for group0, 1 for group1. + * + * @return None + */ +void Cache_Disable_ICache_PreLock(uint16_t group); + +/** + * @brief Lock the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to lock + * + * @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Lock_ICache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Unlock the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to unlock + * + * @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Unlock_ICache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Lock the cache items in tag memory for ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of lock region. + * + * @param uint32_t size : size of lock region. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Lock_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Unlock the cache items in tag memory for ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of unlock region. + * + * @param uint32_t size : size of unlock region. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Unlock_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Disable ICache access for the cpu. + * This operation will make all ICache tag memory invalid, CPU can't access ICache, ICache will keep idle. + * Please do not call this function in your SDK application. + * + * @return uint32_t : auto preload enabled before + */ +uint32_t Cache_Disable_ICache(void); + +/** + * @brief Enable ICache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : ICache will preload then. + * + * @return None + */ +void Cache_Enable_ICache(uint32_t autoload); + +/** + * @brief Suspend ICache access for the cpu. + * The ICache tag memory is still there, CPU can't access ICache, ICache will keep idle. + * Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case). + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : auto preload enabled before + */ +uint32_t Cache_Suspend_ICache(void); + +/** + * @brief Resume ICache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : ICache will preload then. + * + * @return None + */ +void Cache_Resume_ICache(uint32_t autoload); + +/** + * @brief Get ICache cache line size + * + * @param None + * + * @return uint32_t: 16, 32, 64 Byte + */ +uint32_t Cache_Get_ICache_Line_Size(void); + +/** + * @brief Enable freeze for ICache. + * Any miss request will be rejected, including cpu miss and preload/autoload miss. + * Please do not call this function in your SDK application. + * + * @param cache_freeze_mode_t mode : 0 for assert busy 1 for assert hit + * + * @return None + */ +void Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode); + +/** + * @brief Disable freeze for ICache. + * Please do not call this function in your SDK application. + * + * @return None + */ +void Cache_Freeze_ICache_Disable(void); + +/** + * @brief Travel tag memory to run a call back function. + * ICache and DCache are suspend when doing this. + * The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the cache to check and the cache mode. + * + * @param uint32_t filter_addr : only the cache lines which may include the filter_address will be returned to the call back function. + * 0 for do not filter, all cache lines will be returned. + * + * @param void (* process)(struct tag_group_info *) : call back function, which may be called many times, a group(the addresses in the group are in the same position in the cache ways) a time. + * + * @return None + */ +void Cache_Travel_Tag_Memory(struct cache_mode * mode, uint32_t filter_addr, void (* process)(struct tag_group_info *)); + +/** + * @brief Get the virtual address from cache mode, cache tag and the virtual address offset of cache ways. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode. + * + * @param uint32_t tag : the tag part fo a tag item, 12-14 bits. + * + * @param uint32_t addr_offset : the virtual address offset of the cache ways. + * + * @return uint32_t : the virtual address. + */ +uint32_t Cache_Get_Virtual_Addr(struct cache_mode *mode, uint32_t tag, uint32_t vaddr_offset); + +/** + * @} + */ + +/** + * @brief Get the cache MMU IROM end address. + * Please do not call this function in your SDK application. + * + * @param void + * + * @return uint32_t : the word value of the address. + */ +uint32_t Cache_Get_IROM_MMU_End(void); + +/** + * @brief Get the cache MMU DROM end address. + * Please do not call this function in your SDK application. + * + * @param void + * + * @return uint32_t : the word value of the address. + */ +uint32_t Cache_Get_DROM_MMU_End(void); + +/** + * @brief Used by SPI flash mmap + * + */ +uint32_t flash_instr_rodata_start_page(uint32_t bus); +uint32_t flash_instr_rodata_end_page(uint32_t bus); + +#define Cache_Dbus_MMU_Set(ext_ram, vaddr, paddr, psize, num, fixed) \ + Cache_MSPI_MMU_Set(ets_efuse_cache_encryption_enabled() ? MMU_SENSITIVE : 0, ext_ram, vaddr, paddr, psize, num, fixed) + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/include/esp32c6/rom/crc.h b/components/esp_rom/include/esp32c6/rom/crc.h new file mode 100644 index 0000000000..de7002f7a5 --- /dev/null +++ b/components/esp_rom/include/esp32c6/rom/crc.h @@ -0,0 +1,119 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ROM_CRC_H +#define ROM_CRC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup crc_apis, uart configuration and communication related apis + * @brief crc apis + */ + +/** @addtogroup crc_apis + * @{ + */ + + +/* Standard CRC8/16/32 algorithms. */ +// CRC-8 x8+x2+x1+1 0x07 +// CRC16-CCITT x16+x12+x5+1 1021 ISO HDLC, ITU X.25, V.34/V.41/V.42, PPP-FCS +// CRC32: +//G(x) = x32 +x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1 +//If your buf is not continuous, you can use the first result to be the second parameter. + +/** + * @brief Crc32 value that is in little endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint32_t crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc32 value that is in big endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint32_t crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc16 value that is in little endian. + * + * @param uint16_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint16_t crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc16 value that is in big endian. + * + * @param uint16_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint16_t crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc8 value that is in little endian. + * + * @param uint8_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint8_t crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc8 value that is in big endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint8_t crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif diff --git a/components/esp_rom/include/esp32c6/rom/digital_signature.h b/components/esp_rom/include/esp32c6/rom/digital_signature.h new file mode 100644 index 0000000000..e2f62bb15e --- /dev/null +++ b/components/esp_rom/include/esp32c6/rom/digital_signature.h @@ -0,0 +1,142 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#define ETS_DS_MAX_BITS 3072 + +#define ETS_DS_IV_LEN 16 + +/* Length of parameter 'C' stored in flash (not including IV) + + Comprises encrypted Y, M, rinv, md (32), mprime (4), length (4), padding (8) + + Note that if ETS_DS_MAX_BITS<4096, 'C' needs to be split up when writing to hardware +*/ +#define ETS_DS_C_LEN ((ETS_DS_MAX_BITS * 3 / 8) + 32 + 8 + 8) + +/* Encrypted ETS data. Recommended to store in flash in this format. + */ +typedef struct { + /* RSA LENGTH register parameters + * (number of words in RSA key & operands, minus one). + * + * + * This value must match the length field encrypted and stored in 'c', + * or invalid results will be returned. (The DS peripheral will + * always use the value in 'c', not this value, so an attacker can't + * alter the DS peripheral results this way, it will just truncate or + * extend the message and the resulting signature in software.) + */ + unsigned rsa_length; + + /* IV value used to encrypt 'c' */ + uint8_t iv[ETS_DS_IV_LEN]; + + /* Encrypted Digital Signature parameters. Result of AES-CBC encryption + of plaintext values. Includes an encrypted message digest. + */ + uint8_t c[ETS_DS_C_LEN]; +} ets_ds_data_t; + +typedef enum { + ETS_DS_OK, + ETS_DS_INVALID_PARAM, /* Supplied parameters are invalid */ + ETS_DS_INVALID_KEY, /* HMAC peripheral failed to supply key */ + ETS_DS_INVALID_PADDING, /* 'c' decrypted with invalid padding */ + ETS_DS_INVALID_DIGEST, /* 'c' decrypted with invalid digest */ +} ets_ds_result_t; + +void ets_ds_enable(void); + +void ets_ds_disable(void); + + +/* + * @brief Start signing a message (or padded message digest) using the Digital Signature peripheral + * + * - @param message Pointer to message (or padded digest) containing the message to sign. Should be + * (data->rsa_length + 1)*4 bytes long. @param data Pointer to DS data. Can be a pointer to data + * in flash. + * + * Caller must have already called ets_ds_enable() and ets_hmac_calculate_downstream() before calling + * this function, and is responsible for calling ets_ds_finish_sign() and then + * ets_hmac_invalidate_downstream() afterwards. + * + * @return ETS_DS_OK if signature is in progress, ETS_DS_INVALID_PARAM if param is invalid, + * EST_DS_INVALID_KEY if key or HMAC peripheral is configured incorrectly. + */ +ets_ds_result_t ets_ds_start_sign(const void *message, const ets_ds_data_t *data); + + +/* + * @brief Returns true if the DS peripheral is busy following a call to ets_ds_start_sign() + * + * A result of false indicates that a call to ets_ds_finish_sign() will not block. + * + * Only valid if ets_ds_enable() has been called. + */ +bool ets_ds_is_busy(void); + + +/* @brief Finish signing a message using the Digital Signature peripheral + * + * Must be called after ets_ds_start_sign(). Can use ets_ds_busy() to wait until + * peripheral is no longer busy. + * + * - @param signature Pointer to buffer to contain the signature. Should be + * (data->rsa_length + 1)*4 bytes long. + * - @param data Should match the 'data' parameter passed to ets_ds_start_sign() + * + * @param ETS_DS_OK if signing succeeded, ETS_DS_INVALID_PARAM if param is invalid, + * ETS_DS_INVALID_DIGEST or ETS_DS_INVALID_PADDING if there is a problem with the + * encrypted data digest or padding bytes (in case of ETS_DS_INVALID_PADDING, a + * digest is produced anyhow.) + */ +ets_ds_result_t ets_ds_finish_sign(void *signature, const ets_ds_data_t *data); + + +/* Plaintext parameters used by Digital Signature. + + Not used for signing with DS peripheral, but can be encrypted + in-device by calling ets_ds_encrypt_params() +*/ +typedef struct { + uint32_t Y[ETS_DS_MAX_BITS / 32]; + uint32_t M[ETS_DS_MAX_BITS / 32]; + uint32_t Rb[ETS_DS_MAX_BITS / 32]; + uint32_t M_prime; + uint32_t length; +} ets_ds_p_data_t; + +typedef enum { + ETS_DS_KEY_HMAC, /* The HMAC key (as stored in efuse) */ + ETS_DS_KEY_AES, /* The AES key (as derived from HMAC key by HMAC peripheral in downstream mode) */ +} ets_ds_key_t; + +/* @brief Encrypt DS parameters suitable for storing and later use with DS peripheral + * + * @param data Output buffer to store encrypted data, suitable for later use generating signatures. + * @param iv Pointer to 16 byte IV buffer, will be copied into 'data'. Should be randomly generated bytes each time. + * @param p_data Pointer to input plaintext key data. The expectation is this data will be deleted after this process is done and 'data' is stored. + * @param key Pointer to 32 bytes of key data. Type determined by key_type parameter. The expectation is the corresponding HMAC key will be stored to efuse and then permanently erased. + * @param key_type Type of key stored in 'key' (either the AES-256 DS key, or an HMAC DS key from which the AES DS key is derived using HMAC peripheral) + * + * @return ETS_DS_INVALID_PARAM if any parameter is invalid, or ETS_DS_OK if 'data' is successfully generated from the input parameters. + */ +ets_ds_result_t ets_ds_encrypt_params(ets_ds_data_t *data, const void *iv, const ets_ds_p_data_t *p_data, const void *key, ets_ds_key_t key_type); + + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/include/esp32c6/rom/efuse.h b/components/esp_rom/include/esp32c6/rom/efuse.h new file mode 100644 index 0000000000..a095f45568 --- /dev/null +++ b/components/esp_rom/include/esp32c6/rom/efuse.h @@ -0,0 +1,384 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_EFUSE_H_ +#define _ROM_EFUSE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** \defgroup efuse_APIs efuse APIs + * @brief ESP32 efuse read/write APIs + * @attention + * + */ + +/** @addtogroup efuse_APIs + * @{ + */ + +typedef enum { + ETS_EFUSE_KEY_PURPOSE_USER = 0, + ETS_EFUSE_KEY_PURPOSE_RESERVED = 1, + ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, + ETS_EFUSE_KEY_PURPOSE_HMAC_UP = 8, + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, + ETS_EFUSE_KEY_PURPOSE_MAX, +} ets_efuse_purpose_t; + +typedef enum { + ETS_EFUSE_BLOCK0 = 0, + ETS_EFUSE_MAC_SPI_SYS_0 = 1, + ETS_EFUSE_BLOCK_SYS_DATA = 2, + ETS_EFUSE_BLOCK_USR_DATA = 3, + ETS_EFUSE_BLOCK_KEY0 = 4, + ETS_EFUSE_BLOCK_KEY1 = 5, + ETS_EFUSE_BLOCK_KEY2 = 6, + ETS_EFUSE_BLOCK_KEY3 = 7, + ETS_EFUSE_BLOCK_KEY4 = 8, + ETS_EFUSE_BLOCK_KEY5 = 9, + ETS_EFUSE_BLOCK_KEY6 = 10, + ETS_EFUSE_BLOCK_MAX, +} ets_efuse_block_t; + +/** + * @brief set timing accroding the apb clock, so no read error or write error happens. + * + * @param clock: apb clock in HZ, only accept 5M(in FPGA), 10M(in FPGA), 20M, 40M, 80M. + * + * @return : 0 if success, others if clock not accepted + */ +int ets_efuse_set_timing(uint32_t clock); + +/** + * @brief Enable efuse subsystem. Called after reset. Doesn't need to be called again. + */ +void ets_efuse_start(void); + +/** + * @brief Efuse read operation: copies data from physical efuses to efuse read registers. + * + * @param null + * + * @return : 0 if success, others if apb clock is not accepted + */ +int ets_efuse_read(void); + +/** + * @brief Efuse write operation: Copies data from efuse write registers to efuse. Operates on a single block of efuses at a time. + * + * @note This function does not update read efuses, call ets_efuse_read() once all programming is complete. + * + * @return : 0 if success, others if apb clock is not accepted + */ +int ets_efuse_program(ets_efuse_block_t block); + +/** + * @brief Set all Efuse program registers to zero. + * + * Call this before writing new data to the program registers. + */ +void ets_efuse_clear_program_registers(void); + +/** + * @brief Program a block of key data to an efuse block + * + * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. Key block must be unused (@ref ets_efuse_key_block_unused). + * @param purpose Purpose to set for this key. Purpose must be already unset. + * @param data Pointer to data to write. + * @param data_len Length of data to write. + * + * @note This function also calls ets_efuse_program() for the specified block, and for block 0 (setting the purpose) + */ +int ets_efuse_write_key(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose, const void *data, size_t data_len); + + +/* @brief Return the address of a particular efuse block's first read register + * + * @param block Index of efuse block to look up + * + * @return 0 if block is invalid, otherwise a numeric read register address + * of the first word in the block. + */ +uint32_t ets_efuse_get_read_register_address(ets_efuse_block_t block); + +/** + * @brief Return the current purpose set for an efuse key block + * + * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. + */ +ets_efuse_purpose_t ets_efuse_get_key_purpose(ets_efuse_block_t key_block); + +/** + * @brief Find a key block with the particular purpose set + * + * @param purpose Purpose to search for. + * @param[out] key_block Pointer which will be set to the key block if found. Can be NULL, if only need to test the key block exists. + * @return true if found, false if not found. If false, value at key_block pointer is unchanged. + */ +bool ets_efuse_find_purpose(ets_efuse_purpose_t purpose, ets_efuse_block_t *key_block); + +/** + * Return true if the key block is unused, false otherwise. + * + * An unused key block is all zero content, not read or write protected, + * and has purpose 0 (ETS_EFUSE_KEY_PURPOSE_USER) + * + * @param key_block key block to check. + * + * @return true if key block is unused, false if key block or used + * or the specified block index is not a key block. + */ +bool ets_efuse_key_block_unused(ets_efuse_block_t key_block); + + +/** + * @brief Search for an unused key block and return the first one found. + * + * See @ref ets_efuse_key_block_unused for a description of an unused key block. + * + * @return First unused key block, or ETS_EFUSE_BLOCK_MAX if no unused key block is found. + */ +ets_efuse_block_t ets_efuse_find_unused_key_block(void); + +/** + * @brief Return the number of unused efuse key blocks (0-6) + */ +unsigned ets_efuse_count_unused_key_blocks(void); + +/** + * @brief Calculate Reed-Solomon Encoding values for a block of efuse data. + * + * @param data Pointer to data buffer (length 32 bytes) + * @param rs_values Pointer to write encoded data to (length 12 bytes) + */ +void ets_efuse_rs_calculate(const void *data, void *rs_values); + +/** + * @brief Read spi flash pads configuration from Efuse + * + * @return + * - 0 for default SPI pins. + * - 1 for default HSPI pins. + * - Other values define a custom pin configuration mask. Pins are encoded as per the EFUSE_SPICONFIG_RET_SPICLK, + * EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros. + * WP pin (for quad I/O modes) is not saved in efuse and not returned by this function. + */ +uint32_t ets_efuse_get_spiconfig(void); + +/** + * @brief Read spi flash wp pad from Efuse + * + * @return + * - 0x3f for invalid. + * - 0~46 is valid. + */ +uint32_t ets_efuse_get_wp_pad(void); + +/** + * @brief Read opi flash pads configuration from Efuse + * + * @return + * - 0 for default SPI pins. + * - Other values define a custom pin configuration mask. From the LSB, every 6 bits represent a GPIO number which stand for: + * DQS, D4, D5, D6, D7 accordingly. + */ +uint32_t ets_efuse_get_opiconfig(void); + +/** + * @brief Read if download mode disabled from Efuse + * + * @return + * - true for efuse disable download mode. + * - false for efuse doesn't disable download mode. + */ +bool ets_efuse_download_modes_disabled(void); + +/** + * @brief Read if legacy spi flash boot mode disabled from Efuse + * + * @return + * - true for efuse disable legacy spi flash boot mode. + * - false for efuse doesn't disable legacy spi flash boot mode. + */ +bool ets_efuse_legacy_spi_boot_mode_disabled(void); + +/** + * @brief Read if uart print control value from Efuse + * + * @return + * - 0 for uart force print. + * - 1 for uart print when GPIO8 is low when digital reset. + * 2 for uart print when GPIO8 is high when digital reset. + * 3 for uart force slient + */ +uint32_t ets_efuse_get_uart_print_control(void); + +/** + * @brief Read if USB-Serial-JTAG print during rom boot is disabled from Efuse + * + * @return + * - 1 for efuse disable USB-Serial-JTAG print during rom boot. + * - 0 for efuse doesn't disable USB-Serial-JTAG print during rom boot. + */ +uint32_t ets_efuse_usb_serial_jtag_print_is_disabled(void); + +/** + * @brief Read if usb download mode disabled from Efuse + * + * (Also returns true if security download mode is enabled, as this mode + * disables USB download.) + * + * @return + * - true for efuse disable usb download mode. + * - false for efuse doesn't disable usb download mode. + */ +bool ets_efuse_usb_download_mode_disabled(void); + +/** + * @brief Read if tiny basic mode disabled from Efuse + * + * @return + * - true for efuse disable tiny basic mode. + * - false for efuse doesn't disable tiny basic mode. + */ +bool ets_efuse_tiny_basic_mode_disabled(void); + +/** + * @brief Read if usb module disabled from Efuse + * + * @return + * - true for efuse disable usb module. + * - false for efuse doesn't disable usb module. + */ +bool ets_efuse_usb_module_disabled(void); + +/** + * @brief Read if security download modes enabled from Efuse + * + * @return + * - true for efuse enable security download mode. + * - false for efuse doesn't enable security download mode. + */ +bool ets_efuse_security_download_modes_enabled(void); + +/** + * @brief Return true if secure boot is enabled in EFuse + */ +bool ets_efuse_secure_boot_enabled(void); + +/** + * @brief Return true if secure boot aggressive revoke is enabled in EFuse + */ +bool ets_efuse_secure_boot_aggressive_revoke_enabled(void); + +/** + * @brief Return true if cache encryption (flash, etc) is enabled from boot via EFuse + */ +bool ets_efuse_cache_encryption_enabled(void); + +/** + * @brief Return true if EFuse indicates an external phy needs to be used for USB + */ +bool ets_efuse_usb_use_ext_phy(void); + +/** + * @brief Return true if EFuse indicates USB device persistence is disabled + */ +bool ets_efuse_usb_force_nopersist(void); + +/** + * @brief Return true if OPI pins GPIO33-37 are powered by VDDSPI, otherwise by VDD33CPU + */ +bool ets_efuse_flash_opi_5pads_power_sel_vddspi(void); + +/** + * @brief Return true if EFuse indicates an opi flash is attached. + */ +bool ets_efuse_flash_opi_mode(void); + +/** + * @brief Return true if EFuse indicates to send a flash resume command. + */ +bool ets_efuse_force_send_resume(void); + +/** + * @brief return the time in us ROM boot need wait flash to power on from Efuse + * + * @return + * - uint32_t the time in us. + */ +uint32_t ets_efuse_get_flash_delay_us(void); + +#define EFUSE_SPICONFIG_SPI_DEFAULTS 0 +#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1 + +#define EFUSE_SPICONFIG_RET_SPICLK_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT 0 +#define EFUSE_SPICONFIG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK) + +#define EFUSE_SPICONFIG_RET_SPIQ_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT 6 +#define EFUSE_SPICONFIG_RET_SPIQ(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK) + +#define EFUSE_SPICONFIG_RET_SPID_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPID_SHIFT 12 +#define EFUSE_SPICONFIG_RET_SPID(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK) + +#define EFUSE_SPICONFIG_RET_SPICS0_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT 18 +#define EFUSE_SPICONFIG_RET_SPICS0(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK) + + +#define EFUSE_SPICONFIG_RET_SPIHD_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24 +#define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK) + +/** + * @brief Enable JTAG temporarily by writing a JTAG HMAC "key" into + * the JTAG_CTRL registers. + * + * Works if JTAG has been "soft" disabled by burning the EFUSE_SOFT_DIS_JTAG efuse. + * + * Will enable the HMAC module to generate a "downstream" HMAC value from a key already saved in efuse, and then write the JTAG HMAC "key" which will enable JTAG if the two keys match. + * + * @param jtag_hmac_key Pointer to a 32 byte array containing a valid key. Supplied by user. + * @param key_block Index of a key block containing the source for this key. + * + * @return ETS_FAILED if HMAC operation fails or invalid parameter, ETS_OK otherwise. ETS_OK doesn't necessarily mean that JTAG was enabled. + */ +int ets_jtag_enable_temporarily(const uint8_t *jtag_hmac_key, ets_efuse_block_t key_block); + +/** + * @brief A crc8 algorithm used for MAC addresses in efuse + * + * @param unsigned char const *p : Pointer to original data. + * + * @param unsigned int len : Data length in byte. + * + * @return unsigned char: Crc value. + */ +unsigned char esp_crc8(unsigned char const *p, unsigned int len); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_EFUSE_H_ */ diff --git a/components/esp_rom/include/esp32c6/rom/esp_flash.h b/components/esp_rom/include/esp32c6/rom/esp_flash.h new file mode 100644 index 0000000000..d975036fc2 --- /dev/null +++ b/components/esp_rom/include/esp32c6/rom/esp_flash.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Note: Most of esp_flash APIs in ROM are compatible with headers in ESP-IDF, this function + just adds ROM-specific parts +*/ + +struct spi_flash_chip_t; +typedef struct esp_flash_t esp_flash_t; + +/* Structure to wrap "global" data used by esp_flash in ROM */ +typedef struct { + /* Default SPI flash chip, ie main chip attached to the MCU + This chip is used if the 'chip' argument passed to esp_flash_xxx API functions is ever NULL + */ + esp_flash_t *default_chip; + + /* Global API OS notification start/end/chip_check functions + + These are used by ROM if no other host functions are configured. + */ + struct { + esp_err_t (*start)(esp_flash_t *chip); + esp_err_t (*end)(esp_flash_t *chip, esp_err_t err); + esp_err_t (*chip_check)(esp_flash_t **inout_chip); + } api_funcs; +} esp_flash_rom_global_data_t; + +/** Access a pointer to the global data used by the ROM spi_flash driver + */ +esp_flash_rom_global_data_t *esp_flash_get_rom_global_data(void); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/include/esp32c6/rom/ets_sys.h b/components/esp_rom/include/esp32c6/rom/ets_sys.h new file mode 100644 index 0000000000..afd3467728 --- /dev/null +++ b/components/esp_rom/include/esp32c6/rom/ets_sys.h @@ -0,0 +1,555 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_ETS_SYS_H_ +#define _ROM_ETS_SYS_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup ets_sys_apis, ets system related apis + * @brief ets system apis + */ + +/** @addtogroup ets_sys_apis + * @{ + */ + +/************************************************************************ + * NOTE + * Many functions in this header files can't be run in FreeRTOS. + * Please see the comment of the Functions. + * There are also some functions that doesn't work on FreeRTOS + * without listed in the header, such as: + * xtos functions start with "_xtos_" in ld file. + * + *********************************************************************** + */ + +/** \defgroup ets_apis, Espressif Task Scheduler related apis + * @brief ets apis + */ + +/** @addtogroup ets_apis + * @{ + */ + +typedef enum { + ETS_OK = 0, /**< return successful in ets*/ + ETS_FAILED = 1 /**< return failed in ets*/ +} ETS_STATUS; + +typedef ETS_STATUS ets_status_t; + +typedef uint32_t ETSSignal; +typedef uint32_t ETSParam; + +typedef struct ETSEventTag ETSEvent; /**< Event transmit/receive in ets*/ + +struct ETSEventTag { + ETSSignal sig; /**< Event signal, in same task, different Event with different signal*/ + ETSParam par; /**< Event parameter, sometimes without usage, then will be set as 0*/ +}; + +typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processer*/ +typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/ + +/** + * @brief Start the Espressif Task Scheduler, which is an infinit loop. Please do not add code after it. + * + * @param none + * + * @return none + */ +void ets_run(void); + +/** + * @brief Set the Idle callback, when Tasks are processed, will call the callback before CPU goto sleep. + * + * @param ets_idle_cb_t func : The callback function. + * + * @param void *arg : Argument of the callback. + * + * @return None + */ +void ets_set_idle_cb(ets_idle_cb_t func, void *arg); + +/** + * @brief Init a task with processer, priority, queue to receive Event, queue length. + * + * @param ETSTask task : The task processer. + * + * @param uint8_t prio : Task priority, 0-31, bigger num with high priority, one priority with one task. + * + * @param ETSEvent *queue : Queue belongs to the task, task always receives Events, Queue is circular used. + * + * @param uint8_t qlen : Queue length. + * + * @return None + */ +void ets_task(ETSTask task, uint8_t prio, ETSEvent *queue, uint8_t qlen); + +/** + * @brief Post an event to an Task. + * + * @param uint8_t prio : Priority of the Task. + * + * @param ETSSignal sig : Event signal. + * + * @param ETSParam par : Event parameter + * + * @return ETS_OK : post successful + * @return ETS_FAILED : post failed + */ +ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par); + +/** + * @} + */ + +/** \defgroup ets_boot_apis, Boot routing related apis + * @brief ets boot apis + */ + +/** @addtogroup ets_apis + * @{ + */ + +extern const char *const exc_cause_table[40]; ///**< excption cause that defined by the core.*/ + +/** + * @brief Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed. + * When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL. + * + * @param uint32_t start : the PRO Entry code address value in uint32_t + * + * @return None + */ +void ets_set_user_start(uint32_t start); + +/** + * @brief Set Pro cpu Startup code, code can be called when booting is not completed, or in Entry code. + * When Entry code completed, CPU will call the Startup code if not NULL, else call ets_run. + * + * @param uint32_t callback : the Startup code address value in uint32_t + * + * @return None : post successful + */ +void ets_set_startup_callback(uint32_t callback); + +/** + * @brief Set App cpu Entry code, code can be called in PRO CPU. + * When APP booting is completed, APP CPU will call the Entry code if not NULL. + * + * @param uint32_t start : the APP Entry code address value in uint32_t, stored in register APPCPU_CTRL_REG_D. + * + * @return None + */ +void ets_set_appcpu_boot_addr(uint32_t start); + +/** + * @} + */ + +/** \defgroup ets_printf_apis, ets_printf related apis used in ets + * @brief ets printf apis + */ + +/** @addtogroup ets_printf_apis + * @{ + */ + +/** + * @brief Printf the strings to uart or other devices, similar with printf, simple than printf. + * Can not print float point data format, or longlong data format. + * So we maybe only use this in ROM. + * + * @param const char *fmt : See printf. + * + * @param ... : See printf. + * + * @return int : the length printed to the output device. + */ +int ets_printf(const char *fmt, ...); + +/** + * @brief Set the uart channel of ets_printf(uart_tx_one_char). + * ROM will set it base on the efuse and gpio setting, however, this can be changed after booting. + * + * @param uart_no : 0 for UART0, 1 for UART1. + * + * @return None + */ +void ets_set_printf_channel(uint8_t uart_no); + +/** + * @brief Get the uart channel of ets_printf(uart_tx_one_char). + * + * @return uint8_t uart channel used by ets_printf(uart_tx_one_char). + */ +uint8_t ets_get_printf_channel(void); + +/** + * @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function. + * Can not print float point data format, or longlong data format + * + * @param char c : char to output. + * + * @return None + */ +void ets_write_char_uart(char c); + +/** + * @brief Ets_printf have two output functionsï¼ putc1 and putc2, both of which will be called if need ouput. + * To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode. + * + * @param void (*)(char) p: Output function to install. + * + * @return None + */ +void ets_install_putc1(void (*p)(char c)); + +/** + * @brief Ets_printf have two output functionsï¼ putc1 and putc2, both of which will be called if need ouput. + * To install putc2, which is defaulted installed as NULL. + * + * @param void (*)(char) p: Output function to install. + * + * @return None + */ +void ets_install_putc2(void (*p)(char c)); + +/** + * @brief Install putc1 as ets_write_char_uart. + * In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok. + * + * @param None + * + * @return None + */ +void ets_install_uart_printf(void); + +#define ETS_PRINTF(...) ets_printf(...) + +#define ETS_ASSERT(v) do { \ + if (!(v)) { \ + ets_printf("%s %u \n", __FILE__, __LINE__); \ + while (1) {}; \ + } \ +} while (0); + +/** + * @} + */ + +/** \defgroup ets_timer_apis, ets_timer related apis used in ets + * @brief ets timer apis + */ + +/** @addtogroup ets_timer_apis + * @{ + */ +typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/ + +typedef struct _ETSTIMER_ { + struct _ETSTIMER_ *timer_next; /**< timer linker*/ + uint32_t timer_expire; /**< abstruct time when timer expire*/ + uint32_t timer_period; /**< timer period, 0 means timer is not periodic repeated*/ + ETSTimerFunc *timer_func; /**< timer handler*/ + void *timer_arg; /**< timer handler argument*/ +} ETSTimer; + +/** + * @brief Init ets timer, this timer range is 640 us to 429496 ms + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_timer_init(void); + +/** + * @brief In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_timer_deinit(void); + +/** + * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param uint32_t tmout : Timer value in ms, range is 1 to 429496. + * + * @param bool repeat : Timer is periodic repeated. + * + * @return None + */ +void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat); + +/** + * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param uint32_t tmout : Timer value in us, range is 1 to 429496729. + * + * @param bool repeat : Timer is periodic repeated. + * + * @return None + */ +void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat); + +/** + * @brief Disarm an ets timer. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @return None + */ +void ets_timer_disarm(ETSTimer *timer); + +/** + * @brief Set timer callback and argument. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param ETSTimerFunc *pfunction : Timer callback. + * + * @param void *parg : Timer callback argument. + * + * @return None + */ +void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg); + +/** + * @brief Unset timer callback and argument to NULL. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @return None + */ +void ets_timer_done(ETSTimer *ptimer); + +/** + * @brief CPU do while loop for some time. + * In FreeRTOS task, please call FreeRTOS apis. + * + * @param uint32_t us : Delay time in us. + * + * @return None + */ +void ets_delay_us(uint32_t us); + +/** + * @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate. + * Call this function when CPU frequency is changed. + * + * @param uint32_t ticks_per_us : CPU ticks per us. + * + * @return None + */ +void ets_update_cpu_frequency(uint32_t ticks_per_us); + +/** + * @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate. + * + * @note This function only sets the tick rate for the current CPU. It is located in ROM, + * so the deep sleep stub can use it even if IRAM is not initialized yet. + * + * @param uint32_t ticks_per_us : CPU ticks per us. + * + * @return None + */ +void ets_update_cpu_frequency_rom(uint32_t ticks_per_us); + +/** + * @brief Get the real CPU ticks per us to the ets. + * This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency. + * + * @param None + * + * @return uint32_t : CPU ticks per us record in ets. + */ +uint32_t ets_get_cpu_frequency(void); + +/** + * @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store. + * + * @param None + * + * @return uint32_t : if stored in efuse(not 0) + * clock = ets_efuse_get_xtal_freq() * 1000000; + * else if analog_8M in efuse + * clock = ets_get_xtal_scale() * 625 / 16 * ets_efuse_get_8M_clock(); + * else clock = 40M. + */ +uint32_t ets_get_xtal_freq(void); + +/** + * @brief Get the apb divior by xtal frequency. + * When any types of reset happen, the default value is 2. + * + * @param None + * + * @return uint32_t : 1 or 2. + */ +uint32_t ets_get_xtal_div(void); + +/** + * @brief Get apb_freq value, If value not stored in RTC_STORE5, than store. + * + * @param None + * + * @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register. + * clock = (REG_READ(RTC_STORE5) & 0xffff) << 12; + * else store ets_get_detected_xtal_freq() in. + */ +uint32_t ets_get_apb_freq(void); + +/** + * @} + */ + +/** \defgroup ets_intr_apis, ets interrupt configure related apis + * @brief ets intr apis + */ + +/** @addtogroup ets_intr_apis + * @{ + */ + +typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/ + +/** + * @brief Attach a interrupt handler to a CPU interrupt number. + * This function equals to _xtos_set_interrupt_handler_arg(i, func, arg). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param int i : CPU interrupt number. + * + * @param ets_isr_t func : Interrupt handler. + * + * @param void *arg : argument of the handler. + * + * @return None + */ +void ets_isr_attach(int i, ets_isr_t func, void *arg); + +/** + * @brief Mask the interrupts which show in mask bits. + * This function equals to _xtos_ints_off(mask). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. + * + * @return None + */ +void ets_isr_mask(uint32_t mask); + +/** + * @brief Unmask the interrupts which show in mask bits. + * This function equals to _xtos_ints_on(mask). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. + * + * @return None + */ +void ets_isr_unmask(uint32_t unmask); + +/** + * @brief Lock the interrupt to level 2. + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_intr_lock(void); + +/** + * @brief Unlock the interrupt to level 0. + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_intr_unlock(void); + +/** + * @brief Unlock the interrupt to level 0, and CPU will go into power save mode(wait interrupt). + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_waiti0(void); + +/** + * @brief Attach an CPU interrupt to a hardware source. + * We have 4 steps to use an interrupt: + * 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM); + * 2.Set interrupt handler. xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL); + * 3.Enable interrupt for CPU. xt_ints_on(1 << ETS_WMAC_INUM); + * 4.Enable interrupt in the module. + * + * @param int cpu_no : The CPU which the interrupt number belongs. + * + * @param uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table. + * + * @param uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table. + * + * @return None + */ +void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); + +/** + * @} + */ + +#ifndef MAC2STR +#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5] +#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x" +#endif + +#define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) + +typedef enum { + OK = 0, + FAIL, + PENDING, + BUSY, + CANCEL, +} STATUS; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_ETS_SYS_H_ */ diff --git a/components/esp_rom/include/esp32c6/rom/gpio.h b/components/esp_rom/include/esp32c6/rom/gpio.h new file mode 100644 index 0000000000..62fc551b3a --- /dev/null +++ b/components/esp_rom/include/esp32c6/rom/gpio.h @@ -0,0 +1,303 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_GPIO_H_ +#define _ROM_GPIO_H_ + +#include +#include + +#include "esp_attr.h" +#include "soc/gpio_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup gpio_apis, uart configuration and communication related apis + * @brief gpio apis + */ + +/** @addtogroup gpio_apis + * @{ + */ + +#define GPIO_REG_READ(reg) READ_PERI_REG(reg) +#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(reg, val) +#define GPIO_ID_PIN0 0 +#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) +#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4) + +#define GPIO_FUNC_IN_HIGH 0x38 +#define GPIO_FUNC_IN_LOW 0x3C + +#define GPIO_ID_IS_PIN_REGISTER(reg_id) \ + ((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1))) + +#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0) + +typedef enum { + GPIO_PIN_INTR_DISABLE = 0, + GPIO_PIN_INTR_POSEDGE = 1, + GPIO_PIN_INTR_NEGEDGE = 2, + GPIO_PIN_INTR_ANYEDGE = 3, + GPIO_PIN_INTR_LOLEVEL = 4, + GPIO_PIN_INTR_HILEVEL = 5 +} GPIO_INT_TYPE; + +#define GPIO_OUTPUT_SET(gpio_no, bit_value) \ + ((gpio_no < 32) ? gpio_output_set(bit_value<>gpio_no)&BIT0) : ((gpio_input_get_high()>>(gpio_no - 32))&BIT0)) + +/* GPIO interrupt handler, registered through gpio_intr_handler_register */ +typedef void (* gpio_intr_handler_fn_t)(uint32_t intr_mask, bool high, void *arg); + +/** + * @brief Initialize GPIO. This includes reading the GPIO Configuration DataSet + * to initialize "output enables" and pin configurations for each gpio pin. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void gpio_init(void); + +/** + * @brief Change GPIO(0-31) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0). + * There is no particular ordering guaranteed; so if the order of writes is significant, + * calling code should divide a single call into multiple calls. + * + * @param uint32_t set_mask : the gpios that need high level. + * + * @param uint32_t clear_mask : the gpios that need low level. + * + * @param uint32_t enable_mask : the gpios that need be changed. + * + * @param uint32_t disable_mask : the gpios that need diable output. + * + * @return None + */ +void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask); + +/** + * @brief Change GPIO(32-39) pin output by setting, clearing, or disabling pins, GPIO32<->BIT(0). + * There is no particular ordering guaranteed; so if the order of writes is significant, + * calling code should divide a single call into multiple calls. + * + * @param uint32_t set_mask : the gpios that need high level. + * + * @param uint32_t clear_mask : the gpios that need low level. + * + * @param uint32_t enable_mask : the gpios that need be changed. + * + * @param uint32_t disable_mask : the gpios that need diable output. + * + * @return None + */ +void gpio_output_set_high(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask); + +/** + * @brief Sample the value of GPIO input pins(0-31) and returns a bitmask. + * + * @param None + * + * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0. + */ +uint32_t gpio_input_get(void); + +/** + * @brief Sample the value of GPIO input pins(32-39) and returns a bitmask. + * + * @param None + * + * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO32. + */ +uint32_t gpio_input_get_high(void); + +/** + * @brief Register an application-specific interrupt handler for GPIO pin interrupts. + * Once the interrupt handler is called, it will not be called again until after a call to gpio_intr_ack. + * Please do not call this function in SDK. + * + * @param gpio_intr_handler_fn_t fn : gpio application-specific interrupt handler + * + * @param void *arg : gpio application-specific interrupt handler argument. + * + * @return None + */ +void gpio_intr_handler_register(gpio_intr_handler_fn_t fn, void *arg); + +/** + * @brief Get gpio interrupts which happens but not processed. + * Please do not call this function in SDK. + * + * @param None + * + * @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO0. + */ +uint32_t gpio_intr_pending(void); + +/** + * @brief Get gpio interrupts which happens but not processed. + * Please do not call this function in SDK. + * + * @param None + * + * @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO32. + */ +uint32_t gpio_intr_pending_high(void); + +/** + * @brief Ack gpio interrupts to process pending interrupts. + * Please do not call this function in SDK. + * + * @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO0. + * + * @return None + */ +void gpio_intr_ack(uint32_t ack_mask); + +/** + * @brief Ack gpio interrupts to process pending interrupts. + * Please do not call this function in SDK. + * + * @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO32. + * + * @return None + */ +void gpio_intr_ack_high(uint32_t ack_mask); + +/** + * @brief Set GPIO to wakeup the ESP32. + * Please do not call this function in SDK. + * + * @param uint32_t i: gpio number. + * + * @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used + * + * @return None + */ +void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state); + +/** + * @brief disable GPIOs to wakeup the ESP32. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void gpio_pin_wakeup_disable(void); + +/** + * @brief set gpio input to a signal, one gpio can input to several signals. + * + * @param uint32_t gpio : gpio number, 0~0x2f + * gpio == 0x3C, input 0 to signal + * gpio == 0x3A, input nothing to signal + * gpio == 0x38, input 1 to signal + * + * @param uint32_t signal_idx : signal index. + * + * @param bool inv : the signal is inv or not + * + * @return None + */ +void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv); + +/** + * @brief set signal output to gpio, one signal can output to several gpios. + * + * @param uint32_t gpio : gpio number, 0~0x2f + * + * @param uint32_t signal_idx : signal index. + * signal_idx == 0x100, cancel output put to the gpio + * + * @param bool out_inv : the signal output is invert or not + * + * @param bool oen_inv : the signal output enable is invert or not + * + * @return None + */ +void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv); + +/** + * @brief Select pad as a gpio function from IOMUX. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +void gpio_pad_select_gpio(uint32_t gpio_num); + +/** + * @brief Set pad driver capability. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @param uint32_t drv : 0-3 + * + * @return None + */ +void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv); + +/** + * @brief Pull up the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +void gpio_pad_pullup(uint32_t gpio_num); + +/** + * @brief Pull down the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +void gpio_pad_pulldown(uint32_t gpio_num); + +/** + * @brief Unhold the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +void gpio_pad_unhold(uint32_t gpio_num); + +/** + * @brief Hold the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +void gpio_pad_hold(uint32_t gpio_num); + +/** + * @brief enable gpio pad input. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +void gpio_pad_input_enable(uint32_t gpio_num); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_GPIO_H_ */ diff --git a/components/esp_rom/include/esp32c6/rom/hmac.h b/components/esp_rom/include/esp32c6/rom/hmac.h new file mode 100644 index 0000000000..126b8a46a1 --- /dev/null +++ b/components/esp_rom/include/esp32c6/rom/hmac.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_HMAC_H_ +#define _ROM_HMAC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "efuse.h" + +void ets_hmac_enable(void); + +void ets_hmac_disable(void); + +/* Use the "upstream" HMAC key (ETS_EFUSE_KEY_PURPOSE_HMAC_UP) + to digest a message. +*/ +int ets_hmac_calculate_message(ets_efuse_block_t key_block, const void *message, size_t message_len, uint8_t *hmac); + +/* Calculate a downstream HMAC message to temporarily enable JTAG, or + to generate a Digital Signature data decryption key. + + - purpose must be ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE + or ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG + + - key_block must be in range ETS_EFUSE_BLOCK_KEY0 toETS_EFUSE_BLOCK_KEY6. + This efuse block must have the corresponding purpose set in "purpose", or + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL. + + The result of this HMAC calculation is only made available "downstream" to the + corresponding hardware module, and cannot be accessed by software. +*/ +int ets_hmac_calculate_downstream(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose); + +/* Invalidate a downstream HMAC value previously calculated by ets_hmac_calculate_downstream(). + * + * - purpose must match a previous call to ets_hmac_calculate_downstream(). + * + * After this function is called, the corresponding internal operation (JTAG or DS) will no longer + * have access to the generated key. + */ +int ets_hmac_invalidate_downstream(ets_efuse_purpose_t purpose); + +#ifdef __cplusplus +} +#endif + +#endif // _ROM_HMAC_H_ diff --git a/components/esp_rom/include/esp32c6/rom/libc_stubs.h b/components/esp_rom/include/esp32c6/rom/libc_stubs.h new file mode 100644 index 0000000000..1ccc11f86a --- /dev/null +++ b/components/esp_rom/include/esp32c6/rom/libc_stubs.h @@ -0,0 +1,82 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _ROM_LIBC_STUBS_H_ +#define _ROM_LIBC_STUBS_H_ + +#include +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* +ESP32-C6 ROM code contains implementations of some of C library functions. +Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall +implementation defined in the following struct. + +The table itself, by default, is not allocated in RAM. A global pointer syscall_table_ptr is used to +set the address + +So, before using any of the C library functions (except for pure functions and memcpy/memset functions), +application must allocate syscall table structure for each CPU being used, and populate it with pointers +to actual implementations of corresponding syscalls. +*/ + +struct syscall_stub_table { + struct _reent *(*__getreent)(void); + void *(*_malloc_r)(struct _reent *r, size_t); + void (*_free_r)(struct _reent *r, void *); + void *(*_realloc_r)(struct _reent *r, void *, size_t); + void *(*_calloc_r)(struct _reent *r, size_t, size_t); + void (*_abort)(void); + int (*_system_r)(struct _reent *r, const char *); + int (*_rename_r)(struct _reent *r, const char *, const char *); + clock_t (*_times_r)(struct _reent *r, struct tms *); + int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *); + void (*_raise_r)(struct _reent *r); + int (*_unlink_r)(struct _reent *r, const char *); + int (*_link_r)(struct _reent *r, const char *, const char *); + int (*_stat_r)(struct _reent *r, const char *, struct stat *); + int (*_fstat_r)(struct _reent *r, int, struct stat *); + void *(*_sbrk_r)(struct _reent *r, ptrdiff_t); + int (*_getpid_r)(struct _reent *r); + int (*_kill_r)(struct _reent *r, int, int); + void (*_exit_r)(struct _reent *r, int); + int (*_close_r)(struct _reent *r, int); + int (*_open_r)(struct _reent *r, const char *, int, int); + int (*_write_r)(struct _reent *r, int, const void *, int); + int (*_lseek_r)(struct _reent *r, int, int, int); + int (*_read_r)(struct _reent *r, int, void *, int); + void (*_retarget_lock_init)(_LOCK_T *lock); + void (*_retarget_lock_init_recursive)(_LOCK_T *lock); + void (*_retarget_lock_close)(_LOCK_T lock); + void (*_retarget_lock_close_recursive)(_LOCK_T lock); + void (*_retarget_lock_acquire)(_LOCK_T lock); + void (*_retarget_lock_acquire_recursive)(_LOCK_T lock); + int (*_retarget_lock_try_acquire)(_LOCK_T lock); + int (*_retarget_lock_try_acquire_recursive)(_LOCK_T lock); + void (*_retarget_lock_release)(_LOCK_T lock); + void (*_retarget_lock_release_recursive)(_LOCK_T lock); + int (*_printf_float)(struct _reent *data, void *pdata, FILE *fp, int (*pfunc) (struct _reent *, FILE *, const char *, size_t len), va_list *ap); + int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap); + void (*__assert_func) (const char *file, int line, const char *func, const char *failedexpr) __attribute__((noreturn)); + void (*__sinit) (struct _reent *r); + void (*_cleanup_r) (struct _reent *r); +}; + +extern struct syscall_stub_table *syscall_table_ptr; + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif /* _ROM_LIBC_STUBS_H_ */ diff --git a/components/esp_rom/include/esp32c6/rom/lldesc.h b/components/esp_rom/include/esp32c6/rom/lldesc.h new file mode 100644 index 0000000000..86562a8546 --- /dev/null +++ b/components/esp_rom/include/esp32c6/rom/lldesc.h @@ -0,0 +1,143 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_LLDESC_H_ +#define _ROM_LLDESC_H_ + +#include + +#include "sys/queue.h" +#include "esp_rom_lldesc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define LLDESC_TX_MBLK_SIZE 268 /* */ +#define LLDESC_RX_SMBLK_SIZE 64 /* small block size, for small mgmt frame */ +#define LLDESC_RX_MBLK_SIZE 524 /* rx is large sinec we want to contain mgmt frame in one block*/ +#define LLDESC_RX_AMPDU_ENTRY_MBLK_SIZE 64 /* it is a small buffer which is a cycle link*/ +#define LLDESC_RX_AMPDU_LEN_MBLK_SIZE 256 /*for ampdu entry*/ +#ifdef ESP_MAC_5 +#define LLDESC_TX_MBLK_NUM 116 /* 64K / 256 */ +#define LLDESC_RX_MBLK_NUM 82 /* 64K / 512 MAX 172*/ +#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4 +#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 12 +#else +#ifdef SBUF_RXTX +#define LLDESC_TX_MBLK_NUM_MAX (2 * 48) /* 23K / 260 - 8 */ +#define LLDESC_RX_MBLK_NUM_MAX (2 * 48) /* 23K / 524 */ +#define LLDESC_TX_MBLK_NUM_MIN (2 * 16) /* 23K / 260 - 8 */ +#define LLDESC_RX_MBLK_NUM_MIN (2 * 16) /* 23K / 524 */ +#endif +#define LLDESC_TX_MBLK_NUM 10 //(2 * 32) /* 23K / 260 - 8 */ + +#ifdef IEEE80211_RX_AMPDU +#define LLDESC_RX_MBLK_NUM 30 +#else +#define LLDESC_RX_MBLK_NUM 10 +#endif /*IEEE80211_RX_AMPDU*/ + +#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4 +#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 8 +#endif /* !ESP_MAC_5 */ + +typedef struct tx_ampdu_entry_s { + uint32_t sub_len : 12, + dili_num : 7, + : 1, + null_byte: 2, + data : 1, + enc : 1, + seq : 8; +} tx_ampdu_entry_t; + +typedef struct lldesc_chain_s { + lldesc_t *head; + lldesc_t *tail; +} lldesc_chain_t; + +#ifdef SBUF_RXTX +enum sbuf_mask_s { + SBUF_MOVE_NO = 0, + SBUF_MOVE_TX2RX, + SBUF_MOVE_RX2TX, +} ; + +#define SBUF_MOVE_STEP 8 +#endif +#define LLDESC_SIZE sizeof(struct lldesc_s) + +/* SLC Descriptor */ +#define LLDESC_OWNER_MASK 0x80000000 +#define LLDESC_OWNER_SHIFT 31 +#define LLDESC_SW_OWNED 0 +#define LLDESC_HW_OWNED 1 + +#define LLDESC_EOF_MASK 0x40000000 +#define LLDESC_EOF_SHIFT 30 + +#define LLDESC_SOSF_MASK 0x20000000 +#define LLDESC_SOSF_SHIFT 29 + +#define LLDESC_LENGTH_MASK 0x00fff000 +#define LLDESC_LENGTH_SHIFT 12 + +#define LLDESC_SIZE_MASK 0x00000fff +#define LLDESC_SIZE_SHIFT 0 + +#define LLDESC_ADDR_MASK 0x000fffff + +void lldesc_build_chain(uint8_t *descptr, uint32_t desclen, uint8_t *mblkptr, uint32_t buflen, uint32_t blksz, uint8_t owner, + lldesc_t **head, +#ifdef TO_HOST_RESTART + lldesc_t **one_before_tail, +#endif + lldesc_t **tail); + +lldesc_t *lldesc_num2link(lldesc_t *head, uint16_t nblks); + +lldesc_t *lldesc_set_owner(lldesc_t *head, uint16_t nblks, uint8_t owner); + +static inline uint32_t lldesc_get_chain_length(lldesc_t *head) +{ + lldesc_t *ds = head; + uint32_t len = 0; + + while (ds) { + len += ds->length; + ds = STAILQ_NEXT(ds, qe); + } + + return len; +} + +static inline void lldesc_config(lldesc_t *ds, uint8_t owner, uint8_t eof, uint8_t sosf, uint16_t len) +{ + ds->owner = owner; + ds->eof = eof; + ds->sosf = sosf; + ds->length = len; +} + +#define LLDESC_CONFIG(_desc, _owner, _eof, _sosf, _len) do { \ + (_desc)->owner = (_owner); \ + (_desc)->eof = (_eof); \ + (_desc)->sosf = (_sosf); \ + (_desc)->length = (_len); \ +} while(0) + +#define LLDESC_FROM_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0) + +#define LLDESC_MAC_RX_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, (ds)->size) + +#define LLDESC_TO_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0) + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_LLDESC_H_ */ diff --git a/components/esp_rom/include/esp32c6/rom/md5_hash.h b/components/esp_rom/include/esp32c6/rom/md5_hash.h new file mode 100644 index 0000000000..3c5e10d1bf --- /dev/null +++ b/components/esp_rom/include/esp32c6/rom/md5_hash.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: 2003-2005, Jouni Malinen + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/* + * MD5 internal definitions + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +#ifndef _ROM_MD5_HASH_H_ +#define _ROM_MD5_HASH_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct MD5Context { + uint32_t buf[4]; + uint32_t bits[2]; + uint8_t in[64]; +}; + +void MD5Init(struct MD5Context *context); +void MD5Update(struct MD5Context *context, unsigned char const *buf, unsigned len); +void MD5Final(unsigned char digest[16], struct MD5Context *context); + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_MD5_HASH_H_ */ diff --git a/components/esp_rom/include/esp32c6/rom/miniz.h b/components/esp_rom/include/esp32c6/rom/miniz.h new file mode 100644 index 0000000000..902f64c13e --- /dev/null +++ b/components/esp_rom/include/esp32c6/rom/miniz.h @@ -0,0 +1,765 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef MINIZ_HEADER_INCLUDED +#define MINIZ_HEADER_INCLUDED + +#include + +// Defines to completely disable specific portions of miniz.c: +// If all macros here are defined the only functionality remaining will be CRC-32, adler-32, tinfl, and tdefl. + +// Define MINIZ_NO_STDIO to disable all usage and any functions which rely on stdio for file I/O. +#define MINIZ_NO_STDIO + +// If MINIZ_NO_TIME is specified then the ZIP archive functions will not be able to get the current time, or +// get/set file times, and the C run-time funcs that get/set times won't be called. +// The current downside is the times written to your archives will be from 1979. +#define MINIZ_NO_TIME + +// Define MINIZ_NO_ARCHIVE_APIS to disable all ZIP archive API's. +#define MINIZ_NO_ARCHIVE_APIS + +// Define MINIZ_NO_ARCHIVE_APIS to disable all writing related ZIP archive API's. +#define MINIZ_NO_ARCHIVE_WRITING_APIS + +// Define MINIZ_NO_ZLIB_APIS to remove all ZLIB-style compression/decompression API's. +#define MINIZ_NO_ZLIB_APIS + +// Define MINIZ_NO_ZLIB_COMPATIBLE_NAME to disable zlib names, to prevent conflicts against stock zlib. +#define MINIZ_NO_ZLIB_COMPATIBLE_NAMES + +// Define MINIZ_NO_MALLOC to disable all calls to malloc, free, and realloc. +// Note if MINIZ_NO_MALLOC is defined then the user must always provide custom user alloc/free/realloc +// callbacks to the zlib and archive API's, and a few stand-alone helper API's which don't provide custom user +// functions (such as tdefl_compress_mem_to_heap() and tinfl_decompress_mem_to_heap()) won't work. +#define MINIZ_NO_MALLOC + +#if defined(__TINYC__) && (defined(__linux) || defined(__linux__)) +// TODO: Work around "error: include file 'sys\utime.h' when compiling with tcc on Linux +#define MINIZ_NO_TIME +#endif + +#if !defined(MINIZ_NO_TIME) && !defined(MINIZ_NO_ARCHIVE_APIS) +#include +#endif + +//Hardcoded options for Xtensa - JD +#define MINIZ_X86_OR_X64_CPU 0 +#define MINIZ_LITTLE_ENDIAN 1 +#define MINIZ_USE_UNALIGNED_LOADS_AND_STORES 0 +#define MINIZ_HAS_64BIT_REGISTERS 0 +#define TINFL_USE_64BIT_BITBUF 0 + + +#if defined(_M_IX86) || defined(_M_X64) || defined(__i386__) || defined(__i386) || defined(__i486__) || defined(__i486) || defined(i386) || defined(__ia64__) || defined(__x86_64__) +// MINIZ_X86_OR_X64_CPU is only used to help set the below macros. +#define MINIZ_X86_OR_X64_CPU 1 +#endif + +#if (__BYTE_ORDER__==__ORDER_LITTLE_ENDIAN__) || MINIZ_X86_OR_X64_CPU +// Set MINIZ_LITTLE_ENDIAN to 1 if the processor is little endian. +#define MINIZ_LITTLE_ENDIAN 1 +#endif + +#if MINIZ_X86_OR_X64_CPU +// Set MINIZ_USE_UNALIGNED_LOADS_AND_STORES to 1 on CPU's that permit efficient integer loads and stores from unaligned addresses. +#define MINIZ_USE_UNALIGNED_LOADS_AND_STORES 1 +#endif + +#if defined(_M_X64) || defined(_WIN64) || defined(__MINGW64__) || defined(_LP64) || defined(__LP64__) || defined(__ia64__) || defined(__x86_64__) +// Set MINIZ_HAS_64BIT_REGISTERS to 1 if operations on 64-bit integers are reasonably fast (and don't involve compiler generated calls to helper functions). +#define MINIZ_HAS_64BIT_REGISTERS 1 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +// ------------------- zlib-style API Definitions. + +// For more compatibility with zlib, miniz.c uses unsigned long for some parameters/struct members. Beware: mz_ulong can be either 32 or 64-bits! +typedef unsigned long mz_ulong; + +// mz_free() internally uses the MZ_FREE() macro (which by default calls free() unless you've modified the MZ_MALLOC macro) to release a block allocated from the heap. +void mz_free(void *p); + +#define MZ_ADLER32_INIT (1) +// mz_adler32() returns the initial adler-32 value to use when called with ptr==NULL. +mz_ulong mz_adler32(mz_ulong adler, const unsigned char *ptr, size_t buf_len); + +#define MZ_CRC32_INIT (0) +// mz_crc32() returns the initial CRC-32 value to use when called with ptr==NULL. +mz_ulong mz_crc32(mz_ulong crc, const unsigned char *ptr, size_t buf_len); + +// Compression strategies. +enum { MZ_DEFAULT_STRATEGY = 0, MZ_FILTERED = 1, MZ_HUFFMAN_ONLY = 2, MZ_RLE = 3, MZ_FIXED = 4 }; + +// Method +#define MZ_DEFLATED 8 + +#ifndef MINIZ_NO_ZLIB_APIS + +// Heap allocation callbacks. +// Note that mz_alloc_func parameter types purpsosely differ from zlib's: items/size is size_t, not unsigned long. +typedef void *(*mz_alloc_func)(void *opaque, size_t items, size_t size); +typedef void (*mz_free_func)(void *opaque, void *address); +typedef void *(*mz_realloc_func)(void *opaque, void *address, size_t items, size_t size); + +#define MZ_VERSION "9.1.15" +#define MZ_VERNUM 0x91F0 +#define MZ_VER_MAJOR 9 +#define MZ_VER_MINOR 1 +#define MZ_VER_REVISION 15 +#define MZ_VER_SUBREVISION 0 + +// Flush values. For typical usage you only need MZ_NO_FLUSH and MZ_FINISH. The other values are for advanced use (refer to the zlib docs). +enum { MZ_NO_FLUSH = 0, MZ_PARTIAL_FLUSH = 1, MZ_SYNC_FLUSH = 2, MZ_FULL_FLUSH = 3, MZ_FINISH = 4, MZ_BLOCK = 5 }; + +// Return status codes. MZ_PARAM_ERROR is non-standard. +enum { MZ_OK = 0, MZ_STREAM_END = 1, MZ_NEED_DICT = 2, MZ_ERRNO = -1, MZ_STREAM_ERROR = -2, MZ_DATA_ERROR = -3, MZ_MEM_ERROR = -4, MZ_BUF_ERROR = -5, MZ_VERSION_ERROR = -6, MZ_PARAM_ERROR = -10000 }; + +// Compression levels: 0-9 are the standard zlib-style levels, 10 is best possible compression (not zlib compatible, and may be very slow), MZ_DEFAULT_COMPRESSION=MZ_DEFAULT_LEVEL. +enum { MZ_NO_COMPRESSION = 0, MZ_BEST_SPEED = 1, MZ_BEST_COMPRESSION = 9, MZ_UBER_COMPRESSION = 10, MZ_DEFAULT_LEVEL = 6, MZ_DEFAULT_COMPRESSION = -1 }; + +// Window bits +#define MZ_DEFAULT_WINDOW_BITS 15 + +struct mz_internal_state; + +// Compression/decompression stream struct. +typedef struct mz_stream_s { + const unsigned char *next_in; // pointer to next byte to read + unsigned int avail_in; // number of bytes available at next_in + mz_ulong total_in; // total number of bytes consumed so far + + unsigned char *next_out; // pointer to next byte to write + unsigned int avail_out; // number of bytes that can be written to next_out + mz_ulong total_out; // total number of bytes produced so far + + char *msg; // error msg (unused) + struct mz_internal_state *state; // internal state, allocated by zalloc/zfree + + mz_alloc_func zalloc; // optional heap allocation function (defaults to malloc) + mz_free_func zfree; // optional heap free function (defaults to free) + void *opaque; // heap alloc function user pointer + + int data_type; // data_type (unused) + mz_ulong adler; // adler32 of the source or uncompressed data + mz_ulong reserved; // not used +} mz_stream; + +typedef mz_stream *mz_streamp; + +// Returns the version string of miniz.c. +const char *mz_version(void); + +// mz_deflateInit() initializes a compressor with default options: +// Parameters: +// pStream must point to an initialized mz_stream struct. +// level must be between [MZ_NO_COMPRESSION, MZ_BEST_COMPRESSION]. +// level 1 enables a specially optimized compression function that's been optimized purely for performance, not ratio. +// (This special func. is currently only enabled when MINIZ_USE_UNALIGNED_LOADS_AND_STORES and MINIZ_LITTLE_ENDIAN are defined.) +// Return values: +// MZ_OK on success. +// MZ_STREAM_ERROR if the stream is bogus. +// MZ_PARAM_ERROR if the input parameters are bogus. +// MZ_MEM_ERROR on out of memory. +int mz_deflateInit(mz_streamp pStream, int level); + +// mz_deflateInit2() is like mz_deflate(), except with more control: +// Additional parameters: +// method must be MZ_DEFLATED +// window_bits must be MZ_DEFAULT_WINDOW_BITS (to wrap the deflate stream with zlib header/adler-32 footer) or -MZ_DEFAULT_WINDOW_BITS (raw deflate/no header or footer) +// mem_level must be between [1, 9] (it's checked but ignored by miniz.c) +int mz_deflateInit2(mz_streamp pStream, int level, int method, int window_bits, int mem_level, int strategy); + +// Quickly resets a compressor without having to reallocate anything. Same as calling mz_deflateEnd() followed by mz_deflateInit()/mz_deflateInit2(). +int mz_deflateReset(mz_streamp pStream); + +// mz_deflate() compresses the input to output, consuming as much of the input and producing as much output as possible. +// Parameters: +// pStream is the stream to read from and write to. You must initialize/update the next_in, avail_in, next_out, and avail_out members. +// flush may be MZ_NO_FLUSH, MZ_PARTIAL_FLUSH/MZ_SYNC_FLUSH, MZ_FULL_FLUSH, or MZ_FINISH. +// Return values: +// MZ_OK on success (when flushing, or if more input is needed but not available, and/or there's more output to be written but the output buffer is full). +// MZ_STREAM_END if all input has been consumed and all output bytes have been written. Don't call mz_deflate() on the stream anymore. +// MZ_STREAM_ERROR if the stream is bogus. +// MZ_PARAM_ERROR if one of the parameters is invalid. +// MZ_BUF_ERROR if no forward progress is possible because the input and/or output buffers are empty. (Fill up the input buffer or free up some output space and try again.) +int mz_deflate(mz_streamp pStream, int flush); + +// mz_deflateEnd() deinitializes a compressor: +// Return values: +// MZ_OK on success. +// MZ_STREAM_ERROR if the stream is bogus. +int mz_deflateEnd(mz_streamp pStream); + +// mz_deflateBound() returns a (very) conservative upper bound on the amount of data that could be generated by deflate(), assuming flush is set to only MZ_NO_FLUSH or MZ_FINISH. +mz_ulong mz_deflateBound(mz_streamp pStream, mz_ulong source_len); + +// Single-call compression functions mz_compress() and mz_compress2(): +// Returns MZ_OK on success, or one of the error codes from mz_deflate() on failure. +int mz_compress(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len); +int mz_compress2(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len, int level); + +// mz_compressBound() returns a (very) conservative upper bound on the amount of data that could be generated by calling mz_compress(). +mz_ulong mz_compressBound(mz_ulong source_len); + +// Initializes a decompressor. +int mz_inflateInit(mz_streamp pStream); + +// mz_inflateInit2() is like mz_inflateInit() with an additional option that controls the window size and whether or not the stream has been wrapped with a zlib header/footer: +// window_bits must be MZ_DEFAULT_WINDOW_BITS (to parse zlib header/footer) or -MZ_DEFAULT_WINDOW_BITS (raw deflate). +int mz_inflateInit2(mz_streamp pStream, int window_bits); + +// Decompresses the input stream to the output, consuming only as much of the input as needed, and writing as much to the output as possible. +// Parameters: +// pStream is the stream to read from and write to. You must initialize/update the next_in, avail_in, next_out, and avail_out members. +// flush may be MZ_NO_FLUSH, MZ_SYNC_FLUSH, or MZ_FINISH. +// On the first call, if flush is MZ_FINISH it's assumed the input and output buffers are both sized large enough to decompress the entire stream in a single call (this is slightly faster). +// MZ_FINISH implies that there are no more source bytes available beside what's already in the input buffer, and that the output buffer is large enough to hold the rest of the decompressed data. +// Return values: +// MZ_OK on success. Either more input is needed but not available, and/or there's more output to be written but the output buffer is full. +// MZ_STREAM_END if all needed input has been consumed and all output bytes have been written. For zlib streams, the adler-32 of the decompressed data has also been verified. +// MZ_STREAM_ERROR if the stream is bogus. +// MZ_DATA_ERROR if the deflate stream is invalid. +// MZ_PARAM_ERROR if one of the parameters is invalid. +// MZ_BUF_ERROR if no forward progress is possible because the input buffer is empty but the inflater needs more input to continue, or if the output buffer is not large enough. Call mz_inflate() again +// with more input data, or with more room in the output buffer (except when using single call decompression, described above). +int mz_inflate(mz_streamp pStream, int flush); + +// Deinitializes a decompressor. +int mz_inflateEnd(mz_streamp pStream); + +// Single-call decompression. +// Returns MZ_OK on success, or one of the error codes from mz_inflate() on failure. +int mz_uncompress(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len); + +// Returns a string description of the specified error code, or NULL if the error code is invalid. +const char *mz_error(int err); + +// Redefine zlib-compatible names to miniz equivalents, so miniz.c can be used as a drop-in replacement for the subset of zlib that miniz.c supports. +// Define MINIZ_NO_ZLIB_COMPATIBLE_NAMES to disable zlib-compatibility if you use zlib in the same project. +#ifndef MINIZ_NO_ZLIB_COMPATIBLE_NAMES +typedef unsigned char Byte; +typedef unsigned int uInt; +typedef mz_ulong uLong; +typedef Byte Bytef; +typedef uInt uIntf; +typedef char charf; +typedef int intf; +typedef void *voidpf; +typedef uLong uLongf; +typedef void *voidp; +typedef void *const voidpc; +#define Z_NULL 0 +#define Z_NO_FLUSH MZ_NO_FLUSH +#define Z_PARTIAL_FLUSH MZ_PARTIAL_FLUSH +#define Z_SYNC_FLUSH MZ_SYNC_FLUSH +#define Z_FULL_FLUSH MZ_FULL_FLUSH +#define Z_FINISH MZ_FINISH +#define Z_BLOCK MZ_BLOCK +#define Z_OK MZ_OK +#define Z_STREAM_END MZ_STREAM_END +#define Z_NEED_DICT MZ_NEED_DICT +#define Z_ERRNO MZ_ERRNO +#define Z_STREAM_ERROR MZ_STREAM_ERROR +#define Z_DATA_ERROR MZ_DATA_ERROR +#define Z_MEM_ERROR MZ_MEM_ERROR +#define Z_BUF_ERROR MZ_BUF_ERROR +#define Z_VERSION_ERROR MZ_VERSION_ERROR +#define Z_PARAM_ERROR MZ_PARAM_ERROR +#define Z_NO_COMPRESSION MZ_NO_COMPRESSION +#define Z_BEST_SPEED MZ_BEST_SPEED +#define Z_BEST_COMPRESSION MZ_BEST_COMPRESSION +#define Z_DEFAULT_COMPRESSION MZ_DEFAULT_COMPRESSION +#define Z_DEFAULT_STRATEGY MZ_DEFAULT_STRATEGY +#define Z_FILTERED MZ_FILTERED +#define Z_HUFFMAN_ONLY MZ_HUFFMAN_ONLY +#define Z_RLE MZ_RLE +#define Z_FIXED MZ_FIXED +#define Z_DEFLATED MZ_DEFLATED +#define Z_DEFAULT_WINDOW_BITS MZ_DEFAULT_WINDOW_BITS +#define alloc_func mz_alloc_func +#define free_func mz_free_func +#define internal_state mz_internal_state +#define z_stream mz_stream +#define deflateInit mz_deflateInit +#define deflateInit2 mz_deflateInit2 +#define deflateReset mz_deflateReset +#define deflate mz_deflate +#define deflateEnd mz_deflateEnd +#define deflateBound mz_deflateBound +#define compress mz_compress +#define compress2 mz_compress2 +#define compressBound mz_compressBound +#define inflateInit mz_inflateInit +#define inflateInit2 mz_inflateInit2 +#define inflate mz_inflate +#define inflateEnd mz_inflateEnd +#define uncompress mz_uncompress +#define crc32 mz_crc32 +#define adler32 mz_adler32 +#define MAX_WBITS 15 +#define MAX_MEM_LEVEL 9 +#define zError mz_error +#define ZLIB_VERSION MZ_VERSION +#define ZLIB_VERNUM MZ_VERNUM +#define ZLIB_VER_MAJOR MZ_VER_MAJOR +#define ZLIB_VER_MINOR MZ_VER_MINOR +#define ZLIB_VER_REVISION MZ_VER_REVISION +#define ZLIB_VER_SUBREVISION MZ_VER_SUBREVISION +#define zlibVersion mz_version +#define zlib_version mz_version() +#endif // #ifndef MINIZ_NO_ZLIB_COMPATIBLE_NAMES + +#endif // MINIZ_NO_ZLIB_APIS + +// ------------------- Types and macros + +typedef unsigned char mz_uint8; +typedef signed short mz_int16; +typedef unsigned short mz_uint16; +typedef unsigned int mz_uint32; +typedef unsigned int mz_uint; +typedef long long mz_int64; +typedef unsigned long long mz_uint64; +typedef int mz_bool; + +#define MZ_FALSE (0) +#define MZ_TRUE (1) + +// An attempt to work around MSVC's spammy "warning C4127: conditional expression is constant" message. +#ifdef _MSC_VER +#define MZ_MACRO_END while (0, 0) +#else +#define MZ_MACRO_END while (0) +#endif + +// ------------------- ZIP archive reading/writing + +#ifndef MINIZ_NO_ARCHIVE_APIS + +enum { + MZ_ZIP_MAX_IO_BUF_SIZE = 64 * 1024, + MZ_ZIP_MAX_ARCHIVE_FILENAME_SIZE = 260, + MZ_ZIP_MAX_ARCHIVE_FILE_COMMENT_SIZE = 256 +}; + +typedef struct { + mz_uint32 m_file_index; + mz_uint32 m_central_dir_ofs; + mz_uint16 m_version_made_by; + mz_uint16 m_version_needed; + mz_uint16 m_bit_flag; + mz_uint16 m_method; +#ifndef MINIZ_NO_TIME + time_t m_time; +#endif + mz_uint32 m_crc32; + mz_uint64 m_comp_size; + mz_uint64 m_uncomp_size; + mz_uint16 m_internal_attr; + mz_uint32 m_external_attr; + mz_uint64 m_local_header_ofs; + mz_uint32 m_comment_size; + char m_filename[MZ_ZIP_MAX_ARCHIVE_FILENAME_SIZE]; + char m_comment[MZ_ZIP_MAX_ARCHIVE_FILE_COMMENT_SIZE]; +} mz_zip_archive_file_stat; + +typedef size_t (*mz_file_read_func)(void *pOpaque, mz_uint64 file_ofs, void *pBuf, size_t n); +typedef size_t (*mz_file_write_func)(void *pOpaque, mz_uint64 file_ofs, const void *pBuf, size_t n); + +struct mz_zip_internal_state_tag; +typedef struct mz_zip_internal_state_tag mz_zip_internal_state; + +typedef enum { + MZ_ZIP_MODE_INVALID = 0, + MZ_ZIP_MODE_READING = 1, + MZ_ZIP_MODE_WRITING = 2, + MZ_ZIP_MODE_WRITING_HAS_BEEN_FINALIZED = 3 +} mz_zip_mode; + +typedef struct mz_zip_archive_tag { + mz_uint64 m_archive_size; + mz_uint64 m_central_directory_file_ofs; + mz_uint m_total_files; + mz_zip_mode m_zip_mode; + + mz_uint m_file_offset_alignment; + + mz_alloc_func m_pAlloc; + mz_free_func m_pFree; + mz_realloc_func m_pRealloc; + void *m_pAlloc_opaque; + + mz_file_read_func m_pRead; + mz_file_write_func m_pWrite; + void *m_pIO_opaque; + + mz_zip_internal_state *m_pState; + +} mz_zip_archive; + +typedef enum { + MZ_ZIP_FLAG_CASE_SENSITIVE = 0x0100, + MZ_ZIP_FLAG_IGNORE_PATH = 0x0200, + MZ_ZIP_FLAG_COMPRESSED_DATA = 0x0400, + MZ_ZIP_FLAG_DO_NOT_SORT_CENTRAL_DIRECTORY = 0x0800 +} mz_zip_flags; + +// ZIP archive reading + +// Inits a ZIP archive reader. +// These functions read and validate the archive's central directory. +mz_bool mz_zip_reader_init(mz_zip_archive *pZip, mz_uint64 size, mz_uint32 flags); +mz_bool mz_zip_reader_init_mem(mz_zip_archive *pZip, const void *pMem, size_t size, mz_uint32 flags); + +#ifndef MINIZ_NO_STDIO +mz_bool mz_zip_reader_init_file(mz_zip_archive *pZip, const char *pFilename, mz_uint32 flags); +#endif + +// Returns the total number of files in the archive. +mz_uint mz_zip_reader_get_num_files(mz_zip_archive *pZip); + +// Returns detailed information about an archive file entry. +mz_bool mz_zip_reader_file_stat(mz_zip_archive *pZip, mz_uint file_index, mz_zip_archive_file_stat *pStat); + +// Determines if an archive file entry is a directory entry. +mz_bool mz_zip_reader_is_file_a_directory(mz_zip_archive *pZip, mz_uint file_index); +mz_bool mz_zip_reader_is_file_encrypted(mz_zip_archive *pZip, mz_uint file_index); + +// Retrieves the filename of an archive file entry. +// Returns the number of bytes written to pFilename, or if filename_buf_size is 0 this function returns the number of bytes needed to fully store the filename. +mz_uint mz_zip_reader_get_filename(mz_zip_archive *pZip, mz_uint file_index, char *pFilename, mz_uint filename_buf_size); + +// Attempts to locates a file in the archive's central directory. +// Valid flags: MZ_ZIP_FLAG_CASE_SENSITIVE, MZ_ZIP_FLAG_IGNORE_PATH +// Returns -1 if the file cannot be found. +int mz_zip_reader_locate_file(mz_zip_archive *pZip, const char *pName, const char *pComment, mz_uint flags); + +// Extracts a archive file to a memory buffer using no memory allocation. +mz_bool mz_zip_reader_extract_to_mem_no_alloc(mz_zip_archive *pZip, mz_uint file_index, void *pBuf, size_t buf_size, mz_uint flags, void *pUser_read_buf, size_t user_read_buf_size); +mz_bool mz_zip_reader_extract_file_to_mem_no_alloc(mz_zip_archive *pZip, const char *pFilename, void *pBuf, size_t buf_size, mz_uint flags, void *pUser_read_buf, size_t user_read_buf_size); + +// Extracts a archive file to a memory buffer. +mz_bool mz_zip_reader_extract_to_mem(mz_zip_archive *pZip, mz_uint file_index, void *pBuf, size_t buf_size, mz_uint flags); +mz_bool mz_zip_reader_extract_file_to_mem(mz_zip_archive *pZip, const char *pFilename, void *pBuf, size_t buf_size, mz_uint flags); + +// Extracts a archive file to a dynamically allocated heap buffer. +void *mz_zip_reader_extract_to_heap(mz_zip_archive *pZip, mz_uint file_index, size_t *pSize, mz_uint flags); +void *mz_zip_reader_extract_file_to_heap(mz_zip_archive *pZip, const char *pFilename, size_t *pSize, mz_uint flags); + +// Extracts a archive file using a callback function to output the file's data. +mz_bool mz_zip_reader_extract_to_callback(mz_zip_archive *pZip, mz_uint file_index, mz_file_write_func pCallback, void *pOpaque, mz_uint flags); +mz_bool mz_zip_reader_extract_file_to_callback(mz_zip_archive *pZip, const char *pFilename, mz_file_write_func pCallback, void *pOpaque, mz_uint flags); + +#ifndef MINIZ_NO_STDIO +// Extracts a archive file to a disk file and sets its last accessed and modified times. +// This function only extracts files, not archive directory records. +mz_bool mz_zip_reader_extract_to_file(mz_zip_archive *pZip, mz_uint file_index, const char *pDst_filename, mz_uint flags); +mz_bool mz_zip_reader_extract_file_to_file(mz_zip_archive *pZip, const char *pArchive_filename, const char *pDst_filename, mz_uint flags); +#endif + +// Ends archive reading, freeing all allocations, and closing the input archive file if mz_zip_reader_init_file() was used. +mz_bool mz_zip_reader_end(mz_zip_archive *pZip); + +// ZIP archive writing + +#ifndef MINIZ_NO_ARCHIVE_WRITING_APIS + +// Inits a ZIP archive writer. +mz_bool mz_zip_writer_init(mz_zip_archive *pZip, mz_uint64 existing_size); +mz_bool mz_zip_writer_init_heap(mz_zip_archive *pZip, size_t size_to_reserve_at_beginning, size_t initial_allocation_size); + +#ifndef MINIZ_NO_STDIO +mz_bool mz_zip_writer_init_file(mz_zip_archive *pZip, const char *pFilename, mz_uint64 size_to_reserve_at_beginning); +#endif + +// Converts a ZIP archive reader object into a writer object, to allow efficient in-place file appends to occur on an existing archive. +// For archives opened using mz_zip_reader_init_file, pFilename must be the archive's filename so it can be reopened for writing. If the file can't be reopened, mz_zip_reader_end() will be called. +// For archives opened using mz_zip_reader_init_mem, the memory block must be growable using the realloc callback (which defaults to realloc unless you've overridden it). +// Finally, for archives opened using mz_zip_reader_init, the mz_zip_archive's user provided m_pWrite function cannot be NULL. +// Note: In-place archive modification is not recommended unless you know what you're doing, because if execution stops or something goes wrong before +// the archive is finalized the file's central directory will be hosed. +mz_bool mz_zip_writer_init_from_reader(mz_zip_archive *pZip, const char *pFilename); + +// Adds the contents of a memory buffer to an archive. These functions record the current local time into the archive. +// To add a directory entry, call this method with an archive name ending in a forwardslash with empty buffer. +// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION. +mz_bool mz_zip_writer_add_mem(mz_zip_archive *pZip, const char *pArchive_name, const void *pBuf, size_t buf_size, mz_uint level_and_flags); +mz_bool mz_zip_writer_add_mem_ex(mz_zip_archive *pZip, const char *pArchive_name, const void *pBuf, size_t buf_size, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags, mz_uint64 uncomp_size, mz_uint32 uncomp_crc32); + +#ifndef MINIZ_NO_STDIO +// Adds the contents of a disk file to an archive. This function also records the disk file's modified time into the archive. +// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION. +mz_bool mz_zip_writer_add_file(mz_zip_archive *pZip, const char *pArchive_name, const char *pSrc_filename, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags); +#endif + +// Adds a file to an archive by fully cloning the data from another archive. +// This function fully clones the source file's compressed data (no recompression), along with its full filename, extra data, and comment fields. +mz_bool mz_zip_writer_add_from_zip_reader(mz_zip_archive *pZip, mz_zip_archive *pSource_zip, mz_uint file_index); + +// Finalizes the archive by writing the central directory records followed by the end of central directory record. +// After an archive is finalized, the only valid call on the mz_zip_archive struct is mz_zip_writer_end(). +// An archive must be manually finalized by calling this function for it to be valid. +mz_bool mz_zip_writer_finalize_archive(mz_zip_archive *pZip); +mz_bool mz_zip_writer_finalize_heap_archive(mz_zip_archive *pZip, void **pBuf, size_t *pSize); + +// Ends archive writing, freeing all allocations, and closing the output file if mz_zip_writer_init_file() was used. +// Note for the archive to be valid, it must have been finalized before ending. +mz_bool mz_zip_writer_end(mz_zip_archive *pZip); + +// Misc. high-level helper functions: + +// mz_zip_add_mem_to_archive_file_in_place() efficiently (but not atomically) appends a memory blob to a ZIP archive. +// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION. +mz_bool mz_zip_add_mem_to_archive_file_in_place(const char *pZip_filename, const char *pArchive_name, const void *pBuf, size_t buf_size, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags); + +// Reads a single file from an archive into a heap block. +// Returns NULL on failure. +void *mz_zip_extract_archive_file_to_heap(const char *pZip_filename, const char *pArchive_name, size_t *pSize, mz_uint zip_flags); + +#endif // #ifndef MINIZ_NO_ARCHIVE_WRITING_APIS + +#endif // #ifndef MINIZ_NO_ARCHIVE_APIS + +// ------------------- Low-level Decompression API Definitions + +// Decompression flags used by tinfl_decompress(). +// TINFL_FLAG_PARSE_ZLIB_HEADER: If set, the input has a valid zlib header and ends with an adler32 checksum (it's a valid zlib stream). Otherwise, the input is a raw deflate stream. +// TINFL_FLAG_HAS_MORE_INPUT: If set, there are more input bytes available beyond the end of the supplied input buffer. If clear, the input buffer contains all remaining input. +// TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF: If set, the output buffer is large enough to hold the entire decompressed stream. If clear, the output buffer is at least the size of the dictionary (typically 32KB). +// TINFL_FLAG_COMPUTE_ADLER32: Force adler-32 checksum computation of the decompressed bytes. +enum { + TINFL_FLAG_PARSE_ZLIB_HEADER = 1, + TINFL_FLAG_HAS_MORE_INPUT = 2, + TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF = 4, + TINFL_FLAG_COMPUTE_ADLER32 = 8 +}; + +// High level decompression functions: +// tinfl_decompress_mem_to_heap() decompresses a block in memory to a heap block allocated via malloc(). +// On entry: +// pSrc_buf, src_buf_len: Pointer and size of the Deflate or zlib source data to decompress. +// On return: +// Function returns a pointer to the decompressed data, or NULL on failure. +// *pOut_len will be set to the decompressed data's size, which could be larger than src_buf_len on uncompressible data. +// The caller must call mz_free() on the returned block when it's no longer needed. +void *tinfl_decompress_mem_to_heap(const void *pSrc_buf, size_t src_buf_len, size_t *pOut_len, int flags); + +// tinfl_decompress_mem_to_mem() decompresses a block in memory to another block in memory. +// Returns TINFL_DECOMPRESS_MEM_TO_MEM_FAILED on failure, or the number of bytes written on success. +#define TINFL_DECOMPRESS_MEM_TO_MEM_FAILED ((size_t)(-1)) +size_t tinfl_decompress_mem_to_mem(void *pOut_buf, size_t out_buf_len, const void *pSrc_buf, size_t src_buf_len, int flags); + +// tinfl_decompress_mem_to_callback() decompresses a block in memory to an internal 32KB buffer, and a user provided callback function will be called to flush the buffer. +// Returns 1 on success or 0 on failure. +typedef int (*tinfl_put_buf_func_ptr)(const void *pBuf, int len, void *pUser); +int tinfl_decompress_mem_to_callback(const void *pIn_buf, size_t *pIn_buf_size, tinfl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags); + +struct tinfl_decompressor_tag; typedef struct tinfl_decompressor_tag tinfl_decompressor; + +// Max size of LZ dictionary. +#define TINFL_LZ_DICT_SIZE 32768 + +// Return status. +typedef enum { + TINFL_STATUS_BAD_PARAM = -3, + TINFL_STATUS_ADLER32_MISMATCH = -2, + TINFL_STATUS_FAILED = -1, + TINFL_STATUS_DONE = 0, + TINFL_STATUS_NEEDS_MORE_INPUT = 1, + TINFL_STATUS_HAS_MORE_OUTPUT = 2 +} tinfl_status; + +// Initializes the decompressor to its initial state. +#define tinfl_init(r) do { (r)->m_state = 0; } MZ_MACRO_END +#define tinfl_get_adler32(r) (r)->m_check_adler32 + +// Main low-level decompressor coroutine function. This is the only function actually needed for decompression. All the other functions are just high-level helpers for improved usability. +// This is a universal API, i.e. it can be used as a building block to build any desired higher level decompression API. In the limit case, it can be called once per every byte input or output. +tinfl_status tinfl_decompress(tinfl_decompressor *r, const mz_uint8 *pIn_buf_next, size_t *pIn_buf_size, mz_uint8 *pOut_buf_start, mz_uint8 *pOut_buf_next, size_t *pOut_buf_size, const mz_uint32 decomp_flags); + +// Internal/private bits follow. +enum { + TINFL_MAX_HUFF_TABLES = 3, TINFL_MAX_HUFF_SYMBOLS_0 = 288, TINFL_MAX_HUFF_SYMBOLS_1 = 32, TINFL_MAX_HUFF_SYMBOLS_2 = 19, + TINFL_FAST_LOOKUP_BITS = 10, TINFL_FAST_LOOKUP_SIZE = 1 << TINFL_FAST_LOOKUP_BITS +}; + +typedef struct { + mz_uint8 m_code_size[TINFL_MAX_HUFF_SYMBOLS_0]; + mz_int16 m_look_up[TINFL_FAST_LOOKUP_SIZE], m_tree[TINFL_MAX_HUFF_SYMBOLS_0 * 2]; +} tinfl_huff_table; + +#if MINIZ_HAS_64BIT_REGISTERS +#define TINFL_USE_64BIT_BITBUF 1 +#endif + +#if TINFL_USE_64BIT_BITBUF +typedef mz_uint64 tinfl_bit_buf_t; +#define TINFL_BITBUF_SIZE (64) +#else +typedef mz_uint32 tinfl_bit_buf_t; +#define TINFL_BITBUF_SIZE (32) +#endif + +struct tinfl_decompressor_tag { + mz_uint32 m_state, m_num_bits, m_zhdr0, m_zhdr1, m_z_adler32, m_final, m_type, m_check_adler32, m_dist, m_counter, m_num_extra, m_table_sizes[TINFL_MAX_HUFF_TABLES]; + tinfl_bit_buf_t m_bit_buf; + size_t m_dist_from_out_buf_start; + tinfl_huff_table m_tables[TINFL_MAX_HUFF_TABLES]; + mz_uint8 m_raw_header[4], m_len_codes[TINFL_MAX_HUFF_SYMBOLS_0 + TINFL_MAX_HUFF_SYMBOLS_1 + 137]; +}; + +// ------------------- Low-level Compression API Definitions + +// Set TDEFL_LESS_MEMORY to 1 to use less memory (compression will be slightly slower, and raw/dynamic blocks will be output more frequently). +#define TDEFL_LESS_MEMORY 1 + +// tdefl_init() compression flags logically OR'd together (low 12 bits contain the max. number of probes per dictionary search): +// TDEFL_DEFAULT_MAX_PROBES: The compressor defaults to 128 dictionary probes per dictionary search. 0=Huffman only, 1=Huffman+LZ (fastest/crap compression), 4095=Huffman+LZ (slowest/best compression). +enum { + TDEFL_HUFFMAN_ONLY = 0, TDEFL_DEFAULT_MAX_PROBES = 128, TDEFL_MAX_PROBES_MASK = 0xFFF +}; + +// TDEFL_WRITE_ZLIB_HEADER: If set, the compressor outputs a zlib header before the deflate data, and the Adler-32 of the source data at the end. Otherwise, you'll get raw deflate data. +// TDEFL_COMPUTE_ADLER32: Always compute the adler-32 of the input data (even when not writing zlib headers). +// TDEFL_GREEDY_PARSING_FLAG: Set to use faster greedy parsing, instead of more efficient lazy parsing. +// TDEFL_NONDETERMINISTIC_PARSING_FLAG: Enable to decrease the compressor's initialization time to the minimum, but the output may vary from run to run given the same input (depending on the contents of memory). +// TDEFL_RLE_MATCHES: Only look for RLE matches (matches with a distance of 1) +// TDEFL_FILTER_MATCHES: Discards matches <= 5 chars if enabled. +// TDEFL_FORCE_ALL_STATIC_BLOCKS: Disable usage of optimized Huffman tables. +// TDEFL_FORCE_ALL_RAW_BLOCKS: Only use raw (uncompressed) deflate blocks. +// The low 12 bits are reserved to control the max # of hash probes per dictionary lookup (see TDEFL_MAX_PROBES_MASK). +enum { + TDEFL_WRITE_ZLIB_HEADER = 0x01000, + TDEFL_COMPUTE_ADLER32 = 0x02000, + TDEFL_GREEDY_PARSING_FLAG = 0x04000, + TDEFL_NONDETERMINISTIC_PARSING_FLAG = 0x08000, + TDEFL_RLE_MATCHES = 0x10000, + TDEFL_FILTER_MATCHES = 0x20000, + TDEFL_FORCE_ALL_STATIC_BLOCKS = 0x40000, + TDEFL_FORCE_ALL_RAW_BLOCKS = 0x80000 +}; + +// High level compression functions: +// tdefl_compress_mem_to_heap() compresses a block in memory to a heap block allocated via malloc(). +// On entry: +// pSrc_buf, src_buf_len: Pointer and size of source block to compress. +// flags: The max match finder probes (default is 128) logically OR'd against the above flags. Higher probes are slower but improve compression. +// On return: +// Function returns a pointer to the compressed data, or NULL on failure. +// *pOut_len will be set to the compressed data's size, which could be larger than src_buf_len on uncompressible data. +// The caller must free() the returned block when it's no longer needed. +void *tdefl_compress_mem_to_heap(const void *pSrc_buf, size_t src_buf_len, size_t *pOut_len, int flags); + +// tdefl_compress_mem_to_mem() compresses a block in memory to another block in memory. +// Returns 0 on failure. +size_t tdefl_compress_mem_to_mem(void *pOut_buf, size_t out_buf_len, const void *pSrc_buf, size_t src_buf_len, int flags); + +// Compresses an image to a compressed PNG file in memory. +// On entry: +// pImage, w, h, and num_chans describe the image to compress. num_chans may be 1, 2, 3, or 4. +// The image pitch in bytes per scanline will be w*num_chans. The leftmost pixel on the top scanline is stored first in memory. +// level may range from [0,10], use MZ_NO_COMPRESSION, MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc. or a decent default is MZ_DEFAULT_LEVEL +// If flip is true, the image will be flipped on the Y axis (useful for OpenGL apps). +// On return: +// Function returns a pointer to the compressed data, or NULL on failure. +// *pLen_out will be set to the size of the PNG image file. +// The caller must mz_free() the returned heap block (which will typically be larger than *pLen_out) when it's no longer needed. +void *tdefl_write_image_to_png_file_in_memory_ex(const void *pImage, int w, int h, int num_chans, size_t *pLen_out, mz_uint level, mz_bool flip); +void *tdefl_write_image_to_png_file_in_memory(const void *pImage, int w, int h, int num_chans, size_t *pLen_out); + +// Output stream interface. The compressor uses this interface to write compressed data. It'll typically be called TDEFL_OUT_BUF_SIZE at a time. +typedef mz_bool (*tdefl_put_buf_func_ptr)(const void *pBuf, int len, void *pUser); + +// tdefl_compress_mem_to_output() compresses a block to an output stream. The above helpers use this function internally. +mz_bool tdefl_compress_mem_to_output(const void *pBuf, size_t buf_len, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags); + +enum { TDEFL_MAX_HUFF_TABLES = 3, TDEFL_MAX_HUFF_SYMBOLS_0 = 288, TDEFL_MAX_HUFF_SYMBOLS_1 = 32, TDEFL_MAX_HUFF_SYMBOLS_2 = 19, TDEFL_LZ_DICT_SIZE = 32768, TDEFL_LZ_DICT_SIZE_MASK = TDEFL_LZ_DICT_SIZE - 1, TDEFL_MIN_MATCH_LEN = 3, TDEFL_MAX_MATCH_LEN = 258 }; + +// TDEFL_OUT_BUF_SIZE MUST be large enough to hold a single entire compressed output block (using static/fixed Huffman codes). +#if TDEFL_LESS_MEMORY +enum { TDEFL_LZ_CODE_BUF_SIZE = 24 * 1024, TDEFL_OUT_BUF_SIZE = (TDEFL_LZ_CODE_BUF_SIZE * 13 ) / 10, TDEFL_MAX_HUFF_SYMBOLS = 288, TDEFL_LZ_HASH_BITS = 12, TDEFL_LEVEL1_HASH_SIZE_MASK = 4095, TDEFL_LZ_HASH_SHIFT = (TDEFL_LZ_HASH_BITS + 2) / 3, TDEFL_LZ_HASH_SIZE = 1 << TDEFL_LZ_HASH_BITS }; +#else +enum { TDEFL_LZ_CODE_BUF_SIZE = 64 * 1024, TDEFL_OUT_BUF_SIZE = (TDEFL_LZ_CODE_BUF_SIZE * 13 ) / 10, TDEFL_MAX_HUFF_SYMBOLS = 288, TDEFL_LZ_HASH_BITS = 15, TDEFL_LEVEL1_HASH_SIZE_MASK = 4095, TDEFL_LZ_HASH_SHIFT = (TDEFL_LZ_HASH_BITS + 2) / 3, TDEFL_LZ_HASH_SIZE = 1 << TDEFL_LZ_HASH_BITS }; +#endif + +// The low-level tdefl functions below may be used directly if the above helper functions aren't flexible enough. The low-level functions don't make any heap allocations, unlike the above helper functions. +typedef enum { + TDEFL_STATUS_BAD_PARAM = -2, + TDEFL_STATUS_PUT_BUF_FAILED = -1, + TDEFL_STATUS_OKAY = 0, + TDEFL_STATUS_DONE = 1, +} tdefl_status; + +// Must map to MZ_NO_FLUSH, MZ_SYNC_FLUSH, etc. enums +typedef enum { + TDEFL_NO_FLUSH = 0, + TDEFL_SYNC_FLUSH = 2, + TDEFL_FULL_FLUSH = 3, + TDEFL_FINISH = 4 +} tdefl_flush; + +// tdefl's compression state structure. +typedef struct { + tdefl_put_buf_func_ptr m_pPut_buf_func; + void *m_pPut_buf_user; + mz_uint m_flags, m_max_probes[2]; + int m_greedy_parsing; + mz_uint m_adler32, m_lookahead_pos, m_lookahead_size, m_dict_size; + mz_uint8 *m_pLZ_code_buf, *m_pLZ_flags, *m_pOutput_buf, *m_pOutput_buf_end; + mz_uint m_num_flags_left, m_total_lz_bytes, m_lz_code_buf_dict_pos, m_bits_in, m_bit_buffer; + mz_uint m_saved_match_dist, m_saved_match_len, m_saved_lit, m_output_flush_ofs, m_output_flush_remaining, m_finished, m_block_index, m_wants_to_finish; + tdefl_status m_prev_return_status; + const void *m_pIn_buf; + void *m_pOut_buf; + size_t *m_pIn_buf_size, *m_pOut_buf_size; + tdefl_flush m_flush; + const mz_uint8 *m_pSrc; + size_t m_src_buf_left, m_out_buf_ofs; + mz_uint8 m_dict[TDEFL_LZ_DICT_SIZE + TDEFL_MAX_MATCH_LEN - 1]; + mz_uint16 m_huff_count[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS]; + mz_uint16 m_huff_codes[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS]; + mz_uint8 m_huff_code_sizes[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS]; + mz_uint8 m_lz_code_buf[TDEFL_LZ_CODE_BUF_SIZE]; + mz_uint16 m_next[TDEFL_LZ_DICT_SIZE]; + mz_uint16 m_hash[TDEFL_LZ_HASH_SIZE]; + mz_uint8 m_output_buf[TDEFL_OUT_BUF_SIZE]; +} tdefl_compressor; + +// Initializes the compressor. +// There is no corresponding deinit() function because the tdefl API's do not dynamically allocate memory. +// pBut_buf_func: If **not** NULL, output data will be supplied to the specified callback. In this case, the user should call the tdefl_compress_buffer() API for compression. +// If pBut_buf_func is NULL the user should always call the tdefl_compress() API. +// flags: See the above enums (TDEFL_HUFFMAN_ONLY, TDEFL_WRITE_ZLIB_HEADER, etc.) +tdefl_status tdefl_init(tdefl_compressor *d, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags); + +// Compresses a block of data, consuming as much of the specified input buffer as possible, and writing as much compressed data to the specified output buffer as possible. +tdefl_status tdefl_compress(tdefl_compressor *d, const void *pIn_buf, size_t *pIn_buf_size, void *pOut_buf, size_t *pOut_buf_size, tdefl_flush flush); + +// tdefl_compress_buffer() is only usable when the tdefl_init() is called with a non-NULL tdefl_put_buf_func_ptr. +// tdefl_compress_buffer() always consumes the entire input buffer. +tdefl_status tdefl_compress_buffer(tdefl_compressor *d, const void *pIn_buf, size_t in_buf_size, tdefl_flush flush); + +tdefl_status tdefl_get_prev_return_status(tdefl_compressor *d); +mz_uint32 tdefl_get_adler32(tdefl_compressor *d); + +// Can't use tdefl_create_comp_flags_from_zip_params if MINIZ_NO_ZLIB_APIS isn't defined, because it uses some of its macros. +#ifndef MINIZ_NO_ZLIB_APIS +// Create tdefl_compress() flags given zlib-style compression parameters. +// level may range from [0,10] (where 10 is absolute max compression, but may be much slower on some files) +// window_bits may be -15 (raw deflate) or 15 (zlib) +// strategy may be either MZ_DEFAULT_STRATEGY, MZ_FILTERED, MZ_HUFFMAN_ONLY, MZ_RLE, or MZ_FIXED +mz_uint tdefl_create_comp_flags_from_zip_params(int level, int window_bits, int strategy); +#endif // #ifndef MINIZ_NO_ZLIB_APIS + +#ifdef __cplusplus +} +#endif + +#endif // MINIZ_HEADER_INCLUDED diff --git a/components/esp_rom/include/esp32c6/rom/rom_layout.h b/components/esp_rom/include/esp32c6/rom/rom_layout.h new file mode 100644 index 0000000000..0775a366a0 --- /dev/null +++ b/components/esp_rom/include/esp32c6/rom/rom_layout.h @@ -0,0 +1,95 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SUPPORT_BTDM 1 +#define SUPPORT_BTBB 1 +#define SUPPORT_WIFI 1 +#define SUPPORT_USB_DEVICE 1 +#define SUPPORT_COEXIST 1 + +/* Structure and functions for returning ROM global layout + * + * This is for address symbols defined in the linker script, which may change during ECOs. + */ +typedef struct { + void *dram0_stack_shared_mem_start; + void *dram0_rtos_reserved_start; + void *stack_sentry; + void *stack; + +#if SUPPORT_BTDM + void *data_start_btdm; + void *data_end_btdm; + void *bss_start_btdm; + void *bss_end_btdm; + void *data_start_btdm_rom; + void *data_start_interface_btdm; + void *data_end_interface_btdm; + void *bss_start_interface_btdm; + void *bss_end_interface_btdm; +#endif + +#if SUPPORT_BTBB + void *dram_start_btbbrom; + void *dram_end_btbbrom; +#endif + +#if SUPPORT_BTDM || SUPPORT_WIFI + void *dram_start_phyrom; + void *dram_end_phyrom; +#endif + +#if SUPPORT_WIFI + void *dram_start_net80211; + void *dram_end_net80211; + void *data_start_interface_net80211; + void *data_end_interface_net80211; + void *bss_start_interface_net80211; + void *bss_end_interface_net80211; + void *dram_start_pp; + void *dram_end_pp; + void *data_start_interface_pp; + void *data_end_interface_pp; + void *bss_start_interface_pp; + void *bss_end_interface_pp; +#endif + +#if SUPPORT_COEXIST + void *dram_start_coexist; + void *dram_end_coexist; + void *data_start_interface_coexist; + void *data_end_interface_coexist; + void *bss_start_interface_coexist; + void *bss_end_interface_coexist; +#endif + +#if SUPPORT_MBEDTLS + void *dram_start_mbedtls_rom; + void *dram_end_mbedtls_rom; +#endif + +#if SUPPORT_USB_DEVICE + void *dram_start_usbdev_rom; + void *dram_end_usbdev_rom; +#endif + + void *dram_start_uart_rom; + void *dram_end_uart_rom; +} ets_rom_layout_t; + +extern const ets_rom_layout_t *const ets_rom_layout_p; + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/include/esp32c6/rom/rsa_pss.h b/components/esp_rom/include/esp32c6/rom/rsa_pss.h new file mode 100644 index 0000000000..d6140879c8 --- /dev/null +++ b/components/esp_rom/include/esp32c6/rom/rsa_pss.h @@ -0,0 +1,38 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_RSA_PSS_H_ +#define _ROM_RSA_PSS_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define ETS_SIG_LEN 384 /* Bytes */ +#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */ + +typedef struct { + uint8_t n[384]; /* Public key modulus */ + uint32_t e; /* Public key exponent */ + uint8_t rinv[384]; + uint32_t mdash; +} ets_rsa_pubkey_t; + +bool ets_rsa_pss_verify(const ets_rsa_pubkey_t *key, const uint8_t *sig, const uint8_t *digest, uint8_t *verified_digest); + +void ets_mgf1_sha256(const uint8_t *mgfSeed, size_t seedLen, size_t maskLen, uint8_t *mask); + +bool ets_emsa_pss_verify(const uint8_t *encoded_message, const uint8_t *mhash); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/components/esp_rom/include/esp32c6/rom/rtc.h b/components/esp_rom/include/esp32c6/rom/rtc.h new file mode 100644 index 0000000000..c466382863 --- /dev/null +++ b/components/esp_rom/include/esp32c6/rom/rtc.h @@ -0,0 +1,255 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_RTC_H_ +#define _ROM_RTC_H_ + +#include "ets_sys.h" + +#include +#include + +#include "soc/soc.h" +#include "soc/lp_aon_reg.h" +#include "soc/reset_reasons.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup rtc_apis, rtc registers and memory related apis + * @brief rtc apis + */ + +/** @addtogroup rtc_apis + * @{ + */ + +/************************************************************************************** + * Note: * + * Some Rtc memory and registers are used, in ROM or in internal library. * + * Please do not use reserved or used rtc memory or registers. * + * * + ************************************************************************************* + * RTC Memory & Store Register usage + ************************************************************************************* + * rtc memory addr type size usage + * 0x3f421000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry + * 0x3f421000+SIZE_CP Slow 8192-SIZE_CP + * + * 0x3ff80000(0x40070000) Fast 8192 deep sleep entry code + * + ************************************************************************************* + * RTC store registers usage + * RTC_CNTL_STORE0_REG Reserved + * RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value + * RTC_CNTL_STORE2_REG Boot time, low word + * RTC_CNTL_STORE3_REG Boot time, high word + * RTC_CNTL_STORE4_REG External XTAL frequency + * RTC_CNTL_STORE5_REG APB bus frequency + * RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY + * RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC + ************************************************************************************* + */ + +#define RTC_SLOW_CLK_CAL_REG LP_AON_STORE1_REG +#define RTC_BOOT_TIME_LOW_REG LP_AON_STORE2_REG +#define RTC_BOOT_TIME_HIGH_REG LP_AON_STORE3_REG +#define RTC_XTAL_FREQ_REG LP_AON_STORE4_REG +#define RTC_APB_FREQ_REG LP_AON_STORE5_REG +#define RTC_ENTRY_ADDR_REG LP_AON_STORE6_REG +#define RTC_RESET_CAUSE_REG LP_AON_STORE6_REG +#define RTC_MEMORY_CRC_REG LP_AON_STORE7_REG + +#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code. + + +typedef enum { + AWAKE = 0, // +#include +#include "ets_sys.h" +#include "rsa_pss.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct ets_secure_boot_sig_block ets_secure_boot_sig_block_t; +typedef struct ets_secure_boot_signature ets_secure_boot_signature_t; +typedef struct ets_secure_boot_key_digests ets_secure_boot_key_digests_t; + +/* Anti-FI measure: use full words for success/fail, instead of + 0/non-zero +*/ +typedef enum { + SB_SUCCESS = 0x3A5A5AA5, + SB_FAILED = 0x7533885E, +} ets_secure_boot_status_t; + + +/* Verify and stage-load the bootloader image + (reconfigures cache to map, loads trusted key digests from efuse, + copies the bootloader into the staging buffer.) + + If allow_key_revoke is true and aggressive revoke efuse is set, + any failed signature has its associated key revoked in efuse. + + If result is SB_SUCCESS, the "simple hash" of the bootloader + is copied into verified_hash. +*/ +ets_secure_boot_status_t ets_secure_boot_verify_stage_bootloader(uint8_t *verified_hash, bool allow_key_revoke); + +/* Verify bootloader image (reconfigures cache to map), + with key digests provided as parameters.) + + Can be used to verify secure boot status before enabling + secure boot permanently. + + If stage_load parameter is true, bootloader is copied into staging + buffer in RAM at the same time. + + If result is SB_SUCCESS, the "simple hash" of the bootloader is + copied into verified_hash. +*/ +ets_secure_boot_status_t ets_secure_boot_verify_bootloader_with_keys(uint8_t *verified_hash, const ets_secure_boot_key_digests_t *trusted_keys, bool stage_load); + +/* Read key digests from efuse. Any revoked/missing digests will be + marked as NULL +*/ +ETS_STATUS ets_secure_boot_read_key_digests(ets_secure_boot_key_digests_t *trusted_keys); + +/* Verify supplied signature against supplied digest, using + supplied trusted key digests. + + Doesn't reconfigure cache or any other hardware access except for RSA peripheral. + + If result is SB_SUCCESS, the image_digest value is copied into verified_digest. +*/ +ets_secure_boot_status_t ets_secure_boot_verify_signature(const ets_secure_boot_signature_t *sig, const uint8_t *image_digest, const ets_secure_boot_key_digests_t *trusted_keys, uint8_t *verified_digest); + +/* Revoke a public key digest in efuse. + @param index Digest to revoke. Must be 0, 1 or 2. + */ +void ets_secure_boot_revoke_public_key_digest(int index); + +#define CRC_SIGN_BLOCK_LEN 1196 +#define SIG_BLOCK_PADDING 4096 +#define ETS_SECURE_BOOT_V2_SIGNATURE_MAGIC 0xE7 + +/* Secure Boot V2 signature block + + (Up to 3 in a signature sector are appended to the image) + */ +struct ets_secure_boot_sig_block { + uint8_t magic_byte; + uint8_t version; + uint8_t _reserved1; + uint8_t _reserved2; + uint8_t image_digest[32]; + ets_rsa_pubkey_t key; + uint8_t signature[384]; + uint32_t block_crc; + uint8_t _padding[16]; +}; + +_Static_assert(sizeof(ets_secure_boot_sig_block_t) == 1216, "invalid sig block size"); + +#define SECURE_BOOT_NUM_BLOCKS 3 + +/* V2 Secure boot signature sector (up to 3 blocks) */ +struct ets_secure_boot_signature { + ets_secure_boot_sig_block_t block[SECURE_BOOT_NUM_BLOCKS]; + uint8_t _padding[4096 - (sizeof(ets_secure_boot_sig_block_t) * SECURE_BOOT_NUM_BLOCKS)]; +}; + +_Static_assert(sizeof(ets_secure_boot_signature_t) == 4096, "invalid sig sector size"); + +#define MAX_KEY_DIGESTS 3 + +struct ets_secure_boot_key_digests { + const void *key_digests[MAX_KEY_DIGESTS]; + bool allow_key_revoke; +}; + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/include/esp32c6/rom/sha.h b/components/esp_rom/include/esp32c6/rom/sha.h new file mode 100644 index 0000000000..c9eda2fd99 --- /dev/null +++ b/components/esp_rom/include/esp32c6/rom/sha.h @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _ROM_SHA_H_ +#define _ROM_SHA_H_ + +#include +#include +#include "ets_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + SHA1 = 0, + SHA2_224, + SHA2_256, + SHA_TYPE_MAX +} SHA_TYPE; + +typedef struct SHAContext { + bool start; + bool in_hardware; // Is this context currently in peripheral? Needs to be manually cleared if multiple SHAs are interleaved + SHA_TYPE type; + uint32_t state[16]; // For SHA1/SHA224/SHA256, used 8, other used 16 + unsigned char buffer[128]; // For SHA1/SHA224/SHA256, used 64, other used 128 + uint32_t total_bits[4]; +} SHA_CTX; + +void ets_sha_enable(void); + +void ets_sha_disable(void); + +ets_status_t ets_sha_init(SHA_CTX *ctx, SHA_TYPE type); + +ets_status_t ets_sha_starts(SHA_CTX *ctx, uint16_t sha512_t); + +void ets_sha_get_state(SHA_CTX *ctx); + +void ets_sha_process(SHA_CTX *ctx, const unsigned char *input); + +void ets_sha_update(SHA_CTX *ctx, const unsigned char *input, uint32_t input_bytes, bool update_ctx); + +ets_status_t ets_sha_finish(SHA_CTX *ctx, unsigned char *output); + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_SHA_H_ */ diff --git a/components/esp_rom/include/esp32c6/rom/spi_flash.h b/components/esp_rom/include/esp32c6/rom/spi_flash.h new file mode 100644 index 0000000000..61de15fb52 --- /dev/null +++ b/components/esp_rom/include/esp32c6/rom/spi_flash.h @@ -0,0 +1,485 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "esp_attr.h" +#include "esp_rom_spiflash.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1) +#define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1) +#define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1) +#define PERIPHS_SPI_FLASH_CTRL1 SPI_MEM_CTRL1_REG(1) +#define PERIPHS_SPI_FLASH_STATUS SPI_MEM_RD_STATUS_REG(1) +#define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1) +#define PERIPHS_SPI_FLASH_USRREG1 SPI_MEM_USER1_REG(1) +#define PERIPHS_SPI_FLASH_USRREG2 SPI_MEM_USER2_REG(1) +#define PERIPHS_SPI_FLASH_C0 SPI_MEM_W0_REG(1) +#define PERIPHS_SPI_FLASH_C1 SPI_MEM_W1_REG(1) +#define PERIPHS_SPI_FLASH_C2 SPI_MEM_W2_REG(1) +#define PERIPHS_SPI_FLASH_C3 SPI_MEM_W3_REG(1) +#define PERIPHS_SPI_FLASH_C4 SPI_MEM_W4_REG(1) +#define PERIPHS_SPI_FLASH_C5 SPI_MEM_W5_REG(1) +#define PERIPHS_SPI_FLASH_C6 SPI_MEM_W6_REG(1) +#define PERIPHS_SPI_FLASH_C7 SPI_MEM_W7_REG(1) +#define PERIPHS_SPI_FLASH_TX_CRC SPI_MEM_TX_CRC_REG(1) + +#define SPI0_R_QIO_DUMMY_CYCLELEN 5 +#define SPI0_R_QIO_ADDR_BITSLEN 23 +#define SPI0_R_FAST_DUMMY_CYCLELEN 7 +#define SPI0_R_DIO_DUMMY_CYCLELEN 3 +#define SPI0_R_FAST_ADDR_BITSLEN 23 +#define SPI0_R_SIO_ADDR_BITSLEN 23 + +#define SPI1_R_QIO_DUMMY_CYCLELEN 5 +#define SPI1_R_QIO_ADDR_BITSLEN 23 +#define SPI1_R_FAST_DUMMY_CYCLELEN 7 +#define SPI1_R_DIO_DUMMY_CYCLELEN 3 +#define SPI1_R_DIO_ADDR_BITSLEN 23 +#define SPI1_R_FAST_ADDR_BITSLEN 23 +#define SPI1_R_SIO_ADDR_BITSLEN 23 + +#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23 + +#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_MEM_WRSR_2B + +//SPI address register +#define ESP_ROM_SPIFLASH_BYTES_LEN 24 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf + +typedef void (* spi_flash_func_t)(void); +typedef esp_rom_spiflash_result_t (* spi_flash_op_t)(void); +typedef esp_rom_spiflash_result_t (* spi_flash_erase_t)(uint32_t); +typedef esp_rom_spiflash_result_t (* spi_flash_rd_t)(uint32_t, uint32_t*, int); +typedef esp_rom_spiflash_result_t (* spi_flash_wr_t)(uint32_t, const uint32_t*, int); +typedef esp_rom_spiflash_result_t (* spi_flash_ewr_t)(uint32_t, const void*, uint32_t); +typedef esp_rom_spiflash_result_t (* spi_flash_wren_t)(void*); +typedef esp_rom_spiflash_result_t (* spi_flash_erase_area_t)(uint32_t, uint32_t); + +typedef struct { + uint8_t pp_addr_bit_len; + uint8_t se_addr_bit_len; + uint8_t be_addr_bit_len; + uint8_t rd_addr_bit_len; + uint32_t read_sub_len; + uint32_t write_sub_len; + spi_flash_op_t unlock; + spi_flash_erase_t erase_sector; + spi_flash_erase_t erase_block; + spi_flash_rd_t read; + spi_flash_wr_t write; + spi_flash_ewr_t encrypt_write; + spi_flash_func_t check_sus; + spi_flash_wren_t wren; + spi_flash_op_t wait_idle; + spi_flash_erase_area_t erase_area; +} spiflash_legacy_funcs_t; + +typedef struct { + uint8_t data_length; + uint8_t read_cmd0; + uint8_t read_cmd1; + uint8_t write_cmd; + uint16_t data_mask; + uint16_t data; +} esp_rom_spiflash_common_cmd_t; + +/** + * @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode. + * Please do not call this function in SDK. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @param uint8_t legacy: always keeping false. + * + * @return None + */ +void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy); + +/** + * @brief SPI Read Flash status register. We use CMD 0x05 (RDSR). + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t *status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status); + +/** + * @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2). + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t *status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status); + +/** + * @brief Write status to Flash status register. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t status_value : Value to . + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : write OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value); + +/** + * @brief Use a command to Read Flash status register. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t*status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd); + +/** + * @brief Config SPI Flash read mode when init. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. + * + * This function does not try to set the QIO Enable bit in the status register, caller is responsible for this. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : config error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode); + +/** + * @brief Config SPI Flash clock divisor. + * Please do not call this function in SDK. + * + * @param uint8_t freqdiv: clock divisor. + * + * @param uint8_t spi: 0 for SPI0, 1 for SPI1. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : config error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi); + +/** + * @brief Clear all SR bits except QE bit. + * Please do not call this function in SDK. + * + * @param None. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_clear_bp(void); + +/** + * @brief Clear all SR bits except QE bit. + * Please do not call this function in SDK. + * + * @param None. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void); + +/** + * @brief Update SPI Flash parameter. + * Please do not call this function in SDK. + * + * @param uint32_t deviceId : Device ID read from SPI, the low 32 bit. + * + * @param uint32_t chip_size : The Flash size. + * + * @param uint32_t block_size : The Flash block size. + * + * @param uint32_t sector_size : The Flash sector size. + * + * @param uint32_t page_size : The Flash page size. + * + * @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD). + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Update error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, + uint32_t sector_size, uint32_t page_size, uint32_t status_mask); + +/** + * @brief Erase whole flash chip. + * Please do not call this function in SDK. + * + * @param None + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void); + +/** + * @brief Erase a 64KB block of flash + * Uses SPI flash command D8H. + * Please do not call this function in SDK. + * + * @param uint32_t block_num : Which block to erase. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num); + +/** + * @brief Erase a sector of flash. + * Uses SPI flash command 20H. + * Please do not call this function in SDK. + * + * @param uint32_t sector_num : Which sector to erase. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num); + +/** + * @brief Erase some sectors. + * Please do not call this function in SDK. + * + * @param uint32_t start_addr : Start addr to erase, should be sector aligned. + * + * @param uint32_t area_len : Length to erase, should be sector aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len); + +/** + * @brief Write Data to Flash, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t dest_addr : Address to write, should be 4 bytes aligned. + * + * @param const uint32_t *src : The pointer to data which is to write. + * + * @param uint32_t len : Length to write, should be 4 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len); + +/** + * @brief Read Data from Flash, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t src_addr : Address to read, should be 4 bytes aligned. + * + * @param uint32_t *dest : The buf to read the data. + * + * @param uint32_t len : Length to read, should be 4 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len); + +/** + * @brief SPI1 go into encrypto mode. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void esp_rom_spiflash_write_encrypted_enable(void); + +/** + * @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t flash_addr : Address to write, should be 32 bytes aligned. + * + * @param uint32_t *data : The pointer to data which is to write. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, uint32_t *data); + +/** + * @brief SPI1 go out of encrypto mode. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void esp_rom_spiflash_write_encrypted_disable(void); + +/** + * @brief Write data to flash with transparent encryption. + * @note Sectors to be written should already be erased. + * + * @note Please do not call this function in SDK. + * + * @param uint32_t flash_addr : Address to write, should be 32 byte aligned. + * + * @param uint32_t *data : The pointer to data to write. Note, this pointer must + * be 32 bit aligned and the content of the data will be + * modified by the encryption function. + * + * @param uint32_t len : Length to write, should be 32 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully. + * ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len); + + +/** @brief Wait until SPI flash write operation is complete + * + * @note Please do not call this function in SDK. + * + * Reads the Write In Progress bit of the SPI flash status register, + * repeats until this bit is zero (indicating write complete). + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete + * ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi); + + +/** @brief Enable Quad I/O pin functions + * + * @note Please do not call this function in SDK. + * + * Sets the HD & WP pin functions for Quad I/O modes, based on the + * efuse SPI pin configuration. + * + * @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O. + * + * @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig(). + * - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored. + * - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored. + * - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used + * to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI). + * Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral. + */ +void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig); + +/** + * @brief Clear WEL bit unconditionally. + * + * @return always ESP_ROM_SPIFLASH_RESULT_OK + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void); + +/** + * @brief Set WREN bit. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @return always ESP_ROM_SPIFLASH_RESULT_OK + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_enable(esp_rom_spiflash_chip_t *spi); + +/** + * @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed. + * Please do not call this function in SDK. + * + * @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write). + * + * @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M. + * + * @return None + */ +void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv); + +/** + * @brief Set SPI Flash pad drivers. + * Please do not call this function in SDK. + * + * @param uint8_t wp_gpio_num: WP gpio number. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid + * drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp. + * Values usually read from falsh by rom code, function usually callde by rom code. + * if value with bit(3) set, the value is valid, bit[2:0] is the real value. + * + * @return None + */ +void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs); + +/** + * @brief Select SPI Flash function for pads. + * Please do not call this function in SDK. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @return None + */ +void esp_rom_spiflash_select_padsfunc(uint32_t ishspi); + +/** + * @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command. + * + * @return uint16_t 0 : do not send command any more. + * 1 : go to the next command. + * n > 1 : skip (n - 1) commands. + */ +uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd); + +extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs; + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/include/esp32c2/rom/tjpgd.h b/components/esp_rom/include/esp32c6/rom/tjpgd.h similarity index 98% rename from components/esp_rom/include/esp32c2/rom/tjpgd.h rename to components/esp_rom/include/esp32c6/rom/tjpgd.h index 635a0abf45..3050f865c9 100644 --- a/components/esp_rom/include/esp32c2/rom/tjpgd.h +++ b/components/esp_rom/include/esp32c6/rom/tjpgd.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/esp_rom/include/esp32c6/rom/uart.h b/components/esp_rom/include/esp32c6/rom/uart.h new file mode 100644 index 0000000000..6b1a3a2c60 --- /dev/null +++ b/components/esp_rom/include/esp32c6/rom/uart.h @@ -0,0 +1,432 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_UART_H_ +#define _ROM_UART_H_ + +#include "esp_types.h" +#include "esp_attr.h" +#include "ets_sys.h" +#include "soc/soc.h" +#include "soc/uart_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup uart_apis, uart configuration and communication related apis + * @brief uart apis + */ + +/** @addtogroup uart_apis + * @{ + */ + +#define RX_BUFF_SIZE 0x400 +#define TX_BUFF_SIZE 100 + +//uart int enalbe register ctrl bits +#define UART_RCV_INTEN BIT0 +#define UART_TRX_INTEN BIT1 +#define UART_LINE_STATUS_INTEN BIT2 + +//uart int identification ctrl bits +#define UART_INT_FLAG_MASK 0x0E + +//uart fifo ctrl bits +#define UART_CLR_RCV_FIFO BIT1 +#define UART_CLR_TRX_FIFO BIT2 +#define UART_RCVFIFO_TRG_LVL_BITS BIT6 + +//uart line control bits +#define UART_DIV_LATCH_ACCESS_BIT BIT7 + +//uart line status bits +#define UART_RCV_DATA_RDY_FLAG BIT0 +#define UART_RCV_OVER_FLOW_FLAG BIT1 +#define UART_RCV_PARITY_ERR_FLAG BIT2 +#define UART_RCV_FRAME_ERR_FLAG BIT3 +#define UART_BRK_INT_FLAG BIT4 +#define UART_TRX_FIFO_EMPTY_FLAG BIT5 +#define UART_TRX_ALL_EMPTY_FLAG BIT6 // include fifo and shift reg +#define UART_RCV_ERR_FLAG BIT7 + +//send and receive message frame head +#define FRAME_FLAG 0x7E + +typedef enum { + UART_LINE_STATUS_INT_FLAG = 0x06, + UART_RCV_FIFO_INT_FLAG = 0x04, + UART_RCV_TMOUT_INT_FLAG = 0x0C, + UART_TXBUFF_EMPTY_INT_FLAG = 0x02 +} UartIntType; //consider bit0 for int_flag + +typedef enum { + RCV_ONE_BYTE = 0x0, + RCV_FOUR_BYTE = 0x1, + RCV_EIGHT_BYTE = 0x2, + RCV_FOURTEEN_BYTE = 0x3 +} UartRcvFifoTrgLvl; + +typedef enum { + FIVE_BITS = 0x0, + SIX_BITS = 0x1, + SEVEN_BITS = 0x2, + EIGHT_BITS = 0x3 +} UartBitsNum4Char; + +typedef enum { + ONE_STOP_BIT = 1, + ONE_HALF_STOP_BIT = 2, + TWO_STOP_BIT = 3 +} UartStopBitsNum; + +typedef enum { + NONE_BITS = 0, + ODD_BITS = 2, + EVEN_BITS = 3 + +} UartParityMode; + +typedef enum { + STICK_PARITY_DIS = 0, + STICK_PARITY_EN = 2 +} UartExistParity; + +typedef enum { + BIT_RATE_9600 = 9600, + BIT_RATE_19200 = 19200, + BIT_RATE_38400 = 38400, + BIT_RATE_57600 = 57600, + BIT_RATE_115200 = 115200, + BIT_RATE_230400 = 230400, + BIT_RATE_460800 = 460800, + BIT_RATE_921600 = 921600 +} UartBautRate; + +typedef enum { + NONE_CTRL, + HARDWARE_CTRL, + XON_XOFF_CTRL +} UartFlowCtrl; + +typedef enum { + EMPTY, + UNDER_WRITE, + WRITE_OVER +} RcvMsgBuffState; + +typedef struct { + uint8_t *pRcvMsgBuff; + uint8_t *pWritePos; + uint8_t *pReadPos; + uint8_t TrigLvl; + RcvMsgBuffState BuffState; +} RcvMsgBuff; + +typedef struct { + uint32_t TrxBuffSize; + uint8_t *pTrxBuff; +} TrxMsgBuff; + +typedef enum { + BAUD_RATE_DET, + WAIT_SYNC_FRM, + SRCH_MSG_HEAD, + RCV_MSG_BODY, + RCV_ESC_CHAR, +} RcvMsgState; + +typedef struct { + UartBautRate baut_rate; + UartBitsNum4Char data_bits; + UartExistParity exist_parity; + UartParityMode parity; // chip size in byte + UartStopBitsNum stop_bits; + UartFlowCtrl flow_ctrl; + uint8_t buff_uart_no; //indicate which uart use tx/rx buffer + RcvMsgBuff rcv_buff; +// TrxMsgBuff trx_buff; + RcvMsgState rcv_state; + int received; +} UartDevice; + +/** + * @brief Init uart device struct value and reset uart0/uart1 rx. + * Please do not call this function in SDK. + * + * @param rxBuffer, must be a pointer to RX_BUFF_SIZE bytes or NULL + * + * @return None + */ +void uartAttach(void *rxBuffer); + +/** + * @brief Init uart0 or uart1 for UART download booting mode. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, else for UART1. + * + * @param uint32_t clock : clock used by uart module, to adjust baudrate. + * + * @return None + */ +void Uart_Init(uint8_t uart_no, uint32_t clock); + +/** + * @brief Modify uart baudrate. + * This function will reset RX/TX fifo for uart. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @param uint32_t DivLatchValue : (clock << 4)/baudrate. + * + * @return None + */ +void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue); + +/** + * @brief Init uart0 or uart1 for UART download booting mode. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @param uint8_t is_sync : 0, only one UART module, easy to detect, wait until detected; + * 1, two UART modules, hard to detect, detect and return. + * + * @return None + */ +int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync); + +/** + * @brief Switch printf channel of uart_tx_one_char. + * Please do not call this function when printf. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None + */ +void uart_tx_switch(uint8_t uart_no); + +/** + * @brief Switch message exchange channel for UART download booting. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None + */ +void uart_buff_switch(uint8_t uart_no); + +/** + * @brief Output a char to printf channel, wait until fifo not full. + * + * @param None + * + * @return OK. + */ +STATUS uart_tx_one_char(uint8_t TxChar); + +/** + * @brief Output a char to message exchange channel, wait until fifo not full. + * Please do not call this function in SDK. + * + * @param None + * + * @return OK. + */ +STATUS uart_tx_one_char2(uint8_t TxChar); + +/** + * @brief Wait until uart tx full empty. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None. + */ +void uart_tx_flush(uint8_t uart_no); + +/** + * @brief Wait until uart tx full empty and the last char send ok. + * + * @param uart_no : 0 for UART0, 1 for UART1 + * + * The function defined in ROM code has a bug, so we define the correct version + * here for compatibility. + */ +void uart_tx_wait_idle(uint8_t uart_no); + +/** + * @brief Get an input char from message channel. + * Please do not call this function in SDK. + * + * @param uint8_t *pRxChar : the pointer to store the char. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS uart_rx_one_char(uint8_t *pRxChar); + +/** + * @brief Get an input char from message channel, wait until successful. + * Please do not call this function in SDK. + * + * @param None + * + * @return char : input char value. + */ +char uart_rx_one_char_block(void); + +/** + * @brief Get an input string line from message channel. + * Please do not call this function in SDK. + * + * @param uint8_t *pString : the pointer to store the string. + * + * @param uint8_t MaxStrlen : the max string length, incude '\0'. + * + * @return OK. + */ +STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); + +/** + * @brief Process uart recevied information in the interrupt handler. + * Please do not call this function in SDK. + * + * @param void *para : the message receive buffer. + * + * @return None + */ +void uart_rx_intr_handler(void *para); + +/** + * @brief Get an char from receive buffer. + * Please do not call this function in SDK. + * + * @param RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer. + * + * @param uint8_t *pRxByte : the pointer to store the char. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); + +/** + * @brief Get all chars from receive buffer. + * Please do not call this function in SDK. + * + * @param uint8_t *pCmdLn : the pointer to store the string. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS UartGetCmdLn(uint8_t *pCmdLn); + +/** + * @brief Get uart configuration struct. + * Please do not call this function in SDK. + * + * @param None + * + * @return UartDevice * : uart configuration struct pointer. + */ +UartDevice *GetUartDevice(void); + +/** + * @brief Send an packet to download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *p : the pointer to output string. + * + * @param int len : the string length. + * + * @return None. + */ +void send_packet(uint8_t *p, int len); + +/** + * @brief Receive an packet from download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *p : the pointer to input string. + * + * @param int len : If string length > len, the string will be truncated. + * + * @param uint8_t is_sync : 0, only one UART module; + * 1, two UART modules. + * + * @return int : the length of the string. + */ +int recv_packet(uint8_t *p, int len, uint8_t is_sync); + +/** + * @brief Send an packet to download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *pData : the pointer to input string. + * + * @param uint16_t DataLen : the string length. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS SendMsg(uint8_t *pData, uint16_t DataLen); + +/** + * @brief Receive an packet from download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *pData : the pointer to input string. + * + * @param uint16_t MaxDataLen : If string length > MaxDataLen, the string will be truncated. + * + * @param uint8_t is_sync : 0, only one UART module; + * 1, two UART modules. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); + +/** + * @brief Check if this UART is in download connection. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return ETS_NO_BOOT = 0 for no. + * SEL_UART_BOOT = BIT(1) for yes. + */ +uint8_t UartConnCheck(uint8_t uart_no); + +/** + * @brief Initialize the USB ACM UART + * Needs to be fed a buffer of at least 128 bytes, plus any rx buffer you may want to have. + * + * @param cdc_acm_work_mem Pointer to work mem for CDC-ACM code + * @param cdc_acm_work_mem_len Length of work mem + */ +void Uart_Init_USB(void *cdc_acm_work_mem, int cdc_acm_work_mem_len); + + +/** + * @brief Install handler to reset the chip when a RTS change has been detected on the CDC-ACM 'UART'. + */ +void uart_usb_enable_reset_on_rts(void); + + +extern UartDevice UartDev; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_UART_H_ */ diff --git a/components/esp_rom/include/esp32h2/rom/md5_hash.h b/components/esp_rom/include/esp32h2/rom/md5_hash.h index 63ce15857b..3c5e10d1bf 100644 --- a/components/esp_rom/include/esp32h2/rom/md5_hash.h +++ b/components/esp_rom/include/esp32h2/rom/md5_hash.h @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2003-2005, Jouni Malinen + * + * SPDX-License-Identifier: BSD-3-Clause + */ /* * MD5 internal definitions * Copyright (c) 2003-2005, Jouni Malinen diff --git a/components/esp_rom/include/esp32h2/rom/miniz.h b/components/esp_rom/include/esp32h2/rom/miniz.h index 4c8cb7a421..aaef48c14a 100644 --- a/components/esp_rom/include/esp32h2/rom/miniz.h +++ b/components/esp_rom/include/esp32h2/rom/miniz.h @@ -729,7 +729,7 @@ typedef struct { // Initializes the compressor. // There is no corresponding deinit() function because the tdefl API's do not dynamically allocate memory. -// pBut_buf_func: If NULL, output data will be supplied to the specified callback. In this case, the user should call the tdefl_compress_buffer() API for compression. +// pBut_buf_func: If **not** NULL, output data will be supplied to the specified callback. In this case, the user should call the tdefl_compress_buffer() API for compression. // If pBut_buf_func is NULL the user should always call the tdefl_compress() API. // flags: See the above enums (TDEFL_HUFFMAN_ONLY, TDEFL_WRITE_ZLIB_HEADER, etc.) tdefl_status tdefl_init(tdefl_compressor *d, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags); diff --git a/components/esp_rom/include/esp32s2/rom/md5_hash.h b/components/esp_rom/include/esp32s2/rom/md5_hash.h index f116f1e670..6092546033 100644 --- a/components/esp_rom/include/esp32s2/rom/md5_hash.h +++ b/components/esp_rom/include/esp32s2/rom/md5_hash.h @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2003-2005, Jouni Malinen + * + * SPDX-License-Identifier: BSD-3-Clause + */ /* * MD5 internal definitions * Copyright (c) 2003-2005, Jouni Malinen diff --git a/components/esp_rom/include/esp32s2/rom/miniz.h b/components/esp_rom/include/esp32s2/rom/miniz.h index b9b9202aaa..fd2fe3c9a1 100644 --- a/components/esp_rom/include/esp32s2/rom/miniz.h +++ b/components/esp_rom/include/esp32s2/rom/miniz.h @@ -745,7 +745,7 @@ typedef struct // Initializes the compressor. // There is no corresponding deinit() function because the tdefl API's do not dynamically allocate memory. -// pBut_buf_func: If NULL, output data will be supplied to the specified callback. In this case, the user should call the tdefl_compress_buffer() API for compression. +// pBut_buf_func: If **not** NULL, output data will be supplied to the specified callback. In this case, the user should call the tdefl_compress_buffer() API for compression. // If pBut_buf_func is NULL the user should always call the tdefl_compress() API. // flags: See the above enums (TDEFL_HUFFMAN_ONLY, TDEFL_WRITE_ZLIB_HEADER, etc.) tdefl_status tdefl_init(tdefl_compressor *d, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags); diff --git a/components/esp_rom/include/esp32s3/rom/md5_hash.h b/components/esp_rom/include/esp32s3/rom/md5_hash.h index 8676ace2b1..5f97e8483f 100644 --- a/components/esp_rom/include/esp32s3/rom/md5_hash.h +++ b/components/esp_rom/include/esp32s3/rom/md5_hash.h @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2003-2005, Jouni Malinen + * + * SPDX-License-Identifier: BSD-3-Clause + */ /* * MD5 internal definitions * Copyright (c) 2003-2005, Jouni Malinen diff --git a/components/esp_rom/include/esp32s3/rom/miniz.h b/components/esp_rom/include/esp32s3/rom/miniz.h index 7553511349..f095b539b9 100644 --- a/components/esp_rom/include/esp32s3/rom/miniz.h +++ b/components/esp_rom/include/esp32s3/rom/miniz.h @@ -728,7 +728,7 @@ typedef struct { // Initializes the compressor. // There is no corresponding deinit() function because the tdefl API's do not dynamically allocate memory. -// pBut_buf_func: If NULL, output data will be supplied to the specified callback. In this case, the user should call the tdefl_compress_buffer() API for compression. +// pBut_buf_func: If **not** NULL, output data will be supplied to the specified callback. In this case, the user should call the tdefl_compress_buffer() API for compression. // If pBut_buf_func is NULL the user should always call the tdefl_compress() API. // flags: See the above enums (TDEFL_HUFFMAN_ONLY, TDEFL_WRITE_ZLIB_HEADER, etc.) tdefl_status tdefl_init(tdefl_compressor *d, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags); diff --git a/components/esp_rom/include/esp_rom_sys.h b/components/esp_rom/include/esp_rom_sys.h index 54ef25fe47..6d119edda6 100644 --- a/components/esp_rom/include/esp_rom_sys.h +++ b/components/esp_rom/include/esp_rom_sys.h @@ -13,6 +13,24 @@ extern "C" { #endif +/** + * @brief Software Reset digital core include RTC. + * + * It is not recommended to use this function in esp-idf, use + * esp_restart() instead. + */ +void esp_rom_software_reset_system(void); + +/** + * @brief Software Reset cpu core. + * + * It is not recommended to use this function in esp-idf, use + * esp_restart() instead. + * + * @param cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU. + */ +void esp_rom_software_reset_cpu(int cpu_no); + /** * @brief Print formated string to console device * @note float and long long data are not supported! diff --git a/components/esp_rom/include/esp_rom_tjpgd.h b/components/esp_rom/include/esp_rom_tjpgd.h deleted file mode 100644 index 318519ba74..0000000000 --- a/components/esp_rom/include/esp_rom_tjpgd.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/*-----------------------------------------------------------------------------/ -/ TJpgDec - Tiny JPEG Decompressor R0.01b (C)ChaN, 2012 -/-----------------------------------------------------------------------------/ -/ The TJpgDec is a generic JPEG decompressor module for tiny embedded systems. -/ This is a free software that opened for education, research and commercial -/ developments under license policy of following terms. -/ -/ Copyright (C) 2012, ChaN, all right reserved. -/ -/ * The TJpgDec module is a free software and there is NO WARRANTY. -/ * No restriction on use. You can use, modify and redistribute it for -/ personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY. -/ * Redistributions of source code must retain the above copyright notice. -/ -/-----------------------------------------------------------------------------*/ - -#pragma once - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* Error code */ -typedef enum { - JDR_OK = 0, /* 0: Succeeded */ - JDR_INTR, /* 1: Interrupted by output function */ - JDR_INP, /* 2: Device error or wrong termination of input stream */ - JDR_MEM1, /* 3: Insufficient memory pool for the image */ - JDR_MEM2, /* 4: Insufficient stream input buffer */ - JDR_PAR, /* 5: Parameter error */ - JDR_FMT1, /* 6: Data format error (may be damaged data) */ - JDR_FMT2, /* 7: Right format but not supported */ - JDR_FMT3 /* 8: Not supported JPEG standard */ -} esp_rom_tjpgd_result_t; - -/* Rectangular structure */ -typedef struct { - uint16_t left; /* Left end */ - uint16_t right; /* Right end */ - uint16_t top; /* Top end */ - uint16_t bottom;/* Bottom end */ -} esp_rom_tjpgd_rect_t; - -typedef struct JDEC_s esp_rom_tjpgd_dec_t; - -/** - * @brief Type of user defined input function to read data from input stream - * @param dec Specifies the decompression object of the decompression session - * @param buffer Specifies the pointer to the read buffer to store the read data. A NULL specifies to remove the data from input stream - * @param ndata Specifies number of bytes to read/remove from the input stream - * - * @return number of bytes read/removed. When a zero is returned, the esp_rom_tjpgd_prepare and esp_rom_tjpgd_decomp function aborts with JDR_INP - */ -typedef uint32_t (*esp_rom_tjpgd_input_function_t)(esp_rom_tjpgd_dec_t *dec, uint8_t *buffer, uint32_t ndata); - -/** - * @brief User defined output function to write decompressed pixels to the output device - * - * This function is the data output interface of the TJpgDec module. - * The corresponding decompression session can be identified by the pointer to the device identifier jdec->device passed to the 5th argument of jd_prepare function. - * The bitmap is sent to the frame buffer or display device in this function. - * The first pixel in the bitmap is the left-top of the rectangular, the second one is next right and last pixel is the bottom-right of the rectangular. - * The size of rectangular varies from 1x1 to 16x16 depends on clipping, scaling and sampling factor of the image. - * If the rectangular is out of the frame buffer, it should be clipped in this function. - * - * The pixel format is currently configured to RGB888 - * - * @param dec Specifies the decompression object of the decompression session - * @param bitmap Specifies the RGB bitmap to be output - * @param rect Specifies rectangular region in the image to output the RGB bitmap - * - * @return Normally returns 1. It lets TJpgDec to continue the decompressing process. - * When a 0 is returned, the esp_rom_tjpgd_decomp function aborts with JDR_INTR. - * This is useful to interrupt the decompression process - */ -typedef uint32_t (*esp_rom_tjpgd_output_function_t)(esp_rom_tjpgd_dec_t *dec, void *bitmap, esp_rom_tjpgd_rect_t *rect); - -struct JDEC_s { - uint32_t dctr; /* Number of bytes available in the input buffer */ - uint8_t *dptr; /* Current data read ptr */ - uint8_t *inbuf; /* Bit stream input buffer */ - uint8_t dmsk; /* Current bit in the current read byte */ - uint8_t scale; /* Output scaling ratio */ - uint8_t msx, msy; /* MCU size in unit of block (width, height) */ - uint8_t qtid[3]; /* Quantization table ID of each component */ - int16_t dcv[3]; /* Previous DC element of each component */ - uint16_t nrst; /* Restart inverval */ - uint32_t width, height; /* Size of the input image (pixel) */ - uint8_t *huffbits[2][2]; /* Huffman bit distribution tables [id][dcac] */ - uint16_t *huffcode[2][2]; /* Huffman code word tables [id][dcac] */ - uint8_t *huffdata[2][2]; /* Huffman decoded data tables [id][dcac] */ - int32_t *qttbl[4]; /* Dequaitizer tables [id] */ - void *workbuf; /* Working buffer for IDCT and RGB output */ - uint8_t *mcubuf; /* Working buffer for the MCU */ - void *pool; /* Pointer to available memory pool */ - uint32_t sz_pool; /* Size of momory pool (bytes available) */ - esp_rom_tjpgd_input_function_t infunc; /* Pointer to jpeg stream input function */ - void *device; /* Pointer to I/O device identifiler for the session */ -}; - -/* TJpgDec API functions */ - -/** - * @brief Analyzes the JPEG data and create a decompression object for subsequent decompression process. - * @param dec Specifies the decompression object to be initialized. The decompression object is used for subsequent decompression process. - * @param infunc Specifies the user defined data input function. - * @param work Specifies pointer to the work area for this session. It should be aligned to word boundary or it can result an exception. - * @param sz_work Specifies size of the work area in unit of byte. - * TJpgDec requires upto 3092 bytes of work area depends on the built-in parameter tables of the JPEG image. - * Thus 3092 bytes of work area is sufficient for most case. - * @param dev Specifies pointer to the user defined device identifier for this session. - * It is stored to the member device in the decompression object. It can be referred by I/O functions to identify the current session. - * When I/O device is fixed in the project or this feature is not needed, set NULL and do not care about this. - * - * @return - * - JDR_OK Function succeeded and decompression object is valid. - * - JDR_INP An error occurred in input function due to hard error or wrong stream termination. - * - JDR_MEM1 Insufficient work area for this JPEG image. - * - JDR_MEM2 Insufficient input buffer for this JPEG image. JD_SZBUF may be too small. - * - JDR_PAR Parameter error. Given pointer to the work area is NULL. - * - JDR_FMT1 Data format error. The JPEG data can be collapsed. - * - JDR_FMT2 Right format but not supported. May be a grayscale image. - * - JDR_FMT3 Not supported JPEG standard. May be a progressive JPEG image. - */ -esp_rom_tjpgd_result_t esp_rom_tjpgd_prepare(esp_rom_tjpgd_dec_t *dec, esp_rom_tjpgd_input_function_t infunc, void *work, uint32_t sz_work, void *dev); - -/** - * @brief Decompress the JPEG image and output it as RGB data. - * @param dec Specifies the valid decompressor object. - * @param outfunc Specifies the user defined data output function. The esp_rom_tjpgd_decomp function calls this function to output the decompressed JPEG image in RGB form. - * @param scale Specifies scaling factor N for output. The output image is descaled to 1 / 2 ^ N (N = 0 to 3). - * - * @return - * - JDR_OK Function succeeded. - * - JDR_INTR The decompression process is interrupted by output function. - * - JDR_INP An error occured in input function due to hard error or wrong stream termination. - * - JDR_PAR Parameter error. Given scale factor is invalid. - * - JDR_FMT1 Data format error. The JPEG data can be collapted. - */ -esp_rom_tjpgd_result_t esp_rom_tjpgd_decomp(esp_rom_tjpgd_dec_t *dec, esp_rom_tjpgd_output_function_t outfunc, uint8_t scale); - -#ifdef __cplusplus -} -#endif diff --git a/components/esp_rom/patches/esp_rom_regi2c.c b/components/esp_rom/patches/esp_rom_regi2c.c index 73d7d842f0..90827ab287 100644 --- a/components/esp_rom/patches/esp_rom_regi2c.c +++ b/components/esp_rom/patches/esp_rom_regi2c.c @@ -6,11 +6,11 @@ #include #include "esp_bit_defs.h" -#include "soc/syscon_reg.h" #include "esp_rom_caps.h" #include "sdkconfig.h" #if CONFIG_IDF_TARGET_ESP32S2 +#include "soc/syscon_reg.h" #define I2C_RTC_WIFI_CLK_EN (SYSCON_WIFI_CLK_EN_REG) diff --git a/components/esp_rom/patches/esp_rom_tjpgd.c b/components/esp_rom/patches/esp_rom_tjpgd.c deleted file mode 100644 index 8e0b8d2713..0000000000 --- a/components/esp_rom/patches/esp_rom_tjpgd.c +++ /dev/null @@ -1,976 +0,0 @@ -/*----------------------------------------------------------------------------/ -/ TJpgDec - Tiny JPEG Decompressor R0.01b (C)ChaN, 2012 -/-----------------------------------------------------------------------------/ -/ The TJpgDec is a generic JPEG decompressor module for tiny embedded systems. -/ This is a free software that opened for education, research and commercial -/ developments under license policy of following terms. -/ -/ Copyright (C) 2012, ChaN, all right reserved. -/ -/ * The TJpgDec module is a free software and there is NO WARRANTY. -/ * No restriction on use. You can use, modify and redistribute it for -/ personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY. -/ * Redistributions of source code must retain the above copyright notice. -/ -/-----------------------------------------------------------------------------/ -/ Oct 04,'11 R0.01 First release. -/ Feb 19,'12 R0.01a Fixed decompression fails when scan starts with an escape seq. -/ Sep 03,'12 R0.01b Added JD_TBLCLIP option. -/----------------------------------------------------------------------------*/ - -#include "esp_rom_caps.h" - -#if !ESP_ROM_HAS_JPEG_DECODE - -#include "esp_rom_tjpgd.h" - -#define JD_SZBUF 512 /* Size of stream input buffer */ -#define JD_FORMAT 0 /* Output pixel format 0:RGB888 (3 BYTE/pix), 1:RGB565 (1 WORD/pix) */ -#define JD_USE_SCALE 1 /* Use descaling feature for output */ -#define JD_TBLCLIP 1 /* Use table for saturation (might be a bit faster but increases 1K bytes of code size) */ - - -/*-----------------------------------------------*/ -/* Zigzag-order to raster-order conversion table */ -/*-----------------------------------------------*/ - -#define ZIG(n) Zig[n] - -static -const uint8_t Zig[64] = { /* Zigzag-order to raster-order conversion table */ - 0, 1, 8, 16, 9, 2, 3, 10, 17, 24, 32, 25, 18, 11, 4, 5, - 12, 19, 26, 33, 40, 48, 41, 34, 27, 20, 13, 6, 7, 14, 21, 28, - 35, 42, 49, 56, 57, 50, 43, 36, 29, 22, 15, 23, 30, 37, 44, 51, - 58, 59, 52, 45, 38, 31, 39, 46, 53, 60, 61, 54, 47, 55, 62, 63 -}; - - - -/*-------------------------------------------------*/ -/* Input scale factor of Arai algorithm */ -/* (scaled up 16 bits for fixed point operations) */ -/*-------------------------------------------------*/ - -#define IPSF(n) Ipsf[n] - -static -const uint16_t Ipsf[64] = { /* See also aa_idct.png */ - (uint16_t)(1.00000*8192), (uint16_t)(1.38704*8192), (uint16_t)(1.30656*8192), (uint16_t)(1.17588*8192), (uint16_t)(1.00000*8192), (uint16_t)(0.78570*8192), (uint16_t)(0.54120*8192), (uint16_t)(0.27590*8192), - (uint16_t)(1.38704*8192), (uint16_t)(1.92388*8192), (uint16_t)(1.81226*8192), (uint16_t)(1.63099*8192), (uint16_t)(1.38704*8192), (uint16_t)(1.08979*8192), (uint16_t)(0.75066*8192), (uint16_t)(0.38268*8192), - (uint16_t)(1.30656*8192), (uint16_t)(1.81226*8192), (uint16_t)(1.70711*8192), (uint16_t)(1.53636*8192), (uint16_t)(1.30656*8192), (uint16_t)(1.02656*8192), (uint16_t)(0.70711*8192), (uint16_t)(0.36048*8192), - (uint16_t)(1.17588*8192), (uint16_t)(1.63099*8192), (uint16_t)(1.53636*8192), (uint16_t)(1.38268*8192), (uint16_t)(1.17588*8192), (uint16_t)(0.92388*8192), (uint16_t)(0.63638*8192), (uint16_t)(0.32442*8192), - (uint16_t)(1.00000*8192), (uint16_t)(1.38704*8192), (uint16_t)(1.30656*8192), (uint16_t)(1.17588*8192), (uint16_t)(1.00000*8192), (uint16_t)(0.78570*8192), (uint16_t)(0.54120*8192), (uint16_t)(0.27590*8192), - (uint16_t)(0.78570*8192), (uint16_t)(1.08979*8192), (uint16_t)(1.02656*8192), (uint16_t)(0.92388*8192), (uint16_t)(0.78570*8192), (uint16_t)(0.61732*8192), (uint16_t)(0.42522*8192), (uint16_t)(0.21677*8192), - (uint16_t)(0.54120*8192), (uint16_t)(0.75066*8192), (uint16_t)(0.70711*8192), (uint16_t)(0.63638*8192), (uint16_t)(0.54120*8192), (uint16_t)(0.42522*8192), (uint16_t)(0.29290*8192), (uint16_t)(0.14932*8192), - (uint16_t)(0.27590*8192), (uint16_t)(0.38268*8192), (uint16_t)(0.36048*8192), (uint16_t)(0.32442*8192), (uint16_t)(0.27590*8192), (uint16_t)(0.21678*8192), (uint16_t)(0.14932*8192), (uint16_t)(0.07612*8192) -}; - - - -/*---------------------------------------------*/ -/* Conversion table for fast clipping process */ -/*---------------------------------------------*/ - -#if JD_TBLCLIP - -#define BYTECLIP(v) Clip8[(uint32_t)(v) & 0x3FF] - -static -const uint8_t Clip8[1024] = { - /* 0..255 */ - 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, - 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, - 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, - 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, - 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, - 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, - 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, - 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, - /* 256..511 */ - 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, - 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, - 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, - 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, - 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, - 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, - 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, - 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, - /* -512..-257 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* -256..-1 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; - -#else /* JD_TBLCLIP */ - -inline -uint8_t BYTECLIP ( - int32_t val -) -{ - if (val < 0) val = 0; - if (val > 255) val = 255; - - return (uint8_t)val; -} - -#endif - - - -/*-----------------------------------------------------------------------*/ -/* Allocate a memory block from memory pool */ -/*-----------------------------------------------------------------------*/ - -static -void* alloc_pool ( /* Pointer to allocated memory block (NULL:no memory available) */ - esp_rom_tjpgd_dec_t* jd, /* Pointer to the decompressor object */ - uint32_t nd /* Number of bytes to allocate */ -) -{ - char *rp = 0; - - - nd = (nd + 3) & ~3; /* Align block size to the word boundary */ - - if (jd->sz_pool >= nd) { - jd->sz_pool -= nd; - rp = (char*)jd->pool; /* Get start of available memory pool */ - jd->pool = (void*)(rp + nd); /* Allocate requierd bytes */ - } - - return (void*)rp; /* Return allocated memory block (NULL:no memory to allocate) */ -} - - - - -/*-----------------------------------------------------------------------*/ -/* Create de-quantization and prescaling tables with a DQT segment */ -/*-----------------------------------------------------------------------*/ - -static -uint32_t create_qt_tbl ( /* 0:OK, !0:Failed */ - esp_rom_tjpgd_dec_t* jd, /* Pointer to the decompressor object */ - const uint8_t* data, /* Pointer to the quantizer tables */ - uint32_t ndata /* Size of input data */ -) -{ - uint32_t i; - uint8_t d, z; - int32_t *pb; - - - while (ndata) { /* Process all tables in the segment */ - if (ndata < 65) return JDR_FMT1; /* Err: table size is unaligned */ - ndata -= 65; - d = *data++; /* Get table property */ - if (d & 0xF0) return JDR_FMT1; /* Err: not 8-bit resolution */ - i = d & 3; /* Get table ID */ - pb = alloc_pool(jd, 64 * sizeof (int32_t));/* Allocate a memory block for the table */ - if (!pb) return JDR_MEM1; /* Err: not enough memory */ - jd->qttbl[i] = pb; /* Register the table */ - for (i = 0; i < 64; i++) { /* Load the table */ - z = ZIG(i); /* Zigzag-order to raster-order conversion */ - pb[z] = (int32_t)((uint32_t)*data++ * IPSF(z)); /* Apply scale factor of Arai algorithm to the de-quantizers */ - } - } - - return JDR_OK; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Create huffman code tables with a DHT segment */ -/*-----------------------------------------------------------------------*/ - -static -uint32_t create_huffman_tbl ( /* 0:OK, !0:Failed */ - esp_rom_tjpgd_dec_t* jd, /* Pointer to the decompressor object */ - const uint8_t* data, /* Pointer to the packed huffman tables */ - uint32_t ndata /* Size of input data */ -) -{ - uint32_t i, j, b, np, cls, num; - uint8_t d, *pb, *pd; - uint16_t hc, *ph; - - - while (ndata) { /* Process all tables in the segment */ - if (ndata < 17) return JDR_FMT1; /* Err: wrong data size */ - ndata -= 17; - d = *data++; /* Get table number and class */ - cls = (d >> 4); num = d & 0x0F; /* class = dc(0)/ac(1), table number = 0/1 */ - if (d & 0xEE) return JDR_FMT1; /* Err: invalid class/number */ - pb = alloc_pool(jd, 16); /* Allocate a memory block for the bit distribution table */ - if (!pb) return JDR_MEM1; /* Err: not enough memory */ - jd->huffbits[num][cls] = pb; - for (np = i = 0; i < 16; i++) { /* Load number of patterns for 1 to 16-bit code */ - pb[i] = b = *data++; - np += b; /* Get sum of code words for each code */ - } - - ph = alloc_pool(jd, np * sizeof (uint16_t));/* Allocate a memory block for the code word table */ - if (!ph) return JDR_MEM1; /* Err: not enough memory */ - jd->huffcode[num][cls] = ph; - hc = 0; - for (j = i = 0; i < 16; i++) { /* Re-build huffman code word table */ - b = pb[i]; - while (b--) ph[j++] = hc++; - hc <<= 1; - } - - if (ndata < np) return JDR_FMT1; /* Err: wrong data size */ - ndata -= np; - pd = alloc_pool(jd, np); /* Allocate a memory block for the decoded data */ - if (!pd) return JDR_MEM1; /* Err: not enough memory */ - jd->huffdata[num][cls] = pd; - for (i = 0; i < np; i++) { /* Load decoded data corresponds to each code ward */ - d = *data++; - if (!cls && d > 11) return JDR_FMT1; - *pd++ = d; - } - } - - return JDR_OK; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Extract N bits from input stream */ -/*-----------------------------------------------------------------------*/ - -static -int32_t bitext ( /* >=0: extracted data, <0: error code */ - esp_rom_tjpgd_dec_t* jd, /* Pointer to the decompressor object */ - uint32_t nbit /* Number of bits to extract (1 to 11) */ -) -{ - uint8_t msk, s, *dp; - uint32_t dc, v, f; - - - msk = jd->dmsk; dc = jd->dctr; dp = jd->dptr; /* Bit mask, number of data available, read ptr */ - s = *dp; v = f = 0; - do { - if (!msk) { /* Next byte? */ - if (!dc) { /* No input data is available, re-fill input buffer */ - dp = jd->inbuf; /* Top of input buffer */ - dc = jd->infunc(jd, dp, JD_SZBUF); - if (!dc) return 0 - (int32_t)JDR_INP; /* Err: read error or wrong stream termination */ - } else { - dp++; /* Next data ptr */ - } - dc--; /* Decrement number of available bytes */ - if (f) { /* In flag sequence? */ - f = 0; /* Exit flag sequence */ - if (*dp != 0) return 0 - (int32_t)JDR_FMT1; /* Err: unexpected flag is detected (may be collapted data) */ - *dp = s = 0xFF; /* The flag is a data 0xFF */ - } else { - s = *dp; /* Get next data byte */ - if (s == 0xFF) { /* Is start of flag sequence? */ - f = 1; continue; /* Enter flag sequence */ - } - } - msk = 0x80; /* Read from MSB */ - } - v <<= 1; /* Get a bit */ - if (s & msk) v++; - msk >>= 1; - nbit--; - } while (nbit); - jd->dmsk = msk; jd->dctr = dc; jd->dptr = dp; - - return (int32_t)v; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Extract a huffman decoded data from input stream */ -/*-----------------------------------------------------------------------*/ - -static -int32_t huffext ( /* >=0: decoded data, <0: error code */ - esp_rom_tjpgd_dec_t* jd, /* Pointer to the decompressor object */ - const uint8_t* hbits, /* Pointer to the bit distribution table */ - const uint16_t* hcode, /* Pointer to the code word table */ - const uint8_t* hdata /* Pointer to the data table */ -) -{ - uint8_t msk, s, *dp; - uint32_t dc, v, f, bl, nd; - - - msk = jd->dmsk; dc = jd->dctr; dp = jd->dptr; /* Bit mask, number of data available, read ptr */ - s = *dp; v = f = 0; - bl = 16; /* Max code length */ - do { - if (!msk) { /* Next byte? */ - if (!dc) { /* No input data is available, re-fill input buffer */ - dp = jd->inbuf; /* Top of input buffer */ - dc = jd->infunc(jd, dp, JD_SZBUF); - if (!dc) return 0 - (int32_t)JDR_INP; /* Err: read error or wrong stream termination */ - } else { - dp++; /* Next data ptr */ - } - dc--; /* Decrement number of available bytes */ - if (f) { /* In flag sequence? */ - f = 0; /* Exit flag sequence */ - if (*dp != 0) - return 0 - (int32_t)JDR_FMT1; /* Err: unexpected flag is detected (may be collapted data) */ - *dp = s = 0xFF; /* The flag is a data 0xFF */ - } else { - s = *dp; /* Get next data byte */ - if (s == 0xFF) { /* Is start of flag sequence? */ - f = 1; continue; /* Enter flag sequence, get trailing byte */ - } - } - msk = 0x80; /* Read from MSB */ - } - v <<= 1; /* Get a bit */ - if (s & msk) v++; - msk >>= 1; - - for (nd = *hbits++; nd; nd--) { /* Search the code word in this bit length */ - if (v == *hcode++) { /* Matched? */ - jd->dmsk = msk; jd->dctr = dc; jd->dptr = dp; - return *hdata; /* Return the decoded data */ - } - hdata++; - } - bl--; - } while (bl); - - return 0 - (int32_t)JDR_FMT1; /* Err: code not found (may be collapted data) */ -} - - - - -/*-----------------------------------------------------------------------*/ -/* Apply Inverse-DCT in Arai Algorithm (see also aa_idct.png) */ -/*-----------------------------------------------------------------------*/ - -static -void block_idct ( - int32_t* src, /* Input block data (de-quantized and pre-scaled for Arai Algorithm) */ - uint8_t* dst /* Pointer to the destination to store the block as byte array */ -) -{ - const int32_t M13 = (int32_t)(1.41421*4096), M2 = (int32_t)(1.08239*4096), M4 = (int32_t)(2.61313*4096), M5 = (int32_t)(1.84776*4096); - int32_t v0, v1, v2, v3, v4, v5, v6, v7; - int32_t t10, t11, t12, t13; - uint32_t i; - - /* Process columns */ - for (i = 0; i < 8; i++) { - v0 = src[8 * 0]; /* Get even elements */ - v1 = src[8 * 2]; - v2 = src[8 * 4]; - v3 = src[8 * 6]; - - t10 = v0 + v2; /* Process the even elements */ - t12 = v0 - v2; - t11 = (v1 - v3) * M13 >> 12; - v3 += v1; - t11 -= v3; - v0 = t10 + v3; - v3 = t10 - v3; - v1 = t11 + t12; - v2 = t12 - t11; - - v4 = src[8 * 7]; /* Get odd elements */ - v5 = src[8 * 1]; - v6 = src[8 * 5]; - v7 = src[8 * 3]; - - t10 = v5 - v4; /* Process the odd elements */ - t11 = v5 + v4; - t12 = v6 - v7; - v7 += v6; - v5 = (t11 - v7) * M13 >> 12; - v7 += t11; - t13 = (t10 + t12) * M5 >> 12; - v4 = t13 - (t10 * M2 >> 12); - v6 = t13 - (t12 * M4 >> 12) - v7; - v5 -= v6; - v4 -= v5; - - src[8 * 0] = v0 + v7; /* Write-back transformed values */ - src[8 * 7] = v0 - v7; - src[8 * 1] = v1 + v6; - src[8 * 6] = v1 - v6; - src[8 * 2] = v2 + v5; - src[8 * 5] = v2 - v5; - src[8 * 3] = v3 + v4; - src[8 * 4] = v3 - v4; - - src++; /* Next column */ - } - - /* Process rows */ - src -= 8; - for (i = 0; i < 8; i++) { - v0 = src[0] + (128L << 8); /* Get even elements (remove DC offset (-128) here) */ - v1 = src[2]; - v2 = src[4]; - v3 = src[6]; - - t10 = v0 + v2; /* Process the even elements */ - t12 = v0 - v2; - t11 = (v1 - v3) * M13 >> 12; - v3 += v1; - t11 -= v3; - v0 = t10 + v3; - v3 = t10 - v3; - v1 = t11 + t12; - v2 = t12 - t11; - - v4 = src[7]; /* Get odd elements */ - v5 = src[1]; - v6 = src[5]; - v7 = src[3]; - - t10 = v5 - v4; /* Process the odd elements */ - t11 = v5 + v4; - t12 = v6 - v7; - v7 += v6; - v5 = (t11 - v7) * M13 >> 12; - v7 += t11; - t13 = (t10 + t12) * M5 >> 12; - v4 = t13 - (t10 * M2 >> 12); - v6 = t13 - (t12 * M4 >> 12) - v7; - v5 -= v6; - v4 -= v5; - - dst[0] = BYTECLIP((v0 + v7) >> 8); /* Descale the transformed values 8 bits and output */ - dst[7] = BYTECLIP((v0 - v7) >> 8); - dst[1] = BYTECLIP((v1 + v6) >> 8); - dst[6] = BYTECLIP((v1 - v6) >> 8); - dst[2] = BYTECLIP((v2 + v5) >> 8); - dst[5] = BYTECLIP((v2 - v5) >> 8); - dst[3] = BYTECLIP((v3 + v4) >> 8); - dst[4] = BYTECLIP((v3 - v4) >> 8); - dst += 8; - - src += 8; /* Next row */ - } -} - - - - -/*-----------------------------------------------------------------------*/ -/* Load all blocks in the MCU into working buffer */ -/*-----------------------------------------------------------------------*/ - -static -esp_rom_tjpgd_result_t mcu_load ( - esp_rom_tjpgd_dec_t* jd /* Pointer to the decompressor object */ -) -{ - int32_t *tmp = (int32_t*)jd->workbuf; /* Block working buffer for de-quantize and IDCT */ - uint32_t blk, nby, nbc, i, z, id, cmp; - int32_t b, d, e; - uint8_t *bp; - const uint8_t *hb, *hd; - const uint16_t *hc; - const int32_t *dqf; - - - nby = jd->msx * jd->msy; /* Number of Y blocks (1, 2 or 4) */ - nbc = 2; /* Number of C blocks (2) */ - bp = jd->mcubuf; /* Pointer to the first block */ - - for (blk = 0; blk < nby + nbc; blk++) { - cmp = (blk < nby) ? 0 : blk - nby + 1; /* Component number 0:Y, 1:Cb, 2:Cr */ - id = cmp ? 1 : 0; /* Huffman table ID of the component */ - - /* Extract a DC element from input stream */ - hb = jd->huffbits[id][0]; /* Huffman table for the DC element */ - hc = jd->huffcode[id][0]; - hd = jd->huffdata[id][0]; - b = huffext(jd, hb, hc, hd); /* Extract a huffman coded data (bit length) */ - if (b < 0) return 0 - b; /* Err: invalid code or input */ - d = jd->dcv[cmp]; /* DC value of previous block */ - if (b) { /* If there is any difference from previous block */ - e = bitext(jd, b); /* Extract data bits */ - if (e < 0) return 0 - e; /* Err: input */ - b = 1 << (b - 1); /* MSB position */ - if (!(e & b)) e -= (b << 1) - 1; /* Restore sign if needed */ - d += e; /* Get current value */ - jd->dcv[cmp] = (int16_t)d; /* Save current DC value for next block */ - } - dqf = jd->qttbl[jd->qtid[cmp]]; /* De-quantizer table ID for this component */ - tmp[0] = d * dqf[0] >> 8; /* De-quantize, apply scale factor of Arai algorithm and descale 8 bits */ - - /* Extract following 63 AC elements from input stream */ - for (i = 1; i < 64; i++) tmp[i] = 0; /* Clear rest of elements */ - hb = jd->huffbits[id][1]; /* Huffman table for the AC elements */ - hc = jd->huffcode[id][1]; - hd = jd->huffdata[id][1]; - i = 1; /* Top of the AC elements */ - do { - b = huffext(jd, hb, hc, hd); /* Extract a huffman coded value (zero runs and bit length) */ - if (b == 0) break; /* EOB? */ - if (b < 0) return 0 - b; /* Err: invalid code or input error */ - z = (uint32_t)b >> 4; /* Number of leading zero elements */ - if (z) { - i += z; /* Skip zero elements */ - if (i >= 64) return JDR_FMT1; /* Too long zero run */ - } - if (b &= 0x0F) { /* Bit length */ - d = bitext(jd, b); /* Extract data bits */ - if (d < 0) return 0 - d; /* Err: input device */ - b = 1 << (b - 1); /* MSB position */ - if (!(d & b)) d -= (b << 1) - 1;/* Restore negative value if needed */ - z = ZIG(i); /* Zigzag-order to raster-order converted index */ - tmp[z] = d * dqf[z] >> 8; /* De-quantize, apply scale factor of Arai algorithm and descale 8 bits */ - } - } while (++i < 64); /* Next AC element */ - - if (JD_USE_SCALE && jd->scale == 3) - *bp = (*tmp / 256) + 128; /* If scale ratio is 1/8, IDCT can be ommited and only DC element is used */ - else - block_idct(tmp, bp); /* Apply IDCT and store the block to the MCU buffer */ - - bp += 64; /* Next block */ - } - - return JDR_OK; /* All blocks have been loaded successfully */ -} - - - - -/*-----------------------------------------------------------------------*/ -/* Output an MCU: Convert YCrCb to RGB and output it in RGB form */ -/*-----------------------------------------------------------------------*/ - -static -esp_rom_tjpgd_result_t mcu_output ( - esp_rom_tjpgd_dec_t* jd, /* Pointer to the decompressor object */ - uint32_t (*outfunc)(esp_rom_tjpgd_dec_t*, void*, esp_rom_tjpgd_rect_t*), /* RGB output function */ - uint32_t x, /* MCU position in the image (left of the MCU) */ - uint32_t y /* MCU position in the image (top of the MCU) */ -) -{ - const int32_t CVACC = (sizeof (int32_t) > 2) ? 1024 : 128; - uint32_t ix, iy, mx, my, rx, ry; - int32_t yy, cb, cr; - uint8_t *py, *pc, *rgb24; - esp_rom_tjpgd_rect_t rect; - - - mx = jd->msx * 8; my = jd->msy * 8; /* MCU size (pixel) */ - rx = (x + mx <= jd->width) ? mx : jd->width - x; /* Output rectangular size (it may be clipped at right/bottom end) */ - ry = (y + my <= jd->height) ? my : jd->height - y; - if (JD_USE_SCALE) { - rx >>= jd->scale; ry >>= jd->scale; - if (!rx || !ry) return JDR_OK; /* Skip this MCU if all pixel is to be rounded off */ - x >>= jd->scale; y >>= jd->scale; - } - rect.left = x; rect.right = x + rx - 1; /* Rectangular area in the frame buffer */ - rect.top = y; rect.bottom = y + ry - 1; - - - if (!JD_USE_SCALE || jd->scale != 3) { /* Not for 1/8 scaling */ - - /* Build an RGB MCU from discrete comopnents */ - rgb24 = (uint8_t*)jd->workbuf; - for (iy = 0; iy < my; iy++) { - pc = jd->mcubuf; - py = pc + iy * 8; - if (my == 16) { /* Double block height? */ - pc += 64 * 4 + (iy >> 1) * 8; - if (iy >= 8) py += 64; - } else { /* Single block height */ - pc += mx * 8 + iy * 8; - } - for (ix = 0; ix < mx; ix++) { - cb = pc[0] - 128; /* Get Cb/Cr component and restore right level */ - cr = pc[64] - 128; - if (mx == 16) { /* Double block width? */ - if (ix == 8) py += 64 - 8; /* Jump to next block if double block heigt */ - pc += ix & 1; /* Increase chroma pointer every two pixels */ - } else { /* Single block width */ - pc++; /* Increase chroma pointer every pixel */ - } - yy = *py++; /* Get Y component */ - - /* Convert YCbCr to RGB */ - *rgb24++ = /* R */ BYTECLIP(yy + ((int32_t)(1.402 * CVACC) * cr) / CVACC); - *rgb24++ = /* G */ BYTECLIP(yy - ((int32_t)(0.344 * CVACC) * cb + (int32_t)(0.714 * CVACC) * cr) / CVACC); - *rgb24++ = /* B */ BYTECLIP(yy + ((int32_t)(1.772 * CVACC) * cb) / CVACC); - } - } - - /* Descale the MCU rectangular if needed */ - if (JD_USE_SCALE && jd->scale) { - uint32_t x, y, r, g, b, s, w, a; - uint8_t *op; - - /* Get averaged RGB value of each square correcponds to a pixel */ - s = jd->scale * 2; /* Bumber of shifts for averaging */ - w = 1 << jd->scale; /* Width of square */ - a = (mx - w) * 3; /* Bytes to skip for next line in the square */ - op = (uint8_t*)jd->workbuf; - for (iy = 0; iy < my; iy += w) { - for (ix = 0; ix < mx; ix += w) { - rgb24 = (uint8_t*)jd->workbuf + (iy * mx + ix) * 3; - r = g = b = 0; - for (y = 0; y < w; y++) { /* Accumulate RGB value in the square */ - for (x = 0; x < w; x++) { - r += *rgb24++; - g += *rgb24++; - b += *rgb24++; - } - rgb24 += a; - } /* Put the averaged RGB value as a pixel */ - *op++ = (uint8_t)(r >> s); - *op++ = (uint8_t)(g >> s); - *op++ = (uint8_t)(b >> s); - } - } - } - - } else { /* For only 1/8 scaling (left-top pixel in each block are the DC value of the block) */ - - /* Build a 1/8 descaled RGB MCU from discrete comopnents */ - rgb24 = (uint8_t*)jd->workbuf; - pc = jd->mcubuf + mx * my; - cb = pc[0] - 128; /* Get Cb/Cr component and restore right level */ - cr = pc[64] - 128; - for (iy = 0; iy < my; iy += 8) { - py = jd->mcubuf; - if (iy == 8) py += 64 * 2; - for (ix = 0; ix < mx; ix += 8) { - yy = *py; /* Get Y component */ - py += 64; - - /* Convert YCbCr to RGB */ - *rgb24++ = /* R */ BYTECLIP(yy + ((int32_t)(1.402 * CVACC) * cr / CVACC)); - *rgb24++ = /* G */ BYTECLIP(yy - ((int32_t)(0.344 * CVACC) * cb + (int32_t)(0.714 * CVACC) * cr) / CVACC); - *rgb24++ = /* B */ BYTECLIP(yy + ((int32_t)(1.772 * CVACC) * cb / CVACC)); - } - } - } - - /* Squeeze up pixel table if a part of MCU is to be truncated */ - mx >>= jd->scale; - if (rx < mx) { - uint8_t *s, *d; - uint32_t x, y; - - s = d = (uint8_t*)jd->workbuf; - for (y = 0; y < ry; y++) { - for (x = 0; x < rx; x++) { /* Copy effective pixels */ - *d++ = *s++; - *d++ = *s++; - *d++ = *s++; - } - s += (mx - rx) * 3; /* Skip truncated pixels */ - } - } - - /* Convert RGB888 to RGB565 if needed */ - if (JD_FORMAT == 1) { - uint8_t *s = (uint8_t*)jd->workbuf; - uint16_t w, *d = (uint16_t*)s; - uint32_t n = rx * ry; - - do { - w = (*s++ & 0xF8) << 8; /* RRRRR----------- */ - w |= (*s++ & 0xFC) << 3; /* -----GGGGGG----- */ - w |= *s++ >> 3; /* -----------BBBBB */ - *d++ = w; - } while (--n); - } - - /* Output the RGB rectangular */ - return outfunc(jd, jd->workbuf, &rect) ? JDR_OK : JDR_INTR; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Process restart interval */ -/*-----------------------------------------------------------------------*/ - -static -esp_rom_tjpgd_result_t restart ( - esp_rom_tjpgd_dec_t* jd, /* Pointer to the decompressor object */ - uint16_t rstn /* Expected restert sequense number */ -) -{ - uint32_t i, dc; - uint16_t d; - uint8_t *dp; - - - /* Discard padding bits and get two bytes from the input stream */ - dp = jd->dptr; dc = jd->dctr; - d = 0; - for (i = 0; i < 2; i++) { - if (!dc) { /* No input data is available, re-fill input buffer */ - dp = jd->inbuf; - dc = jd->infunc(jd, dp, JD_SZBUF); - if (!dc) return JDR_INP; - } else { - dp++; - } - dc--; - d = (d << 8) | *dp; /* Get a byte */ - } - jd->dptr = dp; jd->dctr = dc; jd->dmsk = 0; - - /* Check the marker */ - if ((d & 0xFFD8) != 0xFFD0 || (d & 7) != (rstn & 7)) - return JDR_FMT1; /* Err: expected RSTn marker is not detected (may be collapted data) */ - - /* Reset DC offset */ - jd->dcv[2] = jd->dcv[1] = jd->dcv[0] = 0; - - return JDR_OK; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Analyze the JPEG image and Initialize decompressor object */ -/*-----------------------------------------------------------------------*/ - -#define LDB_WORD(ptr) (uint16_t)(((uint16_t)*((uint8_t*)(ptr))<<8)|(uint16_t)*(uint8_t*)((ptr)+1)) - - -esp_rom_tjpgd_result_t esp_rom_tjpgd_prepare ( - esp_rom_tjpgd_dec_t* jd, /* Blank decompressor object */ - uint32_t (*infunc)(esp_rom_tjpgd_dec_t*, uint8_t*, uint32_t), /* JPEG strem input function */ - void* pool, /* Working buffer for the decompression session */ - uint32_t sz_pool, /* Size of working buffer */ - void* dev /* I/O device identifier for the session */ -) -{ - uint8_t *seg, b; - uint16_t marker; - uint32_t ofs; - uint32_t n, i, j, len; - esp_rom_tjpgd_result_t rc; - - - if (!pool) return JDR_PAR; - - jd->pool = pool; /* Work memroy */ - jd->sz_pool = sz_pool; /* Size of given work memory */ - jd->infunc = infunc; /* Stream input function */ - jd->device = dev; /* I/O device identifier */ - jd->nrst = 0; /* No restart interval (default) */ - - for (i = 0; i < 2; i++) { /* Nulls pointers */ - for (j = 0; j < 2; j++) { - jd->huffbits[i][j] = 0; - jd->huffcode[i][j] = 0; - jd->huffdata[i][j] = 0; - } - } - for (i = 0; i < 4; i++) jd->qttbl[i] = 0; - - jd->inbuf = seg = alloc_pool(jd, JD_SZBUF); /* Allocate stream input buffer */ - if (!seg) return JDR_MEM1; - - if (jd->infunc(jd, seg, 2) != 2) return JDR_INP;/* Check SOI marker */ - if (LDB_WORD(seg) != 0xFFD8) return JDR_FMT1; /* Err: SOI is not detected */ - ofs = 2; - - for (;;) { - /* Get a JPEG marker */ - if (jd->infunc(jd, seg, 4) != 4) return JDR_INP; - marker = LDB_WORD(seg); /* Marker */ - len = LDB_WORD(seg + 2); /* Length field */ - if (len <= 2 || (marker >> 8) != 0xFF) return JDR_FMT1; - len -= 2; /* Content size excluding length field */ - ofs += 4 + len; /* Number of bytes loaded */ - - switch (marker & 0xFF) { - case 0xC0: /* SOF0 (baseline JPEG) */ - /* Load segment data */ - if (len > JD_SZBUF) return JDR_MEM2; - if (jd->infunc(jd, seg, len) != len) return JDR_INP; - - jd->width = LDB_WORD(seg+3); /* Image width in unit of pixel */ - jd->height = LDB_WORD(seg+1); /* Image height in unit of pixel */ - if (seg[5] != 3) return JDR_FMT3; /* Err: Supports only Y/Cb/Cr format */ - - /* Check three image components */ - for (i = 0; i < 3; i++) { - b = seg[7 + 3 * i]; /* Get sampling factor */ - if (!i) { /* Y component */ - if (b != 0x11 && b != 0x22 && b != 0x21)/* Check sampling factor */ - return JDR_FMT3; /* Err: Supports only 4:4:4, 4:2:0 or 4:2:2 */ - jd->msx = b >> 4; jd->msy = b & 15; /* Size of MCU [blocks] */ - } else { /* Cb/Cr component */ - if (b != 0x11) return JDR_FMT3; /* Err: Sampling factor of Cr/Cb must be 1 */ - } - b = seg[8 + 3 * i]; /* Get dequantizer table ID for this component */ - if (b > 3) return JDR_FMT3; /* Err: Invalid ID */ - jd->qtid[i] = b; - } - break; - - case 0xDD: /* DRI */ - /* Load segment data */ - if (len > JD_SZBUF) return JDR_MEM2; - if (jd->infunc(jd, seg, len) != len) return JDR_INP; - - /* Get restart interval (MCUs) */ - jd->nrst = LDB_WORD(seg); - break; - - case 0xC4: /* DHT */ - /* Load segment data */ - if (len > JD_SZBUF) return JDR_MEM2; - if (jd->infunc(jd, seg, len) != len) return JDR_INP; - - /* Create huffman tables */ - rc = create_huffman_tbl(jd, seg, len); - if (rc) return rc; - break; - - case 0xDB: /* DQT */ - /* Load segment data */ - if (len > JD_SZBUF) return JDR_MEM2; - if (jd->infunc(jd, seg, len) != len) return JDR_INP; - - /* Create de-quantizer tables */ - rc = create_qt_tbl(jd, seg, len); - if (rc) return rc; - break; - - case 0xDA: /* SOS */ - /* Load segment data */ - if (len > JD_SZBUF) return JDR_MEM2; - if (jd->infunc(jd, seg, len) != len) return JDR_INP; - - if (!jd->width || !jd->height) return JDR_FMT1; /* Err: Invalid image size */ - - if (seg[0] != 3) return JDR_FMT3; /* Err: Supports only three color components format */ - - /* Check if all tables corresponding to each components have been loaded */ - for (i = 0; i < 3; i++) { - b = seg[2 + 2 * i]; /* Get huffman table ID */ - if (b != 0x00 && b != 0x11) return JDR_FMT3; /* Err: Different table number for DC/AC element */ - b = i ? 1 : 0; - if (!jd->huffbits[b][0] || !jd->huffbits[b][1]) /* Check huffman table for this component */ - return JDR_FMT1; /* Err: Huffman table not loaded */ - if (!jd->qttbl[jd->qtid[i]]) return JDR_FMT1; /* Err: Dequantizer table not loaded */ - } - - /* Allocate working buffer for MCU and RGB */ - n = jd->msy * jd->msx; /* Number of Y blocks in the MCU */ - if (!n) return JDR_FMT1; /* Err: SOF0 has not been loaded */ - len = n * 64 * 2 + 64; /* Allocate buffer for IDCT and RGB output */ - if (len < 256) len = 256; /* but at least 256 byte is required for IDCT */ - jd->workbuf = alloc_pool(jd, len); /* and it may occupy a part of following MCU working buffer for RGB output */ - if (!jd->workbuf) return JDR_MEM1; /* Err: not enough memory */ - jd->mcubuf = alloc_pool(jd, (n + 2) * 64); /* Allocate MCU working buffer */ - if (!jd->mcubuf) return JDR_MEM1; /* Err: not enough memory */ - - /* Pre-load the JPEG data to extract it from the bit stream */ - jd->dptr = seg; jd->dctr = 0; jd->dmsk = 0; /* Prepare to read bit stream */ - if (ofs %= JD_SZBUF) { /* Align read offset to JD_SZBUF */ - jd->dctr = jd->infunc(jd, seg + ofs, JD_SZBUF - (uint32_t)ofs); - jd->dptr = seg + ofs - 1; - } - - return JDR_OK; /* Initialization succeeded. Ready to decompress the JPEG image. */ - - case 0xC1: /* SOF1 */ - case 0xC2: /* SOF2 */ - case 0xC3: /* SOF3 */ - case 0xC5: /* SOF5 */ - case 0xC6: /* SOF6 */ - case 0xC7: /* SOF7 */ - case 0xC9: /* SOF9 */ - case 0xCA: /* SOF10 */ - case 0xCB: /* SOF11 */ - case 0xCD: /* SOF13 */ - case 0xCE: /* SOF14 */ - case 0xCF: /* SOF15 */ - case 0xD9: /* EOI */ - return JDR_FMT3; /* Unsuppoted JPEG standard (may be progressive JPEG) */ - - default: /* Unknown segment (comment, exif or etc..) */ - /* Skip segment data */ - if (jd->infunc(jd, 0, len) != len) /* Null pointer specifies to skip bytes of stream */ - return JDR_INP; - } - } -} - - - - -/*-----------------------------------------------------------------------*/ -/* Start to decompress the JPEG picture */ -/*-----------------------------------------------------------------------*/ - -esp_rom_tjpgd_result_t esp_rom_tjpgd_decomp ( - esp_rom_tjpgd_dec_t* jd, /* Initialized decompression object */ - uint32_t (*outfunc)(esp_rom_tjpgd_dec_t*, void*, esp_rom_tjpgd_rect_t*), /* RGB output function */ - uint8_t scale /* Output de-scaling factor (0 to 3) */ -) -{ - uint32_t x, y, mx, my; - uint16_t rst, rsc; - esp_rom_tjpgd_result_t rc; - - - if (scale > (JD_USE_SCALE ? 3 : 0)) return JDR_PAR; - jd->scale = scale; - - mx = jd->msx * 8; my = jd->msy * 8; /* Size of the MCU (pixel) */ - - jd->dcv[2] = jd->dcv[1] = jd->dcv[0] = 0; /* Initialize DC values */ - rst = rsc = 0; - - rc = JDR_OK; - for (y = 0; y < jd->height; y += my) { /* Vertical loop of MCUs */ - for (x = 0; x < jd->width; x += mx) { /* Horizontal loop of MCUs */ - if (jd->nrst && rst++ == jd->nrst) { /* Process restart interval if enabled */ - rc = restart(jd, rsc++); - if (rc != JDR_OK) return rc; - rst = 1; - } - rc = mcu_load(jd); /* Load an MCU (decompress huffman coded stream and apply IDCT) */ - if (rc != JDR_OK) return rc; - rc = mcu_output(jd, outfunc, x, y); /* Output the MCU (color space conversion, scaling and output) */ - if (rc != JDR_OK) return rc; - } - } - - return rc; -} - -#endif // ESP_ROM_HAS_JPEG_DECODE diff --git a/components/esp_rom/patches/esp_rom_tlsf.c b/components/esp_rom/patches/esp_rom_tlsf.c new file mode 100644 index 0000000000..541b9a0b82 --- /dev/null +++ b/components/esp_rom/patches/esp_rom_tlsf.c @@ -0,0 +1,307 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * This file is a patch for the tlsf implementation stored in ROM + * - tlsf_check() now implements a call to a hook giving the user the possibility + * to implement specific checks on the memory of every free blocks. + * - The function tlsf_poison_check_pfunc_set() was added to allow the user to + * register the hook function called in tlsf_check(). + */ + +#include +#include +#include + +#include "esp_rom_caps.h" +#include "rom/tlsf.h" + +/*! + * @brief Opaque types for TLSF implementation + */ +typedef void* tlsf_t; +typedef void* pool_t; +typedef void* tlsf_walker; + +/* ---------------------------------------------------------------- + * Bring certain inline functions, macro and structures from the + * tlsf ROM implementation to be able to compile the patch. + * ---------------------------------------------------------------- */ + +#define tlsf_cast(t, exp) ((t) (exp)) + +enum tlsf_config { + /* log2 of number of linear subdivisions of block sizes. Larger + ** values require more memory in the control structure. Values of + ** 4 or 5 are typical. + */ + SL_INDEX_COUNT_LOG2 = 5, + + /* All allocation sizes and addresses are aligned to 4 bytes. */ + ALIGN_SIZE_LOG2 = 2, + ALIGN_SIZE = (1 << ALIGN_SIZE_LOG2), + +/* + ** We support allocations of sizes up to (1 << FL_INDEX_MAX) bits. + ** However, because we linearly subdivide the second-level lists, and + ** our minimum size granularity is 4 bytes, it doesn't make sense to + ** create first-level lists for sizes smaller than SL_INDEX_COUNT * 4, + ** or (1 << (SL_INDEX_COUNT_LOG2 + 2)) bytes, as there we will be + ** trying to split size ranges into more slots than we have available. + ** Instead, we calculate the minimum threshold size, and place all + ** blocks below that size into the 0th first-level list. + */ + + /* Fix the value of FL_INDEX_MAX to match the value that is defined + * in the ROM implementation. */ + FL_INDEX_MAX = 18, //Each pool can have up 256KB + + SL_INDEX_COUNT = (1 << SL_INDEX_COUNT_LOG2), + FL_INDEX_SHIFT = (SL_INDEX_COUNT_LOG2 + ALIGN_SIZE_LOG2), + FL_INDEX_COUNT = (FL_INDEX_MAX - FL_INDEX_SHIFT + 1), + + SMALL_BLOCK_SIZE = (1 << FL_INDEX_SHIFT), +}; + +#define block_header_free_bit (1 << 0) +#define block_header_prev_free_bit (1 << 1) +#define block_header_overhead (sizeof(size_t)) +#define block_start_offset (offsetof(block_header_t, size) + sizeof(size_t)) +#define block_size_min (sizeof(block_header_t) - sizeof(block_header_t*)) + +typedef ptrdiff_t tlsfptr_t; + +typedef struct block_header_t +{ + /* Points to the previous physical block. */ + struct block_header_t* prev_phys_block; + + /* The size of this block, excluding the block header. */ + size_t size; + + /* Next and previous free blocks. */ + struct block_header_t* next_free; + struct block_header_t* prev_free; +} block_header_t; + +/* The TLSF control structure. */ +typedef struct control_t +{ + /* Empty lists point at this block to indicate they are free. */ + block_header_t block_null; + + /* Bitmaps for free lists. */ + unsigned int fl_bitmap; + unsigned int sl_bitmap[FL_INDEX_COUNT]; + + /* Head of free lists. */ + block_header_t* blocks[FL_INDEX_COUNT][SL_INDEX_COUNT]; +} control_t; + +static inline __attribute__((__always_inline__)) int tlsf_fls(unsigned int word) +{ + const int bit = word ? 32 - __builtin_clz(word) : 0; + return bit - 1; +} + +static inline __attribute__((__always_inline__)) size_t block_size(const block_header_t* block) +{ + return block->size & ~(block_header_free_bit | block_header_prev_free_bit); +} + +static inline __attribute__((__always_inline__)) int block_is_free(const block_header_t* block) +{ + return tlsf_cast(int, block->size & block_header_free_bit); +} + +static inline __attribute__((__always_inline__)) int block_is_prev_free(const block_header_t* block) +{ + return tlsf_cast(int, block->size & block_header_prev_free_bit); +} + +static inline __attribute__((__always_inline__)) block_header_t* offset_to_block(const void* ptr, size_t size) +{ + return tlsf_cast(block_header_t*, tlsf_cast(tlsfptr_t, ptr) + size); +} + +static inline __attribute__((__always_inline__)) void* block_to_ptr(const block_header_t* block) +{ + return tlsf_cast(void*, + tlsf_cast(unsigned char*, block) + block_start_offset); +} + +static inline __attribute__((__always_inline__)) block_header_t* block_next(const block_header_t* block) +{ + block_header_t* next = offset_to_block(block_to_ptr(block), + block_size(block) - block_header_overhead); + return next; +} + +static inline __attribute__((__always_inline__)) void mapping_insert(size_t size, int* fli, int* sli) +{ + int fl, sl; + if (size < SMALL_BLOCK_SIZE) + { + /* Store small blocks in first list. */ + fl = 0; + sl = tlsf_cast(int, size) >> 2; + } + else + { + fl = tlsf_fls(size); + sl = tlsf_cast(int, size >> (fl - SL_INDEX_COUNT_LOG2)) ^ (1 << SL_INDEX_COUNT_LOG2); + fl -= (FL_INDEX_SHIFT - 1); + } + *fli = fl; + *sli = sl; +} + +/* ---------------------------------------------------------------- + * End of the environment necessary to compile and link the patch + * defined below + * ---------------------------------------------------------------- */ + +typedef bool (*poison_check_pfunc_t)(void *start, size_t size, bool is_free, bool print_errors); +static poison_check_pfunc_t s_poison_check_region = NULL; + +void tlsf_poison_check_pfunc_set(void *pfunc) +{ + s_poison_check_region = (poison_check_pfunc_t)pfunc; +} + +#define tlsf_insist_no_assert(x) { if (!(x)) { status--; } } + +int tlsf_check(tlsf_t tlsf) +{ + int i, j; + + control_t* control = tlsf_cast(control_t*, tlsf); + int status = 0; + + /* Check that the free lists and bitmaps are accurate. */ + for (i = 0; i < FL_INDEX_COUNT; ++i) + { + for (j = 0; j < SL_INDEX_COUNT; ++j) + { + const int fl_map = control->fl_bitmap & (1 << i); + const int sl_list = control->sl_bitmap[i]; + const int sl_map = sl_list & (1 << j); + const block_header_t* block = control->blocks[i][j]; + + /* Check that first- and second-level lists agree. */ + if (!fl_map) + { + tlsf_insist_no_assert(!sl_map && "second-level map must be null"); + } + + if (!sl_map) + { + tlsf_insist_no_assert(block == &control->block_null && "block list must be null"); + continue; + } + + /* Check that there is at least one free block. */ + tlsf_insist_no_assert(sl_list && "no free blocks in second-level map"); + tlsf_insist_no_assert(block != &control->block_null && "block should not be null"); + + while (block != &control->block_null) + { + int fli, sli; + const bool is_block_free = block_is_free(block); + tlsf_insist_no_assert(is_block_free && "block should be free"); + tlsf_insist_no_assert(!block_is_prev_free(block) && "blocks should have coalesced"); + tlsf_insist_no_assert(!block_is_free(block_next(block)) && "blocks should have coalesced"); + tlsf_insist_no_assert(block_is_prev_free(block_next(block)) && "block should be free"); + tlsf_insist_no_assert(block_size(block) >= block_size_min && "block not minimum size"); + + mapping_insert(block_size(block), &fli, &sli); + tlsf_insist_no_assert(fli == i && sli == j && "block size indexed in wrong list"); + + /* block_size(block) returns the size of the usable memory when the block is allocated. + * As the block under test is free, we need to subtract to the block size the next_free + * and prev_free fields of the block header as they are not a part of the usable memory + * when the block is free. In addition, we also need to subtract the size of prev_phys_block + * as this field is in fact part of the current free block and not part of the next (allocated) + * block. Check the comments in block_split function for more details. + */ + const size_t actual_free_block_size = block_size(block) + - offsetof(block_header_t, next_free) + - block_header_overhead; + + if (s_poison_check_region != NULL) { + tlsf_insist_no_assert(s_poison_check_region((char *)block + sizeof(block_header_t), + actual_free_block_size, is_block_free, true /* print errors */)); + } + + block = block->next_free; + } + } + } + + return status; +} + +#undef tlsf_insist_no_assert + +/* Set up the TLSF ROM patches here */ + +/*! + * @brief Structure to store all the functions of a TLSF implementation. + * The goal of this table is to change any of the address here in order + * to let the ROM code call another function implementation than the one + * in ROM. + */ +struct heap_tlsf_stub_table_t { + tlsf_t (*tlsf_create)(void* mem); + tlsf_t (*tlsf_create_with_pool)(void* mem, size_t bytes); + pool_t (*tlsf_get_pool)(tlsf_t tlsf); + pool_t (*tlsf_add_pool)(tlsf_t tlsf, void* mem, size_t bytes); + void (*tlsf_remove_pool)(tlsf_t tlsf, pool_t pool); + + void* (*tlsf_malloc)(tlsf_t tlsf, size_t size); + void* (*tlsf_memalign)(tlsf_t tlsf, size_t align, size_t size); + void* (*tlsf_memalign_offs)(tlsf_t tlsf, size_t align, size_t size, size_t offset); + void* (*tlsf_realloc)(tlsf_t tlsf, void* ptr, size_t size); + void (*tlsf_free)(tlsf_t tlsf, void* ptr); + + size_t (*tlsf_block_size)(void* ptr); + size_t (*tlsf_size)(void); + size_t (*tlsf_align_size)(void); + size_t (*tlsf_block_size_min)(void); + size_t (*tlsf_block_size_max)(void); + size_t (*tlsf_pool_overhead)(void); + size_t (*tlsf_alloc_overhead)(void); + + void (*tlsf_walk_pool)(pool_t pool, tlsf_walker walker, void* user); + + int (*tlsf_check)(tlsf_t tlsf); + int (*tlsf_check_pool)(pool_t pool); +}; + +/* We need the original table from the ROM */ +extern struct heap_tlsf_stub_table_t* heap_tlsf_table_ptr; + +/* We will copy the ROM table and modify the functions we patch */ +struct heap_tlsf_stub_table_t heap_tlsf_patch_table_ptr; + +/*! + * @brief Setup the TLSF ROM patches. + * This function must be called when setting up the heap. It will put in place the function patched + * from the ROM implementation. + * This function must not be defined as static, as it is marked as "undefined" in the linker flags + * (to force the linker to integrate the functions of this file inside the final binary) + */ +void __attribute__((constructor)) tlsf_set_rom_patches(void) +{ + /* Copy the ROM default table inside our table */ + memcpy(&heap_tlsf_patch_table_ptr, heap_tlsf_table_ptr, sizeof(struct heap_tlsf_stub_table_t)); + + /* Set the patched function here */ + heap_tlsf_patch_table_ptr.tlsf_check = tlsf_check; + + /* Set our table as the one to use in the ROM code */ + heap_tlsf_table_ptr = &heap_tlsf_patch_table_ptr; +} diff --git a/components/esp_rom/test/CMakeLists.txt b/components/esp_rom/test/CMakeLists.txt deleted file mode 100644 index 0edd942c0f..0000000000 --- a/components/esp_rom/test/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -idf_component_register(SRC_DIRS . - PRIV_INCLUDE_DIRS . ${CMAKE_CURRENT_BINARY_DIR} - PRIV_REQUIRES cmock test_utils) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") - -add_custom_command(OUTPUT "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h" - COMMAND xxd -i "logo.jpg" "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h" - WORKING_DIRECTORY ${COMPONENT_DIR} - DEPENDS "${CMAKE_CURRENT_LIST_DIR}/logo.jpg") -add_custom_target(test_logo DEPENDS "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h") -add_dependencies(${COMPONENT_LIB} test_logo) diff --git a/components/esp_rom/test/logo.jpg b/components/esp_rom/test/logo.jpg deleted file mode 100644 index 2bd9e775ea..0000000000 Binary files a/components/esp_rom/test/logo.jpg and /dev/null differ diff --git a/components/esp_rom/test/test_tjpgd.c b/components/esp_rom/test/test_tjpgd.c deleted file mode 100644 index 673d91a358..0000000000 --- a/components/esp_rom/test/test_tjpgd.c +++ /dev/null @@ -1,89 +0,0 @@ -#include -#include -#include -#include -#include "sdkconfig.h" -#include "unity.h" - -#include "esp_rom_tjpgd.h" -#include "test_tjpgd_logo.h" - -typedef struct { - const unsigned char *inData; - int inPos; - unsigned char *outData; - int outW; - int outH; -} JpegDev; - -static uint32_t infunc(esp_rom_tjpgd_dec_t *decoder, uint8_t *buf, uint32_t len) -{ - JpegDev *jd = (JpegDev *)decoder->device; - printf("Reading %d bytes from pos %d\n", len, jd->inPos); - if (buf != NULL) { - memcpy(buf, jd->inData + jd->inPos, len); - } - jd->inPos += len; - return len; -} - -static uint32_t outfunc(esp_rom_tjpgd_dec_t *decoder, void *bitmap, esp_rom_tjpgd_rect_t *rect) -{ - unsigned char *in = (unsigned char *)bitmap; - unsigned char *out; - int y; - printf("Rect %d,%d - %d,%d\n", rect->top, rect->left, rect->bottom, rect->right); - JpegDev *jd = (JpegDev *)decoder->device; - for (y = rect->top; y <= rect->bottom; y++) { - out = jd->outData + ((jd->outW * y) + rect->left) * 3; - memcpy(out, in, ((rect->right - rect->left) + 1) * 3); - in += ((rect->right - rect->left) + 1) * 3; - } - return 1; -} - -#define TESTW 48 -#define TESTH 48 -#define WORKSZ 3100 - -TEST_CASE("Test JPEG decompression library", "[rom][tjpgd]") -{ - char aapix[] = " .:;+=xX$$"; - unsigned char *decoded, *p; - char *work; - int r; - int x, y, v; - esp_rom_tjpgd_dec_t decoder; - JpegDev jd; - decoded = malloc(TESTW * TESTH * 3); - for (x = 0; x < TESTW * TESTH * 3; x += 2) { - decoded[x] = 0; - decoded[x + 1] = 0xff; - } - work = malloc(WORKSZ); - memset(work, 0, WORKSZ); - - jd.inData = logo_jpg; - jd.inPos = 0; - jd.outData = decoded; - jd.outW = TESTW; - jd.outH = TESTH; - - r = esp_rom_tjpgd_prepare(&decoder, infunc, work, WORKSZ, (void *)&jd); - TEST_ASSERT_EQUAL(r, JDR_OK); - r = esp_rom_tjpgd_decomp(&decoder, outfunc, 0); - TEST_ASSERT_EQUAL(r, JDR_OK); - - p = decoded + 2; - for (y = 0; y < TESTH; y++) { - for (x = 0; x < TESTH; x++) { - v = ((*p) * (sizeof(aapix) - 2) * 2) / 256; - printf("%c%c", aapix[v / 2], aapix[(v + 1) / 2]); - p += 3; - } - printf("%c%c", ' ', '\n'); - } - - free(work); - free(decoded); -} diff --git a/components/esp_rom/test_apps/CMakeLists.txt b/components/esp_rom/test_apps/CMakeLists.txt new file mode 100644 index 0000000000..5df555b801 --- /dev/null +++ b/components/esp_rom/test_apps/CMakeLists.txt @@ -0,0 +1,5 @@ +# This is the project CMakeLists.txt file for the test subproject +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(esp_rom_test) diff --git a/components/esp_rom/test_apps/README.md b/components/esp_rom/test_apps/README.md new file mode 100644 index 0000000000..b5be4985c5 --- /dev/null +++ b/components/esp_rom/test_apps/README.md @@ -0,0 +1,2 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | diff --git a/components/esp_rom/test_apps/main/CMakeLists.txt b/components/esp_rom/test_apps/main/CMakeLists.txt new file mode 100644 index 0000000000..1a8ffc6092 --- /dev/null +++ b/components/esp_rom/test_apps/main/CMakeLists.txt @@ -0,0 +1,8 @@ +set(srcs "test_app_main.c" + "test_libgcc.c" + "test_miniz.c") + +# In order for the cases defined by `TEST_CASE` to be linked into the final elf, +# the component can be registered as WHOLE_ARCHIVE +idf_component_register(SRCS ${srcs} + WHOLE_ARCHIVE) diff --git a/components/esp_rom/test_apps/main/test_app_main.c b/components/esp_rom/test_apps/main/test_app_main.c new file mode 100644 index 0000000000..f739ea079f --- /dev/null +++ b/components/esp_rom/test_apps/main/test_app_main.c @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#include "unity.h" +#include "unity_test_runner.h" +#include "esp_heap_caps.h" + +#define TEST_MEMORY_LEAK_THRESHOLD (-100) + +static size_t before_free_8bit; +static size_t before_free_32bit; + +static void check_leak(size_t before_free, size_t after_free, const char *type) +{ + ssize_t delta = after_free - before_free; + printf("MALLOC_CAP_%s: Before %u bytes free, After %u bytes free (delta %d)\n", type, before_free, after_free, delta); + TEST_ASSERT_MESSAGE(delta >= TEST_MEMORY_LEAK_THRESHOLD, "memory leak"); +} + +void setUp(void) +{ + before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); +} + +void tearDown(void) +{ + size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); + check_leak(before_free_8bit, after_free_8bit, "8BIT"); + check_leak(before_free_32bit, after_free_32bit, "32BIT"); +} + +void app_main(void) +{ + unity_run_menu(); +} diff --git a/components/esp_rom/test/test_libgcc.c b/components/esp_rom/test_apps/main/test_libgcc.c similarity index 98% rename from components/esp_rom/test/test_libgcc.c rename to components/esp_rom/test_apps/main/test_libgcc.c index 85c9398643..d3b84a876f 100644 --- a/components/esp_rom/test/test_libgcc.c +++ b/components/esp_rom/test_apps/main/test_libgcc.c @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ #include #include "unity.h" @@ -175,7 +180,7 @@ TEST_CASE("libgcc math functions", "[rom][libgcc]") TEST_ASSERT(__umoddi3(15, 2) == 1); extern unsigned __umodsi3(unsigned x, unsigned y); TEST_ASSERT(__umodsi3(15, 2) == 1); -#if !(CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3) +#ifndef __riscv extern uint64_t __umulsidi3(unsigned x, unsigned y); TEST_ASSERT(__umulsidi3(0x10000000, 0x10000000) == 0x100000000000000ULL); #endif diff --git a/components/esp_rom/test/test_miniz.c b/components/esp_rom/test_apps/main/test_miniz.c similarity index 86% rename from components/esp_rom/test/test_miniz.c rename to components/esp_rom/test_apps/main/test_miniz.c index 4744aba6a9..e5c34e6911 100644 --- a/components/esp_rom/test/test_miniz.c +++ b/components/esp_rom/test_apps/main/test_miniz.c @@ -1,27 +1,17 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ #include #include #include #include #include "sdkconfig.h" #include "unity.h" +#include "rom/miniz.h" -// compression/decompression will take off a bunch of memory -// test it only with PSRAM enabled -#ifdef CONFIG_SPIRAM - -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32) -// miniz unit test can't pass on ESP32 non-ECO3 version IDF-1807 - -#if CONFIG_IDF_TARGET_ESP32 -#include "esp32/rom/miniz.h" -#elif CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/rom/miniz.h" -#else -#error "unsupported target" -#endif - - -#define DATASIZE (1024 * 64) +#define DATASIZE (1024 * 32) TEST_CASE("Test miniz compression/decompression", "[rom][miniz]") { @@ -101,6 +91,3 @@ TEST_CASE("Test miniz compression/decompression", "[rom][miniz]") free(outbuf); free(decomp); } - -#endif //#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32) -#endif // CONFIG_SPIRAM diff --git a/components/esp_rom/test_apps/pytest_esp_rom.py b/components/esp_rom/test_apps/pytest_esp_rom.py new file mode 100644 index 0000000000..9ddf838c2b --- /dev/null +++ b/components/esp_rom/test_apps/pytest_esp_rom.py @@ -0,0 +1,16 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +import pytest +from pytest_embedded import Dut + + +@pytest.mark.esp32c3 +@pytest.mark.esp32s2 +@pytest.mark.esp32s3 +@pytest.mark.generic +@pytest.mark.nightly_run +def test_esp_rom(dut: Dut) -> None: + dut.expect('Press ENTER to see the list of tests') + dut.write('*') + dut.expect_unity_test_output() diff --git a/components/esp_rom/test_apps/sdkconfig.defaults b/components/esp_rom/test_apps/sdkconfig.defaults new file mode 100644 index 0000000000..b308cb2ddd --- /dev/null +++ b/components/esp_rom/test_apps/sdkconfig.defaults @@ -0,0 +1,2 @@ +CONFIG_FREERTOS_HZ=1000 +CONFIG_ESP_TASK_WDT=n diff --git a/components/esp_serial_slave_link/CMakeLists.txt b/components/esp_serial_slave_link/CMakeLists.txt deleted file mode 100644 index 5375d478ee..0000000000 --- a/components/esp_serial_slave_link/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -idf_component_register(SRCS "essl.c" - "essl_sdio.c" - "essl_spi.c" - INCLUDE_DIRS "include" - REQUIRES "sdmmc" - "driver" - PRIV_INCLUDE_DIRS "." - "include/esp_serial_slave_link" -) - -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/components/esp_serial_slave_link/include/essl_spi/esp32c3_defs.h b/components/esp_serial_slave_link/include/essl_spi/esp32c3_defs.h deleted file mode 100644 index 3dfd4a14b7..0000000000 --- a/components/esp_serial_slave_link/include/essl_spi/esp32c3_defs.h +++ /dev/null @@ -1,38 +0,0 @@ -// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - - -#pragma once - -// NOTE: From the view of master -#define CMD_HD_WRBUF_REG 0x01 -#define CMD_HD_RDBUF_REG 0x02 -#define CMD_HD_WRDMA_REG 0x03 -#define CMD_HD_RDDMA_REG 0x04 - -#define CMD_HD_ONEBIT_MODE 0x00 -#define CMD_HD_DOUT_MODE 0x10 -#define CMD_HD_QOUT_MODE 0x20 -#define CMD_HD_DIO_MODE 0x50 -#define CMD_HD_QIO_MODE 0xA0 - -#define CMD_HD_SEG_END_REG 0x05 -#define CMD_HD_EN_QPI_REG 0x06 -#define CMD_HD_WR_END_REG 0x07 -#define CMD_HD_INT0_REG 0x08 -#define CMD_HD_INT1_REG 0x09 -#define CMD_HD_INT2_REG 0x0A -#define CMD_HD_EX_QPI_REG 0xDD - -#define SPI_SLAVE_HD_BUFFER_SIZE 64 diff --git a/components/esp_serial_slave_link/include/essl_spi/esp32s2_defs.h b/components/esp_serial_slave_link/include/essl_spi/esp32s2_defs.h deleted file mode 100644 index 49ba82ddf0..0000000000 --- a/components/esp_serial_slave_link/include/essl_spi/esp32s2_defs.h +++ /dev/null @@ -1,38 +0,0 @@ -// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - - -#pragma once - -// NOTE: From the view of master -#define CMD_HD_WRBUF_REG 0x01 -#define CMD_HD_RDBUF_REG 0x02 -#define CMD_HD_WRDMA_REG 0x03 -#define CMD_HD_RDDMA_REG 0x04 - -#define CMD_HD_ONEBIT_MODE 0x00 -#define CMD_HD_DOUT_MODE 0x10 -#define CMD_HD_QOUT_MODE 0x20 -#define CMD_HD_DIO_MODE 0x50 -#define CMD_HD_QIO_MODE 0xA0 - -#define CMD_HD_SEG_END_REG 0x05 -#define CMD_HD_EN_QPI_REG 0x06 -#define CMD_HD_WR_END_REG 0x07 -#define CMD_HD_INT0_REG 0x08 -#define CMD_HD_INT1_REG 0x09 -#define CMD_HD_INT2_REG 0x0A -#define CMD_HD_EX_QPI_REG 0xDD - -#define SPI_SLAVE_HD_BUFFER_SIZE 72 diff --git a/components/esp_serial_slave_link/include/essl_spi/esp32s3_defs.h b/components/esp_serial_slave_link/include/essl_spi/esp32s3_defs.h deleted file mode 100644 index 3dfd4a14b7..0000000000 --- a/components/esp_serial_slave_link/include/essl_spi/esp32s3_defs.h +++ /dev/null @@ -1,38 +0,0 @@ -// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - - -#pragma once - -// NOTE: From the view of master -#define CMD_HD_WRBUF_REG 0x01 -#define CMD_HD_RDBUF_REG 0x02 -#define CMD_HD_WRDMA_REG 0x03 -#define CMD_HD_RDDMA_REG 0x04 - -#define CMD_HD_ONEBIT_MODE 0x00 -#define CMD_HD_DOUT_MODE 0x10 -#define CMD_HD_QOUT_MODE 0x20 -#define CMD_HD_DIO_MODE 0x50 -#define CMD_HD_QIO_MODE 0xA0 - -#define CMD_HD_SEG_END_REG 0x05 -#define CMD_HD_EN_QPI_REG 0x06 -#define CMD_HD_WR_END_REG 0x07 -#define CMD_HD_INT0_REG 0x08 -#define CMD_HD_INT1_REG 0x09 -#define CMD_HD_INT2_REG 0x0A -#define CMD_HD_EX_QPI_REG 0xDD - -#define SPI_SLAVE_HD_BUFFER_SIZE 64 diff --git a/components/esp_system/CMakeLists.txt b/components/esp_system/CMakeLists.txt index 620396fcfd..d8da31a837 100644 --- a/components/esp_system/CMakeLists.txt +++ b/components/esp_system/CMakeLists.txt @@ -21,11 +21,20 @@ else() "startup.c" "system_time.c" "stack_check.c" - "task_wdt.c" "ubsan.c" "xt_wdt.c" "debug_stubs.c") + if(CONFIG_ESP_TASK_WDT_EN) + list(APPEND srcs "task_wdt/task_wdt.c") + + if(CONFIG_ESP_TASK_WDT_USE_ESP_TIMER) + list(APPEND srcs "task_wdt/task_wdt_impl_esp_timer.c") + else() + list(APPEND srcs "task_wdt/task_wdt_impl_timergroup.c") + endif() + endif() + if(CONFIG_ESP_SYSTEM_USE_EH_FRAME) list(APPEND srcs "eh_frame_parser.c") endif() @@ -85,7 +94,7 @@ endif() # need to introduce panic "event" concept to remove this dependency (IDF-2194) idf_component_optional_requires(PRIVATE esp_gdbstub) -idf_component_optional_requires(PRIVATE app_update) +idf_component_optional_requires(PRIVATE esp_app_format) if(CONFIG_PM_ENABLE) idf_component_optional_requires(PRIVATE pm) diff --git a/components/esp_system/Kconfig b/components/esp_system/Kconfig index e3f1a51d6e..1fbb378ad2 100644 --- a/components/esp_system/Kconfig +++ b/components/esp_system/Kconfig @@ -91,6 +91,7 @@ menu "ESP System Settings" default y if IDF_TARGET_ESP32C3 default y if IDF_TARGET_ESP32S3 default y if IDF_TARGET_ESP32H2 + default y if IDF_TARGET_ESP32C6 depends on !IDF_TARGET_ESP32C2 config ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP @@ -301,6 +302,7 @@ menu "ESP System Settings" default 1 if IDF_TARGET_ESP32 default 20 if IDF_TARGET_ESP32C2 default 21 if IDF_TARGET_ESP32C3 + default 16 if IDF_TARGET_ESP32C6 default 43 help This GPIO is used for console UART TX output in the ESP-IDF Bootloader and the app (including @@ -316,6 +318,7 @@ menu "ESP System Settings" default 3 if IDF_TARGET_ESP32 default 19 if IDF_TARGET_ESP32C2 default 20 if IDF_TARGET_ESP32C3 + default 17 if IDF_TARGET_ESP32C6 default 44 help This GPIO is used for UART RX input in the ESP-IDF Bootloader and the app (including @@ -367,7 +370,6 @@ menu "ESP System Settings" config ESP_INT_WDT bool "Interrupt watchdog" - default n if IDF_TARGET_ESP32C2 # add support in IDF-4114 default y help This watchdog timer can detect if the FreeRTOS tick interrupt has not been called for a certain time, @@ -391,19 +393,36 @@ menu "ESP System Settings" help Also detect if interrupts on CPU 1 are disabled for too long. - config ESP_TASK_WDT - bool "Initialize Task Watchdog Timer on startup" + config ESP_TASK_WDT_EN + bool "Enable Task Watchdog Timer" default y select FREERTOS_ENABLE_TASK_SNAPSHOT help The Task Watchdog Timer can be used to make sure individual tasks are still - running. Enabling this option will cause the Task Watchdog Timer to be - initialized automatically at startup. The Task Watchdog timer can be - initialized after startup as well (see Task Watchdog Timer API Reference) + running. Enabling this option will enable the Task Watchdog Timer. It can be + either initialized automatically at startup or initialized after startup + (see Task Watchdog Timer API Reference) + + config ESP_TASK_WDT_USE_ESP_TIMER + # Software implementation of Task Watchdog, handy for targets with only a single + # Timer Group, such as the ESP32-C2 + bool + depends on ESP_TASK_WDT_EN + default y if IDF_TARGET_ESP32C2 + default n if !IDF_TARGET_ESP32C2 + select ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD + + config ESP_TASK_WDT_INIT + bool "Initialize Task Watchdog Timer on startup" + depends on ESP_TASK_WDT_EN + default y + help + Enabling this option will cause the Task Watchdog Timer to be initialized + automatically at startup. config ESP_TASK_WDT_PANIC bool "Invoke panic handler on Task Watchdog timeout" - depends on ESP_TASK_WDT + depends on ESP_TASK_WDT_INIT default n help If this option is enabled, the Task Watchdog Timer will be configured to @@ -412,7 +431,7 @@ menu "ESP System Settings" config ESP_TASK_WDT_TIMEOUT_S int "Task Watchdog timeout period (seconds)" - depends on ESP_TASK_WDT + depends on ESP_TASK_WDT_INIT range 1 60 default 5 help @@ -421,7 +440,7 @@ menu "ESP System Settings" config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 bool "Watch CPU0 Idle Task" - depends on ESP_TASK_WDT + depends on ESP_TASK_WDT_INIT default y help If this option is enabled, the Task Watchdog Timer will watch the CPU0 @@ -432,10 +451,10 @@ menu "ESP System Settings" config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1 bool "Watch CPU1 Idle Task" - depends on ESP_TASK_WDT && !FREERTOS_UNICORE + depends on ESP_TASK_WDT_INIT && !FREERTOS_UNICORE default y help - If this option is enabled, the Task Wtachdog Timer will wach the CPU1 + If this option is enabled, the Task Watchdog Timer will wach the CPU1 Idle Task. config ESP_XT_WDT diff --git a/components/esp_system/crosscore_int.c b/components/esp_system/crosscore_int.c index 4aae2a2540..2fda084714 100644 --- a/components/esp_system/crosscore_int.c +++ b/components/esp_system/crosscore_int.c @@ -21,7 +21,7 @@ #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 #include "soc/dport_reg.h" -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 +#else #include "soc/system_reg.h" #endif @@ -29,7 +29,7 @@ #define REASON_FREQ_SWITCH BIT(1) #define REASON_GDB_CALL BIT(3) -#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 && !IDF_TARGET_ESP32C2 +#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 && !IDF_TARGET_ESP32C2 && !IDF_TARGET_ESP32C6 #define REASON_PRINT_BACKTRACE BIT(2) #define REASON_TWDT_ABORT BIT(4) #endif @@ -66,7 +66,7 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) { } else { WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, 0); } -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0); #endif @@ -96,12 +96,14 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) { esp_backtrace_print(100); } +#if CONFIG_ESP_TASK_WDT_EN if (my_reason_val & REASON_TWDT_ABORT) { extern void task_wdt_timeout_abort_xtensa(bool); /* Called from a crosscore interrupt, thus, we are not the core that received * the TWDT interrupt, call the function with `false` as a parameter. */ task_wdt_timeout_abort_xtensa(false); } +#endif // CONFIG_ESP_TASK_WDT_EN #endif // CONFIG_IDF_TARGET_ARCH_XTENSA } @@ -145,7 +147,7 @@ static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask) } else { WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, SYSTEM_CPU_INTR_FROM_CPU_1); } -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0); #endif } @@ -165,13 +167,15 @@ void IRAM_ATTR esp_crosscore_int_send_gdb_call(int core_id) esp_crosscore_int_send(core_id, REASON_GDB_CALL); } -#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 && !IDF_TARGET_ESP32C2 +#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 && !IDF_TARGET_ESP32C2 && !IDF_TARGET_ESP32C6 void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id) { esp_crosscore_int_send(core_id, REASON_PRINT_BACKTRACE); } +#if CONFIG_ESP_TASK_WDT_EN void IRAM_ATTR esp_crosscore_int_send_twdt_abort(int core_id) { esp_crosscore_int_send(core_id, REASON_TWDT_ABORT); } +#endif // CONFIG_ESP_TASK_WDT_EN #endif diff --git a/components/esp_system/esp_system.c b/components/esp_system/esp_system.c index 0767a874fd..d8c473a95e 100644 --- a/components/esp_system/esp_system.c +++ b/components/esp_system/esp_system.c @@ -11,9 +11,9 @@ #include "freertos/task.h" #include "esp_cpu.h" #include "soc/rtc.h" -#include "soc/rtc_cntl_reg.h" #include "esp_private/panic_internal.h" #include "esp_rom_uart.h" +#include "esp_rom_sys.h" #if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE #if CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/memprot.h" @@ -42,7 +42,7 @@ void IRAM_ATTR esp_restart_noos_dig(void) esp_cpu_unstall(PRO_CPU_NUM); #endif // reset the digital part - SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); + esp_rom_software_reset_system(); while (true) { ; } diff --git a/components/esp_system/fpga_overrides.c b/components/esp_system/fpga_overrides.c index 70f5fa3850..b46ceaad98 100644 --- a/components/esp_system/fpga_overrides.c +++ b/components/esp_system/fpga_overrides.c @@ -9,7 +9,21 @@ #include "soc/system_reg.h" #endif // not CONFIG_IDF_TARGET_ESP32 #include "soc/rtc.h" -#include "soc/rtc_cntl_reg.h" +#if CONFIG_IDF_TARGET_ESP32 +#include "esp32/rom/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32S2 +#include "esp32s2/rom/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32C3 +#include "esp32c3/rom/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32H2 +#include "esp32h2/rom/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32C2 +#include "esp32c2/rom/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/rtc.h" +#endif #include "esp_log.h" #include "esp_rom_sys.h" #include "esp_rom_uart.h" @@ -17,13 +31,6 @@ static const char *TAG = "fpga"; -#ifdef CONFIG_IDF_TARGET_ESP32 -#include "esp32/rom/rtc.h" -#endif -#ifdef CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/rom/rtc.h" -#endif - extern void ets_update_cpu_frequency(uint32_t ticks_per_us); static void s_warn(void) @@ -42,13 +49,13 @@ void bootloader_clock_configure(void) #elif CONFIG_IDF_TARGET_ESP32H2 uint32_t apb_freq_hz = 32000000; #else - uint32_t apb_freq_hz = 40000000; + uint32_t apb_freq_hz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * 1000000; #endif // CONFIG_IDF_TARGET_ESP32S2 ets_update_cpu_frequency(apb_freq_hz / 1000000); #ifdef RTC_APB_FREQ_REG REG_WRITE(RTC_APB_FREQ_REG, (apb_freq_hz >> 12) | ((apb_freq_hz >> 12) << 16)); #endif - REG_WRITE(RTC_CNTL_STORE4_REG, (xtal_freq_mhz) | ((xtal_freq_mhz) << 16)); + REG_WRITE(RTC_XTAL_FREQ_REG, (xtal_freq_mhz) | ((xtal_freq_mhz) << 16)); } /* Placed in IRAM since test_apps expects it to be */ diff --git a/components/esp_system/include/esp_ipc_isr.h b/components/esp_system/include/esp_ipc_isr.h index 22fa5b10b0..70290ba561 100644 --- a/components/esp_system/include/esp_ipc_isr.h +++ b/components/esp_system/include/esp_ipc_isr.h @@ -62,6 +62,7 @@ void esp_ipc_isr_asm_call_blocking(esp_ipc_isr_func_t func, void* arg); * - If the stall feature is paused using esp_ipc_isr_stall_pause(), this function will have no effect * * @note This function is not available in single-core mode. + * @note It is the caller's responsibility to avoid deadlocking on spinlocks */ void esp_ipc_isr_stall_other_cpu(void); diff --git a/components/esp_system/include/esp_private/critical_section.h b/components/esp_system/include/esp_private/critical_section.h new file mode 100644 index 0000000000..4cee457300 --- /dev/null +++ b/components/esp_system/include/esp_private/critical_section.h @@ -0,0 +1,383 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * This file provides an abstract OS API for entering and exiting critical sections. + * It furthermore provides macros to define and initialize an optional spinlock + * if the used chip is a multi-core chip. If a single-core chip is used, just disabling interrupts + * is sufficient to guarantee consecutive, non-interrupted execution of a critical section. + * Hence, the spinlock is unneccessary and will be automatically ommitted by the macros. + */ +#pragma once + +#include "freertos/portmacro.h" +#include "spinlock.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if CONFIG_FREERTOS_UNICORE && !CONFIG_IDF_TARGET_ESP32S2 +/** + * This macro also helps users switching between spinlock declarations/definitions for multi-/single core environments + * if the macros below aren't sufficient. + */ +#define OS_SPINLOCK 0 +#else +#define OS_SPINLOCK 1 +#endif + +#if OS_SPINLOCK == 1 +typedef spinlock_t esp_os_spinlock_t; +#endif + +/** + * Define and initialize a static (internal linking) lock for entering critical sections. + * + * Use this when all the critical sections are local inside a file. + * The lock will only be defined if built for a multi-core system, otherwise it is unnecessary. + * + * @note When using this macro, the critical section macros esp_os_enter_critical* and esp_os_exit_critical* + * MUST be used, otherwise normal functions would be passed an undefined variable when build for single-core systems. + * + * @param lock_name Variable name of the lock. This will later be used to reference the declared lock. + * @param optional_qualifiers Qualifiers such as DRAM_ATTR and other attributes. Can be omitted if no qualifiers are + * required. + * + * Example usage: + * @code{c} + * ... + * #include "os/critical_section.h" + * ... + * DEFINE_CRIT_SECTION_LOCK_STATIC(my_lock); // will have internal linking (static) + * ... + * esp_os_enter_critical(&my_lock); + * ... + * esp_os_exit_critical(&my_lock); + * @endcode + */ +#if OS_SPINLOCK == 1 +#define DEFINE_CRIT_SECTION_LOCK_STATIC(lock_name, optional_qualifiers...) static optional_qualifiers esp_os_spinlock_t lock_name = SPINLOCK_INITIALIZER +#else +#define DEFINE_CRIT_SECTION_LOCK_STATIC(lock_name, optional_qualifiers...) +#endif + +/** + * Define and initialize a non-static (external linking) lock for entering critical sections. + * + * Locks defined by this macro can be linked among object files but this rather exceptional. + * Prefer the static lock definition whenever possible. + * The lock will only be defined if built for a multi-core system, otherwise it is unnecessary. + * + * @note When using this macro, the critical section macros esp_os_enter_critical* and esp_os_exit_critical* + * MUST be used, otherwise normal functions would be passed an undefined variable when build for single-core systems. + * + * @param lock_name Variable name of the lock. This will later be used to reference the declared lock. + * @param optional_qualifiers Qualifiers such as DRAM_ATTR and other attributes. Can be omitted if no qualifiers are + * required. + * + * Example usage: + * @code{c} + * ... + * #include "os/critical_section.h" + * ... + * DEFINE_CRIT_SECTION_LOCK(my_lock); // will have external linking (non-static) + * ... + * esp_os_enter_critical(&my_lock); + * ... + * esp_os_exit_critical(&my_lock); + * @endcode + */ +#if OS_SPINLOCK == 1 +#define DEFINE_CRIT_SECTION_LOCK(lock_name, optional_qualifiers...) optional_qualifiers esp_os_spinlock_t lock_name = SPINLOCK_INITIALIZER +#else +#define DEFINE_CRIT_SECTION_LOCK(lock_name, optional_qualifiers...) +#endif + +/** + * @brief This macro initializes a critical section lock at runtime. + * + * This macro basically creates a member of the initialization list, including the trailing comma. + * If the lock is unnecessary because the architecture is single-core, this macro will not do anything. + * This is incompatible with a lock created by DEFINE_CRIT_SECTION_LOCK_STATIC from above. + * + * @param lock_name Pointer to the lock. + * + * @note When using this macro, the critical section macros esp_os_enter_critical* and esp_os_exit_critical* + * MUST be used, otherwise normal functions would be passed an undefined variable when build for single-core + * systems. + * + * Example usage: + * @code{c} + * ... + * #include "os/critical_section.h" + * ... + * typedef struct protected_struct_t { + * int member1; + * DECLARE_CRIT_SECTION_LOCK_IN_STRUCT(my_lock) + * int another_member; + * }; + * ... + * protected_struct_t my_protected; + * INIT_CRIT_SECTION_LOCK_IN_STRUCT(&(my_protected.my_lock)); + * }; + * @endcode + */ +#if OS_SPINLOCK == 1 +#define INIT_CRIT_SECTION_LOCK_RUNTIME(lock_name) spinlock_initialize(lock_name) +#else +#define INIT_CRIT_SECTION_LOCK_RUNTIME(lock_name) +#endif + +/** + * @brief This macro declares a critical section lock as a member of a struct. + * + * The critical section lock member is only declared if built for multi-core systems, otherwise it is omitted. + * + * @note When using this macro, the critical section macros esp_os_enter_critical* and esp_os_exit_critical* + * MUST be used, otherwise normal functions would be passed an undefined variable when build for single-core + * systems. + * @note Do NOT add any semicolon after declaring the member with this macro. + * The trailing semicolon is included in the macro, otherwise -Wpedantic would complain about + * superfluous ";" if OS_SPINLOCK == 0. + * + * Example usage: + * @code{c} + * ... + * #include "os/critical_section.h" + * ... + * typedef struct protected_struct_t { + * int member1; + * DECLARE_CRIT_SECTION_LOCK_IN_STRUCT(my_lock) // no semicolon! + * int another_member; + * }; + * @endcode + */ +#if OS_SPINLOCK == 1 +#define DECLARE_CRIT_SECTION_LOCK_IN_STRUCT(lock_name) esp_os_spinlock_t lock_name; +#else +#define DECLARE_CRIT_SECTION_LOCK_IN_STRUCT(lock_name) +#endif + +/** + * @brief This macro initializes a critical section lock as a member of a struct when using an list initialization. + * It has to be used together with \c DECLARE_CRIT_SECTION_LOCK_IN_STRUCT() to work. + * + * This macro basically creates a member of the initialization list, including the trailing comma. + * If the lock is unnecessary because the architecture is single-core, this macro will not do anything. + * This means that if \c lock_name is still a member of the struct, \c lock_name will be uninitialized. + * Hence, this macro has to be used together with \c DECLARE_CRIT_SECTION_LOCK_IN_STRUCT() to correctly to declare + * or omit the struct member \c lock_name. + * + * @param lock_name The field name of the lock inside the struct. + * + * @note When using this macro, the critical section macros esp_os_enter_critical* and esp_os_exit_critical* + * MUST be used, otherwise normal functions would be passed an undefined variable when build for single-core + * systems. + * @note Do NOT add any comma in the initializer list after using this macro. + * + * Example usage: + * @code{c} + * ... + * #include "os/critical_section.h" + * ... + * typedef struct protected_struct_t { + * int member1; + * DECLARE_CRIT_SECTION_LOCK_IN_STRUCT(my_lock) + * int another_member; + * }; + * ... + * protected_struct_t my_protected = { + * .member1 = 0, + * INIT_CRIT_SECTION_LOCK_IN_STRUCT(my_lock) // no comma! + * another_member = 47, + * }; + * @endcode + */ +#if OS_SPINLOCK == 1 +#define INIT_CRIT_SECTION_LOCK_IN_STRUCT(lock_name) .lock_name = portMUX_INITIALIZER_UNLOCKED, +#else +#define INIT_CRIT_SECTION_LOCK_IN_STRUCT(lock_name) +#endif + +/** + * @brief Enter a critical section, i.e., a section that will not be interrupted by any other task or interrupt. + * + * On multi-core systems, this will disable interrupts and take the spinlock \c lock. On single core systems, a + * spinlock is unncessary, hence \c lock is ignored and interrupts are disabled only. + * + * @note This macro MUST be used together with any of the initialization macros, e.g. + * DEFINE_CRIT_SECTION_LOCK_STATIC. If not, there may be unused variables. + * + * @param lock Pointer to the critical section lock. Ignored if build for single core system. + * + * Example usage with static locks: + * @code{c} + * ... + * #include "os/critical_section.h" + * ... + * DEFINE_CRIT_SECTION_LOCK_STATIC(my_lock); // will have internal linking (static) + * ... + * esp_os_enter_critical(&my_lock); + * // code inside critical section + * esp_os_exit_critical(&my_lock); + * @endcode + */ +#if OS_SPINLOCK == 1 +#define esp_os_enter_critical(lock) portENTER_CRITICAL(lock) +#else +#define esp_os_enter_critical(lock) vPortEnterCritical() +#endif + +/** + * @brief Exit a critical section. + * + * On multi-core systems, this will enable interrupts and release the spinlock \c lock. On single core systems, a + * spinlock is unncessary, hence \c lock is ignored and interrupts are enabled only. + * + * @note This macro MUST be used together with any of the initialization macros, e.g. + * DEFINE_CRIT_SECTION_LOCK_STATIC. If not, there may be unused variables. + * + * @param lock Pointer to the critical section lock. Ignored if build for single core system. + * + * Example usage with static locks: + * @code{c} + * ... + * #include "os/critical_section.h" + * ... + * DEFINE_CRIT_SECTION_LOCK_STATIC(my_lock); // will have internal linking (static) + * ... + * esp_os_enter_critical(&my_lock); + * // code inside critical section + * esp_os_exit_critical(&my_lock); + * @endcode + */ +#if OS_SPINLOCK == 1 +#define esp_os_exit_critical(lock) portEXIT_CRITICAL(lock) +#else +#define esp_os_exit_critical(lock) vPortExitCritical() +#endif + +/** + * @brief Enter a critical section while from ISR. + * + * On multi-core systems, this will disable interrupts and take the spinlock \c lock. On single core systems, a + * spinlock is unncessary, hence \c lock is ignored and interrupts are disabled only. + * + * @note This macro MUST be used together with any of the initialization macros, e.g. + * DEFINE_CRIT_SECTION_LOCK_STATIC. If not, there may be unused variables. + * + * @param lock Pointer to the critical section lock. Ignored if build for single core system. + * + * Example usage with static locks: + * @code{c} + * ... + * #include "os/critical_section.h" + * ... + * DEFINE_CRIT_SECTION_LOCK_STATIC(my_lock); // will have internal linking (static) + * ... + * esp_os_enter_critical(&my_lock); + * // code inside critical section + * esp_os_exit_critical(&my_lock); + * @endcode + */ +#if OS_SPINLOCK == 1 +#define esp_os_enter_critical_isr(lock) portENTER_CRITICAL_ISR(lock) +#else +#define esp_os_enter_critical_isr(lock) vPortEnterCritical() +#endif + +/** + * @brief Exit a critical section after entering from ISR. + * + * On multi-core systems, this will enable interrupts and release the spinlock \c lock. On single core systems, a + * spinlock is unncessary, hence \c lock is ignored and interrupts are enabled only. + * + * @note This macro MUST be used together with any of the initialization macros, e.g. + * DEFINE_CRIT_SECTION_LOCK_STATIC. If not, there may be unused variables. + * + * @param lock Pointer to the critical section lock. Ignored if build for single core system. + * + * Example usage with static locks: + * @code{c} + * ... + * #include "os/critical_section.h" + * ... + * DEFINE_CRIT_SECTION_LOCK_STATIC(my_lock); // will have internal linking (static) + * ... + * esp_os_enter_critical(&my_lock); + * // code inside critical section + * esp_os_exit_critical(&my_lock); + * @endcode + */ +#if OS_SPINLOCK == 1 +#define esp_os_exit_critical_isr(lock) portEXIT_CRITICAL_ISR(lock) +#else +#define esp_os_exit_critical_isr(lock) vPortExitCritical() +#endif + +/** + * @brief Enter a critical section from normal task or ISR. This macro will check if the current CPU is processing + * an ISR or not and enter the critical section accordingly. + * + * On multi-core systems, this will disable interrupts and take the spinlock \c lock. On single core systems, a + * spinlock is unncessary, hence \c lock is ignored and interrupts are disabled only. + * + * @note This macro MUST be used together with any of the initialization macros, e.g. + * DEFINE_CRIT_SECTION_LOCK_STATIC. If not, there may be unused variables. + * + * @param lock Pointer to the critical section lock. Ignored if build for single core system. + * + * Example usage with static locks: + * @code{c} + * ... + * #include "os/critical_section.h" + * ... + * DEFINE_CRIT_SECTION_LOCK_STATIC(my_lock); // will have internal linking (static) + * ... + * esp_os_enter_critical(&my_lock); + * // code inside critical section + * esp_os_exit_critical(&my_lock); + * @endcode + */ +#if OS_SPINLOCK == 1 +#define esp_os_enter_critical_safe(lock) portENTER_CRITICAL_SAFE(lock) +#else +#define esp_os_enter_critical_safe(lock) vPortEnterCritical() +#endif + +/** + * @brief Exit a critical section after entering via esp_os_enter_critical_safe. + * + * On multi-core systems, this will enable interrupts and release the spinlock \c lock. On single core systems, a + * spinlock is unncessary, hence \c lock is ignored and interrupts are enabled only. + * + * @note This macro MUST be used together with any of the initialization macros, e.g. + * DEFINE_CRIT_SECTION_LOCK_STATIC. If not, there may be unused variables. + * + * @param lock Pointer to the critical section lock. Ignored if build for single core system. + * + * Example usage with static locks: + * @code{c} + * ... + * #include "os/critical_section.h" + * ... + * DEFINE_CRIT_SECTION_LOCK_STATIC(my_lock); // will have internal linking (static) + * ... + * esp_os_enter_critical(&my_lock); + * // code inside critical section + * esp_os_exit_critical(&my_lock); + * @endcode + */ +#if OS_SPINLOCK == 1 +#define esp_os_exit_critical_safe(lock) portEXIT_CRITICAL_SAFE(lock) +#else +#define esp_os_exit_critical_safe(lock) vPortExitCritical() +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_system/include/esp_private/crosscore_int.h b/components/esp_system/include/esp_private/crosscore_int.h index 0acdbb8159..1325c2a055 100644 --- a/components/esp_system/include/esp_private/crosscore_int.h +++ b/components/esp_system/include/esp_private/crosscore_int.h @@ -50,7 +50,7 @@ void esp_crosscore_int_send_freq_switch(int core_id); void esp_crosscore_int_send_gdb_call(int core_id); -#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C2 +#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6 /** * Send an interrupt to a CPU indicating it should print its current backtrace * @@ -61,6 +61,7 @@ void esp_crosscore_int_send_gdb_call(int core_id); */ void esp_crosscore_int_send_print_backtrace(int core_id); +#if CONFIG_ESP_TASK_WDT_EN /** * Send an interrupt to a CPU indicating it call `task_wdt_timeout_abort_xtensa`. * This will make the CPU abort, using the interrupted task frame. @@ -72,7 +73,9 @@ void esp_crosscore_int_send_print_backtrace(int core_id); * @param core_id Core that should abort */ void esp_crosscore_int_send_twdt_abort(int core_id); -#endif + +#endif // CONFIG_ESP_TASK_WDT_EN +#endif // !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6 #ifdef __cplusplus } diff --git a/components/esp_system/include/esp_private/esp_int_wdt.h b/components/esp_system/include/esp_private/esp_int_wdt.h index 38cd30bb7b..18746d0298 100644 --- a/components/esp_system/include/esp_private/esp_int_wdt.h +++ b/components/esp_system/include/esp_private/esp_int_wdt.h @@ -6,10 +6,32 @@ #pragma once +#include "system_internal.h" +#include "soc/periph_defs.h" + #ifdef __cplusplus extern "C" { #endif +#if SOC_TIMER_GROUPS > 1 + +/* If we have two hardware timer groups, use the second one for interrupt watchdog. */ +#define WDT_LEVEL_INTR_SOURCE ETS_TG1_WDT_LEVEL_INTR_SOURCE +#define IWDT_PRESCALER MWDT1_TICK_PRESCALER // Tick period of 500us if WDT source clock is 80MHz +#define IWDT_TICKS_PER_US MWDT1_TICKS_PER_US +#define IWDT_INSTANCE WDT_MWDT1 +#define IWDT_INITIAL_TIMEOUT_S 5 + +#else + +#define WDT_LEVEL_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE +#define IWDT_PRESCALER MWDT0_TICK_PRESCALER // Tick period of 500us if WDT source clock is 80MHz +#define IWDT_TICKS_PER_US MWDT0_TICKS_PER_US +#define IWDT_INSTANCE WDT_MWDT0 +#define IWDT_INITIAL_TIMEOUT_S 5 + +#endif // SOC_TIMER_GROUPS > 1 + /** * @brief Initialize the non-CPU-specific parts of interrupt watchdog. * diff --git a/components/esp_system/include/esp_private/esp_task_wdt.h b/components/esp_system/include/esp_private/esp_task_wdt.h new file mode 100644 index 0000000000..ab9548e544 --- /dev/null +++ b/components/esp_system/include/esp_private/esp_task_wdt.h @@ -0,0 +1,57 @@ +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "sdkconfig.h" +#include "esp_err.h" + +#if CONFIG_ESP_TASK_WDT_EN + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Type used to define the context of a Task WatchDog Timer implementation. + * This is used internally in the TWDT driver, it is implementation specific. + */ +typedef void* twdt_ctx_t; + +/** + * @brief Type of the function used as an ISR callback. + */ +typedef void (*twdt_isr_callback)(void*); + +/** + * @brief Stop the Task Watchdog Timer (TWDT) + * + * This function will temporarily stop the timer until it is restarted by a call to esp_task_wdt_restart(). + + * @note esp_task_wdt_stop() must not be called by multiple tasks simultaneously. + * @return + * - ESP_OK: TWDT successfully stopped + * - Other: Failed to stop the TWDT + */ +esp_err_t esp_task_wdt_stop(void); + +/** + * @brief Restart the Task Watchdog Timer (TWDT) + * + * This function will restart the timer after it has been stopped by esp_task_wdt_stop(). + + * @note esp_task_wdt_restart() must not be called by multiple tasks simultaneously. + * @return + * - ESP_OK: TWDT successfully stopped + * - Other: Failed to stop the TWDT + */ +esp_err_t esp_task_wdt_restart(void); + +#ifdef __cplusplus +} +#endif + +#endif // CONFIG_ESP_TASK_WDT_EN diff --git a/components/esp_system/include/esp_private/esp_task_wdt_impl.h b/components/esp_system/include/esp_private/esp_task_wdt_impl.h new file mode 100644 index 0000000000..43adc3238f --- /dev/null +++ b/components/esp_system/include/esp_private/esp_task_wdt_impl.h @@ -0,0 +1,101 @@ +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_err.h" +#include "../esp_task_wdt.h" +#include "esp_private/esp_task_wdt.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief Allocate and initialize the Task Watchdog Timer (TWDT) with the given configuration. + * + * @param[in] config Pointer to the configuration structure + * @param[out] obj Abstract context for the current timer, this will be passed to all the other functions + * + * @return + * - ESP_OK: Successfully initialized and configured the timer + * - Other: Failed to initialize the timer + */ +esp_err_t esp_task_wdt_impl_timer_allocate(const esp_task_wdt_config_t *config, + twdt_isr_callback callback, + twdt_ctx_t *obj); + + +/** + * @brief Reconfigure a timer. + * + * The timer must be stopped when calling this function. The timer will not be restarted at the end of this + * function. + * + * @param[in] config Pointer to the configuration structure + * + * @return + * - ESP_OK: Successfully reconfigured the timer + * - Other: Failed to reconfigure the timer + */ +esp_err_t esp_task_wdt_impl_timer_reconfigure(twdt_ctx_t obj, const esp_task_wdt_config_t *config); + +/** + * @brief Free the Task Watchdog Timer (TWDT). + * + * @param[in] obj Abstract implementation context + * + */ +void esp_task_wdt_impl_timer_free(twdt_ctx_t obj); + + +/** + * @brief Feed the Task Watchdog Timer (TWDT) + * + * Feed the timer underneath to prevent it from triggering for the next period (configured at initialization). + * + * @param[in] obj Abstract implementation context + * @return + * - ESP_OK: timer successfully feeded + * - Other: failed to feed the timer + */ +esp_err_t esp_task_wdt_impl_timer_feed(twdt_ctx_t obj); + + +/** + * @brief Function invoked as soon as the Task Watchdog Timer (TWDT) ISR callback is called. + * + * @param[in] obj Abstract implementation context + */ +void esp_task_wdt_impl_timeout_triggered(twdt_ctx_t obj); + + +/** + * @brief Stop the Task Watchdog Timer (TWDT). + * + * @param[in] obj Abstract implementation context + * + */ +esp_err_t esp_task_wdt_impl_timer_stop(twdt_ctx_t obj); + + +/** + * @brief Restart the Task Watchdog Timer (TWDT) + * + * This function will restart/resume the timer after it has been stopped. + * + * @param[in] obj Abstract implementation context + * @return + * - ESP_OK: timer successfully stopped + * - Other: failed to stop the timer + */ +esp_err_t esp_task_wdt_impl_timer_restart(twdt_ctx_t obj); + + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_system/include/esp_private/system_internal.h b/components/esp_system/include/esp_private/system_internal.h index 2125fa7ff4..6851a3fc85 100644 --- a/components/esp_system/include/esp_private/system_internal.h +++ b/components/esp_system/include/esp_private/system_internal.h @@ -1,16 +1,8 @@ -// Copyright 2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -19,12 +11,28 @@ extern "C" { #endif #include "esp_system.h" +#include "soc/soc_caps.h" +#if SOC_TIMER_GROUPS >= 2 + +/* All the targets that have more than one timer group are using + * APB clock by default, which frequency is 80MHz. + * Thus, we can determine the default parameter for the prescaler here */ #define MWDT0_TICK_PRESCALER 40000 #define MWDT0_TICKS_PER_US 500 #define MWDT1_TICK_PRESCALER 40000 #define MWDT1_TICKS_PER_US 500 +#else + +/* The targets that have a single timer group use a 40MHz clock for the + * Timer Group 0. Let's adapt the prescaler value accordingly. + */ +#define MWDT0_TICK_PRESCALER 20000 +#define MWDT0_TICKS_PER_US 500 + +#endif + /** * @brief Internal function to restart PRO and APP CPUs. * diff --git a/components/esp_system/include/esp_task_wdt.h b/components/esp_system/include/esp_task_wdt.h index 3ca1b86b00..c5c1d5fa11 100644 --- a/components/esp_system/include/esp_task_wdt.h +++ b/components/esp_system/include/esp_task_wdt.h @@ -32,18 +32,36 @@ typedef struct esp_task_wdt_user_handle_s * esp_task_wdt_user_handle_t; /** * @brief Initialize the Task Watchdog Timer (TWDT) * - * This function configures and initializes the TWDT. If the TWDT is already initialized when this function is called, - * this function will update the TWDT's current configuration. This funciton will also subscribe the idle tasks if + * This function configures and initializes the TWDT. This function will subscribe the idle tasks if * configured to do so. For other tasks, users can subscribe them using esp_task_wdt_add() or esp_task_wdt_add_user(). + * This function won't start the timer if no task have been registered yet. * - * @note esp_task_wdt_init() must only be called after the scheduler is started + * @note esp_task_wdt_init() must only be called after the scheduler is started. Moreover, it must not be called by + * multiple tasks simultaneously. * @param[in] config Configuration structure * @return * - ESP_OK: Initialization was successful + * - ESP_ERR_INVALID_STATE: Already initialized * - Other: Failed to initialize TWDT */ esp_err_t esp_task_wdt_init(const esp_task_wdt_config_t *config); +/** + * @brief Reconfigure the Task Watchdog Timer (TWDT) + * + * The function reconfigures the running TWDT. It must already be initialized when this function is called. + * + * @note esp_task_wdt_reconfigure() must not be called by multiple tasks simultaneously. + * + * @param[in] config Configuration structure + * + * @return + * - ESP_OK: Reconfiguring was successful + * - ESP_ERR_INVALID_STATE: TWDT not initialized yet + * - Other: Failed to initialize TWDT + */ +esp_err_t esp_task_wdt_reconfigure(const esp_task_wdt_config_t *config); + /** * @brief Deinitialize the Task Watchdog Timer (TWDT) * @@ -51,6 +69,7 @@ esp_err_t esp_task_wdt_init(const esp_task_wdt_config_t *config); * are still subscribed to the TWDT, or when the TWDT is already deinitialized, will result in an error code being * returned. * + * @note esp_task_wdt_deinit() must not be called by multiple tasks simultaneously. * @return * - ESP_OK: TWDT successfully deinitialized * - Other: Failed to deinitialize TWDT @@ -150,6 +169,16 @@ esp_err_t esp_task_wdt_delete_user(esp_task_wdt_user_handle_t user_handle); */ esp_err_t esp_task_wdt_status(TaskHandle_t task_handle); +/** + * @brief User ISR callback placeholder + * + * This function is called by task_wdt_isr function (ISR for when TWDT times out). It can be defined in user code to + * handle TWDT events. + * + * @note It has the same limitations as the interrupt function. Do not use ESP_LOGx functions inside. + */ +void __attribute__((weak)) esp_task_wdt_isr_user_handler(void); + #ifdef __cplusplus } #endif diff --git a/components/esp_system/int_wdt.c b/components/esp_system/int_wdt.c index 298ba92b0d..c1f2afd1b4 100644 --- a/components/esp_system/int_wdt.c +++ b/components/esp_system/int_wdt.c @@ -20,16 +20,9 @@ #include "esp_freertos_hooks.h" #include "esp_private/periph_ctrl.h" #include "esp_private/esp_int_wdt.h" -#include "esp_private/system_internal.h" #if CONFIG_ESP_INT_WDT -#define WDT_INT_NUM ETS_T1_WDT_INUM -#define IWDT_INSTANCE WDT_MWDT1 -#define IWDT_PRESCALER MWDT1_TICK_PRESCALER // Tick period of 500us if WDT source clock is 80MHz -#define IWDT_TICKS_PER_US MWDT1_TICKS_PER_US -#define IWDT_INITIAL_TIMEOUT_S 5 - static wdt_hal_context_t iwdt_context; #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX @@ -131,7 +124,6 @@ void esp_int_wdt_init(void) void esp_int_wdt_cpu_init(void) { -#if SOC_TIMER_GROUPS > 1 assert((CONFIG_ESP_INT_WDT_TIMEOUT_MS >= (portTICK_PERIOD_MS << 1)) && "Interrupt watchdog timeout needs to be at least twice the RTOS tick period!"); // Register tick hook for current CPU to feed the INT WDT esp_register_freertos_tick_hook_for_cpu(tick_hook, esp_cpu_get_core_id()); @@ -139,11 +131,11 @@ void esp_int_wdt_cpu_init(void) * Register INT WDT interrupt for current CPU. We do this manually as the timeout interrupt should call an assembly * panic handler (see riscv/vector.S and xtensa_vectors.S). */ - esp_intr_disable_source(WDT_INT_NUM); - esp_rom_route_intr_matrix(esp_cpu_get_core_id(), ETS_TG1_WDT_LEVEL_INTR_SOURCE, WDT_INT_NUM); + esp_intr_disable_source(ETS_INT_WDT_INUM); + esp_rom_route_intr_matrix(esp_cpu_get_core_id(), WDT_LEVEL_INTR_SOURCE, ETS_INT_WDT_INUM); #if SOC_CPU_HAS_FLEXIBLE_INTC - esp_cpu_intr_set_type(WDT_INT_NUM, INTR_TYPE_LEVEL); - esp_cpu_intr_set_priority(WDT_INT_NUM, SOC_INTERRUPT_LEVEL_MEDIUM); + esp_cpu_intr_set_type(ETS_INT_WDT_INUM, INTR_TYPE_LEVEL); + esp_cpu_intr_set_priority(ETS_INT_WDT_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); #endif #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX /* @@ -157,11 +149,7 @@ void esp_int_wdt_cpu_init(void) _lx_intr_livelock_max = CONFIG_ESP_INT_WDT_TIMEOUT_MS / IWDT_LIVELOCK_TIMEOUT_MS - 1; } #endif - esp_intr_enable_source(WDT_INT_NUM); -#else // SOC_TIMER_GROUPS > 1 - // TODO: Clean up code for ESP32-C2, IDF-4114 - ESP_EARLY_LOGW("INT_WDT", "ESP32-C2 only has one timer group"); -#endif // SOC_TIMER_GROUPS > 1 + esp_intr_enable_source(ETS_INT_WDT_INUM); } #endif // CONFIG_ESP_INT_WDT diff --git a/components/esp_system/ld/esp32/sections.ld.in b/components/esp_system/ld/esp32/sections.ld.in index 29f581ef8e..5dffe85b09 100644 --- a/components/esp_system/ld/esp32/sections.ld.in +++ b/components/esp_system/ld/esp32/sections.ld.in @@ -245,6 +245,7 @@ SECTIONS .flash.appdesc : ALIGN(0x10) { + _rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */ _rodata_start = ABSOLUTE(.); *(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */ @@ -318,6 +319,7 @@ SECTIONS *(.tbss) *(.tbss.*) _thread_local_end = ABSOLUTE(.); + _rodata_reserved_end = ABSOLUTE(.); /* This is a symbol marking the flash.rodata end, this can be used for mmu driver to maintain virtual address */ . = ALIGN(4); } >default_rodata_seg @@ -332,6 +334,7 @@ SECTIONS .flash.text : { _stext = .; + _instruction_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */ _text_start = ABSOLUTE(.); mapping[flash_text] @@ -350,6 +353,7 @@ SECTIONS . += _esp_flash_mmap_prefetch_pad_size; _text_end = ABSOLUTE(.); + _instruction_reserved_end = ABSOLUTE(.); /* This is a symbol marking the flash.text end, this can be used for mmu driver to maintain virtual address */ _etext = .; /* Similar to _iram_start, this symbol goes here so it is diff --git a/components/esp_system/ld/esp32c6/memory.ld.in b/components/esp_system/ld/esp32c6/memory.ld.in new file mode 100644 index 0000000000..95178e726b --- /dev/null +++ b/components/esp_system/ld/esp32c6/memory.ld.in @@ -0,0 +1,149 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * ESP32-C6 Linker Script Memory Layout + * This file describes the memory layout (memory blocks) by virtual memory addresses. + * This linker script is passed through the C preprocessor to include configuration options. + * Please use preprocessor features sparingly! + * Restrict to simple macros with numeric values, and/or #if/#endif blocks. + */ + +#include "sdkconfig.h" +#include "ld.common" + +#ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC +#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE) +#elif defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP) +#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE) +#else +#define ESP_BOOTLOADER_RESERVE_RTC 0 +#endif + +/** + * physical memory is mapped twice to the vritual address (IRAM and DRAM). + * `I_D_SRAM_OFFSET` is the offset between the two locations of the same physical memory + */ +#define SRAM_IRAM_START 0x40800000 +#define SRAM_DRAM_START 0x40800000 + +#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START) +#define SRAM_DRAM_END 0x40880000 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */ + +#define SRAM_IRAM_ORG (SRAM_IRAM_START) +#define SRAM_DRAM_ORG (SRAM_DRAM_START) + +#define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG + +#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS +/* + * IDRAM0_2_SEG_SIZE_DEFAULT is used when page size is 64KB + */ +#define IDRAM0_2_SEG_SIZE (CONFIG_MMU_PAGE_SIZE << 8) +#endif + +#if CONFIG_ESP32C6_USE_FIXED_STATIC_RAM_SIZE +ASSERT((CONFIG_ESP32C6_FIXED_STATIC_RAM_SIZE <= I_D_SRAM_SIZE), "Fixed static ram data does not fit.") +#define DRAM0_0_SEG_LEN CONFIG_ESP3C6_FIXED_STATIC_RAM_SIZE +#else +#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE +#endif // CONFIG_ESP32C6_USE_FIXED_STATIC_RAM_SIZE +MEMORY +{ + /** + * All these values assume the flash cache is on, and have the blocks this uses subtracted from the length + * of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but + * are connected to the data port of the CPU and eg allow byte-wise access. + */ + + /* IRAM for PRO CPU. */ + iram0_0_seg (RX) : org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE + +#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS + /* Flash mapped instruction data */ + iram0_2_seg (RX) : org = 0x42000020, len = (IDRAM0_2_SEG_SIZE >> 1) -0x20 + + /** + * (0x20 offset above is a convenience for the app binary image generation. + * Flash cache has 64KB pages. The .bin file which is flashed to the chip + * has a 0x18 byte file header, and each segment has a 0x08 byte segment + * header. Setting this offset makes it simple to meet the flash cache MMU's + * constraint that (paddr % 64KB == vaddr % 64KB).) + */ +#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS + + /** + * Shared data RAM, excluding memory reserved for ROM bss/data/stack. + * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available. + */ + dram0_0_seg (RW) : org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN + +#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS + /* Flash mapped constant data */ + drom0_0_seg (R) : org = 0x42000020 + (IDRAM0_2_SEG_SIZE >> 1), len = (IDRAM0_2_SEG_SIZE >> 1)-0x20 + + /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */ +#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS + + /** + * lp ram memory (RWX). Persists over deep sleep. // TODO: IDF-5667 + */ +#if CONFIG_ULP_COPROC_ENABLED + lp_ram_seg(RW) : org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM, + len = 0x4000 - CONFIG_ULP_COPROC_RESERVE_MEM +#else + lp_ram_seg(RW) : org = 0x50000000 , len = 0x4000 +#endif // CONFIG_ULP_COPROC_ENABLED + +} + +#if CONFIG_ESP32C6_USE_FIXED_STATIC_RAM_SIZE +/* static data ends at defined address */ +_static_data_end = 0x40820000 + DRAM0_0_SEG_LEN; +#else +_static_data_end = _bss_end; +#endif // CONFIG_ESP32C6_USE_FIXED_STATIC_RAM_SIZE + +/* Heap ends at top of dram0_0_seg */ +_heap_end = 0x40000000; + +_data_seg_org = ORIGIN(rtc_data_seg); + +/** + * The lines below define location alias for .rtc.data section + * C6 has no distinguished LP(RTC) fast and slow memory sections, instead, there is a unified LP_RAM section + * Thus, the following region segments are not configurable like on other targets + */ +REGION_ALIAS("rtc_iram_seg", lp_ram_seg ); +REGION_ALIAS("rtc_data_seg", rtc_iram_seg ); +REGION_ALIAS("rtc_slow_seg", rtc_iram_seg ); +REGION_ALIAS("rtc_data_location", rtc_iram_seg ); + +#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS + REGION_ALIAS("default_code_seg", iram0_2_seg); +#else + REGION_ALIAS("default_code_seg", iram0_0_seg); +#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS + +#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS + REGION_ALIAS("default_rodata_seg", drom0_0_seg); +#else + REGION_ALIAS("default_rodata_seg", dram0_0_seg); +#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS + +/** + * If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must + * also be first in the segment. + */ +#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS + ASSERT(_flash_rodata_dummy_start == ORIGIN(default_rodata_seg), + ".flash_rodata_dummy section must be placed at the beginning of the rodata segment.") +#endif + +#if CONFIG_ESP_SYSTEM_USE_EH_FRAME + ASSERT ((__eh_frame_end > __eh_frame), "Error: eh_frame size is null!"); + ASSERT ((__eh_frame_hdr_end > __eh_frame_hdr), "Error: eh_frame_hdr size is null!"); +#endif diff --git a/components/esp_system/ld/esp32c6/sections.ld.in b/components/esp_system/ld/esp32c6/sections.ld.in new file mode 100644 index 0000000000..b32633a5e5 --- /dev/null +++ b/components/esp_system/ld/esp32c6/sections.ld.in @@ -0,0 +1,410 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Default entry point */ +ENTRY(call_start_cpu0); + +SECTIONS +{ + /** + * RTC fast memory holds RTC wake stub code, + * including from any source file named rtc_wake_stub*.c + */ + .rtc.text : + { + . = ALIGN(4); + _rtc_fast_start = ABSOLUTE(.); + + mapping[rtc_text] + + *rtc_wake_stub*.*(.literal .text .literal.* .text.*) + *(.rtc_text_end_test) + + /* 16B padding for possible CPU prefetch and 4B alignment for PMS split lines */ + . += _esp_memprot_prefetch_pad_size; + . = ALIGN(4); + + _rtc_text_end = ABSOLUTE(.); + } > lp_ram_seg + + /** + * This section located in RTC FAST Memory area. + * It holds data marked with RTC_FAST_ATTR attribute. + * See the file "esp_attr.h" for more information. + */ + .rtc.force_fast : + { + . = ALIGN(4); + _rtc_force_fast_start = ABSOLUTE(.); + + mapping[rtc_force_fast] + + *(.rtc.force_fast .rtc.force_fast.*) + . = ALIGN(4) ; + _rtc_force_fast_end = ABSOLUTE(.); + } > lp_ram_seg + + /** + * RTC data section holds RTC wake stub + * data/rodata, including from any source file + * named rtc_wake_stub*.c and the data marked with + * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes. + */ + .rtc.data : + { + _rtc_data_start = ABSOLUTE(.); + + mapping[rtc_data] + + *rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .bss .bss.*) + _rtc_data_end = ABSOLUTE(.); + } > lp_ram_seg + + /* RTC bss, from any source file named rtc_wake_stub*.c */ + .rtc.bss (NOLOAD) : + { + _rtc_bss_start = ABSOLUTE(.); + *rtc_wake_stub*.*(.bss .bss.*) + *rtc_wake_stub*.*(COMMON) + + mapping[rtc_bss] + + _rtc_bss_end = ABSOLUTE(.); + } > lp_ram_seg + + /** + * This section holds data that should not be initialized at power up + * and will be retained during deep sleep. + * User data marked with RTC_NOINIT_ATTR will be placed + * into this section. See the file "esp_attr.h" for more information. + */ + .rtc_noinit (NOLOAD): + { + . = ALIGN(4); + _rtc_noinit_start = ABSOLUTE(.); + *(.rtc_noinit .rtc_noinit.*) + . = ALIGN(4) ; + _rtc_noinit_end = ABSOLUTE(.); + } > lp_ram_seg + + /** + * This section located in RTC SLOW Memory area. + * It holds data marked with RTC_SLOW_ATTR attribute. + * See the file "esp_attr.h" for more information. + */ + .rtc.force_slow : + { + . = ALIGN(4); + _rtc_force_slow_start = ABSOLUTE(.); + *(.rtc.force_slow .rtc.force_slow.*) + . = ALIGN(4) ; + _rtc_force_slow_end = ABSOLUTE(.); + } > lp_ram_seg + + /* Get size of rtc slow data based on rtc_data_location alias */ + _rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) + ? (_rtc_force_slow_end - _rtc_data_start) + : (_rtc_force_slow_end - _rtc_force_slow_start); + + _rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) + ? (_rtc_force_fast_end - _rtc_fast_start) + : (_rtc_noinit_end - _rtc_fast_start); + + ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), + "RTC_SLOW segment data does not fit.") + + ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), + "RTC_FAST segment data does not fit.") + + .iram0.text : + { + _iram_start = ABSOLUTE(.); + /* Vectors go to start of IRAM */ + ASSERT(ABSOLUTE(.) % 0x100 == 0, "vector address must be 256 byte aligned"); + KEEP(*(.exception_vectors.text)); + . = ALIGN(4); + + _invalid_pc_placeholder = ABSOLUTE(.); + + /* Code marked as running out of IRAM */ + _iram_text_start = ABSOLUTE(.); + + mapping[iram0_text] + + } > iram0_0_seg + + /* Marks the end of IRAM code segment */ + .iram0.text_end (NOLOAD) : + { + /* ESP32-C6 memprot requires 16B padding for possible CPU prefetch and 512B alignment for PMS split lines */ + . += _esp_memprot_prefetch_pad_size; + . = ALIGN(_esp_memprot_align_size); + /* iram_end_test section exists for use by memprot unit tests only */ + *(.iram_end_test) + _iram_text_end = ABSOLUTE(.); + } > iram0_0_seg + + .iram0.data : + { + . = ALIGN(16); + _iram_data_start = ABSOLUTE(.); + + mapping[iram0_data] + + _iram_data_end = ABSOLUTE(.); + } > iram0_0_seg + + .iram0.bss (NOLOAD) : + { + . = ALIGN(16); + _iram_bss_start = ABSOLUTE(.); + + mapping[iram0_bss] + + _iram_bss_end = ABSOLUTE(.); + . = ALIGN(16); + _iram_end = ABSOLUTE(.); + } > iram0_0_seg + + /** + * This section is required to skip .iram0.text area because iram0_0_seg and + * dram0_0_seg reflect the same address space on different buses. + */ + .dram0.dummy (NOLOAD): + { + . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; + } > dram0_0_seg + + .dram0.data : + { + _data_start = ABSOLUTE(.); + *(.gnu.linkonce.d.*) + *(.data1) + __global_pointer$ = . + 0x800; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + + mapping[dram0_data] + + _data_end = ABSOLUTE(.); + . = ALIGN(4); + } > dram0_0_seg + + /** + * This section holds data that should not be initialized at power up. + * The section located in Internal SRAM memory region. The macro _NOINIT + * can be used as attribute to place data into this section. + * See the "esp_attr.h" file for more information. + */ + .noinit (NOLOAD): + { + . = ALIGN(4); + _noinit_start = ABSOLUTE(.); + *(.noinit .noinit.*) + . = ALIGN(4) ; + _noinit_end = ABSOLUTE(.); + } > dram0_0_seg + + /* Shared RAM */ + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + + mapping[dram0_bss] + + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.share.mem) + *(.gnu.linkonce.b.*) + + . = ALIGN (8); + _bss_end = ABSOLUTE(.); + } > dram0_0_seg + + ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") + + .flash.text : + { + _stext = .; + _instruction_reserved_start = ABSOLUTE(.); + _text_start = ABSOLUTE(.); + + mapping[flash_text] + + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + + /** CPU will try to prefetch up to 16 bytes of + * of instructions. This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + . += _esp_flash_mmap_prefetch_pad_size; + + _text_end = ABSOLUTE(.); + _instruction_reserved_end = ABSOLUTE(.); + _etext = .; + + /** + * Similar to _iram_start, this symbol goes here so it is + * resolved by addr2line in preference to the first symbol in + * the flash.text segment. + */ + _flash_cache_start = ABSOLUTE(0); + } > default_code_seg + + /** + * This dummy section represents the .flash.text section but in default_rodata_seg. + * Thus, it must have its alignment and (at least) its size. + */ + .flash_rodata_dummy (NOLOAD): + { + _flash_rodata_dummy_start = .; + /* Start at the same alignment constraint than .flash.text */ + . = ALIGN(ALIGNOF(.flash.text)); + /* Create an empty gap as big as .flash.text section */ + . = . + SIZEOF(.flash.text); + /* Prepare the alignment of the section above. Few bytes (0x20) must be + * added for the mapping header. */ + . = ALIGN(0x10000) + 0x20; + _rodata_reserved_start = .; + } > default_rodata_seg + + .flash.appdesc : ALIGN(0x10) + { + _rodata_start = ABSOLUTE(.); + + *(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */ + *(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */ + + /* Create an empty gap within this section. Thanks to this, the end of this + * section will match .flash.rodata's begin address. Thus, both sections + * will be merged when creating the final bin image. */ + . = ALIGN(ALIGNOF(.flash.rodata)); + } >default_rodata_seg + + .flash.rodata : ALIGN(0x10) + { + _flash_rodata_start = ABSOLUTE(.); + + mapping[flash_rodata] + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 7) & ~ 3; + /* + * C++ constructor and destructor tables + * Don't include anything from crtbegin.o or crtend.o, as IDF doesn't use toolchain crt. + * + * RISC-V gcc is configured with --enable-initfini-array so it emits an .init_array section instead. + * But the init_priority sections will be sorted for iteration in ascending order during startup. + * The rest of the init_array sections is sorted for iteration in descending order during startup, however. + * Hence a different section is generated for the init_priority functions which is iterated in + * ascending order during startup. The corresponding code can be found in startup.c. + */ + __init_priority_array_start = ABSOLUTE(.); + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*)) + __init_priority_array_end = ABSOLUTE(.); + __init_array_start = ABSOLUTE(.); + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array)) + __init_array_end = ABSOLUTE(.); + KEEP (*crtbegin.*(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + /* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */ + soc_reserved_memory_region_start = ABSOLUTE(.); + KEEP (*(.reserved_memory_address)) + soc_reserved_memory_region_end = ABSOLUTE(.); + /* System init functions registered via ESP_SYSTEM_INIT_FN */ + _esp_system_init_fn_array_start = ABSOLUTE(.); + KEEP (*(SORT_BY_INIT_PRIORITY(.esp_system_init_fn.*))) + _esp_system_init_fn_array_end = ABSOLUTE(.); + _rodata_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + _thread_local_start = ABSOLUTE(.); + *(.tdata) + *(.tdata.*) + *(.tbss) + *(.tbss.*) + _thread_local_end = ABSOLUTE(.); + _rodata_reserved_end = ABSOLUTE(.); + . = ALIGN(ALIGNOF(.eh_frame)); + } > default_rodata_seg + + /* Keep this section shall be at least aligned on 4 */ + .eh_frame : ALIGN(8) + { + __eh_frame = ABSOLUTE(.); + KEEP (*(.eh_frame)) + __eh_frame_end = ABSOLUTE(.); + /* Guarantee that this section and the next one will be merged by making + * them adjacent. */ + . = ALIGN(ALIGNOF(.eh_frame_hdr)); + } > default_rodata_seg + + /* To avoid any exception in C++ exception frame unwinding code, this section + * shall be aligned on 8. */ + .eh_frame_hdr : ALIGN(8) + { + __eh_frame_hdr = ABSOLUTE(.); + KEEP (*(.eh_frame_hdr)) + __eh_frame_hdr_end = ABSOLUTE(.); + } > default_rodata_seg + + .flash.rodata_noload (NOLOAD) : + { + . = ALIGN (4); + mapping[rodata_noload] + } > default_rodata_seg + + /* Marks the end of data, bss and possibly rodata */ + .dram0.heap_start (NOLOAD) : + { + . = ALIGN (16); + _heap_start = ABSOLUTE(.); + } > dram0_0_seg +} + +ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), + "IRAM0 segment data does not fit.") + +ASSERT(((_heap_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), + "DRAM segment data does not fit.") diff --git a/components/esp_system/ld/esp32s2/memory.ld.in b/components/esp_system/ld/esp32s2/memory.ld.in index a6fb834eb1..68c3a70e0b 100644 --- a/components/esp_system/ld/esp32s2/memory.ld.in +++ b/components/esp_system/ld/esp32s2/memory.ld.in @@ -114,8 +114,8 @@ MEMORY rtc_data_seg(RW) : org = 0x3ff9e000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC /* external memory, covers the dport, dram0, dram1 cacheable address space */ - extern_ram_seg(RWX) : org = 0x3F500000, - len = 0xA80000 + extern_ram_seg(RWX) : org = 0x3F800000, + len = 0x780000 } #if defined(CONFIG_ESP32S2_USE_FIXED_STATIC_RAM_SIZE) diff --git a/components/esp_system/ld/esp32s2/sections.ld.in b/components/esp_system/ld/esp32s2/sections.ld.in index 16b9104edd..44f2b8da5e 100644 --- a/components/esp_system/ld/esp32s2/sections.ld.in +++ b/components/esp_system/ld/esp32s2/sections.ld.in @@ -264,7 +264,7 @@ SECTIONS .flash.appdesc : ALIGN(0x10) { - _rodata_reserved_start = ABSOLUTE(.); + _rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */ _rodata_start = ABSOLUTE(.); *(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */ @@ -336,7 +336,7 @@ SECTIONS *(.tbss) *(.tbss.*) _thread_local_end = ABSOLUTE(.); - _rodata_reserved_end = ABSOLUTE(.); + _rodata_reserved_end = ABSOLUTE(.); /* This is a symbol marking the flash.rodata end, this can be used for mmu driver to maintain virtual address */ . = ALIGN(4); } >default_rodata_seg @@ -351,7 +351,7 @@ SECTIONS .flash.text : { _stext = .; - _instruction_reserved_start = ABSOLUTE(.); + _instruction_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */ _text_start = ABSOLUTE(.); mapping[flash_text] @@ -370,7 +370,7 @@ SECTIONS . += _esp_flash_mmap_prefetch_pad_size; _text_end = ABSOLUTE(.); - _instruction_reserved_end = ABSOLUTE(.); + _instruction_reserved_end = ABSOLUTE(.); /* This is a symbol marking the flash.text end, this can be used for mmu driver to maintain virtual address */ _etext = .; /* Similar to _iram_start, this symbol goes here so it is diff --git a/components/esp_system/ld/esp32s3/sections.ld.in b/components/esp_system/ld/esp32s3/sections.ld.in index 13741b45ef..ab48772187 100644 --- a/components/esp_system/ld/esp32s3/sections.ld.in +++ b/components/esp_system/ld/esp32s3/sections.ld.in @@ -244,7 +244,7 @@ SECTIONS .flash.text : { _stext = .; - _instruction_reserved_start = ABSOLUTE(.); + _instruction_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */ _text_start = ABSOLUTE(.); mapping[flash_text] @@ -263,7 +263,7 @@ SECTIONS . += _esp_flash_mmap_prefetch_pad_size; _text_end = ABSOLUTE(.); - _instruction_reserved_end = ABSOLUTE(.); + _instruction_reserved_end = ABSOLUTE(.); /* This is a symbol marking the flash.text end, this can be used for mmu driver to maintain virtual address */ _etext = .; /** @@ -288,7 +288,7 @@ SECTIONS /* Prepare the alignment of the section above. Few bytes (0x20) must be * added for the mapping header. */ . = ALIGN(0x10000) + 0x20; - _rodata_reserved_start = .; + _rodata_reserved_start = .; /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */ } > default_rodata_seg .flash.appdesc : ALIGN(0x10) @@ -361,7 +361,7 @@ SECTIONS *(.tbss) *(.tbss.*) _thread_local_end = ABSOLUTE(.); - _rodata_reserved_end = ABSOLUTE(.); + _rodata_reserved_end = ABSOLUTE(.); /* This is a symbol marking the flash.rodata end, this can be used for mmu driver to maintain virtual address */ . = ALIGN(4); } > default_rodata_seg diff --git a/components/esp_system/panic.c b/components/esp_system/panic.c index 3903796a79..57c07fc9e1 100644 --- a/components/esp_system/panic.c +++ b/components/esp_system/panic.c @@ -17,6 +17,7 @@ #include "hal/timer_hal.h" #include "hal/wdt_types.h" #include "hal/wdt_hal.h" +#include "esp_private/esp_int_wdt.h" #include "esp_private/panic_internal.h" #include "port/panic_funcs.h" @@ -24,9 +25,9 @@ #include "sdkconfig.h" -#if __has_include("esp_ota_ops.h") -#include "esp_ota_ops.h" -#define HAS_ESP_OTA 1 +#if __has_include("esp_app_desc.h") +#define WITH_ELF_SHA256 +#include "esp_app_desc.h" #endif #if CONFIG_ESP_COREDUMP_ENABLE @@ -61,7 +62,11 @@ bool g_panic_abort = false; static char *s_panic_abort_details = NULL; +#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5653 +static wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &LP_WDT}; +#else static wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; +#endif #if !CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT @@ -312,13 +317,13 @@ void esp_panic_handler(panic_info_t *info) PANIC_INFO_DUMP(info, state); panic_print_str("\r\n"); -#if HAS_ESP_OTA +#ifdef WITH_ELF_SHA256 panic_print_str("\r\nELF file SHA256: "); char sha256_buf[65]; - esp_ota_get_app_elf_sha256(sha256_buf, sizeof(sha256_buf)); + esp_app_get_elf_sha256(sha256_buf, sizeof(sha256_buf)); panic_print_str(sha256_buf); panic_print_str("\r\n"); -#endif //HAS_ESP_OTA +#endif panic_print_str("\r\n"); diff --git a/components/esp_system/port/arch/riscv/panic_arch.c b/components/esp_system/port/arch/riscv/panic_arch.c index 3afa68ae6e..cf9b7c363b 100644 --- a/components/esp_system/port/arch/riscv/panic_arch.c +++ b/components/esp_system/port/arch/riscv/panic_arch.c @@ -13,6 +13,7 @@ #include "esp_private/panic_reason.h" #include "riscv/rvruntime-frames.h" #include "esp_private/cache_err_int.h" +#include "soc/timer_periph.h" #if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE #if CONFIG_IDF_TARGET_ESP32C2 @@ -76,6 +77,7 @@ static inline bool test_and_print_register_bits(const uint32_t status, */ static inline void print_cache_err_details(const void *frame) { +#if !CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5657 /* Define the array that contains the status (bits) to test on the register * EXTMEM_CORE0_ACS_CACHE_INT_ST_REG. each bit is accompanied by a small * message. @@ -148,6 +150,7 @@ static inline void print_cache_err_details(const void *frame) panic_print_str("\r\n"); } } +#endif } @@ -287,7 +290,7 @@ void panic_soc_fill_info(void *f, panic_info_t *info) info->reason = pseudo_reason[PANIC_RSN_CACHEERR]; info->details = print_cache_err_details; - } else if (frame->mcause == ETS_T1_WDT_INUM) { + } else if (frame->mcause == ETS_INT_WDT_INUM) { /* Watchdog interrupt occured, get the core on which it happened * and update the reason/message accordingly. */ diff --git a/components/esp_system/port/brownout.c b/components/esp_system/port/brownout.c index c700f79d7d..3d146ce00d 100644 --- a/components/esp_system/port/brownout.c +++ b/components/esp_system/port/brownout.c @@ -76,7 +76,11 @@ void esp_brownout_init(void) brownout_hal_config(&cfg); brownout_hal_intr_clear(); +#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645 + rtc_isr_register(rtc_brownout_isr_handler, NULL, LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA_M, RTC_INTR_FLAG_IRAM); +#else rtc_isr_register(rtc_brownout_isr_handler, NULL, RTC_CNTL_BROWN_OUT_INT_ENA_M, RTC_INTR_FLAG_IRAM); +#endif brownout_hal_intr_enable(true); #else // brownout without interrupt diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index abd5dc8f59..ebc7d03cd7 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -47,6 +47,10 @@ #include "esp32c3/rom/cache.h" #include "esp32c3/rom/secure_boot.h" #include "esp_memprot.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rtc.h" +#include "esp32c6/rom/cache.h" +#include "esp_memprot.h" #elif CONFIG_IDF_TARGET_ESP32H2 #include "esp32h2/rtc.h" #include "esp32h2/rom/cache.h" @@ -287,7 +291,11 @@ void IRAM_ATTR call_start_cpu0(void) || rst_reas[1] == RESET_REASON_CORE_RTC_WDT || rst_reas[1] == RESET_REASON_CORE_MWDT0 #endif ) { +#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5653 + wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &LP_WDT}; +#else wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; +#endif wdt_hal_write_protect_disable(&rtc_wdt_ctx); wdt_hal_disable(&rtc_wdt_ctx); wdt_hal_write_protect_enable(&rtc_wdt_ctx); @@ -341,7 +349,7 @@ void IRAM_ATTR call_start_cpu0(void) esp_restart(); } -#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 +#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 /* Configure the Cache MMU size for instruction and rodata in flash. */ extern uint32_t Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); extern int _rodata_reserved_start; @@ -354,7 +362,7 @@ void IRAM_ATTR call_start_cpu0(void) #endif Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size); -#endif // CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 +#endif // CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 #if CONFIG_ESPTOOLPY_OCT_FLASH bool efuse_opflash_en = efuse_ll_get_flash_type(); @@ -473,7 +481,7 @@ void IRAM_ATTR call_start_cpu0(void) #endif #if CONFIG_IDF_TARGET_ESP32C2 -// TODO : IDF-4194 +// TODO : IDF-5020 #if CONFIG_ESP32C2_INSTRUCTION_CACHE_WRAP extern void esp_enable_cache_wrap(uint32_t icache_wrap_enable); esp_enable_cache_wrap(1); diff --git a/components/esp_system/port/soc/esp32/clk.c b/components/esp_system/port/soc/esp32/clk.c index 9396b9379c..fef50f109a 100644 --- a/components/esp_system/port/soc/esp32/clk.c +++ b/components/esp_system/port/soc/esp32/clk.c @@ -36,11 +36,6 @@ static const char* TAG = "clk"; #define RTC_XTAL_CAL_RETRY 1 #endif -/* Lower threshold for a reasonably-looking calibration value for a 32k XTAL. - * The ideal value (assuming 32768 Hz frequency) is 1000000/32768*(2**19) = 16*10^6. - */ -#define MIN_32K_XTAL_CAL_VAL 15000000L - /* Indicates that this 32k oscillator gets input from external oscillator, rather * than a crystal. */ @@ -84,7 +79,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup. if (SLOW_CLK_CAL_CYCLES > 0) { cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES); - if (cal_val == 0 || cal_val < MIN_32K_XTAL_CAL_VAL) { + if (cal_val == 0) { if (retry_32k_xtal-- > 0) { continue; } diff --git a/components/esp_system/port/soc/esp32c2/clk.c b/components/esp_system/port/soc/esp32c2/clk.c index 814e3b96a1..ebc800e576 100644 --- a/components/esp_system/port/soc/esp32c2/clk.c +++ b/components/esp_system/port/soc/esp32c2/clk.c @@ -35,11 +35,6 @@ #define MHZ (1000000) -/* Lower threshold for a reasonably-looking calibration value for a 32k XTAL. - * The ideal value (assuming 32768 Hz frequency) is 1000000/32768*(2**19) = 16*10^6. - */ -#define MIN_32K_XTAL_CAL_VAL 15000000L - /* Indicates that this 32k oscillator gets input from external oscillator, rather * than a crystal. */ @@ -154,8 +149,8 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup. if (SLOW_CLK_CAL_CYCLES > 0) { - cal_val = rtc_clk_cal(RTC_CAL_EXT_CLK, SLOW_CLK_CAL_CYCLES); - if (cal_val == 0 || cal_val < MIN_32K_XTAL_CAL_VAL) { + cal_val = rtc_clk_cal(RTC_CAL_EXT_32K, SLOW_CLK_CAL_CYCLES); + if (cal_val == 0) { if (retry_ext_clk-- > 0) { continue; } diff --git a/components/esp_system/port/soc/esp32c2/system_internal.c b/components/esp_system/port/soc/esp32c2/system_internal.c index 551b4a672f..f14e225df4 100644 --- a/components/esp_system/port/soc/esp32c2/system_internal.c +++ b/components/esp_system/port/soc/esp32c2/system_internal.c @@ -11,8 +11,7 @@ #include "esp_attr.h" #include "esp_efuse.h" #include "esp_log.h" -#include "riscv/riscv_interrupts.h" -#include "riscv/interrupt.h" +#include "riscv/rv_utils.h" #include "esp_rom_uart.h" #include "soc/gpio_reg.h" #include "soc/rtc_cntl_reg.h" @@ -35,7 +34,7 @@ void IRAM_ATTR esp_restart_noos(void) { // Disable interrupts - riscv_global_interrupts_disable(); + rv_utils_intr_global_disable(); // Enable RTC watchdog for 1 second wdt_hal_context_t rtc_wdt_ctx; wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false); diff --git a/components/esp_system/port/soc/esp32c3/clk.c b/components/esp_system/port/soc/esp32c3/clk.c index bf92e30f19..3f044443c1 100644 --- a/components/esp_system/port/soc/esp32c3/clk.c +++ b/components/esp_system/port/soc/esp32c3/clk.c @@ -36,11 +36,6 @@ #define MHZ (1000000) -/* Lower threshold for a reasonably-looking calibration value for a 32k XTAL. - * The ideal value (assuming 32768 Hz frequency) is 1000000/32768*(2**19) = 16*10^6. - */ -#define MIN_32K_XTAL_CAL_VAL 15000000L - /* Indicates that this 32k oscillator gets input from external oscillator, rather * than a crystal. */ @@ -165,7 +160,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup. if (SLOW_CLK_CAL_CYCLES > 0) { cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES); - if (cal_val == 0 || cal_val < MIN_32K_XTAL_CAL_VAL) { + if (cal_val == 0) { if (retry_32k_xtal-- > 0) { continue; } diff --git a/components/esp_system/port/soc/esp32c3/system_internal.c b/components/esp_system/port/soc/esp32c3/system_internal.c index 950538da0f..f5ca5ddda0 100644 --- a/components/esp_system/port/soc/esp32c3/system_internal.c +++ b/components/esp_system/port/soc/esp32c3/system_internal.c @@ -11,8 +11,7 @@ #include "esp_attr.h" #include "esp_efuse.h" #include "esp_log.h" -#include "riscv/riscv_interrupts.h" -#include "riscv/interrupt.h" +#include "riscv/rv_utils.h" #include "esp_rom_uart.h" #include "soc/gpio_reg.h" #include "soc/rtc_cntl_reg.h" @@ -36,7 +35,7 @@ void IRAM_ATTR esp_restart_noos(void) { // Disable interrupts - riscv_global_interrupts_disable(); + rv_utils_intr_global_disable(); // Enable RTC watchdog for 1 second wdt_hal_context_t rtc_wdt_ctx; wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false); diff --git a/components/esp_system/port/soc/esp32c6/CMakeLists.txt b/components/esp_system/port/soc/esp32c6/CMakeLists.txt new file mode 100644 index 0000000000..d77109f3b5 --- /dev/null +++ b/components/esp_system/port/soc/esp32c6/CMakeLists.txt @@ -0,0 +1,12 @@ +set(srcs "clk.c" + "reset_reason.c" + "system_internal.c" + "cache_err_int.c" + "../../arch/riscv/expression_with_stack.c" + "../../arch/riscv/expression_with_stack_asm.S" + "../../arch/riscv/panic_arch.c" + "../../arch/riscv/debug_stubs.c") + +add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" ${srcs}) + +target_sources(${COMPONENT_LIB} PRIVATE ${srcs}) diff --git a/components/esp_system/port/soc/esp32c6/Kconfig.cpu b/components/esp_system/port/soc/esp32c6/Kconfig.cpu new file mode 100644 index 0000000000..414e4377f3 --- /dev/null +++ b/components/esp_system/port/soc/esp32c6/Kconfig.cpu @@ -0,0 +1,21 @@ +choice ESP_DEFAULT_CPU_FREQ_MHZ + prompt "CPU frequency" + default ESP_DEFAULT_CPU_FREQ_MHZ_40 if IDF_ENV_FPGA + default ESP_DEFAULT_CPU_FREQ_MHZ_160 + help + CPU frequency to be set on application startup. + + config ESP_DEFAULT_CPU_FREQ_MHZ_40 + bool "40 MHz" + depends on IDF_ENV_FPGA + config ESP_DEFAULT_CPU_FREQ_MHZ_80 + bool "80 MHz" + config ESP_DEFAULT_CPU_FREQ_MHZ_160 + bool "160 MHz" +endchoice + +config ESP_DEFAULT_CPU_FREQ_MHZ + int + default 40 if ESP_DEFAULT_CPU_FREQ_MHZ_40 + default 80 if ESP_DEFAULT_CPU_FREQ_MHZ_80 + default 160 if ESP_DEFAULT_CPU_FREQ_MHZ_160 diff --git a/components/esp_system/port/soc/esp32c6/Kconfig.system b/components/esp_system/port/soc/esp32c6/Kconfig.system new file mode 100644 index 0000000000..1427bb2521 --- /dev/null +++ b/components/esp_system/port/soc/esp32c6/Kconfig.system @@ -0,0 +1,45 @@ +menu "Brownout Detector" + config ESP_BROWNOUT_DET + bool "Hardware brownout detect & reset" + depends on !IDF_ENV_FPGA + default y + help + The ESP32-C6 has a built-in brownout detector which can detect if the voltage is lower than + a specific value. If this happens, it will reset the chip in order to prevent unintended + behaviour. + + choice ESP_BROWNOUT_DET_LVL_SEL + prompt "Brownout voltage level" + depends on ESP_BROWNOUT_DET + default ESP_BROWNOUT_DET_LVL_SEL_7 + help + The brownout detector will reset the chip when the supply voltage is approximately + below this level. Note that there may be some variation of brownout voltage level + between each chip. + + #The voltage levels here are estimates, more work needs to be done to figure out the exact voltages + #of the brownout threshold levels. + config ESP_BROWNOUT_DET_LVL_SEL_7 + bool "2.51V" + config ESP_BROWNOUT_DET_LVL_SEL_6 + bool "2.64V" + config ESP_BROWNOUT_DET_LVL_SEL_5 + bool "2.76V" + config ESP_BROWNOUT_DET_LVL_SEL_4 + bool "2.92V" + config ESP_BROWNOUT_DET_LVL_SEL_3 + bool "3.10V" + config ESP_BROWNOUT_DET_LVL_SEL_2 + bool "3.27V" + endchoice + + config ESP_BROWNOUT_DET_LVL + int + default 2 if ESP_BROWNOUT_DET_LVL_SEL_2 + default 3 if ESP_BROWNOUT_DET_LVL_SEL_3 + default 4 if ESP_BROWNOUT_DET_LVL_SEL_4 + default 5 if ESP_BROWNOUT_DET_LVL_SEL_5 + default 6 if ESP_BROWNOUT_DET_LVL_SEL_6 + default 7 if ESP_BROWNOUT_DET_LVL_SEL_7 + +endmenu diff --git a/components/esp_system/port/soc/esp32c6/cache_err_int.c b/components/esp_system/port/soc/esp32c6/cache_err_int.c new file mode 100644 index 0000000000..44ac5fb759 --- /dev/null +++ b/components/esp_system/port/soc/esp32c6/cache_err_int.c @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + The cache has an interrupt that can be raised as soon as an access to a cached + region (flash) is done without the cache being enabled. We use that here + to panic the CPU, which from a debugging perspective is better than grabbing bad + data from the bus. +*/ +#include "esp_rom_sys.h" +#include "esp_attr.h" +#include "esp_log.h" +#include "esp_intr_alloc.h" +#include "soc/periph_defs.h" +#include "riscv/interrupt.h" +#include "hal/cache_ll.h" + +static const char *TAG = "CACHE_ERR"; + +void esp_cache_err_int_init(void) +{ + ESP_EARLY_LOGW(TAG, "esp_cache_err_int_init() has not been implemented yet"); +#if 0 // TODO: IDF-5656 + const uint32_t core_id = 0; + + /* Disable cache interrupts if enabled. */ + ESP_INTR_DISABLE(ETS_CACHEERR_INUM); + + /** + * Bind all cache errors to ETS_CACHEERR_INUM interrupt. we will deal with + * them in handler by different types + * I) Cache access error + * 1. dbus trying to write to icache + * 2. dbus authentication fail + * 3. cpu access icache while dbus is disabled [1] + * 4. ibus authentication fail + * 5. ibus trying to write icache + * 6. cpu access icache while ibus is disabled + * II) Cache illegal error + * 1. dbus counter overflow + * 2. ibus counter overflow + * 3. mmu entry fault + * 4. icache preload configurations fault + * 5. icache sync configuration fault + * + * [1]: On ESP32C6 boards, the caches are shared but buses are still + * distinct. So, we have an ibus and a dbus sharing the same cache. + * This error can occur if the dbus performs a request but the icache + * (or simply cache) is disabled. + */ + esp_rom_route_intr_matrix(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM); + esp_rom_route_intr_matrix(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM); + + /* Set the type and priority to cache error interrupts. */ + esprv_intc_int_set_type(BIT(ETS_CACHEERR_INUM), INTR_TYPE_LEVEL); + esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); + + ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK); + /* On the hardware side, start by clearing all the bits reponsible for cache access error */ + cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); + /* Then enable cache access error interrupts. */ + cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); + + /* Same goes for cache illegal error: start by clearing the bits and then + * set them back. */ + ESP_DRAM_LOGV(TAG, "illegal error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ILG_EVENT_MASK); + cache_ll_l1_clear_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); + cache_ll_l1_enable_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); + + /* Enable the interrupts for cache error. */ + ESP_INTR_ENABLE(ETS_CACHEERR_INUM); +#endif +} + +int IRAM_ATTR esp_cache_err_get_cpuid(void) +{ + return 0; +} diff --git a/components/esp_system/port/soc/esp32c6/clk.c b/components/esp_system/port/soc/esp32c6/clk.c new file mode 100644 index 0000000000..f27a26561f --- /dev/null +++ b/components/esp_system/port/soc/esp32c6/clk.c @@ -0,0 +1,305 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include "sdkconfig.h" +#include "esp_attr.h" +#include "esp_log.h" +#include "esp_clk_internal.h" +#include "esp32c6/rom/ets_sys.h" +#include "esp32c6/rom/uart.h" +// #include "soc/system_reg.h" +#include "soc/soc.h" +#include "soc/rtc.h" +#include "soc/rtc_periph.h" +#include "soc/i2s_reg.h" +#include "esp_cpu.h" +#include "hal/wdt_hal.h" +#include "esp_private/periph_ctrl.h" +#include "esp_private/esp_clk.h" +#include "bootloader_clock.h" +// #include "soc/syscon_reg.h" +#include "esp_rom_uart.h" +#include "esp_rom_sys.h" + +/* Number of cycles to wait from the 32k XTAL oscillator to consider it running. + * Larger values increase startup delay. Smaller values may cause false positive + * detection (i.e. oscillator runs for a few cycles and then stops). + */ +#define SLOW_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES + +#define MHZ (1000000) + +/* Lower threshold for a reasonably-looking calibration value for a 32k XTAL. + * The ideal value (assuming 32768 Hz frequency) is 1000000/32768*(2**19) = 16*10^6. + */ +#define MIN_32K_XTAL_CAL_VAL 15000000L + +/* Indicates that this 32k oscillator gets input from external oscillator, rather + * than a crystal. + */ +#define EXT_OSC_FLAG BIT(3) + +/* This is almost the same as soc_rtc_slow_clk_src_t, except that we define + * an extra enum member for the external 32k oscillator. + * For convenience, lower 2 bits should correspond to soc_rtc_slow_clk_src_t values. + */ +typedef enum { + SLOW_CLK_RTC = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150 kHz RC oscillator + SLOW_CLK_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32 kHz XTAL + SLOW_CLK_8MD256 = SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256, //!< Internal 8 MHz RC oscillator, divided by 256 + SLOW_CLK_32K_EXT_OSC = SOC_RTC_SLOW_CLK_SRC_XTAL32K | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin +} slow_clk_sel_t; + +static void select_rtc_slow_clk(slow_clk_sel_t slow_clk); + +static const char *TAG = "clk"; + + + __attribute__((weak)) void esp_clk_init(void) +{ +#if !CONFIG_IDF_ENV_FPGA + rtc_config_t cfg = RTC_CONFIG_DEFAULT(); + soc_reset_reason_t rst_reas; + rst_reas = esp_rom_get_reset_reason(0); + if (rst_reas == RESET_REASON_CHIP_POWER_ON) { + cfg.cali_ocode = 1; + } + rtc_init(cfg); + + assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M); + + bool rc_fast_d256_is_enabled = rtc_clk_8md256_enabled(); + rtc_clk_8m_enable(true, rc_fast_d256_is_enabled); + rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST); +#endif + +#ifdef CONFIG_BOOTLOADER_WDT_ENABLE + // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed. + // If the frequency changes from 150kHz to 32kHz, then the timeout set for the WDT will increase 4.6 times. + // Therefore, for the time of frequency change, set a new lower timeout value (1.6 sec). + // This prevents excessive delay before resetting in case the supply voltage is drawdown. + // (If frequency is changed from 150kHz to 32kHz then WDT timeout will increased to 1.6sec * 150/32 = 7.5 sec). + wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &LP_WDT}; // TODO: IDF-5653 + uint32_t stage_timeout_ticks = (uint32_t)(1600ULL * rtc_clk_slow_freq_get_hz() / 1000ULL); + wdt_hal_write_protect_disable(&rtc_wdt_ctx); + wdt_hal_feed(&rtc_wdt_ctx); + //Bootloader has enabled RTC WDT until now. We're only modifying timeout, so keep the stage and timeout action the same + wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC); + wdt_hal_write_protect_enable(&rtc_wdt_ctx); +#endif + +#if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS) + select_rtc_slow_clk(SLOW_CLK_32K_XTAL); +#elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC) + select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC); +#elif defined(CONFIG_RTC_CLK_SRC_INT_8MD256) + select_rtc_slow_clk(SLOW_CLK_8MD256); +#else + select_rtc_slow_clk(SLOW_CLK_RTC); +#endif + +#ifdef CONFIG_BOOTLOADER_WDT_ENABLE + // After changing a frequency WDT timeout needs to be set for new frequency. + stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000); + wdt_hal_write_protect_disable(&rtc_wdt_ctx); + wdt_hal_feed(&rtc_wdt_ctx); + wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC); + wdt_hal_write_protect_enable(&rtc_wdt_ctx); +#endif + + rtc_cpu_freq_config_t old_config, new_config; + rtc_clk_cpu_freq_get_config(&old_config); + const uint32_t old_freq_mhz = old_config.freq_mhz; + const uint32_t new_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ; + + bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config); + assert(res); + + // Wait for UART TX to finish, otherwise some UART output will be lost + // when switching APB frequency + esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM); + + if (res) { + rtc_clk_cpu_freq_set_config(&new_config); + } + + // Re calculate the ccount to make time calculation correct. + esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz ); +} + +static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) +{ + ESP_EARLY_LOGW(TAG, "select_rtc_slow_clk() has not been implemented yet"); +#if 0 // TODO: IDF-5645 + soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V; + uint32_t cal_val = 0; + /* number of times to repeat 32k XTAL calibration + * before giving up and switching to the internal RC + */ + int retry_32k_xtal = 3; + + do { + if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { + /* 32k XTAL oscillator needs to be enabled and running before it can + * be used. Hardware doesn't have a direct way of checking if the + * oscillator is running. Here we use rtc_clk_cal function to count + * the number of main XTAL cycles in the given number of 32k XTAL + * oscillator cycles. If the 32k XTAL has not started up, calibration + * will time out, returning 0. + */ + ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up"); + if (slow_clk == SLOW_CLK_32K_XTAL) { + rtc_clk_32k_enable(true); + } else if (slow_clk == SLOW_CLK_32K_EXT_OSC) { + rtc_clk_32k_enable_external(); + } + // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup. + if (SLOW_CLK_CAL_CYCLES > 0) { + cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES); + if (cal_val == 0 || cal_val < MIN_32K_XTAL_CAL_VAL) { + if (retry_32k_xtal-- > 0) { + continue; + } + ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 150 kHz oscillator"); + rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW; + } + } + } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { + rtc_clk_8m_enable(true, true); + } + rtc_clk_slow_src_set(rtc_slow_clk_src); + + if (SLOW_CLK_CAL_CYCLES > 0) { + /* TODO: 32k XTAL oscillator has some frequency drift at startup. + * Improve calibration routine to wait until the frequency is stable. + */ + cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES); + } else { + const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; + cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz()); + } + } while (cal_val == 0); + ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val); + esp_clk_slowclk_cal_set(cal_val); +#endif +} + +void rtc_clk_select_rtc_slow_clk(void) +{ + select_rtc_slow_clk(SLOW_CLK_32K_XTAL); +} + +/* This function is not exposed as an API at this point. + * All peripheral clocks are default enabled after chip is powered on. + * This function disables some peripheral clocks when cpu starts. + * These peripheral clocks are enabled when the peripherals are initialized + * and disabled when they are de-initialized. + */ +__attribute__((weak)) void esp_perip_clk_init(void) +{ + ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet"); +#if 0 // TODO: IDF-5658 + uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0; + uint32_t common_perip_clk1 = 0; + + soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); + + /* For reason that only reset CPU, do not disable the clocks + * that have been enabled before reset. + */ + if (rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW || + rst_reason == RESET_REASON_CPU0_RTC_WDT || rst_reason == RESET_REASON_CPU0_MWDT1) { + common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG); + hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG); + wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG); + } else { + common_perip_clk = SYSTEM_WDG_CLK_EN | + SYSTEM_I2S0_CLK_EN | +#if CONFIG_ESP_CONSOLE_UART_NUM != 0 + SYSTEM_UART_CLK_EN | +#endif +#if CONFIG_ESP_CONSOLE_UART_NUM != 1 + SYSTEM_UART1_CLK_EN | +#endif + SYSTEM_SPI2_CLK_EN | + SYSTEM_I2C_EXT0_CLK_EN | + SYSTEM_UHCI0_CLK_EN | + SYSTEM_RMT_CLK_EN | + SYSTEM_LEDC_CLK_EN | + SYSTEM_TIMERGROUP1_CLK_EN | + SYSTEM_SPI3_CLK_EN | + SYSTEM_SPI4_CLK_EN | + SYSTEM_TWAI_CLK_EN | + SYSTEM_I2S1_CLK_EN | + SYSTEM_SPI2_DMA_CLK_EN | + SYSTEM_SPI3_DMA_CLK_EN; + + common_perip_clk1 = 0; + hwcrypto_perip_clk = SYSTEM_CRYPTO_AES_CLK_EN | + SYSTEM_CRYPTO_SHA_CLK_EN | + SYSTEM_CRYPTO_RSA_CLK_EN; + wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN | + SYSTEM_WIFI_CLK_BT_EN_M | + SYSTEM_WIFI_CLK_UNUSED_BIT5 | + SYSTEM_WIFI_CLK_UNUSED_BIT12; + } + + //Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state. + common_perip_clk |= SYSTEM_I2S0_CLK_EN | +#if CONFIG_ESP_CONSOLE_UART_NUM != 0 + SYSTEM_UART_CLK_EN | +#endif +#if CONFIG_ESP_CONSOLE_UART_NUM != 1 + SYSTEM_UART1_CLK_EN | +#endif + SYSTEM_SPI2_CLK_EN | + SYSTEM_I2C_EXT0_CLK_EN | + SYSTEM_UHCI0_CLK_EN | + SYSTEM_RMT_CLK_EN | + SYSTEM_UHCI1_CLK_EN | + SYSTEM_SPI3_CLK_EN | + SYSTEM_SPI4_CLK_EN | + SYSTEM_I2C_EXT1_CLK_EN | + SYSTEM_I2S1_CLK_EN | + SYSTEM_SPI2_DMA_CLK_EN | + SYSTEM_SPI3_DMA_CLK_EN; + common_perip_clk1 = 0; + + /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock, + * the current is not reduced when disable I2S clock. + */ + // TOCK(check replacement) + // REG_SET_FIELD(I2S_CLKM_CONF_REG(0), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL); + // REG_SET_FIELD(I2S_CLKM_CONF_REG(1), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL); + + /* Disable some peripheral clocks. */ + CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk); + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk); + + CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, common_perip_clk1); + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, common_perip_clk1); + + /* Disable hardware crypto clocks. */ + CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk); + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, hwcrypto_perip_clk); + + /* Disable WiFi/BT/SDIO clocks. */ + CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, wifi_bt_sdio_clk); + SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN); + + /* Set WiFi light sleep clock source to RTC slow clock */ + REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0); + CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M); + SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW); + + /* Enable RNG clock. */ + periph_module_enable(PERIPH_RNG_MODULE); +#endif +} diff --git a/components/esp_system/port/soc/esp32c6/reset_reason.c b/components/esp_system/port/soc/esp32c6/reset_reason.c new file mode 100644 index 0000000000..bd82c8a3d3 --- /dev/null +++ b/components/esp_system/port/soc/esp32c6/reset_reason.c @@ -0,0 +1,110 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_system.h" +#include "esp_rom_sys.h" +#include "esp_private/system_internal.h" +#include "soc/rtc_periph.h" +#include "esp32c6/rom/rtc.h" + +static void esp_reset_reason_clear_hint(void); + +static esp_reset_reason_t s_reset_reason; + +static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason, esp_reset_reason_t reset_reason_hint) +{ + switch (rtc_reset_reason) { + case RESET_REASON_CHIP_POWER_ON: + return ESP_RST_POWERON; + + case RESET_REASON_CPU0_SW: + case RESET_REASON_CORE_SW: + if (reset_reason_hint == ESP_RST_PANIC || + reset_reason_hint == ESP_RST_BROWNOUT || + reset_reason_hint == ESP_RST_TASK_WDT || + reset_reason_hint == ESP_RST_INT_WDT) { + return reset_reason_hint; + } + return ESP_RST_SW; + + case RESET_REASON_CORE_DEEP_SLEEP: + return ESP_RST_DEEPSLEEP; + + case RESET_REASON_CORE_MWDT0: + return ESP_RST_TASK_WDT; + + case RESET_REASON_CORE_MWDT1: + return ESP_RST_INT_WDT; + + case RESET_REASON_CORE_RTC_WDT: + case RESET_REASON_SYS_RTC_WDT: + case RESET_REASON_SYS_SUPER_WDT: + case RESET_REASON_CPU0_RTC_WDT: + case RESET_REASON_CPU0_MWDT0: + case RESET_REASON_CPU0_MWDT1: + return ESP_RST_WDT; + + case RESET_REASON_SYS_BROWN_OUT: + return ESP_RST_BROWNOUT; + + default: + return ESP_RST_UNKNOWN; + } +} + +static void __attribute__((constructor)) esp_reset_reason_init(void) +{ + esp_reset_reason_t hint = esp_reset_reason_get_hint(); + s_reset_reason = get_reset_reason(esp_rom_get_reset_reason(PRO_CPU_NUM), hint); + if (hint != ESP_RST_UNKNOWN) { + esp_reset_reason_clear_hint(); + } +} + +esp_reset_reason_t esp_reset_reason(void) +{ + return s_reset_reason; +} + +/* Reset reason hint is stored in RTC_RESET_CAUSE_REG, a.k.a. RTC_CNTL_STORE6_REG, + * a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the + * deep sleep wake stub entry address and for reset reason hint, since wake stub + * is only used for deep sleep reset, and in this case the reason provided by + * esp_rom_get_reset_reason is unambiguous. + * + * Same layout is used as for RTC_APB_FREQ_REG (a.k.a. RTC_CNTL_STORE5_REG): + * the value is replicated in low and high half-words. In addition to that, + * MSB is set to 1, which doesn't happen when RTC_CNTL_STORE6_REG contains + * deep sleep wake stub address. + */ + +#define RST_REASON_BIT 0x80000000 +#define RST_REASON_MASK 0x7FFF +#define RST_REASON_SHIFT 16 + +/* in IRAM, can be called from panic handler */ +void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint) +{ + assert((hint & (~RST_REASON_MASK)) == 0); + uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT; + REG_WRITE(RTC_RESET_CAUSE_REG, val); +} + +/* in IRAM, can be called from panic handler */ +esp_reset_reason_t IRAM_ATTR esp_reset_reason_get_hint(void) +{ + uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG); + uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK; + uint32_t low = reset_reason_hint & RST_REASON_MASK; + if ((reset_reason_hint & RST_REASON_BIT) == 0 || high != low) { + return ESP_RST_UNKNOWN; + } + return (esp_reset_reason_t) low; +} +static inline void esp_reset_reason_clear_hint(void) +{ + REG_WRITE(RTC_RESET_CAUSE_REG, 0); +} diff --git a/components/esp_system/port/soc/esp32c6/system_internal.c b/components/esp_system/port/soc/esp32c6/system_internal.c new file mode 100644 index 0000000000..0522220e77 --- /dev/null +++ b/components/esp_system/port/soc/esp32c6/system_internal.c @@ -0,0 +1,119 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "sdkconfig.h" +#include "esp_system.h" +#include "esp_private/system_internal.h" +#include "esp_attr.h" +#include "esp_log.h" +#include "esp_rom_sys.h" +#include "riscv/rv_utils.h" +#include "esp_rom_uart.h" +#include "soc/gpio_reg.h" +#include "esp_cpu.h" +#include "soc/rtc.h" +#include "soc/rtc_periph.h" +#include "soc/uart_reg.h" +#include "hal/wdt_hal.h" +#include "esp_private/cache_err_int.h" + +#include "esp32c6/rom/cache.h" +#include "esp32c6/rom/rtc.h" +#include "soc/pcr_reg.h" + +/* "inner" restart function for after RTOS, interrupts & anything else on this + * core are already stopped. Stalls other core, resets hardware, + * triggers restart. +*/ +void IRAM_ATTR esp_restart_noos(void) +{ + // Disable interrupts + rv_utils_intr_global_disable(); + // Enable RTC watchdog for 1 second + wdt_hal_context_t rtc_wdt_ctx; + wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false); + uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL); + wdt_hal_write_protect_disable(&rtc_wdt_ctx); + wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM); + wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC); + //Enable flash boot mode so that flash booting after restart is protected by the RTC WDT. + wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true); + wdt_hal_write_protect_enable(&rtc_wdt_ctx); + + // C6 is a single core SoC, no need to reset and stall the other CPU + + // Disable TG0/TG1 watchdogs + wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0}; + wdt_hal_write_protect_disable(&wdt0_context); + wdt_hal_disable(&wdt0_context); + wdt_hal_write_protect_enable(&wdt0_context); + + wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1}; + wdt_hal_write_protect_disable(&wdt1_context); + wdt_hal_disable(&wdt1_context); + wdt_hal_write_protect_enable(&wdt1_context); + + // Flush any data left in UART FIFOs + esp_rom_uart_tx_wait_idle(0); + esp_rom_uart_tx_wait_idle(1); + // Disable cache + Cache_Disable_ICache(); + + // 2nd stage bootloader reconfigures SPI flash signals. + // Reset them to the defaults expected by ROM. + WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); + // TODO: IDF-5659 + // WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); + // WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); + // WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); + // WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); + // WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); + + // Reset wifi/bluetooth/ethernet/sdio (bb/mac) + // Moved to module internal + // SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, + // SYSTEM_WIFIBB_RST | SYSTEM_FE_RST | // TODO: IDF-5680 (esp_phy) + // SYSTEM_WIFIMAC_RST | // TODO: IDF-5679 (esp_wifi) + // SYSTEM_SDIO_RST | // SDIO_HINF_HINF_SDIO_RST? + // SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | // TODO: IDF-5325 (ethernet) + // SYSTEM_BTBB_RST | SYSTEM_BTBB_REG_RST | // TODO: IDF-5727 (bt) + // SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST | SYSTEM_RW_BTMAC_REG_RST | SYSTEM_RW_BTLP_REG_RST); + // REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0); + + // Set Peripheral clk rst + SET_PERI_REG_MASK(PCR_TIMERGROUP0_CONF_REG, PCR_TG0_RST_EN); + SET_PERI_REG_MASK(PCR_TIMERGROUP1_CONF_REG, PCR_TG1_RST_EN); + SET_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN); + SET_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN); + SET_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN); + SET_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN); + SET_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN); + SET_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN); + SET_PERI_REG_MASK(PCR_MODEM_APB_CONF_REG, PCR_MODEM_RST_EN); + + // Clear Peripheral clk rst + CLEAR_PERI_REG_MASK(PCR_TIMERGROUP0_CONF_REG, PCR_TG0_RST_EN); + CLEAR_PERI_REG_MASK(PCR_TIMERGROUP1_CONF_REG, PCR_TG1_RST_EN); + CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN); + CLEAR_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN); + CLEAR_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN); + CLEAR_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN); + CLEAR_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN); + CLEAR_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN); + CLEAR_PERI_REG_MASK(PCR_MODEM_APB_CONF_REG, PCR_MODEM_RST_EN); + + // Set CPU back to XTAL source, no PLL, same as hard reset +#if !CONFIG_IDF_ENV_FPGA + rtc_clk_cpu_freq_set_xtal(); +#endif + + // Reset PRO CPU + esp_rom_software_reset_cpu(0); + while (true) { + ; + } +} diff --git a/components/esp_system/port/soc/esp32h2/clk.c b/components/esp_system/port/soc/esp32h2/clk.c index 60a2fdad13..de5612b7c2 100644 --- a/components/esp_system/port/soc/esp32h2/clk.c +++ b/components/esp_system/port/soc/esp32h2/clk.c @@ -36,11 +36,6 @@ #define MHZ (1000000) -/* Lower threshold for a reasonably-looking calibration value for a 32k XTAL. - * The ideal value (assuming 32768 Hz frequency) is 1000000/32768*(2**19) = 16*10^6. - */ -#define MIN_32K_XTAL_CAL_VAL 15000000L - /* Indicates that this 32k oscillator gets input from external oscillator, rather * than a crystal. */ @@ -157,7 +152,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup. if (SLOW_CLK_CAL_CYCLES > 0) { cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES); - if (cal_val == 0 || cal_val < MIN_32K_XTAL_CAL_VAL) { + if (cal_val == 0) { if (retry_32k_xtal-- > 0) { continue; } diff --git a/components/esp_system/port/soc/esp32h2/system_internal.c b/components/esp_system/port/soc/esp32h2/system_internal.c index f335416a35..a7dd7548f3 100644 --- a/components/esp_system/port/soc/esp32h2/system_internal.c +++ b/components/esp_system/port/soc/esp32h2/system_internal.c @@ -11,8 +11,7 @@ #include "esp_attr.h" #include "esp_efuse.h" #include "esp_log.h" -#include "riscv/riscv_interrupts.h" -#include "riscv/interrupt.h" +#include "riscv/rv_utils.h" #include "esp_rom_uart.h" #include "soc/gpio_reg.h" #include "soc/rtc_cntl_reg.h" @@ -35,7 +34,7 @@ void IRAM_ATTR esp_restart_noos(void) { // Disable interrupts - riscv_global_interrupts_disable(); + rv_utils_intr_global_disable(); // Enable RTC watchdog for 1 second wdt_hal_context_t rtc_wdt_ctx; wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false); diff --git a/components/esp_system/port/soc/esp32s2/clk.c b/components/esp_system/port/soc/esp32s2/clk.c index cbb6eae977..8461d16c83 100644 --- a/components/esp_system/port/soc/esp32s2/clk.c +++ b/components/esp_system/port/soc/esp32s2/clk.c @@ -42,11 +42,6 @@ static const char *TAG = "clk"; #define RTC_XTAL_CAL_RETRY 1 #endif -/* Lower threshold for a reasonably-looking calibration value for a 32k XTAL. - * The ideal value (assuming 32768 Hz frequency) is 1000000/32768*(2**19) = 16*10^6. - */ -#define MIN_32K_XTAL_CAL_VAL 15000000L - /* Indicates that this 32k oscillator gets input from external oscillator, rather * than a crystal. */ @@ -170,7 +165,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup. if (SLOW_CLK_CAL_CYCLES > 0) { cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES); - if (cal_val == 0 || cal_val < MIN_32K_XTAL_CAL_VAL) { + if (cal_val == 0) { if (retry_32k_xtal-- > 0) { continue; } diff --git a/components/esp_system/port/soc/esp32s3/clk.c b/components/esp_system/port/soc/esp32s3/clk.c index 0b102eb42f..8c3e1418e0 100644 --- a/components/esp_system/port/soc/esp32s3/clk.c +++ b/components/esp_system/port/soc/esp32s3/clk.c @@ -36,11 +36,6 @@ static const char *TAG = "clk"; #define RTC_XTAL_CAL_RETRY 1 -/* Lower threshold for a reasonably-looking calibration value for a 32k XTAL. - * The ideal value (assuming 32768 Hz frequency) is 1000000/32768*(2**19) = 16*10^6. - */ -#define MIN_32K_XTAL_CAL_VAL 15000000L - /* Indicates that this 32k oscillator gets input from external oscillator, rather * than a crystal. */ @@ -159,7 +154,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup. if (SLOW_CLK_CAL_CYCLES > 0) { cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES); - if (cal_val == 0 || cal_val < MIN_32K_XTAL_CAL_VAL) { + if (cal_val == 0) { if (retry_32k_xtal-- > 0) { continue; } diff --git a/components/esp_system/sdkconfig.rename b/components/esp_system/sdkconfig.rename index 5a9dc895b7..826f9cb0a3 100644 --- a/components/esp_system/sdkconfig.rename +++ b/components/esp_system/sdkconfig.rename @@ -26,6 +26,7 @@ CONFIG_TASK_WDT_PANIC CONFIG_ESP_TASK_WDT_PANI CONFIG_TASK_WDT_TIMEOUT_S CONFIG_ESP_TASK_WDT_TIMEOUT_S CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1 +CONFIG_ESP_TASK_WDT CONFIG_ESP_TASK_WDT_INIT CONFIG_ESP32_DEBUG_STUBS_ENABLE CONFIG_ESP_DEBUG_STUBS_ENABLE CONFIG_BROWNOUT_DET CONFIG_ESP_BROWNOUT_DET diff --git a/components/esp_system/startup.c b/components/esp_system/startup.c index 6adda6dbd3..8d1efa93fe 100644 --- a/components/esp_system/startup.c +++ b/components/esp_system/startup.c @@ -20,8 +20,6 @@ #include "hal/uart_types.h" #include "hal/uart_ll.h" -#include "esp_system.h" -#include "esp_log.h" #include "esp_heap_caps_init.h" #include "spi_flash_mmap.h" #include "esp_flash_internal.h" @@ -33,10 +31,7 @@ #include "esp_xt_wdt.h" #include "esp_cpu.h" -#if __has_include("esp_ota_ops.h") -#include "esp_ota_ops.h" -#define HAS_ESP_OTA 1 -#endif +#include "esp_partition.h" /***********************************************/ // Headers for other components init functions @@ -44,6 +39,11 @@ #include "esp_coexist_internal.h" #endif +#if __has_include("esp_app_desc.h") +#define WITH_APP_IMAGE_INFO +#include "esp_app_desc.h" +#endif + #if CONFIG_ESP_COREDUMP_ENABLE #include "esp_core_dump.h" #endif @@ -65,6 +65,7 @@ #include "esp_private/spi_flash_os.h" #include "esp_private/brownout.h" +#include "esp_rom_caps.h" #include "esp_rom_sys.h" #if CONFIG_SPIRAM @@ -306,6 +307,20 @@ static void do_core_init(void) _GLOBAL_REENT->_stdin = fopen(default_stdio_dev, "r"); _GLOBAL_REENT->_stdout = fopen(default_stdio_dev, "w"); _GLOBAL_REENT->_stderr = fopen(default_stdio_dev, "w"); +#if ESP_ROM_NEEDS_SWSETUP_WORKAROUND + /* + - This workaround for printf functions using 32-bit time_t after the 64-bit time_t upgrade + - The 32-bit time_t usage is triggered through ROM Newlib functions printf related functions calling __swsetup_r() on + the first call to a particular file pointer (i.e., stdin, stdout, stderr) + - Thus, we call the toolchain version of __swsetup_r() now (before any printf calls are made) to setup all of the + file pointers. Thus, the ROM newlib code will never call the ROM version of __swsetup_r(). + - See IDFGH-7728 for more details + */ + extern int __swsetup_r(struct _reent *, FILE *); + __swsetup_r(_GLOBAL_REENT, _GLOBAL_REENT->_stdout); + __swsetup_r(_GLOBAL_REENT, _GLOBAL_REENT->_stderr); + __swsetup_r(_GLOBAL_REENT, _GLOBAL_REENT->_stdin); +#endif // ESP_ROM_NEEDS_SWSETUP_WORKAROUND #else // defined(CONFIG_VFS_SUPPORT_IO) && !defined(CONFIG_ESP_CONSOLE_NONE) _REENT_SMALL_CHECK_INIT(_GLOBAL_REENT); #endif // defined(CONFIG_VFS_SUPPORT_IO) && !defined(CONFIG_ESP_CONSOLE_NONE) @@ -408,10 +423,10 @@ static void start_cpu0_default(void) int cpu_freq = esp_clk_cpu_freq(); ESP_EARLY_LOGI(TAG, "cpu freq: %d Hz", cpu_freq); -#if HAS_ESP_OTA // [refactor-todo] find a better way to handle this. +#ifdef WITH_APP_IMAGE_INFO // Display information about the current running image. if (LOG_LOCAL_LEVEL >= ESP_LOG_INFO) { - const esp_app_desc_t *app_desc = esp_ota_get_app_description(); + const esp_app_desc_t *app_desc = esp_app_get_description(); ESP_EARLY_LOGI(TAG, "Application information:"); #ifndef CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR ESP_EARLY_LOGI(TAG, "Project name: %s", app_desc->project_name); @@ -426,11 +441,11 @@ static void start_cpu0_default(void) ESP_EARLY_LOGI(TAG, "Compile time: %s %s", app_desc->date, app_desc->time); #endif char buf[17]; - esp_ota_get_app_elf_sha256(buf, sizeof(buf)); + esp_app_get_elf_sha256(buf, sizeof(buf)); ESP_EARLY_LOGI(TAG, "ELF file SHA256: %s...", buf); ESP_EARLY_LOGI(TAG, "ESP-IDF: %s", app_desc->idf_ver); } -#endif //HAS_ESP_OTA +#endif // Initialize core components and services. do_core_init(); @@ -444,7 +459,11 @@ static void start_cpu0_default(void) // Now that the application is about to start, disable boot watchdog #ifndef CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE +#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5653 + wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &LP_WDT}; +#else wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; +#endif wdt_hal_write_protect_disable(&rtc_wdt_ctx); wdt_hal_disable(&rtc_wdt_ctx); wdt_hal_write_protect_enable(&rtc_wdt_ctx); diff --git a/components/esp_system/system_time.c b/components/esp_system/system_time.c index 075f54dfa8..f6b9839089 100644 --- a/components/esp_system/system_time.c +++ b/components/esp_system/system_time.c @@ -25,6 +25,8 @@ #include "esp32h2/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rtc.h" #endif #include "esp_private/startup_internal.h" diff --git a/components/esp_system/task_wdt.c b/components/esp_system/task_wdt/task_wdt.c similarity index 82% rename from components/esp_system/task_wdt.c rename to components/esp_system/task_wdt/task_wdt.c index 58d1247bf0..9bd7770ca2 100644 --- a/components/esp_system/task_wdt.c +++ b/components/esp_system/task_wdt/task_wdt.c @@ -11,24 +11,24 @@ #include "sdkconfig.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" -#include "hal/wdt_hal.h" +#include "freertos/task_snapshot.h" #include "esp_err.h" #include "esp_attr.h" #include "esp_check.h" #include "esp_log.h" -#include "esp_intr_alloc.h" #include "esp_debug_helpers.h" #include "esp_freertos_hooks.h" #include "esp_task_wdt.h" -#include "esp_private/periph_ctrl.h" #include "esp_private/system_internal.h" #include "esp_private/crosscore_int.h" -#include "freertos/task_snapshot.h" +#include "esp_private/esp_task_wdt.h" +#include "esp_private/esp_task_wdt_impl.h" #if CONFIG_ESP_SYSTEM_USE_EH_FRAME #include "esp_private/eh_frame_parser.h" #endif // CONFIG_ESP_SYSTEM_USE_EH_FRAME + #if CONFIG_IDF_TARGET_ARCH_RISCV && !CONFIG_ESP_SYSTEM_USE_EH_FRAME /* Function used to print all the registers pointed by the given frame .*/ extern void panic_print_registers(const void *frame, int core); @@ -38,6 +38,9 @@ extern void panic_print_registers(const void *frame, int core); * a different context than the one it's called from. */ extern void xt_unhandled_exception(void *frame); +/* Forward declaration of the idle hook callback */ +static bool idle_hook_cb(void); + /* Global flag set to make the `panic` mechanism think a real `abort()` was * called. This is used in the ISR handler, in case we have to panic when * a task doesn't feed its timer. */ @@ -48,13 +51,6 @@ bool g_twdt_isr = false; // --------------------------------------------------- Definitions ----------------------------------------------------- -// ----------------------- Macros -------------------------- - -// HAL related variables and constants -#define TWDT_INSTANCE WDT_MWDT0 -#define TWDT_TICKS_PER_US MWDT0_TICKS_PER_US -#define TWDT_PRESCALER MWDT0_TICK_PRESCALER // Tick period of 500us if WDT source clock is 80MHz - // ---------------------- Typedefs ------------------------- /** @@ -71,11 +67,11 @@ struct twdt_entry { // Structure used to hold run time configuration of the TWDT typedef struct twdt_obj twdt_obj_t; struct twdt_obj { - wdt_hal_context_t hal; + twdt_ctx_t impl_ctx; SLIST_HEAD(entry_list_head, twdt_entry) entries_slist; uint32_t idle_core_mask; // Current core's who's idle tasks are subscribed bool panic; // Flag to trigger panic when TWDT times out - intr_handle_t intr_handle; + bool waiting_for_task; // Flag to start the timer as soon as a task is added }; // ----------------------- Objects ------------------------- @@ -92,50 +88,17 @@ static char core_user_names[portNUM_PROCESSORS][CORE_USER_NAME_LEN]; // ----------------------------------------------------- Private ------------------------------------------------------- -// ---------------------- Callbacks ------------------------ - -/** - * @brief User ISR callback placeholder - * - * This function is called by task_wdt_isr function (ISR for when TWDT times out). It can be redefined in user code to - * handle TWDT events. - * - * @note It has the same limitations as the interrupt function. Do not use ESP_LOGI functions inside. - */ -void __attribute__((weak)) esp_task_wdt_isr_user_handler(void) -{ - -} - -/** - * @brief Idle hook callback - * - * Idle hook callback called by the idle tasks to feed the TWDT - * - * @return Whether the idle tasks should continue idling - */ -static bool idle_hook_cb(void) -{ -#if CONFIG_FREERTOS_SMP - esp_task_wdt_reset_user(core_user_handles[xPortGetCoreID()]); -#else - esp_task_wdt_reset(); -#endif - return true; -} - // ----------------------- Helpers ------------------------- /** - * @brief Reset hardware timer and reset flags of each entry + * @brief Reset the timer and reset flags of each entry + * When entering this function, the spinlock has already been taken, no need to take it back. */ -static void reset_hw_timer(void) +static void task_wdt_timer_feed(void) { - // All tasks have reset; time to reset the hardware timer. - wdt_hal_write_protect_disable(&p_twdt_obj->hal); - wdt_hal_feed(&p_twdt_obj->hal); - wdt_hal_write_protect_enable(&p_twdt_obj->hal); - //Clear the has_reset flag in each entry + esp_task_wdt_impl_timer_feed(p_twdt_obj->impl_ctx); + + /* Clear the has_reset flag in each entry */ twdt_entry_t *entry; SLIST_FOREACH(entry, &p_twdt_obj->entries_slist, slist_entry) { entry->has_reset = false; @@ -229,8 +192,13 @@ static esp_err_t add_entry(bool is_task, void *entry_data, twdt_entry_t **entry_ } // Add entry to list SLIST_INSERT_HEAD(&p_twdt_obj->entries_slist, entry, slist_entry); + // Start the timer if it has not been started yet and was waiting on a task to registered + if (p_twdt_obj->waiting_for_task) { + esp_task_wdt_impl_timer_restart(p_twdt_obj->impl_ctx); + p_twdt_obj->waiting_for_task = false; + } if (all_reset) { //Reset hardware timer if all other tasks in list have reset in - reset_hw_timer(); + task_wdt_timer_feed(); } portEXIT_CRITICAL(&spinlock); *entry_ret = entry; @@ -269,9 +237,16 @@ static esp_err_t delete_entry(bool is_task, void *entry_data) } // Remove entry SLIST_REMOVE(&p_twdt_obj->entries_slist, entry, twdt_entry, slist_entry); - // Reset hardware timer if all remaining tasks have reset - if (all_reset) { - reset_hw_timer(); + /* Stop the timer if we don't have any more tasks/objects to watch */ + if (SLIST_EMPTY(&p_twdt_obj->entries_slist)) { + p_twdt_obj->waiting_for_task = true; + esp_task_wdt_impl_timer_stop(p_twdt_obj->impl_ctx); + } else { + p_twdt_obj->waiting_for_task = false; + } + /* Reset hardware timer if all remaining tasks have reset and if the list of tasks is not empty */ + if (!p_twdt_obj->waiting_for_task && all_reset) { + task_wdt_timer_feed(); } portEXIT_CRITICAL(&spinlock); free(entry); @@ -297,12 +272,12 @@ static void unsubscribe_idle(uint32_t core_mask) esp_deregister_freertos_idle_hook_for_cpu(idle_hook_cb, core_num); ESP_ERROR_CHECK(esp_task_wdt_delete_user(core_user_handles[core_num])); core_user_handles[core_num] = NULL; -#else +#else // CONFIG_FREERTOS_SMP TaskHandle_t idle_task_handle = xTaskGetIdleTaskHandleForCPU(core_num); assert(idle_task_handle); esp_deregister_freertos_idle_hook_for_cpu(idle_hook_cb, core_num); ESP_ERROR_CHECK(esp_task_wdt_delete(idle_task_handle)); -#endif +#endif // CONFIG_FREERTOS_SMP } core_mask >>= 1; core_num++; @@ -324,12 +299,12 @@ static void subscribe_idle(uint32_t core_mask) snprintf(core_user_names[core_num], CORE_USER_NAME_LEN, "CPU %d", (uint8_t)core_num); ESP_ERROR_CHECK(esp_task_wdt_add_user((const char *)core_user_names[core_num], &core_user_handles[core_num])); ESP_ERROR_CHECK(esp_register_freertos_idle_hook_for_cpu(idle_hook_cb, core_num)); -#else +#else // CONFIG_FREERTOS_SMP TaskHandle_t idle_task_handle = xTaskGetIdleTaskHandleForCPU(core_num); assert(idle_task_handle); ESP_ERROR_CHECK(esp_task_wdt_add(idle_task_handle)); ESP_ERROR_CHECK(esp_register_freertos_idle_hook_for_cpu(idle_hook_cb, core_num)); -#endif +#endif // CONFIG_FREERTOS_SMP } core_mask >>= 1; core_num++; @@ -498,6 +473,25 @@ static void task_wdt_timeout_handling(int cores_fail, bool panic) #endif // CONFIG_IDF_TARGET_ARCH_RISCV +// ---------------------- Callbacks ------------------------ + +/** + * @brief Idle hook callback + * + * Idle hook callback called by the idle tasks to feed the TWDT + * + * @return Whether the idle tasks should continue idling + */ +static bool idle_hook_cb(void) +{ +#if CONFIG_FREERTOS_SMP + esp_task_wdt_reset_user(core_user_handles[xPortGetCoreID()]); +#else // CONFIG_FREERTOS_SMP + esp_task_wdt_reset(); +#endif // CONFIG_FREERTOS_SMP + return true; +} + /** * @brief TWDT timeout ISR function * @@ -509,10 +503,8 @@ static void task_wdt_timeout_handling(int cores_fail, bool panic) static void task_wdt_isr(void *arg) { portENTER_CRITICAL_ISR(&spinlock); - // Reset hardware timer so that 2nd stage timeout is not reached (will trigger system reset) - wdt_hal_write_protect_disable(&p_twdt_obj->hal); - wdt_hal_handle_intr(&p_twdt_obj->hal); // Feeds WDT and clears acknowledges interrupt - wdt_hal_write_protect_enable(&p_twdt_obj->hal); + esp_task_wdt_impl_timeout_triggered(p_twdt_obj->impl_ctx); + // If there are no entries, there's nothing to do. if (SLIST_EMPTY(&p_twdt_obj->entries_slist)) { portEXIT_CRITICAL_ISR(&spinlock); @@ -578,8 +570,15 @@ static void task_wdt_isr(void *arg) } portEXIT_CRITICAL_ISR(&spinlock); - // Run user ISR handler - esp_task_wdt_isr_user_handler(); + /* Run user ISR handler. + * This function has been declared as weak, thus, it may be possible that it was not defines. + * to check this, we can directly test its address. In any case, the linker will get rid of + * this `if` when linking, this means that if the function was not defined, the whole `if` + * block will be discarded (zero runtime overhead), else only the function call will be kept. + */ + if (esp_task_wdt_isr_user_handler != NULL) { + esp_task_wdt_isr_user_handler(); + } // Trigger configured timeout behavior (e.g., panic or print backtrace) assert(cpus_fail != 0); @@ -592,81 +591,153 @@ esp_err_t esp_task_wdt_init(const esp_task_wdt_config_t *config) { ESP_RETURN_ON_FALSE((config != NULL && config->idle_core_mask < (1 << portNUM_PROCESSORS)), ESP_ERR_INVALID_ARG, TAG, "Invalid arguments"); ESP_RETURN_ON_FALSE(p_twdt_obj == NULL, ESP_ERR_INVALID_STATE, TAG, "TWDT already initialized"); - esp_err_t ret; - + esp_err_t ret = ESP_OK; twdt_obj_t *obj = NULL; - if (p_twdt_obj == NULL) { - // Allocate and initialize TWDT driver object - obj = calloc(1, sizeof(twdt_obj_t)); - ESP_GOTO_ON_FALSE((obj != NULL), ESP_ERR_NO_MEM, err, TAG, "insufficient memory"); - SLIST_INIT(&obj->entries_slist); - obj->panic = config->trigger_panic; - ESP_ERROR_CHECK(esp_intr_alloc(ETS_TG0_WDT_LEVEL_INTR_SOURCE, 0, task_wdt_isr, NULL, &obj->intr_handle)); - portENTER_CRITICAL(&spinlock); - // Configure hardware timer - periph_module_enable(PERIPH_TIMG0_MODULE); - wdt_hal_init(&obj->hal, TWDT_INSTANCE, TWDT_PRESCALER, true); - // Assign the driver object - p_twdt_obj = obj; - portEXIT_CRITICAL(&spinlock); + + /* Allocate and initialize the global object */ + obj = calloc(1, sizeof(twdt_obj_t)); + ESP_GOTO_ON_FALSE((obj != NULL), ESP_ERR_NO_MEM, err, TAG, "insufficient memory"); + SLIST_INIT(&obj->entries_slist); + obj->panic = config->trigger_panic; + + /* Allocate the timer itself, NOT STARTED */ + ret = esp_task_wdt_impl_timer_allocate(config, task_wdt_isr, &obj->impl_ctx); + if (ret != ESP_OK) { + goto err; } - portENTER_CRITICAL(&spinlock); - wdt_hal_write_protect_disable(&p_twdt_obj->hal); - // Configure 1st stage timeout and behavior - wdt_hal_config_stage(&p_twdt_obj->hal, WDT_STAGE0, config->timeout_ms * (1000 / TWDT_TICKS_PER_US), WDT_STAGE_ACTION_INT); - // Configure 2nd stage timeout and behavior - wdt_hal_config_stage(&p_twdt_obj->hal, WDT_STAGE1, config->timeout_ms * (2 * 1000 / TWDT_TICKS_PER_US), WDT_STAGE_ACTION_RESET_SYSTEM); - // Enable the WDT - wdt_hal_enable(&p_twdt_obj->hal); - wdt_hal_write_protect_enable(&p_twdt_obj->hal); - // Update which core's idle tasks are subscribed - uint32_t old_core_mask = p_twdt_obj->idle_core_mask; + /* No error so far, we can assign it to the driver object */ + p_twdt_obj = obj; + + /* Update which core's idle tasks are subscribed */ p_twdt_obj->idle_core_mask = config->idle_core_mask; - portEXIT_CRITICAL(&spinlock); - if (old_core_mask) { - // Unsubscribe all previously watched core idle tasks - unsubscribe_idle(old_core_mask); - } if (config->idle_core_mask) { - // Subscribe the new cores idle tasks + /* Subscribe the new cores idle tasks */ subscribe_idle(config->idle_core_mask); } - ret = ESP_OK; + /* Start the timer only if we are watching some tasks */ + if (!SLIST_EMPTY(&p_twdt_obj->entries_slist)) { + p_twdt_obj->waiting_for_task = false; + esp_task_wdt_impl_timer_restart(p_twdt_obj->impl_ctx); + } else { + p_twdt_obj->waiting_for_task = true; + } + + return ESP_OK; err: + free(obj); + return ret; +} + +esp_err_t esp_task_wdt_reconfigure(const esp_task_wdt_config_t *config) +{ + ESP_RETURN_ON_FALSE((config != NULL && config->idle_core_mask < (1 << portNUM_PROCESSORS)), ESP_ERR_INVALID_ARG, TAG, "Invalid arguments"); + ESP_RETURN_ON_FALSE(p_twdt_obj != NULL, ESP_ERR_INVALID_STATE, TAG, "TWDT not initialized yet"); + uint32_t old_core_mask = 0; + esp_err_t ret = ESP_OK; + + /* Stop the timer to make sure we don't get into the ISR while reconfiguring the TWDT */ + portENTER_CRITICAL(&spinlock); + ret = esp_task_wdt_impl_timer_stop(p_twdt_obj->impl_ctx); + if (ret != ESP_OK) { + goto err; + } + + /* We can start reconfiguring the tasks */ + p_twdt_obj->panic = config->trigger_panic; + + /* Reconfigure the timer underneath (without restarting it) */ + ret = esp_task_wdt_impl_timer_reconfigure(p_twdt_obj->impl_ctx, config); + if (ret != ESP_OK) { + goto err; + } + + old_core_mask = p_twdt_obj->idle_core_mask; + /* If the new mask is different than the old one, we have to subscribe the new idle tasks */ + if (old_core_mask != config->idle_core_mask) { + p_twdt_obj->idle_core_mask = config->idle_core_mask; + + /* Unsubscribe all previously watched core idle tasks */ + unsubscribe_idle(old_core_mask); + + if (config->idle_core_mask) { + /* Subscribe the new cores idle tasks */ + subscribe_idle(config->idle_core_mask); + } + } + + /* Start the timer only if we are watching some tasks */ + if (!SLIST_EMPTY(&p_twdt_obj->entries_slist)) { + esp_task_wdt_impl_timer_restart(p_twdt_obj->impl_ctx); + } + + portEXIT_CRITICAL(&spinlock); +err: + return ESP_OK; +} + +esp_err_t esp_task_wdt_stop(void) +{ + esp_err_t ret = ESP_OK; + + /* If the timer has not been initialized, do not attempt to stop it */ + if (p_twdt_obj == NULL) { + ret = ESP_ERR_INVALID_STATE; + } + + if (ret == ESP_OK) { + portENTER_CRITICAL(&spinlock); + ret = esp_task_wdt_impl_timer_stop(p_twdt_obj->impl_ctx); + portEXIT_CRITICAL(&spinlock); + } + + return ret; +} + +esp_err_t esp_task_wdt_restart(void) +{ + esp_err_t ret = ESP_OK; + + /* If the timer has not been initialized, do not attempt to stop it */ + if (p_twdt_obj == NULL) { + ret = ESP_ERR_INVALID_STATE; + } + + if (ret == ESP_OK) { + portENTER_CRITICAL(&spinlock); + ret = esp_task_wdt_impl_timer_restart(p_twdt_obj->impl_ctx); + portEXIT_CRITICAL(&spinlock); + } + return ret; } esp_err_t esp_task_wdt_deinit(void) { + esp_err_t ret; + ESP_RETURN_ON_FALSE(p_twdt_obj != NULL, ESP_ERR_INVALID_STATE, TAG, "TWDT was never initialized"); - esp_err_t ret; // Unsubscribe all previously watched core idle tasks unsubscribe_idle(p_twdt_obj->idle_core_mask); - portENTER_CRITICAL(&spinlock); // Check TWDT state ESP_GOTO_ON_FALSE_ISR(SLIST_EMPTY(&p_twdt_obj->entries_slist), ESP_ERR_INVALID_STATE, err, TAG, "Tasks/users still subscribed"); - // Disable hardware timer and the interrupt - wdt_hal_write_protect_disable(&p_twdt_obj->hal); - wdt_hal_disable(&p_twdt_obj->hal); - wdt_hal_write_protect_enable(&p_twdt_obj->hal); - wdt_hal_deinit(&p_twdt_obj->hal); - esp_intr_disable(p_twdt_obj->intr_handle); - // Unassign driver object - twdt_obj_t *obj = p_twdt_obj; - p_twdt_obj = NULL; - portEXIT_CRITICAL(&spinlock); + + // Disable the timer + esp_task_wdt_impl_timer_stop(p_twdt_obj->impl_ctx); // Free driver resources - ESP_ERROR_CHECK(esp_intr_free(obj->intr_handle)); // Deregister interrupt - free(obj); // Free p_twdt_obj + esp_task_wdt_impl_timer_free(p_twdt_obj->impl_ctx); + + // Free the global object + free(p_twdt_obj); + p_twdt_obj = NULL; + return ESP_OK; err: - portEXIT_CRITICAL(&spinlock); subscribe_idle(p_twdt_obj->idle_core_mask); // Resubscribe idle tasks return ret; } @@ -713,7 +784,7 @@ esp_err_t esp_task_wdt_reset(void) // Mark entry as reset and issue timer reset if all entries have been reset entry->has_reset = true; // Reset the task if it's on the task list if (all_reset) { // Reset if all other tasks in list have reset in - reset_hw_timer(); + task_wdt_timer_feed(); } ret = ESP_OK; err: @@ -737,7 +808,7 @@ esp_err_t esp_task_wdt_reset_user(esp_task_wdt_user_handle_t user_handle) // Mark entry as reset and issue timer reset if all entries have been reset entry->has_reset = true; // Reset the task if it's on the task list if (all_reset) { // Reset if all other tasks in list have reset in - reset_hw_timer(); + task_wdt_timer_feed(); } ret = ESP_OK; err: diff --git a/components/esp_system/task_wdt/task_wdt_impl_esp_timer.c b/components/esp_system/task_wdt/task_wdt_impl_esp_timer.c new file mode 100644 index 0000000000..35bc61bc3e --- /dev/null +++ b/components/esp_system/task_wdt/task_wdt_impl_esp_timer.c @@ -0,0 +1,155 @@ +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include "sdkconfig.h" +#include "hal/wdt_hal.h" +#include "esp_err.h" +#include "esp_attr.h" +#include "esp_check.h" +#include "esp_log.h" +#include "esp_debug_helpers.h" +#include "esp_timer.h" +#include "esp_private/esp_task_wdt_impl.h" + +/** + * Private API provided by esp_timer component to feed a timer without + * the need of disabling it, removing it and inserting it manually. + */ +esp_err_t esp_timer_feed(esp_timer_handle_t timer); + +/** + * Context for the software implementation of the Task WatchDog Timer. + * This will be passed as a parameter to public functions below. */ +typedef struct { + esp_timer_handle_t sw_timer; + uint32_t period_ms; +} twdt_ctx_soft_t; + +/** + * Declare the initial context as static. It will be passed to the + * task_wdt implementation as the implementation context in the + * init function. */ +static twdt_ctx_soft_t init_context; + +static const char *TAG = "task_wdt_impl_soft"; + + +esp_err_t esp_task_wdt_impl_timer_allocate(const esp_task_wdt_config_t *config, + twdt_isr_callback callback, + twdt_ctx_t *obj) +{ + twdt_ctx_soft_t *ctx = &init_context; + const esp_timer_create_args_t timer_args = { + .callback = callback, + .arg = NULL, + .dispatch_method = ESP_TIMER_ISR, + .name = "Task software watchdog", + .skip_unhandled_events = true + }; + + /* Software Task timer. As we don't have a spare hardware watchdog timer, we will use esp_timer to simulate one */ + esp_err_t ret = esp_timer_create(&timer_args, &ctx->sw_timer); + ESP_GOTO_ON_FALSE((ret == ESP_OK), ret, reterr, TAG, "could not start periodic timer"); + + /* Configure it as a periodic timer, so that we check the Tasks everytime it is triggered. + * No need to start the timer here, it will be started later with `esp_task_wdt_impl_timer_restart` */ + ctx->period_ms = config->timeout_ms; + + /* Return our context to the caller */ + *obj = (twdt_ctx_t) ctx; + +reterr: + return ret; +} + +esp_err_t esp_task_wdt_impl_timer_reconfigure(twdt_ctx_t obj, const esp_task_wdt_config_t *config) +{ + esp_err_t ret = ESP_OK; + twdt_ctx_soft_t* ctx = (twdt_ctx_soft_t*) obj; + + if (config == NULL || ctx == NULL) { + ret = ESP_ERR_INVALID_STATE; + } + + if (ret == ESP_OK) { + /* The timer is stopped, we only need to update the period in our context, next time we start the + * timer with `esp_task_wdt_impl_timer_restart`, we will pass the context's period to the + * underlying esp_timer instance. */ + ctx->period_ms = config->timeout_ms; + } + + return ret; +} + + +void esp_task_wdt_impl_timer_free(twdt_ctx_t obj) +{ + const twdt_ctx_soft_t* ctx = (twdt_ctx_soft_t*) obj; + + if (ctx != NULL && ctx->sw_timer != NULL) { + ESP_ERROR_CHECK(esp_timer_delete(ctx->sw_timer)); + } +} + + +esp_err_t esp_task_wdt_impl_timer_feed(twdt_ctx_t obj) +{ + esp_err_t ret = ESP_OK; + const twdt_ctx_soft_t* ctx = (twdt_ctx_soft_t*) obj; + + if (ctx == NULL) { + ret = ESP_ERR_INVALID_STATE; + } + + if (ret == ESP_OK) { + ret = esp_timer_feed(ctx->sw_timer); + } + + return ret; +} + + +void esp_task_wdt_impl_timeout_triggered(twdt_ctx_t obj) +{ + (void) obj; +} + + +esp_err_t esp_task_wdt_impl_timer_stop(twdt_ctx_t obj) +{ + esp_err_t ret = ESP_OK; + const twdt_ctx_soft_t* ctx = (twdt_ctx_soft_t*) obj; + + if (ctx == NULL || ctx->sw_timer == NULL) { + ret = ESP_ERR_INVALID_STATE; + } + + if (ret == ESP_OK) { + ret = esp_timer_stop(ctx->sw_timer); + } + + return ret; +} + + +esp_err_t esp_task_wdt_impl_timer_restart(twdt_ctx_t obj) +{ + esp_err_t ret = ESP_OK; + twdt_ctx_soft_t* ctx = (twdt_ctx_soft_t*) obj; + + if (ctx == NULL || ctx->sw_timer == NULL) { + ret = ESP_ERR_INVALID_STATE; + } + + if (ret == ESP_OK) { + esp_timer_start_periodic(ctx->sw_timer, ctx->period_ms * 1000); + } + + return ret; +} diff --git a/components/esp_system/task_wdt/task_wdt_impl_timergroup.c b/components/esp_system/task_wdt/task_wdt_impl_timergroup.c new file mode 100644 index 0000000000..57af2cd7e0 --- /dev/null +++ b/components/esp_system/task_wdt/task_wdt_impl_timergroup.c @@ -0,0 +1,184 @@ +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include "sdkconfig.h" +#include "hal/wdt_hal.h" +#include "esp_err.h" +#include "esp_attr.h" +#include "esp_intr_alloc.h" +#include "esp_private/system_internal.h" +#include "esp_private/periph_ctrl.h" +#include "esp_private/esp_task_wdt_impl.h" + +#define TWDT_INSTANCE WDT_MWDT0 +#define TWDT_TICKS_PER_US MWDT0_TICKS_PER_US +#define TWDT_PRESCALER MWDT0_TICK_PRESCALER // Tick period of 500us if WDT source clock is 80MHz +#define TWDT_PERIPH_MODULE PERIPH_TIMG0_MODULE +#define TWDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE + +/** + * Context for the software implementation of the Task WatchDog Timer. + * This will be passed as a parameter to public functions below. */ +typedef struct { + wdt_hal_context_t hal; + intr_handle_t intr_handle; +} twdt_ctx_hard_t; + +/** + * Declare the initial context as static. It will be passed to the + * task_wdt implementation as the implementation context in the + * init function. */ +static twdt_ctx_hard_t init_context; + + + +esp_err_t esp_task_wdt_impl_timer_allocate(const esp_task_wdt_config_t *config, + twdt_isr_callback callback, + twdt_ctx_t *obj) +{ + esp_err_t ret = ESP_OK; + twdt_ctx_hard_t *ctx = &init_context; + + if (config == NULL || obj == NULL) { + ret = ESP_ERR_INVALID_STATE; + } + + if (ret == ESP_OK) { + esp_intr_alloc(TWDT_INTR_SOURCE, 0, callback, NULL, &ctx->intr_handle); + } + + if (ret == ESP_OK) { + periph_module_enable(TWDT_PERIPH_MODULE); + wdt_hal_init(&ctx->hal, TWDT_INSTANCE, TWDT_PRESCALER, true); + + wdt_hal_write_protect_disable(&ctx->hal); + // Configure 1st stage timeout and behavior + wdt_hal_config_stage(&ctx->hal, WDT_STAGE0, config->timeout_ms * (1000 / TWDT_TICKS_PER_US), WDT_STAGE_ACTION_INT); + // Configure 2nd stage timeout and behavior + wdt_hal_config_stage(&ctx->hal, WDT_STAGE1, config->timeout_ms * (2 * 1000 / TWDT_TICKS_PER_US), WDT_STAGE_ACTION_RESET_SYSTEM); + // No need to enable to enable the WDT here, it will be enabled with `esp_task_wdt_impl_timer_restart` + wdt_hal_write_protect_enable(&ctx->hal); + + /* Return the implementation context to the caller */ + *obj = (twdt_ctx_t) ctx; + } + + return ret; +} + + +esp_err_t esp_task_wdt_impl_timer_reconfigure(twdt_ctx_t obj, const esp_task_wdt_config_t *config) +{ + esp_err_t ret = ESP_OK; + + twdt_ctx_hard_t* ctx = (twdt_ctx_hard_t*) obj; + + if (config == NULL || ctx == NULL) { + ret = ESP_ERR_INVALID_STATE; + } + + if (ret == ESP_OK) { + wdt_hal_write_protect_disable(&ctx->hal); + /* Reconfigure the 1st and 2nd stage timeout */ + wdt_hal_config_stage(&ctx->hal, WDT_STAGE0, config->timeout_ms * (1000 / TWDT_TICKS_PER_US), WDT_STAGE_ACTION_INT); + wdt_hal_config_stage(&ctx->hal, WDT_STAGE1, config->timeout_ms * (2 * 1000 / TWDT_TICKS_PER_US), WDT_STAGE_ACTION_RESET_SYSTEM); + wdt_hal_write_protect_enable(&ctx->hal); + } + + return ret; +} + + +void esp_task_wdt_impl_timer_free(twdt_ctx_t obj) +{ + twdt_ctx_hard_t* ctx = (twdt_ctx_hard_t*) obj; + + if (ctx != NULL) { + /* Stop hardware timer and the interrupt associated */ + wdt_hal_deinit(&ctx->hal); + ESP_ERROR_CHECK(esp_intr_disable(ctx->intr_handle)); + + /* Disable the Timer Group module */ + periph_module_enable(TWDT_PERIPH_MODULE); + + /* Deregister interrupt */ + ESP_ERROR_CHECK(esp_intr_free(ctx->intr_handle)); + } +} + + +esp_err_t esp_task_wdt_impl_timer_feed(twdt_ctx_t obj) +{ + esp_err_t ret = ESP_OK; + twdt_ctx_hard_t* ctx = (twdt_ctx_hard_t*) obj; + + if (ctx == NULL) { + ret = ESP_ERR_INVALID_STATE; + } + + if (ret == ESP_OK) { + wdt_hal_write_protect_disable(&ctx->hal); + wdt_hal_feed(&ctx->hal); + wdt_hal_write_protect_enable(&ctx->hal); + } + + return ret; +} + + +void esp_task_wdt_impl_timeout_triggered(twdt_ctx_t obj) +{ + twdt_ctx_hard_t* ctx = (twdt_ctx_hard_t*) obj; + + if (ctx != NULL) { + /* Reset hardware timer so that 2nd stage timeout is not reached (will trigger system reset) */ + wdt_hal_write_protect_disable(&ctx->hal); + wdt_hal_handle_intr(&ctx->hal); // Feeds WDT and clears acknowledges interrupt + wdt_hal_write_protect_enable(&ctx->hal); + } +} + + +esp_err_t esp_task_wdt_impl_timer_stop(twdt_ctx_t obj) +{ + esp_err_t ret = ESP_OK; + twdt_ctx_hard_t* ctx = (twdt_ctx_hard_t*) obj; + + if (ctx == NULL) { + ret = ESP_ERR_INVALID_STATE; + } + + if (ret == ESP_OK) { + wdt_hal_write_protect_disable(&ctx->hal); + wdt_hal_disable(&ctx->hal); + wdt_hal_write_protect_enable(&ctx->hal); + } + + return ret; +} + + +esp_err_t esp_task_wdt_impl_timer_restart(twdt_ctx_t obj) +{ + esp_err_t ret = ESP_OK; + twdt_ctx_hard_t* ctx = (twdt_ctx_hard_t*) obj; + + if (ctx == NULL) { + ret = ESP_ERR_INVALID_STATE; + } + + if (ret == ESP_OK) { + wdt_hal_write_protect_disable(&ctx->hal); + wdt_hal_enable(&ctx->hal); + wdt_hal_feed(&ctx->hal); + wdt_hal_write_protect_enable(&ctx->hal); + } + + return ret; +} diff --git a/components/esp_system/test/test_reset_reason.c b/components/esp_system/test/test_reset_reason.c index 9347b8b013..60b1c343a4 100644 --- a/components/esp_system/test/test_reset_reason.c +++ b/components/esp_system/test/test_reset_reason.c @@ -2,11 +2,11 @@ #include "esp_system.h" #include "esp_task_wdt.h" #include "esp_attr.h" +#include "esp_sleep.h" #include "soc/rtc.h" #include "hal/wdt_hal.h" -#include "esp_sleep.h" #if CONFIG_IDF_TARGET_ARCH_RISCV -#include "riscv/riscv_interrupts.h" +#include "riscv/rv_utils.h" #endif #define RTC_BSS_ATTR __attribute__((section(".rtc.bss"))) @@ -199,7 +199,7 @@ static void do_int_wdt_hw(void) { setup_values(); #if CONFIG_IDF_TARGET_ARCH_RISCV - riscv_global_interrupts_disable(); + rv_utils_intr_global_disable(); #else XTOS_SET_INTLEVEL(XCHAL_NMILEVEL); #endif @@ -222,6 +222,7 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_INT_WDT after interrupt watchdog do_int_wdt_hw, check_reset_reason_int_wdt); +#if CONFIG_ESP_TASK_WDT_EN static void do_task_wdt(void) { setup_values(); @@ -251,6 +252,7 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_TASK_WDT after task watchdog", "[reset_reason][reset="RESET"]", do_task_wdt, check_reset_reason_task_wdt); +#endif // CONFIG_ESP_TASK_WDT_EN static void do_rtc_wdt(void) { diff --git a/components/esp_system/test/test_sleep.c b/components/esp_system/test/test_sleep.c index 9979b1e624..1a9e2d4df0 100644 --- a/components/esp_system/test/test_sleep.c +++ b/components/esp_system/test/test_sleep.c @@ -15,6 +15,7 @@ #include "soc/gpio_periph.h" #include "hal/uart_types.h" #include "hal/uart_ll.h" +#include "driver/uart.h" #include "soc/rtc.h" // for wakeup trigger defines #include "soc/rtc_periph.h" // for read rtc registers directly (cause) #include "soc/soc.h" // for direct register read macros @@ -208,7 +209,10 @@ TEST_CASE("light sleep and frequency switching", "[deepsleep]") clk_source = UART_SCLK_XTAL; #endif uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), clk_source); - uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), CONFIG_ESP_CONSOLE_UART_BAUDRATE); + + uint32_t sclk_freq; + TEST_ESP_OK(uart_get_sclk_freq(clk_source, &sclk_freq)); + uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), CONFIG_ESP_CONSOLE_UART_BAUDRATE, sclk_freq); #endif rtc_cpu_freq_config_t config_xtal, config_default; diff --git a/components/esp_system/test/test_task_wdt.c b/components/esp_system/test/test_task_wdt.c index b80ccae0be..858dcd9ecf 100644 --- a/components/esp_system/test/test_task_wdt.c +++ b/components/esp_system/test/test_task_wdt.c @@ -4,6 +4,10 @@ * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ +#include "sdkconfig.h" + +#if CONFIG_ESP_TASK_WDT_EN + #include #include "unity.h" #include "esp_rom_sys.h" @@ -19,8 +23,6 @@ void esp_task_wdt_isr_user_handler(void) timeout_flag = true; } -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) -//IDF-5055 TEST_CASE("Task WDT task timeout", "[task_wdt]") { timeout_flag = false; @@ -37,7 +39,60 @@ TEST_CASE("Task WDT task timeout", "[task_wdt]") TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_delete(NULL)); TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_deinit()); } -#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) + +TEST_CASE("Task WDT inactive when no task to watch", "[task_wdt]") +{ + /* Make sure a timeout is NOT trigger when we have no task to watch */ + timeout_flag = false; + esp_task_wdt_config_t twdt_config = { + .timeout_ms = TASK_WDT_TIMEOUT_MS, + .idle_core_mask = 0, + .trigger_panic = false, + }; + TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_init(&twdt_config)); + esp_rom_delay_us(2 * TASK_WDT_TIMEOUT_MS * 1000); + TEST_ASSERT_EQUAL(false, timeout_flag); + /* Add a task to watch, it should start the watchdog */ + TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_add(NULL)); + esp_rom_delay_us(TASK_WDT_TIMEOUT_MS * 1000); + TEST_ASSERT_EQUAL(true, timeout_flag); + /* Remove the task we just addded and make sure the WDT is stopped*/ + timeout_flag = false; + TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_delete(NULL)); + esp_rom_delay_us(2 * TASK_WDT_TIMEOUT_MS * 1000); + TEST_ASSERT_EQUAL(false, timeout_flag); + /* Success, terminate the test */ + TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_deinit()); +} + +TEST_CASE("Task WDT can be reconfigured", "[task_wdt]") +{ + /* Make sure a timeout is NOT trigger when we have no task to watch */ + timeout_flag = false; + esp_task_wdt_config_t twdt_config = { + .timeout_ms = TASK_WDT_TIMEOUT_MS / 2, + .idle_core_mask = 0, + .trigger_panic = false, + }; + TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_init(&twdt_config)); + TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_add(NULL)); + /* Timer started, check that a timeout is raised after a while */ + esp_rom_delay_us((TASK_WDT_TIMEOUT_MS / 2 + 1) * 1000); + TEST_ASSERT_EQUAL(true, timeout_flag); + /* Reconfigure the timer with a bigger timeout. The timer is restarted + * after reconfiguring it. */ + twdt_config.timeout_ms = TASK_WDT_TIMEOUT_MS; + timeout_flag = false; + TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_reconfigure(&twdt_config)); + esp_rom_delay_us((TASK_WDT_TIMEOUT_MS / 2 + 1) * 1000); + TEST_ASSERT_EQUAL(false, timeout_flag); + /* Should be triggered now, we've spent TASK_WDT_TIMEOUT_MS waiting */ + esp_rom_delay_us((TASK_WDT_TIMEOUT_MS / 2 + 1) * 1000); + TEST_ASSERT_EQUAL(true, timeout_flag); + /* Success, terminate the test */ + TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_delete(NULL)); + TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_deinit()); +} TEST_CASE("Task WDT task feed", "[task_wdt]") { @@ -58,8 +113,6 @@ TEST_CASE("Task WDT task feed", "[task_wdt]") TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_deinit()); } -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) -//IDF-5055 TEST_CASE("Task WDT user timeout", "[task_wdt]") { const char *user_name = "test_user"; @@ -78,7 +131,6 @@ TEST_CASE("Task WDT user timeout", "[task_wdt]") TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_delete_user(user_handle)); TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_deinit()); } -#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) TEST_CASE("Task WDT user feed", "[task_wdt]") { @@ -100,3 +152,5 @@ TEST_CASE("Task WDT user feed", "[task_wdt]") TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_delete_user(user_handle)); TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_deinit()); } + +#endif // CONFIG_ESP_TASK_WDT_EN diff --git a/components/esp_timer/include/esp_private/esp_timer_private.h b/components/esp_timer/include/esp_private/esp_timer_private.h index 4744b20a39..37aaeac03f 100644 --- a/components/esp_timer/include/esp_private/esp_timer_private.h +++ b/components/esp_timer/include/esp_private/esp_timer_private.h @@ -51,11 +51,11 @@ void esp_timer_private_set(uint64_t new_us); void esp_timer_private_advance(int64_t time_diff_us); /** - * @brief obtain internal critical section used esp_timer implementation + * @brief obtain internal critical section used in the esp_timer implementation * This can be used when a sequence of calls to esp_timer has to be made, * and it is necessary that the state of the timer is consistent between * the calls. Should be treated in the same way as a spinlock. - * Call esp_timer_unlock to release the lock + * Call esp_timer_private_unlock to release the lock */ void esp_timer_private_lock(void); diff --git a/components/esp_timer/src/esp_timer.c b/components/esp_timer/src/esp_timer.c index 3ca19f642f..bca212d253 100644 --- a/components/esp_timer/src/esp_timer.c +++ b/components/esp_timer/src/esp_timer.c @@ -34,6 +34,8 @@ #include "esp32h2/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rtc.h" #endif #include "sdkconfig.h" @@ -141,6 +143,49 @@ esp_err_t esp_timer_create(const esp_timer_create_args_t* args, return ESP_OK; } +/** + * Function to feed a timer. It is not part of the public header + * file on purpose as it shall only be used by the Task WDT component. + */ +esp_err_t esp_timer_feed(esp_timer_handle_t timer) +{ + esp_err_t ret = ESP_OK; + + if (timer == NULL) { + return ESP_ERR_INVALID_ARG; + } + + if (!is_initialized() || !timer_armed(timer) || timer->period == 0 ) { + return ESP_ERR_INVALID_STATE; + } + + esp_timer_dispatch_t dispatch_method = timer->flags & FL_ISR_DISPATCH_METHOD; + timer_list_lock(dispatch_method); + + const int64_t now = esp_timer_impl_get_time(); + const uint64_t period = timer->period; + /* Currently we are guaranteed that the remaining delay between now and the timer's + * alarm is less than the period, so the following won't cause the alarm to be + * triggered earlier than before feeding occurs. */ + const uint64_t alarm = now + period; + + /* We need to remove the timer to the list of timers and reinsert it at + * the right position. In fact, the timers are sorted by their alarm value + * (earliest first) */ + ret = timer_remove(timer); + + if (ret == ESP_OK) { + /* Remove function got rid of the alarm and period fields, restore them */ + timer->alarm = alarm; + timer->period = period; + ret = timer_insert(timer, false); + } + + timer_list_unlock(dispatch_method); + + return ret; +} + esp_err_t IRAM_ATTR esp_timer_start_once(esp_timer_handle_t timer, uint64_t timeout_us) { if (timer == NULL) { diff --git a/components/esp_timer/src/ets_timer_legacy.c b/components/esp_timer/src/ets_timer_legacy.c index 841f8d04f1..d03aa7cbcd 100644 --- a/components/esp_timer/src/ets_timer_legacy.c +++ b/components/esp_timer/src/ets_timer_legacy.c @@ -34,6 +34,8 @@ #include "esp32c2/rom/ets_sys.h" #elif CONFIG_IDF_TARGET_ESP32H2 #include "esp32h2/rom/ets_sys.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/ets_sys.h" #endif /* We abuse 'timer_arg' field of ETSTimer structure to hold a pointer to esp_timer */ diff --git a/components/esp_timer/src/system_time.c b/components/esp_timer/src/system_time.c index 6387422c86..ddc5949a0e 100644 --- a/components/esp_timer/src/system_time.c +++ b/components/esp_timer/src/system_time.c @@ -29,6 +29,8 @@ #include "esp32h2/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rtc.h" #endif __attribute__((unused)) static const char* TAG = "system_time"; diff --git a/components/esp_timer/test/test_esp_timer.c b/components/esp_timer/test/test_esp_timer.c index bb24c44ac4..e26b0c40c2 100644 --- a/components/esp_timer/test/test_esp_timer.c +++ b/components/esp_timer/test/test_esp_timer.c @@ -866,6 +866,49 @@ TEST_CASE("Test a latency between a call of callback and real event", "[esp_time TEST_ESP_OK(esp_timer_delete(periodic_timer)); } +static void test_periodic_timer_feed(void* timer1_fed) +{ + *((int*) timer1_fed) = 1; +} + +/** + * Feed function is not part of the esp_timer header file: it's a public in the sense that it is not static, + * but it is only meant to be used in IDF components. + */ +esp_err_t esp_timer_feed(esp_timer_handle_t timer); + +TEST_CASE("periodic esp_timer can be fed", "[esp_timer]") +{ + const int delay_ms = 100; + int timer_fed = 0; + esp_timer_handle_t timer1; + esp_timer_create_args_t create_args = { + .callback = &test_periodic_timer_feed, + .arg = &timer_fed, + .name = "timer1", + }; + TEST_ESP_OK(esp_timer_create(&create_args, &timer1)); + TEST_ESP_OK(esp_timer_start_periodic(timer1, delay_ms * 1000)); + /* Sleep for delay_ms/2 and feed the timer */ + vTaskDelay((delay_ms / 2) * portTICK_PERIOD_MS); + /* Check that the alarm was not triggered */ + TEST_ASSERT_EQUAL(0, timer_fed); + /* Reaching this point, the timer will be triggered in delay_ms/2. + * Let's feed the timer now. */ + TEST_ESP_OK(esp_timer_feed(timer1)); + /* Sleep for a bit more than delay_ms/2 */ + vTaskDelay(((delay_ms / 2) + 1) * portTICK_PERIOD_MS); + /* If the alarm was triggered, feed didn't work */ + TEST_ASSERT_EQUAL(0, timer_fed); + /* Else, wait for another delay_ms/2, which should trigger the alarm */ + vTaskDelay(((delay_ms / 2) + 1) * portTICK_PERIOD_MS); + TEST_ASSERT_EQUAL(1, timer_fed); + + TEST_ESP_OK( esp_timer_stop(timer1) ); + TEST_ESP_OK( esp_timer_delete(timer1) ); +} + + #ifdef CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD static int64_t old_time[2]; diff --git a/components/esp_timer/test/test_ets_timer.c b/components/esp_timer/test/test_ets_timer.c index b72e4fdf9e..15ba842ece 100644 --- a/components/esp_timer/test/test_ets_timer.c +++ b/components/esp_timer/test/test_ets_timer.c @@ -26,6 +26,8 @@ #include "esp32h2/rom/ets_sys.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/ets_sys.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/ets_sys.h" #endif static void test_correct_delay_timer_func(void* arg) diff --git a/components/esp_wifi/CMakeLists.txt b/components/esp_wifi/CMakeLists.txt index 1323d51e3f..5722e0a00c 100644 --- a/components/esp_wifi/CMakeLists.txt +++ b/components/esp_wifi/CMakeLists.txt @@ -39,7 +39,7 @@ if(CONFIG_ESP32_WIFI_ENABLED) idf_build_get_property(build_dir BUILD_DIR) set(target_name "${idf_target}") - target_link_libraries(${COMPONENT_LIB} PUBLIC "-L \"${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}\"") + target_link_directories(${COMPONENT_LIB} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}") if(link_binary_libs) if(CONFIG_IDF_TARGET_ESP32C2) diff --git a/components/esp_wifi/esp32c2/esp_adapter.c b/components/esp_wifi/esp32c2/esp_adapter.c index 2b7827683a..96b32a1f7d 100644 --- a/components/esp_wifi/esp32c2/esp_adapter.c +++ b/components/esp_wifi/esp32c2/esp_adapter.c @@ -18,7 +18,6 @@ #include "freertos/event_groups.h" #include "freertos/portmacro.h" #include "riscv/interrupt.h" -#include "riscv/riscv_interrupts.h" #include "esp_types.h" #include "esp_random.h" #include "esp_mac.h" diff --git a/components/esp_wifi/esp32c3/esp_adapter.c b/components/esp_wifi/esp32c3/esp_adapter.c index 65f594dc00..c5d1d7c5ab 100644 --- a/components/esp_wifi/esp32c3/esp_adapter.c +++ b/components/esp_wifi/esp32c3/esp_adapter.c @@ -18,7 +18,6 @@ #include "freertos/event_groups.h" #include "freertos/portmacro.h" #include "riscv/interrupt.h" -#include "riscv/riscv_interrupts.h" #include "esp_types.h" #include "esp_random.h" #include "esp_mac.h" diff --git a/components/esp_wifi/include/esp_wifi.h b/components/esp_wifi/include/esp_wifi.h index c58ee53fe6..6ba1e98812 100644 --- a/components/esp_wifi/include/esp_wifi.h +++ b/components/esp_wifi/include/esp_wifi.h @@ -453,6 +453,21 @@ esp_err_t esp_wifi_scan_get_ap_num(uint16_t *number); esp_err_t esp_wifi_scan_get_ap_records(uint16_t *number, wifi_ap_record_t *ap_records); +/** + * @brief Clear AP list found in last scan + * + * @attention When the obtained ap list fails,bss info must be cleared,otherwise it may cause memory leakage. + * + * @return + * - ESP_OK: succeed + * - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init + * - ESP_ERR_WIFI_NOT_STARTED: WiFi is not started by esp_wifi_start + * - ESP_ERR_WIFI_MODE: WiFi mode is wrong + * - ESP_ERR_INVALID_ARG: invalid argument + */ +esp_err_t esp_wifi_clear_ap_list(void); + + /** * @brief Get information of AP which the ESP32 station is associated with * @@ -598,18 +613,19 @@ esp_err_t esp_wifi_get_channel(uint8_t *primary, wifi_second_chan_t *second); * @attention 1. It is discouraged to call this API since this doesn't validate the per-country rules, * it's up to the user to fill in all fields according to local regulations. * Please use esp_wifi_set_country_code instead. - * @attention 2. The default country is CHINA {.cc="CN", .schan=1, .nchan=13, policy=WIFI_COUNTRY_POLICY_AUTO} - * @attention 3. When the country policy is WIFI_COUNTRY_POLICY_AUTO, the country info of the AP to which - * the station is connected is used. E.g. if the configured country info is {.cc="USA", .schan=1, .nchan=11} + * @attention 2. The default country is "01" (world safe mode) {.cc="01", .schan=1, .nchan=11, .policy=WIFI_COUNTRY_POLICY_AUTO}. + * @attention 3. The third octect of country code string is one of the following: ' ', 'O', 'I', 'X', otherwise it is considered as ' '. + * @attention 4. When the country policy is WIFI_COUNTRY_POLICY_AUTO, the country info of the AP to which + * the station is connected is used. E.g. if the configured country info is {.cc="US", .schan=1, .nchan=11} * and the country info of the AP to which the station is connected is {.cc="JP", .schan=1, .nchan=14} * then the country info that will be used is {.cc="JP", .schan=1, .nchan=14}. If the station disconnected * from the AP the country info is set back to the country info of the station automatically, * {.cc="US", .schan=1, .nchan=11} in the example. - * @attention 4. When the country policy is WIFI_COUNTRY_POLICY_MANUAL, then the configured country info is used always. - * @attention 5. When the country info is changed because of configuration or because the station connects to a different + * @attention 5. When the country policy is WIFI_COUNTRY_POLICY_MANUAL, then the configured country info is used always. + * @attention 6. When the country info is changed because of configuration or because the station connects to a different * external AP, the country IE in probe response/beacon of the soft-AP is also changed. - * @attention 6. The country configuration is stored into flash. - * @attention 7. When this API is called, the PHY init data will switch to the PHY init data type corresponding to the + * @attention 7. The country configuration is stored into flash. + * @attention 8. When this API is called, the PHY init data will switch to the PHY init data type corresponding to the * country info. * * @param country the configured country info @@ -617,7 +633,6 @@ esp_err_t esp_wifi_get_channel(uint8_t *primary, wifi_second_chan_t *second); * @return * - ESP_OK: succeed * - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init - * - ESP_ERR_WIFI_NOT_STARTED: WiFi is not started by esp_wifi_start * - ESP_ERR_INVALID_ARG: invalid argument */ esp_err_t esp_wifi_set_country(const wifi_country_t *country); @@ -1244,6 +1259,7 @@ esp_err_t esp_wifi_connectionless_module_set_wake_interval(uint16_t wake_interva * * @attention 7. When country code "01" (world safe mode) is set, SoftAP mode won't contain country IE. * @attention 8. The default country is "01" (world safe mode) and ieee80211d_enabled is TRUE. + * @attention 9. The third octect of country code string is one of the following: ' ', 'O', 'I', 'X', otherwise it is considered as ' '. * * @param country the configured country ISO code * @param ieee80211d_enabled 802.11d is enabled or not @@ -1251,7 +1267,6 @@ esp_err_t esp_wifi_connectionless_module_set_wake_interval(uint16_t wake_interva * @return * - ESP_OK: succeed * - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init - * - ESP_ERR_WIFI_NOT_STARTED: WiFi is not started by esp_wifi_start * - ESP_ERR_INVALID_ARG: invalid argument */ esp_err_t esp_wifi_set_country_code(const char *country, bool ieee80211d_enabled); diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib index fd23b3bc66..7bd8d12bd5 160000 --- a/components/esp_wifi/lib +++ b/components/esp_wifi/lib @@ -1 +1 @@ -Subproject commit fd23b3bc66102918dd0ce6492997f7cfdd6e86c0 +Subproject commit 7bd8d12bd5b49596b651db72b7b4e9dc609c5981 diff --git a/components/esp_wifi/test/test_wifi_init.c b/components/esp_wifi/test/test_wifi_init.c index 7ddc37e5ef..ed4d0d9029 100644 --- a/components/esp_wifi/test/test_wifi_init.c +++ b/components/esp_wifi/test/test_wifi_init.c @@ -279,4 +279,109 @@ TEST_CASE("Calling esp_wifi_deinit() without stop", "[wifi_init]") unity_utils_task_delete(th); } +static void wifi_country_code_task(void* arg) +{ + SemaphoreHandle_t *sema = (SemaphoreHandle_t *) arg; + wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT(); + + ESP_LOGI(TAG, EMPH_STR("nvs_flash_erase")); + nvs_flash_erase(); + ESP_LOGI(TAG, EMPH_STR("nvs_flash_init")); + esp_err_t r = nvs_flash_init(); + if (r == ESP_ERR_NVS_NO_FREE_PAGES || r == ESP_ERR_NVS_NEW_VERSION_FOUND) { + ESP_LOGI(TAG, EMPH_STR("no free pages or NFS version mismatch, erase..")); + TEST_ESP_OK(nvs_flash_erase()); + r = nvs_flash_init(); + } + TEST_ESP_OK(r); + //init tcpip stack + test_case_uses_tcpip(); + ESP_LOGI(TAG, EMPH_STR("event_init")); + TEST_ESP_OK(event_init()); + ESP_LOGI(TAG, EMPH_STR("esp_wifi_init")); + TEST_ESP_OK(esp_wifi_init(&cfg)); + + wifi_country_t country; + wifi_country_t country_01 = {.cc="01", .schan=1, .nchan=11, .policy=WIFI_COUNTRY_POLICY_MANUAL}; + wifi_country_t country_CN = {.cc="CN", .schan=1, .nchan=13, .policy=WIFI_COUNTRY_POLICY_MANUAL}; + ESP_LOGI(TAG, EMPH_STR("esp_wifi_get_country")); + TEST_ESP_OK(esp_wifi_get_country(&country)); + TEST_ASSERT(country.cc[0] == country_01.cc[0] && country.cc[1] == country_01.cc[1]); + + ESP_LOGI(TAG, EMPH_STR("esp_wifi_set_country")); + TEST_ESP_OK(esp_wifi_set_country(&country_CN)); + + ESP_LOGI(TAG, EMPH_STR("esp_wifi_get_country")); + TEST_ESP_OK(esp_wifi_get_country(&country)); + TEST_ASSERT(country.cc[0] == country_CN.cc[0] && country.cc[1] == country_CN.cc[1]); + + + ESP_LOGI(TAG, EMPH_STR("esp_wifi_deinit")); + TEST_ESP_OK(esp_wifi_deinit()); + ESP_LOGI(TAG, EMPH_STR("event_deinit")); + TEST_ESP_OK(event_deinit()); + ESP_LOGI(TAG, EMPH_STR("nvs_flash_deinit...")); + nvs_flash_deinit(); + + ESP_LOGI(TAG, EMPH_STR("nvs_flash_erase")); + nvs_flash_erase(); + ESP_LOGI(TAG, EMPH_STR("nvs_flash_init")); + r = nvs_flash_init(); + if (r == ESP_ERR_NVS_NO_FREE_PAGES || r == ESP_ERR_NVS_NEW_VERSION_FOUND) { + ESP_LOGI(TAG, EMPH_STR("no free pages or NFS version mismatch, erase..")); + TEST_ESP_OK(nvs_flash_erase()); + r = nvs_flash_init(); + } + TEST_ESP_OK(r); + //init tcpip stack + test_case_uses_tcpip(); + ESP_LOGI(TAG, EMPH_STR("event_init")); + TEST_ESP_OK(event_init()); + ESP_LOGI(TAG, EMPH_STR("esp_wifi_init")); + TEST_ESP_OK(esp_wifi_init(&cfg)); + + char country_code_string[3]; + char country_code_string_01[3] = "01"; + char country_code_string_CN[3] = "CN"; + ESP_LOGI(TAG, EMPH_STR("esp_wifi_get_country_code")); + TEST_ESP_OK(esp_wifi_get_country_code(&country_code_string[0])); + TEST_ASSERT(country_code_string[0] == country_code_string_01[0] && country_code_string[1] == country_code_string_01[1]); + + ESP_LOGI(TAG, EMPH_STR("esp_wifi_set_country_code")); + TEST_ESP_OK(esp_wifi_set_country_code(&country_code_string_CN[0], false)); + + ESP_LOGI(TAG, EMPH_STR("esp_wifi_get_country_code")); + TEST_ESP_OK(esp_wifi_get_country_code(&country_code_string[0])); + TEST_ASSERT(country_code_string[0] == country_code_string_CN[0] && country_code_string[1] == country_code_string_CN[1]); + + + ESP_LOGI(TAG, EMPH_STR("esp_wifi_deinit")); + TEST_ESP_OK(esp_wifi_deinit()); + ESP_LOGI(TAG, EMPH_STR("event_deinit")); + TEST_ESP_OK(event_deinit()); + ESP_LOGI(TAG, EMPH_STR("nvs_flash_deinit...")); + nvs_flash_deinit(); + + ESP_LOGI(TAG, "test passed..."); + xSemaphoreGive(*sema); + vTaskSuspend(NULL); +} + +TEST_CASE("wifi set country code", "[wifi_init]") +{ + TaskHandle_t th = NULL; + SemaphoreHandle_t sema = xSemaphoreCreateBinary(); + TEST_ASSERT_NOT_NULL(sema); + printf("Creating tasks\n"); +#ifndef CONFIG_FREERTOS_UNICORE + xTaskCreatePinnedToCore(wifi_country_code_task, "wifi_country_code_task", 2048*2, &sema, 3, &th, 0); +#else + xTaskCreate(wifi_country_code_task, "wifi_country_code_task", 2048*2, &sema, 3, &th); +#endif + TEST_ASSERT_NOT_NULL(th); + xSemaphoreTake(sema, portMAX_DELAY); + vSemaphoreDelete(sema); + sema = NULL; + unity_utils_task_delete(th); +} #endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) diff --git a/components/espcoredump/.build-test-rules.yml b/components/espcoredump/.build-test-rules.yml deleted file mode 100644 index 8f546a13dc..0000000000 --- a/components/espcoredump/.build-test-rules.yml +++ /dev/null @@ -1,7 +0,0 @@ -# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps - -components/espcoredump/test_apps: - disable: - - if: IDF_TARGET == "esp32c2" - temporary: true - reason: target esp32c2 is not supported yet diff --git a/components/espcoredump/CMakeLists.txt b/components/espcoredump/CMakeLists.txt index 7f936a1cb4..6be5b6a29a 100644 --- a/components/espcoredump/CMakeLists.txt +++ b/components/espcoredump/CMakeLists.txt @@ -24,4 +24,8 @@ idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${includes} PRIV_INCLUDE_DIRS ${priv_includes} LDFRAGMENTS linker.lf - PRIV_REQUIRES spi_flash app_update mbedtls esp_rom soc driver) + PRIV_REQUIRES spi_flash bootloader_support mbedtls esp_rom soc esp_system driver) + +if(CONFIG_ESP_COREDUMP_DATA_FORMAT_ELF) + target_link_libraries(${COMPONENT_LIB} PRIVATE idf::esp_app_format) +endif() diff --git a/components/espcoredump/espcoredump.py b/components/espcoredump/espcoredump.py index 0dc03dd603..b17f234b56 100755 --- a/components/espcoredump/espcoredump.py +++ b/components/espcoredump/espcoredump.py @@ -51,8 +51,8 @@ def main(): # type: () -> None # pass the extra_gdbinit_file if the build is reproducible kwargs['extra_gdbinit_file'] = get_prefix_map_gdbinit_path(kwargs['prog']) - del(kwargs['debug']) - del(kwargs['operation']) + del kwargs['debug'] + del kwargs['operation'] espcoredump = CoreDump(**kwargs) temp_core_files = None diff --git a/components/espcoredump/include_core_dump/esp_core_dump_common.h b/components/espcoredump/include_core_dump/esp_core_dump_common.h index 8915db228e..61772eb9d8 100644 --- a/components/espcoredump/include_core_dump/esp_core_dump_common.h +++ b/components/espcoredump/include_core_dump/esp_core_dump_common.h @@ -22,8 +22,10 @@ extern "C" { typedef enum { COREDUMP_MEMORY_DRAM, COREDUMP_MEMORY_IRAM, +#if SOC_RTC_MEM_SUPPORTED COREDUMP_MEMORY_RTC, COREDUMP_MEMORY_RTC_FAST, +#endif COREDUMP_MEMORY_MAX, COREDUMP_MEMORY_START = COREDUMP_MEMORY_DRAM } coredump_region_t; diff --git a/components/espcoredump/src/core_dump_common.c b/components/espcoredump/src/core_dump_common.c index 2ea3502701..24607d1b65 100644 --- a/components/espcoredump/src/core_dump_common.c +++ b/components/espcoredump/src/core_dump_common.c @@ -28,10 +28,12 @@ extern int _coredump_dram_start; extern int _coredump_dram_end; extern int _coredump_iram_start; extern int _coredump_iram_end; +#if SOC_RTC_MEM_SUPPORTED extern int _coredump_rtc_start; extern int _coredump_rtc_end; extern int _coredump_rtc_fast_start; extern int _coredump_rtc_fast_end; +#endif /** * @brief In the menconfig, it is possible to specify a specific stack size for @@ -226,8 +228,10 @@ uint32_t esp_core_dump_get_user_ram_segments(void) // count number of memory segments to insert into ELF structure total_sz += COREDUMP_GET_MEMORY_SIZE(&_coredump_dram_end, &_coredump_dram_start) > 0 ? 1 : 0; +#if SOC_RTC_MEM_SUPPORTED total_sz += COREDUMP_GET_MEMORY_SIZE(&_coredump_rtc_end, &_coredump_rtc_start) > 0 ? 1 : 0; total_sz += COREDUMP_GET_MEMORY_SIZE(&_coredump_rtc_fast_end, &_coredump_rtc_fast_start) > 0 ? 1 : 0; +#endif total_sz += COREDUMP_GET_MEMORY_SIZE(&_coredump_iram_end, &_coredump_iram_start) > 0 ? 1 : 0; return total_sz; @@ -238,8 +242,10 @@ uint32_t esp_core_dump_get_user_ram_size(void) uint32_t total_sz = 0; total_sz += COREDUMP_GET_MEMORY_SIZE(&_coredump_dram_end, &_coredump_dram_start); +#if SOC_RTC_MEM_SUPPORTED total_sz += COREDUMP_GET_MEMORY_SIZE(&_coredump_rtc_end, &_coredump_rtc_start); total_sz += COREDUMP_GET_MEMORY_SIZE(&_coredump_rtc_fast_end, &_coredump_rtc_fast_start); +#endif total_sz += COREDUMP_GET_MEMORY_SIZE(&_coredump_iram_end, &_coredump_iram_start); return total_sz; @@ -262,6 +268,7 @@ int esp_core_dump_get_user_ram_info(coredump_region_t region, uint32_t *start) total_sz = (uint8_t *)&_coredump_iram_end - (uint8_t *)&_coredump_iram_start; break; +#if SOC_RTC_MEM_SUPPORTED case COREDUMP_MEMORY_RTC: *start = (uint32_t)&_coredump_rtc_start; total_sz = (uint8_t *)&_coredump_rtc_end - (uint8_t *)&_coredump_rtc_start; @@ -271,6 +278,7 @@ int esp_core_dump_get_user_ram_info(coredump_region_t region, uint32_t *start) *start = (uint32_t)&_coredump_rtc_fast_start; total_sz = (uint8_t *)&_coredump_rtc_fast_end - (uint8_t *)&_coredump_rtc_fast_start; break; +#endif default: break; @@ -286,6 +294,7 @@ inline bool esp_core_dump_tcb_addr_is_sane(uint32_t addr) inline bool esp_core_dump_in_isr_context(void) { +#if CONFIG_ESP_TASK_WDT_EN /* This function will be used to check whether a panic occurred in an ISR. * In that case, the execution frame must be switch to the interrupt stack. * However, in case where the task watchdog ISR calls the panic handler, @@ -295,6 +304,9 @@ inline bool esp_core_dump_in_isr_context(void) * TODO: IDF-5694. */ extern bool g_twdt_isr; return xPortInterruptedFromISRContext() && !g_twdt_isr; +#else // CONFIG_ESP_TASK_WDT_EN + return xPortInterruptedFromISRContext(); +#endif // CONFIG_ESP_TASK_WDT_EN } inline core_dump_task_handle_t esp_core_dump_get_current_task_handle() diff --git a/components/espcoredump/src/core_dump_elf.c b/components/espcoredump/src/core_dump_elf.c index 2cd0b53f30..11bde327c7 100644 --- a/components/espcoredump/src/core_dump_elf.c +++ b/components/espcoredump/src/core_dump_elf.c @@ -6,7 +6,6 @@ #include #include "esp_attr.h" #include "esp_partition.h" -#include "esp_ota_ops.h" #include "spi_flash_mmap.h" #include "esp_flash_encrypt.h" #include "sdkconfig.h" @@ -16,6 +15,10 @@ #include "esp_core_dump_port_impl.h" #include "esp_core_dump_common.h" +#ifdef CONFIG_ESP_COREDUMP_DATA_FORMAT_ELF +#include "esp_app_desc.h" +#endif + #define ELF_CLASS ELFCLASS32 #include "elf.h" // for ELF file types @@ -496,7 +499,7 @@ static int elf_write_core_dump_info(core_dump_elf_t *self) ESP_COREDUMP_LOG_PROCESS("================ Processing coredump info ================"); int data_len = (int)sizeof(self->elf_version_info.app_elf_sha256); - data_len = esp_ota_get_app_elf_sha256((char*)self->elf_version_info.app_elf_sha256, (size_t)data_len); + data_len = esp_app_get_elf_sha256((char*)self->elf_version_info.app_elf_sha256, (size_t)data_len); ESP_COREDUMP_LOG_PROCESS("Application SHA256='%s', length=%d.", self->elf_version_info.app_elf_sha256, data_len); self->elf_version_info.version = esp_core_dump_elf_version(); diff --git a/components/espcoredump/test/esp32c2/coredump.b64 b/components/espcoredump/test/esp32c2/coredump.b64 new file mode 100644 index 0000000000..524d741774 --- /dev/null +++ b/components/espcoredump/test/esp32c2/coredump.b64 @@ -0,0 +1,124 @@ +tBEAAAABBQAAAAAAAAAAAAAAAAA= +f0VMRgEBAQAAAAAAAAAAAAQA8wABAAAAAAAAADQAAAAAAAAAAAAAADQAIAAMACgA +AAAAAA== +BAAAALQBAAAAAAAAAAAAAGAEAABgBAAABgAAAAAAAAA= +AQAAABQGAACw6M0/sOjNP1QBAABUAQAABgAAAAAAAAA= +AQAAAGgHAABw580/cOfNPzABAAAwAQAABgAAAAAAAAA= +AQAAAJgIAAD83s0//N7NP1QBAABUAQAABgAAAAAAAAA= +AQAAAOwJAAAg3s0/IN7NP9AAAADQAAAABgAAAAAAAAA= +AQAAALwKAABo68o/aOvKP1QBAABUAQAABgAAAAAAAAA= +AQAAABAMAACg6so/oOrKP8AAAADAAAAABgAAAAAAAAA= +AQAAANAMAAAM8s0/DPLNP1QBAABUAQAABgAAAAAAAAA= +AQAAACQOAAAw8c0/MPHNP9AAAADQAAAABgAAAAAAAAA= +AQAAAPQOAABw1Mo/cNTKP1QBAABUAQAABgAAAAAAAAA= +AQAAAEgQAACQ08o/kNPKP9AAAADQAAAABgAAAAAAAAA= +BAAAABgRAAAAAAAAAAAAAIQAAACEAAAABgAAAAAAAAA= +CAAAAMwAAAABAAAA +Q09SRQAAAAA= +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAsOjNPwAAAAAAAAAAAAAAAAAAAAAAAAAA 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+AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AQAAPw== +1mI4QABjOEAQ1Mo/EJLKP2yxyj8AAAAAAAAAAAAAAAAAAAAA/////wEAAAABAAAA +/////wQAAAAAsMo/ACAMYAAAAAAAAAAAAQAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABAAAA/////wAAAADyXThA +AAAAAAAAAAAAAAAAZDIAQgAAAAAAAAAAAAAAAJhiOEAAAAAAAAAAAAAAAAAAAAAA +AAAAAKWlpaWlpaWlpaWlpQ== +FAAAAEgAAABKIAAA +RVNQX0NPUkVfRFVNUF9JTkZPAAA= +AAEFADUzMjk1N2QzOThiYmJkMWMAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA +DAAAAAQAAAClAgAA +RVhUUkFfSU5GTwAA +sOjNPw== +TI3Lgg== diff --git a/components/espcoredump/test/esp32c2/expected_output b/components/espcoredump/test/esp32c2/expected_output new file mode 100644 index 0000000000..ed78f3f1a3 --- /dev/null +++ b/components/espcoredump/test/esp32c2/expected_output @@ -0,0 +1,314 @@ +espcoredump.py v1.4 +=============================================================== +==================== ESP32 CORE DUMP START ==================== + +Crashed task handle: 0x3fcde8b0, name: 'unaligned_ptr_t', GDB name: 'process 1070459056' + +================== CURRENT THREAD REGISTERS =================== +ra 0x42006d0c 0x42006d0c +sp 0x3fcde810 0x3fcde810 +gp 0x3fca9210 0x3fca9210 <__c.48> +tp 0x3fcdc5ac 0x3fcdc5ac +t0 0x4005e3c8 1074127816 +t1 0x0 0 +t2 0x0 0 +fp 0x0 0x0 +s1 0x0 0 +a0 0x20 32 +a1 0x3fcde72c 1070458668 +a2 0x0 0 +a3 0x7 7 +a4 0xffffffad -83 +a5 0x5 5 +a6 0x42004030 1107312688 +a7 0x0 0 +s2 0x0 0 +s3 0x0 0 +s4 0x0 0 +s5 0x0 0 +s6 0x0 0 +s7 0x0 0 +s8 0x0 0 +s9 0x0 0 +s10 0x0 0 +s11 0x0 0 +t3 0x0 0 +t4 0x0 0 +t5 0x0 0 +t6 0x0 0 +pc 0x42006d12 0x42006d12 + +==================== CURRENT THREAD STACK ===================== +#0 0x42006d12 in recur_func () at /builds/espressif/esp-idf/components/espcoredump/test_apps/main/test_core_dump.c:75 +#1 0x42006cec in recur_func () at /builds/espressif/esp-idf/components/espcoredump/test_apps/main/test_core_dump.c:68 +#2 0x42006cec in recur_func () at /builds/espressif/esp-idf/components/espcoredump/test_apps/main/test_core_dump.c:68 +#3 0x42006d54 in unaligned_ptr_task (pvParameter=) at /builds/espressif/esp-idf/components/espcoredump/test_apps/main/test_core_dump.c:85 +#4 0x40386298 in prvTaskExitError () at /builds/espressif/esp-idf/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c:132 +Backtrace stopped: frame did not save the PC + +======================== THREADS INFO ========================= + Id Target Id Frame +* 1 process 1070459056 0x42006d12 in recur_func () at /builds/espressif/esp-idf/components/espcoredump/test_apps/main/test_core_dump.c:75 + 2 process 1070456572 0x403830ea in esp_crosscore_int_send_yield (core_id=core_id@entry=0) at /builds/espressif/esp-idf/components/esp_system/crosscore_int.c:158 + 3 process 1070263144 0x403831b2 in esp_cpu_wait_for_intr () at /builds/espressif/esp-idf/components/esp_hw_support/cpu.c:110 + 4 process 1070461452 0x403830ea in esp_crosscore_int_send_yield (core_id=core_id@entry=0) at /builds/espressif/esp-idf/components/esp_system/crosscore_int.c:158 + 5 process 1070257264 0x403862d6 in vPortClearInterruptMask (mask=1) at /builds/espressif/esp-idf/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c:305 + +==================== THREAD 1 (TCB: 0x3fcde8b0, name: 'unaligned_ptr_t') ===================== +#0 0x42006d12 in recur_func () at /builds/espressif/esp-idf/components/espcoredump/test_apps/main/test_core_dump.c:75 +#1 0x42006cec in recur_func () at /builds/espressif/esp-idf/components/espcoredump/test_apps/main/test_core_dump.c:68 +#2 0x42006cec in recur_func () at /builds/espressif/esp-idf/components/espcoredump/test_apps/main/test_core_dump.c:68 +#3 0x42006d54 in unaligned_ptr_task (pvParameter=) at /builds/espressif/esp-idf/components/espcoredump/test_apps/main/test_core_dump.c:85 +#4 0x40386298 in prvTaskExitError () at /builds/espressif/esp-idf/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c:132 +Backtrace stopped: frame did not save the PC + +==================== THREAD 2 (TCB: 0x3fcddefc, name: 'bad_ptr_task') ===================== +#0 0x403830ea in esp_crosscore_int_send_yield (core_id=core_id@entry=0) at /builds/espressif/esp-idf/components/esp_system/crosscore_int.c:158 +#1 0x40386338 in vPortYield () at /builds/espressif/esp-idf/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c:313 +#2 0x40385b50 in vTaskDelay (xTicksToDelay=xTicksToDelay@entry=100) at /builds/espressif/esp-idf/components/freertos/FreeRTOS-Kernel/tasks.c:1661 +#3 0x42006ca0 in bad_ptr_task (pvParameter=) at /builds/espressif/esp-idf/components/espcoredump/test_apps/main/test_core_dump.c:48 +#4 0x40386298 in prvTaskExitError () at /builds/espressif/esp-idf/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c:132 +Backtrace stopped: frame did not save the PC + +==================== THREAD 3 (TCB: 0x3fcaeb68, name: 'IDLE') ===================== +#0 0x403831b2 in esp_cpu_wait_for_intr () at /builds/espressif/esp-idf/components/esp_hw_support/cpu.c:110 +#1 0x420086cc in esp_vApplicationIdleHook () at /builds/espressif/esp-idf/components/esp_system/freertos_hooks.c:59 +#2 0x403851fe in prvIdleTask (pvParameters=) at /builds/espressif/esp-idf/components/freertos/FreeRTOS-Kernel/tasks.c:4243 +#3 0x40386298 in prvTaskExitError () at /builds/espressif/esp-idf/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c:132 +Backtrace stopped: frame did not save the PC + +==================== THREAD 4 (TCB: 0x3fcdf20c, name: 'failed_assert_t') ===================== +#0 0x403830ea in esp_crosscore_int_send_yield (core_id=core_id@entry=0) at /builds/espressif/esp-idf/components/esp_system/crosscore_int.c:158 +#1 0x40386338 in vPortYield () at /builds/espressif/esp-idf/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c:313 +#2 0x40385b50 in vTaskDelay (xTicksToDelay=xTicksToDelay@entry=100) at /builds/espressif/esp-idf/components/freertos/FreeRTOS-Kernel/tasks.c:1661 +#3 0x42006b7a in failed_assert_task (pvParameter=) at /builds/espressif/esp-idf/components/espcoredump/test_apps/main/test_core_dump.c:94 +#4 0x40386298 in prvTaskExitError () at /builds/espressif/esp-idf/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c:132 +Backtrace stopped: frame did not save the PC + +==================== THREAD 5 (TCB: 0x3fcad470, name: 'esp_timer') ===================== +#0 0x403862d6 in vPortClearInterruptMask (mask=1) at /builds/espressif/esp-idf/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c:305 +#1 0x40386300 in vPortExitCritical () at /builds/espressif/esp-idf/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c:256 +#2 0x40385df2 in ulTaskGenericNotifyTake (uxIndexToWait=uxIndexToWait@entry=0, xClearCountOnExit=xClearCountOnExit@entry=1, xTicksToWait=xTicksToWait@entry=4294967295) at /builds/espressif/esp-idf/components/freertos/FreeRTOS-Kernel/tasks.c:5651 +#3 0x42003264 in timer_task (arg=) at /builds/espressif/esp-idf/components/esp_timer/src/esp_timer.c:430 +#4 0x40386298 in prvTaskExitError () at /builds/espressif/esp-idf/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c:132 +Backtrace stopped: frame did not save the PC + + +======================= ALL MEMORY REGIONS ======================== +Name Address Size Attrs +.iram0.text 0x40380000 0x8a0c R XA +.dram0.data 0x3fca8a10 0x1ab0 RW A +.noinit 0x3fcaa4c0 0x0 RW +.flash.text 0x42000020 0xe39e R XA +.flash.appdesc 0x3c010020 0x100 R A +.flash.rodata 0x3c010120 0x22f8 RW A +.eh_frame 0x3c012418 0x7e8 R A +.flash.rodata_noload 0x3c012c00 0x0 RW +.iram0.text_end 0x40388a0c 0x0 RW +.iram0.bss 0x40388a10 0x0 RW +.coredump.tasks.data 0x3fcde8b0 0x154 RW +.coredump.tasks.data 0x3fcde770 0x130 RW +.coredump.tasks.data 0x3fcddefc 0x154 RW +.coredump.tasks.data 0x3fcdde20 0xd0 RW +.coredump.tasks.data 0x3fcaeb68 0x154 RW +.coredump.tasks.data 0x3fcaeaa0 0xc0 RW +.coredump.tasks.data 0x3fcdf20c 0x154 RW +.coredump.tasks.data 0x3fcdf130 0xd0 RW +.coredump.tasks.data 0x3fcad470 0x154 RW +.coredump.tasks.data 0x3fcad390 0xd0 RW + +====================== CORE DUMP MEMORY CONTENTS ======================== +.coredump.tasks.data 0x3fcde8b0 0x154 RW +0x3fcde8b0: 0x3fcde7d0 0x00000064 0x3fcaaf10 0x3fcaaf10 +0x3fcde8c0: 0x3fcde8b0 0x3fcaaf08 0x00000012 0xb1ca9edd +0x3fcde8d0: 0xa9cc4611 0x3fcde8b0 0x00000000 0x00000007 +0x3fcde8e0: 0x3fcde0ac 0x6c616e75 0x656e6769 0x74705f64 +0x3fcde8f0: 0x00745f72 0x00000000 0x3fcde8a0 0x00000007 +0x3fcde900: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcde910: 0x3fcac134 0x3fcac19c 0x3fcac204 0x00000000 +0x3fcde920: 0x00000000 0x00000001 0x00000000 0x00000000 +0x3fcde930: 0x00000000 0x4200c450 0x00000000 0x00000000 +0x3fcde940: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcde950: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcde960: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcde970: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcde980: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcde990: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcde9a0: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcde9b0: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcde9c0: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcde9d0: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcde9e0: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcde9f0: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcdea00: 0x3f000000 +.coredump.tasks.data 0x3fcde770 0x130 RW +0x3fcde770: 0x42006d12 0x42006d0c 0x3fcde810 0x3fca9210 +0x3fcde780: 0x3fcdc5ac 0x4005e3c8 0x00000000 0x00000000 +0x3fcde790: 0x00000000 0x00000000 0x00000020 0x3fcde72c +0x3fcde7a0: 0x00000000 0x00000007 0xffffffad 0x00000005 +0x3fcde7b0: 0x42004030 0x00000000 0x00000000 0x00000000 +0x3fcde7c0: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcde7d0: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcde7e0: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcde7f0: 0x00001881 0x40380001 0x00000007 0x00000005 +0x3fcde800: 0x00000000 0x00000002 0x42004030 0x00000000 +0x3fcde810: 0x00000000 0x00000000 0x00000000 0x00000003 +0x3fcde820: 0x00000000 0x0000000a 0x3fcac19c 0x42006cec +0x3fcde830: 0x00000000 0x00000000 0x00000000 0x00000003 +0x3fcde840: 0x00000000 0x3fcde850 0x00000002 0x42006cec +0x3fcde850: 0x3c01137c 0x0000001e 0x3ff4d760 0x00000003 +0x3fcde860: 0x00000000 0x00000000 0x00000000 0x42006d54 +0x3fcde870: 0x00000000 0x00000000 0x00000000 0x40386298 +0x3fcde880: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcde890: 0x00000000 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +.coredump.tasks.data 0x3fcddefc 0x154 RW +0x3fcddefc: 0x3fcdde20 0x00000064 0x3fcaaee8 0x3fcaaee8 +0x3fcddf0c: 0x3fcddefc 0x3fcaaee0 0x00000014 0x531908a0 +0x3fcddf1c: 0x27d6ee0c 0x3fcddefc 0x00000000 0x00000005 +0x3fcddf2c: 0x3fcdd6f8 0x5f646162 0x5f727470 0x6b736174 +0x3fcddf3c: 0x00976d00 0x00000000 0x3fcddef0 0x00000005 +0x3fcddf4c: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcddf5c: 0x3fcac134 0x3fcac19c 0x3fcac204 0x00000000 +0x3fcddf6c: 0x00000000 0x00000001 0x00000000 0x00000000 +0x3fcddf7c: 0x00000000 0x4200c450 0x00000000 0x00000000 +0x3fcddf8c: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcddf9c: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcddfac: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcddfbc: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcddfcc: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcddfdc: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcddfec: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcddffc: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcde00c: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcde01c: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcde02c: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcde03c: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcde04c: 0x3f000000 +.coredump.tasks.data 0x3fcdde20 0xd0 RW +0x3fcdde20: 0x403830ea 0x40386338 0x3fcddea0 0x3fca9210 +0x3fcdde30: 0x3fcdbbfc 0x4005e3c8 0xffffffe0 0x00000000 +0x3fcdde40: 0x00000064 0x00000000 0x00000001 0x00000001 +0x3fcdde50: 0x00000064 0x00000004 0x00000001 0x600c0000 +0x3fcdde60: 0x42004030 0x00000000 0x00000000 0x00000000 +0x3fcdde70: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcdde80: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcdde90: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcddea0: 0x00000000 0x00000000 0x00000064 0x40385b50 +0x3fcddeb0: 0x00000000 0x00000000 0x00000000 0x42006ca0 +0x3fcddec0: 0x00000000 0x00000000 0x00000000 0x40386298 +0x3fcdded0: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcddee0: 0x00000000 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +.coredump.tasks.data 0x3fcaeb68 0x154 RW +0x3fcaeb68: 0x3fcaeaa0 0x3fcab8c4 0x3fcaae84 0x3fcaae84 +0x3fcaeb78: 0x3fcaeb68 0x3fcaae7c 0x00000019 0x23fb2403 +0x3fcaeb88: 0x8cc7236f 0x3fcaeb68 0x00000000 0x00000000 +0x3fcaeb98: 0x3fcae564 0x454c4449 0xab327d00 0xa559a356 +0x3fcaeba8: 0x00ee44c4 0x00000000 0x3fcaeb60 0x00000000 +0x3fcaebb8: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcaebc8: 0x3fcac134 0x3fcac19c 0x3fcac204 0x00000000 +0x3fcaebd8: 0x00000000 0x00000001 0x00000000 0x00000000 +0x3fcaebe8: 0x00000000 0x4200c450 0x00000000 0x00000000 +0x3fcaebf8: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcaec08: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcaec18: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcaec28: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcaec38: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcaec48: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcaec58: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcaec68: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcaec78: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcaec88: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcaec98: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcaeca8: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcaecb8: 0x3f000200 +.coredump.tasks.data 0x3fcaeaa0 0xc0 RW +0x3fcaeaa0: 0x403831b2 0x420086cc 0x3fcaeb20 0x3fca9210 +0x3fcaeab0: 0x3fcac86c 0x400586f0 0xffffffe0 0x00000000 +0x3fcaeac0: 0x00000008 0x00000001 0x00000001 0x00000000 +0x3fcaead0: 0xfff00000 0x60023000 0x0000001c 0x00000000 +0x3fcaeae0: 0x00000001 0x00000000 0x00000000 0x00000000 +0x3fcaeaf0: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcaeb00: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcaeb10: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcaeb20: 0x00000000 0x00000000 0x00000000 0x403851fe +0x3fcaeb30: 0x00000000 0x00000000 0x00000000 0x40386298 +0x3fcaeb40: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcaeb50: 0x00000000 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +.coredump.tasks.data 0x3fcdf20c 0x154 RW +0x3fcdf20c: 0x3fcdf130 0x000000c8 0x3fcab078 0x3fcab078 +0x3fcdf21c: 0x3fcdf20c 0x3fcab070 0x0000000f 0x00000000 +0x3fcdf22c: 0x00000000 0x3fcdf20c 0x00000000 0x0000000a +0x3fcdf23c: 0x3fcdea08 0x6c696166 0x615f6465 0x72657373 +0x3fcdf24c: 0x00745f74 0x00000000 0x3fcdf200 0x0000000a +0x3fcdf25c: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcdf26c: 0x3fcac134 0x3fcac19c 0x3fcac204 0x00000000 +0x3fcdf27c: 0x00000000 0x00000001 0x00000000 0x00000000 +0x3fcdf28c: 0x00000000 0x4200c450 0x00000000 0x00000000 +0x3fcdf29c: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcdf2ac: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcdf2bc: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcdf2cc: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcdf2dc: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcdf2ec: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcdf2fc: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcdf30c: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcdf31c: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcdf32c: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcdf33c: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcdf34c: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcdf35c: 0x3f000000 +.coredump.tasks.data 0x3fcdf130 0xd0 RW +0x3fcdf130: 0x403830ea 0x40386338 0x3fcdf1b0 0x3fca9210 +0x3fcdf140: 0x3fcdcf0c 0x4005e3c8 0x00000000 0x00000000 +0x3fcdf150: 0x00000064 0x00000000 0x00000001 0x00000001 +0x3fcdf160: 0x000000c8 0x00000004 0x00000001 0x600c0000 +0x3fcdf170: 0x42004030 0x00000000 0x00000000 0x00000000 +0x3fcdf180: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcdf190: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcdf1a0: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcdf1b0: 0x00000000 0x00000000 0x00000064 0x40385b50 +0x3fcdf1c0: 0x00000000 0x00000000 0x00000000 0x42006b7a +0x3fcdf1d0: 0x00000000 0x00000000 0x00000000 0x40386298 +0x3fcdf1e0: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcdf1f0: 0x00000000 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 +.coredump.tasks.data 0x3fcad470 0x154 RW +0x3fcad470: 0x3fcad390 0x3fcab8c4 0x3fcab0b4 0x3fcab0b4 +0x3fcad480: 0x3fcad470 0x3fcab0ac 0x00000003 0x76f29c86 +0x3fcad490: 0xc53fc37b 0x3fcad470 0x00000000 0x00000016 +0x3fcad4a0: 0x3fcac66c 0x5f707365 0x656d6974 0x7bcd0072 +0x3fcad4b0: 0x00267a48 0x00000000 0x3fcad460 0x00000016 +0x3fcad4c0: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcad4d0: 0x3fcac134 0x3fcac19c 0x3fcac204 0x00000000 +0x3fcad4e0: 0x00000000 0x00000001 0x00000000 0x00000000 +0x3fcad4f0: 0x00000000 0x4200c450 0x00000000 0x00000000 +0x3fcad500: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcad510: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcad520: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcad530: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcad540: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcad550: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcad560: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcad570: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcad580: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcad590: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcad5a0: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcad5b0: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcad5c0: 0x3f000001 +.coredump.tasks.data 0x3fcad390 0xd0 RW +0x3fcad390: 0x403862d6 0x40386300 0x3fcad410 0x3fca9210 +0x3fcad3a0: 0x3fcab16c 0x00000000 0x00000000 0x00000000 +0x3fcad3b0: 0x00000000 0xffffffff 0x00000001 0x00000001 +0x3fcad3c0: 0xffffffff 0x00000004 0x3fcab000 0x600c2000 +0x3fcad3d0: 0x00000000 0x00000000 0x00000001 0x00000000 +0x3fcad3e0: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcad3f0: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcad400: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcad410: 0x00000001 0xffffffff 0x00000000 0x40385df2 +0x3fcad420: 0x00000000 0x00000000 0x00000000 0x42003264 +0x3fcad430: 0x00000000 0x00000000 0x00000000 0x40386298 +0x3fcad440: 0x00000000 0x00000000 0x00000000 0x00000000 +0x3fcad450: 0x00000000 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 + +===================== ESP32 CORE DUMP END ===================== +=============================================================== +Done! diff --git a/components/espcoredump/test/test_espcoredump.py b/components/espcoredump/test/test_espcoredump.py index 819586bc85..9b5f074a35 100755 --- a/components/espcoredump/test/test_espcoredump.py +++ b/components/espcoredump/test/test_espcoredump.py @@ -14,7 +14,7 @@ except ImportError: raise ModuleNotFoundError('No module named "esp_coredump" please install esp_coredump by running ' '"python -m pip install esp-coredump"') -SUPPORTED_TARGET = ['esp32', 'esp32s2', 'esp32c3', 'esp32s3'] +SUPPORTED_TARGET = ['esp32', 'esp32s2', 'esp32c3', 'esp32s3', 'esp32c2'] class TestESPCoreDumpElfFile(unittest.TestCase): diff --git a/components/espcoredump/test/test_espcoredump.sh b/components/espcoredump/test/test_espcoredump.sh index fa3045a2a1..0b3d11a9d8 100755 --- a/components/espcoredump/test/test_espcoredump.sh +++ b/components/espcoredump/test/test_espcoredump.sh @@ -13,7 +13,7 @@ fi COREDUMP_VERSION="espcoredump.py v$(python -c "import pkg_resources; print(pkg_resources.get_distribution('esp-coredump').version)")" COREDUMP_VERSION_REGEX="espcoredump.py v([0-9])+.([0-9a-z-])+(.[0-9a-z-])?" -SUPPORTED_TARGETS=("esp32" "esp32s2" "esp32c3" "esp32s3" ) +SUPPORTED_TARGETS=("esp32" "esp32s2" "esp32c3" "esp32s3" "esp32c2") res=0 for chip in "${SUPPORTED_TARGETS[@]}"; do { diff --git a/components/espcoredump/test/test_sections.c b/components/espcoredump/test/test_sections.c index 175369e1b6..0ec31b9dba 100644 --- a/components/espcoredump/test/test_sections.c +++ b/components/espcoredump/test/test_sections.c @@ -8,24 +8,25 @@ #include "esp_attr.h" #include "test_utils.h" -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) -//IDF-5050 - /* Global variables that should be part of the coredump */ COREDUMP_IRAM_DATA_ATTR uint32_t var_iram = 0x42; COREDUMP_DRAM_ATTR uint32_t var_dram = 0x43; +#if SOC_RTC_MEM_SUPPORTED COREDUMP_RTC_DATA_ATTR uint32_t var_rtc = 0x44; COREDUMP_RTC_FAST_ATTR uint32_t var_rtcfast = 0x45; +#endif // SOC_RTC_MEM_SUPPORTED /* Memory regions to dump, defined at compile time. */ extern int _coredump_dram_start; extern int _coredump_dram_end; extern int _coredump_iram_start; extern int _coredump_iram_end; +#if SOC_RTC_MEM_SUPPORTED extern int _coredump_rtc_start; extern int _coredump_rtc_end; extern int _coredump_rtc_fast_start; extern int _coredump_rtc_fast_end; +#endif // SOC_RTC_MEM_SUPPORTED static inline bool is_addr_in_region(void* addr, uint8_t* region, int region_size) { @@ -51,6 +52,7 @@ TEST_CASE("test variables presence in core dump sections", "[espcoredump]") TEST_ASSERT(section_size > 0); TEST_ASSERT(is_addr_in_region(&var_iram, (uint8_t*) section_start, section_size)); #endif +#if SOC_RTC_MEM_SUPPORTED /* Check RTC coredump section */ section_start = (uint32_t)&_coredump_rtc_start; section_size = (uint8_t *)&_coredump_rtc_end - (uint8_t *)&_coredump_rtc_start; @@ -61,6 +63,5 @@ TEST_CASE("test variables presence in core dump sections", "[espcoredump]") section_size = (uint8_t *)&_coredump_rtc_fast_end - (uint8_t *)&_coredump_rtc_fast_start; TEST_ASSERT(section_size > 0); TEST_ASSERT(is_addr_in_region(&var_rtcfast, (uint8_t*) section_start, section_size)); +#endif // SOC_RTC_MEM_SUPPORTED } - -#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) diff --git a/components/espcoredump/test_apps/README.md b/components/espcoredump/test_apps/README.md index 2159d40a70..f0bf02b571 100644 --- a/components/espcoredump/test_apps/README.md +++ b/components/espcoredump/test_apps/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | # ESP Core Dump Tests diff --git a/components/espcoredump/test_apps/build_espcoredump.sh b/components/espcoredump/test_apps/build_espcoredump.sh index 9f7ac84d3f..4964aa2e6c 100755 --- a/components/espcoredump/test_apps/build_espcoredump.sh +++ b/components/espcoredump/test_apps/build_espcoredump.sh @@ -11,7 +11,7 @@ else output_dir=$1 fi -SUPPORTED_TARGETS=("esp32" "esp32s2" "esp32c3" "esp32s3") +SUPPORTED_TARGETS=("esp32" "esp32s2" "esp32c3" "esp32s3" "esp32c2") for chip in "${SUPPORTED_TARGETS[@]}"; do { echo "--------------------------" diff --git a/components/esptool_py/project_include.cmake b/components/esptool_py/project_include.cmake index 50c6b74190..61bb1954f7 100644 --- a/components/esptool_py/project_include.cmake +++ b/components/esptool_py/project_include.cmake @@ -46,7 +46,10 @@ set(MMU_PAGE_SIZE ${CONFIG_MMU_PAGE_MODE}) if(NOT BOOTLOADER_BUILD) list(APPEND esptool_elf2image_args --elf-sha256-offset 0xb0) - if(CONFIG_IDF_TARGET_ESP32C2) + # For chips that support configurable MMU page size feature + # If page size is configured to values other than the default "64KB" in menuconfig, + # then we need to pass the actual size to flash-mmu-page-size arg + if(NOT MMU_PAGE_SIZE STREQUAL "64KB") list(APPEND esptool_elf2image_args --flash-mmu-page-size ${MMU_PAGE_SIZE}) endif() endif() @@ -140,6 +143,8 @@ endif() if(NOT BOOTLOADER_BUILD AND CONFIG_SECURE_SIGNED_APPS) if(CONFIG_SECURE_BOOT_BUILD_SIGNED_BINARIES) # for locally signed secure boot image, add a signing step to get from unsigned app to signed app + get_filename_component(secure_boot_signing_key "${CONFIG_SECURE_BOOT_SIGNING_KEY}" + ABSOLUTE BASE_DIR "${project_dir}") add_custom_command(OUTPUT "${build_dir}/.signed_bin_timestamp" COMMAND ${ESPSECUREPY} sign_data --version ${secure_boot_version} --keyfile ${secure_boot_signing_key} -o "${build_dir}/${PROJECT_BIN}" "${build_dir}/${unsigned_project_binary}" @@ -323,43 +328,6 @@ function(esptool_py_flash_target_image target_name image_name offset image) endif() endfunction() -# Use this function to generate a ternary expression that will be evaluated. -# - retexpr is the expression returned by the function -# - condition is the expression evaluated to a boolean -# - condtrue is the expression to evaluate if condition is true -# - condfalse is the expression to evaluate if condition is false -# This function can be summarized as: -# retexpr = condition ? condtrue : condfalse -function(if_expr_generator retexpr condition condtrue condfalse) - # CMake version 3.8 and above provide a ternary operator for expression - # generator. For version under, we must simulate this behaviour - if(${CMAKE_VERSION} VERSION_LESS "3.8.0") - - # If condtrue is not empty, then we have to do something in case the - # condition is true. Generate the expression that will be used in that - # case - if(condtrue) - set(iftrue "$<${condition}:${condtrue}>") - endif() - - # Same for condfalse. If it is empty, it is useless to create an - # expression that will be evaluated later - if(condfalse) - set(iffalse "$<$:${condfalse}>") - endif() - - # Concatenate the previously generated expressions. If one of them was - # not initialized (because of empty condtrue/condfalse) it will be - # replaced by an empty string - set(${retexpr} "${iftrue}${iffalse}" PARENT_SCOPE) - - else() - # CMake 3.8 and above implement what we want, making the expression - # simpler - set(${retexpr} "$" PARENT_SCOPE) - endif() -endfunction() - function(esptool_py_flash_target target_name main_args sub_args) set(single_value OFFSET IMAGE) # template file to use to be able to @@ -442,8 +410,7 @@ $,\n>") encrypted-${target_name},NON_ENCRYPTED_IMAGES>>") # Prepare esptool arguments (--encrypt or --encrypt-files) - if_expr_generator(if_non_enc_expr ${has_non_encrypted_images} - "" "--encrypt") + set(if_non_enc_expr "$") set_target_properties(encrypted-${target_name} PROPERTIES SUB_ARGS "${sub_args}; ${if_non_enc_expr}") @@ -455,8 +422,7 @@ encrypted-${target_name},NON_ENCRYPTED_IMAGES>,\n>") # Put both lists together, use --encrypted-files if we do also have # plain images to flash - if_expr_generator(if_enc_expr ${has_non_encrypted_images} - "--encrypt-files\n" "") + set(if_enc_expr "$") set(flash_args_content "$, >\ ${non_encrypted_files}\n\ diff --git a/components/fatfs/.build-test-rules.yml b/components/fatfs/.build-test-rules.yml new file mode 100644 index 0000000000..c879f1132b --- /dev/null +++ b/components/fatfs/.build-test-rules.yml @@ -0,0 +1,7 @@ +# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps + +components/fatfs/test_apps/sdcard: + disable_test: + - if: IDF_TARGET in ["esp32s3", "esp32c2"] + temporary: true + reason: No sdspi runners for these targets diff --git a/components/fatfs/diskio/diskio_rawflash.c b/components/fatfs/diskio/diskio_rawflash.c index 382e532393..cbd03e0f31 100644 --- a/components/fatfs/diskio/diskio_rawflash.c +++ b/components/fatfs/diskio/diskio_rawflash.c @@ -1,16 +1,8 @@ -// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include #include "diskio_impl.h" @@ -22,11 +14,48 @@ static const char* TAG = "diskio_rawflash"; -const esp_partition_t* ff_raw_handles[FF_VOLUMES]; +static const esp_partition_t* s_ff_raw_handles[FF_VOLUMES]; +// Determine the sector size and sector count by parsing the boot sector +static size_t s_sector_size[FF_VOLUMES]; +static size_t s_sectors_count[FF_VOLUMES]; + +#define BPB_BytsPerSec 11 +#define BPB_TotSec16 19 +#define BPB_TotSec32 32 DSTATUS ff_raw_initialize (BYTE pdrv) { + + uint16_t sector_size_tmp; + uint16_t sectors_count_tmp_16; + uint32_t sectors_count_tmp_32; + + const esp_partition_t* part = s_ff_raw_handles[pdrv]; + assert(part); + esp_err_t err = esp_partition_read(part, BPB_BytsPerSec, §or_size_tmp, sizeof(sector_size_tmp)); + if (unlikely(err != ESP_OK)) { + ESP_LOGE(TAG, "esp_partition_read failed (0x%x)", err); + return RES_ERROR; + } + s_sector_size[pdrv] = sector_size_tmp; + + err = esp_partition_read(part, BPB_TotSec16, §ors_count_tmp_16, sizeof(sectors_count_tmp_16)); + if (unlikely(err != ESP_OK)) { + ESP_LOGE(TAG, "esp_partition_read failed (0x%x)", err); + return RES_ERROR; + } + s_sectors_count[pdrv] = sectors_count_tmp_16; + // For FAT32, the number of sectors is stored in a different field + if (sectors_count_tmp_16 == 0){ + err = esp_partition_read(part, BPB_TotSec32, §ors_count_tmp_32, sizeof(sectors_count_tmp_32)); + if (unlikely(err != ESP_OK)) { + ESP_LOGE(TAG, "esp_partition_read failed (0x%x)", err); + return RES_ERROR; + } + s_sectors_count[pdrv] = sectors_count_tmp_32; + } + return 0; } @@ -38,9 +67,9 @@ DSTATUS ff_raw_status (BYTE pdrv) DRESULT ff_raw_read (BYTE pdrv, BYTE *buff, DWORD sector, UINT count) { ESP_LOGV(TAG, "ff_raw_read - pdrv=%i, sector=%i, count=%in", (unsigned int)pdrv, (unsigned int)sector, (unsigned int)count); - const esp_partition_t* part = ff_raw_handles[pdrv]; + const esp_partition_t* part = s_ff_raw_handles[pdrv]; assert(part); - esp_err_t err = esp_partition_read(part, sector * SPI_FLASH_SEC_SIZE, buff, count * SPI_FLASH_SEC_SIZE); + esp_err_t err = esp_partition_read(part, sector * s_sector_size[pdrv], buff, count * s_sector_size[pdrv]); if (unlikely(err != ESP_OK)) { ESP_LOGE(TAG, "esp_partition_read failed (0x%x)", err); return RES_ERROR; @@ -56,17 +85,17 @@ DRESULT ff_raw_write (BYTE pdrv, const BYTE *buff, DWORD sector, UINT count) DRESULT ff_raw_ioctl (BYTE pdrv, BYTE cmd, void *buff) { - const esp_partition_t* part = ff_raw_handles[pdrv]; + const esp_partition_t* part = s_ff_raw_handles[pdrv]; ESP_LOGV(TAG, "ff_raw_ioctl: cmd=%in", cmd); assert(part); switch (cmd) { case CTRL_SYNC: return RES_OK; case GET_SECTOR_COUNT: - *((DWORD *) buff) = part->size / SPI_FLASH_SEC_SIZE; + *((DWORD *) buff) = s_sectors_count[pdrv]; return RES_OK; case GET_SECTOR_SIZE: - *((WORD *) buff) = SPI_FLASH_SEC_SIZE; + *((WORD *) buff) = s_sector_size[pdrv]; return RES_OK; case GET_BLOCK_SIZE: return RES_ERROR; @@ -88,7 +117,7 @@ esp_err_t ff_diskio_register_raw_partition(BYTE pdrv, const esp_partition_t* par .ioctl = &ff_raw_ioctl }; ff_diskio_register(pdrv, &raw_impl); - ff_raw_handles[pdrv] = part_handle; + s_ff_raw_handles[pdrv] = part_handle; return ESP_OK; } @@ -97,7 +126,7 @@ esp_err_t ff_diskio_register_raw_partition(BYTE pdrv, const esp_partition_t* par BYTE ff_diskio_get_pdrv_raw(const esp_partition_t* part_handle) { for (int i = 0; i < FF_VOLUMES; i++) { - if (part_handle == ff_raw_handles[i]) { + if (part_handle == s_ff_raw_handles[i]) { return i; } } diff --git a/components/fatfs/fatfs_utils/boot_sector.py b/components/fatfs/fatfs_utils/boot_sector.py index e8f25bf398..615dd06511 100644 --- a/components/fatfs/fatfs_utils/boot_sector.py +++ b/components/fatfs/fatfs_utils/boot_sector.py @@ -3,7 +3,7 @@ from inspect import getmembers, isroutine from typing import Optional -from construct import Const, Int8ul, Int16ul, Int32ul, PaddedString, Struct +from construct import Const, Int8ul, Int16ul, Int32ul, PaddedString, Struct, core from .exceptions import InconsistentFATAttributes, NotInitialized from .fatfs_state import BootSectorState @@ -56,7 +56,7 @@ class BootSector: assert BOOT_SECTOR_HEADER.sizeof() == BOOT_HEADER_SIZE def __init__(self, boot_sector_state: Optional[BootSectorState] = None) -> None: - self._parsed_header = None + self._parsed_header: dict = {} self.boot_sector_state: BootSectorState = boot_sector_state def generate_boot_sector(self) -> None: @@ -97,8 +97,12 @@ class BootSector: ) def parse_boot_sector(self, binary_data: bytes) -> None: - self._parsed_header = BootSector.BOOT_SECTOR_HEADER.parse(binary_data) - if self._parsed_header is None: + """ + Checks the validity of the boot sector and derives the metadata from boot sector to the structured shape. + """ + try: + self._parsed_header = BootSector.BOOT_SECTOR_HEADER.parse(binary_data) + except core.StreamError: raise NotInitialized('The boot sector header is not parsed successfully!') if self._parsed_header['BPB_TotSec16'] != 0x00: @@ -141,9 +145,14 @@ class BootSector: assert self.boot_sector_state.file_sys_type in (f'FAT{self.boot_sector_state.fatfs_type} ', 'FAT ') def __str__(self) -> str: - if self._parsed_header is None: + """ + FATFS properties parser (internal helper tool for fatfsgen.py/fatfsparse.py) + Provides all the properties of given FATFS instance by parsing its boot sector (returns formatted string) + """ + + if self._parsed_header == {}: return 'Boot sector is not initialized!' - res: str = 'Properties of the FATFS:\n' + res: str = 'FATFS properties:\n' for member in getmembers(self.boot_sector_state, lambda a: not (isroutine(a))): prop_ = getattr(self.boot_sector_state, member[0]) if isinstance(prop_, int) or isinstance(prop_, str) and not member[0].startswith('_'): @@ -152,7 +161,8 @@ class BootSector: @property def binary_image(self) -> bytes: - if len(self.boot_sector_state.binary_image) == 0: - raise NotInitialized('Boot sector is not generated nor initialized!') + # when BootSector is not instantiated, self.boot_sector_state might be None + if self.boot_sector_state is None or len(self.boot_sector_state.binary_image) == 0: + raise NotInitialized('Boot sector is not initialized!') bin_image_: bytes = self.boot_sector_state.binary_image return bin_image_ diff --git a/components/fatfs/fatfs_utils/cluster.py b/components/fatfs/fatfs_utils/cluster.py index 4ea6c315e6..ced9b1f5c3 100644 --- a/components/fatfs/fatfs_utils/cluster.py +++ b/components/fatfs/fatfs_utils/cluster.py @@ -30,6 +30,14 @@ class Cluster: cluster_id: int, boot_sector_state: BootSectorState, init_: bool) -> None: + """ + Initially, if init_ is False, the cluster is virtual and is not allocated (doesn't do changes in the FAT). + :param cluster_id: the cluster ID - a key value linking the file's cluster, + the corresponding physical cluster (data region) and the FAT table cluster. + :param boot_sector_state: auxiliary structure holding the file-system's metadata + :param init_: True for allocation the cluster on instantiation, otherwise False. + :returns: None + """ self.id: int = cluster_id self.boot_sector_state: BootSectorState = boot_sector_state @@ -50,8 +58,19 @@ class Cluster: def next_cluster(self, value): # type: (Optional[Cluster]) -> None self._next_cluster = value - def _cluster_id_to_logical_position_in_bits(self, _id: int) -> int: - # computes address of the cluster in fat table + def _cluster_id_to_fat_position_in_bits(self, _id: int) -> int: + """ + This private method calculates the position of the memory block (cluster) in the FAT table. + + :param _id: the cluster ID - a key value linking the file's cluster, + the corresponding physical cluster (data region) and the FAT table cluster. + :returns: bit offset of the cluster in FAT + e.g.: + 00003000: 42 65 00 2E 00 74 00 78 00 74 00 0F 00 43 FF FF + + For FAT12 the third cluster has value = 0x02E and ID = 2. + Its bit-address is 24 (24 bits preceding, 0-indexed), because 0x2E starts at the bit-offset 24. + """ logical_position_: int = self.boot_sector_state.fatfs_type * _id return logical_position_ @@ -73,18 +92,10 @@ class Cluster: def _compute_cluster_data_address(self) -> int: return self.compute_cluster_data_address(self.boot_sector_state, self.id) - def _set_left_half_byte(self, address: int, value: int) -> None: - self.boot_sector_state.binary_image[address] &= 0x0f - self.boot_sector_state.binary_image[address] |= value << 4 - - def _set_right_half_byte(self, address: int, value: int) -> None: - self.boot_sector_state.binary_image[address] &= 0xf0 - self.boot_sector_state.binary_image[address] |= value - @property def fat_cluster_address(self) -> int: """Determines how many bits precede the first bit of the cluster in FAT""" - return self._cluster_id_to_logical_position_in_bits(self.id) + return self._cluster_id_to_fat_position_in_bits(self.id) @property def real_cluster_address(self) -> int: @@ -141,6 +152,27 @@ class Cluster: 2. if the cluster index is odd, we set the first half of the computed byte and the full consequent byte. Order of half bytes is 1, 3, 2. """ + + def _set_msb_half_byte(address: int, value_: int) -> None: + """ + Sets 4 most significant bits (msb half-byte) of 'boot_sector_state.binary_image' at given + 'address' to 'value_' (size of variable 'value_' is half byte) + + If a byte contents is 0b11110000, the msb half-byte would be 0b1111 + """ + self.boot_sector_state.binary_image[address] &= 0x0f + self.boot_sector_state.binary_image[address] |= value_ << 4 + + def _set_lsb_half_byte(address: int, value_: int) -> None: + """ + Sets 4 least significant bits (lsb half-byte) of 'boot_sector_state.binary_image' at given + 'address' to 'value_' (size of variable 'value_' is half byte) + + If a byte contents is 0b11110000, the lsb half-byte would be 0b0000 + """ + self.boot_sector_state.binary_image[address] &= 0xf0 + self.boot_sector_state.binary_image[address] |= value_ + # value must fit into number of bits of the fat (12, 16 or 32) assert value <= (1 << self.boot_sector_state.fatfs_type) - 1 half_bytes = split_by_half_byte_12_bit_little_endian(value) @@ -151,10 +183,10 @@ class Cluster: if self.fat_cluster_address % 8 == 0: # even block bin_img_[self.real_cluster_address] = build_byte(half_bytes[1], half_bytes[0]) - self._set_right_half_byte(self.real_cluster_address + 1, half_bytes[2]) + _set_lsb_half_byte(self.real_cluster_address + 1, half_bytes[2]) elif self.fat_cluster_address % 8 != 0: # odd block - self._set_left_half_byte(self.real_cluster_address, half_bytes[0]) + _set_msb_half_byte(self.real_cluster_address, half_bytes[0]) bin_img_[self.real_cluster_address + 1] = build_byte(half_bytes[2], half_bytes[1]) elif self.boot_sector_state.fatfs_type == FAT16: bin_img_[self.real_cluster_address:self.real_cluster_address + 2] = Int16ul.build(value) @@ -162,6 +194,11 @@ class Cluster: @property def is_root(self) -> bool: + """ + The FAT12/FAT16 contains only one root directory, + the root directory allocates the first cluster with the ID `ROOT_BLOCK_ID`. + The method checks if the cluster belongs to the root directory. + """ return self.id == Cluster.ROOT_BLOCK_ID def allocate_cluster(self) -> None: diff --git a/components/fatfs/fatfs_utils/entry.py b/components/fatfs/fatfs_utils/entry.py index c33bd9e834..ec986a39c8 100644 --- a/components/fatfs/fatfs_utils/entry.py +++ b/components/fatfs/fatfs_utils/entry.py @@ -31,11 +31,14 @@ class Entry: LDIR_Name3_IDX: int = 28 LDIR_Name3_SIZE: int = 2 + # short entry in long file names + LDIR_DIR_NTRES: int = 0x18 # one entry can hold 13 characters with size 2 bytes distributed in three regions of the 32 bytes entry CHARS_PER_ENTRY: int = LDIR_Name1_SIZE + LDIR_Name2_SIZE + LDIR_Name3_SIZE + # the last 16 bytes record in the LFN entry has first byte masked with the following value + LAST_RECORD_LFN_ENTRY: int = 0x40 SHORT_ENTRY: int = -1 - # this value is used for short-like entry but with accepted lower case SHORT_ENTRY_LN: int = 0 @@ -103,7 +106,7 @@ class Entry: 00002040: 54 48 49 53 49 53 7E 31 54 58 54 20 00 00 00 00 THISIS~1TXT..... 00002050: 21 00 00 00 00 00 00 00 21 00 02 00 15 00 00 00 !.......!....... """ - order |= (0x40 if is_last else 0x00) + order |= (Entry.LAST_RECORD_LFN_ENTRY if is_last else 0x00) long_entry: bytes = (Int8ul.build(order) + # order of the long name entry (possibly masked with 0x40) names[0] + # first 5 characters (10 bytes) of the name part Int8ul.build(Entry.ATTR_LONG_NAME) + # one byte entity type ATTR_LONG_NAME @@ -124,7 +127,13 @@ class Entry: return {} names1 = entry_bytes_[14:26] names2 = entry_bytes_[28:32] - return {'order': order_, 'name1': names0, 'name2': names1, 'name3': names2, 'is_last': bool(order_ & 0x40 == 0x40)} + return { + 'order': order_, + 'name1': names0, + 'name2': names1, + 'name3': names2, + 'is_last': bool(order_ & Entry.LAST_RECORD_LFN_ENTRY == Entry.LAST_RECORD_LFN_ENTRY) + } @property def entry_bytes(self) -> bytes: diff --git a/components/fatfs/fatfs_utils/exceptions.py b/components/fatfs/fatfs_utils/exceptions.py index b27c760770..a3a27df5d6 100644 --- a/components/fatfs/fatfs_utils/exceptions.py +++ b/components/fatfs/fatfs_utils/exceptions.py @@ -48,4 +48,7 @@ class FatalError(Exception): class InconsistentFATAttributes(Exception): + """ + Caused by e.g. wrong number of clusters for given FAT type + """ pass diff --git a/components/fatfs/fatfs_utils/fat.py b/components/fatfs/fatfs_utils/fat.py index 4d5571c45f..396075dd08 100644 --- a/components/fatfs/fatfs_utils/fat.py +++ b/components/fatfs/fatfs_utils/fat.py @@ -1,7 +1,7 @@ # SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 -from typing import List +from typing import List, Optional from .cluster import Cluster from .exceptions import NoFreeClusterException @@ -22,7 +22,7 @@ class FAT: self.clusters[Cluster.ROOT_BLOCK_ID].allocate_cluster() def __init__(self, boot_sector_state: BootSectorState, init_: bool) -> None: - self._first_free_cluster_id = 0 + self._first_free_cluster_id = 1 self.boot_sector_state = boot_sector_state self.clusters: List[Cluster] = [Cluster(cluster_id=i, boot_sector_state=self.boot_sector_state, @@ -31,42 +31,67 @@ class FAT: self.allocate_root_dir() def get_cluster_value(self, cluster_id_: int) -> int: + """ + The method retrieves the values of the FAT memory block. + E.g. in case of FAT12: + 00000000: F8 FF FF 55 05 00 00 00 00 00 00 00 00 00 00 00 + + The reserved value is 0xFF8, the value of first cluster if 0xFFF, thus is last in chain, + and the value of the second cluster is 0x555, so refers to the cluster number 0x555. + """ fat_cluster_value_: int = self.clusters[cluster_id_].get_from_fat() return fat_cluster_value_ def is_cluster_last(self, cluster_id_: int) -> bool: + """ + Checks if the cluster is last in its cluster chain. If the value of the cluster is + 0xFFF for FAT12, 0xFFFF for FAT16 or 0xFFFFFFFF for FAT32, the cluster is the last. + """ value_ = self.get_cluster_value(cluster_id_) is_cluster_last_: bool = value_ == (1 << self.boot_sector_state.fatfs_type) - 1 return is_cluster_last_ - def chain_content(self, cluster_id_: int) -> bytearray: - bin_im: bytearray = self.boot_sector_state.binary_image - if self.is_cluster_last(cluster_id_): - data_address_ = Cluster.compute_cluster_data_address(self.boot_sector_state, cluster_id_) - content_: bytearray = bin_im[data_address_: data_address_ + self.boot_sector_state.sector_size] - return content_ - fat_value_: int = self.get_cluster_value(cluster_id_) + def get_chained_content(self, cluster_id_: int, size: Optional[int] = None) -> bytearray: + """ + The purpose of the method is retrieving the content from chain of clusters when the FAT FS partition + is analyzed. The file entry provides the reference to the first cluster, this method + traverses linked list of clusters and append partial results to the content. + """ + binary_image: bytearray = self.boot_sector_state.binary_image + data_address_ = Cluster.compute_cluster_data_address(self.boot_sector_state, cluster_id_) - content_ = bin_im[data_address_: data_address_ + self.boot_sector_state.sector_size] + content_ = binary_image[data_address_: data_address_ + self.boot_sector_state.sector_size] while not self.is_cluster_last(cluster_id_): - cluster_id_ = fat_value_ - fat_value_ = self.get_cluster_value(cluster_id_) + cluster_id_ = self.get_cluster_value(cluster_id_) data_address_ = Cluster.compute_cluster_data_address(self.boot_sector_state, cluster_id_) - content_ += bin_im[data_address_: data_address_ + self.boot_sector_state.sector_size] - return content_ + content_ += binary_image[data_address_: data_address_ + self.boot_sector_state.sector_size] + # the size is None if the object is directory + if size is None: + return content_ + return content_[:size] def find_free_cluster(self) -> Cluster: - # finds first empty cluster and allocates it - for cluster_id, cluster in enumerate(self.clusters[self._first_free_cluster_id:], - start=self._first_free_cluster_id): - if cluster.is_empty: - cluster.allocate_cluster() - self._first_free_cluster_id = cluster_id - return cluster - raise NoFreeClusterException('No free cluster available!') + """ + Returns the first free cluster and increments value of `self._first_free_cluster_id`. + The method works only in context of creating a partition from scratch. + In situations where the clusters are allocated and freed during the run of the program, + might the method cause `Out of space` error despite there would be free clusters. + """ + + if self._first_free_cluster_id + 1 >= len(self.clusters): + raise NoFreeClusterException('No free cluster available!') + cluster = self.clusters[self._first_free_cluster_id + 1] + if not cluster.is_empty: + raise NoFreeClusterException('No free cluster available!') + cluster.allocate_cluster() + self._first_free_cluster_id += 1 + return cluster def allocate_chain(self, first_cluster: Cluster, size: int) -> None: + """ + Allocates the linked list of clusters needed for the given file or directory. + """ current = first_cluster for _ in range(size - 1): free_cluster = self.find_free_cluster() diff --git a/components/fatfs/fatfs_utils/fatfs_state.py b/components/fatfs/fatfs_utils/fatfs_state.py index 45d1c7e519..22af7bfb0d 100644 --- a/components/fatfs/fatfs_utils/fatfs_state.py +++ b/components/fatfs/fatfs_utils/fatfs_state.py @@ -5,8 +5,9 @@ from textwrap import dedent from typing import Optional from .exceptions import InconsistentFATAttributes -from .utils import (ALLOWED_SECTOR_SIZES, FAT12, FAT12_MAX_CLUSTERS, FAT16, FAT16_MAX_CLUSTERS, FATDefaults, - get_fat_sectors_count, get_fatfs_type, get_non_data_sectors_cnt, number_of_clusters) +from .utils import (ALLOWED_SECTOR_SIZES, FAT12, FAT12_MAX_CLUSTERS, FAT16, FAT16_MAX_CLUSTERS, + RESERVED_CLUSTERS_COUNT, FATDefaults, get_fat_sectors_count, get_fatfs_type, + get_non_data_sectors_cnt, number_of_clusters) class FATFSState: @@ -133,7 +134,13 @@ class BootSectorState: @property def clusters(self) -> int: - clusters_cnt_: int = number_of_clusters(self.data_sectors, self.sectors_per_cluster) + """ + The actual number of clusters is calculated by `number_of_clusters`, + however, the initial two blocks of FAT are reserved (device type and root directory), + despite they don't refer to the data region. + Since that, two clusters are added to use the full potential of the FAT file system partition. + """ + clusters_cnt_: int = number_of_clusters(self.data_sectors, self.sectors_per_cluster) + RESERVED_CLUSTERS_COUNT return clusters_cnt_ @property diff --git a/components/fatfs/fatfs_utils/fs_object.py b/components/fatfs/fatfs_utils/fs_object.py index 9d68eb27b5..307087cfb3 100644 --- a/components/fatfs/fatfs_utils/fs_object.py +++ b/components/fatfs/fatfs_utils/fs_object.py @@ -12,8 +12,9 @@ from .fatfs_state import FATFSState from .long_filename_utils import (build_lfn_full_name, build_lfn_unique_entry_name_order, get_required_lfn_entries_count, split_name_to_lfn_entries, split_name_to_lfn_entry_blocks) -from .utils import (DATETIME, MAX_EXT_SIZE, MAX_NAME_SIZE, FATDefaults, build_lfn_short_entry_name, lfn_checksum, - required_clusters_count, split_content_into_sectors, split_to_name_and_extension) +from .utils import (DATETIME, INVALID_SFN_CHARS_PATTERN, MAX_EXT_SIZE, MAX_NAME_SIZE, FATDefaults, + build_lfn_short_entry_name, build_name, lfn_checksum, required_clusters_count, + split_content_into_sectors, split_to_name_and_extension) class File: @@ -45,7 +46,8 @@ class File: self._first_cluster = value def name_equals(self, name: str, extension: str) -> bool: - return self.name == name and self.extension == extension + equals_: bool = build_name(name, extension) == build_name(self.name, self.extension) + return equals_ def write(self, content: bytes) -> None: self.entry.update_content_size(len(content)) @@ -112,7 +114,8 @@ class Directory: self._first_cluster = value def name_equals(self, name: str, extension: str) -> bool: - return self.name == name and self.extension == extension + equals_: bool = build_name(name, extension) == build_name(self.name, self.extension) + return equals_ @property def entries_count(self) -> int: @@ -141,7 +144,7 @@ class Directory: def lookup_entity(self, object_name: str, extension: str): # type: ignore for entity in self.entities: - if entity.name == object_name and entity.extension == extension: + if build_name(entity.name, entity.extension) == build_name(object_name, extension): return entity return None @@ -198,11 +201,11 @@ class Directory: name, extension, target_dir, - free_cluster, + free_cluster_id, entity_type, date, time): - # type: (Entry, str, str, Directory, Cluster, int, DATETIME, DATETIME) -> Tuple[Cluster, Entry, Directory] + # type: (Entry, str, str, Directory, int, int, DATETIME, DATETIME) -> Entry lfn_full_name: str = build_lfn_full_name(name, extension) lfn_unique_entry_order: int = build_lfn_unique_entry_name_order(target_dir.entities, name) lfn_short_entry_name: str = build_lfn_short_entry_name(name, extension, lfn_unique_entry_order) @@ -210,12 +213,12 @@ class Directory: entries_count: int = get_required_lfn_entries_count(lfn_full_name) # entries in long file name entries chain starts with the last entry - split_names_reversed = reversed(list(enumerate(split_name_to_lfn_entries(lfn_full_name, entries_count)))) + split_names_reversed = list(reversed(list(enumerate(split_name_to_lfn_entries(lfn_full_name, entries_count))))) for i, name_split_to_entry in split_names_reversed: order: int = i + 1 blocks_: List[bytes] = split_name_to_lfn_entry_blocks(name_split_to_entry) lfn_names: List[bytes] = list(map(lambda x: x.lower(), blocks_)) - free_entry.allocate_entry(first_cluster_id=free_cluster.id, + free_entry.allocate_entry(first_cluster_id=free_cluster_id, entity_name=name, entity_extension=extension, entity_type=entity_type, @@ -224,38 +227,50 @@ class Directory: lfn_checksum_=checksum, lfn_is_last=order == entries_count) free_entry = target_dir.find_free_entry() or target_dir.chain_directory() - free_entry.allocate_entry(first_cluster_id=free_cluster.id, + free_entry.allocate_entry(first_cluster_id=free_cluster_id, entity_name=lfn_short_entry_name[:MAX_NAME_SIZE], entity_extension=lfn_short_entry_name[MAX_NAME_SIZE:], entity_type=entity_type, lfn_order=Entry.SHORT_ENTRY_LN, date=date, time=time) - return free_cluster, free_entry, target_dir + return free_entry + + @staticmethod + def _is_valid_sfn(name: str, extension: str) -> bool: + if INVALID_SFN_CHARS_PATTERN.search(name) or INVALID_SFN_CHARS_PATTERN.search(name): + return False + ret: bool = len(name) <= MAX_NAME_SIZE and len(extension) <= MAX_EXT_SIZE + return ret def allocate_object(self, name, entity_type, object_timestamp_, path_from_root=None, - extension=''): - # type: (str, int, datetime, Optional[List[str]], str) -> Tuple[Cluster, Entry, Directory] + extension='', + is_empty=False): + # type: (str, int, datetime, Optional[List[str]], str, bool) -> Tuple[Cluster, Entry, Directory] """ Method finds the target directory in the path and allocates cluster (both the record in FAT and cluster in the data region) and entry in the specified directory """ - free_cluster: Cluster = self.fat.find_free_cluster() + + free_cluster: Optional[Cluster] = None + free_cluster_id = 0x00 + if not is_empty: + free_cluster = self.fat.find_free_cluster() + free_cluster_id = free_cluster.id + target_dir: Directory = self if not path_from_root else self.recursive_search(path_from_root, self) free_entry: Entry = target_dir.find_free_entry() or target_dir.chain_directory() - name_fits_short_struct: bool = len(name) <= MAX_NAME_SIZE and len(extension) <= MAX_EXT_SIZE - fatfs_date_ = (object_timestamp_.year, object_timestamp_.month, object_timestamp_.day) fatfs_time_ = (object_timestamp_.hour, object_timestamp_.minute, object_timestamp_.second) - if not self.fatfs_state.long_names_enabled or name_fits_short_struct: - free_entry.allocate_entry(first_cluster_id=free_cluster.id, + if not self.fatfs_state.long_names_enabled or self._is_valid_sfn(name, extension): + free_entry.allocate_entry(first_cluster_id=free_cluster_id, entity_name=name, entity_extension=extension, date=fatfs_date_, @@ -263,25 +278,27 @@ class Directory: fits_short=True, entity_type=entity_type) return free_cluster, free_entry, target_dir - return self.allocate_long_name_object(free_entry=free_entry, - name=name, - extension=extension, - target_dir=target_dir, - free_cluster=free_cluster, - entity_type=entity_type, - date=fatfs_date_, - time=fatfs_time_) + return free_cluster, self.allocate_long_name_object(free_entry=free_entry, + name=name, + extension=extension, + target_dir=target_dir, + free_cluster_id=free_cluster_id, + entity_type=entity_type, + date=fatfs_date_, + time=fatfs_time_), target_dir def new_file(self, name: str, extension: str, path_from_root: Optional[List[str]], - object_timestamp_: datetime) -> None: + object_timestamp_: datetime, + is_empty: bool) -> None: free_cluster, free_entry, target_dir = self.allocate_object(name=name, extension=extension, entity_type=Directory.ATTR_ARCHIVE, path_from_root=path_from_root, - object_timestamp_=object_timestamp_) + object_timestamp_=object_timestamp_, + is_empty=is_empty) file: File = File(name=name, fat=self.fat, diff --git a/components/fatfs/fatfs_utils/long_filename_utils.py b/components/fatfs/fatfs_utils/long_filename_utils.py index ccd63b5317..649312aead 100644 --- a/components/fatfs/fatfs_utils/long_filename_utils.py +++ b/components/fatfs/fatfs_utils/long_filename_utils.py @@ -3,7 +3,8 @@ from typing import List from .entry import Entry -from .utils import convert_to_utf16_and_pad +from .exceptions import NoFreeClusterException +from .utils import build_name, convert_to_utf16_and_pad # File name with long filenames support can be as long as memory allows. It is split into entries # holding 13 characters of the filename, thus the number of required entries is ceil(len(long_name) / 13). @@ -11,6 +12,8 @@ from .utils import convert_to_utf16_and_pad # For creating long name entries we need to split the name by 13 characters using `split_name_to_lfn_entries` # and in every entry into three blocks with sizes 5, 6 and 2 characters using `split_name_to_lfn_entry`. +MAXIMAL_FILES_SAME_PREFIX: int = 127 + def get_required_lfn_entries_count(lfn_full_name: str) -> int: """ @@ -68,16 +71,18 @@ def build_lfn_unique_entry_name_order(entities: list, lfn_entry_name: str) -> in The short entry contains only the first 6 characters of the file name, and we have to distinguish it from other names within the directory starting with the same 6 characters. To make it unique, we add its order in relation to other names such that lfn_entry_name[:6] == other[:6]. - The order is specified by the character, starting with '1'. + The order is specified by the character, starting with chr(1). E.g. the file in directory 'thisisverylongfilenama.txt' will be named 'THISIS~1TXT' in its short entry. If we add another file 'thisisverylongfilenamax.txt' its name in the short entry will be 'THISIS~2TXT'. """ - preceding_entries: int = 0 + preceding_entries: int = 1 for entity in entities: if entity.name[:6] == lfn_entry_name[:6]: preceding_entries += 1 - return preceding_entries + ord('1') + if preceding_entries > MAXIMAL_FILES_SAME_PREFIX: + raise NoFreeClusterException('Maximal number of files with the same prefix is 127') + return preceding_entries def build_lfn_full_name(name: str, extension: str) -> str: @@ -85,4 +90,9 @@ def build_lfn_full_name(name: str, extension: str) -> str: The extension is optional, and the long filename entry explicitly specifies it, on the opposite as for short file names. """ - return f'{name}.{extension}' if len(extension) > 0 else name + lfn_record: str = build_name(name, extension) + # the name must be terminated with NULL terminator + # if it doesn't fit into the set of long name directory entries + if len(lfn_record) % Entry.CHARS_PER_ENTRY != 0: + return lfn_record + chr(0) + return lfn_record diff --git a/components/fatfs/fatfs_utils/utils.py b/components/fatfs/fatfs_utils/utils.py index e869a64064..3b516a9920 100644 --- a/components/fatfs/fatfs_utils/utils.py +++ b/components/fatfs/fatfs_utils/utils.py @@ -4,14 +4,19 @@ import argparse import binascii import os +import re import uuid from datetime import datetime from typing import List, Optional, Tuple from construct import BitsInteger, BitStruct, Int16ul +# the regex pattern defines symbols that are allowed by long file names but not by short file names +INVALID_SFN_CHARS_PATTERN = re.compile(r'[.+,;=\[\]]') + FAT12_MAX_CLUSTERS: int = 4085 FAT16_MAX_CLUSTERS: int = 65525 +RESERVED_CLUSTERS_COUNT: int = 2 PAD_CHAR: int = 0x20 FAT12: int = 12 FAT16: int = 16 @@ -42,7 +47,11 @@ FATFS_SECONDS_GRANULARITY: int = 2 LONG_NAMES_ENCODING: str = 'utf-16' SHORT_NAMES_ENCODING: str = 'utf-8' -ALLOWED_SECTOR_SIZES: List[int] = [4096] +# compatible with WL_SECTOR_SIZE +# choices for WL are WL_SECTOR_SIZE_512 and WL_SECTOR_SIZE_4096 +ALLOWED_WL_SECTOR_SIZES: List[int] = [512, 4096] +ALLOWED_SECTOR_SIZES: List[int] = [512, 1024, 2048, 4096] + ALLOWED_SECTORS_PER_CLUSTER: List[int] = [1, 2, 4, 8, 16, 32, 64, 128] @@ -118,14 +127,11 @@ def lfn_checksum(short_entry_name: str) -> int: def convert_to_utf16_and_pad(content: str, expected_size: int, - pad: bytes = FULL_BYTE, - terminator: bytes = b'\x00\x00') -> bytes: + pad: bytes = FULL_BYTE) -> bytes: # we need to get rid of the Byte order mark 0xfeff or 0xfffe, fatfs does not use it bom_utf16: bytes = b'\xfe\xff' encoded_content_utf16: bytes = content.encode(LONG_NAMES_ENCODING)[len(bom_utf16):] - terminated_encoded_content_utf16: bytes = (encoded_content_utf16 + terminator) if (2 * expected_size > len( - encoded_content_utf16) > 0) else encoded_content_utf16 - return terminated_encoded_content_utf16.ljust(2 * expected_size, pad) + return encoded_content_utf16.ljust(2 * expected_size, pad) def split_to_name_and_extension(full_name: str) -> Tuple[str, str]: @@ -159,7 +165,7 @@ def split_content_into_sectors(content: bytes, sector_size: int) -> List[bytes]: return result -def get_args_for_partition_generator(desc: str) -> argparse.Namespace: +def get_args_for_partition_generator(desc: str, wl: bool) -> argparse.Namespace: parser: argparse.ArgumentParser = argparse.ArgumentParser(description=desc) parser.add_argument('input_directory', help='Path to the directory that will be encoded into fatfs image') @@ -172,7 +178,7 @@ def get_args_for_partition_generator(desc: str) -> argparse.Namespace: parser.add_argument('--sector_size', default=FATDefaults.SECTOR_SIZE, type=int, - choices=ALLOWED_SECTOR_SIZES, + choices=ALLOWED_WL_SECTOR_SIZES if wl else ALLOWED_SECTOR_SIZES, help='Size of the partition in bytes') parser.add_argument('--sectors_per_cluster', default=1, @@ -224,6 +230,10 @@ TIME_ENTRY = BitStruct( ) +def build_name(name: str, extension: str) -> str: + return f'{name}.{extension}' if len(extension) > 0 else name + + def build_date_entry(year: int, mon: int, mday: int) -> int: """ :param year: denotes year starting from 1980 (0 ~ 1980, 1 ~ 1981, etc), valid values are 1980 + 0..127 inclusive @@ -280,4 +290,5 @@ class FATDefaults: TEMP_BUFFER_SIZE: int = 32 UPDATE_RATE: int = 16 WR_SIZE: int = 16 + # wear leveling metadata (config sector) contains always sector size 4096 WL_SECTOR_SIZE: int = 4096 diff --git a/components/fatfs/fatfsgen.py b/components/fatfs/fatfsgen.py index 8976b1567b..f01be09815 100755 --- a/components/fatfs/fatfsgen.py +++ b/components/fatfs/fatfsgen.py @@ -78,17 +78,41 @@ class FATFS: def create_file(self, name: str, extension: str = '', path_from_root: Optional[List[str]] = None, - object_timestamp_: datetime = FATFS_INCEPTION) -> None: - # when path_from_root is None the dir is root + object_timestamp_: datetime = FATFS_INCEPTION, + is_empty: bool = False) -> None: + """ + Root directory recursively finds the parent directory of the new file, allocates cluster, + entry and appends a new file into the parent directory. + + When path_from_root is None the dir is root. + + :param name: The name of the file. + :param extension: The extension of the file. + :param path_from_root: List of strings containing names of the ancestor directories in the given order. + :param object_timestamp_: is not None, this will be propagated to the file's entry + :param is_empty: True if there is no need to allocate any cluster, otherwise False + """ self.root_directory.new_file(name=name, extension=extension, path_from_root=path_from_root, - object_timestamp_=object_timestamp_) + object_timestamp_=object_timestamp_, + is_empty=is_empty) def create_directory(self, name: str, path_from_root: Optional[List[str]] = None, object_timestamp_: datetime = FATFS_INCEPTION) -> None: - # when path_from_root is None the dir is root + """ + Initially recursively finds a parent of the new directory + and then create a new directory inside the parent. + + When path_from_root is None the parent dir is root. + + :param name: The full name of the directory (excluding its path) + :param path_from_root: List of strings containing names of the ancestor directories in the given order. + :param object_timestamp_: in case the user preserves the timestamps, this will be propagated to the + metadata of the directory (to the corresponding entry) + :returns: None + """ parent_dir = self.root_directory if path_from_root: parent_dir = self.root_directory.recursive_search(path_from_root, self.root_directory) @@ -138,7 +162,8 @@ class FATFS: self.create_file(name=file_name, extension=extension, path_from_root=split_path[1:-1] or None, - object_timestamp_=object_timestamp) + object_timestamp_=object_timestamp, + is_empty=len(content) == 0) self.write_content(split_path[1:], content) elif os.path.isdir(real_path): if not is_dir: @@ -160,7 +185,7 @@ class FATFS: def main() -> None: - args = get_args_for_partition_generator('Create a FAT filesystem and populate it with directory content') + args = get_args_for_partition_generator('Create a FAT filesystem and populate it with directory content', wl=False) fatfs = FATFS(sector_size=args.sector_size, sectors_per_cluster=args.sectors_per_cluster, size=args.partition_size, diff --git a/components/fatfs/fatfsparse.py b/components/fatfs/fatfsparse.py index ad8195798f..c5d3716c56 100755 --- a/components/fatfs/fatfsparse.py +++ b/components/fatfs/fatfsparse.py @@ -24,7 +24,9 @@ def get_obj_name(obj_: dict, directory_bytes_: bytes, entry_position_: int, lfn_ ext_ = f'.{obj_ext_}' if len(obj_ext_) > 0 else '' obj_name_: str = obj_['DIR_Name'].rstrip(chr(PAD_CHAR)) + ext_ # short entry name - if not args.long_name_support: + # if LFN was detected, the record is considered as single SFN record only if DIR_NTRes == 0x18 (LDIR_DIR_NTRES) + # if LFN was not detected, the record cannot be part of the LFN, no matter the value of DIR_NTRes + if not args.long_name_support or obj_['DIR_NTRes'] == Entry.LDIR_DIR_NTRES: return obj_name_ full_name = {} @@ -55,9 +57,8 @@ def traverse_folder_tree(directory_bytes_: bytes, try: obj_: dict = Entry.ENTRY_FORMAT_SHORT_NAME.parse( directory_bytes_[obj_address_: obj_address_ + FATDefaults.ENTRY_SIZE]) - except (construct.core.ConstError, UnicodeDecodeError) as e: - if not args.long_name_support: - raise e + except (construct.core.ConstError, UnicodeDecodeError): + args.long_name_support = True continue if obj_['DIR_Attr'] == 0: # empty entry @@ -68,14 +69,17 @@ def traverse_folder_tree(directory_bytes_: bytes, entry_position_=i, lfn_checksum_=lfn_checksum(obj_['DIR_Name'] + obj_['DIR_Name_ext'])) if obj_['DIR_Attr'] == Entry.ATTR_ARCHIVE: - content_ = fat_.chain_content(cluster_id_=Entry.get_cluster_id(obj_)).rstrip(chr(0x00).encode()) + content_ = b'' + if obj_['DIR_FileSize'] > 0: + content_ = fat_.get_chained_content(cluster_id_=Entry.get_cluster_id(obj_), + size=obj_['DIR_FileSize']) with open(os.path.join(name, obj_name_), 'wb') as new_file: new_file.write(content_) elif obj_['DIR_Attr'] == Entry.ATTR_DIRECTORY: # avoid creating symlinks to itself and parent folder if obj_name_ in ('.', '..'): continue - child_directory_bytes_ = fat_.chain_content(cluster_id_=obj_['DIR_FstClusLO']) + child_directory_bytes_ = fat_.get_chained_content(cluster_id_=obj_['DIR_FstClusLO']) traverse_folder_tree(directory_bytes_=child_directory_bytes_, name=os.path.join(name, obj_name_), state_=state_, @@ -83,6 +87,25 @@ def traverse_folder_tree(directory_bytes_: bytes, binary_array_=binary_array_) +def remove_wear_levelling_if_exists(fs_: bytes) -> bytes: + """ + Detection of the wear levelling layer is performed in two steps: + 1) check if the first sector is a valid boot sector + 2) check if the size defined in the boot sector is the same as the partition size: + - if it is, there is no wear levelling layer + - otherwise, we need to remove wl for further processing + """ + try: + boot_sector__ = BootSector() + boot_sector__.parse_boot_sector(fs_) + if boot_sector__.boot_sector_state.size == len(fs_): + return fs_ + except construct.core.ConstError: + pass + plain_fs: bytes = remove_wl(fs_) + return plain_fs + + if __name__ == '__main__': desc = 'Tool for parsing fatfs image and extracting directory structure on host.' argument_parser: argparse.ArgumentParser = argparse.ArgumentParser(description=desc) @@ -90,14 +113,31 @@ if __name__ == '__main__': help='Path to the image that will be parsed and extracted.') argument_parser.add_argument('--long-name-support', action='store_true', - help='Set flag to enable long names support.') + help=argparse.SUPPRESS) + # ensures backward compatibility argument_parser.add_argument('--wear-leveling', action='store_true', - help='Set flag to parse an image encoded using wear levelling.') + help=argparse.SUPPRESS) + argument_parser.add_argument('--wl-layer', + choices=['detect', 'enabled', 'disabled'], + default=None, + help="If detection doesn't work correctly, " + 'you can force analyzer to or not to assume WL.') args = argument_parser.parse_args() + # if wear levelling is detected or user explicitly sets the parameter `--wl_layer enabled` + # the partition with wear levelling is transformed to partition without WL for convenient parsing + # in some cases the partitions with and without wear levelling can be 100% equivalent + # and only user can break this tie by explicitly setting + # the parameter --wl-layer to enabled, respectively disabled + if args.wear_leveling and args.wl_layer: + raise NotImplementedError('Argument --wear-leveling cannot be combined with --wl-layer!') + if args.wear_leveling: + args.wl_layer = 'enabled' + args.wl_layer = args.wl_layer or 'detect' + fs = read_filesystem(args.input_image) # An algorithm for removing wear levelling: @@ -109,8 +149,12 @@ if __name__ == '__main__': # 2. remove state sectors (trivial) # 3. remove cfg sector (trivial) # 4. valid fs is then old_fs[-mc:] + old_fs[:-mc] - if args.wear_leveling: + if args.wl_layer == 'enabled': fs = remove_wl(fs) + elif args.wl_layer != 'disabled': + # wear levelling is removed to enable parsing using common algorithm + fs = remove_wear_levelling_if_exists(fs) + boot_sector_ = BootSector() boot_sector_.parse_boot_sector(fs) fat = FAT(boot_sector_.boot_sector_state, init_=False) diff --git a/components/fatfs/test/CMakeLists.txt b/components/fatfs/test/CMakeLists.txt deleted file mode 100644 index 518f57c83a..0000000000 --- a/components/fatfs/test/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -idf_component_register(SRC_DIRS . - PRIV_INCLUDE_DIRS . - PRIV_REQUIRES cmock test_utils vfs fatfs - EMBED_TXTFILES fatfs.img - ) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/components/fatfs/test/fatfs.img b/components/fatfs/test/fatfs.img deleted file mode 100644 index d602cc782c..0000000000 Binary files a/components/fatfs/test/fatfs.img and /dev/null differ diff --git a/components/fatfs/test_apps/flash_ro/CMakeLists.txt b/components/fatfs/test_apps/flash_ro/CMakeLists.txt new file mode 100644 index 0000000000..9a1f08ef13 --- /dev/null +++ b/components/fatfs/test_apps/flash_ro/CMakeLists.txt @@ -0,0 +1,8 @@ +cmake_minimum_required(VERSION 3.16) + +set(COMPONENTS main) +set(EXTRA_COMPONENT_DIRS "${CMAKE_CURRENT_LIST_DIR}/../test_fatfs_common") + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) + +project(test_fatfs_flash_ro) diff --git a/components/fatfs/test_apps/flash_ro/README.md b/components/fatfs/test_apps/flash_ro/README.md new file mode 100644 index 0000000000..dd48f82c4d --- /dev/null +++ b/components/fatfs/test_apps/flash_ro/README.md @@ -0,0 +1,14 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | + +This test app runs a few FATFS test cases in a read-only FAT partition. + +These tests should be possible to run on any ESP development board, not extra hardware is necessary. + +The initial FAT image is generated during the build process in [main/CMakeLists.txt](main/CMakeLists.txt): +- `create_test_files` function creates a set of files expected by the test cases +- `fatfs_create_rawflash_image` generates a FAT image from the set of files (via `fatfsgen.py`) + +The generated FAT image is flashed into `storage` partition when running `idf.py flash`. + +See [../README.md](../README.md) for more information about FATFS test apps. diff --git a/components/fatfs/test_apps/flash_ro/main/CMakeLists.txt b/components/fatfs/test_apps/flash_ro/main/CMakeLists.txt new file mode 100644 index 0000000000..87329220aa --- /dev/null +++ b/components/fatfs/test_apps/flash_ro/main/CMakeLists.txt @@ -0,0 +1,41 @@ +idf_component_register(SRCS "test_fatfs_flash_ro.c" + INCLUDE_DIRS "." + PRIV_REQUIRES unity spi_flash fatfs vfs test_fatfs_common + WHOLE_ARCHIVE) + + +set(out_dir "${CMAKE_CURRENT_BINARY_DIR}/fatfs_image") + +# This helper function creates a set of files expected by the test case. +# The files are then added into the FAT image by 'fatfs_create_rawflash_image' below. +function(create_test_files) + message(STATUS "Generating source files for test_fatfs_flash_ro in ${out_dir}...") + + # used in "(raw) can read file" + file(WRITE "${out_dir}/hello.txt" "Hello, World!\n") + + # used in "(raw) can open maximum number of files" + foreach(i RANGE 1 32) + file(WRITE "${out_dir}/f/${i}.txt") + endforeach() + + # used in "(raw) opendir, readdir, rewinddir, seekdir work as expected" + file(WRITE "${out_dir}/dir/1.txt") + file(WRITE "${out_dir}/dir/2.txt") + file(WRITE "${out_dir}/dir/boo.bin") + file(WRITE "${out_dir}/dir/inner/3.txt") + + # used in "(raw) multiple tasks can use same volume" + foreach(i RANGE 1 4) + string(REPEAT "${i}" 32000 file_content) + file(WRITE "${out_dir}/ccrnt/${i}.txt" ${file_content}) + endforeach() + + # used in "(raw) read speed test" + string(REPEAT "a" 262144 file_content) + file(WRITE "${out_dir}/256k.bin" ${file_content}) +endfunction() + +create_test_files() + +fatfs_create_rawflash_image(storage ${out_dir} FLASH_IN_PROJECT PRESERVE_TIME) diff --git a/components/fatfs/test/test_fatfs_rawflash.c b/components/fatfs/test_apps/flash_ro/main/test_fatfs_flash_ro.c similarity index 78% rename from components/fatfs/test/test_fatfs_rawflash.c rename to components/fatfs/test_apps/flash_ro/main/test_fatfs_flash_ro.c index efb7437198..61786bfe97 100644 --- a/components/fatfs/test/test_fatfs_rawflash.c +++ b/components/fatfs/test_apps/flash_ro/main/test_fatfs_flash_ro.c @@ -11,53 +11,30 @@ #include #include #include "unity.h" -#include "test_utils.h" -#include "esp_log.h" -#include "esp_system.h" #include "esp_vfs.h" #include "esp_vfs_fat.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "test_fatfs_common.h" -#include "esp_partition.h" -#include "ff.h" -#include "esp_rom_sys.h" -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) -//IDF-5136 +void app_main(void) +{ + unity_run_menu(); +} + static void test_setup(size_t max_files) { - extern const char fatfs_start[] asm("_binary_fatfs_img_start"); - extern const char fatfs_end[] asm("_binary_fatfs_img_end"); esp_vfs_fat_sdmmc_mount_config_t mount_config = { .format_if_mount_failed = false, .max_files = max_files }; - const esp_partition_t* part = get_test_data_partition(); - - TEST_ASSERT(part->size == (fatfs_end - fatfs_start - 1)); - - spi_flash_mmap_handle_t mmap_handle; - const void* mmap_ptr; - TEST_ESP_OK(esp_partition_mmap(part, 0, part->size, SPI_FLASH_MMAP_DATA, &mmap_ptr, &mmap_handle)); - bool content_valid = memcmp(fatfs_start, mmap_ptr, part->size) == 0; - spi_flash_munmap(mmap_handle); - - if (!content_valid) { - printf("Copying fatfs.img into test partition...\n"); - esp_partition_erase_range(part, 0, part->size); - for (int i = 0; i < part->size; i+= SPI_FLASH_SEC_SIZE) { - ESP_ERROR_CHECK( esp_partition_write(part, i, fatfs_start + i, SPI_FLASH_SEC_SIZE) ); - } - } - - TEST_ESP_OK(esp_vfs_fat_spiflash_mount_ro("/spiflash", "flash_test", &mount_config)); + TEST_ESP_OK(esp_vfs_fat_spiflash_mount_ro("/spiflash", "storage", &mount_config)); } static void test_teardown(void) { - TEST_ESP_OK(esp_vfs_fat_spiflash_unmount_ro("/spiflash","flash_test")); + TEST_ESP_OK(esp_vfs_fat_spiflash_unmount_ro("/spiflash", "storage")); } TEST_CASE("(raw) can read file", "[fatfs]") @@ -94,7 +71,6 @@ TEST_CASE("(raw) can open maximum number of files", "[fatfs]") } - TEST_CASE("(raw) can lseek", "[fatfs]") { test_setup(5); @@ -129,7 +105,7 @@ TEST_CASE("(raw) stat returns correct values", "[fatfs]") printf("Reference time: %s", asctime(&tm)); struct stat st; - TEST_ASSERT_EQUAL(0, stat("/spiflash/stat.txt", &st)); + TEST_ASSERT_EQUAL(0, stat("/spiflash/hello.txt", &st)); time_t mtime = st.st_mtime; struct tm mtm; @@ -148,8 +124,6 @@ TEST_CASE("(raw) stat returns correct values", "[fatfs]") test_teardown(); } - - TEST_CASE("(raw) can opendir root directory of FS", "[fatfs]") { test_setup(5); @@ -161,7 +135,7 @@ TEST_CASE("(raw) can opendir root directory of FS", "[fatfs]") if (!de) { break; } - if (strcasecmp(de->d_name, "test_opd.txt") == 0) { + if (strcasecmp(de->d_name, "hello.txt") == 0) { found = true; break; } @@ -171,6 +145,7 @@ TEST_CASE("(raw) can opendir root directory of FS", "[fatfs]") test_teardown(); } + TEST_CASE("(raw) opendir, readdir, rewinddir, seekdir work as expected", "[fatfs]") { test_setup(5); @@ -229,20 +204,17 @@ TEST_CASE("(raw) opendir, readdir, rewinddir, seekdir work as expected", "[fatfs test_teardown(); } - typedef struct { const char* filename; size_t word_count; - int seed; - int val; + unsigned val; SemaphoreHandle_t done; - int result; + esp_err_t result; } read_test_arg_t; -#define READ_TEST_ARG_INIT(name, seed_, val_) \ +#define READ_TEST_ARG_INIT(name, val_) \ { \ .filename = name, \ - .seed = seed_, \ .word_count = 8000, \ .val = val_, \ .done = xSemaphoreCreateBinary() \ @@ -257,12 +229,11 @@ static void read_task(void* param) goto done; } - srand(args->seed); for (size_t i = 0; i < args->word_count; ++i) { - uint32_t rval; + unsigned rval; int cnt = fread(&rval, sizeof(rval), 1, f); if (cnt != 1 || rval != args->val) { - esp_rom_printf("E(r): i=%d, cnt=%d rval=%d val=%d\n\n", i, cnt, rval, args->val); + printf("E(r): i=%d, cnt=%d rval=0x08%x val=0x%08x\n", i, cnt, rval, args->val); args->result = ESP_FAIL; goto close; } @@ -278,7 +249,6 @@ done: vTaskDelete(NULL); } - TEST_CASE("(raw) multiple tasks can use same volume", "[fatfs]") { test_setup(5); @@ -287,10 +257,10 @@ TEST_CASE("(raw) multiple tasks can use same volume", "[fatfs]") snprintf(names[i], sizeof(names[i]), "/spiflash/ccrnt/%d.txt", i + 1); } - read_test_arg_t args1 = READ_TEST_ARG_INIT(names[0], 1, 0x31313131); - read_test_arg_t args2 = READ_TEST_ARG_INIT(names[1], 2, 0x32323232); - read_test_arg_t args3 = READ_TEST_ARG_INIT(names[2], 3, 0x33333333); - read_test_arg_t args4 = READ_TEST_ARG_INIT(names[3], 4, 0x34343434); + read_test_arg_t args1 = READ_TEST_ARG_INIT(names[0], 0x31313131); + read_test_arg_t args2 = READ_TEST_ARG_INIT(names[1], 0x32323232); + read_test_arg_t args3 = READ_TEST_ARG_INIT(names[2], 0x33333333); + read_test_arg_t args4 = READ_TEST_ARG_INIT(names[3], 0x34343434); const int cpuid_0 = 0; const int cpuid_1 = portNUM_PROCESSORS - 1; @@ -339,10 +309,3 @@ TEST_CASE("(raw) read speed test", "[fatfs][timeout=60]") free(buf); test_teardown(); } -#else //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) -TEST_CASE("FATFS dummy test", "[spi_flash]") -{ - printf("This test does nothing, just to make the UT build fatfs-fast-seek passed.\n"); - printf("When any case above is supported, remove this test case\n"); -} -#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) diff --git a/components/fatfs/test_apps/flash_ro/partitions.csv b/components/fatfs/test_apps/flash_ro/partitions.csv new file mode 100644 index 0000000000..a929971141 --- /dev/null +++ b/components/fatfs/test_apps/flash_ro/partitions.csv @@ -0,0 +1,3 @@ +# Name, Type, SubType, Offset, Size, Flags +factory, app, factory, 0x10000, 1M, +storage, data, fat, , 528k, diff --git a/components/fatfs/test_apps/flash_ro/pytest_fatfs_flash_ro.py b/components/fatfs/test_apps/flash_ro/pytest_fatfs_flash_ro.py new file mode 100644 index 0000000000..eda296ef2e --- /dev/null +++ b/components/fatfs/test_apps/flash_ro/pytest_fatfs_flash_ro.py @@ -0,0 +1,15 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +import pytest +from pytest_embedded import Dut + + +@pytest.mark.supported_targets +@pytest.mark.generic +def test_fatfs_flash_ro(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('') + dut.expect_exact('Enter test for running.') + dut.write('*') + dut.expect_unity_test_output() diff --git a/components/fatfs/test_apps/flash_ro/sdkconfig.defaults b/components/fatfs/test_apps/flash_ro/sdkconfig.defaults new file mode 100644 index 0000000000..c679bc7b4d --- /dev/null +++ b/components/fatfs/test_apps/flash_ro/sdkconfig.defaults @@ -0,0 +1,14 @@ +# General options for additional checks +CONFIG_HEAP_POISONING_COMPREHENSIVE=y +CONFIG_COMPILER_WARN_WRITE_STRINGS=y +CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y +CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y +CONFIG_COMPILER_STACK_CHECK_MODE_STRONG=y +CONFIG_COMPILER_STACK_CHECK=y + +# disable task watchdog since this app uses an interactive menu +CONFIG_ESP_TASK_WDT_INIT=n + +# use custom partition table +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" diff --git a/components/fatfs/test_apps/flash_wl/CMakeLists.txt b/components/fatfs/test_apps/flash_wl/CMakeLists.txt new file mode 100644 index 0000000000..3c63fc0c0c --- /dev/null +++ b/components/fatfs/test_apps/flash_wl/CMakeLists.txt @@ -0,0 +1,8 @@ +cmake_minimum_required(VERSION 3.16) + +set(COMPONENTS main) +set(EXTRA_COMPONENT_DIRS "${CMAKE_CURRENT_LIST_DIR}/../test_fatfs_common") + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) + +project(test_fatfs_flash_wl) diff --git a/components/fatfs/test_apps/flash_wl/README.md b/components/fatfs/test_apps/flash_wl/README.md new file mode 100644 index 0000000000..1a530524e6 --- /dev/null +++ b/components/fatfs/test_apps/flash_wl/README.md @@ -0,0 +1,8 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | + +This test app runs a few FATFS test cases in a wear levelling FAT partition. + +These tests should be possible to run on any ESP development board, not extra hardware is necessary. + +See [../README.md](../README.md) for more information about FATFS test apps. diff --git a/components/fatfs/test_apps/flash_wl/main/CMakeLists.txt b/components/fatfs/test_apps/flash_wl/main/CMakeLists.txt new file mode 100644 index 0000000000..20b600fca2 --- /dev/null +++ b/components/fatfs/test_apps/flash_wl/main/CMakeLists.txt @@ -0,0 +1,4 @@ +idf_component_register(SRCS "test_fatfs_flash_wl.c" + INCLUDE_DIRS "." + PRIV_REQUIRES unity spi_flash fatfs vfs test_fatfs_common + WHOLE_ARCHIVE) diff --git a/components/fatfs/test/test_fatfs_spiflash.c b/components/fatfs/test_apps/flash_wl/main/test_fatfs_flash_wl.c similarity index 90% rename from components/fatfs/test/test_fatfs_spiflash.c rename to components/fatfs/test_apps/flash_wl/main/test_fatfs_flash_wl.c index 19c33c0440..a73c6b8aa5 100644 --- a/components/fatfs/test/test_fatfs_spiflash.c +++ b/components/fatfs/test_apps/flash_wl/main/test_fatfs_flash_wl.c @@ -11,7 +11,7 @@ #include #include #include "unity.h" -#include "test_utils.h" +#include "esp_partition.h" #include "esp_log.h" #include "esp_random.h" #include "esp_vfs.h" @@ -23,9 +23,11 @@ #include "esp_partition.h" #include "esp_memory_utils.h" +void app_main(void) +{ + unity_run_menu(); +} -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) -//IDF-5136 static wl_handle_t s_test_wl_handle; static void test_setup(void) { @@ -44,7 +46,8 @@ static void test_teardown(void) TEST_CASE("(WL) can format partition", "[fatfs][wear_levelling]") { - const esp_partition_t* part = get_test_data_partition(); + const esp_partition_t* part = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, + ESP_PARTITION_SUBTYPE_DATA_FAT, NULL); esp_partition_erase_range(part, 0, part->size); test_setup(); test_teardown(); @@ -176,10 +179,22 @@ TEST_CASE("(WL) multiple tasks can use same volume", "[fatfs][wear_levelling]") test_teardown(); } +TEST_CASE("(WL) fatfs does not ignore leading spaces", "[fatfs][wear_levelling]") +{ + // the functionality of ignoring leading and trailing whitespaces is not implemented yet + // when the feature is implemented, this test will fail + // please, remove the test and implement the functionality in fatfsgen.py to preserve the consistency + test_setup(); + test_leading_spaces(); + test_teardown(); +} + + TEST_CASE("(WL) write/read speed test", "[fatfs][wear_levelling][timeout=60]") { /* Erase partition before running the test to get consistent results */ - const esp_partition_t* part = get_test_data_partition(); + const esp_partition_t* part = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, + ESP_PARTITION_SUBTYPE_DATA_FAT, NULL); esp_partition_erase_range(part, 0, part->size); test_setup(); @@ -210,7 +225,6 @@ TEST_CASE("(WL) can get partition info", "[fatfs][wear_levelling]") test_fatfs_info("/spiflash", "/spiflash/test.txt"); test_teardown(); } -#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) /* * In FatFs menuconfig, set CONFIG_FATFS_API_ENCODING to UTF-8 and set the @@ -218,9 +232,6 @@ TEST_CASE("(WL) can get partition info", "[fatfs][wear_levelling]") * Ensure that the text editor is UTF-8 compatible when compiling these tests. */ #if defined(CONFIG_FATFS_API_ENCODING_UTF_8) && (CONFIG_FATFS_CODEPAGE == 936) - -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) -//IDF-5136 TEST_CASE("(WL) can read file with UTF-8 encoded strings", "[fatfs][wear_levelling]") { test_setup(); @@ -235,7 +246,6 @@ TEST_CASE("(WL) opendir, readdir, rewinddir, seekdir work as expected using UTF- test_fatfs_opendir_readdir_rewinddir_utf_8("/spiflash/目录"); test_teardown(); } -#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) #endif //defined(CONFIG_FATFS_API_ENCODING_UTF_8) && (CONFIG_FATFS_CODEPAGE == 936) #ifdef CONFIG_SPIRAM diff --git a/components/fatfs/test_apps/flash_wl/partitions.csv b/components/fatfs/test_apps/flash_wl/partitions.csv new file mode 100644 index 0000000000..a929971141 --- /dev/null +++ b/components/fatfs/test_apps/flash_wl/partitions.csv @@ -0,0 +1,3 @@ +# Name, Type, SubType, Offset, Size, Flags +factory, app, factory, 0x10000, 1M, +storage, data, fat, , 528k, diff --git a/components/fatfs/test_apps/flash_wl/pytest_fatfs_flash_wl.py b/components/fatfs/test_apps/flash_wl/pytest_fatfs_flash_wl.py new file mode 100644 index 0000000000..70b46cbf25 --- /dev/null +++ b/components/fatfs/test_apps/flash_wl/pytest_fatfs_flash_wl.py @@ -0,0 +1,39 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +import pytest +from pytest_embedded import Dut + + +@pytest.mark.supported_targets +@pytest.mark.generic +@pytest.mark.parametrize( + 'config', + [ + 'default', + 'release', + 'fastseek', + ] +) +def test_fatfs_flash_wl_generic(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('') + dut.expect_exact('Enter test for running.') + dut.write('*') + dut.expect_unity_test_output(timeout=120) + + +@pytest.mark.supported_targets +@pytest.mark.psram +@pytest.mark.parametrize( + 'config', + [ + 'psram', + ] +) +def test_fatfs_flash_wl_psram(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('') + dut.expect_exact('Enter test for running.') + dut.write('*') + dut.expect_unity_test_output(timeout=120) diff --git a/components/soc/esp32c3/include/soc/soc_ulp.h b/components/fatfs/test_apps/flash_wl/sdkconfig.ci.default similarity index 100% rename from components/soc/esp32c3/include/soc/soc_ulp.h rename to components/fatfs/test_apps/flash_wl/sdkconfig.ci.default diff --git a/tools/unit-test-app/configs/fatfs_fast_seek b/components/fatfs/test_apps/flash_wl/sdkconfig.ci.fastseek similarity index 75% rename from tools/unit-test-app/configs/fatfs_fast_seek rename to components/fatfs/test_apps/flash_wl/sdkconfig.ci.fastseek index 0a2037a670..6b1351cf77 100644 --- a/tools/unit-test-app/configs/fatfs_fast_seek +++ b/components/fatfs/test_apps/flash_wl/sdkconfig.ci.fastseek @@ -1,3 +1,2 @@ -TEST_COMPONENTS=fatfs CONFIG_FATFS_USE_FASTSEEK=y CONFIG_FATFS_FAST_SEEK_BUFFER_SIZE=64 diff --git a/components/fatfs/test_apps/flash_wl/sdkconfig.ci.psram b/components/fatfs/test_apps/flash_wl/sdkconfig.ci.psram new file mode 100644 index 0000000000..b3b45db94a --- /dev/null +++ b/components/fatfs/test_apps/flash_wl/sdkconfig.ci.psram @@ -0,0 +1,3 @@ +CONFIG_SPIRAM=y +CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=0 +CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y diff --git a/components/fatfs/test_apps/flash_wl/sdkconfig.ci.release b/components/fatfs/test_apps/flash_wl/sdkconfig.ci.release new file mode 100644 index 0000000000..6a81ea9ab9 --- /dev/null +++ b/components/fatfs/test_apps/flash_wl/sdkconfig.ci.release @@ -0,0 +1,2 @@ +CONFIG_COMPILER_OPTIMIZATION_SIZE=y +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y diff --git a/components/fatfs/test_apps/flash_wl/sdkconfig.defaults b/components/fatfs/test_apps/flash_wl/sdkconfig.defaults new file mode 100644 index 0000000000..80df3c5ec0 --- /dev/null +++ b/components/fatfs/test_apps/flash_wl/sdkconfig.defaults @@ -0,0 +1,18 @@ +# General options for additional checks +CONFIG_HEAP_POISONING_COMPREHENSIVE=y +CONFIG_COMPILER_WARN_WRITE_STRINGS=y +CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y +CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y +CONFIG_COMPILER_STACK_CHECK_MODE_STRONG=y +CONFIG_COMPILER_STACK_CHECK=y + +# disable task watchdog since this app uses an interactive menu +CONFIG_ESP_TASK_WDT_INIT=n + +# use custom partition table +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" + +# some tests verify file name encoding +CONFIG_FATFS_API_ENCODING_UTF_8=y +CONFIG_FATFS_CODEPAGE_936=y diff --git a/components/fatfs/test_apps/sdcard/CMakeLists.txt b/components/fatfs/test_apps/sdcard/CMakeLists.txt new file mode 100644 index 0000000000..a01f216624 --- /dev/null +++ b/components/fatfs/test_apps/sdcard/CMakeLists.txt @@ -0,0 +1,8 @@ +cmake_minimum_required(VERSION 3.16) + +set(COMPONENTS main) +set(EXTRA_COMPONENT_DIRS "${CMAKE_CURRENT_LIST_DIR}/../test_fatfs_common") + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) + +project(test_fatfs_sdcard) diff --git a/components/fatfs/test_apps/sdcard/README.md b/components/fatfs/test_apps/sdcard/README.md new file mode 100644 index 0000000000..237e42a9d6 --- /dev/null +++ b/components/fatfs/test_apps/sdcard/README.md @@ -0,0 +1,14 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | + +This test app runs a few FATFS test cases in a FAT-formatted SD card. + +These tests require a development board with an SD card slot: + +* ESP32-WROVER-KIT +* ESP32-S2 USB_OTG +* ESP32-C3-DevKit-C with an SD card breakout board + +The test cases are split between `[sdmmc]` and `[sdspi]`. Only a few tests are executed for sdspi, though. The app could be refactored to ensure that a similar set of tests runs for sdmmc and sdspi. + +See [../README.md](../README.md) for more information about FATFS test apps. diff --git a/components/fatfs/test_apps/sdcard/main/CMakeLists.txt b/components/fatfs/test_apps/sdcard/main/CMakeLists.txt new file mode 100644 index 0000000000..be2a969afb --- /dev/null +++ b/components/fatfs/test_apps/sdcard/main/CMakeLists.txt @@ -0,0 +1,8 @@ +idf_component_register(SRCS "test_fatfs_sdcard_main.c" "test_fatfs_sdspi.c" + INCLUDE_DIRS "." + PRIV_REQUIRES unity fatfs vfs sdmmc driver test_fatfs_common + WHOLE_ARCHIVE) + +if(CONFIG_SOC_SDMMC_HOST_SUPPORTED) + target_sources(${COMPONENT_LIB} PRIVATE "test_fatfs_sdmmc.c") +endif() diff --git a/components/fatfs/test_apps/sdcard/main/test_fatfs_sdcard_main.c b/components/fatfs/test_apps/sdcard/main/test_fatfs_sdcard_main.c new file mode 100644 index 0000000000..1b61d31b58 --- /dev/null +++ b/components/fatfs/test_apps/sdcard/main/test_fatfs_sdcard_main.c @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include "unity.h" + +void app_main(void) +{ + unity_run_menu(); +} diff --git a/components/fatfs/test/test_fatfs_sdmmc.c b/components/fatfs/test_apps/sdcard/main/test_fatfs_sdmmc.c similarity index 62% rename from components/fatfs/test/test_fatfs_sdmmc.c rename to components/fatfs/test_apps/sdcard/main/test_fatfs_sdmmc.c index a9504d0ace..d18359e121 100644 --- a/components/fatfs/test/test_fatfs_sdmmc.c +++ b/components/fatfs/test_apps/sdcard/main/test_fatfs_sdmmc.c @@ -47,12 +47,10 @@ #endif //SPI_DMA_CHAN #define SDSPI_HOST_ID SPI2_HOST -#if SOC_SDMMC_HOST_SUPPORTED #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) // No runner #include "driver/sdmmc_host.h" - static void test_setup_sdmmc(void) { sdmmc_host_t host = SDMMC_HOST_DEFAULT(); @@ -72,7 +70,7 @@ static void test_teardown_sdmmc(void) static const char* test_filename = "/sdcard/hello.txt"; -TEST_CASE("Mount fails cleanly without card inserted", "[fatfs][sd][ignore]") +TEST_CASE("Mount fails cleanly without card inserted", "[fatfs][ignore]") { size_t heap_size; HEAP_SIZE_CAPTURE(heap_size); @@ -92,14 +90,14 @@ TEST_CASE("Mount fails cleanly without card inserted", "[fatfs][sd][ignore]") HEAP_SIZE_CHECK(heap_size, 0); } -TEST_CASE("(SD) can create and write file", "[fatfs][sd][test_env=UT_T1_SDMODE][timeout=60]") +TEST_CASE("(SD) can create and write file", "[fatfs][sdmmc]") { test_setup_sdmmc(); test_fatfs_create_file_with_text(test_filename, fatfs_test_hello_str); test_teardown_sdmmc(); } -TEST_CASE("(SD) can read file", "[fatfs][test_env=UT_T1_SDMODE][timeout=60]") +TEST_CASE("(SD) can read file", "[fatfs][sdmmc]") { test_setup_sdmmc(); test_fatfs_create_file_with_text(test_filename, fatfs_test_hello_str); @@ -107,7 +105,7 @@ TEST_CASE("(SD) can read file", "[fatfs][test_env=UT_T1_SDMODE][timeout=60]") test_teardown_sdmmc(); } -TEST_CASE("(SD) can read file with pread()", "[fatfs][test_env=UT_T1_SDMODE][timeout=60]") +TEST_CASE("(SD) can read file with pread()", "[fatfs][sdmmc]") { test_setup_sdmmc(); test_fatfs_create_file_with_text(test_filename, fatfs_test_hello_str); @@ -115,91 +113,91 @@ TEST_CASE("(SD) can read file with pread()", "[fatfs][test_env=UT_T1_SDMODE][tim test_teardown_sdmmc(); } -TEST_CASE("(SD) pwrite() works well", "[fatfs][test_env=UT_T1_SDMODE][timeout=60]") +TEST_CASE("(SD) pwrite() works well", "[fatfs][sdmmc]") { test_setup_sdmmc(); test_fatfs_pwrite_file(test_filename); test_teardown_sdmmc(); } -TEST_CASE("(SD) overwrite and append file", "[fatfs][sd][test_env=UT_T1_SDMODE][timeout=60]") +TEST_CASE("(SD) overwrite and append file", "[fatfs][sdmmc]") { test_setup_sdmmc(); test_fatfs_overwrite_append(test_filename); test_teardown_sdmmc(); } -TEST_CASE("(SD) can lseek", "[fatfs][sd][test_env=UT_T1_SDMODE][timeout=60]") +TEST_CASE("(SD) can lseek", "[fatfs][sdmmc]") { test_setup_sdmmc(); test_fatfs_lseek("/sdcard/seek.txt"); test_teardown_sdmmc(); } -TEST_CASE("(SD) can truncate", "[fatfs][sd][test_env=UT_T1_SDMODE][timeout=60]") +TEST_CASE("(SD) can truncate", "[fatfs][sdmmc]") { test_setup_sdmmc(); test_fatfs_truncate_file("/sdcard/truncate.txt"); test_teardown_sdmmc(); } -TEST_CASE("(SD) can ftruncate", "[fatfs][sd][test_env=UT_T1_SDMODE][timeout=60]") +TEST_CASE("(SD) can ftruncate", "[fatfs][sdmmc]") { test_setup_sdmmc(); test_fatfs_ftruncate_file("/sdcard/ftrunc.txt"); test_teardown_sdmmc(); } -TEST_CASE("(SD) stat returns correct values", "[fatfs][test_env=UT_T1_SDMODE][timeout=60]") +TEST_CASE("(SD) stat returns correct values", "[fatfs][sdmmc]") { test_setup_sdmmc(); test_fatfs_stat("/sdcard/stat.txt", "/sdcard"); test_teardown_sdmmc(); } -TEST_CASE("(SD) utime sets modification time", "[fatfs][test_env=UT_T1_SDMODE][timeout=60]") +TEST_CASE("(SD) utime sets modification time", "[fatfs][sdmmc]") { test_setup_sdmmc(); test_fatfs_utime("/sdcard/utime.txt", "/sdcard"); test_teardown_sdmmc(); } -TEST_CASE("(SD) unlink removes a file", "[fatfs][test_env=UT_T1_SDMODE][timeout=60]") +TEST_CASE("(SD) unlink removes a file", "[fatfs][sdmmc]") { test_setup_sdmmc(); test_fatfs_unlink("/sdcard/unlink.txt"); test_teardown_sdmmc(); } -TEST_CASE("(SD) link copies a file, rename moves a file", "[fatfs][test_env=UT_T1_SDMODE][timeout=60]") +TEST_CASE("(SD) link copies a file, rename moves a file", "[fatfs][sdmmc]") { test_setup_sdmmc(); test_fatfs_link_rename("/sdcard/link"); test_teardown_sdmmc(); } -TEST_CASE("(SD) can create and remove directories", "[fatfs][test_env=UT_T1_SDMODE][timeout=60]") +TEST_CASE("(SD) can create and remove directories", "[fatfs][sdmmc]") { test_setup_sdmmc(); test_fatfs_mkdir_rmdir("/sdcard/dir"); test_teardown_sdmmc(); } -TEST_CASE("(SD) can opendir root directory of FS", "[fatfs][test_env=UT_T1_SDMODE][timeout=60]") +TEST_CASE("(SD) can opendir root directory of FS", "[fatfs][sdmmc]") { test_setup_sdmmc(); test_fatfs_can_opendir("/sdcard"); test_teardown_sdmmc(); } -TEST_CASE("(SD) opendir, readdir, rewinddir, seekdir work as expected", "[fatfs][test_env=UT_T1_SDMODE][timeout=60]") +TEST_CASE("(SD) opendir, readdir, rewinddir, seekdir work as expected", "[fatfs][sdmmc]") { test_setup_sdmmc(); test_fatfs_opendir_readdir_rewinddir("/sdcard/dir"); test_teardown_sdmmc(); } -TEST_CASE("(SD) multiple tasks can use same volume", "[fatfs][test_env=UT_T1_SDMODE][timeout=60]") +TEST_CASE("(SD) multiple tasks can use same volume", "[fatfs][sdmmc]") { test_setup_sdmmc(); test_fatfs_concurrent("/sdcard/f"); @@ -208,7 +206,7 @@ TEST_CASE("(SD) multiple tasks can use same volume", "[fatfs][test_env=UT_T1_SDM static void sdmmc_speed_test(void *buf, size_t buf_size, size_t file_size, bool write); -TEST_CASE("(SD) write/read speed test", "[fatfs][sd][test_env=UT_T1_SDMODE][timeout=60]") +TEST_CASE("(SD) write/read speed test", "[fatfs][sdmmc]") { size_t heap_size; HEAP_SIZE_CAPTURE(heap_size); @@ -248,7 +246,7 @@ static void sdmmc_speed_test(void *buf, size_t buf_size, size_t file_size, bool TEST_ESP_OK(esp_vfs_fat_sdmmc_unmount()); } -TEST_CASE("(SD) mount two FAT partitions, SDMMC and WL, at the same time", "[fatfs][sd][test_env=UT_T1_SDMODE][timeout=60]") +TEST_CASE("(SD) mount two FAT partitions, SDMMC and WL, at the same time", "[fatfs][sdmmc]") { esp_vfs_fat_sdmmc_mount_config_t mount_config = { .format_if_mount_failed = true, @@ -260,10 +258,10 @@ TEST_CASE("(SD) mount two FAT partitions, SDMMC and WL, at the same time", "[fat const char* str_sd = "this is sd\n"; const char* str_wl = "this is spiflash\n"; - /* Erase flash before the firs use */ - const esp_partition_t *test_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, "flash_test"); + /* Erase flash before the first use */ + const esp_partition_t *test_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_FAT, NULL); + TEST_ASSERT_NOT_NULL(test_partition); esp_partition_erase_range(test_partition, 0, test_partition->size); - printf("Partition erased: addr- 0x%08x, size- 0x%08x\n", test_partition->address, test_partition->size); /* Mount FATFS in SD can WL at the same time. Create a file on each FS */ wl_handle_t wl_handle = WL_INVALID_HANDLE; @@ -307,7 +305,7 @@ TEST_CASE("(SD) mount two FAT partitions, SDMMC and WL, at the same time", "[fat static const char* test_filename_utf_8 = "/sdcard/测试文件.txt"; -TEST_CASE("(SD) can read file using UTF-8 encoded strings", "[fatfs][sd][test_env=UT_T1_SDMODE]") +TEST_CASE("(SD) can read file using UTF-8 encoded strings", "[fatfs][sdmmc]") { test_setup_sdmmc(); test_fatfs_create_file_with_text(test_filename_utf_8, fatfs_test_hello_str_utf); @@ -323,7 +321,7 @@ TEST_CASE("(SD) opendir, readdir, rewinddir, seekdir work as expected using UTF- } #endif // CONFIG_FATFS_API_ENCODING_UTF_8 && CONFIG_FATFS_CODEPAGE == 936 -TEST_CASE("(SD) can get partition info", "[fatfs][sd][test_env=UT_T1_SDMODE][timeout=60]") +TEST_CASE("(SD) can get partition info", "[fatfs][sdmmc]") { test_setup_sdmmc(); test_fatfs_info("/sdcard", "/sdcard/test.txt"); @@ -331,122 +329,3 @@ TEST_CASE("(SD) can get partition info", "[fatfs][sd][test_env=UT_T1_SDMODE][tim } #endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) -#endif //SDMMC HOST SUPPORTED - - -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3, ESP32C2) -//no runners - -typedef struct sdspi_mem { - size_t heap_size; - uint32_t* buf; -} sdspi_mem_t; - -static void sdspi_speed_test(void *buf, size_t buf_size, size_t file_size, bool write); - -static void test_setup_sdspi(sdspi_mem_t* mem) -{ - HEAP_SIZE_CAPTURE(mem->heap_size); - - const size_t buf_size = 16 * 1024; - mem->buf = (uint32_t*) calloc(1, buf_size); - esp_fill_random(mem->buf, buf_size); - - spi_bus_config_t bus_cfg = { - .mosi_io_num = SDSPI_MOSI_PIN, - .miso_io_num = SDSPI_MISO_PIN, - .sclk_io_num = SDSPI_CLK_PIN, - .quadwp_io_num = -1, - .quadhd_io_num = -1, - .max_transfer_sz = 4000, - }; - esp_err_t err = spi_bus_initialize(SDSPI_HOST_ID, &bus_cfg, SPI_DMA_CHAN); - TEST_ESP_OK(err); -} - -static void test_teardown_sdspi(sdspi_mem_t* mem) -{ - free(mem->buf); - spi_bus_free(SDSPI_HOST_ID); - HEAP_SIZE_CHECK(mem->heap_size, 0); -} - -TEST_CASE("(SDSPI) write/read speed test", "[fatfs][sd][test_env=UT_T1_SPIMODE][timeout=60]") -{ - sdspi_mem_t mem; - size_t file_size = 1 * 1024 * 1024; - - test_setup_sdspi(&mem); - - sdspi_speed_test(mem.buf, 4 * 1024, file_size, true); - sdspi_speed_test(mem.buf, 8 * 1024, file_size, true); - sdspi_speed_test(mem.buf, 16 * 1024, file_size, true); - - sdspi_speed_test(mem.buf, 4 * 1024, file_size, false); - sdspi_speed_test(mem.buf, 8 * 1024, file_size, false); - sdspi_speed_test(mem.buf, 16 * 1024, file_size, false); - - test_teardown_sdspi(&mem); -} - -static void sdspi_speed_test(void *buf, size_t buf_size, size_t file_size, bool write) -{ - const char path[] = "/sdcard"; - sdmmc_card_t *card; - card = NULL; - sdspi_device_config_t device_cfg = { - .gpio_cs = SDSPI_CS_PIN, - .host_id = SDSPI_HOST_ID, - .gpio_cd = SDSPI_SLOT_NO_CD, - .gpio_wp = SDSPI_SLOT_NO_WP, - .gpio_int = SDSPI_SLOT_NO_INT, - }; - - sdmmc_host_t host = SDSPI_HOST_DEFAULT(); - host.slot = SDSPI_HOST_ID; - esp_vfs_fat_sdmmc_mount_config_t mount_config = { - .format_if_mount_failed = write, - .max_files = 5, - .allocation_unit_size = 64 * 1024 - }; - TEST_ESP_OK(esp_vfs_fat_sdspi_mount(path, &host, &device_cfg, &mount_config, &card)); - - test_fatfs_rw_speed("/sdcard/4mb.bin", buf, buf_size, file_size, write); - - TEST_ESP_OK(esp_vfs_fat_sdcard_unmount(path, card)); -} - -TEST_CASE("(SDSPI) can get partition info", "[fatfs][sd][test_env=UT_T1_SPIMODE][timeout=60]") -{ - sdspi_mem_t mem; - - test_setup_sdspi(&mem); - - const char path[] = "/sdcard"; - sdmmc_card_t *card; - card = NULL; - sdspi_device_config_t device_cfg = { - .gpio_cs = SDSPI_CS_PIN, - .host_id = SDSPI_HOST_ID, - .gpio_cd = SDSPI_SLOT_NO_CD, - .gpio_wp = SDSPI_SLOT_NO_WP, - .gpio_int = SDSPI_SLOT_NO_INT, - }; - - sdmmc_host_t host = SDSPI_HOST_DEFAULT(); - host.slot = SDSPI_HOST_ID; - esp_vfs_fat_sdmmc_mount_config_t mount_config = { - .format_if_mount_failed = true, - .max_files = 5, - .allocation_unit_size = 64 * 1024 - }; - TEST_ESP_OK(esp_vfs_fat_sdspi_mount(path, &host, &device_cfg, &mount_config, &card)); - - test_fatfs_info("/sdcard", "/sdcard/test.txt"); - - TEST_ESP_OK(esp_vfs_fat_sdcard_unmount(path, card)); - - test_teardown_sdspi(&mem); -} - -#endif //TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) diff --git a/components/fatfs/test_apps/sdcard/main/test_fatfs_sdspi.c b/components/fatfs/test_apps/sdcard/main/test_fatfs_sdspi.c new file mode 100644 index 0000000000..d79da9f57b --- /dev/null +++ b/components/fatfs/test_apps/sdcard/main/test_fatfs_sdspi.c @@ -0,0 +1,165 @@ +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include "unity.h" +#include "esp_log.h" +#include "esp_random.h" +#include "esp_vfs.h" +#include "esp_vfs_fat.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "driver/sdmmc_defs.h" +#include "sdmmc_cmd.h" +#include "ff.h" +#include "test_fatfs_common.h" +#include "soc/soc_caps.h" + +#if CONFIG_IDF_TARGET_ESP32 +#define SDSPI_MISO_PIN 2 +#define SDSPI_MOSI_PIN 15 +#define SDSPI_CLK_PIN 14 +#define SDSPI_CS_PIN 13 +#elif CONFIG_IDF_TARGET_ESP32S2 +// Adapted for internal test board ESP-32-S3-USB-OTG-Ev-BOARD_V1.0 (with ESP32-S2-MINI-1 module) +#define SDSPI_MISO_PIN 37 +#define SDSPI_MOSI_PIN 35 +#define SDSPI_CLK_PIN 36 +#define SDSPI_CS_PIN 34 +#elif CONFIG_IDF_TARGET_ESP32C3 +#define SDSPI_MISO_PIN 6 +#define SDSPI_MOSI_PIN 4 +#define SDSPI_CLK_PIN 5 +#define SDSPI_CS_PIN 1 +#define SPI_DMA_CHAN SPI_DMA_CH_AUTO +#endif //CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3 + +#ifndef SPI_DMA_CHAN +#define SPI_DMA_CHAN 1 +#endif //SPI_DMA_CHAN +#define SDSPI_HOST_ID SPI2_HOST + +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3, ESP32C2) +//no runners + +typedef struct sdspi_mem { + size_t heap_size; + uint32_t* buf; +} sdspi_mem_t; + +static void sdspi_speed_test(void *buf, size_t buf_size, size_t file_size, bool write); + +static void test_setup_sdspi(sdspi_mem_t* mem) +{ + HEAP_SIZE_CAPTURE(mem->heap_size); + + const size_t buf_size = 16 * 1024; + mem->buf = (uint32_t*) calloc(1, buf_size); + esp_fill_random(mem->buf, buf_size); + + spi_bus_config_t bus_cfg = { + .mosi_io_num = SDSPI_MOSI_PIN, + .miso_io_num = SDSPI_MISO_PIN, + .sclk_io_num = SDSPI_CLK_PIN, + .quadwp_io_num = -1, + .quadhd_io_num = -1, + .max_transfer_sz = 4000, + }; + esp_err_t err = spi_bus_initialize(SDSPI_HOST_ID, &bus_cfg, SPI_DMA_CHAN); + TEST_ESP_OK(err); +} + +static void test_teardown_sdspi(sdspi_mem_t* mem) +{ + free(mem->buf); + spi_bus_free(SDSPI_HOST_ID); + HEAP_SIZE_CHECK(mem->heap_size, 0); +} + +TEST_CASE("(SDSPI) write/read speed test", "[fatfs][sdspi]") +{ + sdspi_mem_t mem; + size_t file_size = 1 * 1024 * 1024; + + test_setup_sdspi(&mem); + + sdspi_speed_test(mem.buf, 4 * 1024, file_size, true); + sdspi_speed_test(mem.buf, 8 * 1024, file_size, true); + sdspi_speed_test(mem.buf, 16 * 1024, file_size, true); + + sdspi_speed_test(mem.buf, 4 * 1024, file_size, false); + sdspi_speed_test(mem.buf, 8 * 1024, file_size, false); + sdspi_speed_test(mem.buf, 16 * 1024, file_size, false); + + test_teardown_sdspi(&mem); +} + +static void sdspi_speed_test(void *buf, size_t buf_size, size_t file_size, bool write) +{ + const char path[] = "/sdcard"; + sdmmc_card_t *card; + card = NULL; + sdspi_device_config_t device_cfg = { + .gpio_cs = SDSPI_CS_PIN, + .host_id = SDSPI_HOST_ID, + .gpio_cd = SDSPI_SLOT_NO_CD, + .gpio_wp = SDSPI_SLOT_NO_WP, + .gpio_int = SDSPI_SLOT_NO_INT, + }; + + sdmmc_host_t host = SDSPI_HOST_DEFAULT(); + host.slot = SDSPI_HOST_ID; + esp_vfs_fat_sdmmc_mount_config_t mount_config = { + .format_if_mount_failed = write, + .max_files = 5, + .allocation_unit_size = 64 * 1024 + }; + TEST_ESP_OK(esp_vfs_fat_sdspi_mount(path, &host, &device_cfg, &mount_config, &card)); + + test_fatfs_rw_speed("/sdcard/4mb.bin", buf, buf_size, file_size, write); + + TEST_ESP_OK(esp_vfs_fat_sdcard_unmount(path, card)); +} + +TEST_CASE("(SDSPI) can get partition info", "[fatfs][sdspi]") +{ + sdspi_mem_t mem; + + test_setup_sdspi(&mem); + + const char path[] = "/sdcard"; + sdmmc_card_t *card; + card = NULL; + sdspi_device_config_t device_cfg = { + .gpio_cs = SDSPI_CS_PIN, + .host_id = SDSPI_HOST_ID, + .gpio_cd = SDSPI_SLOT_NO_CD, + .gpio_wp = SDSPI_SLOT_NO_WP, + .gpio_int = SDSPI_SLOT_NO_INT, + }; + + sdmmc_host_t host = SDSPI_HOST_DEFAULT(); + host.slot = SDSPI_HOST_ID; + esp_vfs_fat_sdmmc_mount_config_t mount_config = { + .format_if_mount_failed = true, + .max_files = 5, + .allocation_unit_size = 64 * 1024 + }; + TEST_ESP_OK(esp_vfs_fat_sdspi_mount(path, &host, &device_cfg, &mount_config, &card)); + + test_fatfs_info("/sdcard", "/sdcard/test.txt"); + + TEST_ESP_OK(esp_vfs_fat_sdcard_unmount(path, card)); + + test_teardown_sdspi(&mem); +} + +#endif //TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) diff --git a/components/fatfs/test_apps/sdcard/partitions.csv b/components/fatfs/test_apps/sdcard/partitions.csv new file mode 100644 index 0000000000..a929971141 --- /dev/null +++ b/components/fatfs/test_apps/sdcard/partitions.csv @@ -0,0 +1,3 @@ +# Name, Type, SubType, Offset, Size, Flags +factory, app, factory, 0x10000, 1M, +storage, data, fat, , 528k, diff --git a/components/fatfs/test_apps/sdcard/pytest_fatfs_sdcard.py b/components/fatfs/test_apps/sdcard/pytest_fatfs_sdcard.py new file mode 100644 index 0000000000..4ec667dd14 --- /dev/null +++ b/components/fatfs/test_apps/sdcard/pytest_fatfs_sdcard.py @@ -0,0 +1,75 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +import pytest +from pytest_embedded import Dut + + +@pytest.mark.esp32 +@pytest.mark.sdcard_sdmode +@pytest.mark.parametrize( + 'config', + [ + 'default', + 'release', + ] +) +def test_fatfs_sdcard_generic_sdmmc(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('') + dut.expect_exact('Enter test for running.') + dut.write('[sdmmc]') + dut.expect_unity_test_output() + + +@pytest.mark.esp32 +@pytest.mark.esp32s2 +@pytest.mark.esp32c3 +@pytest.mark.sdcard_spimode +@pytest.mark.parametrize( + 'config', + [ + 'default', + 'release', + ] +) +def test_fatfs_sdcard_generic_sdspi(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('') + dut.expect_exact('Enter test for running.') + dut.write('[sdspi]') + dut.expect_unity_test_output() + + +@pytest.mark.esp32 +@pytest.mark.sdcard_sdmode +@pytest.mark.psram +@pytest.mark.parametrize( + 'config', + [ + 'psram', + ] +) +def test_fatfs_sdcard_psram_sdmmc(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('') + dut.expect_exact('Enter test for running.') + dut.write('[sdmmc]') + dut.expect_unity_test_output() + + +@pytest.mark.esp32 +@pytest.mark.sdcard_spimode +@pytest.mark.psram +@pytest.mark.parametrize( + 'config', + [ + 'psram', + ] +) +def test_fatfs_sdcard_psram_sdspi(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('') + dut.expect_exact('Enter test for running.') + dut.write('[sdspi]') + dut.expect_unity_test_output() diff --git a/components/soc/esp32h2/include/soc/soc_ulp.h b/components/fatfs/test_apps/sdcard/sdkconfig.ci.default similarity index 100% rename from components/soc/esp32h2/include/soc/soc_ulp.h rename to components/fatfs/test_apps/sdcard/sdkconfig.ci.default diff --git a/components/fatfs/test_apps/sdcard/sdkconfig.ci.psram b/components/fatfs/test_apps/sdcard/sdkconfig.ci.psram new file mode 100644 index 0000000000..b3b45db94a --- /dev/null +++ b/components/fatfs/test_apps/sdcard/sdkconfig.ci.psram @@ -0,0 +1,3 @@ +CONFIG_SPIRAM=y +CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=0 +CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y diff --git a/components/fatfs/test_apps/sdcard/sdkconfig.ci.release b/components/fatfs/test_apps/sdcard/sdkconfig.ci.release new file mode 100644 index 0000000000..6a81ea9ab9 --- /dev/null +++ b/components/fatfs/test_apps/sdcard/sdkconfig.ci.release @@ -0,0 +1,2 @@ +CONFIG_COMPILER_OPTIMIZATION_SIZE=y +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y diff --git a/components/fatfs/test_apps/sdcard/sdkconfig.defaults b/components/fatfs/test_apps/sdcard/sdkconfig.defaults new file mode 100644 index 0000000000..862b5bd85a --- /dev/null +++ b/components/fatfs/test_apps/sdcard/sdkconfig.defaults @@ -0,0 +1,19 @@ +# General options for additional checks +CONFIG_HEAP_POISONING_COMPREHENSIVE=y +CONFIG_COMPILER_WARN_WRITE_STRINGS=y +CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y +CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y +CONFIG_COMPILER_STACK_CHECK_MODE_STRONG=y +CONFIG_COMPILER_STACK_CHECK=y + +# disable task watchdog since this app uses an interactive menu +CONFIG_ESP_TASK_WDT_INIT=n + +# some tests verify file name encoding +CONFIG_FATFS_API_ENCODING_UTF_8=y +CONFIG_FATFS_CODEPAGE_936=y + +# some of the tests verify concurrent operation of FAT partitions in +# an SD card and in Flash, so need to use a custom partition table. +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" diff --git a/components/fatfs/test_apps/test_fatfs_common/CMakeLists.txt b/components/fatfs/test_apps/test_fatfs_common/CMakeLists.txt new file mode 100644 index 0000000000..8f06878d30 --- /dev/null +++ b/components/fatfs/test_apps/test_fatfs_common/CMakeLists.txt @@ -0,0 +1,3 @@ +idf_component_register(SRCS "test_fatfs_common.c" + INCLUDE_DIRS "." + PRIV_REQUIRES unity fatfs vfs unity) diff --git a/components/fatfs/test/test_fatfs_common.c b/components/fatfs/test_apps/test_fatfs_common/test_fatfs_common.c similarity index 97% rename from components/fatfs/test/test_fatfs_common.c rename to components/fatfs/test_apps/test_fatfs_common/test_fatfs_common.c index b9f79c9783..c9b578868e 100644 --- a/components/fatfs/test/test_fatfs_common.c +++ b/components/fatfs/test_apps/test_fatfs_common/test_fatfs_common.c @@ -15,15 +15,11 @@ #include #include #include "unity.h" -#include "esp_log.h" -#include "esp_system.h" #include "esp_vfs.h" #include "esp_vfs_fat.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" -#include "ff.h" #include "test_fatfs_common.h" -#include "esp_rom_sys.h" const char* fatfs_test_hello_str = "Hello, World!\n"; const char* fatfs_test_hello_str_utf = "世界，你好ï¼\n"; @@ -780,9 +776,9 @@ typedef struct { const char* filename; bool write; size_t word_count; - int seed; + unsigned seed; SemaphoreHandle_t done; - int result; + esp_err_t result; } read_write_test_arg_t; #define READ_WRITE_TEST_ARG_INIT(name, seed_) \ @@ -805,19 +801,19 @@ static void read_write_task(void* param) srand(args->seed); for (size_t i = 0; i < args->word_count; ++i) { - uint32_t val = rand(); + unsigned val = rand(); if (args->write) { int cnt = fwrite(&val, sizeof(val), 1, f); if (cnt != 1) { - esp_rom_printf("E(w): i=%d, cnt=%d val=%d\n\n", i, cnt, val); + printf("E(w): i=%d, cnt=%d val=0x08%x\n", i, cnt, val); args->result = ESP_FAIL; goto close; } } else { - uint32_t rval; + unsigned rval; int cnt = fread(&rval, sizeof(rval), 1, f); if (cnt != 1 || rval != val) { - esp_rom_printf("E(r): i=%d, cnt=%d rval=%d val=%d\n\n", i, cnt, rval, val); + printf("E(r): i=%d, cnt=%d rval=0x08%x val=0x08%x\n", i, cnt, rval, val); args->result = ESP_FAIL; goto close; } @@ -891,6 +887,15 @@ void test_fatfs_concurrent(const char* filename_prefix) vSemaphoreDelete(args4.done); } +void test_leading_spaces(void){ + // fatfs should ignore leading and trailing whitespaces + // and files "/spiflash/ thelongfile.txt " and "/spiflash/thelongfile.txt" should be equivalent + // this feature is currently not implemented + FILE* f = fopen( "/spiflash/ thelongfile.txt ", "wb"); + fclose(f); + TEST_ASSERT_NULL(fopen("/spiflash/thelongfile.txt", "r")); +} + void test_fatfs_rw_speed(const char* filename, void* buf, size_t buf_size, size_t file_size, bool is_write) { const size_t buf_count = file_size / buf_size; diff --git a/components/fatfs/test/test_fatfs_common.h b/components/fatfs/test_apps/test_fatfs_common/test_fatfs_common.h similarity index 98% rename from components/fatfs/test/test_fatfs_common.h rename to components/fatfs/test_apps/test_fatfs_common/test_fatfs_common.h index 7d05da5680..8b2ed0ea32 100644 --- a/components/fatfs/test/test_fatfs_common.h +++ b/components/fatfs/test_apps/test_fatfs_common/test_fatfs_common.h @@ -65,6 +65,8 @@ void test_fatfs_opendir_readdir_rewinddir(const char* dir_prefix); void test_fatfs_opendir_readdir_rewinddir_utf_8(const char* dir_prefix); +void test_leading_spaces(void); + void test_fatfs_rw_speed(const char* filename, void* buf, size_t buf_size, size_t file_size, bool write); void test_fatfs_info(const char* base_path, const char* filepath); diff --git a/components/fatfs/test_fatfsgen/test_fatfsgen.py b/components/fatfs/test_fatfsgen/test_fatfsgen.py index 1f7d3b2983..5816991c0e 100755 --- a/components/fatfs/test_fatfsgen/test_fatfsgen.py +++ b/components/fatfs/test_fatfsgen/test_fatfsgen.py @@ -12,10 +12,15 @@ from test_utils import CFG, fill_sector, generate_test_dir_1, generate_test_dir_ sys.path.append(os.path.join(os.path.dirname(__file__), '..')) import fatfsgen # noqa E402 # pylint: disable=C0413 +from fatfs_utils.boot_sector import BootSector # noqa E402 # pylint: disable=C0413 +from fatfs_utils.cluster import Cluster # noqa E402 # pylint: disable=C0413 +from fatfs_utils.entry import Entry # noqa E402 # pylint: disable=C0413 from fatfs_utils.exceptions import InconsistentFATAttributes # noqa E402 # pylint: disable=C0413 +from fatfs_utils.exceptions import NotInitialized # noqa E402 # pylint: disable=C0413 from fatfs_utils.exceptions import TooLongNameException # noqa E402 # pylint: disable=C0413 from fatfs_utils.exceptions import WriteDirectoryException # noqa E402 # pylint: disable=C0413 from fatfs_utils.exceptions import LowerCaseException, NoFreeClusterException # noqa E402 # pylint: disable=C0413 +from fatfs_utils.utils import right_strip_string # noqa E402 # pylint: disable=C0413 from fatfs_utils.utils import FAT12, read_filesystem # noqa E402 # pylint: disable=C0413 @@ -311,11 +316,11 @@ class FatFSGen(unittest.TestCase): fatfs.create_file('HELLOHELLOHELLO', extension='TXT') fatfs.write_filesystem(CFG['output_file']) file_system = read_filesystem(CFG['output_file']) - self.assertEqual(file_system[0x2000: 0x2010], b'Bl\x00o\x00.\x00t\x00x\x00\x0f\x00\xb3t\x00') + self.assertEqual(file_system[0x2000: 0x2010], b'Bl\x00o\x00.\x00t\x00x\x00\x0f\x00\xadt\x00') self.assertEqual(file_system[0x2012: 0x2020], b'\xff\xff\xff\xff\xff\xff\xff\xff\x00\x00\xff\xff\xff\xff') - self.assertEqual(file_system[0x2020: 0x2030], b'\x01h\x00e\x00l\x00l\x00o\x00\x0f\x00\xb3h\x00') + self.assertEqual(file_system[0x2020: 0x2030], b'\x01h\x00e\x00l\x00l\x00o\x00\x0f\x00\xadh\x00') self.assertEqual(file_system[0x2030: 0x2040], b'e\x00l\x00l\x00o\x00h\x00\x00\x00e\x00l\x00') - self.assertEqual(file_system[0x2040: 0x2050], b'HELLOH~1TXT \x00\x00\x00\x00') + self.assertEqual(file_system[0x2040: 0x2050], b'HELLOH~\x01TXT \x00\x00\x00\x00') self.assertEqual(file_system[0x2050: 0x2060], b'!\x00!\x00\x00\x00\x00\x00!\x00\x02\x00\x00\x00\x00\x00') def test_lfn_plain_name(self) -> None: @@ -324,11 +329,11 @@ class FatFSGen(unittest.TestCase): fatfs.write_content(path_from_root=['HELLOHELLOHELLO.TXT'], content=b'this is a test') fatfs.write_filesystem(CFG['output_file']) file_system = read_filesystem(CFG['output_file']) - self.assertEqual(file_system[0x2000: 0x2010], b'Bl\x00o\x00.\x00t\x00x\x00\x0f\x00\xb3t\x00') + self.assertEqual(file_system[0x2000: 0x2010], b'Bl\x00o\x00.\x00t\x00x\x00\x0f\x00\xadt\x00') self.assertEqual(file_system[0x2012: 0x2020], b'\xff\xff\xff\xff\xff\xff\xff\xff\x00\x00\xff\xff\xff\xff') - self.assertEqual(file_system[0x2020: 0x2030], b'\x01h\x00e\x00l\x00l\x00o\x00\x0f\x00\xb3h\x00') + self.assertEqual(file_system[0x2020: 0x2030], b'\x01h\x00e\x00l\x00l\x00o\x00\x0f\x00\xadh\x00') self.assertEqual(file_system[0x2030: 0x2040], b'e\x00l\x00l\x00o\x00h\x00\x00\x00e\x00l\x00') - self.assertEqual(file_system[0x2040: 0x2050], b'HELLOH~1TXT \x00\x00\x00\x00') + self.assertEqual(file_system[0x2040: 0x2050], b'HELLOH~\x01TXT \x00\x00\x00\x00') self.assertEqual(file_system[0x2050: 0x2060], b'!\x00!\x00\x00\x00\x00\x00!\x00\x02\x00\x0e\x00\x00\x00') self.assertEqual(file_system[0x6000: 0x6010], b'this is a test\x00\x00') @@ -338,11 +343,11 @@ class FatFSGen(unittest.TestCase): fatfs.write_content(path_from_root=['HELLOHELLOHELLO'], content=b'this is a test') fatfs.write_filesystem(CFG['output_file']) file_system = read_filesystem(CFG['output_file']) - self.assertEqual(file_system[0x2000: 0x2010], b'Bl\x00o\x00\x00\x00\xff\xff\xff\xff\x0f\x00V\xff\xff') + self.assertEqual(file_system[0x2000: 0x2010], b'Bl\x00o\x00\x00\x00\xff\xff\xff\xff\x0f\x00P\xff\xff') self.assertEqual(file_system[0x2012: 0x2020], b'\xff\xff\xff\xff\xff\xff\xff\xff\x00\x00\xff\xff\xff\xff') - self.assertEqual(file_system[0x2020: 0x2030], b'\x01h\x00e\x00l\x00l\x00o\x00\x0f\x00Vh\x00') + self.assertEqual(file_system[0x2020: 0x2030], b'\x01h\x00e\x00l\x00l\x00o\x00\x0f\x00Ph\x00') self.assertEqual(file_system[0x2030: 0x2040], b'e\x00l\x00l\x00o\x00h\x00\x00\x00e\x00l\x00') - self.assertEqual(file_system[0x2040: 0x2050], b'HELLOH~1 \x00\x00\x00\x00') + self.assertEqual(file_system[0x2040: 0x2050], b'HELLOH~\x01 \x00\x00\x00\x00') self.assertEqual(file_system[0x2050: 0x2060], b'!\x00!\x00\x00\x00\x00\x00!\x00\x02\x00\x0e\x00\x00\x00') self.assertEqual(file_system[0x6000: 0x6010], b'this is a test\x00\x00') @@ -356,11 +361,11 @@ class FatFSGen(unittest.TestCase): fatfs.create_file('HELLO', extension='TXT', path_from_root=['VERYLONGTESTFOLD']) fatfs.write_filesystem(CFG['output_file']) file_system = read_filesystem(CFG['output_file']) - self.assertEqual(file_system[0x2000: 0x2010], b'Bo\x00l\x00d\x00\x00\x00\xff\xff\x0f\x00\xa6\xff\xff') + self.assertEqual(file_system[0x2000: 0x2010], b'Bo\x00l\x00d\x00\x00\x00\xff\xff\x0f\x00\xa0\xff\xff') self.assertEqual(file_system[0x2012: 0x2020], b'\xff\xff\xff\xff\xff\xff\xff\xff\x00\x00\xff\xff\xff\xff') - self.assertEqual(file_system[0x2020: 0x2030], b'\x01v\x00e\x00r\x00y\x00l\x00\x0f\x00\xa6o\x00') + self.assertEqual(file_system[0x2020: 0x2030], b'\x01v\x00e\x00r\x00y\x00l\x00\x0f\x00\xa0o\x00') self.assertEqual(file_system[0x2030: 0x2040], b'n\x00g\x00t\x00e\x00s\x00\x00\x00t\x00f\x00') - self.assertEqual(file_system[0x2040: 0x2050], b'VERYLO~1 \x10\x00\x00\x00\x00') + self.assertEqual(file_system[0x2040: 0x2050], b'VERYLO~\x01 \x10\x00\x00\x00\x00') self.assertEqual(file_system[0x2050: 0x2060], b'!\x00!\x00\x00\x00\x00\x00!\x00\x02\x00\x00\x00\x00\x00') self.assertEqual(file_system[0x6000: 0x6010], b'. \x10\x00\x00\x00\x00') @@ -377,18 +382,18 @@ class FatFSGen(unittest.TestCase): fatfs.write_filesystem(CFG['output_file']) file_system = read_filesystem(CFG['output_file']) - self.assertEqual(file_system[0x2000: 0x2010], b'Bo\x00l\x00d\x00\x00\x00\xff\xff\x0f\x00\x10\xff\xff') + self.assertEqual(file_system[0x2000: 0x2010], b'Bo\x00l\x00d\x00\x00\x00\xff\xff\x0f\x00\n\xff\xff') self.assertEqual(file_system[0x2012: 0x2020], b'\xff\xff\xff\xff\xff\xff\xff\xff\x00\x00\xff\xff\xff\xff') - self.assertEqual(file_system[0x2020: 0x2030], b'\x01v\x00e\x00r\x00y\x00l\x00\x0f\x00\x10o\x00') + self.assertEqual(file_system[0x2020: 0x2030], b'\x01v\x00e\x00r\x00y\x00l\x00\x0f\x00\no\x00') self.assertEqual(file_system[0x2030: 0x2040], b'n\x00g\x00t\x00e\x00s\x00\x00\x00t\x00f\x00') - self.assertEqual(file_system[0x2040: 0x2050], b'verylo~1 \x10\x00\x00\x00\x00') + self.assertEqual(file_system[0x2040: 0x2050], b'verylo~\x01 \x10\x00\x00\x00\x00') self.assertEqual(file_system[0x2050: 0x2060], b'!\x00!\x00\x00\x00\x00\x00!\x00\x02\x00\x00\x00\x00\x00') self.assertEqual(file_system[0x6000: 0x6010], b'. \x10\x00\x00\x00\x00') self.assertEqual(file_system[0x6012: 0x6020], b'!\x00\x00\x00\x00\x00!\x00\x02\x00\x00\x00\x00\x00') self.assertEqual(file_system[0x6020: 0x6030], b'.. \x10\x00\x00\x00\x00') self.assertEqual(file_system[0x6030: 0x6040], b'!\x00!\x00\x00\x00\x00\x00!\x00\x01\x00\x00\x00\x00\x00') - self.assertEqual(file_system[0x6040: 0x6050], b'Bl\x00o\x00.\x00t\x00x\x00\x0f\x00\xd5t\x00') + self.assertEqual(file_system[0x6040: 0x6050], b'Bl\x00o\x00.\x00t\x00x\x00\x0f\x00\xcft\x00') self.assertEqual(file_system[0x6050: 0x6060], b'\x00\x00\xff\xff\xff\xff\xff\xff\xff\xff\x00\x00\xff\xff\xff\xff') @@ -399,11 +404,11 @@ class FatFSGen(unittest.TestCase): fatfs.write_content(path_from_root=['VERYLONGTESTFOLD', 'HELLO.TXT'], content=b'this is a test') fatfs.write_filesystem(CFG['output_file']) file_system = read_filesystem(CFG['output_file']) - self.assertEqual(file_system[0x2000: 0x2010], b'Bo\x00l\x00d\x00\x00\x00\xff\xff\x0f\x00\xa6\xff\xff') + self.assertEqual(file_system[0x2000: 0x2010], b'Bo\x00l\x00d\x00\x00\x00\xff\xff\x0f\x00\xa0\xff\xff') self.assertEqual(file_system[0x2012: 0x2020], b'\xff\xff\xff\xff\xff\xff\xff\xff\x00\x00\xff\xff\xff\xff') - self.assertEqual(file_system[0x2020: 0x2030], b'\x01v\x00e\x00r\x00y\x00l\x00\x0f\x00\xa6o\x00') + self.assertEqual(file_system[0x2020: 0x2030], b'\x01v\x00e\x00r\x00y\x00l\x00\x0f\x00\xa0o\x00') self.assertEqual(file_system[0x2030: 0x2040], b'n\x00g\x00t\x00e\x00s\x00\x00\x00t\x00f\x00') - self.assertEqual(file_system[0x2040: 0x2050], b'VERYLO~1 \x10\x00\x00\x00\x00') + self.assertEqual(file_system[0x2040: 0x2050], b'VERYLO~\x01 \x10\x00\x00\x00\x00') self.assertEqual(file_system[0x2050: 0x2060], b'!\x00!\x00\x00\x00\x00\x00!\x00\x02\x00\x00\x00\x00\x00') self.assertEqual(file_system[0x6000: 0x6010], b'. \x10\x00\x00\x00\x00') @@ -447,31 +452,83 @@ class FatFSGen(unittest.TestCase): fatfs.write_filesystem(CFG['output_file']) file_system = read_filesystem(CFG['output_file']) - self.assertEqual(file_system[0x2000: 0x2010], b'Bo\x00l\x00d\x00\x00\x00\xff\xff\x0f\x00\xa6\xff\xff') + self.assertEqual(file_system[0x2000: 0x2010], b'Bo\x00l\x00d\x00\x00\x00\xff\xff\x0f\x00\xa0\xff\xff') self.assertEqual(file_system[0x2011: 0x2020], b'\xff\xff\xff\xff\xff\xff\xff\xff\xff\x00\x00\xff\xff\xff\xff') - self.assertEqual(file_system[0x2020: 0x2030], b'\x01v\x00e\x00r\x00y\x00l\x00\x0f\x00\xa6o\x00') + self.assertEqual(file_system[0x2020: 0x2030], b'\x01v\x00e\x00r\x00y\x00l\x00\x0f\x00\xa0o\x00') self.assertEqual(file_system[0x2030: 0x2040], b'n\x00g\x00t\x00e\x00s\x00\x00\x00t\x00f\x00') - self.assertEqual(file_system[0x2040: 0x2050], b'VERYLO~1 \x10\x00\x00\x00\x00') + self.assertEqual(file_system[0x2040: 0x2050], b'VERYLO~\x01 \x10\x00\x00\x00\x00') self.assertEqual(file_system[0x2050: 0x2060], b'!\x00!\x00\x00\x00\x00\x00!\x00\x02\x00\x00\x00\x00\x00') self.assertEqual(file_system[0x6000: 0x6010], b'. \x10\x00\x00\x00\x00') self.assertEqual(file_system[0x6011: 0x6020], b'\x00!\x00\x00\x00\x00\x00!\x00\x02\x00\x00\x00\x00\x00') self.assertEqual(file_system[0x6020: 0x6030], b'.. \x10\x00\x00\x00\x00') self.assertEqual(file_system[0x6030: 0x6040], b'!\x00!\x00\x00\x00\x00\x00!\x00\x01\x00\x00\x00\x00\x00') - self.assertEqual(file_system[0x6040: 0x6050], b'Bl\x00o\x00o\x00o\x00o\x00\x0f\x00\xb3o\x00') + self.assertEqual(file_system[0x6040: 0x6050], b'Bl\x00o\x00o\x00o\x00o\x00\x0f\x00\xado\x00') self.assertEqual(file_system[0x6050: 0x6060], b'o\x00o\x00.\x00t\x00x\x00\x00\x00t\x00\x00\x00') self.assertEqual(file_system[0x6050: 0x6060], b'o\x00o\x00.\x00t\x00x\x00\x00\x00t\x00\x00\x00') - self.assertEqual(file_system[0x6060: 0x6070], b'\x01h\x00e\x00l\x00l\x00o\x00\x0f\x00\xb3h\x00') + self.assertEqual(file_system[0x6060: 0x6070], b'\x01h\x00e\x00l\x00l\x00o\x00\x0f\x00\xadh\x00') self.assertEqual(file_system[0x6070: 0x6080], b'e\x00l\x00l\x00o\x00h\x00\x00\x00e\x00l\x00') - self.assertEqual(file_system[0x6080: 0x6090], b'HELLOH~1TXT \x00\x00\x00\x00') + self.assertEqual(file_system[0x6080: 0x6090], b'HELLOH~\x01TXT \x00\x00\x00\x00') self.assertEqual(file_system[0x6090: 0x60a0], b'!\x00!\x00\x00\x00\x00\x00!\x00\x03\x00\x10\x00\x00\x00') - self.assertEqual(file_system[0x60a0: 0x60b0], b'Bl\x00o\x00o\x00o\x00o\x00\x0f\x00\x93o\x00') + self.assertEqual(file_system[0x60a0: 0x60b0], b'Bl\x00o\x00o\x00o\x00o\x00\x0f\x00\x8do\x00') self.assertEqual(file_system[0x60b0: 0x60c0], b'o\x00b\x00.\x00t\x00x\x00\x00\x00t\x00\x00\x00') - self.assertEqual(file_system[0x60c0: 0x60d0], b'\x01h\x00e\x00l\x00l\x00o\x00\x0f\x00\x93h\x00') + self.assertEqual(file_system[0x60c0: 0x60d0], b'\x01h\x00e\x00l\x00l\x00o\x00\x0f\x00\x8dh\x00') self.assertEqual(file_system[0x60d0: 0x60e0], b'e\x00l\x00l\x00o\x00h\x00\x00\x00e\x00l\x00') - self.assertEqual(file_system[0x60e0: 0x60f0], b'HELLOH~2TXT \x00\x00\x00\x00') + self.assertEqual(file_system[0x60e0: 0x60f0], b'HELLOH~\x02TXT \x00\x00\x00\x00') + + def test_bs_not_initialized(self) -> None: + self.assertEqual(str(BootSector()), 'Boot sector is not initialized!') + self.assertRaises(NotInitialized, BootSector().generate_boot_sector) + self.assertRaises(NotInitialized, lambda: BootSector().binary_image) # encapsulate property to callable + + def test_bs_str(self) -> None: + fatfs = fatfsgen.FATFS() + bs = BootSector(fatfs.state.boot_sector_state) + bs.generate_boot_sector() + bs.parse_boot_sector(bs.binary_image) + x = 'FATFS properties:,clusters: 252,data_region_start: 24576,data_sectors: ' \ + '250,entries_root_count: 512,fat_table_start_address: 4096,fat_tables_cnt: 1,' \ + 'fatfs_type: 12,file_sys_type: FAT ,hidden_sectors: 0,media_type: 248,' \ + 'non_data_sectors: 6,num_heads: 255,oem_name: MSDOS5.0,reserved_sectors_cnt: 1,' \ + 'root_dir_sectors_cnt: 4,root_directory_start: 8192,sec_per_track: 63,sector_size: 4096,' \ + 'sectors_count: 256,sectors_per_cluster: 1,sectors_per_fat_cnt: 1,size: 1048576,' \ + 'volume_label: Espressif ,volume_uuid: 1144419653,' + self.assertEqual(x.split(',')[:-2], str(bs).split('\n')[:-2]) # except for volume id + + def test_parsing_error(self) -> None: + self.assertRaises(NotInitialized, BootSector().parse_boot_sector, b'') + + def test_not_implemented_fat32(self) -> None: + self.assertEqual( + Entry.get_cluster_id( + Entry.ENTRY_FORMAT_SHORT_NAME.parse( + bytearray(b'AHOJ \x18\x00\xb0[&U&U\x00\x00\xb0[&U\x02\x00\x08\x00\x00\x00'))), + 2) + + def test_get_cluster_value_from_fat(self) -> None: + fatfs = fatfsgen.FATFS() + self.assertEqual(fatfs.fat.get_cluster_value(1), 0xFFF) + + def test_is_cluster_last(self) -> None: + fatfs = fatfsgen.FATFS() + self.assertEqual(fatfs.fat.is_cluster_last(2), False) + + def test_chain_in_fat(self) -> None: + fatfs = fatfsgen.FATFS() + self.assertEqual(fatfs.fat.get_chained_content(1), b'\x00' * 0x1000) + + def test_retrieve_file_chaining(self) -> None: + fatfs = fatfsgen.FATFS() + fatfs.create_file('WRITEF', extension='TXT') + fatfs.write_content(path_from_root=['WRITEF.TXT'], content=CFG['sector_size'] * b'a' + b'a') + fatfs.write_filesystem(CFG['output_file']) + self.assertEqual(fatfs.fat.get_chained_content(1)[:15], b'WRITEF TXT \x00\x00\x00') + self.assertEqual(fatfs.fat.get_chained_content(2)[:15], b'aaaaaaaaaaaaaaa') + + def test_lstrip(self) -> None: + self.assertEqual(right_strip_string('\x20\x20\x20thisistest\x20\x20\x20'), ' thisistest') if __name__ == '__main__': diff --git a/components/fatfs/test_fatfsgen/test_fatfsparse.py b/components/fatfs/test_fatfsgen/test_fatfsparse.py index 648926ca44..15a7f3d866 100755 --- a/components/fatfs/test_fatfsgen/test_fatfsparse.py +++ b/components/fatfs/test_fatfsgen/test_fatfsparse.py @@ -12,6 +12,7 @@ from test_utils import compare_folders, fill_sector, generate_local_folder_struc sys.path.append(os.path.join(os.path.dirname(__file__), '..')) import fatfsgen # noqa E402 # pylint: disable=C0413 +from fatfs_utils.entry import Entry # noqa E402 # pylint: disable=C0413 class FatFSGen(unittest.TestCase): @@ -146,7 +147,7 @@ class FatFSGen(unittest.TestCase): f'{os.path.join(os.path.dirname(__file__), "..", "wl_fatfsgen.py")}', 'testf' ], stderr=STDOUT) - run(['python', '../fatfsparse.py', '--wear-leveling', 'fatfs_image.img'], stderr=STDOUT) + run(['python', '../fatfsparse.py', 'fatfs_image.img'], stderr=STDOUT) assert compare_folders('testf', 'Espressif') def test_e2e_deeper(self) -> None: @@ -185,7 +186,7 @@ class FatFSGen(unittest.TestCase): f'{os.path.join(os.path.dirname(__file__), "..", "wl_fatfsgen.py")}', 'testf' ], stderr=STDOUT) - run(['python', '../fatfsparse.py', '--wear-leveling', 'fatfs_image.img'], stderr=STDOUT) + run(['python', '../fatfsparse.py', 'fatfs_image.img'], stderr=STDOUT) assert compare_folders('testf', 'Espressif') def test_e2e_deeper_large(self) -> None: @@ -241,7 +242,7 @@ class FatFSGen(unittest.TestCase): f'{os.path.join(os.path.dirname(__file__), "..", "wl_fatfsgen.py")}', 'testf' ], stderr=STDOUT) - run(['python', '../fatfsparse.py', '--wear-leveling', 'fatfs_image.img'], stderr=STDOUT) + run(['python', '../fatfsparse.py', 'fatfs_image.img'], stderr=STDOUT) assert compare_folders('testf', 'Espressif') def test_e2e_very_deep(self) -> None: @@ -320,9 +321,34 @@ class FatFSGen(unittest.TestCase): f'{os.path.join(os.path.dirname(__file__), "..", "fatfsgen.py")}', 'testf', '--long_name_support' ], stderr=STDOUT) - run(['python', '../fatfsparse.py', 'fatfs_image.img', '--long-name-support'], stderr=STDOUT) + run(['python', '../fatfsparse.py', 'fatfs_image.img'], stderr=STDOUT) assert compare_folders('testf', 'Espressif') + def test_parse_long_name(self) -> None: + self.assertEqual( + Entry.parse_entry_long( + b'\x01t\x00h\x00i\x00s\x00_\x00\x0f\x00\xfbi\x00s\x00_\x00l\x00o\x00n\x00\x00\x00g\x00_\x00', 251), + { + 'order': 1, + 'name1': b't\x00h\x00i\x00s\x00_\x00', + 'name2': b'i\x00s\x00_\x00l\x00o\x00n\x00', + 'name3': b'g\x00_\x00', + 'is_last': False + } + ) + self.assertEqual( + Entry.parse_entry_long( + b'\x01t\x00h\x00i\x00s\x00_\x00\x0f\x00\xfbi\x00s\x00_\x00l\x00o\x00n\x00\x00\x00g\x00_\x00', 252 + ), + {} + ) + self.assertEqual( + Entry.parse_entry_long( + b'\x01t\x00h\x00i\x00s\x00_\x00\x0f\x01\xfbi\x00s\x00_\x00l\x00o\x00n\x00\x00\x00g\x00_\x00', 251 + ), + {} + ) + if __name__ == '__main__': unittest.main() diff --git a/components/fatfs/test_fatfsgen/test_wl_fatfsgen.py b/components/fatfs/test_fatfsgen/test_wl_fatfsgen.py index e39d7cd8c4..2b3e28c7eb 100755 --- a/components/fatfs/test_fatfsgen/test_wl_fatfsgen.py +++ b/components/fatfs/test_fatfsgen/test_wl_fatfsgen.py @@ -25,7 +25,7 @@ class WLFatFSGen(unittest.TestCase): def test_empty_file_sn_fat12(self) -> None: fatfs = wl_fatfsgen.WLFATFS() - fatfs.wl_create_file('TESTFILE') + fatfs.plain_fatfs.create_file('TESTFILE') fatfs.init_wl() fatfs.wl_write_filesystem(CFG['output_file']) with open(CFG['output_file'], 'rb') as fs_file: @@ -36,7 +36,7 @@ class WLFatFSGen(unittest.TestCase): def test_directory_sn_fat12(self) -> None: fatfs = wl_fatfsgen.WLFATFS(device_id=3750448905) - fatfs.wl_create_directory('TESTFOLD') + fatfs.plain_fatfs.create_directory('TESTFOLD') fatfs.init_wl() fatfs.wl_write_filesystem(CFG['output_file']) @@ -73,7 +73,7 @@ class WLFatFSGen(unittest.TestCase): def test_directory_sn_fat122mb(self) -> None: fatfs = wl_fatfsgen.WLFATFS(device_id=3750448905, size=2 * 1024 * 1024) - fatfs.wl_create_directory('TESTFOLD') + fatfs.plain_fatfs.create_directory('TESTFOLD') fatfs.init_wl() fatfs.wl_write_filesystem(CFG['output_file']) @@ -102,12 +102,12 @@ class WLFatFSGen(unittest.TestCase): def test_write_not_initialized_wlfatfs(self) -> None: fatfs = wl_fatfsgen.WLFATFS() - fatfs.wl_create_directory('TESTFOLD') + fatfs.plain_fatfs.create_directory('TESTFOLD') self.assertRaises(WLNotInitialized, fatfs.wl_write_filesystem, CFG['output_file']) def test_e2e_deep_folder_into_image_ext(self) -> None: fatfs = wl_fatfsgen.WLFATFS() - fatfs.wl_generate(CFG['test_dir2']) + fatfs.plain_fatfs.generate(CFG['test_dir2']) fatfs.init_wl() fatfs.wl_write_filesystem(CFG['output_file']) with open(CFG['output_file'], 'rb') as fs_file: @@ -124,7 +124,7 @@ class WLFatFSGen(unittest.TestCase): def test_e2e_deep_folder_into_image(self) -> None: fatfs = wl_fatfsgen.WLFATFS() - fatfs.wl_generate(CFG['test_dir']) + fatfs.plain_fatfs.generate(CFG['test_dir']) fatfs.init_wl() fatfs.wl_write_filesystem(CFG['output_file']) with open(CFG['output_file'], 'rb') as fs_file: diff --git a/components/fatfs/wl_fatfsgen.py b/components/fatfs/wl_fatfsgen.py index 827dfe72a1..4a685434a0 100755 --- a/components/fatfs/wl_fatfsgen.py +++ b/components/fatfs/wl_fatfsgen.py @@ -2,8 +2,6 @@ # SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 -from typing import List, Optional - from construct import Const, Int32ul, Struct from fatfs_utils.exceptions import WLNotInitialized from fatfs_utils.utils import (FULL_BYTE, UINT32_MAX, FATDefaults, crc32, generate_4bytes_random, @@ -82,6 +80,7 @@ class WLFATFS: def __init__(self, size: int = FATDefaults.SIZE, + sector_size: int = FATDefaults.SECTOR_SIZE, reserved_sectors_cnt: int = FATDefaults.RESERVED_SECTORS_COUNT, fat_tables_cnt: int = FATDefaults.FAT_TABLES_COUNT, sectors_per_cluster: int = FATDefaults.SECTORS_PER_CLUSTER, @@ -122,7 +121,7 @@ class WLFATFS: reserved_sectors_cnt=reserved_sectors_cnt, fat_tables_cnt=fat_tables_cnt, sectors_per_cluster=sectors_per_cluster, - sector_size=FATDefaults.WL_SECTOR_SIZE, + sector_size=sector_size, root_entry_count=root_entry_count, hidden_sectors=hidden_sectors, long_names_enabled=long_names_enabled, @@ -199,33 +198,18 @@ class WLFATFS: with open(output_path, 'wb') as output: output.write(bytearray(self.fatfs_binary_image)) - def wl_generate(self, input_directory: str) -> None: - """ - Normalize path to folder and recursively encode folder to binary image - """ - self.plain_fatfs.generate(input_directory=input_directory) - - def wl_create_file(self, name: str, extension: str = '', path_from_root: Optional[List[str]] = None) -> None: - self.plain_fatfs.create_file(name, extension, path_from_root) - - def wl_create_directory(self, name: str, path_from_root: Optional[List[str]] = None) -> None: - self.plain_fatfs.create_directory(name, path_from_root) - - def wl_write_content(self, path_from_root: List[str], content: bytes) -> None: - self.plain_fatfs.write_content(path_from_root, content) - if __name__ == '__main__': desc = 'Create a FAT filesystem with support for wear levelling and populate it with directory content' - args = get_args_for_partition_generator(desc) - + args = get_args_for_partition_generator(desc, wl=True) wl_fatfs = WLFATFS(sectors_per_cluster=args.sectors_per_cluster, size=args.partition_size, + sector_size=args.sector_size, root_entry_count=args.root_entry_count, explicit_fat_type=args.fat_type, long_names_enabled=args.long_name_support, use_default_datetime=args.use_default_datetime) - wl_fatfs.wl_generate(args.input_directory) + wl_fatfs.plain_fatfs.generate(args.input_directory) wl_fatfs.init_wl() wl_fatfs.wl_write_filesystem(args.output_file) diff --git a/components/freertos/CMakeLists.txt b/components/freertos/CMakeLists.txt index b62e112596..8eda6517a7 100644 --- a/components/freertos/CMakeLists.txt +++ b/components/freertos/CMakeLists.txt @@ -6,6 +6,43 @@ endif() idf_build_get_property(target IDF_TARGET) +if(${target} STREQUAL "linux") + set(kernel_dir "FreeRTOS-Kernel") + set(srcs + "${kernel_dir}/portable/linux/port.c" + "${kernel_dir}/portable/linux/port_idf.c" + "${kernel_dir}/portable/linux/utils/wait_for_event.c" + "${kernel_dir}/list.c" + "${kernel_dir}/queue.c" + "${kernel_dir}/tasks.c" + "${kernel_dir}/timers.c" + ) + + set(include_dirs + ${kernel_dir}/include + ${kernel_dir}/portable/linux/include # For arch-specific FreeRTOSConfig_arch.h in portable//include + ${kernel_dir}/portable/linux/include/freertos + "esp_additions/include/freertos" # For config via #include "FreeRTOSConfig.h" + "esp_additions/include" # For #include "freertos/task_snapshot.h" and #include "freertos/FreeRTOSConfig.h" + ) + + set(private_include_dirs + ${kernel_dir}/portable/linux + ${kernel_dir}/portable/priv_include + ${kernel_dir}/include/freertos + . + ) + + idf_component_register(SRCS "${srcs}" + INCLUDE_DIRS ${include_dirs} + PRIV_INCLUDE_DIRS ${private_include_dirs}) + + target_compile_definitions(${COMPONENT_LIB} PUBLIC "projCOVERAGE_TEST=0") + target_link_libraries(${COMPONENT_LIB} PUBLIC pthread) + + return() +endif() + if(CONFIG_FREERTOS_SMP) set(ldfragments linker_smp.lf) if(CONFIG_IDF_TARGET_ARCH_XTENSA) @@ -140,7 +177,12 @@ idf_component_register(SRCS "${srcs}" PRIV_REQUIRES soc esp_pm) idf_component_get_property(COMPONENT_DIR freertos COMPONENT_DIR) -idf_component_set_property(freertos ORIG_INCLUDE_PATH "${COMPONENT_DIR}/include/freertos/") + +if(CONFIG_FREERTOS_SMP) + idf_component_set_property(freertos ORIG_INCLUDE_PATH "${COMPONENT_DIR}/FreeRTOS-Kernel-SMP/include/freertos/") +else() + idf_component_set_property(freertos ORIG_INCLUDE_PATH "${COMPONENT_DIR}/FreeRTOS-Kernel/include/freertos/") +endif() if(CONFIG_FREERTOS_DEBUG_OCDAWARE) target_link_libraries(${COMPONENT_LIB} INTERFACE "-Wl,--undefined=uxTopUsedPriority") #will be removed diff --git a/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/include/freertos/FreeRTOSConfig_smp.h b/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/include/freertos/FreeRTOSConfig_smp.h index 03c2e76d48..0728e7b10c 100644 --- a/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/include/freertos/FreeRTOSConfig_smp.h +++ b/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/include/freertos/FreeRTOSConfig_smp.h @@ -250,6 +250,18 @@ Default values for trace macros added by ESP-IDF and are not part of Vanilla Fre #define traceISR_ENTER(_n_) #endif +#ifndef traceQUEUE_GIVE_FROM_ISR + #define traceQUEUE_GIVE_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_GIVE_FROM_ISR_FAILED + #define traceQUEUE_GIVE_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_SEMAPHORE_RECEIVE + #define traceQUEUE_SEMAPHORE_RECEIVE( pxQueue ) +#endif + /* ------------------------------------------------ IDF Compatibility -------------------------------------------------- * - We need these in order for ESP-IDF to compile * ------------------------------------------------------------------------------------------------------------------ */ diff --git a/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/include/freertos/portmacro.h b/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/include/freertos/portmacro.h index f5a4057296..bce9f42258 100644 --- a/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/include/freertos/portmacro.h +++ b/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/include/freertos/portmacro.h @@ -9,7 +9,7 @@ #include "sdkconfig.h" #include #include "spinlock.h" -#include "soc/interrupt_core0_reg.h" +#include "soc/interrupt_reg.h" #include "esp_macros.h" #include "esp_cpu.h" #include "esp_private/crosscore_int.h" diff --git a/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c b/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c index 2474875022..32765d8a96 100644 --- a/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c +++ b/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c @@ -12,7 +12,7 @@ #include "hal/systimer_hal.h" #include "hal/systimer_ll.h" #include "riscv/rvruntime-frames.h" -#include "riscv/riscv_interrupts.h" +#include "riscv/rv_utils.h" #include "riscv/interrupt.h" #include "esp_private/crosscore_int.h" #include "esp_private/esp_int_wdt.h" @@ -107,7 +107,16 @@ void vPortSetStackWatchpoint(void *pxStackStart) BaseType_t xPortSysTickHandler(void); -#if CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER +#ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT + +#ifdef CONFIG_FREERTOS_CORETIMER_0 + #define SYSTICK_INTR_ID (ETS_INTERNAL_TIMER0_INTR_SOURCE+ETS_INTERNAL_INTR_SOURCE_OFF) +#endif +#ifdef CONFIG_FREERTOS_CORETIMER_1 + #define SYSTICK_INTR_ID (ETS_INTERNAL_TIMER1_INTR_SOURCE+ETS_INTERNAL_INTR_SOURCE_OFF) +#endif + +#elif CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER _Static_assert(SOC_CPU_CORES_NUM <= SOC_SYSTIMER_ALARM_NUM - 1, "the number of cores must match the number of core alarms in SYSTIMER"); @@ -243,7 +252,7 @@ static void main_task(void *args) #endif //Initialize task wdt if configured to do so -#if CONFIG_ESP_TASK_WDT +#if CONFIG_ESP_TASK_WDT_INIT esp_task_wdt_config_t twdt_config = { .timeout_ms = CONFIG_ESP_TASK_WDT_TIMEOUT_S * 1000, .idle_core_mask = 0, @@ -258,7 +267,7 @@ static void main_task(void *args) twdt_config.idle_core_mask |= (1 << 1); #endif ESP_ERROR_CHECK(esp_task_wdt_init(&twdt_config)); -#endif // CONFIG_ESP_TASK_WDT +#endif // CONFIG_ESP_TASK_WDT_INIT app_main(); vTaskDelete(NULL); @@ -266,7 +275,7 @@ static void main_task(void *args) void esp_startup_start_app_common(void) { -#if CONFIG_ESP_INT_WDT +#if CONFIG_ESP_INT_WDT_INIT esp_int_wdt_init(); //Initialize the interrupt watch dog for CPU0. esp_int_wdt_cpu_init(); @@ -397,7 +406,6 @@ void vPortYieldFromISR( void ) // ----------------- Scheduler Start/End ------------------- -extern void esprv_intc_int_set_threshold(int); // FIXME, this function is in ROM only BaseType_t xPortStartScheduler(void) { uxInterruptNesting = 0; @@ -408,7 +416,7 @@ BaseType_t xPortStartScheduler(void) vPortSetupTimer(); esprv_intc_int_set_threshold(1); /* set global INTC masking level */ - riscv_global_interrupts_enable(); + rv_utils_intr_global_enable(); vPortYield(); @@ -530,78 +538,161 @@ __attribute__((naked)) static void prvTaskExitError(void) _prvTaskExitError(); } -StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters) +/** + * @brief Align stack pointer in a downward growing stack + * + * This macro is used to round a stack pointer downwards to the nearest n-byte boundary, where n is a power of 2. + * This macro is generally used when allocating aligned areas on a downward growing stack. + */ +#define STACKPTR_ALIGN_DOWN(n, ptr) ((ptr) & (~((n)-1))) + +/** + * @brief Allocate and initialize GCC TLS area + * + * This function allocates and initializes the area on the stack used to store GCC TLS (Thread Local Storage) variables. + * - The area's size is derived from the TLS section's linker variables, and rounded up to a multiple of 16 bytes + * - The allocated area is aligned to a 16-byte aligned address + * - The TLS variables in the area are then initialized + * + * Each task access the TLS variables using the THREADPTR register plus an offset to obtain the address of the variable. + * The value for the THREADPTR register is also calculated by this function, and that value should be use to initialize + * the THREADPTR register. + * + * @param[in] uxStackPointer Current stack pointer address + * @param[out] ret_threadptr_reg_init Calculated THREADPTR register initialization value + * @return Stack pointer that points to the TLS area + */ +FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackTLS(UBaseType_t uxStackPointer, uint32_t *ret_threadptr_reg_init) { - extern uint32_t __global_pointer$; - uint8_t *task_thread_local_start; - uint8_t *threadptr; + /* + TLS layout at link-time, where 0xNNN is the offset that the linker calculates to a particular TLS variable. + + LOW ADDRESS + |---------------------------| Linker Symbols + | Section | -------------- + | .flash.rodata | + 0x0|---------------------------| <- _flash_rodata_start + ^ | Other Data | + | |---------------------------| <- _thread_local_start + | | .tbss | ^ + V | | | + 0xNNN | int example; | | tls_area_size + | | | + | .tdata | V + |---------------------------| <- _thread_local_end + | Other data | + | ... | + |---------------------------| + HIGH ADDRESS + */ + // Calculate TLS area size and round up to multiple of 16 bytes. extern char _thread_local_start, _thread_local_end, _flash_rodata_start; + const uint32_t tls_area_size = ALIGNUP(16, (uint32_t)&_thread_local_end - (uint32_t)&_thread_local_start); + // TODO: check that TLS area fits the stack - /* Byte pointer, so that subsequent calculations don't depend on sizeof(StackType_t). */ - uint8_t *sp = (uint8_t *) pxTopOfStack; + // Allocate space for the TLS area on the stack. The area must be aligned to 16-bytes + uxStackPointer = STACKPTR_ALIGN_DOWN(16, uxStackPointer - (UBaseType_t)tls_area_size); + // Initialize the TLS area with the initialization values of each TLS variable + memcpy((void *)uxStackPointer, &_thread_local_start, tls_area_size); - /* Set up TLS area. - * The following diagram illustrates the layout of link-time and run-time - * TLS sections. - * - * +-------------+ - * |Section: | Linker symbols: - * |.flash.rodata| --------------- - * 0x0+-------------+ <-- _flash_rodata_start - * ^ | | - * | | Other data | - * | | ... | - * | +-------------+ <-- _thread_local_start - * | |.tbss | ^ - * v | | | - * 0xNNNN|int example; | | (thread_local_size) - * |.tdata | v - * +-------------+ <-- _thread_local_end - * | Other data | - * | ... | - * | | - * +-------------+ - * - * Local variables of - * pxPortInitialiseStack - * ----------------------- - * +-------------+ <-- pxTopOfStack - * |.tdata (*) | ^ - * ^ |int example; | |(thread_local_size - * | | | | - * | |.tbss (*) | v - * | +-------------+ <-- task_thread_local_start - * 0xNNNN | | | ^ - * | | | | - * | | | |_thread_local_start - _rodata_start - * | | | | - * | | | v - * v +-------------+ <-- threadptr - * - * (*) The stack grows downward! - */ + /* + Calculate the THREADPTR register's initialization value based on the link-time offset and the TLS area allocated on + the stack. - uint32_t thread_local_sz = (uint32_t) (&_thread_local_end - &_thread_local_start); - thread_local_sz = ALIGNUP(0x10, thread_local_sz); - sp -= thread_local_sz; - task_thread_local_start = sp; - memcpy(task_thread_local_start, &_thread_local_start, thread_local_sz); - threadptr = task_thread_local_start - (&_thread_local_start - &_flash_rodata_start); + HIGH ADDRESS + |---------------------------| + | .tdata (*) | + ^ | int example; | + | | | + | | .tbss (*) | + | |---------------------------| <- uxStackPointer (start of TLS area) + 0xNNN | | | ^ + | | | | + | ... | _thread_local_start - _rodata_start + | | | | + | | | V + V | | <- threadptr register's value - /* Simulate the stack frame as it would be created by a context switch interrupt. */ - sp -= RV_STK_FRMSZ; - RvExcFrame *frame = (RvExcFrame *)sp; - memset(frame, 0, sizeof(*frame)); - /* Shifting RA into prvTaskExitError is necessary to make GDB backtrace ending inside that function. - Otherwise backtrace will end in the function laying just before prvTaskExitError in address space. */ - frame->ra = (UBaseType_t)prvTaskExitError + 4/*size of the nop insruction at the beginning of prvTaskExitError*/; + LOW ADDRESS + */ + *ret_threadptr_reg_init = (uint32_t)uxStackPointer - ((uint32_t)&_thread_local_start - (uint32_t)&_flash_rodata_start); + return uxStackPointer; +} + +/** + * @brief Initialize the task's starting interrupt stack frame + * + * This function initializes the task's starting interrupt stack frame. The dispatcher will use this stack frame in a + * context restore routine. Therefore, the starting stack frame must be initialized as if the task was interrupted right + * before its first instruction is called. + * + * - The stack frame is allocated to a 16-byte aligned address + * + * @param[in] uxStackPointer Current stack pointer address + * @param[in] pxCode Task function + * @param[in] pvParameters Task function's parameter + * @param[in] threadptr_reg_init THREADPTR register initialization value + * @return Stack pointer that points to the stack frame + */ +FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackFrame(UBaseType_t uxStackPointer, TaskFunction_t pxCode, void *pvParameters, uint32_t threadptr_reg_init) +{ + /* + Allocate space for the task's starting interrupt stack frame. + - The stack frame must be allocated to a 16-byte aligned address. + - We use RV_STK_FRMSZ (instead of sizeof(RvExcFrame)) as it rounds up the total size to a multiple of 16. + */ + uxStackPointer = STACKPTR_ALIGN_DOWN(16, uxStackPointer - RV_STK_FRMSZ); + + // Clear the entire interrupt stack frame + RvExcFrame *frame = (RvExcFrame *)uxStackPointer; + memset(frame, 0, sizeof(RvExcFrame)); + + /* + Initialize the stack frame. + + Note: Shifting RA into prvTaskExitError is necessary to make the GDB backtrace terminate inside that function. + Otherwise, the backtrace will end in the function located just before prvTaskExitError in the address space. + */ + extern uint32_t __global_pointer$; + frame->ra = (UBaseType_t)prvTaskExitError + 4; // size of the nop instruction at the beginning of prvTaskExitError frame->mepc = (UBaseType_t)pxCode; frame->a0 = (UBaseType_t)pvParameters; frame->gp = (UBaseType_t)&__global_pointer$; - frame->tp = (UBaseType_t)threadptr; + frame->tp = (UBaseType_t)threadptr_reg_init; + return uxStackPointer; +} + +StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters) +{ + /* + HIGH ADDRESS + |---------------------------| <- pxTopOfStack on entry + | TLS Variables | + | ------------------------- | <- Start of useable stack + | Starting stack frame | + | ------------------------- | <- pxTopOfStack on return (which is the tasks current SP) + | | | + | | | + | V | + ----------------------------- <- Bottom of stack + LOW ADDRESS + + - All stack areas are aligned to 16 byte boundary + - We use UBaseType_t for all of stack area initialization functions for more convenient pointer arithmetic + */ + + UBaseType_t uxStackPointer = (UBaseType_t)pxTopOfStack; + + // Initialize GCC TLS area + uint32_t threadptr_reg_init; + uxStackPointer = uxInitialiseStackTLS(uxStackPointer, &threadptr_reg_init); + + // Initialize the starting interrupt stack frame + uxStackPointer = uxInitialiseStackFrame(uxStackPointer, pxCode, pvParameters, threadptr_reg_init); + // Return the task's current stack pointer address which should point to the starting interrupt stack frame + return (StackType_t *)uxStackPointer; //TODO: IDF-2393 - return (StackType_t *)frame; } // ------- Thread Local Storage Pointers Deletion Callbacks ------- diff --git a/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/include/freertos/FreeRTOSConfig_smp.h b/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/include/freertos/FreeRTOSConfig_smp.h index 9da8470f35..66c44f807a 100644 --- a/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/include/freertos/FreeRTOSConfig_smp.h +++ b/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/include/freertos/FreeRTOSConfig_smp.h @@ -282,6 +282,18 @@ Default values for trace macros added by ESP-IDF and are not part of Vanilla Fre #define traceISR_ENTER(_n_) #endif +#ifndef traceQUEUE_GIVE_FROM_ISR + #define traceQUEUE_GIVE_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_GIVE_FROM_ISR_FAILED + #define traceQUEUE_GIVE_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_SEMAPHORE_RECEIVE + #define traceQUEUE_SEMAPHORE_RECEIVE( pxQueue ) +#endif + /* ------------------------------------------------ IDF Compatibility -------------------------------------------------- * - We need these in order for ESP-IDF to compile * ------------------------------------------------------------------------------------------------------------------ */ diff --git a/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/port.c b/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/port.c index fa585852da..75c48ebd7b 100644 --- a/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/port.c +++ b/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/port.c @@ -20,6 +20,7 @@ #include "esp_private/esp_int_wdt.h" #include "esp_private/systimer.h" #include "esp_private/periph_ctrl.h" +#include "esp_attr.h" #include "esp_heap_caps.h" #include "esp_system.h" #include "esp_task.h" @@ -174,6 +175,13 @@ BaseType_t xPortSysTickHandler(void); extern void _frxt_tick_timer_init(void); extern void _xt_tick_divisor_init(void); +#ifdef CONFIG_FREERTOS_CORETIMER_0 + #define SYSTICK_INTR_ID (ETS_INTERNAL_TIMER0_INTR_SOURCE+ETS_INTERNAL_INTR_SOURCE_OFF) +#endif +#ifdef CONFIG_FREERTOS_CORETIMER_1 + #define SYSTICK_INTR_ID (ETS_INTERNAL_TIMER1_INTR_SOURCE+ETS_INTERNAL_INTR_SOURCE_OFF) +#endif + /** * @brief Initialize CCONT timer to generate the tick interrupt * @@ -324,7 +332,7 @@ static void main_task(void *args) #endif //Initialize TWDT if configured to do so -#if CONFIG_ESP_TASK_WDT +#if CONFIG_ESP_TASK_WDT_INIT esp_task_wdt_config_t twdt_config = { .timeout_ms = CONFIG_ESP_TASK_WDT_TIMEOUT_S * 1000, .idle_core_mask = 0, @@ -591,6 +599,240 @@ const DRAM_ATTR uint32_t offset_uxCoreAffinityMask = offsetof(StaticTask_t, uxDu #endif // ( configUSE_CORE_AFFINITY == 1 && configNUM_CORES > 1 ) const DRAM_ATTR uint32_t offset_cpsa = XT_CP_SIZE; +/** + * @brief Align stack pointer in a downward growing stack + * + * This macro is used to round a stack pointer downwards to the nearest n-byte boundary, where n is a power of 2. + * This macro is generally used when allocating aligned areas on a downward growing stack. + */ +#define STACKPTR_ALIGN_DOWN(n, ptr) ((ptr) & (~((n)-1))) + +#if XCHAL_CP_NUM > 0 +/** + * @brief Allocate and initialize coprocessor save area on the stack + * + * This function allocates the coprocessor save area on the stack (sized XT_CP_SIZE) which includes... + * - Individual save areas for each coprocessor (size XT_CPx_SA, inclusive of each area's alignment) + * - Coprocessor context switching flags (e.g., XT_CPENABLE, XT_CPSTORED, XT_CP_CS_ST, XT_CP_ASA). + * + * The coprocessor save area is aligned to a 16-byte boundary. + * The coprocessor context switching flags are then initialized + * + * @param[in] uxStackPointer Current stack pointer address + * @return Stack pointer that points to allocated and initialized the coprocessor save area + */ +FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackCPSA(UBaseType_t uxStackPointer) +{ + /* + HIGH ADDRESS + |-------------------| XT_CP_SIZE + | CPn SA | ^ + | ... | | + | CP0 SA | | + | ----------------- | | ---- XCHAL_TOTAL_SA_ALIGN aligned + |-------------------| | 12 bytes + | XT_CP_ASA | | ^ + | XT_CP_CS_ST | | | + | XT_CPSTORED | | | + | XT_CPENABLE | | | + |-------------------| ---------------------- 16 byte aligned + LOW ADDRESS + */ + + // Allocate overall coprocessor save area, aligned down to 16 byte boundary + uxStackPointer = STACKPTR_ALIGN_DOWN(16, uxStackPointer - XT_CP_SIZE); + // Initialize the coprocessor context switching flags. + uint32_t *p = (uint32_t *)uxStackPointer; + p[0] = 0; // Clear XT_CPENABLE and XT_CPSTORED + p[1] = 0; // Clear XT_CP_CS_ST + // XT_CP_ASA points to the aligned start of the individual CP save areas (i.e., start of CP0 SA) + p[2] = (uint32_t)ALIGNUP(XCHAL_TOTAL_SA_ALIGN, (uint32_t)uxStackPointer + 12); + return uxStackPointer; +} +#endif /* XCHAL_CP_NUM > 0 */ + +/** + * @brief Allocate and initialize GCC TLS area + * + * This function allocates and initializes the area on the stack used to store GCC TLS (Thread Local Storage) variables. + * - The area's size is derived from the TLS section's linker variables, and rounded up to a multiple of 16 bytes + * - The allocated area is aligned to a 16-byte aligned address + * - The TLS variables in the area are then initialized + * + * Each task access the TLS variables using the THREADPTR register plus an offset to obtain the address of the variable. + * The value for the THREADPTR register is also calculated by this function, and that value should be use to initialize + * the THREADPTR register. + * + * @param[in] uxStackPointer Current stack pointer address + * @param[out] ret_threadptr_reg_init Calculated THREADPTR register initialization value + * @return Stack pointer that points to the TLS area + */ +FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackTLS(UBaseType_t uxStackPointer, uint32_t *ret_threadptr_reg_init) +{ + /* + TLS layout at link-time, where 0xNNN is the offset that the linker calculates to a particular TLS variable. + + LOW ADDRESS + |---------------------------| Linker Symbols + | Section | -------------- + | .flash.rodata | + 0x0|---------------------------| <- _flash_rodata_start + ^ | Other Data | + | |---------------------------| <- _thread_local_start + | | .tbss | ^ + V | | | + 0xNNN | int example; | | tls_area_size + | | | + | .tdata | V + |---------------------------| <- _thread_local_end + | Other data | + | ... | + |---------------------------| + HIGH ADDRESS + */ + // Calculate the TLS area's size (rounded up to multiple of 16 bytes). + extern int _thread_local_start, _thread_local_end, _flash_rodata_start, _flash_rodata_align; + const uint32_t tls_area_size = ALIGNUP(16, (uint32_t)&_thread_local_end - (uint32_t)&_thread_local_start); + // TODO: check that TLS area fits the stack + + // Allocate space for the TLS area on the stack. The area must be allocated at a 16-byte aligned address + uxStackPointer = STACKPTR_ALIGN_DOWN(16, uxStackPointer - (UBaseType_t)tls_area_size); + // Initialize the TLS area with the initialization values of each TLS variable + memcpy((void *)uxStackPointer, &_thread_local_start, tls_area_size); + + /* + Calculate the THREADPTR register's initialization value based on the link-time offset and the TLS area allocated on + the stack. + + HIGH ADDRESS + |---------------------------| + | .tdata (*) | + ^ | int example; | + | | | + | | .tbss (*) | + | |---------------------------| <- uxStackPointer (start of TLS area) + 0xNNN | | | ^ + | | | | + | ... | (_thread_local_start - _flash_rodata_start) + align_up(TCB_SIZE, tls_section_alignment) + | | | | + | | | V + V | | <- threadptr register's value + + LOW ADDRESS + + Note: Xtensa is slightly different compared to the RISC-V port as there is an implicit aligned TCB_SIZE added to + the offset. (search for 'tpoff' in elf32-xtensa.c in BFD): + - "offset = address - tls_section_vma + align_up(TCB_SIZE, tls_section_alignment)" + - TCB_SIZE is hardcoded to 8 + */ + const uint32_t tls_section_align = (uint32_t)&_flash_rodata_align; // ALIGN value of .flash.rodata section + #define TCB_SIZE 8 + const uint32_t base = ALIGNUP(tls_section_align, TCB_SIZE); + *ret_threadptr_reg_init = (uint32_t)uxStackPointer - ((uint32_t)&_thread_local_start - (uint32_t)&_flash_rodata_start) - base; + + return uxStackPointer; +} + +/** + * @brief Initialize the task's starting interrupt stack frame + * + * This function initializes the task's starting interrupt stack frame. The dispatcher will use this stack frame in a + * context restore routine. Therefore, the starting stack frame must be initialized as if the task was interrupted right + * before its first instruction is called. + * + * - The stack frame is allocated to a 16-byte aligned address + * - The THREADPTR register is saved in the extra storage area of the stack frame. This is also initialized + * + * @param[in] uxStackPointer Current stack pointer address + * @param[in] pxCode Task function + * @param[in] pvParameters Task function's parameter + * @param[in] threadptr_reg_init THREADPTR register initialization value + * @return Stack pointer that points to the stack frame + */ +FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackFrame(UBaseType_t uxStackPointer, TaskFunction_t pxCode, void *pvParameters, uint32_t threadptr_reg_init) +{ + /* + HIGH ADDRESS + |---------------------------| ^ XT_STK_FRMSZ + | | | + | Stack Frame Extra Storage | | + | | | + | ------------------------- | | ^ XT_STK_EXTRA + | | | | + | Intr/Exc Stack Frame | | | + | | V V + | ------------------------- | ---------------------- 16 byte aligned + LOW ADDRESS + */ + + /* + Allocate space for the task's starting interrupt stack frame. + - The stack frame must be allocated to a 16-byte aligned address. + - We use XT_STK_FRMSZ (instead of sizeof(XtExcFrame)) as it... + - includes the size of the extra storage area + - includes the size for a base save area before the stack frame + - rounds up the total size to a multiple of 16 + */ + UBaseType_t uxStackPointerPrevious = uxStackPointer; + uxStackPointer = STACKPTR_ALIGN_DOWN(16, uxStackPointer - XT_STK_FRMSZ); + + // Clear the entire interrupt stack frame + memset((void *)uxStackPointer, 0, (size_t)(uxStackPointerPrevious - uxStackPointer)); + + XtExcFrame *frame = (XtExcFrame *)uxStackPointer; + + /* + Initialize common registers + */ + frame->a0 = 0; // Set the return address to 0 terminate GDB backtrace + frame->a1 = uxStackPointer + XT_STK_FRMSZ; // Saved stack pointer should point to physical top of stack frame + frame->exit = (UBaseType_t) _xt_user_exit; // User exception exit dispatcher + + /* + Initialize the task's entry point. This will differ depending on + - Whether the task's entry point is the wrapper function or pxCode + - Whether Windowed ABI is used (for windowed, we mimic the task entry point being call4'd ) + */ + #if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER + frame->pc = (UBaseType_t) vPortTaskWrapper; // Task entry point is the wrapper function + #ifdef __XTENSA_CALL0_ABI__ + frame->a2 = (UBaseType_t) pxCode; // Wrapper function's argument 0 (which is the task function) + frame->a3 = (UBaseType_t) pvParameters; // Wrapper function's argument 1 (which is the task function's argument) + #else // __XTENSA_CALL0_ABI__ + frame->a6 = (UBaseType_t) pxCode; // Wrapper function's argument 0 (which is the task function), passed as if we call4'd + frame->a7 = (UBaseType_t) pvParameters; // Wrapper function's argument 1 (which is the task function's argument), passed as if we call4'd + #endif // __XTENSA_CALL0_ABI__ + #else + frame->pc = (UBaseType_t) pxCode; // Task entry point is the provided task function + #ifdef __XTENSA_CALL0_ABI__ + frame->a2 = (UBaseType_t) pvParameters; // Task function's argument + #else // __XTENSA_CALL0_ABI__ + frame->a6 = (UBaseType_t) pvParameters; // Task function's argument, passed as if we call4'd + #endif // __XTENSA_CALL0_ABI__ + #endif + + /* + Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. + For windowed ABI also set WOE and CALLINC (pretend task was 'call4'd) + */ + #ifdef __XTENSA_CALL0_ABI__ + frame->ps = PS_UM | PS_EXCM; + #else // __XTENSA_CALL0_ABI__ + frame->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1); + #endif // __XTENSA_CALL0_ABI__ + + #ifdef XT_USE_SWPRI + // Set the initial virtual priority mask value to all 1's. + frame->vpri = 0xFFFFFFFF; + #endif + + // Initialize the threadptr register in the extra save area of the stack frame + uint32_t *threadptr_reg = (uint32_t *)(uxStackPointer + XT_STK_EXTRA); + *threadptr_reg = threadptr_reg_init; + + return uxStackPointer; +} + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t * pxEndOfStack, @@ -602,108 +844,41 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, void * pvParameters ) #endif { - StackType_t *sp, *tp; - XtExcFrame *frame; -#if XCHAL_CP_NUM > 0 - uint32_t *p; -#endif - uint32_t *threadptr; - void *task_thread_local_start; - extern int _thread_local_start, _thread_local_end, _flash_rodata_start, _flash_rodata_align; - // TODO: check that TLS area fits the stack - uint32_t thread_local_sz = (uint8_t *)&_thread_local_end - (uint8_t *)&_thread_local_start; + /* + HIGH ADDRESS + |---------------------------| <- pxTopOfStack on entry + | Coproc Save Area | + | ------------------------- | + | TLS Variables | + | ------------------------- | <- Start of useable stack + | Starting stack frame | + | ------------------------- | <- pxTopOfStack on return (which is the tasks current SP) + | | | + | | | + | V | + ----------------------------- <- Bottom of stack + LOW ADDRESS - thread_local_sz = ALIGNUP(0x10, thread_local_sz); + - All stack areas are aligned to 16 byte boundary + - We use UBaseType_t for all of stack area initialization functions for more convenient pointer arithmetic + */ - /* Initialize task's stack so that we have the following structure at the top: - - ----LOW ADDRESSES ----------------------------------------HIGH ADDRESSES---------- - task stack | interrupt stack frame | thread local vars | co-processor save area | - ---------------------------------------------------------------------------------- - | | - SP pxTopOfStack - - All parts are aligned to 16 byte boundary. */ - sp = (StackType_t *) (((UBaseType_t)pxTopOfStack - XT_CP_SIZE - thread_local_sz - XT_STK_FRMSZ) & ~0xf); - - /* Clear the entire frame (do not use memset() because we don't depend on C library) */ - for (tp = sp; tp <= pxTopOfStack; ++tp) { - *tp = 0; - } - - frame = (XtExcFrame *) sp; - - /* Explicitly initialize certain saved registers */ -#if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER - frame->pc = (UBaseType_t) vPortTaskWrapper; /* task wrapper */ -#else - frame->pc = (UBaseType_t) pxCode; /* task entrypoint */ -#endif - frame->a0 = 0; /* to terminate GDB backtrace */ - frame->a1 = (UBaseType_t) sp + XT_STK_FRMSZ; /* physical top of stack frame */ - frame->exit = (UBaseType_t) _xt_user_exit; /* user exception exit dispatcher */ - - /* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. */ - /* Also set entry point argument parameter. */ -#ifdef __XTENSA_CALL0_ABI__ -#if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER - frame->a2 = (UBaseType_t) pxCode; - frame->a3 = (UBaseType_t) pvParameters; -#else - frame->a2 = (UBaseType_t) pvParameters; -#endif - frame->ps = PS_UM | PS_EXCM; -#else /* __XTENSA_CALL0_ABI__ */ - /* + for windowed ABI also set WOE and CALLINC (pretend task was 'call4'd). */ -#if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER - frame->a6 = (UBaseType_t) pxCode; - frame->a7 = (UBaseType_t) pvParameters; -#else - frame->a6 = (UBaseType_t) pvParameters; -#endif - frame->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1); -#endif /* __XTENSA_CALL0_ABI__ */ - -#ifdef XT_USE_SWPRI - /* Set the initial virtual priority mask value to all 1's. */ - frame->vpri = 0xFFFFFFFF; -#endif - - /* Init threadptr register and set up TLS run-time area. - * The diagram in port/riscv/port.c illustrates the calculations below. - */ - task_thread_local_start = (void *)(((uint32_t)pxTopOfStack - XT_CP_SIZE - thread_local_sz) & ~0xf); - memcpy(task_thread_local_start, &_thread_local_start, thread_local_sz); - threadptr = (uint32_t *)(sp + XT_STK_EXTRA); - /* Calculate THREADPTR value. - * The generated code will add THREADPTR value to a constant value determined at link time, - * to get the address of the TLS variable. - * The constant value is calculated by the linker as follows - * (search for 'tpoff' in elf32-xtensa.c in BFD): - * offset = address - tls_section_vma + align_up(TCB_SIZE, tls_section_alignment) - * where TCB_SIZE is hardcoded to 8. - * Note this is slightly different compared to the RISC-V port, where offset = address - tls_section_vma. - */ - const uint32_t tls_section_alignment = (uint32_t) &_flash_rodata_align; /* ALIGN value of .flash.rodata section */ - const uint32_t tcb_size = 8; /* Unrelated to FreeRTOS, this is the constant from BFD */ - const uint32_t base = (tcb_size + tls_section_alignment - 1) & (~(tls_section_alignment - 1)); - *threadptr = (uint32_t)task_thread_local_start - ((uint32_t)&_thread_local_start - (uint32_t)&_flash_rodata_start) - base; + UBaseType_t uxStackPointer = (UBaseType_t)pxTopOfStack; #if XCHAL_CP_NUM > 0 - /* Init the coprocessor save area (see xtensa_context.h) */ - /* No access to TCB here, so derive indirectly. Stack growth is top to bottom. - * //p = (uint32_t *) xMPUSettings->coproc_area; - */ - p = (uint32_t *)(((uint32_t) pxTopOfStack - XT_CP_SIZE) & ~0xf); - configASSERT( ( uint32_t ) p >= frame->a1 ); - p[0] = 0; - p[1] = 0; - p[2] = (((uint32_t) p) + 12 + XCHAL_TOTAL_SA_ALIGN - 1) & -XCHAL_TOTAL_SA_ALIGN; -#endif /* XCHAL_CP_NUM */ + // Initialize the coprocessor save area + uxStackPointer = uxInitialiseStackCPSA(uxStackPointer); +#endif /* XCHAL_CP_NUM > 0 */ - return sp; + // Initialize the GCC TLS area + uint32_t threadptr_reg_init; + uxStackPointer = uxInitialiseStackTLS(uxStackPointer, &threadptr_reg_init); + + // Initialize the starting interrupt stack frame + uxStackPointer = uxInitialiseStackFrame(uxStackPointer, pxCode, pvParameters, threadptr_reg_init); + // Return the task's current stack pointer address which should point to the starting interrupt stack frame + return (StackType_t *)uxStackPointer; } - // -------------------- Co-Processor ----------------------- #if ( XCHAL_CP_NUM > 0 && configUSE_CORE_AFFINITY == 1 && configNUM_CORES > 1 ) diff --git a/components/freertos/FreeRTOS-Kernel-SMP/queue.c b/components/freertos/FreeRTOS-Kernel-SMP/queue.c index 0233171d6d..56869290b8 100644 --- a/components/freertos/FreeRTOS-Kernel-SMP/queue.c +++ b/components/freertos/FreeRTOS-Kernel-SMP/queue.c @@ -1202,7 +1202,9 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, { const int8_t cTxLock = pxQueue->cTxLock; - traceQUEUE_SEND_FROM_ISR( pxQueue ); +#ifdef ESP_PLATFORM // IDF-5384 + traceQUEUE_GIVE_FROM_ISR( pxQueue ); +#endif /* A task can only have an inherited priority if it is a mutex * holder - and if there is a mutex holder then the mutex cannot be @@ -1309,7 +1311,9 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, } else { - traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); +#ifdef ESP_PLATFORM // IDF-5384 + traceQUEUE_GIVE_FROM_ISR_FAILED( pxQueue ); +#endif xReturn = errQUEUE_FULL; } } @@ -1502,8 +1506,9 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, * must be the highest priority task wanting to access the queue. */ if( uxSemaphoreCount > ( UBaseType_t ) 0 ) { - traceQUEUE_RECEIVE( pxQueue ); - +#ifdef ESP_PLATFORM + traceQUEUE_SEMAPHORE_RECEIVE( pxQueue ); +#endif /* Semaphores are queues with a data size of zero and where the * messages waiting is the semaphore's count. Reduce the count. */ pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1; diff --git a/components/freertos/FreeRTOS-Kernel/event_groups.c b/components/freertos/FreeRTOS-Kernel/event_groups.c index 0d35f33244..d1b6ba4987 100644 --- a/components/freertos/FreeRTOS-Kernel/event_groups.c +++ b/components/freertos/FreeRTOS-Kernel/event_groups.c @@ -45,18 +45,6 @@ #include "timers.h" #include "event_groups.h" -#ifdef ESP_PLATFORM -#define taskCRITICAL_MUX &pxEventBits->eventGroupMux -#undef taskENTER_CRITICAL -#undef taskEXIT_CRITICAL -#undef taskENTER_CRITICAL_ISR -#undef taskEXIT_CRITICAL_ISR -#define taskENTER_CRITICAL( ) portENTER_CRITICAL( taskCRITICAL_MUX ) -#define taskEXIT_CRITICAL( ) portEXIT_CRITICAL( taskCRITICAL_MUX ) -#define taskENTER_CRITICAL_ISR( ) portENTER_CRITICAL_ISR( taskCRITICAL_MUX ) -#define taskEXIT_CRITICAL_ISR( ) portEXIT_CRITICAL_ISR( taskCRITICAL_MUX ) -#endif - /* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined * for the header files above, but not in this file, in order to generate the @@ -92,7 +80,7 @@ typedef struct EventGroupDef_t #endif #ifdef ESP_PLATFORM - portMUX_TYPE eventGroupMux; //Mutex required due to SMP + portMUX_TYPE xEventGroupLock; /* Spinlock required for SMP critical sections */ #endif // ESP_PLATFORM } EventGroup_t; @@ -150,7 +138,7 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, traceEVENT_GROUP_CREATE( pxEventBits ); #ifdef ESP_PLATFORM - portMUX_INITIALIZE( &pxEventBits->eventGroupMux ); + portMUX_INITIALIZE( &pxEventBits->xEventGroupLock ); #endif // ESP_PLATFORM } else @@ -203,7 +191,7 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, #endif /* configSUPPORT_STATIC_ALLOCATION */ #ifdef ESP_PLATFORM - portMUX_INITIALIZE( &pxEventBits->eventGroupMux ); + portMUX_INITIALIZE( &pxEventBits->xEventGroupLock ); #endif // ESP_PLATFORM traceEVENT_GROUP_CREATE( pxEventBits ); @@ -226,9 +214,7 @@ EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, { EventBits_t uxOriginalBitValue, uxReturn; EventGroup_t * pxEventBits = xEventGroup; -#ifndef ESP_PLATFORM BaseType_t xAlreadyYielded; -#endif // ESP_PLATFORM BaseType_t xTimeoutOccurred = pdFALSE; configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); @@ -240,7 +226,7 @@ EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, #endif #ifdef ESP_PLATFORM // IDF-3755 - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxEventBits->xEventGroupLock ) ); #else vTaskSuspendAll(); #endif // ESP_PLATFORM @@ -287,16 +273,14 @@ EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, } } #ifdef ESP_PLATFORM // IDF-3755 - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxEventBits->xEventGroupLock ) ); + xAlreadyYielded = pdFALSE; #else xAlreadyYielded = xTaskResumeAll(); #endif // ESP_PLATFORM if( xTicksToWait != ( TickType_t ) 0 ) { -#ifdef ESP_PLATFORM - portYIELD_WITHIN_API(); -#else if( xAlreadyYielded == pdFALSE ) { portYIELD_WITHIN_API(); @@ -305,7 +289,6 @@ EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, { mtCOVERAGE_TEST_MARKER(); } -#endif // ESP_PLATFORM /* The task blocked to wait for its required bits to be set - at this * point either the required bits were set or the block time expired. If @@ -316,7 +299,7 @@ EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) { /* The task timed out, just return the current event bit value. */ - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxEventBits->xEventGroupLock ) ); { uxReturn = pxEventBits->uxEventBits; @@ -333,7 +316,7 @@ EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, mtCOVERAGE_TEST_MARKER(); } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxEventBits->xEventGroupLock ) ); xTimeoutOccurred = pdTRUE; } @@ -364,11 +347,7 @@ EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, { EventGroup_t * pxEventBits = xEventGroup; EventBits_t uxReturn, uxControlBits = 0; -#ifdef ESP_PLATFORM - BaseType_t xWaitConditionMet; -#else BaseType_t xWaitConditionMet, xAlreadyYielded; -#endif // ESP_PLATFORM BaseType_t xTimeoutOccurred = pdFALSE; /* Check the user is not attempting to wait on the bits used by the kernel @@ -383,7 +362,7 @@ EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, #endif #ifdef ESP_PLATFORM // IDF-3755 - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxEventBits->xEventGroupLock ) ); #else vTaskSuspendAll(); #endif // ESP_PLATFORM @@ -455,16 +434,14 @@ EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, } } #ifdef ESP_PLATFORM // IDF-3755 - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxEventBits->xEventGroupLock ) ); + xAlreadyYielded = pdFALSE; #else xAlreadyYielded = xTaskResumeAll(); #endif // ESP_PLATFORM if( xTicksToWait != ( TickType_t ) 0 ) { -#ifdef ESP_PLATFORM - portYIELD_WITHIN_API(); -#else if( xAlreadyYielded == pdFALSE ) { portYIELD_WITHIN_API(); @@ -473,7 +450,6 @@ EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, { mtCOVERAGE_TEST_MARKER(); } -#endif // ESP_PLATFORM /* The task blocked to wait for its required bits to be set - at this * point either the required bits were set or the block time expired. If @@ -483,7 +459,7 @@ EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) { - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxEventBits->xEventGroupLock ) ); { /* The task timed out, just return the current event bit value. */ uxReturn = pxEventBits->uxEventBits; @@ -508,7 +484,7 @@ EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, xTimeoutOccurred = pdTRUE; } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxEventBits->xEventGroupLock ) ); } else { @@ -539,7 +515,7 @@ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, configASSERT( xEventGroup ); configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxEventBits->xEventGroupLock ) ); { traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ); @@ -550,7 +526,7 @@ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, /* Clear the bits. */ pxEventBits->uxEventBits &= ~uxBitsToClear; } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxEventBits->xEventGroupLock ) ); return uxReturn; } @@ -606,11 +582,10 @@ EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, pxList = &( pxEventBits->xTasksWaitingForBits ); pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ #ifdef ESP_PLATFORM // IDF-3755 - taskENTER_CRITICAL(); - /* The critical section above only takes the event groups spinlock. However, we are about to traverse a task list. - * Thus we need call the function below to take the task list spinlock located in tasks.c. Not doing so will risk - * the task list's being changed while be are traversing it. */ - vTaskTakeEventListLock(); + taskENTER_CRITICAL( &( pxEventBits->xEventGroupLock ) ); + /* We are about to traverse a task list which is a kernel data structure. + * Thus we need to call vTaskTakeKernelLock() to take the kernel lock. */ + vTaskTakeKernelLock(); #else vTaskSuspendAll(); #endif // ESP_PLATFORM @@ -686,9 +661,9 @@ EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, pxEventBits->uxEventBits &= ~uxBitsToClear; } #ifdef ESP_PLATFORM // IDF-3755 - /* Release the previously held task list spinlock, then release the event group spinlock. */ - vTaskReleaseEventListLock(); - taskEXIT_CRITICAL(); + /* Release the previously taken kernel lock, then release the event group spinlock. */ + vTaskReleaseKernelLock(); + taskEXIT_CRITICAL( &( pxEventBits->xEventGroupLock ) ); #else ( void ) xTaskResumeAll(); #endif // ESP_PLATFORM @@ -705,12 +680,11 @@ void vEventGroupDelete( EventGroupHandle_t xEventGroup ) traceEVENT_GROUP_DELETE( xEventGroup ); // IDF-3755 - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxEventBits->xEventGroupLock ) ); #ifdef ESP_PLATFORM - /* The critical section above only takes the event groups spinlock. However, we are about to traverse a task list. - * Thus we need call the function below to take the task list spinlock located in tasks.c. Not doing so will risk - * the task list's being changed while be are traversing it. */ - vTaskTakeEventListLock(); + /* We are about to traverse a task list which is a kernel data structure. + * Thus we need to call vTaskTakeKernelLock() to take the kernel lock. */ + vTaskTakeKernelLock(); #endif { while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 ) @@ -722,10 +696,10 @@ void vEventGroupDelete( EventGroupHandle_t xEventGroup ) } } #ifdef ESP_PLATFORM - /* Release the previously held task list spinlock. */ - vTaskReleaseEventListLock(); + /* Release the previously taken kernel lock. */ + vTaskReleaseKernelLock(); #endif - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxEventBits->xEventGroupLock ) ); #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) { diff --git a/components/freertos/FreeRTOS-Kernel/include/freertos/task.h b/components/freertos/FreeRTOS-Kernel/include/freertos/task.h index 0cd5f1b94a..a3893e45b9 100644 --- a/components/freertos/FreeRTOS-Kernel/include/freertos/task.h +++ b/components/freertos/FreeRTOS-Kernel/include/freertos/task.h @@ -3391,8 +3391,8 @@ void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. * - * This function is a wrapper to take the "xTaskQueueMutex" spinlock of tasks.c. - * This lock is taken whenver any of the task lists or event lists are + * This function is a wrapper to take the "xKernelLock" spinlock of tasks.c. + * This lock is taken whenver any of the kernel's data structures are * accessed/modified, such as when adding/removing tasks to/from the delayed * task list or various event lists. * @@ -3401,8 +3401,8 @@ void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, * of delegating the entire responsibility to one of vTask...EventList() * functions). */ -void vTaskTakeEventListLock( void ); -void vTaskReleaseEventListLock( void ); +void vTaskTakeKernelLock( void ); +void vTaskReleaseKernelLock( void ); #endif // ESP_PLATFORM /* diff --git a/components/freertos/FreeRTOS-Kernel/portable/linux/include/freertos/portmacro.h b/components/freertos/FreeRTOS-Kernel/portable/linux/include/freertos/portmacro.h index 9d4cde1871..085967281b 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/linux/include/freertos/portmacro.h +++ b/components/freertos/FreeRTOS-Kernel/portable/linux/include/freertos/portmacro.h @@ -1,41 +1,141 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * FreeRTOS Kernel V10.4.6 + * Copyright 2020 Cambridge Consultants Ltd. * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2020 Cambridge Consultants Ltd. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS */ -#pragma once -#include "esp_attr.h" -#include +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include #ifdef __cplusplus extern "C" { #endif -#define portBYTE_ALIGNMENT 16 +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ /* Type definitions. */ -#define portCHAR uint8_t -#define portFLOAT float -#define portDOUBLE double -#define portLONG int32_t -#define portSHORT int16_t -#define portSTACK_TYPE uint8_t -#define portBASE_TYPE int -// interrupt module will mask interrupt with priority less than threshold -#define RVHAL_EXCM_LEVEL 4 +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned long +#define portBASE_TYPE long +#define portPOINTER_SIZE_TYPE intptr_t -typedef portSTACK_TYPE StackType_t; -typedef portBASE_TYPE BaseType_t; -typedef unsigned portBASE_TYPE UBaseType_t; -typedef uint32_t TickType_t; -#define portMAX_DELAY ( TickType_t ) 0xffffffffUL +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; -typedef int portMUX_TYPE; +typedef unsigned long TickType_t; +#define portMAX_DELAY ( TickType_t ) ULONG_MAX -#define portTICK_PERIOD_MS ( ( TickType_t ) 1 ) +#define portTICK_TYPE_IS_ATOMIC 1 + +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portHAS_STACK_OVERFLOW_CHECKING ( 1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portTICK_RATE_MICROSECONDS ( ( TickType_t ) 1000000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ +extern void vPortYield( void ); + +#define portYIELD() vPortYield() + +#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) vPortYield() +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortDisableInterrupts( void ); +extern void vPortEnableInterrupts( void ); +#define portSET_INTERRUPT_MASK() ( vPortDisableInterrupts() ) +#define portCLEAR_INTERRUPT_MASK() ( vPortEnableInterrupts() ) + +extern portBASE_TYPE xPortSetInterruptMask( void ); +extern void vPortClearInterruptMask( portBASE_TYPE xMask ); + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portSET_INTERRUPT_MASK_FROM_ISR() xPortSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x) +#define portDISABLE_INTERRUPTS() portSET_INTERRUPT_MASK() +#define portENABLE_INTERRUPTS() portCLEAR_INTERRUPT_MASK() +#define portENTER_CRITICAL(mux) {(void)mux; vPortEnterCritical();} +#define portEXIT_CRITICAL(mux) {(void)mux; vPortExitCritical();} +#define portENTER_CRITICAL_ISR(mux) portENTER_CRITICAL(mux) +#define portEXIT_CRITICAL_ISR(mux) portEXIT_CRITICAL(mux) + +/*-----------------------------------------------------------*/ + +extern void vPortThreadDying( void *pxTaskToDelete, volatile BaseType_t *pxPendYield ); +extern void vPortCancelThread( void *pxTaskToDelete ); +#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxPendYield ) vPortThreadDying( ( pvTaskToDelete ), ( pxPendYield ) ) +#define portCLEAN_UP_TCB( pxTCB ) vPortCancelThread( pxTCB ) +/*-----------------------------------------------------------*/ + +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +/* + * Tasks run in their own pthreads and context switches between them + * are always a full memory barrier. ISRs are emulated as signals + * which also imply a full memory barrier. + * + * Thus, only a compilier barrier is needed to prevent the compiler + * reordering. + */ +#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) + +extern unsigned long ulPortGetRunTime( void ); +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() /* no-op */ +#define portGET_RUN_TIME_COUNTER_VALUE() ulPortGetRunTime() #ifdef __cplusplus } #endif + +// We need additional definitions for ESP-IDF code +#include "portmacro_idf.h" + +#endif /* PORTMACRO_H */ diff --git a/components/freertos/FreeRTOS-Kernel/portable/linux/include/freertos/portmacro_idf.h b/components/freertos/FreeRTOS-Kernel/portable/linux/include/freertos/portmacro_idf.h new file mode 100644 index 0000000000..c00c8c6d2e --- /dev/null +++ b/components/freertos/FreeRTOS-Kernel/portable/linux/include/freertos/portmacro_idf.h @@ -0,0 +1,98 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * This is the "IDF-part" of the POSIX portmacro. + * We need additional definitions for code in ESP-IDF which is kept here to separate the original + * FreeRTOS POSIX port code from the additional IDF POSIX port code. + */ + +#pragma once + +#include +#include "sdkconfig.h" +#include "esp_attr.h" +#include "spinlock.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: IDF-5983 From esp_task.h, should later be used from there +// or be refactored in IDF (e.g. move esp_task.h to freertos) +// See also configMINIMAL_STACK_SIZE for more information. +#define CONFIG_ESP_MAIN_TASK_STACK_SIZE ( ( unsigned short ) (0x4000 + 40) / sizeof(portSTACK_TYPE) ) // should be in Kconfig again +#define CONFIG_ESP_MAIN_TASK_AFFINITY 0 + +#define ESP_TASK_PRIO_MAX (configMAX_PRIORITIES) +#define ESP_TASK_PRIO_MIN (0) +#define ESP_TASK_MAIN_PRIO (ESP_TASK_PRIO_MIN + 1) +#define ESP_TASK_MAIN_STACK (CONFIG_ESP_MAIN_TASK_STACK_SIZE) +#define ESP_TASK_MAIN_CORE CONFIG_ESP_MAIN_TASK_AFFINITY + +// interrupt module will mask interrupt with priority less than threshold +#define RVHAL_EXCM_LEVEL 4 + +typedef spinlock_t portMUX_TYPE; + +/**< Spinlock initializer */ +#define portMUX_INITIALIZER_UNLOCKED { \ + .owner = portMUX_FREE_VAL, \ + .count = 0, \ + } +#define portMUX_FREE_VAL SPINLOCK_FREE /**< Spinlock is free. [refactor-todo] check if this is still required */ + +void vPortYieldFromISR(void); +void vPortYieldOtherCore(BaseType_t coreid); + +#define portMUX_INITIALIZE(mux) spinlock_initialize(mux) /*< Initialize a spinlock to its unlocked state */ + +/** + * @brief Get the current core's ID + * + * @note dummy function for freertos simulator, always returns 0. + @ return BaseType_t 0 + */ +static inline BaseType_t IRAM_ATTR xPortGetCoreID(void) +{ + return (BaseType_t) 0; +} + +static inline bool portVALID_TCB_MEM(const void *ptr) +{ + return true; +} + +static inline bool portVALID_STACK_MEM(const void *ptr) +{ + return true; +} + +#define pvPortMallocTcbMem(size) pvPortMalloc(size) +#define pvPortMallocStackMem(size) pvPortMalloc(size) + +BaseType_t xPortCheckIfInISR(void); + +/** + * @brief Checks if the current core is in an ISR context + * + * - ISR context consist of Low/Mid priority ISR, or time tick ISR + * - High priority ISRs aren't detected here, but they normally cannot call C code, so that should not be an issue anyway. + * + * @note [refactor-todo] Check if this should be inlined + * @return + * - pdTRUE if in ISR + * - pdFALSE otherwise + */ +static inline BaseType_t xPortInIsrContext(void) +{ + //Just call the FreeRTOS port interface version + return xPortCheckIfInISR(); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/freertos/FreeRTOS-Kernel/portable/linux/include/spinlock.h b/components/freertos/FreeRTOS-Kernel/portable/linux/include/spinlock.h new file mode 100644 index 0000000000..54d2072af0 --- /dev/null +++ b/components/freertos/FreeRTOS-Kernel/portable/linux/include/spinlock.h @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * This file provides only very simple stubs to build IDF-based FreeRTOSes which use spinlocks on Linux. + */ +#pragma once + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SPINLOCK_FREE 0xB33FFFFF +#define SPINLOCK_WAIT_FOREVER (-1) +#define SPINLOCK_NO_WAIT 0 +#define SPINLOCK_INITIALIZER {.owner = SPINLOCK_FREE,.count = 0} +#define CORE_ID_REGVAL_XOR_SWAP (0xCDCD ^ 0xABAB) + +/** + * @brief Spinlock object + * Owner: + * - Set to 0 if uninitialized + * - Set to portMUX_FREE_VAL when free + * - Set to CORE_ID_REGVAL_PRO or CORE_ID_REGVAL_AP when locked + * - Any other value indicates corruption + * Count: + * - 0 if unlocked + * - Recursive count if locked + * + * @note Not a true spinlock as single core RISC-V does not have atomic compare and set instruction + * @note Keep portMUX_INITIALIZER_UNLOCKED in sync with this struct + */ +typedef struct { + uint32_t owner; + uint32_t count; +}spinlock_t; + +static inline void __attribute__((always_inline)) spinlock_initialize(spinlock_t *lock) +{ +} + +static inline bool __attribute__((always_inline)) spinlock_acquire(spinlock_t *lock, int32_t timeout) +{ + return true; +} + +static inline void __attribute__((always_inline)) spinlock_release(spinlock_t *lock) +{ +} + +#ifdef __cplusplus +} +#endif diff --git a/components/freertos/FreeRTOS-Kernel/portable/linux/port.c b/components/freertos/FreeRTOS-Kernel/portable/linux/port.c new file mode 100644 index 0000000000..6727ce3f1e --- /dev/null +++ b/components/freertos/FreeRTOS-Kernel/portable/linux/port.c @@ -0,0 +1,564 @@ +/* + * SPDX-FileCopyrightText: 2020 Amazon.com, Inc. or its affiliates + * + * SPDX-License-Identifier: MIT + */ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Posix port. + * + * Each task has a pthread which eases use of standard debuggers + * (allowing backtraces of tasks etc). Threads for tasks that are not + * running are blocked in sigwait(). + * + * Task switch is done by resuming the thread for the next task by + * signaling the condition variable and then waiting on a condition variable + * with the current thread. + * + * The timer interrupt uses SIGALRM and care is taken to ensure that + * the signal handler runs only on the thread for the current task. + * + * Use of part of the standard C library requires care as some + * functions can take pthread mutexes internally which can result in + * deadlocks as the FreeRTOS kernel can switch tasks while they're + * holding a pthread mutex. + * + * stdio (printf() and friends) should be called from a single task + * only or serialized with a FreeRTOS primitive such as a binary + * semaphore or mutex. + *----------------------------------------------------------*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "utils/wait_for_event.h" +/*-----------------------------------------------------------*/ + +#define SIG_RESUME SIGUSR1 + +typedef struct THREAD +{ + pthread_t pthread; + TaskFunction_t pxCode; + void *pvParams; + BaseType_t xDying; + struct event *ev; +} Thread_t; + +/* + * The additional per-thread data is stored at the beginning of the + * task's stack. + */ +static inline Thread_t *prvGetThreadFromTask(TaskHandle_t xTask) +{ +StackType_t *pxTopOfStack = *(StackType_t **)xTask; + + return (Thread_t *)(pxTopOfStack + 1); +} + +/*-----------------------------------------------------------*/ + +static pthread_once_t hSigSetupThread = PTHREAD_ONCE_INIT; +static sigset_t xAllSignals; +static sigset_t xSchedulerOriginalSignalMask; +static pthread_t hMainThread = ( pthread_t )NULL; +static volatile portBASE_TYPE uxCriticalNesting; +/*-----------------------------------------------------------*/ + +static portBASE_TYPE xSchedulerEnd = pdFALSE; +/*-----------------------------------------------------------*/ + +static void prvSetupSignalsAndSchedulerPolicy( void ); +static void prvSetupTimerInterrupt( void ); +static void *prvWaitForStart( void * pvParams ); +static void prvSwitchThread( Thread_t * xThreadToResume, + Thread_t *xThreadToSuspend ); +static void prvSuspendSelf( Thread_t * thread); +static void prvResumeThread( Thread_t * xThreadId ); +static void vPortSystemTickHandler( int sig ); +static void vPortStartFirstTask( void ); +/*-----------------------------------------------------------*/ + +static void prvFatalError( const char *pcCall, int iErrno ) +{ + fprintf( stderr, "%s: %s\n", pcCall, strerror( iErrno ) ); + abort(); +} + +/* + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, + portSTACK_TYPE *pxEndOfStack, + TaskFunction_t pxCode, void *pvParameters ) +{ +Thread_t *thread; +pthread_attr_t xThreadAttributes; +size_t ulStackSize; +int iRet; + + (void)pthread_once( &hSigSetupThread, prvSetupSignalsAndSchedulerPolicy ); + + /* + * Store the additional thread data at the start of the stack. + */ + thread = (Thread_t *)(pxTopOfStack + 1) - 1; + pxTopOfStack = (portSTACK_TYPE *)thread - 1; + ulStackSize = (pxTopOfStack + 1 - pxEndOfStack) * sizeof(*pxTopOfStack); + + thread->pxCode = pxCode; + thread->pvParams = pvParameters; + thread->xDying = pdFALSE; + + pthread_attr_init( &xThreadAttributes ); + pthread_attr_setstack( &xThreadAttributes, pxEndOfStack, ulStackSize ); + + thread->ev = event_create(); + + vPortEnterCritical(); + + iRet = pthread_create( &thread->pthread, &xThreadAttributes, + prvWaitForStart, thread ); + if ( iRet ) + { + prvFatalError( "pthread_create", iRet ); + } + + vPortExitCritical(); + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortStartFirstTask( void ) +{ +Thread_t *pxFirstThread = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() ); + + /* Start the first task. */ + prvResumeThread( pxFirstThread ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portBASE_TYPE xPortStartScheduler( void ) +{ +int iSignal; +sigset_t xSignals; + + hMainThread = pthread_self(); + + /* Start the timer that generates the tick ISR(SIGALRM). + Interrupts are disabled here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Wait until signaled by vPortEndScheduler(). */ + sigemptyset( &xSignals ); + sigaddset( &xSignals, SIG_RESUME ); + + while ( !xSchedulerEnd ) + { + sigwait( &xSignals, &iSignal ); + } + + /* Cancel the Idle task and free its resources */ +#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + vPortCancelThread( xTaskGetIdleTaskHandle() ); +#endif + +#if ( configUSE_TIMERS == 1 ) + /* Cancel the Timer task and free its resources */ + vPortCancelThread( xTimerGetTimerDaemonTaskHandle() ); +#endif /* configUSE_TIMERS */ + + /* Restore original signal mask. */ + (void)pthread_sigmask( SIG_SETMASK, &xSchedulerOriginalSignalMask, NULL ); + + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ +struct itimerval itimer; +struct sigaction sigtick; +Thread_t *xCurrentThread; + + /* Stop the timer and ignore any pending SIGALRMs that would end + * up running on the main thread when it is resumed. */ + itimer.it_value.tv_sec = 0; + itimer.it_value.tv_usec = 0; + + itimer.it_interval.tv_sec = 0; + itimer.it_interval.tv_usec = 0; + (void)setitimer( ITIMER_REAL, &itimer, NULL ); + + sigtick.sa_flags = 0; + sigtick.sa_handler = SIG_IGN; + sigemptyset( &sigtick.sa_mask ); + sigaction( SIGALRM, &sigtick, NULL ); + + /* Signal the scheduler to exit its loop. */ + xSchedulerEnd = pdTRUE; + (void)pthread_kill( hMainThread, SIG_RESUME ); + + xCurrentThread = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() ); + prvSuspendSelf(xCurrentThread); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + if ( uxCriticalNesting == 0 ) + { + vPortDisableInterrupts(); + } + uxCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + uxCriticalNesting--; + + /* If we have reached 0 then re-enable the interrupts. */ + if( uxCriticalNesting == 0 ) + { + vPortEnableInterrupts(); + } +} +/*-----------------------------------------------------------*/ + +void vPortYieldFromISR( void ) +{ +Thread_t *xThreadToSuspend; +Thread_t *xThreadToResume; + + xThreadToSuspend = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() ); + + vTaskSwitchContext(); + + xThreadToResume = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() ); + + prvSwitchThread( xThreadToResume, xThreadToSuspend ); +} +/*-----------------------------------------------------------*/ + +void vPortYield( void ) +{ + vPortEnterCritical(); + + vPortYieldFromISR(); + + vPortExitCritical(); +} +/*-----------------------------------------------------------*/ + +void vPortDisableInterrupts( void ) +{ + pthread_sigmask( SIG_BLOCK, &xAllSignals, NULL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnableInterrupts( void ) +{ + pthread_sigmask( SIG_UNBLOCK, &xAllSignals, NULL ); +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortSetInterruptMask( void ) +{ + /* Interrupts are always disabled inside ISRs (signals + handlers). */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMask( portBASE_TYPE xMask ) +{ +} +/*-----------------------------------------------------------*/ + +static uint64_t prvGetTimeNs(void) +{ +struct timespec t; + + clock_gettime(CLOCK_MONOTONIC, &t); + + return t.tv_sec * 1000000000ull + t.tv_nsec; +} + +static uint64_t prvStartTimeNs; +/* commented as part of the code below in vPortSystemTickHandler, + * to adjust timing according to full demo requirements */ +/* static uint64_t prvTickCount; */ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +void prvSetupTimerInterrupt( void ) +{ +struct itimerval itimer; +int iRet; + + /* Initialise the structure with the current timer information. */ + iRet = getitimer( ITIMER_REAL, &itimer ); + if ( iRet ) + { + prvFatalError( "getitimer", errno ); + } + + /* Set the interval between timer events. */ + itimer.it_interval.tv_sec = 0; + itimer.it_interval.tv_usec = portTICK_RATE_MICROSECONDS; + + /* Set the current count-down. */ + itimer.it_value.tv_sec = 0; + itimer.it_value.tv_usec = portTICK_RATE_MICROSECONDS; + + /* Set-up the timer interrupt. */ + iRet = setitimer( ITIMER_REAL, &itimer, NULL ); + if ( iRet ) + { + prvFatalError( "setitimer", errno ); + } + + prvStartTimeNs = prvGetTimeNs(); +} +/*-----------------------------------------------------------*/ + +static void vPortSystemTickHandler( int sig ) +{ +Thread_t *pxThreadToSuspend; +Thread_t *pxThreadToResume; +/* uint64_t xExpectedTicks; */ + + uxCriticalNesting++; /* Signals are blocked in this signal handler. */ + +#if ( configUSE_PREEMPTION == 1 ) + pxThreadToSuspend = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() ); +#endif + + /* Tick Increment, accounting for any lost signals or drift in + * the timer. */ +/* + * Comment code to adjust timing according to full demo requirements + * xExpectedTicks = (prvGetTimeNs() - prvStartTimeNs) + * / (portTICK_RATE_MICROSECONDS * 1000); + * do { */ + xTaskIncrementTick(); +/* prvTickCount++; + * } while (prvTickCount < xExpectedTicks); +*/ + +#if ( configUSE_PREEMPTION == 1 ) + /* Select Next Task. */ + vTaskSwitchContext(); + + pxThreadToResume = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() ); + + prvSwitchThread(pxThreadToResume, pxThreadToSuspend); +#endif + + uxCriticalNesting--; +} +/*-----------------------------------------------------------*/ + +void vPortThreadDying( void *pxTaskToDelete, volatile BaseType_t *pxPendYield ) +{ +Thread_t *pxThread = prvGetThreadFromTask( pxTaskToDelete ); + + pxThread->xDying = pdTRUE; +} + +void vPortCancelThread( void *pxTaskToDelete ) +{ +Thread_t *pxThreadToCancel = prvGetThreadFromTask( pxTaskToDelete ); + + /* + * The thread has already been suspended so it can be safely cancelled. + */ + pthread_cancel( pxThreadToCancel->pthread ); + pthread_join( pxThreadToCancel->pthread, NULL ); + event_delete( pxThreadToCancel->ev ); +} +/*-----------------------------------------------------------*/ + +static void *prvWaitForStart( void * pvParams ) +{ +Thread_t *pxThread = pvParams; + + prvSuspendSelf(pxThread); + + /* Resumed for the first time, unblocks all signals. */ + uxCriticalNesting = 0; + vPortEnableInterrupts(); + + /* Call the task's entry point. */ + pxThread->pxCode( pxThread->pvParams ); + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, so application writers can + * catch the error. */ + configASSERT( pdFALSE ); + + return NULL; +} +/*-----------------------------------------------------------*/ + +static void prvSwitchThread( Thread_t *pxThreadToResume, + Thread_t *pxThreadToSuspend ) +{ +BaseType_t uxSavedCriticalNesting; + + if ( pxThreadToSuspend != pxThreadToResume ) + { + /* + * Switch tasks. + * + * The critical section nesting is per-task, so save it on the + * stack of the current (suspending thread), restoring it when + * we switch back to this task. + */ + uxSavedCriticalNesting = uxCriticalNesting; + + prvResumeThread( pxThreadToResume ); + if ( pxThreadToSuspend->xDying ) + { + pthread_exit( NULL ); + } + prvSuspendSelf( pxThreadToSuspend ); + + uxCriticalNesting = uxSavedCriticalNesting; + } +} +/*-----------------------------------------------------------*/ + +static void prvSuspendSelf( Thread_t *thread ) +{ + /* + * Suspend this thread by waiting for a pthread_cond_signal event. + * + * A suspended thread must not handle signals (interrupts) so + * all signals must be blocked by calling this from: + * + * - Inside a critical section (vPortEnterCritical() / + * vPortExitCritical()). + * + * - From a signal handler that has all signals masked. + * + * - A thread with all signals blocked with pthread_sigmask(). + */ + event_wait(thread->ev); +} + +/*-----------------------------------------------------------*/ + +static void prvResumeThread( Thread_t *xThreadId ) +{ + if ( pthread_self() != xThreadId->pthread ) + { + event_signal(xThreadId->ev); + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupSignalsAndSchedulerPolicy( void ) +{ +struct sigaction sigresume, sigtick; +int iRet; + + hMainThread = pthread_self(); + + /* Initialise common signal masks. */ + sigfillset( &xAllSignals ); + /* Don't block SIGINT so this can be used to break into GDB while + * in a critical section. */ + sigdelset( &xAllSignals, SIGINT ); + + /* + * Block all signals in this thread so all new threads + * inherits this mask. + * + * When a thread is resumed for the first time, all signals + * will be unblocked. + */ + (void)pthread_sigmask( SIG_SETMASK, &xAllSignals, + &xSchedulerOriginalSignalMask ); + + /* SIG_RESUME is only used with sigwait() so doesn't need a + handler. */ + sigresume.sa_flags = 0; + sigresume.sa_handler = SIG_IGN; + sigfillset( &sigresume.sa_mask ); + + sigtick.sa_flags = 0; + sigtick.sa_handler = vPortSystemTickHandler; + sigfillset( &sigtick.sa_mask ); + + iRet = sigaction( SIG_RESUME, &sigresume, NULL ); + if ( iRet ) + { + prvFatalError( "sigaction", errno ); + } + + iRet = sigaction( SIGALRM, &sigtick, NULL ); + if ( iRet ) + { + prvFatalError( "sigaction", errno ); + } +} +/*-----------------------------------------------------------*/ + +unsigned long ulPortGetRunTime( void ) +{ +struct tms xTimes; + + times( &xTimes ); + + return ( unsigned long ) xTimes.tms_utime; +} +/*-----------------------------------------------------------*/ diff --git a/components/freertos/FreeRTOS-Kernel/portable/linux/port_idf.c b/components/freertos/FreeRTOS-Kernel/portable/linux/port_idf.c new file mode 100644 index 0000000000..bb4db35dcb --- /dev/null +++ b/components/freertos/FreeRTOS-Kernel/portable/linux/port_idf.c @@ -0,0 +1,164 @@ +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * This file contains most of the code located in the demo application in the + * upstream FreeRTOS repository. It is put here so that IDF applications can + * seamlessly switch between Linux and chip targets without the need to provide + * or implement additional functionality if the target is the Linux target. + */ + +#include +#include +#include +#include +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "utils/wait_for_event.h" +#include "esp_log.h" + +static const char *TAG = "port"; + +static volatile UBaseType_t uxInterruptNesting = 0; + +/* When configSUPPORT_STATIC_ALLOCATION is set to 1 the application writer can + * use a callback function to optionally provide the memory required by the idle + * and timer tasks. This is the stack that will be used by the timer task. It is + * declared here, as a global, so it can be checked by a test that is implemented + * in a different file. */ +StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; + +BaseType_t xPortCheckIfInISR(void) +{ + return uxInterruptNesting; +} + +void app_main(void); + +static void main_task(void* args) +{ + app_main(); + vTaskDelete(NULL); +} + +int main(int argc, const char **argv) +{ + // This makes sure that stdio is flushed after each '\n' so that idf.py monitor + // reads the program output on time. + setvbuf(stdout, NULL, _IOLBF, 0); + + usleep(1000); + portBASE_TYPE res = xTaskCreatePinnedToCore(&main_task, "main", + ESP_TASK_MAIN_STACK, NULL, + ESP_TASK_MAIN_PRIO, NULL, ESP_TASK_MAIN_CORE); + assert(res == pdTRUE); + (void)res; + + ESP_LOGI(TAG, "Starting scheduler."); + vTaskStartScheduler(); + + // This line should never be reached + assert(false); +} + +void esp_vApplicationIdleHook(void) +{ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + * to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle + * task. It is essential that code added to this hook function never attempts + * to block in any way (for example, call xQueueReceive() with a block time + * specified, or call vTaskDelay()). If application tasks make use of the + * vTaskDelete() API function to delete themselves then it is also important + * that vApplicationIdleHook() is permitted to return to its calling function, + * because it is the responsibility of the idle task to clean up memory + * allocated by the kernel to any task that has since deleted itself. */ + + + usleep( 15000 ); +} + +void esp_vApplicationTickHook( void ) { } + +#if ( configUSE_TICK_HOOK > 0 ) +void vApplicationTickHook( void ) +{ + esp_vApplicationTickHook(); +} +#endif + +void vPortYieldOtherCore( BaseType_t coreid ) { } // trying to skip for now + +/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an + * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is + * used by the Idle task. */ +void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ) +{ +/* If the buffers to be provided to the Idle task are declared inside this + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Idle task's + * state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; +} +/*-----------------------------------------------------------*/ + +/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the + * application must provide an implementation of vApplicationGetTimerTaskMemory() + * to provide the memory that is used by the Timer service task. */ +void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ) +{ +/* If the buffers to be provided to the Timer task are declared inside this + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xTimerTaskTCB; + + /* Pass out a pointer to the StaticTask_t structure in which the Timer + * task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; +} + +void __attribute__((weak)) vApplicationStackOverflowHook(TaskHandle_t xTask, char *pcTaskName) +{ +#define ERR_STR1 "***ERROR*** A stack overflow in task " +#define ERR_STR2 " has been detected." + const char *str[] = {ERR_STR1, pcTaskName, ERR_STR2}; + + char buf[sizeof(ERR_STR1) + CONFIG_FREERTOS_MAX_TASK_NAME_LEN + sizeof(ERR_STR2) + 1 /* null char */] = {0}; + + char *dest = buf; + for (int i = 0; i < sizeof(str) / sizeof(str[0]); i++) { + dest = strcat(dest, str[i]); + } + printf("%s\n", buf); + abort(); +} diff --git a/components/freertos/FreeRTOS-Kernel/portable/linux/utils/wait_for_event.c b/components/freertos/FreeRTOS-Kernel/portable/linux/utils/wait_for_event.c new file mode 100644 index 0000000000..d3e5f03226 --- /dev/null +++ b/components/freertos/FreeRTOS-Kernel/portable/linux/utils/wait_for_event.c @@ -0,0 +1,109 @@ +/* + * SPDX-FileCopyrightText: 2021 Amazon.com, Inc. or its affiliates + * + * SPDX-License-Identifier: MIT + */ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include +#include +#include + +#include "wait_for_event.h" + +struct event +{ + pthread_mutex_t mutex; + pthread_cond_t cond; + bool event_triggered; +}; + +struct event * event_create() +{ + struct event * ev = malloc( sizeof( struct event ) ); + + ev->event_triggered = false; + pthread_mutex_init( &ev->mutex, NULL ); + pthread_cond_init( &ev->cond, NULL ); + return ev; +} + +void event_delete( struct event * ev ) +{ + pthread_mutex_destroy( &ev->mutex ); + pthread_cond_destroy( &ev->cond ); + free( ev ); +} + +bool event_wait( struct event * ev ) +{ + pthread_mutex_lock( &ev->mutex ); + + while( ev->event_triggered == false ) + { + pthread_cond_wait( &ev->cond, &ev->mutex ); + } + + ev->event_triggered = false; + pthread_mutex_unlock( &ev->mutex ); + return true; +} +bool event_wait_timed( struct event * ev, + time_t ms ) +{ + struct timespec ts; + int ret = 0; + + clock_gettime( CLOCK_REALTIME, &ts ); + ts.tv_sec += ms / 1000; + ts.tv_nsec += ((ms % 1000) * 1000000); + pthread_mutex_lock( &ev->mutex ); + + while( (ev->event_triggered == false) && (ret == 0) ) + { + ret = pthread_cond_timedwait( &ev->cond, &ev->mutex, &ts ); + + if( ( ret == -1 ) && ( errno == ETIMEDOUT ) ) + { + return false; + } + } + + ev->event_triggered = false; + pthread_mutex_unlock( &ev->mutex ); + return true; +} + +void event_signal( struct event * ev ) +{ + pthread_mutex_lock( &ev->mutex ); + ev->event_triggered = true; + pthread_cond_signal( &ev->cond ); + pthread_mutex_unlock( &ev->mutex ); +} diff --git a/components/freertos/FreeRTOS-Kernel/portable/linux/utils/wait_for_event.h b/components/freertos/FreeRTOS-Kernel/portable/linux/utils/wait_for_event.h new file mode 100644 index 0000000000..45336238c5 --- /dev/null +++ b/components/freertos/FreeRTOS-Kernel/portable/linux/utils/wait_for_event.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: 2021 Amazon.com, Inc. or its affiliates + * + * SPDX-License-Identifier: MIT + */ +/* + * FreeRTOS Kernel V10.4.6 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef _WAIT_FOR_EVENT_H_ +#define _WAIT_FOR_EVENT_H_ + +#include +#include + +struct event; + +struct event * event_create(); +void event_delete( struct event * ); +bool event_wait( struct event * ev ); +bool event_wait_timed( struct event * ev, + time_t ms ); +void event_signal( struct event * ev ); + + + +#endif /* ifndef _WAIT_FOR_EVENT_H_ */ diff --git a/components/freertos/FreeRTOS-Kernel/portable/port_common.c b/components/freertos/FreeRTOS-Kernel/portable/port_common.c index 15c74fe939..420ad29ded 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/port_common.c +++ b/components/freertos/FreeRTOS-Kernel/portable/port_common.c @@ -111,7 +111,7 @@ static void main_task(void* args) #endif //Initialize TWDT if configured to do so -#if CONFIG_ESP_TASK_WDT +#if CONFIG_ESP_TASK_WDT_INIT esp_task_wdt_config_t twdt_config = { .timeout_ms = CONFIG_ESP_TASK_WDT_TIMEOUT_S * 1000, .idle_core_mask = 0, diff --git a/components/freertos/FreeRTOS-Kernel/portable/port_systick.c b/components/freertos/FreeRTOS-Kernel/portable/port_systick.c index 9031ef81bd..2c12f72f89 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/port_systick.c +++ b/components/freertos/FreeRTOS-Kernel/portable/port_systick.c @@ -16,7 +16,6 @@ #include "sdkconfig.h" #ifdef CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER #include "soc/periph_defs.h" -#include "soc/system_reg.h" #include "hal/systimer_hal.h" #include "hal/systimer_ll.h" #endif diff --git a/components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h b/components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h index d719560520..82446da536 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h +++ b/components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h @@ -43,7 +43,7 @@ #include #include #include "spinlock.h" -#include "soc/interrupt_core0_reg.h" +#include "soc/interrupt_reg.h" #include "esp_macros.h" #include "esp_attr.h" #include "esp_cpu.h" @@ -108,6 +108,7 @@ typedef uint32_t TickType_t; #define portSTACK_GROWTH (-1) #define portTICK_PERIOD_MS ((TickType_t) (1000 / configTICK_RATE_HZ)) #define portBYTE_ALIGNMENT 16 +#define portTICK_TYPE_IS_ATOMIC 1 #define portNOP() __asm volatile (" nop ") diff --git a/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c b/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c index c493ded1f2..85b92fa2c8 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c +++ b/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c @@ -44,7 +44,7 @@ #include "hal/systimer_hal.h" #include "hal/systimer_ll.h" #include "riscv/rvruntime-frames.h" -#include "riscv/riscv_interrupts.h" +#include "riscv/rv_utils.h" #include "riscv/interrupt.h" #include "esp_private/crosscore_int.h" #include "esp_attr.h" @@ -88,7 +88,6 @@ StackType_t *xIsrStackTop = &xIsrStack[0] + (configISR_STACK_SIZE & (~((portPOIN // ----------------- Scheduler Start/End ------------------- -extern void esprv_intc_int_set_threshold(int); // FIXME, this function is in ROM only BaseType_t xPortStartScheduler(void) { uxInterruptNesting = 0; @@ -99,7 +98,7 @@ BaseType_t xPortStartScheduler(void) vPortSetupTimer(); esprv_intc_int_set_threshold(1); /* set global INTC masking level */ - riscv_global_interrupts_enable(); + rv_utils_intr_global_enable(); vPortYield(); @@ -140,78 +139,161 @@ __attribute__((naked)) static void prvTaskExitError(void) _prvTaskExitError(); } -StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters) +/** + * @brief Align stack pointer in a downward growing stack + * + * This macro is used to round a stack pointer downwards to the nearest n-byte boundary, where n is a power of 2. + * This macro is generally used when allocating aligned areas on a downward growing stack. + */ +#define STACKPTR_ALIGN_DOWN(n, ptr) ((ptr) & (~((n)-1))) + +/** + * @brief Allocate and initialize GCC TLS area + * + * This function allocates and initializes the area on the stack used to store GCC TLS (Thread Local Storage) variables. + * - The area's size is derived from the TLS section's linker variables, and rounded up to a multiple of 16 bytes + * - The allocated area is aligned to a 16-byte aligned address + * - The TLS variables in the area are then initialized + * + * Each task access the TLS variables using the THREADPTR register plus an offset to obtain the address of the variable. + * The value for the THREADPTR register is also calculated by this function, and that value should be use to initialize + * the THREADPTR register. + * + * @param[in] uxStackPointer Current stack pointer address + * @param[out] ret_threadptr_reg_init Calculated THREADPTR register initialization value + * @return Stack pointer that points to the TLS area + */ +FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackTLS(UBaseType_t uxStackPointer, uint32_t *ret_threadptr_reg_init) { - extern uint32_t __global_pointer$; - uint8_t *task_thread_local_start; - uint8_t *threadptr; + /* + TLS layout at link-time, where 0xNNN is the offset that the linker calculates to a particular TLS variable. + + LOW ADDRESS + |---------------------------| Linker Symbols + | Section | -------------- + | .flash.rodata | + 0x0|---------------------------| <- _flash_rodata_start + ^ | Other Data | + | |---------------------------| <- _thread_local_start + | | .tbss | ^ + V | | | + 0xNNN | int example; | | tls_area_size + | | | + | .tdata | V + |---------------------------| <- _thread_local_end + | Other data | + | ... | + |---------------------------| + HIGH ADDRESS + */ + // Calculate TLS area size and round up to multiple of 16 bytes. extern char _thread_local_start, _thread_local_end, _flash_rodata_start; + const uint32_t tls_area_size = ALIGNUP(16, (uint32_t)&_thread_local_end - (uint32_t)&_thread_local_start); + // TODO: check that TLS area fits the stack - /* Byte pointer, so that subsequent calculations don't depend on sizeof(StackType_t). */ - uint8_t *sp = (uint8_t *) pxTopOfStack; + // Allocate space for the TLS area on the stack. The area must be aligned to 16-bytes + uxStackPointer = STACKPTR_ALIGN_DOWN(16, uxStackPointer - (UBaseType_t)tls_area_size); + // Initialize the TLS area with the initialization values of each TLS variable + memcpy((void *)uxStackPointer, &_thread_local_start, tls_area_size); - /* Set up TLS area. - * The following diagram illustrates the layout of link-time and run-time - * TLS sections. - * - * +-------------+ - * |Section: | Linker symbols: - * |.flash.rodata| --------------- - * 0x0+-------------+ <-- _flash_rodata_start - * ^ | | - * | | Other data | - * | | ... | - * | +-------------+ <-- _thread_local_start - * | |.tbss | ^ - * v | | | - * 0xNNNN|int example; | | (thread_local_size) - * |.tdata | v - * +-------------+ <-- _thread_local_end - * | Other data | - * | ... | - * | | - * +-------------+ - * - * Local variables of - * pxPortInitialiseStack - * ----------------------- - * +-------------+ <-- pxTopOfStack - * |.tdata (*) | ^ - * ^ |int example; | |(thread_local_size - * | | | | - * | |.tbss (*) | v - * | +-------------+ <-- task_thread_local_start - * 0xNNNN | | | ^ - * | | | | - * | | | |_thread_local_start - _rodata_start - * | | | | - * | | | v - * v +-------------+ <-- threadptr - * - * (*) The stack grows downward! - */ + /* + Calculate the THREADPTR register's initialization value based on the link-time offset and the TLS area allocated on + the stack. - uint32_t thread_local_sz = (uint32_t) (&_thread_local_end - &_thread_local_start); - thread_local_sz = ALIGNUP(0x10, thread_local_sz); - sp -= thread_local_sz; - task_thread_local_start = sp; - memcpy(task_thread_local_start, &_thread_local_start, thread_local_sz); - threadptr = task_thread_local_start - (&_thread_local_start - &_flash_rodata_start); + HIGH ADDRESS + |---------------------------| + | .tdata (*) | + ^ | int example; | + | | | + | | .tbss (*) | + | |---------------------------| <- uxStackPointer (start of TLS area) + 0xNNN | | | ^ + | | | | + | ... | _thread_local_start - _rodata_start + | | | | + | | | V + V | | <- threadptr register's value - /* Simulate the stack frame as it would be created by a context switch interrupt. */ - sp -= RV_STK_FRMSZ; - RvExcFrame *frame = (RvExcFrame *)sp; - memset(frame, 0, sizeof(*frame)); - /* Shifting RA into prvTaskExitError is necessary to make GDB backtrace ending inside that function. - Otherwise backtrace will end in the function laying just before prvTaskExitError in address space. */ - frame->ra = (UBaseType_t)prvTaskExitError + 4/*size of the nop insruction at the beginning of prvTaskExitError*/; + LOW ADDRESS + */ + *ret_threadptr_reg_init = (uint32_t)uxStackPointer - ((uint32_t)&_thread_local_start - (uint32_t)&_flash_rodata_start); + return uxStackPointer; +} + +/** + * @brief Initialize the task's starting interrupt stack frame + * + * This function initializes the task's starting interrupt stack frame. The dispatcher will use this stack frame in a + * context restore routine. Therefore, the starting stack frame must be initialized as if the task was interrupted right + * before its first instruction is called. + * + * - The stack frame is allocated to a 16-byte aligned address + * + * @param[in] uxStackPointer Current stack pointer address + * @param[in] pxCode Task function + * @param[in] pvParameters Task function's parameter + * @param[in] threadptr_reg_init THREADPTR register initialization value + * @return Stack pointer that points to the stack frame + */ +FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackFrame(UBaseType_t uxStackPointer, TaskFunction_t pxCode, void *pvParameters, uint32_t threadptr_reg_init) +{ + /* + Allocate space for the task's starting interrupt stack frame. + - The stack frame must be allocated to a 16-byte aligned address. + - We use XT_STK_FRMSZ (instead of sizeof(XtExcFrame)) as it rounds up the total size to a multiple of 16. + */ + uxStackPointer = STACKPTR_ALIGN_DOWN(16, uxStackPointer - RV_STK_FRMSZ); + + // Clear the entire interrupt stack frame + RvExcFrame *frame = (RvExcFrame *)uxStackPointer; + memset(frame, 0, sizeof(RvExcFrame)); + + /* + Initialize the stack frame. + + Note: Shifting RA into prvTaskExitError is necessary to make the GDB backtrace terminate inside that function. + Otherwise, the backtrace will end in the function located just before prvTaskExitError in the address space. + */ + extern uint32_t __global_pointer$; + frame->ra = (UBaseType_t)prvTaskExitError + 4; // size of the nop instruction at the beginning of prvTaskExitError frame->mepc = (UBaseType_t)pxCode; frame->a0 = (UBaseType_t)pvParameters; frame->gp = (UBaseType_t)&__global_pointer$; - frame->tp = (UBaseType_t)threadptr; + frame->tp = (UBaseType_t)threadptr_reg_init; + return uxStackPointer; +} + +StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters) +{ + /* + HIGH ADDRESS + |---------------------------| <- pxTopOfStack on entry + | TLS Variables | + | ------------------------- | <- Start of useable stack + | Starting stack frame | + | ------------------------- | <- pxTopOfStack on return (which is the tasks current SP) + | | | + | | | + | V | + ----------------------------- <- Bottom of stack + LOW ADDRESS + + - All stack areas are aligned to 16 byte boundary + - We use UBaseType_t for all of stack area initialization functions for more convenient pointer arithmetic + */ + + UBaseType_t uxStackPointer = (UBaseType_t)pxTopOfStack; + + // Initialize GCC TLS area + uint32_t threadptr_reg_init; + uxStackPointer = uxInitialiseStackTLS(uxStackPointer, &threadptr_reg_init); + + // Initialize the starting interrupt stack frame + uxStackPointer = uxInitialiseStackFrame(uxStackPointer, pxCode, pvParameters, threadptr_reg_init); + // Return the task's current stack pointer address which should point to the starting interrupt stack frame + return (StackType_t *)uxStackPointer; //TODO: IDF-2393 - return (StackType_t *)frame; } diff --git a/components/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h b/components/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h index a2780e2cd4..06b52e908e 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h +++ b/components/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h @@ -140,6 +140,7 @@ typedef uint32_t TickType_t; #define portSTACK_GROWTH ( -1 ) #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) #define portBYTE_ALIGNMENT 4 +#define portTICK_TYPE_IS_ATOMIC 1 #define portNOP() XT_NOP() diff --git a/components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c b/components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c index 0a631d2172..004bf10bb3 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c +++ b/components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c @@ -64,6 +64,7 @@ #include #include #include "soc/soc_caps.h" +#include "esp_attr.h" #include "esp_private/crosscore_int.h" #include "esp_private/esp_int_wdt.h" #include "esp_system.h" @@ -156,112 +157,280 @@ static void vPortTaskWrapper(TaskFunction_t pxCode, void *pvParameters) } #endif +/** + * @brief Align stack pointer in a downward growing stack + * + * This macro is used to round a stack pointer downwards to the nearest n-byte boundary, where n is a power of 2. + * This macro is generally used when allocating aligned areas on a downward growing stack. + */ +#define STACKPTR_ALIGN_DOWN(n, ptr) ((ptr) & (~((n)-1))) + +#if XCHAL_CP_NUM > 0 +/** + * @brief Allocate and initialize coprocessor save area on the stack + * + * This function allocates the coprocessor save area on the stack (sized XT_CP_SIZE) which includes... + * - Individual save areas for each coprocessor (size XT_CPx_SA, inclusive of each area's alignment) + * - Coprocessor context switching flags (e.g., XT_CPENABLE, XT_CPSTORED, XT_CP_CS_ST, XT_CP_ASA). + * + * The coprocessor save area is aligned to a 16-byte boundary. + * The coprocessor context switching flags are then initialized + * + * @param[in] uxStackPointer Current stack pointer address + * @return Stack pointer that points to allocated and initialized the coprocessor save area + */ +FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackCPSA(UBaseType_t uxStackPointer) +{ + /* + HIGH ADDRESS + |-------------------| XT_CP_SIZE + | CPn SA | ^ + | ... | | + | CP0 SA | | + | ----------------- | | ---- XCHAL_TOTAL_SA_ALIGN aligned + |-------------------| | 12 bytes + | XT_CP_ASA | | ^ + | XT_CP_CS_ST | | | + | XT_CPSTORED | | | + | XT_CPENABLE | | | + |-------------------| ---------------------- 16 byte aligned + LOW ADDRESS + */ + + // Allocate overall coprocessor save area, aligned down to 16 byte boundary + uxStackPointer = STACKPTR_ALIGN_DOWN(16, uxStackPointer - XT_CP_SIZE); + // Initialize the coprocessor context switching flags. + uint32_t *p = (uint32_t *)uxStackPointer; + p[0] = 0; // Clear XT_CPENABLE and XT_CPSTORED + p[1] = 0; // Clear XT_CP_CS_ST + // XT_CP_ASA points to the aligned start of the individual CP save areas (i.e., start of CP0 SA) + p[2] = (uint32_t)ALIGNUP(XCHAL_TOTAL_SA_ALIGN, (uint32_t)uxStackPointer + 12); + return uxStackPointer; +} +#endif /* XCHAL_CP_NUM > 0 */ + +/** + * @brief Allocate and initialize GCC TLS area + * + * This function allocates and initializes the area on the stack used to store GCC TLS (Thread Local Storage) variables. + * - The area's size is derived from the TLS section's linker variables, and rounded up to a multiple of 16 bytes + * - The allocated area is aligned to a 16-byte aligned address + * - The TLS variables in the area are then initialized + * + * Each task access the TLS variables using the THREADPTR register plus an offset to obtain the address of the variable. + * The value for the THREADPTR register is also calculated by this function, and that value should be use to initialize + * the THREADPTR register. + * + * @param[in] uxStackPointer Current stack pointer address + * @param[out] ret_threadptr_reg_init Calculated THREADPTR register initialization value + * @return Stack pointer that points to the TLS area + */ +FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackTLS(UBaseType_t uxStackPointer, uint32_t *ret_threadptr_reg_init) +{ + /* + TLS layout at link-time, where 0xNNN is the offset that the linker calculates to a particular TLS variable. + + LOW ADDRESS + |---------------------------| Linker Symbols + | Section | -------------- + | .flash.rodata | + 0x0|---------------------------| <- _flash_rodata_start + ^ | Other Data | + | |---------------------------| <- _thread_local_start + | | .tbss | ^ + V | | | + 0xNNN | int example; | | tls_area_size + | | | + | .tdata | V + |---------------------------| <- _thread_local_end + | Other data | + | ... | + |---------------------------| + HIGH ADDRESS + */ + // Calculate the TLS area's size (rounded up to multiple of 16 bytes). + extern int _thread_local_start, _thread_local_end, _flash_rodata_start, _flash_rodata_align; + const uint32_t tls_area_size = ALIGNUP(16, (uint32_t)&_thread_local_end - (uint32_t)&_thread_local_start); + // TODO: check that TLS area fits the stack + + // Allocate space for the TLS area on the stack. The area must be allocated at a 16-byte aligned address + uxStackPointer = STACKPTR_ALIGN_DOWN(16, uxStackPointer - (UBaseType_t)tls_area_size); + // Initialize the TLS area with the initialization values of each TLS variable + memcpy((void *)uxStackPointer, &_thread_local_start, tls_area_size); + + /* + Calculate the THREADPTR register's initialization value based on the link-time offset and the TLS area allocated on + the stack. + + HIGH ADDRESS + |---------------------------| + | .tdata (*) | + ^ | int example; | + | | | + | | .tbss (*) | + | |---------------------------| <- uxStackPointer (start of TLS area) + 0xNNN | | | ^ + | | | | + | ... | (_thread_local_start - _flash_rodata_start) + align_up(TCB_SIZE, tls_section_alignment) + | | | | + | | | V + V | | <- threadptr register's value + + LOW ADDRESS + + Note: Xtensa is slightly different compared to the RISC-V port as there is an implicit aligned TCB_SIZE added to + the offset. (search for 'tpoff' in elf32-xtensa.c in BFD): + - "offset = address - tls_section_vma + align_up(TCB_SIZE, tls_section_alignment)" + - TCB_SIZE is hardcoded to 8 + */ + const uint32_t tls_section_align = (uint32_t)&_flash_rodata_align; // ALIGN value of .flash.rodata section + #define TCB_SIZE 8 + const uint32_t base = ALIGNUP(tls_section_align, TCB_SIZE); + *ret_threadptr_reg_init = (uint32_t)uxStackPointer - ((uint32_t)&_thread_local_start - (uint32_t)&_flash_rodata_start) - base; + + return uxStackPointer; +} + +/** + * @brief Initialize the task's starting interrupt stack frame + * + * This function initializes the task's starting interrupt stack frame. The dispatcher will use this stack frame in a + * context restore routine. Therefore, the starting stack frame must be initialized as if the task was interrupted right + * before its first instruction is called. + * + * - The stack frame is allocated to a 16-byte aligned address + * - The THREADPTR register is saved in the extra storage area of the stack frame. This is also initialized + * + * @param[in] uxStackPointer Current stack pointer address + * @param[in] pxCode Task function + * @param[in] pvParameters Task function's parameter + * @param[in] threadptr_reg_init THREADPTR register initialization value + * @return Stack pointer that points to the stack frame + */ +FORCE_INLINE_ATTR UBaseType_t uxInitialiseStackFrame(UBaseType_t uxStackPointer, TaskFunction_t pxCode, void *pvParameters, uint32_t threadptr_reg_init) +{ + /* + HIGH ADDRESS + |---------------------------| ^ XT_STK_FRMSZ + | | | + | Stack Frame Extra Storage | | + | | | + | ------------------------- | | ^ XT_STK_EXTRA + | | | | + | Intr/Exc Stack Frame | | | + | | V V + | ------------------------- | ---------------------- 16 byte aligned + LOW ADDRESS + */ + + /* + Allocate space for the task's starting interrupt stack frame. + - The stack frame must be allocated to a 16-byte aligned address. + - We use XT_STK_FRMSZ (instead of sizeof(XtExcFrame)) as it... + - includes the size of the extra storage area + - includes the size for a base save area before the stack frame + - rounds up the total size to a multiple of 16 + */ + UBaseType_t uxStackPointerPrevious = uxStackPointer; + uxStackPointer = STACKPTR_ALIGN_DOWN(16, uxStackPointer - XT_STK_FRMSZ); + + // Clear the entire interrupt stack frame + memset((void *)uxStackPointer, 0, (size_t)(uxStackPointerPrevious - uxStackPointer)); + + XtExcFrame *frame = (XtExcFrame *)uxStackPointer; + + /* + Initialize common registers + */ + frame->a0 = 0; // Set the return address to 0 terminate GDB backtrace + frame->a1 = uxStackPointer + XT_STK_FRMSZ; // Saved stack pointer should point to physical top of stack frame + frame->exit = (UBaseType_t) _xt_user_exit; // User exception exit dispatcher + + /* + Initialize the task's entry point. This will differ depending on + - Whether the task's entry point is the wrapper function or pxCode + - Whether Windowed ABI is used (for windowed, we mimic the task entry point being call4'd ) + */ + #if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER + frame->pc = (UBaseType_t) vPortTaskWrapper; // Task entry point is the wrapper function + #ifdef __XTENSA_CALL0_ABI__ + frame->a2 = (UBaseType_t) pxCode; // Wrapper function's argument 0 (which is the task function) + frame->a3 = (UBaseType_t) pvParameters; // Wrapper function's argument 1 (which is the task function's argument) + #else // __XTENSA_CALL0_ABI__ + frame->a6 = (UBaseType_t) pxCode; // Wrapper function's argument 0 (which is the task function), passed as if we call4'd + frame->a7 = (UBaseType_t) pvParameters; // Wrapper function's argument 1 (which is the task function's argument), passed as if we call4'd + #endif // __XTENSA_CALL0_ABI__ + #else + frame->pc = (UBaseType_t) pxCode; // Task entry point is the provided task function + #ifdef __XTENSA_CALL0_ABI__ + frame->a2 = (UBaseType_t) pvParameters; // Task function's argument + #else // __XTENSA_CALL0_ABI__ + frame->a6 = (UBaseType_t) pvParameters; // Task function's argument, passed as if we call4'd + #endif // __XTENSA_CALL0_ABI__ + #endif + + /* + Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. + For windowed ABI also set WOE and CALLINC (pretend task was 'call4'd) + */ + #ifdef __XTENSA_CALL0_ABI__ + frame->ps = PS_UM | PS_EXCM; + #else // __XTENSA_CALL0_ABI__ + frame->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1); + #endif // __XTENSA_CALL0_ABI__ + + #ifdef XT_USE_SWPRI + // Set the initial virtual priority mask value to all 1's. + frame->vpri = 0xFFFFFFFF; + #endif + + // Initialize the threadptr register in the extra save area of the stack frame + uint32_t *threadptr_reg = (uint32_t *)(uxStackPointer + XT_STK_EXTRA); + *threadptr_reg = threadptr_reg_init; + + return uxStackPointer; +} + #if portUSING_MPU_WRAPPERS -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) +StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged) #else -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) #endif { - StackType_t *sp, *tp; - XtExcFrame *frame; -#if XCHAL_CP_NUM > 0 - uint32_t *p; -#endif - uint32_t *threadptr; - void *task_thread_local_start; - extern int _thread_local_start, _thread_local_end, _flash_rodata_start, _flash_rodata_align; - // TODO: check that TLS area fits the stack - uint32_t thread_local_sz = (uint8_t *)&_thread_local_end - (uint8_t *)&_thread_local_start; + /* + HIGH ADDRESS + |---------------------------| <- pxTopOfStack on entry + | Coproc Save Area | + | ------------------------- | + | TLS Variables | + | ------------------------- | <- Start of useable stack + | Starting stack frame | + | ------------------------- | <- pxTopOfStack on return (which is the tasks current SP) + | | | + | | | + | V | + ----------------------------- <- Bottom of stack + LOW ADDRESS - thread_local_sz = ALIGNUP(0x10, thread_local_sz); + - All stack areas are aligned to 16 byte boundary + - We use UBaseType_t for all of stack area initialization functions for more convenient pointer arithmetic + */ - /* Initialize task's stack so that we have the following structure at the top: - - ----LOW ADDRESSES ----------------------------------------HIGH ADDRESSES---------- - task stack | interrupt stack frame | thread local vars | co-processor save area | - ---------------------------------------------------------------------------------- - | | - SP pxTopOfStack - - All parts are aligned to 16 byte boundary. */ - sp = (StackType_t *) (((UBaseType_t)pxTopOfStack - XT_CP_SIZE - thread_local_sz - XT_STK_FRMSZ) & ~0xf); - - /* Clear the entire frame (do not use memset() because we don't depend on C library) */ - for (tp = sp; tp <= pxTopOfStack; ++tp) { - *tp = 0; - } - - frame = (XtExcFrame *) sp; - - /* Explicitly initialize certain saved registers */ -#if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER - frame->pc = (UBaseType_t) vPortTaskWrapper; /* task wrapper */ -#else - frame->pc = (UBaseType_t) pxCode; /* task entrypoint */ -#endif - frame->a0 = 0; /* to terminate GDB backtrace */ - frame->a1 = (UBaseType_t) sp + XT_STK_FRMSZ; /* physical top of stack frame */ - frame->exit = (UBaseType_t) _xt_user_exit; /* user exception exit dispatcher */ - - /* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. */ - /* Also set entry point argument parameter. */ -#ifdef __XTENSA_CALL0_ABI__ -#if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER - frame->a2 = (UBaseType_t) pxCode; - frame->a3 = (UBaseType_t) pvParameters; -#else - frame->a2 = (UBaseType_t) pvParameters; -#endif - frame->ps = PS_UM | PS_EXCM; -#else /* __XTENSA_CALL0_ABI__ */ - /* + for windowed ABI also set WOE and CALLINC (pretend task was 'call4'd). */ -#if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER - frame->a6 = (UBaseType_t) pxCode; - frame->a7 = (UBaseType_t) pvParameters; -#else - frame->a6 = (UBaseType_t) pvParameters; -#endif - frame->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1); -#endif /* __XTENSA_CALL0_ABI__ */ - -#ifdef XT_USE_SWPRI - /* Set the initial virtual priority mask value to all 1's. */ - frame->vpri = 0xFFFFFFFF; -#endif - - /* Init threadptr register and set up TLS run-time area. - * The diagram in port/riscv/port.c illustrates the calculations below. - */ - task_thread_local_start = (void *)(((uint32_t)pxTopOfStack - XT_CP_SIZE - thread_local_sz) & ~0xf); - memcpy(task_thread_local_start, &_thread_local_start, thread_local_sz); - threadptr = (uint32_t *)(sp + XT_STK_EXTRA); - /* Calculate THREADPTR value. - * The generated code will add THREADPTR value to a constant value determined at link time, - * to get the address of the TLS variable. - * The constant value is calculated by the linker as follows - * (search for 'tpoff' in elf32-xtensa.c in BFD): - * offset = address - tls_section_vma + align_up(TCB_SIZE, tls_section_alignment) - * where TCB_SIZE is hardcoded to 8. - * Note this is slightly different compared to the RISC-V port, where offset = address - tls_section_vma. - */ - const uint32_t tls_section_alignment = (uint32_t) &_flash_rodata_align; /* ALIGN value of .flash.rodata section */ - const uint32_t tcb_size = 8; /* Unrelated to FreeRTOS, this is the constant from BFD */ - const uint32_t base = (tcb_size + tls_section_alignment - 1) & (~(tls_section_alignment - 1)); - *threadptr = (uint32_t)task_thread_local_start - ((uint32_t)&_thread_local_start - (uint32_t)&_flash_rodata_start) - base; + UBaseType_t uxStackPointer = (UBaseType_t)pxTopOfStack; #if XCHAL_CP_NUM > 0 - /* Init the coprocessor save area (see xtensa_context.h) */ - /* No access to TCB here, so derive indirectly. Stack growth is top to bottom. - * //p = (uint32_t *) xMPUSettings->coproc_area; - */ - p = (uint32_t *)(((uint32_t) pxTopOfStack - XT_CP_SIZE) & ~0xf); - configASSERT( ( uint32_t ) p >= frame->a1 ); - p[0] = 0; - p[1] = 0; - p[2] = (((uint32_t) p) + 12 + XCHAL_TOTAL_SA_ALIGN - 1) & -XCHAL_TOTAL_SA_ALIGN; -#endif /* XCHAL_CP_NUM */ + // Initialize the coprocessor save area + uxStackPointer = uxInitialiseStackCPSA(uxStackPointer); +#endif /* XCHAL_CP_NUM > 0 */ - return sp; + // Initialize the GCC TLS area + uint32_t threadptr_reg_init; + uxStackPointer = uxInitialiseStackTLS(uxStackPointer, &threadptr_reg_init); + + // Initialize the starting interrupt stack frame + uxStackPointer = uxInitialiseStackFrame(uxStackPointer, pxCode, pvParameters, threadptr_reg_init); + // Return the task's current stack pointer address which should point to the starting interrupt stack frame + return (StackType_t *)uxStackPointer; } diff --git a/components/freertos/FreeRTOS-Kernel/queue.c b/components/freertos/FreeRTOS-Kernel/queue.c index bd40e8057b..6c473aa822 100644 --- a/components/freertos/FreeRTOS-Kernel/queue.c +++ b/components/freertos/FreeRTOS-Kernel/queue.c @@ -47,18 +47,6 @@ #include "croutine.h" #endif -#ifdef ESP_PLATFORM -#define taskCRITICAL_MUX &((Queue_t *)pxQueue)->mux -#undef taskENTER_CRITICAL -#undef taskEXIT_CRITICAL -#undef taskENTER_CRITICAL_ISR -#undef taskEXIT_CRITICAL_ISR -#define taskENTER_CRITICAL( ) portENTER_CRITICAL( taskCRITICAL_MUX ) -#define taskEXIT_CRITICAL( ) portEXIT_CRITICAL( taskCRITICAL_MUX ) -#define taskENTER_CRITICAL_ISR( ) portENTER_CRITICAL_ISR( taskCRITICAL_MUX ) -#define taskEXIT_CRITICAL_ISR( ) portEXIT_CRITICAL_ISR( taskCRITICAL_MUX ) -#endif - /* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined * for the header files above, but not in this file, in order to generate the @@ -148,7 +136,7 @@ typedef struct QueueDefinition /* The old naming convention is used to prevent b uint8_t ucQueueType; #endif #ifdef ESP_PLATFORM - portMUX_TYPE mux; //Mutex required due to SMP + portMUX_TYPE xQueueLock; /* Spinlock required for SMP critical sections */ #endif // ESP_PLATFORM } xQUEUE; @@ -183,8 +171,8 @@ typedef xQUEUE Queue_t; * array position being vacant. */ PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ]; #ifdef ESP_PLATFORM - //Need to add queue registry mutex to protect against simultaneous access - static portMUX_TYPE queue_registry_spinlock = portMUX_INITIALIZER_UNLOCKED; + /* Spinlock required in SMP when accessing the queue registry */ + static portMUX_TYPE xQueueRegistryLock = portMUX_INITIALIZER_UNLOCKED; #endif // ESP_PLATFORM #endif /* configQUEUE_REGISTRY_SIZE */ @@ -232,7 +220,7 @@ static void prvCopyDataFromQueue( Queue_t * const pxQueue, * Checks to see if a queue is a member of a queue set, and if so, notifies * the queue set that the queue contains data. */ - static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION; + static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION; #endif /* @@ -272,7 +260,7 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, * accessing the queue event lists. */ #define prvLockQueue( pxQueue ) \ - taskENTER_CRITICAL(); \ + taskENTER_CRITICAL( &( pxQueue->xQueueLock ) ); \ { \ if( ( pxQueue )->cRxLock == queueUNLOCKED ) \ { \ @@ -283,7 +271,7 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, ( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED; \ } \ } \ - taskEXIT_CRITICAL() + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ) /*-----------------------------------------------------------*/ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, @@ -296,11 +284,11 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, #ifdef ESP_PLATFORM if( xNewQueue == pdTRUE ) { - portMUX_INITIALIZE(&pxQueue->mux); + portMUX_INITIALIZE( &( pxQueue->xQueueLock ) ); } #endif // ESP_PLATFORM - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxQueue->xQueueLock ) ); { pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; @@ -339,7 +327,7 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); /* A value is returned for calling semantic consistency with previous * versions. */ @@ -374,10 +362,8 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, * variable of type StaticQueue_t or StaticSemaphore_t equals the size of * the real queue and semaphore structures. */ volatile size_t xSize = sizeof( StaticQueue_t ); - - /* This assertion cannot be branch covered in unit tests */ - configASSERT( xSize == sizeof( Queue_t ) ); /* LCOV_EXCL_BR_LINE */ - ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ + configASSERT( xSize == sizeof( Queue_t ) ); + ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ } #endif /* configASSERT_DEFINED */ @@ -417,30 +403,22 @@ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) { - Queue_t * pxNewQueue = NULL; + Queue_t * pxNewQueue; size_t xQueueSizeInBytes; uint8_t * pucQueueStorage; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); - if( uxItemSize == ( UBaseType_t ) 0 ) - { - /* There is not going to be a queue storage area. */ - xQueueSizeInBytes = ( size_t ) 0; - } - else - { - /* Allocate enough space to hold the maximum number of items that - * can be in the queue at any time. It is valid for uxItemSize to be - * zero in the case the queue is used as a semaphore. */ - xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ - } + /* Allocate enough space to hold the maximum number of items that + * can be in the queue at any time. It is valid for uxItemSize to be + * zero in the case the queue is used as a semaphore. */ + xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ /* Check for multiplication overflow. */ configASSERT( ( uxItemSize == 0 ) || ( uxQueueLength == ( xQueueSizeInBytes / uxItemSize ) ) ); /* Check for addition overflow. */ - configASSERT( ( sizeof( Queue_t ) + xQueueSizeInBytes ) > xQueueSizeInBytes ); + configASSERT( ( sizeof( Queue_t ) + xQueueSizeInBytes ) > xQueueSizeInBytes ); /* Allocate the queue and storage area. Justification for MISRA * deviation as follows: pvPortMalloc() always ensures returned memory @@ -545,7 +523,7 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, /* In case this is a recursive mutex. */ pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0; #ifdef ESP_PLATFORM - portMUX_INITIALIZE(&pxNewQueue->mux); + portMUX_INITIALIZE( &( pxNewQueue->xQueueLock ) ); #endif // ESP_PLATFORM traceCREATE_MUTEX( pxNewQueue ); @@ -610,10 +588,7 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, * calling task is the mutex holder, but not a good way of determining the * identity of the mutex holder, as the holder may change between the * following critical section exiting and the function returning. */ -#ifdef ESP_PLATFORM - Queue_t * const pxQueue = (Queue_t *)pxSemaphore; -#endif - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxSemaphore->xQueueLock ) ); { if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX ) { @@ -624,7 +599,7 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, pxReturn = NULL; } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxSemaphore->xQueueLock ) ); return pxReturn; } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */ @@ -762,7 +737,7 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxInitialCount, StaticQueue_t * pxStaticQueue ) { - QueueHandle_t xHandle = NULL; + QueueHandle_t xHandle; configASSERT( uxMaxCount != 0 ); configASSERT( uxInitialCount <= uxMaxCount ); @@ -791,7 +766,7 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) { - QueueHandle_t xHandle = NULL; + QueueHandle_t xHandle; configASSERT( uxMaxCount != 0 ); configASSERT( uxInitialCount <= uxMaxCount ); @@ -844,7 +819,7 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, * interest of execution time efficiency. */ for( ; ; ) { - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxQueue->xQueueLock ) ); { /* Is there room on the queue now? The running task must be the * highest priority task wanting to access the queue. If the head item @@ -856,7 +831,7 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, #if ( configUSE_QUEUE_SETS == 1 ) { - UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; + const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); @@ -869,7 +844,7 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, * in the queue has not changed. */ mtCOVERAGE_TEST_MARKER(); } - else if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE ) + else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) { /* The queue is a member of a queue set, and posting * to the queue set caused a higher priority task to @@ -950,7 +925,7 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, } #endif /* configUSE_QUEUE_SETS */ - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); return pdPASS; } else @@ -959,7 +934,7 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, { /* The queue was full and no block time is specified (or * the block time has expired) so leave now. */ - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); /* Return to the original privilege level before exiting * the function. */ @@ -980,13 +955,13 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, } } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); /* Interrupts and other tasks can send to and receive from the queue * now the critical section has been exited. */ #ifdef ESP_PLATFORM // IDF-3755 - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxQueue->xQueueLock ) ); #else vTaskSuspendAll(); #endif // ESP_PLATFORM @@ -1013,7 +988,7 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, * case the yield will not cause a context switch unless there * is also a higher priority task in the pending ready list. */ #ifdef ESP_PLATFORM // IDF-3755 - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); #else if( xTaskResumeAll() == pdFALSE ) #endif // ESP_PLATFORM @@ -1027,7 +1002,7 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, /* Try again. */ prvUnlockQueue( pxQueue ); #ifdef ESP_PLATFORM // IDF-3755 - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); #else ( void ) xTaskResumeAll(); #endif // ESP_PLATFORM @@ -1038,7 +1013,7 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, /* The timeout has expired. */ prvUnlockQueue( pxQueue ); #ifdef ESP_PLATFORM // IDF-3755 - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); #else ( void ) xTaskResumeAll(); #endif // ESP_PLATFORM @@ -1086,11 +1061,12 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, * post). */ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); { - taskENTER_CRITICAL_ISR(); + taskENTER_CRITICAL_ISR( &( pxQueue->xQueueLock ) ); if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) { const int8_t cTxLock = pxQueue->cTxLock; + const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; traceQUEUE_SEND_FROM_ISR( pxQueue ); @@ -1109,7 +1085,14 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, { if( pxQueue->pxQueueSetContainer != NULL ) { - if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE ) + if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) ) + { + /* Do not notify the queue set as an existing item + * was overwritten in the queue so the number of items + * in the queue has not changed. */ + mtCOVERAGE_TEST_MARKER(); + } + else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) { /* The queue is a member of a queue set, and posting * to the queue set caused a higher priority task to @@ -1182,6 +1165,9 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, { mtCOVERAGE_TEST_MARKER(); } + + /* Not used in this path. */ + ( void ) uxPreviousMessagesWaiting; } #endif /* configUSE_QUEUE_SETS */ } @@ -1200,7 +1186,7 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, xReturn = errQUEUE_FULL; } - taskEXIT_CRITICAL_ISR(); + taskEXIT_CRITICAL_ISR( &( pxQueue->xQueueLock ) ); } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); @@ -1250,7 +1236,7 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); { - taskENTER_CRITICAL_ISR(); + taskENTER_CRITICAL_ISR( &( pxQueue->xQueueLock ) ); const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; @@ -1279,7 +1265,7 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, { if( pxQueue->pxQueueSetContainer != NULL ) { - if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) != pdFALSE ) + if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) { /* The semaphore is a member of a queue set, and * posting to the queue set caused a higher priority @@ -1359,6 +1345,8 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, { /* Increment the lock count so the task that unlocks the queue * knows that data was posted while it was locked. */ + configASSERT( cTxLock != queueINT8_MAX ); + pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); } @@ -1369,7 +1357,7 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, traceQUEUE_GIVE_FROM_ISR_FAILED( pxQueue ); xReturn = errQUEUE_FULL; } - taskEXIT_CRITICAL_ISR(); + taskEXIT_CRITICAL_ISR( &( pxQueue->xQueueLock ) ); } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); @@ -1404,7 +1392,7 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue, * interest of execution time efficiency. */ for( ; ; ) { - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxQueue->xQueueLock ) ); { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; @@ -1436,7 +1424,7 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue, mtCOVERAGE_TEST_MARKER(); } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); return pdPASS; } else @@ -1445,7 +1433,7 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue, { /* The queue was empty and no block time is specified (or * the block time has expired) so leave now. */ - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; } @@ -1463,13 +1451,13 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue, } } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); /* Interrupts and other tasks can send to and receive from the queue * now the critical section has been exited. */ #ifdef ESP_PLATFORM // IDF-3755 - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxQueue->xQueueLock ) ); #else vTaskSuspendAll(); #endif // ESP_PLATFORM @@ -1486,7 +1474,7 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue, vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); prvUnlockQueue( pxQueue ); #ifdef ESP_PLATFORM // IDF-3755 - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); #else if( xTaskResumeAll() == pdFALSE ) #endif // ESP_PLATFORM @@ -1506,7 +1494,7 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue, * data. */ prvUnlockQueue( pxQueue ); #ifdef ESP_PLATFORM // IDF-3755 - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); #else ( void ) xTaskResumeAll(); #endif // ESP_PLATFORM @@ -1518,7 +1506,7 @@ BaseType_t xQueueReceive( QueueHandle_t xQueue, * back and attempt to read the data. */ prvUnlockQueue( pxQueue ); #ifdef ESP_PLATFORM // IDF-3755 - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); #else ( void ) xTaskResumeAll(); #endif // ESP_PLATFORM @@ -1567,7 +1555,7 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, * of execution time efficiency. */ for( ; ; ) { - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxQueue->xQueueLock ) ); { /* Semaphores are queues with an item size of 0, and where the * number of messages in the queue is the semaphore's count value. */ @@ -1616,7 +1604,7 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, mtCOVERAGE_TEST_MARKER(); } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); return pdPASS; } else @@ -1634,7 +1622,7 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, /* The semaphore count was 0 and no block time is specified * (or the block time has expired) so exit now. */ - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; } @@ -1652,13 +1640,13 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, } } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); /* Interrupts and other tasks can give to and take from the semaphore * now the critical section has been exited. */ #ifdef ESP_PLATFORM // IDF-3755 - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxQueue->xQueueLock ) ); #else vTaskSuspendAll(); #endif // ESP_PLATFORM @@ -1679,11 +1667,11 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) { - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxQueue->xQueueLock ) ); { xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder ); } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); } else { @@ -1695,7 +1683,7 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); prvUnlockQueue( pxQueue ); #ifdef ESP_PLATFORM // IDF-3755 - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); #else if( xTaskResumeAll() == pdFALSE ) #endif // ESP_PLATFORM @@ -1715,7 +1703,7 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, * attempt to take the semaphore again. */ prvUnlockQueue( pxQueue ); #ifdef ESP_PLATFORM // IDF-3755 - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); #else ( void ) xTaskResumeAll(); #endif // ESP_PLATFORM @@ -1726,7 +1714,7 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, /* Timed out. */ prvUnlockQueue( pxQueue ); #ifdef ESP_PLATFORM // IDF-3755 - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); #else ( void ) xTaskResumeAll(); #endif // ESP_PLATFORM @@ -1744,7 +1732,7 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, * test the mutex type again to check it is actually a mutex. */ if( xInheritanceOccurred != pdFALSE ) { - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxQueue->xQueueLock ) ); { UBaseType_t uxHighestWaitingPriority; @@ -1756,7 +1744,7 @@ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue ); vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority ); } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); } } #endif /* configUSE_MUTEXES */ @@ -1801,7 +1789,7 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue, * interest of execution time efficiency. */ for( ; ; ) { - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxQueue->xQueueLock ) ); { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; @@ -1839,7 +1827,7 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue, mtCOVERAGE_TEST_MARKER(); } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); return pdPASS; } else @@ -1848,7 +1836,7 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue, { /* The queue was empty and no block time is specified (or * the block time has expired) so leave now. */ - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); traceQUEUE_PEEK_FAILED( pxQueue ); return errQUEUE_EMPTY; } @@ -1867,13 +1855,13 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue, } } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); /* Interrupts and other tasks can send to and receive from the queue * now the critical section has been exited. */ #ifdef ESP_PLATFORM // IDF-3755 - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxQueue->xQueueLock ) ); #else vTaskSuspendAll(); #endif // ESP_PLATFORM @@ -1890,7 +1878,7 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue, vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); prvUnlockQueue( pxQueue ); #ifdef ESP_PLATFORM // IDF-3755 - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); #else if( xTaskResumeAll() == pdFALSE ) #endif // ESP_PLATFORM @@ -1910,7 +1898,7 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue, * state, instead return to try and obtain the data. */ prvUnlockQueue( pxQueue ); #ifdef ESP_PLATFORM // IDF-3755 - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); #else ( void ) xTaskResumeAll(); #endif // ESP_PLATFORM @@ -1922,7 +1910,7 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue, * exit, otherwise go back and try to read the data again. */ prvUnlockQueue( pxQueue ); #ifdef ESP_PLATFORM // IDF-3755 - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); #else ( void ) xTaskResumeAll(); #endif // ESP_PLATFORM @@ -1970,7 +1958,7 @@ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); { - taskENTER_CRITICAL_ISR(); + taskENTER_CRITICAL_ISR( &( pxQueue->xQueueLock ) ); const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; @@ -2019,6 +2007,8 @@ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, { /* Increment the lock count so the task that unlocks the queue * knows that data was removed while it was locked. */ + configASSERT( cRxLock != queueINT8_MAX ); + pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 ); } @@ -2029,7 +2019,7 @@ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, xReturn = pdFAIL; traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ); } - taskEXIT_CRITICAL_ISR(); + taskEXIT_CRITICAL_ISR( &( pxQueue->xQueueLock ) ); } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); @@ -2066,7 +2056,7 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); - taskENTER_CRITICAL_ISR(); + taskENTER_CRITICAL_ISR( &( pxQueue->xQueueLock ) ); { /* Cannot block in an ISR, so check there is data available. */ if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 ) @@ -2087,7 +2077,7 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ); } } - taskEXIT_CRITICAL_ISR(); + taskEXIT_CRITICAL_ISR( &( pxQueue->xQueueLock ) ); portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; @@ -2097,15 +2087,14 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) { UBaseType_t uxReturn; - Queue_t * const pxQueue = ( Queue_t * ) xQueue; configASSERT( xQueue ); - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( ( ( Queue_t * ) xQueue )->xQueueLock ) ); { uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting; } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( ( ( Queue_t * ) xQueue )->xQueueLock ) ); return uxReturn; } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ @@ -2118,11 +2107,11 @@ UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) configASSERT( pxQueue ); - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxQueue->xQueueLock ) ); { uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting; } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); return uxReturn; } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ @@ -2352,7 +2341,7 @@ static void prvUnlockQueue( Queue_t * const pxQueue ) * removed from the queue while the queue was locked. When a queue is * locked items can be added or removed, but the event lists cannot be * updated. */ - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxQueue->xQueueLock ) ); { int8_t cTxLock = pxQueue->cTxLock; @@ -2365,7 +2354,7 @@ static void prvUnlockQueue( Queue_t * const pxQueue ) { if( pxQueue->pxQueueSetContainer != NULL ) { - if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) != pdFALSE ) + if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) { /* The queue is a member of a queue set, and posting to * the queue set caused a higher priority task to unblock. @@ -2430,10 +2419,10 @@ static void prvUnlockQueue( Queue_t * const pxQueue ) pxQueue->cTxLock = queueUNLOCKED; } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); /* Do the same for the Rx lock. */ - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxQueue->xQueueLock ) ); { int8_t cRxLock = pxQueue->cRxLock; @@ -2460,14 +2449,14 @@ static void prvUnlockQueue( Queue_t * const pxQueue ) pxQueue->cRxLock = queueUNLOCKED; } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); } /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue ) { BaseType_t xReturn; - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( ( ( Queue_t * ) pxQueue )->xQueueLock ) ); { if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) { @@ -2478,7 +2467,7 @@ static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue ) xReturn = pdFALSE; } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( ( ( Queue_t * ) pxQueue )->xQueueLock ) ); return xReturn; } @@ -2508,6 +2497,9 @@ static BaseType_t prvIsQueueFull( const Queue_t * pxQueue ) { BaseType_t xReturn; +#ifndef ESP_PLATFORM + taskENTER_CRITICAL( &( pxQueue->xQueueLock ) ); +#endif { if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) { @@ -2518,6 +2510,9 @@ static BaseType_t prvIsQueueFull( const Queue_t * pxQueue ) xReturn = pdFALSE; } } +#ifndef ESP_PLATFORM + taskEXIT_CRITICAL( &( pxQueue->xQueueLock ) ); +#endif return xReturn; } @@ -2837,7 +2832,7 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) { UBaseType_t ux; - portENTER_CRITICAL(&queue_registry_spinlock); + taskENTER_CRITICAL( &xQueueRegistryLock ); /* See if there is an empty space in the registry. A NULL name denotes * a free slot. */ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) @@ -2856,7 +2851,7 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) mtCOVERAGE_TEST_MARKER(); } } - portEXIT_CRITICAL(&queue_registry_spinlock); + taskEXIT_CRITICAL( &xQueueRegistryLock ); } #endif /* configQUEUE_REGISTRY_SIZE */ @@ -2869,7 +2864,7 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) UBaseType_t ux; const char * pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ - portENTER_CRITICAL(&queue_registry_spinlock); + taskENTER_CRITICAL( &xQueueRegistryLock ); /* Note there is nothing here to protect against another task adding or * removing entries from the registry while it is being searched. */ @@ -2886,7 +2881,7 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) mtCOVERAGE_TEST_MARKER(); } } - portEXIT_CRITICAL(&queue_registry_spinlock); + taskEXIT_CRITICAL( &xQueueRegistryLock ); return pcReturn; } /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */ @@ -2900,7 +2895,7 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) { UBaseType_t ux; - portENTER_CRITICAL(&queue_registry_spinlock); + taskENTER_CRITICAL( &xQueueRegistryLock ); /* See if the handle of the queue being unregistered in actually in the * registry. */ @@ -2922,7 +2917,7 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) mtCOVERAGE_TEST_MARKER(); } } - portEXIT_CRITICAL(&queue_registry_spinlock); + taskEXIT_CRITICAL( &xQueueRegistryLock ); } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ @@ -2989,11 +2984,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) QueueSetHandle_t xQueueSet ) { BaseType_t xReturn; -#ifdef ESP_PLATFORM - Queue_t * pxQueue = (Queue_t * )xQueueOrSemaphore; -#endif - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( ( ( Queue_t * ) xQueueOrSemaphore )->xQueueLock ) ); { if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL ) { @@ -3012,7 +3004,7 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) xReturn = pdPASS; } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( ( ( Queue_t * ) xQueueOrSemaphore )->xQueueLock ) ); return xReturn; } @@ -3042,15 +3034,12 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) } else { -#ifdef ESP_PLATFORM - Queue_t* pxQueue = (Queue_t*)pxQueueOrSemaphore; -#endif - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( ( ( Queue_t * ) pxQueueOrSemaphore )->xQueueLock ) ); { /* The queue is no longer contained in the set. */ pxQueueOrSemaphore->pxQueueSetContainer = NULL; } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( ( ( Queue_t * ) pxQueueOrSemaphore )->xQueueLock ) ); xReturn = pdPASS; } @@ -3089,21 +3078,17 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) #if ( configUSE_QUEUE_SETS == 1 ) - static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, - const BaseType_t xCopyPosition ) + static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) { Queue_t * pxQueueSetContainer = pxQueue->pxQueueSetContainer; BaseType_t xReturn = pdFALSE; /* This function must be called form a critical section. */ - /* The following line is not reachable in unit tests because every call - * to prvNotifyQueueSetContainer is preceded by a check that - * pxQueueSetContainer != NULL */ - configASSERT( pxQueueSetContainer ); /* LCOV_EXCL_BR_LINE */ + configASSERT( pxQueueSetContainer ); - //Acquire the Queue set's spinlock - portENTER_CRITICAL(&(pxQueueSetContainer->mux)); + /* Acquire the Queue set's spinlock */ + taskENTER_CRITICAL( &( pxQueueSetContainer->xQueueLock ) ); configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength ); @@ -3111,10 +3096,10 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) { const int8_t cTxLock = pxQueueSetContainer->cTxLock; - traceQUEUE_SEND( pxQueueSetContainer ); + traceQUEUE_SET_SEND( pxQueueSetContainer ); /* The data copied is the handle of the queue that contains data. */ - xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, xCopyPosition ); + xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, queueSEND_TO_BACK ); if( cTxLock == queueUNLOCKED ) { @@ -3137,6 +3122,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) } else { + configASSERT( cTxLock != queueINT8_MAX ); + pxQueueSetContainer->cTxLock = ( int8_t ) ( cTxLock + 1 ); } } @@ -3145,8 +3132,8 @@ BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) mtCOVERAGE_TEST_MARKER(); } - //Release the Queue set's spinlock - portEXIT_CRITICAL(&(pxQueueSetContainer->mux)); + /* Release the Queue set's spinlock */ + taskEXIT_CRITICAL( &( pxQueueSetContainer->xQueueLock ) ); return xReturn; } diff --git a/components/freertos/FreeRTOS-Kernel/stream_buffer.c b/components/freertos/FreeRTOS-Kernel/stream_buffer.c index 2cfb4aade6..38c4fef59c 100644 --- a/components/freertos/FreeRTOS-Kernel/stream_buffer.c +++ b/components/freertos/FreeRTOS-Kernel/stream_buffer.c @@ -45,18 +45,6 @@ #include "task.h" #include "stream_buffer.h" -#ifdef ESP_PLATFORM -#define taskCRITICAL_MUX &pxStreamBuffer->xStreamBufferMux -#undef taskENTER_CRITICAL -#undef taskEXIT_CRITICAL -#undef taskENTER_CRITICAL_ISR -#undef taskEXIT_CRITICAL_ISR -#define taskENTER_CRITICAL( ) portENTER_CRITICAL( taskCRITICAL_MUX ) -#define taskEXIT_CRITICAL( ) portEXIT_CRITICAL( taskCRITICAL_MUX ) -#define taskENTER_CRITICAL_ISR( ) portENTER_CRITICAL_ISR( taskCRITICAL_MUX ) -#define taskEXIT_CRITICAL_ISR( ) portEXIT_CRITICAL_ISR( taskCRITICAL_MUX ) -#endif - #if ( configUSE_TASK_NOTIFICATIONS != 1 ) #error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c #endif @@ -75,7 +63,7 @@ #ifndef sbRECEIVE_COMPLETED #ifdef ESP_PLATFORM // IDF-3775 #define sbRECEIVE_COMPLETED( pxStreamBuffer ) \ - taskENTER_CRITICAL(); \ + taskENTER_CRITICAL( &( pxStreamBuffer->xStreamBufferLock ) ); \ { \ if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) \ { \ @@ -85,7 +73,7 @@ ( pxStreamBuffer )->xTaskWaitingToSend = NULL; \ } \ } \ - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxStreamBuffer->xStreamBufferLock ) ); #else #define sbRECEIVE_COMPLETED( pxStreamBuffer ) \ vTaskSuspendAll(); \ @@ -129,7 +117,7 @@ #ifndef sbSEND_COMPLETED #ifdef ESP_PLATFORM // IDF-3755 #define sbSEND_COMPLETED( pxStreamBuffer ) \ - taskENTER_CRITICAL(); \ + taskENTER_CRITICAL( &( pxStreamBuffer->xStreamBufferLock ) ); \ { \ if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) \ { \ @@ -139,7 +127,7 @@ ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; \ } \ } \ - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxStreamBuffer->xStreamBufferLock ) ); #else #define sbSEND_COMPLETED( pxStreamBuffer ) \ vTaskSuspendAll(); \ @@ -202,8 +190,7 @@ typedef struct StreamBufferDef_t /*lint !e9058 Style convention UBaseType_t uxStreamBufferNumber; /* Used for tracing purposes. */ #endif #ifdef ESP_PLATFORM - /* Mutex required due to SMP. This field shall be the last one of the structure. */ - portMUX_TYPE xStreamBufferMux; + portMUX_TYPE xStreamBufferLock; /* Spinlock required for SMP critical sections */ #endif // ESP_PLATFORM } StreamBuffer_t; @@ -485,7 +472,7 @@ BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) #endif /* Can only reset a message buffer if there are no tasks blocked on it. */ - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxStreamBuffer->xStreamBufferLock ) ); { if( pxStreamBuffer->xTaskWaitingToReceive == NULL ) { @@ -520,7 +507,7 @@ BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) } } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxStreamBuffer->xStreamBufferLock ) ); return xReturn; } @@ -601,14 +588,13 @@ size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, size_t xReturn, xSpace = 0; size_t xRequiredSpace = xDataLengthBytes; TimeOut_t xTimeOut; - size_t xMaxReportedSpace = 0; - - configASSERT( pvTxData ); - configASSERT( pxStreamBuffer ); /* The maximum amount of space a stream buffer will ever report is its length * minus 1. */ - xMaxReportedSpace = pxStreamBuffer->xLength - ( size_t ) 1; + const size_t xMaxReportedSpace = pxStreamBuffer->xLength - ( size_t ) 1; + + configASSERT( pvTxData ); + configASSERT( pxStreamBuffer ); /* This send function is used to write to both message buffers and stream * buffers. If this is a message buffer then the space needed must be @@ -657,7 +643,7 @@ size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, { /* Wait until the required number of bytes are free in the message * buffer. */ - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxStreamBuffer->xStreamBufferLock ) ); { xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); @@ -672,11 +658,11 @@ size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, } else { - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxStreamBuffer->xStreamBufferLock ) ); break; } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxStreamBuffer->xStreamBufferLock ) ); traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ); ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); @@ -855,7 +841,7 @@ size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, { /* Checking if there is data and clearing the notification state must be * performed atomically. */ - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &( pxStreamBuffer->xStreamBufferLock ) ); { xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); @@ -878,7 +864,7 @@ size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, mtCOVERAGE_TEST_MARKER(); } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &( pxStreamBuffer->xStreamBufferLock ) ); if( xBytesAvailable <= xBytesToStoreMessageLength ) { @@ -1358,7 +1344,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes; pxStreamBuffer->ucFlags = ucFlags; #ifdef ESP_PLATFORM - portMUX_INITIALIZE( &pxStreamBuffer->xStreamBufferMux ); + portMUX_INITIALIZE( &( pxStreamBuffer->xStreamBufferLock ) ); #endif // ESP_PLATFORM } @@ -1386,8 +1372,8 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, /* Do not include the spinlock in the part to reset! * Thus, make sure the spinlock is the last field of the structure. */ - _Static_assert( offsetof(StreamBuffer_t, xStreamBufferMux) == sizeof( StreamBuffer_t ) - sizeof(portMUX_TYPE), - "xStreamBufferMux must be the last field of structure StreamBuffer_t" ); + _Static_assert( offsetof(StreamBuffer_t, xStreamBufferLock) == sizeof( StreamBuffer_t ) - sizeof(portMUX_TYPE), + "xStreamBufferLock must be the last field of structure StreamBuffer_t" ); const size_t erasable = sizeof( StreamBuffer_t ) - sizeof(portMUX_TYPE); ( void ) memset( ( void * ) pxStreamBuffer, 0x00, erasable ); /*lint !e9087 memset() requires void *. */ pxStreamBuffer->pucBuffer = pucBuffer; diff --git a/components/freertos/FreeRTOS-Kernel/tasks.c b/components/freertos/FreeRTOS-Kernel/tasks.c index 6b2252071e..f705d7634a 100644 --- a/components/freertos/FreeRTOS-Kernel/tasks.c +++ b/components/freertos/FreeRTOS-Kernel/tasks.c @@ -47,15 +47,6 @@ #include "stack_macros.h" #ifdef ESP_PLATFORM -#define taskCRITICAL_MUX &xTaskQueueMutex -#undef taskENTER_CRITICAL -#undef taskEXIT_CRITICAL -#undef taskENTER_CRITICAL_ISR -#undef taskEXIT_CRITICAL_ISR -#define taskENTER_CRITICAL( ) portENTER_CRITICAL( taskCRITICAL_MUX ) -#define taskEXIT_CRITICAL( ) portEXIT_CRITICAL( taskCRITICAL_MUX ) -#define taskENTER_CRITICAL_ISR( ) portENTER_CRITICAL_ISR( taskCRITICAL_MUX ) -#define taskEXIT_CRITICAL_ISR( ) portEXIT_CRITICAL_ISR( taskCRITICAL_MUX ) #undef _REENT_INIT_PTR #define _REENT_INIT_PTR esp_reent_init extern void esp_vApplicationIdleHook(void); @@ -249,7 +240,33 @@ extern void esp_vApplicationIdleHook(void); tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB ) /*-----------------------------------------------------------*/ -#define tskCAN_RUN_HERE( cpuid ) ( cpuid==xPortGetCoreID() || cpuid==tskNO_AFFINITY ) +#if ( configNUM_CORES > 1 ) + #define prvCheckForYield( pxTCB, xCurCoreID, xYieldEqualPriority ) ( prvCheckForYieldUsingPrioritySMP( ( pxTCB )->uxPriority, ( pxTCB )->xCoreID, xCurCoreID, xYieldEqualPriority ) == pdTRUE ) + #define prvCheckForYieldUsingPriority( uxTaskPriority, xTaskCoreID, xCurCoreID, xYieldEqualPriority ) ( prvCheckForYieldUsingPrioritySMP( uxTaskPriority, xTaskCoreID, xCurCoreID, xYieldEqualPriority ) == pdTRUE ) +#else + #define prvCheckForYield( pxTargetTCB, xCurCoreID, xYieldEqualPriority ) ( ( ( pxTargetTCB )->uxPriority + ( ( xYieldEqualPriority == pdTRUE ) ? 1 : 0 ) ) > pxCurrentTCB[ 0 ]->uxPriority ) + #define prvCheckForYieldUsingPriority( uxTaskPriority, xTaskCoreID, xCurCoreID, xYieldEqualPriority ) ( ( uxTaskPriority + ( ( xYieldEqualPriority == pdTRUE ) ? 1 : 0 ) ) >= pxCurrentTCB[ 0 ]->uxPriority ) +#endif /* configNUM_CORES > 1 */ +/*-----------------------------------------------------------*/ + +/* + * Check if a particular task (using its xCoreID) can run on a designated core. + * On single core, this macro always evaluates to true. + */ +#if ( configNUM_CORES > 1 ) + #define taskCAN_RUN_ON_CORE( xCore, xCoreID ) ( ( ( ( xCoreID ) == xCore ) || ( ( xCoreID ) == tskNO_AFFINITY ) ) ? pdTRUE : pdFALSE ) +#else + #define taskCAN_RUN_ON_CORE( xCore, xCoreID ) ( pdTRUE ) +#endif /* configNUM_CORES > 1 */ + +/* Check if a task is a currently running task. */ +#if ( configNUM_CORES > 1 ) + #define taskIS_CURRENTLY_RUNNING( pxTCB ) ( ( ( pxTCB ) == pxCurrentTCB[ 0 ] ) || ( ( pxTCB ) == pxCurrentTCB[ 1 ] ) ) + #define taskIS_CURRENTLY_RUNNING_ON_CORE( pxTCB, xCoreID ) ( ( pxTCB ) == pxCurrentTCB[ ( xCoreID ) ] ) +#else + #define taskIS_CURRENTLY_RUNNING( pxTCB ) ( ( pxTCB ) == pxCurrentTCB[ 0 ] ) + #define taskIS_CURRENTLY_RUNNING_ON_CORE( pxTCB, xCoreID ) taskIS_CURRENTLY_RUNNING( ( pxTCB ) ) +#endif /* configNUM_CORES > 1 */ /* * Several functions take a TaskHandle_t parameter that can optionally be NULL, @@ -386,7 +403,9 @@ PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList; /*< Poi PRIVILEGED_DATA static List_t xPendingReadyList[ configNUM_CORES ]; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready list when the scheduler is resumed. */ #ifdef ESP_PLATFORM -PRIVILEGED_DATA static portMUX_TYPE xTaskQueueMutex = portMUX_INITIALIZER_UNLOCKED; +/* Spinlock required for SMP critical sections. This lock protects all of the + * kernel's data structures such as various tasks lists, flags, and tick counts. */ +PRIVILEGED_DATA static portMUX_TYPE xKernelLock = portMUX_INITIALIZER_UNLOCKED; #endif // ESP_PLATFORM #if ( INCLUDE_vTaskDelete == 1 ) @@ -530,8 +549,8 @@ static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION; * The currently executing task is entering the Blocked state. Add the task to * either the current or the overflow delayed task list. */ -static void prvAddCurrentTaskToDelayedList( const portBASE_TYPE xCoreID, - const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, + const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION; /* * Fills an TaskStatus_t structure with information on each task that is @@ -621,9 +640,49 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, * Called after a new task has been created and initialised to place the task * under the control of the scheduler. */ -static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, - TaskFunction_t pxTaskCode, - BaseType_t xCoreID ) PRIVILEGED_FUNCTION; +static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION; + +#if ( configNUM_CORES > 1 ) + +/* + * Check whether a yield (on either core) is required after unblocking (or + * changing the priority of) a particular task. + * + * - This function is the SMP replacement for checking if an unblocked task has + * a higher (or equal) priority than the current task. + * - It should be called before calling taskYIELD_IF_USING_PREEMPTION() or + * before setting xYieldRequired + * - If it is the other core that requires a yield, this function will + * internally trigger the other core to yield + * + * Note: In some special instances, a yield is triggered if the unblocked task + * has an equal priority (such as in xTaskResumeAll). Thus the + * xYieldEqualPriority parameter specifies whether to yield if the current + * task has equal priority. + * + * Scheduling Algorithm: + * This function will bias towards yielding the current core. + * - If the unblocked task has a higher (or equal) priority than then current + * core, the current core is yielded regardless of the current priority of the + * other core. + * - A core (current or other) will only yield if their schedulers are not + * suspended. + * + * Todo: This can be optimized (IDF-5772) + * + * Entry: + * - This function must be called in a critical section + * - A task must just have been unblocked, or its priority raised + * Exit: + * - Returns pdTRUE if the current core requires yielding + * - The other core will be triggered to yield if required + */ +static BaseType_t prvCheckForYieldUsingPrioritySMP( UBaseType_t uxTaskPriority, + BaseType_t xTaskCoreID, + BaseType_t xCurCoreID, + BaseType_t xYieldEqualPriority ) PRIVILEGED_FUNCTION; + +#endif /* configNUM_CORES > 1 */ /* * freertos_tasks_c_additions_init() should only be called if the user definable @@ -636,54 +695,25 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, #endif -/* - * This routine tries to send an interrupt to another core if needed to make it execute a task - * of higher priority. We try to figure out if needed first by inspecting the pxTCB of the - * other CPU first. Specifically for Xtensa, we can do this because pxTCB is an atomic pointer. It - * is possible that it is inaccurate because the other CPU just did a task switch, but in that case - * at most a superfluous interrupt is generated. -*/ -void taskYIELD_OTHER_CORE( BaseType_t xCoreID, UBaseType_t uxPriority ) -{ - BaseType_t i; - - if (xCoreID != tskNO_AFFINITY) { - if ( pxCurrentTCB[ xCoreID ]->uxPriority < uxPriority ) { // NOLINT(clang-analyzer-core.NullDereference) IDF-685 - vPortYieldOtherCore( xCoreID ); - } - } - else - { - /* The task has no affinity. See if we can find a CPU to put it on.*/ - for (i=0; iuxPriority < uxPriority) - { - vPortYieldOtherCore( i ); - break; - } - } - } -} - /*-----------------------------------------------------------*/ #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) - TaskHandle_t xTaskCreateStaticPinnedToCore( TaskFunction_t pvTaskCode, + TaskHandle_t xTaskCreateStaticPinnedToCore( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, - StackType_t * const pxStackBuffer, + StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer, const BaseType_t xCoreID ) { TCB_t *pxNewTCB; TaskHandle_t xReturn; - configASSERT( portVALID_TCB_MEM(pxTaskBuffer) ); - configASSERT( portVALID_STACK_MEM(pxStackBuffer) ); - configASSERT( (xCoreID>=0 && xCoreID= 0 ) && ( xCoreID < configNUM_CORES ) ) || ( xCoreID == tskNO_AFFINITY ) ); #if ( configASSERT_DEFINED == 1 ) { @@ -696,13 +726,12 @@ void taskYIELD_OTHER_CORE( BaseType_t xCoreID, UBaseType_t uxPriority ) } #endif /* configASSERT_DEFINED */ - - if( ( pxTaskBuffer != NULL ) && ( pxStackBuffer != NULL ) ) + if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) { /* The memory used for the task's TCB and stack are passed into this * function - use them. */ pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ - pxNewTCB->pxStack = ( StackType_t * ) pxStackBuffer; + pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { @@ -712,8 +741,8 @@ void taskYIELD_OTHER_CORE( BaseType_t xCoreID, UBaseType_t uxPriority ) } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ - prvInitialiseNewTask( pvTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL, xCoreID ); - prvAddNewTaskToReadyList( pxNewTCB, pvTaskCode, xCoreID ); + prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL, xCoreID ); + prvAddNewTaskToReadyList( pxNewTCB ); } else { @@ -764,7 +793,7 @@ void taskYIELD_OTHER_CORE( BaseType_t xCoreID, UBaseType_t uxPriority ) pxTaskDefinition->xRegions, tskNO_AFFINITY ); - prvAddNewTaskToReadyList( pxNewTCB, pxTaskDefinition->pvTaskCode, tskNO_AFFINITY); + prvAddNewTaskToReadyList( pxNewTCB ); xReturn = pdPASS; } @@ -814,7 +843,7 @@ void taskYIELD_OTHER_CORE( BaseType_t xCoreID, UBaseType_t uxPriority ) pxTaskDefinition->xRegions, tskNO_AFFINITY ); - prvAddNewTaskToReadyList( pxNewTCB, pxTaskDefinition->pvTaskCode, tskNO_AFFINITY); + prvAddNewTaskToReadyList( pxNewTCB ); xReturn = pdPASS; } } @@ -827,13 +856,13 @@ void taskYIELD_OTHER_CORE( BaseType_t xCoreID, UBaseType_t uxPriority ) #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) - BaseType_t xTaskCreatePinnedToCore( TaskFunction_t pvTaskCode, - const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ - const uint32_t usStackDepth, - void * const pvParameters, - UBaseType_t uxPriority, - TaskHandle_t * const pvCreatedTask, - const BaseType_t xCoreID) + BaseType_t xTaskCreatePinnedToCore( TaskFunction_t pxTaskCode, + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const configSTACK_DEPTH_TYPE usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask, + const BaseType_t xCoreID) { TCB_t * pxNewTCB; BaseType_t xReturn; @@ -904,8 +933,8 @@ void taskYIELD_OTHER_CORE( BaseType_t xCoreID, UBaseType_t uxPriority ) } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ - prvInitialiseNewTask( pvTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pvCreatedTask, pxNewTCB, NULL, xCoreID ); - prvAddNewTaskToReadyList( pxNewTCB, pvTaskCode, xCoreID); + prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL, xCoreID ); + prvAddNewTaskToReadyList( pxNewTCB ); xReturn = pdPASS; } else @@ -932,8 +961,10 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, StackType_t * pxTopOfStack; UBaseType_t x; - #if (configNUM_CORES < 2) - xCoreID = 0; + #if ( configNUM_CORES == 1 ) + { + xCoreID = 0; + } #endif #if ( portUSING_MPU_WRAPPERS == 1 ) @@ -1188,76 +1219,42 @@ static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, } /*-----------------------------------------------------------*/ -static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, - TaskFunction_t pxTaskCode, - BaseType_t xCoreID ) +static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) { - TCB_t *curTCB, *tcb0, *tcb1; - - #if (configNUM_CORES < 2) - xCoreID = 0; - #endif - /* Ensure interrupts don't access the task lists while the lists are being * updated. */ - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); { uxCurrentNumberOfTasks++; - if ( xCoreID == tskNO_AFFINITY ) + if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) { - if ( configNUM_CORES == 1 ) - { - xCoreID = 0; - } - else - { - // if the task has no affinity, put it on either core if nothing is currently scheduled there. Failing that, - // put it on the core where it will preempt the lowest priority running task. If neither of these are true, - // queue it on the currently running core. - tcb0 = pxCurrentTCB[0]; - tcb1 = pxCurrentTCB[1]; - if ( tcb0 == NULL ) - { - xCoreID = 0; - } - else if ( tcb1 == NULL ) - { - xCoreID = 1; - } - else if ( tcb0->uxPriority < pxNewTCB->uxPriority && tcb0->uxPriority < tcb1->uxPriority ) - { - xCoreID = 0; - } - else if ( tcb1->uxPriority < pxNewTCB->uxPriority ) - { - xCoreID = 1; - } - else - { - xCoreID = xPortGetCoreID(); // Both CPU have higher priority tasks running on them, so this won't run yet - } - } + /* This is the first task to be created so do the preliminary + * initialisation required. We will not recover if this call + * fails, but we will report the failure. */ + prvInitialiseTaskLists(); + } + else + { + mtCOVERAGE_TEST_MARKER(); } - if( pxCurrentTCB[xCoreID] == NULL ) + if( ( pxCurrentTCB[ 0 ] == NULL ) && ( taskCAN_RUN_ON_CORE( 0, pxNewTCB->xCoreID ) == pdTRUE ) ) { - /* There are no other tasks, or all the other tasks are in - * the suspended state - make this the current task. */ - pxCurrentTCB[xCoreID] = pxNewTCB; - - if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) - { - /* This is the first task to be created so do the preliminary - * initialisation required. We will not recover if this call - * fails, but we will report the failure. */ - prvInitialiseTaskLists(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } + /* On core 0, there are no other tasks, or all the other tasks + * are in the suspended state - make this the current task. */ + pxCurrentTCB[ 0 ] = pxNewTCB; } + + #if ( configNUM_CORES > 1 ) + else if( ( pxCurrentTCB[ 1 ] == NULL ) && ( taskCAN_RUN_ON_CORE( 1, pxNewTCB->xCoreID ) == pdTRUE ) ) + { + /* On core 1, there are no other tasks, or all the other tasks + * are in the suspended state - make this the current task. */ + pxCurrentTCB[ 1 ] = pxNewTCB; + } + #endif /* configNUM_CORES > 1 */ + else { /* If the scheduler is not already running, make this task the @@ -1265,10 +1262,22 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, * so far. */ if( xSchedulerRunning == pdFALSE ) { - if( pxCurrentTCB[xCoreID] == NULL || pxCurrentTCB[xCoreID]->uxPriority <= pxNewTCB->uxPriority ) + if( ( pxCurrentTCB[ 0 ] != NULL ) + && ( taskCAN_RUN_ON_CORE( 0, pxNewTCB->xCoreID ) == pdTRUE ) + && ( pxCurrentTCB[ 0 ]->uxPriority <= pxNewTCB->uxPriority ) ) { - pxCurrentTCB[xCoreID] = pxNewTCB; + pxCurrentTCB[ 0 ] = pxNewTCB; } + + #if ( configNUM_CORES > 1 ) + else if( ( pxCurrentTCB[ 1 ] != NULL ) + && ( taskCAN_RUN_ON_CORE( 1, pxNewTCB->xCoreID ) == pdTRUE ) + && ( pxCurrentTCB[ 1 ]->uxPriority <= pxNewTCB->uxPriority ) ) + { + pxCurrentTCB[ 1 ] = pxNewTCB; + } + #endif /* configNUM_CORES > 1 */ + else { mtCOVERAGE_TEST_MARKER(); @@ -1293,52 +1302,88 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, prvAddTaskToReadyList( pxNewTCB ); portSETUP_TCB( pxNewTCB ); - } - taskEXIT_CRITICAL(); - if( xSchedulerRunning != pdFALSE ) - { - /* If the created task is of a higher priority than the current task - * then it should run now. */ - taskENTER_CRITICAL(); - - curTCB = pxCurrentTCB[ xCoreID ]; - if( curTCB == NULL || curTCB->uxPriority < pxNewTCB->uxPriority ) + if( xSchedulerRunning != pdFALSE ) { - if( xCoreID == xPortGetCoreID() ) + /* If the created task is of a higher priority than the current task + * then it should run now. */ + if( prvCheckForYield( pxNewTCB, xPortGetCoreID(), pdTRUE ) ) { taskYIELD_IF_USING_PREEMPTION(); } - else { - taskYIELD_OTHER_CORE(xCoreID, pxNewTCB->uxPriority); + else + { + mtCOVERAGE_TEST_MARKER(); } } else { mtCOVERAGE_TEST_MARKER(); } - taskEXIT_CRITICAL(); - } - else - { - mtCOVERAGE_TEST_MARKER(); + } + taskEXIT_CRITICAL( &xKernelLock ); } /*-----------------------------------------------------------*/ +#if ( configNUM_CORES > 1 ) + + static BaseType_t prvCheckForYieldUsingPrioritySMP( UBaseType_t uxTaskPriority, + BaseType_t xTaskCoreID, + BaseType_t xCurCoreID, + BaseType_t xYieldEqualPriority ) + { + if( xYieldEqualPriority == pdTRUE ) + { + /* Increment the task priority to achieve the same affect as if( uxTaskPriority >= pxCurrentTCB->uxPriority ) */ + uxTaskPriority++; + } + + /* Indicate whether the current core needs to yield */ + BaseType_t xYieldRequiredCurrentCore; + + /* If the target task can run on the current core, and has a higher priority than the current core, then yield the current core */ + if( ( ( xTaskCoreID == xCurCoreID ) || ( xTaskCoreID == tskNO_AFFINITY ) ) && ( uxTaskPriority > pxCurrentTCB[ xCurCoreID ]->uxPriority ) ) + { + /* Return true for the caller to yield the current core */ + xYieldRequiredCurrentCore = pdTRUE; + } + /* If the target task can run on the other core, and has a higher priority then the other core, and the other core has not suspended scheduling, the yield the other core */ + else if( ( ( xTaskCoreID == !xCurCoreID ) || ( xTaskCoreID == tskNO_AFFINITY ) ) + && ( uxTaskPriority > pxCurrentTCB[ !xCurCoreID ]->uxPriority ) + && ( uxSchedulerSuspended[ !xCurCoreID ] == ( UBaseType_t ) pdFALSE ) ) + { + /* Signal the other core to yield */ + vPortYieldOtherCore( !xCurCoreID ); + xYieldRequiredCurrentCore = pdFALSE; + } + else + { + xYieldRequiredCurrentCore = pdFALSE; + } + + return xYieldRequiredCurrentCore; + } + +#endif /* configNUM_CORES > 1 */ +/*-----------------------------------------------------------*/ + #if ( INCLUDE_vTaskDelete == 1 ) void vTaskDelete( TaskHandle_t xTaskToDelete ) { TCB_t * pxTCB; - TCB_t * curTCB; - BaseType_t core; - BaseType_t xFreeNow = 0; + BaseType_t xFreeNow; - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); { - core = xPortGetCoreID(); - curTCB = pxCurrentTCB[core]; + BaseType_t xCurCoreID; + #if ( configNUM_CORES > 1 ) + xCurCoreID = xPortGetCoreID(); + #else + xCurCoreID = 0; + ( void ) xCurCoreID; + #endif /* If null is passed in here then it is the calling task that is * being deleted. */ @@ -1370,12 +1415,19 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, * not return. */ uxTaskNumber++; - if( pxTCB == curTCB || - /* in SMP, we also can't immediately delete the task active on the other core */ - (configNUM_CORES > 1 && pxTCB == pxCurrentTCB[ !core ]) || - /* ... and we can't delete a non-running task pinned to the other core, as - FPU cleanup has to happen on the same core */ - (configNUM_CORES > 1 && pxTCB->xCoreID == (!core)) ) + /* + * We cannot immediately a task that is + * - Currently running on either core + * - If the task is not currently running but is pinned to the other (due to FPU cleanup) + * Todo: Allow deletion of tasks pinned to other core (IDF-5803) + */ + #if ( configNUM_CORES > 1 ) + xFreeNow = ( taskIS_CURRENTLY_RUNNING( pxTCB ) || ( pxTCB->xCoreID == !xCurCoreID ) ) ? pdFALSE : pdTRUE; + #else + xFreeNow = ( taskIS_CURRENTLY_RUNNING( pxTCB ) ) ? pdFALSE : pdTRUE; + #endif /* configNUM_CORES > 1 */ + + if( xFreeNow == pdFALSE ) { /* A task is deleting itself. This cannot complete within the * task itself, as a context switch to another task is required. @@ -1389,43 +1441,47 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, * check the xTasksWaitingTermination list. */ ++uxDeletedTasksWaitingCleanUp; + /* Call the delete hook before portPRE_TASK_DELETE_HOOK() as + * portPRE_TASK_DELETE_HOOK() does not return in the Win32 port. */ + traceTASK_DELETE( pxTCB ); + /* The pre-delete hook is primarily for the Windows simulator, * in which Windows specific clean up operations are performed, * after which it is not possible to yield away from this task - * hence xYieldPending is used to latch that a context switch is * required. */ - portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending[core] ); + portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending[ xCurCoreID ] ); - if (configNUM_CORES > 1 && pxTCB == pxCurrentTCB[ !core ]) - { - /* SMP case of deleting a task running on a different core. Same issue - as a task deleting itself, but we need to send a yield to this task now - before we release xTaskQueueMutex. + #if ( configNUM_CORES > 1 ) + if( taskIS_CURRENTLY_RUNNING_ON_CORE( pxTCB, !xCurCoreID ) ) + { + /* SMP case of deleting a task running on a different core. Same issue + as a task deleting itself, but we need to send a yield to this task now + before we release xKernelLock. - Specifically there is a case where the other core may already be spinning on - xTaskQueueMutex waiting to go into a blocked state. A check is added in - prvAddCurrentTaskToDelayedList() to prevent it from removing itself from - xTasksWaitingTermination list in this case (instead it will immediately - release xTaskQueueMutex again and be yielded before the FreeRTOS function - returns.) */ - vPortYieldOtherCore( !core ); - } + Specifically there is a case where the other core may already be spinning on + xKernelLock waiting to go into a blocked state. A check is added in + prvAddCurrentTaskToDelayedList() to prevent it from removing itself from + xTasksWaitingTermination list in this case (instead it will immediately + release xKernelLock again and be yielded before the FreeRTOS function + returns.) */ + vPortYieldOtherCore( !xCurCoreID ); + } + #endif /* configNUM_CORES > 1 */ } else { --uxCurrentNumberOfTasks; - xFreeNow = pdTRUE; + traceTASK_DELETE( pxTCB ); /* Reset the next expected unblock time in case it referred to * the task that has just been deleted. */ prvResetNextTaskUnblockTime(); } - - traceTASK_DELETE( pxTCB ); } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); - if(xFreeNow == pdTRUE) { + if( xFreeNow == pdTRUE ) { #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) && ( configTHREAD_LOCAL_STORAGE_DELETE_CALLBACKS ) prvDeleteTLS( pxTCB ); #endif @@ -1437,7 +1493,8 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, * been deleted. */ if( xSchedulerRunning != pdFALSE ) { - if( pxTCB == curTCB ) + taskENTER_CRITICAL( &xKernelLock ); + if( taskIS_CURRENTLY_RUNNING_ON_CORE( pxTCB, xPortGetCoreID() ) ) { configASSERT( xTaskGetSchedulerState() != taskSCHEDULER_SUSPENDED ); portYIELD_WITHIN_API(); @@ -1446,6 +1503,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, { mtCOVERAGE_TEST_MARKER(); } + taskEXIT_CRITICAL( &xKernelLock ); } } @@ -1467,18 +1525,14 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, const TickType_t xTimeIncrement ) { TickType_t xTimeToWake; -#ifdef ESP_PLATFORM - BaseType_t xShouldDelay = pdFALSE; -#else BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE; -#endif // ESP_PLATFORM configASSERT( pxPreviousWakeTime ); configASSERT( ( xTimeIncrement > 0U ) ); configASSERT( xTaskGetSchedulerState() != taskSCHEDULER_SUSPENDED ); #ifdef ESP_PLATFORM // IDF-3755 - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); #else vTaskSuspendAll(); #endif // ESP_PLATFORM @@ -1526,11 +1580,11 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, if( xShouldDelay != pdFALSE ) { - traceTASK_DELAY_UNTIL(); + traceTASK_DELAY_UNTIL( xTimeToWake ); /* prvAddCurrentTaskToDelayedList() needs the block time, not * the time to wake, so subtract the current tick count. */ - prvAddCurrentTaskToDelayedList( xPortGetCoreID(), xTimeToWake - xConstTickCount ); + prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE ); } else { @@ -1538,16 +1592,14 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, } } #ifdef ESP_PLATFORM // IDF-3755 - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); + xAlreadyYielded = pdFALSE; #else xAlreadyYielded = xTaskResumeAll(); #endif // ESP_PLATFORM /* Force a reschedule if xTaskResumeAll has not already done so, we may * have put ourselves to sleep. */ -#ifdef ESP_PLATFORM - portYIELD_WITHIN_API(); -#else if( xAlreadyYielded == pdFALSE ) { portYIELD_WITHIN_API(); @@ -1556,7 +1608,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, { mtCOVERAGE_TEST_MARKER(); } -#endif // ESP_PLATFORM + return xShouldDelay; } @@ -1567,12 +1619,14 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, void vTaskDelay( const TickType_t xTicksToDelay ) { + BaseType_t xAlreadyYielded = pdFALSE; + /* A delay time of zero just forces a reschedule. */ if( xTicksToDelay > ( TickType_t ) 0U ) { configASSERT( xTaskGetSchedulerState() != taskSCHEDULER_SUSPENDED ); #ifdef ESP_PLATFORM // IDF-3755 - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); #else vTaskSuspendAll(); #endif // ESP_PLATFORM @@ -1586,10 +1640,11 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, * * This task cannot be in an event list as it is the currently * executing task. */ - prvAddCurrentTaskToDelayedList( xPortGetCoreID(), xTicksToDelay ); + prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); } #ifdef ESP_PLATFORM // IDF-3755 - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); + xAlreadyYielded = pdFALSE; #else xAlreadyYielded = xTaskResumeAll(); #endif // ESP_PLATFORM @@ -1599,8 +1654,16 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, mtCOVERAGE_TEST_MARKER(); } - /* Force a reschedule, we may have put ourselves to sleep. */ - portYIELD_WITHIN_API(); + /* Force a reschedule if xTaskResumeAll has not already done so, we may + * have put ourselves to sleep. */ + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } } #endif /* INCLUDE_vTaskDelay */ @@ -1616,19 +1679,12 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, configASSERT( pxTCB ); - taskENTER_CRITICAL(); //Need critical section incase either core context switches in between - if( pxTCB == pxCurrentTCB[xPortGetCoreID()]) + taskENTER_CRITICAL( &xKernelLock ); //Need critical section incase either core context switches in between + if( taskIS_CURRENTLY_RUNNING( pxTCB ) ) { /* The task calling this function is querying its own state. */ eReturn = eRunning; } - #if (configNUM_CORES > 1) - else if (pxTCB == pxCurrentTCB[!xPortGetCoreID()]) - { - /* The task calling this function is querying its own state. */ - eReturn = eRunning; - } - #endif else { pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) ); @@ -1700,7 +1756,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, eReturn = eReady; } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); return eReturn; } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */ @@ -1715,14 +1771,14 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, TCB_t const * pxTCB; UBaseType_t uxReturn; - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); { /* If null is passed in here then it is the priority of the task * that called uxTaskPriorityGet() that is being queried. */ pxTCB = prvGetTCBFromHandle( xTask ); uxReturn = pxTCB->uxPriority; } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); return uxReturn; } @@ -1755,14 +1811,14 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); - portENTER_CRITICAL_ISR(&xTaskQueueMutex ); + taskENTER_CRITICAL_ISR( &xKernelLock ); { /* If null is passed in here then it is the priority of the calling * task that is being queried. */ pxTCB = prvGetTCBFromHandle( xTask ); uxReturn = pxTCB->uxPriority; } - portEXIT_CRITICAL_ISR(&xTaskQueueMutex); + taskEXIT_CRITICAL_ISR( &xKernelLock ); return uxReturn; } @@ -1791,7 +1847,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, mtCOVERAGE_TEST_MARKER(); } - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); { /* If null is passed in here then it is the priority of the calling * task that is being changed. */ @@ -1815,19 +1871,15 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, * priority than the calling task. */ if( uxNewPriority > uxCurrentBasePriority ) { - if( pxTCB != pxCurrentTCB[xPortGetCoreID()] ) + if( !taskIS_CURRENTLY_RUNNING( pxTCB ) ) { /* The priority of a task other than the currently * running task is being raised. Is the priority being * raised above that of the running task? */ - if ( tskCAN_RUN_HERE(pxTCB->xCoreID) && uxNewPriority >= pxCurrentTCB[ xPortGetCoreID() ]->uxPriority ) + if ( prvCheckForYieldUsingPriority( uxNewPriority, pxTCB->xCoreID, xPortGetCoreID(), pdTRUE ) ) { xYieldRequired = pdTRUE; } - else if ( pxTCB->xCoreID != xPortGetCoreID() ) - { - taskYIELD_OTHER_CORE( pxTCB->xCoreID, uxNewPriority ); - } else { mtCOVERAGE_TEST_MARKER(); @@ -1840,31 +1892,22 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, * priority task able to run so no yield is required. */ } } - else if( pxTCB == pxCurrentTCB[xPortGetCoreID()] ) + else if( taskIS_CURRENTLY_RUNNING_ON_CORE( pxTCB, 0 ) ) { /* Setting the priority of the running task down means * there may now be another task of higher priority that * is ready to execute. */ xYieldRequired = pdTRUE; } - else if( pxTCB != pxCurrentTCB[xPortGetCoreID()] ) - { - /* The priority of a task other than the currently - * running task is being raised. Is the priority being - * raised above that of the running task? */ - if( uxNewPriority >= pxCurrentTCB[xPortGetCoreID()]->uxPriority ) + #if ( configNUM_CORES > 1 ) + else if( taskIS_CURRENTLY_RUNNING_ON_CORE( pxTCB, 1 ) ) { - xYieldRequired = pdTRUE; + /* Setting the priority of the running task on the other + * core down means there may now be another task of + * higher priority that is ready to execute. */ + vPortYieldOtherCore( 1 ); } - else if ( pxTCB->xCoreID != xPortGetCoreID() ) //Need to check if not currently running on other core - { - taskYIELD_OTHER_CORE( pxTCB->xCoreID, uxNewPriority ); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - } + #endif /* configNUM_CORES > 1 */ else { /* Setting the priority of any other task down does not @@ -1952,7 +1995,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, ( void ) uxPriorityUsedOnEntry; } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); } #endif /* INCLUDE_vTaskPrioritySet */ @@ -1963,9 +2006,8 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, void vTaskSuspend( TaskHandle_t xTaskToSuspend ) { TCB_t * pxTCB; - TCB_t * curTCB; - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); { /* If null is passed in here then it is the running task that is * being suspended. */ @@ -1995,7 +2037,6 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, } vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ); - curTCB = pxCurrentTCB[ xPortGetCoreID() ]; #if ( configUSE_TASK_NOTIFICATIONS == 1 ) { @@ -2012,76 +2053,70 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, } } #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ - } - taskEXIT_CRITICAL(); - if( xSchedulerRunning != pdFALSE ) - { - /* Reset the next expected unblock time in case it referred to the - * task that is now in the Suspended state. */ - taskENTER_CRITICAL(); - { - prvResetNextTaskUnblockTime(); - } - taskEXIT_CRITICAL(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - - if( pxTCB == curTCB ) - { if( xSchedulerRunning != pdFALSE ) { - /* The current task has just been suspended. */ - taskENTER_CRITICAL(); - BaseType_t suspended = uxSchedulerSuspended[xPortGetCoreID()]; - taskEXIT_CRITICAL(); - - configASSERT( suspended == 0 ); - (void)suspended; - portYIELD_WITHIN_API(); - } - else - { - /* The scheduler is not running, but the task that was pointed - * to by pxCurrentTCB has just been suspended and pxCurrentTCB - * must be adjusted to point to a different task. */ - if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */ - { - /* No other tasks are ready, so set pxCurrentTCB back to - * NULL so when the next task is created pxCurrentTCB will - * be set to point to it no matter what its relative priority - * is. */ - taskENTER_CRITICAL(); - pxCurrentTCB[ xPortGetCoreID() ] = NULL; - taskEXIT_CRITICAL(); - } - else - { - vTaskSwitchContext(); - } - } - } - else - { - if( xSchedulerRunning != pdFALSE ) - { - /* A task other than the currently running task was suspended, - * reset the next expected unblock time in case it referred to the + /* Reset the next expected unblock time in case it referred to the * task that is now in the Suspended state. */ - taskENTER_CRITICAL(); - { - prvResetNextTaskUnblockTime(); - } - taskEXIT_CRITICAL(); + prvResetNextTaskUnblockTime(); } else { mtCOVERAGE_TEST_MARKER(); } + + if( taskIS_CURRENTLY_RUNNING_ON_CORE( pxTCB, xPortGetCoreID() ) ) + { + if( xSchedulerRunning != pdFALSE ) + { + /* The current task has just been suspended. */ + configASSERT( uxSchedulerSuspended[ xPortGetCoreID() ] == 0 ); + portYIELD_WITHIN_API(); + } + else + { + /* The scheduler is not running, but the task that was pointed + * to by pxCurrentTCB has just been suspended and pxCurrentTCB + * must be adjusted to point to a different task. */ + if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */ + { + /* No other tasks are ready, so set pxCurrentTCB back to + * NULL so when the next task is created pxCurrentTCB will + * be set to point to it no matter what its relative priority + * is. */ + pxCurrentTCB[ xPortGetCoreID() ] = NULL; + } + else + { + vTaskSwitchContext(); + } + } + } + #if ( configNUM_CORES > 1 ) + else if( taskIS_CURRENTLY_RUNNING_ON_CORE( pxTCB, !xPortGetCoreID() ) ) + { + /* The other core's current task has just been suspended */ + if( xSchedulerRunning != pdFALSE ) + { + vPortYieldOtherCore( !xPortGetCoreID() ); + } + else + { + /* The scheduler is not running, but the task that was pointed + * to by pxCurrentTCB[ otherCore ] has just been suspended. + * We simply set the pxCurrentTCB[ otherCore ] to NULL for now. + * Todo: Update vTaskSwitchContext() to be runnable on + * behalf of the other core. */ + pxCurrentTCB[ !xPortGetCoreID() ] = NULL; + } + } + #endif /* configNUM_CORES > 1 */ + else + { + mtCOVERAGE_TEST_MARKER(); + } } + taskEXIT_CRITICAL( &xKernelLock ); } #endif /* INCLUDE_vTaskSuspend */ @@ -2104,8 +2139,12 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE ) { /* Has the task already been resumed from within an ISR? */ - if( listIS_CONTAINED_WITHIN( &xPendingReadyList[xPortGetCoreID()], &( pxTCB->xEventListItem )) == pdFALSE && - listIS_CONTAINED_WITHIN( &xPendingReadyList[!xPortGetCoreID()], &( pxTCB->xEventListItem )) == pdFALSE ) + #if ( configNUM_CORES > 1 ) + if( ( listIS_CONTAINED_WITHIN( &xPendingReadyList[ 0 ], &( pxTCB->xEventListItem ) ) == pdFALSE ) + && ( listIS_CONTAINED_WITHIN( &xPendingReadyList[ 1 ], &( pxTCB->xEventListItem ) ) == pdFALSE ) ) + #else + if( listIS_CONTAINED_WITHIN( &xPendingReadyList[ 0 ], &( pxTCB->xEventListItem ) ) == pdFALSE ) + #endif { /* Is it in the suspended list because it is in the Suspended * state, or because is is blocked with no timeout? */ @@ -2142,12 +2181,12 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, /* It does not make sense to resume the calling task. */ configASSERT( xTaskToResume ); - taskENTER_CRITICAL(); - /* The parameter cannot be NULL as it is impossible to resume the - * currently executing task. */ - if( ( pxTCB != pxCurrentTCB[xPortGetCoreID()] ) && ( pxTCB != NULL ) ) + taskENTER_CRITICAL( &xKernelLock ); { + /* The parameter cannot be NULL as it is impossible to resume the + * currently executing task. */ + if( !taskIS_CURRENTLY_RUNNING( pxTCB ) && ( pxTCB != NULL ) ) { if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE ) { @@ -2158,18 +2197,14 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); prvAddTaskToReadyList( pxTCB ); - /* We may have just resumed a higher priority task. */ - if( tskCAN_RUN_HERE(pxTCB->xCoreID) && pxTCB->uxPriority >= pxCurrentTCB[ xPortGetCoreID() ]->uxPriority ) + /* A higher priority task may have just been resumed. */ + if( prvCheckForYield( pxTCB, xPortGetCoreID(), pdTRUE ) ) { /* This yield may not cause the task just resumed to run, * but will leave the lists in the correct state for the * next yield. */ taskYIELD_IF_USING_PREEMPTION(); } - else if( pxTCB->xCoreID != xPortGetCoreID() ) - { - taskYIELD_OTHER_CORE( pxTCB->xCoreID, pxTCB->uxPriority ); - } else { mtCOVERAGE_TEST_MARKER(); @@ -2180,12 +2215,12 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, mtCOVERAGE_TEST_MARKER(); } } + else + { + mtCOVERAGE_TEST_MARKER(); + } } - else - { - mtCOVERAGE_TEST_MARKER(); - } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); } #endif /* INCLUDE_vTaskSuspend */ @@ -2217,41 +2252,43 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, * simple as possible. More information (albeit Cortex-M specific) is * provided on the following link: * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - //portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); - taskENTER_CRITICAL_ISR(); + taskENTER_CRITICAL_ISR( &xKernelLock ); { if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE ) { traceTASK_RESUME_FROM_ISR( pxTCB ); /* Check the ready lists can be accessed. */ - if( uxSchedulerSuspended[xPortGetCoreID()] == ( UBaseType_t ) pdFALSE ) + /* Known issue IDF-5856. We also need to check if the other core is suspended */ + if( uxSchedulerSuspended[ xPortGetCoreID() ] == ( UBaseType_t ) pdFALSE ) { - - ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); - prvAddTaskToReadyList( pxTCB ); - - if( tskCAN_RUN_HERE( pxTCB->xCoreID ) && pxTCB->uxPriority >= pxCurrentTCB[ xPortGetCoreID() ]->uxPriority ) + /* Ready lists can be accessed so move the task from the + * suspended list to the ready list directly. */ + if( prvCheckForYield( pxTCB, xPortGetCoreID(), pdTRUE ) ) { xYieldRequired = pdTRUE; - } - else if ( pxTCB->xCoreID != xPortGetCoreID() ) - { - taskYIELD_OTHER_CORE( pxTCB->xCoreID, pxTCB->uxPriority); + + /* Mark that a yield is pending in case the user is not + * using the return value to initiate a context switch + * from the ISR using portYIELD_FROM_ISR. */ + xYieldPending[ xPortGetCoreID() ] = pdTRUE; } else { mtCOVERAGE_TEST_MARKER(); } + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); } else { /* The delayed or ready lists cannot be accessed so the task * is held in the pending ready list until the scheduler is * unsuspended. */ - vListInsertEnd( &( xPendingReadyList[xPortGetCoreID()] ), &( pxTCB->xEventListItem ) ); + vListInsertEnd( &( xPendingReadyList[ xPortGetCoreID() ] ), &( pxTCB->xEventListItem ) ); } } else @@ -2259,7 +2296,7 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB, mtCOVERAGE_TEST_MARKER(); } } - taskEXIT_CRITICAL_ISR(); + taskEXIT_CRITICAL_ISR( &xKernelLock ); return xYieldRequired; } @@ -2273,7 +2310,7 @@ void vTaskStartScheduler( void ) #ifdef ESP_PLATFORM /* Create an IDLE task for each core */ - for(BaseType_t xCoreID = 0; xCoreID < configNUM_CORES; xCoreID++) + for( BaseType_t xCoreID = 0; xCoreID < configNUM_CORES; xCoreID++ ) #endif //ESP_PLATFORM /* Add the idle task at the lowest priority. */ #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) @@ -2283,7 +2320,7 @@ void vTaskStartScheduler( void ) uint32_t ulIdleTaskStackSize; /* The Idle task is created using user provided RAM - obtain the - address of the RAM then create the idle task. */ + * address of the RAM then create the idle task. */ vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); xIdleTaskHandle[ xCoreID ] = xTaskCreateStaticPinnedToCore( prvIdleTask, configIDLE_TASK_NAME, @@ -2423,12 +2460,12 @@ void vTaskSuspendAll( void ) * BaseType_t. Please read Richard Barry's reply in the following link to a * post in the FreeRTOS support forum before reporting this as a bug! - * https://goo.gl/wu4acr */ -#ifdef ESP_PLATFORM - /* For SMP, although each core has their own uxSchedulerSuspended, we still - * need to disable interrupts or enter a critical section when accessing. */ - unsigned state; - state = portSET_INTERRUPT_MASK_FROM_ISR(); -#endif + + #if ( configNUM_CORES > 1 ) + /* For SMP, although each core has their own uxSchedulerSuspended, we still + * need enter a critical section when accessing. */ + taskENTER_CRITICAL( &xKernelLock ); + #endif /* portSOFRWARE_BARRIER() is only implemented for emulated/simulated ports that * do not otherwise exhibit real time behaviour. */ @@ -2442,55 +2479,53 @@ void vTaskSuspendAll( void ) * the above increment elsewhere. */ portMEMORY_BARRIER(); -#ifdef ESP_PLATFORM - portCLEAR_INTERRUPT_MASK_FROM_ISR( state ); -#endif + #if ( configNUM_CORES > 1 ) + taskEXIT_CRITICAL( &xKernelLock ); + #endif } /*----------------------------------------------------------*/ #if ( configUSE_TICKLESS_IDLE != 0 ) -#if ( configNUM_CORES > 1 ) - - static BaseType_t xHaveReadyTasks( void ) - { - for (int i = tskIDLE_PRIORITY + 1; i < configMAX_PRIORITIES; ++i) - { - if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ i ] ) ) > 0 ) - { - return pdTRUE; - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - } - return pdFALSE; - } - -#endif // configNUM_CORES > 1 - static TickType_t prvGetExpectedIdleTime( void ) { - TickType_t xReturn; + TickType_t xReturn; + UBaseType_t uxHigherPriorityReadyTasks = pdFALSE; + /* We need a critical section here as we are about to access kernel data structures */ + taskENTER_CRITICAL( &xKernelLock ); + + /* uxHigherPriorityReadyTasks takes care of the case where + * configUSE_PREEMPTION is 0, so there may be tasks above the idle priority + * task that are in the Ready state, even though the idle task is + * running. */ + #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) + { + if( uxTopReadyPriority > tskIDLE_PRIORITY ) + { + uxHigherPriorityReadyTasks = pdTRUE; + } + } + #else + { + const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01; + + /* When port optimised task selection is used the uxTopReadyPriority + * variable is used as a bit map. If bits other than the least + * significant bit are set then there are tasks that have a priority + * above the idle priority that are in the Ready state. This takes + * care of the case where the co-operative scheduler is in use. */ + if( uxTopReadyPriority > uxLeastSignificantBit ) + { + uxHigherPriorityReadyTasks = pdTRUE; + } + } + #endif /* if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) */ - taskENTER_CRITICAL(); if( pxCurrentTCB[ xPortGetCoreID() ]->uxPriority > tskIDLE_PRIORITY ) { xReturn = 0; } -#if configNUM_CORES > 1 - /* This function is called from Idle task; in single core case this - * means that no higher priority tasks are ready to run, and we can - * enter sleep. In SMP case, there might be ready tasks waiting for - * the other CPU, so need to check all ready lists. - */ - else if( xHaveReadyTasks() ) - { - xReturn = 0; - } -#endif // configNUM_CORES > 1 else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > configNUM_CORES ) { /* There are other idle priority tasks in the ready state. If @@ -2498,11 +2533,19 @@ void vTaskSuspendAll( void ) * processed. */ xReturn = 0; } + else if( uxHigherPriorityReadyTasks != pdFALSE ) + { + /* There are tasks in the Ready state that have a priority above the + * idle priority. This path can only be reached if + * configUSE_PREEMPTION is 0. */ + xReturn = 0; + } else { xReturn = xNextTaskUnblockTime - xTickCount; } - taskEXIT_CRITICAL(); + + taskEXIT_CRITICAL( &xKernelLock ); return xReturn; } @@ -2524,14 +2567,11 @@ BaseType_t xTaskResumeAll( void ) * removed task will have been added to the xPendingReadyList. Once the * scheduler has been resumed it is safe to move all the pending ready * tasks from this list into their appropriate ready list. */ - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); { -#ifdef ESP_PLATFORM /* Minor optimization. Core ID can't change while inside a critical section */ BaseType_t xCoreID = xPortGetCoreID(); -#else - BaseType_t xCoreID = 0; -#endif + --uxSchedulerSuspended[ xCoreID ]; if( uxSchedulerSuspended[ xCoreID ] == ( UBaseType_t ) pdFALSE ) @@ -2549,7 +2589,7 @@ BaseType_t xTaskResumeAll( void ) /* If the moved task has a priority higher than the current * task then a yield must be performed. */ - if( pxTCB->uxPriority >= pxCurrentTCB[ xCoreID ]->uxPriority ) + if( prvCheckForYield( pxTCB, xPortGetCoreID(), pdTRUE ) ) { xYieldPending[ xCoreID ] = pdTRUE; } @@ -2574,11 +2614,9 @@ BaseType_t xTaskResumeAll( void ) * they should be processed now. This ensures the tick count does * not slip, and that any delayed tasks are resumed at the correct * time. */ -#ifdef ESP_PLATFORM /* Core 0 is solely responsible for managing tick count, thus it * must be the only core to unwind the pended ticks */ if ( xCoreID == 0 ) -#endif { TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ @@ -2626,7 +2664,7 @@ BaseType_t xTaskResumeAll( void ) mtCOVERAGE_TEST_MARKER(); } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); return xAlreadyYielded; } @@ -2636,7 +2674,12 @@ TickType_t xTaskGetTickCount( void ) { TickType_t xTicks; - xTicks = xTickCount; + /* Critical section required if running on a 16 bit processor. */ + portTICK_TYPE_ENTER_CRITICAL(); + { + xTicks = xTickCount; + } + portTICK_TYPE_EXIT_CRITICAL(); return xTicks; } @@ -2645,7 +2688,6 @@ TickType_t xTaskGetTickCount( void ) TickType_t xTaskGetTickCountFromISR( void ) { TickType_t xReturn; - UBaseType_t uxSavedInterruptStatus; /* RTOS ports that support interrupt nesting have the concept of a maximum * system call (or maximum API call) interrupt priority. Interrupts that are @@ -2663,11 +2705,21 @@ TickType_t xTaskGetTickCountFromISR( void ) * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); - uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR(); + #if ( configNUM_CORES > 1 ) + /* We need a critical section here as we are about to access kernel data structures */ + taskENTER_CRITICAL_ISR( &xKernelLock ); + #else + UBaseType_t uxSavedInterruptStatus; + uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR(); + #endif { xReturn = xTickCount; } - portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + #if ( configNUM_CORES > 1 ) + taskEXIT_CRITICAL_ISR( &xKernelLock ); + #else + portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + #endif return xReturn; } @@ -2773,7 +2825,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN ); #ifdef ESP_PLATFORM // IDF-3755 - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); #else vTaskSuspendAll(); #endif // ESP_PLATFORM @@ -2823,7 +2875,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char #endif } #ifdef ESP_PLATFORM // IDF-3755 - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); #else ( void ) xTaskResumeAll(); #endif // ESP_PLATFORM @@ -2843,7 +2895,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES; #ifdef ESP_PLATFORM // IDF-3755 - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); #else vTaskSuspendAll(); #endif // ESP_PLATFORM @@ -2906,7 +2958,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char } } #ifdef ESP_PLATFORM // IDF-3755 - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); #else ( void ) xTaskResumeAll(); #endif // ESP_PLATFORM @@ -2946,7 +2998,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char { #ifdef ESP_PLATFORM /* For SMP, we require a critical section to access xTickCount */ - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); #endif /* Correct the tick count value after a period during which the tick * was suppressed. Note this does *not* call the tick hook function for @@ -2955,7 +3007,7 @@ char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char xTickCount += xTicksToJump; traceINCREASE_TICK_COUNT( xTicksToJump ); #ifdef ESP_PLATFORM - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); #endif } @@ -2980,9 +3032,9 @@ BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) #ifdef ESP_PLATFORM /* For SMP, we still require a critical section to access xPendedTicks even * if the scheduler is disabled. */ - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); xPendedTicks += xTicksToCatchUp; - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); #else // ESP_PLATFORM xPendedTicks += xTicksToCatchUp; #endif // ESP_PLATFORM @@ -3002,7 +3054,7 @@ BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) configASSERT( pxTCB ); #ifdef ESP_PLATFORM // IDF-3755 - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); #else vTaskSuspendAll(); #endif // ESP_PLATFORM @@ -3022,7 +3074,7 @@ BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) * the event list too. Interrupts can touch the event list item, * even though the scheduler is suspended, so a critical section * is used. */ - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); { if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) { @@ -3038,7 +3090,7 @@ BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) mtCOVERAGE_TEST_MARKER(); } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); /* Place the unblocked task into the appropriate ready list. */ prvAddTaskToReadyList( pxTCB ); @@ -3050,15 +3102,11 @@ BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) /* Preemption is on, but a context switch should only be * performed if the unblocked task has a priority that is * equal to or higher than the currently executing task. */ - if( tskCAN_RUN_HERE(pxTCB->xCoreID) && pxTCB->uxPriority >= pxCurrentTCB[ xPortGetCoreID() ]->uxPriority ) + if( prvCheckForYield( pxTCB, xPortGetCoreID(), pdFALSE ) ) { /* Pend the yield to be performed when the scheduler * is unsuspended. */ - xYieldPending[xPortGetCoreID()] = pdTRUE; - } - else if ( pxTCB->xCoreID != xPortGetCoreID() ) - { - taskYIELD_OTHER_CORE( pxTCB->xCoreID, pxTCB->uxPriority ); + xYieldPending[ xPortGetCoreID() ] = pdTRUE; } else { @@ -3073,7 +3121,7 @@ BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) } } #ifdef ESP_PLATFORM // IDF-3755 - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); #else ( void ) xTaskResumeAll(); #endif // ESP_PLATFORM @@ -3109,7 +3157,7 @@ BaseType_t xTaskIncrementTick( void ) * - Other cores could be accessing them simultaneously * - Unlike other ports, we call xTaskIncrementTick() without disabling nested * interrupts, which in turn is disabled by the critical section. */ - taskENTER_CRITICAL_ISR(); + taskENTER_CRITICAL_ISR( &xKernelLock ); #endif // ESP_PLATFORM if( uxSchedulerSuspended[ 0 ] == ( UBaseType_t ) pdFALSE ) @@ -3241,7 +3289,7 @@ BaseType_t xTaskIncrementTick( void ) TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ #endif /* configUSE_TICK_HOOK */ /* Exit the critical section as we have finished accessing the kernel data structures. */ - taskEXIT_CRITICAL_ISR(); + taskEXIT_CRITICAL_ISR( &xKernelLock ); #endif // ESP_PLATFORM #if ( configUSE_TICK_HOOK == 1 ) @@ -3281,7 +3329,7 @@ BaseType_t xTaskIncrementTick( void ) ++xPendedTicks; #ifdef ESP_PLATFORM /* Exit the critical section as we have finished accessing the kernel data structures. */ - taskEXIT_CRITICAL_ISR(); + taskEXIT_CRITICAL_ISR( &xKernelLock ); #endif // ESP_PLATFORM /* The tick hook gets called at regular intervals, even if the @@ -3320,7 +3368,7 @@ BaseType_t xTaskIncrementTick( void ) * - Unlike other ports, we call xTaskIncrementTick() without disabling * nested interrupts, which in turn is disabled by the critical * section. */ - taskENTER_CRITICAL_ISR(); + taskENTER_CRITICAL_ISR( &xKernelLock ); /* A task being unblocked cannot cause an immediate context switch * if preemption is turned off. */ @@ -3354,7 +3402,7 @@ BaseType_t xTaskIncrementTick( void ) #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */ /* Exit the critical section as we have finished accessing the kernel data structures. */ - taskEXIT_CRITICAL_ISR(); + taskEXIT_CRITICAL_ISR( &xKernelLock ); #if ( configUSE_PREEMPTION == 1 ) { @@ -3402,11 +3450,11 @@ BaseType_t xTaskIncrementTick( void ) /* Save the hook function in the TCB. A critical section is required as * the value can be accessed from an interrupt. */ - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); { xTCB->pxTaskTag = pxHookFunction; } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); } #endif /* configUSE_APPLICATION_TASK_TAG */ @@ -3424,11 +3472,11 @@ BaseType_t xTaskIncrementTick( void ) /* Save the hook function in the TCB. A critical section is required as * the value can be accessed from an interrupt. */ - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); { xReturn = pxTCB->pxTaskTag; } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); return xReturn; } @@ -3442,28 +3490,26 @@ BaseType_t xTaskIncrementTick( void ) { TCB_t * pxTCB; TaskHookFunction_t xReturn; -#ifndef ESP_PLATFORM - UBaseType_t uxSavedInterruptStatus; -#endif /* If xTask is NULL then set the calling task's hook. */ pxTCB = prvGetTCBFromHandle( xTask ); /* Save the hook function in the TCB. A critical section is required as * the value can be accessed from an interrupt. */ -#ifdef ESP_PLATFORM - portENTER_CRITICAL_ISR(&xTaskQueueMutex); -#else - uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); -#endif + #if ( configNUM_CORES > 1 ) + taskENTER_CRITICAL_ISR( &xKernelLock ); + #else + UBaseType_t uxSavedInterruptStatus; + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + #endif { xReturn = pxTCB->pxTaskTag; } -#ifdef ESP_PLATFORM - portEXIT_CRITICAL_ISR(&xTaskQueueMutex); -#else - portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); -#endif + #if ( configNUM_CORES > 1 ) + taskEXIT_CRITICAL_ISR( &xKernelLock ); + #else + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + #endif return xReturn; } @@ -3598,7 +3644,7 @@ void vTaskSwitchContext( void ) * - ISR dispatcher when return from an ISR (interrupts will already be disabled) * - vTaskSuspend() which is not in a critical section * Therefore, we enter a critical section ISR version to ensure safety */ - taskENTER_CRITICAL_ISR(); + taskENTER_CRITICAL_ISR( &xKernelLock ); #endif // ESP_PLATFORM if( uxSchedulerSuspended[ xPortGetCoreID() ] != ( UBaseType_t ) pdFALSE ) { @@ -3688,7 +3734,7 @@ void vTaskSwitchContext( void ) } #ifdef ESP_PLATFORM /* Exit the critical section previously entered */ - taskEXIT_CRITICAL_ISR(); + taskEXIT_CRITICAL_ISR( &xKernelLock ); #endif // ESP_PLATFORM } /*-----------------------------------------------------------*/ @@ -3697,7 +3743,9 @@ void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) { configASSERT( pxEventList ); - taskENTER_CRITICAL(); + + /* Take the kernel lock as we are about to access the task lists. */ + taskENTER_CRITICAL( &xKernelLock ); /* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE * SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */ @@ -3706,10 +3754,11 @@ void vTaskPlaceOnEventList( List_t * const pxEventList, * This is placed in the list in priority order so the highest priority task * is the first to be woken by the event. The queue that contains the event * list is locked, preventing simultaneous access from interrupts. */ - vListInsert( pxEventList, &( pxCurrentTCB[xPortGetCoreID()]->xEventListItem ) ); + vListInsert( pxEventList, &( pxCurrentTCB[ xPortGetCoreID() ]->xEventListItem ) ); - prvAddCurrentTaskToDelayedList( xPortGetCoreID(), xTicksToWait); - taskEXIT_CRITICAL(); + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); + + taskEXIT_CRITICAL( &xKernelLock ); } /*-----------------------------------------------------------*/ @@ -3718,22 +3767,30 @@ void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xTicksToWait ) { configASSERT( pxEventList ); - taskENTER_CRITICAL(); + + /* Take the kernel lock as we are about to access the task lists. */ + taskENTER_CRITICAL( &xKernelLock ); + + /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by + * the event groups implementation. */ + /* Note. We currently don't always suspend the scheduler. Todo: IDF-3755 + * configASSERT( uxSchedulerSuspended[ xPortGetCoreID() ] != 0 ); */ /* Store the item value in the event list item. It is safe to access the * event list item here as interrupts won't access the event list item of a * task that is not in the Blocked state. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB[xPortGetCoreID()]->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE ); + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB[ xPortGetCoreID() ]->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE ); /* Place the event list item of the TCB at the end of the appropriate event * list. It is safe to access the event list here because it is part of an * event group implementation - and interrupts don't access event groups * directly (instead they access them indirectly by pending function calls to * the task level). */ - vListInsertEnd( pxEventList, &( pxCurrentTCB[xPortGetCoreID()]->xEventListItem ) ); + vListInsertEnd( pxEventList, &( pxCurrentTCB[ xPortGetCoreID() ]->xEventListItem ) ); - prvAddCurrentTaskToDelayedList( xPortGetCoreID(), xTicksToWait ); - taskEXIT_CRITICAL(); + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); + + taskEXIT_CRITICAL( &xKernelLock ); } /*-----------------------------------------------------------*/ @@ -3741,9 +3798,11 @@ void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { - taskENTER_CRITICAL(); configASSERT( pxEventList ); + /* Take the kernel lock as we are about to access the task lists. */ + taskENTER_CRITICAL( &xKernelLock ); + /* This function should not be called by application code hence the * 'Restricted' in its name. It is not part of the public API. It is * designed for use by kernel code, and has special calling requirements - @@ -3754,7 +3813,7 @@ void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, * In this case it is assume that this is the only task that is going to * be waiting on this event list, so the faster vListInsertEnd() function * can be used in place of vListInsert. */ - vListInsertEnd( pxEventList, &( pxCurrentTCB[xPortGetCoreID()]->xEventListItem ) ); + vListInsertEnd( pxEventList, &( pxCurrentTCB[ xPortGetCoreID() ]->xEventListItem ) ); /* If the task should block indefinitely then set the block time to a * value that will be recognised as an indefinite delay inside the @@ -3764,9 +3823,10 @@ void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, xTicksToWait = portMAX_DELAY; } - traceTASK_DELAY_UNTIL( ); - prvAddCurrentTaskToDelayedList( xPortGetCoreID(), xTicksToWait ); - taskEXIT_CRITICAL(); + traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) ); + prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely ); + + taskEXIT_CRITICAL( &xKernelLock ); } #endif /* configUSE_TIMERS */ @@ -3776,117 +3836,125 @@ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) { TCB_t * pxUnblockedTCB; BaseType_t xReturn; - BaseType_t xTaskCanBeReady; - UBaseType_t i, uxTargetCPU; - taskENTER_CRITICAL_ISR(); /* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION. It can also be - * called from a critical section within an ISR. */ - - /* The event list is sorted in priority order, so the first in the list can - * be removed as it is known to be the highest priority. Remove the TCB from - * the delayed list, and add it to the ready list. + * called from a critical section within an ISR. * - * If an event is for a queue that is locked then this function will never - * get called - the lock count on the queue will get modified instead. This - * means exclusive access to the event list is guaranteed here. - * - * This function assumes that a check has already been made to ensure that - * pxEventList is not empty. */ - if ( ( listLIST_IS_EMPTY( pxEventList ) ) == pdFALSE ) + * However, we still need to take the kernel lock as we are about to access + * kernel data structures. Note that we use the ISR version of the macro as + * this function could be called from an ISR critical section. */ + taskENTER_CRITICAL_ISR( &xKernelLock ); { - pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ - configASSERT( pxUnblockedTCB ); - ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); - } - else - { - taskEXIT_CRITICAL_ISR(); - return pdFALSE; - } - - xTaskCanBeReady = pdFALSE; - if ( pxUnblockedTCB->xCoreID == tskNO_AFFINITY ) - { - uxTargetCPU = xPortGetCoreID(); - for (i = 0; i < configNUM_CORES; i++) + /* Before taking the kernel lock, another task/ISR could have already + * emptied the pxEventList. So we insert a check here to see if + * pxEventList is empty before attempting to remove an item from it. */ + if( listLIST_IS_EMPTY( pxEventList ) == pdFALSE ) { - if ( uxSchedulerSuspended[ i ] == ( UBaseType_t ) pdFALSE ) + BaseType_t xCurCoreID = xPortGetCoreID(); + + /* The event list is sorted in priority order, so the first in the list can + * be removed as it is known to be the highest priority. Remove the TCB from + * the delayed list, and add it to the ready list. + * + * If an event is for a queue that is locked then this function will never + * get called - the lock count on the queue will get modified instead. This + * means exclusive access to the event list is guaranteed here. + * + * This function assumes that a check has already been made to ensure that + * pxEventList is not empty. */ + pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + configASSERT( pxUnblockedTCB ); + ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); + + /* Add the task to the ready list if a core with compatible affinity + * has NOT suspended its scheduler. This occurs when: + * - The task is pinned, and the pinned core's scheduler is running + * - The task is unpinned, and at least one of the core's scheduler is running */ + #if ( configNUM_CORES > 1 ) + if( ( ( uxSchedulerSuspended[ 0 ] == ( UBaseType_t ) pdFALSE ) && ( taskCAN_RUN_ON_CORE( 0, pxUnblockedTCB->xCoreID) == pdTRUE ) ) + || ( ( uxSchedulerSuspended[ 1 ] == ( UBaseType_t ) pdFALSE ) && ( taskCAN_RUN_ON_CORE( 1, pxUnblockedTCB->xCoreID) == pdTRUE ) ) ) + #else + if( uxSchedulerSuspended[ 0 ] == ( UBaseType_t ) pdFALSE ) + #endif /* configNUM_CORES > 1 */ { - xTaskCanBeReady = pdTRUE; - break; + ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxUnblockedTCB ); + + #if ( configUSE_TICKLESS_IDLE != 0 ) + { + /* If a task is blocked on a kernel object then xNextTaskUnblockTime + * might be set to the blocked task's time out time. If the task is + * unblocked for a reason other than a timeout xNextTaskUnblockTime is + * normally left unchanged, because it is automatically reset to a new + * value when the tick count equals xNextTaskUnblockTime. However if + * tickless idling is used it might be more important to enter sleep mode + * at the earliest possible time - so reset xNextTaskUnblockTime here to + * ensure it is updated at the earliest possible time. */ + prvResetNextTaskUnblockTime(); + } + #endif + } + else + { + /* We arrive here due to one of the following possibilities: + * - The task is pinned to core X and core X has suspended its scheduler + * - The task is unpinned and both cores have suspend their schedulers + * Therefore, we add the task to one of the pending lists: + * - If the task is pinned to core X, add it to core X's pending list + * - If the task is unpinned, add it to the current core's pending list */ + BaseType_t xPendingListCore; + #if ( configNUM_CORES > 1 ) + xPendingListCore = ( ( pxUnblockedTCB->xCoreID == tskNO_AFFINITY ) ? xCurCoreID : pxUnblockedTCB->xCoreID ); + #else + xPendingListCore = 0; + #endif /* configNUM_CORES > 1 */ + configASSERT( uxSchedulerSuspended[ xPendingListCore ] == pdTRUE ); + + /* The delayed and ready lists cannot be accessed, so hold this task + * pending until the scheduler is resumed. */ + vListInsertEnd( &( xPendingReadyList[ xPendingListCore ] ), &( pxUnblockedTCB->xEventListItem ) ); + } + + if( prvCheckForYield( pxUnblockedTCB, xCurCoreID, pdFALSE ) ) + { + /* Return true if the task removed from the event list has a higher + * priority than the calling task. This allows the calling task to know if + * it should force a context switch now. */ + xReturn = pdTRUE; + + /* Mark that a yield is pending in case the user is not using the + * "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ + xYieldPending[ xCurCoreID ] = pdTRUE; + } + else + { + xReturn = pdFALSE; } } + else + { + /* The pxEventList was emptied before we entered the critical section, + * Nothing to do except return pdFALSE. */ + xReturn = pdFALSE; + } } - else - { - uxTargetCPU = pxUnblockedTCB->xCoreID; - xTaskCanBeReady = uxSchedulerSuspended[ uxTargetCPU ] == ( UBaseType_t ) pdFALSE; - } + taskEXIT_CRITICAL_ISR( &xKernelLock ); - if( xTaskCanBeReady ) - { - ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); - prvAddTaskToReadyList( pxUnblockedTCB ); - } - else - { - /* The delayed and ready lists cannot be accessed, so hold this task - * pending until the scheduler is resumed on this CPU. */ - vListInsertEnd( &( xPendingReadyList[ uxTargetCPU ] ), &( pxUnblockedTCB->xEventListItem ) ); - } - - if ( tskCAN_RUN_HERE(pxUnblockedTCB->xCoreID) && pxUnblockedTCB->uxPriority >= pxCurrentTCB[ xPortGetCoreID() ]->uxPriority ) - { - /* Return true if the task removed from the event list has a higher - * priority than the calling task. This allows the calling task to know if - * it should force a context switch now. */ - xReturn = pdTRUE; - - /* Mark that a yield is pending in case the user is not using the - * "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ - xYieldPending[ xPortGetCoreID() ] = pdTRUE; - } - else if ( pxUnblockedTCB->xCoreID != xPortGetCoreID() ) - { - taskYIELD_OTHER_CORE( pxUnblockedTCB->xCoreID, pxUnblockedTCB->uxPriority ); - xReturn = pdFALSE; - } - else - { - xReturn = pdFALSE; - } - - #if( configUSE_TICKLESS_IDLE != 0 ) - { - /* If a task is blocked on a kernel object then xNextTaskUnblockTime - might be set to the blocked task's time out time. If the task is - unblocked for a reason other than a timeout xNextTaskUnblockTime is - normally left unchanged, because it is automatically reset to a new - value when the tick count equals xNextTaskUnblockTime. However if - tickless idling is used it might be more important to enter sleep mode - at the earliest possible time - so reset xNextTaskUnblockTime here to - ensure it is updated at the earliest possible time. */ - prvResetNextTaskUnblockTime(); - } - #endif - - taskEXIT_CRITICAL_ISR(); return xReturn; } /*-----------------------------------------------------------*/ #ifdef ESP_PLATFORM -void vTaskTakeEventListLock( void ) +void vTaskTakeKernelLock( void ) { - /* We call the tasks.c critical section macro to take xTaskQueueMutex */ - taskENTER_CRITICAL(); + /* We call the tasks.c critical section macro to take xKernelLock */ + taskENTER_CRITICAL( &xKernelLock ); } -void vTaskReleaseEventListLock( void ) +void vTaskReleaseKernelLock( void ) { - /* We call the tasks.c critical section macro to release xTaskQueueMutex */ - taskEXIT_CRITICAL(); + /* We call the tasks.c critical section macro to release xKernelLock */ + taskEXIT_CRITICAL( &xKernelLock ); } #endif // ESP_PLATFORM @@ -3894,48 +3962,65 @@ void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) { TCB_t * pxUnblockedTCB; + BaseType_t xCurCoreID = xPortGetCoreID(); - taskENTER_CRITICAL(); + /* THIS FUNCTION MUST BE CALLED WITH THE KERNEL LOCK ALREADY TAKEN. + * It is used by the event flags implementation, thus those functions + * should call vTaskTakeKernelLock() before calling this function. */ + /* + Todo: IDF-5785 + configASSERT( uxSchedulerSuspended[ xCurCoreID ] != pdFALSE ); + */ /* Store the new item value in the event list. */ listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE ); /* Remove the event list form the event flag. Interrupts do not access * event flags. */ - pxUnblockedTCB = ( TCB_t * ) listGET_LIST_ITEM_OWNER( pxEventListItem ); + pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ configASSERT( pxUnblockedTCB ); ( void ) uxListRemove( pxEventListItem ); + #if ( configUSE_TICKLESS_IDLE != 0 ) + { + /* If a task is blocked on a kernel object then xNextTaskUnblockTime + * might be set to the blocked task's time out time. If the task is + * unblocked for a reason other than a timeout xNextTaskUnblockTime is + * normally left unchanged, because it is automatically reset to a new + * value when the tick count equals xNextTaskUnblockTime. However if + * tickless idling is used it might be more important to enter sleep mode + * at the earliest possible time - so reset xNextTaskUnblockTime here to + * ensure it is updated at the earliest possible time. */ + prvResetNextTaskUnblockTime(); + } + #endif + /* Remove the task from the delayed list and add it to the ready list. The * scheduler is suspended so interrupts will not be accessing the ready * lists. */ ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); prvAddTaskToReadyList( pxUnblockedTCB ); - if ( tskCAN_RUN_HERE(pxUnblockedTCB->xCoreID) && pxUnblockedTCB->uxPriority >= pxCurrentTCB[ xPortGetCoreID() ]->uxPriority ) + if( prvCheckForYield( pxUnblockedTCB, xCurCoreID, pdFALSE ) ) { - /* Mark that a yield is pending in case the user is not using the - * "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ - xYieldPending[ xPortGetCoreID() ] = pdTRUE; + /* The unblocked task has a priority above that of the calling task, so + * a context switch is required. This function is called with the + * scheduler suspended so xYieldPending is set so the context switch + * occurs immediately that the scheduler is resumed (unsuspended). */ + xYieldPending[ xCurCoreID ] = pdTRUE; } - else if ( pxUnblockedTCB->xCoreID != xPortGetCoreID() ) - { - taskYIELD_OTHER_CORE( pxUnblockedTCB->xCoreID, pxUnblockedTCB->uxPriority ); - } - - taskEXIT_CRITICAL(); } /*-----------------------------------------------------------*/ void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) { configASSERT( pxTimeOut ); - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); { pxTimeOut->xOverflowCount = xNumOfOverflows; pxTimeOut->xTimeOnEntering = xTickCount; } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); } /*-----------------------------------------------------------*/ @@ -3955,7 +4040,7 @@ void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) */ #if ( ( ESP_PLATFORM == 1 ) && ( configNUM_CORES > 1 ) ) configASSERT( pxTimeOut ); - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); #endif // ( ( ESP_PLATFORM == 1 ) && ( configNUM_CORES > 1 ) ) /* For internal use only as it does not use a critical section. */ @@ -3963,7 +4048,7 @@ void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) pxTimeOut->xTimeOnEntering = xTickCount; #if ( ( ESP_PLATFORM == 1 ) && ( configNUM_CORES > 1 ) ) - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); #endif // ( ( ESP_PLATFORM == 1 ) && ( configNUM_CORES > 1 ) ) } /*-----------------------------------------------------------*/ @@ -3976,7 +4061,7 @@ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, configASSERT( pxTimeOut ); configASSERT( pxTicksToWait ); - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount; @@ -4012,6 +4097,7 @@ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, * around and gone past again. This passed since vTaskSetTimeout() * was called. */ xReturn = pdTRUE; + *pxTicksToWait = ( TickType_t ) 0; } else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ { @@ -4022,11 +4108,11 @@ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, } else { - *pxTicksToWait = 0; + *pxTicksToWait = ( TickType_t ) 0; xReturn = pdTRUE; } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); return xReturn; } @@ -4175,7 +4261,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters ) if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP ) { #ifdef ESP_PLATFORM // IDF-3755 - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); #else vTaskSuspendAll(); #endif // ESP_PLATFORM @@ -4203,7 +4289,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters ) } } #ifdef ESP_PLATFORM // IDF-3755 - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); #else ( void ) xTaskResumeAll(); #endif // ESP_PLATFORM @@ -4226,7 +4312,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters ) const UBaseType_t uxNonApplicationTasks = 1; eSleepModeStatus eReturn = eStandardSleep; - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); if( listCURRENT_LIST_LENGTH( &xPendingReadyList[xPortGetCoreID()] ) != 0 ) { /* A task was made ready while the scheduler was suspended. */ @@ -4252,7 +4338,7 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters ) mtCOVERAGE_TEST_MARKER(); } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); return eReturn; } @@ -4270,11 +4356,11 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters ) if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS ) { - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); pxTCB = prvGetTCBFromHandle( xTaskToSet ); pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue; pxTCB->pvThreadLocalStoragePointersDelCallback[ xIndex ] = xDelCallback; - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); } } @@ -4293,10 +4379,10 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters ) if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS ) { - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); pxTCB = prvGetTCBFromHandle( xTaskToSet ); pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue; - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); } } #endif /* configTHREAD_LOCAL_STORAGE_DELETE_CALLBACKS */ @@ -4357,13 +4443,10 @@ static void prvInitialiseTaskLists( void ) vListInitialise( &xDelayedTaskList1 ); vListInitialise( &xDelayedTaskList2 ); - #if ( configNUM_CORES > 1 ) - for(BaseType_t i = 0; i < configNUM_CORES; i++) { - vListInitialise( &xPendingReadyList[ i ] ); + for( BaseType_t x = 0; x < configNUM_CORES; x++ ) + { + vListInitialise( &xPendingReadyList[ x ] ); } - #else - vListInitialise( &xPendingReadyList[xPortGetCoreID()] ); - #endif #if ( INCLUDE_vTaskDelete == 1 ) { @@ -4393,13 +4476,13 @@ static void prvCheckTasksWaitingTermination( void ) BaseType_t xListIsEmpty; BaseType_t core = xPortGetCoreID(); - /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() + /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL( &xKernelLock ) * being called too often in the idle task. */ while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) { TCB_t *pxTCB = NULL; - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); { xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination ); if( xListIsEmpty == pdFALSE ) @@ -4426,7 +4509,7 @@ static void prvCheckTasksWaitingTermination( void ) } } } - taskEXIT_CRITICAL(); //Need to call deletion callbacks outside critical section + taskEXIT_CRITICAL( &xKernelLock ); //Need to call deletion callbacks outside critical section if (pxTCB != NULL) { //Call deletion callbacks and free TCB memory #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) && ( configTHREAD_LOCAL_STORAGE_DELETE_CALLBACKS ) @@ -4462,9 +4545,8 @@ static void prvCheckTasksWaitingTermination( void ) pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority; pxTaskStatus->pxStackBase = pxTCB->pxStack; pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber; - #if ( configTASKLIST_INCLUDE_COREID == 1 ) - pxTaskStatus->xCoreID = pxTCB->xCoreID; + pxTaskStatus->xCoreID = pxTCB->xCoreID; #endif /* configTASKLIST_INCLUDE_COREID */ #if ( configUSE_MUTEXES == 1 ) @@ -4508,7 +4590,7 @@ static void prvCheckTasksWaitingTermination( void ) if( eState == eSuspended ) { #ifdef ESP_PLATFORM // IDF-3755 - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); #else vTaskSuspendAll(); #endif // ESP_PLATFORM @@ -4519,7 +4601,7 @@ static void prvCheckTasksWaitingTermination( void ) } } #ifdef ESP_PLATFORM // IDF-3755 - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); #else ( void ) xTaskResumeAll(); #endif // ESP_PLATFORM @@ -4843,6 +4925,7 @@ static void prvResetNextTaskUnblockTime( void ) BaseType_t xReturn; unsigned state; + /* Known issue. This should use critical sections. See IDF-5889 */ state = portSET_INTERRUPT_MASK_FROM_ISR(); if( xSchedulerRunning == pdFALSE ) { @@ -4874,7 +4957,7 @@ static void prvResetNextTaskUnblockTime( void ) TCB_t * const pxMutexHolderTCB = pxMutexHolder; BaseType_t xReturn = pdFALSE; - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); /* If the mutex was given back by an interrupt while the queue was * locked then the mutex holder might now be NULL. _RB_ Is this still * needed as interrupts can no longer use mutexes? */ @@ -4951,7 +5034,7 @@ static void prvResetNextTaskUnblockTime( void ) { mtCOVERAGE_TEST_MARKER(); } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); return xReturn; } @@ -4966,7 +5049,7 @@ static void prvResetNextTaskUnblockTime( void ) TCB_t * const pxTCB = pxMutexHolder; BaseType_t xReturn = pdFALSE; - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); if( pxMutexHolder != NULL ) { /* A task can only have an inherited priority if it holds the mutex. @@ -5033,7 +5116,7 @@ static void prvResetNextTaskUnblockTime( void ) { mtCOVERAGE_TEST_MARKER(); } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); return xReturn; } @@ -5050,7 +5133,7 @@ static void prvResetNextTaskUnblockTime( void ) UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse; const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1; - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); if( pxMutexHolder != NULL ) { /* If pxMutexHolder is not NULL then the holder must hold at least @@ -5143,7 +5226,7 @@ static void prvResetNextTaskUnblockTime( void ) { mtCOVERAGE_TEST_MARKER(); } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); } #endif /* configUSE_MUTEXES */ @@ -5477,14 +5560,18 @@ static void prvResetNextTaskUnblockTime( void ) TickType_t uxTaskResetEventItemValue( void ) { TickType_t uxReturn; + TCB_t *pxCurTCB; - taskENTER_CRITICAL(); - uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB[ xPortGetCoreID() ]->xEventListItem ) ); + taskENTER_CRITICAL( &xKernelLock ); + pxCurTCB = pxCurrentTCB[ xPortGetCoreID() ]; + + uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurTCB->xEventListItem ) ); /* Reset the event list item to its normal value - so it can be used with * queues and semaphores. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB[ xPortGetCoreID() ]->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB[ xPortGetCoreID() ]->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ - taskEXIT_CRITICAL(); + listSET_LIST_ITEM_VALUE( &( pxCurTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + + taskEXIT_CRITICAL( &xKernelLock ); return uxReturn; } @@ -5498,13 +5585,13 @@ TickType_t uxTaskResetEventItemValue( void ) /* If xSemaphoreCreateMutex() is called before any tasks have been created * then pxCurrentTCB will be NULL. */ - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); if( pxCurrentTCB[ xPortGetCoreID() ] != NULL ) { ( pxCurrentTCB[ xPortGetCoreID() ]->uxMutexesHeld )++; } curTCB = pxCurrentTCB[ xPortGetCoreID() ]; - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); return curTCB; } @@ -5532,7 +5619,7 @@ TickType_t uxTaskResetEventItemValue( void ) configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES ); - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); { /* Only block if the notification count is not already non-zero. */ if( pxCurrentTCB[xPortGetCoreID()]->ulNotifiedValue[ uxIndexToWait ] == 0UL ) @@ -5542,7 +5629,7 @@ TickType_t uxTaskResetEventItemValue( void ) if( xTicksToWait > ( TickType_t ) 0 ) { - prvAddCurrentTaskToDelayedList( xPortGetCoreID(), xTicksToWait ); + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWait ); /* All ports are written to allow a yield in a critical @@ -5561,9 +5648,9 @@ TickType_t uxTaskResetEventItemValue( void ) mtCOVERAGE_TEST_MARKER(); } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); { traceTASK_NOTIFY_TAKE( uxIndexToWait ); ulReturn = pxCurrentTCB[xPortGetCoreID()]->ulNotifiedValue[ uxIndexToWait ]; @@ -5586,7 +5673,7 @@ TickType_t uxTaskResetEventItemValue( void ) pxCurrentTCB[xPortGetCoreID()]->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION; } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); return ulReturn; } @@ -5618,7 +5705,7 @@ TickType_t uxTaskResetEventItemValue( void ) configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES ); - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); { /* Only block if a notification is not already pending. */ if( pxCurrentTCB[xPortGetCoreID()]->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED ) @@ -5633,7 +5720,7 @@ TickType_t uxTaskResetEventItemValue( void ) if( xTicksToWait > ( TickType_t ) 0 ) { - prvAddCurrentTaskToDelayedList( xPortGetCoreID(), xTicksToWait); + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWait ); /* All ports are written to allow a yield in a critical @@ -5652,9 +5739,9 @@ TickType_t uxTaskResetEventItemValue( void ) mtCOVERAGE_TEST_MARKER(); } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); { traceTASK_NOTIFY_WAIT( uxIndexToWait ); @@ -5684,7 +5771,7 @@ TickType_t uxTaskResetEventItemValue( void ) pxCurrentTCB[xPortGetCoreID()]->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION; } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); return xReturn; } @@ -5708,7 +5795,7 @@ TickType_t uxTaskResetEventItemValue( void ) configASSERT( xTaskToNotify ); pxTCB = xTaskToNotify; - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); { if( pulPreviousNotificationValue != NULL ) { @@ -5791,15 +5878,11 @@ TickType_t uxTaskResetEventItemValue( void ) } #endif - if( tskCAN_RUN_HERE(pxTCB->xCoreID) && pxTCB->uxPriority > pxCurrentTCB[ xPortGetCoreID() ]->uxPriority ) + if( prvCheckForYield( pxTCB, xPortGetCoreID(), pdFALSE ) ) { /* The notified task has a priority above the currently * executing task so a yield is required. */ - portYIELD_WITHIN_API(); - } - else if ( pxTCB->xCoreID != xPortGetCoreID() ) - { - taskYIELD_OTHER_CORE(pxTCB->xCoreID, pxTCB->uxPriority); + taskYIELD_IF_USING_PREEMPTION(); } else { @@ -5811,7 +5894,7 @@ TickType_t uxTaskResetEventItemValue( void ) mtCOVERAGE_TEST_MARKER(); } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); return xReturn; } @@ -5855,7 +5938,7 @@ TickType_t uxTaskResetEventItemValue( void ) pxTCB = xTaskToNotify; - taskENTER_CRITICAL_ISR(); + taskENTER_CRITICAL_ISR( &xKernelLock ); { if( pulPreviousNotificationValue != NULL ) { @@ -5929,7 +6012,7 @@ TickType_t uxTaskResetEventItemValue( void ) vListInsertEnd( &( xPendingReadyList[xPortGetCoreID()] ), &( pxTCB->xEventListItem ) ); } - if( tskCAN_RUN_HERE(pxTCB->xCoreID) && pxTCB->uxPriority > pxCurrentTCB[ xPortGetCoreID() ]->uxPriority ) + if( prvCheckForYield( pxTCB, xPortGetCoreID(), pdFALSE ) ) { /* The notified task has a priority above the currently * executing task so a yield is required. */ @@ -5937,10 +6020,11 @@ TickType_t uxTaskResetEventItemValue( void ) { *pxHigherPriorityTaskWoken = pdTRUE; } - } - else if ( pxTCB->xCoreID != xPortGetCoreID() ) - { - taskYIELD_OTHER_CORE( pxTCB->xCoreID, pxTCB->uxPriority ); + + /* Mark that a yield is pending in case the user is not + * using the "xHigherPriorityTaskWoken" parameter to an ISR + * safe FreeRTOS function. */ + xYieldPending[ xPortGetCoreID() ] = pdTRUE; } else { @@ -5948,7 +6032,7 @@ TickType_t uxTaskResetEventItemValue( void ) } } } - taskEXIT_CRITICAL_ISR(); + taskEXIT_CRITICAL_ISR( &xKernelLock ); return xReturn; } @@ -5989,7 +6073,7 @@ TickType_t uxTaskResetEventItemValue( void ) pxTCB = xTaskToNotify; - taskENTER_CRITICAL_ISR(); + taskENTER_CRITICAL_ISR( &xKernelLock ); { ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ]; pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED; @@ -6019,7 +6103,7 @@ TickType_t uxTaskResetEventItemValue( void ) vListInsertEnd( &( xPendingReadyList[xPortGetCoreID()] ), &( pxTCB->xEventListItem ) ); } - if( tskCAN_RUN_HERE(pxTCB->xCoreID) && pxTCB->uxPriority > pxCurrentTCB[ xPortGetCoreID() ]->uxPriority ) + if( prvCheckForYield( pxTCB, xPortGetCoreID(), pdFALSE ) ) { /* The notified task has a priority above the currently * executing task so a yield is required. */ @@ -6027,10 +6111,11 @@ TickType_t uxTaskResetEventItemValue( void ) { *pxHigherPriorityTaskWoken = pdTRUE; } - } - else if ( pxTCB->xCoreID != xPortGetCoreID() ) - { - taskYIELD_OTHER_CORE( pxTCB->xCoreID, pxTCB->uxPriority ); + + /* Mark that a yield is pending in case the user is not + * using the "xHigherPriorityTaskWoken" parameter in an ISR + * safe FreeRTOS function. */ + xYieldPending[ xPortGetCoreID() ] = pdTRUE; } else { @@ -6038,7 +6123,7 @@ TickType_t uxTaskResetEventItemValue( void ) } } } - taskEXIT_CRITICAL_ISR(); + taskEXIT_CRITICAL_ISR( &xKernelLock ); } #endif /* configUSE_TASK_NOTIFICATIONS */ @@ -6058,7 +6143,7 @@ TickType_t uxTaskResetEventItemValue( void ) * its notification state cleared. */ pxTCB = prvGetTCBFromHandle( xTask ); - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); { if( pxTCB->ucNotifyState[ uxIndexToClear ] == taskNOTIFICATION_RECEIVED ) { @@ -6070,7 +6155,7 @@ TickType_t uxTaskResetEventItemValue( void ) xReturn = pdFAIL; } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); return xReturn; } @@ -6091,14 +6176,14 @@ TickType_t uxTaskResetEventItemValue( void ) * its notification state cleared. */ pxTCB = prvGetTCBFromHandle( xTask ); - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); { /* Return the notification as it was before the bits were cleared, * then clear the bit mask. */ ulReturn = pxTCB->ulNotifiedValue[ uxIndexToClear ]; pxTCB->ulNotifiedValue[ uxIndexToClear ] &= ~ulBitsToClear; } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); return ulReturn; } @@ -6110,9 +6195,9 @@ TickType_t uxTaskResetEventItemValue( void ) uint32_t ulTaskGetIdleRunTimeCounter( void ) { - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xKernelLock ); tskTCB *pxTCB = (tskTCB *)xIdleTaskHandle[xPortGetCoreID()]; - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xKernelLock ); return pxTCB->ulRunTimeCounter; } @@ -6120,34 +6205,39 @@ TickType_t uxTaskResetEventItemValue( void ) #endif /*-----------------------------------------------------------*/ -static void prvAddCurrentTaskToDelayedList( const portBASE_TYPE xCoreID, const TickType_t xTicksToWait ) +static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, + const BaseType_t xCanBlockIndefinitely ) { TickType_t xTimeToWake; const TickType_t xConstTickCount = xTickCount; + BaseType_t xCurCoreID = xPortGetCoreID(); - if (configNUM_CORES > 1 && listIS_CONTAINED_WITHIN(&xTasksWaitingTermination, &( pxCurrentTCB[xCoreID]->xStateListItem))) { - /* vTaskDelete() has been called to delete this task. This would have happened from the other core while this task was spinning on xTaskQueueMutex, - so don't move the running task to the delayed list - as soon as this core re-enables interrupts this task will - be suspended permanently */ - return; - } + #if ( configNUM_CORES > 1 ) + if( listIS_CONTAINED_WITHIN( &xTasksWaitingTermination, &( pxCurrentTCB[ xCurCoreID ]->xStateListItem ) ) == pdTRUE ) + { + /* vTaskDelete() has been called to delete this task. This would have happened from the other core while this task was spinning on xTaskQueueMutex, + so don't move the running task to the delayed list - as soon as this core re-enables interrupts this task will + be suspended permanently. Todo: IDF-5844. */ + return; + } + #endif #if ( INCLUDE_xTaskAbortDelay == 1 ) { /* About to enter a delayed list, so ensure the ucDelayAborted flag is * reset to pdFALSE so it can be detected as having been set to pdTRUE * when the task leaves the Blocked state. */ - pxCurrentTCB[xCoreID]->ucDelayAborted = pdFALSE; + pxCurrentTCB[ xCurCoreID ]->ucDelayAborted = pdFALSE; } #endif /* Remove the task from the ready list before adding it to the blocked list * as the same list item is used for both lists. */ - if( uxListRemove( &( pxCurrentTCB[xCoreID]->xStateListItem ) ) == ( UBaseType_t ) 0 ) + if( uxListRemove( &( pxCurrentTCB[ xCurCoreID ]->xStateListItem ) ) == ( UBaseType_t ) 0 ) { /* The current task must be in a ready list, so there is no need to * check, and the port reset macro can be called directly. */ - portRESET_READY_PRIORITY( pxCurrentTCB[xCoreID]->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB[xPortGetCoreID()] cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */ + portRESET_READY_PRIORITY( pxCurrentTCB[ xCurCoreID ]->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */ } else { @@ -6156,12 +6246,12 @@ static void prvAddCurrentTaskToDelayedList( const portBASE_TYPE xCoreID, const T #if ( INCLUDE_vTaskSuspend == 1 ) { - if( ( xTicksToWait == portMAX_DELAY ) ) + if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) { /* Add the task to the suspended task list instead of a delayed task * list to ensure it is not woken by a timing event. It will block * indefinitely. */ - vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB[xCoreID]->xStateListItem ) ); + vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB[ xCurCoreID ]->xStateListItem ) ); } else { @@ -6171,19 +6261,19 @@ static void prvAddCurrentTaskToDelayedList( const portBASE_TYPE xCoreID, const T xTimeToWake = xConstTickCount + xTicksToWait; /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB[xCoreID]->xStateListItem ), xTimeToWake ); + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB[ xCurCoreID ]->xStateListItem ), xTimeToWake ); if( xTimeToWake < xConstTickCount ) { /* Wake time has overflowed. Place this item in the overflow * list. */ - vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB[xCoreID]->xStateListItem ) ); + vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB[ xCurCoreID ]->xStateListItem ) ); } else { /* The wake time has not overflowed, so the current block list * is used. */ - vListInsert( pxDelayedTaskList, &( pxCurrentTCB[xCoreID]->xStateListItem ) ); + vListInsert( pxDelayedTaskList, &( pxCurrentTCB[ xCurCoreID ]->xStateListItem ) ); /* If the task entering the blocked state was placed at the * head of the list of blocked tasks then xNextTaskUnblockTime @@ -6207,17 +6297,17 @@ static void prvAddCurrentTaskToDelayedList( const portBASE_TYPE xCoreID, const T xTimeToWake = xConstTickCount + xTicksToWait; /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB[xCoreID]->xStateListItem ), xTimeToWake ); + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB[ xCurCoreID ]->xStateListItem ), xTimeToWake ); if( xTimeToWake < xConstTickCount ) { /* Wake time has overflowed. Place this item in the overflow list. */ - vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB[xCoreID]->xStateListItem ) ); + vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB[ xCurCoreID ]->xStateListItem ) ); } else { /* The wake time has not overflowed, so the current block list is used. */ - vListInsert( pxDelayedTaskList, &( pxCurrentTCB[xCoreID]->xStateListItem ) ); + vListInsert( pxDelayedTaskList, &( pxCurrentTCB[ xCurCoreID ]->xStateListItem ) ); /* If the task entering the blocked state was placed at the head of the * list of blocked tasks then xNextTaskUnblockTime needs to be updated @@ -6231,6 +6321,9 @@ static void prvAddCurrentTaskToDelayedList( const portBASE_TYPE xCoreID, const T mtCOVERAGE_TEST_MARKER(); } } + + /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ + ( void ) xCanBlockIndefinitely; } #endif /* INCLUDE_vTaskSuspend */ } diff --git a/components/freertos/FreeRTOS-Kernel/timers.c b/components/freertos/FreeRTOS-Kernel/timers.c index 1356f7853f..4baf423a0e 100644 --- a/components/freertos/FreeRTOS-Kernel/timers.c +++ b/components/freertos/FreeRTOS-Kernel/timers.c @@ -48,18 +48,6 @@ #error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available. #endif -#ifdef ESP_PLATFORM -#define taskCRITICAL_MUX &xTimerMux -#undef taskENTER_CRITICAL -#undef taskEXIT_CRITICAL -#undef taskENTER_CRITICAL_ISR -#undef taskEXIT_CRITICAL_ISR -#define taskENTER_CRITICAL( ) portENTER_CRITICAL( taskCRITICAL_MUX ) -#define taskEXIT_CRITICAL( ) portEXIT_CRITICAL( taskCRITICAL_MUX ) -#define taskENTER_CRITICAL_ISR( ) portENTER_CRITICAL_ISR( taskCRITICAL_MUX ) -#define taskEXIT_CRITICAL_ISR( ) portEXIT_CRITICAL_ISR( taskCRITICAL_MUX ) -#endif - /* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined * for the header files above, but not in this file, in order to generate the @@ -160,8 +148,9 @@ PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL; #ifdef ESP_PLATFORM -/* Mux. We use a single mux for all the timers for now. ToDo: maybe increase granularity here? */ -PRIVILEGED_DATA portMUX_TYPE xTimerMux = portMUX_INITIALIZER_UNLOCKED; +/* Spinlock required in SMP when accessing the timers. For now we use a single lock + * Todo: Each timer could possible have its own lock for increased granularity. */ +PRIVILEGED_DATA portMUX_TYPE xTimerLock = portMUX_INITIALIZER_UNLOCKED; #endif // ESP_PLATFORM /*lint -restore */ @@ -470,7 +459,7 @@ PRIVILEGED_DATA portMUX_TYPE xTimerMux = portMUX_INITIALIZER_UNLOCKED; Timer_t * pxTimer = xTimer; configASSERT( xTimer ); - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xTimerLock ); { if( uxAutoReload != pdFALSE ) { @@ -481,7 +470,7 @@ PRIVILEGED_DATA portMUX_TYPE xTimerMux = portMUX_INITIALIZER_UNLOCKED; pxTimer->ucStatus &= ~tmrSTATUS_IS_AUTORELOAD; } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xTimerLock ); } /*-----------------------------------------------------------*/ @@ -491,7 +480,7 @@ PRIVILEGED_DATA portMUX_TYPE xTimerMux = portMUX_INITIALIZER_UNLOCKED; UBaseType_t uxReturn; configASSERT( xTimer ); - taskENTER_CRITICAL( ); + taskENTER_CRITICAL( &xTimerLock ); { if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0 ) { @@ -504,7 +493,7 @@ PRIVILEGED_DATA portMUX_TYPE xTimerMux = portMUX_INITIALIZER_UNLOCKED; uxReturn = ( UBaseType_t ) pdTRUE; } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xTimerLock ); return uxReturn; } @@ -616,7 +605,7 @@ PRIVILEGED_DATA portMUX_TYPE xTimerMux = portMUX_INITIALIZER_UNLOCKED; BaseType_t xTimerListsWereSwitched; #ifdef ESP_PLATFORM - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xTimerLock ); #else vTaskSuspendAll(); #endif // ESP_PLATFORM @@ -634,7 +623,7 @@ PRIVILEGED_DATA portMUX_TYPE xTimerMux = portMUX_INITIALIZER_UNLOCKED; if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) { #ifdef ESP_PLATFORM - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xTimerLock ); #else ( void ) xTaskResumeAll(); #endif // ESP_PLATFORM @@ -658,7 +647,7 @@ PRIVILEGED_DATA portMUX_TYPE xTimerMux = portMUX_INITIALIZER_UNLOCKED; vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); #ifdef ESP_PLATFORM // IDF-3755 - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xTimerLock ); #else if( xTaskResumeAll() == pdFALSE ) #endif // ESP_PLATFORM @@ -680,7 +669,7 @@ PRIVILEGED_DATA portMUX_TYPE xTimerMux = portMUX_INITIALIZER_UNLOCKED; else { #ifdef ESP_PLATFORM // IDF-3755 - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xTimerLock ); #else ( void ) xTaskResumeAll(); #endif // ESP_PLATFORM @@ -999,7 +988,7 @@ PRIVILEGED_DATA portMUX_TYPE xTimerMux = portMUX_INITIALIZER_UNLOCKED; /* Check that the list from which active timers are referenced, and the * queue used to communicate with the timer service, have been * initialised. */ - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xTimerLock ); { if( xTimerQueue == NULL ) { @@ -1041,7 +1030,7 @@ PRIVILEGED_DATA portMUX_TYPE xTimerMux = portMUX_INITIALIZER_UNLOCKED; mtCOVERAGE_TEST_MARKER(); } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xTimerLock ); } /*-----------------------------------------------------------*/ @@ -1053,7 +1042,7 @@ PRIVILEGED_DATA portMUX_TYPE xTimerMux = portMUX_INITIALIZER_UNLOCKED; configASSERT( xTimer ); /* Is the timer in the list of active timers? */ - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xTimerLock ); { if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 ) { @@ -1064,7 +1053,7 @@ PRIVILEGED_DATA portMUX_TYPE xTimerMux = portMUX_INITIALIZER_UNLOCKED; xReturn = pdTRUE; } } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xTimerLock ); return xReturn; } /*lint !e818 Can't be pointer to const due to the typedef. */ @@ -1077,11 +1066,11 @@ PRIVILEGED_DATA portMUX_TYPE xTimerMux = portMUX_INITIALIZER_UNLOCKED; configASSERT( xTimer ); - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xTimerLock ); { pvReturn = pxTimer->pvTimerID; } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xTimerLock ); return pvReturn; } @@ -1094,11 +1083,11 @@ PRIVILEGED_DATA portMUX_TYPE xTimerMux = portMUX_INITIALIZER_UNLOCKED; configASSERT( xTimer ); - taskENTER_CRITICAL(); + taskENTER_CRITICAL( &xTimerLock ); { pxTimer->pvTimerID = pvNewID; } - taskEXIT_CRITICAL(); + taskEXIT_CRITICAL( &xTimerLock ); } /*-----------------------------------------------------------*/ diff --git a/components/freertos/Kconfig b/components/freertos/Kconfig index 7927e5cf75..8e578c9982 100644 --- a/components/freertos/Kconfig +++ b/components/freertos/Kconfig @@ -4,16 +4,24 @@ menu "FreeRTOS" # Upstream FreeRTOS configurations go here config FREERTOS_SMP - bool "Run the SMP FreeRTOS kernel instead (FEATURE UNDER DEVELOPMENT)" + bool "Run the Amazon SMP FreeRTOS kernel instead (FEATURE UNDER DEVELOPMENT)" default "n" help - This will cause the FreeRTOS component to compile with the SMP FreeRTOS kernel instead. - THIS FEATURE IS UNDER ACTIVE DEVELOPMENT, users use this at their own risk. + Amazon has released an SMP version of the FreeRTOS Kernel which can be found via the following link: + https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/smp + + IDF has added an experimental port of this SMP kernel located in + components/freertos/FreeRTOS-Kernel-SMP. Enabling this option will cause IDF to use the Amazon SMP + kernel. Note that THIS FEATURE IS UNDER ACTIVE DEVELOPMENT, users use this at their own risk. + + Leaving this option disabled will mean the IDF FreeRTOS kernel is used instead, which is located in: + components/freertos/FreeRTOS-Kernel. Both kernel versions are SMP capable, but differ in + their implementation and features. config FREERTOS_UNICORE # Todo: Replace with CONFIG_NUM_CORES (IDF-4986) bool "Run FreeRTOS only on first core" - default "y" if IDF_TARGET_ESP32S2 + default "y" if IDF_TARGET_ESP32S2 || IDF_TARGET_LINUX select ESP_SYSTEM_SINGLE_CORE_MODE help This version of FreeRTOS normally takes control of all cores of the CPU. Select this if you only want @@ -161,6 +169,7 @@ menu "FreeRTOS" config FREERTOS_TIMER_TASK_STACK_DEPTH int "configTIMER_TASK_STACK_DEPTH" range 1536 32768 + default 2053 if IDF_TARGET_LINUX default 2048 help Set the timer task's stack size (see configTIMER_TASK_STACK_DEPTH documentation for more details). diff --git a/components/freertos/esp_additions/include/freertos/FreeRTOSConfig.h b/components/freertos/esp_additions/include/freertos/FreeRTOSConfig.h index c9651b0b18..7d8e19f308 100644 --- a/components/freertos/esp_additions/include/freertos/FreeRTOSConfig.h +++ b/components/freertos/esp_additions/include/freertos/FreeRTOSConfig.h @@ -102,8 +102,17 @@ This file get's pulled into assembly sources. Therefore, some includes need to b #endif //configUSE_TICKLESS_IDLE #define configCPU_CLOCK_HZ (CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * 1000000) #define configTICK_RATE_HZ CONFIG_FREERTOS_HZ +#ifdef CONFIG_IDF_TARGET_LINUX +#define configMAX_PRIORITIES ( 7 ) // Default in upstream simulator +/* The stack allocated by FreeRTOS will be passed passed to a pthread. + pthread has a minimal stack size which currently is 16KB. + The rest is for additional structures of the POSIX/Linux port. + This is a magic number since PTHREAD_STACK_MIN seems to not be a constant. */ +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) (0x4000 + 40) / sizeof(portSTACK_TYPE) ) +#else #define configMAX_PRIORITIES ( 25 ) //This has impact on speed of search for highest priority #define configMINIMAL_STACK_SIZE ( 768 + configSTACK_OVERHEAD_TOTAL ) +#endif #define configUSE_TIME_SLICING 1 #define configUSE_16_BIT_TICKS 0 #define configIDLE_SHOULD_YIELD 0 @@ -123,9 +132,12 @@ This file get's pulled into assembly sources. Therefore, some includes need to b #define configMAX_TASK_NAME_LEN CONFIG_FREERTOS_MAX_TASK_NAME_LEN #define configNUM_THREAD_LOCAL_STORAGE_POINTERS CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS -#ifndef CONFIG_IDF_TARGET_LINUX #define configSTACK_DEPTH_TYPE uint32_t +#ifndef CONFIG_IDF_TARGET_LINUX #define configUSE_NEWLIB_REENTRANT 1 +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 +#else +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 // Default in upstream simulator #endif #if CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY #define configENABLE_BACKWARD_COMPATIBILITY 1 @@ -133,15 +145,18 @@ This file get's pulled into assembly sources. Therefore, some includes need to b #define configENABLE_BACKWARD_COMPATIBILITY 0 #endif #define configASSERT(a) assert(a) -#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 // ----------------------- Memory ------------------------- #define configSUPPORT_STATIC_ALLOCATION 1 #define configSUPPORT_DYNAMIC_ALLOCATION 1 +#ifdef CONFIG_IDF_TARGET_LINUX +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 65 * 1024 ) ) // Default in upstream simulator +#else //We define the heap to span all of the non-statically-allocated shared RAM. ToDo: Make sure there //is some space left for the app and main cpu when running outside of a thread. #define configTOTAL_HEAP_SIZE (&_heap_end - &_heap_start)//( ( size_t ) (64 * 1024) ) +#endif #define configAPPLICATION_ALLOCATED_HEAP 1 #define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 @@ -163,9 +178,13 @@ This file get's pulled into assembly sources. Therefore, some includes need to b #ifdef CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS #define configGENERATE_RUN_TIME_STATS 1 /* Used by vTaskGetRunTimeStats() */ #endif +#ifdef CONFIG_IDF_TARGET_LINUX +#define configUSE_TRACE_FACILITY 1 +#else #ifdef CONFIG_FREERTOS_USE_TRACE_FACILITY #define configUSE_TRACE_FACILITY 1 /* Used by uxTaskGetSystemState(), and other trace facility functions */ #endif +#endif #ifdef CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS #define configUSE_STATS_FORMATTING_FUNCTIONS 1 /* Used by vTaskList() */ #endif @@ -194,7 +213,6 @@ This file get's pulled into assembly sources. Therefore, some includes need to b #define INCLUDE_uxTaskPriorityGet 1 #define INCLUDE_vTaskDelete 1 #define INCLUDE_vTaskSuspend 1 -#define INCLUDE_xTaskDelayUntil 1 #define INCLUDE_vTaskDelay 1 #define INCLUDE_xTaskGetIdleTaskHandle 1 #define INCLUDE_xTaskAbortDelay 1 @@ -206,7 +224,13 @@ This file get's pulled into assembly sources. Therefore, some includes need to b #define INCLUDE_xTaskResumeFromISR 1 #define INCLUDE_xTimerPendFunctionCall 1 #define INCLUDE_xTaskGetSchedulerState 1 +#ifdef CONFIG_IDF_TARGET_LINUX +#define INCLUDE_xTaskGetCurrentTaskHandle 0 // not defined in POSIX simulator +#define INCLUDE_vTaskDelayUntil 1 +#else +#define INCLUDE_xTaskDelayUntil 1 #define INCLUDE_xTaskGetCurrentTaskHandle 1 +#endif //Unlisted #define INCLUDE_pxTaskGetStackStart 1 diff --git a/components/freertos/esp_additions/include/freertos/idf_additions.h b/components/freertos/esp_additions/include/freertos/idf_additions.h index 038deb950d..6523575c8d 100644 --- a/components/freertos/esp_additions/include/freertos/idf_additions.h +++ b/components/freertos/esp_additions/include/freertos/idf_additions.h @@ -7,6 +7,7 @@ #include "sdkconfig.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" +#include "idf_additions_inc.h" #if CONFIG_FREERTOS_SMP || __DOXYGEN__ @@ -141,3 +142,50 @@ BaseType_t xTaskGetAffinity( TaskHandle_t xTask ); #endif // CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS #endif // CONFIG_FREERTOS_SMP || __DOXYGEN__ + +#if ( INCLUDE_vTaskPrioritySet == 1 ) + +/** + * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Saves the current priority and current base priority of a task, then raises the tasks + * current and base priority to uxNewPriority if uxNewPriority is of a higher priority. + * Once a task's priority has been raised with this function, the priority can be restored + * by calling prvTaskPriorityRestore() + * - Note that this function differs from vTaskPrioritySet() as the task's current priority + * will be modified even if the task has already inherited a priority. + * - This function is intended for special circumstance where a task must be forced immediately + * to a higher priority. + * + * For configUSE_MUTEXES == 0: A context switch will occur before the function returns if the priority + * being set is higher than the currently executing task. + * + * @note This functions is private is only be called internally within various IDF components. + * Users should never call this function from their application. + * + * @note vTaskPrioritySet() should not be called while a task's priority is already raised via this function + * + * @param pxSavedPriority returns base and current priorities + * + * @param uxNewPriority The priority to which the task will be set. + */ +void prvTaskPriorityRaise( prvTaskSavedPriority_t * pxSavedPriority, UBaseType_t uxNewPriority ); + +/** + * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Restore a task's priority that was previously raised by prvTaskPriorityRaise(). + * + * For configUSE_MUTEXES == 0: A context switch will occur before the function returns if the priority + * being set is higher than the currently executing task. + * + * @note This functions is private is only be called internally within various IDF components. + * Users should never call this function from their application. + * + * @param pxSavedPriority previously saved base and current priorities that need to be restored + */ +void prvTaskPriorityRestore( prvTaskSavedPriority_t * pxSavedPriority ); + +#endif // ( INCLUDE_vTaskPrioritySet == 1) diff --git a/components/freertos/esp_additions/include/freertos/idf_additions_inc.h b/components/freertos/esp_additions/include/freertos/idf_additions_inc.h new file mode 100644 index 0000000000..25b0b6d9a4 --- /dev/null +++ b/components/freertos/esp_additions/include/freertos/idf_additions_inc.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +#ifndef FREERTOS_ADDITITIONS_INC_H_ +#define FREERTOS_ADDITITIONS_INC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sdkconfig.h" +#include "freertos/FreeRTOS.h" + +#if ( INCLUDE_vTaskPrioritySet == 1 ) + +typedef struct { + UBaseType_t uxPriority; +#if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxBasePriority; +#endif +} prvTaskSavedPriority_t; + +#endif // ( INCLUDE_vTaskPrioritySet == 1) + +#ifdef __cplusplus +} +#endif + +#endif //FREERTOS_ADDITITIONS_INC_H_ diff --git a/components/freertos/esp_additions/private_include/freertos_tasks_c_additions.h b/components/freertos/esp_additions/private_include/freertos_tasks_c_additions.h index f5ecdbb5a9..bc43cabdcd 100644 --- a/components/freertos/esp_additions/private_include/freertos_tasks_c_additions.h +++ b/components/freertos/esp_additions/private_include/freertos_tasks_c_additions.h @@ -7,6 +7,7 @@ #pragma once #include "sdkconfig.h" +#include "idf_additions_inc.h" /** * This file will be included in `tasks.c` file, thus, it must NOT be included @@ -393,3 +394,204 @@ void vTaskSetThreadLocalStoragePointerAndDelCallback( TaskHandle_t xTaskToSet, B #endif // CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS #endif // CONFIG_FREERTOS_SMP + +#if ( INCLUDE_vTaskPrioritySet == 1 ) + +void prvTaskPriorityRaise( prvTaskSavedPriority_t * pxSavedPriority, UBaseType_t uxNewPriority ) +{ + TCB_t * pxTCB; + UBaseType_t uxPriorityUsedOnEntry; + + configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) ); + + /* Ensure the new priority is valid. */ + if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) + { + uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; + } + +#if CONFIG_FREERTOS_SMP + taskENTER_CRITICAL(); +#else + taskENTER_CRITICAL( &xKernelLock ); +#endif + { + pxTCB = prvGetTCBFromHandle( NULL ); + + #if ( configUSE_MUTEXES == 1 ) + { + pxSavedPriority->uxPriority = pxTCB->uxPriority; + pxSavedPriority->uxBasePriority = pxTCB->uxBasePriority; + + /* If uxNewPriority < uxBasePriority, then there is nothing else to + * do, as uxBasePriority is always <= uxPriority. */ + if( uxNewPriority > pxTCB->uxBasePriority ) + { + pxTCB->uxBasePriority = uxNewPriority; + + /* Remember the task's current priority before attempting to + * change it. If the task's current priority is changed, it must + * be done so before moving the task between task lists) in order + * for the taskRESET_READY_PRIORITY() macro to function correctly. */ + uxPriorityUsedOnEntry = pxTCB->uxPriority; + + if( uxNewPriority > pxTCB->uxPriority ) + { + pxTCB->uxPriority = uxNewPriority; + + /* Only reset the event list item value if the value is not + * being used for anything else. */ + if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) + { + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + } + + /* If the task is in the blocked or suspended list we need do + * nothing more than change its priority variable. However, if + * the task is in a ready list it needs to be removed and placed + * in the list appropriate to its new priority. */ + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) + { + /* The task is currently in its ready list - remove before + * adding it to its new ready list. As we are in a critical + * section we can do this even if the scheduler is suspended. */ + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + /* It is known that the task is in its ready list so + * there is no need to check again and the port level + * reset macro can be called directly. */ + portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority ); + } + prvAddTaskToReadyList( pxTCB ); + } + } + } + } + #else /* if ( configUSE_MUTEXES == 1 ) */ + { + pxSavedPriority->uxPriority = pxTCB->uxPriority; + if ( uxNewPriority > pxTCB->uxPriority) + { + vTaskPrioritySet( NULL, uxNewPriority ); + } + } + #endif + } +#if CONFIG_FREERTOS_SMP + taskEXIT_CRITICAL(); +#else + taskEXIT_CRITICAL( &xKernelLock ); +#endif +} + +void prvTaskPriorityRestore( prvTaskSavedPriority_t * pxSavedPriority ) +{ + TCB_t * pxTCB; + UBaseType_t uxNewPriority; + UBaseType_t uxPriorityUsedOnEntry; + UBaseType_t uxBasePriorityUsedOnEntry; + BaseType_t xYieldRequired = pdFALSE; + +#if CONFIG_FREERTOS_SMP + taskENTER_CRITICAL(); +#else + taskENTER_CRITICAL( &xKernelLock ); +#endif + { + pxTCB = prvGetTCBFromHandle( NULL ); + + #if ( configUSE_MUTEXES == 1 ) + { + /* If the saved uxBasePriority == the task's uxBasePriority, it means + * that prvTaskPriorityRaise() never raised the task's uxBasePriority. + * In that case, there is nothing else to do. */ + if( pxSavedPriority->uxBasePriority != pxTCB->uxBasePriority ) + { + uxBasePriorityUsedOnEntry = pxTCB->uxBasePriority; + pxTCB->uxBasePriority = pxSavedPriority->uxBasePriority; + + /* Remember the task's current priority before attempting to + * change it. If the task's current priority is changed, it must + * be done so before moving the task between task lists in order + * for the taskRESET_READY_PRIORITY() macro to function correctly. */ + uxPriorityUsedOnEntry = pxTCB->uxPriority; + + /* Check if the task inherited a priority after prvTaskPriorityRaise(). + * If this is the case, there is nothing else to do. The priority + * will be restored when the task disinherits its priority. */ + if( pxTCB->uxPriority == uxBasePriorityUsedOnEntry ) + { + if( pxTCB->uxMutexesHeld == 0 ) + { + /* The task may have inherited a priority before prvTaskPriorityRaise() + * then disinherited a priority after prvTaskPriorityRaise(). + * Thus we need set the uxPriority to the saved base priority + * so that the task's priority gets restored to the priority + * before any inheritance or raising. */ + pxTCB->uxPriority = pxSavedPriority->uxBasePriority; + } + else + { + /* The task may have inherited a priority before prvTaskPriorityRaise() + * was called. Thus, we need to restore uxPriority to the + * "saved uxPriority" so that the task still retains that + * inherited priority. */ + pxTCB->uxPriority = pxSavedPriority->uxPriority; + } + uxNewPriority = pxTCB->uxPriority; + + if( uxNewPriority < uxPriorityUsedOnEntry ) + { + /* Setting the priority of the running task down means + * there may now be another task of higher priority that + * is ready to execute. */ + xYieldRequired = pdTRUE; + } + + /* Only reset the event list item value if the value is not + * being used for anything else. */ + if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) + { + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + } + + /* If the task is in the blocked or suspended list we need do + * nothing more than change its priority variable. However, if + * the task is in a ready list it needs to be removed and placed + * in the list appropriate to its new priority. */ + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) + { + /* The task is currently in its ready list - remove before + * adding it to its new ready list. As we are in a critical + * section we can do this even if the scheduler is suspended. */ + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + /* It is known that the task is in its ready list so + * there is no need to check again and the port level + * reset macro can be called directly. */ + portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority ); + } + prvAddTaskToReadyList( pxTCB ); + } + + if( xYieldRequired != pdFALSE ) + { + taskYIELD_IF_USING_PREEMPTION(); + } + } + } + } + #else /* if ( configUSE_MUTEXES == 1 ) */ + { + vTaskPrioritySet( NULL, pxSavedPriority->uxPriority ); + } + #endif + } +#if CONFIG_FREERTOS_SMP + taskEXIT_CRITICAL(); +#else + taskEXIT_CRITICAL( &xKernelLock ); +#endif +} + +#endif // ( INCLUDE_vTaskPrioritySet == 1 ) diff --git a/components/freertos/linker.lf b/components/freertos/linker.lf index 58fda61f49..1c27b25384 100644 --- a/components/freertos/linker.lf +++ b/components/freertos/linker.lf @@ -34,6 +34,8 @@ entries: tasks: vTaskRemoveFromUnorderedEventList (default) tasks: uxTaskPriorityGet (default) tasks: vTaskPrioritySet (default) + tasks: prvTaskPriorityRaise (default) + tasks: prvTaskPriorityRestore (default) tasks: vTaskSetThreadLocalStoragePointerAndDelCallback (default) tasks: pvTaskGetThreadLocalStoragePointer (default) tasks: xTaskGetCurrentTaskHandleForCPU (default) @@ -125,7 +127,14 @@ entries: queue: uxQueueGetQueueNumber (default) queue: vQueueSetQueueNumber (default) queue: ucQueueGetQueueType (default) - port_common:main_task (default) + # port.c Functions port: esp_startup_start_app (default) if ESP_SYSTEM_SINGLE_CORE_MODE = n: port: esp_startup_start_app_other_cores (default) + # port_common.c Functions + port_common:main_task (default) + port_common:esp_startup_start_app_common (default) + port_common:vApplicationGetIdleTaskMemory (default) + port_common:vApplicationGetTimerTaskMemory (default) + if FREERTOS_UNICORE = n: + port_common:other_cpu_startup_idle_hook_cb (default) diff --git a/components/freertos/linker_smp.lf b/components/freertos/linker_smp.lf index ff9ba77f55..01f7c5b211 100644 --- a/components/freertos/linker_smp.lf +++ b/components/freertos/linker_smp.lf @@ -76,6 +76,8 @@ entries: tasks: eTaskGetState (default) tasks: uxTaskPriorityGet (default) tasks: vTaskPrioritySet (default) + tasks: prvTaskPriorityRaise (default) + tasks: prvTaskPriorityRestore (default) tasks: vTaskSuspend (default) tasks: vTaskResume (default) tasks: prvCreateIdleTasks (default) diff --git a/components/freertos/test/CMakeLists.txt b/components/freertos/test/CMakeLists.txt index 6e81913af4..ac4364d633 100644 --- a/components/freertos/test/CMakeLists.txt +++ b/components/freertos/test/CMakeLists.txt @@ -1,4 +1,8 @@ -idf_component_register(SRC_DIRS integration/event_groups +# For refactored FreeRTOS unit tests, we need to support #include "xxx.h" of FreeRTOS headers +idf_component_get_property(FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH) + +idf_component_register(SRC_DIRS integration # For freertos_test_utils.c + integration/event_groups integration/queue integration/stream_buffer integration/tasks @@ -6,6 +10,6 @@ idf_component_register(SRC_DIRS integration/event_groups miscellaneous performance port - PRIV_INCLUDE_DIRS . + PRIV_INCLUDE_DIRS . ./integration "${FREERTOS_ORIG_INCLUDE_PATH}" PRIV_REQUIRES cmock test_utils esp_system driver esp_timer) target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/components/freertos/test/integration/README.md b/components/freertos/test/integration/README.md new file mode 100644 index 0000000000..6eabb0d7d8 --- /dev/null +++ b/components/freertos/test/integration/README.md @@ -0,0 +1,73 @@ +# FreeRTOS Tests Guidelines + +The FreeRTOS tests are currently being refactored/reorganized with the goal of being upstreamed. This document describes the set of guidelines to which the tests are refactored/reorganized according to. + +## Unity Port + +These test cases assume that the FreeRTOS port has also ported the [Unity Test Framework](https://github.com/ThrowTheSwitch/Unity). Because each FreeRTOS test case will require the scheduler to be started, the way that each test case is invoked will differ form regular Unity ports. + +Regular Unity ports will assume that the `main()` function invokes each test using the `RUN_TEST()` macro. However, these test cases assume the following about the Unity port: + +- Each test case is invoked from a `UnityTask` instead of `main()`. Thus each test case is run from the context of the `UnityTask`. + - The `UnityTask` is created using `xTaskCreate...()` (and pinned to core 0 if SMP) from the port's startup (i.e., `main()`) + - The port's startup (i.e., `main()`) should also start the scheduler using `vTaskStartScheduler()` + - Note that this is similar to the startup of most FreeRTOS Demos. +- Each test case is defined using the `TEST_CASE(name, ...)` macro. The `VA_ARGS` of the macro allows each port to specify a set of extra arguments (such as test case labels/tags) to be used into their CI pipelines. +- A `portTestMacro.h` must be provided by each port. This header will contain + - Some constants used by test cases such as default task stack sizes (e.g., `configTEST_DEFAULT_STACK_SIZE`) + - Some port implementation specific functions/macros required by test cases such as getting current system time (e.g., `portTEST_GET_TIME()`). + +## Test Organization + +- Test cases are grouped into sub-directories roughly matching the header files of FreeRTOS (e.g., task, queue, semaphore, event groups etc). +- Each source file should ideally test a particular behavior (e.g., priority scheduling, queue send, scheduler suspend). This should usually result in one test case per behavior, thus one test case per source file +- Some test case behaviors may depend on configuration (e.g., priority scheduling in single core vs SMP). In such cases + - If the affect is small, use an `#if (config... == 1)` to wrap the affected areas + - If the affect is large, write a separate test case in a separate source file and wrap the entire test case with `#if (config... == 1)`. + +## Test Case Template + +Each test case should have the following: + +- Test case description describing + - Purpose of the test case + - Test case procedure + - Excepted outcome/behavior of the test case +- The test case code wrapped in its required `config...` macros +- The expected outcomes should be tested using the `TEST_ASSERT_...()` macros provided by unity + +```c +// In test_priority_scheduling.c + +/* +Test Priority Scheduling (Single Core) + +Purpose: + - Test that the single-core scheduler always schedules the highest priority ready task +Procedure: + - Raise the unityTask priority to (configMAX_PRIORITIES - 1) + - unityTask creates the following lower priority tasks + - task_A (configMAX_PRIORITIES - 2) + - task_B (configMAX_PRIORITIES - 3) + - UnityTask blocks for a short period of time to allow task_A to run + - Clean up and restore unityTask's original priority +Expected: + - task_A should run after unityTask blocks + - task_B should never have run +*/ +#if ( configNUM_CORES == 1 ) + +static BaseType_t test_static_var = 0; + +static void test_static_func(void) +{ + ... +} + +TEST_CASE("Tasks: Priority scheduling single core", "[freertos]") +{ + ... +} + +#endif /* configNUM_CORES == 1 */ +``` diff --git a/components/freertos/test/integration/event_groups/test_freertos_eventgroups.c b/components/freertos/test/integration/event_groups/test_freertos_eventgroups.c index a4521ec91e..e0a9e8c9e6 100644 --- a/components/freertos/test/integration/event_groups/test_freertos_eventgroups.c +++ b/components/freertos/test/integration/event_groups/test_freertos_eventgroups.c @@ -15,11 +15,13 @@ #include "unity.h" #include "unity_test_utils.h" -#define BIT_CALL (1 << 0) -#define BIT_RESPONSE(TASK) (1 << (TASK+1)) -#define ALL_RESPONSE_BITS (((1 << NUM_TASKS) - 1) << 1) +#define NUM_TASKS 8 +#define ALL_TASK_BITS ((1 << NUM_TASKS) - 1) +#define BIT_CALL(task) (1 << (task)) +#define BIT_RESPONSE(task) (1 << ((task) + NUM_TASKS)) +#define ALL_CALL_BITS (ALL_TASK_BITS) +#define ALL_RESPONSE_BITS (ALL_TASK_BITS << NUM_TASKS) -static const int NUM_TASKS = 8; static const int COUNT = 1000; static EventGroupHandle_t eg; static SemaphoreHandle_t done_sem; @@ -33,7 +35,7 @@ static void task_event_group_call_response(void *param) for (int i = 0; i < COUNT; i++) { /* Wait until the common "call" bit is set, starts off all tasks (clear on return) */ - TEST_ASSERT( xEventGroupWaitBits(eg, BIT_CALL, true, false, portMAX_DELAY) ); + TEST_ASSERT( xEventGroupWaitBits(eg, BIT_CALL(task_num), true, false, portMAX_DELAY) ); /* Set our individual "response" bit */ xEventGroupSetBits(eg, BIT_RESPONSE(task_num)); @@ -55,20 +57,20 @@ TEST_CASE("FreeRTOS Event Groups", "[freertos]") /* Note: task_event_group_call_response all have higher priority than this task, so on this core they will always preempt this task. - This is important because we need to know all tasks have blocked on BIT_CALL each time we signal it, - or they get out of sync. + This is important because we need to know all tasks have blocked on their own BIT_CALL(task_num) each time we + signal it, or they get out of sync. */ for (int c = 0; c < NUM_TASKS; c++) { xTaskCreatePinnedToCore(task_event_group_call_response, "tsk_call_resp", 4096, (void *)c, configMAX_PRIORITIES - 1, &task_handles[c], c % portNUM_PROCESSORS); } /* Tasks all start instantly, but this task will resume running at the same time as the higher priority tasks on the - other processor may still be setting up, so allow time for them to also block on BIT_CALL... */ + other processor may still be setting up, so allow time for them to also block on BIT_CALL()... */ vTaskDelay(10); for (int i = 0; i < COUNT; i++) { - /* signal all tasks with "CALL" bit... */ - xEventGroupSetBits(eg, BIT_CALL); + /* signal all the "CALL" bits of each task */ + xEventGroupSetBits(eg, ALL_CALL_BITS); /* Wait until all tasks have set their respective response bits */ TEST_ASSERT_EQUAL_HEX16(ALL_RESPONSE_BITS, xEventGroupWaitBits(eg, ALL_RESPONSE_BITS, true, true, portMAX_DELAY)); @@ -87,8 +89,6 @@ TEST_CASE("FreeRTOS Event Groups", "[freertos]") vEventGroupDelete(eg); } -#define BIT_DONE(X) (1<<(NUM_TASKS+1+X)) - static void task_test_sync(void *param) { int task_num = (int)param; @@ -97,11 +97,11 @@ static void task_test_sync(void *param) for (int i = 0; i < COUNT; i++) { /* set our bit, and wait on all tasks to set their bits */ - xEventGroupSync(eg, BIT_RESPONSE(task_num), ALL_RESPONSE_BITS, portMAX_DELAY); + xEventGroupSync(eg, BIT_CALL(task_num), ALL_CALL_BITS, portMAX_DELAY); /* clear our bit */ - xEventGroupClearBits(eg, BIT_RESPONSE(task_num)); + xEventGroupClearBits(eg, BIT_CALL(task_num)); } - int after_done = xEventGroupSetBits(eg, BIT_DONE(task_num)); + int after_done = xEventGroupSetBits(eg, BIT_RESPONSE(task_num)); printf("Done %d = 0x%08x\n", task_num, after_done); @@ -119,8 +119,8 @@ TEST_CASE("FreeRTOS Event Group Sync", "[freertos]") } for (int c = 0; c < NUM_TASKS; c++) { - printf("Waiting on %d (0x%08x)\n", c, BIT_DONE(c)); - TEST_ASSERT( xEventGroupWaitBits(eg, BIT_DONE(c), false, false, portMAX_DELAY) ); + printf("Waiting on %d (0x%08x)\n", c, BIT_RESPONSE(c)); + TEST_ASSERT( xEventGroupWaitBits(eg, BIT_RESPONSE(c), false, false, portMAX_DELAY) ); } /* Ensure all tasks cleaned up correctly */ diff --git a/components/freertos/test/integration/freertos_test_utils.c b/components/freertos/test/integration/freertos_test_utils.c new file mode 100644 index 0000000000..80ba37c788 --- /dev/null +++ b/components/freertos/test/integration/freertos_test_utils.c @@ -0,0 +1,72 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "FreeRTOS.h" +#include "semphr.h" +#include "freertos_test_utils.h" + +#if ( configNUM_CORES > 1 ) + + typedef struct { + const TestFunction_t pxTestCode; + void * const pvTestCodeArg; + const SemaphoreHandle_t xTaskDoneSem; + } TestArgs_t; + + static void test_func_task( void * pvParameters ) + { + TestArgs_t * pxTestArgs = ( TestArgs_t * ) pvParameters; + /* Call the test function */ + pxTestArgs->pxTestCode( pxTestArgs->pvTestCodeArg ); + /* Indicate completion to the creation task and wait to be deleted. */ + xSemaphoreGive( pxTestArgs->xTaskDoneSem ); + vTaskSuspend( NULL ); + } + + void vTestOnAllCores( TestFunction_t pxTestCode, void * pvTestCodeArg, uint32_t ulStackDepth, UBaseType_t uxPriority ) + { + SemaphoreHandle_t xTaskDoneSem = xSemaphoreCreateCounting( configNUM_CORES, 0 ); + TaskHandle_t xTaskHandles[ configNUM_CORES ]; + TestArgs_t xTestArgs = { + .pxTestCode = pxTestCode, + .pvTestCodeArg = pvTestCodeArg, + .xTaskDoneSem = xTaskDoneSem, + }; + + /* Create a separate task on each core to run the test function */ + for( BaseType_t xCoreID = 0; xCoreID < configNUM_CORES; xCoreID++ ) { + #if ( CONFIG_FREERTOS_SMP == 1 ) + xTaskCreateAffinitySet( test_func_task, + "task", + ulStackDepth, + ( void * ) &xTestArgs, + uxPriority, + ( UBaseType_t ) ( 1 << xCoreID ), + &( xTaskHandles[ xCoreID ] ) ); + #else + xTaskCreatePinnedToCore( test_func_task, + "task", + ulStackDepth, + ( void * ) &xTestArgs, + uxPriority, + &( xTaskHandles[ xCoreID ] ), + xCoreID ); + #endif + } + + /* Wait for each tasks to complete test */ + for( BaseType_t xCoreID = 0; xCoreID < configNUM_CORES; xCoreID++ ) { + xSemaphoreTake( xTaskDoneSem, portMAX_DELAY ); + } + + /* Cleanup */ + for( BaseType_t xCoreID = 0; xCoreID < configNUM_CORES; xCoreID++ ) { + vTaskDelete( xTaskHandles[ xCoreID ] ); + } + vSemaphoreDelete( xTaskDoneSem ); + } + +#endif /* ( configNUM_CORES > 1 ) */ diff --git a/components/freertos/test/integration/freertos_test_utils.h b/components/freertos/test/integration/freertos_test_utils.h new file mode 100644 index 0000000000..fee7259d21 --- /dev/null +++ b/components/freertos/test/integration/freertos_test_utils.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "FreeRTOS.h" + +#if ( configNUM_CORES > 1 ) + + /** + * @brief Prototype for test function. + * + * A test function can be passed to vTestOnAllCores() which will run the test function from a task on each core. + */ + typedef void (* TestFunction_t)( void * ); + + /** + * @brief Run a test function on each core + * + * This function will internally create a task pinned to each core, where each task will call the provided test + * function. This function will block until all cores finish executing the test function. + * + * @param pxTestCode Test function + * @param pvTestCodeArg Argument provided to test function + * @param ulStackDepth Stack depth of the created tasks + * @param uxPriority Priority of the created tasks + */ + void vTestOnAllCores( TestFunction_t pxTestCode, void * pvTestCodeArg, uint32_t ulStackDepth, UBaseType_t uxPriority ); + +#endif /* ( configNUM_CORES > 1 ) */ diff --git a/components/freertos/test/integration/portTestMacro.h b/components/freertos/test/integration/portTestMacro.h new file mode 100644 index 0000000000..f46a2048aa --- /dev/null +++ b/components/freertos/test/integration/portTestMacro.h @@ -0,0 +1,16 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "test_utils.h" + +#define configTEST_DEFAULT_STACK_SIZE 4096 +#define configTEST_UNITY_TASK_PRIORITY UNITY_FREERTOS_PRIORITY + +#define portTEST_REF_CLOCK_TYPE uint32_t +#define portTEST_REF_CLOCK_INIT() ref_clock_init() +#define portTEST_REF_CLOCK_DEINIT() ref_clock_deinit() +#define portTEST_REF_CLOCK_GET_TIME() ((uint32_t) ref_clock_get()) +#define portTEST_TICKS_TO_REF_CLOCK(ticks) ((ticks) * (1000000/configTICK_RATE_HZ)) diff --git a/components/freertos/test/integration/tasks/test_freertos_task_delay_until.c b/components/freertos/test/integration/tasks/test_freertos_task_delay_until.c deleted file mode 100644 index 921427e8ea..0000000000 --- a/components/freertos/test/integration/tasks/test_freertos_task_delay_until.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - Test for FreeRTOS vTaskDelayUntil() function by comparing the delay period of - the function to comparing it to ref clock. -*/ - -#include -#include -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "freertos/semphr.h" -#include "unity.h" -#include "test_utils.h" - -#define TSK_PRIORITY (UNITY_FREERTOS_PRIORITY + 1) - -#define NO_OF_CYCLES 5 -#define NO_OF_TASKS_PER_CORE 2 -#define TICKS_TO_DELAY 10 -#define TICK_RATE configTICK_RATE_HZ -#define TICK_PERIOD_US (1000000/TICK_RATE) -#define IDEAL_DELAY_PERIOD_MS ((1000*TICKS_TO_DELAY)/TICK_RATE) -#define IDEAL_DELAY_PERIOD_US (IDEAL_DELAY_PERIOD_MS*1000) - -#define TICKS_TO_MS(x) (((x)*1000)/TICK_RATE) -#define REF_TO_ROUND_MS(x) (((x)+500)/1000) - -static SemaphoreHandle_t task_delete_semphr; - -static void delaying_task(void* arg) -{ - uint64_t ref_prev, ref_current; - TickType_t last_wake_time; - TickType_t ticks_before_delay; - - vTaskDelay(1); //Delay until next tick to synchronize operations to tick boundaries - - last_wake_time = xTaskGetTickCount(); - ticks_before_delay = last_wake_time; - ref_prev = ref_clock_get(); - - for(int i = 0; i < NO_OF_CYCLES; i++){ - //Delay of TICKS_TO_DELAY - vTaskDelayUntil(&last_wake_time, TICKS_TO_DELAY); - //Get current ref clock - TEST_ASSERT_EQUAL(IDEAL_DELAY_PERIOD_MS, TICKS_TO_MS(xTaskGetTickCount() - ticks_before_delay)); - ref_current = ref_clock_get(); - TEST_ASSERT_UINT32_WITHIN(TICK_PERIOD_US, IDEAL_DELAY_PERIOD_US, (uint32_t)(ref_current - ref_prev)); - ref_prev = ref_current; - ticks_before_delay = last_wake_time; - } - - //Delete Task after prescribed number of cycles - xSemaphoreGive(task_delete_semphr); - vTaskDelete(NULL); -} - -TEST_CASE("Test vTaskDelayUntil", "[freertos]") -{ - task_delete_semphr = xQueueCreateCountingSemaphore(NO_OF_TASKS_PER_CORE*portNUM_PROCESSORS, 0); - ref_clock_init(); - - for(int i = 0; i < portNUM_PROCESSORS; i++){ - xTaskCreatePinnedToCore(delaying_task, "delay_pinned", 1024, NULL, TSK_PRIORITY, NULL, i); - xTaskCreatePinnedToCore(delaying_task, "delay_no_aff", 1024, NULL, TSK_PRIORITY, NULL, tskNO_AFFINITY); - } - - for(int i = 0; i < NO_OF_TASKS_PER_CORE*portNUM_PROCESSORS; i++){ - xSemaphoreTake(task_delete_semphr, portMAX_DELAY); - } - //Cleanup - vSemaphoreDelete(task_delete_semphr); - ref_clock_deinit(); -} diff --git a/components/freertos/test/integration/tasks/test_priority_scheduling.c b/components/freertos/test/integration/tasks/test_priority_scheduling.c new file mode 100644 index 0000000000..a9b7e76fa8 --- /dev/null +++ b/components/freertos/test/integration/tasks/test_priority_scheduling.c @@ -0,0 +1,82 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "FreeRTOS.h" +#include "task.h" +#include "unity.h" +#include "portTestMacro.h" + +/* ------------------------------------------------------------------------------------------------------------------ */ + +/* +Test Priority Scheduling (Single Core) + +Purpose: + - Test that the single-core scheduler always schedules the highest priority ready task +Procedure: + - Raise the unityTask priority to (configMAX_PRIORITIES - 1) + - unityTask creates the following lower priority tasks + - task_A (configMAX_PRIORITIES - 2) + - task_B (configMAX_PRIORITIES - 3) + - UnityTask blocks for a short period of time to allow task_A to run + - Clean up and restore unityTask's original priority +Expected: + - task_A should run after unityTask blocks + - task_B should never have run +*/ + +#if ( configNUM_CORES == 1 ) + +#define UNITY_TASK_DELAY_TICKS 10 + +static BaseType_t task_A_ran; +static BaseType_t task_B_ran; + +static void task_A(void *arg) +{ + task_A_ran = pdTRUE; + /* Keeping spinning to prevent the lower priority task_B from running */ + while (1) { + ; + } +} + +static void task_B(void *arg) +{ + /* The following should never run due to task_B having a lower priority */ + task_B_ran = pdTRUE; + while (1) { + ; + } +} + +TEST_CASE("Tasks: Test priority scheduling", "[freertos]") +{ + TaskHandle_t task_A_handle; + TaskHandle_t task_B_handle; + task_A_ran = pdFALSE; + task_B_ran = pdFALSE; + + /* Raise the priority of the unityTask */ + vTaskPrioritySet(NULL, configMAX_PRIORITIES - 1); + /* Create task_A and task_B */ + xTaskCreate(task_A, "task_A", configTEST_DEFAULT_STACK_SIZE, (void *)xTaskGetCurrentTaskHandle(), configMAX_PRIORITIES - 2, &task_A_handle); + xTaskCreate(task_B, "task_B", configTEST_DEFAULT_STACK_SIZE, (void *)xTaskGetCurrentTaskHandle(), configMAX_PRIORITIES - 3, &task_B_handle); + + /* Block to allow task_A to be scheduled */ + vTaskDelay(UNITY_TASK_DELAY_TICKS); + + /* Test that only task_A has run */ + TEST_ASSERT_EQUAL(pdTRUE, task_A_ran); + TEST_ASSERT_EQUAL(pdFALSE, task_B_ran); + + vTaskDelete(task_A_handle); + vTaskDelete(task_B_handle); + /* Restore the priority of the unityTask */ + vTaskPrioritySet(NULL, configTEST_UNITY_TASK_PRIORITY); +} + +#endif /* configNUM_CORES == 1 */ diff --git a/components/freertos/test/integration/tasks/test_priority_scheduling_smp.c b/components/freertos/test/integration/tasks/test_priority_scheduling_smp.c new file mode 100644 index 0000000000..2f4b0cad9a --- /dev/null +++ b/components/freertos/test/integration/tasks/test_priority_scheduling_smp.c @@ -0,0 +1,102 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" +#include "unity.h" +#include "portTestMacro.h" + +/* ------------------------------------------------------------------------------------------------------------------ */ + +/* +Test Priority Scheduling SMP + +Purpose: + - Test that the SMP scheduler always schedules the highest priority ready tasks for each core +Procedure: + - Raise the unityTask priority to (configMAX_PRIORITIES - 1) + - unityTask creates the following lower priority tasks for each core + - task_A (configMAX_PRIORITIES - 2) for each core + - task_B (configMAX_PRIORITIES - 3) for each core + - unityTask blocks for a short period of time to allow all of the task_As to run + - Clean up and restore unityTask's original priority +Expected: + - All of the task_As should be run by the scheduler + - None of the task_Bs should have run +*/ + +#if ( defined( CONFIG_FREERTOS_SMP ) && ( configNUM_CORES > 1 ) && ( configRUN_MULTIPLE_PRIORITIES == 1 ) ) \ + || ( !defined( CONFIG_FREERTOS_SMP ) && ( configNUM_CORES > 1 ) ) + +#define UNITY_TASK_DELAY_TICKS 10 + +static BaseType_t task_A_ran[configNUM_CORES]; +static BaseType_t task_B_ran[configNUM_CORES]; + +static void task_A(void *arg) +{ + BaseType_t task_idx = (BaseType_t) arg; + task_A_ran[task_idx] = pdTRUE; + /* Keeping spinning to prevent the lower priority task_B from running */ + while (1) { + ; + } +} + +static void task_B(void *arg) +{ + /* The following should never be run due to task_B having a lower priority */ + BaseType_t task_idx = (BaseType_t) arg; + task_B_ran[task_idx] = pdTRUE; + while (1) { + ; + } +} + +TEST_CASE("Tasks: Test priority scheduling (SMP)", "[freertos]") +{ + TaskHandle_t task_A_handles[configNUM_CORES]; + TaskHandle_t task_B_handles[configNUM_CORES]; + memset(task_A_ran, pdFALSE, sizeof(task_A_ran)); + memset(task_B_ran, pdFALSE, sizeof(task_B_ran)); + + /* Raise the priority of the unityTask */ + vTaskPrioritySet(NULL, configMAX_PRIORITIES - 1); + + /* Create task_A for each core */ + for (UBaseType_t x = 0; x < configNUM_CORES; x++) { + xTaskCreate(task_A, "task_A", configTEST_DEFAULT_STACK_SIZE, (void *)x, configMAX_PRIORITIES - 2, &task_A_handles[x]); + } + + /* Create task_B for each core */ + for (UBaseType_t x = 0; x < configNUM_CORES; x++) { + xTaskCreate(task_B, "task_B", configTEST_DEFAULT_STACK_SIZE, (void *)x, configMAX_PRIORITIES - 3, &task_B_handles[x]); + } + + /* Block to ensure all the task_As to be scheduled */ + vTaskDelay(UNITY_TASK_DELAY_TICKS); + + /* Check that all the task_As have run, and none of the task_Bs have run */ + for (UBaseType_t x = 0; x < configNUM_CORES; x++) { + TEST_ASSERT_EQUAL(pdTRUE, task_A_ran[x]); + TEST_ASSERT_EQUAL(pdFALSE, task_B_ran[x]); + } + + /* Cleanup */ + for (UBaseType_t x = 0; x < configNUM_CORES; x++) { + vTaskDelete(task_A_handles[x]); + vTaskDelete(task_B_handles[x]); + } + + /* Restore the priority of the unityTask */ + vTaskPrioritySet(NULL, configTEST_UNITY_TASK_PRIORITY); +} + +#endif /* ( defined( CONFIG_FREERTOS_SMP ) && ( configNUM_CORES > 1 ) && ( configRUN_MULTIPLE_PRIORITIES == 1 ) ) + || ( !defined( CONFIG_FREERTOS_SMP ) && ( configNUM_CORES > 1 ) ) */ diff --git a/components/freertos/test/integration/tasks/test_task_delay.c b/components/freertos/test/integration/tasks/test_task_delay.c new file mode 100644 index 0000000000..9a54db40b5 --- /dev/null +++ b/components/freertos/test/integration/tasks/test_task_delay.c @@ -0,0 +1,163 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" +#include "unity.h" +#include "freertos_test_utils.h" +#include "portTestMacro.h" + +/* ------------------------------------------------------------------------------------------------------------------ */ + +/* +Test vTaskDelay + +Purpose: + - Test that vTaskDelay is accurate +Procedure: + - The test contains TEST_VTASKDELAY_ITERATIONS number of iterations. For each iteration... + - vTaskDelay(1) to align to next tick boundary + - Store current tick count and current time (using ref clock) + - vTaskDelay for TEST_VTASKDELAY_TICKS + - Get post delay tick count and ref clock time + - For single core, run the test directly from the UnityTask + - For SMP, run the test once on each core (using vTestOnAllCores()) +Expected: + - The elapsed ticks should be TEST_VTASKDELAY_TICKS, with 1 tick of error allowed (in case ref clock functions last + long enough to cross a tick boundary). + - The elapsed time should be equivalent to TEST_VTASKDELAY_TICKS tick periods, with 1 tick period of error allowed + (in case ref clock functions last longer that a tick period). +*/ + +#if ( INCLUDE_vTaskDelay == 1 ) + +#define TEST_VTASKDELAY_TICKS 5 // Number of ticks to delay in test +#define TEST_VTASKDELAY_ITERATIONS 5 // Number of iterations in test + +static void test_vTaskDelay(void *arg) +{ + for (int i = 0; i < TEST_VTASKDELAY_ITERATIONS; i++) { + TickType_t tick_start, tick_end; + portTEST_REF_CLOCK_TYPE ref_clock_start, ref_clock_end; + + /* Delay until the next tick boundary */ + vTaskDelay(1); + + /* Get the current tick count and ref clock time */ + tick_start = xTaskGetTickCount(); + ref_clock_start = portTEST_REF_CLOCK_GET_TIME(); + + vTaskDelay(TEST_VTASKDELAY_TICKS); + + /* Get the post delay tick count and ref clock time */ + tick_end = xTaskGetTickCount(); + ref_clock_end = portTEST_REF_CLOCK_GET_TIME(); + + /* Check that elapsed ticks and ref clock is accurate. We allow 1 tick of error in case vTaskDelay() was called + * right before/after the tick boundary. */ + #if ( configUSE_16_BIT_TICKS == 1 ) + TEST_ASSERT_UINT16_WITHIN(1, TEST_VTASKDELAY_TICKS, tick_end - tick_start); + #else + TEST_ASSERT_UINT32_WITHIN(1, TEST_VTASKDELAY_TICKS, tick_end - tick_start); + #endif + TEST_ASSERT_UINT32_WITHIN(portTEST_TICKS_TO_REF_CLOCK(1), + portTEST_TICKS_TO_REF_CLOCK(TEST_VTASKDELAY_TICKS), + ref_clock_end - ref_clock_start); + } +} + +TEST_CASE("Tasks: Test vTaskDelay", "[freertos]") +{ + portTEST_REF_CLOCK_INIT(); + + #if ( configNUM_CORES > 1 ) + vTestOnAllCores(test_vTaskDelay, NULL, configTEST_DEFAULT_STACK_SIZE, configTEST_UNITY_TASK_PRIORITY - 1); + #else + /* Test vTaskDelay directly on the current core */ + test_vTaskDelay(NULL); + #endif + + portTEST_REF_CLOCK_DEINIT(); +} + +#endif /* ( INCLUDE_vTaskDelay == 1 ) */ + +/* ------------------------------------------------------------------------------------------------------------------ */ + +/* +Test vTaskDelayUntil + +Purpose: + - Test that vTaskDelayUntil is accurate +Procedure: + - The test contains TEST_VTASKDELAYUNTIL_ITERATIONS number of iterations. For each iteration... + - vTaskDelay(1) to align to next tick boundary + - Store current tick count and current time (using ref clock) + - Call vTaskDelayUntil() for TEST_VTASKDELAYUNTIL_TICKS, using the stored tick count as the previous wake time + - Get post delay tick count and ref clock time + - For single core, run the test directly from the UnityTask + - For SMP, run the test once on each core (using vTestOnAllCores()) +Expected: + - The elapsed ticks should be exactly TEST_VTASKDELAYUNTIL_TICKS since vTaskDelayUntil() is relative to the previous + wake time + - The elapsed time should be equivalent to TEST_VTASKDELAYUNTIL_TICKS tick periods, with 1 tick period of error + allowed (in case ref clock functions last longer that a tick period). +*/ + +#if ( INCLUDE_xTaskDelayUntil == 1 ) + +#define TEST_VTASKDELAYUNTIL_TICKS 5 // Number of ticks to delay in test +#define TEST_VTASKDELAYUNTIL_ITERATIONS 5 // Number of iterations in test + +static void test_vTaskDelayUntil(void *arg) +{ + /* Delay until the next tick boundary */ + vTaskDelay(1); + + for (int i = 0; i < TEST_VTASKDELAYUNTIL_ITERATIONS; i++) { + TickType_t tick_start, tick_end, last_wake_tick; + portTEST_REF_CLOCK_TYPE ref_clock_start, ref_clock_end; + + /* Get the current tick count and ref clock time */ + tick_start = xTaskGetTickCount(); + last_wake_tick = tick_start; + ref_clock_start = portTEST_REF_CLOCK_GET_TIME(); + + vTaskDelayUntil(&last_wake_tick, TEST_VTASKDELAYUNTIL_TICKS); + + /* Get the post delay tick count and ref clock time */ + tick_end = xTaskGetTickCount(); + ref_clock_end = portTEST_REF_CLOCK_GET_TIME(); + + /* Check that the elapsed ticks is accurate. Elapsed ticks should be exact as vTaskDelayUntil() executes a + * delay relative to last_wake_tick. */ + TEST_ASSERT_EQUAL(TEST_VTASKDELAYUNTIL_TICKS, tick_end - tick_start); + TEST_ASSERT_EQUAL(tick_end, last_wake_tick); + + /* Check that the elapsed ref clock time is accurate. We allow 1 tick time worth of error to account for the + * the execution time of the ref clock functions. */ + TEST_ASSERT_UINT32_WITHIN(portTEST_TICKS_TO_REF_CLOCK(1), + portTEST_TICKS_TO_REF_CLOCK(TEST_VTASKDELAYUNTIL_TICKS), + ref_clock_end - ref_clock_start); + } +} + +TEST_CASE("Tasks: Test vTaskDelayUntil", "[freertos]") +{ + portTEST_REF_CLOCK_INIT(); + + #if ( configNUM_CORES > 1 ) + vTestOnAllCores(test_vTaskDelayUntil, NULL, configTEST_DEFAULT_STACK_SIZE, configTEST_UNITY_TASK_PRIORITY - 1); + #else + /* Test vTaskDelay directly on the current core */ + test_vTaskDelayUntil(NULL); + #endif + + portTEST_REF_CLOCK_DEINIT(); +} + +#endif /* ( INCLUDE_xTaskDelayUntil == 1 ) */ diff --git a/components/freertos/test/integration/tasks/test_vTaskSuspendAll_xTaskResumeAll.c b/components/freertos/test/integration/tasks/test_vTaskSuspendAll_xTaskResumeAll.c index 34d5d96d33..4ef4f081e4 100644 --- a/components/freertos/test/integration/tasks/test_vTaskSuspendAll_xTaskResumeAll.c +++ b/components/freertos/test/integration/tasks/test_vTaskSuspendAll_xTaskResumeAll.c @@ -229,6 +229,8 @@ TEST_CASE("Test vTaskSuspendAll() and xTaskResumeAll() multicore", "[freertos]") } vSemaphoreDelete(done_sem); + // Add a short delay to allow the idle task to free any remaining task memory + vTaskDelay(10); } #endif // !CONFIG_FREERTOS_UNICORE @@ -387,6 +389,8 @@ TEST_CASE("Test vTaskSuspendAll allows scheduling on other cores", "[freertos]") } vSemaphoreDelete(test_unblk_done_sem); + // Add a short delay to allow the idle task to free any remaining task memory + vTaskDelay(10); } #endif // !CONFIG_FREERTOS_UNICORE @@ -504,5 +508,7 @@ TEST_CASE("Test xTaskResumeAll resumes pended tasks", "[freertos]") ulTaskNotifyTake(pdTRUE, portMAX_DELAY); vTaskDelete(susp_tsk_hdl); } + // Add a short delay to allow the idle task to free any remaining task memory + vTaskDelay(10); } #endif // !CONFIG_FREERTOS_SMP diff --git a/components/freertos/test_apps/.build-test-rules.yml b/components/freertos/test_apps/.build-test-rules.yml new file mode 100644 index 0000000000..8a0214c0a6 --- /dev/null +++ b/components/freertos/test_apps/.build-test-rules.yml @@ -0,0 +1,6 @@ +# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps + +components/freertos/test_apps/orig_inc_path: + enable: + - if: IDF_TARGET in ["esp32"] + reason: The feature only depends on the build system, nothing target-specific that needs to be tested diff --git a/components/freertos/test_apps/orig_inc_path/CMakeLists.txt b/components/freertos/test_apps/orig_inc_path/CMakeLists.txt new file mode 100644 index 0000000000..1ddfb866ad --- /dev/null +++ b/components/freertos/test_apps/orig_inc_path/CMakeLists.txt @@ -0,0 +1,6 @@ +# The following lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(test_freertos_orig_inc_path) diff --git a/components/freertos/test_apps/orig_inc_path/README.md b/components/freertos/test_apps/orig_inc_path/README.md new file mode 100644 index 0000000000..f708a1985a --- /dev/null +++ b/components/freertos/test_apps/orig_inc_path/README.md @@ -0,0 +1,2 @@ +| Supported Targets | ESP32 | +| ----------------- | ----- | diff --git a/components/freertos/test_apps/orig_inc_path/main/CMakeLists.txt b/components/freertos/test_apps/orig_inc_path/main/CMakeLists.txt new file mode 100644 index 0000000000..5b80b256ee --- /dev/null +++ b/components/freertos/test_apps/orig_inc_path/main/CMakeLists.txt @@ -0,0 +1,6 @@ +idf_component_register(SRCS "test_main.c" + INCLUDE_DIRS ".") + +# Update include path to not include the directory, i.e. "task.h" instead of "freertos/task.h" +idf_component_get_property(FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH) +target_include_directories(${COMPONENT_TARGET} PRIVATE "${FREERTOS_ORIG_INCLUDE_PATH}") diff --git a/components/freertos/test_apps/orig_inc_path/main/test_main.c b/components/freertos/test_apps/orig_inc_path/main/test_main.c new file mode 100644 index 0000000000..a597b1b3b8 --- /dev/null +++ b/components/freertos/test_apps/orig_inc_path/main/test_main.c @@ -0,0 +1,13 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Check that freeRTOS headers can be included without the 'freertos/' directory path prefix */ +#include "FreeRTOS.h" +#include "task.h" + +void app_main(void) +{ +} diff --git a/components/freertos/test_apps/orig_inc_path/sdkconfig.ci.default b/components/freertos/test_apps/orig_inc_path/sdkconfig.ci.default new file mode 100644 index 0000000000..e69de29bb2 diff --git a/components/freertos/test_apps/orig_inc_path/sdkconfig.ci.freertos_smp b/components/freertos/test_apps/orig_inc_path/sdkconfig.ci.freertos_smp new file mode 100644 index 0000000000..08f988b14a --- /dev/null +++ b/components/freertos/test_apps/orig_inc_path/sdkconfig.ci.freertos_smp @@ -0,0 +1 @@ +CONFIG_FREERTOS_SMP=y diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index 0c21243325..deb55e1ea1 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -32,17 +32,12 @@ if(NOT BOOTLOADER_BUILD) "spi_slave_hal_iram.c" "timer_hal.c" "timer_hal_iram.c" - "ledc_hal.c" - "ledc_hal_iram.c" - "i2c_hal.c" - "i2c_hal_iram.c" "gpio_hal.c" "uart_hal.c" "uart_hal_iram.c" "spi_flash_hal.c" "spi_flash_hal_iram.c" "spi_flash_encrypt_hal_iram.c" - "sha_hal.c" "adc_hal_common.c" "adc_oneshot_hal.c") @@ -50,6 +45,14 @@ if(NOT BOOTLOADER_BUILD) list(APPEND srcs "systimer_hal.c") endif() + if(CONFIG_SOC_LEDC_SUPPORTED) + list(APPEND srcs "ledc_hal.c" "ledc_hal_iram.c") + endif() + + if(CONFIG_SOC_I2C_SUPPORTED) + list(APPEND srcs "i2c_hal.c" "i2c_hal_iram.c") + endif() + if(CONFIG_SOC_RMT_SUPPORTED) list(APPEND srcs "rmt_hal.c") endif() @@ -94,6 +97,10 @@ if(NOT BOOTLOADER_BUILD) list(APPEND srcs "ecc_hal.c") endif() + if(CONFIG_SOC_SHA_SUPPORTED) + list(APPEND srcs "sha_hal.c") + endif() + if(${target} STREQUAL "esp32") list(APPEND srcs "dac_hal.c" @@ -119,7 +126,7 @@ if(NOT BOOTLOADER_BUILD) "esp32s2/cp_dma_hal.c" "esp32s2/touch_sensor_hal.c" "esp32s2/dac_hal.c" - "usbh_hal.c") + "usb_dwc_hal.c") endif() if(${target} STREQUAL "esp32s3") @@ -136,7 +143,7 @@ if(NOT BOOTLOADER_BUILD) "esp32s3/hmac_hal.c" "esp32s3/touch_sensor_hal.c" "esp32s3/rtc_cntl_hal.c" - "usbh_hal.c") + "usb_dwc_hal.c") endif() if(${target} STREQUAL "esp32c3") @@ -169,6 +176,20 @@ if(NOT BOOTLOADER_BUILD) "esp32c2/brownout_hal.c" "esp32c2/rtc_cntl_hal.c") endif() + + if(${target} STREQUAL "esp32c6") + list(APPEND srcs + "spi_flash_hal_gpspi.c" + "spi_slave_hd_hal.c" + "esp32c6/brownout_hal.c" + "esp32c6/rtc_cntl_hal.c") + + # TODO: IDF-5310 + list(REMOVE_ITEM srcs + "adc_oneshot_hal.c" + "adc_hal_common.c" + ) + endif() endif() idf_component_register(SRCS ${srcs} diff --git a/components/hal/adc_oneshot_hal.c b/components/hal/adc_oneshot_hal.c index e8597f62f3..b7664aa0c9 100644 --- a/components/hal/adc_oneshot_hal.c +++ b/components/hal/adc_oneshot_hal.c @@ -25,7 +25,7 @@ #endif -#if SOC_DAC_SUPPORTED +#if CONFIG_ADC_DISABLE_DAC_OUTPUT // To disable DAC, workarounds, see this function body to know more static void s_disable_dac(adc_oneshot_hal_ctx_t *hal, adc_channel_t channel); #endif @@ -52,7 +52,7 @@ void adc_oneshot_hal_setup(adc_oneshot_hal_ctx_t *hal, adc_channel_t chan) adc_ll_amp_disable(); //Currently the LNA is not open, close it by default. #endif -#if SOC_DAC_SUPPORTED +#if CONFIG_ADC_DISABLE_DAC_OUTPUT s_disable_dac(hal, chan); #endif @@ -144,7 +144,7 @@ bool adc_oneshot_hal_convert(adc_oneshot_hal_ctx_t *hal, int *out_raw) /*--------------------------------------------------------------- Workarounds ---------------------------------------------------------------*/ -#if SOC_DAC_SUPPORTED +#if CONFIG_ADC_DISABLE_DAC_OUTPUT static void s_disable_dac(adc_oneshot_hal_ctx_t *hal, adc_channel_t channel) { /** diff --git a/components/hal/cache_hal.c b/components/hal/cache_hal.c index 48d374ff8c..f0fb9cd5ee 100644 --- a/components/hal/cache_hal.c +++ b/components/hal/cache_hal.c @@ -24,6 +24,8 @@ #include "esp32c2/rom/cache.h" #elif CONFIG_IDF_TARGET_ESP32H2 #include "esp32h2/rom/cache.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/cache.h" #endif /*------------------------------------------------------------------------------ diff --git a/components/hal/esp32/include/hal/gpio_ll.h b/components/hal/esp32/include/hal/gpio_ll.h index 841e0c9960..7c139f73ff 100644 --- a/components/hal/esp32/include/hal/gpio_ll.h +++ b/components/hal/esp32/include/hal/gpio_ll.h @@ -27,6 +27,9 @@ extern "C" { #endif +// the address of esp32's IO_MUX_GPIOx_REGs are not incremented as the gpio number increments(address are out of order) +extern const uint8_t GPIO_PIN_MUX_REG_OFFSET[SOC_GPIO_PIN_COUNT]; + // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) @@ -53,9 +56,10 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) { - REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); + REG_CLR_BIT(DR_REG_IO_MUX_BASE + GPIO_PIN_MUX_REG_OFFSET[gpio_num], FUN_PU); } /** @@ -87,9 +91,10 @@ static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) { - REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); + REG_CLR_BIT(DR_REG_IO_MUX_BASE + GPIO_PIN_MUX_REG_OFFSET[gpio_num], FUN_PD); } /** @@ -303,9 +308,10 @@ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); + PIN_INPUT_DISABLE(DR_REG_IO_MUX_BASE + GPIO_PIN_MUX_REG_OFFSET[gpio_num]); } /** @@ -325,6 +331,7 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_output_disable(gpio_dev_t *hw, uint32_t gpio_num) { if (gpio_num < 32) { @@ -419,6 +426,18 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num) hw->pin[gpio_num].pad_driver = 1; } +/** + * @brief Select a function for the pin in the IOMUX + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + * @param func Function to assign to the pin + */ +static inline __attribute__((always_inline)) void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func) +{ + PIN_FUNC_SELECT(DR_REG_IO_MUX_BASE + GPIO_PIN_MUX_REG_OFFSET[gpio_num], func); +} + /** * @brief GPIO set output level * @@ -518,6 +537,7 @@ static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu */ static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw) { + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); } @@ -531,6 +551,21 @@ static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw) CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); } +/** + * @brief Get deep sleep hold status + * + * @param hw Peripheral GPIO hardware instance address. + * + * @return + * - true deep sleep hold is enabled + * - false deep sleep hold is disabled + */ +__attribute__((always_inline)) +static inline bool gpio_ll_deep_sleep_hold_is_en(gpio_dev_t *hw) +{ + return !GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD) && GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); +} + /** * @brief Enable gpio pad hold function. * @@ -553,6 +588,36 @@ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num) CLEAR_PERI_REG_MASK(RTC_IO_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); } +/** + * @brief Get digital gpio pad hold status. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + * + * @note caller must ensure that gpio_num is a digital io pad + * + * @return + * - true digital gpio pad is held + * - false digital gpio pad is unheld + */ +__attribute__((always_inline)) +static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num) +{ + uint32_t mask = 0; + + switch (gpio_num) { + case 1: mask = BIT(1); break; + case 3: mask = BIT(0); break; + case 5: mask = BIT(8); break; + case 6 ... 11 : mask = BIT(gpio_num - 4); break; + case 16 ... 19: + case 21 ... 23: mask = BIT(gpio_num - 7); break; + default: break; + } + + return GET_PERI_REG_MASK(RTC_IO_DIG_PAD_HOLD_REG, mask); +} + /** * @brief Set pad input to a peripheral signal through the IOMUX. * diff --git a/components/hal/esp32/include/hal/i2c_ll.h b/components/hal/esp32/include/hal/i2c_ll.h index af94151cf0..83b898b0dd 100644 --- a/components/hal/esp32/include/hal/i2c_ll.h +++ b/components/hal/esp32/include/hal/i2c_ll.h @@ -8,18 +8,18 @@ #pragma once +#include #include "hal/misc.h" #include "soc/i2c_periph.h" #include "soc/i2c_struct.h" #include "soc/clk_tree_defs.h" #include "hal/i2c_types.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { #endif -#define I2C_LL_INTR_MASK (0x3fff) /*!< I2C all interrupt bitmap */ - /** * @brief I2C hardware cmd register fields. */ @@ -36,33 +36,6 @@ typedef union { uint32_t val; } i2c_hw_cmd_t; -/** - * @brief I2C interrupt event - */ -typedef enum { - I2C_INTR_EVENT_ERR, - I2C_INTR_EVENT_ARBIT_LOST, /*!< I2C arbition lost event */ - I2C_INTR_EVENT_NACK, /*!< I2C NACK event */ - I2C_INTR_EVENT_TOUT, /*!< I2C time out event */ - I2C_INTR_EVENT_END_DET, /*!< I2C end detected event */ - I2C_INTR_EVENT_TRANS_DONE, /*!< I2C trans done event */ - I2C_INTR_EVENT_RXFIFO_FULL, /*!< I2C rxfifo full event */ - I2C_INTR_EVENT_TXFIFO_EMPTY, /*!< I2C txfifo empty event */ -} i2c_intr_event_t; - -/** - * @brief Data structure for calculating I2C bus timing. - */ -typedef struct { - uint16_t scl_low; /*!< I2C scl low period */ - uint16_t scl_high; /*!< I2C scl hight period */ - uint16_t sda_hold; /*!< I2C scl low period */ - uint16_t sda_sample; /*!< I2C sda sample time */ - uint16_t setup; /*!< I2C start and stop condition setup period */ - uint16_t hold; /*!< I2C start and stop condition hold period */ - uint16_t tout; /*!< I2C bus timeout period */ -} i2c_clk_cal_t; - // I2C operation mode command #define I2C_LL_CMD_RESTART 0 /*!scl_low = half_cycle; @@ -114,7 +92,7 @@ static inline void i2c_ll_cal_bus_clk(uint32_t source_clk, uint32_t bus_freq, i2 * * @return None */ -static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_clk_cal_t *bus_cfg) +static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_hal_clk_config_t *bus_cfg) { /* SCL period. According to the TRM, we should always subtract 1 to SCL low period */ assert(bus_cfg->scl_low > 0); @@ -199,7 +177,8 @@ static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int hight_period, int lo * * @return None */ -static inline void i2c_ll_clr_intsts_mask(i2c_dev_t *hw, uint32_t mask) +__attribute__((always_inline)) +static inline void i2c_ll_clear_intr_mask(i2c_dev_t *hw, uint32_t mask) { hw->int_clr.val = mask; } @@ -225,6 +204,7 @@ static inline void i2c_ll_enable_intr_mask(i2c_dev_t *hw, uint32_t mask) * * @return None */ +__attribute__((always_inline)) static inline void i2c_ll_disable_intr_mask(i2c_dev_t *hw, uint32_t mask) { hw->int_ena.val &= (~mask); @@ -237,9 +217,10 @@ static inline void i2c_ll_disable_intr_mask(i2c_dev_t *hw, uint32_t mask) * * @return I2C interrupt status */ -static inline uint32_t i2c_ll_get_intsts_mask(i2c_dev_t *hw) +__attribute__((always_inline)) +static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status) { - return hw->int_status.val; + *intr_status = hw->int_status.val; } /** @@ -413,17 +394,6 @@ static inline void i2c_ll_get_sda_timing(i2c_dev_t *hw, int *sda_sample, int *sd *sda_sample = hw->sda_sample.time; } -/** - * @brief Get the I2C hardware version - * - * @param hw Beginning address of the peripheral registers - * - * @return The I2C hardware version - */ -static inline uint32_t i2c_ll_get_hw_version(i2c_dev_t *hw) -{ - return hw->date; -} /** * @brief Check if the I2C bus is busy @@ -437,18 +407,6 @@ static inline bool i2c_ll_is_bus_busy(i2c_dev_t *hw) return hw->status_reg.bus_busy; } -/** - * @brief Check if I2C is master mode - * - * @param hw Beginning address of the peripheral registers - * - * @return True if I2C is master mode, else false will be returned - */ -static inline bool i2c_ll_is_master_mode(i2c_dev_t *hw) -{ - return hw->ctr.ms_mode; -} - /** * @brief Get the rxFIFO readable length * @@ -456,9 +414,10 @@ static inline bool i2c_ll_is_master_mode(i2c_dev_t *hw) * * @return RxFIFO readable length */ -static inline uint32_t i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw) +__attribute__((always_inline)) +static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length) { - return hw->status_reg.rx_fifo_cnt; + *length = hw->status_reg.rx_fifo_cnt; } /** @@ -468,9 +427,10 @@ static inline uint32_t i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw) * * @return TxFIFO writable length */ -static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw) +__attribute__((always_inline)) +static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length) { - return SOC_I2C_FIFO_LEN - hw->status_reg.tx_fifo_cnt; + *length = SOC_I2C_FIFO_LEN - hw->status_reg.tx_fifo_cnt; } /** @@ -480,9 +440,9 @@ static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw) * * @return The I2C timeout value */ -static inline uint32_t i2c_ll_get_tout(i2c_dev_t *hw) +static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout) { - return hw->timeout.tout; + *timeout = hw->timeout.tout; } /** @@ -551,7 +511,8 @@ static inline void i2c_ll_get_scl_timing(i2c_dev_t *hw, int *high_period, int *l * * @return None. */ -static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) +__attribute__((always_inline)) +static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len) { uint32_t fifo_addr = (hw == &I2C0) ? 0x6001301c : 0x6002701c; for(int i = 0; i < len; i++) { @@ -568,6 +529,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) * * @return None */ +__attribute__((always_inline)) static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) { for(int i = 0; i < len; i++) { @@ -604,155 +566,9 @@ static inline void i2c_ll_set_filter(i2c_dev_t *hw, uint8_t filter_num) * * @return The hardware filter configuration */ -static inline uint8_t i2c_ll_get_filter(i2c_dev_t *hw) +static inline void i2c_ll_get_filter(i2c_dev_t *hw, uint8_t *filter_conf) { - return hw->sda_filter_cfg.thres; -} - -/** - * @brief Enable I2C master TX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_enable_tx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = ~0; - hw->int_ena.val = I2C_LL_MASTER_TX_INT; -} - -/** - * @brief Enable I2C master RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_enable_rx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = ~0; - hw->int_ena.val = I2C_LL_MASTER_RX_INT; -} - -/** - * @brief Disable I2C master TX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_disable_tx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT); -} - -/** - * @brief Disable I2C master RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_MASTER_RX_INT); -} - -/** - * @brief Clear I2C master TX interrupt status register - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_clr_tx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = I2C_LL_MASTER_TX_INT; -} - -/** - * @brief Clear I2C master RX interrupt status register - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_clr_rx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = I2C_LL_MASTER_RX_INT; -} - -/** - * @brief - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_enable_tx_it(i2c_dev_t *hw) -{ - hw->int_ena.val |= I2C_LL_SLAVE_TX_INT; -} - -/** - * @brief Enable I2C slave RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_enable_rx_it(i2c_dev_t *hw) -{ - hw->int_ena.val |= I2C_LL_SLAVE_RX_INT; -} - -/** - * @brief Disable I2C slave TX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_disable_tx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_SLAVE_TX_INT); -} - -/** - * @brief Disable I2C slave RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT); -} - -/** - * @brief Clear I2C slave TX interrupt status register - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_clr_tx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = I2C_LL_SLAVE_TX_INT; -} - -/** - * @brief Clear I2C slave RX interrupt status register. - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_clr_rx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = I2C_LL_SLAVE_RX_INT; + *filter_conf = hw->sda_filter_cfg.thres; } /** @@ -795,54 +611,6 @@ static inline void i2c_ll_set_source_clk(i2c_dev_t *hw, i2c_clock_source_t src_c ;//Not support on ESP32 } -/** - * @brief Get I2C master interrupt event - * - * @param hw Beginning address of the peripheral registers - * @param event Pointer to accept the interrupt event - * - * @return None - */ -static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) -{ - typeof(hw->int_status) int_sts = hw->int_status; - if (int_sts.arbitration_lost) { - *event = I2C_INTR_EVENT_ARBIT_LOST; - } else if (int_sts.ack_err) { - *event = I2C_INTR_EVENT_NACK; - } else if (int_sts.time_out) { - *event = I2C_INTR_EVENT_TOUT; - } else if (int_sts.end_detect) { - *event = I2C_INTR_EVENT_END_DET; - } else if (int_sts.trans_complete) { - *event = I2C_INTR_EVENT_TRANS_DONE; - } else { - *event = I2C_INTR_EVENT_ERR; - } -} - -/** - * @brief Get I2C slave interrupt event - * - * @param hw Beginning address of the peripheral registers - * @param event Pointer to accept the interrupt event - * - * @return None - */ -static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) -{ - typeof(hw->int_status) int_sts = hw->int_status; - if (int_sts.tx_fifo_empty) { - *event = I2C_INTR_EVENT_TXFIFO_EMPTY; - } else if (int_sts.trans_complete) { - *event = I2C_INTR_EVENT_TRANS_DONE; - } else if (int_sts.rx_fifo_full) { - *event = I2C_INTR_EVENT_RXFIFO_FULL; - } else { - *event = I2C_INTR_EVENT_ERR; - } -} - /** * @brief Init I2C master * @@ -890,22 +658,60 @@ static inline void i2c_ll_update(i2c_dev_t *hw) } /** - * @brief Configure I2C SCL timing + * @brief Set whether slave should auto start, or only start with start signal from master * - * @param hw Beginning address of the peripheral registers - * @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2) - * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) - * @param wait_high_period The I2C SCL wait rising edge period. - * - * @return None. + * @param hw Beginning address of the peripheral registers + * @param slv_ex_auto_en 1 if slave auto start data transaction, otherwise, 0. */ -static inline void i2c_ll_set_scl_clk_timing(i2c_dev_t *hw, int high_period, int low_period, int wait_high_period) +static inline void i2c_ll_slave_tx_auto_start_en(i2c_dev_t *hw, bool slv_ex_auto_en) { - (void)wait_high_period; - hw->scl_low_period.period = low_period; - hw->scl_high_period.period = high_period; + ;// ESP32 do not support } +/** + * @brief Get I2C interrupt status register address + */ +static inline volatile void *i2c_ll_get_interrupt_status_reg(i2c_dev_t *dev) +{ + return &dev->int_status; +} + +//////////////////////////////////////////Deprecated Functions////////////////////////////////////////////////////////// +/////////////////////////////The following functions are only used by the legacy driver///////////////////////////////// +/////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +// Get the I2C hardware instance +#define I2C_LL_GET_HW(i2c_num) (((i2c_num) == 0) ? &I2C0 : &I2C1) +// Get the I2C hardware FIFO address +#define I2C_LL_GET_FIFO_ADDR(i2c_num) (I2C_DATA_APB_REG(i2c_num)) +// I2C master TX interrupt bitmap +#define I2C_LL_MASTER_TX_INT (I2C_ACK_ERR_INT_ENA_M|I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M) +// I2C master RX interrupt bitmap +#define I2C_LL_MASTER_RX_INT (I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M) +// I2C slave TX interrupt bitmap +#define I2C_LL_SLAVE_TX_INT (I2C_TXFIFO_EMPTY_INT_ENA_M) +// I2C slave RX interrupt bitmap +#define I2C_LL_SLAVE_RX_INT (I2C_RXFIFO_FULL_INT_ENA_M | I2C_TRANS_COMPLETE_INT_ENA_M) +// I2C max timeout value +#define I2C_LL_MAX_TIMEOUT I2C_TIME_OUT_REG_V + +#define I2C_LL_INTR_MASK (0xffff) /*!< I2C all interrupt bitmap */ + +/** + * @brief I2C interrupt event + */ +typedef enum { + I2C_INTR_EVENT_ERR, + I2C_INTR_EVENT_ARBIT_LOST, /*!< I2C arbition lost event */ + I2C_INTR_EVENT_NACK, /*!< I2C NACK event */ + I2C_INTR_EVENT_TOUT, /*!< I2C time out event */ + I2C_INTR_EVENT_END_DET, /*!< I2C end detected event */ + I2C_INTR_EVENT_TRANS_DONE, /*!< I2C trans done event */ + I2C_INTR_EVENT_RXFIFO_FULL, /*!< I2C rxfifo full event */ + I2C_INTR_EVENT_TXFIFO_EMPTY, /*!< I2C txfifo empty event */ +} i2c_intr_event_t; + /** * @brief Get I2C SCL timing configuration * @@ -922,6 +728,186 @@ static inline void i2c_ll_get_scl_clk_timing(i2c_dev_t *hw, int *high_period, in *low_period = hw->scl_low_period.period; } +/** + * @brief Configure I2C SCL timing + * + * @param hw Beginning address of the peripheral registers + * @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2) + * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) + * @param wait_high_period The I2C SCL wait rising edge period. + * + * @return None. + */ +static inline void i2c_ll_set_scl_clk_timing(i2c_dev_t *hw, int high_period, int low_period, int wait_high_period) +{ + (void)wait_high_period; + hw->scl_low_period.period = low_period; + hw->scl_high_period.period = high_period; +} + +/** + * @brief Get I2C slave interrupt event + * + * @param hw Beginning address of the peripheral registers + * @param event Pointer to accept the interrupt event + * + * @return None + */ +__attribute__((always_inline)) +static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) +{ + typeof(hw->int_status) int_sts = hw->int_status; + if (int_sts.tx_fifo_empty) { + *event = I2C_INTR_EVENT_TXFIFO_EMPTY; + } else if (int_sts.trans_complete) { + *event = I2C_INTR_EVENT_TRANS_DONE; + } else if (int_sts.rx_fifo_full) { + *event = I2C_INTR_EVENT_RXFIFO_FULL; + } else { + *event = I2C_INTR_EVENT_ERR; + } +} + +/** + * @brief Get I2C master interrupt event + * + * @param hw Beginning address of the peripheral registers + * @param event Pointer to accept the interrupt event + * + * @return None + */ +__attribute__((always_inline)) +static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) +{ + typeof(hw->int_status) int_sts = hw->int_status; + if (int_sts.arbitration_lost) { + *event = I2C_INTR_EVENT_ARBIT_LOST; + } else if (int_sts.ack_err) { + *event = I2C_INTR_EVENT_NACK; + } else if (int_sts.time_out) { + *event = I2C_INTR_EVENT_TOUT; + } else if (int_sts.end_detect) { + *event = I2C_INTR_EVENT_END_DET; + } else if (int_sts.trans_complete) { + *event = I2C_INTR_EVENT_TRANS_DONE; + } else { + *event = I2C_INTR_EVENT_ERR; + } +} + +/** + * @brief + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_slave_enable_tx_it(i2c_dev_t *hw) +{ + hw->int_ena.val |= I2C_LL_SLAVE_TX_INT; +} + +/** + * @brief Enable I2C slave RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_slave_enable_rx_it(i2c_dev_t *hw) +{ + hw->int_ena.val |= I2C_LL_SLAVE_RX_INT; +} + +/** + * @brief Disable I2C slave TX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +__attribute__((always_inline)) +static inline void i2c_ll_slave_disable_tx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_SLAVE_TX_INT); +} + +/** + * @brief Disable I2C slave RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT); +} + +/** + * @brief Enable I2C master TX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_enable_tx_it(i2c_dev_t *hw) +{ + hw->int_clr.val = UINT32_MAX; + hw->int_ena.val = I2C_LL_MASTER_TX_INT; +} + +/** + * @brief Enable I2C master RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_enable_rx_it(i2c_dev_t *hw) +{ + hw->int_clr.val = UINT32_MAX; + hw->int_ena.val = I2C_LL_MASTER_RX_INT; +} + +/** + * @brief Disable I2C master TX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_disable_tx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT); +} + +/** + * @brief Disable I2C master RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +__attribute__((always_inline)) +static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_MASTER_RX_INT); +} + +/** + * @brief Get the I2C hardware version + * + * @param hw Beginning address of the peripheral registers + * + * @return The I2C hardware version + */ +static inline uint32_t i2c_ll_get_hw_version(i2c_dev_t *hw) +{ + return hw->date; +} + + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32/include/hal/i2s_ll.h b/components/hal/esp32/include/hal/i2s_ll.h index 37b15698b2..70e9a79442 100644 --- a/components/hal/esp32/include/hal/i2s_ll.h +++ b/components/hal/esp32/include/hal/i2s_ll.h @@ -29,7 +29,6 @@ extern "C" { #define I2S_LL_AD_BCK_FACTOR (2) #define I2S_LL_PDM_BCK_FACTOR (64) -#define I2S_LL_BASE_CLK (2 * APB_CLK_FREQ) #define I2S_LL_MCLK_DIVIDER_BIT_WIDTH (6) #define I2S_LL_MCLK_DIVIDER_MAX ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1) @@ -287,7 +286,7 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val) * @note mclk on ESP32 is shared by both TX and RX channel * * @param hw Peripheral I2S hardware instance address. - * @param sclk system clock, 0 means use apll + * @param sclk system clock * @param mclk module clock * @param mclk_div integer part of the division from sclk to mclk */ @@ -363,7 +362,7 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val) * @note mclk on ESP32 is shared by both TX and RX channel * * @param hw Peripheral I2S hardware instance address. - * @param sclk system clock, 0 means use apll + * @param sclk system clock * @param mclk module clock * @param mclk_div integer part of the division from sclk to mclk */ diff --git a/components/hal/esp32/include/hal/mmu_ll.h b/components/hal/esp32/include/hal/mmu_ll.h index adb5cc62f2..d7d0a8aa23 100644 --- a/components/hal/esp32/include/hal/mmu_ll.h +++ b/components/hal/esp32/include/hal/mmu_ll.h @@ -18,6 +18,38 @@ extern "C" { #endif +/** + * Convert MMU virtual address to linear address + * + * @param vaddr virtual address + * + * @return linear address + */ +static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr) +{ + return vaddr & SOC_MMU_LINEAR_ADDR_MASK; +} + +/** + * Convert MMU linear address to virtual address + * + * @param laddr linear address + * @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t` + * + * @return virtual address + */ +static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type) +{ + uint32_t vaddr_base = 0; + if (vaddr_type == MMU_VADDR_DATA) { + vaddr_base = SOC_MMU_DBUS_VADDR_BASE; + } else { + vaddr_base = SOC_MMU_IBUS_VADDR_BASE; + } + + return vaddr_base | laddr; +} + /** * Get MMU page size * diff --git a/components/hal/esp32/include/hal/rmt_ll.h b/components/hal/esp32/include/hal/rmt_ll.h index b1735e5e6b..e16763ccd5 100644 --- a/components/hal/esp32/include/hal/rmt_ll.h +++ b/components/hal/esp32/include/hal/rmt_ll.h @@ -99,6 +99,20 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, } } +/** + * @brief Enable RMT peripheral source clock + * + * @note RMT doesn't support enable/disable clock source, this function is only for compatibility + * + * @param dev Peripheral instance address + * @param en True to enable, False to disable + */ +static inline void rmt_ll_enable_group_clock(rmt_dev_t *dev, bool en) +{ + (void)dev; + (void)en; +} + ////////////////////////////////////////TX Channel Specific///////////////////////////////////////////////////////////// /** @@ -504,48 +518,57 @@ static inline uint32_t rmt_ll_rx_get_interrupt_status(rmt_dev_t *dev, uint32_t c /////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_status_word(rmt_dev_t *dev, uint32_t channel) { return dev->status_ch[channel]; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_status_word(rmt_dev_t *dev, uint32_t channel) { return dev->status_ch[channel]; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt); return div == 0 ? 256 : div; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt); return div == 0 ? 256 : div; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel) { return HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf0.mem_size; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf0.mem_size; } +__attribute__((always_inline)) static inline bool rmt_ll_tx_is_loop_enabled(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf1.tx_conti_mode; } +__attribute__((always_inline)) static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel) { if (dev->conf_ch[channel].conf1.ref_always_on) { @@ -554,11 +577,13 @@ static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint return RMT_CLK_SRC_REF_TICK; } +__attribute__((always_inline)) static inline bool rmt_ll_tx_is_idle_enabled(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf1.idle_out_en; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf1.idle_out_lv; @@ -570,11 +595,13 @@ static inline bool rmt_ll_is_mem_powered_down(rmt_dev_t *dev) return dev->conf_ch[0].conf0.mem_pd; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_mem_owner(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf1.mem_owner; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev) { uint32_t status = dev->int_st.val; @@ -582,6 +609,7 @@ static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev) ((status & 0x1000) >> 8) | ((status & 0x8000) >> 10) | ((status & 0x40000) >> 12) | ((status & 0x200000) >> 14); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev) { uint32_t status = dev->int_st.val; @@ -589,6 +617,7 @@ static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev) ((status & 0x2000) >> 9) | ((status & 0x10000) >> 11) | ((status & 0x80000) >> 13) | ((status & 0x400000) >> 15); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_err_interrupt_status(rmt_dev_t *dev) { uint32_t status = dev->int_st.val; @@ -596,6 +625,7 @@ static inline uint32_t rmt_ll_get_tx_err_interrupt_status(rmt_dev_t *dev) ((status & 0x4000) >> 10) | ((status & 0x20000) >> 12) | ((status & 0x100000) >> 14) | ((status & 0x800000) >> 16); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_err_interrupt_status(rmt_dev_t *dev) { uint32_t status = dev->int_st.val; @@ -603,6 +633,7 @@ static inline uint32_t rmt_ll_get_rx_err_interrupt_status(rmt_dev_t *dev) ((status & 0x4000) >> 10) | ((status & 0x20000) >> 12) | ((status & 0x100000) >> 14) | ((status & 0x800000) >> 16); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev) { uint32_t status = dev->int_st.val; diff --git a/components/hal/esp32/include/hal/rtc_cntl_ll.h b/components/hal/esp32/include/hal/rtc_cntl_ll.h index 31caf551bf..a4f6b3f7d8 100644 --- a/components/hal/esp32/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32/include/hal/rtc_cntl_ll.h @@ -47,6 +47,22 @@ static inline void rtc_cntl_ll_ulp_int_clear(void) REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_SAR_INT_CLR); } +static inline void rtc_cntl_ll_timer2_set_touch_wait_cycle(uint32_t wait_cycle) +{ + REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, wait_cycle); +} + +static inline void rtc_cntl_ll_reset_system(void) +{ + REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); +} + +static inline void rtc_cntl_ll_reset_cpu(int cpu_no) +{ + uint32_t rtc_cntl_rst = (cpu_no == 0) ? RTC_CNTL_SW_PROCPU_RST : RTC_CNTL_SW_APPCPU_RST; + REG_WRITE(RTC_CNTL_OPTIONS0_REG, rtc_cntl_rst); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32/include/hal/rtc_io_ll.h b/components/hal/esp32/include/hal/rtc_io_ll.h index f96452532e..b84fe52a9f 100644 --- a/components/hal/esp32/include/hal/rtc_io_ll.h +++ b/components/hal/esp32/include/hal/rtc_io_ll.h @@ -1,16 +1,8 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /******************************************************************************* * NOTICE @@ -21,9 +13,7 @@ #pragma once #include -#include "soc/rtc_io_periph.h" -#include "soc/rtc_io_struct.h" -#include "hal/rtc_io_types.h" +#include "soc/rtc_periph.h" #include "hal/gpio_types.h" #define RTCIO_LL_PIN_FUNC 0 @@ -229,6 +219,7 @@ static inline void rtcio_ll_pulldown_disable(int rtcio_num) static inline void rtcio_ll_force_hold_enable(int rtcio_num) { REG_SET_BIT(RTC_CNTL_HOLD_FORCE_REG, rtc_io_desc[rtcio_num].hold_force); + REG_SET_BIT(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].hold); } /** diff --git a/components/hal/esp32/include/hal/spi_ll.h b/components/hal/esp32/include/hal/spi_ll.h index 63efb384eb..cf09b6e94f 100644 --- a/components/hal/esp32/include/hal/spi_ll.h +++ b/components/hal/esp32/include/hal/spi_ll.h @@ -1081,6 +1081,29 @@ static inline void spi_dma_ll_enable_out_auto_wrback(spi_dma_dev_t *dma_out, uin //does not configure it in ESP32 } +/** + * Get the spi communication command + * + * @param cmd_t Base command value + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode) +{ + //This is not supported in esp32 + return 0; +} + +/** + * Get the dummy bits + * + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode) +{ + //This is not supported in esp32 + return 0; +} + #undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK diff --git a/components/hal/esp32/include/hal/timer_ll.h b/components/hal/esp32/include/hal/timer_ll.h index 4922126f47..63ba28801a 100644 --- a/components/hal/esp32/include/hal/timer_ll.h +++ b/components/hal/esp32/include/hal/timer_ll.h @@ -40,6 +40,22 @@ static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num, } } +/** + * @brief Enable Timer Group (GPTimer) module clock + * + * @note This function is not optional, created for backward compatible. + * + * @param hw Timer Group register base address + * @param timer_num Timer index in the group + * @param en true to enable, false to disable + */ +static inline void timer_ll_enable_clock(timg_dev_t *hw, uint32_t timer_num, bool en) +{ + (void)hw; + (void)timer_num; + (void)en; +} + /** * @brief Enable alarm event * @@ -112,6 +128,22 @@ static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, b hw->hw_timer[timer_num].config.tx_en = en; } +/** + * @brief Trigger software capture event + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + */ +__attribute__((always_inline)) +static inline void timer_ll_trigger_soft_capture(timg_dev_t *hw, uint32_t timer_num) +{ + hw->hw_timer[timer_num].update.tx_update = 1; + // Timer register is in a different clock domain from Timer hardware logic + // We need to wait for the update to take effect before fetching the count value + while (hw->hw_timer[timer_num].update.tx_update) { + } +} + /** * @brief Get counter value * @@ -123,11 +155,6 @@ static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, b __attribute__((always_inline)) static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer_num) { - hw->hw_timer[timer_num].update.tx_update = 1; - // Timer register is in a different clock domain from Timer hardware logic - // We need to wait for the update to take effect before fetching the count value - while (hw->hw_timer[timer_num].update.tx_update) { - } return ((uint64_t) hw->hw_timer[timer_num].hi.tx_hi << 32) | (hw->hw_timer[timer_num].lo.tx_lo); } diff --git a/components/hal/esp32/include/hal/uart_ll.h b/components/hal/esp32/include/hal/uart_ll.h index de8fc640ff..7e8e6ae050 100644 --- a/components/hal/esp32/include/hal/uart_ll.h +++ b/components/hal/esp32/include/hal/uart_ll.h @@ -1,16 +1,8 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ // The LL layer for UART register operations. // Note that most of the register operations in this layer are non-atomic operations. @@ -89,31 +81,19 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t* source_clk) *source_clk = hw->conf0.tick_ref_always_on ? UART_SCLK_APB : UART_SCLK_REF_TICK; } -/** - * @brief Get the UART source clock frequency. - * - * @param hw Beginning address of the peripheral registers. - * - * @return Current source clock frequency - */ -FORCE_INLINE_ATTR uint32_t uart_ll_get_sclk_freq(uart_dev_t *hw) -{ - return (hw->conf0.tick_ref_always_on) ? APB_CLK_FREQ : REF_CLK_FREQ; -} - /** * @brief Configure the baud-rate. * * @param hw Beginning address of the peripheral registers. * @param baud The baud-rate to be set. When the source clock is APB, the max baud-rate is `UART_LL_BITRATE_MAX` + * @param sclk_freq Frequency of the clock source of UART, in Hz. * @return None */ -FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud) +FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { - uint32_t sclk_freq, clk_div; + uint32_t clk_div; - sclk_freq = uart_ll_get_sclk_freq(hw); clk_div = ((sclk_freq) << 4) / baud; // The baud-rate configuration register is divided into // an integer part and a fractional part. @@ -125,12 +105,12 @@ FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud) * @brief Get the current baud-rate. * * @param hw Beginning address of the peripheral registers. + * @param sclk_freq Frequency of the clock source of UART, in Hz. * * @return The current baudrate */ -FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq) { - uint32_t sclk_freq = uart_ll_get_sclk_freq(hw); typeof(hw->clk_div) div_reg = hw->clk_div; return ((sclk_freq << 4)) / ((div_reg.div_int << 4) | div_reg.div_frag); } diff --git a/components/hal/esp32c2/efuse_hal.c b/components/hal/esp32c2/efuse_hal.c index 1c01e3f72d..2bf6908baa 100644 --- a/components/hal/esp32c2/efuse_hal.c +++ b/components/hal/esp32c2/efuse_hal.c @@ -10,6 +10,7 @@ #include "hal/assert.h" #include "hal/efuse_hal.h" #include "hal/efuse_ll.h" +#include "hal/clk_tree_ll.h" #define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x0F << (4 * (block)))) @@ -29,6 +30,11 @@ void efuse_hal_set_timing(uint32_t apb_freq_hz) { (void) apb_freq_hz; efuse_ll_set_pwr_off_num(0x190); + int xtal = clk_ll_xtal_load_freq_mhz(); + HAL_ASSERT(xtal == 40 || xtal == 26); + // for the XTAL = 40 MHz we use the default value = 200. + // XTAL = 26 MHz the value = 130. + efuse_ll_set_tpgm_inactive(xtal * 5); } void efuse_hal_read(void) diff --git a/components/hal/esp32c2/include/hal/efuse_hal.h b/components/hal/esp32c2/include/hal/efuse_hal.h index ec1cf007ef..c4bc7fcc1f 100644 --- a/components/hal/esp32c2/include/hal/efuse_hal.h +++ b/components/hal/esp32c2/include/hal/efuse_hal.h @@ -19,7 +19,7 @@ extern "C" { /** * @brief set eFuse timings * - * @param apb_freq_hz APB frequency in Hz + * @param apb_freq_hz APB frequency in Hz (not used, kept for API compatibility) */ void efuse_hal_set_timing(uint32_t apb_freq_hz); diff --git a/components/hal/esp32c2/include/hal/efuse_ll.h b/components/hal/esp32c2/include/hal/efuse_ll.h index 6cbcee4ef5..9847ab3f85 100644 --- a/components/hal/esp32c2/include/hal/efuse_ll.h +++ b/components/hal/esp32c2/include/hal/efuse_ll.h @@ -120,6 +120,10 @@ __attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint1 EFUSE.wr_tim_conf2.pwr_off_num = value; } +__attribute__((always_inline)) static inline void efuse_ll_set_tpgm_inactive(uint8_t value) +{ + EFUSE.wr_tim_conf0.tpgm_inactive = value; +} /******************* eFuse control functions *************************/ #ifdef __cplusplus diff --git a/components/hal/esp32c2/include/hal/gpio_ll.h b/components/hal/esp32c2/include/hal/gpio_ll.h index eee81ebacc..0f7c6ad4be 100644 --- a/components/hal/esp32c2/include/hal/gpio_ll.h +++ b/components/hal/esp32c2/include/hal/gpio_ll.h @@ -14,12 +14,13 @@ #pragma once +#include +#include #include "soc/soc.h" #include "soc/gpio_periph.h" #include "soc/rtc_cntl_reg.h" #include "hal/gpio_types.h" #include "hal/assert.h" -#include "stdlib.h" #ifdef __cplusplus extern "C" { @@ -47,9 +48,10 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) { - REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); + REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU); } /** @@ -69,9 +71,10 @@ static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) { - REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); + REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD); } /** @@ -168,9 +171,10 @@ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); + PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); } /** @@ -190,6 +194,7 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_output_disable(gpio_dev_t *hw, uint32_t gpio_num) { hw->enable_w1tc.enable_w1tc = (0x1 << gpio_num); @@ -231,6 +236,18 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num) hw->pin[gpio_num].pad_driver = 1; } +/** + * @brief Select a function for the pin in the IOMUX + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + * @param func Function to assign to the pin + */ +static inline __attribute__((always_inline)) void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func) +{ + PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func); +} + /** * @brief GPIO set output level * @@ -329,7 +346,22 @@ static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw) */ static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw) { - SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD); + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); +} + +/** + * @brief Get deep sleep hold status + * + * @param hw Peripheral GPIO hardware instance address. + * + * @return + * - true deep sleep hold is enabled + * - false deep sleep hold is disabled + */ +__attribute__((always_inline)) +static inline bool gpio_ll_deep_sleep_hold_is_en(gpio_dev_t *hw) +{ + return !GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD) && GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); } /** @@ -362,6 +394,24 @@ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num) } } +/** + * @brief Get digital gpio pad hold status. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + * + * @note caller must ensure that gpio_num is a digital io pad + * + * @return + * - true digital gpio pad is held + * - false digital gpio pad is unheld + */ +__attribute__((always_inline)) +static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num) +{ + return GET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, BIT(gpio_num)); +} + /** * @brief Set pad input to a peripheral signal through the IOMUX. * diff --git a/components/hal/esp32c2/include/hal/i2c_ll.h b/components/hal/esp32c2/include/hal/i2c_ll.h index 953e5d59a2..5a8db8aba5 100644 --- a/components/hal/esp32c2/include/hal/i2c_ll.h +++ b/components/hal/esp32c2/include/hal/i2c_ll.h @@ -8,6 +8,7 @@ #pragma once +#include #include "hal/misc.h" #include "soc/i2c_periph.h" #include "soc/soc_caps.h" @@ -16,13 +17,12 @@ #include "soc/rtc_cntl_reg.h" #include "soc/clk_tree_defs.h" #include "esp_rom_sys.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { #endif -#define I2C_LL_INTR_MASK (0x3fff) /*!< I2C all interrupt bitmap */ - /** * @brief I2C hardware cmd register fields. */ @@ -39,35 +39,6 @@ typedef union { uint32_t val; } i2c_hw_cmd_t; -/** - * @brief I2C interrupt event - */ -typedef enum { - I2C_INTR_EVENT_ERR, - I2C_INTR_EVENT_ARBIT_LOST, /*!< I2C arbition lost event */ - I2C_INTR_EVENT_NACK, /*!< I2C NACK event */ - I2C_INTR_EVENT_TOUT, /*!< I2C time out event */ - I2C_INTR_EVENT_END_DET, /*!< I2C end detected event */ - I2C_INTR_EVENT_TRANS_DONE, /*!< I2C trans done event */ - I2C_INTR_EVENT_RXFIFO_FULL, /*!< I2C rxfifo full event */ - I2C_INTR_EVENT_TXFIFO_EMPTY, /*!< I2C txfifo empty event */ -} i2c_intr_event_t; - -/** - * @brief Data structure for calculating I2C bus timing. - */ -typedef struct { - uint16_t clkm_div; /*!< I2C core clock devider */ - uint16_t scl_low; /*!< I2C scl low period */ - uint16_t scl_high; /*!< I2C scl hight period */ - uint16_t scl_wait_high; /*!< I2C scl wait_high period */ - uint16_t sda_hold; /*!< I2C scl low period */ - uint16_t sda_sample; /*!< I2C sda sample time */ - uint16_t setup; /*!< I2C start and stop condition setup period */ - uint16_t hold; /*!< I2C start and stop condition hold period */ - uint16_t tout; /*!< I2C bus timeout period */ -} i2c_clk_cal_t; - // I2C operation mode command #define I2C_LL_CMD_RESTART 6 /*!ctr.conf_upgate = 1; @@ -142,7 +120,7 @@ static inline void i2c_ll_update(i2c_dev_t *hw) * * @return None */ -static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_clk_cal_t *bus_cfg) +static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_hal_clk_config_t *bus_cfg) { HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, bus_cfg->clkm_div - 1); /* According to the Technical Reference Manual, the following timings must be subtracted by 1. @@ -216,7 +194,8 @@ static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int hight_period, int lo * * @return None */ -static inline void i2c_ll_clr_intsts_mask(i2c_dev_t *hw, uint32_t mask) +__attribute__((always_inline)) +static inline void i2c_ll_clear_intr_mask(i2c_dev_t *hw, uint32_t mask) { hw->int_clr.val = mask; } @@ -242,6 +221,7 @@ static inline void i2c_ll_enable_intr_mask(i2c_dev_t *hw, uint32_t mask) * * @return None */ +__attribute__((always_inline)) static inline void i2c_ll_disable_intr_mask(i2c_dev_t *hw, uint32_t mask) { hw->int_ena.val &= (~mask); @@ -254,9 +234,10 @@ static inline void i2c_ll_disable_intr_mask(i2c_dev_t *hw, uint32_t mask) * * @return I2C interrupt status */ -static inline uint32_t i2c_ll_get_intsts_mask(i2c_dev_t *hw) +__attribute__((always_inline)) +static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status) { - return hw->int_status.val; + *intr_status = hw->int_status.val; } /** @@ -458,9 +439,10 @@ static inline bool i2c_ll_is_master_mode(i2c_dev_t *hw) * * @return RxFIFO readable length */ -static inline uint32_t i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw) +__attribute__((always_inline)) +static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length) { - return hw->sr.rxfifo_cnt; + *length = hw->sr.rxfifo_cnt; } /** @@ -470,9 +452,10 @@ static inline uint32_t i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw) * * @return TxFIFO writable length */ -static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw) +__attribute__((always_inline)) +static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length) { - return SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt; + *length = SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt; } /** @@ -482,9 +465,9 @@ static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw) * * @return The I2C timeout value */ -static inline uint32_t i2c_ll_get_tout(i2c_dev_t *hw) +static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout) { - return hw->to.time_out_value; + *timeout = hw->to.time_out_value; } /** @@ -553,7 +536,8 @@ static inline void i2c_ll_get_scl_timing(i2c_dev_t *hw, int *high_period, int *l * * @return None. */ -static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) +__attribute__((always_inline)) +static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len) { for (int i = 0; i< len; i++) { HAL_FORCE_MODIFY_U32_REG_FIELD(hw->data, fifo_rdata, ptr[i]); @@ -569,6 +553,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) * * @return None */ +__attribute__((always_inline)) static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) { for(int i = 0; i < len; i++) { @@ -605,83 +590,9 @@ static inline void i2c_ll_set_filter(i2c_dev_t *hw, uint8_t filter_num) * * @return The hardware filter configuration */ -static inline uint8_t i2c_ll_get_filter(i2c_dev_t *hw) +static inline void i2c_ll_get_filter(i2c_dev_t *hw, uint8_t *filter_conf) { - return hw->filter_cfg.scl_filter_thres; -} - -/** - * @brief Enable I2C master TX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_enable_tx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = ~0; - hw->int_ena.val = I2C_LL_MASTER_TX_INT; -} - -/** - * @brief Enable I2C master RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_enable_rx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = ~0; - hw->int_ena.val = I2C_LL_MASTER_RX_INT; -} - -/** - * @brief Disable I2C master TX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_disable_tx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT); -} - -/** - * @brief Disable I2C master RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_MASTER_RX_INT); -} - -/** - * @brief Clear I2C master TX interrupt status register - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_clr_tx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = I2C_LL_MASTER_TX_INT; -} - -/** - * @brief Clear I2C master RX interrupt status register - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_clr_rx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = I2C_LL_MASTER_RX_INT; + *filter_conf = hw->filter_cfg.scl_filter_thres; } /** @@ -693,6 +604,7 @@ static inline void i2c_ll_master_clr_rx_it(i2c_dev_t *hw) */ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw) { + // fsm_rst is a self cleared bit. hw->ctr.fsm_rst = 1; } @@ -731,32 +643,6 @@ static inline void i2c_ll_set_source_clk(i2c_dev_t *hw, i2c_clock_source_t src_c hw->clk_conf.sclk_sel = (src_clk == I2C_CLK_SRC_RC_FAST) ? 1 : 0; } -/** - * @brief Get I2C master interrupt event - * - * @param hw Beginning address of the peripheral registers - * @param event Pointer to accept the interrupt event - * - * @return None - */ -static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) -{ - i2c_int_status_reg_t int_sts = hw->int_status; - if (int_sts.arbitration_lost_int_st) { - *event = I2C_INTR_EVENT_ARBIT_LOST; - } else if (int_sts.nack_int_st) { - *event = I2C_INTR_EVENT_NACK; - } else if (int_sts.time_out_int_st) { - *event = I2C_INTR_EVENT_TOUT; - } else if (int_sts.end_detect_int_st) { - *event = I2C_INTR_EVENT_END_DET; - } else if (int_sts.trans_complete_int_st) { - *event = I2C_INTR_EVENT_TRANS_DONE; - } else { - *event = I2C_INTR_EVENT_ERR; - } -} - /** * @brief Init I2C master * @@ -775,6 +661,48 @@ static inline void i2c_ll_master_init(i2c_dev_t *hw) hw->ctr.val = ctrl_reg.val; } +/** + * @brief Get I2C interrupt status register address + */ +static inline volatile void *i2c_ll_get_interrupt_status_reg(i2c_dev_t *dev) +{ + return &dev->int_status; +} + +//////////////////////////////////////////Deprecated Functions////////////////////////////////////////////////////////// +/////////////////////////////The following functions are only used by the legacy driver///////////////////////////////// +/////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +// Get the I2C hardware instance +#define I2C_LL_GET_HW(i2c_num) (&I2C0) +// Get the I2C hardware FIFO address +#define I2C_LL_GET_FIFO_ADDR(i2c_num) (I2C_DATA_APB_REG(i2c_num)) +// I2C master TX interrupt bitmap +#define I2C_LL_MASTER_TX_INT (I2C_NACK_INT_ENA_M|I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M) +// I2C master RX interrupt bitmap +#define I2C_LL_MASTER_RX_INT (I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M) +// delay time after rtc_clk swiching on +#define DELAY_RTC_CLK_SWITCH (5) +// I2C max timeout value +#define I2C_LL_MAX_TIMEOUT I2C_TIME_OUT_VALUE + +#define I2C_LL_INTR_MASK (0x3fff) /*!< I2C all interrupt bitmap */ + +/** + * @brief I2C interrupt event + */ +typedef enum { + I2C_INTR_EVENT_ERR, + I2C_INTR_EVENT_ARBIT_LOST, /*!< I2C arbition lost event */ + I2C_INTR_EVENT_NACK, /*!< I2C NACK event */ + I2C_INTR_EVENT_TOUT, /*!< I2C time out event */ + I2C_INTR_EVENT_END_DET, /*!< I2C end detected event */ + I2C_INTR_EVENT_TRANS_DONE, /*!< I2C trans done event */ + I2C_INTR_EVENT_RXFIFO_FULL, /*!< I2C rxfifo full event */ + I2C_INTR_EVENT_TXFIFO_EMPTY, /*!< I2C txfifo empty event */ +} i2c_intr_event_t; + /** * @brief Configure I2C SCL timing * @@ -808,6 +736,84 @@ static inline void i2c_ll_get_scl_clk_timing(i2c_dev_t *hw, int *high_period, in *low_period = hw->scl_low_period.scl_low_period; } +/** + * @brief Get I2C master interrupt event + * + * @param hw Beginning address of the peripheral registers + * @param event Pointer to accept the interrupt event + * + * @return None + */ +__attribute__((always_inline)) +static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) +{ + i2c_int_status_reg_t int_sts = hw->int_status; + if (int_sts.arbitration_lost_int_st) { + *event = I2C_INTR_EVENT_ARBIT_LOST; + } else if (int_sts.nack_int_st) { + *event = I2C_INTR_EVENT_NACK; + } else if (int_sts.time_out_int_st) { + *event = I2C_INTR_EVENT_TOUT; + } else if (int_sts.end_detect_int_st) { + *event = I2C_INTR_EVENT_END_DET; + } else if (int_sts.trans_complete_int_st) { + *event = I2C_INTR_EVENT_TRANS_DONE; + } else { + *event = I2C_INTR_EVENT_ERR; + } +} + +/** + * @brief Enable I2C master TX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_enable_tx_it(i2c_dev_t *hw) +{ + hw->int_clr.val = UINT32_MAX; + hw->int_ena.val = I2C_LL_MASTER_TX_INT; +} + +/** + * @brief Enable I2C master RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_enable_rx_it(i2c_dev_t *hw) +{ + hw->int_clr.val = UINT32_MAX; + hw->int_ena.val = I2C_LL_MASTER_RX_INT; +} + +/** + * @brief Disable I2C master TX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_disable_tx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT); +} + +/** + * @brief Disable I2C master RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +__attribute__((always_inline)) +static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_MASTER_RX_INT); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c2/include/hal/rtc_cntl_ll.h b/components/hal/esp32c2/include/hal/rtc_cntl_ll.h index f98d7994eb..e7ee245713 100644 --- a/components/hal/esp32c2/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32c2/include/hal/rtc_cntl_ll.h @@ -54,6 +54,16 @@ static inline void rtc_cntl_ll_disable_cpu_retention(void) REG_CLR_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); } +static inline void rtc_cntl_ll_reset_system(void) +{ + REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); +} + +static inline void rtc_cntl_ll_reset_cpu(int cpu_no) +{ + REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c2/include/hal/spi_ll.h b/components/hal/esp32c2/include/hal/spi_ll.h index 13f5b6ed8d..ca67e3960a 100644 --- a/components/hal/esp32c2/include/hal/spi_ll.h +++ b/components/hal/esp32c2/include/hal/spi_ll.h @@ -74,6 +74,21 @@ typedef enum { } spi_ll_trans_len_cond_t; FLAG_ATTR(spi_ll_trans_len_cond_t) +// SPI base command in esp32c2 +typedef enum { + /* Slave HD Only */ + SPI_LL_BASE_CMD_HD_WRBUF = 0x01, + SPI_LL_BASE_CMD_HD_RDBUF = 0x02, + SPI_LL_BASE_CMD_HD_WRDMA = 0x03, + SPI_LL_BASE_CMD_HD_RDDMA = 0x04, + SPI_LL_BASE_CMD_HD_SEG_END = 0x05, + SPI_LL_BASE_CMD_HD_EN_QPI = 0x06, + SPI_LL_BASE_CMD_HD_WR_END = 0x07, + SPI_LL_BASE_CMD_HD_INT0 = 0x08, + SPI_LL_BASE_CMD_HD_INT1 = 0x09, + SPI_LL_BASE_CMD_HD_INT2 = 0x0A, +} spi_ll_base_command_t; + /*------------------------------------------------------------------------------ * Control *----------------------------------------------------------------------------*/ @@ -1073,6 +1088,93 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) return hw->slave1.last_addr; } +/** + * Get the base spi command in esp32c2 + * + * @param cmd_t Command value + */ +static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) +{ + uint8_t cmd_base = 0x00; + switch (cmd_t) + { + case SPI_CMD_HD_WRBUF: + cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; + break; + case SPI_CMD_HD_RDBUF: + cmd_base = SPI_LL_BASE_CMD_HD_RDBUF; + break; + case SPI_CMD_HD_WRDMA: + cmd_base = SPI_LL_BASE_CMD_HD_WRDMA; + break; + case SPI_CMD_HD_RDDMA: + cmd_base = SPI_LL_BASE_CMD_HD_RDDMA; + break; + case SPI_CMD_HD_SEG_END: + cmd_base = SPI_LL_BASE_CMD_HD_SEG_END; + break; + case SPI_CMD_HD_EN_QPI: + cmd_base = SPI_LL_BASE_CMD_HD_EN_QPI; + break; + case SPI_CMD_HD_WR_END: + cmd_base = SPI_LL_BASE_CMD_HD_WR_END; + break; + case SPI_CMD_HD_INT0: + cmd_base = SPI_LL_BASE_CMD_HD_INT0; + break; + case SPI_CMD_HD_INT1: + cmd_base = SPI_LL_BASE_CMD_HD_INT1; + break; + case SPI_CMD_HD_INT2: + cmd_base = SPI_LL_BASE_CMD_HD_INT2; + break; + default: + HAL_ASSERT(cmd_base); + } + return cmd_base; +} + +/** + * Get the spi communication command + * + * @param cmd_t Base command value + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode) +{ + uint8_t cmd_base = spi_ll_get_slave_hd_base_command(cmd_t); + uint8_t cmd_mod = 0x00; //CMD:1-bit, ADDR:1-bit, DATA:1-bit + + if (line_mode.data_lines == 2) { + if (line_mode.addr_lines == 2) { + cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit + } else { + cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit + } + } else if (line_mode.data_lines == 4) { + if (line_mode.addr_lines == 4) { + cmd_mod = 0xA0; //CMD:1-bit, ADDR:4-bit, DATA:4-bit + } else { + cmd_mod = 0x20; //CMD:1-bit, ADDR:1-bit, DATA:4-bit + } + } + if (cmd_base == SPI_LL_BASE_CMD_HD_SEG_END || cmd_base == SPI_LL_BASE_CMD_HD_EN_QPI) { + cmd_mod = 0x00; + } + + return cmd_base | cmd_mod; +} + +/** + * Get the dummy bits + * + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode) +{ + return 8; +} + #undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK diff --git a/components/hal/esp32c2/include/hal/timer_ll.h b/components/hal/esp32c2/include/hal/timer_ll.h index 8abd74484d..f77d5fc641 100644 --- a/components/hal/esp32c2/include/hal/timer_ll.h +++ b/components/hal/esp32c2/include/hal/timer_ll.h @@ -44,6 +44,19 @@ static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num, } } +/** + * @brief Enable Timer Group (GPTimer) module clock + * + * @param hw Timer Group register base address + * @param timer_num Timer index in the group + * @param en true to enable, false to disable + */ +static inline void timer_ll_enable_clock(timg_dev_t *hw, uint32_t timer_num, bool en) +{ + (void)timer_num; // only one timer in the group + hw->regclk.timer_clk_is_active = en; +} + /** * @brief Enable alarm event * @@ -115,6 +128,22 @@ static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, b hw->hw_timer[timer_num].config.tx_en = en; } +/** + * @brief Trigger software capture event + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + */ +__attribute__((always_inline)) +static inline void timer_ll_trigger_soft_capture(timg_dev_t *hw, uint32_t timer_num) +{ + hw->hw_timer[timer_num].update.tx_update = 1; + // Timer register is in a different clock domain from Timer hardware logic + // We need to wait for the update to take effect before fetching the count value + while (hw->hw_timer[timer_num].update.tx_update) { + } +} + /** * @brief Get counter value * @@ -126,11 +155,6 @@ static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, b __attribute__((always_inline)) static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer_num) { - hw->hw_timer[timer_num].update.tx_update = 1; - // Timer register is in a different clock domain from Timer hardware logic - // We need to wait for the update to take effect before fetching the count value - while (hw->hw_timer[timer_num].update.tx_update) { - } return ((uint64_t) hw->hw_timer[timer_num].hi.tx_hi << 32) | (hw->hw_timer[timer_num].lo.tx_lo); } diff --git a/components/hal/esp32c2/include/hal/uart_ll.h b/components/hal/esp32c2/include/hal/uart_ll.h index 8d38c0e9e1..eb6752f2d1 100644 --- a/components/hal/esp32c2/include/hal/uart_ll.h +++ b/components/hal/esp32c2/include/hal/uart_ll.h @@ -11,7 +11,6 @@ #pragma once #include "hal/uart_types.h" #include "soc/uart_periph.h" -#include "hal/clk_tree_ll.h" #ifdef __cplusplus extern "C" { @@ -142,38 +141,18 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk) } } -/** - * @brief Get the UART source clock frequency. - * - * @param hw Beginning address of the peripheral registers. - * - * @return Current source clock frequency - */ -static inline uint32_t uart_ll_get_sclk_freq(uart_dev_t *hw) -{ - switch (hw->clk_conf.sclk_sel) { - default: - case 1: - return APB_CLK_FREQ; - case 2: - return RTC_CLK_FREQ; - case 3: - return clk_ll_xtal_load_freq_mhz() * MHZ; - } -} - /** * @brief Configure the baud-rate. * * @param hw Beginning address of the peripheral registers. * @param baud The baud rate to be set. + * @param sclk_freq Frequency of the clock source of UART, in Hz. * * @return None */ -static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud) +static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { #define DIV_UP(a, b) (((a) + (b) - 1) / (b)) - uint32_t sclk_freq = uart_ll_get_sclk_freq(hw); const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits int sclk_div = DIV_UP(sclk_freq, max_div * baud); @@ -190,12 +169,12 @@ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud) * @brief Get the current baud-rate. * * @param hw Beginning address of the peripheral registers. + * @param sclk_freq Frequency of the clock source of UART, in Hz. * * @return The current baudrate */ -static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw) +static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq) { - uint32_t sclk_freq = uart_ll_get_sclk_freq(hw); typeof(hw->clk_div) div_reg = hw->clk_div; return ((sclk_freq << 4)) / (((div_reg.div_int << 4) | div_reg.div_frag) * (hw->clk_conf.sclk_div_num + 1)); } diff --git a/components/hal/esp32c3/include/hal/aes_ll.h b/components/hal/esp32c3/include/hal/aes_ll.h index e18c44e58e..efa7928377 100644 --- a/components/hal/esp32c3/include/hal/aes_ll.h +++ b/components/hal/esp32c3/include/hal/aes_ll.h @@ -1,16 +1,8 @@ -// Copyright 2020-2021 Espressif Systems (Shanghai) CO LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -224,7 +216,7 @@ static inline void aes_ll_interrupt_enable(bool enable) */ static inline void aes_ll_interrupt_clear(void) { - REG_WRITE(AES_INT_CLR_REG, 1); + REG_WRITE(AES_INT_CLEAR_REG, 1); } diff --git a/components/hal/esp32c3/include/hal/gpio_ll.h b/components/hal/esp32c3/include/hal/gpio_ll.h index 2a71eb55ab..fae5f48ca5 100644 --- a/components/hal/esp32c3/include/hal/gpio_ll.h +++ b/components/hal/esp32c3/include/hal/gpio_ll.h @@ -14,6 +14,8 @@ #pragma once +#include +#include #include "soc/soc.h" #include "soc/gpio_periph.h" #include "soc/gpio_struct.h" @@ -21,7 +23,6 @@ #include "soc/usb_serial_jtag_reg.h" #include "hal/gpio_types.h" #include "hal/assert.h" -#include "stdlib.h" #ifdef __cplusplus extern "C" { @@ -49,9 +50,16 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) { - REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); + // The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value + // USB DP pin is default to PU enabled + if (gpio_num == USB_DP_GPIO_NUM) { + SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE); + CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP); + } + REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU); } /** @@ -71,9 +79,10 @@ static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) { - REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); + REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD); } /** @@ -170,9 +179,10 @@ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); + PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); } /** @@ -192,6 +202,7 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_output_disable(gpio_dev_t *hw, uint32_t gpio_num) { hw->enable_w1tc.enable_w1tc = (0x1 << gpio_num); @@ -233,6 +244,22 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num) hw->pin[gpio_num].pad_driver = 1; } +/** + * @brief Select a function for the pin in the IOMUX + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + * @param func Function to assign to the pin + */ +static inline __attribute__((always_inline)) void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func) +{ + // Disable USB Serial JTAG if pins 18 or pins 19 needs to select an IOMUX function + if (gpio_num == 18 || gpio_num == 19) { + CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); + } + PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func); +} + /** * @brief GPIO set output level * @@ -331,7 +358,22 @@ static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw) */ static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw) { - SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD); + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); +} + +/** + * @brief Get deep sleep hold status + * + * @param hw Peripheral GPIO hardware instance address. + * + * @return + * - true deep sleep hold is enabled + * - false deep sleep hold is disabled + */ +__attribute__((always_inline)) +static inline bool gpio_ll_deep_sleep_hold_is_en(gpio_dev_t *hw) +{ + return !GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD) && GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); } /** @@ -364,6 +406,24 @@ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num) } } +/** + * @brief Get digital gpio pad hold status. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + * + * @note caller must ensure that gpio_num is a digital io pad + * + * @return + * - true digital gpio pad is held + * - false digital gpio pad is unheld + */ +__attribute__((always_inline)) +static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num) +{ + return GET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, BIT(gpio_num)); +} + /** * @brief Set pad input to a peripheral signal through the IOMUX. * diff --git a/components/hal/esp32c3/include/hal/i2c_ll.h b/components/hal/esp32c3/include/hal/i2c_ll.h index b796022860..e0a8b69eea 100644 --- a/components/hal/esp32c3/include/hal/i2c_ll.h +++ b/components/hal/esp32c3/include/hal/i2c_ll.h @@ -8,6 +8,7 @@ #pragma once +#include "stdbool.h" #include "hal/misc.h" #include "soc/i2c_periph.h" #include "soc/soc_caps.h" @@ -16,12 +17,12 @@ #include "soc/rtc_cntl_reg.h" #include "soc/clk_tree_defs.h" #include "esp_rom_sys.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { #endif -#define I2C_LL_INTR_MASK (0x3fff) /*!< I2C all interrupt bitmap */ /** * @brief I2C hardware cmd register fields. @@ -39,35 +40,6 @@ typedef union { uint32_t val; } i2c_hw_cmd_t; -/** - * @brief I2C interrupt event - */ -typedef enum { - I2C_INTR_EVENT_ERR, - I2C_INTR_EVENT_ARBIT_LOST, /*!< I2C arbition lost event */ - I2C_INTR_EVENT_NACK, /*!< I2C NACK event */ - I2C_INTR_EVENT_TOUT, /*!< I2C time out event */ - I2C_INTR_EVENT_END_DET, /*!< I2C end detected event */ - I2C_INTR_EVENT_TRANS_DONE, /*!< I2C trans done event */ - I2C_INTR_EVENT_RXFIFO_FULL, /*!< I2C rxfifo full event */ - I2C_INTR_EVENT_TXFIFO_EMPTY, /*!< I2C txfifo empty event */ -} i2c_intr_event_t; - -/** - * @brief Data structure for calculating I2C bus timing. - */ -typedef struct { - uint16_t clkm_div; /*!< I2C core clock devider */ - uint16_t scl_low; /*!< I2C scl low period */ - uint16_t scl_high; /*!< I2C scl hight period */ - uint16_t scl_wait_high; /*!< I2C scl wait_high period */ - uint16_t sda_hold; /*!< I2C scl low period */ - uint16_t sda_sample; /*!< I2C sda sample time */ - uint16_t setup; /*!< I2C start and stop condition setup period */ - uint16_t hold; /*!< I2C start and stop condition hold period */ - uint16_t tout; /*!< I2C bus timeout period */ -} i2c_clk_cal_t; - // I2C operation mode command #define I2C_LL_CMD_RESTART 6 /*!ctr.conf_upgate = 1; @@ -146,7 +122,7 @@ static inline void i2c_ll_update(i2c_dev_t *hw) * * @return None */ -static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_clk_cal_t *bus_cfg) +static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_hal_clk_config_t *bus_cfg) { HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, bus_cfg->clkm_div - 1); /* According to the Technical Reference Manual, the following timings must be subtracted by 1. @@ -220,7 +196,8 @@ static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int hight_period, int lo * * @return None */ -static inline void i2c_ll_clr_intsts_mask(i2c_dev_t *hw, uint32_t mask) +__attribute__((always_inline)) +static inline void i2c_ll_clear_intr_mask(i2c_dev_t *hw, uint32_t mask) { hw->int_clr.val = mask; } @@ -246,6 +223,7 @@ static inline void i2c_ll_enable_intr_mask(i2c_dev_t *hw, uint32_t mask) * * @return None */ +__attribute__((always_inline)) static inline void i2c_ll_disable_intr_mask(i2c_dev_t *hw, uint32_t mask) { hw->int_ena.val &= (~mask); @@ -258,9 +236,10 @@ static inline void i2c_ll_disable_intr_mask(i2c_dev_t *hw, uint32_t mask) * * @return I2C interrupt status */ -static inline uint32_t i2c_ll_get_intsts_mask(i2c_dev_t *hw) +__attribute__((always_inline)) +static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status) { - return hw->int_status.val; + *intr_status = hw->int_status.val; } /** @@ -477,9 +456,10 @@ static inline bool i2c_ll_is_master_mode(i2c_dev_t *hw) * * @return RxFIFO readable length */ -static inline uint32_t i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw) +__attribute__((always_inline)) +static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length) { - return hw->sr.rx_fifo_cnt; + *length = hw->sr.rx_fifo_cnt; } /** @@ -489,9 +469,10 @@ static inline uint32_t i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw) * * @return TxFIFO writable length */ -static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw) +__attribute__((always_inline)) +static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length) { - return SOC_I2C_FIFO_LEN - hw->sr.tx_fifo_cnt; + *length = SOC_I2C_FIFO_LEN - hw->sr.tx_fifo_cnt; } /** @@ -501,9 +482,9 @@ static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw) * * @return The I2C timeout value */ -static inline uint32_t i2c_ll_get_tout(i2c_dev_t *hw) +static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout) { - return hw->timeout.time_out_value; + *timeout = hw->timeout.time_out_value; } /** @@ -572,7 +553,8 @@ static inline void i2c_ll_get_scl_timing(i2c_dev_t *hw, int *high_period, int *l * * @return None. */ -static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) +__attribute__((always_inline)) +static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len) { for (int i = 0; i< len; i++) { HAL_FORCE_MODIFY_U32_REG_FIELD(hw->fifo_data, data, ptr[i]); @@ -588,6 +570,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) * * @return None */ +__attribute__((always_inline)) static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) { for(int i = 0; i < len; i++) { @@ -624,156 +607,12 @@ static inline void i2c_ll_set_filter(i2c_dev_t *hw, uint8_t filter_num) * * @return The hardware filter configuration */ -static inline uint8_t i2c_ll_get_filter(i2c_dev_t *hw) +static inline void i2c_ll_get_filter(i2c_dev_t *hw, uint8_t *filter_conf) { - return hw->filter_cfg.scl_thres; + *filter_conf = hw->filter_cfg.scl_thres; } -/** - * @brief Enable I2C master TX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_enable_tx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = ~0; - hw->int_ena.val = I2C_LL_MASTER_TX_INT; -} -/** - * @brief Enable I2C master RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_enable_rx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = ~0; - hw->int_ena.val = I2C_LL_MASTER_RX_INT; -} - -/** - * @brief Disable I2C master TX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_disable_tx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT); -} - -/** - * @brief Disable I2C master RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_MASTER_RX_INT); -} - -/** - * @brief Clear I2C master TX interrupt status register - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_clr_tx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = I2C_LL_MASTER_TX_INT; -} - -/** - * @brief Clear I2C master RX interrupt status register - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_clr_rx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = I2C_LL_MASTER_RX_INT; -} - -/** - * @brief - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_enable_tx_it(i2c_dev_t *hw) -{ - hw->int_ena.val |= I2C_LL_SLAVE_TX_INT; -} - -/** - * @brief Enable I2C slave RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_enable_rx_it(i2c_dev_t *hw) -{ - hw->int_ena.val |= I2C_LL_SLAVE_RX_INT; -} - -/** - * @brief Disable I2C slave TX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_disable_tx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_SLAVE_TX_INT); -} - -/** - * @brief Disable I2C slave RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT); -} - -/** - * @brief Clear I2C slave TX interrupt status register - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_clr_tx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = I2C_LL_SLAVE_TX_INT; -} - -/** - * @brief Clear I2C slave RX interrupt status register. - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_clr_rx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = I2C_LL_SLAVE_RX_INT; -} /** * @brief Reste I2C master FSM. When the master FSM is stuck, call this function to reset the FSM @@ -784,6 +623,7 @@ static inline void i2c_ll_slave_clr_rx_it(i2c_dev_t *hw) */ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw) { + // fsm_rst is a self cleared bit. hw->ctr.fsm_rst = 1; } @@ -822,53 +662,7 @@ static inline void i2c_ll_set_source_clk(i2c_dev_t *hw, i2c_clock_source_t src_c hw->clk_conf.sclk_sel = (src_clk == I2C_CLK_SRC_RC_FAST) ? 1 : 0; } -/** - * @brief Get I2C master interrupt event - * - * @param hw Beginning address of the peripheral registers - * @param event Pointer to accept the interrupt event - * - * @return None - */ -static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) -{ - typeof(hw->int_status) int_sts = hw->int_status; - if (int_sts.arbitration_lost) { - *event = I2C_INTR_EVENT_ARBIT_LOST; - } else if (int_sts.nack) { - *event = I2C_INTR_EVENT_NACK; - } else if (int_sts.time_out) { - *event = I2C_INTR_EVENT_TOUT; - } else if (int_sts.end_detect) { - *event = I2C_INTR_EVENT_END_DET; - } else if (int_sts.trans_complete) { - *event = I2C_INTR_EVENT_TRANS_DONE; - } else { - *event = I2C_INTR_EVENT_ERR; - } -} -/** - * @brief Get I2C slave interrupt event - * - * @param hw Beginning address of the peripheral registers - * @param event Pointer to accept the interrupt event - * - * @return None - */ -static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) -{ - typeof(hw->int_status) int_sts = hw->int_status; - if (int_sts.tx_fifo_wm) { - *event = I2C_INTR_EVENT_TXFIFO_EMPTY; - } else if (int_sts.trans_complete) { - *event = I2C_INTR_EVENT_TRANS_DONE; - } else if (int_sts.rx_fifo_wm) { - *event = I2C_INTR_EVENT_RXFIFO_FULL; - } else { - *event = I2C_INTR_EVENT_ERR; - } -} /** * @brief Init I2C master @@ -902,10 +696,64 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw) ctrl_reg.sda_force_out = 1; ctrl_reg.scl_force_out = 1; hw->ctr.val = ctrl_reg.val; - hw->ctr.slv_tx_auto_start_en = 1; hw->fifo_conf.fifo_addr_cfg_en = 0; } +/** + * @brief Set whether slave should auto start, or only start with start signal from master + * + * @param hw Beginning address of the peripheral registers + * @param slv_ex_auto_en 1 if slave auto start data transaction, otherwise, 0. + */ +static inline void i2c_ll_slave_tx_auto_start_en(i2c_dev_t *hw, bool slv_ex_auto_en) +{ + hw->ctr.slv_tx_auto_start_en = slv_ex_auto_en; +} + +/** + * @brief Get I2C interrupt status register address + */ +static inline volatile void *i2c_ll_get_interrupt_status_reg(i2c_dev_t *dev) +{ + return &dev->int_status; +} + +//////////////////////////////////////////Deprecated Functions////////////////////////////////////////////////////////// +/////////////////////////////The following functions are only used by the legacy driver///////////////////////////////// +/////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +// Get the I2C hardware instance +#define I2C_LL_GET_HW(i2c_num) (&I2C0) +// Get the I2C hardware FIFO address +#define I2C_LL_GET_FIFO_ADDR(i2c_num) (I2C_DATA_APB_REG(i2c_num)) +// I2C master TX interrupt bitmap +#define I2C_LL_MASTER_TX_INT (I2C_NACK_INT_ENA_M|I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M) +// I2C master RX interrupt bitmap +#define I2C_LL_MASTER_RX_INT (I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M) +// I2C slave TX interrupt bitmap +#define I2C_LL_SLAVE_TX_INT (I2C_TXFIFO_WM_INT_ENA_M) +// I2C slave RX interrupt bitmap +#define I2C_LL_SLAVE_RX_INT (I2C_RXFIFO_WM_INT_ENA_M | I2C_TRANS_COMPLETE_INT_ENA_M) +// I2C max timeout value +#define I2C_LL_MAX_TIMEOUT I2C_TIME_OUT_REG_V + +#define I2C_LL_INTR_MASK (0xffff) /*!< I2C all interrupt bitmap */ + +/** + * @brief I2C interrupt event + */ +typedef enum { + I2C_INTR_EVENT_ERR, + I2C_INTR_EVENT_ARBIT_LOST, /*!< I2C arbition lost event */ + I2C_INTR_EVENT_NACK, /*!< I2C NACK event */ + I2C_INTR_EVENT_TOUT, /*!< I2C time out event */ + I2C_INTR_EVENT_END_DET, /*!< I2C end detected event */ + I2C_INTR_EVENT_TRANS_DONE, /*!< I2C trans done event */ + I2C_INTR_EVENT_RXFIFO_FULL, /*!< I2C rxfifo full event */ + I2C_INTR_EVENT_TXFIFO_EMPTY, /*!< I2C txfifo empty event */ +} i2c_intr_event_t; + /** * @brief Configure I2C SCL timing * @@ -939,6 +787,157 @@ static inline void i2c_ll_get_scl_clk_timing(i2c_dev_t *hw, int *high_period, in *low_period = hw->scl_low_period.period; } +/** + * @brief Get I2C master interrupt event + * + * @param hw Beginning address of the peripheral registers + * @param event Pointer to accept the interrupt event + * + * @return None + */ +__attribute__((always_inline)) +static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) +{ + typeof(hw->int_status) int_sts = hw->int_status; + if (int_sts.arbitration_lost) { + *event = I2C_INTR_EVENT_ARBIT_LOST; + } else if (int_sts.nack) { + *event = I2C_INTR_EVENT_NACK; + } else if (int_sts.time_out||int_sts.scl_st_to||int_sts.scl_main_st_to) { + *event = I2C_INTR_EVENT_TOUT; + } else if (int_sts.end_detect) { + *event = I2C_INTR_EVENT_END_DET; + } else if (int_sts.trans_complete) { + *event = I2C_INTR_EVENT_TRANS_DONE; + } else { + *event = I2C_INTR_EVENT_ERR; + } +} + +/** + * @brief Get I2C slave interrupt event + * + * @param hw Beginning address of the peripheral registers + * @param event Pointer to accept the interrupt event + * + * @return None + */ +__attribute__((always_inline)) +static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) +{ + typeof(hw->int_status) int_sts = hw->int_status; + if (int_sts.tx_fifo_wm) { + *event = I2C_INTR_EVENT_TXFIFO_EMPTY; + } else if (int_sts.trans_complete) { + *event = I2C_INTR_EVENT_TRANS_DONE; + } else if (int_sts.rx_fifo_wm) { + *event = I2C_INTR_EVENT_RXFIFO_FULL; + } else { + *event = I2C_INTR_EVENT_ERR; + } +} + +/** + * @brief Enable I2C master TX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_enable_tx_it(i2c_dev_t *hw) +{ + hw->int_clr.val = UINT32_MAX; + hw->int_ena.val = I2C_LL_MASTER_TX_INT; +} + +/** + * @brief Enable I2C master RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_enable_rx_it(i2c_dev_t *hw) +{ + hw->int_clr.val = UINT32_MAX; + hw->int_ena.val = I2C_LL_MASTER_RX_INT; +} + +/** + * @brief Disable I2C master TX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_disable_tx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT); +} + +/** + * @brief Disable I2C master RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +__attribute__((always_inline)) +static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_MASTER_RX_INT); +} + +/** + * @brief + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_slave_enable_tx_it(i2c_dev_t *hw) +{ + hw->int_ena.val |= I2C_LL_SLAVE_TX_INT; +} + +/** + * @brief Enable I2C slave RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_slave_enable_rx_it(i2c_dev_t *hw) +{ + hw->int_ena.val |= I2C_LL_SLAVE_RX_INT; +} + +/** + * @brief Disable I2C slave TX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +__attribute__((always_inline)) +static inline void i2c_ll_slave_disable_tx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_SLAVE_TX_INT); +} + +/** + * @brief Disable I2C slave RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT); +} + + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c3/include/hal/i2s_ll.h b/components/hal/esp32c3/include/hal/i2s_ll.h index 579f356768..4448f0ef95 100644 --- a/components/hal/esp32c3/include/hal/i2s_ll.h +++ b/components/hal/esp32c3/include/hal/i2s_ll.h @@ -14,6 +14,7 @@ #pragma once #include #include "hal/misc.h" +#include "hal/assert.h" #include "soc/i2s_periph.h" #include "soc/i2s_struct.h" #include "hal/i2s_types.h" @@ -23,11 +24,10 @@ extern "C" { #endif -#define I2S_LL_GET_HW(num) (&I2S0) +#define I2S_LL_GET_HW(num) (((num) == 0)? (&I2S0) : NULL) #define I2S_LL_TDM_CH_MASK (0xffff) #define I2S_LL_PDM_BCK_FACTOR (64) -#define I2S_LL_BASE_CLK (2*APB_CLK_FREQ) #define I2S_LL_MCLK_DIVIDER_BIT_WIDTH (9) #define I2S_LL_MCLK_DIVIDER_MAX ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1) @@ -193,18 +193,40 @@ static inline void i2s_ll_rx_reset_fifo(i2s_dev_t *hw) */ static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src) { - hw->tx_clkm_conf.tx_clk_sel = 2; + switch (src) + { + case I2S_CLK_SRC_XTAL: + hw->tx_clkm_conf.tx_clk_sel = 0; + break; + case I2S_CLK_SRC_PLL_160M: + hw->tx_clkm_conf.tx_clk_sel = 2; + break; + default: + HAL_ASSERT(false && "unsupported clock source"); + break; + } } /** * @brief Set RX source clock * * @param hw Peripheral I2S hardware instance address. - * @param src I2S source clock, ESP32-C3 only support `I2S_CLK_SRC_PLL_160M` + * @param src I2S source clock */ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src) { - hw->rx_clkm_conf.rx_clk_sel = 2; + switch (src) + { + case I2S_CLK_SRC_XTAL: + hw->rx_clkm_conf.rx_clk_sel = 0; + break; + case I2S_CLK_SRC_PLL_160M: + hw->rx_clkm_conf.rx_clk_sel = 2; + break; + default: + HAL_ASSERT(false && "unsupported clock source"); + break; + } } /** @@ -256,7 +278,7 @@ static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t * @brief Configure I2S TX module clock divider * * @param hw Peripheral I2S hardware instance address. - * @param sclk system clock, 0 means use apll + * @param sclk system clock * @param mclk module clock * @param mclk_div integer part of the division from sclk to mclk */ diff --git a/components/hal/esp32c3/include/hal/rmt_ll.h b/components/hal/esp32c3/include/hal/rmt_ll.h index 177e4ecea8..7b8106dfe0 100644 --- a/components/hal/esp32c3/include/hal/rmt_ll.h +++ b/components/hal/esp32c3/include/hal/rmt_ll.h @@ -90,7 +90,6 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, // Formula: rmt_sclk = module_clock_src / (1 + div_num + div_a / div_b) (void)channel; // the source clock is set for all channels HAL_ASSERT(divider_integral >= 1); - dev->sys_conf.sclk_active = 0; HAL_FORCE_MODIFY_U32_REG_FIELD(dev->sys_conf, sclk_div_num, divider_integral - 1); dev->sys_conf.sclk_div_a = divider_numerator; dev->sys_conf.sclk_div_b = divider_denominator; @@ -108,7 +107,17 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, HAL_ASSERT(false && "unsupported RMT clock source"); break; } - dev->sys_conf.sclk_active = 1; +} + +/** + * @brief Enable RMT peripheral source clock + * + * @param dev Peripheral instance address + * @param en True to enable, False to disable + */ +static inline void rmt_ll_enable_group_clock(rmt_dev_t *dev, bool en) +{ + dev->sys_conf.sclk_active = en; } ////////////////////////////////////////TX Channel Specific///////////////////////////////////////////////////////////// @@ -684,48 +693,57 @@ static inline uint32_t rmt_ll_rx_get_interrupt_status(rmt_dev_t *dev, uint32_t c /////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_status_word(rmt_dev_t *dev, uint32_t channel) { return dev->tx_status[channel].val; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_status_word(rmt_dev_t *dev, uint32_t channel) { return dev->rx_status[channel].val; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->tx_conf[channel], div_cnt); return div == 0 ? 256 : div; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->rx_conf[channel].conf0, div_cnt); return div == 0 ? 256 : div; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel) { return dev->rx_conf[channel].conf0.idle_thres; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) { return dev->tx_conf[channel].mem_size; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) { return dev->rx_conf[channel].conf0.mem_size; } +__attribute__((always_inline)) static inline bool rmt_ll_tx_is_loop_enabled(rmt_dev_t *dev, uint32_t channel) { return dev->tx_conf[channel].tx_conti_mode; } +__attribute__((always_inline)) static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel) { rmt_clock_source_t clk_src = RMT_CLK_SRC_APB; @@ -743,11 +761,13 @@ static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint return clk_src; } +__attribute__((always_inline)) static inline bool rmt_ll_tx_is_idle_enabled(rmt_dev_t *dev, uint32_t channel) { return dev->tx_conf[channel].idle_out_en; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel) { return dev->tx_conf[channel].idle_out_lv; @@ -761,46 +781,55 @@ static inline bool rmt_ll_is_mem_powered_down(rmt_dev_t *dev) return (dev->sys_conf.mem_force_pd) || !(dev->sys_conf.mem_force_pu); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_mem_owner(rmt_dev_t *dev, uint32_t channel) { return dev->rx_conf[channel].conf1.mem_owner; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_limit(rmt_dev_t *dev, uint32_t channel) { return dev->rx_lim[channel].rx_lim; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev) { return dev->int_st.val & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 2) & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_err_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 4) & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_err_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 6) & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 8) & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_thres_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 10) & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_loop_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 12) & 0x03; diff --git a/components/hal/esp32c3/include/hal/rtc_cntl_ll.h b/components/hal/esp32c3/include/hal/rtc_cntl_ll.h index 9f298bbf09..7e1b553422 100644 --- a/components/hal/esp32c3/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32c3/include/hal/rtc_cntl_ll.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -68,6 +60,16 @@ static inline void rtc_cntl_ll_disable_cpu_retention(void) REG_CLR_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); } +static inline void rtc_cntl_ll_reset_system(void) +{ + REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); +} + +static inline void rtc_cntl_ll_reset_cpu(int cpu_no) +{ + REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c3/include/hal/spi_ll.h b/components/hal/esp32c3/include/hal/spi_ll.h index 01070e918f..78b58de6c4 100644 --- a/components/hal/esp32c3/include/hal/spi_ll.h +++ b/components/hal/esp32c3/include/hal/spi_ll.h @@ -74,6 +74,21 @@ typedef enum { } spi_ll_trans_len_cond_t; FLAG_ATTR(spi_ll_trans_len_cond_t) +// SPI base command in esp32c3 +typedef enum { + /* Slave HD Only */ + SPI_LL_BASE_CMD_HD_WRBUF = 0x01, + SPI_LL_BASE_CMD_HD_RDBUF = 0x02, + SPI_LL_BASE_CMD_HD_WRDMA = 0x03, + SPI_LL_BASE_CMD_HD_RDDMA = 0x04, + SPI_LL_BASE_CMD_HD_SEG_END = 0x05, + SPI_LL_BASE_CMD_HD_EN_QPI = 0x06, + SPI_LL_BASE_CMD_HD_WR_END = 0x07, + SPI_LL_BASE_CMD_HD_INT0 = 0x08, + SPI_LL_BASE_CMD_HD_INT1 = 0x09, + SPI_LL_BASE_CMD_HD_INT2 = 0x0A, +} spi_ll_base_command_t; + /*------------------------------------------------------------------------------ * Control *----------------------------------------------------------------------------*/ @@ -1076,6 +1091,93 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) #undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK +/** + * Get the base spi command in esp32c3 + * + * @param cmd_t Command value + */ +static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) +{ + uint8_t cmd_base = 0x00; + switch (cmd_t) + { + case SPI_CMD_HD_WRBUF: + cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; + break; + case SPI_CMD_HD_RDBUF: + cmd_base = SPI_LL_BASE_CMD_HD_RDBUF; + break; + case SPI_CMD_HD_WRDMA: + cmd_base = SPI_LL_BASE_CMD_HD_WRDMA; + break; + case SPI_CMD_HD_RDDMA: + cmd_base = SPI_LL_BASE_CMD_HD_RDDMA; + break; + case SPI_CMD_HD_SEG_END: + cmd_base = SPI_LL_BASE_CMD_HD_SEG_END; + break; + case SPI_CMD_HD_EN_QPI: + cmd_base = SPI_LL_BASE_CMD_HD_EN_QPI; + break; + case SPI_CMD_HD_WR_END: + cmd_base = SPI_LL_BASE_CMD_HD_WR_END; + break; + case SPI_CMD_HD_INT0: + cmd_base = SPI_LL_BASE_CMD_HD_INT0; + break; + case SPI_CMD_HD_INT1: + cmd_base = SPI_LL_BASE_CMD_HD_INT1; + break; + case SPI_CMD_HD_INT2: + cmd_base = SPI_LL_BASE_CMD_HD_INT2; + break; + default: + HAL_ASSERT(cmd_base); + } + return cmd_base; +} + +/** + * Get the spi communication command + * + * @param cmd_t Base command value + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode) +{ + uint8_t cmd_base = spi_ll_get_slave_hd_base_command(cmd_t); + uint8_t cmd_mod = 0x00; //CMD:1-bit, ADDR:1-bit, DATA:1-bit + + if (line_mode.data_lines == 2) { + if (line_mode.addr_lines == 2) { + cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit + } else { + cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit + } + } else if (line_mode.data_lines == 4) { + if (line_mode.addr_lines == 4) { + cmd_mod = 0xA0; //CMD:1-bit, ADDR:4-bit, DATA:4-bit + } else { + cmd_mod = 0x20; //CMD:1-bit, ADDR:1-bit, DATA:4-bit + } + } + if (cmd_base == SPI_LL_BASE_CMD_HD_SEG_END || cmd_base == SPI_LL_BASE_CMD_HD_EN_QPI) { + cmd_mod = 0x00; + } + + return cmd_base | cmd_mod; +} + +/** + * Get the dummy bits + * + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode) +{ + return 8; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c3/include/hal/timer_ll.h b/components/hal/esp32c3/include/hal/timer_ll.h index d55a4116fe..2c9ed9395d 100644 --- a/components/hal/esp32c3/include/hal/timer_ll.h +++ b/components/hal/esp32c3/include/hal/timer_ll.h @@ -44,6 +44,19 @@ static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num, } } +/** + * @brief Enable Timer Group (GPTimer) module clock + * + * @param hw Timer Group register base address + * @param timer_num Timer index in the group + * @param en true to enable, false to disable + */ +static inline void timer_ll_enable_clock(timg_dev_t *hw, uint32_t timer_num, bool en) +{ + (void)timer_num; // only one timer in the group + hw->regclk.timer_clk_is_active = en; +} + /** * @brief Enable alarm event * @@ -115,6 +128,22 @@ static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, b hw->hw_timer[timer_num].config.tx_en = en; } +/** + * @brief Trigger software capture event + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + */ +__attribute__((always_inline)) +static inline void timer_ll_trigger_soft_capture(timg_dev_t *hw, uint32_t timer_num) +{ + hw->hw_timer[timer_num].update.tx_update = 1; + // Timer register is in a different clock domain from Timer hardware logic + // We need to wait for the update to take effect before fetching the count value + while (hw->hw_timer[timer_num].update.tx_update) { + } +} + /** * @brief Get counter value * @@ -126,11 +155,6 @@ static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, b __attribute__((always_inline)) static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer_num) { - hw->hw_timer[timer_num].update.tx_update = 1; - // Timer register is in a different clock domain from Timer hardware logic - // We need to wait for the update to take effect before fetching the count value - while (hw->hw_timer[timer_num].update.tx_update) { - } return ((uint64_t) hw->hw_timer[timer_num].hi.tx_hi << 32) | (hw->hw_timer[timer_num].lo.tx_lo); } diff --git a/components/hal/esp32c3/include/hal/uart_ll.h b/components/hal/esp32c3/include/hal/uart_ll.h index 7757929adb..067c79ce37 100644 --- a/components/hal/esp32c3/include/hal/uart_ll.h +++ b/components/hal/esp32c3/include/hal/uart_ll.h @@ -144,38 +144,18 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk) } } -/** - * @brief Get the UART source clock frequency. - * - * @param hw Beginning address of the peripheral registers. - * - * @return Current source clock frequency - */ -static inline uint32_t uart_ll_get_sclk_freq(uart_dev_t *hw) -{ - switch (hw->clk_conf.sclk_sel) { - default: - case 1: - return APB_CLK_FREQ; - case 2: - return RTC_CLK_FREQ; - case 3: - return XTAL_CLK_FREQ; - } -} - /** * @brief Configure the baud-rate. * * @param hw Beginning address of the peripheral registers. * @param baud The baud rate to be set. + * @param sclk_freq Frequency of the clock source of UART, in Hz. * * @return None */ -static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud) +static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { #define DIV_UP(a, b) (((a) + (b) - 1) / (b)) - uint32_t sclk_freq = uart_ll_get_sclk_freq(hw); const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits int sclk_div = DIV_UP(sclk_freq, max_div * baud); @@ -192,12 +172,12 @@ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud) * @brief Get the current baud-rate. * * @param hw Beginning address of the peripheral registers. + * @param sclk_freq Frequency of the clock source of UART, in Hz. * * @return The current baudrate */ -static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw) +static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq) { - uint32_t sclk_freq = uart_ll_get_sclk_freq(hw); typeof(hw->clk_div) div_reg = hw->clk_div; return ((sclk_freq << 4)) / (((div_reg.div_int << 4) | div_reg.div_frag) * (HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1)); } diff --git a/components/hal/esp32c3/include/hal/usb_phy_ll.h b/components/hal/esp32c3/include/hal/usb_phy_ll.h new file mode 100644 index 0000000000..40d4cd1800 --- /dev/null +++ b/components/hal/esp32c3/include/hal/usb_phy_ll.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc/usb_serial_jtag_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Configures the internal PHY for USB_Serial_JTAG + * + * @param hw Start address of the USB Serial_JTAG registers + */ +static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw) +{ + // USB_Serial_JTAG use internal PHY + hw->conf0.phy_sel = 0; + // Disable software control USB D+ D- pullup pulldown (Device FS: dp_pullup = 1) + hw->conf0.pad_pull_override = 0; + // Enable USB D+ pullup + hw->conf0.dp_pullup = 1; + // Enable USB pad function + hw->conf0.usb_pad_enable = 1; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/brownout_hal.c b/components/hal/esp32c6/brownout_hal.c new file mode 100644 index 0000000000..31d98e5264 --- /dev/null +++ b/components/hal/esp32c6/brownout_hal.c @@ -0,0 +1,26 @@ + +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "hal/brownout_hal.h" +#include "esp_attr.h" +#include "hal/regi2c_ctrl.h" +#include "soc/regi2c_brownout.h" + +void brownout_hal_config(const brownout_hal_config_t *cfg) +{ + // TODO: IDF-5711 +} + +void brownout_hal_intr_enable(bool enable) +{ + // TODO: IDF-5711 +} + +IRAM_ATTR void brownout_hal_intr_clear(void) +{ + // TODO: IDF-5711 +} diff --git a/components/hal/esp32c6/efuse_hal.c b/components/hal/esp32c6/efuse_hal.c new file mode 100644 index 0000000000..02a3486fab --- /dev/null +++ b/components/hal/esp32c6/efuse_hal.c @@ -0,0 +1,94 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include +#include "soc/soc_caps.h" +#include "hal/assert.h" +#include "hal/efuse_hal.h" +#include "hal/efuse_ll.h" + +#define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x08 << (4 * (block)))) +#define ESP_EFUSE_BLOCK_ERROR_NUM_BITS(error_reg, block) ((error_reg) & (0x07 << (4 * (block)))) + +uint32_t efuse_hal_get_major_chip_version(void) +{ + return efuse_ll_get_chip_wafer_version_major(); +} + +uint32_t efuse_hal_get_minor_chip_version(void) +{ + return efuse_ll_get_chip_wafer_version_minor(); +} + +/******************* eFuse control functions *************************/ + +void efuse_hal_set_timing(uint32_t apb_freq_hz) +{ + (void) apb_freq_hz; + efuse_ll_set_pwr_off_num(0x190); +} + +void efuse_hal_read(void) +{ + efuse_hal_set_timing(0); + + efuse_ll_set_conf_read_op_code(); + efuse_ll_set_read_cmd(); + + while (efuse_ll_get_read_cmd() != 0) { } + /*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/ + while (efuse_ll_get_read_cmd() != 0) { } +} + +void efuse_hal_clear_program_registers(void) +{ + ets_efuse_clear_program_registers(); +} + +void efuse_hal_program(uint32_t block) +{ + efuse_hal_set_timing(0); + + efuse_ll_set_conf_write_op_code(); + efuse_ll_set_pgm_cmd(block); + + while (efuse_ll_get_pgm_cmd() != 0) { } + + efuse_hal_clear_program_registers(); + efuse_hal_read(); +} + +void efuse_hal_rs_calculate(const void *data, void *rs_values) +{ + ets_efuse_rs_calculate(data, rs_values); +} + +/******************* eFuse control functions *************************/ + +bool efuse_hal_is_coding_error_in_block(unsigned block) +{ + if (block == 0) { + for (unsigned i = 0; i < 5; i++) { + if (REG_READ(EFUSE_RD_REPEAT_ERR0_REG + i * 4)) { + return true; + } + } + } else if (block <= 10) { + // The order of error in these regs is different only for the C3 chip. + // Fail bit (mask=0x8): + // EFUSE_RD_RS_ERR0_REG: (hi) BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1, ------ (low) + // EFUSE_RD_RS_ERR1_REG: BLOCK9, BLOCK8 + // Error num bits (mask=0x7): + // EFUSE_RD_RS_ERR0_REG: (hi) BLOCK8, BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1 (low) + // EFUSE_RD_RS_ERR1_REG: BLOCK10, BLOCK9 + // BLOCK10 is not presented in the error regs. + uint32_t err_fail_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4); + uint32_t err_num_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + ((block - 1) / 8) * 4); + return (ESP_EFUSE_BLOCK_ERROR_BITS(err_fail_reg, block % 8) != 0) || (ESP_EFUSE_BLOCK_ERROR_NUM_BITS(err_num_reg, (block - 1) % 8) != 0); + } + return false; +} diff --git a/components/hal/esp32c6/include/hal/cache_ll.h b/components/hal/esp32c6/include/hal/cache_ll.h new file mode 100644 index 0000000000..6fd9a99376 --- /dev/null +++ b/components/hal/esp32c6/include/hal/cache_ll.h @@ -0,0 +1,197 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for Cache register operations + +#pragma once + +#include "soc/extmem_reg.h" +#include "soc/ext_mem_defs.h" +#include "hal/cache_types.h" +#include "hal/assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0 +#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0 + +#define CACHE_LL_L1_ACCESS_EVENT_MASK (0x3f) +#define CACHE_LL_L1_ACCESS_EVENT_DBUS_WR_IC (1<<5) +#define CACHE_LL_L1_ACCESS_EVENT_DBUS_REJECT (1<<4) +#define CACHE_LL_L1_ACCESS_EVENT_DBUS_ACS_MSK_IC (1<<3) +#define CACHE_LL_L1_ACCESS_EVENT_IBUS_REJECT (1<<2) +#define CACHE_LL_L1_ACCESS_EVENT_IBUS_WR_IC (1<<1) +#define CACHE_LL_L1_ACCESS_EVENT_IBUS_ACS_MSK_IC (1<<0) + +#define CACHE_LL_L1_ILG_EVENT_MASK (0x23) +#define CACHE_LL_L1_ILG_EVENT_MMU_ENTRY_FAULT (1<<5) +#define CACHE_LL_L1_ILG_EVENT_PRELOAD_OP_FAULT (1<<1) +#define CACHE_LL_L1_ILG_EVENT_SYNC_OP_FAULT (1<<0) + + +/** + * @brief Get the buses of a particular cache that are mapped to a virtual address range + * + * External virtual address can only be accessed when the involved cache buses are enabled. + * This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside. + * + * @param cache_id cache ID (when l1 cache is per core) + * @param vaddr_start virtual address start + * @param len vaddr length + */ +#if !BOOTLOADER_BUILD +__attribute__((always_inline)) +#endif +static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len) +{ + HAL_ASSERT(cache_id == 0); + cache_bus_mask_t mask = 0; + + uint32_t vaddr_end = vaddr_start + len - 1; + if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH(CONFIG_MMU_PAGE_SIZE)) { + mask |= CACHE_BUS_IBUS0; + } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH(CONFIG_MMU_PAGE_SIZE)) { + mask |= CACHE_BUS_DBUS0; + } else { + HAL_ASSERT(0); //Out of region + } + + return mask; +} + +/** + * Enable the Cache Buses + * + * @param cache_id cache ID (when l1 cache is per core) + * @param mask To know which buses should be enabled + */ +#if !BOOTLOADER_BUILD +__attribute__((always_inline)) +#endif +static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) +{ + HAL_ASSERT(cache_id == 0); + //On esp32c3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first + HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); + + uint32_t ibus_mask = 0; + ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_DCACHE_SHUT_DBUS0 : 0; + REG_CLR_BIT(EXTMEM_ICACHE_CTRL_REG, ibus_mask); + + uint32_t dbus_mask = 0; + dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_DBUS1 : 0; + REG_CLR_BIT(EXTMEM_ICACHE_CTRL_REG, dbus_mask); +} + +/** + * Disable the Cache Buses + * + * @param cache_id cache ID (when l1 cache is per core) + * @param mask To know which buses should be disabled + */ +__attribute__((always_inline)) +static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) +{ + HAL_ASSERT(cache_id == 0); + //On esp32c3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first + HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); + + uint32_t ibus_mask = 0; + ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_DCACHE_SHUT_DBUS0 : 0; + REG_SET_BIT(EXTMEM_ICACHE_CTRL_REG, ibus_mask); + + uint32_t dbus_mask = 0; + dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_DBUS1 : 0; + REG_SET_BIT(EXTMEM_ICACHE_CTRL_REG, dbus_mask); +} + +/*------------------------------------------------------------------------------ + * Interrupt + *----------------------------------------------------------------------------*/ +/** + * @brief Enable Cache access error interrupt + * + * @param cache_id Cache ID, not used on C3. For compabitlity + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask) +{ + // TODO: IDF-5656 + // SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG, mask); +} + +/** + * @brief Clear Cache access error interrupt status + * + * @param cache_id Cache ID, not used on C3. For compabitlity + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask) +{ + // TODO: IDF-5656 + // SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG, mask); +} + +/** + * @brief Get Cache access error interrupt status + * + * @param cache_id Cache ID, not used on C3. For compabitlity + * @param mask Interrupt mask + * + * @return Status mask + */ +static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask) +{ + // TODO: IDF-5656 + // return GET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG, mask); + return 0; +} + +/** + * @brief Enable Cache illegal error interrupt + * + * @param cache_id Cache ID, not used on C3. For compabitlity + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_enable_illegal_error_intr(uint32_t cache_id, uint32_t mask) +{ + // TODO: IDF-5656 + // SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG, mask); +} + +/** + * @brief Clear Cache illegal error interrupt status + * + * @param cache_id Cache ID, not used on C3. For compabitlity + * @param mask Interrupt mask + */ +static inline void cache_ll_l1_clear_illegal_error_intr(uint32_t cache_id, uint32_t mask) +{ + // TODO: IDF-5656 + // SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG, mask); +} + +/** + * @brief Get Cache illegal error interrupt status + * + * @param cache_id Cache ID, not used on C3. For compabitlity + * @param mask Interrupt mask + * + * @return Status mask + */ +static inline uint32_t cache_ll_l1_get_illegal_error_intr_status(uint32_t cache_id, uint32_t mask) +{ + // TODO: IDF-5656 + // return GET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ST_REG, mask); + return 0; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/clk_gate_ll.h b/components/hal/esp32c6/include/hal/clk_gate_ll.h new file mode 100644 index 0000000000..50fb6b6795 --- /dev/null +++ b/components/hal/esp32c6/include/hal/clk_gate_ll.h @@ -0,0 +1,330 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/periph_defs.h" +#include "soc/pcr_reg.h" +#include "soc/dport_access.h" +#include "esp_attr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph) +{ // TODO: IDF-5713 + switch (periph) { + case PERIPH_SARADC_MODULE: + return PCR_SARADC_CLK_EN; + case PERIPH_RMT_MODULE: + return PCR_RMT_CLK_EN; + case PERIPH_PCNT_MODULE: + return PCR_PCNT_CLK_EN; + case PERIPH_LEDC_MODULE: + return PCR_LEDC_CLK_EN; + case PERIPH_UART0_MODULE: + return PCR_UART0_CLK_EN; + case PERIPH_UART1_MODULE: + return PCR_UART1_CLK_EN; + case PERIPH_I2C0_MODULE: + return PCR_I2C_CLK_EN; + case PERIPH_I2S1_MODULE: + return PCR_I2S_CLK_EN; + case PERIPH_TIMG0_MODULE: + return PCR_TG0_CLK_EN; + case PERIPH_TIMG1_MODULE: + return PCR_TG1_CLK_EN; + case PERIPH_UHCI0_MODULE: + return PCR_UHCI_CLK_EN; + case PERIPH_SYSTIMER_MODULE: + return PCR_SYSTIMER_CLK_EN; + case PERIPH_SPI_MODULE: + return PCR_MSPI_CLK_EN; + case PERIPH_SPI2_MODULE: + return PCR_SPI2_CLK_EN; + case PERIPH_TWAI0_MODULE: + return PCR_TWAI0_CLK_EN; + case PERIPH_TWAI1_MODULE: + return PCR_TWAI1_CLK_EN; + case PERIPH_GDMA_MODULE: + return PCR_GDMA_CLK_EN; + case PERIPH_AES_MODULE: + return PCR_AES_CLK_EN; + case PERIPH_SHA_MODULE: + return PCR_SHA_CLK_EN; + case PERIPH_RSA_MODULE: + return PCR_RSA_CLK_EN; + case PERIPH_HMAC_MODULE: + return PCR_HMAC_CLK_EN; + case PERIPH_DS_MODULE: + return PCR_DS_CLK_EN; + // case PERIPH_RNG_MODULE: + // return PCR_WIFI_CLK_RNG_EN; + // case PERIPH_WIFI_MODULE: + // return PCR_WIFI_CLK_WIFI_EN_M; + // case PERIPH_BT_MODULE: + // return PCR_WIFI_CLK_BT_EN_M; + // case PERIPH_WIFI_BT_COMMON_MODULE: + // return PCR_WIFI_CLK_WIFI_BT_COMMON_M; + // case PERIPH_BT_BASEBAND_MODULE: + // return PCR_BT_BASEBAND_EN; + // case PERIPH_BT_LC_MODULE: + // return PCR_BT_LC_EN; + default: + return 0; + } +} + +static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool enable) +{ // TODO: IDF-5713 + (void)enable; // unused + + switch (periph) { + case PERIPH_SARADC_MODULE: + return PCR_SARADC_RST_EN; + case PERIPH_RMT_MODULE: + return PCR_RMT_RST_EN; + case PERIPH_PCNT_MODULE: + return PCR_PCNT_RST_EN; + case PERIPH_LEDC_MODULE: + return PCR_LEDC_RST_EN; + case PERIPH_UART0_MODULE: + return PCR_UART0_RST_EN; + case PERIPH_UART1_MODULE: + return PCR_UART1_RST_EN; + case PERIPH_I2C0_MODULE: + return PCR_I2C_RST_EN; + case PERIPH_I2S1_MODULE: + return PCR_I2S_RST_EN; + case PERIPH_TIMG0_MODULE: + return PCR_TG0_RST_EN; + case PERIPH_TIMG1_MODULE: + return PCR_TG1_RST_EN; + case PERIPH_UHCI0_MODULE: + return PCR_UHCI_RST_EN; + case PERIPH_SYSTIMER_MODULE: + return PCR_SYSTIMER_RST_EN; + case PERIPH_SPI_MODULE: + return PCR_MSPI_RST_EN; + case PERIPH_SPI2_MODULE: + return PCR_SPI2_RST_EN; + case PERIPH_TWAI0_MODULE: + return PCR_TWAI0_RST_EN; + case PERIPH_TWAI1_MODULE: + return PCR_TWAI1_RST_EN; + case PERIPH_GDMA_MODULE: + return PCR_GDMA_RST_EN; + case PERIPH_AES_MODULE: + if (enable == true) { + // Clear reset on digital signature, otherwise AES unit is held in reset also. + return (PCR_AES_RST_EN | PCR_DS_RST_EN); + } else { + //Don't return other units to reset, as this pulls reset on RSA & SHA units, respectively. + return PCR_AES_RST_EN; + } + case PERIPH_SHA_MODULE: + if (enable == true) { + // Clear reset on digital signature and HMAC, otherwise SHA is held in reset + return (PCR_SHA_RST_EN | PCR_DS_RST_EN | PCR_HMAC_RST_EN); + } else { + // Don't assert reset on secure boot, otherwise AES is held in reset + return PCR_SHA_RST_EN; + } + case PERIPH_RSA_MODULE: + if (enable == true) { + /* also clear reset on digital signature, otherwise RSA is held in reset */ + return (PCR_RSA_RST_EN | PCR_DS_RST_EN); + } else { + /* don't reset digital signature unit, as this resets AES also */ + return PCR_RSA_RST_EN; + } + case PERIPH_HMAC_MODULE: + return PCR_HMAC_RST_EN; + case PERIPH_DS_MODULE: + return PCR_DS_RST_EN; + // case PERIPH_RNG_MODULE: + // return PCR_WIFI_CLK_RNG_EN; + // case PERIPH_WIFI_MODULE: + // return PCR_WIFI_CLK_WIFI_EN_M; + // case PERIPH_BT_MODULE: + // return PCR_WIFI_CLK_BT_EN_M; + // case PERIPH_WIFI_BT_COMMON_MODULE: + // return PCR_WIFI_CLK_WIFI_BT_COMMON_M; + // case PERIPH_BT_BASEBAND_MODULE: + // return PCR_BT_BASEBAND_EN; + // case PERIPH_BT_LC_MODULE: + // return PCR_BT_LC_EN; + default: + return 0; + } +} + +static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph) +{ // TODO: IDF-5713 + switch (periph) { + // case PERIPH_RNG_MODULE: + // case PERIPH_WIFI_MODULE: + // case PERIPH_BT_MODULE: + // case PERIPH_WIFI_BT_COMMON_MODULE: + // case PERIPH_BT_BASEBAND_MODULE: + // case PERIPH_BT_LC_MODULE: + // return SYSTEM_WIFI_CLK_EN_REG; + + case PERIPH_SARADC_MODULE: + return PCR_SARADC_CONF_REG; + case PERIPH_RMT_MODULE: + return PCR_RMT_CONF_REG; + case PERIPH_PCNT_MODULE: + return PCR_PCNT_CONF_REG; + case PERIPH_LEDC_MODULE: + return PCR_LEDC_CONF_REG; + case PERIPH_UART0_MODULE: + return PCR_UART0_CONF_REG; + case PERIPH_UART1_MODULE: + return PCR_UART1_CONF_REG; + case PERIPH_I2C0_MODULE: + return PCR_I2C_CONF_REG; + case PERIPH_I2S1_MODULE: + return PCR_I2S_CONF_REG; + case PERIPH_TIMG0_MODULE: + return PCR_TIMERGROUP0_CONF_REG; + case PERIPH_TIMG1_MODULE: + return PCR_TIMERGROUP1_CONF_REG; + case PERIPH_UHCI0_MODULE: + return PCR_UHCI_CONF_REG; + case PERIPH_SYSTIMER_MODULE: + return PCR_SYSTIMER_CONF_REG; + case PERIPH_SPI_MODULE: + return PCR_MSPI_CONF_REG; + case PERIPH_SPI2_MODULE: + return PCR_SPI2_CONF_REG; + case PERIPH_TWAI0_MODULE: + return PCR_TWAI0_CONF_REG; + case PERIPH_TWAI1_MODULE: + return PCR_TWAI1_CONF_REG; + case PERIPH_GDMA_MODULE: + return PCR_GDMA_CONF_REG; + case PERIPH_AES_MODULE: + return PCR_AES_CONF_REG; + case PERIPH_SHA_MODULE: + return PCR_SHA_CONF_REG; + case PERIPH_RSA_MODULE: + return PCR_RSA_CONF_REG; + case PERIPH_HMAC_MODULE: + return PCR_HMAC_CONF_REG; + case PERIPH_DS_MODULE: + return PCR_DS_CONF_REG; + default: + return 0; + } +} + +static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph) +{ // TODO: IDF-5713 + switch (periph) { + case PERIPH_SARADC_MODULE: + return PCR_SARADC_CONF_REG; + case PERIPH_RMT_MODULE: + return PCR_RMT_CONF_REG; + case PERIPH_PCNT_MODULE: + return PCR_PCNT_CONF_REG; + case PERIPH_LEDC_MODULE: + return PCR_LEDC_CONF_REG; + case PERIPH_UART0_MODULE: + return PCR_UART0_CONF_REG; + case PERIPH_UART1_MODULE: + return PCR_UART1_CONF_REG; + case PERIPH_I2C0_MODULE: + return PCR_I2C_CONF_REG; + case PERIPH_I2S1_MODULE: + return PCR_I2S_CONF_REG; + case PERIPH_TIMG0_MODULE: + return PCR_TIMERGROUP0_CONF_REG; + case PERIPH_TIMG1_MODULE: + return PCR_TIMERGROUP1_CONF_REG; + case PERIPH_UHCI0_MODULE: + return PCR_UHCI_CONF_REG; + case PERIPH_SYSTIMER_MODULE: + return PCR_SYSTIMER_CONF_REG; + case PERIPH_SPI_MODULE: + return PCR_MSPI_CONF_REG; + case PERIPH_SPI2_MODULE: + return PCR_SPI2_CONF_REG; + case PERIPH_TWAI0_MODULE: + return PCR_TWAI0_CONF_REG; + case PERIPH_TWAI1_MODULE: + return PCR_TWAI1_CONF_REG; + case PERIPH_GDMA_MODULE: + return PCR_GDMA_CONF_REG; + case PERIPH_AES_MODULE: + return PCR_AES_CONF_REG; + case PERIPH_SHA_MODULE: + return PCR_SHA_CONF_REG; + case PERIPH_RSA_MODULE: + return PCR_RSA_CONF_REG; + case PERIPH_HMAC_MODULE: + return PCR_HMAC_CONF_REG; + case PERIPH_DS_MODULE: + return PCR_DS_CONF_REG; + default: + return 0; + } +} + +static inline void periph_ll_enable_clk_clear_rst(periph_module_t periph) +{ + DPORT_SET_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)); + DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, true)); +} + +static inline void periph_ll_disable_clk_set_rst(periph_module_t periph) +{ + DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)); + DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); +} + +static inline void IRAM_ATTR periph_ll_wifi_bt_module_enable_clk_clear_rst(void) +{ + // DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M);// TODO: IDF-5679 + // DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); +} + +static inline void IRAM_ATTR periph_ll_wifi_bt_module_disable_clk_set_rst(void) +{ + // DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M);// TODO: IDF-5679 + // DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); +} + +static inline void periph_ll_reset(periph_module_t periph) +{ + DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); + DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); +} + +static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph) +{ + return DPORT_REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 && + DPORT_REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0; +} + +static inline void periph_ll_wifi_module_enable_clk_clear_rst(void) +{ + // DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_EN_M); // TODO: IDF-5679 + // DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); +} + +static inline void periph_ll_wifi_module_disable_clk_set_rst(void) +{ + // DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_EN_M); // TODO: IDF-5679 + // DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/clk_tree_ll.h b/components/hal/esp32c6/include/hal/clk_tree_ll.h new file mode 100644 index 0000000000..f7fd22513c --- /dev/null +++ b/components/hal/esp32c6/include/hal/clk_tree_ll.h @@ -0,0 +1,511 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "soc/soc.h" +#include "soc/clk_tree_defs.h" +#include "soc/rtc.h" +#include "soc/pcr_reg.h" +#include "hal/regi2c_ctrl.h" +#include "soc/regi2c_bbpll.h" +#include "hal/assert.h" +#include "hal/log.h" +#include "esp32c6/rom/rtc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define MHZ (1000000) + +#define CLK_LL_PLL_80M_FREQ_MHZ (80) +#define CLK_LL_PLL_160M_FREQ_MHZ (160) + +#define CLK_LL_PLL_320M_FREQ_MHZ (320) +#define CLK_LL_PLL_480M_FREQ_MHZ (480) + +#define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \ + .dac = 3, \ + .dres = 3, \ + .dgm = 3, \ + .dbuf = 1, \ +} + +/** + * @brief XTAL32K_CLK enable modes + */ +typedef enum { + CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL, //!< Enable the external 32kHz crystal for XTAL32K_CLK + CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL, //!< Enable the external clock signal for XTAL32K_CLK + CLK_LL_XTAL32K_ENABLE_MODE_BOOTSTRAP, //!< Bootstrap the crystal oscillator for faster XTAL32K_CLK start up */ +} clk_ll_xtal32k_enable_mode_t; + +/** + * @brief XTAL32K_CLK configuration structure + */ +typedef struct { + uint32_t dac : 6; + uint32_t dres : 3; + uint32_t dgm : 3; + uint32_t dbuf: 1; +} clk_ll_xtal32k_config_t; + +/** + * @brief Power up BBPLL circuit + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_enable(void) +{ + // TODO: IDF-5645 +} + +/** + * @brief Power down BBPLL circuit + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void) +{ + // TODO: IDF-5645 +} + +/** + * @brief Enable the 32kHz crystal oscillator + * + * @param mode Used to determine the xtal32k configuration parameters + */ +static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) +{ + // TODO: IDF-5645 +} + +/** + * @brief Disable the 32kHz crystal oscillator + */ +static inline void clk_ll_xtal32k_disable(void) +{ + // TODO: IDF-5645 +} + +/** + * @brief Get the state of the 32kHz crystal clock + * + * @return True if the 32kHz XTAL is enabled + */ +static inline bool clk_ll_xtal32k_is_enabled(void) +{ + // TODO: IDF-5645 + return 0; +} + +/** + * @brief Enable the internal oscillator output for RC_FAST_CLK + */ +static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void) +{ + // TODO: IDF-5645 +} + +/** + * @brief Disable the internal oscillator output for RC_FAST_CLK + */ +static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void) +{ + // TODO: IDF-5645 +} + +/** + * @brief Get the state of the internal oscillator for RC_FAST_CLK + * + * @return True if the oscillator is enabled + */ +static inline bool clk_ll_rc_fast_is_enabled(void) +{ + // TODO: IDF-5645 + return 1; +} + +/** + * @brief Enable the output from the internal oscillator to be passed into a configurable divider, + * which by default divides the input clock frequency by 256. i.e. RC_FAST_D256_CLK = RC_FAST_CLK / 256 + * + * Divider values other than 256 may be configured, but this facility is not currently needed, + * so is not exposed in the code. + * The output of the divider, RC_FAST_D256_CLK, is referred as 8md256 or simply d256 in reg. descriptions. + */ +static inline void clk_ll_rc_fast_d256_enable(void) +{ + // TODO: IDF-5645 +} + +/** + * @brief Disable the output from the internal oscillator to be passed into a configurable divider. + * i.e. RC_FAST_D256_CLK = RC_FAST_CLK / 256 + * + * Disabling this divider could reduce power consumption. + */ +static inline void clk_ll_rc_fast_d256_disable(void) +{ + // TODO: IDF-5645 +} + +/** + * @brief Get the state of the divider which is applied to the output from the internal oscillator (RC_FAST_CLK) + * + * @return True if the divided output is enabled + */ +static inline bool clk_ll_rc_fast_d256_is_enabled(void) +{ + // TODO: IDF-5645 + return 1; +} + +/** + * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals. + */ +static inline void clk_ll_rc_fast_digi_enable(void) +{ + // TODO: IDF-5645 +} + +/** + * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals. + */ +static inline void clk_ll_rc_fast_digi_disable(void) +{ + // TODO: IDF-5645 +} + +/** + * @brief Get the state of the digital RC_FAST_CLK + * + * @return True if the digital RC_FAST_CLK is enabled + */ +static inline bool clk_ll_rc_fast_digi_is_enabled(void) +{ + // TODO: IDF-5645 + return 0; +} + +/** + * @brief Enable the digital RC_FAST_D256_CLK, which is used to support peripherals. + */ +static inline void clk_ll_rc_fast_d256_digi_enable(void) +{ + // TODO: IDF-5645 +} + +/** + * @brief Disable the digital RC_FAST_D256_CLK, which is used to support peripherals. + */ +static inline void clk_ll_rc_fast_d256_digi_disable(void) +{ + // TODO: IDF-5645 +} + +/** + * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals. + */ +static inline void clk_ll_xtal32k_digi_enable(void) +{ + // TODO: IDF-5645 +} + +/** + * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals. + */ +static inline void clk_ll_xtal32k_digi_disable(void) +{ + // TODO: IDF-5645 +} + +/** + * @brief Get the state of the digital XTAL32K_CLK + * + * @return True if the digital XTAL32K_CLK is enabled + */ +static inline bool clk_ll_xtal32k_digi_is_enabled(void) +{ + // TODO: IDF-5645 + return 0; +} + +/** + * @brief Get PLL_CLK frequency + * + * @return PLL clock frequency, in MHz. Returns 0 if register field value is invalid. + */ +static inline __attribute__((always_inline)) uint32_t clk_ll_bbpll_get_freq_mhz(void) +{ + // TODO: IDF-5645 + return 0; +} + +/** + * @brief Set BBPLL frequency from XTAL source (Digital part) + * + * @param pll_freq_mhz PLL frequency, in MHz + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_set_freq_mhz(uint32_t pll_freq_mhz) +{ + // TODO: IDF-5645 +} + +/** + * @brief Set BBPLL frequency from XTAL source (Analog part) + * + * @param pll_freq_mhz PLL frequency, in MHz + * @param xtal_freq_mhz XTAL frequency, in MHz + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32_t pll_freq_mhz, uint32_t xtal_freq_mhz) +{ + // TODO: IDF-5645 +} + +/** + * @brief Select the clock source for CPU_CLK + * + * @param in_sel One of the clock sources in soc_cpu_clk_src_t + */ +static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk_src_t in_sel) +{ + // TODO: IDF-5645 + switch (in_sel) { + case SOC_CPU_CLK_SRC_XTAL: + REG_SET_FIELD(PCR_SYSCLK_CONF_REG, PCR_SOC_CLK_SEL, 0); + break; + case SOC_CPU_CLK_SRC_PLL: + REG_SET_FIELD(PCR_SYSCLK_CONF_REG, PCR_SOC_CLK_SEL, 1); + break; + case SOC_CPU_CLK_SRC_RC_FAST: + REG_SET_FIELD(PCR_SYSCLK_CONF_REG, PCR_SOC_CLK_SEL, 2); + break; + default: + // Unsupported CPU_CLK mux input sel + abort(); + } +} + +/** + * @brief Get the clock source for CPU_CLK + * + * @return Currently selected clock source (one of soc_cpu_clk_src_t values) + */ +static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_src(void) +{ + // TODO: IDF-5645 + uint32_t clk_sel = REG_GET_FIELD(PCR_SYSCLK_CONF_REG, PCR_SOC_CLK_SEL); + switch (clk_sel) { + case 0: + return SOC_CPU_CLK_SRC_XTAL; + case 1: + return SOC_CPU_CLK_SRC_PLL; + case 2: + return SOC_CPU_CLK_SRC_RC_FAST; + default: + // Invalid SOC_CLK_SEL value + return SOC_CPU_CLK_SRC_INVALID; + } +} + +/** + * @brief Set CPU frequency from PLL clock + * + * @param cpu_mhz CPU frequency value, in MHz + */ +static inline __attribute__((always_inline)) void clk_ll_cpu_set_freq_mhz_from_pll(uint32_t cpu_mhz) +{ + // TODO: IDF-5645 +} + +/** + * @brief Get CPU_CLK frequency from PLL_CLK source + * + * @return CPU clock frequency, in MHz. Returns 0 if register field value is invalid. + */ +static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_freq_mhz_from_pll(void) +{ + // TODO: IDF-5645 + return 0; +} + +/** + * @brief Set CPU_CLK's XTAL/FAST_RC clock source path divider + * + * @param divider Divider. Usually this divider is set to 1 in bootloader stage. PRE_DIV_CNT = divider - 1. + */ +static inline __attribute__((always_inline)) void clk_ll_cpu_set_divider(uint32_t divider) +{ + // TODO: IDF-5645 not configurable for 761, fixed at 3 for HS, 1 for LS +} + +/** + * @brief Get CPU_CLK's XTAL/FAST_RC clock source path divider + * + * @return Divider. Divider = (PRE_DIV_CNT + 1). + */ +static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(void) +{ + // TODO: IDF-5645 + return 0; +} + +/** + * @brief Select the clock source for RTC_SLOW_CLK + * + * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t + */ +static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) +{ + // TODO: IDF-5645 +} + +/** + * @brief Get the clock source for RTC_SLOW_CLK + * + * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values) + */ +static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) +{ + // TODO: IDF-5645 + return 0; +} + +/** + * @brief Select the clock source for RTC_FAST_CLK + * + * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t + */ +static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) +{ + // TODO: IDF-5645 +} + +/** + * @brief Get the clock source for RTC_FAST_CLK + * + * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values) + */ +static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) +{ + // TODO: IDF-5645 + return 0; +} + +/** + * @brief Set RC_FAST_CLK divider. The output from the divider is passed into rtc_fast_clk MUX. + * + * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. + */ +static inline void clk_ll_rc_fast_set_divider(uint32_t divider) +{ + // TODO: IDF-5645 +} + +/** + * @brief Get RC_FAST_CLK divider + * + * @return Divider. Divider = (CK8M_DIV_SEL + 1). + */ +static inline uint32_t clk_ll_rc_fast_get_divider(void) +{ + // TODO: IDF-5645 + return 0; +} + +/** + * @brief Set RC_SLOW_CLK divider + * + * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. + */ +static inline void clk_ll_rc_slow_set_divider(uint32_t divider) +{ + // TODO: IDF-5645 +} + +/************************* RTC STORAGE REGISTER STORE/LOAD **************************/ +/** + * @brief Store XTAL_CLK frequency in RTC storage register + * + * Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit + * halves. These are the routines to work with that representation. + * + * @param xtal_freq_mhz XTAL frequency, in MHz + */ +static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) +{ + // TODO: IDF-5645 +} + +/** + * @brief Load XTAL_CLK frequency from RTC storage register + * + * Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit + * halves. These are the routines to work with that representation. + * + * @return XTAL frequency, in MHz. Returns 0 if value in reg is invalid. + */ +static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz(void) +{ + // TODO: IDF-5645 + return 0; +} + +/** + * @brief Store APB_CLK frequency in RTC storage register + * + * Value of RTC_APB_FREQ_REG is stored as two copies in lower and upper 16-bit + * halves. These are the routines to work with that representation. + * + * @param apb_freq_hz APB frequency, in Hz + */ +static inline __attribute__((always_inline)) void clk_ll_apb_store_freq_hz(uint32_t apb_freq_hz) +{ + // TODO: IDF-5645 +} + +/** + * @brief Load APB_CLK frequency from RTC storage register + * + * Value of RTC_APB_FREQ_REG is stored as two copies in lower and upper 16-bit + * halves. These are the routines to work with that representation. + * + * @return The stored APB frequency, in Hz + */ +static inline uint32_t clk_ll_apb_load_freq_hz(void) +{ + // TODO: IDF-5645 + return 0; +} + +/** + * @brief Store RTC_SLOW_CLK calibration value in RTC storage register + * + * Value of RTC_SLOW_CLK_CAL_REG has to be in the same format as returned by rtc_clk_cal (microseconds, + * in Q13.19 fixed-point format). + * + * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format + */ +static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value) +{ + // TODO: IDF-5645 +} + +/** + * @brief Load the calibration value of RTC_SLOW_CLK frequency from RTC storage register + * + * This value gets updated (i.e. rtc slow clock gets calibrated) every time RTC_SLOW_CLK source switches + * + * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format + */ +static inline uint32_t clk_ll_rtc_slow_load_cal(void) +{ + // TODO: IDF-5645 + return 0; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32c6/include/hal/dedic_gpio_cpu_ll.h new file mode 100644 index 0000000000..0b08505346 --- /dev/null +++ b/components/hal/esp32c6/include/hal/dedic_gpio_cpu_ll.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "riscv/csr.h" + +/*fast gpio*/ +#define CSR_GPIO_OEN_USER 0x803 +#define CSR_GPIO_IN_USER 0x804 +#define CSR_GPIO_OUT_USER 0x805 + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((always_inline)) +static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) +{ + RV_WRITE_CSR(CSR_GPIO_OEN_USER, mask); +} + +static inline void dedic_gpio_cpu_ll_write_all(uint32_t value) +{ + RV_WRITE_CSR(CSR_GPIO_OUT_USER, value); +} + +__attribute__((always_inline)) +static inline uint32_t dedic_gpio_cpu_ll_read_in(void) +{ + uint32_t value = RV_READ_CSR(CSR_GPIO_IN_USER); + return value; +} + +__attribute__((always_inline)) +static inline uint32_t dedic_gpio_cpu_ll_read_out(void) +{ + uint32_t value = RV_READ_CSR(CSR_GPIO_OUT_USER); + return value; +} + +__attribute__((always_inline)) +static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value) +{ + RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value); + RV_CLEAR_CSR(CSR_GPIO_OUT_USER, mask & ~(value)); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/efuse_hal.h b/components/hal/esp32c6/include/hal/efuse_hal.h new file mode 100644 index 0000000000..b6c83d6da6 --- /dev/null +++ b/components/hal/esp32c6/include/hal/efuse_hal.h @@ -0,0 +1,69 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/soc_caps.h" +#include "hal/efuse_ll.h" +#include_next "hal/efuse_hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief get chip version + */ +uint32_t efuse_hal_get_chip_revision(void); + +/** + * @brief set eFuse timings + * + * @param apb_freq_hz APB frequency in Hz + */ +void efuse_hal_set_timing(uint32_t apb_freq_hz); + +/** + * @brief trigger eFuse read operation + */ +void efuse_hal_read(void); + +/** + * @brief clear registers for programming eFuses + */ +void efuse_hal_clear_program_registers(void); + +/** + * @brief burn eFuses written in programming registers (one block at once) + * + * @param block block number + */ +void efuse_hal_program(uint32_t block); + +/** + * @brief Calculate Reed-Solomon Encoding values for a block of efuse data. + * + * @param data Pointer to data buffer (length 32 bytes) + * @param rs_values Pointer to write encoded data to (length 12 bytes) + */ +void efuse_hal_rs_calculate(const void *data, void *rs_values); + +/** + * @brief Checks coding error in a block + * + * @param block Index of efuse block + * + * @return True - block has an error. + * False - no error. + */ +bool efuse_hal_is_coding_error_in_block(unsigned block); + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/efuse_ll.h b/components/hal/esp32c6/include/hal/efuse_ll.h new file mode 100644 index 0000000000..9505c17ab7 --- /dev/null +++ b/components/hal/esp32c6/include/hal/efuse_ll.h @@ -0,0 +1,133 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/efuse_periph.h" +#include "hal/assert.h" +#include "esp32c6/rom/efuse.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Always inline these functions even no gcc optimization is applied. + +/******************* eFuse fields *************************/ + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void) +{ + return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void) +{ + return EFUSE.rd_repeat_data1.wdt_delay_sel; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) +{ + return EFUSE.rd_mac_spi_sys_0.mac_0; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) +{ + return EFUSE.rd_mac_spi_sys_1.mac_1; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) +{ + return EFUSE.rd_repeat_data2.secure_boot_en; +} + +// TODO: IDF-5341 +// __attribute__((always_inline)) static inline bool efuse_ll_get_err_rst_enable(void) +// { +// return EFUSE.rd_repeat_data3.err_rst_enable; +// } + +// use efuse_hal_get_major_chip_version() to get major chip version +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void) +{ + return EFUSE.rd_mac_spi_sys_5.wafer_version_major; +} + +// use efuse_hal_get_minor_chip_version() to get minor chip version +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) +{ + return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_high << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_low; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) +{ + return EFUSE.rd_repeat_data4.disable_wafer_version_major; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void) +{ + return EFUSE.rd_sys_part1_data4.blk_version_major; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void) +{ + return EFUSE.rd_mac_spi_sys_3.blk_version_minor; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void) +{ + return EFUSE.rd_repeat_data4.disable_blk_version_major; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) +{ + return EFUSE.rd_mac_spi_sys_3.pkg_version; +} + +/******************* eFuse control functions *************************/ + +__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void) +{ + return EFUSE.cmd.read_cmd; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void) +{ + return EFUSE.cmd.pgm_cmd; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void) +{ + EFUSE.cmd.read_cmd = 1; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block) +{ + HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX); + EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void) +{ + EFUSE.conf.op_code = EFUSE_READ_OP_CODE; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void) +{ + EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value) +{ + EFUSE.wr_tim_conf2.pwr_off_num = value; +} + +/******************* eFuse control functions *************************/ + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/gdma_ll.h b/components/hal/esp32c6/include/hal/gdma_ll.h new file mode 100644 index 0000000000..f938c1600f --- /dev/null +++ b/components/hal/esp32c6/include/hal/gdma_ll.h @@ -0,0 +1,468 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include /* Required for NULL constant */ +#include +#include +#include "soc/gdma_struct.h" +#include "soc/gdma_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define GDMA_LL_GET_HW(id) (((id) == 0) ? (&GDMA) : NULL) + +#define GDMA_LL_RX_EVENT_MASK (0x7F) +#define GDMA_LL_TX_EVENT_MASK (0x3F) + +#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<5) +#define GDMA_LL_EVENT_TX_FIFO_OVF (1<<4) +#define GDMA_LL_EVENT_RX_FIFO_UDF (1<<6) +#define GDMA_LL_EVENT_RX_FIFO_OVF (1<<5) +#define GDMA_LL_EVENT_TX_TOTAL_EOF (1<<3) +#define GDMA_LL_EVENT_RX_DESC_EMPTY (1<<4) +#define GDMA_LL_EVENT_TX_DESC_ERROR (1<<2) +#define GDMA_LL_EVENT_RX_DESC_ERROR (1<<3) +#define GDMA_LL_EVENT_TX_EOF (1<<1) +#define GDMA_LL_EVENT_TX_DONE (1<<0) +#define GDMA_LL_EVENT_RX_ERR_EOF (1<<2) +#define GDMA_LL_EVENT_RX_SUC_EOF (1<<1) +#define GDMA_LL_EVENT_RX_DONE (1<<0) + +///////////////////////////////////// Common ///////////////////////////////////////// +/** + * @brief Enable DMA channel M2M mode (TX channel n forward data to RX channel n), disabled by default + */ +static inline void gdma_ll_enable_m2m_mode(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_conf0.mem_trans_en = enable; + if (enable) { + // to enable m2m mode, the tx chan has to be the same to rx chan, and set to a valid value + dev->channel[channel].in.in_peri_sel.peri_in_sel = 0; + dev->channel[channel].out.out_peri_sel.peri_out_sel = 0; + } +} + +/** + * @brief Enable DMA clock gating + */ +static inline void gdma_ll_enable_clock(gdma_dev_t *dev, bool enable) +{ + dev->misc_conf.clk_en = enable; +} + +///////////////////////////////////// RX ///////////////////////////////////////// +/** + * @brief Get DMA RX channel interrupt status word + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) +{ + return dev->in_intr[channel].st.val & GDMA_LL_RX_EVENT_MASK; +} + +/** + * @brief Enable DMA RX channel interrupt + */ +static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable) +{ + if (enable) { + dev->in_intr[channel].ena.val |= (mask & GDMA_LL_RX_EVENT_MASK); + } else { + dev->in_intr[channel].ena.val &= ~(mask & GDMA_LL_RX_EVENT_MASK); + } +} + +/** + * @brief Clear DMA RX channel interrupt + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask) +{ + dev->in_intr[channel].clr.val = (mask & GDMA_LL_RX_EVENT_MASK); +} + +/** + * @brief Get DMA RX channel interrupt status register address + */ +static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel) +{ + return (volatile void *)(&dev->in_intr[channel].st); +} + +/** + * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default + */ +static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_conf1.in_check_owner = enable; +} + +/** + * @brief Enable DMA RX channel burst reading data, disabled by default + */ +static inline void gdma_ll_rx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_conf0.in_data_burst_en = enable; +} + +/** + * @brief Enable DMA RX channel burst reading descriptor link, disabled by default + */ +static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_conf0.indscr_burst_en = enable; +} + +/** + * @brief Reset DMA RX channel FSM and FIFO pointer + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_conf0.in_rst = 1; + dev->channel[channel].in.in_conf0.in_rst = 0; +} + +/** + * @brief Check if DMA RX FIFO is full + * @param fifo_level only supports level 1 + */ +static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].in.infifo_status.val & 0x01; +} + +/** + * @brief Check if DMA RX FIFO is empty + * @param fifo_level only supports level 1 + */ +static inline bool gdma_ll_rx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].in.infifo_status.val & 0x02; +} + +/** + * @brief Get number of bytes in RX FIFO + * @param fifo_level only supports level 1 + */ +static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].in.infifo_status.infifo_cnt; +} + +/** + * @brief Pop data from DMA RX FIFO + */ +static inline uint32_t gdma_ll_rx_pop_data(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_pop.infifo_pop = 1; + return dev->channel[channel].in.in_pop.infifo_rdata; +} + +/** + * @brief Set the descriptor link base address for RX channel + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr) +{ + dev->channel[channel].in.in_link.inlink_addr = addr; +} + +/** + * @brief Start dealing with RX descriptors + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_start(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_link.inlink_start = 1; +} + +/** + * @brief Stop dealing with RX descriptors + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_link.inlink_stop = 1; +} + +/** + * @brief Restart a new inlink right after the last descriptor + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_link.inlink_restart = 1; +} + +/** + * @brief Enable DMA RX to return the address of current descriptor when receives error + */ +static inline void gdma_ll_rx_enable_auto_return(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_link.inlink_auto_ret = enable; +} + +/** + * @brief Check if DMA RX FSM is in IDLE state + */ +static inline bool gdma_ll_rx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_link.inlink_park; +} + +/** + * @brief Get RX success EOF descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_suc_eof_des_addr.val; +} + +/** + * @brief Get RX error EOF descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_err_eof_des_addr.val; +} + +/** + * @brief Get current RX descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_rx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_dscr.val; +} + +/** + * @brief Set priority for DMA RX channel + */ +static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio) +{ + dev->channel[channel].in.in_pri.rx_pri = prio; +} + +/** + * @brief Connect DMA RX channel to a given peripheral + */ +static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id) +{ + dev->channel[channel].in.in_peri_sel.peri_in_sel = periph_id; +} + +///////////////////////////////////// TX ///////////////////////////////////////// +/** + * @brief Get DMA TX channel interrupt status word + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) +{ + return dev->out_intr[channel].st.val & GDMA_LL_TX_EVENT_MASK; +} + +/** + * @brief Enable DMA TX channel interrupt + */ +static inline void gdma_ll_tx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable) +{ + if (enable) { + dev->out_intr[channel].ena.val |= (mask & GDMA_LL_TX_EVENT_MASK); + } else { + dev->out_intr[channel].ena.val &= ~(mask & GDMA_LL_TX_EVENT_MASK); + } +} + +/** + * @brief Clear DMA TX channel interrupt + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask) +{ + dev->out_intr[channel].clr.val = (mask & GDMA_LL_TX_EVENT_MASK); +} + +/** + * @brief Get DMA TX channel interrupt status register address + */ +static inline volatile void *gdma_ll_tx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel) +{ + return (volatile void *)(&dev->out_intr[channel].st); +} + +/** + * @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default + */ +static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf1.out_check_owner = enable; +} + +/** + * @brief Enable DMA TX channel burst sending data, disabled by default + */ +static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf0.out_data_burst_en = enable; +} + +/** + * @brief Enable DMA TX channel burst reading descriptor link, disabled by default + */ +static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf0.outdscr_burst_en = enable; +} + +/** + * @brief Set TX channel EOF mode + */ +static inline void gdma_ll_tx_set_eof_mode(gdma_dev_t *dev, uint32_t channel, uint32_t mode) +{ + dev->channel[channel].out.out_conf0.out_eof_mode = mode; +} + +/** + * @brief Enable DMA TX channel automatic write results back to descriptor after all data has been sent out, disabled by default + */ +static inline void gdma_ll_tx_enable_auto_write_back(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf0.out_auto_wrback = enable; +} + +/** + * @brief Reset DMA TX channel FSM and FIFO pointer + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_conf0.out_rst = 1; + dev->channel[channel].out.out_conf0.out_rst = 0; +} + +/** + * @brief Check if DMA TX FIFO is full + * @param fifo_level only supports level 1 + */ +static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].out.outfifo_status.val & 0x01; +} + +/** + * @brief Check if DMA TX FIFO is empty + * @param fifo_level only supports level 1 + */ +static inline bool gdma_ll_tx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].out.outfifo_status.val & 0x02; +} + +/** + * @brief Get number of bytes in TX FIFO + * @param fifo_level only supports level 1 + */ +static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].out.outfifo_status.outfifo_cnt; +} + +/** + * @brief Push data into DMA TX FIFO + */ +static inline void gdma_ll_tx_push_data(gdma_dev_t *dev, uint32_t channel, uint32_t data) +{ + dev->channel[channel].out.out_push.outfifo_wdata = data; + dev->channel[channel].out.out_push.outfifo_push = 1; +} + +/** + * @brief Set the descriptor link base address for TX channel + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr) +{ + dev->channel[channel].out.out_link.outlink_addr = addr; +} + +/** + * @brief Start dealing with TX descriptors + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_link.outlink_start = 1; +} + +/** + * @brief Stop dealing with TX descriptors + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_link.outlink_stop = 1; +} + +/** + * @brief Restart a new outlink right after the last descriptor + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_link.outlink_restart = 1; +} + +/** + * @brief Check if DMA TX FSM is in IDLE state + */ +static inline bool gdma_ll_tx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].out.out_link.outlink_park; +} + +/** + * @brief Get TX EOF descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_tx_get_eof_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].out.out_eof_des_addr.val; +} + +/** + * @brief Get current TX descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_tx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].out.out_dscr.val; +} + +/** + * @brief Set priority for DMA TX channel + */ +static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio) +{ + dev->channel[channel].out.out_pri.tx_pri = prio; +} + +/** + * @brief Connect DMA TX channel to a given peripheral + */ +static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id) +{ + dev->channel[channel].out.out_peri_sel.peri_out_sel = periph_id; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/gpio_ll.h b/components/hal/esp32c6/include/hal/gpio_ll.h new file mode 100644 index 0000000000..8232384afe --- /dev/null +++ b/components/hal/esp32c6/include/hal/gpio_ll.h @@ -0,0 +1,601 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in hal/include/hal/readme.md + ******************************************************************************/ + +// The LL layer for ESP32-C6 GPIO register operations + +#pragma once + +#include "soc/soc.h" +#include "soc/gpio_periph.h" +#include "soc/gpio_struct.h" +#include "soc/lp_aon_reg.h" +#include "soc/lp_io_reg.h" +#include "soc/pmu_reg.h" +#include "soc/usb_serial_jtag_reg.h" +#include "hal/gpio_types.h" +#include "hal/assert.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// Get GPIO hardware instance with giving gpio num +#define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) + +#define GPIO_LL_PRO_CPU_INTR_ENA (BIT(0)) +#define GPIO_LL_PRO_CPU_NMI_INTR_ENA (BIT(1)) +/** + * @brief Enable pull-up on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) +{ + REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); +} + +/** + * @brief Disable pull-up on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) +{ + REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); +} + +/** + * @brief Enable pull-down on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) +{ + REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); +} + +/** + * @brief Disable pull-down on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) +{ + // The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value + // USB DP pin is default to PU enabled + // Note that esp32c6 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin + // which should be checked is USB_DM_GPIO_NUM instead. + // if (gpio_num == USB_DP_GPIO_NUM) { // TODO: IDF-5321 find out pin number + // SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE); + // CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP); + // } + REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); +} + +/** + * @brief GPIO set interrupt trigger type + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to set the trigger type of e.g. of GPIO16, gpio_num should be GPIO_NUM_16 (16); + * @param intr_type Interrupt type, select from gpio_int_type_t + */ +static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, uint32_t gpio_num, gpio_int_type_t intr_type) +{ + hw->pin[gpio_num].int_type = intr_type; +} + +/** + * @brief Get GPIO interrupt status + * + * @param hw Peripheral GPIO hardware instance address. + * @param core_id interrupt core id + * @param status interrupt status + */ +__attribute__((always_inline)) +static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status) +{ + (void)core_id; + *status = hw->pcpu_int.procpu_int; +} + +/** + * @brief Get GPIO interrupt status high + * + * @param hw Peripheral GPIO hardware instance address. + * @param core_id interrupt core id + * @param status interrupt status high + */ +__attribute__((always_inline)) +static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status) +{ + *status = 0; // Less than 32 GPIOs in ESP32-C6 +} + +/** + * @brief Clear GPIO interrupt status + * + * @param hw Peripheral GPIO hardware instance address. + * @param mask interrupt status clear mask + */ +__attribute__((always_inline)) +static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask) +{ + hw->status_w1tc.status_w1tc = mask; +} + +/** + * @brief Clear GPIO interrupt status high + * + * @param hw Peripheral GPIO hardware instance address. + * @param mask interrupt status high clear mask + */ +__attribute__((always_inline)) +static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask) +{ + // Less than 32 GPIOs on ESP32-C6 Do nothing. +} + +/** + * @brief Enable GPIO module interrupt signal + * + * @param hw Peripheral GPIO hardware instance address. + * @param core_id Interrupt enabled CPU to corresponding ID + * @param gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + */ +__attribute__((always_inline)) +static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, uint32_t gpio_num) +{ + HAL_ASSERT(core_id == 0 && "target SoC only has a single core"); + GPIO.pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA; //enable pro cpu intr +} + +/** + * @brief Disable GPIO module interrupt signal + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + */ +__attribute__((always_inline)) +static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num) +{ + hw->pin[gpio_num].int_ena = 0; //disable GPIO intr +} + +/** + * @brief Disable input mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num) +{ + PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Enable input mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num) +{ + PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Disable output mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_output_disable(gpio_dev_t *hw, uint32_t gpio_num) +{ + hw->enable_w1tc.enable_w1tc = (0x1 << gpio_num); + // Ensure no other output signal is routed via GPIO matrix to this pin + REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4), + SIG_GPIO_OUT_IDX); +} + +/** + * @brief Enable output mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_output_enable(gpio_dev_t *hw, uint32_t gpio_num) +{ + hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num); +} + +/** + * @brief Disable open-drain mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_od_disable(gpio_dev_t *hw, uint32_t gpio_num) +{ + hw->pin[gpio_num].pad_driver = 0; +} + +/** + * @brief Enable open-drain mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num) +{ + hw->pin[gpio_num].pad_driver = 1; +} + +/** + * @brief GPIO set output level + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + * @param level Output level. 0: low ; 1: high + */ +__attribute__((always_inline)) +static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t level) +{ + if (level) { + hw->out_w1ts.out_w1ts = (1 << gpio_num); + } else { + hw->out_w1tc.out_w1tc = (1 << gpio_num); + } +} + +/** + * @brief GPIO get input level + * + * @warning If the pad is not configured for input (or input and output) the returned value is always 0. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to get the logic level of e.g. pin GPIO16, gpio_num should be GPIO_NUM_16 (16); + * + * @return + * - 0 the GPIO input level is 0 + * - 1 the GPIO input level is 1 + */ +static inline int gpio_ll_get_level(gpio_dev_t *hw, uint32_t gpio_num) +{ + return (hw->in.in_data_next >> gpio_num) & 0x1; +} + +/** + * @brief Enable GPIO wake-up function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. + */ +static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num) +{ + hw->pin[gpio_num].wakeup_enable = 0x1; +} + +/** + * @brief Disable GPIO wake-up function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num) +{ + hw->pin[gpio_num].wakeup_enable = 0; +} + +/** + * @brief Set GPIO pad drive capability + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + * @param strength Drive capability of the pad + */ +static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t strength) +{ + SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, strength, FUN_DRV_S); +} + +/** + * @brief Get GPIO pad drive capability + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + * @param strength Pointer to accept drive capability of the pad + */ +static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t *strength) +{ + *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S); +} + +/** + * @brief Enable all digital gpio pad hold function during Deep-sleep. + * + * @param hw Peripheral GPIO hardware instance address. + */ +static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw) +{ + // ESP32C6 has removed deepsleep and replace with software backup sleep + // TODO: IDF-5321 +} + +/** + * @brief Disable all digital gpio pad hold function during Deep-sleep. + * + * @param hw Peripheral GPIO hardware instance address. + */ +static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw) +{ + // ESP32C6 has removed deepsleep and replace with software backup sleep + // TODO: IDF-5321 +} + +/** + * @brief Enable gpio pad hold function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + */ +static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: IDF-5321 + // if (gpio_num <32) { + // SET_PERI_REG_MASK(LP_AON_GPIO_HOLD0_REG, GPIO_HOLD_MASK[gpio_num]); + // } else if (gpio_num <= MAX_PAD_GPIO_NUM) { + // SET_PERI_REG_MASK(LP_AON_GPIO_HOLD1_REG, GPIO_HOLD_MASK[gpio_num]); + // } +} + +/** + * @brief Disable gpio pad hold function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + */ +static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: IDF-5321 + // if (gpio_num <32) { + // CLEAR_PERI_REG_MASK(LP_AON_GPIO_HOLD0_REG, GPIO_HOLD_MASK[gpio_num]); + // } else if (gpio_num <= MAX_PAD_GPIO_NUM) { + // CLEAR_PERI_REG_MASK(LP_AON_GPIO_HOLD1_REG, GPIO_HOLD_MASK[gpio_num]); + // } +} + +/** + * @brief Set pad input to a peripheral signal through the IOMUX. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number of the pad. + * @param signal_idx Peripheral signal id to input. One of the ``*_IN_IDX`` signals in ``soc/gpio_sig_map.h``. + */ +static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx) +{ + hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0; + PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio]); +} + +/** + * @brief Select a function for the pin in the IOMUX + * + * @param pin_name Pin name to configure + * @param func Function to assign to the pin + */ +static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) +{ + // TODO: IDF-5321 + // // Disable USB Serial JTAG if pins 18 or pins 19 needs to select an IOMUX function + // if (pin_name == IO_MUX_GPIO18_REG || pin_name == IO_MUX_GPIO19_REG) { + // CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); + // } + // PIN_FUNC_SELECT(pin_name, func); +} + +/** + * @brief Set peripheral output to an GPIO pad through the IOMUX. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num gpio_num GPIO number of the pad. + * @param func The function number of the peripheral pin to output pin. + * One of the ``FUNC_X_*`` of specified pin (X) in ``soc/io_mux_reg.h``. + * @param oen_inv True if the output enable needs to be inverted, otherwise False. + */ +static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, uint32_t oen_inv) +{ + hw->func_out_sel_cfg[gpio_num].oen_sel = 0; + hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; + gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); +} + +/** + * @brief Force hold digital and rtc gpio pad. + * @note GPIO force hold, whether the chip in sleep mode or wakeup mode. + */ +static inline void gpio_ll_force_hold_all(void) +{ + // TODO: IDF-5321 + // REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_HIGH_HP_PAD_HOLD_ALL); + // REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_HIGH_LP_PAD_HOLD_ALL); +} + +/** + * @brief Force unhold digital and rtc gpio pad. + * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode. + */ +static inline void gpio_ll_force_unhold_all(void) +{ + // TODO: IDF-5321 + // REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_LOW_HP_PAD_HOLD_ALL); + // REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_LOW_LP_PAD_HOLD_ALL); +} + +/** + * @brief Enable GPIO pin used for wakeup from sleep. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: IDF-5321 + // PIN_SLP_SEL_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Disable GPIO pin used for wakeup from sleep. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: IDF-5321 + // PIN_SLP_SEL_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Disable GPIO pull-up in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: IDF-5321 + // PIN_SLP_PULLUP_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Enable GPIO pull-up in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: IDF-5321 + // PIN_SLP_PULLUP_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Enable GPIO pull-down in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: IDF-5321 + // PIN_SLP_PULLDOWN_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Disable GPIO pull-down in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: IDF-5321 + // PIN_SLP_PULLDOWN_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Disable GPIO input in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: IDF-5321 + // PIN_SLP_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Enable GPIO input in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: IDF-5321 + // PIN_SLP_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Disable GPIO output in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: IDF-5321 + // PIN_SLP_OUTPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Enable GPIO output in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: IDF-5321 + // PIN_SLP_OUTPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); +} + +/** + * @brief Enable GPIO deep-sleep wake-up function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. + * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used. + */ +static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num, gpio_int_type_t intr_type) +{ + HAL_ASSERT(gpio_num <= GPIO_NUM_5 && "gpio larger than 5 does not support deep sleep wake-up function"); + + // TODO: IDF-5321 + // SET_PERI_REG_MASK(LP_IO_PIN0_REG + 0x4 * gpio_num, LP_IO_LP_GPIO0_WAKEUP_ENABLE); + // REG_SET_FIELD(LP_IO_PIN0_REG + 0x4 * gpio_num, LP_IO_LP_GPIO0_INT_TYPE, intr_type); +} + +/** + * @brief Disable GPIO deep-sleep wake-up function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num) +{ + HAL_ASSERT(gpio_num <= GPIO_NUM_5 && "gpio larger than 5 does not support deep sleep wake-up function"); + + // TODO: IDF-5321 + // CLEAR_PERI_REG_MASK(LP_IO_PIN0_REG + 0x4 * gpio_num, LP_IO_LP_GPIO0_WAKEUP_ENABLE); + // CLEAR_PERI_REG_MASK(LP_IO_PIN0_REG + 0x4 * gpio_num, LP_IO_LP_GPIO0_INT_TYPE); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/gpspi_flash_ll.h b/components/hal/esp32c6/include/hal/gpspi_flash_ll.h new file mode 100644 index 0000000000..1a8f3a7d57 --- /dev/null +++ b/components/hal/esp32c6/include/hal/gpspi_flash_ll.h @@ -0,0 +1,409 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The ll is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The Lowlevel layer for SPI Flash + +#pragma once + +#include +#include "soc/spi_periph.h" +#include "soc/spi_struct.h" +#include "hal/spi_types.h" +#include "hal/spi_flash_types.h" +#include // For MIN/MAX +#include +#include +#include "hal/misc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +//NOTE: These macros are changed on c3 for build. MODIFY these when bringup flash. +#define gpspi_flash_ll_get_hw(host_id) ( ((host_id)==SPI2_HOST) ? &GPSPI2 : ({abort();(spi_dev_t*)0;}) ) +#define gpspi_flash_ll_hw_get_id(dev) ( ((dev) == (void*)&GPSPI2) ? SPI2_HOST : -1 ) + +typedef typeof(GPSPI2.clock.val) gpspi_flash_ll_clock_reg_t; +#define GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ (80) + +/*------------------------------------------------------------------------------ + * Control + *----------------------------------------------------------------------------*/ +/** + * Reset peripheral registers before configuration and starting control + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void gpspi_flash_ll_reset(spi_dev_t *dev) +{ + dev->user.val = 0; + dev->ctrl.val = 0; + + dev->clk_gate.clk_en = 1; + dev->clk_gate.mst_clk_active = 1; + dev->clk_gate.mst_clk_sel = 1; + + dev->dma_conf.val = 0; + dev->dma_conf.slv_tx_seg_trans_clr_en = 1; + dev->dma_conf.slv_rx_seg_trans_clr_en = 1; + dev->dma_conf.dma_slv_seg_trans_en = 0; +} + +/** + * Check whether the previous operation is done. + * + * @param dev Beginning address of the peripheral registers. + * + * @return true if last command is done, otherwise false. + */ +static inline bool gpspi_flash_ll_cmd_is_done(const spi_dev_t *dev) +{ + return (dev->cmd.usr == 0); +} + +/** + * Get the read data from the buffer after ``gpspi_flash_ll_read`` is done. + * + * @param dev Beginning address of the peripheral registers. + * @param buffer Buffer to hold the output data + * @param read_len Length to get out of the buffer + */ +static inline void gpspi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer, uint32_t read_len) +{ + if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) { + // If everything is word-aligned, do a faster memcpy + memcpy(buffer, (void *)dev->data_buf, read_len); + } else { + // Otherwise, slow(er) path copies word by word + int copy_len = read_len; + for (int i = 0; i < (read_len + 3) / 4; i++) { + int word_len = MIN(sizeof(uint32_t), copy_len); + uint32_t word = dev->data_buf[i].buf; + memcpy(buffer, &word, word_len); + buffer = (void *)((intptr_t)buffer + word_len); + copy_len -= word_len; + } + } +} + +/** + * Write a word to the data buffer. + * + * @param dev Beginning address of the peripheral registers. + * @param word Data to write at address 0. + */ +static inline void gpspi_flash_ll_write_word(spi_dev_t *dev, uint32_t word) +{ + dev->data_buf[0].buf = word; +} + +/** + * Set the data to be written in the data buffer. + * + * @param dev Beginning address of the peripheral registers. + * @param buffer Buffer holding the data + * @param length Length of data in bytes. + */ +static inline void gpspi_flash_ll_set_buffer_data(spi_dev_t *dev, const void *buffer, uint32_t length) +{ + // Load data registers, word at a time + int num_words = (length + 3) / 4; + for (int i = 0; i < num_words; i++) { + uint32_t word = 0; + uint32_t word_len = MIN(length, sizeof(word)); + memcpy(&word, buffer, word_len); + dev->data_buf[i].buf = word; + length -= word_len; + buffer = (void *)((intptr_t)buffer + word_len); + } +} + +/** + * Trigger a user defined transaction. All phases, including command, address, dummy, and the data phases, + * should be configured before this is called. + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void gpspi_flash_ll_user_start(spi_dev_t *dev) +{ + dev->cmd.update = 1; + while (dev->cmd.update); + dev->cmd.usr = 1; +} + +/** + * Set HD pin high when flash work at spi mode. + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void gpspi_flash_ll_set_hold_pol(spi_dev_t *dev, uint32_t pol_val) +{ + dev->ctrl.hold_pol = pol_val; +} + +/** + * Check whether the host is idle to perform new commands. + * + * @param dev Beginning address of the peripheral registers. + * + * @return true if the host is idle, otherwise false + */ +static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev) +{ + return dev->cmd.usr == 0; +} + +/** + * Set phases for user-defined transaction to read + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev) +{ + typeof (dev->user) user = { + .usr_command = 1, + .usr_mosi = 0, + .usr_miso = 1, + .usr_addr = 1, + }; + dev->user = user; +} +/*------------------------------------------------------------------------------ + * Configs + *----------------------------------------------------------------------------*/ +/** + * Select which pin to use for the flash + * + * @param dev Beginning address of the peripheral registers. + * @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins. + */ +static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin) +{ + dev->misc.cs0_dis = (pin == 0) ? 0 : 1; + dev->misc.cs1_dis = (pin == 1) ? 0 : 1; +} + +/** + * Set the read io mode. + * + * @param dev Beginning address of the peripheral registers. + * @param read_mode I/O mode to use in the following transactions. + */ +static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode) +{ + typeof (dev->ctrl) ctrl = dev->ctrl; + typeof (dev->user) user = dev->user; + + ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M); + user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M); + + switch (read_mode) { + case SPI_FLASH_FASTRD: + //the default option + case SPI_FLASH_SLOWRD: + break; + case SPI_FLASH_QIO: + ctrl.fread_quad = 1; + ctrl.faddr_quad = 1; + user.fwrite_quad = 1; + break; + case SPI_FLASH_QOUT: + ctrl.fread_quad = 1; + user.fwrite_quad = 1; + break; + case SPI_FLASH_DIO: + ctrl.fread_dual = 1; + ctrl.faddr_dual = 1; + user.fwrite_dual = 1; + break; + case SPI_FLASH_DOUT: + ctrl.fread_dual = 1; + user.fwrite_dual = 1; + break; + default: + abort(); + } + + dev->ctrl = ctrl; + dev->user = user; +} + +/** + * Set clock frequency to work at. + * + * @param dev Beginning address of the peripheral registers. + * @param clock_val pointer to the clock value to set + */ +static inline void gpspi_flash_ll_set_clock(spi_dev_t *dev, gpspi_flash_ll_clock_reg_t *clock_val) +{ + dev->clock.val = *clock_val; +} + +/** + * Set the input length, in bits. + * + * @param dev Beginning address of the peripheral registers. + * @param bitlen Length of input, in bits. + */ +static inline void gpspi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitlen) +{ + dev->user.usr_miso = bitlen > 0; + if (bitlen) { + dev->ms_dlen.ms_data_bitlen = bitlen - 1; + } +} + +/** + * Set the output length, in bits (not including command, address and dummy + * phases) + * + * @param dev Beginning address of the peripheral registers. + * @param bitlen Length of output, in bits. + */ +static inline void gpspi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bitlen) +{ + dev->user.usr_mosi = bitlen > 0; + if (bitlen) { + dev->ms_dlen.ms_data_bitlen = bitlen - 1; + } +} + +/** + * Set the command. + * + * @param dev Beginning address of the peripheral registers. + * @param command Command to send + * @param bitlen Length of the command + */ +static inline void gpspi_flash_ll_set_command(spi_dev_t *dev, uint8_t command, uint32_t bitlen) +{ + dev->user.usr_command = 1; + typeof(dev->user2) user2 = { + .usr_command_value = command, + .usr_command_bitlen = (bitlen - 1), + }; + dev->user2 = user2; +} + +/** + * Get the address length that is set in register, in bits. + * + * @param dev Beginning address of the peripheral registers. + * + */ +static inline int gpspi_flash_ll_get_addr_bitlen(spi_dev_t *dev) +{ + return dev->user.usr_addr ? dev->user1.usr_addr_bitlen + 1 : 0; +} + +/** + * Set the address length to send, in bits. Should be called before commands that requires the address e.g. erase sector, read, write... + * + * @param dev Beginning address of the peripheral registers. + * @param bitlen Length of the address, in bits + */ +static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitlen) +{ + dev->user1.usr_addr_bitlen = (bitlen - 1); + dev->user.usr_addr = bitlen ? 1 : 0; +} + +/** + * Set the address to send in user mode. Should be called before commands that requires the address e.g. erase sector, read, write... + * + * @param dev Beginning address of the peripheral registers. + * @param addr Address to send + */ +static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen) +{ + // The blank region should be all ones + uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen); + dev->addr.val = (addr << (32 - bitlen)) | padding_ones; +} + +/** + * Set the address to send. Should be called before commands that requires the address e.g. erase sector, read, write... + * + * @param dev Beginning address of the peripheral registers. + * @param addr Address to send + */ +static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr) +{ + dev->addr.val = addr; +} + +/** + * Set the length of dummy cycles. + * + * @param dev Beginning address of the peripheral registers. + * @param dummy_n Cycles of dummy phases + */ +static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n) +{ + dev->user.usr_dummy = dummy_n ? 1 : 0; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1); +} + +/** + * Set D/Q output level during dummy phase + * + * @param dev Beginning address of the peripheral registers. + * @param out_en whether to enable IO output for dummy phase + * @param out_level dummy output level + */ +static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en, uint32_t out_lev) +{ + dev->ctrl.dummy_out = out_en; + dev->ctrl.q_pol = out_lev; + dev->ctrl.d_pol = out_lev; +} + +/** + * Set extra hold time of CS after the clocks. + * + * @param dev Beginning address of the peripheral registers. + * @param hold_n Cycles of clocks before CS is inactive + */ +static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n) +{ + dev->user1.cs_hold_time = hold_n - 1; + dev->user.cs_hold = (hold_n > 0? 1: 0); +} + +static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time) +{ + dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0); + dev->user1.cs_setup_time = cs_setup_time - 1; +} + +/** + * Calculate spi_flash clock frequency division parameters for register. + * + * @param clkdiv frequency division factor + * + * @return Register setting for the given clock division factor. + */ +static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv) +{ + uint32_t div_parameter; + // See comments of `clock` in `spi_struct.h` + if (clkdiv == 1) { + div_parameter = (1 << 31); + } else { + div_parameter = ((clkdiv - 1) | (((clkdiv/2 - 1) & 0xff) << 6 ) | (((clkdiv - 1) & 0xff) << 12)); + } + return div_parameter; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/i2s_ll.h b/components/hal/esp32c6/include/hal/i2s_ll.h new file mode 100644 index 0000000000..aac0bcbddd --- /dev/null +++ b/components/hal/esp32c6/include/hal/i2s_ll.h @@ -0,0 +1,1166 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for I2S register operations +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in hal/include/hal/readme.md + ******************************************************************************/ + +#pragma once +#include +#include "hal/misc.h" +#include "hal/assert.h" +#include "soc/i2s_periph.h" +#include "soc/i2s_struct.h" +#include "soc/pcr_struct.h" +#include "hal/i2s_types.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +#define I2S_LL_GET_HW(num) (((num) == 0)? (&I2S0) : NULL) + +#define I2S_LL_TDM_CH_MASK (0xffff) +#define I2S_LL_PDM_BCK_FACTOR (64) + +#define I2S_LL_MCLK_DIVIDER_BIT_WIDTH (9) +#define I2S_LL_MCLK_DIVIDER_MAX ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1) + +/* I2S clock configuration structure */ +typedef struct { + uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a) + uint16_t a; + uint16_t b; // The decimal part of module clock divider, the decimal is: b/a +} i2s_ll_mclk_div_t; + +/** + * @brief I2S module general init, enable I2S clock. + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_enable_clock(i2s_dev_t *hw) +{ + // The clock gate enabling is moved to `periph_module_enable` + (void)hw; +} + +/** + * @brief I2S module disable I2S clock. + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_disable_clock(i2s_dev_t *hw) +{ + // The clock gate disabling is moved to `periph_module_disable` + (void)hw; +} + +/** + * @brief Enable I2S tx module clock + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_tx_enable_clock(i2s_dev_t *hw) +{ + (void)hw; + PCR.i2s_tx_clkm_conf.i2s_tx_clkm_en = 1; +} + +/** + * @brief Enable I2S rx module clock + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_rx_enable_clock(i2s_dev_t *hw) +{ + (void)hw; + PCR.i2s_rx_clkm_conf.i2s_rx_clkm_en = 1; +} + +/** + * @brief Disable I2S tx module clock + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_tx_disable_clock(i2s_dev_t *hw) +{ + (void)hw; + PCR.i2s_tx_clkm_conf.i2s_tx_clkm_en = 0; +} + +/** + * @brief Disable I2S rx module clock + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_rx_disable_clock(i2s_dev_t *hw) +{ + (void)hw; + PCR.i2s_rx_clkm_conf.i2s_rx_clkm_en = 0; +} + +/** + * @brief I2S mclk use tx module clock + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_mclk_bind_to_tx_clk(i2s_dev_t *hw) +{ + (void)hw; + PCR.i2s_rx_clkm_conf.i2s_mclk_sel = 0; +} + +/** + * @brief I2S mclk use rx module clock + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_mclk_bind_to_rx_clk(i2s_dev_t *hw) +{ + (void)hw; + PCR.i2s_rx_clkm_conf.i2s_mclk_sel = 1; +} + +/** + * @brief Enable I2S TX slave mode + * + * @param hw Peripheral I2S hardware instance address. + * @param slave_en Set true to enable slave mode + */ +static inline void i2s_ll_tx_set_slave_mod(i2s_dev_t *hw, bool slave_en) +{ + hw->tx_conf.tx_slave_mod = slave_en; +} + +/** + * @brief Enable I2S RX slave mode + * + * @param hw Peripheral I2S hardware instance address. + * @param slave_en Set true to enable slave mode + */ +static inline void i2s_ll_rx_set_slave_mod(i2s_dev_t *hw, bool slave_en) +{ + hw->rx_conf.rx_slave_mod = slave_en; +} + +/** + * @brief Reset I2S TX module + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_tx_reset(i2s_dev_t *hw) +{ + hw->tx_conf.tx_reset = 1; + hw->tx_conf.tx_reset = 0; +} + +/** + * @brief Reset I2S RX module + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_rx_reset(i2s_dev_t *hw) +{ + hw->rx_conf.rx_reset = 1; + hw->rx_conf.rx_reset = 0; +} + +/** + * @brief Reset I2S TX FIFO + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_tx_reset_fifo(i2s_dev_t *hw) +{ + hw->tx_conf.tx_fifo_reset = 1; + hw->tx_conf.tx_fifo_reset = 0; +} + +/** + * @brief Reset I2S RX FIFO + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_rx_reset_fifo(i2s_dev_t *hw) +{ + hw->rx_conf.rx_fifo_reset = 1; + hw->rx_conf.rx_fifo_reset = 0; +} + +/** + * @brief Set TX source clock + * + * @param hw Peripheral I2S hardware instance address. + * @param src I2S source clock. + */ +static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src) +{ + (void)hw; + switch (src) + { + case I2S_CLK_SRC_XTAL: + PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 0; + break; + case I2S_CLK_SRC_PLL_160M: + PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 2; + break; + default: + HAL_ASSERT(false && "unsupported clock source"); + break; + } +} + +/** + * @brief Set RX source clock + * + * @param hw Peripheral I2S hardware instance address. + * @param src I2S source clock + */ +static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src) +{ + (void)hw; + switch (src) + { + case I2S_CLK_SRC_XTAL: + PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel = 0; + break; + case I2S_CLK_SRC_PLL_160M: + PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel = 2; + break; + default: + HAL_ASSERT(false && "unsupported clock source"); + break; + } +} + +/** + * @brief Set I2S tx bck div num + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx bck div num + */ +static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val) +{ + hw->tx_conf1.tx_bck_div_num = val - 1; +} + +/** + * @brief Set I2S tx raw clock division + * + * @param hw Peripheral I2S hardware instance address. + * @param x div x + * @param y div y + * @param z div z + * @param yn1 yn1 + */ +static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1) +{ + (void)hw; + PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_x = x; + PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_y = y; + PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_z = z; + PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_yn1 = yn1; +} + +/** + * @brief Set I2S rx raw clock division + * + * @param hw Peripheral I2S hardware instance address. + * @param x div x + * @param y div y + * @param z div z + * @param yn1 yn1 + */ +static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1) +{ + (void)hw; + PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_x = x; + PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_y = y; + PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_z = z; + PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_yn1 = yn1; +} + +/** + * @brief Configure I2S TX module clock divider + * + * @param hw Peripheral I2S hardware instance address. + * @param sclk system clock + * @param mclk module clock + * @param mclk_div integer part of the division from sclk to mclk + */ +static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div) +{ + (void)hw; + int ma = 0; + int mb = 0; + int denominator = 1; + int numerator = 0; + + uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div)); + if (!freq_diff) { + goto finish; + } + float decimal = freq_diff / (float)mclk; + // Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0 + if (decimal > 125.0 / 126.0) { + mclk_div++; + goto finish; + } + uint32_t min = ~0; + for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) { + int b = (int)(a * (freq_diff / (double)mclk) + 0.5); + ma = freq_diff * a; + mb = mclk * b; + if (ma == mb) { + denominator = a; + numerator = b; + goto finish; + } + if (abs((mb - ma)) < min) { + denominator = a; + numerator = b; + min = abs(mb - ma); + } + } +finish: + if (denominator == 0 || numerator == 0) { + PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_x = 0; + PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_y = 0; + PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_z = 0; + } else { + if (numerator > denominator / 2) { + PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_x = denominator / (denominator - numerator) - 1; + PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_y = denominator % (denominator - numerator); + PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_z = denominator - numerator; + PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_yn1 = 1; + } else { + PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_x = denominator / numerator - 1; + PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_y = denominator % numerator; + PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_z = numerator; + PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_yn1 = 0; + } + } + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_tx_clkm_conf, i2s_tx_clkm_div_num, mclk_div); +} + +/** + * @brief Set I2S rx bck div num + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx bck div num + */ +static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val) +{ + hw->rx_conf1.rx_bck_div_num = val - 1; +} + +/** + * @brief Configure I2S RX module clock divider + * @note mclk on ESP32 is shared by both TX and RX channel + * + * @param hw Peripheral I2S hardware instance address. + * @param sclk system clock, 0 means use apll + * @param mclk module clock + * @param mclk_div integer part of the division from sclk to mclk + */ +static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div) +{ + (void)hw; + int ma = 0; + int mb = 0; + int denominator = 1; + int numerator = 0; + + uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div)); + if (!freq_diff) { + goto finish; + } + float decimal = freq_diff / (float)mclk; + // Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0 + if (decimal > 125.0 / 126.0) { + mclk_div++; + goto finish; + } + uint32_t min = ~0; + for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) { + int b = (int)(a * (freq_diff / (double)mclk) + 0.5); + ma = freq_diff * a; + mb = mclk * b; + if (ma == mb) { + denominator = a; + numerator = b; + goto finish; + } + if (abs((mb - ma)) < min) { + denominator = a; + numerator = b; + min = abs(mb - ma); + } + } +finish: + if (denominator == 0 || numerator == 0) { + PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_x = 0; + PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_y = 0; + PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_z = 0; + } else { + if (numerator > denominator / 2) { + PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_x = denominator / (denominator - numerator) - 1; + PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_y = denominator % (denominator - numerator); + PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_z = denominator - numerator; + PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_yn1 = 1; + } else { + PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_x = denominator / numerator - 1; + PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_y = denominator % numerator; + PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_z = numerator; + PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_yn1 = 0; + } + } + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_rx_clkm_conf, i2s_rx_clkm_div_num, mclk_div); +} + +/** + * @brief Start I2S TX + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_tx_start(i2s_dev_t *hw) +{ + hw->tx_conf.tx_update = 0; + hw->tx_conf.tx_update = 1; + hw->tx_conf.tx_start = 1; +} + +/** + * @brief Start I2S RX + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_rx_start(i2s_dev_t *hw) +{ + hw->rx_conf.rx_update = 0; + hw->rx_conf.rx_update = 1; + hw->rx_conf.rx_start = 1; +} + +/** + * @brief Stop I2S TX + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_tx_stop(i2s_dev_t *hw) +{ + hw->tx_conf.tx_start = 0; +} + +/** + * @brief Stop I2S RX + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_rx_stop(i2s_dev_t *hw) +{ + hw->rx_conf.rx_start = 0; +} + +/** + * @brief Configure TX WS signal width + * + * @param hw Peripheral I2S hardware instance address. + * @param width WS width in BCK cycle + */ +static inline void i2s_ll_tx_set_ws_width(i2s_dev_t *hw, int width) +{ + hw->tx_conf1.tx_tdm_ws_width = width - 1; +} + +/** + * @brief Configure RX WS signal width + * + * @param hw Peripheral I2S hardware instance address. + * @param width WS width in BCK cycle + */ +static inline void i2s_ll_rx_set_ws_width(i2s_dev_t *hw, int width) +{ + hw->rx_conf1.rx_tdm_ws_width = width - 1; +} + +/** + * @brief Configure the received length to trigger in_suc_eof interrupt + * + * @param hw Peripheral I2S hardware instance address. + * @param eof_num the byte length to trigger in_suc_eof interrupt + */ +static inline void i2s_ll_rx_set_eof_num(i2s_dev_t *hw, int eof_num) +{ + hw->rx_eof_num.rx_eof_num = eof_num; +} + +/** + * @brief Congfigure TX chan bit and audio data bit + * + * @param hw Peripheral I2S hardware instance address. + * @param chan_bit The chan bit width + * @param data_bit The audio data bit width + */ +static inline void i2s_ll_tx_set_sample_bit(i2s_dev_t *hw, uint8_t chan_bit, int data_bit) +{ + hw->tx_conf1.tx_bits_mod = data_bit - 1; + hw->tx_conf1.tx_tdm_chan_bits = chan_bit - 1; +} + +/** + * @brief Congfigure RX chan bit and audio data bit + * + * @param hw Peripheral I2S hardware instance address. + * @param chan_bit The chan bit width + * @param data_bit The audio data bit width + */ +static inline void i2s_ll_rx_set_sample_bit(i2s_dev_t *hw, uint8_t chan_bit, int data_bit) +{ + hw->rx_conf1.rx_bits_mod = data_bit - 1; + hw->rx_conf1.rx_tdm_chan_bits = chan_bit - 1; +} + +/** + * @brief Configure RX half_sample_bit + * + * @param hw Peripheral I2S hardware instance address. + * @param half_sample_bits half sample bit width + */ +static inline void i2s_ll_tx_set_half_sample_bit(i2s_dev_t *hw, int half_sample_bits) +{ + hw->tx_conf1.tx_half_sample_bits = half_sample_bits - 1; +} + +/** + * @brief Configure RX half_sample_bit + * + * @param hw Peripheral I2S hardware instance address. + * @param half_sample_bits half sample bit width + */ +static inline void i2s_ll_rx_set_half_sample_bit(i2s_dev_t *hw, int half_sample_bits) +{ + hw->rx_conf1.rx_half_sample_bits = half_sample_bits - 1; +} + +/** + * @brief Enable TX MSB shift, the data will be launch at the first BCK clock + * + * @param hw Peripheral I2S hardware instance address. + * @param msb_shift_enable Set true to enable MSB shift + */ +static inline void i2s_ll_tx_enable_msb_shift(i2s_dev_t *hw, bool msb_shift_enable) +{ + hw->tx_conf1.tx_msb_shift = msb_shift_enable; +} + +/** + * @brief Enable RX MSB shift, the data will be launch at the first BCK clock + * + * @param hw Peripheral I2S hardware instance address. + * @param msb_shift_enable Set true to enable MSB shift + */ +static inline void i2s_ll_rx_enable_msb_shift(i2s_dev_t *hw, bool msb_shift_enable) +{ + hw->rx_conf1.rx_msb_shift = msb_shift_enable; +} + +/** + * @brief Configure TX total chan number + * + * @param hw Peripheral I2S hardware instance address. + * @param total_num Total chan number + */ +static inline void i2s_ll_tx_set_chan_num(i2s_dev_t *hw, int total_num) +{ + hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = total_num - 1; +} + +/** + * @brief Configure RX total chan number + * + * @param hw Peripheral I2S hardware instance address. + * @param total_num Total chan number + */ +static inline void i2s_ll_rx_set_chan_num(i2s_dev_t *hw, int total_num) +{ + hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = total_num - 1; +} + +/** + * @brief Set the bimap of the active TX chan, only the active chan can launch audio data. + * + * @param hw Peripheral I2S hardware instance address. + * @param chan_mask mask of tx active chan + */ +static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask) +{ + typeof(hw->tx_tdm_ctrl) tdm_ctrl_reg = hw->tx_tdm_ctrl; + tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK; + tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK; + hw->tx_tdm_ctrl.val = tdm_ctrl_reg.val; +} + +/** + * @brief Set the bimap of the active RX chan, only the active chan can receive audio data. + * + * @param hw Peripheral I2S hardware instance address. + * @param chan_mask mask of rx active chan + */ +static inline void i2s_ll_rx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask) +{ + typeof(hw->rx_tdm_ctrl) tdm_ctrl_reg = hw->rx_tdm_ctrl; + tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK; + tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK; + hw->rx_tdm_ctrl.val = tdm_ctrl_reg.val; +} + +/** + * @brief Set I2S tx chan mode + * + * @param hw Peripheral I2S hardware instance address. + * @param slot_mask select slot to send data + */ +static inline void i2s_ll_tx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t slot_mask) +{ + /* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot + * Otherwise always enable the first two slots */ + hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1; // tx_tdm_tot_chan_num = 2 slots - 1 = 1 + hw->tx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK; + switch (slot_mask) + { + case I2S_STD_SLOT_LEFT: + hw->tx_tdm_ctrl.val |= 0x01; + break; + case I2S_STD_SLOT_RIGHT: + hw->tx_tdm_ctrl.val |= 0x02; + break; + case I2S_STD_SLOT_BOTH: + hw->tx_tdm_ctrl.val |= 0x03; + break; + default: + break; + } +} + +/** + * @brief Set I2S rx chan mode + * + * @param hw Peripheral I2S hardware instance address. + * @param slot_mask select slot to receive data + */ +static inline void i2s_ll_rx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t slot_mask) +{ + /* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot + * Otherwise always enable the first two slots */ + hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1 + hw->rx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK; + switch (slot_mask) + { + case I2S_STD_SLOT_LEFT: + hw->rx_tdm_ctrl.val |= 0x01; + break; + case I2S_STD_SLOT_RIGHT: + hw->rx_tdm_ctrl.val |= 0x02; + break; + case I2S_STD_SLOT_BOTH: + hw->rx_tdm_ctrl.val |= 0x03; + break; + default: + break; + } +} + +/** + * @brief PDM slot mode + * + * @param hw Peripheral I2S hardware instance address. + * @param mod Channel mode + * while tx_ws_idle_pol = 0: + * 0: stereo + * 1: Both slots transmit left + * 2: Both slots transmit right + * 3: Left transmits `conf_single_data` right transmits data + * 4: Right transmits `conf_single_data` left transmits data + * while tx_ws_idle_pol = 1: + 0: stereo + * 1: Both slots transmit right + * 2: Both slots transmit left + * 3: Right transmits `conf_single_data` left transmits data + * 4: Left transmits `conf_single_data` right transmits data + */ +static inline void i2s_ll_tx_set_pdm_chan_mod(i2s_dev_t *hw, uint32_t mod) +{ + hw->tx_conf.tx_chan_mod = mod; +} + +/** + * @brief Set TX WS signal pol level + * + * @param hw Peripheral I2S hardware instance address. + * @param ws_pol_level pin level of WS(output) when receiving left channel data + */ +static inline void i2s_ll_tx_set_ws_idle_pol(i2s_dev_t *hw, bool ws_pol_level) +{ + hw->tx_conf.tx_ws_idle_pol = ws_pol_level; +} + +/** + * @brief Set RX WS signal pol level + * + * @param hw Peripheral I2S hardware instance address. + * @param ws_pol_level pin level of WS(input) when receiving left channel data + */ +static inline void i2s_ll_rx_set_ws_idle_pol(i2s_dev_t *hw, bool ws_pol_level) +{ + hw->rx_conf.rx_ws_idle_pol = ws_pol_level; +} + +/** + * @brief Enable I2S TX TDM mode + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_tx_enable_tdm(i2s_dev_t *hw) +{ + hw->tx_conf.tx_pdm_en = false; + hw->tx_conf.tx_tdm_en = true; + hw->tx_pcm2pdm_conf.pcm2pdm_conv_en = false; +} + +/** + * @brief Enable I2S RX TDM mode + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_rx_enable_tdm(i2s_dev_t *hw) +{ + hw->rx_conf.rx_pdm_en = false; + hw->rx_conf.rx_tdm_en = true; +} + +/** + * @brief Enable I2S TX STD mode + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_tx_enable_std(i2s_dev_t *hw) +{ + i2s_ll_tx_enable_tdm(hw); +} + +/** + * @brief Enable I2S RX STD mode + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_rx_enable_std(i2s_dev_t *hw) +{ + i2s_ll_rx_enable_tdm(hw); +} + +/** + * @brief Enable TX PDM mode. + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_tx_enable_pdm(i2s_dev_t *hw) +{ + hw->tx_conf.tx_pdm_en = true; + hw->tx_conf.tx_tdm_en = false; + hw->tx_pcm2pdm_conf.pcm2pdm_conv_en = true; +} + +/** + * @brief Set I2S TX PDM prescale + * + * @param hw Peripheral I2S hardware instance address. + * @param prescale I2S TX PDM prescale + */ +static inline void i2s_ll_tx_set_pdm_prescale(i2s_dev_t *hw, bool prescale) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_pcm2pdm_conf, tx_pdm_prescale, prescale); +} + +/** + * @brief Set I2S TX PDM high pass filter scaling + * + * @param hw Peripheral I2S hardware instance address. + * @param sig_scale I2S TX PDM signal scaling before transmit to the filter + */ +static inline void i2s_ll_tx_set_pdm_hp_scale(i2s_dev_t *hw, i2s_pdm_sig_scale_t sig_scale) +{ + hw->tx_pcm2pdm_conf.tx_pdm_hp_in_shift = sig_scale; +} + +/** + * @brief Set I2S TX PDM low pass filter scaling + * + * @param hw Peripheral I2S hardware instance address. + * @param sig_scale I2S TX PDM signal scaling before transmit to the filter + */ +static inline void i2s_ll_tx_set_pdm_lp_scale(i2s_dev_t *hw, i2s_pdm_sig_scale_t sig_scale) +{ + hw->tx_pcm2pdm_conf.tx_pdm_lp_in_shift = sig_scale; +} + +/** + * @brief Set I2S TX PDM sinc filter scaling + * + * @param hw Peripheral I2S hardware instance address. + * @param sig_scale I2S TX PDM signal scaling before transmit to the filter + */ +static inline void i2s_ll_tx_set_pdm_sinc_scale(i2s_dev_t *hw, i2s_pdm_sig_scale_t sig_scale) +{ + hw->tx_pcm2pdm_conf.tx_pdm_sinc_in_shift = sig_scale; +} + +/** + * @brief Set I2S TX PDM sigma-delta filter scaling + * + * @param hw Peripheral I2S hardware instance address. + * @param sig_scale I2S TX PDM signal scaling before transmit to the filter + */ +static inline void i2s_ll_tx_set_pdm_sd_scale(i2s_dev_t *hw, i2s_pdm_sig_scale_t sig_scale) +{ + hw->tx_pcm2pdm_conf.tx_pdm_sigmadelta_in_shift = sig_scale; +} + +/** + * @brief Set I2S TX PDM high pass filter param0 + * + * @param hw Peripheral I2S hardware instance address. + * @param param The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0]) + */ +static inline void i2s_ll_tx_set_pdm_hp_filter_param0(i2s_dev_t *hw, uint32_t param) +{ + hw->tx_pcm2pdm_conf1.tx_iir_hp_mult12_0 = param; +} + +/** + * @brief Set I2S TX PDM high pass filter param5 + * + * @param hw Peripheral I2S hardware instance address. + * @param param The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0]) + */ +static inline void i2s_ll_tx_set_pdm_hp_filter_param5(i2s_dev_t *hw, uint32_t param) +{ + hw->tx_pcm2pdm_conf1.tx_iir_hp_mult12_5 = param; +} + +/** + * @brief Enable I2S TX PDM high pass filter + * + * @param hw Peripheral I2S hardware instance address. + * @param enable Set true to enable I2S TX PDM high pass filter, set false to bypass it + */ +static inline void i2s_ll_tx_enable_pdm_hp_filter(i2s_dev_t *hw, bool enable) +{ + hw->tx_pcm2pdm_conf.tx_pdm_hp_bypass = !enable; +} + +/** + * @brief Set I2S TX PDM sigma-delta codec dither + * + * @param hw Peripheral I2S hardware instance address. + * @param dither I2S TX PDM sigmadelta dither value + */ +static inline void i2s_ll_tx_set_pdm_sd_dither(i2s_dev_t *hw, uint32_t dither) +{ + hw->tx_pcm2pdm_conf.tx_pdm_sigmadelta_dither = dither; +} + +/** + * @brief Set I2S TX PDM sigma-delta codec dither + * + * @param hw Peripheral I2S hardware instance address. + * @param dither2 I2S TX PDM sigmadelta dither2 value + */ +static inline void i2s_ll_tx_set_pdm_sd_dither2(i2s_dev_t *hw, uint32_t dither2) +{ + hw->tx_pcm2pdm_conf.tx_pdm_sigmadelta_dither2 = dither2; +} + +/** + * @brief Configure I2S TX PDM sample rate + * Fpdm = 64*Fpcm*fp/fs + * + * @param hw Peripheral I2S hardware instance address. + * @param fp The fp value of TX PDM filter module group0. + * @param fs The fs value of TX PDM filter module group0. + */ +static inline void i2s_ll_tx_set_pdm_fpfs(i2s_dev_t *hw, uint32_t fp, uint32_t fs) +{ + hw->tx_pcm2pdm_conf1.tx_pdm_fp = fp; + hw->tx_pcm2pdm_conf1.tx_pdm_fs = fs; + hw->tx_pcm2pdm_conf.tx_pdm_sinc_osr2 = fp / fs; +} + +/** + * @brief Get I2S TX PDM fp configuration paramater + * + * @param hw Peripheral I2S hardware instance address. + * @return + * - fp configuration paramater + */ +static inline uint32_t i2s_ll_tx_get_pdm_fp(i2s_dev_t *hw) +{ + return hw->tx_pcm2pdm_conf1.tx_pdm_fp; +} + +/** + * @brief Get I2S TX PDM fs configuration paramater + * + * @param hw Peripheral I2S hardware instance address. + * @return + * - fs configuration paramater + */ +static inline uint32_t i2s_ll_tx_get_pdm_fs(i2s_dev_t *hw) +{ + return hw->tx_pcm2pdm_conf1.tx_pdm_fs; +} + +/** + * @brief Enable RX PDM mode. + * @note ESP32-C6 doesn't support pdm in rx mode, disable anyway + * + * @param hw Peripheral I2S hardware instance address. + * @param pdm_enable Set true to RX enable PDM mode (ignored) + */ +static inline void i2s_ll_rx_enable_pdm(i2s_dev_t *hw, bool pdm_enable) +{ + hw->rx_conf.rx_pdm_en = 0; + hw->rx_conf.rx_tdm_en = 1; +} + +/** + * @brief Configura TX a/u-law decompress or compress + * + * @param hw Peripheral I2S hardware instance address. + * @param pcm_cfg PCM configuration paramater + */ +static inline void i2s_ll_tx_set_pcm_type(i2s_dev_t *hw, i2s_pcm_compress_t pcm_cfg) +{ + hw->tx_conf.tx_pcm_conf = pcm_cfg; + hw->tx_conf.tx_pcm_bypass = !pcm_cfg; +} + +/** + * @brief Configure RX a/u-law decompress or compress + * + * @param hw Peripheral I2S hardware instance address. + * @param pcm_cfg PCM configuration paramater + */ +static inline void i2s_ll_rx_set_pcm_type(i2s_dev_t *hw, i2s_pcm_compress_t pcm_cfg) +{ + hw->rx_conf.rx_pcm_conf = pcm_cfg; + hw->rx_conf.rx_pcm_bypass = !pcm_cfg; +} + +/** + * @brief Enable TX audio data left alignment + * + * @param hw Peripheral I2S hardware instance address. + * @param ena Set true to enable left alignment + */ +static inline void i2s_ll_tx_enable_left_align(i2s_dev_t *hw, bool ena) +{ + hw->tx_conf.tx_left_align = ena; +} + +/** + * @brief Enable RX audio data left alignment + * + * @param hw Peripheral I2S hardware instance address. + * @param ena Set true to enable left alignment + */ +static inline void i2s_ll_rx_enable_left_align(i2s_dev_t *hw, bool ena) +{ + hw->rx_conf.rx_left_align = ena; +} + +/** + * @brief Enable TX big endian mode + * + * @param hw Peripheral I2S hardware instance address. + * @param ena Set true to enable big endian mode + */ +static inline void i2s_ll_rx_enable_big_endian(i2s_dev_t *hw, bool ena) +{ + hw->rx_conf.rx_big_endian = ena; +} + +/** + * @brief Enable RX big endian mode + * + * @param hw Peripheral I2S hardware instance address. + * @param ena Set true to enable big endian mode + */ +static inline void i2s_ll_tx_enable_big_endian(i2s_dev_t *hw, bool ena) +{ + hw->tx_conf.tx_big_endian = ena; +} + +/** + * @brief Configure TX bit order + * + * @param hw Peripheral I2S hardware instance address. + * @param lsb_order_ena Set true to enable LSB bit order + */ +static inline void i2s_ll_tx_set_bit_order(i2s_dev_t *hw, bool lsb_order_ena) +{ + hw->tx_conf.tx_bit_order = lsb_order_ena; +} + +/** + * @brief Configure RX bit order + * + * @param hw Peripheral I2S hardware instance address. + * @param lsb_order_ena Set true to enable LSB bit order + */ +static inline void i2s_ll_rx_set_bit_order(i2s_dev_t *hw, bool lsb_order_ena) +{ + hw->rx_conf.rx_bit_order = lsb_order_ena; +} + +/** + * @brief Configure TX skip mask enable + * + * @param hw Peripheral I2S hardware instance address. + * @param skip_mask_ena Set true to skip inactive channels. + */ +static inline void i2s_ll_tx_set_skip_mask(i2s_dev_t *hw, bool skip_mask_ena) +{ + hw->tx_tdm_ctrl.tx_tdm_skip_msk_en = skip_mask_ena; +} + + +/** + * @brief Configure single data + * + * @param hw Peripheral I2S hardware instance address. + * @param data Single data to be set + */ +static inline void i2s_ll_set_single_data(i2s_dev_t *hw, uint32_t data) +{ + hw->conf_single_data.val = data; +} + +/** + * @brief Enable TX mono mode + * @note MONO in hardware means only one channel got data, but another doesn't + * MONO in software means two channel share same data + * This function aims to use MONO in software meaning + * so 'tx_mono' and 'tx_chan_equal' should be enabled at the same time + * + * @param hw Peripheral I2S hardware instance address. + * @param mono_ena Set true to enable mono mde. + */ +static inline void i2s_ll_tx_enable_mono_mode(i2s_dev_t *hw, bool mono_ena) +{ + hw->tx_conf.tx_mono = mono_ena; + hw->tx_conf.tx_chan_equal = mono_ena; +} + +/** + * @brief Enable RX mono mode + * + * @param hw Peripheral I2S hardware instance address. + * @param mono_ena Set true to enable mono mde. + */ +static inline void i2s_ll_rx_enable_mono_mode(i2s_dev_t *hw, bool mono_ena) +{ + hw->rx_conf.rx_mono = mono_ena; + hw->rx_conf.rx_mono_fst_vld = mono_ena; +} + +/** + * @brief Enable loopback mode + * + * @param hw Peripheral I2S hardware instance address. + * @param ena Set true to share BCK and WS signal for tx module and rx module. + */ +static inline void i2s_ll_share_bck_ws(i2s_dev_t *hw, bool ena) +{ + hw->tx_conf.sig_loopback = ena; +} + +/** + * @brief PDM TX DMA data take mode + * + * @param hw Peripheral I2S hardware instance address. + * @param is_mono The DMA data only has one slot (mono) or contains two slots (stereo) + * @param is_fst_valid Whether take the DMA data at the first half period + * Only take effet when 'is_mono' is true + */ +static inline void i2s_ll_tx_pdm_dma_take_mode(i2s_dev_t *hw, bool is_mono, bool is_fst_valid) +{ + hw->tx_conf.tx_mono = is_mono; + hw->tx_conf.tx_mono_fst_vld = is_fst_valid; +} + +/** + * @brief PDM TX slot mode + * @note Mode Left Slot Right Slot Chan Mode WS Pol + * ----------------------------------------------------------------- + * Stereo Left Right 0 x + * ----------------------------------------------------------------- + * Mono Left Left 1 0 + * Mono Right Right 2 0 + * Mono Single Right 3 0 + * Mono Left Single 4 0 + * ----------------------------------------------------------------- + * Mono Right Right 1 1 + * Mono Left Left 2 1 + * Mono Left Single 3 1 + * Mono Single Right 4 1 + * @note The 'Single' above means always sending the value of `conf_single_data` reg + * The default value of `conf_single_data` reg is '0', it is not public for now + * + * @param hw Peripheral I2S hardware instance address. + * @param is_mono The DMA data only has one slot (mono) or contains two slots (stereo) + * @param is_copy Whether the un-selected slot copies the data from the selected one + * If not, the un-selected slot will transmit the data from 'conf_single_data' + * @param mask The slot mask to selet the slot + */ +static inline void i2s_ll_tx_pdm_slot_mode(i2s_dev_t *hw, bool is_mono, bool is_copy, i2s_pdm_slot_mask_t mask) +{ + if (is_mono) { + /* The default tx_ws_idle_pol is false */ + if (is_copy) { + hw->tx_conf.tx_chan_mod = mask == I2S_PDM_SLOT_LEFT ? 1 : 2; + } else { + hw->tx_conf.tx_chan_mod = mask == I2S_PDM_SLOT_LEFT ? 4 : 3; + } + } else { + hw->tx_conf.tx_chan_mod = 0; + } +} + +/** + * @brief PDM TX line mode + * @note Mode DAC Mode 2 lines output + * ------------------------------------------- + * PDM codec 0 1 + * DAC 1-line 1 0 + * DAC 2-line 1 1 + * + * @param hw Peripheral I2S hardware instance address. + * @param line_mode PDM TX line mode + */ +static inline void i2s_ll_tx_pdm_line_mode(i2s_dev_t *hw, i2s_pdm_tx_line_mode_t line_mode) +{ + hw->tx_pcm2pdm_conf.tx_pdm_dac_mode_en = line_mode > I2S_PDM_TX_ONE_LINE_CODEC; + hw->tx_pcm2pdm_conf.tx_pdm_dac_2out_en = line_mode != I2S_PDM_TX_ONE_LINE_DAC; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/lpwdt_ll.h b/components/hal/esp32c6/include/hal/lpwdt_ll.h new file mode 100644 index 0000000000..504b112014 --- /dev/null +++ b/components/hal/esp32c6/include/hal/lpwdt_ll.h @@ -0,0 +1,307 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for Timer Group register operations. +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "hal/misc.h" +#include "hal/wdt_types.h" +#include "soc/rtc_cntl_periph.h" +#include "soc/efuse_reg.h" +#include "esp_attr.h" + +#include "esp32c6/rom/ets_sys.h" + +// TODO: IDF-5717 +// //Type check wdt_stage_action_t +// _Static_assert(WDT_STAGE_ACTION_OFF == RTC_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +// _Static_assert(WDT_STAGE_ACTION_INT == RTC_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +// _Static_assert(WDT_STAGE_ACTION_RESET_CPU == RTC_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +// _Static_assert(WDT_STAGE_ACTION_RESET_SYSTEM == RTC_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +// _Static_assert(WDT_STAGE_ACTION_RESET_RTC == RTC_WDT_STG_SEL_RESET_RTC, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +// //Type check wdt_reset_sig_length_t +// _Static_assert(WDT_RESET_SIG_LENGTH_100ns == RTC_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +// _Static_assert(WDT_RESET_SIG_LENGTH_200ns == RTC_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +// _Static_assert(WDT_RESET_SIG_LENGTH_300ns == RTC_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +// _Static_assert(WDT_RESET_SIG_LENGTH_400ns == RTC_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +// _Static_assert(WDT_RESET_SIG_LENGTH_500ns == RTC_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +// _Static_assert(WDT_RESET_SIG_LENGTH_800ns == RTC_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +// _Static_assert(WDT_RESET_SIG_LENGTH_1_6us == RTC_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +// _Static_assert(WDT_RESET_SIG_LENGTH_3_2us == RTC_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); + +/** + * @brief Enable the RWDT + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void lpwdt_ll_enable(lp_wdt_dev_t *hw) +{ + hw->config0.wdt_en = 1; +} + +/** + * @brief Disable the RWDT + * + * @param hw Start address of the peripheral registers. + * @note This function does not disable the flashboot mode. Therefore, given that + * the MWDT is disabled using this function, a timeout can still occur + * if the flashboot mode is simultaneously enabled. + */ +FORCE_INLINE_ATTR void lpwdt_ll_disable(lp_wdt_dev_t *hw) +{ + hw->config0.wdt_en = 0; +} + +/** + * @brief Check if the RWDT is enabled + * + * @param hw Start address of the peripheral registers. + * @return True if RTC WDT is enabled + */ +FORCE_INLINE_ATTR bool lpwdt_ll_check_if_enabled(lp_wdt_dev_t *hw) +{ + return (hw->config0.wdt_en) ? true : false; +} + +/** + * @brief Configure a particular stage of the RWDT + * + * @param hw Start address of the peripheral registers. + * @param stage Which stage to configure + * @param timeout Number of timer ticks for the stage to timeout (see note). + * @param behavior What action to take when the stage times out + * + * @note The value of of RWDT stage 0 timeout register is special, in + * that an implicit multiplier is applied to that value to produce + * and effective timeout tick value. The multiplier is dependent + * on an EFuse value. Therefore, when configuring stage 0, the valid + * values for the timeout argument are: + * - If Efuse value is 0, any even number between [2,2*UINT32_MAX] + * - If Efuse value is 1, any multiple of 4 between [4,4*UINT32_MAX] + * - If Efuse value is 2, any multiple of 8 between [8,8*UINT32_MAX] + * - If Efuse value is 3, any multiple of 16 between [16,16*UINT32_MAX] + */ +FORCE_INLINE_ATTR void lpwdt_ll_config_stage(lp_wdt_dev_t *hw, wdt_stage_t stage, uint32_t timeout_ticks, wdt_stage_action_t behavior) +{ + switch (stage) { + case WDT_STAGE0: + hw->config0.wdt_stg0 = behavior; + //Account of implicty multiplier applied to stage 0 timeout tick config value + hw->config1.val = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL)); + break; + case WDT_STAGE1: + hw->config0.wdt_stg1 = behavior; + hw->config2.val = timeout_ticks; + break; + case WDT_STAGE2: + hw->config0.wdt_stg2 = behavior; + hw->config3.val = timeout_ticks; + break; + case WDT_STAGE3: + hw->config0.wdt_stg3 = behavior; + hw->config4.val = timeout_ticks; + break; + default: + abort(); + } +} + +/** + * @brief Disable a particular stage of the RWDT + * + * @param hw Start address of the peripheral registers. + * @param stage Which stage to disable + */ +FORCE_INLINE_ATTR void lpwdt_ll_disable_stage(lp_wdt_dev_t *hw, wdt_stage_t stage) +{ + switch (stage) { + case WDT_STAGE0: + hw->config0.wdt_stg0 = WDT_STAGE_ACTION_OFF; + break; + case WDT_STAGE1: + hw->config0.wdt_stg1 = WDT_STAGE_ACTION_OFF; + break; + case WDT_STAGE2: + hw->config0.wdt_stg2 = WDT_STAGE_ACTION_OFF; + break; + case WDT_STAGE3: + hw->config0.wdt_stg3 = WDT_STAGE_ACTION_OFF; + break; + default: + abort(); + } +} + +/** + * @brief Set the length of the CPU reset action + * + * @param hw Start address of the peripheral registers. + * @param length Length of CPU reset signal + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_cpu_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length) +{ + hw->config0.wdt_cpu_reset_length = length; +} + +/** + * @brief Set the length of the system reset action + * + * @param hw Start address of the peripheral registers. + * @param length Length of system reset signal + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_sys_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length) +{ + hw->config0.wdt_sys_reset_length = length; +} + +/** + * @brief Enable/Disable the RWDT flashboot mode. + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable RWDT flashboot mode, false to disable RWDT flashboot mode. + * + * @note Flashboot mode is independent and can trigger a WDT timeout event if the + * WDT's enable bit is set to 0. Flashboot mode for RWDT is automatically enabled + * on flashboot, and should be disabled by software when flashbooting completes. + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_flashboot_en(lp_wdt_dev_t *hw, bool enable) +{ + hw->config0.wdt_flashboot_mod_en = (enable) ? 1 : 0; +} + +/** + * @brief Enable/Disable the CPU0 to be reset on WDT_STAGE_ACTION_RESET_CPU + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable CPU0 to be reset, false to disable. + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_procpu_reset_en(lp_wdt_dev_t *hw, bool enable) +{ + hw->config0.wdt_procpu_reset_en = (enable) ? 1 : 0; +} + +/** + * @brief Enable/Disable the CPU1 to be reset on WDT_STAGE_ACTION_RESET_CPU + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable CPU1 to be reset, false to disable. + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_appcpu_reset_en(lp_wdt_dev_t *hw, bool enable) +{ + hw->config0.wdt_appcpu_reset_en = (enable) ? 1 : 0; +} + +/** + * @brief Enable/Disable the RWDT pause during sleep functionality + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable, false to disable. + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_pause_in_sleep_en(lp_wdt_dev_t *hw, bool enable) +{ + hw->config0.wdt_pause_in_slp = (enable) ? 1 : 0; +} + +/** + * @brief Enable/Disable chip reset on RWDT timeout. + * + * A chip reset also resets the analog portion of the chip. It will appear as a + * POWERON reset rather than an RTC reset. + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable, false to disable. + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_en(lp_wdt_dev_t *hw, bool enable) +{ + hw->config0.wdt_chip_reset_en = (enable) ? 1 : 0; +} + +/** + * @brief Set width of chip reset signal + * + * @param hw Start address of the peripheral registers. + * @param width Width of chip reset signal in terms of number of RTC_SLOW_CLK cycles + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_width(lp_wdt_dev_t *hw, uint32_t width) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->config0, wdt_chip_reset_width, width); +} + +/** + * @brief Feed the RWDT + * + * Resets the current timer count and current stage. + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void lpwdt_ll_feed(lp_wdt_dev_t *hw) +{ + hw->feed.rtc_wdt_feed = 1; +} + +/** + * @brief Enable write protection of the RWDT registers + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void lpwdt_ll_write_protect_enable(lp_wdt_dev_t *hw) +{ + hw->wprotect.val = 0; +} + +/** + * @brief Disable write protection of the RWDT registers + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void lpwdt_ll_write_protect_disable(lp_wdt_dev_t *hw) +{ + hw->wprotect.val = RTC_CNTL_WDT_WKEY_VALUE; +} + +/** + * @brief Enable the RWDT interrupt. + * + * @param hw Start address of the peripheral registers. + * @param enable True to enable RWDT interrupt, false to disable. + */ +FORCE_INLINE_ATTR void lpwdt_ll_set_intr_enable(lp_wdt_dev_t *hw, bool enable) +{ + hw->int_ena.lp_wdt_int_ena = (enable) ? 1 : 0; +} + +/** + * @brief Check if the RWDT interrupt has been triggered + * + * @param hw Start address of the peripheral registers. + * @return True if the RWDT interrupt was triggered + */ +FORCE_INLINE_ATTR bool lpwdt_ll_check_intr_status(lp_wdt_dev_t *hw) +{ + return (hw->int_st.lp_wdt_int_st) ? true : false; +} + +/** + * @brief Clear the RWDT interrupt status. + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void lpwdt_ll_clear_intr_status(lp_wdt_dev_t *hw) +{ + hw->int_clr.lp_wdt_int_clr = 1; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/mmu_ll.h b/components/hal/esp32c6/include/hal/mmu_ll.h new file mode 100644 index 0000000000..15a90902e2 --- /dev/null +++ b/components/hal/esp32c6/include/hal/mmu_ll.h @@ -0,0 +1,239 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for MMU register operations + +#pragma once + +#include "soc/spi_mem_reg.h" +#include "soc/ext_mem_defs.h" +#include "hal/assert.h" +#include "hal/mmu_types.h" +#include "hal/efuse_ll.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief The real MMU page size get from Kconfig. + * + * @note Only used in this file + */ +#define MMU_LL_PAGE_SIZE (CONFIG_MMU_PAGE_SIZE) + +__attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void) +{ + unsigned cnt = efuse_ll_get_flash_crypt_cnt(); + // 3 bits wide, any odd number - 1 or 3 - bits set means encryption is on + cnt = ((cnt >> 2) ^ (cnt >> 1) ^ cnt) & 0x1; + return (cnt == 1); +} + +/** + * Get MMU page size + * + * @param mmu_id MMU ID + * + * @return MMU page size code + */ +__attribute__((always_inline)) +static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id) +{ + (void)mmu_id; + uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE); + return (page_size_code == 0) ? MMU_PAGE_64KB : \ + (page_size_code == 1) ? MMU_PAGE_32KB : \ + (page_size_code == 2) ? MMU_PAGE_16KB : \ + MMU_PAGE_8KB; +} + +/** + * Set MMU page size + * + * @param size MMU page size + */ +__attribute__((always_inline)) +static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size) +{ + uint8_t reg_val = (size == MMU_PAGE_64KB) ? 0 : \ + (size == MMU_PAGE_32KB) ? 1 : \ + (size == MMU_PAGE_16KB) ? 2 : \ + (size == MMU_PAGE_8KB) ? 3 : 0; + REG_SET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE, reg_val); +} + +/** + * Check if the external memory vaddr region is valid + * + * @param mmu_id MMU ID + * @param vaddr_start start of the virtual address + * @param len length, in bytes + * + * @return + * True for valid + */ +__attribute__((always_inline)) +static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len) +{ + (void)mmu_id; + uint32_t vaddr_end = vaddr_start + len; + return (ADDRESS_IN_IRAM0_CACHE(vaddr_start, MMU_LL_PAGE_SIZE) && ADDRESS_IN_IRAM0_CACHE(vaddr_end, MMU_LL_PAGE_SIZE)) || (ADDRESS_IN_DRAM0_CACHE(vaddr_start, MMU_LL_PAGE_SIZE) && ADDRESS_IN_DRAM0_CACHE(vaddr_end, MMU_LL_PAGE_SIZE)); +} + +/** + * To get the MMU table entry id to be mapped + * + * @param mmu_id MMU ID + * @param vaddr virtual address to be mapped + * + * @return + * MMU table entry id + */ +__attribute__((always_inline)) +static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) +{ + (void)mmu_id; + mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); + uint32_t shift_code = 0; + switch (page_size) { + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + default: + HAL_ASSERT(shift_code); + } + return ((vaddr & MMU_VADDR_MASK(page_size)) >> shift_code); +} + +/** + * Format the paddr to be mappable + * + * @param mmu_id MMU ID + * @param paddr physical address to be mapped + * + * @return + * mmu_val - paddr in MMU table supported format + */ +__attribute__((always_inline)) +static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr) +{ + (void)mmu_id; + mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); + uint32_t shift_code = 0; + switch (page_size) { + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + default: + HAL_ASSERT(shift_code); + } + return paddr >> shift_code; +} + +/** + * Write to the MMU table to map the virtual memory and the physical memory + * + * @param mmu_id MMU ID + * @param entry_id MMU entry ID + * @param mmu_val Value to be set into an MMU entry, for physical address + * @param target MMU target physical memory. + */ +__attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target) +{ + (void)mmu_id; + (void)target; + uint32_t mmu_raw_value; + if (mmu_ll_cache_encryption_enabled()) { + mmu_val |= MMU_SENSITIVE; + } + /* Note: for ESP32-C6, invert invalid bit for compatible with upper-layer software */ + mmu_raw_value = mmu_val ^ MMU_INVALID_MASK; + REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); + REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value); +} + +/** + * Read the raw value from MMU table + * + * @param mmu_id MMU ID + * @param entry_id MMU entry ID + * @param mmu_val Value to be read from MMU table + */ +__attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id) +{ + (void)mmu_id; + uint32_t mmu_raw_value; + uint32_t ret; + REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); + mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)); + if (mmu_ll_cache_encryption_enabled()) { + mmu_raw_value &= ~MMU_SENSITIVE; + } + /* Note: for ESP32-C6, invert invalid bit for compatible with upper-layer software */ + ret = mmu_raw_value ^ MMU_INVALID_MASK; + return ret; +} + +/** + * Set MMU table entry as invalid + * + * @param mmu_id MMU ID + * @param entry_id MMU entry + */ +__attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) +{ + (void)mmu_id; + REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); + REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), MMU_INVALID); +} + +/** + * Get MMU table entry is invalid + * + * @param mmu_id MMU ID + * @param entry_id MMU entry ID + * return ture for MMU entry is invalid, false for valid + */ +__attribute__((always_inline)) static inline bool mmu_ll_get_entry_is_invalid(uint32_t mmu_id, uint32_t entry_id) +{ + (void)mmu_id; + uint32_t mmu_raw_value; + REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); + mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)); + /* Note: for ESP32-C6, the invalid-bit of MMU: 0 for invalid, 1 for valid */ + return (mmu_raw_value & MMU_INVALID_MASK) ? false : true; +} + +/** + * Unmap all the items in the MMU table + * + * @param mmu_id MMU ID + */ +__attribute__((always_inline)) +static inline void mmu_ll_unmap_all(uint32_t mmu_id) +{ + for (int i = 0; i < MMU_ENTRY_NUM; i++) { + mmu_ll_set_entry_invalid(mmu_id, i); + } +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/mpu_ll.h b/components/hal/esp32c6/include/hal/mpu_ll.h new file mode 100644 index 0000000000..d90dc01368 --- /dev/null +++ b/components/hal/esp32c6/include/hal/mpu_ll.h @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include "soc/soc_caps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Copied from C3, and this LL is currently unused for ESP32-C3 */ + +static inline uint32_t mpu_ll_id_to_addr(unsigned id) +{ + abort(); +} + +static inline void mpu_ll_set_region_rw(uint32_t addr) +{ + abort(); +} + +static inline void mpu_ll_set_region_rwx(uint32_t addr) +{ + abort(); +} + +static inline void mpu_ll_set_region_x(uint32_t addr) +{ + abort(); +} + + +static inline void mpu_ll_set_region_illegal(uint32_t addr) +{ + abort(); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/mwdt_ll.h b/components/hal/esp32c6/include/hal/mwdt_ll.h new file mode 100644 index 0000000000..6bc12709b8 --- /dev/null +++ b/components/hal/esp32c6/include/hal/mwdt_ll.h @@ -0,0 +1,253 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for Timer Group register operations. +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "soc/timer_periph.h" +#include "soc/timer_group_struct.h" +#include "hal/wdt_types.h" +#include "hal/assert.h" +#include "esp_attr.h" +#include "hal/misc.h" + +//Type check wdt_stage_action_t +_Static_assert(WDT_STAGE_ACTION_OFF == TIMG_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +_Static_assert(WDT_STAGE_ACTION_INT == TIMG_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +_Static_assert(WDT_STAGE_ACTION_RESET_CPU == TIMG_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +_Static_assert(WDT_STAGE_ACTION_RESET_SYSTEM == TIMG_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); +//Type check wdt_reset_sig_length_t +_Static_assert(WDT_RESET_SIG_LENGTH_100ns == TIMG_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +_Static_assert(WDT_RESET_SIG_LENGTH_200ns == TIMG_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +_Static_assert(WDT_RESET_SIG_LENGTH_300ns == TIMG_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +_Static_assert(WDT_RESET_SIG_LENGTH_400ns == TIMG_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +_Static_assert(WDT_RESET_SIG_LENGTH_500ns == TIMG_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +_Static_assert(WDT_RESET_SIG_LENGTH_800ns == TIMG_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +_Static_assert(WDT_RESET_SIG_LENGTH_1_6us == TIMG_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); +_Static_assert(WDT_RESET_SIG_LENGTH_3_2us == TIMG_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); + +/** + * @brief Enable the MWDT + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void mwdt_ll_enable(timg_dev_t *hw) +{ + hw->wdtconfig0.wdt_en = 1; +} + +/** + * @brief Disable the MWDT + * + * @param hw Start address of the peripheral registers. + * @note This function does not disable the flashboot mode. Therefore, given that + * the MWDT is disabled using this function, a timeout can still occur + * if the flashboot mode is simultaneously enabled. + */ +FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw) +{ + hw->wdtconfig0.wdt_en = 0; +} + +/** + * Check if the MWDT is enabled + * + * @param hw Start address of the peripheral registers. + * @return True if the MWDT is enabled, false otherwise + */ +FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw) +{ + return (hw->wdtconfig0.wdt_en) ? true : false; +} + +/** + * @brief Configure a particular stage of the MWDT + * + * @param hw Start address of the peripheral registers. + * @param stage Which stage to configure + * @param timeout Number of timer ticks for the stage to timeout + * @param behavior What action to take when the stage times out + */ +FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_t stage, uint32_t timeout, wdt_stage_action_t behavior) +{ + switch (stage) { + case WDT_STAGE0: + hw->wdtconfig0.wdt_stg0 = behavior; + hw->wdtconfig2.wdt_stg0_hold = timeout; + break; + case WDT_STAGE1: + hw->wdtconfig0.wdt_stg1 = behavior; + hw->wdtconfig3.wdt_stg1_hold = timeout; + break; + case WDT_STAGE2: + hw->wdtconfig0.wdt_stg2 = behavior; + hw->wdtconfig4.wdt_stg2_hold = timeout; + break; + case WDT_STAGE3: + hw->wdtconfig0.wdt_stg3 = behavior; + hw->wdtconfig5.wdt_stg3_hold = timeout; + break; + default: + HAL_ASSERT(false && "unsupported WDT stage"); + break; + } + //Config registers are updated asynchronously + hw->wdtconfig0.wdt_conf_update_en = 1; +} + +/** + * @brief Disable a particular stage of the MWDT + * + * @param hw Start address of the peripheral registers. + * @param stage Which stage to disable + */ +FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage) +{ + switch (stage) { + case WDT_STAGE0: + hw->wdtconfig0.wdt_stg0 = WDT_STAGE_ACTION_OFF; + break; + case WDT_STAGE1: + hw->wdtconfig0.wdt_stg1 = WDT_STAGE_ACTION_OFF; + break; + case WDT_STAGE2: + hw->wdtconfig0.wdt_stg2 = WDT_STAGE_ACTION_OFF; + break; + case WDT_STAGE3: + hw->wdtconfig0.wdt_stg3 = WDT_STAGE_ACTION_OFF; + break; + default: + HAL_ASSERT(false && "unsupported WDT stage"); + break; + } + //Config registers are updated asynchronously + hw->wdtconfig0.wdt_conf_update_en = 1; +} + +/** + * @brief Set the length of the CPU reset action + * + * @param hw Start address of the peripheral registers. + * @param length Length of CPU reset signal + */ +FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length) +{ + hw->wdtconfig0.wdt_cpu_reset_length = length; + //Config registers are updated asynchronously + hw->wdtconfig0.wdt_conf_update_en = 1; +} + +/** + * @brief Set the length of the system reset action + * + * @param hw Start address of the peripheral registers. + * @param length Length of system reset signal + */ +FORCE_INLINE_ATTR void mwdt_ll_set_sys_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length) +{ + hw->wdtconfig0.wdt_sys_reset_length = length; + //Config registers are updated asynchronously + hw->wdtconfig0.wdt_conf_update_en = 1; +} + +/** + * @brief Enable/Disable the MWDT flashboot mode. + * + * @param hw Beginning address of the peripheral registers. + * @param enable True to enable WDT flashboot mode, false to disable WDT flashboot mode. + * + * @note Flashboot mode is independent and can trigger a WDT timeout event if the + * WDT's enable bit is set to 0. Flashboot mode for TG0 is automatically enabled + * on flashboot, and should be disabled by software when flashbooting completes. + */ +FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable) +{ + hw->wdtconfig0.wdt_flashboot_mod_en = (enable) ? 1 : 0; + //Config registers are updated asynchronously + hw->wdtconfig0.wdt_conf_update_en = 1; +} + +/** + * @brief Set the clock prescaler of the MWDT + * + * @param hw Start address of the peripheral registers. + * @param prescaler Prescaler value between 1 to 65535 + */ +FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler) +{ + // In case the compiler optimise a 32bit instruction (e.g. s32i) into 8/16bit instruction (e.g. s8i, which is not allowed to access a register) + // We take care of the "read-modify-write" procedure by ourselves. + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdtconfig1, wdt_clk_prescale, prescaler); + //Config registers are updated asynchronously + hw->wdtconfig0.wdt_conf_update_en = 1; +} + +/** + * @brief Feed the MWDT + * + * Resets the current timer count and current stage. + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw) +{ + hw->wdtfeed.wdt_feed = 1; +} + +/** + * @brief Enable write protection of the MWDT registers + * + * Locking the MWDT will prevent any of the MWDT's registers from being modified + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void mwdt_ll_write_protect_enable(timg_dev_t *hw) +{ + hw->wdtwprotect.wdt_wkey = 0; +} + +/** + * @brief Disable write protection of the MWDT registers + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw) +{ + hw->wdtwprotect.wdt_wkey = TIMG_WDT_WKEY_VALUE; +} + +/** + * @brief Clear the MWDT interrupt status. + * + * @param hw Start address of the peripheral registers. + */ +FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t *hw) +{ + hw->int_clr_timers.wdt_int_clr = 1; +} + +/** + * @brief Set the interrupt enable bit for the MWDT interrupt. + * + * @param hw Beginning address of the peripheral registers. + * @param enable Whether to enable the MWDT interrupt + */ +FORCE_INLINE_ATTR void mwdt_ll_set_intr_enable(timg_dev_t *hw, bool enable) +{ + hw->int_ena_timers.wdt_int_ena = (enable) ? 1 : 0; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/pcnt_ll.h b/components/hal/esp32c6/include/hal/pcnt_ll.h new file mode 100644 index 0000000000..963fbf7c73 --- /dev/null +++ b/components/hal/esp32c6/include/hal/pcnt_ll.h @@ -0,0 +1,426 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in hal/include/hal/readme.md + ******************************************************************************/ + +// The LL layer for ESP32-C6 PCNT register operations + +#pragma once + +#include +#include +#include +#include "soc/pcnt_struct.h" +#include "hal/pcnt_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define PCNT_LL_GET_HW(num) (((num) == 0) ? (&PCNT) : NULL) +#define PCNT_LL_MAX_GLITCH_WIDTH 1023 +#define PCNT_LL_MAX_LIM SHRT_MAX +#define PCNT_LL_MIN_LIN SHRT_MIN + +typedef enum { + PCNT_LL_WATCH_EVENT_INVALID = -1, + PCNT_LL_WATCH_EVENT_THRES1, + PCNT_LL_WATCH_EVENT_THRES0, + PCNT_LL_WATCH_EVENT_LOW_LIMIT, + PCNT_LL_WATCH_EVENT_HIGH_LIMIT, + PCNT_LL_WATCH_EVENT_ZERO_CROSS, + PCNT_LL_WATCH_EVENT_MAX +} pcnt_ll_watch_event_id_t; + +#define PCNT_LL_WATCH_EVENT_MASK ((1 << PCNT_LL_WATCH_EVENT_MAX) - 1) +#define PCNT_LL_UNIT_WATCH_EVENT(unit_id) (1 << (unit_id)) + +/** + * @brief Set PCNT channel edge action + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number + * @param channel PCNT channel number + * @param pos_act Counter action when detecting positive edge + * @param neg_act Counter action when detecting negative edge + */ +static inline void pcnt_ll_set_edge_action(pcnt_dev_t *hw, uint32_t unit, uint32_t channel, pcnt_channel_edge_action_t pos_act, pcnt_channel_edge_action_t neg_act) +{ + if (channel == 0) { + hw->conf_unit[unit].conf0.ch0_pos_mode = pos_act; + hw->conf_unit[unit].conf0.ch0_neg_mode = neg_act; + } else { + hw->conf_unit[unit].conf0.ch1_pos_mode = pos_act; + hw->conf_unit[unit].conf0.ch1_neg_mode = neg_act; + } +} + +/** + * @brief Set PCNT channel level action + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number + * @param channel PCNT channel number + * @param high_act Counter action when control signal is high level + * @param low_act Counter action when control signal is low level + */ +static inline void pcnt_ll_set_level_action(pcnt_dev_t *hw, uint32_t unit, uint32_t channel, pcnt_channel_level_action_t high_act, pcnt_channel_level_action_t low_act) +{ + if (channel == 0) { + hw->conf_unit[unit].conf0.ch0_hctrl_mode = high_act; + hw->conf_unit[unit].conf0.ch0_lctrl_mode = low_act; + } else { + hw->conf_unit[unit].conf0.ch1_hctrl_mode = high_act; + hw->conf_unit[unit].conf0.ch1_lctrl_mode = low_act; + } +} + +/** + * @brief Get pulse counter value + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit Pulse Counter unit number + * @return PCNT count value (a signed integer) + */ +__attribute__((always_inline)) +static inline int pcnt_ll_get_count(pcnt_dev_t *hw, uint32_t unit) +{ + pcnt_un_cnt_reg_t cnt_reg = hw->cnt_unit[unit]; + int16_t value = cnt_reg.pulse_cnt; + return value; +} + +/** + * @brief Pause PCNT counter of PCNT unit + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number + */ +__attribute__((always_inline)) +static inline void pcnt_ll_stop_count(pcnt_dev_t *hw, uint32_t unit) +{ + hw->ctrl.val |= 1 << (2 * unit + 1); +} + +/** + * @brief Resume counting for PCNT counter + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number, select from uint32_t + */ +__attribute__((always_inline)) +static inline void pcnt_ll_start_count(pcnt_dev_t *hw, uint32_t unit) +{ + hw->ctrl.val &= ~(1 << (2 * unit + 1)); +} + +/** + * @brief Clear PCNT counter value to zero + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number, select from uint32_t + */ +__attribute__((always_inline)) +static inline void pcnt_ll_clear_count(pcnt_dev_t *hw, uint32_t unit) +{ + hw->ctrl.val |= 1 << (2 * unit); + hw->ctrl.val &= ~(1 << (2 * unit)); +} + +/** + * @brief Enable PCNT interrupt for PCNT unit + * @note Each PCNT unit has five watch point events that share the same interrupt bit. + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit_mask PCNT units mask + * @param enable True to enable interrupt, False to disable interrupt + */ +static inline void pcnt_ll_enable_intr(pcnt_dev_t *hw, uint32_t unit_mask, bool enable) +{ + if (enable) { + hw->int_ena.val |= unit_mask; + } else { + hw->int_ena.val &= ~unit_mask; + } +} + +/** + * @brief Get PCNT interrupt status + * + * @param hw Peripheral PCNT hardware instance address. + * @return Interrupt status word + */ +__attribute__((always_inline)) +static inline uint32_t pcnt_ll_get_intr_status(pcnt_dev_t *hw) +{ + return hw->int_st.val; +} + +/** + * @brief Clear PCNT interrupt status + * + * @param hw Peripheral PCNT hardware instance address. + * @param status value to clear interrupt status + */ +__attribute__((always_inline)) +static inline void pcnt_ll_clear_intr_status(pcnt_dev_t *hw, uint32_t status) +{ + hw->int_clr.val = status; +} + +/** + * @brief Enable PCNT high limit event + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number + * @param enable true to enable, false to disable + */ +static inline void pcnt_ll_enable_high_limit_event(pcnt_dev_t *hw, uint32_t unit, bool enable) +{ + hw->conf_unit[unit].conf0.thr_h_lim_en = enable; +} + +/** + * @brief Enable PCNT low limit event + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number + * @param enable true to enable, false to disable + */ +static inline void pcnt_ll_enable_low_limit_event(pcnt_dev_t *hw, uint32_t unit, bool enable) +{ + hw->conf_unit[unit].conf0.thr_l_lim_en = enable; +} + +/** + * @brief Enable PCNT zero cross event + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number + * @param enable true to enable, false to disable + */ +static inline void pcnt_ll_enable_zero_cross_event(pcnt_dev_t *hw, uint32_t unit, bool enable) +{ + hw->conf_unit[unit].conf0.thr_zero_en = enable; +} + +/** + * @brief Enable PCNT threshold event + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number + * @param thres Threshold ID + * @param enable true to enable, false to disable + */ +static inline void pcnt_ll_enable_thres_event(pcnt_dev_t *hw, uint32_t unit, uint32_t thres, bool enable) +{ + if (thres == 0) { + hw->conf_unit[unit].conf0.thr_thres0_en = enable; + } else { + hw->conf_unit[unit].conf0.thr_thres1_en = enable; + } +} + +/** + * @brief Disable all PCNT threshold events + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit unit number + */ +static inline void pcnt_ll_disable_all_events(pcnt_dev_t *hw, uint32_t unit) +{ + hw->conf_unit[unit].conf0.val &= ~(PCNT_LL_WATCH_EVENT_MASK << 11); +} + +/** + * @brief Set PCNT high limit value + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number + * @param value PCNT high limit value + */ +static inline void pcnt_ll_set_high_limit_value(pcnt_dev_t *hw, uint32_t unit, int value) +{ + pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2; + conf2_reg.cnt_h_lim = value; + hw->conf_unit[unit].conf2 = conf2_reg; +} + +/** + * @brief Set PCNT low limit value + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number + * @param value PCNT low limit value + */ +static inline void pcnt_ll_set_low_limit_value(pcnt_dev_t *hw, uint32_t unit, int value) +{ + pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2; + conf2_reg.cnt_l_lim = value; + hw->conf_unit[unit].conf2 = conf2_reg; +} + +/** + * @brief Set PCNT threshold value + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number + * @param thres Threshold ID + * @param value PCNT threshold value + */ +static inline void pcnt_ll_set_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32_t thres, int value) +{ + pcnt_un_conf1_reg_t conf1_reg = hw->conf_unit[unit].conf1; + if (thres == 0) { + conf1_reg.cnt_thres0 = value; + } else { + conf1_reg.cnt_thres1 = value; + } + hw->conf_unit[unit].conf1 = conf1_reg; +} + +/** + * @brief Get PCNT high limit value + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number + * @return PCNT high limit value + */ +static inline int pcnt_ll_get_high_limit_value(pcnt_dev_t *hw, uint32_t unit) +{ + pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2; + int16_t value = conf2_reg.cnt_h_lim ; + return value; +} + +/** + * @brief Get PCNT low limit value + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number + * @return PCNT high limit value + */ +static inline int pcnt_ll_get_low_limit_value(pcnt_dev_t *hw, uint32_t unit) +{ + pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2; + int16_t value = conf2_reg.cnt_l_lim ; + return value; +} + +/** + * @brief Get PCNT threshold value + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number + * @param thres Threshold ID + * @return PCNT threshold value + */ +static inline int pcnt_ll_get_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32_t thres) +{ + int16_t value; + pcnt_un_conf1_reg_t conf1_reg = hw->conf_unit[unit].conf1; + if (thres == 0) { + value = conf1_reg.cnt_thres0 ; + } else { + value = conf1_reg.cnt_thres1 ; + } + return value; +} + +/** + * @brief Get PCNT unit runtime status + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number + * @return PCNT unit runtime status + */ +static inline uint32_t pcnt_ll_get_unit_status(pcnt_dev_t *hw, uint32_t unit) +{ + return hw->status_unit[unit].val; +} + +/** + * @brief Get PCNT zero cross mode + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number + * @return Zero cross mode + */ +__attribute__((always_inline)) +static inline pcnt_unit_zero_cross_mode_t pcnt_ll_get_zero_cross_mode(pcnt_dev_t *hw, uint32_t unit) +{ + return hw->status_unit[unit].val & 0x03; +} + +/** + * @brief Get PCNT event status + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number + * @return Event status word + */ +__attribute__((always_inline)) +static inline uint32_t pcnt_ll_get_event_status(pcnt_dev_t *hw, uint32_t unit) +{ + return hw->status_unit[unit].val >> 2; +} + +/** + * @brief Set PCNT glitch filter threshold + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number + * @param filter_val PCNT signal filter value, counter in APB_CLK cycles. + * Any pulses lasting shorter than this will be ignored when the filter is enabled. + */ +static inline void pcnt_ll_set_glitch_filter_thres(pcnt_dev_t *hw, uint32_t unit, uint32_t filter_val) +{ + hw->conf_unit[unit].conf0.filter_thres = filter_val; +} + +/** + * @brief Get PCNT glitch filter threshold + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number + * @return glitch filter threshold + */ +static inline uint32_t pcnt_ll_get_glitch_filter_thres(pcnt_dev_t *hw, uint32_t unit) +{ + return hw->conf_unit[unit].conf0.filter_thres ; +} + +/** + * @brief Enable PCNT glitch filter + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number + * @param enable True to enable the filter, False to disable the filter + */ +static inline void pcnt_ll_enable_glitch_filter(pcnt_dev_t *hw, uint32_t unit, bool enable) +{ + hw->conf_unit[unit].conf0.filter_en = enable; +} + +/** + * @brief Get interrupt status register address. + * + * @param hw Beginning address of the peripheral registers. + * + * @return Interrupt status register address + */ +static inline volatile void *pcnt_ll_get_intr_status_reg(pcnt_dev_t *hw) +{ + return &hw->int_st.val; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h new file mode 100644 index 0000000000..627f9745e8 --- /dev/null +++ b/components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h @@ -0,0 +1,62 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "soc/soc.h" +#include "soc/regi2c_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Reset (Disable) the I2C internal bus for all regi2c registers + */ +static inline void regi2c_ctrl_ll_i2c_reset(void) +{ + SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S); +} + +/** + * @brief Enable the I2C internal bus to do I2C read/write operation to the BBPLL configuration register + */ +static inline void regi2c_ctrl_ll_i2c_bbpll_enable(void) +{ + CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_BBPLL_M); +} + +/** + * @brief Start BBPLL self-calibration + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void) +{ + REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); + REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); +} + +/** + * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC register + */ +static inline void regi2c_ctrl_ll_i2c_saradc_enable(void) +{ + CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD); + SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU); +} + +/** + * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register + */ +static inline void regi2c_ctrl_ll_i2c_saradc_disable(void) +{ + CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PU); + SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PD); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/rmt_ll.h b/components/hal/esp32c6/include/hal/rmt_ll.h new file mode 100644 index 0000000000..35beca2c9c --- /dev/null +++ b/components/hal/esp32c6/include/hal/rmt_ll.h @@ -0,0 +1,849 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @note TX and RX channels are index from 0 in the LL driver, i.e. tx_channel = [0,1], rx_channel = [0,1] + */ + +#pragma once + +#include +#include +#include +#include "hal/misc.h" +#include "hal/assert.h" +#include "hal/rmt_types.h" +#include "soc/rmt_struct.h" +#include "soc/pcr_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define RMT_LL_EVENT_TX_DONE(channel) (1 << (channel)) +#define RMT_LL_EVENT_TX_THRES(channel) (1 << ((channel) + 8)) +#define RMT_LL_EVENT_TX_LOOP_END(channel) (1 << ((channel) + 12)) +#define RMT_LL_EVENT_TX_ERROR(channel) (1 << ((channel) + 4)) +#define RMT_LL_EVENT_RX_DONE(channel) (1 << ((channel) + 2)) +#define RMT_LL_EVENT_RX_THRES(channel) (1 << ((channel) + 10)) +#define RMT_LL_EVENT_RX_ERROR(channel) (1 << ((channel) + 6)) +#define RMT_LL_EVENT_TX_MASK(channel) (RMT_LL_EVENT_TX_DONE(channel) | RMT_LL_EVENT_TX_THRES(channel) | RMT_LL_EVENT_TX_LOOP_END(channel)) +#define RMT_LL_EVENT_RX_MASK(channel) (RMT_LL_EVENT_RX_DONE(channel) | RMT_LL_EVENT_RX_THRES(channel)) + +#define RMT_LL_MAX_LOOP_COUNT_PER_BATCH 1023 + +typedef enum { + RMT_LL_MEM_OWNER_SW = 0, + RMT_LL_MEM_OWNER_HW = 1, +} rmt_ll_mem_owner_t; + +/** + * @brief Enable clock gate for register and memory + * + * @param dev Peripheral instance address + * @param enable True to enable, False to disable + */ +static inline void rmt_ll_enable_periph_clock(rmt_dev_t *dev, bool enable) +{ + dev->sys_conf.clk_en = enable; // register clock gating + dev->sys_conf.mem_clk_force_on = enable; // memory clock gating +} + +/** + * @brief Power down memory + * + * @param dev Peripheral instance address + * @param enable True to power down, False to power up + */ +static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, bool enable) +{ + dev->sys_conf.mem_force_pu = !enable; + dev->sys_conf.mem_force_pd = enable; +} + +/** + * @brief Enable APB accessing RMT memory in nonfifo mode + * + * @param dev Peripheral instance address + * @param enable True to enable, False to disable + */ +static inline void rmt_ll_enable_mem_access_nonfifo(rmt_dev_t *dev, bool enable) +{ + dev->sys_conf.apb_fifo_mask = enable; +} + +/** + * @brief Set clock source and divider for RMT channel group + * + * @param dev Peripheral instance address + * @param channel not used as clock source is set for all channels + * @param src Clock source + * @param divider_integral Integral part of the divider + * @param divider_denominator Denominator part of the divider + * @param divider_numerator Numerator part of the divider + */ +static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, rmt_clock_source_t src, + uint32_t divider_integral, uint32_t divider_denominator, uint32_t divider_numerator) +{ + // Formula: rmt_sclk = module_clock_src / (1 + div_num + div_a / div_b) + (void)channel; // the source clock is set for all channels + HAL_ASSERT(divider_integral >= 1); + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.rmt_sclk_conf, rmt_sclk_div_num, divider_integral - 1); + PCR.rmt_sclk_conf.rmt_sclk_div_a = divider_numerator; + PCR.rmt_sclk_conf.rmt_sclk_div_b = divider_denominator; + switch (src) { + case RMT_CLK_SRC_APB: + PCR.rmt_sclk_conf.rmt_sclk_sel = 1; + break; + case RMT_CLK_SRC_XTAL: + PCR.rmt_sclk_conf.rmt_sclk_sel = 3; + break; + default: + HAL_ASSERT(false); + break; + } +} + +/** + * @brief Enable RMT peripheral source clock + * + * @param dev Peripheral instance address + * @param en True to enable, False to disable + */ +static inline void rmt_ll_enable_group_clock(rmt_dev_t *dev, bool en) +{ + (void)dev; + PCR.rmt_sclk_conf.rmt_sclk_en = en; +} + +////////////////////////////////////////TX Channel Specific///////////////////////////////////////////////////////////// + +/** + * @brief Reset clock divider for TX channels by mask + * + * @param dev Peripheral instance address + * @param channel_mask Mask of TX channels + */ +static inline void rmt_ll_tx_reset_channels_clock_div(rmt_dev_t *dev, uint32_t channel_mask) +{ + // write 1 to reset + dev->ref_cnt_rst.val |= channel_mask & 0x03; +} + +/** + * @brief Set TX channel clock divider + * + * @param dev Peripheral instance address + * @param channel RMT TX channel number + * @param div Division value + */ +static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) +{ + HAL_ASSERT(div >= 1 && div <= 256 && "divider out of range"); + // limit the maximum divider to 256 + if (div >= 256) { + div = 0; // 0 means 256 division + } + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chnconf0[channel], div_cnt_chn, div); +} + +/** + * @brief Reset RMT reading pointer for TX channel + * + * @param dev Peripheral instance address + * @param channel RMT TX channel number + */ +__attribute__((always_inline)) +static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel) +{ + dev->chnconf0[channel].mem_rd_rst_chn = 1; + dev->chnconf0[channel].mem_rd_rst_chn = 0; + dev->chnconf0[channel].apb_mem_rst_chn = 1; + dev->chnconf0[channel].apb_mem_rst_chn = 0; +} + +/** + * @brief Start transmitting for TX channel + * + * @param dev Peripheral instance address + * @param channel RMT TX channel number + */ +__attribute__((always_inline)) +static inline void rmt_ll_tx_start(rmt_dev_t *dev, uint32_t channel) +{ + // update other configuration registers before start transmitting + dev->chnconf0[channel].conf_update_chn = 1; + dev->chnconf0[channel].tx_start_chn = 1; +} + +/** + * @brief Stop transmitting for TX channel + * + * @param dev Peripheral instance address + * @param channel RMT TX channel number + */ +__attribute__((always_inline)) +static inline void rmt_ll_tx_stop(rmt_dev_t *dev, uint32_t channel) +{ + dev->chnconf0[channel].tx_stop_chn = 1; + // stop won't take place until configurations updated + dev->chnconf0[channel].conf_update_chn = 1; +} + +/** + * @brief Set memory block number for TX channel + * + * @param dev Peripheral instance address + * @param channel RMT TX channel number + * @param block_num memory block number + */ +static inline void rmt_ll_tx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num) +{ + dev->chnconf0[channel].mem_size_chn = block_num; +} + +/** + * @brief Enable TX wrap + * + * @param dev Peripheral instance address + * @param channel RMT TX channel number + * @param enable True to enable, False to disable + */ +static inline void rmt_ll_tx_enable_wrap(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + dev->chnconf0[channel].mem_tx_wrap_en_chn = enable; +} + +/** + * @brief Enable transmitting in a loop + * + * @param dev Peripheral instance address + * @param channel RMT TX channel number + * @param enable True to enable, False to disable + */ +__attribute__((always_inline)) +static inline void rmt_ll_tx_enable_loop(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + dev->chnconf0[channel].tx_conti_mode_chn = enable; +} + +/** + * @brief Set loop count for TX channel + * + * @param dev Peripheral instance address + * @param channel RMT TX channel number + * @param count TX loop count + */ +__attribute__((always_inline)) +static inline void rmt_ll_tx_set_loop_count(rmt_dev_t *dev, uint32_t channel, uint32_t count) +{ + HAL_ASSERT(count <= RMT_LL_MAX_LOOP_COUNT_PER_BATCH && "loop count out of range"); + dev->chn_tx_lim[channel].tx_loop_num_chn = count; +} + +/** + * @brief Reset loop count for TX channel + * + * @param dev Peripheral instance address + * @param channel RMT TX channel number + */ +__attribute__((always_inline)) +static inline void rmt_ll_tx_reset_loop_count(rmt_dev_t *dev, uint32_t channel) +{ + dev->chn_tx_lim[channel].loop_count_reset_chn = 1; + dev->chn_tx_lim[channel].loop_count_reset_chn = 0; +} + +/** + * @brief Enable loop count for TX channel + * + * @param dev Peripheral instance address + * @param channel RMT TX channel number + * @param enable True to enable, False to disable + */ +__attribute__((always_inline)) +static inline void rmt_ll_tx_enable_loop_count(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + dev->chn_tx_lim[channel].tx_loop_cnt_en_chn = enable; +} + +/** + * @brief Enable loop stop at count value automatically + * + * @param dev Peripheral instance address + * @param channel RMT TX channel number + * @param enable True to enable, False to disable + */ +__attribute__((always_inline)) +static inline void rmt_ll_tx_enable_loop_autostop(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + dev->chn_tx_lim[channel].loop_stop_en_chn = enable; +} + +/** + * @brief Enable transmit multiple channels synchronously + * + * @param dev Peripheral instance address + * @param enable True to enable, False to disable + */ +static inline void rmt_ll_tx_enable_sync(rmt_dev_t *dev, bool enable) +{ + dev->tx_sim.tx_sim_en = enable; +} + +/** + * @brief Clear the TX channels synchronous group + * + * @param dev Peripheral instance address + */ +static inline void rmt_ll_tx_clear_sync_group(rmt_dev_t *dev) +{ + dev->tx_sim.val &= ~(0x03); +} + +/** + * @brief Add TX channels to the synchronous group + * + * @param dev Peripheral instance address + * @param channel_mask Mask of TX channels to be added to the synchronous group + */ +static inline void rmt_ll_tx_sync_group_add_channels(rmt_dev_t *dev, uint32_t channel_mask) +{ + dev->tx_sim.val |= (channel_mask & 0x03); +} + +/** + * @brief Remove TX channels from the synchronous group + * + * @param dev Peripheral instance address + * @param channel_mask Mask of TX channels to be removed from the synchronous group + */ +static inline void rmt_ll_tx_sync_group_remove_channels(rmt_dev_t *dev, uint32_t channel_mask) +{ + dev->tx_sim.val &= ~channel_mask; +} + +/** + * @brief Fix the output level when TX channel is in IDLE state + * + * @param dev Peripheral instance address + * @param channel RMT TX channel number + * @param level IDLE level (1 => high, 0 => low) + * @param enable True to fix the IDLE level, otherwise the IDLE level is determined by EOF encoder + */ +__attribute__((always_inline)) +static inline void rmt_ll_tx_fix_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level, bool enable) +{ + dev->chnconf0[channel].idle_out_en_chn = enable; + dev->chnconf0[channel].idle_out_lv_chn = level; +} + +/** + * @brief Set the amount of RMT symbols that can trigger the limitation interrupt + * + * @param dev Peripheral instance address + * @param channel RMT TX channel number + * @param limit Specify the number of symbols + */ +static inline void rmt_ll_tx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit) +{ + dev->chn_tx_lim[channel].tx_lim_chn = limit; +} + +/** + * @brief Set high and low duration of carrier signal + * + * @param dev Peripheral instance address + * @param channel RMT TX channel number + * @param high_ticks Duration of high level + * @param low_ticks Duration of low level + */ +static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks) +{ + HAL_ASSERT(high_ticks >= 1 && high_ticks <= 65536 && low_ticks >= 1 && low_ticks <= 65536 && "out of range high/low ticks"); + // ticks=0 means 65536 in hardware + if (high_ticks >= 65536) { + high_ticks = 0; + } + if (low_ticks >= 65536) { + low_ticks = 0; + } + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chncarrier_duty[channel], carrier_high_chn, high_ticks); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chncarrier_duty[channel], carrier_low_chn, low_ticks); +} + +/** + * @brief Enable modulating carrier signal to TX channel + * + * @param dev Peripheral instance address + * @param channel RMT TX channel number + * @param enable True to enable, False to disable + */ +static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + dev->chnconf0[channel].carrier_en_chn = enable; +} + +/** + * @brief Set on high or low to modulate the carrier signal + * + * @param dev Peripheral instance address + * @param channel RMT TX channel number + * @param level Which level to modulate on (0=>low level, 1=>high level) + */ +static inline void rmt_ll_tx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) +{ + dev->chnconf0[channel].carrier_out_lv_chn = level; +} + +/** + * @brief Enable to always output carrier signal, regardless of a valid data transmission + * + * @param dev Peripheral instance address + * @param channel RMT TX channel number + * @param enable True to output carrier signal in all RMT state, False to only ouput carrier signal for effective data + */ +static inline void rmt_ll_tx_enable_carrier_always_on(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + dev->chnconf0[channel].carrier_eff_en_chn = !enable; +} + +////////////////////////////////////////RX Channel Specific///////////////////////////////////////////////////////////// + +/** + * @brief Reset clock divider for RX channels by mask + * + * @param dev Peripheral instance address + * @param channel_mask Mask of RX channels + */ +static inline void rmt_ll_rx_reset_channels_clock_div(rmt_dev_t *dev, uint32_t channel_mask) +{ + // write 1 to reset + dev->ref_cnt_rst.val |= ((channel_mask & 0x03) << 2); +} + +/** + * @brief Set RX channel clock divider + * + * @param dev Peripheral instance address + * @param channel RMT RX channel number + * @param div Division value + */ +static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) +{ + HAL_ASSERT(div >= 1 && div <= 256 && "divider out of range"); + // limit the maximum divider to 256 + if (div >= 256) { + div = 0; // 0 means 256 division + } + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chmconf[channel].conf0, div_cnt_chm, div); +} + +/** + * @brief Reset RMT writing pointer for RX channel + * + * @param dev Peripheral instance address + * @param channel RMT RX channel number + */ +static inline void rmt_ll_rx_reset_pointer(rmt_dev_t *dev, uint32_t channel) +{ + dev->chmconf[channel].conf1.mem_wr_rst_chm = 1; + dev->chmconf[channel].conf1.mem_wr_rst_chm = 0; + dev->chmconf[channel].conf1.apb_mem_rst_chm = 1; + dev->chmconf[channel].conf1.apb_mem_rst_chm = 0; +} + +/** + * @brief Enable receiving for RX channel + * + * @param dev Peripheral instance address + * @param channel RMT RX channel number + * @param enable True to enable, False to disable + */ +__attribute__((always_inline)) +static inline void rmt_ll_rx_enable(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + dev->chmconf[channel].conf1.rx_en_chm = enable; + // rx won't be enabled until configurations updated + dev->chmconf[channel].conf1.conf_update_chm = 1; +} + +/** + * @brief Set memory block number for RX channel + * + * @param dev Peripheral instance address + * @param channel RMT RX channel number + * @param block_num memory block number + */ +static inline void rmt_ll_rx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num) +{ + dev->chmconf[channel].conf0.mem_size_chm = block_num; +} + +/** + * @brief Set the time length for RX channel before going into IDLE state + * + * @param dev Peripheral instance address + * @param channel RMT RX channel number + * @param thres Time length threshold + */ +static inline void rmt_ll_rx_set_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres) +{ + dev->chmconf[channel].conf0.idle_thres_chm = thres; +} + +/** + * @brief Set RMT memory owner for RX channel + * + * @param dev Peripheral instance address + * @param channel RMT RX channel number + * @param owner Memory owner + */ +__attribute__((always_inline)) +static inline void rmt_ll_rx_set_mem_owner(rmt_dev_t *dev, uint32_t channel, rmt_ll_mem_owner_t owner) +{ + dev->chmconf[channel].conf1.mem_owner_chm = owner; +} + +/** + * @brief Enable filter for RX channel + * + * @param dev Peripheral instance address + * @param channel RMT RX chanenl number + * @param enable True to enable, False to disable + */ +static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + dev->chmconf[channel].conf1.rx_filter_en_chm = enable; +} + +/** + * @brief Set RX channel filter threshold (i.e. the maximum width of one pulse signal that would be treated as a noise) + * + * @param dev Peripheral instance address + * @param channel RMT RX channel number + * @param thres Filter threshold + */ +static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chmconf[channel].conf1, rx_filter_thres_chm, thres); +} + +/** + * @brief Get RMT memory write cursor offset + * + * @param dev Peripheral instance address + * @param channel RMT RX channel number + * @return writer offset + */ +__attribute__((always_inline)) +static inline uint32_t rmt_ll_rx_get_memory_writer_offset(rmt_dev_t *dev, uint32_t channel) +{ + return dev->chmstatus[channel].mem_waddr_ex_chm - (channel + 2) * 48; +} + +/** + * @brief Set the amount of RMT symbols that can trigger the limitation interrupt + * + * @param dev Peripheral instance address + * @param channel RMT RX channel number + * @param limit Specify the number of symbols + */ +static inline void rmt_ll_rx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit) +{ + dev->chm_rx_lim[channel].rmt_rx_lim_chm = limit; +} + +/** + * @brief Set high and low duration of carrier signal + * + * @param dev dev Peripheral instance address + * @param channel RMT TX channel number + * @param high_ticks Duration of high level + * @param low_ticks Duration of low level + */ +static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks) +{ + HAL_ASSERT(high_ticks >= 1 && high_ticks <= 65536 && low_ticks >= 1 && low_ticks <= 65536 && "out of range high/low ticks"); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chm_rx_carrier_rm[channel], carrier_high_thres_chm, high_ticks - 1); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chm_rx_carrier_rm[channel], carrier_low_thres_chm, low_ticks - 1); +} + +/** + * @brief Enable demodulating the carrier on RX channel + * + * @param dev Peripheral instance address + * @param channel RMT RX channel number + * @param enable True to enable, False to disable + */ +static inline void rmt_ll_rx_enable_carrier_demodulation(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + dev->chmconf[channel].conf0.carrier_en_chm = enable; +} + +/** + * @brief Set on high or low to demodulate the carrier signal + * + * @param dev Peripheral instance address + * @param channel RMT RX channel number + * @param level Which level to demodulate (0=>low level, 1=>high level) + */ +static inline void rmt_ll_rx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) +{ + dev->chmconf[channel].conf0.carrier_out_lv_chm = level; +} + +/** + * @brief Enable RX wrap + * + * @param dev Peripheral instance address + * @param channel RMT RX channel number + * @param enable True to enable, False to disable + */ +static inline void rmt_ll_rx_enable_wrap(rmt_dev_t *dev, uint32_t channel, bool enable) +{ + dev->chmconf[channel].conf1.mem_rx_wrap_en_chm = enable; +} + +//////////////////////////////////////////Interrupt Specific//////////////////////////////////////////////////////////// + +/** + * @brief Enable RMT interrupt for specific event mask + * + * @param dev Peripheral instance address + * @param mask Event mask + * @param enable True to enable, False to disable + */ +__attribute__((always_inline)) +static inline void rmt_ll_enable_interrupt(rmt_dev_t *dev, uint32_t mask, bool enable) +{ + if (enable) { + dev->int_ena.val |= mask; + } else { + dev->int_ena.val &= ~mask; + } +} + +/** + * @brief Clear RMT interrupt status by mask + * + * @param dev Peripheral instance address + * @param mask Interupt status mask + */ +__attribute__((always_inline)) +static inline void rmt_ll_clear_interrupt_status(rmt_dev_t *dev, uint32_t mask) +{ + dev->int_clr.val = mask; +} + +/** + * @brief Get interrupt status register address + * + * @param dev Peripheral instance address + * @return Register address + */ +static inline volatile void *rmt_ll_get_interrupt_status_reg(rmt_dev_t *dev) +{ + return &dev->int_st; +} + +/** + * @brief Get interrupt status for TX channel + * + * @param dev Peripheral instance address + * @param channel RMT TX channel number + * @return Interrupt status + */ +__attribute__((always_inline)) +static inline uint32_t rmt_ll_tx_get_interrupt_status(rmt_dev_t *dev, uint32_t channel) +{ + return dev->int_st.val & RMT_LL_EVENT_TX_MASK(channel); +} + +/** + * @brief Get interrupt raw status for TX channel + * + * @param dev Peripheral instance address + * @param channel RMT TX channel number + * @return Interrupt raw status + */ +static inline uint32_t rmt_ll_tx_get_interrupt_status_raw(rmt_dev_t *dev, uint32_t channel) +{ + return dev->int_raw.val & (RMT_LL_EVENT_TX_MASK(channel) | RMT_LL_EVENT_TX_ERROR(channel)); +} + +/** + * @brief Get interrupt raw status for RX channel + * + * @param dev Peripheral instance address + * @param channel RMT RX channel number + * @return Interrupt raw status + */ +static inline uint32_t rmt_ll_rx_get_interrupt_status_raw(rmt_dev_t *dev, uint32_t channel) +{ + return dev->int_raw.val & (RMT_LL_EVENT_RX_MASK(channel) | RMT_LL_EVENT_RX_ERROR(channel)); +} + +/** + * @brief Get interrupt status for RX channel + * + * @param dev Peripheral instance address + * @param channel RMT RX channel number + * @return Interrupt status + */ +__attribute__((always_inline)) +static inline uint32_t rmt_ll_rx_get_interrupt_status(rmt_dev_t *dev, uint32_t channel) +{ + return dev->int_st.val & RMT_LL_EVENT_RX_MASK(channel); +} + +//////////////////////////////////////////Deprecated Functions////////////////////////////////////////////////////////// +/////////////////////////////The following functions are only used by the legacy driver///////////////////////////////// +/////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +__attribute__((always_inline)) +static inline uint32_t rmt_ll_tx_get_status_word(rmt_dev_t *dev, uint32_t channel) +{ + return dev->chnstatus[channel].val; +} + +__attribute__((always_inline)) +static inline uint32_t rmt_ll_rx_get_status_word(rmt_dev_t *dev, uint32_t channel) +{ + return dev->chmstatus[channel].val; +} + +__attribute__((always_inline)) +static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) +{ + uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->chnconf0[channel], div_cnt_chn); + return div == 0 ? 256 : div; +} + +__attribute__((always_inline)) +static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) +{ + uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->chmconf[channel].conf0, div_cnt_chm); + return div == 0 ? 256 : div; +} + +__attribute__((always_inline)) +static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel) +{ + return dev->chmconf[channel].conf0.idle_thres_chm; +} + +__attribute__((always_inline)) +static inline uint32_t rmt_ll_tx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) +{ + return dev->chnconf0[channel].mem_size_chn; +} + +__attribute__((always_inline)) +static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) +{ + return dev->chmconf[channel].conf0.mem_size_chm; +} + +__attribute__((always_inline)) +static inline bool rmt_ll_tx_is_loop_enabled(rmt_dev_t *dev, uint32_t channel) +{ + return dev->chnconf0[channel].tx_conti_mode_chn; +} + +__attribute__((always_inline)) +static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel) +{ + rmt_clock_source_t clk_src = RMT_CLK_SRC_APB; + switch (PCR.rmt_sclk_conf.rmt_sclk_sel) { + case 1: + clk_src = RMT_CLK_SRC_APB; + break; + case 3: + clk_src = RMT_CLK_SRC_XTAL; + break; + } + return clk_src; +} + +__attribute__((always_inline)) +static inline bool rmt_ll_tx_is_idle_enabled(rmt_dev_t *dev, uint32_t channel) +{ + return dev->chnconf0[channel].idle_out_en_chn; +} + +__attribute__((always_inline)) +static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel) +{ + return dev->chnconf0[channel].idle_out_lv_chn; +} + +static inline bool rmt_ll_is_mem_powered_down(rmt_dev_t *dev) +{ + // the RTC domain can also power down RMT memory + // so it's probably not enough to detect whether it's powered down or not + // mem_force_pd has higher priority than mem_force_pu + return (dev->sys_conf.mem_force_pd) || !(dev->sys_conf.mem_force_pu); +} + +__attribute__((always_inline)) +static inline uint32_t rmt_ll_rx_get_mem_owner(rmt_dev_t *dev, uint32_t channel) +{ + return dev->chmconf[channel].conf1.mem_owner_chm; +} + +__attribute__((always_inline)) +static inline uint32_t rmt_ll_rx_get_limit(rmt_dev_t *dev, uint32_t channel) +{ + return dev->chm_rx_lim[channel].rmt_rx_lim_chm; +} + +__attribute__((always_inline)) +static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev) +{ + return dev->int_st.val & 0x03; +} + +__attribute__((always_inline)) +static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev) +{ + return (dev->int_st.val >> 2) & 0x03; +} + +__attribute__((always_inline)) +static inline uint32_t rmt_ll_get_tx_err_interrupt_status(rmt_dev_t *dev) +{ + return (dev->int_st.val >> 4) & 0x03; +} + +__attribute__((always_inline)) +static inline uint32_t rmt_ll_get_rx_err_interrupt_status(rmt_dev_t *dev) +{ + return (dev->int_st.val >> 6) & 0x03; +} + +__attribute__((always_inline)) +static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev) +{ + return (dev->int_st.val >> 8) & 0x03; +} + +__attribute__((always_inline)) +static inline uint32_t rmt_ll_get_rx_thres_interrupt_status(rmt_dev_t *dev) +{ + return (dev->int_st.val >> 10) & 0x03; +} + +__attribute__((always_inline)) +static inline uint32_t rmt_ll_get_tx_loop_interrupt_status(rmt_dev_t *dev) +{ + return (dev->int_st.val >> 12) & 0x03; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/rtc_cntl_ll.h b/components/hal/esp32c6/include/hal/rtc_cntl_ll.h new file mode 100644 index 0000000000..b5bff8bd10 --- /dev/null +++ b/components/hal/esp32c6/include/hal/rtc_cntl_ll.h @@ -0,0 +1,70 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc/soc.h" +#include "soc/rtc.h" +#include "soc/lp_aon_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) +{ + // TODO: IDF-5645 +} + +static inline uint32_t rtc_cntl_ll_gpio_get_wakeup_pins(void) +{ + // TODO: IDF-5645 + return 0; +} + +static inline void rtc_cntl_ll_gpio_set_wakeup_pins(void) +{ + // TODO: IDF-5645 +} + +static inline void rtc_cntl_ll_gpio_clear_wakeup_pins(void) +{ + // TODO: IDF-5645 +} + +static inline void rtc_cntl_ll_set_cpu_retention_link_addr(uint32_t addr) +{ + // TODO: IDF-5718 has removed the retention feature +} + +static inline void rtc_cntl_ll_enable_cpu_retention_clock(void) +{ + // TODO: IDF-5718 has removed the retention feature +} + +static inline void rtc_cntl_ll_enable_cpu_retention(void) +{ + // TODO: IDF-5718 has removed the retention feature +} + +static inline void rtc_cntl_ll_disable_cpu_retention(void) +{ + // TODO: IDF-5718 has removed the retention feature +} + +static inline void rtc_cntl_ll_reset_system(void) +{ + REG_SET_BIT(LP_AON_SYS_CFG_REG, LP_AON_HPSYS_SW_RESET); +} + +static inline void rtc_cntl_ll_reset_cpu(int cpu_no) +{ + REG_SET_BIT(LP_AON_CPUCORE0_CFG_REG, LP_AON_CPU_CORE0_SW_RESET); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/rwdt_ll.h b/components/hal/esp32c6/include/hal/rwdt_ll.h new file mode 100644 index 0000000000..ca930a8277 --- /dev/null +++ b/components/hal/esp32c6/include/hal/rwdt_ll.h @@ -0,0 +1,76 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +// The LL layer for RTC(LP) watchdog register operations. +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "hal/lpwdt_ll.h" + +#define rwdt_ll_enable(hw) \ + lpwdt_ll_enable(hw) + +#define rwdt_ll_disable(hw) \ + lpwdt_ll_disable(hw) + +#define rwdt_ll_check_if_enabled(hw) \ + lpwdt_ll_check_if_enabled(hw) + +#define rwdt_ll_config_stage(hw, stage, timeout_ticks, behavior) \ + lpwdt_ll_config_stage(hw, stage, timeout_ticks, behavior) + +#define rwdt_ll_disable_stage(hw, stage) \ + lpwdt_ll_disable_stage(hw, stage) + +#define rwdt_ll_set_cpu_reset_length(hw, length) \ + lpwdt_ll_set_cpu_reset_length(hw, length) + +#define rwdt_ll_set_sys_reset_length(hw, length) \ + lpwdt_ll_set_sys_reset_length(hw, length) + +#define rwdt_ll_set_flashboot_en(hw, enable) \ + lpwdt_ll_set_flashboot_en(hw, enable) + +#define rwdt_ll_set_procpu_reset_en(hw, enable) \ + lpwdt_ll_set_procpu_reset_en(hw, enable) + +#define rwdt_ll_set_appcpu_reset_en(hw, enable) \ + lpwdt_ll_set_appcpu_reset_en(hw, enable) + +#define rwdt_ll_set_pause_in_sleep_en(hw, enable) \ + lpwdt_ll_set_pause_in_sleep_en(hw, enable) + +#define rwdt_ll_set_chip_reset_en(hw, enable) \ + lpwdt_ll_set_chip_reset_en(hw, enable) + +#define rwdt_ll_set_chip_reset_width(hw, width) \ + lpwdt_ll_set_chip_reset_width(hw, width) + +#define rwdt_ll_feed(hw) \ + lpwdt_ll_feed(hw) + +#define rwdt_ll_write_protect_enable(hw) \ + lpwdt_ll_write_protect_enable(hw) + +#define rwdt_ll_write_protect_disable(hw) \ + lpwdt_ll_write_protect_disable(hw) + +#define rwdt_ll_set_intr_enable(hw, enable) \ + lpwdt_ll_set_intr_enable(hw, enable) + +#define rwdt_ll_check_intr_status(hw) \ + lpwdt_ll_check_intr_status(hw) + +#define rwdt_ll_clear_intr_status(hw) \ + lpwdt_ll_clear_intr_status(hw) + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/sdm_ll.h b/components/hal/esp32c6/include/hal/sdm_ll.h new file mode 100644 index 0000000000..fbf387e258 --- /dev/null +++ b/components/hal/esp32c6/include/hal/sdm_ll.h @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "hal/misc.h" +#include "hal/assert.h" +#include "soc/gpio_ext_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Set Sigma-delta enable + * + * @param hw Peripheral SIGMADELTA hardware instance address. + * @param en Sigma-delta enable value + */ +static inline void sdm_ll_enable_clock(gpio_sd_dev_t *hw, bool en) +{ + hw->misc.function_clk_en = en; +} + +/** + * @brief Set Sigma-delta channel duty. + * + * @param hw Peripheral SIGMADELTA hardware instance address. + * @param channel Sigma-delta channel number + * @param duty Sigma-delta duty of one channel, the value ranges from -128 to 127, recommended range is -90 ~ 90. + * The waveform is more like a random one in this range. + */ +__attribute__((always_inline)) +static inline void sdm_ll_set_duty(gpio_sd_dev_t *hw, int channel, int8_t duty) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)duty); +} + +/** + * @brief Set Sigma-delta channel's clock pre-scale value. + * + * @param hw Peripheral SIGMADELTA hardware instance address. + * @param channel Sigma-delta channel number + * @param prescale The divider of source clock, ranges from 1 to 256 + */ +static inline void sdm_ll_set_prescale(gpio_sd_dev_t *hw, int channel, uint32_t prescale) +{ + HAL_ASSERT(prescale && prescale <= 256); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale - 1); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/spi_flash_encrypted_ll.h b/components/hal/esp32c6/include/hal/spi_flash_encrypted_ll.h new file mode 100644 index 0000000000..eaa3ffb2f9 --- /dev/null +++ b/components/hal/esp32c6/include/hal/spi_flash_encrypted_ll.h @@ -0,0 +1,149 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The ll is not public api, don't use in application code. + * See readme.md in hal/include/hal/readme.md + ******************************************************************************/ + +// The Lowlevel layer for SPI Flash Encryption. + +#include +#include +#include "soc/hp_system_reg.h" +#include "soc/spi_mem_reg.h" +#include "soc/soc.h" +#include "hal/assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/// Choose type of chip you want to encrypt manully +typedef enum +{ + FLASH_ENCRYPTION_MANU = 0, ///!< Manually encrypt the flash chip. + PSRAM_ENCRYPTION_MANU = 1 ///!< Manually encrypt the psram chip. +} flash_encrypt_ll_type_t; + +/** + * Enable the flash encryption function under spi boot mode and download boot mode. + */ +static inline void spi_flash_encrypt_ll_enable(void) +{ + REG_SET_BIT(HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG, + HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT | + HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT); +} + +/* + * Disable the flash encryption mode. + */ +static inline void spi_flash_encrypt_ll_disable(void) +{ + REG_CLR_BIT(HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG, + HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT); +} + +/** + * Choose type of chip you want to encrypt manully + * + * @param type The type of chip to be encrypted + * + * @note The hardware currently support flash encryption. + */ +static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type) +{ + // Our hardware only support flash encryption + HAL_ASSERT(type == FLASH_ENCRYPTION_MANU); + REG_SET_FIELD(SPI_MEM_XTS_DESTINATION_REG(0), SPI_MEM_XTS_DESTINATION, type); +} + +/** + * Configure the data size of a single encryption. + * + * @param block_size Size of the desired block. + */ +static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size) +{ + // Desired block should not be larger than the block size. + REG_SET_FIELD(SPI_MEM_XTS_LINESIZE_REG(0), SPI_MEM_XTS_LINESIZE, size >> 5); +} + +/** + * Save 32-bit piece of plaintext. + * + * @param address the address of written flash partition. + * @param buffer Buffer to store the input data. + * @param size Buffer size. + * + */ +static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const uint32_t* buffer, uint32_t size) +{ + uint32_t plaintext_offs = (address % 64); + memcpy((void *)(SPI_MEM_XTS_PLAIN_BASE_REG(0) + plaintext_offs), buffer, size); +} + +/** + * Copy the flash address to XTS_AES physical address + * + * @param flash_addr flash address to write. + */ +static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr) +{ + REG_SET_FIELD(SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(0), SPI_MEM_XTS_PHYSICAL_ADDRESS, flash_addr); +} + +/** + * Start flash encryption + */ +static inline void spi_flash_encrypt_ll_calculate_start(void) +{ + REG_SET_FIELD(SPI_MEM_XTS_TRIGGER_REG(0), SPI_MEM_XTS_TRIGGER, 1); +} + +/** + * Wait for flash encryption termination + */ +static inline void spi_flash_encrypt_ll_calculate_wait_idle(void) +{ + while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_XTS_STATE) == 0x1) { + } +} + +/** + * Finish the flash encryption and make encrypted result accessible to SPI. + */ +static inline void spi_flash_encrypt_ll_done(void) +{ + REG_SET_BIT(SPI_MEM_XTS_RELEASE_REG(0), SPI_MEM_XTS_RELEASE); + while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_XTS_STATE) != 0x3) { + } +} + +/** + * Set to destroy encrypted result + */ +static inline void spi_flash_encrypt_ll_destroy(void) +{ + REG_SET_BIT(SPI_MEM_XTS_DESTROY_REG(0), SPI_MEM_XTS_DESTROY); +} + +/** + * Check if is qualified to encrypt the buffer + * + * @param address the address of written flash partition. + * @param length Buffer size. + */ +static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length) +{ + return ((address % length) == 0) ? true : false; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/spi_flash_ll.h b/components/hal/esp32c6/include/hal/spi_flash_ll.h new file mode 100644 index 0000000000..4e4a8c6dc5 --- /dev/null +++ b/components/hal/esp32c6/include/hal/spi_flash_ll.h @@ -0,0 +1,99 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The ll is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The Lowlevel layer for SPI Flash + +#pragma once + +#include "gpspi_flash_ll.h" +#include "spimem_flash_ll.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define spi_flash_ll_calculate_clock_reg(host_id, clock_div) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_calculate_clock_reg(clock_div) \ + : gpspi_flash_ll_calculate_clock_reg(clock_div)) + +#define spi_flash_ll_get_source_clock_freq_mhz(host_id) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_get_source_freq_mhz() : GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ) + +#define spi_flash_ll_get_hw(host_id) (((host_id)<=SPI1_HOST ? (spi_dev_t*) spimem_flash_ll_get_hw(host_id) \ + : gpspi_flash_ll_get_hw(host_id))) + +#define spi_flash_ll_hw_get_id(dev) ({int dev_id = spimem_flash_ll_hw_get_id(dev); \ + if (dev_id < 0) {\ + dev_id = gpspi_flash_ll_hw_get_id(dev);\ + }\ + dev_id; \ + }) + + +typedef union { + gpspi_flash_ll_clock_reg_t gpspi; + spimem_flash_ll_clock_reg_t spimem; +} spi_flash_ll_clock_reg_t; + +#ifdef GPSPI_BUILD +#define spi_flash_ll_reset(dev) gpspi_flash_ll_reset((spi_dev_t*)dev) +#define spi_flash_ll_cmd_is_done(dev) gpspi_flash_ll_cmd_is_done((spi_dev_t*)dev) +#define spi_flash_ll_get_buffer_data(dev, buffer, read_len) gpspi_flash_ll_get_buffer_data((spi_dev_t*)dev, buffer, read_len) +#define spi_flash_ll_set_buffer_data(dev, buffer, len) gpspi_flash_ll_set_buffer_data((spi_dev_t*)dev, buffer, len) +#define spi_flash_ll_user_start(dev) gpspi_flash_ll_user_start((spi_dev_t*)dev) +#define spi_flash_ll_host_idle(dev) gpspi_flash_ll_host_idle((spi_dev_t*)dev) +#define spi_flash_ll_read_phase(dev) gpspi_flash_ll_read_phase((spi_dev_t*)dev) +#define spi_flash_ll_set_cs_pin(dev, pin) gpspi_flash_ll_set_cs_pin((spi_dev_t*)dev, pin) +#define spi_flash_ll_set_read_mode(dev, read_mode) gpspi_flash_ll_set_read_mode((spi_dev_t*)dev, read_mode) +#define spi_flash_ll_set_clock(dev, clk) gpspi_flash_ll_set_clock((spi_dev_t*)dev, (gpspi_flash_ll_clock_reg_t*)clk) +#define spi_flash_ll_set_miso_bitlen(dev, bitlen) gpspi_flash_ll_set_miso_bitlen((spi_dev_t*)dev, bitlen) +#define spi_flash_ll_set_mosi_bitlen(dev, bitlen) gpspi_flash_ll_set_mosi_bitlen((spi_dev_t*)dev, bitlen) +#define spi_flash_ll_set_command(dev, cmd, bitlen) gpspi_flash_ll_set_command((spi_dev_t*)dev, cmd, bitlen) +#define spi_flash_ll_set_addr_bitlen(dev, bitlen) gpspi_flash_ll_set_addr_bitlen((spi_dev_t*)dev, bitlen) +#define spi_flash_ll_get_addr_bitlen(dev) gpspi_flash_ll_get_addr_bitlen((spi_dev_t*)dev) +#define spi_flash_ll_set_address(dev, addr) gpspi_flash_ll_set_address((spi_dev_t*)dev, addr) +#define spi_flash_ll_set_usr_address(dev, addr, bitlen) gpspi_flash_ll_set_usr_address((spi_dev_t*)dev, addr, bitlen) +#define spi_flash_ll_set_dummy(dev, dummy) gpspi_flash_ll_set_dummy((spi_dev_t*)dev, dummy) +#define spi_flash_ll_set_dummy_out(dev, en, lev) gpspi_flash_ll_set_dummy_out((spi_dev_t*)dev, en, lev) +#define spi_flash_ll_set_hold(dev, hold_n) gpspi_flash_ll_set_hold((spi_dev_t*)dev, hold_n) +#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) gpspi_flash_ll_set_cs_setup((spi_dev_t*)dev, cs_setup_time) +#else +#define spi_flash_ll_reset(dev) spimem_flash_ll_reset((spi_mem_dev_t*)dev) +#define spi_flash_ll_cmd_is_done(dev) spimem_flash_ll_cmd_is_done((spi_mem_dev_t*)dev) +#define spi_flash_ll_erase_chip(dev) spimem_flash_ll_erase_chip((spi_mem_dev_t*)dev) +#define spi_flash_ll_erase_sector(dev) spimem_flash_ll_erase_sector((spi_mem_dev_t*)dev) +#define spi_flash_ll_erase_block(dev) spimem_flash_ll_erase_block((spi_mem_dev_t*)dev) +#define spi_flash_ll_set_write_protect(dev, wp) spimem_flash_ll_set_write_protect((spi_mem_dev_t*)dev, wp) +#define spi_flash_ll_get_buffer_data(dev, buffer, read_len) spimem_flash_ll_get_buffer_data((spi_mem_dev_t*)dev, buffer, read_len) +#define spi_flash_ll_set_buffer_data(dev, buffer, len) spimem_flash_ll_set_buffer_data((spi_mem_dev_t*)dev, buffer, len) +#define spi_flash_ll_program_page(dev, buffer, len) spimem_flash_ll_program_page((spi_mem_dev_t*)dev, buffer, len) +#define spi_flash_ll_user_start(dev) spimem_flash_ll_user_start((spi_mem_dev_t*)dev) +#define spi_flash_ll_host_idle(dev) spimem_flash_ll_host_idle((spi_mem_dev_t*)dev) +#define spi_flash_ll_read_phase(dev) spimem_flash_ll_read_phase((spi_mem_dev_t*)dev) +#define spi_flash_ll_set_cs_pin(dev, pin) spimem_flash_ll_set_cs_pin((spi_mem_dev_t*)dev, pin) +#define spi_flash_ll_set_read_mode(dev, read_mode) spimem_flash_ll_set_read_mode((spi_mem_dev_t*)dev, read_mode) +#define spi_flash_ll_set_clock(dev, clk) spimem_flash_ll_set_clock((spi_mem_dev_t*)dev, (spimem_flash_ll_clock_reg_t*)clk) +#define spi_flash_ll_set_miso_bitlen(dev, bitlen) spimem_flash_ll_set_miso_bitlen((spi_mem_dev_t*)dev, bitlen) +#define spi_flash_ll_set_mosi_bitlen(dev, bitlen) spimem_flash_ll_set_mosi_bitlen((spi_mem_dev_t*)dev, bitlen) +#define spi_flash_ll_set_command(dev, cmd, bitlen) spimem_flash_ll_set_command((spi_mem_dev_t*)dev, cmd, bitlen) +#define spi_flash_ll_set_addr_bitlen(dev, bitlen) spimem_flash_ll_set_addr_bitlen((spi_mem_dev_t*)dev, bitlen) +#define spi_flash_ll_get_addr_bitlen(dev) spimem_flash_ll_get_addr_bitlen((spi_mem_dev_t*) dev) +#define spi_flash_ll_set_address(dev, addr) spimem_flash_ll_set_address((spi_mem_dev_t*)dev, addr) +#define spi_flash_ll_set_usr_address(dev, addr, bitlen) spimem_flash_ll_set_usr_address((spi_mem_dev_t*)dev, addr, bitlen) +#define spi_flash_ll_set_dummy(dev, dummy) spimem_flash_ll_set_dummy((spi_mem_dev_t*)dev, dummy) +#define spi_flash_ll_set_dummy_out(dev, en, lev) spimem_flash_ll_set_dummy_out((spi_mem_dev_t*)dev, en, lev) +#define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n) +#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time) + +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/spi_ll.h b/components/hal/esp32c6/include/hal/spi_ll.h new file mode 100644 index 0000000000..5f427ad6d5 --- /dev/null +++ b/components/hal/esp32c6/include/hal/spi_ll.h @@ -0,0 +1,1183 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The LL layer for SPI register operations + +#pragma once + +#include //for abs() +#include +#include "esp_attr.h" +#include "esp_types.h" +#include "soc/spi_periph.h" +#include "soc/spi_struct.h" +#include "soc/lldesc.h" +#include "hal/assert.h" +#include "hal/misc.h" +#include "hal/spi_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/// Interrupt not used. Don't use in app. +#define SPI_LL_UNUSED_INT_MASK (SPI_TRANS_DONE_INT_ENA | SPI_SLV_WR_DMA_DONE_INT_ENA | SPI_SLV_RD_DMA_DONE_INT_ENA | SPI_SLV_WR_BUF_DONE_INT_ENA | SPI_SLV_RD_BUF_DONE_INT_ENA) +/// These 2 masks together will set SPI transaction to one line mode +#define SPI_LL_ONE_LINE_CTRL_MASK (SPI_FREAD_QUAD | SPI_FREAD_DUAL | SPI_FCMD_QUAD | SPI_FCMD_DUAL | SPI_FADDR_QUAD | SPI_FADDR_DUAL) +#define SPI_LL_ONE_LINE_USER_MASK (SPI_FWRITE_QUAD | SPI_FWRITE_DUAL) +/// Swap the bit order to its correct place to send +#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len)) +/// This is the expected clock frequency +#define SPI_LL_PERIPH_CLK_FREQ (80 * 1000000) +#define SPI_LL_GET_HW(ID) ((ID)==0? ({abort();NULL;}):&GPSPI2) + +#define SPI_LL_DATA_MAX_BIT_LEN (1 << 18) + +/** + * The data structure holding calculated clock configuration. Since the + * calculation needs long time, it should be calculated during initialization and + * stored somewhere to be quickly used. + */ +typedef uint32_t spi_ll_clock_val_t; +typedef spi_dev_t spi_dma_dev_t; + +// Type definition of all supported interrupts +typedef enum { + SPI_LL_INTR_TRANS_DONE = BIT(0), ///< A transaction has done + SPI_LL_INTR_RDBUF = BIT(6), ///< Has received RDBUF command. Only available in slave HD. + SPI_LL_INTR_WRBUF = BIT(7), ///< Has received WRBUF command. Only available in slave HD. + SPI_LL_INTR_RDDMA = BIT(8), ///< Has received RDDMA command. Only available in slave HD. + SPI_LL_INTR_WRDMA = BIT(9), ///< Has received WRDMA command. Only available in slave HD. + SPI_LL_INTR_CMD7 = BIT(10), ///< Has received CMD7 command. Only available in slave HD. + SPI_LL_INTR_CMD8 = BIT(11), ///< Has received CMD8 command. Only available in slave HD. + SPI_LL_INTR_CMD9 = BIT(12), ///< Has received CMD9 command. Only available in slave HD. + SPI_LL_INTR_CMDA = BIT(13), ///< Has received CMDA command. Only available in slave HD. + SPI_LL_INTR_SEG_DONE = BIT(14), +} spi_ll_intr_t; +FLAG_ATTR(spi_ll_intr_t) + +// Flags for conditions under which the transaction length should be recorded +typedef enum { + SPI_LL_TRANS_LEN_COND_WRBUF = BIT(0), ///< WRBUF length will be recorded + SPI_LL_TRANS_LEN_COND_RDBUF = BIT(1), ///< RDBUF length will be recorded + SPI_LL_TRANS_LEN_COND_WRDMA = BIT(2), ///< WRDMA length will be recorded + SPI_LL_TRANS_LEN_COND_RDDMA = BIT(3), ///< RDDMA length will be recorded +} spi_ll_trans_len_cond_t; +FLAG_ATTR(spi_ll_trans_len_cond_t) + +// SPI base command +typedef enum { + /* Slave HD Only */ + SPI_LL_BASE_CMD_HD_WRBUF = 0x01, + SPI_LL_BASE_CMD_HD_RDBUF = 0x02, + SPI_LL_BASE_CMD_HD_WRDMA = 0x03, + SPI_LL_BASE_CMD_HD_RDDMA = 0x04, + SPI_LL_BASE_CMD_HD_SEG_END = 0x05, + SPI_LL_BASE_CMD_HD_EN_QPI = 0x06, + SPI_LL_BASE_CMD_HD_WR_END = 0x07, + SPI_LL_BASE_CMD_HD_INT0 = 0x08, + SPI_LL_BASE_CMD_HD_INT1 = 0x09, + SPI_LL_BASE_CMD_HD_INT2 = 0x0A, +} spi_ll_base_command_t; + +/*------------------------------------------------------------------------------ + * Control + *----------------------------------------------------------------------------*/ +/** + * Initialize SPI peripheral (master). + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_master_init(spi_dev_t *hw) +{ + //Reset timing + hw->user1.cs_setup_time = 0; + hw->user1.cs_hold_time = 0; + + //use all 64 bytes of the buffer + hw->user.usr_miso_highpart = 0; + hw->user.usr_mosi_highpart = 0; + + //Disable unneeded ints + hw->slave.val = 0; + hw->user.val = 0; + + hw->clk_gate.clk_en = 1; + hw->clk_gate.mst_clk_active = 1; + hw->clk_gate.mst_clk_sel = 1; + + hw->dma_conf.val = 0; + hw->dma_conf.slv_tx_seg_trans_clr_en = 1; + hw->dma_conf.slv_rx_seg_trans_clr_en = 1; + hw->dma_conf.dma_slv_seg_trans_en = 0; +} + +/** + * Initialize SPI peripheral (slave). + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_slave_init(spi_dev_t *hw) +{ + //Configure slave + hw->clock.val = 0; + hw->user.val = 0; + hw->ctrl.val = 0; + hw->user.doutdin = 1; //we only support full duplex + hw->user.sio = 0; + hw->slave.slave_mode = 1; + hw->slave.soft_reset = 1; + hw->slave.soft_reset = 0; + //use all 64 bytes of the buffer + hw->user.usr_miso_highpart = 0; + hw->user.usr_mosi_highpart = 0; + + // Configure DMA In-Link to not be terminated when transaction bit counter exceeds + hw->dma_conf.rx_eof_en = 0; + hw->dma_conf.dma_slv_seg_trans_en = 0; + + //Disable unneeded ints + hw->dma_int_ena.val &= ~SPI_LL_UNUSED_INT_MASK; +} + +/** + * Initialize SPI peripheral (slave half duplex mode) + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_slave_hd_init(spi_dev_t *hw) +{ + hw->clock.val = 0; + hw->user.val = 0; + hw->ctrl.val = 0; + hw->user.doutdin = 0; + hw->user.sio = 0; + + hw->slave.soft_reset = 1; + hw->slave.soft_reset = 0; + hw->slave.slave_mode = 1; +} + +/** + * Check whether user-defined transaction is done. + * + * @param hw Beginning address of the peripheral registers. + * + * @return True if transaction is done, otherwise false. + */ +static inline bool spi_ll_usr_is_done(spi_dev_t *hw) +{ + return hw->dma_int_raw.trans_done; +} + +/** + * Trigger start of user-defined transaction for master. + * The synchronization between two clock domains is required in ESP32-S3 + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_master_user_start(spi_dev_t *hw) +{ + hw->cmd.update = 1; + while (hw->cmd.update); + hw->cmd.usr = 1; +} + +/** + * Trigger start of user-defined transaction for slave. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_slave_user_start(spi_dev_t *hw) +{ + hw->cmd.usr = 1; +} + +/** + * Get current running command bit-mask. (Preview) + * + * @param hw Beginning address of the peripheral registers. + * + * @return Bitmask of running command, see ``SPI_CMD_REG``. 0 if no in-flight command. + */ +static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw) +{ + return hw->cmd.val; +} + +/** + * Reset the slave peripheral before next transaction. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_slave_reset(spi_dev_t *hw) +{ + hw->slave.soft_reset = 1; + hw->slave.soft_reset = 0; +} + +/** + * Reset SPI CPU TX FIFO + * + * On ESP32C3, this function is not seperated + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_cpu_tx_fifo_reset(spi_dev_t *hw) +{ + hw->dma_conf.buf_afifo_rst = 1; + hw->dma_conf.buf_afifo_rst = 0; +} + +/** + * Reset SPI CPU RX FIFO + * + * On ESP32C3, this function is not seperated + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_cpu_rx_fifo_reset(spi_dev_t *hw) +{ + hw->dma_conf.rx_afifo_rst = 1; + hw->dma_conf.rx_afifo_rst = 0; +} + +/** + * Reset SPI DMA TX FIFO + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_dma_tx_fifo_reset(spi_dev_t *hw) +{ + hw->dma_conf.dma_afifo_rst = 1; + hw->dma_conf.dma_afifo_rst = 0; +} + +/** + * Reset SPI DMA RX FIFO + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_dma_rx_fifo_reset(spi_dev_t *hw) +{ + hw->dma_conf.rx_afifo_rst = 1; + hw->dma_conf.rx_afifo_rst = 0; +} + +/** + * Clear in fifo full error + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_infifo_full_clr(spi_dev_t *hw) +{ + hw->dma_int_clr.dma_infifo_full_err = 1; +} + +/** + * Clear out fifo empty error + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_outfifo_empty_clr(spi_dev_t *hw) +{ + hw->dma_int_clr.dma_outfifo_empty_err = 1; +} + +/*------------------------------------------------------------------------------ + * DMA + *----------------------------------------------------------------------------*/ +/** + * Enable/Disable RX DMA (Peripherals->DMA->RAM) + * + * @param hw Beginning address of the peripheral registers. + * @param enable 1: enable; 2: disable + */ +static inline void spi_ll_dma_rx_enable(spi_dev_t *hw, bool enable) +{ + hw->dma_conf.dma_rx_ena = enable; +} + +/** + * Enable/Disable TX DMA (RAM->DMA->Peripherals) + * + * @param hw Beginning address of the peripheral registers. + * @param enable 1: enable; 2: disable + */ +static inline void spi_ll_dma_tx_enable(spi_dev_t *hw, bool enable) +{ + hw->dma_conf.dma_tx_ena = enable; +} + +/** + * Configuration of RX DMA EOF interrupt generation way + * + * @param hw Beginning address of the peripheral registers. + * @param enable 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. + */ +static inline void spi_ll_dma_set_rx_eof_generation(spi_dev_t *hw, bool enable) +{ + hw->dma_conf.rx_eof_en = enable; +} + +/*------------------------------------------------------------------------------ + * Buffer + *----------------------------------------------------------------------------*/ +/** + * Write to SPI hardware data buffer. + * + * @param hw Beginning address of the peripheral registers. + * @param buffer_to_send Address of the data to be written to the hardware data buffer. + * @param bitlen Length to write, in bits. + */ +static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_send, size_t bitlen) +{ + for (int x = 0; x < bitlen; x += 32) { + //Use memcpy to get around alignment issues for txdata + uint32_t word; + memcpy(&word, &buffer_to_send[x / 8], 4); + hw->data_buf[(x / 32)].buf = word; + } +} + +/** + * Write to SPI hardware data buffer by buffer ID (address) + * + * @param hw Beginning address of the peripheral registers + * @param byte_id Start ID (address) of the hardware buffer to be written + * @param data Address of the data to be written to the hardware data buffer. + * @param len Length to write, in bytes. + */ +static inline void spi_ll_write_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *data, int len) +{ + HAL_ASSERT(byte_id + len <= 64); + HAL_ASSERT(len > 0); + HAL_ASSERT(byte_id >= 0); + + while (len > 0) { + uint32_t word; + int offset = byte_id % 4; + int copy_len = 4 - offset; + if (copy_len > len) { + copy_len = len; + } + + //read-modify-write + if (copy_len != 4) { + word = hw->data_buf[byte_id / 4].buf; //read + } + memcpy(((uint8_t *)&word) + offset, data, copy_len); //modify + hw->data_buf[byte_id / 4].buf = word; //write + + data += copy_len; + byte_id += copy_len; + len -= copy_len; + } +} + +/** + * Read from SPI hardware data buffer. + * + * @param hw Beginning address of the peripheral registers. + * @param buffer_to_rcv Address of a buffer to read data from hardware data buffer + * @param bitlen Length to read, in bits. + */ +static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, size_t bitlen) +{ + for (int x = 0; x < bitlen; x += 32) { + //Do a memcpy to get around possible alignment issues in rx_buffer + uint32_t word = hw->data_buf[x / 32].buf; + int len = bitlen - x; + if (len > 32) { + len = 32; + } + memcpy(&buffer_to_rcv[x / 8], &word, (len + 7) / 8); + } +} + +/** + * Read from SPI hardware data buffer by buffer ID (address) + * + * @param hw Beginning address of the peripheral registers + * @param byte_id Start ID (address) of the hardware buffer to be read + * @param data Address of a buffer to read data from hardware data buffer + * @param len Length to read, in bytes. + */ +static inline void spi_ll_read_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *out_data, int len) +{ + while (len > 0) { + uint32_t word = hw->data_buf[byte_id / 4].buf; + int offset = byte_id % 4; + int copy_len = 4 - offset; + if (copy_len > len) { + copy_len = len; + } + + memcpy(out_data, ((uint8_t *)&word) + offset, copy_len); + byte_id += copy_len; + out_data += copy_len; + len -= copy_len; + } +} + +/*------------------------------------------------------------------------------ + * Configs: mode + *----------------------------------------------------------------------------*/ +/** + * Enable/disable the postive-cs feature. + * + * @param hw Beginning address of the peripheral registers. + * @param cs One of the CS (0-2) to enable/disable the feature. + * @param pos_cs True to enable the feature, otherwise disable (default). + */ +static inline void spi_ll_master_set_pos_cs(spi_dev_t *hw, int cs, uint32_t pos_cs) +{ + if (pos_cs) { + hw->misc.master_cs_pol |= (1 << cs); + } else { + hw->misc.master_cs_pol &= ~(1 << cs); + } +} + +/** + * Enable/disable the LSBFIRST feature for TX data. + * + * @param hw Beginning address of the peripheral registers. + * @param lsbfirst True if LSB of TX data to be sent first, otherwise MSB is sent first (default). + */ +static inline void spi_ll_set_tx_lsbfirst(spi_dev_t *hw, bool lsbfirst) +{ + hw->ctrl.wr_bit_order = lsbfirst; +} + +/** + * Enable/disable the LSBFIRST feature for RX data. + * + * @param hw Beginning address of the peripheral registers. + * @param lsbfirst True if first bit received as LSB, otherwise as MSB (default). + */ +static inline void spi_ll_set_rx_lsbfirst(spi_dev_t *hw, bool lsbfirst) +{ + hw->ctrl.rd_bit_order = lsbfirst; +} + +/** + * Set SPI mode for the peripheral as master. + * + * @param hw Beginning address of the peripheral registers. + * @param mode SPI mode to work at, 0-3. + */ +static inline void spi_ll_master_set_mode(spi_dev_t *hw, uint8_t mode) +{ + //Configure polarity + if (mode == 0) { + hw->misc.ck_idle_edge = 0; + hw->user.ck_out_edge = 0; + } else if (mode == 1) { + hw->misc.ck_idle_edge = 0; + hw->user.ck_out_edge = 1; + } else if (mode == 2) { + hw->misc.ck_idle_edge = 1; + hw->user.ck_out_edge = 1; + } else if (mode == 3) { + hw->misc.ck_idle_edge = 1; + hw->user.ck_out_edge = 0; + } +} + +/** + * Set SPI mode for the peripheral as slave. + * + * @param hw Beginning address of the peripheral registers. + * @param mode SPI mode to work at, 0-3. + */ +static inline void spi_ll_slave_set_mode(spi_dev_t *hw, const int mode, bool dma_used) +{ + if (mode == 0) { + hw->misc.ck_idle_edge = 0; + hw->user.rsck_i_edge = 0; + hw->user.tsck_i_edge = 0; + hw->slave.clk_mode_13 = 0; + } else if (mode == 1) { + hw->misc.ck_idle_edge = 0; + hw->user.rsck_i_edge = 1; + hw->user.tsck_i_edge = 1; + hw->slave.clk_mode_13 = 1; + } else if (mode == 2) { + hw->misc.ck_idle_edge = 1; + hw->user.rsck_i_edge = 1; + hw->user.tsck_i_edge = 1; + hw->slave.clk_mode_13 = 0; + } else if (mode == 3) { + hw->misc.ck_idle_edge = 1; + hw->user.rsck_i_edge = 0; + hw->user.tsck_i_edge = 0; + hw->slave.clk_mode_13 = 1; + } + hw->slave.rsck_data_out = 0; +} + +/** + * Set SPI to work in full duplex or half duplex mode. + * + * @param hw Beginning address of the peripheral registers. + * @param half_duplex True to work in half duplex mode, otherwise in full duplex mode. + */ +static inline void spi_ll_set_half_duplex(spi_dev_t *hw, bool half_duplex) +{ + hw->user.doutdin = !half_duplex; +} + +/** + * Set SPI to work in SIO mode or not. + * + * SIO is a mode which MOSI and MISO share a line. The device MUST work in half-duplexmode. + * + * @param hw Beginning address of the peripheral registers. + * @param sio_mode True to work in SIO mode, otherwise false. + */ +static inline void spi_ll_set_sio_mode(spi_dev_t *hw, int sio_mode) +{ + hw->user.sio = sio_mode; +} + +/** + * Configure the SPI transaction line mode for the master to use. + * + * @param hw Beginning address of the peripheral registers. + * @param line_mode SPI transaction line mode to use, see ``spi_line_mode_t``. + */ +static inline void spi_ll_master_set_line_mode(spi_dev_t *hw, spi_line_mode_t line_mode) +{ + hw->ctrl.val &= ~SPI_LL_ONE_LINE_CTRL_MASK; + hw->user.val &= ~SPI_LL_ONE_LINE_USER_MASK; + hw->ctrl.fcmd_dual = (line_mode.cmd_lines == 2); + hw->ctrl.fcmd_quad = (line_mode.cmd_lines == 4); + hw->ctrl.faddr_dual = (line_mode.addr_lines == 2); + hw->ctrl.faddr_quad = (line_mode.addr_lines == 4); + hw->ctrl.fread_dual = (line_mode.data_lines == 2); + hw->user.fwrite_dual = (line_mode.data_lines == 2); + hw->ctrl.fread_quad = (line_mode.data_lines == 4); + hw->user.fwrite_quad = (line_mode.data_lines == 4); +} + +/** + * Set the SPI slave to work in segment transaction mode + * + * @param hw Beginning address of the peripheral registers. + * @param seg_trans True to work in seg mode, otherwise false. + */ +static inline void spi_ll_slave_set_seg_mode(spi_dev_t *hw, bool seg_trans) +{ + hw->dma_conf.dma_slv_seg_trans_en = seg_trans; +} + +/** + * Select one of the CS to use in current transaction. + * + * @param hw Beginning address of the peripheral registers. + * @param cs_id The cs to use, 0-2, otherwise none of them is used. + */ +static inline void spi_ll_master_select_cs(spi_dev_t *hw, int cs_id) +{ + hw->misc.cs0_dis = (cs_id == 0) ? 0 : 1; + hw->misc.cs1_dis = (cs_id == 1) ? 0 : 1; + hw->misc.cs2_dis = (cs_id == 2) ? 0 : 1; + hw->misc.cs3_dis = (cs_id == 3) ? 0 : 1; + hw->misc.cs4_dis = (cs_id == 4) ? 0 : 1; + hw->misc.cs5_dis = (cs_id == 5) ? 0 : 1; +} + +/** + * Keep Chip Select activated after the current transaction. + * + * @param hw Beginning address of the peripheral registers. + * @param keep_active if 0 don't keep CS activated, else keep CS activated + */ +static inline void spi_ll_master_keep_cs(spi_dev_t *hw, int keep_active) +{ + hw->misc.cs_keep_active = (keep_active != 0) ? 1 : 0; +} + +/*------------------------------------------------------------------------------ + * Configs: parameters + *----------------------------------------------------------------------------*/ +/** + * Set the clock for master by stored value. + * + * @param hw Beginning address of the peripheral registers. + * @param val Stored clock configuration calculated before (by ``spi_ll_cal_clock``). + */ +static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, const spi_ll_clock_val_t *val) +{ + hw->clock.val = *(uint32_t *)val; +} + +/** + * Get the frequency of given dividers. Don't use in app. + * + * @param fapb APB clock of the system. + * @param pre Pre devider. + * @param n Main divider. + * + * @return Frequency of given dividers. + */ +static inline int spi_ll_freq_for_pre_n(int fapb, int pre, int n) +{ + return (fapb / (pre * n)); +} + +/** + * Calculate the nearest frequency avaliable for master. + * + * @param fapb APB clock of the system. + * @param hz Frequncy desired. + * @param duty_cycle Duty cycle desired. + * @param out_reg Output address to store the calculated clock configurations for the return frequency. + * + * @return Actual (nearest) frequency. + */ +static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ll_clock_val_t *out_reg) +{ + typeof(GPSPI2.clock) reg; + int eff_clk; + + //In hw, n, h and l are 1-64, pre is 1-8K. Value written to register is one lower than used value. + if (hz > ((fapb / 4) * 3)) { + //Using Fapb directly will give us the best result here. + reg.clkcnt_l = 0; + reg.clkcnt_h = 0; + reg.clkcnt_n = 0; + reg.clkdiv_pre = 0; + reg.clk_equ_sysclk = 1; + eff_clk = fapb; + } else { + //For best duty cycle resolution, we want n to be as close to 32 as possible, but + //we also need a pre/n combo that gets us as close as possible to the intended freq. + //To do this, we bruteforce n and calculate the best pre to go along with that. + //If there's a choice between pre/n combos that give the same result, use the one + //with the higher n. + int pre, n, h, l; + int bestn = -1; + int bestpre = -1; + int besterr = 0; + int errval; + for (n = 2; n <= 64; n++) { //Start at 2: we need to be able to set h/l so we have at least one high and one low pulse. + //Effectively, this does pre=round((fapb/n)/hz). + pre = ((fapb / n) + (hz / 2)) / hz; + if (pre <= 0) { + pre = 1; + } + if (pre > 16) { + pre = 16; + } + errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz); + if (bestn == -1 || errval <= besterr) { + besterr = errval; + bestn = n; + bestpre = pre; + } + } + + n = bestn; + pre = bestpre; + l = n; + //This effectively does round((duty_cycle*n)/256) + h = (duty_cycle * n + 127) / 256; + if (h <= 0) { + h = 1; + } + + reg.clk_equ_sysclk = 0; + reg.clkcnt_n = n - 1; + reg.clkdiv_pre = pre - 1; + reg.clkcnt_h = h - 1; + reg.clkcnt_l = l - 1; + eff_clk = spi_ll_freq_for_pre_n(fapb, pre, n); + } + if (out_reg != NULL) { + *(uint32_t *)out_reg = reg.val; + } + return eff_clk; +} + +/** + * Calculate and set clock for SPI master according to desired parameters. + * + * This takes long, suggest to calculate the configuration during + * initialization by ``spi_ll_master_cal_clock`` and store the result, then + * configure the clock by stored value when used by + * ``spi_ll_msater_set_clock_by_reg``. + * + * @param hw Beginning address of the peripheral registers. + * @param fapb APB clock of the system. + * @param hz Frequncy desired. + * @param duty_cycle Duty cycle desired. + * + * @return Actual frequency that is used. + */ +static inline int spi_ll_master_set_clock(spi_dev_t *hw, int fapb, int hz, int duty_cycle) +{ + spi_ll_clock_val_t reg_val; + int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, ®_val); + spi_ll_master_set_clock_by_reg(hw, ®_val); + return freq; +} + +/** + * Set the mosi delay after the output edge to the signal. (Preview) + * + * The delay mode/num is a Espressif conception, may change in the new chips. + * + * @param hw Beginning address of the peripheral registers. + * @param delay_mode Delay mode, see TRM. + * @param delay_num APB clocks to delay. + */ +static inline void spi_ll_set_mosi_delay(spi_dev_t *hw, int delay_mode, int delay_num) +{ +} + +/** + * Set the miso delay applied to the input signal before the internal peripheral. (Preview) + * + * The delay mode/num is a Espressif conception, may change in the new chips. + * + * @param hw Beginning address of the peripheral registers. + * @param delay_mode Delay mode, see TRM. + * @param delay_num APB clocks to delay. + */ +static inline void spi_ll_set_miso_delay(spi_dev_t *hw, int delay_mode, int delay_num) +{ +} + +/** + * Set the delay of SPI clocks before the CS inactive edge after the last SPI clock. + * + * @param hw Beginning address of the peripheral registers. + * @param hold Delay of SPI clocks after the last clock, 0 to disable the hold phase. + */ +static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) +{ + hw->user1.cs_hold_time = hold; + hw->user.cs_hold = hold ? 1 : 0; +} + +/** + * Set the delay of SPI clocks before the first SPI clock after the CS active edge. + * + * Note ESP32 doesn't support to use this feature when command/address phases + * are used in full duplex mode. + * + * @param hw Beginning address of the peripheral registers. + * @param setup Delay of SPI clocks after the CS active edge, 0 to disable the setup phase. + */ +static inline void spi_ll_master_set_cs_setup(spi_dev_t *hw, uint8_t setup) +{ + hw->user1.cs_setup_time = setup - 1; + hw->user.cs_setup = setup ? 1 : 0; +} + +/*------------------------------------------------------------------------------ + * Configs: data + *----------------------------------------------------------------------------*/ +/** + * Set the output length (master). + * This should be called before master setting MISO(input) length + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen output length, in bits. + */ +static inline void spi_ll_set_mosi_bitlen(spi_dev_t *hw, size_t bitlen) +{ + if (bitlen > 0) { + hw->ms_dlen.ms_data_bitlen = bitlen - 1; + } +} + +/** + * Set the input length (master). + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen input length, in bits. + */ +static inline void spi_ll_set_miso_bitlen(spi_dev_t *hw, size_t bitlen) +{ + if (bitlen > 0) { + hw->ms_dlen.ms_data_bitlen = bitlen - 1; + } +} + +/** + * Set the maximum input length (slave). + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen Input length, in bits. + */ +static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen) +{ + //This is not used in esp32c3 +} + +/** + * Set the maximum output length (slave). + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen Output length, in bits. + */ +static inline void spi_ll_slave_set_tx_bitlen(spi_dev_t *hw, size_t bitlen) +{ + //This is not used in esp32c3 +} + +/** + * Set the length of command phase. + * + * When in 4-bit mode, the SPI cycles of the phase will be shorter. E.g. 16-bit + * command phases takes 4 cycles in 4-bit mode. + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen Length of command phase, in bits. 0 to disable the command phase. + */ +static inline void spi_ll_set_command_bitlen(spi_dev_t *hw, int bitlen) +{ + hw->user2.usr_command_bitlen = bitlen - 1; + hw->user.usr_command = bitlen ? 1 : 0; +} + +/** + * Set the length of address phase. + * + * When in 4-bit mode, the SPI cycles of the phase will be shorter. E.g. 16-bit + * address phases takes 4 cycles in 4-bit mode. + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen Length of address phase, in bits. 0 to disable the address phase. + */ +static inline void spi_ll_set_addr_bitlen(spi_dev_t *hw, int bitlen) +{ + hw->user1.usr_addr_bitlen = bitlen - 1; + hw->user.usr_addr = bitlen ? 1 : 0; +} + +/** + * Set the address value in an intuitive way. + * + * The length and lsbfirst is required to shift and swap the address to the right place. + * + * @param hw Beginning address of the peripheral registers. + * @param address Address to set + * @param addrlen Length of the address phase + * @param lsbfirst Whether the LSB first feature is enabled. + */ +static inline void spi_ll_set_address(spi_dev_t *hw, uint64_t addr, int addrlen, uint32_t lsbfirst) +{ + if (lsbfirst) { + /* The output address start from the LSB of the highest byte, i.e. + * addr[24] -> addr[31] + * ... + * addr[0] -> addr[7] + * So swap the byte order to let the LSB sent first. + */ + addr = HAL_SWAP32(addr); + //otherwise only addr register is sent + hw->addr.val = addr; + } else { + // shift the address to MSB of addr register. + // output address will be sent from MSB to LSB of addr register + hw->addr.val = addr << (32 - addrlen); + } +} + +/** + * Set the command value in an intuitive way. + * + * The length and lsbfirst is required to shift and swap the command to the right place. + * + * @param hw Beginning command of the peripheral registers. + * @param command Command to set + * @param addrlen Length of the command phase + * @param lsbfirst Whether the LSB first feature is enabled. + */ +static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst) +{ + if (lsbfirst) { + // The output command start from bit0 to bit 15, kept as is. + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, cmd); + } else { + /* Output command will be sent from bit 7 to 0 of command_value, and + * then bit 15 to 8 of the same register field. Shift and swap to send + * more straightly. + */ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, HAL_SPI_SWAP_DATA_TX(cmd, cmdlen)); + } +} + +/** + * Set dummy clocks to output before RX phase (master), or clocks to skip + * before the data phase and after the address phase (slave). + * + * Note this phase is also used to compensate RX timing in half duplex mode. + * + * @param hw Beginning address of the peripheral registers. + * @param dummy_n Dummy cycles used. 0 to disable the dummy phase. + */ +static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n) +{ + hw->user.usr_dummy = dummy_n ? 1 : 0; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); +} + +/** + * Enable/disable the RX data phase. + * + * @param hw Beginning address of the peripheral registers. + * @param enable True if RX phase exist, otherwise false. + */ +static inline void spi_ll_enable_miso(spi_dev_t *hw, int enable) +{ + hw->user.usr_miso = enable; +} + +/** + * Enable/disable the TX data phase. + * + * @param hw Beginning address of the peripheral registers. + * @param enable True if TX phase exist, otherwise false. + */ +static inline void spi_ll_enable_mosi(spi_dev_t *hw, int enable) +{ + hw->user.usr_mosi = enable; +} + +/** + * Get the received bit length of the slave. + * + * @param hw Beginning address of the peripheral registers. + * + * @return Received bits of the slave. + */ +static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw) +{ + return hw->slave1.slv_data_bitlen; +} + +/*------------------------------------------------------------------------------ + * Interrupts + *----------------------------------------------------------------------------*/ +//helper macros to generate code for each interrupts +#define FOR_EACH_ITEM(op, list) do { list(op) } while(0) +#define INTR_LIST(item) \ + item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done, dma_int_raw.trans_done, dma_int_clr.trans_done=1) \ + item(SPI_LL_INTR_RDBUF, dma_int_ena.slv_rd_buf_done, dma_int_raw.slv_rd_buf_done, dma_int_clr.slv_rd_buf_done=1) \ + item(SPI_LL_INTR_WRBUF, dma_int_ena.slv_wr_buf_done, dma_int_raw.slv_wr_buf_done, dma_int_clr.slv_wr_buf_done=1) \ + item(SPI_LL_INTR_RDDMA, dma_int_ena.slv_rd_dma_done, dma_int_raw.slv_rd_dma_done, dma_int_clr.slv_rd_dma_done=1) \ + item(SPI_LL_INTR_WRDMA, dma_int_ena.slv_wr_dma_done, dma_int_raw.slv_wr_dma_done, dma_int_clr.slv_wr_dma_done=1) \ + item(SPI_LL_INTR_SEG_DONE, dma_int_ena.dma_seg_trans_done, dma_int_raw.dma_seg_trans_done, dma_int_clr.dma_seg_trans_done=1) \ + item(SPI_LL_INTR_CMD7, dma_int_ena.slv_cmd7, dma_int_raw.slv_cmd7, dma_int_clr.slv_cmd7=1) \ + item(SPI_LL_INTR_CMD8, dma_int_ena.slv_cmd8, dma_int_raw.slv_cmd8, dma_int_clr.slv_cmd8=1) \ + item(SPI_LL_INTR_CMD9, dma_int_ena.slv_cmd9, dma_int_raw.slv_cmd9, dma_int_clr.slv_cmd9=1) \ + item(SPI_LL_INTR_CMDA, dma_int_ena.slv_cmda, dma_int_raw.slv_cmda, dma_int_clr.slv_cmda=1) + + +static inline void spi_ll_enable_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) +{ +#define ENA_INTR(intr_bit, en_reg, ...) if (intr_mask & (intr_bit)) hw->en_reg = 1; + FOR_EACH_ITEM(ENA_INTR, INTR_LIST); +#undef ENA_INTR +} + +static inline void spi_ll_disable_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) +{ +#define DIS_INTR(intr_bit, en_reg, ...) if (intr_mask & (intr_bit)) hw->en_reg = 0; + FOR_EACH_ITEM(DIS_INTR, INTR_LIST); +#undef DIS_INTR +} + +static inline void spi_ll_set_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) +{ +#define SET_INTR(intr_bit, _, st_reg, ...) if (intr_mask & (intr_bit)) hw->st_reg = 1; + FOR_EACH_ITEM(SET_INTR, INTR_LIST); +#undef SET_INTR +} + +static inline void spi_ll_clear_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) +{ +#define CLR_INTR(intr_bit, _, __, clr_reg) if (intr_mask & (intr_bit)) hw->clr_reg; + FOR_EACH_ITEM(CLR_INTR, INTR_LIST); +#undef CLR_INTR +} + +static inline bool spi_ll_get_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) +{ +#define GET_INTR(intr_bit, _, st_reg, ...) if (intr_mask & (intr_bit) && hw->st_reg) return true; + FOR_EACH_ITEM(GET_INTR, INTR_LIST); + return false; +#undef GET_INTR +} + +#undef FOR_EACH_ITEM +#undef INTR_LIST + +/** + * Disable the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_disable_int(spi_dev_t *hw) +{ + hw->dma_int_ena.trans_done = 0; +} + +/** + * Clear the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_clear_int_stat(spi_dev_t *hw) +{ + hw->dma_int_raw.trans_done = 0; +} + +/** + * Set the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_set_int_stat(spi_dev_t *hw) +{ + hw->dma_int_raw.trans_done = 1; +} + +/** + * Enable the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_enable_int(spi_dev_t *hw) +{ + hw->dma_int_ena.trans_done = 1; +} + +/*------------------------------------------------------------------------------ + * Slave HD + *----------------------------------------------------------------------------*/ +static inline void spi_ll_slave_hd_set_len_cond(spi_dev_t *hw, spi_ll_trans_len_cond_t cond_mask) +{ + hw->slave.slv_rdbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0; + hw->slave.slv_wrbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0; + hw->slave.slv_rddma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0; + hw->slave.slv_wrdma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0; +} + +static inline int spi_ll_slave_get_rx_byte_len(spi_dev_t *hw) +{ + return hw->slave1.slv_data_bitlen / 8; +} + +static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) +{ + return hw->slave1.slv_last_addr; +} + +#undef SPI_LL_RST_MASK +#undef SPI_LL_UNUSED_INT_MASK + +/** + * Get the base spi command + * + * @param cmd_t Command value + */ +static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) +{ + uint8_t cmd_base = 0x00; + switch (cmd_t) + { + case SPI_CMD_HD_WRBUF: + cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; + break; + case SPI_CMD_HD_RDBUF: + cmd_base = SPI_LL_BASE_CMD_HD_RDBUF; + break; + case SPI_CMD_HD_WRDMA: + cmd_base = SPI_LL_BASE_CMD_HD_WRDMA; + break; + case SPI_CMD_HD_RDDMA: + cmd_base = SPI_LL_BASE_CMD_HD_RDDMA; + break; + case SPI_CMD_HD_SEG_END: + cmd_base = SPI_LL_BASE_CMD_HD_SEG_END; + break; + case SPI_CMD_HD_EN_QPI: + cmd_base = SPI_LL_BASE_CMD_HD_EN_QPI; + break; + case SPI_CMD_HD_WR_END: + cmd_base = SPI_LL_BASE_CMD_HD_WR_END; + break; + case SPI_CMD_HD_INT0: + cmd_base = SPI_LL_BASE_CMD_HD_INT0; + break; + case SPI_CMD_HD_INT1: + cmd_base = SPI_LL_BASE_CMD_HD_INT1; + break; + case SPI_CMD_HD_INT2: + cmd_base = SPI_LL_BASE_CMD_HD_INT2; + break; + default: + HAL_ASSERT(cmd_base); + } + return cmd_base; +} + +/** + * Get the spi communication command + * + * @param cmd_t Base command value + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode) +{ + uint8_t cmd_base = spi_ll_get_slave_hd_base_command(cmd_t); + uint8_t cmd_mod = 0x00; //CMD:1-bit, ADDR:1-bit, DATA:1-bit + + if (line_mode.data_lines == 2) { + if (line_mode.addr_lines == 2) { + cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit + } else { + cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit + } + } else if (line_mode.data_lines == 4) { + if (line_mode.addr_lines == 4) { + cmd_mod = 0xA0; //CMD:1-bit, ADDR:4-bit, DATA:4-bit + } else { + cmd_mod = 0x20; //CMD:1-bit, ADDR:1-bit, DATA:4-bit + } + } + if (cmd_base == SPI_LL_BASE_CMD_HD_SEG_END || cmd_base == SPI_LL_BASE_CMD_HD_EN_QPI) { + cmd_mod = 0x00; + } + + return cmd_base | cmd_mod; +} + +/** + * Get the dummy bits + * + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode) +{ + return 8; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/spimem_flash_ll.h b/components/hal/esp32c6/include/hal/spimem_flash_ll.h new file mode 100644 index 0000000000..25e942f5bc --- /dev/null +++ b/components/hal/esp32c6/include/hal/spimem_flash_ll.h @@ -0,0 +1,596 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The ll is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The Lowlevel layer for SPI Flash + +#pragma once + +#include +#include // For MIN/MAX +#include +#include + +#include "soc/spi_periph.h" +#include "soc/spi_mem_struct.h" +#include "hal/assert.h" +#include "hal/spi_types.h" +#include "hal/spi_flash_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define spimem_flash_ll_get_hw(host_id) (((host_id)==SPI1_HOST ? &SPIMEM1 : NULL )) +#define spimem_flash_ll_hw_get_id(dev) ((dev) == (void*)&SPIMEM1? SPI1_HOST: -1) + +typedef typeof(SPIMEM1.clock.val) spimem_flash_ll_clock_reg_t; + +/*------------------------------------------------------------------------------ + * Control + *----------------------------------------------------------------------------*/ +/** + * Reset peripheral registers before configuration and starting control + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_reset(spi_mem_dev_t *dev) +{ + dev->user.val = 0; + dev->ctrl.val = 0; +} + +/** + * Check whether the previous operation is done. + * + * @param dev Beginning address of the peripheral registers. + * + * @return true if last command is done, otherwise false. + */ +static inline bool spimem_flash_ll_cmd_is_done(const spi_mem_dev_t *dev) +{ + return (dev->cmd.val == 0); +} + +/** + * Erase the flash chip. + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_erase_chip(spi_mem_dev_t *dev) +{ + dev->cmd.flash_ce = 1; +} + +/** + * Erase the sector, the address should be set by spimem_flash_ll_set_address. + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_erase_sector(spi_mem_dev_t *dev) +{ + dev->ctrl.val = 0; + dev->cmd.flash_se = 1; +} + +/** + * Erase the block, the address should be set by spimem_flash_ll_set_address. + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_erase_block(spi_mem_dev_t *dev) +{ + dev->cmd.flash_be = 1; +} + +/** + * Suspend erase/program operation. + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_suspend(spi_mem_dev_t *dev) +{ + dev->flash_sus_ctrl.flash_pes = 1; +} + +/** + * Resume suspended erase/program operation. + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_resume(spi_mem_dev_t *dev) +{ + dev->flash_sus_ctrl.flash_per = 1; +} + +/** + * Initialize auto suspend mode, and esp32c3 doesn't support disable auto-suspend. + * + * @param dev Beginning address of the peripheral registers. + * @param auto_sus Enable/disable Flash Auto-Suspend. + */ +static inline void spimem_flash_ll_auto_suspend_init(spi_mem_dev_t *dev, bool auto_sus) +{ + dev->flash_sus_ctrl.flash_pes_en = auto_sus; +} + +/** + * Initialize auto resume mode + * + * @param dev Beginning address of the peripheral registers. + * @param auto_res Enable/Disable Flash Auto-Resume. + * + */ +static inline void spimem_flash_ll_auto_resume_init(spi_mem_dev_t *dev, bool auto_res) +{ + dev->flash_sus_ctrl.pes_per_en = auto_res; +} + +/** + * Setup the flash suspend command, may vary from chips to chips. + * + * @param dev Beginning address of the peripheral registers. + * @param sus_cmd Flash suspend command. + * + */ +static inline void spimem_flash_ll_suspend_cmd_setup(spi_mem_dev_t *dev, uint32_t sus_cmd) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, flash_pes_command, sus_cmd); +} + +/** + * Setup the flash resume command, may vary from chips to chips. + * + * @param dev Beginning address of the peripheral registers. + * @param res_cmd Flash resume command. + * + */ +static inline void spimem_flash_ll_resume_cmd_setup(spi_mem_dev_t *dev, uint32_t res_cmd) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->sus_status, flash_per_command, res_cmd); +} + +/** + * Setup the flash read suspend status command, may vary from chips to chips. + * + * @param dev Beginning address of the peripheral registers. + * @param pesr_cmd Flash read suspend status command. + * + */ +static inline void spimem_flash_ll_rd_sus_cmd_setup(spi_mem_dev_t *dev, uint32_t pesr_cmd) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, wait_pesr_command, pesr_cmd); +} + +/** + * Setup to check SUS/SUS1/SUS2 to ensure the suspend status of flashs. + * + * @param dev Beginning address of the peripheral registers. + * @param sus_check_sus_en 1: enable, 0: disable. + * + */ +static inline void spimem_flash_ll_sus_check_sus_setup(spi_mem_dev_t *dev, bool sus_check_sus_en) +{ + dev->flash_sus_ctrl.sus_timeout_cnt = 5; + dev->flash_sus_ctrl.pes_end_en = sus_check_sus_en; +} + +/** + * Setup to check SUS/SUS1/SUS2 to ensure the resume status of flashs. + * + * @param dev Beginning address of the peripheral registers. + * @param sus_check_sus_en 1: enable, 0: disable. + * + */ +static inline void spimem_flash_ll_res_check_sus_setup(spi_mem_dev_t *dev, bool res_check_sus_en) +{ + dev->flash_sus_ctrl.sus_timeout_cnt = 5; + dev->flash_sus_ctrl.per_end_en = res_check_sus_en; +} + +/** + * Set 8 bit command to read suspend status + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint32_t sus_conf) +{ + dev->flash_sus_ctrl.frd_sus_2b = 0; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, pesr_end_msk, sus_conf); +} + +/** + * Initialize auto wait idle mode + * + * @param dev Beginning address of the peripheral registers. + * @param auto_waiti Enable/disable auto wait-idle function + */ +static inline void spimem_flash_ll_auto_wait_idle_init(spi_mem_dev_t *dev, bool auto_waiti) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_waiti_ctrl, waiti_cmd, 0x05); + dev->flash_sus_ctrl.flash_per_wait_en = auto_waiti; + dev->flash_sus_ctrl.flash_pes_wait_en = auto_waiti; +} + +/** + * Return the suspend status of erase or program operations. + * + * @param dev Beginning address of the peripheral registers. + * + * @return true if suspended, otherwise false. + */ +static inline bool spimem_flash_ll_sus_status(spi_mem_dev_t *dev) +{ + return dev->sus_status.flash_sus; +} + +/** + * Enable/disable write protection for the flash chip. + * + * @param dev Beginning address of the peripheral registers. + * @param wp true to enable the protection, false to disable (write enable). + */ +static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp) +{ + if (wp) { + dev->cmd.flash_wrdi = 1; + } else { + dev->cmd.flash_wren = 1; + } +} + +/** + * Get the read data from the buffer after ``spimem_flash_ll_read`` is done. + * + * @param dev Beginning address of the peripheral registers. + * @param buffer Buffer to hold the output data + * @param read_len Length to get out of the buffer + */ +static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buffer, uint32_t read_len) +{ + if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) { + // If everything is word-aligned, do a faster memcpy + memcpy(buffer, (void *)dev->data_buf, read_len); + } else { + // Otherwise, slow(er) path copies word by word + int copy_len = read_len; + for (int i = 0; i < (read_len + 3) / 4; i++) { + int word_len = MIN(sizeof(uint32_t), copy_len); + uint32_t word = dev->data_buf[i]; + memcpy(buffer, &word, word_len); + buffer = (void *)((intptr_t)buffer + word_len); + copy_len -= word_len; + } + } +} + +/** + * Set the data to be written in the data buffer. + * + * @param dev Beginning address of the peripheral registers. + * @param buffer Buffer holding the data + * @param length Length of data in bytes. + */ +static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const void *buffer, uint32_t length) +{ + // Load data registers, word at a time + int num_words = (length + 3) / 4; + for (int i = 0; i < num_words; i++) { + uint32_t word = 0; + uint32_t word_len = MIN(length, sizeof(word)); + memcpy(&word, buffer, word_len); + dev->data_buf[i] = word; + length -= word_len; + buffer = (void *)((intptr_t)buffer + word_len); + } +} + + +/** + * Program a page of the flash chip. Call ``spimem_flash_ll_set_address`` before + * this to set the address to program. + * + * @param dev Beginning address of the peripheral registers. + * @param buffer Buffer holding the data to program + * @param length Length to program. + */ +static inline void spimem_flash_ll_program_page(spi_mem_dev_t *dev, const void *buffer, uint32_t length) +{ + dev->user.usr_dummy = 0; + spimem_flash_ll_set_buffer_data(dev, buffer, length); + dev->cmd.flash_pp = 1; +} + +/** + * Trigger a user defined transaction. All phases, including command, address, dummy, and the data phases, + * should be configured before this is called. + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_user_start(spi_mem_dev_t *dev) +{ + dev->cmd.usr = 1; +} + +/** + * Check whether the host is idle to perform new commands. + * + * @param dev Beginning address of the peripheral registers. + * + * @return true if the host is idle, otherwise false + */ +static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev) +{ + return dev->cmd.mst_st == 0; +} + +/** + * Set phases for user-defined transaction to read + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev) +{ + typeof (dev->user) user = { + .usr_command = 1, + .usr_mosi = 0, + .usr_miso = 1, + .usr_addr = 1, + }; + dev->user = user; +} +/*------------------------------------------------------------------------------ + * Configs + *----------------------------------------------------------------------------*/ +/** + * Select which pin to use for the flash + * + * @param dev Beginning address of the peripheral registers. + * @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins. + */ +static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin) +{ + dev->misc.cs0_dis = (pin == 0) ? 0 : 1; + dev->misc.cs1_dis = (pin == 1) ? 0 : 1; +} + +/** + * Set the read io mode. + * + * @param dev Beginning address of the peripheral registers. + * @param read_mode I/O mode to use in the following transactions. + */ +static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode) +{ + typeof (dev->ctrl) ctrl = dev->ctrl; + ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M); + ctrl.val |= SPI_MEM_FASTRD_MODE_M; + switch (read_mode) { + case SPI_FLASH_FASTRD: + //the default option + break; + case SPI_FLASH_QIO: + ctrl.fread_qio = 1; + break; + case SPI_FLASH_QOUT: + ctrl.fread_quad = 1; + break; + case SPI_FLASH_DIO: + ctrl.fread_dio = 1; + break; + case SPI_FLASH_DOUT: + ctrl.fread_dual = 1; + break; + case SPI_FLASH_SLOWRD: + ctrl.fastrd_mode = 0; + break; + default: + abort(); + } + dev->ctrl = ctrl; +} + +/** + * Set clock frequency to work at. + * + * @param dev Beginning address of the peripheral registers. + * @param clock_val pointer to the clock value to set + */ +static inline void spimem_flash_ll_set_clock(spi_mem_dev_t *dev, spimem_flash_ll_clock_reg_t *clock_val) +{ + dev->clock.val = *clock_val; +} + +/** + * Set the input length, in bits. + * + * @param dev Beginning address of the peripheral registers. + * @param bitlen Length of input, in bits. + */ +static inline void spimem_flash_ll_set_miso_bitlen(spi_mem_dev_t *dev, uint32_t bitlen) +{ + dev->user.usr_miso = bitlen > 0; + dev->miso_dlen.usr_miso_bit_len = bitlen ? (bitlen - 1) : 0; +} + +/** + * Set the output length, in bits (not including command, address and dummy + * phases) + * + * @param dev Beginning address of the peripheral registers. + * @param bitlen Length of output, in bits. + */ +static inline void spimem_flash_ll_set_mosi_bitlen(spi_mem_dev_t *dev, uint32_t bitlen) +{ + dev->user.usr_mosi = bitlen > 0; + dev->mosi_dlen.usr_mosi_bit_len = bitlen ? (bitlen - 1) : 0; +} + +/** + * Set the command. + * + * @param dev Beginning address of the peripheral registers. + * @param command Command to send + * @param bitlen Length of the command + */ +static inline void spimem_flash_ll_set_command(spi_mem_dev_t *dev, uint32_t command, uint32_t bitlen) +{ + dev->user.usr_command = 1; + typeof(dev->user2) user2 = { + .usr_command_value = command, + .usr_command_bitlen = (bitlen - 1), + }; + dev->user2 = user2; +} + +/** + * Get the address length that is set in register, in bits. + * + * @param dev Beginning address of the peripheral registers. + * + */ +static inline int spimem_flash_ll_get_addr_bitlen(spi_mem_dev_t *dev) +{ + return dev->user.usr_addr ? dev->user1.usr_addr_bitlen + 1 : 0; +} + +/** + * Set the address length to send, in bits. Should be called before commands that requires the address e.g. erase sector, read, write... + * + * @param dev Beginning address of the peripheral registers. + * @param bitlen Length of the address, in bits + */ +static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t bitlen) +{ + dev->user1.usr_addr_bitlen = (bitlen - 1); + dev->user.usr_addr = bitlen ? 1 : 0; +} + +/** + * Set the address to send. Should be called before commands that requires the address e.g. erase sector, read, write... + * + * @param dev Beginning address of the peripheral registers. + * @param addr Address to send + */ +static inline void spimem_flash_ll_set_address(spi_mem_dev_t *dev, uint32_t addr) +{ + dev->addr = addr; +} + +/** + * Set the address to send in user mode. Should be called before commands that requires the address e.g. erase sector, read, write... + * + * @param dev Beginning address of the peripheral registers. + * @param addr Address to send + */ +static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t addr, uint32_t bitlen) +{ + (void)bitlen; + spimem_flash_ll_set_address(dev, addr); +} + +/** + * Set the length of dummy cycles. + * + * @param dev Beginning address of the peripheral registers. + * @param dummy_n Cycles of dummy phases + */ +static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n) +{ + dev->user.usr_dummy = dummy_n ? 1 : 0; + dev->user1.usr_dummy_cyclelen = dummy_n - 1; +} + +/** + * Set D/Q output level during dummy phase + * + * @param dev Beginning address of the peripheral registers. + * @param out_en whether to enable IO output for dummy phase + * @param out_level dummy output level + */ +static inline void spimem_flash_ll_set_dummy_out(spi_mem_dev_t *dev, uint32_t out_en, uint32_t out_lev) +{ + // dev->ctrl.fdummy_out = out_en; // TODO: IDF-5333 removed + dev->ctrl.q_pol = out_lev; + dev->ctrl.d_pol = out_lev; +} + +/** + * Set CS hold time. + * + * @param dev Beginning address of the peripheral registers. + * @param hold_n CS hold time config used by the host. + */ +static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n) +{ + dev->ctrl2.cs_hold_time = hold_n - 1; + dev->user.cs_hold = (hold_n > 0? 1: 0); +} + +static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time) +{ + dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0); + dev->ctrl2.cs_setup_time = cs_setup_time - 1; +} + +/** + * Get the spi flash source clock frequency. Used for calculating + * the divider parameters. + * + * @param None + * + * @return the frequency of spi flash clock source.(MHz) + */ +static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void) +{ + // TODO: IDF-5333 + // // TODO: Default is PLL480M, this is hard-coded. + // // In the future, we can get the CPU clock source by calling interface. + // uint8_t clock_val = 0; + // switch (SPIMEM0.core_clk_sel.spi01_clk_sel) { + // case 0: + // clock_val = 80; + // break; + // case 1: + // clock_val = 120; + // break; + // case 2: + // clock_val = 160; + // break; + // default: + // abort(); + // } + // return clock_val; + return 80; +} + +/** + * Calculate spi_flash clock frequency division parameters for register. + * + * @param clkdiv frequency division factor + * + * @return Register setting for the given clock division factor. + */ +static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv) +{ + uint32_t div_parameter; + // See comments of `clock` in `spi_mem_struct.h` + if (clkdiv == 1) { + div_parameter = (1 << 31); + } else { + div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16)); + } + return div_parameter; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/systimer_ll.h b/components/hal/esp32c6/include/hal/systimer_ll.h new file mode 100644 index 0000000000..8818a44961 --- /dev/null +++ b/components/hal/esp32c6/include/hal/systimer_ll.h @@ -0,0 +1,159 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include "soc/systimer_struct.h" +#include "hal/assert.h" + +#define SYSTIMER_LL_COUNTER_CLOCK 0 // Counter used by esptimer, to generate the system level wall clock +#define SYSTIMER_LL_COUNTER_OS_TICK 1 // Counter used by RTOS porting layer, to generate the OS tick +#define SYSTIMER_LL_ALARM_OS_TICK_CORE0 0 // Alarm used by OS tick, dedicated for core 0 +#define SYSTIMER_LL_ALARM_CLOCK 2 // Alarm used by esptimer + +#ifdef __cplusplus +extern "C" { +#endif + +// All these functions get invoked either from ISR or HAL that linked to IRAM. +// Always inline these functions even no gcc optimization is applied. + +/******************* Clock *************************/ + +__attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en) +{ + dev->conf.clk_en = en; +} + +/******************* Counter *************************/ + +__attribute__((always_inline)) static inline void systimer_ll_enable_counter(systimer_dev_t *dev, uint32_t counter_id, bool en) +{ + if (en) { + dev->conf.val |= 1 << (30 - counter_id); + } else { + dev->conf.val &= ~(1 << (30 - counter_id)); + } +} + +__attribute__((always_inline)) static inline void systimer_ll_counter_can_stall_by_cpu(systimer_dev_t *dev, uint32_t counter_id, uint32_t cpu_id, bool can) +{ + if (can) { + dev->conf.val |= 1 << ((28 - counter_id * 2) - cpu_id); + } else { + dev->conf.val &= ~(1 << ((28 - counter_id * 2) - cpu_id)); + } +} + +__attribute__((always_inline)) static inline void systimer_ll_counter_snapshot(systimer_dev_t *dev, uint32_t counter_id) +{ + dev->unit_op[counter_id].timer_unit_update = 1; +} + +__attribute__((always_inline)) static inline bool systimer_ll_is_counter_value_valid(systimer_dev_t *dev, uint32_t counter_id) +{ + return dev->unit_op[counter_id].timer_unit_value_valid; +} + +__attribute__((always_inline)) static inline void systimer_ll_set_counter_value(systimer_dev_t *dev, uint32_t counter_id, uint64_t value) +{ + dev->unit_load_val[counter_id].hi.timer_unit_load_hi = value >> 32; + dev->unit_load_val[counter_id].lo.timer_unit_load_lo = value & 0xFFFFFFFF; +} + +__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_low(systimer_dev_t *dev, uint32_t counter_id) +{ + return dev->unit_val[counter_id].lo.timer_unit_value_lo; +} + +__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_high(systimer_dev_t *dev, uint32_t counter_id) +{ + return dev->unit_val[counter_id].hi.timer_unit_value_hi; +} + +__attribute__((always_inline)) static inline void systimer_ll_apply_counter_value(systimer_dev_t *dev, uint32_t counter_id) +{ + dev->unit_load[counter_id].val = 0x01; +} + +/******************* Alarm *************************/ + +__attribute__((always_inline)) static inline void systimer_ll_set_alarm_target(systimer_dev_t *dev, uint32_t alarm_id, uint64_t value) +{ + dev->target_val[alarm_id].hi.timer_target_hi = value >> 32; + dev->target_val[alarm_id].lo.timer_target_lo = value & 0xFFFFFFFF; +} + +__attribute__((always_inline)) static inline uint64_t systimer_ll_get_alarm_target(systimer_dev_t *dev, uint32_t alarm_id) +{ + return ((uint64_t)(dev->target_val[alarm_id].hi.timer_target_hi) << 32) | dev->target_val[alarm_id].lo.timer_target_lo; +} + +__attribute__((always_inline)) static inline void systimer_ll_connect_alarm_counter(systimer_dev_t *dev, uint32_t alarm_id, uint32_t counter_id) +{ + dev->target_conf[alarm_id].target_timer_unit_sel = counter_id; +} + +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_oneshot(systimer_dev_t *dev, uint32_t alarm_id) +{ + dev->target_conf[alarm_id].target_period_mode = 0; +} + +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_period(systimer_dev_t *dev, uint32_t alarm_id) +{ + dev->target_conf[alarm_id].target_period_mode = 1; +} + +__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(systimer_dev_t *dev, uint32_t alarm_id, uint32_t period) +{ + HAL_ASSERT(period < (1 << 26)); + dev->target_conf[alarm_id].target_period = period; +} + +__attribute__((always_inline)) static inline uint32_t systimer_ll_get_alarm_period(systimer_dev_t *dev, uint32_t alarm_id) +{ + return dev->target_conf[alarm_id].target_period; +} + +__attribute__((always_inline)) static inline void systimer_ll_apply_alarm_value(systimer_dev_t *dev, uint32_t alarm_id) +{ + dev->comp_load[alarm_id].val = 0x01; +} + +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm(systimer_dev_t *dev, uint32_t alarm_id, bool en) +{ + if (en) { + dev->conf.val |= 1 << (24 - alarm_id); + } else { + dev->conf.val &= ~(1 << (24 - alarm_id)); + } +} + +/******************* Interrupt *************************/ + +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_int(systimer_dev_t *dev, uint32_t alarm_id, bool en) +{ + if (en) { + dev->int_ena.val |= 1 << alarm_id; + } else { + dev->int_ena.val &= ~(1 << alarm_id); + } +} + +__attribute__((always_inline)) static inline bool systimer_ll_is_alarm_int_fired(systimer_dev_t *dev, uint32_t alarm_id) +{ + return dev->int_st.val & (1 << alarm_id); +} + +__attribute__((always_inline)) static inline void systimer_ll_clear_alarm_int(systimer_dev_t *dev, uint32_t alarm_id) +{ + dev->int_clr.val |= 1 << alarm_id; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/timer_ll.h b/components/hal/esp32c6/include/hal/timer_ll.h new file mode 100644 index 0000000000..96c5490a57 --- /dev/null +++ b/components/hal/esp32c6/include/hal/timer_ll.h @@ -0,0 +1,304 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "hal/timer_types.h" +#include "soc/timer_group_struct.h" +#include "soc/pcr_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Get timer group register base address with giving group number +#define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1)) +#define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id)) + +/** + * @brief Set clock source for timer + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + * @param clk_src Clock source + */ +static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num, gptimer_clock_source_t clk_src) +{ + (void)timer_num; // only one timer in each group + uint8_t clk_id = 0; + switch (clk_src) { + case GPTIMER_CLK_SRC_XTAL: + clk_id = 0; + break; + case GPTIMER_CLK_SRC_APB: + clk_id = 1; + break; + default: + HAL_ASSERT(false); + break; + } + if (hw == &TIMERG0) { + PCR.timergroup0_timer_clk_conf.tg0_timer_clk_sel = clk_id; + } else { + PCR.timergroup1_timer_clk_conf.tg1_timer_clk_sel = clk_id; + } +} + +/** + * @brief Enable Timer Group (GPTimer) module clock + * + * @param hw Timer Group register base address + * @param timer_num Timer index in the group + * @param en true to enable, false to disable + */ +static inline void timer_ll_enable_clock(timg_dev_t *hw, uint32_t timer_num, bool en) +{ + (void)timer_num; // only one timer in each group + if (hw == &TIMERG0) { + PCR.timergroup0_timer_clk_conf.tg0_timer_clk_en = en; + } else { + PCR.timergroup1_timer_clk_conf.tg1_timer_clk_en = en; + } +} + +/** + * @brief Enable alarm event + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + * @param en True: enable alarm + * False: disable alarm + */ +__attribute__((always_inline)) +static inline void timer_ll_enable_alarm(timg_dev_t *hw, uint32_t timer_num, bool en) +{ + hw->hw_timer[timer_num].config.tx_alarm_en = en; +} + +/** + * @brief Set clock prescale for timer + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + * @param divider Prescale value (0 and 1 are not valid) + */ +static inline void timer_ll_set_clock_prescale(timg_dev_t *hw, uint32_t timer_num, uint32_t divider) +{ + HAL_ASSERT(divider >= 2 && divider <= 65536); + if (divider >= 65536) { + divider = 0; + } + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider); + hw->hw_timer[timer_num].config.tx_divcnt_rst = 1; +} + +/** + * @brief Enable auto-reload mode + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + * @param en True: enable auto reload mode + * False: disable auto reload mode + */ +__attribute__((always_inline)) +static inline void timer_ll_enable_auto_reload(timg_dev_t *hw, uint32_t timer_num, bool en) +{ + hw->hw_timer[timer_num].config.tx_autoreload = en; +} + +/** + * @brief Set count direction + * + * @param hw Timer peripheral register base address + * @param timer_num Timer number in the group + * @param direction Count direction + */ +static inline void timer_ll_set_count_direction(timg_dev_t *hw, uint32_t timer_num, gptimer_count_direction_t direction) +{ + hw->hw_timer[timer_num].config.tx_increase = (direction == GPTIMER_COUNT_UP); +} + +/** + * @brief Enable timer, start couting + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + * @param en True: enable the counter + * False: disable the counter + */ +__attribute__((always_inline)) +static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, bool en) +{ + hw->hw_timer[timer_num].config.tx_en = en; +} + +/** + * @brief Trigger software capture event + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + */ +__attribute__((always_inline)) +static inline void timer_ll_trigger_soft_capture(timg_dev_t *hw, uint32_t timer_num) +{ + hw->hw_timer[timer_num].update.tx_update = 1; + // Timer register is in a different clock domain from Timer hardware logic + // We need to wait for the update to take effect before fetching the count value + while (hw->hw_timer[timer_num].update.tx_update) { + } +} + +/** + * @brief Get counter value + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + * + * @return counter value + */ +__attribute__((always_inline)) +static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer_num) +{ + return ((uint64_t)hw->hw_timer[timer_num].hi.tx_hi << 32) | (hw->hw_timer[timer_num].lo.tx_lo); +} + +/** + * @brief Set alarm value + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + * @param alarm_value When counter reaches alarm value, alarm event will be triggered + */ +__attribute__((always_inline)) +static inline void timer_ll_set_alarm_value(timg_dev_t *hw, uint32_t timer_num, uint64_t alarm_value) +{ + hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t)(alarm_value >> 32); + hw->hw_timer[timer_num].alarmlo.tx_alarm_lo = (uint32_t)alarm_value; +} + +/** + * @brief Set reload value + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + * @param reload_val Reload counter value + */ +__attribute__((always_inline)) +static inline void timer_ll_set_reload_value(timg_dev_t *hw, uint32_t timer_num, uint64_t reload_val) +{ + hw->hw_timer[timer_num].loadhi.tx_load_hi = (uint32_t)(reload_val >> 32); + hw->hw_timer[timer_num].loadlo.tx_load_lo = (uint32_t)reload_val; +} + +/** + * @brief Get reload value + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + * @return reload count value + */ +static inline uint64_t timer_ll_get_reload_value(timg_dev_t *hw, uint32_t timer_num) +{ + return ((uint64_t)hw->hw_timer[timer_num].loadhi.tx_load_hi << 32) | (hw->hw_timer[timer_num].loadlo.tx_load_lo); +} + +/** + * @brief Trigger software reload, value set by `timer_ll_set_reload_value()` will be reflected into counter immediately + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + */ +static inline void timer_ll_trigger_soft_reload(timg_dev_t *hw, uint32_t timer_num) +{ + hw->hw_timer[timer_num].load.tx_load = 1; +} + +/** + * @brief Enable ETM module + * + * @param hw Timer Group register base address + * @param en True: enable ETM module, False: disable ETM module + */ +static inline void timer_ll_enable_etm(timg_dev_t *hw, bool en) +{ + hw->regclk.etm_en = en; +} + +/** + * @brief Enable timer interrupt by mask + * + * @param hw Timer Group register base address + * @param mask Mask of interrupt events + * @param en True: enable interrupt + * False: disable interrupt + */ +__attribute__((always_inline)) +static inline void timer_ll_enable_intr(timg_dev_t *hw, uint32_t mask, bool en) +{ + if (en) { + hw->int_ena_timers.val |= mask; + } else { + hw->int_ena_timers.val &= ~mask; + } +} + +/** + * @brief Get interrupt status + * + * @param hw Timer Group register base address + * + * @return Interrupt status + */ +__attribute__((always_inline)) +static inline uint32_t timer_ll_get_intr_status(timg_dev_t *hw) +{ + return hw->int_st_timers.val & 0x01; +} + +/** + * @brief Clear interrupt status by mask + * + * @param hw Timer Group register base address + * @param mask Interrupt events mask + */ +__attribute__((always_inline)) +static inline void timer_ll_clear_intr_status(timg_dev_t *hw, uint32_t mask) +{ + hw->int_clr_timers.val = mask; +} + +/** + * @brief Enable the register clock forever + * + * @param hw Timer Group register base address + * @param en True: Enable the register clock forever + * False: Register clock is enabled only when register operation happens + */ +static inline void timer_ll_enable_register_clock_always_on(timg_dev_t *hw, bool en) +{ + hw->regclk.clk_en = en; +} + +/** + * @brief Get interrupt status register address + * + * @param hw Timer Group register base address + * + * @return Interrupt status register address + */ +static inline volatile void *timer_ll_get_intr_status_reg(timg_dev_t *hw) +{ + return &hw->int_st_timers; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/uart_ll.h b/components/hal/esp32c6/include/hal/uart_ll.h new file mode 100644 index 0000000000..f1c5e57180 --- /dev/null +++ b/components/hal/esp32c6/include/hal/uart_ll.h @@ -0,0 +1,1087 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for UART register operations. +// Note that most of the register operations in this layer are non-atomic operations. + + +#pragma once + +#include "hal/misc.h" +#include "hal/uart_types.h" +#include "soc/uart_periph.h" +#include "soc/uart_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// The default fifo depth +#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN) +// Get UART hardware instance with giving uart num +#define UART_LL_GET_HW(num) (((num) == 0) ? (&UART0) : (&UART1)) + +#define UART_LL_MIN_WAKEUP_THRESH (2) +#define UART_LL_INTR_MASK (0x7ffff) //All interrupt mask + +#define UART_LL_FSM_IDLE (0x0) +#define UART_LL_FSM_TX_WAIT_SEND (0xf) + +// Define UART interrupts +typedef enum { + UART_INTR_RXFIFO_FULL = (0x1 << 0), + UART_INTR_TXFIFO_EMPTY = (0x1 << 1), + UART_INTR_PARITY_ERR = (0x1 << 2), + UART_INTR_FRAM_ERR = (0x1 << 3), + UART_INTR_RXFIFO_OVF = (0x1 << 4), + UART_INTR_DSR_CHG = (0x1 << 5), + UART_INTR_CTS_CHG = (0x1 << 6), + UART_INTR_BRK_DET = (0x1 << 7), + UART_INTR_RXFIFO_TOUT = (0x1 << 8), + UART_INTR_SW_XON = (0x1 << 9), + UART_INTR_SW_XOFF = (0x1 << 10), + UART_INTR_GLITCH_DET = (0x1 << 11), + UART_INTR_TX_BRK_DONE = (0x1 << 12), + UART_INTR_TX_BRK_IDLE = (0x1 << 13), + UART_INTR_TX_DONE = (0x1 << 14), + UART_INTR_RS485_PARITY_ERR = (0x1 << 15), + UART_INTR_RS485_FRM_ERR = (0x1 << 16), + UART_INTR_RS485_CLASH = (0x1 << 17), + UART_INTR_CMD_CHAR_DET = (0x1 << 18), + // UART_INTR_WAKEUP = (0x1 << 19), // TODO: IDF-5338 +} uart_intr_t; + +static inline void uart_ll_update(int uart_no) // TODO: IDF-5338 should use uart_dev_t *hw +{ + // TODO: set a timeout ?? + while(1) { + int update = GET_PERI_REG_BITS2(UART_REG_UPDATE_REG(uart_no), UART_REG_UPDATE_V, UART_REG_UPDATE_S); + if (!update) { + break; + } + } + SET_PERI_REG_MASK(UART_REG_UPDATE_REG(uart_no), UART_REG_UPDATE_M); +} + +/** + * @brief Configure the UART core reset. + * + * @param hw Beginning address of the peripheral registers. + * @param core_rst_en True to enable the core reset, otherwise set it false. + * + * @return None. + */ +static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) +{ + hw->clk_conf.rst_core = core_rst_en; +} + +/** + * @brief Enable the UART clock. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +static inline void uart_ll_sclk_enable(uart_dev_t *hw) +{ + hw->clk_conf.sclk_en = 1; + hw->clk_conf.rx_sclk_en = 1; + hw->clk_conf.tx_sclk_en = 1; +} + +/** + * @brief Disable the UART clock. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +static inline void uart_ll_sclk_disable(uart_dev_t *hw) +{ + hw->clk_conf.sclk_en = 0; + hw->clk_conf.rx_sclk_en = 0; + hw->clk_conf.tx_sclk_en = 0; +} + +/** + * @brief Set the UART source clock. + * + * @param hw Beginning address of the peripheral registers. + * @param source_clk The UART source clock. The source clock can be APB clock, RTC clock or XTAL clock. + * If the source clock is RTC/XTAL, the UART can still work when the APB changes. + * + * @return None. + */ +static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk) +{ + switch (source_clk) { + default: + case UART_SCLK_APB: + hw->clk_conf.sclk_sel = 1; + break; + case UART_SCLK_RTC: + hw->clk_conf.sclk_sel = 2; + break; + case UART_SCLK_XTAL: + hw->clk_conf.sclk_sel = 3; + break; + } +} + +/** + * @brief Get the UART source clock type. + * + * @param hw Beginning address of the peripheral registers. + * @param source_clk The pointer to accept the UART source clock type. + * + * @return None. + */ +static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk) +{ + switch (hw->clk_conf.sclk_sel) { + default: + case 1: + *source_clk = UART_SCLK_APB; + break; + case 2: + *source_clk = UART_SCLK_RTC; + break; + case 3: + *source_clk = UART_SCLK_XTAL; + break; + } +} + +/** + * @brief Configure the baud-rate. + * + * @param hw Beginning address of the peripheral registers. + * @param baud The baud rate to be set. + * @param sclk_freq Frequency of the clock source of UART, in Hz. + * + * @return None + */ +static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) +{ +#define DIV_UP(a, b) (((a) + (b) - 1) / (b)) + const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits + int sclk_div = DIV_UP(sclk_freq, max_div * baud); + + uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); + // The baud rate configuration register is divided into + // an integer part and a fractional part. + hw->clkdiv_sync.clkdiv_int = clk_div >> 4; + hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1); +#undef DIV_UP + uart_ll_update(0); // TODO: IDF-5338 +} + +/** + * @brief Get the current baud-rate. + * + * @param hw Beginning address of the peripheral registers. + * @param sclk_freq Frequency of the clock source of UART, in Hz. + * + * @return The current baudrate + */ +static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq) +{ + typeof(hw->clkdiv_sync) div_reg = hw->clkdiv_sync; + return ((sclk_freq << 4)) / (((div_reg.clkdiv_int << 4) | div_reg.clkdiv_frag) * (HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1)); +} + +/** + * @brief Enable the UART interrupt based on the given mask. + * + * @param hw Beginning address of the peripheral registers. + * @param mask The bitmap of the interrupts need to be enabled. + * + * @return None + */ +static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask) +{ + hw->int_ena.val |= mask; +} + +/** + * @brief Disable the UART interrupt based on the given mask. + * + * @param hw Beginning address of the peripheral registers. + * @param mask The bitmap of the interrupts need to be disabled. + * + * @return None + */ +static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask) +{ + hw->int_ena.val &= (~mask); +} + +/** + * @brief Get the UART interrupt status. + * + * @param hw Beginning address of the peripheral registers. + * + * @return The UART interrupt status. + */ +static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) +{ + return hw->int_st.val; +} + +/** + * @brief Clear the UART interrupt status based on the given mask. + * + * @param hw Beginning address of the peripheral registers. + * @param mask The bitmap of the interrupts need to be cleared. + * + * @return None + */ +static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask) +{ + hw->int_clr.val = mask; +} + +/** + * @brief Get status of enabled interrupt. + * + * @param hw Beginning address of the peripheral registers. + * + * @return interrupt enable value + */ +static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw) +{ + return hw->int_ena.val; +} + +/** + * @brief Read the UART rxfifo. + * + * @param hw Beginning address of the peripheral registers. + * @param buf The data buffer. The buffer size should be large than 128 byts. + * @param rd_len The data length needs to be read. + * + * @return None. + */ +static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) +{ + for (int i = 0; i < (int)rd_len; i++) { + buf[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->fifo, rxfifo_rd_byte); + } +} + +/** + * @brief Write byte to the UART txfifo. + * + * @param hw Beginning address of the peripheral registers. + * @param buf The data buffer. + * @param wr_len The data length needs to be writen. + * + * @return None + */ +static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len) +{ + for (int i = 0; i < (int)wr_len; i++) { + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->fifo, rxfifo_rd_byte, buf[i]); + } +} + +/** + * @brief Reset the UART hw rxfifo. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None + */ +static inline void uart_ll_rxfifo_rst(uart_dev_t *hw) +{ + hw->conf0_sync.rxfifo_rst = 1; + uart_ll_update(0); // TODO: IDF-5338 + hw->conf0_sync.rxfifo_rst = 0; + uart_ll_update(0); // TODO: IDF-5338 +} + +/** + * @brief Reset the UART hw txfifo. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None + */ +static inline void uart_ll_txfifo_rst(uart_dev_t *hw) +{ + hw->conf0_sync.txfifo_rst = 1; + uart_ll_update(0); // TODO: IDF-5338 + hw->conf0_sync.txfifo_rst = 0; + uart_ll_update(0); // TODO: IDF-5338 +} + +/** + * @brief Get the length of readable data in UART rxfifo. + * + * @param hw Beginning address of the peripheral registers. + * + * @return The readable data length in rxfifo. + */ +static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw) +{ + return hw->status.rxfifo_cnt; +} + +/** + * @brief Get the writable data length of UART txfifo. + * + * @param hw Beginning address of the peripheral registers. + * + * @return The data length of txfifo can be written. + */ +static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw) +{ + return UART_LL_FIFO_DEF_LEN - hw->status.txfifo_cnt; +} + +/** + * @brief Configure the UART stop bit. + * + * @param hw Beginning address of the peripheral registers. + * @param stop_bit The stop bit number to be set. + * + * @return None. + */ +static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit) +{ + hw->conf0_sync.stop_bit_num = stop_bit; + uart_ll_update(0); // TODO: IDF-5338 +} + +/** + * @brief Get the configuration of the UART stop bit. + * + * @param hw Beginning address of the peripheral registers. + * @param stop_bit The pointer to accept the stop bit configuration + * + * @return None. + */ +static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit) +{ + *stop_bit = hw->conf0_sync.stop_bit_num; +} + +/** + * @brief Configure the UART parity check mode. + * + * @param hw Beginning address of the peripheral registers. + * @param parity_mode The parity check mode to be set. + * + * @return None. + */ +static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode) +{ + if (parity_mode != UART_PARITY_DISABLE) { + hw->conf0_sync.parity = parity_mode & 0x1; + } + hw->conf0_sync.parity_en = (parity_mode >> 1) & 0x1; + uart_ll_update(0); // TODO: IDF-5338 +} + +/** + * @brief Get the UART parity check mode configuration. + * + * @param hw Beginning address of the peripheral registers. + * @param parity_mode The pointer to accept the parity check mode configuration. + * + * @return None. + */ +static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode) +{ + if (hw->conf0_sync.parity_en) { + *parity_mode = 0X2 | hw->conf0_sync.parity; + } else { + *parity_mode = UART_PARITY_DISABLE; + } +} + +/** + * @brief Set the UART rxfifo full threshold value. When the data in rxfifo is more than the threshold value, + * it will produce rxfifo_full_int_raw interrupt. + * + * @param hw Beginning address of the peripheral registers. + * @param full_thrhd The full threshold value of the rxfifo. `full_thrhd` should be less than `UART_LL_FIFO_DEF_LEN`. + * + * @return None. + */ +static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd) +{ + hw->conf1.rxfifo_full_thrhd = full_thrhd; +} + +/** + * @brief Set the txfifo empty threshold. when the data length in txfifo is less than threshold value, + * it will produce txfifo_empty_int_raw interrupt. + * + * @param hw Beginning address of the peripheral registers. + * @param empty_thrhd The empty threshold of txfifo. + * + * @return None. + */ +static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd) +{ + hw->conf1.txfifo_empty_thrhd = empty_thrhd; +} + +/** + * @brief Set the UART rx-idle threshold value. when receiver takes more time than rx_idle_thrhd to receive a byte data, + * it will produce frame end signal for uhci to stop receiving data. + * + * @param hw Beginning address of the peripheral registers. + * @param rx_idle_thr The rx-idle threshold to be set. + * + * @return None. + */ +static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr) +{ + hw->idle_conf_sync.rx_idle_thrhd = rx_idle_thr; + uart_ll_update(0); // TODO: IDF-5338 +} + +/** + * @brief Configure the duration time between transfers. + * + * @param hw Beginning address of the peripheral registers. + * @param idle_num the duration time between transfers. + * + * @return None. + */ +static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num) +{ + hw->idle_conf_sync.tx_idle_num = idle_num; + uart_ll_update(0); // TODO: IDF-5338 +} + +/** + * @brief Configure the transmiter to send break chars. + * + * @param hw Beginning address of the peripheral registers. + * @param break_num The number of the break chars need to be send. + * + * @return None. + */ +static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num) +{ + if (break_num > 0) { + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf_sync, tx_brk_num, break_num); + uart_ll_update(0); // TODO: IDF-5338 + hw->conf0_sync.txd_brk = 1; + uart_ll_update(0); // TODO: IDF-5338 + } else { + hw->conf0_sync.txd_brk = 0; + uart_ll_update(0); // TODO: IDF-5338 + } +} + +/** + * @brief Configure the UART hardware flow control. + * + * @param hw Beginning address of the peripheral registers. + * @param flow_ctrl The hw flow control configuration. + * @param rx_thrs The rx flow control signal will be active if the data length in rxfifo is more than this value. + * + * @return None. + */ +static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs) +{ + //only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set. + if (flow_ctrl & UART_HW_FLOWCTRL_RTS) { + hw->hwfc_conf_sync.rx_flow_thrhd = rx_thrs; + uart_ll_update(0); // TODO: IDF-5338 + hw->hwfc_conf_sync.rx_flow_en = 1; + uart_ll_update(0); // TODO: IDF-5338 + } else { + hw->hwfc_conf_sync.rx_flow_en = 0; + uart_ll_update(0); // TODO: IDF-5338 + } + if (flow_ctrl & UART_HW_FLOWCTRL_CTS) { + hw->conf0_sync.tx_flow_en = 1; + uart_ll_update(0); // TODO: IDF-5338 + } else { + hw->conf0_sync.tx_flow_en = 0; + uart_ll_update(0); // TODO: IDF-5338 + } +} + +/** + * @brief Configure the hardware flow control. + * + * @param hw Beginning address of the peripheral registers. + * @param flow_ctrl A pointer to accept the hw flow control configuration. + * + * @return None. + */ +static inline void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl) +{ + *flow_ctrl = UART_HW_FLOWCTRL_DISABLE; + if (hw->hwfc_conf_sync.rx_flow_en) { + *flow_ctrl |= UART_HW_FLOWCTRL_RTS; + } + if (hw->conf0_sync.tx_flow_en) { + *flow_ctrl |= UART_HW_FLOWCTRL_CTS; + } +} + +/** + * @brief Configure the software flow control. + * + * @param hw Beginning address of the peripheral registers. + * @param flow_ctrl The UART sofware flow control settings. + * @param sw_flow_ctrl_en Set true to enable software flow control, otherwise set it false. + * + * @return None. + */ +static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en) +{ + if (sw_flow_ctrl_en) { + hw->swfc_conf0_sync.xonoff_del = 1; + uart_ll_update(0); // TODO: IDF-5338 + hw->swfc_conf0_sync.sw_flow_con_en = 1; + uart_ll_update(0); // TODO: IDF-5338 + hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd; + hw->swfc_conf1.xoff_threshold = flow_ctrl->xoff_thrd; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_char, flow_ctrl->xon_char); + uart_ll_update(0); // TODO: IDF-5338 + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_char, flow_ctrl->xoff_char); + uart_ll_update(0); // TODO: IDF-5338 + } else { + hw->swfc_conf0_sync.sw_flow_con_en = 0; + uart_ll_update(0); // TODO: IDF-5338 + hw->swfc_conf0_sync.xonoff_del = 0; + uart_ll_update(0); // TODO: IDF-5338 + } +} + +/** + * @brief Configure the AT cmd char. When the receiver receives a continuous AT cmd char, it will produce at_cmd_char_det interrupt. + * + * @param hw Beginning address of the peripheral registers. + * @param cmd_char The AT cmd char configuration.The configuration member is: + * - cmd_char The AT cmd character + * - char_num The number of received AT cmd char must be equal to or greater than this value + * - gap_tout The interval between each AT cmd char, when the duration is less than this value, it will not take this data as AT cmd char + * - pre_idle The idle time before the first AT cmd char, when the duration is less than this value, it will not take the previous data as the last AT cmd char + * - post_idle The idle time after the last AT cmd char, when the duration is less than this value, it will not take this data as the first AT cmd char + * + * @return None. + */ +static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, data, cmd_char->cmd_char); + uart_ll_update(0); // TODO: IDF-5338 + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, char_num, cmd_char->char_num); + uart_ll_update(0); // TODO: IDF-5338 + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt_sync, post_idle_num, cmd_char->post_idle); + uart_ll_update(0); // TODO: IDF-5338 + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt_sync, pre_idle_num, cmd_char->pre_idle); + uart_ll_update(0); // TODO: IDF-5338 + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout_sync, rx_gap_tout, cmd_char->gap_tout); + uart_ll_update(0); // TODO: IDF-5338 +} + +/** + * @brief Set the UART data bit mode. + * + * @param hw Beginning address of the peripheral registers. + * @param data_bit The data bit mode to be set. + * + * @return None. + */ +static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit) +{ + hw->conf0_sync.bit_num = data_bit; + uart_ll_update(0); // TODO: IDF-5338 +} + +/** + * @brief Set the rts active level. + * + * @param hw Beginning address of the peripheral registers. + * @param level The rts active level, 0 or 1. + * + * @return None. + */ +static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level) +{ + hw->conf0_sync.sw_rts = level & 0x1; + uart_ll_update(0); // TODO: IDF-5338 +} + +/** + * @brief Set the dtr active level. + * + * @param hw Beginning address of the peripheral registers. + * @param level The dtr active level, 0 or 1. + * + * @return None. + */ +static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level) +{ + hw->conf1.sw_dtr = level & 0x1; +} + +/** + * @brief Set the UART wakeup threshold. + * + * @param hw Beginning address of the peripheral registers. + * @param wakeup_thrd The wakeup threshold value to be set. When the input rx edge changes more than this value, + * the UART will active from light sleeping mode. + * + * @return None. + */ +static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd) +{ + hw->sleep_conf2.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH; +} + +/** + * @brief Configure the UART work in normal mode. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +static inline void uart_ll_set_mode_normal(uart_dev_t *hw) +{ + hw->rs485_conf_sync.rs485_en = 0; + uart_ll_update(0); // TODO: IDF-5338 + hw->rs485_conf_sync.rs485tx_rx_en = 0; + uart_ll_update(0); // TODO: IDF-5338 + hw->rs485_conf_sync.rs485rxby_tx_en = 0; + uart_ll_update(0); // TODO: IDF-5338 + hw->conf0_sync.irda_en = 0; + uart_ll_update(0); // TODO: IDF-5338 +} + +/** + * @brief Configure the UART work in rs485_app_ctrl mode. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw) +{ + // Application software control, remove echo + hw->rs485_conf_sync.rs485rxby_tx_en = 1; + uart_ll_update(0); // TODO: IDF-5338 + hw->conf0_sync.irda_en = 0; + uart_ll_update(0); // TODO: IDF-5338 + hw->conf0_sync.sw_rts = 0; + uart_ll_update(0); // TODO: IDF-5338 + hw->conf0_sync.irda_en = 0; + uart_ll_update(0); // TODO: IDF-5338 + hw->rs485_conf_sync.dl0_en = 1; + uart_ll_update(0); // TODO: IDF-5338 + hw->rs485_conf_sync.dl1_en = 1; + uart_ll_update(0); // TODO: IDF-5338 + hw->rs485_conf_sync.rs485_en = 1; + uart_ll_update(0); // TODO: IDF-5338 +} + +/** + * @brief Configure the UART work in rs485_half_duplex mode. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw) +{ + // Enable receiver, sw_rts = 1 generates low level on RTS pin + hw->conf0_sync.sw_rts = 1; + uart_ll_update(0); // TODO: IDF-5338 + // Half duplex mode + hw->rs485_conf_sync.rs485tx_rx_en = 0; + uart_ll_update(0); // TODO: IDF-5338 + // Setting this bit will allow data to be transmitted while receiving data(full-duplex mode). + // But note that this full-duplex mode has no conflict detection function + hw->rs485_conf_sync.rs485rxby_tx_en = 0; + uart_ll_update(0); // TODO: IDF-5338 + hw->conf0_sync.irda_en = 0; + uart_ll_update(0); // TODO: IDF-5338 + hw->rs485_conf_sync.dl0_en = 1; + uart_ll_update(0); // TODO: IDF-5338 + hw->rs485_conf_sync.dl1_en = 1; + uart_ll_update(0); // TODO: IDF-5338 + hw->rs485_conf_sync.rs485_en = 1; + uart_ll_update(0); // TODO: IDF-5338 +} + +/** + * @brief Configure the UART work in collision_detect mode. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw) +{ + hw->conf0_sync.irda_en = 0; + uart_ll_update(0); // TODO: IDF-5338 + // Enable full-duplex mode + hw->rs485_conf_sync.rs485tx_rx_en = 1; + uart_ll_update(0); // TODO: IDF-5338 + // Transmitter should send data when the receiver is busy, + hw->rs485_conf_sync.rs485rxby_tx_en = 1; + uart_ll_update(0); // TODO: IDF-5338 + hw->rs485_conf_sync.dl0_en = 1; + uart_ll_update(0); // TODO: IDF-5338 + hw->rs485_conf_sync.dl1_en = 1; + uart_ll_update(0); // TODO: IDF-5338 + hw->conf0_sync.sw_rts = 0; + uart_ll_update(0); // TODO: IDF-5338 + hw->rs485_conf_sync.rs485_en = 1; + uart_ll_update(0); // TODO: IDF-5338 +} + +/** + * @brief Configure the UART work in irda mode. + * + * @param hw Beginning address of the peripheral registers. + * + * @return None. + */ +static inline void uart_ll_set_mode_irda(uart_dev_t *hw) +{ + hw->rs485_conf_sync.rs485_en = 0; + uart_ll_update(0); // TODO: IDF-5338 + hw->rs485_conf_sync.rs485tx_rx_en = 0; + uart_ll_update(0); // TODO: IDF-5338 + hw->rs485_conf_sync.rs485rxby_tx_en = 0; + uart_ll_update(0); // TODO: IDF-5338 + hw->conf0_sync.sw_rts = 0; + uart_ll_update(0); // TODO: IDF-5338 + hw->conf0_sync.irda_en = 1; + uart_ll_update(0); // TODO: IDF-5338 +} + +/** + * @brief Set uart mode. + * + * @param hw Beginning address of the peripheral registers. + * @param mode The UART mode to be set. + * + * @return None. + */ +static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode) +{ + switch (mode) { + default: + case UART_MODE_UART: + uart_ll_set_mode_normal(hw); + break; + case UART_MODE_RS485_COLLISION_DETECT: + uart_ll_set_mode_collision_detect(hw); + break; + case UART_MODE_RS485_APP_CTRL: + uart_ll_set_mode_rs485_app_ctrl(hw); + break; + case UART_MODE_RS485_HALF_DUPLEX: + uart_ll_set_mode_rs485_half_duplex(hw); + break; + case UART_MODE_IRDA: + uart_ll_set_mode_irda(hw); + break; + } +} + +/** + * @brief Get the UART AT cmd char configuration. + * + * @param hw Beginning address of the peripheral registers. + * @param cmd_char The Pointer to accept value of UART AT cmd char. + * @param char_num Pointer to accept the repeat number of UART AT cmd char. + * + * @return None. + */ +static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num) +{ + *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, data); + uart_ll_update(0); // TODO: IDF-5338 + *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, char_num); + uart_ll_update(0); // TODO: IDF-5338 +} + +/** + * @brief Get the UART wakeup threshold value. + * + * @param hw Beginning address of the peripheral registers. + * + * @return The UART wakeup threshold value. + */ +static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw) +{ + return hw->sleep_conf2.active_threshold + UART_LL_MIN_WAKEUP_THRESH; +} + +/** + * @brief Get the UART data bit configuration. + * + * @param hw Beginning address of the peripheral registers. + * @param data_bit The pointer to accept the UART data bit configuration. + * + * @return The bit mode. + */ +static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit) +{ + *data_bit = hw->conf0_sync.bit_num; +} + +/** + * @brief Check if the UART sending state machine is in the IDLE state. + * + * @param hw Beginning address of the peripheral registers. + * + * @return True if the state machine is in the IDLE state, otherwise false is returned. + */ +static inline bool uart_ll_is_tx_idle(uart_dev_t *hw) +{ + return ((hw->status.txfifo_cnt == 0) && (hw->fsm_status.st_utx_out == 0)); +} + +/** + * @brief Check if the UART rts flow control is enabled. + * + * @param hw Beginning address of the peripheral registers. + * + * @return True if hw rts flow control is enabled, otherwise false is returned. + */ +static inline bool uart_ll_is_hw_rts_en(uart_dev_t *hw) +{ + return hw->hwfc_conf_sync.rx_flow_en; +} + +/** + * @brief Check if the UART cts flow control is enabled. + * + * @param hw Beginning address of the peripheral registers. + * + * @return True if hw cts flow control is enabled, otherwise false is returned. + */ +static inline bool uart_ll_is_hw_cts_en(uart_dev_t *hw) +{ + return hw->conf0_sync.tx_flow_en; +} + +/** + * @brief Configure TX signal loop back to RX module, just for the testing purposes + * + * @param hw Beginning address of the peripheral registers. + * @param loop_back_en Set ture to enable the loop back function, else set it false. + * + * @return None + */ +static inline void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en) +{ + hw->conf0_sync.loopback = loop_back_en; +} + +static inline void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on) +{ + hw->swfc_conf0_sync.force_xon = 1; + uart_ll_update(0); // TODO: IDF-5338 + if(!always_on) { + hw->swfc_conf0_sync.force_xon = 0; + uart_ll_update(0); // TODO: IDF-5338 + } +} + +/** + * @brief Inverse the UART signal with the given mask. + * + * @param hw Beginning address of the peripheral registers. + * @param inv_mask The UART signal bitmap needs to be inversed. + * Use the ORred mask of `uart_signal_inv_t`; + * + * @return None. + */ +static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask) +{ + typeof(hw->conf0_sync) conf0_reg = hw->conf0_sync; + conf0_reg.irda_tx_inv = (inv_mask & UART_SIGNAL_IRDA_TX_INV) ? 1 : 0; + conf0_reg.irda_rx_inv = (inv_mask & UART_SIGNAL_IRDA_RX_INV) ? 1 : 0; + conf0_reg.rxd_inv = (inv_mask & UART_SIGNAL_RXD_INV) ? 1 : 0; + conf0_reg.txd_inv = (inv_mask & UART_SIGNAL_TXD_INV) ? 1 : 0; + hw->conf0_sync.val = conf0_reg.val; + uart_ll_update(0); // TODO: IDF-5338 + + typeof(hw->conf1) conf1_reg = hw->conf1; + conf1_reg.rts_inv = (inv_mask & UART_SIGNAL_RTS_INV) ? 1 : 0; + conf1_reg.dtr_inv = (inv_mask & UART_SIGNAL_DTR_INV) ? 1 : 0; + conf1_reg.cts_inv = (inv_mask & UART_SIGNAL_CTS_INV) ? 1 : 0; + conf1_reg.dsr_inv = (inv_mask & UART_SIGNAL_DSR_INV) ? 1 : 0; + hw->conf1.val = conf1_reg.val; +} + +/** + * @brief Configure the timeout value for receiver receiving a byte, and enable rx timeout function. + * + * @param hw Beginning address of the peripheral registers. + * @param tout_thrd The timeout value as UART bit time. The rx timeout function will be disabled if `tout_thrd == 0`. + * + * @return None. + */ +static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd) +{ + uint16_t tout_val = tout_thrd; + if(tout_thrd > 0) { + hw->tout_conf_sync.rx_tout_thrhd = tout_val; + uart_ll_update(0); // TODO: IDF-5338 + hw->tout_conf_sync.rx_tout_en = 1; + uart_ll_update(0); // TODO: IDF-5338 + } else { + hw->tout_conf_sync.rx_tout_en = 0; + uart_ll_update(0); // TODO: IDF-5338 + } +} + +/** + * @brief Get the timeout value for receiver receiving a byte. + * + * @param hw Beginning address of the peripheral registers. + * + * @return tout_thr The timeout threshold value. If timeout feature is disabled returns 0. + */ +static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw) +{ + uint16_t tout_thrd = 0; + if(hw->tout_conf_sync.rx_tout_en > 0) { + tout_thrd = hw->tout_conf_sync.rx_tout_thrhd; + } + return tout_thrd; +} + +/** + * @brief Get UART maximum timeout threshold. + * + * @param hw Beginning address of the peripheral registers. + * + * @return maximum timeout threshold. + */ +static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw) +{ + return UART_RX_TOUT_THRHD_V; +} + +/** + * @brief Configure the auto baudrate. + * + * @param hw Beginning address of the peripheral registers. + * @param enable Boolean marking whether the auto baudrate should be enabled or not. + */ +static inline void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable) +{ + hw->conf0_sync.autobaud_en = enable ? 1 : 0; + uart_ll_update(0); // TODO: IDF-5338 +} + +/** + * @brief Get the RXD edge count. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw) +{ + return hw->rxd_cnt.rxd_edge_cnt; +} + +/** + * @brief Get the positive pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw) +{ + return hw->pospulse.posedge_min_cnt; +} + +/** + * @brief Get the negative pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw) +{ + return hw->negpulse.negedge_min_cnt; +} + +/** + * @brief Get the high pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw) +{ + return hw->highpulse.highpulse_min_cnt; +} + +/** + * @brief Get the low pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw) +{ + return hw->lowpulse.lowpulse_min_cnt; +} + +/** + * @brief Force UART xoff. + * + * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). + * + * @return None. + */ +static inline void uart_ll_force_xoff(uart_port_t uart_num) +{ + REG_CLR_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_FORCE_XON); + uart_ll_update(0); // TODO: IDF-5338 + REG_SET_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_SW_FLOW_CON_EN | UART_FORCE_XOFF); + uart_ll_update(0); // TODO: IDF-5338 + // REG_SET_BIT(UART_ID_REG(uart_num), UART_UPDATE); +} + +/** + * @brief Force UART xon. + * + * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). + * + * @return None. + */ +static inline void uart_ll_force_xon(uart_port_t uart_num) +{ + REG_CLR_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_FORCE_XOFF); + uart_ll_update(0); // TODO: IDF-5338 + REG_SET_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_FORCE_XON); + uart_ll_update(0); // TODO: IDF-5338 + REG_CLR_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_SW_FLOW_CON_EN | UART_FORCE_XON); + uart_ll_update(0); // TODO: IDF-5338 + // REG_SET_BIT(UART_ID_REG(uart_num), UART_UPDATE); +} + +/** + * @brief Get UART finite-state machine status. + * + * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). + * + * @return UART module FSM status. + */ +static inline uint32_t uart_ll_get_fsm_status(uart_port_t uart_num) +{ + return REG_GET_FIELD(UART_FSM_STATUS_REG(uart_num), UART_ST_UTX_OUT); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/usb_phy_ll.h b/components/hal/esp32c6/include/hal/usb_phy_ll.h new file mode 100644 index 0000000000..312ff236cd --- /dev/null +++ b/components/hal/esp32c6/include/hal/usb_phy_ll.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc/usb_serial_jtag_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Configures the internal PHY for USB_Serial_JTAG + * + * @param hw Start address of the USB Serial_JTAG registers + */ +static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw) +{ + // USB_Serial_JTAG use internal PHY + hw->conf0.phy_sel = 0; + // Disable software control USB D+ D- pullup pulldown (Device FS: dp_pullup = 1) + hw->conf0.pad_pull_override = 0; + // Enable USB D+ pullup + hw->conf0.dp_pullup = 1; + // Enable USB pad function + hw->conf0.usb_pad_enable = 1; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32c6/include/hal/usb_serial_jtag_ll.h new file mode 100644 index 0000000000..06ade12c70 --- /dev/null +++ b/components/hal/esp32c6/include/hal/usb_serial_jtag_ll.h @@ -0,0 +1,164 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer of the USB-serial-jtag controller + +#pragma once +#include "soc/usb_serial_jtag_reg.h" +#include "soc/usb_serial_jtag_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +//The in and out endpoints are this long. +#define USB_SERIAL_JTAG_PACKET_SZ_BYTES 64 + +#define USB_SERIAL_JTAG_LL_INTR_MASK (0x7ffff) //All interrupt mask + +// Define USB_SERIAL_JTAG interrupts +// Note the hardware has more interrupts, but they're only useful for debugging +// the hardware. +typedef enum { + USB_SERIAL_JTAG_INTR_SOF = (1 << 1), + USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT = (1 << 2), + USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY = (1 << 3), + USB_SERIAL_JTAG_INTR_TOKEN_REC_IN_EP1 = (1 << 8), + USB_SERIAL_JTAG_INTR_BUS_RESET = (1 << 9), + USB_SERIAL_JTAG_INTR_EP1_ZERO_PAYLOAD = (1 << 10), +} usb_serial_jtag_ll_intr_t; + +/** + * @brief Enable the USB_SERIAL_JTAG interrupt based on the given mask. + * + * @param mask The bitmap of the interrupts need to be enabled. + * + * @return None + */ +static inline void usb_serial_jtag_ll_ena_intr_mask(uint32_t mask) +{ + USB_SERIAL_JTAG.int_ena.val |= mask; +} + +/** + * @brief Disable the USB_SERIAL_JTAG interrupt based on the given mask. + * + * @param mask The bitmap of the interrupts need to be disabled. + * + * @return None + */ +static inline void usb_serial_jtag_ll_disable_intr_mask(uint32_t mask) +{ + USB_SERIAL_JTAG.int_ena.val &= (~mask); +} + +/** + * @brief Get the USB_SERIAL_JTAG interrupt status. + * + * @return The USB_SERIAL_JTAG interrupt status. + */ +static inline uint32_t usb_serial_jtag_ll_get_intsts_mask(void) +{ + return USB_SERIAL_JTAG.int_st.val; +} + +/** + * @brief Clear the USB_SERIAL_JTAG interrupt status based on the given mask. + * + * @param mask The bitmap of the interrupts need to be cleared. + * + * @return None + */ +static inline void usb_serial_jtag_ll_clr_intsts_mask(uint32_t mask) +{ + USB_SERIAL_JTAG.int_clr.val = mask; +} + +/** + * @brief Get status of enabled interrupt. + * + * @return interrupt enable value + */ +static inline uint32_t usb_serial_jtag_ll_get_intr_ena_status(void) +{ + return USB_SERIAL_JTAG.int_ena.val; +} + +/** + * @brief Read the bytes from the USB_SERIAL_JTAG rxfifo. + * + * @param buf The data buffer. + * @param rd_len The data length needs to be read. + * + * @return amount of bytes read + */ +static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len) +{ + int i; + for (i = 0; i < (int)rd_len; i++) { + if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break; + buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte; + } + return i; +} + +/** + * @brief Write byte to the USB_SERIAL_JTAG txfifo. Only writes bytes as long / if there + * is room in the buffer. + * + * @param buf The data buffer. + * @param wr_len The data length needs to be writen. + * + * @return Amount of bytes actually written. May be less than wr_len. + */ +static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t wr_len) +{ + int i; + for (i = 0; i < (int)wr_len; i++) { + if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break; + USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i]; + } + return i; +} + +/** + * @brief Returns 1 if the USB_SERIAL_JTAG rxfifo has data available. + * + * @return 0 if no data available, 1 if data available + */ +static inline int usb_serial_jtag_ll_rxfifo_data_available(void) +{ + return USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail; +} + +/** + * @brief Returns 1 if the USB_SERIAL_JTAG txfifo has room. + * + * @return 0 if no data available, 1 if data available + */ +static inline int usb_serial_jtag_ll_txfifo_writable(void) +{ + return USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free; +} + +/** + * @brief Flushes the TX buffer, that is, make it available for the + * host to pick up. + * + * @note When fifo is full (with 64 byte), HW will flush the buffer automatically. + * It won't be executed if there is nothing in the fifo. + * + * @return na + */ +static inline void usb_serial_jtag_ll_txfifo_flush(void) +{ + USB_SERIAL_JTAG.ep1_conf.wr_done=1; +} + + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/rtc_cntl_hal.c b/components/hal/esp32c6/rtc_cntl_hal.c new file mode 100644 index 0000000000..ebcfb668f6 --- /dev/null +++ b/components/hal/esp32c6/rtc_cntl_hal.c @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The HAL layer for RTC CNTL (common part) + +#include "soc/soc_caps.h" +#include "soc/lldesc.h" +#include "hal/dma_types.h" +#include "hal/rtc_hal.h" +#include "hal/assert.h" +#include "esp_attr.h" + +#define RTC_CNTL_HAL_LINK_BUF_SIZE_MIN (SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE) /* The minimum size of dma link buffer */ + +typedef struct rtc_cntl_link_buf_conf { + uint32_t cfg[4]; /* 4 word for dma link buffer configuration */ +} rtc_cntl_link_buf_conf_t; + +void * rtc_cntl_hal_dma_link_init(void *elem, void *buff, int size, void *next) +{ + HAL_ASSERT(elem != NULL); + HAL_ASSERT(buff != NULL); + HAL_ASSERT(size >= RTC_CNTL_HAL_LINK_BUF_SIZE_MIN); + + lldesc_t *plink = (lldesc_t *)elem; + + plink->eof = next ? 0 : 1; + plink->owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA; + plink->size = size >> 4; /* in unit of 16 bytes */ + plink->length = size >> 4; + plink->buf = buff; + plink->offset = 0; + plink->sosf = 0; + STAILQ_NEXT(plink, qe) = next; + return (void *)plink; +} + +#if SOC_PM_SUPPORT_CPU_PD + +void rtc_cntl_hal_enable_cpu_retention(void *addr) +{ + // TODO: IDF-5718 has removed the retention feature +} + +void IRAM_ATTR rtc_cntl_hal_disable_cpu_retention(void *addr) +{ + // TODO: IDF-5718 has removed the retention feature +} + +#endif // SOC_PM_SUPPORT_CPU_PD diff --git a/components/hal/esp32h2/include/hal/aes_ll.h b/components/hal/esp32h2/include/hal/aes_ll.h index e18c44e58e..efa7928377 100644 --- a/components/hal/esp32h2/include/hal/aes_ll.h +++ b/components/hal/esp32h2/include/hal/aes_ll.h @@ -1,16 +1,8 @@ -// Copyright 2020-2021 Espressif Systems (Shanghai) CO LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -224,7 +216,7 @@ static inline void aes_ll_interrupt_enable(bool enable) */ static inline void aes_ll_interrupt_clear(void) { - REG_WRITE(AES_INT_CLR_REG, 1); + REG_WRITE(AES_INT_CLEAR_REG, 1); } diff --git a/components/hal/esp32h2/include/hal/i2c_ll.h b/components/hal/esp32h2/include/hal/i2c_ll.h index 7ef4b9547d..88668d2e35 100644 --- a/components/hal/esp32h2/include/hal/i2c_ll.h +++ b/components/hal/esp32h2/include/hal/i2c_ll.h @@ -8,6 +8,7 @@ #pragma once +#include "stdbool.h" #include "hal/misc.h" #include "soc/i2c_periph.h" #include "soc/soc_caps.h" @@ -16,15 +17,14 @@ #include "soc/rtc_cntl_reg.h" #include "soc/clk_tree_defs.h" #include "esp_rom_sys.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { #endif -#define I2C_LL_INTR_MASK (0x3fff) /*!< I2C all interrupt bitmap */ - /** - * @brief I2C hardware cmd register filed. + * @brief I2C hardware cmd register fields. */ typedef union { struct { @@ -39,35 +39,6 @@ typedef union { uint32_t val; } i2c_hw_cmd_t; -/** - * @brief I2C interrupt event - */ -typedef enum { - I2C_INTR_EVENT_ERR, - I2C_INTR_EVENT_ARBIT_LOST, /*!< I2C arbition lost event */ - I2C_INTR_EVENT_NACK, /*!< I2C NACK event */ - I2C_INTR_EVENT_TOUT, /*!< I2C time out event */ - I2C_INTR_EVENT_END_DET, /*!< I2C end detected event */ - I2C_INTR_EVENT_TRANS_DONE, /*!< I2C trans done event */ - I2C_INTR_EVENT_RXFIFO_FULL, /*!< I2C rxfifo full event */ - I2C_INTR_EVENT_TXFIFO_EMPTY, /*!< I2C txfifo empty event */ -} i2c_intr_event_t; - -/** - * @brief Data structure for calculating I2C bus timing. - */ -typedef struct { - uint16_t clkm_div; /*!< I2C core clock devider */ - uint16_t scl_low; /*!< I2C scl low period */ - uint16_t scl_high; /*!< I2C scl hight period */ - uint16_t scl_wait_high; /*!< I2C scl wait_high period */ - uint16_t sda_hold; /*!< I2C scl low period */ - uint16_t sda_sample; /*!< I2C sda sample time */ - uint16_t setup; /*!< I2C start and stop condition setup period */ - uint16_t hold; /*!< I2C start and stop condition hold period */ - uint16_t tout; /*!< I2C bus timeout period */ -} i2c_clk_cal_t; - // I2C operation mode command #define I2C_LL_CMD_RESTART 6 /*!ctr.conf_upgate = 1; @@ -146,7 +122,7 @@ static inline void i2c_ll_update(i2c_dev_t *hw) * * @return None */ -static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_clk_cal_t *bus_cfg) +static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_hal_clk_config_t *bus_cfg) { HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, bus_cfg->clkm_div - 1); /* According to the Technical Reference Manual, the following timings must be subtracted by 1. @@ -220,7 +196,8 @@ static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int hight_period, int lo * * @return None */ -static inline void i2c_ll_clr_intsts_mask(i2c_dev_t *hw, uint32_t mask) +__attribute__((always_inline)) +static inline void i2c_ll_clear_intr_mask(i2c_dev_t *hw, uint32_t mask) { hw->int_clr.val = mask; } @@ -246,6 +223,7 @@ static inline void i2c_ll_enable_intr_mask(i2c_dev_t *hw, uint32_t mask) * * @return None */ +__attribute__((always_inline)) static inline void i2c_ll_disable_intr_mask(i2c_dev_t *hw, uint32_t mask) { hw->int_ena.val &= (~mask); @@ -258,9 +236,10 @@ static inline void i2c_ll_disable_intr_mask(i2c_dev_t *hw, uint32_t mask) * * @return I2C interrupt status */ -static inline uint32_t i2c_ll_get_intsts_mask(i2c_dev_t *hw) +__attribute__((always_inline)) +static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status) { - return hw->int_status.val; + *intr_status = hw->int_status.val; } /** @@ -477,9 +456,10 @@ static inline bool i2c_ll_is_master_mode(i2c_dev_t *hw) * * @return RxFIFO readable length */ -static inline uint32_t i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw) +__attribute__((always_inline)) +static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length) { - return hw->sr.rx_fifo_cnt; + *length = hw->sr.rx_fifo_cnt; } /** @@ -489,9 +469,10 @@ static inline uint32_t i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw) * * @return TxFIFO writable length */ -static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw) +__attribute__((always_inline)) +static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length) { - return SOC_I2C_FIFO_LEN - hw->sr.tx_fifo_cnt; + *length = SOC_I2C_FIFO_LEN - hw->sr.tx_fifo_cnt; } /** @@ -501,9 +482,9 @@ static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw) * * @return The I2C timeout value */ -static inline uint32_t i2c_ll_get_tout(i2c_dev_t *hw) +static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout) { - return hw->timeout.time_out_value; + *timeout = hw->timeout.time_out_value; } /** @@ -572,7 +553,8 @@ static inline void i2c_ll_get_scl_timing(i2c_dev_t *hw, int *high_period, int *l * * @return None. */ -static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) +__attribute__((always_inline)) +static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len) { for (int i = 0; i< len; i++) { HAL_FORCE_MODIFY_U32_REG_FIELD(hw->fifo_data, data, ptr[i]); @@ -588,6 +570,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) * * @return None */ +__attribute__((always_inline)) static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) { for(int i = 0; i < len; i++) { @@ -624,155 +607,9 @@ static inline void i2c_ll_set_filter(i2c_dev_t *hw, uint8_t filter_num) * * @return The hardware filter configuration */ -static inline uint8_t i2c_ll_get_filter(i2c_dev_t *hw) +static inline void i2c_ll_get_filter(i2c_dev_t *hw, uint8_t *filter_conf) { - return hw->filter_cfg.scl_thres; -} - -/** - * @brief Enable I2C master TX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_enable_tx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = ~0; - hw->int_ena.val = I2C_LL_MASTER_TX_INT; -} - -/** - * @brief Enable I2C master RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_enable_rx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = ~0; - hw->int_ena.val = I2C_LL_MASTER_RX_INT; -} - -/** - * @brief Disable I2C master TX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_disable_tx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT); -} - -/** - * @brief Disable I2C master RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_MASTER_RX_INT); -} - -/** - * @brief Clear I2C master TX interrupt status register - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_clr_tx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = I2C_LL_MASTER_TX_INT; -} - -/** - * @brief Clear I2C master RX interrupt status register - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_clr_rx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = I2C_LL_MASTER_RX_INT; -} - -/** - * @brief - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_enable_tx_it(i2c_dev_t *hw) -{ - hw->int_ena.val |= I2C_LL_SLAVE_TX_INT; -} - -/** - * @brief Enable I2C slave RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_enable_rx_it(i2c_dev_t *hw) -{ - hw->int_ena.val |= I2C_LL_SLAVE_RX_INT; -} - -/** - * @brief Disable I2C slave TX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_disable_tx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_SLAVE_TX_INT); -} - -/** - * @brief Disable I2C slave RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT); -} - -/** - * @brief Clear I2C slave TX interrupt status register - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_clr_tx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = I2C_LL_SLAVE_TX_INT; -} - -/** - * @brief Clear I2C slave RX interrupt status register. - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_clr_rx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = I2C_LL_SLAVE_RX_INT; + *filter_conf = hw->filter_cfg.scl_thres; } /** @@ -800,9 +637,12 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw) static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw) { hw->scl_sp_conf.scl_rst_slv_num = 9; - hw->scl_sp_conf.scl_rst_slv_en = 0; - hw->ctr.conf_upgate = 1; hw->scl_sp_conf.scl_rst_slv_en = 1; + hw->ctr.conf_upgate = 1; + // hardward will clear scl_rst_slv_en after sending SCL pulses, + // and we should set conf_upgate bit to synchronize register value. + while (hw->scl_sp_conf.scl_rst_slv_en); + hw->ctr.conf_upgate = 1; } /** @@ -819,54 +659,6 @@ static inline void i2c_ll_set_source_clk(i2c_dev_t *hw, i2c_clock_source_t src_c hw->clk_conf.sclk_sel = (src_clk == I2C_CLK_SRC_RC_FAST) ? 1 : 0; } -/** - * @brief Get I2C master interrupt event - * - * @param hw Beginning address of the peripheral registers - * @param event Pointer to accept the interrupt event - * - * @return None - */ -static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) -{ - typeof(hw->int_status) int_sts = hw->int_status; - if (int_sts.arbitration_lost) { - *event = I2C_INTR_EVENT_ARBIT_LOST; - } else if (int_sts.nack) { - *event = I2C_INTR_EVENT_NACK; - } else if (int_sts.time_out) { - *event = I2C_INTR_EVENT_TOUT; - } else if (int_sts.end_detect) { - *event = I2C_INTR_EVENT_END_DET; - } else if (int_sts.trans_complete) { - *event = I2C_INTR_EVENT_TRANS_DONE; - } else { - *event = I2C_INTR_EVENT_ERR; - } -} - -/** - * @brief Get I2C slave interrupt event - * - * @param hw Beginning address of the peripheral registers - * @param event Pointer to accept the interrupt event - * - * @return None - */ -static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) -{ - typeof(hw->int_status) int_sts = hw->int_status; - if (int_sts.tx_fifo_wm) { - *event = I2C_INTR_EVENT_TXFIFO_EMPTY; - } else if (int_sts.trans_complete) { - *event = I2C_INTR_EVENT_TRANS_DONE; - } else if (int_sts.rx_fifo_wm) { - *event = I2C_INTR_EVENT_RXFIFO_FULL; - } else { - *event = I2C_INTR_EVENT_ERR; - } -} - /** * @brief Init I2C master * @@ -899,10 +691,64 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw) ctrl_reg.sda_force_out = 1; ctrl_reg.scl_force_out = 1; hw->ctr.val = ctrl_reg.val; - hw->ctr.slv_tx_auto_start_en = 1; hw->fifo_conf.fifo_addr_cfg_en = 0; } +/** + * @brief Set whether slave should auto start, or only start with start signal from master + * + * @param hw Beginning address of the peripheral registers + * @param slv_ex_auto_en 1 if slave auto start data transaction, otherwise, 0. + */ +static inline void i2c_ll_slave_tx_auto_start_en(i2c_dev_t *hw, bool slv_ex_auto_en) +{ + hw->ctr.slv_tx_auto_start_en = slv_ex_auto_en; +} + +/** + * @brief Get I2C interrupt status register address + */ +static inline volatile void *i2c_ll_get_interrupt_status_reg(i2c_dev_t *dev) +{ + return &dev->int_status; +} + +//////////////////////////////////////////Deprecated Functions////////////////////////////////////////////////////////// +/////////////////////////////The following functions are only used by the legacy driver///////////////////////////////// +/////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +// Get the I2C hardware instance +#define I2C_LL_GET_HW(i2c_num) (&I2C0) +// Get the I2C hardware FIFO address +#define I2C_LL_GET_FIFO_ADDR(i2c_num) (I2C_DATA_APB_REG(i2c_num)) +// I2C master TX interrupt bitmap +#define I2C_LL_MASTER_TX_INT (I2C_NACK_INT_ENA_M|I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M) +// I2C master RX interrupt bitmap +#define I2C_LL_MASTER_RX_INT (I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M) +// I2C slave TX interrupt bitmap +#define I2C_LL_SLAVE_TX_INT (I2C_TXFIFO_WM_INT_ENA_M) +// I2C slave RX interrupt bitmap +#define I2C_LL_SLAVE_RX_INT (I2C_RXFIFO_WM_INT_ENA_M | I2C_TRANS_COMPLETE_INT_ENA_M) +// I2C max timeout value +#define I2C_LL_MAX_TIMEOUT I2C_TIME_OUT_REG_V + +#define I2C_LL_INTR_MASK (0xffff) /*!< I2C all interrupt bitmap */ + +/** + * @brief I2C interrupt event + */ +typedef enum { + I2C_INTR_EVENT_ERR, + I2C_INTR_EVENT_ARBIT_LOST, /*!< I2C arbition lost event */ + I2C_INTR_EVENT_NACK, /*!< I2C NACK event */ + I2C_INTR_EVENT_TOUT, /*!< I2C time out event */ + I2C_INTR_EVENT_END_DET, /*!< I2C end detected event */ + I2C_INTR_EVENT_TRANS_DONE, /*!< I2C trans done event */ + I2C_INTR_EVENT_RXFIFO_FULL, /*!< I2C rxfifo full event */ + I2C_INTR_EVENT_TXFIFO_EMPTY, /*!< I2C txfifo empty event */ +} i2c_intr_event_t; + /** * @brief Configure I2C SCL timing * @@ -936,6 +782,156 @@ static inline void i2c_ll_get_scl_clk_timing(i2c_dev_t *hw, int *high_period, in *low_period = hw->scl_low_period.period; } +/** + * @brief Get I2C master interrupt event + * + * @param hw Beginning address of the peripheral registers + * @param event Pointer to accept the interrupt event + * + * @return None + */ +__attribute__((always_inline)) +static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) +{ + typeof(hw->int_status) int_sts = hw->int_status; + if (int_sts.arbitration_lost) { + *event = I2C_INTR_EVENT_ARBIT_LOST; + } else if (int_sts.nack) { + *event = I2C_INTR_EVENT_NACK; + } else if (int_sts.time_out) { + *event = I2C_INTR_EVENT_TOUT; + } else if (int_sts.end_detect) { + *event = I2C_INTR_EVENT_END_DET; + } else if (int_sts.trans_complete) { + *event = I2C_INTR_EVENT_TRANS_DONE; + } else { + *event = I2C_INTR_EVENT_ERR; + } +} + +/** + * @brief Get I2C slave interrupt event + * + * @param hw Beginning address of the peripheral registers + * @param event Pointer to accept the interrupt event + * + * @return None + */ +__attribute__((always_inline)) +static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) +{ + typeof(hw->int_status) int_sts = hw->int_status; + if (int_sts.tx_fifo_wm) { + *event = I2C_INTR_EVENT_TXFIFO_EMPTY; + } else if (int_sts.trans_complete) { + *event = I2C_INTR_EVENT_TRANS_DONE; + } else if (int_sts.rx_fifo_wm) { + *event = I2C_INTR_EVENT_RXFIFO_FULL; + } else { + *event = I2C_INTR_EVENT_ERR; + } +} + +/** + * @brief Enable I2C master TX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_enable_tx_it(i2c_dev_t *hw) +{ + hw->int_clr.val = UINT32_MAX; + hw->int_ena.val = I2C_LL_MASTER_TX_INT; +} + +/** + * @brief Enable I2C master RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_enable_rx_it(i2c_dev_t *hw) +{ + hw->int_clr.val = UINT32_MAX; + hw->int_ena.val = I2C_LL_MASTER_RX_INT; +} + +/** + * @brief Disable I2C master TX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_disable_tx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT); +} + +/** + * @brief Disable I2C master RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +__attribute__((always_inline)) +static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_MASTER_RX_INT); +} + +/** + * @brief + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_slave_enable_tx_it(i2c_dev_t *hw) +{ + hw->int_ena.val |= I2C_LL_SLAVE_TX_INT; +} + +/** + * @brief Enable I2C slave RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_slave_enable_rx_it(i2c_dev_t *hw) +{ + hw->int_ena.val |= I2C_LL_SLAVE_RX_INT; +} + +/** + * @brief Disable I2C slave TX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +__attribute__((always_inline)) +static inline void i2c_ll_slave_disable_tx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_SLAVE_TX_INT); +} + +/** + * @brief Disable I2C slave RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h2/include/hal/i2s_ll.h b/components/hal/esp32h2/include/hal/i2s_ll.h index edbafcc252..5a508057b4 100644 --- a/components/hal/esp32h2/include/hal/i2s_ll.h +++ b/components/hal/esp32h2/include/hal/i2s_ll.h @@ -15,6 +15,7 @@ #pragma once #include #include "hal/misc.h" +#include "hal/assert.h" #include "soc/i2s_periph.h" #include "soc/i2s_struct.h" #include "hal/i2s_types.h" @@ -24,12 +25,10 @@ extern "C" { #endif -#define I2S_LL_GET_HW(num) (&I2S0) +#define I2S_LL_GET_HW(num) (((num) == 0)? (&I2S0) : NULL) #define I2S_LL_TDM_CH_MASK (0xffff) #define I2S_LL_PDM_BCK_FACTOR (64) -// [clk_tree] TODO: replace the following switch table by clk_tree API -#define I2S_LL_BASE_CLK (96*1000000) #define I2S_LL_MCLK_DIVIDER_BIT_WIDTH (9) #define I2S_LL_MCLK_DIVIDER_MAX ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1) @@ -195,18 +194,40 @@ static inline void i2s_ll_rx_reset_fifo(i2s_dev_t *hw) */ static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src) { - hw->tx_clkm_conf.tx_clk_sel = 2; + switch (src) + { + case I2S_CLK_SRC_XTAL: + hw->tx_clkm_conf.tx_clk_sel = 0; + break; + case I2S_CLK_SRC_PLL_96M: + hw->tx_clkm_conf.tx_clk_sel = 2; + break; + default: + HAL_ASSERT(false && "unsupported clock source"); + break; + } } /** * @brief Set RX source clock * * @param hw Peripheral I2S hardware instance address. - * @param src I2S source clock, ESP32-H2 only support `I2S_CLK_SRC_PLL_96M` for now + * @param src I2S source clock */ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src) { - hw->rx_clkm_conf.rx_clk_sel = 2; + switch (src) + { + case I2S_CLK_SRC_XTAL: + hw->rx_clkm_conf.rx_clk_sel = 0; + break; + case I2S_CLK_SRC_PLL_96M: + hw->rx_clkm_conf.rx_clk_sel = 2; + break; + default: + HAL_ASSERT(false && "unsupported clock source"); + break; + } } /** @@ -258,7 +279,7 @@ static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t * @brief Configure I2S TX module clock divider * * @param hw Peripheral I2S hardware instance address. - * @param sclk system clock, 0 means use apll + * @param sclk system clock * @param mclk module clock * @param mclk_div integer part of the division from sclk to mclk */ diff --git a/components/hal/esp32h2/include/hal/rmt_ll.h b/components/hal/esp32h2/include/hal/rmt_ll.h index ce76e09e73..826227ffa9 100644 --- a/components/hal/esp32h2/include/hal/rmt_ll.h +++ b/components/hal/esp32h2/include/hal/rmt_ll.h @@ -90,7 +90,6 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, // Formula: rmt_sclk = module_clock_src / (1 + div_num + div_a / div_b) (void)channel; // the source clock is set for all channels HAL_ASSERT(divider_integral >= 1); - dev->sys_conf.sclk_active = 0; HAL_FORCE_MODIFY_U32_REG_FIELD(dev->sys_conf, sclk_div_num, divider_integral - 1); dev->sys_conf.sclk_div_a = divider_numerator; dev->sys_conf.sclk_div_b = divider_denominator; @@ -98,9 +97,6 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, case RMT_CLK_SRC_AHB: dev->sys_conf.sclk_sel = 1; break; - case RMT_CLK_SRC_RC_FAST: - dev->sys_conf.sclk_sel = 2; - break; case RMT_CLK_SRC_XTAL: dev->sys_conf.sclk_sel = 3; break; @@ -108,7 +104,17 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, HAL_ASSERT(false && "unsupported RMT clock source"); break; } - dev->sys_conf.sclk_active = 1; +} + +/** + * @brief Enable RMT peripheral source clock + * + * @param dev Peripheral instance address + * @param en True to enable, False to disable + */ +static inline void rmt_ll_enable_group_clock(rmt_dev_t *dev, bool en) +{ + dev->sys_conf.sclk_active = en; } ////////////////////////////////////////TX Channel Specific///////////////////////////////////////////////////////////// @@ -684,48 +690,57 @@ static inline uint32_t rmt_ll_rx_get_interrupt_status(rmt_dev_t *dev, uint32_t c /////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_status_word(rmt_dev_t *dev, uint32_t channel) { return dev->tx_status[channel].val; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_status_word(rmt_dev_t *dev, uint32_t channel) { return dev->rx_status[channel].val; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->tx_conf[channel], div_cnt); return div == 0 ? 256 : div; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->rx_conf[channel].conf0, div_cnt); return div == 0 ? 256 : div; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel) { return dev->rx_conf[channel].conf0.idle_thres; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) { return dev->tx_conf[channel].mem_size; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) { return dev->rx_conf[channel].conf0.mem_size; } +__attribute__((always_inline)) static inline bool rmt_ll_tx_is_loop_enabled(rmt_dev_t *dev, uint32_t channel) { return dev->tx_conf[channel].tx_conti_mode; } +__attribute__((always_inline)) static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel) { rmt_clock_source_t clk_src = RMT_CLK_SRC_AHB; @@ -733,9 +748,6 @@ static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint case 1: clk_src = RMT_CLK_SRC_AHB; break; - case 2: - clk_src = RMT_CLK_SRC_RC_FAST; - break; case 3: clk_src = RMT_CLK_SRC_XTAL; break; @@ -743,11 +755,13 @@ static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint return clk_src; } +__attribute__((always_inline)) static inline bool rmt_ll_tx_is_idle_enabled(rmt_dev_t *dev, uint32_t channel) { return dev->tx_conf[channel].idle_out_en; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel) { return dev->tx_conf[channel].idle_out_lv; @@ -761,46 +775,55 @@ static inline bool rmt_ll_is_mem_powered_down(rmt_dev_t *dev) return (dev->sys_conf.mem_force_pd) || !(dev->sys_conf.mem_force_pu); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_mem_owner(rmt_dev_t *dev, uint32_t channel) { return dev->rx_conf[channel].conf1.mem_owner; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_limit(rmt_dev_t *dev, uint32_t channel) { return dev->rx_lim[channel].rx_lim; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev) { return dev->int_st.val & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 2) & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_err_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 4) & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_err_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 6) & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 8) & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_thres_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 10) & 0x03; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_loop_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 12) & 0x03; diff --git a/components/hal/esp32h2/include/hal/rtc_cntl_ll.h b/components/hal/esp32h2/include/hal/rtc_cntl_ll.h index bff6c79390..750bc13333 100644 --- a/components/hal/esp32h2/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32h2/include/hal/rtc_cntl_ll.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -57,6 +49,16 @@ static inline void rtc_cntl_ll_disable_cpu_retention(void) // ESP32H2-TODO: IDF-3383 } +static inline void rtc_cntl_ll_reset_system(void) +{ + REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); +} + +static inline void rtc_cntl_ll_reset_cpu(int cpu_no) +{ + REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h2/include/hal/spi_ll.h b/components/hal/esp32h2/include/hal/spi_ll.h index 8c7cc0bec2..2881407dd9 100644 --- a/components/hal/esp32h2/include/hal/spi_ll.h +++ b/components/hal/esp32h2/include/hal/spi_ll.h @@ -74,6 +74,21 @@ typedef enum { } spi_ll_trans_len_cond_t; FLAG_ATTR(spi_ll_trans_len_cond_t) +// SPI base command in esp32h2 +typedef enum { + /* Slave HD Only */ + SPI_LL_BASE_CMD_HD_WRBUF = 0x01, + SPI_LL_BASE_CMD_HD_RDBUF = 0x02, + SPI_LL_BASE_CMD_HD_WRDMA = 0x03, + SPI_LL_BASE_CMD_HD_RDDMA = 0x04, + SPI_LL_BASE_CMD_HD_SEG_END = 0x05, + SPI_LL_BASE_CMD_HD_EN_QPI = 0x06, + SPI_LL_BASE_CMD_HD_WR_END = 0x07, + SPI_LL_BASE_CMD_HD_INT0 = 0x08, + SPI_LL_BASE_CMD_HD_INT1 = 0x09, + SPI_LL_BASE_CMD_HD_INT2 = 0x0A, +} spi_ll_base_command_t; + /*------------------------------------------------------------------------------ * Control *----------------------------------------------------------------------------*/ @@ -1074,6 +1089,93 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) #undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK +/** + * Get the base spi command in esp32h2 + * + * @param cmd_t Command value + */ +static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) +{ + uint8_t cmd_base = 0x00; + switch (cmd_t) + { + case SPI_CMD_HD_WRBUF: + cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; + break; + case SPI_CMD_HD_RDBUF: + cmd_base = SPI_LL_BASE_CMD_HD_RDBUF; + break; + case SPI_CMD_HD_WRDMA: + cmd_base = SPI_LL_BASE_CMD_HD_WRDMA; + break; + case SPI_CMD_HD_RDDMA: + cmd_base = SPI_LL_BASE_CMD_HD_RDDMA; + break; + case SPI_CMD_HD_SEG_END: + cmd_base = SPI_LL_BASE_CMD_HD_SEG_END; + break; + case SPI_CMD_HD_EN_QPI: + cmd_base = SPI_LL_BASE_CMD_HD_EN_QPI; + break; + case SPI_CMD_HD_WR_END: + cmd_base = SPI_LL_BASE_CMD_HD_WR_END; + break; + case SPI_CMD_HD_INT0: + cmd_base = SPI_LL_BASE_CMD_HD_INT0; + break; + case SPI_CMD_HD_INT1: + cmd_base = SPI_LL_BASE_CMD_HD_INT1; + break; + case SPI_CMD_HD_INT2: + cmd_base = SPI_LL_BASE_CMD_HD_INT2; + break; + default: + HAL_ASSERT(cmd_base); + } + return cmd_base; +} + +/** + * Get the spi communication command + * + * @param cmd_t Base command value + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode) +{ + uint8_t cmd_base = spi_ll_get_slave_hd_base_command(cmd_t); + uint8_t cmd_mod = 0x00; //CMD:1-bit, ADDR:1-bit, DATA:1-bit + + if (line_mode.data_lines == 2) { + if (line_mode.addr_lines == 2) { + cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit + } else { + cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit + } + } else if (line_mode.data_lines == 4) { + if (line_mode.addr_lines == 4) { + cmd_mod = 0xA0; //CMD:1-bit, ADDR:4-bit, DATA:4-bit + } else { + cmd_mod = 0x20; //CMD:1-bit, ADDR:1-bit, DATA:4-bit + } + } + if (cmd_base == SPI_LL_BASE_CMD_HD_SEG_END || cmd_base == SPI_LL_BASE_CMD_HD_EN_QPI) { + cmd_mod = 0x00; + } + + return cmd_base | cmd_mod; +} + +/** + * Get the dummy bits + * + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode) +{ + return 8; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h2/include/hal/timer_ll.h b/components/hal/esp32h2/include/hal/timer_ll.h index ef315f40b3..b0fe1c7b6a 100644 --- a/components/hal/esp32h2/include/hal/timer_ll.h +++ b/components/hal/esp32h2/include/hal/timer_ll.h @@ -44,6 +44,19 @@ static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num, } } +/** + * @brief Enable Timer Group (GPTimer) module clock + * + * @param hw Timer Group register base address + * @param timer_num Timer index in the group + * @param en true to enable, false to disable + */ +static inline void timer_ll_enable_clock(timg_dev_t *hw, uint32_t timer_num, bool en) +{ + (void)timer_num; // only one timer in the group + hw->regclk.timer_clk_is_active = en; +} + /** * @brief Enable alarm event * @@ -115,6 +128,22 @@ static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, b hw->hw_timer[timer_num].config.tx_en = en; } +/** + * @brief Trigger software capture event + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + */ +__attribute__((always_inline)) +static inline void timer_ll_trigger_soft_capture(timg_dev_t *hw, uint32_t timer_num) +{ + hw->hw_timer[timer_num].update.tx_update = 1; + // Timer register is in a different clock domain from Timer hardware logic + // We need to wait for the update to take effect before fetching the count value + while (hw->hw_timer[timer_num].update.tx_update) { + } +} + /** * @brief Get counter value * @@ -126,11 +155,6 @@ static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, b __attribute__((always_inline)) static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer_num) { - hw->hw_timer[timer_num].update.tx_update = 1; - // Timer register is in a different clock domain from Timer hardware logic - // We need to wait for the update to take effect before fetching the count value - while (hw->hw_timer[timer_num].update.tx_update) { - } return ((uint64_t) hw->hw_timer[timer_num].hi.tx_hi << 32) | (hw->hw_timer[timer_num].lo.tx_lo); } diff --git a/components/hal/esp32h2/include/hal/uart_ll.h b/components/hal/esp32h2/include/hal/uart_ll.h index 3e9e15f983..d0eeca30a6 100644 --- a/components/hal/esp32h2/include/hal/uart_ll.h +++ b/components/hal/esp32h2/include/hal/uart_ll.h @@ -144,38 +144,18 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk) } } -/** - * @brief Get the UART source clock frequency. - * - * @param hw Beginning address of the peripheral registers. - * - * @return Current source clock frequency - */ -static inline uint32_t uart_ll_get_sclk_freq(uart_dev_t *hw) -{ - switch (hw->clk_conf.sclk_sel) { - default: - case 1: - return APB_CLK_FREQ; - case 2: - return RTC_CLK_FREQ; - case 3: - return XTAL_CLK_FREQ; - } -} - /** * @brief Configure the baud-rate. * * @param hw Beginning address of the peripheral registers. * @param baud The baud rate to be set. + * @param sclk_freq Frequency of the clock source of UART, in Hz. * * @return None */ -static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud) +static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { #define DIV_UP(a, b) (((a) + (b) - 1) / (b)) - uint32_t sclk_freq = uart_ll_get_sclk_freq(hw); const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits int sclk_div = DIV_UP(sclk_freq, max_div * baud); @@ -192,12 +172,12 @@ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud) * @brief Get the current baud-rate. * * @param hw Beginning address of the peripheral registers. + * @param sclk_freq Frequency of the clock source of UART, in Hz. * * @return The current baudrate */ -static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw) +static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq) { - uint32_t sclk_freq = uart_ll_get_sclk_freq(hw); typeof(hw->clk_div) div_reg = hw->clk_div; return ((sclk_freq << 4)) / (((div_reg.div_int << 4) | div_reg.div_frag) * (HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1)); } diff --git a/components/hal/esp32h2/include/hal/usb_phy_ll.h b/components/hal/esp32h2/include/hal/usb_phy_ll.h new file mode 100644 index 0000000000..40d4cd1800 --- /dev/null +++ b/components/hal/esp32h2/include/hal/usb_phy_ll.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc/usb_serial_jtag_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Configures the internal PHY for USB_Serial_JTAG + * + * @param hw Start address of the USB Serial_JTAG registers + */ +static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw) +{ + // USB_Serial_JTAG use internal PHY + hw->conf0.phy_sel = 0; + // Disable software control USB D+ D- pullup pulldown (Device FS: dp_pullup = 1) + hw->conf0.pad_pull_override = 0; + // Enable USB D+ pullup + hw->conf0.dp_pullup = 1; + // Enable USB pad function + hw->conf0.usb_pad_enable = 1; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/rev1/hal/gpio_ll.h b/components/hal/esp32h2/include/rev1/hal/gpio_ll.h index 64274e845c..bb7376aae5 100644 --- a/components/hal/esp32h2/include/rev1/hal/gpio_ll.h +++ b/components/hal/esp32h2/include/rev1/hal/gpio_ll.h @@ -51,6 +51,12 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) { + // The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value + // USB DP pin is default to PU enabled + if (gpio_num == USB_DP_GPIO_NUM) { + SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE); + CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP); + } REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); } diff --git a/components/hal/esp32h2/include/rev2/hal/gpio_ll.h b/components/hal/esp32h2/include/rev2/hal/gpio_ll.h index f414512cb4..7975f502a2 100644 --- a/components/hal/esp32h2/include/rev2/hal/gpio_ll.h +++ b/components/hal/esp32h2/include/rev2/hal/gpio_ll.h @@ -51,6 +51,12 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) { + // The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value + // USB DP pin is default to PU enabled + if (gpio_num == USB_DP_GPIO_NUM) { + SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE); + CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP); + } REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); } diff --git a/components/hal/esp32s2/include/hal/aes_ll.h b/components/hal/esp32s2/include/hal/aes_ll.h index 653253d06d..1caa406bfe 100644 --- a/components/hal/esp32s2/include/hal/aes_ll.h +++ b/components/hal/esp32s2/include/hal/aes_ll.h @@ -1,16 +1,8 @@ -// Copyright 2020-2021 Espressif Systems (Shanghai) CO LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -235,7 +227,7 @@ static inline void aes_ll_interrupt_enable(bool enable) */ static inline void aes_ll_interrupt_clear(void) { - REG_WRITE(AES_INT_CLR_REG, 1); + REG_WRITE(AES_INT_CLEAR_REG, 1); } /** diff --git a/components/hal/esp32s2/include/hal/gpio_ll.h b/components/hal/esp32s2/include/hal/gpio_ll.h index dbae67ea86..75b7c4b0b4 100644 --- a/components/hal/esp32s2/include/hal/gpio_ll.h +++ b/components/hal/esp32s2/include/hal/gpio_ll.h @@ -14,6 +14,7 @@ #pragma once +#include #include "soc/soc.h" #include "soc/gpio_periph.h" #include "soc/rtc_cntl_reg.h" @@ -49,9 +50,10 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) { - REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); + REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU); } /** @@ -71,9 +73,10 @@ static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) { - REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); + REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD); } /** @@ -170,9 +173,10 @@ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); + PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); } /** @@ -192,6 +196,7 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_output_disable(gpio_dev_t *hw, uint32_t gpio_num) { if (gpio_num < 32) { @@ -242,6 +247,18 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num) hw->pin[gpio_num].pad_driver = 1; } +/** + * @brief Select a function for the pin in the IOMUX + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + * @param func Function to assign to the pin + */ +static inline __attribute__((always_inline)) void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func) +{ + PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func); +} + /** * @brief GPIO set output level * @@ -341,6 +358,7 @@ static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu */ static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw) { + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); } @@ -351,7 +369,22 @@ static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw) */ static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw) { - SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD); + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); +} + +/** + * @brief Get deep sleep hold status + * + * @param hw Peripheral GPIO hardware instance address. + * + * @return + * - true deep sleep hold is enabled + * - false deep sleep hold is disabled + */ +__attribute__((always_inline)) +static inline bool gpio_ll_deep_sleep_hold_is_en(gpio_dev_t *hw) +{ + return !GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD) && GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); } /** @@ -376,6 +409,24 @@ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num) CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); } +/** + * @brief Get digital gpio pad hold status. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + * + * @note caller must ensure that gpio_num is a digital io pad + * + * @return + * - true digital gpio pad is held + * - false digital gpio pad is unheld + */ +__attribute__((always_inline)) +static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num) +{ + return GET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, BIT(gpio_num - 21)); +} + /** * @brief Set pad input to a peripheral signal through the IOMUX. * @@ -417,7 +468,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, } /** - * @brief Force hold digital and rtc gpio pad. + * @brief Force hold digital gpio pad. * @note GPIO force hold, whether the chip in sleep mode or wakeup mode. */ static inline void gpio_ll_force_hold_all(void) @@ -427,7 +478,7 @@ static inline void gpio_ll_force_hold_all(void) } /** - * @brief Force unhold digital and rtc gpio pad. + * @brief Force unhold digital gpio pad. * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode. */ static inline void gpio_ll_force_unhold_all(void) diff --git a/components/hal/esp32s2/include/hal/i2c_ll.h b/components/hal/esp32s2/include/hal/i2c_ll.h index 94f99116ad..19dd073f65 100644 --- a/components/hal/esp32s2/include/hal/i2c_ll.h +++ b/components/hal/esp32s2/include/hal/i2c_ll.h @@ -7,16 +7,18 @@ // The LL layer for I2C register operations #pragma once +#include #include "soc/i2c_periph.h" #include "soc/i2c_struct.h" #include "soc/clk_tree_defs.h" #include "hal/i2c_types.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { #endif -#define I2C_LL_INTR_MASK (0x1ffff) /*!< I2C all interrupt bitmap */ + /** * @brief I2C hardware cmd register fields. @@ -34,34 +36,6 @@ typedef union { uint32_t val; } i2c_hw_cmd_t; -/** - * @brief I2C interrupt event - */ -typedef enum { - I2C_INTR_EVENT_ERR, - I2C_INTR_EVENT_ARBIT_LOST, /*!< I2C arbition lost event */ - I2C_INTR_EVENT_NACK, /*!< I2C NACK event */ - I2C_INTR_EVENT_TOUT, /*!< I2C time out event */ - I2C_INTR_EVENT_END_DET, /*!< I2C end detected event */ - I2C_INTR_EVENT_TRANS_DONE, /*!< I2C trans done event */ - I2C_INTR_EVENT_RXFIFO_FULL, /*!< I2C rxfifo full event */ - I2C_INTR_EVENT_TXFIFO_EMPTY, /*!< I2C txfifo empty event */ -} i2c_intr_event_t; - -/** - * @brief Data structure for calculating I2C bus timing. - */ -typedef struct { - uint16_t scl_low; /*!< I2C scl low period */ - uint16_t scl_high; /*!< I2C scl hight period */ - uint16_t scl_wait_high; /*!< I2C scl wait_high period */ - uint16_t sda_hold; /*!< I2C scl low period */ - uint16_t sda_sample; /*!< I2C sda sample time */ - uint16_t setup; /*!< I2C start and stop condition setup period */ - uint16_t hold; /*!< I2C start and stop condition hold period */ - uint16_t tout; /*!< I2C bus timeout period */ -} i2c_clk_cal_t; - // I2C operation mode command #define I2C_LL_CMD_RESTART 0 /*!scl_low_period.period = bus_cfg->scl_low - 1; @@ -185,7 +165,8 @@ static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int hight_period, int lo * * @return None */ -static inline void i2c_ll_clr_intsts_mask(i2c_dev_t *hw, uint32_t mask) +__attribute__((always_inline)) +static inline void i2c_ll_clear_intr_mask(i2c_dev_t *hw, uint32_t mask) { hw->int_clr.val = mask; } @@ -211,6 +192,7 @@ static inline void i2c_ll_enable_intr_mask(i2c_dev_t *hw, uint32_t mask) * * @return None */ +__attribute__((always_inline)) static inline void i2c_ll_disable_intr_mask(i2c_dev_t *hw, uint32_t mask) { hw->int_ena.val &= (~mask); @@ -223,9 +205,10 @@ static inline void i2c_ll_disable_intr_mask(i2c_dev_t *hw, uint32_t mask) * * @return I2C interrupt status */ -static inline uint32_t i2c_ll_get_intsts_mask(i2c_dev_t *hw) +__attribute__((always_inline)) +static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status) { - return hw->int_status.val; + *intr_status = hw->int_status.val; } /** @@ -443,9 +426,10 @@ static inline bool i2c_ll_is_master_mode(i2c_dev_t *hw) * * @return RxFIFO readable length */ -static inline uint32_t i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw) +__attribute__((always_inline)) +static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length) { - return hw->status_reg.rx_fifo_cnt; + *length = hw->status_reg.rx_fifo_cnt; } /** @@ -455,9 +439,10 @@ static inline uint32_t i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw) * * @return TxFIFO writable length */ -static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw) +__attribute__((always_inline)) +static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length) { - return SOC_I2C_FIFO_LEN - hw->status_reg.tx_fifo_cnt; + *length = SOC_I2C_FIFO_LEN - hw->status_reg.tx_fifo_cnt; } /** @@ -467,9 +452,9 @@ static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw) * * @return The I2C timeout value */ -static inline uint32_t i2c_ll_get_tout(i2c_dev_t *hw) +static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout) { - return hw->timeout.tout; + *timeout = hw->timeout.tout; } /** @@ -538,7 +523,8 @@ static inline void i2c_ll_get_scl_timing(i2c_dev_t *hw, int *high_period, int *l * * @return None. */ -static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) +__attribute__((always_inline)) +static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len) { uint32_t fifo_addr = (hw == &I2C0) ? 0x6001301c : 0x6002701c; for(int i = 0; i < len; i++) { @@ -555,6 +541,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) * * @return None */ +__attribute__((always_inline)) static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) { uint32_t fifo_addr = (hw == &I2C0) ? 0x6001301c : 0x6002701c; @@ -592,155 +579,9 @@ static inline void i2c_ll_set_filter(i2c_dev_t *hw, uint8_t filter_num) * * @return The hardware filter configuration */ -static inline uint8_t i2c_ll_get_filter(i2c_dev_t *hw) +static inline void i2c_ll_get_filter(i2c_dev_t *hw, uint8_t *filter_conf) { - return hw->sda_filter_cfg.thres; -} - -/** - * @brief Enable I2C master TX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_enable_tx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = ~0; - hw->int_ena.val = I2C_LL_MASTER_TX_INT; -} - -/** - * @brief Enable I2C master RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_enable_rx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = ~0; - hw->int_ena.val = I2C_LL_MASTER_RX_INT; -} - -/** - * @brief Disable I2C master TX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_disable_tx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT); -} - -/** - * @brief Disable I2C master RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_MASTER_RX_INT); -} - -/** - * @brief Clear I2C master TX interrupt status register - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_clr_tx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = I2C_LL_MASTER_TX_INT; -} - -/** - * @brief Clear I2C master RX interrupt status register - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_clr_rx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = I2C_LL_MASTER_RX_INT; -} - -/** - * @brief Enable I2C slave TX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_enable_tx_it(i2c_dev_t *hw) -{ - hw->int_ena.val |= I2C_LL_SLAVE_TX_INT; -} - -/** - * @brief Enable I2C slave RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_enable_rx_it(i2c_dev_t *hw) -{ - hw->int_ena.val |= I2C_LL_SLAVE_RX_INT; -} - -/** - * @brief Disable I2C slave TX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_disable_tx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_SLAVE_TX_INT); -} - -/** - * @brief Disable I2C slave RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT); -} - -/** - * @brief Clear I2C slave TX interrupt status register - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_clr_tx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = I2C_LL_SLAVE_TX_INT; -} - -/** - * @brief Clear I2C slave RX interrupt status register. - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_clr_rx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = I2C_LL_SLAVE_RX_INT; + *filter_conf = hw->sda_filter_cfg.thres; } /** @@ -786,53 +627,6 @@ static inline void i2c_ll_set_source_clk(i2c_dev_t *hw, i2c_clock_source_t src_c hw->ctr.ref_always_on = (src_clk == I2C_CLK_SRC_REF_TICK) ? 0 : 1; } -/** - * @brief Get I2C master interrupt event - * - * @param hw Beginning address of the peripheral registers - * @param event Pointer to accept the interrupt event - * - * @return None - */ -static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) -{ - typeof(hw->int_status) int_sts = hw->int_status; - if (int_sts.arbitration_lost) { - *event = I2C_INTR_EVENT_ARBIT_LOST; - } else if (int_sts.nack) { - *event = I2C_INTR_EVENT_NACK; - } else if (int_sts.time_out) { - *event = I2C_INTR_EVENT_TOUT; - } else if (int_sts.end_detect) { - *event = I2C_INTR_EVENT_END_DET; - } else if (int_sts.trans_complete) { - *event = I2C_INTR_EVENT_TRANS_DONE; - } else { - *event = I2C_INTR_EVENT_ERR; - } -} - -/** - * @brief Get I2C slave interrupt event - * - * @param hw Beginning address of the peripheral registers - * @param event Pointer to accept the interrupt event - * - * @return None - */ -static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) -{ - typeof(hw->int_status) int_sts = hw->int_status; - if (int_sts.tx_fifo_wm) { - *event = I2C_INTR_EVENT_TXFIFO_EMPTY; - } else if (int_sts.trans_complete) { - *event = I2C_INTR_EVENT_TRANS_DONE; - } else if (int_sts.rx_fifo_wm) { - *event = I2C_INTR_EVENT_RXFIFO_FULL; - } else { - *event = I2C_INTR_EVENT_ERR; - } -} /** * @brief Init I2C master @@ -893,11 +687,67 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw) * * @return None */ +__attribute__((always_inline)) static inline void i2c_ll_update(i2c_dev_t *hw) { ;// ESP32S2 do not support } +/** + * @brief Set whether slave should auto start, or only start with start signal from master + * + * @param hw Beginning address of the peripheral registers + * @param slv_ex_auto_en 1 if slave auto start data transaction, otherwise, 0. + */ +static inline void i2c_ll_slave_tx_auto_start_en(i2c_dev_t *hw, bool slv_ex_auto_en) +{ + ;// ESP32-S2 do not support +} + +/** + * @brief Get I2C interrupt status register address + */ +static inline volatile void *i2c_ll_get_interrupt_status_reg(i2c_dev_t *dev) +{ + return &dev->int_status; +} + +//////////////////////////////////////////Deprecated Functions////////////////////////////////////////////////////////// +/////////////////////////////The following functions are only used by the legacy driver///////////////////////////////// +/////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +// Get the I2C hardware instance +#define I2C_LL_GET_HW(i2c_num) (((i2c_num) == 0) ? &I2C0 : &I2C1) +// Get the I2C hardware FIFO address +#define I2C_LL_GET_FIFO_ADDR(i2c_num) (I2C_DATA_APB_REG(i2c_num)) +// I2C master TX interrupt bitmap +#define I2C_LL_MASTER_TX_INT (I2C_NACK_INT_ENA_M|I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M) +// I2C master RX interrupt bitmap +#define I2C_LL_MASTER_RX_INT (I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M) +// I2C slave TX interrupt bitmap +#define I2C_LL_SLAVE_TX_INT (I2C_TXFIFO_WM_INT_ENA_M) +// I2C slave RX interrupt bitmap +#define I2C_LL_SLAVE_RX_INT (I2C_RXFIFO_WM_INT_ENA_M | I2C_TRANS_COMPLETE_INT_ENA_M) +// I2C max timeout value +#define I2C_LL_MAX_TIMEOUT I2C_TIME_OUT_REG_V + +#define I2C_LL_INTR_MASK (0x1ffff) /*!< I2C all interrupt bitmap */ + +/** + * @brief I2C interrupt event + */ +typedef enum { + I2C_INTR_EVENT_ERR, + I2C_INTR_EVENT_ARBIT_LOST, /*!< I2C arbition lost event */ + I2C_INTR_EVENT_NACK, /*!< I2C NACK event */ + I2C_INTR_EVENT_TOUT, /*!< I2C time out event */ + I2C_INTR_EVENT_END_DET, /*!< I2C end detected event */ + I2C_INTR_EVENT_TRANS_DONE, /*!< I2C trans done event */ + I2C_INTR_EVENT_RXFIFO_FULL, /*!< I2C rxfifo full event */ + I2C_INTR_EVENT_TXFIFO_EMPTY, /*!< I2C txfifo empty event */ +} i2c_intr_event_t; + /** * @brief Configure I2C SCL timing * @@ -931,6 +781,157 @@ static inline void i2c_ll_get_scl_clk_timing(i2c_dev_t *hw, int *high_period, in *low_period = hw->scl_low_period.period; } +/** + * @brief Get I2C master interrupt event + * + * @param hw Beginning address of the peripheral registers + * @param event Pointer to accept the interrupt event + * + * @return None + */ +__attribute__((always_inline)) +static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) +{ + typeof(hw->int_status) int_sts = hw->int_status; + if (int_sts.arbitration_lost) { + *event = I2C_INTR_EVENT_ARBIT_LOST; + } else if (int_sts.nack) { + *event = I2C_INTR_EVENT_NACK; + } else if (int_sts.time_out) { + *event = I2C_INTR_EVENT_TOUT; + } else if (int_sts.end_detect) { + *event = I2C_INTR_EVENT_END_DET; + } else if (int_sts.trans_complete) { + *event = I2C_INTR_EVENT_TRANS_DONE; + } else { + *event = I2C_INTR_EVENT_ERR; + } +} + +/** + * @brief Get I2C slave interrupt event + * + * @param hw Beginning address of the peripheral registers + * @param event Pointer to accept the interrupt event + * + * @return None + */ +__attribute__((always_inline)) +static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) +{ + typeof(hw->int_status) int_sts = hw->int_status; + if (int_sts.tx_fifo_wm) { + *event = I2C_INTR_EVENT_TXFIFO_EMPTY; + } else if (int_sts.trans_complete) { + *event = I2C_INTR_EVENT_TRANS_DONE; + } else if (int_sts.rx_fifo_wm) { + *event = I2C_INTR_EVENT_RXFIFO_FULL; + } else { + *event = I2C_INTR_EVENT_ERR; + } +} + + +/** + * @brief Enable I2C master TX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_enable_tx_it(i2c_dev_t *hw) +{ + hw->int_clr.val = UINT32_MAX; + hw->int_ena.val = I2C_LL_MASTER_TX_INT; +} + +/** + * @brief Enable I2C master RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_enable_rx_it(i2c_dev_t *hw) +{ + hw->int_clr.val = UINT32_MAX; + hw->int_ena.val = I2C_LL_MASTER_RX_INT; +} + +/** + * @brief Disable I2C master TX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_disable_tx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT); +} + +/** + * @brief Disable I2C master RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +__attribute__((always_inline)) +static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_MASTER_RX_INT); +} + +/** + * @brief Enable I2C slave TX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_slave_enable_tx_it(i2c_dev_t *hw) +{ + hw->int_ena.val |= I2C_LL_SLAVE_TX_INT; +} + +/** + * @brief Enable I2C slave RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_slave_enable_rx_it(i2c_dev_t *hw) +{ + hw->int_ena.val |= I2C_LL_SLAVE_RX_INT; +} + +/** + * @brief Disable I2C slave TX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +__attribute__((always_inline)) +static inline void i2c_ll_slave_disable_tx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_SLAVE_TX_INT); +} + +/** + * @brief Disable I2C slave RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s2/include/hal/i2s_ll.h b/components/hal/esp32s2/include/hal/i2s_ll.h index 9483235b46..773c94e453 100644 --- a/components/hal/esp32s2/include/hal/i2s_ll.h +++ b/components/hal/esp32s2/include/hal/i2s_ll.h @@ -28,8 +28,6 @@ extern "C" { // Get I2S hardware instance with giving i2s num #define I2S_LL_GET_HW(num) (((num) == 0) ? (&I2S0) : NULL) -#define I2S_LL_BASE_CLK (2 * APB_CLK_FREQ) - #define I2S_LL_BCK_MAX_PRESCALE (64) #define I2S_LL_MCLK_DIVIDER_BIT_WIDTH (6) @@ -280,7 +278,7 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val) * @note mclk on ESP32S2 is shared by both TX and RX channel * * @param hw Peripheral I2S hardware instance address. - * @param sclk system clock, 0 means use apll + * @param sclk system clock * @param mclk module clock * @param mclk_div integer part of the division from sclk to mclk */ @@ -356,7 +354,7 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val) * @note mclk on ESP32S2 is shared by both TX and RX channel * * @param hw Peripheral I2S hardware instance address. - * @param sclk system clock, 0 means use apll + * @param sclk system clock * @param mclk module clock * @param mclk_div integer part of the division from sclk to mclk */ diff --git a/components/hal/esp32s2/include/hal/mmu_ll.h b/components/hal/esp32s2/include/hal/mmu_ll.h index 0eed27a4a3..43bfd9b39b 100644 --- a/components/hal/esp32s2/include/hal/mmu_ll.h +++ b/components/hal/esp32s2/include/hal/mmu_ll.h @@ -8,6 +8,7 @@ #pragma once +#include "stdint.h" #include "soc/extmem_reg.h" #include "soc/ext_mem_defs.h" #include "hal/assert.h" @@ -18,6 +19,38 @@ extern "C" { #endif +/** + * Convert MMU virtual address to linear address + * + * @param vaddr virtual address + * + * @return linear address + */ +static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr) +{ + return vaddr & SOC_MMU_LINEAR_ADDR_MASK; +} + +/** + * Convert MMU linear address to virtual address + * + * @param laddr linear address + * @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t` + * + * @return virtual address + */ +static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type) +{ + uint32_t vaddr_base = 0; + if (vaddr_type == MMU_VADDR_DATA) { + vaddr_base = SOC_MMU_DBUS_VADDR_BASE; + } else { + vaddr_base = SOC_MMU_IBUS_VADDR_BASE; + } + + return vaddr_base | laddr; +} + /** * Get MMU page size * diff --git a/components/hal/esp32s2/include/hal/rmt_ll.h b/components/hal/esp32s2/include/hal/rmt_ll.h index 5a453d1f32..23510d674a 100644 --- a/components/hal/esp32s2/include/hal/rmt_ll.h +++ b/components/hal/esp32s2/include/hal/rmt_ll.h @@ -104,6 +104,20 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, } } +/** + * @brief Enable RMT peripheral source clock + * + * @note RMT doesn't support enable/disable clock source, this function is only for compatibility + * + * @param dev Peripheral instance address + * @param en True to enable, False to disable + */ +static inline void rmt_ll_enable_group_clock(rmt_dev_t *dev, bool en) +{ + (void)dev; + (void)en; +} + ////////////////////////////////////////TX Channel Specific///////////////////////////////////////////////////////////// /** @@ -649,48 +663,57 @@ static inline uint32_t rmt_ll_rx_get_interrupt_status(rmt_dev_t *dev, uint32_t c /////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_status_word(rmt_dev_t *dev, uint32_t channel) { return dev->chnstatus[channel].val; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_status_word(rmt_dev_t *dev, uint32_t channel) { return dev->chnstatus[channel].val; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt_chn); return div == 0 ? 256 : div; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt_chn); return div == 0 ? 256 : div; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel) { return HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres_chn); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf0.mem_size_chn; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf0.mem_size_chn; } +__attribute__((always_inline)) static inline bool rmt_ll_tx_is_loop_enabled(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf1.tx_conti_mode_chn; } +__attribute__((always_inline)) static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel) { if (dev->conf_ch[channel].conf1.ref_always_on_chn) { @@ -699,11 +722,13 @@ static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint return RMT_CLK_SRC_REF_TICK; } +__attribute__((always_inline)) static inline bool rmt_ll_tx_is_idle_enabled(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf1.idle_out_en_chn; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf1.idle_out_lv_chn; @@ -717,41 +742,48 @@ static inline bool rmt_ll_is_mem_powered_down(rmt_dev_t *dev) return (dev->apb_conf.mem_force_pd) || !(dev->apb_conf.mem_force_pu); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_mem_owner(rmt_dev_t *dev, uint32_t channel) { return dev->conf_ch[channel].conf1.mem_owner_chn; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev) { uint32_t status = dev->int_st.val; return ((status & 0x01) >> 0) | ((status & 0x08) >> 2) | ((status & 0x40) >> 4) | ((status & 0x200) >> 6); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev) { uint32_t status = dev->int_st.val; return ((status & 0x02) >> 1) | ((status & 0x10) >> 3) | ((status & 0x80) >> 5) | ((status & 0x400) >> 7); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_err_interrupt_status(rmt_dev_t *dev) { uint32_t status = dev->int_st.val; return ((status & 0x04) >> 2) | ((status & 0x20) >> 4) | ((status & 0x100) >> 6) | ((status & 0x800) >> 8); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_err_interrupt_status(rmt_dev_t *dev) { uint32_t status = dev->int_st.val; return ((status & 0x04) >> 2) | ((status & 0x20) >> 4) | ((status & 0x100) >> 6) | ((status & 0x800) >> 8); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev) { uint32_t status = dev->int_st.val; return (status & 0xF000) >> 12; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_loop_interrupt_status(rmt_dev_t *dev) { uint32_t status = dev->int_st.val; diff --git a/components/hal/esp32s2/include/hal/rtc_cntl_ll.h b/components/hal/esp32s2/include/hal/rtc_cntl_ll.h index ffba472c47..9ce2461517 100644 --- a/components/hal/esp32s2/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32s2/include/hal/rtc_cntl_ll.h @@ -47,6 +47,21 @@ static inline void rtc_cntl_ll_ulp_int_clear(void) REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_TRAP_INT_CLR); } +static inline void rtc_cntl_ll_timer2_set_touch_wait_cycle(uint32_t wait_cycle) +{ + REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, wait_cycle); +} + +static inline void rtc_cntl_ll_reset_system(void) +{ + REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); +} + +static inline void rtc_cntl_ll_reset_cpu(int cpu_no) +{ + REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s2/include/hal/rtc_io_ll.h b/components/hal/esp32s2/include/hal/rtc_io_ll.h index cdd19466b6..4086e6d15a 100644 --- a/components/hal/esp32s2/include/hal/rtc_io_ll.h +++ b/components/hal/esp32s2/include/hal/rtc_io_ll.h @@ -1,16 +1,8 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /******************************************************************************* * NOTICE @@ -21,10 +13,8 @@ #pragma once #include -#include "soc/rtc_io_periph.h" -#include "soc/rtc_io_struct.h" +#include "soc/rtc_periph.h" #include "soc/sens_struct.h" -#include "hal/rtc_io_types.h" #include "hal/gpio_types.h" #define RTCIO_LL_PIN_FUNC 0 diff --git a/components/hal/esp32s2/include/hal/spi_ll.h b/components/hal/esp32s2/include/hal/spi_ll.h index 9b0fa420ec..65084c8d23 100644 --- a/components/hal/esp32s2/include/hal/spi_ll.h +++ b/components/hal/esp32s2/include/hal/spi_ll.h @@ -84,6 +84,21 @@ typedef enum { } spi_ll_trans_len_cond_t; FLAG_ATTR(spi_ll_trans_len_cond_t) +// SPI base command in esp32s2 +typedef enum { + /* Slave HD Only */ + SPI_LL_BASE_CMD_HD_WRBUF = 0x01, + SPI_LL_BASE_CMD_HD_RDBUF = 0x02, + SPI_LL_BASE_CMD_HD_WRDMA = 0x03, + SPI_LL_BASE_CMD_HD_RDDMA = 0x04, + SPI_LL_BASE_CMD_HD_SEG_END = 0x05, + SPI_LL_BASE_CMD_HD_EN_QPI = 0x06, + SPI_LL_BASE_CMD_HD_WR_END = 0x07, + SPI_LL_BASE_CMD_HD_INT0 = 0x08, + SPI_LL_BASE_CMD_HD_INT1 = 0x09, + SPI_LL_BASE_CMD_HD_INT2 = 0x0A, +} spi_ll_base_command_t; + /*------------------------------------------------------------------------------ * Control *----------------------------------------------------------------------------*/ @@ -1278,6 +1293,104 @@ static inline bool spi_ll_tx_get_empty_err(spi_dev_t *hw) #undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK +/** + * Get the base spi command in esp32s2 + * + * @param cmd_t Command value + */ +static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) +{ + uint8_t cmd_base = 0x00; + switch (cmd_t) + { + case SPI_CMD_HD_WRBUF: + cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; + break; + case SPI_CMD_HD_RDBUF: + cmd_base = SPI_LL_BASE_CMD_HD_RDBUF; + break; + case SPI_CMD_HD_WRDMA: + cmd_base = SPI_LL_BASE_CMD_HD_WRDMA; + break; + case SPI_CMD_HD_RDDMA: + cmd_base = SPI_LL_BASE_CMD_HD_RDDMA; + break; + case SPI_CMD_HD_SEG_END: + cmd_base = SPI_LL_BASE_CMD_HD_SEG_END; + break; + case SPI_CMD_HD_EN_QPI: + cmd_base = SPI_LL_BASE_CMD_HD_EN_QPI; + break; + case SPI_CMD_HD_WR_END: + cmd_base = SPI_LL_BASE_CMD_HD_WR_END; + break; + case SPI_CMD_HD_INT0: + cmd_base = SPI_LL_BASE_CMD_HD_INT0; + break; + case SPI_CMD_HD_INT1: + cmd_base = SPI_LL_BASE_CMD_HD_INT1; + break; + case SPI_CMD_HD_INT2: + cmd_base = SPI_LL_BASE_CMD_HD_INT2; + break; + default: + HAL_ASSERT(cmd_base); + } + return cmd_base; +} + +/** + * Get the spi communication command + * + * @param cmd_t Base command value + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode) +{ + uint8_t cmd_base = spi_ll_get_slave_hd_base_command(cmd_t); + uint8_t cmd_mod = 0x00; //CMD:1-bit, ADDR:1-bit, DATA:1-bit + + if (line_mode.data_lines == 2) { + if (line_mode.addr_lines == 2) { + cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit + } else { + cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit + } + } else if (line_mode.data_lines == 4) { + if (line_mode.addr_lines == 4) { + cmd_mod = 0xA0; //CMD:1-bit, ADDR:4-bit, DATA:4-bit + } else { + cmd_mod = 0x20; //CMD:1-bit, ADDR:1-bit, DATA:4-bit + } + } + if (cmd_base == SPI_LL_BASE_CMD_HD_SEG_END || cmd_base == SPI_LL_BASE_CMD_HD_EN_QPI) { + cmd_mod = 0x00; + } + + return cmd_base | cmd_mod; +} + +/** + * Get the dummy bits + * + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode) +{ + uint8_t dummy_bits = 0; + + if (line_mode.data_lines == 2) { + dummy_bits = 4; + } else if (line_mode.data_lines == 4) { + dummy_bits = 4; + } else { + dummy_bits = 8; + } + + HAL_ASSERT(dummy_bits); + return dummy_bits; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s2/include/hal/timer_ll.h b/components/hal/esp32s2/include/hal/timer_ll.h index 103881ef4f..42daa564e3 100644 --- a/components/hal/esp32s2/include/hal/timer_ll.h +++ b/components/hal/esp32s2/include/hal/timer_ll.h @@ -44,6 +44,22 @@ static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num, } } +/** + * @brief Enable Timer Group (GPTimer) module clock + * + * @note This function is not optional, created for backward compatible. + * + * @param hw Timer Group register base address + * @param timer_num Timer index in the group + * @param en true to enable, false to disable + */ +static inline void timer_ll_enable_clock(timg_dev_t *hw, uint32_t timer_num, bool en) +{ + (void)hw; + (void)timer_num; + (void)en; +} + /** * @brief Enable alarm event * @@ -116,6 +132,22 @@ static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, b hw->hw_timer[timer_num].config.tx_en = en; } +/** + * @brief Trigger software capture event + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + */ +__attribute__((always_inline)) +static inline void timer_ll_trigger_soft_capture(timg_dev_t *hw, uint32_t timer_num) +{ + hw->hw_timer[timer_num].update.tx_update = 1; + // Timer register is in a different clock domain from Timer hardware logic + // We need to wait for the update to take effect before fetching the count value + while (hw->hw_timer[timer_num].update.tx_update) { + } +} + /** * @brief Get counter value * @@ -127,11 +159,6 @@ static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, b __attribute__((always_inline)) static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer_num) { - hw->hw_timer[timer_num].update.tx_update = 1; - // Timer register is in a different clock domain from Timer hardware logic - // We need to wait for the update to take effect before fetching the count value - while (hw->hw_timer[timer_num].update.tx_update) { - } return ((uint64_t) hw->hw_timer[timer_num].hi.tx_hi << 32) | (hw->hw_timer[timer_num].lo.tx_lo); } diff --git a/components/hal/esp32s2/include/hal/uart_ll.h b/components/hal/esp32s2/include/hal/uart_ll.h index b5e27a37bd..90e7fb01d8 100644 --- a/components/hal/esp32s2/include/hal/uart_ll.h +++ b/components/hal/esp32s2/include/hal/uart_ll.h @@ -79,31 +79,19 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t* source_clk) *source_clk = hw->conf0.tick_ref_always_on ? UART_SCLK_APB : UART_SCLK_REF_TICK; } -/** - * @brief Get the UART source clock frequency. - * - * @param hw Beginning address of the peripheral registers. - * - * @return Current source clock frequency - */ -FORCE_INLINE_ATTR uint32_t uart_ll_get_sclk_freq(uart_dev_t *hw) -{ - return (hw->conf0.tick_ref_always_on) ? APB_CLK_FREQ : REF_CLK_FREQ; -} - /** * @brief Configure the baud-rate. * * @param hw Beginning address of the peripheral registers. * @param baud The baud rate to be set. When the source clock is APB, the max baud rate is `UART_LL_BITRATE_MAX` + * @param sclk_freq Frequency of the clock source of UART, in Hz. * @return None */ -FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud) +FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { - uint32_t sclk_freq, clk_div; + uint32_t clk_div; - sclk_freq = uart_ll_get_sclk_freq(hw); clk_div = ((sclk_freq) << 4) / baud; // The baud rate configuration register is divided into // an integer part and a fractional part. @@ -115,12 +103,12 @@ FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud) * @brief Get the current baud-rate. * * @param hw Beginning address of the peripheral registers. + * @param sclk_freq Frequency of the clock source of UART, in Hz. * * @return The current baudrate */ -FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq) { - uint32_t sclk_freq = uart_ll_get_sclk_freq(hw); typeof(hw->clk_div) div_reg = hw->clk_div; return ((sclk_freq << 4)) / ((div_reg.div_int << 4) | div_reg.div_frag); } diff --git a/components/hal/esp32s3/include/hal/aes_ll.h b/components/hal/esp32s3/include/hal/aes_ll.h index e18c44e58e..efa7928377 100644 --- a/components/hal/esp32s3/include/hal/aes_ll.h +++ b/components/hal/esp32s3/include/hal/aes_ll.h @@ -1,16 +1,8 @@ -// Copyright 2020-2021 Espressif Systems (Shanghai) CO LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -224,7 +216,7 @@ static inline void aes_ll_interrupt_enable(bool enable) */ static inline void aes_ll_interrupt_clear(void) { - REG_WRITE(AES_INT_CLR_REG, 1); + REG_WRITE(AES_INT_CLEAR_REG, 1); } diff --git a/components/hal/esp32s3/include/hal/gpio_ll.h b/components/hal/esp32s3/include/hal/gpio_ll.h index e98e0395a3..520707dd9c 100644 --- a/components/hal/esp32s3/include/hal/gpio_ll.h +++ b/components/hal/esp32s3/include/hal/gpio_ll.h @@ -14,6 +14,7 @@ #pragma once +#include #include "soc/soc.h" #include "soc/gpio_periph.h" #include "soc/rtc_cntl_reg.h" @@ -50,9 +51,18 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) { - REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); + // The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value + // USB DP pin is default to PU enabled + // Note that from esp32s3 ECO1, USB_EXCHG_PINS feature has been supported. If this efuse is burnt, the gpio pin + // which should be checked is USB_DM_GPIO_NUM instead. + if (gpio_num == USB_DP_GPIO_NUM) { + SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE); + CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP); + } + REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU); } /** @@ -72,9 +82,10 @@ static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) { - REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); + REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD); } /** @@ -175,9 +186,10 @@ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); + PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); } /** @@ -197,6 +209,7 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_output_disable(gpio_dev_t *hw, uint32_t gpio_num) { if (gpio_num < 32) { @@ -247,6 +260,21 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num) hw->pin[gpio_num].pad_driver = 1; } +/** + * @brief Select a function for the pin in the IOMUX + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + * @param func Function to assign to the pin + */ +static inline __attribute__((always_inline)) void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func) +{ + if (gpio_num == 19 || gpio_num == 20) { + CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); + } + PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func); +} + /** * @brief GPIO set output level * @@ -346,6 +374,7 @@ static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu */ static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw) { + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); } @@ -356,7 +385,22 @@ static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw) */ static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw) { - SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD); + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); +} + +/** + * @brief Get deep sleep hold status + * + * @param hw Peripheral GPIO hardware instance address. + * + * @return + * - true deep sleep hold is enabled + * - false deep sleep hold is disabled + */ +__attribute__((always_inline)) +static inline bool gpio_ll_deep_sleep_hold_is_en(gpio_dev_t *hw) +{ + return !GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD) && GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); } /** @@ -381,6 +425,24 @@ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num) CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); } +/** + * @brief Get gpio pad hold status. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + * + * @note caller must ensure that gpio_num is a digital io pad + * + * @return + * - true digital gpio pad is held + * - false digital gpio pad is unheld + */ +__attribute__((always_inline)) +static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num) +{ + return GET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, BIT(gpio_num - 21)); +} + /** * @brief Set pad input to a peripheral signal through the IOMUX. * @@ -425,7 +487,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, } /** - * @brief Force hold digital and rtc gpio pad. + * @brief Force hold digital gpio pad. * @note GPIO force hold, whether the chip in sleep mode or wakeup mode. */ static inline void gpio_ll_force_hold_all(void) @@ -435,7 +497,7 @@ static inline void gpio_ll_force_hold_all(void) } /** - * @brief Force unhold digital and rtc gpio pad. + * @brief Force unhold digital gpio pad. * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode. */ static inline void gpio_ll_force_unhold_all(void) diff --git a/components/hal/esp32s3/include/hal/i2c_ll.h b/components/hal/esp32s3/include/hal/i2c_ll.h index 617e9f3856..38bd0762ba 100644 --- a/components/hal/esp32s3/include/hal/i2c_ll.h +++ b/components/hal/esp32s3/include/hal/i2c_ll.h @@ -8,18 +8,19 @@ #pragma once +#include "stdbool.h" #include "hal/misc.h" #include "soc/i2c_periph.h" #include "soc/soc_caps.h" #include "soc/i2c_struct.h" #include "soc/clk_tree_defs.h" #include "hal/i2c_types.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { #endif -#define I2C_LL_INTR_MASK (0x3fff) /*!< I2C all interrupt bitmap */ /** * @brief I2C hardware cmd register fields. */ @@ -36,35 +37,6 @@ typedef union { uint32_t val; } i2c_hw_cmd_t; -/** - * @brief I2C interrupt event - */ -typedef enum { - I2C_INTR_EVENT_ERR, - I2C_INTR_EVENT_ARBIT_LOST, /*!< I2C arbition lost event */ - I2C_INTR_EVENT_NACK, /*!< I2C NACK event */ - I2C_INTR_EVENT_TOUT, /*!< I2C time out event */ - I2C_INTR_EVENT_END_DET, /*!< I2C end detected event */ - I2C_INTR_EVENT_TRANS_DONE, /*!< I2C trans done event */ - I2C_INTR_EVENT_RXFIFO_FULL, /*!< I2C rxfifo full event */ - I2C_INTR_EVENT_TXFIFO_EMPTY, /*!< I2C txfifo empty event */ -} i2c_intr_event_t; - -/** - * @brief Data structure for calculating I2C bus timing. - */ -typedef struct { - uint16_t clkm_div; /*!< I2C core clock divider */ - uint16_t scl_low; /*!< I2C scl low period */ - uint16_t scl_high; /*!< I2C scl hight period */ - uint16_t scl_wait_high; /*!< I2C scl wait_high period */ - uint16_t sda_hold; /*!< I2C scl low period */ - uint16_t sda_sample; /*!< I2C sda sample time */ - uint16_t setup; /*!< I2C start and stop condition setup period */ - uint16_t hold; /*!< I2C start and stop condition hold period */ - uint16_t tout; /*!< I2C bus timeout period */ -} i2c_clk_cal_t; - // I2C operation mode command #define I2C_LL_CMD_RESTART 6 /*!ctr.conf_upgate = 1; @@ -141,7 +118,7 @@ static inline void i2c_ll_update(i2c_dev_t *hw) * * @return None */ -static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_clk_cal_t *bus_cfg) +static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_hal_clk_config_t *bus_cfg) { HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, bus_cfg->clkm_div - 1); /* According to the Technical Reference Manual, the following timings must be subtracted by 1. @@ -208,23 +185,6 @@ static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int high_period, int low hw->scl_high_period.scl_wait_high_period = high_period - high_period_output; } -/** - * @brief Configure I2C SCL timing - * - * @param hw Beginning address of the peripheral registers - * @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2) - * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) - * @param wait_high_period The I2C SCL wait rising edge period. - * - * @return None. - */ -static inline void i2c_ll_set_scl_clk_timing(i2c_dev_t *hw, int high_period, int low_period, int wait_high_period) -{ - hw->scl_low_period.scl_low_period = low_period; - hw->scl_high_period.scl_high_period = high_period; - hw->scl_high_period.scl_wait_high_period = wait_high_period; -} - /** * @brief Clear I2C interrupt status * @@ -233,7 +193,8 @@ static inline void i2c_ll_set_scl_clk_timing(i2c_dev_t *hw, int high_period, int * * @return None */ -static inline void i2c_ll_clr_intsts_mask(i2c_dev_t *hw, uint32_t mask) +__attribute__((always_inline)) +static inline void i2c_ll_clear_intr_mask(i2c_dev_t *hw, uint32_t mask) { hw->int_clr.val = mask; } @@ -259,6 +220,7 @@ static inline void i2c_ll_enable_intr_mask(i2c_dev_t *hw, uint32_t mask) * * @return None */ +__attribute__((always_inline)) static inline void i2c_ll_disable_intr_mask(i2c_dev_t *hw, uint32_t mask) { hw->int_ena.val &= (~mask); @@ -271,9 +233,10 @@ static inline void i2c_ll_disable_intr_mask(i2c_dev_t *hw, uint32_t mask) * * @return I2C interrupt status */ -static inline uint32_t i2c_ll_get_intsts_mask(i2c_dev_t *hw) +__attribute__((always_inline)) +static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status) { - return hw->int_status.val; + *intr_status = hw->int_status.val; } /** @@ -493,9 +456,10 @@ static inline bool i2c_ll_is_master_mode(i2c_dev_t *hw) * * @return RxFIFO readable length */ -static inline uint32_t i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw) +__attribute__((always_inline)) +static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length) { - return hw->sr.rxfifo_cnt; + *length = hw->sr.rxfifo_cnt; } /** @@ -505,9 +469,10 @@ static inline uint32_t i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw) * * @return TxFIFO writable length */ -static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw) +__attribute__((always_inline)) +static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length) { - return SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt; + *length = SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt; } /** @@ -517,9 +482,9 @@ static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw) * * @return The I2C timeout value */ -static inline uint32_t i2c_ll_get_tout(i2c_dev_t *hw) +static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout) { - return hw->to.time_out_value; + *timeout = hw->to.time_out_value; } /** @@ -579,22 +544,6 @@ static inline void i2c_ll_get_scl_timing(i2c_dev_t *hw, int *high_period, int *l *low_period = hw->scl_low_period.scl_low_period + 1; } -/** - * @brief Get I2C SCL timing configuration - * - * @param hw Beginning address of the peripheral registers - * @param high_period Pointer to accept the SCL high period - * @param low_period Pointer to accept the SCL low period - * - * @return None - */ -static inline void i2c_ll_get_scl_clk_timing(i2c_dev_t *hw, int *high_period, int *low_period, int *wait_high_period) -{ - *high_period = hw->scl_high_period.scl_high_period; - *wait_high_period = hw->scl_high_period.scl_wait_high_period; - *low_period = hw->scl_low_period.scl_low_period; -} - /** * @brief Write the I2C hardware txFIFO * @@ -604,7 +553,8 @@ static inline void i2c_ll_get_scl_clk_timing(i2c_dev_t *hw, int *high_period, in * * @return None. */ -static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) +__attribute__((always_inline)) +static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len) { for (int i = 0; i< len; i++) { HAL_FORCE_MODIFY_U32_REG_FIELD(hw->data, fifo_rdata, ptr[i]); @@ -620,6 +570,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) * * @return None */ +__attribute__((always_inline)) static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) { for(int i = 0; i < len; i++) { @@ -656,155 +607,9 @@ static inline void i2c_ll_set_filter(i2c_dev_t *hw, uint8_t filter_num) * * @return The hardware filter configuration */ -static inline uint8_t i2c_ll_get_filter(i2c_dev_t *hw) +static inline void i2c_ll_get_filter(i2c_dev_t *hw, uint8_t *filter_conf) { - return hw->filter_cfg.scl_filter_thres; -} - -/** - * @brief Enable I2C master TX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_enable_tx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = ~0; - hw->int_ena.val = I2C_LL_MASTER_TX_INT; -} - -/** - * @brief Enable I2C master RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_enable_rx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = ~0; - hw->int_ena.val = I2C_LL_MASTER_RX_INT; -} - -/** - * @brief Disable I2C master TX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_disable_tx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT); -} - -/** - * @brief Disable I2C master RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_MASTER_RX_INT); -} - -/** - * @brief Clear I2C master TX interrupt status register - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_clr_tx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = I2C_LL_MASTER_TX_INT; -} - -/** - * @brief Clear I2C master RX interrupt status register - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_clr_rx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = I2C_LL_MASTER_RX_INT; -} - -/** - * @brief - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_enable_tx_it(i2c_dev_t *hw) -{ - hw->int_ena.val |= I2C_LL_SLAVE_TX_INT; -} - -/** - * @brief Enable I2C slave RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_enable_rx_it(i2c_dev_t *hw) -{ - hw->int_ena.val |= I2C_LL_SLAVE_RX_INT; -} - -/** - * @brief Disable I2C slave TX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_disable_tx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_SLAVE_TX_INT); -} - -/** - * @brief Disable I2C slave RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT); -} - -/** - * @brief Clear I2C slave TX interrupt status register - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_clr_tx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = I2C_LL_SLAVE_TX_INT; -} - -/** - * @brief Clear I2C slave RX interrupt status register. - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_clr_rx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = I2C_LL_SLAVE_RX_INT; + *filter_conf = hw->filter_cfg.scl_filter_thres; } /** @@ -832,9 +637,8 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw) static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw) { hw->scl_sp_conf.scl_rst_slv_num = 9; - hw->scl_sp_conf.scl_rst_slv_en = 0; - hw->ctr.conf_upgate = 1; hw->scl_sp_conf.scl_rst_slv_en = 1; + hw->ctr.conf_upgate = 1; } /** @@ -850,54 +654,6 @@ static inline void i2c_ll_set_source_clk(i2c_dev_t *hw, i2c_clock_source_t src_c hw->clk_conf.sclk_sel = (src_clk == I2C_CLK_SRC_RC_FAST) ? 1 : 0; } -/** - * @brief Get I2C master interrupt event - * - * @param hw Beginning address of the peripheral registers - * @param event Pointer to accept the interrupt event - * - * @return None - */ -static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) -{ - typeof(hw->int_status) int_sts = hw->int_status; - if (int_sts.arbitration_lost_int_st) { - *event = I2C_INTR_EVENT_ARBIT_LOST; - } else if (int_sts.nack_int_st) { - *event = I2C_INTR_EVENT_NACK; - } else if (int_sts.time_out_int_st) { - *event = I2C_INTR_EVENT_TOUT; - } else if (int_sts.end_detect_int_st) { - *event = I2C_INTR_EVENT_END_DET; - } else if (int_sts.trans_complete_int_st) { - *event = I2C_INTR_EVENT_TRANS_DONE; - } else { - *event = I2C_INTR_EVENT_ERR; - } -} - -/** - * @brief Get I2C slave interrupt event - * - * @param hw Beginning address of the peripheral registers - * @param event Pointer to accept the interrupt event - * - * @return None - */ -static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) -{ - typeof(hw->int_status) int_sts = hw->int_status; - if (int_sts.txfifo_wm_int_st) { - *event = I2C_INTR_EVENT_TXFIFO_EMPTY; - } else if (int_sts.trans_complete_int_st) { - *event = I2C_INTR_EVENT_TRANS_DONE; - } else if (int_sts.rxfifo_wm_int_st) { - *event = I2C_INTR_EVENT_RXFIFO_FULL; - } else { - *event = I2C_INTR_EVENT_ERR; - } -} - /** * @brief Init I2C master * @@ -930,10 +686,247 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw) ctrl_reg.sda_force_out = 1; ctrl_reg.scl_force_out = 1; hw->ctr.val = ctrl_reg.val; - hw->ctr.slv_tx_auto_start_en = 1; hw->fifo_conf.fifo_addr_cfg_en = 0; } +/** + * @brief Set whether slave should auto start, or only start with start signal from master + * + * @param hw Beginning address of the peripheral registers + * @param slv_ex_auto_en 1 if slave auto start data transaction, otherwise, 0. + */ +static inline void i2c_ll_slave_tx_auto_start_en(i2c_dev_t *hw, bool slv_ex_auto_en) +{ + hw->ctr.slv_tx_auto_start_en = slv_ex_auto_en; +} + +/** + * @brief Get I2C interrupt status register address + */ +static inline volatile void *i2c_ll_get_interrupt_status_reg(i2c_dev_t *dev) +{ + return &dev->int_status; +} + +//////////////////////////////////////////Deprecated Functions////////////////////////////////////////////////////////// +/////////////////////////////The following functions are only used by the legacy driver///////////////////////////////// +/////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +// Get the I2C hardware instance +#define I2C_LL_GET_HW(i2c_num) (((i2c_num) == 0) ? &I2C0 : &I2C1) +// Get the I2C hardware FIFO address +#define I2C_LL_GET_FIFO_ADDR(i2c_num) (I2C_DATA_APB_REG(i2c_num)) +// I2C master TX interrupt bitmap +#define I2C_LL_MASTER_TX_INT (I2C_NACK_INT_ENA_M|I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M) +// I2C master RX interrupt bitmap +#define I2C_LL_MASTER_RX_INT (I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M) +// I2C slave TX interrupt bitmap +#define I2C_LL_SLAVE_TX_INT (I2C_TXFIFO_WM_INT_ENA_M) +// I2C slave RX interrupt bitmap +#define I2C_LL_SLAVE_RX_INT (I2C_RXFIFO_WM_INT_ENA_M | I2C_TRANS_COMPLETE_INT_ENA_M) +// I2C max timeout value +#define I2C_LL_MAX_TIMEOUT I2C_TIME_OUT_VALUE_V + +#define I2C_LL_INTR_MASK (0x3fff) /*!< I2C all interrupt bitmap */ + +/** + * @brief I2C interrupt event + */ +typedef enum { + I2C_INTR_EVENT_ERR, + I2C_INTR_EVENT_ARBIT_LOST, /*!< I2C arbition lost event */ + I2C_INTR_EVENT_NACK, /*!< I2C NACK event */ + I2C_INTR_EVENT_TOUT, /*!< I2C time out event */ + I2C_INTR_EVENT_END_DET, /*!< I2C end detected event */ + I2C_INTR_EVENT_TRANS_DONE, /*!< I2C trans done event */ + I2C_INTR_EVENT_RXFIFO_FULL, /*!< I2C rxfifo full event */ + I2C_INTR_EVENT_TXFIFO_EMPTY, /*!< I2C txfifo empty event */ +} i2c_intr_event_t; + +/** + * @brief Get I2C SCL timing configuration + * + * @param hw Beginning address of the peripheral registers + * @param high_period Pointer to accept the SCL high period + * @param low_period Pointer to accept the SCL low period + * + * @return None + */ +static inline void i2c_ll_get_scl_clk_timing(i2c_dev_t *hw, int *high_period, int *low_period, int *wait_high_period) +{ + *high_period = hw->scl_high_period.scl_high_period; + *wait_high_period = hw->scl_high_period.scl_wait_high_period; + *low_period = hw->scl_low_period.scl_low_period; +} + +/** + * @brief Configure I2C SCL timing + * + * @param hw Beginning address of the peripheral registers + * @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2) + * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) + * @param wait_high_period The I2C SCL wait rising edge period. + * + * @return None. + */ +static inline void i2c_ll_set_scl_clk_timing(i2c_dev_t *hw, int high_period, int low_period, int wait_high_period) +{ + hw->scl_low_period.scl_low_period = low_period; + hw->scl_high_period.scl_high_period = high_period; + hw->scl_high_period.scl_wait_high_period = wait_high_period; +} + +/** + * @brief Get I2C master interrupt event + * + * @param hw Beginning address of the peripheral registers + * @param event Pointer to accept the interrupt event + * + * @return None + */ +__attribute__((always_inline)) +static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) +{ + typeof(hw->int_status) int_sts = hw->int_status; + if (int_sts.arbitration_lost_int_st) { + *event = I2C_INTR_EVENT_ARBIT_LOST; + } else if (int_sts.nack_int_st) { + *event = I2C_INTR_EVENT_NACK; + } else if (int_sts.time_out_int_st) { + *event = I2C_INTR_EVENT_TOUT; + } else if (int_sts.end_detect_int_st) { + *event = I2C_INTR_EVENT_END_DET; + } else if (int_sts.trans_complete_int_st) { + *event = I2C_INTR_EVENT_TRANS_DONE; + } else { + *event = I2C_INTR_EVENT_ERR; + } +} + +/** + * @brief Get I2C slave interrupt event + * + * @param hw Beginning address of the peripheral registers + * @param event Pointer to accept the interrupt event + * + * @return None + */ +__attribute__((always_inline)) +static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) +{ + typeof(hw->int_status) int_sts = hw->int_status; + if (int_sts.txfifo_wm_int_st) { + *event = I2C_INTR_EVENT_TXFIFO_EMPTY; + } else if (int_sts.trans_complete_int_st) { + *event = I2C_INTR_EVENT_TRANS_DONE; + } else if (int_sts.rxfifo_wm_int_st) { + *event = I2C_INTR_EVENT_RXFIFO_FULL; + } else { + *event = I2C_INTR_EVENT_ERR; + } +} + +/** + * @brief Enable I2C master TX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_enable_tx_it(i2c_dev_t *hw) +{ + hw->int_clr.val = UINT32_MAX; + hw->int_ena.val = I2C_LL_MASTER_TX_INT; +} + +/** + * @brief Enable I2C master RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_enable_rx_it(i2c_dev_t *hw) +{ + hw->int_clr.val = UINT32_MAX; + hw->int_ena.val = I2C_LL_MASTER_RX_INT; +} + +/** + * @brief Disable I2C master TX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_master_disable_tx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT); +} + +/** + * @brief Disable I2C master RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +__attribute__((always_inline)) +static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_MASTER_RX_INT); +} + +/** + * @brief + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_slave_enable_tx_it(i2c_dev_t *hw) +{ + hw->int_ena.val |= 0x2; +} + +/** + * @brief Enable I2C slave RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_slave_enable_rx_it(i2c_dev_t *hw) +{ + hw->int_ena.val |= I2C_LL_SLAVE_RX_INT; +} + +/** + * @brief Disable I2C slave TX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +__attribute__((always_inline)) +static inline void i2c_ll_slave_disable_tx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_SLAVE_TX_INT); +} + +/** + * @brief Disable I2C slave RX interrupt + * + * @param hw Beginning address of the peripheral registers + * + * @return None + */ +static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw) +{ + hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s3/include/hal/i2s_ll.h b/components/hal/esp32s3/include/hal/i2s_ll.h index 14b4e6d4e7..0f35ff0be3 100644 --- a/components/hal/esp32s3/include/hal/i2s_ll.h +++ b/components/hal/esp32s3/include/hal/i2s_ll.h @@ -14,6 +14,7 @@ #pragma once #include #include "hal/misc.h" +#include "hal/assert.h" #include "soc/i2s_periph.h" #include "soc/i2s_struct.h" #include "hal/i2s_types.h" @@ -28,7 +29,6 @@ extern "C" { #define I2S_LL_TDM_CH_MASK (0xffff) #define I2S_LL_PDM_BCK_FACTOR (64) -#define I2S_LL_BASE_CLK (2*APB_CLK_FREQ) #define I2S_LL_MCLK_DIVIDER_BIT_WIDTH (9) #define I2S_LL_MCLK_DIVIDER_MAX ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1) @@ -190,26 +190,45 @@ static inline void i2s_ll_rx_reset_fifo(i2s_dev_t *hw) * @brief Set TX source clock * * @param hw Peripheral I2S hardware instance address. - * @param src I2S source clock, ESP32-S3 only support `I2S_CLK_SRC_PLL_160M` - * TX and RX share the same clock setting + * @param src I2S source clock. */ static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src) { - hw->tx_clkm_conf.tx_clk_sel = 2; + switch (src) + { + case I2S_CLK_SRC_XTAL: + hw->tx_clkm_conf.tx_clk_sel = 0; + break; + case I2S_CLK_SRC_PLL_160M: + hw->tx_clkm_conf.tx_clk_sel = 2; + break; + default: + HAL_ASSERT(false && "unsupported clock source"); + break; + } } /** * @brief Set RX source clock * * @param hw Peripheral I2S hardware instance address. - * @param src I2S source clock, ESP32-S3 only support `I2S_CLK_SRC_PLL_160M` - * TX and RX share the same clock setting + * @param src I2S source clock */ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src) { - hw->rx_clkm_conf.rx_clk_sel = 2; + switch (src) + { + case I2S_CLK_SRC_XTAL: + hw->rx_clkm_conf.rx_clk_sel = 0; + break; + case I2S_CLK_SRC_PLL_160M: + hw->rx_clkm_conf.rx_clk_sel = 2; + break; + default: + HAL_ASSERT(false && "unsupported clock source"); + break; + } } - /** * @brief Set I2S tx bck div num * @@ -259,7 +278,7 @@ static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t * @brief Configure I2S TX module clock divider * * @param hw Peripheral I2S hardware instance address. - * @param sclk system clock, 0 means use apll + * @param sclk system clock * @param mclk module clock * @param mclk_div integer part of the division from sclk to mclk */ diff --git a/components/hal/esp32s3/include/hal/lcd_ll.h b/components/hal/esp32s3/include/hal/lcd_ll.h index 41a886b2af..f2cc1487be 100644 --- a/components/hal/esp32s3/include/hal/lcd_ll.h +++ b/components/hal/esp32s3/include/hal/lcd_ll.h @@ -28,6 +28,10 @@ extern "C" { #define LCD_LL_CLK_FRAC_DIV_AB_MAX 64 // LCD_CLK = LCD_CLK_S / (N + b/a), the a/b register is 6 bit-width #define LCD_LL_PCLK_DIV_MAX 64 // LCD_PCLK = LCD_CLK / MO, the MO register is 6 bit-width +#define LCD_LL_COLOR_RANGE_TO_REG(range) (uint8_t[]){0,1}[(range)] +#define LCD_LL_CONV_STD_TO_REG(std) (uint8_t[]){0,1}[(std)] +#define LCD_LL_YUV_SAMPLE_TO_REG(sample) (uint8_t[]){0,1,2}[(sample)] + /** * @brief Enable clock gating * @@ -144,6 +148,92 @@ static inline void lcd_ll_enable_rgb_yuv_convert(lcd_cam_dev_t *dev, bool en) dev->lcd_rgb_yuv.lcd_conv_bypass = en; } +/** + * @brief Set convert data line width + * + * @param dev LCD register base address + * @param width data line width (8 or 16) + */ +static inline void lcd_ll_set_convert_data_width(lcd_cam_dev_t *dev, uint32_t width) +{ + HAL_ASSERT(width == 8 || width == 16); + dev->lcd_rgb_yuv.lcd_conv_mode_8bits_on = (width == 8) ? 1 : 0; +} + +/** + * @brief Set the color range of input data + * + * @param dev LCD register base address + * @param range Color range + */ +static inline void lcd_ll_set_input_color_range(lcd_cam_dev_t *dev, lcd_color_range_t range) +{ + dev->lcd_rgb_yuv.lcd_conv_data_in_mode = LCD_LL_COLOR_RANGE_TO_REG(range); +} + +/** + * @brief Set the color range of output data + * + * @param dev LCD register base address + * @param range Color range + */ +static inline void lcd_ll_set_output_color_range(lcd_cam_dev_t *dev, lcd_color_range_t range) +{ + dev->lcd_rgb_yuv.lcd_conv_data_out_mode = LCD_LL_COLOR_RANGE_TO_REG(range); +} + +/** + * @brief Set YUV conversion standard + * + * @param dev LCD register base address + * @param std YUV conversion standard + */ +static inline void lcd_ll_set_yuv_convert_std(lcd_cam_dev_t *dev, lcd_yuv_conv_std_t std) +{ + dev->lcd_rgb_yuv.lcd_conv_protocol_mode = LCD_LL_CONV_STD_TO_REG(std); +} + +/** + * @brief Set the converter mode: RGB565 to YUV + * + * @param dev LCD register base address + * @param yuv_sample YUV sample mode + */ +static inline void lcd_ll_set_convert_mode_rgb_to_yuv(lcd_cam_dev_t *dev, lcd_yuv_sample_t yuv_sample) +{ + dev->lcd_rgb_yuv.lcd_conv_trans_mode = 1; + dev->lcd_rgb_yuv.lcd_conv_yuv_mode = LCD_LL_YUV_SAMPLE_TO_REG(yuv_sample); + dev->lcd_rgb_yuv.lcd_conv_yuv2yuv_mode = 3; +} + +/** + * @brief Set the converter mode: YUV to RGB565 + * + * @param dev LCD register base address + * @param yuv_sample YUV sample mode + */ +static inline void lcd_ll_set_convert_mode_yuv_to_rgb(lcd_cam_dev_t *dev, lcd_yuv_sample_t yuv_sample) +{ + dev->lcd_rgb_yuv.lcd_conv_trans_mode = 0; + dev->lcd_rgb_yuv.lcd_conv_yuv_mode = LCD_LL_YUV_SAMPLE_TO_REG(yuv_sample); + dev->lcd_rgb_yuv.lcd_conv_yuv2yuv_mode = 3; +} + +/** + * @brief Set the converter mode: YUV to YUV + * + * @param dev LCD register base address + * @param src_sample Source YUV sample mode + * @param dst_sample Destination YUV sample mode + */ +static inline void lcd_ll_set_convert_mode_yuv_to_yuv(lcd_cam_dev_t *dev, lcd_yuv_sample_t src_sample, lcd_yuv_sample_t dst_sample) +{ + HAL_ASSERT(src_sample != dst_sample); + dev->lcd_rgb_yuv.lcd_conv_trans_mode = 1; + dev->lcd_rgb_yuv.lcd_conv_yuv_mode = LCD_LL_YUV_SAMPLE_TO_REG(src_sample); + dev->lcd_rgb_yuv.lcd_conv_yuv2yuv_mode = LCD_LL_YUV_SAMPLE_TO_REG(dst_sample); +} + /** * @brief Set clock cycles of each transaction phases * diff --git a/components/hal/esp32s3/include/hal/mmu_ll.h b/components/hal/esp32s3/include/hal/mmu_ll.h index fe2d38cd38..dfe70f1dee 100644 --- a/components/hal/esp32s3/include/hal/mmu_ll.h +++ b/components/hal/esp32s3/include/hal/mmu_ll.h @@ -18,6 +18,38 @@ extern "C" { #endif +/** + * Convert MMU virtual address to linear address + * + * @param vaddr virtual address + * + * @return linear address + */ +static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr) +{ + return vaddr & SOC_MMU_LINEAR_ADDR_MASK; +} + +/** + * Convert MMU linear address to virtual address + * + * @param laddr linear address + * @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t` + * + * @return virtual address + */ +static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type) +{ + uint32_t vaddr_base = 0; + if (vaddr_type == MMU_VADDR_DATA) { + vaddr_base = SOC_MMU_DBUS_VADDR_BASE; + } else { + vaddr_base = SOC_MMU_IBUS_VADDR_BASE; + } + + return vaddr_base | laddr; +} + /** * Get MMU page size * diff --git a/components/hal/esp32s3/include/hal/rmt_ll.h b/components/hal/esp32s3/include/hal/rmt_ll.h index 7b2ba02876..9489593940 100644 --- a/components/hal/esp32s3/include/hal/rmt_ll.h +++ b/components/hal/esp32s3/include/hal/rmt_ll.h @@ -90,7 +90,6 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, // Formula: rmt_sclk = module_clock_src / (1 + div_num + div_a / div_b) (void)channel; // the source clock is set for all channels HAL_ASSERT(divider_integral >= 1); - dev->sys_conf.sclk_active = 0; HAL_FORCE_MODIFY_U32_REG_FIELD(dev->sys_conf, sclk_div_num, divider_integral - 1); dev->sys_conf.sclk_div_a = divider_numerator; dev->sys_conf.sclk_div_b = divider_denominator; @@ -108,7 +107,17 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, HAL_ASSERT(false && "unsupported RMT clock source"); break; } - dev->sys_conf.sclk_active = 1; +} + +/** + * @brief Enable RMT peripheral source clock + * + * @param dev Peripheral instance address + * @param en True to enable, False to disable + */ +static inline void rmt_ll_enable_group_clock(rmt_dev_t *dev, bool en) +{ + dev->sys_conf.sclk_active = en; } ////////////////////////////////////////TX Channel Specific///////////////////////////////////////////////////////////// @@ -722,48 +731,57 @@ static inline uint32_t rmt_ll_rx_get_interrupt_status(rmt_dev_t *dev, uint32_t c /////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_status_word(rmt_dev_t *dev, uint32_t channel) { return dev->chnstatus[channel].val; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_status_word(rmt_dev_t *dev, uint32_t channel) { return dev->chmstatus[channel].val; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->chnconf0[channel], div_cnt_chn); return div == 0 ? 256 : div; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->chmconf[channel].conf0, div_cnt_chm); return div == 0 ? 256 : div; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel) { return dev->chmconf[channel].conf0.idle_thres_chm; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) { return dev->chnconf0[channel].mem_size_chn; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) { return dev->chmconf[channel].conf0.mem_size_chm; } +__attribute__((always_inline)) static inline bool rmt_ll_tx_is_loop_enabled(rmt_dev_t *dev, uint32_t channel) { return dev->chnconf0[channel].tx_conti_mode_chn; } +__attribute__((always_inline)) static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel) { rmt_clock_source_t clk_src = RMT_CLK_SRC_APB; @@ -781,11 +799,13 @@ static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint return clk_src; } +__attribute__((always_inline)) static inline bool rmt_ll_tx_is_idle_enabled(rmt_dev_t *dev, uint32_t channel) { return dev->chnconf0[channel].idle_out_en_chn; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel) { return dev->chnconf0[channel].idle_out_lv_chn; @@ -799,46 +819,55 @@ static inline bool rmt_ll_is_mem_powered_down(rmt_dev_t *dev) return (dev->sys_conf.mem_force_pd) || !(dev->sys_conf.mem_force_pu); } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_mem_owner(rmt_dev_t *dev, uint32_t channel) { return dev->chmconf[channel].conf1.mem_owner_chm; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_rx_get_limit(rmt_dev_t *dev, uint32_t channel) { return dev->chm_rx_lim[channel].rx_lim_chm; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev) { return dev->int_st.val & 0x0F; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 16) & 0x0F; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_err_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 4) & 0x0F; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_err_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 20) & 0x0F; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 8) & 0x0F; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_rx_thres_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 24) & 0x0F; } +__attribute__((always_inline)) static inline uint32_t rmt_ll_get_tx_loop_interrupt_status(rmt_dev_t *dev) { return (dev->int_st.val >> 12) & 0x0F; diff --git a/components/hal/esp32s3/include/hal/rtc_cntl_ll.h b/components/hal/esp32s3/include/hal/rtc_cntl_ll.h index 3dfa5e3e71..947f113668 100644 --- a/components/hal/esp32s3/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32s3/include/hal/rtc_cntl_ll.h @@ -127,6 +127,22 @@ static inline void rtc_cntl_ll_ulp_int_clear(void) REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_TRAP_INT_CLR); } +static inline void rtc_cntl_ll_timer2_set_touch_wait_cycle(uint32_t wait_cycle) +{ + REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, wait_cycle); +} + +static inline void rtc_cntl_ll_reset_system(void) +{ + REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); +} + +static inline void rtc_cntl_ll_reset_cpu(int cpu_no) +{ + uint32_t rtc_cntl_rst = (cpu_no == 0) ? RTC_CNTL_SW_PROCPU_RST : RTC_CNTL_SW_APPCPU_RST; + REG_WRITE(RTC_CNTL_OPTIONS0_REG, rtc_cntl_rst); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s3/include/hal/rtc_io_ll.h b/components/hal/esp32s3/include/hal/rtc_io_ll.h index ff3a314fd5..92d684c13b 100644 --- a/components/hal/esp32s3/include/hal/rtc_io_ll.h +++ b/components/hal/esp32s3/include/hal/rtc_io_ll.h @@ -13,10 +13,11 @@ #pragma once #include -#include "soc/rtc_io_periph.h" -#include "soc/rtc_io_struct.h" -#include "hal/rtc_io_types.h" +#include "soc/rtc_periph.h" #include "hal/gpio_types.h" +#include "soc/io_mux_reg.h" +#include "soc/usb_serial_jtag_reg.h" +#include "soc/usb_serial_jtag_struct.h" #ifdef __cplusplus extern "C" { @@ -50,6 +51,10 @@ typedef enum { static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func) { if (func == RTCIO_FUNC_RTC) { + // Disable USB Serial JTAG if pin 19 or pin 20 needs to select the rtc function + if (rtcio_num == rtc_io_num_map[USB_DM_GPIO_NUM] || rtcio_num == rtc_io_num_map[USB_DP_GPIO_NUM]) { + USB_SERIAL_JTAG.conf0.usb_pad_enable = 0; + } SENS.sar_peri_clk_gate_conf.iomux_clk_en = 1; // 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module. SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux)); @@ -58,6 +63,8 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func) } else if (func == RTCIO_FUNC_DIGITAL) { CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux)); SENS.sar_peri_clk_gate_conf.iomux_clk_en = 0; + // USB Serial JTAG pad re-enable won't be done here (it requires both DM and DP pins not in rtc function) + // Instead, USB_SERIAL_JTAG_USB_PAD_ENABLE needs to be guaranteed to be set in usb_serial_jtag driver } } @@ -181,6 +188,14 @@ static inline void rtcio_ll_pullup_enable(int rtcio_num) */ static inline void rtcio_ll_pullup_disable(int rtcio_num) { + // The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value + // USB DP pin is default to PU enabled + // Note that from esp32s3 ECO1, USB_EXCHG_PINS feature has been supported. If this efuse is burnt, the gpio pin + // which should be checked is USB_DM_GPIO_NUM instead. + if (rtcio_num == USB_DP_GPIO_NUM) { + SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE); + CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP); + } if (rtc_io_desc[rtcio_num].pullup) { CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].pullup); } diff --git a/components/hal/esp32s3/include/hal/spi_ll.h b/components/hal/esp32s3/include/hal/spi_ll.h index 6058afe1e5..e210a76f8e 100644 --- a/components/hal/esp32s3/include/hal/spi_ll.h +++ b/components/hal/esp32s3/include/hal/spi_ll.h @@ -76,6 +76,21 @@ typedef enum { } spi_ll_trans_len_cond_t; FLAG_ATTR(spi_ll_trans_len_cond_t) +// SPI base command in esp32s3 +typedef enum { + /* Slave HD Only */ + SPI_LL_BASE_CMD_HD_WRBUF = 0x01, + SPI_LL_BASE_CMD_HD_RDBUF = 0x02, + SPI_LL_BASE_CMD_HD_WRDMA = 0x03, + SPI_LL_BASE_CMD_HD_RDDMA = 0x04, + SPI_LL_BASE_CMD_HD_SEG_END = 0x05, + SPI_LL_BASE_CMD_HD_EN_QPI = 0x06, + SPI_LL_BASE_CMD_HD_WR_END = 0x07, + SPI_LL_BASE_CMD_HD_INT0 = 0x08, + SPI_LL_BASE_CMD_HD_INT1 = 0x09, + SPI_LL_BASE_CMD_HD_INT2 = 0x0A, +} spi_ll_base_command_t; + /*------------------------------------------------------------------------------ * Control *----------------------------------------------------------------------------*/ @@ -1091,6 +1106,93 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) #undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK +/** + * Get the base spi command in esp32s3 + * + * @param cmd_t Command value + */ +static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) +{ + uint8_t cmd_base = 0x00; + switch (cmd_t) + { + case SPI_CMD_HD_WRBUF: + cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; + break; + case SPI_CMD_HD_RDBUF: + cmd_base = SPI_LL_BASE_CMD_HD_RDBUF; + break; + case SPI_CMD_HD_WRDMA: + cmd_base = SPI_LL_BASE_CMD_HD_WRDMA; + break; + case SPI_CMD_HD_RDDMA: + cmd_base = SPI_LL_BASE_CMD_HD_RDDMA; + break; + case SPI_CMD_HD_SEG_END: + cmd_base = SPI_LL_BASE_CMD_HD_SEG_END; + break; + case SPI_CMD_HD_EN_QPI: + cmd_base = SPI_LL_BASE_CMD_HD_EN_QPI; + break; + case SPI_CMD_HD_WR_END: + cmd_base = SPI_LL_BASE_CMD_HD_WR_END; + break; + case SPI_CMD_HD_INT0: + cmd_base = SPI_LL_BASE_CMD_HD_INT0; + break; + case SPI_CMD_HD_INT1: + cmd_base = SPI_LL_BASE_CMD_HD_INT1; + break; + case SPI_CMD_HD_INT2: + cmd_base = SPI_LL_BASE_CMD_HD_INT2; + break; + default: + HAL_ASSERT(cmd_base); + } + return cmd_base; +} + +/** + * Get the spi communication command + * + * @param cmd_t Base command value + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode) +{ + uint8_t cmd_base = spi_ll_get_slave_hd_base_command(cmd_t); + uint8_t cmd_mod = 0x00; //CMD:1-bit, ADDR:1-bit, DATA:1-bit + + if (line_mode.data_lines == 2) { + if (line_mode.addr_lines == 2) { + cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit + } else { + cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit + } + } else if (line_mode.data_lines == 4) { + if (line_mode.addr_lines == 4) { + cmd_mod = 0xA0; //CMD:1-bit, ADDR:4-bit, DATA:4-bit + } else { + cmd_mod = 0x20; //CMD:1-bit, ADDR:1-bit, DATA:4-bit + } + } + if (cmd_base == SPI_LL_BASE_CMD_HD_SEG_END || cmd_base == SPI_LL_BASE_CMD_HD_EN_QPI) { + cmd_mod = 0x00; + } + + return cmd_base | cmd_mod; +} + +/** + * Get the dummy bits + * + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode) +{ + return 8; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s3/include/hal/timer_ll.h b/components/hal/esp32s3/include/hal/timer_ll.h index a5f5f115a8..f6bebcceea 100644 --- a/components/hal/esp32s3/include/hal/timer_ll.h +++ b/components/hal/esp32s3/include/hal/timer_ll.h @@ -44,6 +44,22 @@ static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num, } } +/** + * @brief Enable Timer Group (GPTimer) module clock + * + * @note This function is not optional, created for backward compatible. + * + * @param hw Timer Group register base address + * @param timer_num Timer index in the group + * @param en true to enable, false to disable + */ +static inline void timer_ll_enable_clock(timg_dev_t *hw, uint32_t timer_num, bool en) +{ + (void)hw; + (void)timer_num; + (void)en; +} + /** * @brief Enable alarm event * @@ -115,6 +131,22 @@ static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, b hw->hw_timer[timer_num].config.tn_en = en; } +/** + * @brief Trigger software capture event + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + */ +__attribute__((always_inline)) +static inline void timer_ll_trigger_soft_capture(timg_dev_t *hw, uint32_t timer_num) +{ + hw->hw_timer[timer_num].update.tn_update = 1; + // Timer register is in a different clock domain from Timer hardware logic + // We need to wait for the update to take effect before fetching the count value + while (hw->hw_timer[timer_num].update.tn_update) { + } +} + /** * @brief Get counter value * @@ -126,11 +158,6 @@ static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, b __attribute__((always_inline)) static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer_num) { - hw->hw_timer[timer_num].update.tn_update = 1; - // Timer register is in a different clock domain from Timer hardware logic - // We need to wait for the update to take effect before fetching the count value - while (hw->hw_timer[timer_num].update.tn_update) { - } return ((uint64_t)hw->hw_timer[timer_num].hi.tn_hi << 32) | (hw->hw_timer[timer_num].lo.tn_lo); } diff --git a/components/hal/esp32s3/include/hal/uart_ll.h b/components/hal/esp32s3/include/hal/uart_ll.h index d1afedc577..261f0e9dd8 100644 --- a/components/hal/esp32s3/include/hal/uart_ll.h +++ b/components/hal/esp32s3/include/hal/uart_ll.h @@ -117,38 +117,18 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk) } } -/** - * @brief Get the UART source clock frequency. - * - * @param hw Beginning address of the peripheral registers. - * - * @return Current source clock frequency - */ -FORCE_INLINE_ATTR uint32_t uart_ll_get_sclk_freq(uart_dev_t *hw) -{ - switch (hw->clk_conf.sclk_sel) { - default: - case 1: - return APB_CLK_FREQ; - case 2: - return RTC_CLK_FREQ; - case 3: - return XTAL_CLK_FREQ; - } -} - /** * @brief Configure the baud-rate. * * @param hw Beginning address of the peripheral registers. * @param baud The baud rate to be set. + * @param sclk_freq Frequency of the clock source of UART, in Hz. * * @return None */ -FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud) +FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { #define DIV_UP(a, b) (((a) + (b) - 1) / (b)) - uint32_t sclk_freq = uart_ll_get_sclk_freq(hw); const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits int sclk_div = DIV_UP(sclk_freq, max_div * baud); @@ -165,12 +145,12 @@ FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud) * @brief Get the current baud-rate. * * @param hw Beginning address of the peripheral registers. + * @param sclk_freq Frequency of the clock source of UART, in Hz. * * @return The current baudrate */ -FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw) +FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq) { - uint32_t sclk_freq = uart_ll_get_sclk_freq(hw); uart_clkdiv_reg_t div_reg = hw->clkdiv; return ((sclk_freq << 4)) / (((div_reg.clkdiv << 4) | div_reg.clkdiv_frag) * (HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1)); diff --git a/components/hal/esp32s3/include/hal/usb_phy_ll.h b/components/hal/esp32s3/include/hal/usb_phy_ll.h index fc665552d8..acf6eed102 100644 --- a/components/hal/esp32s3/include/hal/usb_phy_ll.h +++ b/components/hal/esp32s3/include/hal/usb_phy_ll.h @@ -59,6 +59,8 @@ static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw) hw->conf0.phy_sel = 0; // Disable software control USB D+ D- pullup pulldown (Device FS: dp_pullup = 1) hw->conf0.pad_pull_override = 0; + // Enable USB D+ pullup + hw->conf0.dp_pullup = 1; // Enable USB pad function hw->conf0.usb_pad_enable = 1; // phy_sel is controlled by the following register value diff --git a/components/hal/i2c_hal.c b/components/hal/i2c_hal.c index 80d194bd94..7497cb206c 100644 --- a/components/hal/i2c_hal.c +++ b/components/hal/i2c_hal.c @@ -5,154 +5,12 @@ */ #include "hal/i2c_hal.h" - -void i2c_hal_txfifo_rst(i2c_hal_context_t *hal) -{ - i2c_ll_txfifo_rst(hal->dev); -} - -void i2c_hal_rxfifo_rst(i2c_hal_context_t *hal) -{ - i2c_ll_rxfifo_rst(hal->dev); -} - -void i2c_hal_set_data_mode(i2c_hal_context_t *hal, i2c_trans_mode_t tx_mode, i2c_trans_mode_t rx_mode) -{ - i2c_ll_set_data_mode(hal->dev, tx_mode, rx_mode); -} - -void i2c_hal_get_data_mode(i2c_hal_context_t *hal, i2c_trans_mode_t *tx_mode, i2c_trans_mode_t *rx_mode) -{ - i2c_ll_get_data_mode(hal->dev, tx_mode, rx_mode); -} - -void i2c_hal_set_filter(i2c_hal_context_t *hal, uint8_t filter_num) -{ - i2c_ll_set_filter(hal->dev, filter_num); -} - -void i2c_hal_get_filter(i2c_hal_context_t *hal, uint8_t *filter_num) -{ - *filter_num = i2c_ll_get_filter(hal->dev); -} - -void i2c_hal_set_scl_timing(i2c_hal_context_t *hal, int hight_period, int low_period) -{ - i2c_ll_set_scl_timing(hal->dev, hight_period, low_period); -} - -void i2c_hal_clr_intsts_mask(i2c_hal_context_t *hal, uint32_t mask) -{ - i2c_ll_clr_intsts_mask(hal->dev, mask); -} - -void i2c_hal_enable_intr_mask(i2c_hal_context_t *hal, uint32_t mask) -{ - i2c_ll_enable_intr_mask(hal->dev, mask); -} - -void i2c_hal_disable_intr_mask(i2c_hal_context_t *hal, uint32_t mask) -{ - i2c_ll_disable_intr_mask(hal->dev, mask); -} - -void i2c_hal_get_intsts_mask(i2c_hal_context_t *hal, uint32_t *mask) -{ - *mask = i2c_ll_get_intsts_mask(hal->dev); -} - -void i2c_hal_set_fifo_mode(i2c_hal_context_t *hal, bool fifo_mode_en) -{ - i2c_ll_set_fifo_mode(hal->dev, fifo_mode_en); -} - -void i2c_hal_set_tout(i2c_hal_context_t *hal, int tout_num) -{ - i2c_ll_set_tout(hal->dev, tout_num); -} - -void i2c_hal_set_stop_timing(i2c_hal_context_t *hal, int stop_setup, int stop_hold) -{ - i2c_ll_set_stop_timing(hal->dev, stop_setup, stop_hold); -} - -void i2c_hal_set_start_timing(i2c_hal_context_t *hal, int start_setup, int start_hold) -{ - i2c_ll_set_start_timing(hal->dev, start_setup, start_hold); -} - -void i2c_hal_set_sda_timing(i2c_hal_context_t *hal, int sda_sample, int sda_hold) -{ - i2c_ll_set_sda_timing(hal->dev, sda_sample, sda_hold); -} - -void i2c_hal_set_txfifo_empty_thr(i2c_hal_context_t *hal, uint8_t empty_thr) -{ - i2c_ll_set_txfifo_empty_thr(hal->dev, empty_thr); -} - -void i2c_hal_set_rxfifo_full_thr(i2c_hal_context_t *hal, uint8_t full_thr) -{ - i2c_ll_set_rxfifo_full_thr(hal->dev, full_thr); -} - -bool i2c_hal_is_bus_busy(i2c_hal_context_t *hal) -{ - return i2c_ll_is_bus_busy(hal->dev); -} - -void i2c_hal_get_sda_timing(i2c_hal_context_t *hal, int *sample_time, int *hold_time) -{ - i2c_ll_get_sda_timing(hal->dev, sample_time, hold_time); -} - -void i2c_hal_get_tout(i2c_hal_context_t *hal, int *tout_val) -{ - *tout_val = i2c_ll_get_tout(hal->dev); -} - -void i2c_hal_get_start_timing(i2c_hal_context_t *hal, int *setup_time, int *hold_time) -{ - i2c_ll_get_start_timing(hal->dev, setup_time, hold_time); -} - -void i2c_hal_get_stop_timing(i2c_hal_context_t *hal, int *setup_time, int *hold_time) -{ - i2c_ll_get_stop_timing(hal->dev, setup_time, hold_time); -} - -void i2c_hal_get_scl_timing(i2c_hal_context_t *hal, int *high_period, int *low_period) -{ - i2c_ll_get_scl_timing(hal->dev, high_period, low_period); -} - -bool i2c_hal_is_master_mode(i2c_hal_context_t *hal) -{ - return i2c_ll_is_master_mode(hal->dev); -} +#include "hal/i2c_ll.h" +#include "hal/i2c_types.h" #if SOC_I2C_SUPPORT_SLAVE -void i2c_hal_set_slave_addr(i2c_hal_context_t *hal, uint16_t slave_addr, bool addr_10bit_en) -{ - i2c_ll_set_slave_addr(hal->dev, slave_addr, addr_10bit_en); -} -void i2c_hal_enable_slave_tx_it(i2c_hal_context_t *hal) -{ - i2c_ll_slave_enable_tx_it(hal->dev); -} - -void i2c_hal_enable_slave_rx_it(i2c_hal_context_t *hal) -{ - i2c_ll_slave_enable_rx_it(hal->dev); -} - -void i2c_hal_disable_slave_rx_it(i2c_hal_context_t *hal) -{ - i2c_ll_slave_disable_rx_it(hal->dev); -} - -void i2c_hal_slave_init(i2c_hal_context_t *hal, int i2c_num) +void i2c_hal_slave_init(i2c_hal_context_t *hal) { i2c_ll_slave_init(hal->dev); //Use fifo mode @@ -168,24 +26,18 @@ void i2c_hal_slave_init(i2c_hal_context_t *hal, int i2c_num) void i2c_hal_set_bus_timing(i2c_hal_context_t *hal, int scl_freq, i2c_clock_source_t src_clk, int source_freq) { i2c_ll_set_source_clk(hal->dev, src_clk); - i2c_clk_cal_t clk_cal = {0}; + i2c_hal_clk_config_t clk_cal = {0}; i2c_ll_cal_bus_clk(source_freq, scl_freq, &clk_cal); i2c_ll_set_bus_timing(hal->dev, &clk_cal); } -void i2c_hal_master_clr_bus(i2c_hal_context_t *hal) -{ - i2c_ll_master_clr_bus(hal->dev); -} - void i2c_hal_master_fsm_rst(i2c_hal_context_t *hal) { i2c_ll_master_fsm_rst(hal->dev); } -void i2c_hal_master_init(i2c_hal_context_t *hal, int i2c_num) +void i2c_hal_master_init(i2c_hal_context_t *hal) { - hal->version = i2c_ll_get_hw_version(hal->dev); i2c_ll_master_init(hal->dev); //Use fifo mode i2c_ll_set_fifo_mode(hal->dev, true); @@ -195,3 +47,32 @@ void i2c_hal_master_init(i2c_hal_context_t *hal, int i2c_num) i2c_ll_txfifo_rst(hal->dev); i2c_ll_rxfifo_rst(hal->dev); } + +void i2c_hal_init(i2c_hal_context_t *hal, int i2c_port) +{ + hal->dev = I2C_LL_GET_HW(i2c_port); +} + +void i2c_hal_master_trans_start(i2c_hal_context_t *hal) +{ + i2c_ll_update(hal->dev); + i2c_ll_trans_start(hal->dev); +} + +void i2c_hal_get_timing_config(i2c_hal_context_t *hal, i2c_hal_timing_config_t *timing_config) +{ + i2c_ll_get_scl_clk_timing(hal->dev, &timing_config->high_period, &timing_config->low_period, &timing_config->wait_high_period); + i2c_ll_get_start_timing(hal->dev, &timing_config->rstart_setup, &timing_config->start_hold); + i2c_ll_get_stop_timing(hal->dev, &timing_config->stop_setup, &timing_config->stop_hold); + i2c_ll_get_sda_timing(hal->dev, &timing_config->sda_sample, &timing_config->sda_hold); + i2c_ll_get_tout(hal->dev, &timing_config->timeout); +} + +void i2c_hal_set_timing_config(i2c_hal_context_t *hal, i2c_hal_timing_config_t *timing_config) +{ + i2c_ll_set_scl_clk_timing(hal->dev, timing_config->high_period, timing_config->low_period, timing_config->wait_high_period); + i2c_ll_set_start_timing(hal->dev, timing_config->rstart_setup, timing_config->start_hold); + i2c_ll_set_stop_timing(hal->dev, timing_config->stop_setup, timing_config->stop_hold); + i2c_ll_set_sda_timing(hal->dev, timing_config->sda_sample, timing_config->sda_hold); + i2c_ll_set_tout(hal->dev, timing_config->timeout); +} diff --git a/components/hal/i2c_hal_iram.c b/components/hal/i2c_hal_iram.c index 303fda4546..d2d7e97e02 100644 --- a/components/hal/i2c_hal_iram.c +++ b/components/hal/i2c_hal_iram.c @@ -6,57 +6,41 @@ #include "hal/i2c_hal.h" + +//////////////////////////////////////////Deprecated Functions////////////////////////////////////////////////////////// +/////////////////////////////The following functions are only used by the legacy driver///////////////////////////////// +/////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + void i2c_hal_master_handle_tx_event(i2c_hal_context_t *hal, i2c_intr_event_t *event) { - if (i2c_ll_get_intsts_mask(hal->dev) != 0) { + uint32_t intr_status = 0; + i2c_ll_get_intr_mask(hal->dev, &intr_status); + if (intr_status != 0) { // If intr status is 0, no need to handle it. i2c_ll_master_get_event(hal->dev, event); if ((*event < I2C_INTR_EVENT_END_DET) || (*event == I2C_INTR_EVENT_TRANS_DONE)) { i2c_ll_master_disable_tx_it(hal->dev); - i2c_ll_master_clr_tx_it(hal->dev); + i2c_ll_clear_intr_mask(hal->dev, intr_status); } else if (*event == I2C_INTR_EVENT_END_DET) { - i2c_ll_master_clr_tx_it(hal->dev); + i2c_ll_clear_intr_mask(hal->dev, intr_status); } } } void i2c_hal_master_handle_rx_event(i2c_hal_context_t *hal, i2c_intr_event_t *event) { - if (i2c_ll_get_intsts_mask(hal->dev) != 0) { + uint32_t intr_status = 0; + i2c_ll_get_intr_mask(hal->dev, &intr_status); + if (intr_status != 0) { i2c_ll_master_get_event(hal->dev, event); if ((*event < I2C_INTR_EVENT_END_DET) || (*event == I2C_INTR_EVENT_TRANS_DONE)) { i2c_ll_master_disable_rx_it(hal->dev); - i2c_ll_master_clr_rx_it(hal->dev); + i2c_ll_clear_intr_mask(hal->dev, intr_status); } else if (*event == I2C_INTR_EVENT_END_DET) { - i2c_ll_master_clr_rx_it(hal->dev); + i2c_ll_clear_intr_mask(hal->dev, intr_status); } } } -#if SOC_I2C_SUPPORT_SLAVE -void i2c_hal_slave_handle_event(i2c_hal_context_t *hal, i2c_intr_event_t *event) -{ - i2c_ll_slave_get_event(hal->dev, event); -} - -void i2c_hal_disable_slave_tx_it(i2c_hal_context_t *hal) -{ - i2c_ll_slave_disable_tx_it(hal->dev); -} -#endif // SOC_I2C_SUPPORT_SLAVE - -void i2c_hal_update_config(i2c_hal_context_t *hal) -{ - i2c_ll_update(hal->dev); -} - -void i2c_hal_get_rxfifo_cnt(i2c_hal_context_t *hal, uint32_t *len) -{ - *len = i2c_ll_get_rxfifo_cnt(hal->dev); -} - -void i2c_hal_get_txfifo_cnt(i2c_hal_context_t *hal, uint32_t *len) -{ - *len = i2c_ll_get_txfifo_len(hal->dev); -} diff --git a/components/hal/include/hal/adc_types.h b/components/hal/include/hal/adc_types.h index fd27771223..785ea76c97 100644 --- a/components/hal/include/hal/adc_types.h +++ b/components/hal/include/hal/adc_types.h @@ -55,8 +55,9 @@ typedef enum { } adc_bitwidth_t; typedef enum { - ADC_ULP_MODE_FSM = 1, ///< ADC is controlled by ULP FSM - ADC_ULP_MODE_RISCV = 2, ///< ADC is controlled by ULP RISCV + ADC_ULP_MODE_DISABLE = 0, ///< ADC ULP mode is disabled + ADC_ULP_MODE_FSM = 1, ///< ADC is controlled by ULP FSM + ADC_ULP_MODE_RISCV = 2, ///< ADC is controlled by ULP RISCV } adc_ulp_mode_t; /** diff --git a/components/hal/include/hal/gpio_hal.h b/components/hal/include/hal/gpio_hal.h index 78c4d92424..2c9c08bfa9 100644 --- a/components/hal/include/hal/gpio_hal.h +++ b/components/hal/include/hal/gpio_hal.h @@ -95,20 +95,13 @@ typedef struct { #define gpio_hal_get_intr_status_high(hal, core_id, status) gpio_ll_get_intr_status_high((hal)->dev, core_id, status) /** - * @brief Clear GPIO interrupt status - * - * @param hal Context of the HAL layer - * @param mask interrupt status clear mask - */ -#define gpio_hal_clear_intr_status(hal, mask) gpio_ll_clear_intr_status((hal)->dev, mask) - -/** - * @brief Clear GPIO interrupt status high - * - * @param hal Context of the HAL layer - * @param mask interrupt status high clear mask - */ -#define gpio_hal_clear_intr_status_high(hal, mask) gpio_ll_clear_intr_status_high((hal)->dev, mask) + * @brief Clear GPIO interrupt status bit + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number. If you want to clear the interrupt status bit of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + */ +#define gpio_hal_clear_intr_status_bit(hal, gpio_num) (((gpio_num) < 32) ? gpio_ll_clear_intr_status((hal)->dev, 1 << gpio_num) \ + : gpio_ll_clear_intr_status_high((hal)->dev, 1 << (gpio_num - 32))) /** * @brief Enable GPIO module interrupt signal @@ -175,6 +168,15 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num); */ #define gpio_hal_od_enable(hal, gpio_num) gpio_ll_od_enable((hal)->dev, gpio_num) +/** + * @brief Select a function for the pin in the IOMUX + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + * @param func Function to assign to the pin + */ +#define gpio_hal_func_sel(hal, gpio_num, func) gpio_ll_func_sel((hal)->dev, gpio_num, func) + /** * @brief GPIO set output level * @@ -267,6 +269,22 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num); */ #define gpio_hal_hold_dis(hal, gpio_num) gpio_ll_hold_dis((hal)->dev, gpio_num) +/** + * @brief Get wether digital gpio pad is held + * + * @param hal Context of the HAL layer + * @param gpio_num GPIO number, only support output GPIOs + * + * @note digital io means io pad powered by VDD3P3_CPU or VDD_SPI + * rtc io means io pad powered by VDD3P3_RTC + * caller must ensure that gpio_num is a digital io pad + * + * @return + * - true digital gpio pad is held + * - false digital gpio pad is unheld + */ +#define gpio_hal_is_digital_io_hold(hal, gpio_num) gpio_ll_is_digital_io_hold((hal)->dev, gpio_num) + /** * @brief Enable all digital gpio pad hold function during Deep-sleep. * @@ -287,6 +305,17 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num); */ #define gpio_hal_deep_sleep_hold_dis(hal) gpio_ll_deep_sleep_hold_dis((hal)->dev) +/** + * @brief Get whether all digital gpio pad hold function during Deep-sleep is enabled. + * + * @param hal Context of the HAL layer + * + * @return + * - true deep sleep hold is enabled + * - false deep sleep hold is disabled + */ +#define gpio_hal_deep_sleep_hold_is_en(hal) gpio_ll_deep_sleep_hold_is_en((hal)->dev) + /** * @brief Set pad input to a peripheral signal through the IOMUX. * @@ -309,13 +338,13 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num); #if SOC_GPIO_SUPPORT_FORCE_HOLD /** - * @brief Force hold digital and rtc gpio pad. + * @brief Force hold digital gpio pad. * @note GPIO force hold, whether the chip in sleep mode or wakeup mode. */ #define gpio_hal_force_hold_all() gpio_ll_force_hold_all() /** - * @brief Force unhold digital and rtc gpio pad. + * @brief Force unhold digital gpio pad. * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode. */ #define gpio_hal_force_unhold_all() gpio_ll_force_unhold_all() diff --git a/components/hal/include/hal/gpio_types.h b/components/hal/include/hal/gpio_types.h index dbc2208a07..c1aa6f4a2b 100644 --- a/components/hal/include/hal/gpio_types.h +++ b/components/hal/include/hal/gpio_types.h @@ -348,6 +348,43 @@ typedef enum { GPIO_NUM_MAX, /** @endcond */ } gpio_num_t; +#elif CONFIG_IDF_TARGET_ESP32C6 +typedef enum { + GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */ + GPIO_NUM_0 = 0, /*!< GPIO0, input and output */ + GPIO_NUM_1 = 1, /*!< GPIO1, input and output */ + GPIO_NUM_2 = 2, /*!< GPIO2, input and output */ + GPIO_NUM_3 = 3, /*!< GPIO3, input and output */ + GPIO_NUM_4 = 4, /*!< GPIO4, input and output */ + GPIO_NUM_5 = 5, /*!< GPIO5, input and output */ + GPIO_NUM_6 = 6, /*!< GPIO6, input and output */ + GPIO_NUM_7 = 7, /*!< GPIO7, input and output */ + GPIO_NUM_8 = 8, /*!< GPIO8, input and output */ + GPIO_NUM_9 = 9, /*!< GPIO9, input and output */ + GPIO_NUM_10 = 10, /*!< GPIO10, input and output */ + GPIO_NUM_11 = 11, /*!< GPIO11, input and output */ + GPIO_NUM_12 = 12, /*!< GPIO12, input and output */ + GPIO_NUM_13 = 13, /*!< GPIO13, input and output */ + GPIO_NUM_14 = 14, /*!< GPIO14, input and output */ + GPIO_NUM_15 = 15, /*!< GPIO15, input and output */ + GPIO_NUM_16 = 16, /*!< GPIO16, input and output */ + GPIO_NUM_17 = 17, /*!< GPIO17, input and output */ + GPIO_NUM_18 = 18, /*!< GPIO18, input and output */ + GPIO_NUM_19 = 19, /*!< GPIO19, input and output */ + GPIO_NUM_20 = 20, /*!< GPIO20, input and output */ + GPIO_NUM_21 = 21, /*!< GPIO21, input and output */ + GPIO_NUM_22 = 22, /*!< GPIO22, input and output */ + GPIO_NUM_23 = 23, /*!< GPIO23, input and output */ + GPIO_NUM_24 = 24, /*!< GPIO24, input and output */ + GPIO_NUM_25 = 25, /*!< GPIO25, input and output */ + GPIO_NUM_26 = 26, /*!< GPIO26, input and output */ + GPIO_NUM_27 = 27, /*!< GPIO27, input and output */ + GPIO_NUM_28 = 28, /*!< GPIO28, input and output */ + GPIO_NUM_29 = 29, /*!< GPIO29, input and output */ + GPIO_NUM_30 = 30, /*!< GPIO30, input and output */ + GPIO_NUM_MAX, +/** @endcond */ +} gpio_num_t; #endif typedef enum { @@ -386,17 +423,6 @@ typedef enum { GPIO_PULLDOWN_ENABLE = 0x1, /*!< Enable GPIO pull-down resistor */ } gpio_pulldown_t; -/** - * @brief Configuration parameters of GPIO pad for gpio_config function - */ -typedef struct { - uint64_t pin_bit_mask; /*!< GPIO pin: set with bit mask, each bit maps to a GPIO */ - gpio_mode_t mode; /*!< GPIO mode: set input/output mode */ - gpio_pullup_t pull_up_en; /*!< GPIO pull-up */ - gpio_pulldown_t pull_down_en; /*!< GPIO pull-down */ - gpio_int_type_t intr_type; /*!< GPIO interrupt type */ -} gpio_config_t; - typedef enum { GPIO_PULLUP_ONLY, /*!< Pad pull up */ GPIO_PULLDOWN_ONLY, /*!< Pad pull down */ @@ -413,8 +439,6 @@ typedef enum { GPIO_DRIVE_CAP_MAX, } gpio_drive_cap_t; -typedef void (*gpio_isr_t)(void *); - #ifdef __cplusplus } #endif diff --git a/components/hal/include/hal/i2c_hal.h b/components/hal/include/hal/i2c_hal.h index 9ec37d3150..2f3df91b10 100644 --- a/components/hal/include/hal/i2c_hal.h +++ b/components/hal/include/hal/i2c_hal.h @@ -13,95 +13,22 @@ // The HAL layer for I2C #pragma once + #include "hal/i2c_ll.h" #include "hal/i2c_types.h" +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief I2C hal Context definition */ typedef struct { i2c_dev_t *dev; - uint32_t version; } i2c_hal_context_t; -/** - * @brief Write the I2C rxfifo with the given length - * - * @param hal Context of the HAL layer - * @param wr_data Pointer to data buffer - * @param wr_size Amount of data needs write - * - * @return None - */ -#define i2c_hal_write_txfifo(hal,wr_data,wr_size) i2c_ll_write_txfifo((hal)->dev,wr_data,wr_size) - -/** - * @brief Read the I2C rxfifo with the given length - * - * @param hal Context of the HAL layer - * @param buf Pointer to data buffer - * @param rd_size Amount of data needs read - * - * @return None - */ -#define i2c_hal_read_rxfifo(hal,buf,rd_size) i2c_ll_read_rxfifo((hal)->dev,buf,rd_size) - -/** - * @brief Write I2C cmd register - * - * @param hal Context of the HAL layer - * @param cmd I2C hardware command - * @param cmd_idx The index of the command register, should be less than 16 - * - * @return None - */ -#define i2c_hal_write_cmd_reg(hal,cmd, cmd_idx) i2c_ll_write_cmd_reg((hal)->dev,cmd,cmd_idx) - -/** - * @brief Configure the I2C to triger a transaction - * - * @param hal Context of the HAL layer - * - * @return None - */ -#define i2c_hal_trans_start(hal) i2c_ll_trans_start((hal)->dev) - -/** - * @brief Enable I2C master RX interrupt - * - * @param hal Context of the HAL layer - * - * @return None - */ -#define i2c_hal_enable_master_rx_it(hal) i2c_ll_master_enable_rx_it((hal)->dev) - -/** - * @brief Enable I2C master TX interrupt - * - * @param hal Context of the HAL layer - * - * @return None - */ -#define i2c_hal_enable_master_tx_it(hal) i2c_ll_master_enable_tx_it((hal)->dev) - #if SOC_I2C_SUPPORT_SLAVE -/** - * @brief Clear I2C slave TX interrupt - * - * @param hal Context of the HAL layer - * - * @return None - */ -#define i2c_hal_slave_clr_tx_it(hal) i2c_ll_slave_clr_tx_it((hal)->dev) - -/** - * @brief Clear I2C slave RX interrupt - * - * @param hal Context of the HAL layer - * - * @return None - */ -#define i2c_hal_slave_clr_rx_it(hal) i2c_ll_slave_clr_rx_it((hal)->dev) /** * @brief Init the I2C slave. @@ -111,100 +38,10 @@ typedef struct { * * @return None */ -void i2c_hal_slave_init(i2c_hal_context_t *hal, i2c_port_t i2c_num); +void i2c_hal_slave_init(i2c_hal_context_t *hal); -/** - * @brief Configure the I2C slave address - * - * @param hal Context of the HAL layer - * @param slave_addr Slave address - * @param addr_10bit_en Set true to enable 10-bit slave address mode, Set false to enable 7-bit address mode - * - * @return None - */ -void i2c_hal_set_slave_addr(i2c_hal_context_t *hal, uint16_t slave_addr, bool addr_10bit_en); - - -/** - * @brief Enable I2C slave TX interrupt - * - * @param hal Context of the HAL layer - * - * @return None - */ -void i2c_hal_enable_slave_tx_it(i2c_hal_context_t *hal); - -/** - * @brief Disable I2C slave TX interrupt - * - * @param hal Context of the HAL layer - * - * @return None - */ -void i2c_hal_disable_slave_tx_it(i2c_hal_context_t *hal); - -/** - * @brief Enable I2C slave RX interrupt - * - * @param hal Context of the HAL layer - * - * @return None - */ -void i2c_hal_enable_slave_rx_it(i2c_hal_context_t *hal); - -/** - * @brief Disable I2C slave RX interrupt - * - * @param hal Context of the HAL layer - * - * @return None - */ -void i2c_hal_disable_slave_rx_it(i2c_hal_context_t *hal); - -/** - * @brief I2C slave handle interrupt event - * - * @param hal Context of the HAL layer - * @param event Pointer to accept the interrupt event - * - * @return None - */ -void i2c_hal_slave_handle_event(i2c_hal_context_t *hal, i2c_intr_event_t *event); #endif // SOC_I2C_SUPPORT_SLAVE -/** - * @brief Set the source clock. This function is meant to be used in - * slave mode, in order to select a source clock abe to handle - * the expected SCL frequency. - * - * @param hal Context of the HAL layer - * @param src_clk Source clock to use choosen from `i2c_clock_source_t` type - */ -#define i2c_hal_set_source_clk(hal, src_clk) i2c_ll_set_source_clk((hal)->dev, src_clk) - -/** - * @brief Configure I2C SCL timing - * - * @param hw Beginning address of the peripheral registers - * @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2) - * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) - * @param wait_high_period The I2C SCL wait rising edge period. - * - * @return None. - */ -#define i2c_hal_set_scl_clk_timing(hal, high_period, low_period, wait_high_period) i2c_ll_set_scl_clk_timing((hal)->dev, high_period, low_period, wait_high_period) - -/** - * @brief Get I2C SCL timing configuration - * - * @param hw Beginning address of the peripheral registers - * @param high_period Pointer to accept the SCL high period - * @param low_period Pointer to accept the SCL low period - * - * @return None - */ -#define i2c_hal_get_scl_clk_timing(hal, high_period, low_period, wait_high_period) i2c_ll_get_scl_clk_timing((hal)->dev, high_period, low_period, wait_high_period) - /** * @brief Init the I2C master. * @@ -213,273 +50,7 @@ void i2c_hal_slave_handle_event(i2c_hal_context_t *hal, i2c_intr_event_t *event) * * @return None */ -void i2c_hal_master_init(i2c_hal_context_t *hal, i2c_port_t i2c_num); - -/** - * @brief Reset the I2C hw txfifo - * - * @param hal Context of the HAL layer - * - * @return None - */ -void i2c_hal_txfifo_rst(i2c_hal_context_t *hal); - -/** - * @brief Reset the I2C hw rxfifo - * - * @param hal Context of the HAL layer - * - * @return None - */ -void i2c_hal_rxfifo_rst(i2c_hal_context_t *hal); - -/** - * @brief Configure the I2C data MSB bit shifted first or LSB bit shifted first. - * - * @param hal Context of the HAL layer - * @param tx_mode Data format of TX - * @param rx_mode Data format of RX - * - * @return None - */ -void i2c_hal_set_data_mode(i2c_hal_context_t *hal, i2c_trans_mode_t tx_mode, i2c_trans_mode_t rx_mode); - -/** - * @brief Configure the I2C hardware filter function. - * - * @param hal Context of the HAL layer - * @param filter_num If the glitch period on the line is less than this value(in APB cycle), it will be filtered out - * If `filter_num == 0`, the filter will be disabled - * - * @return None - */ -void i2c_hal_set_filter(i2c_hal_context_t *hal, uint8_t filter_num); - -/** - * @brief Get the I2C hardware filter configuration - * - * @param hal Context of the HAL layer - * @param filter_num Pointer to accept the hardware filter configuration - * - * @return None - */ -void i2c_hal_get_filter(i2c_hal_context_t *hal, uint8_t *filter_num); - -/** - * @brief Configure the I2C SCL timing - * - * @param hal Context of the HAL layer - * @param hight_period SCL high period - * @param low_period SCL low period - * - * @return None - */ -void i2c_hal_set_scl_timing(i2c_hal_context_t *hal, int hight_period, int low_period); - -/** - * @brief Configure the I2C master SCL frequency - * - * @param hal Context of the HAL layer - * @param src_clk The I2C Source clock frequency - * @param scl_freq The SCL frequency to be set - * - * @return None - */ -void i2c_hal_set_scl_freq(i2c_hal_context_t *hal, uint32_t src_clk, uint32_t scl_freq); - -/** - * @brief Clear the I2C interrupt status with the given mask - * - * @param hal Context of the HAL layer - * @param mask The interrupt bitmap needs to be clearned - * - * @return None - */ -void i2c_hal_clr_intsts_mask(i2c_hal_context_t *hal, uint32_t mask); - -/** - * @brief Enable the I2C interrupt with the given mask - * - * @param hal Context of the HAL layer - * @param mask The interrupt bitmap needs to be enabled - * - * @return None - */ -void i2c_hal_enable_intr_mask(i2c_hal_context_t *hal, uint32_t mask); - -/** - * @brief Disable the I2C interrupt with the given mask - * - * @param hal Context of the HAL layer - * @param mask The interrupt bitmap needs to be disabled - * - * @return None - */ -void i2c_hal_disable_intr_mask(i2c_hal_context_t *hal, uint32_t mask); - -/** - * @brief Configure the I2C memory access mode, FIFO mode or none FIFO mode - * - * @param hal Context of the HAL layer - * @param fifo_mode_en Set true to enable FIFO access mode, else set it false - * - * @return None - */ -void i2c_hal_set_fifo_mode(i2c_hal_context_t *hal, bool fifo_mode_en); - -/** - * @brief Configure the I2C timeout value - * - * @param hal Context of the HAL layer - * @param tout_val the timeout value to be set - * - * @return None - */ -void i2c_hal_set_tout(i2c_hal_context_t *hal, int tout_val); - -/** - * @brief Get the I2C time out configuration - * - * @param tout_val Pointer to accept the timeout configuration - * - * @return None - */ -void i2c_hal_get_tout(i2c_hal_context_t *hal, int *tout_val); - -/** - * @brief Configure the I2C stop timing - * - * @param hal Context of the HAL layer - * @param stop_setup The stop condition setup period (in APB cycle) - * @param stop_hold The stop condition hold period (in APB cycle) - * - * @return None - */ -void i2c_hal_set_stop_timing(i2c_hal_context_t *hal, int stop_setup, int stop_hold); - -/** - * @brief Configure the I2C start timing - * - * @param hal Context of the HAL layer - * @param start_setup The start condition setup period (in APB cycle) - * @param start_hold The start condition hold period (in APB cycle) - * - * @return None - */ -void i2c_hal_set_start_timing(i2c_hal_context_t *hal, int start_setup, int start_hold); - -/** - * @brief Configure the I2C sda sample timing - * - * @param hal Context of the HAL layer - * @param sda_sample The SDA sample time (in APB cycle) - * @param sda_hold The SDA hold time (in APB cycle) - * - * @return None - */ -void i2c_hal_set_sda_timing(i2c_hal_context_t *hal, int sda_sample, int sda_hold); - -/** - * @brief Configure the I2C txfifo empty threshold value - * - * @param hal Context of the HAL layer. - * @param empty_thr TxFIFO empty threshold value - * - * @return None - */ -void i2c_hal_set_txfifo_empty_thr(i2c_hal_context_t *hal, uint8_t empty_thr); - -/** - * @brief Configure the I2C rxfifo full threshold value - * - * @param hal Context of the HAL layer - * @param full_thr RxFIFO full threshold value - * - * @return None - */ -void i2c_hal_set_rxfifo_full_thr(i2c_hal_context_t *hal, uint8_t full_thr); - -/** - * @brief Get the I2C interrupt status - * - * @param hal Context of the HAL layer - * @param mask Pointer to accept the interrupt status - * - * @return None - */ -void i2c_hal_get_intsts_mask(i2c_hal_context_t *hal, uint32_t *mask); - -/** - * @brief Check if the I2C bus is busy - * - * @param hal Context of the HAL layer - * - * @return True if the bus is busy, otherwise, fale will be returned - */ -bool i2c_hal_is_bus_busy(i2c_hal_context_t *hal); - -/** - * @brief Get the I2C sda sample timing configuration - * - * @param hal Context of the HAL layer - * @param sample_time Pointer to accept the SDA sample time - * @param hold_time Pointer to accept the SDA hold time - * - * @return None - */ -void i2c_hal_get_sda_timing(i2c_hal_context_t *hal, int *sample_time, int *hold_time); - -/** - * @brief Get the I2C stop timing configuration - * - * @param hal Context of the HAL layer - * @param setup_time Pointer to accept the stop condition setup period - * @param hold_time Pointer to accept the stop condition hold period - * - * @return None - */ -void i2c_hal_get_stop_timing(i2c_hal_context_t *hal, int *setup_time, int *hold_time); - -/** - * @brief Get the I2C scl timing configuration - * - * @param hal Context of the HAL layer - * @param high_period Pointer to accept the scl high period - * @param low_period Pointer to accept the scl low period - * - * @return None - */ -void i2c_hal_get_scl_timing(i2c_hal_context_t *hal, int *high_period, int *low_period); - -/** - * @brief Get the I2C start timing configuration - * - * @param hal Context of the HAL layer - * @param setup_time Pointer to accept the start condition setup period - * @param hold_time Pointer to accept the start condition hold period - * - * @return None - */ -void i2c_hal_get_start_timing(i2c_hal_context_t *hal, int *setup_time, int *hold_time); - -/** - * @brief Check if the I2C is master mode - * - * @param hal Context of the HAL layer - * - * @return True if in master mode, otherwise, false will be returned - */ -bool i2c_hal_is_master_mode(i2c_hal_context_t *hal); - -/** - * @brief Get the rxFIFO readable length - * - * @param hal Context of the HAL layer - * @param len Pointer to accept the rxFIFO readable length - * - * @return None - */ -void i2c_hal_get_rxfifo_cnt(i2c_hal_context_t *hal, uint32_t *len); +void i2c_hal_master_init(i2c_hal_context_t *hal); /** * @brief Set I2C bus timing with the given frequency @@ -493,27 +64,6 @@ void i2c_hal_get_rxfifo_cnt(i2c_hal_context_t *hal, uint32_t *len); */ void i2c_hal_set_bus_timing(i2c_hal_context_t *hal, int scl_freq, i2c_clock_source_t src_clk, int source_freq); -/** - * @brief Get I2C txFIFO writeable length - * - * @param hal Context of the HAL layer - * @param len Pointer to accept the txFIFO writeable length - * - * @return None - */ -void i2c_hal_get_txfifo_cnt(i2c_hal_context_t *hal, uint32_t *len); - -/** - * @brief Check if the I2C is master mode - * - * @param hal Context of the HAL layer - * @param tx_mode Pointer to accept the TX data mode - * @param rx_mode Pointer to accept the RX data mode - * - * @return None - */ -void i2c_hal_get_data_mode(i2c_hal_context_t *hal, i2c_trans_mode_t *tx_mode, i2c_trans_mode_t *rx_mode); - /** * @brief I2C hardware FSM reset * @@ -523,15 +73,6 @@ void i2c_hal_get_data_mode(i2c_hal_context_t *hal, i2c_trans_mode_t *tx_mode, i2 */ void i2c_hal_master_fsm_rst(i2c_hal_context_t *hal); -/** - * @brief @brief Clear I2C bus - * - * @param hal Context of the HAL layer - * - * @return None - */ -void i2c_hal_master_clr_bus(i2c_hal_context_t *hal); - /** * @brief I2C master handle tx interrupt event * @@ -553,11 +94,36 @@ void i2c_hal_master_handle_tx_event(i2c_hal_context_t *hal, i2c_intr_event_t *ev void i2c_hal_master_handle_rx_event(i2c_hal_context_t *hal, i2c_intr_event_t *event); /** - * @brief Synchronize I2C status - * - * @param hal Context of the HAL layer - * - * @return None + * @brief Init I2C hal layer * + * @param hal Context of the HAL + * @param i2c_port I2C port number. */ -void i2c_hal_update_config(i2c_hal_context_t *hal); +void i2c_hal_init(i2c_hal_context_t *hal, int i2c_port); + +/** + * @brief Start I2C master transaction + * + * @param hal Context of the HAL + */ +void i2c_hal_master_trans_start(i2c_hal_context_t *hal); + +/** + * @brief Get timing configuration + * + * @param hal Context of the HAL + * @param timing_config Pointer to timing config structure. + */ +void i2c_hal_get_timing_config(i2c_hal_context_t *hal, i2c_hal_timing_config_t *timing_config); + +/** + * @brief Set timing configuration + * + * @param hal Context of the HAL + * @param timing_config Timing config structure. + */ +void i2c_hal_set_timing_config(i2c_hal_context_t *hal, i2c_hal_timing_config_t *timing_config); + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/include/hal/i2c_types.h b/components/hal/include/hal/i2c_types.h index 35bddc7511..c5878737c0 100644 --- a/components/hal/include/hal/i2c_types.h +++ b/components/hal/include/hal/i2c_types.h @@ -18,7 +18,28 @@ extern "C" { /** * @brief I2C port number, can be I2C_NUM_0 ~ (I2C_NUM_MAX-1). */ -typedef int i2c_port_t; +typedef enum { + I2C_NUM_0 = 0, /*!< I2C port 0 */ +#if SOC_I2C_NUM >= 2 + I2C_NUM_1, /*!< I2C port 1 */ +#endif + I2C_NUM_MAX, /*!< I2C port max */ +} i2c_port_t; + +/** + * @brief Data structure for calculating I2C bus timing. + */ +typedef struct { + uint16_t clkm_div; /*!< I2C core clock devider */ + uint16_t scl_low; /*!< I2C scl low period */ + uint16_t scl_high; /*!< I2C scl hight period */ + uint16_t scl_wait_high; /*!< I2C scl wait_high period */ + uint16_t sda_hold; /*!< I2C scl low period */ + uint16_t sda_sample; /*!< I2C sda sample time */ + uint16_t setup; /*!< I2C start and stop condition setup period */ + uint16_t hold; /*!< I2C start and stop condition hold period */ + uint16_t tout; /*!< I2C bus timeout period */ +} i2c_hal_clk_config_t; typedef enum{ #if SOC_I2C_SUPPORT_SLAVE @@ -52,6 +73,23 @@ typedef enum { I2C_MASTER_ACK_MAX, } i2c_ack_type_t; +/** + * @brief Timing configuration structure. Used for I2C reset internally. + */ +typedef struct { + int high_period; /*!< high_period time */ + int low_period; /*!< low_period time */ + int wait_high_period; /*!< wait_high_period time */ + int rstart_setup; /*!< restart setup */ + int start_hold; /*!< start hold time */ + int stop_setup; /*!< stop setup */ + int stop_hold; /*!< stop hold time */ + int sda_sample; /*!< high_period time */ + int sda_hold; /*!< sda hold time */ + int timeout; /*!< timeout value */ +} i2c_hal_timing_config_t; + + /** * @brief I2C group clock source */ diff --git a/components/hal/include/hal/lcd_types.h b/components/hal/include/hal/lcd_types.h index 6236585417..0bf2b412bd 100644 --- a/components/hal/include/hal/lcd_types.h +++ b/components/hal/include/hal/lcd_types.h @@ -20,6 +20,47 @@ extern "C" { typedef soc_periph_lcd_clk_src_t lcd_clock_source_t; #endif +/** + * @brief RGB color endian + */ +typedef enum { + LCD_RGB_ENDIAN_RGB, /*!< RGB data endian: RGB */ + LCD_RGB_ENDIAN_BGR, /*!< RGB data endian: BGR */ +} lcd_color_rgb_endian_t; + +/** + * @brief LCD color space + */ +typedef enum { + LCD_COLOR_SPACE_RGB, /*!< Color space: RGB */ + LCD_COLOR_SPACE_YUV, /*!< Color space: YUV */ +} lcd_color_space_t; + +/** + * @brief LCD color range + */ +typedef enum { + LCD_COLOR_RANGE_LIMIT, /*!< Limited color range */ + LCD_COLOR_RANGE_FULL, /*!< Full color range */ +} lcd_color_range_t; + +/** + * @brief YUV sampling method + */ +typedef enum { + LCD_YUV_SAMPLE_422, /*!< YUV 4:2:2 sampling */ + LCD_YUV_SAMPLE_420, /*!< YUV 4:2:0 sampling */ + LCD_YUV_SAMPLE_411, /*!< YUV 4:1:1 sampling */ +} lcd_yuv_sample_t; + +/** + * @brief The standard used for conversion between RGB and YUV + */ +typedef enum { + LCD_YUV_CONV_STD_BT601, /*!< YUV<->RGB conversion standard: BT.601 */ + LCD_YUV_CONV_STD_BT709, /*!< YUV<->RGB conversion standard: BT.709 */ +} lcd_yuv_conv_std_t; + #ifdef __cplusplus } #endif diff --git a/components/hal/include/hal/mmu_types.h b/components/hal/include/hal/mmu_types.h index bc64830ef3..37a3a2cd5d 100644 --- a/components/hal/include/hal/mmu_types.h +++ b/components/hal/include/hal/mmu_types.h @@ -15,11 +15,20 @@ extern "C" { * MMU Page size */ typedef enum { + MMU_PAGE_8KB = 0x2000, MMU_PAGE_16KB = 0x4000, MMU_PAGE_32KB = 0x8000, MMU_PAGE_64KB = 0x10000, } mmu_page_size_t; +/** + * MMU virtual address type + */ +typedef enum { + MMU_VADDR_DATA, + MMU_VADDR_INSTRUCTION, +} mmu_vaddr_t; + /** * External physical memory */ diff --git a/components/hal/include/hal/rtc_hal.h b/components/hal/include/hal/rtc_hal.h index ae399f3fe3..862b50e1ee 100644 --- a/components/hal/include/hal/rtc_hal.h +++ b/components/hal/include/hal/rtc_hal.h @@ -10,7 +10,7 @@ #include "soc/soc_caps.h" #include "hal/gpio_types.h" #include "hal/rtc_cntl_ll.h" -#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C2 +#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED #include "hal/rtc_io_ll.h" #endif diff --git a/components/hal/include/hal/rtc_io_hal.h b/components/hal/include/hal/rtc_io_hal.h index d3d9684a05..665105da37 100644 --- a/components/hal/include/hal/rtc_io_hal.h +++ b/components/hal/include/hal/rtc_io_hal.h @@ -17,9 +17,10 @@ #include #include "sdkconfig.h" -#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C2 +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 #include "soc/soc_caps.h" #include "hal/rtc_io_ll.h" +#include "hal/rtc_io_types.h" #endif #ifdef __cplusplus diff --git a/components/hal/include/hal/sdio_slave_hal.h b/components/hal/include/hal/sdio_slave_hal.h index 5b252ea9ba..210cedd4bd 100644 --- a/components/hal/include/hal/sdio_slave_hal.h +++ b/components/hal/include/hal/sdio_slave_hal.h @@ -1,16 +1,8 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /******************************************************************************* * NOTICE @@ -210,6 +202,10 @@ typedef struct { * configured before using the HAL. `SDIO_SLAVE_TIMING_PSEND_PSAMPLE` is * recommended by default. */ + //some boolean flags + struct { + uint32_t no_highspeed: 1; /**< Disable the highspeed support */ + }; int send_queue_size; /**< Max buffers that can be queued before sending. Should be manually * configured before using the HAL. */ @@ -220,6 +216,7 @@ typedef struct { sdio_ringbuf_t send_desc_queue; /**< The ring buffer used to hold queued descriptors. Should be manually * initialized before using the HAL. */ + //Internal status, no need to touch. send_state_t send_state; // Current state of sending part. uint32_t tail_pkt_len; // The accumulated send length of the tail packet. diff --git a/components/hal/include/hal/sdio_slave_types.h b/components/hal/include/hal/sdio_slave_types.h index dc48dbeb66..56eaa2a334 100644 --- a/components/hal/include/hal/sdio_slave_types.h +++ b/components/hal/include/hal/sdio_slave_types.h @@ -25,9 +25,14 @@ typedef enum { /// Timing of SDIO slave typedef enum { SDIO_SLAVE_TIMING_PSEND_PSAMPLE = 0,/**< Send at posedge, and sample at posedge. Default value for HS mode. + * If :c:macro:`SDIO_SLAVE_FLAG_HIGH_SPEED` is specified in + * :cpp:class:`sdio_slave_config_t`, this should be selected. * Normally there's no problem using this to work in DS mode. */ - SDIO_SLAVE_TIMING_NSEND_PSAMPLE ,///< Send at negedge, and sample at posedge. Default value for DS mode and below. + SDIO_SLAVE_TIMING_NSEND_PSAMPLE, /**< Send at negedge, and sample at posedge. Default value for DS mode and + * below. If :c:macro:`SDIO_SLAVE_FLAG_DEFAULT_SPEED` is specified in + * :cpp:class:`sdio_slave_config_t`, this should be selected. + */ SDIO_SLAVE_TIMING_PSEND_NSAMPLE, ///< Send at posedge, and sample at negedge SDIO_SLAVE_TIMING_NSEND_NSAMPLE, ///< Send at negedge, and sample at negedge } sdio_slave_timing_t; diff --git a/components/hal/include/hal/sha_types.h b/components/hal/include/hal/sha_types.h index 6a9b6ea1c1..3946f1157e 100644 --- a/components/hal/include/hal/sha_types.h +++ b/components/hal/include/hal/sha_types.h @@ -21,6 +21,8 @@ #include "esp32h2/rom/sha.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/sha.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/sha.h" #endif #ifdef __cplusplus diff --git a/components/hal/include/hal/spi_types.h b/components/hal/include/hal/spi_types.h index 37e9e53787..3420468872 100644 --- a/components/hal/include/hal/spi_types.h +++ b/components/hal/include/hal/spi_types.h @@ -53,6 +53,22 @@ typedef struct { uint8_t data_lines; ///< The line width of data phase, e.g. 4-line-data-phase. } spi_line_mode_t; +/** + * @brief SPI command. + */ +typedef enum { + /* Slave HD Only */ + SPI_CMD_HD_WRBUF = BIT(0), + SPI_CMD_HD_RDBUF = BIT(1), + SPI_CMD_HD_WRDMA = BIT(2), + SPI_CMD_HD_RDDMA = BIT(3), + SPI_CMD_HD_SEG_END = BIT(4), + SPI_CMD_HD_EN_QPI = BIT(5), + SPI_CMD_HD_WR_END = BIT(6), + SPI_CMD_HD_INT0 = BIT(7), + SPI_CMD_HD_INT1 = BIT(8), + SPI_CMD_HD_INT2 = BIT(9), +} spi_command_t; /** @cond */ //Doxy command to hide preprocessor definitions from docs */ diff --git a/components/hal/include/hal/timer_hal.h b/components/hal/include/hal/timer_hal.h index 126c24def6..02220ffa36 100644 --- a/components/hal/include/hal/timer_hal.h +++ b/components/hal/include/hal/timer_hal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -37,6 +37,13 @@ typedef struct { */ void timer_hal_init(timer_hal_context_t *hal, uint32_t group_num, uint32_t timer_num); +/** + * @brief Deinit timer hal context. + * + * @param hal Context of HAL layer + */ +void timer_hal_deinit(timer_hal_context_t *hal); + /** * @brief Load counter value into time-base counter * @@ -45,6 +52,14 @@ void timer_hal_init(timer_hal_context_t *hal, uint32_t group_num, uint32_t timer */ void timer_hal_set_counter_value(timer_hal_context_t *hal, uint64_t load_val); +/** + * @brief Trigger a software capture event and then return the captured count value + * + * @param hal Context of the HAL layer + * @return Counter value + */ +uint64_t timer_hal_capture_and_get_counter_value(timer_hal_context_t *hal); + #ifdef __cplusplus } #endif diff --git a/components/hal/include/hal/uart_hal.h b/components/hal/include/hal/uart_hal.h index 6445d76967..89c89ed400 100644 --- a/components/hal/include/hal/uart_hal.h +++ b/components/hal/include/hal/uart_hal.h @@ -203,10 +203,11 @@ void uart_hal_get_sclk(uart_hal_context_t *hal, uart_sclk_t *sclk); * * @param hal Context of the HAL layer * @param baud_rate The baud-rate to be set + * @param sclk_freq Frequency of the clock source of UART, in Hz. * * @return None */ -void uart_hal_set_baudrate(uart_hal_context_t *hal, uint32_t baud_rate); +void uart_hal_set_baudrate(uart_hal_context_t *hal, uint32_t baud_rate, uint32_t sclk_freq); /** * @brief Configure the UART stop bit @@ -408,10 +409,11 @@ void uart_hal_get_parity(uart_hal_context_t *hal, uart_parity_t *parity_mode); * * @param hal Context of the HAL layer * @param baud_rate Pointer to accept the current baud-rate + * @param sclk_freq Frequency of the clock source of UART, in Hz. * * @return None */ -void uart_hal_get_baudrate(uart_hal_context_t *hal, uint32_t *baud_rate); +void uart_hal_get_baudrate(uart_hal_context_t *hal, uint32_t *baud_rate, uint32_t sclk_freq); /** * @brief Get the hw flow control configuration diff --git a/components/hal/include/hal/usbh_hal.h b/components/hal/include/hal/usb_dwc_hal.h similarity index 67% rename from components/hal/include/hal/usbh_hal.h rename to components/hal/include/hal/usb_dwc_hal.h index 5326deb2dc..d52e882cb9 100644 --- a/components/hal/include/hal/usbh_hal.h +++ b/components/hal/include/hal/usb_dwc_hal.h @@ -17,8 +17,8 @@ NOTE: Thread safety is the responsibility fo the HAL user. All USB Host HAL #include #include -#include "soc/usbh_struct.h" -#include "hal/usbh_ll.h" +#include "soc/usb_dwc_struct.h" +#include "hal/usb_dwc_ll.h" #include "hal/usb_types_private.h" #include "hal/assert.h" @@ -26,11 +26,11 @@ NOTE: Thread safety is the responsibility fo the HAL user. All USB Host HAL // ------------------ Constants/Configs -------------------- -#define USBH_HAL_DMA_MEM_ALIGN 512 -#define USBH_HAL_FRAME_LIST_MEM_ALIGN 512 //The frame list needs to be 512 bytes aligned (contrary to the databook) -#define USBH_HAL_NUM_CHAN 8 -#define USBH_HAL_XFER_DESC_SIZE (sizeof(usbh_ll_dma_qtd_t)) -#define USBH_HAL_FIFO_TOTAL_USABLE_LINES 200 //Although we have a 256 lines, only 200 lines are usuable due to EPINFO_CTL +#define USB_DWC_HAL_DMA_MEM_ALIGN 512 +#define USB_DWC_HAL_FRAME_LIST_MEM_ALIGN 512 //The frame list needs to be 512 bytes aligned (contrary to the databook) +#define USB_DWC_HAL_NUM_CHAN 8 +#define USB_DWC_HAL_XFER_DESC_SIZE (sizeof(usb_dwc_ll_dma_qtd_t)) +#define USB_DWC_HAL_FIFO_TOTAL_USABLE_LINES 200 //Although we have a 256 lines, only 200 lines are usuable due to EPINFO_CTL /** * @brief FIFO size configuration structure @@ -39,7 +39,7 @@ typedef struct { uint32_t rx_fifo_lines; /**< Size of the RX FIFO in terms the number of FIFO lines */ uint32_t nptx_fifo_lines; /**< Size of the Non-periodic FIFO in terms the number of FIFO lines */ uint32_t ptx_fifo_lines; /**< Size of the Periodic FIFO in terms the number of FIFO lines */ -} usbh_hal_fifo_config_t; +} usb_dwc_hal_fifo_config_t; // --------------------- HAL Events ------------------------ @@ -47,25 +47,25 @@ typedef struct { * @brief Host port HAL events */ typedef enum { - USBH_HAL_PORT_EVENT_NONE, /**< No event occurred, or could not decode interrupt */ - USBH_HAL_PORT_EVENT_CHAN, /**< A channel event has occurred. Call the the channel event handler instead */ - USBH_HAL_PORT_EVENT_CONN, /**< The host port has detected a connection */ - USBH_HAL_PORT_EVENT_DISCONN, /**< The host port has been disconnected */ - USBH_HAL_PORT_EVENT_ENABLED, /**< The host port has been enabled (i.e., connected to a device that has been reset. Started sending SOFs) */ - USBH_HAL_PORT_EVENT_DISABLED, /**< The host port has been disabled (no more SOFs). Could be due to disable/reset request, or a port error (e.g. port babble condition. See 11.8.1 of USB2.0 spec) */ - USBH_HAL_PORT_EVENT_OVRCUR, /**< The host port has encountered an overcurrent condition */ - USBH_HAL_PORT_EVENT_OVRCUR_CLR, /**< The host port has been cleared of the overcurrent condition */ -} usbh_hal_port_event_t; + USB_DWC_HAL_PORT_EVENT_NONE, /**< No event occurred, or could not decode interrupt */ + USB_DWC_HAL_PORT_EVENT_CHAN, /**< A channel event has occurred. Call the the channel event handler instead */ + USB_DWC_HAL_PORT_EVENT_CONN, /**< The host port has detected a connection */ + USB_DWC_HAL_PORT_EVENT_DISCONN, /**< The host port has been disconnected */ + USB_DWC_HAL_PORT_EVENT_ENABLED, /**< The host port has been enabled (i.e., connected to a device that has been reset. Started sending SOFs) */ + USB_DWC_HAL_PORT_EVENT_DISABLED, /**< The host port has been disabled (no more SOFs). Could be due to disable/reset request, or a port error (e.g. port babble condition. See 11.8.1 of USB2.0 spec) */ + USB_DWC_HAL_PORT_EVENT_OVRCUR, /**< The host port has encountered an overcurrent condition */ + USB_DWC_HAL_PORT_EVENT_OVRCUR_CLR, /**< The host port has been cleared of the overcurrent condition */ +} usb_dwc_hal_port_event_t; /** * @brief Channel events */ typedef enum { - USBH_HAL_CHAN_EVENT_CPLT, /**< The channel has completed execution of a transfer descriptor that had the USBH_HAL_XFER_DESC_FLAG_HOC flag set. Channel is now halted */ - USBH_HAL_CHAN_EVENT_ERROR, /**< The channel has encountered an error. Channel is now halted. */ - USBH_HAL_CHAN_EVENT_HALT_REQ, /**< The channel has been successfully halted as requested */ - USBH_HAL_CHAN_EVENT_NONE, /**< No event (interrupt ran for internal processing) */ -} usbh_hal_chan_event_t; + USB_DWC_HAL_CHAN_EVENT_CPLT, /**< The channel has completed execution of a transfer descriptor that had the USB_DWC_HAL_XFER_DESC_FLAG_HOC flag set. Channel is now halted */ + USB_DWC_HAL_CHAN_EVENT_ERROR, /**< The channel has encountered an error. Channel is now halted. */ + USB_DWC_HAL_CHAN_EVENT_HALT_REQ, /**< The channel has been successfully halted as requested */ + USB_DWC_HAL_CHAN_EVENT_NONE, /**< No event (interrupt ran for internal processing) */ +} usb_dwc_hal_chan_event_t; // --------------------- HAL Errors ------------------------ @@ -73,20 +73,20 @@ typedef enum { * @brief Channel errors */ typedef enum { - USBH_HAL_CHAN_ERROR_XCS_XACT = 0, /**< Excessive (three consecutive) transaction errors (e.g., no response, bad CRC etc */ - USBH_HAL_CHAN_ERROR_BNA, /**< Buffer Not Available error (i.e., An inactive transfer descriptor was fetched by the channel) */ - USBH_HAL_CHAN_ERROR_PKT_BBL, /**< Packet babbler error (packet exceeded MPS) */ - USBH_HAL_CHAN_ERROR_STALL, /**< STALL response received */ -} usbh_hal_chan_error_t; + USB_DWC_HAL_CHAN_ERROR_XCS_XACT = 0, /**< Excessive (three consecutive) transaction errors (e.g., no response, bad CRC etc */ + USB_DWC_HAL_CHAN_ERROR_BNA, /**< Buffer Not Available error (i.e., An inactive transfer descriptor was fetched by the channel) */ + USB_DWC_HAL_CHAN_ERROR_PKT_BBL, /**< Packet babbler error (packet exceeded MPS) */ + USB_DWC_HAL_CHAN_ERROR_STALL, /**< STALL response received */ +} usb_dwc_hal_chan_error_t; // ------------- Transfer Descriptor Related --------------- /** * @brief Flags used to describe the type of transfer descriptor to fill */ -#define USBH_HAL_XFER_DESC_FLAG_IN 0x01 /**< Indicates this transfer descriptor is of the IN direction */ -#define USBH_HAL_XFER_DESC_FLAG_SETUP 0x02 /**< Indicates this transfer descriptor is an OUT setup */ -#define USBH_HAL_XFER_DESC_FLAG_HOC 0x04 /**< Indicates that the channel will be halted after this transfer descriptor completes */ +#define USB_DWC_HAL_XFER_DESC_FLAG_IN 0x01 /**< Indicates this transfer descriptor is of the IN direction */ +#define USB_DWC_HAL_XFER_DESC_FLAG_SETUP 0x02 /**< Indicates this transfer descriptor is an OUT setup */ +#define USB_DWC_HAL_XFER_DESC_FLAG_HOC 0x04 /**< Indicates that the channel will be halted after this transfer descriptor completes */ /** * @brief Status value of a transfer descriptor @@ -95,10 +95,10 @@ typedef enum { * or an error). Therefore, if a channel halt is requested before a transfer descriptor completes, the transfer * descriptor remains unexecuted. */ -#define USBH_HAL_XFER_DESC_STS_SUCCESS USBH_LL_QTD_STATUS_SUCCESS -#define USBH_HAL_XFER_DESC_STS_PKTERR USBH_LL_QTD_STATUS_PKTERR -#define USBH_HAL_XFER_DESC_STS_BUFFER_ERR USBH_LL_QTD_STATUS_BUFFER -#define USBH_HAL_XFER_DESC_STS_NOT_EXECUTED USBH_LL_QTD_STATUS_NOT_EXECUTED +#define USB_DWC_HAL_XFER_DESC_STS_SUCCESS USB_DWC_LL_QTD_STATUS_SUCCESS +#define USB_DWC_HAL_XFER_DESC_STS_PKTERR USB_DWC_LL_QTD_STATUS_PKTERR +#define USB_DWC_HAL_XFER_DESC_STS_BUFFER_ERR USB_DWC_LL_QTD_STATUS_BUFFER +#define USB_DWC_HAL_XFER_DESC_STS_NOT_EXECUTED USB_DWC_LL_QTD_STATUS_NOT_EXECUTED // -------------------- Object Types ----------------------- @@ -122,7 +122,7 @@ typedef struct { usb_hal_interval_t interval; /**< The interval of the endpoint */ uint32_t phase_offset_frames; /**< Phase offset in number of frames */ } periodic; /**< Characteristic for periodic (interrupt/isochronous) endpoints only */ -} usbh_hal_ep_char_t; +} usb_dwc_hal_ep_char_t; /** * @brief Channel object @@ -139,18 +139,18 @@ typedef struct { }; uint32_t val; } flags; /**< Flags regarding channel's status and information */ - usb_host_chan_regs_t *regs; /**< Pointer to the channel's register set */ - usbh_hal_chan_error_t error; /**< The last error that occurred on the channel */ + usb_dwc_host_chan_regs_t *regs; /**< Pointer to the channel's register set */ + usb_dwc_hal_chan_error_t error; /**< The last error that occurred on the channel */ usb_priv_xfer_type_t type; /**< The transfer type of the channel */ void *chan_ctx; /**< Context variable for the owner of the channel */ -} usbh_hal_chan_t; +} usb_dwc_hal_chan_t; /** * @brief HAL context structure */ typedef struct { //Context - usbh_dev_t *dev; /**< Pointer to base address of DWC_OTG registers */ + usb_dwc_dev_t *dev; /**< Pointer to base address of DWC_OTG registers */ //Host Port related uint32_t *periodic_frame_list; /**< Pointer to scheduling frame list */ usb_hal_frame_list_len_t frame_list_len; /**< Length of the periodic scheduling frame list */ @@ -168,9 +168,9 @@ typedef struct { struct { int num_allocd; /**< Number of channels currently allocated */ uint32_t chan_pend_intrs_msk; /**< Bit mask of channels with pending interrupts */ - usbh_hal_chan_t *hdls[USBH_HAL_NUM_CHAN]; /**< Handles of each channel. Set to NULL if channel has not been allocated */ + usb_dwc_hal_chan_t *hdls[USB_DWC_HAL_NUM_CHAN]; /**< Handles of each channel. Set to NULL if channel has not been allocated */ } channels; -} usbh_hal_context_t; +} usb_dwc_hal_context_t; // -------------------------------------------------- Core (Global) ---------------------------------------------------- @@ -188,12 +188,12 @@ typedef struct { * - Sets default values to some global and OTG registers (GAHBCFG and GUSBCFG) * - Umask global interrupt signal * - Put DWC_OTG into host mode. Require 25ms delay before this takes effect. - * - State -> USBH_HAL_PORT_STATE_OTG + * - State -> USB_DWC_HAL_PORT_STATE_OTG * - Interrupts cleared. Users can now enable their ISR * * @param[inout] hal Context of the HAL layer */ -void usbh_hal_init(usbh_hal_context_t *hal); +void usb_dwc_hal_init(usb_dwc_hal_context_t *hal); /** * @brief Deinitialize the HAL context @@ -206,20 +206,20 @@ void usbh_hal_init(usbh_hal_context_t *hal); * * @param hal Context of the HAL layer */ -void usbh_hal_deinit(usbh_hal_context_t *hal); +void usb_dwc_hal_deinit(usb_dwc_hal_context_t *hal); /** * @brief Issue a soft reset to the controller * * This should be called when the host port encounters an error event or has been disconnected. Before calling this, * users are responsible for safely freeing all channels as a soft reset will wipe all host port and channel registers. - * This function will result in the host port being put back into same state as after calling usbh_hal_init(). + * This function will result in the host port being put back into same state as after calling usb_dwc_hal_init(). * * @note This has nothing to do with a USB bus reset. It simply resets the peripheral * * @param hal Context of the HAL layer */ -void usbh_hal_core_soft_reset(usbh_hal_context_t *hal); +void usb_dwc_hal_core_soft_reset(usb_dwc_hal_context_t *hal); /** * @brief Set FIFO sizes @@ -229,14 +229,14 @@ void usbh_hal_core_soft_reset(usbh_hal_context_t *hal); * may be situations where this function may need to be called again to resize the FIFOs. If resizing FIFOs dynamically, * it is the user's responsibility to ensure there are no active channels when this function is called. * - * @note The totol size of all the FIFOs must be less than or equal to USBH_HAL_FIFO_TOTAL_USABLE_LINES + * @note The totol size of all the FIFOs must be less than or equal to USB_DWC_HAL_FIFO_TOTAL_USABLE_LINES * @note After a port reset, the FIFO size registers will reset to their default values, so this function must be called * again post reset. * * @param hal Context of the HAL layer * @param fifo_config FIFO configuration */ -void usbh_hal_set_fifo_size(usbh_hal_context_t *hal, const usbh_hal_fifo_config_t *fifo_config); +void usb_dwc_hal_set_fifo_size(usb_dwc_hal_context_t *hal, const usb_dwc_hal_fifo_config_t *fifo_config); // ---------------------------------------------------- Host Port ------------------------------------------------------ @@ -249,11 +249,11 @@ void usbh_hal_set_fifo_size(usbh_hal_context_t *hal, const usbh_hal_fifo_config_ * * @param hal Context of the HAL layer */ -static inline void usbh_hal_port_init(usbh_hal_context_t *hal) +static inline void usb_dwc_hal_port_init(usb_dwc_hal_context_t *hal) { //Configure Host related interrupts - usbh_ll_haintmsk_dis_chan_intr(hal->dev, 0xFFFFFFFF); //Disable interrupts for all channels - usb_ll_en_intrs(hal->dev, USB_LL_INTR_CORE_PRTINT | USB_LL_INTR_CORE_HCHINT); + usb_dwc_ll_haintmsk_dis_chan_intr(hal->dev, 0xFFFFFFFF); //Disable interrupts for all channels + usb_dwc_ll_gintmsk_en_intrs(hal->dev, USB_DWC_LL_INTR_CORE_PRTINT | USB_DWC_LL_INTR_CORE_HCHINT); } /** @@ -263,10 +263,10 @@ static inline void usbh_hal_port_init(usbh_hal_context_t *hal) * * @param hal Context of the HAL layer */ -static inline void usbh_hal_port_deinit(usbh_hal_context_t *hal) +static inline void usb_dwc_hal_port_deinit(usb_dwc_hal_context_t *hal) { //Disable Host port and channel interrupts - usb_ll_dis_intrs(hal->dev, USB_LL_INTR_CORE_PRTINT | USB_LL_INTR_CORE_HCHINT); + usb_dwc_ll_gintmsk_dis_intrs(hal->dev, USB_DWC_LL_INTR_CORE_PRTINT | USB_DWC_LL_INTR_CORE_HCHINT); } /** @@ -275,12 +275,12 @@ static inline void usbh_hal_port_deinit(usbh_hal_context_t *hal) * @param hal Context of the HAL layer * @param power_on Whether to power ON or OFF the port */ -static inline void usbh_hal_port_toggle_power(usbh_hal_context_t *hal, bool power_on) +static inline void usb_dwc_hal_port_toggle_power(usb_dwc_hal_context_t *hal, bool power_on) { if (power_on) { - usbh_ll_hprt_en_pwr(hal->dev); + usb_dwc_ll_hprt_en_pwr(hal->dev); } else { - usbh_ll_hprt_dis_pwr(hal->dev); + usb_dwc_ll_hprt_dis_pwr(hal->dev); } } @@ -291,19 +291,19 @@ static inline void usbh_hal_port_toggle_power(usbh_hal_context_t *hal, bool powe * Entry: * - Host port detects a device connection or Host port is already enabled * Exit: - * - On release of the reset signal, a USBH_HAL_PORT_EVENT_ENABLED will be generated + * - On release of the reset signal, a USB_DWC_HAL_PORT_EVENT_ENABLED will be generated * * @note If the host port is already enabled, then issuing a reset will cause it be disabled and generate a - * USBH_HAL_PORT_EVENT_DISABLED event. The host port will not be enabled until the reset signal is released (thus - * generating the USBH_HAL_PORT_EVENT_ENABLED event) + * USB_DWC_HAL_PORT_EVENT_DISABLED event. The host port will not be enabled until the reset signal is released (thus + * generating the USB_DWC_HAL_PORT_EVENT_ENABLED event) * * @param hal Context of the HAL layer * @param enable Enable/disable reset signal */ -static inline void usbh_hal_port_toggle_reset(usbh_hal_context_t *hal, bool enable) +static inline void usb_dwc_hal_port_toggle_reset(usb_dwc_hal_context_t *hal, bool enable) { HAL_ASSERT(hal->channels.num_allocd == 0); //Cannot reset if there are still allocated channels - usbh_ll_hprt_set_port_reset(hal->dev, enable); + usb_dwc_ll_hprt_set_port_reset(hal->dev, enable); } /** @@ -317,7 +317,7 @@ static inline void usbh_hal_port_toggle_reset(usbh_hal_context_t *hal, bool enab * * @param hal Context of the HAL layer */ -void usbh_hal_port_enable(usbh_hal_context_t *hal); +void usb_dwc_hal_port_enable(usb_dwc_hal_context_t *hal); /** * @brief Disable the host port @@ -327,9 +327,9 @@ void usbh_hal_port_enable(usbh_hal_context_t *hal); * * @param hal Context of the HAL layer */ -static inline void usbh_hal_port_disable(usbh_hal_context_t *hal) +static inline void usb_dwc_hal_port_disable(usb_dwc_hal_context_t *hal) { - usbh_ll_hprt_port_dis(hal->dev); + usb_dwc_ll_hprt_port_dis(hal->dev); } /** @@ -337,9 +337,9 @@ static inline void usbh_hal_port_disable(usbh_hal_context_t *hal) * * @param hal Context of the HAL layers */ -static inline void usbh_hal_port_suspend(usbh_hal_context_t *hal) +static inline void usb_dwc_hal_port_suspend(usb_dwc_hal_context_t *hal) { - usbh_ll_hprt_set_port_suspend(hal->dev); + usb_dwc_ll_hprt_set_port_suspend(hal->dev); } /** @@ -352,12 +352,12 @@ static inline void usbh_hal_port_suspend(usbh_hal_context_t *hal) * @param hal Context of the HAL layer * @param enable Enable/disable resume signal */ -static inline void usbh_hal_port_toggle_resume(usbh_hal_context_t *hal, bool enable) +static inline void usb_dwc_hal_port_toggle_resume(usb_dwc_hal_context_t *hal, bool enable) { if (enable) { - usbh_ll_hprt_set_port_resume(hal->dev); + usb_dwc_ll_hprt_set_port_resume(hal->dev); } else { - usbh_ll_hprt_clr_port_resume(hal->dev); + usb_dwc_ll_hprt_clr_port_resume(hal->dev); } } @@ -371,9 +371,9 @@ static inline void usbh_hal_port_toggle_resume(usbh_hal_context_t *hal, bool ena * @return true Resume signal is still being driven * @return false Resume signal is no longer driven */ -static inline bool usbh_hal_port_check_resume(usbh_hal_context_t *hal) +static inline bool usb_dwc_hal_port_check_resume(usb_dwc_hal_context_t *hal) { - return usbh_ll_hprt_get_port_resume(hal->dev); + return usb_dwc_ll_hprt_get_port_resume(hal->dev); } // ---------------- Host Port Scheduling ------------------- @@ -382,13 +382,13 @@ static inline bool usbh_hal_port_check_resume(usbh_hal_context_t *hal) * @brief Sets the periodic scheduling frame list * * @note This function must be called before attempting configuring any channels to be period via - * usbh_hal_chan_set_ep_char() + * usb_dwc_hal_chan_set_ep_char() * * @param hal Context of the HAL layer * @param frame_list Base address of the frame list * @param frame_list_len Number of entries in the frame list (can only be 8, 16, 32, 64) */ -static inline void usbh_hal_port_set_frame_list(usbh_hal_context_t *hal, uint32_t *frame_list, usb_hal_frame_list_len_t len) +static inline void usb_dwc_hal_port_set_frame_list(usb_dwc_hal_context_t *hal, uint32_t *frame_list, usb_hal_frame_list_len_t len) { //Clear and save frame list hal->periodic_frame_list = frame_list; @@ -401,7 +401,7 @@ static inline void usbh_hal_port_set_frame_list(usbh_hal_context_t *hal, uint32_ * @param hal Context of the HAL layer * @return uint32_t* Base address of the periodic scheduling frame list */ -static inline uint32_t *usbh_hal_port_get_frame_list(usbh_hal_context_t *hal) +static inline uint32_t *usb_dwc_hal_port_get_frame_list(usb_dwc_hal_context_t *hal) { return hal->periodic_frame_list; } @@ -409,18 +409,18 @@ static inline uint32_t *usbh_hal_port_get_frame_list(usbh_hal_context_t *hal) /** * @brief Enable periodic scheduling * - * @note The periodic frame list must be set via usbh_hal_port_set_frame_list() should be set before calling this + * @note The periodic frame list must be set via usb_dwc_hal_port_set_frame_list() should be set before calling this * function * @note This function must be called before activating any periodic channels * * @param hal Context of the HAL layer */ -static inline void usbh_hal_port_periodic_enable(usbh_hal_context_t *hal) +static inline void usb_dwc_hal_port_periodic_enable(usb_dwc_hal_context_t *hal) { HAL_ASSERT(hal->periodic_frame_list != NULL); - usbh_ll_set_frame_list_base_addr(hal->dev, (uint32_t)hal->periodic_frame_list); - usbh_ll_hcfg_set_num_frame_list_entries(hal->dev, hal->frame_list_len); - usbh_ll_hcfg_en_perio_sched(hal->dev); + usb_dwc_ll_hflbaddr_set_base_addr(hal->dev, (uint32_t)hal->periodic_frame_list); + usb_dwc_ll_hcfg_set_num_frame_list_entries(hal->dev, hal->frame_list_len); + usb_dwc_ll_hcfg_en_perio_sched(hal->dev); hal->flags.periodic_sched_enabled = 1; } @@ -435,16 +435,16 @@ static inline void usbh_hal_port_periodic_enable(usbh_hal_context_t *hal) * * @param hal Context of the HAL layer */ -static inline void usbh_hal_port_periodic_disable(usbh_hal_context_t *hal) +static inline void usb_dwc_hal_port_periodic_disable(usb_dwc_hal_context_t *hal) { HAL_ASSERT(hal->flags.periodic_sched_enabled); - usbh_ll_hcfg_dis_perio_sched(hal->dev); + usb_dwc_ll_hcfg_dis_perio_sched(hal->dev); hal->flags.periodic_sched_enabled = 0; } -static inline uint32_t usbh_hal_port_get_cur_frame_num(usbh_hal_context_t *hal) +static inline uint32_t usb_dwc_hal_port_get_cur_frame_num(usb_dwc_hal_context_t *hal) { - return usbh_ll_get_frm_num(hal->dev); + return usb_dwc_ll_hfnum_get_frame_num(hal->dev); } // --------------- Host Port Status/State ------------------ @@ -453,19 +453,19 @@ static inline uint32_t usbh_hal_port_get_cur_frame_num(usbh_hal_context_t *hal) * @brief Check if a device is currently connected to the host port * * This function is intended to be called after one of the following events followed by an adequate debounce delay - * - USBH_HAL_PORT_EVENT_CONN - * - USBH_HAL_PORT_EVENT_DISCONN + * - USB_DWC_HAL_PORT_EVENT_CONN + * - USB_DWC_HAL_PORT_EVENT_DISCONN * * @note No other connection/disconnection event will occur again until the debounce lock is disabled via - * usbh_hal_disable_debounce_lock() + * usb_dwc_hal_disable_debounce_lock() * * @param hal Context of the HAL layer * @return true A device is connected to the host port * @return false A device is not connected to the host port */ -static inline bool usbh_hal_port_check_if_connected(usbh_hal_context_t *hal) +static inline bool usb_dwc_hal_port_check_if_connected(usb_dwc_hal_context_t *hal) { - return usbh_ll_hprt_get_conn_status(hal->dev); + return usb_dwc_ll_hprt_get_conn_status(hal->dev); } /** @@ -476,27 +476,27 @@ static inline bool usbh_hal_port_check_if_connected(usbh_hal_context_t *hal) * @param hal Context of the HAL layer * @return usb_priv_speed_t Speed of the connected device (FS or LS only on the esp32-s2 and esp32-s3) */ -static inline usb_priv_speed_t usbh_hal_port_get_conn_speed(usbh_hal_context_t *hal) +static inline usb_priv_speed_t usb_dwc_hal_port_get_conn_speed(usb_dwc_hal_context_t *hal) { - return usbh_ll_hprt_get_speed(hal->dev); + return usb_dwc_ll_hprt_get_speed(hal->dev); } /** * @brief Disable the debounce lock * - * This function must be called after calling usbh_hal_port_check_if_connected() and will allow connection/disconnection + * This function must be called after calling usb_dwc_hal_port_check_if_connected() and will allow connection/disconnection * events to occur again. Any pending connection or disconenction interrupts are cleared. * * @param hal Context of the HAL layer */ -static inline void usbh_hal_disable_debounce_lock(usbh_hal_context_t *hal) +static inline void usb_dwc_hal_disable_debounce_lock(usb_dwc_hal_context_t *hal) { hal->flags.dbnc_lock_enabled = 0; //Clear Conenction and disconenction interrupt in case it triggered again - usb_ll_intr_clear(hal->dev, USB_LL_INTR_CORE_DISCONNINT); - usbh_ll_hprt_intr_clear(hal->dev, USBH_LL_INTR_HPRT_PRTCONNDET); + usb_dwc_ll_gintsts_clear_intrs(hal->dev, USB_DWC_LL_INTR_CORE_DISCONNINT); + usb_dwc_ll_hprt_intr_clear(hal->dev, USB_DWC_LL_INTR_HPRT_PRTCONNDET); //Reenable the hprt (connection) and disconnection interrupts - usb_ll_en_intrs(hal->dev, USB_LL_INTR_CORE_PRTINT | USB_LL_INTR_CORE_DISCONNINT); + usb_dwc_ll_gintmsk_en_intrs(hal->dev, USB_DWC_LL_INTR_CORE_PRTINT | USB_DWC_LL_INTR_CORE_DISCONNINT); } // ----------------------------------------------------- Channel ------------------------------------------------------- @@ -512,7 +512,7 @@ static inline void usbh_hal_disable_debounce_lock(usbh_hal_context_t *hal) * @return true Channel successfully allocated * @return false Failed to allocate channel */ -bool usbh_hal_chan_alloc(usbh_hal_context_t *hal, usbh_hal_chan_t *chan_obj, void *chan_ctx); +bool usb_dwc_hal_chan_alloc(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan_obj, void *chan_ctx); /** * @brief Free a channel @@ -520,7 +520,7 @@ bool usbh_hal_chan_alloc(usbh_hal_context_t *hal, usbh_hal_chan_t *chan_obj, voi * @param[in] hal Context of the HAL layer * @param[in] chan_obj Channel object */ -void usbh_hal_chan_free(usbh_hal_context_t *hal, usbh_hal_chan_t *chan_obj); +void usb_dwc_hal_chan_free(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan_obj); // ---------------- Channel Configuration ------------------ @@ -530,7 +530,7 @@ void usbh_hal_chan_free(usbh_hal_context_t *hal, usbh_hal_chan_t *chan_obj); * @param[in] chan_obj Channel object * @return void* The context variable of the channel */ -static inline void *usbh_hal_chan_get_context(usbh_hal_chan_t *chan_obj) +static inline void *usb_dwc_hal_chan_get_context(usb_dwc_hal_chan_t *chan_obj) { return chan_obj->chan_ctx; } @@ -547,7 +547,7 @@ static inline void *usbh_hal_chan_get_context(usbh_hal_chan_t *chan_obj) * @param chan_obj Channel object * @param ep_char Endpoint characteristics */ -void usbh_hal_chan_set_ep_char(usbh_hal_context_t *hal, usbh_hal_chan_t *chan_obj, usbh_hal_ep_char_t *ep_char); +void usb_dwc_hal_chan_set_ep_char(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan_obj, usb_dwc_hal_ep_char_t *ep_char); /** * @brief Set the direction of the channel @@ -561,11 +561,11 @@ void usbh_hal_chan_set_ep_char(usbh_hal_context_t *hal, usbh_hal_chan_t *chan_ob * @param chan_obj Channel object * @param is_in Whether the direction is IN */ -static inline void usbh_hal_chan_set_dir(usbh_hal_chan_t *chan_obj, bool is_in) +static inline void usb_dwc_hal_chan_set_dir(usb_dwc_hal_chan_t *chan_obj, bool is_in) { //Cannot change direction whilst channel is still active or in error HAL_ASSERT(!chan_obj->flags.active); - usbh_ll_chan_set_dir(chan_obj->regs, is_in); + usb_dwc_ll_hcchar_set_dir(chan_obj->regs, is_in); } /** @@ -580,12 +580,12 @@ static inline void usbh_hal_chan_set_dir(usbh_hal_chan_t *chan_obj, bool is_in) * @param chan_obj Channel object * @param pid PID of the next DATA packet (DATA0 or DATA1) */ -static inline void usbh_hal_chan_set_pid(usbh_hal_chan_t *chan_obj, int pid) +static inline void usb_dwc_hal_chan_set_pid(usb_dwc_hal_chan_t *chan_obj, int pid) { //Cannot change pid whilst channel is still active or in error HAL_ASSERT(!chan_obj->flags.active); //Update channel object and set the register - usbh_ll_chan_set_pid(chan_obj->regs, pid); + usb_dwc_ll_hctsiz_set_pid(chan_obj->regs, pid); } /** @@ -598,10 +598,10 @@ static inline void usbh_hal_chan_set_pid(usbh_hal_chan_t *chan_obj, int pid) * @param chan_obj Channel object * @return uint32_t Starting PID of the next transfer (DATA0 or DATA1) */ -static inline uint32_t usbh_hal_chan_get_pid(usbh_hal_chan_t *chan_obj) +static inline uint32_t usb_dwc_hal_chan_get_pid(usb_dwc_hal_chan_t *chan_obj) { HAL_ASSERT(!chan_obj->flags.active); - return usbh_ll_chan_get_pid(chan_obj->regs); + return usb_dwc_ll_hctsiz_get_pid(chan_obj->regs); } // ------------------- Channel Control --------------------- @@ -619,7 +619,7 @@ static inline uint32_t usbh_hal_chan_get_pid(usbh_hal_chan_t *chan_obj) * @param desc_list_len Transfer descriptor list length * @param start_idx Index of the starting transfer descriptor in the list */ -void usbh_hal_chan_activate(usbh_hal_chan_t *chan_obj, void *xfer_desc_list, int desc_list_len, int start_idx); +void usb_dwc_hal_chan_activate(usb_dwc_hal_chan_t *chan_obj, void *xfer_desc_list, int desc_list_len, int start_idx); /** * @brief Get the index of the current transfer descriptor @@ -627,9 +627,9 @@ void usbh_hal_chan_activate(usbh_hal_chan_t *chan_obj, void *xfer_desc_list, int * @param chan_obj Channel object * @return int Descriptor index */ -static inline int usbh_hal_chan_get_qtd_idx(usbh_hal_chan_t *chan_obj) +static inline int usb_dwc_hal_chan_get_qtd_idx(usb_dwc_hal_chan_t *chan_obj) { - return usbh_ll_chan_get_ctd(chan_obj->regs); + return usb_dwc_ll_hcdam_get_cur_qtd_idx(chan_obj->regs); } /** @@ -637,24 +637,24 @@ static inline int usbh_hal_chan_get_qtd_idx(usbh_hal_chan_t *chan_obj) * * This function should be called in order to halt a channel. If the channel is already halted, this function will * return true. If the channel is still active, this function will return false and users must wait for the - * USBH_HAL_CHAN_EVENT_HALT_REQ event before treating the channel as halted. + * USB_DWC_HAL_CHAN_EVENT_HALT_REQ event before treating the channel as halted. * * @note When a transfer is in progress (i.e., the channel is active) and a halt is requested, the channel will halt * after the next USB packet is completed. If the transfer has more pending packets, the transfer will just be - * marked as USBH_HAL_XFER_DESC_STS_NOT_EXECUTED. + * marked as USB_DWC_HAL_XFER_DESC_STS_NOT_EXECUTED. * * @param chan_obj Channel object * @return true The channel is already halted - * @return false The halt was requested, wait for USBH_HAL_CHAN_EVENT_HALT_REQ + * @return false The halt was requested, wait for USB_DWC_HAL_CHAN_EVENT_HALT_REQ */ -bool usbh_hal_chan_request_halt(usbh_hal_chan_t *chan_obj); +bool usb_dwc_hal_chan_request_halt(usb_dwc_hal_chan_t *chan_obj); /** * @brief Indicate that a channel is halted after a port error * * When a port error occurs (e.g., discconect, overcurrent): * - Any previously active channels will remain active (i.e., they will not receive a channel interrupt) - * - Attempting to disable them using usbh_hal_chan_request_halt() will NOT generate an interrupt for ISOC channels + * - Attempting to disable them using usb_dwc_hal_chan_request_halt() will NOT generate an interrupt for ISOC channels * (probalby something to do with the periodic scheduling) * * However, the channel's enable bit can be left as 1 since after a port error, a soft reset will be done anyways. @@ -663,7 +663,7 @@ bool usbh_hal_chan_request_halt(usbh_hal_chan_t *chan_obj); * * @param chan_obj Channel object */ -static inline void usbh_hal_chan_mark_halted(usbh_hal_chan_t *chan_obj) +static inline void usb_dwc_hal_chan_mark_halted(usb_dwc_hal_chan_t *chan_obj) { chan_obj->flags.active = 0; } @@ -672,9 +672,9 @@ static inline void usbh_hal_chan_mark_halted(usbh_hal_chan_t *chan_obj) * @brief Get a channel's error * * @param chan_obj Channel object - * @return usbh_hal_chan_error_t The type of error the channel has encountered + * @return usb_dwc_hal_chan_error_t The type of error the channel has encountered */ -static inline usbh_hal_chan_error_t usbh_hal_chan_get_error(usbh_hal_chan_t *chan_obj) +static inline usb_dwc_hal_chan_error_t usb_dwc_hal_chan_get_error(usb_dwc_hal_chan_t *chan_obj) { return chan_obj->error; } @@ -688,8 +688,8 @@ static inline usbh_hal_chan_error_t usbh_hal_chan_get_error(usbh_hal_chan_t *cha * - A stage of a transfer (for control transfers) * - A frame of a transfer interval (for interrupt and isoc) * - An entire transfer (for bulk transfers) - * - Check the various USBH_HAL_XFER_DESC_FLAG_ flags for filling a specific type of descriptor - * - For IN transfer entries, set the USBH_HAL_XFER_DESC_FLAG_IN. The transfer size must also be an integer multiple of + * - Check the various USB_DWC_HAL_XFER_DESC_FLAG_ flags for filling a specific type of descriptor + * - For IN transfer entries, set the USB_DWC_HAL_XFER_DESC_FLAG_IN. The transfer size must also be an integer multiple of * the endpoint's MPS * * @note Critical section is not required for this function @@ -700,19 +700,19 @@ static inline usbh_hal_chan_error_t usbh_hal_chan_get_error(usbh_hal_chan_t *cha * @param xfer_len Transfer length * @param flags Transfer flags */ -static inline void usbh_hal_xfer_desc_fill(void *desc_list, uint32_t desc_idx, uint8_t *xfer_data_buff, int xfer_len, uint32_t flags) +static inline void usb_dwc_hal_xfer_desc_fill(void *desc_list, uint32_t desc_idx, uint8_t *xfer_data_buff, int xfer_len, uint32_t flags) { - usbh_ll_dma_qtd_t *qtd_list = (usbh_ll_dma_qtd_t *)desc_list; - if (flags & USBH_HAL_XFER_DESC_FLAG_IN) { - usbh_ll_set_qtd_in(&qtd_list[desc_idx], + usb_dwc_ll_dma_qtd_t *qtd_list = (usb_dwc_ll_dma_qtd_t *)desc_list; + if (flags & USB_DWC_HAL_XFER_DESC_FLAG_IN) { + usb_dwc_ll_qtd_set_in(&qtd_list[desc_idx], xfer_data_buff, xfer_len, - flags & USBH_HAL_XFER_DESC_FLAG_HOC); + flags & USB_DWC_HAL_XFER_DESC_FLAG_HOC); } else { - usbh_ll_set_qtd_out(&qtd_list[desc_idx], + usb_dwc_ll_qtd_set_out(&qtd_list[desc_idx], xfer_data_buff, xfer_len, - flags & USBH_HAL_XFER_DESC_FLAG_HOC, - flags & USBH_HAL_XFER_DESC_FLAG_SETUP); + flags & USB_DWC_HAL_XFER_DESC_FLAG_HOC, + flags & USB_DWC_HAL_XFER_DESC_FLAG_SETUP); } } @@ -722,10 +722,10 @@ static inline void usbh_hal_xfer_desc_fill(void *desc_list, uint32_t desc_idx, u * @param desc_list Transfer descriptor list * @param desc_idx Transfer descriptor index */ -static inline void usbh_hal_xfer_desc_clear(void *desc_list, uint32_t desc_idx) +static inline void usb_dwc_hal_xfer_desc_clear(void *desc_list, uint32_t desc_idx) { - usbh_ll_dma_qtd_t *qtd_list = (usbh_ll_dma_qtd_t *)desc_list; - usbh_ll_set_qtd_null(&qtd_list[desc_idx]); + usb_dwc_ll_dma_qtd_t *qtd_list = (usb_dwc_ll_dma_qtd_t *)desc_list; + usb_dwc_ll_qtd_set_null(&qtd_list[desc_idx]); } /** @@ -738,12 +738,12 @@ static inline void usbh_hal_xfer_desc_clear(void *desc_list, uint32_t desc_idx) * * @note Critical section is not required for this function */ -static inline void usbh_hal_xfer_desc_parse(void *desc_list, uint32_t desc_idx, int *xfer_rem_len, int *xfer_status) +static inline void usb_dwc_hal_xfer_desc_parse(void *desc_list, uint32_t desc_idx, int *xfer_rem_len, int *xfer_status) { - usbh_ll_dma_qtd_t *qtd_list = (usbh_ll_dma_qtd_t *)desc_list; - usbh_ll_get_qtd_status(&qtd_list[desc_idx], xfer_rem_len, xfer_status); + usb_dwc_ll_dma_qtd_t *qtd_list = (usb_dwc_ll_dma_qtd_t *)desc_list; + usb_dwc_ll_qtd_get_status(&qtd_list[desc_idx], xfer_rem_len, xfer_status); //Clear the QTD to prevent it from being read again - usbh_ll_set_qtd_null(&qtd_list[desc_idx]); + usb_dwc_ll_qtd_set_null(&qtd_list[desc_idx]); } // ------------------------------------------------- Event Handling ---------------------------------------------------- @@ -757,9 +757,9 @@ static inline void usbh_hal_xfer_desc_parse(void *desc_list, uint32_t desc_idx, * @note This should be the first interrupt decode function to be run * * @param hal Context of the HAL layer - * @return usbh_hal_port_event_t Host port event + * @return usb_dwc_hal_port_event_t Host port event */ -usbh_hal_port_event_t usbh_hal_decode_intr(usbh_hal_context_t *hal); +usb_dwc_hal_port_event_t usb_dwc_hal_decode_intr(usb_dwc_hal_context_t *hal); /** * @brief Gets the next channel with a pending interrupt @@ -768,9 +768,9 @@ usbh_hal_port_event_t usbh_hal_decode_intr(usbh_hal_context_t *hal); * interrupt, this function returns one of the channel's objects. Call this function repeatedly until it returns NULL. * * @param hal Context of the HAL layer - * @return usbh_hal_chan_t* Channel object. NULL if no channel are pending an interrupt. + * @return usb_dwc_hal_chan_t* Channel object. NULL if no channel are pending an interrupt. */ -usbh_hal_chan_t *usbh_hal_get_chan_pending_intr(usbh_hal_context_t *hal); +usb_dwc_hal_chan_t *usb_dwc_hal_get_chan_pending_intr(usb_dwc_hal_context_t *hal); /** * @brief Decode a particular channel's interrupt @@ -781,9 +781,9 @@ usbh_hal_chan_t *usbh_hal_get_chan_pending_intr(usbh_hal_context_t *hal); * @param chan_obj Channel object * @note If the host port has an error (e.g., a sudden disconnect or an port error), any active channels will not * receive an interrupt. Each active channel must be manually halted. - * @return usbh_hal_chan_event_t Channel event + * @return usb_dwc_hal_chan_event_t Channel event */ -usbh_hal_chan_event_t usbh_hal_chan_decode_intr(usbh_hal_chan_t *chan_obj); +usb_dwc_hal_chan_event_t usb_dwc_hal_chan_decode_intr(usb_dwc_hal_chan_t *chan_obj); #ifdef __cplusplus } diff --git a/components/hal/include/hal/usbh_ll.h b/components/hal/include/hal/usb_dwc_ll.h similarity index 59% rename from components/hal/include/hal/usbh_ll.h rename to components/hal/include/hal/usb_dwc_ll.h index 4320ead0a3..3bbaeca4c2 100644 --- a/components/hal/include/hal/usbh_ll.h +++ b/components/hal/include/hal/usb_dwc_ll.h @@ -12,7 +12,7 @@ extern "C" { #include #include -#include "soc/usbh_struct.h" +#include "soc/usb_dwc_struct.h" #include "hal/usb_types_private.h" #include "hal/misc.h" @@ -24,48 +24,48 @@ extern "C" { /* * Interrupt bit masks of the GINTSTS and GINTMSK registers */ -#define USB_LL_INTR_CORE_WKUPINT (1 << 31) -#define USB_LL_INTR_CORE_SESSREQINT (1 << 30) -#define USB_LL_INTR_CORE_DISCONNINT (1 << 29) -#define USB_LL_INTR_CORE_CONIDSTSCHNG (1 << 28) -#define USB_LL_INTR_CORE_PTXFEMP (1 << 26) -#define USB_LL_INTR_CORE_HCHINT (1 << 25) -#define USB_LL_INTR_CORE_PRTINT (1 << 24) -#define USB_LL_INTR_CORE_RESETDET (1 << 23) -#define USB_LL_INTR_CORE_FETSUSP (1 << 22) -#define USB_LL_INTR_CORE_INCOMPIP (1 << 21) -#define USB_LL_INTR_CORE_INCOMPISOIN (1 << 20) -#define USB_LL_INTR_CORE_OEPINT (1 << 19) -#define USB_LL_INTR_CORE_IEPINT (1 << 18) -#define USB_LL_INTR_CORE_EPMIS (1 << 17) -#define USB_LL_INTR_CORE_EOPF (1 << 15) -#define USB_LL_INTR_CORE_ISOOUTDROP (1 << 14) -#define USB_LL_INTR_CORE_ENUMDONE (1 << 13) -#define USB_LL_INTR_CORE_USBRST (1 << 12) -#define USB_LL_INTR_CORE_USBSUSP (1 << 11) -#define USB_LL_INTR_CORE_ERLYSUSP (1 << 10) -#define USB_LL_INTR_CORE_GOUTNAKEFF (1 << 7) -#define USB_LL_INTR_CORE_GINNAKEFF (1 << 6) -#define USB_LL_INTR_CORE_NPTXFEMP (1 << 5) -#define USB_LL_INTR_CORE_RXFLVL (1 << 4) -#define USB_LL_INTR_CORE_SOF (1 << 3) -#define USB_LL_INTR_CORE_OTGINT (1 << 2) -#define USB_LL_INTR_CORE_MODEMIS (1 << 1) -#define USB_LL_INTR_CORE_CURMOD (1 << 0) +#define USB_DWC_LL_INTR_CORE_WKUPINT (1 << 31) +#define USB_DWC_LL_INTR_CORE_SESSREQINT (1 << 30) +#define USB_DWC_LL_INTR_CORE_DISCONNINT (1 << 29) +#define USB_DWC_LL_INTR_CORE_CONIDSTSCHNG (1 << 28) +#define USB_DWC_LL_INTR_CORE_PTXFEMP (1 << 26) +#define USB_DWC_LL_INTR_CORE_HCHINT (1 << 25) +#define USB_DWC_LL_INTR_CORE_PRTINT (1 << 24) +#define USB_DWC_LL_INTR_CORE_RESETDET (1 << 23) +#define USB_DWC_LL_INTR_CORE_FETSUSP (1 << 22) +#define USB_DWC_LL_INTR_CORE_INCOMPIP (1 << 21) +#define USB_DWC_LL_INTR_CORE_INCOMPISOIN (1 << 20) +#define USB_DWC_LL_INTR_CORE_OEPINT (1 << 19) +#define USB_DWC_LL_INTR_CORE_IEPINT (1 << 18) +#define USB_DWC_LL_INTR_CORE_EPMIS (1 << 17) +#define USB_DWC_LL_INTR_CORE_EOPF (1 << 15) +#define USB_DWC_LL_INTR_CORE_ISOOUTDROP (1 << 14) +#define USB_DWC_LL_INTR_CORE_ENUMDONE (1 << 13) +#define USB_DWC_LL_INTR_CORE_USBRST (1 << 12) +#define USB_DWC_LL_INTR_CORE_USBSUSP (1 << 11) +#define USB_DWC_LL_INTR_CORE_ERLYSUSP (1 << 10) +#define USB_DWC_LL_INTR_CORE_GOUTNAKEFF (1 << 7) +#define USB_DWC_LL_INTR_CORE_GINNAKEFF (1 << 6) +#define USB_DWC_LL_INTR_CORE_NPTXFEMP (1 << 5) +#define USB_DWC_LL_INTR_CORE_RXFLVL (1 << 4) +#define USB_DWC_LL_INTR_CORE_SOF (1 << 3) +#define USB_DWC_LL_INTR_CORE_OTGINT (1 << 2) +#define USB_DWC_LL_INTR_CORE_MODEMIS (1 << 1) +#define USB_DWC_LL_INTR_CORE_CURMOD (1 << 0) /* * Bit mask of interrupt generating bits of the the HPRT register. These bits - * are ORd into the USB_LL_INTR_CORE_PRTINT interrupt. + * are ORd into the USB_DWC_LL_INTR_CORE_PRTINT interrupt. * * Note: Some fields of the HPRT are W1C (write 1 clear), this we cannot do a * simple read and write-back to clear the HPRT interrupt bits. Instead we need * a W1C mask the non-interrupt related bits */ -#define USBH_LL_HPRT_W1C_MSK (0x2E) -#define USBH_LL_HPRT_ENA_MSK (0x04) -#define USBH_LL_INTR_HPRT_PRTOVRCURRCHNG (1 << 5) -#define USBH_LL_INTR_HPRT_PRTENCHNG (1 << 3) -#define USBH_LL_INTR_HPRT_PRTCONNDET (1 << 1) +#define USB_DWC_LL_HPRT_W1C_MSK (0x2E) +#define USB_DWC_LL_HPRT_ENA_MSK (0x04) +#define USB_DWC_LL_INTR_HPRT_PRTOVRCURRCHNG (1 << 5) +#define USB_DWC_LL_INTR_HPRT_PRTENCHNG (1 << 3) +#define USB_DWC_LL_INTR_HPRT_PRTCONNDET (1 << 1) /* * Bit mask of channel interrupts (HCINTi and HCINTMSKi registers) @@ -78,22 +78,22 @@ extern "C" { * - XFERCOMPL * The remaining interrupt bits will still be set (when the corresponding event occurs) * but will not generate an interrupt. Therefore we must proxy through the - * USBH_LL_INTR_CHAN_CHHLTD interrupt to check the other interrupt bits. + * USB_DWC_LL_INTR_CHAN_CHHLTD interrupt to check the other interrupt bits. */ -#define USBH_LL_INTR_CHAN_DESC_LS_ROLL (1 << 13) -#define USBH_LL_INTR_CHAN_XCS_XACT_ERR (1 << 12) -#define USBH_LL_INTR_CHAN_BNAINTR (1 << 11) -#define USBH_LL_INTR_CHAN_DATATGLERR (1 << 10) -#define USBH_LL_INTR_CHAN_FRMOVRUN (1 << 9) -#define USBH_LL_INTR_CHAN_BBLEER (1 << 8) -#define USBH_LL_INTR_CHAN_XACTERR (1 << 7) -#define USBH_LL_INTR_CHAN_NYET (1 << 6) -#define USBH_LL_INTR_CHAN_ACK (1 << 5) -#define USBH_LL_INTR_CHAN_NAK (1 << 4) -#define USBH_LL_INTR_CHAN_STALL (1 << 3) -#define USBH_LL_INTR_CHAN_AHBERR (1 << 2) -#define USBH_LL_INTR_CHAN_CHHLTD (1 << 1) -#define USBH_LL_INTR_CHAN_XFERCOMPL (1 << 0) +#define USB_DWC_LL_INTR_CHAN_DESC_LS_ROLL (1 << 13) +#define USB_DWC_LL_INTR_CHAN_XCS_XACT_ERR (1 << 12) +#define USB_DWC_LL_INTR_CHAN_BNAINTR (1 << 11) +#define USB_DWC_LL_INTR_CHAN_DATATGLERR (1 << 10) +#define USB_DWC_LL_INTR_CHAN_FRMOVRUN (1 << 9) +#define USB_DWC_LL_INTR_CHAN_BBLEER (1 << 8) +#define USB_DWC_LL_INTR_CHAN_XACTERR (1 << 7) +#define USB_DWC_LL_INTR_CHAN_NYET (1 << 6) +#define USB_DWC_LL_INTR_CHAN_ACK (1 << 5) +#define USB_DWC_LL_INTR_CHAN_NAK (1 << 4) +#define USB_DWC_LL_INTR_CHAN_STALL (1 << 3) +#define USB_DWC_LL_INTR_CHAN_AHBERR (1 << 2) +#define USB_DWC_LL_INTR_CHAN_CHHLTD (1 << 1) +#define USB_DWC_LL_INTR_CHAN_XFERCOMPL (1 << 0) /* * QTD (Queue Transfer Descriptor) structure used in Scatter/Gather DMA mode. @@ -150,7 +150,7 @@ typedef struct { uint32_t buffer_status_val; }; uint8_t *buffer; -} usbh_ll_dma_qtd_t; +} usb_dwc_ll_dma_qtd_t; /* ----------------------------------------------------------------------------- @@ -159,61 +159,61 @@ typedef struct { // --------------------------- GAHBCFG Register -------------------------------- -static inline void usb_ll_en_dma_mode(usbh_dev_t *hw) +static inline void usb_dwc_ll_gahbcfg_en_dma_mode(usb_dwc_dev_t *hw) { hw->gahbcfg_reg.dmaen = 1; } -static inline void usb_ll_en_slave_mode(usbh_dev_t *hw) +static inline void usb_dwc_ll_gahbcfg_en_slave_mode(usb_dwc_dev_t *hw) { hw->gahbcfg_reg.dmaen = 0; } -static inline void usb_ll_set_hbstlen(usbh_dev_t *hw, uint32_t burst_len) +static inline void usb_dwc_ll_gahbcfg_set_hbstlen(usb_dwc_dev_t *hw, uint32_t burst_len) { hw->gahbcfg_reg.hbstlen = burst_len; } -static inline void usb_ll_en_global_intr(usbh_dev_t *hw) +static inline void usb_dwc_ll_gahbcfg_en_global_intr(usb_dwc_dev_t *hw) { hw->gahbcfg_reg.glbllntrmsk = 1; } -static inline void usb_ll_dis_global_intr(usbh_dev_t *hw) +static inline void usb_dwc_ll_gahbcfg_dis_global_intr(usb_dwc_dev_t *hw) { hw->gahbcfg_reg.glbllntrmsk = 0; } // --------------------------- GUSBCFG Register -------------------------------- -static inline void usb_ll_set_host_mode(usbh_dev_t *hw) +static inline void usb_dwc_ll_gusbcfg_force_host_mode(usb_dwc_dev_t *hw) { hw->gusbcfg_reg.forcehstmode = 1; } -static inline void usb_ll_dis_hnp_cap(usbh_dev_t *hw) +static inline void usb_dwc_ll_gusbcfg_dis_hnp_cap(usb_dwc_dev_t *hw) { hw->gusbcfg_reg.hnpcap = 0; } -static inline void usb_ll_dis_srp_cap(usbh_dev_t *hw) +static inline void usb_dwc_ll_gusbcfg_dis_srp_cap(usb_dwc_dev_t *hw) { hw->gusbcfg_reg.srpcap = 0; } // --------------------------- GRSTCTL Register -------------------------------- -static inline bool usb_ll_check_ahb_idle(usbh_dev_t *hw) +static inline bool usb_dwc_ll_grstctl_is_ahb_idle(usb_dwc_dev_t *hw) { return hw->grstctl_reg.ahbidle; } -static inline bool usb_ll_check_dma_req_in_progress(usbh_dev_t *hw) +static inline bool usb_dwc_ll_grstctl_is_dma_req_in_progress(usb_dwc_dev_t *hw) { return hw->grstctl_reg.dmareq; } -static inline void usb_ll_flush_nptx_fifo(usbh_dev_t *hw) +static inline void usb_dwc_ll_grstctl_flush_nptx_fifo(usb_dwc_dev_t *hw) { hw->grstctl_reg.txfnum = 0; //Set the TX FIFO number to 0 to select the non-periodic TX FIFO hw->grstctl_reg.txfflsh = 1; //Flush the selected TX FIFO @@ -223,7 +223,7 @@ static inline void usb_ll_flush_nptx_fifo(usbh_dev_t *hw) } } -static inline void usb_ll_flush_ptx_fifo(usbh_dev_t *hw) +static inline void usb_dwc_ll_grstctl_flush_ptx_fifo(usb_dwc_dev_t *hw) { hw->grstctl_reg.txfnum = 1; //Set the TX FIFO number to 1 to select the periodic TX FIFO hw->grstctl_reg.txfflsh = 1; //FLush the select TX FIFO @@ -233,7 +233,7 @@ static inline void usb_ll_flush_ptx_fifo(usbh_dev_t *hw) } } -static inline void usb_ll_flush_rx_fifo(usbh_dev_t *hw) +static inline void usb_dwc_ll_grstctl_flush_rx_fifo(usb_dwc_dev_t *hw) { hw->grstctl_reg.rxfflsh = 1; //Wait for the flushing to complete @@ -242,17 +242,17 @@ static inline void usb_ll_flush_rx_fifo(usbh_dev_t *hw) } } -static inline void usb_ll_reset_frame_counter(usbh_dev_t *hw) +static inline void usb_dwc_ll_grstctl_reset_frame_counter(usb_dwc_dev_t *hw) { hw->grstctl_reg.frmcntrrst = 1; } -static inline void usb_ll_core_soft_reset(usbh_dev_t *hw) +static inline void usb_dwc_ll_grstctl_core_soft_reset(usb_dwc_dev_t *hw) { hw->grstctl_reg.csftrst = 1; } -static inline bool usb_ll_check_core_soft_reset(usbh_dev_t *hw) +static inline bool usb_dwc_ll_grstctl_is_core_soft_reset_in_progress(usb_dwc_dev_t *hw) { return hw->grstctl_reg.csftrst; } @@ -265,9 +265,9 @@ static inline bool usb_ll_check_core_soft_reset(usbh_dev_t *hw) * @param hw Start address of the DWC_OTG registers * @return uint32_t Mask of interrupts */ -static inline uint32_t usb_ll_intr_read_and_clear(usbh_dev_t *hw) +static inline uint32_t usb_dwc_ll_gintsts_read_and_clear_intrs(usb_dwc_dev_t *hw) { - usb_gintsts_reg_t gintsts; + usb_dwc_gintsts_reg_t gintsts; gintsts.val = hw->gintsts_reg.val; hw->gintsts_reg.val = gintsts.val; //Write back to clear return gintsts.val; @@ -279,7 +279,7 @@ static inline uint32_t usb_ll_intr_read_and_clear(usbh_dev_t *hw) * @param hw Start address of the DWC_OTG registers * @param intr_msk Mask of interrupts to clear */ -static inline void usb_ll_intr_clear(usbh_dev_t *hw, uint32_t intr_msk) +static inline void usb_dwc_ll_gintsts_clear_intrs(usb_dwc_dev_t *hw, uint32_t intr_msk) { //All GINTSTS fields are either W1C or read only. So safe to write directly hw->gintsts_reg.val = intr_msk; @@ -287,19 +287,19 @@ static inline void usb_ll_intr_clear(usbh_dev_t *hw, uint32_t intr_msk) // --------------------------- GINTMSK Register -------------------------------- -static inline void usb_ll_en_intrs(usbh_dev_t *hw, uint32_t intr_mask) +static inline void usb_dwc_ll_gintmsk_en_intrs(usb_dwc_dev_t *hw, uint32_t intr_mask) { hw->gintmsk_reg.val |= intr_mask; } -static inline void usb_ll_dis_intrs(usbh_dev_t *hw, uint32_t intr_mask) +static inline void usb_dwc_ll_gintmsk_dis_intrs(usb_dwc_dev_t *hw, uint32_t intr_mask) { hw->gintmsk_reg.val &= ~intr_mask; } // --------------------------- GRXFSIZ Register -------------------------------- -static inline void usb_ll_set_rx_fifo_size(usbh_dev_t *hw, uint32_t num_lines) +static inline void usb_dwc_ll_grxfsiz_set_fifo_size(usb_dwc_dev_t *hw, uint32_t num_lines) { //Set size in words HAL_FORCE_MODIFY_U32_REG_FIELD(hw->grxfsiz_reg, rxfdep, num_lines); @@ -307,20 +307,24 @@ static inline void usb_ll_set_rx_fifo_size(usbh_dev_t *hw, uint32_t num_lines) // -------------------------- GNPTXFSIZ Register ------------------------------- -static inline void usb_ll_set_nptx_fifo_size(usbh_dev_t *hw, uint32_t addr, uint32_t num_lines) +static inline void usb_dwc_ll_gnptxfsiz_set_fifo_size(usb_dwc_dev_t *hw, uint32_t addr, uint32_t num_lines) { - usb_gnptxfsiz_reg_t gnptxfsiz; + usb_dwc_gnptxfsiz_reg_t gnptxfsiz; gnptxfsiz.val = hw->gnptxfsiz_reg.val; HAL_FORCE_MODIFY_U32_REG_FIELD(gnptxfsiz, nptxfstaddr, addr); HAL_FORCE_MODIFY_U32_REG_FIELD(gnptxfsiz, nptxfdep, num_lines); hw->gnptxfsiz_reg.val = gnptxfsiz.val; } -static inline uint32_t usb_ll_get_controller_core_id(usbh_dev_t *hw) +// --------------------------- GSNPSID Register -------------------------------- + +static inline uint32_t usb_dwc_ll_gsnpsid_get_id(usb_dwc_dev_t *hw) { return hw->gsnpsid_reg.val; } +// --------------------------- GHWCFGx Register -------------------------------- + /** * @brief Get the hardware configuration regiters of the DWC_OTG controller * @@ -333,7 +337,7 @@ static inline uint32_t usb_ll_get_controller_core_id(usbh_dev_t *hw) * @param[out] ghwcfg3 Hardware configuration registesr 3 * @param[out] ghwcfg4 Hardware configuration registesr 4 */ -static inline void usb_ll_get_hardware_config(usbh_dev_t *hw, uint32_t *ghwcfg1, uint32_t *ghwcfg2, uint32_t *ghwcfg3, uint32_t *ghwcfg4) +static inline void usb_dwc_ll_ghwcfg_get_hw_config(usb_dwc_dev_t *hw, uint32_t *ghwcfg1, uint32_t *ghwcfg2, uint32_t *ghwcfg3, uint32_t *ghwcfg4) { *ghwcfg1 = hw->ghwcfg1_reg.val; *ghwcfg2 = hw->ghwcfg2_reg.val; @@ -343,9 +347,9 @@ static inline void usb_ll_get_hardware_config(usbh_dev_t *hw, uint32_t *ghwcfg1, // --------------------------- HPTXFSIZ Register ------------------------------- -static inline void usbh_ll_set_ptx_fifo_size(usbh_dev_t *hw, uint32_t addr, uint32_t num_lines) +static inline void usb_dwc_ll_hptxfsiz_set_ptx_fifo_size(usb_dwc_dev_t *hw, uint32_t addr, uint32_t num_lines) { - usb_hptxfsiz_reg_t hptxfsiz; + usb_dwc_hptxfsiz_reg_t hptxfsiz; hptxfsiz.val = hw->hptxfsiz_reg.val; HAL_FORCE_MODIFY_U32_REG_FIELD(hptxfsiz, ptxfstaddr, addr); HAL_FORCE_MODIFY_U32_REG_FIELD(hptxfsiz, ptxfsize, num_lines); @@ -358,12 +362,12 @@ static inline void usbh_ll_set_ptx_fifo_size(usbh_dev_t *hw, uint32_t addr, uint // ----------------------------- HCFG Register --------------------------------- -static inline void usbh_ll_hcfg_en_perio_sched(usbh_dev_t *hw) +static inline void usb_dwc_ll_hcfg_en_perio_sched(usb_dwc_dev_t *hw) { hw->hcfg_reg.perschedena = 1; } -static inline void usbh_ll_hcfg_dis_perio_sched(usbh_dev_t *hw) +static inline void usb_dwc_ll_hcfg_dis_perio_sched(usb_dwc_dev_t *hw) { hw->hcfg_reg.perschedena = 0; } @@ -373,7 +377,7 @@ static inline void usbh_ll_hcfg_dis_perio_sched(usbh_dev_t *hw) * * @param num_entires Number of entires in the frame list */ -static inline void usbh_ll_hcfg_set_num_frame_list_entries(usbh_dev_t *hw, usb_hal_frame_list_len_t num_entries) +static inline void usb_dwc_ll_hcfg_set_num_frame_list_entries(usb_dwc_dev_t *hw, usb_hal_frame_list_len_t num_entries) { uint32_t frlisten; switch (num_entries) { @@ -393,17 +397,17 @@ static inline void usbh_ll_hcfg_set_num_frame_list_entries(usbh_dev_t *hw, usb_h hw->hcfg_reg.frlisten = frlisten; } -static inline void usbh_ll_hcfg_en_scatt_gatt_dma(usbh_dev_t *hw) +static inline void usb_dwc_ll_hcfg_en_scatt_gatt_dma(usb_dwc_dev_t *hw) { hw->hcfg_reg.descdma = 1; } -static inline void usbh_ll_hcfg_set_fsls_supp_only(usbh_dev_t *hw) +static inline void usb_dwc_ll_hcfg_set_fsls_supp_only(usb_dwc_dev_t *hw) { hw->hcfg_reg.fslssupp = 1; } -static inline void usbh_ll_hcfg_set_fsls_pclk_sel(usbh_dev_t *hw) +static inline void usb_dwc_ll_hcfg_set_fsls_pclk_sel(usb_dwc_dev_t *hw) { hw->hcfg_reg.fslspclksel = 1; } @@ -414,7 +418,7 @@ static inline void usbh_ll_hcfg_set_fsls_pclk_sel(usbh_dev_t *hw) * @param hw Start address of the DWC_OTG registers * @param speed Speed to initialize the host port at */ -static inline void usbh_ll_hcfg_set_defaults(usbh_dev_t *hw, usb_priv_speed_t speed) +static inline void usb_dwc_ll_hcfg_set_defaults(usb_dwc_dev_t *hw, usb_priv_speed_t speed) { hw->hcfg_reg.descdma = 1; //Enable scatt/gatt hw->hcfg_reg.fslssupp = 1; //FS/LS support only @@ -429,9 +433,9 @@ static inline void usbh_ll_hcfg_set_defaults(usbh_dev_t *hw, usb_priv_speed_t sp // ----------------------------- HFIR Register --------------------------------- -static inline void usbh_ll_hfir_set_defaults(usbh_dev_t *hw, usb_priv_speed_t speed) +static inline void usb_dwc_ll_hfir_set_defaults(usb_dwc_dev_t *hw, usb_priv_speed_t speed) { - usb_hfir_reg_t hfir; + usb_dwc_hfir_reg_t hfir; hfir.val = hw->hfir_reg.val; hfir.hfirrldctrl = 0; //Disable dynamic loading /* @@ -445,49 +449,49 @@ static inline void usbh_ll_hfir_set_defaults(usbh_dev_t *hw, usb_priv_speed_t sp // ----------------------------- HFNUM Register -------------------------------- -static inline uint32_t usbh_ll_get_frm_time_rem(usbh_dev_t *hw) +static inline uint32_t usb_dwc_ll_hfnum_get_frame_time_rem(usb_dwc_dev_t *hw) { return HAL_FORCE_READ_U32_REG_FIELD(hw->hfnum_reg, frrem); } -static inline uint32_t usbh_ll_get_frm_num(usbh_dev_t *hw) +static inline uint32_t usb_dwc_ll_hfnum_get_frame_num(usb_dwc_dev_t *hw) { return hw->hfnum_reg.frnum; } // ---------------------------- HPTXSTS Register ------------------------------- -static inline uint32_t usbh_ll_get_p_tx_queue_top(usbh_dev_t *hw) +static inline uint32_t usb_dwc_ll_hptxsts_get_ptxq_top(usb_dwc_dev_t *hw) { return HAL_FORCE_READ_U32_REG_FIELD(hw->hptxsts_reg, ptxqtop); } -static inline uint32_t usbh_ll_get_p_tx_queue_space_avail(usbh_dev_t *hw) +static inline uint32_t usb_dwc_ll_hptxsts_get_ptxq_space_avail(usb_dwc_dev_t *hw) { return hw->hptxsts_reg.ptxqspcavail; } -static inline uint32_t usbh_ll_get_p_tx_fifo_space_avail(usbh_dev_t *hw) +static inline uint32_t usb_dwc_ll_ptxsts_get_ptxf_space_avail(usb_dwc_dev_t *hw) { return HAL_FORCE_READ_U32_REG_FIELD(hw->hptxsts_reg, ptxfspcavail); } // ----------------------------- HAINT Register -------------------------------- -static inline uint32_t usbh_ll_get_chan_intrs_msk(usbh_dev_t *hw) +static inline uint32_t usb_dwc_ll_haint_get_chan_intrs(usb_dwc_dev_t *hw) { return HAL_FORCE_READ_U32_REG_FIELD(hw->haint_reg, haint); } // --------------------------- HAINTMSK Register ------------------------------- -static inline void usbh_ll_haintmsk_en_chan_intr(usbh_dev_t *hw, uint32_t mask) +static inline void usb_dwc_ll_haintmsk_en_chan_intr(usb_dwc_dev_t *hw, uint32_t mask) { hw->haintmsk_reg.val |= mask; } -static inline void usbh_ll_haintmsk_dis_chan_intr(usbh_dev_t *hw, uint32_t mask) +static inline void usb_dwc_ll_haintmsk_dis_chan_intr(usb_dwc_dev_t *hw, uint32_t mask) { hw->haintmsk_reg.val &= ~mask; } @@ -504,7 +508,7 @@ static inline void usbh_ll_haintmsk_dis_chan_intr(usbh_dev_t *hw, uint32_t mask) * @param hw Start address of the DWC_OTG registers * @param addr Base address of the scheduling frame list */ -static inline void usbh_ll_set_frame_list_base_addr(usbh_dev_t *hw, uint32_t addr) +static inline void usb_dwc_ll_hflbaddr_set_base_addr(usb_dwc_dev_t *hw, uint32_t addr) { hw->hflbaddr_reg.hflbaddr = addr; } @@ -515,14 +519,14 @@ static inline void usbh_ll_set_frame_list_base_addr(usbh_dev_t *hw, uint32_t add * @param hw Start address of the DWC_OTG registers * @return uint32_t Base address of the scheduling frame list */ -static inline uint32_t usbh_ll_get_frame_list_base_addr(usbh_dev_t *hw) +static inline uint32_t usb_dwc_ll_hflbaddr_get_base_addr(usb_dwc_dev_t *hw) { return hw->hflbaddr_reg.hflbaddr; } // ----------------------------- HPRT Register --------------------------------- -static inline usb_priv_speed_t usbh_ll_hprt_get_speed(usbh_dev_t *hw) +static inline usb_priv_speed_t usb_dwc_ll_hprt_get_speed(usb_dwc_dev_t *hw) { usb_priv_speed_t speed; //esp32-s2 and esp32-s3 only support FS or LS @@ -537,163 +541,163 @@ static inline usb_priv_speed_t usbh_ll_hprt_get_speed(usbh_dev_t *hw) return speed; } -static inline uint32_t usbh_ll_hprt_get_test_ctl(usbh_dev_t *hw) +static inline uint32_t usb_dwc_ll_hprt_get_test_ctl(usb_dwc_dev_t *hw) { return hw->hprt_reg.prttstctl; } -static inline void usbh_ll_hprt_set_test_ctl(usbh_dev_t *hw, uint32_t test_mode) +static inline void usb_dwc_ll_hprt_set_test_ctl(usb_dwc_dev_t *hw, uint32_t test_mode) { - usb_hprt_reg_t hprt; + usb_dwc_hprt_reg_t hprt; hprt.val = hw->hprt_reg.val; hprt.prttstctl = test_mode; - hw->hprt_reg.val = hprt.val & (~USBH_LL_HPRT_W1C_MSK); + hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK); } -static inline void usbh_ll_hprt_en_pwr(usbh_dev_t *hw) +static inline void usb_dwc_ll_hprt_en_pwr(usb_dwc_dev_t *hw) { - usb_hprt_reg_t hprt; + usb_dwc_hprt_reg_t hprt; hprt.val = hw->hprt_reg.val; hprt.prtpwr = 1; - hw->hprt_reg.val = hprt.val & (~USBH_LL_HPRT_W1C_MSK); + hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK); } -static inline void usbh_ll_hprt_dis_pwr(usbh_dev_t *hw) +static inline void usb_dwc_ll_hprt_dis_pwr(usb_dwc_dev_t *hw) { - usb_hprt_reg_t hprt; + usb_dwc_hprt_reg_t hprt; hprt.val = hw->hprt_reg.val; hprt.prtpwr = 0; - hw->hprt_reg.val = hprt.val & (~USBH_LL_HPRT_W1C_MSK); + hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK); } -static inline uint32_t usbh_ll_hprt_get_pwr_line_status(usbh_dev_t *hw) +static inline uint32_t usb_dwc_ll_hprt_get_pwr_line_status(usb_dwc_dev_t *hw) { return hw->hprt_reg.prtlnsts; } -static inline void usbh_ll_hprt_set_port_reset(usbh_dev_t *hw, bool reset) +static inline void usb_dwc_ll_hprt_set_port_reset(usb_dwc_dev_t *hw, bool reset) { - usb_hprt_reg_t hprt; + usb_dwc_hprt_reg_t hprt; hprt.val = hw->hprt_reg.val; hprt.prtrst = reset; - hw->hprt_reg.val = hprt.val & (~USBH_LL_HPRT_W1C_MSK); + hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK); } -static inline bool usbh_ll_hprt_get_port_reset(usbh_dev_t *hw) +static inline bool usb_dwc_ll_hprt_get_port_reset(usb_dwc_dev_t *hw) { return hw->hprt_reg.prtrst; } -static inline void usbh_ll_hprt_set_port_suspend(usbh_dev_t *hw) +static inline void usb_dwc_ll_hprt_set_port_suspend(usb_dwc_dev_t *hw) { - usb_hprt_reg_t hprt; + usb_dwc_hprt_reg_t hprt; hprt.val = hw->hprt_reg.val; hprt.prtsusp = 1; - hw->hprt_reg.val = hprt.val & (~USBH_LL_HPRT_W1C_MSK); + hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK); } -static inline bool usbh_ll_hprt_get_port_suspend(usbh_dev_t *hw) +static inline bool usb_dwc_ll_hprt_get_port_suspend(usb_dwc_dev_t *hw) { return hw->hprt_reg.prtsusp; } -static inline void usbh_ll_hprt_set_port_resume(usbh_dev_t *hw) +static inline void usb_dwc_ll_hprt_set_port_resume(usb_dwc_dev_t *hw) { - usb_hprt_reg_t hprt; + usb_dwc_hprt_reg_t hprt; hprt.val = hw->hprt_reg.val; hprt.prtres = 1; - hw->hprt_reg.val = hprt.val & (~USBH_LL_HPRT_W1C_MSK); + hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK); } -static inline void usbh_ll_hprt_clr_port_resume(usbh_dev_t *hw) +static inline void usb_dwc_ll_hprt_clr_port_resume(usb_dwc_dev_t *hw) { - usb_hprt_reg_t hprt; + usb_dwc_hprt_reg_t hprt; hprt.val = hw->hprt_reg.val; hprt.prtres = 0; - hw->hprt_reg.val = hprt.val & (~USBH_LL_HPRT_W1C_MSK); + hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK); } -static inline bool usbh_ll_hprt_get_port_resume(usbh_dev_t *hw) +static inline bool usb_dwc_ll_hprt_get_port_resume(usb_dwc_dev_t *hw) { return hw->hprt_reg.prtres; } -static inline bool usbh_ll_hprt_get_port_overcur(usbh_dev_t *hw) +static inline bool usb_dwc_ll_hprt_get_port_overcur(usb_dwc_dev_t *hw) { return hw->hprt_reg.prtovrcurract; } -static inline bool usbh_ll_hprt_get_port_en(usbh_dev_t *hw) +static inline bool usb_dwc_ll_hprt_get_port_en(usb_dwc_dev_t *hw) { return hw->hprt_reg.prtena; } -static inline void usbh_ll_hprt_port_dis(usbh_dev_t *hw) +static inline void usb_dwc_ll_hprt_port_dis(usb_dwc_dev_t *hw) { - usb_hprt_reg_t hprt; + usb_dwc_hprt_reg_t hprt; hprt.val = hw->hprt_reg.val; hprt.prtena = 1; //W1C to disable //we want to W1C ENA but not W1C the interrupt bits - hw->hprt_reg.val = hprt.val & ((~USBH_LL_HPRT_W1C_MSK) | USBH_LL_HPRT_ENA_MSK); + hw->hprt_reg.val = hprt.val & ((~USB_DWC_LL_HPRT_W1C_MSK) | USB_DWC_LL_HPRT_ENA_MSK); } -static inline bool usbh_ll_hprt_get_conn_status(usbh_dev_t *hw) +static inline bool usb_dwc_ll_hprt_get_conn_status(usb_dwc_dev_t *hw) { return hw->hprt_reg.prtconnsts; } -static inline uint32_t usbh_ll_hprt_intr_read_and_clear(usbh_dev_t *hw) +static inline uint32_t usb_dwc_ll_hprt_intr_read_and_clear(usb_dwc_dev_t *hw) { - usb_hprt_reg_t hprt; + usb_dwc_hprt_reg_t hprt; hprt.val = hw->hprt_reg.val; //We want to W1C the interrupt bits but not that ENA - hw->hprt_reg.val = hprt.val & (~USBH_LL_HPRT_ENA_MSK); + hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_ENA_MSK); //Return only the interrupt bits - return (hprt.val & (USBH_LL_HPRT_W1C_MSK & ~(USBH_LL_HPRT_ENA_MSK))); + return (hprt.val & (USB_DWC_LL_HPRT_W1C_MSK & ~(USB_DWC_LL_HPRT_ENA_MSK))); } -static inline void usbh_ll_hprt_intr_clear(usbh_dev_t *hw, uint32_t intr_mask) +static inline void usb_dwc_ll_hprt_intr_clear(usb_dwc_dev_t *hw, uint32_t intr_mask) { - usb_hprt_reg_t hprt; + usb_dwc_hprt_reg_t hprt; hprt.val = hw->hprt_reg.val; - hw->hprt_reg.val = ((hprt.val & ~USBH_LL_HPRT_ENA_MSK) & ~USBH_LL_HPRT_W1C_MSK) | intr_mask; + hw->hprt_reg.val = ((hprt.val & ~USB_DWC_LL_HPRT_ENA_MSK) & ~USB_DWC_LL_HPRT_W1C_MSK) | intr_mask; } //Per Channel registers // --------------------------- HCCHARi Register -------------------------------- -static inline void usbh_ll_chan_start(volatile usb_host_chan_regs_t *chan) +static inline void usb_dwc_ll_hcchar_enable_chan(volatile usb_dwc_host_chan_regs_t *chan) { chan->hcchar_reg.chena = 1; } -static inline bool usbh_ll_chan_is_active(volatile usb_host_chan_regs_t *chan) +static inline bool usb_dwc_ll_hcchar_chan_is_enabled(volatile usb_dwc_host_chan_regs_t *chan) { return chan->hcchar_reg.chena; } -static inline void usbh_ll_chan_halt(volatile usb_host_chan_regs_t *chan) +static inline void usb_dwc_ll_hcchar_disable_chan(volatile usb_dwc_host_chan_regs_t *chan) { chan->hcchar_reg.chdis = 1; } -static inline void usbh_ll_chan_xfer_odd_frame(volatile usb_host_chan_regs_t *chan) +static inline void usb_dwc_ll_hcchar_set_odd_frame(volatile usb_dwc_host_chan_regs_t *chan) { chan->hcchar_reg.oddfrm = 1; } -static inline void usbh_ll_chan_xfer_even_frame(volatile usb_host_chan_regs_t *chan) +static inline void usb_dwc_ll_hcchar_set_even_frame(volatile usb_dwc_host_chan_regs_t *chan) { chan->hcchar_reg.oddfrm = 0; } -static inline void usbh_ll_chan_set_dev_addr(volatile usb_host_chan_regs_t *chan, uint32_t addr) +static inline void usb_dwc_ll_hcchar_set_dev_addr(volatile usb_dwc_host_chan_regs_t *chan, uint32_t addr) { chan->hcchar_reg.devaddr = addr; } -static inline void usbh_ll_chan_set_ep_type(volatile usb_host_chan_regs_t *chan, usb_priv_xfer_type_t type) +static inline void usb_dwc_ll_hcchar_set_ep_type(volatile usb_dwc_host_chan_regs_t *chan, usb_priv_xfer_type_t type) { uint32_t ep_type; switch (type) { @@ -715,42 +719,42 @@ static inline void usbh_ll_chan_set_ep_type(volatile usb_host_chan_regs_t *chan, //Indicates whether channel is commuunicating with a LS device connected via a FS hub. Setting this bit to 1 will cause //each packet to be preceded by a PREamble packet -static inline void usbh_ll_chan_set_lspddev(volatile usb_host_chan_regs_t *chan, bool is_ls) +static inline void usb_dwc_ll_hcchar_set_lspddev(volatile usb_dwc_host_chan_regs_t *chan, bool is_ls) { chan->hcchar_reg.lspddev = is_ls; } -static inline void usbh_ll_chan_set_dir(volatile usb_host_chan_regs_t *chan, bool is_in) +static inline void usb_dwc_ll_hcchar_set_dir(volatile usb_dwc_host_chan_regs_t *chan, bool is_in) { chan->hcchar_reg.epdir = is_in; } -static inline void usbh_ll_chan_set_ep_num(volatile usb_host_chan_regs_t *chan, uint32_t num) +static inline void usb_dwc_ll_hcchar_set_ep_num(volatile usb_dwc_host_chan_regs_t *chan, uint32_t num) { chan->hcchar_reg.epnum = num; } -static inline void usbh_ll_chan_set_mps(volatile usb_host_chan_regs_t *chan, uint32_t mps) +static inline void usb_dwc_ll_hcchar_set_mps(volatile usb_dwc_host_chan_regs_t *chan, uint32_t mps) { chan->hcchar_reg.mps = mps; } -static inline void usbh_ll_chan_hcchar_init(volatile usb_host_chan_regs_t *chan, int dev_addr, int ep_num, int mps, usb_priv_xfer_type_t type, bool is_in, bool is_ls) +static inline void usb_dwc_ll_hcchar_init(volatile usb_dwc_host_chan_regs_t *chan, int dev_addr, int ep_num, int mps, usb_priv_xfer_type_t type, bool is_in, bool is_ls) { //Sets all persistent fields of the channel over its lifetimez - usbh_ll_chan_set_dev_addr(chan, dev_addr); - usbh_ll_chan_set_ep_type(chan, type); - usbh_ll_chan_set_lspddev(chan, is_ls); - usbh_ll_chan_set_dir(chan, is_in); - usbh_ll_chan_set_ep_num(chan, ep_num); - usbh_ll_chan_set_mps(chan, mps); + usb_dwc_ll_hcchar_set_dev_addr(chan, dev_addr); + usb_dwc_ll_hcchar_set_ep_type(chan, type); + usb_dwc_ll_hcchar_set_lspddev(chan, is_ls); + usb_dwc_ll_hcchar_set_dir(chan, is_in); + usb_dwc_ll_hcchar_set_ep_num(chan, ep_num); + usb_dwc_ll_hcchar_set_mps(chan, mps); } // ---------------------------- HCINTi Register -------------------------------- -static inline uint32_t usbh_ll_chan_intr_read_and_clear(volatile usb_host_chan_regs_t *chan) +static inline uint32_t usb_dwc_ll_hcint_read_and_clear_intrs(volatile usb_dwc_host_chan_regs_t *chan) { - usb_hcint_reg_t hcint; + usb_dwc_hcint_reg_t hcint; hcint.val = chan->hcint_reg.val; chan->hcint_reg.val = hcint.val; return hcint.val; @@ -758,14 +762,14 @@ static inline uint32_t usbh_ll_chan_intr_read_and_clear(volatile usb_host_chan_r // --------------------------- HCINTMSKi Register ------------------------------ -static inline void usbh_ll_chan_set_intr_mask(volatile usb_host_chan_regs_t *chan, uint32_t mask) +static inline void usb_dwc_ll_hcintmsk_set_intr_mask(volatile usb_dwc_host_chan_regs_t *chan, uint32_t mask) { chan->hcintmsk_reg.val = mask; } -// ---------------------- HCTSIZi and HCDMAi Registers ------------------------- +// ---------------------------- HCTSIZi Register ------------------------------- -static inline void usbh_ll_chan_set_pid(volatile usb_host_chan_regs_t *chan, uint32_t data_pid) +static inline void usb_dwc_ll_hctsiz_set_pid(volatile usb_dwc_host_chan_regs_t *chan, uint32_t data_pid) { if (data_pid == 0) { chan->hctsiz_reg.pid = 0; @@ -774,7 +778,8 @@ static inline void usbh_ll_chan_set_pid(volatile usb_host_chan_regs_t *chan, uin } } -static inline uint32_t usbh_ll_chan_get_pid(volatile usb_host_chan_regs_t *chan) { +static inline uint32_t usb_dwc_ll_hctsiz_get_pid(volatile usb_dwc_host_chan_regs_t *chan) +{ if (chan->hctsiz_reg.pid == 0) { return 0; //DATA0 } else { @@ -782,9 +787,20 @@ static inline uint32_t usbh_ll_chan_get_pid(volatile usb_host_chan_regs_t *chan) } } -static inline void usbh_ll_chan_set_dma_addr_non_iso(volatile usb_host_chan_regs_t *chan, - void *dmaaddr, - uint32_t qtd_idx) +static inline void usb_dwc_ll_hctsiz_set_qtd_list_len(volatile usb_dwc_host_chan_regs_t *chan, int qtd_list_len) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(chan->hctsiz_reg, ntd, qtd_list_len - 1); //Set the length of the descriptor list +} + +static inline void usb_dwc_ll_hctsiz_init(volatile usb_dwc_host_chan_regs_t *chan) +{ + chan->hctsiz_reg.dopng = 0; //Don't do ping + HAL_FORCE_MODIFY_U32_REG_FIELD(chan->hctsiz_reg, sched_info, 0xFF); //Schedinfo is always 0xFF for fullspeed. Not used in Bulk/Ctrl channels +} + +// ---------------------------- HCDMAi Register -------------------------------- + +static inline void usb_dwc_ll_hcdma_set_qtd_list_addr(volatile usb_dwc_host_chan_regs_t *chan, void *dmaaddr, uint32_t qtd_idx) { //Set HCDMAi chan->hcdma_reg.val = 0; @@ -792,25 +808,14 @@ static inline void usbh_ll_chan_set_dma_addr_non_iso(volatile usb_host_chan_regs chan->hcdma_reg.non_iso.ctd = qtd_idx; } -static inline int usbh_ll_chan_get_ctd(usb_host_chan_regs_t *chan) +static inline int usb_dwc_ll_hcdam_get_cur_qtd_idx(usb_dwc_host_chan_regs_t *chan) { return chan->hcdma_reg.non_iso.ctd; } -static inline void usbh_ll_chan_hctsiz_init(volatile usb_host_chan_regs_t *chan) -{ - chan->hctsiz_reg.dopng = 0; //Don't do ping - HAL_FORCE_MODIFY_U32_REG_FIELD(chan->hctsiz_reg, sched_info, 0xFF); //Schedinfo is always 0xFF for fullspeed. Not used in Bulk/Ctrl channels -} - -static inline void usbh_ll_chan_set_qtd_list_len(volatile usb_host_chan_regs_t *chan, int qtd_list_len) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(chan->hctsiz_reg, ntd, qtd_list_len - 1); //Set the length of the descriptor list -} - // ---------------------------- HCDMABi Register ------------------------------- -static inline void *usbh_ll_chan_get_cur_buff_addr(volatile usb_host_chan_regs_t *chan) +static inline void *usb_dwc_ll_hcdmab_get_buff_addr(volatile usb_dwc_host_chan_regs_t *chan) { return (void *)chan->hcdmab_reg.hcdmab; } @@ -826,20 +831,20 @@ static inline void *usbh_ll_chan_get_cur_buff_addr(volatile usb_host_chan_regs_t * * @param dev Start address of the DWC_OTG registers * @param chan_idx The channel's index - * @return usb_host_chan_regs_t* Pointer to channel's registers + * @return usb_dwc_host_chan_regs_t* Pointer to channel's registers */ -static inline usb_host_chan_regs_t *usbh_ll_get_chan_regs(usbh_dev_t *dev, int chan_idx) +static inline usb_dwc_host_chan_regs_t *usb_dwc_ll_chan_get_regs(usb_dwc_dev_t *dev, int chan_idx) { return &dev->host_chans[chan_idx]; } // ------------------------------ QTD related ---------------------------------- -#define USBH_LL_QTD_STATUS_SUCCESS 0x0 //If QTD was processed, it indicates the data was transmitted/received successfully -#define USBH_LL_QTD_STATUS_PKTERR 0x1 //Data trasnmitted/received with errors (CRC/Timeout/Stuff/False EOP/Excessive NAK). +#define USB_DWC_LL_QTD_STATUS_SUCCESS 0x0 //If QTD was processed, it indicates the data was transmitted/received successfully +#define USB_DWC_LL_QTD_STATUS_PKTERR 0x1 //Data trasnmitted/received with errors (CRC/Timeout/Stuff/False EOP/Excessive NAK). //Note: 0x2 is reserved -#define USBH_LL_QTD_STATUS_BUFFER 0x3 //AHB error occurred. -#define USBH_LL_QTD_STATUS_NOT_EXECUTED 0x4 //QTD as never processed +#define USB_DWC_LL_QTD_STATUS_BUFFER 0x3 //AHB error occurred. +#define USB_DWC_LL_QTD_STATUS_NOT_EXECUTED 0x4 //QTD as never processed /** * @brief Set a QTD for a non isochronous IN transfer @@ -850,7 +855,7 @@ static inline usb_host_chan_regs_t *usbh_ll_get_chan_regs(usbh_dev_t *dev, int c * Non zero length must be mulitple of the endpoint's MPS. * @param hoc Halt on complete (will generate an interrupt and halt the channel) */ -static inline void usbh_ll_set_qtd_in(usbh_ll_dma_qtd_t *qtd, uint8_t *data_buff, int xfer_len, bool hoc) +static inline void usb_dwc_ll_qtd_set_in(usb_dwc_ll_dma_qtd_t *qtd, uint8_t *data_buff, int xfer_len, bool hoc) { qtd->buffer = data_buff; //Set pointer to data buffer qtd->buffer_status_val = 0; //Reset all flags to zero @@ -873,7 +878,7 @@ static inline void usbh_ll_set_qtd_in(usbh_ll_dma_qtd_t *qtd, uint8_t *data_buff * @param is_setup Indicates whether this is a control transfer setup packet or a normal OUT Data transfer. * (As per the USB protocol, setup packets cannot be STALLd or NAKd by the device) */ -static inline void usbh_ll_set_qtd_out(usbh_ll_dma_qtd_t *qtd, uint8_t *data_buff, int xfer_len, bool hoc, bool is_setup) +static inline void usb_dwc_ll_qtd_set_out(usb_dwc_ll_dma_qtd_t *qtd, uint8_t *data_buff, int xfer_len, bool hoc, bool is_setup) { qtd->buffer = data_buff; //Set pointer to data buffer qtd->buffer_status_val = 0; //Reset all flags to zero @@ -896,7 +901,7 @@ static inline void usbh_ll_set_qtd_out(usbh_ll_dma_qtd_t *qtd, uint8_t *data_buf * * @param qtd Pointer to the QTD */ -static inline void usbh_ll_set_qtd_null(usbh_ll_dma_qtd_t *qtd) +static inline void usb_dwc_ll_qtd_set_null(usb_dwc_ll_dma_qtd_t *qtd) { qtd->buffer = NULL; qtd->buffer_status_val = 0; //Disable qtd by clearing it to zero. Used by interrupt/isoc as an unscheudled frame @@ -911,12 +916,12 @@ static inline void usbh_ll_set_qtd_null(usbh_ll_dma_qtd_t *qtd) * @param[out] rem_len Number of bytes ramining in the QTD * @param[out] status Status of the QTD */ -static inline void usbh_ll_get_qtd_status(usbh_ll_dma_qtd_t *qtd, int *rem_len, int *status) +static inline void usb_dwc_ll_qtd_get_status(usb_dwc_ll_dma_qtd_t *qtd, int *rem_len, int *status) { //Status is the same regardless of IN or OUT if (qtd->in_non_iso.active) { //QTD was never processed - *status = USBH_LL_QTD_STATUS_NOT_EXECUTED; + *status = USB_DWC_LL_QTD_STATUS_NOT_EXECUTED; } else { *status = qtd->in_non_iso.rx_status; } diff --git a/components/hal/include/hal/wdt_hal.h b/components/hal/include/hal/wdt_hal.h index 13d9f5d2f5..527f146148 100644 --- a/components/hal/include/hal/wdt_hal.h +++ b/components/hal/include/hal/wdt_hal.h @@ -1,16 +1,8 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /******************************************************************************* * NOTICE @@ -37,7 +29,11 @@ typedef struct { wdt_inst_t inst; /**< Which WDT instance this HAL context is using (i.e. MWDT0, MWDT1, RWDT)*/ union { timg_dev_t *mwdt_dev; /**< Starting address of the MWDT */ +#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5653 + lp_wdt_dev_t *rwdt_dev; /**< Starting address of the RWDT*/ +#else rtc_cntl_dev_t *rwdt_dev; /**< Starting address of the RWDT*/ +#endif }; } wdt_hal_context_t; diff --git a/components/hal/linker.lf b/components/hal/linker.lf index 9b23d5a562..2f906cc62a 100644 --- a/components/hal/linker.lf +++ b/components/hal/linker.lf @@ -12,8 +12,10 @@ entries: uart_hal_iram (default) spi_flash_hal_iram (noflash) spi_flash_encrypt_hal_iram (noflash) - ledc_hal_iram (noflash) - i2c_hal_iram (noflash) + if SOC_LEDC_SUPPORTED = y: + ledc_hal_iram (noflash) + if SOC_I2C_SUPPORTED = y: + i2c_hal_iram (noflash) if HAL_WDT_USE_ROM_IMPL = n: wdt_hal_iram (noflash) if SOC_SYSTIMER_SUPPORTED = y && HAL_SYSTIMER_USE_ROM_IMPL = n: @@ -30,7 +32,8 @@ entries: lcd_hal: lcd_hal_cal_pclk_freq (noflash) if ADC_ONESHOT_CTRL_FUNC_IN_IRAM = y: adc_oneshot_hal (noflash) - adc_hal_common: get_controller (noflash) + if COMPILER_OPTIMIZATION_DEFAULT = y: + adc_hal_common: get_controller (noflash) adc_hal_common: adc_hal_set_controller (noflash) if SOC_ADC_ARBITER_SUPPORTED = y: adc_hal_common: adc_hal_arbiter_config (noflash) @@ -40,7 +43,8 @@ entries: if ADC_CONTINUOUS_ISR_IRAM_SAFE = y: adc_hal: adc_hal_get_reading_result (noflash) adc_hal: adc_hal_digi_start (noflash) - adc_hal: adc_hal_digi_dma_link_descriptors (noflash) + if COMPILER_OPTIMIZATION_DEFAULT = y: + adc_hal: adc_hal_digi_dma_link_descriptors (noflash) adc_hal: adc_hal_digi_stop (noflash) if IDF_TARGET_ESP32 = y || IDF_TARGET_ESP32S2 = y: adc_hal: adc_hal_check_event (noflash) diff --git a/components/hal/mmu_hal.c b/components/hal/mmu_hal.c index ad0e829bce..e486634bfe 100644 --- a/components/hal/mmu_hal.c +++ b/components/hal/mmu_hal.c @@ -26,6 +26,8 @@ #include "esp32c2/rom/cache.h" #elif CONFIG_IDF_TARGET_ESP32H2 #include "esp32h2/rom/cache.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/cache.h" #endif void mmu_hal_init(void) diff --git a/components/hal/rmt_hal.c b/components/hal/rmt_hal.c index d83e5952da..c14c8501cc 100644 --- a/components/hal/rmt_hal.c +++ b/components/hal/rmt_hal.c @@ -14,6 +14,7 @@ void rmt_hal_init(rmt_hal_context_t *hal) rmt_ll_enable_mem_access_nonfifo(hal->regs, true); // APB access the RMTMEM in nonfifo mode rmt_ll_enable_interrupt(hal->regs, UINT32_MAX, false); // disable all interupt events rmt_ll_clear_interrupt_status(hal->regs, UINT32_MAX); // clear all pending events + rmt_ll_enable_group_clock(hal->regs, true); // enable clock source #if SOC_RMT_SUPPORT_TX_SYNCHRO rmt_ll_tx_clear_sync_group(hal->regs); #endif // SOC_RMT_SUPPORT_TX_SYNCHRO @@ -24,6 +25,7 @@ void rmt_hal_deinit(rmt_hal_context_t *hal) rmt_ll_enable_interrupt(hal->regs, UINT32_MAX, false); // disable all interupt events rmt_ll_clear_interrupt_status(hal->regs, UINT32_MAX); // clear all pending events rmt_ll_power_down_mem(hal->regs, true); // turn off RMTMEM power domain + rmt_ll_enable_group_clock(hal->regs, false); // disable clock source hal->regs = NULL; } diff --git a/components/hal/sdio_slave_hal.c b/components/hal/sdio_slave_hal.c index 2e3044a28c..1e71cbf953 100644 --- a/components/hal/sdio_slave_hal.c +++ b/components/hal/sdio_slave_hal.c @@ -40,7 +40,7 @@ typedef enum { } sdio_ringbuf_pointer_t; static esp_err_t sdio_ringbuf_send(sdio_ringbuf_t *buf, esp_err_t (*copy_callback)(uint8_t *, void *), void *arg); -static inline esp_err_t sdio_ringbuf_recv(sdio_ringbuf_t *buf, uint8_t **start, uint8_t **end, ringbuf_get_all_t get_all); +esp_err_t sdio_ringbuf_recv(sdio_ringbuf_t *buf, uint8_t **start, uint8_t **end, ringbuf_get_all_t get_all); static inline int sdio_ringbuf_return(sdio_ringbuf_t* buf, uint8_t *ptr); #define _SEND_DESC_NEXT(x) STAILQ_NEXT(&((sdio_slave_hal_send_desc_t*)x)->dma_desc, qe) @@ -95,7 +95,12 @@ static esp_err_t sdio_ringbuf_send(sdio_ringbuf_t *buf, esp_err_t (*copy_callbac // this ringbuf is a return-before-recv-again strategy // since this is designed to be called in the ISR, no parallel logic -static inline esp_err_t sdio_ringbuf_recv(sdio_ringbuf_t *buf, uint8_t **start, uint8_t **end, ringbuf_get_all_t get_all) +/* + * Workaround for gcc 11. GCC-277. Break the inferring of callers. + * This function used to be static inline. + */ +__attribute__((weak)) +esp_err_t sdio_ringbuf_recv(sdio_ringbuf_t *buf, uint8_t **start, uint8_t **end, ringbuf_get_all_t get_all) { HAL_ASSERT(buf->free_ptr == buf->read_ptr); //must return before recv again if (start == NULL && end == NULL) return ESP_ERR_INVALID_ARG; // must have a output @@ -163,7 +168,7 @@ void sdio_slave_hal_init(sdio_slave_context_t *hal) void sdio_slave_hal_hw_init(sdio_slave_context_t *hal) { sdio_slave_ll_init(hal->slc); - sdio_slave_ll_enable_hs(hal->hinf, true); + sdio_slave_ll_enable_hs(hal->hinf, !hal->no_highspeed); sdio_slave_ll_set_timing(hal->host, hal->timing); sdio_slave_ll_slvint_t intr_ena = 0xff; sdio_slave_ll_slvint_set_ena(hal->slc, &intr_ena); diff --git a/components/hal/spi_flash_hal.c b/components/hal/spi_flash_hal.c index 6e4db3c887..8092db667f 100644 --- a/components/hal/spi_flash_hal.c +++ b/components/hal/spi_flash_hal.c @@ -23,7 +23,7 @@ static const char *TAG = "flash_hal"; static uint32_t get_flash_clock_divider(const spi_flash_hal_config_t *cfg) { int clk_source = cfg->clock_src_freq; - // On ESP32, ESP32-S2, ESP32-C3, we allow specific frequency 26.666MHz, + // On ESP32, ESP32-S2, ESP32-C3, we allow specific frequency 26.666MHz, // TODO: IDF-5333 (check this) // If user passes freq_mhz like 26 or 27, it's allowed to use integer divider 3. // However on other chips or on other frequency, we only allow user pass frequency which // can be integer divided. If no, the following strategy is round up the division and diff --git a/components/hal/timer_hal.c b/components/hal/timer_hal.c index d7bbd387be..ae4e55467d 100644 --- a/components/hal/timer_hal.c +++ b/components/hal/timer_hal.c @@ -4,11 +4,37 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include "hal/timer_hal.h" #include "hal/timer_ll.h" +#include "soc/soc_caps.h" void timer_hal_init(timer_hal_context_t *hal, uint32_t group_num, uint32_t timer_num) { hal->dev = TIMER_LL_GET_HW(group_num); hal->timer_id = timer_num; + // enable peripheral clock + timer_ll_enable_clock(hal->dev, timer_num, true); + // stop counter, alarm, auto-reload at first place + timer_ll_enable_counter(hal->dev, timer_num, false); + timer_ll_enable_auto_reload(hal->dev, timer_num, false); + timer_ll_enable_alarm(hal->dev, timer_num, false); + // enable RTM subsystem if available +#if SOC_TIMER_SUPPORT_ETM + timer_ll_enable_etm(hal->dev, true); +#endif +} + +void timer_hal_deinit(timer_hal_context_t *hal) +{ + // disable peripheral clock + timer_ll_enable_clock(hal->dev, hal->timer_id, false); + // ensure counter, alarm, auto-reload are disabled + timer_ll_enable_counter(hal->dev, hal->timer_id, false); + timer_ll_enable_auto_reload(hal->dev, hal->timer_id, false); + timer_ll_enable_alarm(hal->dev, hal->timer_id, false); +#if SOC_TIMER_SUPPORT_ETM + timer_ll_enable_etm(hal->dev, false); +#endif + hal->dev = NULL; } diff --git a/components/hal/timer_hal_iram.c b/components/hal/timer_hal_iram.c index da75d78db5..43bac81e72 100644 --- a/components/hal/timer_hal_iram.c +++ b/components/hal/timer_hal_iram.c @@ -22,3 +22,9 @@ void timer_hal_set_counter_value(timer_hal_context_t *hal, uint64_t load_val) // restore the previous reload value timer_ll_set_reload_value(hal->dev, hal->timer_id, old_reload); } + +uint64_t timer_hal_capture_and_get_counter_value(timer_hal_context_t *hal) +{ + timer_ll_trigger_soft_capture(hal->dev, hal->timer_id); + return timer_ll_get_counter_value(hal->dev, hal->timer_id); +} diff --git a/components/hal/uart_hal.c b/components/hal/uart_hal.c index 3e6862d0cb..5656b2def9 100644 --- a/components/hal/uart_hal.c +++ b/components/hal/uart_hal.c @@ -17,14 +17,14 @@ void uart_hal_get_sclk(uart_hal_context_t *hal, uart_sclk_t *sclk) uart_ll_get_sclk(hal->dev, sclk); } -void uart_hal_set_baudrate(uart_hal_context_t *hal, uint32_t baud_rate) +void uart_hal_set_baudrate(uart_hal_context_t *hal, uint32_t baud_rate, uint32_t sclk_freq) { - uart_ll_set_baudrate(hal->dev, baud_rate); + uart_ll_set_baudrate(hal->dev, baud_rate, sclk_freq); } -void uart_hal_get_baudrate(uart_hal_context_t *hal, uint32_t *baud_rate) +void uart_hal_get_baudrate(uart_hal_context_t *hal, uint32_t *baud_rate, uint32_t sclk_freq) { - *baud_rate = uart_ll_get_baudrate(hal->dev); + *baud_rate = uart_ll_get_baudrate(hal->dev, sclk_freq); } void uart_hal_set_stop_bits(uart_hal_context_t *hal, uart_stop_bits_t stop_bit) @@ -131,9 +131,6 @@ void uart_hal_init(uart_hal_context_t *hal, int uart_num) { // Set default clock source uart_ll_set_sclk(hal->dev, UART_SCLK_DEFAULT); - // Set default baud: 115200, use APB clock. - const uint32_t baud_def = 115200; - uart_ll_set_baudrate(hal->dev, baud_def); // Set UART mode. uart_ll_set_mode(hal->dev, UART_MODE_UART); // Disable UART parity diff --git a/components/hal/usbh_hal.c b/components/hal/usb_dwc_hal.c similarity index 53% rename from components/hal/usbh_hal.c rename to components/hal/usb_dwc_hal.c index b4a10ca5c5..ee0663dfce 100644 --- a/components/hal/usbh_hal.c +++ b/components/hal/usb_dwc_hal.c @@ -8,8 +8,8 @@ #include #include #include "sdkconfig.h" -#include "hal/usbh_hal.h" -#include "hal/usbh_ll.h" +#include "hal/usb_dwc_hal.h" +#include "hal/usb_dwc_ll.h" #include "hal/assert.h" // ------------------------------------------------ Macros and Types --------------------------------------------------- @@ -30,108 +30,108 @@ /** * The following core interrupts will be enabled (listed LSB to MSB). Some of these * interrupts are enabled later than others. - * - USB_LL_INTR_CORE_PRTINT - * - USB_LL_INTR_CORE_HCHINT - * - USB_LL_INTR_CORE_DISCONNINT + * - USB_DWC_LL_INTR_CORE_PRTINT + * - USB_DWC_LL_INTR_CORE_HCHINT + * - USB_DWC_LL_INTR_CORE_DISCONNINT * The following PORT interrupts cannot be masked, listed LSB to MSB - * - USBH_LL_INTR_HPRT_PRTCONNDET - * - USBH_LL_INTR_HPRT_PRTENCHNG - * - USBH_LL_INTR_HPRT_PRTOVRCURRCHNG + * - USB_DWC_LL_INTR_HPRT_PRTCONNDET + * - USB_DWC_LL_INTR_HPRT_PRTENCHNG + * - USB_DWC_LL_INTR_HPRT_PRTOVRCURRCHNG */ -#define CORE_INTRS_EN_MSK (USB_LL_INTR_CORE_DISCONNINT) +#define CORE_INTRS_EN_MSK (USB_DWC_LL_INTR_CORE_DISCONNINT) //Interrupts that pertain to core events -#define CORE_EVENTS_INTRS_MSK (USB_LL_INTR_CORE_DISCONNINT | \ - USB_LL_INTR_CORE_HCHINT) +#define CORE_EVENTS_INTRS_MSK (USB_DWC_LL_INTR_CORE_DISCONNINT | \ + USB_DWC_LL_INTR_CORE_HCHINT) //Interrupt that pertain to host port events -#define PORT_EVENTS_INTRS_MSK (USBH_LL_INTR_HPRT_PRTCONNDET | \ - USBH_LL_INTR_HPRT_PRTENCHNG | \ - USBH_LL_INTR_HPRT_PRTOVRCURRCHNG) +#define PORT_EVENTS_INTRS_MSK (USB_DWC_LL_INTR_HPRT_PRTCONNDET | \ + USB_DWC_LL_INTR_HPRT_PRTENCHNG | \ + USB_DWC_LL_INTR_HPRT_PRTOVRCURRCHNG) /** * The following channel interrupt bits are currently checked (in order LSB to MSB) - * - USBH_LL_INTR_CHAN_XFERCOMPL - * - USBH_LL_INTR_CHAN_CHHLTD - * - USBH_LL_INTR_CHAN_STALL - * - USBH_LL_INTR_CHAN_BBLEER - * - USBH_LL_INTR_CHAN_BNAINTR - * - USBH_LL_INTR_CHAN_XCS_XACT_ERR + * - USB_DWC_LL_INTR_CHAN_XFERCOMPL + * - USB_DWC_LL_INTR_CHAN_CHHLTD + * - USB_DWC_LL_INTR_CHAN_STALL + * - USB_DWC_LL_INTR_CHAN_BBLEER + * - USB_DWC_LL_INTR_CHAN_BNAINTR + * - USB_DWC_LL_INTR_CHAN_XCS_XACT_ERR * * Note the following points about channel interrupts: * - Not all bits are unmaskable under scatter/gather - * - Those bits proxy their interrupt through the USBH_LL_INTR_CHAN_CHHLTD bit - * - USBH_LL_INTR_CHAN_XCS_XACT_ERR is always unmasked - * - When USBH_LL_INTR_CHAN_BNAINTR occurs, USBH_LL_INTR_CHAN_CHHLTD will NOT. - * - USBH_LL_INTR_CHAN_AHBERR doesn't actually ever happen on our system (i.e., ESP32-S2, ESP32-S3): + * - Those bits proxy their interrupt through the USB_DWC_LL_INTR_CHAN_CHHLTD bit + * - USB_DWC_LL_INTR_CHAN_XCS_XACT_ERR is always unmasked + * - When USB_DWC_LL_INTR_CHAN_BNAINTR occurs, USB_DWC_LL_INTR_CHAN_CHHLTD will NOT. + * - USB_DWC_LL_INTR_CHAN_AHBERR doesn't actually ever happen on our system (i.e., ESP32-S2, ESP32-S3): * - If the QTD list's starting address is an invalid address (e.g., NULL), the core will attempt to fetch that * address for a transfer descriptor and probably gets all zeroes. It will interpret the zero as a bad QTD and - * return a USBH_LL_INTR_CHAN_BNAINTR instead. + * return a USB_DWC_LL_INTR_CHAN_BNAINTR instead. * - If the QTD's buffer pointer is an invalid address, the core will attempt to read/write data to/from that * invalid buffer address with NO INDICATION OF ERROR. The transfer will be acknowledged and treated as * successful. Bad buffer pointers MUST BE CHECKED FROM HIGHER LAYERS INSTEAD. */ -#define CHAN_INTRS_EN_MSK (USBH_LL_INTR_CHAN_XFERCOMPL | \ - USBH_LL_INTR_CHAN_CHHLTD | \ - USBH_LL_INTR_CHAN_BNAINTR) +#define CHAN_INTRS_EN_MSK (USB_DWC_LL_INTR_CHAN_XFERCOMPL | \ + USB_DWC_LL_INTR_CHAN_CHHLTD | \ + USB_DWC_LL_INTR_CHAN_BNAINTR) -#define CHAN_INTRS_ERROR_MSK (USBH_LL_INTR_CHAN_STALL | \ - USBH_LL_INTR_CHAN_BBLEER | \ - USBH_LL_INTR_CHAN_BNAINTR | \ - USBH_LL_INTR_CHAN_XCS_XACT_ERR) +#define CHAN_INTRS_ERROR_MSK (USB_DWC_LL_INTR_CHAN_STALL | \ + USB_DWC_LL_INTR_CHAN_BBLEER | \ + USB_DWC_LL_INTR_CHAN_BNAINTR | \ + USB_DWC_LL_INTR_CHAN_XCS_XACT_ERR) // -------------------------------------------------- Core (Global) ---------------------------------------------------- -static void set_defaults(usbh_hal_context_t *hal) +static void set_defaults(usb_dwc_hal_context_t *hal) { //GAHBCFG register - usb_ll_en_dma_mode(hal->dev); + usb_dwc_ll_gahbcfg_en_dma_mode(hal->dev); #ifdef CONFIG_IDF_TARGET_ESP32S2 - usb_ll_set_hbstlen(hal->dev, 1); //Use INCR AHB burst. See the ESP32-S2 and later chip ERRATA. + usb_dwc_ll_gahbcfg_set_hbstlen(hal->dev, 1); //Use INCR AHB burst. See the ESP32-S2 and later chip ERRATA. #elif CONFIG_IDF_TARGET_ESP32S3 - usb_ll_set_hbstlen(hal->dev, 0); //Do not use USB burst INCR mode for the ESP32-S3, to avoid interference with other peripherals. + usb_dwc_ll_gahbcfg_set_hbstlen(hal->dev, 0); //Do not use USB burst INCR mode for the ESP32-S3, to avoid interference with other peripherals. #endif //GUSBCFG register - usb_ll_dis_hnp_cap(hal->dev); //Disable HNP - usb_ll_dis_srp_cap(hal->dev); //Disable SRP + usb_dwc_ll_gusbcfg_dis_hnp_cap(hal->dev); //Disable HNP + usb_dwc_ll_gusbcfg_dis_srp_cap(hal->dev); //Disable SRP //Enable interruts - usb_ll_dis_intrs(hal->dev, 0xFFFFFFFF); //Mask all interrupts first - usb_ll_en_intrs(hal->dev, CORE_INTRS_EN_MSK); //Unmask global interrupts - usb_ll_intr_read_and_clear(hal->dev); //Clear interrupts - usb_ll_en_global_intr(hal->dev); //Enable interrupt signal + usb_dwc_ll_gintmsk_dis_intrs(hal->dev, 0xFFFFFFFF); //Mask all interrupts first + usb_dwc_ll_gintmsk_en_intrs(hal->dev, CORE_INTRS_EN_MSK); //Unmask global interrupts + usb_dwc_ll_gintsts_read_and_clear_intrs(hal->dev); //Clear interrupts + usb_dwc_ll_gahbcfg_en_global_intr(hal->dev); //Enable interrupt signal //Enable host mode - usb_ll_set_host_mode(hal->dev); + usb_dwc_ll_gusbcfg_force_host_mode(hal->dev); } -void usbh_hal_init(usbh_hal_context_t *hal) +void usb_dwc_hal_init(usb_dwc_hal_context_t *hal) { //Check if a peripheral is alive by reading the core ID registers - usbh_dev_t *dev = &USBH; - uint32_t core_id = usb_ll_get_controller_core_id(dev); + usb_dwc_dev_t *dev = &USB_DWC; + uint32_t core_id = usb_dwc_ll_gsnpsid_get_id(dev); HAL_ASSERT(core_id == CORE_REG_GSNPSID); (void) core_id; //Suppress unused variable warning if asserts are disabled //Initialize HAL context - memset(hal, 0, sizeof(usbh_hal_context_t)); + memset(hal, 0, sizeof(usb_dwc_hal_context_t)); hal->dev = dev; set_defaults(hal); } -void usbh_hal_deinit(usbh_hal_context_t *hal) +void usb_dwc_hal_deinit(usb_dwc_hal_context_t *hal) { //Disable and clear global interrupt - usb_ll_dis_intrs(hal->dev, 0xFFFFFFFF); //Disable all interrupts - usb_ll_intr_read_and_clear(hal->dev); //Clear interrupts - usb_ll_dis_global_intr(hal->dev); //Disable interrupt signal + usb_dwc_ll_gintmsk_dis_intrs(hal->dev, 0xFFFFFFFF); //Disable all interrupts + usb_dwc_ll_gintsts_read_and_clear_intrs(hal->dev); //Clear interrupts + usb_dwc_ll_gahbcfg_dis_global_intr(hal->dev); //Disable interrupt signal hal->dev = NULL; } -void usbh_hal_core_soft_reset(usbh_hal_context_t *hal) +void usb_dwc_hal_core_soft_reset(usb_dwc_hal_context_t *hal) { - usb_ll_core_soft_reset(hal->dev); - while (usb_ll_check_core_soft_reset(hal->dev)) { + usb_dwc_ll_grstctl_core_soft_reset(hal->dev); + while (usb_dwc_ll_grstctl_is_core_soft_reset_in_progress(hal->dev)) { ; //Wait until core reset is done } - while (!usb_ll_check_ahb_idle(hal->dev)) { + while (!usb_dwc_ll_grstctl_is_ahb_idle(hal->dev)) { ; //Wait until AHB Master bus is idle before doing any other operations } //Set the default bits @@ -141,60 +141,60 @@ void usbh_hal_core_soft_reset(usbh_hal_context_t *hal) hal->flags.val = 0; hal->channels.num_allocd = 0; hal->channels.chan_pend_intrs_msk = 0; - memset(hal->channels.hdls, 0, sizeof(usbh_hal_chan_t *) * USBH_HAL_NUM_CHAN); + memset(hal->channels.hdls, 0, sizeof(usb_dwc_hal_chan_t *) * USB_DWC_HAL_NUM_CHAN); } -void usbh_hal_set_fifo_size(usbh_hal_context_t *hal, const usbh_hal_fifo_config_t *fifo_config) +void usb_dwc_hal_set_fifo_size(usb_dwc_hal_context_t *hal, const usb_dwc_hal_fifo_config_t *fifo_config) { - HAL_ASSERT((fifo_config->rx_fifo_lines + fifo_config->nptx_fifo_lines + fifo_config->ptx_fifo_lines) <= USBH_HAL_FIFO_TOTAL_USABLE_LINES); + HAL_ASSERT((fifo_config->rx_fifo_lines + fifo_config->nptx_fifo_lines + fifo_config->ptx_fifo_lines) <= USB_DWC_HAL_FIFO_TOTAL_USABLE_LINES); //Check that none of the channels are active - for (int i = 0; i < USBH_HAL_NUM_CHAN; i++) { + for (int i = 0; i < USB_DWC_HAL_NUM_CHAN; i++) { if (hal->channels.hdls[i] != NULL) { HAL_ASSERT(!hal->channels.hdls[i]->flags.active); } } //Set the new FIFO lengths - usb_ll_set_rx_fifo_size(hal->dev, fifo_config->rx_fifo_lines); - usb_ll_set_nptx_fifo_size(hal->dev, fifo_config->rx_fifo_lines, fifo_config->nptx_fifo_lines); - usbh_ll_set_ptx_fifo_size(hal->dev, fifo_config->rx_fifo_lines + fifo_config->nptx_fifo_lines, fifo_config->ptx_fifo_lines); + usb_dwc_ll_grxfsiz_set_fifo_size(hal->dev, fifo_config->rx_fifo_lines); + usb_dwc_ll_gnptxfsiz_set_fifo_size(hal->dev, fifo_config->rx_fifo_lines, fifo_config->nptx_fifo_lines); + usb_dwc_ll_hptxfsiz_set_ptx_fifo_size(hal->dev, fifo_config->rx_fifo_lines + fifo_config->nptx_fifo_lines, fifo_config->ptx_fifo_lines); //Flush the FIFOs - usb_ll_flush_nptx_fifo(hal->dev); - usb_ll_flush_ptx_fifo(hal->dev); - usb_ll_flush_rx_fifo(hal->dev); + usb_dwc_ll_grstctl_flush_nptx_fifo(hal->dev); + usb_dwc_ll_grstctl_flush_ptx_fifo(hal->dev); + usb_dwc_ll_grstctl_flush_rx_fifo(hal->dev); hal->flags.fifo_sizes_set = 1; } // ---------------------------------------------------- Host Port ------------------------------------------------------ -static inline void debounce_lock_enable(usbh_hal_context_t *hal) +static inline void debounce_lock_enable(usb_dwc_hal_context_t *hal) { //Disable the hprt (connection) and disconnection interrupts to prevent repeated triggerings - usb_ll_dis_intrs(hal->dev, USB_LL_INTR_CORE_PRTINT | USB_LL_INTR_CORE_DISCONNINT); + usb_dwc_ll_gintmsk_dis_intrs(hal->dev, USB_DWC_LL_INTR_CORE_PRTINT | USB_DWC_LL_INTR_CORE_DISCONNINT); hal->flags.dbnc_lock_enabled = 1; } -void usbh_hal_port_enable(usbh_hal_context_t *hal) +void usb_dwc_hal_port_enable(usb_dwc_hal_context_t *hal) { - usb_priv_speed_t speed = usbh_ll_hprt_get_speed(hal->dev); + usb_priv_speed_t speed = usb_dwc_ll_hprt_get_speed(hal->dev); //Host Configuration - usbh_ll_hcfg_set_defaults(hal->dev, speed); + usb_dwc_ll_hcfg_set_defaults(hal->dev, speed); //Configure HFIR - usbh_ll_hfir_set_defaults(hal->dev, speed); + usb_dwc_ll_hfir_set_defaults(hal->dev, speed); } // ----------------------------------------------------- Channel ------------------------------------------------------- // ----------------- Channel Allocation -------------------- -bool usbh_hal_chan_alloc(usbh_hal_context_t *hal, usbh_hal_chan_t *chan_obj, void *chan_ctx) +bool usb_dwc_hal_chan_alloc(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan_obj, void *chan_ctx) { HAL_ASSERT(hal->flags.fifo_sizes_set); //FIFO sizes should be set befor attempting to allocate a channel //Attempt to allocate channel - if (hal->channels.num_allocd == USBH_HAL_NUM_CHAN) { + if (hal->channels.num_allocd == USB_DWC_HAL_NUM_CHAN) { return false; //Out of free channels } int chan_idx = -1; - for (int i = 0; i < USBH_HAL_NUM_CHAN; i++) { + for (int i = 0; i < USB_DWC_HAL_NUM_CHAN; i++) { if (hal->channels.hdls[i] == NULL) { hal->channels.hdls[i] = chan_obj; chan_idx = i; @@ -204,21 +204,21 @@ bool usbh_hal_chan_alloc(usbh_hal_context_t *hal, usbh_hal_chan_t *chan_obj, voi } HAL_ASSERT(chan_idx != -1); //Initialize channel object - memset(chan_obj, 0, sizeof(usbh_hal_chan_t)); + memset(chan_obj, 0, sizeof(usb_dwc_hal_chan_t)); chan_obj->flags.chan_idx = chan_idx; - chan_obj->regs = usbh_ll_get_chan_regs(hal->dev, chan_idx); + chan_obj->regs = usb_dwc_ll_chan_get_regs(hal->dev, chan_idx); chan_obj->chan_ctx = chan_ctx; //Note: EP characteristics configured separately //Clean and unmask the channel's interrupt - usbh_ll_chan_intr_read_and_clear(chan_obj->regs); //Clear the interrupt bits for that channel - usbh_ll_haintmsk_en_chan_intr(hal->dev, 1 << chan_obj->flags.chan_idx); - usbh_ll_chan_set_intr_mask(chan_obj->regs, CHAN_INTRS_EN_MSK); //Unmask interrupts for this channel - usbh_ll_chan_set_pid(chan_obj->regs, 0); //Set the initial PID to zero - usbh_ll_chan_hctsiz_init(chan_obj->regs); //Set the non changing parts of the HCTSIZ registers (e.g., do_ping and sched info) + usb_dwc_ll_hcint_read_and_clear_intrs(chan_obj->regs); //Clear the interrupt bits for that channel + usb_dwc_ll_haintmsk_en_chan_intr(hal->dev, 1 << chan_obj->flags.chan_idx); + usb_dwc_ll_hcintmsk_set_intr_mask(chan_obj->regs, CHAN_INTRS_EN_MSK); //Unmask interrupts for this channel + usb_dwc_ll_hctsiz_set_pid(chan_obj->regs, 0); //Set the initial PID to zero + usb_dwc_ll_hctsiz_init(chan_obj->regs); //Set the non changing parts of the HCTSIZ registers (e.g., do_ping and sched info) return true; } -void usbh_hal_chan_free(usbh_hal_context_t *hal, usbh_hal_chan_t *chan_obj) +void usb_dwc_hal_chan_free(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan_obj) { if (chan_obj->type == USB_PRIV_XFER_TYPE_INTR || chan_obj->type == USB_PRIV_XFER_TYPE_ISOCHRONOUS) { //Unschedule this channel @@ -229,7 +229,7 @@ void usbh_hal_chan_free(usbh_hal_context_t *hal, usbh_hal_chan_t *chan_obj) //Can only free a channel when in the disabled state and descriptor list released HAL_ASSERT(!chan_obj->flags.active); //Disable channel's interrupt - usbh_ll_haintmsk_dis_chan_intr(hal->dev, 1 << chan_obj->flags.chan_idx); + usb_dwc_ll_haintmsk_dis_chan_intr(hal->dev, 1 << chan_obj->flags.chan_idx); //Deallocate channel hal->channels.hdls[chan_obj->flags.chan_idx] = NULL; hal->channels.num_allocd--; @@ -238,12 +238,12 @@ void usbh_hal_chan_free(usbh_hal_context_t *hal, usbh_hal_chan_t *chan_obj) // ---------------- Channel Configuration ------------------ -void usbh_hal_chan_set_ep_char(usbh_hal_context_t *hal, usbh_hal_chan_t *chan_obj, usbh_hal_ep_char_t *ep_char) +void usb_dwc_hal_chan_set_ep_char(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan_obj, usb_dwc_hal_ep_char_t *ep_char) { //Cannot change ep_char whilst channel is still active or in error HAL_ASSERT(!chan_obj->flags.active); //Set the endpoint characteristics of the pipe - usbh_ll_chan_hcchar_init(chan_obj->regs, + usb_dwc_ll_hcchar_init(chan_obj->regs, ep_char->dev_addr, ep_char->bEndpointAddress & BENDPOINTADDRESS_NUM_MSK, ep_char->mps, @@ -266,24 +266,24 @@ void usbh_hal_chan_set_ep_char(usbh_hal_context_t *hal, usbh_hal_chan_t *chan_ob // ------------------- Channel Control --------------------- -void usbh_hal_chan_activate(usbh_hal_chan_t *chan_obj, void *xfer_desc_list, int desc_list_len, int start_idx) +void usb_dwc_hal_chan_activate(usb_dwc_hal_chan_t *chan_obj, void *xfer_desc_list, int desc_list_len, int start_idx) { //Cannot activate a channel that has already been enabled or is pending error handling HAL_ASSERT(!chan_obj->flags.active); //Set start address of the QTD list and starting QTD index - usbh_ll_chan_set_dma_addr_non_iso(chan_obj->regs, xfer_desc_list, start_idx); - usbh_ll_chan_set_qtd_list_len(chan_obj->regs, desc_list_len); - usbh_ll_chan_start(chan_obj->regs); //Start the channel + usb_dwc_ll_hcdma_set_qtd_list_addr(chan_obj->regs, xfer_desc_list, start_idx); + usb_dwc_ll_hctsiz_set_qtd_list_len(chan_obj->regs, desc_list_len); + usb_dwc_ll_hcchar_enable_chan(chan_obj->regs); //Start the channel chan_obj->flags.active = 1; } -bool usbh_hal_chan_request_halt(usbh_hal_chan_t *chan_obj) +bool usb_dwc_hal_chan_request_halt(usb_dwc_hal_chan_t *chan_obj) { //Cannot request halt on a channel that is pending error handling - if (usbh_ll_chan_is_active(chan_obj->regs)) { + if (usb_dwc_ll_hcchar_chan_is_enabled(chan_obj->regs)) { //If the register indicates that the channel is still active, the active flag must have been previously set HAL_ASSERT(chan_obj->flags.active); - usbh_ll_chan_halt(chan_obj->regs); + usb_dwc_ll_hcchar_disable_chan(chan_obj->regs); chan_obj->flags.halt_requested = 1; return false; } else { @@ -295,54 +295,54 @@ bool usbh_hal_chan_request_halt(usbh_hal_chan_t *chan_obj) // ------------------------------------------------- Event Handling ---------------------------------------------------- -usbh_hal_port_event_t usbh_hal_decode_intr(usbh_hal_context_t *hal) +usb_dwc_hal_port_event_t usb_dwc_hal_decode_intr(usb_dwc_hal_context_t *hal) { - uint32_t intrs_core = usb_ll_intr_read_and_clear(hal->dev); //Read and clear core interrupts + uint32_t intrs_core = usb_dwc_ll_gintsts_read_and_clear_intrs(hal->dev); //Read and clear core interrupts uint32_t intrs_port = 0; - if (intrs_core & USB_LL_INTR_CORE_PRTINT) { + if (intrs_core & USB_DWC_LL_INTR_CORE_PRTINT) { //There are host port interrupts. Read and clear those as well. - intrs_port = usbh_ll_hprt_intr_read_and_clear(hal->dev); + intrs_port = usb_dwc_ll_hprt_intr_read_and_clear(hal->dev); } //Note: Do not change order of checks. Regressing events (e.g. enable -> disabled, connected -> connected) //always take precedence. ENABLED < DISABLED < CONN < DISCONN < OVRCUR - usbh_hal_port_event_t event = USBH_HAL_PORT_EVENT_NONE; + usb_dwc_hal_port_event_t event = USB_DWC_HAL_PORT_EVENT_NONE; //Check if this is a core or port event if ((intrs_core & CORE_EVENTS_INTRS_MSK) || (intrs_port & PORT_EVENTS_INTRS_MSK)) { //Do not change the order of the following checks. Some events/interrupts take precedence over others - if (intrs_core & USB_LL_INTR_CORE_DISCONNINT) { - event = USBH_HAL_PORT_EVENT_DISCONN; + if (intrs_core & USB_DWC_LL_INTR_CORE_DISCONNINT) { + event = USB_DWC_HAL_PORT_EVENT_DISCONN; debounce_lock_enable(hal); //Mask the port connection and disconnection interrupts to prevent repeated triggering - } else if (intrs_port & USBH_LL_INTR_HPRT_PRTOVRCURRCHNG) { + } else if (intrs_port & USB_DWC_LL_INTR_HPRT_PRTOVRCURRCHNG) { //Check if this is an overcurrent or an overcurrent cleared - if (usbh_ll_hprt_get_port_overcur(hal->dev)) { - event = USBH_HAL_PORT_EVENT_OVRCUR; + if (usb_dwc_ll_hprt_get_port_overcur(hal->dev)) { + event = USB_DWC_HAL_PORT_EVENT_OVRCUR; } else { - event = USBH_HAL_PORT_EVENT_OVRCUR_CLR; + event = USB_DWC_HAL_PORT_EVENT_OVRCUR_CLR; } - } else if (intrs_port & USBH_LL_INTR_HPRT_PRTENCHNG) { - if (usbh_ll_hprt_get_port_en(hal->dev)) { //Host port was enabled - event = USBH_HAL_PORT_EVENT_ENABLED; + } else if (intrs_port & USB_DWC_LL_INTR_HPRT_PRTENCHNG) { + if (usb_dwc_ll_hprt_get_port_en(hal->dev)) { //Host port was enabled + event = USB_DWC_HAL_PORT_EVENT_ENABLED; } else { //Host port has been disabled - event = USBH_HAL_PORT_EVENT_DISABLED; + event = USB_DWC_HAL_PORT_EVENT_DISABLED; } - } else if (intrs_port & USBH_LL_INTR_HPRT_PRTCONNDET && !hal->flags.dbnc_lock_enabled) { - event = USBH_HAL_PORT_EVENT_CONN; + } else if (intrs_port & USB_DWC_LL_INTR_HPRT_PRTCONNDET && !hal->flags.dbnc_lock_enabled) { + event = USB_DWC_HAL_PORT_EVENT_CONN; debounce_lock_enable(hal); } } //Port events always take precedence over channel events - if (event == USBH_HAL_PORT_EVENT_NONE && (intrs_core & USB_LL_INTR_CORE_HCHINT)) { + if (event == USB_DWC_HAL_PORT_EVENT_NONE && (intrs_core & USB_DWC_LL_INTR_CORE_HCHINT)) { //One or more channels have pending interrupts. Store the mask of those channels - hal->channels.chan_pend_intrs_msk = usbh_ll_get_chan_intrs_msk(hal->dev); - event = USBH_HAL_PORT_EVENT_CHAN; + hal->channels.chan_pend_intrs_msk = usb_dwc_ll_haint_get_chan_intrs(hal->dev); + event = USB_DWC_HAL_PORT_EVENT_CHAN; } return event; } -usbh_hal_chan_t *usbh_hal_get_chan_pending_intr(usbh_hal_context_t *hal) +usb_dwc_hal_chan_t *usb_dwc_hal_get_chan_pending_intr(usb_dwc_hal_context_t *hal) { int chan_num = __builtin_ffs(hal->channels.chan_pend_intrs_msk); if (chan_num) { @@ -353,52 +353,52 @@ usbh_hal_chan_t *usbh_hal_get_chan_pending_intr(usbh_hal_context_t *hal) } } -usbh_hal_chan_event_t usbh_hal_chan_decode_intr(usbh_hal_chan_t *chan_obj) +usb_dwc_hal_chan_event_t usb_dwc_hal_chan_decode_intr(usb_dwc_hal_chan_t *chan_obj) { - uint32_t chan_intrs = usbh_ll_chan_intr_read_and_clear(chan_obj->regs); - usbh_hal_chan_event_t chan_event; - //Note: We don't assert on (chan_obj->flags.active) here as it could have been already cleared by usbh_hal_chan_request_halt() + uint32_t chan_intrs = usb_dwc_ll_hcint_read_and_clear_intrs(chan_obj->regs); + usb_dwc_hal_chan_event_t chan_event; + //Note: We don't assert on (chan_obj->flags.active) here as it could have been already cleared by usb_dwc_hal_chan_request_halt() if (chan_intrs & CHAN_INTRS_ERROR_MSK) { //Note: Errors are uncommon, so we check against the entire interrupt mask to reduce frequency of entering this call path - HAL_ASSERT(chan_intrs & USBH_LL_INTR_CHAN_CHHLTD); //An error should have halted the channel + HAL_ASSERT(chan_intrs & USB_DWC_LL_INTR_CHAN_CHHLTD); //An error should have halted the channel //Store the error in hal context - usbh_hal_chan_error_t error; - if (chan_intrs & USBH_LL_INTR_CHAN_STALL) { - error = USBH_HAL_CHAN_ERROR_STALL; - } else if (chan_intrs & USBH_LL_INTR_CHAN_BBLEER) { - error = USBH_HAL_CHAN_ERROR_PKT_BBL; - } else if (chan_intrs & USBH_LL_INTR_CHAN_BNAINTR) { - error = USBH_HAL_CHAN_ERROR_BNA; - } else { //USBH_LL_INTR_CHAN_XCS_XACT_ERR - error = USBH_HAL_CHAN_ERROR_XCS_XACT; + usb_dwc_hal_chan_error_t error; + if (chan_intrs & USB_DWC_LL_INTR_CHAN_STALL) { + error = USB_DWC_HAL_CHAN_ERROR_STALL; + } else if (chan_intrs & USB_DWC_LL_INTR_CHAN_BBLEER) { + error = USB_DWC_HAL_CHAN_ERROR_PKT_BBL; + } else if (chan_intrs & USB_DWC_LL_INTR_CHAN_BNAINTR) { + error = USB_DWC_HAL_CHAN_ERROR_BNA; + } else { //USB_DWC_LL_INTR_CHAN_XCS_XACT_ERR + error = USB_DWC_HAL_CHAN_ERROR_XCS_XACT; } //Update flags chan_obj->error = error; chan_obj->flags.active = 0; //Save the error to be handled later - chan_event = USBH_HAL_CHAN_EVENT_ERROR; - } else if (chan_intrs & USBH_LL_INTR_CHAN_CHHLTD) { + chan_event = USB_DWC_HAL_CHAN_EVENT_ERROR; + } else if (chan_intrs & USB_DWC_LL_INTR_CHAN_CHHLTD) { if (chan_obj->flags.halt_requested) { chan_obj->flags.halt_requested = 0; - chan_event = USBH_HAL_CHAN_EVENT_HALT_REQ; + chan_event = USB_DWC_HAL_CHAN_EVENT_HALT_REQ; } else { //Must have been halted due to QTD HOC - chan_event = USBH_HAL_CHAN_EVENT_CPLT; + chan_event = USB_DWC_HAL_CHAN_EVENT_CPLT; } chan_obj->flags.active = 0; - } else if (chan_intrs & USBH_LL_INTR_CHAN_XFERCOMPL) { + } else if (chan_intrs & USB_DWC_LL_INTR_CHAN_XFERCOMPL) { /* A transfer complete interrupt WITHOUT the channel halting only occurs when receiving a short interrupt IN packet and the underlying QTD does not have the HOC bit set. This signifies the last packet of the Interrupt transfer as all interrupt packets must MPS sized except the last. */ //The channel isn't halted yet, so we need to halt it manually to stop the execution of the next QTD/packet - usbh_ll_chan_halt(chan_obj->regs); + usb_dwc_ll_hcchar_disable_chan(chan_obj->regs); /* After setting the halt bit, this will generate another channel halted interrupt. We treat this interrupt as a NONE event, then cycle back with the channel halted interrupt to handle the CPLT event. */ - chan_event = USBH_HAL_CHAN_EVENT_NONE; + chan_event = USB_DWC_HAL_CHAN_EVENT_NONE; } else { abort(); //Should never reach this point } diff --git a/components/hal/wdt_hal_iram.c b/components/hal/wdt_hal_iram.c index 5afd38433c..8c6609b409 100644 --- a/components/hal/wdt_hal_iram.c +++ b/components/hal/wdt_hal_iram.c @@ -24,7 +24,11 @@ void wdt_hal_init(wdt_hal_context_t *hal, wdt_inst_t wdt_inst, uint32_t prescale } #endif else { +#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5653 + hal->rwdt_dev = &LP_WDT; +#else hal->rwdt_dev = &RTCCNTL; +#endif } hal->inst = wdt_inst; @@ -67,7 +71,7 @@ void wdt_hal_init(wdt_hal_context_t *hal, wdt_inst_t wdt_inst, uint32_t prescale mwdt_ll_disable_stage(hal->mwdt_dev, 1); mwdt_ll_disable_stage(hal->mwdt_dev, 2); mwdt_ll_disable_stage(hal->mwdt_dev, 3); -#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C2 +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 //Enable or disable level interrupt. Edge interrupt is always disabled. mwdt_ll_set_edge_intr(hal->mwdt_dev, false); mwdt_ll_set_level_intr(hal->mwdt_dev, enable_intr); diff --git a/components/heap/heap_caps_init.c b/components/heap/heap_caps_init.c index 75556dd155..5a7beb3a7c 100644 --- a/components/heap/heap_caps_init.c +++ b/components/heap/heap_caps_init.c @@ -189,14 +189,14 @@ bool heap_caps_check_add_region_allowed(intptr_t heap_start, intptr_t heap_end, * 3.add region (s3>=s && e3= heap_start && end < heap_end; * |--------------| correct * - * 4.add region (s4e) |------------------------| wrong: bool condition_4 = start < heap_end && end > heap_end; + * 4.add region (s4=e) |------------------------| wrong: bool condition_4 = start < heap_end && end >= heap_end; * |---------------------| wrong * * 5.add region (s5>=e) |----| correct: bool condition_5 = start >= heap_end; */ bool condition_2 = start < heap_start && end > heap_start; // if true then region not allowed - bool condition_4 = start < heap_end && end > heap_end; // if true then region not allowed + bool condition_4 = start < heap_end && end >= heap_end; // if true then region not allowed return (condition_2 || condition_4) ? false: true; } diff --git a/components/heap/include/esp_heap_caps.h b/components/heap/include/esp_heap_caps.h index a48adb867f..bd5e30a2f5 100644 --- a/components/heap/include/esp_heap_caps.h +++ b/components/heap/include/esp_heap_caps.h @@ -58,8 +58,6 @@ esp_err_t heap_caps_register_failed_alloc_callback(esp_alloc_failed_hook_t callb * * Equivalent semantics to libc malloc(), for capability-aware memory. * - * In IDF, ``malloc(p)`` is equivalent to ``heap_caps_malloc(p, MALLOC_CAP_8BIT)``. - * * @param size Size, in bytes, of the amount of memory to allocate * @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type * of memory to be returned diff --git a/components/heap/include/multi_heap.h b/components/heap/include/multi_heap.h index 6b0990c72d..e2aa6672d7 100644 --- a/components/heap/include/multi_heap.h +++ b/components/heap/include/multi_heap.h @@ -125,6 +125,8 @@ void multi_heap_dump(multi_heap_handle_t heap); * can be optionally printed to stderr. Print behaviour can be overridden at compile time by defining * MULTI_CHECK_FAIL_PRINTF in multi_heap_platform.h. * + * @note This function is not thread-safe as it sets a global variable with the value of print_errors. + * * @param heap Handle to a registered heap. * @param print_errors If true, errors will be printed to stderr. * @return true if heap is valid, false otherwise. diff --git a/components/heap/multi_heap.c b/components/heap/multi_heap.c index 1a0871f457..8481268d55 100644 --- a/components/heap/multi_heap.c +++ b/components/heap/multi_heap.c @@ -81,7 +81,7 @@ typedef struct multi_heap_info { void* heap_data; } heap_t; -#ifdef CONFIG_HEAP_TLSF_USE_ROM_IMPL +#if CONFIG_HEAP_TLSF_USE_ROM_IMPL void _multi_heap_lock(void *lock) { @@ -103,7 +103,7 @@ void multi_heap_in_rom_init(void) multi_heap_os_funcs_init(&multi_heap_os_funcs); } -#else //#ifndef CONFIG_HEAP_TLSF_USE_ROM_IMPL +#else // CONFIG_HEAP_TLSF_USE_ROM_IMPL /* Return true if this block is free. */ static inline bool is_free(const block_header_t *block) @@ -309,13 +309,46 @@ void *multi_heap_aligned_alloc_impl(multi_heap_handle_t heap, size_t size, size_ return multi_heap_aligned_alloc_impl_offs(heap, size, alignment, 0); } +#ifdef MULTI_HEAP_POISONING +/*! + * @brief Global definition of print_errors set in multi_heap_check() when + * MULTI_HEAP_POISONING is active. Allows the transfer of the value to + * multi_heap_poisoning.c without having to propagate it to the tlsf submodule + * and back. + */ +static bool g_print_errors = false; + +/*! + * @brief Definition of the weak function declared in TLSF repository. + * The call of this function execute a check for block poisoning on the memory + * chunk passed as parameter. + * + * @param start: pointer to the start of the memory region to check for corruption + * @param size: size of the memory region to check for corruption + * @param is_free: indicate if the pattern to use the fill the region should be + * an after free or after allocation pattern. + * + * @return bool: true if the the memory is not corrupted, false if the memory if corrupted. + */ +bool tlsf_check_hook(void *start, size_t size, bool is_free) +{ + return multi_heap_internal_check_block_poisoning(start, size, is_free, g_print_errors); +} +#endif // MULTI_HEAP_POISONING + bool multi_heap_check(multi_heap_handle_t heap, bool print_errors) { - (void)print_errors; bool valid = true; assert(heap != NULL); multi_heap_internal_lock(heap); + +#ifdef MULTI_HEAP_POISONING + g_print_errors = print_errors; +#else + (void) print_errors; +#endif + if(tlsf_check(heap->heap_data)) { valid = false; } diff --git a/components/heap/multi_heap_poisoning.c b/components/heap/multi_heap_poisoning.c index f59ef6766d..9cb42b95d4 100644 --- a/components/heap/multi_heap_poisoning.c +++ b/components/heap/multi_heap_poisoning.c @@ -25,8 +25,8 @@ #include "tlsf.h" #else /* Header containing the declaration of tlsf_poison_fill_pfunc_set() - * used to register multi_heap_internal_poison_fill_region() as a - * callback to fill memory region with given patterns in the heap + * and tlsf_poison_check_pfunc_set() used to register callbacks to + * fill and check memory region with given patterns in the heap * components. */ #include "rom/tlsf.h" @@ -359,9 +359,10 @@ multi_heap_handle_t multi_heap_register(void *start, size_t size) memset(start, FREE_FILL_PATTERN, size); } #endif -#ifdef CONFIG_HEAP_TLSF_USE_ROM_IMPL +#if CONFIG_HEAP_TLSF_USE_ROM_IMPL tlsf_poison_fill_pfunc_set(multi_heap_internal_poison_fill_region); -#endif + tlsf_poison_check_pfunc_set(multi_heap_internal_check_block_poisoning); +#endif // CONFIG_HEAP_TLSF_USE_ROM_IMPL return multi_heap_register_impl(start, size); } diff --git a/components/heap/port/esp32c6/memory_layout.c b/components/heap/port/esp32c6/memory_layout.c new file mode 100644 index 0000000000..201059bfd6 --- /dev/null +++ b/components/heap/port/esp32c6/memory_layout.c @@ -0,0 +1,100 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "esp_attr.h" +#include "sdkconfig.h" +#include "soc/soc.h" +#include "heap_memory_layout.h" +#include "esp_heap_caps.h" + +/** + * @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC. + * Each type of memory map consists of one or more regions in the address space. + * Each type contains an array of prioritized capabilities. + * Types with later entries are only taken if earlier ones can't fulfill the memory request. + * + * - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory. + * - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM. + * - Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM. + * - Most other malloc caps only fit in one region anyway. + * + */ + +/* Index of memory in `soc_memory_types[]` */ +enum { + SOC_MEMORY_TYPE_DRAM = 0, + SOC_MEMORY_TYPE_STACK_DRAM = 1, + SOC_MEMORY_TYPE_DIRAM = 2, + SOC_MEMORY_TYPE_RTCRAM = 3, + SOC_MEMORY_TYPE_NUM, +}; + +const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = { + // Type 0: DRAM + [SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false}, + // Type 1: DRAM used for startup stacks + [SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true}, + // Type 2: DRAM which has an alias on the I-port + [SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false}, + // Type 3: RTCRAM // TODO: IDF-5667 Better to rename to LPRAM + [SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false}, +}; + +#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE +#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM +#else +#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM +#endif + +const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); + +/** + * @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type. + * + * @note Because of requirements in the coalescing code which merges adjacent regions, + * this list should always be sorted from low to high by start address. + * + */ + +/** + * Register the shared buffer area of the last memory block into the heap during heap initialization + */ +#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) + +const soc_memory_region_t soc_memory_regions[] = { + { 0x40800000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40800000}, //D/IRAM level0, can be used as trace memory + { 0x40820000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40820000}, //D/IRAM level1, can be used as trace memory + { 0x40840000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40860000}, //D/IRAM level2, can be used as trace memory + { 0x40860000, (APP_USABLE_DRAM_END-0x40860000), SOC_MEMORY_TYPE_DEFAULT, 0x40860000}, //D/IRAM level3, can be used as trace memory + { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, APP_USABLE_DRAM_END}, //D/IRAM level3, can be used as trace memory (ROM reserved area) +#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP + { 0x50000000, 0x4000, SOC_MEMORY_TYPE_RTCRAM, 0}, //LPRAM +#endif +}; + +const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t); + + +extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end; + +/** + * Reserved memory regions. + * These are removed from the soc_memory_regions array when heaps are created. + * + */ + +// Static data region. DRAM used by data+bss and possibly rodata +SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data); + +// Target has a shared D/IRAM virtual address, no need to calculate I_D_OFFSET like previous chips +SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code); + +#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP +// TODO: IDF-6019 check reserved lp mem region +SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data); +#endif diff --git a/components/heap/port/memory_layout_utils.c b/components/heap/port/memory_layout_utils.c index bf4c4bc9a4..1f934b50fe 100644 --- a/components/heap/port/memory_layout_utils.c +++ b/components/heap/port/memory_layout_utils.c @@ -8,22 +8,21 @@ #include "sdkconfig.h" #include "esp_log.h" #include "soc/soc_memory_layout.h" +#include "esp_rom_caps.h" +#if ESP_ROM_HAS_LAYOUT_TABLE #ifdef CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/rom_layout.h" -#define ROM_HAS_LAYOUT_TABLE 1 #elif CONFIG_IDF_TARGET_ESP32S3 #include "esp32s3/rom/rom_layout.h" -#define ROM_HAS_LAYOUT_TABLE 1 #elif CONFIG_IDF_TARGET_ESP32H2 #include "esp32h2/rom/rom_layout.h" -#define ROM_HAS_LAYOUT_TABLE 1 #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/rom_layout.h" -#define ROM_HAS_LAYOUT_TABLE 1 -#else -#define ROM_HAS_LAYOUT_TABLE 0 +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/rom_layout.h" #endif +#endif // ESP_ROM_HAS_LAYOUT_TABLE static const char *TAG = "memory_layout"; @@ -38,7 +37,7 @@ static size_t s_get_num_reserved_regions(void) { size_t result = ( &soc_reserved_memory_region_end - &soc_reserved_memory_region_start ); -#if ROM_HAS_LAYOUT_TABLE +#if ESP_ROM_HAS_LAYOUT_TABLE return result + 1; // ROM table means one entry needs to be added at runtime #else return result; @@ -66,7 +65,7 @@ static int s_compare_reserved_regions(const void *a, const void *b) */ static void s_prepare_reserved_regions(soc_reserved_region_t *reserved, size_t count) { -#if ROM_HAS_LAYOUT_TABLE +#if ESP_ROM_HAS_LAYOUT_TABLE /* Get the ROM layout to find which part of DRAM is reserved */ const ets_rom_layout_t *layout = ets_rom_layout_p; reserved[0].start = (intptr_t)layout->dram0_rtos_reserved_start; diff --git a/components/heap/test/CMakeLists.txt b/components/heap/test/CMakeLists.txt deleted file mode 100644 index 3ccce3753e..0000000000 --- a/components/heap/test/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -idf_component_register(SRC_DIRS "." - PRIV_INCLUDE_DIRS "." - PRIV_REQUIRES cmock test_utils heap) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/components/heap/test_apps/CMakeLists.txt b/components/heap/test_apps/CMakeLists.txt new file mode 100644 index 0000000000..df2d30eeb0 --- /dev/null +++ b/components/heap/test_apps/CMakeLists.txt @@ -0,0 +1,6 @@ +# The following lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(test_heap) diff --git a/components/heap/test_apps/README.md b/components/heap/test_apps/README.md new file mode 100644 index 0000000000..284564238d --- /dev/null +++ b/components/heap/test_apps/README.md @@ -0,0 +1,2 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | \ No newline at end of file diff --git a/components/heap/test_apps/main/CMakeLists.txt b/components/heap/test_apps/main/CMakeLists.txt new file mode 100644 index 0000000000..d823d12c98 --- /dev/null +++ b/components/heap/test_apps/main/CMakeLists.txt @@ -0,0 +1,14 @@ +set(src_test "test_heap_main.c" + "test_aligned_alloc_caps.c" + "test_allocator_timings.c" + "test_corruption_check.c" + "test_diram.c" + "test_heap_trace.c" + "test_malloc_caps.c" + "test_malloc.c" + "test_realloc.c" + "test_runtime_heap_reg.c") + +idf_component_register(SRCS ${src_test} + INCLUDE_DIRS "." + WHOLE_ARCHIVE) diff --git a/components/heap/test/test_aligned_alloc_caps.c b/components/heap/test_apps/main/test_aligned_alloc_caps.c similarity index 83% rename from components/heap/test/test_aligned_alloc_caps.c rename to components/heap/test_apps/main/test_aligned_alloc_caps.c index 60b8866f12..4da12332ef 100644 --- a/components/heap/test/test_aligned_alloc_caps.c +++ b/components/heap/test_apps/main/test_aligned_alloc_caps.c @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ /* Tests for the capabilities-based memory allocator. */ @@ -12,6 +17,7 @@ #include #include #include +#include TEST_CASE("Capabilities aligned allocator test", "[heap]") { @@ -23,10 +29,10 @@ TEST_CASE("Capabilities aligned allocator test", "[heap]") uint8_t *buf = (uint8_t *)memalign(alignments, (alignments + 137)); if(((alignments & (alignments - 1)) != 0) || (!alignments)) { TEST_ASSERT( buf == NULL ); - //printf("[ALIGNED_ALLOC] alignment: %u is not a power of two, don't allow allocation \n", aligments); + //printf("[ALIGNED_ALLOC] alignment: %"PRIu32" is not a power of two, don't allow allocation \n", aligments); } else { TEST_ASSERT( buf != NULL ); - printf("[ALIGNED_ALLOC] alignment required: %u \n", alignments); + printf("[ALIGNED_ALLOC] alignment required: %"PRIu32" \n", alignments); printf("[ALIGNED_ALLOC] address of allocated memory: %p \n\n", (void *)buf); //Address of obtained block must be aligned with selected value TEST_ASSERT(((intptr_t)buf & (alignments - 1)) == 0); @@ -52,10 +58,10 @@ TEST_CASE("Capabilities aligned allocator test", "[heap]") uint8_t *buf = (uint8_t *)heap_caps_aligned_alloc(alignments, 10*1024, MALLOC_CAP_SPIRAM); if(((alignments & (alignments - 1)) != 0) || (!alignments)) { TEST_ASSERT( buf == NULL ); - //printf("[ALIGNED_ALLOC] alignment: %u is not a power of two, don't allow allocation \n", aligments); + //printf("[ALIGNED_ALLOC] alignment: %"PRIu32" is not a power of two, don't allow allocation \n", aligments); } else { TEST_ASSERT( buf != NULL ); - printf("[ALIGNED_ALLOC] alignment required: %u \n", alignments); + printf("[ALIGNED_ALLOC] alignment required: %"PRIu32" \n", alignments); printf("[ALIGNED_ALLOC] address of allocated memory: %p \n\n", (void *)buf); //Address of obtained block must be aligned with selected value TEST_ASSERT(((intptr_t)buf & (alignments - 1)) == 0); @@ -80,10 +86,10 @@ TEST_CASE("Capabilities aligned calloc test", "[heap]") uint8_t *buf = (uint8_t *)heap_caps_aligned_calloc(alignments, 1, (alignments + 137), MALLOC_CAP_DEFAULT); if(((alignments & (alignments - 1)) != 0) || (!alignments)) { TEST_ASSERT( buf == NULL ); - //printf("[ALIGNED_ALLOC] alignment: %u is not a power of two, don't allow allocation \n", aligments); + //printf("[ALIGNED_ALLOC] alignment: %"PRIu32" is not a power of two, don't allow allocation \n", aligments); } else { TEST_ASSERT( buf != NULL ); - printf("[ALIGNED_ALLOC] alignment required: %u \n", alignments); + printf("[ALIGNED_ALLOC] alignment required: %"PRIu32" \n", alignments); printf("[ALIGNED_ALLOC] address of allocated memory: %p \n\n", (void *)buf); //Address of obtained block must be aligned with selected value TEST_ASSERT(((intptr_t)buf & (alignments - 1)) == 0); @@ -120,10 +126,10 @@ TEST_CASE("Capabilities aligned calloc test", "[heap]") uint8_t *buf = (uint8_t *)(uint8_t *)heap_caps_aligned_calloc(alignments, 1, 10*1024, MALLOC_CAP_SPIRAM); if(((alignments & (alignments - 1)) != 0) || (!alignments)) { TEST_ASSERT( buf == NULL ); - //printf("[ALIGNED_ALLOC] alignment: %u is not a power of two, don't allow allocation \n", aligments); + //printf("[ALIGNED_ALLOC] alignment: %"PRIu32" is not a power of two, don't allow allocation \n", aligments); } else { TEST_ASSERT( buf != NULL ); - printf("[ALIGNED_ALLOC] alignment required: %u \n", alignments); + printf("[ALIGNED_ALLOC] alignment required: %"PRIu32" \n", alignments); printf("[ALIGNED_ALLOC] address of allocated memory: %p \n\n", (void *)buf); //Address of obtained block must be aligned with selected value TEST_ASSERT(((intptr_t)buf & (alignments - 1)) == 0); diff --git a/components/heap/test/test_allocator_timings.c b/components/heap/test_apps/main/test_allocator_timings.c similarity index 82% rename from components/heap/test/test_allocator_timings.c rename to components/heap/test_apps/main/test_allocator_timings.c index 0e130c95b6..7fe740a7a8 100644 --- a/components/heap/test/test_allocator_timings.c +++ b/components/heap/test_apps/main/test_allocator_timings.c @@ -1,19 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ #include "freertos/FreeRTOS.h" #include #include #include "unity.h" #include "esp_attr.h" #include "esp_heap_caps.h" +#include "esp_log.h" #include #include #include -#include //This test only makes sense with poisoning disabled (light or comprehensive) #if !defined(CONFIG_HEAP_POISONING_COMPREHENSIVE) && !defined(CONFIG_HEAP_POISONING_LIGHT) #define NUM_POINTERS 128 -#define ITERATIONS 10000 +#define ITERATIONS 5000 + +static const char *TAG = "test_heap"; TEST_CASE("Heap many random allocations timings", "[heap]") { @@ -26,19 +33,19 @@ TEST_CASE("Heap many random allocations timings", "[heap]") uint64_t realloc_time_average = 0; for (int i = 0; i < ITERATIONS; i++) { - uint8_t n = esp_random() % NUM_POINTERS; + uint8_t n = (uint32_t)rand() % NUM_POINTERS; - if (esp_random() % 4 == 0) { + if (i % 4 == 0) { /* 1 in 4 iterations, try to realloc the buffer instead of using malloc/free */ - size_t new_size = esp_random() % 1024; + size_t new_size = (uint32_t)rand() % 1024; cycles_before = portGET_RUN_TIME_COUNTER_VALUE(); void *new_p = heap_caps_realloc(p[n], new_size, MALLOC_CAP_DEFAULT); realloc_time_average = portGET_RUN_TIME_COUNTER_VALUE() - cycles_before; - printf("realloc %p -> %p (%zu -> %zu) time spent cycles: %lld \n", p[n], new_p, s[n], new_size, realloc_time_average); + ESP_LOGD(TAG, "realloc %p -> %p (%zu -> %zu) time spent cycles: %lld \n", p[n], new_p, s[n], new_size, realloc_time_average); heap_caps_check_integrity(MALLOC_CAP_DEFAULT, true); if (new_size == 0 || new_p != NULL) { p[n] = new_p; @@ -63,7 +70,7 @@ TEST_CASE("Heap many random allocations timings", "[heap]") heap_caps_free(p[n]); free_time_average = portGET_RUN_TIME_COUNTER_VALUE() - cycles_before; - printf("freed %p (%zu) time spent cycles: %lld\n", p[n], s[n], free_time_average); + ESP_LOGD(TAG, "freed %p (%zu) time spent cycles: %lld\n", p[n], s[n], free_time_average); if (!heap_caps_check_integrity(MALLOC_CAP_DEFAULT, true)) { printf("FAILED iteration %d after freeing %p\n", i, p[n]); @@ -78,7 +85,7 @@ TEST_CASE("Heap many random allocations timings", "[heap]") p[n] = heap_caps_malloc(s[n], MALLOC_CAP_DEFAULT); alloc_time_average = portGET_RUN_TIME_COUNTER_VALUE() - cycles_before; - printf("malloc %p (%zu) time spent cycles: %lld \n", p[n], s[n], alloc_time_average); + ESP_LOGD(TAG, "malloc %p (%zu) time spent cycles: %lld \n", p[n], s[n], alloc_time_average); if (!heap_caps_check_integrity(MALLOC_CAP_DEFAULT, true)) { printf("FAILED iteration %d after mallocing %p (%zu bytes)\n", i, p[n], s[n]); diff --git a/components/heap/test_apps/main/test_corruption_check.c b/components/heap/test_apps/main/test_corruption_check.c new file mode 100644 index 0000000000..d7dc8125ac --- /dev/null +++ b/components/heap/test_apps/main/test_corruption_check.c @@ -0,0 +1,73 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include "unity.h" +#include "stdio.h" + +#include "esp_heap_caps.h" + +//This test only makes sense with poisoning enabled (light or comprehensive) +#if defined(CONFIG_HEAP_POISONING_COMPREHENSIVE) || defined(CONFIG_HEAP_POISONING_LIGHT) + +/* executing multi_heap_internal_check_block_poisoning() + * takes longer on external RAM and therefore the timeout + * in the test of 30 seconds is exceeded. Execute the test + * on a smaller memory chunk + */ +#ifdef CONFIG_SPIRAM +const size_t MALLOC_SIZE = 16; +#else +const size_t MALLOC_SIZE = 64; +#endif +const uint8_t CORRUPTED_VALUE = 0xaa; + +/* This test will corrupt the memory of a free block in the heap and check + * that in the case of comprehensive poisoning the heap corruption is detected + * by heap_caps_check_integrity(). For light poisoning and no poisoning, the test will + * check that heap_caps_check_integrity() does not report the corruption. + */ +TEST_CASE("multi_heap poisoning detection", "[heap]") +{ + /* malloc some memory to get a pointer */ + uint8_t *ptr = heap_caps_malloc(MALLOC_SIZE, MALLOC_CAP_8BIT); + + /* free the memory to free the block but keep the pointer in mind */ + heap_caps_free(ptr); + + /* variable used in the test */ + uint8_t original_value = 0x00; + + for (size_t i = 0; i < MALLOC_SIZE; i++) + { + /* keep the good value in store in order to check that when we set the byte back + * to its original value, heap_caps_check_integrity() no longer returns the + * heap corruption. */ + original_value = ptr[i]; + + /* set corrupted value in the free memory*/ + ptr[i] = CORRUPTED_VALUE; + + bool is_heap_ok = heap_caps_check_integrity(MALLOC_CAP_8BIT, true); + + /* fix the corruption by restoring the original value at ptr + i. + * We need to do this before the ASSERT because they may print a message. + * Using print allocates memory on the heap, so the heap has to be fixed. */ + ptr[i] = original_value; + +#if CONFIG_HEAP_POISONING_COMPREHENSIVE + /* check that heap_caps_check_integrity() detects the corruption */ + TEST_ASSERT_FALSE(is_heap_ok); +#else + /* the comprehensive corruption is not checked in the heap_caps_check_integrity() */ + TEST_ASSERT_TRUE(is_heap_ok); +#endif + + /* check that heap_caps_check_integrity() stops reporting the corruption */ + is_heap_ok = heap_caps_check_integrity(MALLOC_CAP_8BIT, true); + TEST_ASSERT_TRUE(is_heap_ok); + } +} + +#endif diff --git a/components/heap/test/test_diram.c b/components/heap/test_apps/main/test_diram.c similarity index 90% rename from components/heap/test/test_diram.c rename to components/heap/test_apps/main/test_diram.c index f31aecb673..569139f93b 100644 --- a/components/heap/test/test_diram.c +++ b/components/heap/test_apps/main/test_diram.c @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ /* Tests for D/IRAM support in heap capability allocator */ @@ -12,6 +17,7 @@ #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) //IDF-5167 +#ifndef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE static void *malloc_block_diram(uint32_t caps) { void *attempts[256] = { 0 }; // Allocate up to 256 ALLOC_SZ blocks to exhaust all non-D/IRAM memory temporarily @@ -74,4 +80,5 @@ TEST_CASE("Allocate D/IRAM as IRAM", "[heap]") free(iram); } +#endif // CONFIG_ESP_SYSTEM_MEMPROT_FEATURE #endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) diff --git a/components/heap/test_apps/main/test_heap_main.c b/components/heap/test_apps/main/test_heap_main.c new file mode 100644 index 0000000000..c271df754f --- /dev/null +++ b/components/heap/test_apps/main/test_heap_main.c @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "unity.h" +#include "unity_test_runner.h" +#include "esp_heap_caps.h" + +#define TEST_MEMORY_LEAK_THRESHOLD_DEFAULT -100 +static int leak_threshold = TEST_MEMORY_LEAK_THRESHOLD_DEFAULT; +void set_leak_threshold(int threshold) +{ + leak_threshold = threshold; +} + +static size_t before_free_8bit; +static size_t before_free_32bit; + +static void check_leak(size_t before_free, size_t after_free, const char *type) +{ + ssize_t delta = after_free - before_free; + printf("MALLOC_CAP_%s: Before %u bytes free, After %u bytes free (delta %d)\n", type, before_free, after_free, delta); + TEST_ASSERT_MESSAGE(delta >= leak_threshold, "memory leak"); +} + +void setUp(void) +{ + before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); +} + +void tearDown(void) +{ + size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); + check_leak(before_free_8bit, after_free_8bit, "8BIT"); + check_leak(before_free_32bit, after_free_32bit, "32BIT"); + + leak_threshold = TEST_MEMORY_LEAK_THRESHOLD_DEFAULT; +} + +void app_main(void) +{ + printf("Running heap component tests\n"); + unity_run_menu(); +} diff --git a/components/heap/test/test_heap_trace.c b/components/heap/test_apps/main/test_heap_trace.c similarity index 97% rename from components/heap/test/test_heap_trace.c rename to components/heap/test_apps/main/test_heap_trace.c index 909aa31b5c..b88e270b18 100644 --- a/components/heap/test/test_heap_trace.c +++ b/components/heap/test_apps/main/test_heap_trace.c @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ /* Generic test for heap tracing support diff --git a/components/heap/test/test_malloc.c b/components/heap/test_apps/main/test_malloc.c similarity index 97% rename from components/heap/test/test_malloc.c rename to components/heap/test_apps/main/test_malloc.c index 995a64da33..0fe523a7a0 100644 --- a/components/heap/test/test_malloc.c +++ b/components/heap/test_apps/main/test_malloc.c @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ /* Generic test for malloc/free */ diff --git a/components/heap/test/test_malloc_caps.c b/components/heap/test_apps/main/test_malloc_caps.c similarity index 97% rename from components/heap/test/test_malloc_caps.c rename to components/heap/test_apps/main/test_malloc_caps.c index 0010327441..2eb69625db 100644 --- a/components/heap/test/test_malloc_caps.c +++ b/components/heap/test_apps/main/test_malloc_caps.c @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ /* Tests for the capabilities-based memory allocator. */ @@ -106,7 +111,7 @@ TEST_CASE("Capabilities allocator test", "[heap]") free(m1); printf("Done.\n"); } -#endif +#endif // CONFIG_ESP_SYSTEM_MEMPROT_FEATURE #endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) #ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY @@ -175,6 +180,7 @@ TEST_CASE("heap_caps metadata test", "[heap]") /* Small function runs from IRAM to check that malloc/free/realloc all work OK when cache is disabled... */ +#ifndef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE static IRAM_ATTR __attribute__((noinline)) bool iram_malloc_test(void) { spi_flash_guard_get()->start(); // Disables flash cache @@ -196,6 +202,7 @@ TEST_CASE("heap_caps_xxx functions work with flash cache disabled", "[heap]") { TEST_ASSERT( iram_malloc_test() ); } +#endif // CONFIG_ESP_SYSTEM_MEMPROT_FEATURE #endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) #ifdef CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS @@ -212,7 +219,7 @@ static bool called_user_failed_hook = false; void heap_caps_alloc_failed_hook(size_t requested_size, uint32_t caps, const char *function_name) { - printf("%s was called but failed to allocate %d bytes with 0x%X capabilities. \n",function_name, requested_size, caps); + printf("%s was called but failed to allocate %d bytes with 0x%lX capabilities. \n",function_name, requested_size, caps); called_user_failed_hook = true; } diff --git a/components/heap/test/test_realloc.c b/components/heap/test_apps/main/test_realloc.c similarity index 91% rename from components/heap/test/test_realloc.c rename to components/heap/test_apps/main/test_realloc.c index c106c57f19..d6e91e940d 100644 --- a/components/heap/test/test_realloc.c +++ b/components/heap/test_apps/main/test_realloc.c @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ /* Generic test for realloc */ @@ -64,5 +69,5 @@ TEST_CASE("realloc move data to a new heap type", "[heap]") free(c); } -#endif +#endif // CONFIG_ESP_SYSTEM_MEMPROT_FEATURE #endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) diff --git a/components/heap/test/test_runtime_heap_reg.c b/components/heap/test_apps/main/test_runtime_heap_reg.c similarity index 66% rename from components/heap/test/test_runtime_heap_reg.c rename to components/heap/test_apps/main/test_runtime_heap_reg.c index c7a9dc493c..8e54973ede 100644 --- a/components/heap/test/test_runtime_heap_reg.c +++ b/components/heap/test_apps/main/test_runtime_heap_reg.c @@ -1,41 +1,58 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ /* Tests for registering new heap memory at runtime */ #include #include +#include #include "unity.h" #include "esp_heap_caps_init.h" #include "esp_system.h" #include "heap_memory_layout.h" +#include "../tlsf/tlsf.h" + +extern void set_leak_threshold(int threshold); /* NOTE: This is not a well-formed unit test, it leaks memory */ -TEST_CASE("Allocate new heap at runtime", "[heap][ignore]") +TEST_CASE("Allocate new heap at runtime", "[heap]") { - const size_t BUF_SZ = 1000; - const size_t HEAP_OVERHEAD_MAX = 200; + // 84 bytes of overhead to account for multi_heap structs and eventual + // poisoning bytes + size of control_t from tlsf + const size_t HEAP_OVERHEAD_MAX = tlsf_size() + 84; + const size_t MIN_HEAP_SIZE = HEAP_OVERHEAD_MAX + tlsf_block_size_min(); + const size_t BUF_SZ = MIN_HEAP_SIZE; void *buffer = malloc(BUF_SZ); + TEST_ASSERT_NOT_NULL(buffer); uint32_t before_free = esp_get_free_heap_size(); TEST_ESP_OK( heap_caps_add_region((intptr_t)buffer, (intptr_t)buffer + BUF_SZ) ); uint32_t after_free = esp_get_free_heap_size(); - printf("Before %u after %u\n", before_free, after_free); + printf("Before %"PRIu32" after %"PRIu32"\n", before_free, after_free); /* allow for some 'heap overhead' from accounting structures */ TEST_ASSERT(after_free >= before_free + BUF_SZ - HEAP_OVERHEAD_MAX); + + // set the leak threshold to a bigger value as this test leaks memory + set_leak_threshold(-3000); } /* NOTE: This is not a well-formed unit test, it leaks memory and may fail if run twice in a row without a reset. */ -TEST_CASE("Allocate new heap with new capability", "[heap][ignore]") +TEST_CASE("Allocate new heap with new capability", "[heap]") { - const size_t BUF_SZ = 100; -#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE - const size_t ALLOC_SZ = 32; -#else - const size_t ALLOC_SZ = 64; // More than half of BUF_SZ -#endif + // 84 bytes of overhead to account for multi_heap structs and eventual + // poisoning bytes + size of control_t from tlsf + const size_t HEAP_OVERHEAD = tlsf_size() + 84; + const size_t MIN_HEAP_SIZE = HEAP_OVERHEAD + tlsf_block_size_min(); + const size_t BUF_SZ = MIN_HEAP_SIZE; + const size_t ALLOC_SZ = tlsf_block_size_min(); + const uint32_t MALLOC_CAP_INVENTED = (1 << 30); /* this must be unused in esp_heap_caps.h */ /* no memory exists to provide this capability */ @@ -48,23 +65,26 @@ TEST_CASE("Allocate new heap with new capability", "[heap][ignore]") /* ta-da, it's now possible! */ TEST_ASSERT_NOT_NULL( heap_caps_malloc(ALLOC_SZ, MALLOC_CAP_INVENTED) ); + + // set the leak threshold to a bigger value as this test leaks memory + set_leak_threshold(-3000); } /* NOTE: This is not a well-formed unit test. * If run twice without a reset, it will failed. */ -TEST_CASE("Add .bss memory to heap region runtime", "[heap][ignore]") +TEST_CASE("Add .bss memory to heap region runtime", "[heap]") { -#define BUF_SZ 1000 -#define HEAP_OVERHEAD_MAX 200 +#define HEAP_OVERHEAD_MAX 3248 +#define BUF_SZ 3260 static uint8_t s_buffer[BUF_SZ]; printf("s_buffer start %08x end %08x\n", (intptr_t)s_buffer, (intptr_t)s_buffer + BUF_SZ); uint32_t before_free = esp_get_free_heap_size(); TEST_ESP_OK( heap_caps_add_region((intptr_t)s_buffer, (intptr_t)s_buffer + BUF_SZ) ); uint32_t after_free = esp_get_free_heap_size(); - printf("Before %u after %u\n", before_free, after_free); + printf("Before %"PRIu32" after %"PRIu32"\n", before_free, after_free); /* allow for some 'heap overhead' from accounting structures */ TEST_ASSERT(after_free >= before_free + BUF_SZ - HEAP_OVERHEAD_MAX); @@ -81,10 +101,10 @@ TEST_CASE("Add heap region address range checks", "[heap]") TEST_ASSERT_TRUE(heap_caps_check_add_region_allowed(heap_start, heap_end, 0x0, 0x1000)); TEST_ASSERT_TRUE(heap_caps_check_add_region_allowed(heap_start, heap_end, 0x1000, 0x2000)); - TEST_ASSERT_TRUE(heap_caps_check_add_region_allowed(heap_start, heap_end, 0x1000, 0x3000)); TEST_ASSERT_TRUE(heap_caps_check_add_region_allowed(heap_start, heap_end, 0x3000, 0x4000)); TEST_ASSERT_FALSE(heap_caps_check_add_region_allowed(heap_start, heap_end, 0x0, 0x2000)); TEST_ASSERT_FALSE(heap_caps_check_add_region_allowed(heap_start, heap_end, 0x0, 0x4000)); TEST_ASSERT_FALSE(heap_caps_check_add_region_allowed(heap_start, heap_end, 0x1000, 0x4000)); TEST_ASSERT_FALSE(heap_caps_check_add_region_allowed(heap_start, heap_end, 0x2000, 0x4000)); + TEST_ASSERT_FALSE(heap_caps_check_add_region_allowed(heap_start, heap_end, 0x1000, 0x3000)); } diff --git a/components/heap/test_apps/pytest_heap.py b/components/heap/test_apps/pytest_heap.py new file mode 100644 index 0000000000..377e595c43 --- /dev/null +++ b/components/heap/test_apps/pytest_heap.py @@ -0,0 +1,66 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +import pytest +from pytest_embedded import Dut + + +@pytest.mark.generic +@pytest.mark.supported_targets +@pytest.mark.parametrize( + 'config', + [ + 'no_poisoning', + 'light_poisoning', + 'comprehensive_poisoning' + ] +) +def test_heap_poisoning(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('*') + dut.expect_unity_test_output(timeout=300) + + +@pytest.mark.generic +@pytest.mark.esp32 +@pytest.mark.esp32s2 +@pytest.mark.esp32s3 +@pytest.mark.parametrize( + 'config', + [ + 'psram', + 'psram_all_ext' + ] +) +def test_heap(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('*') + dut.expect_unity_test_output(timeout=300) + + +@pytest.mark.generic +@pytest.mark.esp32 +@pytest.mark.parametrize( + 'config', + [ + 'abort_alloc_fail' + ] +) +def test_heap_abort_on_alloc_failure(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('"When enabled, allocation operation failure generates an abort"') + dut.expect('Backtrace: ') + + +@pytest.mark.generic +@pytest.mark.esp32 +@pytest.mark.parametrize( + 'config', + [ + '8bit_access' + ] +) +def test_heap_8bit_access(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('"IRAM_8BIT capability test"') + dut.expect_unity_test_output(timeout=300) diff --git a/components/heap/test_apps/sdkconfig.ci.8bit_access b/components/heap/test_apps/sdkconfig.ci.8bit_access new file mode 100644 index 0000000000..c8710c4043 --- /dev/null +++ b/components/heap/test_apps/sdkconfig.ci.8bit_access @@ -0,0 +1,2 @@ +CONFIG_FREERTOS_UNICORE=y +CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY=y diff --git a/components/heap/test_apps/sdkconfig.ci.abort_alloc_fail b/components/heap/test_apps/sdkconfig.ci.abort_alloc_fail new file mode 100644 index 0000000000..1dd2c31d33 --- /dev/null +++ b/components/heap/test_apps/sdkconfig.ci.abort_alloc_fail @@ -0,0 +1 @@ +CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS=y diff --git a/components/heap/test_apps/sdkconfig.ci.comprehensive_poisoning b/components/heap/test_apps/sdkconfig.ci.comprehensive_poisoning new file mode 100644 index 0000000000..864e4213dd --- /dev/null +++ b/components/heap/test_apps/sdkconfig.ci.comprehensive_poisoning @@ -0,0 +1,3 @@ +CONFIG_HEAP_POISONING_DISABLED=n +CONFIG_HEAP_POISONING_LIGHT=n +CONFIG_HEAP_POISONING_COMPREHENSIVE=y diff --git a/tools/unit-test-app/configs/heap_light_poison b/components/heap/test_apps/sdkconfig.ci.light_poisoning similarity index 59% rename from tools/unit-test-app/configs/heap_light_poison rename to components/heap/test_apps/sdkconfig.ci.light_poisoning index 540d65168b..0e2c3bc1d2 100644 --- a/tools/unit-test-app/configs/heap_light_poison +++ b/components/heap/test_apps/sdkconfig.ci.light_poisoning @@ -1,4 +1,3 @@ -CONFIG_IDF_TARGET="esp32" -TEST_COMPONENTS=heap -CONFIG_HEAP_POISONING_COMPREHENSIVE=n +CONFIG_HEAP_POISONING_DISABLED=n CONFIG_HEAP_POISONING_LIGHT=y +CONFIG_HEAP_POISONING_COMPREHENSIVE=n diff --git a/components/heap/test_apps/sdkconfig.ci.no_poisoning b/components/heap/test_apps/sdkconfig.ci.no_poisoning new file mode 100644 index 0000000000..657a760928 --- /dev/null +++ b/components/heap/test_apps/sdkconfig.ci.no_poisoning @@ -0,0 +1,3 @@ +CONFIG_HEAP_POISONING_DISABLED=y +CONFIG_HEAP_POISONING_LIGHT=n +CONFIG_HEAP_POISONING_COMPREHENSIVE=n diff --git a/components/heap/test_apps/sdkconfig.ci.psram b/components/heap/test_apps/sdkconfig.ci.psram new file mode 100644 index 0000000000..cc641ea603 --- /dev/null +++ b/components/heap/test_apps/sdkconfig.ci.psram @@ -0,0 +1 @@ +CONFIG_SPIRAM=y diff --git a/components/heap/test_apps/sdkconfig.ci.psram_all_ext b/components/heap/test_apps/sdkconfig.ci.psram_all_ext new file mode 100644 index 0000000000..db575808cf --- /dev/null +++ b/components/heap/test_apps/sdkconfig.ci.psram_all_ext @@ -0,0 +1,2 @@ +CONFIG_SPIRAM=y +CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=0 diff --git a/components/heap/test_apps/sdkconfig.defaults b/components/heap/test_apps/sdkconfig.defaults new file mode 100644 index 0000000000..0e8a2c2557 --- /dev/null +++ b/components/heap/test_apps/sdkconfig.defaults @@ -0,0 +1,2 @@ +CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=n +CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=n # memory protection needs to be disabled for certain tests diff --git a/components/heap/test_multi_heap_host/Makefile b/components/heap/test_multi_heap_host/Makefile index 6c10f8035a..7d97cbcc6f 100644 --- a/components/heap/test_multi_heap_host/Makefile +++ b/components/heap/test_multi_heap_host/Makefile @@ -17,7 +17,7 @@ INCLUDE_FLAGS = -I../include -I../../../tools/catch -I../tlsf GCOV ?= gcov -CPPFLAGS += $(INCLUDE_FLAGS) -D CONFIG_LOG_DEFAULT_LEVEL -g -fstack-protector-all -m32 -DCONFIG_HEAP_POISONING_COMPREHENSIVE +CPPFLAGS += $(INCLUDE_FLAGS) -D CONFIG_LOG_DEFAULT_LEVEL -g -fstack-protector-all -m32 CFLAGS += -Wall -Werror -fprofile-arcs -ftest-coverage CXXFLAGS += -std=c++11 -Wall -Werror -fprofile-arcs -ftest-coverage LDFLAGS += -lstdc++ -fprofile-arcs -ftest-coverage -m32 diff --git a/components/heap/test_multi_heap_host/test_multi_heap.cpp b/components/heap/test_multi_heap_host/test_multi_heap.cpp index e85cceddc6..c3cac1cad1 100644 --- a/components/heap/test_multi_heap_host/test_multi_heap.cpp +++ b/components/heap/test_multi_heap_host/test_multi_heap.cpp @@ -2,6 +2,8 @@ #include "multi_heap.h" #include "../multi_heap_config.h" +#include "../tlsf/tlsf_common.h" +#include "../tlsf/tlsf_block_functions.h" #include #include @@ -523,3 +525,65 @@ TEST_CASE("multi_heap allocation overhead", "[multi_heap]") multi_heap_free(heap, x); } + +/* This test will corrupt the memory of a free block in the heap and check + * that in the case of comprehensive poisoning the heap corruption is detected + * by multi_heap_check(). For light poisoning and no poisoning, the test will + * check that multi_heap_check() does not report the corruption. + */ +TEST_CASE("multi_heap poisoning detection", "[multi_heap]") +{ + const size_t HEAP_SIZE = 4 * 1024; + + /* define heap related data */ + uint8_t heap_mem[HEAP_SIZE]; + memset(heap_mem, 0x00, HEAP_SIZE); + + /* register the heap memory. One free block only will be available */ + multi_heap_handle_t heap = multi_heap_register(heap_mem, HEAP_SIZE); + + /* offset in memory at which to find the first free memory byte */ + const size_t free_memory_offset = sizeof(multi_heap_info_t) + sizeof(control_t) + block_header_overhead; + + /* block header of the free block under test in the heap () */ + const block_header_t* block = (block_header_t*)(heap_mem + free_memory_offset - sizeof(block_header_t)); + + /* actual number of bytes potentially filled with the free pattern in the free block under test */ + const size_t effective_free_size = block_size(block) - block_header_overhead - offsetof(block_header_t, next_free); + + /* variable used in the test */ + size_t affected_byte = 0x00; + uint8_t original_value = 0x00; + uint8_t corrupted_value = 0x00; + + /* repeat the corruption a few times to cover more of the free memory */ + for (size_t i = 0; i < effective_free_size; i++) + { + /* corrupt random bytes in the heap (it needs to be bytes from free memory in + * order to check that the comprehensive poisoning is doing its job) */ + affected_byte = free_memory_offset + i; + corrupted_value = (rand() % UINT8_MAX) | 1; + + /* keep the good value in store in order to check that when we set the byte back + * to its original value, multi_heap_check() no longer returns the heap corruption. */ + original_value = heap_mem[affected_byte]; + + /* make sure we are not replacing the original value with the same value */ + heap_mem[affected_byte] ^= corrupted_value; + + bool is_heap_ok = multi_heap_check(heap, true); +#ifdef CONFIG_HEAP_POISONING_COMPREHENSIVE + /* check that multi_heap_check() detects the corruption */ + REQUIRE(is_heap_ok == false); +#else + /* the comprehensive corruption is not checked in the multi_heap_check() */ + REQUIRE(is_heap_ok == true); +#endif + /* fix the corruption */ + heap_mem[affected_byte] = original_value; + + /* check that multi_heap_check() stops reporting the corruption */ + is_heap_ok = multi_heap_check(heap, true); + REQUIRE(is_heap_ok == true); + } +} diff --git a/components/heap/tlsf b/components/heap/tlsf index ff11688f24..ab17d6798d 160000 --- a/components/heap/tlsf +++ b/components/heap/tlsf @@ -1 +1 @@ -Subproject commit ff11688f242b28b3918c2cdaa20738d12d73b5f4 +Subproject commit ab17d6798d1561758827b6553d56d57f19aa4d66 diff --git a/components/idf_test/include/esp32c6/.gitkeep b/components/idf_test/include/esp32c6/.gitkeep new file mode 100644 index 0000000000..e69de29bb2 diff --git a/components/ieee802154/CMakeLists.txt b/components/ieee802154/CMakeLists.txt index 65f3f1760d..c96b558752 100644 --- a/components/ieee802154/CMakeLists.txt +++ b/components/ieee802154/CMakeLists.txt @@ -22,7 +22,7 @@ if(CONFIG_IEEE802154_ENABLED) "-L ${CMAKE_CURRENT_SOURCE_DIR}/lib/${idf_target}/rev2") endif() else() - target_link_libraries(${COMPONENT_LIB} INTERFACE "-L ${CMAKE_CURRENT_SOURCE_DIR}/lib/${idf_target}") + target_link_directories(${COMPONENT_LIB} INTERFACE "${CMAKE_CURRENT_SOURCE_DIR}/lib/${idf_target}") endif() target_link_libraries(${COMPONENT_LIB} INTERFACE $ lib802154.a libphy.a libbtbb.a $) diff --git a/components/ieee802154/lib b/components/ieee802154/lib index d9838acadd..2b52a261fe 160000 --- a/components/ieee802154/lib +++ b/components/ieee802154/lib @@ -1 +1 @@ -Subproject commit d9838acadd72e5021cee5f79a897e195076d3645 +Subproject commit 2b52a261fef2ad7b630e11866dca567d17170401 diff --git a/components/lwip/lwip b/components/lwip/lwip index 3f5a04bc63..316cfc17ce 160000 --- a/components/lwip/lwip +++ b/components/lwip/lwip @@ -1 +1 @@ -Subproject commit 3f5a04bc63c8c1b1509bfe06cf941a51c9e80d4a +Subproject commit 316cfc17ce24f2d5d65c9f28251ec43a59a74cb1 diff --git a/components/mbedtls/CMakeLists.txt b/components/mbedtls/CMakeLists.txt index 51d6331978..881c34b5ab 100644 --- a/components/mbedtls/CMakeLists.txt +++ b/components/mbedtls/CMakeLists.txt @@ -8,7 +8,7 @@ if(NOT BOOTLOADER_BUILD) endif() set(mbedtls_srcs "") -set(mbedtls_include_dirs "port/include" "mbedtls/include" "./mbedtls/library") +set(mbedtls_include_dirs "port/include" "mbedtls/include" "mbedtls/library") if(CONFIG_MBEDTLS_CERTIFICATE_BUNDLE) list(APPEND mbedtls_srcs "esp_crt_bundle/esp_crt_bundle.c") @@ -238,6 +238,7 @@ endforeach() if(CONFIG_MBEDTLS_DYNAMIC_BUFFER) set(WRAP_FUNCTIONS + mbedtls_ssl_write_client_hello mbedtls_ssl_handshake_client_step mbedtls_ssl_handshake_server_step mbedtls_ssl_read @@ -268,6 +269,5 @@ endif() # Link esp-cryptoauthlib to mbedtls if(CONFIG_ATCA_MBEDTLS_ECDSA) - idf_component_get_property(cryptoauthlib esp-cryptoauthlib COMPONENT_LIB) - target_link_libraries(${COMPONENT_LIB} ${linkage_type} ${cryptoauthlib}) + idf_component_optional_requires(PRIVATE espressif__esp-cryptoauthlib esp-cryptoauthlib) endif() diff --git a/components/mbedtls/esp_crt_bundle/gen_crt_bundle.py b/components/mbedtls/esp_crt_bundle/gen_crt_bundle.py index 6c5d18edff..0211514a46 100755 --- a/components/mbedtls/esp_crt_bundle/gen_crt_bundle.py +++ b/components/mbedtls/esp_crt_bundle/gen_crt_bundle.py @@ -107,7 +107,7 @@ class CertificateBundle: if start is True: crt += strg - if(count == 0): + if count == 0: raise InputError('No certificate found') status('Successfully added %d certificates' % count) diff --git a/components/mbedtls/mbedtls b/components/mbedtls/mbedtls index 9bb5effc32..7b428b1bf2 160000 --- a/components/mbedtls/mbedtls +++ b/components/mbedtls/mbedtls @@ -1 +1 @@ -Subproject commit 9bb5effc3298265f829878825d9bd38478e67514 +Subproject commit 7b428b1bf260ce1fec4e3ffb6494070d439a3a67 diff --git a/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.c b/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.c index a44723d33c..fb9c93bdcf 100644 --- a/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.c +++ b/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.c @@ -458,10 +458,10 @@ size_t esp_mbedtls_get_crt_size(mbedtls_x509_crt *cert, size_t *num) size_t bytes = 0; while (cert) { - bytes += cert->MBEDTLS_PRIVATE(raw).MBEDTLS_PRIVATE(len); + bytes += cert->raw.len; n++; - cert = cert->MBEDTLS_PRIVATE(next); + cert = cert->next; } *num = n; @@ -473,14 +473,15 @@ size_t esp_mbedtls_get_crt_size(mbedtls_x509_crt *cert, size_t *num) void esp_mbedtls_free_dhm(mbedtls_ssl_context *ssl) { #ifdef CONFIG_MBEDTLS_DHM_C - mbedtls_mpi_free((mbedtls_mpi *)&ssl->MBEDTLS_PRIVATE(conf)->MBEDTLS_PRIVATE(dhm_P)); - mbedtls_mpi_free((mbedtls_mpi *)&ssl->MBEDTLS_PRIVATE(conf)->MBEDTLS_PRIVATE(dhm_G)); + const mbedtls_ssl_config *conf = mbedtls_ssl_context_get_config(ssl); + mbedtls_mpi_free((mbedtls_mpi *)conf->MBEDTLS_PRIVATE(dhm_P)); + mbedtls_mpi_free((mbedtls_mpi *)conf->MBEDTLS_PRIVATE(dhm_G)); #endif /* CONFIG_MBEDTLS_DHM_C */ } void esp_mbedtls_free_keycert(mbedtls_ssl_context *ssl) { - mbedtls_ssl_config *conf = (mbedtls_ssl_config *)ssl->MBEDTLS_PRIVATE(conf); + mbedtls_ssl_config *conf = (mbedtls_ssl_config * )mbedtls_ssl_context_get_config(ssl); mbedtls_ssl_key_cert *keycert = conf->MBEDTLS_PRIVATE(key_cert), *next; while (keycert) { @@ -498,7 +499,8 @@ void esp_mbedtls_free_keycert(mbedtls_ssl_context *ssl) void esp_mbedtls_free_keycert_key(mbedtls_ssl_context *ssl) { - mbedtls_ssl_key_cert *keycert = ssl->MBEDTLS_PRIVATE(conf)->MBEDTLS_PRIVATE(key_cert); + const mbedtls_ssl_config *conf = mbedtls_ssl_context_get_config(ssl); + mbedtls_ssl_key_cert *keycert = conf->MBEDTLS_PRIVATE(key_cert); while (keycert) { if (keycert->key) { @@ -511,7 +513,8 @@ void esp_mbedtls_free_keycert_key(mbedtls_ssl_context *ssl) void esp_mbedtls_free_keycert_cert(mbedtls_ssl_context *ssl) { - mbedtls_ssl_key_cert *keycert = ssl->MBEDTLS_PRIVATE(conf)->MBEDTLS_PRIVATE(key_cert); + const mbedtls_ssl_config *conf = mbedtls_ssl_context_get_config(ssl); + mbedtls_ssl_key_cert *keycert = conf->MBEDTLS_PRIVATE(key_cert); while (keycert) { if (keycert->cert) { @@ -527,7 +530,7 @@ void esp_mbedtls_free_keycert_cert(mbedtls_ssl_context *ssl) void esp_mbedtls_free_cacert(mbedtls_ssl_context *ssl) { if (ssl->MBEDTLS_PRIVATE(conf)->MBEDTLS_PRIVATE(ca_chain)) { - mbedtls_ssl_config *conf = (mbedtls_ssl_config *)ssl->MBEDTLS_PRIVATE(conf); + mbedtls_ssl_config *conf = (mbedtls_ssl_config * )mbedtls_ssl_context_get_config(ssl); mbedtls_x509_crt_free(conf->MBEDTLS_PRIVATE(ca_chain)); conf->MBEDTLS_PRIVATE(ca_chain) = NULL; diff --git a/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.h b/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.h index 6adda7bb84..72641b3a54 100644 --- a/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.h +++ b/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.h @@ -9,15 +9,19 @@ #include #include #include -/* ToDo - Remove this once appropriate solution is available. -We need to define this for the file as ssl_misc.h uses private structures from mbedtls, -which are undefined if the following flag is not defined */ -/* Many APIs in the file make use of this flag instead of `MBEDTLS_PRIVATE` */ -/* ToDo - Replace them with proper getter-setter once they are added */ + +/* TODO: Remove this once the appropriate solution is found + * + * ssl_misc.h header uses private elements from + * mbedtls, which become undefined if the following flag + * is not defined + */ #define MBEDTLS_ALLOW_PRIVATE_ACCESS +// located at mbedtls/library/ssl_misc.h +#include "ssl_misc.h" + #include "mbedtls/ssl.h" -#include "ssl_misc.h" // located at mbedtls/library/ssl_misc.h #include "mbedtls/platform.h" #include "esp_log.h" diff --git a/components/mbedtls/port/dynamic/esp_ssl_cli.c b/components/mbedtls/port/dynamic/esp_ssl_cli.c index 615525b271..46178bf654 100644 --- a/components/mbedtls/port/dynamic/esp_ssl_cli.c +++ b/components/mbedtls/port/dynamic/esp_ssl_cli.c @@ -8,8 +8,10 @@ #include "esp_mbedtls_dynamic_impl.h" int __real_mbedtls_ssl_handshake_client_step(mbedtls_ssl_context *ssl); +int __real_mbedtls_ssl_write_client_hello(mbedtls_ssl_context *ssl); int __wrap_mbedtls_ssl_handshake_client_step(mbedtls_ssl_context *ssl); +int __wrap_mbedtls_ssl_write_client_hello(mbedtls_ssl_context *ssl); static const char *TAG = "SSL client"; @@ -17,7 +19,7 @@ static int manage_resource(mbedtls_ssl_context *ssl, bool add) { int state = add ? ssl->MBEDTLS_PRIVATE(state) : ssl->MBEDTLS_PRIVATE(state) - 1; - if (ssl->MBEDTLS_PRIVATE(state) == MBEDTLS_SSL_HANDSHAKE_OVER || ssl->MBEDTLS_PRIVATE(handshake) == NULL) { + if (mbedtls_ssl_is_handshake_over(ssl) || ssl->MBEDTLS_PRIVATE(handshake) == NULL) { return 0; } @@ -27,6 +29,16 @@ static int manage_resource(mbedtls_ssl_context *ssl, bool add) } } + /* Change state now, so that it is right in mbedtls_ssl_read_record(), used + * by DTLS for dropping out-of-sequence ChangeCipherSpec records */ +#if defined(MBEDTLS_SSL_SESSION_TICKETS) + if( ssl->state == MBEDTLS_SSL_SERVER_CHANGE_CIPHER_SPEC && + ssl->handshake->new_session_ticket != 0 ) + { + ssl->state = MBEDTLS_SSL_SERVER_NEW_SESSION_TICKET; + } +#endif + switch (state) { case MBEDTLS_SSL_HELLO_REQUEST: break; @@ -91,7 +103,9 @@ static int manage_resource(mbedtls_ssl_context *ssl, bool add) case MBEDTLS_SSL_CLIENT_CERTIFICATE: if (add) { size_t buffer_len = 3; - mbedtls_ssl_key_cert *key_cert = ssl->MBEDTLS_PRIVATE(conf)->MBEDTLS_PRIVATE(key_cert); + + const mbedtls_ssl_config *conf = mbedtls_ssl_context_get_config(ssl); + mbedtls_ssl_key_cert *key_cert = conf->MBEDTLS_PRIVATE(key_cert); while (key_cert && key_cert->cert) { size_t num; @@ -189,3 +203,14 @@ int __wrap_mbedtls_ssl_handshake_client_step(mbedtls_ssl_context *ssl) return 0; } + +int __wrap_mbedtls_ssl_write_client_hello(mbedtls_ssl_context *ssl) +{ + CHECK_OK(manage_resource(ssl, true)); + + CHECK_OK(__real_mbedtls_ssl_write_client_hello(ssl)); + + CHECK_OK(manage_resource(ssl, false)); + + return 0; +} diff --git a/components/mbedtls/port/dynamic/esp_ssl_srv.c b/components/mbedtls/port/dynamic/esp_ssl_srv.c index 872807ff21..5a657b56c7 100644 --- a/components/mbedtls/port/dynamic/esp_ssl_srv.c +++ b/components/mbedtls/port/dynamic/esp_ssl_srv.c @@ -34,7 +34,7 @@ static int manage_resource(mbedtls_ssl_context *ssl, bool add) { int state = add ? ssl->MBEDTLS_PRIVATE(state) : ssl->MBEDTLS_PRIVATE(state) - 1; - if (ssl->MBEDTLS_PRIVATE(state) == MBEDTLS_SSL_HANDSHAKE_OVER || ssl->MBEDTLS_PRIVATE(handshake) == NULL) { + if (mbedtls_ssl_is_handshake_over(ssl) || ssl->MBEDTLS_PRIVATE(handshake) == NULL) { return 0; } @@ -46,7 +46,6 @@ static int manage_resource(mbedtls_ssl_context *ssl, bool add) switch (state) { case MBEDTLS_SSL_HELLO_REQUEST: - ssl->MBEDTLS_PRIVATE(major_ver) = MBEDTLS_SSL_MAJOR_VERSION_3; break; case MBEDTLS_SSL_CLIENT_HELLO: if (add) { @@ -67,7 +66,9 @@ static int manage_resource(mbedtls_ssl_context *ssl, bool add) case MBEDTLS_SSL_SERVER_CERTIFICATE: if (add) { size_t buffer_len = 3; - mbedtls_ssl_key_cert *key_cert = ssl->MBEDTLS_PRIVATE(conf)->MBEDTLS_PRIVATE(key_cert); + + const mbedtls_ssl_config *conf = mbedtls_ssl_context_get_config(ssl); + mbedtls_ssl_key_cert *key_cert = conf->MBEDTLS_PRIVATE(key_cert); while (key_cert && key_cert->cert) { size_t num; diff --git a/components/mbedtls/port/dynamic/esp_ssl_tls.c b/components/mbedtls/port/dynamic/esp_ssl_tls.c index 72cfc60f3a..21f8ca95e1 100644 --- a/components/mbedtls/port/dynamic/esp_ssl_tls.c +++ b/components/mbedtls/port/dynamic/esp_ssl_tls.c @@ -45,33 +45,18 @@ static int rx_done(mbedtls_ssl_context *ssl) static void ssl_update_checksum_start( mbedtls_ssl_context *ssl, const unsigned char *buf, size_t len ) { -#if defined(MBEDTLS_SSL_PROTO_SSL3) || defined(MBEDTLS_SSL_PROTO_TLS1) || \ - defined(MBEDTLS_SSL_PROTO_TLS1_1) - mbedtls_md5_update( &ssl->handshake->fin_md5 , buf, len ); - mbedtls_sha1_update( &ssl->handshake->fin_sha1, buf, len ); -#endif -#if defined(MBEDTLS_SSL_PROTO_TLS1_2) #if defined(MBEDTLS_SHA256_C) mbedtls_sha256_update( &ssl->handshake->fin_sha256, buf, len ); #endif #if defined(MBEDTLS_SHA512_C) mbedtls_sha512_update( &ssl->handshake->fin_sha512, buf, len ); #endif -#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ } static void ssl_handshake_params_init( mbedtls_ssl_handshake_params *handshake ) { memset( handshake, 0, sizeof( mbedtls_ssl_handshake_params ) ); -#if defined(MBEDTLS_SSL_PROTO_SSL3) || defined(MBEDTLS_SSL_PROTO_TLS1) || \ - defined(MBEDTLS_SSL_PROTO_TLS1_1) - mbedtls_md5_init( &handshake->fin_md5 ); - mbedtls_sha1_init( &handshake->fin_sha1 ); - mbedtls_md5_starts( &handshake->fin_md5 ); - mbedtls_sha1_starts( &handshake->fin_sha1 ); -#endif -#if defined(MBEDTLS_SSL_PROTO_TLS1_2) #if defined(MBEDTLS_SHA256_C) mbedtls_sha256_init( &handshake->fin_sha256 ); mbedtls_sha256_starts( &handshake->fin_sha256, 0 ); @@ -80,15 +65,9 @@ static void ssl_handshake_params_init( mbedtls_ssl_handshake_params *handshake ) mbedtls_sha512_init( &handshake->fin_sha512 ); mbedtls_sha512_starts( &handshake->fin_sha512, 1 ); #endif -#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ handshake->update_checksum = ssl_update_checksum_start; -#if defined(MBEDTLS_SSL_PROTO_TLS1_2) && \ - defined(MBEDTLS_KEY_EXCHANGE_WITH_CERT_ENABLED) - mbedtls_ssl_sig_hash_set_init( &handshake->hash_algs ); -#endif - #if defined(MBEDTLS_DHM_C) mbedtls_dhm_init( &handshake->dhm_ctx ); #endif @@ -145,6 +124,12 @@ static int ssl_handshake_init( mbedtls_ssl_context *ssl ) { ssl->handshake = mbedtls_calloc( 1, sizeof(mbedtls_ssl_handshake_params) ); } +#if defined(MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH) + /* If the buffers are too small - reallocate */ + + handle_buffer_resizing( ssl, 0, MBEDTLS_SSL_IN_BUFFER_LEN, + MBEDTLS_SSL_OUT_BUFFER_LEN ); +#endif /* All pointers should exist and can be directly freed without issue */ if( ssl->handshake == NULL || @@ -169,6 +154,120 @@ static int ssl_handshake_init( mbedtls_ssl_context *ssl ) mbedtls_ssl_transform_init( ssl->transform_negotiate ); ssl_handshake_params_init( ssl->handshake ); +/* + * curve_list is translated to IANA TLS group identifiers here because + * mbedtls_ssl_conf_curves returns void and so can't return + * any error codes. + */ +#if defined(MBEDTLS_ECP_C) +#if !defined(MBEDTLS_DEPRECATED_REMOVED) + /* Heap allocate and translate curve_list from internal to IANA group ids */ + if ( ssl->conf->curve_list != NULL ) + { + size_t length; + const mbedtls_ecp_group_id *curve_list = ssl->conf->curve_list; + + for( length = 0; ( curve_list[length] != MBEDTLS_ECP_DP_NONE ) && + ( length < MBEDTLS_ECP_DP_MAX ); length++ ) {} + + /* Leave room for zero termination */ + uint16_t *group_list = mbedtls_calloc( length + 1, sizeof(uint16_t) ); + if ( group_list == NULL ) + return( MBEDTLS_ERR_SSL_ALLOC_FAILED ); + + for( size_t i = 0; i < length; i++ ) + { + const mbedtls_ecp_curve_info *info = + mbedtls_ecp_curve_info_from_grp_id( curve_list[i] ); + if ( info == NULL ) + { + mbedtls_free( group_list ); + return( MBEDTLS_ERR_SSL_BAD_CONFIG ); + } + group_list[i] = info->tls_id; + } + + group_list[length] = 0; + + ssl->handshake->group_list = group_list; + ssl->handshake->group_list_heap_allocated = 1; + } + else + { + ssl->handshake->group_list = ssl->conf->group_list; + ssl->handshake->group_list_heap_allocated = 0; + } +#endif /* MBEDTLS_DEPRECATED_REMOVED */ +#endif /* MBEDTLS_ECP_C */ + +#if defined(MBEDTLS_KEY_EXCHANGE_WITH_CERT_ENABLED) +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +#if defined(MBEDTLS_SSL_PROTO_TLS1_2) + /* Heap allocate and translate sig_hashes from internal hash identifiers to + signature algorithms IANA identifiers. */ + if ( mbedtls_ssl_conf_is_tls12_only( ssl->conf ) && + ssl->conf->sig_hashes != NULL ) + { + const int *md; + const int *sig_hashes = ssl->conf->sig_hashes; + size_t sig_algs_len = 0; + uint16_t *p; + +#if defined(static_assert) + static_assert( MBEDTLS_SSL_MAX_SIG_ALG_LIST_LEN + <= ( SIZE_MAX - ( 2 * sizeof(uint16_t) ) ), + "MBEDTLS_SSL_MAX_SIG_ALG_LIST_LEN too big" ); +#endif + + for( md = sig_hashes; *md != MBEDTLS_MD_NONE; md++ ) + { + if( mbedtls_ssl_hash_from_md_alg( *md ) == MBEDTLS_SSL_HASH_NONE ) + continue; +#if defined(MBEDTLS_ECDSA_C) + sig_algs_len += sizeof( uint16_t ); +#endif + +#if defined(MBEDTLS_RSA_C) + sig_algs_len += sizeof( uint16_t ); +#endif + if( sig_algs_len > MBEDTLS_SSL_MAX_SIG_ALG_LIST_LEN ) + return( MBEDTLS_ERR_SSL_BAD_CONFIG ); + } + + if( sig_algs_len < MBEDTLS_SSL_MIN_SIG_ALG_LIST_LEN ) + return( MBEDTLS_ERR_SSL_BAD_CONFIG ); + + ssl->handshake->sig_algs = mbedtls_calloc( 1, sig_algs_len + + sizeof( uint16_t )); + if( ssl->handshake->sig_algs == NULL ) + return( MBEDTLS_ERR_SSL_ALLOC_FAILED ); + + p = (uint16_t *)ssl->handshake->sig_algs; + for( md = sig_hashes; *md != MBEDTLS_MD_NONE; md++ ) + { + unsigned char hash = mbedtls_ssl_hash_from_md_alg( *md ); + if( hash == MBEDTLS_SSL_HASH_NONE ) + continue; +#if defined(MBEDTLS_ECDSA_C) + *p = (( hash << 8 ) | MBEDTLS_SSL_SIG_ECDSA); + p++; +#endif +#if defined(MBEDTLS_RSA_C) + *p = (( hash << 8 ) | MBEDTLS_SSL_SIG_RSA); + p++; +#endif + } + *p = MBEDTLS_TLS_SIG_NONE; + ssl->handshake->sig_algs_heap_allocated = 1; + } + else +#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ + { + ssl->handshake->sig_algs_heap_allocated = 0; + } +#endif /* !MBEDTLS_DEPRECATED_REMOVED */ +#endif /* MBEDTLS_KEY_EXCHANGE_WITH_CERT_ENABLED */ + return( 0 ); } diff --git a/components/mbedtls/port/ecc/ecc_alt.c b/components/mbedtls/port/ecc/ecc_alt.c index 646df7f5d3..e78babc404 100644 --- a/components/mbedtls/port/ecc/ecc_alt.c +++ b/components/mbedtls/port/ecc/ecc_alt.c @@ -8,11 +8,6 @@ #include "soc/hwcrypto_periph.h" #include "ecc_impl.h" -/* TBD: Remove this and use proper getter/setter methods to access - * private members of EC data structures once they are available - * in mbedTLS stack */ -#define MBEDTLS_ALLOW_PRIVATE_ACCESS - #include "mbedtls/ecp.h" #include "mbedtls/platform_util.h" @@ -37,56 +32,41 @@ static int esp_mbedtls_ecp_point_multiply(const mbedtls_ecp_group *grp, mbedtls_ p_pt.len = grp->pbits / 8; - memcpy(&p_pt.x, P->X.p, mbedtls_mpi_size(&P->X)); - memcpy(&p_pt.y, P->Y.p, mbedtls_mpi_size(&P->Y)); + memcpy(&p_pt.x, P->MBEDTLS_PRIVATE(X).MBEDTLS_PRIVATE(p), mbedtls_mpi_size(&P->MBEDTLS_PRIVATE(X))); + memcpy(&p_pt.y, P->MBEDTLS_PRIVATE(Y).MBEDTLS_PRIVATE(p), mbedtls_mpi_size(&P->MBEDTLS_PRIVATE(Y))); - ret = esp_ecc_point_multiply(&p_pt, (uint8_t *)m->p, &r_pt, false); + ret = esp_ecc_point_multiply(&p_pt, (uint8_t *)m->MBEDTLS_PRIVATE(p), &r_pt, false); for (int i = 0; i < MAX_SIZE; i++) { x_tmp[MAX_SIZE - i - 1] = r_pt.x[i]; y_tmp[MAX_SIZE - i - 1] = r_pt.y[i]; } - mbedtls_mpi_read_binary(&R->X, x_tmp, MAX_SIZE); - mbedtls_mpi_read_binary(&R->Y, y_tmp, MAX_SIZE); - mbedtls_mpi_lset(&R->Z, 1); + mbedtls_mpi_read_binary(&R->MBEDTLS_PRIVATE(X), x_tmp, MAX_SIZE); + mbedtls_mpi_read_binary(&R->MBEDTLS_PRIVATE(Y), y_tmp, MAX_SIZE); + mbedtls_mpi_lset(&R->MBEDTLS_PRIVATE(Z), 1); return ret; } -/* - * Restartable multiplication R = m * P - */ -int mbedtls_ecp_mul_restartable( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, +int ecp_mul_restartable_internal( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, const mbedtls_mpi *m, const mbedtls_ecp_point *P, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, mbedtls_ecp_restart_ctx *rs_ctx ) { int ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; - if (grp->id != MBEDTLS_ECP_DP_SECP192R1 && grp->id != MBEDTLS_ECP_DP_SECP256R1) { #if defined(MBEDTLS_ECP_MUL_ALT_SOFT_FALLBACK) - return mbedtls_ecp_mul_restartable_soft(grp, R, m, P, f_rng, p_rng, rs_ctx); + return ecp_mul_restartable_internal_soft(grp, R, m, P, f_rng, p_rng, rs_ctx); #else return ret; #endif } - ECP_VALIDATE_RET( grp != NULL ); - ECP_VALIDATE_RET( R != NULL ); - ECP_VALIDATE_RET( m != NULL ); - ECP_VALIDATE_RET( P != NULL ); - /* Common sanity checks */ - MBEDTLS_MPI_CHK( mbedtls_ecp_check_privkey( grp, m ) ); - MBEDTLS_MPI_CHK( mbedtls_ecp_check_pubkey( grp, P ) ); - - ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; - /* MBEDTLS_MPI_CHK macro assigns the return value of the function to - * `ret` variable - */ MBEDTLS_MPI_CHK( esp_mbedtls_ecp_point_multiply(grp, R, m, P) ); cleanup: return( ret ); } + #endif /* defined(MBEDTLS_ECP_MUL_ALT) || defined(MBEDTLS_ECP_MUL_ALT_SOFT_FALLBACK) */ #if defined(MBEDTLS_ECP_VERIFY_ALT) || defined(MBEDTLS_ECP_VERIFY_ALT_SOFT_FALLBACK) @@ -109,13 +89,13 @@ int mbedtls_ecp_check_pubkey( const mbedtls_ecp_group *grp, ECP_VALIDATE_RET( pt != NULL ); /* Must use affine coordinates */ - if( mbedtls_mpi_cmp_int( &pt->Z, 1 ) != 0 ) + if( mbedtls_mpi_cmp_int( &pt->MBEDTLS_PRIVATE(Z), 1 ) != 0 ) return( MBEDTLS_ERR_ECP_INVALID_KEY ); mbedtls_platform_zeroize((void *)&point, sizeof(ecc_point_t)); - memcpy(&point.x, pt->X.p, mbedtls_mpi_size(&pt->X)); - memcpy(&point.y, pt->Y.p, mbedtls_mpi_size(&pt->Y)); + memcpy(&point.x, pt->MBEDTLS_PRIVATE(X).MBEDTLS_PRIVATE(p), mbedtls_mpi_size(&pt->MBEDTLS_PRIVATE(X))); + memcpy(&point.y, pt->MBEDTLS_PRIVATE(Y).MBEDTLS_PRIVATE(p), mbedtls_mpi_size(&pt->MBEDTLS_PRIVATE(Y))); point.len = grp->pbits / 8; diff --git a/components/mbedtls/port/esp_ds/esp_rsa_sign_alt.c b/components/mbedtls/port/esp_ds/esp_rsa_sign_alt.c index a6f9f0cde1..86e15b6950 100644 --- a/components/mbedtls/port/esp_ds/esp_rsa_sign_alt.c +++ b/components/mbedtls/port/esp_ds/esp_rsa_sign_alt.c @@ -6,6 +6,7 @@ #include "esp_ds.h" #include "rsa_sign_alt.h" +#include "esp_memory_utils.h" #ifdef CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/digital_signature.h" @@ -57,7 +58,7 @@ void esp_ds_set_session_timeout(int timeout) } } -esp_err_t esp_ds_init_data_ctx(esp_ds_data_ctx_t *ds_data) +esp_err_t esp_ds_init_data_ctx(esp_ds_data_ctx_t *ds_data) { if (ds_data == NULL || ds_data->esp_ds_data == NULL) { return ESP_ERR_INVALID_ARG; @@ -69,8 +70,22 @@ esp_err_t esp_ds_init_data_ctx(esp_ds_data_ctx_t *ds_data) } s_ds_data = ds_data->esp_ds_data; s_esp_ds_hmac_key_id = (hmac_key_id_t) ds_data->efuse_key_id; - /* calculate the rsa_length in terms of esp_digital_signature_length_t which is required for the internal DS API */ - s_ds_data->rsa_length = (ds_data->rsa_length_bits / 32) - 1; + + const unsigned rsa_length_int = (ds_data->rsa_length_bits / 32) - 1; + if (esp_ptr_byte_accessible(s_ds_data)) { + /* calculate the rsa_length in terms of esp_digital_signature_length_t which is required for the internal DS API */ + s_ds_data->rsa_length = rsa_length_int; + } else if (s_ds_data->rsa_length != rsa_length_int) { + /* + * Configuration data is most likely from DROM segment and it + * is not properly formatted for all parameters consideration. + * Moreover, we can not modify as it is read-only and hence + * the error. + */ + ESP_LOGE(TAG, "RSA length mismatch %u, %u", s_ds_data->rsa_length, rsa_length_int); + return ESP_ERR_INVALID_ARG; + } + return ESP_OK; } diff --git a/components/mbedtls/port/esp_timing.c b/components/mbedtls/port/esp_timing.c index d310f75772..96858f765a 100644 --- a/components/mbedtls/port/esp_timing.c +++ b/components/mbedtls/port/esp_timing.c @@ -83,4 +83,12 @@ int mbedtls_timing_get_delay( void *data ) return( 0 ); } +/* + * Get the final delay. + */ +uint32_t mbedtls_timing_get_final_delay( const mbedtls_timing_delay_context *data ) +{ + return( data->MBEDTLS_PRIVATE(fin_ms) ); +} + #endif /* MBEDTLS_ESP_TIMING_C */ diff --git a/components/mbedtls/port/include/mbedtls/ecp.h b/components/mbedtls/port/include/mbedtls/ecp.h index 7340615b86..28ccd5c79c 100644 --- a/components/mbedtls/port/include/mbedtls/ecp.h +++ b/components/mbedtls/port/include/mbedtls/ecp.h @@ -12,13 +12,18 @@ extern "C" { #endif -#if defined(MBEDTLS_ECP_MUL_ALT_SOFT_FALLBACK) - -int mbedtls_ecp_mul_restartable_soft(mbedtls_ecp_group *grp, mbedtls_ecp_point *R, +#if defined(MBEDTLS_ECP_MUL_ALT) || defined(MBEDTLS_ECP_MUL_ALT_SOFT_FALLBACK) +int ecp_mul_restartable_internal( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, const mbedtls_mpi *m, const mbedtls_ecp_point *P, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, mbedtls_ecp_restart_ctx *rs_ctx ); +#endif +#if defined(MBEDTLS_ECP_MUL_ALT_SOFT_FALLBACK) +int ecp_mul_restartable_internal_soft( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx ); #endif #if defined(MBEDTLS_ECP_VERIFY_ALT_SOFT_FALLBACK) diff --git a/components/mbedtls/test_apps/CMakeLists.txt b/components/mbedtls/test_apps/CMakeLists.txt new file mode 100644 index 0000000000..16481610bb --- /dev/null +++ b/components/mbedtls/test_apps/CMakeLists.txt @@ -0,0 +1,7 @@ +#This is the project CMakeLists.txt file for the test subproject +cmake_minimum_required(VERSION 3.16) + +set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components") + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(mbedtls_test) diff --git a/components/mbedtls/test_apps/README.md b/components/mbedtls/test_apps/README.md new file mode 100644 index 0000000000..b5be4985c5 --- /dev/null +++ b/components/mbedtls/test_apps/README.md @@ -0,0 +1,2 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | diff --git a/components/mbedtls/test/CMakeLists.txt b/components/mbedtls/test_apps/main/CMakeLists.txt similarity index 89% rename from components/mbedtls/test/CMakeLists.txt rename to components/mbedtls/test_apps/main/CMakeLists.txt index d51cbed59a..533724e2a6 100644 --- a/components/mbedtls/test/CMakeLists.txt +++ b/components/mbedtls/test_apps/main/CMakeLists.txt @@ -7,8 +7,9 @@ set(TEST_CRTS "crts/server_cert_chain.pem" idf_component_register(SRC_DIRS "." PRIV_INCLUDE_DIRS "." - PRIV_REQUIRES cmock test_utils mbedtls esp_timer - EMBED_TXTFILES ${TEST_CRTS}) + PRIV_REQUIRES cmock test_utils mbedtls esp_timer unity + EMBED_TXTFILES ${TEST_CRTS} + WHOLE_ARCHIVE) target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") idf_component_get_property(mbedtls mbedtls COMPONENT_LIB) diff --git a/components/mbedtls/test_apps/main/app_main.c b/components/mbedtls/test_apps/main/app_main.c new file mode 100644 index 0000000000..0716defabf --- /dev/null +++ b/components/mbedtls/test_apps/main/app_main.c @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "unity.h" +#include "memory_checks.h" + +/* setUp runs before every test */ +void setUp(void) +{ + test_utils_record_free_mem(); + test_utils_set_leak_level(CONFIG_UNITY_CRITICAL_LEAK_LEVEL_GENERAL, ESP_LEAK_TYPE_CRITICAL, ESP_COMP_LEAK_GENERAL); + test_utils_set_leak_level(CONFIG_UNITY_WARN_LEAK_LEVEL_GENERAL, ESP_LEAK_TYPE_WARNING, ESP_COMP_LEAK_GENERAL); + test_utils_set_leak_level(0, ESP_LEAK_TYPE_CRITICAL, ESP_COMP_LEAK_LWIP); +} + +/* tearDown runs after every test */ +void tearDown(void) +{ + /* some FreeRTOS stuff is cleaned up by idle task */ + vTaskDelay(5); + + /* clean up some of the newlib's lazy allocations */ + esp_reent_cleanup(); + + /* check if unit test has caused heap corruption in any heap */ + TEST_ASSERT_MESSAGE( heap_caps_check_integrity(MALLOC_CAP_INVALID, true), "The test has corrupted the heap"); + + test_utils_finish_and_evaluate_leaks(test_utils_get_leak_level(ESP_LEAK_TYPE_WARNING, ESP_COMP_LEAK_ALL), + test_utils_get_leak_level(ESP_LEAK_TYPE_CRITICAL, ESP_COMP_LEAK_ALL)); + +} + +static void test_task(void *pvParameters) +{ + vTaskDelay(2); /* Delay a bit to let the main task be deleted */ + unity_run_menu(); +} + +void app_main(void) +{ + xTaskCreatePinnedToCore(test_task, "testTask", CONFIG_UNITY_FREERTOS_STACK_SIZE, NULL, CONFIG_UNITY_FREERTOS_PRIORITY, NULL, CONFIG_UNITY_FREERTOS_CPU); +} diff --git a/components/mbedtls/test/crts/bad_md_crt.pem b/components/mbedtls/test_apps/main/crts/bad_md_crt.pem similarity index 100% rename from components/mbedtls/test/crts/bad_md_crt.pem rename to components/mbedtls/test_apps/main/crts/bad_md_crt.pem diff --git a/components/mbedtls/test/crts/correct_sig_crt_esp32_com.pem b/components/mbedtls/test_apps/main/crts/correct_sig_crt_esp32_com.pem similarity index 100% rename from components/mbedtls/test/crts/correct_sig_crt_esp32_com.pem rename to components/mbedtls/test_apps/main/crts/correct_sig_crt_esp32_com.pem diff --git a/components/mbedtls/test/crts/prvtkey.pem b/components/mbedtls/test_apps/main/crts/prvtkey.pem similarity index 100% rename from components/mbedtls/test/crts/prvtkey.pem rename to components/mbedtls/test_apps/main/crts/prvtkey.pem diff --git a/components/mbedtls/test/crts/server_cert_bundle b/components/mbedtls/test_apps/main/crts/server_cert_bundle similarity index 100% rename from components/mbedtls/test/crts/server_cert_bundle rename to components/mbedtls/test_apps/main/crts/server_cert_bundle diff --git a/components/mbedtls/test/crts/server_cert_chain.pem b/components/mbedtls/test_apps/main/crts/server_cert_chain.pem similarity index 100% rename from components/mbedtls/test/crts/server_cert_chain.pem rename to components/mbedtls/test_apps/main/crts/server_cert_chain.pem diff --git a/components/mbedtls/test/crts/server_root.pem b/components/mbedtls/test_apps/main/crts/server_root.pem similarity index 100% rename from components/mbedtls/test/crts/server_root.pem rename to components/mbedtls/test_apps/main/crts/server_root.pem diff --git a/components/mbedtls/test/crts/wrong_sig_crt_esp32_com.pem b/components/mbedtls/test_apps/main/crts/wrong_sig_crt_esp32_com.pem similarity index 100% rename from components/mbedtls/test/crts/wrong_sig_crt_esp32_com.pem rename to components/mbedtls/test_apps/main/crts/wrong_sig_crt_esp32_com.pem diff --git a/components/mbedtls/test/test_aes.c b/components/mbedtls/test_apps/main/test_aes.c similarity index 99% rename from components/mbedtls/test/test_aes.c rename to components/mbedtls/test_apps/main/test_aes.c index 4d5e4872d9..925e4a82f2 100644 --- a/components/mbedtls/test/test_aes.c +++ b/components/mbedtls/test_apps/main/test_aes.c @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ /* mbedTLS AES test */ #include diff --git a/components/mbedtls/test/test_aes_gcm.c b/components/mbedtls/test_apps/main/test_aes_gcm.c similarity index 100% rename from components/mbedtls/test/test_aes_gcm.c rename to components/mbedtls/test_apps/main/test_aes_gcm.c diff --git a/components/mbedtls/test/test_aes_perf.c b/components/mbedtls/test_apps/main/test_aes_perf.c similarity index 94% rename from components/mbedtls/test/test_aes_perf.c rename to components/mbedtls/test_apps/main/test_aes_perf.c index 00a6247bf4..6ba8f15c10 100644 --- a/components/mbedtls/test/test_aes_perf.c +++ b/components/mbedtls/test_apps/main/test_aes_perf.c @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ /* mbedTLS AES performance test */ #include diff --git a/components/mbedtls/test/test_aes_sha_parallel.c b/components/mbedtls/test_apps/main/test_aes_sha_parallel.c similarity index 100% rename from components/mbedtls/test/test_aes_sha_parallel.c rename to components/mbedtls/test_apps/main/test_aes_sha_parallel.c diff --git a/components/mbedtls/test/test_aes_sha_rsa.c b/components/mbedtls/test_apps/main/test_aes_sha_rsa.c similarity index 100% rename from components/mbedtls/test/test_aes_sha_rsa.c rename to components/mbedtls/test_apps/main/test_aes_sha_rsa.c diff --git a/components/mbedtls/test/test_apb_dport_access.c b/components/mbedtls/test_apps/main/test_apb_dport_access.c similarity index 90% rename from components/mbedtls/test/test_apb_dport_access.c rename to components/mbedtls/test_apps/main/test_apb_dport_access.c index 07203ac1ea..34cb956872 100644 --- a/components/mbedtls/test/test_apb_dport_access.c +++ b/components/mbedtls/test_apps/main/test_apb_dport_access.c @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ /* Implementation of utility functions to verify unit tests aren't performing SMP-unsafe DPORT reads. */ diff --git a/components/mbedtls/test/test_apb_dport_access.h b/components/mbedtls/test_apps/main/test_apb_dport_access.h similarity index 82% rename from components/mbedtls/test/test_apb_dport_access.h rename to components/mbedtls/test_apps/main/test_apb_dport_access.h index 8f30e0465a..3231d745e2 100644 --- a/components/mbedtls/test/test_apb_dport_access.h +++ b/components/mbedtls/test_apps/main/test_apb_dport_access.h @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ /* Utility functions to test that APB access is still safe while the other CPU performs some set of DPORT accesses diff --git a/components/mbedtls/test/test_ecp.c b/components/mbedtls/test_apps/main/test_ecp.c similarity index 82% rename from components/mbedtls/test/test_ecp.c rename to components/mbedtls/test_apps/main/test_ecp.c index 44a58e92cd..ce86dc97b5 100644 --- a/components/mbedtls/test/test_ecp.c +++ b/components/mbedtls/test_apps/main/test_ecp.c @@ -12,13 +12,6 @@ #include #include -/* ToDo - Remove this once appropriate solution is available. -We need to define this for the file as ssl_misc.h uses private structures from mbedtls, -which are undefined if the following flag is not defined */ -/* Many APIs in the file make use of this flag instead of `MBEDTLS_PRIVATE` */ -/* ToDo - Replace them with proper getter-setter once they are added */ -#define MBEDTLS_ALLOW_PRIVATE_ACCESS - #include #include #include @@ -31,6 +24,20 @@ which are undefined if the following flag is not defined */ error hex value (mbedTLS uses -N for error codes) */ #define TEST_ASSERT_MBEDTLS_OK(X) TEST_ASSERT_EQUAL_HEX32(0, -(X)) +/* TODO: Currently MBEDTLS_ECDH_LEGACY_CONTEXT is enabled by default + * when MBEDTLS_ECP_RESTARTABLE is enabled. + * This is a temporary workaround to allow that. + * + * The legacy option is soon going to be removed in future mbedtls + * versions and this workaround will be removed once the appropriate + * solution is available. + */ +#ifdef CONFIG_MBEDTLS_ECDH_LEGACY_CONTEXT +#define ACCESS_ECDH(S, var) S.MBEDTLS_PRIVATE(var) +#else +#define ACCESS_ECDH(S, var) S.MBEDTLS_PRIVATE(ctx).MBEDTLS_PRIVATE(mbed_ecdh).MBEDTLS_PRIVATE(var) +#endif + TEST_CASE("mbedtls ECDH Generate Key", "[mbedtls]") { mbedtls_ecdh_context ctx; @@ -43,9 +50,9 @@ TEST_CASE("mbedtls ECDH Generate Key", "[mbedtls]") mbedtls_entropy_init(&entropy); TEST_ASSERT_MBEDTLS_OK( mbedtls_ctr_drbg_seed(&ctr_drbg, mbedtls_entropy_func, &entropy, NULL, 0) ); - TEST_ASSERT_MBEDTLS_OK( mbedtls_ecp_group_load(&ctx.ctx.mbed_ecdh.grp, MBEDTLS_ECP_DP_CURVE25519) ); + TEST_ASSERT_MBEDTLS_OK( mbedtls_ecp_group_load(ACCESS_ECDH(&ctx, grp), MBEDTLS_ECP_DP_CURVE25519) ); - TEST_ASSERT_MBEDTLS_OK( mbedtls_ecdh_gen_public(&ctx.ctx.mbed_ecdh.grp, &ctx.ctx.mbed_ecdh.d, &ctx.ctx.mbed_ecdh.Q, + TEST_ASSERT_MBEDTLS_OK( mbedtls_ecdh_gen_public(ACCESS_ECDH(&ctx, grp), ACCESS_ECDH(&ctx, d), ACCESS_ECDH(&ctx, Q), mbedtls_ctr_drbg_random, &ctr_drbg ) ); mbedtls_ecdh_free(&ctx); @@ -77,7 +84,8 @@ TEST_CASE("mbedtls ECP mul w/ koblitz", "[mbedtls]") mbedtls_ctr_drbg_random, &ctxRandom) ); - TEST_ASSERT_MBEDTLS_OK(mbedtls_ecp_mul(&ctxECDSA.grp, &ctxECDSA.Q, &ctxECDSA.d, &ctxECDSA.grp.G, + TEST_ASSERT_MBEDTLS_OK(mbedtls_ecp_mul(&ctxECDSA.MBEDTLS_PRIVATE(grp), &ctxECDSA.MBEDTLS_PRIVATE(Q), + &ctxECDSA.MBEDTLS_PRIVATE(d), &ctxECDSA.MBEDTLS_PRIVATE(grp).G, mbedtls_ctr_drbg_random, &ctxRandom) ); mbedtls_ecdsa_free(&ctxECDSA); @@ -184,20 +192,20 @@ static void test_ecp_mul(mbedtls_ecp_group_id id, const uint8_t *x_coord, const mbedtls_mpi_read_binary(&m, scalar, size); - mbedtls_mpi_read_binary(&P.X, x_coord, size); - mbedtls_mpi_read_binary(&P.Y, y_coord, size); + mbedtls_mpi_read_binary(&P.MBEDTLS_PRIVATE(X), x_coord, size); + mbedtls_mpi_read_binary(&P.MBEDTLS_PRIVATE(Y), y_coord, size); - mbedtls_mpi_lset(&P.Z, 1); + mbedtls_mpi_lset(&P.MBEDTLS_PRIVATE(Z), 1); ret = mbedtls_ecp_mul(&grp, &R, &m, &P, rng_wrapper, NULL); TEST_ASSERT_EQUAL(0, ret); - mbedtls_mpi_write_binary(&R.X, x, mbedtls_mpi_size(&R.X)); - mbedtls_mpi_write_binary(&R.Y, y, mbedtls_mpi_size(&R.Y)); + mbedtls_mpi_write_binary(&R.MBEDTLS_PRIVATE(X), x, mbedtls_mpi_size(&R.MBEDTLS_PRIVATE(X))); + mbedtls_mpi_write_binary(&R.MBEDTLS_PRIVATE(Y), y, mbedtls_mpi_size(&R.MBEDTLS_PRIVATE(Y))); - TEST_ASSERT_EQUAL(0, memcmp(x, result_x_coord, mbedtls_mpi_size(&R.X))); - TEST_ASSERT_EQUAL(0, memcmp(y, result_y_coord, mbedtls_mpi_size(&R.Y))); + TEST_ASSERT_EQUAL(0, memcmp(x, result_x_coord, mbedtls_mpi_size(&R.MBEDTLS_PRIVATE(X)))); + TEST_ASSERT_EQUAL(0, memcmp(y, result_y_coord, mbedtls_mpi_size(&R.MBEDTLS_PRIVATE(Y)))); mbedtls_ecp_point_free(&R); mbedtls_ecp_point_free(&P); @@ -232,9 +240,9 @@ static void test_ecp_verify(mbedtls_ecp_group_id id, const uint8_t *x_coord, con size = grp.pbits / 8; - mbedtls_mpi_read_binary(&P.X, x_coord, size); - mbedtls_mpi_read_binary(&P.Y, y_coord, size); - mbedtls_mpi_lset(&P.Z, 1); + mbedtls_mpi_read_binary(&P.MBEDTLS_PRIVATE(X), x_coord, size); + mbedtls_mpi_read_binary(&P.MBEDTLS_PRIVATE(Y), y_coord, size); + mbedtls_mpi_lset(&P.MBEDTLS_PRIVATE(Z), 1); ret = mbedtls_ecp_check_pubkey(&grp, &P); diff --git a/components/mbedtls/test/test_esp_crt_bundle.c b/components/mbedtls/test_apps/main/test_esp_crt_bundle.c similarity index 83% rename from components/mbedtls/test/test_esp_crt_bundle.c rename to components/mbedtls/test_apps/main/test_esp_crt_bundle.c index 1c0e3e57a2..1080863105 100644 --- a/components/mbedtls/test/test_esp_crt_bundle.c +++ b/components/mbedtls/test_apps/main/test_esp_crt_bundle.c @@ -29,6 +29,7 @@ #include "unity.h" #include "test_utils.h" +#include "unity_test_utils.h" #define SERVER_ADDRESS "localhost" #define SERVER_PORT "4433" @@ -51,6 +52,7 @@ extern const uint8_t wrong_sig_crt_pem_end[] asm("_binary_wrong_sig_crt_esp32_ extern const uint8_t correct_sig_crt_pem_start[] asm("_binary_correct_sig_crt_esp32_com_pem_start"); extern const uint8_t correct_sig_crt_pem_end[] asm("_binary_correct_sig_crt_esp32_com_pem_end"); +#define SEM_TIMEOUT 10000 typedef struct { mbedtls_ssl_context ssl; mbedtls_net_context listen_fd; @@ -187,7 +189,7 @@ void server_task(void *pvParameters) exit: endpoint_teardown(&server); xSemaphoreGive(*sema); - vTaskDelete(NULL); + vTaskSuspend(NULL); } @@ -250,25 +252,58 @@ esp_err_t client_setup(mbedtls_endpoint_t *client) return ESP_OK; } -int client_task(const uint8_t *bundle, size_t bundle_size, esp_crt_validate_res_t *res) +void client_task(void *pvParameters) { + SemaphoreHandle_t *client_signal_sem = (SemaphoreHandle_t *) pvParameters; int ret = ESP_FAIL; mbedtls_endpoint_t client; - - *res = ESP_CRT_VALIDATE_UNKNOWN; + esp_crt_validate_res_t res = ESP_CRT_VALIDATE_UNKNOWN; if (client_setup(&client) != ESP_OK) { ESP_LOGE(TAG, "SSL client setup failed"); goto exit; } - esp_crt_bundle_attach(&client.conf); - if (bundle) { - /* Set a bundle different from the menuconfig bundle */ - esp_crt_bundle_set(bundle, bundle_size); + /* Test with default crt bundle that doesnt contain the ca crt */ + ESP_LOGI(TAG, "Connecting to %s:%s...", SERVER_ADDRESS, SERVER_PORT); + if ((ret = mbedtls_net_connect(&client.client_fd, SERVER_ADDRESS, SERVER_PORT, MBEDTLS_NET_PROTO_TCP)) != 0) { + ESP_LOGE(TAG, "mbedtls_net_connect returned -%x", -ret); + goto exit; } + ESP_LOGI(TAG, "Connected."); + mbedtls_ssl_set_bio(&client.ssl, &client.client_fd, mbedtls_net_send, mbedtls_net_recv, NULL); + + ESP_LOGI(TAG, "Performing the SSL/TLS handshake with bundle that is missing the server root certificate"); + while ( ( ret = mbedtls_ssl_handshake( &client.ssl ) ) != 0 ) { + if ( ret != MBEDTLS_ERR_SSL_WANT_READ && ret != MBEDTLS_ERR_SSL_WANT_WRITE ) { + printf( "mbedtls_ssl_handshake failed with -0x%x\n", -ret ); + break; + } + } + + ESP_LOGI(TAG, "Verifying peer X.509 certificate for bundle ..."); + ret = mbedtls_ssl_get_verify_result(&client.ssl); + + res = (ret == 0) ? ESP_CRT_VALIDATE_OK : ESP_CRT_VALIDATE_FAIL; + + if (res == ESP_CRT_VALIDATE_OK) { + ESP_LOGI(TAG, "Certificate verification passed!"); + } else { + ESP_LOGE(TAG, "Certificate verification failed!"); + } + TEST_ASSERT(res == ESP_CRT_VALIDATE_FAIL); + + // Reset session before new connection + mbedtls_ssl_close_notify(&client.ssl); + mbedtls_ssl_session_reset(&client.ssl); + mbedtls_net_free( &client.client_fd); + + /* Test with bundle that does contain the CA crt */ + esp_crt_bundle_attach(&client.conf); + esp_crt_bundle_set(server_cert_bundle_start, server_cert_bundle_end - server_cert_bundle_start); + ESP_LOGI(TAG, "Connecting to %s:%s...", SERVER_ADDRESS, SERVER_PORT); if ((ret = mbedtls_net_connect(&client.client_fd, SERVER_ADDRESS, SERVER_PORT, MBEDTLS_NET_PROTO_TCP)) != 0) { ESP_LOGE(TAG, "mbedtls_net_connect returned -%x", -ret); @@ -289,14 +324,14 @@ int client_task(const uint8_t *bundle, size_t bundle_size, esp_crt_validate_res_ ESP_LOGI(TAG, "Verifying peer X.509 certificate for bundle ..."); ret = mbedtls_ssl_get_verify_result(&client.ssl); - *res = (ret == 0) ? ESP_CRT_VALIDATE_OK : ESP_CRT_VALIDATE_FAIL; + res = (ret == 0) ? ESP_CRT_VALIDATE_OK : ESP_CRT_VALIDATE_FAIL; - if (*res == ESP_CRT_VALIDATE_OK) { + if (res == ESP_CRT_VALIDATE_OK) { ESP_LOGI(TAG, "Certificate verification passed!"); } else { ESP_LOGE(TAG, "Certificate verification failed!"); } - + TEST_ASSERT(res == ESP_CRT_VALIDATE_OK); // Reset session before new connection mbedtls_ssl_close_notify(&client.ssl); @@ -309,42 +344,45 @@ exit: mbedtls_ssl_session_reset(&client.ssl); esp_crt_bundle_detach(&client.conf); endpoint_teardown(&client); - - return ret; + xSemaphoreGive(*client_signal_sem); + vTaskSuspend(NULL); } TEST_CASE("custom certificate bundle", "[mbedtls]") { - esp_crt_validate_res_t validate_res; - test_case_uses_tcpip(); SemaphoreHandle_t signal_sem = xSemaphoreCreateBinary(); TEST_ASSERT_NOT_NULL(signal_sem); exit_flag = false; - xTaskCreate(server_task, "server task", 8192, &signal_sem, 10, NULL); + TaskHandle_t server_task_handle; + xTaskCreate(server_task, "server task", 8192, &signal_sem, 10, &server_task_handle); // Wait for the server to start up - if (!xSemaphoreTake(signal_sem, 10000 / portTICK_PERIOD_MS)) { + if (!xSemaphoreTake(signal_sem, SEM_TIMEOUT / portTICK_PERIOD_MS)) { TEST_FAIL_MESSAGE("signal_sem not released, server start failed"); } - /* Test with default crt bundle that doesnt contain the ca crt */ - client_task(NULL, 0, &validate_res); - TEST_ASSERT(validate_res == ESP_CRT_VALIDATE_FAIL); + SemaphoreHandle_t client_signal_sem = xSemaphoreCreateBinary(); + TEST_ASSERT_NOT_NULL(client_signal_sem); - /* Test with bundle that does contain the CA crt */ - client_task(server_cert_bundle_start, server_cert_bundle_end - server_cert_bundle_start, &validate_res); - TEST_ASSERT(validate_res == ESP_CRT_VALIDATE_OK); + TaskHandle_t client_task_handle; + xTaskCreate(client_task, "client task", 8192, &client_signal_sem, 10, &client_task_handle); + + if (!xSemaphoreTake(client_signal_sem, SEM_TIMEOUT / portTICK_PERIOD_MS)) { + TEST_FAIL_MESSAGE("client_signal_sem not released, client exit failed"); + } + unity_utils_task_delete(client_task_handle); exit_flag = true; - if (!xSemaphoreTake(signal_sem, 10000 / portTICK_PERIOD_MS)) { + if (!xSemaphoreTake(signal_sem, SEM_TIMEOUT / portTICK_PERIOD_MS)) { TEST_FAIL_MESSAGE("signal_sem not released, server exit failed"); } - + unity_utils_task_delete(server_task_handle); + vSemaphoreDelete(client_signal_sem); vSemaphoreDelete(signal_sem); } diff --git a/components/mbedtls/test/test_mbedtls.c b/components/mbedtls/test_apps/main/test_mbedtls.c similarity index 90% rename from components/mbedtls/test/test_mbedtls.c rename to components/mbedtls/test_apps/main/test_mbedtls.c index 70eeac5b6b..a35ba2140b 100644 --- a/components/mbedtls/test/test_mbedtls.c +++ b/components/mbedtls/test_apps/main/test_mbedtls.c @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ /* mbedTLS self-tests as unit tests Focus on testing functionality where we use ESP32 hardware diff --git a/components/mbedtls/test/test_mbedtls_mpi.c b/components/mbedtls/test_apps/main/test_mbedtls_mpi.c similarity index 100% rename from components/mbedtls/test/test_mbedtls_mpi.c rename to components/mbedtls/test_apps/main/test_mbedtls_mpi.c diff --git a/components/mbedtls/test/test_mbedtls_sha.c b/components/mbedtls/test_apps/main/test_mbedtls_sha.c similarity index 100% rename from components/mbedtls/test/test_mbedtls_sha.c rename to components/mbedtls/test_apps/main/test_mbedtls_sha.c diff --git a/components/mbedtls/test/test_mbedtls_utils.c b/components/mbedtls/test_apps/main/test_mbedtls_utils.c similarity index 100% rename from components/mbedtls/test/test_mbedtls_utils.c rename to components/mbedtls/test_apps/main/test_mbedtls_utils.c diff --git a/components/mbedtls/test/test_mbedtls_utils.h b/components/mbedtls/test_apps/main/test_mbedtls_utils.h similarity index 100% rename from components/mbedtls/test/test_mbedtls_utils.h rename to components/mbedtls/test_apps/main/test_mbedtls_utils.h diff --git a/components/mbedtls/test/test_rsa.c b/components/mbedtls/test_apps/main/test_rsa.c similarity index 96% rename from components/mbedtls/test/test_rsa.c rename to components/mbedtls/test_apps/main/test_rsa.c index 9f85458f2c..f69a0238f8 100644 --- a/components/mbedtls/test/test_rsa.c +++ b/components/mbedtls/test_apps/main/test_rsa.c @@ -20,6 +20,7 @@ #include "freertos/FreeRTOS.h" #include "unity.h" #include "test_utils.h" +#include "memory_checks.h" #include "ccomp_timer.h" #define PRINT_DEBUG_INFO @@ -423,23 +424,24 @@ static void print_rsa_details(mbedtls_rsa_context *rsa) } #endif -/** NOTE: -* For ESP32-S3, CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG is enabled -* by default; allocating a lock of 92 bytes, which is never freed. -* -* MR !18574 adds the MPI crypto lock for S3 increasing the leakage by -* 92 bytes. This caused the RSA UT to fail with a leakage more than -* 1024 bytes. -* -* The allocations made by ESP32-S2 (944 bytes) and ESP32-S3 are the same, -* except for the JTAG lock (92 + 944 > 1024). -*/ #if CONFIG_FREERTOS_SMP // IDF-5260 -TEST_CASE("test performance RSA key operations", "[bignum][leaks=1088][timeout=60]") +TEST_CASE("test performance RSA key operations", "[bignum][timeout=60]") #else -TEST_CASE("test performance RSA key operations", "[bignum][leaks=1088]") +TEST_CASE("test performance RSA key operations", "[bignum]") #endif { + /** NOTE: + * For ESP32-S3, CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG is enabled + * by default; allocating a lock of 92 bytes, which is never freed. + * + * MR !18574 adds the MPI crypto lock for S3 increasing the leakage by + * 92 bytes. This caused the RSA UT to fail with a leakage more than + * 1024 bytes. + * + * The allocations made by ESP32-S2 (944 bytes) and ESP32-S3 are the same, + * except for the JTAG lock (92 + 944 > 1024). + */ + TEST_ESP_OK(test_utils_set_leak_level(1088, ESP_LEAK_TYPE_CRITICAL, ESP_COMP_LEAK_GENERAL)); for (int keysize = 2048; keysize <= SOC_RSA_MAX_BIT_LEN; keysize += 1024) { rsa_key_operations(keysize, true, false); } @@ -570,7 +572,7 @@ TEST_CASE("mbedtls RSA Generate Key", "[mbedtls][timeout=60]") const unsigned int key_size = 2048; const int exponent = 65537; -#if CONFIG_MBEDTLS_MPI_USE_INTERRUPT +#if CONFIG_MBEDTLS_MPI_USE_INTERRUPT && CONFIG_ESP_TASK_WDT_EN && !CONFIG_ESP_TASK_WDT_INIT /* Check that generating keys doesnt starve the watchdog if interrupt-based driver is used */ esp_task_wdt_config_t twdt_config = { .timeout_ms = 1000, @@ -578,7 +580,7 @@ TEST_CASE("mbedtls RSA Generate Key", "[mbedtls][timeout=60]") .trigger_panic = true, }; TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_init(&twdt_config)); -#endif //CONFIG_MBEDTLS_MPI_USE_INTERRUPT +#endif // CONFIG_MBEDTLS_MPI_USE_INTERRUPT && CONFIG_ESP_TASK_WDT_EN && !CONFIG_ESP_TASK_WDT_INIT mbedtls_rsa_init(&ctx); mbedtls_ctr_drbg_init(&ctr_drbg); @@ -592,9 +594,9 @@ TEST_CASE("mbedtls RSA Generate Key", "[mbedtls][timeout=60]") mbedtls_ctr_drbg_free(&ctr_drbg); mbedtls_entropy_free(&entropy); -#if CONFIG_MBEDTLS_MPI_USE_INTERRUPT +#if CONFIG_MBEDTLS_MPI_USE_INTERRUPT && CONFIG_ESP_TASK_WDT_EN && !CONFIG_ESP_TASK_WDT_INIT TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_deinit()); -#endif //CONFIG_MBEDTLS_MPI_USE_INTERRUPT +#endif // CONFIG_MBEDTLS_MPI_USE_INTERRUPT && CONFIG_ESP_TASK_WDT_EN && !CONFIG_ESP_TASK_WDT_INIT } diff --git a/components/mbedtls/test/test_sha.c b/components/mbedtls/test_apps/main/test_sha.c similarity index 100% rename from components/mbedtls/test/test_sha.c rename to components/mbedtls/test_apps/main/test_sha.c diff --git a/components/mbedtls/test/test_sha_perf.c b/components/mbedtls/test_apps/main/test_sha_perf.c similarity index 100% rename from components/mbedtls/test/test_sha_perf.c rename to components/mbedtls/test_apps/main/test_sha_perf.c diff --git a/components/mbedtls/test_apps/pytest_mbedtls_ut.py b/components/mbedtls/test_apps/pytest_mbedtls_ut.py new file mode 100644 index 0000000000..43dd24d909 --- /dev/null +++ b/components/mbedtls/test_apps/pytest_mbedtls_ut.py @@ -0,0 +1,64 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +import pytest +from pytest_embedded import Dut + + +@pytest.mark.supported_targets +@pytest.mark.generic +def test_mbedtls(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('*') + dut.expect_unity_test_output(timeout=120) + + +@pytest.mark.esp32 +@pytest.mark.esp32s2 +@pytest.mark.esp32s3 +@pytest.mark.esp32c3 +@pytest.mark.generic +@pytest.mark.parametrize( + 'config', + [ + 'aes_no_hw', + ], + indirect=True, +) +def test_mbedtls_aes_no_hw(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('*') + dut.expect_unity_test_output(timeout=120) + + +@pytest.mark.esp32 +@pytest.mark.esp32s2 +@pytest.mark.esp32s3 +@pytest.mark.generic +@pytest.mark.parametrize( + 'config', + [ + 'psram', + ], + indirect=True, +) +def test_mbedtls_psram(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('*') + dut.expect_unity_test_output(timeout=120) + + +@pytest.mark.esp32 +@pytest.mark.generic +@pytest.mark.parametrize( + 'config', + [ + 'psram_esp32', + 'psram_all_ext', + ], + indirect=True, +) +def test_mbedtls_psram_esp32(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('*') + dut.expect_unity_test_output(timeout=120) diff --git a/components/mbedtls/test_apps/sdkconfig.ci.aes_no_hw b/components/mbedtls/test_apps/sdkconfig.ci.aes_no_hw new file mode 100644 index 0000000000..aadb89a893 --- /dev/null +++ b/components/mbedtls/test_apps/sdkconfig.ci.aes_no_hw @@ -0,0 +1,2 @@ +CONFIG_MBEDTLS_HARDWARE_AES=n +CONFIG_MBEDTLS_MPI_USE_INTERRUPT=n diff --git a/components/mbedtls/test_apps/sdkconfig.ci.default b/components/mbedtls/test_apps/sdkconfig.ci.default new file mode 100644 index 0000000000..e69de29bb2 diff --git a/components/mbedtls/test_apps/sdkconfig.ci.psram b/components/mbedtls/test_apps/sdkconfig.ci.psram new file mode 100644 index 0000000000..cc641ea603 --- /dev/null +++ b/components/mbedtls/test_apps/sdkconfig.ci.psram @@ -0,0 +1 @@ +CONFIG_SPIRAM=y diff --git a/components/mbedtls/test_apps/sdkconfig.ci.psram_all_ext b/components/mbedtls/test_apps/sdkconfig.ci.psram_all_ext new file mode 100644 index 0000000000..ad3452cf7b --- /dev/null +++ b/components/mbedtls/test_apps/sdkconfig.ci.psram_all_ext @@ -0,0 +1,4 @@ +CONFIG_SPIRAM=y +CONFIG_ESP_INT_WDT_TIMEOUT_MS=800 +CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y +CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=0 diff --git a/components/mbedtls/test_apps/sdkconfig.ci.psram_esp32 b/components/mbedtls/test_apps/sdkconfig.ci.psram_esp32 new file mode 100644 index 0000000000..5acbcfd7fc --- /dev/null +++ b/components/mbedtls/test_apps/sdkconfig.ci.psram_esp32 @@ -0,0 +1,3 @@ +CONFIG_SPIRAM=y +CONFIG_ESP_INT_WDT_TIMEOUT_MS=800 +CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y diff --git a/components/mbedtls/test_apps/sdkconfig.defaults b/components/mbedtls/test_apps/sdkconfig.defaults new file mode 100644 index 0000000000..ec826a5a16 --- /dev/null +++ b/components/mbedtls/test_apps/sdkconfig.defaults @@ -0,0 +1,9 @@ +# General options for additional checks +CONFIG_HEAP_POISONING_COMPREHENSIVE=y +CONFIG_COMPILER_WARN_WRITE_STRINGS=y +CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y +CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y +CONFIG_COMPILER_STACK_CHECK_MODE_STRONG=y +CONFIG_COMPILER_STACK_CHECK=y + +CONFIG_ESP_TASK_WDT=n diff --git a/components/mbedtls/test_apps/sdkconfig.defaults.esp32 b/components/mbedtls/test_apps/sdkconfig.defaults.esp32 new file mode 100644 index 0000000000..59093635f0 --- /dev/null +++ b/components/mbedtls/test_apps/sdkconfig.defaults.esp32 @@ -0,0 +1,3 @@ +CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y +CONFIG_XTAL_FREQ_AUTO=y +CONFIG_SPI_FLASH_SHARE_SPI1_BUS=y diff --git a/components/mbedtls/test_apps/sdkconfig.defaults.esp32c2 b/components/mbedtls/test_apps/sdkconfig.defaults.esp32c2 new file mode 100644 index 0000000000..bb33cff20a --- /dev/null +++ b/components/mbedtls/test_apps/sdkconfig.defaults.esp32c2 @@ -0,0 +1,2 @@ +CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=n +CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y diff --git a/components/mbedtls/test_apps/sdkconfig.defaults.esp32c3 b/components/mbedtls/test_apps/sdkconfig.defaults.esp32c3 new file mode 100644 index 0000000000..d0ea27a6c6 --- /dev/null +++ b/components/mbedtls/test_apps/sdkconfig.defaults.esp32c3 @@ -0,0 +1 @@ +CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=n diff --git a/components/mbedtls/test_apps/sdkconfig.defaults.esp32s2 b/components/mbedtls/test_apps/sdkconfig.defaults.esp32s2 new file mode 100644 index 0000000000..da22be442b --- /dev/null +++ b/components/mbedtls/test_apps/sdkconfig.defaults.esp32s2 @@ -0,0 +1,2 @@ +CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y +CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=n diff --git a/components/mbedtls/test_apps/sdkconfig.defaults.esp32s3 b/components/mbedtls/test_apps/sdkconfig.defaults.esp32s3 new file mode 100644 index 0000000000..da22be442b --- /dev/null +++ b/components/mbedtls/test_apps/sdkconfig.defaults.esp32s3 @@ -0,0 +1,2 @@ +CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y +CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=n diff --git a/components/mqtt/CMakeLists.txt b/components/mqtt/CMakeLists.txt index 15aea3d745..29aa3497d5 100644 --- a/components/mqtt/CMakeLists.txt +++ b/components/mqtt/CMakeLists.txt @@ -7,122 +7,7 @@ endif() idf_component_register(SRCS "${srcs}" INCLUDE_DIRS esp-mqtt/include PRIV_INCLUDE_DIRS "esp-mqtt/lib/include" - PRIV_REQUIRES esp_timer + REQUIRES esp_event tcp_transport + PRIV_REQUIRES esp_timer http_parser esp_hw_support ) target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") - -if(TEST_BUILD) -message(STATUS "building MOCKS") -idf_component_get_property(tcp_transport_dir tcp_transport COMPONENT_DIR) -idf_component_get_property(esp_hw_support_dir esp_hw_support COMPONENT_DIR) -idf_component_get_property(esp_event_dir esp_event COMPONENT_DIR) -idf_component_get_property(log_dir log COMPONENT_DIR) -idf_component_get_property(freertos_dir freertos COMPONENT_OVERRIDEN_DIR) -idf_component_get_property(http_parser_dir http_parser COMPONENT_DIR) -idf_component_get_property(esp_wifi_dir esp_wifi COMPONENT_DIR) -idf_component_get_property(esp_tls_dir esp-tls COMPONENT_DIR) -idf_component_get_property(esp_netif_dir esp_netif COMPONENT_DIR) -idf_component_get_property(esp_common_dir esp_common COMPONENT_DIR) -idf_component_get_property(esp_rom_dir esp_rom COMPONENT_DIR) -idf_component_get_property(esp_system_dir esp_system COMPONENT_DIR) -idf_component_get_property(mbedtls_dir mbedtls COMPONENT_DIR) - - idf_component_get_property(cmock_lib cmock COMPONENT_LIB) - set(IDF_PATH $ENV{IDF_PATH}) - set(CMOCK_DIR "${IDF_PATH}/components/cmock/CMock") - set(MOCK_GEN_DIR "${CMAKE_CURRENT_BINARY_DIR}/mocks") - set(ENV{UNITY_DIR} "$ENV{IDF_PATH}/components/cmock/CMock") - file(MAKE_DIRECTORY ${MOCK_GEN_DIR}) - - set(MOCK_OUTPUT - "${MOCK_GEN_DIR}/Mockesp_transport.c" "${MOCK_GEN_DIR}/Mockesp_transport.h" - "${MOCK_GEN_DIR}/Mockesp_transport_ssl.c" "${MOCK_GEN_DIR}/Mockesp_transport_ssl.h" - "${MOCK_GEN_DIR}/Mockesp_transport_ws.c" "${MOCK_GEN_DIR}/Mockesp_transport_ws.h" - "${MOCK_GEN_DIR}/Mockesp_transport_tcp.c" "${MOCK_GEN_DIR}/Mockesp_transport_tcp.h" - "${MOCK_GEN_DIR}/Mockesp_event.c" "${MOCK_GEN_DIR}/Mockesp_event.h" - "${MOCK_GEN_DIR}/Mockesp_mac.c" "${MOCK_GEN_DIR}/Mockesp_mac.h" - "${MOCK_GEN_DIR}/Mockesp_random.c" "${MOCK_GEN_DIR}/Mockesp_random.h" - "${MOCK_GEN_DIR}/Mockesp_system.c" "${MOCK_GEN_DIR}/Mockesp_system.h" - "${MOCK_GEN_DIR}/Mockesp_tls.c" "${MOCK_GEN_DIR}/Mockesp_tls.h" - "${MOCK_GEN_DIR}/Mockevent_groups.c" "${MOCK_GEN_DIR}/Mockevent_groups.h" - "${MOCK_GEN_DIR}/Mockqueue.c" "${MOCK_GEN_DIR}/Mockqueue.h" - "${MOCK_GEN_DIR}/Mocktask.c" "${MOCK_GEN_DIR}/Mocktask.h" - "${MOCK_GEN_DIR}/Mockesp_log.c" "${MOCK_GEN_DIR}/Mockesp_log.h" - "${MOCK_GEN_DIR}/Mockhttp_parser.c" "${MOCK_GEN_DIR}/Mockhttp_parser.h" - ) - - set(HEADERS_TO_MOCK - ${tcp_transport_dir}/include/esp_transport_tcp.h - ${tcp_transport_dir}/include/esp_transport_ws.h - ${tcp_transport_dir}/include/esp_transport_ssl.h - ${tcp_transport_dir}/include/esp_transport.h - ${esp_event_dir}/include/esp_event.h - ${esp_hw_support_dir}/include/esp_mac.h - ${esp_hw_support_dir}/include/esp_random.h - ${freertos_dir}/FreeRTOS-Kernel/include/freertos/event_groups.h - ${log_dir}/include/esp_log.h - ${http_parser_dir}/http_parser.h - ) - - set(srcs - ${MOCK_GEN_DIR}/Mockesp_transport.c - ${MOCK_GEN_DIR}/Mockesp_transport_ws.c - ${MOCK_GEN_DIR}/Mockesp_transport_ssl.c - ${MOCK_GEN_DIR}/Mockesp_transport_tcp.c - ${MOCK_GEN_DIR}/Mockesp_transport_tcp.c - ${MOCK_GEN_DIR}/Mockesp_event.c - ${MOCK_GEN_DIR}/Mockesp_mac.c - ${MOCK_GEN_DIR}/Mockesp_random.c - ${MOCK_GEN_DIR}/Mockesp_log.c - ${MOCK_GEN_DIR}/Mockhttp_parser.c - ${MOCK_GEN_DIR}/Mockevent_groups.c - ) - - add_custom_command( - OUTPUT ruby_found SYMBOLIC - COMMAND "ruby" "-v" - COMMENT "Try to find ruby. If this fails, you need to install ruby" - ) - - add_custom_command( - OUTPUT ${MOCK_OUTPUT} - DEPENDS ruby_found - COMMAND ${CMAKE_COMMAND} -E env "UNITY_DIR=${IDF_PATH}/components/unity/unity" - ruby - ${CMOCK_DIR}/lib/cmock.rb - -o${CMAKE_CURRENT_SOURCE_DIR}/host_test/mocks/config.yaml - ${HEADERS_TO_MOCK} - ) - - add_library(mocks ${srcs}) - target_include_directories(mocks PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/host_test/mocks/include - ${tcp_transport_dir}/include - ${esp_tls_dir} - ${freertos_dir}/FreeRTOS-Kernel/include - ${esp_event_dir}/include - ${esp_system_dir}/include - ${esp_common_dir}/include - ${esp_wifi_dir}/include - ${esp_hw_support_dir}/include - ${esp_netif_dir}/include - ${log_dir}/include - ${esp_rom_dir}/include - ${mbedtls_dir}/port/include - ${http_parser_dir} - ${mbedtls_dir}/mbedtls/include - ${freertos_dir}/FreeRTOS-Kernel/include/freertos - esp-mqtt/lib/include - ${MOCK_GEN_DIR} - ) - target_link_libraries(mocks PUBLIC ${cmock_lib}) - target_compile_definitions(mocks PUBLIC - CONFIG_LOG_TIMESTAMP_SOURCE_RTOS) - target_link_options(${COMPONENT_LIB} INTERFACE -fsanitize=address) - - target_link_libraries(${COMPONENT_LIB} PUBLIC mocks) - -else() - idf_component_optional_requires(PUBLIC esp_event tcp_transport) - idf_component_optional_requires(PRIVATE http_parser) -endif() diff --git a/components/mqtt/host_test/CMakeLists.txt b/components/mqtt/host_test/CMakeLists.txt index 7137910836..d1c1ac6ab8 100644 --- a/components/mqtt/host_test/CMakeLists.txt +++ b/components/mqtt/host_test/CMakeLists.txt @@ -2,9 +2,15 @@ cmake_minimum_required(VERSION 3.16) include($ENV{IDF_PATH}/tools/cmake/project.cmake) set(COMPONENTS main) -list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/mocks/freertos/" +list(APPEND EXTRA_COMPONENT_DIRS + "$ENV{IDF_PATH}/tools/mocks/esp_hw_support/" + "$ENV{IDF_PATH}/tools/mocks/freertos/" "$ENV{IDF_PATH}/tools/mocks/esp_timer/" + "$ENV{IDF_PATH}/tools/mocks/esp_event/" + "$ENV{IDF_PATH}/tools/mocks/lwip/" + "$ENV{IDF_PATH}/tools/mocks/esp-tls/" + "$ENV{IDF_PATH}/tools/mocks/http_parser/" + "$ENV{IDF_PATH}/tools/mocks/tcp_transport/" ) -option(TEST_BUILD "" ON) project(host_mqtt_client_test) diff --git a/components/mqtt/host_test/main/CMakeLists.txt b/components/mqtt/host_test/main/CMakeLists.txt index 90692f6cce..6c4a9c708a 100644 --- a/components/mqtt/host_test/main/CMakeLists.txt +++ b/components/mqtt/host_test/main/CMakeLists.txt @@ -1,3 +1,3 @@ idf_component_register(SRCS "test_mqtt_client.cpp" INCLUDE_DIRS "$ENV{IDF_PATH}/tools/catch" - REQUIRES cmock mqtt esp_timer) + REQUIRES cmock mqtt esp_timer esp_hw_support http_parser log) diff --git a/components/mqtt/host_test/main/test_mqtt_client.cpp b/components/mqtt/host_test/main/test_mqtt_client.cpp index 4979c194f1..8ebbf1eefc 100644 --- a/components/mqtt/host_test/main/test_mqtt_client.cpp +++ b/components/mqtt/host_test/main/test_mqtt_client.cpp @@ -3,7 +3,6 @@ extern "C" { #include "Mockesp_event.h" -#include "Mockesp_log.h" #include "Mockesp_mac.h" #include "Mockesp_transport.h" #include "Mockesp_transport_ssl.h" @@ -37,14 +36,12 @@ struct ClientInitializedFixture { int transport; int event_group; uint8_t mac[] = {0xAA, 0x55, 0xAA, 0x55, 0xAA, 0x55}; - esp_log_write_Ignore(); esp_timer_get_time_IgnoreAndReturn(0); xQueueTakeMutexRecursive_IgnoreAndReturn(true); xQueueGiveMutexRecursive_IgnoreAndReturn(true); xQueueCreateMutex_ExpectAnyArgsAndReturn( reinterpret_cast(&mtx)); xEventGroupCreate_IgnoreAndReturn(reinterpret_cast(&event_group)); - esp_log_timestamp_IgnoreAndReturn(0); esp_transport_list_init_IgnoreAndReturn(reinterpret_cast(&transport_list)); esp_transport_tcp_init_IgnoreAndReturn(reinterpret_cast(&transport)); esp_transport_ssl_init_IgnoreAndReturn(reinterpret_cast(&transport)); diff --git a/components/mqtt/test/test_mqtt.c b/components/mqtt/test/test_mqtt.c index 2494d03c8a..d997bceb98 100644 --- a/components/mqtt/test/test_mqtt.c +++ b/components/mqtt/test/test_mqtt.c @@ -104,4 +104,5 @@ TEST_CASE("mqtt broker tests", "[mqtt][test_env=UT_T2_Ethernet]") connect_test_fixture_teardown(); } + #endif // SOC_EMAC_SUPPORTED diff --git a/components/newlib/locks.c b/components/newlib/locks.c index b11c07017e..15f5bd8062 100644 --- a/components/newlib/locks.c +++ b/components/newlib/locks.c @@ -384,7 +384,7 @@ void esp_newlib_locks_init(void) __sinit_recursive_mutex = (_lock_t) &s_common_recursive_mutex; extern _lock_t __sfp_recursive_mutex; __sfp_recursive_mutex = (_lock_t) &s_common_recursive_mutex; -#elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32H2) || defined(CONFIG_IDF_TARGET_ESP32C2) +#elif ESP_ROM_HAS_RETARGETABLE_LOCKING /* Newlib 3.3.0 is used in ROM, built with _RETARGETABLE_LOCKING. * No access to lock variables for the purpose of ECO forward compatibility, * however we have an API to initialize lock variables used in the ROM. diff --git a/components/newlib/newlib_init.c b/components/newlib/newlib_init.c index bfb0c81143..c59c6d3572 100644 --- a/components/newlib/newlib_init.c +++ b/components/newlib/newlib_init.c @@ -33,6 +33,8 @@ #include "esp32h2/rom/libc_stubs.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/libc_stubs.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/libc_stubs.h" #endif static struct _reent s_reent; @@ -109,7 +111,8 @@ static struct syscall_stub_table s_stub_table = { ._printf_float = NULL, ._scanf_float = NULL, #endif -#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 +#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 \ + || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 /* TODO IDF-2570 : mark that this assert failed in ROM, to avoid confusion between IDF & ROM assertion failures (as function names & source file names will be similar) */ @@ -132,7 +135,8 @@ void esp_newlib_init(void) syscall_table_ptr_pro = syscall_table_ptr_app = &s_stub_table; #elif CONFIG_IDF_TARGET_ESP32S2 syscall_table_ptr_pro = &s_stub_table; -#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 +#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 \ + || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 syscall_table_ptr = &s_stub_table; #endif diff --git a/components/newlib/port/esp_time_impl.c b/components/newlib/port/esp_time_impl.c index 77485e971a..ec8f8c0b41 100644 --- a/components/newlib/port/esp_time_impl.c +++ b/components/newlib/port/esp_time_impl.c @@ -39,6 +39,9 @@ #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/rtc.h" #include "esp32c2/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/rtc.h" +#include "esp32c6/rtc.h" #endif diff --git a/components/newlib/test/test_newlib.c b/components/newlib/test/test_newlib.c index f58151d3a6..3bf451dec6 100644 --- a/components/newlib/test/test_newlib.c +++ b/components/newlib/test/test_newlib.c @@ -146,7 +146,8 @@ TEST_CASE("check if ROM or Flash is used for functions", "[newlib]") #if defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_SPIRAM) TEST_ASSERT(fn_in_rom(atoi)); TEST_ASSERT(fn_in_rom(strtol)); -#elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32H2) || defined(CONFIG_IDF_TARGET_ESP32C2) +#elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32H2)\ + || defined(CONFIG_IDF_TARGET_ESP32C2) || defined(CONFIG_IDF_TARGET_ESP32C6) /* S3 and C3 always use these from ROM */ TEST_ASSERT(fn_in_rom(atoi)); TEST_ASSERT(fn_in_rom(strtol)); diff --git a/components/newlib/test/test_time.c b/components/newlib/test/test_time.c index a72ffbe6d7..e43944523d 100644 --- a/components/newlib/test/test_time.c +++ b/components/newlib/test/test_time.c @@ -40,6 +40,8 @@ #include "esp32h2/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rtc.h" #endif #if portNUM_PROCESSORS == 2 diff --git a/components/newlib/test_apps/main/CMakeLists.txt b/components/newlib/test_apps/main/CMakeLists.txt index 76686cf622..b54d173420 100644 --- a/components/newlib/test_apps/main/CMakeLists.txt +++ b/components/newlib/test_apps/main/CMakeLists.txt @@ -2,5 +2,6 @@ idf_component_register(SRCS "test_newlib_main.c" "test_stdatomic.c" "test_misc.c" + "test_file.c" REQUIRES test_utils - PRIV_REQUIRES unity) + PRIV_REQUIRES unity vfs) diff --git a/components/newlib/test_apps/main/test_file.c b/components/newlib/test_apps/main/test_file.c new file mode 100644 index 0000000000..e25df6b11a --- /dev/null +++ b/components/newlib/test_apps/main/test_file.c @@ -0,0 +1,94 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include +#include +#include +#include +#include +#include "esp_vfs.h" +#include "unity.h" +#include "unity_fixture.h" + +TEST_GROUP(file); + +TEST_SETUP(file) +{ +} + +TEST_TEAR_DOWN(file) +{ +} + +/* This test checks that st_blksize value set in struct stat correctly affects the + * FILE structure: + * - _blksize field should be equal to st_blksize + * - buffer size should be equal to st_blksize if it is nonzero, and __BUFSIZ__ otherwise. + * This is more of an integration test since some of the functions responsible for this are + * in ROM, and have been built without HAVE_BLKSIZE feature for the ESP32 chip. + */ + +typedef struct { + unsigned blksize; +} blksize_test_ctx_t; + +static int blksize_test_open(void* ctx, const char * path, int flags, int mode) +{ + return 1; +} + +static int blksize_test_fstat(void* ctx, int fd, struct stat * st) +{ + blksize_test_ctx_t* test_ctx = (blksize_test_ctx_t*) ctx; + memset(st, 0, sizeof(*st)); + st->st_mode = S_IFREG; + st->st_blksize = test_ctx->blksize; + return 0; +} + +static ssize_t blksize_test_write(void* ctx, int fd, const void * data, size_t size) +{ + return size; +} + +TEST(file, blksize) +{ + FILE* f; + blksize_test_ctx_t ctx = {}; + const char c = 42; + const esp_vfs_t desc = { + .flags = ESP_VFS_FLAG_CONTEXT_PTR, + .open_p = blksize_test_open, + .fstat_p = blksize_test_fstat, + .write_p = blksize_test_write, + }; + + TEST_ESP_OK(esp_vfs_register("/test", &desc, &ctx)); + + /* test with zero st_blksize (=not set) */ + ctx.blksize = 0; + f = fopen("/test/path", "w"); + TEST_ASSERT_NOT_NULL(f); + fwrite(&c, 1, 1, f); + TEST_ASSERT_EQUAL(0, f->_blksize); + TEST_ASSERT_EQUAL(__BUFSIZ__, __fbufsize(f)); + fclose(f); + + /* test with non-zero st_blksize */ + ctx.blksize = 4096; + f = fopen("/test/path", "w"); + TEST_ASSERT_NOT_NULL(f); + fwrite(&c, 1, 1, f); + TEST_ASSERT_EQUAL(ctx.blksize, f->_blksize); + TEST_ASSERT_EQUAL(ctx.blksize, __fbufsize(f)); + fclose(f); + + TEST_ESP_OK(esp_vfs_unregister("/test")); +} + +TEST_GROUP_RUNNER(file) +{ + RUN_TEST_CASE(file, blksize) +} diff --git a/components/newlib/test_apps/main/test_newlib_main.c b/components/newlib/test_apps/main/test_newlib_main.c index 00de90fa06..a18a88d85a 100644 --- a/components/newlib/test_apps/main/test_newlib_main.c +++ b/components/newlib/test_apps/main/test_newlib_main.c @@ -10,6 +10,7 @@ static void run_all_tests(void) { RUN_TEST_GROUP(stdatomic); RUN_TEST_GROUP(misc); + RUN_TEST_GROUP(file); } void app_main(void) diff --git a/components/nvs_flash/host_test/nvs_page_test/CMakeLists.txt b/components/nvs_flash/host_test/nvs_page_test/CMakeLists.txt index 7cbfe573bb..6d51e4612e 100644 --- a/components/nvs_flash/host_test/nvs_page_test/CMakeLists.txt +++ b/components/nvs_flash/host_test/nvs_page_test/CMakeLists.txt @@ -7,7 +7,7 @@ list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/mocks/driver/") list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/mocks/freertos/") list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/mocks/spi_flash/") -idf_build_set_property(COMPILE_DEFINITIONS "-DNO_DEBUG_STORAGE" APPEND) +idf_build_set_property(COMPILE_DEFINITIONS "NO_DEBUG_STORAGE" APPEND) project(test_nvs_page_host) diff --git a/components/nvs_flash/include/nvs.h b/components/nvs_flash/include/nvs.h index c49a212749..966c16de69 100644 --- a/components/nvs_flash/include/nvs.h +++ b/components/nvs_flash/include/nvs.h @@ -132,6 +132,8 @@ typedef struct nvs_opaque_iterator_t *nvs_iterator_t; * mode is NVS_READONLY * - ESP_ERR_NVS_INVALID_NAME if namespace name doesn't satisfy constraints * - ESP_ERR_NO_MEM in case memory could not be allocated for the internal structures + * - ESP_ERR_NVS_NOT_ENOUGH_SPACE if there is no space for a new entry or there are too many different + * namespaces (maximum allowed different namespaces: 254) * - other error codes from the underlying storage driver */ esp_err_t nvs_open(const char* namespace_name, nvs_open_mode_t open_mode, nvs_handle_t *out_handle); @@ -161,6 +163,8 @@ esp_err_t nvs_open(const char* namespace_name, nvs_open_mode_t open_mode, nvs_ha * mode is NVS_READONLY * - ESP_ERR_NVS_INVALID_NAME if namespace name doesn't satisfy constraints * - ESP_ERR_NO_MEM in case memory could not be allocated for the internal structures + * - ESP_ERR_NVS_NOT_ENOUGH_SPACE if there is no space for a new entry or there are too many different + * namespaces (maximum allowed different namespaces: 254) * - other error codes from the underlying storage driver */ esp_err_t nvs_open_from_partition(const char *part_name, const char* namespace_name, nvs_open_mode_t open_mode, nvs_handle_t *out_handle); diff --git a/components/nvs_flash/nvs_partition_generator/nvs_partition_gen.py b/components/nvs_flash/nvs_partition_generator/nvs_partition_gen.py index b515d12ac2..c99db28bdc 100755 --- a/components/nvs_flash/nvs_partition_generator/nvs_partition_gen.py +++ b/components/nvs_flash/nvs_partition_generator/nvs_partition_gen.py @@ -7,8 +7,6 @@ # SPDX-License-Identifier: Apache-2.0 # -from __future__ import division, print_function - import argparse import array import binascii @@ -21,7 +19,6 @@ import random import struct import sys import zlib -from builtins import bytes, int, range from io import open try: diff --git a/components/nvs_flash/nvs_partition_parser/README.rst b/components/nvs_flash/nvs_partition_parser/README.rst new file mode 100644 index 0000000000..dee97a85e0 --- /dev/null +++ b/components/nvs_flash/nvs_partition_parser/README.rst @@ -0,0 +1,29 @@ +NVS Partition Parser Utility +============================ + +:link_to_translation:`zh_CN:[中文]` + +Introduction +------------ + +The utility :component_file:`nvs_flash/nvs_partition_parser/nvs_read.py` loads and parses an NVS storage partition for easier debugging and data extraction. The utility also features integrity check which scans the partition for potential errors. + +Encrypted Partitions +-------------------- + +This utility does not support decryption. To decrypt the NVS partition, please use the :doc:`NVS Partition Generator Utility ` which does support NVS partition encryption and decryption. + +Usage +----- + +The utility provides six different output styles with `-d` or `--dump` option: + - `all` (default) - Prints all entries with metadata. + - `written` - Prints only written entries with metadata. + - `minimal` - Prints written `namespace:key = value` pairs. + - `namespaces` - Prints all written namespaces + - `blobs` - Prints all blobs and strings (reconstructs them if they are chunked). + - `storage_info` - Prints entry states count for every page. + +.. note:: There is also a `none` option which will not print anything. This can be used with the integrity check option if the NVS partition contents are irrelevant. + +The utility also provides an integrity check feature via the `-i` or `--integrity-check` option. This feature scans through the entire partition and prints potential errors. It can be used with the `-d none` option which will print only the potential errors. diff --git a/components/nvs_flash/nvs_partition_parser/README_CN.rst b/components/nvs_flash/nvs_partition_parser/README_CN.rst new file mode 100644 index 0000000000..a5d418e81e --- /dev/null +++ b/components/nvs_flash/nvs_partition_parser/README_CN.rst @@ -0,0 +1,29 @@ +NVS 分区解æç¨‹åº +====================== + +:link_to_translation:`en:[English]` + +ä»‹ç» +------- + +NVS 分区解æç¨‹åº :component_file:`nvs_flash/nvs_partition_parser/nvs_read.py` å è½½å¹¶è§£æ NVS 存储分区，以便äºè°ƒè¯•å’Œæ•°æ®æå–ă€‚è¯¥ç¨‹åºè¿˜æ”¯æŒå®Œæ•´æ€§æ£€æŸ¥åŸèƒ½ï¼Œå¯æ‰«æ分区中å¯èƒ½å­˜åœ¨ç„é”™è¯¯ă€‚ + +å å¯†åˆ†åŒº +----------- + +此程åºä¸æ”¯æŒè§£å¯†ă€‚如需解密 NVS 分区，请使用 :doc:`NVS 分区生æˆç¨‹åº `ă€‚è¯¥å·¥å…·æ”¯æŒ NVS 分区å è§£å¯†ă€‚ + +使用方法 +----------- + +该程åºé€è¿‡ `-d` 或 `-dump` 选项æ供了六ç§ä¸åŒç„输出方å¼ï¼ + - `all` (默认) - 打å°æ‰€æœ‰å¸¦æœ‰å…ƒæ•°æ®ç„æ¡ç›®ă€‚ + - `written` - åªæ‰“å°å¸¦æœ‰å…ƒæ•°æ®ç„写入æ¡ç›®ă€‚ + - `minimal` - 打å°å†™å…¥ç„ `namespace:key = value` å¯¹ă€‚ + - `namespaces` - 打å°æ‰€æœ‰å†™å…¥ç„命åç©ºé—´ă€‚ + - `blobs` - 打å°æ‰€æœ‰ blob 和字符串（若 blob 和字符串是以分å—ç„å½¢å¼ï¼Œåˆ™å¯¹å…¶è¿›è¡Œé‡ç»„ï¼‰ă€‚ + - `storage_info` - 打å°æ¯ä¸€é¡µé¢ç„æ¡ç›®ç¶æ€è®¡æ•°ă€‚ + +.. 注æ„:: 该程åºè¿˜æä¾› `none` 选项，该选项ä¸ä¼æ‰“å°ä»»ä½•ä¸œè¥¿ă€‚å¦‚æœ NVS 分区ç„内容并ä¸ç›¸å…³ï¼Œå¯ä»¥å°†è¯¥é€‰é¡¹å’Œå®Œæ•´æ€§æ£€æŸ¥é€‰é¡¹ä¸€èµ·ä½¿ç”¨ă€‚ + +该程åºæ”¯æŒå®Œæ•´æ€§æ£€æŸ¥åŸèƒ½ï¼Œé€‰æ‹©é€‰é¡¹ `-i` 或 `--integrity-check` å³å¯è¿è¡Œă€‚æ­¤åŸèƒ½å¯æ‰«æ整个分区，并打å°å‡ºå¯èƒ½å­˜åœ¨ç„é”™è¯¯ă€‚å½“æ­¤åŸèƒ½å’Œ `-d none` 一起使用时，å¯åªæ‰“å°å¯èƒ½å­˜åœ¨ç„é”™è¯¯ă€‚ diff --git a/components/nvs_flash/nvs_partition_parser/nvs_read.py b/components/nvs_flash/nvs_partition_parser/nvs_read.py new file mode 100644 index 0000000000..82baabfa67 --- /dev/null +++ b/components/nvs_flash/nvs_partition_parser/nvs_read.py @@ -0,0 +1,780 @@ +#!/usr/bin/env python3 +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +import argparse +import sys +import traceback +from typing import Any, Dict, List +from zlib import crc32 + + +class Logger: + ansi = { + 'red': '\033[31m', + 'green': '\033[32m', + 'yellow': '\033[33m', + 'blue': '\033[34m', + 'cyan': '\033[36m', + 'bold': '\033[1m', + 'clear': '\033[0m' + } + + def __init__(self, *, color:str='auto'): + self.color = color == 'always' or (color == 'auto' and sys.stdout.isatty()) + + def set_color(self, color:str) -> None: + self.color = color == 'always' or (color == 'auto' and sys.stdout.isatty()) + + def info(self, *args, **kwargs) -> None: # type: ignore + kwargs['file'] = kwargs.get('file', sys.stdout) # Set default output to be stdout, but can be overwritten + print(*args, **kwargs) + + def error(self, *args, **kwargs) -> None: # type: ignore + kwargs['file'] = kwargs.get('file', sys.stderr) # Set default output to be stderr, but can be overwritten + print(*args, **kwargs) + + def red(self, text:str) -> str: + if self.color: + return Logger.ansi['red'] + text + Logger.ansi['clear'] + return text + + def green(self, text:str) -> str: + if self.color: + return Logger.ansi['green'] + text + Logger.ansi['clear'] + return text + + def yellow(self, text:str) -> str: + if self.color: + return Logger.ansi['yellow'] + text + Logger.ansi['clear'] + return text + + def blue(self, text:str) -> str: + if self.color: + return Logger.ansi['blue'] + text + Logger.ansi['clear'] + return text + + def cyan(self, text:str) -> str: + if self.color: + return Logger.ansi['cyan'] + text + Logger.ansi['clear'] + return text + + def bold(self, text:str) -> str: + if self.color: + return Logger.ansi['bold'] + text + Logger.ansi['clear'] + return text + + +# Constants +class Constants: + class ConstantError(AttributeError): + pass + + def __init__(self) -> None: + self.page_size = 4096 + self.entry_size = 32 + self.item_type = { + 0x01: 'uint8_t', + 0x11: 'int8_t', + 0x02: 'uint16_t', + 0x12: 'int16_t', + 0x04: 'uint32_t', + 0x14: 'int32_t', + 0x08: 'uint64_t', + 0x18: 'int64_t', + 0x21: 'string', + 0x41: 'blob', + 0x42: 'blob_data', + 0x48: 'blob_index', + } + self.page_status = { + 0xffffffff: 'Empty', + 0xfffffffe: 'Active', + 0xfffffffc: 'Full', + 0xfffffff8: 'Freeing', + } + self.entry_status = { + 0b11: 'Empty', + 0b10: 'Written', + 0b00: 'Erased', + } + + def __setattr__(self, key:str, val:Any) -> None: + if self.__dict__.get(key, None) is None: + self.__dict__[key] = val + else: + raise Constants.ConstantError('Cannot change a constant!') + + +const = Constants() +log = Logger() + + +class NotAlignedError(ValueError): + pass + + +class NVS_Partition: + def __init__(self, name:str, raw_data:bytearray): + if len(raw_data) % const.page_size != 0: + raise NotAlignedError(f'Given partition data is not aligned to page size ({len(raw_data)} % {const.page_size} = {len(raw_data)%const.page_size})') + + # Divide partition into pages + self.name = name + self.pages = [] + for i in range(0, len(raw_data), const.page_size): + self.pages.append(NVS_Page(raw_data[i:i + const.page_size], i)) + + +class NVS_Page: + def __init__(self, page_data:bytearray, address:int): + if len(page_data) != const.page_size: + raise NotAlignedError(f'Size of given page does not match page size ({len(page_data)} != {const.page_size})') + + # Initialize class + self.is_empty = page_data[0:const.entry_size] == bytearray({0xff}) * const.entry_size + self.start_address = address + self.raw_header = page_data[0:const.entry_size] + self.raw_entry_state_bitmap = page_data[const.entry_size:2 * const.entry_size] + self.entries = [] + + # Load header + self.header:Dict[str, Any] = { + 'status': const.page_status.get(int.from_bytes(page_data[0:4], byteorder='little'), 'Invalid'), + 'page_index': int.from_bytes(page_data[4:8], byteorder='little'), + 'version': 256 - page_data[8], + 'crc':{ + 'original': int.from_bytes(page_data[28:32], byteorder='little'), + 'computed': crc32(page_data[4:28], 0xFFFFFFFF) + } + } + + # Load entry state bitmap + entry_states = [] + for c in self.raw_entry_state_bitmap: + for index in range(0, 8, 2): + entry_states.append(const.entry_status.get((c >> index) & 3, 'Invalid')) + entry_states = entry_states[:-2] + + # Load entries + i = 2 + while i < int(const.page_size / const.entry_size): # Loop through every entry + span = page_data[(i * const.entry_size) + 2] + if span in [0xff, 0]: # 'Default' span length to prevent span overflow + span = 1 + + # Load an entry + entry = NVS_Entry(i - 2, page_data[i * const.entry_size:(i + 1) * const.entry_size], entry_states[i - 2]) + self.entries.append(entry) + + # Load all children entries + if span != 1: + for span_idx in range(1, span): + page_addr = i + span_idx + entry_idx = page_addr - 2 + if page_addr * const.entry_size >= const.page_size: + break + child_entry = NVS_Entry(entry_idx, page_data[page_addr * const.entry_size:(page_addr + 1) * const.entry_size], entry_states[entry_idx]) + entry.child_assign(child_entry) + entry.compute_crc() + i += span + + +class NVS_Entry: + def __init__(self, index:int, entry_data:bytearray, entry_state:str): + if len(entry_data) != const.entry_size: + raise NotAlignedError(f'Given entry is not aligned to entry size ({len(entry_data)} % {const.entry_size} = {len(entry_data)%const.entry_size})') + + def item_convert(i_type:int, data:bytearray) -> Dict: + byte_size_mask = 0x0f + number_sign_mask = 0xf0 + fixed_entry_length_threshold = 0x20 # Fixed length entry type number is always smaller than this + if i_type in const.item_type: + # Deal with non variable length entries + if i_type < fixed_entry_length_threshold: + size = i_type & byte_size_mask + num = int.from_bytes(data[:size], byteorder='little', signed=bool(i_type & number_sign_mask)) + return {'value':num} + + # Deal with variable length entries + if const.item_type[i_type] in ['string', 'blob_data', 'blob']: + size = int.from_bytes(data[:2], byteorder='little') + crc = int.from_bytes(data[4:8], byteorder='little') + return {'value': [size, crc], + 'size': size, + 'crc': crc} + if const.item_type[i_type] == 'blob_index': + size = int.from_bytes(data[:4], byteorder='little') + chunk_count = data[4] + chunk_start = data[5] + return {'value': [size, chunk_count, chunk_start], + 'size': size, + 'chunk_count': chunk_count, + 'chunk_start': chunk_start} + return {'value': log.red('Cannot parse')} + + def key_decode(data:bytearray) -> str: + decoded = '' + for n in data: + char = chr(n) + if char.isprintable(): + decoded += char + return decoded + + self.raw = entry_data + self.state = entry_state + self.is_empty = self.raw == bytearray({0xff}) * const.entry_size + self.index = index + + namespace = self.raw[0] + entry_type = self.raw[1] + span = self.raw[2] + chunk_index = self.raw[3] + crc = self.raw[4:8] + key = self.raw[8:24] + data = self.raw[24:32] + raw_without_crc = self.raw[:4] + self.raw[8:32] + self.metadata: Dict[str, Any] = { + 'namespace': namespace, + 'type': const.item_type.get(entry_type, f'0x{entry_type:02x}'), + 'span': span, + 'chunk_index': chunk_index, + 'crc':{ + 'original': int.from_bytes(crc, byteorder='little'), + 'computed': crc32(raw_without_crc, 0xFFFFFFFF), + 'data_original': int.from_bytes(data[-4:], byteorder='little'), + 'data_computed': 0 + } + } + self.children: List['NVS_Entry'] = [] + self.key = key_decode(key) + self.data = item_convert(entry_type, data) + + def dump_raw(self) -> str: + hex_bytes = '' + decoded = '' + for i, c in enumerate(self.raw): + middle_index = int(len(self.raw) / 2) + if i == middle_index: # Add a space in the middle + hex_bytes += ' ' + decoded += ' ' + hex_bytes += f'{c:02x} ' + decoded += chr(c) if chr(c).isprintable() else '.' + return hex_bytes + ' ' + decoded + + def child_assign(self, entry:'NVS_Entry') -> None: + if not isinstance(entry, type(self)): + raise ValueError('You can assign only NVS_Entry') + self.children.append(entry) + + def compute_crc(self) -> None: + if self.metadata['span'] == 1: + return + + # Merge entries into one buffer + children_data = bytearray() + for entry in self.children: + children_data += entry.raw + children_data = children_data[:self.data['size']] # Discard padding + + self.metadata['crc']['data_computed'] = crc32(children_data, 0xFFFFFFFF) + + +def storage_stats(nvs_partition:NVS_Partition) -> None: + global_stats = { + 'written_entries': 0, + 'free_entries': 0, + 'erased_entries': 0, + 'invalid_entries': 0 + } + + for page in nvs_partition.pages: + written_e = 0 + free_e = 0 + erased_e = 0 + invalid_e = 0 + for entry in page.entries: + if entry.state == 'Written': + written_e += 1 + elif entry.state == 'Empty': + free_e += 1 + elif entry.state == 'Erased': + erased_e += 1 + else: + invalid_e += 1 + + log.info(log.bold(f'Page {page.header["status"]}')) + log.info(' Found entries:') + log.info(f' Written: {written_e: 5d}') + log.info(f' Erased: {erased_e: 5d}') + log.info(f' Empty: {free_e: 5d}') + log.info(f' Invalid: {invalid_e: 5d}') + log.info(f' Total: {written_e + free_e + erased_e + invalid_e: 5d}') + log.info() + global_stats['written_entries'] += written_e + global_stats['erased_entries'] += erased_e + global_stats['free_entries'] += free_e + global_stats['invalid_entries'] += invalid_e + + log.info(log.bold('Global')) + log.info(' Config:') + log.info(f' Page size: {const.page_size: 5d}') + log.info(f' Entry size: {const.entry_size: 5d}') + log.info(f' Total pages: {len(nvs_partition.pages): 5d}') + log.info(' Entries:') + log.info(f' Written: {global_stats["written_entries"]: 5d}') + log.info(f' Erased: {global_stats["erased_entries"]: 5d}') + log.info(f' Empty: {global_stats["free_entries"]: 5d}') + log.info(f' Invalid: {global_stats["invalid_entries"]: 5d}') + log.info(f' Total: {sum([global_stats[key] for key in global_stats]): 5d}') + log.info() + + +def dump_everything(nvs_partition:NVS_Partition, written_only:bool=False) -> None: + for page in nvs_partition.pages: + # Print page header + if page.is_empty: + log.info(log.bold(f'Page Empty, Page address: 0x{page.start_address:x}')) + else: + if page.header['crc']['original'] == page.header['crc']['computed']: # Color CRC32 + crc = log.green(f'{page.header["crc"]["original"]: >8x}') + else: + crc = log.red(f'{page.header["crc"]["original"]: >8x}') + log.info(log.bold(f'Page no. {page.header["page_index"]}' + + f', Status: {page.header["status"]}' + + f', Version: {page.header["version"]}' + + f', CRC32: {crc}') + + log.bold(f', Page address: 0x{page.start_address:x}')) + + log.info(log.bold(' Entry state bitmap: '), end='') + for x in page.raw_entry_state_bitmap: + log.info(f'{x:02x} ', end='') + log.info() + + # Dump entries + empty_entries = [] + for entry in page.entries: + # Skip non-written entries if needed + if written_only and not entry.state == 'Written': + continue + + # Compress all empty entries + if entry.state == 'Empty' and entry.is_empty: # Gather all subsequent empty entries + empty_entries.append(entry) + continue + else: + # Print the empty entries + if len(empty_entries) >= 3: # There is enough entries to compress + log.info(log.bold(f' {empty_entries[0].index:03d}.'), 'Empty') + log.info(log.bold(' ...')) + log.info(log.bold(f' {empty_entries[-1].index:03d}.'), 'Empty') + else: # No need for compression + for e in empty_entries: + log.info(log.bold(f' {e.index:03d}.'), 'Empty') + empty_entries.clear() + + # Dump a single entry + status = entry.state + if status == 'Written': + status = log.green(f'{status: <7}') + elif status == 'Erased': + status = log.red(f'{status: <7}') + + crc = '' + if entry.metadata['crc']['original'] == entry.metadata['crc']['computed']: # Color CRC32 + crc = log.green(f'{entry.metadata["crc"]["original"]: >8x}') + else: + crc = log.red(f'{entry.metadata["crc"]["original"]: >8x}') + + log.info(log.bold(f' {entry.index:03d}.') + + ' ' + status + + f', Namespace Index: {entry.metadata["namespace"]:03d}' + + f', Type: {entry.metadata["type"]:<10}' + + f', Span: {entry.metadata["span"]:03d}' + + f', Chunk Index: {entry.metadata["chunk_index"]:03d}' + + f', CRC32: {crc}' + + f' | {entry.key} : ', end='') + + if entry.metadata['type'] not in ['string', 'blob_data', 'blob_index', 'blob']: # Entry is non-variable length + log.info(entry.data['value']) + else: + if entry.metadata['type'] == 'blob_index': + log.info(f'Size={entry.data["size"]}' + + f', ChunkCount={entry.data["chunk_count"]}' + + f', ChunkStart={entry.data["chunk_start"]}') + else: + if entry.metadata['crc']['data_original'] == entry.metadata['crc']['data_computed']: # Color CRC32 + crc = log.green(f'{entry.metadata["crc"]["data_original"]:x}') + else: + crc = log.red(f'{entry.metadata["crc"]["data_original"]:x}') + log.info(f'Size={entry.data["size"]}, CRC32={crc}') + + # Dump all children entries + if entry.metadata['span'] != 1: + for i, data in enumerate(entry.children): + log.info(f'{"": >6}0x{(i*const.entry_size):03x} {data.dump_raw()}') + + # Dump trailing empty entries + if len(empty_entries) >= 3: + log.info(log.bold(f' {empty_entries[0].index:03d}.'), 'Empty') + log.info(log.bold(' ...')) + log.info(log.bold(f' {empty_entries[-1].index:03d}.'), 'Empty') + else: + for e in empty_entries: + log.info(log.bold(f' {e.index:03d}.'), 'Empty') + empty_entries.clear() + log.info() + + +def dump_written_entries(nvs_partition:NVS_Partition) -> None: + dump_everything(nvs_partition, True) + + +def list_namespaces(nvs_partition:NVS_Partition) -> None: + # Gather namespaces + ns = {} + for page in nvs_partition.pages: + for entry in page.entries: + if entry.state == 'Written' and entry.metadata['namespace'] == 0: + ns[entry.data['value']] = entry.key + + # Print found namespaces + log.info(log.bold(f'Index : Namespace')) + for ns_index in sorted(ns): + log.info(f' {ns_index:03d} :', log.cyan(ns[ns_index])) + + +def dump_key_value_pairs(nvs_partition:NVS_Partition) -> None: + # Get namespace list + ns = {} + for page in nvs_partition.pages: + for entry in page.entries: + if entry.state == 'Written' and entry.metadata['namespace'] == 0: + ns[entry.data['value']] = entry.key + + # Print key-value pairs + for page in nvs_partition.pages: + # Print page header + if page.is_empty: + log.info(log.bold('Page Empty')) + else: + log.info(log.bold(f'Page no. {page.header["page_index"]}' + + f', Status: {page.header["status"]}')) + + # Print entries + for entry in page.entries: + if entry.state == 'Written' and entry.metadata['namespace'] != 0: # Ignore non-written entries + chunk_index = '' + data = '' + if entry.metadata['type'] not in ['string', 'blob_data', 'blob_index', 'blob']: # Non-variable length entry + data = entry.data['value'] + elif entry.metadata['type'] == 'blob_index': + continue + else: # Variable length entries + tmp = b'' + for e in entry.children: # Merge all children entries + tmp += bytes(e.raw) + tmp = tmp[:entry.data['size']] # Discard padding + if entry.metadata['type'] == 'blob_data': + if entry.metadata['chunk_index'] >= 128: # Get real chunk index + chunk_index = f'[{entry.metadata["chunk_index"] - 128}]' + else: + chunk_index = f'[{entry.metadata["chunk_index"]}]' + data = str(tmp) + + if entry.metadata['namespace'] not in ns: + continue + else: + log.info(' ' + + log.cyan(ns[entry.metadata['namespace']]) + + ':' + + log.yellow(entry.key) + + f'{chunk_index} = {data}') + log.info() + + +def dump_written_blobs(nvs_partition:NVS_Partition) -> None: + blobs: Dict = {} + strings: List[NVS_Entry] = [] + legacy_blobs: List[NVS_Entry] = [] + ns = {} + empty_entry = NVS_Entry(-1, bytearray(32), 'Erased') + + # Gather namespaces, blob indexes and legacy blobs + for page in nvs_partition.pages: + for entry in page.entries: + if entry.state == 'Written': + if entry.metadata['type'] == 'blob_index': + blobs[f'{entry.metadata["namespace"]:03d}{entry.key}'] = [entry] + [empty_entry] * entry.data['chunk_count'] + elif entry.metadata['type'] == 'blob': + legacy_blobs.append(entry) + elif entry.metadata['type'] == 'string': + strings.append(entry) + elif entry.metadata['namespace'] == 0: + ns[entry.data['value']] = entry.key + + # Dump blobs + for key in blobs: + for page in nvs_partition.pages: + for entry in page.entries: + # Gather all blob chunks + if entry.state == 'Written' \ + and entry.metadata['type'] != 'blob_index' \ + and entry.metadata['namespace'] == blobs[key][0].metadata['namespace'] \ + and entry.key == blobs[key][0].key: + blobs[key][1 + entry.metadata['chunk_index'] - blobs[key][0].data['chunk_start']] = entry + + blob_index = blobs[key][0] + blob_chunks = blobs[key][1:] + + # Print blob info + log.info(log.cyan(ns.get(blob_index.metadata['namespace'], blob_index.metadata['namespace'])) + + ':' + + log.yellow(blob_index.key) + + ' - ' + + f'Type: Blob (Version 2), ' + + f'Size: {blob_index.data["size"]}') + + # Print blob data + raw_entries = [] + for kid in blob_chunks: # Gather all chunk entries + if kid is empty_entry: + raw_entries += [empty_entry] + else: + raw_entries += kid.children + + for i, entry in enumerate(raw_entries): + if entry is empty_entry: + log.info(log.yellow(f' {"":->63} Missing data {"":-<64}')) + else: + log.info(f' 0x{(i * const.entry_size):05x} {entry.dump_raw()}') + log.info() + + # Dump strings + for string in strings: + log.info(log.cyan(ns.get(string.metadata['namespace'], string.metadata['namespace'])) + + ':' + + log.yellow(string.key) + + ' - ' + + 'Type: String, ' + + f'Size: {string.data["size"]}') + for i, entry in enumerate(string.children): + log.info(f' 0x{(i * const.entry_size):05x} {entry.dump_raw()}') + log.info() + + # Dump legacy blobs + for blob in legacy_blobs: + log.info(log.cyan(ns.get(blob.metadata['namespace'], blob.metadata['namespace'])) + + ':' + + log.yellow(blob.key) + + ' - ' + + 'Type: Blob (Version 1), ' + + f'Size: {blob.data["size"]}') + for i, entry in enumerate(blob.children): + log.info(f' 0x{(i * const.entry_size):05x} {entry.dump_raw()}') + log.info() + + +def integrity_check(nvs_partition:NVS_Partition) -> None: + used_namespaces: Dict[int, None] = {} + found_namespaces: Dict[int, str] = {} + blobs:Dict = {} + blob_chunks: List[NVS_Entry] = [] + empty_entry = NVS_Entry(-1, bytearray(32), 'Erased') + + # Partition size + if len(nvs_partition.pages) < 3: + log.info(log.yellow('Partition has to have at least 3 pages to function properly!')) + + for page in nvs_partition.pages: + # Print page header + if page.header['status'] == 'Empty': + log.info(log.cyan('Page Empty')) + + # Check if page is truly empty + if page.raw_entry_state_bitmap != bytearray({0xff}) * const.entry_size: + log.info(log.red('Page is reported as empty but entry state bitmap is not empty!')) + if any([not e.is_empty for e in page.entries]): + log.info(log.red('Page is reported as emtpy but there is written data!')) + else: + # Check page header CRC32 + if page.header['crc']['original'] == page.header['crc']['computed']: + log.info(log.cyan(f'Page no. {page.header["page_index"]}')) + else: + log.info(log.cyan(f'Page no. {page.header["page_index"]}'), + f'Written CRC32:', + log.red(f'{page.header["crc"]["original"]:x}'), + f'Generated CRC32:', + log.green(f'{page.header["crc"]["computed"]:x}')) + + # Check all entries + for entry in page.entries: + # Entry state check + if entry.is_empty: + if entry.state == 'Written': + log.info(log.red(f' Entry #{entry.index:03d} is reported as written but is empty!')) + continue + elif entry.state == 'Erased': + log.info(log.yellow(f' Entry #{entry.index:03d} is reported as erased but is empty!')) + + if entry.state == 'Written': + # Entry CRC32 check + if entry.metadata['crc']['original'] != entry.metadata['crc']['computed']: + log.info(log.red(f' Entry #{entry.index:03d} {entry.key} has wrong CRC32!{"": <5}'), + f'Written:', + log.red(f'{entry.metadata["crc"]["original"]:x}'), + f'Generated:', + log.green(f'{entry.metadata["crc"]["computed"]:x}')) + + # Entry children CRC32 check + if entry.metadata['span'] > 1 and entry.metadata['crc']['data_original'] != entry.metadata['crc']['data_computed']: + log.info(log.red(f' Entry #{entry.index:03d} {entry.key} data has wrong CRC32!'), + f'Written:', + log.red(f'{entry.metadata["crc"]["original"]:x}'), + f'Generated:', + log.green(f'{entry.metadata["crc"]["computed"]:x}')) + + # Entry type check + if entry.metadata['type'] not in [const.item_type[key] for key in const.item_type]: + log.info(log.yellow(f' Type of entry #{entry.index:03d} {entry.key} is unrecognized!'), + f'Type: {entry.metadata["type"]}') + + # Span check + if entry.index + entry.metadata['span'] - 1 >= int(const.page_size / const.entry_size) - 2: + log.info(log.red(f' Variable length entry #{entry.index:03d} {entry.key} is out of bounds!')) + # Spanned entry state checks + elif entry.metadata['span'] > 1: + parent_state = entry.state + for kid in entry.children: + if parent_state != kid.state: + log.info(log.yellow(' Inconsistent data state!'), + f'Entry #{entry.index:03d} {entry.key} state: {parent_state},', + f'Data entry #{kid.index:03d} {entry.key} state: {kid.state}') + + # Gather blobs & namespaces + if entry.metadata['type'] == 'blob_index': + blobs[f'{entry.metadata["namespace"]:03d}{entry.key}'] = [entry] + [empty_entry] * entry.data['chunk_count'] + elif entry.metadata['type'] == 'blob_data': + blob_chunks.append(entry) + + if entry.metadata['namespace'] == 0: + found_namespaces[entry.data['value']] = entry.key + else: + used_namespaces[entry.metadata['namespace']] = None + log.info() + + # Assemble blobs + for chunk in blob_chunks: + parent = blobs.get(f'{chunk.metadata["namespace"]:03d}{chunk.key}', [empty_entry])[0] + if parent is empty_entry: + log.info(log.red(f'Blob {chunk.key} chunk has no blob index!'), + f'Namespace index: {chunk.metadata["namespace"]:03d}', + f'[{found_namespaces.get(chunk.metadata["namespace"], "undefined")}],', + f'Chunk Index: {chunk.metadata["chunk_index"]:03d}') + else: + blob_key = f'{chunk.metadata["namespace"]:03d}{chunk.key}' + chunk_index = chunk.metadata['chunk_index'] - parent.data['chunk_start'] + blobs[blob_key][chunk_index + 1] = chunk + + # Check all blobs + for blob_key in blobs: + blob_index = blobs[blob_key][0] + blob_chunks = blobs[blob_key][1:] + blob_size = blob_index.data['size'] + + # Blob data check + for i, chunk in enumerate(blob_chunks): + if chunk is empty_entry: + log.info(log.red(f'Blob {blob_index.key} is missing a chunk!'), + f'Namespace index: {blob_index.metadata["namespace"]:03d}', + f'[{found_namespaces.get(blob_index.metadata["namespace"], "undefined")}],', + f'Chunk Index: {i:03d}') + else: + blob_size -= len(chunk.children) * const.entry_size + + if blob_size > 0: + log.info(log.red(f'Blob {blob_index.key} is missing {blob_size} B of data!'), + f'Namespace index: {blob_index.metadata["namespace"]:03d}') + + # Namespaces + for used_ns in used_namespaces: + key = found_namespaces.pop(used_ns, '') + if key == '': + log.info(log.red('Undefined namespace index!'), + f'Namespace index: {used_ns:03d}', + f'[undefined]') + + for unused_ns in found_namespaces: + log.info(log.yellow('Found unused namespace.'), + f'Namespace index: {unused_ns:03d}', + f'[{found_namespaces[unused_ns]}]') + + +def program_args() -> argparse.Namespace: + parser = argparse.ArgumentParser(description='Parse NVS partition') + parser.add_argument('file', help='Path to dumped NVS partition') + parser.add_argument('-i', '--integrity-check', action='store_true', + help='Check partition for potential errors') + tmp = {'all': 'Print everything', + 'written': 'Print only currently written entries', + 'minimal': 'Print only namespace:key=value pairs', + 'namespaces': 'List all written namespaces', + 'blobs': 'Print all blobs and strings', + 'storage_info': 'Print storage related information (free/used entries, etc)', + 'none': 'Do not print anything (if you only want to do integrity check)'} + parser.add_argument('-d', '--dump', choices=tmp, default='all', metavar='type', + help=f"type={{{str(list(tmp.keys()))[1:-1]}}} : {' ; '.join([f'{opt} - {tmp[opt]}' for opt in tmp])}") + parser.add_argument('--color', choices=['never', 'auto', 'always'], default='auto', help='Enable color (ANSI)') + return parser.parse_args() + + +def main() -> None: + args = program_args() + + if const.entry_size != 32: + raise ValueError(f'Entry size is not 32 B! This is currently non negotiable.') + + log.set_color(args.color) + + try: + with open(args.file, 'rb') as f: + partition = f.read() + except IndexError: + log.error('No file given') + raise + except FileNotFoundError: + log.error('Bad filename') + raise + + nvs = NVS_Partition(args.file.split('/')[-1], bytearray(partition)) + + def noop(_:NVS_Partition) -> None: + pass + + def not_implemented(_:NVS_Partition) -> None: + raise RuntimeError(f'{args.dump} is not implemented') + + cmds = { + 'all': dump_everything, + 'written': dump_written_entries, + 'minimal': dump_key_value_pairs, + 'namespaces': list_namespaces, + 'blobs': dump_written_blobs, + 'storage_info': storage_stats, + 'none': noop, + } + cmds.get(args.dump, not_implemented)(nvs) # type: ignore + + if args.integrity_check: + log.info() + integrity_check(nvs) + + +if __name__ == '__main__': + try: + main() + except ValueError: + traceback.print_exc(file=sys.stderr) + sys.exit(1) + except Constants.ConstantError: + traceback.print_exc(file=sys.stderr) + sys.exit(1) diff --git a/components/nvs_flash/src/intrusive_list.h b/components/nvs_flash/src/intrusive_list.h index 798b718a66..9a8c6f228e 100644 --- a/components/nvs_flash/src/intrusive_list.h +++ b/components/nvs_flash/src/intrusive_list.h @@ -30,9 +30,14 @@ class intrusive_list public: - class iterator : public std::iterator + class iterator { public: + using iterator_category = std::forward_iterator_tag; + using value_type = T; + using difference_type = ptrdiff_t; + using pointer = T*; + using reference = T&; iterator() : mPos(nullptr) {} diff --git a/components/nvs_flash/src/nvs_api.cpp b/components/nvs_flash/src/nvs_api.cpp index 8d63c25469..6d7f546050 100644 --- a/components/nvs_flash/src/nvs_api.cpp +++ b/components/nvs_flash/src/nvs_api.cpp @@ -116,7 +116,7 @@ extern "C" esp_err_t nvs_flash_init_partition_ptr(const esp_partition_t *partiti return init_res; } -#ifndef LINUX_TARGET +#ifndef LINUX_HOST_LEGACY_TEST extern "C" esp_err_t nvs_flash_init_partition(const char *part_name) { esp_err_t lock_result = Lock::init(); @@ -239,7 +239,7 @@ extern "C" esp_err_t nvs_flash_erase(void) { return nvs_flash_erase_partition(NVS_DEFAULT_PART_NAME); } -#endif // ! LINUX_TARGET +#endif // LINUX_HOST_LEGACY_TEST extern "C" esp_err_t nvs_flash_deinit_partition(const char* partition_name) { diff --git a/components/nvs_flash/src/nvs_page.cpp b/components/nvs_flash/src/nvs_page.cpp index dbae73060e..36cde3db25 100644 --- a/components/nvs_flash/src/nvs_page.cpp +++ b/components/nvs_flash/src/nvs_page.cpp @@ -128,37 +128,11 @@ esp_err_t Page::writeEntryData(const uint8_t* data, size_t size) NVS_ASSERT_OR_RETURN(mFirstUsedEntry != INVALID_ENTRY, ESP_FAIL); const uint16_t count = size / ENTRY_SIZE; - const uint8_t* buf = data; - -#if !defined LINUX_TARGET - // TODO: check whether still necessary with esp_partition* API - /* On the ESP32, data can come from DROM, which is not accessible by spi_flash_write - * function. To work around this, we copy the data to heap if it came from DROM. - * Hopefully this won't happen very often in practice. For data from DRAM, we should - * still be able to write it to flash directly. - * TODO: figure out how to make this platform-specific check nicer (probably by introducing - * a platform-specific flash layer). - */ - if ((uint32_t) data < 0x3ff00000) { - buf = (uint8_t*) malloc(size); - if (!buf) { - return ESP_ERR_NO_MEM; - } - memcpy((void*)buf, data, size); - } -#endif // ! LINUX_TARGET - uint32_t phyAddr; esp_err_t rc = getEntryAddress(mNextFreeEntry, &phyAddr); if (rc == ESP_OK) { - rc = mPartition->write(phyAddr, buf, size); + rc = mPartition->write(phyAddr, data, size); } - -#if !defined LINUX_TARGET - if (buf != data) { - free((void*)buf); - } -#endif // ! LINUX_TARGET if (rc != ESP_OK) { mState = PageState::INVALID; return rc; diff --git a/components/nvs_flash/src/nvs_pagemanager.cpp b/components/nvs_flash/src/nvs_pagemanager.cpp index cdc6b221dd..062f627743 100644 --- a/components/nvs_flash/src/nvs_pagemanager.cpp +++ b/components/nvs_flash/src/nvs_pagemanager.cpp @@ -47,7 +47,10 @@ esp_err_t PageManager::load(Partition *partition, uint32_t baseSector, uint32_t return activatePage(); } else { uint32_t lastSeqNo; - ESP_ERROR_CHECK( mPageList.back().getSeqNumber(lastSeqNo) ); + auto err = mPageList.back().getSeqNumber(lastSeqNo); + if (err != ESP_OK) { + return err; + } mSeqNumber = lastSeqNo + 1; } diff --git a/components/nvs_flash/src/nvs_storage.cpp b/components/nvs_flash/src/nvs_storage.cpp index 1cf3b94859..03172f1a96 100644 --- a/components/nvs_flash/src/nvs_storage.cpp +++ b/components/nvs_flash/src/nvs_storage.cpp @@ -4,6 +4,10 @@ * SPDX-License-Identifier: Apache-2.0 */ #include "nvs_storage.hpp" +#if __has_include() +// for strlcpy +#include +#endif #ifndef ESP_PLATFORM // We need NO_DEBUG_STORAGE here since the integration tests on the host add some debug code. @@ -305,7 +309,10 @@ esp_err_t Storage::writeItem(uint8_t nsIndex, ItemType datatype, const char* key if (findPage->state() == Page::PageState::UNINITIALIZED || findPage->state() == Page::PageState::INVALID) { - ESP_ERROR_CHECK(findItem(nsIndex, datatype, key, findPage, item)); + err = findItem(nsIndex, datatype, key, findPage, item); + if (err != ESP_OK) { + return err; + } } /* Get the version of the previous index with same */ prevStart = item.blobIndex.chunkStart; @@ -383,7 +390,10 @@ esp_err_t Storage::writeItem(uint8_t nsIndex, ItemType datatype, const char* key if (findPage) { if (findPage->state() == Page::PageState::UNINITIALIZED || findPage->state() == Page::PageState::INVALID) { - ESP_ERROR_CHECK(findItem(nsIndex, datatype, key, findPage, item)); + err = findItem(nsIndex, datatype, key, findPage, item); + if (err != ESP_OK) { + return err; + } } err = findPage->eraseItem(nsIndex, datatype, key); if (err == ESP_ERR_FLASH_OP_FAIL) { @@ -749,11 +759,7 @@ void Storage::fillEntryInfo(Item &item, nvs_entry_info_t &info) for (auto &name : mNamespaces) { if(item.nsIndex == name.mIndex) { -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstringop-truncation" - strncpy(info.namespace_name, name.mName, sizeof(info.namespace_name) - 1); -#pragma GCC diagnostic pop - info.namespace_name[sizeof(info.namespace_name) -1] = '\0'; + strlcpy(info.namespace_name, name.mName, sizeof(info.namespace_name)); break; } } diff --git a/components/nvs_flash/test_nvs_host/Makefile b/components/nvs_flash/test_nvs_host/Makefile index 10669bfb6f..ffa5a920c3 100644 --- a/components/nvs_flash/test_nvs_host/Makefile +++ b/components/nvs_flash/test_nvs_host/Makefile @@ -2,7 +2,6 @@ TEST_PROGRAM=test_nvs all: $(TEST_PROGRAM) SOURCE_FILES = \ - esp_error_check_stub.cpp \ $(addprefix ../src/, \ nvs_types.cpp \ nvs_api.cpp \ @@ -30,7 +29,7 @@ SOURCE_FILES = \ test_nvs_initialization.cpp \ main.cpp -SOURCE_FILES_C = ../../esp_rom/linux/esp_rom_crc.c +SOURCE_FILES_C = ../../esp_rom/linux/esp_rom_crc.c ../../esp_common/src/esp_err_check_linux.c ifeq ($(shell $(CC) -v 2>&1 | grep -c "clang version"), 1) COMPILER := clang @@ -39,10 +38,14 @@ COMPILER := gcc endif CPPFLAGS += -I../private_include -I../include -I../src -I../../esp_rom/include -I../../esp_rom/include/linux -I../../log/include -I./ -I../../esp_common/include -I../../esp32/include -I ../../mbedtls/mbedtls/include -I ../../spi_flash/include -I ../../hal/include -I ../../xtensa/include -I ../../../tools/catch -fprofile-arcs -ftest-coverage -g2 -ggdb -CFLAGS += -fprofile-arcs -ftest-coverage -DLINUX_TARGET -CXXFLAGS += -std=c++11 -Wall -Werror -DLINUX_TARGET +CFLAGS += -fprofile-arcs -ftest-coverage -DLINUX_TARGET -DLINUX_HOST_LEGACY_TEST +CXXFLAGS += -std=c++11 -Wall -Werror -DLINUX_TARGET -DLINUX_HOST_LEGACY_TEST LDFLAGS += -lstdc++ -Wall -fprofile-arcs -ftest-coverage +ifeq ($(shell uname -s),Linux) +LDFLAGS += -lbsd +endif + ifeq ($(COMPILER),clang) CFLAGS += -fsanitize=address CXXFLAGS += -fsanitize=address @@ -53,13 +56,16 @@ OBJ_FILES = $(SOURCE_FILES:.cpp=.o) OBJ_FILES_C = $(SOURCE_FILES_C:.c=.o) COVERAGE_FILES = $(OBJ_FILES:.o=.gc*) +MBEDTLS_LIB := ../../mbedtls/mbedtls/library/libmbedcrypto.a $(OBJ_FILES): %.o: %.cpp $(OBJ_FILES_C): %.c: %.c -$(TEST_PROGRAM): clean-coverage $(OBJ_FILES) $(OBJ_FILES_C) +$(MBEDTLS_LIB): $(MAKE) -C ../../mbedtls/mbedtls/ lib - g++ $(LDFLAGS) -o $(TEST_PROGRAM) $(OBJ_FILES) $(OBJ_FILES_C) ../../mbedtls/mbedtls/library/libmbedcrypto.a + +$(TEST_PROGRAM): $(OBJ_FILES) $(OBJ_FILES_C) $(MBEDTLS_LIB) | clean-coverage + g++ -o $@ $^ $(LDFLAGS) $(OUTPUT_DIR): mkdir -p $(OUTPUT_DIR) diff --git a/components/openthread/CMakeLists.txt b/components/openthread/CMakeLists.txt index d29b6bd6e4..0b91fd9b3b 100644 --- a/components/openthread/CMakeLists.txt +++ b/components/openthread/CMakeLists.txt @@ -34,16 +34,20 @@ if(CONFIG_OPENTHREAD_ENABLED) if(CONFIG_OPENTHREAD_FTD OR CONFIG_OPENTHREAD_MTD) list(APPEND src_dirs "src" - "openthread/examples/apps/cli" "openthread/src/core/backbone_router" "openthread/src/core/coap" "openthread/src/core/meshcop" "openthread/src/core/net" - "openthread/src/cli" "openthread/src/lib/platform") - list(APPEND exclude_srcs - "openthread/examples/apps/cli/main.c") + if(CONFIG_OPENTHREAD_CLI) + list(APPEND src_dirs + "openthread/examples/apps/cli" + "openthread/src/cli") + + list(APPEND exclude_srcs + "openthread/examples/apps/cli/main.c") + endif() elseif(CONFIG_OPENTHREAD_RADIO) list(APPEND src_dirs @@ -61,6 +65,7 @@ if(CONFIG_OPENTHREAD_ENABLED) "openthread/src/core/api/ip6_api.cpp" "openthread/src/core/api/link_api.cpp" "openthread/src/core/api/message_api.cpp" + "openthread/src/core/api/nat64_api.cpp" "openthread/src/core/api/netdata_api.cpp" "openthread/src/core/api/random_crypto_api.cpp" "openthread/src/core/api/tcp_api.cpp" @@ -78,6 +83,7 @@ if(CONFIG_OPENTHREAD_ENABLED) "openthread/src/core/mac/mac_links.cpp" "openthread/src/core/thread/announce_begin_server.cpp" "openthread/src/core/thread/announce_sender.cpp" + "openthread/src/core/thread/address_resolver.cpp" "openthread/src/core/thread/discover_scanner.cpp" "openthread/src/core/thread/energy_scan_server.cpp" "openthread/src/core/thread/key_manager.cpp" diff --git a/components/openthread/Kconfig b/components/openthread/Kconfig index e6e962be94..b5e86b104a 100644 --- a/components/openthread/Kconfig +++ b/components/openthread/Kconfig @@ -6,6 +6,44 @@ menu "OpenThread" help Select this option to enable OpenThread and show the submenu with OpenThread configuration choices. + config OPENTHREAD_LOG_LEVEL_DYNAMIC + bool "Enable dynamic log level control" + depends on OPENTHREAD_ENABLED + default y + help + Select this option to enable dynamic log level control for OpenThread + + choice OPENTHREAD_LOG_LEVEL + prompt "OpenThread log verbosity" + depends on OPENTHREAD_ENABLED && !OPENTHREAD_LOG_LEVEL_DYNAMIC + default OPENTHREAD_LOG_LEVEL_INFO + help + Select OpenThread log level. + + config OPENTHREAD_LOG_LEVEL_NONE + bool "No logs" + config OPENTHREAD_LOG_LEVEL_CRIT + bool "Error logs" + config OPENTHREAD_LOG_LEVEL_WARN + bool "Warning logs" + config OPENTHREAD_LOG_LEVEL_NOTE + bool "Notice logs" + config OPENTHREAD_LOG_LEVEL_INFO + bool "Info logs" + config OPENTHREAD_LOG_LEVEL_DEBG + bool "Debug logs" + endchoice #OPENTHREAD_LOG_LEVEL + + config OPENTHREAD_LOG_LEVEL + int + depends on OPENTHREAD_ENABLED && !OPENTHREAD_LOG_LEVEL_DYNAMIC + default 0 if OPENTHREAD_LOG_LEVEL_NONE + default 1 if OPENTHREAD_LOG_LEVEL_CRIT + default 2 if OPENTHREAD_LOG_LEVEL_WARN + default 3 if OPENTHREAD_LOG_LEVEL_NOTE + default 4 if OPENTHREAD_LOG_LEVEL_INFO + default 5 if OPENTHREAD_LOG_LEVEL_DEBG + choice OPENTHREAD_RADIO_TYPE prompt "Config the Thread radio type" depends on OPENTHREAD_ENABLED @@ -51,6 +89,13 @@ menu "OpenThread" radio only device. endchoice + config OPENTHREAD_CLI + bool "Enable Openthread Command-Line Interface" + depends on OPENTHREAD_ENABLED + default y + help + Select this option to enable Command-Line Interface in OpenThread. + config OPENTHREAD_DIAG bool "Enable diag" depends on OPENTHREAD_ENABLED diff --git a/components/openthread/lib b/components/openthread/lib index af1ac2b377..698e8386c3 160000 --- a/components/openthread/lib +++ b/components/openthread/lib @@ -1 +1 @@ -Subproject commit af1ac2b3770335db96702bcb06ca793a1425dc86 +Subproject commit 698e8386c31f2c34e167b65f72a6b2553e838dd9 diff --git a/components/openthread/openthread b/components/openthread/openthread index c055c10a9a..e64ba13faa 160000 --- a/components/openthread/openthread +++ b/components/openthread/openthread @@ -1 +1 @@ -Subproject commit c055c10a9a1362a96687614d4478dd2773e6ddc0 +Subproject commit e64ba13faa865aa7febd5cb7dc7eb52ff19a2c5c diff --git a/components/openthread/private_include/openthread-core-esp32x-ftd-config.h b/components/openthread/private_include/openthread-core-esp32x-ftd-config.h index 49be86e632..ad015fba3d 100644 --- a/components/openthread/private_include/openthread-core-esp32x-ftd-config.h +++ b/components/openthread/private_include/openthread-core-esp32x-ftd-config.h @@ -41,6 +41,14 @@ */ #define OPENTHREAD_CONFIG_LOG_OUTPUT OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED +/** + * @def OPENTHREAD_CONFIG_LOG_LEVEL_DYNAMIC_ENABLE + * + * Configuration option to enable dynamic log level control. + * + */ +#define OPENTHREAD_CONFIG_LOG_LEVEL_DYNAMIC_ENABLE CONFIG_OPENTHREAD_LOG_LEVEL_DYNAMIC + /** * @def OPENTHREAD_CONFIG_LOG_LEVEL * @@ -48,15 +56,11 @@ * verbose log level possible. See `OPENTHREAD_CONFIG_LOG_LEVEL_INIT` to set the initial log level. * */ +#if OPENTHREAD_CONFIG_LOG_LEVEL_DYNAMIC_ENABLE #define OPENTHREAD_CONFIG_LOG_LEVEL OT_LOG_LEVEL_DEBG - -/** - * @def OPENTHREAD_CONFIG_LOG_LEVEL_DYNAMIC_ENABLE - * - * Define as 1 to enable dynamic log level control. - * - */ -#define OPENTHREAD_CONFIG_LOG_LEVEL_DYNAMIC_ENABLE 1 +#else +#define OPENTHREAD_CONFIG_LOG_LEVEL CONFIG_OPENTHREAD_LOG_LEVEL +#endif #define OPENTHREAD_CONFIG_LOG_CLI 1 #define OPENTHREAD_CONFIG_LOG_PKT_DUMP 1 @@ -150,13 +154,13 @@ #endif /** - * @def OPENTHREAD_CONFIG_BORDER_ROUTING_NAT64_ENABLE + * @def OPENTHREAD_CONFIG_NAT64_BORDER_ROUTING_ENABLE * * Define to 1 to enable Border Routing NAT64 support. * */ -#ifndef OPENTHREAD_CONFIG_BORDER_ROUTING_NAT64_ENABLE -#define OPENTHREAD_CONFIG_BORDER_ROUTING_NAT64_ENABLE 1 +#ifndef OPENTHREAD_CONFIG_NAT64_BORDER_ROUTING_ENABLE +#define OPENTHREAD_CONFIG_NAT64_BORDER_ROUTING_ENABLE 1 #endif /** diff --git a/components/openthread/private_include/openthread-core-esp32x-mtd-config.h b/components/openthread/private_include/openthread-core-esp32x-mtd-config.h index f2131e46e6..a675e00853 100644 --- a/components/openthread/private_include/openthread-core-esp32x-mtd-config.h +++ b/components/openthread/private_include/openthread-core-esp32x-mtd-config.h @@ -41,6 +41,14 @@ */ #define OPENTHREAD_CONFIG_LOG_OUTPUT OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED +/** + * @def OPENTHREAD_CONFIG_LOG_LEVEL_DYNAMIC_ENABLE + * + * Configuration option to enable dynamic log level control. + * + */ +#define OPENTHREAD_CONFIG_LOG_LEVEL_DYNAMIC_ENABLE CONFIG_OPENTHREAD_LOG_LEVEL_DYNAMIC + /** * @def OPENTHREAD_CONFIG_LOG_LEVEL * @@ -48,15 +56,11 @@ * verbose log level possible. See `OPENTHREAD_CONFIG_LOG_LEVEL_INIT` to set the initial log level. * */ +#if OPENTHREAD_CONFIG_LOG_LEVEL_DYNAMIC_ENABLE #define OPENTHREAD_CONFIG_LOG_LEVEL OT_LOG_LEVEL_DEBG - -/** - * @def OPENTHREAD_CONFIG_LOG_LEVEL_DYNAMIC_ENABLE - * - * Define as 1 to enable dynamic log level control. - * - */ -#define OPENTHREAD_CONFIG_LOG_LEVEL_DYNAMIC_ENABLE 1 +#else +#define OPENTHREAD_CONFIG_LOG_LEVEL CONFIG_OPENTHREAD_LOG_LEVEL +#endif #define OPENTHREAD_CONFIG_LOG_CLI 1 #define OPENTHREAD_CONFIG_LOG_PKT_DUMP 1 diff --git a/components/openthread/src/esp_openthread_stubs.c b/components/openthread/src/esp_openthread_stubs.c new file mode 100644 index 0000000000..c129d04e85 --- /dev/null +++ b/components/openthread/src/esp_openthread_stubs.c @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +OT_TOOL_WEAK void otPlatUartReceived(const uint8_t *, uint16_t) +{ +} + +OT_TOOL_WEAK void otPlatUartSendDone(void) +{ +} + +OT_TOOL_WEAK void otPlatDiagRadioTransmitDone(otInstance *, otRadioFrame *, otError) +{ +} + +OT_TOOL_WEAK void otPlatDiagRadioReceiveDone(otInstance *, otRadioFrame *, otError) +{ +} + +OT_TOOL_WEAK void otPlatDiagAlarmFired(otInstance *) +{ +} diff --git a/components/partition_table/gen_extra_subtypes_inc.py b/components/partition_table/gen_extra_subtypes_inc.py index 1bc62734fb..45e4751a47 100755 --- a/components/partition_table/gen_extra_subtypes_inc.py +++ b/components/partition_table/gen_extra_subtypes_inc.py @@ -14,7 +14,7 @@ def gen_header_file(path: str, subtypes: str) -> None: f.write('/*\n\t' + PARTTOOL_USAGE + '\n\t') f.write('--extra-partition-subtypes ') for line_no in subtypes: - f.write(line_no + ' ') + f.write(f'"{line_no}" ') f.write('\n*/\n\n') f.write('#pragma once\n\n') for line_no in subtypes: diff --git a/components/partition_table/parttool.py b/components/partition_table/parttool.py index 847d4bc0a9..3c30d850cc 100755 --- a/components/partition_table/parttool.py +++ b/components/partition_table/parttool.py @@ -252,6 +252,7 @@ def main(): using the same fallback logic as the IDF bootloader', action='store_true') partition_selection_parser.add_argument('--partition-subtype', '-s', help='subtype of the partition') + partition_selection_parser.add_argument('--extra-partition-subtypes', help='Extra partition subtype entries', nargs='*') subparsers = parser.add_subparsers(dest='operation', help='run parttool -h for additional help') @@ -270,7 +271,6 @@ def main(): print_partition_info_subparser.add_argument('--info', help='type of partition information to get', choices=['name', 'type', 'subtype', 'offset', 'size', 'encrypted'], default=['offset', 'size'], nargs='+') print_partition_info_subparser.add_argument('--part_list', help='Get a list of partitions suitable for a given type', action='store_true') - print_partition_info_subparser.add_argument('--extra-partition-subtypes', help='Extra partition subtype entries', nargs='*') args = parser.parse_args() quiet = args.quiet diff --git a/components/perfmon/CMakeLists.txt b/components/perfmon/CMakeLists.txt index 670f1c912b..590ac8bed0 100644 --- a/components/perfmon/CMakeLists.txt +++ b/components/perfmon/CMakeLists.txt @@ -1,6 +1,7 @@ -idf_build_get_property(target IDF_TARGET) -if(${target} STREQUAL "esp32c3" OR ${target} STREQUAL "esp32h2" OR ${target} STREQUAL "esp32c2") - return() +idf_build_get_property(arch IDF_TARGET_ARCH) + +if(NOT "${arch}" STREQUAL "xtensa") + return() endif() set(xtensa_perfmon_srcs "xtensa_perfmon_access.c" diff --git a/components/protobuf-c/protobuf-c b/components/protobuf-c/protobuf-c index f224ab2eeb..abc67a11c6 160000 --- a/components/protobuf-c/protobuf-c +++ b/components/protobuf-c/protobuf-c @@ -1 +1 @@ -Subproject commit f224ab2eeb648a818eb20687d7150a285442c907 +Subproject commit abc67a11c6db271bedbb9f58be85d6f4e2ea8389 diff --git a/components/protocomm/Kconfig b/components/protocomm/Kconfig index d85a7336fe..312d10d679 100644 --- a/components/protocomm/Kconfig +++ b/components/protocomm/Kconfig @@ -20,7 +20,7 @@ menu "Protocomm" config ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2 bool "Support protocomm security version 2 (SRP6a-based key exchange + AES-GCM encryption/decryption)" - default n + default y help Enable support of security version 2. Disabling this option saves some code size. diff --git a/components/protocomm/include/common/protocomm.h b/components/protocomm/include/common/protocomm.h index e2704a3364..5056f78771 100644 --- a/components/protocomm/include/common/protocomm.h +++ b/components/protocomm/include/common/protocomm.h @@ -192,6 +192,8 @@ esp_err_t protocomm_req_handle(protocomm_t *pc, const char *ep_name, uint32_t se * For protocomm security version 1 and 2 * sec_params should contain pointer to struct of type * protocomm_security1_params_t and protocmm_security2_params_t respectively. + * The contents of this pointer must be valid till the security session + * has been running and is not closed. * @return * - ESP_OK : Success * - ESP_FAIL : Error adding endpoint / Endpoint with this name already exists diff --git a/components/protocomm/include/transports/protocomm_ble.h b/components/protocomm/include/transports/protocomm_ble.h index d684e7e921..0efb31c213 100644 --- a/components/protocomm/include/transports/protocomm_ble.h +++ b/components/protocomm/include/transports/protocomm_ble.h @@ -52,7 +52,7 @@ typedef struct protocomm_ble_config { /** * BLE device name being broadcast at the time of provisioning */ - char device_name[MAX_BLE_DEVNAME_LEN]; + char device_name[MAX_BLE_DEVNAME_LEN + 1]; /** * 128 bit UUID of the provisioning service diff --git a/components/protocomm/src/crypto/srp6a/esp_srp.c b/components/protocomm/src/crypto/srp6a/esp_srp.c index 79159bc41f..36fbc08342 100644 --- a/components/protocomm/src/crypto/srp6a/esp_srp.c +++ b/components/protocomm/src/crypto/srp6a/esp_srp.c @@ -388,7 +388,7 @@ error: return ESP_FAIL; } -esp_err_t esp_srp_get_session_key(esp_srp_handle_t *hd, char *bytes_A, int len_A, char **bytes_key, int *len_key) +esp_err_t esp_srp_get_session_key(esp_srp_handle_t *hd, char *bytes_A, int len_A, char **bytes_key, uint16_t *len_key) { esp_mpi_t *u = NULL; esp_mpi_t *vu = NULL; @@ -524,6 +524,7 @@ esp_err_t esp_srp_exchange_proofs(esp_srp_handle_t *hd, char *username, uint16_t ESP_LOG_BUFFER_HEX_LEVEL(TAG, (char *)digest, sizeof(digest), ESP_LOG_DEBUG); if (memcmp(bytes_user_proof, digest, SHA512_HASH_SZ) != 0) { + free(s); return ESP_FAIL; } diff --git a/components/protocomm/src/crypto/srp6a/esp_srp_mpi.c b/components/protocomm/src/crypto/srp6a/esp_srp_mpi.c index c02cbab000..2cb60e4ee9 100644 --- a/components/protocomm/src/crypto/srp6a/esp_srp_mpi.c +++ b/components/protocomm/src/crypto/srp6a/esp_srp_mpi.c @@ -26,6 +26,7 @@ esp_mpi_t *esp_mpi_new_from_hex(const char *hex) int ret = mbedtls_mpi_read_string(a, 16, hex); if (ret != 0) { printf("mbedtls_mpi_read_string() failed, returned %x\n", ret); + esp_mpi_free(a); return NULL; } return a; @@ -41,6 +42,7 @@ esp_mpi_t *esp_mpi_new_from_bin(const char *str, int str_len) int ret = mbedtls_mpi_read_binary(a, (unsigned char *)str, str_len); if (ret != 0) { printf("mbedtls_mpi_read_binary() failed, returned %x\n", ret); + esp_mpi_free(a); return NULL; } return a; @@ -81,6 +83,7 @@ char *esp_mpi_to_bin(esp_mpi_t *bn, int *len) int ret = mbedtls_mpi_write_binary(bn, (unsigned char *)p, *len); if (ret != 0) { printf("mbedtls_mpi_read_string() failed, returned %x\n", ret); + free(p); return NULL; } return p; diff --git a/components/protocomm/src/crypto/srp6a/include/esp_srp.h b/components/protocomm/src/crypto/srp6a/include/esp_srp.h index 388fab7acb..972704f038 100644 --- a/components/protocomm/src/crypto/srp6a/include/esp_srp.h +++ b/components/protocomm/src/crypto/srp6a/include/esp_srp.h @@ -88,7 +88,7 @@ esp_err_t esp_srp_srv_pubkey_from_salt_verifier(esp_srp_handle_t *hd, char **byt /* Returns bytes_key * *bytes_key MUST NOT BE FREED BY THE CALLER */ -esp_err_t esp_srp_get_session_key(esp_srp_handle_t *hd, char *bytes_A, int len_A, char **bytes_key, int *len_key); +esp_err_t esp_srp_get_session_key(esp_srp_handle_t *hd, char *bytes_A, int len_A, char **bytes_key, uint16_t *len_key); /* Exchange proofs * Returns 1 if user's proof is ok. Also 1 when is returned, bytes_host_proof contains our proof. diff --git a/components/protocomm/src/security/security1.c b/components/protocomm/src/security/security1.c index 316747b673..f530055fab 100644 --- a/components/protocomm/src/security/security1.c +++ b/components/protocomm/src/security/security1.c @@ -10,23 +10,18 @@ #include #include -/* ToDo - Remove this once appropriate solution is available. -We need to define this for the file as ssl_misc.h uses private structures from mbedtls, -which are undefined if the following flag is not defined */ -/* Many APIs in the file make use of this flag instead of `MBEDTLS_PRIVATE` */ -/* ToDo - Replace them with proper getter-setter once they are added */ -#define MBEDTLS_ALLOW_PRIVATE_ACCESS - -/* ToDo - Remove this once appropriate solution is available. - * Currently MBEDTLS_LEGACY_CONTEXT is enabled by default for MBEDTLS_ECP_RESTARTABLE +/* TODO: Currently MBEDTLS_ECDH_LEGACY_CONTEXT is enabled by default + * when MBEDTLS_ECP_RESTARTABLE is enabled. * This is a temporary workaround to allow that. - * The LEGACY option is soon going to be removed in future mbedtls - * once it is removed we can remove the workaround. + * + * The legacy option is soon going to be removed in future mbedtls + * versions and this workaround will be removed once the appropriate + * solution is available. */ #ifdef CONFIG_MBEDTLS_ECDH_LEGACY_CONTEXT -#define ACCESS_ECDH(S, var) S->var +#define ACCESS_ECDH(S, var) S->MBEDTLS_PRIVATE(var) #else -#define ACCESS_ECDH(S, var) S->ctx.mbed_ecdh.var +#define ACCESS_ECDH(S, var) S->MBEDTLS_PRIVATE(ctx).MBEDTLS_PRIVATE(mbed_ecdh).MBEDTLS_PRIVATE(var) #endif #include @@ -36,7 +31,6 @@ which are undefined if the following flag is not defined */ #include #include #include -#include #include #include @@ -249,7 +243,7 @@ static esp_err_t handle_session_command0(session_t *cur_session, goto exit_cmd0; } - mbed_err = mbedtls_mpi_write_binary(ACCESS_ECDH(&ctx_server, Q).X, + mbed_err = mbedtls_mpi_write_binary(ACCESS_ECDH(&ctx_server, Q).MBEDTLS_PRIVATE(X), cur_session->device_pubkey, PUBLIC_KEY_LEN); if (mbed_err != 0) { @@ -266,7 +260,7 @@ static esp_err_t handle_session_command0(session_t *cur_session, hexdump("Device pubkey", dev_pubkey, PUBLIC_KEY_LEN); hexdump("Client pubkey", cli_pubkey, PUBLIC_KEY_LEN); - mbed_err = mbedtls_mpi_lset(ACCESS_ECDH(&ctx_server, Qp).Z, 1); + mbed_err = mbedtls_mpi_lset(ACCESS_ECDH(&ctx_server, Qp).MBEDTLS_PRIVATE(Z), 1); if (mbed_err != 0) { ESP_LOGE(TAG, "Failed at mbedtls_mpi_lset with error code : -0x%x", -mbed_err); ret = ESP_FAIL; @@ -274,7 +268,7 @@ static esp_err_t handle_session_command0(session_t *cur_session, } flip_endian(cur_session->client_pubkey, PUBLIC_KEY_LEN); - mbed_err = mbedtls_mpi_read_binary(ACCESS_ECDH(&ctx_server, Qp).X, cli_pubkey, PUBLIC_KEY_LEN); + mbed_err = mbedtls_mpi_read_binary(ACCESS_ECDH(&ctx_server, Qp).MBEDTLS_PRIVATE(X), cli_pubkey, PUBLIC_KEY_LEN); flip_endian(cur_session->client_pubkey, PUBLIC_KEY_LEN); if (mbed_err != 0) { ESP_LOGE(TAG, "Failed at mbedtls_mpi_read_binary with error code : -0x%x", -mbed_err); diff --git a/components/protocomm/src/security/security2.c b/components/protocomm/src/security/security2.c index e13d2a7d09..19e33f8ee2 100644 --- a/components/protocomm/src/security/security2.c +++ b/components/protocomm/src/security/security2.c @@ -48,8 +48,6 @@ typedef struct session { uint16_t salt_len; char *verifier; uint16_t verifier_len; - char *client_pubkey; - uint16_t client_pubkey_len; char *session_key; uint16_t session_key_len; uint8_t iv[AES_GCM_IV_SIZE]; @@ -90,23 +88,16 @@ static esp_err_t handle_session_command0(session_t *cur_session, return ESP_ERR_INVALID_ARG; } - cur_session->username_len = in->sc0->client_username.len; - cur_session->username = calloc(cur_session->username_len, sizeof(char)); - if (!cur_session->username) { - ESP_LOGE(TAG, "Failed to allocate memory!"); - return ESP_ERR_NO_MEM; + if (sv == NULL) { + ESP_LOGE(TAG, "Invalid security params"); + return ESP_ERR_INVALID_ARG; } - memcpy(cur_session->username, in->sc0->client_username.data, in->sc0->client_username.len); - ESP_LOGD(TAG, "Username: %.*s", cur_session->username_len, cur_session->username); - cur_session->client_pubkey = calloc(PUBLIC_KEY_LEN, sizeof(char)); - if (!cur_session->client_pubkey ) { - ESP_LOGE(TAG, "Failed to allocate memory!"); - return ESP_ERR_NO_MEM; - } - memcpy(cur_session->client_pubkey, in->sc0->client_pubkey.data, PUBLIC_KEY_LEN); - cur_session->client_pubkey_len = PUBLIC_KEY_LEN; - hexdump("Client Public Key", cur_session->client_pubkey, PUBLIC_KEY_LEN); + + ESP_LOGD(TAG, "Username: %.*s", in->sc0->client_username.len, in->sc0->client_username.data); + + + hexdump("Client Public Key", (char *) in->sc0->client_pubkey.data, PUBLIC_KEY_LEN); /* Initialize mu srp context */ cur_session->srp_hd = calloc(1, sizeof(esp_srp_handle_t)); @@ -117,6 +108,7 @@ static esp_err_t handle_session_command0(session_t *cur_session, if (esp_srp_init(cur_session->srp_hd, ESP_NG_3072) != ESP_OK) { ESP_LOGE(TAG, "Failed to initialise security context!"); + free(cur_session->srp_hd); return ESP_FAIL; } @@ -129,31 +121,33 @@ static esp_err_t handle_session_command0(session_t *cur_session, cur_session->verifier_len = sv->verifier_len; ESP_LOGI(TAG, "Using salt and verifier to generate public key..."); - if (sv != NULL && sv->salt != NULL && sv->salt_len != 0 && sv->verifier != NULL && sv->verifier_len != 0) { + if (sv->salt != NULL && sv->salt_len != 0 && sv->verifier != NULL && sv->verifier_len != 0) { if (esp_srp_set_salt_verifier(cur_session->srp_hd, cur_session->salt, cur_session->salt_len, cur_session->verifier, cur_session->verifier_len) != ESP_OK) { ESP_LOGE(TAG, "Failed to set salt and verifier!"); + free(cur_session->srp_hd); return ESP_FAIL; } if (esp_srp_srv_pubkey_from_salt_verifier(cur_session->srp_hd, &device_pubkey, &device_pubkey_len) != ESP_OK) { ESP_LOGE(TAG, "Failed to device public key!"); + free(cur_session->srp_hd); return ESP_FAIL; } } hexdump("Device Public Key", device_pubkey, device_pubkey_len); - - if (esp_srp_get_session_key(cur_session->srp_hd, cur_session->client_pubkey, cur_session->client_pubkey_len, - &cur_session->session_key, (int *)&cur_session->session_key_len) != ESP_OK) { + if (esp_srp_get_session_key(cur_session->srp_hd, (char *) in->sc0->client_pubkey.data, PUBLIC_KEY_LEN, + &cur_session->session_key, &cur_session->session_key_len) != ESP_OK) { ESP_LOGE(TAG, "Failed to generate device session key!"); + free(cur_session->srp_hd); return ESP_FAIL; } hexdump("Session Key", cur_session->session_key, cur_session->session_key_len); - Sec2Payload *out = (Sec2Payload *) malloc(sizeof(Sec2Payload)); S2SessionResp0 *out_resp = (S2SessionResp0 *) malloc(sizeof(S2SessionResp0)); if (!out || !out_resp) { ESP_LOGE(TAG, "Error allocating memory for response0"); + free(cur_session->srp_hd); free(out); free(out_resp); return ESP_ERR_NO_MEM; @@ -178,6 +172,15 @@ static esp_err_t handle_session_command0(session_t *cur_session, resp->proto_case = SESSION_DATA__PROTO_SEC2; resp->sec2 = out; + cur_session->username_len = in->sc0->client_username.len; + cur_session->username = malloc(cur_session->username_len); + if (!cur_session->username) { + ESP_LOGE(TAG, "Failed to allocate memory!"); + free(cur_session->srp_hd); + return ESP_ERR_NO_MEM; + } + memcpy(cur_session->username, in->sc0->client_username.data, in->sc0->client_username.len); + cur_session->state = SESSION_STATE_CMD1; ESP_LOGD(TAG, "Session setup phase1 done"); @@ -209,6 +212,7 @@ static esp_err_t handle_session_command1(session_t *cur_session, if (esp_srp_exchange_proofs(cur_session->srp_hd, cur_session->username, cur_session->username_len, (char * ) in->sc1->client_proof.data, device_proof) != ESP_OK) { ESP_LOGE(TAG, "Failed to authenticate client proof!"); + free(device_proof); return ESP_FAIL; } hexdump("Device proof", device_proof, CLIENT_PROOF_LEN); @@ -225,6 +229,7 @@ static esp_err_t handle_session_command1(session_t *cur_session, mbed_err = mbedtls_gcm_setkey(&cur_session->ctx_gcm, MBEDTLS_CIPHER_ID_AES, (unsigned char *)cur_session->session_key, AES_GCM_KEY_LEN); if (mbed_err != 0) { ESP_LOGE(TAG, "Failure at mbedtls_gcm_setkey_enc with error code : -0x%x", -mbed_err); + free(device_proof); mbedtls_gcm_free(&cur_session->ctx_gcm); return ESP_FAIL; } @@ -233,6 +238,7 @@ static esp_err_t handle_session_command1(session_t *cur_session, S2SessionResp1 *out_resp = (S2SessionResp1 *) malloc(sizeof(S2SessionResp1)); if (!out || !out_resp) { ESP_LOGE(TAG, "Error allocating memory for response1"); + free(device_proof); free(out); free(out_resp); mbedtls_gcm_free(&cur_session->ctx_gcm); @@ -341,7 +347,6 @@ static esp_err_t sec2_close_session(protocomm_security_handle_t handle, uint32_t } free(cur_session->username); - free(cur_session->client_pubkey); if (cur_session->srp_hd) { esp_srp_free(cur_session->srp_hd); diff --git a/components/protocomm/test_apps/CMakeLists.txt b/components/protocomm/test_apps/CMakeLists.txt new file mode 100644 index 0000000000..a5df5df3af --- /dev/null +++ b/components/protocomm/test_apps/CMakeLists.txt @@ -0,0 +1,7 @@ +#This is the project CMakeLists.txt file for the test subproject +cmake_minimum_required(VERSION 3.16) + +set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components") + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(protocomm_test) diff --git a/components/protocomm/test_apps/README.md b/components/protocomm/test_apps/README.md new file mode 100644 index 0000000000..b5be4985c5 --- /dev/null +++ b/components/protocomm/test_apps/README.md @@ -0,0 +1,2 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | diff --git a/components/protocomm/test/CMakeLists.txt b/components/protocomm/test_apps/main/CMakeLists.txt similarity index 51% rename from components/protocomm/test/CMakeLists.txt rename to components/protocomm/test_apps/main/CMakeLists.txt index 1e618a976e..bf687e286b 100644 --- a/components/protocomm/test/CMakeLists.txt +++ b/components/protocomm/test_apps/main/CMakeLists.txt @@ -1,5 +1,4 @@ idf_component_register(SRC_DIRS "." PRIV_INCLUDE_DIRS "." - PRIV_INCLUDE_DIRS "../proto-c/" - PRIV_REQUIRES cmock mbedtls protocomm protobuf-c test_utils) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") + PRIV_INCLUDE_DIRS "../../proto-c/" + PRIV_REQUIRES cmock mbedtls protocomm protobuf-c test_utils unity) diff --git a/components/protocomm/test/test_protocomm.c b/components/protocomm/test_apps/main/test_protocomm.c similarity index 94% rename from components/protocomm/test/test_protocomm.c rename to components/protocomm/test_apps/main/test_protocomm.c index 8fab4d1181..7160d90817 100644 --- a/components/protocomm/test/test_protocomm.c +++ b/components/protocomm/test_apps/main/test_protocomm.c @@ -14,12 +14,19 @@ #include #include -/* ToDo - Remove this once appropriate solution is available. -We need to define this for the file as ssl_misc.h uses private structures from mbedtls, -which are undefined if the following flag is not defined */ -/* Many APIs in the file make use of this flag instead of `MBEDTLS_PRIVATE()` */ -/* ToDo - Replace them with proper getter-setter once they are added */ -#define MBEDTLS_ALLOW_PRIVATE_ACCESS +/* TODO: Currently MBEDTLS_ECDH_LEGACY_CONTEXT is enabled by default + * when MBEDTLS_ECP_RESTARTABLE is enabled. + * This is a temporary workaround to allow that. + * + * The legacy option is soon going to be removed in future mbedtls + * versions and this workaround will be removed once the appropriate + * solution is available. + */ +#ifdef CONFIG_MBEDTLS_ECDH_LEGACY_CONTEXT +#define ACCESS_ECDH(S, var) S.MBEDTLS_PRIVATE(var) +#else +#define ACCESS_ECDH(S, var) S.MBEDTLS_PRIVATE(ctx).MBEDTLS_PRIVATE(mbed_ecdh).MBEDTLS_PRIVATE(var) +#endif #include #include @@ -155,24 +162,24 @@ static esp_err_t verify_response0(session_t *session, SessionData *resp) hexdump("Device pubkey", dev_pubkey, PUBLIC_KEY_LEN); hexdump("Client pubkey", cli_pubkey, PUBLIC_KEY_LEN); - ret = mbedtls_mpi_lset(&session->ctx_client.ctx.mbed_ecdh.Qp.Z, 1); + ret = mbedtls_mpi_lset(ACCESS_ECDH(&session->ctx_client, Qp).MBEDTLS_PRIVATE(Z), 1); if (ret != 0) { ESP_LOGE(TAG, "Failed at mbedtls_mpi_lset with error code : %d", ret); return ESP_FAIL; } flip_endian(session->device_pubkey, PUBLIC_KEY_LEN); - ret = mbedtls_mpi_read_binary(&session->ctx_client.ctx.mbed_ecdh.Qp.X, dev_pubkey, PUBLIC_KEY_LEN); + ret = mbedtls_mpi_read_binary(ACCESS_ECDH(&session->ctx_client, Qp).MBEDTLS_PRIVATE(X), dev_pubkey, PUBLIC_KEY_LEN); flip_endian(session->device_pubkey, PUBLIC_KEY_LEN); if (ret != 0) { ESP_LOGE(TAG, "Failed at mbedtls_mpi_read_binary with error code : %d", ret); return ESP_FAIL; } - ret = mbedtls_ecdh_compute_shared(&session->ctx_client.ctx.mbed_ecdh.grp, - &session->ctx_client.ctx.mbed_ecdh.z, - &session->ctx_client.ctx.mbed_ecdh.Qp, - &session->ctx_client.ctx.mbed_ecdh.d, + ret = mbedtls_ecdh_compute_shared(ACCESS_ECDH(&session->ctx_client, grp), + ACCESS_ECDH(&session->ctx_client, z), + ACCESS_ECDH(&session->ctx_client, Qp), + ACCESS_ECDH(&session->ctx_client, d), mbedtls_ctr_drbg_random, &session->ctr_drbg); if (ret != 0) { @@ -180,7 +187,7 @@ static esp_err_t verify_response0(session_t *session, SessionData *resp) return ESP_FAIL; } - ret = mbedtls_mpi_write_binary(&session->ctx_client.ctx.mbed_ecdh.z, session->sym_key, PUBLIC_KEY_LEN); + ret = mbedtls_mpi_write_binary(ACCESS_ECDH(&session->ctx_client, z), session->sym_key, PUBLIC_KEY_LEN); if (ret != 0) { ESP_LOGE(TAG, "Failed at mbedtls_mpi_write_binary with error code : %d", ret); return ESP_FAIL; @@ -382,15 +389,15 @@ static esp_err_t test_sec_endpoint(session_t *session) goto abort_test_sec_endpoint; } - ret = mbedtls_ecp_group_load(&session->ctx_client.ctx.mbed_ecdh.grp, MBEDTLS_ECP_DP_CURVE25519); + ret = mbedtls_ecp_group_load(ACCESS_ECDH(&session->ctx_client, grp), MBEDTLS_ECP_DP_CURVE25519); if (ret != 0) { ESP_LOGE(TAG, "Failed at mbedtls_ecp_group_load with error code : %d", ret); goto abort_test_sec_endpoint; } - ret = mbedtls_ecdh_gen_public(&session->ctx_client.ctx.mbed_ecdh.grp, - &session->ctx_client.ctx.mbed_ecdh.d, - &session->ctx_client.ctx.mbed_ecdh.Q, + ret = mbedtls_ecdh_gen_public(ACCESS_ECDH(&session->ctx_client, grp), + ACCESS_ECDH(&session->ctx_client, d), + ACCESS_ECDH(&session->ctx_client, Q), mbedtls_ctr_drbg_random, &session->ctr_drbg); if (ret != 0) { @@ -400,7 +407,7 @@ static esp_err_t test_sec_endpoint(session_t *session) if (session->weak) { /* Read zero client public key */ - ret = mbedtls_mpi_read_binary(&session->ctx_client.ctx.mbed_ecdh.Q.X, + ret = mbedtls_mpi_read_binary(ACCESS_ECDH(&session->ctx_client, Q).MBEDTLS_PRIVATE(X), session->client_pubkey, PUBLIC_KEY_LEN); if (ret != 0) { @@ -408,7 +415,7 @@ static esp_err_t test_sec_endpoint(session_t *session) goto abort_test_sec_endpoint; } } - ret = mbedtls_mpi_write_binary(&session->ctx_client.ctx.mbed_ecdh.Q.X, + ret = mbedtls_mpi_write_binary(ACCESS_ECDH(&session->ctx_client, Q).MBEDTLS_PRIVATE(X), session->client_pubkey, PUBLIC_KEY_LEN); if (ret != 0) { @@ -557,7 +564,7 @@ static esp_err_t test_req_endpoint(session_t *session) // Check if the AES key is correctly set before calling the software encryption // API. Without this check, the code will crash, resulting in a test case failure. // For hardware AES, portability layer takes care of this. - if (session->ctx_aes.rk != NULL && session->ctx_aes.nr > 0) { + if (session->ctx_aes.MBEDTLS_PRIVATE(rk) != NULL && session->ctx_aes.MBEDTLS_PRIVATE(nr) > 0) { #endif mbedtls_aes_crypt_ctr(&session->ctx_aes, sizeof(rand_test_data), &session->nc_off, @@ -1183,3 +1190,8 @@ TEST_CASE("security 1 weak session test", "[PROTOCOMM]") { TEST_ASSERT(test_security1_weak_session() == ESP_OK); } + +void app_main(void) +{ + unity_run_menu(); +} diff --git a/components/protocomm/test_apps/pytest_protocomm_ut.py b/components/protocomm/test_apps/pytest_protocomm_ut.py new file mode 100644 index 0000000000..bedefba978 --- /dev/null +++ b/components/protocomm/test_apps/pytest_protocomm_ut.py @@ -0,0 +1,13 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +import pytest +from pytest_embedded import Dut + + +@pytest.mark.supported_targets +@pytest.mark.generic +def test_protocomm(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('*') + dut.expect_unity_test_output() diff --git a/components/protocomm/test_apps/sdkconfig.defaults b/components/protocomm/test_apps/sdkconfig.defaults new file mode 100644 index 0000000000..ec826a5a16 --- /dev/null +++ b/components/protocomm/test_apps/sdkconfig.defaults @@ -0,0 +1,9 @@ +# General options for additional checks +CONFIG_HEAP_POISONING_COMPREHENSIVE=y +CONFIG_COMPILER_WARN_WRITE_STRINGS=y +CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y +CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y +CONFIG_COMPILER_STACK_CHECK_MODE_STRONG=y +CONFIG_COMPILER_STACK_CHECK=y + +CONFIG_ESP_TASK_WDT=n diff --git a/components/pthread/CMakeLists.txt b/components/pthread/CMakeLists.txt index 1db395070e..e7336108c0 100644 --- a/components/pthread/CMakeLists.txt +++ b/components/pthread/CMakeLists.txt @@ -6,7 +6,7 @@ set(sources "pthread.c" idf_component_register(SRCS ${sources} INCLUDE_DIRS include) -idf_build_set_property(COMPILE_DEFINITIONS "-D_POSIX_READER_WRITER_LOCKS" APPEND) +idf_build_set_property(COMPILE_DEFINITIONS "_POSIX_READER_WRITER_LOCKS" APPEND) set(extra_link_flags "-u pthread_include_pthread_impl") list(APPEND extra_link_flags "-u pthread_include_pthread_cond_impl") diff --git a/components/pthread/test/CMakeLists.txt b/components/pthread/test/CMakeLists.txt deleted file mode 100644 index 17bc3e8954..0000000000 --- a/components/pthread/test/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -set(sources "test_pthread.c" - "test_pthread_cond_var.c" - "test_pthread_local_storage.c" - "test_pthread_cxx.cpp" - "test_pthread_rwlock.c") - -idf_component_register(SRCS ${sources} - PRIV_REQUIRES cmock test_utils pthread esp_timer) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/components/pthread/test_apps/pthread_unity_tests/CMakeLists.txt b/components/pthread/test_apps/pthread_unity_tests/CMakeLists.txt new file mode 100644 index 0000000000..510842cb6b --- /dev/null +++ b/components/pthread/test_apps/pthread_unity_tests/CMakeLists.txt @@ -0,0 +1,8 @@ +# The following lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components") + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(test_pthread) diff --git a/components/pthread/test_apps/pthread_unity_tests/README.md b/components/pthread/test_apps/pthread_unity_tests/README.md new file mode 100644 index 0000000000..b5be4985c5 --- /dev/null +++ b/components/pthread/test_apps/pthread_unity_tests/README.md @@ -0,0 +1,2 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | diff --git a/components/pthread/test_apps/pthread_unity_tests/main/CMakeLists.txt b/components/pthread/test_apps/pthread_unity_tests/main/CMakeLists.txt new file mode 100644 index 0000000000..80ad2a8722 --- /dev/null +++ b/components/pthread/test_apps/pthread_unity_tests/main/CMakeLists.txt @@ -0,0 +1,11 @@ +set(sources "test_app_main.c" + "test_pthread.c" + "test_pthread_cond_var.c" + "test_pthread_local_storage.c" + "test_pthread_cxx.cpp" + "test_pthread_rwlock.c") + +idf_component_register(SRCS ${sources} + INCLUDE_DIRS "." + REQUIRES pthread esp_timer test_utils + WHOLE_ARCHIVE) diff --git a/tools/test_apps/peripherals/usb/main/usb_test_main.c b/components/pthread/test_apps/pthread_unity_tests/main/test_app_main.c similarity index 76% rename from tools/test_apps/peripherals/usb/main/usb_test_main.c rename to components/pthread/test_apps/pthread_unity_tests/main/test_app_main.c index a902b52b4c..80036e7b9d 100644 --- a/tools/test_apps/peripherals/usb/main/usb_test_main.c +++ b/components/pthread/test_apps/pthread_unity_tests/main/test_app_main.c @@ -1,18 +1,20 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#include -#include #include "unity.h" +#include "unity_test_runner.h" #include "esp_heap_caps.h" + +// Some resources are lazy allocated (e.g. newlib locks), the threshold is left for that case +#define TEST_MEMORY_LEAK_THRESHOLD (-200) + static size_t before_free_8bit; static size_t before_free_32bit; -#define TEST_MEMORY_LEAK_THRESHOLD (-10000) // @todo MSC test are leaking memory static void check_leak(size_t before_free, size_t after_free, const char *type) { ssize_t delta = after_free - before_free; @@ -20,21 +22,14 @@ static void check_leak(size_t before_free, size_t after_free, const char *type) TEST_ASSERT_MESSAGE(delta >= TEST_MEMORY_LEAK_THRESHOLD, "memory leak"); } -void app_main(void) -{ - UNITY_BEGIN(); - unity_run_menu(); - UNITY_END(); -} - -/* setUp runs before every test */ void setUp(void) { before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); } -/* tearDown runs after every test */ + + void tearDown(void) { size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); @@ -42,3 +37,9 @@ void tearDown(void) check_leak(before_free_8bit, after_free_8bit, "8BIT"); check_leak(before_free_32bit, after_free_32bit, "32BIT"); } + +void app_main(void) +{ + printf("Running pthread component unity tests\n"); + unity_run_menu(); +} diff --git a/components/pthread/test/test_cxx_cond_var.cpp b/components/pthread/test_apps/pthread_unity_tests/main/test_cxx_cond_var.cpp similarity index 96% rename from components/pthread/test/test_cxx_cond_var.cpp rename to components/pthread/test_apps/pthread_unity_tests/main/test_cxx_cond_var.cpp index 0225f60710..18c1e2692b 100644 --- a/components/pthread/test/test_cxx_cond_var.cpp +++ b/components/pthread/test_apps/pthread_unity_tests/main/test_cxx_cond_var.cpp @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ #include #include #include diff --git a/components/pthread/test/test_cxx_std_future.cpp b/components/pthread/test_apps/pthread_unity_tests/main/test_cxx_std_future.cpp similarity index 87% rename from components/pthread/test/test_cxx_std_future.cpp rename to components/pthread/test_apps/pthread_unity_tests/main/test_cxx_std_future.cpp index 792ee89d41..58f4fcb0ba 100644 --- a/components/pthread/test/test_cxx_std_future.cpp +++ b/components/pthread/test_apps/pthread_unity_tests/main/test_cxx_std_future.cpp @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ #include #include #include diff --git a/components/pthread/test/test_pthread.c b/components/pthread/test_apps/pthread_unity_tests/main/test_pthread.c similarity index 98% rename from components/pthread/test/test_pthread.c rename to components/pthread/test_apps/pthread_unity_tests/main/test_pthread.c index f58bbf849a..675d4208b2 100644 --- a/components/pthread/test/test_pthread.c +++ b/components/pthread/test_apps/pthread_unity_tests/main/test_pthread.c @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ #include #include "freertos/FreeRTOS.h" diff --git a/components/pthread/test/test_pthread_cond_var.c b/components/pthread/test_apps/pthread_unity_tests/main/test_pthread_cond_var.c similarity index 95% rename from components/pthread/test/test_pthread_cond_var.c rename to components/pthread/test_apps/pthread_unity_tests/main/test_pthread_cond_var.c index 6cd18f5a61..00ad4d4f3a 100644 --- a/components/pthread/test/test_pthread_cond_var.c +++ b/components/pthread/test_apps/pthread_unity_tests/main/test_pthread_cond_var.c @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ #include #include "unity.h" diff --git a/components/pthread/test/test_pthread_cxx.cpp b/components/pthread/test_apps/pthread_unity_tests/main/test_pthread_cxx.cpp similarity index 95% rename from components/pthread/test/test_pthread_cxx.cpp rename to components/pthread/test_apps/pthread_unity_tests/main/test_pthread_cxx.cpp index f7131bbf74..27dabd5e00 100644 --- a/components/pthread/test/test_pthread_cxx.cpp +++ b/components/pthread/test_apps/pthread_unity_tests/main/test_pthread_cxx.cpp @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ #include #include #include @@ -135,5 +140,8 @@ TEST_CASE("pthread mix C/C++", "[pthread]") std::cout << "Join thread " << std::hex << t1.get_id() << std::endl; t1.join(); } + + /* Short delay to allow cleanup, avoid leaks */ + vTaskDelay(10); } #endif diff --git a/components/pthread/test/test_pthread_local_storage.c b/components/pthread/test_apps/pthread_unity_tests/main/test_pthread_local_storage.c similarity index 97% rename from components/pthread/test/test_pthread_local_storage.c rename to components/pthread/test_apps/pthread_unity_tests/main/test_pthread_local_storage.c index 1047f2f175..1ad96af5a5 100644 --- a/components/pthread/test/test_pthread_local_storage.c +++ b/components/pthread/test_apps/pthread_unity_tests/main/test_pthread_local_storage.c @@ -1,5 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ // Test pthread_create_key, pthread_delete_key, pthread_setspecific, pthread_getspecific #include +#include #include "unity.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" @@ -36,7 +42,7 @@ TEST_CASE("pthread local storage unique keys", "[pthread]") for (int i = 0; i < NUM_KEYS; i++) { TEST_ASSERT_EQUAL(0, pthread_key_create(&keys[i], NULL)); - printf("New key %d = %d\n", i, keys[i]); + printf("New key %d = %"PRIu32"\n", i, keys[i]); } for (int i = 0; i < NUM_KEYS; i++) { diff --git a/components/pthread/test/test_pthread_rwlock.c b/components/pthread/test_apps/pthread_unity_tests/main/test_pthread_rwlock.c similarity index 96% rename from components/pthread/test/test_pthread_rwlock.c rename to components/pthread/test_apps/pthread_unity_tests/main/test_pthread_rwlock.c index ce2a7a6330..06df0fcd8a 100644 --- a/components/pthread/test/test_pthread_rwlock.c +++ b/components/pthread/test_apps/pthread_unity_tests/main/test_pthread_rwlock.c @@ -1,13 +1,7 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: CC0 - * - * This example code is in the Public Domain (or CC0 licensed, at your option.) - * - * Unless required by applicable law or agreed to in writing, this - * software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR - * CONDITIONS OF ANY KIND, either express or implied. + * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ #include "sdkconfig.h" diff --git a/components/pthread/test_apps/pthread_unity_tests/pytest_pthread_unity_tests.py b/components/pthread/test_apps/pthread_unity_tests/pytest_pthread_unity_tests.py new file mode 100644 index 0000000000..85722ea21b --- /dev/null +++ b/components/pthread/test_apps/pthread_unity_tests/pytest_pthread_unity_tests.py @@ -0,0 +1,35 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +import pytest +from pytest_embedded import Dut + + +@pytest.mark.generic +@pytest.mark.supported_targets +@pytest.mark.parametrize( + 'config', + [ + 'default', + ], + indirect=True, +) +def test_pthread(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('*') + dut.expect_unity_test_output(timeout=300) + + +@pytest.mark.generic +@pytest.mark.parametrize( + 'config', + [ + pytest.param('single_core_esp32', marks=[pytest.mark.esp32]), + pytest.param('single_core_esp32s3', marks=[pytest.mark.esp32s3]), + ], + indirect=True, +) +def test_pthread_single_core(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('*') + dut.expect_unity_test_output(timeout=300) diff --git a/components/pthread/test_apps/pthread_unity_tests/sdkconfig.ci.default b/components/pthread/test_apps/pthread_unity_tests/sdkconfig.ci.default new file mode 100644 index 0000000000..e69de29bb2 diff --git a/components/pthread/test_apps/pthread_unity_tests/sdkconfig.ci.single_core_esp32 b/components/pthread/test_apps/pthread_unity_tests/sdkconfig.ci.single_core_esp32 new file mode 100644 index 0000000000..5262d9dafb --- /dev/null +++ b/components/pthread/test_apps/pthread_unity_tests/sdkconfig.ci.single_core_esp32 @@ -0,0 +1,2 @@ +CONFIG_IDF_TARGET="esp32" +CONFIG_FREERTOS_UNICORE=y diff --git a/components/pthread/test_apps/pthread_unity_tests/sdkconfig.ci.single_core_esp32s3 b/components/pthread/test_apps/pthread_unity_tests/sdkconfig.ci.single_core_esp32s3 new file mode 100644 index 0000000000..625306512f --- /dev/null +++ b/components/pthread/test_apps/pthread_unity_tests/sdkconfig.ci.single_core_esp32s3 @@ -0,0 +1,2 @@ +CONFIG_IDF_TARGET="esp32s3" +CONFIG_FREERTOS_UNICORE=y diff --git a/components/pthread/test_apps/pthread_unity_tests/sdkconfig.defaults b/components/pthread/test_apps/pthread_unity_tests/sdkconfig.defaults new file mode 100644 index 0000000000..7b19867521 --- /dev/null +++ b/components/pthread/test_apps/pthread_unity_tests/sdkconfig.defaults @@ -0,0 +1,2 @@ +# Some of the tests will starve the watchdog +CONFIG_ESP_TASK_WDT=n diff --git a/components/riscv/include/riscv/interrupt.h b/components/riscv/include/riscv/interrupt.h index e98115410d..c3b88084b9 100644 --- a/components/riscv/include/riscv/interrupt.h +++ b/components/riscv/include/riscv/interrupt.h @@ -115,7 +115,7 @@ int esprv_intc_int_get_priority(int rv_int_num); * * @param priority_threshold Interrupt priority threshold, 0 to 7 */ -void esprv_intc_set_threshold(int priority_threshold); +void esprv_intc_int_set_threshold(int priority_threshold); /** * @brief Get interrupt unmask diff --git a/components/riscv/include/riscv/riscv_interrupts.h b/components/riscv/include/riscv/riscv_interrupts.h deleted file mode 100644 index b3d225d58c..0000000000 --- a/components/riscv/include/riscv/riscv_interrupts.h +++ /dev/null @@ -1,45 +0,0 @@ -// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Enable CPU interrupt - * @param rv_int_num CPU interrupt number - */ -void riscv_interrupt_enable(int rv_int_num); - -/** - * Disable CPU interrupt - * @param rv_int_num CPU interrupt number - */ -void riscv_interrupt_disable(int rv_int_num); - -/** - * Globally enable CPU interrupts - */ -void riscv_global_interrupts_enable(void); - -/** - * Globally disable CPU interrupts - */ -void riscv_global_interrupts_disable(void); - -#ifdef __cplusplus -} -#endif diff --git a/components/riscv/include/riscv/rv_utils.h b/components/riscv/include/riscv/rv_utils.h index f0c2e5f8dd..cff0fa2786 100644 --- a/components/riscv/include/riscv/rv_utils.h +++ b/components/riscv/include/riscv/rv_utils.h @@ -10,7 +10,7 @@ #include "soc/soc_caps.h" #include "soc/assist_debug_reg.h" -#include "soc/interrupt_core0_reg.h" +#include "soc/interrupt_reg.h" #include "esp_attr.h" #include "riscv/csr.h" #include "riscv/interrupt.h" @@ -83,7 +83,7 @@ FORCE_INLINE_ATTR void rv_utils_set_mtvec(uint32_t mtvec_val) FORCE_INLINE_ATTR void rv_utils_intr_enable(uint32_t intr_mask) { - //Disable all interrupts to make updating of the interrupt mask atomic. + // Disable all interrupts to make updating of the interrupt mask atomic. unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE); esprv_intc_int_enable(intr_mask); RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE); @@ -91,7 +91,7 @@ FORCE_INLINE_ATTR void rv_utils_intr_enable(uint32_t intr_mask) FORCE_INLINE_ATTR void rv_utils_intr_disable(uint32_t intr_mask) { - //Disable all interrupts to make updating of the interrupt mask atomic. + // Disable all interrupts to make updating of the interrupt mask atomic. unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE); esprv_intc_int_disable(intr_mask); RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE); @@ -107,6 +107,16 @@ FORCE_INLINE_ATTR void rv_utils_intr_edge_ack(int intr_num) REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr_num); } +FORCE_INLINE_ATTR void rv_utils_intr_global_enable(void) +{ + RV_SET_CSR(mstatus, MSTATUS_MIE); +} + +FORCE_INLINE_ATTR void rv_utils_intr_global_disable(void) +{ + RV_CLEAR_CSR(mstatus, MSTATUS_MIE); +} + /* -------------------------------------------------- Memory Ports ----------------------------------------------------- * * ------------------------------------------------------------------------------------------------------------------ */ @@ -185,7 +195,9 @@ FORCE_INLINE_ATTR void rv_utils_dbgr_break(void) FORCE_INLINE_ATTR bool rv_utils_compare_and_set(volatile uint32_t *addr, uint32_t compare_value, uint32_t new_value) { - // Single core target has no atomic CAS instruction. We can achieve atomicity by disabling interrupts + // ESP32C6 starts to support atomic CAS instructions, but it is still a single core target, no need to implement + // through lr and sc instructions for now + // For an RV target has no atomic CAS instruction, we can achieve atomicity by disabling interrupts unsigned old_mstatus; old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE); // Compare and set diff --git a/components/riscv/interrupt.c b/components/riscv/interrupt.c index 24b4d5d033..5984d0d374 100644 --- a/components/riscv/interrupt.c +++ b/components/riscv/interrupt.c @@ -67,16 +67,6 @@ void intr_matrix_route(int intr_src, int intr_num) REG_WRITE(DR_REG_INTERRUPT_BASE + 4 * intr_src, intr_num); } -void riscv_global_interrupts_enable(void) -{ - RV_SET_CSR(mstatus, MSTATUS_MIE); -} - -void riscv_global_interrupts_disable(void) -{ - RV_CLEAR_CSR(mstatus, MSTATUS_MIE); -} - uint32_t esprv_intc_get_interrupt_unmask(void) { return REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG); diff --git a/components/riscv/vectors.S b/components/riscv/vectors.S index 9b868280db..56d0a2c85f 100644 --- a/components/riscv/vectors.S +++ b/components/riscv/vectors.S @@ -121,10 +121,10 @@ _vector_table: .option push .option norvc j _panic_handler /* exception handler, entry 0 */ - .rept (ETS_T1_WDT_INUM - 1) + .rept (ETS_INT_WDT_INUM - 1) j _interrupt_handler /* 24 identical entries, all pointing to the interrupt handler */ .endr - j _panic_handler /* Call panic handler for ETS_T1_WDT_INUM interrupt (soc-level panic)*/ + j _panic_handler /* Call panic handler for ETS_INT_WDT_INUM interrupt (soc-level panic)*/ j _panic_handler /* Call panic handler for ETS_CACHEERR_INUM interrupt (soc-level panic)*/ #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE j _panic_handler /* Call panic handler for ETS_MEMPROT_ERR_INUM interrupt (soc-level panic)*/ diff --git a/components/sdmmc/sdmmc_common.c b/components/sdmmc/sdmmc_common.c index 341a0f4a9c..302901b4c6 100644 --- a/components/sdmmc/sdmmc_common.c +++ b/components/sdmmc/sdmmc_common.c @@ -197,34 +197,18 @@ esp_err_t sdmmc_init_host_frequency(sdmmc_card_t* card) { assert(card->max_freq_khz <= card->host.max_freq_khz); - /* Find highest frequency in the following list, - * which is below card->max_freq_khz. - */ - const uint32_t freq_values[] = { - SDMMC_FREQ_52M, - SDMMC_FREQ_HIGHSPEED, - SDMMC_FREQ_26M, - SDMMC_FREQ_DEFAULT - //NOTE: in sdspi mode, 20MHz may not work. in that case, add 10MHz here. - }; - const int n_freq_values = sizeof(freq_values) / sizeof(freq_values[0]); - - uint32_t selected_freq = SDMMC_FREQ_PROBING; - for (int i = 0; i < n_freq_values; ++i) { - uint32_t freq = freq_values[i]; - if (card->max_freq_khz >= freq) { - selected_freq = freq; - break; - } - } - - ESP_LOGD(TAG, "%s: using %d kHz bus frequency", __func__, selected_freq); - if (selected_freq > SDMMC_FREQ_PROBING) { - esp_err_t err = (*card->host.set_card_clk)(card->host.slot, selected_freq); + if (card->max_freq_khz > SDMMC_FREQ_PROBING) { + esp_err_t err = (*card->host.set_card_clk)(card->host.slot, card->max_freq_khz); if (err != ESP_OK) { ESP_LOGE(TAG, "failed to switch bus frequency (0x%x)", err); return err; } + + err = (*card->host.get_real_freq)(card->host.slot, &(card->real_freq_khz)); + if (err != ESP_OK) { + ESP_LOGE(TAG, "failed to get real working frequency (0x%x)", err); + return err; + } } if (card->is_ddr) { @@ -258,7 +242,9 @@ void sdmmc_card_print_info(FILE* stream, const sdmmc_card_t* card) bool print_scr = false; bool print_csd = false; const char* type; + fprintf(stream, "Name: %s\n", card->cid.name); + if (card->is_sdio) { type = "SDIO"; print_scr = true; @@ -271,12 +257,17 @@ void sdmmc_card_print_info(FILE* stream, const sdmmc_card_t* card) print_csd = true; } fprintf(stream, "Type: %s\n", type); - if (card->max_freq_khz < 1000) { - fprintf(stream, "Speed: %d kHz\n", card->max_freq_khz); + + if (card->real_freq_khz == 0) { + fprintf(stream, "Speed: N/A\n"); } else { - fprintf(stream, "Speed: %d MHz%s\n", card->max_freq_khz / 1000, - card->is_ddr ? ", DDR" : ""); + const char *freq_unit = card->real_freq_khz < 1000 ? "kHz" : "MHz"; + const float freq = card->real_freq_khz < 1000 ? card->real_freq_khz : card->real_freq_khz / 1000.0; + const char *max_freq_unit = card->max_freq_khz < 1000 ? "kHz" : "MHz"; + const float max_freq = card->max_freq_khz < 1000 ? card->max_freq_khz : card->max_freq_khz / 1000.0; + fprintf(stream, "Speed: %.2f %s (limit: %.2f %s)%s\n", freq, freq_unit, max_freq, max_freq_unit, card->is_ddr ? ", DDR" : ""); } + fprintf(stream, "Size: %lluMB\n", ((uint64_t) card->csd.capacity) * card->csd.sector_size / (1024 * 1024)); if (print_csd) { diff --git a/components/sdmmc/sdmmc_sd.c b/components/sdmmc/sdmmc_sd.c index 15bc866357..5b33cb7e45 100644 --- a/components/sdmmc/sdmmc_sd.c +++ b/components/sdmmc/sdmmc_sd.c @@ -292,7 +292,7 @@ esp_err_t sdmmc_enable_hs_mode_and_check(sdmmc_card_t* card) return ESP_ERR_NOT_SUPPORTED; } - card->max_freq_khz = SDMMC_FREQ_HIGHSPEED; + card->max_freq_khz = MIN(card->host.max_freq_khz, SDMMC_FREQ_HIGHSPEED); return ESP_OK; } diff --git a/components/sdmmc/test/test_sd.c b/components/sdmmc/test/test_sd.c index 642ed37a3b..af990a8bee 100644 --- a/components/sdmmc/test/test_sd.c +++ b/components/sdmmc/test/test_sd.c @@ -132,6 +132,17 @@ static void probe_sd(int slot, int width, int freq_khz, int ddr) free(card); sd_test_board_power_off(); } + +extern void sdmmc_host_get_clk_dividers(const int freq_khz, int *host_div, int *card_div); + +static void sd_test_check_clk_dividers(const int freq_khz, const int expected_host_div, const int expected_card_div) +{ + printf(" %6d | %2d | %2d\n", freq_khz, expected_host_div, expected_card_div); + int host_divider, card_divider; + sdmmc_host_get_clk_dividers(freq_khz, &host_divider, &card_divider); + TEST_ASSERT_EQUAL(host_divider, expected_host_div); + TEST_ASSERT_EQUAL(card_divider, expected_card_div); +} #endif //WITH_SD_TEST || WITH_EMMC_TEST #if WITH_SD_TEST @@ -140,6 +151,8 @@ TEST_CASE("probe SD, slot 1, 4-bit", "[sd][test_env=UT_T1_SDMODE]") probe_sd(SDMMC_HOST_SLOT_1, 4, SDMMC_FREQ_PROBING, 0); probe_sd(SDMMC_HOST_SLOT_1, 4, SDMMC_FREQ_DEFAULT, 0); probe_sd(SDMMC_HOST_SLOT_1, 4, SDMMC_FREQ_HIGHSPEED, 0); + //custom frequency test + probe_sd(SDMMC_HOST_SLOT_1, 4, 10000, 0); } TEST_CASE("probe SD, slot 1, 1-bit", "[sd][test_env=UT_T1_SDMODE]") @@ -163,6 +176,21 @@ TEST_CASE("probe SD, slot 0, 1-bit", "[sd][ignore]") probe_sd(SDMMC_HOST_SLOT_0, 1, SDMMC_FREQ_DEFAULT, 0); probe_sd(SDMMC_HOST_SLOT_0, 1, SDMMC_FREQ_HIGHSPEED, 0); } + +TEST_CASE("SD clock dividers calculation", "[sd][test_env=UT_T1_SDMODE]") +{ + printf("Frequency (kHz) | Expected host.div | Expected card.div\n"); + sd_test_check_clk_dividers(SDMMC_FREQ_PROBING, 10, 20); + sd_test_check_clk_dividers(SDMMC_FREQ_DEFAULT, 8, 0); + sd_test_check_clk_dividers(SDMMC_FREQ_HIGHSPEED, 4, 0); + sd_test_check_clk_dividers(36000, 5, 0); + sd_test_check_clk_dividers(30000, 6, 0); + sd_test_check_clk_dividers(16000, 10, 0); + sd_test_check_clk_dividers(10000, 2, 4); + sd_test_check_clk_dividers(6000, 2, 7); + sd_test_check_clk_dividers(1000, 2, 40); + sd_test_check_clk_dividers(600, 2, 67); +} #endif //WITH_SD_TEST #if WITH_EMMC_TEST @@ -218,10 +246,11 @@ static void test_sdspi_deinit_bus(spi_host_device_t host) TEST_ESP_OK(err); } -static void probe_core(int slot) +static void probe_core(int slot, int freq_khz) { sdmmc_host_t config = SDSPI_HOST_DEFAULT(); config.slot = slot; + config.max_freq_khz = freq_khz; sdmmc_card_t* card = malloc(sizeof(sdmmc_card_t)); TEST_ASSERT_NOT_NULL(card); @@ -242,7 +271,7 @@ static void probe_spi(int freq_khz, int pin_miso, int pin_mosi, int pin_sck, int TEST_ESP_OK(sdspi_host_init()); TEST_ESP_OK(sdspi_host_init_device(&dev_config, &handle)); - probe_core(handle); + probe_core(handle, freq_khz); TEST_ESP_OK(sdspi_host_deinit()); test_sdspi_deinit_bus(dev_config.host_id); @@ -253,6 +282,8 @@ static void probe_spi(int freq_khz, int pin_miso, int pin_mosi, int pin_sck, int TEST_CASE("probe SD in SPI mode", "[sd][test_env=UT_T1_SPIMODE]") { probe_spi(SDMMC_FREQ_DEFAULT, SDSPI_TEST_MISO_PIN, SDSPI_TEST_MOSI_PIN, SDSPI_TEST_SCLK_PIN, SDSPI_TEST_CS_PIN); + //custom frequency test + probe_spi(10000, SDSPI_TEST_MISO_PIN, SDSPI_TEST_MOSI_PIN, SDSPI_TEST_SCLK_PIN, SDSPI_TEST_CS_PIN); } // No runner for this diff --git a/components/soc/esp32/gpio_periph.c b/components/soc/esp32/gpio_periph.c index 97b1cefad4..b2940e378f 100644 --- a/components/soc/esp32/gpio_periph.c +++ b/components/soc/esp32/gpio_periph.c @@ -5,6 +5,7 @@ */ #include "soc/gpio_periph.h" +#include "esp_attr.h" const uint32_t GPIO_PIN_MUX_REG[] = { IO_MUX_GPIO0_REG, @@ -49,6 +50,49 @@ const uint32_t GPIO_PIN_MUX_REG[] = { IO_MUX_GPIO39_REG, }; +DRAM_ATTR const uint8_t GPIO_PIN_MUX_REG_OFFSET[] = { + 0x44, + 0x88, + 0x40, + 0x84, + 0x48, + 0x6c, + 0x60, + 0x64, + 0x68, + 0x54, + 0x58, + 0x5c, + 0x34, + 0x38, + 0x30, + 0x3c, + 0x4c, + 0x50, + 0x70, + 0x74, + 0x78, + 0x7c, + 0x80, + 0x8c, + 0xFF, // 24 + 0x24, + 0x28, + 0x2c, + 0xFF, // 28 + 0xFF, // 29 + 0xFF, // 30 + 0xFF, // 31 + 0x1c, + 0x20, + 0x14, + 0x18, + 0x04, + 0x08, + 0x0c, + 0x10, +}; + _Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG"); const uint32_t GPIO_HOLD_MASK[] = { diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in index 03480b7cd9..d17400cf5e 100644 --- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in @@ -39,10 +39,6 @@ config SOC_BT_SUPPORTED bool default y -config SOC_CLASSIC_BT_SUPPORTED - bool - default y - config SOC_PCNT_SUPPORTED bool default y @@ -95,6 +91,14 @@ config SOC_SDM_SUPPORTED bool default y +config SOC_LEDC_SUPPORTED + bool + default y + +config SOC_I2C_SUPPORTED + bool + default y + config SOC_SUPPORT_COEXISTENCE bool default y @@ -211,6 +215,10 @@ config SOC_SHARED_IDCACHE_SUPPORTED bool default y +config SOC_MMU_LINEAR_ADDRESS_REGION_NUM + int + default 5 + config SOC_CPU_CORES_NUM int default 2 @@ -255,6 +263,10 @@ config SOC_GPIO_VALID_GPIO_MASK hex default 0xFFFFFFFFFF +config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK + hex + default 0xEF0FEA + config SOC_GPIO_SUPPORT_SLP_SWITCH bool default y @@ -527,6 +539,10 @@ config SOC_SPI_DMA_CHAN_NUM int default 2 +config SOC_SPI_MAX_CS_NUM + int + default 3 + config SOC_SPI_MAXIMUM_BUFFER_SIZE int default 64 @@ -599,6 +615,10 @@ config SOC_UART_NUM int default 3 +config SOC_UART_SUPPORT_APB_CLK + bool + default y + config SOC_UART_SUPPORT_REF_TICK bool default y @@ -699,10 +719,6 @@ config SOC_SDMMC_NUM_SLOTS int default 2 -config SOC_BLE_DONT_UPDATE_OWN_RPA - bool - default y - config SOC_WIFI_HW_TSF bool default n @@ -726,3 +742,15 @@ config SOC_WIFI_CSI_SUPPORT config SOC_WIFI_MESH_SUPPORT bool default y + +config SOC_BLE_SUPPORTED + bool + default y + +config SOC_BLE_MESH_SUPPORTED + bool + default y + +config SOC_BT_CLASSIC_SUPPORTED + bool + default y diff --git a/components/soc/esp32/include/soc/ext_mem_defs.h b/components/soc/esp32/include/soc/ext_mem_defs.h index 2b5d1e4bb2..e4ec354ac1 100644 --- a/components/soc/esp32/include/soc/ext_mem_defs.h +++ b/components/soc/esp32/include/soc/ext_mem_defs.h @@ -29,6 +29,7 @@ extern "C" { #define DROM0_CACHE_ADDRESS_HIGH 0x3F800000 +#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) #define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) #define ADDRESS_IN_IRAM1_CACHE(vaddr) ADDRESS_IN_BUS(IRAM1_CACHE, vaddr) @@ -36,10 +37,43 @@ extern "C" { #define ADDRESS_IN_DRAM1_CACHE(vaddr) ADDRESS_IN_BUS(DRAM1_CACHE, vaddr) #define ADDRESS_IN_DROM0_CACHE(vaddr) ADDRESS_IN_BUS(DROM0_CACHE, vaddr) -#define MMU_INVALID BIT(8) +#define MMU_INVALID BIT(8) + +//MMU entry num, 384 entries that are used in IDF +#define MMU_ENTRY_NUM 384 + + +#define SOC_MMU_DBUS_VADDR_BASE 0x3E000000 +#define SOC_MMU_IBUS_VADDR_BASE 0x40000000 + +/*------------------------------------------------------------------------------ + * MMU Linear Address + *----------------------------------------------------------------------------*/ +/** + * - 64KB MMU page size: the last 0xFFFF, which is the offset + * - 384 MMU entries, needs 0x1FF to hold it. + * + * Therefore, 0x1FF,FFFF + */ +#define SOC_MMU_LINEAR_ADDR_MASK 0x1FFFFFF + +#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) +#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) + +#define SOC_MMU_IRAM1_LINEAR_ADDRESS_LOW (IRAM1_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) +#define SOC_MMU_IRAM1_LINEAR_ADDRESS_HIGH (IRAM1_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) + +#define SOC_MMU_IROM0_LINEAR_ADDRESS_LOW (IROM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) +#define SOC_MMU_IROM0_LINEAR_ADDRESS_HIGH (IROM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) + +#define SOC_MMU_DROM0_LINEAR_ADDRESS_LOW (DROM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) +#define SOC_MMU_DROM0_LINEAR_ADDRESS_HIGH (DROM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) + +#define SOC_MMU_DRAM1_LINEAR_ADDRESS_LOW (DRAM1_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) +#define SOC_MMU_DRAM1_LINEAR_ADDRESS_HIGH (DRAM1_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) + + -//MMU entry num -#define MMU_ENTRY_NUM 256 #ifdef __cplusplus } diff --git a/components/soc/esp32/include/soc/rtc.h b/components/soc/esp32/include/soc/rtc.h index aa2b6f7fc9..9f927aee69 100644 --- a/components/soc/esp32/include/soc/rtc.h +++ b/components/soc/esp32/include/soc/rtc.h @@ -394,6 +394,11 @@ uint32_t rtc_clk_apb_freq_get(void); * 32k XTAL is being calibrated, but the oscillator has not started up (due to * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board). * + * @note When 32k CLK is being calibrated, this function will check the accuracy + * of the clock. Since the xtal 32k or ext osc 32k is generally very stable, if + * the check fails, then consider this an invalid 32k clock and return 0. This + * check can filter some jamming signal. + * * @param cal_clk clock to be measured * @param slow_clk_cycles number of slow clock cycles to average * @return average slow clock period in microseconds, Q13.19 fixed point format, diff --git a/components/soc/esp32/include/soc/soc.h b/components/soc/esp32/include/soc/soc.h index e7cb5f33e9..d0640ac6cf 100644 --- a/components/soc/esp32/include/soc/soc.h +++ b/components/soc/esp32/include/soc/soc.h @@ -403,3 +403,6 @@ //Invalid interrupt for number interrupt matrix #define ETS_INVALID_INUM 6 + +// Interrupt number for the Interrupt watchdog +#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM) diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index 3c284abc5e..d783231fdd 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -69,7 +69,6 @@ #define SOC_MCPWM_SUPPORTED 1 #define SOC_SDMMC_HOST_SUPPORTED 1 #define SOC_BT_SUPPORTED 1 -#define SOC_CLASSIC_BT_SUPPORTED 1 #define SOC_PCNT_SUPPORTED 1 #define SOC_WIFI_SUPPORTED 1 #define SOC_SDIO_SLAVE_SUPPORTED 1 @@ -83,6 +82,8 @@ #define SOC_I2S_SUPPORTED 1 #define SOC_RMT_SUPPORTED 1 #define SOC_SDM_SUPPORTED 1 +#define SOC_LEDC_SUPPORTED 1 +#define SOC_I2C_SUPPORTED 1 #define SOC_SUPPORT_COEXISTENCE 1 #define SOC_AES_SUPPORTED 1 #define SOC_MPI_SUPPORTED 1 @@ -131,8 +132,11 @@ #define SOC_BROWNOUT_RESET_SUPPORTED 1 #endif -/*-------------------------- CACHE CAPS --------------------------------------*/ + +/*-------------------------- CACHE/MMU CAPS ----------------------------------*/ #define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data +#define SOC_MMU_LINEAR_ADDRESS_REGION_NUM 5 + /*-------------------------- CPU CAPS ----------------------------------------*/ #define SOC_CPU_CORES_NUM 2 @@ -161,6 +165,9 @@ // GPIO >= 34 are input only #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT34 | BIT35 | BIT36 | BIT37 | BIT38 | BIT39)) +// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM: 1, 3, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19, 21, 22, 23) +#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0xEF0FEAULL + // Support to configure slept status #define SOC_GPIO_SUPPORT_SLP_SWITCH (1) @@ -264,6 +271,7 @@ #define SOC_SPI_DMA_CHAN_NUM 2 #define SOC_SPI_PERIPH_CS_NUM(i) 3 +#define SOC_SPI_MAX_CS_NUM 3 #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 #define SOC_SPI_MAX_PRE_DIVIDER 8192 @@ -306,6 +314,7 @@ /*-------------------------- UART CAPS ---------------------------------------*/ // ESP32 have 3 UART. #define SOC_UART_NUM (3) +#define SOC_UART_SUPPORT_APB_CLK (1) /*!< Support APB as the clock source */ #define SOC_UART_SUPPORT_REF_TICK (1) /*!< Support REF_TICK as the clock source */ #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ @@ -377,9 +386,6 @@ #define SOC_SDMMC_USE_IOMUX 1 #define SOC_SDMMC_NUM_SLOTS 2 -/*------------------------------ BLE --------------------------------------------*/ -#define SOC_BLE_DONT_UPDATE_OWN_RPA (1) - /*-------------------------- WI-FI HARDWARE CAPS -------------------------------*/ #define SOC_WIFI_HW_TSF (0) /*!< Hardware TSF is not supported */ #define SOC_WIFI_FTM_SUPPORT (0) /*!< FTM is not supported */ @@ -387,3 +393,8 @@ #define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */ #define SOC_WIFI_CSI_SUPPORT (1) /*!< Support CSI */ #define SOC_WIFI_MESH_SUPPORT (1) /*!< Support WIFI MESH */ + +/*---------------------------------- Bluetooth CAPS ----------------------------------*/ +#define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */ +#define SOC_BLE_MESH_SUPPORTED (1) /*!< Support BLE MESH */ +#define SOC_BT_CLASSIC_SUPPORTED (1) /*!< Support Bluetooth Classic hardware */ diff --git a/components/soc/esp32/interrupts.c b/components/soc/esp32/interrupts.c index ed23bbd42b..76b3032a19 100644 --- a/components/soc/esp32/interrupts.c +++ b/components/soc/esp32/interrupts.c @@ -1,16 +1,8 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include "soc/interrupts.h" @@ -60,7 +52,7 @@ const char * const esp_isr_names[ETS_MAX_INTR_SOURCE] = { [42] = "PWM3", [43] = "LEDC", [44] = "EFUSE", - [45] = "CAN", + [45] = "TWAI", [46] = "RTC_CORE", [47] = "RMT", [48] = "PCNT", diff --git a/components/soc/esp32/rtc_io_periph.c b/components/soc/esp32/rtc_io_periph.c index 4f4cd77b10..133fb738f2 100644 --- a/components/soc/esp32/rtc_io_periph.c +++ b/components/soc/esp32/rtc_io_periph.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/rtc_io_periph.h" +#include "soc/rtc_periph.h" const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = { RTCIO_GPIO0_CHANNEL, //GPIO0 diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in index d32f09d2c6..c2d20d1286 100644 --- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in @@ -19,10 +19,6 @@ config SOC_BT_SUPPORTED bool default y -config SOC_ESP_NIMBLE_CONTROLLER - bool - default y - config SOC_WIFI_SUPPORTED bool default y @@ -47,6 +43,14 @@ config SOC_TEMP_SENSOR_SUPPORTED bool default y +config SOC_LEDC_SUPPORTED + bool + default y + +config SOC_I2C_SUPPORTED + bool + default y + config SOC_SHA_SUPPORTED bool default y @@ -179,6 +183,10 @@ config SOC_CPU_IDRAM_SPLIT_USING_PMP bool default y +config SOC_MMU_PAGE_SIZE_CONFIGURABLE + bool + default y + config SOC_GDMA_GROUPS int default 1 @@ -215,6 +223,10 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK int default 0 +config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK + hex + default 0x00000000001FFFC0 + config SOC_GPIO_SUPPORT_SLP_SWITCH bool default y @@ -237,7 +249,7 @@ config SOC_I2C_NUM config SOC_I2C_FIFO_LEN int - default 32 + default 16 config SOC_I2C_SUPPORT_HW_CLR_BUS bool @@ -327,6 +339,10 @@ config SOC_SPI_PERIPH_NUM int default 2 +config SOC_SPI_MAX_CS_NUM + int + default 6 + config SOC_SPI_MAXIMUM_BUFFER_SIZE int default 64 @@ -499,6 +515,10 @@ config SOC_UART_SUPPORT_WAKEUP_INT bool default y +config SOC_UART_SUPPORT_PLL_F40M_CLK + bool + default y + config SOC_UART_SUPPORT_RTC_CLK bool default y @@ -535,10 +555,6 @@ config SOC_PM_SUPPORT_BT_WAKEUP bool default y -config SOC_MMU_PAGE_SIZE_CONFIGURABLE - bool - default y - config SOC_PM_SUPPORT_CPU_PD bool default n @@ -574,3 +590,15 @@ config SOC_WIFI_CSI_SUPPORT config SOC_WIFI_MESH_SUPPORT bool default n + +config SOC_BLE_SUPPORTED + bool + default y + +config SOC_BLE_MESH_SUPPORTED + bool + default n + +config SOC_ESP_NIMBLE_CONTROLLER + bool + default y diff --git a/components/soc/esp32c2/include/soc/clk_tree_defs.h b/components/soc/esp32c2/include/soc/clk_tree_defs.h index ac5e243457..dcae8277a6 100644 --- a/components/soc/esp32c2/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c2/include/soc/clk_tree_defs.h @@ -51,7 +51,7 @@ typedef enum { SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 17.5MHz RC oscillator */ SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */ SOC_ROOT_CLK_EXT_XTAL, /*!< External 26/40MHz crystal */ - SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin0 */ + SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin0, only support 32.768 KHz currently */ } soc_root_clk_t; /** diff --git a/components/soc/esp32c2/include/soc/io_mux_reg.h b/components/soc/esp32c2/include/soc/io_mux_reg.h index 4da0498397..b610a6e9dd 100644 --- a/components/soc/esp32c2/include/soc/io_mux_reg.h +++ b/components/soc/esp32c2/include/soc/io_mux_reg.h @@ -115,9 +115,6 @@ #define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) #define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) -#define U0RXD_GPIO_NUM 19 -#define U0TXD_GPIO_NUM 20 - #define SPI_HD_GPIO_NUM 12 #define SPI_WP_GPIO_NUM 13 #define SPI_CS0_GPIO_NUM 14 diff --git a/components/soc/esp32c2/include/soc/rtc.h b/components/soc/esp32c2/include/soc/rtc.h index 775c39cfbe..0b63443d55 100644 --- a/components/soc/esp32c2/include/soc/rtc.h +++ b/components/soc/esp32c2/include/soc/rtc.h @@ -90,7 +90,7 @@ extern "C" { #define RTC_CNTL_SCK_DCAP_DEFAULT 255 /* Various delays to be programmed into power control state machines */ -#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250) +#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (1000) #define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) #define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4) #define RTC_CNTL_WAKEUP_DELAY_CYCLES (5) @@ -153,7 +153,7 @@ typedef struct rtc_cpu_freq_config_s { typedef enum { RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256 - RTC_CAL_EXT_CLK = 2 //!< External CLK + RTC_CAL_EXT_32K = 2 //!< External 32.768 KHz CLK } rtc_cal_sel_t; /** @@ -179,7 +179,7 @@ typedef struct { .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \ .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \ .clk_rtc_clk_div = 0, \ - .clk_8m_clk_div = 0, \ + .clk_8m_clk_div = 1, \ .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \ } @@ -403,6 +403,11 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles); * 32k XTAL is being calibrated, but the oscillator has not started up (due to * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board). * + * @note When 32k CLK is being calibrated, this function will check the accuracy + * of the clock. Since the xtal 32k or ext osc 32k is generally very stable, if + * the check fails, then consider this an invalid 32k clock and return 0. This + * check can filter some jamming signal. + * * @param cal_clk clock to be measured * @param slow_clk_cycles number of slow clock cycles to average * @return average slow clock period in microseconds, Q13.19 fixed point format, diff --git a/components/soc/esp32c2/include/soc/soc.h b/components/soc/esp32c2/include/soc/soc.h index e7c9bdc5fc..e57de6148e 100644 --- a/components/soc/esp32c2/include/soc/soc.h +++ b/components/soc/esp32c2/include/soc/soc.h @@ -211,7 +211,7 @@ //CPU0 Interrupt number reserved in riscv/vector.S, not touch this. -#define ETS_T1_WDT_INUM 24 // Remove TODO: IDF-4246 +#define ETS_T0_WDT_INUM 24 #define ETS_CACHEERR_INUM 25 #define ETS_MEMPROT_ERR_INUM 26 #define ETS_DPORT_INUM 28 @@ -234,3 +234,6 @@ //Interrupt medium level, used for INT WDT for example #define SOC_INTERRUPT_LEVEL_MEDIUM 4 + +// Interrupt number for the Interrupt watchdog +#define ETS_INT_WDT_INUM (ETS_T0_WDT_INUM) diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h index 10259a7949..430720e17c 100644 --- a/components/soc/esp32c2/include/soc/soc_caps.h +++ b/components/soc/esp32c2/include/soc/soc_caps.h @@ -29,13 +29,14 @@ #define SOC_DEDICATED_GPIO_SUPPORTED 1 #define SOC_GDMA_SUPPORTED 1 #define SOC_BT_SUPPORTED 1 -#define SOC_ESP_NIMBLE_CONTROLLER 1 #define SOC_WIFI_SUPPORTED 1 #define SOC_ASYNC_MEMCPY_SUPPORTED 1 #define SOC_SUPPORTS_SECURE_DL_MODE 1 #define SOC_EFUSE_KEY_PURPOSE_FIELD 0 #define SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK 1 #define SOC_TEMP_SENSOR_SUPPORTED 1 +#define SOC_LEDC_SUPPORTED 1 +#define SOC_I2C_SUPPORTED 1 #define SOC_SHA_SUPPORTED 1 #define SOC_ECC_SUPPORTED 1 #define SOC_FLASH_ENC_SUPPORTED 1 @@ -89,6 +90,9 @@ #define SOC_CPU_IDRAM_SPLIT_USING_PMP 1 +/*-------------------------- MMU CAPS ----------------------------------------*/ +#define SOC_MMU_PAGE_SIZE_CONFIGURABLE (1) + /*-------------------------- GDMA CAPS -------------------------------------*/ #define SOC_GDMA_GROUPS (1U) // Number of GDMA groups #define SOC_GDMA_PAIRS_PER_GROUP (1U) // Number of GDMA pairs in each group @@ -111,6 +115,9 @@ #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5) +// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_20) +#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000001FFFC0ULL + // Support to configure sleep status #define SOC_GPIO_SUPPORT_SLP_SWITCH (1) @@ -123,7 +130,7 @@ // ESP32-C2 has 1 I2C #define SOC_I2C_NUM (1U) -#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */ +#define SOC_I2C_FIFO_LEN (16) /*!< I2C hardware FIFO depth */ // FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined. #define SOC_I2C_SUPPORT_HW_CLR_BUS (1) @@ -175,6 +182,7 @@ /*-------------------------- SPI CAPS ----------------------------------------*/ #define SOC_SPI_PERIPH_NUM 2 #define SOC_SPI_PERIPH_CS_NUM(i) 6 +#define SOC_SPI_MAX_CS_NUM 6 #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 @@ -241,8 +249,9 @@ #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ -#define SOC_UART_SUPPORT_RTC_CLK (1) -#define SOC_UART_SUPPORT_XTAL_CLK (1) +#define SOC_UART_SUPPORT_PLL_F40M_CLK (1) /*!< Support APB as the clock source */ +#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ +#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) @@ -259,15 +268,9 @@ /*-------------------------- Power Management CAPS ----------------------------*/ #define SOC_PM_SUPPORT_WIFI_WAKEUP (1) - #define SOC_PM_SUPPORT_BT_WAKEUP (1) - -/*-------------------------- MMU CAPS ----------------------------------------*/ -#define SOC_MMU_PAGE_SIZE_CONFIGURABLE (1) #define SOC_PM_SUPPORT_CPU_PD (0) - #define SOC_PM_SUPPORT_WIFI_PD (0) - #define SOC_PM_SUPPORT_BT_PD (0) /*------------------------------------ WI-FI CAPS ------------------------------------*/ @@ -277,3 +280,8 @@ #define SOC_WIFI_WAPI_SUPPORT (0) /*!< WAPI is not supported */ #define SOC_WIFI_CSI_SUPPORT (0) /*!< CSI is not supported */ #define SOC_WIFI_MESH_SUPPORT (0) /*!< WIFI MESH is not supported */ + +/*---------------------------------- Bluetooth CAPS ----------------------------------*/ +#define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */ +#define SOC_BLE_MESH_SUPPORTED (0) /*!< Support BLE MESH */ +#define SOC_ESP_NIMBLE_CONTROLLER (1) /*!< Support BLE EMBEDDED controller V1 */ diff --git a/components/soc/esp32c2/include/soc/system_reg.h b/components/soc/esp32c2/include/soc/system_reg.h index caf223db03..1b55d4246c 100644 --- a/components/soc/esp32c2/include/soc/system_reg.h +++ b/components/soc/esp32c2/include/soc/system_reg.h @@ -5,7 +5,6 @@ */ #pragma once -#include #include "soc/soc.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/esp32c2/include/soc/timer_group_struct.h b/components/soc/esp32c2/include/soc/timer_group_struct.h index 34cba27ee6..0cec799d5d 100644 --- a/components/soc/esp32c2/include/soc/timer_group_struct.h +++ b/components/soc/esp32c2/include/soc/timer_group_struct.h @@ -173,11 +173,7 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:12; - /** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0; - * WDT reset CPU enable. - */ - uint32_t wdt_appcpu_reset_en:1; + uint32_t reserved_0:13; /** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0; * WDT reset CPU enable. */ @@ -239,7 +235,7 @@ typedef union { uint32_t wdt_divcnt_rst:1; uint32_t reserved_1:15; /** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1; - * MWDT clock prescaler value. MWDT clock period = 12.5 ns * + * MWDT clock prescaler value. MWDT clock period = 25 ns * * TIMG_WDT_CLK_PRESCALE. */ uint32_t wdt_clk_prescale:16; diff --git a/components/soc/esp32c2/spi_periph.c b/components/soc/esp32c2/spi_periph.c index 0ac8169ea8..ce1c5c9af9 100644 --- a/components/soc/esp32c2/spi_periph.c +++ b/components/soc/esp32c2/spi_periph.c @@ -46,7 +46,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .spiq_in = FSPIQ_IN_IDX, .spiwp_in = FSPIWP_IN_IDX, .spihd_in = FSPIHD_IN_IDX, - .spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX}, + .spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX, FSPICS3_OUT_IDX, FSPICS4_OUT_IDX, FSPICS5_OUT_IDX}, .spics_in = FSPICS0_IN_IDX, .spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK, .spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI, diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in index cf719099f8..84578d3cc0 100644 --- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in @@ -75,6 +75,14 @@ config SOC_SDM_SUPPORTED bool default y +config SOC_LEDC_SUPPORTED + bool + default y + +config SOC_I2C_SUPPORTED + bool + default y + config SOC_SYSTIMER_SUPPORTED bool default y @@ -307,6 +315,10 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK int default 0 +config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK + hex + default 0x00000000003FFFC0 + config SOC_GPIO_SUPPORT_SLP_SWITCH bool default y @@ -355,6 +367,10 @@ config SOC_I2S_HW_VERSION_2 bool default y +config SOC_I2S_SUPPORTS_XTAL + bool + default y + config SOC_I2S_SUPPORTS_PCM bool default y @@ -531,6 +547,10 @@ config SOC_SPI_PERIPH_NUM int default 2 +config SOC_SPI_MAX_CS_NUM + int + default 6 + config SOC_SPI_MAXIMUM_BUFFER_SIZE int default 64 @@ -723,6 +743,10 @@ config SOC_UART_BITRATE_MAX int default 5000000 +config SOC_UART_SUPPORT_APB_CLK + bool + default y + config SOC_UART_SUPPORT_RTC_CLK bool default y @@ -810,3 +834,11 @@ config SOC_WIFI_CSI_SUPPORT config SOC_WIFI_MESH_SUPPORT bool default y + +config SOC_BLE_SUPPORTED + bool + default y + +config SOC_BLE_MESH_SUPPORTED + bool + default y diff --git a/components/soc/esp32c3/include/soc/clk_tree_defs.h b/components/soc/esp32c3/include/soc/clk_tree_defs.h index b6c88ee00f..c9203c587a 100644 --- a/components/soc/esp32c3/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c3/include/soc/clk_tree_defs.h @@ -206,7 +206,7 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of I2S */ -#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M} +#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} /** * @brief I2S clock source enum @@ -214,6 +214,7 @@ typedef enum { typedef enum { I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */ I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ + I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ } soc_periph_i2s_clk_src_t; /////////////////////////////////////////////////I2C//////////////////////////////////////////////////////////////////// diff --git a/components/soc/esp32c3/include/soc/hwcrypto_reg.h b/components/soc/esp32c3/include/soc/hwcrypto_reg.h index 474b07faa3..0e4ceb3000 100644 --- a/components/soc/esp32c3/include/soc/hwcrypto_reg.h +++ b/components/soc/esp32c3/include/soc/hwcrypto_reg.h @@ -1,16 +1,9 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. #ifndef __HWCRYPTO_REG_H__ #define __HWCRYPTO_REG_H__ @@ -113,11 +106,6 @@ #define AES_J_BASE ((DR_REG_AES_BASE) + 0x70) #define AES_T_BASE ((DR_REG_AES_BASE) + 0x80) -#define AES_INT_CLR_REG ((DR_REG_AES_BASE) + 0xAC) -#define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0) -#define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4) -#define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8) - /* AES_STATE_REG values */ #define AES_STATE_IDLE 0 #define AES_STATE_BUSY 1 diff --git a/components/soc/esp32c3/include/soc/i2s_struct.h b/components/soc/esp32c3/include/soc/i2s_struct.h index de550a6c58..8e27e2b702 100644 --- a/components/soc/esp32c3/include/soc/i2s_struct.h +++ b/components/soc/esp32c3/include/soc/i2s_struct.h @@ -140,7 +140,7 @@ typedef volatile struct i2s_dev_s { uint32_t rx_clkm_div_num: 8; /*Integral I2S clock divider value*/ uint32_t reserved8: 18; /*Reserved*/ uint32_t rx_clk_active: 1; /*I2S Rx module clock enable signal.*/ - uint32_t rx_clk_sel: 2; /*Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/ + uint32_t rx_clk_sel: 2; /*Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/ uint32_t mclk_sel: 1; /*0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT.*/ uint32_t reserved30: 2; /*Reserved*/ }; @@ -151,7 +151,7 @@ typedef volatile struct i2s_dev_s { uint32_t tx_clkm_div_num: 8; /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2 z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2 z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/ uint32_t reserved8: 18; /*Reserved*/ uint32_t tx_clk_active: 1; /*I2S Tx module clock enable signal.*/ - uint32_t tx_clk_sel: 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/ + uint32_t tx_clk_sel: 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/ uint32_t clk_en: 1; /*Set this bit to enable clk gate*/ uint32_t reserved30: 2; /*Reserved*/ }; diff --git a/components/soc/esp32c3/include/soc/rtc.h b/components/soc/esp32c3/include/soc/rtc.h index a570d8bb25..a52ee8b75d 100644 --- a/components/soc/esp32c3/include/soc/rtc.h +++ b/components/soc/esp32c3/include/soc/rtc.h @@ -430,6 +430,11 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles); * 32k XTAL is being calibrated, but the oscillator has not started up (due to * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board). * + * @note When 32k CLK is being calibrated, this function will check the accuracy + * of the clock. Since the xtal 32k or ext osc 32k is generally very stable, if + * the check fails, then consider this an invalid 32k clock and return 0. This + * check can filter some jamming signal. + * * @param cal_clk clock to be measured * @param slow_clk_cycles number of slow clock cycles to average * @return average slow clock period in microseconds, Q13.19 fixed point format, diff --git a/components/soc/esp32c3/include/soc/rtc_i2c_struct.h b/components/soc/esp32c3/include/soc/rtc_i2c_struct.h index 2f41b0f10f..6bac0548ee 100644 --- a/components/soc/esp32c3/include/soc/rtc_i2c_struct.h +++ b/components/soc/esp32c3/include/soc/rtc_i2c_struct.h @@ -165,7 +165,11 @@ typedef volatile struct rtc_i2c_dev_s { } fifo_data; union { struct { - uint32_t command0: 14; /*command0*/ + uint32_t byte_num: 8; + uint32_t ack_en: 1; + uint32_t ack_exp: 1; + uint32_t ack_val: 1; + uint32_t op_code: 3; uint32_t reserved14: 17; uint32_t done: 1; /*command0_done*/ }; diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index dc8be888d8..a16ce05da3 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -235,3 +235,6 @@ //Interrupt medium level, used for INT WDT for example #define SOC_INTERRUPT_LEVEL_MEDIUM 4 + +// Interrupt number for the Interrupt watchdog +#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM) diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index b69476162f..90dd288885 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -43,6 +43,8 @@ #define SOC_I2S_SUPPORTED 1 #define SOC_RMT_SUPPORTED 1 #define SOC_SDM_SUPPORTED 1 +#define SOC_LEDC_SUPPORTED 1 +#define SOC_I2C_SUPPORTED 1 #define SOC_SYSTIMER_SUPPORTED 1 #define SOC_SUPPORT_COEXISTENCE 1 #define SOC_AES_SUPPORTED 1 @@ -153,6 +155,9 @@ #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5) +// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_21) +#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000003FFFC0ULL + // Support to configure sleep status #define SOC_GPIO_SUPPORT_SLP_SWITCH (1) @@ -177,6 +182,7 @@ /*-------------------------- I2S CAPS ----------------------------------------*/ #define SOC_I2S_NUM (1) #define SOC_I2S_HW_VERSION_2 (1) +#define SOC_I2S_SUPPORTS_XTAL (1) #define SOC_I2S_SUPPORTS_PCM (1) #define SOC_I2S_SUPPORTS_PDM (1) #define SOC_I2S_SUPPORTS_PDM_TX (1) @@ -258,6 +264,7 @@ /*-------------------------- SPI CAPS ----------------------------------------*/ #define SOC_SPI_PERIPH_NUM 2 #define SOC_SPI_PERIPH_CS_NUM(i) 6 +#define SOC_SPI_MAX_CS_NUM 6 #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 @@ -334,8 +341,9 @@ #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ -#define SOC_UART_SUPPORT_RTC_CLK (1) -#define SOC_UART_SUPPORT_XTAL_CLK (1) +#define SOC_UART_SUPPORT_APB_CLK (1) /*!< Support APB as the clock source */ +#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ +#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ #define SOC_UART_REQUIRE_CORE_RESET (1) @@ -374,3 +382,7 @@ #define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */ #define SOC_WIFI_CSI_SUPPORT (1) /*!< Support CSI */ #define SOC_WIFI_MESH_SUPPORT (1) /*!< Support WIFI MESH */ + +/*---------------------------------- Bluetooth CAPS ----------------------------------*/ +#define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */ +#define SOC_BLE_MESH_SUPPORTED (1) /*!< Support BLE MESH */ diff --git a/components/soc/esp32c3/spi_periph.c b/components/soc/esp32c3/spi_periph.c index a7c656288b..ce1c5c9af9 100644 --- a/components/soc/esp32c3/spi_periph.c +++ b/components/soc/esp32c3/spi_periph.c @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include "soc/spi_periph.h" #include "stddef.h" @@ -54,7 +46,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .spiq_in = FSPIQ_IN_IDX, .spiwp_in = FSPIWP_IN_IDX, .spihd_in = FSPIHD_IN_IDX, - .spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX}, + .spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX, FSPICS3_OUT_IDX, FSPICS4_OUT_IDX, FSPICS5_OUT_IDX}, .spics_in = FSPICS0_IN_IDX, .spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK, .spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI, diff --git a/components/soc/esp32c6/CMakeLists.txt b/components/soc/esp32c6/CMakeLists.txt new file mode 100644 index 0000000000..762518d93f --- /dev/null +++ b/components/soc/esp32c6/CMakeLists.txt @@ -0,0 +1,29 @@ +set(srcs + "adc_periph.c" + "dedic_gpio_periph.c" + "gdma_periph.c" + "gpio_periph.c" + "sdm_periph.c" + "interrupts.c" + "spi_periph.c" + "ledc_periph.c" + "pcnt_periph.c" + "rmt_periph.c" + "i2s_periph.c" + "i2c_periph.c" + "uart_periph.c" + "temperature_sensor_periph.c" + "timer_periph.c") + +# ESP32C6-TODO +list(REMOVE_ITEM srcs + "adc_periph.c" # TODO: IDF-5310 + "ledc_periph.c" # TODO: IDF-5328 + "i2c_periph.c" # TODO: IDF-5326 + "temperature_sensor_periph.c" # TODO: IDF-5322 + ) + +add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}") + +target_sources(${COMPONENT_LIB} PRIVATE "${srcs}") +target_include_directories(${COMPONENT_LIB} PUBLIC . include) diff --git a/components/soc/esp32c6/adc_periph.c b/components/soc/esp32c6/adc_periph.c new file mode 100644 index 0000000000..54675d8b6d --- /dev/null +++ b/components/soc/esp32c6/adc_periph.c @@ -0,0 +1,19 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/adc_periph.h" + +/* Store IO number corresponding to the ADC channel number. */ +const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = { + /* ADC1 */ + { + ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM + }, + /* ADC2 */ + { + ADC2_CHANNEL_0_GPIO_NUM, -1, -1, -1, -1 + } +}; diff --git a/components/soc/esp32c6/dedic_gpio_periph.c b/components/soc/esp32c6/dedic_gpio_periph.c new file mode 100644 index 0000000000..1321608a3e --- /dev/null +++ b/components/soc/esp32c6/dedic_gpio_periph.c @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/gpio_sig_map.h" +#include "soc/dedic_gpio_periph.h" + +const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = { + .module = -1, + .irq = -1, + .cores = { + [0] = { + .in_sig_per_channel = { + [0] = CPU_GPIO_IN0_IDX, + [1] = CPU_GPIO_IN1_IDX, + [2] = CPU_GPIO_IN2_IDX, + [3] = CPU_GPIO_IN3_IDX, + [4] = CPU_GPIO_IN4_IDX, + [5] = CPU_GPIO_IN5_IDX, + [6] = CPU_GPIO_IN6_IDX, + [7] = CPU_GPIO_IN7_IDX, + }, + .out_sig_per_channel = { + [0] = CPU_GPIO_OUT0_IDX, + [1] = CPU_GPIO_OUT1_IDX, + [2] = CPU_GPIO_OUT2_IDX, + [3] = CPU_GPIO_OUT3_IDX, + [4] = CPU_GPIO_OUT4_IDX, + [5] = CPU_GPIO_OUT5_IDX, + [6] = CPU_GPIO_OUT6_IDX, + [7] = CPU_GPIO_OUT7_IDX, + } + }, + }, +}; diff --git a/components/soc/esp32c6/gdma_periph.c b/components/soc/esp32c6/gdma_periph.c new file mode 100644 index 0000000000..83fe4ddbb5 --- /dev/null +++ b/components/soc/esp32c6/gdma_periph.c @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/gdma_periph.h" + +const gdma_signal_conn_t gdma_periph_signals = { + .groups = { + [0] = { + .module = PERIPH_GDMA_MODULE, + .pairs = { + [0] = { + .rx_irq_id = ETS_DMA_IN_CH0_INTR_SOURCE, + .tx_irq_id = ETS_DMA_OUT_CH0_INTR_SOURCE, + }, + [1] = { + .rx_irq_id = ETS_DMA_IN_CH1_INTR_SOURCE, + .tx_irq_id = ETS_DMA_OUT_CH1_INTR_SOURCE, + }, + [2] = { + .rx_irq_id = ETS_DMA_IN_CH2_INTR_SOURCE, + .tx_irq_id = ETS_DMA_OUT_CH2_INTR_SOURCE, + } + } + } + } +}; diff --git a/components/soc/esp32c6/gpio_periph.c b/components/soc/esp32c6/gpio_periph.c new file mode 100644 index 0000000000..d04df9fc97 --- /dev/null +++ b/components/soc/esp32c6/gpio_periph.c @@ -0,0 +1,79 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/gpio_periph.h" + +const uint32_t GPIO_PIN_MUX_REG[] = { + IO_MUX_GPIO0_REG, + IO_MUX_GPIO1_REG, + IO_MUX_GPIO2_REG, + IO_MUX_GPIO3_REG, + IO_MUX_GPIO4_REG, + IO_MUX_GPIO5_REG, + IO_MUX_GPIO6_REG, + IO_MUX_GPIO7_REG, + IO_MUX_GPIO8_REG, + IO_MUX_GPIO9_REG, + IO_MUX_GPIO10_REG, + IO_MUX_GPIO11_REG, + IO_MUX_GPIO12_REG, + IO_MUX_GPIO13_REG, + IO_MUX_GPIO14_REG, + IO_MUX_GPIO15_REG, + IO_MUX_GPIO16_REG, + IO_MUX_GPIO17_REG, + IO_MUX_GPIO18_REG, + IO_MUX_GPIO19_REG, + IO_MUX_GPIO20_REG, + IO_MUX_GPIO21_REG, + IO_MUX_GPIO22_REG, + IO_MUX_GPIO23_REG, + IO_MUX_GPIO24_REG, + IO_MUX_GPIO25_REG, + IO_MUX_GPIO26_REG, + IO_MUX_GPIO27_REG, + IO_MUX_GPIO28_REG, + IO_MUX_GPIO29_REG, + IO_MUX_GPIO30_REG, +}; + +_Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG"); + +const uint32_t GPIO_HOLD_MASK[] = { + BIT(0), //GPIO0 // LP_AON_GPIO_HOLD0_REG + BIT(1), //GPIO1 + BIT(2), //GPIO2 + BIT(3), //GPIO3 + BIT(4), //GPIO4 + BIT(5), //GPIO5 + BIT(6), //GPIO6 + BIT(7), //GPIO7 + BIT(8), //GPIO8 + BIT(9), //GPIO9 + BIT(10), //GPIO10 + BIT(11), //GPIO11 + BIT(12), //GPIO12 + BIT(13), //GPIO13 + BIT(14), //GPIO14 + BIT(15), //GPIO15 + BIT(16), //GPIO16 + BIT(17), //GPIO17 + BIT(18), //GPIO18 + BIT(19), //GPIO19 + BIT(20), //GPIO20 + BIT(21), //GPIO21 + BIT(22), //GPIO22 + BIT(23), //GPIO23 + BIT(24), //GPIO24 + BIT(25), //GPIO25 + BIT(26), //GPIO26 + BIT(27), //GPIO27 + BIT(28), //GPIO28 + BIT(29), //GPIO29 + BIT(30), //GPIO30 +}; + +_Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK"); diff --git a/components/soc/esp32c6/i2c_periph.c b/components/soc/esp32c6/i2c_periph.c new file mode 100644 index 0000000000..95a1a0fe16 --- /dev/null +++ b/components/soc/esp32c6/i2c_periph.c @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/i2c_periph.h" +#include "soc/gpio_sig_map.h" + +/* + Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = { + { + .sda_out_sig = I2CEXT0_SDA_OUT_IDX, + .sda_in_sig = I2CEXT0_SDA_IN_IDX, + .scl_out_sig = I2CEXT0_SCL_OUT_IDX, + .scl_in_sig = I2CEXT0_SCL_IN_IDX, + .irq = ETS_I2C_EXT0_INTR_SOURCE, + .module = PERIPH_I2C0_MODULE, + }, +}; diff --git a/components/soc/esp32c6/i2s_periph.c b/components/soc/esp32c6/i2s_periph.c new file mode 100644 index 0000000000..53417594ce --- /dev/null +++ b/components/soc/esp32c6/i2s_periph.c @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/i2s_periph.h" +#include "soc/gpio_sig_map.h" + +/* + Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = { + { + .mck_out_sig = I2S_MCLK_OUT_IDX, + + .m_tx_bck_sig = I2SO_BCK_OUT_IDX, + .m_rx_bck_sig = I2SI_BCK_OUT_IDX, + .m_tx_ws_sig = I2SO_WS_OUT_IDX, + .m_rx_ws_sig = I2SI_WS_OUT_IDX, + + .s_tx_bck_sig = I2SO_BCK_IN_IDX, + .s_rx_bck_sig = I2SI_BCK_IN_IDX, + .s_tx_ws_sig = I2SO_WS_IN_IDX, + .s_rx_ws_sig = I2SI_WS_IN_IDX, + + .data_out_sig = I2SO_SD_OUT_IDX, + .data_in_sig = I2SI_SD_IN_IDX, + + .irq = -1, + .module = PERIPH_I2S1_MODULE, + } +}; diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in new file mode 100644 index 0000000000..73d0666948 --- /dev/null +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -0,0 +1,780 @@ +##################################################### +# This file is auto-generated from SoC caps +# using gen_soc_caps_kconfig.py, do not edit manually +##################################################### + +config SOC_DEDICATED_GPIO_SUPPORTED + bool + default y + +config SOC_GDMA_SUPPORTED + bool + default y + +config SOC_PCNT_SUPPORTED + bool + default y + +config SOC_BT_SUPPORTED + bool + default y + +config SOC_ASYNC_MEMCPY_SUPPORTED + bool + default y + +config SOC_USB_SERIAL_JTAG_SUPPORTED + bool + default y + +config SOC_SUPPORTS_SECURE_DL_MODE + bool + default y + +config SOC_EFUSE_KEY_PURPOSE_FIELD + bool + default y + +config SOC_RTC_FAST_MEM_SUPPORTED + bool + default y + +config SOC_RTC_MEM_SUPPORTED + bool + default y + +config SOC_I2S_SUPPORTED + bool + default y + +config SOC_RMT_SUPPORTED + bool + default y + +config SOC_SDM_SUPPORTED + bool + default y + +config SOC_SYSTIMER_SUPPORTED + bool + default y + +config SOC_SUPPORT_COEXISTENCE + bool + default y + +config SOC_FLASH_ENC_SUPPORTED + bool + default y + +config SOC_SECURE_BOOT_SUPPORTED + bool + default y + +config SOC_XTAL_SUPPORT_40M + bool + default y + +config SOC_AES_SUPPORT_DMA + bool + default y + +config SOC_AES_GDMA + bool + default y + +config SOC_AES_SUPPORT_AES_128 + bool + default y + +config SOC_AES_SUPPORT_AES_256 + bool + default y + +config SOC_ADC_DIG_CTRL_SUPPORTED + bool + default y + +config SOC_ADC_ARBITER_SUPPORTED + bool + default y + +config SOC_ADC_FILTER_SUPPORTED + bool + default y + +config SOC_ADC_MONITOR_SUPPORTED + bool + default y + +config SOC_ADC_PERIPH_NUM + int + default 2 + +config SOC_ADC_MAX_CHANNEL_NUM + int + default 5 + +config SOC_ADC_ATTEN_NUM + int + default 4 + +config SOC_ADC_DIGI_CONTROLLER_NUM + int + default 1 + +config SOC_ADC_PATT_LEN_MAX + int + default 8 + +config SOC_ADC_DIGI_MAX_BITWIDTH + int + default 12 + +config SOC_ADC_DIGI_FILTER_NUM + int + default 2 + +config SOC_ADC_DIGI_MONITOR_NUM + int + default 2 + +config SOC_ADC_SAMPLE_FREQ_THRES_HIGH + int + default 83333 + +config SOC_ADC_SAMPLE_FREQ_THRES_LOW + int + default 611 + +config SOC_ADC_RTC_MIN_BITWIDTH + int + default 12 + +config SOC_ADC_RTC_MAX_BITWIDTH + int + default 12 + +config SOC_ADC_CALIBRATION_V1_SUPPORTED + bool + default n + +config SOC_APB_BACKUP_DMA + bool + default n + +config SOC_BROWNOUT_RESET_SUPPORTED + bool + default y + +config SOC_SHARED_IDCACHE_SUPPORTED + bool + default y + +config SOC_CPU_CORES_NUM + int + default 1 + +config SOC_CPU_INTR_NUM + int + default 32 + +config SOC_CPU_HAS_FLEXIBLE_INTC + bool + default y + +config SOC_INT_PLIC_SUPPORTED + bool + default y + +config SOC_CPU_BREAKPOINTS_NUM + int + default 4 + +config SOC_CPU_WATCHPOINTS_NUM + int + default 4 + +config SOC_CPU_WATCHPOINT_SIZE + hex + default 0x80000000 + +config SOC_MMU_PAGE_SIZE_CONFIGURABLE + bool + default y + +config SOC_DS_SIGNATURE_MAX_BIT_LEN + int + default 3072 + +config SOC_DS_KEY_PARAM_MD_IV_LENGTH + int + default 16 + +config SOC_DS_KEY_CHECK_MAX_WAIT_US + int + default 1100 + +config SOC_GDMA_GROUPS + int + default 1 + +config SOC_GDMA_PAIRS_PER_GROUP + int + default 3 + +config SOC_GPIO_PORT + int + default 1 + +config SOC_GPIO_PIN_COUNT + int + default 31 + +config SOC_GPIO_SUPPORTS_RTC_INDEPENDENT + bool + default y + +config SOC_GPIO_SUPPORT_FORCE_HOLD + bool + default y + +config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP + bool + default y + +config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK + int + default 0 + +config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK + hex + default 0x000000007FFFFF00 + +config SOC_GPIO_SUPPORT_SLP_SWITCH + bool + default y + +config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM + int + default 8 + +config SOC_DEDIC_GPIO_IN_CHANNELS_NUM + int + default 8 + +config SOC_DEDIC_PERIPH_ALWAYS_ENABLE + bool + default y + +config SOC_I2C_NUM + int + default 1 + +config SOC_I2C_FIFO_LEN + int + default 32 + +config SOC_I2C_SUPPORT_SLAVE + bool + default y + +config SOC_I2C_SUPPORT_HW_CLR_BUS + bool + default y + +config SOC_I2C_SUPPORT_XTAL + bool + default y + +config SOC_I2C_SUPPORT_RTC + bool + default y + +config SOC_I2S_NUM + bool + default y + +config SOC_I2S_HW_VERSION_2 + bool + default y + +config SOC_I2S_SUPPORTS_XTAL + bool + default y + +config SOC_I2S_SUPPORTS_PCM + bool + default y + +config SOC_I2S_SUPPORTS_PDM + bool + default y + +config SOC_I2S_SUPPORTS_PDM_TX + bool + default y + +config SOC_I2S_SUPPORTS_PDM_CODEC + bool + default y + +config SOC_I2S_SUPPORTS_TDM + bool + default y + +config SOC_LEDC_SUPPORT_APB_CLOCK + bool + default y + +config SOC_LEDC_SUPPORT_XTAL_CLOCK + bool + default y + +config SOC_LEDC_CHANNEL_NUM + int + default 6 + +config SOC_LEDC_TIMER_BIT_WIDE_NUM + int + default 14 + +config SOC_LEDC_SUPPORT_FADE_STOP + bool + default y + +config SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED + bool + default n + +config SOC_MPU_MIN_REGION_SIZE + hex + default 0x20000000 + +config SOC_MPU_REGIONS_MAX_NUM + int + default 8 + +config SOC_MPU_REGION_RO_SUPPORTED + bool + default n + +config SOC_MPU_REGION_WO_SUPPORTED + bool + default n + +config SOC_PCNT_GROUPS + int + default 1 + +config SOC_PCNT_UNITS_PER_GROUP + int + default 4 + +config SOC_PCNT_CHANNELS_PER_UNIT + int + default 2 + +config SOC_PCNT_THRES_POINT_PER_UNIT + int + default 2 + +config SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE + bool + default y + +config SOC_RMT_GROUPS + int + default 1 + +config SOC_RMT_TX_CANDIDATES_PER_GROUP + int + default 2 + +config SOC_RMT_RX_CANDIDATES_PER_GROUP + int + default 2 + +config SOC_RMT_CHANNELS_PER_GROUP + int + default 4 + +config SOC_RMT_MEM_WORDS_PER_CHANNEL + int + default 48 + +config SOC_RMT_SUPPORT_RX_PINGPONG + bool + default y + +config SOC_RMT_SUPPORT_RX_DEMODULATION + bool + default y + +config SOC_RMT_SUPPORT_TX_ASYNC_STOP + bool + default y + +config SOC_RMT_SUPPORT_TX_LOOP_COUNT + bool + default y + +config SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP + bool + default y + +config SOC_RMT_SUPPORT_TX_SYNCHRO + bool + default y + +config SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY + bool + default y + +config SOC_RMT_SUPPORT_XTAL + bool + default y + +config SOC_RMT_SUPPORT_APB + bool + default y + +config SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH + int + default 128 + +config SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM + int + default 108 + +config SOC_RTCIO_PIN_COUNT + int + default 0 + +config SOC_RSA_MAX_BIT_LEN + int + default 3072 + +config SOC_SHA_DMA_MAX_BUFFER_SIZE + int + default 3968 + +config SOC_SHA_SUPPORT_DMA + bool + default y + +config SOC_SHA_SUPPORT_RESUME + bool + default y + +config SOC_SHA_GDMA + bool + default y + +config SOC_SHA_SUPPORT_SHA1 + bool + default y + +config SOC_SHA_SUPPORT_SHA224 + bool + default y + +config SOC_SHA_SUPPORT_SHA256 + bool + default y + +config SOC_SDM_GROUPS + int + default 1 + +config SOC_SDM_CHANNELS_PER_GROUP + int + default 4 + +config SOC_SPI_PERIPH_NUM + int + default 2 + +config SOC_SPI_MAX_CS_NUM + int + default 6 + +config SOC_SPI_MAXIMUM_BUFFER_SIZE + int + default 64 + +config SOC_SPI_SUPPORT_DDRCLK + bool + default y + +config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS + bool + default y + +config SOC_SPI_SUPPORT_CD_SIG + bool + default y + +config SOC_SPI_SUPPORT_CONTINUOUS_TRANS + bool + default y + +config SOC_SPI_SUPPORT_SLAVE_HD_VER2 + bool + default y + +config SOC_MEMSPI_IS_INDEPENDENT + bool + default y + +config SOC_SPI_MAX_PRE_DIVIDER + int + default 16 + +config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE + bool + default y + +config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND + bool + default y + +config SOC_SPI_MEM_SUPPORT_AUTO_RESUME + bool + default y + +config SOC_SPI_MEM_SUPPORT_IDLE_INTR + bool + default y + +config SOC_SPI_MEM_SUPPORT_SW_SUSPEND + bool + default y + +config SOC_SPI_MEM_SUPPORT_CHECK_SUS + bool + default y + +config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED + bool + default y + +config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED + bool + default y + +config SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED + bool + default y + +config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED + bool + default y + +config SOC_SYSTIMER_COUNTER_NUM + int + default 2 + +config SOC_SYSTIMER_ALARM_NUM + int + default 3 + +config SOC_SYSTIMER_BIT_WIDTH_LO + int + default 32 + +config SOC_SYSTIMER_BIT_WIDTH_HI + int + default 20 + +config SOC_SYSTIMER_FIXED_DIVIDER + bool + default y + +config SOC_SYSTIMER_INT_LEVEL + bool + default y + +config SOC_SYSTIMER_ALARM_MISS_COMPENSATE + bool + default y + +config SOC_TIMER_GROUPS + int + default 2 + +config SOC_TIMER_GROUP_TIMERS_PER_GROUP + int + default 1 + +config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH + int + default 54 + +config SOC_TIMER_GROUP_SUPPORT_XTAL + bool + default y + +config SOC_TIMER_GROUP_SUPPORT_APB + bool + default y + +config SOC_TIMER_GROUP_TOTAL_TIMERS + int + default 2 + +config SOC_TIMER_SUPPORT_ETM + bool + default y + +config SOC_TWAI_BRP_MIN + int + default 2 + +config SOC_TWAI_BRP_MAX + int + default 16384 + +config SOC_TWAI_SUPPORTS_RX_STATUS + bool + default y + +config SOC_SECURE_BOOT_V2_RSA + bool + default y + +config SOC_SECURE_BOOT_V2_ECC + bool + default y + +config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS + int + default 3 + +config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS + bool + default y + +config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY + bool + default y + +config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX + int + default 32 + +config SOC_FLASH_ENCRYPTION_XTS_AES + bool + default y + +config SOC_FLASH_ENCRYPTION_XTS_AES_128 + bool + default y + +config SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE + int + default 16 + +config SOC_MEMPROT_MEM_ALIGN_SIZE + int + default 512 + +config SOC_UART_NUM + int + default 2 + +config SOC_UART_FIFO_LEN + int + default 128 + +config SOC_UART_BITRATE_MAX + int + default 5000000 + +config SOC_UART_SUPPORT_APB_CLK + bool + default y + +config SOC_UART_SUPPORT_RTC_CLK + bool + default n + +config SOC_UART_SUPPORT_XTAL_CLK + bool + default y + +config SOC_UART_REQUIRE_CORE_RESET + bool + default y + +config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND + bool + default y + +config SOC_COEX_HW_PTI + bool + default y + +config SOC_PHY_DIG_REGS_MEM_SIZE + int + default 21 + +config SOC_MAC_BB_PD_MEM_SIZE + int + default 192 + +config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH + int + default 12 + +config SOC_PM_SUPPORT_WIFI_WAKEUP + bool + default y + +config SOC_PM_SUPPORT_BT_WAKEUP + bool + default y + +config SOC_PM_SUPPORT_CPU_PD + bool + default y + +config SOC_PM_SUPPORT_WIFI_PD + bool + default y + +config SOC_PM_SUPPORT_BT_PD + bool + default y + +config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC + bool + default y + +config SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL + bool + default y + +config SOC_WIFI_HW_TSF + bool + default y + +config SOC_WIFI_FTM_SUPPORT + bool + default y + +config SOC_WIFI_GCMP_SUPPORT + bool + default y + +config SOC_WIFI_WAPI_SUPPORT + bool + default y + +config SOC_WIFI_CSI_SUPPORT + bool + default y + +config SOC_WIFI_MESH_SUPPORT + bool + default y diff --git a/components/soc/esp32c6/include/soc/adc_channel.h b/components/soc/esp32c6/include/soc/adc_channel.h new file mode 100644 index 0000000000..194e7bdd99 --- /dev/null +++ b/components/soc/esp32c6/include/soc/adc_channel.h @@ -0,0 +1,25 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define ADC1_GPIO0_CHANNEL ADC1_CHANNEL_0 +#define ADC1_CHANNEL_0_GPIO_NUM 0 + +#define ADC1_GPIO1_CHANNEL ADC1_CHANNEL_1 +#define ADC1_CHANNEL_1_GPIO_NUM 1 + +#define ADC1_GPIO2_CHANNEL ADC1_CHANNEL_2 +#define ADC1_CHANNEL_2_GPIO_NUM 2 + +#define ADC1_GPIO3_CHANNEL ADC1_CHANNEL_3 +#define ADC1_CHANNEL_3_GPIO_NUM 3 + +#define ADC1_GPIO4_CHANNEL ADC1_CHANNEL_4 +#define ADC1_CHANNEL_4_GPIO_NUM 4 + +#define ADC2_GPIO5_CHANNEL ADC2_CHANNEL_0 +#define ADC2_CHANNEL_0_GPIO_NUM 5 diff --git a/components/soc/esp32c6/include/soc/aes_reg.h b/components/soc/esp32c6/include/soc/aes_reg.h new file mode 100644 index 0000000000..c096489ca4 --- /dev/null +++ b/components/soc/esp32c6/include/soc/aes_reg.h @@ -0,0 +1,417 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** AES_KEY_0_REG register + * Key material key_0 configure register + */ +#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0) +/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_0 that is a part of key material. + */ +#define AES_KEY_0 0xFFFFFFFFU +#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S) +#define AES_KEY_0_V 0xFFFFFFFFU +#define AES_KEY_0_S 0 + +/** AES_KEY_1_REG register + * Key material key_1 configure register + */ +#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4) +/** AES_KEY_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_1 that is a part of key material. + */ +#define AES_KEY_1 0xFFFFFFFFU +#define AES_KEY_1_M (AES_KEY_1_V << AES_KEY_1_S) +#define AES_KEY_1_V 0xFFFFFFFFU +#define AES_KEY_1_S 0 + +/** AES_KEY_2_REG register + * Key material key_2 configure register + */ +#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8) +/** AES_KEY_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_2 that is a part of key material. + */ +#define AES_KEY_2 0xFFFFFFFFU +#define AES_KEY_2_M (AES_KEY_2_V << AES_KEY_2_S) +#define AES_KEY_2_V 0xFFFFFFFFU +#define AES_KEY_2_S 0 + +/** AES_KEY_3_REG register + * Key material key_3 configure register + */ +#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc) +/** AES_KEY_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_3 that is a part of key material. + */ +#define AES_KEY_3 0xFFFFFFFFU +#define AES_KEY_3_M (AES_KEY_3_V << AES_KEY_3_S) +#define AES_KEY_3_V 0xFFFFFFFFU +#define AES_KEY_3_S 0 + +/** AES_KEY_4_REG register + * Key material key_4 configure register + */ +#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10) +/** AES_KEY_4 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_4 that is a part of key material. + */ +#define AES_KEY_4 0xFFFFFFFFU +#define AES_KEY_4_M (AES_KEY_4_V << AES_KEY_4_S) +#define AES_KEY_4_V 0xFFFFFFFFU +#define AES_KEY_4_S 0 + +/** AES_KEY_5_REG register + * Key material key_5 configure register + */ +#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14) +/** AES_KEY_5 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_5 that is a part of key material. + */ +#define AES_KEY_5 0xFFFFFFFFU +#define AES_KEY_5_M (AES_KEY_5_V << AES_KEY_5_S) +#define AES_KEY_5_V 0xFFFFFFFFU +#define AES_KEY_5_S 0 + +/** AES_KEY_6_REG register + * Key material key_6 configure register + */ +#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18) +/** AES_KEY_6 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_6 that is a part of key material. + */ +#define AES_KEY_6 0xFFFFFFFFU +#define AES_KEY_6_M (AES_KEY_6_V << AES_KEY_6_S) +#define AES_KEY_6_V 0xFFFFFFFFU +#define AES_KEY_6_S 0 + +/** AES_KEY_7_REG register + * Key material key_7 configure register + */ +#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c) +/** AES_KEY_7 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_7 that is a part of key material. + */ +#define AES_KEY_7 0xFFFFFFFFU +#define AES_KEY_7_M (AES_KEY_7_V << AES_KEY_7_S) +#define AES_KEY_7_V 0xFFFFFFFFU +#define AES_KEY_7_S 0 + +/** AES_TEXT_IN_0_REG register + * source text material text_in_0 configure register + */ +#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20) +/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_0 that is a part of source text material. + */ +#define AES_TEXT_IN_0 0xFFFFFFFFU +#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S) +#define AES_TEXT_IN_0_V 0xFFFFFFFFU +#define AES_TEXT_IN_0_S 0 + +/** AES_TEXT_IN_1_REG register + * source text material text_in_1 configure register + */ +#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24) +/** AES_TEXT_IN_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_1 that is a part of source text material. + */ +#define AES_TEXT_IN_1 0xFFFFFFFFU +#define AES_TEXT_IN_1_M (AES_TEXT_IN_1_V << AES_TEXT_IN_1_S) +#define AES_TEXT_IN_1_V 0xFFFFFFFFU +#define AES_TEXT_IN_1_S 0 + +/** AES_TEXT_IN_2_REG register + * source text material text_in_2 configure register + */ +#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28) +/** AES_TEXT_IN_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_2 that is a part of source text material. + */ +#define AES_TEXT_IN_2 0xFFFFFFFFU +#define AES_TEXT_IN_2_M (AES_TEXT_IN_2_V << AES_TEXT_IN_2_S) +#define AES_TEXT_IN_2_V 0xFFFFFFFFU +#define AES_TEXT_IN_2_S 0 + +/** AES_TEXT_IN_3_REG register + * source text material text_in_3 configure register + */ +#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c) +/** AES_TEXT_IN_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_3 that is a part of source text material. + */ +#define AES_TEXT_IN_3 0xFFFFFFFFU +#define AES_TEXT_IN_3_M (AES_TEXT_IN_3_V << AES_TEXT_IN_3_S) +#define AES_TEXT_IN_3_V 0xFFFFFFFFU +#define AES_TEXT_IN_3_S 0 + +/** AES_TEXT_OUT_0_REG register + * result text material text_out_0 configure register + */ +#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30) +/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_0 that is a part of result text material. + */ +#define AES_TEXT_OUT_0 0xFFFFFFFFU +#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S) +#define AES_TEXT_OUT_0_V 0xFFFFFFFFU +#define AES_TEXT_OUT_0_S 0 + +/** AES_TEXT_OUT_1_REG register + * result text material text_out_1 configure register + */ +#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34) +/** AES_TEXT_OUT_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_1 that is a part of result text material. + */ +#define AES_TEXT_OUT_1 0xFFFFFFFFU +#define AES_TEXT_OUT_1_M (AES_TEXT_OUT_1_V << AES_TEXT_OUT_1_S) +#define AES_TEXT_OUT_1_V 0xFFFFFFFFU +#define AES_TEXT_OUT_1_S 0 + +/** AES_TEXT_OUT_2_REG register + * result text material text_out_2 configure register + */ +#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38) +/** AES_TEXT_OUT_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_2 that is a part of result text material. + */ +#define AES_TEXT_OUT_2 0xFFFFFFFFU +#define AES_TEXT_OUT_2_M (AES_TEXT_OUT_2_V << AES_TEXT_OUT_2_S) +#define AES_TEXT_OUT_2_V 0xFFFFFFFFU +#define AES_TEXT_OUT_2_S 0 + +/** AES_TEXT_OUT_3_REG register + * result text material text_out_3 configure register + */ +#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c) +/** AES_TEXT_OUT_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_3 that is a part of result text material. + */ +#define AES_TEXT_OUT_3 0xFFFFFFFFU +#define AES_TEXT_OUT_3_M (AES_TEXT_OUT_3_V << AES_TEXT_OUT_3_S) +#define AES_TEXT_OUT_3_V 0xFFFFFFFFU +#define AES_TEXT_OUT_3_S 0 + +/** AES_MODE_REG register + * AES Mode register + */ +#define AES_MODE_REG (DR_REG_AES_BASE + 0x40) +/** AES_MODE : R/W; bitpos: [2:0]; default: 0; + * This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: + * AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256. + */ +#define AES_MODE 0x00000007U +#define AES_MODE_M (AES_MODE_V << AES_MODE_S) +#define AES_MODE_V 0x00000007U +#define AES_MODE_S 0 + +/** AES_ENDIAN_REG register + * AES Endian configure register + */ +#define AES_ENDIAN_REG (DR_REG_AES_BASE + 0x44) +/** AES_ENDIAN : R/W; bitpos: [5:0]; default: 0; + * endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out + * endian or out_stream endian + */ +#define AES_ENDIAN 0x0000003FU +#define AES_ENDIAN_M (AES_ENDIAN_V << AES_ENDIAN_S) +#define AES_ENDIAN_V 0x0000003FU +#define AES_ENDIAN_S 0 + +/** AES_TRIGGER_REG register + * AES trigger register + */ +#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48) +/** AES_TRIGGER : WT; bitpos: [0]; default: 0; + * Set this bit to start AES calculation. + */ +#define AES_TRIGGER (BIT(0)) +#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S) +#define AES_TRIGGER_V 0x00000001U +#define AES_TRIGGER_S 0 + +/** AES_STATE_REG register + * AES state register + */ +#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c) +/** AES_STATE : RO; bitpos: [1:0]; default: 0; + * Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: + * idle, 1: busy, 2: calculation_done. + */ +#define AES_STATE 0x00000003U +#define AES_STATE_M (AES_STATE_V << AES_STATE_S) +#define AES_STATE_V 0x00000003U +#define AES_STATE_S 0 + +/** AES_IV_MEM register + * The memory that stores initialization vector + */ +#define AES_IV_MEM (DR_REG_AES_BASE + 0x50) +#define AES_IV_MEM_SIZE_BYTES 16 + +/** AES_H_MEM register + * The memory that stores GCM hash subkey + */ +#define AES_H_MEM (DR_REG_AES_BASE + 0x60) +#define AES_H_MEM_SIZE_BYTES 16 + +/** AES_J0_MEM register + * The memory that stores J0 + */ +#define AES_J0_MEM (DR_REG_AES_BASE + 0x70) +#define AES_J0_MEM_SIZE_BYTES 16 + +/** AES_T0_MEM register + * The memory that stores T0 + */ +#define AES_T0_MEM (DR_REG_AES_BASE + 0x80) +#define AES_T0_MEM_SIZE_BYTES 16 + +/** AES_DMA_ENABLE_REG register + * DMA-AES working mode register + */ +#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90) +/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0; + * 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. + */ +#define AES_DMA_ENABLE (BIT(0)) +#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S) +#define AES_DMA_ENABLE_V 0x00000001U +#define AES_DMA_ENABLE_S 0 + +/** AES_BLOCK_MODE_REG register + * AES cipher block mode register + */ +#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94) +/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0; + * Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, + * 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved. + */ +#define AES_BLOCK_MODE 0x00000007U +#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S) +#define AES_BLOCK_MODE_V 0x00000007U +#define AES_BLOCK_MODE_S 0 + +/** AES_BLOCK_NUM_REG register + * AES block number register + */ +#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98) +/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; + * Those bits stores the number of Plaintext/ciphertext block. + */ +#define AES_BLOCK_NUM 0xFFFFFFFFU +#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S) +#define AES_BLOCK_NUM_V 0xFFFFFFFFU +#define AES_BLOCK_NUM_S 0 + +/** AES_INC_SEL_REG register + * Standard incrementing function configure register + */ +#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c) +/** AES_INC_SEL : R/W; bitpos: [0]; default: 0; + * This bit decides the standard incrementing function. 0: INC32. 1: INC128. + */ +#define AES_INC_SEL (BIT(0)) +#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S) +#define AES_INC_SEL_V 0x00000001U +#define AES_INC_SEL_S 0 + +/** AES_AAD_BLOCK_NUM_REG register + * Additional Authential Data block number register + */ +#define AES_AAD_BLOCK_NUM_REG (DR_REG_AES_BASE + 0xa0) +/** AES_AAD_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; + * Those bits stores the number of AAD block. + */ +#define AES_AAD_BLOCK_NUM 0xFFFFFFFFU +#define AES_AAD_BLOCK_NUM_M (AES_AAD_BLOCK_NUM_V << AES_AAD_BLOCK_NUM_S) +#define AES_AAD_BLOCK_NUM_V 0xFFFFFFFFU +#define AES_AAD_BLOCK_NUM_S 0 + +/** AES_REMAINDER_BIT_NUM_REG register + * AES remainder bit number register + */ +#define AES_REMAINDER_BIT_NUM_REG (DR_REG_AES_BASE + 0xa4) +/** AES_REMAINDER_BIT_NUM : R/W; bitpos: [6:0]; default: 0; + * Those bits stores the number of remainder bit. + */ +#define AES_REMAINDER_BIT_NUM 0x0000007FU +#define AES_REMAINDER_BIT_NUM_M (AES_REMAINDER_BIT_NUM_V << AES_REMAINDER_BIT_NUM_S) +#define AES_REMAINDER_BIT_NUM_V 0x0000007FU +#define AES_REMAINDER_BIT_NUM_S 0 + +/** AES_CONTINUE_REG register + * AES continue register + */ +#define AES_CONTINUE_REG (DR_REG_AES_BASE + 0xa8) +/** AES_CONTINUE : WT; bitpos: [0]; default: 0; + * Set this bit to continue GCM operation. + */ +#define AES_CONTINUE (BIT(0)) +#define AES_CONTINUE_M (AES_CONTINUE_V << AES_CONTINUE_S) +#define AES_CONTINUE_V 0x00000001U +#define AES_CONTINUE_S 0 + +/** AES_INT_CLEAR_REG register + * AES Interrupt clear register + */ +#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac) +/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the AES interrupt. + */ +#define AES_INT_CLEAR (BIT(0)) +#define AES_INT_CLEAR_M (AES_INT_CLEAR_V << AES_INT_CLEAR_S) +#define AES_INT_CLEAR_V 0x00000001U +#define AES_INT_CLEAR_S 0 + +/** AES_INT_ENA_REG register + * AES Interrupt enable register + */ +#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0) +/** AES_INT_ENA : R/W; bitpos: [0]; default: 0; + * Set this bit to enable interrupt that occurs when DMA-AES calculation is done. + */ +#define AES_INT_ENA (BIT(0)) +#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S) +#define AES_INT_ENA_V 0x00000001U +#define AES_INT_ENA_S 0 + +/** AES_DATE_REG register + * AES version control register + */ +#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4) +/** AES_DATE : R/W; bitpos: [29:0]; default: 538513936; + * This bits stores the version information of AES. + */ +#define AES_DATE 0x3FFFFFFFU +#define AES_DATE_M (AES_DATE_V << AES_DATE_S) +#define AES_DATE_V 0x3FFFFFFFU +#define AES_DATE_S 0 + +/** AES_DMA_EXIT_REG register + * AES-DMA exit config + */ +#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8) +/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0; + * Set this register to leave calculation done stage. Recommend to use it after + * software finishes reading DMA's output buffer. + */ +#define AES_DMA_EXIT (BIT(0)) +#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S) +#define AES_DMA_EXIT_V 0x00000001U +#define AES_DMA_EXIT_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/aes_struct.h b/components/soc/esp32c6/include/soc/aes_struct.h new file mode 100644 index 0000000000..ec092a2e9e --- /dev/null +++ b/components/soc/esp32c6/include/soc/aes_struct.h @@ -0,0 +1,496 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: key register */ +/** Type of key_0 register + * Key material key_0 configure register + */ +typedef union { + struct { + /** key_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_0 that is a part of key material. + */ + uint32_t key_0:32; + }; + uint32_t val; +} aes_key_0_reg_t; + +/** Type of key_1 register + * Key material key_1 configure register + */ +typedef union { + struct { + /** key_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_1 that is a part of key material. + */ + uint32_t key_1:32; + }; + uint32_t val; +} aes_key_1_reg_t; + +/** Type of key_2 register + * Key material key_2 configure register + */ +typedef union { + struct { + /** key_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_2 that is a part of key material. + */ + uint32_t key_2:32; + }; + uint32_t val; +} aes_key_2_reg_t; + +/** Type of key_3 register + * Key material key_3 configure register + */ +typedef union { + struct { + /** key_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_3 that is a part of key material. + */ + uint32_t key_3:32; + }; + uint32_t val; +} aes_key_3_reg_t; + +/** Type of key_4 register + * Key material key_4 configure register + */ +typedef union { + struct { + /** key_4 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_4 that is a part of key material. + */ + uint32_t key_4:32; + }; + uint32_t val; +} aes_key_4_reg_t; + +/** Type of key_5 register + * Key material key_5 configure register + */ +typedef union { + struct { + /** key_5 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_5 that is a part of key material. + */ + uint32_t key_5:32; + }; + uint32_t val; +} aes_key_5_reg_t; + +/** Type of key_6 register + * Key material key_6 configure register + */ +typedef union { + struct { + /** key_6 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_6 that is a part of key material. + */ + uint32_t key_6:32; + }; + uint32_t val; +} aes_key_6_reg_t; + +/** Type of key_7 register + * Key material key_7 configure register + */ +typedef union { + struct { + /** key_7 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_7 that is a part of key material. + */ + uint32_t key_7:32; + }; + uint32_t val; +} aes_key_7_reg_t; + + +/** Group: text in register */ +/** Type of text_in_0 register + * source text material text_in_0 configure register + */ +typedef union { + struct { + /** text_in_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_0 that is a part of source text material. + */ + uint32_t text_in_0:32; + }; + uint32_t val; +} aes_text_in_0_reg_t; + +/** Type of text_in_1 register + * source text material text_in_1 configure register + */ +typedef union { + struct { + /** text_in_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_1 that is a part of source text material. + */ + uint32_t text_in_1:32; + }; + uint32_t val; +} aes_text_in_1_reg_t; + +/** Type of text_in_2 register + * source text material text_in_2 configure register + */ +typedef union { + struct { + /** text_in_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_2 that is a part of source text material. + */ + uint32_t text_in_2:32; + }; + uint32_t val; +} aes_text_in_2_reg_t; + +/** Type of text_in_3 register + * source text material text_in_3 configure register + */ +typedef union { + struct { + /** text_in_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_3 that is a part of source text material. + */ + uint32_t text_in_3:32; + }; + uint32_t val; +} aes_text_in_3_reg_t; + + +/** Group: text out register */ +/** Type of text_out_0 register + * result text material text_out_0 configure register + */ +typedef union { + struct { + /** text_out_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_0 that is a part of result text material. + */ + uint32_t text_out_0:32; + }; + uint32_t val; +} aes_text_out_0_reg_t; + +/** Type of text_out_1 register + * result text material text_out_1 configure register + */ +typedef union { + struct { + /** text_out_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_1 that is a part of result text material. + */ + uint32_t text_out_1:32; + }; + uint32_t val; +} aes_text_out_1_reg_t; + +/** Type of text_out_2 register + * result text material text_out_2 configure register + */ +typedef union { + struct { + /** text_out_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_2 that is a part of result text material. + */ + uint32_t text_out_2:32; + }; + uint32_t val; +} aes_text_out_2_reg_t; + +/** Type of text_out_3 register + * result text material text_out_3 configure register + */ +typedef union { + struct { + /** text_out_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_3 that is a part of result text material. + */ + uint32_t text_out_3:32; + }; + uint32_t val; +} aes_text_out_3_reg_t; + + +/** Group: Configuration register */ +/** Type of mode register + * AES Mode register + */ +typedef union { + struct { + /** mode : R/W; bitpos: [2:0]; default: 0; + * This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: + * AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256. + */ + uint32_t mode:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} aes_mode_reg_t; + +/** Type of endian register + * AES Endian configure register + */ +typedef union { + struct { + /** endian : R/W; bitpos: [5:0]; default: 0; + * endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out + * endian or out_stream endian + */ + uint32_t endian:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} aes_endian_reg_t; + +/** Type of block_mode register + * AES cipher block mode register + */ +typedef union { + struct { + /** block_mode : R/W; bitpos: [2:0]; default: 0; + * Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, + * 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved. + */ + uint32_t block_mode:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} aes_block_mode_reg_t; + +/** Type of block_num register + * AES block number register + */ +typedef union { + struct { + /** block_num : R/W; bitpos: [31:0]; default: 0; + * Those bits stores the number of Plaintext/ciphertext block. + */ + uint32_t block_num:32; + }; + uint32_t val; +} aes_block_num_reg_t; + +/** Type of inc_sel register + * Standard incrementing function configure register + */ +typedef union { + struct { + /** inc_sel : R/W; bitpos: [0]; default: 0; + * This bit decides the standard incrementing function. 0: INC32. 1: INC128. + */ + uint32_t inc_sel:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_inc_sel_reg_t; + +/** Type of aad_block_num register + * Additional Authential Data block number register + */ +typedef union { + struct { + /** aad_block_num : R/W; bitpos: [31:0]; default: 0; + * Those bits stores the number of AAD block. + */ + uint32_t aad_block_num:32; + }; + uint32_t val; +} aes_aad_block_num_reg_t; + +/** Type of remainder_bit_num register + * AES remainder bit number register + */ +typedef union { + struct { + /** remainder_bit_num : R/W; bitpos: [6:0]; default: 0; + * Those bits stores the number of remainder bit. + */ + uint32_t remainder_bit_num:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} aes_remainder_bit_num_reg_t; + + +/** Group: Control/Status register */ +/** Type of trigger register + * AES trigger register + */ +typedef union { + struct { + /** trigger : WT; bitpos: [0]; default: 0; + * Set this bit to start AES calculation. + */ + uint32_t trigger:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_trigger_reg_t; + +/** Type of state register + * AES state register + */ +typedef union { + struct { + /** state : RO; bitpos: [1:0]; default: 0; + * Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: + * idle, 1: busy, 2: calculation_done. + */ + uint32_t state:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} aes_state_reg_t; + +/** Type of dma_enable register + * DMA-AES working mode register + */ +typedef union { + struct { + /** dma_enable : R/W; bitpos: [0]; default: 0; + * 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. + */ + uint32_t dma_enable:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_dma_enable_reg_t; + +/** Type of continue register + * AES continue register + */ +typedef union { + struct { + /** conti : WT; bitpos: [0]; default: 0; + * Set this bit to continue GCM operation. + */ + uint32_t conti:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_continue_reg_t; + +/** Type of dma_exit register + * AES-DMA exit config + */ +typedef union { + struct { + /** dma_exit : WT; bitpos: [0]; default: 0; + * Set this register to leave calculation done stage. Recommend to use it after + * software finishes reading DMA's output buffer. + */ + uint32_t dma_exit:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_dma_exit_reg_t; + + +/** Group: memory type */ + +/** Group: interrupt register */ +/** Type of int_clear register + * AES Interrupt clear register + */ +typedef union { + struct { + /** int_clear : WT; bitpos: [0]; default: 0; + * Set this bit to clear the AES interrupt. + */ + uint32_t int_clear:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_int_clear_reg_t; + +/** Type of int_ena register + * AES Interrupt enable register + */ +typedef union { + struct { + /** int_ena : R/W; bitpos: [0]; default: 0; + * Set this bit to enable interrupt that occurs when DMA-AES calculation is done. + */ + uint32_t int_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_int_ena_reg_t; + + +/** Group: Version control register */ +/** Type of date register + * AES version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 538513936; + * This bits stores the version information of AES. + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} aes_date_reg_t; + + +typedef struct aes_dev_t { + volatile aes_key_0_reg_t key_0; + volatile aes_key_1_reg_t key_1; + volatile aes_key_2_reg_t key_2; + volatile aes_key_3_reg_t key_3; + volatile aes_key_4_reg_t key_4; + volatile aes_key_5_reg_t key_5; + volatile aes_key_6_reg_t key_6; + volatile aes_key_7_reg_t key_7; + volatile aes_text_in_0_reg_t text_in_0; + volatile aes_text_in_1_reg_t text_in_1; + volatile aes_text_in_2_reg_t text_in_2; + volatile aes_text_in_3_reg_t text_in_3; + volatile aes_text_out_0_reg_t text_out_0; + volatile aes_text_out_1_reg_t text_out_1; + volatile aes_text_out_2_reg_t text_out_2; + volatile aes_text_out_3_reg_t text_out_3; + volatile aes_mode_reg_t mode; + volatile aes_endian_reg_t endian; + volatile aes_trigger_reg_t trigger; + volatile aes_state_reg_t state; + volatile uint32_t iv[4]; + volatile uint32_t h[4]; + volatile uint32_t j0[4]; + volatile uint32_t t0[4]; + volatile aes_dma_enable_reg_t dma_enable; + volatile aes_block_mode_reg_t block_mode; + volatile aes_block_num_reg_t block_num; + volatile aes_inc_sel_reg_t inc_sel; + volatile aes_aad_block_num_reg_t aad_block_num; + volatile aes_remainder_bit_num_reg_t remainder_bit_num; + volatile aes_continue_reg_t conti; + volatile aes_int_clear_reg_t int_clear; + volatile aes_int_ena_reg_t int_ena; + volatile aes_date_reg_t date; + volatile aes_dma_exit_reg_t dma_exit; +} aes_dev_t; + +extern aes_dev_t AES; + +#ifndef __cplusplus +_Static_assert(sizeof(aes_dev_t) == 0xbc, "Invalid size of aes_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/apb_saradc_reg.h b/components/soc/esp32c6/include/soc/apb_saradc_reg.h new file mode 100644 index 0000000000..6a5bea4b5c --- /dev/null +++ b/components/soc/esp32c6/include/soc/apb_saradc_reg.h @@ -0,0 +1,884 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** APB_SARADC_CTRL_REG register + * digital saradc configure register + */ +#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0) +/** APB_SARADC_SARADC_START_FORCE : R/W; bitpos: [0]; default: 0; + * select software enable saradc sample + */ +#define APB_SARADC_SARADC_START_FORCE (BIT(0)) +#define APB_SARADC_SARADC_START_FORCE_M (APB_SARADC_SARADC_START_FORCE_V << APB_SARADC_SARADC_START_FORCE_S) +#define APB_SARADC_SARADC_START_FORCE_V 0x00000001U +#define APB_SARADC_SARADC_START_FORCE_S 0 +/** APB_SARADC_SARADC_START : R/W; bitpos: [1]; default: 0; + * software enable saradc sample + */ +#define APB_SARADC_SARADC_START (BIT(1)) +#define APB_SARADC_SARADC_START_M (APB_SARADC_SARADC_START_V << APB_SARADC_SARADC_START_S) +#define APB_SARADC_SARADC_START_V 0x00000001U +#define APB_SARADC_SARADC_START_S 1 +/** APB_SARADC_SARADC_SAR_CLK_GATED : R/W; bitpos: [6]; default: 1; + * SAR clock gated + */ +#define APB_SARADC_SARADC_SAR_CLK_GATED (BIT(6)) +#define APB_SARADC_SARADC_SAR_CLK_GATED_M (APB_SARADC_SARADC_SAR_CLK_GATED_V << APB_SARADC_SARADC_SAR_CLK_GATED_S) +#define APB_SARADC_SARADC_SAR_CLK_GATED_V 0x00000001U +#define APB_SARADC_SARADC_SAR_CLK_GATED_S 6 +/** APB_SARADC_SARADC_SAR_CLK_DIV : R/W; bitpos: [14:7]; default: 4; + * SAR clock divider + */ +#define APB_SARADC_SARADC_SAR_CLK_DIV 0x000000FFU +#define APB_SARADC_SARADC_SAR_CLK_DIV_M (APB_SARADC_SARADC_SAR_CLK_DIV_V << APB_SARADC_SARADC_SAR_CLK_DIV_S) +#define APB_SARADC_SARADC_SAR_CLK_DIV_V 0x000000FFU +#define APB_SARADC_SARADC_SAR_CLK_DIV_S 7 +/** APB_SARADC_SARADC_SAR_PATT_LEN : R/W; bitpos: [17:15]; default: 7; + * 0 ~ 15 means length 1 ~ 16 + */ +#define APB_SARADC_SARADC_SAR_PATT_LEN 0x00000007U +#define APB_SARADC_SARADC_SAR_PATT_LEN_M (APB_SARADC_SARADC_SAR_PATT_LEN_V << APB_SARADC_SARADC_SAR_PATT_LEN_S) +#define APB_SARADC_SARADC_SAR_PATT_LEN_V 0x00000007U +#define APB_SARADC_SARADC_SAR_PATT_LEN_S 15 +/** APB_SARADC_SARADC_SAR_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0; + * clear the pointer of pattern table for DIG ADC1 CTRL + */ +#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR (BIT(23)) +#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_M (APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V << APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S) +#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V 0x00000001U +#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S 23 +/** APB_SARADC_SARADC_XPD_SAR_FORCE : R/W; bitpos: [28:27]; default: 0; + * force option to xpd sar blocks + */ +#define APB_SARADC_SARADC_XPD_SAR_FORCE 0x00000003U +#define APB_SARADC_SARADC_XPD_SAR_FORCE_M (APB_SARADC_SARADC_XPD_SAR_FORCE_V << APB_SARADC_SARADC_XPD_SAR_FORCE_S) +#define APB_SARADC_SARADC_XPD_SAR_FORCE_V 0x00000003U +#define APB_SARADC_SARADC_XPD_SAR_FORCE_S 27 +/** APB_SARADC_SARADC2_PWDET_DRV : R/W; bitpos: [29]; default: 0; + * enable saradc2 power detect driven func. + */ +#define APB_SARADC_SARADC2_PWDET_DRV (BIT(29)) +#define APB_SARADC_SARADC2_PWDET_DRV_M (APB_SARADC_SARADC2_PWDET_DRV_V << APB_SARADC_SARADC2_PWDET_DRV_S) +#define APB_SARADC_SARADC2_PWDET_DRV_V 0x00000001U +#define APB_SARADC_SARADC2_PWDET_DRV_S 29 +/** APB_SARADC_SARADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1; + * wait arbit signal stable after sar_done + */ +#define APB_SARADC_SARADC_WAIT_ARB_CYCLE 0x00000003U +#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_M (APB_SARADC_SARADC_WAIT_ARB_CYCLE_V << APB_SARADC_SARADC_WAIT_ARB_CYCLE_S) +#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_V 0x00000003U +#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_S 30 + +/** APB_SARADC_CTRL2_REG register + * digital saradc configure register + */ +#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4) +/** APB_SARADC_SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0; + * enable max meas num + */ +#define APB_SARADC_SARADC_MEAS_NUM_LIMIT (BIT(0)) +#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_M (APB_SARADC_SARADC_MEAS_NUM_LIMIT_V << APB_SARADC_SARADC_MEAS_NUM_LIMIT_S) +#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_V 0x00000001U +#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_S 0 +/** APB_SARADC_SARADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255; + * max conversion number + */ +#define APB_SARADC_SARADC_MAX_MEAS_NUM 0x000000FFU +#define APB_SARADC_SARADC_MAX_MEAS_NUM_M (APB_SARADC_SARADC_MAX_MEAS_NUM_V << APB_SARADC_SARADC_MAX_MEAS_NUM_S) +#define APB_SARADC_SARADC_MAX_MEAS_NUM_V 0x000000FFU +#define APB_SARADC_SARADC_MAX_MEAS_NUM_S 1 +/** APB_SARADC_SARADC_SAR1_INV : R/W; bitpos: [9]; default: 0; + * 1: data to DIG ADC1 CTRL is inverted, otherwise not + */ +#define APB_SARADC_SARADC_SAR1_INV (BIT(9)) +#define APB_SARADC_SARADC_SAR1_INV_M (APB_SARADC_SARADC_SAR1_INV_V << APB_SARADC_SARADC_SAR1_INV_S) +#define APB_SARADC_SARADC_SAR1_INV_V 0x00000001U +#define APB_SARADC_SARADC_SAR1_INV_S 9 +/** APB_SARADC_SARADC_SAR2_INV : R/W; bitpos: [10]; default: 0; + * 1: data to DIG ADC2 CTRL is inverted, otherwise not + */ +#define APB_SARADC_SARADC_SAR2_INV (BIT(10)) +#define APB_SARADC_SARADC_SAR2_INV_M (APB_SARADC_SARADC_SAR2_INV_V << APB_SARADC_SARADC_SAR2_INV_S) +#define APB_SARADC_SARADC_SAR2_INV_V 0x00000001U +#define APB_SARADC_SARADC_SAR2_INV_S 10 +/** APB_SARADC_SARADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10; + * to set saradc timer target + */ +#define APB_SARADC_SARADC_TIMER_TARGET 0x00000FFFU +#define APB_SARADC_SARADC_TIMER_TARGET_M (APB_SARADC_SARADC_TIMER_TARGET_V << APB_SARADC_SARADC_TIMER_TARGET_S) +#define APB_SARADC_SARADC_TIMER_TARGET_V 0x00000FFFU +#define APB_SARADC_SARADC_TIMER_TARGET_S 12 +/** APB_SARADC_SARADC_TIMER_EN : R/W; bitpos: [24]; default: 0; + * to enable saradc timer trigger + */ +#define APB_SARADC_SARADC_TIMER_EN (BIT(24)) +#define APB_SARADC_SARADC_TIMER_EN_M (APB_SARADC_SARADC_TIMER_EN_V << APB_SARADC_SARADC_TIMER_EN_S) +#define APB_SARADC_SARADC_TIMER_EN_V 0x00000001U +#define APB_SARADC_SARADC_TIMER_EN_S 24 + +/** APB_SARADC_FILTER_CTRL1_REG register + * digital saradc configure register + */ +#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8) +/** APB_SARADC_APB_SARADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0; + * Factor of saradc filter1 + */ +#define APB_SARADC_APB_SARADC_FILTER_FACTOR1 0x00000007U +#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_M (APB_SARADC_APB_SARADC_FILTER_FACTOR1_V << APB_SARADC_APB_SARADC_FILTER_FACTOR1_S) +#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_V 0x00000007U +#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_S 26 +/** APB_SARADC_APB_SARADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0; + * Factor of saradc filter0 + */ +#define APB_SARADC_APB_SARADC_FILTER_FACTOR0 0x00000007U +#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_M (APB_SARADC_APB_SARADC_FILTER_FACTOR0_V << APB_SARADC_APB_SARADC_FILTER_FACTOR0_S) +#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_V 0x00000007U +#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_S 29 + +/** APB_SARADC_FSM_WAIT_REG register + * digital saradc configure register + */ +#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0xc) +/** APB_SARADC_SARADC_XPD_WAIT : R/W; bitpos: [7:0]; default: 8; + * saradc_xpd_wait + */ +#define APB_SARADC_SARADC_XPD_WAIT 0x000000FFU +#define APB_SARADC_SARADC_XPD_WAIT_M (APB_SARADC_SARADC_XPD_WAIT_V << APB_SARADC_SARADC_XPD_WAIT_S) +#define APB_SARADC_SARADC_XPD_WAIT_V 0x000000FFU +#define APB_SARADC_SARADC_XPD_WAIT_S 0 +/** APB_SARADC_SARADC_RSTB_WAIT : R/W; bitpos: [15:8]; default: 8; + * saradc_rstb_wait + */ +#define APB_SARADC_SARADC_RSTB_WAIT 0x000000FFU +#define APB_SARADC_SARADC_RSTB_WAIT_M (APB_SARADC_SARADC_RSTB_WAIT_V << APB_SARADC_SARADC_RSTB_WAIT_S) +#define APB_SARADC_SARADC_RSTB_WAIT_V 0x000000FFU +#define APB_SARADC_SARADC_RSTB_WAIT_S 8 +/** APB_SARADC_SARADC_STANDBY_WAIT : R/W; bitpos: [23:16]; default: 255; + * saradc_standby_wait + */ +#define APB_SARADC_SARADC_STANDBY_WAIT 0x000000FFU +#define APB_SARADC_SARADC_STANDBY_WAIT_M (APB_SARADC_SARADC_STANDBY_WAIT_V << APB_SARADC_SARADC_STANDBY_WAIT_S) +#define APB_SARADC_SARADC_STANDBY_WAIT_V 0x000000FFU +#define APB_SARADC_SARADC_STANDBY_WAIT_S 16 + +/** APB_SARADC_SAR1_STATUS_REG register + * digital saradc configure register + */ +#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x10) +/** APB_SARADC_SARADC_SAR1_STATUS : RO; bitpos: [31:0]; default: 536870912; + * saradc1 status about data and channel + */ +#define APB_SARADC_SARADC_SAR1_STATUS 0xFFFFFFFFU +#define APB_SARADC_SARADC_SAR1_STATUS_M (APB_SARADC_SARADC_SAR1_STATUS_V << APB_SARADC_SARADC_SAR1_STATUS_S) +#define APB_SARADC_SARADC_SAR1_STATUS_V 0xFFFFFFFFU +#define APB_SARADC_SARADC_SAR1_STATUS_S 0 + +/** APB_SARADC_SAR2_STATUS_REG register + * digital saradc configure register + */ +#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x14) +/** APB_SARADC_SARADC_SAR2_STATUS : RO; bitpos: [31:0]; default: 536870912; + * saradc2 status about data and channel + */ +#define APB_SARADC_SARADC_SAR2_STATUS 0xFFFFFFFFU +#define APB_SARADC_SARADC_SAR2_STATUS_M (APB_SARADC_SARADC_SAR2_STATUS_V << APB_SARADC_SARADC_SAR2_STATUS_S) +#define APB_SARADC_SARADC_SAR2_STATUS_V 0xFFFFFFFFU +#define APB_SARADC_SARADC_SAR2_STATUS_S 0 + +/** APB_SARADC_SAR_PATT_TAB1_REG register + * digital saradc configure register + */ +#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18) +/** APB_SARADC_SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215; + * item 0 ~ 3 for pattern table 1 (each item one byte) + */ +#define APB_SARADC_SARADC_SAR_PATT_TAB1 0x00FFFFFFU +#define APB_SARADC_SARADC_SAR_PATT_TAB1_M (APB_SARADC_SARADC_SAR_PATT_TAB1_V << APB_SARADC_SARADC_SAR_PATT_TAB1_S) +#define APB_SARADC_SARADC_SAR_PATT_TAB1_V 0x00FFFFFFU +#define APB_SARADC_SARADC_SAR_PATT_TAB1_S 0 + +/** APB_SARADC_SAR_PATT_TAB2_REG register + * digital saradc configure register + */ +#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1c) +/** APB_SARADC_SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215; + * Item 4 ~ 7 for pattern table 1 (each item one byte) + */ +#define APB_SARADC_SARADC_SAR_PATT_TAB2 0x00FFFFFFU +#define APB_SARADC_SARADC_SAR_PATT_TAB2_M (APB_SARADC_SARADC_SAR_PATT_TAB2_V << APB_SARADC_SARADC_SAR_PATT_TAB2_S) +#define APB_SARADC_SARADC_SAR_PATT_TAB2_V 0x00FFFFFFU +#define APB_SARADC_SARADC_SAR_PATT_TAB2_S 0 + +/** APB_SARADC_ONETIME_SAMPLE_REG register + * digital saradc configure register + */ +#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x20) +/** APB_SARADC_SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0; + * configure onetime atten + */ +#define APB_SARADC_SARADC_ONETIME_ATTEN 0x00000003U +#define APB_SARADC_SARADC_ONETIME_ATTEN_M (APB_SARADC_SARADC_ONETIME_ATTEN_V << APB_SARADC_SARADC_ONETIME_ATTEN_S) +#define APB_SARADC_SARADC_ONETIME_ATTEN_V 0x00000003U +#define APB_SARADC_SARADC_ONETIME_ATTEN_S 23 +/** APB_SARADC_SARADC_ONETIME_CHANNEL : R/W; bitpos: [28:25]; default: 13; + * configure onetime channel + */ +#define APB_SARADC_SARADC_ONETIME_CHANNEL 0x0000000FU +#define APB_SARADC_SARADC_ONETIME_CHANNEL_M (APB_SARADC_SARADC_ONETIME_CHANNEL_V << APB_SARADC_SARADC_ONETIME_CHANNEL_S) +#define APB_SARADC_SARADC_ONETIME_CHANNEL_V 0x0000000FU +#define APB_SARADC_SARADC_ONETIME_CHANNEL_S 25 +/** APB_SARADC_SARADC_ONETIME_START : R/W; bitpos: [29]; default: 0; + * trigger adc onetime sample + */ +#define APB_SARADC_SARADC_ONETIME_START (BIT(29)) +#define APB_SARADC_SARADC_ONETIME_START_M (APB_SARADC_SARADC_ONETIME_START_V << APB_SARADC_SARADC_ONETIME_START_S) +#define APB_SARADC_SARADC_ONETIME_START_V 0x00000001U +#define APB_SARADC_SARADC_ONETIME_START_S 29 +/** APB_SARADC_SARADC2_ONETIME_SAMPLE : R/W; bitpos: [30]; default: 0; + * enable adc2 onetime sample + */ +#define APB_SARADC_SARADC2_ONETIME_SAMPLE (BIT(30)) +#define APB_SARADC_SARADC2_ONETIME_SAMPLE_M (APB_SARADC_SARADC2_ONETIME_SAMPLE_V << APB_SARADC_SARADC2_ONETIME_SAMPLE_S) +#define APB_SARADC_SARADC2_ONETIME_SAMPLE_V 0x00000001U +#define APB_SARADC_SARADC2_ONETIME_SAMPLE_S 30 +/** APB_SARADC_SARADC1_ONETIME_SAMPLE : R/W; bitpos: [31]; default: 0; + * enable adc1 onetime sample + */ +#define APB_SARADC_SARADC1_ONETIME_SAMPLE (BIT(31)) +#define APB_SARADC_SARADC1_ONETIME_SAMPLE_M (APB_SARADC_SARADC1_ONETIME_SAMPLE_V << APB_SARADC_SARADC1_ONETIME_SAMPLE_S) +#define APB_SARADC_SARADC1_ONETIME_SAMPLE_V 0x00000001U +#define APB_SARADC_SARADC1_ONETIME_SAMPLE_S 31 + +/** APB_SARADC_ARB_CTRL_REG register + * digital saradc configure register + */ +#define APB_SARADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x24) +/** APB_SARADC_ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0; + * adc2 arbiter force to enableapb controller + */ +#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2)) +#define APB_SARADC_ADC_ARB_APB_FORCE_M (APB_SARADC_ADC_ARB_APB_FORCE_V << APB_SARADC_ADC_ARB_APB_FORCE_S) +#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x00000001U +#define APB_SARADC_ADC_ARB_APB_FORCE_S 2 +/** APB_SARADC_ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0; + * adc2 arbiter force to enable rtc controller + */ +#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3)) +#define APB_SARADC_ADC_ARB_RTC_FORCE_M (APB_SARADC_ADC_ARB_RTC_FORCE_V << APB_SARADC_ADC_ARB_RTC_FORCE_S) +#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x00000001U +#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3 +/** APB_SARADC_ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0; + * adc2 arbiter force to enable wifi controller + */ +#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4)) +#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (APB_SARADC_ADC_ARB_WIFI_FORCE_V << APB_SARADC_ADC_ARB_WIFI_FORCE_S) +#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x00000001U +#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4 +/** APB_SARADC_ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0; + * adc2 arbiter force grant + */ +#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5)) +#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (APB_SARADC_ADC_ARB_GRANT_FORCE_V << APB_SARADC_ADC_ARB_GRANT_FORCE_S) +#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x00000001U +#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5 +/** APB_SARADC_ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0; + * Set adc2 arbiterapb priority + */ +#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003U +#define APB_SARADC_ADC_ARB_APB_PRIORITY_M (APB_SARADC_ADC_ARB_APB_PRIORITY_V << APB_SARADC_ADC_ARB_APB_PRIORITY_S) +#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x00000003U +#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6 +/** APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1; + * Set adc2 arbiter rtc priority + */ +#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003U +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M (APB_SARADC_ADC_ARB_RTC_PRIORITY_V << APB_SARADC_ADC_ARB_RTC_PRIORITY_S) +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x00000003U +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8 +/** APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2; + * Set adc2 arbiter wifi priority + */ +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003U +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M (APB_SARADC_ADC_ARB_WIFI_PRIORITY_V << APB_SARADC_ADC_ARB_WIFI_PRIORITY_S) +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x00000003U +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10 +/** APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0; + * adc2 arbiter uses fixed priority + */ +#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12)) +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (APB_SARADC_ADC_ARB_FIX_PRIORITY_V << APB_SARADC_ADC_ARB_FIX_PRIORITY_S) +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x00000001U +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12 + +/** APB_SARADC_FILTER_CTRL0_REG register + * digital saradc configure register + */ +#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x28) +/** APB_SARADC_APB_SARADC_FILTER_CHANNEL1 : R/W; bitpos: [21:18]; default: 13; + * configure filter1 to adc channel + */ +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1 0x0000000FU +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S) +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V 0x0000000FU +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S 18 +/** APB_SARADC_APB_SARADC_FILTER_CHANNEL0 : R/W; bitpos: [25:22]; default: 13; + * configure filter0 to adc channel + */ +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0 0x0000000FU +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S) +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V 0x0000000FU +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S 22 +/** APB_SARADC_APB_SARADC_FILTER_RESET : R/W; bitpos: [31]; default: 0; + * enable apb_adc1_filter + */ +#define APB_SARADC_APB_SARADC_FILTER_RESET (BIT(31)) +#define APB_SARADC_APB_SARADC_FILTER_RESET_M (APB_SARADC_APB_SARADC_FILTER_RESET_V << APB_SARADC_APB_SARADC_FILTER_RESET_S) +#define APB_SARADC_APB_SARADC_FILTER_RESET_V 0x00000001U +#define APB_SARADC_APB_SARADC_FILTER_RESET_S 31 + +/** APB_SARADC_SAR1DATA_STATUS_REG register + * digital saradc configure register + */ +#define APB_SARADC_SAR1DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x2c) +/** APB_SARADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0; + * saradc1 data + */ +#define APB_SARADC_APB_SARADC1_DATA 0x0001FFFFU +#define APB_SARADC_APB_SARADC1_DATA_M (APB_SARADC_APB_SARADC1_DATA_V << APB_SARADC_APB_SARADC1_DATA_S) +#define APB_SARADC_APB_SARADC1_DATA_V 0x0001FFFFU +#define APB_SARADC_APB_SARADC1_DATA_S 0 + +/** APB_SARADC_SAR2DATA_STATUS_REG register + * digital saradc configure register + */ +#define APB_SARADC_SAR2DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x30) +/** APB_SARADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0; + * saradc2 data + */ +#define APB_SARADC_APB_SARADC2_DATA 0x0001FFFFU +#define APB_SARADC_APB_SARADC2_DATA_M (APB_SARADC_APB_SARADC2_DATA_V << APB_SARADC_APB_SARADC2_DATA_S) +#define APB_SARADC_APB_SARADC2_DATA_V 0x0001FFFFU +#define APB_SARADC_APB_SARADC2_DATA_S 0 + +/** APB_SARADC_THRES0_CTRL_REG register + * digital saradc configure register + */ +#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x34) +/** APB_SARADC_APB_SARADC_THRES0_CHANNEL : R/W; bitpos: [3:0]; default: 13; + * configure thres0 to adc channel + */ +#define APB_SARADC_APB_SARADC_THRES0_CHANNEL 0x0000000FU +#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_M (APB_SARADC_APB_SARADC_THRES0_CHANNEL_V << APB_SARADC_APB_SARADC_THRES0_CHANNEL_S) +#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_V 0x0000000FU +#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_S 0 +/** APB_SARADC_APB_SARADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191; + * saradc thres0 monitor thres + */ +#define APB_SARADC_APB_SARADC_THRES0_HIGH 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES0_HIGH_M (APB_SARADC_APB_SARADC_THRES0_HIGH_V << APB_SARADC_APB_SARADC_THRES0_HIGH_S) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_V 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES0_HIGH_S 5 +/** APB_SARADC_APB_SARADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0; + * saradc thres0 monitor thres + */ +#define APB_SARADC_APB_SARADC_THRES0_LOW 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES0_LOW_M (APB_SARADC_APB_SARADC_THRES0_LOW_V << APB_SARADC_APB_SARADC_THRES0_LOW_S) +#define APB_SARADC_APB_SARADC_THRES0_LOW_V 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES0_LOW_S 18 + +/** APB_SARADC_THRES1_CTRL_REG register + * digital saradc configure register + */ +#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x38) +/** APB_SARADC_APB_SARADC_THRES1_CHANNEL : R/W; bitpos: [3:0]; default: 13; + * configure thres1 to adc channel + */ +#define APB_SARADC_APB_SARADC_THRES1_CHANNEL 0x0000000FU +#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_M (APB_SARADC_APB_SARADC_THRES1_CHANNEL_V << APB_SARADC_APB_SARADC_THRES1_CHANNEL_S) +#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_V 0x0000000FU +#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_S 0 +/** APB_SARADC_APB_SARADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191; + * saradc thres1 monitor thres + */ +#define APB_SARADC_APB_SARADC_THRES1_HIGH 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES1_HIGH_M (APB_SARADC_APB_SARADC_THRES1_HIGH_V << APB_SARADC_APB_SARADC_THRES1_HIGH_S) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_V 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES1_HIGH_S 5 +/** APB_SARADC_APB_SARADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0; + * saradc thres1 monitor thres + */ +#define APB_SARADC_APB_SARADC_THRES1_LOW 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES1_LOW_M (APB_SARADC_APB_SARADC_THRES1_LOW_V << APB_SARADC_APB_SARADC_THRES1_LOW_S) +#define APB_SARADC_APB_SARADC_THRES1_LOW_V 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES1_LOW_S 18 + +/** APB_SARADC_THRES_CTRL_REG register + * digital saradc configure register + */ +#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x3c) +/** APB_SARADC_APB_SARADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0; + * enable thres to all channel + */ +#define APB_SARADC_APB_SARADC_THRES_ALL_EN (BIT(27)) +#define APB_SARADC_APB_SARADC_THRES_ALL_EN_M (APB_SARADC_APB_SARADC_THRES_ALL_EN_V << APB_SARADC_APB_SARADC_THRES_ALL_EN_S) +#define APB_SARADC_APB_SARADC_THRES_ALL_EN_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES_ALL_EN_S 27 +/** APB_SARADC_APB_SARADC_THRES1_EN : R/W; bitpos: [30]; default: 0; + * enable thres1 + */ +#define APB_SARADC_APB_SARADC_THRES1_EN (BIT(30)) +#define APB_SARADC_APB_SARADC_THRES1_EN_M (APB_SARADC_APB_SARADC_THRES1_EN_V << APB_SARADC_APB_SARADC_THRES1_EN_S) +#define APB_SARADC_APB_SARADC_THRES1_EN_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_EN_S 30 +/** APB_SARADC_APB_SARADC_THRES0_EN : R/W; bitpos: [31]; default: 0; + * enable thres0 + */ +#define APB_SARADC_APB_SARADC_THRES0_EN (BIT(31)) +#define APB_SARADC_APB_SARADC_THRES0_EN_M (APB_SARADC_APB_SARADC_THRES0_EN_V << APB_SARADC_APB_SARADC_THRES0_EN_S) +#define APB_SARADC_APB_SARADC_THRES0_EN_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_EN_S 31 + +/** APB_SARADC_INT_ENA_REG register + * digital saradc int register + */ +#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x40) +/** APB_SARADC_APB_SARADC_TSENS_INT_ENA : R/W; bitpos: [25]; default: 0; + * tsens low interrupt enable + */ +#define APB_SARADC_APB_SARADC_TSENS_INT_ENA (BIT(25)) +#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_M (APB_SARADC_APB_SARADC_TSENS_INT_ENA_V << APB_SARADC_APB_SARADC_TSENS_INT_ENA_S) +#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_S 25 +/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0; + * saradc thres1 low interrupt enable + */ +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA (BIT(26)) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S 26 +/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0; + * saradc thres0 low interrupt enable + */ +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA (BIT(27)) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S 27 +/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0; + * saradc thres1 high interrupt enable + */ +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28)) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S 28 +/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0; + * saradc thres0 high interrupt enable + */ +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29)) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S 29 +/** APB_SARADC_APB_SARADC2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0; + * saradc2 done interrupt enable + */ +#define APB_SARADC_APB_SARADC2_DONE_INT_ENA (BIT(30)) +#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_M (APB_SARADC_APB_SARADC2_DONE_INT_ENA_V << APB_SARADC_APB_SARADC2_DONE_INT_ENA_S) +#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_S 30 +/** APB_SARADC_APB_SARADC1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0; + * saradc1 done interrupt enable + */ +#define APB_SARADC_APB_SARADC1_DONE_INT_ENA (BIT(31)) +#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_M (APB_SARADC_APB_SARADC1_DONE_INT_ENA_V << APB_SARADC_APB_SARADC1_DONE_INT_ENA_S) +#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_S 31 + +/** APB_SARADC_INT_RAW_REG register + * digital saradc int register + */ +#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x44) +/** APB_SARADC_APB_SARADC_TSENS_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * saradc tsens interrupt raw + */ +#define APB_SARADC_APB_SARADC_TSENS_INT_RAW (BIT(25)) +#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_M (APB_SARADC_APB_SARADC_TSENS_INT_RAW_V << APB_SARADC_APB_SARADC_TSENS_INT_RAW_S) +#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_S 25 +/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * saradc thres1 low interrupt raw + */ +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW (BIT(26)) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S 26 +/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * saradc thres0 low interrupt raw + */ +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW (BIT(27)) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S 27 +/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * saradc thres1 high interrupt raw + */ +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28)) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S 28 +/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * saradc thres0 high interrupt raw + */ +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29)) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S 29 +/** APB_SARADC_APB_SARADC2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * saradc2 done interrupt raw + */ +#define APB_SARADC_APB_SARADC2_DONE_INT_RAW (BIT(30)) +#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_M (APB_SARADC_APB_SARADC2_DONE_INT_RAW_V << APB_SARADC_APB_SARADC2_DONE_INT_RAW_S) +#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_S 30 +/** APB_SARADC_APB_SARADC1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * saradc1 done interrupt raw + */ +#define APB_SARADC_APB_SARADC1_DONE_INT_RAW (BIT(31)) +#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_M (APB_SARADC_APB_SARADC1_DONE_INT_RAW_V << APB_SARADC_APB_SARADC1_DONE_INT_RAW_S) +#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_S 31 + +/** APB_SARADC_INT_ST_REG register + * digital saradc int register + */ +#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x48) +/** APB_SARADC_APB_SARADC_TSENS_INT_ST : RO; bitpos: [25]; default: 0; + * saradc tsens interrupt state + */ +#define APB_SARADC_APB_SARADC_TSENS_INT_ST (BIT(25)) +#define APB_SARADC_APB_SARADC_TSENS_INT_ST_M (APB_SARADC_APB_SARADC_TSENS_INT_ST_V << APB_SARADC_APB_SARADC_TSENS_INT_ST_S) +#define APB_SARADC_APB_SARADC_TSENS_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC_TSENS_INT_ST_S 25 +/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0; + * saradc thres1 low interrupt state + */ +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST (BIT(26)) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S 26 +/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0; + * saradc thres0 low interrupt state + */ +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST (BIT(27)) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S 27 +/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0; + * saradc thres1 high interrupt state + */ +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST (BIT(28)) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S 28 +/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0; + * saradc thres0 high interrupt state + */ +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST (BIT(29)) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S 29 +/** APB_SARADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0; + * saradc2 done interrupt state + */ +#define APB_SARADC_APB_SARADC2_DONE_INT_ST (BIT(30)) +#define APB_SARADC_APB_SARADC2_DONE_INT_ST_M (APB_SARADC_APB_SARADC2_DONE_INT_ST_V << APB_SARADC_APB_SARADC2_DONE_INT_ST_S) +#define APB_SARADC_APB_SARADC2_DONE_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC2_DONE_INT_ST_S 30 +/** APB_SARADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0; + * saradc1 done interrupt state + */ +#define APB_SARADC_APB_SARADC1_DONE_INT_ST (BIT(31)) +#define APB_SARADC_APB_SARADC1_DONE_INT_ST_M (APB_SARADC_APB_SARADC1_DONE_INT_ST_V << APB_SARADC_APB_SARADC1_DONE_INT_ST_S) +#define APB_SARADC_APB_SARADC1_DONE_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC1_DONE_INT_ST_S 31 + +/** APB_SARADC_INT_CLR_REG register + * digital saradc int register + */ +#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x4c) +/** APB_SARADC_APB_SARADC_TSENS_INT_CLR : WT; bitpos: [25]; default: 0; + * saradc tsens interrupt clear + */ +#define APB_SARADC_APB_SARADC_TSENS_INT_CLR (BIT(25)) +#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_M (APB_SARADC_APB_SARADC_TSENS_INT_CLR_V << APB_SARADC_APB_SARADC_TSENS_INT_CLR_S) +#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_S 25 +/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0; + * saradc thres1 low interrupt clear + */ +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR (BIT(26)) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S 26 +/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0; + * saradc thres0 low interrupt clear + */ +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR (BIT(27)) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S 27 +/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0; + * saradc thres1 high interrupt clear + */ +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28)) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S 28 +/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0; + * saradc thres0 high interrupt clear + */ +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29)) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S 29 +/** APB_SARADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0; + * saradc2 done interrupt clear + */ +#define APB_SARADC_APB_SARADC2_DONE_INT_CLR (BIT(30)) +#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_M (APB_SARADC_APB_SARADC2_DONE_INT_CLR_V << APB_SARADC_APB_SARADC2_DONE_INT_CLR_S) +#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_S 30 +/** APB_SARADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0; + * saradc1 done interrupt clear + */ +#define APB_SARADC_APB_SARADC1_DONE_INT_CLR (BIT(31)) +#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_M (APB_SARADC_APB_SARADC1_DONE_INT_CLR_V << APB_SARADC_APB_SARADC1_DONE_INT_CLR_S) +#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_S 31 + +/** APB_SARADC_DMA_CONF_REG register + * digital saradc configure register + */ +#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x50) +/** APB_SARADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255; + * the dma_in_suc_eof gen when sample cnt = spi_eof_num + */ +#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFFU +#define APB_SARADC_APB_ADC_EOF_NUM_M (APB_SARADC_APB_ADC_EOF_NUM_V << APB_SARADC_APB_ADC_EOF_NUM_S) +#define APB_SARADC_APB_ADC_EOF_NUM_V 0x0000FFFFU +#define APB_SARADC_APB_ADC_EOF_NUM_S 0 +/** APB_SARADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0; + * reset_apb_adc_state + */ +#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30)) +#define APB_SARADC_APB_ADC_RESET_FSM_M (APB_SARADC_APB_ADC_RESET_FSM_V << APB_SARADC_APB_ADC_RESET_FSM_S) +#define APB_SARADC_APB_ADC_RESET_FSM_V 0x00000001U +#define APB_SARADC_APB_ADC_RESET_FSM_S 30 +/** APB_SARADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0; + * enable apb_adc use spi_dma + */ +#define APB_SARADC_APB_ADC_TRANS (BIT(31)) +#define APB_SARADC_APB_ADC_TRANS_M (APB_SARADC_APB_ADC_TRANS_V << APB_SARADC_APB_ADC_TRANS_S) +#define APB_SARADC_APB_ADC_TRANS_V 0x00000001U +#define APB_SARADC_APB_ADC_TRANS_S 31 + +/** APB_SARADC_CLKM_CONF_REG register + * digital saradc configure register + */ +#define APB_SARADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x54) +/** APB_SARADC_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4; + * Integral I2S clock divider value + */ +#define APB_SARADC_CLKM_DIV_NUM 0x000000FFU +#define APB_SARADC_CLKM_DIV_NUM_M (APB_SARADC_CLKM_DIV_NUM_V << APB_SARADC_CLKM_DIV_NUM_S) +#define APB_SARADC_CLKM_DIV_NUM_V 0x000000FFU +#define APB_SARADC_CLKM_DIV_NUM_S 0 +/** APB_SARADC_CLKM_DIV_B : R/W; bitpos: [13:8]; default: 0; + * Fractional clock divider numerator value + */ +#define APB_SARADC_CLKM_DIV_B 0x0000003FU +#define APB_SARADC_CLKM_DIV_B_M (APB_SARADC_CLKM_DIV_B_V << APB_SARADC_CLKM_DIV_B_S) +#define APB_SARADC_CLKM_DIV_B_V 0x0000003FU +#define APB_SARADC_CLKM_DIV_B_S 8 +/** APB_SARADC_CLKM_DIV_A : R/W; bitpos: [19:14]; default: 0; + * Fractional clock divider denominator value + */ +#define APB_SARADC_CLKM_DIV_A 0x0000003FU +#define APB_SARADC_CLKM_DIV_A_M (APB_SARADC_CLKM_DIV_A_V << APB_SARADC_CLKM_DIV_A_S) +#define APB_SARADC_CLKM_DIV_A_V 0x0000003FU +#define APB_SARADC_CLKM_DIV_A_S 14 +/** APB_SARADC_CLK_EN : R/W; bitpos: [20]; default: 0; + * reg clk en + */ +#define APB_SARADC_CLK_EN (BIT(20)) +#define APB_SARADC_CLK_EN_M (APB_SARADC_CLK_EN_V << APB_SARADC_CLK_EN_S) +#define APB_SARADC_CLK_EN_V 0x00000001U +#define APB_SARADC_CLK_EN_S 20 +/** APB_SARADC_CLK_SEL : R/W; bitpos: [22:21]; default: 0; + * Set this bit to enable clk_apll + */ +#define APB_SARADC_CLK_SEL 0x00000003U +#define APB_SARADC_CLK_SEL_M (APB_SARADC_CLK_SEL_V << APB_SARADC_CLK_SEL_S) +#define APB_SARADC_CLK_SEL_V 0x00000003U +#define APB_SARADC_CLK_SEL_S 21 + +/** APB_SARADC_APB_TSENS_CTRL_REG register + * digital tsens configure register + */ +#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x58) +/** APB_SARADC_TSENS_OUT : RO; bitpos: [7:0]; default: 128; + * temperature sensor data out + */ +#define APB_SARADC_TSENS_OUT 0x000000FFU +#define APB_SARADC_TSENS_OUT_M (APB_SARADC_TSENS_OUT_V << APB_SARADC_TSENS_OUT_S) +#define APB_SARADC_TSENS_OUT_V 0x000000FFU +#define APB_SARADC_TSENS_OUT_S 0 +/** APB_SARADC_TSENS_IN_INV : R/W; bitpos: [13]; default: 0; + * invert temperature sensor data + */ +#define APB_SARADC_TSENS_IN_INV (BIT(13)) +#define APB_SARADC_TSENS_IN_INV_M (APB_SARADC_TSENS_IN_INV_V << APB_SARADC_TSENS_IN_INV_S) +#define APB_SARADC_TSENS_IN_INV_V 0x00000001U +#define APB_SARADC_TSENS_IN_INV_S 13 +/** APB_SARADC_TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6; + * temperature sensor clock divider + */ +#define APB_SARADC_TSENS_CLK_DIV 0x000000FFU +#define APB_SARADC_TSENS_CLK_DIV_M (APB_SARADC_TSENS_CLK_DIV_V << APB_SARADC_TSENS_CLK_DIV_S) +#define APB_SARADC_TSENS_CLK_DIV_V 0x000000FFU +#define APB_SARADC_TSENS_CLK_DIV_S 14 +/** APB_SARADC_TSENS_PU : R/W; bitpos: [22]; default: 0; + * temperature sensor power up + */ +#define APB_SARADC_TSENS_PU (BIT(22)) +#define APB_SARADC_TSENS_PU_M (APB_SARADC_TSENS_PU_V << APB_SARADC_TSENS_PU_S) +#define APB_SARADC_TSENS_PU_V 0x00000001U +#define APB_SARADC_TSENS_PU_S 22 + +/** APB_SARADC_TSENS_CTRL2_REG register + * digital tsens configure register + */ +#define APB_SARADC_TSENS_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x5c) +/** APB_SARADC_TSENS_XPD_WAIT : R/W; bitpos: [11:0]; default: 2; + * the time that power up tsens need wait + */ +#define APB_SARADC_TSENS_XPD_WAIT 0x00000FFFU +#define APB_SARADC_TSENS_XPD_WAIT_M (APB_SARADC_TSENS_XPD_WAIT_V << APB_SARADC_TSENS_XPD_WAIT_S) +#define APB_SARADC_TSENS_XPD_WAIT_V 0x00000FFFU +#define APB_SARADC_TSENS_XPD_WAIT_S 0 +/** APB_SARADC_TSENS_XPD_FORCE : R/W; bitpos: [13:12]; default: 0; + * force power up tsens + */ +#define APB_SARADC_TSENS_XPD_FORCE 0x00000003U +#define APB_SARADC_TSENS_XPD_FORCE_M (APB_SARADC_TSENS_XPD_FORCE_V << APB_SARADC_TSENS_XPD_FORCE_S) +#define APB_SARADC_TSENS_XPD_FORCE_V 0x00000003U +#define APB_SARADC_TSENS_XPD_FORCE_S 12 +/** APB_SARADC_TSENS_CLK_INV : R/W; bitpos: [14]; default: 1; + * inv tsens clk + */ +#define APB_SARADC_TSENS_CLK_INV (BIT(14)) +#define APB_SARADC_TSENS_CLK_INV_M (APB_SARADC_TSENS_CLK_INV_V << APB_SARADC_TSENS_CLK_INV_S) +#define APB_SARADC_TSENS_CLK_INV_V 0x00000001U +#define APB_SARADC_TSENS_CLK_INV_S 14 +/** APB_SARADC_TSENS_CLK_SEL : R/W; bitpos: [15]; default: 0; + * tsens clk select + */ +#define APB_SARADC_TSENS_CLK_SEL (BIT(15)) +#define APB_SARADC_TSENS_CLK_SEL_M (APB_SARADC_TSENS_CLK_SEL_V << APB_SARADC_TSENS_CLK_SEL_S) +#define APB_SARADC_TSENS_CLK_SEL_V 0x00000001U +#define APB_SARADC_TSENS_CLK_SEL_S 15 + +/** APB_SARADC_CALI_REG register + * digital saradc configure register + */ +#define APB_SARADC_CALI_REG (DR_REG_APB_SARADC_BASE + 0x60) +/** APB_SARADC_APB_SARADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768; + * saradc cali factor + */ +#define APB_SARADC_APB_SARADC_CALI_CFG 0x0001FFFFU +#define APB_SARADC_APB_SARADC_CALI_CFG_M (APB_SARADC_APB_SARADC_CALI_CFG_V << APB_SARADC_APB_SARADC_CALI_CFG_S) +#define APB_SARADC_APB_SARADC_CALI_CFG_V 0x0001FFFFU +#define APB_SARADC_APB_SARADC_CALI_CFG_S 0 + +/** APB_TSENS_WAKE_REG register + * digital tsens configure register + */ +#define APB_TSENS_WAKE_REG (DR_REG_APB_SARADC_BASE + 0x64) +/** APB_SARADC_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0; + * reg_wakeup_th_low + */ +#define APB_SARADC_WAKEUP_TH_LOW 0x000000FFU +#define APB_SARADC_WAKEUP_TH_LOW_M (APB_SARADC_WAKEUP_TH_LOW_V << APB_SARADC_WAKEUP_TH_LOW_S) +#define APB_SARADC_WAKEUP_TH_LOW_V 0x000000FFU +#define APB_SARADC_WAKEUP_TH_LOW_S 0 +/** APB_SARADC_WAKEUP_TH_HIGH : R/W; bitpos: [15:8]; default: 255; + * reg_wakeup_th_high + */ +#define APB_SARADC_WAKEUP_TH_HIGH 0x000000FFU +#define APB_SARADC_WAKEUP_TH_HIGH_M (APB_SARADC_WAKEUP_TH_HIGH_V << APB_SARADC_WAKEUP_TH_HIGH_S) +#define APB_SARADC_WAKEUP_TH_HIGH_V 0x000000FFU +#define APB_SARADC_WAKEUP_TH_HIGH_S 8 +/** APB_SARADC_WAKEUP_OVER_UPPER_TH : RO; bitpos: [16]; default: 0; + * reg_wakeup_over_upper_th + */ +#define APB_SARADC_WAKEUP_OVER_UPPER_TH (BIT(16)) +#define APB_SARADC_WAKEUP_OVER_UPPER_TH_M (APB_SARADC_WAKEUP_OVER_UPPER_TH_V << APB_SARADC_WAKEUP_OVER_UPPER_TH_S) +#define APB_SARADC_WAKEUP_OVER_UPPER_TH_V 0x00000001U +#define APB_SARADC_WAKEUP_OVER_UPPER_TH_S 16 +/** APB_SARADC_WAKEUP_MODE : R/W; bitpos: [17]; default: 0; + * reg_wakeup_mode + */ +#define APB_SARADC_WAKEUP_MODE (BIT(17)) +#define APB_SARADC_WAKEUP_MODE_M (APB_SARADC_WAKEUP_MODE_V << APB_SARADC_WAKEUP_MODE_S) +#define APB_SARADC_WAKEUP_MODE_V 0x00000001U +#define APB_SARADC_WAKEUP_MODE_S 17 +/** APB_SARADC_WAKEUP_EN : R/W; bitpos: [18]; default: 0; + * reg_wakeup_en + */ +#define APB_SARADC_WAKEUP_EN (BIT(18)) +#define APB_SARADC_WAKEUP_EN_M (APB_SARADC_WAKEUP_EN_V << APB_SARADC_WAKEUP_EN_S) +#define APB_SARADC_WAKEUP_EN_V 0x00000001U +#define APB_SARADC_WAKEUP_EN_S 18 + +/** APB_TSENS_SAMPLE_REG register + * digital tsens configure register + */ +#define APB_TSENS_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x68) +/** APB_SARADC_TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20; + * HW sample rate + */ +#define APB_SARADC_TSENS_SAMPLE_RATE 0x0000FFFFU +#define APB_SARADC_TSENS_SAMPLE_RATE_M (APB_SARADC_TSENS_SAMPLE_RATE_V << APB_SARADC_TSENS_SAMPLE_RATE_S) +#define APB_SARADC_TSENS_SAMPLE_RATE_V 0x0000FFFFU +#define APB_SARADC_TSENS_SAMPLE_RATE_S 0 +/** APB_SARADC_TSENS_SAMPLE_EN : R/W; bitpos: [16]; default: 0; + * HW sample en + */ +#define APB_SARADC_TSENS_SAMPLE_EN (BIT(16)) +#define APB_SARADC_TSENS_SAMPLE_EN_M (APB_SARADC_TSENS_SAMPLE_EN_V << APB_SARADC_TSENS_SAMPLE_EN_S) +#define APB_SARADC_TSENS_SAMPLE_EN_V 0x00000001U +#define APB_SARADC_TSENS_SAMPLE_EN_S 16 + +/** APB_SARADC_CTRL_DATE_REG register + * version + */ +#define APB_SARADC_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3fc) +/** APB_SARADC_DATE : R/W; bitpos: [31:0]; default: 35676736; + * version + */ +#define APB_SARADC_DATE 0xFFFFFFFFU +#define APB_SARADC_DATE_M (APB_SARADC_DATE_V << APB_SARADC_DATE_S) +#define APB_SARADC_DATE_V 0xFFFFFFFFU +#define APB_SARADC_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/apb_saradc_struct.h b/components/soc/esp32c6/include/soc/apb_saradc_struct.h new file mode 100644 index 0000000000..32736d3097 --- /dev/null +++ b/components/soc/esp32c6/include/soc/apb_saradc_struct.h @@ -0,0 +1,757 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configure Register */ +/** Type of saradc_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_saradc_start_force : R/W; bitpos: [0]; default: 0; + * select software enable saradc sample + */ + uint32_t saradc_saradc_start_force:1; + /** saradc_saradc_start : R/W; bitpos: [1]; default: 0; + * software enable saradc sample + */ + uint32_t saradc_saradc_start:1; + uint32_t reserved_2:4; + /** saradc_saradc_sar_clk_gated : R/W; bitpos: [6]; default: 1; + * SAR clock gated + */ + uint32_t saradc_saradc_sar_clk_gated:1; + /** saradc_saradc_sar_clk_div : R/W; bitpos: [14:7]; default: 4; + * SAR clock divider + */ + uint32_t saradc_saradc_sar_clk_div:8; + /** saradc_saradc_sar_patt_len : R/W; bitpos: [17:15]; default: 7; + * 0 ~ 15 means length 1 ~ 16 + */ + uint32_t saradc_saradc_sar_patt_len:3; + uint32_t reserved_18:5; + /** saradc_saradc_sar_patt_p_clear : R/W; bitpos: [23]; default: 0; + * clear the pointer of pattern table for DIG ADC1 CTRL + */ + uint32_t saradc_saradc_sar_patt_p_clear:1; + uint32_t reserved_24:3; + /** saradc_saradc_xpd_sar_force : R/W; bitpos: [28:27]; default: 0; + * force option to xpd sar blocks + */ + uint32_t saradc_saradc_xpd_sar_force:2; + /** saradc_saradc2_pwdet_drv : R/W; bitpos: [29]; default: 0; + * enable saradc2 power detect driven func. + */ + uint32_t saradc_saradc2_pwdet_drv:1; + /** saradc_saradc_wait_arb_cycle : R/W; bitpos: [31:30]; default: 1; + * wait arbit signal stable after sar_done + */ + uint32_t saradc_saradc_wait_arb_cycle:2; + }; + uint32_t val; +} apb_saradc_ctrl_reg_t; + +/** Type of saradc_ctrl2 register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_saradc_meas_num_limit : R/W; bitpos: [0]; default: 0; + * enable max meas num + */ + uint32_t saradc_saradc_meas_num_limit:1; + /** saradc_saradc_max_meas_num : R/W; bitpos: [8:1]; default: 255; + * max conversion number + */ + uint32_t saradc_saradc_max_meas_num:8; + /** saradc_saradc_sar1_inv : R/W; bitpos: [9]; default: 0; + * 1: data to DIG ADC1 CTRL is inverted, otherwise not + */ + uint32_t saradc_saradc_sar1_inv:1; + /** saradc_saradc_sar2_inv : R/W; bitpos: [10]; default: 0; + * 1: data to DIG ADC2 CTRL is inverted, otherwise not + */ + uint32_t saradc_saradc_sar2_inv:1; + uint32_t reserved_11:1; + /** saradc_saradc_timer_target : R/W; bitpos: [23:12]; default: 10; + * to set saradc timer target + */ + uint32_t saradc_saradc_timer_target:12; + /** saradc_saradc_timer_en : R/W; bitpos: [24]; default: 0; + * to enable saradc timer trigger + */ + uint32_t saradc_saradc_timer_en:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} apb_saradc_ctrl2_reg_t; + +/** Type of saradc_filter_ctrl1 register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** saradc_apb_saradc_filter_factor1 : R/W; bitpos: [28:26]; default: 0; + * Factor of saradc filter1 + */ + uint32_t saradc_apb_saradc_filter_factor1:3; + /** saradc_apb_saradc_filter_factor0 : R/W; bitpos: [31:29]; default: 0; + * Factor of saradc filter0 + */ + uint32_t saradc_apb_saradc_filter_factor0:3; + }; + uint32_t val; +} apb_saradc_filter_ctrl1_reg_t; + +/** Type of saradc_fsm_wait register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_saradc_xpd_wait : R/W; bitpos: [7:0]; default: 8; + * saradc_xpd_wait + */ + uint32_t saradc_saradc_xpd_wait:8; + /** saradc_saradc_rstb_wait : R/W; bitpos: [15:8]; default: 8; + * saradc_rstb_wait + */ + uint32_t saradc_saradc_rstb_wait:8; + /** saradc_saradc_standby_wait : R/W; bitpos: [23:16]; default: 255; + * saradc_standby_wait + */ + uint32_t saradc_saradc_standby_wait:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} apb_saradc_fsm_wait_reg_t; + +/** Type of saradc_sar1_status register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_saradc_sar1_status : RO; bitpos: [31:0]; default: 536870912; + * saradc1 status about data and channel + */ + uint32_t saradc_saradc_sar1_status:32; + }; + uint32_t val; +} apb_saradc_sar1_status_reg_t; + +/** Type of saradc_sar2_status register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_saradc_sar2_status : RO; bitpos: [31:0]; default: 536870912; + * saradc2 status about data and channel + */ + uint32_t saradc_saradc_sar2_status:32; + }; + uint32_t val; +} apb_saradc_sar2_status_reg_t; + +/** Type of saradc_sar_patt_tab1 register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_saradc_sar_patt_tab1 : R/W; bitpos: [23:0]; default: 16777215; + * item 0 ~ 3 for pattern table 1 (each item one byte) + */ + uint32_t saradc_saradc_sar_patt_tab1:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} apb_saradc_sar_patt_tab1_reg_t; + +/** Type of saradc_sar_patt_tab2 register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_saradc_sar_patt_tab2 : R/W; bitpos: [23:0]; default: 16777215; + * Item 4 ~ 7 for pattern table 1 (each item one byte) + */ + uint32_t saradc_saradc_sar_patt_tab2:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} apb_saradc_sar_patt_tab2_reg_t; + +/** Type of saradc_onetime_sample register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** saradc_saradc_onetime_atten : R/W; bitpos: [24:23]; default: 0; + * configure onetime atten + */ + uint32_t saradc_saradc_onetime_atten:2; + /** saradc_saradc_onetime_channel : R/W; bitpos: [28:25]; default: 13; + * configure onetime channel + */ + uint32_t saradc_saradc_onetime_channel:4; + /** saradc_saradc_onetime_start : R/W; bitpos: [29]; default: 0; + * trigger adc onetime sample + */ + uint32_t saradc_saradc_onetime_start:1; + /** saradc_saradc2_onetime_sample : R/W; bitpos: [30]; default: 0; + * enable adc2 onetime sample + */ + uint32_t saradc_saradc2_onetime_sample:1; + /** saradc_saradc1_onetime_sample : R/W; bitpos: [31]; default: 0; + * enable adc1 onetime sample + */ + uint32_t saradc_saradc1_onetime_sample:1; + }; + uint32_t val; +} apb_saradc_onetime_sample_reg_t; + +/** Type of saradc_arb_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** saradc_adc_arb_apb_force : R/W; bitpos: [2]; default: 0; + * adc2 arbiter force to enableapb controller + */ + uint32_t saradc_adc_arb_apb_force:1; + /** saradc_adc_arb_rtc_force : R/W; bitpos: [3]; default: 0; + * adc2 arbiter force to enable rtc controller + */ + uint32_t saradc_adc_arb_rtc_force:1; + /** saradc_adc_arb_wifi_force : R/W; bitpos: [4]; default: 0; + * adc2 arbiter force to enable wifi controller + */ + uint32_t saradc_adc_arb_wifi_force:1; + /** saradc_adc_arb_grant_force : R/W; bitpos: [5]; default: 0; + * adc2 arbiter force grant + */ + uint32_t saradc_adc_arb_grant_force:1; + /** saradc_adc_arb_apb_priority : R/W; bitpos: [7:6]; default: 0; + * Set adc2 arbiterapb priority + */ + uint32_t saradc_adc_arb_apb_priority:2; + /** saradc_adc_arb_rtc_priority : R/W; bitpos: [9:8]; default: 1; + * Set adc2 arbiter rtc priority + */ + uint32_t saradc_adc_arb_rtc_priority:2; + /** saradc_adc_arb_wifi_priority : R/W; bitpos: [11:10]; default: 2; + * Set adc2 arbiter wifi priority + */ + uint32_t saradc_adc_arb_wifi_priority:2; + /** saradc_adc_arb_fix_priority : R/W; bitpos: [12]; default: 0; + * adc2 arbiter uses fixed priority + */ + uint32_t saradc_adc_arb_fix_priority:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} apb_saradc_arb_ctrl_reg_t; + +/** Type of saradc_filter_ctrl0 register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:18; + /** saradc_apb_saradc_filter_channel1 : R/W; bitpos: [21:18]; default: 13; + * configure filter1 to adc channel + */ + uint32_t saradc_apb_saradc_filter_channel1:4; + /** saradc_apb_saradc_filter_channel0 : R/W; bitpos: [25:22]; default: 13; + * configure filter0 to adc channel + */ + uint32_t saradc_apb_saradc_filter_channel0:4; + uint32_t reserved_26:5; + /** saradc_apb_saradc_filter_reset : R/W; bitpos: [31]; default: 0; + * enable apb_adc1_filter + */ + uint32_t saradc_apb_saradc_filter_reset:1; + }; + uint32_t val; +} apb_saradc_filter_ctrl0_reg_t; + +/** Type of saradc_sar1data_status register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_saradc1_data : RO; bitpos: [16:0]; default: 0; + * saradc1 data + */ + uint32_t saradc_apb_saradc1_data:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} apb_saradc_sar1data_status_reg_t; + +/** Type of saradc_sar2data_status register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_saradc2_data : RO; bitpos: [16:0]; default: 0; + * saradc2 data + */ + uint32_t saradc_apb_saradc2_data:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} apb_saradc_sar2data_status_reg_t; + +/** Type of saradc_thres0_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_saradc_thres0_channel : R/W; bitpos: [3:0]; default: 13; + * configure thres0 to adc channel + */ + uint32_t saradc_apb_saradc_thres0_channel:4; + uint32_t reserved_4:1; + /** saradc_apb_saradc_thres0_high : R/W; bitpos: [17:5]; default: 8191; + * saradc thres0 monitor thres + */ + uint32_t saradc_apb_saradc_thres0_high:13; + /** saradc_apb_saradc_thres0_low : R/W; bitpos: [30:18]; default: 0; + * saradc thres0 monitor thres + */ + uint32_t saradc_apb_saradc_thres0_low:13; + uint32_t reserved_31:1; + }; + uint32_t val; +} apb_saradc_thres0_ctrl_reg_t; + +/** Type of saradc_thres1_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_saradc_thres1_channel : R/W; bitpos: [3:0]; default: 13; + * configure thres1 to adc channel + */ + uint32_t saradc_apb_saradc_thres1_channel:4; + uint32_t reserved_4:1; + /** saradc_apb_saradc_thres1_high : R/W; bitpos: [17:5]; default: 8191; + * saradc thres1 monitor thres + */ + uint32_t saradc_apb_saradc_thres1_high:13; + /** saradc_apb_saradc_thres1_low : R/W; bitpos: [30:18]; default: 0; + * saradc thres1 monitor thres + */ + uint32_t saradc_apb_saradc_thres1_low:13; + uint32_t reserved_31:1; + }; + uint32_t val; +} apb_saradc_thres1_ctrl_reg_t; + +/** Type of saradc_thres_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** saradc_apb_saradc_thres_all_en : R/W; bitpos: [27]; default: 0; + * enable thres to all channel + */ + uint32_t saradc_apb_saradc_thres_all_en:1; + uint32_t reserved_28:2; + /** saradc_apb_saradc_thres1_en : R/W; bitpos: [30]; default: 0; + * enable thres1 + */ + uint32_t saradc_apb_saradc_thres1_en:1; + /** saradc_apb_saradc_thres0_en : R/W; bitpos: [31]; default: 0; + * enable thres0 + */ + uint32_t saradc_apb_saradc_thres0_en:1; + }; + uint32_t val; +} apb_saradc_thres_ctrl_reg_t; + +/** Type of saradc_int_ena register + * digital saradc int register + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** saradc_apb_saradc_tsens_int_ena : R/W; bitpos: [25]; default: 0; + * tsens low interrupt enable + */ + uint32_t saradc_apb_saradc_tsens_int_ena:1; + /** saradc_apb_saradc_thres1_low_int_ena : R/W; bitpos: [26]; default: 0; + * saradc thres1 low interrupt enable + */ + uint32_t saradc_apb_saradc_thres1_low_int_ena:1; + /** saradc_apb_saradc_thres0_low_int_ena : R/W; bitpos: [27]; default: 0; + * saradc thres0 low interrupt enable + */ + uint32_t saradc_apb_saradc_thres0_low_int_ena:1; + /** saradc_apb_saradc_thres1_high_int_ena : R/W; bitpos: [28]; default: 0; + * saradc thres1 high interrupt enable + */ + uint32_t saradc_apb_saradc_thres1_high_int_ena:1; + /** saradc_apb_saradc_thres0_high_int_ena : R/W; bitpos: [29]; default: 0; + * saradc thres0 high interrupt enable + */ + uint32_t saradc_apb_saradc_thres0_high_int_ena:1; + /** saradc_apb_saradc2_done_int_ena : R/W; bitpos: [30]; default: 0; + * saradc2 done interrupt enable + */ + uint32_t saradc_apb_saradc2_done_int_ena:1; + /** saradc_apb_saradc1_done_int_ena : R/W; bitpos: [31]; default: 0; + * saradc1 done interrupt enable + */ + uint32_t saradc_apb_saradc1_done_int_ena:1; + }; + uint32_t val; +} apb_saradc_int_ena_reg_t; + +/** Type of saradc_int_raw register + * digital saradc int register + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** saradc_apb_saradc_tsens_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * saradc tsens interrupt raw + */ + uint32_t saradc_apb_saradc_tsens_int_raw:1; + /** saradc_apb_saradc_thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * saradc thres1 low interrupt raw + */ + uint32_t saradc_apb_saradc_thres1_low_int_raw:1; + /** saradc_apb_saradc_thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * saradc thres0 low interrupt raw + */ + uint32_t saradc_apb_saradc_thres0_low_int_raw:1; + /** saradc_apb_saradc_thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * saradc thres1 high interrupt raw + */ + uint32_t saradc_apb_saradc_thres1_high_int_raw:1; + /** saradc_apb_saradc_thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * saradc thres0 high interrupt raw + */ + uint32_t saradc_apb_saradc_thres0_high_int_raw:1; + /** saradc_apb_saradc2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * saradc2 done interrupt raw + */ + uint32_t saradc_apb_saradc2_done_int_raw:1; + /** saradc_apb_saradc1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * saradc1 done interrupt raw + */ + uint32_t saradc_apb_saradc1_done_int_raw:1; + }; + uint32_t val; +} apb_saradc_int_raw_reg_t; + +/** Type of saradc_int_st register + * digital saradc int register + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** saradc_apb_saradc_tsens_int_st : RO; bitpos: [25]; default: 0; + * saradc tsens interrupt state + */ + uint32_t saradc_apb_saradc_tsens_int_st:1; + /** saradc_apb_saradc_thres1_low_int_st : RO; bitpos: [26]; default: 0; + * saradc thres1 low interrupt state + */ + uint32_t saradc_apb_saradc_thres1_low_int_st:1; + /** saradc_apb_saradc_thres0_low_int_st : RO; bitpos: [27]; default: 0; + * saradc thres0 low interrupt state + */ + uint32_t saradc_apb_saradc_thres0_low_int_st:1; + /** saradc_apb_saradc_thres1_high_int_st : RO; bitpos: [28]; default: 0; + * saradc thres1 high interrupt state + */ + uint32_t saradc_apb_saradc_thres1_high_int_st:1; + /** saradc_apb_saradc_thres0_high_int_st : RO; bitpos: [29]; default: 0; + * saradc thres0 high interrupt state + */ + uint32_t saradc_apb_saradc_thres0_high_int_st:1; + /** saradc_apb_saradc2_done_int_st : RO; bitpos: [30]; default: 0; + * saradc2 done interrupt state + */ + uint32_t saradc_apb_saradc2_done_int_st:1; + /** saradc_apb_saradc1_done_int_st : RO; bitpos: [31]; default: 0; + * saradc1 done interrupt state + */ + uint32_t saradc_apb_saradc1_done_int_st:1; + }; + uint32_t val; +} apb_saradc_int_st_reg_t; + +/** Type of saradc_int_clr register + * digital saradc int register + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** saradc_apb_saradc_tsens_int_clr : WT; bitpos: [25]; default: 0; + * saradc tsens interrupt clear + */ + uint32_t saradc_apb_saradc_tsens_int_clr:1; + /** saradc_apb_saradc_thres1_low_int_clr : WT; bitpos: [26]; default: 0; + * saradc thres1 low interrupt clear + */ + uint32_t saradc_apb_saradc_thres1_low_int_clr:1; + /** saradc_apb_saradc_thres0_low_int_clr : WT; bitpos: [27]; default: 0; + * saradc thres0 low interrupt clear + */ + uint32_t saradc_apb_saradc_thres0_low_int_clr:1; + /** saradc_apb_saradc_thres1_high_int_clr : WT; bitpos: [28]; default: 0; + * saradc thres1 high interrupt clear + */ + uint32_t saradc_apb_saradc_thres1_high_int_clr:1; + /** saradc_apb_saradc_thres0_high_int_clr : WT; bitpos: [29]; default: 0; + * saradc thres0 high interrupt clear + */ + uint32_t saradc_apb_saradc_thres0_high_int_clr:1; + /** saradc_apb_saradc2_done_int_clr : WT; bitpos: [30]; default: 0; + * saradc2 done interrupt clear + */ + uint32_t saradc_apb_saradc2_done_int_clr:1; + /** saradc_apb_saradc1_done_int_clr : WT; bitpos: [31]; default: 0; + * saradc1 done interrupt clear + */ + uint32_t saradc_apb_saradc1_done_int_clr:1; + }; + uint32_t val; +} apb_saradc_int_clr_reg_t; + +/** Type of saradc_dma_conf register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255; + * the dma_in_suc_eof gen when sample cnt = spi_eof_num + */ + uint32_t saradc_apb_adc_eof_num:16; + uint32_t reserved_16:14; + /** saradc_apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0; + * reset_apb_adc_state + */ + uint32_t saradc_apb_adc_reset_fsm:1; + /** saradc_apb_adc_trans : R/W; bitpos: [31]; default: 0; + * enable apb_adc use spi_dma + */ + uint32_t saradc_apb_adc_trans:1; + }; + uint32_t val; +} apb_saradc_dma_conf_reg_t; + +/** Type of saradc_clkm_conf register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_clkm_div_num : R/W; bitpos: [7:0]; default: 4; + * Integral I2S clock divider value + */ + uint32_t saradc_clkm_div_num:8; + /** saradc_clkm_div_b : R/W; bitpos: [13:8]; default: 0; + * Fractional clock divider numerator value + */ + uint32_t saradc_clkm_div_b:6; + /** saradc_clkm_div_a : R/W; bitpos: [19:14]; default: 0; + * Fractional clock divider denominator value + */ + uint32_t saradc_clkm_div_a:6; + /** saradc_clk_en : R/W; bitpos: [20]; default: 0; + * reg clk en + */ + uint32_t saradc_clk_en:1; + /** saradc_clk_sel : R/W; bitpos: [22:21]; default: 0; + * Set this bit to enable clk_apll + */ + uint32_t saradc_clk_sel:2; + uint32_t reserved_23:9; + }; + uint32_t val; +} apb_saradc_clkm_conf_reg_t; + +/** Type of saradc_apb_tsens_ctrl register + * digital tsens configure register + */ +typedef union { + struct { + /** saradc_tsens_out : RO; bitpos: [7:0]; default: 128; + * temperature sensor data out + */ + uint32_t saradc_tsens_out:8; + uint32_t reserved_8:5; + /** saradc_tsens_in_inv : R/W; bitpos: [13]; default: 0; + * invert temperature sensor data + */ + uint32_t saradc_tsens_in_inv:1; + /** saradc_tsens_clk_div : R/W; bitpos: [21:14]; default: 6; + * temperature sensor clock divider + */ + uint32_t saradc_tsens_clk_div:8; + /** saradc_tsens_pu : R/W; bitpos: [22]; default: 0; + * temperature sensor power up + */ + uint32_t saradc_tsens_pu:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} apb_saradc_apb_tsens_ctrl_reg_t; + +/** Type of saradc_tsens_ctrl2 register + * digital tsens configure register + */ +typedef union { + struct { + /** saradc_tsens_xpd_wait : R/W; bitpos: [11:0]; default: 2; + * the time that power up tsens need wait + */ + uint32_t saradc_tsens_xpd_wait:12; + /** saradc_tsens_xpd_force : R/W; bitpos: [13:12]; default: 0; + * force power up tsens + */ + uint32_t saradc_tsens_xpd_force:2; + /** saradc_tsens_clk_inv : R/W; bitpos: [14]; default: 1; + * inv tsens clk + */ + uint32_t saradc_tsens_clk_inv:1; + /** saradc_tsens_clk_sel : R/W; bitpos: [15]; default: 0; + * tsens clk select + */ + uint32_t saradc_tsens_clk_sel:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} apb_saradc_tsens_ctrl2_reg_t; + +/** Type of saradc_cali register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_saradc_cali_cfg : R/W; bitpos: [16:0]; default: 32768; + * saradc cali factor + */ + uint32_t saradc_apb_saradc_cali_cfg:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} apb_saradc_cali_reg_t; + +/** Type of tsens_wake register + * digital tsens configure register + */ +typedef union { + struct { + /** saradc_wakeup_th_low : R/W; bitpos: [7:0]; default: 0; + * reg_wakeup_th_low + */ + uint32_t saradc_wakeup_th_low:8; + /** saradc_wakeup_th_high : R/W; bitpos: [15:8]; default: 255; + * reg_wakeup_th_high + */ + uint32_t saradc_wakeup_th_high:8; + /** saradc_wakeup_over_upper_th : RO; bitpos: [16]; default: 0; + * reg_wakeup_over_upper_th + */ + uint32_t saradc_wakeup_over_upper_th:1; + /** saradc_wakeup_mode : R/W; bitpos: [17]; default: 0; + * reg_wakeup_mode + */ + uint32_t saradc_wakeup_mode:1; + /** saradc_wakeup_en : R/W; bitpos: [18]; default: 0; + * reg_wakeup_en + */ + uint32_t saradc_wakeup_en:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} apb_tsens_wake_reg_t; + +/** Type of tsens_sample register + * digital tsens configure register + */ +typedef union { + struct { + /** saradc_tsens_sample_rate : R/W; bitpos: [15:0]; default: 20; + * HW sample rate + */ + uint32_t saradc_tsens_sample_rate:16; + /** saradc_tsens_sample_en : R/W; bitpos: [16]; default: 0; + * HW sample en + */ + uint32_t saradc_tsens_sample_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} apb_tsens_sample_reg_t; + +/** Type of saradc_ctrl_date register + * version + */ +typedef union { + struct { + /** saradc_date : R/W; bitpos: [31:0]; default: 35676736; + * version + */ + uint32_t saradc_date:32; + }; + uint32_t val; +} apb_saradc_ctrl_date_reg_t; + + +typedef struct apb_dev_t { + volatile apb_saradc_ctrl_reg_t saradc_ctrl; + volatile apb_saradc_ctrl2_reg_t saradc_ctrl2; + volatile apb_saradc_filter_ctrl1_reg_t saradc_filter_ctrl1; + volatile apb_saradc_fsm_wait_reg_t saradc_fsm_wait; + volatile apb_saradc_sar1_status_reg_t saradc_sar1_status; + volatile apb_saradc_sar2_status_reg_t saradc_sar2_status; + volatile apb_saradc_sar_patt_tab1_reg_t saradc_sar_patt_tab1; + volatile apb_saradc_sar_patt_tab2_reg_t saradc_sar_patt_tab2; + volatile apb_saradc_onetime_sample_reg_t saradc_onetime_sample; + volatile apb_saradc_arb_ctrl_reg_t saradc_arb_ctrl; + volatile apb_saradc_filter_ctrl0_reg_t saradc_filter_ctrl0; + volatile apb_saradc_sar1data_status_reg_t saradc_sar1data_status; + volatile apb_saradc_sar2data_status_reg_t saradc_sar2data_status; + volatile apb_saradc_thres0_ctrl_reg_t saradc_thres0_ctrl; + volatile apb_saradc_thres1_ctrl_reg_t saradc_thres1_ctrl; + volatile apb_saradc_thres_ctrl_reg_t saradc_thres_ctrl; + volatile apb_saradc_int_ena_reg_t saradc_int_ena; + volatile apb_saradc_int_raw_reg_t saradc_int_raw; + volatile apb_saradc_int_st_reg_t saradc_int_st; + volatile apb_saradc_int_clr_reg_t saradc_int_clr; + volatile apb_saradc_dma_conf_reg_t saradc_dma_conf; + volatile apb_saradc_clkm_conf_reg_t saradc_clkm_conf; + volatile apb_saradc_apb_tsens_ctrl_reg_t saradc_apb_tsens_ctrl; + volatile apb_saradc_tsens_ctrl2_reg_t saradc_tsens_ctrl2; + volatile apb_saradc_cali_reg_t saradc_cali; + volatile apb_tsens_wake_reg_t tsens_wake; + volatile apb_tsens_sample_reg_t tsens_sample; + uint32_t reserved_06c[228]; + volatile apb_saradc_ctrl_date_reg_t saradc_ctrl_date; +} apb_dev_t; + +extern apb_dev_t APB_SARADC; + +#ifndef __cplusplus +_Static_assert(sizeof(apb_dev_t) == 0x400, "Invalid size of apb_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/assist_debug_reg.h b/components/soc/esp32c6/include/soc/assist_debug_reg.h new file mode 100644 index 0000000000..e77c2575d6 --- /dev/null +++ b/components/soc/esp32c6/include/soc/assist_debug_reg.h @@ -0,0 +1,778 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register + * core0 monitor enable configuration register + */ +#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor enable + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor enable + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9 +/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [10]; default: 0; + * IBUS busy monitor enable + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10 +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0; + * DBUS busy monitor enbale + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S 11 + +/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register + * core0 monitor interrupt status register + */ +#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9 +/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [10]; default: 0; + * IBUS busy monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S 10 +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [11]; default: 0; + * DBUS busy monitor initerrupt status + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S 11 + +/** ASSIST_DEBUG_CORE_0_INTR_RLS_REG register + * core0 monitor interrupt enable register + */ +#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S 0 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S 1 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S 2 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S 3 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S 4 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S 5 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S 6 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S 7 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S 8 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S 9 +/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [10]; default: 0; + * IBUS busy monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S 10 +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [11]; default: 0; + * DBUS busy monitor interrupt enbale + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S 11 + +/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register + * core0 monitor interrupt clr register + */ +#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9 +/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [10]; default: 0; + * IBUS busy monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S 10 +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [11]; default: 0; + * DBUS busy monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S 11 + +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register + * core0 dram0 region0 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 dram0 region0 start addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register + * core0 dram0 region0 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0; + * Core0 dram0 region0 end addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register + * core0 dram0 region1 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 dram0 region1 start addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register + * core0 dram0 region1 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0; + * Core0 dram0 region1 end addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register + * core0 PIF region0 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20) +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 PIF region0 start addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register + * core0 PIF region0 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24) +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0; + * Core0 PIF region0 end addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register + * core0 PIF region1 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28) +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 PIF region1 start addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register + * core0 PIF region1 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c) +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0; + * Core0 PIF region1 end addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register + * core0 area pc status register + */ +#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30) +/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0; + * the stackpointer when first touch region monitor interrupt + */ +#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PC_M (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S) +#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register + * core0 area sp status register + */ +#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34) +/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0; + * the PC when first touch region monitor interrupt + */ +#define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_SP_M (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S) +#define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_SP_S 0 + +/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register + * stack min value + */ +#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38) +/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0; + * core0 sp region configuration regsiter + */ +#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S) +#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register + * stack max value + */ +#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c) +/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295; + * core0 sp pc status register + */ +#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_MAX_M (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S) +#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_SP_PC_REG register + * stack monitor pc status register + */ +#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40) +/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0; + * This regsiter stores the PC when trigger stack monitor. + */ +#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S) +#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_PC_S 0 + +/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register + * record enable configuration register + */ +#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44) +/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable record PC + */ +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0)) +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S) +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0 +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0; + * Set 1 to enable cpu pdebug function, must set this bit can get cpu PC + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1)) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1 + +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register + * record status regsiter + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48) +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0; + * recorded PC + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0 + +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register + * record status regsiter + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c) +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0; + * recorded sp + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0 + +/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register + * exception monitor status register0 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50) +/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0; + * reg_core_0_iram0_recording_addr_0 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 0x00FFFFFFU +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V 0x00FFFFFFU +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S 0 +/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0; + * reg_core_0_iram0_recording_wr_0 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 (BIT(24)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S 24 +/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [25]; default: 0; + * reg_core_0_iram0_recording_loadstore_0 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 (BIT(25)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S 25 + +/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register + * exception monitor status register1 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54) +/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0; + * reg_core_0_iram0_recording_addr_1 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 0x00FFFFFFU +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V 0x00FFFFFFU +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S 0 +/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0; + * reg_core_0_iram0_recording_wr_1 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 (BIT(24)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S 24 +/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [25]; default: 0; + * reg_core_0_iram0_recording_loadstore_1 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 (BIT(25)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S 25 + +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register + * exception monitor status register2 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58) +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0; + * reg_core_0_dram0_recording_addr_0 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 0x00FFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V 0x00FFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S 0 +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0; + * reg_core_0_dram0_recording_wr_0 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 (BIT(24)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S 24 +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [28:25]; default: 0; + * reg_core_0_dram0_recording_byteen_0 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 0x0000000FU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V 0x0000000FU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S 25 + +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register + * exception monitor status register3 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c) +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0; + * reg_core_0_dram0_recording_pc_0 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S 0 + +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register + * exception monitor status register4 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60) +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0; + * reg_core_0_dram0_recording_addr_1 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 0x00FFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V 0x00FFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S 0 +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0; + * reg_core_0_dram0_recording_wr_1 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 (BIT(24)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S 24 +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [28:25]; default: 0; + * reg_core_0_dram0_recording_byteen_1 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 0x0000000FU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V 0x0000000FU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S 25 + +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register + * exception monitor status register5 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64) +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0; + * reg_core_0_dram0_recording_pc_1 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S 0 + +/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register + * exception monitor status register6 + */ +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68) +/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0; + * reg_core_x_iram0_dram0_limit_cycle_0 + */ +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFFU +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S) +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0x000FFFFFU +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S 0 + +/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register + * exception monitor status register7 + */ +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c) +/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0; + * reg_core_x_iram0_dram0_limit_cycle_1 + */ +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 0x000FFFFFU +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S) +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V 0x000FFFFFU +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S 0 + +/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register + * cpu status register + */ +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70) +/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0; + * cpu's lastpc before exception + */ +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S) +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0 + +/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register + * cpu status register + */ +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74) +/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0; + * cpu debug mode status, 1 means cpu enter debug mode. + */ +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0)) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0 +/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0; + * cpu debug_module active status + */ +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1)) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1 + +/** ASSIST_DEBUG_CLOCK_GATE_REG register + * clock register + */ +#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x78) +/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 force on the clock gate + */ +#define ASSIST_DEBUG_CLK_EN (BIT(0)) +#define ASSIST_DEBUG_CLK_EN_M (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S) +#define ASSIST_DEBUG_CLK_EN_V 0x00000001U +#define ASSIST_DEBUG_CLK_EN_S 0 + +/** ASSIST_DEBUG_DATE_REG register + * version register + */ +#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc) +/** ASSIST_DEBUG_ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34640176; + * version register + */ +#define ASSIST_DEBUG_ASSIST_DEBUG_DATE 0x0FFFFFFFU +#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_M (ASSIST_DEBUG_ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_ASSIST_DEBUG_DATE_S) +#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_V 0x0FFFFFFFU +#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/assist_debug_struct.h b/components/soc/esp32c6/include/soc/assist_debug_struct.h new file mode 100644 index 0000000000..24c28c33ef --- /dev/null +++ b/components/soc/esp32c6/include/soc/assist_debug_struct.h @@ -0,0 +1,717 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: monitor configuration registers */ +/** Type of core_0_intr_ena register + * core0 monitor enable configuration register + */ +typedef union { + struct { + /** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor enable + */ + uint32_t core_0_area_dram0_0_rd_ena:1; + /** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor enable + */ + uint32_t core_0_area_dram0_0_wr_ena:1; + /** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor enable + */ + uint32_t core_0_area_dram0_1_rd_ena:1; + /** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor enable + */ + uint32_t core_0_area_dram0_1_wr_ena:1; + /** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor enable + */ + uint32_t core_0_area_pif_0_rd_ena:1; + /** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor enable + */ + uint32_t core_0_area_pif_0_wr_ena:1; + /** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor enable + */ + uint32_t core_0_area_pif_1_rd_ena:1; + /** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor enable + */ + uint32_t core_0_area_pif_1_wr_ena:1; + /** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor enable + */ + uint32_t core_0_sp_spill_min_ena:1; + /** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor enable + */ + uint32_t core_0_sp_spill_max_ena:1; + /** core_0_iram0_exception_monitor_ena : R/W; bitpos: [10]; default: 0; + * IBUS busy monitor enable + */ + uint32_t core_0_iram0_exception_monitor_ena:1; + /** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0; + * DBUS busy monitor enbale + */ + uint32_t core_0_dram0_exception_monitor_ena:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} assist_debug_core_0_intr_ena_reg_t; + +/** Type of core_0_area_dram0_0_min register + * core0 dram0 region0 addr configuration register + */ +typedef union { + struct { + /** core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 dram0 region0 start addr + */ + uint32_t core_0_area_dram0_0_min:32; + }; + uint32_t val; +} assist_debug_core_0_area_dram0_0_min_reg_t; + +/** Type of core_0_area_dram0_0_max register + * core0 dram0 region0 addr configuration register + */ +typedef union { + struct { + /** core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0; + * Core0 dram0 region0 end addr + */ + uint32_t core_0_area_dram0_0_max:32; + }; + uint32_t val; +} assist_debug_core_0_area_dram0_0_max_reg_t; + +/** Type of core_0_area_dram0_1_min register + * core0 dram0 region1 addr configuration register + */ +typedef union { + struct { + /** core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 dram0 region1 start addr + */ + uint32_t core_0_area_dram0_1_min:32; + }; + uint32_t val; +} assist_debug_core_0_area_dram0_1_min_reg_t; + +/** Type of core_0_area_dram0_1_max register + * core0 dram0 region1 addr configuration register + */ +typedef union { + struct { + /** core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0; + * Core0 dram0 region1 end addr + */ + uint32_t core_0_area_dram0_1_max:32; + }; + uint32_t val; +} assist_debug_core_0_area_dram0_1_max_reg_t; + +/** Type of core_0_area_pif_0_min register + * core0 PIF region0 addr configuration register + */ +typedef union { + struct { + /** core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 PIF region0 start addr + */ + uint32_t core_0_area_pif_0_min:32; + }; + uint32_t val; +} assist_debug_core_0_area_pif_0_min_reg_t; + +/** Type of core_0_area_pif_0_max register + * core0 PIF region0 addr configuration register + */ +typedef union { + struct { + /** core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0; + * Core0 PIF region0 end addr + */ + uint32_t core_0_area_pif_0_max:32; + }; + uint32_t val; +} assist_debug_core_0_area_pif_0_max_reg_t; + +/** Type of core_0_area_pif_1_min register + * core0 PIF region1 addr configuration register + */ +typedef union { + struct { + /** core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 PIF region1 start addr + */ + uint32_t core_0_area_pif_1_min:32; + }; + uint32_t val; +} assist_debug_core_0_area_pif_1_min_reg_t; + +/** Type of core_0_area_pif_1_max register + * core0 PIF region1 addr configuration register + */ +typedef union { + struct { + /** core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0; + * Core0 PIF region1 end addr + */ + uint32_t core_0_area_pif_1_max:32; + }; + uint32_t val; +} assist_debug_core_0_area_pif_1_max_reg_t; + +/** Type of core_0_area_pc register + * core0 area pc status register + */ +typedef union { + struct { + /** core_0_area_pc : RO; bitpos: [31:0]; default: 0; + * the stackpointer when first touch region monitor interrupt + */ + uint32_t core_0_area_pc:32; + }; + uint32_t val; +} assist_debug_core_0_area_pc_reg_t; + +/** Type of core_0_area_sp register + * core0 area sp status register + */ +typedef union { + struct { + /** core_0_area_sp : RO; bitpos: [31:0]; default: 0; + * the PC when first touch region monitor interrupt + */ + uint32_t core_0_area_sp:32; + }; + uint32_t val; +} assist_debug_core_0_area_sp_reg_t; + +/** Type of core_0_sp_min register + * stack min value + */ +typedef union { + struct { + /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0; + * core0 sp region configuration regsiter + */ + uint32_t core_0_sp_min:32; + }; + uint32_t val; +} assist_debug_core_0_sp_min_reg_t; + +/** Type of core_0_sp_max register + * stack max value + */ +typedef union { + struct { + /** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295; + * core0 sp pc status register + */ + uint32_t core_0_sp_max:32; + }; + uint32_t val; +} assist_debug_core_0_sp_max_reg_t; + +/** Type of core_0_sp_pc register + * stack monitor pc status register + */ +typedef union { + struct { + /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0; + * This regsiter stores the PC when trigger stack monitor. + */ + uint32_t core_0_sp_pc:32; + }; + uint32_t val; +} assist_debug_core_0_sp_pc_reg_t; + + +/** Group: interrupt configuration register */ +/** Type of core_0_intr_raw register + * core0 monitor interrupt status register + */ +typedef union { + struct { + /** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt status + */ + uint32_t core_0_area_dram0_0_rd_raw:1; + /** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt status + */ + uint32_t core_0_area_dram0_0_wr_raw:1; + /** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt status + */ + uint32_t core_0_area_dram0_1_rd_raw:1; + /** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt status + */ + uint32_t core_0_area_dram0_1_wr_raw:1; + /** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt status + */ + uint32_t core_0_area_pif_0_rd_raw:1; + /** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt status + */ + uint32_t core_0_area_pif_0_wr_raw:1; + /** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt status + */ + uint32_t core_0_area_pif_1_rd_raw:1; + /** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt status + */ + uint32_t core_0_area_pif_1_wr_raw:1; + /** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt status + */ + uint32_t core_0_sp_spill_min_raw:1; + /** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt status + */ + uint32_t core_0_sp_spill_max_raw:1; + /** core_0_iram0_exception_monitor_raw : RO; bitpos: [10]; default: 0; + * IBUS busy monitor interrupt status + */ + uint32_t core_0_iram0_exception_monitor_raw:1; + /** core_0_dram0_exception_monitor_raw : RO; bitpos: [11]; default: 0; + * DBUS busy monitor initerrupt status + */ + uint32_t core_0_dram0_exception_monitor_raw:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} assist_debug_core_0_intr_raw_reg_t; + +/** Type of core_0_intr_rls register + * core0 monitor interrupt enable register + */ +typedef union { + struct { + /** core_0_area_dram0_0_rd_rls : R/W; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt enable + */ + uint32_t core_0_area_dram0_0_rd_rls:1; + /** core_0_area_dram0_0_wr_rls : R/W; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt enable + */ + uint32_t core_0_area_dram0_0_wr_rls:1; + /** core_0_area_dram0_1_rd_rls : R/W; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt enable + */ + uint32_t core_0_area_dram0_1_rd_rls:1; + /** core_0_area_dram0_1_wr_rls : R/W; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt enable + */ + uint32_t core_0_area_dram0_1_wr_rls:1; + /** core_0_area_pif_0_rd_rls : R/W; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt enable + */ + uint32_t core_0_area_pif_0_rd_rls:1; + /** core_0_area_pif_0_wr_rls : R/W; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt enable + */ + uint32_t core_0_area_pif_0_wr_rls:1; + /** core_0_area_pif_1_rd_rls : R/W; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt enable + */ + uint32_t core_0_area_pif_1_rd_rls:1; + /** core_0_area_pif_1_wr_rls : R/W; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt enable + */ + uint32_t core_0_area_pif_1_wr_rls:1; + /** core_0_sp_spill_min_rls : R/W; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt enable + */ + uint32_t core_0_sp_spill_min_rls:1; + /** core_0_sp_spill_max_rls : R/W; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt enable + */ + uint32_t core_0_sp_spill_max_rls:1; + /** core_0_iram0_exception_monitor_rls : R/W; bitpos: [10]; default: 0; + * IBUS busy monitor interrupt enable + */ + uint32_t core_0_iram0_exception_monitor_rls:1; + /** core_0_dram0_exception_monitor_rls : R/W; bitpos: [11]; default: 0; + * DBUS busy monitor interrupt enbale + */ + uint32_t core_0_dram0_exception_monitor_rls:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} assist_debug_core_0_intr_rls_reg_t; + +/** Type of core_0_intr_clr register + * core0 monitor interrupt clr register + */ +typedef union { + struct { + /** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt clr + */ + uint32_t core_0_area_dram0_0_rd_clr:1; + /** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt clr + */ + uint32_t core_0_area_dram0_0_wr_clr:1; + /** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt clr + */ + uint32_t core_0_area_dram0_1_rd_clr:1; + /** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt clr + */ + uint32_t core_0_area_dram0_1_wr_clr:1; + /** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt clr + */ + uint32_t core_0_area_pif_0_rd_clr:1; + /** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt clr + */ + uint32_t core_0_area_pif_0_wr_clr:1; + /** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt clr + */ + uint32_t core_0_area_pif_1_rd_clr:1; + /** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt clr + */ + uint32_t core_0_area_pif_1_wr_clr:1; + /** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt clr + */ + uint32_t core_0_sp_spill_min_clr:1; + /** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt clr + */ + uint32_t core_0_sp_spill_max_clr:1; + /** core_0_iram0_exception_monitor_clr : WT; bitpos: [10]; default: 0; + * IBUS busy monitor interrupt clr + */ + uint32_t core_0_iram0_exception_monitor_clr:1; + /** core_0_dram0_exception_monitor_clr : WT; bitpos: [11]; default: 0; + * DBUS busy monitor interrupt clr + */ + uint32_t core_0_dram0_exception_monitor_clr:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} assist_debug_core_0_intr_clr_reg_t; + + +/** Group: pc reording configuration register */ +/** Type of core_0_rcd_en register + * record enable configuration register + */ +typedef union { + struct { + /** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0; + * Set 1 to enable record PC + */ + uint32_t core_0_rcd_recorden:1; + /** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0; + * Set 1 to enable cpu pdebug function, must set this bit can get cpu PC + */ + uint32_t core_0_rcd_pdebugen:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} assist_debug_core_0_rcd_en_reg_t; + + +/** Group: pc reording status register */ +/** Type of core_0_rcd_pdebugpc register + * record status regsiter + */ +typedef union { + struct { + /** core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0; + * recorded PC + */ + uint32_t core_0_rcd_pdebugpc:32; + }; + uint32_t val; +} assist_debug_core_0_rcd_pdebugpc_reg_t; + +/** Type of core_0_rcd_pdebugsp register + * record status regsiter + */ +typedef union { + struct { + /** core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0; + * recorded sp + */ + uint32_t core_0_rcd_pdebugsp:32; + }; + uint32_t val; +} assist_debug_core_0_rcd_pdebugsp_reg_t; + + +/** Group: exception monitor regsiter */ +/** Type of core_0_iram0_exception_monitor_0 register + * exception monitor status register0 + */ +typedef union { + struct { + /** core_0_iram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0; + * reg_core_0_iram0_recording_addr_0 + */ + uint32_t core_0_iram0_recording_addr_0:24; + /** core_0_iram0_recording_wr_0 : RO; bitpos: [24]; default: 0; + * reg_core_0_iram0_recording_wr_0 + */ + uint32_t core_0_iram0_recording_wr_0:1; + /** core_0_iram0_recording_loadstore_0 : RO; bitpos: [25]; default: 0; + * reg_core_0_iram0_recording_loadstore_0 + */ + uint32_t core_0_iram0_recording_loadstore_0:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} assist_debug_core_0_iram0_exception_monitor_0_reg_t; + +/** Type of core_0_iram0_exception_monitor_1 register + * exception monitor status register1 + */ +typedef union { + struct { + /** core_0_iram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0; + * reg_core_0_iram0_recording_addr_1 + */ + uint32_t core_0_iram0_recording_addr_1:24; + /** core_0_iram0_recording_wr_1 : RO; bitpos: [24]; default: 0; + * reg_core_0_iram0_recording_wr_1 + */ + uint32_t core_0_iram0_recording_wr_1:1; + /** core_0_iram0_recording_loadstore_1 : RO; bitpos: [25]; default: 0; + * reg_core_0_iram0_recording_loadstore_1 + */ + uint32_t core_0_iram0_recording_loadstore_1:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} assist_debug_core_0_iram0_exception_monitor_1_reg_t; + +/** Type of core_0_dram0_exception_monitor_0 register + * exception monitor status register2 + */ +typedef union { + struct { + /** core_0_dram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0; + * reg_core_0_dram0_recording_addr_0 + */ + uint32_t core_0_dram0_recording_addr_0:24; + /** core_0_dram0_recording_wr_0 : RO; bitpos: [24]; default: 0; + * reg_core_0_dram0_recording_wr_0 + */ + uint32_t core_0_dram0_recording_wr_0:1; + /** core_0_dram0_recording_byteen_0 : RO; bitpos: [28:25]; default: 0; + * reg_core_0_dram0_recording_byteen_0 + */ + uint32_t core_0_dram0_recording_byteen_0:4; + uint32_t reserved_29:3; + }; + uint32_t val; +} assist_debug_core_0_dram0_exception_monitor_0_reg_t; + +/** Type of core_0_dram0_exception_monitor_1 register + * exception monitor status register3 + */ +typedef union { + struct { + /** core_0_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0; + * reg_core_0_dram0_recording_pc_0 + */ + uint32_t core_0_dram0_recording_pc_0:32; + }; + uint32_t val; +} assist_debug_core_0_dram0_exception_monitor_1_reg_t; + +/** Type of core_0_dram0_exception_monitor_2 register + * exception monitor status register4 + */ +typedef union { + struct { + /** core_0_dram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0; + * reg_core_0_dram0_recording_addr_1 + */ + uint32_t core_0_dram0_recording_addr_1:24; + /** core_0_dram0_recording_wr_1 : RO; bitpos: [24]; default: 0; + * reg_core_0_dram0_recording_wr_1 + */ + uint32_t core_0_dram0_recording_wr_1:1; + /** core_0_dram0_recording_byteen_1 : RO; bitpos: [28:25]; default: 0; + * reg_core_0_dram0_recording_byteen_1 + */ + uint32_t core_0_dram0_recording_byteen_1:4; + uint32_t reserved_29:3; + }; + uint32_t val; +} assist_debug_core_0_dram0_exception_monitor_2_reg_t; + +/** Type of core_0_dram0_exception_monitor_3 register + * exception monitor status register5 + */ +typedef union { + struct { + /** core_0_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0; + * reg_core_0_dram0_recording_pc_1 + */ + uint32_t core_0_dram0_recording_pc_1:32; + }; + uint32_t val; +} assist_debug_core_0_dram0_exception_monitor_3_reg_t; + +/** Type of core_x_iram0_dram0_exception_monitor_0 register + * exception monitor status register6 + */ +typedef union { + struct { + /** core_x_iram0_dram0_limit_cycle_0 : R/W; bitpos: [19:0]; default: 0; + * reg_core_x_iram0_dram0_limit_cycle_0 + */ + uint32_t core_x_iram0_dram0_limit_cycle_0:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t; + +/** Type of core_x_iram0_dram0_exception_monitor_1 register + * exception monitor status register7 + */ +typedef union { + struct { + /** core_x_iram0_dram0_limit_cycle_1 : R/W; bitpos: [19:0]; default: 0; + * reg_core_x_iram0_dram0_limit_cycle_1 + */ + uint32_t core_x_iram0_dram0_limit_cycle_1:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t; + + +/** Group: cpu status registers */ +/** Type of core_0_lastpc_before_exception register + * cpu status register + */ +typedef union { + struct { + /** core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0; + * cpu's lastpc before exception + */ + uint32_t core_0_lastpc_before_exc:32; + }; + uint32_t val; +} assist_debug_core_0_lastpc_before_exception_reg_t; + +/** Type of core_0_debug_mode register + * cpu status register + */ +typedef union { + struct { + /** core_0_debug_mode : RO; bitpos: [0]; default: 0; + * cpu debug mode status, 1 means cpu enter debug mode. + */ + uint32_t core_0_debug_mode:1; + /** core_0_debug_module_active : RO; bitpos: [1]; default: 0; + * cpu debug_module active status + */ + uint32_t core_0_debug_module_active:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} assist_debug_core_0_debug_mode_reg_t; + + +/** Group: Configuration Registers */ +/** Type of clock_gate register + * clock register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 force on the clock gate + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} assist_debug_clock_gate_reg_t; + +/** Type of date register + * version register + */ +typedef union { + struct { + /** assist_debug_date : R/W; bitpos: [27:0]; default: 34640176; + * version register + */ + uint32_t assist_debug_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} assist_debug_date_reg_t; + + +typedef struct assist_debug_dev_t { + volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena; + volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw; + volatile assist_debug_core_0_intr_rls_reg_t core_0_intr_rls; + volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr; + volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min; + volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max; + volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min; + volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max; + volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min; + volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max; + volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min; + volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max; + volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc; + volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp; + volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min; + volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max; + volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc; + volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en; + volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc; + volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp; + volatile assist_debug_core_0_iram0_exception_monitor_0_reg_t core_0_iram0_exception_monitor_0; + volatile assist_debug_core_0_iram0_exception_monitor_1_reg_t core_0_iram0_exception_monitor_1; + volatile assist_debug_core_0_dram0_exception_monitor_0_reg_t core_0_dram0_exception_monitor_0; + volatile assist_debug_core_0_dram0_exception_monitor_1_reg_t core_0_dram0_exception_monitor_1; + volatile assist_debug_core_0_dram0_exception_monitor_2_reg_t core_0_dram0_exception_monitor_2; + volatile assist_debug_core_0_dram0_exception_monitor_3_reg_t core_0_dram0_exception_monitor_3; + volatile assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0; + volatile assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t core_x_iram0_dram0_exception_monitor_1; + volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception; + volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode; + volatile assist_debug_clock_gate_reg_t clock_gate; + uint32_t reserved_07c[224]; + volatile assist_debug_date_reg_t date; +} assist_debug_dev_t; + +extern assist_debug_dev_t ASSIST_DEBUG; + +#ifndef __cplusplus +_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/boot_mode.h b/components/soc/esp32c6/include/soc/boot_mode.h new file mode 100644 index 0000000000..3921a29c56 --- /dev/null +++ b/components/soc/esp32c6/include/soc/boot_mode.h @@ -0,0 +1,93 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_BOOT_MODE_H_ +#define _SOC_BOOT_MODE_H_ + +#include "soc.h" + +/*SPI Boot*/ +#define IS_1XXX(v) (((v)&0x08)==0x08) + +/*Download Boot, SPI(or SDIO_V2)/UART0*/ +#define IS_00XX(v) (((v)&0x0c)==0x00) + +/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/ +#define IS_0000(v) (((v)&0x0f)==0x00) + +/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/ +#define IS_0001(v) (((v)&0x0f)==0x01) + +/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/ +#define IS_0010(v) (((v)&0x0f)==0x02) + +/*Download Boot, SDIO/UART0/UART1,REI_REO V2*/ +#define IS_0011(v) (((v)&0x0f)==0x03) + +/*legacy SPI Boot*/ +#define IS_0100(v) (((v)&0x0f)==0x04) + +/*ATE/ANALOG Mode*/ +#define IS_0101(v) (((v)&0x0f)==0x05) + +/*SPI(or SDIO_V1) download Mode*/ +#define IS_0110(v) (((v)&0x0f)==0x06) + +/*Diagnostic Mode+UART0 download Mode*/ +#define IS_0111(v) (((v)&0x0f)==0x07) + + + +#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG)) + +/*do not include download mode*/ +#define ETS_IS_UART_BOOT() IS_0111(BOOT_MODE_GET()) + +/*all spi boot including spi/legacy*/ +#define ETS_IS_FLASH_BOOT() (IS_1XXX(BOOT_MODE_GET()) || IS_0100(BOOT_MODE_GET())) + +/*all faster spi boot including spi*/ +#define ETS_IS_FAST_FLASH_BOOT() IS_1XXX(BOOT_MODE_GET()) + +#if SUPPORT_SDIO_DOWNLOAD + +/*all sdio V2 of failing edge input, failing edge output*/ +#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_0000(BOOT_MODE_GET()) + +/*all sdio V2 of failing edge input, raising edge output*/ +#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_0001(BOOT_MODE_GET()) + +/*all sdio V2 of raising edge input, failing edge output*/ +#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_0010(BOOT_MODE_GET()) + +/*all sdio V2 of raising edge input, raising edge output*/ +#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_0011(BOOT_MODE_GET()) + +/*all sdio V1 of raising edge input, failing edge output*/ +#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_0110(BOOT_MODE_GET()) + +/*do not include joint download mode*/ +#define ETS_IS_SDIO_BOOT() IS_0110(BOOT_MODE_GET()) +#else + +/*do not include joint download mode*/ +#define ETS_IS_SPI_DOWNLOAD_BOOT() IS_0110(BOOT_MODE_GET()) + +#endif + +/*joint download boot*/ +#define ETS_IS_JOINT_DOWNLOAD_BOOT() IS_00XX(BOOT_MODE_GET()) + +/*ATE mode*/ +#define ETS_IS_ATE_BOOT() IS_0101(BOOT_MODE_GET()) + +/*used by ETS_IS_SDIO_UART_BOOT*/ +#define SEL_NO_BOOT 0 +#define SEL_SDIO_BOOT BIT0 +#define SEL_UART_BOOT BIT1 +#define SEL_SPI_SLAVE_BOOT BIT2 + +#endif /* _SOC_BOOT_MODE_H_ */ diff --git a/components/soc/esp32c6/include/soc/clint_reg.h b/components/soc/esp32c6/include/soc/clint_reg.h new file mode 100644 index 0000000000..08ab89c524 --- /dev/null +++ b/components/soc/esp32c6/include/soc/clint_reg.h @@ -0,0 +1,160 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/*CLINT MINT*/ +#define CLINT_MINT_SIP_REG (DR_REG_CLINT_M_BASE + 0x0) +/* CLINT_CPU_MINT_SIP : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_SIP 0xFFFFFFFF +#define CLINT_CPU_MINT_SIP_M ((CLINT_CPU_MINT_SIP_V)<<(CLINT_CPU_MINT_SIP_S)) +#define CLINT_CPU_MINT_SIP_V 0xFFFFFFFF +#define CLINT_CPU_MINT_SIP_S 0 + +#define CLINT_MINT_TIMECTL_REG (DR_REG_CLINT_M_BASE + 0x4) +/* CLINT_MINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: .*/ +#define CLINT_MINT_SAMPLING_MODE 0x00000003 +#define CLINT_MINT_SAMPLING_MODE_M ((CLINT_CPU_MINT_TIMECTL_V)<<(CLINT_CPU_MINT_TIMECTL_S)) +#define CLINT_MINT_SAMPLING_MODE_V 0x3 +#define CLINT_MINT_SAMPLING_MODE_S 4 +/* CLINT_MINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define CLINT_MINT_COUNTER_OVERFLOW (BIT(3)) +#define CLINT_MINT_COUNTER_OVERFLOW_M (BIT(3)) +#define CLINT_MINT_COUNTER_OVERFLOW_V 0x1 +#define CLINT_MINT_COUNTER_OVERFLOW_S 3 +/* CLINT_MINT_TIMERINT_PENDING : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define CLINT_MINT_TIMERINT_PENDING (BIT(2)) +#define CLINT_MINT_TIMERINT_PENDING_M (BIT(2)) +#define CLINT_MINT_TIMERINT_PENDING_V 0x1 +#define CLINT_MINT_TIMERINT_PENDING_S 2 +/* CLINT_MINT_TIMERINT_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define CLINT_MINT_TIMERINT_EN (BIT(1)) +#define CLINT_MINT_TIMERINT_EN_M (BIT(1)) +#define CLINT_MINT_TIMERINT_EN_V 0x1 +#define CLINT_MINT_TIMERINT_EN_S 1 +/* CLINT_MINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define CLINT_MINT_COUNTER_EN (BIT(0)) +#define CLINT_MINT_COUNTER_EN_M (BIT(0)) +#define CLINT_MINT_COUNTER_EN_V 0x1 +#define CLINT_MINT_COUNTER_EN_S 0 + +#define CLINT_MINT_MTIME_L_REG (DR_REG_CLINT_M_BASE + 0x8) +/* CLINT_CPU_MINT_MTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_MTIME_L 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIME_L_M ((CLINT_CPU_MINT_MTIME_L_V)<<(CLINT_CPU_MINT_MTIME_L_S)) +#define CLINT_CPU_MINT_MTIME_L_V 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIME_L_S 0 + +#define CLINT_MINT_MTIME_H_REG (DR_REG_CLINT_M_BASE + 0xC) +/* CLINT_CPU_MINT_MTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_MTIME_H 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIME_H_M ((CLINT_CPU_MINT_MTIME_H_V)<<(CLINT_CPU_MINT_MTIME_H_S)) +#define CLINT_CPU_MINT_MTIME_H_V 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIME_H_S 0 + +#define CLINT_MINT_MTIMECMP_L_REG (DR_REG_CLINT_M_BASE + 0x10) +/* CLINT_CPU_MINT_MTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_MTIMECMP_L 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIMECMP_L_M ((CLINT_CPU_MINT_MTIMECMP_L_V)<<(CLINT_CPU_MINT_MTIMECMP_L_S)) +#define CLINT_CPU_MINT_MTIMECMP_L_V 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIMECMP_L_S 0 + +#define CLINT_MINT_MTIMECMP_H_REG (DR_REG_CLINT_M_BASE + 0x14) +/* CLINT_CPU_MINT_MTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_MTIMECMP_H 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIMECMP_H_M ((CLINT_CPU_MINT_MTIMECMP_H_V)<<(CLINT_CPU_MINT_MTIMECMP_H_S)) +#define CLINT_CPU_MINT_MTIMECMP_H_V 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIMECMP_H_S 0 + +/*CLINT UINT*/ +#define CLINT_UINT_SIP_REG (DR_REG_CLINT_U_BASE + 0x0) +/* CLINT_CPU_UINT_SIP : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: .*/ +#define CLINT_CPU_UINT_SIP 0xFFFFFFFF +#define CLINT_CPU_UINT_SIP_M ((CLINT_CPU_UINT_SIP_V)<<(CLINT_CPU_UINT_SIP_S)) +#define CLINT_CPU_UINT_SIP_V 0xFFFFFFFF +#define CLINT_CPU_UINT_SIP_S 0 + +#define CLINT_UINT_TIMECTL_REG (DR_REG_CLINT_U_BASE + 0x4) +/* CLINT_UINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: .*/ +#define CLINT_UINT_SAMPLING_MODE 0x00000003 +#define CLINT_UINT_SAMPLING_MODE_M ((CLINT_CPU_UINT_TIMECTL_V)<<(CLINT_CPU_UINT_TIMECTL_S)) +#define CLINT_UINT_SAMPLING_MODE_V 0x3 +#define CLINT_UINT_SAMPLING_MODE_S 4 +/* CLINT_UINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define CLINT_UINT_COUNTER_OVERFLOW (BIT(3)) +#define CLINT_UINT_COUNTER_OVERFLOW_M (BIT(3)) +#define CLINT_UINT_COUNTER_OVERFLOW_V 0x1 +#define CLINT_UINT_COUNTER_OVERFLOW_S 3 +/* CLINT_UINT_TIMERINT_PENDING : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define CLINT_UINT_TIMERINT_PENDING (BIT(2)) +#define CLINT_UINT_TIMERINT_PENDING_M (BIT(2)) +#define CLINT_UINT_TIMERINT_PENDING_V 0x1 +#define CLINT_UINT_TIMERINT_PENDING_S 2 +/* CLINT_UINT_TIMERINT_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define CLINT_UINT_TIMERINT_EN (BIT(1)) +#define CLINT_UINT_TIMERINT_EN_M (BIT(1)) +#define CLINT_UINT_TIMERINT_EN_V 0x1 +#define CLINT_UINT_TIMERINT_EN_S 1 +/* CLINT_UINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define CLINT_UINT_COUNTER_EN (BIT(0)) +#define CLINT_UINT_COUNTER_EN_M (BIT(0)) +#define CLINT_UINT_COUNTER_EN_V 0x1 +#define CLINT_UINT_COUNTER_EN_S 0 + +#define CLINT_UINT_UTIME_L_REG (DR_REG_CLINT_U_BASE + 0x8) +/* CLINT_CPU_UINT_UTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_UINT_UTIME_L 0xFFFFFFFF +#define CLINT_CPU_UINT_UTIME_L_M ((CLINT_CPU_UINT_UTIME_L_V)<<(CLINT_CPU_UINT_UTIME_L_S)) +#define CLINT_CPU_UINT_UTIME_L_V 0xFFFFFFFF +#define CLINT_CPU_UINT_UTIME_L_S 0 + +#define CLINT_UINT_UTIME_H_REG (DR_REG_CLINT_U_BASE + 0xC) +/* CLINT_CPU_UINT_UTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_UINT_UTIME_H 0xFFFFFFFF +#define CLINT_CPU_UINT_UTIME_H_M ((CLINT_CPU_UINT_UTIME_H_V)<<(CLINT_CPU_UINT_UTIME_H_S)) +#define CLINT_CPU_UINT_UTIME_H_V 0xFFFFFFFF +#define CLINT_CPU_UINT_UTIME_H_S 0 + +#define CLINT_UINT_UTIMECMP_L_REG (DR_REG_CLINT_U_BASE + 0x10) +/* CLINT_CPU_UINT_UTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_UINT_UTIMECMP_L 0xFFFFFFFF +#define CLINT_CPU_UINT_UTIMECMP_L_M ((CLINT_CPU_UINT_UTIMECMP_L_V)<<(CLINT_CPU_UINT_UTIMECMP_L_S)) +#define CLINT_CPU_UINT_UTIMECMP_L_V 0xFFFFFFFF +#define CLINT_CPU_UINT_UTIMECMP_L_S 0 + +#define CLINT_UINT_UTIMECMP_H_REG (DR_REG_CLINT_U_BASE + 0x14) +/* CLINT_CPU_UINT_UTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_UINT_UTIMECMP_H 0xFFFFFFFF +#define CLINT_CPU_UINT_UTIMECMP_H_M ((CLINT_CPU_UINT_UTIMECMP_H_V)<<(CLINT_CPU_UINT_UTIMECMP_H_S)) +#define CLINT_CPU_UINT_UTIMECMP_H_V 0xFFFFFFFF +#define CLINT_CPU_UINT_UTIMECMP_H_S 0 +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/clk_tree_defs.h b/components/soc/esp32c6/include/soc/clk_tree_defs.h new file mode 100644 index 0000000000..1343a8cddd --- /dev/null +++ b/components/soc/esp32c6/include/soc/clk_tree_defs.h @@ -0,0 +1,279 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "sdkconfig.h" // TODO: IDF-5973 + +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: IDF-5346 Copied from C3, need to update +/* + ************************* ESP32C6 Root Clock Source **************************** + * 1) Internal 17.5MHz RC Oscillator: RC_FAST (usually referred as FOSC or CK8M/CLK8M in TRM and reg. description) + * + * This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK. + * The ~17.5MHz signal output is also passed into a configurable divider, which by default divides the input clock + * frequency by 256, to generate a RC_FAST_D256_CLK (usually referred as 8md256 or simply d256 in reg. description). + * + * The exact frequency of RC_FAST_CLK can be computed in runtime through calibration on the RC_FAST_D256_CLK. + * + * 2) External 40MHz Crystal Clock: XTAL + * + * 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description) + * + * This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock + * can be computed in runtime through calibration. + * + * 4) External 32kHz Crystal Clock (optional): XTAL32K + * + * The clock source for this XTAL32K_CLK can be either a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N + * pins or a 32kHz clock signal generated by an external circuit. The external signal must be connected to the + * XTAL_32K_P pin. + * + * XTAL32K_CLK can also be calibrated to get its exact frequency. + */ + +/* With the default value of CK8M_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */ +#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!< Approximate RC_FAST_CLK frequency in Hz */ +#define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */ +#define SOC_CLK_RC_FAST_D256_FREQ_APPROX (SOC_CLK_RC_FAST_FREQ_APPROX / 256) /*!< Approximate RC_FAST_D256_CLK frequency in Hz */ +#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */ + +// Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr] +// {loc}: EXT, INT +// {type}: XTAL, RC +// [attr] - optional: [frequency], FAST, SLOW +/** + * @brief Root clock + */ +typedef enum { + SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 17.5MHz RC oscillator */ + SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */ + SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */ + SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal/clock signal */ +} soc_root_clk_t; + +/** + * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { + SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 480MHz or 320MHz) */ + SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */ +} soc_cpu_clk_src_t; + +/** + * @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { + SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 = 2, /*!< Select RC_FAST_D256_CLK (referred as FOSC_DIV or 8m_d256/8md256 in TRM and reg. description) as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */ +} soc_rtc_slow_clk_src_t; + +/** + * @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { + SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 0, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */ + SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */ +} soc_rtc_fast_clk_src_t; + +// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr] +// {[upstream]clock_name}: APB, (BB)PLL, etc. +// [attr] - optional: FAST, SLOW, D, F +/** + * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.) + * + * @note enum starts from 1, to save 0 for special purpose + */ +typedef enum { + // For CPU domain + SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */ + // For RTC domain + SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */ + SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC_FAST_D256 by configuring soc_rtc_slow_clk_src_t */ + // For digital domain: peripherals, WIFI, BLE + SOC_MOD_CLK_APB, /*!< APB_CLK is highly dependent on the CPU_CLK source */ + SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL, and has a fixed frequency of 80MHz */ + SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL, and has a fixed frequency of 160MHz */ + SOC_MOD_CLK_PLL_D2, /*!< PLL_D2_CLK is derived from PLL, it has a fixed divider of 2 */ + SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */ + SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */ + SOC_MOD_CLK_RC_FAST_D256, /*!< RC_FAST_D256_CLK comes from the internal 20MHz rc oscillator, divided by 256, and passing a clock gating to the peripherals */ + SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */ +} soc_module_clk_t; + +//////////////////////////////////////////////////GPTimer/////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of GPTimer + * + * The following code can be used to iterate all possible clocks: + * @code{c} + * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS; + * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) { + * soc_periph_gptimer_clk_src_t clk = gptimer_clks[i]; + * // Test GPTimer with the clock `clk` + * } + * @endcode + */ +#if CONFIG_IDF_ENV_FPGA +#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_XTAL} +#else +#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_XTAL} +#endif + +/** + * @brief Type of GPTimer clock source + */ +typedef enum { + GPTIMER_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ + GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ +#if CONFIG_IDF_ENV_FPGA + GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */ +#else + GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */ +#endif +} soc_periph_gptimer_clk_src_t; + +/** + * @brief Type of Timer Group clock source, reserved for the legacy timer group driver + */ +typedef enum { + TIMER_SRC_CLK_APB = SOC_MOD_CLK_APB, /*!< Timer group clock source is APB */ + TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */ + TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_APB, /*!< Timer group clock source default choice is APB */ +} soc_periph_tg_clk_src_legacy_t; + +//////////////////////////////////////////////////RMT/////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of RMT + */ +#if CONFIG_IDF_ENV_FPGA +#define SOC_RMT_CLKS {SOC_MOD_CLK_XTAL} +#else +#define SOC_RMT_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_XTAL} +#endif + +/** + * @brief Type of RMT clock source + */ +typedef enum { + RMT_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ + RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ +#if CONFIG_IDF_ENV_FPGA + RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */ +#else + RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */ +#endif +} soc_periph_rmt_clk_src_t; + +/** + * @brief Type of RMT clock source, reserved for the legacy RMT driver + */ +typedef enum { + RMT_BASECLK_APB = SOC_MOD_CLK_APB, /*!< RMT source clock is APB */ + RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */ + RMT_BASECLK_DEFAULT = SOC_MOD_CLK_APB, /*!< RMT source clock default choice is APB */ +} soc_periph_rmt_clk_src_legacy_t; + +//////////////////////////////////////////////////Temp Sensor/////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of Temperature Sensor + */ +#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of Temp Sensor clock source + */ +typedef enum { + TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */ +} soc_periph_temperature_sensor_clk_src_t; + +///////////////////////////////////////////////////UART///////////////////////////////////////////////////////////////// + +/** + * @brief Type of UART clock source, reserved for the legacy UART driver + */ +typedef enum { + UART_SCLK_APB = SOC_MOD_CLK_APB, /*!< UART source clock is APB CLK */ + UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */ + UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */ + UART_SCLK_DEFAULT = SOC_MOD_CLK_APB, /*!< UART source clock default choice is APB */ +} soc_periph_uart_clk_src_legacy_t; + +///////////////////////////////////////////////////// I2S ////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of I2S + */ +#if CONFIG_IDF_ENV_FPGA +#define SOC_I2S_CLKS {SOC_MOD_CLK_XTAL} +#else +#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} +#endif + +/** + * @brief I2S clock source enum + */ +typedef enum { +#if CONFIG_IDF_ENV_FPGA + I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, +#else + I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */ +#endif + I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ + I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ +} soc_periph_i2s_clk_src_t; + +/////////////////////////////////////////////////I2C//////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of I2C + */ +#define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of I2C clock source. + */ +typedef enum { + I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, + I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, + I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, +} soc_periph_i2c_clk_src_t; + +//////////////////////////////////////////////////SDM////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of SDM + */ +#define SOC_SDM_CLKS {SOC_MOD_CLK_APB} + +/** + * @brief Sigma Delta Modulator clock source + */ +typedef enum { + SDM_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ + SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */ +} soc_periph_sdm_clk_src_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/clkout_channel.h b/components/soc/esp32c6/include/soc/clkout_channel.h new file mode 100644 index 0000000000..d821cef127 --- /dev/null +++ b/components/soc/esp32c6/include/soc/clkout_channel.h @@ -0,0 +1,19 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_CLKOUT_CHANNEL_H +#define _SOC_CLKOUT_CHANNEL_H + +// TODO: IDF-5870 +//CLKOUT channels +#define CLKOUT_GPIO20_DIRECT_CHANNEL CLKOUT_CHANNEL_1 +#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM 20 +#define CLKOUT_GPIO19_DIRECT_CHANNEL CLKOUT_CHANNEL_2 +#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM 19 +#define CLKOUT_GPIO18_DIRECT_CHANNEL CLKOUT_CHANNEL_3 +#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM 18 + +#endif diff --git a/components/soc/esp32c6/include/soc/dport_access.h b/components/soc/esp32c6/include/soc/dport_access.h new file mode 100644 index 0000000000..000b58c36a --- /dev/null +++ b/components/soc/esp32c6/include/soc/dport_access.h @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _DPORT_ACCESS_H_ +#define _DPORT_ACCESS_H_ + +#include +#include "soc.h" +#include "uart_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions + +#define DPORT_INTERRUPT_DISABLE() +#define DPORT_INTERRUPT_RESTORE() + +/** + * @brief Read a sequence of DPORT registers to the buffer. + * + * @param[out] buff_out Contains the read data. + * @param[in] address Initial address for reading registers. + * @param[in] num_words The number of words. + */ +void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words); + +// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent. +#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r)) +#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) + +// Write value to DPORT register (does not require protecting) +#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v)) + +#define DPORT_REG_READ(_r) _DPORT_REG_READ(_r) +#define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r) + +//get bit or get bits from register +#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b)) + +//set bit or set bits to register +#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b))) + +//clear bit or clear bits of register +#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b)))) + +//set bits of register controlled by mask +#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m)))) + +//get field from register, uses field _S & _V to determine mask +#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V)) + +//set field to register, used when _f is not left shifted by _f##_S +#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S)))) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe. +#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr))) +#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val) +#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b))) +#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b)))) + +#define DPORT_READ_PERI_REG(addr) _DPORT_READ_PERI_REG(addr) + +//write value to register +#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val)) + +//clear bits of register controlled by mask +#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask)))) + +//set bits of register controlled by mask +#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask))) + +//get bits of register controlled by mask +#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) + +//get bits of register controlled by highest bit and lowest bit +#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) + +//set bits of register controlled by mask and shift +#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)))) + +//get field of register +#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) +//}} + +#ifdef __cplusplus +} +#endif + +#endif /* _DPORT_ACCESS_H_ */ diff --git a/components/soc/esp32c6/include/soc/ds_reg.h b/components/soc/esp32c6/include/soc/ds_reg.h new file mode 100644 index 0000000000..4ca749c1de --- /dev/null +++ b/components/soc/esp32c6/include/soc/ds_reg.h @@ -0,0 +1,149 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** DS_Y_MEM register + * memory that stores Y + */ +#define DS_Y_MEM (DR_REG_DS_BASE + 0x0) +#define DS_Y_MEM_SIZE_BYTES 512 + +/** DS_M_MEM register + * memory that stores M + */ +#define DS_M_MEM (DR_REG_DS_BASE + 0x200) +#define DS_M_MEM_SIZE_BYTES 512 + +/** DS_RB_MEM register + * memory that stores Rb + */ +#define DS_RB_MEM (DR_REG_DS_BASE + 0x400) +#define DS_RB_MEM_SIZE_BYTES 512 + +/** DS_BOX_MEM register + * memory that stores BOX + */ +#define DS_BOX_MEM (DR_REG_DS_BASE + 0x600) +#define DS_BOX_MEM_SIZE_BYTES 48 + +/** DS_IV_MEM register + * memory that stores IV + */ +#define DS_IV_MEM (DR_REG_DS_BASE + 0x630) +#define DS_IV_MEM_SIZE_BYTES 16 + +/** DS_X_MEM register + * memory that stores X + */ +#define DS_X_MEM (DR_REG_DS_BASE + 0x800) +#define DS_X_MEM_SIZE_BYTES 512 + +/** DS_Z_MEM register + * memory that stores Z + */ +#define DS_Z_MEM (DR_REG_DS_BASE + 0xa00) +#define DS_Z_MEM_SIZE_BYTES 512 + +/** DS_SET_START_REG register + * DS start control register + */ +#define DS_SET_START_REG (DR_REG_DS_BASE + 0xe00) +/** DS_SET_START : WT; bitpos: [0]; default: 0; + * set this bit to start DS operation. + */ +#define DS_SET_START (BIT(0)) +#define DS_SET_START_M (DS_SET_START_V << DS_SET_START_S) +#define DS_SET_START_V 0x00000001U +#define DS_SET_START_S 0 + +/** DS_SET_CONTINUE_REG register + * DS continue control register + */ +#define DS_SET_CONTINUE_REG (DR_REG_DS_BASE + 0xe04) +/** DS_SET_CONTINUE : WT; bitpos: [0]; default: 0; + * set this bit to continue DS operation. + */ +#define DS_SET_CONTINUE (BIT(0)) +#define DS_SET_CONTINUE_M (DS_SET_CONTINUE_V << DS_SET_CONTINUE_S) +#define DS_SET_CONTINUE_V 0x00000001U +#define DS_SET_CONTINUE_S 0 + +/** DS_SET_FINISH_REG register + * DS finish control register + */ +#define DS_SET_FINISH_REG (DR_REG_DS_BASE + 0xe08) +/** DS_SET_FINISH : WT; bitpos: [0]; default: 0; + * Set this bit to finish DS process. + */ +#define DS_SET_FINISH (BIT(0)) +#define DS_SET_FINISH_M (DS_SET_FINISH_V << DS_SET_FINISH_S) +#define DS_SET_FINISH_V 0x00000001U +#define DS_SET_FINISH_S 0 + +/** DS_QUERY_BUSY_REG register + * DS query busy register + */ +#define DS_QUERY_BUSY_REG (DR_REG_DS_BASE + 0xe0c) +/** DS_QUERY_BUSY : RO; bitpos: [0]; default: 0; + * digital signature state. 1'b0: idle, 1'b1: busy + */ +#define DS_QUERY_BUSY (BIT(0)) +#define DS_QUERY_BUSY_M (DS_QUERY_BUSY_V << DS_QUERY_BUSY_S) +#define DS_QUERY_BUSY_V 0x00000001U +#define DS_QUERY_BUSY_S 0 + +/** DS_QUERY_KEY_WRONG_REG register + * DS query key-wrong counter register + */ +#define DS_QUERY_KEY_WRONG_REG (DR_REG_DS_BASE + 0xe10) +/** DS_QUERY_KEY_WRONG : RO; bitpos: [3:0]; default: 0; + * digital signature key wrong counter + */ +#define DS_QUERY_KEY_WRONG 0x0000000FU +#define DS_QUERY_KEY_WRONG_M (DS_QUERY_KEY_WRONG_V << DS_QUERY_KEY_WRONG_S) +#define DS_QUERY_KEY_WRONG_V 0x0000000FU +#define DS_QUERY_KEY_WRONG_S 0 + +/** DS_QUERY_CHECK_REG register + * DS query check result register + */ +#define DS_QUERY_CHECK_REG (DR_REG_DS_BASE + 0xe14) +/** DS_MD_ERROR : RO; bitpos: [0]; default: 0; + * MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail + */ +#define DS_MD_ERROR (BIT(0)) +#define DS_MD_ERROR_M (DS_MD_ERROR_V << DS_MD_ERROR_S) +#define DS_MD_ERROR_V 0x00000001U +#define DS_MD_ERROR_S 0 +/** DS_PADDING_BAD : RO; bitpos: [1]; default: 0; + * padding checkout result. 1'b0: a good padding, 1'b1: a bad padding + */ +#define DS_PADDING_BAD (BIT(1)) +#define DS_PADDING_BAD_M (DS_PADDING_BAD_V << DS_PADDING_BAD_S) +#define DS_PADDING_BAD_V 0x00000001U +#define DS_PADDING_BAD_S 1 + +/** DS_DATE_REG register + * DS version control register + */ +#define DS_DATE_REG (DR_REG_DS_BASE + 0xe20) +/** DS_DATE : R/W; bitpos: [29:0]; default: 538969624; + * ds version information + */ +#define DS_DATE 0x3FFFFFFFU +#define DS_DATE_M (DS_DATE_V << DS_DATE_S) +#define DS_DATE_V 0x3FFFFFFFU +#define DS_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/ds_struct.h b/components/soc/esp32c6/include/soc/ds_struct.h new file mode 100644 index 0000000000..3a7d953c73 --- /dev/null +++ b/components/soc/esp32c6/include/soc/ds_struct.h @@ -0,0 +1,149 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: memory type */ + +/** Group: Control/Status registers */ +/** Type of set_start register + * DS start control register + */ +typedef union { + struct { + /** set_start : WT; bitpos: [0]; default: 0; + * set this bit to start DS operation. + */ + uint32_t set_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ds_set_start_reg_t; + +/** Type of set_continue register + * DS continue control register + */ +typedef union { + struct { + /** set_continue : WT; bitpos: [0]; default: 0; + * set this bit to continue DS operation. + */ + uint32_t set_continue:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ds_set_continue_reg_t; + +/** Type of set_finish register + * DS finish control register + */ +typedef union { + struct { + /** set_finish : WT; bitpos: [0]; default: 0; + * Set this bit to finish DS process. + */ + uint32_t set_finish:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ds_set_finish_reg_t; + +/** Type of query_busy register + * DS query busy register + */ +typedef union { + struct { + /** query_busy : RO; bitpos: [0]; default: 0; + * digital signature state. 1'b0: idle, 1'b1: busy + */ + uint32_t query_busy:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ds_query_busy_reg_t; + +/** Type of query_key_wrong register + * DS query key-wrong counter register + */ +typedef union { + struct { + /** query_key_wrong : RO; bitpos: [3:0]; default: 0; + * digital signature key wrong counter + */ + uint32_t query_key_wrong:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ds_query_key_wrong_reg_t; + +/** Type of query_check register + * DS query check result register + */ +typedef union { + struct { + /** md_error : RO; bitpos: [0]; default: 0; + * MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail + */ + uint32_t md_error:1; + /** padding_bad : RO; bitpos: [1]; default: 0; + * padding checkout result. 1'b0: a good padding, 1'b1: a bad padding + */ + uint32_t padding_bad:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} ds_query_check_reg_t; + + +/** Group: version control register */ +/** Type of date register + * DS version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 538969624; + * ds version information + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} ds_date_reg_t; + + +typedef struct ds_dev_t { + volatile uint32_t y[128]; + volatile uint32_t m[128]; + volatile uint32_t rb[128]; + volatile uint32_t box[12]; + volatile uint32_t iv[4]; + uint32_t reserved_640[112]; + volatile uint32_t x[128]; + volatile uint32_t z[128]; + uint32_t reserved_c00[128]; + volatile ds_set_start_reg_t set_start; + volatile ds_set_continue_reg_t set_continue; + volatile ds_set_finish_reg_t set_finish; + volatile ds_query_busy_reg_t query_busy; + volatile ds_query_key_wrong_reg_t query_key_wrong; + volatile ds_query_check_reg_t query_check; + uint32_t reserved_e18[2]; + volatile ds_date_reg_t date; +} ds_dev_t; + +extern ds_dev_t DS; + +#ifndef __cplusplus +_Static_assert(sizeof(ds_dev_t) == 0xe24, "Invalid size of ds_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/ecc_mult_reg.h b/components/soc/esp32c6/include/soc/ecc_mult_reg.h new file mode 100644 index 0000000000..dca2cc1206 --- /dev/null +++ b/components/soc/esp32c6/include/soc/ecc_mult_reg.h @@ -0,0 +1,158 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** ECC_MULT_INT_RAW_REG register + * ECC interrupt raw register, valid in level. + */ +#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc) +/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the ecc_calc_done_int interrupt + */ +#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_RAW_M (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S) +#define ECC_MULT_CALC_DONE_INT_RAW_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_RAW_S 0 + +/** ECC_MULT_INT_ST_REG register + * ECC interrupt status register. + */ +#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10) +/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the ecc_calc_done_int interrupt + */ +#define ECC_MULT_CALC_DONE_INT_ST (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_ST_M (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S) +#define ECC_MULT_CALC_DONE_INT_ST_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_ST_S 0 + +/** ECC_MULT_INT_ENA_REG register + * ECC interrupt enable register. + */ +#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14) +/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the ecc_calc_done_int interrupt + */ +#define ECC_MULT_CALC_DONE_INT_ENA (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_ENA_M (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S) +#define ECC_MULT_CALC_DONE_INT_ENA_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_ENA_S 0 + +/** ECC_MULT_INT_CLR_REG register + * ECC interrupt clear register. + */ +#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18) +/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the ecc_calc_done_int interrupt + */ +#define ECC_MULT_CALC_DONE_INT_CLR (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_CLR_M (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S) +#define ECC_MULT_CALC_DONE_INT_CLR_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_CLR_S 0 + +/** ECC_MULT_CONF_REG register + * ECC configure register + */ +#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c) +/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0; + * Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after + * the caculatrion is done. + */ +#define ECC_MULT_START (BIT(0)) +#define ECC_MULT_START_M (ECC_MULT_START_V << ECC_MULT_START_S) +#define ECC_MULT_START_V 0x00000001U +#define ECC_MULT_START_S 0 +/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0; + * Write 1 to reset ECC Accelerator. + */ +#define ECC_MULT_RESET (BIT(1)) +#define ECC_MULT_RESET_M (ECC_MULT_RESET_V << ECC_MULT_RESET_S) +#define ECC_MULT_RESET_V 0x00000001U +#define ECC_MULT_RESET_S 1 +/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0; + * The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256. + */ +#define ECC_MULT_KEY_LENGTH (BIT(2)) +#define ECC_MULT_KEY_LENGTH_M (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S) +#define ECC_MULT_KEY_LENGTH_V 0x00000001U +#define ECC_MULT_KEY_LENGTH_S 2 +/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [3]; default: 0; + * Reserved + */ +#define ECC_MULT_SECURITY_MODE (BIT(3)) +#define ECC_MULT_SECURITY_MODE_M (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S) +#define ECC_MULT_SECURITY_MODE_V 0x00000001U +#define ECC_MULT_SECURITY_MODE_S 3 +/** ECC_MULT_CLK_EN : R/W; bitpos: [4]; default: 0; + * Write 1 to force on register clock gate. + */ +#define ECC_MULT_CLK_EN (BIT(4)) +#define ECC_MULT_CLK_EN_M (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S) +#define ECC_MULT_CLK_EN_V 0x00000001U +#define ECC_MULT_CLK_EN_S 4 +/** ECC_MULT_WORK_MODE : R/W; bitpos: [7:5]; default: 0; + * The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Division mode. 2: + * Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: + * Reserved. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. + */ +#define ECC_MULT_WORK_MODE 0x00000007U +#define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S) +#define ECC_MULT_WORK_MODE_V 0x00000007U +#define ECC_MULT_WORK_MODE_S 5 +/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [8]; default: 0; + * The verification result bit of ECC Accelerator, only valid when calculation is done. + */ +#define ECC_MULT_VERIFICATION_RESULT (BIT(8)) +#define ECC_MULT_VERIFICATION_RESULT_M (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S) +#define ECC_MULT_VERIFICATION_RESULT_V 0x00000001U +#define ECC_MULT_VERIFICATION_RESULT_S 8 +/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 1; + * ECC memory clock gate force on register + */ +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON (BIT(31)) +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S) +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V 0x00000001U +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S 31 + +/** ECC_MULT_DATE_REG register + * Version control register + */ +#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc) +/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 35656256; + * ECC mult version control register + */ +#define ECC_MULT_DATE 0x0FFFFFFFU +#define ECC_MULT_DATE_M (ECC_MULT_DATE_V << ECC_MULT_DATE_S) +#define ECC_MULT_DATE_V 0x0FFFFFFFU +#define ECC_MULT_DATE_S 0 + +/** ECC_MULT_K_MEM register + * The memory that stores k. + */ +#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100) +#define ECC_MULT_K_MEM_SIZE_BYTES 32 + +/** ECC_MULT_PX_MEM register + * The memory that stores Px. + */ +#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x120) +#define ECC_MULT_PX_MEM_SIZE_BYTES 32 + +/** ECC_MULT_PY_MEM register + * The memory that stores Py. + */ +#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x140) +#define ECC_MULT_PY_MEM_SIZE_BYTES 32 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/ecc_mult_struct.h b/components/soc/esp32c6/include/soc/ecc_mult_struct.h new file mode 100644 index 0000000000..c120fb068d --- /dev/null +++ b/components/soc/esp32c6/include/soc/ecc_mult_struct.h @@ -0,0 +1,158 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Memory data */ + +/** Group: Interrupt registers */ +/** Type of int_raw register + * ECC interrupt raw register, valid in level. + */ +typedef union { + struct { + /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the ecc_calc_done_int interrupt + */ + uint32_t calc_done_int_raw:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_raw_reg_t; + +/** Type of int_st register + * ECC interrupt status register. + */ +typedef union { + struct { + /** calc_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the ecc_calc_done_int interrupt + */ + uint32_t calc_done_int_st:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_st_reg_t; + +/** Type of int_ena register + * ECC interrupt enable register. + */ +typedef union { + struct { + /** calc_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the ecc_calc_done_int interrupt + */ + uint32_t calc_done_int_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_ena_reg_t; + +/** Type of int_clr register + * ECC interrupt clear register. + */ +typedef union { + struct { + /** calc_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the ecc_calc_done_int interrupt + */ + uint32_t calc_done_int_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_clr_reg_t; + + +/** Group: RX Control and configuration registers */ +/** Type of conf register + * ECC configure register + */ +typedef union { + struct { + /** start : R/W/SC; bitpos: [0]; default: 0; + * Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after + * the caculatrion is done. + */ + uint32_t start:1; + /** reset : WT; bitpos: [1]; default: 0; + * Write 1 to reset ECC Accelerator. + */ + uint32_t reset:1; + /** key_length : R/W; bitpos: [2]; default: 0; + * The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256. + */ + uint32_t key_length:1; + /** security_mode : R/W; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t security_mode:1; + /** clk_en : R/W; bitpos: [4]; default: 0; + * Write 1 to force on register clock gate. + */ + uint32_t clk_en:1; + /** work_mode : R/W; bitpos: [7:5]; default: 0; + * The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Division mode. 2: + * Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: + * Reserved. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. + */ + uint32_t work_mode:3; + /** verification_result : RO/SS; bitpos: [8]; default: 0; + * The verification result bit of ECC Accelerator, only valid when calculation is done. + */ + uint32_t verification_result:1; + uint32_t reserved_9:22; + /** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 1; + * ECC memory clock gate force on register + */ + uint32_t mem_clock_gate_force_on:1; + }; + uint32_t val; +} ecc_mult_conf_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35656256; + * ECC mult version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} ecc_mult_date_reg_t; + + +typedef struct ecc_mult_dev_t { + uint32_t reserved_000[3]; + volatile ecc_mult_int_raw_reg_t int_raw; + volatile ecc_mult_int_st_reg_t int_st; + volatile ecc_mult_int_ena_reg_t int_ena; + volatile ecc_mult_int_clr_reg_t int_clr; + volatile ecc_mult_conf_reg_t conf; + uint32_t reserved_020[55]; + volatile ecc_mult_date_reg_t date; + volatile uint32_t k[8]; + volatile uint32_t px[8]; + volatile uint32_t py[8]; +} ecc_mult_dev_t; + +extern ecc_mult_dev_t ECC; + +#ifndef __cplusplus +_Static_assert(sizeof(ecc_mult_dev_t) == 0x160, "Invalid size of ecc_mult_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/efuse_reg.h b/components/soc/esp32c6/include/soc/efuse_reg.h new file mode 100644 index 0000000000..7b55a151d6 --- /dev/null +++ b/components/soc/esp32c6/include/soc/efuse_reg.h @@ -0,0 +1,2501 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** EFUSE_PGM_DATA0_REG register + * Register 0 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 + +/** EFUSE_PGM_DATA1_REG register + * Register 1 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) +/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) +#define EFUSE_PGM_DATA_1_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_1_S 0 + +/** EFUSE_PGM_DATA2_REG register + * Register 2 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) +/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) +#define EFUSE_PGM_DATA_2_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_2_S 0 + +/** EFUSE_PGM_DATA3_REG register + * Register 3 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) +/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; + * Configures the 3rd 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_3 0xFFFFFFFFU +#define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) +#define EFUSE_PGM_DATA_3_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_3_S 0 + +/** EFUSE_PGM_DATA4_REG register + * Register 4 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) +/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; + * Configures the 4th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_4 0xFFFFFFFFU +#define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) +#define EFUSE_PGM_DATA_4_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_4_S 0 + +/** EFUSE_PGM_DATA5_REG register + * Register 5 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) +/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; + * Configures the 5th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_5 0xFFFFFFFFU +#define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) +#define EFUSE_PGM_DATA_5_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_5_S 0 + +/** EFUSE_PGM_DATA6_REG register + * Register 6 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) +/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; + * Configures the 6th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_6 0xFFFFFFFFU +#define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) +#define EFUSE_PGM_DATA_6_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_6_S 0 + +/** EFUSE_PGM_DATA7_REG register + * Register 7 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) +/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; + * Configures the 7th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_7 0xFFFFFFFFU +#define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) +#define EFUSE_PGM_DATA_7_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_7_S 0 + +/** EFUSE_PGM_CHECK_VALUE0_REG register + * Register 0 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) +/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_S 0 + +/** EFUSE_PGM_CHECK_VALUE1_REG register + * Register 1 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) +/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) +#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_1_S 0 + +/** EFUSE_PGM_CHECK_VALUE2_REG register + * Register 2 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) +/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) +#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_2_S 0 + +/** EFUSE_RD_WR_DIS_REG register + * BLOCK0 data register 0. + */ +#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) +/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; + * Represents whether programming of individual eFuse memory bit is disabled or + * enabled. 1: Disabled. 0 Enabled. + */ +#define EFUSE_WR_DIS 0xFFFFFFFFU +#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) +#define EFUSE_WR_DIS_V 0xFFFFFFFFU +#define EFUSE_WR_DIS_S 0 + +/** EFUSE_RD_REPEAT_DATA0_REG register + * BLOCK0 data register 1. + */ +#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) +/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; + * Represents whether reading of individual eFuse block(block4~block10) is disabled or + * enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_RD_DIS 0x0000007FU +#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) +#define EFUSE_RD_DIS_V 0x0000007FU +#define EFUSE_RD_DIS_S 0 +/** EFUSE_SWAP_UART_SDIO_EN : RO; bitpos: [7]; default: 0; + * Represents whether pad of uart and sdio is swapped or not. 1: swapped. 0: not + * swapped. + */ +#define EFUSE_SWAP_UART_SDIO_EN (BIT(7)) +#define EFUSE_SWAP_UART_SDIO_EN_M (EFUSE_SWAP_UART_SDIO_EN_V << EFUSE_SWAP_UART_SDIO_EN_S) +#define EFUSE_SWAP_UART_SDIO_EN_V 0x00000001U +#define EFUSE_SWAP_UART_SDIO_EN_S 7 +/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; + * Represents whether icache is disabled or enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_ICACHE (BIT(8)) +#define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) +#define EFUSE_DIS_ICACHE_V 0x00000001U +#define EFUSE_DIS_ICACHE_S 8 +/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0; + * Represents whether the function of usb switch to jtag is disabled or enabled. 1: + * disabled. 0: enabled. + */ +#define EFUSE_DIS_USB_JTAG (BIT(9)) +#define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) +#define EFUSE_DIS_USB_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_JTAG_S 9 +/** EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0; + * Represents whether icache is disabled or enabled in Download mode. 1: disabled. 0: + * enabled. + */ +#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_M (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 +/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0; + * Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG (BIT(11)) +#define EFUSE_DIS_USB_SERIAL_JTAG_M (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_S 11 +/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; + * Represents whether the function that forces chip into download mode is disabled or + * enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 +/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0; + * Represents whether SPI0 controller during boot_mode_download is disabled or + * enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS (BIT(13)) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V 0x00000001U +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S 13 +/** EFUSE_DIS_CAN : RO; bitpos: [14]; default: 0; + * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_CAN (BIT(14)) +#define EFUSE_DIS_CAN_M (EFUSE_DIS_CAN_V << EFUSE_DIS_CAN_S) +#define EFUSE_DIS_CAN_V 0x00000001U +#define EFUSE_DIS_CAN_S 14 +/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0; + * Represents whether the selection between usb_to_jtag and pad_to_jtag through + * strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 + * is enabled or disabled. 1: enabled. 0: disabled. + */ +#define EFUSE_JTAG_SEL_ENABLE (BIT(15)) +#define EFUSE_JTAG_SEL_ENABLE_M (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S) +#define EFUSE_JTAG_SEL_ENABLE_V 0x00000001U +#define EFUSE_JTAG_SEL_ENABLE_S 15 +/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; + * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: + * enabled. + */ +#define EFUSE_SOFT_DIS_JTAG 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) +#define EFUSE_SOFT_DIS_JTAG_V 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_S 16 +/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; + * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: + * enabled. + */ +#define EFUSE_DIS_PAD_JTAG (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) +#define EFUSE_DIS_PAD_JTAG_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_S 19 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; + * Represents whether flash encrypt function is disabled or enabled(except in SPI boot + * mode). 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 +/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0; + * Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV. + */ +#define EFUSE_USB_DREFH 0x00000003U +#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) +#define EFUSE_USB_DREFH_V 0x00000003U +#define EFUSE_USB_DREFH_S 21 +/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0; + * Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV. + */ +#define EFUSE_USB_DREFL 0x00000003U +#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) +#define EFUSE_USB_DREFL_V 0x00000003U +#define EFUSE_USB_DREFL_S 23 +/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0; + * Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged. + */ +#define EFUSE_USB_EXCHG_PINS (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) +#define EFUSE_USB_EXCHG_PINS_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_S 25 +/** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0; + * Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not + * functioned. + */ +#define EFUSE_VDD_SPI_AS_GPIO (BIT(26)) +#define EFUSE_VDD_SPI_AS_GPIO_M (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S) +#define EFUSE_VDD_SPI_AS_GPIO_V 0x00000001U +#define EFUSE_VDD_SPI_AS_GPIO_S 26 +/** EFUSE_RPT4_RESERVED0_2 : RO; bitpos: [28:27]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED0_2 0x00000003U +#define EFUSE_RPT4_RESERVED0_2_M (EFUSE_RPT4_RESERVED0_2_V << EFUSE_RPT4_RESERVED0_2_S) +#define EFUSE_RPT4_RESERVED0_2_V 0x00000003U +#define EFUSE_RPT4_RESERVED0_2_S 27 +/** EFUSE_RPT4_RESERVED0_1 : RO; bitpos: [29]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED0_1 (BIT(29)) +#define EFUSE_RPT4_RESERVED0_1_M (EFUSE_RPT4_RESERVED0_1_V << EFUSE_RPT4_RESERVED0_1_S) +#define EFUSE_RPT4_RESERVED0_1_V 0x00000001U +#define EFUSE_RPT4_RESERVED0_1_S 29 +/** EFUSE_RPT4_RESERVED0_0 : RO; bitpos: [31:30]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED0_0 0x00000003U +#define EFUSE_RPT4_RESERVED0_0_M (EFUSE_RPT4_RESERVED0_0_V << EFUSE_RPT4_RESERVED0_0_S) +#define EFUSE_RPT4_RESERVED0_0_V 0x00000003U +#define EFUSE_RPT4_RESERVED0_0_S 30 + +/** EFUSE_RD_REPEAT_DATA1_REG register + * BLOCK0 data register 2. + */ +#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) +/** EFUSE_RPT4_RESERVED1_0 : RO; bitpos: [15:0]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED1_0 0x0000FFFFU +#define EFUSE_RPT4_RESERVED1_0_M (EFUSE_RPT4_RESERVED1_0_V << EFUSE_RPT4_RESERVED1_0_S) +#define EFUSE_RPT4_RESERVED1_0_V 0x0000FFFFU +#define EFUSE_RPT4_RESERVED1_0_S 0 +/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; + * Represents whether RTC watchdog timeout threshold is selected at startup. 1: + * selected. 0: not selected. + */ +#define EFUSE_WDT_DELAY_SEL 0x00000003U +#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) +#define EFUSE_WDT_DELAY_SEL_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_S 16 +/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; + * Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of + * 1: enabled. Even number of 1: disabled. + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; + * Represents whether revoking first secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; + * Represents whether revoking second secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; + * Represents whether revoking third secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 +/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; + * Represents the purpose of Key0. + */ +#define EFUSE_KEY_PURPOSE_0 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) +#define EFUSE_KEY_PURPOSE_0_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_S 24 +/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; + * Represents the purpose of Key1. + */ +#define EFUSE_KEY_PURPOSE_1 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) +#define EFUSE_KEY_PURPOSE_1_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_S 28 + +/** EFUSE_RD_REPEAT_DATA2_REG register + * BLOCK0 data register 3. + */ +#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) +/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; + * Represents the purpose of Key2. + */ +#define EFUSE_KEY_PURPOSE_2 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) +#define EFUSE_KEY_PURPOSE_2_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_S 0 +/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; + * Represents the purpose of Key3. + */ +#define EFUSE_KEY_PURPOSE_3 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) +#define EFUSE_KEY_PURPOSE_3_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_S 4 +/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; + * Represents the purpose of Key4. + */ +#define EFUSE_KEY_PURPOSE_4 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) +#define EFUSE_KEY_PURPOSE_4_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_S 8 +/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; + * Represents the purpose of Key5. + */ +#define EFUSE_KEY_PURPOSE_5 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) +#define EFUSE_KEY_PURPOSE_5_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_S 12 +/** EFUSE_DPA_SEC_LEVEL : RO; bitpos: [17:16]; default: 0; + * Represents the spa secure level by configuring the clock random divide mode. + */ +#define EFUSE_DPA_SEC_LEVEL 0x00000003U +#define EFUSE_DPA_SEC_LEVEL_M (EFUSE_DPA_SEC_LEVEL_V << EFUSE_DPA_SEC_LEVEL_S) +#define EFUSE_DPA_SEC_LEVEL_V 0x00000003U +#define EFUSE_DPA_SEC_LEVEL_S 16 +/** EFUSE_RPT4_RESERVED2_1 : RO; bitpos: [18]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED2_1 (BIT(18)) +#define EFUSE_RPT4_RESERVED2_1_M (EFUSE_RPT4_RESERVED2_1_V << EFUSE_RPT4_RESERVED2_1_S) +#define EFUSE_RPT4_RESERVED2_1_V 0x00000001U +#define EFUSE_RPT4_RESERVED2_1_S 18 +/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1; + * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. + */ +#define EFUSE_CRYPT_DPA_ENABLE (BIT(19)) +#define EFUSE_CRYPT_DPA_ENABLE_M (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S) +#define EFUSE_CRYPT_DPA_ENABLE_V 0x00000001U +#define EFUSE_CRYPT_DPA_ENABLE_S 19 +/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; + * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_EN (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) +#define EFUSE_SECURE_BOOT_EN_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_S 20 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; + * Represents whether revoking aggressive secure boot is enabled or disabled. 1: + * enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 +/** EFUSE_RPT4_RESERVED2_0 : RO; bitpos: [27:22]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED2_0 0x0000003FU +#define EFUSE_RPT4_RESERVED2_0_M (EFUSE_RPT4_RESERVED2_0_V << EFUSE_RPT4_RESERVED2_0_S) +#define EFUSE_RPT4_RESERVED2_0_V 0x0000003FU +#define EFUSE_RPT4_RESERVED2_0_S 22 +/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; + * Represents the flash waiting time after power-up, in unit of ms. When the value + * less than 15, the waiting time is the programmed value. Otherwise, the waiting time + * is 2 times the programmed value. + */ +#define EFUSE_FLASH_TPUW 0x0000000FU +#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) +#define EFUSE_FLASH_TPUW_V 0x0000000FU +#define EFUSE_FLASH_TPUW_S 28 + +/** EFUSE_RD_REPEAT_DATA3_REG register + * BLOCK0 data register 4. + */ +#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) +/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; + * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) +#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MODE_S 0 +/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; + * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_DIRECT_BOOT (BIT(1)) +#define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) +#define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U +#define EFUSE_DIS_DIRECT_BOOT_S 1 +/** EFUSE_DIS_USB_PRINT : RO; bitpos: [2]; default: 0; + * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. + * 0: enabled. + */ +#define EFUSE_DIS_USB_PRINT (BIT(2)) +#define EFUSE_DIS_USB_PRINT_M (EFUSE_DIS_USB_PRINT_V << EFUSE_DIS_USB_PRINT_S) +#define EFUSE_DIS_USB_PRINT_V 0x00000001U +#define EFUSE_DIS_USB_PRINT_S 2 +/** EFUSE_RPT4_RESERVED3_5 : RO; bitpos: [3]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED3_5 (BIT(3)) +#define EFUSE_RPT4_RESERVED3_5_M (EFUSE_RPT4_RESERVED3_5_V << EFUSE_RPT4_RESERVED3_5_S) +#define EFUSE_RPT4_RESERVED3_5_V 0x00000001U +#define EFUSE_RPT4_RESERVED3_5_S 3 +/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; + * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: + * disabled. 0: enabled. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; + * Represents whether security download is enabled or disabled. 1: enabled. 0: + * disabled. + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 +/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; + * Represents the type of UART printing. 00: force enable printing. 01: enable + * printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset + * at high level. 11: force disable printing. + */ +#define EFUSE_UART_PRINT_CONTROL 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) +#define EFUSE_UART_PRINT_CONTROL_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_S 6 +/** EFUSE_RPT4_RESERVED3_4 : RO; bitpos: [8]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED3_4 (BIT(8)) +#define EFUSE_RPT4_RESERVED3_4_M (EFUSE_RPT4_RESERVED3_4_V << EFUSE_RPT4_RESERVED3_4_S) +#define EFUSE_RPT4_RESERVED3_4_V 0x00000001U +#define EFUSE_RPT4_RESERVED3_4_S 8 +/** EFUSE_RPT4_RESERVED3_3 : RO; bitpos: [9]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED3_3 (BIT(9)) +#define EFUSE_RPT4_RESERVED3_3_M (EFUSE_RPT4_RESERVED3_3_V << EFUSE_RPT4_RESERVED3_3_S) +#define EFUSE_RPT4_RESERVED3_3_V 0x00000001U +#define EFUSE_RPT4_RESERVED3_3_S 9 +/** EFUSE_RPT4_RESERVED3_2 : RO; bitpos: [11:10]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED3_2 0x00000003U +#define EFUSE_RPT4_RESERVED3_2_M (EFUSE_RPT4_RESERVED3_2_V << EFUSE_RPT4_RESERVED3_2_S) +#define EFUSE_RPT4_RESERVED3_2_V 0x00000003U +#define EFUSE_RPT4_RESERVED3_2_S 10 +/** EFUSE_RPT4_RESERVED3_1 : RO; bitpos: [12]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED3_1 (BIT(12)) +#define EFUSE_RPT4_RESERVED3_1_M (EFUSE_RPT4_RESERVED3_1_V << EFUSE_RPT4_RESERVED3_1_S) +#define EFUSE_RPT4_RESERVED3_1_V 0x00000001U +#define EFUSE_RPT4_RESERVED3_1_S 12 +/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [13]; default: 0; + * Represents whether ROM code is forced to send a resume command during SPI boot. 1: + * forced. 0:not forced. + */ +#define EFUSE_FORCE_SEND_RESUME (BIT(13)) +#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) +#define EFUSE_FORCE_SEND_RESUME_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_S 13 +/** EFUSE_SECURE_VERSION : RO; bitpos: [29:14]; default: 0; + * Represents the version used by ESP-IDF anti-rollback feature. + */ +#define EFUSE_SECURE_VERSION 0x0000FFFFU +#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) +#define EFUSE_SECURE_VERSION_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_S 14 +/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [30]; default: 0; + * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is + * enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE (BIT(30)) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V 0x00000001U +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S 30 +/** EFUSE_RPT4_RESERVED3_0 : RO; bitpos: [31]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED3_0 (BIT(31)) +#define EFUSE_RPT4_RESERVED3_0_M (EFUSE_RPT4_RESERVED3_0_V << EFUSE_RPT4_RESERVED3_0_S) +#define EFUSE_RPT4_RESERVED3_0_V 0x00000001U +#define EFUSE_RPT4_RESERVED3_0_S 31 + +/** EFUSE_RD_REPEAT_DATA4_REG register + * BLOCK0 data register 5. + */ +#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) +/** EFUSE_RPT4_RESERVED4_1 : RO; bitpos: [23:0]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED4_1 0x00FFFFFFU +#define EFUSE_RPT4_RESERVED4_1_M (EFUSE_RPT4_RESERVED4_1_V << EFUSE_RPT4_RESERVED4_1_S) +#define EFUSE_RPT4_RESERVED4_1_V 0x00FFFFFFU +#define EFUSE_RPT4_RESERVED4_1_S 0 +/** EFUSE_RPT4_RESERVED4_0 : RO; bitpos: [31:24]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED4_0 0x000000FFU +#define EFUSE_RPT4_RESERVED4_0_M (EFUSE_RPT4_RESERVED4_0_V << EFUSE_RPT4_RESERVED4_0_S) +#define EFUSE_RPT4_RESERVED4_0_V 0x000000FFU +#define EFUSE_RPT4_RESERVED4_0_S 24 + +/** EFUSE_RD_MAC_SPI_SYS_0_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) +/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ +#define EFUSE_MAC_0 0xFFFFFFFFU +#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) +#define EFUSE_MAC_0_V 0xFFFFFFFFU +#define EFUSE_MAC_0_S 0 + +/** EFUSE_RD_MAC_SPI_SYS_1_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) +/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ +#define EFUSE_MAC_1 0x0000FFFFU +#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) +#define EFUSE_MAC_1_V 0x0000FFFFU +#define EFUSE_MAC_1_S 0 +/** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0; + * Stores the extended bits of MAC address. + */ +#define EFUSE_MAC_EXT 0x0000FFFFU +#define EFUSE_MAC_EXT_M (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S) +#define EFUSE_MAC_EXT_V 0x0000FFFFU +#define EFUSE_MAC_EXT_S 16 + +/** EFUSE_RD_MAC_SPI_SYS_2_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) +/** EFUSE_MAC_SPI_RESERVED : RO; bitpos: [13:0]; default: 0; + * Reserved. + */ +#define EFUSE_MAC_SPI_RESERVED 0x00003FFFU +#define EFUSE_MAC_SPI_RESERVED_M (EFUSE_MAC_SPI_RESERVED_V << EFUSE_MAC_SPI_RESERVED_S) +#define EFUSE_MAC_SPI_RESERVED_V 0x00003FFFU +#define EFUSE_MAC_SPI_RESERVED_S 0 +/** EFUSE_SPI_PAD_CONF_1 : RO; bitpos: [31:14]; default: 0; + * Stores the first part of SPI_PAD_CONF. + */ +#define EFUSE_SPI_PAD_CONF_1 0x0003FFFFU +#define EFUSE_SPI_PAD_CONF_1_M (EFUSE_SPI_PAD_CONF_1_V << EFUSE_SPI_PAD_CONF_1_S) +#define EFUSE_SPI_PAD_CONF_1_V 0x0003FFFFU +#define EFUSE_SPI_PAD_CONF_1_S 14 + +/** EFUSE_RD_MAC_SPI_SYS_3_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) +/** EFUSE_SPI_PAD_CONF_2 : RO; bitpos: [17:0]; default: 0; + * Stores the second part of SPI_PAD_CONF. + */ +#define EFUSE_SPI_PAD_CONF_2 0x0003FFFFU +#define EFUSE_SPI_PAD_CONF_2_M (EFUSE_SPI_PAD_CONF_2_V << EFUSE_SPI_PAD_CONF_2_S) +#define EFUSE_SPI_PAD_CONF_2_V 0x0003FFFFU +#define EFUSE_SPI_PAD_CONF_2_S 0 +/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; + * Stores the first 14 bits of the zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU +#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) +#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU +#define EFUSE_SYS_DATA_PART0_0_S 18 + +/** EFUSE_RD_MAC_SPI_SYS_4_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) +/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of the zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S) +#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_1_S 0 + +/** EFUSE_RD_MAC_SPI_SYS_5_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) +/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of the zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) +#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_2_S 0 + +/** EFUSE_RD_SYS_PART1_DATA0_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) +/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) +#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_0_S 0 + +/** EFUSE_RD_SYS_PART1_DATA1_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) +/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) +#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_1_S 0 + +/** EFUSE_RD_SYS_PART1_DATA2_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) +/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) +#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_2_S 0 + +/** EFUSE_RD_SYS_PART1_DATA3_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) +/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) +#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_3_S 0 + +/** EFUSE_RD_SYS_PART1_DATA4_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) +/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) +#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_4_S 0 + +/** EFUSE_RD_SYS_PART1_DATA5_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) +/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) +#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_5_S 0 + +/** EFUSE_RD_SYS_PART1_DATA6_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) +/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) +#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_6_S 0 + +/** EFUSE_RD_SYS_PART1_DATA7_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) +/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) +#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_7_S 0 + +/** EFUSE_RD_USR_DATA0_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) +/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA0 0xFFFFFFFFU +#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) +#define EFUSE_USR_DATA0_V 0xFFFFFFFFU +#define EFUSE_USR_DATA0_S 0 + +/** EFUSE_RD_USR_DATA1_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) +/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA1 0xFFFFFFFFU +#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) +#define EFUSE_USR_DATA1_V 0xFFFFFFFFU +#define EFUSE_USR_DATA1_S 0 + +/** EFUSE_RD_USR_DATA2_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) +/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA2 0xFFFFFFFFU +#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) +#define EFUSE_USR_DATA2_V 0xFFFFFFFFU +#define EFUSE_USR_DATA2_S 0 + +/** EFUSE_RD_USR_DATA3_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) +/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA3 0xFFFFFFFFU +#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) +#define EFUSE_USR_DATA3_V 0xFFFFFFFFU +#define EFUSE_USR_DATA3_S 0 + +/** EFUSE_RD_USR_DATA4_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) +/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA4 0xFFFFFFFFU +#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) +#define EFUSE_USR_DATA4_V 0xFFFFFFFFU +#define EFUSE_USR_DATA4_S 0 + +/** EFUSE_RD_USR_DATA5_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) +/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA5 0xFFFFFFFFU +#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) +#define EFUSE_USR_DATA5_V 0xFFFFFFFFU +#define EFUSE_USR_DATA5_S 0 + +/** EFUSE_RD_USR_DATA6_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) +/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA6 0xFFFFFFFFU +#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) +#define EFUSE_USR_DATA6_V 0xFFFFFFFFU +#define EFUSE_USR_DATA6_S 0 + +/** EFUSE_RD_USR_DATA7_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) +/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA7 0xFFFFFFFFU +#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) +#define EFUSE_USR_DATA7_V 0xFFFFFFFFU +#define EFUSE_USR_DATA7_S 0 + +/** EFUSE_RD_KEY0_DATA0_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) +/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA0 0xFFFFFFFFU +#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) +#define EFUSE_KEY0_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA0_S 0 + +/** EFUSE_RD_KEY0_DATA1_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) +/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA1 0xFFFFFFFFU +#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) +#define EFUSE_KEY0_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA1_S 0 + +/** EFUSE_RD_KEY0_DATA2_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) +/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA2 0xFFFFFFFFU +#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) +#define EFUSE_KEY0_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA2_S 0 + +/** EFUSE_RD_KEY0_DATA3_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) +/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA3 0xFFFFFFFFU +#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) +#define EFUSE_KEY0_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA3_S 0 + +/** EFUSE_RD_KEY0_DATA4_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) +/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA4 0xFFFFFFFFU +#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) +#define EFUSE_KEY0_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA4_S 0 + +/** EFUSE_RD_KEY0_DATA5_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) +/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA5 0xFFFFFFFFU +#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) +#define EFUSE_KEY0_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA5_S 0 + +/** EFUSE_RD_KEY0_DATA6_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) +/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA6 0xFFFFFFFFU +#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) +#define EFUSE_KEY0_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA6_S 0 + +/** EFUSE_RD_KEY0_DATA7_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) +/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA7 0xFFFFFFFFU +#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) +#define EFUSE_KEY0_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA7_S 0 + +/** EFUSE_RD_KEY1_DATA0_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) +/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA0 0xFFFFFFFFU +#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) +#define EFUSE_KEY1_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA0_S 0 + +/** EFUSE_RD_KEY1_DATA1_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) +/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA1 0xFFFFFFFFU +#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) +#define EFUSE_KEY1_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA1_S 0 + +/** EFUSE_RD_KEY1_DATA2_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) +/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA2 0xFFFFFFFFU +#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) +#define EFUSE_KEY1_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA2_S 0 + +/** EFUSE_RD_KEY1_DATA3_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) +/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA3 0xFFFFFFFFU +#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) +#define EFUSE_KEY1_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA3_S 0 + +/** EFUSE_RD_KEY1_DATA4_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) +/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA4 0xFFFFFFFFU +#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) +#define EFUSE_KEY1_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA4_S 0 + +/** EFUSE_RD_KEY1_DATA5_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) +/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA5 0xFFFFFFFFU +#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) +#define EFUSE_KEY1_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA5_S 0 + +/** EFUSE_RD_KEY1_DATA6_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) +/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA6 0xFFFFFFFFU +#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) +#define EFUSE_KEY1_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA6_S 0 + +/** EFUSE_RD_KEY1_DATA7_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) +/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA7 0xFFFFFFFFU +#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) +#define EFUSE_KEY1_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA7_S 0 + +/** EFUSE_RD_KEY2_DATA0_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) +/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA0 0xFFFFFFFFU +#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) +#define EFUSE_KEY2_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA0_S 0 + +/** EFUSE_RD_KEY2_DATA1_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) +/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA1 0xFFFFFFFFU +#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) +#define EFUSE_KEY2_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA1_S 0 + +/** EFUSE_RD_KEY2_DATA2_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) +/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA2 0xFFFFFFFFU +#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) +#define EFUSE_KEY2_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA2_S 0 + +/** EFUSE_RD_KEY2_DATA3_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) +/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA3 0xFFFFFFFFU +#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) +#define EFUSE_KEY2_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA3_S 0 + +/** EFUSE_RD_KEY2_DATA4_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) +/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA4 0xFFFFFFFFU +#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) +#define EFUSE_KEY2_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA4_S 0 + +/** EFUSE_RD_KEY2_DATA5_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) +/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA5 0xFFFFFFFFU +#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) +#define EFUSE_KEY2_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA5_S 0 + +/** EFUSE_RD_KEY2_DATA6_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) +/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA6 0xFFFFFFFFU +#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) +#define EFUSE_KEY2_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA6_S 0 + +/** EFUSE_RD_KEY2_DATA7_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) +/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA7 0xFFFFFFFFU +#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) +#define EFUSE_KEY2_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA7_S 0 + +/** EFUSE_RD_KEY3_DATA0_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) +/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA0 0xFFFFFFFFU +#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) +#define EFUSE_KEY3_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA0_S 0 + +/** EFUSE_RD_KEY3_DATA1_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) +/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA1 0xFFFFFFFFU +#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) +#define EFUSE_KEY3_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA1_S 0 + +/** EFUSE_RD_KEY3_DATA2_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) +/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA2 0xFFFFFFFFU +#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) +#define EFUSE_KEY3_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA2_S 0 + +/** EFUSE_RD_KEY3_DATA3_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) +/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA3 0xFFFFFFFFU +#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) +#define EFUSE_KEY3_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA3_S 0 + +/** EFUSE_RD_KEY3_DATA4_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) +/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA4 0xFFFFFFFFU +#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) +#define EFUSE_KEY3_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA4_S 0 + +/** EFUSE_RD_KEY3_DATA5_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) +/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA5 0xFFFFFFFFU +#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) +#define EFUSE_KEY3_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA5_S 0 + +/** EFUSE_RD_KEY3_DATA6_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) +/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA6 0xFFFFFFFFU +#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) +#define EFUSE_KEY3_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA6_S 0 + +/** EFUSE_RD_KEY3_DATA7_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) +/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA7 0xFFFFFFFFU +#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) +#define EFUSE_KEY3_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA7_S 0 + +/** EFUSE_RD_KEY4_DATA0_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) +/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA0 0xFFFFFFFFU +#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) +#define EFUSE_KEY4_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA0_S 0 + +/** EFUSE_RD_KEY4_DATA1_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) +/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA1 0xFFFFFFFFU +#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) +#define EFUSE_KEY4_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA1_S 0 + +/** EFUSE_RD_KEY4_DATA2_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) +/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA2 0xFFFFFFFFU +#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) +#define EFUSE_KEY4_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA2_S 0 + +/** EFUSE_RD_KEY4_DATA3_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) +/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA3 0xFFFFFFFFU +#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) +#define EFUSE_KEY4_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA3_S 0 + +/** EFUSE_RD_KEY4_DATA4_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) +/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA4 0xFFFFFFFFU +#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) +#define EFUSE_KEY4_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA4_S 0 + +/** EFUSE_RD_KEY4_DATA5_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) +/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA5 0xFFFFFFFFU +#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) +#define EFUSE_KEY4_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA5_S 0 + +/** EFUSE_RD_KEY4_DATA6_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) +/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA6 0xFFFFFFFFU +#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) +#define EFUSE_KEY4_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA6_S 0 + +/** EFUSE_RD_KEY4_DATA7_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) +/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA7 0xFFFFFFFFU +#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) +#define EFUSE_KEY4_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA7_S 0 + +/** EFUSE_RD_KEY5_DATA0_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) +/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA0 0xFFFFFFFFU +#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) +#define EFUSE_KEY5_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA0_S 0 + +/** EFUSE_RD_KEY5_DATA1_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) +/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA1 0xFFFFFFFFU +#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) +#define EFUSE_KEY5_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA1_S 0 + +/** EFUSE_RD_KEY5_DATA2_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) +/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA2 0xFFFFFFFFU +#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) +#define EFUSE_KEY5_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA2_S 0 + +/** EFUSE_RD_KEY5_DATA3_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) +/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA3 0xFFFFFFFFU +#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) +#define EFUSE_KEY5_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA3_S 0 + +/** EFUSE_RD_KEY5_DATA4_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) +/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA4 0xFFFFFFFFU +#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) +#define EFUSE_KEY5_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA4_S 0 + +/** EFUSE_RD_KEY5_DATA5_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) +/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA5 0xFFFFFFFFU +#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) +#define EFUSE_KEY5_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA5_S 0 + +/** EFUSE_RD_KEY5_DATA6_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) +/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA6 0xFFFFFFFFU +#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) +#define EFUSE_KEY5_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA6_S 0 + +/** EFUSE_RD_KEY5_DATA7_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) +/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA7 0xFFFFFFFFU +#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) +#define EFUSE_KEY5_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA7_S 0 + +/** EFUSE_RD_SYS_PART2_DATA0_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) +/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) +#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_0_S 0 + +/** EFUSE_RD_SYS_PART2_DATA1_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) +/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) +#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_1_S 0 + +/** EFUSE_RD_SYS_PART2_DATA2_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) +/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) +#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_2_S 0 + +/** EFUSE_RD_SYS_PART2_DATA3_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) +/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) +#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_3_S 0 + +/** EFUSE_RD_SYS_PART2_DATA4_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) +/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) +#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_4_S 0 + +/** EFUSE_RD_SYS_PART2_DATA5_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) +/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) +#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_5_S 0 + +/** EFUSE_RD_SYS_PART2_DATA6_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) +/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) +#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_6_S 0 + +/** EFUSE_RD_SYS_PART2_DATA7_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) +/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) +#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_7_S 0 + +/** EFUSE_RD_REPEAT_ERR0_REG register + * Programming error record register 0 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) +/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; + * Indicates a programming error of RD_DIS. + */ +#define EFUSE_RD_DIS_ERR 0x0000007FU +#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) +#define EFUSE_RD_DIS_ERR_V 0x0000007FU +#define EFUSE_RD_DIS_ERR_S 0 +/** EFUSE_SWAP_UART_SDIO_EN_ERR : RO; bitpos: [7]; default: 0; + * Indicates a programming error of SWAP_UART_SDIO_EN. + */ +#define EFUSE_SWAP_UART_SDIO_EN_ERR (BIT(7)) +#define EFUSE_SWAP_UART_SDIO_EN_ERR_M (EFUSE_SWAP_UART_SDIO_EN_ERR_V << EFUSE_SWAP_UART_SDIO_EN_ERR_S) +#define EFUSE_SWAP_UART_SDIO_EN_ERR_V 0x00000001U +#define EFUSE_SWAP_UART_SDIO_EN_ERR_S 7 +/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; + * Indicates a programming error of DIS_ICACHE. + */ +#define EFUSE_DIS_ICACHE_ERR (BIT(8)) +#define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) +#define EFUSE_DIS_ICACHE_ERR_V 0x00000001U +#define EFUSE_DIS_ICACHE_ERR_S 8 +/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0; + * Indicates a programming error of DIS_USB_JTAG. + */ +#define EFUSE_DIS_USB_JTAG_ERR (BIT(9)) +#define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) +#define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_USB_JTAG_ERR_S 9 +/** EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0; + * Indicates a programming error of DIS_DOWNLOAD_ICACHE. + */ +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 +/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0; + * Indicates a programming error of DIS_USB_DEVICE. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR (BIT(11)) +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S 11 +/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; + * Indicates a programming error of DIS_FORCE_DOWNLOAD. + */ +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 +/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0; + * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + */ +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR (BIT(13)) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V 0x00000001U +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S 13 +/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0; + * Indicates a programming error of DIS_CAN. + */ +#define EFUSE_DIS_TWAI_ERR (BIT(14)) +#define EFUSE_DIS_TWAI_ERR_M (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S) +#define EFUSE_DIS_TWAI_ERR_V 0x00000001U +#define EFUSE_DIS_TWAI_ERR_S 14 +/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0; + * Indicates a programming error of JTAG_SEL_ENABLE. + */ +#define EFUSE_JTAG_SEL_ENABLE_ERR (BIT(15)) +#define EFUSE_JTAG_SEL_ENABLE_ERR_M (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S) +#define EFUSE_JTAG_SEL_ENABLE_ERR_V 0x00000001U +#define EFUSE_JTAG_SEL_ENABLE_ERR_S 15 +/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0; + * Indicates a programming error of SOFT_DIS_JTAG. + */ +#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) +#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_ERR_S 16 +/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0; + * Indicates a programming error of DIS_PAD_JTAG. + */ +#define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) +#define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_ERR_S 19 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0; + * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 +/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0; + * Indicates a programming error of USB_DREFH. + */ +#define EFUSE_USB_DREFH_ERR 0x00000003U +#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) +#define EFUSE_USB_DREFH_ERR_V 0x00000003U +#define EFUSE_USB_DREFH_ERR_S 21 +/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0; + * Indicates a programming error of USB_DREFL. + */ +#define EFUSE_USB_DREFL_ERR 0x00000003U +#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) +#define EFUSE_USB_DREFL_ERR_V 0x00000003U +#define EFUSE_USB_DREFL_ERR_S 23 +/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0; + * Indicates a programming error of USB_EXCHG_PINS. + */ +#define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) +#define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_ERR_S 25 +/** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0; + * Indicates a programming error of VDD_SPI_AS_GPIO. + */ +#define EFUSE_VDD_SPI_AS_GPIO_ERR (BIT(26)) +#define EFUSE_VDD_SPI_AS_GPIO_ERR_M (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S) +#define EFUSE_VDD_SPI_AS_GPIO_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_AS_GPIO_ERR_S 26 +/** EFUSE_RPT4_RESERVED0_ERR_2 : RO; bitpos: [28:27]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED0_ERR_2 0x00000003U +#define EFUSE_RPT4_RESERVED0_ERR_2_M (EFUSE_RPT4_RESERVED0_ERR_2_V << EFUSE_RPT4_RESERVED0_ERR_2_S) +#define EFUSE_RPT4_RESERVED0_ERR_2_V 0x00000003U +#define EFUSE_RPT4_RESERVED0_ERR_2_S 27 +/** EFUSE_RPT4_RESERVED0_ERR_1 : RO; bitpos: [29]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED0_ERR_1 (BIT(29)) +#define EFUSE_RPT4_RESERVED0_ERR_1_M (EFUSE_RPT4_RESERVED0_ERR_1_V << EFUSE_RPT4_RESERVED0_ERR_1_S) +#define EFUSE_RPT4_RESERVED0_ERR_1_V 0x00000001U +#define EFUSE_RPT4_RESERVED0_ERR_1_S 29 +/** EFUSE_RPT4_RESERVED0_ERR_0 : RO; bitpos: [31:30]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED0_ERR_0 0x00000003U +#define EFUSE_RPT4_RESERVED0_ERR_0_M (EFUSE_RPT4_RESERVED0_ERR_0_V << EFUSE_RPT4_RESERVED0_ERR_0_S) +#define EFUSE_RPT4_RESERVED0_ERR_0_V 0x00000003U +#define EFUSE_RPT4_RESERVED0_ERR_0_S 30 + +/** EFUSE_RD_REPEAT_ERR1_REG register + * Programming error record register 1 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) +/** EFUSE_RPT4_RESERVED1_ERR_0 : RO; bitpos: [15:0]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED1_ERR_0 0x0000FFFFU +#define EFUSE_RPT4_RESERVED1_ERR_0_M (EFUSE_RPT4_RESERVED1_ERR_0_V << EFUSE_RPT4_RESERVED1_ERR_0_S) +#define EFUSE_RPT4_RESERVED1_ERR_0_V 0x0000FFFFU +#define EFUSE_RPT4_RESERVED1_ERR_0_S 0 +/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; + * Indicates a programming error of WDT_DELAY_SEL. + */ +#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) +#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_S 16 +/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; + * Indicates a programming error of SPI_BOOT_CRYPT_CNT. + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 +/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; + * Indicates a programming error of KEY_PURPOSE_0. + */ +#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) +#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_S 24 +/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; + * Indicates a programming error of KEY_PURPOSE_1. + */ +#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) +#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_S 28 + +/** EFUSE_RD_REPEAT_ERR2_REG register + * Programming error record register 2 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) +/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; + * Indicates a programming error of KEY_PURPOSE_2. + */ +#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) +#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_ERR_S 0 +/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; + * Indicates a programming error of KEY_PURPOSE_3. + */ +#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) +#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_S 4 +/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; + * Indicates a programming error of KEY_PURPOSE_4. + */ +#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) +#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_S 8 +/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; + * Indicates a programming error of KEY_PURPOSE_5. + */ +#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) +#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_S 12 +/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0; + * Indicates a programming error of SEC_DPA_LEVEL. + */ +#define EFUSE_SEC_DPA_LEVEL_ERR 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_ERR_M (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S) +#define EFUSE_SEC_DPA_LEVEL_ERR_V 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_ERR_S 16 +/** EFUSE_RPT4_RESERVED2_ERR_1 : RO; bitpos: [18]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED2_ERR_1 (BIT(18)) +#define EFUSE_RPT4_RESERVED2_ERR_1_M (EFUSE_RPT4_RESERVED2_ERR_1_V << EFUSE_RPT4_RESERVED2_ERR_1_S) +#define EFUSE_RPT4_RESERVED2_ERR_1_V 0x00000001U +#define EFUSE_RPT4_RESERVED2_ERR_1_S 18 +/** EFUSE_CRYPT_DPA_ENABLE_ERR : RO; bitpos: [19]; default: 0; + * Indicates a programming error of CRYPT_DPA_ENABLE. + */ +#define EFUSE_CRYPT_DPA_ENABLE_ERR (BIT(19)) +#define EFUSE_CRYPT_DPA_ENABLE_ERR_M (EFUSE_CRYPT_DPA_ENABLE_ERR_V << EFUSE_CRYPT_DPA_ENABLE_ERR_S) +#define EFUSE_CRYPT_DPA_ENABLE_ERR_V 0x00000001U +#define EFUSE_CRYPT_DPA_ENABLE_ERR_S 19 +/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; + * Indicates a programming error of SECURE_BOOT_EN. + */ +#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) +#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_ERR_S 20 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; + * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 +/** EFUSE_RPT4_RESERVED2_ERR_0 : RO; bitpos: [27:22]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED2_ERR_0 0x0000003FU +#define EFUSE_RPT4_RESERVED2_ERR_0_M (EFUSE_RPT4_RESERVED2_ERR_0_V << EFUSE_RPT4_RESERVED2_ERR_0_S) +#define EFUSE_RPT4_RESERVED2_ERR_0_V 0x0000003FU +#define EFUSE_RPT4_RESERVED2_ERR_0_S 22 +/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; + * Indicates a programming error of FLASH_TPUW. + */ +#define EFUSE_FLASH_TPUW_ERR 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) +#define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_S 28 + +/** EFUSE_RD_REPEAT_ERR3_REG register + * Programming error record register 3 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) +/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; + * Indicates a programming error of DIS_DOWNLOAD_MODE. + */ +#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 +/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0; + * Indicates a programming error of DIS_DIRECT_BOOT. + */ +#define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(1)) +#define EFUSE_DIS_DIRECT_BOOT_ERR_M (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S) +#define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x00000001U +#define EFUSE_DIS_DIRECT_BOOT_ERR_S 1 +/** EFUSE_USB_PRINT_ERR : RO; bitpos: [2]; default: 0; + * Indicates a programming error of UART_PRINT_CHANNEL. + */ +#define EFUSE_USB_PRINT_ERR (BIT(2)) +#define EFUSE_USB_PRINT_ERR_M (EFUSE_USB_PRINT_ERR_V << EFUSE_USB_PRINT_ERR_S) +#define EFUSE_USB_PRINT_ERR_V 0x00000001U +#define EFUSE_USB_PRINT_ERR_S 2 +/** EFUSE_RPT4_RESERVED3_ERR_5 : RO; bitpos: [3]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED3_ERR_5 (BIT(3)) +#define EFUSE_RPT4_RESERVED3_ERR_5_M (EFUSE_RPT4_RESERVED3_ERR_5_V << EFUSE_RPT4_RESERVED3_ERR_5_S) +#define EFUSE_RPT4_RESERVED3_ERR_5_V 0x00000001U +#define EFUSE_RPT4_RESERVED3_ERR_5_S 3 +/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; + * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR (BIT(4)) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; + * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 +/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; + * Indicates a programming error of UART_PRINT_CONTROL. + */ +#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) +#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 +/** EFUSE_RPT4_RESERVED3_ERR_4 : RO; bitpos: [8]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED3_ERR_4 (BIT(8)) +#define EFUSE_RPT4_RESERVED3_ERR_4_M (EFUSE_RPT4_RESERVED3_ERR_4_V << EFUSE_RPT4_RESERVED3_ERR_4_S) +#define EFUSE_RPT4_RESERVED3_ERR_4_V 0x00000001U +#define EFUSE_RPT4_RESERVED3_ERR_4_S 8 +/** EFUSE_RPT4_RESERVED3_ERR_3 : RO; bitpos: [9]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED3_ERR_3 (BIT(9)) +#define EFUSE_RPT4_RESERVED3_ERR_3_M (EFUSE_RPT4_RESERVED3_ERR_3_V << EFUSE_RPT4_RESERVED3_ERR_3_S) +#define EFUSE_RPT4_RESERVED3_ERR_3_V 0x00000001U +#define EFUSE_RPT4_RESERVED3_ERR_3_S 9 +/** EFUSE_RPT4_RESERVED3_ERR_2 : RO; bitpos: [11:10]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED3_ERR_2 0x00000003U +#define EFUSE_RPT4_RESERVED3_ERR_2_M (EFUSE_RPT4_RESERVED3_ERR_2_V << EFUSE_RPT4_RESERVED3_ERR_2_S) +#define EFUSE_RPT4_RESERVED3_ERR_2_V 0x00000003U +#define EFUSE_RPT4_RESERVED3_ERR_2_S 10 +/** EFUSE_RPT4_RESERVED3_ERR_1 : RO; bitpos: [12]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED3_ERR_1 (BIT(12)) +#define EFUSE_RPT4_RESERVED3_ERR_1_M (EFUSE_RPT4_RESERVED3_ERR_1_V << EFUSE_RPT4_RESERVED3_ERR_1_S) +#define EFUSE_RPT4_RESERVED3_ERR_1_V 0x00000001U +#define EFUSE_RPT4_RESERVED3_ERR_1_S 12 +/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [13]; default: 0; + * Indicates a programming error of FORCE_SEND_RESUME. + */ +#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(13)) +#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) +#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_ERR_S 13 +/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [29:14]; default: 0; + * Indicates a programming error of SECURE_VERSION. + */ +#define EFUSE_SECURE_VERSION_ERR 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) +#define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_S 14 +/** EFUSE_RPT4_RESERVED3_ERR_0 : RO; bitpos: [31:30]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED3_ERR_0 0x00000003U +#define EFUSE_RPT4_RESERVED3_ERR_0_M (EFUSE_RPT4_RESERVED3_ERR_0_V << EFUSE_RPT4_RESERVED3_ERR_0_S) +#define EFUSE_RPT4_RESERVED3_ERR_0_V 0x00000003U +#define EFUSE_RPT4_RESERVED3_ERR_0_S 30 + +/** EFUSE_RD_REPEAT_ERR4_REG register + * Programming error record register 4 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190) +/** EFUSE_RPT4_RESERVED4_ERR_1 : RO; bitpos: [23:0]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED4_ERR_1 0x00FFFFFFU +#define EFUSE_RPT4_RESERVED4_ERR_1_M (EFUSE_RPT4_RESERVED4_ERR_1_V << EFUSE_RPT4_RESERVED4_ERR_1_S) +#define EFUSE_RPT4_RESERVED4_ERR_1_V 0x00FFFFFFU +#define EFUSE_RPT4_RESERVED4_ERR_1_S 0 +/** EFUSE_RPT4_RESERVED4_ERR_0 : RO; bitpos: [31:24]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED4_ERR_0 0x000000FFU +#define EFUSE_RPT4_RESERVED4_ERR_0_M (EFUSE_RPT4_RESERVED4_ERR_0_V << EFUSE_RPT4_RESERVED4_ERR_0_S) +#define EFUSE_RPT4_RESERVED4_ERR_0_V 0x000000FFU +#define EFUSE_RPT4_RESERVED4_ERR_0_S 24 + +/** EFUSE_RD_RS_ERR0_REG register + * Programming error record register 0 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) +/** EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007U +#define EFUSE_MAC_SPI_8M_ERR_NUM_M (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S) +#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x00000007U +#define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 +/** EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) +#define EFUSE_MAC_SPI_8M_FAIL_M (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S) +#define EFUSE_MAC_SPI_8M_FAIL_V 0x00000001U +#define EFUSE_MAC_SPI_8M_FAIL_S 3 +/** EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_SYS_PART1_NUM 0x00000007U +#define EFUSE_SYS_PART1_NUM_M (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S) +#define EFUSE_SYS_PART1_NUM_V 0x00000007U +#define EFUSE_SYS_PART1_NUM_S 4 +/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_SYS_PART1_FAIL (BIT(7)) +#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) +#define EFUSE_SYS_PART1_FAIL_V 0x00000001U +#define EFUSE_SYS_PART1_FAIL_S 7 +/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_USR_DATA_ERR_NUM 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) +#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_S 8 +/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the user data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ +#define EFUSE_USR_DATA_FAIL (BIT(11)) +#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) +#define EFUSE_USR_DATA_FAIL_V 0x00000001U +#define EFUSE_USR_DATA_FAIL_S 11 +/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY0_ERR_NUM 0x00000007U +#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) +#define EFUSE_KEY0_ERR_NUM_V 0x00000007U +#define EFUSE_KEY0_ERR_NUM_S 12 +/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of key0 is reliable 1: Means that programming + * key0 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY0_FAIL (BIT(15)) +#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) +#define EFUSE_KEY0_FAIL_V 0x00000001U +#define EFUSE_KEY0_FAIL_S 15 +/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY1_ERR_NUM 0x00000007U +#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) +#define EFUSE_KEY1_ERR_NUM_V 0x00000007U +#define EFUSE_KEY1_ERR_NUM_S 16 +/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of key1 is reliable 1: Means that programming + * key1 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY1_FAIL (BIT(19)) +#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) +#define EFUSE_KEY1_FAIL_V 0x00000001U +#define EFUSE_KEY1_FAIL_S 19 +/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY2_ERR_NUM 0x00000007U +#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) +#define EFUSE_KEY2_ERR_NUM_V 0x00000007U +#define EFUSE_KEY2_ERR_NUM_S 20 +/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of key2 is reliable 1: Means that programming + * key2 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY2_FAIL (BIT(23)) +#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) +#define EFUSE_KEY2_FAIL_V 0x00000001U +#define EFUSE_KEY2_FAIL_S 23 +/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY3_ERR_NUM 0x00000007U +#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) +#define EFUSE_KEY3_ERR_NUM_V 0x00000007U +#define EFUSE_KEY3_ERR_NUM_S 24 +/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of key3 is reliable 1: Means that programming + * key3 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY3_FAIL (BIT(27)) +#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) +#define EFUSE_KEY3_FAIL_V 0x00000001U +#define EFUSE_KEY3_FAIL_S 27 +/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY4_ERR_NUM 0x00000007U +#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) +#define EFUSE_KEY4_ERR_NUM_V 0x00000007U +#define EFUSE_KEY4_ERR_NUM_S 28 +/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of key4 is reliable 1: Means that programming + * key4 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY4_FAIL (BIT(31)) +#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) +#define EFUSE_KEY4_FAIL_V 0x00000001U +#define EFUSE_KEY4_FAIL_S 31 + +/** EFUSE_RD_RS_ERR1_REG register + * Programming error record register 1 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) +/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY5_ERR_NUM 0x00000007U +#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) +#define EFUSE_KEY5_ERR_NUM_V 0x00000007U +#define EFUSE_KEY5_ERR_NUM_S 0 +/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of key5 is reliable 1: Means that programming + * key5 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY5_FAIL (BIT(3)) +#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) +#define EFUSE_KEY5_FAIL_V 0x00000001U +#define EFUSE_KEY5_FAIL_S 3 +/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_SYS_PART2_ERR_NUM 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) +#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_S 4 +/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_SYS_PART2_FAIL (BIT(7)) +#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) +#define EFUSE_SYS_PART2_FAIL_V 0x00000001U +#define EFUSE_SYS_PART2_FAIL_S 7 + +/** EFUSE_CLK_REG register + * eFuse clcok configuration register. + */ +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) +/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to force eFuse SRAM into power-saving mode. + */ +#define EFUSE_MEM_FORCE_PD (BIT(0)) +#define EFUSE_MEM_FORCE_PD_M (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S) +#define EFUSE_MEM_FORCE_PD_V 0x00000001U +#define EFUSE_MEM_FORCE_PD_S 0 +/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; + * Set this bit and force to activate clock signal of eFuse SRAM. + */ +#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) +#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) +#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U +#define EFUSE_MEM_CLK_FORCE_ON_S 1 +/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; + * Set this bit to force eFuse SRAM into working mode. + */ +#define EFUSE_MEM_FORCE_PU (BIT(2)) +#define EFUSE_MEM_FORCE_PU_M (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S) +#define EFUSE_MEM_FORCE_PU_V 0x00000001U +#define EFUSE_MEM_FORCE_PU_S 2 +/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; + * Set this bit to force enable eFuse register configuration clock signal. + */ +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) +#define EFUSE_CLK_EN_V 0x00000001U +#define EFUSE_CLK_EN_S 16 + +/** EFUSE_CONF_REG register + * eFuse operation mode configuraiton register + */ +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) +/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: programming operation command 0x5AA5: read operation command. + */ +#define EFUSE_OP_CODE 0x0000FFFFU +#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) +#define EFUSE_OP_CODE_V 0x0000FFFFU +#define EFUSE_OP_CODE_S 0 + +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + +/** EFUSE_STATUS_REG register + * eFuse status register. + */ +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) +/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ +#define EFUSE_STATE 0x0000000FU +#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) +#define EFUSE_STATE_V 0x0000000FU +#define EFUSE_STATE_S 0 +/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ +#define EFUSE_OTP_LOAD_SW (BIT(4)) +#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) +#define EFUSE_OTP_LOAD_SW_V 0x00000001U +#define EFUSE_OTP_LOAD_SW_S 4 +/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ +#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) +#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001U +#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 +/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ +#define EFUSE_OTP_STROBE_SW (BIT(6)) +#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) +#define EFUSE_OTP_STROBE_SW_V 0x00000001U +#define EFUSE_OTP_STROBE_SW_S 6 +/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ +#define EFUSE_OTP_CSB_SW (BIT(7)) +#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) +#define EFUSE_OTP_CSB_SW_V 0x00000001U +#define EFUSE_OTP_CSB_SW_S 7 +/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ +#define EFUSE_OTP_PGENB_SW (BIT(8)) +#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) +#define EFUSE_OTP_PGENB_SW_V 0x00000001U +#define EFUSE_OTP_PGENB_SW_S 8 +/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ +#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) +#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001U +#define EFUSE_OTP_VDDQ_IS_SW_S 9 +/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0; + * Indicates the number of block valid bit. + */ +#define EFUSE_BLK0_VALID_BIT_CNT 0x000003FFU +#define EFUSE_BLK0_VALID_BIT_CNT_M (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S) +#define EFUSE_BLK0_VALID_BIT_CNT_V 0x000003FFU +#define EFUSE_BLK0_VALID_BIT_CNT_S 10 + +/** EFUSE_CMD_REG register + * eFuse command register. + */ +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) +/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ +#define EFUSE_READ_CMD (BIT(0)) +#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) +#define EFUSE_READ_CMD_V 0x00000001U +#define EFUSE_READ_CMD_S 0 +/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) +#define EFUSE_PGM_CMD_V 0x00000001U +#define EFUSE_PGM_CMD_S 1 +/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ +#define EFUSE_BLK_NUM 0x0000000FU +#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) +#define EFUSE_BLK_NUM_V 0x0000000FU +#define EFUSE_BLK_NUM_S 2 + +/** EFUSE_INT_RAW_REG register + * eFuse raw interrupt register. + */ +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) +/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) +#define EFUSE_READ_DONE_INT_RAW_V 0x00000001U +#define EFUSE_READ_DONE_INT_RAW_S 0 +/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) +#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001U +#define EFUSE_PGM_DONE_INT_RAW_S 1 + +/** EFUSE_INT_ST_REG register + * eFuse interrupt status register. + */ +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) +/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_ST (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) +#define EFUSE_READ_DONE_INT_ST_V 0x00000001U +#define EFUSE_READ_DONE_INT_ST_S 0 +/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) +#define EFUSE_PGM_DONE_INT_ST_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ST_S 1 + +/** EFUSE_INT_ENA_REG register + * eFuse interrupt enable register. + */ +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) +/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) +#define EFUSE_READ_DONE_INT_ENA_V 0x00000001U +#define EFUSE_READ_DONE_INT_ENA_S 0 +/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) +#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ENA_S 1 + +/** EFUSE_INT_CLR_REG register + * eFuse interrupt clear register. + */ +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) +/** EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) +#define EFUSE_READ_DONE_INT_CLR_V 0x00000001U +#define EFUSE_READ_DONE_INT_CLR_S 0 +/** EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) +#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001U +#define EFUSE_PGM_DONE_INT_CLR_S 1 + +/** EFUSE_DAC_CONF_REG register + * Controls the eFuse programming voltage. + */ +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) +/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28; + * Controls the division factor of the rising clock of the programming voltage. + */ +#define EFUSE_DAC_CLK_DIV 0x000000FFU +#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) +#define EFUSE_DAC_CLK_DIV_V 0x000000FFU +#define EFUSE_DAC_CLK_DIV_S 0 +/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; + * Don't care. + */ +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U +#define EFUSE_DAC_CLK_PAD_SEL_S 8 +/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ +#define EFUSE_DAC_NUM 0x000000FFU +#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) +#define EFUSE_DAC_NUM_V 0x000000FFU +#define EFUSE_DAC_NUM_S 9 +/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ +#define EFUSE_OE_CLR (BIT(17)) +#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) +#define EFUSE_OE_CLR_V 0x00000001U +#define EFUSE_OE_CLR_S 17 + +/** EFUSE_RD_TIM_CONF_REG register + * Configures read timing parameters. + */ +#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) +/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; + * Configures the read hold time. + */ +#define EFUSE_THR_A 0x000000FFU +#define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) +#define EFUSE_THR_A_V 0x000000FFU +#define EFUSE_THR_A_S 0 +/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2; + * Configures the read time. + */ +#define EFUSE_TRD 0x000000FFU +#define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) +#define EFUSE_TRD_V 0x000000FFU +#define EFUSE_TRD_S 8 +/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; + * Configures the read setup time. + */ +#define EFUSE_TSUR_A 0x000000FFU +#define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) +#define EFUSE_TSUR_A_V 0x000000FFU +#define EFUSE_TSUR_A_S 16 +/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; + * Configures the waiting time of reading eFuse memory. + */ +#define EFUSE_READ_INIT_NUM 0x000000FFU +#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) +#define EFUSE_READ_INIT_NUM_V 0x000000FFU +#define EFUSE_READ_INIT_NUM_S 24 + +/** EFUSE_WR_TIM_CONF1_REG register + * Configurarion register 1 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0) +/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; + * Configures the programming setup time. + */ +#define EFUSE_TSUP_A 0x000000FFU +#define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) +#define EFUSE_TSUP_A_V 0x000000FFU +#define EFUSE_TSUP_A_S 0 +/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 12288; + * Configures the power up time for VDDQ. + */ +#define EFUSE_PWR_ON_NUM 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) +#define EFUSE_PWR_ON_NUM_V 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_S 8 +/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1; + * Configures the programming hold time. + */ +#define EFUSE_THP_A 0x000000FFU +#define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) +#define EFUSE_THP_A_V 0x000000FFU +#define EFUSE_THP_A_S 24 + +/** EFUSE_WR_TIM_CONF2_REG register + * Configurarion register 2 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4) +/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ +#define EFUSE_PWR_OFF_NUM 0x0000FFFFU +#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) +#define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU +#define EFUSE_PWR_OFF_NUM_S 0 +/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 200; + * Configures the active programming time. + */ +#define EFUSE_TPGM 0x0000FFFFU +#define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) +#define EFUSE_TPGM_V 0x0000FFFFU +#define EFUSE_TPGM_S 16 + +/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register + * Configurarion register0 of eFuse programming time parameters and rs bypass + * operation. + */ +#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8) +/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0; + * Set this bit to bypass reed solomon correction step. + */ +#define EFUSE_BYPASS_RS_CORRECTION (BIT(0)) +#define EFUSE_BYPASS_RS_CORRECTION_M (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S) +#define EFUSE_BYPASS_RS_CORRECTION_V 0x00000001U +#define EFUSE_BYPASS_RS_CORRECTION_S 0 +/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0; + * Configures block number of programming twice operation. + */ +#define EFUSE_BYPASS_RS_BLK_NUM 0x000007FFU +#define EFUSE_BYPASS_RS_BLK_NUM_M (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S) +#define EFUSE_BYPASS_RS_BLK_NUM_V 0x000007FFU +#define EFUSE_BYPASS_RS_BLK_NUM_S 1 +/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0; + * Set this bit to update multi-bit register signals. + */ +#define EFUSE_UPDATE (BIT(12)) +#define EFUSE_UPDATE_M (EFUSE_UPDATE_V << EFUSE_UPDATE_S) +#define EFUSE_UPDATE_V 0x00000001U +#define EFUSE_UPDATE_S 12 +/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1; + * Configures the inactive programming time. + */ +#define EFUSE_TPGM_INACTIVE 0x000000FFU +#define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) +#define EFUSE_TPGM_INACTIVE_V 0x000000FFU +#define EFUSE_TPGM_INACTIVE_S 13 + +/** EFUSE_DATE_REG register + * eFuse version register. + */ +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) +/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 35676928; + * Stores eFuse version. + */ +#define EFUSE_DATE 0x0FFFFFFFU +#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) +#define EFUSE_DATE_V 0x0FFFFFFFU +#define EFUSE_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/efuse_struct.h b/components/soc/esp32c6/include/soc/efuse_struct.h new file mode 100644 index 0000000000..2090d26ce2 --- /dev/null +++ b/components/soc/esp32c6/include/soc/efuse_struct.h @@ -0,0 +1,2294 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: PGM Data Register */ +/** Type of pgm_data0 register + * Register 0 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data0_reg_t; + +/** Type of pgm_data1 register + * Register 1 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit data to be programmed. + */ + uint32_t pgm_data_1:32; + }; + uint32_t val; +} efuse_pgm_data1_reg_t; + +/** Type of pgm_data2 register + * Register 2 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit data to be programmed. + */ + uint32_t pgm_data_2:32; + }; + uint32_t val; +} efuse_pgm_data2_reg_t; + +/** Type of pgm_data3 register + * Register 3 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; + * Configures the 3rd 32-bit data to be programmed. + */ + uint32_t pgm_data_3:32; + }; + uint32_t val; +} efuse_pgm_data3_reg_t; + +/** Type of pgm_data4 register + * Register 4 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; + * Configures the 4th 32-bit data to be programmed. + */ + uint32_t pgm_data_4:32; + }; + uint32_t val; +} efuse_pgm_data4_reg_t; + +/** Type of pgm_data5 register + * Register 5 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; + * Configures the 5th 32-bit data to be programmed. + */ + uint32_t pgm_data_5:32; + }; + uint32_t val; +} efuse_pgm_data5_reg_t; + +/** Type of pgm_data6 register + * Register 6 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; + * Configures the 6th 32-bit data to be programmed. + */ + uint32_t pgm_data_6:32; + }; + uint32_t val; +} efuse_pgm_data6_reg_t; + +/** Type of pgm_data7 register + * Register 7 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; + * Configures the 7th 32-bit data to be programmed. + */ + uint32_t pgm_data_7:32; + }; + uint32_t val; +} efuse_pgm_data7_reg_t; + +/** Type of pgm_check_value0 register + * Register 0 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_0:32; + }; + uint32_t val; +} efuse_pgm_check_value0_reg_t; + +/** Type of pgm_check_value1 register + * Register 1 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_1:32; + }; + uint32_t val; +} efuse_pgm_check_value1_reg_t; + +/** Type of pgm_check_value2 register + * Register 2 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_2:32; + }; + uint32_t val; +} efuse_pgm_check_value2_reg_t; + + +/** Group: ******** Registers */ +/** Type of rd_wr_dis register + * BLOCK0 data register 0. + */ +typedef union { + struct { + /** wr_dis : RO; bitpos: [31:0]; default: 0; + * Represents whether programming of individual eFuse memory bit is disabled or + * enabled. 1: Disabled. 0 Enabled. + */ + uint32_t wr_dis:32; + }; + uint32_t val; +} efuse_rd_wr_dis_reg_t; + +/** Type of rd_repeat_data0 register + * BLOCK0 data register 1. + */ +typedef union { + struct { + /** rd_dis : RO; bitpos: [6:0]; default: 0; + * Represents whether reading of individual eFuse block(block4~block10) is disabled or + * enabled. 1: disabled. 0: enabled. + */ + uint32_t rd_dis:7; + /** swap_uart_sdio_en : RO; bitpos: [7]; default: 0; + * Represents whether pad of uart and sdio is swapped or not. 1: swapped. 0: not + * swapped. + */ + uint32_t swap_uart_sdio_en:1; + /** dis_icache : RO; bitpos: [8]; default: 0; + * Represents whether icache is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_icache:1; + /** dis_usb_jtag : RO; bitpos: [9]; default: 0; + * Represents whether the function of usb switch to jtag is disabled or enabled. 1: + * disabled. 0: enabled. + */ + uint32_t dis_usb_jtag:1; + /** dis_download_icache : RO; bitpos: [10]; default: 0; + * Represents whether icache is disabled or enabled in Download mode. 1: disabled. 0: + * enabled. + */ + uint32_t dis_download_icache:1; + /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0; + * Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_usb_serial_jtag:1; + /** dis_force_download : RO; bitpos: [12]; default: 0; + * Represents whether the function that forces chip into download mode is disabled or + * enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_force_download:1; + /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0; + * Represents whether SPI0 controller during boot_mode_download is disabled or + * enabled. 1: disabled. 0: enabled. + */ + uint32_t spi_download_mspi_dis:1; + /** dis_can : RO; bitpos: [14]; default: 0; + * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_can:1; + /** jtag_sel_enable : RO; bitpos: [15]; default: 0; + * Represents whether the selection between usb_to_jtag and pad_to_jtag through + * strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 + * is enabled or disabled. 1: enabled. 0: disabled. + */ + uint32_t jtag_sel_enable:1; + /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; + * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: + * enabled. + */ + uint32_t soft_dis_jtag:3; + /** dis_pad_jtag : RO; bitpos: [19]; default: 0; + * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: + * enabled. + */ + uint32_t dis_pad_jtag:1; + /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; + * Represents whether flash encrypt function is disabled or enabled(except in SPI boot + * mode). 1: disabled. 0: enabled. + */ + uint32_t dis_download_manual_encrypt:1; + /** usb_drefh : RO; bitpos: [22:21]; default: 0; + * Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV. + */ + uint32_t usb_drefh:2; + /** usb_drefl : RO; bitpos: [24:23]; default: 0; + * Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV. + */ + uint32_t usb_drefl:2; + /** usb_exchg_pins : RO; bitpos: [25]; default: 0; + * Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged. + */ + uint32_t usb_exchg_pins:1; + /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0; + * Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not + * functioned. + */ + uint32_t vdd_spi_as_gpio:1; + /** rpt4_reserved0_2 : RO; bitpos: [28:27]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved0_2:2; + /** rpt4_reserved0_1 : RO; bitpos: [29]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved0_1:1; + /** rpt4_reserved0_0 : RO; bitpos: [31:30]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved0_0:2; + }; + uint32_t val; +} efuse_rd_repeat_data0_reg_t; + +/** Type of rd_repeat_data1 register + * BLOCK0 data register 2. + */ +typedef union { + struct { + /** rpt4_reserved1_0 : RO; bitpos: [15:0]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved1_0:16; + /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; + * Represents whether RTC watchdog timeout threshold is selected at startup. 1: + * selected. 0: not selected. + */ + uint32_t wdt_delay_sel:2; + /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; + * Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of + * 1: enabled. Even number of 1: disabled. + */ + uint32_t spi_boot_crypt_cnt:3; + /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; + * Represents whether revoking first secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_key_revoke0:1; + /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; + * Represents whether revoking second secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_key_revoke1:1; + /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; + * Represents whether revoking third secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_key_revoke2:1; + /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; + * Represents the purpose of Key0. + */ + uint32_t key_purpose_0:4; + /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; + * Represents the purpose of Key1. + */ + uint32_t key_purpose_1:4; + }; + uint32_t val; +} efuse_rd_repeat_data1_reg_t; + +/** Type of rd_repeat_data2 register + * BLOCK0 data register 3. + */ +typedef union { + struct { + /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; + * Represents the purpose of Key2. + */ + uint32_t key_purpose_2:4; + /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; + * Represents the purpose of Key3. + */ + uint32_t key_purpose_3:4; + /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; + * Represents the purpose of Key4. + */ + uint32_t key_purpose_4:4; + /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; + * Represents the purpose of Key5. + */ + uint32_t key_purpose_5:4; + /** dpa_sec_level : RO; bitpos: [17:16]; default: 0; + * Represents the spa secure level by configuring the clock random divide mode. + */ + uint32_t dpa_sec_level:2; + /** rpt4_reserved2_1 : RO; bitpos: [18]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved2_1:1; + /** crypt_dpa_enable : RO; bitpos: [19]; default: 1; + * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. + */ + uint32_t crypt_dpa_enable:1; + /** secure_boot_en : RO; bitpos: [20]; default: 0; + * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. + */ + uint32_t secure_boot_en:1; + /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; + * Represents whether revoking aggressive secure boot is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_aggressive_revoke:1; + /** rpt4_reserved2_0 : RO; bitpos: [27:22]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved2_0:6; + /** flash_tpuw : RO; bitpos: [31:28]; default: 0; + * Represents the flash waiting time after power-up, in unit of ms. When the value + * less than 15, the waiting time is the programmed value. Otherwise, the waiting time + * is 2 times the programmed value. + */ + uint32_t flash_tpuw:4; + }; + uint32_t val; +} efuse_rd_repeat_data2_reg_t; + +/** Type of rd_repeat_data3 register + * BLOCK0 data register 4. + */ +typedef union { + struct { + /** dis_download_mode : RO; bitpos: [0]; default: 0; + * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_download_mode:1; + /** dis_direct_boot : RO; bitpos: [1]; default: 0; + * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_direct_boot:1; + /** dis_usb_print : RO; bitpos: [2]; default: 0; + * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. + * 0: enabled. + */ + uint32_t dis_usb_print:1; + /** rpt4_reserved3_5 : RO; bitpos: [3]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved3_5:1; + /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; + * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: + * disabled. 0: enabled. + */ + uint32_t dis_usb_serial_jtag_download_mode:1; + /** enable_security_download : RO; bitpos: [5]; default: 0; + * Represents whether security download is enabled or disabled. 1: enabled. 0: + * disabled. + */ + uint32_t enable_security_download:1; + /** uart_print_control : RO; bitpos: [7:6]; default: 0; + * Represents the type of UART printing. 00: force enable printing. 01: enable + * printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset + * at high level. 11: force disable printing. + */ + uint32_t uart_print_control:2; + /** rpt4_reserved3_4 : RO; bitpos: [8]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved3_4:1; + /** rpt4_reserved3_3 : RO; bitpos: [9]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved3_3:1; + /** rpt4_reserved3_2 : RO; bitpos: [11:10]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved3_2:2; + /** rpt4_reserved3_1 : RO; bitpos: [12]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved3_1:1; + /** force_send_resume : RO; bitpos: [13]; default: 0; + * Represents whether ROM code is forced to send a resume command during SPI boot. 1: + * forced. 0:not forced. + */ + uint32_t force_send_resume:1; + /** secure_version : RO; bitpos: [29:14]; default: 0; + * Represents the version used by ESP-IDF anti-rollback feature. + */ + uint32_t secure_version:16; + /** secure_boot_disable_fast_wake : RO; bitpos: [30]; default: 0; + * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is + * enabled. 1: disabled. 0: enabled. + */ + uint32_t secure_boot_disable_fast_wake:1; + /** rpt4_reserved3_0 : RO; bitpos: [31]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved3_0:1; + }; + uint32_t val; +} efuse_rd_repeat_data3_reg_t; + +/** Type of rd_repeat_data4 register + * BLOCK0 data register 5. + */ +typedef union { + struct { + uint32_t disable_wafer_version_major:1; + uint32_t disable_blk_version_major: 1; + uint32_t rpt4_reserved4:22; /*Reserved.*/ + uint32_t reserved24:8; /*Reserved.*/ + }; + uint32_t val; +} efuse_rd_repeat_data4_reg_t; + +/** Type of rd_mac_spi_sys_0 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** mac_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ + uint32_t mac_0:32; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_0_reg_t; + +/** Type of rd_mac_spi_sys_1 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** mac_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ + uint32_t mac_1:16; + /** spi_pad_conf_0 : RO; bitpos: [31:16]; default: 0; + * Stores the zeroth part of SPI_PAD_CONF. + */ + uint32_t spi_pad_conf_0:16; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_1_reg_t; + +/** Type of rd_mac_spi_sys_2 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + uint32_t reserved:32; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_2_reg_t; + +/** Type of rd_mac_spi_sys_3 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** spi_pad_conf_2 : RO; bitpos: [17:0]; default: 0; + * Stores the second part of SPI_PAD_CONF. + */ + uint32_t spi_pad_conf_2:18; + uint32_t wafer_version_minor_low:3; + uint32_t pkg_version:3; + uint32_t blk_version_minor:3; + /** sys_data_part0_0 : RO; bitpos: [31:27]; default: 0; + * Stores the first 5 bits of the zeroth part of system data. + */ + uint32_t sys_data_part0_0:5; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_3_reg_t; + +/** Type of rd_mac_spi_sys_4 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + uint32_t reserved:32; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_4_reg_t; + +/** Type of rd_mac_spi_sys_5 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + uint32_t reserved1:23; + uint32_t wafer_version_minor_high:1; + uint32_t wafer_version_major:2; + uint32_t reserved2:6; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_5_reg_t; + +/** Type of rd_sys_part1_data0 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_0:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data0_reg_t; + +/** Type of rd_sys_part1_data1 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_1:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data1_reg_t; + +/** Type of rd_sys_part1_data2 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_2:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data2_reg_t; + +/** Type of rd_sys_part1_data3 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_3:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data3_reg_t; + +/** Type of rd_sys_part1_data4 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + uint32_t blk_version_major :2; + uint32_t reserved1:30; + }; + uint32_t val; +} efuse_rd_sys_part1_data4_reg_t; + +/** Type of rd_sys_part1_data5 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_5:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data5_reg_t; + +/** Type of rd_sys_part1_data6 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_6:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data6_reg_t; + +/** Type of rd_sys_part1_data7 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_7:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data7_reg_t; + +/** Type of rd_usr_data0 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data0:32; + }; + uint32_t val; +} efuse_rd_usr_data0_reg_t; + +/** Type of rd_usr_data1 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of BLOCK3 (user). + */ + uint32_t usr_data1:32; + }; + uint32_t val; +} efuse_rd_usr_data1_reg_t; + +/** Type of rd_usr_data2 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of BLOCK3 (user). + */ + uint32_t usr_data2:32; + }; + uint32_t val; +} efuse_rd_usr_data2_reg_t; + +/** Type of rd_usr_data3 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of BLOCK3 (user). + */ + uint32_t usr_data3:32; + }; + uint32_t val; +} efuse_rd_usr_data3_reg_t; + +/** Type of rd_usr_data4 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data4:32; + }; + uint32_t val; +} efuse_rd_usr_data4_reg_t; + +/** Type of rd_usr_data5 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data5:32; + }; + uint32_t val; +} efuse_rd_usr_data5_reg_t; + +/** Type of rd_usr_data6 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data6:32; + }; + uint32_t val; +} efuse_rd_usr_data6_reg_t; + +/** Type of rd_usr_data7 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of BLOCK3 (user). + */ + uint32_t usr_data7:32; + }; + uint32_t val; +} efuse_rd_usr_data7_reg_t; + +/** Type of rd_key0_data0 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY0. + */ + uint32_t key0_data0:32; + }; + uint32_t val; +} efuse_rd_key0_data0_reg_t; + +/** Type of rd_key0_data1 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY0. + */ + uint32_t key0_data1:32; + }; + uint32_t val; +} efuse_rd_key0_data1_reg_t; + +/** Type of rd_key0_data2 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY0. + */ + uint32_t key0_data2:32; + }; + uint32_t val; +} efuse_rd_key0_data2_reg_t; + +/** Type of rd_key0_data3 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY0. + */ + uint32_t key0_data3:32; + }; + uint32_t val; +} efuse_rd_key0_data3_reg_t; + +/** Type of rd_key0_data4 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY0. + */ + uint32_t key0_data4:32; + }; + uint32_t val; +} efuse_rd_key0_data4_reg_t; + +/** Type of rd_key0_data5 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY0. + */ + uint32_t key0_data5:32; + }; + uint32_t val; +} efuse_rd_key0_data5_reg_t; + +/** Type of rd_key0_data6 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY0. + */ + uint32_t key0_data6:32; + }; + uint32_t val; +} efuse_rd_key0_data6_reg_t; + +/** Type of rd_key0_data7 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY0. + */ + uint32_t key0_data7:32; + }; + uint32_t val; +} efuse_rd_key0_data7_reg_t; + +/** Type of rd_key1_data0 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY1. + */ + uint32_t key1_data0:32; + }; + uint32_t val; +} efuse_rd_key1_data0_reg_t; + +/** Type of rd_key1_data1 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY1. + */ + uint32_t key1_data1:32; + }; + uint32_t val; +} efuse_rd_key1_data1_reg_t; + +/** Type of rd_key1_data2 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY1. + */ + uint32_t key1_data2:32; + }; + uint32_t val; +} efuse_rd_key1_data2_reg_t; + +/** Type of rd_key1_data3 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY1. + */ + uint32_t key1_data3:32; + }; + uint32_t val; +} efuse_rd_key1_data3_reg_t; + +/** Type of rd_key1_data4 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY1. + */ + uint32_t key1_data4:32; + }; + uint32_t val; +} efuse_rd_key1_data4_reg_t; + +/** Type of rd_key1_data5 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY1. + */ + uint32_t key1_data5:32; + }; + uint32_t val; +} efuse_rd_key1_data5_reg_t; + +/** Type of rd_key1_data6 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY1. + */ + uint32_t key1_data6:32; + }; + uint32_t val; +} efuse_rd_key1_data6_reg_t; + +/** Type of rd_key1_data7 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY1. + */ + uint32_t key1_data7:32; + }; + uint32_t val; +} efuse_rd_key1_data7_reg_t; + +/** Type of rd_key2_data0 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY2. + */ + uint32_t key2_data0:32; + }; + uint32_t val; +} efuse_rd_key2_data0_reg_t; + +/** Type of rd_key2_data1 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY2. + */ + uint32_t key2_data1:32; + }; + uint32_t val; +} efuse_rd_key2_data1_reg_t; + +/** Type of rd_key2_data2 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY2. + */ + uint32_t key2_data2:32; + }; + uint32_t val; +} efuse_rd_key2_data2_reg_t; + +/** Type of rd_key2_data3 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY2. + */ + uint32_t key2_data3:32; + }; + uint32_t val; +} efuse_rd_key2_data3_reg_t; + +/** Type of rd_key2_data4 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY2. + */ + uint32_t key2_data4:32; + }; + uint32_t val; +} efuse_rd_key2_data4_reg_t; + +/** Type of rd_key2_data5 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY2. + */ + uint32_t key2_data5:32; + }; + uint32_t val; +} efuse_rd_key2_data5_reg_t; + +/** Type of rd_key2_data6 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY2. + */ + uint32_t key2_data6:32; + }; + uint32_t val; +} efuse_rd_key2_data6_reg_t; + +/** Type of rd_key2_data7 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY2. + */ + uint32_t key2_data7:32; + }; + uint32_t val; +} efuse_rd_key2_data7_reg_t; + +/** Type of rd_key3_data0 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY3. + */ + uint32_t key3_data0:32; + }; + uint32_t val; +} efuse_rd_key3_data0_reg_t; + +/** Type of rd_key3_data1 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY3. + */ + uint32_t key3_data1:32; + }; + uint32_t val; +} efuse_rd_key3_data1_reg_t; + +/** Type of rd_key3_data2 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY3. + */ + uint32_t key3_data2:32; + }; + uint32_t val; +} efuse_rd_key3_data2_reg_t; + +/** Type of rd_key3_data3 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY3. + */ + uint32_t key3_data3:32; + }; + uint32_t val; +} efuse_rd_key3_data3_reg_t; + +/** Type of rd_key3_data4 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY3. + */ + uint32_t key3_data4:32; + }; + uint32_t val; +} efuse_rd_key3_data4_reg_t; + +/** Type of rd_key3_data5 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY3. + */ + uint32_t key3_data5:32; + }; + uint32_t val; +} efuse_rd_key3_data5_reg_t; + +/** Type of rd_key3_data6 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY3. + */ + uint32_t key3_data6:32; + }; + uint32_t val; +} efuse_rd_key3_data6_reg_t; + +/** Type of rd_key3_data7 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY3. + */ + uint32_t key3_data7:32; + }; + uint32_t val; +} efuse_rd_key3_data7_reg_t; + +/** Type of rd_key4_data0 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY4. + */ + uint32_t key4_data0:32; + }; + uint32_t val; +} efuse_rd_key4_data0_reg_t; + +/** Type of rd_key4_data1 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY4. + */ + uint32_t key4_data1:32; + }; + uint32_t val; +} efuse_rd_key4_data1_reg_t; + +/** Type of rd_key4_data2 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY4. + */ + uint32_t key4_data2:32; + }; + uint32_t val; +} efuse_rd_key4_data2_reg_t; + +/** Type of rd_key4_data3 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY4. + */ + uint32_t key4_data3:32; + }; + uint32_t val; +} efuse_rd_key4_data3_reg_t; + +/** Type of rd_key4_data4 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY4. + */ + uint32_t key4_data4:32; + }; + uint32_t val; +} efuse_rd_key4_data4_reg_t; + +/** Type of rd_key4_data5 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY4. + */ + uint32_t key4_data5:32; + }; + uint32_t val; +} efuse_rd_key4_data5_reg_t; + +/** Type of rd_key4_data6 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY4. + */ + uint32_t key4_data6:32; + }; + uint32_t val; +} efuse_rd_key4_data6_reg_t; + +/** Type of rd_key4_data7 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY4. + */ + uint32_t key4_data7:32; + }; + uint32_t val; +} efuse_rd_key4_data7_reg_t; + +/** Type of rd_key5_data0 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY5. + */ + uint32_t key5_data0:32; + }; + uint32_t val; +} efuse_rd_key5_data0_reg_t; + +/** Type of rd_key5_data1 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY5. + */ + uint32_t key5_data1:32; + }; + uint32_t val; +} efuse_rd_key5_data1_reg_t; + +/** Type of rd_key5_data2 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY5. + */ + uint32_t key5_data2:32; + }; + uint32_t val; +} efuse_rd_key5_data2_reg_t; + +/** Type of rd_key5_data3 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY5. + */ + uint32_t key5_data3:32; + }; + uint32_t val; +} efuse_rd_key5_data3_reg_t; + +/** Type of rd_key5_data4 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY5. + */ + uint32_t key5_data4:32; + }; + uint32_t val; +} efuse_rd_key5_data4_reg_t; + +/** Type of rd_key5_data5 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY5. + */ + uint32_t key5_data5:32; + }; + uint32_t val; +} efuse_rd_key5_data5_reg_t; + +/** Type of rd_key5_data6 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY5. + */ + uint32_t key5_data6:32; + }; + uint32_t val; +} efuse_rd_key5_data6_reg_t; + +/** Type of rd_key5_data7 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY5. + */ + uint32_t key5_data7:32; + }; + uint32_t val; +} efuse_rd_key5_data7_reg_t; + +/** Type of rd_sys_part2_data0 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_0:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data0_reg_t; + +/** Type of rd_sys_part2_data1 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_1:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data1_reg_t; + +/** Type of rd_sys_part2_data2 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_2:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data2_reg_t; + +/** Type of rd_sys_part2_data3 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_3:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data3_reg_t; + +/** Type of rd_sys_part2_data4 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_4:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data4_reg_t; + +/** Type of rd_sys_part2_data5 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_5:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data5_reg_t; + +/** Type of rd_sys_part2_data6 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_6:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data6_reg_t; + +/** Type of rd_sys_part2_data7 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_7:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data7_reg_t; + +/** Type of rd_repeat_err0 register + * Programming error record register 0 of BLOCK0. + */ +typedef union { + struct { + /** rd_dis_err : RO; bitpos: [6:0]; default: 0; + * Indicates a programming error of RD_DIS. + */ + uint32_t rd_dis_err:7; + /** swap_uart_sdio_en_err : RO; bitpos: [7]; default: 0; + * Indicates a programming error of SWAP_UART_SDIO_EN. + */ + uint32_t swap_uart_sdio_en_err:1; + /** dis_icache_err : RO; bitpos: [8]; default: 0; + * Indicates a programming error of DIS_ICACHE. + */ + uint32_t dis_icache_err:1; + /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0; + * Indicates a programming error of DIS_USB_JTAG. + */ + uint32_t dis_usb_jtag_err:1; + /** dis_download_icache_err : RO; bitpos: [10]; default: 0; + * Indicates a programming error of DIS_DOWNLOAD_ICACHE. + */ + uint32_t dis_download_icache_err:1; + /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0; + * Indicates a programming error of DIS_USB_DEVICE. + */ + uint32_t dis_usb_serial_jtag_err:1; + /** dis_force_download_err : RO; bitpos: [12]; default: 0; + * Indicates a programming error of DIS_FORCE_DOWNLOAD. + */ + uint32_t dis_force_download_err:1; + /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0; + * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + */ + uint32_t spi_download_mspi_dis_err:1; + /** dis_twai_err : RO; bitpos: [14]; default: 0; + * Indicates a programming error of DIS_CAN. + */ + uint32_t dis_twai_err:1; + /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0; + * Indicates a programming error of JTAG_SEL_ENABLE. + */ + uint32_t jtag_sel_enable_err:1; + /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; + * Indicates a programming error of SOFT_DIS_JTAG. + */ + uint32_t soft_dis_jtag_err:3; + /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; + * Indicates a programming error of DIS_PAD_JTAG. + */ + uint32_t dis_pad_jtag_err:1; + /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; + * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + */ + uint32_t dis_download_manual_encrypt_err:1; + /** usb_drefh_err : RO; bitpos: [22:21]; default: 0; + * Indicates a programming error of USB_DREFH. + */ + uint32_t usb_drefh_err:2; + /** usb_drefl_err : RO; bitpos: [24:23]; default: 0; + * Indicates a programming error of USB_DREFL. + */ + uint32_t usb_drefl_err:2; + /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0; + * Indicates a programming error of USB_EXCHG_PINS. + */ + uint32_t usb_exchg_pins_err:1; + /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0; + * Indicates a programming error of VDD_SPI_AS_GPIO. + */ + uint32_t vdd_spi_as_gpio_err:1; + /** rpt4_reserved0_err_2 : RO; bitpos: [28:27]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved0_err_2:2; + /** rpt4_reserved0_err_1 : RO; bitpos: [29]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved0_err_1:1; + /** rpt4_reserved0_err_0 : RO; bitpos: [31:30]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved0_err_0:2; + }; + uint32_t val; +} efuse_rd_repeat_err0_reg_t; + +/** Type of rd_repeat_err1 register + * Programming error record register 1 of BLOCK0. + */ +typedef union { + struct { + /** rpt4_reserved1_err_0 : RO; bitpos: [15:0]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved1_err_0:16; + /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; + * Indicates a programming error of WDT_DELAY_SEL. + */ + uint32_t wdt_delay_sel_err:2; + /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; + * Indicates a programming error of SPI_BOOT_CRYPT_CNT. + */ + uint32_t spi_boot_crypt_cnt_err:3; + /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + */ + uint32_t secure_boot_key_revoke0_err:1; + /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + */ + uint32_t secure_boot_key_revoke1_err:1; + /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + */ + uint32_t secure_boot_key_revoke2_err:1; + /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; + * Indicates a programming error of KEY_PURPOSE_0. + */ + uint32_t key_purpose_0_err:4; + /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; + * Indicates a programming error of KEY_PURPOSE_1. + */ + uint32_t key_purpose_1_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err1_reg_t; + +/** Type of rd_repeat_err2 register + * Programming error record register 2 of BLOCK0. + */ +typedef union { + struct { + /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; + * Indicates a programming error of KEY_PURPOSE_2. + */ + uint32_t key_purpose_2_err:4; + /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; + * Indicates a programming error of KEY_PURPOSE_3. + */ + uint32_t key_purpose_3_err:4; + /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; + * Indicates a programming error of KEY_PURPOSE_4. + */ + uint32_t key_purpose_4_err:4; + /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; + * Indicates a programming error of KEY_PURPOSE_5. + */ + uint32_t key_purpose_5_err:4; + /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0; + * Indicates a programming error of SEC_DPA_LEVEL. + */ + uint32_t sec_dpa_level_err:2; + /** rpt4_reserved2_err_1 : RO; bitpos: [18]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved2_err_1:1; + /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0; + * Indicates a programming error of CRYPT_DPA_ENABLE. + */ + uint32_t crypt_dpa_enable_err:1; + /** secure_boot_en_err : RO; bitpos: [20]; default: 0; + * Indicates a programming error of SECURE_BOOT_EN. + */ + uint32_t secure_boot_en_err:1; + /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; + * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + */ + uint32_t secure_boot_aggressive_revoke_err:1; + /** rpt4_reserved2_err_0 : RO; bitpos: [27:22]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved2_err_0:6; + /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; + * Indicates a programming error of FLASH_TPUW. + */ + uint32_t flash_tpuw_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err2_reg_t; + +/** Type of rd_repeat_err3 register + * Programming error record register 3 of BLOCK0. + */ +typedef union { + struct { + /** dis_download_mode_err : RO; bitpos: [0]; default: 0; + * Indicates a programming error of DIS_DOWNLOAD_MODE. + */ + uint32_t dis_download_mode_err:1; + /** dis_direct_boot_err : RO; bitpos: [1]; default: 0; + * Indicates a programming error of DIS_DIRECT_BOOT. + */ + uint32_t dis_direct_boot_err:1; + /** usb_print_err : RO; bitpos: [2]; default: 0; + * Indicates a programming error of UART_PRINT_CHANNEL. + */ + uint32_t usb_print_err:1; + /** rpt4_reserved3_err_5 : RO; bitpos: [3]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved3_err_5:1; + /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0; + * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + */ + uint32_t dis_usb_serial_jtag_download_mode_err:1; + /** enable_security_download_err : RO; bitpos: [5]; default: 0; + * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + */ + uint32_t enable_security_download_err:1; + /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; + * Indicates a programming error of UART_PRINT_CONTROL. + */ + uint32_t uart_print_control_err:2; + /** rpt4_reserved3_err_4 : RO; bitpos: [8]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved3_err_4:1; + /** rpt4_reserved3_err_3 : RO; bitpos: [9]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved3_err_3:1; + /** rpt4_reserved3_err_2 : RO; bitpos: [11:10]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved3_err_2:2; + /** rpt4_reserved3_err_1 : RO; bitpos: [12]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved3_err_1:1; + /** force_send_resume_err : RO; bitpos: [13]; default: 0; + * Indicates a programming error of FORCE_SEND_RESUME. + */ + uint32_t force_send_resume_err:1; + /** secure_version_err : RO; bitpos: [29:14]; default: 0; + * Indicates a programming error of SECURE_VERSION. + */ + uint32_t secure_version_err:16; + /** rpt4_reserved3_err_0 : RO; bitpos: [31:30]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved3_err_0:2; + }; + uint32_t val; +} efuse_rd_repeat_err3_reg_t; + +/** Type of rd_repeat_err4 register + * Programming error record register 4 of BLOCK0. + */ +typedef union { + struct { + /** rpt4_reserved4_err_1 : RO; bitpos: [23:0]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved4_err_1:24; + /** rpt4_reserved4_err_0 : RO; bitpos: [31:24]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved4_err_0:8; + }; + uint32_t val; +} efuse_rd_repeat_err4_reg_t; + +/** Type of rd_rs_err0 register + * Programming error record register 0 of BLOCK1-10. + */ +typedef union { + struct { + /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t mac_spi_8m_err_num:3; + /** mac_spi_8m_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t mac_spi_8m_fail:1; + /** sys_part1_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t sys_part1_num:3; + /** sys_part1_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t sys_part1_fail:1; + /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t usr_data_err_num:3; + /** usr_data_fail : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the user data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ + uint32_t usr_data_fail:1; + /** key0_err_num : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key0_err_num:3; + /** key0_fail : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of key0 is reliable 1: Means that programming + * key0 failed and the number of error bytes is over 6. + */ + uint32_t key0_fail:1; + /** key1_err_num : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key1_err_num:3; + /** key1_fail : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of key1 is reliable 1: Means that programming + * key1 failed and the number of error bytes is over 6. + */ + uint32_t key1_fail:1; + /** key2_err_num : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key2_err_num:3; + /** key2_fail : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of key2 is reliable 1: Means that programming + * key2 failed and the number of error bytes is over 6. + */ + uint32_t key2_fail:1; + /** key3_err_num : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key3_err_num:3; + /** key3_fail : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of key3 is reliable 1: Means that programming + * key3 failed and the number of error bytes is over 6. + */ + uint32_t key3_fail:1; + /** key4_err_num : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key4_err_num:3; + /** key4_fail : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of key4 is reliable 1: Means that programming + * key4 failed and the number of error bytes is over 6. + */ + uint32_t key4_fail:1; + }; + uint32_t val; +} efuse_rd_rs_err0_reg_t; + +/** Type of rd_rs_err1 register + * Programming error record register 1 of BLOCK1-10. + */ +typedef union { + struct { + /** key5_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key5_err_num:3; + /** key5_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of key5 is reliable 1: Means that programming + * key5 failed and the number of error bytes is over 6. + */ + uint32_t key5_fail:1; + /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t sys_part2_err_num:3; + /** sys_part2_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t sys_part2_fail:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} efuse_rd_rs_err1_reg_t; + +/** Type of clk register + * eFuse clcok configuration register. + */ +typedef union { + struct { + /** mem_force_pd : R/W; bitpos: [0]; default: 0; + * Set this bit to force eFuse SRAM into power-saving mode. + */ + uint32_t mem_force_pd:1; + /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; + * Set this bit and force to activate clock signal of eFuse SRAM. + */ + uint32_t mem_clk_force_on:1; + /** mem_force_pu : R/W; bitpos: [2]; default: 0; + * Set this bit to force eFuse SRAM into working mode. + */ + uint32_t mem_force_pu:1; + uint32_t reserved_3:13; + /** clk_en : R/W; bitpos: [16]; default: 0; + * Set this bit to force enable eFuse register configuration clock signal. + */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} efuse_clk_reg_t; + +/** Type of conf register + * eFuse operation mode configuraiton register + */ +typedef union { + struct { + /** op_code : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: programming operation command 0x5AA5: read operation command. + */ + uint32_t op_code:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} efuse_conf_reg_t; + +/** Type of status register + * eFuse status register. + */ +typedef union { + struct { + /** state : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ + uint32_t state:4; + /** otp_load_sw : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ + uint32_t otp_load_sw:1; + /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ + uint32_t otp_vddq_c_sync2:1; + /** otp_strobe_sw : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ + uint32_t otp_strobe_sw:1; + /** otp_csb_sw : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ + uint32_t otp_csb_sw:1; + /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ + uint32_t otp_pgenb_sw:1; + /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ + uint32_t otp_vddq_is_sw:1; + /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0; + * Indicates the number of block valid bit. + */ + uint32_t blk0_valid_bit_cnt:10; + uint32_t reserved_20:12; + }; + uint32_t val; +} efuse_status_reg_t; + +/** Type of cmd register + * eFuse command register. + */ +typedef union { + struct { + /** read_cmd : R/W/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ + uint32_t read_cmd:1; + /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ + uint32_t pgm_cmd:1; + /** blk_num : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ + uint32_t blk_num:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} efuse_cmd_reg_t; + +/** Type of int_raw register + * eFuse raw interrupt register. + */ +typedef union { + struct { + /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ + uint32_t read_done_int_raw:1; + /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_raw_reg_t; + +/** Type of int_st register + * eFuse interrupt status register. + */ +typedef union { + struct { + /** read_done_int_st : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ + uint32_t read_done_int_st:1; + /** pgm_done_int_st : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_st_reg_t; + +/** Type of int_ena register + * eFuse interrupt enable register. + */ +typedef union { + struct { + /** read_done_int_ena : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ + uint32_t read_done_int_ena:1; + /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_ena_reg_t; + +/** Type of int_clr register + * eFuse interrupt clear register. + */ +typedef union { + struct { + /** read_done_int_clr : WO; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ + uint32_t read_done_int_clr:1; + /** pgm_done_int_clr : WO; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_clr_reg_t; + +/** Type of dac_conf register + * Controls the eFuse programming voltage. + */ +typedef union { + struct { + /** dac_clk_div : R/W; bitpos: [7:0]; default: 28; + * Controls the division factor of the rising clock of the programming voltage. + */ + uint32_t dac_clk_div:8; + /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; + * Don't care. + */ + uint32_t dac_clk_pad_sel:1; + /** dac_num : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ + uint32_t dac_num:8; + /** oe_clr : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ + uint32_t oe_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_dac_conf_reg_t; + +/** Type of rd_tim_conf register + * Configures read timing parameters. + */ +typedef union { + struct { + /** thr_a : R/W; bitpos: [7:0]; default: 1; + * Configures the read hold time. + */ + uint32_t thr_a:8; + /** trd : R/W; bitpos: [15:8]; default: 2; + * Configures the read time. + */ + uint32_t trd:8; + /** tsur_a : R/W; bitpos: [23:16]; default: 1; + * Configures the read setup time. + */ + uint32_t tsur_a:8; + /** read_init_num : R/W; bitpos: [31:24]; default: 18; + * Configures the waiting time of reading eFuse memory. + */ + uint32_t read_init_num:8; + }; + uint32_t val; +} efuse_rd_tim_conf_reg_t; + +/** Type of wr_tim_conf1 register + * Configurarion register 1 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** tsup_a : R/W; bitpos: [7:0]; default: 1; + * Configures the programming setup time. + */ + uint32_t tsup_a:8; + /** pwr_on_num : R/W; bitpos: [23:8]; default: 12288; + * Configures the power up time for VDDQ. + */ + uint32_t pwr_on_num:16; + /** thp_a : R/W; bitpos: [31:24]; default: 1; + * Configures the programming hold time. + */ + uint32_t thp_a:8; + }; + uint32_t val; +} efuse_wr_tim_conf1_reg_t; + +/** Type of wr_tim_conf2 register + * Configurarion register 2 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** pwr_off_num : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ + uint32_t pwr_off_num:16; + /** tpgm : R/W; bitpos: [31:16]; default: 200; + * Configures the active programming time. + */ + uint32_t tpgm:16; + }; + uint32_t val; +} efuse_wr_tim_conf2_reg_t; + +/** Type of wr_tim_conf0_rs_bypass register + * Configurarion register0 of eFuse programming time parameters and rs bypass + * operation. + */ +typedef union { + struct { + /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; + * Set this bit to bypass reed solomon correction step. + */ + uint32_t bypass_rs_correction:1; + /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; + * Configures block number of programming twice operation. + */ + uint32_t bypass_rs_blk_num:11; + /** update : WT; bitpos: [12]; default: 0; + * Set this bit to update multi-bit register signals. + */ + uint32_t update:1; + /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; + * Configures the inactive programming time. + */ + uint32_t tpgm_inactive:8; + uint32_t reserved_21:11; + }; + uint32_t val; +} efuse_wr_tim_conf0_rs_bypass_reg_t; + +/** Type of date register + * eFuse version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35676928; + * Stores eFuse version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} efuse_date_reg_t; + + +typedef struct efuse_dev_t { + volatile efuse_pgm_data0_reg_t pgm_data0; + volatile efuse_pgm_data1_reg_t pgm_data1; + volatile efuse_pgm_data2_reg_t pgm_data2; + volatile efuse_pgm_data3_reg_t pgm_data3; + volatile efuse_pgm_data4_reg_t pgm_data4; + volatile efuse_pgm_data5_reg_t pgm_data5; + volatile efuse_pgm_data6_reg_t pgm_data6; + volatile efuse_pgm_data7_reg_t pgm_data7; + volatile efuse_pgm_check_value0_reg_t pgm_check_value0; + volatile efuse_pgm_check_value1_reg_t pgm_check_value1; + volatile efuse_pgm_check_value2_reg_t pgm_check_value2; + volatile efuse_rd_wr_dis_reg_t rd_wr_dis; + volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; + volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; + volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; + volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; + volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; + volatile efuse_rd_mac_spi_sys_0_reg_t rd_mac_spi_sys_0; + volatile efuse_rd_mac_spi_sys_1_reg_t rd_mac_spi_sys_1; + volatile efuse_rd_mac_spi_sys_2_reg_t rd_mac_spi_sys_2; + volatile efuse_rd_mac_spi_sys_3_reg_t rd_mac_spi_sys_3; + volatile efuse_rd_mac_spi_sys_4_reg_t rd_mac_spi_sys_4; + volatile efuse_rd_mac_spi_sys_5_reg_t rd_mac_spi_sys_5; + volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; + volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; + volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; + volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; + volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; + volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; + volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; + volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; + volatile efuse_rd_usr_data0_reg_t rd_usr_data0; + volatile efuse_rd_usr_data1_reg_t rd_usr_data1; + volatile efuse_rd_usr_data2_reg_t rd_usr_data2; + volatile efuse_rd_usr_data3_reg_t rd_usr_data3; + volatile efuse_rd_usr_data4_reg_t rd_usr_data4; + volatile efuse_rd_usr_data5_reg_t rd_usr_data5; + volatile efuse_rd_usr_data6_reg_t rd_usr_data6; + volatile efuse_rd_usr_data7_reg_t rd_usr_data7; + volatile efuse_rd_key0_data0_reg_t rd_key0_data0; + volatile efuse_rd_key0_data1_reg_t rd_key0_data1; + volatile efuse_rd_key0_data2_reg_t rd_key0_data2; + volatile efuse_rd_key0_data3_reg_t rd_key0_data3; + volatile efuse_rd_key0_data4_reg_t rd_key0_data4; + volatile efuse_rd_key0_data5_reg_t rd_key0_data5; + volatile efuse_rd_key0_data6_reg_t rd_key0_data6; + volatile efuse_rd_key0_data7_reg_t rd_key0_data7; + volatile efuse_rd_key1_data0_reg_t rd_key1_data0; + volatile efuse_rd_key1_data1_reg_t rd_key1_data1; + volatile efuse_rd_key1_data2_reg_t rd_key1_data2; + volatile efuse_rd_key1_data3_reg_t rd_key1_data3; + volatile efuse_rd_key1_data4_reg_t rd_key1_data4; + volatile efuse_rd_key1_data5_reg_t rd_key1_data5; + volatile efuse_rd_key1_data6_reg_t rd_key1_data6; + volatile efuse_rd_key1_data7_reg_t rd_key1_data7; + volatile efuse_rd_key2_data0_reg_t rd_key2_data0; + volatile efuse_rd_key2_data1_reg_t rd_key2_data1; + volatile efuse_rd_key2_data2_reg_t rd_key2_data2; + volatile efuse_rd_key2_data3_reg_t rd_key2_data3; + volatile efuse_rd_key2_data4_reg_t rd_key2_data4; + volatile efuse_rd_key2_data5_reg_t rd_key2_data5; + volatile efuse_rd_key2_data6_reg_t rd_key2_data6; + volatile efuse_rd_key2_data7_reg_t rd_key2_data7; + volatile efuse_rd_key3_data0_reg_t rd_key3_data0; + volatile efuse_rd_key3_data1_reg_t rd_key3_data1; + volatile efuse_rd_key3_data2_reg_t rd_key3_data2; + volatile efuse_rd_key3_data3_reg_t rd_key3_data3; + volatile efuse_rd_key3_data4_reg_t rd_key3_data4; + volatile efuse_rd_key3_data5_reg_t rd_key3_data5; + volatile efuse_rd_key3_data6_reg_t rd_key3_data6; + volatile efuse_rd_key3_data7_reg_t rd_key3_data7; + volatile efuse_rd_key4_data0_reg_t rd_key4_data0; + volatile efuse_rd_key4_data1_reg_t rd_key4_data1; + volatile efuse_rd_key4_data2_reg_t rd_key4_data2; + volatile efuse_rd_key4_data3_reg_t rd_key4_data3; + volatile efuse_rd_key4_data4_reg_t rd_key4_data4; + volatile efuse_rd_key4_data5_reg_t rd_key4_data5; + volatile efuse_rd_key4_data6_reg_t rd_key4_data6; + volatile efuse_rd_key4_data7_reg_t rd_key4_data7; + volatile efuse_rd_key5_data0_reg_t rd_key5_data0; + volatile efuse_rd_key5_data1_reg_t rd_key5_data1; + volatile efuse_rd_key5_data2_reg_t rd_key5_data2; + volatile efuse_rd_key5_data3_reg_t rd_key5_data3; + volatile efuse_rd_key5_data4_reg_t rd_key5_data4; + volatile efuse_rd_key5_data5_reg_t rd_key5_data5; + volatile efuse_rd_key5_data6_reg_t rd_key5_data6; + volatile efuse_rd_key5_data7_reg_t rd_key5_data7; + volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; + volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; + volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; + volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; + volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; + volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; + volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; + volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; + volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; + volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; + volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; + volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; + uint32_t reserved_18c; + volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; + uint32_t reserved_194[11]; + volatile efuse_rd_rs_err0_reg_t rd_rs_err0; + volatile efuse_rd_rs_err1_reg_t rd_rs_err1; + volatile efuse_clk_reg_t clk; + volatile efuse_conf_reg_t conf; + volatile efuse_status_reg_t status; + volatile efuse_cmd_reg_t cmd; + volatile efuse_int_raw_reg_t int_raw; + volatile efuse_int_st_reg_t int_st; + volatile efuse_int_ena_reg_t int_ena; + volatile efuse_int_clr_reg_t int_clr; + volatile efuse_dac_conf_reg_t dac_conf; + volatile efuse_rd_tim_conf_reg_t rd_tim_conf; + volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; + volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; + volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass; + volatile efuse_date_reg_t date; +} efuse_dev_t; + +extern efuse_dev_t EFUSE; + +#ifndef __cplusplus +_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/ext_mem_defs.h b/components/soc/esp32c6/include/soc/ext_mem_defs.h new file mode 100644 index 0000000000..9768e6cd9c --- /dev/null +++ b/components/soc/esp32c6/include/soc/ext_mem_defs.h @@ -0,0 +1,115 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _CACHE_MEMORY_H_ +#define _CACHE_MEMORY_H_ + +#include "esp_bit_defs.h" +#include "sdkconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*IRAM0 is connected with Cache IBUS0*/ +#define IRAM0_CACHE_ADDRESS_LOW 0x42000000 +#define IRAM0_CACHE_ADDRESS_HIGH(page_size) (IRAM0_CACHE_ADDRESS_LOW + ((page_size) * 128)) // MMU has 256 pages, first 128 for instruction +#define IRAM0_ADDRESS_LOW 0x40000000 +#define IRAM0_ADDRESS_HIGH(page_size) IRAM0_CACHE_ADDRESS_HIGH(page_size) + +/*DRAM0 is connected with Cache DBUS0*/ +#define DRAM0_ADDRESS_LOW 0x42000000 +#define DRAM0_ADDRESS_HIGH 0x43000000 +#define DRAM0_CACHE_ADDRESS_LOW IRAM0_CACHE_ADDRESS_HIGH(CONFIG_MMU_PAGE_SIZE) // ESP32C6-TODO after fixed, also need to remove the sdkconfig.h inclusion +#define DRAM0_CACHE_ADDRESS_HIGH(page_size) (IRAM0_CACHE_ADDRESS_HIGH(page_size) + ((page_size) * 128)) // MMU has 256 pages, second 128 for data +#define DRAM0_CACHE_OPERATION_HIGH(page_size) DRAM0_CACHE_ADDRESS_HIGH(page_size) +#define ESP_CACHE_TEMP_ADDR 0x42000000 + +#define BUS_SIZE(bus_name, page_size) (bus_name##_ADDRESS_HIGH(page_size) - bus_name##_ADDRESS_LOW) +#define ADDRESS_IN_BUS(bus_name, vaddr, page_size) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH(page_size)) + +#define ADDRESS_IN_IRAM0(vaddr, page_size) ADDRESS_IN_BUS(IRAM0, vaddr, page_size) +#define ADDRESS_IN_IRAM0_CACHE(vaddr, page_size) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr, page_size) +#define ADDRESS_IN_DRAM0(vaddr, page_size) ADDRESS_IN_BUS(DRAM0, vaddr, page_size) +#define ADDRESS_IN_DRAM0_CACHE(vaddr, page_size) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr, page_size) + +#define BUS_IRAM0_CACHE_SIZE(page_size) BUS_SIZE(IRAM0_CACHE, page_size) +#define BUS_DRAM0_CACHE_SIZE(page_size) BUS_SIZE(DRAM0_CACHE, page_size) + +#define CACHE_IBUS 0 +#define CACHE_IBUS_MMU_START 0 +#define CACHE_IBUS_MMU_END 0x200 + +#define CACHE_DBUS 1 +#define CACHE_DBUS_MMU_START 0 +#define CACHE_DBUS_MMU_END 0x200 + +//TODO, remove these cache function dependencies +#define CACHE_IROM_MMU_START 0 +#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End() +#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START) + +#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END +#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End() +#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START) + +#define CACHE_DROM_MMU_MAX_END 0x400 + +#define ICACHE_MMU_SIZE 0x200 +#define DCACHE_MMU_SIZE 0x200 + +#define MMU_BUS_START(i) 0 +#define MMU_BUS_SIZE(i) 0x200 + +#define MMU_MSPI_ACCESS_FLASH 0 +#define MMU_MSPI_VALID BIT(9) +#define MMU_MSPI_INVALID 0 +#define MMU_MSPI_SENSITIVE BIT(10) + +#define MMU_ACCESS_FLASH MMU_MSPI_ACCESS_FLASH +#define MMU_ACCESS_SPIRAM MMU_MSPI_ACCESS_SPIRAM +#define MMU_VALID MMU_MSPI_VALID +#define MMU_SENSITIVE MMU_MSPI_SENSITIVE + +// ESP32C6-TODO +#define MMU_INVALID_MASK MMU_MSPI_VALID +#define MMU_INVALID MMU_MSPI_INVALID + + + +#define CACHE_MAX_SYNC_NUM 0x400000 +#define CACHE_MAX_LOCK_NUM 0x8000 + +#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE) +#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t)) + +/** + * MMU entry valid bit mask for mapping value. For an entry: + * valid bit + value bits + * valid bit is BIT(9), so value bits are 0x1ff + */ +#define MMU_VALID_VAL_MASK 0x1ff +/** + * Max MMU available paddr page num. + * `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: + * 256 * 64KB, means MMU can support 16MB paddr at most + */ +#define MMU_MAX_PADDR_PAGE_NUM 256 +//MMU entry num +#define MMU_ENTRY_NUM 256 + +/** + * This is the mask used for mapping. e.g.: + * 0x4200_0000 & MMU_VADDR_MASK + */ +#define MMU_VADDR_MASK(page_size) ((page_size) * MMU_ENTRY_NUM - 1) + +#define CACHE_MEMORY_IBANK0_ADDR 0x40800000 + +#ifdef __cplusplus +} +#endif + +#endif /*_CACHE_MEMORY_H_ */ diff --git a/components/soc/esp32c6/include/soc/extmem_reg.h b/components/soc/esp32c6/include/soc/extmem_reg.h new file mode 100644 index 0000000000..42cea3bdb3 --- /dev/null +++ b/components/soc/esp32c6/include/soc/extmem_reg.h @@ -0,0 +1,951 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: IDF-5797 + +#define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0) + +#define EXTMEM_DCACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x4) +/* EXTMEM_DCACHE_SHUT_DBUS1 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The bit is used to disable core1 dbus access L1-DCache, 0: enable, 1: disable.*/ +#define EXTMEM_DCACHE_SHUT_DBUS1 (BIT(1)) +#define EXTMEM_DCACHE_SHUT_DBUS1_M (BIT(1)) +#define EXTMEM_DCACHE_SHUT_DBUS1_V 0x1 +#define EXTMEM_DCACHE_SHUT_DBUS1_S 1 +/* EXTMEM_DCACHE_SHUT_DBUS0 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The bit is used to disable core0 dbus access L1-DCache, 0: enable, 1: disable.*/ +#define EXTMEM_DCACHE_SHUT_DBUS0 (BIT(0)) +#define EXTMEM_DCACHE_SHUT_DBUS0_M (BIT(0)) +#define EXTMEM_DCACHE_SHUT_DBUS0_V 0x1 +#define EXTMEM_DCACHE_SHUT_DBUS0_S 0 + +#define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x20) +/* EXTMEM_DCACHE_WRAP : R/W ;bitpos:[4] ;default: 1'h0 ; */ +/*description: Set this bit as 1 to enable L1-DCache wrap around mode..*/ +#define EXTMEM_CACHE_FLASH_WRAP_AROUND (BIT(4)) +#define EXTMEM_CACHE_FLASH_WRAP_AROUND_M (BIT(4)) +#define EXTMEM_CACHE_FLASH_WRAP_AROUND_V 0x1 +#define EXTMEM_CACHE_FLASH_WRAP_AROUND_S 4 + +#define EXTMEM_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x24) +/* EXTMEM_DCACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */ +/*description: The bit is used to power L1-DCache tag memory up. 0: follow rtc_lslp, 1: power u +p.*/ +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU (BIT(18)) +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_M (BIT(18)) +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_V 0x1 +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_S 18 +/* EXTMEM_DCACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: The bit is used to power L1-DCache tag memory down. 0: follow rtc_lslp, 1: power + down.*/ +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD (BIT(17)) +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_M (BIT(17)) +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_V 0x1 +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_S 17 +/* EXTMEM_DCACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */ +/*description: The bit is used to close clock gating of L1-DCache tag memory. 1: close gating, + 0: open clock gating..*/ +#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON (BIT(16)) +#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_M (BIT(16)) +#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_V 0x1 +#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_S 16 + +#define EXTMEM_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x28) +/* EXTMEM_DCACHE_DATA_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */ +/*description: The bit is used to power L1-DCache data memory up. 0: follow rtc_lslp, 1: power +up.*/ +#define EXTMEM_DCACHE_DATA_MEM_FORCE_PU (BIT(18)) +#define EXTMEM_DCACHE_DATA_MEM_FORCE_PU_M (BIT(18)) +#define EXTMEM_DCACHE_DATA_MEM_FORCE_PU_V 0x1 +#define EXTMEM_DCACHE_DATA_MEM_FORCE_PU_S 18 +/* EXTMEM_DCACHE_DATA_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: The bit is used to power L1-DCache data memory down. 0: follow rtc_lslp, 1: powe +r down.*/ +#define EXTMEM_DCACHE_DATA_MEM_FORCE_PD (BIT(17)) +#define EXTMEM_DCACHE_DATA_MEM_FORCE_PD_M (BIT(17)) +#define EXTMEM_DCACHE_DATA_MEM_FORCE_PD_V 0x1 +#define EXTMEM_DCACHE_DATA_MEM_FORCE_PD_S 17 +/* EXTMEM_DCACHE_DATA_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */ +/*description: The bit is used to close clock gating of L1-DCache data memory. 1: close gating +, 0: open clock gating..*/ +#define EXTMEM_DCACHE_DATA_MEM_FORCE_ON (BIT(16)) +#define EXTMEM_DCACHE_DATA_MEM_FORCE_ON_M (BIT(16)) +#define EXTMEM_DCACHE_DATA_MEM_FORCE_ON_V 0x1 +#define EXTMEM_DCACHE_DATA_MEM_FORCE_ON_S 16 + +#define EXTMEM_CACHE_FREEZE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x2C) +/* EXTMEM_DCACHE_FREEZE_DONE : RO ;bitpos:[18] ;default: 1'h0 ; */ +/*description: The bit is used to indicate whether freeze operation on L1-DCache is finished or + not. 0: not finished. 1: finished..*/ +#define EXTMEM_DCACHE_FREEZE_DONE (BIT(18)) +#define EXTMEM_DCACHE_FREEZE_DONE_M (BIT(18)) +#define EXTMEM_DCACHE_FREEZE_DONE_V 0x1 +#define EXTMEM_DCACHE_FREEZE_DONE_S 18 +/* EXTMEM_DCACHE_FREEZE_MODE : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-acces +s will not stuck. 1: a miss-access will stuck..*/ +#define EXTMEM_DCACHE_FREEZE_MODE (BIT(17)) +#define EXTMEM_DCACHE_FREEZE_MODE_M (BIT(17)) +#define EXTMEM_DCACHE_FREEZE_MODE_V 0x1 +#define EXTMEM_DCACHE_FREEZE_MODE_S 17 +/* EXTMEM_DCACHE_FREEZE_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: The bit is used to enable freeze operation on L1-DCache. It can be cleared by so +ftware..*/ +#define EXTMEM_DCACHE_FREEZE_EN (BIT(16)) +#define EXTMEM_DCACHE_FREEZE_EN_M (BIT(16)) +#define EXTMEM_DCACHE_FREEZE_EN_V 0x1 +#define EXTMEM_DCACHE_FREEZE_EN_S 16 + +#define EXTMEM_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_EXTMEM_BASE + 0x30) +/* EXTMEM_DCACHE_DATA_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */ +/*description: The bit is used to enable config-bus write L1-DCache data memoryory. 0: disable, + 1: enable..*/ +#define EXTMEM_DCACHE_DATA_MEM_WR_EN (BIT(17)) +#define EXTMEM_DCACHE_DATA_MEM_WR_EN_M (BIT(17)) +#define EXTMEM_DCACHE_DATA_MEM_WR_EN_V 0x1 +#define EXTMEM_DCACHE_DATA_MEM_WR_EN_S 17 +/* EXTMEM_DCACHE_DATA_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */ +/*description: The bit is used to enable config-bus read L1-DCache data memoryory. 0: disable, +1: enable..*/ +#define EXTMEM_DCACHE_DATA_MEM_RD_EN (BIT(16)) +#define EXTMEM_DCACHE_DATA_MEM_RD_EN_M (BIT(16)) +#define EXTMEM_DCACHE_DATA_MEM_RD_EN_V 0x1 +#define EXTMEM_DCACHE_DATA_MEM_RD_EN_S 16 + +#define EXTMEM_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_EXTMEM_BASE + 0x34) +/* EXTMEM_DCACHE_TAG_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */ +/*description: The bit is used to enable config-bus write L1-DCache tag memoryory. 0: disable, +1: enable..*/ +#define EXTMEM_DCACHE_TAG_MEM_WR_EN (BIT(17)) +#define EXTMEM_DCACHE_TAG_MEM_WR_EN_M (BIT(17)) +#define EXTMEM_DCACHE_TAG_MEM_WR_EN_V 0x1 +#define EXTMEM_DCACHE_TAG_MEM_WR_EN_S 17 +/* EXTMEM_DCACHE_TAG_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */ +/*description: The bit is used to enable config-bus read L1-DCache tag memoryory. 0: disable, 1 +: enable..*/ +#define EXTMEM_DCACHE_TAG_MEM_RD_EN (BIT(16)) +#define EXTMEM_DCACHE_TAG_MEM_RD_EN_M (BIT(16)) +#define EXTMEM_DCACHE_TAG_MEM_RD_EN_V 0x1 +#define EXTMEM_DCACHE_TAG_MEM_RD_EN_S 16 + +#define EXTMEM_DCACHE_PRELOCK_CONF_REG (DR_REG_EXTMEM_BASE + 0x78) +/* EXTMEM_DCACHE_PRELOCK_RGID : HRO ;bitpos:[5:2] ;default: 4'h0 ; */ +/*description: The bit is used to set the gid of l1 dcache prelock..*/ +#define EXTMEM_DCACHE_PRELOCK_RGID 0x0000000F +#define EXTMEM_DCACHE_PRELOCK_RGID_M ((EXTMEM_DCACHE_PRELOCK_RGID_V)<<(EXTMEM_DCACHE_PRELOCK_RGID_S)) +#define EXTMEM_DCACHE_PRELOCK_RGID_V 0xF +#define EXTMEM_DCACHE_PRELOCK_RGID_S 2 +/* EXTMEM_DCACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The bit is used to enable the second section of prelock function on L1-DCache..*/ +#define EXTMEM_DCACHE_PRELOCK_SCT1_EN (BIT(1)) +#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_M (BIT(1)) +#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_V 0x1 +#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_S 1 +/* EXTMEM_DCACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The bit is used to enable the first section of prelock function on L1-DCache..*/ +#define EXTMEM_DCACHE_PRELOCK_SCT0_EN (BIT(0)) +#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_M (BIT(0)) +#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_V 0x1 +#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_S 0 + +#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x7C) +/* EXTMEM_DCACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Those bits are used to configure the start virtual address of the first section +of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SC +T0_SIZE_REG.*/ +#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF +#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_M ((EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S)) +#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF +#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S 0 + +#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x80) +/* EXTMEM_DCACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Those bits are used to configure the start virtual address of the second section + of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_S +CT1_SIZE_REG.*/ +#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF +#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_M ((EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S)) +#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFF +#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S 0 + +#define EXTMEM_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x84) +/* EXTMEM_DCACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[29:16] ;default: 14'h3fff ; */ +/*description: Those bits are used to configure the size of the second section of prelock on L1 +-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_ADDR_REG.*/ +#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE 0x00003FFF +#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S)) +#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V 0x3FFF +#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S 16 +/* EXTMEM_DCACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h3fff ; */ +/*description: Those bits are used to configure the size of the first section of prelock on L1- +DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG.*/ +#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE 0x00003FFF +#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S)) +#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V 0x3FFF +#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S 0 + +#define EXTMEM_CACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x88) +/* EXTMEM_CACHE_LOCK_RGID : HRO ;bitpos:[6:3] ;default: 4'h0 ; */ +/*description: The bit is used to set the gid of cache lock/unlock..*/ +#define EXTMEM_CACHE_LOCK_RGID 0x0000000F +#define EXTMEM_CACHE_LOCK_RGID_M ((EXTMEM_CACHE_LOCK_RGID_V)<<(EXTMEM_CACHE_LOCK_RGID_S)) +#define EXTMEM_CACHE_LOCK_RGID_V 0xF +#define EXTMEM_CACHE_LOCK_RGID_S 3 +/* EXTMEM_CACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'h1 ; */ +/*description: The bit is used to indicate whether unlock/lock operation is finished or not. 0: + not finished. 1: finished..*/ +#define EXTMEM_CACHE_LOCK_DONE (BIT(2)) +#define EXTMEM_CACHE_LOCK_DONE_M (BIT(2)) +#define EXTMEM_CACHE_LOCK_DONE_V 0x1 +#define EXTMEM_CACHE_LOCK_DONE_S 2 +/* EXTMEM_CACHE_UNLOCK_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The bit is used to enable unlock operation. It will be cleared by hardware after + unlock operation done. Note that (1) this bit and lock_ena bit are mutually exc +lusive, that is, those bits can not be set to 1 at the same time. (2) unlock ope +ration can be applied on L1-ICache, L1-DCache and L2-Cache..*/ +#define EXTMEM_CACHE_UNLOCK_ENA (BIT(1)) +#define EXTMEM_CACHE_UNLOCK_ENA_M (BIT(1)) +#define EXTMEM_CACHE_UNLOCK_ENA_V 0x1 +#define EXTMEM_CACHE_UNLOCK_ENA_S 1 +/* EXTMEM_CACHE_LOCK_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The bit is used to enable lock operation. It will be cleared by hardware after l +ock operation done. Note that (1) this bit and unlock_ena bit are mutually exclu +sive, that is, those bits can not be set to 1 at the same time. (2) lock operati +on can be applied on LL1-ICache, L1-DCache and L2-Cache..*/ +#define EXTMEM_CACHE_LOCK_ENA (BIT(0)) +#define EXTMEM_CACHE_LOCK_ENA_M (BIT(0)) +#define EXTMEM_CACHE_LOCK_ENA_V 0x1 +#define EXTMEM_CACHE_LOCK_ENA_S 0 + +#define EXTMEM_CACHE_LOCK_MAP_REG (DR_REG_EXTMEM_BASE + 0x8C) +/* EXTMEM_CACHE_LOCK_MAP : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: Those bits are used to indicate which caches in the two-level cache structure wi +ll apply this lock/unlock operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-I +Cache2, [3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache..*/ +#define EXTMEM_CACHE_LOCK_MAP 0x0000003F +#define EXTMEM_CACHE_LOCK_MAP_M ((EXTMEM_CACHE_LOCK_MAP_V)<<(EXTMEM_CACHE_LOCK_MAP_S)) +#define EXTMEM_CACHE_LOCK_MAP_V 0x3F +#define EXTMEM_CACHE_LOCK_MAP_S 0 + +#define EXTMEM_CACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x90) +/* EXTMEM_CACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Those bits are used to configure the start virtual address of the lock/unlock op +eration, which should be used together with CACHE_LOCK_SIZE_REG.*/ +#define EXTMEM_CACHE_LOCK_ADDR 0xFFFFFFFF +#define EXTMEM_CACHE_LOCK_ADDR_M ((EXTMEM_CACHE_LOCK_ADDR_V)<<(EXTMEM_CACHE_LOCK_ADDR_S)) +#define EXTMEM_CACHE_LOCK_ADDR_V 0xFFFFFFFF +#define EXTMEM_CACHE_LOCK_ADDR_S 0 + +#define EXTMEM_CACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x94) +/* EXTMEM_CACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: Those bits are used to configure the size of the lock/unlock operation, which sh +ould be used together with CACHE_LOCK_ADDR_REG.*/ +#define EXTMEM_CACHE_LOCK_SIZE 0x0000FFFF +#define EXTMEM_CACHE_LOCK_SIZE_M ((EXTMEM_CACHE_LOCK_SIZE_V)<<(EXTMEM_CACHE_LOCK_SIZE_S)) +#define EXTMEM_CACHE_LOCK_SIZE_V 0xFFFF +#define EXTMEM_CACHE_LOCK_SIZE_S 0 + +#define EXTMEM_CACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x98) +/* EXTMEM_CACHE_SYNC_RGID : HRO ;bitpos:[8:5] ;default: 4'h0 ; */ +/*description: The bit is used to set the gid of cache sync operation (invalidate, clean, writ +eback, writeback_invalidate).*/ +#define EXTMEM_CACHE_SYNC_RGID 0x0000000F +#define EXTMEM_CACHE_SYNC_RGID_M ((EXTMEM_CACHE_SYNC_RGID_V)<<(EXTMEM_CACHE_SYNC_RGID_S)) +#define EXTMEM_CACHE_SYNC_RGID_V 0xF +#define EXTMEM_CACHE_SYNC_RGID_S 5 +/* EXTMEM_CACHE_SYNC_DONE : RO ;bitpos:[4] ;default: 1'h0 ; */ +/*description: The bit is used to indicate whether sync operation (invalidate, clean, writeback +, writeback_invalidate) is finished or not. 0: not finished. 1: finished..*/ +#define EXTMEM_CACHE_SYNC_DONE (BIT(4)) +#define EXTMEM_CACHE_SYNC_DONE_M (BIT(4)) +#define EXTMEM_CACHE_SYNC_DONE_V 0x1 +#define EXTMEM_CACHE_SYNC_DONE_S 4 +/* EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC ;bitpos:[3] ;default: 1'h0 ; */ +/*description: The bit is used to enable writeback-invalidate operation. It will be cleared by +hardware after writeback-invalidate operation done. Note that this bit and the o +ther sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive +, that is, those bits can not be set to 1 at the same time..*/ +#define EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA (BIT(3)) +#define EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA_M (BIT(3)) +#define EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA_V 0x1 +#define EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA_S 3 +/* EXTMEM_CACHE_WRITEBACK_ENA : R/W/SC ;bitpos:[2] ;default: 1'h0 ; */ +/*description: The bit is used to enable writeback operation. It will be cleared by hardware af +ter writeback operation done. Note that this bit and the other sync-bits (invali +date_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is, +those bits can not be set to 1 at the same time..*/ +#define EXTMEM_CACHE_WRITEBACK_ENA (BIT(2)) +#define EXTMEM_CACHE_WRITEBACK_ENA_M (BIT(2)) +#define EXTMEM_CACHE_WRITEBACK_ENA_V 0x1 +#define EXTMEM_CACHE_WRITEBACK_ENA_S 2 +/* EXTMEM_CACHE_CLEAN_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The bit is used to enable clean operation. It will be cleared by hardware after +clean operation done. Note that this bit and the other sync-bits (invalidate_ena +, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, thos +e bits can not be set to 1 at the same time..*/ +#define EXTMEM_CACHE_CLEAN_ENA (BIT(1)) +#define EXTMEM_CACHE_CLEAN_ENA_M (BIT(1)) +#define EXTMEM_CACHE_CLEAN_ENA_V 0x1 +#define EXTMEM_CACHE_CLEAN_ENA_S 1 +/* EXTMEM_CACHE_INVALIDATE_ENA : R/W/SC ;bitpos:[0] ;default: 1'h1 ; */ +/*description: The bit is used to enable invalidate operation. It will be cleared by hardware a +fter invalidate operation done. Note that this bit and the other sync-bits (clea +n_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, + those bits can not be set to 1 at the same time..*/ +#define EXTMEM_CACHE_INVALIDATE_ENA (BIT(0)) +#define EXTMEM_CACHE_INVALIDATE_ENA_M (BIT(0)) +#define EXTMEM_CACHE_INVALIDATE_ENA_V 0x1 +#define EXTMEM_CACHE_INVALIDATE_ENA_S 0 + +#define EXTMEM_CACHE_SYNC_MAP_REG (DR_REG_EXTMEM_BASE + 0x9C) +/* EXTMEM_CACHE_SYNC_MAP : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ +/*description: Those bits are used to indicate which caches in the two-level cache structure wi +ll apply the sync operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-ICache2, +[3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache..*/ +#define EXTMEM_CACHE_SYNC_MAP 0x0000003F +#define EXTMEM_CACHE_SYNC_MAP_M ((EXTMEM_CACHE_SYNC_MAP_V)<<(EXTMEM_CACHE_SYNC_MAP_S)) +#define EXTMEM_CACHE_SYNC_MAP_V 0x3F +#define EXTMEM_CACHE_SYNC_MAP_S 0 + +#define EXTMEM_CACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0xA0) +/* EXTMEM_CACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Those bits are used to configure the start virtual address of the sync operation +, which should be used together with CACHE_SYNC_SIZE_REG.*/ +#define EXTMEM_CACHE_SYNC_ADDR 0xFFFFFFFF +#define EXTMEM_CACHE_SYNC_ADDR_M ((EXTMEM_CACHE_SYNC_ADDR_V)<<(EXTMEM_CACHE_SYNC_ADDR_S)) +#define EXTMEM_CACHE_SYNC_ADDR_V 0xFFFFFFFF +#define EXTMEM_CACHE_SYNC_ADDR_S 0 + +#define EXTMEM_CACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0xA4) +/* EXTMEM_CACHE_SYNC_SIZE : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: Those bits are used to configure the size of the sync operation, which should be + used together with CACHE_SYNC_ADDR_REG.*/ +#define EXTMEM_CACHE_SYNC_SIZE 0x00FFFFFF +#define EXTMEM_CACHE_SYNC_SIZE_M ((EXTMEM_CACHE_SYNC_SIZE_V)<<(EXTMEM_CACHE_SYNC_SIZE_S)) +#define EXTMEM_CACHE_SYNC_SIZE_V 0xFFFFFF +#define EXTMEM_CACHE_SYNC_SIZE_S 0 + +#define EXTMEM_DCACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0xD8) +/* EXTMEM_DCACHE_PRELOAD_RGID : HRO ;bitpos:[6:3] ;default: 4'h0 ; */ +/*description: The bit is used to set the gid of l1 dcache preload..*/ +#define EXTMEM_DCACHE_PRELOAD_RGID 0x0000000F +#define EXTMEM_DCACHE_PRELOAD_RGID_M ((EXTMEM_DCACHE_PRELOAD_RGID_V)<<(EXTMEM_DCACHE_PRELOAD_RGID_S)) +#define EXTMEM_DCACHE_PRELOAD_RGID_V 0xF +#define EXTMEM_DCACHE_PRELOAD_RGID_S 3 +/* EXTMEM_DCACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: The bit is used to configure the direction of preload operation. 0: ascending, 1 +: descending..*/ +#define EXTMEM_DCACHE_PRELOAD_ORDER (BIT(2)) +#define EXTMEM_DCACHE_PRELOAD_ORDER_M (BIT(2)) +#define EXTMEM_DCACHE_PRELOAD_ORDER_V 0x1 +#define EXTMEM_DCACHE_PRELOAD_ORDER_S 2 +/* EXTMEM_DCACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */ +/*description: The bit is used to indicate whether preload operation is finished or not. 0: not + finished. 1: finished..*/ +#define EXTMEM_DCACHE_PRELOAD_DONE (BIT(1)) +#define EXTMEM_DCACHE_PRELOAD_DONE_M (BIT(1)) +#define EXTMEM_DCACHE_PRELOAD_DONE_V 0x1 +#define EXTMEM_DCACHE_PRELOAD_DONE_S 1 +/* EXTMEM_DCACHE_PRELOAD_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The bit is used to enable preload operation on L1-DCache. It will be cleared by +hardware automatically after preload operation is done..*/ +#define EXTMEM_DCACHE_PRELOAD_ENA (BIT(0)) +#define EXTMEM_DCACHE_PRELOAD_ENA_M (BIT(0)) +#define EXTMEM_DCACHE_PRELOAD_ENA_V 0x1 +#define EXTMEM_DCACHE_PRELOAD_ENA_S 0 + +#define EXTMEM_DCACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0xDC) +/* EXTMEM_DCACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Those bits are used to configure the start virtual address of preload on L1-DCac +he, which should be used together with L1_DCACHE_PRELOAD_SIZE_REG.*/ +#define EXTMEM_DCACHE_PRELOAD_ADDR 0xFFFFFFFF +#define EXTMEM_DCACHE_PRELOAD_ADDR_M ((EXTMEM_DCACHE_PRELOAD_ADDR_V)<<(EXTMEM_DCACHE_PRELOAD_ADDR_S)) +#define EXTMEM_DCACHE_PRELOAD_ADDR_V 0xFFFFFFFF +#define EXTMEM_DCACHE_PRELOAD_ADDR_S 0 + +#define EXTMEM_DCACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0xE0) +/* EXTMEM_DCACHE_PRELOAD_SIZE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: Those bits are used to configure the size of the first section of prelock on L1- +DCache, which should be used together with L1_DCACHE_PRELOAD_ADDR_REG.*/ +#define EXTMEM_DCACHE_PRELOAD_SIZE 0x00003FFF +#define EXTMEM_DCACHE_PRELOAD_SIZE_M ((EXTMEM_DCACHE_PRELOAD_SIZE_V)<<(EXTMEM_DCACHE_PRELOAD_SIZE_S)) +#define EXTMEM_DCACHE_PRELOAD_SIZE_V 0x3FFF +#define EXTMEM_DCACHE_PRELOAD_SIZE_S 0 + +#define EXTMEM_DCACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x134) +/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: The bit is used to enable the second section for autoload operation on L1-DCache +..*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA (BIT(9)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_M (BIT(9)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_V 0x1 +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_S 9 +/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: The bit is used to enable the first section for autoload operation on L1-DCache..*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA (BIT(8)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_M (BIT(8)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_V 0x1 +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_S 8 +/* EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: The field is used to configure trigger mode of autoload operation on L1-DCache. +0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger..*/ +#define EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE 0x00000003 +#define EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_M ((EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_V)<<(EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_S)) +#define EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_V 0x3 +#define EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_S 3 +/* EXTMEM_DCACHE_AUTOLOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: The bit is used to configure the direction of autoload operation on L1-DCache. 0 +: ascending. 1: descending..*/ +#define EXTMEM_DCACHE_AUTOLOAD_ORDER (BIT(2)) +#define EXTMEM_DCACHE_AUTOLOAD_ORDER_M (BIT(2)) +#define EXTMEM_DCACHE_AUTOLOAD_ORDER_V 0x1 +#define EXTMEM_DCACHE_AUTOLOAD_ORDER_S 2 +/* EXTMEM_DCACHE_AUTOLOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */ +/*description: The bit is used to indicate whether autoload operation on L1-DCache is finished +or not. 0: not finished. 1: finished..*/ +#define EXTMEM_DCACHE_AUTOLOAD_DONE (BIT(1)) +#define EXTMEM_DCACHE_AUTOLOAD_DONE_M (BIT(1)) +#define EXTMEM_DCACHE_AUTOLOAD_DONE_V 0x1 +#define EXTMEM_DCACHE_AUTOLOAD_DONE_S 1 +/* EXTMEM_DCACHE_AUTOLOAD_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The bit is used to enable and disable autoload operation on L1-DCache. 1: enabl +e, 0: disable..*/ +#define EXTMEM_DCACHE_AUTOLOAD_ENA (BIT(0)) +#define EXTMEM_DCACHE_AUTOLOAD_ENA_M (BIT(0)) +#define EXTMEM_DCACHE_AUTOLOAD_ENA_V 0x1 +#define EXTMEM_DCACHE_AUTOLOAD_ENA_S 0 + +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x138) +/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Those bits are used to configure the start virtual address of the first section +for autoload operation on L1-DCache. Note that it should be used together with L +1_DCACHE_AUTOLOAD_SCT0_SIZE and L1_DCACHE_AUTOLOAD_SCT0_ENA..*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S 0 + +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x13C) +/* EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */ +/*description: Those bits are used to configure the size of the first section for autoload oper +ation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD +_SCT0_ADDR and L1_DCACHE_AUTOLOAD_SCT0_ENA..*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE 0x0FFFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V 0xFFFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S 0 + +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x140) +/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Those bits are used to configure the start virtual address of the second section + for autoload operation on L1-DCache. Note that it should be used together with +L1_DCACHE_AUTOLOAD_SCT1_SIZE and L1_DCACHE_AUTOLOAD_SCT1_ENA..*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_M ((EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S 0 + +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x144) +/* EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */ +/*description: Those bits are used to configure the size of the second section for autoload ope +ration on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOA +D_SCT1_ADDR and L1_DCACHE_AUTOLOAD_SCT1_ENA..*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE 0x0FFFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V 0xFFFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S 0 + +#define EXTMEM_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x158) +/* EXTMEM_DBUS1_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt of one of counters overflow that occurs in L +1-DCache due to bus1 accesses L1-DCache..*/ +#define EXTMEM_DBUS1_OVF_INT_ENA (BIT(5)) +#define EXTMEM_DBUS1_OVF_INT_ENA_M (BIT(5)) +#define EXTMEM_DBUS1_OVF_INT_ENA_V 0x1 +#define EXTMEM_DBUS1_OVF_INT_ENA_S 5 +/* EXTMEM_DBUS0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt of one of counters overflow that occurs in L +1-DCache due to bus0 accesses L1-DCache..*/ +#define EXTMEM_DBUS0_OVF_INT_ENA (BIT(4)) +#define EXTMEM_DBUS0_OVF_INT_ENA_M (BIT(4)) +#define EXTMEM_DBUS0_OVF_INT_ENA_V 0x1 +#define EXTMEM_DBUS0_OVF_INT_ENA_S 4 + +#define EXTMEM_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x15C) +/* EXTMEM_DBUS1_OVF_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d +ue to bus1 accesses L1-DCache..*/ +#define EXTMEM_DBUS1_OVF_INT_CLR (BIT(5)) +#define EXTMEM_DBUS1_OVF_INT_CLR_M (BIT(5)) +#define EXTMEM_DBUS1_OVF_INT_CLR_V 0x1 +#define EXTMEM_DBUS1_OVF_INT_CLR_S 5 +/* EXTMEM_DBUS0_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d +ue to bus0 accesses L1-DCache..*/ +#define EXTMEM_DBUS0_OVF_INT_CLR (BIT(4)) +#define EXTMEM_DBUS0_OVF_INT_CLR_M (BIT(4)) +#define EXTMEM_DBUS0_OVF_INT_CLR_V 0x1 +#define EXTMEM_DBUS0_OVF_INT_CLR_S 4 + +#define EXTMEM_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x160) +/* EXTMEM_DBUS1_OVF_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach +e due to bus1 accesses L1-DCache..*/ +#define EXTMEM_DBUS1_OVF_INT_RAW (BIT(5)) +#define EXTMEM_DBUS1_OVF_INT_RAW_M (BIT(5)) +#define EXTMEM_DBUS1_OVF_INT_RAW_V 0x1 +#define EXTMEM_DBUS1_OVF_INT_RAW_S 5 +/* EXTMEM_DBUS0_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach +e due to bus0 accesses L1-DCache..*/ +#define EXTMEM_DBUS0_OVF_INT_RAW (BIT(4)) +#define EXTMEM_DBUS0_OVF_INT_RAW_M (BIT(4)) +#define EXTMEM_DBUS0_OVF_INT_RAW_V 0x1 +#define EXTMEM_DBUS0_OVF_INT_RAW_S 4 + +#define EXTMEM_CACHE_ACS_CNT_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x164) +/* EXTMEM_DBUS1_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit indicates the interrupt status of one of counters overflow that occurs i +n L1-DCache due to bus1 accesses L1-DCache..*/ +#define EXTMEM_DBUS1_OVF_INT_ST (BIT(5)) +#define EXTMEM_DBUS1_OVF_INT_ST_M (BIT(5)) +#define EXTMEM_DBUS1_OVF_INT_ST_V 0x1 +#define EXTMEM_DBUS1_OVF_INT_ST_S 5 +/* EXTMEM_DBUS0_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit indicates the interrupt status of one of counters overflow that occurs i +n L1-DCache due to bus0 accesses L1-DCache..*/ +#define EXTMEM_DBUS0_OVF_INT_ST (BIT(4)) +#define EXTMEM_DBUS0_OVF_INT_ST_M (BIT(4)) +#define EXTMEM_DBUS0_OVF_INT_ST_V 0x1 +#define EXTMEM_DBUS0_OVF_INT_ST_S 4 + +#define EXTMEM_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x168) +/* EXTMEM_DCACHE_FAIL_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt of access fail that occurs in L1-DCache due +to cpu accesses L1-DCache..*/ +#define EXTMEM_DCACHE_FAIL_INT_ENA (BIT(4)) +#define EXTMEM_DCACHE_FAIL_INT_ENA_M (BIT(4)) +#define EXTMEM_DCACHE_FAIL_INT_ENA_V 0x1 +#define EXTMEM_DCACHE_FAIL_INT_ENA_S 4 + +#define EXTMEM_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x16C) +/* EXTMEM_DCACHE_FAIL_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt of access fail that occurs in L1-DCache due t +o cpu accesses L1-DCache..*/ +#define EXTMEM_DCACHE_FAIL_INT_CLR (BIT(4)) +#define EXTMEM_DCACHE_FAIL_INT_CLR_M (BIT(4)) +#define EXTMEM_DCACHE_FAIL_INT_CLR_V 0x1 +#define EXTMEM_DCACHE_FAIL_INT_CLR_S 4 + +#define EXTMEM_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x170) +/* EXTMEM_DCACHE_FAIL_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw bit of the interrupt of access fail that occurs in L1-DCache..*/ +#define EXTMEM_DCACHE_FAIL_INT_RAW (BIT(4)) +#define EXTMEM_DCACHE_FAIL_INT_RAW_M (BIT(4)) +#define EXTMEM_DCACHE_FAIL_INT_RAW_V 0x1 +#define EXTMEM_DCACHE_FAIL_INT_RAW_S 4 + +#define EXTMEM_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x174) +/* EXTMEM_DCACHE_FAIL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache d +ue to cpu accesses L1-DCache..*/ +#define EXTMEM_DCACHE_FAIL_INT_ST (BIT(4)) +#define EXTMEM_DCACHE_FAIL_INT_ST_M (BIT(4)) +#define EXTMEM_DCACHE_FAIL_INT_ST_V 0x1 +#define EXTMEM_DCACHE_FAIL_INT_ST_S 4 + +#define EXTMEM_CACHE_ACS_CNT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x178) +/* EXTMEM_DBUS1_CNT_CLR : WT ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The bit is used to clear dbus1 counter in L1-DCache..*/ +#define EXTMEM_DBUS1_CNT_CLR (BIT(21)) +#define EXTMEM_DBUS1_CNT_CLR_M (BIT(21)) +#define EXTMEM_DBUS1_CNT_CLR_V 0x1 +#define EXTMEM_DBUS1_CNT_CLR_S 21 +/* EXTMEM_DBUS0_CNT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The bit is used to clear dbus0 counter in L1-DCache..*/ +#define EXTMEM_DBUS0_CNT_CLR (BIT(20)) +#define EXTMEM_DBUS0_CNT_CLR_M (BIT(20)) +#define EXTMEM_DBUS0_CNT_CLR_V 0x1 +#define EXTMEM_DBUS0_CNT_CLR_S 20 +/* EXTMEM_DBUS1_CNT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to enable dbus1 counter in L1-DCache..*/ +#define EXTMEM_DBUS1_CNT_ENA (BIT(5)) +#define EXTMEM_DBUS1_CNT_ENA_M (BIT(5)) +#define EXTMEM_DBUS1_CNT_ENA_V 0x1 +#define EXTMEM_DBUS1_CNT_ENA_S 5 +/* EXTMEM_DBUS0_CNT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to enable dbus0 counter in L1-DCache..*/ +#define EXTMEM_DBUS0_CNT_ENA (BIT(4)) +#define EXTMEM_DBUS0_CNT_ENA_M (BIT(4)) +#define EXTMEM_DBUS0_CNT_ENA_V 0x1 +#define EXTMEM_DBUS0_CNT_ENA_S 4 + +#define EXTMEM_DBUS0_ACS_HIT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1BC) +/* EXTMEM_DBUS0_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of hits when bus0 accesses L1-DCache..*/ +#define EXTMEM_DBUS0_HIT_CNT 0xFFFFFFFF +#define EXTMEM_DBUS0_HIT_CNT_M ((EXTMEM_DBUS0_HIT_CNT_V)<<(EXTMEM_DBUS0_HIT_CNT_S)) +#define EXTMEM_DBUS0_HIT_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS0_HIT_CNT_S 0 + +#define EXTMEM_DBUS0_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C0) +/* EXTMEM_DBUS0_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of missing when bus0 accesses L1-DCache..*/ +#define EXTMEM_DBUS0_MISS_CNT 0xFFFFFFFF +#define EXTMEM_DBUS0_MISS_CNT_M ((EXTMEM_DBUS0_MISS_CNT_V)<<(EXTMEM_DBUS0_MISS_CNT_S)) +#define EXTMEM_DBUS0_MISS_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS0_MISS_CNT_S 0 + +#define EXTMEM_DBUS0_ACS_CONFLICT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C4) +/* EXTMEM_DBUS0_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of access-conflicts when bus0 accesses L1-DCache +..*/ +#define EXTMEM_DBUS0_CONFLICT_CNT 0xFFFFFFFF +#define EXTMEM_DBUS0_CONFLICT_CNT_M ((EXTMEM_DBUS0_CONFLICT_CNT_V)<<(EXTMEM_DBUS0_CONFLICT_CNT_S)) +#define EXTMEM_DBUS0_CONFLICT_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS0_CONFLICT_CNT_S 0 + +#define EXTMEM_DBUS0_ACS_NXTLVL_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C8) +/* EXTMEM_DBUS0_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of times that L1-DCache accesses L2-Cache due to + bus0 accessing L1-DCache..*/ +#define EXTMEM_DBUS0_NXTLVL_CNT 0xFFFFFFFF +#define EXTMEM_DBUS0_NXTLVL_CNT_M ((EXTMEM_DBUS0_NXTLVL_CNT_V)<<(EXTMEM_DBUS0_NXTLVL_CNT_S)) +#define EXTMEM_DBUS0_NXTLVL_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS0_NXTLVL_CNT_S 0 + +#define EXTMEM_DBUS1_ACS_HIT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1CC) +/* EXTMEM_DBUS1_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of hits when bus1 accesses L1-DCache..*/ +#define EXTMEM_DBUS1_HIT_CNT 0xFFFFFFFF +#define EXTMEM_DBUS1_HIT_CNT_M ((EXTMEM_DBUS1_HIT_CNT_V)<<(EXTMEM_DBUS1_HIT_CNT_S)) +#define EXTMEM_DBUS1_HIT_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS1_HIT_CNT_S 0 + +#define EXTMEM_DBUS1_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D0) +/* EXTMEM_DBUS1_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of missing when bus1 accesses L1-DCache..*/ +#define EXTMEM_DBUS1_MISS_CNT 0xFFFFFFFF +#define EXTMEM_DBUS1_MISS_CNT_M ((EXTMEM_DBUS1_MISS_CNT_V)<<(EXTMEM_DBUS1_MISS_CNT_S)) +#define EXTMEM_DBUS1_MISS_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS1_MISS_CNT_S 0 + +#define EXTMEM_DBUS1_ACS_CONFLICT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D4) +/* EXTMEM_DBUS1_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of access-conflicts when bus1 accesses L1-DCache +..*/ +#define EXTMEM_DBUS1_CONFLICT_CNT 0xFFFFFFFF +#define EXTMEM_DBUS1_CONFLICT_CNT_M ((EXTMEM_DBUS1_CONFLICT_CNT_V)<<(EXTMEM_DBUS1_CONFLICT_CNT_S)) +#define EXTMEM_DBUS1_CONFLICT_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS1_CONFLICT_CNT_S 0 + +#define EXTMEM_DBUS1_ACS_NXTLVL_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D8) +/* EXTMEM_DBUS1_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of times that L1-DCache accesses L2-Cache due to + bus1 accessing L1-DCache..*/ +#define EXTMEM_DBUS1_NXTLVL_CNT 0xFFFFFFFF +#define EXTMEM_DBUS1_NXTLVL_CNT_M ((EXTMEM_DBUS1_NXTLVL_CNT_V)<<(EXTMEM_DBUS1_NXTLVL_CNT_S)) +#define EXTMEM_DBUS1_NXTLVL_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS1_NXTLVL_CNT_S 0 + +#define EXTMEM_ICACHE0_ACS_FAIL_ID_ATTR_REG (DR_REG_EXTMEM_BASE + 0x1FC) +/* EXTMEM_ICACHE0_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: The register records the attribution of fail-access when cache0 accesses L1-ICac +he..*/ +#define EXTMEM_ICACHE0_FAIL_ATTR 0x0000FFFF +#define EXTMEM_ICACHE0_FAIL_ATTR_M ((EXTMEM_ICACHE0_FAIL_ATTR_V)<<(EXTMEM_ICACHE0_FAIL_ATTR_S)) +#define EXTMEM_ICACHE0_FAIL_ATTR_V 0xFFFF +#define EXTMEM_ICACHE0_FAIL_ATTR_S 16 +/* EXTMEM_ICACHE0_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The register records the ID of fail-access when cache0 accesses L1-ICache..*/ +#define EXTMEM_ICACHE0_FAIL_ID 0x0000FFFF +#define EXTMEM_ICACHE0_FAIL_ID_M ((EXTMEM_ICACHE0_FAIL_ID_V)<<(EXTMEM_ICACHE0_FAIL_ID_S)) +#define EXTMEM_ICACHE0_FAIL_ID_V 0xFFFF +#define EXTMEM_ICACHE0_FAIL_ID_S 0 + +#define EXTMEM_ICACHE0_ACS_FAIL_ADDR_REG (DR_REG_EXTMEM_BASE + 0x200) +/* EXTMEM_ICACHE0_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the address of fail-access when cache0 accesses L1-ICache..*/ +#define EXTMEM_ICACHE0_FAIL_ADDR 0xFFFFFFFF +#define EXTMEM_ICACHE0_FAIL_ADDR_M ((EXTMEM_ICACHE0_FAIL_ADDR_V)<<(EXTMEM_ICACHE0_FAIL_ADDR_S)) +#define EXTMEM_ICACHE0_FAIL_ADDR_V 0xFFFFFFFF +#define EXTMEM_ICACHE0_FAIL_ADDR_S 0 + +#define EXTMEM_ICACHE1_ACS_FAIL_ID_ATTR_REG (DR_REG_EXTMEM_BASE + 0x204) +/* EXTMEM_ICACHE1_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: The register records the attribution of fail-access when cache1 accesses L1-ICac +he..*/ +#define EXTMEM_ICACHE1_FAIL_ATTR 0x0000FFFF +#define EXTMEM_ICACHE1_FAIL_ATTR_M ((EXTMEM_ICACHE1_FAIL_ATTR_V)<<(EXTMEM_ICACHE1_FAIL_ATTR_S)) +#define EXTMEM_ICACHE1_FAIL_ATTR_V 0xFFFF +#define EXTMEM_ICACHE1_FAIL_ATTR_S 16 +/* EXTMEM_ICACHE1_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The register records the ID of fail-access when cache1 accesses L1-ICache..*/ +#define EXTMEM_ICACHE1_FAIL_ID 0x0000FFFF +#define EXTMEM_ICACHE1_FAIL_ID_M ((EXTMEM_ICACHE1_FAIL_ID_V)<<(EXTMEM_ICACHE1_FAIL_ID_S)) +#define EXTMEM_ICACHE1_FAIL_ID_V 0xFFFF +#define EXTMEM_ICACHE1_FAIL_ID_S 0 + +#define EXTMEM_ICACHE1_ACS_FAIL_ADDR_REG (DR_REG_EXTMEM_BASE + 0x208) +/* EXTMEM_ICACHE1_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the address of fail-access when cache1 accesses L1-ICache..*/ +#define EXTMEM_ICACHE1_FAIL_ADDR 0xFFFFFFFF +#define EXTMEM_ICACHE1_FAIL_ADDR_M ((EXTMEM_ICACHE1_FAIL_ADDR_V)<<(EXTMEM_ICACHE1_FAIL_ADDR_S)) +#define EXTMEM_ICACHE1_FAIL_ADDR_V 0xFFFFFFFF +#define EXTMEM_ICACHE1_FAIL_ADDR_S 0 + +#define EXTMEM_DCACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_EXTMEM_BASE + 0x21C) +/* EXTMEM_DCACHE_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: The register records the attribution of fail-access when cache accesses L1-DCach +e..*/ +#define EXTMEM_DCACHE_FAIL_ATTR 0x0000FFFF +#define EXTMEM_DCACHE_FAIL_ATTR_M ((EXTMEM_DCACHE_FAIL_ATTR_V)<<(EXTMEM_DCACHE_FAIL_ATTR_S)) +#define EXTMEM_DCACHE_FAIL_ATTR_V 0xFFFF +#define EXTMEM_DCACHE_FAIL_ATTR_S 16 +/* EXTMEM_DCACHE_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The register records the ID of fail-access when cache accesses L1-DCache..*/ +#define EXTMEM_DCACHE_FAIL_ID 0x0000FFFF +#define EXTMEM_DCACHE_FAIL_ID_M ((EXTMEM_DCACHE_FAIL_ID_V)<<(EXTMEM_DCACHE_FAIL_ID_S)) +#define EXTMEM_DCACHE_FAIL_ID_V 0xFFFF +#define EXTMEM_DCACHE_FAIL_ID_S 0 + +#define EXTMEM_DCACHE_ACS_FAIL_ADDR_REG (DR_REG_EXTMEM_BASE + 0x220) +/* EXTMEM_DCACHE_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the address of fail-access when cache accesses L1-DCache..*/ +#define EXTMEM_DCACHE_FAIL_ADDR 0xFFFFFFFF +#define EXTMEM_DCACHE_FAIL_ADDR_M ((EXTMEM_DCACHE_FAIL_ADDR_V)<<(EXTMEM_DCACHE_FAIL_ADDR_S)) +#define EXTMEM_DCACHE_FAIL_ADDR_V 0xFFFFFFFF +#define EXTMEM_DCACHE_FAIL_ADDR_S 0 + +#define EXTMEM_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x224) +/* EXTMEM_CACHE_SYNC_ERR_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt of Cache sync-operation error..*/ +#define EXTMEM_CACHE_SYNC_ERR_INT_ENA (BIT(13)) +#define EXTMEM_CACHE_SYNC_ERR_INT_ENA_M (BIT(13)) +#define EXTMEM_CACHE_SYNC_ERR_INT_ENA_V 0x1 +#define EXTMEM_CACHE_SYNC_ERR_INT_ENA_S 13 +/* EXTMEM_DCACHE_PLD_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt of L1-DCache preload-operation error..*/ +#define EXTMEM_DCACHE_PLD_ERR_INT_ENA (BIT(11)) +#define EXTMEM_DCACHE_PLD_ERR_INT_ENA_M (BIT(11)) +#define EXTMEM_DCACHE_PLD_ERR_INT_ENA_V 0x1 +#define EXTMEM_DCACHE_PLD_ERR_INT_ENA_S 11 +/* EXTMEM_CACHE_SYNC_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt of Cache sync-operation done..*/ +#define EXTMEM_CACHE_SYNC_DONE_INT_ENA (BIT(6)) +#define EXTMEM_CACHE_SYNC_DONE_INT_ENA_M (BIT(6)) +#define EXTMEM_CACHE_SYNC_DONE_INT_ENA_V 0x1 +#define EXTMEM_CACHE_SYNC_DONE_INT_ENA_S 6 +/* EXTMEM_DCACHE_PLD_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt of L1-DCache preload-operation. If preload o +peration is done, interrupt occurs..*/ +#define EXTMEM_DCACHE_PLD_DONE_INT_ENA (BIT(4)) +#define EXTMEM_DCACHE_PLD_DONE_INT_ENA_M (BIT(4)) +#define EXTMEM_DCACHE_PLD_DONE_INT_ENA_V 0x1 +#define EXTMEM_DCACHE_PLD_DONE_INT_ENA_S 4 + +#define EXTMEM_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x228) +/* EXTMEM_CACHE_SYNC_ERR_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt of Cache sync-operation error..*/ +#define EXTMEM_CACHE_SYNC_ERR_INT_CLR (BIT(13)) +#define EXTMEM_CACHE_SYNC_ERR_INT_CLR_M (BIT(13)) +#define EXTMEM_CACHE_SYNC_ERR_INT_CLR_V 0x1 +#define EXTMEM_CACHE_SYNC_ERR_INT_CLR_S 13 +/* EXTMEM_DCACHE_PLD_ERR_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt of L1-DCache preload-operation error..*/ +#define EXTMEM_DCACHE_PLD_ERR_INT_CLR (BIT(11)) +#define EXTMEM_DCACHE_PLD_ERR_INT_CLR_M (BIT(11)) +#define EXTMEM_DCACHE_PLD_ERR_INT_CLR_V 0x1 +#define EXTMEM_DCACHE_PLD_ERR_INT_CLR_S 11 +/* EXTMEM_CACHE_SYNC_DONE_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt that occurs only when Cache sync-operation is + done..*/ +#define EXTMEM_CACHE_SYNC_DONE_INT_CLR (BIT(6)) +#define EXTMEM_CACHE_SYNC_DONE_INT_CLR_M (BIT(6)) +#define EXTMEM_CACHE_SYNC_DONE_INT_CLR_V 0x1 +#define EXTMEM_CACHE_SYNC_DONE_INT_CLR_S 6 +/* EXTMEM_DCACHE_PLD_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt that occurs only when L1-DCache preload-opera +tion is done..*/ +#define EXTMEM_DCACHE_PLD_DONE_INT_CLR (BIT(4)) +#define EXTMEM_DCACHE_PLD_DONE_INT_CLR_M (BIT(4)) +#define EXTMEM_DCACHE_PLD_DONE_INT_CLR_V 0x1 +#define EXTMEM_DCACHE_PLD_DONE_INT_CLR_S 4 + +#define EXTMEM_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x22C) +/* EXTMEM_CACHE_SYNC_ERR_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The raw bit of the interrupt that occurs only when Cache sync-operation error oc +curs..*/ +#define EXTMEM_CACHE_SYNC_ERR_INT_RAW (BIT(13)) +#define EXTMEM_CACHE_SYNC_ERR_INT_RAW_M (BIT(13)) +#define EXTMEM_CACHE_SYNC_ERR_INT_RAW_V 0x1 +#define EXTMEM_CACHE_SYNC_ERR_INT_RAW_S 13 +/* EXTMEM_DCACHE_PLD_ERR_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The raw bit of the interrupt that occurs only when L1-DCache preload-operation e +rror occurs..*/ +#define EXTMEM_DCACHE_PLD_ERR_INT_RAW (BIT(11)) +#define EXTMEM_DCACHE_PLD_ERR_INT_RAW_M (BIT(11)) +#define EXTMEM_DCACHE_PLD_ERR_INT_RAW_V 0x1 +#define EXTMEM_DCACHE_PLD_ERR_INT_RAW_S 11 +/* EXTMEM_CACHE_SYNC_DONE_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw bit of the interrupt that occurs only when Cache sync-operation is done..*/ +#define EXTMEM_CACHE_SYNC_DONE_INT_RAW (BIT(6)) +#define EXTMEM_CACHE_SYNC_DONE_INT_RAW_M (BIT(6)) +#define EXTMEM_CACHE_SYNC_DONE_INT_RAW_V 0x1 +#define EXTMEM_CACHE_SYNC_DONE_INT_RAW_S 6 +/* EXTMEM_DCACHE_PLD_DONE_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw bit of the interrupt that occurs only when L1-DCache preload-operation i +s done..*/ +#define EXTMEM_DCACHE_PLD_DONE_INT_RAW (BIT(4)) +#define EXTMEM_DCACHE_PLD_DONE_INT_RAW_M (BIT(4)) +#define EXTMEM_DCACHE_PLD_DONE_INT_RAW_V 0x1 +#define EXTMEM_DCACHE_PLD_DONE_INT_RAW_S 4 + +#define EXTMEM_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x230) +/* EXTMEM_CACHE_SYNC_ERR_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The bit indicates the status of the interrupt of Cache sync-operation error..*/ +#define EXTMEM_CACHE_SYNC_ERR_INT_ST (BIT(13)) +#define EXTMEM_CACHE_SYNC_ERR_INT_ST_M (BIT(13)) +#define EXTMEM_CACHE_SYNC_ERR_INT_ST_V 0x1 +#define EXTMEM_CACHE_SYNC_ERR_INT_ST_S 13 +/* EXTMEM_DCACHE_PLD_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The bit indicates the status of the interrupt of L1-DCache preload-operation err +or..*/ +#define EXTMEM_DCACHE_PLD_ERR_INT_ST (BIT(11)) +#define EXTMEM_DCACHE_PLD_ERR_INT_ST_M (BIT(11)) +#define EXTMEM_DCACHE_PLD_ERR_INT_ST_V 0x1 +#define EXTMEM_DCACHE_PLD_ERR_INT_ST_S 11 +/* EXTMEM_CACHE_SYNC_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The bit indicates the status of the interrupt that occurs only when Cache sync-o +peration is done..*/ +#define EXTMEM_CACHE_SYNC_DONE_INT_ST (BIT(6)) +#define EXTMEM_CACHE_SYNC_DONE_INT_ST_M (BIT(6)) +#define EXTMEM_CACHE_SYNC_DONE_INT_ST_V 0x1 +#define EXTMEM_CACHE_SYNC_DONE_INT_ST_S 6 +/* EXTMEM_DCACHE_PLD_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit indicates the status of the interrupt that occurs only when L1-DCache pr +eload-operation is done..*/ +#define EXTMEM_DCACHE_PLD_DONE_INT_ST (BIT(4)) +#define EXTMEM_DCACHE_PLD_DONE_INT_ST_M (BIT(4)) +#define EXTMEM_DCACHE_PLD_DONE_INT_ST_V 0x1 +#define EXTMEM_DCACHE_PLD_DONE_INT_ST_S 4 + +#define EXTMEM_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_EXTMEM_BASE + 0x234) +/* EXTMEM_CACHE_SYNC_ERR_CODE : RO ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: The values 0-2 are available which means sync map, command conflict and size are + error in Cache System..*/ +#define EXTMEM_CACHE_SYNC_ERR_CODE 0x00000003 +#define EXTMEM_CACHE_SYNC_ERR_CODE_M ((EXTMEM_CACHE_SYNC_ERR_CODE_V)<<(EXTMEM_CACHE_SYNC_ERR_CODE_S)) +#define EXTMEM_CACHE_SYNC_ERR_CODE_V 0x3 +#define EXTMEM_CACHE_SYNC_ERR_CODE_S 12 +/* EXTMEM_DCACHE_PLD_ERR_CODE : RO ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: The value 2 is Only available which means preload size is error in L1-DCache..*/ +#define EXTMEM_DCACHE_PLD_ERR_CODE 0x00000003 +#define EXTMEM_DCACHE_PLD_ERR_CODE_M ((EXTMEM_DCACHE_PLD_ERR_CODE_V)<<(EXTMEM_DCACHE_PLD_ERR_CODE_S)) +#define EXTMEM_DCACHE_PLD_ERR_CODE_V 0x3 +#define EXTMEM_DCACHE_PLD_ERR_CODE_S 8 + +#define EXTMEM_CACHE_SYNC_RST_CTRL_REG (DR_REG_EXTMEM_BASE + 0x238) +/* EXTMEM_DCACHE_SYNC_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: set this bit to reset sync-logic inside L1-DCache. Recommend that this should on +ly be used to initialize sync-logic when some fatal error of sync-logic occurs..*/ +#define EXTMEM_DCACHE_SYNC_RST (BIT(4)) +#define EXTMEM_DCACHE_SYNC_RST_M (BIT(4)) +#define EXTMEM_DCACHE_SYNC_RST_V 0x1 +#define EXTMEM_DCACHE_SYNC_RST_S 4 + +#define EXTMEM_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_EXTMEM_BASE + 0x23C) +/* EXTMEM_DCACHE_PLD_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: set this bit to reset preload-logic inside L1-DCache. Recommend that this should + only be used to initialize preload-logic when some fatal error of preload-logic + occurs..*/ +#define EXTMEM_DCACHE_PLD_RST (BIT(4)) +#define EXTMEM_DCACHE_PLD_RST_M (BIT(4)) +#define EXTMEM_DCACHE_PLD_RST_V 0x1 +#define EXTMEM_DCACHE_PLD_RST_S 4 + +#define EXTMEM_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_EXTMEM_BASE + 0x240) +/* EXTMEM_DCACHE_ALD_BUF_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: set this bit to clear autoload-buffer inside L1-DCache. If this bit is active, a +utoload will not work in L1-DCache. This bit should not be active when autoload +works in L1-DCache..*/ +#define EXTMEM_DCACHE_ALD_BUF_CLR (BIT(4)) +#define EXTMEM_DCACHE_ALD_BUF_CLR_M (BIT(4)) +#define EXTMEM_DCACHE_ALD_BUF_CLR_V 0x1 +#define EXTMEM_DCACHE_ALD_BUF_CLR_S 4 + +#define EXTMEM_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_EXTMEM_BASE + 0x244) +/* EXTMEM_DCACHE_UNALLOC_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to clear the unallocate request buffer of l1 dcache where the un +allocate request is responsed but not completed..*/ +#define EXTMEM_DCACHE_UNALLOC_CLR (BIT(4)) +#define EXTMEM_DCACHE_UNALLOC_CLR_M (BIT(4)) +#define EXTMEM_DCACHE_UNALLOC_CLR_V 0x1 +#define EXTMEM_DCACHE_UNALLOC_CLR_S 4 + +#define EXTMEM_CACHE_OBJECT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x248) +/* EXTMEM_DCACHE_MEM_OBJECT : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to set L1-DCache data memory as object. This bit should be onehot w +ith the others fields inside this register..*/ +#define EXTMEM_DCACHE_MEM_OBJECT (BIT(10)) +#define EXTMEM_DCACHE_MEM_OBJECT_M (BIT(10)) +#define EXTMEM_DCACHE_MEM_OBJECT_V 0x1 +#define EXTMEM_DCACHE_MEM_OBJECT_S 10 +/* EXTMEM_DCACHE_TAG_OBJECT : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to set L1-DCache tag memory as object. This bit should be onehot wi +th the others fields inside this register..*/ +#define EXTMEM_DCACHE_TAG_OBJECT (BIT(4)) +#define EXTMEM_DCACHE_TAG_OBJECT_M (BIT(4)) +#define EXTMEM_DCACHE_TAG_OBJECT_V 0x1 +#define EXTMEM_DCACHE_TAG_OBJECT_S 4 + +#define EXTMEM_CACHE_WAY_OBJECT_REG (DR_REG_EXTMEM_BASE + 0x24C) +/* EXTMEM_CACHE_WAY_OBJECT : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: Set this bits to select which way of the tag-object will be accessed. 0: way0, 1 +: way1, 2: way2, 3: way3, ?, 7: way7..*/ +#define EXTMEM_CACHE_WAY_OBJECT 0x00000007 +#define EXTMEM_CACHE_WAY_OBJECT_M ((EXTMEM_CACHE_WAY_OBJECT_V)<<(EXTMEM_CACHE_WAY_OBJECT_S)) +#define EXTMEM_CACHE_WAY_OBJECT_V 0x7 +#define EXTMEM_CACHE_WAY_OBJECT_S 0 + +#define EXTMEM_CACHE_VADDR_REG (DR_REG_EXTMEM_BASE + 0x250) +/* EXTMEM_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h40000000 ; */ +/*description: Those bits stores the virtual address which will decide where inside the specifi +ed tag memory object will be accessed..*/ +#define EXTMEM_CACHE_VADDR 0xFFFFFFFF +#define EXTMEM_CACHE_VADDR_M ((EXTMEM_CACHE_VADDR_V)<<(EXTMEM_CACHE_VADDR_S)) +#define EXTMEM_CACHE_VADDR_V 0xFFFFFFFF +#define EXTMEM_CACHE_VADDR_S 0 + +#define EXTMEM_CACHE_DEBUG_BUS_REG (DR_REG_EXTMEM_BASE + 0x254) +/* EXTMEM_CACHE_DEBUG_BUS : R/W ;bitpos:[31:0] ;default: 32'h254 ; */ +/*description: This is a constant place where we can write data to or read data from the tag/da +ta memory on the specified cache..*/ +#define EXTMEM_CACHE_DEBUG_BUS 0xFFFFFFFF +#define EXTMEM_CACHE_DEBUG_BUS_M ((EXTMEM_CACHE_DEBUG_BUS_V)<<(EXTMEM_CACHE_DEBUG_BUS_S)) +#define EXTMEM_CACHE_DEBUG_BUS_V 0xFFFFFFFF +#define EXTMEM_CACHE_DEBUG_BUS_S 0 + +#define EXTMEM_DATE_REG (DR_REG_EXTMEM_BASE + 0x3FC) +/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2202080 ; */ +/*description: version control register. Note that this default value stored is the latest date + when the hardware logic was updated..*/ +#define EXTMEM_DATE 0x0FFFFFFF +#define EXTMEM_DATE_M ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S)) +#define EXTMEM_DATE_V 0xFFFFFFF +#define EXTMEM_DATE_S 0 + + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/extmem_struct.h b/components/soc/esp32c6/include/soc/extmem_struct.h new file mode 100644 index 0000000000..d309e09235 --- /dev/null +++ b/components/soc/esp32c6/include/soc/extmem_struct.h @@ -0,0 +1,5747 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Control and configuration registers */ +/** Type of l1_icache_ctrl register + * L1 instruction Cache(L1-ICache) control register + */ +typedef union { + struct { + /** l1_icache_shut_ibus0 : HRO; bitpos: [0]; default: 0; + * The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable + */ + uint32_t l1_icache_shut_ibus0:1; + /** l1_icache_shut_ibus1 : HRO; bitpos: [1]; default: 0; + * The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable + */ + uint32_t l1_icache_shut_ibus1:1; + /** l1_icache_shut_ibus2 : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache_shut_ibus2:1; + /** l1_icache_shut_ibus3 : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache_shut_ibus3:1; + /** l1_icache_undef_op : HRO; bitpos: [7:4]; default: 0; + * Reserved + */ + uint32_t l1_icache_undef_op:4; + uint32_t reserved_8:24; + }; + uint32_t val; +} extmem_l1_icache_ctrl_reg_t; + +/** Type of l1_cache_ctrl register + * L1 data Cache(L1-Cache) control register + */ +typedef union { + struct { + /** l1_cache_shut_bus0 : R/W; bitpos: [0]; default: 0; + * The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable + */ + uint32_t l1_cache_shut_bus0:1; + /** l1_cache_shut_bus1 : R/W; bitpos: [1]; default: 0; + * The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable + */ + uint32_t l1_cache_shut_bus1:1; + /** l1_cache_shut_dbus2 : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_cache_shut_dbus2:1; + /** l1_cache_shut_dbus3 : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_cache_shut_dbus3:1; + /** l1_cache_shut_dma : HRO; bitpos: [4]; default: 0; + * The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable + */ + uint32_t l1_cache_shut_dma:1; + uint32_t reserved_5:3; + /** l1_cache_undef_op : R/W; bitpos: [11:8]; default: 0; + * Reserved + */ + uint32_t l1_cache_undef_op:4; + uint32_t reserved_12:20; + }; + uint32_t val; +} extmem_l1_cache_ctrl_reg_t; + +/** Type of l2_cache_ctrl register + * L2 Cache(L2-Cache) control register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l2_cache_shut_dma : HRO; bitpos: [4]; default: 0; + * The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable + */ + uint32_t l2_cache_shut_dma:1; + /** l2_cache_undef_op : HRO; bitpos: [8:5]; default: 0; + * Reserved + */ + uint32_t l2_cache_undef_op:4; + uint32_t reserved_9:23; + }; + uint32_t val; +} extmem_l2_cache_ctrl_reg_t; + + +/** Group: Bypass Cache Control and configuration registers */ +/** Type of l1_bypass_cache_conf register + * Bypass Cache configure register + */ +typedef union { + struct { + /** bypass_l1_icache0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass. + */ + uint32_t bypass_l1_icache0_en:1; + /** bypass_l1_icache1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass. + */ + uint32_t bypass_l1_icache1_en:1; + /** bypass_l1_icache2_en : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t bypass_l1_icache2_en:1; + /** bypass_l1_icache3_en : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t bypass_l1_icache3_en:1; + /** bypass_l1_dcache_en : HRO; bitpos: [4]; default: 0; + * The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass. + */ + uint32_t bypass_l1_dcache_en:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} extmem_l1_bypass_cache_conf_reg_t; + +/** Type of l2_bypass_cache_conf register + * Bypass Cache configure register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** bypass_l2_cache_en : HRO; bitpos: [5]; default: 0; + * The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass. + */ + uint32_t bypass_l2_cache_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_bypass_cache_conf_reg_t; + + +/** Group: Cache Atomic Control and configuration registers */ +/** Type of l1_cache_atomic_conf register + * L1 Cache atomic feature configure register + */ +typedef union { + struct { + /** l1_cache_atomic_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable atomic feature on L1-Cache when multiple cores access + * L1-Cache. 1: disable, 1: enable. + */ + uint32_t l1_cache_atomic_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} extmem_l1_cache_atomic_conf_reg_t; + + +/** Group: Cache Mode Control and configuration registers */ +/** Type of l1_icache_cachesize_conf register + * L1 instruction Cache CacheSize mode configure register + */ +typedef union { + struct { + /** l1_icache_cachesize_1k : HRO; bitpos: [0]; default: 0; + * The field is used to configure cachesize of L1-ICache as 1k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_1k:1; + /** l1_icache_cachesize_2k : HRO; bitpos: [1]; default: 0; + * The field is used to configure cachesize of L1-ICache as 2k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_2k:1; + /** l1_icache_cachesize_4k : HRO; bitpos: [2]; default: 0; + * The field is used to configure cachesize of L1-ICache as 4k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_4k:1; + /** l1_icache_cachesize_8k : HRO; bitpos: [3]; default: 0; + * The field is used to configure cachesize of L1-ICache as 8k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_8k:1; + /** l1_icache_cachesize_16k : HRO; bitpos: [4]; default: 0; + * The field is used to configure cachesize of L1-ICache as 16k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_16k:1; + /** l1_icache_cachesize_32k : HRO; bitpos: [5]; default: 0; + * The field is used to configure cachesize of L1-ICache as 32k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_32k:1; + /** l1_icache_cachesize_64k : HRO; bitpos: [6]; default: 0; + * The field is used to configure cachesize of L1-ICache as 64k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_64k:1; + /** l1_icache_cachesize_128k : HRO; bitpos: [7]; default: 0; + * The field is used to configure cachesize of L1-ICache as 128k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_128k:1; + /** l1_icache_cachesize_256k : HRO; bitpos: [8]; default: 0; + * The field is used to configure cachesize of L1-ICache as 256k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_256k:1; + /** l1_icache_cachesize_512k : HRO; bitpos: [9]; default: 0; + * The field is used to configure cachesize of L1-ICache as 512k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_512k:1; + /** l1_icache_cachesize_1024k : HRO; bitpos: [10]; default: 0; + * The field is used to configure cachesize of L1-ICache as 1024k bytes. This field + * and all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_1024k:1; + /** l1_icache_cachesize_2048k : HRO; bitpos: [11]; default: 0; + * The field is used to configure cachesize of L1-ICache as 2048k bytes. This field + * and all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_2048k:1; + /** l1_icache_cachesize_4096k : HRO; bitpos: [12]; default: 0; + * The field is used to configure cachesize of L1-ICache as 4096k bytes. This field + * and all other fields within this register is onehot. + */ + uint32_t l1_icache_cachesize_4096k:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} extmem_l1_icache_cachesize_conf_reg_t; + +/** Type of l1_icache_blocksize_conf register + * L1 instruction Cache BlockSize mode configure register + */ +typedef union { + struct { + /** l1_icache_blocksize_8 : HRO; bitpos: [0]; default: 0; + * The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_8:1; + /** l1_icache_blocksize_16 : HRO; bitpos: [1]; default: 0; + * The field is used to configureblocksize of L1-ICache as 16 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_16:1; + /** l1_icache_blocksize_32 : HRO; bitpos: [2]; default: 0; + * The field is used to configureblocksize of L1-ICache as 32 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_32:1; + /** l1_icache_blocksize_64 : HRO; bitpos: [3]; default: 0; + * The field is used to configureblocksize of L1-ICache as 64 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_64:1; + /** l1_icache_blocksize_128 : HRO; bitpos: [4]; default: 0; + * The field is used to configureblocksize of L1-ICache as 128 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_128:1; + /** l1_icache_blocksize_256 : HRO; bitpos: [5]; default: 0; + * The field is used to configureblocksize of L1-ICache as 256 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_icache_blocksize_256:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l1_icache_blocksize_conf_reg_t; + +/** Type of l1_cache_cachesize_conf register + * L1 data Cache CacheSize mode configure register + */ +typedef union { + struct { + /** l1_cache_cachesize_1k : HRO; bitpos: [0]; default: 0; + * The field is used to configure cachesize of L1-Cache as 1k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_1k:1; + /** l1_cache_cachesize_2k : HRO; bitpos: [1]; default: 0; + * The field is used to configure cachesize of L1-Cache as 2k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_2k:1; + /** l1_cache_cachesize_4k : HRO; bitpos: [2]; default: 0; + * The field is used to configure cachesize of L1-Cache as 4k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_4k:1; + /** l1_cache_cachesize_8k : HRO; bitpos: [3]; default: 0; + * The field is used to configure cachesize of L1-Cache as 8k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_8k:1; + /** l1_cache_cachesize_16k : HRO; bitpos: [4]; default: 0; + * The field is used to configure cachesize of L1-Cache as 16k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_16k:1; + /** l1_cache_cachesize_32k : HRO; bitpos: [5]; default: 1; + * The field is used to configure cachesize of L1-Cache as 32k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_32k:1; + /** l1_cache_cachesize_64k : HRO; bitpos: [6]; default: 0; + * The field is used to configure cachesize of L1-Cache as 64k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_64k:1; + /** l1_cache_cachesize_128k : HRO; bitpos: [7]; default: 0; + * The field is used to configure cachesize of L1-Cache as 128k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_128k:1; + /** l1_cache_cachesize_256k : HRO; bitpos: [8]; default: 0; + * The field is used to configure cachesize of L1-Cache as 256k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_256k:1; + /** l1_cache_cachesize_512k : HRO; bitpos: [9]; default: 0; + * The field is used to configure cachesize of L1-Cache as 512k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_512k:1; + /** l1_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0; + * The field is used to configure cachesize of L1-Cache as 1024k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_1024k:1; + /** l1_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0; + * The field is used to configure cachesize of L1-Cache as 2048k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_2048k:1; + /** l1_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0; + * The field is used to configure cachesize of L1-Cache as 4096k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_cachesize_4096k:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} extmem_l1_cache_cachesize_conf_reg_t; + +/** Type of l1_cache_blocksize_conf register + * L1 data Cache BlockSize mode configure register + */ +typedef union { + struct { + /** l1_cache_blocksize_8 : HRO; bitpos: [0]; default: 0; + * The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_8:1; + /** l1_cache_blocksize_16 : HRO; bitpos: [1]; default: 0; + * The field is used to configureblocksize of L1-DCache as 16 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_16:1; + /** l1_cache_blocksize_32 : HRO; bitpos: [2]; default: 1; + * The field is used to configureblocksize of L1-DCache as 32 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_32:1; + /** l1_cache_blocksize_64 : HRO; bitpos: [3]; default: 0; + * The field is used to configureblocksize of L1-DCache as 64 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_64:1; + /** l1_cache_blocksize_128 : HRO; bitpos: [4]; default: 0; + * The field is used to configureblocksize of L1-DCache as 128 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_128:1; + /** l1_cache_blocksize_256 : HRO; bitpos: [5]; default: 0; + * The field is used to configureblocksize of L1-DCache as 256 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l1_cache_blocksize_256:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l1_cache_blocksize_conf_reg_t; + +/** Type of l2_cache_cachesize_conf register + * L2 Cache CacheSize mode configure register + */ +typedef union { + struct { + /** l2_cache_cachesize_1k : HRO; bitpos: [0]; default: 0; + * The field is used to configure cachesize of L2-Cache as 1k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_1k:1; + /** l2_cache_cachesize_2k : HRO; bitpos: [1]; default: 0; + * The field is used to configure cachesize of L2-Cache as 2k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_2k:1; + /** l2_cache_cachesize_4k : HRO; bitpos: [2]; default: 0; + * The field is used to configure cachesize of L2-Cache as 4k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_4k:1; + /** l2_cache_cachesize_8k : HRO; bitpos: [3]; default: 0; + * The field is used to configure cachesize of L2-Cache as 8k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_8k:1; + /** l2_cache_cachesize_16k : HRO; bitpos: [4]; default: 0; + * The field is used to configure cachesize of L2-Cache as 16k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_16k:1; + /** l2_cache_cachesize_32k : HRO; bitpos: [5]; default: 0; + * The field is used to configure cachesize of L2-Cache as 32k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_32k:1; + /** l2_cache_cachesize_64k : HRO; bitpos: [6]; default: 0; + * The field is used to configure cachesize of L2-Cache as 64k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_64k:1; + /** l2_cache_cachesize_128k : HRO; bitpos: [7]; default: 0; + * The field is used to configure cachesize of L2-Cache as 128k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_128k:1; + /** l2_cache_cachesize_256k : HRO; bitpos: [8]; default: 0; + * The field is used to configure cachesize of L2-Cache as 256k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_256k:1; + /** l2_cache_cachesize_512k : HRO; bitpos: [9]; default: 0; + * The field is used to configure cachesize of L2-Cache as 512k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_512k:1; + /** l2_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0; + * The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_1024k:1; + /** l2_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0; + * The field is used to configure cachesize of L2-Cache as 2048k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_2048k:1; + /** l2_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0; + * The field is used to configure cachesize of L2-Cache as 4096k bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_cachesize_4096k:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} extmem_l2_cache_cachesize_conf_reg_t; + +/** Type of l2_cache_blocksize_conf register + * L2 Cache BlockSize mode configure register + */ +typedef union { + struct { + /** l2_cache_blocksize_8 : HRO; bitpos: [0]; default: 0; + * The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_8:1; + /** l2_cache_blocksize_16 : HRO; bitpos: [1]; default: 0; + * The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_16:1; + /** l2_cache_blocksize_32 : HRO; bitpos: [2]; default: 0; + * The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_32:1; + /** l2_cache_blocksize_64 : HRO; bitpos: [3]; default: 0; + * The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all + * other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_64:1; + /** l2_cache_blocksize_128 : HRO; bitpos: [4]; default: 0; + * The field is used to configureblocksize of L2-Cache as 128 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_128:1; + /** l2_cache_blocksize_256 : HRO; bitpos: [5]; default: 0; + * The field is used to configureblocksize of L2-Cache as 256 bytes. This field and + * all other fields within this register is onehot. + */ + uint32_t l2_cache_blocksize_256:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_cache_blocksize_conf_reg_t; + + +/** Group: Wrap Mode Control and configuration registers */ +/** Type of l1_cache_wrap_around_ctrl register + * Cache wrap around control register + */ +typedef union { + struct { + /** l1_icache0_wrap : HRO; bitpos: [0]; default: 0; + * Set this bit as 1 to enable L1-ICache0 wrap around mode. + */ + uint32_t l1_icache0_wrap:1; + /** l1_icache1_wrap : HRO; bitpos: [1]; default: 0; + * Set this bit as 1 to enable L1-ICache1 wrap around mode. + */ + uint32_t l1_icache1_wrap:1; + /** l1_icache2_wrap : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_wrap:1; + /** l1_icache3_wrap : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_wrap:1; + /** l1_cache_wrap : R/W; bitpos: [4]; default: 0; + * Set this bit as 1 to enable L1-DCache wrap around mode. + */ + uint32_t l1_cache_wrap:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} extmem_l1_cache_wrap_around_ctrl_reg_t; + +/** Type of l2_cache_wrap_around_ctrl register + * Cache wrap around control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_wrap : HRO; bitpos: [5]; default: 0; + * Set this bit as 1 to enable L2-Cache wrap around mode. + */ + uint32_t l2_cache_wrap:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_cache_wrap_around_ctrl_reg_t; + + +/** Group: Cache Tag Memory Power Control registers */ +/** Type of l1_cache_tag_mem_power_ctrl register + * Cache tag memory power control register + */ +typedef union { + struct { + /** l1_icache0_tag_mem_force_on : HRO; bitpos: [0]; default: 1; + * The bit is used to close clock gating of L1-ICache0 tag memory. 1: close gating, + * 0: open clock gating. + */ + uint32_t l1_icache0_tag_mem_force_on:1; + /** l1_icache0_tag_mem_force_pd : HRO; bitpos: [1]; default: 0; + * The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power + * down + */ + uint32_t l1_icache0_tag_mem_force_pd:1; + /** l1_icache0_tag_mem_force_pu : HRO; bitpos: [2]; default: 1; + * The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l1_icache0_tag_mem_force_pu:1; + uint32_t reserved_3:1; + /** l1_icache1_tag_mem_force_on : HRO; bitpos: [4]; default: 1; + * The bit is used to close clock gating of L1-ICache1 tag memory. 1: close gating, + * 0: open clock gating. + */ + uint32_t l1_icache1_tag_mem_force_on:1; + /** l1_icache1_tag_mem_force_pd : HRO; bitpos: [5]; default: 0; + * The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power + * down + */ + uint32_t l1_icache1_tag_mem_force_pd:1; + /** l1_icache1_tag_mem_force_pu : HRO; bitpos: [6]; default: 1; + * The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l1_icache1_tag_mem_force_pu:1; + uint32_t reserved_7:1; + /** l1_icache2_tag_mem_force_on : HRO; bitpos: [8]; default: 1; + * Reserved + */ + uint32_t l1_icache2_tag_mem_force_on:1; + /** l1_icache2_tag_mem_force_pd : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_tag_mem_force_pd:1; + /** l1_icache2_tag_mem_force_pu : HRO; bitpos: [10]; default: 1; + * Reserved + */ + uint32_t l1_icache2_tag_mem_force_pu:1; + uint32_t reserved_11:1; + /** l1_icache3_tag_mem_force_on : HRO; bitpos: [12]; default: 1; + * Reserved + */ + uint32_t l1_icache3_tag_mem_force_on:1; + /** l1_icache3_tag_mem_force_pd : HRO; bitpos: [13]; default: 0; + * Reserved + */ + uint32_t l1_icache3_tag_mem_force_pd:1; + /** l1_icache3_tag_mem_force_pu : HRO; bitpos: [14]; default: 1; + * Reserved + */ + uint32_t l1_icache3_tag_mem_force_pu:1; + uint32_t reserved_15:1; + /** l1_cache_tag_mem_force_on : R/W; bitpos: [16]; default: 1; + * The bit is used to close clock gating of L1-Cache tag memory. 1: close gating, 0: + * open clock gating. + */ + uint32_t l1_cache_tag_mem_force_on:1; + /** l1_cache_tag_mem_force_pd : R/W; bitpos: [17]; default: 0; + * The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down + */ + uint32_t l1_cache_tag_mem_force_pd:1; + /** l1_cache_tag_mem_force_pu : R/W; bitpos: [18]; default: 1; + * The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l1_cache_tag_mem_force_pu:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} extmem_l1_cache_tag_mem_power_ctrl_reg_t; + +/** Type of l2_cache_tag_mem_power_ctrl register + * Cache tag memory power control register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** l2_cache_tag_mem_force_on : HRO; bitpos: [20]; default: 0; + * The bit is used to close clock gating of L2-Cache tag memory. 1: close gating, 0: + * open clock gating. + */ + uint32_t l2_cache_tag_mem_force_on:1; + /** l2_cache_tag_mem_force_pd : HRO; bitpos: [21]; default: 0; + * The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down + */ + uint32_t l2_cache_tag_mem_force_pd:1; + /** l2_cache_tag_mem_force_pu : HRO; bitpos: [22]; default: 0; + * The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l2_cache_tag_mem_force_pu:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} extmem_l2_cache_tag_mem_power_ctrl_reg_t; + + +/** Group: Cache Data Memory Power Control registers */ +/** Type of l1_cache_data_mem_power_ctrl register + * Cache data memory power control register + */ +typedef union { + struct { + /** l1_icache0_data_mem_force_on : HRO; bitpos: [0]; default: 1; + * The bit is used to close clock gating of L1-ICache0 data memory. 1: close gating, + * 0: open clock gating. + */ + uint32_t l1_icache0_data_mem_force_on:1; + /** l1_icache0_data_mem_force_pd : HRO; bitpos: [1]; default: 0; + * The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power + * down + */ + uint32_t l1_icache0_data_mem_force_pd:1; + /** l1_icache0_data_mem_force_pu : HRO; bitpos: [2]; default: 1; + * The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l1_icache0_data_mem_force_pu:1; + uint32_t reserved_3:1; + /** l1_icache1_data_mem_force_on : HRO; bitpos: [4]; default: 1; + * The bit is used to close clock gating of L1-ICache1 data memory. 1: close gating, + * 0: open clock gating. + */ + uint32_t l1_icache1_data_mem_force_on:1; + /** l1_icache1_data_mem_force_pd : HRO; bitpos: [5]; default: 0; + * The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power + * down + */ + uint32_t l1_icache1_data_mem_force_pd:1; + /** l1_icache1_data_mem_force_pu : HRO; bitpos: [6]; default: 1; + * The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l1_icache1_data_mem_force_pu:1; + uint32_t reserved_7:1; + /** l1_icache2_data_mem_force_on : HRO; bitpos: [8]; default: 1; + * Reserved + */ + uint32_t l1_icache2_data_mem_force_on:1; + /** l1_icache2_data_mem_force_pd : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_data_mem_force_pd:1; + /** l1_icache2_data_mem_force_pu : HRO; bitpos: [10]; default: 1; + * Reserved + */ + uint32_t l1_icache2_data_mem_force_pu:1; + uint32_t reserved_11:1; + /** l1_icache3_data_mem_force_on : HRO; bitpos: [12]; default: 1; + * Reserved + */ + uint32_t l1_icache3_data_mem_force_on:1; + /** l1_icache3_data_mem_force_pd : HRO; bitpos: [13]; default: 0; + * Reserved + */ + uint32_t l1_icache3_data_mem_force_pd:1; + /** l1_icache3_data_mem_force_pu : HRO; bitpos: [14]; default: 1; + * Reserved + */ + uint32_t l1_icache3_data_mem_force_pu:1; + uint32_t reserved_15:1; + /** l1_cache_data_mem_force_on : R/W; bitpos: [16]; default: 1; + * The bit is used to close clock gating of L1-Cache data memory. 1: close gating, 0: + * open clock gating. + */ + uint32_t l1_cache_data_mem_force_on:1; + /** l1_cache_data_mem_force_pd : R/W; bitpos: [17]; default: 0; + * The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power + * down + */ + uint32_t l1_cache_data_mem_force_pd:1; + /** l1_cache_data_mem_force_pu : R/W; bitpos: [18]; default: 1; + * The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l1_cache_data_mem_force_pu:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} extmem_l1_cache_data_mem_power_ctrl_reg_t; + +/** Type of l2_cache_data_mem_power_ctrl register + * Cache data memory power control register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** l2_cache_data_mem_force_on : HRO; bitpos: [20]; default: 0; + * The bit is used to close clock gating of L2-Cache data memory. 1: close gating, 0: + * open clock gating. + */ + uint32_t l2_cache_data_mem_force_on:1; + /** l2_cache_data_mem_force_pd : HRO; bitpos: [21]; default: 0; + * The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power + * down + */ + uint32_t l2_cache_data_mem_force_pd:1; + /** l2_cache_data_mem_force_pu : HRO; bitpos: [22]; default: 0; + * The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l2_cache_data_mem_force_pu:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} extmem_l2_cache_data_mem_power_ctrl_reg_t; + + +/** Group: Cache Freeze Control registers */ +/** Type of l1_cache_freeze_ctrl register + * Cache Freeze control register + */ +typedef union { + struct { + /** l1_icache0_freeze_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable freeze operation on L1-ICache0. It can be cleared by + * software. + */ + uint32_t l1_icache0_freeze_en:1; + /** l1_icache0_freeze_mode : HRO; bitpos: [1]; default: 0; + * The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ + uint32_t l1_icache0_freeze_mode:1; + /** l1_icache0_freeze_done : RO; bitpos: [2]; default: 0; + * The bit is used to indicate whether freeze operation on L1-ICache0 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache0_freeze_done:1; + uint32_t reserved_3:1; + /** l1_icache1_freeze_en : HRO; bitpos: [4]; default: 0; + * The bit is used to enable freeze operation on L1-ICache1. It can be cleared by + * software. + */ + uint32_t l1_icache1_freeze_en:1; + /** l1_icache1_freeze_mode : HRO; bitpos: [5]; default: 0; + * The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ + uint32_t l1_icache1_freeze_mode:1; + /** l1_icache1_freeze_done : RO; bitpos: [6]; default: 0; + * The bit is used to indicate whether freeze operation on L1-ICache1 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache1_freeze_done:1; + uint32_t reserved_7:1; + /** l1_icache2_freeze_en : HRO; bitpos: [8]; default: 0; + * Reserved + */ + uint32_t l1_icache2_freeze_en:1; + /** l1_icache2_freeze_mode : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_freeze_mode:1; + /** l1_icache2_freeze_done : RO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l1_icache2_freeze_done:1; + uint32_t reserved_11:1; + /** l1_icache3_freeze_en : HRO; bitpos: [12]; default: 0; + * Reserved + */ + uint32_t l1_icache3_freeze_en:1; + /** l1_icache3_freeze_mode : HRO; bitpos: [13]; default: 0; + * Reserved + */ + uint32_t l1_icache3_freeze_mode:1; + /** l1_icache3_freeze_done : RO; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t l1_icache3_freeze_done:1; + uint32_t reserved_15:1; + /** l1_cache_freeze_en : R/W; bitpos: [16]; default: 0; + * The bit is used to enable freeze operation on L1-Cache. It can be cleared by + * software. + */ + uint32_t l1_cache_freeze_en:1; + /** l1_cache_freeze_mode : R/W; bitpos: [17]; default: 0; + * The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ + uint32_t l1_cache_freeze_mode:1; + /** l1_cache_freeze_done : RO; bitpos: [18]; default: 0; + * The bit is used to indicate whether freeze operation on L1-Cache is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_cache_freeze_done:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} extmem_l1_cache_freeze_ctrl_reg_t; + +/** Type of l2_cache_freeze_ctrl register + * Cache Freeze control register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** l2_cache_freeze_en : HRO; bitpos: [20]; default: 0; + * The bit is used to enable freeze operation on L2-Cache. It can be cleared by + * software. + */ + uint32_t l2_cache_freeze_en:1; + /** l2_cache_freeze_mode : HRO; bitpos: [21]; default: 0; + * The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ + uint32_t l2_cache_freeze_mode:1; + /** l2_cache_freeze_done : RO; bitpos: [22]; default: 0; + * The bit is used to indicate whether freeze operation on L2-Cache is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l2_cache_freeze_done:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} extmem_l2_cache_freeze_ctrl_reg_t; + + +/** Group: Cache Data Memory Access Control and Configuration registers */ +/** Type of l1_cache_data_mem_acs_conf register + * Cache data memory access configure register + */ +typedef union { + struct { + /** l1_icache0_data_mem_rd_en : HRO; bitpos: [0]; default: 1; + * The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache0_data_mem_rd_en:1; + /** l1_icache0_data_mem_wr_en : HRO; bitpos: [1]; default: 1; + * The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, + * 1: enable. + */ + uint32_t l1_icache0_data_mem_wr_en:1; + uint32_t reserved_2:2; + /** l1_icache1_data_mem_rd_en : HRO; bitpos: [4]; default: 1; + * The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache1_data_mem_rd_en:1; + /** l1_icache1_data_mem_wr_en : HRO; bitpos: [5]; default: 1; + * The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, + * 1: enable. + */ + uint32_t l1_icache1_data_mem_wr_en:1; + uint32_t reserved_6:2; + /** l1_icache2_data_mem_rd_en : HRO; bitpos: [8]; default: 1; + * Reserved + */ + uint32_t l1_icache2_data_mem_rd_en:1; + /** l1_icache2_data_mem_wr_en : HRO; bitpos: [9]; default: 1; + * Reserved + */ + uint32_t l1_icache2_data_mem_wr_en:1; + uint32_t reserved_10:2; + /** l1_icache3_data_mem_rd_en : HRO; bitpos: [12]; default: 1; + * Reserved + */ + uint32_t l1_icache3_data_mem_rd_en:1; + /** l1_icache3_data_mem_wr_en : HRO; bitpos: [13]; default: 1; + * Reserved + */ + uint32_t l1_icache3_data_mem_wr_en:1; + uint32_t reserved_14:2; + /** l1_cache_data_mem_rd_en : R/W; bitpos: [16]; default: 1; + * The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_data_mem_rd_en:1; + /** l1_cache_data_mem_wr_en : R/W; bitpos: [17]; default: 1; + * The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_data_mem_wr_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} extmem_l1_cache_data_mem_acs_conf_reg_t; + +/** Type of l2_cache_data_mem_acs_conf register + * Cache data memory access configure register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** l2_cache_data_mem_rd_en : HRO; bitpos: [20]; default: 0; + * The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l2_cache_data_mem_rd_en:1; + /** l2_cache_data_mem_wr_en : HRO; bitpos: [21]; default: 0; + * The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l2_cache_data_mem_wr_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} extmem_l2_cache_data_mem_acs_conf_reg_t; + + +/** Group: Cache Tag Memory Access Control and Configuration registers */ +/** Type of l1_cache_tag_mem_acs_conf register + * Cache tag memory access configure register + */ +typedef union { + struct { + /** l1_icache0_tag_mem_rd_en : HRO; bitpos: [0]; default: 1; + * The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache0_tag_mem_rd_en:1; + /** l1_icache0_tag_mem_wr_en : HRO; bitpos: [1]; default: 1; + * The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache0_tag_mem_wr_en:1; + uint32_t reserved_2:2; + /** l1_icache1_tag_mem_rd_en : HRO; bitpos: [4]; default: 1; + * The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache1_tag_mem_rd_en:1; + /** l1_icache1_tag_mem_wr_en : HRO; bitpos: [5]; default: 1; + * The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_icache1_tag_mem_wr_en:1; + uint32_t reserved_6:2; + /** l1_icache2_tag_mem_rd_en : HRO; bitpos: [8]; default: 1; + * Reserved + */ + uint32_t l1_icache2_tag_mem_rd_en:1; + /** l1_icache2_tag_mem_wr_en : HRO; bitpos: [9]; default: 1; + * Reserved + */ + uint32_t l1_icache2_tag_mem_wr_en:1; + uint32_t reserved_10:2; + /** l1_icache3_tag_mem_rd_en : HRO; bitpos: [12]; default: 1; + * Reserved + */ + uint32_t l1_icache3_tag_mem_rd_en:1; + /** l1_icache3_tag_mem_wr_en : HRO; bitpos: [13]; default: 1; + * Reserved + */ + uint32_t l1_icache3_tag_mem_wr_en:1; + uint32_t reserved_14:2; + /** l1_cache_tag_mem_rd_en : R/W; bitpos: [16]; default: 1; + * The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_tag_mem_rd_en:1; + /** l1_cache_tag_mem_wr_en : R/W; bitpos: [17]; default: 1; + * The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_tag_mem_wr_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} extmem_l1_cache_tag_mem_acs_conf_reg_t; + +/** Type of l2_cache_tag_mem_acs_conf register + * Cache tag memory access configure register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** l2_cache_tag_mem_rd_en : HRO; bitpos: [20]; default: 0; + * The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l2_cache_tag_mem_rd_en:1; + /** l2_cache_tag_mem_wr_en : HRO; bitpos: [21]; default: 0; + * The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l2_cache_tag_mem_wr_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} extmem_l2_cache_tag_mem_acs_conf_reg_t; + + +/** Group: Prelock Control and configuration registers */ +/** Type of l1_icache0_prelock_conf register + * L1 instruction Cache 0 prelock configure register + */ +typedef union { + struct { + /** l1_icache0_prelock_sct0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache0. + */ + uint32_t l1_icache0_prelock_sct0_en:1; + /** l1_icache0_prelock_sct1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache0. + */ + uint32_t l1_icache0_prelock_sct1_en:1; + /** l1_icache0_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache0 prelock. + */ + uint32_t l1_icache0_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l1_icache0_prelock_conf_reg_t; + +/** Type of l1_icache0_prelock_sct0_addr register + * L1 instruction Cache 0 prelock section0 address configure register + */ +typedef union { + struct { + /** l1_icache0_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-ICache0, which should be used together with + * L1_ICACHE0_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l1_icache0_prelock_sct0_addr:32; + }; + uint32_t val; +} extmem_l1_icache0_prelock_sct0_addr_reg_t; + +/** Type of l1_icache0_prelock_sct1_addr register + * L1 instruction Cache 0 prelock section1 address configure register + */ +typedef union { + struct { + /** l1_icache0_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-ICache0, which should be used together with + * L1_ICACHE0_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l1_icache0_prelock_sct1_addr:32; + }; + uint32_t val; +} extmem_l1_icache0_prelock_sct1_addr_reg_t; + +/** Type of l1_icache0_prelock_sct_size register + * L1 instruction Cache 0 prelock section size configure register + */ +typedef union { + struct { + /** l1_icache0_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l1_icache0_prelock_sct0_size:14; + uint32_t reserved_14:2; + /** l1_icache0_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l1_icache0_prelock_sct1_size:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} extmem_l1_icache0_prelock_sct_size_reg_t; + +/** Type of l1_icache1_prelock_conf register + * L1 instruction Cache 1 prelock configure register + */ +typedef union { + struct { + /** l1_icache1_prelock_sct0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache1. + */ + uint32_t l1_icache1_prelock_sct0_en:1; + /** l1_icache1_prelock_sct1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache1. + */ + uint32_t l1_icache1_prelock_sct1_en:1; + /** l1_icache1_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache1 prelock. + */ + uint32_t l1_icache1_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l1_icache1_prelock_conf_reg_t; + +/** Type of l1_icache1_prelock_sct0_addr register + * L1 instruction Cache 1 prelock section0 address configure register + */ +typedef union { + struct { + /** l1_icache1_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-ICache1, which should be used together with + * L1_ICACHE1_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l1_icache1_prelock_sct0_addr:32; + }; + uint32_t val; +} extmem_l1_icache1_prelock_sct0_addr_reg_t; + +/** Type of l1_icache1_prelock_sct1_addr register + * L1 instruction Cache 1 prelock section1 address configure register + */ +typedef union { + struct { + /** l1_icache1_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-ICache1, which should be used together with + * L1_ICACHE1_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l1_icache1_prelock_sct1_addr:32; + }; + uint32_t val; +} extmem_l1_icache1_prelock_sct1_addr_reg_t; + +/** Type of l1_icache1_prelock_sct_size register + * L1 instruction Cache 1 prelock section size configure register + */ +typedef union { + struct { + /** l1_icache1_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l1_icache1_prelock_sct0_size:14; + uint32_t reserved_14:2; + /** l1_icache1_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l1_icache1_prelock_sct1_size:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} extmem_l1_icache1_prelock_sct_size_reg_t; + +/** Type of l1_icache2_prelock_conf register + * L1 instruction Cache 2 prelock configure register + */ +typedef union { + struct { + /** l1_icache2_prelock_sct0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache2. + */ + uint32_t l1_icache2_prelock_sct0_en:1; + /** l1_icache2_prelock_sct1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache2. + */ + uint32_t l1_icache2_prelock_sct1_en:1; + /** l1_icache2_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache2 prelock. + */ + uint32_t l1_icache2_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l1_icache2_prelock_conf_reg_t; + +/** Type of l1_icache2_prelock_sct0_addr register + * L1 instruction Cache 2 prelock section0 address configure register + */ +typedef union { + struct { + /** l1_icache2_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-ICache2, which should be used together with + * L1_ICACHE2_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l1_icache2_prelock_sct0_addr:32; + }; + uint32_t val; +} extmem_l1_icache2_prelock_sct0_addr_reg_t; + +/** Type of l1_icache2_prelock_sct1_addr register + * L1 instruction Cache 2 prelock section1 address configure register + */ +typedef union { + struct { + /** l1_icache2_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-ICache2, which should be used together with + * L1_ICACHE2_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l1_icache2_prelock_sct1_addr:32; + }; + uint32_t val; +} extmem_l1_icache2_prelock_sct1_addr_reg_t; + +/** Type of l1_icache2_prelock_sct_size register + * L1 instruction Cache 2 prelock section size configure register + */ +typedef union { + struct { + /** l1_icache2_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l1_icache2_prelock_sct0_size:14; + uint32_t reserved_14:2; + /** l1_icache2_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l1_icache2_prelock_sct1_size:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} extmem_l1_icache2_prelock_sct_size_reg_t; + +/** Type of l1_icache3_prelock_conf register + * L1 instruction Cache 3 prelock configure register + */ +typedef union { + struct { + /** l1_icache3_prelock_sct0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-ICache3. + */ + uint32_t l1_icache3_prelock_sct0_en:1; + /** l1_icache3_prelock_sct1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-ICache3. + */ + uint32_t l1_icache3_prelock_sct1_en:1; + /** l1_icache3_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 icache3 prelock. + */ + uint32_t l1_icache3_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l1_icache3_prelock_conf_reg_t; + +/** Type of l1_icache3_prelock_sct0_addr register + * L1 instruction Cache 3 prelock section0 address configure register + */ +typedef union { + struct { + /** l1_icache3_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-ICache3, which should be used together with + * L1_ICACHE3_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l1_icache3_prelock_sct0_addr:32; + }; + uint32_t val; +} extmem_l1_icache3_prelock_sct0_addr_reg_t; + +/** Type of l1_icache3_prelock_sct1_addr register + * L1 instruction Cache 3 prelock section1 address configure register + */ +typedef union { + struct { + /** l1_icache3_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-ICache3, which should be used together with + * L1_ICACHE3_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l1_icache3_prelock_sct1_addr:32; + }; + uint32_t val; +} extmem_l1_icache3_prelock_sct1_addr_reg_t; + +/** Type of l1_icache3_prelock_sct_size register + * L1 instruction Cache 3 prelock section size configure register + */ +typedef union { + struct { + /** l1_icache3_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l1_icache3_prelock_sct0_size:14; + uint32_t reserved_14:2; + /** l1_icache3_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l1_icache3_prelock_sct1_size:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} extmem_l1_icache3_prelock_sct_size_reg_t; + +/** Type of l1_cache_prelock_conf register + * L1 Cache prelock configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct0_en : R/W; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-Cache. + */ + uint32_t l1_cache_prelock_sct0_en:1; + /** l1_cache_prelock_sct1_en : R/W; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-Cache. + */ + uint32_t l1_cache_prelock_sct1_en:1; + /** l1_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 cache prelock. + */ + uint32_t l1_cache_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l1_cache_prelock_conf_reg_t; + +/** Type of l1_cache_prelock_sct0_addr register + * L1 Cache prelock section0 address configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-Cache, which should be used together with + * L1_CACHE_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l1_cache_prelock_sct0_addr:32; + }; + uint32_t val; +} extmem_l1_cache_prelock_sct0_addr_reg_t; + +/** Type of l1_dcache_prelock_sct1_addr register + * L1 Cache prelock section1 address configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-Cache, which should be used together with + * L1_CACHE_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l1_cache_prelock_sct1_addr:32; + }; + uint32_t val; +} extmem_l1_dcache_prelock_sct1_addr_reg_t; + +/** Type of l1_dcache_prelock_sct_size register + * L1 Cache prelock section size configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l1_cache_prelock_sct0_size:14; + uint32_t reserved_14:2; + /** l1_cache_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l1_cache_prelock_sct1_size:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} extmem_l1_dcache_prelock_sct_size_reg_t; + +/** Type of l2_cache_prelock_conf register + * L2 Cache prelock configure register + */ +typedef union { + struct { + /** l2_cache_prelock_sct0_en : HRO; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L2-Cache. + */ + uint32_t l2_cache_prelock_sct0_en:1; + /** l2_cache_prelock_sct1_en : HRO; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L2-Cache. + */ + uint32_t l2_cache_prelock_sct1_en:1; + /** l2_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l2 cache prelock. + */ + uint32_t l2_cache_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_cache_prelock_conf_reg_t; + +/** Type of l2_cache_prelock_sct0_addr register + * L2 Cache prelock section0 address configure register + */ +typedef union { + struct { + /** l2_cache_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L2-Cache, which should be used together with + * L2_CACHE_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l2_cache_prelock_sct0_addr:32; + }; + uint32_t val; +} extmem_l2_cache_prelock_sct0_addr_reg_t; + +/** Type of l2_cache_prelock_sct1_addr register + * L2 Cache prelock section1 address configure register + */ +typedef union { + struct { + /** l2_cache_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L2-Cache, which should be used together with + * L2_CACHE_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l2_cache_prelock_sct1_addr:32; + }; + uint32_t val; +} extmem_l2_cache_prelock_sct1_addr_reg_t; + +/** Type of l2_cache_prelock_sct_size register + * L2 Cache prelock section size configure register + */ +typedef union { + struct { + /** l2_cache_prelock_sct0_size : HRO; bitpos: [15:0]; default: 65535; + * Those bits are used to configure the size of the first section of prelock on + * L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l2_cache_prelock_sct0_size:16; + /** l2_cache_prelock_sct1_size : HRO; bitpos: [31:16]; default: 65535; + * Those bits are used to configure the size of the second section of prelock on + * L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l2_cache_prelock_sct1_size:16; + }; + uint32_t val; +} extmem_l2_cache_prelock_sct_size_reg_t; + + +/** Group: Lock Control and configuration registers */ +/** Type of cache_lock_ctrl register + * Lock-class (manual lock) operation control register + */ +typedef union { + struct { + /** cache_lock_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable lock operation. It will be cleared by hardware after lock + * operation done + */ + uint32_t cache_lock_ena:1; + /** cache_unlock_ena : R/W/SC; bitpos: [1]; default: 0; + * The bit is used to enable unlock operation. It will be cleared by hardware after + * unlock operation done + */ + uint32_t cache_unlock_ena:1; + /** cache_lock_done : RO; bitpos: [2]; default: 1; + * The bit is used to indicate whether unlock/lock operation is finished or not. 0: + * not finished. 1: finished. + */ + uint32_t cache_lock_done:1; + /** cache_lock_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of cache lock/unlock. + */ + uint32_t cache_lock_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} extmem_cache_lock_ctrl_reg_t; + +/** Type of cache_lock_map register + * Lock (manual lock) map configure register + */ +typedef union { + struct { + /** cache_lock_map : R/W; bitpos: [5:0]; default: 0; + * Those bits are used to indicate which caches in the two-level cache structure will + * apply this lock/unlock operation. [4]: L1-Cache + */ + uint32_t cache_lock_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_cache_lock_map_reg_t; + +/** Type of cache_lock_addr register + * Lock (manual lock) address configure register + */ +typedef union { + struct { + /** cache_lock_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the lock/unlock + * operation, which should be used together with CACHE_LOCK_SIZE_REG + */ + uint32_t cache_lock_addr:32; + }; + uint32_t val; +} extmem_cache_lock_addr_reg_t; + +/** Type of cache_lock_size register + * Lock (manual lock) size configure register + */ +typedef union { + struct { + /** cache_lock_size : R/W; bitpos: [15:0]; default: 0; + * Those bits are used to configure the size of the lock/unlock operation, which + * should be used together with CACHE_LOCK_ADDR_REG + */ + uint32_t cache_lock_size:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} extmem_cache_lock_size_reg_t; + + +/** Group: Sync Control and configuration registers */ +/** Type of cache_sync_ctrl register + * Sync-class operation control register + */ +typedef union { + struct { + /** cache_invalidate_ena : R/W/SC; bitpos: [0]; default: 1; + * The bit is used to enable invalidate operation. It will be cleared by hardware + * after invalidate operation done. Note that this bit and the other sync-bits + * (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that + * is, those bits can not be set to 1 at the same time. + */ + uint32_t cache_invalidate_ena:1; + /** cache_clean_ena : R/W/SC; bitpos: [1]; default: 0; + * The bit is used to enable clean operation. It will be cleared by hardware after + * clean operation done. Note that this bit and the other sync-bits (invalidate_ena, + * writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those + * bits can not be set to 1 at the same time. + */ + uint32_t cache_clean_ena:1; + /** cache_writeback_ena : R/W/SC; bitpos: [2]; default: 0; + * The bit is used to enable writeback operation. It will be cleared by hardware after + * writeback operation done. Note that this bit and the other sync-bits + * (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that + * is, those bits can not be set to 1 at the same time. + */ + uint32_t cache_writeback_ena:1; + /** cache_writeback_invalidate_ena : R/W/SC; bitpos: [3]; default: 0; + * The bit is used to enable writeback-invalidate operation. It will be cleared by + * hardware after writeback-invalidate operation done. Note that this bit and the + * other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, + * that is, those bits can not be set to 1 at the same time. + */ + uint32_t cache_writeback_invalidate_ena:1; + /** cache_sync_done : RO; bitpos: [4]; default: 0; + * The bit is used to indicate whether sync operation (invalidate, clean, writeback, + * writeback_invalidate) is finished or not. 0: not finished. 1: finished. + */ + uint32_t cache_sync_done:1; + /** cache_sync_rgid : HRO; bitpos: [8:5]; default: 0; + * The bit is used to set the gid of cache sync operation (invalidate, clean, + * writeback, writeback_invalidate) + */ + uint32_t cache_sync_rgid:4; + uint32_t reserved_9:23; + }; + uint32_t val; +} extmem_cache_sync_ctrl_reg_t; + +/** Type of cache_sync_map register + * Sync map configure register + */ +typedef union { + struct { + /** cache_sync_map : R/W; bitpos: [5:0]; default: 63; + * Those bits are used to indicate which caches in the two-level cache structure will + * apply the sync operation. [4]: L1-Cache + */ + uint32_t cache_sync_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_cache_sync_map_reg_t; + +/** Type of cache_sync_addr register + * Sync address configure register + */ +typedef union { + struct { + /** cache_sync_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the sync operation, + * which should be used together with CACHE_SYNC_SIZE_REG + */ + uint32_t cache_sync_addr:32; + }; + uint32_t val; +} extmem_cache_sync_addr_reg_t; + +/** Type of cache_sync_size register + * Sync size configure register + */ +typedef union { + struct { + /** cache_sync_size : R/W; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the sync operation, which should be + * used together with CACHE_SYNC_ADDR_REG + */ + uint32_t cache_sync_size:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} extmem_cache_sync_size_reg_t; + + +/** Group: Preload Control and configuration registers */ +/** Type of l1_icache0_preload_ctrl register + * L1 instruction Cache 0 preload-operation control register + */ +typedef union { + struct { + /** l1_icache0_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache0. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l1_icache0_preload_ena:1; + /** l1_icache0_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l1_icache0_preload_done:1; + /** l1_icache0_preload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l1_icache0_preload_order:1; + /** l1_icache0_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache0 preload. + */ + uint32_t l1_icache0_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} extmem_l1_icache0_preload_ctrl_reg_t; + +/** Type of l1_icache0_preload_addr register + * L1 instruction Cache 0 preload address configure register + */ +typedef union { + struct { + /** l1_icache0_preload_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on + * L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG + */ + uint32_t l1_icache0_preload_addr:32; + }; + uint32_t val; +} extmem_l1_icache0_preload_addr_reg_t; + +/** Type of l1_icache0_preload_size register + * L1 instruction Cache 0 preload size configure register + */ +typedef union { + struct { + /** l1_icache0_preload_size : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG + */ + uint32_t l1_icache0_preload_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_icache0_preload_size_reg_t; + +/** Type of l1_icache1_preload_ctrl register + * L1 instruction Cache 1 preload-operation control register + */ +typedef union { + struct { + /** l1_icache1_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache1. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l1_icache1_preload_ena:1; + /** l1_icache1_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l1_icache1_preload_done:1; + /** l1_icache1_preload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l1_icache1_preload_order:1; + /** l1_icache1_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache1 preload. + */ + uint32_t l1_icache1_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} extmem_l1_icache1_preload_ctrl_reg_t; + +/** Type of l1_icache1_preload_addr register + * L1 instruction Cache 1 preload address configure register + */ +typedef union { + struct { + /** l1_icache1_preload_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on + * L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG + */ + uint32_t l1_icache1_preload_addr:32; + }; + uint32_t val; +} extmem_l1_icache1_preload_addr_reg_t; + +/** Type of l1_icache1_preload_size register + * L1 instruction Cache 1 preload size configure register + */ +typedef union { + struct { + /** l1_icache1_preload_size : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG + */ + uint32_t l1_icache1_preload_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_icache1_preload_size_reg_t; + +/** Type of l1_icache2_preload_ctrl register + * L1 instruction Cache 2 preload-operation control register + */ +typedef union { + struct { + /** l1_icache2_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache2. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l1_icache2_preload_ena:1; + /** l1_icache2_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l1_icache2_preload_done:1; + /** l1_icache2_preload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l1_icache2_preload_order:1; + /** l1_icache2_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache2 preload. + */ + uint32_t l1_icache2_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} extmem_l1_icache2_preload_ctrl_reg_t; + +/** Type of l1_icache2_preload_addr register + * L1 instruction Cache 2 preload address configure register + */ +typedef union { + struct { + /** l1_icache2_preload_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on + * L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG + */ + uint32_t l1_icache2_preload_addr:32; + }; + uint32_t val; +} extmem_l1_icache2_preload_addr_reg_t; + +/** Type of l1_icache2_preload_size register + * L1 instruction Cache 2 preload size configure register + */ +typedef union { + struct { + /** l1_icache2_preload_size : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG + */ + uint32_t l1_icache2_preload_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_icache2_preload_size_reg_t; + +/** Type of l1_icache3_preload_ctrl register + * L1 instruction Cache 3 preload-operation control register + */ +typedef union { + struct { + /** l1_icache3_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-ICache3. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l1_icache3_preload_ena:1; + /** l1_icache3_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l1_icache3_preload_done:1; + /** l1_icache3_preload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l1_icache3_preload_order:1; + /** l1_icache3_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 icache3 preload. + */ + uint32_t l1_icache3_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} extmem_l1_icache3_preload_ctrl_reg_t; + +/** Type of l1_icache3_preload_addr register + * L1 instruction Cache 3 preload address configure register + */ +typedef union { + struct { + /** l1_icache3_preload_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on + * L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG + */ + uint32_t l1_icache3_preload_addr:32; + }; + uint32_t val; +} extmem_l1_icache3_preload_addr_reg_t; + +/** Type of l1_icache3_preload_size register + * L1 instruction Cache 3 preload size configure register + */ +typedef union { + struct { + /** l1_icache3_preload_size : HRO; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG + */ + uint32_t l1_icache3_preload_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_icache3_preload_size_reg_t; + +/** Type of l1_cache_preload_ctrl register + * L1 Cache preload-operation control register + */ +typedef union { + struct { + /** l1_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-Cache. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l1_cache_preload_ena:1; + /** l1_cache_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l1_cache_preload_done:1; + /** l1_cache_preload_order : R/W; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l1_cache_preload_order:1; + /** l1_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 cache preload. + */ + uint32_t l1_cache_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} extmem_l1_cache_preload_ctrl_reg_t; + +/** Type of l1_dcache_preload_addr register + * L1 Cache preload address configure register + */ +typedef union { + struct { + /** l1_cache_preload_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on L1-Cache, + * which should be used together with L1_CACHE_PRELOAD_SIZE_REG + */ + uint32_t l1_cache_preload_addr:32; + }; + uint32_t val; +} extmem_l1_dcache_preload_addr_reg_t; + +/** Type of l1_dcache_preload_size register + * L1 Cache preload size configure register + */ +typedef union { + struct { + /** l1_cache_preload_size : R/W; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG + */ + uint32_t l1_cache_preload_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_dcache_preload_size_reg_t; + +/** Type of l2_cache_preload_ctrl register + * L2 Cache preload-operation control register + */ +typedef union { + struct { + /** l2_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L2-Cache. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l2_cache_preload_ena:1; + /** l2_cache_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l2_cache_preload_done:1; + /** l2_cache_preload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l2_cache_preload_order:1; + /** l2_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l2 cache preload. + */ + uint32_t l2_cache_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} extmem_l2_cache_preload_ctrl_reg_t; + +/** Type of l2_cache_preload_addr register + * L2 Cache preload address configure register + */ +typedef union { + struct { + /** l2_cache_preload_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on L2-Cache, + * which should be used together with L2_CACHE_PRELOAD_SIZE_REG + */ + uint32_t l2_cache_preload_addr:32; + }; + uint32_t val; +} extmem_l2_cache_preload_addr_reg_t; + +/** Type of l2_cache_preload_size register + * L2 Cache preload size configure register + */ +typedef union { + struct { + /** l2_cache_preload_size : HRO; bitpos: [15:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG + */ + uint32_t l2_cache_preload_size:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} extmem_l2_cache_preload_size_reg_t; + + +/** Group: Autoload Control and configuration registers */ +/** Type of l1_icache0_autoload_ctrl register + * L1 instruction Cache 0 autoload-operation control register + */ +typedef union { + struct { + /** l1_icache0_autoload_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, + * 0: disable. + */ + uint32_t l1_icache0_autoload_ena:1; + /** l1_icache0_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache0 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache0_autoload_done:1; + /** l1_icache0_autoload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache0. 0: + * ascending. 1: descending. + */ + uint32_t l1_icache0_autoload_order:1; + /** l1_icache0_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache0. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l1_icache0_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l1_icache0_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache0. + */ + uint32_t l1_icache0_autoload_sct0_ena:1; + /** l1_icache0_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache0. + */ + uint32_t l1_icache0_autoload_sct1_ena:1; + /** l1_icache0_autoload_rgid : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache0 autoload. + */ + uint32_t l1_icache0_autoload_rgid:4; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_icache0_autoload_ctrl_reg_t; + +/** Type of l1_icache0_autoload_sct0_addr register + * L1 instruction Cache 0 autoload section 0 address configure register + */ +typedef union { + struct { + /** l1_icache0_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache0_autoload_sct0_addr:32; + }; + uint32_t val; +} extmem_l1_icache0_autoload_sct0_addr_reg_t; + +/** Type of l1_icache0_autoload_sct0_size register + * L1 instruction Cache 0 autoload section 0 size configure register + */ +typedef union { + struct { + /** l1_icache0_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache0_autoload_sct0_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_icache0_autoload_sct0_size_reg_t; + +/** Type of l1_icache0_autoload_sct1_addr register + * L1 instruction Cache 0 autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_icache0_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache0_autoload_sct1_addr:32; + }; + uint32_t val; +} extmem_l1_icache0_autoload_sct1_addr_reg_t; + +/** Type of l1_icache0_autoload_sct1_size register + * L1 instruction Cache 0 autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_icache0_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-ICache0. Note that it should be used together with + * L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache0_autoload_sct1_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_icache0_autoload_sct1_size_reg_t; + +/** Type of l1_icache1_autoload_ctrl register + * L1 instruction Cache 1 autoload-operation control register + */ +typedef union { + struct { + /** l1_icache1_autoload_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, + * 0: disable. + */ + uint32_t l1_icache1_autoload_ena:1; + /** l1_icache1_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache1 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache1_autoload_done:1; + /** l1_icache1_autoload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache1. 0: + * ascending. 1: descending. + */ + uint32_t l1_icache1_autoload_order:1; + /** l1_icache1_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache1. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l1_icache1_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l1_icache1_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache1. + */ + uint32_t l1_icache1_autoload_sct0_ena:1; + /** l1_icache1_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache1. + */ + uint32_t l1_icache1_autoload_sct1_ena:1; + /** l1_icache1_autoload_rgid : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache1 autoload. + */ + uint32_t l1_icache1_autoload_rgid:4; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_icache1_autoload_ctrl_reg_t; + +/** Type of l1_icache1_autoload_sct0_addr register + * L1 instruction Cache 1 autoload section 0 address configure register + */ +typedef union { + struct { + /** l1_icache1_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache1_autoload_sct0_addr:32; + }; + uint32_t val; +} extmem_l1_icache1_autoload_sct0_addr_reg_t; + +/** Type of l1_icache1_autoload_sct0_size register + * L1 instruction Cache 1 autoload section 0 size configure register + */ +typedef union { + struct { + /** l1_icache1_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache1_autoload_sct0_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_icache1_autoload_sct0_size_reg_t; + +/** Type of l1_icache1_autoload_sct1_addr register + * L1 instruction Cache 1 autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_icache1_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache1_autoload_sct1_addr:32; + }; + uint32_t val; +} extmem_l1_icache1_autoload_sct1_addr_reg_t; + +/** Type of l1_icache1_autoload_sct1_size register + * L1 instruction Cache 1 autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_icache1_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-ICache1. Note that it should be used together with + * L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache1_autoload_sct1_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_icache1_autoload_sct1_size_reg_t; + +/** Type of l1_icache2_autoload_ctrl register + * L1 instruction Cache 2 autoload-operation control register + */ +typedef union { + struct { + /** l1_icache2_autoload_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache2. 1: enable, + * 0: disable. + */ + uint32_t l1_icache2_autoload_ena:1; + /** l1_icache2_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache2 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache2_autoload_done:1; + /** l1_icache2_autoload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache2. 0: + * ascending. 1: descending. + */ + uint32_t l1_icache2_autoload_order:1; + /** l1_icache2_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache2. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l1_icache2_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l1_icache2_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache2. + */ + uint32_t l1_icache2_autoload_sct0_ena:1; + /** l1_icache2_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache2. + */ + uint32_t l1_icache2_autoload_sct1_ena:1; + /** l1_icache2_autoload_rgid : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache2 autoload. + */ + uint32_t l1_icache2_autoload_rgid:4; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_icache2_autoload_ctrl_reg_t; + +/** Type of l1_icache2_autoload_sct0_addr register + * L1 instruction Cache 2 autoload section 0 address configure register + */ +typedef union { + struct { + /** l1_icache2_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache2_autoload_sct0_addr:32; + }; + uint32_t val; +} extmem_l1_icache2_autoload_sct0_addr_reg_t; + +/** Type of l1_icache2_autoload_sct0_size register + * L1 instruction Cache 2 autoload section 0 size configure register + */ +typedef union { + struct { + /** l1_icache2_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache2_autoload_sct0_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_icache2_autoload_sct0_size_reg_t; + +/** Type of l1_icache2_autoload_sct1_addr register + * L1 instruction Cache 2 autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_icache2_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache2_autoload_sct1_addr:32; + }; + uint32_t val; +} extmem_l1_icache2_autoload_sct1_addr_reg_t; + +/** Type of l1_icache2_autoload_sct1_size register + * L1 instruction Cache 2 autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_icache2_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-ICache2. Note that it should be used together with + * L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache2_autoload_sct1_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_icache2_autoload_sct1_size_reg_t; + +/** Type of l1_icache3_autoload_ctrl register + * L1 instruction Cache 3 autoload-operation control register + */ +typedef union { + struct { + /** l1_icache3_autoload_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-ICache3. 1: enable, + * 0: disable. + */ + uint32_t l1_icache3_autoload_ena:1; + /** l1_icache3_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-ICache3 is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_icache3_autoload_done:1; + /** l1_icache3_autoload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-ICache3. 0: + * ascending. 1: descending. + */ + uint32_t l1_icache3_autoload_order:1; + /** l1_icache3_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-ICache3. + * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l1_icache3_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l1_icache3_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-ICache3. + */ + uint32_t l1_icache3_autoload_sct0_ena:1; + /** l1_icache3_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-ICache3. + */ + uint32_t l1_icache3_autoload_sct1_ena:1; + /** l1_icache3_autoload_rgid : HRO; bitpos: [13:10]; default: 0; + * The bit is used to set the gid of l1 icache3 autoload. + */ + uint32_t l1_icache3_autoload_rgid:4; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_icache3_autoload_ctrl_reg_t; + +/** Type of l1_icache3_autoload_sct0_addr register + * L1 instruction Cache 3 autoload section 0 address configure register + */ +typedef union { + struct { + /** l1_icache3_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-ICache3. Note that it should be used together with + * L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache3_autoload_sct0_addr:32; + }; + uint32_t val; +} extmem_l1_icache3_autoload_sct0_addr_reg_t; + +/** Type of l1_icache3_autoload_sct0_size register + * L1 instruction Cache 3 autoload section 0 size configure register + */ +typedef union { + struct { + /** l1_icache3_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-ICache3. Note that it should be used together with + * L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_icache3_autoload_sct0_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_icache3_autoload_sct0_size_reg_t; + +/** Type of l1_icache3_autoload_sct1_addr register + * L1 instruction Cache 3 autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_icache3_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-ICache3. Note that it should be used together with + * L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_icache3_autoload_sct1_addr:32; + }; + uint32_t val; +} extmem_l1_icache3_autoload_sct1_addr_reg_t; + +/** Type of l1_icache3_autoload_sct1_size register + * L1 instruction Cache 3 autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_icache3_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; + * Reserved + */ + uint32_t l1_icache3_autoload_sct1_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_icache3_autoload_sct1_size_reg_t; + +/** Type of l1_cache_autoload_ctrl register + * L1 Cache autoload-operation control register + */ +typedef union { + struct { + /** l1_cache_autoload_ena : R/W; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-Cache. 1: enable, + * 0: disable. + */ + uint32_t l1_cache_autoload_ena:1; + /** l1_cache_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-Cache is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_cache_autoload_done:1; + /** l1_cache_autoload_order : R/W; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-Cache. 0: + * ascending. 1: descending. + */ + uint32_t l1_cache_autoload_order:1; + /** l1_cache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3: + * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l1_cache_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l1_cache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-Cache. + */ + uint32_t l1_cache_autoload_sct0_ena:1; + /** l1_cache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-Cache. + */ + uint32_t l1_cache_autoload_sct1_ena:1; + /** l1_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0; + * The bit is used to enable the third section for autoload operation on L1-Cache. + */ + uint32_t l1_cache_autoload_sct2_ena:1; + /** l1_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0; + * The bit is used to enable the fourth section for autoload operation on L1-Cache. + */ + uint32_t l1_cache_autoload_sct3_ena:1; + /** l1_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0; + * The bit is used to set the gid of l1 cache autoload. + */ + uint32_t l1_cache_autoload_rgid:4; + uint32_t reserved_16:16; + }; + uint32_t val; +} extmem_l1_cache_autoload_ctrl_reg_t; + +/** Type of l1_cache_autoload_sct0_addr register + * L1 Cache autoload section 0 address configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_cache_autoload_sct0_addr:32; + }; + uint32_t val; +} extmem_l1_cache_autoload_sct0_addr_reg_t; + +/** Type of l1_cache_autoload_sct0_size register + * L1 Cache autoload section 0 size configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct0_size : R/W; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_cache_autoload_sct0_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_cache_autoload_sct0_size_reg_t; + +/** Type of l1_cache_autoload_sct1_addr register + * L1 Cache autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_cache_autoload_sct1_addr:32; + }; + uint32_t val; +} extmem_l1_cache_autoload_sct1_addr_reg_t; + +/** Type of l1_cache_autoload_sct1_size register + * L1 Cache autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct1_size : R/W; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_cache_autoload_sct1_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_cache_autoload_sct1_size_reg_t; + +/** Type of l1_cache_autoload_sct2_addr register + * L1 Cache autoload section 2 address configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the third section for + * autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA. + */ + uint32_t l1_cache_autoload_sct2_addr:32; + }; + uint32_t val; +} extmem_l1_cache_autoload_sct2_addr_reg_t; + +/** Type of l1_cache_autoload_sct2_size register + * L1 Cache autoload section 2 size configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the third section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA. + */ + uint32_t l1_cache_autoload_sct2_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_cache_autoload_sct2_size_reg_t; + +/** Type of l1_cache_autoload_sct3_addr register + * L1 Cache autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the fourth section + * for autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA. + */ + uint32_t l1_cache_autoload_sct3_addr:32; + }; + uint32_t val; +} extmem_l1_cache_autoload_sct3_addr_reg_t; + +/** Type of l1_cache_autoload_sct3_size register + * L1 Cache autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the fourth section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA. + */ + uint32_t l1_cache_autoload_sct3_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l1_cache_autoload_sct3_size_reg_t; + +/** Type of l2_cache_autoload_ctrl register + * L2 Cache autoload-operation control register + */ +typedef union { + struct { + /** l2_cache_autoload_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, + * 0: disable. + */ + uint32_t l2_cache_autoload_ena:1; + /** l2_cache_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L2-Cache is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l2_cache_autoload_done:1; + /** l2_cache_autoload_order : HRO; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L2-Cache. 0: + * ascending. 1: descending. + */ + uint32_t l2_cache_autoload_order:1; + /** l2_cache_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: + * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l2_cache_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l2_cache_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L2-Cache. + */ + uint32_t l2_cache_autoload_sct0_ena:1; + /** l2_cache_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L2-Cache. + */ + uint32_t l2_cache_autoload_sct1_ena:1; + /** l2_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0; + * The bit is used to enable the third section for autoload operation on L2-Cache. + */ + uint32_t l2_cache_autoload_sct2_ena:1; + /** l2_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0; + * The bit is used to enable the fourth section for autoload operation on L2-Cache. + */ + uint32_t l2_cache_autoload_sct3_ena:1; + /** l2_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0; + * The bit is used to set the gid of l2 cache autoload. + */ + uint32_t l2_cache_autoload_rgid:4; + uint32_t reserved_16:16; + }; + uint32_t val; +} extmem_l2_cache_autoload_ctrl_reg_t; + +/** Type of l2_cache_autoload_sct0_addr register + * L2 Cache autoload section 0 address configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l2_cache_autoload_sct0_addr:32; + }; + uint32_t val; +} extmem_l2_cache_autoload_sct0_addr_reg_t; + +/** Type of l2_cache_autoload_sct0_size register + * L2 Cache autoload section 0 size configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l2_cache_autoload_sct0_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l2_cache_autoload_sct0_size_reg_t; + +/** Type of l2_cache_autoload_sct1_addr register + * L2 Cache autoload section 1 address configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l2_cache_autoload_sct1_addr:32; + }; + uint32_t val; +} extmem_l2_cache_autoload_sct1_addr_reg_t; + +/** Type of l2_cache_autoload_sct1_size register + * L2 Cache autoload section 1 size configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l2_cache_autoload_sct1_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l2_cache_autoload_sct1_size_reg_t; + +/** Type of l2_cache_autoload_sct2_addr register + * L2 Cache autoload section 2 address configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the third section for + * autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA. + */ + uint32_t l2_cache_autoload_sct2_addr:32; + }; + uint32_t val; +} extmem_l2_cache_autoload_sct2_addr_reg_t; + +/** Type of l2_cache_autoload_sct2_size register + * L2 Cache autoload section 2 size configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the third section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA. + */ + uint32_t l2_cache_autoload_sct2_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l2_cache_autoload_sct2_size_reg_t; + +/** Type of l2_cache_autoload_sct3_addr register + * L2 Cache autoload section 3 address configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the fourth section + * for autoload operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA. + */ + uint32_t l2_cache_autoload_sct3_addr:32; + }; + uint32_t val; +} extmem_l2_cache_autoload_sct3_addr_reg_t; + +/** Type of l2_cache_autoload_sct3_size register + * L2 Cache autoload section 3 size configure register + */ +typedef union { + struct { + /** l2_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0; + * Those bits are used to configure the size of the fourth section for autoload + * operation on L2-Cache. Note that it should be used together with + * L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA. + */ + uint32_t l2_cache_autoload_sct3_size:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_l2_cache_autoload_sct3_size_reg_t; + + +/** Group: Interrupt registers */ +/** Type of l1_cache_acs_cnt_int_ena register + * Cache Access Counter Interrupt enable register + */ +typedef union { + struct { + /** l1_ibus0_ovf_int_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-ICache0 due to bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_ovf_int_ena:1; + /** l1_ibus1_ovf_int_ena : HRO; bitpos: [1]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-ICache1 due to bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_ovf_int_ena:1; + /** l1_ibus2_ovf_int_ena : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_ibus2_ovf_int_ena:1; + /** l1_ibus3_ovf_int_ena : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_ibus3_ovf_int_ena:1; + /** l1_bus0_ovf_int_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-DCache due to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_ena:1; + /** l1_bus1_ovf_int_ena : R/W; bitpos: [5]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-DCache due to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_ena:1; + /** l1_dbus2_ovf_int_ena : HRO; bitpos: [6]; default: 0; + * Reserved + */ + uint32_t l1_dbus2_ovf_int_ena:1; + /** l1_dbus3_ovf_int_ena : HRO; bitpos: [7]; default: 0; + * Reserved + */ + uint32_t l1_dbus3_ovf_int_ena:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} extmem_l1_cache_acs_cnt_int_ena_reg_t; + +/** Type of l1_cache_acs_cnt_int_clr register + * Cache Access Counter Interrupt clear register + */ +typedef union { + struct { + /** l1_ibus0_ovf_int_clr : HRO; bitpos: [0]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due + * to bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_ovf_int_clr:1; + /** l1_ibus1_ovf_int_clr : HRO; bitpos: [1]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due + * to bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_ovf_int_clr:1; + /** l1_ibus2_ovf_int_clr : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_ibus2_ovf_int_clr:1; + /** l1_ibus3_ovf_int_clr : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_ibus3_ovf_int_clr:1; + /** l1_bus0_ovf_int_clr : WT; bitpos: [4]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-DCache due + * to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_clr:1; + /** l1_bus1_ovf_int_clr : WT; bitpos: [5]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-DCache due + * to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_clr:1; + /** l1_dbus2_ovf_int_clr : HRO; bitpos: [6]; default: 0; + * Reserved + */ + uint32_t l1_dbus2_ovf_int_clr:1; + /** l1_dbus3_ovf_int_clr : HRO; bitpos: [7]; default: 0; + * Reserved + */ + uint32_t l1_dbus3_ovf_int_clr:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} extmem_l1_cache_acs_cnt_int_clr_reg_t; + +/** Type of l1_cache_acs_cnt_int_raw register + * Cache Access Counter Interrupt raw register + */ +typedef union { + struct { + /** l1_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 + * due to bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_ovf_int_raw:1; + /** l1_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 + * due to bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_ovf_int_raw:1; + /** l1_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 + * due to bus2 accesses L1-ICache2. + */ + uint32_t l1_ibus2_ovf_int_raw:1; + /** l1_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 + * due to bus3 accesses L1-ICache3. + */ + uint32_t l1_ibus3_ovf_int_raw:1; + /** l1_bus0_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_raw:1; + /** l1_bus1_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_raw:1; + /** l1_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus2 accesses L1-DCache. + */ + uint32_t l1_dbus2_ovf_int_raw:1; + /** l1_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus3 accesses L1-DCache. + */ + uint32_t l1_dbus3_ovf_int_raw:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} extmem_l1_cache_acs_cnt_int_raw_reg_t; + +/** Type of l1_cache_acs_cnt_int_st register + * Cache Access Counter Interrupt status register + */ +typedef union { + struct { + /** l1_ibus0_ovf_int_st : HRO; bitpos: [0]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-ICache0 due to bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_ovf_int_st:1; + /** l1_ibus1_ovf_int_st : HRO; bitpos: [1]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-ICache1 due to bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_ovf_int_st:1; + /** l1_ibus2_ovf_int_st : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_ibus2_ovf_int_st:1; + /** l1_ibus3_ovf_int_st : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_ibus3_ovf_int_st:1; + /** l1_bus0_ovf_int_st : RO; bitpos: [4]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-DCache due to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_st:1; + /** l1_bus1_ovf_int_st : RO; bitpos: [5]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-DCache due to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_st:1; + /** l1_dbus2_ovf_int_st : HRO; bitpos: [6]; default: 0; + * Reserved + */ + uint32_t l1_dbus2_ovf_int_st:1; + /** l1_dbus3_ovf_int_st : HRO; bitpos: [7]; default: 0; + * Reserved + */ + uint32_t l1_dbus3_ovf_int_st:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} extmem_l1_cache_acs_cnt_int_st_reg_t; + +/** Type of l1_cache_acs_fail_int_ena register + * Cache Access Fail Interrupt enable register + */ +typedef union { + struct { + /** l1_icache0_fail_int_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to + * cpu accesses L1-ICache0. + */ + uint32_t l1_icache0_fail_int_ena:1; + /** l1_icache1_fail_int_ena : HRO; bitpos: [1]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to + * cpu accesses L1-ICache1. + */ + uint32_t l1_icache1_fail_int_ena:1; + /** l1_icache2_fail_int_ena : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_fail_int_ena:1; + /** l1_icache3_fail_int_ena : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_fail_int_ena:1; + /** l1_cache_fail_int_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L1-DCache due to + * cpu accesses L1-DCache. + */ + uint32_t l1_cache_fail_int_ena:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} extmem_l1_cache_acs_fail_int_ena_reg_t; + +/** Type of l1_cache_acs_fail_int_clr register + * L1-Cache Access Fail Interrupt clear register + */ +typedef union { + struct { + /** l1_icache0_fail_int_clr : HRO; bitpos: [0]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to + * cpu accesses L1-ICache0. + */ + uint32_t l1_icache0_fail_int_clr:1; + /** l1_icache1_fail_int_clr : HRO; bitpos: [1]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to + * cpu accesses L1-ICache1. + */ + uint32_t l1_icache1_fail_int_clr:1; + /** l1_icache2_fail_int_clr : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_fail_int_clr:1; + /** l1_icache3_fail_int_clr : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_fail_int_clr:1; + /** l1_cache_fail_int_clr : WT; bitpos: [4]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L1-DCache due to + * cpu accesses L1-DCache. + */ + uint32_t l1_cache_fail_int_clr:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} extmem_l1_cache_acs_fail_int_clr_reg_t; + +/** Type of l1_cache_acs_fail_int_raw register + * Cache Access Fail Interrupt raw register + */ +typedef union { + struct { + /** l1_icache0_fail_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache0. + */ + uint32_t l1_icache0_fail_int_raw:1; + /** l1_icache1_fail_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache1. + */ + uint32_t l1_icache1_fail_int_raw:1; + /** l1_icache2_fail_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache2. + */ + uint32_t l1_icache2_fail_int_raw:1; + /** l1_icache3_fail_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-ICache3. + */ + uint32_t l1_icache3_fail_int_raw:1; + /** l1_cache_fail_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-DCache. + */ + uint32_t l1_cache_fail_int_raw:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} extmem_l1_cache_acs_fail_int_raw_reg_t; + +/** Type of l1_cache_acs_fail_int_st register + * Cache Access Fail Interrupt status register + */ +typedef union { + struct { + /** l1_icache0_fail_int_st : HRO; bitpos: [0]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due + * to cpu accesses L1-ICache. + */ + uint32_t l1_icache0_fail_int_st:1; + /** l1_icache1_fail_int_st : HRO; bitpos: [1]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due + * to cpu accesses L1-ICache. + */ + uint32_t l1_icache1_fail_int_st:1; + /** l1_icache2_fail_int_st : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_fail_int_st:1; + /** l1_icache3_fail_int_st : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_fail_int_st:1; + /** l1_cache_fail_int_st : RO; bitpos: [4]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L1-DCache due + * to cpu accesses L1-DCache. + */ + uint32_t l1_cache_fail_int_st:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} extmem_l1_cache_acs_fail_int_st_reg_t; + +/** Type of l1_cache_sync_preload_int_ena register + * L1-Cache Access Fail Interrupt enable register + */ +typedef union { + struct { + /** l1_icache0_pld_done_int_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload + * operation is done, interrupt occurs. + */ + uint32_t l1_icache0_pld_done_int_ena:1; + /** l1_icache1_pld_done_int_ena : HRO; bitpos: [1]; default: 0; + * The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload + * operation is done, interrupt occurs. + */ + uint32_t l1_icache1_pld_done_int_ena:1; + /** l1_icache2_pld_done_int_ena : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_done_int_ena:1; + /** l1_icache3_pld_done_int_ena : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_done_int_ena:1; + /** l1_cache_pld_done_int_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of L1-Cache preload-operation. If preload + * operation is done, interrupt occurs. + */ + uint32_t l1_cache_pld_done_int_ena:1; + uint32_t reserved_5:1; + /** cache_sync_done_int_ena : R/W; bitpos: [6]; default: 0; + * The bit is used to enable interrupt of Cache sync-operation done. + */ + uint32_t cache_sync_done_int_ena:1; + /** l1_icache0_pld_err_int_ena : HRO; bitpos: [7]; default: 0; + * The bit is used to enable interrupt of L1-ICache0 preload-operation error. + */ + uint32_t l1_icache0_pld_err_int_ena:1; + /** l1_icache1_pld_err_int_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable interrupt of L1-ICache1 preload-operation error. + */ + uint32_t l1_icache1_pld_err_int_ena:1; + /** l1_icache2_pld_err_int_ena : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_err_int_ena:1; + /** l1_icache3_pld_err_int_ena : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_err_int_ena:1; + /** l1_cache_pld_err_int_ena : R/W; bitpos: [11]; default: 0; + * The bit is used to enable interrupt of L1-Cache preload-operation error. + */ + uint32_t l1_cache_pld_err_int_ena:1; + uint32_t reserved_12:1; + /** cache_sync_err_int_ena : R/W; bitpos: [13]; default: 0; + * The bit is used to enable interrupt of Cache sync-operation error. + */ + uint32_t cache_sync_err_int_ena:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_cache_sync_preload_int_ena_reg_t; + +/** Type of l1_cache_sync_preload_int_clr register + * Sync Preload operation Interrupt clear register + */ +typedef union { + struct { + /** l1_icache0_pld_done_int_clr : HRO; bitpos: [0]; default: 0; + * The bit is used to clear interrupt that occurs only when L1-ICache0 + * preload-operation is done. + */ + uint32_t l1_icache0_pld_done_int_clr:1; + /** l1_icache1_pld_done_int_clr : HRO; bitpos: [1]; default: 0; + * The bit is used to clear interrupt that occurs only when L1-ICache1 + * preload-operation is done. + */ + uint32_t l1_icache1_pld_done_int_clr:1; + /** l1_icache2_pld_done_int_clr : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_done_int_clr:1; + /** l1_icache3_pld_done_int_clr : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_done_int_clr:1; + /** l1_cache_pld_done_int_clr : WT; bitpos: [4]; default: 0; + * The bit is used to clear interrupt that occurs only when L1-Cache preload-operation + * is done. + */ + uint32_t l1_cache_pld_done_int_clr:1; + uint32_t reserved_5:1; + /** cache_sync_done_int_clr : WT; bitpos: [6]; default: 0; + * The bit is used to clear interrupt that occurs only when Cache sync-operation is + * done. + */ + uint32_t cache_sync_done_int_clr:1; + /** l1_icache0_pld_err_int_clr : HRO; bitpos: [7]; default: 0; + * The bit is used to clear interrupt of L1-ICache0 preload-operation error. + */ + uint32_t l1_icache0_pld_err_int_clr:1; + /** l1_icache1_pld_err_int_clr : HRO; bitpos: [8]; default: 0; + * The bit is used to clear interrupt of L1-ICache1 preload-operation error. + */ + uint32_t l1_icache1_pld_err_int_clr:1; + /** l1_icache2_pld_err_int_clr : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_err_int_clr:1; + /** l1_icache3_pld_err_int_clr : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_err_int_clr:1; + /** l1_cache_pld_err_int_clr : WT; bitpos: [11]; default: 0; + * The bit is used to clear interrupt of L1-Cache preload-operation error. + */ + uint32_t l1_cache_pld_err_int_clr:1; + uint32_t reserved_12:1; + /** cache_sync_err_int_clr : WT; bitpos: [13]; default: 0; + * The bit is used to clear interrupt of Cache sync-operation error. + */ + uint32_t cache_sync_err_int_clr:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_cache_sync_preload_int_clr_reg_t; + +/** Type of l1_cache_sync_preload_int_raw register + * Sync Preload operation Interrupt raw register + */ +typedef union { + struct { + /** l1_icache0_pld_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is + * done. + */ + uint32_t l1_icache0_pld_done_int_raw:1; + /** l1_icache1_pld_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is + * done. + */ + uint32_t l1_icache1_pld_done_int_raw:1; + /** l1_icache2_pld_done_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_done_int_raw:1; + /** l1_icache3_pld_done_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_done_int_raw:1; + /** l1_cache_pld_done_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt that occurs only when L1-Cache preload-operation is + * done. + */ + uint32_t l1_cache_pld_done_int_raw:1; + uint32_t reserved_5:1; + /** cache_sync_done_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit of the interrupt that occurs only when Cache sync-operation is done. + */ + uint32_t cache_sync_done_int_raw:1; + /** l1_icache0_pld_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation + * error occurs. + */ + uint32_t l1_icache0_pld_err_int_raw:1; + /** l1_icache1_pld_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation + * error occurs. + */ + uint32_t l1_icache1_pld_err_int_raw:1; + /** l1_icache2_pld_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_err_int_raw:1; + /** l1_icache3_pld_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_err_int_raw:1; + /** l1_cache_pld_err_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit of the interrupt that occurs only when L1-Cache preload-operation error + * occurs. + */ + uint32_t l1_cache_pld_err_int_raw:1; + uint32_t reserved_12:1; + /** cache_sync_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit of the interrupt that occurs only when Cache sync-operation error + * occurs. + */ + uint32_t cache_sync_err_int_raw:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_cache_sync_preload_int_raw_reg_t; + +/** Type of l1_cache_sync_preload_int_st register + * L1-Cache Access Fail Interrupt status register + */ +typedef union { + struct { + /** l1_icache0_pld_done_int_st : HRO; bitpos: [0]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L1-ICache0 + * preload-operation is done. + */ + uint32_t l1_icache0_pld_done_int_st:1; + /** l1_icache1_pld_done_int_st : HRO; bitpos: [1]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L1-ICache1 + * preload-operation is done. + */ + uint32_t l1_icache1_pld_done_int_st:1; + /** l1_icache2_pld_done_int_st : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_done_int_st:1; + /** l1_icache3_pld_done_int_st : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_done_int_st:1; + /** l1_cache_pld_done_int_st : RO; bitpos: [4]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L1-Cache + * preload-operation is done. + */ + uint32_t l1_cache_pld_done_int_st:1; + uint32_t reserved_5:1; + /** cache_sync_done_int_st : RO; bitpos: [6]; default: 0; + * The bit indicates the status of the interrupt that occurs only when Cache + * sync-operation is done. + */ + uint32_t cache_sync_done_int_st:1; + /** l1_icache0_pld_err_int_st : HRO; bitpos: [7]; default: 0; + * The bit indicates the status of the interrupt of L1-ICache0 preload-operation error. + */ + uint32_t l1_icache0_pld_err_int_st:1; + /** l1_icache1_pld_err_int_st : HRO; bitpos: [8]; default: 0; + * The bit indicates the status of the interrupt of L1-ICache1 preload-operation error. + */ + uint32_t l1_icache1_pld_err_int_st:1; + /** l1_icache2_pld_err_int_st : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_err_int_st:1; + /** l1_icache3_pld_err_int_st : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_err_int_st:1; + /** l1_cache_pld_err_int_st : RO; bitpos: [11]; default: 0; + * The bit indicates the status of the interrupt of L1-Cache preload-operation error. + */ + uint32_t l1_cache_pld_err_int_st:1; + uint32_t reserved_12:1; + /** cache_sync_err_int_st : RO; bitpos: [13]; default: 0; + * The bit indicates the status of the interrupt of Cache sync-operation error. + */ + uint32_t cache_sync_err_int_st:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_cache_sync_preload_int_st_reg_t; + +/** Type of l2_cache_acs_cnt_int_ena register + * Cache Access Counter Interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** l2_ibus0_ovf_int_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ + uint32_t l2_ibus0_ovf_int_ena:1; + /** l2_ibus1_ovf_int_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ + uint32_t l2_ibus1_ovf_int_ena:1; + /** l2_ibus2_ovf_int_ena : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l2_ibus2_ovf_int_ena:1; + /** l2_ibus3_ovf_int_ena : HRO; bitpos: [11]; default: 0; + * Reserved + */ + uint32_t l2_ibus3_ovf_int_ena:1; + /** l2_dbus0_ovf_int_ena : HRO; bitpos: [12]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ + uint32_t l2_dbus0_ovf_int_ena:1; + /** l2_dbus1_ovf_int_ena : HRO; bitpos: [13]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ + uint32_t l2_dbus1_ovf_int_ena:1; + /** l2_dbus2_ovf_int_ena : HRO; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t l2_dbus2_ovf_int_ena:1; + /** l2_dbus3_ovf_int_ena : HRO; bitpos: [15]; default: 0; + * Reserved + */ + uint32_t l2_dbus3_ovf_int_ena:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} extmem_l2_cache_acs_cnt_int_ena_reg_t; + +/** Type of l2_cache_acs_cnt_int_clr register + * Cache Access Counter Interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** l2_ibus0_ovf_int_clr : HRO; bitpos: [8]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus0 accesses L2-Cache. + */ + uint32_t l2_ibus0_ovf_int_clr:1; + /** l2_ibus1_ovf_int_clr : HRO; bitpos: [9]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus1 accesses L2-Cache. + */ + uint32_t l2_ibus1_ovf_int_clr:1; + /** l2_ibus2_ovf_int_clr : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l2_ibus2_ovf_int_clr:1; + /** l2_ibus3_ovf_int_clr : HRO; bitpos: [11]; default: 0; + * Reserved + */ + uint32_t l2_ibus3_ovf_int_clr:1; + /** l2_dbus0_ovf_int_clr : HRO; bitpos: [12]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus0 accesses L2-Cache. + */ + uint32_t l2_dbus0_ovf_int_clr:1; + /** l2_dbus1_ovf_int_clr : HRO; bitpos: [13]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L2-Cache due + * to bus1 accesses L2-Cache. + */ + uint32_t l2_dbus1_ovf_int_clr:1; + /** l2_dbus2_ovf_int_clr : HRO; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t l2_dbus2_ovf_int_clr:1; + /** l2_dbus3_ovf_int_clr : HRO; bitpos: [15]; default: 0; + * Reserved + */ + uint32_t l2_dbus3_ovf_int_clr:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} extmem_l2_cache_acs_cnt_int_clr_reg_t; + +/** Type of l2_cache_acs_cnt_int_raw register + * Cache Access Counter Interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** l2_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus0 accesses L2-ICache0. + */ + uint32_t l2_ibus0_ovf_int_raw:1; + /** l2_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus1 accesses L2-ICache1. + */ + uint32_t l2_ibus1_ovf_int_raw:1; + /** l2_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus2 accesses L2-ICache2. + */ + uint32_t l2_ibus2_ovf_int_raw:1; + /** l2_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus3 accesses L2-ICache3. + */ + uint32_t l2_ibus3_ovf_int_raw:1; + /** l2_dbus0_ovf_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus0 accesses L2-DCache. + */ + uint32_t l2_dbus0_ovf_int_raw:1; + /** l2_dbus1_ovf_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus1 accesses L2-DCache. + */ + uint32_t l2_dbus1_ovf_int_raw:1; + /** l2_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus2 accesses L2-DCache. + */ + uint32_t l2_dbus2_ovf_int_raw:1; + /** l2_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache + * due to bus3 accesses L2-DCache. + */ + uint32_t l2_dbus3_ovf_int_raw:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} extmem_l2_cache_acs_cnt_int_raw_reg_t; + +/** Type of l2_cache_acs_cnt_int_st register + * Cache Access Counter Interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** l2_ibus0_ovf_int_st : HRO; bitpos: [8]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ + uint32_t l2_ibus0_ovf_int_st:1; + /** l2_ibus1_ovf_int_st : HRO; bitpos: [9]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ + uint32_t l2_ibus1_ovf_int_st:1; + /** l2_ibus2_ovf_int_st : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l2_ibus2_ovf_int_st:1; + /** l2_ibus3_ovf_int_st : HRO; bitpos: [11]; default: 0; + * Reserved + */ + uint32_t l2_ibus3_ovf_int_st:1; + /** l2_dbus0_ovf_int_st : HRO; bitpos: [12]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus0 accesses L2-Cache. + */ + uint32_t l2_dbus0_ovf_int_st:1; + /** l2_dbus1_ovf_int_st : HRO; bitpos: [13]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L2-Cache due to bus1 accesses L2-Cache. + */ + uint32_t l2_dbus1_ovf_int_st:1; + /** l2_dbus2_ovf_int_st : HRO; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t l2_dbus2_ovf_int_st:1; + /** l2_dbus3_ovf_int_st : HRO; bitpos: [15]; default: 0; + * Reserved + */ + uint32_t l2_dbus3_ovf_int_st:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} extmem_l2_cache_acs_cnt_int_st_reg_t; + +/** Type of l2_cache_acs_fail_int_ena register + * Cache Access Fail Interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_fail_int_ena : HRO; bitpos: [5]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L2-Cache due to + * l1 cache accesses L2-Cache. + */ + uint32_t l2_cache_fail_int_ena:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_cache_acs_fail_int_ena_reg_t; + +/** Type of l2_cache_acs_fail_int_clr register + * L1-Cache Access Fail Interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_fail_int_clr : HRO; bitpos: [5]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1 + * cache accesses L2-Cache. + */ + uint32_t l2_cache_fail_int_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_cache_acs_fail_int_clr_reg_t; + +/** Type of l2_cache_acs_fail_int_raw register + * Cache Access Fail Interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_fail_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L2-Cache. + */ + uint32_t l2_cache_fail_int_raw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_cache_acs_fail_int_raw_reg_t; + +/** Type of l2_cache_acs_fail_int_st register + * Cache Access Fail Interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_fail_int_st : HRO; bitpos: [5]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L2-Cache due + * to l1 cache accesses L2-Cache. + */ + uint32_t l2_cache_fail_int_st:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_cache_acs_fail_int_st_reg_t; + +/** Type of l2_cache_sync_preload_int_ena register + * L1-Cache Access Fail Interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_pld_done_int_ena : HRO; bitpos: [5]; default: 0; + * The bit is used to enable interrupt of L2-Cache preload-operation done. + */ + uint32_t l2_cache_pld_done_int_ena:1; + uint32_t reserved_6:6; + /** l2_cache_pld_err_int_ena : HRO; bitpos: [12]; default: 0; + * The bit is used to enable interrupt of L2-Cache preload-operation error. + */ + uint32_t l2_cache_pld_err_int_ena:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} extmem_l2_cache_sync_preload_int_ena_reg_t; + +/** Type of l2_cache_sync_preload_int_clr register + * Sync Preload operation Interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_pld_done_int_clr : HRO; bitpos: [5]; default: 0; + * The bit is used to clear interrupt that occurs only when L2-Cache preload-operation + * is done. + */ + uint32_t l2_cache_pld_done_int_clr:1; + uint32_t reserved_6:6; + /** l2_cache_pld_err_int_clr : HRO; bitpos: [12]; default: 0; + * The bit is used to clear interrupt of L2-Cache preload-operation error. + */ + uint32_t l2_cache_pld_err_int_clr:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} extmem_l2_cache_sync_preload_int_clr_reg_t; + +/** Type of l2_cache_sync_preload_int_raw register + * Sync Preload operation Interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_pld_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit of the interrupt that occurs only when L2-Cache preload-operation is + * done. + */ + uint32_t l2_cache_pld_done_int_raw:1; + uint32_t reserved_6:6; + /** l2_cache_pld_err_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit of the interrupt that occurs only when L2-Cache preload-operation error + * occurs. + */ + uint32_t l2_cache_pld_err_int_raw:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} extmem_l2_cache_sync_preload_int_raw_reg_t; + +/** Type of l2_cache_sync_preload_int_st register + * L1-Cache Access Fail Interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_pld_done_int_st : HRO; bitpos: [5]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L2-Cache + * preload-operation is done. + */ + uint32_t l2_cache_pld_done_int_st:1; + uint32_t reserved_6:6; + /** l2_cache_pld_err_int_st : HRO; bitpos: [12]; default: 0; + * The bit indicates the status of the interrupt of L2-Cache preload-operation error. + */ + uint32_t l2_cache_pld_err_int_st:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} extmem_l2_cache_sync_preload_int_st_reg_t; + + +/** Group: Access Statistics registers */ +/** Type of l1_cache_acs_cnt_ctrl register + * Cache Access Counter enable and clear register + */ +typedef union { + struct { + /** l1_ibus0_cnt_ena : HRO; bitpos: [0]; default: 0; + * The bit is used to enable ibus0 counter in L1-ICache0. + */ + uint32_t l1_ibus0_cnt_ena:1; + /** l1_ibus1_cnt_ena : HRO; bitpos: [1]; default: 0; + * The bit is used to enable ibus1 counter in L1-ICache1. + */ + uint32_t l1_ibus1_cnt_ena:1; + /** l1_ibus2_cnt_ena : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_ibus2_cnt_ena:1; + /** l1_ibus3_cnt_ena : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_ibus3_cnt_ena:1; + /** l1_bus0_cnt_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable dbus0 counter in L1-DCache. + */ + uint32_t l1_bus0_cnt_ena:1; + /** l1_bus1_cnt_ena : R/W; bitpos: [5]; default: 0; + * The bit is used to enable dbus1 counter in L1-DCache. + */ + uint32_t l1_bus1_cnt_ena:1; + /** l1_dbus2_cnt_ena : HRO; bitpos: [6]; default: 0; + * Reserved + */ + uint32_t l1_dbus2_cnt_ena:1; + /** l1_dbus3_cnt_ena : HRO; bitpos: [7]; default: 0; + * Reserved + */ + uint32_t l1_dbus3_cnt_ena:1; + uint32_t reserved_8:8; + /** l1_ibus0_cnt_clr : HRO; bitpos: [16]; default: 0; + * The bit is used to clear ibus0 counter in L1-ICache0. + */ + uint32_t l1_ibus0_cnt_clr:1; + /** l1_ibus1_cnt_clr : HRO; bitpos: [17]; default: 0; + * The bit is used to clear ibus1 counter in L1-ICache1. + */ + uint32_t l1_ibus1_cnt_clr:1; + /** l1_ibus2_cnt_clr : HRO; bitpos: [18]; default: 0; + * Reserved + */ + uint32_t l1_ibus2_cnt_clr:1; + /** l1_ibus3_cnt_clr : HRO; bitpos: [19]; default: 0; + * Reserved + */ + uint32_t l1_ibus3_cnt_clr:1; + /** l1_bus0_cnt_clr : WT; bitpos: [20]; default: 0; + * The bit is used to clear dbus0 counter in L1-DCache. + */ + uint32_t l1_bus0_cnt_clr:1; + /** l1_bus1_cnt_clr : WT; bitpos: [21]; default: 0; + * The bit is used to clear dbus1 counter in L1-DCache. + */ + uint32_t l1_bus1_cnt_clr:1; + /** l1_dbus2_cnt_clr : HRO; bitpos: [22]; default: 0; + * Reserved + */ + uint32_t l1_dbus2_cnt_clr:1; + /** l1_dbus3_cnt_clr : HRO; bitpos: [23]; default: 0; + * Reserved + */ + uint32_t l1_dbus3_cnt_clr:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} extmem_l1_cache_acs_cnt_ctrl_reg_t; + +/** Type of l1_ibus0_acs_hit_cnt register + * L1-ICache bus0 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_hit_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus0_acs_hit_cnt_reg_t; + +/** Type of l1_ibus0_acs_miss_cnt register + * L1-ICache bus0 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_miss_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus0_acs_miss_cnt_reg_t; + +/** Type of l1_ibus0_acs_conflict_cnt register + * L1-ICache bus0 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus0 accesses L1-ICache0. + */ + uint32_t l1_ibus0_conflict_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus0_acs_conflict_cnt_reg_t; + +/** Type of l1_ibus0_acs_nxtlvl_cnt register + * L1-ICache bus0 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus0 accessing L1-ICache0. + */ + uint32_t l1_ibus0_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus0_acs_nxtlvl_cnt_reg_t; + +/** Type of l1_ibus1_acs_hit_cnt register + * L1-ICache bus1 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_hit_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus1_acs_hit_cnt_reg_t; + +/** Type of l1_ibus1_acs_miss_cnt register + * L1-ICache bus1 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_miss_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus1_acs_miss_cnt_reg_t; + +/** Type of l1_ibus1_acs_conflict_cnt register + * L1-ICache bus1 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus1 accesses L1-ICache1. + */ + uint32_t l1_ibus1_conflict_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus1_acs_conflict_cnt_reg_t; + +/** Type of l1_ibus1_acs_nxtlvl_cnt register + * L1-ICache bus1 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus1 accessing L1-ICache1. + */ + uint32_t l1_ibus1_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus1_acs_nxtlvl_cnt_reg_t; + +/** Type of l1_ibus2_acs_hit_cnt register + * L1-ICache bus2 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus2 accesses L1-ICache2. + */ + uint32_t l1_ibus2_hit_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus2_acs_hit_cnt_reg_t; + +/** Type of l1_ibus2_acs_miss_cnt register + * L1-ICache bus2 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus2 accesses L1-ICache2. + */ + uint32_t l1_ibus2_miss_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus2_acs_miss_cnt_reg_t; + +/** Type of l1_ibus2_acs_conflict_cnt register + * L1-ICache bus2 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus2 accesses L1-ICache2. + */ + uint32_t l1_ibus2_conflict_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus2_acs_conflict_cnt_reg_t; + +/** Type of l1_ibus2_acs_nxtlvl_cnt register + * L1-ICache bus2 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus2 accessing L1-ICache2. + */ + uint32_t l1_ibus2_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus2_acs_nxtlvl_cnt_reg_t; + +/** Type of l1_ibus3_acs_hit_cnt register + * L1-ICache bus3 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus3 accesses L1-ICache3. + */ + uint32_t l1_ibus3_hit_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus3_acs_hit_cnt_reg_t; + +/** Type of l1_ibus3_acs_miss_cnt register + * L1-ICache bus3 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus3 accesses L1-ICache3. + */ + uint32_t l1_ibus3_miss_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus3_acs_miss_cnt_reg_t; + +/** Type of l1_ibus3_acs_conflict_cnt register + * L1-ICache bus3 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus3 accesses L1-ICache3. + */ + uint32_t l1_ibus3_conflict_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus3_acs_conflict_cnt_reg_t; + +/** Type of l1_ibus3_acs_nxtlvl_cnt register + * L1-ICache bus3 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-ICache accesses L2-Cache due to + * bus3 accessing L1-ICache3. + */ + uint32_t l1_ibus3_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l1_ibus3_acs_nxtlvl_cnt_reg_t; + +/** Type of l1_bus0_acs_hit_cnt register + * L1-Cache bus0 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus0 accesses L1-Cache. + */ + uint32_t l1_bus0_hit_cnt:32; + }; + uint32_t val; +} extmem_l1_bus0_acs_hit_cnt_reg_t; + +/** Type of l1_bus0_acs_miss_cnt register + * L1-Cache bus0 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus0 accesses L1-Cache. + */ + uint32_t l1_bus0_miss_cnt:32; + }; + uint32_t val; +} extmem_l1_bus0_acs_miss_cnt_reg_t; + +/** Type of l1_bus0_acs_conflict_cnt register + * L1-Cache bus0 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus0 accesses L1-Cache. + */ + uint32_t l1_bus0_conflict_cnt:32; + }; + uint32_t val; +} extmem_l1_bus0_acs_conflict_cnt_reg_t; + +/** Type of l1_bus0_acs_nxtlvl_cnt register + * L1-Cache bus0 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus0 accessing L1-Cache. + */ + uint32_t l1_bus0_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l1_bus0_acs_nxtlvl_cnt_reg_t; + +/** Type of l1_bus1_acs_hit_cnt register + * L1-Cache bus1 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_bus1_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus1 accesses L1-Cache. + */ + uint32_t l1_bus1_hit_cnt:32; + }; + uint32_t val; +} extmem_l1_bus1_acs_hit_cnt_reg_t; + +/** Type of l1_bus1_acs_miss_cnt register + * L1-Cache bus1 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_bus1_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus1 accesses L1-Cache. + */ + uint32_t l1_bus1_miss_cnt:32; + }; + uint32_t val; +} extmem_l1_bus1_acs_miss_cnt_reg_t; + +/** Type of l1_bus1_acs_conflict_cnt register + * L1-Cache bus1 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_bus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus1 accesses L1-Cache. + */ + uint32_t l1_bus1_conflict_cnt:32; + }; + uint32_t val; +} extmem_l1_bus1_acs_conflict_cnt_reg_t; + +/** Type of l1_bus1_acs_nxtlvl_cnt register + * L1-Cache bus1 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_bus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus1 accessing L1-Cache. + */ + uint32_t l1_bus1_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l1_bus1_acs_nxtlvl_cnt_reg_t; + +/** Type of l1_dbus2_acs_hit_cnt register + * L1-DCache bus2 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus2 accesses L1-DCache. + */ + uint32_t l1_dbus2_hit_cnt:32; + }; + uint32_t val; +} extmem_l1_dbus2_acs_hit_cnt_reg_t; + +/** Type of l1_dbus2_acs_miss_cnt register + * L1-DCache bus2 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus2 accesses L1-DCache. + */ + uint32_t l1_dbus2_miss_cnt:32; + }; + uint32_t val; +} extmem_l1_dbus2_acs_miss_cnt_reg_t; + +/** Type of l1_dbus2_acs_conflict_cnt register + * L1-DCache bus2 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus2 accesses L1-DCache. + */ + uint32_t l1_dbus2_conflict_cnt:32; + }; + uint32_t val; +} extmem_l1_dbus2_acs_conflict_cnt_reg_t; + +/** Type of l1_dbus2_acs_nxtlvl_cnt register + * L1-DCache bus2 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-DCache accesses L2-Cache due to + * bus2 accessing L1-DCache. + */ + uint32_t l1_dbus2_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l1_dbus2_acs_nxtlvl_cnt_reg_t; + +/** Type of l1_dbus3_acs_hit_cnt register + * L1-DCache bus3 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus3 accesses L1-DCache. + */ + uint32_t l1_dbus3_hit_cnt:32; + }; + uint32_t val; +} extmem_l1_dbus3_acs_hit_cnt_reg_t; + +/** Type of l1_dbus3_acs_miss_cnt register + * L1-DCache bus3 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus3 accesses L1-DCache. + */ + uint32_t l1_dbus3_miss_cnt:32; + }; + uint32_t val; +} extmem_l1_dbus3_acs_miss_cnt_reg_t; + +/** Type of l1_dbus3_acs_conflict_cnt register + * L1-DCache bus3 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus3 accesses L1-DCache. + */ + uint32_t l1_dbus3_conflict_cnt:32; + }; + uint32_t val; +} extmem_l1_dbus3_acs_conflict_cnt_reg_t; + +/** Type of l1_dbus3_acs_nxtlvl_cnt register + * L1-DCache bus3 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-DCache accesses L2-Cache due to + * bus3 accessing L1-DCache. + */ + uint32_t l1_dbus3_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l1_dbus3_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_cache_acs_cnt_ctrl register + * Cache Access Counter enable and clear register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** l2_ibus0_cnt_ena : HRO; bitpos: [8]; default: 0; + * The bit is used to enable ibus0 counter in L2-Cache. + */ + uint32_t l2_ibus0_cnt_ena:1; + /** l2_ibus1_cnt_ena : HRO; bitpos: [9]; default: 0; + * The bit is used to enable ibus1 counter in L2-Cache. + */ + uint32_t l2_ibus1_cnt_ena:1; + /** l2_ibus2_cnt_ena : HRO; bitpos: [10]; default: 0; + * Reserved + */ + uint32_t l2_ibus2_cnt_ena:1; + /** l2_ibus3_cnt_ena : HRO; bitpos: [11]; default: 0; + * Reserved + */ + uint32_t l2_ibus3_cnt_ena:1; + /** l2_dbus0_cnt_ena : HRO; bitpos: [12]; default: 0; + * The bit is used to enable dbus0 counter in L2-Cache. + */ + uint32_t l2_dbus0_cnt_ena:1; + /** l2_dbus1_cnt_ena : HRO; bitpos: [13]; default: 0; + * The bit is used to enable dbus1 counter in L2-Cache. + */ + uint32_t l2_dbus1_cnt_ena:1; + /** l2_dbus2_cnt_ena : HRO; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t l2_dbus2_cnt_ena:1; + /** l2_dbus3_cnt_ena : HRO; bitpos: [15]; default: 0; + * Reserved + */ + uint32_t l2_dbus3_cnt_ena:1; + uint32_t reserved_16:8; + /** l2_ibus0_cnt_clr : HRO; bitpos: [24]; default: 0; + * The bit is used to clear ibus0 counter in L2-Cache. + */ + uint32_t l2_ibus0_cnt_clr:1; + /** l2_ibus1_cnt_clr : HRO; bitpos: [25]; default: 0; + * The bit is used to clear ibus1 counter in L2-Cache. + */ + uint32_t l2_ibus1_cnt_clr:1; + /** l2_ibus2_cnt_clr : HRO; bitpos: [26]; default: 0; + * Reserved + */ + uint32_t l2_ibus2_cnt_clr:1; + /** l2_ibus3_cnt_clr : HRO; bitpos: [27]; default: 0; + * Reserved + */ + uint32_t l2_ibus3_cnt_clr:1; + /** l2_dbus0_cnt_clr : HRO; bitpos: [28]; default: 0; + * The bit is used to clear dbus0 counter in L2-Cache. + */ + uint32_t l2_dbus0_cnt_clr:1; + /** l2_dbus1_cnt_clr : HRO; bitpos: [29]; default: 0; + * The bit is used to clear dbus1 counter in L2-Cache. + */ + uint32_t l2_dbus1_cnt_clr:1; + /** l2_dbus2_cnt_clr : HRO; bitpos: [30]; default: 0; + * Reserved + */ + uint32_t l2_dbus2_cnt_clr:1; + /** l2_dbus3_cnt_clr : HRO; bitpos: [31]; default: 0; + * Reserved + */ + uint32_t l2_dbus3_cnt_clr:1; + }; + uint32_t val; +} extmem_l2_cache_acs_cnt_ctrl_reg_t; + +/** Type of l2_ibus0_acs_hit_cnt register + * L2-Cache bus0 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache0 accesses L2-Cache due to + * bus0 accessing L1-ICache0. + */ + uint32_t l2_ibus0_hit_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus0_acs_hit_cnt_reg_t; + +/** Type of l2_ibus0_acs_miss_cnt register + * L2-Cache bus0 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache0 accesses L2-Cache due to + * bus0 accessing L1-ICache0. + */ + uint32_t l2_ibus0_miss_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus0_acs_miss_cnt_reg_t; + +/** Type of l2_ibus0_acs_conflict_cnt register + * L2-Cache bus0 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache0 accesses + * L2-Cache due to bus0 accessing L1-ICache0. + */ + uint32_t l2_ibus0_conflict_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus0_acs_conflict_cnt_reg_t; + +/** Type of l2_ibus0_acs_nxtlvl_cnt register + * L2-Cache bus0 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0. + */ + uint32_t l2_ibus0_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus0_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_ibus1_acs_hit_cnt register + * L2-Cache bus1 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache1 accesses L2-Cache due to + * bus1 accessing L1-ICache1. + */ + uint32_t l2_ibus1_hit_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus1_acs_hit_cnt_reg_t; + +/** Type of l2_ibus1_acs_miss_cnt register + * L2-Cache bus1 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache1 accesses L2-Cache due to + * bus1 accessing L1-ICache1. + */ + uint32_t l2_ibus1_miss_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus1_acs_miss_cnt_reg_t; + +/** Type of l2_ibus1_acs_conflict_cnt register + * L2-Cache bus1 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache1 accesses + * L2-Cache due to bus1 accessing L1-ICache1. + */ + uint32_t l2_ibus1_conflict_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus1_acs_conflict_cnt_reg_t; + +/** Type of l2_ibus1_acs_nxtlvl_cnt register + * L2-Cache bus1 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1. + */ + uint32_t l2_ibus1_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus1_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_ibus2_acs_hit_cnt register + * L2-Cache bus2 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache2 accesses L2-Cache due to + * bus2 accessing L1-ICache2. + */ + uint32_t l2_ibus2_hit_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus2_acs_hit_cnt_reg_t; + +/** Type of l2_ibus2_acs_miss_cnt register + * L2-Cache bus2 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache2 accesses L2-Cache due to + * bus2 accessing L1-ICache2. + */ + uint32_t l2_ibus2_miss_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus2_acs_miss_cnt_reg_t; + +/** Type of l2_ibus2_acs_conflict_cnt register + * L2-Cache bus2 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache2 accesses + * L2-Cache due to bus2 accessing L1-ICache2. + */ + uint32_t l2_ibus2_conflict_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus2_acs_conflict_cnt_reg_t; + +/** Type of l2_ibus2_acs_nxtlvl_cnt register + * L2-Cache bus2 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2. + */ + uint32_t l2_ibus2_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus2_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_ibus3_acs_hit_cnt register + * L2-Cache bus3 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-ICache3 accesses L2-Cache due to + * bus3 accessing L1-ICache3. + */ + uint32_t l2_ibus3_hit_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus3_acs_hit_cnt_reg_t; + +/** Type of l2_ibus3_acs_miss_cnt register + * L2-Cache bus3 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-ICache3 accesses L2-Cache due to + * bus3 accessing L1-ICache3. + */ + uint32_t l2_ibus3_miss_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus3_acs_miss_cnt_reg_t; + +/** Type of l2_ibus3_acs_conflict_cnt register + * L2-Cache bus3 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-ICache3 accesses + * L2-Cache due to bus3 accessing L1-ICache3. + */ + uint32_t l2_ibus3_conflict_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus3_acs_conflict_cnt_reg_t; + +/** Type of l2_ibus3_acs_nxtlvl_cnt register + * L2-Cache bus3 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3. + */ + uint32_t l2_ibus3_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l2_ibus3_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_dbus0_acs_hit_cnt register + * L2-Cache bus0 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_dbus0_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus0 accessing L1-DCache. + */ + uint32_t l2_dbus0_hit_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus0_acs_hit_cnt_reg_t; + +/** Type of l2_dbus0_acs_miss_cnt register + * L2-Cache bus0 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_dbus0_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus0 accessing L1-DCache. + */ + uint32_t l2_dbus0_miss_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus0_acs_miss_cnt_reg_t; + +/** Type of l2_dbus0_acs_conflict_cnt register + * L2-Cache bus0 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_dbus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus0 accessing L1-DCache. + */ + uint32_t l2_dbus0_conflict_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus0_acs_conflict_cnt_reg_t; + +/** Type of l2_dbus0_acs_nxtlvl_cnt register + * L2-Cache bus0 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_dbus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache. + */ + uint32_t l2_dbus0_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus0_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_dbus1_acs_hit_cnt register + * L2-Cache bus1 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_dbus1_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus1 accessing L1-DCache. + */ + uint32_t l2_dbus1_hit_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus1_acs_hit_cnt_reg_t; + +/** Type of l2_dbus1_acs_miss_cnt register + * L2-Cache bus1 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_dbus1_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus1 accessing L1-DCache. + */ + uint32_t l2_dbus1_miss_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus1_acs_miss_cnt_reg_t; + +/** Type of l2_dbus1_acs_conflict_cnt register + * L2-Cache bus1 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_dbus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus1 accessing L1-DCache. + */ + uint32_t l2_dbus1_conflict_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus1_acs_conflict_cnt_reg_t; + +/** Type of l2_dbus1_acs_nxtlvl_cnt register + * L2-Cache bus1 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_dbus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache. + */ + uint32_t l2_dbus1_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus1_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_dbus2_acs_hit_cnt register + * L2-Cache bus2 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus2 accessing L1-DCache. + */ + uint32_t l2_dbus2_hit_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus2_acs_hit_cnt_reg_t; + +/** Type of l2_dbus2_acs_miss_cnt register + * L2-Cache bus2 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus2 accessing L1-DCache. + */ + uint32_t l2_dbus2_miss_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus2_acs_miss_cnt_reg_t; + +/** Type of l2_dbus2_acs_conflict_cnt register + * L2-Cache bus2 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus2 accessing L1-DCache. + */ + uint32_t l2_dbus2_conflict_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus2_acs_conflict_cnt_reg_t; + +/** Type of l2_dbus2_acs_nxtlvl_cnt register + * L2-Cache bus2 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache. + */ + uint32_t l2_dbus2_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus2_acs_nxtlvl_cnt_reg_t; + +/** Type of l2_dbus3_acs_hit_cnt register + * L2-Cache bus3 Hit-Access Counter register + */ +typedef union { + struct { + /** l2_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when L1-DCache accesses L2-Cache due to + * bus3 accessing L1-DCache. + */ + uint32_t l2_dbus3_hit_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus3_acs_hit_cnt_reg_t; + +/** Type of l2_dbus3_acs_miss_cnt register + * L2-Cache bus3 Miss-Access Counter register + */ +typedef union { + struct { + /** l2_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when L1-DCache accesses L2-Cache due to + * bus3 accessing L1-DCache. + */ + uint32_t l2_dbus3_miss_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus3_acs_miss_cnt_reg_t; + +/** Type of l2_dbus3_acs_conflict_cnt register + * L2-Cache bus3 Conflict-Access Counter register + */ +typedef union { + struct { + /** l2_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when L1-DCache accesses + * L2-Cache due to bus3 accessing L1-DCache. + */ + uint32_t l2_dbus3_conflict_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus3_acs_conflict_cnt_reg_t; + +/** Type of l2_dbus3_acs_nxtlvl_cnt register + * L2-Cache bus3 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l2_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L2-Cache accesses external memory due + * to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache. + */ + uint32_t l2_dbus3_nxtlvl_cnt:32; + }; + uint32_t val; +} extmem_l2_dbus3_acs_nxtlvl_cnt_reg_t; + + +/** Group: Access Fail Debug registers */ +/** Type of l1_icache0_acs_fail_id_attr register + * L1-ICache0 Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_icache0_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache0 accesses L1-ICache. + */ + uint32_t l1_icache0_fail_id:16; + /** l1_icache0_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache0 accesses L1-ICache. + */ + uint32_t l1_icache0_fail_attr:16; + }; + uint32_t val; +} extmem_l1_icache0_acs_fail_id_attr_reg_t; + +/** Type of l1_icache0_acs_fail_addr register + * L1-ICache0 Access Fail Address information register + */ +typedef union { + struct { + /** l1_icache0_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache0 accesses L1-ICache. + */ + uint32_t l1_icache0_fail_addr:32; + }; + uint32_t val; +} extmem_l1_icache0_acs_fail_addr_reg_t; + +/** Type of l1_icache1_acs_fail_id_attr register + * L1-ICache0 Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_icache1_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache1 accesses L1-ICache. + */ + uint32_t l1_icache1_fail_id:16; + /** l1_icache1_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache1 accesses L1-ICache. + */ + uint32_t l1_icache1_fail_attr:16; + }; + uint32_t val; +} extmem_l1_icache1_acs_fail_id_attr_reg_t; + +/** Type of l1_icache1_acs_fail_addr register + * L1-ICache0 Access Fail Address information register + */ +typedef union { + struct { + /** l1_icache1_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache1 accesses L1-ICache. + */ + uint32_t l1_icache1_fail_addr:32; + }; + uint32_t val; +} extmem_l1_icache1_acs_fail_addr_reg_t; + +/** Type of l1_icache2_acs_fail_id_attr register + * L1-ICache0 Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_icache2_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache2 accesses L1-ICache. + */ + uint32_t l1_icache2_fail_id:16; + /** l1_icache2_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache2 accesses L1-ICache. + */ + uint32_t l1_icache2_fail_attr:16; + }; + uint32_t val; +} extmem_l1_icache2_acs_fail_id_attr_reg_t; + +/** Type of l1_icache2_acs_fail_addr register + * L1-ICache0 Access Fail Address information register + */ +typedef union { + struct { + /** l1_icache2_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache2 accesses L1-ICache. + */ + uint32_t l1_icache2_fail_addr:32; + }; + uint32_t val; +} extmem_l1_icache2_acs_fail_addr_reg_t; + +/** Type of l1_icache3_acs_fail_id_attr register + * L1-ICache0 Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_icache3_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache3 accesses L1-ICache. + */ + uint32_t l1_icache3_fail_id:16; + /** l1_icache3_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache3 accesses L1-ICache. + */ + uint32_t l1_icache3_fail_attr:16; + }; + uint32_t val; +} extmem_l1_icache3_acs_fail_id_attr_reg_t; + +/** Type of l1_icache3_acs_fail_addr register + * L1-ICache0 Access Fail Address information register + */ +typedef union { + struct { + /** l1_icache3_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache3 accesses L1-ICache. + */ + uint32_t l1_icache3_fail_addr:32; + }; + uint32_t val; +} extmem_l1_icache3_acs_fail_addr_reg_t; + +/** Type of l1_cache_acs_fail_id_attr register + * L1-Cache Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_cache_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache accesses L1-Cache. + */ + uint32_t l1_cache_fail_id:16; + /** l1_cache_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache accesses L1-Cache. + */ + uint32_t l1_cache_fail_attr:16; + }; + uint32_t val; +} extmem_l1_cache_acs_fail_id_attr_reg_t; + +/** Type of l1_dcache_acs_fail_addr register + * L1-Cache Access Fail Address information register + */ +typedef union { + struct { + /** l1_cache_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache accesses L1-Cache. + */ + uint32_t l1_cache_fail_addr:32; + }; + uint32_t val; +} extmem_l1_dcache_acs_fail_addr_reg_t; + +/** Type of l2_cache_acs_fail_id_attr register + * L2-Cache Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l2_cache_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when L1-Cache accesses L2-Cache. + */ + uint32_t l2_cache_fail_id:16; + /** l2_cache_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when L1-Cache accesses L2-Cache + * due to cache accessing L1-Cache. + */ + uint32_t l2_cache_fail_attr:16; + }; + uint32_t val; +} extmem_l2_cache_acs_fail_id_attr_reg_t; + +/** Type of l2_cache_acs_fail_addr register + * L2-Cache Access Fail Address information register + */ +typedef union { + struct { + /** l2_cache_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when L1-Cache accesses L2-Cache. + */ + uint32_t l2_cache_fail_addr:32; + }; + uint32_t val; +} extmem_l2_cache_acs_fail_addr_reg_t; + + +/** Group: Operation Exception registers */ +/** Type of l1_cache_sync_preload_exception register + * Cache Sync/Preload Operation exception register + */ +typedef union { + struct { + /** l1_icache0_pld_err_code : RO; bitpos: [1:0]; default: 0; + * The value 2 is Only available which means preload size is error in L1-ICache0. + */ + uint32_t l1_icache0_pld_err_code:2; + /** l1_icache1_pld_err_code : RO; bitpos: [3:2]; default: 0; + * The value 2 is Only available which means preload size is error in L1-ICache1. + */ + uint32_t l1_icache1_pld_err_code:2; + /** l1_icache2_pld_err_code : RO; bitpos: [5:4]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_err_code:2; + /** l1_icache3_pld_err_code : RO; bitpos: [7:6]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_err_code:2; + /** l1_cache_pld_err_code : RO; bitpos: [9:8]; default: 0; + * The value 2 is Only available which means preload size is error in L1-Cache. + */ + uint32_t l1_cache_pld_err_code:2; + uint32_t reserved_10:2; + /** cache_sync_err_code : RO; bitpos: [13:12]; default: 0; + * The values 0-2 are available which means sync map, command conflict and size are + * error in Cache System. + */ + uint32_t cache_sync_err_code:2; + uint32_t reserved_14:18; + }; + uint32_t val; +} extmem_l1_cache_sync_preload_exception_reg_t; + +/** Type of l2_cache_sync_preload_exception register + * Cache Sync/Preload Operation exception register + */ +typedef union { + struct { + uint32_t reserved_0:10; + /** l2_cache_pld_err_code : RO; bitpos: [11:10]; default: 0; + * The value 2 is Only available which means preload size is error in L2-Cache. + */ + uint32_t l2_cache_pld_err_code:2; + uint32_t reserved_12:20; + }; + uint32_t val; +} extmem_l2_cache_sync_preload_exception_reg_t; + + +/** Group: Sync Reset control and configuration registers */ +/** Type of l1_cache_sync_rst_ctrl register + * Cache Sync Reset control register + */ +typedef union { + struct { + /** l1_icache0_sync_rst : HRO; bitpos: [0]; default: 0; + * set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ + uint32_t l1_icache0_sync_rst:1; + /** l1_icache1_sync_rst : HRO; bitpos: [1]; default: 0; + * set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ + uint32_t l1_icache1_sync_rst:1; + /** l1_icache2_sync_rst : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_sync_rst:1; + /** l1_icache3_sync_rst : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_sync_rst:1; + /** l1_cache_sync_rst : R/W; bitpos: [4]; default: 0; + * set this bit to reset sync-logic inside L1-Cache. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ + uint32_t l1_cache_sync_rst:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} extmem_l1_cache_sync_rst_ctrl_reg_t; + +/** Type of l2_cache_sync_rst_ctrl register + * Cache Sync Reset control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_sync_rst : HRO; bitpos: [5]; default: 0; + * set this bit to reset sync-logic inside L2-Cache. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ + uint32_t l2_cache_sync_rst:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_cache_sync_rst_ctrl_reg_t; + + +/** Group: Preload Reset control and configuration registers */ +/** Type of l1_cache_preload_rst_ctrl register + * Cache Preload Reset control register + */ +typedef union { + struct { + /** l1_icache0_pld_rst : HRO; bitpos: [0]; default: 0; + * set this bit to reset preload-logic inside L1-ICache0. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ + uint32_t l1_icache0_pld_rst:1; + /** l1_icache1_pld_rst : HRO; bitpos: [1]; default: 0; + * set this bit to reset preload-logic inside L1-ICache1. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ + uint32_t l1_icache1_pld_rst:1; + /** l1_icache2_pld_rst : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_pld_rst:1; + /** l1_icache3_pld_rst : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_pld_rst:1; + /** l1_cache_pld_rst : R/W; bitpos: [4]; default: 0; + * set this bit to reset preload-logic inside L1-Cache. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ + uint32_t l1_cache_pld_rst:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} extmem_l1_cache_preload_rst_ctrl_reg_t; + +/** Type of l2_cache_preload_rst_ctrl register + * Cache Preload Reset control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_pld_rst : HRO; bitpos: [5]; default: 0; + * set this bit to reset preload-logic inside L2-Cache. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ + uint32_t l2_cache_pld_rst:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_cache_preload_rst_ctrl_reg_t; + + +/** Group: Autoload buffer clear control and configuration registers */ +/** Type of l1_cache_autoload_buf_clr_ctrl register + * Cache Autoload buffer clear control register + */ +typedef union { + struct { + /** l1_icache0_ald_buf_clr : HRO; bitpos: [0]; default: 0; + * set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, + * autoload will not work in L1-ICache0. This bit should not be active when autoload + * works in L1-ICache0. + */ + uint32_t l1_icache0_ald_buf_clr:1; + /** l1_icache1_ald_buf_clr : HRO; bitpos: [1]; default: 0; + * set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, + * autoload will not work in L1-ICache1. This bit should not be active when autoload + * works in L1-ICache1. + */ + uint32_t l1_icache1_ald_buf_clr:1; + /** l1_icache2_ald_buf_clr : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_ald_buf_clr:1; + /** l1_icache3_ald_buf_clr : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_ald_buf_clr:1; + /** l1_cache_ald_buf_clr : R/W; bitpos: [4]; default: 0; + * set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, + * autoload will not work in L1-Cache. This bit should not be active when autoload + * works in L1-Cache. + */ + uint32_t l1_cache_ald_buf_clr:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} extmem_l1_cache_autoload_buf_clr_ctrl_reg_t; + +/** Type of l2_cache_autoload_buf_clr_ctrl register + * Cache Autoload buffer clear control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_ald_buf_clr : HRO; bitpos: [5]; default: 0; + * set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, + * autoload will not work in L2-Cache. This bit should not be active when autoload + * works in L2-Cache. + */ + uint32_t l2_cache_ald_buf_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_cache_autoload_buf_clr_ctrl_reg_t; + + +/** Group: Unallocate request buffer clear registers */ +/** Type of l1_unallocate_buffer_clear register + * Unallocate request buffer clear registers + */ +typedef union { + struct { + /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0; + * The bit is used to clear the unallocate request buffer of l1 icache0 where the + * unallocate request is responsed but not completed. + */ + uint32_t l1_icache0_unalloc_clr:1; + /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0; + * The bit is used to clear the unallocate request buffer of l1 icache1 where the + * unallocate request is responsed but not completed. + */ + uint32_t l1_icache1_unalloc_clr:1; + /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_unalloc_clr:1; + /** l1_icache3_unalloc_clr : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_unalloc_clr:1; + /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0; + * The bit is used to clear the unallocate request buffer of l1 cache where the + * unallocate request is responsed but not completed. + */ + uint32_t l1_cache_unalloc_clr:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} extmem_l1_unallocate_buffer_clear_reg_t; + +/** Type of l2_unallocate_buffer_clear register + * Unallocate request buffer clear registers + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0; + * The bit is used to clear the unallocate request buffer of l2 icache where the + * unallocate request is responsed but not completed. + */ + uint32_t l2_cache_unalloc_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} extmem_l2_unallocate_buffer_clear_reg_t; + + +/** Group: Tag and Data Memory Access Control and configuration register */ +/** Type of l1_cache_object_ctrl register + * Cache Tag and Data memory Object control register + */ +typedef union { + struct { + /** l1_icache0_tag_object : HRO; bitpos: [0]; default: 0; + * Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l1_icache0_tag_object:1; + /** l1_icache1_tag_object : HRO; bitpos: [1]; default: 0; + * Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l1_icache1_tag_object:1; + /** l1_icache2_tag_object : HRO; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_icache2_tag_object:1; + /** l1_icache3_tag_object : HRO; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_icache3_tag_object:1; + /** l1_cache_tag_object : R/W; bitpos: [4]; default: 0; + * Set this bit to set L1-Cache tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l1_cache_tag_object:1; + uint32_t reserved_5:1; + /** l1_icache0_mem_object : HRO; bitpos: [6]; default: 0; + * Set this bit to set L1-ICache0 data memory as object. This bit should be onehot + * with the others fields inside this register. + */ + uint32_t l1_icache0_mem_object:1; + /** l1_icache1_mem_object : HRO; bitpos: [7]; default: 0; + * Set this bit to set L1-ICache1 data memory as object. This bit should be onehot + * with the others fields inside this register. + */ + uint32_t l1_icache1_mem_object:1; + /** l1_icache2_mem_object : HRO; bitpos: [8]; default: 0; + * Reserved + */ + uint32_t l1_icache2_mem_object:1; + /** l1_icache3_mem_object : HRO; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t l1_icache3_mem_object:1; + /** l1_cache_mem_object : R/W; bitpos: [10]; default: 0; + * Set this bit to set L1-Cache data memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l1_cache_mem_object:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} extmem_l1_cache_object_ctrl_reg_t; + +/** Type of l1_cache_way_object register + * Cache Tag and Data memory way register + */ +typedef union { + struct { + /** l1_cache_way_object : R/W; bitpos: [2:0]; default: 0; + * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: + * way1, 2: way2, 3: way3, ?, 7: way7. + */ + uint32_t l1_cache_way_object:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} extmem_l1_cache_way_object_reg_t; + +/** Type of l1_cache_vaddr register + * Cache Vaddr register + */ +typedef union { + struct { + /** l1_cache_vaddr : R/W; bitpos: [31:0]; default: 1073741824; + * Those bits stores the virtual address which will decide where inside the specified + * tag memory object will be accessed. + */ + uint32_t l1_cache_vaddr:32; + }; + uint32_t val; +} extmem_l1_cache_vaddr_reg_t; + +/** Type of l1_cache_debug_bus register + * Cache Tag/data memory content register + */ +typedef union { + struct { + /** l1_cache_debug_bus : R/W; bitpos: [31:0]; default: 596; + * This is a constant place where we can write data to or read data from the tag/data + * memory on the specified cache. + */ + uint32_t l1_cache_debug_bus:32; + }; + uint32_t val; +} extmem_l1_cache_debug_bus_reg_t; + +/** Type of l2_cache_object_ctrl register + * Cache Tag and Data memory Object control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** l2_cache_tag_object : HRO; bitpos: [5]; default: 0; + * Set this bit to set L2-Cache tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l2_cache_tag_object:1; + uint32_t reserved_6:5; + /** l2_cache_mem_object : HRO; bitpos: [11]; default: 0; + * Set this bit to set L2-Cache data memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l2_cache_mem_object:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} extmem_l2_cache_object_ctrl_reg_t; + +/** Type of l2_cache_way_object register + * Cache Tag and Data memory way register + */ +typedef union { + struct { + /** l2_cache_way_object : HRO; bitpos: [2:0]; default: 0; + * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: + * way1, 2: way2, 3: way3, ?, 7: way7. + */ + uint32_t l2_cache_way_object:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} extmem_l2_cache_way_object_reg_t; + +/** Type of l2_cache_vaddr register + * Cache Vaddr register + */ +typedef union { + struct { + /** l2_cache_vaddr : HRO; bitpos: [31:0]; default: 1073741824; + * Those bits stores the virtual address which will decide where inside the specified + * tag memory object will be accessed. + */ + uint32_t l2_cache_vaddr:32; + }; + uint32_t val; +} extmem_l2_cache_vaddr_reg_t; + +/** Type of l2_cache_debug_bus register + * Cache Tag/data memory content register + */ +typedef union { + struct { + /** l2_cache_debug_bus : HRO; bitpos: [31:0]; default: 932; + * This is a constant place where we can write data to or read data from the tag/data + * memory on the specified cache. + */ + uint32_t l2_cache_debug_bus:32; + }; + uint32_t val; +} extmem_l2_cache_debug_bus_reg_t; + + +/** Group: Split L1 and L2 registers */ +/** Type of level_split0 register + * USED TO SPLIT L1 CACHE AND L2 CACHE + */ +typedef union { + struct { + /** level_split0 : HRO; bitpos: [31:0]; default: 600; + * Reserved + */ + uint32_t level_split0:32; + }; + uint32_t val; +} extmem_level_split0_reg_t; + +/** Type of level_split1 register + * USED TO SPLIT L1 CACHE AND L2 CACHE + */ +typedef union { + struct { + /** level_split1 : HRO; bitpos: [31:0]; default: 936; + * Reserved + */ + uint32_t level_split1:32; + }; + uint32_t val; +} extmem_level_split1_reg_t; + + +/** Group: L2 cache access attribute control register */ +/** Type of l2_cache_access_attr_ctrl register + * L1 Cache access Attribute propagation control register + */ +typedef union { + struct { + /** l2_cache_access_force_cc : HRO; bitpos: [0]; default: 1; + * Set this bit to force the request to l2 cache with cacheable attribute, otherwise, + * the attribute is propagated from L1 cache or CPU, it could be one of cacheable and + * non-cacheable. + */ + uint32_t l2_cache_access_force_cc:1; + /** l2_cache_access_force_wb : HRO; bitpos: [1]; default: 1; + * Set this bit to force the request to l2 cache with write-back attribute, otherwise, + * the attribute is propagated from L1 cache or CPU, it could be one of write-back and + * write-through. + */ + uint32_t l2_cache_access_force_wb:1; + /** l2_cache_access_force_wma : HRO; bitpos: [2]; default: 1; + * Set this bit to force the request to l2 cache with write-miss-allocate attribute, + * otherwise, the attribute is propagated from L1 cache or CPU, it could be one of + * write-miss-allocate and write-miss-no-allocate. + */ + uint32_t l2_cache_access_force_wma:1; + /** l2_cache_access_force_rma : HRO; bitpos: [3]; default: 1; + * Set this bit to force the request to l2 cache with read-miss-allocate attribute, + * otherwise, the attribute is propagated from L1 cache or CPU, it could be one of + * read-miss-allocate and read-miss-no-allocate. + */ + uint32_t l2_cache_access_force_rma:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} extmem_l2_cache_access_attr_ctrl_reg_t; + + +/** Group: Clock Gate Control and configuration register */ +/** Type of clock_gate register + * Clock gate control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * The bit is used to enable clock gate when access all registers in this module. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} extmem_clock_gate_reg_t; + + +/** Group: Redundancy register (Prepare for ECO) */ +/** Type of redundancy_sig0 register + * Cache redundancy signal 0 register + */ +typedef union { + struct { + /** cache_redcy_sig0 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ + uint32_t cache_redcy_sig0:32; + }; + uint32_t val; +} extmem_redundancy_sig0_reg_t; + +/** Type of redundancy_sig1 register + * Cache redundancy signal 1 register + */ +typedef union { + struct { + /** cache_redcy_sig1 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ + uint32_t cache_redcy_sig1:32; + }; + uint32_t val; +} extmem_redundancy_sig1_reg_t; + +/** Type of redundancy_sig2 register + * Cache redundancy signal 2 register + */ +typedef union { + struct { + /** cache_redcy_sig2 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ + uint32_t cache_redcy_sig2:32; + }; + uint32_t val; +} extmem_redundancy_sig2_reg_t; + +/** Type of redundancy_sig3 register + * Cache redundancy signal 3 register + */ +typedef union { + struct { + /** cache_redcy_sig3 : R/W; bitpos: [31:0]; default: 0; + * Those bits are prepared for ECO. + */ + uint32_t cache_redcy_sig3:32; + }; + uint32_t val; +} extmem_redundancy_sig3_reg_t; + +/** Type of redundancy_sig4 register + * Cache redundancy signal 0 register + */ +typedef union { + struct { + /** cache_redcy_sig4 : RO; bitpos: [3:0]; default: 0; + * Those bits are prepared for ECO. + */ + uint32_t cache_redcy_sig4:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} extmem_redundancy_sig4_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35659904; + * version control register. Note that this default value stored is the latest date + * when the hardware logic was updated. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} extmem_date_reg_t; + + +typedef struct extmem_dev_s { + volatile extmem_l1_icache_ctrl_reg_t l1_icache_ctrl; + volatile extmem_l1_cache_ctrl_reg_t l1_cache_ctrl; + volatile extmem_l1_bypass_cache_conf_reg_t l1_bypass_cache_conf; + volatile extmem_l1_cache_atomic_conf_reg_t l1_cache_atomic_conf; + volatile extmem_l1_icache_cachesize_conf_reg_t l1_icache_cachesize_conf; + volatile extmem_l1_icache_blocksize_conf_reg_t l1_icache_blocksize_conf; + volatile extmem_l1_cache_cachesize_conf_reg_t l1_cache_cachesize_conf; + volatile extmem_l1_cache_blocksize_conf_reg_t l1_cache_blocksize_conf; + volatile extmem_l1_cache_wrap_around_ctrl_reg_t l1_cache_wrap_around_ctrl; + volatile extmem_l1_cache_tag_mem_power_ctrl_reg_t l1_cache_tag_mem_power_ctrl; + volatile extmem_l1_cache_data_mem_power_ctrl_reg_t l1_cache_data_mem_power_ctrl; + volatile extmem_l1_cache_freeze_ctrl_reg_t l1_cache_freeze_ctrl; + volatile extmem_l1_cache_data_mem_acs_conf_reg_t l1_cache_data_mem_acs_conf; + volatile extmem_l1_cache_tag_mem_acs_conf_reg_t l1_cache_tag_mem_acs_conf; + volatile extmem_l1_icache0_prelock_conf_reg_t l1_icache0_prelock_conf; + volatile extmem_l1_icache0_prelock_sct0_addr_reg_t l1_icache0_prelock_sct0_addr; + volatile extmem_l1_icache0_prelock_sct1_addr_reg_t l1_icache0_prelock_sct1_addr; + volatile extmem_l1_icache0_prelock_sct_size_reg_t l1_icache0_prelock_sct_size; + volatile extmem_l1_icache1_prelock_conf_reg_t l1_icache1_prelock_conf; + volatile extmem_l1_icache1_prelock_sct0_addr_reg_t l1_icache1_prelock_sct0_addr; + volatile extmem_l1_icache1_prelock_sct1_addr_reg_t l1_icache1_prelock_sct1_addr; + volatile extmem_l1_icache1_prelock_sct_size_reg_t l1_icache1_prelock_sct_size; + volatile extmem_l1_icache2_prelock_conf_reg_t l1_icache2_prelock_conf; + volatile extmem_l1_icache2_prelock_sct0_addr_reg_t l1_icache2_prelock_sct0_addr; + volatile extmem_l1_icache2_prelock_sct1_addr_reg_t l1_icache2_prelock_sct1_addr; + volatile extmem_l1_icache2_prelock_sct_size_reg_t l1_icache2_prelock_sct_size; + volatile extmem_l1_icache3_prelock_conf_reg_t l1_icache3_prelock_conf; + volatile extmem_l1_icache3_prelock_sct0_addr_reg_t l1_icache3_prelock_sct0_addr; + volatile extmem_l1_icache3_prelock_sct1_addr_reg_t l1_icache3_prelock_sct1_addr; + volatile extmem_l1_icache3_prelock_sct_size_reg_t l1_icache3_prelock_sct_size; + volatile extmem_l1_cache_prelock_conf_reg_t l1_cache_prelock_conf; + volatile extmem_l1_cache_prelock_sct0_addr_reg_t l1_cache_prelock_sct0_addr; + volatile extmem_l1_dcache_prelock_sct1_addr_reg_t l1_dcache_prelock_sct1_addr; + volatile extmem_l1_dcache_prelock_sct_size_reg_t l1_dcache_prelock_sct_size; + volatile extmem_cache_lock_ctrl_reg_t cache_lock_ctrl; + volatile extmem_cache_lock_map_reg_t cache_lock_map; + volatile extmem_cache_lock_addr_reg_t cache_lock_addr; + volatile extmem_cache_lock_size_reg_t cache_lock_size; + volatile extmem_cache_sync_ctrl_reg_t cache_sync_ctrl; + volatile extmem_cache_sync_map_reg_t cache_sync_map; + volatile extmem_cache_sync_addr_reg_t cache_sync_addr; + volatile extmem_cache_sync_size_reg_t cache_sync_size; + volatile extmem_l1_icache0_preload_ctrl_reg_t l1_icache0_preload_ctrl; + volatile extmem_l1_icache0_preload_addr_reg_t l1_icache0_preload_addr; + volatile extmem_l1_icache0_preload_size_reg_t l1_icache0_preload_size; + volatile extmem_l1_icache1_preload_ctrl_reg_t l1_icache1_preload_ctrl; + volatile extmem_l1_icache1_preload_addr_reg_t l1_icache1_preload_addr; + volatile extmem_l1_icache1_preload_size_reg_t l1_icache1_preload_size; + volatile extmem_l1_icache2_preload_ctrl_reg_t l1_icache2_preload_ctrl; + volatile extmem_l1_icache2_preload_addr_reg_t l1_icache2_preload_addr; + volatile extmem_l1_icache2_preload_size_reg_t l1_icache2_preload_size; + volatile extmem_l1_icache3_preload_ctrl_reg_t l1_icache3_preload_ctrl; + volatile extmem_l1_icache3_preload_addr_reg_t l1_icache3_preload_addr; + volatile extmem_l1_icache3_preload_size_reg_t l1_icache3_preload_size; + volatile extmem_l1_cache_preload_ctrl_reg_t l1_cache_preload_ctrl; + volatile extmem_l1_dcache_preload_addr_reg_t l1_dcache_preload_addr; + volatile extmem_l1_dcache_preload_size_reg_t l1_dcache_preload_size; + volatile extmem_l1_icache0_autoload_ctrl_reg_t l1_icache0_autoload_ctrl; + volatile extmem_l1_icache0_autoload_sct0_addr_reg_t l1_icache0_autoload_sct0_addr; + volatile extmem_l1_icache0_autoload_sct0_size_reg_t l1_icache0_autoload_sct0_size; + volatile extmem_l1_icache0_autoload_sct1_addr_reg_t l1_icache0_autoload_sct1_addr; + volatile extmem_l1_icache0_autoload_sct1_size_reg_t l1_icache0_autoload_sct1_size; + volatile extmem_l1_icache1_autoload_ctrl_reg_t l1_icache1_autoload_ctrl; + volatile extmem_l1_icache1_autoload_sct0_addr_reg_t l1_icache1_autoload_sct0_addr; + volatile extmem_l1_icache1_autoload_sct0_size_reg_t l1_icache1_autoload_sct0_size; + volatile extmem_l1_icache1_autoload_sct1_addr_reg_t l1_icache1_autoload_sct1_addr; + volatile extmem_l1_icache1_autoload_sct1_size_reg_t l1_icache1_autoload_sct1_size; + volatile extmem_l1_icache2_autoload_ctrl_reg_t l1_icache2_autoload_ctrl; + volatile extmem_l1_icache2_autoload_sct0_addr_reg_t l1_icache2_autoload_sct0_addr; + volatile extmem_l1_icache2_autoload_sct0_size_reg_t l1_icache2_autoload_sct0_size; + volatile extmem_l1_icache2_autoload_sct1_addr_reg_t l1_icache2_autoload_sct1_addr; + volatile extmem_l1_icache2_autoload_sct1_size_reg_t l1_icache2_autoload_sct1_size; + volatile extmem_l1_icache3_autoload_ctrl_reg_t l1_icache3_autoload_ctrl; + volatile extmem_l1_icache3_autoload_sct0_addr_reg_t l1_icache3_autoload_sct0_addr; + volatile extmem_l1_icache3_autoload_sct0_size_reg_t l1_icache3_autoload_sct0_size; + volatile extmem_l1_icache3_autoload_sct1_addr_reg_t l1_icache3_autoload_sct1_addr; + volatile extmem_l1_icache3_autoload_sct1_size_reg_t l1_icache3_autoload_sct1_size; + volatile extmem_l1_cache_autoload_ctrl_reg_t l1_cache_autoload_ctrl; + volatile extmem_l1_cache_autoload_sct0_addr_reg_t l1_cache_autoload_sct0_addr; + volatile extmem_l1_cache_autoload_sct0_size_reg_t l1_cache_autoload_sct0_size; + volatile extmem_l1_cache_autoload_sct1_addr_reg_t l1_cache_autoload_sct1_addr; + volatile extmem_l1_cache_autoload_sct1_size_reg_t l1_cache_autoload_sct1_size; + volatile extmem_l1_cache_autoload_sct2_addr_reg_t l1_cache_autoload_sct2_addr; + volatile extmem_l1_cache_autoload_sct2_size_reg_t l1_cache_autoload_sct2_size; + volatile extmem_l1_cache_autoload_sct3_addr_reg_t l1_cache_autoload_sct3_addr; + volatile extmem_l1_cache_autoload_sct3_size_reg_t l1_cache_autoload_sct3_size; + volatile extmem_l1_cache_acs_cnt_int_ena_reg_t l1_cache_acs_cnt_int_ena; + volatile extmem_l1_cache_acs_cnt_int_clr_reg_t l1_cache_acs_cnt_int_clr; + volatile extmem_l1_cache_acs_cnt_int_raw_reg_t l1_cache_acs_cnt_int_raw; + volatile extmem_l1_cache_acs_cnt_int_st_reg_t l1_cache_acs_cnt_int_st; + volatile extmem_l1_cache_acs_fail_int_ena_reg_t l1_cache_acs_fail_int_ena; + volatile extmem_l1_cache_acs_fail_int_clr_reg_t l1_cache_acs_fail_int_clr; + volatile extmem_l1_cache_acs_fail_int_raw_reg_t l1_cache_acs_fail_int_raw; + volatile extmem_l1_cache_acs_fail_int_st_reg_t l1_cache_acs_fail_int_st; + volatile extmem_l1_cache_acs_cnt_ctrl_reg_t l1_cache_acs_cnt_ctrl; + volatile extmem_l1_ibus0_acs_hit_cnt_reg_t l1_ibus0_acs_hit_cnt; + volatile extmem_l1_ibus0_acs_miss_cnt_reg_t l1_ibus0_acs_miss_cnt; + volatile extmem_l1_ibus0_acs_conflict_cnt_reg_t l1_ibus0_acs_conflict_cnt; + volatile extmem_l1_ibus0_acs_nxtlvl_cnt_reg_t l1_ibus0_acs_nxtlvl_cnt; + volatile extmem_l1_ibus1_acs_hit_cnt_reg_t l1_ibus1_acs_hit_cnt; + volatile extmem_l1_ibus1_acs_miss_cnt_reg_t l1_ibus1_acs_miss_cnt; + volatile extmem_l1_ibus1_acs_conflict_cnt_reg_t l1_ibus1_acs_conflict_cnt; + volatile extmem_l1_ibus1_acs_nxtlvl_cnt_reg_t l1_ibus1_acs_nxtlvl_cnt; + volatile extmem_l1_ibus2_acs_hit_cnt_reg_t l1_ibus2_acs_hit_cnt; + volatile extmem_l1_ibus2_acs_miss_cnt_reg_t l1_ibus2_acs_miss_cnt; + volatile extmem_l1_ibus2_acs_conflict_cnt_reg_t l1_ibus2_acs_conflict_cnt; + volatile extmem_l1_ibus2_acs_nxtlvl_cnt_reg_t l1_ibus2_acs_nxtlvl_cnt; + volatile extmem_l1_ibus3_acs_hit_cnt_reg_t l1_ibus3_acs_hit_cnt; + volatile extmem_l1_ibus3_acs_miss_cnt_reg_t l1_ibus3_acs_miss_cnt; + volatile extmem_l1_ibus3_acs_conflict_cnt_reg_t l1_ibus3_acs_conflict_cnt; + volatile extmem_l1_ibus3_acs_nxtlvl_cnt_reg_t l1_ibus3_acs_nxtlvl_cnt; + volatile extmem_l1_bus0_acs_hit_cnt_reg_t l1_bus0_acs_hit_cnt; + volatile extmem_l1_bus0_acs_miss_cnt_reg_t l1_bus0_acs_miss_cnt; + volatile extmem_l1_bus0_acs_conflict_cnt_reg_t l1_bus0_acs_conflict_cnt; + volatile extmem_l1_bus0_acs_nxtlvl_cnt_reg_t l1_bus0_acs_nxtlvl_cnt; + volatile extmem_l1_bus1_acs_hit_cnt_reg_t l1_bus1_acs_hit_cnt; + volatile extmem_l1_bus1_acs_miss_cnt_reg_t l1_bus1_acs_miss_cnt; + volatile extmem_l1_bus1_acs_conflict_cnt_reg_t l1_bus1_acs_conflict_cnt; + volatile extmem_l1_bus1_acs_nxtlvl_cnt_reg_t l1_bus1_acs_nxtlvl_cnt; + volatile extmem_l1_dbus2_acs_hit_cnt_reg_t l1_dbus2_acs_hit_cnt; + volatile extmem_l1_dbus2_acs_miss_cnt_reg_t l1_dbus2_acs_miss_cnt; + volatile extmem_l1_dbus2_acs_conflict_cnt_reg_t l1_dbus2_acs_conflict_cnt; + volatile extmem_l1_dbus2_acs_nxtlvl_cnt_reg_t l1_dbus2_acs_nxtlvl_cnt; + volatile extmem_l1_dbus3_acs_hit_cnt_reg_t l1_dbus3_acs_hit_cnt; + volatile extmem_l1_dbus3_acs_miss_cnt_reg_t l1_dbus3_acs_miss_cnt; + volatile extmem_l1_dbus3_acs_conflict_cnt_reg_t l1_dbus3_acs_conflict_cnt; + volatile extmem_l1_dbus3_acs_nxtlvl_cnt_reg_t l1_dbus3_acs_nxtlvl_cnt; + volatile extmem_l1_icache0_acs_fail_id_attr_reg_t l1_icache0_acs_fail_id_attr; + volatile extmem_l1_icache0_acs_fail_addr_reg_t l1_icache0_acs_fail_addr; + volatile extmem_l1_icache1_acs_fail_id_attr_reg_t l1_icache1_acs_fail_id_attr; + volatile extmem_l1_icache1_acs_fail_addr_reg_t l1_icache1_acs_fail_addr; + volatile extmem_l1_icache2_acs_fail_id_attr_reg_t l1_icache2_acs_fail_id_attr; + volatile extmem_l1_icache2_acs_fail_addr_reg_t l1_icache2_acs_fail_addr; + volatile extmem_l1_icache3_acs_fail_id_attr_reg_t l1_icache3_acs_fail_id_attr; + volatile extmem_l1_icache3_acs_fail_addr_reg_t l1_icache3_acs_fail_addr; + volatile extmem_l1_cache_acs_fail_id_attr_reg_t l1_cache_acs_fail_id_attr; + volatile extmem_l1_dcache_acs_fail_addr_reg_t l1_dcache_acs_fail_addr; + volatile extmem_l1_cache_sync_preload_int_ena_reg_t l1_cache_sync_preload_int_ena; + volatile extmem_l1_cache_sync_preload_int_clr_reg_t l1_cache_sync_preload_int_clr; + volatile extmem_l1_cache_sync_preload_int_raw_reg_t l1_cache_sync_preload_int_raw; + volatile extmem_l1_cache_sync_preload_int_st_reg_t l1_cache_sync_preload_int_st; + volatile extmem_l1_cache_sync_preload_exception_reg_t l1_cache_sync_preload_exception; + volatile extmem_l1_cache_sync_rst_ctrl_reg_t l1_cache_sync_rst_ctrl; + volatile extmem_l1_cache_preload_rst_ctrl_reg_t l1_cache_preload_rst_ctrl; + volatile extmem_l1_cache_autoload_buf_clr_ctrl_reg_t l1_cache_autoload_buf_clr_ctrl; + volatile extmem_l1_unallocate_buffer_clear_reg_t l1_unallocate_buffer_clear; + volatile extmem_l1_cache_object_ctrl_reg_t l1_cache_object_ctrl; + volatile extmem_l1_cache_way_object_reg_t l1_cache_way_object; + volatile extmem_l1_cache_vaddr_reg_t l1_cache_vaddr; + volatile extmem_l1_cache_debug_bus_reg_t l1_cache_debug_bus; + volatile extmem_level_split0_reg_t level_split0; + volatile extmem_l2_cache_ctrl_reg_t l2_cache_ctrl; + volatile extmem_l2_bypass_cache_conf_reg_t l2_bypass_cache_conf; + volatile extmem_l2_cache_cachesize_conf_reg_t l2_cache_cachesize_conf; + volatile extmem_l2_cache_blocksize_conf_reg_t l2_cache_blocksize_conf; + volatile extmem_l2_cache_wrap_around_ctrl_reg_t l2_cache_wrap_around_ctrl; + volatile extmem_l2_cache_tag_mem_power_ctrl_reg_t l2_cache_tag_mem_power_ctrl; + volatile extmem_l2_cache_data_mem_power_ctrl_reg_t l2_cache_data_mem_power_ctrl; + volatile extmem_l2_cache_freeze_ctrl_reg_t l2_cache_freeze_ctrl; + volatile extmem_l2_cache_data_mem_acs_conf_reg_t l2_cache_data_mem_acs_conf; + volatile extmem_l2_cache_tag_mem_acs_conf_reg_t l2_cache_tag_mem_acs_conf; + volatile extmem_l2_cache_prelock_conf_reg_t l2_cache_prelock_conf; + volatile extmem_l2_cache_prelock_sct0_addr_reg_t l2_cache_prelock_sct0_addr; + volatile extmem_l2_cache_prelock_sct1_addr_reg_t l2_cache_prelock_sct1_addr; + volatile extmem_l2_cache_prelock_sct_size_reg_t l2_cache_prelock_sct_size; + volatile extmem_l2_cache_preload_ctrl_reg_t l2_cache_preload_ctrl; + volatile extmem_l2_cache_preload_addr_reg_t l2_cache_preload_addr; + volatile extmem_l2_cache_preload_size_reg_t l2_cache_preload_size; + volatile extmem_l2_cache_autoload_ctrl_reg_t l2_cache_autoload_ctrl; + volatile extmem_l2_cache_autoload_sct0_addr_reg_t l2_cache_autoload_sct0_addr; + volatile extmem_l2_cache_autoload_sct0_size_reg_t l2_cache_autoload_sct0_size; + volatile extmem_l2_cache_autoload_sct1_addr_reg_t l2_cache_autoload_sct1_addr; + volatile extmem_l2_cache_autoload_sct1_size_reg_t l2_cache_autoload_sct1_size; + volatile extmem_l2_cache_autoload_sct2_addr_reg_t l2_cache_autoload_sct2_addr; + volatile extmem_l2_cache_autoload_sct2_size_reg_t l2_cache_autoload_sct2_size; + volatile extmem_l2_cache_autoload_sct3_addr_reg_t l2_cache_autoload_sct3_addr; + volatile extmem_l2_cache_autoload_sct3_size_reg_t l2_cache_autoload_sct3_size; + volatile extmem_l2_cache_acs_cnt_int_ena_reg_t l2_cache_acs_cnt_int_ena; + volatile extmem_l2_cache_acs_cnt_int_clr_reg_t l2_cache_acs_cnt_int_clr; + volatile extmem_l2_cache_acs_cnt_int_raw_reg_t l2_cache_acs_cnt_int_raw; + volatile extmem_l2_cache_acs_cnt_int_st_reg_t l2_cache_acs_cnt_int_st; + volatile extmem_l2_cache_acs_fail_int_ena_reg_t l2_cache_acs_fail_int_ena; + volatile extmem_l2_cache_acs_fail_int_clr_reg_t l2_cache_acs_fail_int_clr; + volatile extmem_l2_cache_acs_fail_int_raw_reg_t l2_cache_acs_fail_int_raw; + volatile extmem_l2_cache_acs_fail_int_st_reg_t l2_cache_acs_fail_int_st; + volatile extmem_l2_cache_acs_cnt_ctrl_reg_t l2_cache_acs_cnt_ctrl; + volatile extmem_l2_ibus0_acs_hit_cnt_reg_t l2_ibus0_acs_hit_cnt; + volatile extmem_l2_ibus0_acs_miss_cnt_reg_t l2_ibus0_acs_miss_cnt; + volatile extmem_l2_ibus0_acs_conflict_cnt_reg_t l2_ibus0_acs_conflict_cnt; + volatile extmem_l2_ibus0_acs_nxtlvl_cnt_reg_t l2_ibus0_acs_nxtlvl_cnt; + volatile extmem_l2_ibus1_acs_hit_cnt_reg_t l2_ibus1_acs_hit_cnt; + volatile extmem_l2_ibus1_acs_miss_cnt_reg_t l2_ibus1_acs_miss_cnt; + volatile extmem_l2_ibus1_acs_conflict_cnt_reg_t l2_ibus1_acs_conflict_cnt; + volatile extmem_l2_ibus1_acs_nxtlvl_cnt_reg_t l2_ibus1_acs_nxtlvl_cnt; + volatile extmem_l2_ibus2_acs_hit_cnt_reg_t l2_ibus2_acs_hit_cnt; + volatile extmem_l2_ibus2_acs_miss_cnt_reg_t l2_ibus2_acs_miss_cnt; + volatile extmem_l2_ibus2_acs_conflict_cnt_reg_t l2_ibus2_acs_conflict_cnt; + volatile extmem_l2_ibus2_acs_nxtlvl_cnt_reg_t l2_ibus2_acs_nxtlvl_cnt; + volatile extmem_l2_ibus3_acs_hit_cnt_reg_t l2_ibus3_acs_hit_cnt; + volatile extmem_l2_ibus3_acs_miss_cnt_reg_t l2_ibus3_acs_miss_cnt; + volatile extmem_l2_ibus3_acs_conflict_cnt_reg_t l2_ibus3_acs_conflict_cnt; + volatile extmem_l2_ibus3_acs_nxtlvl_cnt_reg_t l2_ibus3_acs_nxtlvl_cnt; + volatile extmem_l2_dbus0_acs_hit_cnt_reg_t l2_dbus0_acs_hit_cnt; + volatile extmem_l2_dbus0_acs_miss_cnt_reg_t l2_dbus0_acs_miss_cnt; + volatile extmem_l2_dbus0_acs_conflict_cnt_reg_t l2_dbus0_acs_conflict_cnt; + volatile extmem_l2_dbus0_acs_nxtlvl_cnt_reg_t l2_dbus0_acs_nxtlvl_cnt; + volatile extmem_l2_dbus1_acs_hit_cnt_reg_t l2_dbus1_acs_hit_cnt; + volatile extmem_l2_dbus1_acs_miss_cnt_reg_t l2_dbus1_acs_miss_cnt; + volatile extmem_l2_dbus1_acs_conflict_cnt_reg_t l2_dbus1_acs_conflict_cnt; + volatile extmem_l2_dbus1_acs_nxtlvl_cnt_reg_t l2_dbus1_acs_nxtlvl_cnt; + volatile extmem_l2_dbus2_acs_hit_cnt_reg_t l2_dbus2_acs_hit_cnt; + volatile extmem_l2_dbus2_acs_miss_cnt_reg_t l2_dbus2_acs_miss_cnt; + volatile extmem_l2_dbus2_acs_conflict_cnt_reg_t l2_dbus2_acs_conflict_cnt; + volatile extmem_l2_dbus2_acs_nxtlvl_cnt_reg_t l2_dbus2_acs_nxtlvl_cnt; + volatile extmem_l2_dbus3_acs_hit_cnt_reg_t l2_dbus3_acs_hit_cnt; + volatile extmem_l2_dbus3_acs_miss_cnt_reg_t l2_dbus3_acs_miss_cnt; + volatile extmem_l2_dbus3_acs_conflict_cnt_reg_t l2_dbus3_acs_conflict_cnt; + volatile extmem_l2_dbus3_acs_nxtlvl_cnt_reg_t l2_dbus3_acs_nxtlvl_cnt; + volatile extmem_l2_cache_acs_fail_id_attr_reg_t l2_cache_acs_fail_id_attr; + volatile extmem_l2_cache_acs_fail_addr_reg_t l2_cache_acs_fail_addr; + volatile extmem_l2_cache_sync_preload_int_ena_reg_t l2_cache_sync_preload_int_ena; + volatile extmem_l2_cache_sync_preload_int_clr_reg_t l2_cache_sync_preload_int_clr; + volatile extmem_l2_cache_sync_preload_int_raw_reg_t l2_cache_sync_preload_int_raw; + volatile extmem_l2_cache_sync_preload_int_st_reg_t l2_cache_sync_preload_int_st; + volatile extmem_l2_cache_sync_preload_exception_reg_t l2_cache_sync_preload_exception; + volatile extmem_l2_cache_sync_rst_ctrl_reg_t l2_cache_sync_rst_ctrl; + volatile extmem_l2_cache_preload_rst_ctrl_reg_t l2_cache_preload_rst_ctrl; + volatile extmem_l2_cache_autoload_buf_clr_ctrl_reg_t l2_cache_autoload_buf_clr_ctrl; + volatile extmem_l2_unallocate_buffer_clear_reg_t l2_unallocate_buffer_clear; + volatile extmem_l2_cache_access_attr_ctrl_reg_t l2_cache_access_attr_ctrl; + volatile extmem_l2_cache_object_ctrl_reg_t l2_cache_object_ctrl; + volatile extmem_l2_cache_way_object_reg_t l2_cache_way_object; + volatile extmem_l2_cache_vaddr_reg_t l2_cache_vaddr; + volatile extmem_l2_cache_debug_bus_reg_t l2_cache_debug_bus; + volatile extmem_level_split1_reg_t level_split1; + volatile extmem_clock_gate_reg_t clock_gate; + volatile extmem_redundancy_sig0_reg_t redundancy_sig0; + volatile extmem_redundancy_sig1_reg_t redundancy_sig1; + volatile extmem_redundancy_sig2_reg_t redundancy_sig2; + volatile extmem_redundancy_sig3_reg_t redundancy_sig3; + volatile extmem_redundancy_sig4_reg_t redundancy_sig4; + uint32_t reserved_3c4[14]; + volatile extmem_date_reg_t date; +} extmem_dev_t; + +extern extmem_dev_t EXTMEM; + +#ifndef __cplusplus +_Static_assert(sizeof(extmem_dev_t) == 0x400, "Invalid size of extmem_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/gdma_channel.h b/components/soc/esp32c6/include/soc/gdma_channel.h new file mode 100644 index 0000000000..de9e2dd659 --- /dev/null +++ b/components/soc/esp32c6/include/soc/gdma_channel.h @@ -0,0 +1,16 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER` +#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1) +#define SOC_GDMA_TRIG_PERIPH_SPI2 (0) +#define SOC_GDMA_TRIG_PERIPH_UART0 (2) +#define SOC_GDMA_TRIG_PERIPH_I2S0 (3) +#define SOC_GDMA_TRIG_PERIPH_AES0 (6) +#define SOC_GDMA_TRIG_PERIPH_SHA0 (7) +#define SOC_GDMA_TRIG_PERIPH_ADC0 (8) diff --git a/components/soc/esp32c6/include/soc/gdma_reg.h b/components/soc/esp32c6/include/soc/gdma_reg.h new file mode 100644 index 0000000000..e4e0890bb1 --- /dev/null +++ b/components/soc/esp32c6/include/soc/gdma_reg.h @@ -0,0 +1,3161 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** GDMA_IN_INT_RAW_CH0_REG register + * Raw status interrupt of channel 0 + */ +#define GDMA_IN_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x0) +/** GDMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. + */ +#define GDMA_IN_DONE_CH0_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_RAW_M (GDMA_IN_DONE_CH0_INT_RAW_V << GDMA_IN_DONE_CH0_INT_RAW_S) +#define GDMA_IN_DONE_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_RAW_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel 0. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_M (GDMA_IN_SUC_EOF_CH0_INT_RAW_V << GDMA_IN_SUC_EOF_CH0_INT_RAW_S) +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw + * interrupt is reserved. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_M (GDMA_IN_ERR_EOF_CH0_INT_RAW_V << GDMA_IN_ERR_EOF_CH0_INT_RAW_S) +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel 0. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_M (GDMA_IN_DSCR_ERR_CH0_INT_RAW_V << GDMA_IN_DSCR_ERR_CH0_INT_RAW_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel 0. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * overflow. + */ +#define GDMA_INFIFO_OVF_CH0_INT_RAW (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_RAW_M (GDMA_INFIFO_OVF_CH0_INT_RAW_V << GDMA_INFIFO_OVF_CH0_INT_RAW_S) +#define GDMA_INFIFO_OVF_CH0_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_RAW_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * underflow. + */ +#define GDMA_INFIFO_UDF_CH0_INT_RAW (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_RAW_M (GDMA_INFIFO_UDF_CH0_INT_RAW_V << GDMA_INFIFO_UDF_CH0_INT_RAW_S) +#define GDMA_INFIFO_UDF_CH0_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_RAW_S 6 + +/** GDMA_IN_INT_ST_CH0_REG register + * Masked interrupt of channel 0 + */ +#define GDMA_IN_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x4) +/** GDMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH0_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_ST_M (GDMA_IN_DONE_CH0_INT_ST_V << GDMA_IN_DONE_CH0_INT_ST_S) +#define GDMA_IN_DONE_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_ST_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_ST_M (GDMA_IN_SUC_EOF_CH0_INT_ST_V << GDMA_IN_SUC_EOF_CH0_INT_ST_S) +#define GDMA_IN_SUC_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_ST_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_ST_M (GDMA_IN_ERR_EOF_CH0_INT_ST_V << GDMA_IN_ERR_EOF_CH0_INT_ST_S) +#define GDMA_IN_ERR_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_ST_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_M (GDMA_IN_DSCR_ERR_CH0_INT_ST_V << GDMA_IN_DSCR_ERR_CH0_INT_ST_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_M (GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH0_INT_ST (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_ST_M (GDMA_INFIFO_OVF_CH0_INT_ST_V << GDMA_INFIFO_OVF_CH0_INT_ST_S) +#define GDMA_INFIFO_OVF_CH0_INT_ST_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_ST_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH0_INT_ST (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_ST_M (GDMA_INFIFO_UDF_CH0_INT_ST_V << GDMA_INFIFO_UDF_CH0_INT_ST_S) +#define GDMA_INFIFO_UDF_CH0_INT_ST_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_ST_S 6 + +/** GDMA_IN_INT_ENA_CH0_REG register + * Interrupt enable bits of channel 0 + */ +#define GDMA_IN_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x8) +/** GDMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH0_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_ENA_M (GDMA_IN_DONE_CH0_INT_ENA_V << GDMA_IN_DONE_CH0_INT_ENA_S) +#define GDMA_IN_DONE_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_ENA_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_M (GDMA_IN_SUC_EOF_CH0_INT_ENA_V << GDMA_IN_SUC_EOF_CH0_INT_ENA_S) +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_M (GDMA_IN_ERR_EOF_CH0_INT_ENA_V << GDMA_IN_ERR_EOF_CH0_INT_ENA_S) +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_M (GDMA_IN_DSCR_ERR_CH0_INT_ENA_V << GDMA_IN_DSCR_ERR_CH0_INT_ENA_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_M (GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH0_INT_ENA (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_ENA_M (GDMA_INFIFO_OVF_CH0_INT_ENA_V << GDMA_INFIFO_OVF_CH0_INT_ENA_S) +#define GDMA_INFIFO_OVF_CH0_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_ENA_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH0_INT_ENA (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_ENA_M (GDMA_INFIFO_UDF_CH0_INT_ENA_V << GDMA_INFIFO_UDF_CH0_INT_ENA_S) +#define GDMA_INFIFO_UDF_CH0_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_ENA_S 6 + +/** GDMA_IN_INT_CLR_CH0_REG register + * Interrupt clear bits of channel 0 + */ +#define GDMA_IN_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0xc) +/** GDMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH0_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_CLR_M (GDMA_IN_DONE_CH0_INT_CLR_V << GDMA_IN_DONE_CH0_INT_CLR_S) +#define GDMA_IN_DONE_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_CLR_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_M (GDMA_IN_SUC_EOF_CH0_INT_CLR_V << GDMA_IN_SUC_EOF_CH0_INT_CLR_S) +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_M (GDMA_IN_ERR_EOF_CH0_INT_CLR_V << GDMA_IN_ERR_EOF_CH0_INT_CLR_S) +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_M (GDMA_IN_DSCR_ERR_CH0_INT_CLR_V << GDMA_IN_DSCR_ERR_CH0_INT_CLR_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_M (GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH0_INT_CLR (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_CLR_M (GDMA_INFIFO_OVF_CH0_INT_CLR_V << GDMA_INFIFO_OVF_CH0_INT_CLR_S) +#define GDMA_INFIFO_OVF_CH0_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_CLR_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH0_INT_CLR (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_CLR_M (GDMA_INFIFO_UDF_CH0_INT_CLR_V << GDMA_INFIFO_UDF_CH0_INT_CLR_S) +#define GDMA_INFIFO_UDF_CH0_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_CLR_S 6 + +/** GDMA_IN_INT_RAW_CH1_REG register + * Raw status interrupt of channel 0 + */ +#define GDMA_IN_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x10) +/** GDMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. + */ +#define GDMA_IN_DONE_CH1_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_RAW_M (GDMA_IN_DONE_CH1_INT_RAW_V << GDMA_IN_DONE_CH1_INT_RAW_S) +#define GDMA_IN_DONE_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_RAW_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel 0. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_M (GDMA_IN_SUC_EOF_CH1_INT_RAW_V << GDMA_IN_SUC_EOF_CH1_INT_RAW_S) +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw + * interrupt is reserved. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_M (GDMA_IN_ERR_EOF_CH1_INT_RAW_V << GDMA_IN_ERR_EOF_CH1_INT_RAW_S) +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel 0. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_M (GDMA_IN_DSCR_ERR_CH1_INT_RAW_V << GDMA_IN_DSCR_ERR_CH1_INT_RAW_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel 0. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * overflow. + */ +#define GDMA_INFIFO_OVF_CH1_INT_RAW (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_RAW_M (GDMA_INFIFO_OVF_CH1_INT_RAW_V << GDMA_INFIFO_OVF_CH1_INT_RAW_S) +#define GDMA_INFIFO_OVF_CH1_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_RAW_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * underflow. + */ +#define GDMA_INFIFO_UDF_CH1_INT_RAW (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_RAW_M (GDMA_INFIFO_UDF_CH1_INT_RAW_V << GDMA_INFIFO_UDF_CH1_INT_RAW_S) +#define GDMA_INFIFO_UDF_CH1_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_RAW_S 6 + +/** GDMA_IN_INT_ST_CH1_REG register + * Masked interrupt of channel 0 + */ +#define GDMA_IN_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x14) +/** GDMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH1_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_ST_M (GDMA_IN_DONE_CH1_INT_ST_V << GDMA_IN_DONE_CH1_INT_ST_S) +#define GDMA_IN_DONE_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_ST_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_ST_M (GDMA_IN_SUC_EOF_CH1_INT_ST_V << GDMA_IN_SUC_EOF_CH1_INT_ST_S) +#define GDMA_IN_SUC_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_ST_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_ST_M (GDMA_IN_ERR_EOF_CH1_INT_ST_V << GDMA_IN_ERR_EOF_CH1_INT_ST_S) +#define GDMA_IN_ERR_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_ST_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_M (GDMA_IN_DSCR_ERR_CH1_INT_ST_V << GDMA_IN_DSCR_ERR_CH1_INT_ST_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_M (GDMA_IN_DSCR_EMPTY_CH1_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH1_INT_ST_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH1_INT_ST (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_ST_M (GDMA_INFIFO_OVF_CH1_INT_ST_V << GDMA_INFIFO_OVF_CH1_INT_ST_S) +#define GDMA_INFIFO_OVF_CH1_INT_ST_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_ST_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH1_INT_ST (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_ST_M (GDMA_INFIFO_UDF_CH1_INT_ST_V << GDMA_INFIFO_UDF_CH1_INT_ST_S) +#define GDMA_INFIFO_UDF_CH1_INT_ST_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_ST_S 6 + +/** GDMA_IN_INT_ENA_CH1_REG register + * Interrupt enable bits of channel 0 + */ +#define GDMA_IN_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x18) +/** GDMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH1_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_ENA_M (GDMA_IN_DONE_CH1_INT_ENA_V << GDMA_IN_DONE_CH1_INT_ENA_S) +#define GDMA_IN_DONE_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_ENA_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_M (GDMA_IN_SUC_EOF_CH1_INT_ENA_V << GDMA_IN_SUC_EOF_CH1_INT_ENA_S) +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_M (GDMA_IN_ERR_EOF_CH1_INT_ENA_V << GDMA_IN_ERR_EOF_CH1_INT_ENA_S) +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_M (GDMA_IN_DSCR_ERR_CH1_INT_ENA_V << GDMA_IN_DSCR_ERR_CH1_INT_ENA_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_M (GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH1_INT_ENA (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_ENA_M (GDMA_INFIFO_OVF_CH1_INT_ENA_V << GDMA_INFIFO_OVF_CH1_INT_ENA_S) +#define GDMA_INFIFO_OVF_CH1_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_ENA_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH1_INT_ENA (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_ENA_M (GDMA_INFIFO_UDF_CH1_INT_ENA_V << GDMA_INFIFO_UDF_CH1_INT_ENA_S) +#define GDMA_INFIFO_UDF_CH1_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_ENA_S 6 + +/** GDMA_IN_INT_CLR_CH1_REG register + * Interrupt clear bits of channel 0 + */ +#define GDMA_IN_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x1c) +/** GDMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH1_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_CLR_M (GDMA_IN_DONE_CH1_INT_CLR_V << GDMA_IN_DONE_CH1_INT_CLR_S) +#define GDMA_IN_DONE_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_CLR_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_M (GDMA_IN_SUC_EOF_CH1_INT_CLR_V << GDMA_IN_SUC_EOF_CH1_INT_CLR_S) +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_M (GDMA_IN_ERR_EOF_CH1_INT_CLR_V << GDMA_IN_ERR_EOF_CH1_INT_CLR_S) +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_M (GDMA_IN_DSCR_ERR_CH1_INT_CLR_V << GDMA_IN_DSCR_ERR_CH1_INT_CLR_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_M (GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH1_INT_CLR (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_CLR_M (GDMA_INFIFO_OVF_CH1_INT_CLR_V << GDMA_INFIFO_OVF_CH1_INT_CLR_S) +#define GDMA_INFIFO_OVF_CH1_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_CLR_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH1_INT_CLR (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_CLR_M (GDMA_INFIFO_UDF_CH1_INT_CLR_V << GDMA_INFIFO_UDF_CH1_INT_CLR_S) +#define GDMA_INFIFO_UDF_CH1_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_CLR_S 6 + +/** GDMA_IN_INT_RAW_CH2_REG register + * Raw status interrupt of channel 0 + */ +#define GDMA_IN_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x20) +/** GDMA_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. + */ +#define GDMA_IN_DONE_CH2_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_RAW_M (GDMA_IN_DONE_CH2_INT_RAW_V << GDMA_IN_DONE_CH2_INT_RAW_S) +#define GDMA_IN_DONE_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_RAW_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel 0. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_RAW_M (GDMA_IN_SUC_EOF_CH2_INT_RAW_V << GDMA_IN_SUC_EOF_CH2_INT_RAW_S) +#define GDMA_IN_SUC_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_RAW_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw + * interrupt is reserved. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_RAW_M (GDMA_IN_ERR_EOF_CH2_INT_RAW_V << GDMA_IN_ERR_EOF_CH2_INT_RAW_S) +#define GDMA_IN_ERR_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_RAW_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel 0. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_M (GDMA_IN_DSCR_ERR_CH2_INT_RAW_V << GDMA_IN_DSCR_ERR_CH2_INT_RAW_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel 0. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_M (GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * overflow. + */ +#define GDMA_INFIFO_OVF_CH2_INT_RAW (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_RAW_M (GDMA_INFIFO_OVF_CH2_INT_RAW_V << GDMA_INFIFO_OVF_CH2_INT_RAW_S) +#define GDMA_INFIFO_OVF_CH2_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_RAW_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * underflow. + */ +#define GDMA_INFIFO_UDF_CH2_INT_RAW (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_RAW_M (GDMA_INFIFO_UDF_CH2_INT_RAW_V << GDMA_INFIFO_UDF_CH2_INT_RAW_S) +#define GDMA_INFIFO_UDF_CH2_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_RAW_S 6 + +/** GDMA_IN_INT_ST_CH2_REG register + * Masked interrupt of channel 0 + */ +#define GDMA_IN_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x24) +/** GDMA_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH2_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_ST_M (GDMA_IN_DONE_CH2_INT_ST_V << GDMA_IN_DONE_CH2_INT_ST_S) +#define GDMA_IN_DONE_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_ST_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_ST_M (GDMA_IN_SUC_EOF_CH2_INT_ST_V << GDMA_IN_SUC_EOF_CH2_INT_ST_S) +#define GDMA_IN_SUC_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_ST_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_ST_M (GDMA_IN_ERR_EOF_CH2_INT_ST_V << GDMA_IN_ERR_EOF_CH2_INT_ST_S) +#define GDMA_IN_ERR_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_ST_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_ST_M (GDMA_IN_DSCR_ERR_CH2_INT_ST_V << GDMA_IN_DSCR_ERR_CH2_INT_ST_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_ST_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_M (GDMA_IN_DSCR_EMPTY_CH2_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH2_INT_ST_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH2_INT_ST (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_ST_M (GDMA_INFIFO_OVF_CH2_INT_ST_V << GDMA_INFIFO_OVF_CH2_INT_ST_S) +#define GDMA_INFIFO_OVF_CH2_INT_ST_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_ST_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH2_INT_ST (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_ST_M (GDMA_INFIFO_UDF_CH2_INT_ST_V << GDMA_INFIFO_UDF_CH2_INT_ST_S) +#define GDMA_INFIFO_UDF_CH2_INT_ST_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_ST_S 6 + +/** GDMA_IN_INT_ENA_CH2_REG register + * Interrupt enable bits of channel 0 + */ +#define GDMA_IN_INT_ENA_CH2_REG (DR_REG_GDMA_BASE + 0x28) +/** GDMA_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH2_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_ENA_M (GDMA_IN_DONE_CH2_INT_ENA_V << GDMA_IN_DONE_CH2_INT_ENA_S) +#define GDMA_IN_DONE_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_ENA_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_ENA_M (GDMA_IN_SUC_EOF_CH2_INT_ENA_V << GDMA_IN_SUC_EOF_CH2_INT_ENA_S) +#define GDMA_IN_SUC_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_ENA_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_ENA_M (GDMA_IN_ERR_EOF_CH2_INT_ENA_V << GDMA_IN_ERR_EOF_CH2_INT_ENA_S) +#define GDMA_IN_ERR_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_ENA_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_M (GDMA_IN_DSCR_ERR_CH2_INT_ENA_V << GDMA_IN_DSCR_ERR_CH2_INT_ENA_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_M (GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH2_INT_ENA (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_ENA_M (GDMA_INFIFO_OVF_CH2_INT_ENA_V << GDMA_INFIFO_OVF_CH2_INT_ENA_S) +#define GDMA_INFIFO_OVF_CH2_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_ENA_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH2_INT_ENA (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_ENA_M (GDMA_INFIFO_UDF_CH2_INT_ENA_V << GDMA_INFIFO_UDF_CH2_INT_ENA_S) +#define GDMA_INFIFO_UDF_CH2_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_ENA_S 6 + +/** GDMA_IN_INT_CLR_CH2_REG register + * Interrupt clear bits of channel 0 + */ +#define GDMA_IN_INT_CLR_CH2_REG (DR_REG_GDMA_BASE + 0x2c) +/** GDMA_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH2_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_CLR_M (GDMA_IN_DONE_CH2_INT_CLR_V << GDMA_IN_DONE_CH2_INT_CLR_S) +#define GDMA_IN_DONE_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_CLR_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_CLR_M (GDMA_IN_SUC_EOF_CH2_INT_CLR_V << GDMA_IN_SUC_EOF_CH2_INT_CLR_S) +#define GDMA_IN_SUC_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_CLR_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_CLR_M (GDMA_IN_ERR_EOF_CH2_INT_CLR_V << GDMA_IN_ERR_EOF_CH2_INT_CLR_S) +#define GDMA_IN_ERR_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_CLR_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_M (GDMA_IN_DSCR_ERR_CH2_INT_CLR_V << GDMA_IN_DSCR_ERR_CH2_INT_CLR_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_M (GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH2_INT_CLR (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_CLR_M (GDMA_INFIFO_OVF_CH2_INT_CLR_V << GDMA_INFIFO_OVF_CH2_INT_CLR_S) +#define GDMA_INFIFO_OVF_CH2_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_CLR_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH2_INT_CLR (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_CLR_M (GDMA_INFIFO_UDF_CH2_INT_CLR_V << GDMA_INFIFO_UDF_CH2_INT_CLR_S) +#define GDMA_INFIFO_UDF_CH2_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_CLR_S 6 + +/** GDMA_OUT_INT_RAW_CH0_REG register + * Raw status interrupt of channel 0 + */ +#define GDMA_OUT_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x30) +/** GDMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 0. + */ +#define GDMA_OUT_DONE_CH0_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_RAW_M (GDMA_OUT_DONE_CH0_INT_RAW_V << GDMA_OUT_DONE_CH0_INT_RAW_S) +#define GDMA_OUT_DONE_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_RAW_S 0 +/** GDMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 0. + */ +#define GDMA_OUT_EOF_CH0_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_RAW_M (GDMA_OUT_EOF_CH0_INT_RAW_V << GDMA_OUT_EOF_CH0_INT_RAW_S) +#define GDMA_OUT_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_RAW_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel 0. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_M (GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 0. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * overflow. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_M (GDMA_OUTFIFO_OVF_CH0_INT_RAW_V << GDMA_OUTFIFO_OVF_CH0_INT_RAW_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * underflow. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_M (GDMA_OUTFIFO_UDF_CH0_INT_RAW_V << GDMA_OUTFIFO_UDF_CH0_INT_RAW_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_S 5 + +/** GDMA_OUT_INT_ST_CH0_REG register + * Masked interrupt of channel 0 + */ +#define GDMA_OUT_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x34) +/** GDMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH0_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_ST_M (GDMA_OUT_DONE_CH0_INT_ST_V << GDMA_OUT_DONE_CH0_INT_ST_S) +#define GDMA_OUT_DONE_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_ST_S 0 +/** GDMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH0_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_ST_M (GDMA_OUT_EOF_CH0_INT_ST_V << GDMA_OUT_EOF_CH0_INT_ST_S) +#define GDMA_OUT_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_ST_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_M (GDMA_OUT_DSCR_ERR_CH0_INT_ST_V << GDMA_OUT_DSCR_ERR_CH0_INT_ST_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_M (GDMA_OUT_TOTAL_EOF_CH0_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH0_INT_ST_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_ST_M (GDMA_OUTFIFO_OVF_CH0_INT_ST_V << GDMA_OUTFIFO_OVF_CH0_INT_ST_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_ST_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_ST_M (GDMA_OUTFIFO_UDF_CH0_INT_ST_V << GDMA_OUTFIFO_UDF_CH0_INT_ST_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_ST_S 5 + +/** GDMA_OUT_INT_ENA_CH0_REG register + * Interrupt enable bits of channel 0 + */ +#define GDMA_OUT_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x38) +/** GDMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH0_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_ENA_M (GDMA_OUT_DONE_CH0_INT_ENA_V << GDMA_OUT_DONE_CH0_INT_ENA_S) +#define GDMA_OUT_DONE_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_ENA_S 0 +/** GDMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH0_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_ENA_M (GDMA_OUT_EOF_CH0_INT_ENA_V << GDMA_OUT_EOF_CH0_INT_ENA_S) +#define GDMA_OUT_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_ENA_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_M (GDMA_OUT_DSCR_ERR_CH0_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH0_INT_ENA_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_M (GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_M (GDMA_OUTFIFO_OVF_CH0_INT_ENA_V << GDMA_OUTFIFO_OVF_CH0_INT_ENA_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_M (GDMA_OUTFIFO_UDF_CH0_INT_ENA_V << GDMA_OUTFIFO_UDF_CH0_INT_ENA_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_S 5 + +/** GDMA_OUT_INT_CLR_CH0_REG register + * Interrupt clear bits of channel 0 + */ +#define GDMA_OUT_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0x3c) +/** GDMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH0_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_CLR_M (GDMA_OUT_DONE_CH0_INT_CLR_V << GDMA_OUT_DONE_CH0_INT_CLR_S) +#define GDMA_OUT_DONE_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_CLR_S 0 +/** GDMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH0_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_CLR_M (GDMA_OUT_EOF_CH0_INT_CLR_V << GDMA_OUT_EOF_CH0_INT_CLR_S) +#define GDMA_OUT_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_CLR_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_M (GDMA_OUT_DSCR_ERR_CH0_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH0_INT_CLR_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_M (GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_M (GDMA_OUTFIFO_OVF_CH0_INT_CLR_V << GDMA_OUTFIFO_OVF_CH0_INT_CLR_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_M (GDMA_OUTFIFO_UDF_CH0_INT_CLR_V << GDMA_OUTFIFO_UDF_CH0_INT_CLR_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_S 5 + +/** GDMA_OUT_INT_RAW_CH1_REG register + * Raw status interrupt of channel 0 + */ +#define GDMA_OUT_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x40) +/** GDMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 0. + */ +#define GDMA_OUT_DONE_CH1_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_RAW_M (GDMA_OUT_DONE_CH1_INT_RAW_V << GDMA_OUT_DONE_CH1_INT_RAW_S) +#define GDMA_OUT_DONE_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_RAW_S 0 +/** GDMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 0. + */ +#define GDMA_OUT_EOF_CH1_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_RAW_M (GDMA_OUT_EOF_CH1_INT_RAW_V << GDMA_OUT_EOF_CH1_INT_RAW_S) +#define GDMA_OUT_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_RAW_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel 0. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_M (GDMA_OUT_DSCR_ERR_CH1_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH1_INT_RAW_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 0. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * overflow. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_M (GDMA_OUTFIFO_OVF_CH1_INT_RAW_V << GDMA_OUTFIFO_OVF_CH1_INT_RAW_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * underflow. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_M (GDMA_OUTFIFO_UDF_CH1_INT_RAW_V << GDMA_OUTFIFO_UDF_CH1_INT_RAW_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_S 5 + +/** GDMA_OUT_INT_ST_CH1_REG register + * Masked interrupt of channel 0 + */ +#define GDMA_OUT_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x44) +/** GDMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH1_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_ST_M (GDMA_OUT_DONE_CH1_INT_ST_V << GDMA_OUT_DONE_CH1_INT_ST_S) +#define GDMA_OUT_DONE_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_ST_S 0 +/** GDMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH1_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_ST_M (GDMA_OUT_EOF_CH1_INT_ST_V << GDMA_OUT_EOF_CH1_INT_ST_S) +#define GDMA_OUT_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_ST_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_M (GDMA_OUT_DSCR_ERR_CH1_INT_ST_V << GDMA_OUT_DSCR_ERR_CH1_INT_ST_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_M (GDMA_OUT_TOTAL_EOF_CH1_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH1_INT_ST_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_ST_M (GDMA_OUTFIFO_OVF_CH1_INT_ST_V << GDMA_OUTFIFO_OVF_CH1_INT_ST_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_ST_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_ST_M (GDMA_OUTFIFO_UDF_CH1_INT_ST_V << GDMA_OUTFIFO_UDF_CH1_INT_ST_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_ST_S 5 + +/** GDMA_OUT_INT_ENA_CH1_REG register + * Interrupt enable bits of channel 0 + */ +#define GDMA_OUT_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x48) +/** GDMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH1_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_ENA_M (GDMA_OUT_DONE_CH1_INT_ENA_V << GDMA_OUT_DONE_CH1_INT_ENA_S) +#define GDMA_OUT_DONE_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_ENA_S 0 +/** GDMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH1_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_ENA_M (GDMA_OUT_EOF_CH1_INT_ENA_V << GDMA_OUT_EOF_CH1_INT_ENA_S) +#define GDMA_OUT_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_ENA_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_M (GDMA_OUT_DSCR_ERR_CH1_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH1_INT_ENA_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_M (GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_M (GDMA_OUTFIFO_OVF_CH1_INT_ENA_V << GDMA_OUTFIFO_OVF_CH1_INT_ENA_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_M (GDMA_OUTFIFO_UDF_CH1_INT_ENA_V << GDMA_OUTFIFO_UDF_CH1_INT_ENA_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_S 5 + +/** GDMA_OUT_INT_CLR_CH1_REG register + * Interrupt clear bits of channel 0 + */ +#define GDMA_OUT_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x4c) +/** GDMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH1_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_CLR_M (GDMA_OUT_DONE_CH1_INT_CLR_V << GDMA_OUT_DONE_CH1_INT_CLR_S) +#define GDMA_OUT_DONE_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_CLR_S 0 +/** GDMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH1_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_CLR_M (GDMA_OUT_EOF_CH1_INT_CLR_V << GDMA_OUT_EOF_CH1_INT_CLR_S) +#define GDMA_OUT_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_CLR_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_M (GDMA_OUT_DSCR_ERR_CH1_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH1_INT_CLR_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_M (GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_M (GDMA_OUTFIFO_OVF_CH1_INT_CLR_V << GDMA_OUTFIFO_OVF_CH1_INT_CLR_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_M (GDMA_OUTFIFO_UDF_CH1_INT_CLR_V << GDMA_OUTFIFO_UDF_CH1_INT_CLR_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_S 5 + +/** GDMA_OUT_INT_RAW_CH2_REG register + * Raw status interrupt of channel 0 + */ +#define GDMA_OUT_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x50) +/** GDMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 0. + */ +#define GDMA_OUT_DONE_CH2_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_RAW_M (GDMA_OUT_DONE_CH2_INT_RAW_V << GDMA_OUT_DONE_CH2_INT_RAW_S) +#define GDMA_OUT_DONE_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_RAW_S 0 +/** GDMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 0. + */ +#define GDMA_OUT_EOF_CH2_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_RAW_M (GDMA_OUT_EOF_CH2_INT_RAW_V << GDMA_OUT_EOF_CH2_INT_RAW_S) +#define GDMA_OUT_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_RAW_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel 0. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_M (GDMA_OUT_DSCR_ERR_CH2_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH2_INT_RAW_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 0. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_M (GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * overflow. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW_M (GDMA_OUTFIFO_OVF_CH2_INT_RAW_V << GDMA_OUTFIFO_OVF_CH2_INT_RAW_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * underflow. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW_M (GDMA_OUTFIFO_UDF_CH2_INT_RAW_V << GDMA_OUTFIFO_UDF_CH2_INT_RAW_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW_S 5 + +/** GDMA_OUT_INT_ST_CH2_REG register + * Masked interrupt of channel 0 + */ +#define GDMA_OUT_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x54) +/** GDMA_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH2_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_ST_M (GDMA_OUT_DONE_CH2_INT_ST_V << GDMA_OUT_DONE_CH2_INT_ST_S) +#define GDMA_OUT_DONE_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_ST_S 0 +/** GDMA_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH2_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_ST_M (GDMA_OUT_EOF_CH2_INT_ST_V << GDMA_OUT_EOF_CH2_INT_ST_S) +#define GDMA_OUT_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_ST_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_M (GDMA_OUT_DSCR_ERR_CH2_INT_ST_V << GDMA_OUT_DSCR_ERR_CH2_INT_ST_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_M (GDMA_OUT_TOTAL_EOF_CH2_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH2_INT_ST_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_ST_M (GDMA_OUTFIFO_OVF_CH2_INT_ST_V << GDMA_OUTFIFO_OVF_CH2_INT_ST_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_ST_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_ST_M (GDMA_OUTFIFO_UDF_CH2_INT_ST_V << GDMA_OUTFIFO_UDF_CH2_INT_ST_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_ST_S 5 + +/** GDMA_OUT_INT_ENA_CH2_REG register + * Interrupt enable bits of channel 0 + */ +#define GDMA_OUT_INT_ENA_CH2_REG (DR_REG_GDMA_BASE + 0x58) +/** GDMA_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH2_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_ENA_M (GDMA_OUT_DONE_CH2_INT_ENA_V << GDMA_OUT_DONE_CH2_INT_ENA_S) +#define GDMA_OUT_DONE_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_ENA_S 0 +/** GDMA_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH2_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_ENA_M (GDMA_OUT_EOF_CH2_INT_ENA_V << GDMA_OUT_EOF_CH2_INT_ENA_S) +#define GDMA_OUT_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_ENA_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_M (GDMA_OUT_DSCR_ERR_CH2_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH2_INT_ENA_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_M (GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA_M (GDMA_OUTFIFO_OVF_CH2_INT_ENA_V << GDMA_OUTFIFO_OVF_CH2_INT_ENA_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA_M (GDMA_OUTFIFO_UDF_CH2_INT_ENA_V << GDMA_OUTFIFO_UDF_CH2_INT_ENA_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA_S 5 + +/** GDMA_OUT_INT_CLR_CH2_REG register + * Interrupt clear bits of channel 0 + */ +#define GDMA_OUT_INT_CLR_CH2_REG (DR_REG_GDMA_BASE + 0x5c) +/** GDMA_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH2_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_CLR_M (GDMA_OUT_DONE_CH2_INT_CLR_V << GDMA_OUT_DONE_CH2_INT_CLR_S) +#define GDMA_OUT_DONE_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_CLR_S 0 +/** GDMA_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH2_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_CLR_M (GDMA_OUT_EOF_CH2_INT_CLR_V << GDMA_OUT_EOF_CH2_INT_CLR_S) +#define GDMA_OUT_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_CLR_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_M (GDMA_OUT_DSCR_ERR_CH2_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH2_INT_CLR_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_M (GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR_M (GDMA_OUTFIFO_OVF_CH2_INT_CLR_V << GDMA_OUTFIFO_OVF_CH2_INT_CLR_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR_M (GDMA_OUTFIFO_UDF_CH2_INT_CLR_V << GDMA_OUTFIFO_UDF_CH2_INT_CLR_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR_S 5 + +/** GDMA_AHB_TEST_REG register + * reserved + */ +#define GDMA_AHB_TEST_REG (DR_REG_GDMA_BASE + 0x60) +/** GDMA_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0; + * reserved + */ +#define GDMA_AHB_TESTMODE 0x00000007U +#define GDMA_AHB_TESTMODE_M (GDMA_AHB_TESTMODE_V << GDMA_AHB_TESTMODE_S) +#define GDMA_AHB_TESTMODE_V 0x00000007U +#define GDMA_AHB_TESTMODE_S 0 +/** GDMA_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0; + * reserved + */ +#define GDMA_AHB_TESTADDR 0x00000003U +#define GDMA_AHB_TESTADDR_M (GDMA_AHB_TESTADDR_V << GDMA_AHB_TESTADDR_S) +#define GDMA_AHB_TESTADDR_V 0x00000003U +#define GDMA_AHB_TESTADDR_S 4 + +/** GDMA_MISC_CONF_REG register + * MISC register + */ +#define GDMA_MISC_CONF_REG (DR_REG_GDMA_BASE + 0x64) +/** GDMA_AHBM_RST_INTER : R/W; bitpos: [0]; default: 0; + * Set this bit then clear this bit to reset the internal ahb FSM. + */ +#define GDMA_AHBM_RST_INTER (BIT(0)) +#define GDMA_AHBM_RST_INTER_M (GDMA_AHBM_RST_INTER_V << GDMA_AHBM_RST_INTER_S) +#define GDMA_AHBM_RST_INTER_V 0x00000001U +#define GDMA_AHBM_RST_INTER_S 0 +/** GDMA_ARB_PRI_DIS : R/W; bitpos: [2]; default: 0; + * Set this bit to disable priority arbitration function. + */ +#define GDMA_ARB_PRI_DIS (BIT(2)) +#define GDMA_ARB_PRI_DIS_M (GDMA_ARB_PRI_DIS_V << GDMA_ARB_PRI_DIS_S) +#define GDMA_ARB_PRI_DIS_V 0x00000001U +#define GDMA_ARB_PRI_DIS_S 2 +/** GDMA_CLK_EN : R/W; bitpos: [3]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define GDMA_CLK_EN (BIT(3)) +#define GDMA_CLK_EN_M (GDMA_CLK_EN_V << GDMA_CLK_EN_S) +#define GDMA_CLK_EN_V 0x00000001U +#define GDMA_CLK_EN_S 3 + +/** GDMA_DATE_REG register + * Version control register + */ +#define GDMA_DATE_REG (DR_REG_GDMA_BASE + 0x68) +/** GDMA_DATE : R/W; bitpos: [31:0]; default: 35660368; + * register version. + */ +#define GDMA_DATE 0xFFFFFFFFU +#define GDMA_DATE_M (GDMA_DATE_V << GDMA_DATE_S) +#define GDMA_DATE_V 0xFFFFFFFFU +#define GDMA_DATE_S 0 + +/** GDMA_IN_CONF0_CH0_REG register + * Configure 0 register of Rx channel 0 + */ +#define GDMA_IN_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x70) +/** GDMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset GDMA channel 0 Rx FSM and Rx FIFO pointer. + */ +#define GDMA_IN_RST_CH0 (BIT(0)) +#define GDMA_IN_RST_CH0_M (GDMA_IN_RST_CH0_V << GDMA_IN_RST_CH0_S) +#define GDMA_IN_RST_CH0_V 0x00000001U +#define GDMA_IN_RST_CH0_S 0 +/** GDMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_IN_LOOP_TEST_CH0 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH0_M (GDMA_IN_LOOP_TEST_CH0_V << GDMA_IN_LOOP_TEST_CH0_S) +#define GDMA_IN_LOOP_TEST_CH0_V 0x00000001U +#define GDMA_IN_LOOP_TEST_CH0_S 1 +/** GDMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_INDSCR_BURST_EN_CH0 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH0_M (GDMA_INDSCR_BURST_EN_CH0_V << GDMA_INDSCR_BURST_EN_CH0_S) +#define GDMA_INDSCR_BURST_EN_CH0_V 0x00000001U +#define GDMA_INDSCR_BURST_EN_CH0_S 2 +/** GDMA_IN_DATA_BURST_EN_CH0 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data + * when accessing internal SRAM. + */ +#define GDMA_IN_DATA_BURST_EN_CH0 (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH0_M (GDMA_IN_DATA_BURST_EN_CH0_V << GDMA_IN_DATA_BURST_EN_CH0_S) +#define GDMA_IN_DATA_BURST_EN_CH0_V 0x00000001U +#define GDMA_IN_DATA_BURST_EN_CH0_S 3 +/** GDMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via GDMA. + */ +#define GDMA_MEM_TRANS_EN_CH0 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH0_M (GDMA_MEM_TRANS_EN_CH0_V << GDMA_MEM_TRANS_EN_CH0_S) +#define GDMA_MEM_TRANS_EN_CH0_V 0x00000001U +#define GDMA_MEM_TRANS_EN_CH0_S 4 +/** GDMA_IN_ETM_EN_CH0 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Rx channel 0 is triggered by etm + * task. + */ +#define GDMA_IN_ETM_EN_CH0 (BIT(5)) +#define GDMA_IN_ETM_EN_CH0_M (GDMA_IN_ETM_EN_CH0_V << GDMA_IN_ETM_EN_CH0_S) +#define GDMA_IN_ETM_EN_CH0_V 0x00000001U +#define GDMA_IN_ETM_EN_CH0_S 5 + +/** GDMA_IN_CONF1_CH0_REG register + * Configure 1 register of Rx channel 0 + */ +#define GDMA_IN_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0x74) +/** GDMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_IN_CHECK_OWNER_CH0 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH0_M (GDMA_IN_CHECK_OWNER_CH0_V << GDMA_IN_CHECK_OWNER_CH0_S) +#define GDMA_IN_CHECK_OWNER_CH0_V 0x00000001U +#define GDMA_IN_CHECK_OWNER_CH0_S 12 + +/** GDMA_INFIFO_STATUS_CH0_REG register + * Receive FIFO status of Rx channel 0 + */ +#define GDMA_INFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0x78) +/** GDMA_INFIFO_FULL_CH0 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 0. + */ +#define GDMA_INFIFO_FULL_CH0 (BIT(0)) +#define GDMA_INFIFO_FULL_CH0_M (GDMA_INFIFO_FULL_CH0_V << GDMA_INFIFO_FULL_CH0_S) +#define GDMA_INFIFO_FULL_CH0_V 0x00000001U +#define GDMA_INFIFO_FULL_CH0_S 0 +/** GDMA_INFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 0. + */ +#define GDMA_INFIFO_EMPTY_CH0 (BIT(1)) +#define GDMA_INFIFO_EMPTY_CH0_M (GDMA_INFIFO_EMPTY_CH0_V << GDMA_INFIFO_EMPTY_CH0_S) +#define GDMA_INFIFO_EMPTY_CH0_V 0x00000001U +#define GDMA_INFIFO_EMPTY_CH0_S 1 +/** GDMA_INFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + */ +#define GDMA_INFIFO_CNT_CH0 0x0000003FU +#define GDMA_INFIFO_CNT_CH0_M (GDMA_INFIFO_CNT_CH0_V << GDMA_INFIFO_CNT_CH0_S) +#define GDMA_INFIFO_CNT_CH0_V 0x0000003FU +#define GDMA_INFIFO_CNT_CH0_S 2 +/** GDMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_1B_CH0 (BIT(23)) +#define GDMA_IN_REMAIN_UNDER_1B_CH0_M (GDMA_IN_REMAIN_UNDER_1B_CH0_V << GDMA_IN_REMAIN_UNDER_1B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_1B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_1B_CH0_S 23 +/** GDMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_2B_CH0 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_2B_CH0_M (GDMA_IN_REMAIN_UNDER_2B_CH0_V << GDMA_IN_REMAIN_UNDER_2B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_2B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_2B_CH0_S 24 +/** GDMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_3B_CH0 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_3B_CH0_M (GDMA_IN_REMAIN_UNDER_3B_CH0_V << GDMA_IN_REMAIN_UNDER_3B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_3B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_3B_CH0_S 25 +/** GDMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_4B_CH0 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_4B_CH0_M (GDMA_IN_REMAIN_UNDER_4B_CH0_V << GDMA_IN_REMAIN_UNDER_4B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_4B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_4B_CH0_S 26 +/** GDMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define GDMA_IN_BUF_HUNGRY_CH0 (BIT(27)) +#define GDMA_IN_BUF_HUNGRY_CH0_M (GDMA_IN_BUF_HUNGRY_CH0_V << GDMA_IN_BUF_HUNGRY_CH0_S) +#define GDMA_IN_BUF_HUNGRY_CH0_V 0x00000001U +#define GDMA_IN_BUF_HUNGRY_CH0_S 27 + +/** GDMA_IN_POP_CH0_REG register + * Pop control register of Rx channel 0 + */ +#define GDMA_IN_POP_CH0_REG (DR_REG_GDMA_BASE + 0x7c) +/** GDMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from GDMA FIFO. + */ +#define GDMA_INFIFO_RDATA_CH0 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH0_M (GDMA_INFIFO_RDATA_CH0_V << GDMA_INFIFO_RDATA_CH0_S) +#define GDMA_INFIFO_RDATA_CH0_V 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH0_S 0 +/** GDMA_INFIFO_POP_CH0 : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from GDMA FIFO. + */ +#define GDMA_INFIFO_POP_CH0 (BIT(12)) +#define GDMA_INFIFO_POP_CH0_M (GDMA_INFIFO_POP_CH0_V << GDMA_INFIFO_POP_CH0_S) +#define GDMA_INFIFO_POP_CH0_V 0x00000001U +#define GDMA_INFIFO_POP_CH0_S 12 + +/** GDMA_IN_LINK_CH0_REG register + * Link descriptor configure and control register of Rx channel 0 + */ +#define GDMA_IN_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x80) +/** GDMA_INLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ +#define GDMA_INLINK_ADDR_CH0 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH0_M (GDMA_INLINK_ADDR_CH0_V << GDMA_INLINK_ADDR_CH0_S) +#define GDMA_INLINK_ADDR_CH0_V 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH0_S 0 +/** GDMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ +#define GDMA_INLINK_AUTO_RET_CH0 (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH0_M (GDMA_INLINK_AUTO_RET_CH0_V << GDMA_INLINK_AUTO_RET_CH0_S) +#define GDMA_INLINK_AUTO_RET_CH0_V 0x00000001U +#define GDMA_INLINK_AUTO_RET_CH0_S 20 +/** GDMA_INLINK_STOP_CH0 : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ +#define GDMA_INLINK_STOP_CH0 (BIT(21)) +#define GDMA_INLINK_STOP_CH0_M (GDMA_INLINK_STOP_CH0_V << GDMA_INLINK_STOP_CH0_S) +#define GDMA_INLINK_STOP_CH0_V 0x00000001U +#define GDMA_INLINK_STOP_CH0_S 21 +/** GDMA_INLINK_START_CH0 : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ +#define GDMA_INLINK_START_CH0 (BIT(22)) +#define GDMA_INLINK_START_CH0_M (GDMA_INLINK_START_CH0_V << GDMA_INLINK_START_CH0_S) +#define GDMA_INLINK_START_CH0_V 0x00000001U +#define GDMA_INLINK_START_CH0_S 22 +/** GDMA_INLINK_RESTART_CH0 : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ +#define GDMA_INLINK_RESTART_CH0 (BIT(23)) +#define GDMA_INLINK_RESTART_CH0_M (GDMA_INLINK_RESTART_CH0_V << GDMA_INLINK_RESTART_CH0_S) +#define GDMA_INLINK_RESTART_CH0_V 0x00000001U +#define GDMA_INLINK_RESTART_CH0_S 23 +/** GDMA_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ +#define GDMA_INLINK_PARK_CH0 (BIT(24)) +#define GDMA_INLINK_PARK_CH0_M (GDMA_INLINK_PARK_CH0_V << GDMA_INLINK_PARK_CH0_S) +#define GDMA_INLINK_PARK_CH0_V 0x00000001U +#define GDMA_INLINK_PARK_CH0_S 24 + +/** GDMA_IN_STATE_CH0_REG register + * Receive status of Rx channel 0 + */ +#define GDMA_IN_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x84) +/** GDMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ +#define GDMA_INLINK_DSCR_ADDR_CH0 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH0_M (GDMA_INLINK_DSCR_ADDR_CH0_V << GDMA_INLINK_DSCR_ADDR_CH0_S) +#define GDMA_INLINK_DSCR_ADDR_CH0_V 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH0_S 0 +/** GDMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_IN_DSCR_STATE_CH0 0x00000003U +#define GDMA_IN_DSCR_STATE_CH0_M (GDMA_IN_DSCR_STATE_CH0_V << GDMA_IN_DSCR_STATE_CH0_S) +#define GDMA_IN_DSCR_STATE_CH0_V 0x00000003U +#define GDMA_IN_DSCR_STATE_CH0_S 18 +/** GDMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_IN_STATE_CH0 0x00000007U +#define GDMA_IN_STATE_CH0_M (GDMA_IN_STATE_CH0_V << GDMA_IN_STATE_CH0_S) +#define GDMA_IN_STATE_CH0_V 0x00000007U +#define GDMA_IN_STATE_CH0_S 20 + +/** GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG register + * Inlink descriptor address when EOF occurs of Rx channel 0 + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x88) +/** GDMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_M (GDMA_IN_SUC_EOF_DES_ADDR_CH0_V << GDMA_IN_SUC_EOF_DES_ADDR_CH0_S) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_S 0 + +/** GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG register + * Inlink descriptor address when errors occur of Rx channel 0 + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x8c) +/** GDMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_M (GDMA_IN_ERR_EOF_DES_ADDR_CH0_V << GDMA_IN_ERR_EOF_DES_ADDR_CH0_S) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_S 0 + +/** GDMA_IN_DSCR_CH0_REG register + * Current inlink descriptor address of Rx channel 0 + */ +#define GDMA_IN_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0x90) +/** GDMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ +#define GDMA_INLINK_DSCR_CH0 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH0_M (GDMA_INLINK_DSCR_CH0_V << GDMA_INLINK_DSCR_CH0_S) +#define GDMA_INLINK_DSCR_CH0_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH0_S 0 + +/** GDMA_IN_DSCR_BF0_CH0_REG register + * The last inlink descriptor address of Rx channel 0 + */ +#define GDMA_IN_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0x94) +/** GDMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ +#define GDMA_INLINK_DSCR_BF0_CH0 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH0_M (GDMA_INLINK_DSCR_BF0_CH0_V << GDMA_INLINK_DSCR_BF0_CH0_S) +#define GDMA_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH0_S 0 + +/** GDMA_IN_DSCR_BF1_CH0_REG register + * The second-to-last inlink descriptor address of Rx channel 0 + */ +#define GDMA_IN_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0x98) +/** GDMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_INLINK_DSCR_BF1_CH0 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH0_M (GDMA_INLINK_DSCR_BF1_CH0_V << GDMA_INLINK_DSCR_BF1_CH0_S) +#define GDMA_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH0_S 0 + +/** GDMA_IN_PRI_CH0_REG register + * Priority register of Rx channel 0 + */ +#define GDMA_IN_PRI_CH0_REG (DR_REG_GDMA_BASE + 0x9c) +/** GDMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 0. The larger of the value the higher of the priority. + */ +#define GDMA_RX_PRI_CH0 0x0000000FU +#define GDMA_RX_PRI_CH0_M (GDMA_RX_PRI_CH0_V << GDMA_RX_PRI_CH0_S) +#define GDMA_RX_PRI_CH0_V 0x0000000FU +#define GDMA_RX_PRI_CH0_S 0 + +/** GDMA_IN_PERI_SEL_CH0_REG register + * Peripheral selection of Rx channel 0 + */ +#define GDMA_IN_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0xa0) +/** GDMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. + * 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 9: + * Parallel_IO. + */ +#define GDMA_PERI_IN_SEL_CH0 0x0000003FU +#define GDMA_PERI_IN_SEL_CH0_M (GDMA_PERI_IN_SEL_CH0_V << GDMA_PERI_IN_SEL_CH0_S) +#define GDMA_PERI_IN_SEL_CH0_V 0x0000003FU +#define GDMA_PERI_IN_SEL_CH0_S 0 + +/** GDMA_OUT_CONF0_CH0_REG register + * Configure 0 register of Tx channel 0 + */ +#define GDMA_OUT_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0xd0) +/** GDMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset GDMA channel 0 Tx FSM and Tx FIFO pointer. + */ +#define GDMA_OUT_RST_CH0 (BIT(0)) +#define GDMA_OUT_RST_CH0_M (GDMA_OUT_RST_CH0_V << GDMA_OUT_RST_CH0_S) +#define GDMA_OUT_RST_CH0_V 0x00000001U +#define GDMA_OUT_RST_CH0_S 0 +/** GDMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_OUT_LOOP_TEST_CH0 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH0_M (GDMA_OUT_LOOP_TEST_CH0_V << GDMA_OUT_LOOP_TEST_CH0_S) +#define GDMA_OUT_LOOP_TEST_CH0_V 0x00000001U +#define GDMA_OUT_LOOP_TEST_CH0_S 1 +/** GDMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ +#define GDMA_OUT_AUTO_WRBACK_CH0 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH0_M (GDMA_OUT_AUTO_WRBACK_CH0_V << GDMA_OUT_AUTO_WRBACK_CH0_S) +#define GDMA_OUT_AUTO_WRBACK_CH0_V 0x00000001U +#define GDMA_OUT_AUTO_WRBACK_CH0_S 2 +/** GDMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is + * generated when data need to transmit has been popped from FIFO in GDMA + */ +#define GDMA_OUT_EOF_MODE_CH0 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH0_M (GDMA_OUT_EOF_MODE_CH0_V << GDMA_OUT_EOF_MODE_CH0_S) +#define GDMA_OUT_EOF_MODE_CH0_V 0x00000001U +#define GDMA_OUT_EOF_MODE_CH0_S 3 +/** GDMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_OUTDSCR_BURST_EN_CH0 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH0_M (GDMA_OUTDSCR_BURST_EN_CH0_V << GDMA_OUTDSCR_BURST_EN_CH0_S) +#define GDMA_OUTDSCR_BURST_EN_CH0_V 0x00000001U +#define GDMA_OUTDSCR_BURST_EN_CH0_S 4 +/** GDMA_OUT_DATA_BURST_EN_CH0 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data + * when accessing internal SRAM. + */ +#define GDMA_OUT_DATA_BURST_EN_CH0 (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH0_M (GDMA_OUT_DATA_BURST_EN_CH0_V << GDMA_OUT_DATA_BURST_EN_CH0_S) +#define GDMA_OUT_DATA_BURST_EN_CH0_V 0x00000001U +#define GDMA_OUT_DATA_BURST_EN_CH0_S 5 +/** GDMA_OUT_ETM_EN_CH0 : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Tx channel 0 is triggered by etm + * task. + */ +#define GDMA_OUT_ETM_EN_CH0 (BIT(6)) +#define GDMA_OUT_ETM_EN_CH0_M (GDMA_OUT_ETM_EN_CH0_V << GDMA_OUT_ETM_EN_CH0_S) +#define GDMA_OUT_ETM_EN_CH0_V 0x00000001U +#define GDMA_OUT_ETM_EN_CH0_S 6 + +/** GDMA_OUT_CONF1_CH0_REG register + * Configure 1 register of Tx channel 0 + */ +#define GDMA_OUT_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0xd4) +/** GDMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_OUT_CHECK_OWNER_CH0 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH0_M (GDMA_OUT_CHECK_OWNER_CH0_V << GDMA_OUT_CHECK_OWNER_CH0_S) +#define GDMA_OUT_CHECK_OWNER_CH0_V 0x00000001U +#define GDMA_OUT_CHECK_OWNER_CH0_S 12 + +/** GDMA_OUTFIFO_STATUS_CH0_REG register + * Transmit FIFO status of Tx channel 0 + */ +#define GDMA_OUTFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0xd8) +/** GDMA_OUTFIFO_FULL_CH0 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 0. + */ +#define GDMA_OUTFIFO_FULL_CH0 (BIT(0)) +#define GDMA_OUTFIFO_FULL_CH0_M (GDMA_OUTFIFO_FULL_CH0_V << GDMA_OUTFIFO_FULL_CH0_S) +#define GDMA_OUTFIFO_FULL_CH0_V 0x00000001U +#define GDMA_OUTFIFO_FULL_CH0_S 0 +/** GDMA_OUTFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 0. + */ +#define GDMA_OUTFIFO_EMPTY_CH0 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_CH0_M (GDMA_OUTFIFO_EMPTY_CH0_V << GDMA_OUTFIFO_EMPTY_CH0_S) +#define GDMA_OUTFIFO_EMPTY_CH0_V 0x00000001U +#define GDMA_OUTFIFO_EMPTY_CH0_S 1 +/** GDMA_OUTFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + */ +#define GDMA_OUTFIFO_CNT_CH0 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH0_M (GDMA_OUTFIFO_CNT_CH0_V << GDMA_OUTFIFO_CNT_CH0_S) +#define GDMA_OUTFIFO_CNT_CH0_V 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH0_S 2 +/** GDMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_1B_CH0 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_CH0_M (GDMA_OUT_REMAIN_UNDER_1B_CH0_V << GDMA_OUT_REMAIN_UNDER_1B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_1B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_1B_CH0_S 23 +/** GDMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_2B_CH0 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_CH0_M (GDMA_OUT_REMAIN_UNDER_2B_CH0_V << GDMA_OUT_REMAIN_UNDER_2B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_2B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_2B_CH0_S 24 +/** GDMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_3B_CH0 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_CH0_M (GDMA_OUT_REMAIN_UNDER_3B_CH0_V << GDMA_OUT_REMAIN_UNDER_3B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_3B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_3B_CH0_S 25 +/** GDMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_4B_CH0 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_CH0_M (GDMA_OUT_REMAIN_UNDER_4B_CH0_V << GDMA_OUT_REMAIN_UNDER_4B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_4B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_4B_CH0_S 26 + +/** GDMA_OUT_PUSH_CH0_REG register + * Push control register of Rx channel 0 + */ +#define GDMA_OUT_PUSH_CH0_REG (DR_REG_GDMA_BASE + 0xdc) +/** GDMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into GDMA FIFO. + */ +#define GDMA_OUTFIFO_WDATA_CH0 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH0_M (GDMA_OUTFIFO_WDATA_CH0_V << GDMA_OUTFIFO_WDATA_CH0_S) +#define GDMA_OUTFIFO_WDATA_CH0_V 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH0_S 0 +/** GDMA_OUTFIFO_PUSH_CH0 : WT; bitpos: [9]; default: 0; + * Set this bit to push data into GDMA FIFO. + */ +#define GDMA_OUTFIFO_PUSH_CH0 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH0_M (GDMA_OUTFIFO_PUSH_CH0_V << GDMA_OUTFIFO_PUSH_CH0_S) +#define GDMA_OUTFIFO_PUSH_CH0_V 0x00000001U +#define GDMA_OUTFIFO_PUSH_CH0_S 9 + +/** GDMA_OUT_LINK_CH0_REG register + * Link descriptor configure and control register of Tx channel 0 + */ +#define GDMA_OUT_LINK_CH0_REG (DR_REG_GDMA_BASE + 0xe0) +/** GDMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ +#define GDMA_OUTLINK_ADDR_CH0 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH0_M (GDMA_OUTLINK_ADDR_CH0_V << GDMA_OUTLINK_ADDR_CH0_S) +#define GDMA_OUTLINK_ADDR_CH0_V 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH0_S 0 +/** GDMA_OUTLINK_STOP_CH0 : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_STOP_CH0 (BIT(20)) +#define GDMA_OUTLINK_STOP_CH0_M (GDMA_OUTLINK_STOP_CH0_V << GDMA_OUTLINK_STOP_CH0_S) +#define GDMA_OUTLINK_STOP_CH0_V 0x00000001U +#define GDMA_OUTLINK_STOP_CH0_S 20 +/** GDMA_OUTLINK_START_CH0 : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_START_CH0 (BIT(21)) +#define GDMA_OUTLINK_START_CH0_M (GDMA_OUTLINK_START_CH0_V << GDMA_OUTLINK_START_CH0_S) +#define GDMA_OUTLINK_START_CH0_V 0x00000001U +#define GDMA_OUTLINK_START_CH0_S 21 +/** GDMA_OUTLINK_RESTART_CH0 : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ +#define GDMA_OUTLINK_RESTART_CH0 (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH0_M (GDMA_OUTLINK_RESTART_CH0_V << GDMA_OUTLINK_RESTART_CH0_S) +#define GDMA_OUTLINK_RESTART_CH0_V 0x00000001U +#define GDMA_OUTLINK_RESTART_CH0_S 22 +/** GDMA_OUTLINK_PARK_CH0 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ +#define GDMA_OUTLINK_PARK_CH0 (BIT(23)) +#define GDMA_OUTLINK_PARK_CH0_M (GDMA_OUTLINK_PARK_CH0_V << GDMA_OUTLINK_PARK_CH0_S) +#define GDMA_OUTLINK_PARK_CH0_V 0x00000001U +#define GDMA_OUTLINK_PARK_CH0_S 23 + +/** GDMA_OUT_STATE_CH0_REG register + * Transmit status of Tx channel 0 + */ +#define GDMA_OUT_STATE_CH0_REG (DR_REG_GDMA_BASE + 0xe4) +/** GDMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ +#define GDMA_OUTLINK_DSCR_ADDR_CH0 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH0_M (GDMA_OUTLINK_DSCR_ADDR_CH0_V << GDMA_OUTLINK_DSCR_ADDR_CH0_S) +#define GDMA_OUTLINK_DSCR_ADDR_CH0_V 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH0_S 0 +/** GDMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_OUT_DSCR_STATE_CH0 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH0_M (GDMA_OUT_DSCR_STATE_CH0_V << GDMA_OUT_DSCR_STATE_CH0_S) +#define GDMA_OUT_DSCR_STATE_CH0_V 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH0_S 18 +/** GDMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_OUT_STATE_CH0 0x00000007U +#define GDMA_OUT_STATE_CH0_M (GDMA_OUT_STATE_CH0_V << GDMA_OUT_STATE_CH0_S) +#define GDMA_OUT_STATE_CH0_V 0x00000007U +#define GDMA_OUT_STATE_CH0_S 20 + +/** GDMA_OUT_EOF_DES_ADDR_CH0_REG register + * Outlink descriptor address when EOF occurs of Tx channel 0 + */ +#define GDMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xe8) +/** GDMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH0_M (GDMA_OUT_EOF_DES_ADDR_CH0_V << GDMA_OUT_EOF_DES_ADDR_CH0_S) +#define GDMA_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH0_S 0 + +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG register + * The last outlink descriptor address when EOF occurs of Tx channel 0 + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xec) +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_M (GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S 0 + +/** GDMA_OUT_DSCR_CH0_REG register + * Current inlink descriptor address of Tx channel 0 + */ +#define GDMA_OUT_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0xf0) +/** GDMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ +#define GDMA_OUTLINK_DSCR_CH0 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH0_M (GDMA_OUTLINK_DSCR_CH0_V << GDMA_OUTLINK_DSCR_CH0_S) +#define GDMA_OUTLINK_DSCR_CH0_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH0_S 0 + +/** GDMA_OUT_DSCR_BF0_CH0_REG register + * The last inlink descriptor address of Tx channel 0 + */ +#define GDMA_OUT_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0xf4) +/** GDMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ +#define GDMA_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH0_M (GDMA_OUTLINK_DSCR_BF0_CH0_V << GDMA_OUTLINK_DSCR_BF0_CH0_S) +#define GDMA_OUTLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH0_S 0 + +/** GDMA_OUT_DSCR_BF1_CH0_REG register + * The second-to-last inlink descriptor address of Tx channel 0 + */ +#define GDMA_OUT_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0xf8) +/** GDMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH0_M (GDMA_OUTLINK_DSCR_BF1_CH0_V << GDMA_OUTLINK_DSCR_BF1_CH0_S) +#define GDMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH0_S 0 + +/** GDMA_OUT_PRI_CH0_REG register + * Priority register of Tx channel 0. + */ +#define GDMA_OUT_PRI_CH0_REG (DR_REG_GDMA_BASE + 0xfc) +/** GDMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 0. The larger of the value the higher of the priority. + */ +#define GDMA_TX_PRI_CH0 0x0000000FU +#define GDMA_TX_PRI_CH0_M (GDMA_TX_PRI_CH0_V << GDMA_TX_PRI_CH0_S) +#define GDMA_TX_PRI_CH0_V 0x0000000FU +#define GDMA_TX_PRI_CH0_S 0 + +/** GDMA_OUT_PERI_SEL_CH0_REG register + * Peripheral selection of Tx channel 0 + */ +#define GDMA_OUT_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0x100) +/** GDMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. + * 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 9: + * Parallel_IO. + */ +#define GDMA_PERI_OUT_SEL_CH0 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH0_M (GDMA_PERI_OUT_SEL_CH0_V << GDMA_PERI_OUT_SEL_CH0_S) +#define GDMA_PERI_OUT_SEL_CH0_V 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH0_S 0 + +/** GDMA_IN_CONF0_CH1_REG register + * Configure 0 register of Rx channel 0 + */ +#define GDMA_IN_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x130) +/** GDMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset GDMA channel 0 Rx FSM and Rx FIFO pointer. + */ +#define GDMA_IN_RST_CH1 (BIT(0)) +#define GDMA_IN_RST_CH1_M (GDMA_IN_RST_CH1_V << GDMA_IN_RST_CH1_S) +#define GDMA_IN_RST_CH1_V 0x00000001U +#define GDMA_IN_RST_CH1_S 0 +/** GDMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_IN_LOOP_TEST_CH1 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH1_M (GDMA_IN_LOOP_TEST_CH1_V << GDMA_IN_LOOP_TEST_CH1_S) +#define GDMA_IN_LOOP_TEST_CH1_V 0x00000001U +#define GDMA_IN_LOOP_TEST_CH1_S 1 +/** GDMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_INDSCR_BURST_EN_CH1 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH1_M (GDMA_INDSCR_BURST_EN_CH1_V << GDMA_INDSCR_BURST_EN_CH1_S) +#define GDMA_INDSCR_BURST_EN_CH1_V 0x00000001U +#define GDMA_INDSCR_BURST_EN_CH1_S 2 +/** GDMA_IN_DATA_BURST_EN_CH1 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data + * when accessing internal SRAM. + */ +#define GDMA_IN_DATA_BURST_EN_CH1 (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH1_M (GDMA_IN_DATA_BURST_EN_CH1_V << GDMA_IN_DATA_BURST_EN_CH1_S) +#define GDMA_IN_DATA_BURST_EN_CH1_V 0x00000001U +#define GDMA_IN_DATA_BURST_EN_CH1_S 3 +/** GDMA_MEM_TRANS_EN_CH1 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via GDMA. + */ +#define GDMA_MEM_TRANS_EN_CH1 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH1_M (GDMA_MEM_TRANS_EN_CH1_V << GDMA_MEM_TRANS_EN_CH1_S) +#define GDMA_MEM_TRANS_EN_CH1_V 0x00000001U +#define GDMA_MEM_TRANS_EN_CH1_S 4 +/** GDMA_IN_ETM_EN_CH1 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Rx channel 0 is triggered by etm + * task. + */ +#define GDMA_IN_ETM_EN_CH1 (BIT(5)) +#define GDMA_IN_ETM_EN_CH1_M (GDMA_IN_ETM_EN_CH1_V << GDMA_IN_ETM_EN_CH1_S) +#define GDMA_IN_ETM_EN_CH1_V 0x00000001U +#define GDMA_IN_ETM_EN_CH1_S 5 + +/** GDMA_IN_CONF1_CH1_REG register + * Configure 1 register of Rx channel 0 + */ +#define GDMA_IN_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x134) +/** GDMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_IN_CHECK_OWNER_CH1 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH1_M (GDMA_IN_CHECK_OWNER_CH1_V << GDMA_IN_CHECK_OWNER_CH1_S) +#define GDMA_IN_CHECK_OWNER_CH1_V 0x00000001U +#define GDMA_IN_CHECK_OWNER_CH1_S 12 + +/** GDMA_INFIFO_STATUS_CH1_REG register + * Receive FIFO status of Rx channel 0 + */ +#define GDMA_INFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x138) +/** GDMA_INFIFO_FULL_CH1 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 0. + */ +#define GDMA_INFIFO_FULL_CH1 (BIT(0)) +#define GDMA_INFIFO_FULL_CH1_M (GDMA_INFIFO_FULL_CH1_V << GDMA_INFIFO_FULL_CH1_S) +#define GDMA_INFIFO_FULL_CH1_V 0x00000001U +#define GDMA_INFIFO_FULL_CH1_S 0 +/** GDMA_INFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 0. + */ +#define GDMA_INFIFO_EMPTY_CH1 (BIT(1)) +#define GDMA_INFIFO_EMPTY_CH1_M (GDMA_INFIFO_EMPTY_CH1_V << GDMA_INFIFO_EMPTY_CH1_S) +#define GDMA_INFIFO_EMPTY_CH1_V 0x00000001U +#define GDMA_INFIFO_EMPTY_CH1_S 1 +/** GDMA_INFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + */ +#define GDMA_INFIFO_CNT_CH1 0x0000003FU +#define GDMA_INFIFO_CNT_CH1_M (GDMA_INFIFO_CNT_CH1_V << GDMA_INFIFO_CNT_CH1_S) +#define GDMA_INFIFO_CNT_CH1_V 0x0000003FU +#define GDMA_INFIFO_CNT_CH1_S 2 +/** GDMA_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_1B_CH1 (BIT(23)) +#define GDMA_IN_REMAIN_UNDER_1B_CH1_M (GDMA_IN_REMAIN_UNDER_1B_CH1_V << GDMA_IN_REMAIN_UNDER_1B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_1B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_1B_CH1_S 23 +/** GDMA_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_2B_CH1 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_2B_CH1_M (GDMA_IN_REMAIN_UNDER_2B_CH1_V << GDMA_IN_REMAIN_UNDER_2B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_2B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_2B_CH1_S 24 +/** GDMA_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_3B_CH1 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_3B_CH1_M (GDMA_IN_REMAIN_UNDER_3B_CH1_V << GDMA_IN_REMAIN_UNDER_3B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_3B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_3B_CH1_S 25 +/** GDMA_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_4B_CH1 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_4B_CH1_M (GDMA_IN_REMAIN_UNDER_4B_CH1_V << GDMA_IN_REMAIN_UNDER_4B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_4B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_4B_CH1_S 26 +/** GDMA_IN_BUF_HUNGRY_CH1 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define GDMA_IN_BUF_HUNGRY_CH1 (BIT(27)) +#define GDMA_IN_BUF_HUNGRY_CH1_M (GDMA_IN_BUF_HUNGRY_CH1_V << GDMA_IN_BUF_HUNGRY_CH1_S) +#define GDMA_IN_BUF_HUNGRY_CH1_V 0x00000001U +#define GDMA_IN_BUF_HUNGRY_CH1_S 27 + +/** GDMA_IN_POP_CH1_REG register + * Pop control register of Rx channel 0 + */ +#define GDMA_IN_POP_CH1_REG (DR_REG_GDMA_BASE + 0x13c) +/** GDMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from GDMA FIFO. + */ +#define GDMA_INFIFO_RDATA_CH1 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH1_M (GDMA_INFIFO_RDATA_CH1_V << GDMA_INFIFO_RDATA_CH1_S) +#define GDMA_INFIFO_RDATA_CH1_V 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH1_S 0 +/** GDMA_INFIFO_POP_CH1 : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from GDMA FIFO. + */ +#define GDMA_INFIFO_POP_CH1 (BIT(12)) +#define GDMA_INFIFO_POP_CH1_M (GDMA_INFIFO_POP_CH1_V << GDMA_INFIFO_POP_CH1_S) +#define GDMA_INFIFO_POP_CH1_V 0x00000001U +#define GDMA_INFIFO_POP_CH1_S 12 + +/** GDMA_IN_LINK_CH1_REG register + * Link descriptor configure and control register of Rx channel 0 + */ +#define GDMA_IN_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x140) +/** GDMA_INLINK_ADDR_CH1 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ +#define GDMA_INLINK_ADDR_CH1 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH1_M (GDMA_INLINK_ADDR_CH1_V << GDMA_INLINK_ADDR_CH1_S) +#define GDMA_INLINK_ADDR_CH1_V 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH1_S 0 +/** GDMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ +#define GDMA_INLINK_AUTO_RET_CH1 (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH1_M (GDMA_INLINK_AUTO_RET_CH1_V << GDMA_INLINK_AUTO_RET_CH1_S) +#define GDMA_INLINK_AUTO_RET_CH1_V 0x00000001U +#define GDMA_INLINK_AUTO_RET_CH1_S 20 +/** GDMA_INLINK_STOP_CH1 : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ +#define GDMA_INLINK_STOP_CH1 (BIT(21)) +#define GDMA_INLINK_STOP_CH1_M (GDMA_INLINK_STOP_CH1_V << GDMA_INLINK_STOP_CH1_S) +#define GDMA_INLINK_STOP_CH1_V 0x00000001U +#define GDMA_INLINK_STOP_CH1_S 21 +/** GDMA_INLINK_START_CH1 : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ +#define GDMA_INLINK_START_CH1 (BIT(22)) +#define GDMA_INLINK_START_CH1_M (GDMA_INLINK_START_CH1_V << GDMA_INLINK_START_CH1_S) +#define GDMA_INLINK_START_CH1_V 0x00000001U +#define GDMA_INLINK_START_CH1_S 22 +/** GDMA_INLINK_RESTART_CH1 : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ +#define GDMA_INLINK_RESTART_CH1 (BIT(23)) +#define GDMA_INLINK_RESTART_CH1_M (GDMA_INLINK_RESTART_CH1_V << GDMA_INLINK_RESTART_CH1_S) +#define GDMA_INLINK_RESTART_CH1_V 0x00000001U +#define GDMA_INLINK_RESTART_CH1_S 23 +/** GDMA_INLINK_PARK_CH1 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ +#define GDMA_INLINK_PARK_CH1 (BIT(24)) +#define GDMA_INLINK_PARK_CH1_M (GDMA_INLINK_PARK_CH1_V << GDMA_INLINK_PARK_CH1_S) +#define GDMA_INLINK_PARK_CH1_V 0x00000001U +#define GDMA_INLINK_PARK_CH1_S 24 + +/** GDMA_IN_STATE_CH1_REG register + * Receive status of Rx channel 0 + */ +#define GDMA_IN_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x144) +/** GDMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ +#define GDMA_INLINK_DSCR_ADDR_CH1 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH1_M (GDMA_INLINK_DSCR_ADDR_CH1_V << GDMA_INLINK_DSCR_ADDR_CH1_S) +#define GDMA_INLINK_DSCR_ADDR_CH1_V 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH1_S 0 +/** GDMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_IN_DSCR_STATE_CH1 0x00000003U +#define GDMA_IN_DSCR_STATE_CH1_M (GDMA_IN_DSCR_STATE_CH1_V << GDMA_IN_DSCR_STATE_CH1_S) +#define GDMA_IN_DSCR_STATE_CH1_V 0x00000003U +#define GDMA_IN_DSCR_STATE_CH1_S 18 +/** GDMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_IN_STATE_CH1 0x00000007U +#define GDMA_IN_STATE_CH1_M (GDMA_IN_STATE_CH1_V << GDMA_IN_STATE_CH1_S) +#define GDMA_IN_STATE_CH1_V 0x00000007U +#define GDMA_IN_STATE_CH1_S 20 + +/** GDMA_IN_SUC_EOF_DES_ADDR_CH1_REG register + * Inlink descriptor address when EOF occurs of Rx channel 0 + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x148) +/** GDMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_M (GDMA_IN_SUC_EOF_DES_ADDR_CH1_V << GDMA_IN_SUC_EOF_DES_ADDR_CH1_S) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_S 0 + +/** GDMA_IN_ERR_EOF_DES_ADDR_CH1_REG register + * Inlink descriptor address when errors occur of Rx channel 0 + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x14c) +/** GDMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_M (GDMA_IN_ERR_EOF_DES_ADDR_CH1_V << GDMA_IN_ERR_EOF_DES_ADDR_CH1_S) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_S 0 + +/** GDMA_IN_DSCR_CH1_REG register + * Current inlink descriptor address of Rx channel 0 + */ +#define GDMA_IN_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x150) +/** GDMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ +#define GDMA_INLINK_DSCR_CH1 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH1_M (GDMA_INLINK_DSCR_CH1_V << GDMA_INLINK_DSCR_CH1_S) +#define GDMA_INLINK_DSCR_CH1_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH1_S 0 + +/** GDMA_IN_DSCR_BF0_CH1_REG register + * The last inlink descriptor address of Rx channel 0 + */ +#define GDMA_IN_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x154) +/** GDMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ +#define GDMA_INLINK_DSCR_BF0_CH1 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH1_M (GDMA_INLINK_DSCR_BF0_CH1_V << GDMA_INLINK_DSCR_BF0_CH1_S) +#define GDMA_INLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH1_S 0 + +/** GDMA_IN_DSCR_BF1_CH1_REG register + * The second-to-last inlink descriptor address of Rx channel 0 + */ +#define GDMA_IN_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x158) +/** GDMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_INLINK_DSCR_BF1_CH1 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH1_M (GDMA_INLINK_DSCR_BF1_CH1_V << GDMA_INLINK_DSCR_BF1_CH1_S) +#define GDMA_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH1_S 0 + +/** GDMA_IN_PRI_CH1_REG register + * Priority register of Rx channel 0 + */ +#define GDMA_IN_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x15c) +/** GDMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 0. The larger of the value the higher of the priority. + */ +#define GDMA_RX_PRI_CH1 0x0000000FU +#define GDMA_RX_PRI_CH1_M (GDMA_RX_PRI_CH1_V << GDMA_RX_PRI_CH1_S) +#define GDMA_RX_PRI_CH1_V 0x0000000FU +#define GDMA_RX_PRI_CH1_S 0 + +/** GDMA_IN_PERI_SEL_CH1_REG register + * Peripheral selection of Rx channel 0 + */ +#define GDMA_IN_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x160) +/** GDMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. + * 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 9: + * Parallel_IO. + */ +#define GDMA_PERI_IN_SEL_CH1 0x0000003FU +#define GDMA_PERI_IN_SEL_CH1_M (GDMA_PERI_IN_SEL_CH1_V << GDMA_PERI_IN_SEL_CH1_S) +#define GDMA_PERI_IN_SEL_CH1_V 0x0000003FU +#define GDMA_PERI_IN_SEL_CH1_S 0 + +/** GDMA_OUT_CONF0_CH1_REG register + * Configure 0 register of Tx channel 1 + */ +#define GDMA_OUT_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x190) +/** GDMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset GDMA channel 1 Tx FSM and Tx FIFO pointer. + */ +#define GDMA_OUT_RST_CH1 (BIT(0)) +#define GDMA_OUT_RST_CH1_M (GDMA_OUT_RST_CH1_V << GDMA_OUT_RST_CH1_S) +#define GDMA_OUT_RST_CH1_V 0x00000001U +#define GDMA_OUT_RST_CH1_S 0 +/** GDMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_OUT_LOOP_TEST_CH1 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH1_M (GDMA_OUT_LOOP_TEST_CH1_V << GDMA_OUT_LOOP_TEST_CH1_S) +#define GDMA_OUT_LOOP_TEST_CH1_V 0x00000001U +#define GDMA_OUT_LOOP_TEST_CH1_S 1 +/** GDMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ +#define GDMA_OUT_AUTO_WRBACK_CH1 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH1_M (GDMA_OUT_AUTO_WRBACK_CH1_V << GDMA_OUT_AUTO_WRBACK_CH1_S) +#define GDMA_OUT_AUTO_WRBACK_CH1_V 0x00000001U +#define GDMA_OUT_AUTO_WRBACK_CH1_S 2 +/** GDMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is + * generated when data need to transmit has been popped from FIFO in GDMA + */ +#define GDMA_OUT_EOF_MODE_CH1 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH1_M (GDMA_OUT_EOF_MODE_CH1_V << GDMA_OUT_EOF_MODE_CH1_S) +#define GDMA_OUT_EOF_MODE_CH1_V 0x00000001U +#define GDMA_OUT_EOF_MODE_CH1_S 3 +/** GDMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_OUTDSCR_BURST_EN_CH1 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH1_M (GDMA_OUTDSCR_BURST_EN_CH1_V << GDMA_OUTDSCR_BURST_EN_CH1_S) +#define GDMA_OUTDSCR_BURST_EN_CH1_V 0x00000001U +#define GDMA_OUTDSCR_BURST_EN_CH1_S 4 +/** GDMA_OUT_DATA_BURST_EN_CH1 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data + * when accessing internal SRAM. + */ +#define GDMA_OUT_DATA_BURST_EN_CH1 (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH1_M (GDMA_OUT_DATA_BURST_EN_CH1_V << GDMA_OUT_DATA_BURST_EN_CH1_S) +#define GDMA_OUT_DATA_BURST_EN_CH1_V 0x00000001U +#define GDMA_OUT_DATA_BURST_EN_CH1_S 5 +/** GDMA_OUT_ETM_EN_CH1 : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Tx channel 1 is triggered by etm + * task. + */ +#define GDMA_OUT_ETM_EN_CH1 (BIT(6)) +#define GDMA_OUT_ETM_EN_CH1_M (GDMA_OUT_ETM_EN_CH1_V << GDMA_OUT_ETM_EN_CH1_S) +#define GDMA_OUT_ETM_EN_CH1_V 0x00000001U +#define GDMA_OUT_ETM_EN_CH1_S 6 + +/** GDMA_OUT_CONF1_CH1_REG register + * Configure 1 register of Tx channel 0 + */ +#define GDMA_OUT_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x194) +/** GDMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_OUT_CHECK_OWNER_CH1 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH1_M (GDMA_OUT_CHECK_OWNER_CH1_V << GDMA_OUT_CHECK_OWNER_CH1_S) +#define GDMA_OUT_CHECK_OWNER_CH1_V 0x00000001U +#define GDMA_OUT_CHECK_OWNER_CH1_S 12 + +/** GDMA_OUTFIFO_STATUS_CH1_REG register + * Transmit FIFO status of Tx channel 0 + */ +#define GDMA_OUTFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x198) +/** GDMA_OUTFIFO_FULL_CH1 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 0. + */ +#define GDMA_OUTFIFO_FULL_CH1 (BIT(0)) +#define GDMA_OUTFIFO_FULL_CH1_M (GDMA_OUTFIFO_FULL_CH1_V << GDMA_OUTFIFO_FULL_CH1_S) +#define GDMA_OUTFIFO_FULL_CH1_V 0x00000001U +#define GDMA_OUTFIFO_FULL_CH1_S 0 +/** GDMA_OUTFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 0. + */ +#define GDMA_OUTFIFO_EMPTY_CH1 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_CH1_M (GDMA_OUTFIFO_EMPTY_CH1_V << GDMA_OUTFIFO_EMPTY_CH1_S) +#define GDMA_OUTFIFO_EMPTY_CH1_V 0x00000001U +#define GDMA_OUTFIFO_EMPTY_CH1_S 1 +/** GDMA_OUTFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + */ +#define GDMA_OUTFIFO_CNT_CH1 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH1_M (GDMA_OUTFIFO_CNT_CH1_V << GDMA_OUTFIFO_CNT_CH1_S) +#define GDMA_OUTFIFO_CNT_CH1_V 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH1_S 2 +/** GDMA_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_1B_CH1 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_CH1_M (GDMA_OUT_REMAIN_UNDER_1B_CH1_V << GDMA_OUT_REMAIN_UNDER_1B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_1B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_1B_CH1_S 23 +/** GDMA_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_2B_CH1 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_CH1_M (GDMA_OUT_REMAIN_UNDER_2B_CH1_V << GDMA_OUT_REMAIN_UNDER_2B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_2B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_2B_CH1_S 24 +/** GDMA_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_3B_CH1 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_CH1_M (GDMA_OUT_REMAIN_UNDER_3B_CH1_V << GDMA_OUT_REMAIN_UNDER_3B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_3B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_3B_CH1_S 25 +/** GDMA_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_4B_CH1 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_CH1_M (GDMA_OUT_REMAIN_UNDER_4B_CH1_V << GDMA_OUT_REMAIN_UNDER_4B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_4B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_4B_CH1_S 26 + +/** GDMA_OUT_PUSH_CH1_REG register + * Push control register of Rx channel 0 + */ +#define GDMA_OUT_PUSH_CH1_REG (DR_REG_GDMA_BASE + 0x19c) +/** GDMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into GDMA FIFO. + */ +#define GDMA_OUTFIFO_WDATA_CH1 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH1_M (GDMA_OUTFIFO_WDATA_CH1_V << GDMA_OUTFIFO_WDATA_CH1_S) +#define GDMA_OUTFIFO_WDATA_CH1_V 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH1_S 0 +/** GDMA_OUTFIFO_PUSH_CH1 : WT; bitpos: [9]; default: 0; + * Set this bit to push data into GDMA FIFO. + */ +#define GDMA_OUTFIFO_PUSH_CH1 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH1_M (GDMA_OUTFIFO_PUSH_CH1_V << GDMA_OUTFIFO_PUSH_CH1_S) +#define GDMA_OUTFIFO_PUSH_CH1_V 0x00000001U +#define GDMA_OUTFIFO_PUSH_CH1_S 9 + +/** GDMA_OUT_LINK_CH1_REG register + * Link descriptor configure and control register of Tx channel 0 + */ +#define GDMA_OUT_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x1a0) +/** GDMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ +#define GDMA_OUTLINK_ADDR_CH1 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH1_M (GDMA_OUTLINK_ADDR_CH1_V << GDMA_OUTLINK_ADDR_CH1_S) +#define GDMA_OUTLINK_ADDR_CH1_V 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH1_S 0 +/** GDMA_OUTLINK_STOP_CH1 : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_STOP_CH1 (BIT(20)) +#define GDMA_OUTLINK_STOP_CH1_M (GDMA_OUTLINK_STOP_CH1_V << GDMA_OUTLINK_STOP_CH1_S) +#define GDMA_OUTLINK_STOP_CH1_V 0x00000001U +#define GDMA_OUTLINK_STOP_CH1_S 20 +/** GDMA_OUTLINK_START_CH1 : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_START_CH1 (BIT(21)) +#define GDMA_OUTLINK_START_CH1_M (GDMA_OUTLINK_START_CH1_V << GDMA_OUTLINK_START_CH1_S) +#define GDMA_OUTLINK_START_CH1_V 0x00000001U +#define GDMA_OUTLINK_START_CH1_S 21 +/** GDMA_OUTLINK_RESTART_CH1 : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ +#define GDMA_OUTLINK_RESTART_CH1 (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH1_M (GDMA_OUTLINK_RESTART_CH1_V << GDMA_OUTLINK_RESTART_CH1_S) +#define GDMA_OUTLINK_RESTART_CH1_V 0x00000001U +#define GDMA_OUTLINK_RESTART_CH1_S 22 +/** GDMA_OUTLINK_PARK_CH1 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ +#define GDMA_OUTLINK_PARK_CH1 (BIT(23)) +#define GDMA_OUTLINK_PARK_CH1_M (GDMA_OUTLINK_PARK_CH1_V << GDMA_OUTLINK_PARK_CH1_S) +#define GDMA_OUTLINK_PARK_CH1_V 0x00000001U +#define GDMA_OUTLINK_PARK_CH1_S 23 + +/** GDMA_OUT_STATE_CH1_REG register + * Transmit status of Tx channel 0 + */ +#define GDMA_OUT_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x1a4) +/** GDMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ +#define GDMA_OUTLINK_DSCR_ADDR_CH1 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH1_M (GDMA_OUTLINK_DSCR_ADDR_CH1_V << GDMA_OUTLINK_DSCR_ADDR_CH1_S) +#define GDMA_OUTLINK_DSCR_ADDR_CH1_V 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH1_S 0 +/** GDMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_OUT_DSCR_STATE_CH1 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH1_M (GDMA_OUT_DSCR_STATE_CH1_V << GDMA_OUT_DSCR_STATE_CH1_S) +#define GDMA_OUT_DSCR_STATE_CH1_V 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH1_S 18 +/** GDMA_OUT_STATE_CH1 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_OUT_STATE_CH1 0x00000007U +#define GDMA_OUT_STATE_CH1_M (GDMA_OUT_STATE_CH1_V << GDMA_OUT_STATE_CH1_S) +#define GDMA_OUT_STATE_CH1_V 0x00000007U +#define GDMA_OUT_STATE_CH1_S 20 + +/** GDMA_OUT_EOF_DES_ADDR_CH1_REG register + * Outlink descriptor address when EOF occurs of Tx channel 0 + */ +#define GDMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1a8) +/** GDMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH1_M (GDMA_OUT_EOF_DES_ADDR_CH1_V << GDMA_OUT_EOF_DES_ADDR_CH1_S) +#define GDMA_OUT_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH1_S 0 + +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH1_REG register + * The last outlink descriptor address when EOF occurs of Tx channel 0 + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1ac) +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_M (GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0 + +/** GDMA_OUT_DSCR_CH1_REG register + * Current inlink descriptor address of Tx channel 0 + */ +#define GDMA_OUT_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x1b0) +/** GDMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ +#define GDMA_OUTLINK_DSCR_CH1 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH1_M (GDMA_OUTLINK_DSCR_CH1_V << GDMA_OUTLINK_DSCR_CH1_S) +#define GDMA_OUTLINK_DSCR_CH1_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH1_S 0 + +/** GDMA_OUT_DSCR_BF0_CH1_REG register + * The last inlink descriptor address of Tx channel 0 + */ +#define GDMA_OUT_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x1b4) +/** GDMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ +#define GDMA_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH1_M (GDMA_OUTLINK_DSCR_BF0_CH1_V << GDMA_OUTLINK_DSCR_BF0_CH1_S) +#define GDMA_OUTLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH1_S 0 + +/** GDMA_OUT_DSCR_BF1_CH1_REG register + * The second-to-last inlink descriptor address of Tx channel 0 + */ +#define GDMA_OUT_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x1b8) +/** GDMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH1_M (GDMA_OUTLINK_DSCR_BF1_CH1_V << GDMA_OUTLINK_DSCR_BF1_CH1_S) +#define GDMA_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH1_S 0 + +/** GDMA_OUT_PRI_CH1_REG register + * Priority register of Tx channel 0. + */ +#define GDMA_OUT_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x1bc) +/** GDMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 0. The larger of the value the higher of the priority. + */ +#define GDMA_TX_PRI_CH1 0x0000000FU +#define GDMA_TX_PRI_CH1_M (GDMA_TX_PRI_CH1_V << GDMA_TX_PRI_CH1_S) +#define GDMA_TX_PRI_CH1_V 0x0000000FU +#define GDMA_TX_PRI_CH1_S 0 + +/** GDMA_OUT_PERI_SEL_CH1_REG register + * Peripheral selection of Tx channel 0 + */ +#define GDMA_OUT_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x1c0) +/** GDMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. + * 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 9: + * Parallel_IO. + */ +#define GDMA_PERI_OUT_SEL_CH1 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH1_M (GDMA_PERI_OUT_SEL_CH1_V << GDMA_PERI_OUT_SEL_CH1_S) +#define GDMA_PERI_OUT_SEL_CH1_V 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH1_S 0 + +/** GDMA_IN_CONF0_CH2_REG register + * Configure 0 register of Rx channel 0 + */ +#define GDMA_IN_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x1f0) +/** GDMA_IN_RST_CH2 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset GDMA channel 0 Rx FSM and Rx FIFO pointer. + */ +#define GDMA_IN_RST_CH2 (BIT(0)) +#define GDMA_IN_RST_CH2_M (GDMA_IN_RST_CH2_V << GDMA_IN_RST_CH2_S) +#define GDMA_IN_RST_CH2_V 0x00000001U +#define GDMA_IN_RST_CH2_S 0 +/** GDMA_IN_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_IN_LOOP_TEST_CH2 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH2_M (GDMA_IN_LOOP_TEST_CH2_V << GDMA_IN_LOOP_TEST_CH2_S) +#define GDMA_IN_LOOP_TEST_CH2_V 0x00000001U +#define GDMA_IN_LOOP_TEST_CH2_S 1 +/** GDMA_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_INDSCR_BURST_EN_CH2 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH2_M (GDMA_INDSCR_BURST_EN_CH2_V << GDMA_INDSCR_BURST_EN_CH2_S) +#define GDMA_INDSCR_BURST_EN_CH2_V 0x00000001U +#define GDMA_INDSCR_BURST_EN_CH2_S 2 +/** GDMA_IN_DATA_BURST_EN_CH2 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data + * when accessing internal SRAM. + */ +#define GDMA_IN_DATA_BURST_EN_CH2 (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH2_M (GDMA_IN_DATA_BURST_EN_CH2_V << GDMA_IN_DATA_BURST_EN_CH2_S) +#define GDMA_IN_DATA_BURST_EN_CH2_V 0x00000001U +#define GDMA_IN_DATA_BURST_EN_CH2_S 3 +/** GDMA_MEM_TRANS_EN_CH2 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via GDMA. + */ +#define GDMA_MEM_TRANS_EN_CH2 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH2_M (GDMA_MEM_TRANS_EN_CH2_V << GDMA_MEM_TRANS_EN_CH2_S) +#define GDMA_MEM_TRANS_EN_CH2_V 0x00000001U +#define GDMA_MEM_TRANS_EN_CH2_S 4 +/** GDMA_IN_ETM_EN_CH2 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Rx channel 0 is triggered by etm + * task. + */ +#define GDMA_IN_ETM_EN_CH2 (BIT(5)) +#define GDMA_IN_ETM_EN_CH2_M (GDMA_IN_ETM_EN_CH2_V << GDMA_IN_ETM_EN_CH2_S) +#define GDMA_IN_ETM_EN_CH2_V 0x00000001U +#define GDMA_IN_ETM_EN_CH2_S 5 + +/** GDMA_IN_CONF1_CH2_REG register + * Configure 1 register of Rx channel 0 + */ +#define GDMA_IN_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x1f4) +/** GDMA_IN_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_IN_CHECK_OWNER_CH2 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH2_M (GDMA_IN_CHECK_OWNER_CH2_V << GDMA_IN_CHECK_OWNER_CH2_S) +#define GDMA_IN_CHECK_OWNER_CH2_V 0x00000001U +#define GDMA_IN_CHECK_OWNER_CH2_S 12 + +/** GDMA_INFIFO_STATUS_CH2_REG register + * Receive FIFO status of Rx channel 0 + */ +#define GDMA_INFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x1f8) +/** GDMA_INFIFO_FULL_CH2 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 0. + */ +#define GDMA_INFIFO_FULL_CH2 (BIT(0)) +#define GDMA_INFIFO_FULL_CH2_M (GDMA_INFIFO_FULL_CH2_V << GDMA_INFIFO_FULL_CH2_S) +#define GDMA_INFIFO_FULL_CH2_V 0x00000001U +#define GDMA_INFIFO_FULL_CH2_S 0 +/** GDMA_INFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 0. + */ +#define GDMA_INFIFO_EMPTY_CH2 (BIT(1)) +#define GDMA_INFIFO_EMPTY_CH2_M (GDMA_INFIFO_EMPTY_CH2_V << GDMA_INFIFO_EMPTY_CH2_S) +#define GDMA_INFIFO_EMPTY_CH2_V 0x00000001U +#define GDMA_INFIFO_EMPTY_CH2_S 1 +/** GDMA_INFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + */ +#define GDMA_INFIFO_CNT_CH2 0x0000003FU +#define GDMA_INFIFO_CNT_CH2_M (GDMA_INFIFO_CNT_CH2_V << GDMA_INFIFO_CNT_CH2_S) +#define GDMA_INFIFO_CNT_CH2_V 0x0000003FU +#define GDMA_INFIFO_CNT_CH2_S 2 +/** GDMA_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_1B_CH2 (BIT(23)) +#define GDMA_IN_REMAIN_UNDER_1B_CH2_M (GDMA_IN_REMAIN_UNDER_1B_CH2_V << GDMA_IN_REMAIN_UNDER_1B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_1B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_1B_CH2_S 23 +/** GDMA_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_2B_CH2 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_2B_CH2_M (GDMA_IN_REMAIN_UNDER_2B_CH2_V << GDMA_IN_REMAIN_UNDER_2B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_2B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_2B_CH2_S 24 +/** GDMA_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_3B_CH2 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_3B_CH2_M (GDMA_IN_REMAIN_UNDER_3B_CH2_V << GDMA_IN_REMAIN_UNDER_3B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_3B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_3B_CH2_S 25 +/** GDMA_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_4B_CH2 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_4B_CH2_M (GDMA_IN_REMAIN_UNDER_4B_CH2_V << GDMA_IN_REMAIN_UNDER_4B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_4B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_4B_CH2_S 26 +/** GDMA_IN_BUF_HUNGRY_CH2 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define GDMA_IN_BUF_HUNGRY_CH2 (BIT(27)) +#define GDMA_IN_BUF_HUNGRY_CH2_M (GDMA_IN_BUF_HUNGRY_CH2_V << GDMA_IN_BUF_HUNGRY_CH2_S) +#define GDMA_IN_BUF_HUNGRY_CH2_V 0x00000001U +#define GDMA_IN_BUF_HUNGRY_CH2_S 27 + +/** GDMA_IN_POP_CH2_REG register + * Pop control register of Rx channel 0 + */ +#define GDMA_IN_POP_CH2_REG (DR_REG_GDMA_BASE + 0x1fc) +/** GDMA_INFIFO_RDATA_CH2 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from GDMA FIFO. + */ +#define GDMA_INFIFO_RDATA_CH2 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH2_M (GDMA_INFIFO_RDATA_CH2_V << GDMA_INFIFO_RDATA_CH2_S) +#define GDMA_INFIFO_RDATA_CH2_V 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH2_S 0 +/** GDMA_INFIFO_POP_CH2 : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from GDMA FIFO. + */ +#define GDMA_INFIFO_POP_CH2 (BIT(12)) +#define GDMA_INFIFO_POP_CH2_M (GDMA_INFIFO_POP_CH2_V << GDMA_INFIFO_POP_CH2_S) +#define GDMA_INFIFO_POP_CH2_V 0x00000001U +#define GDMA_INFIFO_POP_CH2_S 12 + +/** GDMA_IN_LINK_CH2_REG register + * Link descriptor configure and control register of Rx channel 0 + */ +#define GDMA_IN_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x200) +/** GDMA_INLINK_ADDR_CH2 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ +#define GDMA_INLINK_ADDR_CH2 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH2_M (GDMA_INLINK_ADDR_CH2_V << GDMA_INLINK_ADDR_CH2_S) +#define GDMA_INLINK_ADDR_CH2_V 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH2_S 0 +/** GDMA_INLINK_AUTO_RET_CH2 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ +#define GDMA_INLINK_AUTO_RET_CH2 (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH2_M (GDMA_INLINK_AUTO_RET_CH2_V << GDMA_INLINK_AUTO_RET_CH2_S) +#define GDMA_INLINK_AUTO_RET_CH2_V 0x00000001U +#define GDMA_INLINK_AUTO_RET_CH2_S 20 +/** GDMA_INLINK_STOP_CH2 : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ +#define GDMA_INLINK_STOP_CH2 (BIT(21)) +#define GDMA_INLINK_STOP_CH2_M (GDMA_INLINK_STOP_CH2_V << GDMA_INLINK_STOP_CH2_S) +#define GDMA_INLINK_STOP_CH2_V 0x00000001U +#define GDMA_INLINK_STOP_CH2_S 21 +/** GDMA_INLINK_START_CH2 : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ +#define GDMA_INLINK_START_CH2 (BIT(22)) +#define GDMA_INLINK_START_CH2_M (GDMA_INLINK_START_CH2_V << GDMA_INLINK_START_CH2_S) +#define GDMA_INLINK_START_CH2_V 0x00000001U +#define GDMA_INLINK_START_CH2_S 22 +/** GDMA_INLINK_RESTART_CH2 : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ +#define GDMA_INLINK_RESTART_CH2 (BIT(23)) +#define GDMA_INLINK_RESTART_CH2_M (GDMA_INLINK_RESTART_CH2_V << GDMA_INLINK_RESTART_CH2_S) +#define GDMA_INLINK_RESTART_CH2_V 0x00000001U +#define GDMA_INLINK_RESTART_CH2_S 23 +/** GDMA_INLINK_PARK_CH2 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ +#define GDMA_INLINK_PARK_CH2 (BIT(24)) +#define GDMA_INLINK_PARK_CH2_M (GDMA_INLINK_PARK_CH2_V << GDMA_INLINK_PARK_CH2_S) +#define GDMA_INLINK_PARK_CH2_V 0x00000001U +#define GDMA_INLINK_PARK_CH2_S 24 + +/** GDMA_IN_STATE_CH2_REG register + * Receive status of Rx channel 0 + */ +#define GDMA_IN_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x204) +/** GDMA_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ +#define GDMA_INLINK_DSCR_ADDR_CH2 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH2_M (GDMA_INLINK_DSCR_ADDR_CH2_V << GDMA_INLINK_DSCR_ADDR_CH2_S) +#define GDMA_INLINK_DSCR_ADDR_CH2_V 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH2_S 0 +/** GDMA_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_IN_DSCR_STATE_CH2 0x00000003U +#define GDMA_IN_DSCR_STATE_CH2_M (GDMA_IN_DSCR_STATE_CH2_V << GDMA_IN_DSCR_STATE_CH2_S) +#define GDMA_IN_DSCR_STATE_CH2_V 0x00000003U +#define GDMA_IN_DSCR_STATE_CH2_S 18 +/** GDMA_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_IN_STATE_CH2 0x00000007U +#define GDMA_IN_STATE_CH2_M (GDMA_IN_STATE_CH2_V << GDMA_IN_STATE_CH2_S) +#define GDMA_IN_STATE_CH2_V 0x00000007U +#define GDMA_IN_STATE_CH2_S 20 + +/** GDMA_IN_SUC_EOF_DES_ADDR_CH2_REG register + * Inlink descriptor address when EOF occurs of Rx channel 0 + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x208) +/** GDMA_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_M (GDMA_IN_SUC_EOF_DES_ADDR_CH2_V << GDMA_IN_SUC_EOF_DES_ADDR_CH2_S) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_S 0 + +/** GDMA_IN_ERR_EOF_DES_ADDR_CH2_REG register + * Inlink descriptor address when errors occur of Rx channel 0 + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x20c) +/** GDMA_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_M (GDMA_IN_ERR_EOF_DES_ADDR_CH2_V << GDMA_IN_ERR_EOF_DES_ADDR_CH2_S) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_S 0 + +/** GDMA_IN_DSCR_CH2_REG register + * Current inlink descriptor address of Rx channel 0 + */ +#define GDMA_IN_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x210) +/** GDMA_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ +#define GDMA_INLINK_DSCR_CH2 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH2_M (GDMA_INLINK_DSCR_CH2_V << GDMA_INLINK_DSCR_CH2_S) +#define GDMA_INLINK_DSCR_CH2_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH2_S 0 + +/** GDMA_IN_DSCR_BF0_CH2_REG register + * The last inlink descriptor address of Rx channel 0 + */ +#define GDMA_IN_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x214) +/** GDMA_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ +#define GDMA_INLINK_DSCR_BF0_CH2 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH2_M (GDMA_INLINK_DSCR_BF0_CH2_V << GDMA_INLINK_DSCR_BF0_CH2_S) +#define GDMA_INLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH2_S 0 + +/** GDMA_IN_DSCR_BF1_CH2_REG register + * The second-to-last inlink descriptor address of Rx channel 0 + */ +#define GDMA_IN_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x218) +/** GDMA_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_INLINK_DSCR_BF1_CH2 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH2_M (GDMA_INLINK_DSCR_BF1_CH2_V << GDMA_INLINK_DSCR_BF1_CH2_S) +#define GDMA_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH2_S 0 + +/** GDMA_IN_PRI_CH2_REG register + * Priority register of Rx channel 0 + */ +#define GDMA_IN_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x21c) +/** GDMA_RX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 0. The larger of the value the higher of the priority. + */ +#define GDMA_RX_PRI_CH2 0x0000000FU +#define GDMA_RX_PRI_CH2_M (GDMA_RX_PRI_CH2_V << GDMA_RX_PRI_CH2_S) +#define GDMA_RX_PRI_CH2_V 0x0000000FU +#define GDMA_RX_PRI_CH2_S 0 + +/** GDMA_IN_PERI_SEL_CH2_REG register + * Peripheral selection of Rx channel 0 + */ +#define GDMA_IN_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x220) +/** GDMA_PERI_IN_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. + * 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 9: + * Parallel_IO. + */ +#define GDMA_PERI_IN_SEL_CH2 0x0000003FU +#define GDMA_PERI_IN_SEL_CH2_M (GDMA_PERI_IN_SEL_CH2_V << GDMA_PERI_IN_SEL_CH2_S) +#define GDMA_PERI_IN_SEL_CH2_V 0x0000003FU +#define GDMA_PERI_IN_SEL_CH2_S 0 + +/** GDMA_OUT_CONF0_CH2_REG register + * Configure 0 register of Tx channel 1 + */ +#define GDMA_OUT_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x250) +/** GDMA_OUT_RST_CH2 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset GDMA channel 1 Tx FSM and Tx FIFO pointer. + */ +#define GDMA_OUT_RST_CH2 (BIT(0)) +#define GDMA_OUT_RST_CH2_M (GDMA_OUT_RST_CH2_V << GDMA_OUT_RST_CH2_S) +#define GDMA_OUT_RST_CH2_V 0x00000001U +#define GDMA_OUT_RST_CH2_S 0 +/** GDMA_OUT_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_OUT_LOOP_TEST_CH2 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH2_M (GDMA_OUT_LOOP_TEST_CH2_V << GDMA_OUT_LOOP_TEST_CH2_S) +#define GDMA_OUT_LOOP_TEST_CH2_V 0x00000001U +#define GDMA_OUT_LOOP_TEST_CH2_S 1 +/** GDMA_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ +#define GDMA_OUT_AUTO_WRBACK_CH2 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH2_M (GDMA_OUT_AUTO_WRBACK_CH2_V << GDMA_OUT_AUTO_WRBACK_CH2_S) +#define GDMA_OUT_AUTO_WRBACK_CH2_V 0x00000001U +#define GDMA_OUT_AUTO_WRBACK_CH2_S 2 +/** GDMA_OUT_EOF_MODE_CH2 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is + * generated when data need to transmit has been popped from FIFO in GDMA + */ +#define GDMA_OUT_EOF_MODE_CH2 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH2_M (GDMA_OUT_EOF_MODE_CH2_V << GDMA_OUT_EOF_MODE_CH2_S) +#define GDMA_OUT_EOF_MODE_CH2_V 0x00000001U +#define GDMA_OUT_EOF_MODE_CH2_S 3 +/** GDMA_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_OUTDSCR_BURST_EN_CH2 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH2_M (GDMA_OUTDSCR_BURST_EN_CH2_V << GDMA_OUTDSCR_BURST_EN_CH2_S) +#define GDMA_OUTDSCR_BURST_EN_CH2_V 0x00000001U +#define GDMA_OUTDSCR_BURST_EN_CH2_S 4 +/** GDMA_OUT_DATA_BURST_EN_CH2 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data + * when accessing internal SRAM. + */ +#define GDMA_OUT_DATA_BURST_EN_CH2 (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH2_M (GDMA_OUT_DATA_BURST_EN_CH2_V << GDMA_OUT_DATA_BURST_EN_CH2_S) +#define GDMA_OUT_DATA_BURST_EN_CH2_V 0x00000001U +#define GDMA_OUT_DATA_BURST_EN_CH2_S 5 +/** GDMA_OUT_ETM_EN_CH2 : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Tx channel 1 is triggered by etm + * task. + */ +#define GDMA_OUT_ETM_EN_CH2 (BIT(6)) +#define GDMA_OUT_ETM_EN_CH2_M (GDMA_OUT_ETM_EN_CH2_V << GDMA_OUT_ETM_EN_CH2_S) +#define GDMA_OUT_ETM_EN_CH2_V 0x00000001U +#define GDMA_OUT_ETM_EN_CH2_S 6 + +/** GDMA_OUT_CONF1_CH2_REG register + * Configure 1 register of Tx channel 0 + */ +#define GDMA_OUT_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x254) +/** GDMA_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_OUT_CHECK_OWNER_CH2 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH2_M (GDMA_OUT_CHECK_OWNER_CH2_V << GDMA_OUT_CHECK_OWNER_CH2_S) +#define GDMA_OUT_CHECK_OWNER_CH2_V 0x00000001U +#define GDMA_OUT_CHECK_OWNER_CH2_S 12 + +/** GDMA_OUTFIFO_STATUS_CH2_REG register + * Transmit FIFO status of Tx channel 0 + */ +#define GDMA_OUTFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x258) +/** GDMA_OUTFIFO_FULL_CH2 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 0. + */ +#define GDMA_OUTFIFO_FULL_CH2 (BIT(0)) +#define GDMA_OUTFIFO_FULL_CH2_M (GDMA_OUTFIFO_FULL_CH2_V << GDMA_OUTFIFO_FULL_CH2_S) +#define GDMA_OUTFIFO_FULL_CH2_V 0x00000001U +#define GDMA_OUTFIFO_FULL_CH2_S 0 +/** GDMA_OUTFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 0. + */ +#define GDMA_OUTFIFO_EMPTY_CH2 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_CH2_M (GDMA_OUTFIFO_EMPTY_CH2_V << GDMA_OUTFIFO_EMPTY_CH2_S) +#define GDMA_OUTFIFO_EMPTY_CH2_V 0x00000001U +#define GDMA_OUTFIFO_EMPTY_CH2_S 1 +/** GDMA_OUTFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + */ +#define GDMA_OUTFIFO_CNT_CH2 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH2_M (GDMA_OUTFIFO_CNT_CH2_V << GDMA_OUTFIFO_CNT_CH2_S) +#define GDMA_OUTFIFO_CNT_CH2_V 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH2_S 2 +/** GDMA_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_1B_CH2 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_CH2_M (GDMA_OUT_REMAIN_UNDER_1B_CH2_V << GDMA_OUT_REMAIN_UNDER_1B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_1B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_1B_CH2_S 23 +/** GDMA_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_2B_CH2 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_CH2_M (GDMA_OUT_REMAIN_UNDER_2B_CH2_V << GDMA_OUT_REMAIN_UNDER_2B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_2B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_2B_CH2_S 24 +/** GDMA_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_3B_CH2 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_CH2_M (GDMA_OUT_REMAIN_UNDER_3B_CH2_V << GDMA_OUT_REMAIN_UNDER_3B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_3B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_3B_CH2_S 25 +/** GDMA_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_4B_CH2 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_CH2_M (GDMA_OUT_REMAIN_UNDER_4B_CH2_V << GDMA_OUT_REMAIN_UNDER_4B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_4B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_4B_CH2_S 26 + +/** GDMA_OUT_PUSH_CH2_REG register + * Push control register of Rx channel 0 + */ +#define GDMA_OUT_PUSH_CH2_REG (DR_REG_GDMA_BASE + 0x25c) +/** GDMA_OUTFIFO_WDATA_CH2 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into GDMA FIFO. + */ +#define GDMA_OUTFIFO_WDATA_CH2 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH2_M (GDMA_OUTFIFO_WDATA_CH2_V << GDMA_OUTFIFO_WDATA_CH2_S) +#define GDMA_OUTFIFO_WDATA_CH2_V 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH2_S 0 +/** GDMA_OUTFIFO_PUSH_CH2 : WT; bitpos: [9]; default: 0; + * Set this bit to push data into GDMA FIFO. + */ +#define GDMA_OUTFIFO_PUSH_CH2 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH2_M (GDMA_OUTFIFO_PUSH_CH2_V << GDMA_OUTFIFO_PUSH_CH2_S) +#define GDMA_OUTFIFO_PUSH_CH2_V 0x00000001U +#define GDMA_OUTFIFO_PUSH_CH2_S 9 + +/** GDMA_OUT_LINK_CH2_REG register + * Link descriptor configure and control register of Tx channel 0 + */ +#define GDMA_OUT_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x260) +/** GDMA_OUTLINK_ADDR_CH2 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ +#define GDMA_OUTLINK_ADDR_CH2 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH2_M (GDMA_OUTLINK_ADDR_CH2_V << GDMA_OUTLINK_ADDR_CH2_S) +#define GDMA_OUTLINK_ADDR_CH2_V 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH2_S 0 +/** GDMA_OUTLINK_STOP_CH2 : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_STOP_CH2 (BIT(20)) +#define GDMA_OUTLINK_STOP_CH2_M (GDMA_OUTLINK_STOP_CH2_V << GDMA_OUTLINK_STOP_CH2_S) +#define GDMA_OUTLINK_STOP_CH2_V 0x00000001U +#define GDMA_OUTLINK_STOP_CH2_S 20 +/** GDMA_OUTLINK_START_CH2 : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_START_CH2 (BIT(21)) +#define GDMA_OUTLINK_START_CH2_M (GDMA_OUTLINK_START_CH2_V << GDMA_OUTLINK_START_CH2_S) +#define GDMA_OUTLINK_START_CH2_V 0x00000001U +#define GDMA_OUTLINK_START_CH2_S 21 +/** GDMA_OUTLINK_RESTART_CH2 : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ +#define GDMA_OUTLINK_RESTART_CH2 (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH2_M (GDMA_OUTLINK_RESTART_CH2_V << GDMA_OUTLINK_RESTART_CH2_S) +#define GDMA_OUTLINK_RESTART_CH2_V 0x00000001U +#define GDMA_OUTLINK_RESTART_CH2_S 22 +/** GDMA_OUTLINK_PARK_CH2 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ +#define GDMA_OUTLINK_PARK_CH2 (BIT(23)) +#define GDMA_OUTLINK_PARK_CH2_M (GDMA_OUTLINK_PARK_CH2_V << GDMA_OUTLINK_PARK_CH2_S) +#define GDMA_OUTLINK_PARK_CH2_V 0x00000001U +#define GDMA_OUTLINK_PARK_CH2_S 23 + +/** GDMA_OUT_STATE_CH2_REG register + * Transmit status of Tx channel 0 + */ +#define GDMA_OUT_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x264) +/** GDMA_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ +#define GDMA_OUTLINK_DSCR_ADDR_CH2 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH2_M (GDMA_OUTLINK_DSCR_ADDR_CH2_V << GDMA_OUTLINK_DSCR_ADDR_CH2_S) +#define GDMA_OUTLINK_DSCR_ADDR_CH2_V 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH2_S 0 +/** GDMA_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_OUT_DSCR_STATE_CH2 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH2_M (GDMA_OUT_DSCR_STATE_CH2_V << GDMA_OUT_DSCR_STATE_CH2_S) +#define GDMA_OUT_DSCR_STATE_CH2_V 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH2_S 18 +/** GDMA_OUT_STATE_CH2 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_OUT_STATE_CH2 0x00000007U +#define GDMA_OUT_STATE_CH2_M (GDMA_OUT_STATE_CH2_V << GDMA_OUT_STATE_CH2_S) +#define GDMA_OUT_STATE_CH2_V 0x00000007U +#define GDMA_OUT_STATE_CH2_S 20 + +/** GDMA_OUT_EOF_DES_ADDR_CH2_REG register + * Outlink descriptor address when EOF occurs of Tx channel 0 + */ +#define GDMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x268) +/** GDMA_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH2_M (GDMA_OUT_EOF_DES_ADDR_CH2_V << GDMA_OUT_EOF_DES_ADDR_CH2_S) +#define GDMA_OUT_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH2_S 0 + +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH2_REG register + * The last outlink descriptor address when EOF occurs of Tx channel 0 + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x26c) +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_M (GDMA_OUT_EOF_BFR_DES_ADDR_CH2_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH2_S) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_S 0 + +/** GDMA_OUT_DSCR_CH2_REG register + * Current inlink descriptor address of Tx channel 0 + */ +#define GDMA_OUT_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x270) +/** GDMA_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ +#define GDMA_OUTLINK_DSCR_CH2 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH2_M (GDMA_OUTLINK_DSCR_CH2_V << GDMA_OUTLINK_DSCR_CH2_S) +#define GDMA_OUTLINK_DSCR_CH2_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH2_S 0 + +/** GDMA_OUT_DSCR_BF0_CH2_REG register + * The last inlink descriptor address of Tx channel 0 + */ +#define GDMA_OUT_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x274) +/** GDMA_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ +#define GDMA_OUTLINK_DSCR_BF0_CH2 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH2_M (GDMA_OUTLINK_DSCR_BF0_CH2_V << GDMA_OUTLINK_DSCR_BF0_CH2_S) +#define GDMA_OUTLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH2_S 0 + +/** GDMA_OUT_DSCR_BF1_CH2_REG register + * The second-to-last inlink descriptor address of Tx channel 0 + */ +#define GDMA_OUT_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x278) +/** GDMA_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_OUTLINK_DSCR_BF1_CH2 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH2_M (GDMA_OUTLINK_DSCR_BF1_CH2_V << GDMA_OUTLINK_DSCR_BF1_CH2_S) +#define GDMA_OUTLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH2_S 0 + +/** GDMA_OUT_PRI_CH2_REG register + * Priority register of Tx channel 0. + */ +#define GDMA_OUT_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x27c) +/** GDMA_TX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 0. The larger of the value the higher of the priority. + */ +#define GDMA_TX_PRI_CH2 0x0000000FU +#define GDMA_TX_PRI_CH2_M (GDMA_TX_PRI_CH2_V << GDMA_TX_PRI_CH2_S) +#define GDMA_TX_PRI_CH2_V 0x0000000FU +#define GDMA_TX_PRI_CH2_S 0 + +/** GDMA_OUT_PERI_SEL_CH2_REG register + * Peripheral selection of Tx channel 0 + */ +#define GDMA_OUT_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x280) +/** GDMA_PERI_OUT_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. + * 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 9: + * Parallel_IO. + */ +#define GDMA_PERI_OUT_SEL_CH2 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH2_M (GDMA_PERI_OUT_SEL_CH2_V << GDMA_PERI_OUT_SEL_CH2_S) +#define GDMA_PERI_OUT_SEL_CH2_V 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH2_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/gdma_struct.h b/components/soc/esp32c6/include/soc/gdma_struct.h new file mode 100644 index 0000000000..7e4e641686 --- /dev/null +++ b/components/soc/esp32c6/include/soc/gdma_struct.h @@ -0,0 +1,995 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Interrupt Registers */ +/** Type of in_int_raw_chn register + * Raw status interrupt of channel 0 + */ +typedef union { + struct { + /** in_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. + */ + uint32_t in_done_int_raw:1; + /** in_suc_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel 0. + */ + uint32_t in_suc_eof_int_raw:1; + /** in_err_eof_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw + * interrupt is reserved. + */ + uint32_t in_err_eof_int_raw:1; + /** in_dscr_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel 0. + */ + uint32_t in_dscr_err_int_raw:1; + /** in_dscr_empty_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel 0. + */ + uint32_t in_dscr_empty_int_raw:1; + /** infifo_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * overflow. + */ + uint32_t infifo_ovf_int_raw:1; + /** infifo_udf_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * underflow. + */ + uint32_t infifo_udf_int_raw:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_raw_chn_reg_t; + +/** Type of in_int_st_chn register + * Masked interrupt of channel 0 + */ +typedef union { + struct { + /** in_done_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ + uint32_t in_done_int_st:1; + /** in_suc_eof_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ + uint32_t in_suc_eof_int_st:1; + /** in_err_eof_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ + uint32_t in_err_eof_int_st:1; + /** in_dscr_err_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + uint32_t in_dscr_err_int_st:1; + /** in_dscr_empty_int_st : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + uint32_t in_dscr_empty_int_st:1; + /** infifo_ovf_int_st : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t infifo_ovf_int_st:1; + /** infifo_udf_int_st : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t infifo_udf_int_st:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_st_chn_reg_t; + +/** Type of in_int_ena_chn register + * Interrupt enable bits of channel 0 + */ +typedef union { + struct { + /** in_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ + uint32_t in_done_int_ena:1; + /** in_suc_eof_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ + uint32_t in_suc_eof_int_ena:1; + /** in_err_eof_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ + uint32_t in_err_eof_int_ena:1; + /** in_dscr_err_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + uint32_t in_dscr_err_int_ena:1; + /** in_dscr_empty_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + uint32_t in_dscr_empty_int_ena:1; + /** infifo_ovf_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t infifo_ovf_int_ena:1; + /** infifo_udf_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t infifo_udf_int_ena:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_ena_chn_reg_t; + +/** Type of in_int_clr_chn register + * Interrupt clear bits of channel 0 + */ +typedef union { + struct { + /** in_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ + uint32_t in_done_int_clr:1; + /** in_suc_eof_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ + uint32_t in_suc_eof_int_clr:1; + /** in_err_eof_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ + uint32_t in_err_eof_int_clr:1; + /** in_dscr_err_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ + uint32_t in_dscr_err_int_clr:1; + /** in_dscr_empty_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ + uint32_t in_dscr_empty_int_clr:1; + /** infifo_ovf_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t infifo_ovf_int_clr:1; + /** infifo_udf_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t infifo_udf_int_clr:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_clr_chn_reg_t; + +/** Type of out_int_raw_chn register + * Raw status interrupt of channel 0 + */ +typedef union { + struct { + /** out_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 0. + */ + uint32_t out_done_int_raw:1; + /** out_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 0. + */ + uint32_t out_eof_int_raw:1; + /** out_dscr_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel 0. + */ + uint32_t out_dscr_err_int_raw:1; + /** out_total_eof_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 0. + */ + uint32_t out_total_eof_int_raw:1; + /** outfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * overflow. + */ + uint32_t outfifo_ovf_int_raw:1; + /** outfifo_udf_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * underflow. + */ + uint32_t outfifo_udf_int_raw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_raw_chn_reg_t; + +/** Type of out_int_st_chn register + * Masked interrupt of channel 0 + */ +typedef union { + struct { + /** out_done_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ + uint32_t out_done_int_st:1; + /** out_eof_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ + uint32_t out_eof_int_st:1; + /** out_dscr_err_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + uint32_t out_dscr_err_int_st:1; + /** out_total_eof_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + uint32_t out_total_eof_int_st:1; + /** outfifo_ovf_int_st : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t outfifo_ovf_int_st:1; + /** outfifo_udf_int_st : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t outfifo_udf_int_st:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_st_chn_reg_t; + +/** Type of out_int_ena_chn register + * Interrupt enable bits of channel 0 + */ +typedef union { + struct { + /** out_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ + uint32_t out_done_int_ena:1; + /** out_eof_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ + uint32_t out_eof_int_ena:1; + /** out_dscr_err_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + uint32_t out_dscr_err_int_ena:1; + /** out_total_eof_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + uint32_t out_total_eof_int_ena:1; + /** outfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t outfifo_ovf_int_ena:1; + /** outfifo_udf_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t outfifo_udf_int_ena:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_ena_chn_reg_t; + +/** Type of out_int_clr_chn register + * Interrupt clear bits of channel 0 + */ +typedef union { + struct { + /** out_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ + uint32_t out_done_int_clr:1; + /** out_eof_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ + uint32_t out_eof_int_clr:1; + /** out_dscr_err_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ + uint32_t out_dscr_err_int_clr:1; + /** out_total_eof_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ + uint32_t out_total_eof_int_clr:1; + /** outfifo_ovf_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t outfifo_ovf_int_clr:1; + /** outfifo_udf_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t outfifo_udf_int_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_clr_chn_reg_t; + + +/** Group: Debug Registers */ +/** Type of ahb_test register + * reserved + */ +typedef union { + struct { + /** ahb_testmode : R/W; bitpos: [2:0]; default: 0; + * reserved + */ + uint32_t ahb_testmode:3; + uint32_t reserved_3:1; + /** ahb_testaddr : R/W; bitpos: [5:4]; default: 0; + * reserved + */ + uint32_t ahb_testaddr:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_ahb_test_reg_t; + + +/** Group: Configuration Registers */ +/** Type of misc_conf register + * MISC register + */ +typedef union { + struct { + /** ahbm_rst_inter : R/W; bitpos: [0]; default: 0; + * Set this bit then clear this bit to reset the internal ahb FSM. + */ + uint32_t ahbm_rst_inter:1; + uint32_t reserved_1:1; + /** arb_pri_dis : R/W; bitpos: [2]; default: 0; + * Set this bit to disable priority arbitration function. + */ + uint32_t arb_pri_dis:1; + /** clk_en : R/W; bitpos: [3]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_misc_conf_reg_t; + +/** Type of in_conf0_chn register + * Configure 0 register of Rx channel 0 + */ +typedef union { + struct { + /** in_rst : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + */ + uint32_t in_rst:1; + /** in_loop_test : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t in_loop_test:1; + /** indscr_burst_en : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link + * descriptor when accessing internal SRAM. + */ + uint32_t indscr_burst_en:1; + /** in_data_burst_en : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data + * when accessing internal SRAM. + */ + uint32_t in_data_burst_en:1; + /** mem_trans_en : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + */ + uint32_t mem_trans_en:1; + /** in_etm_en : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm + * task. + */ + uint32_t in_etm_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_in_conf0_chn_reg_t; + +/** Type of in_conf1_chn register + * Configure 1 register of Rx channel 0 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** in_check_owner : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ + uint32_t in_check_owner:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_in_conf1_chn_reg_t; + +/** Type of in_pop_chn register + * Pop control register of Rx channel 0 + */ +typedef union { + struct { + /** infifo_rdata : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from DMA FIFO. + */ + uint32_t infifo_rdata:12; + /** infifo_pop : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from DMA FIFO. + */ + uint32_t infifo_pop:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_in_pop_chn_reg_t; + +/** Type of in_link_chn register + * Link descriptor configure and control register of Rx channel 0 + */ +typedef union { + struct { + /** inlink_addr : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ + uint32_t inlink_addr:20; + /** inlink_auto_ret : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ + uint32_t inlink_auto_ret:1; + /** inlink_stop : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ + uint32_t inlink_stop:1; + /** inlink_start : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ + uint32_t inlink_start:1; + /** inlink_restart : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ + uint32_t inlink_restart:1; + /** inlink_park : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ + uint32_t inlink_park:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} gdma_in_link_chn_reg_t; + +/** Type of out_conf0_chn register + * Configure 0 register of Tx channel 0 + */ +typedef union { + struct { + /** out_rst : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. + */ + uint32_t out_rst:1; + /** out_loop_test : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t out_loop_test:1; + /** out_auto_wrback : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ + uint32_t out_auto_wrback:1; + /** out_eof_mode : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is + * generated when data need to transmit has been popped from FIFO in DMA + */ + uint32_t out_eof_mode:1; + /** outdscr_burst_en : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link + * descriptor when accessing internal SRAM. + */ + uint32_t outdscr_burst_en:1; + /** out_data_burst_en : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data + * when accessing internal SRAM. + */ + uint32_t out_data_burst_en:1; + /** out_etm_en : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Tx channel 0 is triggered by etm + * task. + */ + uint32_t out_etm_en:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_out_conf0_chn_reg_t; + +/** Type of out_conf1_chn register + * Configure 1 register of Tx channel 0 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** out_check_owner : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ + uint32_t out_check_owner:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_out_conf1_chn_reg_t; + +/** Type of out_push_chn register + * Push control register of Rx channel 0 + */ +typedef union { + struct { + /** outfifo_wdata : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into DMA FIFO. + */ + uint32_t outfifo_wdata:9; + /** outfifo_push : WT; bitpos: [9]; default: 0; + * Set this bit to push data into DMA FIFO. + */ + uint32_t outfifo_push:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} gdma_out_push_chn_reg_t; + +/** Type of out_link_chn register + * Link descriptor configure and control register of Tx channel 0 + */ +typedef union { + struct { + /** outlink_addr : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ + uint32_t outlink_addr:20; + /** outlink_stop : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ + uint32_t outlink_stop:1; + /** outlink_start : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ + uint32_t outlink_start:1; + /** outlink_restart : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ + uint32_t outlink_restart:1; + /** outlink_park : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ + uint32_t outlink_park:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} gdma_out_link_chn_reg_t; + +/** Group: Version Registers */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35660368; + * register version. + */ + uint32_t date:32; + }; + uint32_t val; +} gdma_date_reg_t; + + +/** Group: Status Registers */ +/** Type of infifo_status_chn register + * Receive FIFO status of Rx channel 0 + */ +typedef union { + struct { + /** infifo_full : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 0. + */ + uint32_t infifo_full:1; + /** infifo_empty : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 0. + */ + uint32_t infifo_empty:1; + /** infifo_cnt : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + */ + uint32_t infifo_cnt:6; + uint32_t reserved_8:15; + /** in_remain_under_1b : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t in_remain_under_1b:1; + /** in_remain_under_2b : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t in_remain_under_2b:1; + /** in_remain_under_3b : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t in_remain_under_3b:1; + /** in_remain_under_4b : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t in_remain_under_4b:1; + /** in_buf_hungry : RO; bitpos: [27]; default: 0; + * reserved + */ + uint32_t in_buf_hungry:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} gdma_infifo_status_chn_reg_t; + +/** Type of in_state_chn register + * Receive status of Rx channel 0 + */ +typedef union { + struct { + /** inlink_dscr_addr : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ + uint32_t inlink_dscr_addr:18; + /** in_dscr_state : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t in_dscr_state:2; + /** in_state : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t in_state:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} gdma_in_state_chn_reg_t; + +/** Type of in_suc_eof_des_addr_chn register + * Inlink descriptor address when EOF occurs of Rx channel 0 + */ +typedef union { + struct { + /** in_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t in_suc_eof_des_addr:32; + }; + uint32_t val; +} gdma_in_suc_eof_des_addr_chn_reg_t; + +/** Type of in_err_eof_des_addr_chn register + * Inlink descriptor address when errors occur of Rx channel 0 + */ +typedef union { + struct { + /** in_err_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ + uint32_t in_err_eof_des_addr:32; + }; + uint32_t val; +} gdma_in_err_eof_des_addr_chn_reg_t; + +/** Type of in_dscr_chn register + * Current inlink descriptor address of Rx channel 0 + */ +typedef union { + struct { + /** inlink_dscr : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ + uint32_t inlink_dscr:32; + }; + uint32_t val; +} gdma_in_dscr_chn_reg_t; + +/** Type of in_dscr_bf0_chn register + * The last inlink descriptor address of Rx channel 0 + */ +typedef union { + struct { + /** inlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ + uint32_t inlink_dscr_bf0:32; + }; + uint32_t val; +} gdma_in_dscr_bf0_chn_reg_t; + +/** Type of in_dscr_bf1_chn register + * The second-to-last inlink descriptor address of Rx channel 0 + */ +typedef union { + struct { + /** inlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + uint32_t inlink_dscr_bf1:32; + }; + uint32_t val; +} gdma_in_dscr_bf1_chn_reg_t; + +/** Type of outfifo_status_chn register + * Transmit FIFO status of Tx channel 0 + */ +typedef union { + struct { + /** outfifo_full : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 0. + */ + uint32_t outfifo_full:1; + /** outfifo_empty : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 0. + */ + uint32_t outfifo_empty:1; + /** outfifo_cnt : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + */ + uint32_t outfifo_cnt:6; + uint32_t reserved_8:15; + /** out_remain_under_1b : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t out_remain_under_1b:1; + /** out_remain_under_2b : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t out_remain_under_2b:1; + /** out_remain_under_3b : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t out_remain_under_3b:1; + /** out_remain_under_4b : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t out_remain_under_4b:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} gdma_outfifo_status_chn_reg_t; + +/** Type of out_state_chn register + * Transmit status of Tx channel 0 + */ +typedef union { + struct { + /** outlink_dscr_addr : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ + uint32_t outlink_dscr_addr:18; + /** out_dscr_state : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t out_dscr_state:2; + /** out_state : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t out_state:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} gdma_out_state_chn_reg_t; + +/** Type of out_eof_des_addr_chn register + * Outlink descriptor address when EOF occurs of Tx channel 0 + */ +typedef union { + struct { + /** out_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t out_eof_des_addr:32; + }; + uint32_t val; +} gdma_out_eof_des_addr_chn_reg_t; + +/** Type of out_eof_bfr_des_addr_chn register + * The last outlink descriptor address when EOF occurs of Tx channel 0 + */ +typedef union { + struct { + /** out_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ + uint32_t out_eof_bfr_des_addr:32; + }; + uint32_t val; +} gdma_out_eof_bfr_des_addr_chn_reg_t; + +/** Type of out_dscr_chn register + * Current inlink descriptor address of Tx channel 0 + */ +typedef union { + struct { + /** outlink_dscr : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ + uint32_t outlink_dscr:32; + }; + uint32_t val; +} gdma_out_dscr_chn_reg_t; + +/** Type of out_dscr_bf0_chn register + * The last inlink descriptor address of Tx channel 0 + */ +typedef union { + struct { + /** outlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ + uint32_t outlink_dscr_bf0:32; + }; + uint32_t val; +} gdma_out_dscr_bf0_chn_reg_t; + +/** Type of out_dscr_bf1_chn register + * The second-to-last inlink descriptor address of Tx channel 0 + */ +typedef union { + struct { + /** outlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + uint32_t outlink_dscr_bf1:32; + }; + uint32_t val; +} gdma_out_dscr_bf1_chn_reg_t; + + +/** Group: Priority Registers */ +/** Type of in_pri_chn register + * Priority register of Rx channel 0 + */ +typedef union { + struct { + /** rx_pri : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 0. The larger of the value the higher of the priority. + */ + uint32_t rx_pri:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_in_pri_chn_reg_t; + +/** Type of out_pri_chn register + * Priority register of Tx channel 0. + */ +typedef union { + struct { + /** tx_pri : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 0. The larger of the value the higher of the priority. + */ + uint32_t tx_pri:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_out_pri_chn_reg_t; + + +/** Group: Peripheral Select Registers */ +/** Type of in_peri_sel_chn register + * Peripheral selection of Rx channel 0 + */ +typedef union { + struct { + /** peri_in_sel : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. + * 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 9: + * Parallel_IO. + */ + uint32_t peri_in_sel:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_in_peri_sel_chn_reg_t; + +/** Type of out_peri_sel_chn register + * Peripheral selection of Tx channel 0 + */ +typedef union { + struct { + /** peri_out_sel : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. + * 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 9: + * Parallel_IO. + */ + uint32_t peri_out_sel:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_peri_sel_chn_reg_t; + +typedef struct { + volatile gdma_in_int_raw_chn_reg_t raw; + volatile gdma_in_int_st_chn_reg_t st; + volatile gdma_in_int_ena_chn_reg_t ena; + volatile gdma_in_int_clr_chn_reg_t clr; +} gdma_in_int_chn_reg_t; + +typedef struct { + volatile gdma_out_int_raw_chn_reg_t raw; + volatile gdma_out_int_st_chn_reg_t st; + volatile gdma_out_int_ena_chn_reg_t ena; + volatile gdma_out_int_clr_chn_reg_t clr; +} gdma_out_int_chn_reg_t; + +typedef struct { + volatile gdma_in_conf0_chn_reg_t in_conf0; + volatile gdma_in_conf1_chn_reg_t in_conf1; + volatile gdma_infifo_status_chn_reg_t infifo_status; + volatile gdma_in_pop_chn_reg_t in_pop; + volatile gdma_in_link_chn_reg_t in_link; + volatile gdma_in_state_chn_reg_t in_state; + volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr; + volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr; + volatile gdma_in_dscr_chn_reg_t in_dscr; + volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0; + volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1; + volatile gdma_in_pri_chn_reg_t in_pri; + volatile gdma_in_peri_sel_chn_reg_t in_peri_sel; +} gdma_in_chn_reg_t; + +typedef struct { + volatile gdma_out_conf0_chn_reg_t out_conf0; + volatile gdma_out_conf1_chn_reg_t out_conf1; + volatile gdma_outfifo_status_chn_reg_t outfifo_status; + volatile gdma_out_push_chn_reg_t out_push; + volatile gdma_out_link_chn_reg_t out_link; + volatile gdma_out_state_chn_reg_t out_state; + volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr; + volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr; + volatile gdma_out_dscr_chn_reg_t out_dscr; + volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0; + volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1; + volatile gdma_out_pri_chn_reg_t out_pri; + volatile gdma_out_peri_sel_chn_reg_t out_peri_sel; +} gdma_out_chn_reg_t; + +typedef struct { + volatile gdma_in_chn_reg_t in; + uint32_t reserved_in[11]; + volatile gdma_out_chn_reg_t out; + uint32_t reserved_out[11]; +} gdma_chn_reg_t; + + +typedef struct gdma_dev_s { + volatile gdma_in_int_chn_reg_t in_intr[3]; + volatile gdma_out_int_chn_reg_t out_intr[3]; + volatile gdma_ahb_test_reg_t ahb_test; + volatile gdma_misc_conf_reg_t misc_conf; + volatile gdma_date_reg_t date; + uint32_t reserved_06c; + volatile gdma_chn_reg_t channel[3]; +} gdma_dev_t; + +extern gdma_dev_t GDMA; + +#ifndef __cplusplus +_Static_assert(sizeof(gdma_dev_t) == 0x2B0, "Invalid size of gdma_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/gpio_ext_reg.h b/components/soc/esp32c6/include/soc/gpio_ext_reg.h new file mode 100644 index 0000000000..7f6b4d6d01 --- /dev/null +++ b/components/soc/esp32c6/include/soc/gpio_ext_reg.h @@ -0,0 +1,1025 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** GPIO_SIGMADELTA0_REG register + * Duty Cycle Configure Register of SDM0 + */ +#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_EXT_BASE + 0x0) +/** GPIO_SD0_IN : R/W; bitpos: [7:0]; default: 0; + * This field is used to configure the duty cycle of sigma delta modulation output. + */ +#define GPIO_SD0_IN 0x000000FFU +#define GPIO_SD0_IN_M (GPIO_SD0_IN_V << GPIO_SD0_IN_S) +#define GPIO_SD0_IN_V 0x000000FFU +#define GPIO_SD0_IN_S 0 +/** GPIO_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; + * This field is used to set a divider value to divide APB clock. + */ +#define GPIO_SD0_PRESCALE 0x000000FFU +#define GPIO_SD0_PRESCALE_M (GPIO_SD0_PRESCALE_V << GPIO_SD0_PRESCALE_S) +#define GPIO_SD0_PRESCALE_V 0x000000FFU +#define GPIO_SD0_PRESCALE_S 8 + +/** GPIO_SIGMADELTA1_REG register + * Duty Cycle Configure Register of SDM1 + */ +#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_EXT_BASE + 0x4) +/** GPIO_SD0_IN : R/W; bitpos: [7:0]; default: 0; + * This field is used to configure the duty cycle of sigma delta modulation output. + */ +#define GPIO_SD0_IN 0x000000FFU +#define GPIO_SD0_IN_M (GPIO_SD0_IN_V << GPIO_SD0_IN_S) +#define GPIO_SD0_IN_V 0x000000FFU +#define GPIO_SD0_IN_S 0 +/** GPIO_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; + * This field is used to set a divider value to divide APB clock. + */ +#define GPIO_SD0_PRESCALE 0x000000FFU +#define GPIO_SD0_PRESCALE_M (GPIO_SD0_PRESCALE_V << GPIO_SD0_PRESCALE_S) +#define GPIO_SD0_PRESCALE_V 0x000000FFU +#define GPIO_SD0_PRESCALE_S 8 + +/** GPIO_SIGMADELTA2_REG register + * Duty Cycle Configure Register of SDM2 + */ +#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_EXT_BASE + 0x8) +/** GPIO_SD0_IN : R/W; bitpos: [7:0]; default: 0; + * This field is used to configure the duty cycle of sigma delta modulation output. + */ +#define GPIO_SD0_IN 0x000000FFU +#define GPIO_SD0_IN_M (GPIO_SD0_IN_V << GPIO_SD0_IN_S) +#define GPIO_SD0_IN_V 0x000000FFU +#define GPIO_SD0_IN_S 0 +/** GPIO_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; + * This field is used to set a divider value to divide APB clock. + */ +#define GPIO_SD0_PRESCALE 0x000000FFU +#define GPIO_SD0_PRESCALE_M (GPIO_SD0_PRESCALE_V << GPIO_SD0_PRESCALE_S) +#define GPIO_SD0_PRESCALE_V 0x000000FFU +#define GPIO_SD0_PRESCALE_S 8 + +/** GPIO_SIGMADELTA3_REG register + * Duty Cycle Configure Register of SDM3 + */ +#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_EXT_BASE + 0xc) +/** GPIO_SD0_IN : R/W; bitpos: [7:0]; default: 0; + * This field is used to configure the duty cycle of sigma delta modulation output. + */ +#define GPIO_SD0_IN 0x000000FFU +#define GPIO_SD0_IN_M (GPIO_SD0_IN_V << GPIO_SD0_IN_S) +#define GPIO_SD0_IN_V 0x000000FFU +#define GPIO_SD0_IN_S 0 +/** GPIO_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; + * This field is used to set a divider value to divide APB clock. + */ +#define GPIO_SD0_PRESCALE 0x000000FFU +#define GPIO_SD0_PRESCALE_M (GPIO_SD0_PRESCALE_V << GPIO_SD0_PRESCALE_S) +#define GPIO_SD0_PRESCALE_V 0x000000FFU +#define GPIO_SD0_PRESCALE_S 8 + +/** GPIO_CLOCK_GATE_REG register + * Clock Gating Configure Register + */ +#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_EXT_BASE + 0x20) +/** GPIO_CLK_EN : R/W; bitpos: [0]; default: 0; + * Clock enable bit of configuration registers for sigma delta modulation. + */ +#define GPIO_CLK_EN (BIT(0)) +#define GPIO_CLK_EN_M (GPIO_CLK_EN_V << GPIO_CLK_EN_S) +#define GPIO_CLK_EN_V 0x00000001U +#define GPIO_CLK_EN_S 0 + +/** GPIO_SIGMADELTA_MISC_REG register + * MISC Register + */ +#define GPIO_SIGMADELTA_MISC_REG (DR_REG_GPIO_EXT_BASE + 0x24) +/** GPIO_FUNCTION_CLK_EN : R/W; bitpos: [30]; default: 0; + * Clock enable bit of sigma delta modulation. + */ +#define GPIO_FUNCTION_CLK_EN (BIT(30)) +#define GPIO_FUNCTION_CLK_EN_M (GPIO_FUNCTION_CLK_EN_V << GPIO_FUNCTION_CLK_EN_S) +#define GPIO_FUNCTION_CLK_EN_V 0x00000001U +#define GPIO_FUNCTION_CLK_EN_S 30 +/** GPIO_SPI_SWAP : R/W; bitpos: [31]; default: 0; + * Reserved. + */ +#define GPIO_SPI_SWAP (BIT(31)) +#define GPIO_SPI_SWAP_M (GPIO_SPI_SWAP_V << GPIO_SPI_SWAP_S) +#define GPIO_SPI_SWAP_V 0x00000001U +#define GPIO_SPI_SWAP_S 31 + +/** GPIO_GLITCH_FILTER_CH0_REG register + * Glitch Filter Configure Register of Channel0 + */ +#define GPIO_GLITCH_FILTER_CH0_REG (DR_REG_GPIO_EXT_BASE + 0x30) +/** GPIO_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_FILTER_CH0_EN (BIT(0)) +#define GPIO_FILTER_CH0_EN_M (GPIO_FILTER_CH0_EN_V << GPIO_FILTER_CH0_EN_S) +#define GPIO_FILTER_CH0_EN_V 0x00000001U +#define GPIO_FILTER_CH0_EN_S 0 +/** GPIO_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_FILTER_CH0_INPUT_IO_NUM 0x0000003FU +#define GPIO_FILTER_CH0_INPUT_IO_NUM_M (GPIO_FILTER_CH0_INPUT_IO_NUM_V << GPIO_FILTER_CH0_INPUT_IO_NUM_S) +#define GPIO_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_FILTER_CH0_INPUT_IO_NUM_S 1 +/** GPIO_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_FILTER_CH0_WINDOW_THRES 0x0000003FU +#define GPIO_FILTER_CH0_WINDOW_THRES_M (GPIO_FILTER_CH0_WINDOW_THRES_V << GPIO_FILTER_CH0_WINDOW_THRES_S) +#define GPIO_FILTER_CH0_WINDOW_THRES_V 0x0000003FU +#define GPIO_FILTER_CH0_WINDOW_THRES_S 7 +/** GPIO_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_FILTER_CH0_WINDOW_WIDTH 0x0000003FU +#define GPIO_FILTER_CH0_WINDOW_WIDTH_M (GPIO_FILTER_CH0_WINDOW_WIDTH_V << GPIO_FILTER_CH0_WINDOW_WIDTH_S) +#define GPIO_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_FILTER_CH0_WINDOW_WIDTH_S 13 + +/** GPIO_GLITCH_FILTER_CH1_REG register + * Glitch Filter Configure Register of Channel1 + */ +#define GPIO_GLITCH_FILTER_CH1_REG (DR_REG_GPIO_EXT_BASE + 0x34) +/** GPIO_FILTER_CH1_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_FILTER_CH1_EN (BIT(0)) +#define GPIO_FILTER_CH1_EN_M (GPIO_FILTER_CH1_EN_V << GPIO_FILTER_CH1_EN_S) +#define GPIO_FILTER_CH1_EN_V 0x00000001U +#define GPIO_FILTER_CH1_EN_S 0 +/** GPIO_FILTER_CH1_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_FILTER_CH1_INPUT_IO_NUM 0x0000003FU +#define GPIO_FILTER_CH1_INPUT_IO_NUM_M (GPIO_FILTER_CH1_INPUT_IO_NUM_V << GPIO_FILTER_CH1_INPUT_IO_NUM_S) +#define GPIO_FILTER_CH1_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_FILTER_CH1_INPUT_IO_NUM_S 1 +/** GPIO_FILTER_CH1_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_FILTER_CH1_WINDOW_THRES 0x0000003FU +#define GPIO_FILTER_CH1_WINDOW_THRES_M (GPIO_FILTER_CH1_WINDOW_THRES_V << GPIO_FILTER_CH1_WINDOW_THRES_S) +#define GPIO_FILTER_CH1_WINDOW_THRES_V 0x0000003FU +#define GPIO_FILTER_CH1_WINDOW_THRES_S 7 +/** GPIO_FILTER_CH1_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_FILTER_CH1_WINDOW_WIDTH 0x0000003FU +#define GPIO_FILTER_CH1_WINDOW_WIDTH_M (GPIO_FILTER_CH1_WINDOW_WIDTH_V << GPIO_FILTER_CH1_WINDOW_WIDTH_S) +#define GPIO_FILTER_CH1_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_FILTER_CH1_WINDOW_WIDTH_S 13 + +/** GPIO_GLITCH_FILTER_CH2_REG register + * Glitch Filter Configure Register of Channel2 + */ +#define GPIO_GLITCH_FILTER_CH2_REG (DR_REG_GPIO_EXT_BASE + 0x38) +/** GPIO_FILTER_CH2_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_FILTER_CH2_EN (BIT(0)) +#define GPIO_FILTER_CH2_EN_M (GPIO_FILTER_CH2_EN_V << GPIO_FILTER_CH2_EN_S) +#define GPIO_FILTER_CH2_EN_V 0x00000001U +#define GPIO_FILTER_CH2_EN_S 0 +/** GPIO_FILTER_CH2_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_FILTER_CH2_INPUT_IO_NUM 0x0000003FU +#define GPIO_FILTER_CH2_INPUT_IO_NUM_M (GPIO_FILTER_CH2_INPUT_IO_NUM_V << GPIO_FILTER_CH2_INPUT_IO_NUM_S) +#define GPIO_FILTER_CH2_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_FILTER_CH2_INPUT_IO_NUM_S 1 +/** GPIO_FILTER_CH2_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_FILTER_CH2_WINDOW_THRES 0x0000003FU +#define GPIO_FILTER_CH2_WINDOW_THRES_M (GPIO_FILTER_CH2_WINDOW_THRES_V << GPIO_FILTER_CH2_WINDOW_THRES_S) +#define GPIO_FILTER_CH2_WINDOW_THRES_V 0x0000003FU +#define GPIO_FILTER_CH2_WINDOW_THRES_S 7 +/** GPIO_FILTER_CH2_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_FILTER_CH2_WINDOW_WIDTH 0x0000003FU +#define GPIO_FILTER_CH2_WINDOW_WIDTH_M (GPIO_FILTER_CH2_WINDOW_WIDTH_V << GPIO_FILTER_CH2_WINDOW_WIDTH_S) +#define GPIO_FILTER_CH2_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_FILTER_CH2_WINDOW_WIDTH_S 13 + +/** GPIO_GLITCH_FILTER_CH3_REG register + * Glitch Filter Configure Register of Channel3 + */ +#define GPIO_GLITCH_FILTER_CH3_REG (DR_REG_GPIO_EXT_BASE + 0x3c) +/** GPIO_FILTER_CH3_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_FILTER_CH3_EN (BIT(0)) +#define GPIO_FILTER_CH3_EN_M (GPIO_FILTER_CH3_EN_V << GPIO_FILTER_CH3_EN_S) +#define GPIO_FILTER_CH3_EN_V 0x00000001U +#define GPIO_FILTER_CH3_EN_S 0 +/** GPIO_FILTER_CH3_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_FILTER_CH3_INPUT_IO_NUM 0x0000003FU +#define GPIO_FILTER_CH3_INPUT_IO_NUM_M (GPIO_FILTER_CH3_INPUT_IO_NUM_V << GPIO_FILTER_CH3_INPUT_IO_NUM_S) +#define GPIO_FILTER_CH3_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_FILTER_CH3_INPUT_IO_NUM_S 1 +/** GPIO_FILTER_CH3_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_FILTER_CH3_WINDOW_THRES 0x0000003FU +#define GPIO_FILTER_CH3_WINDOW_THRES_M (GPIO_FILTER_CH3_WINDOW_THRES_V << GPIO_FILTER_CH3_WINDOW_THRES_S) +#define GPIO_FILTER_CH3_WINDOW_THRES_V 0x0000003FU +#define GPIO_FILTER_CH3_WINDOW_THRES_S 7 +/** GPIO_FILTER_CH3_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_FILTER_CH3_WINDOW_WIDTH 0x0000003FU +#define GPIO_FILTER_CH3_WINDOW_WIDTH_M (GPIO_FILTER_CH3_WINDOW_WIDTH_V << GPIO_FILTER_CH3_WINDOW_WIDTH_S) +#define GPIO_FILTER_CH3_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_FILTER_CH3_WINDOW_WIDTH_S 13 + +/** GPIO_GLITCH_FILTER_CH4_REG register + * Glitch Filter Configure Register of Channel4 + */ +#define GPIO_GLITCH_FILTER_CH4_REG (DR_REG_GPIO_EXT_BASE + 0x40) +/** GPIO_FILTER_CH4_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_FILTER_CH4_EN (BIT(0)) +#define GPIO_FILTER_CH4_EN_M (GPIO_FILTER_CH4_EN_V << GPIO_FILTER_CH4_EN_S) +#define GPIO_FILTER_CH4_EN_V 0x00000001U +#define GPIO_FILTER_CH4_EN_S 0 +/** GPIO_FILTER_CH4_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_FILTER_CH4_INPUT_IO_NUM 0x0000003FU +#define GPIO_FILTER_CH4_INPUT_IO_NUM_M (GPIO_FILTER_CH4_INPUT_IO_NUM_V << GPIO_FILTER_CH4_INPUT_IO_NUM_S) +#define GPIO_FILTER_CH4_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_FILTER_CH4_INPUT_IO_NUM_S 1 +/** GPIO_FILTER_CH4_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_FILTER_CH4_WINDOW_THRES 0x0000003FU +#define GPIO_FILTER_CH4_WINDOW_THRES_M (GPIO_FILTER_CH4_WINDOW_THRES_V << GPIO_FILTER_CH4_WINDOW_THRES_S) +#define GPIO_FILTER_CH4_WINDOW_THRES_V 0x0000003FU +#define GPIO_FILTER_CH4_WINDOW_THRES_S 7 +/** GPIO_FILTER_CH4_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_FILTER_CH4_WINDOW_WIDTH 0x0000003FU +#define GPIO_FILTER_CH4_WINDOW_WIDTH_M (GPIO_FILTER_CH4_WINDOW_WIDTH_V << GPIO_FILTER_CH4_WINDOW_WIDTH_S) +#define GPIO_FILTER_CH4_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_FILTER_CH4_WINDOW_WIDTH_S 13 + +/** GPIO_GLITCH_FILTER_CH5_REG register + * Glitch Filter Configure Register of Channel5 + */ +#define GPIO_GLITCH_FILTER_CH5_REG (DR_REG_GPIO_EXT_BASE + 0x44) +/** GPIO_FILTER_CH5_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_FILTER_CH5_EN (BIT(0)) +#define GPIO_FILTER_CH5_EN_M (GPIO_FILTER_CH5_EN_V << GPIO_FILTER_CH5_EN_S) +#define GPIO_FILTER_CH5_EN_V 0x00000001U +#define GPIO_FILTER_CH5_EN_S 0 +/** GPIO_FILTER_CH5_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_FILTER_CH5_INPUT_IO_NUM 0x0000003FU +#define GPIO_FILTER_CH5_INPUT_IO_NUM_M (GPIO_FILTER_CH5_INPUT_IO_NUM_V << GPIO_FILTER_CH5_INPUT_IO_NUM_S) +#define GPIO_FILTER_CH5_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_FILTER_CH5_INPUT_IO_NUM_S 1 +/** GPIO_FILTER_CH5_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_FILTER_CH5_WINDOW_THRES 0x0000003FU +#define GPIO_FILTER_CH5_WINDOW_THRES_M (GPIO_FILTER_CH5_WINDOW_THRES_V << GPIO_FILTER_CH5_WINDOW_THRES_S) +#define GPIO_FILTER_CH5_WINDOW_THRES_V 0x0000003FU +#define GPIO_FILTER_CH5_WINDOW_THRES_S 7 +/** GPIO_FILTER_CH5_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_FILTER_CH5_WINDOW_WIDTH 0x0000003FU +#define GPIO_FILTER_CH5_WINDOW_WIDTH_M (GPIO_FILTER_CH5_WINDOW_WIDTH_V << GPIO_FILTER_CH5_WINDOW_WIDTH_S) +#define GPIO_FILTER_CH5_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_FILTER_CH5_WINDOW_WIDTH_S 13 + +/** GPIO_GLITCH_FILTER_CH6_REG register + * Glitch Filter Configure Register of Channel6 + */ +#define GPIO_GLITCH_FILTER_CH6_REG (DR_REG_GPIO_EXT_BASE + 0x48) +/** GPIO_FILTER_CH6_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_FILTER_CH6_EN (BIT(0)) +#define GPIO_FILTER_CH6_EN_M (GPIO_FILTER_CH6_EN_V << GPIO_FILTER_CH6_EN_S) +#define GPIO_FILTER_CH6_EN_V 0x00000001U +#define GPIO_FILTER_CH6_EN_S 0 +/** GPIO_FILTER_CH6_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_FILTER_CH6_INPUT_IO_NUM 0x0000003FU +#define GPIO_FILTER_CH6_INPUT_IO_NUM_M (GPIO_FILTER_CH6_INPUT_IO_NUM_V << GPIO_FILTER_CH6_INPUT_IO_NUM_S) +#define GPIO_FILTER_CH6_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_FILTER_CH6_INPUT_IO_NUM_S 1 +/** GPIO_FILTER_CH6_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_FILTER_CH6_WINDOW_THRES 0x0000003FU +#define GPIO_FILTER_CH6_WINDOW_THRES_M (GPIO_FILTER_CH6_WINDOW_THRES_V << GPIO_FILTER_CH6_WINDOW_THRES_S) +#define GPIO_FILTER_CH6_WINDOW_THRES_V 0x0000003FU +#define GPIO_FILTER_CH6_WINDOW_THRES_S 7 +/** GPIO_FILTER_CH6_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_FILTER_CH6_WINDOW_WIDTH 0x0000003FU +#define GPIO_FILTER_CH6_WINDOW_WIDTH_M (GPIO_FILTER_CH6_WINDOW_WIDTH_V << GPIO_FILTER_CH6_WINDOW_WIDTH_S) +#define GPIO_FILTER_CH6_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_FILTER_CH6_WINDOW_WIDTH_S 13 + +/** GPIO_GLITCH_FILTER_CH7_REG register + * Glitch Filter Configure Register of Channel7 + */ +#define GPIO_GLITCH_FILTER_CH7_REG (DR_REG_GPIO_EXT_BASE + 0x4c) +/** GPIO_FILTER_CH7_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_FILTER_CH7_EN (BIT(0)) +#define GPIO_FILTER_CH7_EN_M (GPIO_FILTER_CH7_EN_V << GPIO_FILTER_CH7_EN_S) +#define GPIO_FILTER_CH7_EN_V 0x00000001U +#define GPIO_FILTER_CH7_EN_S 0 +/** GPIO_FILTER_CH7_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_FILTER_CH7_INPUT_IO_NUM 0x0000003FU +#define GPIO_FILTER_CH7_INPUT_IO_NUM_M (GPIO_FILTER_CH7_INPUT_IO_NUM_V << GPIO_FILTER_CH7_INPUT_IO_NUM_S) +#define GPIO_FILTER_CH7_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_FILTER_CH7_INPUT_IO_NUM_S 1 +/** GPIO_FILTER_CH7_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_FILTER_CH7_WINDOW_THRES 0x0000003FU +#define GPIO_FILTER_CH7_WINDOW_THRES_M (GPIO_FILTER_CH7_WINDOW_THRES_V << GPIO_FILTER_CH7_WINDOW_THRES_S) +#define GPIO_FILTER_CH7_WINDOW_THRES_V 0x0000003FU +#define GPIO_FILTER_CH7_WINDOW_THRES_S 7 +/** GPIO_FILTER_CH7_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_FILTER_CH7_WINDOW_WIDTH 0x0000003FU +#define GPIO_FILTER_CH7_WINDOW_WIDTH_M (GPIO_FILTER_CH7_WINDOW_WIDTH_V << GPIO_FILTER_CH7_WINDOW_WIDTH_S) +#define GPIO_FILTER_CH7_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_FILTER_CH7_WINDOW_WIDTH_S 13 + +/** GPIO_ETM_EVENT_CH0_CFG_REG register + * Etm Config register of Channel0 + */ +#define GPIO_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x60) +/** GPIO_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_ETM_CH0_EVENT_SEL 0x0000001FU +#define GPIO_ETM_CH0_EVENT_SEL_M (GPIO_ETM_CH0_EVENT_SEL_V << GPIO_ETM_CH0_EVENT_SEL_S) +#define GPIO_ETM_CH0_EVENT_SEL_V 0x0000001FU +#define GPIO_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_ETM_CH0_EVENT_EN_M (GPIO_ETM_CH0_EVENT_EN_V << GPIO_ETM_CH0_EVENT_EN_S) +#define GPIO_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_ETM_CH0_EVENT_EN_S 7 + +/** GPIO_ETM_EVENT_CH1_CFG_REG register + * Etm Config register of Channel1 + */ +#define GPIO_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x64) +/** GPIO_ETM_CH1_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_ETM_CH1_EVENT_SEL 0x0000001FU +#define GPIO_ETM_CH1_EVENT_SEL_M (GPIO_ETM_CH1_EVENT_SEL_V << GPIO_ETM_CH1_EVENT_SEL_S) +#define GPIO_ETM_CH1_EVENT_SEL_V 0x0000001FU +#define GPIO_ETM_CH1_EVENT_SEL_S 0 +/** GPIO_ETM_CH1_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_ETM_CH1_EVENT_EN (BIT(7)) +#define GPIO_ETM_CH1_EVENT_EN_M (GPIO_ETM_CH1_EVENT_EN_V << GPIO_ETM_CH1_EVENT_EN_S) +#define GPIO_ETM_CH1_EVENT_EN_V 0x00000001U +#define GPIO_ETM_CH1_EVENT_EN_S 7 + +/** GPIO_ETM_EVENT_CH2_CFG_REG register + * Etm Config register of Channel2 + */ +#define GPIO_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x68) +/** GPIO_ETM_CH2_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_ETM_CH2_EVENT_SEL 0x0000001FU +#define GPIO_ETM_CH2_EVENT_SEL_M (GPIO_ETM_CH2_EVENT_SEL_V << GPIO_ETM_CH2_EVENT_SEL_S) +#define GPIO_ETM_CH2_EVENT_SEL_V 0x0000001FU +#define GPIO_ETM_CH2_EVENT_SEL_S 0 +/** GPIO_ETM_CH2_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_ETM_CH2_EVENT_EN (BIT(7)) +#define GPIO_ETM_CH2_EVENT_EN_M (GPIO_ETM_CH2_EVENT_EN_V << GPIO_ETM_CH2_EVENT_EN_S) +#define GPIO_ETM_CH2_EVENT_EN_V 0x00000001U +#define GPIO_ETM_CH2_EVENT_EN_S 7 + +/** GPIO_ETM_EVENT_CH3_CFG_REG register + * Etm Config register of Channel3 + */ +#define GPIO_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x6c) +/** GPIO_ETM_CH3_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_ETM_CH3_EVENT_SEL 0x0000001FU +#define GPIO_ETM_CH3_EVENT_SEL_M (GPIO_ETM_CH3_EVENT_SEL_V << GPIO_ETM_CH3_EVENT_SEL_S) +#define GPIO_ETM_CH3_EVENT_SEL_V 0x0000001FU +#define GPIO_ETM_CH3_EVENT_SEL_S 0 +/** GPIO_ETM_CH3_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_ETM_CH3_EVENT_EN (BIT(7)) +#define GPIO_ETM_CH3_EVENT_EN_M (GPIO_ETM_CH3_EVENT_EN_V << GPIO_ETM_CH3_EVENT_EN_S) +#define GPIO_ETM_CH3_EVENT_EN_V 0x00000001U +#define GPIO_ETM_CH3_EVENT_EN_S 7 + +/** GPIO_ETM_EVENT_CH4_CFG_REG register + * Etm Config register of Channel4 + */ +#define GPIO_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x70) +/** GPIO_ETM_CH4_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_ETM_CH4_EVENT_SEL 0x0000001FU +#define GPIO_ETM_CH4_EVENT_SEL_M (GPIO_ETM_CH4_EVENT_SEL_V << GPIO_ETM_CH4_EVENT_SEL_S) +#define GPIO_ETM_CH4_EVENT_SEL_V 0x0000001FU +#define GPIO_ETM_CH4_EVENT_SEL_S 0 +/** GPIO_ETM_CH4_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_ETM_CH4_EVENT_EN (BIT(7)) +#define GPIO_ETM_CH4_EVENT_EN_M (GPIO_ETM_CH4_EVENT_EN_V << GPIO_ETM_CH4_EVENT_EN_S) +#define GPIO_ETM_CH4_EVENT_EN_V 0x00000001U +#define GPIO_ETM_CH4_EVENT_EN_S 7 + +/** GPIO_ETM_EVENT_CH5_CFG_REG register + * Etm Config register of Channel5 + */ +#define GPIO_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x74) +/** GPIO_ETM_CH5_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_ETM_CH5_EVENT_SEL 0x0000001FU +#define GPIO_ETM_CH5_EVENT_SEL_M (GPIO_ETM_CH5_EVENT_SEL_V << GPIO_ETM_CH5_EVENT_SEL_S) +#define GPIO_ETM_CH5_EVENT_SEL_V 0x0000001FU +#define GPIO_ETM_CH5_EVENT_SEL_S 0 +/** GPIO_ETM_CH5_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_ETM_CH5_EVENT_EN (BIT(7)) +#define GPIO_ETM_CH5_EVENT_EN_M (GPIO_ETM_CH5_EVENT_EN_V << GPIO_ETM_CH5_EVENT_EN_S) +#define GPIO_ETM_CH5_EVENT_EN_V 0x00000001U +#define GPIO_ETM_CH5_EVENT_EN_S 7 + +/** GPIO_ETM_EVENT_CH6_CFG_REG register + * Etm Config register of Channel6 + */ +#define GPIO_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x78) +/** GPIO_ETM_CH6_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_ETM_CH6_EVENT_SEL 0x0000001FU +#define GPIO_ETM_CH6_EVENT_SEL_M (GPIO_ETM_CH6_EVENT_SEL_V << GPIO_ETM_CH6_EVENT_SEL_S) +#define GPIO_ETM_CH6_EVENT_SEL_V 0x0000001FU +#define GPIO_ETM_CH6_EVENT_SEL_S 0 +/** GPIO_ETM_CH6_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_ETM_CH6_EVENT_EN (BIT(7)) +#define GPIO_ETM_CH6_EVENT_EN_M (GPIO_ETM_CH6_EVENT_EN_V << GPIO_ETM_CH6_EVENT_EN_S) +#define GPIO_ETM_CH6_EVENT_EN_V 0x00000001U +#define GPIO_ETM_CH6_EVENT_EN_S 7 + +/** GPIO_ETM_EVENT_CH7_CFG_REG register + * Etm Config register of Channel7 + */ +#define GPIO_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x7c) +/** GPIO_ETM_CH7_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_ETM_CH7_EVENT_SEL 0x0000001FU +#define GPIO_ETM_CH7_EVENT_SEL_M (GPIO_ETM_CH7_EVENT_SEL_V << GPIO_ETM_CH7_EVENT_SEL_S) +#define GPIO_ETM_CH7_EVENT_SEL_V 0x0000001FU +#define GPIO_ETM_CH7_EVENT_SEL_S 0 +/** GPIO_ETM_CH7_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_ETM_CH7_EVENT_EN (BIT(7)) +#define GPIO_ETM_CH7_EVENT_EN_M (GPIO_ETM_CH7_EVENT_EN_V << GPIO_ETM_CH7_EVENT_EN_S) +#define GPIO_ETM_CH7_EVENT_EN_V 0x00000001U +#define GPIO_ETM_CH7_EVENT_EN_S 7 + +/** GPIO_ETM_TASK_P0_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa0) +/** GPIO_ETM_TASK_GPIO0_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO0_EN (BIT(0)) +#define GPIO_ETM_TASK_GPIO0_EN_M (GPIO_ETM_TASK_GPIO0_EN_V << GPIO_ETM_TASK_GPIO0_EN_S) +#define GPIO_ETM_TASK_GPIO0_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO0_EN_S 0 +/** GPIO_ETM_TASK_GPIO0_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO0_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO0_SEL_M (GPIO_ETM_TASK_GPIO0_SEL_V << GPIO_ETM_TASK_GPIO0_SEL_S) +#define GPIO_ETM_TASK_GPIO0_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO0_SEL_S 1 +/** GPIO_ETM_TASK_GPIO1_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO1_EN (BIT(8)) +#define GPIO_ETM_TASK_GPIO1_EN_M (GPIO_ETM_TASK_GPIO1_EN_V << GPIO_ETM_TASK_GPIO1_EN_S) +#define GPIO_ETM_TASK_GPIO1_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO1_EN_S 8 +/** GPIO_ETM_TASK_GPIO1_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO1_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO1_SEL_M (GPIO_ETM_TASK_GPIO1_SEL_V << GPIO_ETM_TASK_GPIO1_SEL_S) +#define GPIO_ETM_TASK_GPIO1_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO1_SEL_S 9 +/** GPIO_ETM_TASK_GPIO2_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO2_EN (BIT(16)) +#define GPIO_ETM_TASK_GPIO2_EN_M (GPIO_ETM_TASK_GPIO2_EN_V << GPIO_ETM_TASK_GPIO2_EN_S) +#define GPIO_ETM_TASK_GPIO2_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO2_EN_S 16 +/** GPIO_ETM_TASK_GPIO2_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO2_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO2_SEL_M (GPIO_ETM_TASK_GPIO2_SEL_V << GPIO_ETM_TASK_GPIO2_SEL_S) +#define GPIO_ETM_TASK_GPIO2_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO2_SEL_S 17 +/** GPIO_ETM_TASK_GPIO3_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO3_EN (BIT(24)) +#define GPIO_ETM_TASK_GPIO3_EN_M (GPIO_ETM_TASK_GPIO3_EN_V << GPIO_ETM_TASK_GPIO3_EN_S) +#define GPIO_ETM_TASK_GPIO3_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO3_EN_S 24 +/** GPIO_ETM_TASK_GPIO3_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO3_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO3_SEL_M (GPIO_ETM_TASK_GPIO3_SEL_V << GPIO_ETM_TASK_GPIO3_SEL_S) +#define GPIO_ETM_TASK_GPIO3_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO3_SEL_S 25 + +/** GPIO_ETM_TASK_P1_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa4) +/** GPIO_ETM_TASK_GPIO4_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO4_EN (BIT(0)) +#define GPIO_ETM_TASK_GPIO4_EN_M (GPIO_ETM_TASK_GPIO4_EN_V << GPIO_ETM_TASK_GPIO4_EN_S) +#define GPIO_ETM_TASK_GPIO4_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO4_EN_S 0 +/** GPIO_ETM_TASK_GPIO4_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO4_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO4_SEL_M (GPIO_ETM_TASK_GPIO4_SEL_V << GPIO_ETM_TASK_GPIO4_SEL_S) +#define GPIO_ETM_TASK_GPIO4_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO4_SEL_S 1 +/** GPIO_ETM_TASK_GPIO5_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO5_EN (BIT(8)) +#define GPIO_ETM_TASK_GPIO5_EN_M (GPIO_ETM_TASK_GPIO5_EN_V << GPIO_ETM_TASK_GPIO5_EN_S) +#define GPIO_ETM_TASK_GPIO5_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO5_EN_S 8 +/** GPIO_ETM_TASK_GPIO5_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO5_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO5_SEL_M (GPIO_ETM_TASK_GPIO5_SEL_V << GPIO_ETM_TASK_GPIO5_SEL_S) +#define GPIO_ETM_TASK_GPIO5_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO5_SEL_S 9 +/** GPIO_ETM_TASK_GPIO6_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO6_EN (BIT(16)) +#define GPIO_ETM_TASK_GPIO6_EN_M (GPIO_ETM_TASK_GPIO6_EN_V << GPIO_ETM_TASK_GPIO6_EN_S) +#define GPIO_ETM_TASK_GPIO6_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO6_EN_S 16 +/** GPIO_ETM_TASK_GPIO6_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO6_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO6_SEL_M (GPIO_ETM_TASK_GPIO6_SEL_V << GPIO_ETM_TASK_GPIO6_SEL_S) +#define GPIO_ETM_TASK_GPIO6_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO6_SEL_S 17 +/** GPIO_ETM_TASK_GPIO7_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO7_EN (BIT(24)) +#define GPIO_ETM_TASK_GPIO7_EN_M (GPIO_ETM_TASK_GPIO7_EN_V << GPIO_ETM_TASK_GPIO7_EN_S) +#define GPIO_ETM_TASK_GPIO7_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO7_EN_S 24 +/** GPIO_ETM_TASK_GPIO7_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO7_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO7_SEL_M (GPIO_ETM_TASK_GPIO7_SEL_V << GPIO_ETM_TASK_GPIO7_SEL_S) +#define GPIO_ETM_TASK_GPIO7_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO7_SEL_S 25 + +/** GPIO_ETM_TASK_P2_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa8) +/** GPIO_ETM_TASK_GPIO8_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO8_EN (BIT(0)) +#define GPIO_ETM_TASK_GPIO8_EN_M (GPIO_ETM_TASK_GPIO8_EN_V << GPIO_ETM_TASK_GPIO8_EN_S) +#define GPIO_ETM_TASK_GPIO8_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO8_EN_S 0 +/** GPIO_ETM_TASK_GPIO8_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO8_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO8_SEL_M (GPIO_ETM_TASK_GPIO8_SEL_V << GPIO_ETM_TASK_GPIO8_SEL_S) +#define GPIO_ETM_TASK_GPIO8_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO8_SEL_S 1 +/** GPIO_ETM_TASK_GPIO9_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO9_EN (BIT(8)) +#define GPIO_ETM_TASK_GPIO9_EN_M (GPIO_ETM_TASK_GPIO9_EN_V << GPIO_ETM_TASK_GPIO9_EN_S) +#define GPIO_ETM_TASK_GPIO9_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO9_EN_S 8 +/** GPIO_ETM_TASK_GPIO9_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO9_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO9_SEL_M (GPIO_ETM_TASK_GPIO9_SEL_V << GPIO_ETM_TASK_GPIO9_SEL_S) +#define GPIO_ETM_TASK_GPIO9_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO9_SEL_S 9 +/** GPIO_ETM_TASK_GPIO10_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO10_EN (BIT(16)) +#define GPIO_ETM_TASK_GPIO10_EN_M (GPIO_ETM_TASK_GPIO10_EN_V << GPIO_ETM_TASK_GPIO10_EN_S) +#define GPIO_ETM_TASK_GPIO10_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO10_EN_S 16 +/** GPIO_ETM_TASK_GPIO10_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO10_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO10_SEL_M (GPIO_ETM_TASK_GPIO10_SEL_V << GPIO_ETM_TASK_GPIO10_SEL_S) +#define GPIO_ETM_TASK_GPIO10_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO10_SEL_S 17 +/** GPIO_ETM_TASK_GPIO11_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO11_EN (BIT(24)) +#define GPIO_ETM_TASK_GPIO11_EN_M (GPIO_ETM_TASK_GPIO11_EN_V << GPIO_ETM_TASK_GPIO11_EN_S) +#define GPIO_ETM_TASK_GPIO11_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO11_EN_S 24 +/** GPIO_ETM_TASK_GPIO11_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO11_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO11_SEL_M (GPIO_ETM_TASK_GPIO11_SEL_V << GPIO_ETM_TASK_GPIO11_SEL_S) +#define GPIO_ETM_TASK_GPIO11_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO11_SEL_S 25 + +/** GPIO_ETM_TASK_P3_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xac) +/** GPIO_ETM_TASK_GPIO12_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO12_EN (BIT(0)) +#define GPIO_ETM_TASK_GPIO12_EN_M (GPIO_ETM_TASK_GPIO12_EN_V << GPIO_ETM_TASK_GPIO12_EN_S) +#define GPIO_ETM_TASK_GPIO12_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO12_EN_S 0 +/** GPIO_ETM_TASK_GPIO12_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO12_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO12_SEL_M (GPIO_ETM_TASK_GPIO12_SEL_V << GPIO_ETM_TASK_GPIO12_SEL_S) +#define GPIO_ETM_TASK_GPIO12_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO12_SEL_S 1 +/** GPIO_ETM_TASK_GPIO13_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO13_EN (BIT(8)) +#define GPIO_ETM_TASK_GPIO13_EN_M (GPIO_ETM_TASK_GPIO13_EN_V << GPIO_ETM_TASK_GPIO13_EN_S) +#define GPIO_ETM_TASK_GPIO13_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO13_EN_S 8 +/** GPIO_ETM_TASK_GPIO13_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO13_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO13_SEL_M (GPIO_ETM_TASK_GPIO13_SEL_V << GPIO_ETM_TASK_GPIO13_SEL_S) +#define GPIO_ETM_TASK_GPIO13_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO13_SEL_S 9 +/** GPIO_ETM_TASK_GPIO14_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO14_EN (BIT(16)) +#define GPIO_ETM_TASK_GPIO14_EN_M (GPIO_ETM_TASK_GPIO14_EN_V << GPIO_ETM_TASK_GPIO14_EN_S) +#define GPIO_ETM_TASK_GPIO14_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO14_EN_S 16 +/** GPIO_ETM_TASK_GPIO14_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO14_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO14_SEL_M (GPIO_ETM_TASK_GPIO14_SEL_V << GPIO_ETM_TASK_GPIO14_SEL_S) +#define GPIO_ETM_TASK_GPIO14_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO14_SEL_S 17 +/** GPIO_ETM_TASK_GPIO15_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO15_EN (BIT(24)) +#define GPIO_ETM_TASK_GPIO15_EN_M (GPIO_ETM_TASK_GPIO15_EN_V << GPIO_ETM_TASK_GPIO15_EN_S) +#define GPIO_ETM_TASK_GPIO15_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO15_EN_S 24 +/** GPIO_ETM_TASK_GPIO15_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO15_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO15_SEL_M (GPIO_ETM_TASK_GPIO15_SEL_V << GPIO_ETM_TASK_GPIO15_SEL_S) +#define GPIO_ETM_TASK_GPIO15_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO15_SEL_S 25 + +/** GPIO_ETM_TASK_P4_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb0) +/** GPIO_ETM_TASK_GPIO16_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO16_EN (BIT(0)) +#define GPIO_ETM_TASK_GPIO16_EN_M (GPIO_ETM_TASK_GPIO16_EN_V << GPIO_ETM_TASK_GPIO16_EN_S) +#define GPIO_ETM_TASK_GPIO16_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO16_EN_S 0 +/** GPIO_ETM_TASK_GPIO16_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO16_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO16_SEL_M (GPIO_ETM_TASK_GPIO16_SEL_V << GPIO_ETM_TASK_GPIO16_SEL_S) +#define GPIO_ETM_TASK_GPIO16_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO16_SEL_S 1 +/** GPIO_ETM_TASK_GPIO17_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO17_EN (BIT(8)) +#define GPIO_ETM_TASK_GPIO17_EN_M (GPIO_ETM_TASK_GPIO17_EN_V << GPIO_ETM_TASK_GPIO17_EN_S) +#define GPIO_ETM_TASK_GPIO17_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO17_EN_S 8 +/** GPIO_ETM_TASK_GPIO17_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO17_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO17_SEL_M (GPIO_ETM_TASK_GPIO17_SEL_V << GPIO_ETM_TASK_GPIO17_SEL_S) +#define GPIO_ETM_TASK_GPIO17_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO17_SEL_S 9 +/** GPIO_ETM_TASK_GPIO18_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO18_EN (BIT(16)) +#define GPIO_ETM_TASK_GPIO18_EN_M (GPIO_ETM_TASK_GPIO18_EN_V << GPIO_ETM_TASK_GPIO18_EN_S) +#define GPIO_ETM_TASK_GPIO18_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO18_EN_S 16 +/** GPIO_ETM_TASK_GPIO18_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO18_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO18_SEL_M (GPIO_ETM_TASK_GPIO18_SEL_V << GPIO_ETM_TASK_GPIO18_SEL_S) +#define GPIO_ETM_TASK_GPIO18_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO18_SEL_S 17 +/** GPIO_ETM_TASK_GPIO19_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO19_EN (BIT(24)) +#define GPIO_ETM_TASK_GPIO19_EN_M (GPIO_ETM_TASK_GPIO19_EN_V << GPIO_ETM_TASK_GPIO19_EN_S) +#define GPIO_ETM_TASK_GPIO19_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO19_EN_S 24 +/** GPIO_ETM_TASK_GPIO19_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO19_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO19_SEL_M (GPIO_ETM_TASK_GPIO19_SEL_V << GPIO_ETM_TASK_GPIO19_SEL_S) +#define GPIO_ETM_TASK_GPIO19_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO19_SEL_S 25 + +/** GPIO_ETM_TASK_P5_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_ETM_TASK_P5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb4) +/** GPIO_ETM_TASK_GPIO20_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO20_EN (BIT(0)) +#define GPIO_ETM_TASK_GPIO20_EN_M (GPIO_ETM_TASK_GPIO20_EN_V << GPIO_ETM_TASK_GPIO20_EN_S) +#define GPIO_ETM_TASK_GPIO20_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO20_EN_S 0 +/** GPIO_ETM_TASK_GPIO20_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO20_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO20_SEL_M (GPIO_ETM_TASK_GPIO20_SEL_V << GPIO_ETM_TASK_GPIO20_SEL_S) +#define GPIO_ETM_TASK_GPIO20_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO20_SEL_S 1 +/** GPIO_ETM_TASK_GPIO21_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO21_EN (BIT(8)) +#define GPIO_ETM_TASK_GPIO21_EN_M (GPIO_ETM_TASK_GPIO21_EN_V << GPIO_ETM_TASK_GPIO21_EN_S) +#define GPIO_ETM_TASK_GPIO21_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO21_EN_S 8 +/** GPIO_ETM_TASK_GPIO21_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO21_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO21_SEL_M (GPIO_ETM_TASK_GPIO21_SEL_V << GPIO_ETM_TASK_GPIO21_SEL_S) +#define GPIO_ETM_TASK_GPIO21_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO21_SEL_S 9 +/** GPIO_ETM_TASK_GPIO22_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO22_EN (BIT(16)) +#define GPIO_ETM_TASK_GPIO22_EN_M (GPIO_ETM_TASK_GPIO22_EN_V << GPIO_ETM_TASK_GPIO22_EN_S) +#define GPIO_ETM_TASK_GPIO22_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO22_EN_S 16 +/** GPIO_ETM_TASK_GPIO22_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO22_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO22_SEL_M (GPIO_ETM_TASK_GPIO22_SEL_V << GPIO_ETM_TASK_GPIO22_SEL_S) +#define GPIO_ETM_TASK_GPIO22_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO22_SEL_S 17 +/** GPIO_ETM_TASK_GPIO23_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO23_EN (BIT(24)) +#define GPIO_ETM_TASK_GPIO23_EN_M (GPIO_ETM_TASK_GPIO23_EN_V << GPIO_ETM_TASK_GPIO23_EN_S) +#define GPIO_ETM_TASK_GPIO23_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO23_EN_S 24 +/** GPIO_ETM_TASK_GPIO23_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO23_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO23_SEL_M (GPIO_ETM_TASK_GPIO23_SEL_V << GPIO_ETM_TASK_GPIO23_SEL_S) +#define GPIO_ETM_TASK_GPIO23_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO23_SEL_S 25 + +/** GPIO_ETM_TASK_P6_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_ETM_TASK_P6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb8) +/** GPIO_ETM_TASK_GPIO24_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO24_EN (BIT(0)) +#define GPIO_ETM_TASK_GPIO24_EN_M (GPIO_ETM_TASK_GPIO24_EN_V << GPIO_ETM_TASK_GPIO24_EN_S) +#define GPIO_ETM_TASK_GPIO24_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO24_EN_S 0 +/** GPIO_ETM_TASK_GPIO24_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO24_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO24_SEL_M (GPIO_ETM_TASK_GPIO24_SEL_V << GPIO_ETM_TASK_GPIO24_SEL_S) +#define GPIO_ETM_TASK_GPIO24_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO24_SEL_S 1 +/** GPIO_ETM_TASK_GPIO25_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO25_EN (BIT(8)) +#define GPIO_ETM_TASK_GPIO25_EN_M (GPIO_ETM_TASK_GPIO25_EN_V << GPIO_ETM_TASK_GPIO25_EN_S) +#define GPIO_ETM_TASK_GPIO25_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO25_EN_S 8 +/** GPIO_ETM_TASK_GPIO25_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO25_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO25_SEL_M (GPIO_ETM_TASK_GPIO25_SEL_V << GPIO_ETM_TASK_GPIO25_SEL_S) +#define GPIO_ETM_TASK_GPIO25_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO25_SEL_S 9 +/** GPIO_ETM_TASK_GPIO26_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO26_EN (BIT(16)) +#define GPIO_ETM_TASK_GPIO26_EN_M (GPIO_ETM_TASK_GPIO26_EN_V << GPIO_ETM_TASK_GPIO26_EN_S) +#define GPIO_ETM_TASK_GPIO26_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO26_EN_S 16 +/** GPIO_ETM_TASK_GPIO26_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO26_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO26_SEL_M (GPIO_ETM_TASK_GPIO26_SEL_V << GPIO_ETM_TASK_GPIO26_SEL_S) +#define GPIO_ETM_TASK_GPIO26_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO26_SEL_S 17 +/** GPIO_ETM_TASK_GPIO27_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO27_EN (BIT(24)) +#define GPIO_ETM_TASK_GPIO27_EN_M (GPIO_ETM_TASK_GPIO27_EN_V << GPIO_ETM_TASK_GPIO27_EN_S) +#define GPIO_ETM_TASK_GPIO27_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO27_EN_S 24 +/** GPIO_ETM_TASK_GPIO27_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO27_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO27_SEL_M (GPIO_ETM_TASK_GPIO27_SEL_V << GPIO_ETM_TASK_GPIO27_SEL_S) +#define GPIO_ETM_TASK_GPIO27_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO27_SEL_S 25 + +/** GPIO_ETM_TASK_P7_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_ETM_TASK_P7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xbc) +/** GPIO_ETM_TASK_GPIO28_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO28_EN (BIT(0)) +#define GPIO_ETM_TASK_GPIO28_EN_M (GPIO_ETM_TASK_GPIO28_EN_V << GPIO_ETM_TASK_GPIO28_EN_S) +#define GPIO_ETM_TASK_GPIO28_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO28_EN_S 0 +/** GPIO_ETM_TASK_GPIO28_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO28_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO28_SEL_M (GPIO_ETM_TASK_GPIO28_SEL_V << GPIO_ETM_TASK_GPIO28_SEL_S) +#define GPIO_ETM_TASK_GPIO28_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO28_SEL_S 1 +/** GPIO_ETM_TASK_GPIO29_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO29_EN (BIT(8)) +#define GPIO_ETM_TASK_GPIO29_EN_M (GPIO_ETM_TASK_GPIO29_EN_V << GPIO_ETM_TASK_GPIO29_EN_S) +#define GPIO_ETM_TASK_GPIO29_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO29_EN_S 8 +/** GPIO_ETM_TASK_GPIO29_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO29_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO29_SEL_M (GPIO_ETM_TASK_GPIO29_SEL_V << GPIO_ETM_TASK_GPIO29_SEL_S) +#define GPIO_ETM_TASK_GPIO29_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO29_SEL_S 9 +/** GPIO_ETM_TASK_GPIO30_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_ETM_TASK_GPIO30_EN (BIT(16)) +#define GPIO_ETM_TASK_GPIO30_EN_M (GPIO_ETM_TASK_GPIO30_EN_V << GPIO_ETM_TASK_GPIO30_EN_S) +#define GPIO_ETM_TASK_GPIO30_EN_V 0x00000001U +#define GPIO_ETM_TASK_GPIO30_EN_S 16 +/** GPIO_ETM_TASK_GPIO30_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_ETM_TASK_GPIO30_SEL 0x00000007U +#define GPIO_ETM_TASK_GPIO30_SEL_M (GPIO_ETM_TASK_GPIO30_SEL_V << GPIO_ETM_TASK_GPIO30_SEL_S) +#define GPIO_ETM_TASK_GPIO30_SEL_V 0x00000007U +#define GPIO_ETM_TASK_GPIO30_SEL_S 17 + +/** GPIO_EXT_VERSION_REG register + * Version Control Register + */ +#define GPIO_EXT_VERSION_REG (DR_REG_GPIO_EXT_BASE + 0xfc) +/** GPIO_EXT_DATE : R/W; bitpos: [27:0]; default: 35663952; + * Version control register. + */ +#define GPIO_EXT_DATE 0x0FFFFFFFU +#define GPIO_EXT_DATE_M (GPIO_EXT_DATE_V << GPIO_EXT_DATE_S) +#define GPIO_EXT_DATE_V 0x0FFFFFFFU +#define GPIO_EXT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/gpio_ext_struct.h b/components/soc/esp32c6/include/soc/gpio_ext_struct.h new file mode 100644 index 0000000000..b06cd88027 --- /dev/null +++ b/components/soc/esp32c6/include/soc/gpio_ext_struct.h @@ -0,0 +1,527 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: SDM Configure Registers */ +/** Type of sigmadelta_chn register + * Duty Cycle Configure Register of SDMn + */ +typedef union { + struct { + /** duty : R/W; bitpos: [7:0]; default: 0; + * This field is used to configure the duty cycle of sigma delta modulation output. + */ + uint32_t duty:8; + /** prescale : R/W; bitpos: [15:8]; default: 255; + * This field is used to set a divider value to divide APB clock. + */ + uint32_t prescale:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} gpio_sigmadelta_chn_reg_t; + +/** Type of sigmadelta_misc register + * MISC Register + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** function_clk_en : R/W; bitpos: [30]; default: 0; + * Clock enable bit of sigma delta modulation. + */ + uint32_t function_clk_en:1; + /** spi_swap : R/W; bitpos: [31]; default: 0; + * Reserved. + */ + uint32_t spi_swap:1; + }; + uint32_t val; +} gpio_sigmadelta_misc_reg_t; + + +/** Group: Clock gate Register */ +/** Type of clock_gate register + * Clock Gating Configure Register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Clock enable bit of configuration registers for sigma delta modulation. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gpio_sigmadelta_clock_gate_reg_t; + + +/** Group: Glitch filter Configure Registers */ +/** Type of glitch_filter_chn register + * Glitch Filter Configure Register of Channeln + */ +typedef union { + struct { + /** filter_ch0_en : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ + uint32_t filter_ch0_en:1; + /** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ + uint32_t filter_ch0_input_io_num:6; + /** filter_ch0_window_thres : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ + uint32_t filter_ch0_window_thres:6; + /** filter_ch0_window_width : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ + uint32_t filter_ch0_window_width:6; + uint32_t reserved_19:13; + }; + uint32_t val; +} gpio_glitch_filter_chn_reg_t; + + +/** Group: Etm Configure Registers */ +/** Type of etm_event_chn_cfg register + * Etm Config register of Channeln + */ +typedef union { + struct { + /** etm_ch0_event_sel : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ + uint32_t etm_ch0_event_sel:5; + uint32_t reserved_5:2; + /** etm_ch0_event_en : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ + uint32_t etm_ch0_event_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_etm_event_chn_cfg_reg_t; + +/** Type of etm_task_p0_cfg register + * Etm Configure Register to decide which GPIO been chosen + */ +typedef union { + struct { + /** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio0_en:1; + /** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio0_sel:3; + uint32_t reserved_4:4; + /** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio1_en:1; + /** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio1_sel:3; + uint32_t reserved_12:4; + /** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio2_en:1; + /** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio2_sel:3; + uint32_t reserved_20:4; + /** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio3_en:1; + /** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio3_sel:3; + uint32_t reserved_28:4; + }; + uint32_t val; +} gpio_etm_task_p0_cfg_reg_t; + +/** Type of etm_task_p1_cfg register + * Etm Configure Register to decide which GPIO been chosen + */ +typedef union { + struct { + /** etm_task_gpio4_en : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio4_en:1; + /** etm_task_gpio4_sel : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio4_sel:3; + uint32_t reserved_4:4; + /** etm_task_gpio5_en : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio5_en:1; + /** etm_task_gpio5_sel : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio5_sel:3; + uint32_t reserved_12:4; + /** etm_task_gpio6_en : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio6_en:1; + /** etm_task_gpio6_sel : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio6_sel:3; + uint32_t reserved_20:4; + /** etm_task_gpio7_en : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio7_en:1; + /** etm_task_gpio7_sel : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio7_sel:3; + uint32_t reserved_28:4; + }; + uint32_t val; +} gpio_etm_task_p1_cfg_reg_t; + +/** Type of etm_task_p2_cfg register + * Etm Configure Register to decide which GPIO been chosen + */ +typedef union { + struct { + /** etm_task_gpio8_en : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio8_en:1; + /** etm_task_gpio8_sel : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio8_sel:3; + uint32_t reserved_4:4; + /** etm_task_gpio9_en : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio9_en:1; + /** etm_task_gpio9_sel : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio9_sel:3; + uint32_t reserved_12:4; + /** etm_task_gpio10_en : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio10_en:1; + /** etm_task_gpio10_sel : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio10_sel:3; + uint32_t reserved_20:4; + /** etm_task_gpio11_en : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio11_en:1; + /** etm_task_gpio11_sel : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio11_sel:3; + uint32_t reserved_28:4; + }; + uint32_t val; +} gpio_etm_task_p2_cfg_reg_t; + +/** Type of etm_task_p3_cfg register + * Etm Configure Register to decide which GPIO been chosen + */ +typedef union { + struct { + /** etm_task_gpio12_en : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio12_en:1; + /** etm_task_gpio12_sel : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio12_sel:3; + uint32_t reserved_4:4; + /** etm_task_gpio13_en : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio13_en:1; + /** etm_task_gpio13_sel : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio13_sel:3; + uint32_t reserved_12:4; + /** etm_task_gpio14_en : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio14_en:1; + /** etm_task_gpio14_sel : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio14_sel:3; + uint32_t reserved_20:4; + /** etm_task_gpio15_en : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio15_en:1; + /** etm_task_gpio15_sel : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio15_sel:3; + uint32_t reserved_28:4; + }; + uint32_t val; +} gpio_etm_task_p3_cfg_reg_t; + +/** Type of etm_task_p4_cfg register + * Etm Configure Register to decide which GPIO been chosen + */ +typedef union { + struct { + /** etm_task_gpio16_en : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio16_en:1; + /** etm_task_gpio16_sel : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio16_sel:3; + uint32_t reserved_4:4; + /** etm_task_gpio17_en : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio17_en:1; + /** etm_task_gpio17_sel : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio17_sel:3; + uint32_t reserved_12:4; + /** etm_task_gpio18_en : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio18_en:1; + /** etm_task_gpio18_sel : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio18_sel:3; + uint32_t reserved_20:4; + /** etm_task_gpio19_en : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio19_en:1; + /** etm_task_gpio19_sel : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio19_sel:3; + uint32_t reserved_28:4; + }; + uint32_t val; +} gpio_etm_task_p4_cfg_reg_t; + +/** Type of etm_task_p5_cfg register + * Etm Configure Register to decide which GPIO been chosen + */ +typedef union { + struct { + /** etm_task_gpio20_en : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio20_en:1; + /** etm_task_gpio20_sel : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio20_sel:3; + uint32_t reserved_4:4; + /** etm_task_gpio21_en : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio21_en:1; + /** etm_task_gpio21_sel : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio21_sel:3; + uint32_t reserved_12:4; + /** etm_task_gpio22_en : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio22_en:1; + /** etm_task_gpio22_sel : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio22_sel:3; + uint32_t reserved_20:4; + /** etm_task_gpio23_en : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio23_en:1; + /** etm_task_gpio23_sel : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio23_sel:3; + uint32_t reserved_28:4; + }; + uint32_t val; +} gpio_etm_task_p5_cfg_reg_t; + +/** Type of etm_task_p6_cfg register + * Etm Configure Register to decide which GPIO been chosen + */ +typedef union { + struct { + /** etm_task_gpio24_en : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio24_en:1; + /** etm_task_gpio24_sel : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio24_sel:3; + uint32_t reserved_4:4; + /** etm_task_gpio25_en : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio25_en:1; + /** etm_task_gpio25_sel : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio25_sel:3; + uint32_t reserved_12:4; + /** etm_task_gpio26_en : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio26_en:1; + /** etm_task_gpio26_sel : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio26_sel:3; + uint32_t reserved_20:4; + /** etm_task_gpio27_en : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio27_en:1; + /** etm_task_gpio27_sel : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio27_sel:3; + uint32_t reserved_28:4; + }; + uint32_t val; +} gpio_etm_task_p6_cfg_reg_t; + +/** Type of etm_task_p7_cfg register + * Etm Configure Register to decide which GPIO been chosen + */ +typedef union { + struct { + /** etm_task_gpio28_en : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio28_en:1; + /** etm_task_gpio28_sel : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio28_sel:3; + uint32_t reserved_4:4; + /** etm_task_gpio29_en : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio29_en:1; + /** etm_task_gpio29_sel : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio29_sel:3; + uint32_t reserved_12:4; + /** etm_task_gpio30_en : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio30_en:1; + /** etm_task_gpio30_sel : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio30_sel:3; + uint32_t reserved_20:12; + }; + uint32_t val; +} gpio_etm_task_p7_cfg_reg_t; + + +/** Group: Version Register */ +/** Type of version register + * Version Control Register + */ +typedef union { + struct { + /** gpio_ext_date : R/W; bitpos: [27:0]; default: 35663952; + * Version control register. + */ + uint32_t gpio_ext_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} gpio_ext_version_reg_t; + + +typedef struct gpio_sd_dev_t { + volatile gpio_sigmadelta_chn_reg_t channel[4]; + uint32_t reserved_010[4]; + volatile gpio_sigmadelta_clock_gate_reg_t clock_gate; + volatile gpio_sigmadelta_misc_reg_t misc; +} gpio_sd_dev_t; + +typedef struct { + volatile gpio_glitch_filter_chn_reg_t glitch_filter_chn[8]; +} gpio_glitch_filter_dev_t; + +typedef struct { + volatile gpio_etm_event_chn_cfg_reg_t event_chn_cfg[8]; + uint32_t reserved_080[8]; + volatile gpio_etm_task_p0_cfg_reg_t etm_task_p0_cfg; + volatile gpio_etm_task_p1_cfg_reg_t etm_task_p1_cfg; + volatile gpio_etm_task_p2_cfg_reg_t etm_task_p2_cfg; + volatile gpio_etm_task_p3_cfg_reg_t etm_task_p3_cfg; + volatile gpio_etm_task_p4_cfg_reg_t etm_task_p4_cfg; + volatile gpio_etm_task_p5_cfg_reg_t etm_task_p5_cfg; + volatile gpio_etm_task_p6_cfg_reg_t etm_task_p6_cfg; + volatile gpio_etm_task_p7_cfg_reg_t etm_task_p7_cfg; +} gpio_etm_dev_t; + +typedef struct gpio_ext_dev_t { + volatile gpio_sd_dev_t sigma_delta; + uint32_t reserved_028[2]; + volatile gpio_glitch_filter_dev_t glitch_filter; + uint32_t reserved_050[4]; + volatile gpio_etm_dev_t etm; + uint32_t reserved_0c0[15]; + volatile gpio_ext_version_reg_t version; +} gpio_ext_dev_t; + +extern gpio_sd_dev_t SDM; +extern gpio_glitch_filter_dev_t GLITCH_FILTER; +extern gpio_etm_dev_t GPIO_ETM; + +#ifndef __cplusplus +_Static_assert(sizeof(gpio_ext_dev_t) == 0x100, "Invalid size of gpio_ext_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/gpio_pins.h b/components/soc/esp32c6/include/soc/gpio_pins.h new file mode 100644 index 0000000000..78af5a05dc --- /dev/null +++ b/components/soc/esp32c6/include/soc/gpio_pins.h @@ -0,0 +1,19 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define GPIO_MATRIX_CONST_ONE_INPUT (0x38) +#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/gpio_reg.h b/components/soc/esp32c6/include/soc/gpio_reg.h new file mode 100644 index 0000000000..ab26c59dc9 --- /dev/null +++ b/components/soc/esp32c6/include/soc/gpio_reg.h @@ -0,0 +1,6275 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** GPIO_BT_SELECT_REG register + * GPIO bit select register + */ +#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0) +/** GPIO_BT_SEL : R/W; bitpos: [31:0]; default: 0; + * GPIO bit select register + */ +#define GPIO_BT_SEL 0xFFFFFFFFU +#define GPIO_BT_SEL_M (GPIO_BT_SEL_V << GPIO_BT_SEL_S) +#define GPIO_BT_SEL_V 0xFFFFFFFFU +#define GPIO_BT_SEL_S 0 + +/** GPIO_OUT_REG register + * GPIO output register for GPIO0-31 + */ +#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4) +/** GPIO_OUT_DATA_ORIG : R/W/SC/WTC; bitpos: [31:0]; default: 0; + * GPIO output register for GPIO0-31 + */ +#define GPIO_OUT_DATA_ORIG 0xFFFFFFFFU +#define GPIO_OUT_DATA_ORIG_M (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S) +#define GPIO_OUT_DATA_ORIG_V 0xFFFFFFFFU +#define GPIO_OUT_DATA_ORIG_S 0 + +/** GPIO_OUT_W1TS_REG register + * GPIO output set register for GPIO0-31 + */ +#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8) +/** GPIO_OUT_W1TS : WT; bitpos: [31:0]; default: 0; + * GPIO output set register for GPIO0-31 + */ +#define GPIO_OUT_W1TS 0xFFFFFFFFU +#define GPIO_OUT_W1TS_M (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S) +#define GPIO_OUT_W1TS_V 0xFFFFFFFFU +#define GPIO_OUT_W1TS_S 0 + +/** GPIO_OUT_W1TC_REG register + * GPIO output clear register for GPIO0-31 + */ +#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc) +/** GPIO_OUT_W1TC : WT; bitpos: [31:0]; default: 0; + * GPIO output clear register for GPIO0-31 + */ +#define GPIO_OUT_W1TC 0xFFFFFFFFU +#define GPIO_OUT_W1TC_M (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S) +#define GPIO_OUT_W1TC_V 0xFFFFFFFFU +#define GPIO_OUT_W1TC_S 0 + +/** GPIO_OUT1_REG register + * GPIO output register for GPIO32-34 + */ +#define GPIO_OUT1_REG (DR_REG_GPIO_BASE + 0x10) +/** GPIO_OUT1_DATA_ORIG : R/W/SC/WTC; bitpos: [2:0]; default: 0; + * GPIO output register for GPIO32-34 + */ +#define GPIO_OUT1_DATA_ORIG 0x00000007U +#define GPIO_OUT1_DATA_ORIG_M (GPIO_OUT1_DATA_ORIG_V << GPIO_OUT1_DATA_ORIG_S) +#define GPIO_OUT1_DATA_ORIG_V 0x00000007U +#define GPIO_OUT1_DATA_ORIG_S 0 + +/** GPIO_OUT1_W1TS_REG register + * GPIO output set register for GPIO32-34 + */ +#define GPIO_OUT1_W1TS_REG (DR_REG_GPIO_BASE + 0x14) +/** GPIO_OUT1_W1TS : WT; bitpos: [2:0]; default: 0; + * GPIO output set register for GPIO32-34 + */ +#define GPIO_OUT1_W1TS 0x00000007U +#define GPIO_OUT1_W1TS_M (GPIO_OUT1_W1TS_V << GPIO_OUT1_W1TS_S) +#define GPIO_OUT1_W1TS_V 0x00000007U +#define GPIO_OUT1_W1TS_S 0 + +/** GPIO_OUT1_W1TC_REG register + * GPIO output clear register for GPIO32-34 + */ +#define GPIO_OUT1_W1TC_REG (DR_REG_GPIO_BASE + 0x18) +/** GPIO_OUT1_W1TC : WT; bitpos: [2:0]; default: 0; + * GPIO output clear register for GPIO32-34 + */ +#define GPIO_OUT1_W1TC 0x00000007U +#define GPIO_OUT1_W1TC_M (GPIO_OUT1_W1TC_V << GPIO_OUT1_W1TC_S) +#define GPIO_OUT1_W1TC_V 0x00000007U +#define GPIO_OUT1_W1TC_S 0 + +/** GPIO_SDIO_SELECT_REG register + * GPIO sdio select register + */ +#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x1c) +/** GPIO_SDIO_SEL : R/W; bitpos: [7:0]; default: 0; + * GPIO sdio select register + */ +#define GPIO_SDIO_SEL 0x000000FFU +#define GPIO_SDIO_SEL_M (GPIO_SDIO_SEL_V << GPIO_SDIO_SEL_S) +#define GPIO_SDIO_SEL_V 0x000000FFU +#define GPIO_SDIO_SEL_S 0 + +/** GPIO_ENABLE_REG register + * GPIO output enable register for GPIO0-31 + */ +#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20) +/** GPIO_ENABLE_DATA : R/W/WTC; bitpos: [31:0]; default: 0; + * GPIO output enable register for GPIO0-31 + */ +#define GPIO_ENABLE_DATA 0xFFFFFFFFU +#define GPIO_ENABLE_DATA_M (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S) +#define GPIO_ENABLE_DATA_V 0xFFFFFFFFU +#define GPIO_ENABLE_DATA_S 0 + +/** GPIO_ENABLE_W1TS_REG register + * GPIO output enable set register for GPIO0-31 + */ +#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24) +/** GPIO_ENABLE_W1TS : WT; bitpos: [31:0]; default: 0; + * GPIO output enable set register for GPIO0-31 + */ +#define GPIO_ENABLE_W1TS 0xFFFFFFFFU +#define GPIO_ENABLE_W1TS_M (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S) +#define GPIO_ENABLE_W1TS_V 0xFFFFFFFFU +#define GPIO_ENABLE_W1TS_S 0 + +/** GPIO_ENABLE_W1TC_REG register + * GPIO output enable clear register for GPIO0-31 + */ +#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28) +/** GPIO_ENABLE_W1TC : WT; bitpos: [31:0]; default: 0; + * GPIO output enable clear register for GPIO0-31 + */ +#define GPIO_ENABLE_W1TC 0xFFFFFFFFU +#define GPIO_ENABLE_W1TC_M (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S) +#define GPIO_ENABLE_W1TC_V 0xFFFFFFFFU +#define GPIO_ENABLE_W1TC_S 0 + +/** GPIO_ENABLE1_REG register + * GPIO output enable register for GPIO32-34 + */ +#define GPIO_ENABLE1_REG (DR_REG_GPIO_BASE + 0x2c) +/** GPIO_ENABLE1_DATA : R/W/WTC; bitpos: [2:0]; default: 0; + * GPIO output enable register for GPIO32-34 + */ +#define GPIO_ENABLE1_DATA 0x00000007U +#define GPIO_ENABLE1_DATA_M (GPIO_ENABLE1_DATA_V << GPIO_ENABLE1_DATA_S) +#define GPIO_ENABLE1_DATA_V 0x00000007U +#define GPIO_ENABLE1_DATA_S 0 + +/** GPIO_ENABLE1_W1TS_REG register + * GPIO output enable set register for GPIO32-34 + */ +#define GPIO_ENABLE1_W1TS_REG (DR_REG_GPIO_BASE + 0x30) +/** GPIO_ENABLE1_W1TS : WT; bitpos: [2:0]; default: 0; + * GPIO output enable set register for GPIO32-34 + */ +#define GPIO_ENABLE1_W1TS 0x00000007U +#define GPIO_ENABLE1_W1TS_M (GPIO_ENABLE1_W1TS_V << GPIO_ENABLE1_W1TS_S) +#define GPIO_ENABLE1_W1TS_V 0x00000007U +#define GPIO_ENABLE1_W1TS_S 0 + +/** GPIO_ENABLE1_W1TC_REG register + * GPIO output enable clear register for GPIO32-34 + */ +#define GPIO_ENABLE1_W1TC_REG (DR_REG_GPIO_BASE + 0x34) +/** GPIO_ENABLE1_W1TC : WT; bitpos: [2:0]; default: 0; + * GPIO output enable clear register for GPIO32-34 + */ +#define GPIO_ENABLE1_W1TC 0x00000007U +#define GPIO_ENABLE1_W1TC_M (GPIO_ENABLE1_W1TC_V << GPIO_ENABLE1_W1TC_S) +#define GPIO_ENABLE1_W1TC_V 0x00000007U +#define GPIO_ENABLE1_W1TC_S 0 + +/** GPIO_STRAP_REG register + * pad strapping register + */ +#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38) +/** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0; + * pad strapping register + */ +#define GPIO_STRAPPING 0x0000FFFFU +#define GPIO_STRAPPING_M (GPIO_STRAPPING_V << GPIO_STRAPPING_S) +#define GPIO_STRAPPING_V 0x0000FFFFU +#define GPIO_STRAPPING_S 0 + +/** GPIO_IN_REG register + * GPIO input register for GPIO0-31 + */ +#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3c) +/** GPIO_IN_DATA_NEXT : RO; bitpos: [31:0]; default: 0; + * GPIO input register for GPIO0-31 + */ +#define GPIO_IN_DATA_NEXT 0xFFFFFFFFU +#define GPIO_IN_DATA_NEXT_M (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S) +#define GPIO_IN_DATA_NEXT_V 0xFFFFFFFFU +#define GPIO_IN_DATA_NEXT_S 0 + +/** GPIO_IN1_REG register + * GPIO input register for GPIO32-34 + */ +#define GPIO_IN1_REG (DR_REG_GPIO_BASE + 0x40) +/** GPIO_IN1_DATA_NEXT : RO; bitpos: [2:0]; default: 0; + * GPIO input register for GPIO32-34 + */ +#define GPIO_IN1_DATA_NEXT 0x00000007U +#define GPIO_IN1_DATA_NEXT_M (GPIO_IN1_DATA_NEXT_V << GPIO_IN1_DATA_NEXT_S) +#define GPIO_IN1_DATA_NEXT_V 0x00000007U +#define GPIO_IN1_DATA_NEXT_S 0 + +/** GPIO_STATUS_REG register + * GPIO interrupt status register for GPIO0-31 + */ +#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44) +/** GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [31:0]; default: 0; + * GPIO interrupt status register for GPIO0-31 + */ +#define GPIO_STATUS_INTERRUPT 0xFFFFFFFFU +#define GPIO_STATUS_INTERRUPT_M (GPIO_STATUS_INTERRUPT_V << GPIO_STATUS_INTERRUPT_S) +#define GPIO_STATUS_INTERRUPT_V 0xFFFFFFFFU +#define GPIO_STATUS_INTERRUPT_S 0 + +/** GPIO_STATUS_W1TS_REG register + * GPIO interrupt status set register for GPIO0-31 + */ +#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48) +/** GPIO_STATUS_W1TS : WT; bitpos: [31:0]; default: 0; + * GPIO interrupt status set register for GPIO0-31 + */ +#define GPIO_STATUS_W1TS 0xFFFFFFFFU +#define GPIO_STATUS_W1TS_M (GPIO_STATUS_W1TS_V << GPIO_STATUS_W1TS_S) +#define GPIO_STATUS_W1TS_V 0xFFFFFFFFU +#define GPIO_STATUS_W1TS_S 0 + +/** GPIO_STATUS_W1TC_REG register + * GPIO interrupt status clear register for GPIO0-31 + */ +#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4c) +/** GPIO_STATUS_W1TC : WT; bitpos: [31:0]; default: 0; + * GPIO interrupt status clear register for GPIO0-31 + */ +#define GPIO_STATUS_W1TC 0xFFFFFFFFU +#define GPIO_STATUS_W1TC_M (GPIO_STATUS_W1TC_V << GPIO_STATUS_W1TC_S) +#define GPIO_STATUS_W1TC_V 0xFFFFFFFFU +#define GPIO_STATUS_W1TC_S 0 + +/** GPIO_STATUS1_REG register + * GPIO interrupt status register for GPIO32-34 + */ +#define GPIO_STATUS1_REG (DR_REG_GPIO_BASE + 0x50) +/** GPIO_STATUS1_INTERRUPT : R/W/WTC; bitpos: [2:0]; default: 0; + * GPIO interrupt status register for GPIO32-34 + */ +#define GPIO_STATUS1_INTERRUPT 0x00000007U +#define GPIO_STATUS1_INTERRUPT_M (GPIO_STATUS1_INTERRUPT_V << GPIO_STATUS1_INTERRUPT_S) +#define GPIO_STATUS1_INTERRUPT_V 0x00000007U +#define GPIO_STATUS1_INTERRUPT_S 0 + +/** GPIO_STATUS1_W1TS_REG register + * GPIO interrupt status set register for GPIO32-34 + */ +#define GPIO_STATUS1_W1TS_REG (DR_REG_GPIO_BASE + 0x54) +/** GPIO_STATUS1_W1TS : WT; bitpos: [2:0]; default: 0; + * GPIO interrupt status set register for GPIO32-34 + */ +#define GPIO_STATUS1_W1TS 0x00000007U +#define GPIO_STATUS1_W1TS_M (GPIO_STATUS1_W1TS_V << GPIO_STATUS1_W1TS_S) +#define GPIO_STATUS1_W1TS_V 0x00000007U +#define GPIO_STATUS1_W1TS_S 0 + +/** GPIO_STATUS1_W1TC_REG register + * GPIO interrupt status clear register for GPIO32-34 + */ +#define GPIO_STATUS1_W1TC_REG (DR_REG_GPIO_BASE + 0x58) +/** GPIO_STATUS1_W1TC : WT; bitpos: [2:0]; default: 0; + * GPIO interrupt status clear register for GPIO32-34 + */ +#define GPIO_STATUS1_W1TC 0x00000007U +#define GPIO_STATUS1_W1TC_M (GPIO_STATUS1_W1TC_V << GPIO_STATUS1_W1TC_S) +#define GPIO_STATUS1_W1TC_V 0x00000007U +#define GPIO_STATUS1_W1TC_S 0 + +/** GPIO_PCPU_INT_REG register + * GPIO PRO_CPU interrupt status register for GPIO0-31 + */ +#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x5c) +/** GPIO_PROCPU_INT : RO; bitpos: [31:0]; default: 0; + * GPIO PRO_CPU interrupt status register for GPIO0-31 + */ +#define GPIO_PROCPU_INT 0xFFFFFFFFU +#define GPIO_PROCPU_INT_M (GPIO_PROCPU_INT_V << GPIO_PROCPU_INT_S) +#define GPIO_PROCPU_INT_V 0xFFFFFFFFU +#define GPIO_PROCPU_INT_S 0 + +/** GPIO_PCPU_NMI_INT_REG register + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + */ +#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x60) +/** GPIO_PROCPU_NMI_INT : RO; bitpos: [31:0]; default: 0; + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + */ +#define GPIO_PROCPU_NMI_INT 0xFFFFFFFFU +#define GPIO_PROCPU_NMI_INT_M (GPIO_PROCPU_NMI_INT_V << GPIO_PROCPU_NMI_INT_S) +#define GPIO_PROCPU_NMI_INT_V 0xFFFFFFFFU +#define GPIO_PROCPU_NMI_INT_S 0 + +/** GPIO_CPUSDIO_INT_REG register + * GPIO CPUSDIO interrupt status register for GPIO0-31 + */ +#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x64) +/** GPIO_SDIO_INT : RO; bitpos: [31:0]; default: 0; + * GPIO CPUSDIO interrupt status register for GPIO0-31 + */ +#define GPIO_SDIO_INT 0xFFFFFFFFU +#define GPIO_SDIO_INT_M (GPIO_SDIO_INT_V << GPIO_SDIO_INT_S) +#define GPIO_SDIO_INT_V 0xFFFFFFFFU +#define GPIO_SDIO_INT_S 0 + +/** GPIO_PCPU_INT1_REG register + * GPIO PRO_CPU interrupt status register for GPIO32-34 + */ +#define GPIO_PCPU_INT1_REG (DR_REG_GPIO_BASE + 0x68) +/** GPIO_PROCPU_INT1 : RO; bitpos: [2:0]; default: 0; + * GPIO PRO_CPU interrupt status register for GPIO32-34 + */ +#define GPIO_PROCPU_INT1 0x00000007U +#define GPIO_PROCPU_INT1_M (GPIO_PROCPU_INT1_V << GPIO_PROCPU_INT1_S) +#define GPIO_PROCPU_INT1_V 0x00000007U +#define GPIO_PROCPU_INT1_S 0 + +/** GPIO_PCPU_NMI_INT1_REG register + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-34 + */ +#define GPIO_PCPU_NMI_INT1_REG (DR_REG_GPIO_BASE + 0x6c) +/** GPIO_PROCPU_NMI_INT1 : RO; bitpos: [2:0]; default: 0; + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-34 + */ +#define GPIO_PROCPU_NMI_INT1 0x00000007U +#define GPIO_PROCPU_NMI_INT1_M (GPIO_PROCPU_NMI_INT1_V << GPIO_PROCPU_NMI_INT1_S) +#define GPIO_PROCPU_NMI_INT1_V 0x00000007U +#define GPIO_PROCPU_NMI_INT1_S 0 + +/** GPIO_CPUSDIO_INT1_REG register + * GPIO CPUSDIO interrupt status register for GPIO32-34 + */ +#define GPIO_CPUSDIO_INT1_REG (DR_REG_GPIO_BASE + 0x70) +/** GPIO_SDIO_INT1 : RO; bitpos: [2:0]; default: 0; + * GPIO CPUSDIO interrupt status register for GPIO32-34 + */ +#define GPIO_SDIO_INT1 0x00000007U +#define GPIO_SDIO_INT1_M (GPIO_SDIO_INT1_V << GPIO_SDIO_INT1_S) +#define GPIO_SDIO_INT1_V 0x00000007U +#define GPIO_SDIO_INT1_S 0 + +/** GPIO_PIN0_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74) +/** GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN0_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN0_SYNC2_BYPASS_M (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S) +#define GPIO_PIN0_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN0_SYNC2_BYPASS_S 0 +/** GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER_M (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S) +#define GPIO_PIN0_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN0_PAD_DRIVER_S 2 +/** GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN0_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN0_SYNC1_BYPASS_M (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S) +#define GPIO_PIN0_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN0_SYNC1_BYPASS_S 3 +/** GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN0_INT_TYPE 0x00000007U +#define GPIO_PIN0_INT_TYPE_M (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S) +#define GPIO_PIN0_INT_TYPE_V 0x00000007U +#define GPIO_PIN0_INT_TYPE_S 7 +/** GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE_M (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S) +#define GPIO_PIN0_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN0_WAKEUP_ENABLE_S 10 +/** GPIO_PIN0_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN0_CONFIG 0x00000003U +#define GPIO_PIN0_CONFIG_M (GPIO_PIN0_CONFIG_V << GPIO_PIN0_CONFIG_S) +#define GPIO_PIN0_CONFIG_V 0x00000003U +#define GPIO_PIN0_CONFIG_S 11 +/** GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN0_INT_ENA 0x0000001FU +#define GPIO_PIN0_INT_ENA_M (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S) +#define GPIO_PIN0_INT_ENA_V 0x0000001FU +#define GPIO_PIN0_INT_ENA_S 13 + +/** GPIO_PIN1_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78) +/** GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN1_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN1_SYNC2_BYPASS_M (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S) +#define GPIO_PIN1_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN1_SYNC2_BYPASS_S 0 +/** GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER_M (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S) +#define GPIO_PIN1_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN1_PAD_DRIVER_S 2 +/** GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN1_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN1_SYNC1_BYPASS_M (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S) +#define GPIO_PIN1_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN1_SYNC1_BYPASS_S 3 +/** GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN1_INT_TYPE 0x00000007U +#define GPIO_PIN1_INT_TYPE_M (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S) +#define GPIO_PIN1_INT_TYPE_V 0x00000007U +#define GPIO_PIN1_INT_TYPE_S 7 +/** GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE_M (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S) +#define GPIO_PIN1_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN1_WAKEUP_ENABLE_S 10 +/** GPIO_PIN1_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN1_CONFIG 0x00000003U +#define GPIO_PIN1_CONFIG_M (GPIO_PIN1_CONFIG_V << GPIO_PIN1_CONFIG_S) +#define GPIO_PIN1_CONFIG_V 0x00000003U +#define GPIO_PIN1_CONFIG_S 11 +/** GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN1_INT_ENA 0x0000001FU +#define GPIO_PIN1_INT_ENA_M (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S) +#define GPIO_PIN1_INT_ENA_V 0x0000001FU +#define GPIO_PIN1_INT_ENA_S 13 + +/** GPIO_PIN2_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7c) +/** GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN2_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN2_SYNC2_BYPASS_M (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S) +#define GPIO_PIN2_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN2_SYNC2_BYPASS_S 0 +/** GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER_M (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S) +#define GPIO_PIN2_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN2_PAD_DRIVER_S 2 +/** GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN2_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN2_SYNC1_BYPASS_M (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S) +#define GPIO_PIN2_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN2_SYNC1_BYPASS_S 3 +/** GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN2_INT_TYPE 0x00000007U +#define GPIO_PIN2_INT_TYPE_M (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S) +#define GPIO_PIN2_INT_TYPE_V 0x00000007U +#define GPIO_PIN2_INT_TYPE_S 7 +/** GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE_M (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S) +#define GPIO_PIN2_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN2_WAKEUP_ENABLE_S 10 +/** GPIO_PIN2_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN2_CONFIG 0x00000003U +#define GPIO_PIN2_CONFIG_M (GPIO_PIN2_CONFIG_V << GPIO_PIN2_CONFIG_S) +#define GPIO_PIN2_CONFIG_V 0x00000003U +#define GPIO_PIN2_CONFIG_S 11 +/** GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN2_INT_ENA 0x0000001FU +#define GPIO_PIN2_INT_ENA_M (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S) +#define GPIO_PIN2_INT_ENA_V 0x0000001FU +#define GPIO_PIN2_INT_ENA_S 13 + +/** GPIO_PIN3_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80) +/** GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN3_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN3_SYNC2_BYPASS_M (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S) +#define GPIO_PIN3_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN3_SYNC2_BYPASS_S 0 +/** GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER_M (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S) +#define GPIO_PIN3_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN3_PAD_DRIVER_S 2 +/** GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN3_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN3_SYNC1_BYPASS_M (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S) +#define GPIO_PIN3_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN3_SYNC1_BYPASS_S 3 +/** GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN3_INT_TYPE 0x00000007U +#define GPIO_PIN3_INT_TYPE_M (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S) +#define GPIO_PIN3_INT_TYPE_V 0x00000007U +#define GPIO_PIN3_INT_TYPE_S 7 +/** GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE_M (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S) +#define GPIO_PIN3_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN3_WAKEUP_ENABLE_S 10 +/** GPIO_PIN3_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN3_CONFIG 0x00000003U +#define GPIO_PIN3_CONFIG_M (GPIO_PIN3_CONFIG_V << GPIO_PIN3_CONFIG_S) +#define GPIO_PIN3_CONFIG_V 0x00000003U +#define GPIO_PIN3_CONFIG_S 11 +/** GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN3_INT_ENA 0x0000001FU +#define GPIO_PIN3_INT_ENA_M (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S) +#define GPIO_PIN3_INT_ENA_V 0x0000001FU +#define GPIO_PIN3_INT_ENA_S 13 + +/** GPIO_PIN4_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84) +/** GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN4_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN4_SYNC2_BYPASS_M (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S) +#define GPIO_PIN4_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN4_SYNC2_BYPASS_S 0 +/** GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER_M (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S) +#define GPIO_PIN4_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN4_PAD_DRIVER_S 2 +/** GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN4_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN4_SYNC1_BYPASS_M (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S) +#define GPIO_PIN4_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN4_SYNC1_BYPASS_S 3 +/** GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN4_INT_TYPE 0x00000007U +#define GPIO_PIN4_INT_TYPE_M (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S) +#define GPIO_PIN4_INT_TYPE_V 0x00000007U +#define GPIO_PIN4_INT_TYPE_S 7 +/** GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE_M (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S) +#define GPIO_PIN4_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN4_WAKEUP_ENABLE_S 10 +/** GPIO_PIN4_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN4_CONFIG 0x00000003U +#define GPIO_PIN4_CONFIG_M (GPIO_PIN4_CONFIG_V << GPIO_PIN4_CONFIG_S) +#define GPIO_PIN4_CONFIG_V 0x00000003U +#define GPIO_PIN4_CONFIG_S 11 +/** GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN4_INT_ENA 0x0000001FU +#define GPIO_PIN4_INT_ENA_M (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S) +#define GPIO_PIN4_INT_ENA_V 0x0000001FU +#define GPIO_PIN4_INT_ENA_S 13 + +/** GPIO_PIN5_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88) +/** GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN5_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN5_SYNC2_BYPASS_M (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S) +#define GPIO_PIN5_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN5_SYNC2_BYPASS_S 0 +/** GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER_M (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S) +#define GPIO_PIN5_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN5_PAD_DRIVER_S 2 +/** GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN5_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN5_SYNC1_BYPASS_M (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S) +#define GPIO_PIN5_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN5_SYNC1_BYPASS_S 3 +/** GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN5_INT_TYPE 0x00000007U +#define GPIO_PIN5_INT_TYPE_M (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S) +#define GPIO_PIN5_INT_TYPE_V 0x00000007U +#define GPIO_PIN5_INT_TYPE_S 7 +/** GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE_M (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S) +#define GPIO_PIN5_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN5_WAKEUP_ENABLE_S 10 +/** GPIO_PIN5_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN5_CONFIG 0x00000003U +#define GPIO_PIN5_CONFIG_M (GPIO_PIN5_CONFIG_V << GPIO_PIN5_CONFIG_S) +#define GPIO_PIN5_CONFIG_V 0x00000003U +#define GPIO_PIN5_CONFIG_S 11 +/** GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN5_INT_ENA 0x0000001FU +#define GPIO_PIN5_INT_ENA_M (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S) +#define GPIO_PIN5_INT_ENA_V 0x0000001FU +#define GPIO_PIN5_INT_ENA_S 13 + +/** GPIO_PIN6_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8c) +/** GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN6_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN6_SYNC2_BYPASS_M (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S) +#define GPIO_PIN6_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN6_SYNC2_BYPASS_S 0 +/** GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER_M (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S) +#define GPIO_PIN6_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN6_PAD_DRIVER_S 2 +/** GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN6_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN6_SYNC1_BYPASS_M (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S) +#define GPIO_PIN6_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN6_SYNC1_BYPASS_S 3 +/** GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN6_INT_TYPE 0x00000007U +#define GPIO_PIN6_INT_TYPE_M (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S) +#define GPIO_PIN6_INT_TYPE_V 0x00000007U +#define GPIO_PIN6_INT_TYPE_S 7 +/** GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE_M (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S) +#define GPIO_PIN6_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN6_WAKEUP_ENABLE_S 10 +/** GPIO_PIN6_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN6_CONFIG 0x00000003U +#define GPIO_PIN6_CONFIG_M (GPIO_PIN6_CONFIG_V << GPIO_PIN6_CONFIG_S) +#define GPIO_PIN6_CONFIG_V 0x00000003U +#define GPIO_PIN6_CONFIG_S 11 +/** GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN6_INT_ENA 0x0000001FU +#define GPIO_PIN6_INT_ENA_M (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S) +#define GPIO_PIN6_INT_ENA_V 0x0000001FU +#define GPIO_PIN6_INT_ENA_S 13 + +/** GPIO_PIN7_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90) +/** GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN7_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN7_SYNC2_BYPASS_M (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S) +#define GPIO_PIN7_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN7_SYNC2_BYPASS_S 0 +/** GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER_M (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S) +#define GPIO_PIN7_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN7_PAD_DRIVER_S 2 +/** GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN7_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN7_SYNC1_BYPASS_M (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S) +#define GPIO_PIN7_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN7_SYNC1_BYPASS_S 3 +/** GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN7_INT_TYPE 0x00000007U +#define GPIO_PIN7_INT_TYPE_M (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S) +#define GPIO_PIN7_INT_TYPE_V 0x00000007U +#define GPIO_PIN7_INT_TYPE_S 7 +/** GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE_M (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S) +#define GPIO_PIN7_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN7_WAKEUP_ENABLE_S 10 +/** GPIO_PIN7_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN7_CONFIG 0x00000003U +#define GPIO_PIN7_CONFIG_M (GPIO_PIN7_CONFIG_V << GPIO_PIN7_CONFIG_S) +#define GPIO_PIN7_CONFIG_V 0x00000003U +#define GPIO_PIN7_CONFIG_S 11 +/** GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN7_INT_ENA 0x0000001FU +#define GPIO_PIN7_INT_ENA_M (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S) +#define GPIO_PIN7_INT_ENA_V 0x0000001FU +#define GPIO_PIN7_INT_ENA_S 13 + +/** GPIO_PIN8_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94) +/** GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN8_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN8_SYNC2_BYPASS_M (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S) +#define GPIO_PIN8_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN8_SYNC2_BYPASS_S 0 +/** GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER_M (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S) +#define GPIO_PIN8_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN8_PAD_DRIVER_S 2 +/** GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN8_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN8_SYNC1_BYPASS_M (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S) +#define GPIO_PIN8_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN8_SYNC1_BYPASS_S 3 +/** GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN8_INT_TYPE 0x00000007U +#define GPIO_PIN8_INT_TYPE_M (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S) +#define GPIO_PIN8_INT_TYPE_V 0x00000007U +#define GPIO_PIN8_INT_TYPE_S 7 +/** GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE_M (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S) +#define GPIO_PIN8_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN8_WAKEUP_ENABLE_S 10 +/** GPIO_PIN8_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN8_CONFIG 0x00000003U +#define GPIO_PIN8_CONFIG_M (GPIO_PIN8_CONFIG_V << GPIO_PIN8_CONFIG_S) +#define GPIO_PIN8_CONFIG_V 0x00000003U +#define GPIO_PIN8_CONFIG_S 11 +/** GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN8_INT_ENA 0x0000001FU +#define GPIO_PIN8_INT_ENA_M (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S) +#define GPIO_PIN8_INT_ENA_V 0x0000001FU +#define GPIO_PIN8_INT_ENA_S 13 + +/** GPIO_PIN9_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98) +/** GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN9_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN9_SYNC2_BYPASS_M (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S) +#define GPIO_PIN9_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN9_SYNC2_BYPASS_S 0 +/** GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER_M (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S) +#define GPIO_PIN9_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN9_PAD_DRIVER_S 2 +/** GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN9_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN9_SYNC1_BYPASS_M (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S) +#define GPIO_PIN9_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN9_SYNC1_BYPASS_S 3 +/** GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN9_INT_TYPE 0x00000007U +#define GPIO_PIN9_INT_TYPE_M (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S) +#define GPIO_PIN9_INT_TYPE_V 0x00000007U +#define GPIO_PIN9_INT_TYPE_S 7 +/** GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE_M (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S) +#define GPIO_PIN9_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN9_WAKEUP_ENABLE_S 10 +/** GPIO_PIN9_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN9_CONFIG 0x00000003U +#define GPIO_PIN9_CONFIG_M (GPIO_PIN9_CONFIG_V << GPIO_PIN9_CONFIG_S) +#define GPIO_PIN9_CONFIG_V 0x00000003U +#define GPIO_PIN9_CONFIG_S 11 +/** GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN9_INT_ENA 0x0000001FU +#define GPIO_PIN9_INT_ENA_M (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S) +#define GPIO_PIN9_INT_ENA_V 0x0000001FU +#define GPIO_PIN9_INT_ENA_S 13 + +/** GPIO_PIN10_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9c) +/** GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN10_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN10_SYNC2_BYPASS_M (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S) +#define GPIO_PIN10_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN10_SYNC2_BYPASS_S 0 +/** GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER_M (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S) +#define GPIO_PIN10_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN10_PAD_DRIVER_S 2 +/** GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN10_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN10_SYNC1_BYPASS_M (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S) +#define GPIO_PIN10_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN10_SYNC1_BYPASS_S 3 +/** GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN10_INT_TYPE 0x00000007U +#define GPIO_PIN10_INT_TYPE_M (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S) +#define GPIO_PIN10_INT_TYPE_V 0x00000007U +#define GPIO_PIN10_INT_TYPE_S 7 +/** GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE_M (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S) +#define GPIO_PIN10_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN10_WAKEUP_ENABLE_S 10 +/** GPIO_PIN10_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN10_CONFIG 0x00000003U +#define GPIO_PIN10_CONFIG_M (GPIO_PIN10_CONFIG_V << GPIO_PIN10_CONFIG_S) +#define GPIO_PIN10_CONFIG_V 0x00000003U +#define GPIO_PIN10_CONFIG_S 11 +/** GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN10_INT_ENA 0x0000001FU +#define GPIO_PIN10_INT_ENA_M (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S) +#define GPIO_PIN10_INT_ENA_V 0x0000001FU +#define GPIO_PIN10_INT_ENA_S 13 + +/** GPIO_PIN11_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xa0) +/** GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN11_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN11_SYNC2_BYPASS_M (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S) +#define GPIO_PIN11_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN11_SYNC2_BYPASS_S 0 +/** GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER_M (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S) +#define GPIO_PIN11_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN11_PAD_DRIVER_S 2 +/** GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN11_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN11_SYNC1_BYPASS_M (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S) +#define GPIO_PIN11_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN11_SYNC1_BYPASS_S 3 +/** GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN11_INT_TYPE 0x00000007U +#define GPIO_PIN11_INT_TYPE_M (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S) +#define GPIO_PIN11_INT_TYPE_V 0x00000007U +#define GPIO_PIN11_INT_TYPE_S 7 +/** GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE_M (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S) +#define GPIO_PIN11_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN11_WAKEUP_ENABLE_S 10 +/** GPIO_PIN11_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN11_CONFIG 0x00000003U +#define GPIO_PIN11_CONFIG_M (GPIO_PIN11_CONFIG_V << GPIO_PIN11_CONFIG_S) +#define GPIO_PIN11_CONFIG_V 0x00000003U +#define GPIO_PIN11_CONFIG_S 11 +/** GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN11_INT_ENA 0x0000001FU +#define GPIO_PIN11_INT_ENA_M (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S) +#define GPIO_PIN11_INT_ENA_V 0x0000001FU +#define GPIO_PIN11_INT_ENA_S 13 + +/** GPIO_PIN12_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xa4) +/** GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN12_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN12_SYNC2_BYPASS_M (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S) +#define GPIO_PIN12_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN12_SYNC2_BYPASS_S 0 +/** GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER_M (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S) +#define GPIO_PIN12_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN12_PAD_DRIVER_S 2 +/** GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN12_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN12_SYNC1_BYPASS_M (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S) +#define GPIO_PIN12_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN12_SYNC1_BYPASS_S 3 +/** GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN12_INT_TYPE 0x00000007U +#define GPIO_PIN12_INT_TYPE_M (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S) +#define GPIO_PIN12_INT_TYPE_V 0x00000007U +#define GPIO_PIN12_INT_TYPE_S 7 +/** GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE_M (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S) +#define GPIO_PIN12_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN12_WAKEUP_ENABLE_S 10 +/** GPIO_PIN12_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN12_CONFIG 0x00000003U +#define GPIO_PIN12_CONFIG_M (GPIO_PIN12_CONFIG_V << GPIO_PIN12_CONFIG_S) +#define GPIO_PIN12_CONFIG_V 0x00000003U +#define GPIO_PIN12_CONFIG_S 11 +/** GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN12_INT_ENA 0x0000001FU +#define GPIO_PIN12_INT_ENA_M (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S) +#define GPIO_PIN12_INT_ENA_V 0x0000001FU +#define GPIO_PIN12_INT_ENA_S 13 + +/** GPIO_PIN13_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xa8) +/** GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN13_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN13_SYNC2_BYPASS_M (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S) +#define GPIO_PIN13_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN13_SYNC2_BYPASS_S 0 +/** GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER_M (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S) +#define GPIO_PIN13_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN13_PAD_DRIVER_S 2 +/** GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN13_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN13_SYNC1_BYPASS_M (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S) +#define GPIO_PIN13_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN13_SYNC1_BYPASS_S 3 +/** GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN13_INT_TYPE 0x00000007U +#define GPIO_PIN13_INT_TYPE_M (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S) +#define GPIO_PIN13_INT_TYPE_V 0x00000007U +#define GPIO_PIN13_INT_TYPE_S 7 +/** GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE_M (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S) +#define GPIO_PIN13_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN13_WAKEUP_ENABLE_S 10 +/** GPIO_PIN13_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN13_CONFIG 0x00000003U +#define GPIO_PIN13_CONFIG_M (GPIO_PIN13_CONFIG_V << GPIO_PIN13_CONFIG_S) +#define GPIO_PIN13_CONFIG_V 0x00000003U +#define GPIO_PIN13_CONFIG_S 11 +/** GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN13_INT_ENA 0x0000001FU +#define GPIO_PIN13_INT_ENA_M (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S) +#define GPIO_PIN13_INT_ENA_V 0x0000001FU +#define GPIO_PIN13_INT_ENA_S 13 + +/** GPIO_PIN14_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xac) +/** GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN14_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN14_SYNC2_BYPASS_M (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S) +#define GPIO_PIN14_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN14_SYNC2_BYPASS_S 0 +/** GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER_M (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S) +#define GPIO_PIN14_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN14_PAD_DRIVER_S 2 +/** GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN14_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN14_SYNC1_BYPASS_M (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S) +#define GPIO_PIN14_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN14_SYNC1_BYPASS_S 3 +/** GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN14_INT_TYPE 0x00000007U +#define GPIO_PIN14_INT_TYPE_M (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S) +#define GPIO_PIN14_INT_TYPE_V 0x00000007U +#define GPIO_PIN14_INT_TYPE_S 7 +/** GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE_M (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S) +#define GPIO_PIN14_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN14_WAKEUP_ENABLE_S 10 +/** GPIO_PIN14_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN14_CONFIG 0x00000003U +#define GPIO_PIN14_CONFIG_M (GPIO_PIN14_CONFIG_V << GPIO_PIN14_CONFIG_S) +#define GPIO_PIN14_CONFIG_V 0x00000003U +#define GPIO_PIN14_CONFIG_S 11 +/** GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN14_INT_ENA 0x0000001FU +#define GPIO_PIN14_INT_ENA_M (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S) +#define GPIO_PIN14_INT_ENA_V 0x0000001FU +#define GPIO_PIN14_INT_ENA_S 13 + +/** GPIO_PIN15_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xb0) +/** GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN15_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN15_SYNC2_BYPASS_M (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S) +#define GPIO_PIN15_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN15_SYNC2_BYPASS_S 0 +/** GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER_M (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S) +#define GPIO_PIN15_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN15_PAD_DRIVER_S 2 +/** GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN15_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN15_SYNC1_BYPASS_M (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S) +#define GPIO_PIN15_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN15_SYNC1_BYPASS_S 3 +/** GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN15_INT_TYPE 0x00000007U +#define GPIO_PIN15_INT_TYPE_M (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S) +#define GPIO_PIN15_INT_TYPE_V 0x00000007U +#define GPIO_PIN15_INT_TYPE_S 7 +/** GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE_M (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S) +#define GPIO_PIN15_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN15_WAKEUP_ENABLE_S 10 +/** GPIO_PIN15_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN15_CONFIG 0x00000003U +#define GPIO_PIN15_CONFIG_M (GPIO_PIN15_CONFIG_V << GPIO_PIN15_CONFIG_S) +#define GPIO_PIN15_CONFIG_V 0x00000003U +#define GPIO_PIN15_CONFIG_S 11 +/** GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN15_INT_ENA 0x0000001FU +#define GPIO_PIN15_INT_ENA_M (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S) +#define GPIO_PIN15_INT_ENA_V 0x0000001FU +#define GPIO_PIN15_INT_ENA_S 13 + +/** GPIO_PIN16_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xb4) +/** GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN16_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN16_SYNC2_BYPASS_M (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S) +#define GPIO_PIN16_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN16_SYNC2_BYPASS_S 0 +/** GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER_M (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S) +#define GPIO_PIN16_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN16_PAD_DRIVER_S 2 +/** GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN16_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN16_SYNC1_BYPASS_M (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S) +#define GPIO_PIN16_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN16_SYNC1_BYPASS_S 3 +/** GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN16_INT_TYPE 0x00000007U +#define GPIO_PIN16_INT_TYPE_M (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S) +#define GPIO_PIN16_INT_TYPE_V 0x00000007U +#define GPIO_PIN16_INT_TYPE_S 7 +/** GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE_M (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S) +#define GPIO_PIN16_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN16_WAKEUP_ENABLE_S 10 +/** GPIO_PIN16_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN16_CONFIG 0x00000003U +#define GPIO_PIN16_CONFIG_M (GPIO_PIN16_CONFIG_V << GPIO_PIN16_CONFIG_S) +#define GPIO_PIN16_CONFIG_V 0x00000003U +#define GPIO_PIN16_CONFIG_S 11 +/** GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN16_INT_ENA 0x0000001FU +#define GPIO_PIN16_INT_ENA_M (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S) +#define GPIO_PIN16_INT_ENA_V 0x0000001FU +#define GPIO_PIN16_INT_ENA_S 13 + +/** GPIO_PIN17_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xb8) +/** GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN17_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN17_SYNC2_BYPASS_M (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S) +#define GPIO_PIN17_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN17_SYNC2_BYPASS_S 0 +/** GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER_M (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S) +#define GPIO_PIN17_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN17_PAD_DRIVER_S 2 +/** GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN17_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN17_SYNC1_BYPASS_M (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S) +#define GPIO_PIN17_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN17_SYNC1_BYPASS_S 3 +/** GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN17_INT_TYPE 0x00000007U +#define GPIO_PIN17_INT_TYPE_M (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S) +#define GPIO_PIN17_INT_TYPE_V 0x00000007U +#define GPIO_PIN17_INT_TYPE_S 7 +/** GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE_M (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S) +#define GPIO_PIN17_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN17_WAKEUP_ENABLE_S 10 +/** GPIO_PIN17_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN17_CONFIG 0x00000003U +#define GPIO_PIN17_CONFIG_M (GPIO_PIN17_CONFIG_V << GPIO_PIN17_CONFIG_S) +#define GPIO_PIN17_CONFIG_V 0x00000003U +#define GPIO_PIN17_CONFIG_S 11 +/** GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN17_INT_ENA 0x0000001FU +#define GPIO_PIN17_INT_ENA_M (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S) +#define GPIO_PIN17_INT_ENA_V 0x0000001FU +#define GPIO_PIN17_INT_ENA_S 13 + +/** GPIO_PIN18_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xbc) +/** GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN18_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN18_SYNC2_BYPASS_M (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S) +#define GPIO_PIN18_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN18_SYNC2_BYPASS_S 0 +/** GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN18_PAD_DRIVER (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER_M (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S) +#define GPIO_PIN18_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN18_PAD_DRIVER_S 2 +/** GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN18_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN18_SYNC1_BYPASS_M (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S) +#define GPIO_PIN18_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN18_SYNC1_BYPASS_S 3 +/** GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN18_INT_TYPE 0x00000007U +#define GPIO_PIN18_INT_TYPE_M (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S) +#define GPIO_PIN18_INT_TYPE_V 0x00000007U +#define GPIO_PIN18_INT_TYPE_S 7 +/** GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE_M (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S) +#define GPIO_PIN18_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN18_WAKEUP_ENABLE_S 10 +/** GPIO_PIN18_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN18_CONFIG 0x00000003U +#define GPIO_PIN18_CONFIG_M (GPIO_PIN18_CONFIG_V << GPIO_PIN18_CONFIG_S) +#define GPIO_PIN18_CONFIG_V 0x00000003U +#define GPIO_PIN18_CONFIG_S 11 +/** GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN18_INT_ENA 0x0000001FU +#define GPIO_PIN18_INT_ENA_M (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S) +#define GPIO_PIN18_INT_ENA_V 0x0000001FU +#define GPIO_PIN18_INT_ENA_S 13 + +/** GPIO_PIN19_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xc0) +/** GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN19_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN19_SYNC2_BYPASS_M (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S) +#define GPIO_PIN19_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN19_SYNC2_BYPASS_S 0 +/** GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN19_PAD_DRIVER (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER_M (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S) +#define GPIO_PIN19_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN19_PAD_DRIVER_S 2 +/** GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN19_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN19_SYNC1_BYPASS_M (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S) +#define GPIO_PIN19_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN19_SYNC1_BYPASS_S 3 +/** GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN19_INT_TYPE 0x00000007U +#define GPIO_PIN19_INT_TYPE_M (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S) +#define GPIO_PIN19_INT_TYPE_V 0x00000007U +#define GPIO_PIN19_INT_TYPE_S 7 +/** GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE_M (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S) +#define GPIO_PIN19_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN19_WAKEUP_ENABLE_S 10 +/** GPIO_PIN19_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN19_CONFIG 0x00000003U +#define GPIO_PIN19_CONFIG_M (GPIO_PIN19_CONFIG_V << GPIO_PIN19_CONFIG_S) +#define GPIO_PIN19_CONFIG_V 0x00000003U +#define GPIO_PIN19_CONFIG_S 11 +/** GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN19_INT_ENA 0x0000001FU +#define GPIO_PIN19_INT_ENA_M (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S) +#define GPIO_PIN19_INT_ENA_V 0x0000001FU +#define GPIO_PIN19_INT_ENA_S 13 + +/** GPIO_PIN20_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xc4) +/** GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN20_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN20_SYNC2_BYPASS_M (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S) +#define GPIO_PIN20_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN20_SYNC2_BYPASS_S 0 +/** GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN20_PAD_DRIVER (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER_M (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S) +#define GPIO_PIN20_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN20_PAD_DRIVER_S 2 +/** GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN20_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN20_SYNC1_BYPASS_M (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S) +#define GPIO_PIN20_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN20_SYNC1_BYPASS_S 3 +/** GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN20_INT_TYPE 0x00000007U +#define GPIO_PIN20_INT_TYPE_M (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S) +#define GPIO_PIN20_INT_TYPE_V 0x00000007U +#define GPIO_PIN20_INT_TYPE_S 7 +/** GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE_M (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S) +#define GPIO_PIN20_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN20_WAKEUP_ENABLE_S 10 +/** GPIO_PIN20_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN20_CONFIG 0x00000003U +#define GPIO_PIN20_CONFIG_M (GPIO_PIN20_CONFIG_V << GPIO_PIN20_CONFIG_S) +#define GPIO_PIN20_CONFIG_V 0x00000003U +#define GPIO_PIN20_CONFIG_S 11 +/** GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN20_INT_ENA 0x0000001FU +#define GPIO_PIN20_INT_ENA_M (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S) +#define GPIO_PIN20_INT_ENA_V 0x0000001FU +#define GPIO_PIN20_INT_ENA_S 13 + +/** GPIO_PIN21_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xc8) +/** GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN21_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN21_SYNC2_BYPASS_M (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S) +#define GPIO_PIN21_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN21_SYNC2_BYPASS_S 0 +/** GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN21_PAD_DRIVER (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER_M (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S) +#define GPIO_PIN21_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN21_PAD_DRIVER_S 2 +/** GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN21_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN21_SYNC1_BYPASS_M (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S) +#define GPIO_PIN21_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN21_SYNC1_BYPASS_S 3 +/** GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN21_INT_TYPE 0x00000007U +#define GPIO_PIN21_INT_TYPE_M (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S) +#define GPIO_PIN21_INT_TYPE_V 0x00000007U +#define GPIO_PIN21_INT_TYPE_S 7 +/** GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE_M (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S) +#define GPIO_PIN21_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN21_WAKEUP_ENABLE_S 10 +/** GPIO_PIN21_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN21_CONFIG 0x00000003U +#define GPIO_PIN21_CONFIG_M (GPIO_PIN21_CONFIG_V << GPIO_PIN21_CONFIG_S) +#define GPIO_PIN21_CONFIG_V 0x00000003U +#define GPIO_PIN21_CONFIG_S 11 +/** GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN21_INT_ENA 0x0000001FU +#define GPIO_PIN21_INT_ENA_M (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S) +#define GPIO_PIN21_INT_ENA_V 0x0000001FU +#define GPIO_PIN21_INT_ENA_S 13 + +/** GPIO_PIN22_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xcc) +/** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN22_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN22_SYNC2_BYPASS_M (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S) +#define GPIO_PIN22_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN22_SYNC2_BYPASS_S 0 +/** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN22_PAD_DRIVER (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER_M (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S) +#define GPIO_PIN22_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN22_PAD_DRIVER_S 2 +/** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN22_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN22_SYNC1_BYPASS_M (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S) +#define GPIO_PIN22_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN22_SYNC1_BYPASS_S 3 +/** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN22_INT_TYPE 0x00000007U +#define GPIO_PIN22_INT_TYPE_M (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S) +#define GPIO_PIN22_INT_TYPE_V 0x00000007U +#define GPIO_PIN22_INT_TYPE_S 7 +/** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE_M (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S) +#define GPIO_PIN22_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN22_WAKEUP_ENABLE_S 10 +/** GPIO_PIN22_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN22_CONFIG 0x00000003U +#define GPIO_PIN22_CONFIG_M (GPIO_PIN22_CONFIG_V << GPIO_PIN22_CONFIG_S) +#define GPIO_PIN22_CONFIG_V 0x00000003U +#define GPIO_PIN22_CONFIG_S 11 +/** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN22_INT_ENA 0x0000001FU +#define GPIO_PIN22_INT_ENA_M (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S) +#define GPIO_PIN22_INT_ENA_V 0x0000001FU +#define GPIO_PIN22_INT_ENA_S 13 + +/** GPIO_PIN23_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xd0) +/** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN23_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN23_SYNC2_BYPASS_M (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S) +#define GPIO_PIN23_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN23_SYNC2_BYPASS_S 0 +/** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN23_PAD_DRIVER (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER_M (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S) +#define GPIO_PIN23_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN23_PAD_DRIVER_S 2 +/** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN23_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN23_SYNC1_BYPASS_M (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S) +#define GPIO_PIN23_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN23_SYNC1_BYPASS_S 3 +/** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN23_INT_TYPE 0x00000007U +#define GPIO_PIN23_INT_TYPE_M (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S) +#define GPIO_PIN23_INT_TYPE_V 0x00000007U +#define GPIO_PIN23_INT_TYPE_S 7 +/** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE_M (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S) +#define GPIO_PIN23_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN23_WAKEUP_ENABLE_S 10 +/** GPIO_PIN23_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN23_CONFIG 0x00000003U +#define GPIO_PIN23_CONFIG_M (GPIO_PIN23_CONFIG_V << GPIO_PIN23_CONFIG_S) +#define GPIO_PIN23_CONFIG_V 0x00000003U +#define GPIO_PIN23_CONFIG_S 11 +/** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN23_INT_ENA 0x0000001FU +#define GPIO_PIN23_INT_ENA_M (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S) +#define GPIO_PIN23_INT_ENA_V 0x0000001FU +#define GPIO_PIN23_INT_ENA_S 13 + +/** GPIO_PIN24_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xd4) +/** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN24_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN24_SYNC2_BYPASS_M (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S) +#define GPIO_PIN24_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN24_SYNC2_BYPASS_S 0 +/** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN24_PAD_DRIVER (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER_M (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S) +#define GPIO_PIN24_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN24_PAD_DRIVER_S 2 +/** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN24_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN24_SYNC1_BYPASS_M (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S) +#define GPIO_PIN24_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN24_SYNC1_BYPASS_S 3 +/** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN24_INT_TYPE 0x00000007U +#define GPIO_PIN24_INT_TYPE_M (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S) +#define GPIO_PIN24_INT_TYPE_V 0x00000007U +#define GPIO_PIN24_INT_TYPE_S 7 +/** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE_M (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S) +#define GPIO_PIN24_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN24_WAKEUP_ENABLE_S 10 +/** GPIO_PIN24_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN24_CONFIG 0x00000003U +#define GPIO_PIN24_CONFIG_M (GPIO_PIN24_CONFIG_V << GPIO_PIN24_CONFIG_S) +#define GPIO_PIN24_CONFIG_V 0x00000003U +#define GPIO_PIN24_CONFIG_S 11 +/** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN24_INT_ENA 0x0000001FU +#define GPIO_PIN24_INT_ENA_M (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S) +#define GPIO_PIN24_INT_ENA_V 0x0000001FU +#define GPIO_PIN24_INT_ENA_S 13 + +/** GPIO_PIN25_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xd8) +/** GPIO_PIN25_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN25_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN25_SYNC2_BYPASS_M (GPIO_PIN25_SYNC2_BYPASS_V << GPIO_PIN25_SYNC2_BYPASS_S) +#define GPIO_PIN25_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN25_SYNC2_BYPASS_S 0 +/** GPIO_PIN25_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN25_PAD_DRIVER (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_M (GPIO_PIN25_PAD_DRIVER_V << GPIO_PIN25_PAD_DRIVER_S) +#define GPIO_PIN25_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN25_PAD_DRIVER_S 2 +/** GPIO_PIN25_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN25_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN25_SYNC1_BYPASS_M (GPIO_PIN25_SYNC1_BYPASS_V << GPIO_PIN25_SYNC1_BYPASS_S) +#define GPIO_PIN25_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN25_SYNC1_BYPASS_S 3 +/** GPIO_PIN25_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN25_INT_TYPE 0x00000007U +#define GPIO_PIN25_INT_TYPE_M (GPIO_PIN25_INT_TYPE_V << GPIO_PIN25_INT_TYPE_S) +#define GPIO_PIN25_INT_TYPE_V 0x00000007U +#define GPIO_PIN25_INT_TYPE_S 7 +/** GPIO_PIN25_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_M (GPIO_PIN25_WAKEUP_ENABLE_V << GPIO_PIN25_WAKEUP_ENABLE_S) +#define GPIO_PIN25_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN25_WAKEUP_ENABLE_S 10 +/** GPIO_PIN25_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN25_CONFIG 0x00000003U +#define GPIO_PIN25_CONFIG_M (GPIO_PIN25_CONFIG_V << GPIO_PIN25_CONFIG_S) +#define GPIO_PIN25_CONFIG_V 0x00000003U +#define GPIO_PIN25_CONFIG_S 11 +/** GPIO_PIN25_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN25_INT_ENA 0x0000001FU +#define GPIO_PIN25_INT_ENA_M (GPIO_PIN25_INT_ENA_V << GPIO_PIN25_INT_ENA_S) +#define GPIO_PIN25_INT_ENA_V 0x0000001FU +#define GPIO_PIN25_INT_ENA_S 13 + +/** GPIO_PIN26_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0xdc) +/** GPIO_PIN26_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN26_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN26_SYNC2_BYPASS_M (GPIO_PIN26_SYNC2_BYPASS_V << GPIO_PIN26_SYNC2_BYPASS_S) +#define GPIO_PIN26_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN26_SYNC2_BYPASS_S 0 +/** GPIO_PIN26_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN26_PAD_DRIVER (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER_M (GPIO_PIN26_PAD_DRIVER_V << GPIO_PIN26_PAD_DRIVER_S) +#define GPIO_PIN26_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN26_PAD_DRIVER_S 2 +/** GPIO_PIN26_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN26_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN26_SYNC1_BYPASS_M (GPIO_PIN26_SYNC1_BYPASS_V << GPIO_PIN26_SYNC1_BYPASS_S) +#define GPIO_PIN26_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN26_SYNC1_BYPASS_S 3 +/** GPIO_PIN26_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN26_INT_TYPE 0x00000007U +#define GPIO_PIN26_INT_TYPE_M (GPIO_PIN26_INT_TYPE_V << GPIO_PIN26_INT_TYPE_S) +#define GPIO_PIN26_INT_TYPE_V 0x00000007U +#define GPIO_PIN26_INT_TYPE_S 7 +/** GPIO_PIN26_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE_M (GPIO_PIN26_WAKEUP_ENABLE_V << GPIO_PIN26_WAKEUP_ENABLE_S) +#define GPIO_PIN26_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN26_WAKEUP_ENABLE_S 10 +/** GPIO_PIN26_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN26_CONFIG 0x00000003U +#define GPIO_PIN26_CONFIG_M (GPIO_PIN26_CONFIG_V << GPIO_PIN26_CONFIG_S) +#define GPIO_PIN26_CONFIG_V 0x00000003U +#define GPIO_PIN26_CONFIG_S 11 +/** GPIO_PIN26_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN26_INT_ENA 0x0000001FU +#define GPIO_PIN26_INT_ENA_M (GPIO_PIN26_INT_ENA_V << GPIO_PIN26_INT_ENA_S) +#define GPIO_PIN26_INT_ENA_V 0x0000001FU +#define GPIO_PIN26_INT_ENA_S 13 + +/** GPIO_PIN27_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0xe0) +/** GPIO_PIN27_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN27_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN27_SYNC2_BYPASS_M (GPIO_PIN27_SYNC2_BYPASS_V << GPIO_PIN27_SYNC2_BYPASS_S) +#define GPIO_PIN27_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN27_SYNC2_BYPASS_S 0 +/** GPIO_PIN27_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN27_PAD_DRIVER (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER_M (GPIO_PIN27_PAD_DRIVER_V << GPIO_PIN27_PAD_DRIVER_S) +#define GPIO_PIN27_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN27_PAD_DRIVER_S 2 +/** GPIO_PIN27_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN27_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN27_SYNC1_BYPASS_M (GPIO_PIN27_SYNC1_BYPASS_V << GPIO_PIN27_SYNC1_BYPASS_S) +#define GPIO_PIN27_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN27_SYNC1_BYPASS_S 3 +/** GPIO_PIN27_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN27_INT_TYPE 0x00000007U +#define GPIO_PIN27_INT_TYPE_M (GPIO_PIN27_INT_TYPE_V << GPIO_PIN27_INT_TYPE_S) +#define GPIO_PIN27_INT_TYPE_V 0x00000007U +#define GPIO_PIN27_INT_TYPE_S 7 +/** GPIO_PIN27_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE_M (GPIO_PIN27_WAKEUP_ENABLE_V << GPIO_PIN27_WAKEUP_ENABLE_S) +#define GPIO_PIN27_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN27_WAKEUP_ENABLE_S 10 +/** GPIO_PIN27_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN27_CONFIG 0x00000003U +#define GPIO_PIN27_CONFIG_M (GPIO_PIN27_CONFIG_V << GPIO_PIN27_CONFIG_S) +#define GPIO_PIN27_CONFIG_V 0x00000003U +#define GPIO_PIN27_CONFIG_S 11 +/** GPIO_PIN27_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN27_INT_ENA 0x0000001FU +#define GPIO_PIN27_INT_ENA_M (GPIO_PIN27_INT_ENA_V << GPIO_PIN27_INT_ENA_S) +#define GPIO_PIN27_INT_ENA_V 0x0000001FU +#define GPIO_PIN27_INT_ENA_S 13 + +/** GPIO_PIN28_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0xe4) +/** GPIO_PIN28_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN28_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN28_SYNC2_BYPASS_M (GPIO_PIN28_SYNC2_BYPASS_V << GPIO_PIN28_SYNC2_BYPASS_S) +#define GPIO_PIN28_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN28_SYNC2_BYPASS_S 0 +/** GPIO_PIN28_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN28_PAD_DRIVER (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER_M (GPIO_PIN28_PAD_DRIVER_V << GPIO_PIN28_PAD_DRIVER_S) +#define GPIO_PIN28_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN28_PAD_DRIVER_S 2 +/** GPIO_PIN28_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN28_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN28_SYNC1_BYPASS_M (GPIO_PIN28_SYNC1_BYPASS_V << GPIO_PIN28_SYNC1_BYPASS_S) +#define GPIO_PIN28_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN28_SYNC1_BYPASS_S 3 +/** GPIO_PIN28_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN28_INT_TYPE 0x00000007U +#define GPIO_PIN28_INT_TYPE_M (GPIO_PIN28_INT_TYPE_V << GPIO_PIN28_INT_TYPE_S) +#define GPIO_PIN28_INT_TYPE_V 0x00000007U +#define GPIO_PIN28_INT_TYPE_S 7 +/** GPIO_PIN28_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE_M (GPIO_PIN28_WAKEUP_ENABLE_V << GPIO_PIN28_WAKEUP_ENABLE_S) +#define GPIO_PIN28_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN28_WAKEUP_ENABLE_S 10 +/** GPIO_PIN28_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN28_CONFIG 0x00000003U +#define GPIO_PIN28_CONFIG_M (GPIO_PIN28_CONFIG_V << GPIO_PIN28_CONFIG_S) +#define GPIO_PIN28_CONFIG_V 0x00000003U +#define GPIO_PIN28_CONFIG_S 11 +/** GPIO_PIN28_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN28_INT_ENA 0x0000001FU +#define GPIO_PIN28_INT_ENA_M (GPIO_PIN28_INT_ENA_V << GPIO_PIN28_INT_ENA_S) +#define GPIO_PIN28_INT_ENA_V 0x0000001FU +#define GPIO_PIN28_INT_ENA_S 13 + +/** GPIO_PIN29_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0xe8) +/** GPIO_PIN29_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN29_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN29_SYNC2_BYPASS_M (GPIO_PIN29_SYNC2_BYPASS_V << GPIO_PIN29_SYNC2_BYPASS_S) +#define GPIO_PIN29_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN29_SYNC2_BYPASS_S 0 +/** GPIO_PIN29_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN29_PAD_DRIVER (BIT(2)) +#define GPIO_PIN29_PAD_DRIVER_M (GPIO_PIN29_PAD_DRIVER_V << GPIO_PIN29_PAD_DRIVER_S) +#define GPIO_PIN29_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN29_PAD_DRIVER_S 2 +/** GPIO_PIN29_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN29_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN29_SYNC1_BYPASS_M (GPIO_PIN29_SYNC1_BYPASS_V << GPIO_PIN29_SYNC1_BYPASS_S) +#define GPIO_PIN29_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN29_SYNC1_BYPASS_S 3 +/** GPIO_PIN29_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN29_INT_TYPE 0x00000007U +#define GPIO_PIN29_INT_TYPE_M (GPIO_PIN29_INT_TYPE_V << GPIO_PIN29_INT_TYPE_S) +#define GPIO_PIN29_INT_TYPE_V 0x00000007U +#define GPIO_PIN29_INT_TYPE_S 7 +/** GPIO_PIN29_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN29_WAKEUP_ENABLE_M (GPIO_PIN29_WAKEUP_ENABLE_V << GPIO_PIN29_WAKEUP_ENABLE_S) +#define GPIO_PIN29_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN29_WAKEUP_ENABLE_S 10 +/** GPIO_PIN29_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN29_CONFIG 0x00000003U +#define GPIO_PIN29_CONFIG_M (GPIO_PIN29_CONFIG_V << GPIO_PIN29_CONFIG_S) +#define GPIO_PIN29_CONFIG_V 0x00000003U +#define GPIO_PIN29_CONFIG_S 11 +/** GPIO_PIN29_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN29_INT_ENA 0x0000001FU +#define GPIO_PIN29_INT_ENA_M (GPIO_PIN29_INT_ENA_V << GPIO_PIN29_INT_ENA_S) +#define GPIO_PIN29_INT_ENA_V 0x0000001FU +#define GPIO_PIN29_INT_ENA_S 13 + +/** GPIO_PIN30_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0xec) +/** GPIO_PIN30_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN30_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN30_SYNC2_BYPASS_M (GPIO_PIN30_SYNC2_BYPASS_V << GPIO_PIN30_SYNC2_BYPASS_S) +#define GPIO_PIN30_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN30_SYNC2_BYPASS_S 0 +/** GPIO_PIN30_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN30_PAD_DRIVER (BIT(2)) +#define GPIO_PIN30_PAD_DRIVER_M (GPIO_PIN30_PAD_DRIVER_V << GPIO_PIN30_PAD_DRIVER_S) +#define GPIO_PIN30_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN30_PAD_DRIVER_S 2 +/** GPIO_PIN30_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN30_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN30_SYNC1_BYPASS_M (GPIO_PIN30_SYNC1_BYPASS_V << GPIO_PIN30_SYNC1_BYPASS_S) +#define GPIO_PIN30_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN30_SYNC1_BYPASS_S 3 +/** GPIO_PIN30_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN30_INT_TYPE 0x00000007U +#define GPIO_PIN30_INT_TYPE_M (GPIO_PIN30_INT_TYPE_V << GPIO_PIN30_INT_TYPE_S) +#define GPIO_PIN30_INT_TYPE_V 0x00000007U +#define GPIO_PIN30_INT_TYPE_S 7 +/** GPIO_PIN30_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN30_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN30_WAKEUP_ENABLE_M (GPIO_PIN30_WAKEUP_ENABLE_V << GPIO_PIN30_WAKEUP_ENABLE_S) +#define GPIO_PIN30_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN30_WAKEUP_ENABLE_S 10 +/** GPIO_PIN30_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN30_CONFIG 0x00000003U +#define GPIO_PIN30_CONFIG_M (GPIO_PIN30_CONFIG_V << GPIO_PIN30_CONFIG_S) +#define GPIO_PIN30_CONFIG_V 0x00000003U +#define GPIO_PIN30_CONFIG_S 11 +/** GPIO_PIN30_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN30_INT_ENA 0x0000001FU +#define GPIO_PIN30_INT_ENA_M (GPIO_PIN30_INT_ENA_V << GPIO_PIN30_INT_ENA_S) +#define GPIO_PIN30_INT_ENA_V 0x0000001FU +#define GPIO_PIN30_INT_ENA_S 13 + +/** GPIO_PIN31_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0xf0) +/** GPIO_PIN31_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN31_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN31_SYNC2_BYPASS_M (GPIO_PIN31_SYNC2_BYPASS_V << GPIO_PIN31_SYNC2_BYPASS_S) +#define GPIO_PIN31_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN31_SYNC2_BYPASS_S 0 +/** GPIO_PIN31_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN31_PAD_DRIVER (BIT(2)) +#define GPIO_PIN31_PAD_DRIVER_M (GPIO_PIN31_PAD_DRIVER_V << GPIO_PIN31_PAD_DRIVER_S) +#define GPIO_PIN31_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN31_PAD_DRIVER_S 2 +/** GPIO_PIN31_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN31_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN31_SYNC1_BYPASS_M (GPIO_PIN31_SYNC1_BYPASS_V << GPIO_PIN31_SYNC1_BYPASS_S) +#define GPIO_PIN31_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN31_SYNC1_BYPASS_S 3 +/** GPIO_PIN31_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN31_INT_TYPE 0x00000007U +#define GPIO_PIN31_INT_TYPE_M (GPIO_PIN31_INT_TYPE_V << GPIO_PIN31_INT_TYPE_S) +#define GPIO_PIN31_INT_TYPE_V 0x00000007U +#define GPIO_PIN31_INT_TYPE_S 7 +/** GPIO_PIN31_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN31_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN31_WAKEUP_ENABLE_M (GPIO_PIN31_WAKEUP_ENABLE_V << GPIO_PIN31_WAKEUP_ENABLE_S) +#define GPIO_PIN31_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN31_WAKEUP_ENABLE_S 10 +/** GPIO_PIN31_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN31_CONFIG 0x00000003U +#define GPIO_PIN31_CONFIG_M (GPIO_PIN31_CONFIG_V << GPIO_PIN31_CONFIG_S) +#define GPIO_PIN31_CONFIG_V 0x00000003U +#define GPIO_PIN31_CONFIG_S 11 +/** GPIO_PIN31_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN31_INT_ENA 0x0000001FU +#define GPIO_PIN31_INT_ENA_M (GPIO_PIN31_INT_ENA_V << GPIO_PIN31_INT_ENA_S) +#define GPIO_PIN31_INT_ENA_V 0x0000001FU +#define GPIO_PIN31_INT_ENA_S 13 + +/** GPIO_PIN32_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN32_REG (DR_REG_GPIO_BASE + 0xf4) +/** GPIO_PIN32_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN32_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN32_SYNC2_BYPASS_M (GPIO_PIN32_SYNC2_BYPASS_V << GPIO_PIN32_SYNC2_BYPASS_S) +#define GPIO_PIN32_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN32_SYNC2_BYPASS_S 0 +/** GPIO_PIN32_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN32_PAD_DRIVER (BIT(2)) +#define GPIO_PIN32_PAD_DRIVER_M (GPIO_PIN32_PAD_DRIVER_V << GPIO_PIN32_PAD_DRIVER_S) +#define GPIO_PIN32_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN32_PAD_DRIVER_S 2 +/** GPIO_PIN32_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN32_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN32_SYNC1_BYPASS_M (GPIO_PIN32_SYNC1_BYPASS_V << GPIO_PIN32_SYNC1_BYPASS_S) +#define GPIO_PIN32_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN32_SYNC1_BYPASS_S 3 +/** GPIO_PIN32_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN32_INT_TYPE 0x00000007U +#define GPIO_PIN32_INT_TYPE_M (GPIO_PIN32_INT_TYPE_V << GPIO_PIN32_INT_TYPE_S) +#define GPIO_PIN32_INT_TYPE_V 0x00000007U +#define GPIO_PIN32_INT_TYPE_S 7 +/** GPIO_PIN32_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN32_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN32_WAKEUP_ENABLE_M (GPIO_PIN32_WAKEUP_ENABLE_V << GPIO_PIN32_WAKEUP_ENABLE_S) +#define GPIO_PIN32_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN32_WAKEUP_ENABLE_S 10 +/** GPIO_PIN32_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN32_CONFIG 0x00000003U +#define GPIO_PIN32_CONFIG_M (GPIO_PIN32_CONFIG_V << GPIO_PIN32_CONFIG_S) +#define GPIO_PIN32_CONFIG_V 0x00000003U +#define GPIO_PIN32_CONFIG_S 11 +/** GPIO_PIN32_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN32_INT_ENA 0x0000001FU +#define GPIO_PIN32_INT_ENA_M (GPIO_PIN32_INT_ENA_V << GPIO_PIN32_INT_ENA_S) +#define GPIO_PIN32_INT_ENA_V 0x0000001FU +#define GPIO_PIN32_INT_ENA_S 13 + +/** GPIO_PIN33_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN33_REG (DR_REG_GPIO_BASE + 0xf8) +/** GPIO_PIN33_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN33_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN33_SYNC2_BYPASS_M (GPIO_PIN33_SYNC2_BYPASS_V << GPIO_PIN33_SYNC2_BYPASS_S) +#define GPIO_PIN33_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN33_SYNC2_BYPASS_S 0 +/** GPIO_PIN33_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN33_PAD_DRIVER (BIT(2)) +#define GPIO_PIN33_PAD_DRIVER_M (GPIO_PIN33_PAD_DRIVER_V << GPIO_PIN33_PAD_DRIVER_S) +#define GPIO_PIN33_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN33_PAD_DRIVER_S 2 +/** GPIO_PIN33_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN33_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN33_SYNC1_BYPASS_M (GPIO_PIN33_SYNC1_BYPASS_V << GPIO_PIN33_SYNC1_BYPASS_S) +#define GPIO_PIN33_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN33_SYNC1_BYPASS_S 3 +/** GPIO_PIN33_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN33_INT_TYPE 0x00000007U +#define GPIO_PIN33_INT_TYPE_M (GPIO_PIN33_INT_TYPE_V << GPIO_PIN33_INT_TYPE_S) +#define GPIO_PIN33_INT_TYPE_V 0x00000007U +#define GPIO_PIN33_INT_TYPE_S 7 +/** GPIO_PIN33_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN33_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN33_WAKEUP_ENABLE_M (GPIO_PIN33_WAKEUP_ENABLE_V << GPIO_PIN33_WAKEUP_ENABLE_S) +#define GPIO_PIN33_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN33_WAKEUP_ENABLE_S 10 +/** GPIO_PIN33_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN33_CONFIG 0x00000003U +#define GPIO_PIN33_CONFIG_M (GPIO_PIN33_CONFIG_V << GPIO_PIN33_CONFIG_S) +#define GPIO_PIN33_CONFIG_V 0x00000003U +#define GPIO_PIN33_CONFIG_S 11 +/** GPIO_PIN33_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN33_INT_ENA 0x0000001FU +#define GPIO_PIN33_INT_ENA_M (GPIO_PIN33_INT_ENA_V << GPIO_PIN33_INT_ENA_S) +#define GPIO_PIN33_INT_ENA_V 0x0000001FU +#define GPIO_PIN33_INT_ENA_S 13 + +/** GPIO_PIN34_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN34_REG (DR_REG_GPIO_BASE + 0xfc) +/** GPIO_PIN34_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN34_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN34_SYNC2_BYPASS_M (GPIO_PIN34_SYNC2_BYPASS_V << GPIO_PIN34_SYNC2_BYPASS_S) +#define GPIO_PIN34_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN34_SYNC2_BYPASS_S 0 +/** GPIO_PIN34_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN34_PAD_DRIVER (BIT(2)) +#define GPIO_PIN34_PAD_DRIVER_M (GPIO_PIN34_PAD_DRIVER_V << GPIO_PIN34_PAD_DRIVER_S) +#define GPIO_PIN34_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN34_PAD_DRIVER_S 2 +/** GPIO_PIN34_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN34_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN34_SYNC1_BYPASS_M (GPIO_PIN34_SYNC1_BYPASS_V << GPIO_PIN34_SYNC1_BYPASS_S) +#define GPIO_PIN34_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN34_SYNC1_BYPASS_S 3 +/** GPIO_PIN34_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN34_INT_TYPE 0x00000007U +#define GPIO_PIN34_INT_TYPE_M (GPIO_PIN34_INT_TYPE_V << GPIO_PIN34_INT_TYPE_S) +#define GPIO_PIN34_INT_TYPE_V 0x00000007U +#define GPIO_PIN34_INT_TYPE_S 7 +/** GPIO_PIN34_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN34_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN34_WAKEUP_ENABLE_M (GPIO_PIN34_WAKEUP_ENABLE_V << GPIO_PIN34_WAKEUP_ENABLE_S) +#define GPIO_PIN34_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN34_WAKEUP_ENABLE_S 10 +/** GPIO_PIN34_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN34_CONFIG 0x00000003U +#define GPIO_PIN34_CONFIG_M (GPIO_PIN34_CONFIG_V << GPIO_PIN34_CONFIG_S) +#define GPIO_PIN34_CONFIG_V 0x00000003U +#define GPIO_PIN34_CONFIG_S 11 +/** GPIO_PIN34_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN34_INT_ENA 0x0000001FU +#define GPIO_PIN34_INT_ENA_M (GPIO_PIN34_INT_ENA_V << GPIO_PIN34_INT_ENA_S) +#define GPIO_PIN34_INT_ENA_V 0x0000001FU +#define GPIO_PIN34_INT_ENA_S 13 + +/** GPIO_STATUS_NEXT_REG register + * GPIO interrupt source register for GPIO0-31 + */ +#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x14c) +/** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [31:0]; default: 0; + * GPIO interrupt source register for GPIO0-31 + */ +#define GPIO_STATUS_INTERRUPT_NEXT 0xFFFFFFFFU +#define GPIO_STATUS_INTERRUPT_NEXT_M (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S) +#define GPIO_STATUS_INTERRUPT_NEXT_V 0xFFFFFFFFU +#define GPIO_STATUS_INTERRUPT_NEXT_S 0 + +/** GPIO_STATUS_NEXT1_REG register + * GPIO interrupt source register for GPIO32-34 + */ +#define GPIO_STATUS_NEXT1_REG (DR_REG_GPIO_BASE + 0x150) +/** GPIO_STATUS_INTERRUPT_NEXT1 : RO; bitpos: [2:0]; default: 0; + * GPIO interrupt source register for GPIO32-34 + */ +#define GPIO_STATUS_INTERRUPT_NEXT1 0x00000007U +#define GPIO_STATUS_INTERRUPT_NEXT1_M (GPIO_STATUS_INTERRUPT_NEXT1_V << GPIO_STATUS_INTERRUPT_NEXT1_S) +#define GPIO_STATUS_INTERRUPT_NEXT1_V 0x00000007U +#define GPIO_STATUS_INTERRUPT_NEXT1_S 0 + +/** GPIO_FUNC0_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x154) +/** GPIO_FUNC0_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC0_IN_SEL 0x0000003FU +#define GPIO_FUNC0_IN_SEL_M (GPIO_FUNC0_IN_SEL_V << GPIO_FUNC0_IN_SEL_S) +#define GPIO_FUNC0_IN_SEL_V 0x0000003FU +#define GPIO_FUNC0_IN_SEL_S 0 +/** GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC0_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC0_IN_INV_SEL_M (GPIO_FUNC0_IN_INV_SEL_V << GPIO_FUNC0_IN_INV_SEL_S) +#define GPIO_FUNC0_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC0_IN_INV_SEL_S 6 +/** GPIO_SIG0_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG0_IN_SEL (BIT(7)) +#define GPIO_SIG0_IN_SEL_M (GPIO_SIG0_IN_SEL_V << GPIO_SIG0_IN_SEL_S) +#define GPIO_SIG0_IN_SEL_V 0x00000001U +#define GPIO_SIG0_IN_SEL_S 7 + +/** GPIO_FUNC6_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16c) +/** GPIO_FUNC6_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC6_IN_SEL 0x0000003FU +#define GPIO_FUNC6_IN_SEL_M (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S) +#define GPIO_FUNC6_IN_SEL_V 0x0000003FU +#define GPIO_FUNC6_IN_SEL_S 0 +/** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC6_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC6_IN_INV_SEL_M (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S) +#define GPIO_FUNC6_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC6_IN_INV_SEL_S 6 +/** GPIO_SIG6_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG6_IN_SEL (BIT(7)) +#define GPIO_SIG6_IN_SEL_M (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S) +#define GPIO_SIG6_IN_SEL_V 0x00000001U +#define GPIO_SIG6_IN_SEL_S 7 + +/** GPIO_FUNC7_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170) +/** GPIO_FUNC7_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC7_IN_SEL 0x0000003FU +#define GPIO_FUNC7_IN_SEL_M (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S) +#define GPIO_FUNC7_IN_SEL_V 0x0000003FU +#define GPIO_FUNC7_IN_SEL_S 0 +/** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC7_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC7_IN_INV_SEL_M (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S) +#define GPIO_FUNC7_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC7_IN_INV_SEL_S 6 +/** GPIO_SIG7_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG7_IN_SEL (BIT(7)) +#define GPIO_SIG7_IN_SEL_M (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S) +#define GPIO_SIG7_IN_SEL_V 0x00000001U +#define GPIO_SIG7_IN_SEL_S 7 + +/** GPIO_FUNC8_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174) +/** GPIO_FUNC8_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC8_IN_SEL 0x0000003FU +#define GPIO_FUNC8_IN_SEL_M (GPIO_FUNC8_IN_SEL_V << GPIO_FUNC8_IN_SEL_S) +#define GPIO_FUNC8_IN_SEL_V 0x0000003FU +#define GPIO_FUNC8_IN_SEL_S 0 +/** GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC8_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC8_IN_INV_SEL_M (GPIO_FUNC8_IN_INV_SEL_V << GPIO_FUNC8_IN_INV_SEL_S) +#define GPIO_FUNC8_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC8_IN_INV_SEL_S 6 +/** GPIO_SIG8_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG8_IN_SEL (BIT(7)) +#define GPIO_SIG8_IN_SEL_M (GPIO_SIG8_IN_SEL_V << GPIO_SIG8_IN_SEL_S) +#define GPIO_SIG8_IN_SEL_V 0x00000001U +#define GPIO_SIG8_IN_SEL_S 7 + +/** GPIO_FUNC9_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178) +/** GPIO_FUNC9_IN_SEL : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC9_IN_SEL 0x0000003FU +#define GPIO_FUNC9_IN_SEL_M (GPIO_FUNC9_IN_SEL_V << GPIO_FUNC9_IN_SEL_S) +#define GPIO_FUNC9_IN_SEL_V 0x0000003FU +#define GPIO_FUNC9_IN_SEL_S 0 +/** GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC9_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC9_IN_INV_SEL_M (GPIO_FUNC9_IN_INV_SEL_V << GPIO_FUNC9_IN_INV_SEL_S) +#define GPIO_FUNC9_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC9_IN_INV_SEL_S 6 +/** GPIO_SIG9_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG9_IN_SEL (BIT(7)) +#define GPIO_SIG9_IN_SEL_M (GPIO_SIG9_IN_SEL_V << GPIO_SIG9_IN_SEL_S) +#define GPIO_SIG9_IN_SEL_V 0x00000001U +#define GPIO_SIG9_IN_SEL_S 7 + +/** GPIO_FUNC10_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17c) +/** GPIO_FUNC10_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC10_IN_SEL 0x0000003FU +#define GPIO_FUNC10_IN_SEL_M (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S) +#define GPIO_FUNC10_IN_SEL_V 0x0000003FU +#define GPIO_FUNC10_IN_SEL_S 0 +/** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC10_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC10_IN_INV_SEL_M (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S) +#define GPIO_FUNC10_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC10_IN_INV_SEL_S 6 +/** GPIO_SIG10_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG10_IN_SEL (BIT(7)) +#define GPIO_SIG10_IN_SEL_M (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S) +#define GPIO_SIG10_IN_SEL_V 0x00000001U +#define GPIO_SIG10_IN_SEL_S 7 + +/** GPIO_FUNC11_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180) +/** GPIO_FUNC11_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC11_IN_SEL 0x0000003FU +#define GPIO_FUNC11_IN_SEL_M (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S) +#define GPIO_FUNC11_IN_SEL_V 0x0000003FU +#define GPIO_FUNC11_IN_SEL_S 0 +/** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC11_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC11_IN_INV_SEL_M (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S) +#define GPIO_FUNC11_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC11_IN_INV_SEL_S 6 +/** GPIO_SIG11_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG11_IN_SEL (BIT(7)) +#define GPIO_SIG11_IN_SEL_M (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S) +#define GPIO_SIG11_IN_SEL_V 0x00000001U +#define GPIO_SIG11_IN_SEL_S 7 + +/** GPIO_FUNC12_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184) +/** GPIO_FUNC12_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC12_IN_SEL 0x0000003FU +#define GPIO_FUNC12_IN_SEL_M (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S) +#define GPIO_FUNC12_IN_SEL_V 0x0000003FU +#define GPIO_FUNC12_IN_SEL_S 0 +/** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC12_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC12_IN_INV_SEL_M (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S) +#define GPIO_FUNC12_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC12_IN_INV_SEL_S 6 +/** GPIO_SIG12_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG12_IN_SEL (BIT(7)) +#define GPIO_SIG12_IN_SEL_M (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S) +#define GPIO_SIG12_IN_SEL_V 0x00000001U +#define GPIO_SIG12_IN_SEL_S 7 + +/** GPIO_FUNC13_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188) +/** GPIO_FUNC13_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC13_IN_SEL 0x0000003FU +#define GPIO_FUNC13_IN_SEL_M (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S) +#define GPIO_FUNC13_IN_SEL_V 0x0000003FU +#define GPIO_FUNC13_IN_SEL_S 0 +/** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC13_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC13_IN_INV_SEL_M (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S) +#define GPIO_FUNC13_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC13_IN_INV_SEL_S 6 +/** GPIO_SIG13_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG13_IN_SEL (BIT(7)) +#define GPIO_SIG13_IN_SEL_M (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S) +#define GPIO_SIG13_IN_SEL_V 0x00000001U +#define GPIO_SIG13_IN_SEL_S 7 + +/** GPIO_FUNC14_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18c) +/** GPIO_FUNC14_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC14_IN_SEL 0x0000003FU +#define GPIO_FUNC14_IN_SEL_M (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S) +#define GPIO_FUNC14_IN_SEL_V 0x0000003FU +#define GPIO_FUNC14_IN_SEL_S 0 +/** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC14_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC14_IN_INV_SEL_M (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S) +#define GPIO_FUNC14_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC14_IN_INV_SEL_S 6 +/** GPIO_SIG14_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG14_IN_SEL (BIT(7)) +#define GPIO_SIG14_IN_SEL_M (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S) +#define GPIO_SIG14_IN_SEL_V 0x00000001U +#define GPIO_SIG14_IN_SEL_S 7 + +/** GPIO_FUNC15_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190) +/** GPIO_FUNC15_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC15_IN_SEL 0x0000003FU +#define GPIO_FUNC15_IN_SEL_M (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S) +#define GPIO_FUNC15_IN_SEL_V 0x0000003FU +#define GPIO_FUNC15_IN_SEL_S 0 +/** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC15_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC15_IN_INV_SEL_M (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S) +#define GPIO_FUNC15_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC15_IN_INV_SEL_S 6 +/** GPIO_SIG15_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG15_IN_SEL (BIT(7)) +#define GPIO_SIG15_IN_SEL_M (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S) +#define GPIO_SIG15_IN_SEL_V 0x00000001U +#define GPIO_SIG15_IN_SEL_S 7 + +/** GPIO_FUNC16_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194) +/** GPIO_FUNC16_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC16_IN_SEL 0x0000003FU +#define GPIO_FUNC16_IN_SEL_M (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S) +#define GPIO_FUNC16_IN_SEL_V 0x0000003FU +#define GPIO_FUNC16_IN_SEL_S 0 +/** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC16_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC16_IN_INV_SEL_M (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S) +#define GPIO_FUNC16_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC16_IN_INV_SEL_S 6 +/** GPIO_SIG16_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG16_IN_SEL (BIT(7)) +#define GPIO_SIG16_IN_SEL_M (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S) +#define GPIO_SIG16_IN_SEL_V 0x00000001U +#define GPIO_SIG16_IN_SEL_S 7 + +/** GPIO_FUNC17_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198) +/** GPIO_FUNC17_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC17_IN_SEL 0x0000003FU +#define GPIO_FUNC17_IN_SEL_M (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S) +#define GPIO_FUNC17_IN_SEL_V 0x0000003FU +#define GPIO_FUNC17_IN_SEL_S 0 +/** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC17_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC17_IN_INV_SEL_M (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S) +#define GPIO_FUNC17_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC17_IN_INV_SEL_S 6 +/** GPIO_SIG17_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG17_IN_SEL (BIT(7)) +#define GPIO_SIG17_IN_SEL_M (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S) +#define GPIO_SIG17_IN_SEL_V 0x00000001U +#define GPIO_SIG17_IN_SEL_S 7 + +/** GPIO_FUNC19_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a0) +/** GPIO_FUNC19_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC19_IN_SEL 0x0000003FU +#define GPIO_FUNC19_IN_SEL_M (GPIO_FUNC19_IN_SEL_V << GPIO_FUNC19_IN_SEL_S) +#define GPIO_FUNC19_IN_SEL_V 0x0000003FU +#define GPIO_FUNC19_IN_SEL_S 0 +/** GPIO_FUNC19_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC19_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC19_IN_INV_SEL_M (GPIO_FUNC19_IN_INV_SEL_V << GPIO_FUNC19_IN_INV_SEL_S) +#define GPIO_FUNC19_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC19_IN_INV_SEL_S 6 +/** GPIO_SIG19_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG19_IN_SEL (BIT(7)) +#define GPIO_SIG19_IN_SEL_M (GPIO_SIG19_IN_SEL_V << GPIO_SIG19_IN_SEL_S) +#define GPIO_SIG19_IN_SEL_V 0x00000001U +#define GPIO_SIG19_IN_SEL_S 7 + +/** GPIO_FUNC28_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c4) +/** GPIO_FUNC28_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC28_IN_SEL 0x0000003FU +#define GPIO_FUNC28_IN_SEL_M (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S) +#define GPIO_FUNC28_IN_SEL_V 0x0000003FU +#define GPIO_FUNC28_IN_SEL_S 0 +/** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC28_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC28_IN_INV_SEL_M (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S) +#define GPIO_FUNC28_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_IN_INV_SEL_S 6 +/** GPIO_SIG28_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG28_IN_SEL (BIT(7)) +#define GPIO_SIG28_IN_SEL_M (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S) +#define GPIO_SIG28_IN_SEL_V 0x00000001U +#define GPIO_SIG28_IN_SEL_S 7 + +/** GPIO_FUNC29_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c8) +/** GPIO_FUNC29_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC29_IN_SEL 0x0000003FU +#define GPIO_FUNC29_IN_SEL_M (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S) +#define GPIO_FUNC29_IN_SEL_V 0x0000003FU +#define GPIO_FUNC29_IN_SEL_S 0 +/** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC29_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC29_IN_INV_SEL_M (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S) +#define GPIO_FUNC29_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC29_IN_INV_SEL_S 6 +/** GPIO_SIG29_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG29_IN_SEL (BIT(7)) +#define GPIO_SIG29_IN_SEL_M (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S) +#define GPIO_SIG29_IN_SEL_V 0x00000001U +#define GPIO_SIG29_IN_SEL_S 7 + +/** GPIO_FUNC30_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1cc) +/** GPIO_FUNC30_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC30_IN_SEL 0x0000003FU +#define GPIO_FUNC30_IN_SEL_M (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S) +#define GPIO_FUNC30_IN_SEL_V 0x0000003FU +#define GPIO_FUNC30_IN_SEL_S 0 +/** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC30_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC30_IN_INV_SEL_M (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S) +#define GPIO_FUNC30_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC30_IN_INV_SEL_S 6 +/** GPIO_SIG30_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG30_IN_SEL (BIT(7)) +#define GPIO_SIG30_IN_SEL_M (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S) +#define GPIO_SIG30_IN_SEL_V 0x00000001U +#define GPIO_SIG30_IN_SEL_S 7 + +/** GPIO_FUNC31_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d0) +/** GPIO_FUNC31_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC31_IN_SEL 0x0000003FU +#define GPIO_FUNC31_IN_SEL_M (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S) +#define GPIO_FUNC31_IN_SEL_V 0x0000003FU +#define GPIO_FUNC31_IN_SEL_S 0 +/** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC31_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC31_IN_INV_SEL_M (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S) +#define GPIO_FUNC31_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC31_IN_INV_SEL_S 6 +/** GPIO_SIG31_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG31_IN_SEL (BIT(7)) +#define GPIO_SIG31_IN_SEL_M (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S) +#define GPIO_SIG31_IN_SEL_V 0x00000001U +#define GPIO_SIG31_IN_SEL_S 7 + +/** GPIO_FUNC32_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d4) +/** GPIO_FUNC32_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC32_IN_SEL 0x0000003FU +#define GPIO_FUNC32_IN_SEL_M (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S) +#define GPIO_FUNC32_IN_SEL_V 0x0000003FU +#define GPIO_FUNC32_IN_SEL_S 0 +/** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC32_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC32_IN_INV_SEL_M (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S) +#define GPIO_FUNC32_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC32_IN_INV_SEL_S 6 +/** GPIO_SIG32_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG32_IN_SEL (BIT(7)) +#define GPIO_SIG32_IN_SEL_M (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S) +#define GPIO_SIG32_IN_SEL_V 0x00000001U +#define GPIO_SIG32_IN_SEL_S 7 + +/** GPIO_FUNC33_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d8) +/** GPIO_FUNC33_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC33_IN_SEL 0x0000003FU +#define GPIO_FUNC33_IN_SEL_M (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S) +#define GPIO_FUNC33_IN_SEL_V 0x0000003FU +#define GPIO_FUNC33_IN_SEL_S 0 +/** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC33_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC33_IN_INV_SEL_M (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S) +#define GPIO_FUNC33_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC33_IN_INV_SEL_S 6 +/** GPIO_SIG33_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG33_IN_SEL (BIT(7)) +#define GPIO_SIG33_IN_SEL_M (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S) +#define GPIO_SIG33_IN_SEL_V 0x00000001U +#define GPIO_SIG33_IN_SEL_S 7 + +/** GPIO_FUNC34_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1dc) +/** GPIO_FUNC34_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC34_IN_SEL 0x0000003FU +#define GPIO_FUNC34_IN_SEL_M (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S) +#define GPIO_FUNC34_IN_SEL_V 0x0000003FU +#define GPIO_FUNC34_IN_SEL_S 0 +/** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC34_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC34_IN_INV_SEL_M (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S) +#define GPIO_FUNC34_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC34_IN_INV_SEL_S 6 +/** GPIO_SIG34_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG34_IN_SEL (BIT(7)) +#define GPIO_SIG34_IN_SEL_M (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S) +#define GPIO_SIG34_IN_SEL_V 0x00000001U +#define GPIO_SIG34_IN_SEL_S 7 + +/** GPIO_FUNC35_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e0) +/** GPIO_FUNC35_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC35_IN_SEL 0x0000003FU +#define GPIO_FUNC35_IN_SEL_M (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S) +#define GPIO_FUNC35_IN_SEL_V 0x0000003FU +#define GPIO_FUNC35_IN_SEL_S 0 +/** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC35_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC35_IN_INV_SEL_M (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S) +#define GPIO_FUNC35_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC35_IN_INV_SEL_S 6 +/** GPIO_SIG35_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG35_IN_SEL (BIT(7)) +#define GPIO_SIG35_IN_SEL_M (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S) +#define GPIO_SIG35_IN_SEL_V 0x00000001U +#define GPIO_SIG35_IN_SEL_S 7 + +/** GPIO_FUNC40_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f4) +/** GPIO_FUNC40_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC40_IN_SEL 0x0000003FU +#define GPIO_FUNC40_IN_SEL_M (GPIO_FUNC40_IN_SEL_V << GPIO_FUNC40_IN_SEL_S) +#define GPIO_FUNC40_IN_SEL_V 0x0000003FU +#define GPIO_FUNC40_IN_SEL_S 0 +/** GPIO_FUNC40_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC40_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC40_IN_INV_SEL_M (GPIO_FUNC40_IN_INV_SEL_V << GPIO_FUNC40_IN_INV_SEL_S) +#define GPIO_FUNC40_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC40_IN_INV_SEL_S 6 +/** GPIO_SIG40_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG40_IN_SEL (BIT(7)) +#define GPIO_SIG40_IN_SEL_M (GPIO_SIG40_IN_SEL_V << GPIO_SIG40_IN_SEL_S) +#define GPIO_SIG40_IN_SEL_V 0x00000001U +#define GPIO_SIG40_IN_SEL_S 7 + +/** GPIO_FUNC41_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f8) +/** GPIO_FUNC41_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC41_IN_SEL 0x0000003FU +#define GPIO_FUNC41_IN_SEL_M (GPIO_FUNC41_IN_SEL_V << GPIO_FUNC41_IN_SEL_S) +#define GPIO_FUNC41_IN_SEL_V 0x0000003FU +#define GPIO_FUNC41_IN_SEL_S 0 +/** GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC41_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC41_IN_INV_SEL_M (GPIO_FUNC41_IN_INV_SEL_V << GPIO_FUNC41_IN_INV_SEL_S) +#define GPIO_FUNC41_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC41_IN_INV_SEL_S 6 +/** GPIO_SIG41_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG41_IN_SEL (BIT(7)) +#define GPIO_SIG41_IN_SEL_M (GPIO_SIG41_IN_SEL_V << GPIO_SIG41_IN_SEL_S) +#define GPIO_SIG41_IN_SEL_V 0x00000001U +#define GPIO_SIG41_IN_SEL_S 7 + +/** GPIO_FUNC42_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1fc) +/** GPIO_FUNC42_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC42_IN_SEL 0x0000003FU +#define GPIO_FUNC42_IN_SEL_M (GPIO_FUNC42_IN_SEL_V << GPIO_FUNC42_IN_SEL_S) +#define GPIO_FUNC42_IN_SEL_V 0x0000003FU +#define GPIO_FUNC42_IN_SEL_S 0 +/** GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC42_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC42_IN_INV_SEL_M (GPIO_FUNC42_IN_INV_SEL_V << GPIO_FUNC42_IN_INV_SEL_S) +#define GPIO_FUNC42_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC42_IN_INV_SEL_S 6 +/** GPIO_SIG42_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG42_IN_SEL (BIT(7)) +#define GPIO_SIG42_IN_SEL_M (GPIO_SIG42_IN_SEL_V << GPIO_SIG42_IN_SEL_S) +#define GPIO_SIG42_IN_SEL_V 0x00000001U +#define GPIO_SIG42_IN_SEL_S 7 + +/** GPIO_FUNC45_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208) +/** GPIO_FUNC45_IN_SEL : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC45_IN_SEL 0x0000003FU +#define GPIO_FUNC45_IN_SEL_M (GPIO_FUNC45_IN_SEL_V << GPIO_FUNC45_IN_SEL_S) +#define GPIO_FUNC45_IN_SEL_V 0x0000003FU +#define GPIO_FUNC45_IN_SEL_S 0 +/** GPIO_FUNC45_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC45_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC45_IN_INV_SEL_M (GPIO_FUNC45_IN_INV_SEL_V << GPIO_FUNC45_IN_INV_SEL_S) +#define GPIO_FUNC45_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC45_IN_INV_SEL_S 6 +/** GPIO_SIG45_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG45_IN_SEL (BIT(7)) +#define GPIO_SIG45_IN_SEL_M (GPIO_SIG45_IN_SEL_V << GPIO_SIG45_IN_SEL_S) +#define GPIO_SIG45_IN_SEL_V 0x00000001U +#define GPIO_SIG45_IN_SEL_S 7 + +/** GPIO_FUNC46_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20c) +/** GPIO_FUNC46_IN_SEL : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC46_IN_SEL 0x0000003FU +#define GPIO_FUNC46_IN_SEL_M (GPIO_FUNC46_IN_SEL_V << GPIO_FUNC46_IN_SEL_S) +#define GPIO_FUNC46_IN_SEL_V 0x0000003FU +#define GPIO_FUNC46_IN_SEL_S 0 +/** GPIO_FUNC46_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC46_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC46_IN_INV_SEL_M (GPIO_FUNC46_IN_INV_SEL_V << GPIO_FUNC46_IN_INV_SEL_S) +#define GPIO_FUNC46_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC46_IN_INV_SEL_S 6 +/** GPIO_SIG46_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG46_IN_SEL (BIT(7)) +#define GPIO_SIG46_IN_SEL_M (GPIO_SIG46_IN_SEL_V << GPIO_SIG46_IN_SEL_S) +#define GPIO_SIG46_IN_SEL_V 0x00000001U +#define GPIO_SIG46_IN_SEL_S 7 + +/** GPIO_FUNC47_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x210) +/** GPIO_FUNC47_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC47_IN_SEL 0x0000003FU +#define GPIO_FUNC47_IN_SEL_M (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S) +#define GPIO_FUNC47_IN_SEL_V 0x0000003FU +#define GPIO_FUNC47_IN_SEL_S 0 +/** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC47_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC47_IN_INV_SEL_M (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S) +#define GPIO_FUNC47_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC47_IN_INV_SEL_S 6 +/** GPIO_SIG47_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG47_IN_SEL (BIT(7)) +#define GPIO_SIG47_IN_SEL_M (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S) +#define GPIO_SIG47_IN_SEL_V 0x00000001U +#define GPIO_SIG47_IN_SEL_S 7 + +/** GPIO_FUNC48_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214) +/** GPIO_FUNC48_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC48_IN_SEL 0x0000003FU +#define GPIO_FUNC48_IN_SEL_M (GPIO_FUNC48_IN_SEL_V << GPIO_FUNC48_IN_SEL_S) +#define GPIO_FUNC48_IN_SEL_V 0x0000003FU +#define GPIO_FUNC48_IN_SEL_S 0 +/** GPIO_FUNC48_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC48_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC48_IN_INV_SEL_M (GPIO_FUNC48_IN_INV_SEL_V << GPIO_FUNC48_IN_INV_SEL_S) +#define GPIO_FUNC48_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC48_IN_INV_SEL_S 6 +/** GPIO_SIG48_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG48_IN_SEL (BIT(7)) +#define GPIO_SIG48_IN_SEL_M (GPIO_SIG48_IN_SEL_V << GPIO_SIG48_IN_SEL_S) +#define GPIO_SIG48_IN_SEL_V 0x00000001U +#define GPIO_SIG48_IN_SEL_S 7 + +/** GPIO_FUNC49_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218) +/** GPIO_FUNC49_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC49_IN_SEL 0x0000003FU +#define GPIO_FUNC49_IN_SEL_M (GPIO_FUNC49_IN_SEL_V << GPIO_FUNC49_IN_SEL_S) +#define GPIO_FUNC49_IN_SEL_V 0x0000003FU +#define GPIO_FUNC49_IN_SEL_S 0 +/** GPIO_FUNC49_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC49_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC49_IN_INV_SEL_M (GPIO_FUNC49_IN_INV_SEL_V << GPIO_FUNC49_IN_INV_SEL_S) +#define GPIO_FUNC49_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC49_IN_INV_SEL_S 6 +/** GPIO_SIG49_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG49_IN_SEL (BIT(7)) +#define GPIO_SIG49_IN_SEL_M (GPIO_SIG49_IN_SEL_V << GPIO_SIG49_IN_SEL_S) +#define GPIO_SIG49_IN_SEL_V 0x00000001U +#define GPIO_SIG49_IN_SEL_S 7 + +/** GPIO_FUNC50_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21c) +/** GPIO_FUNC50_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC50_IN_SEL 0x0000003FU +#define GPIO_FUNC50_IN_SEL_M (GPIO_FUNC50_IN_SEL_V << GPIO_FUNC50_IN_SEL_S) +#define GPIO_FUNC50_IN_SEL_V 0x0000003FU +#define GPIO_FUNC50_IN_SEL_S 0 +/** GPIO_FUNC50_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC50_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC50_IN_INV_SEL_M (GPIO_FUNC50_IN_INV_SEL_V << GPIO_FUNC50_IN_INV_SEL_S) +#define GPIO_FUNC50_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC50_IN_INV_SEL_S 6 +/** GPIO_SIG50_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG50_IN_SEL (BIT(7)) +#define GPIO_SIG50_IN_SEL_M (GPIO_SIG50_IN_SEL_V << GPIO_SIG50_IN_SEL_S) +#define GPIO_SIG50_IN_SEL_V 0x00000001U +#define GPIO_SIG50_IN_SEL_S 7 + +/** GPIO_FUNC51_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220) +/** GPIO_FUNC51_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC51_IN_SEL 0x0000003FU +#define GPIO_FUNC51_IN_SEL_M (GPIO_FUNC51_IN_SEL_V << GPIO_FUNC51_IN_SEL_S) +#define GPIO_FUNC51_IN_SEL_V 0x0000003FU +#define GPIO_FUNC51_IN_SEL_S 0 +/** GPIO_FUNC51_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC51_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC51_IN_INV_SEL_M (GPIO_FUNC51_IN_INV_SEL_V << GPIO_FUNC51_IN_INV_SEL_S) +#define GPIO_FUNC51_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC51_IN_INV_SEL_S 6 +/** GPIO_SIG51_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG51_IN_SEL (BIT(7)) +#define GPIO_SIG51_IN_SEL_M (GPIO_SIG51_IN_SEL_V << GPIO_SIG51_IN_SEL_S) +#define GPIO_SIG51_IN_SEL_V 0x00000001U +#define GPIO_SIG51_IN_SEL_S 7 + +/** GPIO_FUNC52_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224) +/** GPIO_FUNC52_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC52_IN_SEL 0x0000003FU +#define GPIO_FUNC52_IN_SEL_M (GPIO_FUNC52_IN_SEL_V << GPIO_FUNC52_IN_SEL_S) +#define GPIO_FUNC52_IN_SEL_V 0x0000003FU +#define GPIO_FUNC52_IN_SEL_S 0 +/** GPIO_FUNC52_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC52_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC52_IN_INV_SEL_M (GPIO_FUNC52_IN_INV_SEL_V << GPIO_FUNC52_IN_INV_SEL_S) +#define GPIO_FUNC52_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC52_IN_INV_SEL_S 6 +/** GPIO_SIG52_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG52_IN_SEL (BIT(7)) +#define GPIO_SIG52_IN_SEL_M (GPIO_SIG52_IN_SEL_V << GPIO_SIG52_IN_SEL_S) +#define GPIO_SIG52_IN_SEL_V 0x00000001U +#define GPIO_SIG52_IN_SEL_S 7 + +/** GPIO_FUNC53_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228) +/** GPIO_FUNC53_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC53_IN_SEL 0x0000003FU +#define GPIO_FUNC53_IN_SEL_M (GPIO_FUNC53_IN_SEL_V << GPIO_FUNC53_IN_SEL_S) +#define GPIO_FUNC53_IN_SEL_V 0x0000003FU +#define GPIO_FUNC53_IN_SEL_S 0 +/** GPIO_FUNC53_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC53_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC53_IN_INV_SEL_M (GPIO_FUNC53_IN_INV_SEL_V << GPIO_FUNC53_IN_INV_SEL_S) +#define GPIO_FUNC53_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC53_IN_INV_SEL_S 6 +/** GPIO_SIG53_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG53_IN_SEL (BIT(7)) +#define GPIO_SIG53_IN_SEL_M (GPIO_SIG53_IN_SEL_V << GPIO_SIG53_IN_SEL_S) +#define GPIO_SIG53_IN_SEL_V 0x00000001U +#define GPIO_SIG53_IN_SEL_S 7 + +/** GPIO_FUNC54_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22c) +/** GPIO_FUNC54_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC54_IN_SEL 0x0000003FU +#define GPIO_FUNC54_IN_SEL_M (GPIO_FUNC54_IN_SEL_V << GPIO_FUNC54_IN_SEL_S) +#define GPIO_FUNC54_IN_SEL_V 0x0000003FU +#define GPIO_FUNC54_IN_SEL_S 0 +/** GPIO_FUNC54_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC54_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC54_IN_INV_SEL_M (GPIO_FUNC54_IN_INV_SEL_V << GPIO_FUNC54_IN_INV_SEL_S) +#define GPIO_FUNC54_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC54_IN_INV_SEL_S 6 +/** GPIO_SIG54_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG54_IN_SEL (BIT(7)) +#define GPIO_SIG54_IN_SEL_M (GPIO_SIG54_IN_SEL_V << GPIO_SIG54_IN_SEL_S) +#define GPIO_SIG54_IN_SEL_V 0x00000001U +#define GPIO_SIG54_IN_SEL_S 7 + +/** GPIO_FUNC55_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x230) +/** GPIO_FUNC55_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC55_IN_SEL 0x0000003FU +#define GPIO_FUNC55_IN_SEL_M (GPIO_FUNC55_IN_SEL_V << GPIO_FUNC55_IN_SEL_S) +#define GPIO_FUNC55_IN_SEL_V 0x0000003FU +#define GPIO_FUNC55_IN_SEL_S 0 +/** GPIO_FUNC55_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC55_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC55_IN_INV_SEL_M (GPIO_FUNC55_IN_INV_SEL_V << GPIO_FUNC55_IN_INV_SEL_S) +#define GPIO_FUNC55_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC55_IN_INV_SEL_S 6 +/** GPIO_SIG55_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG55_IN_SEL (BIT(7)) +#define GPIO_SIG55_IN_SEL_M (GPIO_SIG55_IN_SEL_V << GPIO_SIG55_IN_SEL_S) +#define GPIO_SIG55_IN_SEL_V 0x00000001U +#define GPIO_SIG55_IN_SEL_S 7 + +/** GPIO_FUNC56_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x234) +/** GPIO_FUNC56_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC56_IN_SEL 0x0000003FU +#define GPIO_FUNC56_IN_SEL_M (GPIO_FUNC56_IN_SEL_V << GPIO_FUNC56_IN_SEL_S) +#define GPIO_FUNC56_IN_SEL_V 0x0000003FU +#define GPIO_FUNC56_IN_SEL_S 0 +/** GPIO_FUNC56_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC56_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC56_IN_INV_SEL_M (GPIO_FUNC56_IN_INV_SEL_V << GPIO_FUNC56_IN_INV_SEL_S) +#define GPIO_FUNC56_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC56_IN_INV_SEL_S 6 +/** GPIO_SIG56_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG56_IN_SEL (BIT(7)) +#define GPIO_SIG56_IN_SEL_M (GPIO_SIG56_IN_SEL_V << GPIO_SIG56_IN_SEL_S) +#define GPIO_SIG56_IN_SEL_V 0x00000001U +#define GPIO_SIG56_IN_SEL_S 7 + +/** GPIO_FUNC57_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x238) +/** GPIO_FUNC57_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC57_IN_SEL 0x0000003FU +#define GPIO_FUNC57_IN_SEL_M (GPIO_FUNC57_IN_SEL_V << GPIO_FUNC57_IN_SEL_S) +#define GPIO_FUNC57_IN_SEL_V 0x0000003FU +#define GPIO_FUNC57_IN_SEL_S 0 +/** GPIO_FUNC57_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC57_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC57_IN_INV_SEL_M (GPIO_FUNC57_IN_INV_SEL_V << GPIO_FUNC57_IN_INV_SEL_S) +#define GPIO_FUNC57_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC57_IN_INV_SEL_S 6 +/** GPIO_SIG57_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG57_IN_SEL (BIT(7)) +#define GPIO_SIG57_IN_SEL_M (GPIO_SIG57_IN_SEL_V << GPIO_SIG57_IN_SEL_S) +#define GPIO_SIG57_IN_SEL_V 0x00000001U +#define GPIO_SIG57_IN_SEL_S 7 + +/** GPIO_FUNC58_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x23c) +/** GPIO_FUNC58_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC58_IN_SEL 0x0000003FU +#define GPIO_FUNC58_IN_SEL_M (GPIO_FUNC58_IN_SEL_V << GPIO_FUNC58_IN_SEL_S) +#define GPIO_FUNC58_IN_SEL_V 0x0000003FU +#define GPIO_FUNC58_IN_SEL_S 0 +/** GPIO_FUNC58_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC58_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC58_IN_INV_SEL_M (GPIO_FUNC58_IN_INV_SEL_V << GPIO_FUNC58_IN_INV_SEL_S) +#define GPIO_FUNC58_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC58_IN_INV_SEL_S 6 +/** GPIO_SIG58_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG58_IN_SEL (BIT(7)) +#define GPIO_SIG58_IN_SEL_M (GPIO_SIG58_IN_SEL_V << GPIO_SIG58_IN_SEL_S) +#define GPIO_SIG58_IN_SEL_V 0x00000001U +#define GPIO_SIG58_IN_SEL_S 7 + +/** GPIO_FUNC59_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x240) +/** GPIO_FUNC59_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC59_IN_SEL 0x0000003FU +#define GPIO_FUNC59_IN_SEL_M (GPIO_FUNC59_IN_SEL_V << GPIO_FUNC59_IN_SEL_S) +#define GPIO_FUNC59_IN_SEL_V 0x0000003FU +#define GPIO_FUNC59_IN_SEL_S 0 +/** GPIO_FUNC59_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC59_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC59_IN_INV_SEL_M (GPIO_FUNC59_IN_INV_SEL_V << GPIO_FUNC59_IN_INV_SEL_S) +#define GPIO_FUNC59_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC59_IN_INV_SEL_S 6 +/** GPIO_SIG59_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG59_IN_SEL (BIT(7)) +#define GPIO_SIG59_IN_SEL_M (GPIO_SIG59_IN_SEL_V << GPIO_SIG59_IN_SEL_S) +#define GPIO_SIG59_IN_SEL_V 0x00000001U +#define GPIO_SIG59_IN_SEL_S 7 + +/** GPIO_FUNC60_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x244) +/** GPIO_FUNC60_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC60_IN_SEL 0x0000003FU +#define GPIO_FUNC60_IN_SEL_M (GPIO_FUNC60_IN_SEL_V << GPIO_FUNC60_IN_SEL_S) +#define GPIO_FUNC60_IN_SEL_V 0x0000003FU +#define GPIO_FUNC60_IN_SEL_S 0 +/** GPIO_FUNC60_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC60_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC60_IN_INV_SEL_M (GPIO_FUNC60_IN_INV_SEL_V << GPIO_FUNC60_IN_INV_SEL_S) +#define GPIO_FUNC60_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC60_IN_INV_SEL_S 6 +/** GPIO_SIG60_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG60_IN_SEL (BIT(7)) +#define GPIO_SIG60_IN_SEL_M (GPIO_SIG60_IN_SEL_V << GPIO_SIG60_IN_SEL_S) +#define GPIO_SIG60_IN_SEL_V 0x00000001U +#define GPIO_SIG60_IN_SEL_S 7 + +/** GPIO_FUNC61_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x248) +/** GPIO_FUNC61_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC61_IN_SEL 0x0000003FU +#define GPIO_FUNC61_IN_SEL_M (GPIO_FUNC61_IN_SEL_V << GPIO_FUNC61_IN_SEL_S) +#define GPIO_FUNC61_IN_SEL_V 0x0000003FU +#define GPIO_FUNC61_IN_SEL_S 0 +/** GPIO_FUNC61_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC61_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC61_IN_INV_SEL_M (GPIO_FUNC61_IN_INV_SEL_V << GPIO_FUNC61_IN_INV_SEL_S) +#define GPIO_FUNC61_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC61_IN_INV_SEL_S 6 +/** GPIO_SIG61_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG61_IN_SEL (BIT(7)) +#define GPIO_SIG61_IN_SEL_M (GPIO_SIG61_IN_SEL_V << GPIO_SIG61_IN_SEL_S) +#define GPIO_SIG61_IN_SEL_V 0x00000001U +#define GPIO_SIG61_IN_SEL_S 7 + +/** GPIO_FUNC62_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x24c) +/** GPIO_FUNC62_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC62_IN_SEL 0x0000003FU +#define GPIO_FUNC62_IN_SEL_M (GPIO_FUNC62_IN_SEL_V << GPIO_FUNC62_IN_SEL_S) +#define GPIO_FUNC62_IN_SEL_V 0x0000003FU +#define GPIO_FUNC62_IN_SEL_S 0 +/** GPIO_FUNC62_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC62_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC62_IN_INV_SEL_M (GPIO_FUNC62_IN_INV_SEL_V << GPIO_FUNC62_IN_INV_SEL_S) +#define GPIO_FUNC62_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC62_IN_INV_SEL_S 6 +/** GPIO_SIG62_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG62_IN_SEL (BIT(7)) +#define GPIO_SIG62_IN_SEL_M (GPIO_SIG62_IN_SEL_V << GPIO_SIG62_IN_SEL_S) +#define GPIO_SIG62_IN_SEL_V 0x00000001U +#define GPIO_SIG62_IN_SEL_S 7 + +/** GPIO_FUNC63_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250) +/** GPIO_FUNC63_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC63_IN_SEL 0x0000003FU +#define GPIO_FUNC63_IN_SEL_M (GPIO_FUNC63_IN_SEL_V << GPIO_FUNC63_IN_SEL_S) +#define GPIO_FUNC63_IN_SEL_V 0x0000003FU +#define GPIO_FUNC63_IN_SEL_S 0 +/** GPIO_FUNC63_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC63_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC63_IN_INV_SEL_M (GPIO_FUNC63_IN_INV_SEL_V << GPIO_FUNC63_IN_INV_SEL_S) +#define GPIO_FUNC63_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC63_IN_INV_SEL_S 6 +/** GPIO_SIG63_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG63_IN_SEL (BIT(7)) +#define GPIO_SIG63_IN_SEL_M (GPIO_SIG63_IN_SEL_V << GPIO_SIG63_IN_SEL_S) +#define GPIO_SIG63_IN_SEL_V 0x00000001U +#define GPIO_SIG63_IN_SEL_S 7 + +/** GPIO_FUNC64_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254) +/** GPIO_FUNC64_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC64_IN_SEL 0x0000003FU +#define GPIO_FUNC64_IN_SEL_M (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S) +#define GPIO_FUNC64_IN_SEL_V 0x0000003FU +#define GPIO_FUNC64_IN_SEL_S 0 +/** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC64_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC64_IN_INV_SEL_M (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S) +#define GPIO_FUNC64_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC64_IN_INV_SEL_S 6 +/** GPIO_SIG64_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG64_IN_SEL (BIT(7)) +#define GPIO_SIG64_IN_SEL_M (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S) +#define GPIO_SIG64_IN_SEL_V 0x00000001U +#define GPIO_SIG64_IN_SEL_S 7 + +/** GPIO_FUNC65_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258) +/** GPIO_FUNC65_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC65_IN_SEL 0x0000003FU +#define GPIO_FUNC65_IN_SEL_M (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S) +#define GPIO_FUNC65_IN_SEL_V 0x0000003FU +#define GPIO_FUNC65_IN_SEL_S 0 +/** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC65_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC65_IN_INV_SEL_M (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S) +#define GPIO_FUNC65_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC65_IN_INV_SEL_S 6 +/** GPIO_SIG65_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG65_IN_SEL (BIT(7)) +#define GPIO_SIG65_IN_SEL_M (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S) +#define GPIO_SIG65_IN_SEL_V 0x00000001U +#define GPIO_SIG65_IN_SEL_S 7 + +/** GPIO_FUNC66_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25c) +/** GPIO_FUNC66_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC66_IN_SEL 0x0000003FU +#define GPIO_FUNC66_IN_SEL_M (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S) +#define GPIO_FUNC66_IN_SEL_V 0x0000003FU +#define GPIO_FUNC66_IN_SEL_S 0 +/** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC66_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC66_IN_INV_SEL_M (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S) +#define GPIO_FUNC66_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC66_IN_INV_SEL_S 6 +/** GPIO_SIG66_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG66_IN_SEL (BIT(7)) +#define GPIO_SIG66_IN_SEL_M (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S) +#define GPIO_SIG66_IN_SEL_V 0x00000001U +#define GPIO_SIG66_IN_SEL_S 7 + +/** GPIO_FUNC67_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260) +/** GPIO_FUNC67_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC67_IN_SEL 0x0000003FU +#define GPIO_FUNC67_IN_SEL_M (GPIO_FUNC67_IN_SEL_V << GPIO_FUNC67_IN_SEL_S) +#define GPIO_FUNC67_IN_SEL_V 0x0000003FU +#define GPIO_FUNC67_IN_SEL_S 0 +/** GPIO_FUNC67_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC67_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC67_IN_INV_SEL_M (GPIO_FUNC67_IN_INV_SEL_V << GPIO_FUNC67_IN_INV_SEL_S) +#define GPIO_FUNC67_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC67_IN_INV_SEL_S 6 +/** GPIO_SIG67_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG67_IN_SEL (BIT(7)) +#define GPIO_SIG67_IN_SEL_M (GPIO_SIG67_IN_SEL_V << GPIO_SIG67_IN_SEL_S) +#define GPIO_SIG67_IN_SEL_V 0x00000001U +#define GPIO_SIG67_IN_SEL_S 7 + +/** GPIO_FUNC68_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x264) +/** GPIO_FUNC68_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC68_IN_SEL 0x0000003FU +#define GPIO_FUNC68_IN_SEL_M (GPIO_FUNC68_IN_SEL_V << GPIO_FUNC68_IN_SEL_S) +#define GPIO_FUNC68_IN_SEL_V 0x0000003FU +#define GPIO_FUNC68_IN_SEL_S 0 +/** GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC68_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC68_IN_INV_SEL_M (GPIO_FUNC68_IN_INV_SEL_V << GPIO_FUNC68_IN_INV_SEL_S) +#define GPIO_FUNC68_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC68_IN_INV_SEL_S 6 +/** GPIO_SIG68_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG68_IN_SEL (BIT(7)) +#define GPIO_SIG68_IN_SEL_M (GPIO_SIG68_IN_SEL_V << GPIO_SIG68_IN_SEL_S) +#define GPIO_SIG68_IN_SEL_V 0x00000001U +#define GPIO_SIG68_IN_SEL_S 7 + +/** GPIO_FUNC69_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268) +/** GPIO_FUNC69_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC69_IN_SEL 0x0000003FU +#define GPIO_FUNC69_IN_SEL_M (GPIO_FUNC69_IN_SEL_V << GPIO_FUNC69_IN_SEL_S) +#define GPIO_FUNC69_IN_SEL_V 0x0000003FU +#define GPIO_FUNC69_IN_SEL_S 0 +/** GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC69_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC69_IN_INV_SEL_M (GPIO_FUNC69_IN_INV_SEL_V << GPIO_FUNC69_IN_INV_SEL_S) +#define GPIO_FUNC69_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC69_IN_INV_SEL_S 6 +/** GPIO_SIG69_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG69_IN_SEL (BIT(7)) +#define GPIO_SIG69_IN_SEL_M (GPIO_SIG69_IN_SEL_V << GPIO_SIG69_IN_SEL_S) +#define GPIO_SIG69_IN_SEL_V 0x00000001U +#define GPIO_SIG69_IN_SEL_S 7 + +/** GPIO_FUNC70_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26c) +/** GPIO_FUNC70_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC70_IN_SEL 0x0000003FU +#define GPIO_FUNC70_IN_SEL_M (GPIO_FUNC70_IN_SEL_V << GPIO_FUNC70_IN_SEL_S) +#define GPIO_FUNC70_IN_SEL_V 0x0000003FU +#define GPIO_FUNC70_IN_SEL_S 0 +/** GPIO_FUNC70_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC70_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC70_IN_INV_SEL_M (GPIO_FUNC70_IN_INV_SEL_V << GPIO_FUNC70_IN_INV_SEL_S) +#define GPIO_FUNC70_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC70_IN_INV_SEL_S 6 +/** GPIO_SIG70_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG70_IN_SEL (BIT(7)) +#define GPIO_SIG70_IN_SEL_M (GPIO_SIG70_IN_SEL_V << GPIO_SIG70_IN_SEL_S) +#define GPIO_SIG70_IN_SEL_V 0x00000001U +#define GPIO_SIG70_IN_SEL_S 7 + +/** GPIO_FUNC71_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270) +/** GPIO_FUNC71_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC71_IN_SEL 0x0000003FU +#define GPIO_FUNC71_IN_SEL_M (GPIO_FUNC71_IN_SEL_V << GPIO_FUNC71_IN_SEL_S) +#define GPIO_FUNC71_IN_SEL_V 0x0000003FU +#define GPIO_FUNC71_IN_SEL_S 0 +/** GPIO_FUNC71_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC71_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC71_IN_INV_SEL_M (GPIO_FUNC71_IN_INV_SEL_V << GPIO_FUNC71_IN_INV_SEL_S) +#define GPIO_FUNC71_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC71_IN_INV_SEL_S 6 +/** GPIO_SIG71_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG71_IN_SEL (BIT(7)) +#define GPIO_SIG71_IN_SEL_M (GPIO_SIG71_IN_SEL_V << GPIO_SIG71_IN_SEL_S) +#define GPIO_SIG71_IN_SEL_V 0x00000001U +#define GPIO_SIG71_IN_SEL_S 7 + +/** GPIO_FUNC72_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274) +/** GPIO_FUNC72_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC72_IN_SEL 0x0000003FU +#define GPIO_FUNC72_IN_SEL_M (GPIO_FUNC72_IN_SEL_V << GPIO_FUNC72_IN_SEL_S) +#define GPIO_FUNC72_IN_SEL_V 0x0000003FU +#define GPIO_FUNC72_IN_SEL_S 0 +/** GPIO_FUNC72_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC72_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC72_IN_INV_SEL_M (GPIO_FUNC72_IN_INV_SEL_V << GPIO_FUNC72_IN_INV_SEL_S) +#define GPIO_FUNC72_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC72_IN_INV_SEL_S 6 +/** GPIO_SIG72_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG72_IN_SEL (BIT(7)) +#define GPIO_SIG72_IN_SEL_M (GPIO_SIG72_IN_SEL_V << GPIO_SIG72_IN_SEL_S) +#define GPIO_SIG72_IN_SEL_V 0x00000001U +#define GPIO_SIG72_IN_SEL_S 7 + +/** GPIO_FUNC73_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x278) +/** GPIO_FUNC73_IN_SEL : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC73_IN_SEL 0x0000003FU +#define GPIO_FUNC73_IN_SEL_M (GPIO_FUNC73_IN_SEL_V << GPIO_FUNC73_IN_SEL_S) +#define GPIO_FUNC73_IN_SEL_V 0x0000003FU +#define GPIO_FUNC73_IN_SEL_S 0 +/** GPIO_FUNC73_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC73_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC73_IN_INV_SEL_M (GPIO_FUNC73_IN_INV_SEL_V << GPIO_FUNC73_IN_INV_SEL_S) +#define GPIO_FUNC73_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC73_IN_INV_SEL_S 6 +/** GPIO_SIG73_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG73_IN_SEL (BIT(7)) +#define GPIO_SIG73_IN_SEL_M (GPIO_SIG73_IN_SEL_V << GPIO_SIG73_IN_SEL_S) +#define GPIO_SIG73_IN_SEL_V 0x00000001U +#define GPIO_SIG73_IN_SEL_S 7 + +/** GPIO_FUNC77_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288) +/** GPIO_FUNC77_IN_SEL : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC77_IN_SEL 0x0000003FU +#define GPIO_FUNC77_IN_SEL_M (GPIO_FUNC77_IN_SEL_V << GPIO_FUNC77_IN_SEL_S) +#define GPIO_FUNC77_IN_SEL_V 0x0000003FU +#define GPIO_FUNC77_IN_SEL_S 0 +/** GPIO_FUNC77_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC77_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC77_IN_INV_SEL_M (GPIO_FUNC77_IN_INV_SEL_V << GPIO_FUNC77_IN_INV_SEL_S) +#define GPIO_FUNC77_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC77_IN_INV_SEL_S 6 +/** GPIO_SIG77_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG77_IN_SEL (BIT(7)) +#define GPIO_SIG77_IN_SEL_M (GPIO_SIG77_IN_SEL_V << GPIO_SIG77_IN_SEL_S) +#define GPIO_SIG77_IN_SEL_V 0x00000001U +#define GPIO_SIG77_IN_SEL_S 7 + +/** GPIO_FUNC81_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298) +/** GPIO_FUNC81_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC81_IN_SEL 0x0000003FU +#define GPIO_FUNC81_IN_SEL_M (GPIO_FUNC81_IN_SEL_V << GPIO_FUNC81_IN_SEL_S) +#define GPIO_FUNC81_IN_SEL_V 0x0000003FU +#define GPIO_FUNC81_IN_SEL_S 0 +/** GPIO_FUNC81_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC81_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC81_IN_INV_SEL_M (GPIO_FUNC81_IN_INV_SEL_V << GPIO_FUNC81_IN_INV_SEL_S) +#define GPIO_FUNC81_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC81_IN_INV_SEL_S 6 +/** GPIO_SIG81_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG81_IN_SEL (BIT(7)) +#define GPIO_SIG81_IN_SEL_M (GPIO_SIG81_IN_SEL_V << GPIO_SIG81_IN_SEL_S) +#define GPIO_SIG81_IN_SEL_V 0x00000001U +#define GPIO_SIG81_IN_SEL_S 7 + +/** GPIO_FUNC82_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x29c) +/** GPIO_FUNC82_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC82_IN_SEL 0x0000003FU +#define GPIO_FUNC82_IN_SEL_M (GPIO_FUNC82_IN_SEL_V << GPIO_FUNC82_IN_SEL_S) +#define GPIO_FUNC82_IN_SEL_V 0x0000003FU +#define GPIO_FUNC82_IN_SEL_S 0 +/** GPIO_FUNC82_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC82_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC82_IN_INV_SEL_M (GPIO_FUNC82_IN_INV_SEL_V << GPIO_FUNC82_IN_INV_SEL_S) +#define GPIO_FUNC82_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC82_IN_INV_SEL_S 6 +/** GPIO_SIG82_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG82_IN_SEL (BIT(7)) +#define GPIO_SIG82_IN_SEL_M (GPIO_SIG82_IN_SEL_V << GPIO_SIG82_IN_SEL_S) +#define GPIO_SIG82_IN_SEL_V 0x00000001U +#define GPIO_SIG82_IN_SEL_S 7 + +/** GPIO_FUNC87_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b0) +/** GPIO_FUNC87_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC87_IN_SEL 0x0000003FU +#define GPIO_FUNC87_IN_SEL_M (GPIO_FUNC87_IN_SEL_V << GPIO_FUNC87_IN_SEL_S) +#define GPIO_FUNC87_IN_SEL_V 0x0000003FU +#define GPIO_FUNC87_IN_SEL_S 0 +/** GPIO_FUNC87_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC87_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC87_IN_INV_SEL_M (GPIO_FUNC87_IN_INV_SEL_V << GPIO_FUNC87_IN_INV_SEL_S) +#define GPIO_FUNC87_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC87_IN_INV_SEL_S 6 +/** GPIO_SIG87_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG87_IN_SEL (BIT(7)) +#define GPIO_SIG87_IN_SEL_M (GPIO_SIG87_IN_SEL_V << GPIO_SIG87_IN_SEL_S) +#define GPIO_SIG87_IN_SEL_V 0x00000001U +#define GPIO_SIG87_IN_SEL_S 7 + +/** GPIO_FUNC88_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b4) +/** GPIO_FUNC88_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC88_IN_SEL 0x0000003FU +#define GPIO_FUNC88_IN_SEL_M (GPIO_FUNC88_IN_SEL_V << GPIO_FUNC88_IN_SEL_S) +#define GPIO_FUNC88_IN_SEL_V 0x0000003FU +#define GPIO_FUNC88_IN_SEL_S 0 +/** GPIO_FUNC88_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC88_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC88_IN_INV_SEL_M (GPIO_FUNC88_IN_INV_SEL_V << GPIO_FUNC88_IN_INV_SEL_S) +#define GPIO_FUNC88_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC88_IN_INV_SEL_S 6 +/** GPIO_SIG88_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG88_IN_SEL (BIT(7)) +#define GPIO_SIG88_IN_SEL_M (GPIO_SIG88_IN_SEL_V << GPIO_SIG88_IN_SEL_S) +#define GPIO_SIG88_IN_SEL_V 0x00000001U +#define GPIO_SIG88_IN_SEL_S 7 + +/** GPIO_FUNC89_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b8) +/** GPIO_FUNC89_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC89_IN_SEL 0x0000003FU +#define GPIO_FUNC89_IN_SEL_M (GPIO_FUNC89_IN_SEL_V << GPIO_FUNC89_IN_SEL_S) +#define GPIO_FUNC89_IN_SEL_V 0x0000003FU +#define GPIO_FUNC89_IN_SEL_S 0 +/** GPIO_FUNC89_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC89_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC89_IN_INV_SEL_M (GPIO_FUNC89_IN_INV_SEL_V << GPIO_FUNC89_IN_INV_SEL_S) +#define GPIO_FUNC89_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC89_IN_INV_SEL_S 6 +/** GPIO_SIG89_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG89_IN_SEL (BIT(7)) +#define GPIO_SIG89_IN_SEL_M (GPIO_SIG89_IN_SEL_V << GPIO_SIG89_IN_SEL_S) +#define GPIO_SIG89_IN_SEL_V 0x00000001U +#define GPIO_SIG89_IN_SEL_S 7 + +/** GPIO_FUNC90_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2bc) +/** GPIO_FUNC90_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC90_IN_SEL 0x0000003FU +#define GPIO_FUNC90_IN_SEL_M (GPIO_FUNC90_IN_SEL_V << GPIO_FUNC90_IN_SEL_S) +#define GPIO_FUNC90_IN_SEL_V 0x0000003FU +#define GPIO_FUNC90_IN_SEL_S 0 +/** GPIO_FUNC90_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC90_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC90_IN_INV_SEL_M (GPIO_FUNC90_IN_INV_SEL_V << GPIO_FUNC90_IN_INV_SEL_S) +#define GPIO_FUNC90_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC90_IN_INV_SEL_S 6 +/** GPIO_SIG90_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG90_IN_SEL (BIT(7)) +#define GPIO_SIG90_IN_SEL_M (GPIO_SIG90_IN_SEL_V << GPIO_SIG90_IN_SEL_S) +#define GPIO_SIG90_IN_SEL_V 0x00000001U +#define GPIO_SIG90_IN_SEL_S 7 + +/** GPIO_FUNC91_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c0) +/** GPIO_FUNC91_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC91_IN_SEL 0x0000003FU +#define GPIO_FUNC91_IN_SEL_M (GPIO_FUNC91_IN_SEL_V << GPIO_FUNC91_IN_SEL_S) +#define GPIO_FUNC91_IN_SEL_V 0x0000003FU +#define GPIO_FUNC91_IN_SEL_S 0 +/** GPIO_FUNC91_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC91_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC91_IN_INV_SEL_M (GPIO_FUNC91_IN_INV_SEL_V << GPIO_FUNC91_IN_INV_SEL_S) +#define GPIO_FUNC91_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC91_IN_INV_SEL_S 6 +/** GPIO_SIG91_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG91_IN_SEL (BIT(7)) +#define GPIO_SIG91_IN_SEL_M (GPIO_SIG91_IN_SEL_V << GPIO_SIG91_IN_SEL_S) +#define GPIO_SIG91_IN_SEL_V 0x00000001U +#define GPIO_SIG91_IN_SEL_S 7 + +/** GPIO_FUNC92_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4) +/** GPIO_FUNC92_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC92_IN_SEL 0x0000003FU +#define GPIO_FUNC92_IN_SEL_M (GPIO_FUNC92_IN_SEL_V << GPIO_FUNC92_IN_SEL_S) +#define GPIO_FUNC92_IN_SEL_V 0x0000003FU +#define GPIO_FUNC92_IN_SEL_S 0 +/** GPIO_FUNC92_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC92_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC92_IN_INV_SEL_M (GPIO_FUNC92_IN_INV_SEL_V << GPIO_FUNC92_IN_INV_SEL_S) +#define GPIO_FUNC92_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC92_IN_INV_SEL_S 6 +/** GPIO_SIG92_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG92_IN_SEL (BIT(7)) +#define GPIO_SIG92_IN_SEL_M (GPIO_SIG92_IN_SEL_V << GPIO_SIG92_IN_SEL_S) +#define GPIO_SIG92_IN_SEL_V 0x00000001U +#define GPIO_SIG92_IN_SEL_S 7 + +/** GPIO_FUNC93_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c8) +/** GPIO_FUNC93_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC93_IN_SEL 0x0000003FU +#define GPIO_FUNC93_IN_SEL_M (GPIO_FUNC93_IN_SEL_V << GPIO_FUNC93_IN_SEL_S) +#define GPIO_FUNC93_IN_SEL_V 0x0000003FU +#define GPIO_FUNC93_IN_SEL_S 0 +/** GPIO_FUNC93_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC93_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC93_IN_INV_SEL_M (GPIO_FUNC93_IN_INV_SEL_V << GPIO_FUNC93_IN_INV_SEL_S) +#define GPIO_FUNC93_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC93_IN_INV_SEL_S 6 +/** GPIO_SIG93_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG93_IN_SEL (BIT(7)) +#define GPIO_SIG93_IN_SEL_M (GPIO_SIG93_IN_SEL_V << GPIO_SIG93_IN_SEL_S) +#define GPIO_SIG93_IN_SEL_V 0x00000001U +#define GPIO_SIG93_IN_SEL_S 7 + +/** GPIO_FUNC94_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2cc) +/** GPIO_FUNC94_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC94_IN_SEL 0x0000003FU +#define GPIO_FUNC94_IN_SEL_M (GPIO_FUNC94_IN_SEL_V << GPIO_FUNC94_IN_SEL_S) +#define GPIO_FUNC94_IN_SEL_V 0x0000003FU +#define GPIO_FUNC94_IN_SEL_S 0 +/** GPIO_FUNC94_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC94_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC94_IN_INV_SEL_M (GPIO_FUNC94_IN_INV_SEL_V << GPIO_FUNC94_IN_INV_SEL_S) +#define GPIO_FUNC94_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC94_IN_INV_SEL_S 6 +/** GPIO_SIG94_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG94_IN_SEL (BIT(7)) +#define GPIO_SIG94_IN_SEL_M (GPIO_SIG94_IN_SEL_V << GPIO_SIG94_IN_SEL_S) +#define GPIO_SIG94_IN_SEL_V 0x00000001U +#define GPIO_SIG94_IN_SEL_S 7 + +/** GPIO_FUNC95_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d0) +/** GPIO_FUNC95_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC95_IN_SEL 0x0000003FU +#define GPIO_FUNC95_IN_SEL_M (GPIO_FUNC95_IN_SEL_V << GPIO_FUNC95_IN_SEL_S) +#define GPIO_FUNC95_IN_SEL_V 0x0000003FU +#define GPIO_FUNC95_IN_SEL_S 0 +/** GPIO_FUNC95_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC95_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC95_IN_INV_SEL_M (GPIO_FUNC95_IN_INV_SEL_V << GPIO_FUNC95_IN_INV_SEL_S) +#define GPIO_FUNC95_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC95_IN_INV_SEL_S 6 +/** GPIO_SIG95_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG95_IN_SEL (BIT(7)) +#define GPIO_SIG95_IN_SEL_M (GPIO_SIG95_IN_SEL_V << GPIO_SIG95_IN_SEL_S) +#define GPIO_SIG95_IN_SEL_V 0x00000001U +#define GPIO_SIG95_IN_SEL_S 7 + +/** GPIO_FUNC97_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d8) +/** GPIO_FUNC97_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC97_IN_SEL 0x0000003FU +#define GPIO_FUNC97_IN_SEL_M (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S) +#define GPIO_FUNC97_IN_SEL_V 0x0000003FU +#define GPIO_FUNC97_IN_SEL_S 0 +/** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC97_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC97_IN_INV_SEL_M (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S) +#define GPIO_FUNC97_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC97_IN_INV_SEL_S 6 +/** GPIO_SIG97_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG97_IN_SEL (BIT(7)) +#define GPIO_SIG97_IN_SEL_M (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S) +#define GPIO_SIG97_IN_SEL_V 0x00000001U +#define GPIO_SIG97_IN_SEL_S 7 + +/** GPIO_FUNC98_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc) +/** GPIO_FUNC98_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC98_IN_SEL 0x0000003FU +#define GPIO_FUNC98_IN_SEL_M (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S) +#define GPIO_FUNC98_IN_SEL_V 0x0000003FU +#define GPIO_FUNC98_IN_SEL_S 0 +/** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC98_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC98_IN_INV_SEL_M (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S) +#define GPIO_FUNC98_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC98_IN_INV_SEL_S 6 +/** GPIO_SIG98_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG98_IN_SEL (BIT(7)) +#define GPIO_SIG98_IN_SEL_M (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S) +#define GPIO_SIG98_IN_SEL_V 0x00000001U +#define GPIO_SIG98_IN_SEL_S 7 + +/** GPIO_FUNC99_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0) +/** GPIO_FUNC99_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC99_IN_SEL 0x0000003FU +#define GPIO_FUNC99_IN_SEL_M (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S) +#define GPIO_FUNC99_IN_SEL_V 0x0000003FU +#define GPIO_FUNC99_IN_SEL_S 0 +/** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC99_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC99_IN_INV_SEL_M (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S) +#define GPIO_FUNC99_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC99_IN_INV_SEL_S 6 +/** GPIO_SIG99_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG99_IN_SEL (BIT(7)) +#define GPIO_SIG99_IN_SEL_M (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S) +#define GPIO_SIG99_IN_SEL_V 0x00000001U +#define GPIO_SIG99_IN_SEL_S 7 + +/** GPIO_FUNC100_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4) +/** GPIO_FUNC100_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC100_IN_SEL 0x0000003FU +#define GPIO_FUNC100_IN_SEL_M (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S) +#define GPIO_FUNC100_IN_SEL_V 0x0000003FU +#define GPIO_FUNC100_IN_SEL_S 0 +/** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC100_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC100_IN_INV_SEL_M (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S) +#define GPIO_FUNC100_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC100_IN_INV_SEL_S 6 +/** GPIO_SIG100_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG100_IN_SEL (BIT(7)) +#define GPIO_SIG100_IN_SEL_M (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S) +#define GPIO_SIG100_IN_SEL_V 0x00000001U +#define GPIO_SIG100_IN_SEL_S 7 + +/** GPIO_FUNC101_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8) +/** GPIO_FUNC101_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC101_IN_SEL 0x0000003FU +#define GPIO_FUNC101_IN_SEL_M (GPIO_FUNC101_IN_SEL_V << GPIO_FUNC101_IN_SEL_S) +#define GPIO_FUNC101_IN_SEL_V 0x0000003FU +#define GPIO_FUNC101_IN_SEL_S 0 +/** GPIO_FUNC101_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC101_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC101_IN_INV_SEL_M (GPIO_FUNC101_IN_INV_SEL_V << GPIO_FUNC101_IN_INV_SEL_S) +#define GPIO_FUNC101_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC101_IN_INV_SEL_S 6 +/** GPIO_SIG101_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG101_IN_SEL (BIT(7)) +#define GPIO_SIG101_IN_SEL_M (GPIO_SIG101_IN_SEL_V << GPIO_SIG101_IN_SEL_S) +#define GPIO_SIG101_IN_SEL_V 0x00000001U +#define GPIO_SIG101_IN_SEL_S 7 + +/** GPIO_FUNC102_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec) +/** GPIO_FUNC102_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC102_IN_SEL 0x0000003FU +#define GPIO_FUNC102_IN_SEL_M (GPIO_FUNC102_IN_SEL_V << GPIO_FUNC102_IN_SEL_S) +#define GPIO_FUNC102_IN_SEL_V 0x0000003FU +#define GPIO_FUNC102_IN_SEL_S 0 +/** GPIO_FUNC102_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC102_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC102_IN_INV_SEL_M (GPIO_FUNC102_IN_INV_SEL_V << GPIO_FUNC102_IN_INV_SEL_S) +#define GPIO_FUNC102_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC102_IN_INV_SEL_S 6 +/** GPIO_SIG102_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG102_IN_SEL (BIT(7)) +#define GPIO_SIG102_IN_SEL_M (GPIO_SIG102_IN_SEL_V << GPIO_SIG102_IN_SEL_S) +#define GPIO_SIG102_IN_SEL_V 0x00000001U +#define GPIO_SIG102_IN_SEL_S 7 + +/** GPIO_FUNC103_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0) +/** GPIO_FUNC103_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC103_IN_SEL 0x0000003FU +#define GPIO_FUNC103_IN_SEL_M (GPIO_FUNC103_IN_SEL_V << GPIO_FUNC103_IN_SEL_S) +#define GPIO_FUNC103_IN_SEL_V 0x0000003FU +#define GPIO_FUNC103_IN_SEL_S 0 +/** GPIO_FUNC103_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC103_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC103_IN_INV_SEL_M (GPIO_FUNC103_IN_INV_SEL_V << GPIO_FUNC103_IN_INV_SEL_S) +#define GPIO_FUNC103_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC103_IN_INV_SEL_S 6 +/** GPIO_SIG103_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG103_IN_SEL (BIT(7)) +#define GPIO_SIG103_IN_SEL_M (GPIO_SIG103_IN_SEL_V << GPIO_SIG103_IN_SEL_S) +#define GPIO_SIG103_IN_SEL_V 0x00000001U +#define GPIO_SIG103_IN_SEL_S 7 + +/** GPIO_FUNC104_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4) +/** GPIO_FUNC104_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC104_IN_SEL 0x0000003FU +#define GPIO_FUNC104_IN_SEL_M (GPIO_FUNC104_IN_SEL_V << GPIO_FUNC104_IN_SEL_S) +#define GPIO_FUNC104_IN_SEL_V 0x0000003FU +#define GPIO_FUNC104_IN_SEL_S 0 +/** GPIO_FUNC104_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC104_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC104_IN_INV_SEL_M (GPIO_FUNC104_IN_INV_SEL_V << GPIO_FUNC104_IN_INV_SEL_S) +#define GPIO_FUNC104_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC104_IN_INV_SEL_S 6 +/** GPIO_SIG104_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG104_IN_SEL (BIT(7)) +#define GPIO_SIG104_IN_SEL_M (GPIO_SIG104_IN_SEL_V << GPIO_SIG104_IN_SEL_S) +#define GPIO_SIG104_IN_SEL_V 0x00000001U +#define GPIO_SIG104_IN_SEL_S 7 + +/** GPIO_FUNC105_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8) +/** GPIO_FUNC105_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC105_IN_SEL 0x0000003FU +#define GPIO_FUNC105_IN_SEL_M (GPIO_FUNC105_IN_SEL_V << GPIO_FUNC105_IN_SEL_S) +#define GPIO_FUNC105_IN_SEL_V 0x0000003FU +#define GPIO_FUNC105_IN_SEL_S 0 +/** GPIO_FUNC105_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC105_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC105_IN_INV_SEL_M (GPIO_FUNC105_IN_INV_SEL_V << GPIO_FUNC105_IN_INV_SEL_S) +#define GPIO_FUNC105_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC105_IN_INV_SEL_S 6 +/** GPIO_SIG105_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG105_IN_SEL (BIT(7)) +#define GPIO_SIG105_IN_SEL_M (GPIO_SIG105_IN_SEL_V << GPIO_SIG105_IN_SEL_S) +#define GPIO_SIG105_IN_SEL_V 0x00000001U +#define GPIO_SIG105_IN_SEL_S 7 + +/** GPIO_FUNC106_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc) +/** GPIO_FUNC106_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC106_IN_SEL 0x0000003FU +#define GPIO_FUNC106_IN_SEL_M (GPIO_FUNC106_IN_SEL_V << GPIO_FUNC106_IN_SEL_S) +#define GPIO_FUNC106_IN_SEL_V 0x0000003FU +#define GPIO_FUNC106_IN_SEL_S 0 +/** GPIO_FUNC106_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC106_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC106_IN_INV_SEL_M (GPIO_FUNC106_IN_INV_SEL_V << GPIO_FUNC106_IN_INV_SEL_S) +#define GPIO_FUNC106_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC106_IN_INV_SEL_S 6 +/** GPIO_SIG106_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG106_IN_SEL (BIT(7)) +#define GPIO_SIG106_IN_SEL_M (GPIO_SIG106_IN_SEL_V << GPIO_SIG106_IN_SEL_S) +#define GPIO_SIG106_IN_SEL_V 0x00000001U +#define GPIO_SIG106_IN_SEL_S 7 + +/** GPIO_FUNC107_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) +/** GPIO_FUNC107_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC107_IN_SEL 0x0000003FU +#define GPIO_FUNC107_IN_SEL_M (GPIO_FUNC107_IN_SEL_V << GPIO_FUNC107_IN_SEL_S) +#define GPIO_FUNC107_IN_SEL_V 0x0000003FU +#define GPIO_FUNC107_IN_SEL_S 0 +/** GPIO_FUNC107_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC107_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC107_IN_INV_SEL_M (GPIO_FUNC107_IN_INV_SEL_V << GPIO_FUNC107_IN_INV_SEL_S) +#define GPIO_FUNC107_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC107_IN_INV_SEL_S 6 +/** GPIO_SIG107_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG107_IN_SEL (BIT(7)) +#define GPIO_SIG107_IN_SEL_M (GPIO_SIG107_IN_SEL_V << GPIO_SIG107_IN_SEL_S) +#define GPIO_SIG107_IN_SEL_V 0x00000001U +#define GPIO_SIG107_IN_SEL_S 7 + +/** GPIO_FUNC108_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) +/** GPIO_FUNC108_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC108_IN_SEL 0x0000003FU +#define GPIO_FUNC108_IN_SEL_M (GPIO_FUNC108_IN_SEL_V << GPIO_FUNC108_IN_SEL_S) +#define GPIO_FUNC108_IN_SEL_V 0x0000003FU +#define GPIO_FUNC108_IN_SEL_S 0 +/** GPIO_FUNC108_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC108_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC108_IN_INV_SEL_M (GPIO_FUNC108_IN_INV_SEL_V << GPIO_FUNC108_IN_INV_SEL_S) +#define GPIO_FUNC108_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC108_IN_INV_SEL_S 6 +/** GPIO_SIG108_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG108_IN_SEL (BIT(7)) +#define GPIO_SIG108_IN_SEL_M (GPIO_SIG108_IN_SEL_V << GPIO_SIG108_IN_SEL_S) +#define GPIO_SIG108_IN_SEL_V 0x00000001U +#define GPIO_SIG108_IN_SEL_S 7 + +/** GPIO_FUNC109_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) +/** GPIO_FUNC109_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC109_IN_SEL 0x0000003FU +#define GPIO_FUNC109_IN_SEL_M (GPIO_FUNC109_IN_SEL_V << GPIO_FUNC109_IN_SEL_S) +#define GPIO_FUNC109_IN_SEL_V 0x0000003FU +#define GPIO_FUNC109_IN_SEL_S 0 +/** GPIO_FUNC109_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC109_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC109_IN_INV_SEL_M (GPIO_FUNC109_IN_INV_SEL_V << GPIO_FUNC109_IN_INV_SEL_S) +#define GPIO_FUNC109_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC109_IN_INV_SEL_S 6 +/** GPIO_SIG109_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG109_IN_SEL (BIT(7)) +#define GPIO_SIG109_IN_SEL_M (GPIO_SIG109_IN_SEL_V << GPIO_SIG109_IN_SEL_S) +#define GPIO_SIG109_IN_SEL_V 0x00000001U +#define GPIO_SIG109_IN_SEL_S 7 + +/** GPIO_FUNC110_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c) +/** GPIO_FUNC110_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC110_IN_SEL 0x0000003FU +#define GPIO_FUNC110_IN_SEL_M (GPIO_FUNC110_IN_SEL_V << GPIO_FUNC110_IN_SEL_S) +#define GPIO_FUNC110_IN_SEL_V 0x0000003FU +#define GPIO_FUNC110_IN_SEL_S 0 +/** GPIO_FUNC110_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC110_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC110_IN_INV_SEL_M (GPIO_FUNC110_IN_INV_SEL_V << GPIO_FUNC110_IN_INV_SEL_S) +#define GPIO_FUNC110_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC110_IN_INV_SEL_S 6 +/** GPIO_SIG110_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG110_IN_SEL (BIT(7)) +#define GPIO_SIG110_IN_SEL_M (GPIO_SIG110_IN_SEL_V << GPIO_SIG110_IN_SEL_S) +#define GPIO_SIG110_IN_SEL_V 0x00000001U +#define GPIO_SIG110_IN_SEL_S 7 + +/** GPIO_FUNC111_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310) +/** GPIO_FUNC111_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC111_IN_SEL 0x0000003FU +#define GPIO_FUNC111_IN_SEL_M (GPIO_FUNC111_IN_SEL_V << GPIO_FUNC111_IN_SEL_S) +#define GPIO_FUNC111_IN_SEL_V 0x0000003FU +#define GPIO_FUNC111_IN_SEL_S 0 +/** GPIO_FUNC111_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC111_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC111_IN_INV_SEL_M (GPIO_FUNC111_IN_INV_SEL_V << GPIO_FUNC111_IN_INV_SEL_S) +#define GPIO_FUNC111_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC111_IN_INV_SEL_S 6 +/** GPIO_SIG111_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG111_IN_SEL (BIT(7)) +#define GPIO_SIG111_IN_SEL_M (GPIO_SIG111_IN_SEL_V << GPIO_SIG111_IN_SEL_S) +#define GPIO_SIG111_IN_SEL_V 0x00000001U +#define GPIO_SIG111_IN_SEL_S 7 + +/** GPIO_FUNC112_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314) +/** GPIO_FUNC112_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC112_IN_SEL 0x0000003FU +#define GPIO_FUNC112_IN_SEL_M (GPIO_FUNC112_IN_SEL_V << GPIO_FUNC112_IN_SEL_S) +#define GPIO_FUNC112_IN_SEL_V 0x0000003FU +#define GPIO_FUNC112_IN_SEL_S 0 +/** GPIO_FUNC112_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC112_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC112_IN_INV_SEL_M (GPIO_FUNC112_IN_INV_SEL_V << GPIO_FUNC112_IN_INV_SEL_S) +#define GPIO_FUNC112_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC112_IN_INV_SEL_S 6 +/** GPIO_SIG112_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG112_IN_SEL (BIT(7)) +#define GPIO_SIG112_IN_SEL_M (GPIO_SIG112_IN_SEL_V << GPIO_SIG112_IN_SEL_S) +#define GPIO_SIG112_IN_SEL_V 0x00000001U +#define GPIO_SIG112_IN_SEL_S 7 + +/** GPIO_FUNC113_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318) +/** GPIO_FUNC113_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC113_IN_SEL 0x0000003FU +#define GPIO_FUNC113_IN_SEL_M (GPIO_FUNC113_IN_SEL_V << GPIO_FUNC113_IN_SEL_S) +#define GPIO_FUNC113_IN_SEL_V 0x0000003FU +#define GPIO_FUNC113_IN_SEL_S 0 +/** GPIO_FUNC113_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC113_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC113_IN_INV_SEL_M (GPIO_FUNC113_IN_INV_SEL_V << GPIO_FUNC113_IN_INV_SEL_S) +#define GPIO_FUNC113_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC113_IN_INV_SEL_S 6 +/** GPIO_SIG113_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG113_IN_SEL (BIT(7)) +#define GPIO_SIG113_IN_SEL_M (GPIO_SIG113_IN_SEL_V << GPIO_SIG113_IN_SEL_S) +#define GPIO_SIG113_IN_SEL_V 0x00000001U +#define GPIO_SIG113_IN_SEL_S 7 + +/** GPIO_FUNC114_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31c) +/** GPIO_FUNC114_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC114_IN_SEL 0x0000003FU +#define GPIO_FUNC114_IN_SEL_M (GPIO_FUNC114_IN_SEL_V << GPIO_FUNC114_IN_SEL_S) +#define GPIO_FUNC114_IN_SEL_V 0x0000003FU +#define GPIO_FUNC114_IN_SEL_S 0 +/** GPIO_FUNC114_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC114_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC114_IN_INV_SEL_M (GPIO_FUNC114_IN_INV_SEL_V << GPIO_FUNC114_IN_INV_SEL_S) +#define GPIO_FUNC114_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC114_IN_INV_SEL_S 6 +/** GPIO_SIG114_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG114_IN_SEL (BIT(7)) +#define GPIO_SIG114_IN_SEL_M (GPIO_SIG114_IN_SEL_V << GPIO_SIG114_IN_SEL_S) +#define GPIO_SIG114_IN_SEL_V 0x00000001U +#define GPIO_SIG114_IN_SEL_S 7 + +/** GPIO_FUNC115_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320) +/** GPIO_FUNC115_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC115_IN_SEL 0x0000003FU +#define GPIO_FUNC115_IN_SEL_M (GPIO_FUNC115_IN_SEL_V << GPIO_FUNC115_IN_SEL_S) +#define GPIO_FUNC115_IN_SEL_V 0x0000003FU +#define GPIO_FUNC115_IN_SEL_S 0 +/** GPIO_FUNC115_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC115_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC115_IN_INV_SEL_M (GPIO_FUNC115_IN_INV_SEL_V << GPIO_FUNC115_IN_INV_SEL_S) +#define GPIO_FUNC115_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC115_IN_INV_SEL_S 6 +/** GPIO_SIG115_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG115_IN_SEL (BIT(7)) +#define GPIO_SIG115_IN_SEL_M (GPIO_SIG115_IN_SEL_V << GPIO_SIG115_IN_SEL_S) +#define GPIO_SIG115_IN_SEL_V 0x00000001U +#define GPIO_SIG115_IN_SEL_S 7 + +/** GPIO_FUNC116_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x324) +/** GPIO_FUNC116_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC116_IN_SEL 0x0000003FU +#define GPIO_FUNC116_IN_SEL_M (GPIO_FUNC116_IN_SEL_V << GPIO_FUNC116_IN_SEL_S) +#define GPIO_FUNC116_IN_SEL_V 0x0000003FU +#define GPIO_FUNC116_IN_SEL_S 0 +/** GPIO_FUNC116_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC116_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC116_IN_INV_SEL_M (GPIO_FUNC116_IN_INV_SEL_V << GPIO_FUNC116_IN_INV_SEL_S) +#define GPIO_FUNC116_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC116_IN_INV_SEL_S 6 +/** GPIO_SIG116_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG116_IN_SEL (BIT(7)) +#define GPIO_SIG116_IN_SEL_M (GPIO_SIG116_IN_SEL_V << GPIO_SIG116_IN_SEL_S) +#define GPIO_SIG116_IN_SEL_V 0x00000001U +#define GPIO_SIG116_IN_SEL_S 7 + +/** GPIO_FUNC117_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x328) +/** GPIO_FUNC117_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC117_IN_SEL 0x0000003FU +#define GPIO_FUNC117_IN_SEL_M (GPIO_FUNC117_IN_SEL_V << GPIO_FUNC117_IN_SEL_S) +#define GPIO_FUNC117_IN_SEL_V 0x0000003FU +#define GPIO_FUNC117_IN_SEL_S 0 +/** GPIO_FUNC117_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC117_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC117_IN_INV_SEL_M (GPIO_FUNC117_IN_INV_SEL_V << GPIO_FUNC117_IN_INV_SEL_S) +#define GPIO_FUNC117_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC117_IN_INV_SEL_S 6 +/** GPIO_SIG117_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG117_IN_SEL (BIT(7)) +#define GPIO_SIG117_IN_SEL_M (GPIO_SIG117_IN_SEL_V << GPIO_SIG117_IN_SEL_S) +#define GPIO_SIG117_IN_SEL_V 0x00000001U +#define GPIO_SIG117_IN_SEL_S 7 + +/** GPIO_FUNC118_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32c) +/** GPIO_FUNC118_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC118_IN_SEL 0x0000003FU +#define GPIO_FUNC118_IN_SEL_M (GPIO_FUNC118_IN_SEL_V << GPIO_FUNC118_IN_SEL_S) +#define GPIO_FUNC118_IN_SEL_V 0x0000003FU +#define GPIO_FUNC118_IN_SEL_S 0 +/** GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC118_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC118_IN_INV_SEL_M (GPIO_FUNC118_IN_INV_SEL_V << GPIO_FUNC118_IN_INV_SEL_S) +#define GPIO_FUNC118_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC118_IN_INV_SEL_S 6 +/** GPIO_SIG118_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG118_IN_SEL (BIT(7)) +#define GPIO_SIG118_IN_SEL_M (GPIO_SIG118_IN_SEL_V << GPIO_SIG118_IN_SEL_S) +#define GPIO_SIG118_IN_SEL_V 0x00000001U +#define GPIO_SIG118_IN_SEL_S 7 + +/** GPIO_FUNC119_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330) +/** GPIO_FUNC119_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC119_IN_SEL 0x0000003FU +#define GPIO_FUNC119_IN_SEL_M (GPIO_FUNC119_IN_SEL_V << GPIO_FUNC119_IN_SEL_S) +#define GPIO_FUNC119_IN_SEL_V 0x0000003FU +#define GPIO_FUNC119_IN_SEL_S 0 +/** GPIO_FUNC119_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC119_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC119_IN_INV_SEL_M (GPIO_FUNC119_IN_INV_SEL_V << GPIO_FUNC119_IN_INV_SEL_S) +#define GPIO_FUNC119_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC119_IN_INV_SEL_S 6 +/** GPIO_SIG119_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG119_IN_SEL (BIT(7)) +#define GPIO_SIG119_IN_SEL_M (GPIO_SIG119_IN_SEL_V << GPIO_SIG119_IN_SEL_S) +#define GPIO_SIG119_IN_SEL_V 0x00000001U +#define GPIO_SIG119_IN_SEL_S 7 + +/** GPIO_FUNC120_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334) +/** GPIO_FUNC120_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC120_IN_SEL 0x0000003FU +#define GPIO_FUNC120_IN_SEL_M (GPIO_FUNC120_IN_SEL_V << GPIO_FUNC120_IN_SEL_S) +#define GPIO_FUNC120_IN_SEL_V 0x0000003FU +#define GPIO_FUNC120_IN_SEL_S 0 +/** GPIO_FUNC120_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC120_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC120_IN_INV_SEL_M (GPIO_FUNC120_IN_INV_SEL_V << GPIO_FUNC120_IN_INV_SEL_S) +#define GPIO_FUNC120_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC120_IN_INV_SEL_S 6 +/** GPIO_SIG120_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG120_IN_SEL (BIT(7)) +#define GPIO_SIG120_IN_SEL_M (GPIO_SIG120_IN_SEL_V << GPIO_SIG120_IN_SEL_S) +#define GPIO_SIG120_IN_SEL_V 0x00000001U +#define GPIO_SIG120_IN_SEL_S 7 + +/** GPIO_FUNC121_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338) +/** GPIO_FUNC121_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC121_IN_SEL 0x0000003FU +#define GPIO_FUNC121_IN_SEL_M (GPIO_FUNC121_IN_SEL_V << GPIO_FUNC121_IN_SEL_S) +#define GPIO_FUNC121_IN_SEL_V 0x0000003FU +#define GPIO_FUNC121_IN_SEL_S 0 +/** GPIO_FUNC121_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC121_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC121_IN_INV_SEL_M (GPIO_FUNC121_IN_INV_SEL_V << GPIO_FUNC121_IN_INV_SEL_S) +#define GPIO_FUNC121_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC121_IN_INV_SEL_S 6 +/** GPIO_SIG121_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG121_IN_SEL (BIT(7)) +#define GPIO_SIG121_IN_SEL_M (GPIO_SIG121_IN_SEL_V << GPIO_SIG121_IN_SEL_S) +#define GPIO_SIG121_IN_SEL_V 0x00000001U +#define GPIO_SIG121_IN_SEL_S 7 + +/** GPIO_FUNC122_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33c) +/** GPIO_FUNC122_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC122_IN_SEL 0x0000003FU +#define GPIO_FUNC122_IN_SEL_M (GPIO_FUNC122_IN_SEL_V << GPIO_FUNC122_IN_SEL_S) +#define GPIO_FUNC122_IN_SEL_V 0x0000003FU +#define GPIO_FUNC122_IN_SEL_S 0 +/** GPIO_FUNC122_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC122_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC122_IN_INV_SEL_M (GPIO_FUNC122_IN_INV_SEL_V << GPIO_FUNC122_IN_INV_SEL_S) +#define GPIO_FUNC122_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC122_IN_INV_SEL_S 6 +/** GPIO_SIG122_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG122_IN_SEL (BIT(7)) +#define GPIO_SIG122_IN_SEL_M (GPIO_SIG122_IN_SEL_V << GPIO_SIG122_IN_SEL_S) +#define GPIO_SIG122_IN_SEL_V 0x00000001U +#define GPIO_SIG122_IN_SEL_S 7 + +/** GPIO_FUNC123_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) +/** GPIO_FUNC123_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC123_IN_SEL 0x0000003FU +#define GPIO_FUNC123_IN_SEL_M (GPIO_FUNC123_IN_SEL_V << GPIO_FUNC123_IN_SEL_S) +#define GPIO_FUNC123_IN_SEL_V 0x0000003FU +#define GPIO_FUNC123_IN_SEL_S 0 +/** GPIO_FUNC123_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC123_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC123_IN_INV_SEL_M (GPIO_FUNC123_IN_INV_SEL_V << GPIO_FUNC123_IN_INV_SEL_S) +#define GPIO_FUNC123_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC123_IN_INV_SEL_S 6 +/** GPIO_SIG123_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG123_IN_SEL (BIT(7)) +#define GPIO_SIG123_IN_SEL_M (GPIO_SIG123_IN_SEL_V << GPIO_SIG123_IN_SEL_S) +#define GPIO_SIG123_IN_SEL_V 0x00000001U +#define GPIO_SIG123_IN_SEL_S 7 + +/** GPIO_FUNC124_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) +/** GPIO_FUNC124_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC124_IN_SEL 0x0000003FU +#define GPIO_FUNC124_IN_SEL_M (GPIO_FUNC124_IN_SEL_V << GPIO_FUNC124_IN_SEL_S) +#define GPIO_FUNC124_IN_SEL_V 0x0000003FU +#define GPIO_FUNC124_IN_SEL_S 0 +/** GPIO_FUNC124_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC124_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC124_IN_INV_SEL_M (GPIO_FUNC124_IN_INV_SEL_V << GPIO_FUNC124_IN_INV_SEL_S) +#define GPIO_FUNC124_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC124_IN_INV_SEL_S 6 +/** GPIO_SIG124_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG124_IN_SEL (BIT(7)) +#define GPIO_SIG124_IN_SEL_M (GPIO_SIG124_IN_SEL_V << GPIO_SIG124_IN_SEL_S) +#define GPIO_SIG124_IN_SEL_V 0x00000001U +#define GPIO_SIG124_IN_SEL_S 7 + +/** GPIO_FUNC0_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554) +/** GPIO_FUNC0_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC0_OUT_SEL 0x000000FFU +#define GPIO_FUNC0_OUT_SEL_M (GPIO_FUNC0_OUT_SEL_V << GPIO_FUNC0_OUT_SEL_S) +#define GPIO_FUNC0_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC0_OUT_SEL_S 0 +/** GPIO_FUNC0_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC0_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC0_OUT_INV_SEL_M (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S) +#define GPIO_FUNC0_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC0_OUT_INV_SEL_S 8 +/** GPIO_FUNC0_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC0_OEN_SEL (BIT(9)) +#define GPIO_FUNC0_OEN_SEL_M (GPIO_FUNC0_OEN_SEL_V << GPIO_FUNC0_OEN_SEL_S) +#define GPIO_FUNC0_OEN_SEL_V 0x00000001U +#define GPIO_FUNC0_OEN_SEL_S 9 +/** GPIO_FUNC0_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC0_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC0_OEN_INV_SEL_M (GPIO_FUNC0_OEN_INV_SEL_V << GPIO_FUNC0_OEN_INV_SEL_S) +#define GPIO_FUNC0_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC0_OEN_INV_SEL_S 10 + +/** GPIO_FUNC1_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558) +/** GPIO_FUNC1_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC1_OUT_SEL 0x000000FFU +#define GPIO_FUNC1_OUT_SEL_M (GPIO_FUNC1_OUT_SEL_V << GPIO_FUNC1_OUT_SEL_S) +#define GPIO_FUNC1_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC1_OUT_SEL_S 0 +/** GPIO_FUNC1_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC1_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC1_OUT_INV_SEL_M (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S) +#define GPIO_FUNC1_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC1_OUT_INV_SEL_S 8 +/** GPIO_FUNC1_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC1_OEN_SEL (BIT(9)) +#define GPIO_FUNC1_OEN_SEL_M (GPIO_FUNC1_OEN_SEL_V << GPIO_FUNC1_OEN_SEL_S) +#define GPIO_FUNC1_OEN_SEL_V 0x00000001U +#define GPIO_FUNC1_OEN_SEL_S 9 +/** GPIO_FUNC1_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC1_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC1_OEN_INV_SEL_M (GPIO_FUNC1_OEN_INV_SEL_V << GPIO_FUNC1_OEN_INV_SEL_S) +#define GPIO_FUNC1_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC1_OEN_INV_SEL_S 10 + +/** GPIO_FUNC2_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55c) +/** GPIO_FUNC2_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC2_OUT_SEL 0x000000FFU +#define GPIO_FUNC2_OUT_SEL_M (GPIO_FUNC2_OUT_SEL_V << GPIO_FUNC2_OUT_SEL_S) +#define GPIO_FUNC2_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC2_OUT_SEL_S 0 +/** GPIO_FUNC2_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC2_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC2_OUT_INV_SEL_M (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S) +#define GPIO_FUNC2_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC2_OUT_INV_SEL_S 8 +/** GPIO_FUNC2_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC2_OEN_SEL (BIT(9)) +#define GPIO_FUNC2_OEN_SEL_M (GPIO_FUNC2_OEN_SEL_V << GPIO_FUNC2_OEN_SEL_S) +#define GPIO_FUNC2_OEN_SEL_V 0x00000001U +#define GPIO_FUNC2_OEN_SEL_S 9 +/** GPIO_FUNC2_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC2_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC2_OEN_INV_SEL_M (GPIO_FUNC2_OEN_INV_SEL_V << GPIO_FUNC2_OEN_INV_SEL_S) +#define GPIO_FUNC2_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC2_OEN_INV_SEL_S 10 + +/** GPIO_FUNC3_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560) +/** GPIO_FUNC3_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC3_OUT_SEL 0x000000FFU +#define GPIO_FUNC3_OUT_SEL_M (GPIO_FUNC3_OUT_SEL_V << GPIO_FUNC3_OUT_SEL_S) +#define GPIO_FUNC3_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC3_OUT_SEL_S 0 +/** GPIO_FUNC3_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC3_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC3_OUT_INV_SEL_M (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S) +#define GPIO_FUNC3_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC3_OUT_INV_SEL_S 8 +/** GPIO_FUNC3_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC3_OEN_SEL (BIT(9)) +#define GPIO_FUNC3_OEN_SEL_M (GPIO_FUNC3_OEN_SEL_V << GPIO_FUNC3_OEN_SEL_S) +#define GPIO_FUNC3_OEN_SEL_V 0x00000001U +#define GPIO_FUNC3_OEN_SEL_S 9 +/** GPIO_FUNC3_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC3_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC3_OEN_INV_SEL_M (GPIO_FUNC3_OEN_INV_SEL_V << GPIO_FUNC3_OEN_INV_SEL_S) +#define GPIO_FUNC3_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC3_OEN_INV_SEL_S 10 + +/** GPIO_FUNC4_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564) +/** GPIO_FUNC4_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC4_OUT_SEL 0x000000FFU +#define GPIO_FUNC4_OUT_SEL_M (GPIO_FUNC4_OUT_SEL_V << GPIO_FUNC4_OUT_SEL_S) +#define GPIO_FUNC4_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC4_OUT_SEL_S 0 +/** GPIO_FUNC4_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC4_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC4_OUT_INV_SEL_M (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S) +#define GPIO_FUNC4_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC4_OUT_INV_SEL_S 8 +/** GPIO_FUNC4_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC4_OEN_SEL (BIT(9)) +#define GPIO_FUNC4_OEN_SEL_M (GPIO_FUNC4_OEN_SEL_V << GPIO_FUNC4_OEN_SEL_S) +#define GPIO_FUNC4_OEN_SEL_V 0x00000001U +#define GPIO_FUNC4_OEN_SEL_S 9 +/** GPIO_FUNC4_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC4_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC4_OEN_INV_SEL_M (GPIO_FUNC4_OEN_INV_SEL_V << GPIO_FUNC4_OEN_INV_SEL_S) +#define GPIO_FUNC4_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC4_OEN_INV_SEL_S 10 + +/** GPIO_FUNC5_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568) +/** GPIO_FUNC5_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC5_OUT_SEL 0x000000FFU +#define GPIO_FUNC5_OUT_SEL_M (GPIO_FUNC5_OUT_SEL_V << GPIO_FUNC5_OUT_SEL_S) +#define GPIO_FUNC5_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC5_OUT_SEL_S 0 +/** GPIO_FUNC5_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC5_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC5_OUT_INV_SEL_M (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S) +#define GPIO_FUNC5_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC5_OUT_INV_SEL_S 8 +/** GPIO_FUNC5_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC5_OEN_SEL (BIT(9)) +#define GPIO_FUNC5_OEN_SEL_M (GPIO_FUNC5_OEN_SEL_V << GPIO_FUNC5_OEN_SEL_S) +#define GPIO_FUNC5_OEN_SEL_V 0x00000001U +#define GPIO_FUNC5_OEN_SEL_S 9 +/** GPIO_FUNC5_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC5_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC5_OEN_INV_SEL_M (GPIO_FUNC5_OEN_INV_SEL_V << GPIO_FUNC5_OEN_INV_SEL_S) +#define GPIO_FUNC5_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC5_OEN_INV_SEL_S 10 + +/** GPIO_FUNC6_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56c) +/** GPIO_FUNC6_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC6_OUT_SEL 0x000000FFU +#define GPIO_FUNC6_OUT_SEL_M (GPIO_FUNC6_OUT_SEL_V << GPIO_FUNC6_OUT_SEL_S) +#define GPIO_FUNC6_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC6_OUT_SEL_S 0 +/** GPIO_FUNC6_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC6_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC6_OUT_INV_SEL_M (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S) +#define GPIO_FUNC6_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC6_OUT_INV_SEL_S 8 +/** GPIO_FUNC6_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC6_OEN_SEL (BIT(9)) +#define GPIO_FUNC6_OEN_SEL_M (GPIO_FUNC6_OEN_SEL_V << GPIO_FUNC6_OEN_SEL_S) +#define GPIO_FUNC6_OEN_SEL_V 0x00000001U +#define GPIO_FUNC6_OEN_SEL_S 9 +/** GPIO_FUNC6_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC6_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC6_OEN_INV_SEL_M (GPIO_FUNC6_OEN_INV_SEL_V << GPIO_FUNC6_OEN_INV_SEL_S) +#define GPIO_FUNC6_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC6_OEN_INV_SEL_S 10 + +/** GPIO_FUNC7_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570) +/** GPIO_FUNC7_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC7_OUT_SEL 0x000000FFU +#define GPIO_FUNC7_OUT_SEL_M (GPIO_FUNC7_OUT_SEL_V << GPIO_FUNC7_OUT_SEL_S) +#define GPIO_FUNC7_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC7_OUT_SEL_S 0 +/** GPIO_FUNC7_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC7_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC7_OUT_INV_SEL_M (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S) +#define GPIO_FUNC7_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC7_OUT_INV_SEL_S 8 +/** GPIO_FUNC7_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC7_OEN_SEL (BIT(9)) +#define GPIO_FUNC7_OEN_SEL_M (GPIO_FUNC7_OEN_SEL_V << GPIO_FUNC7_OEN_SEL_S) +#define GPIO_FUNC7_OEN_SEL_V 0x00000001U +#define GPIO_FUNC7_OEN_SEL_S 9 +/** GPIO_FUNC7_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC7_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC7_OEN_INV_SEL_M (GPIO_FUNC7_OEN_INV_SEL_V << GPIO_FUNC7_OEN_INV_SEL_S) +#define GPIO_FUNC7_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC7_OEN_INV_SEL_S 10 + +/** GPIO_FUNC8_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574) +/** GPIO_FUNC8_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC8_OUT_SEL 0x000000FFU +#define GPIO_FUNC8_OUT_SEL_M (GPIO_FUNC8_OUT_SEL_V << GPIO_FUNC8_OUT_SEL_S) +#define GPIO_FUNC8_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC8_OUT_SEL_S 0 +/** GPIO_FUNC8_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC8_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC8_OUT_INV_SEL_M (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S) +#define GPIO_FUNC8_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC8_OUT_INV_SEL_S 8 +/** GPIO_FUNC8_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC8_OEN_SEL (BIT(9)) +#define GPIO_FUNC8_OEN_SEL_M (GPIO_FUNC8_OEN_SEL_V << GPIO_FUNC8_OEN_SEL_S) +#define GPIO_FUNC8_OEN_SEL_V 0x00000001U +#define GPIO_FUNC8_OEN_SEL_S 9 +/** GPIO_FUNC8_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC8_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC8_OEN_INV_SEL_M (GPIO_FUNC8_OEN_INV_SEL_V << GPIO_FUNC8_OEN_INV_SEL_S) +#define GPIO_FUNC8_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC8_OEN_INV_SEL_S 10 + +/** GPIO_FUNC9_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578) +/** GPIO_FUNC9_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC9_OUT_SEL 0x000000FFU +#define GPIO_FUNC9_OUT_SEL_M (GPIO_FUNC9_OUT_SEL_V << GPIO_FUNC9_OUT_SEL_S) +#define GPIO_FUNC9_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC9_OUT_SEL_S 0 +/** GPIO_FUNC9_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC9_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC9_OUT_INV_SEL_M (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S) +#define GPIO_FUNC9_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC9_OUT_INV_SEL_S 8 +/** GPIO_FUNC9_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC9_OEN_SEL (BIT(9)) +#define GPIO_FUNC9_OEN_SEL_M (GPIO_FUNC9_OEN_SEL_V << GPIO_FUNC9_OEN_SEL_S) +#define GPIO_FUNC9_OEN_SEL_V 0x00000001U +#define GPIO_FUNC9_OEN_SEL_S 9 +/** GPIO_FUNC9_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC9_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC9_OEN_INV_SEL_M (GPIO_FUNC9_OEN_INV_SEL_V << GPIO_FUNC9_OEN_INV_SEL_S) +#define GPIO_FUNC9_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC9_OEN_INV_SEL_S 10 + +/** GPIO_FUNC10_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57c) +/** GPIO_FUNC10_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC10_OUT_SEL 0x000000FFU +#define GPIO_FUNC10_OUT_SEL_M (GPIO_FUNC10_OUT_SEL_V << GPIO_FUNC10_OUT_SEL_S) +#define GPIO_FUNC10_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC10_OUT_SEL_S 0 +/** GPIO_FUNC10_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC10_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC10_OUT_INV_SEL_M (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S) +#define GPIO_FUNC10_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC10_OUT_INV_SEL_S 8 +/** GPIO_FUNC10_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC10_OEN_SEL (BIT(9)) +#define GPIO_FUNC10_OEN_SEL_M (GPIO_FUNC10_OEN_SEL_V << GPIO_FUNC10_OEN_SEL_S) +#define GPIO_FUNC10_OEN_SEL_V 0x00000001U +#define GPIO_FUNC10_OEN_SEL_S 9 +/** GPIO_FUNC10_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC10_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC10_OEN_INV_SEL_M (GPIO_FUNC10_OEN_INV_SEL_V << GPIO_FUNC10_OEN_INV_SEL_S) +#define GPIO_FUNC10_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC10_OEN_INV_SEL_S 10 + +/** GPIO_FUNC11_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580) +/** GPIO_FUNC11_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC11_OUT_SEL 0x000000FFU +#define GPIO_FUNC11_OUT_SEL_M (GPIO_FUNC11_OUT_SEL_V << GPIO_FUNC11_OUT_SEL_S) +#define GPIO_FUNC11_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC11_OUT_SEL_S 0 +/** GPIO_FUNC11_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC11_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC11_OUT_INV_SEL_M (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S) +#define GPIO_FUNC11_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC11_OUT_INV_SEL_S 8 +/** GPIO_FUNC11_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC11_OEN_SEL (BIT(9)) +#define GPIO_FUNC11_OEN_SEL_M (GPIO_FUNC11_OEN_SEL_V << GPIO_FUNC11_OEN_SEL_S) +#define GPIO_FUNC11_OEN_SEL_V 0x00000001U +#define GPIO_FUNC11_OEN_SEL_S 9 +/** GPIO_FUNC11_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC11_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC11_OEN_INV_SEL_M (GPIO_FUNC11_OEN_INV_SEL_V << GPIO_FUNC11_OEN_INV_SEL_S) +#define GPIO_FUNC11_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC11_OEN_INV_SEL_S 10 + +/** GPIO_FUNC12_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584) +/** GPIO_FUNC12_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC12_OUT_SEL 0x000000FFU +#define GPIO_FUNC12_OUT_SEL_M (GPIO_FUNC12_OUT_SEL_V << GPIO_FUNC12_OUT_SEL_S) +#define GPIO_FUNC12_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC12_OUT_SEL_S 0 +/** GPIO_FUNC12_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC12_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC12_OUT_INV_SEL_M (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S) +#define GPIO_FUNC12_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC12_OUT_INV_SEL_S 8 +/** GPIO_FUNC12_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC12_OEN_SEL (BIT(9)) +#define GPIO_FUNC12_OEN_SEL_M (GPIO_FUNC12_OEN_SEL_V << GPIO_FUNC12_OEN_SEL_S) +#define GPIO_FUNC12_OEN_SEL_V 0x00000001U +#define GPIO_FUNC12_OEN_SEL_S 9 +/** GPIO_FUNC12_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC12_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC12_OEN_INV_SEL_M (GPIO_FUNC12_OEN_INV_SEL_V << GPIO_FUNC12_OEN_INV_SEL_S) +#define GPIO_FUNC12_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC12_OEN_INV_SEL_S 10 + +/** GPIO_FUNC13_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588) +/** GPIO_FUNC13_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC13_OUT_SEL 0x000000FFU +#define GPIO_FUNC13_OUT_SEL_M (GPIO_FUNC13_OUT_SEL_V << GPIO_FUNC13_OUT_SEL_S) +#define GPIO_FUNC13_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC13_OUT_SEL_S 0 +/** GPIO_FUNC13_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC13_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC13_OUT_INV_SEL_M (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S) +#define GPIO_FUNC13_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC13_OUT_INV_SEL_S 8 +/** GPIO_FUNC13_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC13_OEN_SEL (BIT(9)) +#define GPIO_FUNC13_OEN_SEL_M (GPIO_FUNC13_OEN_SEL_V << GPIO_FUNC13_OEN_SEL_S) +#define GPIO_FUNC13_OEN_SEL_V 0x00000001U +#define GPIO_FUNC13_OEN_SEL_S 9 +/** GPIO_FUNC13_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC13_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC13_OEN_INV_SEL_M (GPIO_FUNC13_OEN_INV_SEL_V << GPIO_FUNC13_OEN_INV_SEL_S) +#define GPIO_FUNC13_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC13_OEN_INV_SEL_S 10 + +/** GPIO_FUNC14_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58c) +/** GPIO_FUNC14_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC14_OUT_SEL 0x000000FFU +#define GPIO_FUNC14_OUT_SEL_M (GPIO_FUNC14_OUT_SEL_V << GPIO_FUNC14_OUT_SEL_S) +#define GPIO_FUNC14_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC14_OUT_SEL_S 0 +/** GPIO_FUNC14_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC14_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC14_OUT_INV_SEL_M (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S) +#define GPIO_FUNC14_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC14_OUT_INV_SEL_S 8 +/** GPIO_FUNC14_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC14_OEN_SEL (BIT(9)) +#define GPIO_FUNC14_OEN_SEL_M (GPIO_FUNC14_OEN_SEL_V << GPIO_FUNC14_OEN_SEL_S) +#define GPIO_FUNC14_OEN_SEL_V 0x00000001U +#define GPIO_FUNC14_OEN_SEL_S 9 +/** GPIO_FUNC14_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC14_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC14_OEN_INV_SEL_M (GPIO_FUNC14_OEN_INV_SEL_V << GPIO_FUNC14_OEN_INV_SEL_S) +#define GPIO_FUNC14_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC14_OEN_INV_SEL_S 10 + +/** GPIO_FUNC15_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590) +/** GPIO_FUNC15_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC15_OUT_SEL 0x000000FFU +#define GPIO_FUNC15_OUT_SEL_M (GPIO_FUNC15_OUT_SEL_V << GPIO_FUNC15_OUT_SEL_S) +#define GPIO_FUNC15_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC15_OUT_SEL_S 0 +/** GPIO_FUNC15_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC15_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC15_OUT_INV_SEL_M (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S) +#define GPIO_FUNC15_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC15_OUT_INV_SEL_S 8 +/** GPIO_FUNC15_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC15_OEN_SEL (BIT(9)) +#define GPIO_FUNC15_OEN_SEL_M (GPIO_FUNC15_OEN_SEL_V << GPIO_FUNC15_OEN_SEL_S) +#define GPIO_FUNC15_OEN_SEL_V 0x00000001U +#define GPIO_FUNC15_OEN_SEL_S 9 +/** GPIO_FUNC15_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC15_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC15_OEN_INV_SEL_M (GPIO_FUNC15_OEN_INV_SEL_V << GPIO_FUNC15_OEN_INV_SEL_S) +#define GPIO_FUNC15_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC15_OEN_INV_SEL_S 10 + +/** GPIO_FUNC16_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594) +/** GPIO_FUNC16_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC16_OUT_SEL 0x000000FFU +#define GPIO_FUNC16_OUT_SEL_M (GPIO_FUNC16_OUT_SEL_V << GPIO_FUNC16_OUT_SEL_S) +#define GPIO_FUNC16_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC16_OUT_SEL_S 0 +/** GPIO_FUNC16_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC16_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC16_OUT_INV_SEL_M (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S) +#define GPIO_FUNC16_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC16_OUT_INV_SEL_S 8 +/** GPIO_FUNC16_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC16_OEN_SEL (BIT(9)) +#define GPIO_FUNC16_OEN_SEL_M (GPIO_FUNC16_OEN_SEL_V << GPIO_FUNC16_OEN_SEL_S) +#define GPIO_FUNC16_OEN_SEL_V 0x00000001U +#define GPIO_FUNC16_OEN_SEL_S 9 +/** GPIO_FUNC16_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC16_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC16_OEN_INV_SEL_M (GPIO_FUNC16_OEN_INV_SEL_V << GPIO_FUNC16_OEN_INV_SEL_S) +#define GPIO_FUNC16_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC16_OEN_INV_SEL_S 10 + +/** GPIO_FUNC17_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598) +/** GPIO_FUNC17_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC17_OUT_SEL 0x000000FFU +#define GPIO_FUNC17_OUT_SEL_M (GPIO_FUNC17_OUT_SEL_V << GPIO_FUNC17_OUT_SEL_S) +#define GPIO_FUNC17_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC17_OUT_SEL_S 0 +/** GPIO_FUNC17_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC17_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC17_OUT_INV_SEL_M (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S) +#define GPIO_FUNC17_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC17_OUT_INV_SEL_S 8 +/** GPIO_FUNC17_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC17_OEN_SEL (BIT(9)) +#define GPIO_FUNC17_OEN_SEL_M (GPIO_FUNC17_OEN_SEL_V << GPIO_FUNC17_OEN_SEL_S) +#define GPIO_FUNC17_OEN_SEL_V 0x00000001U +#define GPIO_FUNC17_OEN_SEL_S 9 +/** GPIO_FUNC17_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC17_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC17_OEN_INV_SEL_M (GPIO_FUNC17_OEN_INV_SEL_V << GPIO_FUNC17_OEN_INV_SEL_S) +#define GPIO_FUNC17_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC17_OEN_INV_SEL_S 10 + +/** GPIO_FUNC18_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59c) +/** GPIO_FUNC18_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC18_OUT_SEL 0x000000FFU +#define GPIO_FUNC18_OUT_SEL_M (GPIO_FUNC18_OUT_SEL_V << GPIO_FUNC18_OUT_SEL_S) +#define GPIO_FUNC18_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC18_OUT_SEL_S 0 +/** GPIO_FUNC18_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC18_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC18_OUT_INV_SEL_M (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S) +#define GPIO_FUNC18_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC18_OUT_INV_SEL_S 8 +/** GPIO_FUNC18_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC18_OEN_SEL (BIT(9)) +#define GPIO_FUNC18_OEN_SEL_M (GPIO_FUNC18_OEN_SEL_V << GPIO_FUNC18_OEN_SEL_S) +#define GPIO_FUNC18_OEN_SEL_V 0x00000001U +#define GPIO_FUNC18_OEN_SEL_S 9 +/** GPIO_FUNC18_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC18_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC18_OEN_INV_SEL_M (GPIO_FUNC18_OEN_INV_SEL_V << GPIO_FUNC18_OEN_INV_SEL_S) +#define GPIO_FUNC18_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC18_OEN_INV_SEL_S 10 + +/** GPIO_FUNC19_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a0) +/** GPIO_FUNC19_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC19_OUT_SEL 0x000000FFU +#define GPIO_FUNC19_OUT_SEL_M (GPIO_FUNC19_OUT_SEL_V << GPIO_FUNC19_OUT_SEL_S) +#define GPIO_FUNC19_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC19_OUT_SEL_S 0 +/** GPIO_FUNC19_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC19_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC19_OUT_INV_SEL_M (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S) +#define GPIO_FUNC19_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC19_OUT_INV_SEL_S 8 +/** GPIO_FUNC19_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC19_OEN_SEL (BIT(9)) +#define GPIO_FUNC19_OEN_SEL_M (GPIO_FUNC19_OEN_SEL_V << GPIO_FUNC19_OEN_SEL_S) +#define GPIO_FUNC19_OEN_SEL_V 0x00000001U +#define GPIO_FUNC19_OEN_SEL_S 9 +/** GPIO_FUNC19_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC19_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC19_OEN_INV_SEL_M (GPIO_FUNC19_OEN_INV_SEL_V << GPIO_FUNC19_OEN_INV_SEL_S) +#define GPIO_FUNC19_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC19_OEN_INV_SEL_S 10 + +/** GPIO_FUNC20_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a4) +/** GPIO_FUNC20_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC20_OUT_SEL 0x000000FFU +#define GPIO_FUNC20_OUT_SEL_M (GPIO_FUNC20_OUT_SEL_V << GPIO_FUNC20_OUT_SEL_S) +#define GPIO_FUNC20_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC20_OUT_SEL_S 0 +/** GPIO_FUNC20_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC20_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC20_OUT_INV_SEL_M (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S) +#define GPIO_FUNC20_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC20_OUT_INV_SEL_S 8 +/** GPIO_FUNC20_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC20_OEN_SEL (BIT(9)) +#define GPIO_FUNC20_OEN_SEL_M (GPIO_FUNC20_OEN_SEL_V << GPIO_FUNC20_OEN_SEL_S) +#define GPIO_FUNC20_OEN_SEL_V 0x00000001U +#define GPIO_FUNC20_OEN_SEL_S 9 +/** GPIO_FUNC20_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC20_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC20_OEN_INV_SEL_M (GPIO_FUNC20_OEN_INV_SEL_V << GPIO_FUNC20_OEN_INV_SEL_S) +#define GPIO_FUNC20_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC20_OEN_INV_SEL_S 10 + +/** GPIO_FUNC21_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a8) +/** GPIO_FUNC21_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC21_OUT_SEL 0x000000FFU +#define GPIO_FUNC21_OUT_SEL_M (GPIO_FUNC21_OUT_SEL_V << GPIO_FUNC21_OUT_SEL_S) +#define GPIO_FUNC21_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC21_OUT_SEL_S 0 +/** GPIO_FUNC21_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC21_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC21_OUT_INV_SEL_M (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S) +#define GPIO_FUNC21_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC21_OUT_INV_SEL_S 8 +/** GPIO_FUNC21_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC21_OEN_SEL (BIT(9)) +#define GPIO_FUNC21_OEN_SEL_M (GPIO_FUNC21_OEN_SEL_V << GPIO_FUNC21_OEN_SEL_S) +#define GPIO_FUNC21_OEN_SEL_V 0x00000001U +#define GPIO_FUNC21_OEN_SEL_S 9 +/** GPIO_FUNC21_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC21_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC21_OEN_INV_SEL_M (GPIO_FUNC21_OEN_INV_SEL_V << GPIO_FUNC21_OEN_INV_SEL_S) +#define GPIO_FUNC21_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC21_OEN_INV_SEL_S 10 + +/** GPIO_FUNC22_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ac) +/** GPIO_FUNC22_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC22_OUT_SEL 0x000000FFU +#define GPIO_FUNC22_OUT_SEL_M (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S) +#define GPIO_FUNC22_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC22_OUT_SEL_S 0 +/** GPIO_FUNC22_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC22_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC22_OUT_INV_SEL_M (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S) +#define GPIO_FUNC22_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC22_OUT_INV_SEL_S 8 +/** GPIO_FUNC22_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC22_OEN_SEL (BIT(9)) +#define GPIO_FUNC22_OEN_SEL_M (GPIO_FUNC22_OEN_SEL_V << GPIO_FUNC22_OEN_SEL_S) +#define GPIO_FUNC22_OEN_SEL_V 0x00000001U +#define GPIO_FUNC22_OEN_SEL_S 9 +/** GPIO_FUNC22_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC22_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC22_OEN_INV_SEL_M (GPIO_FUNC22_OEN_INV_SEL_V << GPIO_FUNC22_OEN_INV_SEL_S) +#define GPIO_FUNC22_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC22_OEN_INV_SEL_S 10 + +/** GPIO_FUNC23_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b0) +/** GPIO_FUNC23_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC23_OUT_SEL 0x000000FFU +#define GPIO_FUNC23_OUT_SEL_M (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S) +#define GPIO_FUNC23_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC23_OUT_SEL_S 0 +/** GPIO_FUNC23_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC23_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC23_OUT_INV_SEL_M (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S) +#define GPIO_FUNC23_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC23_OUT_INV_SEL_S 8 +/** GPIO_FUNC23_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC23_OEN_SEL (BIT(9)) +#define GPIO_FUNC23_OEN_SEL_M (GPIO_FUNC23_OEN_SEL_V << GPIO_FUNC23_OEN_SEL_S) +#define GPIO_FUNC23_OEN_SEL_V 0x00000001U +#define GPIO_FUNC23_OEN_SEL_S 9 +/** GPIO_FUNC23_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC23_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC23_OEN_INV_SEL_M (GPIO_FUNC23_OEN_INV_SEL_V << GPIO_FUNC23_OEN_INV_SEL_S) +#define GPIO_FUNC23_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC23_OEN_INV_SEL_S 10 + +/** GPIO_FUNC24_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b4) +/** GPIO_FUNC24_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC24_OUT_SEL 0x000000FFU +#define GPIO_FUNC24_OUT_SEL_M (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S) +#define GPIO_FUNC24_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC24_OUT_SEL_S 0 +/** GPIO_FUNC24_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC24_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC24_OUT_INV_SEL_M (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S) +#define GPIO_FUNC24_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC24_OUT_INV_SEL_S 8 +/** GPIO_FUNC24_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC24_OEN_SEL (BIT(9)) +#define GPIO_FUNC24_OEN_SEL_M (GPIO_FUNC24_OEN_SEL_V << GPIO_FUNC24_OEN_SEL_S) +#define GPIO_FUNC24_OEN_SEL_V 0x00000001U +#define GPIO_FUNC24_OEN_SEL_S 9 +/** GPIO_FUNC24_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC24_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC24_OEN_INV_SEL_M (GPIO_FUNC24_OEN_INV_SEL_V << GPIO_FUNC24_OEN_INV_SEL_S) +#define GPIO_FUNC24_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC24_OEN_INV_SEL_S 10 + +/** GPIO_FUNC25_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b8) +/** GPIO_FUNC25_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC25_OUT_SEL 0x000000FFU +#define GPIO_FUNC25_OUT_SEL_M (GPIO_FUNC25_OUT_SEL_V << GPIO_FUNC25_OUT_SEL_S) +#define GPIO_FUNC25_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC25_OUT_SEL_S 0 +/** GPIO_FUNC25_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC25_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC25_OUT_INV_SEL_M (GPIO_FUNC25_OUT_INV_SEL_V << GPIO_FUNC25_OUT_INV_SEL_S) +#define GPIO_FUNC25_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC25_OUT_INV_SEL_S 8 +/** GPIO_FUNC25_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC25_OEN_SEL (BIT(9)) +#define GPIO_FUNC25_OEN_SEL_M (GPIO_FUNC25_OEN_SEL_V << GPIO_FUNC25_OEN_SEL_S) +#define GPIO_FUNC25_OEN_SEL_V 0x00000001U +#define GPIO_FUNC25_OEN_SEL_S 9 +/** GPIO_FUNC25_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC25_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC25_OEN_INV_SEL_M (GPIO_FUNC25_OEN_INV_SEL_V << GPIO_FUNC25_OEN_INV_SEL_S) +#define GPIO_FUNC25_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC25_OEN_INV_SEL_S 10 + +/** GPIO_FUNC26_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5bc) +/** GPIO_FUNC26_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC26_OUT_SEL 0x000000FFU +#define GPIO_FUNC26_OUT_SEL_M (GPIO_FUNC26_OUT_SEL_V << GPIO_FUNC26_OUT_SEL_S) +#define GPIO_FUNC26_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC26_OUT_SEL_S 0 +/** GPIO_FUNC26_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC26_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC26_OUT_INV_SEL_M (GPIO_FUNC26_OUT_INV_SEL_V << GPIO_FUNC26_OUT_INV_SEL_S) +#define GPIO_FUNC26_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC26_OUT_INV_SEL_S 8 +/** GPIO_FUNC26_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC26_OEN_SEL (BIT(9)) +#define GPIO_FUNC26_OEN_SEL_M (GPIO_FUNC26_OEN_SEL_V << GPIO_FUNC26_OEN_SEL_S) +#define GPIO_FUNC26_OEN_SEL_V 0x00000001U +#define GPIO_FUNC26_OEN_SEL_S 9 +/** GPIO_FUNC26_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC26_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC26_OEN_INV_SEL_M (GPIO_FUNC26_OEN_INV_SEL_V << GPIO_FUNC26_OEN_INV_SEL_S) +#define GPIO_FUNC26_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC26_OEN_INV_SEL_S 10 + +/** GPIO_FUNC27_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c0) +/** GPIO_FUNC27_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC27_OUT_SEL 0x000000FFU +#define GPIO_FUNC27_OUT_SEL_M (GPIO_FUNC27_OUT_SEL_V << GPIO_FUNC27_OUT_SEL_S) +#define GPIO_FUNC27_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC27_OUT_SEL_S 0 +/** GPIO_FUNC27_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC27_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC27_OUT_INV_SEL_M (GPIO_FUNC27_OUT_INV_SEL_V << GPIO_FUNC27_OUT_INV_SEL_S) +#define GPIO_FUNC27_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC27_OUT_INV_SEL_S 8 +/** GPIO_FUNC27_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC27_OEN_SEL (BIT(9)) +#define GPIO_FUNC27_OEN_SEL_M (GPIO_FUNC27_OEN_SEL_V << GPIO_FUNC27_OEN_SEL_S) +#define GPIO_FUNC27_OEN_SEL_V 0x00000001U +#define GPIO_FUNC27_OEN_SEL_S 9 +/** GPIO_FUNC27_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC27_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC27_OEN_INV_SEL_M (GPIO_FUNC27_OEN_INV_SEL_V << GPIO_FUNC27_OEN_INV_SEL_S) +#define GPIO_FUNC27_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC27_OEN_INV_SEL_S 10 + +/** GPIO_FUNC28_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c4) +/** GPIO_FUNC28_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC28_OUT_SEL 0x000000FFU +#define GPIO_FUNC28_OUT_SEL_M (GPIO_FUNC28_OUT_SEL_V << GPIO_FUNC28_OUT_SEL_S) +#define GPIO_FUNC28_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC28_OUT_SEL_S 0 +/** GPIO_FUNC28_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC28_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC28_OUT_INV_SEL_M (GPIO_FUNC28_OUT_INV_SEL_V << GPIO_FUNC28_OUT_INV_SEL_S) +#define GPIO_FUNC28_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_OUT_INV_SEL_S 8 +/** GPIO_FUNC28_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC28_OEN_SEL (BIT(9)) +#define GPIO_FUNC28_OEN_SEL_M (GPIO_FUNC28_OEN_SEL_V << GPIO_FUNC28_OEN_SEL_S) +#define GPIO_FUNC28_OEN_SEL_V 0x00000001U +#define GPIO_FUNC28_OEN_SEL_S 9 +/** GPIO_FUNC28_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC28_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC28_OEN_INV_SEL_M (GPIO_FUNC28_OEN_INV_SEL_V << GPIO_FUNC28_OEN_INV_SEL_S) +#define GPIO_FUNC28_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_OEN_INV_SEL_S 10 + +/** GPIO_FUNC29_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c8) +/** GPIO_FUNC29_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC29_OUT_SEL 0x000000FFU +#define GPIO_FUNC29_OUT_SEL_M (GPIO_FUNC29_OUT_SEL_V << GPIO_FUNC29_OUT_SEL_S) +#define GPIO_FUNC29_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC29_OUT_SEL_S 0 +/** GPIO_FUNC29_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC29_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC29_OUT_INV_SEL_M (GPIO_FUNC29_OUT_INV_SEL_V << GPIO_FUNC29_OUT_INV_SEL_S) +#define GPIO_FUNC29_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC29_OUT_INV_SEL_S 8 +/** GPIO_FUNC29_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC29_OEN_SEL (BIT(9)) +#define GPIO_FUNC29_OEN_SEL_M (GPIO_FUNC29_OEN_SEL_V << GPIO_FUNC29_OEN_SEL_S) +#define GPIO_FUNC29_OEN_SEL_V 0x00000001U +#define GPIO_FUNC29_OEN_SEL_S 9 +/** GPIO_FUNC29_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC29_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC29_OEN_INV_SEL_M (GPIO_FUNC29_OEN_INV_SEL_V << GPIO_FUNC29_OEN_INV_SEL_S) +#define GPIO_FUNC29_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC29_OEN_INV_SEL_S 10 + +/** GPIO_FUNC30_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5cc) +/** GPIO_FUNC30_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC30_OUT_SEL 0x000000FFU +#define GPIO_FUNC30_OUT_SEL_M (GPIO_FUNC30_OUT_SEL_V << GPIO_FUNC30_OUT_SEL_S) +#define GPIO_FUNC30_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC30_OUT_SEL_S 0 +/** GPIO_FUNC30_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC30_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC30_OUT_INV_SEL_M (GPIO_FUNC30_OUT_INV_SEL_V << GPIO_FUNC30_OUT_INV_SEL_S) +#define GPIO_FUNC30_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC30_OUT_INV_SEL_S 8 +/** GPIO_FUNC30_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC30_OEN_SEL (BIT(9)) +#define GPIO_FUNC30_OEN_SEL_M (GPIO_FUNC30_OEN_SEL_V << GPIO_FUNC30_OEN_SEL_S) +#define GPIO_FUNC30_OEN_SEL_V 0x00000001U +#define GPIO_FUNC30_OEN_SEL_S 9 +/** GPIO_FUNC30_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC30_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC30_OEN_INV_SEL_M (GPIO_FUNC30_OEN_INV_SEL_V << GPIO_FUNC30_OEN_INV_SEL_S) +#define GPIO_FUNC30_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC30_OEN_INV_SEL_S 10 + +/** GPIO_FUNC31_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d0) +/** GPIO_FUNC31_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC31_OUT_SEL 0x000000FFU +#define GPIO_FUNC31_OUT_SEL_M (GPIO_FUNC31_OUT_SEL_V << GPIO_FUNC31_OUT_SEL_S) +#define GPIO_FUNC31_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC31_OUT_SEL_S 0 +/** GPIO_FUNC31_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC31_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC31_OUT_INV_SEL_M (GPIO_FUNC31_OUT_INV_SEL_V << GPIO_FUNC31_OUT_INV_SEL_S) +#define GPIO_FUNC31_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC31_OUT_INV_SEL_S 8 +/** GPIO_FUNC31_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC31_OEN_SEL (BIT(9)) +#define GPIO_FUNC31_OEN_SEL_M (GPIO_FUNC31_OEN_SEL_V << GPIO_FUNC31_OEN_SEL_S) +#define GPIO_FUNC31_OEN_SEL_V 0x00000001U +#define GPIO_FUNC31_OEN_SEL_S 9 +/** GPIO_FUNC31_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC31_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC31_OEN_INV_SEL_M (GPIO_FUNC31_OEN_INV_SEL_V << GPIO_FUNC31_OEN_INV_SEL_S) +#define GPIO_FUNC31_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC31_OEN_INV_SEL_S 10 + +/** GPIO_FUNC32_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC32_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d4) +/** GPIO_FUNC32_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC32_OUT_SEL 0x000000FFU +#define GPIO_FUNC32_OUT_SEL_M (GPIO_FUNC32_OUT_SEL_V << GPIO_FUNC32_OUT_SEL_S) +#define GPIO_FUNC32_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC32_OUT_SEL_S 0 +/** GPIO_FUNC32_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC32_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC32_OUT_INV_SEL_M (GPIO_FUNC32_OUT_INV_SEL_V << GPIO_FUNC32_OUT_INV_SEL_S) +#define GPIO_FUNC32_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC32_OUT_INV_SEL_S 8 +/** GPIO_FUNC32_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC32_OEN_SEL (BIT(9)) +#define GPIO_FUNC32_OEN_SEL_M (GPIO_FUNC32_OEN_SEL_V << GPIO_FUNC32_OEN_SEL_S) +#define GPIO_FUNC32_OEN_SEL_V 0x00000001U +#define GPIO_FUNC32_OEN_SEL_S 9 +/** GPIO_FUNC32_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC32_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC32_OEN_INV_SEL_M (GPIO_FUNC32_OEN_INV_SEL_V << GPIO_FUNC32_OEN_INV_SEL_S) +#define GPIO_FUNC32_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC32_OEN_INV_SEL_S 10 + +/** GPIO_FUNC33_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC33_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d8) +/** GPIO_FUNC33_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC33_OUT_SEL 0x000000FFU +#define GPIO_FUNC33_OUT_SEL_M (GPIO_FUNC33_OUT_SEL_V << GPIO_FUNC33_OUT_SEL_S) +#define GPIO_FUNC33_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC33_OUT_SEL_S 0 +/** GPIO_FUNC33_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC33_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC33_OUT_INV_SEL_M (GPIO_FUNC33_OUT_INV_SEL_V << GPIO_FUNC33_OUT_INV_SEL_S) +#define GPIO_FUNC33_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC33_OUT_INV_SEL_S 8 +/** GPIO_FUNC33_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC33_OEN_SEL (BIT(9)) +#define GPIO_FUNC33_OEN_SEL_M (GPIO_FUNC33_OEN_SEL_V << GPIO_FUNC33_OEN_SEL_S) +#define GPIO_FUNC33_OEN_SEL_V 0x00000001U +#define GPIO_FUNC33_OEN_SEL_S 9 +/** GPIO_FUNC33_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC33_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC33_OEN_INV_SEL_M (GPIO_FUNC33_OEN_INV_SEL_V << GPIO_FUNC33_OEN_INV_SEL_S) +#define GPIO_FUNC33_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC33_OEN_INV_SEL_S 10 + +/** GPIO_FUNC34_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC34_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5dc) +/** GPIO_FUNC34_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC34_OUT_SEL 0x000000FFU +#define GPIO_FUNC34_OUT_SEL_M (GPIO_FUNC34_OUT_SEL_V << GPIO_FUNC34_OUT_SEL_S) +#define GPIO_FUNC34_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC34_OUT_SEL_S 0 +/** GPIO_FUNC34_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC34_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC34_OUT_INV_SEL_M (GPIO_FUNC34_OUT_INV_SEL_V << GPIO_FUNC34_OUT_INV_SEL_S) +#define GPIO_FUNC34_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC34_OUT_INV_SEL_S 8 +/** GPIO_FUNC34_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC34_OEN_SEL (BIT(9)) +#define GPIO_FUNC34_OEN_SEL_M (GPIO_FUNC34_OEN_SEL_V << GPIO_FUNC34_OEN_SEL_S) +#define GPIO_FUNC34_OEN_SEL_V 0x00000001U +#define GPIO_FUNC34_OEN_SEL_S 9 +/** GPIO_FUNC34_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC34_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC34_OEN_INV_SEL_M (GPIO_FUNC34_OEN_INV_SEL_V << GPIO_FUNC34_OEN_INV_SEL_S) +#define GPIO_FUNC34_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC34_OEN_INV_SEL_S 10 + +/** GPIO_CLOCK_GATE_REG register + * GPIO clock gate register + */ +#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x62c) +/** GPIO_CLK_EN : R/W; bitpos: [0]; default: 1; + * set this bit to enable GPIO clock gate + */ +#define GPIO_CLK_EN (BIT(0)) +#define GPIO_CLK_EN_M (GPIO_CLK_EN_V << GPIO_CLK_EN_S) +#define GPIO_CLK_EN_V 0x00000001U +#define GPIO_CLK_EN_S 0 + +/** GPIO_DATE_REG register + * GPIO version register + */ +#define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0x6fc) +/** GPIO_DATE : R/W; bitpos: [27:0]; default: 35655968; + * version register + */ +#define GPIO_DATE 0x0FFFFFFFU +#define GPIO_DATE_M (GPIO_DATE_V << GPIO_DATE_S) +#define GPIO_DATE_V 0x0FFFFFFFU +#define GPIO_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/gpio_sig_map.h b/components/soc/esp32c6/include/soc/gpio_sig_map.h new file mode 100644 index 0000000000..57d2e8414e --- /dev/null +++ b/components/soc/esp32c6/include/soc/gpio_sig_map.h @@ -0,0 +1,257 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _SOC_GPIO_SIG_MAP_H_ +#define _SOC_GPIO_SIG_MAP_H_ + +#define EXT_ADC_START_IDX 0 +#define LEDC_LS_SIG_OUT0_IDX 0 +#define LEDC_LS_SIG_OUT1_IDX 1 +#define LEDC_LS_SIG_OUT2_IDX 2 +#define LEDC_LS_SIG_OUT3_IDX 3 +#define LEDC_LS_SIG_OUT4_IDX 4 +#define LEDC_LS_SIG_OUT5_IDX 5 +#define U0RXD_IN_IDX 6 +#define U0TXD_OUT_IDX 6 +#define U0CTS_IN_IDX 7 +#define U0RTS_OUT_IDX 7 +#define U0DSR_IN_IDX 8 +#define U0DTR_OUT_IDX 8 +#define U1RXD_IN_IDX 9 +#define U1TXD_OUT_IDX 9 +#define U1CTS_IN_IDX 10 +#define U1RTS_OUT_IDX 10 +#define U1DSR_IN_IDX 11 +#define U1DTR_OUT_IDX 11 +#define I2S_MCLK_IN_IDX 12 +#define I2S_MCLK_OUT_IDX 12 +#define I2SO_BCK_IN_IDX 13 +#define I2SO_BCK_OUT_IDX 13 +#define I2SO_WS_IN_IDX 14 +#define I2SO_WS_OUT_IDX 14 +#define I2SI_SD_IN_IDX 15 +#define I2SO_SD_OUT_IDX 15 +#define I2SI_BCK_IN_IDX 16 +#define I2SI_BCK_OUT_IDX 16 +#define I2SI_WS_IN_IDX 17 +#define I2SI_WS_OUT_IDX 17 +#define I2SO_SD1_OUT_IDX 18 +#define USB_JTAG_TDO_BRIDGE_IDX 19 +#define USB_JTAG_TRST_IDX 19 +#define CPU_TESTBUS0_IDX 20 +#define CPU_TESTBUS1_IDX 21 +#define CPU_TESTBUS2_IDX 22 +#define CPU_TESTBUS3_IDX 23 +#define CPU_TESTBUS4_IDX 24 +#define CPU_TESTBUS5_IDX 25 +#define CPU_TESTBUS6_IDX 26 +#define CPU_TESTBUS7_IDX 27 +#define CPU_GPIO_IN0_IDX 28 +#define CPU_GPIO_OUT0_IDX 28 +#define CPU_GPIO_IN1_IDX 29 +#define CPU_GPIO_OUT1_IDX 29 +#define CPU_GPIO_IN2_IDX 30 +#define CPU_GPIO_OUT2_IDX 30 +#define CPU_GPIO_IN3_IDX 31 +#define CPU_GPIO_OUT3_IDX 31 +#define CPU_GPIO_IN4_IDX 32 +#define CPU_GPIO_OUT4_IDX 32 +#define CPU_GPIO_IN5_IDX 33 +#define CPU_GPIO_OUT5_IDX 33 +#define CPU_GPIO_IN6_IDX 34 +#define CPU_GPIO_OUT6_IDX 34 +#define CPU_GPIO_IN7_IDX 35 +#define CPU_GPIO_OUT7_IDX 35 +#define USB_JTAG_TCK_IDX 36 +#define USB_JTAG_TMS_IDX 37 +#define USB_JTAG_TDI_IDX 38 +#define USB_JTAG_TDO_IDX 39 +#define USB_EXTPHY_VP_IDX 40 +#define USB_EXTPHY_OEN_IDX 40 +#define USB_EXTPHY_VM_IDX 41 +#define USB_EXTPHY_SPEED_IDX 41 +#define USB_EXTPHY_RCV_IDX 42 +#define USB_EXTPHY_VPO_IDX 42 +#define USB_EXTPHY_VMO_IDX 43 +#define USB_EXTPHY_SUSPND_IDX 44 +#define I2CEXT0_SCL_IN_IDX 45 +#define I2CEXT0_SCL_OUT_IDX 45 +#define I2CEXT0_SDA_IN_IDX 46 +#define I2CEXT0_SDA_OUT_IDX 46 +#define PARL_RX_DATA0_IDX 47 +#define PARL_TX_DATA0_IDX 47 +#define PARL_RX_DATA1_IDX 48 +#define PARL_TX_DATA1_IDX 48 +#define PARL_RX_DATA2_IDX 49 +#define PARL_TX_DATA2_IDX 49 +#define PARL_RX_DATA3_IDX 50 +#define PARL_TX_DATA3_IDX 50 +#define PARL_RX_DATA4_IDX 51 +#define PARL_TX_DATA4_IDX 51 +#define PARL_RX_DATA5_IDX 52 +#define PARL_TX_DATA5_IDX 52 +#define PARL_RX_DATA6_IDX 53 +#define PARL_TX_DATA6_IDX 53 +#define PARL_RX_DATA7_IDX 54 +#define PARL_TX_DATA7_IDX 54 +#define PARL_RX_DATA8_IDX 55 +#define PARL_TX_DATA8_IDX 55 +#define PARL_RX_DATA9_IDX 56 +#define PARL_TX_DATA9_IDX 56 +#define PARL_RX_DATA10_IDX 57 +#define PARL_TX_DATA10_IDX 57 +#define PARL_RX_DATA11_IDX 58 +#define PARL_TX_DATA11_IDX 58 +#define PARL_RX_DATA12_IDX 59 +#define PARL_TX_DATA12_IDX 59 +#define PARL_RX_DATA13_IDX 60 +#define PARL_TX_DATA13_IDX 60 +#define PARL_RX_DATA14_IDX 61 +#define PARL_TX_DATA14_IDX 61 +#define PARL_RX_DATA15_IDX 62 +#define PARL_TX_DATA15_IDX 62 +#define FSPICLK_IN_IDX 63 +#define FSPICLK_OUT_IDX 63 +#define FSPIQ_IN_IDX 64 +#define FSPIQ_OUT_IDX 64 +#define FSPID_IN_IDX 65 +#define FSPID_OUT_IDX 65 +#define FSPIHD_IN_IDX 66 +#define FSPIHD_OUT_IDX 66 +#define FSPIWP_IN_IDX 67 +#define FSPIWP_OUT_IDX 67 +#define FSPICS0_IN_IDX 68 +#define FSPICS0_OUT_IDX 68 +#define PARL_RX_CLK_IN_IDX 69 +#define SDIO_TOHOST_INT_OUT_IDX 69 +#define PARL_TX_CLK_IN_IDX 70 +#define PARL_TX_CLK_OUT_IDX 70 +#define RMT_SIG_IN0_IDX 71 +#define RMT_SIG_OUT0_IDX 71 +#define MODEM_DIAG0_IDX 71 +#define RMT_SIG_IN1_IDX 72 +#define RMT_SIG_OUT1_IDX 72 +#define MODEM_DIAG1_IDX 72 +#define TWAI0_RX_IDX 73 +#define TWAI0_TX_IDX 73 +#define MODEM_DIAG2_IDX 73 +#define TWAI0_BUS_OFF_ON_IDX 74 +#define MODEM_DIAG3_IDX 74 +#define TWAI0_CLKOUT_IDX 75 +#define MODEM_DIAG4_IDX 75 +#define TWAI0_STANDBY_IDX 76 +#define MODEM_DIAG5_IDX 76 +#define TWAI1_RX_IDX 77 +#define TWAI1_TX_IDX 77 +#define MODEM_DIAG6_IDX 77 +#define TWAI1_BUS_OFF_ON_IDX 78 +#define MODEM_DIAG7_IDX 78 +#define TWAI1_CLKOUT_IDX 79 +#define MODEM_DIAG8_IDX 79 +#define TWAI1_STANDBY_IDX 80 +#define MODEM_DIAG9_IDX 80 +#define EXTERN_PRIORITY_I_IDX 81 +#define EXTERN_PRIORITY_O_IDX 81 +#define EXTERN_ACTIVE_I_IDX 82 +#define EXTERN_ACTIVE_O_IDX 82 +#define GPIO_SD0_OUT_IDX 83 +#define GPIO_SD1_OUT_IDX 84 +#define GPIO_SD2_OUT_IDX 85 +#define GPIO_SD3_OUT_IDX 86 +#define PWM0_SYNC0_IN_IDX 87 +#define PWM0_OUT0A_IDX 87 +#define MODEM_DIAG10_IDX 87 +#define PWM0_SYNC1_IN_IDX 88 +#define PWM0_OUT0B_IDX 88 +#define MODEM_DIAG11_IDX 88 +#define PWM0_SYNC2_IN_IDX 89 +#define PWM0_OUT1A_IDX 89 +#define MODEM_DIAG12_IDX 89 +#define PWM0_F0_IN_IDX 90 +#define PWM0_OUT1B_IDX 90 +#define MODEM_DIAG13_IDX 90 +#define PWM0_F1_IN_IDX 91 +#define PWM0_OUT2A_IDX 91 +#define MODEM_DIAG14_IDX 91 +#define PWM0_F2_IN_IDX 92 +#define PWM0_OUT2B_IDX 92 +#define MODEM_DIAG15_IDX 92 +#define PWM0_CAP0_IN_IDX 93 +#define ANT_SEL0_IDX 93 +#define PWM0_CAP1_IN_IDX 94 +#define ANT_SEL1_IDX 94 +#define PWM0_CAP2_IN_IDX 95 +#define ANT_SEL2_IDX 95 +#define ANT_SEL3_IDX 96 +#define SIG_IN_FUNC_97_IDX 97 +#define SIG_IN_FUNC97_IDX 97 +#define SIG_IN_FUNC_98_IDX 98 +#define SIG_IN_FUNC98_IDX 98 +#define SIG_IN_FUNC_99_IDX 99 +#define SIG_IN_FUNC99_IDX 99 +#define SIG_IN_FUNC_100_IDX 100 +#define SIG_IN_FUNC100_IDX 100 +#define PCNT_SIG_CH0_IN0_IDX 101 +#define FSPICS1_OUT_IDX 101 +#define MODEM_DIAG16_IDX 101 +#define PCNT_SIG_CH1_IN0_IDX 102 +#define FSPICS2_OUT_IDX 102 +#define MODEM_DIAG17_IDX 102 +#define PCNT_CTRL_CH0_IN0_IDX 103 +#define FSPICS3_OUT_IDX 103 +#define MODEM_DIAG18_IDX 103 +#define PCNT_CTRL_CH1_IN0_IDX 104 +#define FSPICS4_OUT_IDX 104 +#define MODEM_DIAG19_IDX 104 +#define PCNT_SIG_CH0_IN1_IDX 105 +#define FSPICS5_OUT_IDX 105 +#define MODEM_DIAG20_IDX 105 +#define PCNT_SIG_CH1_IN1_IDX 106 +#define MODEM_DIAG21_IDX 106 +#define PCNT_CTRL_CH0_IN1_IDX 107 +#define MODEM_DIAG22_IDX 107 +#define PCNT_CTRL_CH1_IN1_IDX 108 +#define MODEM_DIAG23_IDX 108 +#define PCNT_SIG_CH0_IN2_IDX 109 +#define MODEM_DIAG24_IDX 109 +#define PCNT_SIG_CH1_IN2_IDX 110 +#define MODEM_DIAG25_IDX 110 +#define PCNT_CTRL_CH0_IN2_IDX 111 +#define MODEM_DIAG26_IDX 111 +#define PCNT_CTRL_CH1_IN2_IDX 112 +#define MODEM_DIAG27_IDX 112 +#define PCNT_SIG_CH0_IN3_IDX 113 +#define MODEM_DIAG28_IDX 113 +#define PCNT_SIG_CH1_IN3_IDX 114 +#define SPICLK_OUT_IDX 114 +#define MODEM_DIAG29_IDX 114 +#define PCNT_CTRL_CH0_IN3_IDX 115 +#define SPICS0_OUT_IDX 115 +#define MODEM_DIAG30_IDX 115 +#define PCNT_CTRL_CH1_IN3_IDX 116 +#define SPICS1_OUT_IDX 116 +#define MODEM_DIAG31_IDX 116 +#define GPIO_EVENT_MATRIX_IN0_IDX 117 +#define GPIO_TASK_MATRIX_OUT0_IDX 117 +#define GPIO_EVENT_MATRIX_IN1_IDX 118 +#define GPIO_TASK_MATRIX_OUT1_IDX 118 +#define GPIO_EVENT_MATRIX_IN2_IDX 119 +#define GPIO_TASK_MATRIX_OUT2_IDX 119 +#define GPIO_EVENT_MATRIX_IN3_IDX 120 +#define GPIO_TASK_MATRIX_OUT3_IDX 120 +#define SPIQ_IN_IDX 121 +#define SPIQ_OUT_IDX 121 +#define SPID_IN_IDX 122 +#define SPID_OUT_IDX 122 +#define SPIHD_IN_IDX 123 +#define SPIHD_OUT_IDX 123 +#define SPIWP_IN_IDX 124 +#define SPIWP_OUT_IDX 124 +#define CLK_OUT_OUT1_IDX 125 +#define CLK_OUT_OUT2_IDX 126 +#define CLK_OUT_OUT3_IDX 127 +#define SIG_GPIO_OUT_IDX 128 +#define GPIO_MAP_DATE_IDX 0x2201120 +#endif /* _SOC_GPIO_SIG_MAP_H_ */ diff --git a/components/soc/esp32c6/include/soc/gpio_struct.h b/components/soc/esp32c6/include/soc/gpio_struct.h new file mode 100644 index 0000000000..ed3e224ca9 --- /dev/null +++ b/components/soc/esp32c6/include/soc/gpio_struct.h @@ -0,0 +1,609 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configuration register */ +/** Type of bt_select register + * GPIO bit select register + */ +typedef union { + struct { + /** bt_sel : R/W; bitpos: [31:0]; default: 0; + * GPIO bit select register + */ + uint32_t bt_sel:32; + }; + uint32_t val; +} gpio_bt_select_reg_t; + +/** Type of out register + * GPIO output register for GPIO0-31 + */ +typedef union { + struct { + /** out_data_orig : R/W/SC/WTC; bitpos: [31:0]; default: 0; + * GPIO output register for GPIO0-31 + */ + uint32_t out_data_orig:32; + }; + uint32_t val; +} gpio_out_reg_t; + +/** Type of out_w1ts register + * GPIO output set register for GPIO0-31 + */ +typedef union { + struct { + /** out_w1ts : WT; bitpos: [31:0]; default: 0; + * GPIO output set register for GPIO0-31 + */ + uint32_t out_w1ts:32; + }; + uint32_t val; +} gpio_out_w1ts_reg_t; + +/** Type of out_w1tc register + * GPIO output clear register for GPIO0-31 + */ +typedef union { + struct { + /** out_w1tc : WT; bitpos: [31:0]; default: 0; + * GPIO output clear register for GPIO0-31 + */ + uint32_t out_w1tc:32; + }; + uint32_t val; +} gpio_out_w1tc_reg_t; + +/** Type of out1 register + * GPIO output register for GPIO32-34 + */ +typedef union { + struct { + /** out1_data_orig : R/W/SC/WTC; bitpos: [2:0]; default: 0; + * GPIO output register for GPIO32-34 + */ + uint32_t out1_data_orig:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_out1_reg_t; + +/** Type of out1_w1ts register + * GPIO output set register for GPIO32-34 + */ +typedef union { + struct { + /** out1_w1ts : WT; bitpos: [2:0]; default: 0; + * GPIO output set register for GPIO32-34 + */ + uint32_t out1_w1ts:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_out1_w1ts_reg_t; + +/** Type of out1_w1tc register + * GPIO output clear register for GPIO32-34 + */ +typedef union { + struct { + /** out1_w1tc : WT; bitpos: [2:0]; default: 0; + * GPIO output clear register for GPIO32-34 + */ + uint32_t out1_w1tc:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_out1_w1tc_reg_t; + +/** Type of sdio_select register + * GPIO sdio select register + */ +typedef union { + struct { + /** sdio_sel : R/W; bitpos: [7:0]; default: 0; + * GPIO sdio select register + */ + uint32_t sdio_sel:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_sdio_select_reg_t; + +/** Type of enable register + * GPIO output enable register for GPIO0-31 + */ +typedef union { + struct { + /** enable_data : R/W/WTC; bitpos: [31:0]; default: 0; + * GPIO output enable register for GPIO0-31 + */ + uint32_t enable_data:32; + }; + uint32_t val; +} gpio_enable_reg_t; + +/** Type of enable_w1ts register + * GPIO output enable set register for GPIO0-31 + */ +typedef union { + struct { + /** enable_w1ts : WT; bitpos: [31:0]; default: 0; + * GPIO output enable set register for GPIO0-31 + */ + uint32_t enable_w1ts:32; + }; + uint32_t val; +} gpio_enable_w1ts_reg_t; + +/** Type of enable_w1tc register + * GPIO output enable clear register for GPIO0-31 + */ +typedef union { + struct { + /** enable_w1tc : WT; bitpos: [31:0]; default: 0; + * GPIO output enable clear register for GPIO0-31 + */ + uint32_t enable_w1tc:32; + }; + uint32_t val; +} gpio_enable_w1tc_reg_t; + +/** Type of enable1 register + * GPIO output enable register for GPIO32-34 + */ +typedef union { + struct { + /** enable1_data : R/W/WTC; bitpos: [2:0]; default: 0; + * GPIO output enable register for GPIO32-34 + */ + uint32_t enable1_data:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_enable1_reg_t; + +/** Type of enable1_w1ts register + * GPIO output enable set register for GPIO32-34 + */ +typedef union { + struct { + /** enable1_w1ts : WT; bitpos: [2:0]; default: 0; + * GPIO output enable set register for GPIO32-34 + */ + uint32_t enable1_w1ts:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_enable1_w1ts_reg_t; + +/** Type of enable1_w1tc register + * GPIO output enable clear register for GPIO32-34 + */ +typedef union { + struct { + /** enable1_w1tc : WT; bitpos: [2:0]; default: 0; + * GPIO output enable clear register for GPIO32-34 + */ + uint32_t enable1_w1tc:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_enable1_w1tc_reg_t; + +/** Type of strap register + * pad strapping register + */ +typedef union { + struct { + /** strapping : RO; bitpos: [15:0]; default: 0; + * pad strapping register + */ + uint32_t strapping:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} gpio_strap_reg_t; + +/** Type of in register + * GPIO input register for GPIO0-31 + */ +typedef union { + struct { + /** in_data_next : RO; bitpos: [31:0]; default: 0; + * GPIO input register for GPIO0-31 + */ + uint32_t in_data_next:32; + }; + uint32_t val; +} gpio_in_reg_t; + +/** Type of in1 register + * GPIO input register for GPIO32-34 + */ +typedef union { + struct { + /** in1_data_next : RO; bitpos: [2:0]; default: 0; + * GPIO input register for GPIO32-34 + */ + uint32_t in1_data_next:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_in1_reg_t; + +/** Type of status register + * GPIO interrupt status register for GPIO0-31 + */ +typedef union { + struct { + /** status_interrupt : R/W/WTC; bitpos: [31:0]; default: 0; + * GPIO interrupt status register for GPIO0-31 + */ + uint32_t status_interrupt:32; + }; + uint32_t val; +} gpio_status_reg_t; + +/** Type of status_w1ts register + * GPIO interrupt status set register for GPIO0-31 + */ +typedef union { + struct { + /** status_w1ts : WT; bitpos: [31:0]; default: 0; + * GPIO interrupt status set register for GPIO0-31 + */ + uint32_t status_w1ts:32; + }; + uint32_t val; +} gpio_status_w1ts_reg_t; + +/** Type of status_w1tc register + * GPIO interrupt status clear register for GPIO0-31 + */ +typedef union { + struct { + /** status_w1tc : WT; bitpos: [31:0]; default: 0; + * GPIO interrupt status clear register for GPIO0-31 + */ + uint32_t status_w1tc:32; + }; + uint32_t val; +} gpio_status_w1tc_reg_t; + +/** Type of status1 register + * GPIO interrupt status register for GPIO32-34 + */ +typedef union { + struct { + /** status1_interrupt : R/W/WTC; bitpos: [2:0]; default: 0; + * GPIO interrupt status register for GPIO32-34 + */ + uint32_t status1_interrupt:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_status1_reg_t; + +/** Type of status1_w1ts register + * GPIO interrupt status set register for GPIO32-34 + */ +typedef union { + struct { + /** status1_w1ts : WT; bitpos: [2:0]; default: 0; + * GPIO interrupt status set register for GPIO32-34 + */ + uint32_t status1_w1ts:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_status1_w1ts_reg_t; + +/** Type of status1_w1tc register + * GPIO interrupt status clear register for GPIO32-34 + */ +typedef union { + struct { + /** status1_w1tc : WT; bitpos: [2:0]; default: 0; + * GPIO interrupt status clear register for GPIO32-34 + */ + uint32_t status1_w1tc:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_status1_w1tc_reg_t; + +/** Type of pcpu_int register + * GPIO PRO_CPU interrupt status register for GPIO0-31 + */ +typedef union { + struct { + /** procpu_int : RO; bitpos: [31:0]; default: 0; + * GPIO PRO_CPU interrupt status register for GPIO0-31 + */ + uint32_t procpu_int:32; + }; + uint32_t val; +} gpio_pcpu_int_reg_t; + +/** Type of pcpu_nmi_int register + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + */ +typedef union { + struct { + /** procpu_nmi_int : RO; bitpos: [31:0]; default: 0; + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + */ + uint32_t procpu_nmi_int:32; + }; + uint32_t val; +} gpio_pcpu_nmi_int_reg_t; + +/** Type of cpusdio_int register + * GPIO CPUSDIO interrupt status register for GPIO0-31 + */ +typedef union { + struct { + /** sdio_int : RO; bitpos: [31:0]; default: 0; + * GPIO CPUSDIO interrupt status register for GPIO0-31 + */ + uint32_t sdio_int:32; + }; + uint32_t val; +} gpio_cpusdio_int_reg_t; + +/** Type of pcpu_int1 register + * GPIO PRO_CPU interrupt status register for GPIO32-34 + */ +typedef union { + struct { + /** procpu_int1 : RO; bitpos: [2:0]; default: 0; + * GPIO PRO_CPU interrupt status register for GPIO32-34 + */ + uint32_t procpu_int1:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_pcpu_int1_reg_t; + +/** Type of pcpu_nmi_int1 register + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-34 + */ +typedef union { + struct { + /** procpu_nmi_int1 : RO; bitpos: [2:0]; default: 0; + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-34 + */ + uint32_t procpu_nmi_int1:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_pcpu_nmi_int1_reg_t; + +/** Type of cpusdio_int1 register + * GPIO CPUSDIO interrupt status register for GPIO32-34 + */ +typedef union { + struct { + /** sdio_int1 : RO; bitpos: [2:0]; default: 0; + * GPIO CPUSDIO interrupt status register for GPIO32-34 + */ + uint32_t sdio_int1:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_cpusdio_int1_reg_t; + +/** Type of pin register + * GPIO pin configuration register + */ +typedef union { + struct { + /** sync2_bypass : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ + uint32_t sync2_bypass:2; + /** pad_driver : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ + uint32_t pad_driver:1; + /** sync1_bypass : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ + uint32_t sync1_bypass:2; + uint32_t reserved_5:2; + /** int_type : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ + uint32_t int_type:3; + /** wakeup_enable : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ + uint32_t wakeup_enable:1; + /** config : R/W; bitpos: [12:11]; default: 0; + * reserved + */ + uint32_t config:2; + /** int_ena : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ + uint32_t int_ena:5; + uint32_t reserved_18:14; + }; + uint32_t val; +} gpio_pin_reg_t; + +/** Type of status_next register + * GPIO interrupt source register for GPIO0-31 + */ +typedef union { + struct { + /** status_interrupt_next : RO; bitpos: [31:0]; default: 0; + * GPIO interrupt source register for GPIO0-31 + */ + uint32_t status_interrupt_next:32; + }; + uint32_t val; +} gpio_status_next_reg_t; + +/** Type of status_next1 register + * GPIO interrupt source register for GPIO32-34 + */ +typedef union { + struct { + /** status_interrupt_next1 : RO; bitpos: [2:0]; default: 0; + * GPIO interrupt source register for GPIO32-34 + */ + uint32_t status_interrupt_next1:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_status_next1_reg_t; + +/** Type of func_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t in_sel:6; + /** in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t in_inv_sel:1; + /** sig_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func_in_sel_cfg_reg_t; + +/** Type of func_out_sel_cfg register + * GPIO output function select register + */ +typedef union { + struct { + /** out_sel : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ + uint32_t out_sel:8; + /** out_inv_sel : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ + uint32_t out_inv_sel:1; + /** oen_sel : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ + uint32_t oen_sel:1; + /** oen_inv_sel : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ + uint32_t oen_inv_sel:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} gpio_func_out_sel_cfg_reg_t; + +/** Type of clock_gate register + * GPIO clock gate register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * set this bit to enable GPIO clock gate + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gpio_clock_gate_reg_t; + +/** Type of date register + * GPIO version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35655968; + * version register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} gpio_date_reg_t; + + +typedef struct gpio_dev_t { + volatile gpio_bt_select_reg_t bt_select; + volatile gpio_out_reg_t out; + volatile gpio_out_w1ts_reg_t out_w1ts; + volatile gpio_out_w1tc_reg_t out_w1tc; + volatile gpio_out1_reg_t out1; + volatile gpio_out1_w1ts_reg_t out1_w1ts; + volatile gpio_out1_w1tc_reg_t out1_w1tc; + volatile gpio_sdio_select_reg_t sdio_select; + volatile gpio_enable_reg_t enable; + volatile gpio_enable_w1ts_reg_t enable_w1ts; + volatile gpio_enable_w1tc_reg_t enable_w1tc; + volatile gpio_enable1_reg_t enable1; + volatile gpio_enable1_w1ts_reg_t enable1_w1ts; + volatile gpio_enable1_w1tc_reg_t enable1_w1tc; + volatile gpio_strap_reg_t strap; + volatile gpio_in_reg_t in; + volatile gpio_in1_reg_t in1; + volatile gpio_status_reg_t status; + volatile gpio_status_w1ts_reg_t status_w1ts; + volatile gpio_status_w1tc_reg_t status_w1tc; + volatile gpio_status1_reg_t status1; + volatile gpio_status1_w1ts_reg_t status1_w1ts; + volatile gpio_status1_w1tc_reg_t status1_w1tc; + volatile gpio_pcpu_int_reg_t pcpu_int; + volatile gpio_pcpu_nmi_int_reg_t pcpu_nmi_int; + volatile gpio_cpusdio_int_reg_t cpusdio_int; + volatile gpio_pcpu_int1_reg_t pcpu_int1; + volatile gpio_pcpu_nmi_int1_reg_t pcpu_nmi_int1; + volatile gpio_cpusdio_int1_reg_t cpusdio_int1; + volatile gpio_pin_reg_t pin[35]; + uint32_t reserved_100[19]; + volatile gpio_status_next_reg_t status_next; + volatile gpio_status_next1_reg_t status_next1; + volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[125]; + uint32_t reserved_348[131]; + volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[35]; + uint32_t reserved_5e0[19]; + volatile gpio_clock_gate_reg_t clock_gate; + uint32_t reserved_630[51]; + volatile gpio_date_reg_t date; +} gpio_dev_t; + +extern gpio_dev_t GPIO; + +#ifndef __cplusplus +_Static_assert(sizeof(gpio_dev_t) == 0x700, "Invalid size of gpio_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/hardware_lock_reg.h b/components/soc/esp32c6/include/soc/hardware_lock_reg.h new file mode 100644 index 0000000000..a9fbfb8cb0 --- /dev/null +++ b/components/soc/esp32c6/include/soc/hardware_lock_reg.h @@ -0,0 +1,76 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** ATOMIC_ADDR_LOCK_REG register + * hardware lock regsiter + */ +#define ATOMIC_ADDR_LOCK_REG (DR_REG_ATOMIC_BASE + 0x0) +/** ATOMIC_LOCK : R/W; bitpos: [1:0]; default: 0; + * read to acquire hardware lock, write to release hardware lock + */ +#define ATOMIC_LOCK 0x00000003U +#define ATOMIC_LOCK_M (ATOMIC_LOCK_V << ATOMIC_LOCK_S) +#define ATOMIC_LOCK_V 0x00000003U +#define ATOMIC_LOCK_S 0 + +/** ATOMIC_LR_ADDR_REG register + * gloable lr address regsiter + */ +#define ATOMIC_LR_ADDR_REG (DR_REG_ATOMIC_BASE + 0x4) +/** ATOMIC_GLOABLE_LR_ADDR : R/W; bitpos: [31:0]; default: 0; + * backup gloable address + */ +#define ATOMIC_GLOABLE_LR_ADDR 0xFFFFFFFFU +#define ATOMIC_GLOABLE_LR_ADDR_M (ATOMIC_GLOABLE_LR_ADDR_V << ATOMIC_GLOABLE_LR_ADDR_S) +#define ATOMIC_GLOABLE_LR_ADDR_V 0xFFFFFFFFU +#define ATOMIC_GLOABLE_LR_ADDR_S 0 + +/** ATOMIC_LR_VALUE_REG register + * gloable lr value regsiter + */ +#define ATOMIC_LR_VALUE_REG (DR_REG_ATOMIC_BASE + 0x8) +/** ATOMIC_GLOABLE_LR_VALUE : R/W; bitpos: [31:0]; default: 0; + * backup gloable value + */ +#define ATOMIC_GLOABLE_LR_VALUE 0xFFFFFFFFU +#define ATOMIC_GLOABLE_LR_VALUE_M (ATOMIC_GLOABLE_LR_VALUE_V << ATOMIC_GLOABLE_LR_VALUE_S) +#define ATOMIC_GLOABLE_LR_VALUE_V 0xFFFFFFFFU +#define ATOMIC_GLOABLE_LR_VALUE_S 0 + +/** ATOMIC_LOCK_STATUS_REG register + * lock status regsiter + */ +#define ATOMIC_LOCK_STATUS_REG (DR_REG_ATOMIC_BASE + 0xc) +/** ATOMIC_LOCK_STATUS : RO; bitpos: [1:0]; default: 0; + * read hareware lock status for debug + */ +#define ATOMIC_LOCK_STATUS 0x00000003U +#define ATOMIC_LOCK_STATUS_M (ATOMIC_LOCK_STATUS_V << ATOMIC_LOCK_STATUS_S) +#define ATOMIC_LOCK_STATUS_V 0x00000003U +#define ATOMIC_LOCK_STATUS_S 0 + +/** ATOMIC_COUNTER_REG register + * wait counter register + */ +#define ATOMIC_COUNTER_REG (DR_REG_ATOMIC_BASE + 0x10) +/** ATOMIC_WAIT_COUNTER : R/W; bitpos: [15:0]; default: 0; + * delay counter + */ +#define ATOMIC_WAIT_COUNTER 0x0000FFFFU +#define ATOMIC_WAIT_COUNTER_M (ATOMIC_WAIT_COUNTER_V << ATOMIC_WAIT_COUNTER_S) +#define ATOMIC_WAIT_COUNTER_V 0x0000FFFFU +#define ATOMIC_WAIT_COUNTER_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/hardware_lock_struct.h b/components/soc/esp32c6/include/soc/hardware_lock_struct.h new file mode 100644 index 0000000000..0430212e50 --- /dev/null +++ b/components/soc/esp32c6/include/soc/hardware_lock_struct.h @@ -0,0 +1,99 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configuration registers */ +/** Type of addr_lock register + * hardware lock regsiter + */ +typedef union { + struct { + /** lock : R/W; bitpos: [1:0]; default: 0; + * read to acquire hardware lock, write to release hardware lock + */ + uint32_t lock:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} atomic_addr_lock_reg_t; + +/** Type of lr_addr register + * gloable lr address regsiter + */ +typedef union { + struct { + /** gloable_lr_addr : R/W; bitpos: [31:0]; default: 0; + * backup gloable address + */ + uint32_t gloable_lr_addr:32; + }; + uint32_t val; +} atomic_lr_addr_reg_t; + +/** Type of lr_value register + * gloable lr value regsiter + */ +typedef union { + struct { + /** gloable_lr_value : R/W; bitpos: [31:0]; default: 0; + * backup gloable value + */ + uint32_t gloable_lr_value:32; + }; + uint32_t val; +} atomic_lr_value_reg_t; + +/** Type of lock_status register + * lock status regsiter + */ +typedef union { + struct { + /** lock_status : RO; bitpos: [1:0]; default: 0; + * read hareware lock status for debug + */ + uint32_t lock_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} atomic_lock_status_reg_t; + +/** Type of counter register + * wait counter register + */ +typedef union { + struct { + /** wait_counter : R/W; bitpos: [15:0]; default: 0; + * delay counter + */ + uint32_t wait_counter:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} atomic_counter_reg_t; + + +typedef struct atomic_dev_t { + volatile atomic_addr_lock_reg_t addr_lock; + volatile atomic_lr_addr_reg_t lr_addr; + volatile atomic_lr_value_reg_t lr_value; + volatile atomic_lock_status_reg_t lock_status; + volatile atomic_counter_reg_t counter; +} atomic_dev_t; + +extern atomic_dev_t ATOMIC_LOCKER; + +#ifndef __cplusplus +_Static_assert(sizeof(atomic_dev_t) == 0x14, "Invalid size of atomic_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/hinf_reg.h b/components/soc/esp32c6/include/soc/hinf_reg.h new file mode 100644 index 0000000000..356fefb1a2 --- /dev/null +++ b/components/soc/esp32c6/include/soc/hinf_reg.h @@ -0,0 +1,647 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HINF_CFG_DATA0_REG register + * Configure sdio cis content + */ +#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0) +/** HINF_DEVICE_ID_FN1 : R/W; bitpos: [15:0]; default: 26214; + * configure device id of function1 in cis + */ +#define HINF_DEVICE_ID_FN1 0x0000FFFFU +#define HINF_DEVICE_ID_FN1_M (HINF_DEVICE_ID_FN1_V << HINF_DEVICE_ID_FN1_S) +#define HINF_DEVICE_ID_FN1_V 0x0000FFFFU +#define HINF_DEVICE_ID_FN1_S 0 +/** HINF_USER_ID_FN1 : R/W; bitpos: [31:16]; default: 146; + * configure user id of function1 in cis + */ +#define HINF_USER_ID_FN1 0x0000FFFFU +#define HINF_USER_ID_FN1_M (HINF_USER_ID_FN1_V << HINF_USER_ID_FN1_S) +#define HINF_USER_ID_FN1_V 0x0000FFFFU +#define HINF_USER_ID_FN1_S 16 + +/** HINF_CFG_DATA1_REG register + * SDIO configuration register + */ +#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4) +/** HINF_SDIO_ENABLE : R/W; bitpos: [0]; default: 1; + * Sdio clock enable + */ +#define HINF_SDIO_ENABLE (BIT(0)) +#define HINF_SDIO_ENABLE_M (HINF_SDIO_ENABLE_V << HINF_SDIO_ENABLE_S) +#define HINF_SDIO_ENABLE_V 0x00000001U +#define HINF_SDIO_ENABLE_S 0 +/** HINF_SDIO_IOREADY1 : R/W; bitpos: [1]; default: 0; + * sdio function1 io ready signal in cis + */ +#define HINF_SDIO_IOREADY1 (BIT(1)) +#define HINF_SDIO_IOREADY1_M (HINF_SDIO_IOREADY1_V << HINF_SDIO_IOREADY1_S) +#define HINF_SDIO_IOREADY1_V 0x00000001U +#define HINF_SDIO_IOREADY1_S 1 +/** HINF_HIGHSPEED_ENABLE : R/W; bitpos: [2]; default: 0; + * Highspeed enable in cccr + */ +#define HINF_HIGHSPEED_ENABLE (BIT(2)) +#define HINF_HIGHSPEED_ENABLE_M (HINF_HIGHSPEED_ENABLE_V << HINF_HIGHSPEED_ENABLE_S) +#define HINF_HIGHSPEED_ENABLE_V 0x00000001U +#define HINF_HIGHSPEED_ENABLE_S 2 +/** HINF_HIGHSPEED_MODE : RO; bitpos: [3]; default: 0; + * highspeed mode status in cccr + */ +#define HINF_HIGHSPEED_MODE (BIT(3)) +#define HINF_HIGHSPEED_MODE_M (HINF_HIGHSPEED_MODE_V << HINF_HIGHSPEED_MODE_S) +#define HINF_HIGHSPEED_MODE_V 0x00000001U +#define HINF_HIGHSPEED_MODE_S 3 +/** HINF_SDIO_CD_ENABLE : R/W; bitpos: [4]; default: 1; + * sdio card detect enable + */ +#define HINF_SDIO_CD_ENABLE (BIT(4)) +#define HINF_SDIO_CD_ENABLE_M (HINF_SDIO_CD_ENABLE_V << HINF_SDIO_CD_ENABLE_S) +#define HINF_SDIO_CD_ENABLE_V 0x00000001U +#define HINF_SDIO_CD_ENABLE_S 4 +/** HINF_SDIO_IOREADY2 : R/W; bitpos: [5]; default: 0; + * sdio function1 io ready signal in cis + */ +#define HINF_SDIO_IOREADY2 (BIT(5)) +#define HINF_SDIO_IOREADY2_M (HINF_SDIO_IOREADY2_V << HINF_SDIO_IOREADY2_S) +#define HINF_SDIO_IOREADY2_V 0x00000001U +#define HINF_SDIO_IOREADY2_S 5 +/** HINF_SDIO_INT_MASK : R/W; bitpos: [6]; default: 0; + * mask sdio interrupt in cccr, high active + */ +#define HINF_SDIO_INT_MASK (BIT(6)) +#define HINF_SDIO_INT_MASK_M (HINF_SDIO_INT_MASK_V << HINF_SDIO_INT_MASK_S) +#define HINF_SDIO_INT_MASK_V 0x00000001U +#define HINF_SDIO_INT_MASK_S 6 +/** HINF_IOENABLE2 : RO; bitpos: [7]; default: 0; + * ioe2 status in cccr + */ +#define HINF_IOENABLE2 (BIT(7)) +#define HINF_IOENABLE2_M (HINF_IOENABLE2_V << HINF_IOENABLE2_S) +#define HINF_IOENABLE2_V 0x00000001U +#define HINF_IOENABLE2_S 7 +/** HINF_CD_DISABLE : RO; bitpos: [8]; default: 0; + * card disable status in cccr + */ +#define HINF_CD_DISABLE (BIT(8)) +#define HINF_CD_DISABLE_M (HINF_CD_DISABLE_V << HINF_CD_DISABLE_S) +#define HINF_CD_DISABLE_V 0x00000001U +#define HINF_CD_DISABLE_S 8 +/** HINF_FUNC1_EPS : RO; bitpos: [9]; default: 0; + * function1 eps status in fbr + */ +#define HINF_FUNC1_EPS (BIT(9)) +#define HINF_FUNC1_EPS_M (HINF_FUNC1_EPS_V << HINF_FUNC1_EPS_S) +#define HINF_FUNC1_EPS_V 0x00000001U +#define HINF_FUNC1_EPS_S 9 +/** HINF_EMP : RO; bitpos: [10]; default: 0; + * empc status in cccr + */ +#define HINF_EMP (BIT(10)) +#define HINF_EMP_M (HINF_EMP_V << HINF_EMP_S) +#define HINF_EMP_V 0x00000001U +#define HINF_EMP_S 10 +/** HINF_IOENABLE1 : RO; bitpos: [11]; default: 0; + * ioe1 status in cccr + */ +#define HINF_IOENABLE1 (BIT(11)) +#define HINF_IOENABLE1_M (HINF_IOENABLE1_V << HINF_IOENABLE1_S) +#define HINF_IOENABLE1_V 0x00000001U +#define HINF_IOENABLE1_S 11 +/** HINF_SDIO_VER : R/W; bitpos: [23:12]; default: 562; + * sdio version in cccr + */ +#define HINF_SDIO_VER 0x00000FFFU +#define HINF_SDIO_VER_M (HINF_SDIO_VER_V << HINF_SDIO_VER_S) +#define HINF_SDIO_VER_V 0x00000FFFU +#define HINF_SDIO_VER_S 12 +/** HINF_FUNC2_EPS : RO; bitpos: [24]; default: 0; + * function2 eps status in fbr + */ +#define HINF_FUNC2_EPS (BIT(24)) +#define HINF_FUNC2_EPS_M (HINF_FUNC2_EPS_V << HINF_FUNC2_EPS_S) +#define HINF_FUNC2_EPS_V 0x00000001U +#define HINF_FUNC2_EPS_S 24 +/** HINF_SDIO20_CONF : R/W; bitpos: [31:25]; default: 0; + * [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat + * in delayed cycles control,0:no delay, 1:delay 1 cycle. + * [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed + * mode. + * [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when + * [12]=0,posedge when highspeed mode enable. + * [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay. + * [28]: sdio data pad pull up enable + */ +#define HINF_SDIO20_CONF 0x0000007FU +#define HINF_SDIO20_CONF_M (HINF_SDIO20_CONF_V << HINF_SDIO20_CONF_S) +#define HINF_SDIO20_CONF_V 0x0000007FU +#define HINF_SDIO20_CONF_S 25 + +/** HINF_CFG_TIMING_REG register + * Timing configuration registers + */ +#define HINF_CFG_TIMING_REG (DR_REG_HINF_BASE + 0x8) +/** HINF_NCRC : R/W; bitpos: [2:0]; default: 2; + * configure Ncrc parameter in sdr50/104 mode, no more than 6. + */ +#define HINF_NCRC 0x00000007U +#define HINF_NCRC_M (HINF_NCRC_V << HINF_NCRC_S) +#define HINF_NCRC_V 0x00000007U +#define HINF_NCRC_S 0 +/** HINF_PST_END_CMD_LOW_VALUE : R/W; bitpos: [9:3]; default: 2; + * configure cycles to lower cmd after voltage is changed to 1.8V. + */ +#define HINF_PST_END_CMD_LOW_VALUE 0x0000007FU +#define HINF_PST_END_CMD_LOW_VALUE_M (HINF_PST_END_CMD_LOW_VALUE_V << HINF_PST_END_CMD_LOW_VALUE_S) +#define HINF_PST_END_CMD_LOW_VALUE_V 0x0000007FU +#define HINF_PST_END_CMD_LOW_VALUE_S 3 +/** HINF_PST_END_DATA_LOW_VALUE : R/W; bitpos: [15:10]; default: 2; + * configure cycles to lower data after voltage is changed to 1.8V. + */ +#define HINF_PST_END_DATA_LOW_VALUE 0x0000003FU +#define HINF_PST_END_DATA_LOW_VALUE_M (HINF_PST_END_DATA_LOW_VALUE_V << HINF_PST_END_DATA_LOW_VALUE_S) +#define HINF_PST_END_DATA_LOW_VALUE_V 0x0000003FU +#define HINF_PST_END_DATA_LOW_VALUE_S 10 +/** HINF_SDCLK_STOP_THRES : R/W; bitpos: [26:16]; default: 1400; + * Configure the number of cycles of module clk to judge sdclk has stopped + */ +#define HINF_SDCLK_STOP_THRES 0x000007FFU +#define HINF_SDCLK_STOP_THRES_M (HINF_SDCLK_STOP_THRES_V << HINF_SDCLK_STOP_THRES_S) +#define HINF_SDCLK_STOP_THRES_V 0x000007FFU +#define HINF_SDCLK_STOP_THRES_S 16 +/** HINF_SAMPLE_CLK_DIVIDER : R/W; bitpos: [31:28]; default: 1; + * module clk divider to sample sdclk + */ +#define HINF_SAMPLE_CLK_DIVIDER 0x0000000FU +#define HINF_SAMPLE_CLK_DIVIDER_M (HINF_SAMPLE_CLK_DIVIDER_V << HINF_SAMPLE_CLK_DIVIDER_S) +#define HINF_SAMPLE_CLK_DIVIDER_V 0x0000000FU +#define HINF_SAMPLE_CLK_DIVIDER_S 28 + +/** HINF_CFG_UPDATE_REG register + * update sdio configurations + */ +#define HINF_CFG_UPDATE_REG (DR_REG_HINF_BASE + 0xc) +/** HINF_CONF_UPDATE : WT; bitpos: [0]; default: 0; + * update the timing configurations + */ +#define HINF_CONF_UPDATE (BIT(0)) +#define HINF_CONF_UPDATE_M (HINF_CONF_UPDATE_V << HINF_CONF_UPDATE_S) +#define HINF_CONF_UPDATE_V 0x00000001U +#define HINF_CONF_UPDATE_S 0 + +/** HINF_CFG_DATA7_REG register + * SDIO configuration register + */ +#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1c) +/** HINF_PIN_STATE : R/W; bitpos: [7:0]; default: 0; + * configure cis addr 318 and 574 + */ +#define HINF_PIN_STATE 0x000000FFU +#define HINF_PIN_STATE_M (HINF_PIN_STATE_V << HINF_PIN_STATE_S) +#define HINF_PIN_STATE_V 0x000000FFU +#define HINF_PIN_STATE_S 0 +/** HINF_CHIP_STATE : R/W; bitpos: [15:8]; default: 0; + * configure cis addr 312, 315, 568 and 571 + */ +#define HINF_CHIP_STATE 0x000000FFU +#define HINF_CHIP_STATE_M (HINF_CHIP_STATE_V << HINF_CHIP_STATE_S) +#define HINF_CHIP_STATE_V 0x000000FFU +#define HINF_CHIP_STATE_S 8 +/** HINF_SDIO_RST : R/W; bitpos: [16]; default: 0; + * soft reset control for sdio module + */ +#define HINF_SDIO_RST (BIT(16)) +#define HINF_SDIO_RST_M (HINF_SDIO_RST_V << HINF_SDIO_RST_S) +#define HINF_SDIO_RST_V 0x00000001U +#define HINF_SDIO_RST_S 16 +/** HINF_SDIO_IOREADY0 : R/W; bitpos: [17]; default: 1; + * sdio io ready, high enable + */ +#define HINF_SDIO_IOREADY0 (BIT(17)) +#define HINF_SDIO_IOREADY0_M (HINF_SDIO_IOREADY0_V << HINF_SDIO_IOREADY0_S) +#define HINF_SDIO_IOREADY0_V 0x00000001U +#define HINF_SDIO_IOREADY0_S 17 +/** HINF_SDIO_MEM_PD : R/W; bitpos: [18]; default: 0; + * sdio memory power down, high active + */ +#define HINF_SDIO_MEM_PD (BIT(18)) +#define HINF_SDIO_MEM_PD_M (HINF_SDIO_MEM_PD_V << HINF_SDIO_MEM_PD_S) +#define HINF_SDIO_MEM_PD_V 0x00000001U +#define HINF_SDIO_MEM_PD_S 18 +/** HINF_ESDIO_DATA1_INT_EN : R/W; bitpos: [19]; default: 0; + * enable sdio interrupt on data1 line + */ +#define HINF_ESDIO_DATA1_INT_EN (BIT(19)) +#define HINF_ESDIO_DATA1_INT_EN_M (HINF_ESDIO_DATA1_INT_EN_V << HINF_ESDIO_DATA1_INT_EN_S) +#define HINF_ESDIO_DATA1_INT_EN_V 0x00000001U +#define HINF_ESDIO_DATA1_INT_EN_S 19 +/** HINF_SDIO_SWITCH_VOLT_SW : R/W; bitpos: [20]; default: 0; + * control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V + */ +#define HINF_SDIO_SWITCH_VOLT_SW (BIT(20)) +#define HINF_SDIO_SWITCH_VOLT_SW_M (HINF_SDIO_SWITCH_VOLT_SW_V << HINF_SDIO_SWITCH_VOLT_SW_S) +#define HINF_SDIO_SWITCH_VOLT_SW_V 0x00000001U +#define HINF_SDIO_SWITCH_VOLT_SW_S 20 +/** HINF_DDR50_BLK_LEN_FIX_EN : R/W; bitpos: [21]; default: 0; + * enable block length to be fixed to 512 bytes in ddr50 mode + */ +#define HINF_DDR50_BLK_LEN_FIX_EN (BIT(21)) +#define HINF_DDR50_BLK_LEN_FIX_EN_M (HINF_DDR50_BLK_LEN_FIX_EN_V << HINF_DDR50_BLK_LEN_FIX_EN_S) +#define HINF_DDR50_BLK_LEN_FIX_EN_V 0x00000001U +#define HINF_DDR50_BLK_LEN_FIX_EN_S 21 +/** HINF_CLK_EN : R/W; bitpos: [22]; default: 0; + * sdio apb clock for configuration force on control:0-gating,1-force on. + */ +#define HINF_CLK_EN (BIT(22)) +#define HINF_CLK_EN_M (HINF_CLK_EN_V << HINF_CLK_EN_S) +#define HINF_CLK_EN_V 0x00000001U +#define HINF_CLK_EN_S 22 +/** HINF_SDDR50 : R/W; bitpos: [23]; default: 1; + * configure if support sdr50 mode in cccr + */ +#define HINF_SDDR50 (BIT(23)) +#define HINF_SDDR50_M (HINF_SDDR50_V << HINF_SDDR50_S) +#define HINF_SDDR50_V 0x00000001U +#define HINF_SDDR50_S 23 +/** HINF_SSDR104 : R/W; bitpos: [24]; default: 1; + * configure if support sdr104 mode in cccr + */ +#define HINF_SSDR104 (BIT(24)) +#define HINF_SSDR104_M (HINF_SSDR104_V << HINF_SSDR104_S) +#define HINF_SSDR104_V 0x00000001U +#define HINF_SSDR104_S 24 +/** HINF_SSDR50 : R/W; bitpos: [25]; default: 1; + * configure if support ddr50 mode in cccr + */ +#define HINF_SSDR50 (BIT(25)) +#define HINF_SSDR50_M (HINF_SSDR50_V << HINF_SSDR50_S) +#define HINF_SSDR50_V 0x00000001U +#define HINF_SSDR50_S 25 +/** HINF_SDTD : R/W; bitpos: [26]; default: 0; + * configure if support driver type D in cccr + */ +#define HINF_SDTD (BIT(26)) +#define HINF_SDTD_M (HINF_SDTD_V << HINF_SDTD_S) +#define HINF_SDTD_V 0x00000001U +#define HINF_SDTD_S 26 +/** HINF_SDTA : R/W; bitpos: [27]; default: 0; + * configure if support driver type A in cccr + */ +#define HINF_SDTA (BIT(27)) +#define HINF_SDTA_M (HINF_SDTA_V << HINF_SDTA_S) +#define HINF_SDTA_V 0x00000001U +#define HINF_SDTA_S 27 +/** HINF_SDTC : R/W; bitpos: [28]; default: 0; + * configure if support driver type C in cccr + */ +#define HINF_SDTC (BIT(28)) +#define HINF_SDTC_M (HINF_SDTC_V << HINF_SDTC_S) +#define HINF_SDTC_V 0x00000001U +#define HINF_SDTC_S 28 +/** HINF_SAI : R/W; bitpos: [29]; default: 1; + * configure if support asynchronous interrupt in cccr + */ +#define HINF_SAI (BIT(29)) +#define HINF_SAI_M (HINF_SAI_V << HINF_SAI_S) +#define HINF_SAI_V 0x00000001U +#define HINF_SAI_S 29 +/** HINF_SDIO_WAKEUP_CLR : WT; bitpos: [30]; default: 0; + * clear sdio_wake_up signal after the chip wakes up + */ +#define HINF_SDIO_WAKEUP_CLR (BIT(30)) +#define HINF_SDIO_WAKEUP_CLR_M (HINF_SDIO_WAKEUP_CLR_V << HINF_SDIO_WAKEUP_CLR_S) +#define HINF_SDIO_WAKEUP_CLR_V 0x00000001U +#define HINF_SDIO_WAKEUP_CLR_S 30 + +/** HINF_CIS_CONF_W0_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W0_REG (DR_REG_HINF_BASE + 0x20) +/** HINF_CIS_CONF_W0 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 39~36 + */ +#define HINF_CIS_CONF_W0 0xFFFFFFFFU +#define HINF_CIS_CONF_W0_M (HINF_CIS_CONF_W0_V << HINF_CIS_CONF_W0_S) +#define HINF_CIS_CONF_W0_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W0_S 0 + +/** HINF_CIS_CONF_W1_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W1_REG (DR_REG_HINF_BASE + 0x24) +/** HINF_CIS_CONF_W1 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 43~40 + */ +#define HINF_CIS_CONF_W1 0xFFFFFFFFU +#define HINF_CIS_CONF_W1_M (HINF_CIS_CONF_W1_V << HINF_CIS_CONF_W1_S) +#define HINF_CIS_CONF_W1_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W1_S 0 + +/** HINF_CIS_CONF_W2_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W2_REG (DR_REG_HINF_BASE + 0x28) +/** HINF_CIS_CONF_W2 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 47~44 + */ +#define HINF_CIS_CONF_W2 0xFFFFFFFFU +#define HINF_CIS_CONF_W2_M (HINF_CIS_CONF_W2_V << HINF_CIS_CONF_W2_S) +#define HINF_CIS_CONF_W2_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W2_S 0 + +/** HINF_CIS_CONF_W3_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W3_REG (DR_REG_HINF_BASE + 0x2c) +/** HINF_CIS_CONF_W3 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 51~48 + */ +#define HINF_CIS_CONF_W3 0xFFFFFFFFU +#define HINF_CIS_CONF_W3_M (HINF_CIS_CONF_W3_V << HINF_CIS_CONF_W3_S) +#define HINF_CIS_CONF_W3_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W3_S 0 + +/** HINF_CIS_CONF_W4_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W4_REG (DR_REG_HINF_BASE + 0x30) +/** HINF_CIS_CONF_W4 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 55~52 + */ +#define HINF_CIS_CONF_W4 0xFFFFFFFFU +#define HINF_CIS_CONF_W4_M (HINF_CIS_CONF_W4_V << HINF_CIS_CONF_W4_S) +#define HINF_CIS_CONF_W4_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W4_S 0 + +/** HINF_CIS_CONF_W5_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W5_REG (DR_REG_HINF_BASE + 0x34) +/** HINF_CIS_CONF_W5 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 59~56 + */ +#define HINF_CIS_CONF_W5 0xFFFFFFFFU +#define HINF_CIS_CONF_W5_M (HINF_CIS_CONF_W5_V << HINF_CIS_CONF_W5_S) +#define HINF_CIS_CONF_W5_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W5_S 0 + +/** HINF_CIS_CONF_W6_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W6_REG (DR_REG_HINF_BASE + 0x38) +/** HINF_CIS_CONF_W6 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 63~60 + */ +#define HINF_CIS_CONF_W6 0xFFFFFFFFU +#define HINF_CIS_CONF_W6_M (HINF_CIS_CONF_W6_V << HINF_CIS_CONF_W6_S) +#define HINF_CIS_CONF_W6_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W6_S 0 + +/** HINF_CIS_CONF_W7_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W7_REG (DR_REG_HINF_BASE + 0x3c) +/** HINF_CIS_CONF_W7 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 67~64 + */ +#define HINF_CIS_CONF_W7 0xFFFFFFFFU +#define HINF_CIS_CONF_W7_M (HINF_CIS_CONF_W7_V << HINF_CIS_CONF_W7_S) +#define HINF_CIS_CONF_W7_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W7_S 0 + +/** HINF_CFG_DATA16_REG register + * SDIO cis configuration register + */ +#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40) +/** HINF_DEVICE_ID_FN2 : R/W; bitpos: [15:0]; default: 30583; + * configure device id of function2 in cis + */ +#define HINF_DEVICE_ID_FN2 0x0000FFFFU +#define HINF_DEVICE_ID_FN2_M (HINF_DEVICE_ID_FN2_V << HINF_DEVICE_ID_FN2_S) +#define HINF_DEVICE_ID_FN2_V 0x0000FFFFU +#define HINF_DEVICE_ID_FN2_S 0 +/** HINF_USER_ID_FN2 : R/W; bitpos: [31:16]; default: 146; + * configure user id of function2 in cis + */ +#define HINF_USER_ID_FN2 0x0000FFFFU +#define HINF_USER_ID_FN2_M (HINF_USER_ID_FN2_V << HINF_USER_ID_FN2_S) +#define HINF_USER_ID_FN2_V 0x0000FFFFU +#define HINF_USER_ID_FN2_S 16 + +/** HINF_CFG_UHS1_INT_MODE_REG register + * configure int to start and end ahead of time in uhs1 mode + */ +#define HINF_CFG_UHS1_INT_MODE_REG (DR_REG_HINF_BASE + 0x44) +/** HINF_INTOE_END_AHEAD_MODE : R/W; bitpos: [1:0]; default: 0; + * intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ +#define HINF_INTOE_END_AHEAD_MODE 0x00000003U +#define HINF_INTOE_END_AHEAD_MODE_M (HINF_INTOE_END_AHEAD_MODE_V << HINF_INTOE_END_AHEAD_MODE_S) +#define HINF_INTOE_END_AHEAD_MODE_V 0x00000003U +#define HINF_INTOE_END_AHEAD_MODE_S 0 +/** HINF_INT_END_AHEAD_MODE : R/W; bitpos: [3:2]; default: 0; + * int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ +#define HINF_INT_END_AHEAD_MODE 0x00000003U +#define HINF_INT_END_AHEAD_MODE_M (HINF_INT_END_AHEAD_MODE_V << HINF_INT_END_AHEAD_MODE_S) +#define HINF_INT_END_AHEAD_MODE_V 0x00000003U +#define HINF_INT_END_AHEAD_MODE_S 2 +/** HINF_INTOE_ST_AHEAD_MODE : R/W; bitpos: [5:4]; default: 0; + * intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ +#define HINF_INTOE_ST_AHEAD_MODE 0x00000003U +#define HINF_INTOE_ST_AHEAD_MODE_M (HINF_INTOE_ST_AHEAD_MODE_V << HINF_INTOE_ST_AHEAD_MODE_S) +#define HINF_INTOE_ST_AHEAD_MODE_V 0x00000003U +#define HINF_INTOE_ST_AHEAD_MODE_S 4 +/** HINF_INT_ST_AHEAD_MODE : R/W; bitpos: [7:6]; default: 0; + * int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ +#define HINF_INT_ST_AHEAD_MODE 0x00000003U +#define HINF_INT_ST_AHEAD_MODE_M (HINF_INT_ST_AHEAD_MODE_V << HINF_INT_ST_AHEAD_MODE_S) +#define HINF_INT_ST_AHEAD_MODE_V 0x00000003U +#define HINF_INT_ST_AHEAD_MODE_S 6 + +/** HINF_CONF_STATUS_REG register + * func0 config0 status + */ +#define HINF_CONF_STATUS_REG (DR_REG_HINF_BASE + 0x54) +/** HINF_FUNC0_CONFIG0 : RO; bitpos: [7:0]; default: 0; + * func0 config0 (addr: 0x20f0 ) status + */ +#define HINF_FUNC0_CONFIG0 0x000000FFU +#define HINF_FUNC0_CONFIG0_M (HINF_FUNC0_CONFIG0_V << HINF_FUNC0_CONFIG0_S) +#define HINF_FUNC0_CONFIG0_V 0x000000FFU +#define HINF_FUNC0_CONFIG0_S 0 +/** HINF_SDR25_ST : RO; bitpos: [8]; default: 0; + * sdr25 status + */ +#define HINF_SDR25_ST (BIT(8)) +#define HINF_SDR25_ST_M (HINF_SDR25_ST_V << HINF_SDR25_ST_S) +#define HINF_SDR25_ST_V 0x00000001U +#define HINF_SDR25_ST_S 8 +/** HINF_SDR50_ST : RO; bitpos: [9]; default: 0; + * sdr50 status + */ +#define HINF_SDR50_ST (BIT(9)) +#define HINF_SDR50_ST_M (HINF_SDR50_ST_V << HINF_SDR50_ST_S) +#define HINF_SDR50_ST_V 0x00000001U +#define HINF_SDR50_ST_S 9 +/** HINF_SDR104_ST : RO; bitpos: [10]; default: 0; + * sdr104 status + */ +#define HINF_SDR104_ST (BIT(10)) +#define HINF_SDR104_ST_M (HINF_SDR104_ST_V << HINF_SDR104_ST_S) +#define HINF_SDR104_ST_V 0x00000001U +#define HINF_SDR104_ST_S 10 +/** HINF_DDR50_ST : RO; bitpos: [11]; default: 0; + * ddr50 status + */ +#define HINF_DDR50_ST (BIT(11)) +#define HINF_DDR50_ST_M (HINF_DDR50_ST_V << HINF_DDR50_ST_S) +#define HINF_DDR50_ST_V 0x00000001U +#define HINF_DDR50_ST_S 11 +/** HINF_TUNE_ST : RO; bitpos: [14:12]; default: 0; + * tune_st fsm status + */ +#define HINF_TUNE_ST 0x00000007U +#define HINF_TUNE_ST_M (HINF_TUNE_ST_V << HINF_TUNE_ST_S) +#define HINF_TUNE_ST_V 0x00000007U +#define HINF_TUNE_ST_S 12 +/** HINF_SDIO_SWITCH_VOLT_ST : RO; bitpos: [15]; default: 0; + * sdio switch voltage status:0-3.3V, 1-1.8V. + */ +#define HINF_SDIO_SWITCH_VOLT_ST (BIT(15)) +#define HINF_SDIO_SWITCH_VOLT_ST_M (HINF_SDIO_SWITCH_VOLT_ST_V << HINF_SDIO_SWITCH_VOLT_ST_S) +#define HINF_SDIO_SWITCH_VOLT_ST_V 0x00000001U +#define HINF_SDIO_SWITCH_VOLT_ST_S 15 +/** HINF_SDIO_SWITCH_END : RO; bitpos: [16]; default: 0; + * sdio switch voltage ldo ready + */ +#define HINF_SDIO_SWITCH_END (BIT(16)) +#define HINF_SDIO_SWITCH_END_M (HINF_SDIO_SWITCH_END_V << HINF_SDIO_SWITCH_END_S) +#define HINF_SDIO_SWITCH_END_V 0x00000001U +#define HINF_SDIO_SWITCH_END_S 16 + +/** HINF_SDIO_SLAVE_ECO_LOW_REG register + * sdio_slave redundant control registers + */ +#define HINF_SDIO_SLAVE_ECO_LOW_REG (DR_REG_HINF_BASE + 0xa4) +/** HINF_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0; + * redundant registers for sdio_slave + */ +#define HINF_RDN_ECO_LOW 0xFFFFFFFFU +#define HINF_RDN_ECO_LOW_M (HINF_RDN_ECO_LOW_V << HINF_RDN_ECO_LOW_S) +#define HINF_RDN_ECO_LOW_V 0xFFFFFFFFU +#define HINF_RDN_ECO_LOW_S 0 + +/** HINF_SDIO_SLAVE_ECO_HIGH_REG register + * sdio_slave redundant control registers + */ +#define HINF_SDIO_SLAVE_ECO_HIGH_REG (DR_REG_HINF_BASE + 0xa8) +/** HINF_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295; + * redundant registers for sdio_slave + */ +#define HINF_RDN_ECO_HIGH 0xFFFFFFFFU +#define HINF_RDN_ECO_HIGH_M (HINF_RDN_ECO_HIGH_V << HINF_RDN_ECO_HIGH_S) +#define HINF_RDN_ECO_HIGH_V 0xFFFFFFFFU +#define HINF_RDN_ECO_HIGH_S 0 + +/** HINF_SDIO_SLAVE_ECO_CONF_REG register + * sdio_slave redundant control registers + */ +#define HINF_SDIO_SLAVE_ECO_CONF_REG (DR_REG_HINF_BASE + 0xac) +/** HINF_SDIO_SLAVE_RDN_RESULT : RO; bitpos: [0]; default: 0; + * redundant registers for sdio_slave + */ +#define HINF_SDIO_SLAVE_RDN_RESULT (BIT(0)) +#define HINF_SDIO_SLAVE_RDN_RESULT_M (HINF_SDIO_SLAVE_RDN_RESULT_V << HINF_SDIO_SLAVE_RDN_RESULT_S) +#define HINF_SDIO_SLAVE_RDN_RESULT_V 0x00000001U +#define HINF_SDIO_SLAVE_RDN_RESULT_S 0 +/** HINF_SDIO_SLAVE_RDN_ENA : R/W; bitpos: [1]; default: 0; + * redundant registers for sdio_slave + */ +#define HINF_SDIO_SLAVE_RDN_ENA (BIT(1)) +#define HINF_SDIO_SLAVE_RDN_ENA_M (HINF_SDIO_SLAVE_RDN_ENA_V << HINF_SDIO_SLAVE_RDN_ENA_S) +#define HINF_SDIO_SLAVE_RDN_ENA_V 0x00000001U +#define HINF_SDIO_SLAVE_RDN_ENA_S 1 +/** HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT : RO; bitpos: [2]; default: 0; + * redundant registers for sdio_slave + */ +#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT (BIT(2)) +#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_M (HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_V << HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_S) +#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_V 0x00000001U +#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_S 2 +/** HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA : R/W; bitpos: [3]; default: 0; + * redundant registers for sdio_slave + */ +#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA (BIT(3)) +#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_M (HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_V << HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_S) +#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_V 0x00000001U +#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_S 3 +/** HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT : RO; bitpos: [4]; default: 0; + * redundant registers for sdio_slave + */ +#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT (BIT(4)) +#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_M (HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_V << HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_S) +#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_V 0x00000001U +#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_S 4 +/** HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA : R/W; bitpos: [5]; default: 0; + * redundant registers for sdio_slave + */ +#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA (BIT(5)) +#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_M (HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_V << HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_S) +#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_V 0x00000001U +#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_S 5 + +/** HINF_SDIO_SLAVE_LDO_CONF_REG register + * sdio slave ldo control register + */ +#define HINF_SDIO_SLAVE_LDO_CONF_REG (DR_REG_HINF_BASE + 0xb0) +/** HINF_LDO_READY_CTL_IN_EN : R/W; bitpos: [0]; default: 0; + * control ldo ready signal by sdio slave itself + */ +#define HINF_LDO_READY_CTL_IN_EN (BIT(0)) +#define HINF_LDO_READY_CTL_IN_EN_M (HINF_LDO_READY_CTL_IN_EN_V << HINF_LDO_READY_CTL_IN_EN_S) +#define HINF_LDO_READY_CTL_IN_EN_V 0x00000001U +#define HINF_LDO_READY_CTL_IN_EN_S 0 +/** HINF_LDO_READY_THRES : R/W; bitpos: [5:1]; default: 10; + * configure ldo ready counting threshold value, the actual counting target is + * 2^(ldo_ready_thres)-1 + */ +#define HINF_LDO_READY_THRES 0x0000001FU +#define HINF_LDO_READY_THRES_M (HINF_LDO_READY_THRES_V << HINF_LDO_READY_THRES_S) +#define HINF_LDO_READY_THRES_V 0x0000001FU +#define HINF_LDO_READY_THRES_S 1 +/** HINF_LDO_READY_IGNORE_EN : R/W; bitpos: [6]; default: 0; + * ignore ldo ready signal + */ +#define HINF_LDO_READY_IGNORE_EN (BIT(6)) +#define HINF_LDO_READY_IGNORE_EN_M (HINF_LDO_READY_IGNORE_EN_V << HINF_LDO_READY_IGNORE_EN_S) +#define HINF_LDO_READY_IGNORE_EN_V 0x00000001U +#define HINF_LDO_READY_IGNORE_EN_S 6 + +/** HINF_SDIO_DATE_REG register + * ******* Description *********** + */ +#define HINF_SDIO_DATE_REG (DR_REG_HINF_BASE + 0xfc) +/** HINF_SDIO_DATE : R/W; bitpos: [31:0]; default: 35664208; + * sdio version date. + */ +#define HINF_SDIO_DATE 0xFFFFFFFFU +#define HINF_SDIO_DATE_M (HINF_SDIO_DATE_V << HINF_SDIO_DATE_S) +#define HINF_SDIO_DATE_V 0xFFFFFFFFU +#define HINF_SDIO_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/hinf_struct.h b/components/soc/esp32c6/include/soc/hinf_struct.h new file mode 100644 index 0000000000..320fd34600 --- /dev/null +++ b/components/soc/esp32c6/include/soc/hinf_struct.h @@ -0,0 +1,555 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration registers */ +/** Type of cfg_data0 register + * Configure sdio cis content + */ +typedef union { + struct { + /** device_id_fn1 : R/W; bitpos: [15:0]; default: 26214; + * configure device id of function1 in cis + */ + uint32_t device_id_fn1:16; + /** user_id_fn1 : R/W; bitpos: [31:16]; default: 146; + * configure user id of function1 in cis + */ + uint32_t user_id_fn1:16; + }; + uint32_t val; +} hinf_cfg_data0_reg_t; + +/** Type of cfg_data1 register + * SDIO configuration register + */ +typedef union { + struct { + /** sdio_enable : R/W; bitpos: [0]; default: 1; + * Sdio clock enable + */ + uint32_t sdio_enable:1; + /** sdio_ioready1 : R/W; bitpos: [1]; default: 0; + * sdio function1 io ready signal in cis + */ + uint32_t sdio_ioready1:1; + /** highspeed_enable : R/W; bitpos: [2]; default: 0; + * Highspeed enable in cccr + */ + uint32_t highspeed_enable:1; + /** highspeed_mode : RO; bitpos: [3]; default: 0; + * highspeed mode status in cccr + */ + uint32_t highspeed_mode:1; + /** sdio_cd_enable : R/W; bitpos: [4]; default: 1; + * sdio card detect enable + */ + uint32_t sdio_cd_enable:1; + /** sdio_ioready2 : R/W; bitpos: [5]; default: 0; + * sdio function1 io ready signal in cis + */ + uint32_t sdio_ioready2:1; + /** sdio_int_mask : R/W; bitpos: [6]; default: 0; + * mask sdio interrupt in cccr, high active + */ + uint32_t sdio_int_mask:1; + /** ioenable2 : RO; bitpos: [7]; default: 0; + * ioe2 status in cccr + */ + uint32_t ioenable2:1; + /** cd_disable : RO; bitpos: [8]; default: 0; + * card disable status in cccr + */ + uint32_t cd_disable:1; + /** func1_eps : RO; bitpos: [9]; default: 0; + * function1 eps status in fbr + */ + uint32_t func1_eps:1; + /** emp : RO; bitpos: [10]; default: 0; + * empc status in cccr + */ + uint32_t emp:1; + /** ioenable1 : RO; bitpos: [11]; default: 0; + * ioe1 status in cccr + */ + uint32_t ioenable1:1; + /** sdio_ver : R/W; bitpos: [23:12]; default: 562; + * sdio version in cccr + */ + uint32_t sdio_ver:12; + /** func2_eps : RO; bitpos: [24]; default: 0; + * function2 eps status in fbr + */ + uint32_t func2_eps:1; + /** sdio20_conf : R/W; bitpos: [31:25]; default: 0; + * [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat + * in delayed cycles control,0:no delay, 1:delay 1 cycle. + * [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed + * mode. + * [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when + * [12]=0,posedge when highspeed mode enable. + * [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay. + * [28]: sdio data pad pull up enable + */ + uint32_t sdio20_conf:7; + }; + uint32_t val; +} hinf_cfg_data1_reg_t; + +/** Type of cfg_timing register + * Timing configuration registers + */ +typedef union { + struct { + /** ncrc : R/W; bitpos: [2:0]; default: 2; + * configure Ncrc parameter in sdr50/104 mode, no more than 6. + */ + uint32_t ncrc:3; + /** pst_end_cmd_low_value : R/W; bitpos: [9:3]; default: 2; + * configure cycles to lower cmd after voltage is changed to 1.8V. + */ + uint32_t pst_end_cmd_low_value:7; + /** pst_end_data_low_value : R/W; bitpos: [15:10]; default: 2; + * configure cycles to lower data after voltage is changed to 1.8V. + */ + uint32_t pst_end_data_low_value:6; + /** sdclk_stop_thres : R/W; bitpos: [26:16]; default: 1400; + * Configure the number of cycles of module clk to judge sdclk has stopped + */ + uint32_t sdclk_stop_thres:11; + uint32_t reserved_27:1; + /** sample_clk_divider : R/W; bitpos: [31:28]; default: 1; + * module clk divider to sample sdclk + */ + uint32_t sample_clk_divider:4; + }; + uint32_t val; +} hinf_cfg_timing_reg_t; + +/** Type of cfg_update register + * update sdio configurations + */ +typedef union { + struct { + /** conf_update : WT; bitpos: [0]; default: 0; + * update the timing configurations + */ + uint32_t conf_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hinf_cfg_update_reg_t; + +/** Type of cfg_data7 register + * SDIO configuration register + */ +typedef union { + struct { + /** pin_state : R/W; bitpos: [7:0]; default: 0; + * configure cis addr 318 and 574 + */ + uint32_t pin_state:8; + /** chip_state : R/W; bitpos: [15:8]; default: 0; + * configure cis addr 312, 315, 568 and 571 + */ + uint32_t chip_state:8; + /** sdio_rst : R/W; bitpos: [16]; default: 0; + * soft reset control for sdio module + */ + uint32_t sdio_rst:1; + /** sdio_ioready0 : R/W; bitpos: [17]; default: 1; + * sdio io ready, high enable + */ + uint32_t sdio_ioready0:1; + /** sdio_mem_pd : R/W; bitpos: [18]; default: 0; + * sdio memory power down, high active + */ + uint32_t sdio_mem_pd:1; + /** esdio_data1_int_en : R/W; bitpos: [19]; default: 0; + * enable sdio interrupt on data1 line + */ + uint32_t esdio_data1_int_en:1; + /** sdio_switch_volt_sw : R/W; bitpos: [20]; default: 0; + * control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V + */ + uint32_t sdio_switch_volt_sw:1; + /** ddr50_blk_len_fix_en : R/W; bitpos: [21]; default: 0; + * enable block length to be fixed to 512 bytes in ddr50 mode + */ + uint32_t ddr50_blk_len_fix_en:1; + /** clk_en : R/W; bitpos: [22]; default: 0; + * sdio apb clock for configuration force on control:0-gating,1-force on. + */ + uint32_t clk_en:1; + /** sddr50 : R/W; bitpos: [23]; default: 1; + * configure if support sdr50 mode in cccr + */ + uint32_t sddr50:1; + /** ssdr104 : R/W; bitpos: [24]; default: 1; + * configure if support sdr104 mode in cccr + */ + uint32_t ssdr104:1; + /** ssdr50 : R/W; bitpos: [25]; default: 1; + * configure if support ddr50 mode in cccr + */ + uint32_t ssdr50:1; + /** sdtd : R/W; bitpos: [26]; default: 0; + * configure if support driver type D in cccr + */ + uint32_t sdtd:1; + /** sdta : R/W; bitpos: [27]; default: 0; + * configure if support driver type A in cccr + */ + uint32_t sdta:1; + /** sdtc : R/W; bitpos: [28]; default: 0; + * configure if support driver type C in cccr + */ + uint32_t sdtc:1; + /** sai : R/W; bitpos: [29]; default: 1; + * configure if support asynchronous interrupt in cccr + */ + uint32_t sai:1; + /** sdio_wakeup_clr : WT; bitpos: [30]; default: 0; + * clear sdio_wake_up signal after the chip wakes up + */ + uint32_t sdio_wakeup_clr:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} hinf_cfg_data7_reg_t; + +/** Type of cis_conf_w0 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w0 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 39~36 + */ + uint32_t cis_conf_w0:32; + }; + uint32_t val; +} hinf_cis_conf_w0_reg_t; + +/** Type of cis_conf_w1 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w1 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 43~40 + */ + uint32_t cis_conf_w1:32; + }; + uint32_t val; +} hinf_cis_conf_w1_reg_t; + +/** Type of cis_conf_w2 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w2 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 47~44 + */ + uint32_t cis_conf_w2:32; + }; + uint32_t val; +} hinf_cis_conf_w2_reg_t; + +/** Type of cis_conf_w3 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w3 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 51~48 + */ + uint32_t cis_conf_w3:32; + }; + uint32_t val; +} hinf_cis_conf_w3_reg_t; + +/** Type of cis_conf_w4 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w4 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 55~52 + */ + uint32_t cis_conf_w4:32; + }; + uint32_t val; +} hinf_cis_conf_w4_reg_t; + +/** Type of cis_conf_w5 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w5 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 59~56 + */ + uint32_t cis_conf_w5:32; + }; + uint32_t val; +} hinf_cis_conf_w5_reg_t; + +/** Type of cis_conf_w6 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w6 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 63~60 + */ + uint32_t cis_conf_w6:32; + }; + uint32_t val; +} hinf_cis_conf_w6_reg_t; + +/** Type of cis_conf_w7 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w7 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 67~64 + */ + uint32_t cis_conf_w7:32; + }; + uint32_t val; +} hinf_cis_conf_w7_reg_t; + +/** Type of cfg_data16 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** device_id_fn2 : R/W; bitpos: [15:0]; default: 30583; + * configure device id of function2 in cis + */ + uint32_t device_id_fn2:16; + /** user_id_fn2 : R/W; bitpos: [31:16]; default: 146; + * configure user id of function2 in cis + */ + uint32_t user_id_fn2:16; + }; + uint32_t val; +} hinf_cfg_data16_reg_t; + +/** Type of cfg_uhs1_int_mode register + * configure int to start and end ahead of time in uhs1 mode + */ +typedef union { + struct { + /** intoe_end_ahead_mode : R/W; bitpos: [1:0]; default: 0; + * intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ + uint32_t intoe_end_ahead_mode:2; + /** int_end_ahead_mode : R/W; bitpos: [3:2]; default: 0; + * int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ + uint32_t int_end_ahead_mode:2; + /** intoe_st_ahead_mode : R/W; bitpos: [5:4]; default: 0; + * intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ + uint32_t intoe_st_ahead_mode:2; + /** int_st_ahead_mode : R/W; bitpos: [7:6]; default: 0; + * int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ + uint32_t int_st_ahead_mode:2; + uint32_t reserved_8:24; + }; + uint32_t val; +} hinf_cfg_uhs1_int_mode_reg_t; + +/** Type of sdio_slave_eco_low register + * sdio_slave redundant control registers + */ +typedef union { + struct { + /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0; + * redundant registers for sdio_slave + */ + uint32_t rdn_eco_low:32; + }; + uint32_t val; +} hinf_sdio_slave_eco_low_reg_t; + +/** Type of sdio_slave_eco_high register + * sdio_slave redundant control registers + */ +typedef union { + struct { + /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295; + * redundant registers for sdio_slave + */ + uint32_t rdn_eco_high:32; + }; + uint32_t val; +} hinf_sdio_slave_eco_high_reg_t; + +/** Type of sdio_slave_eco_conf register + * sdio_slave redundant control registers + */ +typedef union { + struct { + /** sdio_slave_rdn_result : RO; bitpos: [0]; default: 0; + * redundant registers for sdio_slave + */ + uint32_t sdio_slave_rdn_result:1; + /** sdio_slave_rdn_ena : R/W; bitpos: [1]; default: 0; + * redundant registers for sdio_slave + */ + uint32_t sdio_slave_rdn_ena:1; + /** sdio_slave_sdio_clk_rdn_result : RO; bitpos: [2]; default: 0; + * redundant registers for sdio_slave + */ + uint32_t sdio_slave_sdio_clk_rdn_result:1; + /** sdio_slave_sdio_clk_rdn_ena : R/W; bitpos: [3]; default: 0; + * redundant registers for sdio_slave + */ + uint32_t sdio_slave_sdio_clk_rdn_ena:1; + /** sdio_slave_sdclk_pad_rdn_result : RO; bitpos: [4]; default: 0; + * redundant registers for sdio_slave + */ + uint32_t sdio_slave_sdclk_pad_rdn_result:1; + /** sdio_slave_sdclk_pad_rdn_ena : R/W; bitpos: [5]; default: 0; + * redundant registers for sdio_slave + */ + uint32_t sdio_slave_sdclk_pad_rdn_ena:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} hinf_sdio_slave_eco_conf_reg_t; + +/** Type of sdio_slave_ldo_conf register + * sdio slave ldo control register + */ +typedef union { + struct { + /** ldo_ready_ctl_in_en : R/W; bitpos: [0]; default: 0; + * control ldo ready signal by sdio slave itself + */ + uint32_t ldo_ready_ctl_in_en:1; + /** ldo_ready_thres : R/W; bitpos: [5:1]; default: 10; + * configure ldo ready counting threshold value, the actual counting target is + * 2^(ldo_ready_thres)-1 + */ + uint32_t ldo_ready_thres:5; + /** ldo_ready_ignore_en : R/W; bitpos: [6]; default: 0; + * ignore ldo ready signal + */ + uint32_t ldo_ready_ignore_en:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} hinf_sdio_slave_ldo_conf_reg_t; + + +/** Group: Status registers */ +/** Type of conf_status register + * func0 config0 status + */ +typedef union { + struct { + /** func0_config0 : RO; bitpos: [7:0]; default: 0; + * func0 config0 (addr: 0x20f0 ) status + */ + uint32_t func0_config0:8; + /** sdr25_st : RO; bitpos: [8]; default: 0; + * sdr25 status + */ + uint32_t sdr25_st:1; + /** sdr50_st : RO; bitpos: [9]; default: 0; + * sdr50 status + */ + uint32_t sdr50_st:1; + /** sdr104_st : RO; bitpos: [10]; default: 0; + * sdr104 status + */ + uint32_t sdr104_st:1; + /** ddr50_st : RO; bitpos: [11]; default: 0; + * ddr50 status + */ + uint32_t ddr50_st:1; + /** tune_st : RO; bitpos: [14:12]; default: 0; + * tune_st fsm status + */ + uint32_t tune_st:3; + /** sdio_switch_volt_st : RO; bitpos: [15]; default: 0; + * sdio switch voltage status:0-3.3V, 1-1.8V. + */ + uint32_t sdio_switch_volt_st:1; + /** sdio_switch_end : RO; bitpos: [16]; default: 0; + * sdio switch voltage ldo ready + */ + uint32_t sdio_switch_end:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} hinf_conf_status_reg_t; + + +/** Group: Version register */ +/** Type of sdio_date register + * ******* Description *********** + */ +typedef union { + struct { + /** sdio_date : R/W; bitpos: [31:0]; default: 35664208; + * sdio version date. + */ + uint32_t sdio_date:32; + }; + uint32_t val; +} hinf_sdio_date_reg_t; + + +typedef struct hinf_dev_t { + volatile hinf_cfg_data0_reg_t cfg_data0; + volatile hinf_cfg_data1_reg_t cfg_data1; + volatile hinf_cfg_timing_reg_t cfg_timing; + volatile hinf_cfg_update_reg_t cfg_update; + uint32_t reserved_010[3]; + volatile hinf_cfg_data7_reg_t cfg_data7; + volatile hinf_cis_conf_w0_reg_t cis_conf_w0; + volatile hinf_cis_conf_w1_reg_t cis_conf_w1; + volatile hinf_cis_conf_w2_reg_t cis_conf_w2; + volatile hinf_cis_conf_w3_reg_t cis_conf_w3; + volatile hinf_cis_conf_w4_reg_t cis_conf_w4; + volatile hinf_cis_conf_w5_reg_t cis_conf_w5; + volatile hinf_cis_conf_w6_reg_t cis_conf_w6; + volatile hinf_cis_conf_w7_reg_t cis_conf_w7; + volatile hinf_cfg_data16_reg_t cfg_data16; + volatile hinf_cfg_uhs1_int_mode_reg_t cfg_uhs1_int_mode; + uint32_t reserved_048[3]; + volatile hinf_conf_status_reg_t conf_status; + uint32_t reserved_058[19]; + volatile hinf_sdio_slave_eco_low_reg_t sdio_slave_eco_low; + volatile hinf_sdio_slave_eco_high_reg_t sdio_slave_eco_high; + volatile hinf_sdio_slave_eco_conf_reg_t sdio_slave_eco_conf; + volatile hinf_sdio_slave_ldo_conf_reg_t sdio_slave_ldo_conf; + uint32_t reserved_0b4[18]; + volatile hinf_sdio_date_reg_t sdio_date; +} hinf_dev_t; + +extern hinf_dev_t HINF; + +#ifndef __cplusplus +_Static_assert(sizeof(hinf_dev_t) == 0x100, "Invalid size of hinf_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/hmac_reg.h b/components/soc/esp32c6/include/soc/hmac_reg.h new file mode 100644 index 0000000000..16d527ba0e --- /dev/null +++ b/components/soc/esp32c6/include/soc/hmac_reg.h @@ -0,0 +1,232 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HMAC_SET_START_REG register + * Process control register 0. + */ +#define HMAC_SET_START_REG (DR_REG_HMAC_BASE + 0x40) +/** HMAC_SET_START : WS; bitpos: [0]; default: 0; + * Start hmac operation. + */ +#define HMAC_SET_START (BIT(0)) +#define HMAC_SET_START_M (HMAC_SET_START_V << HMAC_SET_START_S) +#define HMAC_SET_START_V 0x00000001U +#define HMAC_SET_START_S 0 + +/** HMAC_SET_PARA_PURPOSE_REG register + * Configure purpose. + */ +#define HMAC_SET_PARA_PURPOSE_REG (DR_REG_HMAC_BASE + 0x44) +/** HMAC_PURPOSE_SET : WO; bitpos: [3:0]; default: 0; + * Set hmac parameter purpose. + */ +#define HMAC_PURPOSE_SET 0x0000000FU +#define HMAC_PURPOSE_SET_M (HMAC_PURPOSE_SET_V << HMAC_PURPOSE_SET_S) +#define HMAC_PURPOSE_SET_V 0x0000000FU +#define HMAC_PURPOSE_SET_S 0 + +/** HMAC_SET_PARA_KEY_REG register + * Configure key. + */ +#define HMAC_SET_PARA_KEY_REG (DR_REG_HMAC_BASE + 0x48) +/** HMAC_KEY_SET : WO; bitpos: [2:0]; default: 0; + * Set hmac parameter key. + */ +#define HMAC_KEY_SET 0x00000007U +#define HMAC_KEY_SET_M (HMAC_KEY_SET_V << HMAC_KEY_SET_S) +#define HMAC_KEY_SET_V 0x00000007U +#define HMAC_KEY_SET_S 0 + +/** HMAC_SET_PARA_FINISH_REG register + * Finish initial configuration. + */ +#define HMAC_SET_PARA_FINISH_REG (DR_REG_HMAC_BASE + 0x4c) +/** HMAC_SET_PARA_END : WS; bitpos: [0]; default: 0; + * Finish hmac configuration. + */ +#define HMAC_SET_PARA_END (BIT(0)) +#define HMAC_SET_PARA_END_M (HMAC_SET_PARA_END_V << HMAC_SET_PARA_END_S) +#define HMAC_SET_PARA_END_V 0x00000001U +#define HMAC_SET_PARA_END_S 0 + +/** HMAC_SET_MESSAGE_ONE_REG register + * Process control register 1. + */ +#define HMAC_SET_MESSAGE_ONE_REG (DR_REG_HMAC_BASE + 0x50) +/** HMAC_SET_TEXT_ONE : WS; bitpos: [0]; default: 0; + * Call SHA to calculate one message block. + */ +#define HMAC_SET_TEXT_ONE (BIT(0)) +#define HMAC_SET_TEXT_ONE_M (HMAC_SET_TEXT_ONE_V << HMAC_SET_TEXT_ONE_S) +#define HMAC_SET_TEXT_ONE_V 0x00000001U +#define HMAC_SET_TEXT_ONE_S 0 + +/** HMAC_SET_MESSAGE_ING_REG register + * Process control register 2. + */ +#define HMAC_SET_MESSAGE_ING_REG (DR_REG_HMAC_BASE + 0x54) +/** HMAC_SET_TEXT_ING : WS; bitpos: [0]; default: 0; + * Continue typical hmac. + */ +#define HMAC_SET_TEXT_ING (BIT(0)) +#define HMAC_SET_TEXT_ING_M (HMAC_SET_TEXT_ING_V << HMAC_SET_TEXT_ING_S) +#define HMAC_SET_TEXT_ING_V 0x00000001U +#define HMAC_SET_TEXT_ING_S 0 + +/** HMAC_SET_MESSAGE_END_REG register + * Process control register 3. + */ +#define HMAC_SET_MESSAGE_END_REG (DR_REG_HMAC_BASE + 0x58) +/** HMAC_SET_TEXT_END : WS; bitpos: [0]; default: 0; + * Start hardware padding. + */ +#define HMAC_SET_TEXT_END (BIT(0)) +#define HMAC_SET_TEXT_END_M (HMAC_SET_TEXT_END_V << HMAC_SET_TEXT_END_S) +#define HMAC_SET_TEXT_END_V 0x00000001U +#define HMAC_SET_TEXT_END_S 0 + +/** HMAC_SET_RESULT_FINISH_REG register + * Process control register 4. + */ +#define HMAC_SET_RESULT_FINISH_REG (DR_REG_HMAC_BASE + 0x5c) +/** HMAC_SET_RESULT_END : WS; bitpos: [0]; default: 0; + * After read result from upstream, then let hmac back to idle. + */ +#define HMAC_SET_RESULT_END (BIT(0)) +#define HMAC_SET_RESULT_END_M (HMAC_SET_RESULT_END_V << HMAC_SET_RESULT_END_S) +#define HMAC_SET_RESULT_END_V 0x00000001U +#define HMAC_SET_RESULT_END_S 0 + +/** HMAC_SET_INVALIDATE_JTAG_REG register + * Invalidate register 0. + */ +#define HMAC_SET_INVALIDATE_JTAG_REG (DR_REG_HMAC_BASE + 0x60) +/** HMAC_SET_INVALIDATE_JTAG : WS; bitpos: [0]; default: 0; + * Clear result from hmac downstream JTAG. + */ +#define HMAC_SET_INVALIDATE_JTAG (BIT(0)) +#define HMAC_SET_INVALIDATE_JTAG_M (HMAC_SET_INVALIDATE_JTAG_V << HMAC_SET_INVALIDATE_JTAG_S) +#define HMAC_SET_INVALIDATE_JTAG_V 0x00000001U +#define HMAC_SET_INVALIDATE_JTAG_S 0 + +/** HMAC_SET_INVALIDATE_DS_REG register + * Invalidate register 1. + */ +#define HMAC_SET_INVALIDATE_DS_REG (DR_REG_HMAC_BASE + 0x64) +/** HMAC_SET_INVALIDATE_DS : WS; bitpos: [0]; default: 0; + * Clear result from hmac downstream DS. + */ +#define HMAC_SET_INVALIDATE_DS (BIT(0)) +#define HMAC_SET_INVALIDATE_DS_M (HMAC_SET_INVALIDATE_DS_V << HMAC_SET_INVALIDATE_DS_S) +#define HMAC_SET_INVALIDATE_DS_V 0x00000001U +#define HMAC_SET_INVALIDATE_DS_S 0 + +/** HMAC_QUERY_ERROR_REG register + * Error register. + */ +#define HMAC_QUERY_ERROR_REG (DR_REG_HMAC_BASE + 0x68) +/** HMAC_QUREY_CHECK : RO; bitpos: [0]; default: 0; + * Hmac configuration state. 0: key are agree with purpose. 1: error + */ +#define HMAC_QUREY_CHECK (BIT(0)) +#define HMAC_QUREY_CHECK_M (HMAC_QUREY_CHECK_V << HMAC_QUREY_CHECK_S) +#define HMAC_QUREY_CHECK_V 0x00000001U +#define HMAC_QUREY_CHECK_S 0 + +/** HMAC_QUERY_BUSY_REG register + * Busy register. + */ +#define HMAC_QUERY_BUSY_REG (DR_REG_HMAC_BASE + 0x6c) +/** HMAC_BUSY_STATE : RO; bitpos: [0]; default: 0; + * Hmac state. 1'b0: idle. 1'b1: busy + */ +#define HMAC_BUSY_STATE (BIT(0)) +#define HMAC_BUSY_STATE_M (HMAC_BUSY_STATE_V << HMAC_BUSY_STATE_S) +#define HMAC_BUSY_STATE_V 0x00000001U +#define HMAC_BUSY_STATE_S 0 + +/** HMAC_WR_MESSAGE_MEM register + * Message block memory. + */ +#define HMAC_WR_MESSAGE_MEM (DR_REG_HMAC_BASE + 0x80) +#define HMAC_WR_MESSAGE_MEM_SIZE_BYTES 64 + +/** HMAC_RD_RESULT_MEM register + * Result from upstream. + */ +#define HMAC_RD_RESULT_MEM (DR_REG_HMAC_BASE + 0xc0) +#define HMAC_RD_RESULT_MEM_SIZE_BYTES 32 + +/** HMAC_SET_MESSAGE_PAD_REG register + * Process control register 5. + */ +#define HMAC_SET_MESSAGE_PAD_REG (DR_REG_HMAC_BASE + 0xf0) +/** HMAC_SET_TEXT_PAD : WO; bitpos: [0]; default: 0; + * Start software padding. + */ +#define HMAC_SET_TEXT_PAD (BIT(0)) +#define HMAC_SET_TEXT_PAD_M (HMAC_SET_TEXT_PAD_V << HMAC_SET_TEXT_PAD_S) +#define HMAC_SET_TEXT_PAD_V 0x00000001U +#define HMAC_SET_TEXT_PAD_S 0 + +/** HMAC_ONE_BLOCK_REG register + * Process control register 6. + */ +#define HMAC_ONE_BLOCK_REG (DR_REG_HMAC_BASE + 0xf4) +/** HMAC_SET_ONE_BLOCK : WS; bitpos: [0]; default: 0; + * Don't have to do padding. + */ +#define HMAC_SET_ONE_BLOCK (BIT(0)) +#define HMAC_SET_ONE_BLOCK_M (HMAC_SET_ONE_BLOCK_V << HMAC_SET_ONE_BLOCK_S) +#define HMAC_SET_ONE_BLOCK_V 0x00000001U +#define HMAC_SET_ONE_BLOCK_S 0 + +/** HMAC_SOFT_JTAG_CTRL_REG register + * Jtag register 0. + */ +#define HMAC_SOFT_JTAG_CTRL_REG (DR_REG_HMAC_BASE + 0xf8) +/** HMAC_SOFT_JTAG_CTRL : WS; bitpos: [0]; default: 0; + * Turn on JTAG verification. + */ +#define HMAC_SOFT_JTAG_CTRL (BIT(0)) +#define HMAC_SOFT_JTAG_CTRL_M (HMAC_SOFT_JTAG_CTRL_V << HMAC_SOFT_JTAG_CTRL_S) +#define HMAC_SOFT_JTAG_CTRL_V 0x00000001U +#define HMAC_SOFT_JTAG_CTRL_S 0 + +/** HMAC_WR_JTAG_REG register + * Jtag register 1. + */ +#define HMAC_WR_JTAG_REG (DR_REG_HMAC_BASE + 0xfc) +/** HMAC_WR_JTAG : WO; bitpos: [31:0]; default: 0; + * 32-bit of key to be compared. + */ +#define HMAC_WR_JTAG 0xFFFFFFFFU +#define HMAC_WR_JTAG_M (HMAC_WR_JTAG_V << HMAC_WR_JTAG_S) +#define HMAC_WR_JTAG_V 0xFFFFFFFFU +#define HMAC_WR_JTAG_S 0 + +/** HMAC_DATE_REG register + * Date register. + */ +#define HMAC_DATE_REG (DR_REG_HMAC_BASE + 0x1fc) +/** HMAC_DATE : R/W; bitpos: [29:0]; default: 538969624; + * Hmac date information/ hmac version information. + */ +#define HMAC_DATE 0x3FFFFFFFU +#define HMAC_DATE_M (HMAC_DATE_V << HMAC_DATE_S) +#define HMAC_DATE_V 0x3FFFFFFFU +#define HMAC_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/hmac_struct.h b/components/soc/esp32c6/include/soc/hmac_struct.h new file mode 100644 index 0000000000..56622759f0 --- /dev/null +++ b/components/soc/esp32c6/include/soc/hmac_struct.h @@ -0,0 +1,292 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of set_start register + * Process control register 0. + */ +typedef union { + struct { + /** set_start : WS; bitpos: [0]; default: 0; + * Start hmac operation. + */ + uint32_t set_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_start_reg_t; + +/** Type of set_para_purpose register + * Configure purpose. + */ +typedef union { + struct { + /** purpose_set : WO; bitpos: [3:0]; default: 0; + * Set hmac parameter purpose. + */ + uint32_t purpose_set:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} hmac_set_para_purpose_reg_t; + +/** Type of set_para_key register + * Configure key. + */ +typedef union { + struct { + /** key_set : WO; bitpos: [2:0]; default: 0; + * Set hmac parameter key. + */ + uint32_t key_set:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} hmac_set_para_key_reg_t; + +/** Type of set_para_finish register + * Finish initial configuration. + */ +typedef union { + struct { + /** set_para_end : WS; bitpos: [0]; default: 0; + * Finish hmac configuration. + */ + uint32_t set_para_end:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_para_finish_reg_t; + +/** Type of set_message_one register + * Process control register 1. + */ +typedef union { + struct { + /** set_text_one : WS; bitpos: [0]; default: 0; + * Call SHA to calculate one message block. + */ + uint32_t set_text_one:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_message_one_reg_t; + +/** Type of set_message_ing register + * Process control register 2. + */ +typedef union { + struct { + /** set_text_ing : WS; bitpos: [0]; default: 0; + * Continue typical hmac. + */ + uint32_t set_text_ing:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_message_ing_reg_t; + +/** Type of set_message_end register + * Process control register 3. + */ +typedef union { + struct { + /** set_text_end : WS; bitpos: [0]; default: 0; + * Start hardware padding. + */ + uint32_t set_text_end:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_message_end_reg_t; + +/** Type of set_result_finish register + * Process control register 4. + */ +typedef union { + struct { + /** set_result_end : WS; bitpos: [0]; default: 0; + * After read result from upstream, then let hmac back to idle. + */ + uint32_t set_result_end:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_result_finish_reg_t; + +/** Type of set_invalidate_jtag register + * Invalidate register 0. + */ +typedef union { + struct { + /** set_invalidate_jtag : WS; bitpos: [0]; default: 0; + * Clear result from hmac downstream JTAG. + */ + uint32_t set_invalidate_jtag:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_invalidate_jtag_reg_t; + +/** Type of set_invalidate_ds register + * Invalidate register 1. + */ +typedef union { + struct { + /** set_invalidate_ds : WS; bitpos: [0]; default: 0; + * Clear result from hmac downstream DS. + */ + uint32_t set_invalidate_ds:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_invalidate_ds_reg_t; + +/** Type of set_message_pad register + * Process control register 5. + */ +typedef union { + struct { + /** set_text_pad : WO; bitpos: [0]; default: 0; + * Start software padding. + */ + uint32_t set_text_pad:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_message_pad_reg_t; + +/** Type of one_block register + * Process control register 6. + */ +typedef union { + struct { + /** set_one_block : WS; bitpos: [0]; default: 0; + * Don't have to do padding. + */ + uint32_t set_one_block:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_one_block_reg_t; + +/** Type of soft_jtag_ctrl register + * Jtag register 0. + */ +typedef union { + struct { + /** soft_jtag_ctrl : WS; bitpos: [0]; default: 0; + * Turn on JTAG verification. + */ + uint32_t soft_jtag_ctrl:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_soft_jtag_ctrl_reg_t; + +/** Type of wr_jtag register + * Jtag register 1. + */ +typedef union { + struct { + /** wr_jtag : WO; bitpos: [31:0]; default: 0; + * 32-bit of key to be compared. + */ + uint32_t wr_jtag:32; + }; + uint32_t val; +} hmac_wr_jtag_reg_t; + + +/** Group: Status Register */ +/** Type of query_error register + * Error register. + */ +typedef union { + struct { + /** qurey_check : RO; bitpos: [0]; default: 0; + * Hmac configuration state. 0: key are agree with purpose. 1: error + */ + uint32_t qurey_check:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_query_error_reg_t; + +/** Type of query_busy register + * Busy register. + */ +typedef union { + struct { + /** busy_state : RO; bitpos: [0]; default: 0; + * Hmac state. 1'b0: idle. 1'b1: busy + */ + uint32_t busy_state:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_query_busy_reg_t; + + +/** Group: Memory Type */ + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 538969624; + * Hmac date information/ hmac version information. + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} hmac_date_reg_t; + + +typedef struct hmac_dev_t { + uint32_t reserved_000[16]; + volatile hmac_set_start_reg_t set_start; + volatile hmac_set_para_purpose_reg_t set_para_purpose; + volatile hmac_set_para_key_reg_t set_para_key; + volatile hmac_set_para_finish_reg_t set_para_finish; + volatile hmac_set_message_one_reg_t set_message_one; + volatile hmac_set_message_ing_reg_t set_message_ing; + volatile hmac_set_message_end_reg_t set_message_end; + volatile hmac_set_result_finish_reg_t set_result_finish; + volatile hmac_set_invalidate_jtag_reg_t set_invalidate_jtag; + volatile hmac_set_invalidate_ds_reg_t set_invalidate_ds; + volatile hmac_query_error_reg_t query_error; + volatile hmac_query_busy_reg_t query_busy; + uint32_t reserved_070[4]; + volatile uint32_t wr_message[16]; + volatile uint32_t rd_result[8]; + uint32_t reserved_0e0[4]; + volatile hmac_set_message_pad_reg_t set_message_pad; + volatile hmac_one_block_reg_t one_block; + volatile hmac_soft_jtag_ctrl_reg_t soft_jtag_ctrl; + volatile hmac_wr_jtag_reg_t wr_jtag; + uint32_t reserved_100[63]; + volatile hmac_date_reg_t date; +} hmac_dev_t; + +extern hmac_dev_t HMAC; + +#ifndef __cplusplus +_Static_assert(sizeof(hmac_dev_t) == 0x200, "Invalid size of hmac_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/host_reg.h b/components/soc/esp32c6/include/soc/host_reg.h new file mode 100644 index 0000000000..9bd0860687 --- /dev/null +++ b/components/soc/esp32c6/include/soc/host_reg.h @@ -0,0 +1,3883 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SLCHOST_FUNC2_0_REG register + * *******Description*********** + */ +#define SLCHOST_FUNC2_0_REG (DR_REG_SLCHOST_BASE + 0x10) +/** SLCHOST_SLC_FUNC2_INT : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC_FUNC2_INT (BIT(24)) +#define SLCHOST_SLC_FUNC2_INT_M (SLCHOST_SLC_FUNC2_INT_V << SLCHOST_SLC_FUNC2_INT_S) +#define SLCHOST_SLC_FUNC2_INT_V 0x00000001U +#define SLCHOST_SLC_FUNC2_INT_S 24 + +/** SLCHOST_FUNC2_1_REG register + * *******Description*********** + */ +#define SLCHOST_FUNC2_1_REG (DR_REG_SLCHOST_BASE + 0x14) +/** SLCHOST_SLC_FUNC2_INT_EN : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC_FUNC2_INT_EN (BIT(0)) +#define SLCHOST_SLC_FUNC2_INT_EN_M (SLCHOST_SLC_FUNC2_INT_EN_V << SLCHOST_SLC_FUNC2_INT_EN_S) +#define SLCHOST_SLC_FUNC2_INT_EN_V 0x00000001U +#define SLCHOST_SLC_FUNC2_INT_EN_S 0 + +/** SLCHOST_FUNC2_2_REG register + * *******Description*********** + */ +#define SLCHOST_FUNC2_2_REG (DR_REG_SLCHOST_BASE + 0x20) +/** SLCHOST_SLC_FUNC1_MDSTAT : R/W; bitpos: [0]; default: 1; + * *******Description*********** + */ +#define SLCHOST_SLC_FUNC1_MDSTAT (BIT(0)) +#define SLCHOST_SLC_FUNC1_MDSTAT_M (SLCHOST_SLC_FUNC1_MDSTAT_V << SLCHOST_SLC_FUNC1_MDSTAT_S) +#define SLCHOST_SLC_FUNC1_MDSTAT_V 0x00000001U +#define SLCHOST_SLC_FUNC1_MDSTAT_S 0 + +/** SLCHOST_GPIO_STATUS0_REG register + * *******Description*********** + */ +#define SLCHOST_GPIO_STATUS0_REG (DR_REG_SLCHOST_BASE + 0x34) +/** SLCHOST_GPIO_SDIO_INT0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_GPIO_SDIO_INT0 0xFFFFFFFFU +#define SLCHOST_GPIO_SDIO_INT0_M (SLCHOST_GPIO_SDIO_INT0_V << SLCHOST_GPIO_SDIO_INT0_S) +#define SLCHOST_GPIO_SDIO_INT0_V 0xFFFFFFFFU +#define SLCHOST_GPIO_SDIO_INT0_S 0 + +/** SLCHOST_GPIO_STATUS1_REG register + * *******Description*********** + */ +#define SLCHOST_GPIO_STATUS1_REG (DR_REG_SLCHOST_BASE + 0x38) +/** SLCHOST_GPIO_SDIO_INT1 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_GPIO_SDIO_INT1 0xFFFFFFFFU +#define SLCHOST_GPIO_SDIO_INT1_M (SLCHOST_GPIO_SDIO_INT1_V << SLCHOST_GPIO_SDIO_INT1_S) +#define SLCHOST_GPIO_SDIO_INT1_V 0xFFFFFFFFU +#define SLCHOST_GPIO_SDIO_INT1_S 0 + +/** SLCHOST_GPIO_IN0_REG register + * *******Description*********** + */ +#define SLCHOST_GPIO_IN0_REG (DR_REG_SLCHOST_BASE + 0x3c) +/** SLCHOST_GPIO_SDIO_IN0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_GPIO_SDIO_IN0 0xFFFFFFFFU +#define SLCHOST_GPIO_SDIO_IN0_M (SLCHOST_GPIO_SDIO_IN0_V << SLCHOST_GPIO_SDIO_IN0_S) +#define SLCHOST_GPIO_SDIO_IN0_V 0xFFFFFFFFU +#define SLCHOST_GPIO_SDIO_IN0_S 0 + +/** SLCHOST_GPIO_IN1_REG register + * *******Description*********** + */ +#define SLCHOST_GPIO_IN1_REG (DR_REG_SLCHOST_BASE + 0x40) +/** SLCHOST_GPIO_SDIO_IN1 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_GPIO_SDIO_IN1 0xFFFFFFFFU +#define SLCHOST_GPIO_SDIO_IN1_M (SLCHOST_GPIO_SDIO_IN1_V << SLCHOST_GPIO_SDIO_IN1_S) +#define SLCHOST_GPIO_SDIO_IN1_V 0xFFFFFFFFU +#define SLCHOST_GPIO_SDIO_IN1_S 0 + +/** SLCHOST_SLC0HOST_TOKEN_RDATA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x44) +/** SLCHOST_SLC0_TOKEN0 : RO; bitpos: [11:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN0 0x00000FFFU +#define SLCHOST_SLC0_TOKEN0_M (SLCHOST_SLC0_TOKEN0_V << SLCHOST_SLC0_TOKEN0_S) +#define SLCHOST_SLC0_TOKEN0_V 0x00000FFFU +#define SLCHOST_SLC0_TOKEN0_S 0 +/** SLCHOST_SLC0_RX_PF_VALID : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_PF_VALID (BIT(12)) +#define SLCHOST_SLC0_RX_PF_VALID_M (SLCHOST_SLC0_RX_PF_VALID_V << SLCHOST_SLC0_RX_PF_VALID_S) +#define SLCHOST_SLC0_RX_PF_VALID_V 0x00000001U +#define SLCHOST_SLC0_RX_PF_VALID_S 12 +/** SLCHOST_HOSTSLCHOST_SLC0_TOKEN1 : RO; bitpos: [27:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_M (SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_V << SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_S) +#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_V 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_S 16 +/** SLCHOST_SLC0_RX_PF_EOF : RO; bitpos: [31:28]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_PF_EOF 0x0000000FU +#define SLCHOST_SLC0_RX_PF_EOF_M (SLCHOST_SLC0_RX_PF_EOF_V << SLCHOST_SLC0_RX_PF_EOF_S) +#define SLCHOST_SLC0_RX_PF_EOF_V 0x0000000FU +#define SLCHOST_SLC0_RX_PF_EOF_S 28 + +/** SLCHOST_SLC0_HOST_PF_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x48) +/** SLCHOST_SLC0_PF_DATA : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_PF_DATA 0xFFFFFFFFU +#define SLCHOST_SLC0_PF_DATA_M (SLCHOST_SLC0_PF_DATA_V << SLCHOST_SLC0_PF_DATA_S) +#define SLCHOST_SLC0_PF_DATA_V 0xFFFFFFFFU +#define SLCHOST_SLC0_PF_DATA_S 0 + +/** SLCHOST_SLC1_HOST_PF_REG register + * *******Description*********** + */ +#define SLCHOST_SLC1_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x4c) +/** SLCHOST_SLC1_PF_DATA : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_PF_DATA 0xFFFFFFFFU +#define SLCHOST_SLC1_PF_DATA_M (SLCHOST_SLC1_PF_DATA_V << SLCHOST_SLC1_PF_DATA_S) +#define SLCHOST_SLC1_PF_DATA_V 0xFFFFFFFFU +#define SLCHOST_SLC1_PF_DATA_S 0 + +/** SLCHOST_SLC0HOST_INT_RAW_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x50) +/** SLCHOST_SLC0_TOHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW (BIT(0)) +#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_S) +#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_S 0 +/** SLCHOST_SLC0_TOHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW (BIT(1)) +#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_S) +#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_S 1 +/** SLCHOST_SLC0_TOHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW (BIT(2)) +#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_S) +#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_S 2 +/** SLCHOST_SLC0_TOHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW (BIT(3)) +#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_S) +#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_S 3 +/** SLCHOST_SLC0_TOHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW (BIT(4)) +#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_S) +#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_S 4 +/** SLCHOST_SLC0_TOHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW (BIT(5)) +#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_S) +#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_S 5 +/** SLCHOST_SLC0_TOHOST_BIT6_INT_RAW : R/WTC/SS/SC; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW (BIT(6)) +#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_S) +#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_S 6 +/** SLCHOST_SLC0_TOHOST_BIT7_INT_RAW : R/WTC/SS/SC; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW (BIT(7)) +#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_S) +#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_S 7 +/** SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW (BIT(8)) +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_M (SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_S) +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_S 8 +/** SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW (BIT(9)) +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_M (SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_S) +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_S 9 +/** SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW (BIT(10)) +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_M (SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_S) +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_S 10 +/** SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW (BIT(11)) +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_M (SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_S) +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_S 11 +/** SLCHOST_SLC0HOST_RX_SOF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW (BIT(12)) +#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW_M (SLCHOST_SLC0HOST_RX_SOF_INT_RAW_V << SLCHOST_SLC0HOST_RX_SOF_INT_RAW_S) +#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW_S 12 +/** SLCHOST_SLC0HOST_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW (BIT(13)) +#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW_M (SLCHOST_SLC0HOST_RX_EOF_INT_RAW_V << SLCHOST_SLC0HOST_RX_EOF_INT_RAW_S) +#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW_S 13 +/** SLCHOST_SLC0HOST_RX_START_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_START_INT_RAW (BIT(14)) +#define SLCHOST_SLC0HOST_RX_START_INT_RAW_M (SLCHOST_SLC0HOST_RX_START_INT_RAW_V << SLCHOST_SLC0HOST_RX_START_INT_RAW_S) +#define SLCHOST_SLC0HOST_RX_START_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_START_INT_RAW_S 14 +/** SLCHOST_SLC0HOST_TX_START_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TX_START_INT_RAW (BIT(15)) +#define SLCHOST_SLC0HOST_TX_START_INT_RAW_M (SLCHOST_SLC0HOST_TX_START_INT_RAW_V << SLCHOST_SLC0HOST_TX_START_INT_RAW_S) +#define SLCHOST_SLC0HOST_TX_START_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0HOST_TX_START_INT_RAW_S 15 +/** SLCHOST_SLC0_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_UDF_INT_RAW (BIT(16)) +#define SLCHOST_SLC0_RX_UDF_INT_RAW_M (SLCHOST_SLC0_RX_UDF_INT_RAW_V << SLCHOST_SLC0_RX_UDF_INT_RAW_S) +#define SLCHOST_SLC0_RX_UDF_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_RX_UDF_INT_RAW_S 16 +/** SLCHOST_SLC0_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TX_OVF_INT_RAW (BIT(17)) +#define SLCHOST_SLC0_TX_OVF_INT_RAW_M (SLCHOST_SLC0_TX_OVF_INT_RAW_V << SLCHOST_SLC0_TX_OVF_INT_RAW_S) +#define SLCHOST_SLC0_TX_OVF_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TX_OVF_INT_RAW_S 17 +/** SLCHOST_SLC0_RX_PF_VALID_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW (BIT(18)) +#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW_M (SLCHOST_SLC0_RX_PF_VALID_INT_RAW_V << SLCHOST_SLC0_RX_PF_VALID_INT_RAW_S) +#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW_S 18 +/** SLCHOST_SLC0_EXT_BIT0_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT0_INT_RAW (BIT(19)) +#define SLCHOST_SLC0_EXT_BIT0_INT_RAW_M (SLCHOST_SLC0_EXT_BIT0_INT_RAW_V << SLCHOST_SLC0_EXT_BIT0_INT_RAW_S) +#define SLCHOST_SLC0_EXT_BIT0_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT0_INT_RAW_S 19 +/** SLCHOST_SLC0_EXT_BIT1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT1_INT_RAW (BIT(20)) +#define SLCHOST_SLC0_EXT_BIT1_INT_RAW_M (SLCHOST_SLC0_EXT_BIT1_INT_RAW_V << SLCHOST_SLC0_EXT_BIT1_INT_RAW_S) +#define SLCHOST_SLC0_EXT_BIT1_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT1_INT_RAW_S 20 +/** SLCHOST_SLC0_EXT_BIT2_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT2_INT_RAW (BIT(21)) +#define SLCHOST_SLC0_EXT_BIT2_INT_RAW_M (SLCHOST_SLC0_EXT_BIT2_INT_RAW_V << SLCHOST_SLC0_EXT_BIT2_INT_RAW_S) +#define SLCHOST_SLC0_EXT_BIT2_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT2_INT_RAW_S 21 +/** SLCHOST_SLC0_EXT_BIT3_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT3_INT_RAW (BIT(22)) +#define SLCHOST_SLC0_EXT_BIT3_INT_RAW_M (SLCHOST_SLC0_EXT_BIT3_INT_RAW_V << SLCHOST_SLC0_EXT_BIT3_INT_RAW_S) +#define SLCHOST_SLC0_EXT_BIT3_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT3_INT_RAW_S 22 +/** SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW (BIT(23)) +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_M (SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_S) +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_S 23 +/** SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW (BIT(24)) +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_M (SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_S) +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_S 24 +/** SLCHOST_GPIO_SDIO_INT_RAW : R/WTC/SS/SC; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_GPIO_SDIO_INT_RAW (BIT(25)) +#define SLCHOST_GPIO_SDIO_INT_RAW_M (SLCHOST_GPIO_SDIO_INT_RAW_V << SLCHOST_GPIO_SDIO_INT_RAW_S) +#define SLCHOST_GPIO_SDIO_INT_RAW_V 0x00000001U +#define SLCHOST_GPIO_SDIO_INT_RAW_S 25 + +/** SLCHOST_SLC1HOST_INT_RAW_REG register + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x54) +/** SLCHOST_SLC1_TOHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW (BIT(0)) +#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_S) +#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_S 0 +/** SLCHOST_SLC1_TOHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW (BIT(1)) +#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_S) +#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_S 1 +/** SLCHOST_SLC1_TOHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW (BIT(2)) +#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_S) +#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_S 2 +/** SLCHOST_SLC1_TOHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW (BIT(3)) +#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_S) +#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_S 3 +/** SLCHOST_SLC1_TOHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW (BIT(4)) +#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_S) +#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_S 4 +/** SLCHOST_SLC1_TOHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW (BIT(5)) +#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_S) +#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_S 5 +/** SLCHOST_SLC1_TOHOST_BIT6_INT_RAW : R/WTC/SS/SC; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW (BIT(6)) +#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_S) +#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_S 6 +/** SLCHOST_SLC1_TOHOST_BIT7_INT_RAW : R/WTC/SS/SC; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW (BIT(7)) +#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_S) +#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_S 7 +/** SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW (BIT(8)) +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_M (SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_S) +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_S 8 +/** SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW (BIT(9)) +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_M (SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_S) +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_S 9 +/** SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW (BIT(10)) +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_M (SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_S) +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_S 10 +/** SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW (BIT(11)) +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_M (SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_S) +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_S 11 +/** SLCHOST_SLC1HOST_RX_SOF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW (BIT(12)) +#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW_M (SLCHOST_SLC1HOST_RX_SOF_INT_RAW_V << SLCHOST_SLC1HOST_RX_SOF_INT_RAW_S) +#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW_S 12 +/** SLCHOST_SLC1HOST_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW (BIT(13)) +#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW_M (SLCHOST_SLC1HOST_RX_EOF_INT_RAW_V << SLCHOST_SLC1HOST_RX_EOF_INT_RAW_S) +#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW_S 13 +/** SLCHOST_SLC1HOST_RX_START_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_START_INT_RAW (BIT(14)) +#define SLCHOST_SLC1HOST_RX_START_INT_RAW_M (SLCHOST_SLC1HOST_RX_START_INT_RAW_V << SLCHOST_SLC1HOST_RX_START_INT_RAW_S) +#define SLCHOST_SLC1HOST_RX_START_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_START_INT_RAW_S 14 +/** SLCHOST_SLC1HOST_TX_START_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TX_START_INT_RAW (BIT(15)) +#define SLCHOST_SLC1HOST_TX_START_INT_RAW_M (SLCHOST_SLC1HOST_TX_START_INT_RAW_V << SLCHOST_SLC1HOST_TX_START_INT_RAW_S) +#define SLCHOST_SLC1HOST_TX_START_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1HOST_TX_START_INT_RAW_S 15 +/** SLCHOST_SLC1_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_UDF_INT_RAW (BIT(16)) +#define SLCHOST_SLC1_RX_UDF_INT_RAW_M (SLCHOST_SLC1_RX_UDF_INT_RAW_V << SLCHOST_SLC1_RX_UDF_INT_RAW_S) +#define SLCHOST_SLC1_RX_UDF_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_RX_UDF_INT_RAW_S 16 +/** SLCHOST_SLC1_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TX_OVF_INT_RAW (BIT(17)) +#define SLCHOST_SLC1_TX_OVF_INT_RAW_M (SLCHOST_SLC1_TX_OVF_INT_RAW_V << SLCHOST_SLC1_TX_OVF_INT_RAW_S) +#define SLCHOST_SLC1_TX_OVF_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TX_OVF_INT_RAW_S 17 +/** SLCHOST_SLC1_RX_PF_VALID_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW (BIT(18)) +#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW_M (SLCHOST_SLC1_RX_PF_VALID_INT_RAW_V << SLCHOST_SLC1_RX_PF_VALID_INT_RAW_S) +#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW_S 18 +/** SLCHOST_SLC1_EXT_BIT0_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT0_INT_RAW (BIT(19)) +#define SLCHOST_SLC1_EXT_BIT0_INT_RAW_M (SLCHOST_SLC1_EXT_BIT0_INT_RAW_V << SLCHOST_SLC1_EXT_BIT0_INT_RAW_S) +#define SLCHOST_SLC1_EXT_BIT0_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT0_INT_RAW_S 19 +/** SLCHOST_SLC1_EXT_BIT1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT1_INT_RAW (BIT(20)) +#define SLCHOST_SLC1_EXT_BIT1_INT_RAW_M (SLCHOST_SLC1_EXT_BIT1_INT_RAW_V << SLCHOST_SLC1_EXT_BIT1_INT_RAW_S) +#define SLCHOST_SLC1_EXT_BIT1_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT1_INT_RAW_S 20 +/** SLCHOST_SLC1_EXT_BIT2_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT2_INT_RAW (BIT(21)) +#define SLCHOST_SLC1_EXT_BIT2_INT_RAW_M (SLCHOST_SLC1_EXT_BIT2_INT_RAW_V << SLCHOST_SLC1_EXT_BIT2_INT_RAW_S) +#define SLCHOST_SLC1_EXT_BIT2_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT2_INT_RAW_S 21 +/** SLCHOST_SLC1_EXT_BIT3_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT3_INT_RAW (BIT(22)) +#define SLCHOST_SLC1_EXT_BIT3_INT_RAW_M (SLCHOST_SLC1_EXT_BIT3_INT_RAW_V << SLCHOST_SLC1_EXT_BIT3_INT_RAW_S) +#define SLCHOST_SLC1_EXT_BIT3_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT3_INT_RAW_S 22 +/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW (BIT(23)) +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_M (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_S) +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_S 23 +/** SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW (BIT(24)) +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_M (SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_S) +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_S 24 +/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW (BIT(25)) +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_M (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_S) +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_S 25 + +/** SLCHOST_SLC0HOST_INT_ST_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x58) +/** SLCHOST_SLC0_TOHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST (BIT(0)) +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT0_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT0_INT_ST_S) +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST_S 0 +/** SLCHOST_SLC0_TOHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST (BIT(1)) +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT1_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT1_INT_ST_S) +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST_S 1 +/** SLCHOST_SLC0_TOHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST (BIT(2)) +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT2_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT2_INT_ST_S) +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST_S 2 +/** SLCHOST_SLC0_TOHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST (BIT(3)) +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT3_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT3_INT_ST_S) +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST_S 3 +/** SLCHOST_SLC0_TOHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST (BIT(4)) +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT4_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT4_INT_ST_S) +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST_S 4 +/** SLCHOST_SLC0_TOHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST (BIT(5)) +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT5_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT5_INT_ST_S) +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST_S 5 +/** SLCHOST_SLC0_TOHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST (BIT(6)) +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT6_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT6_INT_ST_S) +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST_S 6 +/** SLCHOST_SLC0_TOHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST (BIT(7)) +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT7_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT7_INT_ST_S) +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST_S 7 +/** SLCHOST_SLC0_TOKEN0_1TO0_INT_ST : RO; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST (BIT(8)) +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_M (SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_S) +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_S 8 +/** SLCHOST_SLC0_TOKEN1_1TO0_INT_ST : RO; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST (BIT(9)) +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_M (SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_S) +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_S 9 +/** SLCHOST_SLC0_TOKEN0_0TO1_INT_ST : RO; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST (BIT(10)) +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_M (SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_S) +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_S 10 +/** SLCHOST_SLC0_TOKEN1_0TO1_INT_ST : RO; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST (BIT(11)) +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_M (SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_S) +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_S 11 +/** SLCHOST_SLC0HOST_RX_SOF_INT_ST : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_SOF_INT_ST (BIT(12)) +#define SLCHOST_SLC0HOST_RX_SOF_INT_ST_M (SLCHOST_SLC0HOST_RX_SOF_INT_ST_V << SLCHOST_SLC0HOST_RX_SOF_INT_ST_S) +#define SLCHOST_SLC0HOST_RX_SOF_INT_ST_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_SOF_INT_ST_S 12 +/** SLCHOST_SLC0HOST_RX_EOF_INT_ST : RO; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_EOF_INT_ST (BIT(13)) +#define SLCHOST_SLC0HOST_RX_EOF_INT_ST_M (SLCHOST_SLC0HOST_RX_EOF_INT_ST_V << SLCHOST_SLC0HOST_RX_EOF_INT_ST_S) +#define SLCHOST_SLC0HOST_RX_EOF_INT_ST_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_EOF_INT_ST_S 13 +/** SLCHOST_SLC0HOST_RX_START_INT_ST : RO; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_START_INT_ST (BIT(14)) +#define SLCHOST_SLC0HOST_RX_START_INT_ST_M (SLCHOST_SLC0HOST_RX_START_INT_ST_V << SLCHOST_SLC0HOST_RX_START_INT_ST_S) +#define SLCHOST_SLC0HOST_RX_START_INT_ST_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_START_INT_ST_S 14 +/** SLCHOST_SLC0HOST_TX_START_INT_ST : RO; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TX_START_INT_ST (BIT(15)) +#define SLCHOST_SLC0HOST_TX_START_INT_ST_M (SLCHOST_SLC0HOST_TX_START_INT_ST_V << SLCHOST_SLC0HOST_TX_START_INT_ST_S) +#define SLCHOST_SLC0HOST_TX_START_INT_ST_V 0x00000001U +#define SLCHOST_SLC0HOST_TX_START_INT_ST_S 15 +/** SLCHOST_SLC0_RX_UDF_INT_ST : RO; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_UDF_INT_ST (BIT(16)) +#define SLCHOST_SLC0_RX_UDF_INT_ST_M (SLCHOST_SLC0_RX_UDF_INT_ST_V << SLCHOST_SLC0_RX_UDF_INT_ST_S) +#define SLCHOST_SLC0_RX_UDF_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_RX_UDF_INT_ST_S 16 +/** SLCHOST_SLC0_TX_OVF_INT_ST : RO; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TX_OVF_INT_ST (BIT(17)) +#define SLCHOST_SLC0_TX_OVF_INT_ST_M (SLCHOST_SLC0_TX_OVF_INT_ST_V << SLCHOST_SLC0_TX_OVF_INT_ST_S) +#define SLCHOST_SLC0_TX_OVF_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TX_OVF_INT_ST_S 17 +/** SLCHOST_SLC0_RX_PF_VALID_INT_ST : RO; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_PF_VALID_INT_ST (BIT(18)) +#define SLCHOST_SLC0_RX_PF_VALID_INT_ST_M (SLCHOST_SLC0_RX_PF_VALID_INT_ST_V << SLCHOST_SLC0_RX_PF_VALID_INT_ST_S) +#define SLCHOST_SLC0_RX_PF_VALID_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_RX_PF_VALID_INT_ST_S 18 +/** SLCHOST_SLC0_EXT_BIT0_INT_ST : RO; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT0_INT_ST (BIT(19)) +#define SLCHOST_SLC0_EXT_BIT0_INT_ST_M (SLCHOST_SLC0_EXT_BIT0_INT_ST_V << SLCHOST_SLC0_EXT_BIT0_INT_ST_S) +#define SLCHOST_SLC0_EXT_BIT0_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT0_INT_ST_S 19 +/** SLCHOST_SLC0_EXT_BIT1_INT_ST : RO; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT1_INT_ST (BIT(20)) +#define SLCHOST_SLC0_EXT_BIT1_INT_ST_M (SLCHOST_SLC0_EXT_BIT1_INT_ST_V << SLCHOST_SLC0_EXT_BIT1_INT_ST_S) +#define SLCHOST_SLC0_EXT_BIT1_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT1_INT_ST_S 20 +/** SLCHOST_SLC0_EXT_BIT2_INT_ST : RO; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT2_INT_ST (BIT(21)) +#define SLCHOST_SLC0_EXT_BIT2_INT_ST_M (SLCHOST_SLC0_EXT_BIT2_INT_ST_V << SLCHOST_SLC0_EXT_BIT2_INT_ST_S) +#define SLCHOST_SLC0_EXT_BIT2_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT2_INT_ST_S 21 +/** SLCHOST_SLC0_EXT_BIT3_INT_ST : RO; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT3_INT_ST (BIT(22)) +#define SLCHOST_SLC0_EXT_BIT3_INT_ST_M (SLCHOST_SLC0_EXT_BIT3_INT_ST_V << SLCHOST_SLC0_EXT_BIT3_INT_ST_S) +#define SLCHOST_SLC0_EXT_BIT3_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT3_INT_ST_S 22 +/** SLCHOST_SLC0_RX_NEW_PACKET_INT_ST : RO; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST (BIT(23)) +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_M (SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_S) +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_S 23 +/** SLCHOST_SLC0_HOST_RD_RETRY_INT_ST : RO; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST (BIT(24)) +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_M (SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_S) +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_S 24 +/** SLCHOST_GPIO_SDIO_INT_ST : RO; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_GPIO_SDIO_INT_ST (BIT(25)) +#define SLCHOST_GPIO_SDIO_INT_ST_M (SLCHOST_GPIO_SDIO_INT_ST_V << SLCHOST_GPIO_SDIO_INT_ST_S) +#define SLCHOST_GPIO_SDIO_INT_ST_V 0x00000001U +#define SLCHOST_GPIO_SDIO_INT_ST_S 25 + +/** SLCHOST_SLC1HOST_INT_ST_REG register + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x5c) +/** SLCHOST_SLC1_TOHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST (BIT(0)) +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT0_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT0_INT_ST_S) +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST_S 0 +/** SLCHOST_SLC1_TOHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST (BIT(1)) +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT1_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT1_INT_ST_S) +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST_S 1 +/** SLCHOST_SLC1_TOHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST (BIT(2)) +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT2_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT2_INT_ST_S) +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST_S 2 +/** SLCHOST_SLC1_TOHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST (BIT(3)) +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT3_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT3_INT_ST_S) +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST_S 3 +/** SLCHOST_SLC1_TOHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST (BIT(4)) +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT4_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT4_INT_ST_S) +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST_S 4 +/** SLCHOST_SLC1_TOHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST (BIT(5)) +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT5_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT5_INT_ST_S) +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST_S 5 +/** SLCHOST_SLC1_TOHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST (BIT(6)) +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT6_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT6_INT_ST_S) +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST_S 6 +/** SLCHOST_SLC1_TOHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST (BIT(7)) +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT7_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT7_INT_ST_S) +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST_S 7 +/** SLCHOST_SLC1_TOKEN0_1TO0_INT_ST : RO; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST (BIT(8)) +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_M (SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_S) +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_S 8 +/** SLCHOST_SLC1_TOKEN1_1TO0_INT_ST : RO; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST (BIT(9)) +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_M (SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_S) +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_S 9 +/** SLCHOST_SLC1_TOKEN0_0TO1_INT_ST : RO; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST (BIT(10)) +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_M (SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_S) +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_S 10 +/** SLCHOST_SLC1_TOKEN1_0TO1_INT_ST : RO; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST (BIT(11)) +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_M (SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_S) +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_S 11 +/** SLCHOST_SLC1HOST_RX_SOF_INT_ST : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_SOF_INT_ST (BIT(12)) +#define SLCHOST_SLC1HOST_RX_SOF_INT_ST_M (SLCHOST_SLC1HOST_RX_SOF_INT_ST_V << SLCHOST_SLC1HOST_RX_SOF_INT_ST_S) +#define SLCHOST_SLC1HOST_RX_SOF_INT_ST_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_SOF_INT_ST_S 12 +/** SLCHOST_SLC1HOST_RX_EOF_INT_ST : RO; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_EOF_INT_ST (BIT(13)) +#define SLCHOST_SLC1HOST_RX_EOF_INT_ST_M (SLCHOST_SLC1HOST_RX_EOF_INT_ST_V << SLCHOST_SLC1HOST_RX_EOF_INT_ST_S) +#define SLCHOST_SLC1HOST_RX_EOF_INT_ST_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_EOF_INT_ST_S 13 +/** SLCHOST_SLC1HOST_RX_START_INT_ST : RO; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_START_INT_ST (BIT(14)) +#define SLCHOST_SLC1HOST_RX_START_INT_ST_M (SLCHOST_SLC1HOST_RX_START_INT_ST_V << SLCHOST_SLC1HOST_RX_START_INT_ST_S) +#define SLCHOST_SLC1HOST_RX_START_INT_ST_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_START_INT_ST_S 14 +/** SLCHOST_SLC1HOST_TX_START_INT_ST : RO; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TX_START_INT_ST (BIT(15)) +#define SLCHOST_SLC1HOST_TX_START_INT_ST_M (SLCHOST_SLC1HOST_TX_START_INT_ST_V << SLCHOST_SLC1HOST_TX_START_INT_ST_S) +#define SLCHOST_SLC1HOST_TX_START_INT_ST_V 0x00000001U +#define SLCHOST_SLC1HOST_TX_START_INT_ST_S 15 +/** SLCHOST_SLC1_RX_UDF_INT_ST : RO; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_UDF_INT_ST (BIT(16)) +#define SLCHOST_SLC1_RX_UDF_INT_ST_M (SLCHOST_SLC1_RX_UDF_INT_ST_V << SLCHOST_SLC1_RX_UDF_INT_ST_S) +#define SLCHOST_SLC1_RX_UDF_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_RX_UDF_INT_ST_S 16 +/** SLCHOST_SLC1_TX_OVF_INT_ST : RO; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TX_OVF_INT_ST (BIT(17)) +#define SLCHOST_SLC1_TX_OVF_INT_ST_M (SLCHOST_SLC1_TX_OVF_INT_ST_V << SLCHOST_SLC1_TX_OVF_INT_ST_S) +#define SLCHOST_SLC1_TX_OVF_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TX_OVF_INT_ST_S 17 +/** SLCHOST_SLC1_RX_PF_VALID_INT_ST : RO; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_PF_VALID_INT_ST (BIT(18)) +#define SLCHOST_SLC1_RX_PF_VALID_INT_ST_M (SLCHOST_SLC1_RX_PF_VALID_INT_ST_V << SLCHOST_SLC1_RX_PF_VALID_INT_ST_S) +#define SLCHOST_SLC1_RX_PF_VALID_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_RX_PF_VALID_INT_ST_S 18 +/** SLCHOST_SLC1_EXT_BIT0_INT_ST : RO; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT0_INT_ST (BIT(19)) +#define SLCHOST_SLC1_EXT_BIT0_INT_ST_M (SLCHOST_SLC1_EXT_BIT0_INT_ST_V << SLCHOST_SLC1_EXT_BIT0_INT_ST_S) +#define SLCHOST_SLC1_EXT_BIT0_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT0_INT_ST_S 19 +/** SLCHOST_SLC1_EXT_BIT1_INT_ST : RO; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT1_INT_ST (BIT(20)) +#define SLCHOST_SLC1_EXT_BIT1_INT_ST_M (SLCHOST_SLC1_EXT_BIT1_INT_ST_V << SLCHOST_SLC1_EXT_BIT1_INT_ST_S) +#define SLCHOST_SLC1_EXT_BIT1_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT1_INT_ST_S 20 +/** SLCHOST_SLC1_EXT_BIT2_INT_ST : RO; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT2_INT_ST (BIT(21)) +#define SLCHOST_SLC1_EXT_BIT2_INT_ST_M (SLCHOST_SLC1_EXT_BIT2_INT_ST_V << SLCHOST_SLC1_EXT_BIT2_INT_ST_S) +#define SLCHOST_SLC1_EXT_BIT2_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT2_INT_ST_S 21 +/** SLCHOST_SLC1_EXT_BIT3_INT_ST : RO; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT3_INT_ST (BIT(22)) +#define SLCHOST_SLC1_EXT_BIT3_INT_ST_M (SLCHOST_SLC1_EXT_BIT3_INT_ST_V << SLCHOST_SLC1_EXT_BIT3_INT_ST_S) +#define SLCHOST_SLC1_EXT_BIT3_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT3_INT_ST_S 22 +/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST : RO; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST (BIT(23)) +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_M (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_S) +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_S 23 +/** SLCHOST_SLC1_HOST_RD_RETRY_INT_ST : RO; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST (BIT(24)) +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_M (SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_S) +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_S 24 +/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST : RO; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST (BIT(25)) +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_M (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_S) +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_S 25 + +/** SLCHOST_PKT_LEN_REG register + * *******Description*********** + */ +#define SLCHOST_PKT_LEN_REG (DR_REG_SLCHOST_BASE + 0x60) +/** SLCHOST_HOSTSLCHOST_SLC0_LEN : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_HOSTSLCHOST_SLC0_LEN 0x000FFFFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN_M (SLCHOST_HOSTSLCHOST_SLC0_LEN_V << SLCHOST_HOSTSLCHOST_SLC0_LEN_S) +#define SLCHOST_HOSTSLCHOST_SLC0_LEN_V 0x000FFFFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN_S 0 +/** SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_M (SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_S) +#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_V 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_S 20 + +/** SLCHOST_STATE_W0_REG register + * *******Description*********** + */ +#define SLCHOST_STATE_W0_REG (DR_REG_SLCHOST_BASE + 0x64) +/** SLCHOST_SLCHOST_STATE0 : RO; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_STATE0 0x000000FFU +#define SLCHOST_SLCHOST_STATE0_M (SLCHOST_SLCHOST_STATE0_V << SLCHOST_SLCHOST_STATE0_S) +#define SLCHOST_SLCHOST_STATE0_V 0x000000FFU +#define SLCHOST_SLCHOST_STATE0_S 0 +/** SLCHOST_SLCHOST_STATE1 : RO; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_STATE1 0x000000FFU +#define SLCHOST_SLCHOST_STATE1_M (SLCHOST_SLCHOST_STATE1_V << SLCHOST_SLCHOST_STATE1_S) +#define SLCHOST_SLCHOST_STATE1_V 0x000000FFU +#define SLCHOST_SLCHOST_STATE1_S 8 +/** SLCHOST_SLCHOST_STATE2 : RO; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_STATE2 0x000000FFU +#define SLCHOST_SLCHOST_STATE2_M (SLCHOST_SLCHOST_STATE2_V << SLCHOST_SLCHOST_STATE2_S) +#define SLCHOST_SLCHOST_STATE2_V 0x000000FFU +#define SLCHOST_SLCHOST_STATE2_S 16 +/** SLCHOST_SLCHOST_STATE3 : RO; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_STATE3 0x000000FFU +#define SLCHOST_SLCHOST_STATE3_M (SLCHOST_SLCHOST_STATE3_V << SLCHOST_SLCHOST_STATE3_S) +#define SLCHOST_SLCHOST_STATE3_V 0x000000FFU +#define SLCHOST_SLCHOST_STATE3_S 24 + +/** SLCHOST_STATE_W1_REG register + * *******Description*********** + */ +#define SLCHOST_STATE_W1_REG (DR_REG_SLCHOST_BASE + 0x68) +/** SLCHOST_SLCHOST_STATE4 : RO; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_STATE4 0x000000FFU +#define SLCHOST_SLCHOST_STATE4_M (SLCHOST_SLCHOST_STATE4_V << SLCHOST_SLCHOST_STATE4_S) +#define SLCHOST_SLCHOST_STATE4_V 0x000000FFU +#define SLCHOST_SLCHOST_STATE4_S 0 +/** SLCHOST_SLCHOST_STATE5 : RO; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_STATE5 0x000000FFU +#define SLCHOST_SLCHOST_STATE5_M (SLCHOST_SLCHOST_STATE5_V << SLCHOST_SLCHOST_STATE5_S) +#define SLCHOST_SLCHOST_STATE5_V 0x000000FFU +#define SLCHOST_SLCHOST_STATE5_S 8 +/** SLCHOST_SLCHOST_STATE6 : RO; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_STATE6 0x000000FFU +#define SLCHOST_SLCHOST_STATE6_M (SLCHOST_SLCHOST_STATE6_V << SLCHOST_SLCHOST_STATE6_S) +#define SLCHOST_SLCHOST_STATE6_V 0x000000FFU +#define SLCHOST_SLCHOST_STATE6_S 16 +/** SLCHOST_SLCHOST_STATE7 : RO; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_STATE7 0x000000FFU +#define SLCHOST_SLCHOST_STATE7_M (SLCHOST_SLCHOST_STATE7_V << SLCHOST_SLCHOST_STATE7_S) +#define SLCHOST_SLCHOST_STATE7_V 0x000000FFU +#define SLCHOST_SLCHOST_STATE7_S 24 + +/** SLCHOST_CONF_W0_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W0_REG (DR_REG_SLCHOST_BASE + 0x6c) +/** SLCHOST_SLCHOST_CONF0 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF0 0x000000FFU +#define SLCHOST_SLCHOST_CONF0_M (SLCHOST_SLCHOST_CONF0_V << SLCHOST_SLCHOST_CONF0_S) +#define SLCHOST_SLCHOST_CONF0_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF0_S 0 +/** SLCHOST_SLCHOST_CONF1 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF1 0x000000FFU +#define SLCHOST_SLCHOST_CONF1_M (SLCHOST_SLCHOST_CONF1_V << SLCHOST_SLCHOST_CONF1_S) +#define SLCHOST_SLCHOST_CONF1_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF1_S 8 +/** SLCHOST_SLCHOST_CONF2 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF2 0x000000FFU +#define SLCHOST_SLCHOST_CONF2_M (SLCHOST_SLCHOST_CONF2_V << SLCHOST_SLCHOST_CONF2_S) +#define SLCHOST_SLCHOST_CONF2_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF2_S 16 +/** SLCHOST_SLCHOST_CONF3 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF3 0x000000FFU +#define SLCHOST_SLCHOST_CONF3_M (SLCHOST_SLCHOST_CONF3_V << SLCHOST_SLCHOST_CONF3_S) +#define SLCHOST_SLCHOST_CONF3_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF3_S 24 + +/** SLCHOST_CONF_W1_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W1_REG (DR_REG_SLCHOST_BASE + 0x70) +/** SLCHOST_SLCHOST_CONF4 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF4 0x000000FFU +#define SLCHOST_SLCHOST_CONF4_M (SLCHOST_SLCHOST_CONF4_V << SLCHOST_SLCHOST_CONF4_S) +#define SLCHOST_SLCHOST_CONF4_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF4_S 0 +/** SLCHOST_SLCHOST_CONF5 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF5 0x000000FFU +#define SLCHOST_SLCHOST_CONF5_M (SLCHOST_SLCHOST_CONF5_V << SLCHOST_SLCHOST_CONF5_S) +#define SLCHOST_SLCHOST_CONF5_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF5_S 8 +/** SLCHOST_SLCHOST_CONF6 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF6 0x000000FFU +#define SLCHOST_SLCHOST_CONF6_M (SLCHOST_SLCHOST_CONF6_V << SLCHOST_SLCHOST_CONF6_S) +#define SLCHOST_SLCHOST_CONF6_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF6_S 16 +/** SLCHOST_SLCHOST_CONF7 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF7 0x000000FFU +#define SLCHOST_SLCHOST_CONF7_M (SLCHOST_SLCHOST_CONF7_V << SLCHOST_SLCHOST_CONF7_S) +#define SLCHOST_SLCHOST_CONF7_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF7_S 24 + +/** SLCHOST_CONF_W2_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W2_REG (DR_REG_SLCHOST_BASE + 0x74) +/** SLCHOST_SLCHOST_CONF8 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF8 0x000000FFU +#define SLCHOST_SLCHOST_CONF8_M (SLCHOST_SLCHOST_CONF8_V << SLCHOST_SLCHOST_CONF8_S) +#define SLCHOST_SLCHOST_CONF8_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF8_S 0 +/** SLCHOST_SLCHOST_CONF9 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF9 0x000000FFU +#define SLCHOST_SLCHOST_CONF9_M (SLCHOST_SLCHOST_CONF9_V << SLCHOST_SLCHOST_CONF9_S) +#define SLCHOST_SLCHOST_CONF9_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF9_S 8 +/** SLCHOST_SLCHOST_CONF10 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF10 0x000000FFU +#define SLCHOST_SLCHOST_CONF10_M (SLCHOST_SLCHOST_CONF10_V << SLCHOST_SLCHOST_CONF10_S) +#define SLCHOST_SLCHOST_CONF10_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF10_S 16 +/** SLCHOST_SLCHOST_CONF11 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF11 0x000000FFU +#define SLCHOST_SLCHOST_CONF11_M (SLCHOST_SLCHOST_CONF11_V << SLCHOST_SLCHOST_CONF11_S) +#define SLCHOST_SLCHOST_CONF11_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF11_S 24 + +/** SLCHOST_CONF_W3_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W3_REG (DR_REG_SLCHOST_BASE + 0x78) +/** SLCHOST_SLCHOST_CONF12 : R/W; bitpos: [7:0]; default: 192; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF12 0x000000FFU +#define SLCHOST_SLCHOST_CONF12_M (SLCHOST_SLCHOST_CONF12_V << SLCHOST_SLCHOST_CONF12_S) +#define SLCHOST_SLCHOST_CONF12_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF12_S 0 +/** SLCHOST_SLCHOST_CONF13 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF13 0x000000FFU +#define SLCHOST_SLCHOST_CONF13_M (SLCHOST_SLCHOST_CONF13_V << SLCHOST_SLCHOST_CONF13_S) +#define SLCHOST_SLCHOST_CONF13_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF13_S 8 +/** SLCHOST_SLCHOST_CONF14 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF14 0x000000FFU +#define SLCHOST_SLCHOST_CONF14_M (SLCHOST_SLCHOST_CONF14_V << SLCHOST_SLCHOST_CONF14_S) +#define SLCHOST_SLCHOST_CONF14_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF14_S 16 +/** SLCHOST_SLCHOST_CONF15 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF15 0x000000FFU +#define SLCHOST_SLCHOST_CONF15_M (SLCHOST_SLCHOST_CONF15_V << SLCHOST_SLCHOST_CONF15_S) +#define SLCHOST_SLCHOST_CONF15_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF15_S 24 + +/** SLCHOST_CONF_W4_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W4_REG (DR_REG_SLCHOST_BASE + 0x7c) +/** SLCHOST_SLCHOST_CONF16 : R/W; bitpos: [7:0]; default: 255; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF16 0x000000FFU +#define SLCHOST_SLCHOST_CONF16_M (SLCHOST_SLCHOST_CONF16_V << SLCHOST_SLCHOST_CONF16_S) +#define SLCHOST_SLCHOST_CONF16_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF16_S 0 +/** SLCHOST_SLCHOST_CONF17 : R/W; bitpos: [15:8]; default: 1; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF17 0x000000FFU +#define SLCHOST_SLCHOST_CONF17_M (SLCHOST_SLCHOST_CONF17_V << SLCHOST_SLCHOST_CONF17_S) +#define SLCHOST_SLCHOST_CONF17_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF17_S 8 +/** SLCHOST_SLCHOST_CONF18 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF18 0x000000FFU +#define SLCHOST_SLCHOST_CONF18_M (SLCHOST_SLCHOST_CONF18_V << SLCHOST_SLCHOST_CONF18_S) +#define SLCHOST_SLCHOST_CONF18_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF18_S 16 +/** SLCHOST_SLCHOST_CONF19 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF19 0x000000FFU +#define SLCHOST_SLCHOST_CONF19_M (SLCHOST_SLCHOST_CONF19_V << SLCHOST_SLCHOST_CONF19_S) +#define SLCHOST_SLCHOST_CONF19_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF19_S 24 + +/** SLCHOST_CONF_W5_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W5_REG (DR_REG_SLCHOST_BASE + 0x80) +/** SLCHOST_SLCHOST_CONF20 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF20 0x000000FFU +#define SLCHOST_SLCHOST_CONF20_M (SLCHOST_SLCHOST_CONF20_V << SLCHOST_SLCHOST_CONF20_S) +#define SLCHOST_SLCHOST_CONF20_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF20_S 0 +/** SLCHOST_SLCHOST_CONF21 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF21 0x000000FFU +#define SLCHOST_SLCHOST_CONF21_M (SLCHOST_SLCHOST_CONF21_V << SLCHOST_SLCHOST_CONF21_S) +#define SLCHOST_SLCHOST_CONF21_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF21_S 8 +/** SLCHOST_SLCHOST_CONF22 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF22 0x000000FFU +#define SLCHOST_SLCHOST_CONF22_M (SLCHOST_SLCHOST_CONF22_V << SLCHOST_SLCHOST_CONF22_S) +#define SLCHOST_SLCHOST_CONF22_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF22_S 16 +/** SLCHOST_SLCHOST_CONF23 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF23 0x000000FFU +#define SLCHOST_SLCHOST_CONF23_M (SLCHOST_SLCHOST_CONF23_V << SLCHOST_SLCHOST_CONF23_S) +#define SLCHOST_SLCHOST_CONF23_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF23_S 24 + +/** SLCHOST_WIN_CMD_REG register + * *******Description*********** + */ +#define SLCHOST_WIN_CMD_REG (DR_REG_SLCHOST_BASE + 0x84) +/** SLCHOST_SLCHOST_WIN_CMD : R/W; bitpos: [15:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_WIN_CMD 0x0000FFFFU +#define SLCHOST_SLCHOST_WIN_CMD_M (SLCHOST_SLCHOST_WIN_CMD_V << SLCHOST_SLCHOST_WIN_CMD_S) +#define SLCHOST_SLCHOST_WIN_CMD_V 0x0000FFFFU +#define SLCHOST_SLCHOST_WIN_CMD_S 0 + +/** SLCHOST_CONF_W6_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W6_REG (DR_REG_SLCHOST_BASE + 0x88) +/** SLCHOST_SLCHOST_CONF24 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF24 0x000000FFU +#define SLCHOST_SLCHOST_CONF24_M (SLCHOST_SLCHOST_CONF24_V << SLCHOST_SLCHOST_CONF24_S) +#define SLCHOST_SLCHOST_CONF24_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF24_S 0 +/** SLCHOST_SLCHOST_CONF25 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF25 0x000000FFU +#define SLCHOST_SLCHOST_CONF25_M (SLCHOST_SLCHOST_CONF25_V << SLCHOST_SLCHOST_CONF25_S) +#define SLCHOST_SLCHOST_CONF25_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF25_S 8 +/** SLCHOST_SLCHOST_CONF26 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF26 0x000000FFU +#define SLCHOST_SLCHOST_CONF26_M (SLCHOST_SLCHOST_CONF26_V << SLCHOST_SLCHOST_CONF26_S) +#define SLCHOST_SLCHOST_CONF26_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF26_S 16 +/** SLCHOST_SLCHOST_CONF27 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF27 0x000000FFU +#define SLCHOST_SLCHOST_CONF27_M (SLCHOST_SLCHOST_CONF27_V << SLCHOST_SLCHOST_CONF27_S) +#define SLCHOST_SLCHOST_CONF27_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF27_S 24 + +/** SLCHOST_CONF_W7_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W7_REG (DR_REG_SLCHOST_BASE + 0x8c) +/** SLCHOST_SLCHOST_CONF28 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF28 0x000000FFU +#define SLCHOST_SLCHOST_CONF28_M (SLCHOST_SLCHOST_CONF28_V << SLCHOST_SLCHOST_CONF28_S) +#define SLCHOST_SLCHOST_CONF28_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF28_S 0 +/** SLCHOST_SLCHOST_CONF29 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF29 0x000000FFU +#define SLCHOST_SLCHOST_CONF29_M (SLCHOST_SLCHOST_CONF29_V << SLCHOST_SLCHOST_CONF29_S) +#define SLCHOST_SLCHOST_CONF29_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF29_S 8 +/** SLCHOST_SLCHOST_CONF30 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF30 0x000000FFU +#define SLCHOST_SLCHOST_CONF30_M (SLCHOST_SLCHOST_CONF30_V << SLCHOST_SLCHOST_CONF30_S) +#define SLCHOST_SLCHOST_CONF30_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF30_S 16 +/** SLCHOST_SLCHOST_CONF31 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF31 0x000000FFU +#define SLCHOST_SLCHOST_CONF31_M (SLCHOST_SLCHOST_CONF31_V << SLCHOST_SLCHOST_CONF31_S) +#define SLCHOST_SLCHOST_CONF31_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF31_S 24 + +/** SLCHOST_PKT_LEN0_REG register + * *******Description*********** + */ +#define SLCHOST_PKT_LEN0_REG (DR_REG_SLCHOST_BASE + 0x90) +/** SLCHOST_HOSTSLCHOST_SLC0_LEN0 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_HOSTSLCHOST_SLC0_LEN0 0x000FFFFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_M (SLCHOST_HOSTSLCHOST_SLC0_LEN0_V << SLCHOST_HOSTSLCHOST_SLC0_LEN0_S) +#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_V 0x000FFFFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_S 0 +/** SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_M (SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_S) +#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_V 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_S 20 + +/** SLCHOST_PKT_LEN1_REG register + * *******Description*********** + */ +#define SLCHOST_PKT_LEN1_REG (DR_REG_SLCHOST_BASE + 0x94) +/** SLCHOST_HOSTSLCHOST_SLC0_LEN1 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_HOSTSLCHOST_SLC0_LEN1 0x000FFFFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_M (SLCHOST_HOSTSLCHOST_SLC0_LEN1_V << SLCHOST_HOSTSLCHOST_SLC0_LEN1_S) +#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_V 0x000FFFFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_S 0 +/** SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_M (SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_S) +#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_V 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_S 20 + +/** SLCHOST_PKT_LEN2_REG register + * *******Description*********** + */ +#define SLCHOST_PKT_LEN2_REG (DR_REG_SLCHOST_BASE + 0x98) +/** SLCHOST_HOSTSLCHOST_SLC0_LEN2 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_HOSTSLCHOST_SLC0_LEN2 0x000FFFFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_M (SLCHOST_HOSTSLCHOST_SLC0_LEN2_V << SLCHOST_HOSTSLCHOST_SLC0_LEN2_S) +#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_V 0x000FFFFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_S 0 +/** SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_M (SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_S) +#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_V 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_S 20 + +/** SLCHOST_CONF_W8_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W8_REG (DR_REG_SLCHOST_BASE + 0x9c) +/** SLCHOST_SLCHOST_CONF32 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF32 0x000000FFU +#define SLCHOST_SLCHOST_CONF32_M (SLCHOST_SLCHOST_CONF32_V << SLCHOST_SLCHOST_CONF32_S) +#define SLCHOST_SLCHOST_CONF32_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF32_S 0 +/** SLCHOST_SLCHOST_CONF33 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF33 0x000000FFU +#define SLCHOST_SLCHOST_CONF33_M (SLCHOST_SLCHOST_CONF33_V << SLCHOST_SLCHOST_CONF33_S) +#define SLCHOST_SLCHOST_CONF33_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF33_S 8 +/** SLCHOST_SLCHOST_CONF34 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF34 0x000000FFU +#define SLCHOST_SLCHOST_CONF34_M (SLCHOST_SLCHOST_CONF34_V << SLCHOST_SLCHOST_CONF34_S) +#define SLCHOST_SLCHOST_CONF34_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF34_S 16 +/** SLCHOST_SLCHOST_CONF35 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF35 0x000000FFU +#define SLCHOST_SLCHOST_CONF35_M (SLCHOST_SLCHOST_CONF35_V << SLCHOST_SLCHOST_CONF35_S) +#define SLCHOST_SLCHOST_CONF35_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF35_S 24 + +/** SLCHOST_CONF_W9_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W9_REG (DR_REG_SLCHOST_BASE + 0xa0) +/** SLCHOST_SLCHOST_CONF36 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF36 0x000000FFU +#define SLCHOST_SLCHOST_CONF36_M (SLCHOST_SLCHOST_CONF36_V << SLCHOST_SLCHOST_CONF36_S) +#define SLCHOST_SLCHOST_CONF36_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF36_S 0 +/** SLCHOST_SLCHOST_CONF37 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF37 0x000000FFU +#define SLCHOST_SLCHOST_CONF37_M (SLCHOST_SLCHOST_CONF37_V << SLCHOST_SLCHOST_CONF37_S) +#define SLCHOST_SLCHOST_CONF37_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF37_S 8 +/** SLCHOST_SLCHOST_CONF38 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF38 0x000000FFU +#define SLCHOST_SLCHOST_CONF38_M (SLCHOST_SLCHOST_CONF38_V << SLCHOST_SLCHOST_CONF38_S) +#define SLCHOST_SLCHOST_CONF38_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF38_S 16 +/** SLCHOST_SLCHOST_CONF39 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF39 0x000000FFU +#define SLCHOST_SLCHOST_CONF39_M (SLCHOST_SLCHOST_CONF39_V << SLCHOST_SLCHOST_CONF39_S) +#define SLCHOST_SLCHOST_CONF39_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF39_S 24 + +/** SLCHOST_CONF_W10_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W10_REG (DR_REG_SLCHOST_BASE + 0xa4) +/** SLCHOST_SLCHOST_CONF40 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF40 0x000000FFU +#define SLCHOST_SLCHOST_CONF40_M (SLCHOST_SLCHOST_CONF40_V << SLCHOST_SLCHOST_CONF40_S) +#define SLCHOST_SLCHOST_CONF40_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF40_S 0 +/** SLCHOST_SLCHOST_CONF41 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF41 0x000000FFU +#define SLCHOST_SLCHOST_CONF41_M (SLCHOST_SLCHOST_CONF41_V << SLCHOST_SLCHOST_CONF41_S) +#define SLCHOST_SLCHOST_CONF41_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF41_S 8 +/** SLCHOST_SLCHOST_CONF42 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF42 0x000000FFU +#define SLCHOST_SLCHOST_CONF42_M (SLCHOST_SLCHOST_CONF42_V << SLCHOST_SLCHOST_CONF42_S) +#define SLCHOST_SLCHOST_CONF42_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF42_S 16 +/** SLCHOST_SLCHOST_CONF43 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF43 0x000000FFU +#define SLCHOST_SLCHOST_CONF43_M (SLCHOST_SLCHOST_CONF43_V << SLCHOST_SLCHOST_CONF43_S) +#define SLCHOST_SLCHOST_CONF43_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF43_S 24 + +/** SLCHOST_CONF_W11_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W11_REG (DR_REG_SLCHOST_BASE + 0xa8) +/** SLCHOST_SLCHOST_CONF44 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF44 0x000000FFU +#define SLCHOST_SLCHOST_CONF44_M (SLCHOST_SLCHOST_CONF44_V << SLCHOST_SLCHOST_CONF44_S) +#define SLCHOST_SLCHOST_CONF44_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF44_S 0 +/** SLCHOST_SLCHOST_CONF45 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF45 0x000000FFU +#define SLCHOST_SLCHOST_CONF45_M (SLCHOST_SLCHOST_CONF45_V << SLCHOST_SLCHOST_CONF45_S) +#define SLCHOST_SLCHOST_CONF45_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF45_S 8 +/** SLCHOST_SLCHOST_CONF46 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF46 0x000000FFU +#define SLCHOST_SLCHOST_CONF46_M (SLCHOST_SLCHOST_CONF46_V << SLCHOST_SLCHOST_CONF46_S) +#define SLCHOST_SLCHOST_CONF46_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF46_S 16 +/** SLCHOST_SLCHOST_CONF47 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF47 0x000000FFU +#define SLCHOST_SLCHOST_CONF47_M (SLCHOST_SLCHOST_CONF47_V << SLCHOST_SLCHOST_CONF47_S) +#define SLCHOST_SLCHOST_CONF47_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF47_S 24 + +/** SLCHOST_CONF_W12_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W12_REG (DR_REG_SLCHOST_BASE + 0xac) +/** SLCHOST_SLCHOST_CONF48 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF48 0x000000FFU +#define SLCHOST_SLCHOST_CONF48_M (SLCHOST_SLCHOST_CONF48_V << SLCHOST_SLCHOST_CONF48_S) +#define SLCHOST_SLCHOST_CONF48_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF48_S 0 +/** SLCHOST_SLCHOST_CONF49 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF49 0x000000FFU +#define SLCHOST_SLCHOST_CONF49_M (SLCHOST_SLCHOST_CONF49_V << SLCHOST_SLCHOST_CONF49_S) +#define SLCHOST_SLCHOST_CONF49_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF49_S 8 +/** SLCHOST_SLCHOST_CONF50 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF50 0x000000FFU +#define SLCHOST_SLCHOST_CONF50_M (SLCHOST_SLCHOST_CONF50_V << SLCHOST_SLCHOST_CONF50_S) +#define SLCHOST_SLCHOST_CONF50_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF50_S 16 +/** SLCHOST_SLCHOST_CONF51 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF51 0x000000FFU +#define SLCHOST_SLCHOST_CONF51_M (SLCHOST_SLCHOST_CONF51_V << SLCHOST_SLCHOST_CONF51_S) +#define SLCHOST_SLCHOST_CONF51_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF51_S 24 + +/** SLCHOST_CONF_W13_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W13_REG (DR_REG_SLCHOST_BASE + 0xb0) +/** SLCHOST_SLCHOST_CONF52 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF52 0x000000FFU +#define SLCHOST_SLCHOST_CONF52_M (SLCHOST_SLCHOST_CONF52_V << SLCHOST_SLCHOST_CONF52_S) +#define SLCHOST_SLCHOST_CONF52_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF52_S 0 +/** SLCHOST_SLCHOST_CONF53 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF53 0x000000FFU +#define SLCHOST_SLCHOST_CONF53_M (SLCHOST_SLCHOST_CONF53_V << SLCHOST_SLCHOST_CONF53_S) +#define SLCHOST_SLCHOST_CONF53_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF53_S 8 +/** SLCHOST_SLCHOST_CONF54 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF54 0x000000FFU +#define SLCHOST_SLCHOST_CONF54_M (SLCHOST_SLCHOST_CONF54_V << SLCHOST_SLCHOST_CONF54_S) +#define SLCHOST_SLCHOST_CONF54_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF54_S 16 +/** SLCHOST_SLCHOST_CONF55 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF55 0x000000FFU +#define SLCHOST_SLCHOST_CONF55_M (SLCHOST_SLCHOST_CONF55_V << SLCHOST_SLCHOST_CONF55_S) +#define SLCHOST_SLCHOST_CONF55_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF55_S 24 + +/** SLCHOST_CONF_W14_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W14_REG (DR_REG_SLCHOST_BASE + 0xb4) +/** SLCHOST_SLCHOST_CONF56 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF56 0x000000FFU +#define SLCHOST_SLCHOST_CONF56_M (SLCHOST_SLCHOST_CONF56_V << SLCHOST_SLCHOST_CONF56_S) +#define SLCHOST_SLCHOST_CONF56_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF56_S 0 +/** SLCHOST_SLCHOST_CONF57 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF57 0x000000FFU +#define SLCHOST_SLCHOST_CONF57_M (SLCHOST_SLCHOST_CONF57_V << SLCHOST_SLCHOST_CONF57_S) +#define SLCHOST_SLCHOST_CONF57_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF57_S 8 +/** SLCHOST_SLCHOST_CONF58 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF58 0x000000FFU +#define SLCHOST_SLCHOST_CONF58_M (SLCHOST_SLCHOST_CONF58_V << SLCHOST_SLCHOST_CONF58_S) +#define SLCHOST_SLCHOST_CONF58_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF58_S 16 +/** SLCHOST_SLCHOST_CONF59 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF59 0x000000FFU +#define SLCHOST_SLCHOST_CONF59_M (SLCHOST_SLCHOST_CONF59_V << SLCHOST_SLCHOST_CONF59_S) +#define SLCHOST_SLCHOST_CONF59_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF59_S 24 + +/** SLCHOST_CONF_W15_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W15_REG (DR_REG_SLCHOST_BASE + 0xb8) +/** SLCHOST_SLCHOST_CONF60 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF60 0x000000FFU +#define SLCHOST_SLCHOST_CONF60_M (SLCHOST_SLCHOST_CONF60_V << SLCHOST_SLCHOST_CONF60_S) +#define SLCHOST_SLCHOST_CONF60_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF60_S 0 +/** SLCHOST_SLCHOST_CONF61 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF61 0x000000FFU +#define SLCHOST_SLCHOST_CONF61_M (SLCHOST_SLCHOST_CONF61_V << SLCHOST_SLCHOST_CONF61_S) +#define SLCHOST_SLCHOST_CONF61_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF61_S 8 +/** SLCHOST_SLCHOST_CONF62 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF62 0x000000FFU +#define SLCHOST_SLCHOST_CONF62_M (SLCHOST_SLCHOST_CONF62_V << SLCHOST_SLCHOST_CONF62_S) +#define SLCHOST_SLCHOST_CONF62_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF62_S 16 +/** SLCHOST_SLCHOST_CONF63 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF63 0x000000FFU +#define SLCHOST_SLCHOST_CONF63_M (SLCHOST_SLCHOST_CONF63_V << SLCHOST_SLCHOST_CONF63_S) +#define SLCHOST_SLCHOST_CONF63_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF63_S 24 + +/** SLCHOST_CHECK_SUM0_REG register + * *******Description*********** + */ +#define SLCHOST_CHECK_SUM0_REG (DR_REG_SLCHOST_BASE + 0xbc) +/** SLCHOST_SLCHOST_CHECK_SUM0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CHECK_SUM0 0xFFFFFFFFU +#define SLCHOST_SLCHOST_CHECK_SUM0_M (SLCHOST_SLCHOST_CHECK_SUM0_V << SLCHOST_SLCHOST_CHECK_SUM0_S) +#define SLCHOST_SLCHOST_CHECK_SUM0_V 0xFFFFFFFFU +#define SLCHOST_SLCHOST_CHECK_SUM0_S 0 + +/** SLCHOST_CHECK_SUM1_REG register + * *******Description*********** + */ +#define SLCHOST_CHECK_SUM1_REG (DR_REG_SLCHOST_BASE + 0xc0) +/** SLCHOST_SLCHOST_CHECK_SUM1 : RO; bitpos: [31:0]; default: 319; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CHECK_SUM1 0xFFFFFFFFU +#define SLCHOST_SLCHOST_CHECK_SUM1_M (SLCHOST_SLCHOST_CHECK_SUM1_V << SLCHOST_SLCHOST_CHECK_SUM1_S) +#define SLCHOST_SLCHOST_CHECK_SUM1_V 0xFFFFFFFFU +#define SLCHOST_SLCHOST_CHECK_SUM1_S 0 + +/** SLCHOST_SLC1HOST_TOKEN_RDATA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0xc4) +/** SLCHOST_SLC1_TOKEN0 : RO; bitpos: [11:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN0 0x00000FFFU +#define SLCHOST_SLC1_TOKEN0_M (SLCHOST_SLC1_TOKEN0_V << SLCHOST_SLC1_TOKEN0_S) +#define SLCHOST_SLC1_TOKEN0_V 0x00000FFFU +#define SLCHOST_SLC1_TOKEN0_S 0 +/** SLCHOST_SLC1_RX_PF_VALID : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_PF_VALID (BIT(12)) +#define SLCHOST_SLC1_RX_PF_VALID_M (SLCHOST_SLC1_RX_PF_VALID_V << SLCHOST_SLC1_RX_PF_VALID_S) +#define SLCHOST_SLC1_RX_PF_VALID_V 0x00000001U +#define SLCHOST_SLC1_RX_PF_VALID_S 12 +/** SLCHOST_HOSTSLCHOST_SLC1_TOKEN1 : RO; bitpos: [27:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_M (SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_V << SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_S) +#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_V 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_S 16 +/** SLCHOST_SLC1_RX_PF_EOF : RO; bitpos: [31:28]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_PF_EOF 0x0000000FU +#define SLCHOST_SLC1_RX_PF_EOF_M (SLCHOST_SLC1_RX_PF_EOF_V << SLCHOST_SLC1_RX_PF_EOF_S) +#define SLCHOST_SLC1_RX_PF_EOF_V 0x0000000FU +#define SLCHOST_SLC1_RX_PF_EOF_S 28 + +/** SLCHOST_SLC0HOST_TOKEN_WDATA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TOKEN_WDATA_REG (DR_REG_SLCHOST_BASE + 0xc8) +/** SLCHOST_SLC0HOST_TOKEN0_WD : R/W; bitpos: [11:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TOKEN0_WD 0x00000FFFU +#define SLCHOST_SLC0HOST_TOKEN0_WD_M (SLCHOST_SLC0HOST_TOKEN0_WD_V << SLCHOST_SLC0HOST_TOKEN0_WD_S) +#define SLCHOST_SLC0HOST_TOKEN0_WD_V 0x00000FFFU +#define SLCHOST_SLC0HOST_TOKEN0_WD_S 0 +/** SLCHOST_SLC0HOST_TOKEN1_WD : R/W; bitpos: [27:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TOKEN1_WD 0x00000FFFU +#define SLCHOST_SLC0HOST_TOKEN1_WD_M (SLCHOST_SLC0HOST_TOKEN1_WD_V << SLCHOST_SLC0HOST_TOKEN1_WD_S) +#define SLCHOST_SLC0HOST_TOKEN1_WD_V 0x00000FFFU +#define SLCHOST_SLC0HOST_TOKEN1_WD_S 16 + +/** SLCHOST_SLC1HOST_TOKEN_WDATA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TOKEN_WDATA_REG (DR_REG_SLCHOST_BASE + 0xcc) +/** SLCHOST_SLC1HOST_TOKEN0_WD : R/W; bitpos: [11:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TOKEN0_WD 0x00000FFFU +#define SLCHOST_SLC1HOST_TOKEN0_WD_M (SLCHOST_SLC1HOST_TOKEN0_WD_V << SLCHOST_SLC1HOST_TOKEN0_WD_S) +#define SLCHOST_SLC1HOST_TOKEN0_WD_V 0x00000FFFU +#define SLCHOST_SLC1HOST_TOKEN0_WD_S 0 +/** SLCHOST_SLC1HOST_TOKEN1_WD : R/W; bitpos: [27:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TOKEN1_WD 0x00000FFFU +#define SLCHOST_SLC1HOST_TOKEN1_WD_M (SLCHOST_SLC1HOST_TOKEN1_WD_V << SLCHOST_SLC1HOST_TOKEN1_WD_S) +#define SLCHOST_SLC1HOST_TOKEN1_WD_V 0x00000FFFU +#define SLCHOST_SLC1HOST_TOKEN1_WD_S 16 + +/** SLCHOST_TOKEN_CON_REG register + * *******Description*********** + */ +#define SLCHOST_TOKEN_CON_REG (DR_REG_SLCHOST_BASE + 0xd0) +/** SLCHOST_SLC0HOST_TOKEN0_DEC : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TOKEN0_DEC (BIT(0)) +#define SLCHOST_SLC0HOST_TOKEN0_DEC_M (SLCHOST_SLC0HOST_TOKEN0_DEC_V << SLCHOST_SLC0HOST_TOKEN0_DEC_S) +#define SLCHOST_SLC0HOST_TOKEN0_DEC_V 0x00000001U +#define SLCHOST_SLC0HOST_TOKEN0_DEC_S 0 +/** SLCHOST_SLC0HOST_TOKEN1_DEC : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TOKEN1_DEC (BIT(1)) +#define SLCHOST_SLC0HOST_TOKEN1_DEC_M (SLCHOST_SLC0HOST_TOKEN1_DEC_V << SLCHOST_SLC0HOST_TOKEN1_DEC_S) +#define SLCHOST_SLC0HOST_TOKEN1_DEC_V 0x00000001U +#define SLCHOST_SLC0HOST_TOKEN1_DEC_S 1 +/** SLCHOST_SLC0HOST_TOKEN0_WR : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TOKEN0_WR (BIT(2)) +#define SLCHOST_SLC0HOST_TOKEN0_WR_M (SLCHOST_SLC0HOST_TOKEN0_WR_V << SLCHOST_SLC0HOST_TOKEN0_WR_S) +#define SLCHOST_SLC0HOST_TOKEN0_WR_V 0x00000001U +#define SLCHOST_SLC0HOST_TOKEN0_WR_S 2 +/** SLCHOST_SLC0HOST_TOKEN1_WR : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TOKEN1_WR (BIT(3)) +#define SLCHOST_SLC0HOST_TOKEN1_WR_M (SLCHOST_SLC0HOST_TOKEN1_WR_V << SLCHOST_SLC0HOST_TOKEN1_WR_S) +#define SLCHOST_SLC0HOST_TOKEN1_WR_V 0x00000001U +#define SLCHOST_SLC0HOST_TOKEN1_WR_S 3 +/** SLCHOST_SLC1HOST_TOKEN0_DEC : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TOKEN0_DEC (BIT(4)) +#define SLCHOST_SLC1HOST_TOKEN0_DEC_M (SLCHOST_SLC1HOST_TOKEN0_DEC_V << SLCHOST_SLC1HOST_TOKEN0_DEC_S) +#define SLCHOST_SLC1HOST_TOKEN0_DEC_V 0x00000001U +#define SLCHOST_SLC1HOST_TOKEN0_DEC_S 4 +/** SLCHOST_SLC1HOST_TOKEN1_DEC : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TOKEN1_DEC (BIT(5)) +#define SLCHOST_SLC1HOST_TOKEN1_DEC_M (SLCHOST_SLC1HOST_TOKEN1_DEC_V << SLCHOST_SLC1HOST_TOKEN1_DEC_S) +#define SLCHOST_SLC1HOST_TOKEN1_DEC_V 0x00000001U +#define SLCHOST_SLC1HOST_TOKEN1_DEC_S 5 +/** SLCHOST_SLC1HOST_TOKEN0_WR : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TOKEN0_WR (BIT(6)) +#define SLCHOST_SLC1HOST_TOKEN0_WR_M (SLCHOST_SLC1HOST_TOKEN0_WR_V << SLCHOST_SLC1HOST_TOKEN0_WR_S) +#define SLCHOST_SLC1HOST_TOKEN0_WR_V 0x00000001U +#define SLCHOST_SLC1HOST_TOKEN0_WR_S 6 +/** SLCHOST_SLC1HOST_TOKEN1_WR : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TOKEN1_WR (BIT(7)) +#define SLCHOST_SLC1HOST_TOKEN1_WR_M (SLCHOST_SLC1HOST_TOKEN1_WR_V << SLCHOST_SLC1HOST_TOKEN1_WR_S) +#define SLCHOST_SLC1HOST_TOKEN1_WR_V 0x00000001U +#define SLCHOST_SLC1HOST_TOKEN1_WR_S 7 +/** SLCHOST_SLC0HOST_LEN_WR : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_LEN_WR (BIT(8)) +#define SLCHOST_SLC0HOST_LEN_WR_M (SLCHOST_SLC0HOST_LEN_WR_V << SLCHOST_SLC0HOST_LEN_WR_S) +#define SLCHOST_SLC0HOST_LEN_WR_V 0x00000001U +#define SLCHOST_SLC0HOST_LEN_WR_S 8 + +/** SLCHOST_SLC0HOST_INT_CLR_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xd4) +/** SLCHOST_SLC0_TOHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR (BIT(0)) +#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_S) +#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_S 0 +/** SLCHOST_SLC0_TOHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR (BIT(1)) +#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_S) +#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_S 1 +/** SLCHOST_SLC0_TOHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR (BIT(2)) +#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_S) +#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_S 2 +/** SLCHOST_SLC0_TOHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR (BIT(3)) +#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_S) +#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_S 3 +/** SLCHOST_SLC0_TOHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR (BIT(4)) +#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_S) +#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_S 4 +/** SLCHOST_SLC0_TOHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR (BIT(5)) +#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_S) +#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_S 5 +/** SLCHOST_SLC0_TOHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR (BIT(6)) +#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_S) +#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_S 6 +/** SLCHOST_SLC0_TOHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR (BIT(7)) +#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_S) +#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_S 7 +/** SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR (BIT(8)) +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_M (SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_S) +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_S 8 +/** SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR : WT; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR (BIT(9)) +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_M (SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_S) +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_S 9 +/** SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR : WT; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR (BIT(10)) +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_M (SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_S) +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_S 10 +/** SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR : WT; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR (BIT(11)) +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_M (SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_S) +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_S 11 +/** SLCHOST_SLC0HOST_RX_SOF_INT_CLR : WT; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR (BIT(12)) +#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR_M (SLCHOST_SLC0HOST_RX_SOF_INT_CLR_V << SLCHOST_SLC0HOST_RX_SOF_INT_CLR_S) +#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR_S 12 +/** SLCHOST_SLC0HOST_RX_EOF_INT_CLR : WT; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR (BIT(13)) +#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR_M (SLCHOST_SLC0HOST_RX_EOF_INT_CLR_V << SLCHOST_SLC0HOST_RX_EOF_INT_CLR_S) +#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR_S 13 +/** SLCHOST_SLC0HOST_RX_START_INT_CLR : WT; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_START_INT_CLR (BIT(14)) +#define SLCHOST_SLC0HOST_RX_START_INT_CLR_M (SLCHOST_SLC0HOST_RX_START_INT_CLR_V << SLCHOST_SLC0HOST_RX_START_INT_CLR_S) +#define SLCHOST_SLC0HOST_RX_START_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_START_INT_CLR_S 14 +/** SLCHOST_SLC0HOST_TX_START_INT_CLR : WT; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TX_START_INT_CLR (BIT(15)) +#define SLCHOST_SLC0HOST_TX_START_INT_CLR_M (SLCHOST_SLC0HOST_TX_START_INT_CLR_V << SLCHOST_SLC0HOST_TX_START_INT_CLR_S) +#define SLCHOST_SLC0HOST_TX_START_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0HOST_TX_START_INT_CLR_S 15 +/** SLCHOST_SLC0_RX_UDF_INT_CLR : WT; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_UDF_INT_CLR (BIT(16)) +#define SLCHOST_SLC0_RX_UDF_INT_CLR_M (SLCHOST_SLC0_RX_UDF_INT_CLR_V << SLCHOST_SLC0_RX_UDF_INT_CLR_S) +#define SLCHOST_SLC0_RX_UDF_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_RX_UDF_INT_CLR_S 16 +/** SLCHOST_SLC0_TX_OVF_INT_CLR : WT; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TX_OVF_INT_CLR (BIT(17)) +#define SLCHOST_SLC0_TX_OVF_INT_CLR_M (SLCHOST_SLC0_TX_OVF_INT_CLR_V << SLCHOST_SLC0_TX_OVF_INT_CLR_S) +#define SLCHOST_SLC0_TX_OVF_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TX_OVF_INT_CLR_S 17 +/** SLCHOST_SLC0_RX_PF_VALID_INT_CLR : WT; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR (BIT(18)) +#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR_M (SLCHOST_SLC0_RX_PF_VALID_INT_CLR_V << SLCHOST_SLC0_RX_PF_VALID_INT_CLR_S) +#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR_S 18 +/** SLCHOST_SLC0_EXT_BIT0_INT_CLR : WT; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT0_INT_CLR (BIT(19)) +#define SLCHOST_SLC0_EXT_BIT0_INT_CLR_M (SLCHOST_SLC0_EXT_BIT0_INT_CLR_V << SLCHOST_SLC0_EXT_BIT0_INT_CLR_S) +#define SLCHOST_SLC0_EXT_BIT0_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT0_INT_CLR_S 19 +/** SLCHOST_SLC0_EXT_BIT1_INT_CLR : WT; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT1_INT_CLR (BIT(20)) +#define SLCHOST_SLC0_EXT_BIT1_INT_CLR_M (SLCHOST_SLC0_EXT_BIT1_INT_CLR_V << SLCHOST_SLC0_EXT_BIT1_INT_CLR_S) +#define SLCHOST_SLC0_EXT_BIT1_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT1_INT_CLR_S 20 +/** SLCHOST_SLC0_EXT_BIT2_INT_CLR : WT; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT2_INT_CLR (BIT(21)) +#define SLCHOST_SLC0_EXT_BIT2_INT_CLR_M (SLCHOST_SLC0_EXT_BIT2_INT_CLR_V << SLCHOST_SLC0_EXT_BIT2_INT_CLR_S) +#define SLCHOST_SLC0_EXT_BIT2_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT2_INT_CLR_S 21 +/** SLCHOST_SLC0_EXT_BIT3_INT_CLR : WT; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT3_INT_CLR (BIT(22)) +#define SLCHOST_SLC0_EXT_BIT3_INT_CLR_M (SLCHOST_SLC0_EXT_BIT3_INT_CLR_V << SLCHOST_SLC0_EXT_BIT3_INT_CLR_S) +#define SLCHOST_SLC0_EXT_BIT3_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT3_INT_CLR_S 22 +/** SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR : WT; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR (BIT(23)) +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_M (SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_S) +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_S 23 +/** SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR : WT; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR (BIT(24)) +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_M (SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_S) +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_S 24 +/** SLCHOST_GPIO_SDIO_INT_CLR : WT; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_GPIO_SDIO_INT_CLR (BIT(25)) +#define SLCHOST_GPIO_SDIO_INT_CLR_M (SLCHOST_GPIO_SDIO_INT_CLR_V << SLCHOST_GPIO_SDIO_INT_CLR_S) +#define SLCHOST_GPIO_SDIO_INT_CLR_V 0x00000001U +#define SLCHOST_GPIO_SDIO_INT_CLR_S 25 + +/** SLCHOST_SLC1HOST_INT_CLR_REG register + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xd8) +/** SLCHOST_SLC1_TOHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR (BIT(0)) +#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_S) +#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_S 0 +/** SLCHOST_SLC1_TOHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR (BIT(1)) +#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_S) +#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_S 1 +/** SLCHOST_SLC1_TOHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR (BIT(2)) +#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_S) +#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_S 2 +/** SLCHOST_SLC1_TOHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR (BIT(3)) +#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_S) +#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_S 3 +/** SLCHOST_SLC1_TOHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR (BIT(4)) +#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_S) +#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_S 4 +/** SLCHOST_SLC1_TOHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR (BIT(5)) +#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_S) +#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_S 5 +/** SLCHOST_SLC1_TOHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR (BIT(6)) +#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_S) +#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_S 6 +/** SLCHOST_SLC1_TOHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR (BIT(7)) +#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_S) +#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_S 7 +/** SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR (BIT(8)) +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_M (SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_S) +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_S 8 +/** SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR : WT; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR (BIT(9)) +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_M (SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_S) +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_S 9 +/** SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR : WT; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR (BIT(10)) +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_M (SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_S) +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_S 10 +/** SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR : WT; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR (BIT(11)) +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_M (SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_S) +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_S 11 +/** SLCHOST_SLC1HOST_RX_SOF_INT_CLR : WT; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR (BIT(12)) +#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR_M (SLCHOST_SLC1HOST_RX_SOF_INT_CLR_V << SLCHOST_SLC1HOST_RX_SOF_INT_CLR_S) +#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR_S 12 +/** SLCHOST_SLC1HOST_RX_EOF_INT_CLR : WT; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR (BIT(13)) +#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR_M (SLCHOST_SLC1HOST_RX_EOF_INT_CLR_V << SLCHOST_SLC1HOST_RX_EOF_INT_CLR_S) +#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR_S 13 +/** SLCHOST_SLC1HOST_RX_START_INT_CLR : WT; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_START_INT_CLR (BIT(14)) +#define SLCHOST_SLC1HOST_RX_START_INT_CLR_M (SLCHOST_SLC1HOST_RX_START_INT_CLR_V << SLCHOST_SLC1HOST_RX_START_INT_CLR_S) +#define SLCHOST_SLC1HOST_RX_START_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_START_INT_CLR_S 14 +/** SLCHOST_SLC1HOST_TX_START_INT_CLR : WT; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TX_START_INT_CLR (BIT(15)) +#define SLCHOST_SLC1HOST_TX_START_INT_CLR_M (SLCHOST_SLC1HOST_TX_START_INT_CLR_V << SLCHOST_SLC1HOST_TX_START_INT_CLR_S) +#define SLCHOST_SLC1HOST_TX_START_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1HOST_TX_START_INT_CLR_S 15 +/** SLCHOST_SLC1_RX_UDF_INT_CLR : WT; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_UDF_INT_CLR (BIT(16)) +#define SLCHOST_SLC1_RX_UDF_INT_CLR_M (SLCHOST_SLC1_RX_UDF_INT_CLR_V << SLCHOST_SLC1_RX_UDF_INT_CLR_S) +#define SLCHOST_SLC1_RX_UDF_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_RX_UDF_INT_CLR_S 16 +/** SLCHOST_SLC1_TX_OVF_INT_CLR : WT; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TX_OVF_INT_CLR (BIT(17)) +#define SLCHOST_SLC1_TX_OVF_INT_CLR_M (SLCHOST_SLC1_TX_OVF_INT_CLR_V << SLCHOST_SLC1_TX_OVF_INT_CLR_S) +#define SLCHOST_SLC1_TX_OVF_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TX_OVF_INT_CLR_S 17 +/** SLCHOST_SLC1_RX_PF_VALID_INT_CLR : WT; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR (BIT(18)) +#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR_M (SLCHOST_SLC1_RX_PF_VALID_INT_CLR_V << SLCHOST_SLC1_RX_PF_VALID_INT_CLR_S) +#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR_S 18 +/** SLCHOST_SLC1_EXT_BIT0_INT_CLR : WT; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT0_INT_CLR (BIT(19)) +#define SLCHOST_SLC1_EXT_BIT0_INT_CLR_M (SLCHOST_SLC1_EXT_BIT0_INT_CLR_V << SLCHOST_SLC1_EXT_BIT0_INT_CLR_S) +#define SLCHOST_SLC1_EXT_BIT0_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT0_INT_CLR_S 19 +/** SLCHOST_SLC1_EXT_BIT1_INT_CLR : WT; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT1_INT_CLR (BIT(20)) +#define SLCHOST_SLC1_EXT_BIT1_INT_CLR_M (SLCHOST_SLC1_EXT_BIT1_INT_CLR_V << SLCHOST_SLC1_EXT_BIT1_INT_CLR_S) +#define SLCHOST_SLC1_EXT_BIT1_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT1_INT_CLR_S 20 +/** SLCHOST_SLC1_EXT_BIT2_INT_CLR : WT; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT2_INT_CLR (BIT(21)) +#define SLCHOST_SLC1_EXT_BIT2_INT_CLR_M (SLCHOST_SLC1_EXT_BIT2_INT_CLR_V << SLCHOST_SLC1_EXT_BIT2_INT_CLR_S) +#define SLCHOST_SLC1_EXT_BIT2_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT2_INT_CLR_S 21 +/** SLCHOST_SLC1_EXT_BIT3_INT_CLR : WT; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT3_INT_CLR (BIT(22)) +#define SLCHOST_SLC1_EXT_BIT3_INT_CLR_M (SLCHOST_SLC1_EXT_BIT3_INT_CLR_V << SLCHOST_SLC1_EXT_BIT3_INT_CLR_S) +#define SLCHOST_SLC1_EXT_BIT3_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT3_INT_CLR_S 22 +/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR : WT; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR (BIT(23)) +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_M (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_S) +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_S 23 +/** SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR : WT; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR (BIT(24)) +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_M (SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_S) +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_S 24 +/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR : WT; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR (BIT(25)) +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_M (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_S) +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_S 25 + +/** SLCHOST_SLC0HOST_FUNC1_INT_ENA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xdc) +/** SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S 0 +/** SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S 1 +/** SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S 2 +/** SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S 3 +/** SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S 4 +/** SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S 5 +/** SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S 6 +/** SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S 7 +/** SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_M (SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S 8 +/** SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_M (SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S 9 +/** SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_M (SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S 10 +/** SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_M (SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S 11 +/** SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) +#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_M (SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V << SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S) +#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S 12 +/** SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) +#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_M (SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V << SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S) +#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S 13 +/** SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA (BIT(14)) +#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_M (SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_V << SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_S) +#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_S 14 +/** SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA (BIT(15)) +#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_M (SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_V << SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_S) +#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_S 15 +/** SLCHOST_FN1_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA (BIT(16)) +#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_M (SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_V << SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_S) +#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_S 16 +/** SLCHOST_FN1_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA (BIT(17)) +#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_M (SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_V << SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_S 17 +/** SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) +#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_M (SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V << SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S) +#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S 18 +/** SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA (BIT(19)) +#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_M (SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_S) +#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_S 19 +/** SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA (BIT(20)) +#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_M (SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_S) +#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_S 20 +/** SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA (BIT(21)) +#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_M (SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_S) +#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_S 21 +/** SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA (BIT(22)) +#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_M (SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_S) +#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_S 22 +/** SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_M (SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S) +#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S 23 +/** SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_M (SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S) +#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S 24 +/** SLCHOST_FN1_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_GPIO_SDIO_INT_ENA (BIT(25)) +#define SLCHOST_FN1_GPIO_SDIO_INT_ENA_M (SLCHOST_FN1_GPIO_SDIO_INT_ENA_V << SLCHOST_FN1_GPIO_SDIO_INT_ENA_S) +#define SLCHOST_FN1_GPIO_SDIO_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_GPIO_SDIO_INT_ENA_S 25 + +/** SLCHOST_SLC1HOST_FUNC1_INT_ENA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xe0) +/** SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_S 0 +/** SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_S 1 +/** SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_S 2 +/** SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_S 3 +/** SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_S 4 +/** SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_S 5 +/** SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_S 6 +/** SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_S 7 +/** SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_M (SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_S 8 +/** SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_M (SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_S 9 +/** SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_M (SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_S 10 +/** SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_M (SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_S 11 +/** SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA (BIT(12)) +#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_M (SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_V << SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_S) +#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_S 12 +/** SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA (BIT(13)) +#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_M (SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_V << SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_S) +#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_S 13 +/** SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA (BIT(14)) +#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_M (SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_V << SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_S) +#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_S 14 +/** SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA (BIT(15)) +#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_M (SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_V << SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_S) +#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_S 15 +/** SLCHOST_FN1_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA (BIT(16)) +#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_M (SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_V << SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_S) +#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_S 16 +/** SLCHOST_FN1_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA (BIT(17)) +#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_M (SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_V << SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_S 17 +/** SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA (BIT(18)) +#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_M (SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_V << SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_S) +#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_S 18 +/** SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA (BIT(19)) +#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_M (SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_S) +#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_S 19 +/** SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA (BIT(20)) +#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_M (SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_S) +#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_S 20 +/** SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA (BIT(21)) +#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_M (SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_S) +#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_S 21 +/** SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA (BIT(22)) +#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_M (SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_S) +#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_S 22 +/** SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S) +#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23 +/** SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_M (SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_S) +#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_S 24 +/** SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25)) +#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_S) +#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25 + +/** SLCHOST_SLC0HOST_FUNC2_INT_ENA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_FUNC2_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xe4) +/** SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_S 0 +/** SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_S 1 +/** SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_S 2 +/** SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_S 3 +/** SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_S 4 +/** SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_S 5 +/** SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_S 6 +/** SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_S 7 +/** SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_M (SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_S 8 +/** SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_M (SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_S 9 +/** SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_M (SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_S 10 +/** SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_M (SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_S 11 +/** SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) +#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_M (SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_V << SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_S) +#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_S 12 +/** SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) +#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_M (SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_V << SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_S) +#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_S 13 +/** SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA (BIT(14)) +#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_M (SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_V << SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_S) +#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_S 14 +/** SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA (BIT(15)) +#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_M (SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_V << SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_S) +#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_S 15 +/** SLCHOST_FN2_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA (BIT(16)) +#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_M (SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_V << SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_S) +#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_S 16 +/** SLCHOST_FN2_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA (BIT(17)) +#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_M (SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_V << SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_S 17 +/** SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) +#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_M (SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_V << SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_S) +#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_S 18 +/** SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA (BIT(19)) +#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_M (SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_S) +#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_S 19 +/** SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA (BIT(20)) +#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_M (SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_S) +#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_S 20 +/** SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA (BIT(21)) +#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_M (SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_S) +#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_S 21 +/** SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA (BIT(22)) +#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_M (SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_S) +#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_S 22 +/** SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_M (SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_S) +#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_S 23 +/** SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_M (SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_S) +#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_S 24 +/** SLCHOST_FN2_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_GPIO_SDIO_INT_ENA (BIT(25)) +#define SLCHOST_FN2_GPIO_SDIO_INT_ENA_M (SLCHOST_FN2_GPIO_SDIO_INT_ENA_V << SLCHOST_FN2_GPIO_SDIO_INT_ENA_S) +#define SLCHOST_FN2_GPIO_SDIO_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_GPIO_SDIO_INT_ENA_S 25 + +/** SLCHOST_SLC1HOST_FUNC2_INT_ENA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_FUNC2_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xe8) +/** SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_S 0 +/** SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_S 1 +/** SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_S 2 +/** SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_S 3 +/** SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_S 4 +/** SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_S 5 +/** SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_S 6 +/** SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_S 7 +/** SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_M (SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_S 8 +/** SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_M (SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_S 9 +/** SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_M (SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_S 10 +/** SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_M (SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_S 11 +/** SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA (BIT(12)) +#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_M (SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_V << SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_S) +#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_S 12 +/** SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA (BIT(13)) +#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_M (SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_V << SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_S) +#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_S 13 +/** SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA (BIT(14)) +#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_M (SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_V << SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_S) +#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_S 14 +/** SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA (BIT(15)) +#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_M (SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_V << SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_S) +#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_S 15 +/** SLCHOST_FN2_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA (BIT(16)) +#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_M (SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_V << SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_S) +#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_S 16 +/** SLCHOST_FN2_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA (BIT(17)) +#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_M (SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_V << SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_S 17 +/** SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA (BIT(18)) +#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_M (SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_V << SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_S) +#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_S 18 +/** SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA (BIT(19)) +#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_M (SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_S) +#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_S 19 +/** SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA (BIT(20)) +#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_M (SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_S) +#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_S 20 +/** SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA (BIT(21)) +#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_M (SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_S) +#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_S 21 +/** SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA (BIT(22)) +#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_M (SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_S) +#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_S 22 +/** SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S) +#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23 +/** SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_M (SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_S) +#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_S 24 +/** SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25)) +#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_S) +#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25 + +/** SLCHOST_SLC0HOST_INT_ENA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xec) +/** SLCHOST_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_S) +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_S 0 +/** SLCHOST_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_S) +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_S 1 +/** SLCHOST_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_S) +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_S 2 +/** SLCHOST_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_S) +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_S 3 +/** SLCHOST_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_S) +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_S 4 +/** SLCHOST_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_S) +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_S 5 +/** SLCHOST_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_S) +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_S 6 +/** SLCHOST_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_S) +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_S 7 +/** SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_M (SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_S) +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_S 8 +/** SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_M (SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_S) +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_S 9 +/** SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_M (SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_S) +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_S 10 +/** SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_M (SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_S) +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_S 11 +/** SLCHOST_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) +#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA_M (SLCHOST_SLC0HOST_RX_SOF_INT_ENA_V << SLCHOST_SLC0HOST_RX_SOF_INT_ENA_S) +#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA_S 12 +/** SLCHOST_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) +#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA_M (SLCHOST_SLC0HOST_RX_EOF_INT_ENA_V << SLCHOST_SLC0HOST_RX_EOF_INT_ENA_S) +#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA_S 13 +/** SLCHOST_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_START_INT_ENA (BIT(14)) +#define SLCHOST_SLC0HOST_RX_START_INT_ENA_M (SLCHOST_SLC0HOST_RX_START_INT_ENA_V << SLCHOST_SLC0HOST_RX_START_INT_ENA_S) +#define SLCHOST_SLC0HOST_RX_START_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_START_INT_ENA_S 14 +/** SLCHOST_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TX_START_INT_ENA (BIT(15)) +#define SLCHOST_SLC0HOST_TX_START_INT_ENA_M (SLCHOST_SLC0HOST_TX_START_INT_ENA_V << SLCHOST_SLC0HOST_TX_START_INT_ENA_S) +#define SLCHOST_SLC0HOST_TX_START_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0HOST_TX_START_INT_ENA_S 15 +/** SLCHOST_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_UDF_INT_ENA (BIT(16)) +#define SLCHOST_SLC0_RX_UDF_INT_ENA_M (SLCHOST_SLC0_RX_UDF_INT_ENA_V << SLCHOST_SLC0_RX_UDF_INT_ENA_S) +#define SLCHOST_SLC0_RX_UDF_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_RX_UDF_INT_ENA_S 16 +/** SLCHOST_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TX_OVF_INT_ENA (BIT(17)) +#define SLCHOST_SLC0_TX_OVF_INT_ENA_M (SLCHOST_SLC0_TX_OVF_INT_ENA_V << SLCHOST_SLC0_TX_OVF_INT_ENA_S) +#define SLCHOST_SLC0_TX_OVF_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TX_OVF_INT_ENA_S 17 +/** SLCHOST_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) +#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA_M (SLCHOST_SLC0_RX_PF_VALID_INT_ENA_V << SLCHOST_SLC0_RX_PF_VALID_INT_ENA_S) +#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA_S 18 +/** SLCHOST_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT0_INT_ENA (BIT(19)) +#define SLCHOST_SLC0_EXT_BIT0_INT_ENA_M (SLCHOST_SLC0_EXT_BIT0_INT_ENA_V << SLCHOST_SLC0_EXT_BIT0_INT_ENA_S) +#define SLCHOST_SLC0_EXT_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT0_INT_ENA_S 19 +/** SLCHOST_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT1_INT_ENA (BIT(20)) +#define SLCHOST_SLC0_EXT_BIT1_INT_ENA_M (SLCHOST_SLC0_EXT_BIT1_INT_ENA_V << SLCHOST_SLC0_EXT_BIT1_INT_ENA_S) +#define SLCHOST_SLC0_EXT_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT1_INT_ENA_S 20 +/** SLCHOST_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT2_INT_ENA (BIT(21)) +#define SLCHOST_SLC0_EXT_BIT2_INT_ENA_M (SLCHOST_SLC0_EXT_BIT2_INT_ENA_V << SLCHOST_SLC0_EXT_BIT2_INT_ENA_S) +#define SLCHOST_SLC0_EXT_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT2_INT_ENA_S 21 +/** SLCHOST_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT3_INT_ENA (BIT(22)) +#define SLCHOST_SLC0_EXT_BIT3_INT_ENA_M (SLCHOST_SLC0_EXT_BIT3_INT_ENA_V << SLCHOST_SLC0_EXT_BIT3_INT_ENA_S) +#define SLCHOST_SLC0_EXT_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT3_INT_ENA_S 22 +/** SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_M (SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_S) +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_S 23 +/** SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_M (SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_S) +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_S 24 +/** SLCHOST_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_GPIO_SDIO_INT_ENA (BIT(25)) +#define SLCHOST_GPIO_SDIO_INT_ENA_M (SLCHOST_GPIO_SDIO_INT_ENA_V << SLCHOST_GPIO_SDIO_INT_ENA_S) +#define SLCHOST_GPIO_SDIO_INT_ENA_V 0x00000001U +#define SLCHOST_GPIO_SDIO_INT_ENA_S 25 + +/** SLCHOST_SLC1HOST_INT_ENA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xf0) +/** SLCHOST_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_S) +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_S 0 +/** SLCHOST_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_S) +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_S 1 +/** SLCHOST_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_S) +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_S 2 +/** SLCHOST_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_S) +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_S 3 +/** SLCHOST_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_S) +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_S 4 +/** SLCHOST_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_S) +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_S 5 +/** SLCHOST_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_S) +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_S 6 +/** SLCHOST_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_S) +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_S 7 +/** SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_M (SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_S) +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_S 8 +/** SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_M (SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_S) +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_S 9 +/** SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_M (SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_S) +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_S 10 +/** SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_M (SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_S) +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_S 11 +/** SLCHOST_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA (BIT(12)) +#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA_M (SLCHOST_SLC1HOST_RX_SOF_INT_ENA_V << SLCHOST_SLC1HOST_RX_SOF_INT_ENA_S) +#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA_S 12 +/** SLCHOST_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA (BIT(13)) +#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA_M (SLCHOST_SLC1HOST_RX_EOF_INT_ENA_V << SLCHOST_SLC1HOST_RX_EOF_INT_ENA_S) +#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA_S 13 +/** SLCHOST_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_START_INT_ENA (BIT(14)) +#define SLCHOST_SLC1HOST_RX_START_INT_ENA_M (SLCHOST_SLC1HOST_RX_START_INT_ENA_V << SLCHOST_SLC1HOST_RX_START_INT_ENA_S) +#define SLCHOST_SLC1HOST_RX_START_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_START_INT_ENA_S 14 +/** SLCHOST_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TX_START_INT_ENA (BIT(15)) +#define SLCHOST_SLC1HOST_TX_START_INT_ENA_M (SLCHOST_SLC1HOST_TX_START_INT_ENA_V << SLCHOST_SLC1HOST_TX_START_INT_ENA_S) +#define SLCHOST_SLC1HOST_TX_START_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1HOST_TX_START_INT_ENA_S 15 +/** SLCHOST_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_UDF_INT_ENA (BIT(16)) +#define SLCHOST_SLC1_RX_UDF_INT_ENA_M (SLCHOST_SLC1_RX_UDF_INT_ENA_V << SLCHOST_SLC1_RX_UDF_INT_ENA_S) +#define SLCHOST_SLC1_RX_UDF_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_RX_UDF_INT_ENA_S 16 +/** SLCHOST_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TX_OVF_INT_ENA (BIT(17)) +#define SLCHOST_SLC1_TX_OVF_INT_ENA_M (SLCHOST_SLC1_TX_OVF_INT_ENA_V << SLCHOST_SLC1_TX_OVF_INT_ENA_S) +#define SLCHOST_SLC1_TX_OVF_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TX_OVF_INT_ENA_S 17 +/** SLCHOST_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA (BIT(18)) +#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA_M (SLCHOST_SLC1_RX_PF_VALID_INT_ENA_V << SLCHOST_SLC1_RX_PF_VALID_INT_ENA_S) +#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA_S 18 +/** SLCHOST_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT0_INT_ENA (BIT(19)) +#define SLCHOST_SLC1_EXT_BIT0_INT_ENA_M (SLCHOST_SLC1_EXT_BIT0_INT_ENA_V << SLCHOST_SLC1_EXT_BIT0_INT_ENA_S) +#define SLCHOST_SLC1_EXT_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT0_INT_ENA_S 19 +/** SLCHOST_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT1_INT_ENA (BIT(20)) +#define SLCHOST_SLC1_EXT_BIT1_INT_ENA_M (SLCHOST_SLC1_EXT_BIT1_INT_ENA_V << SLCHOST_SLC1_EXT_BIT1_INT_ENA_S) +#define SLCHOST_SLC1_EXT_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT1_INT_ENA_S 20 +/** SLCHOST_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT2_INT_ENA (BIT(21)) +#define SLCHOST_SLC1_EXT_BIT2_INT_ENA_M (SLCHOST_SLC1_EXT_BIT2_INT_ENA_V << SLCHOST_SLC1_EXT_BIT2_INT_ENA_S) +#define SLCHOST_SLC1_EXT_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT2_INT_ENA_S 21 +/** SLCHOST_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT3_INT_ENA (BIT(22)) +#define SLCHOST_SLC1_EXT_BIT3_INT_ENA_M (SLCHOST_SLC1_EXT_BIT3_INT_ENA_V << SLCHOST_SLC1_EXT_BIT3_INT_ENA_S) +#define SLCHOST_SLC1_EXT_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT3_INT_ENA_S 22 +/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S) +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23 +/** SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_M (SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_S) +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_S 24 +/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25)) +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_S) +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25 + +/** SLCHOST_SLC0HOST_RX_INFOR_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_INFOR_REG (DR_REG_SLCHOST_BASE + 0xf4) +/** SLCHOST_SLC0HOST_RX_INFOR : R/W; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_INFOR 0x000FFFFFU +#define SLCHOST_SLC0HOST_RX_INFOR_M (SLCHOST_SLC0HOST_RX_INFOR_V << SLCHOST_SLC0HOST_RX_INFOR_S) +#define SLCHOST_SLC0HOST_RX_INFOR_V 0x000FFFFFU +#define SLCHOST_SLC0HOST_RX_INFOR_S 0 + +/** SLCHOST_SLC1HOST_RX_INFOR_REG register + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_INFOR_REG (DR_REG_SLCHOST_BASE + 0xf8) +/** SLCHOST_SLC1HOST_RX_INFOR : R/W; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_INFOR 0x000FFFFFU +#define SLCHOST_SLC1HOST_RX_INFOR_M (SLCHOST_SLC1HOST_RX_INFOR_V << SLCHOST_SLC1HOST_RX_INFOR_S) +#define SLCHOST_SLC1HOST_RX_INFOR_V 0x000FFFFFU +#define SLCHOST_SLC1HOST_RX_INFOR_S 0 + +/** SLCHOST_SLC0HOST_LEN_WD_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_LEN_WD_REG (DR_REG_SLCHOST_BASE + 0xfc) +/** SLCHOST_SLC0HOST_LEN_WD : R/W; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_LEN_WD 0xFFFFFFFFU +#define SLCHOST_SLC0HOST_LEN_WD_M (SLCHOST_SLC0HOST_LEN_WD_V << SLCHOST_SLC0HOST_LEN_WD_S) +#define SLCHOST_SLC0HOST_LEN_WD_V 0xFFFFFFFFU +#define SLCHOST_SLC0HOST_LEN_WD_S 0 + +/** SLCHOST_SLC_APBWIN_WDATA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC_APBWIN_WDATA_REG (DR_REG_SLCHOST_BASE + 0x100) +/** SLCHOST_SLC_APBWIN_WDATA : R/W; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC_APBWIN_WDATA 0xFFFFFFFFU +#define SLCHOST_SLC_APBWIN_WDATA_M (SLCHOST_SLC_APBWIN_WDATA_V << SLCHOST_SLC_APBWIN_WDATA_S) +#define SLCHOST_SLC_APBWIN_WDATA_V 0xFFFFFFFFU +#define SLCHOST_SLC_APBWIN_WDATA_S 0 + +/** SLCHOST_SLC_APBWIN_CONF_REG register + * *******Description*********** + */ +#define SLCHOST_SLC_APBWIN_CONF_REG (DR_REG_SLCHOST_BASE + 0x104) +/** SLCHOST_SLC_APBWIN_ADDR : R/W; bitpos: [27:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC_APBWIN_ADDR 0x0FFFFFFFU +#define SLCHOST_SLC_APBWIN_ADDR_M (SLCHOST_SLC_APBWIN_ADDR_V << SLCHOST_SLC_APBWIN_ADDR_S) +#define SLCHOST_SLC_APBWIN_ADDR_V 0x0FFFFFFFU +#define SLCHOST_SLC_APBWIN_ADDR_S 0 +/** SLCHOST_SLC_APBWIN_WR : R/W; bitpos: [28]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC_APBWIN_WR (BIT(28)) +#define SLCHOST_SLC_APBWIN_WR_M (SLCHOST_SLC_APBWIN_WR_V << SLCHOST_SLC_APBWIN_WR_S) +#define SLCHOST_SLC_APBWIN_WR_V 0x00000001U +#define SLCHOST_SLC_APBWIN_WR_S 28 +/** SLCHOST_SLC_APBWIN_START : R/W/SC; bitpos: [29]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC_APBWIN_START (BIT(29)) +#define SLCHOST_SLC_APBWIN_START_M (SLCHOST_SLC_APBWIN_START_V << SLCHOST_SLC_APBWIN_START_S) +#define SLCHOST_SLC_APBWIN_START_V 0x00000001U +#define SLCHOST_SLC_APBWIN_START_S 29 + +/** SLCHOST_SLC_APBWIN_RDATA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC_APBWIN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x108) +/** SLCHOST_SLC_APBWIN_RDATA : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC_APBWIN_RDATA 0xFFFFFFFFU +#define SLCHOST_SLC_APBWIN_RDATA_M (SLCHOST_SLC_APBWIN_RDATA_V << SLCHOST_SLC_APBWIN_RDATA_S) +#define SLCHOST_SLC_APBWIN_RDATA_V 0xFFFFFFFFU +#define SLCHOST_SLC_APBWIN_RDATA_S 0 + +/** SLCHOST_RDCLR0_REG register + * *******Description*********** + */ +#define SLCHOST_RDCLR0_REG (DR_REG_SLCHOST_BASE + 0x10c) +/** SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR : R/W; bitpos: [8:0]; default: 68; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR 0x000001FFU +#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_M (SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_V << SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_S) +#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_V 0x000001FFU +#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_S 0 +/** SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR : R/W; bitpos: [17:9]; default: 480; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR 0x000001FFU +#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_M (SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_V << SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_S) +#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_V 0x000001FFU +#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_S 9 + +/** SLCHOST_RDCLR1_REG register + * *******Description*********** + */ +#define SLCHOST_RDCLR1_REG (DR_REG_SLCHOST_BASE + 0x110) +/** SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR : R/W; bitpos: [8:0]; default: 480; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR 0x000001FFU +#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_M (SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_V << SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_S) +#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_V 0x000001FFU +#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_S 0 +/** SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR : R/W; bitpos: [17:9]; default: 480; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR 0x000001FFU +#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_M (SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_V << SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_S) +#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_V 0x000001FFU +#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_S 9 + +/** SLCHOST_SLC0HOST_INT_ENA1_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_INT_ENA1_REG (DR_REG_SLCHOST_BASE + 0x114) +/** SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1 (BIT(0)) +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_S) +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_S 0 +/** SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1 (BIT(1)) +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_S) +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_S 1 +/** SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1 (BIT(2)) +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_S) +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_S 2 +/** SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1 (BIT(3)) +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_S) +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_S 3 +/** SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1 (BIT(4)) +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_S) +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_S 4 +/** SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1 (BIT(5)) +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_S) +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_S 5 +/** SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1 (BIT(6)) +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_S) +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_S 6 +/** SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1 (BIT(7)) +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_S) +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_S 7 +/** SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1 (BIT(8)) +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_M (SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_S) +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_S 8 +/** SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1 (BIT(9)) +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_M (SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_S) +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_S 9 +/** SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1 : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1 (BIT(10)) +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_M (SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_S) +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_S 10 +/** SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1 : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1 (BIT(11)) +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_M (SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_S) +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_S 11 +/** SLCHOST_SLC0HOST_RX_SOF_INT_ENA1 : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1 (BIT(12)) +#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_M (SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_V << SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_S) +#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_S 12 +/** SLCHOST_SLC0HOST_RX_EOF_INT_ENA1 : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1 (BIT(13)) +#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_M (SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_V << SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_S) +#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_S 13 +/** SLCHOST_SLC0HOST_RX_START_INT_ENA1 : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_START_INT_ENA1 (BIT(14)) +#define SLCHOST_SLC0HOST_RX_START_INT_ENA1_M (SLCHOST_SLC0HOST_RX_START_INT_ENA1_V << SLCHOST_SLC0HOST_RX_START_INT_ENA1_S) +#define SLCHOST_SLC0HOST_RX_START_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_START_INT_ENA1_S 14 +/** SLCHOST_SLC0HOST_TX_START_INT_ENA1 : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TX_START_INT_ENA1 (BIT(15)) +#define SLCHOST_SLC0HOST_TX_START_INT_ENA1_M (SLCHOST_SLC0HOST_TX_START_INT_ENA1_V << SLCHOST_SLC0HOST_TX_START_INT_ENA1_S) +#define SLCHOST_SLC0HOST_TX_START_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0HOST_TX_START_INT_ENA1_S 15 +/** SLCHOST_SLC0_RX_UDF_INT_ENA1 : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_UDF_INT_ENA1 (BIT(16)) +#define SLCHOST_SLC0_RX_UDF_INT_ENA1_M (SLCHOST_SLC0_RX_UDF_INT_ENA1_V << SLCHOST_SLC0_RX_UDF_INT_ENA1_S) +#define SLCHOST_SLC0_RX_UDF_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_RX_UDF_INT_ENA1_S 16 +/** SLCHOST_SLC0_TX_OVF_INT_ENA1 : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TX_OVF_INT_ENA1 (BIT(17)) +#define SLCHOST_SLC0_TX_OVF_INT_ENA1_M (SLCHOST_SLC0_TX_OVF_INT_ENA1_V << SLCHOST_SLC0_TX_OVF_INT_ENA1_S) +#define SLCHOST_SLC0_TX_OVF_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TX_OVF_INT_ENA1_S 17 +/** SLCHOST_SLC0_RX_PF_VALID_INT_ENA1 : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1 (BIT(18)) +#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_M (SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_V << SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_S) +#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_S 18 +/** SLCHOST_SLC0_EXT_BIT0_INT_ENA1 : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1 (BIT(19)) +#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1_M (SLCHOST_SLC0_EXT_BIT0_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT0_INT_ENA1_S) +#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1_S 19 +/** SLCHOST_SLC0_EXT_BIT1_INT_ENA1 : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1 (BIT(20)) +#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1_M (SLCHOST_SLC0_EXT_BIT1_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT1_INT_ENA1_S) +#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1_S 20 +/** SLCHOST_SLC0_EXT_BIT2_INT_ENA1 : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1 (BIT(21)) +#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1_M (SLCHOST_SLC0_EXT_BIT2_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT2_INT_ENA1_S) +#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1_S 21 +/** SLCHOST_SLC0_EXT_BIT3_INT_ENA1 : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1 (BIT(22)) +#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1_M (SLCHOST_SLC0_EXT_BIT3_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT3_INT_ENA1_S) +#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1_S 22 +/** SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1 (BIT(23)) +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_M (SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_S) +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_S 23 +/** SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1 : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1 (BIT(24)) +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_M (SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_S) +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_S 24 +/** SLCHOST_GPIO_SDIO_INT_ENA1 : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_GPIO_SDIO_INT_ENA1 (BIT(25)) +#define SLCHOST_GPIO_SDIO_INT_ENA1_M (SLCHOST_GPIO_SDIO_INT_ENA1_V << SLCHOST_GPIO_SDIO_INT_ENA1_S) +#define SLCHOST_GPIO_SDIO_INT_ENA1_V 0x00000001U +#define SLCHOST_GPIO_SDIO_INT_ENA1_S 25 + +/** SLCHOST_SLC1HOST_INT_ENA1_REG register + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_INT_ENA1_REG (DR_REG_SLCHOST_BASE + 0x118) +/** SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1 (BIT(0)) +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_S) +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_S 0 +/** SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1 (BIT(1)) +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_S) +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_S 1 +/** SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1 (BIT(2)) +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_S) +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_S 2 +/** SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1 (BIT(3)) +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_S) +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_S 3 +/** SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1 (BIT(4)) +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_S) +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_S 4 +/** SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1 (BIT(5)) +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_S) +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_S 5 +/** SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1 (BIT(6)) +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_S) +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_S 6 +/** SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1 (BIT(7)) +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_S) +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_S 7 +/** SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1 (BIT(8)) +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_M (SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_S) +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_S 8 +/** SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1 (BIT(9)) +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_M (SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_S) +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_S 9 +/** SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1 : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1 (BIT(10)) +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_M (SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_S) +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_S 10 +/** SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1 : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1 (BIT(11)) +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_M (SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_S) +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_S 11 +/** SLCHOST_SLC1HOST_RX_SOF_INT_ENA1 : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1 (BIT(12)) +#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_M (SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_V << SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_S) +#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_S 12 +/** SLCHOST_SLC1HOST_RX_EOF_INT_ENA1 : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1 (BIT(13)) +#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_M (SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_V << SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_S) +#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_S 13 +/** SLCHOST_SLC1HOST_RX_START_INT_ENA1 : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_START_INT_ENA1 (BIT(14)) +#define SLCHOST_SLC1HOST_RX_START_INT_ENA1_M (SLCHOST_SLC1HOST_RX_START_INT_ENA1_V << SLCHOST_SLC1HOST_RX_START_INT_ENA1_S) +#define SLCHOST_SLC1HOST_RX_START_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_START_INT_ENA1_S 14 +/** SLCHOST_SLC1HOST_TX_START_INT_ENA1 : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TX_START_INT_ENA1 (BIT(15)) +#define SLCHOST_SLC1HOST_TX_START_INT_ENA1_M (SLCHOST_SLC1HOST_TX_START_INT_ENA1_V << SLCHOST_SLC1HOST_TX_START_INT_ENA1_S) +#define SLCHOST_SLC1HOST_TX_START_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1HOST_TX_START_INT_ENA1_S 15 +/** SLCHOST_SLC1_RX_UDF_INT_ENA1 : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_UDF_INT_ENA1 (BIT(16)) +#define SLCHOST_SLC1_RX_UDF_INT_ENA1_M (SLCHOST_SLC1_RX_UDF_INT_ENA1_V << SLCHOST_SLC1_RX_UDF_INT_ENA1_S) +#define SLCHOST_SLC1_RX_UDF_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_RX_UDF_INT_ENA1_S 16 +/** SLCHOST_SLC1_TX_OVF_INT_ENA1 : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TX_OVF_INT_ENA1 (BIT(17)) +#define SLCHOST_SLC1_TX_OVF_INT_ENA1_M (SLCHOST_SLC1_TX_OVF_INT_ENA1_V << SLCHOST_SLC1_TX_OVF_INT_ENA1_S) +#define SLCHOST_SLC1_TX_OVF_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TX_OVF_INT_ENA1_S 17 +/** SLCHOST_SLC1_RX_PF_VALID_INT_ENA1 : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1 (BIT(18)) +#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_M (SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_V << SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_S) +#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_S 18 +/** SLCHOST_SLC1_EXT_BIT0_INT_ENA1 : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1 (BIT(19)) +#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1_M (SLCHOST_SLC1_EXT_BIT0_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT0_INT_ENA1_S) +#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1_S 19 +/** SLCHOST_SLC1_EXT_BIT1_INT_ENA1 : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1 (BIT(20)) +#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1_M (SLCHOST_SLC1_EXT_BIT1_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT1_INT_ENA1_S) +#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1_S 20 +/** SLCHOST_SLC1_EXT_BIT2_INT_ENA1 : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1 (BIT(21)) +#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1_M (SLCHOST_SLC1_EXT_BIT2_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT2_INT_ENA1_S) +#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1_S 21 +/** SLCHOST_SLC1_EXT_BIT3_INT_ENA1 : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1 (BIT(22)) +#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1_M (SLCHOST_SLC1_EXT_BIT3_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT3_INT_ENA1_S) +#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1_S 22 +/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 (BIT(23)) +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_M (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_S) +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_S 23 +/** SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1 : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1 (BIT(24)) +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_M (SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_S) +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_S 24 +/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 (BIT(25)) +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_M (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_S) +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_S 25 + +/** SLCHOST_SLCHOSTDATE_REG register + * *******Description*********** + */ +#define SLCHOST_SLCHOSTDATE_REG (DR_REG_SLCHOST_BASE + 0x178) +/** SLCHOST_SLCHOST_DATE : R/W; bitpos: [31:0]; default: 554043136; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_DATE 0xFFFFFFFFU +#define SLCHOST_SLCHOST_DATE_M (SLCHOST_SLCHOST_DATE_V << SLCHOST_SLCHOST_DATE_S) +#define SLCHOST_SLCHOST_DATE_V 0xFFFFFFFFU +#define SLCHOST_SLCHOST_DATE_S 0 + +/** SLCHOST_SLCHOSTID_REG register + * *******Description*********** + */ +#define SLCHOST_SLCHOSTID_REG (DR_REG_SLCHOST_BASE + 0x17c) +/** SLCHOST_SLCHOST_ID : R/W; bitpos: [31:0]; default: 1536; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_ID 0xFFFFFFFFU +#define SLCHOST_SLCHOST_ID_M (SLCHOST_SLCHOST_ID_V << SLCHOST_SLCHOST_ID_S) +#define SLCHOST_SLCHOST_ID_V 0xFFFFFFFFU +#define SLCHOST_SLCHOST_ID_S 0 + +/** SLCHOST_CONF_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_REG (DR_REG_SLCHOST_BASE + 0x1f0) +/** SLCHOST_FRC_SDIO11 : R/W; bitpos: [4:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FRC_SDIO11 0x0000001FU +#define SLCHOST_FRC_SDIO11_M (SLCHOST_FRC_SDIO11_V << SLCHOST_FRC_SDIO11_S) +#define SLCHOST_FRC_SDIO11_V 0x0000001FU +#define SLCHOST_FRC_SDIO11_S 0 +/** SLCHOST_FRC_SDIO20 : R/W; bitpos: [9:5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FRC_SDIO20 0x0000001FU +#define SLCHOST_FRC_SDIO20_M (SLCHOST_FRC_SDIO20_V << SLCHOST_FRC_SDIO20_S) +#define SLCHOST_FRC_SDIO20_V 0x0000001FU +#define SLCHOST_FRC_SDIO20_S 5 +/** SLCHOST_FRC_NEG_SAMP : R/W; bitpos: [14:10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FRC_NEG_SAMP 0x0000001FU +#define SLCHOST_FRC_NEG_SAMP_M (SLCHOST_FRC_NEG_SAMP_V << SLCHOST_FRC_NEG_SAMP_S) +#define SLCHOST_FRC_NEG_SAMP_V 0x0000001FU +#define SLCHOST_FRC_NEG_SAMP_S 10 +/** SLCHOST_FRC_POS_SAMP : R/W; bitpos: [19:15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FRC_POS_SAMP 0x0000001FU +#define SLCHOST_FRC_POS_SAMP_M (SLCHOST_FRC_POS_SAMP_V << SLCHOST_FRC_POS_SAMP_S) +#define SLCHOST_FRC_POS_SAMP_V 0x0000001FU +#define SLCHOST_FRC_POS_SAMP_S 15 +/** SLCHOST_FRC_QUICK_IN : R/W; bitpos: [24:20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FRC_QUICK_IN 0x0000001FU +#define SLCHOST_FRC_QUICK_IN_M (SLCHOST_FRC_QUICK_IN_V << SLCHOST_FRC_QUICK_IN_S) +#define SLCHOST_FRC_QUICK_IN_V 0x0000001FU +#define SLCHOST_FRC_QUICK_IN_S 20 +/** SLCHOST_SDIO20_INT_DELAY : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SDIO20_INT_DELAY (BIT(25)) +#define SLCHOST_SDIO20_INT_DELAY_M (SLCHOST_SDIO20_INT_DELAY_V << SLCHOST_SDIO20_INT_DELAY_S) +#define SLCHOST_SDIO20_INT_DELAY_V 0x00000001U +#define SLCHOST_SDIO20_INT_DELAY_S 25 +/** SLCHOST_SDIO_PAD_PULLUP : R/W; bitpos: [26]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SDIO_PAD_PULLUP (BIT(26)) +#define SLCHOST_SDIO_PAD_PULLUP_M (SLCHOST_SDIO_PAD_PULLUP_V << SLCHOST_SDIO_PAD_PULLUP_S) +#define SLCHOST_SDIO_PAD_PULLUP_V 0x00000001U +#define SLCHOST_SDIO_PAD_PULLUP_S 26 +/** SLCHOST_HSPEED_CON_EN : R/W; bitpos: [27]; default: 0; + * *******Description*********** + */ +#define SLCHOST_HSPEED_CON_EN (BIT(27)) +#define SLCHOST_HSPEED_CON_EN_M (SLCHOST_HSPEED_CON_EN_V << SLCHOST_HSPEED_CON_EN_S) +#define SLCHOST_HSPEED_CON_EN_V 0x00000001U +#define SLCHOST_HSPEED_CON_EN_S 27 + +/** SLCHOST_INF_ST_REG register + * *******Description*********** + */ +#define SLCHOST_INF_ST_REG (DR_REG_SLCHOST_BASE + 0x1f4) +/** SLCHOST_SDIO20_MODE : RO; bitpos: [4:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SDIO20_MODE 0x0000001FU +#define SLCHOST_SDIO20_MODE_M (SLCHOST_SDIO20_MODE_V << SLCHOST_SDIO20_MODE_S) +#define SLCHOST_SDIO20_MODE_V 0x0000001FU +#define SLCHOST_SDIO20_MODE_S 0 +/** SLCHOST_SDIO_NEG_SAMP : RO; bitpos: [9:5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SDIO_NEG_SAMP 0x0000001FU +#define SLCHOST_SDIO_NEG_SAMP_M (SLCHOST_SDIO_NEG_SAMP_V << SLCHOST_SDIO_NEG_SAMP_S) +#define SLCHOST_SDIO_NEG_SAMP_V 0x0000001FU +#define SLCHOST_SDIO_NEG_SAMP_S 5 +/** SLCHOST_SDIO_QUICK_IN : RO; bitpos: [14:10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SDIO_QUICK_IN 0x0000001FU +#define SLCHOST_SDIO_QUICK_IN_M (SLCHOST_SDIO_QUICK_IN_V << SLCHOST_SDIO_QUICK_IN_S) +#define SLCHOST_SDIO_QUICK_IN_V 0x0000001FU +#define SLCHOST_SDIO_QUICK_IN_S 10 +/** SLCHOST_DLL_ON_SW : R/W; bitpos: [15]; default: 0; + * dll is controlled by software + */ +#define SLCHOST_DLL_ON_SW (BIT(15)) +#define SLCHOST_DLL_ON_SW_M (SLCHOST_DLL_ON_SW_V << SLCHOST_DLL_ON_SW_S) +#define SLCHOST_DLL_ON_SW_V 0x00000001U +#define SLCHOST_DLL_ON_SW_S 15 +/** SLCHOST_DLL_ON : R/W; bitpos: [16]; default: 0; + * Software dll on + */ +#define SLCHOST_DLL_ON (BIT(16)) +#define SLCHOST_DLL_ON_M (SLCHOST_DLL_ON_V << SLCHOST_DLL_ON_S) +#define SLCHOST_DLL_ON_V 0x00000001U +#define SLCHOST_DLL_ON_S 16 +/** SLCHOST_CLK_MODE_SW : R/W; bitpos: [17]; default: 0; + * dll clock mode is controlled by software + */ +#define SLCHOST_CLK_MODE_SW (BIT(17)) +#define SLCHOST_CLK_MODE_SW_M (SLCHOST_CLK_MODE_SW_V << SLCHOST_CLK_MODE_SW_S) +#define SLCHOST_CLK_MODE_SW_V 0x00000001U +#define SLCHOST_CLK_MODE_SW_S 17 +/** SLCHOST_CLK_MODE : R/W; bitpos: [19:18]; default: 0; + * Software set clock mode + */ +#define SLCHOST_CLK_MODE 0x00000003U +#define SLCHOST_CLK_MODE_M (SLCHOST_CLK_MODE_V << SLCHOST_CLK_MODE_S) +#define SLCHOST_CLK_MODE_V 0x00000003U +#define SLCHOST_CLK_MODE_S 18 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/host_struct.h b/components/soc/esp32c6/include/soc/host_struct.h new file mode 100644 index 0000000000..0462b84276 --- /dev/null +++ b/components/soc/esp32c6/include/soc/host_struct.h @@ -0,0 +1,2738 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: ********Registers */ +/** Type of func2_0 register + * *******Description*********** + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** slc_func2_int : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc_func2_int:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} slchost_func2_0_reg_t; + +/** Type of func2_1 register + * *******Description*********** + */ +typedef union { + struct { + /** slc_func2_int_en : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc_func2_int_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} slchost_func2_1_reg_t; + +/** Type of func2_2 register + * *******Description*********** + */ +typedef union { + struct { + /** slc_func1_mdstat : R/W; bitpos: [0]; default: 1; + * *******Description*********** + */ + uint32_t slc_func1_mdstat:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} slchost_func2_2_reg_t; + +/** Type of gpio_status0 register + * *******Description*********** + */ +typedef union { + struct { + /** gpio_sdio_int0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_int0:32; + }; + uint32_t val; +} slchost_gpio_status0_reg_t; + +/** Type of gpio_status1 register + * *******Description*********** + */ +typedef union { + struct { + /** gpio_sdio_int1 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_int1:32; + }; + uint32_t val; +} slchost_gpio_status1_reg_t; + +/** Type of gpio_in0 register + * *******Description*********** + */ +typedef union { + struct { + /** gpio_sdio_in0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_in0:32; + }; + uint32_t val; +} slchost_gpio_in0_reg_t; + +/** Type of gpio_in1 register + * *******Description*********** + */ +typedef union { + struct { + /** gpio_sdio_in1 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_in1:32; + }; + uint32_t val; +} slchost_gpio_in1_reg_t; + +/** Type of slc0host_token_rdata register + * *******Description*********** + */ +typedef union { + struct { + /** slc0_token0 : RO; bitpos: [11:0]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0:12; + /** slc0_rx_pf_valid : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_pf_valid:1; + uint32_t reserved_13:3; + /** hostslchost_slc0_token1 : RO; bitpos: [27:16]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_token1:12; + /** slc0_rx_pf_eof : RO; bitpos: [31:28]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_pf_eof:4; + }; + uint32_t val; +} slchost_slc0host_token_rdata_reg_t; + +/** Type of slc0_host_pf register + * *******Description*********** + */ +typedef union { + struct { + /** slc0_pf_data : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slc0_pf_data:32; + }; + uint32_t val; +} slchost_slc0_host_pf_reg_t; + +/** Type of slc1_host_pf register + * *******Description*********** + */ +typedef union { + struct { + /** slc1_pf_data : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slc1_pf_data:32; + }; + uint32_t val; +} slchost_slc1_host_pf_reg_t; + +/** Type of slc0host_int_raw register + * *******Description*********** + */ +typedef union { + struct { + /** slc0_tohost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit0_int_raw:1; + /** slc0_tohost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit1_int_raw:1; + /** slc0_tohost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit2_int_raw:1; + /** slc0_tohost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit3_int_raw:1; + /** slc0_tohost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit4_int_raw:1; + /** slc0_tohost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit5_int_raw:1; + /** slc0_tohost_bit6_int_raw : R/WTC/SS/SC; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit6_int_raw:1; + /** slc0_tohost_bit7_int_raw : R/WTC/SS/SC; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit7_int_raw:1; + /** slc0_token0_1to0_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_1to0_int_raw:1; + /** slc0_token1_1to0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_1to0_int_raw:1; + /** slc0_token0_0to1_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_0to1_int_raw:1; + /** slc0_token1_0to1_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_0to1_int_raw:1; + /** slc0host_rx_sof_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_sof_int_raw:1; + /** slc0host_rx_eof_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_eof_int_raw:1; + /** slc0host_rx_start_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_start_int_raw:1; + /** slc0host_tx_start_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_tx_start_int_raw:1; + /** slc0_rx_udf_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_udf_int_raw:1; + /** slc0_tx_ovf_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tx_ovf_int_raw:1; + /** slc0_rx_pf_valid_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_pf_valid_int_raw:1; + /** slc0_ext_bit0_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit0_int_raw:1; + /** slc0_ext_bit1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit1_int_raw:1; + /** slc0_ext_bit2_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit2_int_raw:1; + /** slc0_ext_bit3_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit3_int_raw:1; + /** slc0_rx_new_packet_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_new_packet_int_raw:1; + /** slc0_host_rd_retry_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc0_host_rd_retry_int_raw:1; + /** gpio_sdio_int_raw : R/WTC/SS/SC; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_int_raw:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc0host_int_raw_reg_t; + +/** Type of slc1host_int_raw register + * *******Description*********** + */ +typedef union { + struct { + /** slc1_tohost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit0_int_raw:1; + /** slc1_tohost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit1_int_raw:1; + /** slc1_tohost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit2_int_raw:1; + /** slc1_tohost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit3_int_raw:1; + /** slc1_tohost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit4_int_raw:1; + /** slc1_tohost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit5_int_raw:1; + /** slc1_tohost_bit6_int_raw : R/WTC/SS/SC; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit6_int_raw:1; + /** slc1_tohost_bit7_int_raw : R/WTC/SS/SC; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit7_int_raw:1; + /** slc1_token0_1to0_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_1to0_int_raw:1; + /** slc1_token1_1to0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_1to0_int_raw:1; + /** slc1_token0_0to1_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_0to1_int_raw:1; + /** slc1_token1_0to1_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_0to1_int_raw:1; + /** slc1host_rx_sof_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_sof_int_raw:1; + /** slc1host_rx_eof_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_eof_int_raw:1; + /** slc1host_rx_start_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_start_int_raw:1; + /** slc1host_tx_start_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_tx_start_int_raw:1; + /** slc1_rx_udf_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_udf_int_raw:1; + /** slc1_tx_ovf_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tx_ovf_int_raw:1; + /** slc1_rx_pf_valid_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_pf_valid_int_raw:1; + /** slc1_ext_bit0_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit0_int_raw:1; + /** slc1_ext_bit1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit1_int_raw:1; + /** slc1_ext_bit2_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit2_int_raw:1; + /** slc1_ext_bit3_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit3_int_raw:1; + /** slc1_wifi_rx_new_packet_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc1_wifi_rx_new_packet_int_raw:1; + /** slc1_host_rd_retry_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc1_host_rd_retry_int_raw:1; + /** slc1_bt_rx_new_packet_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slc1_bt_rx_new_packet_int_raw:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc1host_int_raw_reg_t; + +/** Type of slc0host_int_st register + * *******Description*********** + */ +typedef union { + struct { + /** slc0_tohost_bit0_int_st : RO; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit0_int_st:1; + /** slc0_tohost_bit1_int_st : RO; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit1_int_st:1; + /** slc0_tohost_bit2_int_st : RO; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit2_int_st:1; + /** slc0_tohost_bit3_int_st : RO; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit3_int_st:1; + /** slc0_tohost_bit4_int_st : RO; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit4_int_st:1; + /** slc0_tohost_bit5_int_st : RO; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit5_int_st:1; + /** slc0_tohost_bit6_int_st : RO; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit6_int_st:1; + /** slc0_tohost_bit7_int_st : RO; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit7_int_st:1; + /** slc0_token0_1to0_int_st : RO; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_1to0_int_st:1; + /** slc0_token1_1to0_int_st : RO; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_1to0_int_st:1; + /** slc0_token0_0to1_int_st : RO; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_0to1_int_st:1; + /** slc0_token1_0to1_int_st : RO; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_0to1_int_st:1; + /** slc0host_rx_sof_int_st : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_sof_int_st:1; + /** slc0host_rx_eof_int_st : RO; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_eof_int_st:1; + /** slc0host_rx_start_int_st : RO; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_start_int_st:1; + /** slc0host_tx_start_int_st : RO; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_tx_start_int_st:1; + /** slc0_rx_udf_int_st : RO; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_udf_int_st:1; + /** slc0_tx_ovf_int_st : RO; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tx_ovf_int_st:1; + /** slc0_rx_pf_valid_int_st : RO; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_pf_valid_int_st:1; + /** slc0_ext_bit0_int_st : RO; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit0_int_st:1; + /** slc0_ext_bit1_int_st : RO; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit1_int_st:1; + /** slc0_ext_bit2_int_st : RO; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit2_int_st:1; + /** slc0_ext_bit3_int_st : RO; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit3_int_st:1; + /** slc0_rx_new_packet_int_st : RO; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_new_packet_int_st:1; + /** slc0_host_rd_retry_int_st : RO; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc0_host_rd_retry_int_st:1; + /** gpio_sdio_int_st : RO; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_int_st:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc0host_int_st_reg_t; + +/** Type of slc1host_int_st register + * *******Description*********** + */ +typedef union { + struct { + /** slc1_tohost_bit0_int_st : RO; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit0_int_st:1; + /** slc1_tohost_bit1_int_st : RO; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit1_int_st:1; + /** slc1_tohost_bit2_int_st : RO; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit2_int_st:1; + /** slc1_tohost_bit3_int_st : RO; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit3_int_st:1; + /** slc1_tohost_bit4_int_st : RO; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit4_int_st:1; + /** slc1_tohost_bit5_int_st : RO; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit5_int_st:1; + /** slc1_tohost_bit6_int_st : RO; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit6_int_st:1; + /** slc1_tohost_bit7_int_st : RO; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit7_int_st:1; + /** slc1_token0_1to0_int_st : RO; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_1to0_int_st:1; + /** slc1_token1_1to0_int_st : RO; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_1to0_int_st:1; + /** slc1_token0_0to1_int_st : RO; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_0to1_int_st:1; + /** slc1_token1_0to1_int_st : RO; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_0to1_int_st:1; + /** slc1host_rx_sof_int_st : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_sof_int_st:1; + /** slc1host_rx_eof_int_st : RO; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_eof_int_st:1; + /** slc1host_rx_start_int_st : RO; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_start_int_st:1; + /** slc1host_tx_start_int_st : RO; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_tx_start_int_st:1; + /** slc1_rx_udf_int_st : RO; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_udf_int_st:1; + /** slc1_tx_ovf_int_st : RO; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tx_ovf_int_st:1; + /** slc1_rx_pf_valid_int_st : RO; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_pf_valid_int_st:1; + /** slc1_ext_bit0_int_st : RO; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit0_int_st:1; + /** slc1_ext_bit1_int_st : RO; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit1_int_st:1; + /** slc1_ext_bit2_int_st : RO; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit2_int_st:1; + /** slc1_ext_bit3_int_st : RO; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit3_int_st:1; + /** slc1_wifi_rx_new_packet_int_st : RO; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc1_wifi_rx_new_packet_int_st:1; + /** slc1_host_rd_retry_int_st : RO; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc1_host_rd_retry_int_st:1; + /** slc1_bt_rx_new_packet_int_st : RO; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slc1_bt_rx_new_packet_int_st:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc1host_int_st_reg_t; + +/** Type of pkt_len register + * *******Description*********** + */ +typedef union { + struct { + /** hostslchost_slc0_len : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len:20; + /** hostslchost_slc0_len_check : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len_check:12; + }; + uint32_t val; +} slchost_pkt_len_reg_t; + +/** Type of state_w0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_state0 : RO; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state0:8; + /** slchost_state1 : RO; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state1:8; + /** slchost_state2 : RO; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state2:8; + /** slchost_state3 : RO; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state3:8; + }; + uint32_t val; +} slchost_state_w0_reg_t; + +/** Type of state_w1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_state4 : RO; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state4:8; + /** slchost_state5 : RO; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state5:8; + /** slchost_state6 : RO; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state6:8; + /** slchost_state7 : RO; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state7:8; + }; + uint32_t val; +} slchost_state_w1_reg_t; + +/** Type of conf_w0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf0 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf0:8; + /** slchost_conf1 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf1:8; + /** slchost_conf2 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf2:8; + /** slchost_conf3 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf3:8; + }; + uint32_t val; +} slchost_conf_w0_reg_t; + +/** Type of conf_w1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf4 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf4:8; + /** slchost_conf5 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf5:8; + /** slchost_conf6 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf6:8; + /** slchost_conf7 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf7:8; + }; + uint32_t val; +} slchost_conf_w1_reg_t; + +/** Type of conf_w2 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf8 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf8:8; + /** slchost_conf9 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf9:8; + /** slchost_conf10 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf10:8; + /** slchost_conf11 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf11:8; + }; + uint32_t val; +} slchost_conf_w2_reg_t; + +/** Type of conf_w3 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf12 : R/W; bitpos: [7:0]; default: 192; + * *******Description*********** + */ + uint32_t slchost_conf12:8; + /** slchost_conf13 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf13:8; + /** slchost_conf14 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf14:8; + /** slchost_conf15 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf15:8; + }; + uint32_t val; +} slchost_conf_w3_reg_t; + +/** Type of conf_w4 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf16 : R/W; bitpos: [7:0]; default: 255; + * *******Description*********** + */ + uint32_t slchost_conf16:8; + /** slchost_conf17 : R/W; bitpos: [15:8]; default: 1; + * *******Description*********** + */ + uint32_t slchost_conf17:8; + /** slchost_conf18 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf18:8; + /** slchost_conf19 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf19:8; + }; + uint32_t val; +} slchost_conf_w4_reg_t; + +/** Type of conf_w5 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf20 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf20:8; + /** slchost_conf21 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf21:8; + /** slchost_conf22 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf22:8; + /** slchost_conf23 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf23:8; + }; + uint32_t val; +} slchost_conf_w5_reg_t; + +/** Type of win_cmd register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_win_cmd : R/W; bitpos: [15:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_win_cmd:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} slchost_win_cmd_reg_t; + +/** Type of conf_w6 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf24 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf24:8; + /** slchost_conf25 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf25:8; + /** slchost_conf26 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf26:8; + /** slchost_conf27 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf27:8; + }; + uint32_t val; +} slchost_conf_w6_reg_t; + +/** Type of conf_w7 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf28 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf28:8; + /** slchost_conf29 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf29:8; + /** slchost_conf30 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf30:8; + /** slchost_conf31 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf31:8; + }; + uint32_t val; +} slchost_conf_w7_reg_t; + +/** Type of pkt_len0 register + * *******Description*********** + */ +typedef union { + struct { + /** hostslchost_slc0_len0 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len0:20; + /** hostslchost_slc0_len0_check : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len0_check:12; + }; + uint32_t val; +} slchost_pkt_len0_reg_t; + +/** Type of pkt_len1 register + * *******Description*********** + */ +typedef union { + struct { + /** hostslchost_slc0_len1 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len1:20; + /** hostslchost_slc0_len1_check : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len1_check:12; + }; + uint32_t val; +} slchost_pkt_len1_reg_t; + +/** Type of pkt_len2 register + * *******Description*********** + */ +typedef union { + struct { + /** hostslchost_slc0_len2 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len2:20; + /** hostslchost_slc0_len2_check : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len2_check:12; + }; + uint32_t val; +} slchost_pkt_len2_reg_t; + +/** Type of conf_w8 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf32 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf32:8; + /** slchost_conf33 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf33:8; + /** slchost_conf34 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf34:8; + /** slchost_conf35 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf35:8; + }; + uint32_t val; +} slchost_conf_w8_reg_t; + +/** Type of conf_w9 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf36 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf36:8; + /** slchost_conf37 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf37:8; + /** slchost_conf38 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf38:8; + /** slchost_conf39 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf39:8; + }; + uint32_t val; +} slchost_conf_w9_reg_t; + +/** Type of conf_w10 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf40 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf40:8; + /** slchost_conf41 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf41:8; + /** slchost_conf42 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf42:8; + /** slchost_conf43 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf43:8; + }; + uint32_t val; +} slchost_conf_w10_reg_t; + +/** Type of conf_w11 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf44 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf44:8; + /** slchost_conf45 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf45:8; + /** slchost_conf46 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf46:8; + /** slchost_conf47 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf47:8; + }; + uint32_t val; +} slchost_conf_w11_reg_t; + +/** Type of conf_w12 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf48 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf48:8; + /** slchost_conf49 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf49:8; + /** slchost_conf50 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf50:8; + /** slchost_conf51 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf51:8; + }; + uint32_t val; +} slchost_conf_w12_reg_t; + +/** Type of conf_w13 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf52 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf52:8; + /** slchost_conf53 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf53:8; + /** slchost_conf54 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf54:8; + /** slchost_conf55 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf55:8; + }; + uint32_t val; +} slchost_conf_w13_reg_t; + +/** Type of conf_w14 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf56 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf56:8; + /** slchost_conf57 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf57:8; + /** slchost_conf58 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf58:8; + /** slchost_conf59 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf59:8; + }; + uint32_t val; +} slchost_conf_w14_reg_t; + +/** Type of conf_w15 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf60 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf60:8; + /** slchost_conf61 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf61:8; + /** slchost_conf62 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf62:8; + /** slchost_conf63 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf63:8; + }; + uint32_t val; +} slchost_conf_w15_reg_t; + +/** Type of check_sum0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_check_sum0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_check_sum0:32; + }; + uint32_t val; +} slchost_check_sum0_reg_t; + +/** Type of check_sum1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_check_sum1 : RO; bitpos: [31:0]; default: 319; + * *******Description*********** + */ + uint32_t slchost_check_sum1:32; + }; + uint32_t val; +} slchost_check_sum1_reg_t; + +/** Type of slc1host_token_rdata register + * *******Description*********** + */ +typedef union { + struct { + /** slc1_token0 : RO; bitpos: [11:0]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0:12; + /** slc1_rx_pf_valid : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_pf_valid:1; + uint32_t reserved_13:3; + /** hostslchost_slc1_token1 : RO; bitpos: [27:16]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc1_token1:12; + /** slc1_rx_pf_eof : RO; bitpos: [31:28]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_pf_eof:4; + }; + uint32_t val; +} slchost_slc1host_token_rdata_reg_t; + +/** Type of slc0host_token_wdata register + * *******Description*********** + */ +typedef union { + struct { + /** slc0host_token0_wd : R/W; bitpos: [11:0]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_token0_wd:12; + uint32_t reserved_12:4; + /** slc0host_token1_wd : R/W; bitpos: [27:16]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_token1_wd:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} slchost_slc0host_token_wdata_reg_t; + +/** Type of slc1host_token_wdata register + * *******Description*********** + */ +typedef union { + struct { + /** slc1host_token0_wd : R/W; bitpos: [11:0]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_token0_wd:12; + uint32_t reserved_12:4; + /** slc1host_token1_wd : R/W; bitpos: [27:16]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_token1_wd:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} slchost_slc1host_token_wdata_reg_t; + +/** Type of token_con register + * *******Description*********** + */ +typedef union { + struct { + /** slc0host_token0_dec : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_token0_dec:1; + /** slc0host_token1_dec : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_token1_dec:1; + /** slc0host_token0_wr : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_token0_wr:1; + /** slc0host_token1_wr : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_token1_wr:1; + /** slc1host_token0_dec : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_token0_dec:1; + /** slc1host_token1_dec : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_token1_dec:1; + /** slc1host_token0_wr : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_token0_wr:1; + /** slc1host_token1_wr : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_token1_wr:1; + /** slc0host_len_wr : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_len_wr:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} slchost_token_con_reg_t; + +/** Type of slc0host_int_clr register + * *******Description*********** + */ +typedef union { + struct { + /** slc0_tohost_bit0_int_clr : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit0_int_clr:1; + /** slc0_tohost_bit1_int_clr : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit1_int_clr:1; + /** slc0_tohost_bit2_int_clr : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit2_int_clr:1; + /** slc0_tohost_bit3_int_clr : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit3_int_clr:1; + /** slc0_tohost_bit4_int_clr : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit4_int_clr:1; + /** slc0_tohost_bit5_int_clr : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit5_int_clr:1; + /** slc0_tohost_bit6_int_clr : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit6_int_clr:1; + /** slc0_tohost_bit7_int_clr : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit7_int_clr:1; + /** slc0_token0_1to0_int_clr : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_1to0_int_clr:1; + /** slc0_token1_1to0_int_clr : WT; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_1to0_int_clr:1; + /** slc0_token0_0to1_int_clr : WT; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_0to1_int_clr:1; + /** slc0_token1_0to1_int_clr : WT; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_0to1_int_clr:1; + /** slc0host_rx_sof_int_clr : WT; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_sof_int_clr:1; + /** slc0host_rx_eof_int_clr : WT; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_eof_int_clr:1; + /** slc0host_rx_start_int_clr : WT; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_start_int_clr:1; + /** slc0host_tx_start_int_clr : WT; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_tx_start_int_clr:1; + /** slc0_rx_udf_int_clr : WT; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_udf_int_clr:1; + /** slc0_tx_ovf_int_clr : WT; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tx_ovf_int_clr:1; + /** slc0_rx_pf_valid_int_clr : WT; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_pf_valid_int_clr:1; + /** slc0_ext_bit0_int_clr : WT; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit0_int_clr:1; + /** slc0_ext_bit1_int_clr : WT; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit1_int_clr:1; + /** slc0_ext_bit2_int_clr : WT; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit2_int_clr:1; + /** slc0_ext_bit3_int_clr : WT; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit3_int_clr:1; + /** slc0_rx_new_packet_int_clr : WT; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_new_packet_int_clr:1; + /** slc0_host_rd_retry_int_clr : WT; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc0_host_rd_retry_int_clr:1; + /** gpio_sdio_int_clr : WT; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_int_clr:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc0host_int_clr_reg_t; + +/** Type of slc1host_int_clr register + * *******Description*********** + */ +typedef union { + struct { + /** slc1_tohost_bit0_int_clr : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit0_int_clr:1; + /** slc1_tohost_bit1_int_clr : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit1_int_clr:1; + /** slc1_tohost_bit2_int_clr : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit2_int_clr:1; + /** slc1_tohost_bit3_int_clr : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit3_int_clr:1; + /** slc1_tohost_bit4_int_clr : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit4_int_clr:1; + /** slc1_tohost_bit5_int_clr : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit5_int_clr:1; + /** slc1_tohost_bit6_int_clr : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit6_int_clr:1; + /** slc1_tohost_bit7_int_clr : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit7_int_clr:1; + /** slc1_token0_1to0_int_clr : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_1to0_int_clr:1; + /** slc1_token1_1to0_int_clr : WT; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_1to0_int_clr:1; + /** slc1_token0_0to1_int_clr : WT; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_0to1_int_clr:1; + /** slc1_token1_0to1_int_clr : WT; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_0to1_int_clr:1; + /** slc1host_rx_sof_int_clr : WT; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_sof_int_clr:1; + /** slc1host_rx_eof_int_clr : WT; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_eof_int_clr:1; + /** slc1host_rx_start_int_clr : WT; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_start_int_clr:1; + /** slc1host_tx_start_int_clr : WT; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_tx_start_int_clr:1; + /** slc1_rx_udf_int_clr : WT; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_udf_int_clr:1; + /** slc1_tx_ovf_int_clr : WT; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tx_ovf_int_clr:1; + /** slc1_rx_pf_valid_int_clr : WT; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_pf_valid_int_clr:1; + /** slc1_ext_bit0_int_clr : WT; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit0_int_clr:1; + /** slc1_ext_bit1_int_clr : WT; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit1_int_clr:1; + /** slc1_ext_bit2_int_clr : WT; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit2_int_clr:1; + /** slc1_ext_bit3_int_clr : WT; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit3_int_clr:1; + /** slc1_wifi_rx_new_packet_int_clr : WT; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc1_wifi_rx_new_packet_int_clr:1; + /** slc1_host_rd_retry_int_clr : WT; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc1_host_rd_retry_int_clr:1; + /** slc1_bt_rx_new_packet_int_clr : WT; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slc1_bt_rx_new_packet_int_clr:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc1host_int_clr_reg_t; + +/** Type of slc0host_func1_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** fn1_slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit0_int_ena:1; + /** fn1_slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit1_int_ena:1; + /** fn1_slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit2_int_ena:1; + /** fn1_slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit3_int_ena:1; + /** fn1_slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit4_int_ena:1; + /** fn1_slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit5_int_ena:1; + /** fn1_slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit6_int_ena:1; + /** fn1_slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit7_int_ena:1; + /** fn1_slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_token0_1to0_int_ena:1; + /** fn1_slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_token1_1to0_int_ena:1; + /** fn1_slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_token0_0to1_int_ena:1; + /** fn1_slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_token1_0to1_int_ena:1; + /** fn1_slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0host_rx_sof_int_ena:1; + /** fn1_slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0host_rx_eof_int_ena:1; + /** fn1_slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0host_rx_start_int_ena:1; + /** fn1_slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0host_tx_start_int_ena:1; + /** fn1_slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_rx_udf_int_ena:1; + /** fn1_slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tx_ovf_int_ena:1; + /** fn1_slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_rx_pf_valid_int_ena:1; + /** fn1_slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_ext_bit0_int_ena:1; + /** fn1_slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_ext_bit1_int_ena:1; + /** fn1_slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_ext_bit2_int_ena:1; + /** fn1_slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_ext_bit3_int_ena:1; + /** fn1_slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_rx_new_packet_int_ena:1; + /** fn1_slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_host_rd_retry_int_ena:1; + /** fn1_gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t fn1_gpio_sdio_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc0host_func1_int_ena_reg_t; + +/** Type of slc1host_func1_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** fn1_slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit0_int_ena:1; + /** fn1_slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit1_int_ena:1; + /** fn1_slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit2_int_ena:1; + /** fn1_slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit3_int_ena:1; + /** fn1_slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit4_int_ena:1; + /** fn1_slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit5_int_ena:1; + /** fn1_slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit6_int_ena:1; + /** fn1_slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit7_int_ena:1; + /** fn1_slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_token0_1to0_int_ena:1; + /** fn1_slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_token1_1to0_int_ena:1; + /** fn1_slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_token0_0to1_int_ena:1; + /** fn1_slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_token1_0to1_int_ena:1; + /** fn1_slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1host_rx_sof_int_ena:1; + /** fn1_slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1host_rx_eof_int_ena:1; + /** fn1_slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1host_rx_start_int_ena:1; + /** fn1_slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1host_tx_start_int_ena:1; + /** fn1_slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_rx_udf_int_ena:1; + /** fn1_slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tx_ovf_int_ena:1; + /** fn1_slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_rx_pf_valid_int_ena:1; + /** fn1_slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_ext_bit0_int_ena:1; + /** fn1_slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_ext_bit1_int_ena:1; + /** fn1_slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_ext_bit2_int_ena:1; + /** fn1_slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_ext_bit3_int_ena:1; + /** fn1_slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_wifi_rx_new_packet_int_ena:1; + /** fn1_slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_host_rd_retry_int_ena:1; + /** fn1_slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_bt_rx_new_packet_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc1host_func1_int_ena_reg_t; + +/** Type of slc0host_func2_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** fn2_slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit0_int_ena:1; + /** fn2_slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit1_int_ena:1; + /** fn2_slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit2_int_ena:1; + /** fn2_slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit3_int_ena:1; + /** fn2_slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit4_int_ena:1; + /** fn2_slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit5_int_ena:1; + /** fn2_slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit6_int_ena:1; + /** fn2_slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit7_int_ena:1; + /** fn2_slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_token0_1to0_int_ena:1; + /** fn2_slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_token1_1to0_int_ena:1; + /** fn2_slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_token0_0to1_int_ena:1; + /** fn2_slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_token1_0to1_int_ena:1; + /** fn2_slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0host_rx_sof_int_ena:1; + /** fn2_slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0host_rx_eof_int_ena:1; + /** fn2_slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0host_rx_start_int_ena:1; + /** fn2_slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0host_tx_start_int_ena:1; + /** fn2_slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_rx_udf_int_ena:1; + /** fn2_slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tx_ovf_int_ena:1; + /** fn2_slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_rx_pf_valid_int_ena:1; + /** fn2_slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_ext_bit0_int_ena:1; + /** fn2_slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_ext_bit1_int_ena:1; + /** fn2_slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_ext_bit2_int_ena:1; + /** fn2_slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_ext_bit3_int_ena:1; + /** fn2_slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_rx_new_packet_int_ena:1; + /** fn2_slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_host_rd_retry_int_ena:1; + /** fn2_gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t fn2_gpio_sdio_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc0host_func2_int_ena_reg_t; + +/** Type of slc1host_func2_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** fn2_slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit0_int_ena:1; + /** fn2_slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit1_int_ena:1; + /** fn2_slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit2_int_ena:1; + /** fn2_slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit3_int_ena:1; + /** fn2_slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit4_int_ena:1; + /** fn2_slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit5_int_ena:1; + /** fn2_slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit6_int_ena:1; + /** fn2_slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit7_int_ena:1; + /** fn2_slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_token0_1to0_int_ena:1; + /** fn2_slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_token1_1to0_int_ena:1; + /** fn2_slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_token0_0to1_int_ena:1; + /** fn2_slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_token1_0to1_int_ena:1; + /** fn2_slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1host_rx_sof_int_ena:1; + /** fn2_slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1host_rx_eof_int_ena:1; + /** fn2_slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1host_rx_start_int_ena:1; + /** fn2_slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1host_tx_start_int_ena:1; + /** fn2_slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_rx_udf_int_ena:1; + /** fn2_slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tx_ovf_int_ena:1; + /** fn2_slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_rx_pf_valid_int_ena:1; + /** fn2_slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_ext_bit0_int_ena:1; + /** fn2_slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_ext_bit1_int_ena:1; + /** fn2_slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_ext_bit2_int_ena:1; + /** fn2_slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_ext_bit3_int_ena:1; + /** fn2_slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_wifi_rx_new_packet_int_ena:1; + /** fn2_slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_host_rd_retry_int_ena:1; + /** fn2_slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_bt_rx_new_packet_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc1host_func2_int_ena_reg_t; + +/** Type of slc0host_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit0_int_ena:1; + /** slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit1_int_ena:1; + /** slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit2_int_ena:1; + /** slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit3_int_ena:1; + /** slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit4_int_ena:1; + /** slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit5_int_ena:1; + /** slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit6_int_ena:1; + /** slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit7_int_ena:1; + /** slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_1to0_int_ena:1; + /** slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_1to0_int_ena:1; + /** slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_0to1_int_ena:1; + /** slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_0to1_int_ena:1; + /** slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_sof_int_ena:1; + /** slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_eof_int_ena:1; + /** slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_start_int_ena:1; + /** slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_tx_start_int_ena:1; + /** slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_udf_int_ena:1; + /** slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tx_ovf_int_ena:1; + /** slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_pf_valid_int_ena:1; + /** slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit0_int_ena:1; + /** slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit1_int_ena:1; + /** slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit2_int_ena:1; + /** slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit3_int_ena:1; + /** slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_new_packet_int_ena:1; + /** slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc0_host_rd_retry_int_ena:1; + /** gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc0host_int_ena_reg_t; + +/** Type of slc1host_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit0_int_ena:1; + /** slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit1_int_ena:1; + /** slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit2_int_ena:1; + /** slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit3_int_ena:1; + /** slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit4_int_ena:1; + /** slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit5_int_ena:1; + /** slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit6_int_ena:1; + /** slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit7_int_ena:1; + /** slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_1to0_int_ena:1; + /** slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_1to0_int_ena:1; + /** slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_0to1_int_ena:1; + /** slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_0to1_int_ena:1; + /** slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_sof_int_ena:1; + /** slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_eof_int_ena:1; + /** slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_start_int_ena:1; + /** slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_tx_start_int_ena:1; + /** slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_udf_int_ena:1; + /** slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tx_ovf_int_ena:1; + /** slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_pf_valid_int_ena:1; + /** slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit0_int_ena:1; + /** slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit1_int_ena:1; + /** slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit2_int_ena:1; + /** slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit3_int_ena:1; + /** slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc1_wifi_rx_new_packet_int_ena:1; + /** slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc1_host_rd_retry_int_ena:1; + /** slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slc1_bt_rx_new_packet_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc1host_int_ena_reg_t; + +/** Type of slc0host_rx_infor register + * *******Description*********** + */ +typedef union { + struct { + /** slc0host_rx_infor : R/W; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_infor:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} slchost_slc0host_rx_infor_reg_t; + +/** Type of slc1host_rx_infor register + * *******Description*********** + */ +typedef union { + struct { + /** slc1host_rx_infor : R/W; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_infor:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} slchost_slc1host_rx_infor_reg_t; + +/** Type of slc0host_len_wd register + * *******Description*********** + */ +typedef union { + struct { + /** slc0host_len_wd : R/W; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_len_wd:32; + }; + uint32_t val; +} slchost_slc0host_len_wd_reg_t; + +/** Type of slc_apbwin_wdata register + * *******Description*********** + */ +typedef union { + struct { + /** slc_apbwin_wdata : R/W; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slc_apbwin_wdata:32; + }; + uint32_t val; +} slchost_slc_apbwin_wdata_reg_t; + +/** Type of slc_apbwin_conf register + * *******Description*********** + */ +typedef union { + struct { + /** slc_apbwin_addr : R/W; bitpos: [27:0]; default: 0; + * *******Description*********** + */ + uint32_t slc_apbwin_addr:28; + /** slc_apbwin_wr : R/W; bitpos: [28]; default: 0; + * *******Description*********** + */ + uint32_t slc_apbwin_wr:1; + /** slc_apbwin_start : R/W/SC; bitpos: [29]; default: 0; + * *******Description*********** + */ + uint32_t slc_apbwin_start:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} slchost_slc_apbwin_conf_reg_t; + +/** Type of slc_apbwin_rdata register + * *******Description*********** + */ +typedef union { + struct { + /** slc_apbwin_rdata : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slc_apbwin_rdata:32; + }; + uint32_t val; +} slchost_slc_apbwin_rdata_reg_t; + +/** Type of rdclr0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0_bit7_clraddr : R/W; bitpos: [8:0]; default: 68; + * *******Description*********** + */ + uint32_t slchost_slc0_bit7_clraddr:9; + /** slchost_slc0_bit6_clraddr : R/W; bitpos: [17:9]; default: 480; + * *******Description*********** + */ + uint32_t slchost_slc0_bit6_clraddr:9; + uint32_t reserved_18:14; + }; + uint32_t val; +} slchost_rdclr0_reg_t; + +/** Type of rdclr1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc1_bit7_clraddr : R/W; bitpos: [8:0]; default: 480; + * *******Description*********** + */ + uint32_t slchost_slc1_bit7_clraddr:9; + /** slchost_slc1_bit6_clraddr : R/W; bitpos: [17:9]; default: 480; + * *******Description*********** + */ + uint32_t slchost_slc1_bit6_clraddr:9; + uint32_t reserved_18:14; + }; + uint32_t val; +} slchost_rdclr1_reg_t; + +/** Type of slc0host_int_ena1 register + * *******Description*********** + */ +typedef union { + struct { + /** slc0_tohost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit0_int_ena1:1; + /** slc0_tohost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit1_int_ena1:1; + /** slc0_tohost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit2_int_ena1:1; + /** slc0_tohost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit3_int_ena1:1; + /** slc0_tohost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit4_int_ena1:1; + /** slc0_tohost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit5_int_ena1:1; + /** slc0_tohost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit6_int_ena1:1; + /** slc0_tohost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit7_int_ena1:1; + /** slc0_token0_1to0_int_ena1 : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_1to0_int_ena1:1; + /** slc0_token1_1to0_int_ena1 : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_1to0_int_ena1:1; + /** slc0_token0_0to1_int_ena1 : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_0to1_int_ena1:1; + /** slc0_token1_0to1_int_ena1 : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_0to1_int_ena1:1; + /** slc0host_rx_sof_int_ena1 : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_sof_int_ena1:1; + /** slc0host_rx_eof_int_ena1 : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_eof_int_ena1:1; + /** slc0host_rx_start_int_ena1 : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_start_int_ena1:1; + /** slc0host_tx_start_int_ena1 : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_tx_start_int_ena1:1; + /** slc0_rx_udf_int_ena1 : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_udf_int_ena1:1; + /** slc0_tx_ovf_int_ena1 : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tx_ovf_int_ena1:1; + /** slc0_rx_pf_valid_int_ena1 : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_pf_valid_int_ena1:1; + /** slc0_ext_bit0_int_ena1 : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit0_int_ena1:1; + /** slc0_ext_bit1_int_ena1 : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit1_int_ena1:1; + /** slc0_ext_bit2_int_ena1 : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit2_int_ena1:1; + /** slc0_ext_bit3_int_ena1 : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit3_int_ena1:1; + /** slc0_rx_new_packet_int_ena1 : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_new_packet_int_ena1:1; + /** slc0_host_rd_retry_int_ena1 : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc0_host_rd_retry_int_ena1:1; + /** gpio_sdio_int_ena1 : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_int_ena1:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc0host_int_ena1_reg_t; + +/** Type of slc1host_int_ena1 register + * *******Description*********** + */ +typedef union { + struct { + /** slc1_tohost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit0_int_ena1:1; + /** slc1_tohost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit1_int_ena1:1; + /** slc1_tohost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit2_int_ena1:1; + /** slc1_tohost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit3_int_ena1:1; + /** slc1_tohost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit4_int_ena1:1; + /** slc1_tohost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit5_int_ena1:1; + /** slc1_tohost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit6_int_ena1:1; + /** slc1_tohost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit7_int_ena1:1; + /** slc1_token0_1to0_int_ena1 : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_1to0_int_ena1:1; + /** slc1_token1_1to0_int_ena1 : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_1to0_int_ena1:1; + /** slc1_token0_0to1_int_ena1 : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_0to1_int_ena1:1; + /** slc1_token1_0to1_int_ena1 : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_0to1_int_ena1:1; + /** slc1host_rx_sof_int_ena1 : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_sof_int_ena1:1; + /** slc1host_rx_eof_int_ena1 : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_eof_int_ena1:1; + /** slc1host_rx_start_int_ena1 : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_start_int_ena1:1; + /** slc1host_tx_start_int_ena1 : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_tx_start_int_ena1:1; + /** slc1_rx_udf_int_ena1 : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_udf_int_ena1:1; + /** slc1_tx_ovf_int_ena1 : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tx_ovf_int_ena1:1; + /** slc1_rx_pf_valid_int_ena1 : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_pf_valid_int_ena1:1; + /** slc1_ext_bit0_int_ena1 : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit0_int_ena1:1; + /** slc1_ext_bit1_int_ena1 : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit1_int_ena1:1; + /** slc1_ext_bit2_int_ena1 : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit2_int_ena1:1; + /** slc1_ext_bit3_int_ena1 : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit3_int_ena1:1; + /** slc1_wifi_rx_new_packet_int_ena1 : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc1_wifi_rx_new_packet_int_ena1:1; + /** slc1_host_rd_retry_int_ena1 : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc1_host_rd_retry_int_ena1:1; + /** slc1_bt_rx_new_packet_int_ena1 : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slc1_bt_rx_new_packet_int_ena1:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc1host_int_ena1_reg_t; + +/** Type of slchostdate register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_date : R/W; bitpos: [31:0]; default: 554043136; + * *******Description*********** + */ + uint32_t slchost_date:32; + }; + uint32_t val; +} slchost_slchostdate_reg_t; + +/** Type of slchostid register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_id : R/W; bitpos: [31:0]; default: 1536; + * *******Description*********** + */ + uint32_t slchost_id:32; + }; + uint32_t val; +} slchost_slchostid_reg_t; + +/** Type of conf register + * *******Description*********** + */ +typedef union { + struct { + /** frc_sdio11 : R/W; bitpos: [4:0]; default: 0; + * *******Description*********** + */ + uint32_t frc_sdio11:5; + /** frc_sdio20 : R/W; bitpos: [9:5]; default: 0; + * *******Description*********** + */ + uint32_t frc_sdio20:5; + /** frc_neg_samp : R/W; bitpos: [14:10]; default: 0; + * *******Description*********** + */ + uint32_t frc_neg_samp:5; + /** frc_pos_samp : R/W; bitpos: [19:15]; default: 0; + * *******Description*********** + */ + uint32_t frc_pos_samp:5; + /** frc_quick_in : R/W; bitpos: [24:20]; default: 0; + * *******Description*********** + */ + uint32_t frc_quick_in:5; + /** sdio20_int_delay : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t sdio20_int_delay:1; + /** sdio_pad_pullup : R/W; bitpos: [26]; default: 0; + * *******Description*********** + */ + uint32_t sdio_pad_pullup:1; + /** hspeed_con_en : R/W; bitpos: [27]; default: 0; + * *******Description*********** + */ + uint32_t hspeed_con_en:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} slchost_conf_reg_t; + +/** Type of inf_st register + * *******Description*********** + */ +typedef union { + struct { + /** sdio20_mode : RO; bitpos: [4:0]; default: 0; + * *******Description*********** + */ + uint32_t sdio20_mode:5; + /** sdio_neg_samp : RO; bitpos: [9:5]; default: 0; + * *******Description*********** + */ + uint32_t sdio_neg_samp:5; + /** sdio_quick_in : RO; bitpos: [14:10]; default: 0; + * *******Description*********** + */ + uint32_t sdio_quick_in:5; + /** dll_on_sw : R/W; bitpos: [15]; default: 0; + * dll is controlled by software + */ + uint32_t dll_on_sw:1; + /** dll_on : R/W; bitpos: [16]; default: 0; + * Software dll on + */ + uint32_t dll_on:1; + /** clk_mode_sw : R/W; bitpos: [17]; default: 0; + * dll clock mode is controlled by software + */ + uint32_t clk_mode_sw:1; + /** clk_mode : R/W; bitpos: [19:18]; default: 0; + * Software set clock mode + */ + uint32_t clk_mode:2; + uint32_t reserved_20:12; + }; + uint32_t val; +} slchost_inf_st_reg_t; + + +typedef struct slchost_dev_t { + uint32_t reserved_000[4]; + volatile slchost_func2_0_reg_t func2_0; + volatile slchost_func2_1_reg_t func2_1; + uint32_t reserved_018[2]; + volatile slchost_func2_2_reg_t func2_2; + uint32_t reserved_024[4]; + volatile slchost_gpio_status0_reg_t gpio_status0; + volatile slchost_gpio_status1_reg_t gpio_status1; + volatile slchost_gpio_in0_reg_t gpio_in0; + volatile slchost_gpio_in1_reg_t gpio_in1; + volatile slchost_slc0host_token_rdata_reg_t slc0host_token_rdata; + volatile slchost_slc0_host_pf_reg_t slc0_host_pf; + volatile slchost_slc1_host_pf_reg_t slc1_host_pf; + volatile slchost_slc0host_int_raw_reg_t slc0host_int_raw; + volatile slchost_slc1host_int_raw_reg_t slc1host_int_raw; + volatile slchost_slc0host_int_st_reg_t slc0host_int_st; + volatile slchost_slc1host_int_st_reg_t slc1host_int_st; + volatile slchost_pkt_len_reg_t pkt_len; + volatile slchost_state_w0_reg_t state_w0; + volatile slchost_state_w1_reg_t state_w1; + volatile slchost_conf_w0_reg_t conf_w0; + volatile slchost_conf_w1_reg_t conf_w1; + volatile slchost_conf_w2_reg_t conf_w2; + volatile slchost_conf_w3_reg_t conf_w3; + volatile slchost_conf_w4_reg_t conf_w4; + volatile slchost_conf_w5_reg_t conf_w5; + volatile slchost_win_cmd_reg_t win_cmd; + volatile slchost_conf_w6_reg_t conf_w6; + volatile slchost_conf_w7_reg_t conf_w7; + volatile slchost_pkt_len0_reg_t pkt_len0; + volatile slchost_pkt_len1_reg_t pkt_len1; + volatile slchost_pkt_len2_reg_t pkt_len2; + volatile slchost_conf_w8_reg_t conf_w8; + volatile slchost_conf_w9_reg_t conf_w9; + volatile slchost_conf_w10_reg_t conf_w10; + volatile slchost_conf_w11_reg_t conf_w11; + volatile slchost_conf_w12_reg_t conf_w12; + volatile slchost_conf_w13_reg_t conf_w13; + volatile slchost_conf_w14_reg_t conf_w14; + volatile slchost_conf_w15_reg_t conf_w15; + volatile slchost_check_sum0_reg_t check_sum0; + volatile slchost_check_sum1_reg_t check_sum1; + volatile slchost_slc1host_token_rdata_reg_t slc1host_token_rdata; + volatile slchost_slc0host_token_wdata_reg_t slc0host_token_wdata; + volatile slchost_slc1host_token_wdata_reg_t slc1host_token_wdata; + volatile slchost_token_con_reg_t token_con; + volatile slchost_slc0host_int_clr_reg_t slc0host_int_clr; + volatile slchost_slc1host_int_clr_reg_t slc1host_int_clr; + volatile slchost_slc0host_func1_int_ena_reg_t slc0host_func1_int_ena; + volatile slchost_slc1host_func1_int_ena_reg_t slc1host_func1_int_ena; + volatile slchost_slc0host_func2_int_ena_reg_t slc0host_func2_int_ena; + volatile slchost_slc1host_func2_int_ena_reg_t slc1host_func2_int_ena; + volatile slchost_slc0host_int_ena_reg_t slc0host_int_ena; + volatile slchost_slc1host_int_ena_reg_t slc1host_int_ena; + volatile slchost_slc0host_rx_infor_reg_t slc0host_rx_infor; + volatile slchost_slc1host_rx_infor_reg_t slc1host_rx_infor; + volatile slchost_slc0host_len_wd_reg_t slc0host_len_wd; + volatile slchost_slc_apbwin_wdata_reg_t slc_apbwin_wdata; + volatile slchost_slc_apbwin_conf_reg_t slc_apbwin_conf; + volatile slchost_slc_apbwin_rdata_reg_t slc_apbwin_rdata; + volatile slchost_rdclr0_reg_t rdclr0; + volatile slchost_rdclr1_reg_t rdclr1; + volatile slchost_slc0host_int_ena1_reg_t slc0host_int_ena1; + volatile slchost_slc1host_int_ena1_reg_t slc1host_int_ena1; + uint32_t reserved_11c[23]; + volatile slchost_slchostdate_reg_t slchostdate; + volatile slchost_slchostid_reg_t slchostid; + uint32_t reserved_180[28]; + volatile slchost_conf_reg_t conf; + volatile slchost_inf_st_reg_t inf_st; +} slchost_dev_t; + +extern slchost_dev_t HOST; + +#ifndef __cplusplus +_Static_assert(sizeof(slchost_dev_t) == 0x1f8, "Invalid size of slchost_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/hp_apm_reg.h b/components/soc/esp32c6/include/soc/hp_apm_reg.h new file mode 100644 index 0000000000..fb7cc66c15 --- /dev/null +++ b/components/soc/esp32c6/include/soc/hp_apm_reg.h @@ -0,0 +1,1838 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HP_APM_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define HP_APM_REGION_FILTER_EN_REG (DR_REG_HP_APM_BASE + 0x0) +/** HP_APM_REGION_FILTER_EN : R/W; bitpos: [15:0]; default: 1; + * Region filter enable + */ +#define HP_APM_REGION_FILTER_EN 0x0000FFFFU +#define HP_APM_REGION_FILTER_EN_M (HP_APM_REGION_FILTER_EN_V << HP_APM_REGION_FILTER_EN_S) +#define HP_APM_REGION_FILTER_EN_V 0x0000FFFFU +#define HP_APM_REGION_FILTER_EN_S 0 + +/** HP_APM_REGION0_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION0_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4) +/** HP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ +#define HP_APM_REGION0_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION0_ADDR_START_M (HP_APM_REGION0_ADDR_START_V << HP_APM_REGION0_ADDR_START_S) +#define HP_APM_REGION0_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION0_ADDR_START_S 0 + +/** HP_APM_REGION0_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION0_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8) +/** HP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ +#define HP_APM_REGION0_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION0_ADDR_END_M (HP_APM_REGION0_ADDR_END_V << HP_APM_REGION0_ADDR_END_S) +#define HP_APM_REGION0_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION0_ADDR_END_S 0 + +/** HP_APM_REGION0_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION0_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xc) +/** HP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION0_R0_PMS_X (BIT(0)) +#define HP_APM_REGION0_R0_PMS_X_M (HP_APM_REGION0_R0_PMS_X_V << HP_APM_REGION0_R0_PMS_X_S) +#define HP_APM_REGION0_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION0_R0_PMS_X_S 0 +/** HP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION0_R0_PMS_W (BIT(1)) +#define HP_APM_REGION0_R0_PMS_W_M (HP_APM_REGION0_R0_PMS_W_V << HP_APM_REGION0_R0_PMS_W_S) +#define HP_APM_REGION0_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION0_R0_PMS_W_S 1 +/** HP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION0_R0_PMS_R (BIT(2)) +#define HP_APM_REGION0_R0_PMS_R_M (HP_APM_REGION0_R0_PMS_R_V << HP_APM_REGION0_R0_PMS_R_S) +#define HP_APM_REGION0_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION0_R0_PMS_R_S 2 +/** HP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION0_R1_PMS_X (BIT(4)) +#define HP_APM_REGION0_R1_PMS_X_M (HP_APM_REGION0_R1_PMS_X_V << HP_APM_REGION0_R1_PMS_X_S) +#define HP_APM_REGION0_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION0_R1_PMS_X_S 4 +/** HP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION0_R1_PMS_W (BIT(5)) +#define HP_APM_REGION0_R1_PMS_W_M (HP_APM_REGION0_R1_PMS_W_V << HP_APM_REGION0_R1_PMS_W_S) +#define HP_APM_REGION0_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION0_R1_PMS_W_S 5 +/** HP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION0_R1_PMS_R (BIT(6)) +#define HP_APM_REGION0_R1_PMS_R_M (HP_APM_REGION0_R1_PMS_R_V << HP_APM_REGION0_R1_PMS_R_S) +#define HP_APM_REGION0_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION0_R1_PMS_R_S 6 +/** HP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION0_R2_PMS_X (BIT(8)) +#define HP_APM_REGION0_R2_PMS_X_M (HP_APM_REGION0_R2_PMS_X_V << HP_APM_REGION0_R2_PMS_X_S) +#define HP_APM_REGION0_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION0_R2_PMS_X_S 8 +/** HP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION0_R2_PMS_W (BIT(9)) +#define HP_APM_REGION0_R2_PMS_W_M (HP_APM_REGION0_R2_PMS_W_V << HP_APM_REGION0_R2_PMS_W_S) +#define HP_APM_REGION0_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION0_R2_PMS_W_S 9 +/** HP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION0_R2_PMS_R (BIT(10)) +#define HP_APM_REGION0_R2_PMS_R_M (HP_APM_REGION0_R2_PMS_R_V << HP_APM_REGION0_R2_PMS_R_S) +#define HP_APM_REGION0_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION0_R2_PMS_R_S 10 + +/** HP_APM_REGION1_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION1_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x10) +/** HP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ +#define HP_APM_REGION1_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION1_ADDR_START_M (HP_APM_REGION1_ADDR_START_V << HP_APM_REGION1_ADDR_START_S) +#define HP_APM_REGION1_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION1_ADDR_START_S 0 + +/** HP_APM_REGION1_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION1_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x14) +/** HP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ +#define HP_APM_REGION1_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION1_ADDR_END_M (HP_APM_REGION1_ADDR_END_V << HP_APM_REGION1_ADDR_END_S) +#define HP_APM_REGION1_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION1_ADDR_END_S 0 + +/** HP_APM_REGION1_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION1_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x18) +/** HP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION1_R0_PMS_X (BIT(0)) +#define HP_APM_REGION1_R0_PMS_X_M (HP_APM_REGION1_R0_PMS_X_V << HP_APM_REGION1_R0_PMS_X_S) +#define HP_APM_REGION1_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION1_R0_PMS_X_S 0 +/** HP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION1_R0_PMS_W (BIT(1)) +#define HP_APM_REGION1_R0_PMS_W_M (HP_APM_REGION1_R0_PMS_W_V << HP_APM_REGION1_R0_PMS_W_S) +#define HP_APM_REGION1_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION1_R0_PMS_W_S 1 +/** HP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION1_R0_PMS_R (BIT(2)) +#define HP_APM_REGION1_R0_PMS_R_M (HP_APM_REGION1_R0_PMS_R_V << HP_APM_REGION1_R0_PMS_R_S) +#define HP_APM_REGION1_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION1_R0_PMS_R_S 2 +/** HP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION1_R1_PMS_X (BIT(4)) +#define HP_APM_REGION1_R1_PMS_X_M (HP_APM_REGION1_R1_PMS_X_V << HP_APM_REGION1_R1_PMS_X_S) +#define HP_APM_REGION1_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION1_R1_PMS_X_S 4 +/** HP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION1_R1_PMS_W (BIT(5)) +#define HP_APM_REGION1_R1_PMS_W_M (HP_APM_REGION1_R1_PMS_W_V << HP_APM_REGION1_R1_PMS_W_S) +#define HP_APM_REGION1_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION1_R1_PMS_W_S 5 +/** HP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION1_R1_PMS_R (BIT(6)) +#define HP_APM_REGION1_R1_PMS_R_M (HP_APM_REGION1_R1_PMS_R_V << HP_APM_REGION1_R1_PMS_R_S) +#define HP_APM_REGION1_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION1_R1_PMS_R_S 6 +/** HP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION1_R2_PMS_X (BIT(8)) +#define HP_APM_REGION1_R2_PMS_X_M (HP_APM_REGION1_R2_PMS_X_V << HP_APM_REGION1_R2_PMS_X_S) +#define HP_APM_REGION1_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION1_R2_PMS_X_S 8 +/** HP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION1_R2_PMS_W (BIT(9)) +#define HP_APM_REGION1_R2_PMS_W_M (HP_APM_REGION1_R2_PMS_W_V << HP_APM_REGION1_R2_PMS_W_S) +#define HP_APM_REGION1_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION1_R2_PMS_W_S 9 +/** HP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION1_R2_PMS_R (BIT(10)) +#define HP_APM_REGION1_R2_PMS_R_M (HP_APM_REGION1_R2_PMS_R_V << HP_APM_REGION1_R2_PMS_R_S) +#define HP_APM_REGION1_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION1_R2_PMS_R_S 10 + +/** HP_APM_REGION2_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION2_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x1c) +/** HP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ +#define HP_APM_REGION2_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION2_ADDR_START_M (HP_APM_REGION2_ADDR_START_V << HP_APM_REGION2_ADDR_START_S) +#define HP_APM_REGION2_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION2_ADDR_START_S 0 + +/** HP_APM_REGION2_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION2_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x20) +/** HP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ +#define HP_APM_REGION2_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION2_ADDR_END_M (HP_APM_REGION2_ADDR_END_V << HP_APM_REGION2_ADDR_END_S) +#define HP_APM_REGION2_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION2_ADDR_END_S 0 + +/** HP_APM_REGION2_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION2_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x24) +/** HP_APM_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION2_R0_PMS_X (BIT(0)) +#define HP_APM_REGION2_R0_PMS_X_M (HP_APM_REGION2_R0_PMS_X_V << HP_APM_REGION2_R0_PMS_X_S) +#define HP_APM_REGION2_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION2_R0_PMS_X_S 0 +/** HP_APM_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION2_R0_PMS_W (BIT(1)) +#define HP_APM_REGION2_R0_PMS_W_M (HP_APM_REGION2_R0_PMS_W_V << HP_APM_REGION2_R0_PMS_W_S) +#define HP_APM_REGION2_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION2_R0_PMS_W_S 1 +/** HP_APM_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION2_R0_PMS_R (BIT(2)) +#define HP_APM_REGION2_R0_PMS_R_M (HP_APM_REGION2_R0_PMS_R_V << HP_APM_REGION2_R0_PMS_R_S) +#define HP_APM_REGION2_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION2_R0_PMS_R_S 2 +/** HP_APM_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION2_R1_PMS_X (BIT(4)) +#define HP_APM_REGION2_R1_PMS_X_M (HP_APM_REGION2_R1_PMS_X_V << HP_APM_REGION2_R1_PMS_X_S) +#define HP_APM_REGION2_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION2_R1_PMS_X_S 4 +/** HP_APM_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION2_R1_PMS_W (BIT(5)) +#define HP_APM_REGION2_R1_PMS_W_M (HP_APM_REGION2_R1_PMS_W_V << HP_APM_REGION2_R1_PMS_W_S) +#define HP_APM_REGION2_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION2_R1_PMS_W_S 5 +/** HP_APM_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION2_R1_PMS_R (BIT(6)) +#define HP_APM_REGION2_R1_PMS_R_M (HP_APM_REGION2_R1_PMS_R_V << HP_APM_REGION2_R1_PMS_R_S) +#define HP_APM_REGION2_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION2_R1_PMS_R_S 6 +/** HP_APM_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION2_R2_PMS_X (BIT(8)) +#define HP_APM_REGION2_R2_PMS_X_M (HP_APM_REGION2_R2_PMS_X_V << HP_APM_REGION2_R2_PMS_X_S) +#define HP_APM_REGION2_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION2_R2_PMS_X_S 8 +/** HP_APM_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION2_R2_PMS_W (BIT(9)) +#define HP_APM_REGION2_R2_PMS_W_M (HP_APM_REGION2_R2_PMS_W_V << HP_APM_REGION2_R2_PMS_W_S) +#define HP_APM_REGION2_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION2_R2_PMS_W_S 9 +/** HP_APM_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION2_R2_PMS_R (BIT(10)) +#define HP_APM_REGION2_R2_PMS_R_M (HP_APM_REGION2_R2_PMS_R_V << HP_APM_REGION2_R2_PMS_R_S) +#define HP_APM_REGION2_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION2_R2_PMS_R_S 10 + +/** HP_APM_REGION3_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION3_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x28) +/** HP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ +#define HP_APM_REGION3_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION3_ADDR_START_M (HP_APM_REGION3_ADDR_START_V << HP_APM_REGION3_ADDR_START_S) +#define HP_APM_REGION3_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION3_ADDR_START_S 0 + +/** HP_APM_REGION3_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION3_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x2c) +/** HP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ +#define HP_APM_REGION3_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION3_ADDR_END_M (HP_APM_REGION3_ADDR_END_V << HP_APM_REGION3_ADDR_END_S) +#define HP_APM_REGION3_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION3_ADDR_END_S 0 + +/** HP_APM_REGION3_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION3_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x30) +/** HP_APM_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION3_R0_PMS_X (BIT(0)) +#define HP_APM_REGION3_R0_PMS_X_M (HP_APM_REGION3_R0_PMS_X_V << HP_APM_REGION3_R0_PMS_X_S) +#define HP_APM_REGION3_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION3_R0_PMS_X_S 0 +/** HP_APM_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION3_R0_PMS_W (BIT(1)) +#define HP_APM_REGION3_R0_PMS_W_M (HP_APM_REGION3_R0_PMS_W_V << HP_APM_REGION3_R0_PMS_W_S) +#define HP_APM_REGION3_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION3_R0_PMS_W_S 1 +/** HP_APM_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION3_R0_PMS_R (BIT(2)) +#define HP_APM_REGION3_R0_PMS_R_M (HP_APM_REGION3_R0_PMS_R_V << HP_APM_REGION3_R0_PMS_R_S) +#define HP_APM_REGION3_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION3_R0_PMS_R_S 2 +/** HP_APM_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION3_R1_PMS_X (BIT(4)) +#define HP_APM_REGION3_R1_PMS_X_M (HP_APM_REGION3_R1_PMS_X_V << HP_APM_REGION3_R1_PMS_X_S) +#define HP_APM_REGION3_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION3_R1_PMS_X_S 4 +/** HP_APM_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION3_R1_PMS_W (BIT(5)) +#define HP_APM_REGION3_R1_PMS_W_M (HP_APM_REGION3_R1_PMS_W_V << HP_APM_REGION3_R1_PMS_W_S) +#define HP_APM_REGION3_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION3_R1_PMS_W_S 5 +/** HP_APM_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION3_R1_PMS_R (BIT(6)) +#define HP_APM_REGION3_R1_PMS_R_M (HP_APM_REGION3_R1_PMS_R_V << HP_APM_REGION3_R1_PMS_R_S) +#define HP_APM_REGION3_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION3_R1_PMS_R_S 6 +/** HP_APM_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION3_R2_PMS_X (BIT(8)) +#define HP_APM_REGION3_R2_PMS_X_M (HP_APM_REGION3_R2_PMS_X_V << HP_APM_REGION3_R2_PMS_X_S) +#define HP_APM_REGION3_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION3_R2_PMS_X_S 8 +/** HP_APM_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION3_R2_PMS_W (BIT(9)) +#define HP_APM_REGION3_R2_PMS_W_M (HP_APM_REGION3_R2_PMS_W_V << HP_APM_REGION3_R2_PMS_W_S) +#define HP_APM_REGION3_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION3_R2_PMS_W_S 9 +/** HP_APM_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION3_R2_PMS_R (BIT(10)) +#define HP_APM_REGION3_R2_PMS_R_M (HP_APM_REGION3_R2_PMS_R_V << HP_APM_REGION3_R2_PMS_R_S) +#define HP_APM_REGION3_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION3_R2_PMS_R_S 10 + +/** HP_APM_REGION4_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION4_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x34) +/** HP_APM_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region4 + */ +#define HP_APM_REGION4_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION4_ADDR_START_M (HP_APM_REGION4_ADDR_START_V << HP_APM_REGION4_ADDR_START_S) +#define HP_APM_REGION4_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION4_ADDR_START_S 0 + +/** HP_APM_REGION4_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION4_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x38) +/** HP_APM_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region4 + */ +#define HP_APM_REGION4_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION4_ADDR_END_M (HP_APM_REGION4_ADDR_END_V << HP_APM_REGION4_ADDR_END_S) +#define HP_APM_REGION4_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION4_ADDR_END_S 0 + +/** HP_APM_REGION4_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION4_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x3c) +/** HP_APM_REGION4_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION4_R0_PMS_X (BIT(0)) +#define HP_APM_REGION4_R0_PMS_X_M (HP_APM_REGION4_R0_PMS_X_V << HP_APM_REGION4_R0_PMS_X_S) +#define HP_APM_REGION4_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION4_R0_PMS_X_S 0 +/** HP_APM_REGION4_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION4_R0_PMS_W (BIT(1)) +#define HP_APM_REGION4_R0_PMS_W_M (HP_APM_REGION4_R0_PMS_W_V << HP_APM_REGION4_R0_PMS_W_S) +#define HP_APM_REGION4_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION4_R0_PMS_W_S 1 +/** HP_APM_REGION4_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION4_R0_PMS_R (BIT(2)) +#define HP_APM_REGION4_R0_PMS_R_M (HP_APM_REGION4_R0_PMS_R_V << HP_APM_REGION4_R0_PMS_R_S) +#define HP_APM_REGION4_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION4_R0_PMS_R_S 2 +/** HP_APM_REGION4_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION4_R1_PMS_X (BIT(4)) +#define HP_APM_REGION4_R1_PMS_X_M (HP_APM_REGION4_R1_PMS_X_V << HP_APM_REGION4_R1_PMS_X_S) +#define HP_APM_REGION4_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION4_R1_PMS_X_S 4 +/** HP_APM_REGION4_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION4_R1_PMS_W (BIT(5)) +#define HP_APM_REGION4_R1_PMS_W_M (HP_APM_REGION4_R1_PMS_W_V << HP_APM_REGION4_R1_PMS_W_S) +#define HP_APM_REGION4_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION4_R1_PMS_W_S 5 +/** HP_APM_REGION4_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION4_R1_PMS_R (BIT(6)) +#define HP_APM_REGION4_R1_PMS_R_M (HP_APM_REGION4_R1_PMS_R_V << HP_APM_REGION4_R1_PMS_R_S) +#define HP_APM_REGION4_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION4_R1_PMS_R_S 6 +/** HP_APM_REGION4_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION4_R2_PMS_X (BIT(8)) +#define HP_APM_REGION4_R2_PMS_X_M (HP_APM_REGION4_R2_PMS_X_V << HP_APM_REGION4_R2_PMS_X_S) +#define HP_APM_REGION4_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION4_R2_PMS_X_S 8 +/** HP_APM_REGION4_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION4_R2_PMS_W (BIT(9)) +#define HP_APM_REGION4_R2_PMS_W_M (HP_APM_REGION4_R2_PMS_W_V << HP_APM_REGION4_R2_PMS_W_S) +#define HP_APM_REGION4_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION4_R2_PMS_W_S 9 +/** HP_APM_REGION4_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION4_R2_PMS_R (BIT(10)) +#define HP_APM_REGION4_R2_PMS_R_M (HP_APM_REGION4_R2_PMS_R_V << HP_APM_REGION4_R2_PMS_R_S) +#define HP_APM_REGION4_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION4_R2_PMS_R_S 10 + +/** HP_APM_REGION5_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION5_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x40) +/** HP_APM_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region5 + */ +#define HP_APM_REGION5_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION5_ADDR_START_M (HP_APM_REGION5_ADDR_START_V << HP_APM_REGION5_ADDR_START_S) +#define HP_APM_REGION5_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION5_ADDR_START_S 0 + +/** HP_APM_REGION5_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION5_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x44) +/** HP_APM_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region5 + */ +#define HP_APM_REGION5_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION5_ADDR_END_M (HP_APM_REGION5_ADDR_END_V << HP_APM_REGION5_ADDR_END_S) +#define HP_APM_REGION5_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION5_ADDR_END_S 0 + +/** HP_APM_REGION5_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION5_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x48) +/** HP_APM_REGION5_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION5_R0_PMS_X (BIT(0)) +#define HP_APM_REGION5_R0_PMS_X_M (HP_APM_REGION5_R0_PMS_X_V << HP_APM_REGION5_R0_PMS_X_S) +#define HP_APM_REGION5_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION5_R0_PMS_X_S 0 +/** HP_APM_REGION5_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION5_R0_PMS_W (BIT(1)) +#define HP_APM_REGION5_R0_PMS_W_M (HP_APM_REGION5_R0_PMS_W_V << HP_APM_REGION5_R0_PMS_W_S) +#define HP_APM_REGION5_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION5_R0_PMS_W_S 1 +/** HP_APM_REGION5_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION5_R0_PMS_R (BIT(2)) +#define HP_APM_REGION5_R0_PMS_R_M (HP_APM_REGION5_R0_PMS_R_V << HP_APM_REGION5_R0_PMS_R_S) +#define HP_APM_REGION5_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION5_R0_PMS_R_S 2 +/** HP_APM_REGION5_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION5_R1_PMS_X (BIT(4)) +#define HP_APM_REGION5_R1_PMS_X_M (HP_APM_REGION5_R1_PMS_X_V << HP_APM_REGION5_R1_PMS_X_S) +#define HP_APM_REGION5_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION5_R1_PMS_X_S 4 +/** HP_APM_REGION5_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION5_R1_PMS_W (BIT(5)) +#define HP_APM_REGION5_R1_PMS_W_M (HP_APM_REGION5_R1_PMS_W_V << HP_APM_REGION5_R1_PMS_W_S) +#define HP_APM_REGION5_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION5_R1_PMS_W_S 5 +/** HP_APM_REGION5_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION5_R1_PMS_R (BIT(6)) +#define HP_APM_REGION5_R1_PMS_R_M (HP_APM_REGION5_R1_PMS_R_V << HP_APM_REGION5_R1_PMS_R_S) +#define HP_APM_REGION5_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION5_R1_PMS_R_S 6 +/** HP_APM_REGION5_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION5_R2_PMS_X (BIT(8)) +#define HP_APM_REGION5_R2_PMS_X_M (HP_APM_REGION5_R2_PMS_X_V << HP_APM_REGION5_R2_PMS_X_S) +#define HP_APM_REGION5_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION5_R2_PMS_X_S 8 +/** HP_APM_REGION5_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION5_R2_PMS_W (BIT(9)) +#define HP_APM_REGION5_R2_PMS_W_M (HP_APM_REGION5_R2_PMS_W_V << HP_APM_REGION5_R2_PMS_W_S) +#define HP_APM_REGION5_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION5_R2_PMS_W_S 9 +/** HP_APM_REGION5_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION5_R2_PMS_R (BIT(10)) +#define HP_APM_REGION5_R2_PMS_R_M (HP_APM_REGION5_R2_PMS_R_V << HP_APM_REGION5_R2_PMS_R_S) +#define HP_APM_REGION5_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION5_R2_PMS_R_S 10 + +/** HP_APM_REGION6_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION6_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4c) +/** HP_APM_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region6 + */ +#define HP_APM_REGION6_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION6_ADDR_START_M (HP_APM_REGION6_ADDR_START_V << HP_APM_REGION6_ADDR_START_S) +#define HP_APM_REGION6_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION6_ADDR_START_S 0 + +/** HP_APM_REGION6_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION6_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x50) +/** HP_APM_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region6 + */ +#define HP_APM_REGION6_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION6_ADDR_END_M (HP_APM_REGION6_ADDR_END_V << HP_APM_REGION6_ADDR_END_S) +#define HP_APM_REGION6_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION6_ADDR_END_S 0 + +/** HP_APM_REGION6_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION6_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x54) +/** HP_APM_REGION6_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION6_R0_PMS_X (BIT(0)) +#define HP_APM_REGION6_R0_PMS_X_M (HP_APM_REGION6_R0_PMS_X_V << HP_APM_REGION6_R0_PMS_X_S) +#define HP_APM_REGION6_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION6_R0_PMS_X_S 0 +/** HP_APM_REGION6_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION6_R0_PMS_W (BIT(1)) +#define HP_APM_REGION6_R0_PMS_W_M (HP_APM_REGION6_R0_PMS_W_V << HP_APM_REGION6_R0_PMS_W_S) +#define HP_APM_REGION6_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION6_R0_PMS_W_S 1 +/** HP_APM_REGION6_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION6_R0_PMS_R (BIT(2)) +#define HP_APM_REGION6_R0_PMS_R_M (HP_APM_REGION6_R0_PMS_R_V << HP_APM_REGION6_R0_PMS_R_S) +#define HP_APM_REGION6_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION6_R0_PMS_R_S 2 +/** HP_APM_REGION6_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION6_R1_PMS_X (BIT(4)) +#define HP_APM_REGION6_R1_PMS_X_M (HP_APM_REGION6_R1_PMS_X_V << HP_APM_REGION6_R1_PMS_X_S) +#define HP_APM_REGION6_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION6_R1_PMS_X_S 4 +/** HP_APM_REGION6_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION6_R1_PMS_W (BIT(5)) +#define HP_APM_REGION6_R1_PMS_W_M (HP_APM_REGION6_R1_PMS_W_V << HP_APM_REGION6_R1_PMS_W_S) +#define HP_APM_REGION6_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION6_R1_PMS_W_S 5 +/** HP_APM_REGION6_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION6_R1_PMS_R (BIT(6)) +#define HP_APM_REGION6_R1_PMS_R_M (HP_APM_REGION6_R1_PMS_R_V << HP_APM_REGION6_R1_PMS_R_S) +#define HP_APM_REGION6_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION6_R1_PMS_R_S 6 +/** HP_APM_REGION6_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION6_R2_PMS_X (BIT(8)) +#define HP_APM_REGION6_R2_PMS_X_M (HP_APM_REGION6_R2_PMS_X_V << HP_APM_REGION6_R2_PMS_X_S) +#define HP_APM_REGION6_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION6_R2_PMS_X_S 8 +/** HP_APM_REGION6_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION6_R2_PMS_W (BIT(9)) +#define HP_APM_REGION6_R2_PMS_W_M (HP_APM_REGION6_R2_PMS_W_V << HP_APM_REGION6_R2_PMS_W_S) +#define HP_APM_REGION6_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION6_R2_PMS_W_S 9 +/** HP_APM_REGION6_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION6_R2_PMS_R (BIT(10)) +#define HP_APM_REGION6_R2_PMS_R_M (HP_APM_REGION6_R2_PMS_R_V << HP_APM_REGION6_R2_PMS_R_S) +#define HP_APM_REGION6_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION6_R2_PMS_R_S 10 + +/** HP_APM_REGION7_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION7_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x58) +/** HP_APM_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region7 + */ +#define HP_APM_REGION7_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION7_ADDR_START_M (HP_APM_REGION7_ADDR_START_V << HP_APM_REGION7_ADDR_START_S) +#define HP_APM_REGION7_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION7_ADDR_START_S 0 + +/** HP_APM_REGION7_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION7_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x5c) +/** HP_APM_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region7 + */ +#define HP_APM_REGION7_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION7_ADDR_END_M (HP_APM_REGION7_ADDR_END_V << HP_APM_REGION7_ADDR_END_S) +#define HP_APM_REGION7_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION7_ADDR_END_S 0 + +/** HP_APM_REGION7_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION7_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x60) +/** HP_APM_REGION7_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION7_R0_PMS_X (BIT(0)) +#define HP_APM_REGION7_R0_PMS_X_M (HP_APM_REGION7_R0_PMS_X_V << HP_APM_REGION7_R0_PMS_X_S) +#define HP_APM_REGION7_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION7_R0_PMS_X_S 0 +/** HP_APM_REGION7_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION7_R0_PMS_W (BIT(1)) +#define HP_APM_REGION7_R0_PMS_W_M (HP_APM_REGION7_R0_PMS_W_V << HP_APM_REGION7_R0_PMS_W_S) +#define HP_APM_REGION7_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION7_R0_PMS_W_S 1 +/** HP_APM_REGION7_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION7_R0_PMS_R (BIT(2)) +#define HP_APM_REGION7_R0_PMS_R_M (HP_APM_REGION7_R0_PMS_R_V << HP_APM_REGION7_R0_PMS_R_S) +#define HP_APM_REGION7_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION7_R0_PMS_R_S 2 +/** HP_APM_REGION7_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION7_R1_PMS_X (BIT(4)) +#define HP_APM_REGION7_R1_PMS_X_M (HP_APM_REGION7_R1_PMS_X_V << HP_APM_REGION7_R1_PMS_X_S) +#define HP_APM_REGION7_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION7_R1_PMS_X_S 4 +/** HP_APM_REGION7_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION7_R1_PMS_W (BIT(5)) +#define HP_APM_REGION7_R1_PMS_W_M (HP_APM_REGION7_R1_PMS_W_V << HP_APM_REGION7_R1_PMS_W_S) +#define HP_APM_REGION7_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION7_R1_PMS_W_S 5 +/** HP_APM_REGION7_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION7_R1_PMS_R (BIT(6)) +#define HP_APM_REGION7_R1_PMS_R_M (HP_APM_REGION7_R1_PMS_R_V << HP_APM_REGION7_R1_PMS_R_S) +#define HP_APM_REGION7_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION7_R1_PMS_R_S 6 +/** HP_APM_REGION7_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION7_R2_PMS_X (BIT(8)) +#define HP_APM_REGION7_R2_PMS_X_M (HP_APM_REGION7_R2_PMS_X_V << HP_APM_REGION7_R2_PMS_X_S) +#define HP_APM_REGION7_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION7_R2_PMS_X_S 8 +/** HP_APM_REGION7_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION7_R2_PMS_W (BIT(9)) +#define HP_APM_REGION7_R2_PMS_W_M (HP_APM_REGION7_R2_PMS_W_V << HP_APM_REGION7_R2_PMS_W_S) +#define HP_APM_REGION7_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION7_R2_PMS_W_S 9 +/** HP_APM_REGION7_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION7_R2_PMS_R (BIT(10)) +#define HP_APM_REGION7_R2_PMS_R_M (HP_APM_REGION7_R2_PMS_R_V << HP_APM_REGION7_R2_PMS_R_S) +#define HP_APM_REGION7_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION7_R2_PMS_R_S 10 + +/** HP_APM_REGION8_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION8_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x64) +/** HP_APM_REGION8_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region8 + */ +#define HP_APM_REGION8_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION8_ADDR_START_M (HP_APM_REGION8_ADDR_START_V << HP_APM_REGION8_ADDR_START_S) +#define HP_APM_REGION8_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION8_ADDR_START_S 0 + +/** HP_APM_REGION8_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION8_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x68) +/** HP_APM_REGION8_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region8 + */ +#define HP_APM_REGION8_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION8_ADDR_END_M (HP_APM_REGION8_ADDR_END_V << HP_APM_REGION8_ADDR_END_S) +#define HP_APM_REGION8_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION8_ADDR_END_S 0 + +/** HP_APM_REGION8_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION8_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x6c) +/** HP_APM_REGION8_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION8_R0_PMS_X (BIT(0)) +#define HP_APM_REGION8_R0_PMS_X_M (HP_APM_REGION8_R0_PMS_X_V << HP_APM_REGION8_R0_PMS_X_S) +#define HP_APM_REGION8_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION8_R0_PMS_X_S 0 +/** HP_APM_REGION8_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION8_R0_PMS_W (BIT(1)) +#define HP_APM_REGION8_R0_PMS_W_M (HP_APM_REGION8_R0_PMS_W_V << HP_APM_REGION8_R0_PMS_W_S) +#define HP_APM_REGION8_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION8_R0_PMS_W_S 1 +/** HP_APM_REGION8_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION8_R0_PMS_R (BIT(2)) +#define HP_APM_REGION8_R0_PMS_R_M (HP_APM_REGION8_R0_PMS_R_V << HP_APM_REGION8_R0_PMS_R_S) +#define HP_APM_REGION8_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION8_R0_PMS_R_S 2 +/** HP_APM_REGION8_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION8_R1_PMS_X (BIT(4)) +#define HP_APM_REGION8_R1_PMS_X_M (HP_APM_REGION8_R1_PMS_X_V << HP_APM_REGION8_R1_PMS_X_S) +#define HP_APM_REGION8_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION8_R1_PMS_X_S 4 +/** HP_APM_REGION8_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION8_R1_PMS_W (BIT(5)) +#define HP_APM_REGION8_R1_PMS_W_M (HP_APM_REGION8_R1_PMS_W_V << HP_APM_REGION8_R1_PMS_W_S) +#define HP_APM_REGION8_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION8_R1_PMS_W_S 5 +/** HP_APM_REGION8_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION8_R1_PMS_R (BIT(6)) +#define HP_APM_REGION8_R1_PMS_R_M (HP_APM_REGION8_R1_PMS_R_V << HP_APM_REGION8_R1_PMS_R_S) +#define HP_APM_REGION8_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION8_R1_PMS_R_S 6 +/** HP_APM_REGION8_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION8_R2_PMS_X (BIT(8)) +#define HP_APM_REGION8_R2_PMS_X_M (HP_APM_REGION8_R2_PMS_X_V << HP_APM_REGION8_R2_PMS_X_S) +#define HP_APM_REGION8_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION8_R2_PMS_X_S 8 +/** HP_APM_REGION8_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION8_R2_PMS_W (BIT(9)) +#define HP_APM_REGION8_R2_PMS_W_M (HP_APM_REGION8_R2_PMS_W_V << HP_APM_REGION8_R2_PMS_W_S) +#define HP_APM_REGION8_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION8_R2_PMS_W_S 9 +/** HP_APM_REGION8_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION8_R2_PMS_R (BIT(10)) +#define HP_APM_REGION8_R2_PMS_R_M (HP_APM_REGION8_R2_PMS_R_V << HP_APM_REGION8_R2_PMS_R_S) +#define HP_APM_REGION8_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION8_R2_PMS_R_S 10 + +/** HP_APM_REGION9_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION9_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x70) +/** HP_APM_REGION9_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region9 + */ +#define HP_APM_REGION9_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION9_ADDR_START_M (HP_APM_REGION9_ADDR_START_V << HP_APM_REGION9_ADDR_START_S) +#define HP_APM_REGION9_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION9_ADDR_START_S 0 + +/** HP_APM_REGION9_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION9_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x74) +/** HP_APM_REGION9_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region9 + */ +#define HP_APM_REGION9_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION9_ADDR_END_M (HP_APM_REGION9_ADDR_END_V << HP_APM_REGION9_ADDR_END_S) +#define HP_APM_REGION9_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION9_ADDR_END_S 0 + +/** HP_APM_REGION9_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION9_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x78) +/** HP_APM_REGION9_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION9_R0_PMS_X (BIT(0)) +#define HP_APM_REGION9_R0_PMS_X_M (HP_APM_REGION9_R0_PMS_X_V << HP_APM_REGION9_R0_PMS_X_S) +#define HP_APM_REGION9_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION9_R0_PMS_X_S 0 +/** HP_APM_REGION9_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION9_R0_PMS_W (BIT(1)) +#define HP_APM_REGION9_R0_PMS_W_M (HP_APM_REGION9_R0_PMS_W_V << HP_APM_REGION9_R0_PMS_W_S) +#define HP_APM_REGION9_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION9_R0_PMS_W_S 1 +/** HP_APM_REGION9_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION9_R0_PMS_R (BIT(2)) +#define HP_APM_REGION9_R0_PMS_R_M (HP_APM_REGION9_R0_PMS_R_V << HP_APM_REGION9_R0_PMS_R_S) +#define HP_APM_REGION9_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION9_R0_PMS_R_S 2 +/** HP_APM_REGION9_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION9_R1_PMS_X (BIT(4)) +#define HP_APM_REGION9_R1_PMS_X_M (HP_APM_REGION9_R1_PMS_X_V << HP_APM_REGION9_R1_PMS_X_S) +#define HP_APM_REGION9_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION9_R1_PMS_X_S 4 +/** HP_APM_REGION9_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION9_R1_PMS_W (BIT(5)) +#define HP_APM_REGION9_R1_PMS_W_M (HP_APM_REGION9_R1_PMS_W_V << HP_APM_REGION9_R1_PMS_W_S) +#define HP_APM_REGION9_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION9_R1_PMS_W_S 5 +/** HP_APM_REGION9_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION9_R1_PMS_R (BIT(6)) +#define HP_APM_REGION9_R1_PMS_R_M (HP_APM_REGION9_R1_PMS_R_V << HP_APM_REGION9_R1_PMS_R_S) +#define HP_APM_REGION9_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION9_R1_PMS_R_S 6 +/** HP_APM_REGION9_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION9_R2_PMS_X (BIT(8)) +#define HP_APM_REGION9_R2_PMS_X_M (HP_APM_REGION9_R2_PMS_X_V << HP_APM_REGION9_R2_PMS_X_S) +#define HP_APM_REGION9_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION9_R2_PMS_X_S 8 +/** HP_APM_REGION9_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION9_R2_PMS_W (BIT(9)) +#define HP_APM_REGION9_R2_PMS_W_M (HP_APM_REGION9_R2_PMS_W_V << HP_APM_REGION9_R2_PMS_W_S) +#define HP_APM_REGION9_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION9_R2_PMS_W_S 9 +/** HP_APM_REGION9_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION9_R2_PMS_R (BIT(10)) +#define HP_APM_REGION9_R2_PMS_R_M (HP_APM_REGION9_R2_PMS_R_V << HP_APM_REGION9_R2_PMS_R_S) +#define HP_APM_REGION9_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION9_R2_PMS_R_S 10 + +/** HP_APM_REGION10_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION10_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x7c) +/** HP_APM_REGION10_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region10 + */ +#define HP_APM_REGION10_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION10_ADDR_START_M (HP_APM_REGION10_ADDR_START_V << HP_APM_REGION10_ADDR_START_S) +#define HP_APM_REGION10_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION10_ADDR_START_S 0 + +/** HP_APM_REGION10_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION10_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x80) +/** HP_APM_REGION10_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region10 + */ +#define HP_APM_REGION10_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION10_ADDR_END_M (HP_APM_REGION10_ADDR_END_V << HP_APM_REGION10_ADDR_END_S) +#define HP_APM_REGION10_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION10_ADDR_END_S 0 + +/** HP_APM_REGION10_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION10_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x84) +/** HP_APM_REGION10_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION10_R0_PMS_X (BIT(0)) +#define HP_APM_REGION10_R0_PMS_X_M (HP_APM_REGION10_R0_PMS_X_V << HP_APM_REGION10_R0_PMS_X_S) +#define HP_APM_REGION10_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION10_R0_PMS_X_S 0 +/** HP_APM_REGION10_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION10_R0_PMS_W (BIT(1)) +#define HP_APM_REGION10_R0_PMS_W_M (HP_APM_REGION10_R0_PMS_W_V << HP_APM_REGION10_R0_PMS_W_S) +#define HP_APM_REGION10_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION10_R0_PMS_W_S 1 +/** HP_APM_REGION10_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION10_R0_PMS_R (BIT(2)) +#define HP_APM_REGION10_R0_PMS_R_M (HP_APM_REGION10_R0_PMS_R_V << HP_APM_REGION10_R0_PMS_R_S) +#define HP_APM_REGION10_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION10_R0_PMS_R_S 2 +/** HP_APM_REGION10_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION10_R1_PMS_X (BIT(4)) +#define HP_APM_REGION10_R1_PMS_X_M (HP_APM_REGION10_R1_PMS_X_V << HP_APM_REGION10_R1_PMS_X_S) +#define HP_APM_REGION10_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION10_R1_PMS_X_S 4 +/** HP_APM_REGION10_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION10_R1_PMS_W (BIT(5)) +#define HP_APM_REGION10_R1_PMS_W_M (HP_APM_REGION10_R1_PMS_W_V << HP_APM_REGION10_R1_PMS_W_S) +#define HP_APM_REGION10_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION10_R1_PMS_W_S 5 +/** HP_APM_REGION10_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION10_R1_PMS_R (BIT(6)) +#define HP_APM_REGION10_R1_PMS_R_M (HP_APM_REGION10_R1_PMS_R_V << HP_APM_REGION10_R1_PMS_R_S) +#define HP_APM_REGION10_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION10_R1_PMS_R_S 6 +/** HP_APM_REGION10_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION10_R2_PMS_X (BIT(8)) +#define HP_APM_REGION10_R2_PMS_X_M (HP_APM_REGION10_R2_PMS_X_V << HP_APM_REGION10_R2_PMS_X_S) +#define HP_APM_REGION10_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION10_R2_PMS_X_S 8 +/** HP_APM_REGION10_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION10_R2_PMS_W (BIT(9)) +#define HP_APM_REGION10_R2_PMS_W_M (HP_APM_REGION10_R2_PMS_W_V << HP_APM_REGION10_R2_PMS_W_S) +#define HP_APM_REGION10_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION10_R2_PMS_W_S 9 +/** HP_APM_REGION10_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION10_R2_PMS_R (BIT(10)) +#define HP_APM_REGION10_R2_PMS_R_M (HP_APM_REGION10_R2_PMS_R_V << HP_APM_REGION10_R2_PMS_R_S) +#define HP_APM_REGION10_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION10_R2_PMS_R_S 10 + +/** HP_APM_REGION11_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION11_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x88) +/** HP_APM_REGION11_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region11 + */ +#define HP_APM_REGION11_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION11_ADDR_START_M (HP_APM_REGION11_ADDR_START_V << HP_APM_REGION11_ADDR_START_S) +#define HP_APM_REGION11_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION11_ADDR_START_S 0 + +/** HP_APM_REGION11_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION11_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8c) +/** HP_APM_REGION11_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region11 + */ +#define HP_APM_REGION11_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION11_ADDR_END_M (HP_APM_REGION11_ADDR_END_V << HP_APM_REGION11_ADDR_END_S) +#define HP_APM_REGION11_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION11_ADDR_END_S 0 + +/** HP_APM_REGION11_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION11_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x90) +/** HP_APM_REGION11_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION11_R0_PMS_X (BIT(0)) +#define HP_APM_REGION11_R0_PMS_X_M (HP_APM_REGION11_R0_PMS_X_V << HP_APM_REGION11_R0_PMS_X_S) +#define HP_APM_REGION11_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION11_R0_PMS_X_S 0 +/** HP_APM_REGION11_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION11_R0_PMS_W (BIT(1)) +#define HP_APM_REGION11_R0_PMS_W_M (HP_APM_REGION11_R0_PMS_W_V << HP_APM_REGION11_R0_PMS_W_S) +#define HP_APM_REGION11_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION11_R0_PMS_W_S 1 +/** HP_APM_REGION11_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION11_R0_PMS_R (BIT(2)) +#define HP_APM_REGION11_R0_PMS_R_M (HP_APM_REGION11_R0_PMS_R_V << HP_APM_REGION11_R0_PMS_R_S) +#define HP_APM_REGION11_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION11_R0_PMS_R_S 2 +/** HP_APM_REGION11_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION11_R1_PMS_X (BIT(4)) +#define HP_APM_REGION11_R1_PMS_X_M (HP_APM_REGION11_R1_PMS_X_V << HP_APM_REGION11_R1_PMS_X_S) +#define HP_APM_REGION11_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION11_R1_PMS_X_S 4 +/** HP_APM_REGION11_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION11_R1_PMS_W (BIT(5)) +#define HP_APM_REGION11_R1_PMS_W_M (HP_APM_REGION11_R1_PMS_W_V << HP_APM_REGION11_R1_PMS_W_S) +#define HP_APM_REGION11_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION11_R1_PMS_W_S 5 +/** HP_APM_REGION11_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION11_R1_PMS_R (BIT(6)) +#define HP_APM_REGION11_R1_PMS_R_M (HP_APM_REGION11_R1_PMS_R_V << HP_APM_REGION11_R1_PMS_R_S) +#define HP_APM_REGION11_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION11_R1_PMS_R_S 6 +/** HP_APM_REGION11_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION11_R2_PMS_X (BIT(8)) +#define HP_APM_REGION11_R2_PMS_X_M (HP_APM_REGION11_R2_PMS_X_V << HP_APM_REGION11_R2_PMS_X_S) +#define HP_APM_REGION11_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION11_R2_PMS_X_S 8 +/** HP_APM_REGION11_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION11_R2_PMS_W (BIT(9)) +#define HP_APM_REGION11_R2_PMS_W_M (HP_APM_REGION11_R2_PMS_W_V << HP_APM_REGION11_R2_PMS_W_S) +#define HP_APM_REGION11_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION11_R2_PMS_W_S 9 +/** HP_APM_REGION11_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION11_R2_PMS_R (BIT(10)) +#define HP_APM_REGION11_R2_PMS_R_M (HP_APM_REGION11_R2_PMS_R_V << HP_APM_REGION11_R2_PMS_R_S) +#define HP_APM_REGION11_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION11_R2_PMS_R_S 10 + +/** HP_APM_REGION12_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION12_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x94) +/** HP_APM_REGION12_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region12 + */ +#define HP_APM_REGION12_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION12_ADDR_START_M (HP_APM_REGION12_ADDR_START_V << HP_APM_REGION12_ADDR_START_S) +#define HP_APM_REGION12_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION12_ADDR_START_S 0 + +/** HP_APM_REGION12_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION12_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x98) +/** HP_APM_REGION12_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region12 + */ +#define HP_APM_REGION12_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION12_ADDR_END_M (HP_APM_REGION12_ADDR_END_V << HP_APM_REGION12_ADDR_END_S) +#define HP_APM_REGION12_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION12_ADDR_END_S 0 + +/** HP_APM_REGION12_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION12_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x9c) +/** HP_APM_REGION12_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION12_R0_PMS_X (BIT(0)) +#define HP_APM_REGION12_R0_PMS_X_M (HP_APM_REGION12_R0_PMS_X_V << HP_APM_REGION12_R0_PMS_X_S) +#define HP_APM_REGION12_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION12_R0_PMS_X_S 0 +/** HP_APM_REGION12_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION12_R0_PMS_W (BIT(1)) +#define HP_APM_REGION12_R0_PMS_W_M (HP_APM_REGION12_R0_PMS_W_V << HP_APM_REGION12_R0_PMS_W_S) +#define HP_APM_REGION12_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION12_R0_PMS_W_S 1 +/** HP_APM_REGION12_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION12_R0_PMS_R (BIT(2)) +#define HP_APM_REGION12_R0_PMS_R_M (HP_APM_REGION12_R0_PMS_R_V << HP_APM_REGION12_R0_PMS_R_S) +#define HP_APM_REGION12_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION12_R0_PMS_R_S 2 +/** HP_APM_REGION12_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION12_R1_PMS_X (BIT(4)) +#define HP_APM_REGION12_R1_PMS_X_M (HP_APM_REGION12_R1_PMS_X_V << HP_APM_REGION12_R1_PMS_X_S) +#define HP_APM_REGION12_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION12_R1_PMS_X_S 4 +/** HP_APM_REGION12_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION12_R1_PMS_W (BIT(5)) +#define HP_APM_REGION12_R1_PMS_W_M (HP_APM_REGION12_R1_PMS_W_V << HP_APM_REGION12_R1_PMS_W_S) +#define HP_APM_REGION12_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION12_R1_PMS_W_S 5 +/** HP_APM_REGION12_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION12_R1_PMS_R (BIT(6)) +#define HP_APM_REGION12_R1_PMS_R_M (HP_APM_REGION12_R1_PMS_R_V << HP_APM_REGION12_R1_PMS_R_S) +#define HP_APM_REGION12_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION12_R1_PMS_R_S 6 +/** HP_APM_REGION12_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION12_R2_PMS_X (BIT(8)) +#define HP_APM_REGION12_R2_PMS_X_M (HP_APM_REGION12_R2_PMS_X_V << HP_APM_REGION12_R2_PMS_X_S) +#define HP_APM_REGION12_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION12_R2_PMS_X_S 8 +/** HP_APM_REGION12_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION12_R2_PMS_W (BIT(9)) +#define HP_APM_REGION12_R2_PMS_W_M (HP_APM_REGION12_R2_PMS_W_V << HP_APM_REGION12_R2_PMS_W_S) +#define HP_APM_REGION12_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION12_R2_PMS_W_S 9 +/** HP_APM_REGION12_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION12_R2_PMS_R (BIT(10)) +#define HP_APM_REGION12_R2_PMS_R_M (HP_APM_REGION12_R2_PMS_R_V << HP_APM_REGION12_R2_PMS_R_S) +#define HP_APM_REGION12_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION12_R2_PMS_R_S 10 + +/** HP_APM_REGION13_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION13_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xa0) +/** HP_APM_REGION13_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region13 + */ +#define HP_APM_REGION13_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION13_ADDR_START_M (HP_APM_REGION13_ADDR_START_V << HP_APM_REGION13_ADDR_START_S) +#define HP_APM_REGION13_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION13_ADDR_START_S 0 + +/** HP_APM_REGION13_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION13_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xa4) +/** HP_APM_REGION13_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region13 + */ +#define HP_APM_REGION13_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION13_ADDR_END_M (HP_APM_REGION13_ADDR_END_V << HP_APM_REGION13_ADDR_END_S) +#define HP_APM_REGION13_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION13_ADDR_END_S 0 + +/** HP_APM_REGION13_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION13_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xa8) +/** HP_APM_REGION13_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION13_R0_PMS_X (BIT(0)) +#define HP_APM_REGION13_R0_PMS_X_M (HP_APM_REGION13_R0_PMS_X_V << HP_APM_REGION13_R0_PMS_X_S) +#define HP_APM_REGION13_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION13_R0_PMS_X_S 0 +/** HP_APM_REGION13_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION13_R0_PMS_W (BIT(1)) +#define HP_APM_REGION13_R0_PMS_W_M (HP_APM_REGION13_R0_PMS_W_V << HP_APM_REGION13_R0_PMS_W_S) +#define HP_APM_REGION13_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION13_R0_PMS_W_S 1 +/** HP_APM_REGION13_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION13_R0_PMS_R (BIT(2)) +#define HP_APM_REGION13_R0_PMS_R_M (HP_APM_REGION13_R0_PMS_R_V << HP_APM_REGION13_R0_PMS_R_S) +#define HP_APM_REGION13_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION13_R0_PMS_R_S 2 +/** HP_APM_REGION13_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION13_R1_PMS_X (BIT(4)) +#define HP_APM_REGION13_R1_PMS_X_M (HP_APM_REGION13_R1_PMS_X_V << HP_APM_REGION13_R1_PMS_X_S) +#define HP_APM_REGION13_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION13_R1_PMS_X_S 4 +/** HP_APM_REGION13_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION13_R1_PMS_W (BIT(5)) +#define HP_APM_REGION13_R1_PMS_W_M (HP_APM_REGION13_R1_PMS_W_V << HP_APM_REGION13_R1_PMS_W_S) +#define HP_APM_REGION13_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION13_R1_PMS_W_S 5 +/** HP_APM_REGION13_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION13_R1_PMS_R (BIT(6)) +#define HP_APM_REGION13_R1_PMS_R_M (HP_APM_REGION13_R1_PMS_R_V << HP_APM_REGION13_R1_PMS_R_S) +#define HP_APM_REGION13_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION13_R1_PMS_R_S 6 +/** HP_APM_REGION13_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION13_R2_PMS_X (BIT(8)) +#define HP_APM_REGION13_R2_PMS_X_M (HP_APM_REGION13_R2_PMS_X_V << HP_APM_REGION13_R2_PMS_X_S) +#define HP_APM_REGION13_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION13_R2_PMS_X_S 8 +/** HP_APM_REGION13_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION13_R2_PMS_W (BIT(9)) +#define HP_APM_REGION13_R2_PMS_W_M (HP_APM_REGION13_R2_PMS_W_V << HP_APM_REGION13_R2_PMS_W_S) +#define HP_APM_REGION13_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION13_R2_PMS_W_S 9 +/** HP_APM_REGION13_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION13_R2_PMS_R (BIT(10)) +#define HP_APM_REGION13_R2_PMS_R_M (HP_APM_REGION13_R2_PMS_R_V << HP_APM_REGION13_R2_PMS_R_S) +#define HP_APM_REGION13_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION13_R2_PMS_R_S 10 + +/** HP_APM_REGION14_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION14_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xac) +/** HP_APM_REGION14_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region14 + */ +#define HP_APM_REGION14_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION14_ADDR_START_M (HP_APM_REGION14_ADDR_START_V << HP_APM_REGION14_ADDR_START_S) +#define HP_APM_REGION14_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION14_ADDR_START_S 0 + +/** HP_APM_REGION14_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION14_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xb0) +/** HP_APM_REGION14_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region14 + */ +#define HP_APM_REGION14_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION14_ADDR_END_M (HP_APM_REGION14_ADDR_END_V << HP_APM_REGION14_ADDR_END_S) +#define HP_APM_REGION14_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION14_ADDR_END_S 0 + +/** HP_APM_REGION14_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION14_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xb4) +/** HP_APM_REGION14_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION14_R0_PMS_X (BIT(0)) +#define HP_APM_REGION14_R0_PMS_X_M (HP_APM_REGION14_R0_PMS_X_V << HP_APM_REGION14_R0_PMS_X_S) +#define HP_APM_REGION14_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION14_R0_PMS_X_S 0 +/** HP_APM_REGION14_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION14_R0_PMS_W (BIT(1)) +#define HP_APM_REGION14_R0_PMS_W_M (HP_APM_REGION14_R0_PMS_W_V << HP_APM_REGION14_R0_PMS_W_S) +#define HP_APM_REGION14_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION14_R0_PMS_W_S 1 +/** HP_APM_REGION14_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION14_R0_PMS_R (BIT(2)) +#define HP_APM_REGION14_R0_PMS_R_M (HP_APM_REGION14_R0_PMS_R_V << HP_APM_REGION14_R0_PMS_R_S) +#define HP_APM_REGION14_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION14_R0_PMS_R_S 2 +/** HP_APM_REGION14_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION14_R1_PMS_X (BIT(4)) +#define HP_APM_REGION14_R1_PMS_X_M (HP_APM_REGION14_R1_PMS_X_V << HP_APM_REGION14_R1_PMS_X_S) +#define HP_APM_REGION14_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION14_R1_PMS_X_S 4 +/** HP_APM_REGION14_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION14_R1_PMS_W (BIT(5)) +#define HP_APM_REGION14_R1_PMS_W_M (HP_APM_REGION14_R1_PMS_W_V << HP_APM_REGION14_R1_PMS_W_S) +#define HP_APM_REGION14_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION14_R1_PMS_W_S 5 +/** HP_APM_REGION14_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION14_R1_PMS_R (BIT(6)) +#define HP_APM_REGION14_R1_PMS_R_M (HP_APM_REGION14_R1_PMS_R_V << HP_APM_REGION14_R1_PMS_R_S) +#define HP_APM_REGION14_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION14_R1_PMS_R_S 6 +/** HP_APM_REGION14_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION14_R2_PMS_X (BIT(8)) +#define HP_APM_REGION14_R2_PMS_X_M (HP_APM_REGION14_R2_PMS_X_V << HP_APM_REGION14_R2_PMS_X_S) +#define HP_APM_REGION14_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION14_R2_PMS_X_S 8 +/** HP_APM_REGION14_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION14_R2_PMS_W (BIT(9)) +#define HP_APM_REGION14_R2_PMS_W_M (HP_APM_REGION14_R2_PMS_W_V << HP_APM_REGION14_R2_PMS_W_S) +#define HP_APM_REGION14_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION14_R2_PMS_W_S 9 +/** HP_APM_REGION14_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION14_R2_PMS_R (BIT(10)) +#define HP_APM_REGION14_R2_PMS_R_M (HP_APM_REGION14_R2_PMS_R_V << HP_APM_REGION14_R2_PMS_R_S) +#define HP_APM_REGION14_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION14_R2_PMS_R_S 10 + +/** HP_APM_REGION15_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION15_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xb8) +/** HP_APM_REGION15_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region15 + */ +#define HP_APM_REGION15_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION15_ADDR_START_M (HP_APM_REGION15_ADDR_START_V << HP_APM_REGION15_ADDR_START_S) +#define HP_APM_REGION15_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION15_ADDR_START_S 0 + +/** HP_APM_REGION15_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION15_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xbc) +/** HP_APM_REGION15_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region15 + */ +#define HP_APM_REGION15_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION15_ADDR_END_M (HP_APM_REGION15_ADDR_END_V << HP_APM_REGION15_ADDR_END_S) +#define HP_APM_REGION15_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION15_ADDR_END_S 0 + +/** HP_APM_REGION15_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION15_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xc0) +/** HP_APM_REGION15_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION15_R0_PMS_X (BIT(0)) +#define HP_APM_REGION15_R0_PMS_X_M (HP_APM_REGION15_R0_PMS_X_V << HP_APM_REGION15_R0_PMS_X_S) +#define HP_APM_REGION15_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION15_R0_PMS_X_S 0 +/** HP_APM_REGION15_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION15_R0_PMS_W (BIT(1)) +#define HP_APM_REGION15_R0_PMS_W_M (HP_APM_REGION15_R0_PMS_W_V << HP_APM_REGION15_R0_PMS_W_S) +#define HP_APM_REGION15_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION15_R0_PMS_W_S 1 +/** HP_APM_REGION15_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION15_R0_PMS_R (BIT(2)) +#define HP_APM_REGION15_R0_PMS_R_M (HP_APM_REGION15_R0_PMS_R_V << HP_APM_REGION15_R0_PMS_R_S) +#define HP_APM_REGION15_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION15_R0_PMS_R_S 2 +/** HP_APM_REGION15_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION15_R1_PMS_X (BIT(4)) +#define HP_APM_REGION15_R1_PMS_X_M (HP_APM_REGION15_R1_PMS_X_V << HP_APM_REGION15_R1_PMS_X_S) +#define HP_APM_REGION15_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION15_R1_PMS_X_S 4 +/** HP_APM_REGION15_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION15_R1_PMS_W (BIT(5)) +#define HP_APM_REGION15_R1_PMS_W_M (HP_APM_REGION15_R1_PMS_W_V << HP_APM_REGION15_R1_PMS_W_S) +#define HP_APM_REGION15_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION15_R1_PMS_W_S 5 +/** HP_APM_REGION15_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION15_R1_PMS_R (BIT(6)) +#define HP_APM_REGION15_R1_PMS_R_M (HP_APM_REGION15_R1_PMS_R_V << HP_APM_REGION15_R1_PMS_R_S) +#define HP_APM_REGION15_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION15_R1_PMS_R_S 6 +/** HP_APM_REGION15_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION15_R2_PMS_X (BIT(8)) +#define HP_APM_REGION15_R2_PMS_X_M (HP_APM_REGION15_R2_PMS_X_V << HP_APM_REGION15_R2_PMS_X_S) +#define HP_APM_REGION15_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION15_R2_PMS_X_S 8 +/** HP_APM_REGION15_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION15_R2_PMS_W (BIT(9)) +#define HP_APM_REGION15_R2_PMS_W_M (HP_APM_REGION15_R2_PMS_W_V << HP_APM_REGION15_R2_PMS_W_S) +#define HP_APM_REGION15_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION15_R2_PMS_W_S 9 +/** HP_APM_REGION15_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION15_R2_PMS_R (BIT(10)) +#define HP_APM_REGION15_R2_PMS_R_M (HP_APM_REGION15_R2_PMS_R_V << HP_APM_REGION15_R2_PMS_R_S) +#define HP_APM_REGION15_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION15_R2_PMS_R_S 10 + +/** HP_APM_FUNC_CTRL_REG register + * PMS function control register + */ +#define HP_APM_FUNC_CTRL_REG (DR_REG_HP_APM_BASE + 0xc4) +/** HP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define HP_APM_M0_PMS_FUNC_EN (BIT(0)) +#define HP_APM_M0_PMS_FUNC_EN_M (HP_APM_M0_PMS_FUNC_EN_V << HP_APM_M0_PMS_FUNC_EN_S) +#define HP_APM_M0_PMS_FUNC_EN_V 0x00000001U +#define HP_APM_M0_PMS_FUNC_EN_S 0 +/** HP_APM_M1_PMS_FUNC_EN : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ +#define HP_APM_M1_PMS_FUNC_EN (BIT(1)) +#define HP_APM_M1_PMS_FUNC_EN_M (HP_APM_M1_PMS_FUNC_EN_V << HP_APM_M1_PMS_FUNC_EN_S) +#define HP_APM_M1_PMS_FUNC_EN_V 0x00000001U +#define HP_APM_M1_PMS_FUNC_EN_S 1 +/** HP_APM_M2_PMS_FUNC_EN : R/W; bitpos: [2]; default: 1; + * PMS M2 function enable + */ +#define HP_APM_M2_PMS_FUNC_EN (BIT(2)) +#define HP_APM_M2_PMS_FUNC_EN_M (HP_APM_M2_PMS_FUNC_EN_V << HP_APM_M2_PMS_FUNC_EN_S) +#define HP_APM_M2_PMS_FUNC_EN_V 0x00000001U +#define HP_APM_M2_PMS_FUNC_EN_S 2 +/** HP_APM_M3_PMS_FUNC_EN : R/W; bitpos: [3]; default: 1; + * PMS M3 function enable + */ +#define HP_APM_M3_PMS_FUNC_EN (BIT(3)) +#define HP_APM_M3_PMS_FUNC_EN_M (HP_APM_M3_PMS_FUNC_EN_V << HP_APM_M3_PMS_FUNC_EN_S) +#define HP_APM_M3_PMS_FUNC_EN_V 0x00000001U +#define HP_APM_M3_PMS_FUNC_EN_S 3 + +/** HP_APM_M0_STATUS_REG register + * M0 status register + */ +#define HP_APM_M0_STATUS_REG (DR_REG_HP_APM_BASE + 0xc8) +/** HP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define HP_APM_M0_EXCEPTION_STATUS 0x00000003U +#define HP_APM_M0_EXCEPTION_STATUS_M (HP_APM_M0_EXCEPTION_STATUS_V << HP_APM_M0_EXCEPTION_STATUS_S) +#define HP_APM_M0_EXCEPTION_STATUS_V 0x00000003U +#define HP_APM_M0_EXCEPTION_STATUS_S 0 + +/** HP_APM_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define HP_APM_M0_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xcc) +/** HP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define HP_APM_M0_REGION_STATUS_CLR (BIT(0)) +#define HP_APM_M0_REGION_STATUS_CLR_M (HP_APM_M0_REGION_STATUS_CLR_V << HP_APM_M0_REGION_STATUS_CLR_S) +#define HP_APM_M0_REGION_STATUS_CLR_V 0x00000001U +#define HP_APM_M0_REGION_STATUS_CLR_S 0 + +/** HP_APM_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define HP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xd0) +/** HP_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Exception region + */ +#define HP_APM_M0_EXCEPTION_REGION 0x0000FFFFU +#define HP_APM_M0_EXCEPTION_REGION_M (HP_APM_M0_EXCEPTION_REGION_V << HP_APM_M0_EXCEPTION_REGION_S) +#define HP_APM_M0_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_APM_M0_EXCEPTION_REGION_S 0 +/** HP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define HP_APM_M0_EXCEPTION_MODE 0x00000003U +#define HP_APM_M0_EXCEPTION_MODE_M (HP_APM_M0_EXCEPTION_MODE_V << HP_APM_M0_EXCEPTION_MODE_S) +#define HP_APM_M0_EXCEPTION_MODE_V 0x00000003U +#define HP_APM_M0_EXCEPTION_MODE_S 16 +/** HP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define HP_APM_M0_EXCEPTION_ID 0x0000001FU +#define HP_APM_M0_EXCEPTION_ID_M (HP_APM_M0_EXCEPTION_ID_V << HP_APM_M0_EXCEPTION_ID_S) +#define HP_APM_M0_EXCEPTION_ID_V 0x0000001FU +#define HP_APM_M0_EXCEPTION_ID_S 18 + +/** HP_APM_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define HP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xd4) +/** HP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define HP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_APM_M0_EXCEPTION_ADDR_M (HP_APM_M0_EXCEPTION_ADDR_V << HP_APM_M0_EXCEPTION_ADDR_S) +#define HP_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_APM_M0_EXCEPTION_ADDR_S 0 + +/** HP_APM_M1_STATUS_REG register + * M1 status register + */ +#define HP_APM_M1_STATUS_REG (DR_REG_HP_APM_BASE + 0xd8) +/** HP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define HP_APM_M1_EXCEPTION_STATUS 0x00000003U +#define HP_APM_M1_EXCEPTION_STATUS_M (HP_APM_M1_EXCEPTION_STATUS_V << HP_APM_M1_EXCEPTION_STATUS_S) +#define HP_APM_M1_EXCEPTION_STATUS_V 0x00000003U +#define HP_APM_M1_EXCEPTION_STATUS_S 0 + +/** HP_APM_M1_STATUS_CLR_REG register + * M1 status clear register + */ +#define HP_APM_M1_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xdc) +/** HP_APM_M1_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define HP_APM_M1_REGION_STATUS_CLR (BIT(0)) +#define HP_APM_M1_REGION_STATUS_CLR_M (HP_APM_M1_REGION_STATUS_CLR_V << HP_APM_M1_REGION_STATUS_CLR_S) +#define HP_APM_M1_REGION_STATUS_CLR_V 0x00000001U +#define HP_APM_M1_REGION_STATUS_CLR_S 0 + +/** HP_APM_M1_EXCEPTION_INFO0_REG register + * M1 exception_info0 register + */ +#define HP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xe0) +/** HP_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Exception region + */ +#define HP_APM_M1_EXCEPTION_REGION 0x0000FFFFU +#define HP_APM_M1_EXCEPTION_REGION_M (HP_APM_M1_EXCEPTION_REGION_V << HP_APM_M1_EXCEPTION_REGION_S) +#define HP_APM_M1_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_APM_M1_EXCEPTION_REGION_S 0 +/** HP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define HP_APM_M1_EXCEPTION_MODE 0x00000003U +#define HP_APM_M1_EXCEPTION_MODE_M (HP_APM_M1_EXCEPTION_MODE_V << HP_APM_M1_EXCEPTION_MODE_S) +#define HP_APM_M1_EXCEPTION_MODE_V 0x00000003U +#define HP_APM_M1_EXCEPTION_MODE_S 16 +/** HP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define HP_APM_M1_EXCEPTION_ID 0x0000001FU +#define HP_APM_M1_EXCEPTION_ID_M (HP_APM_M1_EXCEPTION_ID_V << HP_APM_M1_EXCEPTION_ID_S) +#define HP_APM_M1_EXCEPTION_ID_V 0x0000001FU +#define HP_APM_M1_EXCEPTION_ID_S 18 + +/** HP_APM_M1_EXCEPTION_INFO1_REG register + * M1 exception_info1 register + */ +#define HP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xe4) +/** HP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define HP_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_APM_M1_EXCEPTION_ADDR_M (HP_APM_M1_EXCEPTION_ADDR_V << HP_APM_M1_EXCEPTION_ADDR_S) +#define HP_APM_M1_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_APM_M1_EXCEPTION_ADDR_S 0 + +/** HP_APM_M2_STATUS_REG register + * M2 status register + */ +#define HP_APM_M2_STATUS_REG (DR_REG_HP_APM_BASE + 0xe8) +/** HP_APM_M2_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define HP_APM_M2_EXCEPTION_STATUS 0x00000003U +#define HP_APM_M2_EXCEPTION_STATUS_M (HP_APM_M2_EXCEPTION_STATUS_V << HP_APM_M2_EXCEPTION_STATUS_S) +#define HP_APM_M2_EXCEPTION_STATUS_V 0x00000003U +#define HP_APM_M2_EXCEPTION_STATUS_S 0 + +/** HP_APM_M2_STATUS_CLR_REG register + * M2 status clear register + */ +#define HP_APM_M2_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xec) +/** HP_APM_M2_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define HP_APM_M2_REGION_STATUS_CLR (BIT(0)) +#define HP_APM_M2_REGION_STATUS_CLR_M (HP_APM_M2_REGION_STATUS_CLR_V << HP_APM_M2_REGION_STATUS_CLR_S) +#define HP_APM_M2_REGION_STATUS_CLR_V 0x00000001U +#define HP_APM_M2_REGION_STATUS_CLR_S 0 + +/** HP_APM_M2_EXCEPTION_INFO0_REG register + * M2 exception_info0 register + */ +#define HP_APM_M2_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xf0) +/** HP_APM_M2_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Exception region + */ +#define HP_APM_M2_EXCEPTION_REGION 0x0000FFFFU +#define HP_APM_M2_EXCEPTION_REGION_M (HP_APM_M2_EXCEPTION_REGION_V << HP_APM_M2_EXCEPTION_REGION_S) +#define HP_APM_M2_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_APM_M2_EXCEPTION_REGION_S 0 +/** HP_APM_M2_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define HP_APM_M2_EXCEPTION_MODE 0x00000003U +#define HP_APM_M2_EXCEPTION_MODE_M (HP_APM_M2_EXCEPTION_MODE_V << HP_APM_M2_EXCEPTION_MODE_S) +#define HP_APM_M2_EXCEPTION_MODE_V 0x00000003U +#define HP_APM_M2_EXCEPTION_MODE_S 16 +/** HP_APM_M2_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define HP_APM_M2_EXCEPTION_ID 0x0000001FU +#define HP_APM_M2_EXCEPTION_ID_M (HP_APM_M2_EXCEPTION_ID_V << HP_APM_M2_EXCEPTION_ID_S) +#define HP_APM_M2_EXCEPTION_ID_V 0x0000001FU +#define HP_APM_M2_EXCEPTION_ID_S 18 + +/** HP_APM_M2_EXCEPTION_INFO1_REG register + * M2 exception_info1 register + */ +#define HP_APM_M2_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xf4) +/** HP_APM_M2_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define HP_APM_M2_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_APM_M2_EXCEPTION_ADDR_M (HP_APM_M2_EXCEPTION_ADDR_V << HP_APM_M2_EXCEPTION_ADDR_S) +#define HP_APM_M2_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_APM_M2_EXCEPTION_ADDR_S 0 + +/** HP_APM_M3_STATUS_REG register + * M3 status register + */ +#define HP_APM_M3_STATUS_REG (DR_REG_HP_APM_BASE + 0xf8) +/** HP_APM_M3_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define HP_APM_M3_EXCEPTION_STATUS 0x00000003U +#define HP_APM_M3_EXCEPTION_STATUS_M (HP_APM_M3_EXCEPTION_STATUS_V << HP_APM_M3_EXCEPTION_STATUS_S) +#define HP_APM_M3_EXCEPTION_STATUS_V 0x00000003U +#define HP_APM_M3_EXCEPTION_STATUS_S 0 + +/** HP_APM_M3_STATUS_CLR_REG register + * M3 status clear register + */ +#define HP_APM_M3_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xfc) +/** HP_APM_M3_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define HP_APM_M3_REGION_STATUS_CLR (BIT(0)) +#define HP_APM_M3_REGION_STATUS_CLR_M (HP_APM_M3_REGION_STATUS_CLR_V << HP_APM_M3_REGION_STATUS_CLR_S) +#define HP_APM_M3_REGION_STATUS_CLR_V 0x00000001U +#define HP_APM_M3_REGION_STATUS_CLR_S 0 + +/** HP_APM_M3_EXCEPTION_INFO0_REG register + * M3 exception_info0 register + */ +#define HP_APM_M3_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0x100) +/** HP_APM_M3_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Exception region + */ +#define HP_APM_M3_EXCEPTION_REGION 0x0000FFFFU +#define HP_APM_M3_EXCEPTION_REGION_M (HP_APM_M3_EXCEPTION_REGION_V << HP_APM_M3_EXCEPTION_REGION_S) +#define HP_APM_M3_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_APM_M3_EXCEPTION_REGION_S 0 +/** HP_APM_M3_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define HP_APM_M3_EXCEPTION_MODE 0x00000003U +#define HP_APM_M3_EXCEPTION_MODE_M (HP_APM_M3_EXCEPTION_MODE_V << HP_APM_M3_EXCEPTION_MODE_S) +#define HP_APM_M3_EXCEPTION_MODE_V 0x00000003U +#define HP_APM_M3_EXCEPTION_MODE_S 16 +/** HP_APM_M3_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define HP_APM_M3_EXCEPTION_ID 0x0000001FU +#define HP_APM_M3_EXCEPTION_ID_M (HP_APM_M3_EXCEPTION_ID_V << HP_APM_M3_EXCEPTION_ID_S) +#define HP_APM_M3_EXCEPTION_ID_V 0x0000001FU +#define HP_APM_M3_EXCEPTION_ID_S 18 + +/** HP_APM_M3_EXCEPTION_INFO1_REG register + * M3 exception_info1 register + */ +#define HP_APM_M3_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0x104) +/** HP_APM_M3_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define HP_APM_M3_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_APM_M3_EXCEPTION_ADDR_M (HP_APM_M3_EXCEPTION_ADDR_V << HP_APM_M3_EXCEPTION_ADDR_S) +#define HP_APM_M3_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_APM_M3_EXCEPTION_ADDR_S 0 + +/** HP_APM_INT_EN_REG register + * APM interrupt enable register + */ +#define HP_APM_INT_EN_REG (DR_REG_HP_APM_BASE + 0x108) +/** HP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ +#define HP_APM_M0_APM_INT_EN (BIT(0)) +#define HP_APM_M0_APM_INT_EN_M (HP_APM_M0_APM_INT_EN_V << HP_APM_M0_APM_INT_EN_S) +#define HP_APM_M0_APM_INT_EN_V 0x00000001U +#define HP_APM_M0_APM_INT_EN_S 0 +/** HP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; + * APM M1 interrupt enable + */ +#define HP_APM_M1_APM_INT_EN (BIT(1)) +#define HP_APM_M1_APM_INT_EN_M (HP_APM_M1_APM_INT_EN_V << HP_APM_M1_APM_INT_EN_S) +#define HP_APM_M1_APM_INT_EN_V 0x00000001U +#define HP_APM_M1_APM_INT_EN_S 1 +/** HP_APM_M2_APM_INT_EN : R/W; bitpos: [2]; default: 0; + * APM M2 interrupt enable + */ +#define HP_APM_M2_APM_INT_EN (BIT(2)) +#define HP_APM_M2_APM_INT_EN_M (HP_APM_M2_APM_INT_EN_V << HP_APM_M2_APM_INT_EN_S) +#define HP_APM_M2_APM_INT_EN_V 0x00000001U +#define HP_APM_M2_APM_INT_EN_S 2 +/** HP_APM_M3_APM_INT_EN : R/W; bitpos: [3]; default: 0; + * APM M3 interrupt enable + */ +#define HP_APM_M3_APM_INT_EN (BIT(3)) +#define HP_APM_M3_APM_INT_EN_M (HP_APM_M3_APM_INT_EN_V << HP_APM_M3_APM_INT_EN_S) +#define HP_APM_M3_APM_INT_EN_V 0x00000001U +#define HP_APM_M3_APM_INT_EN_S 3 + +/** HP_APM_CLOCK_GATE_REG register + * clock gating register + */ +#define HP_APM_CLOCK_GATE_REG (DR_REG_HP_APM_BASE + 0x10c) +/** HP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define HP_APM_CLK_EN (BIT(0)) +#define HP_APM_CLK_EN_M (HP_APM_CLK_EN_V << HP_APM_CLK_EN_S) +#define HP_APM_CLK_EN_V 0x00000001U +#define HP_APM_CLK_EN_S 0 + +/** HP_APM_DATE_REG register + * Version register + */ +#define HP_APM_DATE_REG (DR_REG_HP_APM_BASE + 0x7fc) +/** HP_APM_DATE : R/W; bitpos: [27:0]; default: 35672640; + * reg_date + */ +#define HP_APM_DATE 0x0FFFFFFFU +#define HP_APM_DATE_M (HP_APM_DATE_V << HP_APM_DATE_S) +#define HP_APM_DATE_V 0x0FFFFFFFU +#define HP_APM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/hp_apm_struct.h b/components/soc/esp32c6/include/soc/hp_apm_struct.h new file mode 100644 index 0000000000..5cc1cd3938 --- /dev/null +++ b/components/soc/esp32c6/include/soc/hp_apm_struct.h @@ -0,0 +1,1670 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** region_filter_en : R/W; bitpos: [15:0]; default: 1; + * Region filter enable + */ + uint32_t region_filter_en:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} hp_apm_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of region0_addr_start register + * Region address register + */ +typedef union { + struct { + /** region0_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ + uint32_t region0_addr_start:32; + }; + uint32_t val; +} hp_apm_region0_addr_start_reg_t; + +/** Type of region0_addr_end register + * Region address register + */ +typedef union { + struct { + /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ + uint32_t region0_addr_end:32; + }; + uint32_t val; +} hp_apm_region0_addr_end_reg_t; + +/** Type of region1_addr_start register + * Region address register + */ +typedef union { + struct { + /** region1_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ + uint32_t region1_addr_start:32; + }; + uint32_t val; +} hp_apm_region1_addr_start_reg_t; + +/** Type of region1_addr_end register + * Region address register + */ +typedef union { + struct { + /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ + uint32_t region1_addr_end:32; + }; + uint32_t val; +} hp_apm_region1_addr_end_reg_t; + +/** Type of region2_addr_start register + * Region address register + */ +typedef union { + struct { + /** region2_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ + uint32_t region2_addr_start:32; + }; + uint32_t val; +} hp_apm_region2_addr_start_reg_t; + +/** Type of region2_addr_end register + * Region address register + */ +typedef union { + struct { + /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ + uint32_t region2_addr_end:32; + }; + uint32_t val; +} hp_apm_region2_addr_end_reg_t; + +/** Type of region3_addr_start register + * Region address register + */ +typedef union { + struct { + /** region3_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ + uint32_t region3_addr_start:32; + }; + uint32_t val; +} hp_apm_region3_addr_start_reg_t; + +/** Type of region3_addr_end register + * Region address register + */ +typedef union { + struct { + /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ + uint32_t region3_addr_end:32; + }; + uint32_t val; +} hp_apm_region3_addr_end_reg_t; + +/** Type of region4_addr_start register + * Region address register + */ +typedef union { + struct { + /** region4_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region4 + */ + uint32_t region4_addr_start:32; + }; + uint32_t val; +} hp_apm_region4_addr_start_reg_t; + +/** Type of region4_addr_end register + * Region address register + */ +typedef union { + struct { + /** region4_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region4 + */ + uint32_t region4_addr_end:32; + }; + uint32_t val; +} hp_apm_region4_addr_end_reg_t; + +/** Type of region5_addr_start register + * Region address register + */ +typedef union { + struct { + /** region5_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region5 + */ + uint32_t region5_addr_start:32; + }; + uint32_t val; +} hp_apm_region5_addr_start_reg_t; + +/** Type of region5_addr_end register + * Region address register + */ +typedef union { + struct { + /** region5_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region5 + */ + uint32_t region5_addr_end:32; + }; + uint32_t val; +} hp_apm_region5_addr_end_reg_t; + +/** Type of region6_addr_start register + * Region address register + */ +typedef union { + struct { + /** region6_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region6 + */ + uint32_t region6_addr_start:32; + }; + uint32_t val; +} hp_apm_region6_addr_start_reg_t; + +/** Type of region6_addr_end register + * Region address register + */ +typedef union { + struct { + /** region6_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region6 + */ + uint32_t region6_addr_end:32; + }; + uint32_t val; +} hp_apm_region6_addr_end_reg_t; + +/** Type of region7_addr_start register + * Region address register + */ +typedef union { + struct { + /** region7_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region7 + */ + uint32_t region7_addr_start:32; + }; + uint32_t val; +} hp_apm_region7_addr_start_reg_t; + +/** Type of region7_addr_end register + * Region address register + */ +typedef union { + struct { + /** region7_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region7 + */ + uint32_t region7_addr_end:32; + }; + uint32_t val; +} hp_apm_region7_addr_end_reg_t; + +/** Type of region8_addr_start register + * Region address register + */ +typedef union { + struct { + /** region8_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region8 + */ + uint32_t region8_addr_start:32; + }; + uint32_t val; +} hp_apm_region8_addr_start_reg_t; + +/** Type of region8_addr_end register + * Region address register + */ +typedef union { + struct { + /** region8_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region8 + */ + uint32_t region8_addr_end:32; + }; + uint32_t val; +} hp_apm_region8_addr_end_reg_t; + +/** Type of region9_addr_start register + * Region address register + */ +typedef union { + struct { + /** region9_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region9 + */ + uint32_t region9_addr_start:32; + }; + uint32_t val; +} hp_apm_region9_addr_start_reg_t; + +/** Type of region9_addr_end register + * Region address register + */ +typedef union { + struct { + /** region9_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region9 + */ + uint32_t region9_addr_end:32; + }; + uint32_t val; +} hp_apm_region9_addr_end_reg_t; + +/** Type of region10_addr_start register + * Region address register + */ +typedef union { + struct { + /** region10_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region10 + */ + uint32_t region10_addr_start:32; + }; + uint32_t val; +} hp_apm_region10_addr_start_reg_t; + +/** Type of region10_addr_end register + * Region address register + */ +typedef union { + struct { + /** region10_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region10 + */ + uint32_t region10_addr_end:32; + }; + uint32_t val; +} hp_apm_region10_addr_end_reg_t; + +/** Type of region11_addr_start register + * Region address register + */ +typedef union { + struct { + /** region11_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region11 + */ + uint32_t region11_addr_start:32; + }; + uint32_t val; +} hp_apm_region11_addr_start_reg_t; + +/** Type of region11_addr_end register + * Region address register + */ +typedef union { + struct { + /** region11_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region11 + */ + uint32_t region11_addr_end:32; + }; + uint32_t val; +} hp_apm_region11_addr_end_reg_t; + +/** Type of region12_addr_start register + * Region address register + */ +typedef union { + struct { + /** region12_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region12 + */ + uint32_t region12_addr_start:32; + }; + uint32_t val; +} hp_apm_region12_addr_start_reg_t; + +/** Type of region12_addr_end register + * Region address register + */ +typedef union { + struct { + /** region12_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region12 + */ + uint32_t region12_addr_end:32; + }; + uint32_t val; +} hp_apm_region12_addr_end_reg_t; + +/** Type of region13_addr_start register + * Region address register + */ +typedef union { + struct { + /** region13_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region13 + */ + uint32_t region13_addr_start:32; + }; + uint32_t val; +} hp_apm_region13_addr_start_reg_t; + +/** Type of region13_addr_end register + * Region address register + */ +typedef union { + struct { + /** region13_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region13 + */ + uint32_t region13_addr_end:32; + }; + uint32_t val; +} hp_apm_region13_addr_end_reg_t; + +/** Type of region14_addr_start register + * Region address register + */ +typedef union { + struct { + /** region14_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region14 + */ + uint32_t region14_addr_start:32; + }; + uint32_t val; +} hp_apm_region14_addr_start_reg_t; + +/** Type of region14_addr_end register + * Region address register + */ +typedef union { + struct { + /** region14_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region14 + */ + uint32_t region14_addr_end:32; + }; + uint32_t val; +} hp_apm_region14_addr_end_reg_t; + +/** Type of region15_addr_start register + * Region address register + */ +typedef union { + struct { + /** region15_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region15 + */ + uint32_t region15_addr_start:32; + }; + uint32_t val; +} hp_apm_region15_addr_start_reg_t; + +/** Type of region15_addr_end register + * Region address register + */ +typedef union { + struct { + /** region15_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region15 + */ + uint32_t region15_addr_end:32; + }; + uint32_t val; +} hp_apm_region15_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of region0_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region0_r0_pms_x:1; + /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region0_r0_pms_w:1; + /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region0_r0_pms_r:1; + uint32_t reserved_3:1; + /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region0_r1_pms_x:1; + /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region0_r1_pms_w:1; + /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region0_r1_pms_r:1; + uint32_t reserved_7:1; + /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region0_r2_pms_x:1; + /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region0_r2_pms_w:1; + /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region0_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region0_pms_attr_reg_t; + +/** Type of region1_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region1_r0_pms_x:1; + /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region1_r0_pms_w:1; + /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region1_r0_pms_r:1; + uint32_t reserved_3:1; + /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region1_r1_pms_x:1; + /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region1_r1_pms_w:1; + /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region1_r1_pms_r:1; + uint32_t reserved_7:1; + /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region1_r2_pms_x:1; + /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region1_r2_pms_w:1; + /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region1_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region1_pms_attr_reg_t; + +/** Type of region2_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region2_r0_pms_x:1; + /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region2_r0_pms_w:1; + /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region2_r0_pms_r:1; + uint32_t reserved_3:1; + /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region2_r1_pms_x:1; + /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region2_r1_pms_w:1; + /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region2_r1_pms_r:1; + uint32_t reserved_7:1; + /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region2_r2_pms_x:1; + /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region2_r2_pms_w:1; + /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region2_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region2_pms_attr_reg_t; + +/** Type of region3_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region3_r0_pms_x:1; + /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region3_r0_pms_w:1; + /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region3_r0_pms_r:1; + uint32_t reserved_3:1; + /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region3_r1_pms_x:1; + /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region3_r1_pms_w:1; + /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region3_r1_pms_r:1; + uint32_t reserved_7:1; + /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region3_r2_pms_x:1; + /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region3_r2_pms_w:1; + /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region3_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region3_pms_attr_reg_t; + +/** Type of region4_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region4_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region4_r0_pms_x:1; + /** region4_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region4_r0_pms_w:1; + /** region4_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region4_r0_pms_r:1; + uint32_t reserved_3:1; + /** region4_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region4_r1_pms_x:1; + /** region4_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region4_r1_pms_w:1; + /** region4_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region4_r1_pms_r:1; + uint32_t reserved_7:1; + /** region4_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region4_r2_pms_x:1; + /** region4_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region4_r2_pms_w:1; + /** region4_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region4_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region4_pms_attr_reg_t; + +/** Type of region5_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region5_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region5_r0_pms_x:1; + /** region5_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region5_r0_pms_w:1; + /** region5_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region5_r0_pms_r:1; + uint32_t reserved_3:1; + /** region5_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region5_r1_pms_x:1; + /** region5_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region5_r1_pms_w:1; + /** region5_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region5_r1_pms_r:1; + uint32_t reserved_7:1; + /** region5_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region5_r2_pms_x:1; + /** region5_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region5_r2_pms_w:1; + /** region5_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region5_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region5_pms_attr_reg_t; + +/** Type of region6_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region6_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region6_r0_pms_x:1; + /** region6_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region6_r0_pms_w:1; + /** region6_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region6_r0_pms_r:1; + uint32_t reserved_3:1; + /** region6_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region6_r1_pms_x:1; + /** region6_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region6_r1_pms_w:1; + /** region6_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region6_r1_pms_r:1; + uint32_t reserved_7:1; + /** region6_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region6_r2_pms_x:1; + /** region6_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region6_r2_pms_w:1; + /** region6_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region6_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region6_pms_attr_reg_t; + +/** Type of region7_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region7_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region7_r0_pms_x:1; + /** region7_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region7_r0_pms_w:1; + /** region7_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region7_r0_pms_r:1; + uint32_t reserved_3:1; + /** region7_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region7_r1_pms_x:1; + /** region7_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region7_r1_pms_w:1; + /** region7_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region7_r1_pms_r:1; + uint32_t reserved_7:1; + /** region7_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region7_r2_pms_x:1; + /** region7_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region7_r2_pms_w:1; + /** region7_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region7_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region7_pms_attr_reg_t; + +/** Type of region8_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region8_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region8_r0_pms_x:1; + /** region8_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region8_r0_pms_w:1; + /** region8_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region8_r0_pms_r:1; + uint32_t reserved_3:1; + /** region8_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region8_r1_pms_x:1; + /** region8_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region8_r1_pms_w:1; + /** region8_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region8_r1_pms_r:1; + uint32_t reserved_7:1; + /** region8_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region8_r2_pms_x:1; + /** region8_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region8_r2_pms_w:1; + /** region8_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region8_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region8_pms_attr_reg_t; + +/** Type of region9_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region9_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region9_r0_pms_x:1; + /** region9_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region9_r0_pms_w:1; + /** region9_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region9_r0_pms_r:1; + uint32_t reserved_3:1; + /** region9_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region9_r1_pms_x:1; + /** region9_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region9_r1_pms_w:1; + /** region9_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region9_r1_pms_r:1; + uint32_t reserved_7:1; + /** region9_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region9_r2_pms_x:1; + /** region9_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region9_r2_pms_w:1; + /** region9_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region9_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region9_pms_attr_reg_t; + +/** Type of region10_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region10_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region10_r0_pms_x:1; + /** region10_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region10_r0_pms_w:1; + /** region10_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region10_r0_pms_r:1; + uint32_t reserved_3:1; + /** region10_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region10_r1_pms_x:1; + /** region10_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region10_r1_pms_w:1; + /** region10_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region10_r1_pms_r:1; + uint32_t reserved_7:1; + /** region10_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region10_r2_pms_x:1; + /** region10_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region10_r2_pms_w:1; + /** region10_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region10_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region10_pms_attr_reg_t; + +/** Type of region11_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region11_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region11_r0_pms_x:1; + /** region11_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region11_r0_pms_w:1; + /** region11_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region11_r0_pms_r:1; + uint32_t reserved_3:1; + /** region11_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region11_r1_pms_x:1; + /** region11_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region11_r1_pms_w:1; + /** region11_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region11_r1_pms_r:1; + uint32_t reserved_7:1; + /** region11_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region11_r2_pms_x:1; + /** region11_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region11_r2_pms_w:1; + /** region11_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region11_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region11_pms_attr_reg_t; + +/** Type of region12_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region12_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region12_r0_pms_x:1; + /** region12_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region12_r0_pms_w:1; + /** region12_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region12_r0_pms_r:1; + uint32_t reserved_3:1; + /** region12_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region12_r1_pms_x:1; + /** region12_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region12_r1_pms_w:1; + /** region12_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region12_r1_pms_r:1; + uint32_t reserved_7:1; + /** region12_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region12_r2_pms_x:1; + /** region12_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region12_r2_pms_w:1; + /** region12_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region12_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region12_pms_attr_reg_t; + +/** Type of region13_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region13_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region13_r0_pms_x:1; + /** region13_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region13_r0_pms_w:1; + /** region13_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region13_r0_pms_r:1; + uint32_t reserved_3:1; + /** region13_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region13_r1_pms_x:1; + /** region13_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region13_r1_pms_w:1; + /** region13_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region13_r1_pms_r:1; + uint32_t reserved_7:1; + /** region13_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region13_r2_pms_x:1; + /** region13_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region13_r2_pms_w:1; + /** region13_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region13_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region13_pms_attr_reg_t; + +/** Type of region14_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region14_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region14_r0_pms_x:1; + /** region14_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region14_r0_pms_w:1; + /** region14_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region14_r0_pms_r:1; + uint32_t reserved_3:1; + /** region14_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region14_r1_pms_x:1; + /** region14_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region14_r1_pms_w:1; + /** region14_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region14_r1_pms_r:1; + uint32_t reserved_7:1; + /** region14_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region14_r2_pms_x:1; + /** region14_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region14_r2_pms_w:1; + /** region14_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region14_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region14_pms_attr_reg_t; + +/** Type of region15_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region15_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region15_r0_pms_x:1; + /** region15_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region15_r0_pms_w:1; + /** region15_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region15_r0_pms_r:1; + uint32_t reserved_3:1; + /** region15_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region15_r1_pms_x:1; + /** region15_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region15_r1_pms_w:1; + /** region15_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region15_r1_pms_r:1; + uint32_t reserved_7:1; + /** region15_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region15_r2_pms_x:1; + /** region15_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region15_r2_pms_w:1; + /** region15_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region15_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} hp_apm_region15_pms_attr_reg_t; + + +/** Group: PMS function control register */ +/** Type of func_ctrl register + * PMS function control register + */ +typedef union { + struct { + /** m0_pms_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t m0_pms_func_en:1; + /** m1_pms_func_en : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ + uint32_t m1_pms_func_en:1; + /** m2_pms_func_en : R/W; bitpos: [2]; default: 1; + * PMS M2 function enable + */ + uint32_t m2_pms_func_en:1; + /** m3_pms_func_en : R/W; bitpos: [3]; default: 1; + * PMS M3 function enable + */ + uint32_t m3_pms_func_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} hp_apm_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of m0_status register + * M0 status register + */ +typedef union { + struct { + /** m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_apm_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** m0_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m0_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** m0_exception_region : RO; bitpos: [15:0]; default: 0; + * Exception region + */ + uint32_t m0_exception_region:16; + /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m0_exception_mode:2; + /** m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_apm_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m0_exception_addr:32; + }; + uint32_t val; +} hp_apm_m0_exception_info1_reg_t; + + +/** Group: M1 status register */ +/** Type of m1_status register + * M1 status register + */ +typedef union { + struct { + /** m1_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m1_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_apm_m1_status_reg_t; + + +/** Group: M1 status clear register */ +/** Type of m1_status_clr register + * M1 status clear register + */ +typedef union { + struct { + /** m1_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m1_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_m1_status_clr_reg_t; + + +/** Group: M1 exception_info0 register */ +/** Type of m1_exception_info0 register + * M1 exception_info0 register + */ +typedef union { + struct { + /** m1_exception_region : RO; bitpos: [15:0]; default: 0; + * Exception region + */ + uint32_t m1_exception_region:16; + /** m1_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m1_exception_mode:2; + /** m1_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m1_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_apm_m1_exception_info0_reg_t; + + +/** Group: M1 exception_info1 register */ +/** Type of m1_exception_info1 register + * M1 exception_info1 register + */ +typedef union { + struct { + /** m1_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m1_exception_addr:32; + }; + uint32_t val; +} hp_apm_m1_exception_info1_reg_t; + + +/** Group: M2 status register */ +/** Type of m2_status register + * M2 status register + */ +typedef union { + struct { + /** m2_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m2_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_apm_m2_status_reg_t; + + +/** Group: M2 status clear register */ +/** Type of m2_status_clr register + * M2 status clear register + */ +typedef union { + struct { + /** m2_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m2_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_m2_status_clr_reg_t; + + +/** Group: M2 exception_info0 register */ +/** Type of m2_exception_info0 register + * M2 exception_info0 register + */ +typedef union { + struct { + /** m2_exception_region : RO; bitpos: [15:0]; default: 0; + * Exception region + */ + uint32_t m2_exception_region:16; + /** m2_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m2_exception_mode:2; + /** m2_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m2_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_apm_m2_exception_info0_reg_t; + + +/** Group: M2 exception_info1 register */ +/** Type of m2_exception_info1 register + * M2 exception_info1 register + */ +typedef union { + struct { + /** m2_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m2_exception_addr:32; + }; + uint32_t val; +} hp_apm_m2_exception_info1_reg_t; + + +/** Group: M3 status register */ +/** Type of m3_status register + * M3 status register + */ +typedef union { + struct { + /** m3_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m3_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_apm_m3_status_reg_t; + + +/** Group: M3 status clear register */ +/** Type of m3_status_clr register + * M3 status clear register + */ +typedef union { + struct { + /** m3_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m3_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_m3_status_clr_reg_t; + + +/** Group: M3 exception_info0 register */ +/** Type of m3_exception_info0 register + * M3 exception_info0 register + */ +typedef union { + struct { + /** m3_exception_region : RO; bitpos: [15:0]; default: 0; + * Exception region + */ + uint32_t m3_exception_region:16; + /** m3_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m3_exception_mode:2; + /** m3_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m3_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_apm_m3_exception_info0_reg_t; + + +/** Group: M3 exception_info1 register */ +/** Type of m3_exception_info1 register + * M3 exception_info1 register + */ +typedef union { + struct { + /** m3_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m3_exception_addr:32; + }; + uint32_t val; +} hp_apm_m3_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ + uint32_t m0_apm_int_en:1; + /** m1_apm_int_en : R/W; bitpos: [1]; default: 0; + * APM M1 interrupt enable + */ + uint32_t m1_apm_int_en:1; + /** m2_apm_int_en : R/W; bitpos: [2]; default: 0; + * APM M2 interrupt enable + */ + uint32_t m2_apm_int_en:1; + /** m3_apm_int_en : R/W; bitpos: [3]; default: 0; + * APM M3 interrupt enable + */ + uint32_t m3_apm_int_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} hp_apm_int_en_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35672640; + * reg_date + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} hp_apm_date_reg_t; + + +typedef struct hp_apm_dev_t { + volatile hp_apm_region_filter_en_reg_t region_filter_en; + volatile hp_apm_region0_addr_start_reg_t region0_addr_start; + volatile hp_apm_region0_addr_end_reg_t region0_addr_end; + volatile hp_apm_region0_pms_attr_reg_t region0_pms_attr; + volatile hp_apm_region1_addr_start_reg_t region1_addr_start; + volatile hp_apm_region1_addr_end_reg_t region1_addr_end; + volatile hp_apm_region1_pms_attr_reg_t region1_pms_attr; + volatile hp_apm_region2_addr_start_reg_t region2_addr_start; + volatile hp_apm_region2_addr_end_reg_t region2_addr_end; + volatile hp_apm_region2_pms_attr_reg_t region2_pms_attr; + volatile hp_apm_region3_addr_start_reg_t region3_addr_start; + volatile hp_apm_region3_addr_end_reg_t region3_addr_end; + volatile hp_apm_region3_pms_attr_reg_t region3_pms_attr; + volatile hp_apm_region4_addr_start_reg_t region4_addr_start; + volatile hp_apm_region4_addr_end_reg_t region4_addr_end; + volatile hp_apm_region4_pms_attr_reg_t region4_pms_attr; + volatile hp_apm_region5_addr_start_reg_t region5_addr_start; + volatile hp_apm_region5_addr_end_reg_t region5_addr_end; + volatile hp_apm_region5_pms_attr_reg_t region5_pms_attr; + volatile hp_apm_region6_addr_start_reg_t region6_addr_start; + volatile hp_apm_region6_addr_end_reg_t region6_addr_end; + volatile hp_apm_region6_pms_attr_reg_t region6_pms_attr; + volatile hp_apm_region7_addr_start_reg_t region7_addr_start; + volatile hp_apm_region7_addr_end_reg_t region7_addr_end; + volatile hp_apm_region7_pms_attr_reg_t region7_pms_attr; + volatile hp_apm_region8_addr_start_reg_t region8_addr_start; + volatile hp_apm_region8_addr_end_reg_t region8_addr_end; + volatile hp_apm_region8_pms_attr_reg_t region8_pms_attr; + volatile hp_apm_region9_addr_start_reg_t region9_addr_start; + volatile hp_apm_region9_addr_end_reg_t region9_addr_end; + volatile hp_apm_region9_pms_attr_reg_t region9_pms_attr; + volatile hp_apm_region10_addr_start_reg_t region10_addr_start; + volatile hp_apm_region10_addr_end_reg_t region10_addr_end; + volatile hp_apm_region10_pms_attr_reg_t region10_pms_attr; + volatile hp_apm_region11_addr_start_reg_t region11_addr_start; + volatile hp_apm_region11_addr_end_reg_t region11_addr_end; + volatile hp_apm_region11_pms_attr_reg_t region11_pms_attr; + volatile hp_apm_region12_addr_start_reg_t region12_addr_start; + volatile hp_apm_region12_addr_end_reg_t region12_addr_end; + volatile hp_apm_region12_pms_attr_reg_t region12_pms_attr; + volatile hp_apm_region13_addr_start_reg_t region13_addr_start; + volatile hp_apm_region13_addr_end_reg_t region13_addr_end; + volatile hp_apm_region13_pms_attr_reg_t region13_pms_attr; + volatile hp_apm_region14_addr_start_reg_t region14_addr_start; + volatile hp_apm_region14_addr_end_reg_t region14_addr_end; + volatile hp_apm_region14_pms_attr_reg_t region14_pms_attr; + volatile hp_apm_region15_addr_start_reg_t region15_addr_start; + volatile hp_apm_region15_addr_end_reg_t region15_addr_end; + volatile hp_apm_region15_pms_attr_reg_t region15_pms_attr; + volatile hp_apm_func_ctrl_reg_t func_ctrl; + volatile hp_apm_m0_status_reg_t m0_status; + volatile hp_apm_m0_status_clr_reg_t m0_status_clr; + volatile hp_apm_m0_exception_info0_reg_t m0_exception_info0; + volatile hp_apm_m0_exception_info1_reg_t m0_exception_info1; + volatile hp_apm_m1_status_reg_t m1_status; + volatile hp_apm_m1_status_clr_reg_t m1_status_clr; + volatile hp_apm_m1_exception_info0_reg_t m1_exception_info0; + volatile hp_apm_m1_exception_info1_reg_t m1_exception_info1; + volatile hp_apm_m2_status_reg_t m2_status; + volatile hp_apm_m2_status_clr_reg_t m2_status_clr; + volatile hp_apm_m2_exception_info0_reg_t m2_exception_info0; + volatile hp_apm_m2_exception_info1_reg_t m2_exception_info1; + volatile hp_apm_m3_status_reg_t m3_status; + volatile hp_apm_m3_status_clr_reg_t m3_status_clr; + volatile hp_apm_m3_exception_info0_reg_t m3_exception_info0; + volatile hp_apm_m3_exception_info1_reg_t m3_exception_info1; + volatile hp_apm_int_en_reg_t int_en; + volatile hp_apm_clock_gate_reg_t clock_gate; + uint32_t reserved_110[443]; + volatile hp_apm_date_reg_t date; +} hp_apm_dev_t; + +extern hp_apm_dev_t HP_APM; + +#ifndef __cplusplus +_Static_assert(sizeof(hp_apm_dev_t) == 0x800, "Invalid size of hp_apm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/hp_system_reg.h b/components/soc/esp32c6/include/soc/hp_system_reg.h new file mode 100644 index 0000000000..898d0fb0e5 --- /dev/null +++ b/components/soc/esp32c6/include/soc/hp_system_reg.h @@ -0,0 +1,415 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register + * EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register + */ +#define HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_HP_SYSTEM_BASE + 0x0) +/** HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode. + */ +#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) +#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S) +#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x00000001U +#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0 +/** HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) +#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S) +#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001U +#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 +/** HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0; + * Set this bit as 1 to enable mspi xts auto decrypt in download boot mode. + */ +#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) +#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S) +#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x00000001U +#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 +/** HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0; + * Set this bit as 1 to enable mspi xts manual encrypt in download boot mode. + */ +#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) +#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S) +#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U +#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 + +/** HP_SYSTEM_SRAM_USAGE_CONF_REG register + * HP memory usage configuration register + */ +#define HP_SYSTEM_SRAM_USAGE_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x4) +/** HP_SYSTEM_CACHE_USAGE : HRO; bitpos: [0]; default: 0; + * reserved + */ +#define HP_SYSTEM_CACHE_USAGE (BIT(0)) +#define HP_SYSTEM_CACHE_USAGE_M (HP_SYSTEM_CACHE_USAGE_V << HP_SYSTEM_CACHE_USAGE_S) +#define HP_SYSTEM_CACHE_USAGE_V 0x00000001U +#define HP_SYSTEM_CACHE_USAGE_S 0 +/** HP_SYSTEM_SRAM_USAGE : R/W; bitpos: [11:8]; default: 0; + * 0: cpu use hp-memory. 1:mac-dump accessing hp-memory. + */ +#define HP_SYSTEM_SRAM_USAGE 0x0000000FU +#define HP_SYSTEM_SRAM_USAGE_M (HP_SYSTEM_SRAM_USAGE_V << HP_SYSTEM_SRAM_USAGE_S) +#define HP_SYSTEM_SRAM_USAGE_V 0x0000000FU +#define HP_SYSTEM_SRAM_USAGE_S 8 +/** HP_SYSTEM_MAC_DUMP_ALLOC : R/W; bitpos: [16]; default: 0; + * Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory. + */ +#define HP_SYSTEM_MAC_DUMP_ALLOC (BIT(16)) +#define HP_SYSTEM_MAC_DUMP_ALLOC_M (HP_SYSTEM_MAC_DUMP_ALLOC_V << HP_SYSTEM_MAC_DUMP_ALLOC_S) +#define HP_SYSTEM_MAC_DUMP_ALLOC_V 0x00000001U +#define HP_SYSTEM_MAC_DUMP_ALLOC_S 16 + +/** HP_SYSTEM_SEC_DPA_CONF_REG register + * HP anti-DPA security configuration register + */ +#define HP_SYSTEM_SEC_DPA_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x8) +/** HP_SYSTEM_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0; + * 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger + * the number, the stronger the ability to resist DPA attacks and the higher the + * security level, but it will increase the computational overhead of the hardware + * crypto-accelerators. Only avaliable if HP_SYSTEM_SEC_DPA_CFG_SEL is 0. + */ +#define HP_SYSTEM_SEC_DPA_LEVEL 0x00000003U +#define HP_SYSTEM_SEC_DPA_LEVEL_M (HP_SYSTEM_SEC_DPA_LEVEL_V << HP_SYSTEM_SEC_DPA_LEVEL_S) +#define HP_SYSTEM_SEC_DPA_LEVEL_V 0x00000003U +#define HP_SYSTEM_SEC_DPA_LEVEL_S 0 +/** HP_SYSTEM_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0; + * This field is used to select either HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL + * (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYSTEM_SEC_DPA_LEVEL. + */ +#define HP_SYSTEM_SEC_DPA_CFG_SEL (BIT(2)) +#define HP_SYSTEM_SEC_DPA_CFG_SEL_M (HP_SYSTEM_SEC_DPA_CFG_SEL_V << HP_SYSTEM_SEC_DPA_CFG_SEL_S) +#define HP_SYSTEM_SEC_DPA_CFG_SEL_V 0x00000001U +#define HP_SYSTEM_SEC_DPA_CFG_SEL_S 2 + +/** HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG register + * CPU_PERI_TIMEOUT configuration register + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0xc) +/** HP_SYSTEM_CPU_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535; + * Set the timeout threshold for bus access, corresponding to the number of clock + * cycles of the clock domain. + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES 0x0000FFFFU +#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_M (HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V << HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V 0x0000FFFFU +#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S 0 +/** HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0; + * Set this bit as 1 to clear timeout interrupt + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR (BIT(16)) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U +#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S 16 +/** HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1; + * Set this bit as 1 to enable timeout protection for accessing cpu peripheral + * registers + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN (BIT(17)) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U +#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S 17 + +/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG register + * CPU_PERI_TIMEOUT_ADDR register + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x10) +/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; + * Record the address information of abnormal access + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR 0xFFFFFFFFU +#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU +#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S 0 + +/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG register + * CPU_PERI_TIMEOUT_UID register + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x14) +/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; + * Record master id[4:0] & master permission[6:5] when trigger timeout. This register + * will be cleared after the interrupt is cleared. + */ +#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID 0x0000007FU +#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_M (HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V << HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S) +#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V 0x0000007FU +#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S 0 + +/** HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG register + * HP_PERI_TIMEOUT configuration register + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x18) +/** HP_SYSTEM_HP_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535; + * Set the timeout threshold for bus access, corresponding to the number of clock + * cycles of the clock domain. + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES 0x0000FFFFU +#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_M (HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V << HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S) +#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V 0x0000FFFFU +#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S 0 +/** HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0; + * Set this bit as 1 to clear timeout interrupt + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR (BIT(16)) +#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S) +#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U +#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S 16 +/** HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1; + * Set this bit as 1 to enable timeout protection for accessing hp peripheral registers + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN (BIT(17)) +#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S) +#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U +#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S 17 + +/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG register + * HP_PERI_TIMEOUT_ADDR register + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x1c) +/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; + * Record the address information of abnormal access + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU +#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S) +#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU +#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S 0 + +/** HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG register + * HP_PERI_TIMEOUT_UID register + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x20) +/** HP_SYSTEM_HP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; + * Record master id[4:0] & master permission[6:5] when trigger timeout. This register + * will be cleared after the interrupt is cleared. + */ +#define HP_SYSTEM_HP_PERI_TIMEOUT_UID 0x0000007FU +#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_M (HP_SYSTEM_HP_PERI_TIMEOUT_UID_V << HP_SYSTEM_HP_PERI_TIMEOUT_UID_S) +#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_V 0x0000007FU +#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_S 0 + +/** HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG register + * MODEM_PERI_TIMEOUT configuration register + */ +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x24) +/** HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535; + * Set the timeout threshold for bus access, corresponding to the number of clock + * cycles of the clock domain. + */ +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES 0x0000FFFFU +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S) +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_V 0x0000FFFFU +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S 0 +/** HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0; + * Set this bit as 1 to clear timeout interrupt + */ +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR (BIT(16)) +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S) +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S 16 +/** HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1; + * Set this bit as 1 to enable timeout protection for accessing modem registers + */ +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN (BIT(17)) +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_S) +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_S 17 + +/** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG register + * MODEM_PERI_TIMEOUT_ADDR register + */ +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x28) +/** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; + * Record the address information of abnormal access + */ +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR 0xFFFFFFFFU +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_S) +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_S 0 + +/** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG register + * MODEM_PERI_TIMEOUT_UID register + */ +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x2c) +/** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; + * Record master id[4:0] & master permission[6:5] when trigger timeout. This register + * will be cleared after the interrupt is cleared. + */ +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID 0x0000007FU +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_S) +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_V 0x0000007FU +#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_S 0 + +/** HP_SYSTEM_SDIO_CTRL_REG register + * SDIO Control configuration register + */ +#define HP_SYSTEM_SDIO_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x30) +/** HP_SYSTEM_DIS_SDIO_PROB : R/W; bitpos: [0]; default: 1; + * Set this bit as 1 to disable SDIO_PROB function. disable by default. + */ +#define HP_SYSTEM_DIS_SDIO_PROB (BIT(0)) +#define HP_SYSTEM_DIS_SDIO_PROB_M (HP_SYSTEM_DIS_SDIO_PROB_V << HP_SYSTEM_DIS_SDIO_PROB_S) +#define HP_SYSTEM_DIS_SDIO_PROB_V 0x00000001U +#define HP_SYSTEM_DIS_SDIO_PROB_S 0 +/** HP_SYSTEM_SDIO_WIN_ACCESS_EN : R/W; bitpos: [1]; default: 1; + * Enable sdio slave to access other peripherals on the chip + */ +#define HP_SYSTEM_SDIO_WIN_ACCESS_EN (BIT(1)) +#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_M (HP_SYSTEM_SDIO_WIN_ACCESS_EN_V << HP_SYSTEM_SDIO_WIN_ACCESS_EN_S) +#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_V 0x00000001U +#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_S 1 + +/** HP_SYSTEM_RETENTION_CONF_REG register + * Retention configuration register + */ +#define HP_SYSTEM_RETENTION_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x34) +/** HP_SYSTEM_RETENTION_DISABLE : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to disable retention function. Not disable by default. + */ +#define HP_SYSTEM_RETENTION_DISABLE (BIT(0)) +#define HP_SYSTEM_RETENTION_DISABLE_M (HP_SYSTEM_RETENTION_DISABLE_V << HP_SYSTEM_RETENTION_DISABLE_S) +#define HP_SYSTEM_RETENTION_DISABLE_V 0x00000001U +#define HP_SYSTEM_RETENTION_DISABLE_S 0 + +/** HP_SYSTEM_ROM_TABLE_LOCK_REG register + * Rom-Table lock register + */ +#define HP_SYSTEM_ROM_TABLE_LOCK_REG (DR_REG_HP_SYSTEM_BASE + 0x38) +/** HP_SYSTEM_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0; + * XXXX + */ +#define HP_SYSTEM_ROM_TABLE_LOCK (BIT(0)) +#define HP_SYSTEM_ROM_TABLE_LOCK_M (HP_SYSTEM_ROM_TABLE_LOCK_V << HP_SYSTEM_ROM_TABLE_LOCK_S) +#define HP_SYSTEM_ROM_TABLE_LOCK_V 0x00000001U +#define HP_SYSTEM_ROM_TABLE_LOCK_S 0 + +/** HP_SYSTEM_ROM_TABLE_REG register + * Rom-Table register + */ +#define HP_SYSTEM_ROM_TABLE_REG (DR_REG_HP_SYSTEM_BASE + 0x3c) +/** HP_SYSTEM_ROM_TABLE : R/W; bitpos: [31:0]; default: 0; + * XXXX + */ +#define HP_SYSTEM_ROM_TABLE 0xFFFFFFFFU +#define HP_SYSTEM_ROM_TABLE_M (HP_SYSTEM_ROM_TABLE_V << HP_SYSTEM_ROM_TABLE_S) +#define HP_SYSTEM_ROM_TABLE_V 0xFFFFFFFFU +#define HP_SYSTEM_ROM_TABLE_S 0 + +/** HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG register + * Core Debug runstall configure register + */ +#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x40) +/** HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE : R/W; bitpos: [0]; default: 0; + * Set this field to 1 to enable debug runstall feature between HP-core and LP-core. + */ +#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE (BIT(0)) +#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_M (HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_V << HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_S) +#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_V 0x00000001U +#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_S 0 + +/** HP_SYSTEM_MEM_TEST_CONF_REG register + * MEM_TEST configuration register + */ +#define HP_SYSTEM_MEM_TEST_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x44) +/** HP_SYSTEM_HP_MEM_WPULSE : R/W; bitpos: [2:0]; default: 0; + * This field controls hp system memory WPULSE parameter. + */ +#define HP_SYSTEM_HP_MEM_WPULSE 0x00000007U +#define HP_SYSTEM_HP_MEM_WPULSE_M (HP_SYSTEM_HP_MEM_WPULSE_V << HP_SYSTEM_HP_MEM_WPULSE_S) +#define HP_SYSTEM_HP_MEM_WPULSE_V 0x00000007U +#define HP_SYSTEM_HP_MEM_WPULSE_S 0 +/** HP_SYSTEM_HP_MEM_WA : R/W; bitpos: [5:3]; default: 4; + * This field controls hp system memory WA parameter. + */ +#define HP_SYSTEM_HP_MEM_WA 0x00000007U +#define HP_SYSTEM_HP_MEM_WA_M (HP_SYSTEM_HP_MEM_WA_V << HP_SYSTEM_HP_MEM_WA_S) +#define HP_SYSTEM_HP_MEM_WA_V 0x00000007U +#define HP_SYSTEM_HP_MEM_WA_S 3 +/** HP_SYSTEM_HP_MEM_RA : R/W; bitpos: [7:6]; default: 0; + * This field controls hp system memory RA parameter. + */ +#define HP_SYSTEM_HP_MEM_RA 0x00000003U +#define HP_SYSTEM_HP_MEM_RA_M (HP_SYSTEM_HP_MEM_RA_V << HP_SYSTEM_HP_MEM_RA_S) +#define HP_SYSTEM_HP_MEM_RA_V 0x00000003U +#define HP_SYSTEM_HP_MEM_RA_S 6 + +/** HP_SYSTEM_RND_ECO_REG register + * redcy eco register. + */ +#define HP_SYSTEM_RND_ECO_REG (DR_REG_HP_SYSTEM_BASE + 0x3e0) +/** HP_SYSTEM_REDCY_ENA : W/R; bitpos: [0]; default: 0; + * Only reserved for ECO. + */ +#define HP_SYSTEM_REDCY_ENA (BIT(0)) +#define HP_SYSTEM_REDCY_ENA_M (HP_SYSTEM_REDCY_ENA_V << HP_SYSTEM_REDCY_ENA_S) +#define HP_SYSTEM_REDCY_ENA_V 0x00000001U +#define HP_SYSTEM_REDCY_ENA_S 0 +/** HP_SYSTEM_REDCY_RESULT : RO; bitpos: [1]; default: 0; + * Only reserved for ECO. + */ +#define HP_SYSTEM_REDCY_RESULT (BIT(1)) +#define HP_SYSTEM_REDCY_RESULT_M (HP_SYSTEM_REDCY_RESULT_V << HP_SYSTEM_REDCY_RESULT_S) +#define HP_SYSTEM_REDCY_RESULT_V 0x00000001U +#define HP_SYSTEM_REDCY_RESULT_S 1 + +/** HP_SYSTEM_RND_ECO_LOW_REG register + * redcy eco low register. + */ +#define HP_SYSTEM_RND_ECO_LOW_REG (DR_REG_HP_SYSTEM_BASE + 0x3e4) +/** HP_SYSTEM_REDCY_LOW : W/R; bitpos: [31:0]; default: 0; + * Only reserved for ECO. + */ +#define HP_SYSTEM_REDCY_LOW 0xFFFFFFFFU +#define HP_SYSTEM_REDCY_LOW_M (HP_SYSTEM_REDCY_LOW_V << HP_SYSTEM_REDCY_LOW_S) +#define HP_SYSTEM_REDCY_LOW_V 0xFFFFFFFFU +#define HP_SYSTEM_REDCY_LOW_S 0 + +/** HP_SYSTEM_RND_ECO_HIGH_REG register + * redcy eco high register. + */ +#define HP_SYSTEM_RND_ECO_HIGH_REG (DR_REG_HP_SYSTEM_BASE + 0x3e8) +/** HP_SYSTEM_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295; + * Only reserved for ECO. + */ +#define HP_SYSTEM_REDCY_HIGH 0xFFFFFFFFU +#define HP_SYSTEM_REDCY_HIGH_M (HP_SYSTEM_REDCY_HIGH_V << HP_SYSTEM_REDCY_HIGH_S) +#define HP_SYSTEM_REDCY_HIGH_V 0xFFFFFFFFU +#define HP_SYSTEM_REDCY_HIGH_S 0 + +/** HP_SYSTEM_CLOCK_GATE_REG register + * HP-SYSTEM clock gating configure register + */ +#define HP_SYSTEM_CLOCK_GATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3f8) +/** HP_SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to force on clock gating. + */ +#define HP_SYSTEM_CLK_EN (BIT(0)) +#define HP_SYSTEM_CLK_EN_M (HP_SYSTEM_CLK_EN_V << HP_SYSTEM_CLK_EN_S) +#define HP_SYSTEM_CLK_EN_V 0x00000001U +#define HP_SYSTEM_CLK_EN_S 0 + +/** HP_SYSTEM_DATE_REG register + * Date register. + */ +#define HP_SYSTEM_DATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3fc) +/** HP_SYSTEM_DATE : R/W; bitpos: [27:0]; default: 35676432; + * HP-SYSTEM date information/ HP-SYSTEM version information. + */ +#define HP_SYSTEM_DATE 0x0FFFFFFFU +#define HP_SYSTEM_DATE_M (HP_SYSTEM_DATE_V << HP_SYSTEM_DATE_S) +#define HP_SYSTEM_DATE_V 0x0FFFFFFFU +#define HP_SYSTEM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/hp_system_struct.h b/components/soc/esp32c6/include/soc/hp_system_struct.h new file mode 100644 index 0000000000..b174aa4290 --- /dev/null +++ b/components/soc/esp32c6/include/soc/hp_system_struct.h @@ -0,0 +1,450 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of external_device_encrypt_decrypt_control register + * EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register + */ +typedef union { + struct { + /** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode. + */ + uint32_t enable_spi_manual_encrypt:1; + /** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t enable_download_db_encrypt:1; + /** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0; + * Set this bit as 1 to enable mspi xts auto decrypt in download boot mode. + */ + uint32_t enable_download_g0cb_decrypt:1; + /** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0; + * Set this bit as 1 to enable mspi xts manual encrypt in download boot mode. + */ + uint32_t enable_download_manual_encrypt:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} hp_system_external_device_encrypt_decrypt_control_reg_t; + +/** Type of sram_usage_conf register + * HP memory usage configuration register + */ +typedef union { + struct { + /** cache_usage : HRO; bitpos: [0]; default: 0; + * reserved + */ + uint32_t cache_usage:1; + uint32_t reserved_1:7; + /** sram_usage : R/W; bitpos: [11:8]; default: 0; + * 0: cpu use hp-memory. 1:mac-dump accessing hp-memory. + */ + uint32_t sram_usage:4; + uint32_t reserved_12:4; + /** mac_dump_alloc : R/W; bitpos: [16]; default: 0; + * Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory. + */ + uint32_t mac_dump_alloc:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} hp_system_sram_usage_conf_reg_t; + +/** Type of sec_dpa_conf register + * HP anti-DPA security configuration register + */ +typedef union { + struct { + /** sec_dpa_level : R/W; bitpos: [1:0]; default: 0; + * 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger + * the number, the stronger the ability to resist DPA attacks and the higher the + * security level, but it will increase the computational overhead of the hardware + * crypto-accelerators. Only avaliable if HP_SYSTEM_SEC_DPA_CFG_SEL is 0. + */ + uint32_t sec_dpa_level:2; + /** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0; + * This field is used to select either HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL + * (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYSTEM_SEC_DPA_LEVEL. + */ + uint32_t sec_dpa_cfg_sel:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} hp_system_sec_dpa_conf_reg_t; + +/** Type of sdio_ctrl register + * SDIO Control configuration register + */ +typedef union { + struct { + /** dis_sdio_prob : R/W; bitpos: [0]; default: 1; + * Set this bit as 1 to disable SDIO_PROB function. disable by default. + */ + uint32_t dis_sdio_prob:1; + /** sdio_win_access_en : R/W; bitpos: [1]; default: 1; + * Enable sdio slave to access other peripherals on the chip + */ + uint32_t sdio_win_access_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_system_sdio_ctrl_reg_t; + +/** Type of retention_conf register + * Retention configuration register + */ +typedef union { + struct { + /** retention_disable : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to disable retention function. Not disable by default. + */ + uint32_t retention_disable:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_system_retention_conf_reg_t; + +/** Type of rom_table_lock register + * Rom-Table lock register + */ +typedef union { + struct { + /** rom_table_lock : R/W; bitpos: [0]; default: 0; + * XXXX + */ + uint32_t rom_table_lock:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_system_rom_table_lock_reg_t; + +/** Type of rom_table register + * Rom-Table register + */ +typedef union { + struct { + /** rom_table : R/W; bitpos: [31:0]; default: 0; + * XXXX + */ + uint32_t rom_table:32; + }; + uint32_t val; +} hp_system_rom_table_reg_t; + +/** Type of core_debug_runstall_conf register + * Core Debug runstall configure register + */ +typedef union { + struct { + /** core_debug_runstall_enable : R/W; bitpos: [0]; default: 0; + * Set this field to 1 to enable debug runstall feature between HP-core and LP-core. + */ + uint32_t core_debug_runstall_enable:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_system_core_debug_runstall_conf_reg_t; + +/** Type of mem_test_conf register + * MEM_TEST configuration register + */ +typedef union { + struct { + /** hp_mem_wpulse : R/W; bitpos: [2:0]; default: 0; + * This field controls hp system memory WPULSE parameter. + */ + uint32_t hp_mem_wpulse:3; + /** hp_mem_wa : R/W; bitpos: [5:3]; default: 4; + * This field controls hp system memory WA parameter. + */ + uint32_t hp_mem_wa:3; + /** hp_mem_ra : R/W; bitpos: [7:6]; default: 0; + * This field controls hp system memory RA parameter. + */ + uint32_t hp_mem_ra:2; + uint32_t reserved_8:24; + }; + uint32_t val; +} hp_system_mem_test_conf_reg_t; + +/** Type of clock_gate register + * HP-SYSTEM clock gating configure register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to force on clock gating. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_system_clock_gate_reg_t; + + +/** Group: Timeout Register */ +/** Type of cpu_peri_timeout_conf register + * CPU_PERI_TIMEOUT configuration register + */ +typedef union { + struct { + /** cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; + * Set the timeout threshold for bus access, corresponding to the number of clock + * cycles of the clock domain. + */ + uint32_t cpu_peri_timeout_thres:16; + /** cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; + * Set this bit as 1 to clear timeout interrupt + */ + uint32_t cpu_peri_timeout_int_clear:1; + /** cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; + * Set this bit as 1 to enable timeout protection for accessing cpu peripheral + * registers + */ + uint32_t cpu_peri_timeout_protect_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} hp_system_cpu_peri_timeout_conf_reg_t; + +/** Type of cpu_peri_timeout_addr register + * CPU_PERI_TIMEOUT_ADDR register + */ +typedef union { + struct { + /** cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + * Record the address information of abnormal access + */ + uint32_t cpu_peri_timeout_addr:32; + }; + uint32_t val; +} hp_system_cpu_peri_timeout_addr_reg_t; + +/** Type of cpu_peri_timeout_uid register + * CPU_PERI_TIMEOUT_UID register + */ +typedef union { + struct { + /** cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + * Record master id[4:0] & master permission[6:5] when trigger timeout. This register + * will be cleared after the interrupt is cleared. + */ + uint32_t cpu_peri_timeout_uid:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} hp_system_cpu_peri_timeout_uid_reg_t; + +/** Type of hp_peri_timeout_conf register + * HP_PERI_TIMEOUT configuration register + */ +typedef union { + struct { + /** hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; + * Set the timeout threshold for bus access, corresponding to the number of clock + * cycles of the clock domain. + */ + uint32_t hp_peri_timeout_thres:16; + /** hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; + * Set this bit as 1 to clear timeout interrupt + */ + uint32_t hp_peri_timeout_int_clear:1; + /** hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; + * Set this bit as 1 to enable timeout protection for accessing hp peripheral registers + */ + uint32_t hp_peri_timeout_protect_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} hp_system_hp_peri_timeout_conf_reg_t; + +/** Type of hp_peri_timeout_addr register + * HP_PERI_TIMEOUT_ADDR register + */ +typedef union { + struct { + /** hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + * Record the address information of abnormal access + */ + uint32_t hp_peri_timeout_addr:32; + }; + uint32_t val; +} hp_system_hp_peri_timeout_addr_reg_t; + +/** Type of hp_peri_timeout_uid register + * HP_PERI_TIMEOUT_UID register + */ +typedef union { + struct { + /** hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + * Record master id[4:0] & master permission[6:5] when trigger timeout. This register + * will be cleared after the interrupt is cleared. + */ + uint32_t hp_peri_timeout_uid:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} hp_system_hp_peri_timeout_uid_reg_t; + +/** Type of modem_peri_timeout_conf register + * MODEM_PERI_TIMEOUT configuration register + */ +typedef union { + struct { + /** modem_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; + * Set the timeout threshold for bus access, corresponding to the number of clock + * cycles of the clock domain. + */ + uint32_t modem_peri_timeout_thres:16; + /** modem_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; + * Set this bit as 1 to clear timeout interrupt + */ + uint32_t modem_peri_timeout_int_clear:1; + /** modem_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; + * Set this bit as 1 to enable timeout protection for accessing modem registers + */ + uint32_t modem_peri_timeout_protect_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} hp_system_modem_peri_timeout_conf_reg_t; + +/** Type of modem_peri_timeout_addr register + * MODEM_PERI_TIMEOUT_ADDR register + */ +typedef union { + struct { + /** modem_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + * Record the address information of abnormal access + */ + uint32_t modem_peri_timeout_addr:32; + }; + uint32_t val; +} hp_system_modem_peri_timeout_addr_reg_t; + +/** Type of modem_peri_timeout_uid register + * MODEM_PERI_TIMEOUT_UID register + */ +typedef union { + struct { + /** modem_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + * Record master id[4:0] & master permission[6:5] when trigger timeout. This register + * will be cleared after the interrupt is cleared. + */ + uint32_t modem_peri_timeout_uid:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} hp_system_modem_peri_timeout_uid_reg_t; + + +/** Group: Redcy ECO Registers */ +/** Type of rnd_eco register + * redcy eco register. + */ +typedef union { + struct { + /** redcy_ena : W/R; bitpos: [0]; default: 0; + * Only reserved for ECO. + */ + uint32_t redcy_ena:1; + /** redcy_result : RO; bitpos: [1]; default: 0; + * Only reserved for ECO. + */ + uint32_t redcy_result:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_system_rnd_eco_reg_t; + +/** Type of rnd_eco_low register + * redcy eco low register. + */ +typedef union { + struct { + /** redcy_low : W/R; bitpos: [31:0]; default: 0; + * Only reserved for ECO. + */ + uint32_t redcy_low:32; + }; + uint32_t val; +} hp_system_rnd_eco_low_reg_t; + +/** Type of rnd_eco_high register + * redcy eco high register. + */ +typedef union { + struct { + /** redcy_high : W/R; bitpos: [31:0]; default: 4294967295; + * Only reserved for ECO. + */ + uint32_t redcy_high:32; + }; + uint32_t val; +} hp_system_rnd_eco_high_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35676432; + * HP-SYSTEM date information/ HP-SYSTEM version information. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} hp_system_date_reg_t; + + +typedef struct hp_system_dev_t { + volatile hp_system_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control; + volatile hp_system_sram_usage_conf_reg_t sram_usage_conf; + volatile hp_system_sec_dpa_conf_reg_t sec_dpa_conf; + volatile hp_system_cpu_peri_timeout_conf_reg_t cpu_peri_timeout_conf; + volatile hp_system_cpu_peri_timeout_addr_reg_t cpu_peri_timeout_addr; + volatile hp_system_cpu_peri_timeout_uid_reg_t cpu_peri_timeout_uid; + volatile hp_system_hp_peri_timeout_conf_reg_t hp_peri_timeout_conf; + volatile hp_system_hp_peri_timeout_addr_reg_t hp_peri_timeout_addr; + volatile hp_system_hp_peri_timeout_uid_reg_t hp_peri_timeout_uid; + volatile hp_system_modem_peri_timeout_conf_reg_t modem_peri_timeout_conf; + volatile hp_system_modem_peri_timeout_addr_reg_t modem_peri_timeout_addr; + volatile hp_system_modem_peri_timeout_uid_reg_t modem_peri_timeout_uid; + volatile hp_system_sdio_ctrl_reg_t sdio_ctrl; + volatile hp_system_retention_conf_reg_t retention_conf; + volatile hp_system_rom_table_lock_reg_t rom_table_lock; + volatile hp_system_rom_table_reg_t rom_table; + volatile hp_system_core_debug_runstall_conf_reg_t core_debug_runstall_conf; + volatile hp_system_mem_test_conf_reg_t mem_test_conf; + uint32_t reserved_048[230]; + volatile hp_system_rnd_eco_reg_t rnd_eco; + volatile hp_system_rnd_eco_low_reg_t rnd_eco_low; + volatile hp_system_rnd_eco_high_reg_t rnd_eco_high; + uint32_t reserved_3ec[3]; + volatile hp_system_clock_gate_reg_t clock_gate; + volatile hp_system_date_reg_t date; +} hp_system_dev_t; + +extern hp_system_dev_t HP_SYSTEM; + +#ifndef __cplusplus +_Static_assert(sizeof(hp_system_dev_t) == 0x400, "Invalid size of hp_system_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/hwcrypto_reg.h b/components/soc/esp32c6/include/soc/hwcrypto_reg.h new file mode 100644 index 0000000000..71a680e4ce --- /dev/null +++ b/components/soc/esp32c6/include/soc/hwcrypto_reg.h @@ -0,0 +1,15 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef __HWCRYPTO_REG_H__ +#define __HWCRYPTO_REG_H__ + +#include "soc/aes_reg.h" +#include "soc/ds_reg.h" +#include "soc/hmac_reg.h" +#include "soc/rsa_reg.h" +#include "soc/sha_reg.h" + +#endif diff --git a/components/soc/esp32c6/include/soc/i2c_reg.h b/components/soc/esp32c6/include/soc/i2c_reg.h new file mode 100644 index 0000000000..c92b0a6190 --- /dev/null +++ b/components/soc/esp32c6/include/soc/i2c_reg.h @@ -0,0 +1,1450 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** I2C_SCL_LOW_PERIOD_REG register + * Configures the low level width of the SCL + * Clock + */ +#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0) +/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SCL remains low in master mode, in + * I2C module clock cycles. + */ +#define I2C_SCL_LOW_PERIOD 0x000001FFU +#define I2C_SCL_LOW_PERIOD_M (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S) +#define I2C_SCL_LOW_PERIOD_V 0x000001FFU +#define I2C_SCL_LOW_PERIOD_S 0 + +/** I2C_CTR_REG register + * Transmission setting + */ +#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x4) +/** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0; + * 1: direct output, 0: open drain output. + */ +#define I2C_SDA_FORCE_OUT (BIT(0)) +#define I2C_SDA_FORCE_OUT_M (I2C_SDA_FORCE_OUT_V << I2C_SDA_FORCE_OUT_S) +#define I2C_SDA_FORCE_OUT_V 0x00000001U +#define I2C_SDA_FORCE_OUT_S 0 +/** I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0; + * 1: direct output, 0: open drain output. + */ +#define I2C_SCL_FORCE_OUT (BIT(1)) +#define I2C_SCL_FORCE_OUT_M (I2C_SCL_FORCE_OUT_V << I2C_SCL_FORCE_OUT_S) +#define I2C_SCL_FORCE_OUT_V 0x00000001U +#define I2C_SCL_FORCE_OUT_S 1 +/** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; + * This register is used to select the sample mode. + * 1: sample SDA data on the SCL low level. + * 0: sample SDA data on the SCL high level. + */ +#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) +#define I2C_SAMPLE_SCL_LEVEL_M (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S) +#define I2C_SAMPLE_SCL_LEVEL_V 0x00000001U +#define I2C_SAMPLE_SCL_LEVEL_S 2 +/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; + * This register is used to configure the ACK value that need to sent by master when + * the rx_fifo_cnt has reached the threshold. + */ +#define I2C_RX_FULL_ACK_LEVEL (BIT(3)) +#define I2C_RX_FULL_ACK_LEVEL_M (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S) +#define I2C_RX_FULL_ACK_LEVEL_V 0x00000001U +#define I2C_RX_FULL_ACK_LEVEL_S 3 +/** I2C_MS_MODE : R/W; bitpos: [4]; default: 0; + * Set this bit to configure the module as an I2C Master. Clear this bit to configure + * the + * module as an I2C Slave. + */ +#define I2C_MS_MODE (BIT(4)) +#define I2C_MS_MODE_M (I2C_MS_MODE_V << I2C_MS_MODE_S) +#define I2C_MS_MODE_V 0x00000001U +#define I2C_MS_MODE_S 4 +/** I2C_TRANS_START : WT; bitpos: [5]; default: 0; + * Set this bit to start sending the data in txfifo. + */ +#define I2C_TRANS_START (BIT(5)) +#define I2C_TRANS_START_M (I2C_TRANS_START_V << I2C_TRANS_START_S) +#define I2C_TRANS_START_V 0x00000001U +#define I2C_TRANS_START_S 5 +/** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; + * This bit is used to control the sending mode for data needing to be sent. + * 1: send data from the least significant bit, + * 0: send data from the most significant bit. + */ +#define I2C_TX_LSB_FIRST (BIT(6)) +#define I2C_TX_LSB_FIRST_M (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S) +#define I2C_TX_LSB_FIRST_V 0x00000001U +#define I2C_TX_LSB_FIRST_S 6 +/** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; + * This bit is used to control the storage mode for received data. + * 1: receive data from the least significant bit, + * 0: receive data from the most significant bit. + */ +#define I2C_RX_LSB_FIRST (BIT(7)) +#define I2C_RX_LSB_FIRST_M (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S) +#define I2C_RX_LSB_FIRST_V 0x00000001U +#define I2C_RX_LSB_FIRST_S 7 +/** I2C_CLK_EN : R/W; bitpos: [8]; default: 0; + * Reserved + */ +#define I2C_CLK_EN (BIT(8)) +#define I2C_CLK_EN_M (I2C_CLK_EN_V << I2C_CLK_EN_S) +#define I2C_CLK_EN_V 0x00000001U +#define I2C_CLK_EN_S 8 +/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; + * This is the enable bit for arbitration_lost. + */ +#define I2C_ARBITRATION_EN (BIT(9)) +#define I2C_ARBITRATION_EN_M (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S) +#define I2C_ARBITRATION_EN_V 0x00000001U +#define I2C_ARBITRATION_EN_S 9 +/** I2C_FSM_RST : WT; bitpos: [10]; default: 0; + * This register is used to reset the scl FMS. + */ +#define I2C_FSM_RST (BIT(10)) +#define I2C_FSM_RST_M (I2C_FSM_RST_V << I2C_FSM_RST_S) +#define I2C_FSM_RST_V 0x00000001U +#define I2C_FSM_RST_S 10 +/** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; + * synchronization bit + */ +#define I2C_CONF_UPGATE (BIT(11)) +#define I2C_CONF_UPGATE_M (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S) +#define I2C_CONF_UPGATE_V 0x00000001U +#define I2C_CONF_UPGATE_S 11 +/** I2C_SLV_TX_AUTO_START_EN : R/W; bitpos: [12]; default: 0; + * This is the enable bit for slave to send data automatically + */ +#define I2C_SLV_TX_AUTO_START_EN (BIT(12)) +#define I2C_SLV_TX_AUTO_START_EN_M (I2C_SLV_TX_AUTO_START_EN_V << I2C_SLV_TX_AUTO_START_EN_S) +#define I2C_SLV_TX_AUTO_START_EN_V 0x00000001U +#define I2C_SLV_TX_AUTO_START_EN_S 12 +/** I2C_ADDR_10BIT_RW_CHECK_EN : R/W; bitpos: [13]; default: 0; + * This is the enable bit to check if the r/w bit of 10bit addressing consists with + * I2C protocol + */ +#define I2C_ADDR_10BIT_RW_CHECK_EN (BIT(13)) +#define I2C_ADDR_10BIT_RW_CHECK_EN_M (I2C_ADDR_10BIT_RW_CHECK_EN_V << I2C_ADDR_10BIT_RW_CHECK_EN_S) +#define I2C_ADDR_10BIT_RW_CHECK_EN_V 0x00000001U +#define I2C_ADDR_10BIT_RW_CHECK_EN_S 13 +/** I2C_ADDR_BROADCASTING_EN : R/W; bitpos: [14]; default: 0; + * This is the enable bit to support the 7bit general call function. + */ +#define I2C_ADDR_BROADCASTING_EN (BIT(14)) +#define I2C_ADDR_BROADCASTING_EN_M (I2C_ADDR_BROADCASTING_EN_V << I2C_ADDR_BROADCASTING_EN_S) +#define I2C_ADDR_BROADCASTING_EN_V 0x00000001U +#define I2C_ADDR_BROADCASTING_EN_S 14 + +/** I2C_SR_REG register + * Describe I2C work status. + */ +#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x8) +/** I2C_RESP_REC : RO; bitpos: [0]; default: 0; + * The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + */ +#define I2C_RESP_REC (BIT(0)) +#define I2C_RESP_REC_M (I2C_RESP_REC_V << I2C_RESP_REC_S) +#define I2C_RESP_REC_V 0x00000001U +#define I2C_RESP_REC_S 0 +/** I2C_SLAVE_RW : RO; bitpos: [1]; default: 0; + * When in slave mode, 1: master reads from slave, 0: master writes to slave. + */ +#define I2C_SLAVE_RW (BIT(1)) +#define I2C_SLAVE_RW_M (I2C_SLAVE_RW_V << I2C_SLAVE_RW_S) +#define I2C_SLAVE_RW_V 0x00000001U +#define I2C_SLAVE_RW_S 1 +/** I2C_ARB_LOST : RO; bitpos: [3]; default: 0; + * When the I2C controller loses control of SCL line, this register changes to 1. + */ +#define I2C_ARB_LOST (BIT(3)) +#define I2C_ARB_LOST_M (I2C_ARB_LOST_V << I2C_ARB_LOST_S) +#define I2C_ARB_LOST_V 0x00000001U +#define I2C_ARB_LOST_S 3 +/** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; + * 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. + */ +#define I2C_BUS_BUSY (BIT(4)) +#define I2C_BUS_BUSY_M (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S) +#define I2C_BUS_BUSY_V 0x00000001U +#define I2C_BUS_BUSY_S 4 +/** I2C_SLAVE_ADDRESSED : RO; bitpos: [5]; default: 0; + * When configured as an I2C Slave, and the address sent by the master is + * equal to the address of the slave, then this bit will be of high level. + */ +#define I2C_SLAVE_ADDRESSED (BIT(5)) +#define I2C_SLAVE_ADDRESSED_M (I2C_SLAVE_ADDRESSED_V << I2C_SLAVE_ADDRESSED_S) +#define I2C_SLAVE_ADDRESSED_V 0x00000001U +#define I2C_SLAVE_ADDRESSED_S 5 +/** I2C_RXFIFO_CNT : RO; bitpos: [13:8]; default: 0; + * This field represents the amount of data needed to be sent. + */ +#define I2C_RXFIFO_CNT 0x0000003FU +#define I2C_RXFIFO_CNT_M (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S) +#define I2C_RXFIFO_CNT_V 0x0000003FU +#define I2C_RXFIFO_CNT_S 8 +/** I2C_STRETCH_CAUSE : RO; bitpos: [15:14]; default: 3; + * The cause of stretching SCL low in slave mode. 0: stretching SCL low at the + * beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty + * in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode. + */ +#define I2C_STRETCH_CAUSE 0x00000003U +#define I2C_STRETCH_CAUSE_M (I2C_STRETCH_CAUSE_V << I2C_STRETCH_CAUSE_S) +#define I2C_STRETCH_CAUSE_V 0x00000003U +#define I2C_STRETCH_CAUSE_S 14 +/** I2C_TXFIFO_CNT : RO; bitpos: [23:18]; default: 0; + * This field stores the amount of received data in RAM. + */ +#define I2C_TXFIFO_CNT 0x0000003FU +#define I2C_TXFIFO_CNT_M (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S) +#define I2C_TXFIFO_CNT_V 0x0000003FU +#define I2C_TXFIFO_CNT_S 18 +/** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; + * This field indicates the states of the I2C module state machine. + * 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: + * Wait ACK + */ +#define I2C_SCL_MAIN_STATE_LAST 0x00000007U +#define I2C_SCL_MAIN_STATE_LAST_M (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S) +#define I2C_SCL_MAIN_STATE_LAST_V 0x00000007U +#define I2C_SCL_MAIN_STATE_LAST_S 24 +/** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; + * This field indicates the states of the state machine used to produce SCL. + * 0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop + */ +#define I2C_SCL_STATE_LAST 0x00000007U +#define I2C_SCL_STATE_LAST_M (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S) +#define I2C_SCL_STATE_LAST_V 0x00000007U +#define I2C_SCL_STATE_LAST_S 28 + +/** I2C_TO_REG register + * Setting time out control for receiving data. + */ +#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0xc) +/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; + * This register is used to configure the timeout for receiving a data bit in APB + * clock cycles. + */ +#define I2C_TIME_OUT_VALUE 0x0000001FU +#define I2C_TIME_OUT_VALUE_M (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S) +#define I2C_TIME_OUT_VALUE_V 0x0000001FU +#define I2C_TIME_OUT_VALUE_S 0 +/** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; + * This is the enable bit for time out control. + */ +#define I2C_TIME_OUT_EN (BIT(5)) +#define I2C_TIME_OUT_EN_M (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S) +#define I2C_TIME_OUT_EN_V 0x00000001U +#define I2C_TIME_OUT_EN_S 5 + +/** I2C_SLAVE_ADDR_REG register + * Local slave address setting + */ +#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x10) +/** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0; + * When configured as an I2C Slave, this field is used to configure the slave address. + */ +#define I2C_SLAVE_ADDR 0x00007FFFU +#define I2C_SLAVE_ADDR_M (I2C_SLAVE_ADDR_V << I2C_SLAVE_ADDR_S) +#define I2C_SLAVE_ADDR_V 0x00007FFFU +#define I2C_SLAVE_ADDR_S 0 +/** I2C_ADDR_10BIT_EN : R/W; bitpos: [31]; default: 0; + * This field is used to enable the slave 10-bit addressing mode in master mode. + */ +#define I2C_ADDR_10BIT_EN (BIT(31)) +#define I2C_ADDR_10BIT_EN_M (I2C_ADDR_10BIT_EN_V << I2C_ADDR_10BIT_EN_S) +#define I2C_ADDR_10BIT_EN_V 0x00000001U +#define I2C_ADDR_10BIT_EN_S 31 + +/** I2C_FIFO_ST_REG register + * FIFO status register. + */ +#define I2C_FIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x14) +/** I2C_RXFIFO_RADDR : RO; bitpos: [4:0]; default: 0; + * This is the offset address of the APB reading from rxfifo + */ +#define I2C_RXFIFO_RADDR 0x0000001FU +#define I2C_RXFIFO_RADDR_M (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S) +#define I2C_RXFIFO_RADDR_V 0x0000001FU +#define I2C_RXFIFO_RADDR_S 0 +/** I2C_RXFIFO_WADDR : RO; bitpos: [9:5]; default: 0; + * This is the offset address of i2c module receiving data and writing to rxfifo. + */ +#define I2C_RXFIFO_WADDR 0x0000001FU +#define I2C_RXFIFO_WADDR_M (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S) +#define I2C_RXFIFO_WADDR_V 0x0000001FU +#define I2C_RXFIFO_WADDR_S 5 +/** I2C_TXFIFO_RADDR : RO; bitpos: [14:10]; default: 0; + * This is the offset address of i2c module reading from txfifo. + */ +#define I2C_TXFIFO_RADDR 0x0000001FU +#define I2C_TXFIFO_RADDR_M (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S) +#define I2C_TXFIFO_RADDR_V 0x0000001FU +#define I2C_TXFIFO_RADDR_S 10 +/** I2C_TXFIFO_WADDR : RO; bitpos: [19:15]; default: 0; + * This is the offset address of APB bus writing to txfifo. + */ +#define I2C_TXFIFO_WADDR 0x0000001FU +#define I2C_TXFIFO_WADDR_M (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S) +#define I2C_TXFIFO_WADDR_V 0x0000001FU +#define I2C_TXFIFO_WADDR_S 15 +/** I2C_SLAVE_RW_POINT : RO; bitpos: [29:22]; default: 0; + * The received data in I2C slave mode. + */ +#define I2C_SLAVE_RW_POINT 0x000000FFU +#define I2C_SLAVE_RW_POINT_M (I2C_SLAVE_RW_POINT_V << I2C_SLAVE_RW_POINT_S) +#define I2C_SLAVE_RW_POINT_V 0x000000FFU +#define I2C_SLAVE_RW_POINT_S 22 + +/** I2C_FIFO_CONF_REG register + * FIFO configuration register. + */ +#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x18) +/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [4:0]; default: 11; + * The water mark threshold of rx FIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than + * reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. + */ +#define I2C_RXFIFO_WM_THRHD 0x0000001FU +#define I2C_RXFIFO_WM_THRHD_M (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S) +#define I2C_RXFIFO_WM_THRHD_V 0x0000001FU +#define I2C_RXFIFO_WM_THRHD_S 0 +/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [9:5]; default: 4; + * The water mark threshold of tx FIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than + * reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. + */ +#define I2C_TXFIFO_WM_THRHD 0x0000001FU +#define I2C_TXFIFO_WM_THRHD_M (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S) +#define I2C_TXFIFO_WM_THRHD_V 0x0000001FU +#define I2C_TXFIFO_WM_THRHD_S 5 +/** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0; + * Set this bit to enable APB nonfifo access. + */ +#define I2C_NONFIFO_EN (BIT(10)) +#define I2C_NONFIFO_EN_M (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S) +#define I2C_NONFIFO_EN_V 0x00000001U +#define I2C_NONFIFO_EN_S 10 +/** I2C_FIFO_ADDR_CFG_EN : R/W; bitpos: [11]; default: 0; + * When this bit is set to 1, the byte received after the I2C address byte represents + * the offset address in the I2C Slave RAM. + */ +#define I2C_FIFO_ADDR_CFG_EN (BIT(11)) +#define I2C_FIFO_ADDR_CFG_EN_M (I2C_FIFO_ADDR_CFG_EN_V << I2C_FIFO_ADDR_CFG_EN_S) +#define I2C_FIFO_ADDR_CFG_EN_V 0x00000001U +#define I2C_FIFO_ADDR_CFG_EN_S 11 +/** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; + * Set this bit to reset rx-fifo. + */ +#define I2C_RX_FIFO_RST (BIT(12)) +#define I2C_RX_FIFO_RST_M (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S) +#define I2C_RX_FIFO_RST_V 0x00000001U +#define I2C_RX_FIFO_RST_S 12 +/** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; + * Set this bit to reset tx-fifo. + */ +#define I2C_TX_FIFO_RST (BIT(13)) +#define I2C_TX_FIFO_RST_M (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S) +#define I2C_TX_FIFO_RST_V 0x00000001U +#define I2C_TX_FIFO_RST_S 13 +/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; + * The control enable bit of FIFO pointer in non-fifo access mode. This bit controls + * the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. + */ +#define I2C_FIFO_PRT_EN (BIT(14)) +#define I2C_FIFO_PRT_EN_M (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S) +#define I2C_FIFO_PRT_EN_V 0x00000001U +#define I2C_FIFO_PRT_EN_S 14 + +/** I2C_DATA_REG register + * Rx FIFO read data. + */ +#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x1c) +/** I2C_FIFO_RDATA : HRO; bitpos: [7:0]; default: 0; + * The value of rx FIFO read data. + */ +#define I2C_FIFO_RDATA 0x000000FFU +#define I2C_FIFO_RDATA_M (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S) +#define I2C_FIFO_RDATA_V 0x000000FFU +#define I2C_FIFO_RDATA_S 0 + +/** I2C_INT_RAW_REG register + * Raw interrupt status + */ +#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x20) +/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_RAW (BIT(0)) +#define I2C_RXFIFO_WM_INT_RAW_M (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S) +#define I2C_RXFIFO_WM_INT_RAW_V 0x00000001U +#define I2C_RXFIFO_WM_INT_RAW_S 0 +/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_RAW (BIT(1)) +#define I2C_TXFIFO_WM_INT_RAW_M (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S) +#define I2C_TXFIFO_WM_INT_RAW_V 0x00000001U +#define I2C_TXFIFO_WM_INT_RAW_S 1 +/** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) +#define I2C_RXFIFO_OVF_INT_RAW_M (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S) +#define I2C_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_RAW_S 2 +/** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_RAW (BIT(3)) +#define I2C_END_DETECT_INT_RAW_M (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S) +#define I2C_END_DETECT_INT_RAW_V 0x00000001U +#define I2C_END_DETECT_INT_RAW_S 3 +/** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_RAW_M (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S) +#define I2C_BYTE_TRANS_DONE_INT_RAW_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_RAW_S 4 +/** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_RAW_M (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S) +#define I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_RAW_S 5 +/** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_RAW_M (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S) +#define I2C_MST_TXFIFO_UDF_INT_RAW_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_RAW_S 6 +/** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_RAW_M (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S) +#define I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_RAW_S 7 +/** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_RAW (BIT(8)) +#define I2C_TIME_OUT_INT_RAW_M (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S) +#define I2C_TIME_OUT_INT_RAW_V 0x00000001U +#define I2C_TIME_OUT_INT_RAW_S 8 +/** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_RAW (BIT(9)) +#define I2C_TRANS_START_INT_RAW_M (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S) +#define I2C_TRANS_START_INT_RAW_V 0x00000001U +#define I2C_TRANS_START_INT_RAW_S 9 +/** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_RAW (BIT(10)) +#define I2C_NACK_INT_RAW_M (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S) +#define I2C_NACK_INT_RAW_V 0x00000001U +#define I2C_NACK_INT_RAW_S 10 +/** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_RAW (BIT(11)) +#define I2C_TXFIFO_OVF_INT_RAW_M (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S) +#define I2C_TXFIFO_OVF_INT_RAW_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_RAW_S 11 +/** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_RAW (BIT(12)) +#define I2C_RXFIFO_UDF_INT_RAW_M (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S) +#define I2C_RXFIFO_UDF_INT_RAW_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_RAW_S 12 +/** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_RAW (BIT(13)) +#define I2C_SCL_ST_TO_INT_RAW_M (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S) +#define I2C_SCL_ST_TO_INT_RAW_V 0x00000001U +#define I2C_SCL_ST_TO_INT_RAW_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_RAW_M (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S) +#define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 +/** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt bit for I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_RAW (BIT(15)) +#define I2C_DET_START_INT_RAW_M (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S) +#define I2C_DET_START_INT_RAW_V 0x00000001U +#define I2C_DET_START_INT_RAW_S 15 +/** I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC; bitpos: [16]; default: 0; + * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_RAW (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_RAW_M (I2C_SLAVE_STRETCH_INT_RAW_V << I2C_SLAVE_STRETCH_INT_RAW_S) +#define I2C_SLAVE_STRETCH_INT_RAW_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_RAW_S 16 +/** I2C_GENERAL_CALL_INT_RAW : R/SS/WTC; bitpos: [17]; default: 0; + * The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_RAW (BIT(17)) +#define I2C_GENERAL_CALL_INT_RAW_M (I2C_GENERAL_CALL_INT_RAW_V << I2C_GENERAL_CALL_INT_RAW_S) +#define I2C_GENERAL_CALL_INT_RAW_V 0x00000001U +#define I2C_GENERAL_CALL_INT_RAW_S 17 +/** I2C_SLAVE_ADDR_UNMATCH_INT_RAW : R/SS/WTC; bitpos: [18]; default: 0; + * The raw interrupt bit for I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + */ +#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW (BIT(18)) +#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_M (I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V << I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S) +#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V 0x00000001U +#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S 18 + +/** I2C_INT_CLR_REG register + * Interrupt clear bits + */ +#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x24) +/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_CLR (BIT(0)) +#define I2C_RXFIFO_WM_INT_CLR_M (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S) +#define I2C_RXFIFO_WM_INT_CLR_V 0x00000001U +#define I2C_RXFIFO_WM_INT_CLR_S 0 +/** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_CLR (BIT(1)) +#define I2C_TXFIFO_WM_INT_CLR_M (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S) +#define I2C_TXFIFO_WM_INT_CLR_V 0x00000001U +#define I2C_TXFIFO_WM_INT_CLR_S 1 +/** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) +#define I2C_RXFIFO_OVF_INT_CLR_M (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S) +#define I2C_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_CLR_S 2 +/** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_CLR (BIT(3)) +#define I2C_END_DETECT_INT_CLR_M (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S) +#define I2C_END_DETECT_INT_CLR_V 0x00000001U +#define I2C_END_DETECT_INT_CLR_S 3 +/** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_CLR_M (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S) +#define I2C_BYTE_TRANS_DONE_INT_CLR_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_CLR_S 4 +/** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_CLR_M (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S) +#define I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_CLR_S 5 +/** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_CLR_M (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S) +#define I2C_MST_TXFIFO_UDF_INT_CLR_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_CLR_S 6 +/** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_CLR_M (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S) +#define I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_CLR_S 7 +/** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_CLR (BIT(8)) +#define I2C_TIME_OUT_INT_CLR_M (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S) +#define I2C_TIME_OUT_INT_CLR_V 0x00000001U +#define I2C_TIME_OUT_INT_CLR_S 8 +/** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_CLR (BIT(9)) +#define I2C_TRANS_START_INT_CLR_M (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S) +#define I2C_TRANS_START_INT_CLR_V 0x00000001U +#define I2C_TRANS_START_INT_CLR_S 9 +/** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_CLR (BIT(10)) +#define I2C_NACK_INT_CLR_M (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S) +#define I2C_NACK_INT_CLR_V 0x00000001U +#define I2C_NACK_INT_CLR_S 10 +/** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_CLR (BIT(11)) +#define I2C_TXFIFO_OVF_INT_CLR_M (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S) +#define I2C_TXFIFO_OVF_INT_CLR_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_CLR_S 11 +/** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_CLR (BIT(12)) +#define I2C_RXFIFO_UDF_INT_CLR_M (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S) +#define I2C_RXFIFO_UDF_INT_CLR_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_CLR_S 12 +/** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_CLR (BIT(13)) +#define I2C_SCL_ST_TO_INT_CLR_M (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S) +#define I2C_SCL_ST_TO_INT_CLR_V 0x00000001U +#define I2C_SCL_ST_TO_INT_CLR_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_CLR_M (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S) +#define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 +/** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_CLR (BIT(15)) +#define I2C_DET_START_INT_CLR_M (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S) +#define I2C_DET_START_INT_CLR_V 0x00000001U +#define I2C_DET_START_INT_CLR_S 15 +/** I2C_SLAVE_STRETCH_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_CLR (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_CLR_M (I2C_SLAVE_STRETCH_INT_CLR_V << I2C_SLAVE_STRETCH_INT_CLR_S) +#define I2C_SLAVE_STRETCH_INT_CLR_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_CLR_S 16 +/** I2C_GENERAL_CALL_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_CLR (BIT(17)) +#define I2C_GENERAL_CALL_INT_CLR_M (I2C_GENERAL_CALL_INT_CLR_V << I2C_GENERAL_CALL_INT_CLR_S) +#define I2C_GENERAL_CALL_INT_CLR_V 0x00000001U +#define I2C_GENERAL_CALL_INT_CLR_S 17 +/** I2C_SLAVE_ADDR_UNMATCH_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + */ +#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR (BIT(18)) +#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_M (I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V << I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S) +#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V 0x00000001U +#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S 18 + +/** I2C_INT_ENA_REG register + * Interrupt enable bits + */ +#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x28) +/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_ENA (BIT(0)) +#define I2C_RXFIFO_WM_INT_ENA_M (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S) +#define I2C_RXFIFO_WM_INT_ENA_V 0x00000001U +#define I2C_RXFIFO_WM_INT_ENA_S 0 +/** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_ENA (BIT(1)) +#define I2C_TXFIFO_WM_INT_ENA_M (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S) +#define I2C_TXFIFO_WM_INT_ENA_V 0x00000001U +#define I2C_TXFIFO_WM_INT_ENA_S 1 +/** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ENA_M (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S) +#define I2C_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_ENA_S 2 +/** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_ENA (BIT(3)) +#define I2C_END_DETECT_INT_ENA_M (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S) +#define I2C_END_DETECT_INT_ENA_V 0x00000001U +#define I2C_END_DETECT_INT_ENA_S 3 +/** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ENA_M (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S) +#define I2C_BYTE_TRANS_DONE_INT_ENA_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_ENA_S 4 +/** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ENA_M (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S) +#define I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_ENA_S 5 +/** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ENA_M (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S) +#define I2C_MST_TXFIFO_UDF_INT_ENA_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_ENA_S 6 +/** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ENA_M (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S) +#define I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_ENA_S 7 +/** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_ENA (BIT(8)) +#define I2C_TIME_OUT_INT_ENA_M (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S) +#define I2C_TIME_OUT_INT_ENA_V 0x00000001U +#define I2C_TIME_OUT_INT_ENA_S 8 +/** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_ENA (BIT(9)) +#define I2C_TRANS_START_INT_ENA_M (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S) +#define I2C_TRANS_START_INT_ENA_V 0x00000001U +#define I2C_TRANS_START_INT_ENA_S 9 +/** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_ENA (BIT(10)) +#define I2C_NACK_INT_ENA_M (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S) +#define I2C_NACK_INT_ENA_V 0x00000001U +#define I2C_NACK_INT_ENA_S 10 +/** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_ENA (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ENA_M (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S) +#define I2C_TXFIFO_OVF_INT_ENA_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_ENA_S 11 +/** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_ENA (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ENA_M (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S) +#define I2C_RXFIFO_UDF_INT_ENA_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_ENA_S 12 +/** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_ENA (BIT(13)) +#define I2C_SCL_ST_TO_INT_ENA_M (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S) +#define I2C_SCL_ST_TO_INT_ENA_V 0x00000001U +#define I2C_SCL_ST_TO_INT_ENA_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ENA_M (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S) +#define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 +/** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_ENA (BIT(15)) +#define I2C_DET_START_INT_ENA_M (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S) +#define I2C_DET_START_INT_ENA_V 0x00000001U +#define I2C_DET_START_INT_ENA_S 15 +/** I2C_SLAVE_STRETCH_INT_ENA : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_ENA (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ENA_M (I2C_SLAVE_STRETCH_INT_ENA_V << I2C_SLAVE_STRETCH_INT_ENA_S) +#define I2C_SLAVE_STRETCH_INT_ENA_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_ENA_S 16 +/** I2C_GENERAL_CALL_INT_ENA : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_ENA (BIT(17)) +#define I2C_GENERAL_CALL_INT_ENA_M (I2C_GENERAL_CALL_INT_ENA_V << I2C_GENERAL_CALL_INT_ENA_S) +#define I2C_GENERAL_CALL_INT_ENA_V 0x00000001U +#define I2C_GENERAL_CALL_INT_ENA_S 17 +/** I2C_SLAVE_ADDR_UNMATCH_INT_ENA : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + */ +#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA (BIT(18)) +#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_M (I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V << I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S) +#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V 0x00000001U +#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S 18 + +/** I2C_INT_STATUS_REG register + * Status of captured I2C communication events + */ +#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x2c) +/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_ST (BIT(0)) +#define I2C_RXFIFO_WM_INT_ST_M (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S) +#define I2C_RXFIFO_WM_INT_ST_V 0x00000001U +#define I2C_RXFIFO_WM_INT_ST_S 0 +/** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_ST (BIT(1)) +#define I2C_TXFIFO_WM_INT_ST_M (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S) +#define I2C_TXFIFO_WM_INT_ST_V 0x00000001U +#define I2C_TXFIFO_WM_INT_ST_S 1 +/** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ST_M (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S) +#define I2C_RXFIFO_OVF_INT_ST_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_ST_S 2 +/** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_ST (BIT(3)) +#define I2C_END_DETECT_INT_ST_M (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S) +#define I2C_END_DETECT_INT_ST_V 0x00000001U +#define I2C_END_DETECT_INT_ST_S 3 +/** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ST_M (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S) +#define I2C_BYTE_TRANS_DONE_INT_ST_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_ST_S 4 +/** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ST_M (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S) +#define I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_ST_S 5 +/** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ST_M (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S) +#define I2C_MST_TXFIFO_UDF_INT_ST_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_ST_S 6 +/** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ST_M (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S) +#define I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_ST_S 7 +/** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_ST (BIT(8)) +#define I2C_TIME_OUT_INT_ST_M (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S) +#define I2C_TIME_OUT_INT_ST_V 0x00000001U +#define I2C_TIME_OUT_INT_ST_S 8 +/** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_ST (BIT(9)) +#define I2C_TRANS_START_INT_ST_M (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S) +#define I2C_TRANS_START_INT_ST_V 0x00000001U +#define I2C_TRANS_START_INT_ST_S 9 +/** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_ST (BIT(10)) +#define I2C_NACK_INT_ST_M (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S) +#define I2C_NACK_INT_ST_V 0x00000001U +#define I2C_NACK_INT_ST_S 10 +/** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_ST (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ST_M (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S) +#define I2C_TXFIFO_OVF_INT_ST_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_ST_S 11 +/** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_ST (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ST_M (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S) +#define I2C_RXFIFO_UDF_INT_ST_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_ST_S 12 +/** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_ST (BIT(13)) +#define I2C_SCL_ST_TO_INT_ST_M (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S) +#define I2C_SCL_ST_TO_INT_ST_V 0x00000001U +#define I2C_SCL_ST_TO_INT_ST_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ST_M (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S) +#define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_ST_S 14 +/** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_ST (BIT(15)) +#define I2C_DET_START_INT_ST_M (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S) +#define I2C_DET_START_INT_ST_V 0x00000001U +#define I2C_DET_START_INT_ST_S 15 +/** I2C_SLAVE_STRETCH_INT_ST : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_ST (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ST_M (I2C_SLAVE_STRETCH_INT_ST_V << I2C_SLAVE_STRETCH_INT_ST_S) +#define I2C_SLAVE_STRETCH_INT_ST_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_ST_S 16 +/** I2C_GENERAL_CALL_INT_ST : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_ST (BIT(17)) +#define I2C_GENERAL_CALL_INT_ST_M (I2C_GENERAL_CALL_INT_ST_V << I2C_GENERAL_CALL_INT_ST_S) +#define I2C_GENERAL_CALL_INT_ST_V 0x00000001U +#define I2C_GENERAL_CALL_INT_ST_S 17 +/** I2C_SLAVE_ADDR_UNMATCH_INT_ST : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + */ +#define I2C_SLAVE_ADDR_UNMATCH_INT_ST (BIT(18)) +#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_M (I2C_SLAVE_ADDR_UNMATCH_INT_ST_V << I2C_SLAVE_ADDR_UNMATCH_INT_ST_S) +#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_V 0x00000001U +#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_S 18 + +/** I2C_SDA_HOLD_REG register + * Configures the hold time after a negative SCL edge. + */ +#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x30) +/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure the time to hold the data after the negative + * edge of SCL, in I2C module clock cycles. + */ +#define I2C_SDA_HOLD_TIME 0x000001FFU +#define I2C_SDA_HOLD_TIME_M (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S) +#define I2C_SDA_HOLD_TIME_V 0x000001FFU +#define I2C_SDA_HOLD_TIME_S 0 + +/** I2C_SDA_SAMPLE_REG register + * Configures the sample time after a positive SCL edge. + */ +#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x34) +/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SDA is sampled, in I2C module clock + * cycles. + */ +#define I2C_SDA_SAMPLE_TIME 0x000001FFU +#define I2C_SDA_SAMPLE_TIME_M (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S) +#define I2C_SDA_SAMPLE_TIME_V 0x000001FFU +#define I2C_SDA_SAMPLE_TIME_S 0 + +/** I2C_SCL_HIGH_PERIOD_REG register + * Configures the high level width of SCL + */ +#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x38) +/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SCL remains high in master mode, in + * I2C module clock cycles. + */ +#define I2C_SCL_HIGH_PERIOD 0x000001FFU +#define I2C_SCL_HIGH_PERIOD_M (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S) +#define I2C_SCL_HIGH_PERIOD_V 0x000001FFU +#define I2C_SCL_HIGH_PERIOD_S 0 +/** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; + * This register is used to configure for the SCL_FSM's waiting period for SCL high + * level in master mode, in I2C module clock cycles. + */ +#define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU +#define I2C_SCL_WAIT_HIGH_PERIOD_M (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S) +#define I2C_SCL_WAIT_HIGH_PERIOD_V 0x0000007FU +#define I2C_SCL_WAIT_HIGH_PERIOD_S 9 + +/** I2C_SCL_START_HOLD_REG register + * Configures the delay between the SDA and SCL negative edge for a start condition + */ +#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x40) +/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the negative edge + * of SDA and the negative edge of SCL for a START condition, in I2C module clock + * cycles. + */ +#define I2C_SCL_START_HOLD_TIME 0x000001FFU +#define I2C_SCL_START_HOLD_TIME_M (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S) +#define I2C_SCL_START_HOLD_TIME_V 0x000001FFU +#define I2C_SCL_START_HOLD_TIME_S 0 + +/** I2C_SCL_RSTART_SETUP_REG register + * Configures the delay between the positive + * edge of SCL and the negative edge of SDA + */ +#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x44) +/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the positive + * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module + * clock cycles. + */ +#define I2C_SCL_RSTART_SETUP_TIME 0x000001FFU +#define I2C_SCL_RSTART_SETUP_TIME_M (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S) +#define I2C_SCL_RSTART_SETUP_TIME_V 0x000001FFU +#define I2C_SCL_RSTART_SETUP_TIME_S 0 + +/** I2C_SCL_STOP_HOLD_REG register + * Configures the delay after the SCL clock + * edge for a stop condition + */ +#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x48) +/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the delay after the STOP condition, + * in I2C module clock cycles. + */ +#define I2C_SCL_STOP_HOLD_TIME 0x000001FFU +#define I2C_SCL_STOP_HOLD_TIME_M (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S) +#define I2C_SCL_STOP_HOLD_TIME_V 0x000001FFU +#define I2C_SCL_STOP_HOLD_TIME_S 0 + +/** I2C_SCL_STOP_SETUP_REG register + * Configures the delay between the SDA and + * SCL positive edge for a stop condition + */ +#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x4c) +/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the positive edge + * of SCL and the positive edge of SDA, in I2C module clock cycles. + */ +#define I2C_SCL_STOP_SETUP_TIME 0x000001FFU +#define I2C_SCL_STOP_SETUP_TIME_M (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S) +#define I2C_SCL_STOP_SETUP_TIME_V 0x000001FFU +#define I2C_SCL_STOP_SETUP_TIME_S 0 + +/** I2C_FILTER_CFG_REG register + * SCL and SDA filter configuration register + */ +#define I2C_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x50) +/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0; + * When a pulse on the SCL input has smaller width than this register value + * in I2C module clock cycles, the I2C controller will ignore that pulse. + */ +#define I2C_SCL_FILTER_THRES 0x0000000FU +#define I2C_SCL_FILTER_THRES_M (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S) +#define I2C_SCL_FILTER_THRES_V 0x0000000FU +#define I2C_SCL_FILTER_THRES_S 0 +/** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0; + * When a pulse on the SDA input has smaller width than this register value + * in I2C module clock cycles, the I2C controller will ignore that pulse. + */ +#define I2C_SDA_FILTER_THRES 0x0000000FU +#define I2C_SDA_FILTER_THRES_M (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S) +#define I2C_SDA_FILTER_THRES_V 0x0000000FU +#define I2C_SDA_FILTER_THRES_S 4 +/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; + * This is the filter enable bit for SCL. + */ +#define I2C_SCL_FILTER_EN (BIT(8)) +#define I2C_SCL_FILTER_EN_M (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S) +#define I2C_SCL_FILTER_EN_V 0x00000001U +#define I2C_SCL_FILTER_EN_S 8 +/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; + * This is the filter enable bit for SDA. + */ +#define I2C_SDA_FILTER_EN (BIT(9)) +#define I2C_SDA_FILTER_EN_M (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S) +#define I2C_SDA_FILTER_EN_V 0x00000001U +#define I2C_SDA_FILTER_EN_S 9 + +/** I2C_CLK_CONF_REG register + * I2C CLK configuration register + */ +#define I2C_CLK_CONF_REG(i) (REG_I2C_BASE(i) + 0x54) +/** I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * the integral part of the fractional divisor for i2c module + */ +#define I2C_SCLK_DIV_NUM 0x000000FFU +#define I2C_SCLK_DIV_NUM_M (I2C_SCLK_DIV_NUM_V << I2C_SCLK_DIV_NUM_S) +#define I2C_SCLK_DIV_NUM_V 0x000000FFU +#define I2C_SCLK_DIV_NUM_S 0 +/** I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0; + * the numerator of the fractional part of the fractional divisor for i2c module + */ +#define I2C_SCLK_DIV_A 0x0000003FU +#define I2C_SCLK_DIV_A_M (I2C_SCLK_DIV_A_V << I2C_SCLK_DIV_A_S) +#define I2C_SCLK_DIV_A_V 0x0000003FU +#define I2C_SCLK_DIV_A_S 8 +/** I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0; + * the denominator of the fractional part of the fractional divisor for i2c module + */ +#define I2C_SCLK_DIV_B 0x0000003FU +#define I2C_SCLK_DIV_B_M (I2C_SCLK_DIV_B_V << I2C_SCLK_DIV_B_S) +#define I2C_SCLK_DIV_B_V 0x0000003FU +#define I2C_SCLK_DIV_B_S 14 +/** I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; + * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + */ +#define I2C_SCLK_SEL (BIT(20)) +#define I2C_SCLK_SEL_M (I2C_SCLK_SEL_V << I2C_SCLK_SEL_S) +#define I2C_SCLK_SEL_V 0x00000001U +#define I2C_SCLK_SEL_S 20 +/** I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1; + * The clock switch for i2c module + */ +#define I2C_SCLK_ACTIVE (BIT(21)) +#define I2C_SCLK_ACTIVE_M (I2C_SCLK_ACTIVE_V << I2C_SCLK_ACTIVE_S) +#define I2C_SCLK_ACTIVE_V 0x00000001U +#define I2C_SCLK_ACTIVE_S 21 + +/** I2C_COMD0_REG register + * I2C command register 0 + */ +#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x58) +/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 0. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND0 0x00003FFFU +#define I2C_COMMAND0_M (I2C_COMMAND0_V << I2C_COMMAND0_S) +#define I2C_COMMAND0_V 0x00003FFFU +#define I2C_COMMAND0_S 0 +/** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 0 is done in I2C Master mode, this bit changes to high + * level. + */ +#define I2C_COMMAND0_DONE (BIT(31)) +#define I2C_COMMAND0_DONE_M (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S) +#define I2C_COMMAND0_DONE_V 0x00000001U +#define I2C_COMMAND0_DONE_S 31 + +/** I2C_COMD1_REG register + * I2C command register 1 + */ +#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x5c) +/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 1. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND1 0x00003FFFU +#define I2C_COMMAND1_M (I2C_COMMAND1_V << I2C_COMMAND1_S) +#define I2C_COMMAND1_V 0x00003FFFU +#define I2C_COMMAND1_S 0 +/** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 1 is done in I2C Master mode, this bit changes to high + * level. + */ +#define I2C_COMMAND1_DONE (BIT(31)) +#define I2C_COMMAND1_DONE_M (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S) +#define I2C_COMMAND1_DONE_V 0x00000001U +#define I2C_COMMAND1_DONE_S 31 + +/** I2C_COMD2_REG register + * I2C command register 2 + */ +#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x60) +/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 2. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND2 0x00003FFFU +#define I2C_COMMAND2_M (I2C_COMMAND2_V << I2C_COMMAND2_S) +#define I2C_COMMAND2_V 0x00003FFFU +#define I2C_COMMAND2_S 0 +/** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 2 is done in I2C Master mode, this bit changes to high + * Level. + */ +#define I2C_COMMAND2_DONE (BIT(31)) +#define I2C_COMMAND2_DONE_M (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S) +#define I2C_COMMAND2_DONE_V 0x00000001U +#define I2C_COMMAND2_DONE_S 31 + +/** I2C_COMD3_REG register + * I2C command register 3 + */ +#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x64) +/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 3. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND3 0x00003FFFU +#define I2C_COMMAND3_M (I2C_COMMAND3_V << I2C_COMMAND3_S) +#define I2C_COMMAND3_V 0x00003FFFU +#define I2C_COMMAND3_S 0 +/** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 3 is done in I2C Master mode, this bit changes to high + * level. + */ +#define I2C_COMMAND3_DONE (BIT(31)) +#define I2C_COMMAND3_DONE_M (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S) +#define I2C_COMMAND3_DONE_V 0x00000001U +#define I2C_COMMAND3_DONE_S 31 + +/** I2C_COMD4_REG register + * I2C command register 4 + */ +#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x68) +/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 4. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND4 0x00003FFFU +#define I2C_COMMAND4_M (I2C_COMMAND4_V << I2C_COMMAND4_S) +#define I2C_COMMAND4_V 0x00003FFFU +#define I2C_COMMAND4_S 0 +/** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 4 is done in I2C Master mode, this bit changes to high + * level. + */ +#define I2C_COMMAND4_DONE (BIT(31)) +#define I2C_COMMAND4_DONE_M (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S) +#define I2C_COMMAND4_DONE_V 0x00000001U +#define I2C_COMMAND4_DONE_S 31 + +/** I2C_COMD5_REG register + * I2C command register 5 + */ +#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x6c) +/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 5. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND5 0x00003FFFU +#define I2C_COMMAND5_M (I2C_COMMAND5_V << I2C_COMMAND5_S) +#define I2C_COMMAND5_V 0x00003FFFU +#define I2C_COMMAND5_S 0 +/** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 5 is done in I2C Master mode, this bit changes to high level. + */ +#define I2C_COMMAND5_DONE (BIT(31)) +#define I2C_COMMAND5_DONE_M (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S) +#define I2C_COMMAND5_DONE_V 0x00000001U +#define I2C_COMMAND5_DONE_S 31 + +/** I2C_COMD6_REG register + * I2C command register 6 + */ +#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x70) +/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 6. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND6 0x00003FFFU +#define I2C_COMMAND6_M (I2C_COMMAND6_V << I2C_COMMAND6_S) +#define I2C_COMMAND6_V 0x00003FFFU +#define I2C_COMMAND6_S 0 +/** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 6 is done in I2C Master mode, this bit changes to high level. + */ +#define I2C_COMMAND6_DONE (BIT(31)) +#define I2C_COMMAND6_DONE_M (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S) +#define I2C_COMMAND6_DONE_V 0x00000001U +#define I2C_COMMAND6_DONE_S 31 + +/** I2C_COMD7_REG register + * I2C command register 7 + */ +#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x74) +/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 7. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND7 0x00003FFFU +#define I2C_COMMAND7_M (I2C_COMMAND7_V << I2C_COMMAND7_S) +#define I2C_COMMAND7_V 0x00003FFFU +#define I2C_COMMAND7_S 0 +/** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 7 is done in I2C Master mode, this bit changes to high level. + */ +#define I2C_COMMAND7_DONE (BIT(31)) +#define I2C_COMMAND7_DONE_M (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S) +#define I2C_COMMAND7_DONE_V 0x00000001U +#define I2C_COMMAND7_DONE_S 31 + +/** I2C_SCL_ST_TIME_OUT_REG register + * SCL status time out register + */ +#define I2C_SCL_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x78) +/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; + * The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + */ +#define I2C_SCL_ST_TO_I2C 0x0000001FU +#define I2C_SCL_ST_TO_I2C_M (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S) +#define I2C_SCL_ST_TO_I2C_V 0x0000001FU +#define I2C_SCL_ST_TO_I2C_S 0 + +/** I2C_SCL_MAIN_ST_TIME_OUT_REG register + * SCL main status time out register + */ +#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x7c) +/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; + * The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more + * than 23 + */ +#define I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU +#define I2C_SCL_MAIN_ST_TO_I2C_M (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S) +#define I2C_SCL_MAIN_ST_TO_I2C_V 0x0000001FU +#define I2C_SCL_MAIN_ST_TO_I2C_S 0 + +/** I2C_SCL_SP_CONF_REG register + * Power configuration register + */ +#define I2C_SCL_SP_CONF_REG(i) (REG_I2C_BASE(i) + 0x80) +/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0; + * When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses + * equals to reg_scl_rst_slv_num[4:0]. + */ +#define I2C_SCL_RST_SLV_EN (BIT(0)) +#define I2C_SCL_RST_SLV_EN_M (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S) +#define I2C_SCL_RST_SLV_EN_V 0x00000001U +#define I2C_SCL_RST_SLV_EN_S 0 +/** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; + * Configure the pulses of SCL generated in I2C master mode. Valid when + * reg_scl_rst_slv_en is 1. + */ +#define I2C_SCL_RST_SLV_NUM 0x0000001FU +#define I2C_SCL_RST_SLV_NUM_M (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S) +#define I2C_SCL_RST_SLV_NUM_V 0x0000001FU +#define I2C_SCL_RST_SLV_NUM_S 1 +/** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; + * The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power + * down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. + */ +#define I2C_SCL_PD_EN (BIT(6)) +#define I2C_SCL_PD_EN_M (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S) +#define I2C_SCL_PD_EN_V 0x00000001U +#define I2C_SCL_PD_EN_S 6 +/** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; + * The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power + * down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. + */ +#define I2C_SDA_PD_EN (BIT(7)) +#define I2C_SDA_PD_EN_M (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S) +#define I2C_SDA_PD_EN_V 0x00000001U +#define I2C_SDA_PD_EN_S 7 + +/** I2C_SCL_STRETCH_CONF_REG register + * Set SCL stretch of I2C slave + */ +#define I2C_SCL_STRETCH_CONF_REG(i) (REG_I2C_BASE(i) + 0x84) +/** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0; + * Configure the period of I2C slave stretching SCL line. + */ +#define I2C_STRETCH_PROTECT_NUM 0x000003FFU +#define I2C_STRETCH_PROTECT_NUM_M (I2C_STRETCH_PROTECT_NUM_V << I2C_STRETCH_PROTECT_NUM_S) +#define I2C_STRETCH_PROTECT_NUM_V 0x000003FFU +#define I2C_STRETCH_PROTECT_NUM_S 0 +/** I2C_SLAVE_SCL_STRETCH_EN : R/W; bitpos: [10]; default: 0; + * The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL + * output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch + * event happens. The stretch cause can be seen in reg_stretch_cause. + */ +#define I2C_SLAVE_SCL_STRETCH_EN (BIT(10)) +#define I2C_SLAVE_SCL_STRETCH_EN_M (I2C_SLAVE_SCL_STRETCH_EN_V << I2C_SLAVE_SCL_STRETCH_EN_S) +#define I2C_SLAVE_SCL_STRETCH_EN_V 0x00000001U +#define I2C_SLAVE_SCL_STRETCH_EN_S 10 +/** I2C_SLAVE_SCL_STRETCH_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the I2C slave SCL stretch function. + */ +#define I2C_SLAVE_SCL_STRETCH_CLR (BIT(11)) +#define I2C_SLAVE_SCL_STRETCH_CLR_M (I2C_SLAVE_SCL_STRETCH_CLR_V << I2C_SLAVE_SCL_STRETCH_CLR_S) +#define I2C_SLAVE_SCL_STRETCH_CLR_V 0x00000001U +#define I2C_SLAVE_SCL_STRETCH_CLR_S 11 +/** I2C_SLAVE_BYTE_ACK_CTL_EN : R/W; bitpos: [12]; default: 0; + * The enable bit for slave to control ACK level function. + */ +#define I2C_SLAVE_BYTE_ACK_CTL_EN (BIT(12)) +#define I2C_SLAVE_BYTE_ACK_CTL_EN_M (I2C_SLAVE_BYTE_ACK_CTL_EN_V << I2C_SLAVE_BYTE_ACK_CTL_EN_S) +#define I2C_SLAVE_BYTE_ACK_CTL_EN_V 0x00000001U +#define I2C_SLAVE_BYTE_ACK_CTL_EN_S 12 +/** I2C_SLAVE_BYTE_ACK_LVL : R/W; bitpos: [13]; default: 0; + * Set the ACK level when slave controlling ACK level function enables. + */ +#define I2C_SLAVE_BYTE_ACK_LVL (BIT(13)) +#define I2C_SLAVE_BYTE_ACK_LVL_M (I2C_SLAVE_BYTE_ACK_LVL_V << I2C_SLAVE_BYTE_ACK_LVL_S) +#define I2C_SLAVE_BYTE_ACK_LVL_V 0x00000001U +#define I2C_SLAVE_BYTE_ACK_LVL_S 13 + +/** I2C_DATE_REG register + * Version register + */ +#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0xf8) +/** I2C_DATE : R/W; bitpos: [31:0]; default: 35656050; + * This is the the version register. + */ +#define I2C_DATE 0xFFFFFFFFU +#define I2C_DATE_M (I2C_DATE_V << I2C_DATE_S) +#define I2C_DATE_V 0xFFFFFFFFU +#define I2C_DATE_S 0 + +/** I2C_TXFIFO_START_ADDR_REG register + * I2C TXFIFO base address register + */ +#define I2C_TXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x100) +/** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; + * This is the I2C txfifo first address. + */ +#define I2C_TXFIFO_START_ADDR 0xFFFFFFFFU +#define I2C_TXFIFO_START_ADDR_M (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S) +#define I2C_TXFIFO_START_ADDR_V 0xFFFFFFFFU +#define I2C_TXFIFO_START_ADDR_S 0 + +/** I2C_RXFIFO_START_ADDR_REG register + * I2C RXFIFO base address register + */ +#define I2C_RXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x180) +/** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; + * This is the I2C rxfifo first address. + */ +#define I2C_RXFIFO_START_ADDR 0xFFFFFFFFU +#define I2C_RXFIFO_START_ADDR_M (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S) +#define I2C_RXFIFO_START_ADDR_V 0xFFFFFFFFU +#define I2C_RXFIFO_START_ADDR_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/i2c_struct.h b/components/soc/esp32c6/include/soc/i2c_struct.h new file mode 100644 index 0000000000..e1a03349f4 --- /dev/null +++ b/components/soc/esp32c6/include/soc/i2c_struct.h @@ -0,0 +1,1023 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Timing registers */ +/** Type of scl_low_period register + * Configures the low level width of the SCL + * Clock + */ +typedef union { + struct { + /** scl_low_period : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SCL remains low in master mode, in + * I2C module clock cycles. + */ + uint32_t scl_low_period:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_low_period_reg_t; + +/** Type of sda_hold register + * Configures the hold time after a negative SCL edge. + */ +typedef union { + struct { + /** sda_hold_time : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure the time to hold the data after the negative + * edge of SCL, in I2C module clock cycles. + */ + uint32_t sda_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_sda_hold_reg_t; + +/** Type of sda_sample register + * Configures the sample time after a positive SCL edge. + */ +typedef union { + struct { + /** sda_sample_time : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SDA is sampled, in I2C module clock + * cycles. + */ + uint32_t sda_sample_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_sda_sample_reg_t; + +/** Type of scl_high_period register + * Configures the high level width of SCL + */ +typedef union { + struct { + /** scl_high_period : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SCL remains high in master mode, in + * I2C module clock cycles. + */ + uint32_t scl_high_period:9; + /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0; + * This register is used to configure for the SCL_FSM's waiting period for SCL high + * level in master mode, in I2C module clock cycles. + */ + uint32_t scl_wait_high_period:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} i2c_scl_high_period_reg_t; + +/** Type of scl_start_hold register + * Configures the delay between the SDA and SCL negative edge for a start condition + */ +typedef union { + struct { + /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the negative edge + * of SDA and the negative edge of SCL for a START condition, in I2C module clock + * cycles. + */ + uint32_t scl_start_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_start_hold_reg_t; + +/** Type of scl_rstart_setup register + * Configures the delay between the positive + * edge of SCL and the negative edge of SDA + */ +typedef union { + struct { + /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the positive + * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module + * clock cycles. + */ + uint32_t scl_rstart_setup_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_rstart_setup_reg_t; + +/** Type of scl_stop_hold register + * Configures the delay after the SCL clock + * edge for a stop condition + */ +typedef union { + struct { + /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the delay after the STOP condition, + * in I2C module clock cycles. + */ + uint32_t scl_stop_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_stop_hold_reg_t; + +/** Type of scl_stop_setup register + * Configures the delay between the SDA and + * SCL positive edge for a stop condition + */ +typedef union { + struct { + /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the positive edge + * of SCL and the positive edge of SDA, in I2C module clock cycles. + */ + uint32_t scl_stop_setup_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_stop_setup_reg_t; + +/** Type of scl_st_time_out register + * SCL status time out register + */ +typedef union { + struct { + /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16; + * The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + */ + uint32_t scl_st_to_i2c:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} i2c_scl_st_time_out_reg_t; + +/** Type of scl_main_st_time_out register + * SCL main status time out register + */ +typedef union { + struct { + /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16; + * The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more + * than 23 + */ + uint32_t scl_main_st_to_i2c:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} i2c_scl_main_st_time_out_reg_t; + + +/** Group: Configuration registers */ +/** Type of ctr register + * Transmission setting + */ +typedef union { + struct { + /** sda_force_out : R/W; bitpos: [0]; default: 0; + * 1: direct output, 0: open drain output. + */ + uint32_t sda_force_out:1; + /** scl_force_out : R/W; bitpos: [1]; default: 0; + * 1: direct output, 0: open drain output. + */ + uint32_t scl_force_out:1; + /** sample_scl_level : R/W; bitpos: [2]; default: 0; + * This register is used to select the sample mode. + * 1: sample SDA data on the SCL low level. + * 0: sample SDA data on the SCL high level. + */ + uint32_t sample_scl_level:1; + /** rx_full_ack_level : R/W; bitpos: [3]; default: 1; + * This register is used to configure the ACK value that need to sent by master when + * the rx_fifo_cnt has reached the threshold. + */ + uint32_t rx_full_ack_level:1; + /** ms_mode : R/W; bitpos: [4]; default: 0; + * Set this bit to configure the module as an I2C Master. Clear this bit to configure + * the + * module as an I2C Slave. + */ + uint32_t ms_mode:1; + /** trans_start : WT; bitpos: [5]; default: 0; + * Set this bit to start sending the data in txfifo. + */ + uint32_t trans_start:1; + /** tx_lsb_first : R/W; bitpos: [6]; default: 0; + * This bit is used to control the sending mode for data needing to be sent. + * 1: send data from the least significant bit, + * 0: send data from the most significant bit. + */ + uint32_t tx_lsb_first:1; + /** rx_lsb_first : R/W; bitpos: [7]; default: 0; + * This bit is used to control the storage mode for received data. + * 1: receive data from the least significant bit, + * 0: receive data from the most significant bit. + */ + uint32_t rx_lsb_first:1; + /** clk_en : R/W; bitpos: [8]; default: 0; + * Reserved + */ + uint32_t clk_en:1; + /** arbitration_en : R/W; bitpos: [9]; default: 1; + * This is the enable bit for arbitration_lost. + */ + uint32_t arbitration_en:1; + /** fsm_rst : WT; bitpos: [10]; default: 0; + * This register is used to reset the scl FMS. + */ + uint32_t fsm_rst:1; + /** conf_upgate : WT; bitpos: [11]; default: 0; + * synchronization bit + */ + uint32_t conf_upgate:1; + /** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0; + * This is the enable bit for slave to send data automatically + */ + uint32_t slv_tx_auto_start_en:1; + /** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0; + * This is the enable bit to check if the r/w bit of 10bit addressing consists with + * I2C protocol + */ + uint32_t addr_10bit_rw_check_en:1; + /** addr_broadcasting_en : R/W; bitpos: [14]; default: 0; + * This is the enable bit to support the 7bit general call function. + */ + uint32_t addr_broadcasting_en:1; + uint32_t reserved_15:17; + }; + uint32_t val; +} i2c_ctr_reg_t; + +/** Type of to register + * Setting time out control for receiving data. + */ +typedef union { + struct { + /** time_out_value : R/W; bitpos: [4:0]; default: 16; + * This register is used to configure the timeout for receiving a data bit in APB + * clock cycles. + */ + uint32_t time_out_value:5; + /** time_out_en : R/W; bitpos: [5]; default: 0; + * This is the enable bit for time out control. + */ + uint32_t time_out_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} i2c_to_reg_t; + +/** Type of slave_addr register + * Local slave address setting + */ +typedef union { + struct { + /** slave_addr : R/W; bitpos: [14:0]; default: 0; + * When configured as an I2C Slave, this field is used to configure the slave address. + */ + uint32_t slave_addr:15; + uint32_t reserved_15:16; + /** addr_10bit_en : R/W; bitpos: [31]; default: 0; + * This field is used to enable the slave 10-bit addressing mode in master mode. + */ + uint32_t addr_10bit_en:1; + }; + uint32_t val; +} i2c_slave_addr_reg_t; + +/** Type of fifo_conf register + * FIFO configuration register. + */ +typedef union { + struct { + /** rxfifo_wm_thrhd : R/W; bitpos: [4:0]; default: 11; + * The water mark threshold of rx FIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than + * reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. + */ + uint32_t rxfifo_wm_thrhd:5; + /** txfifo_wm_thrhd : R/W; bitpos: [9:5]; default: 4; + * The water mark threshold of tx FIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than + * reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. + */ + uint32_t txfifo_wm_thrhd:5; + /** nonfifo_en : R/W; bitpos: [10]; default: 0; + * Set this bit to enable APB nonfifo access. + */ + uint32_t nonfifo_en:1; + /** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0; + * When this bit is set to 1, the byte received after the I2C address byte represents + * the offset address in the I2C Slave RAM. + */ + uint32_t fifo_addr_cfg_en:1; + /** rx_fifo_rst : R/W; bitpos: [12]; default: 0; + * Set this bit to reset rx-fifo. + */ + uint32_t rx_fifo_rst:1; + /** tx_fifo_rst : R/W; bitpos: [13]; default: 0; + * Set this bit to reset tx-fifo. + */ + uint32_t tx_fifo_rst:1; + /** fifo_prt_en : R/W; bitpos: [14]; default: 1; + * The control enable bit of FIFO pointer in non-fifo access mode. This bit controls + * the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. + */ + uint32_t fifo_prt_en:1; + uint32_t reserved_15:17; + }; + uint32_t val; +} i2c_fifo_conf_reg_t; + +/** Type of filter_cfg register + * SCL and SDA filter configuration register + */ +typedef union { + struct { + /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0; + * When a pulse on the SCL input has smaller width than this register value + * in I2C module clock cycles, the I2C controller will ignore that pulse. + */ + uint32_t scl_filter_thres:4; + /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0; + * When a pulse on the SDA input has smaller width than this register value + * in I2C module clock cycles, the I2C controller will ignore that pulse. + */ + uint32_t sda_filter_thres:4; + /** scl_filter_en : R/W; bitpos: [8]; default: 1; + * This is the filter enable bit for SCL. + */ + uint32_t scl_filter_en:1; + /** sda_filter_en : R/W; bitpos: [9]; default: 1; + * This is the filter enable bit for SDA. + */ + uint32_t sda_filter_en:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} i2c_filter_cfg_reg_t; + +/** Type of clk_conf register + * I2C CLK configuration register + */ +typedef union { + struct { + /** sclk_div_num : R/W; bitpos: [7:0]; default: 0; + * the integral part of the fractional divisor for i2c module + */ + uint32_t sclk_div_num:8; + /** sclk_div_a : R/W; bitpos: [13:8]; default: 0; + * the numerator of the fractional part of the fractional divisor for i2c module + */ + uint32_t sclk_div_a:6; + /** sclk_div_b : R/W; bitpos: [19:14]; default: 0; + * the denominator of the fractional part of the fractional divisor for i2c module + */ + uint32_t sclk_div_b:6; + /** sclk_sel : R/W; bitpos: [20]; default: 0; + * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + */ + uint32_t sclk_sel:1; + /** sclk_active : R/W; bitpos: [21]; default: 1; + * The clock switch for i2c module + */ + uint32_t sclk_active:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} i2c_clk_conf_reg_t; + +/** Type of scl_sp_conf register + * Power configuration register + */ +typedef union { + struct { + /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0; + * When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses + * equals to reg_scl_rst_slv_num[4:0]. + */ + uint32_t scl_rst_slv_en:1; + /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0; + * Configure the pulses of SCL generated in I2C master mode. Valid when + * reg_scl_rst_slv_en is 1. + */ + uint32_t scl_rst_slv_num:5; + /** scl_pd_en : R/W; bitpos: [6]; default: 0; + * The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power + * down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. + */ + uint32_t scl_pd_en:1; + /** sda_pd_en : R/W; bitpos: [7]; default: 0; + * The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power + * down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. + */ + uint32_t sda_pd_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} i2c_scl_sp_conf_reg_t; + +/** Type of scl_stretch_conf register + * Set SCL stretch of I2C slave + */ +typedef union { + struct { + /** stretch_protect_num : R/W; bitpos: [9:0]; default: 0; + * Configure the period of I2C slave stretching SCL line. + */ + uint32_t stretch_protect_num:10; + /** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0; + * The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL + * output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch + * event happens. The stretch cause can be seen in reg_stretch_cause. + */ + uint32_t slave_scl_stretch_en:1; + /** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the I2C slave SCL stretch function. + */ + uint32_t slave_scl_stretch_clr:1; + /** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0; + * The enable bit for slave to control ACK level function. + */ + uint32_t slave_byte_ack_ctl_en:1; + /** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0; + * Set the ACK level when slave controlling ACK level function enables. + */ + uint32_t slave_byte_ack_lvl:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} i2c_scl_stretch_conf_reg_t; + + +/** Group: Status registers */ +/** Type of sr register + * Describe I2C work status. + */ +typedef union { + struct { + /** resp_rec : RO; bitpos: [0]; default: 0; + * The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + */ + uint32_t resp_rec:1; + /** slave_rw : RO; bitpos: [1]; default: 0; + * When in slave mode, 1: master reads from slave, 0: master writes to slave. + */ + uint32_t slave_rw:1; + uint32_t reserved_2:1; + /** arb_lost : RO; bitpos: [3]; default: 0; + * When the I2C controller loses control of SCL line, this register changes to 1. + */ + uint32_t arb_lost:1; + /** bus_busy : RO; bitpos: [4]; default: 0; + * 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. + */ + uint32_t bus_busy:1; + /** slave_addressed : RO; bitpos: [5]; default: 0; + * When configured as an I2C Slave, and the address sent by the master is + * equal to the address of the slave, then this bit will be of high level. + */ + uint32_t slave_addressed:1; + uint32_t reserved_6:2; + /** rxfifo_cnt : RO; bitpos: [13:8]; default: 0; + * This field represents the amount of data needed to be sent. + */ + uint32_t rxfifo_cnt:6; + /** stretch_cause : RO; bitpos: [15:14]; default: 3; + * The cause of stretching SCL low in slave mode. 0: stretching SCL low at the + * beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty + * in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode. + */ + uint32_t stretch_cause:2; + uint32_t reserved_16:2; + /** txfifo_cnt : RO; bitpos: [23:18]; default: 0; + * This field stores the amount of received data in RAM. + */ + uint32_t txfifo_cnt:6; + /** scl_main_state_last : RO; bitpos: [26:24]; default: 0; + * This field indicates the states of the I2C module state machine. + * 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: + * Wait ACK + */ + uint32_t scl_main_state_last:3; + uint32_t reserved_27:1; + /** scl_state_last : RO; bitpos: [30:28]; default: 0; + * This field indicates the states of the state machine used to produce SCL. + * 0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop + */ + uint32_t scl_state_last:3; + uint32_t reserved_31:1; + }; + uint32_t val; +} i2c_sr_reg_t; + +/** Type of fifo_st register + * FIFO status register. + */ +typedef union { + struct { + /** rxfifo_raddr : RO; bitpos: [4:0]; default: 0; + * This is the offset address of the APB reading from rxfifo + */ + uint32_t rxfifo_raddr:5; + /** rxfifo_waddr : RO; bitpos: [9:5]; default: 0; + * This is the offset address of i2c module receiving data and writing to rxfifo. + */ + uint32_t rxfifo_waddr:5; + /** txfifo_raddr : RO; bitpos: [14:10]; default: 0; + * This is the offset address of i2c module reading from txfifo. + */ + uint32_t txfifo_raddr:5; + /** txfifo_waddr : RO; bitpos: [19:15]; default: 0; + * This is the offset address of APB bus writing to txfifo. + */ + uint32_t txfifo_waddr:5; + uint32_t reserved_20:2; + /** slave_rw_point : RO; bitpos: [29:22]; default: 0; + * The received data in I2C slave mode. + */ + uint32_t slave_rw_point:8; + uint32_t reserved_30:2; + }; + uint32_t val; +} i2c_fifo_st_reg_t; + +/** Type of data register + * Rx FIFO read data. + */ +typedef union { + struct { + /** fifo_rdata : HRO; bitpos: [7:0]; default: 0; + * The value of rx FIFO read data. + */ + uint32_t fifo_rdata:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} i2c_data_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_raw:1; + /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_raw:1; + /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_raw:1; + /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_raw:1; + /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_raw:1; + /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_raw:1; + /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_raw:1; + /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_raw:1; + /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_raw:1; + /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_raw:1; + /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_raw:1; + /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_raw:1; + /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_raw:1; + /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_raw:1; + /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_raw:1; + /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt bit for I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_raw:1; + /** slave_stretch_int_raw : R/SS/WTC; bitpos: [16]; default: 0; + * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_raw:1; + /** general_call_int_raw : R/SS/WTC; bitpos: [17]; default: 0; + * The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_raw:1; + /** slave_addr_unmatch_int_raw : R/SS/WTC; bitpos: [18]; default: 0; + * The raw interrupt bit for I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + */ + uint32_t slave_addr_unmatch_int_raw:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} i2c_int_raw_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_clr:1; + /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_clr:1; + /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_clr:1; + /** end_detect_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_clr:1; + /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_clr:1; + /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_clr:1; + /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_clr:1; + /** trans_complete_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_clr:1; + /** time_out_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_clr:1; + /** trans_start_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_clr:1; + /** nack_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_clr:1; + /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_clr:1; + /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_clr:1; + /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_clr:1; + /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_clr:1; + /** det_start_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_clr:1; + /** slave_stretch_int_clr : WT; bitpos: [16]; default: 0; + * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_clr:1; + /** general_call_int_clr : WT; bitpos: [17]; default: 0; + * Set this bit to clear I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_clr:1; + /** slave_addr_unmatch_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + */ + uint32_t slave_addr_unmatch_int_clr:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} i2c_int_clr_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_ena:1; + /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_ena:1; + /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_ena:1; + /** end_detect_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_ena:1; + /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_ena:1; + /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_ena:1; + /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_ena:1; + /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_ena:1; + /** time_out_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_ena:1; + /** trans_start_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_ena:1; + /** nack_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_ena:1; + /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_ena:1; + /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_ena:1; + /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_ena:1; + /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_ena:1; + /** det_start_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_ena:1; + /** slave_stretch_int_ena : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_ena:1; + /** general_call_int_ena : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_ena:1; + /** slave_addr_unmatch_int_ena : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + */ + uint32_t slave_addr_unmatch_int_ena:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} i2c_int_ena_reg_t; + +/** Type of int_status register + * Status of captured I2C communication events + */ +typedef union { + struct { + /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_st:1; + /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_st:1; + /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_st:1; + /** end_detect_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_st:1; + /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_st:1; + /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_st:1; + /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_st:1; + /** trans_complete_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_st:1; + /** time_out_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_st:1; + /** trans_start_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_st:1; + /** nack_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_st:1; + /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_st:1; + /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_st:1; + /** scl_st_to_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_st:1; + /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_st:1; + /** det_start_int_st : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_st:1; + /** slave_stretch_int_st : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_st:1; + /** general_call_int_st : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_st:1; + /** slave_addr_unmatch_int_st : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + */ + uint32_t slave_addr_unmatch_int_st:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} i2c_int_status_reg_t; + + +/** Group: Command registers */ +/** Type of comd register + * I2C command register 0~7 + */ +typedef union { + struct { + /** command : R/W; bitpos: [13:0]; default: 0; + * This is the content of command. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command:14; + uint32_t reserved_14:17; + /** command_done : R/W/SS; bitpos: [31]; default: 0; + * When command is done in I2C Master mode, this bit changes to high + * level. + */ + uint32_t command_done:1; + }; + uint32_t val; +} i2c_comd_reg_t; + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35656050; + * This is the the version register. + */ + uint32_t date:32; + }; + uint32_t val; +} i2c_date_reg_t; + + +/** Group: Address register */ +/** Type of txfifo_start_addr register + * I2C TXFIFO base address register + */ +typedef union { + struct { + /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0; + * This is the I2C txfifo first address. + */ + uint32_t txfifo_start_addr:32; + }; + uint32_t val; +} i2c_txfifo_start_addr_reg_t; + +/** Type of rxfifo_start_addr register + * I2C RXFIFO base address register + */ +typedef union { + struct { + /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0; + * This is the I2C rxfifo first address. + */ + uint32_t rxfifo_start_addr:32; + }; + uint32_t val; +} i2c_rxfifo_start_addr_reg_t; + + +typedef struct i2c_dev_t { + volatile i2c_scl_low_period_reg_t scl_low_period; + volatile i2c_ctr_reg_t ctr; + volatile i2c_sr_reg_t sr; + volatile i2c_to_reg_t to; + volatile i2c_slave_addr_reg_t slave_addr; + volatile i2c_fifo_st_reg_t fifo_st; + volatile i2c_fifo_conf_reg_t fifo_conf; + volatile i2c_data_reg_t data; + volatile i2c_int_raw_reg_t int_raw; + volatile i2c_int_clr_reg_t int_clr; + volatile i2c_int_ena_reg_t int_ena; + volatile i2c_int_status_reg_t int_status; + volatile i2c_sda_hold_reg_t sda_hold; + volatile i2c_sda_sample_reg_t sda_sample; + volatile i2c_scl_high_period_reg_t scl_high_period; + uint32_t reserved_03c; + volatile i2c_scl_start_hold_reg_t scl_start_hold; + volatile i2c_scl_rstart_setup_reg_t scl_rstart_setup; + volatile i2c_scl_stop_hold_reg_t scl_stop_hold; + volatile i2c_scl_stop_setup_reg_t scl_stop_setup; + volatile i2c_filter_cfg_reg_t filter_cfg; + volatile i2c_clk_conf_reg_t clk_conf; + volatile i2c_comd_reg_t command[8]; + volatile i2c_scl_st_time_out_reg_t scl_st_time_out; + volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out; + volatile i2c_scl_sp_conf_reg_t scl_sp_conf; + volatile i2c_scl_stretch_conf_reg_t scl_stretch_conf; + uint32_t reserved_088[28]; + volatile i2c_date_reg_t date; + uint32_t reserved_0fc; + volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr; + uint32_t reserved_104[31]; + volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr; +} i2c_dev_t; + +extern i2c_dev_t I2C0; + +#ifndef __cplusplus +_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/i2s_reg.h b/components/soc/esp32c6/include/soc/i2s_reg.h new file mode 100644 index 0000000000..89fd5eb844 --- /dev/null +++ b/components/soc/esp32c6/include/soc/i2s_reg.h @@ -0,0 +1,1294 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** I2S_INT_RAW_REG register + * I2S interrupt raw register, valid in level. + */ +#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0xc) +/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the i2s_rx_done_int interrupt + */ +#define I2S_RX_DONE_INT_RAW (BIT(0)) +#define I2S_RX_DONE_INT_RAW_M (I2S_RX_DONE_INT_RAW_V << I2S_RX_DONE_INT_RAW_S) +#define I2S_RX_DONE_INT_RAW_V 0x00000001U +#define I2S_RX_DONE_INT_RAW_S 0 +/** I2S_TX_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the i2s_tx_done_int interrupt + */ +#define I2S_TX_DONE_INT_RAW (BIT(1)) +#define I2S_TX_DONE_INT_RAW_M (I2S_TX_DONE_INT_RAW_V << I2S_TX_DONE_INT_RAW_S) +#define I2S_TX_DONE_INT_RAW_V 0x00000001U +#define I2S_TX_DONE_INT_RAW_S 1 +/** I2S_RX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the i2s_rx_hung_int interrupt + */ +#define I2S_RX_HUNG_INT_RAW (BIT(2)) +#define I2S_RX_HUNG_INT_RAW_M (I2S_RX_HUNG_INT_RAW_V << I2S_RX_HUNG_INT_RAW_S) +#define I2S_RX_HUNG_INT_RAW_V 0x00000001U +#define I2S_RX_HUNG_INT_RAW_S 2 +/** I2S_TX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the i2s_tx_hung_int interrupt + */ +#define I2S_TX_HUNG_INT_RAW (BIT(3)) +#define I2S_TX_HUNG_INT_RAW_M (I2S_TX_HUNG_INT_RAW_V << I2S_TX_HUNG_INT_RAW_S) +#define I2S_TX_HUNG_INT_RAW_V 0x00000001U +#define I2S_TX_HUNG_INT_RAW_S 3 + +/** I2S_INT_ST_REG register + * I2S interrupt status register. + */ +#define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x10) +/** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the i2s_rx_done_int interrupt + */ +#define I2S_RX_DONE_INT_ST (BIT(0)) +#define I2S_RX_DONE_INT_ST_M (I2S_RX_DONE_INT_ST_V << I2S_RX_DONE_INT_ST_S) +#define I2S_RX_DONE_INT_ST_V 0x00000001U +#define I2S_RX_DONE_INT_ST_S 0 +/** I2S_TX_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the i2s_tx_done_int interrupt + */ +#define I2S_TX_DONE_INT_ST (BIT(1)) +#define I2S_TX_DONE_INT_ST_M (I2S_TX_DONE_INT_ST_V << I2S_TX_DONE_INT_ST_S) +#define I2S_TX_DONE_INT_ST_V 0x00000001U +#define I2S_TX_DONE_INT_ST_S 1 +/** I2S_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the i2s_rx_hung_int interrupt + */ +#define I2S_RX_HUNG_INT_ST (BIT(2)) +#define I2S_RX_HUNG_INT_ST_M (I2S_RX_HUNG_INT_ST_V << I2S_RX_HUNG_INT_ST_S) +#define I2S_RX_HUNG_INT_ST_V 0x00000001U +#define I2S_RX_HUNG_INT_ST_S 2 +/** I2S_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the i2s_tx_hung_int interrupt + */ +#define I2S_TX_HUNG_INT_ST (BIT(3)) +#define I2S_TX_HUNG_INT_ST_M (I2S_TX_HUNG_INT_ST_V << I2S_TX_HUNG_INT_ST_S) +#define I2S_TX_HUNG_INT_ST_V 0x00000001U +#define I2S_TX_HUNG_INT_ST_S 3 + +/** I2S_INT_ENA_REG register + * I2S interrupt enable register. + */ +#define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x14) +/** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the i2s_rx_done_int interrupt + */ +#define I2S_RX_DONE_INT_ENA (BIT(0)) +#define I2S_RX_DONE_INT_ENA_M (I2S_RX_DONE_INT_ENA_V << I2S_RX_DONE_INT_ENA_S) +#define I2S_RX_DONE_INT_ENA_V 0x00000001U +#define I2S_RX_DONE_INT_ENA_S 0 +/** I2S_TX_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the i2s_tx_done_int interrupt + */ +#define I2S_TX_DONE_INT_ENA (BIT(1)) +#define I2S_TX_DONE_INT_ENA_M (I2S_TX_DONE_INT_ENA_V << I2S_TX_DONE_INT_ENA_S) +#define I2S_TX_DONE_INT_ENA_V 0x00000001U +#define I2S_TX_DONE_INT_ENA_S 1 +/** I2S_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the i2s_rx_hung_int interrupt + */ +#define I2S_RX_HUNG_INT_ENA (BIT(2)) +#define I2S_RX_HUNG_INT_ENA_M (I2S_RX_HUNG_INT_ENA_V << I2S_RX_HUNG_INT_ENA_S) +#define I2S_RX_HUNG_INT_ENA_V 0x00000001U +#define I2S_RX_HUNG_INT_ENA_S 2 +/** I2S_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the i2s_tx_hung_int interrupt + */ +#define I2S_TX_HUNG_INT_ENA (BIT(3)) +#define I2S_TX_HUNG_INT_ENA_M (I2S_TX_HUNG_INT_ENA_V << I2S_TX_HUNG_INT_ENA_S) +#define I2S_TX_HUNG_INT_ENA_V 0x00000001U +#define I2S_TX_HUNG_INT_ENA_S 3 + +/** I2S_INT_CLR_REG register + * I2S interrupt clear register. + */ +#define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x18) +/** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the i2s_rx_done_int interrupt + */ +#define I2S_RX_DONE_INT_CLR (BIT(0)) +#define I2S_RX_DONE_INT_CLR_M (I2S_RX_DONE_INT_CLR_V << I2S_RX_DONE_INT_CLR_S) +#define I2S_RX_DONE_INT_CLR_V 0x00000001U +#define I2S_RX_DONE_INT_CLR_S 0 +/** I2S_TX_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the i2s_tx_done_int interrupt + */ +#define I2S_TX_DONE_INT_CLR (BIT(1)) +#define I2S_TX_DONE_INT_CLR_M (I2S_TX_DONE_INT_CLR_V << I2S_TX_DONE_INT_CLR_S) +#define I2S_TX_DONE_INT_CLR_V 0x00000001U +#define I2S_TX_DONE_INT_CLR_S 1 +/** I2S_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the i2s_rx_hung_int interrupt + */ +#define I2S_RX_HUNG_INT_CLR (BIT(2)) +#define I2S_RX_HUNG_INT_CLR_M (I2S_RX_HUNG_INT_CLR_V << I2S_RX_HUNG_INT_CLR_S) +#define I2S_RX_HUNG_INT_CLR_V 0x00000001U +#define I2S_RX_HUNG_INT_CLR_S 2 +/** I2S_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the i2s_tx_hung_int interrupt + */ +#define I2S_TX_HUNG_INT_CLR (BIT(3)) +#define I2S_TX_HUNG_INT_CLR_M (I2S_TX_HUNG_INT_CLR_V << I2S_TX_HUNG_INT_CLR_S) +#define I2S_TX_HUNG_INT_CLR_V 0x00000001U +#define I2S_TX_HUNG_INT_CLR_S 3 + +/** I2S_RX_CONF_REG register + * I2S RX configure register + */ +#define I2S_RX_CONF_REG(i) (REG_I2S_BASE(i) + 0x20) +/** I2S_RX_RESET : WT; bitpos: [0]; default: 0; + * Set this bit to reset receiver + */ +#define I2S_RX_RESET (BIT(0)) +#define I2S_RX_RESET_M (I2S_RX_RESET_V << I2S_RX_RESET_S) +#define I2S_RX_RESET_V 0x00000001U +#define I2S_RX_RESET_S 0 +/** I2S_RX_FIFO_RESET : WT; bitpos: [1]; default: 0; + * Set this bit to reset Rx AFIFO + */ +#define I2S_RX_FIFO_RESET (BIT(1)) +#define I2S_RX_FIFO_RESET_M (I2S_RX_FIFO_RESET_V << I2S_RX_FIFO_RESET_S) +#define I2S_RX_FIFO_RESET_V 0x00000001U +#define I2S_RX_FIFO_RESET_S 1 +/** I2S_RX_START : R/W/SC; bitpos: [2]; default: 0; + * Set this bit to start receiving data + */ +#define I2S_RX_START (BIT(2)) +#define I2S_RX_START_M (I2S_RX_START_V << I2S_RX_START_S) +#define I2S_RX_START_V 0x00000001U +#define I2S_RX_START_S 2 +/** I2S_RX_SLAVE_MOD : R/W; bitpos: [3]; default: 0; + * Set this bit to enable slave receiver mode + */ +#define I2S_RX_SLAVE_MOD (BIT(3)) +#define I2S_RX_SLAVE_MOD_M (I2S_RX_SLAVE_MOD_V << I2S_RX_SLAVE_MOD_S) +#define I2S_RX_SLAVE_MOD_V 0x00000001U +#define I2S_RX_SLAVE_MOD_S 3 +/** I2S_RX_MONO : R/W; bitpos: [5]; default: 0; + * Set this bit to enable receiver in mono mode + */ +#define I2S_RX_MONO (BIT(5)) +#define I2S_RX_MONO_M (I2S_RX_MONO_V << I2S_RX_MONO_S) +#define I2S_RX_MONO_V 0x00000001U +#define I2S_RX_MONO_S 5 +/** I2S_RX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0; + * I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + */ +#define I2S_RX_BIG_ENDIAN (BIT(7)) +#define I2S_RX_BIG_ENDIAN_M (I2S_RX_BIG_ENDIAN_V << I2S_RX_BIG_ENDIAN_S) +#define I2S_RX_BIG_ENDIAN_V 0x00000001U +#define I2S_RX_BIG_ENDIAN_S 7 +/** I2S_RX_UPDATE : R/W/SC; bitpos: [8]; default: 0; + * Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This + * bit will be cleared by hardware after update register done. + */ +#define I2S_RX_UPDATE (BIT(8)) +#define I2S_RX_UPDATE_M (I2S_RX_UPDATE_V << I2S_RX_UPDATE_S) +#define I2S_RX_UPDATE_V 0x00000001U +#define I2S_RX_UPDATE_S 8 +/** I2S_RX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1; + * 1: The first channel data value is valid in I2S RX mono mode. 0: The second + * channel data value is valid in I2S RX mono mode. + */ +#define I2S_RX_MONO_FST_VLD (BIT(9)) +#define I2S_RX_MONO_FST_VLD_M (I2S_RX_MONO_FST_VLD_V << I2S_RX_MONO_FST_VLD_S) +#define I2S_RX_MONO_FST_VLD_V 0x00000001U +#define I2S_RX_MONO_FST_VLD_S 9 +/** I2S_RX_PCM_CONF : R/W; bitpos: [11:10]; default: 1; + * I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 + * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + */ +#define I2S_RX_PCM_CONF 0x00000003U +#define I2S_RX_PCM_CONF_M (I2S_RX_PCM_CONF_V << I2S_RX_PCM_CONF_S) +#define I2S_RX_PCM_CONF_V 0x00000003U +#define I2S_RX_PCM_CONF_S 10 +/** I2S_RX_PCM_BYPASS : R/W; bitpos: [12]; default: 1; + * Set this bit to bypass Compress/Decompress module for received data. + */ +#define I2S_RX_PCM_BYPASS (BIT(12)) +#define I2S_RX_PCM_BYPASS_M (I2S_RX_PCM_BYPASS_V << I2S_RX_PCM_BYPASS_S) +#define I2S_RX_PCM_BYPASS_V 0x00000001U +#define I2S_RX_PCM_BYPASS_S 12 +/** I2S_RX_STOP_MODE : R/W; bitpos: [14:13]; default: 0; + * 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is + * 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + */ +#define I2S_RX_STOP_MODE 0x00000003U +#define I2S_RX_STOP_MODE_M (I2S_RX_STOP_MODE_V << I2S_RX_STOP_MODE_S) +#define I2S_RX_STOP_MODE_V 0x00000003U +#define I2S_RX_STOP_MODE_S 13 +/** I2S_RX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1; + * 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + */ +#define I2S_RX_LEFT_ALIGN (BIT(15)) +#define I2S_RX_LEFT_ALIGN_M (I2S_RX_LEFT_ALIGN_V << I2S_RX_LEFT_ALIGN_S) +#define I2S_RX_LEFT_ALIGN_V 0x00000001U +#define I2S_RX_LEFT_ALIGN_S 15 +/** I2S_RX_24_FILL_EN : R/W; bitpos: [16]; default: 0; + * 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + */ +#define I2S_RX_24_FILL_EN (BIT(16)) +#define I2S_RX_24_FILL_EN_M (I2S_RX_24_FILL_EN_V << I2S_RX_24_FILL_EN_S) +#define I2S_RX_24_FILL_EN_V 0x00000001U +#define I2S_RX_24_FILL_EN_S 16 +/** I2S_RX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0; + * 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. + * 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + */ +#define I2S_RX_WS_IDLE_POL (BIT(17)) +#define I2S_RX_WS_IDLE_POL_M (I2S_RX_WS_IDLE_POL_V << I2S_RX_WS_IDLE_POL_S) +#define I2S_RX_WS_IDLE_POL_V 0x00000001U +#define I2S_RX_WS_IDLE_POL_S 17 +/** I2S_RX_BIT_ORDER : R/W; bitpos: [18]; default: 0; + * I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB + * is received first. + */ +#define I2S_RX_BIT_ORDER (BIT(18)) +#define I2S_RX_BIT_ORDER_M (I2S_RX_BIT_ORDER_V << I2S_RX_BIT_ORDER_S) +#define I2S_RX_BIT_ORDER_V 0x00000001U +#define I2S_RX_BIT_ORDER_S 18 +/** I2S_RX_TDM_EN : R/W; bitpos: [19]; default: 0; + * 1: Enable I2S TDM Rx mode . 0: Disable. + */ +#define I2S_RX_TDM_EN (BIT(19)) +#define I2S_RX_TDM_EN_M (I2S_RX_TDM_EN_V << I2S_RX_TDM_EN_S) +#define I2S_RX_TDM_EN_V 0x00000001U +#define I2S_RX_TDM_EN_S 19 +/** I2S_RX_PDM_EN : R/W; bitpos: [20]; default: 0; + * 1: Enable I2S PDM Rx mode . 0: Disable. + */ +#define I2S_RX_PDM_EN (BIT(20)) +#define I2S_RX_PDM_EN_M (I2S_RX_PDM_EN_V << I2S_RX_PDM_EN_S) +#define I2S_RX_PDM_EN_V 0x00000001U +#define I2S_RX_PDM_EN_S 20 + +/** I2S_TX_CONF_REG register + * I2S TX configure register + */ +#define I2S_TX_CONF_REG(i) (REG_I2S_BASE(i) + 0x24) +/** I2S_TX_RESET : WT; bitpos: [0]; default: 0; + * Set this bit to reset transmitter + */ +#define I2S_TX_RESET (BIT(0)) +#define I2S_TX_RESET_M (I2S_TX_RESET_V << I2S_TX_RESET_S) +#define I2S_TX_RESET_V 0x00000001U +#define I2S_TX_RESET_S 0 +/** I2S_TX_FIFO_RESET : WT; bitpos: [1]; default: 0; + * Set this bit to reset Tx AFIFO + */ +#define I2S_TX_FIFO_RESET (BIT(1)) +#define I2S_TX_FIFO_RESET_M (I2S_TX_FIFO_RESET_V << I2S_TX_FIFO_RESET_S) +#define I2S_TX_FIFO_RESET_V 0x00000001U +#define I2S_TX_FIFO_RESET_S 1 +/** I2S_TX_START : R/W/SC; bitpos: [2]; default: 0; + * Set this bit to start transmitting data + */ +#define I2S_TX_START (BIT(2)) +#define I2S_TX_START_M (I2S_TX_START_V << I2S_TX_START_S) +#define I2S_TX_START_V 0x00000001U +#define I2S_TX_START_S 2 +/** I2S_TX_SLAVE_MOD : R/W; bitpos: [3]; default: 0; + * Set this bit to enable slave transmitter mode + */ +#define I2S_TX_SLAVE_MOD (BIT(3)) +#define I2S_TX_SLAVE_MOD_M (I2S_TX_SLAVE_MOD_V << I2S_TX_SLAVE_MOD_S) +#define I2S_TX_SLAVE_MOD_V 0x00000001U +#define I2S_TX_SLAVE_MOD_S 3 +/** I2S_TX_MONO : R/W; bitpos: [5]; default: 0; + * Set this bit to enable transmitter in mono mode + */ +#define I2S_TX_MONO (BIT(5)) +#define I2S_TX_MONO_M (I2S_TX_MONO_V << I2S_TX_MONO_S) +#define I2S_TX_MONO_V 0x00000001U +#define I2S_TX_MONO_S 5 +/** I2S_TX_CHAN_EQUAL : R/W; bitpos: [6]; default: 0; + * 1: The value of Left channel data is equal to the value of right channel data in + * I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is + * reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. + */ +#define I2S_TX_CHAN_EQUAL (BIT(6)) +#define I2S_TX_CHAN_EQUAL_M (I2S_TX_CHAN_EQUAL_V << I2S_TX_CHAN_EQUAL_S) +#define I2S_TX_CHAN_EQUAL_V 0x00000001U +#define I2S_TX_CHAN_EQUAL_S 6 +/** I2S_TX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0; + * I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr + * value. + */ +#define I2S_TX_BIG_ENDIAN (BIT(7)) +#define I2S_TX_BIG_ENDIAN_M (I2S_TX_BIG_ENDIAN_V << I2S_TX_BIG_ENDIAN_S) +#define I2S_TX_BIG_ENDIAN_V 0x00000001U +#define I2S_TX_BIG_ENDIAN_S 7 +/** I2S_TX_UPDATE : R/W/SC; bitpos: [8]; default: 0; + * Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This + * bit will be cleared by hardware after update register done. + */ +#define I2S_TX_UPDATE (BIT(8)) +#define I2S_TX_UPDATE_M (I2S_TX_UPDATE_V << I2S_TX_UPDATE_S) +#define I2S_TX_UPDATE_V 0x00000001U +#define I2S_TX_UPDATE_S 8 +/** I2S_TX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1; + * 1: The first channel data value is valid in I2S TX mono mode. 0: The second + * channel data value is valid in I2S TX mono mode. + */ +#define I2S_TX_MONO_FST_VLD (BIT(9)) +#define I2S_TX_MONO_FST_VLD_M (I2S_TX_MONO_FST_VLD_V << I2S_TX_MONO_FST_VLD_S) +#define I2S_TX_MONO_FST_VLD_V 0x00000001U +#define I2S_TX_MONO_FST_VLD_S 9 +/** I2S_TX_PCM_CONF : R/W; bitpos: [11:10]; default: 0; + * I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 + * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + */ +#define I2S_TX_PCM_CONF 0x00000003U +#define I2S_TX_PCM_CONF_M (I2S_TX_PCM_CONF_V << I2S_TX_PCM_CONF_S) +#define I2S_TX_PCM_CONF_V 0x00000003U +#define I2S_TX_PCM_CONF_S 10 +/** I2S_TX_PCM_BYPASS : R/W; bitpos: [12]; default: 1; + * Set this bit to bypass Compress/Decompress module for transmitted data. + */ +#define I2S_TX_PCM_BYPASS (BIT(12)) +#define I2S_TX_PCM_BYPASS_M (I2S_TX_PCM_BYPASS_V << I2S_TX_PCM_BYPASS_S) +#define I2S_TX_PCM_BYPASS_V 0x00000001U +#define I2S_TX_PCM_BYPASS_S 12 +/** I2S_TX_STOP_EN : R/W; bitpos: [13]; default: 1; + * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + */ +#define I2S_TX_STOP_EN (BIT(13)) +#define I2S_TX_STOP_EN_M (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S) +#define I2S_TX_STOP_EN_V 0x00000001U +#define I2S_TX_STOP_EN_S 13 +/** I2S_TX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1; + * 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + */ +#define I2S_TX_LEFT_ALIGN (BIT(15)) +#define I2S_TX_LEFT_ALIGN_M (I2S_TX_LEFT_ALIGN_V << I2S_TX_LEFT_ALIGN_S) +#define I2S_TX_LEFT_ALIGN_V 0x00000001U +#define I2S_TX_LEFT_ALIGN_S 15 +/** I2S_TX_24_FILL_EN : R/W; bitpos: [16]; default: 0; + * 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + */ +#define I2S_TX_24_FILL_EN (BIT(16)) +#define I2S_TX_24_FILL_EN_M (I2S_TX_24_FILL_EN_V << I2S_TX_24_FILL_EN_S) +#define I2S_TX_24_FILL_EN_V 0x00000001U +#define I2S_TX_24_FILL_EN_S 16 +/** I2S_TX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0; + * 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: + * WS should be 1 when sending left channel data, and WS is 0in right channel. + */ +#define I2S_TX_WS_IDLE_POL (BIT(17)) +#define I2S_TX_WS_IDLE_POL_M (I2S_TX_WS_IDLE_POL_V << I2S_TX_WS_IDLE_POL_S) +#define I2S_TX_WS_IDLE_POL_V 0x00000001U +#define I2S_TX_WS_IDLE_POL_S 17 +/** I2S_TX_BIT_ORDER : R/W; bitpos: [18]; default: 0; + * I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is + * sent first. + */ +#define I2S_TX_BIT_ORDER (BIT(18)) +#define I2S_TX_BIT_ORDER_M (I2S_TX_BIT_ORDER_V << I2S_TX_BIT_ORDER_S) +#define I2S_TX_BIT_ORDER_V 0x00000001U +#define I2S_TX_BIT_ORDER_S 18 +/** I2S_TX_TDM_EN : R/W; bitpos: [19]; default: 0; + * 1: Enable I2S TDM Tx mode . 0: Disable. + */ +#define I2S_TX_TDM_EN (BIT(19)) +#define I2S_TX_TDM_EN_M (I2S_TX_TDM_EN_V << I2S_TX_TDM_EN_S) +#define I2S_TX_TDM_EN_V 0x00000001U +#define I2S_TX_TDM_EN_S 19 +/** I2S_TX_PDM_EN : R/W; bitpos: [20]; default: 0; + * 1: Enable I2S PDM Tx mode . 0: Disable. + */ +#define I2S_TX_PDM_EN (BIT(20)) +#define I2S_TX_PDM_EN_M (I2S_TX_PDM_EN_V << I2S_TX_PDM_EN_S) +#define I2S_TX_PDM_EN_V 0x00000001U +#define I2S_TX_PDM_EN_S 20 +/** I2S_TX_CHAN_MOD : R/W; bitpos: [26:24]; default: 0; + * I2S transmitter channel mode configuration bits. + */ +#define I2S_TX_CHAN_MOD 0x00000007U +#define I2S_TX_CHAN_MOD_M (I2S_TX_CHAN_MOD_V << I2S_TX_CHAN_MOD_S) +#define I2S_TX_CHAN_MOD_V 0x00000007U +#define I2S_TX_CHAN_MOD_S 24 +/** I2S_SIG_LOOPBACK : R/W; bitpos: [27]; default: 0; + * Enable signal loop back mode with transmitter module and receiver module sharing + * the same WS and BCK signals. + */ +#define I2S_SIG_LOOPBACK (BIT(27)) +#define I2S_SIG_LOOPBACK_M (I2S_SIG_LOOPBACK_V << I2S_SIG_LOOPBACK_S) +#define I2S_SIG_LOOPBACK_V 0x00000001U +#define I2S_SIG_LOOPBACK_S 27 + +/** I2S_RX_CONF1_REG register + * I2S RX configure register 1 + */ +#define I2S_RX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x28) +/** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [6:0]; default: 0; + * The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck + */ +#define I2S_RX_TDM_WS_WIDTH 0x0000007FU +#define I2S_RX_TDM_WS_WIDTH_M (I2S_RX_TDM_WS_WIDTH_V << I2S_RX_TDM_WS_WIDTH_S) +#define I2S_RX_TDM_WS_WIDTH_V 0x0000007FU +#define I2S_RX_TDM_WS_WIDTH_S 0 +/** I2S_RX_BCK_DIV_NUM : R/W; bitpos: [12:7]; default: 6; + * Bit clock configuration bits in receiver mode. + */ +#define I2S_RX_BCK_DIV_NUM 0x0000003FU +#define I2S_RX_BCK_DIV_NUM_M (I2S_RX_BCK_DIV_NUM_V << I2S_RX_BCK_DIV_NUM_S) +#define I2S_RX_BCK_DIV_NUM_V 0x0000003FU +#define I2S_RX_BCK_DIV_NUM_S 7 +/** I2S_RX_BITS_MOD : R/W; bitpos: [17:13]; default: 15; + * Set the bits to configure the valid data bit length of I2S receiver channel. 7: all + * the valid channel data is in 8-bit-mode. 15: all the valid channel data is in + * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid + * channel data is in 32-bit-mode. + */ +#define I2S_RX_BITS_MOD 0x0000001FU +#define I2S_RX_BITS_MOD_M (I2S_RX_BITS_MOD_V << I2S_RX_BITS_MOD_S) +#define I2S_RX_BITS_MOD_V 0x0000001FU +#define I2S_RX_BITS_MOD_S 13 +/** I2S_RX_HALF_SAMPLE_BITS : R/W; bitpos: [23:18]; default: 15; + * I2S Rx half sample bits -1. + */ +#define I2S_RX_HALF_SAMPLE_BITS 0x0000003FU +#define I2S_RX_HALF_SAMPLE_BITS_M (I2S_RX_HALF_SAMPLE_BITS_V << I2S_RX_HALF_SAMPLE_BITS_S) +#define I2S_RX_HALF_SAMPLE_BITS_V 0x0000003FU +#define I2S_RX_HALF_SAMPLE_BITS_S 18 +/** I2S_RX_TDM_CHAN_BITS : R/W; bitpos: [28:24]; default: 15; + * The Rx bit number for each channel minus 1in TDM mode. + */ +#define I2S_RX_TDM_CHAN_BITS 0x0000001FU +#define I2S_RX_TDM_CHAN_BITS_M (I2S_RX_TDM_CHAN_BITS_V << I2S_RX_TDM_CHAN_BITS_S) +#define I2S_RX_TDM_CHAN_BITS_V 0x0000001FU +#define I2S_RX_TDM_CHAN_BITS_S 24 +/** I2S_RX_MSB_SHIFT : R/W; bitpos: [29]; default: 1; + * Set this bit to enable receiver in Phillips standard mode + */ +#define I2S_RX_MSB_SHIFT (BIT(29)) +#define I2S_RX_MSB_SHIFT_M (I2S_RX_MSB_SHIFT_V << I2S_RX_MSB_SHIFT_S) +#define I2S_RX_MSB_SHIFT_V 0x00000001U +#define I2S_RX_MSB_SHIFT_S 29 + +/** I2S_TX_CONF1_REG register + * I2S TX configure register 1 + */ +#define I2S_TX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x2c) +/** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [6:0]; default: 0; + * The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck + */ +#define I2S_TX_TDM_WS_WIDTH 0x0000007FU +#define I2S_TX_TDM_WS_WIDTH_M (I2S_TX_TDM_WS_WIDTH_V << I2S_TX_TDM_WS_WIDTH_S) +#define I2S_TX_TDM_WS_WIDTH_V 0x0000007FU +#define I2S_TX_TDM_WS_WIDTH_S 0 +/** I2S_TX_BCK_DIV_NUM : R/W; bitpos: [12:7]; default: 6; + * Bit clock configuration bits in transmitter mode. + */ +#define I2S_TX_BCK_DIV_NUM 0x0000003FU +#define I2S_TX_BCK_DIV_NUM_M (I2S_TX_BCK_DIV_NUM_V << I2S_TX_BCK_DIV_NUM_S) +#define I2S_TX_BCK_DIV_NUM_V 0x0000003FU +#define I2S_TX_BCK_DIV_NUM_S 7 +/** I2S_TX_BITS_MOD : R/W; bitpos: [17:13]; default: 15; + * Set the bits to configure the valid data bit length of I2S transmitter channel. 7: + * all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in + * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid + * channel data is in 32-bit-mode. + */ +#define I2S_TX_BITS_MOD 0x0000001FU +#define I2S_TX_BITS_MOD_M (I2S_TX_BITS_MOD_V << I2S_TX_BITS_MOD_S) +#define I2S_TX_BITS_MOD_V 0x0000001FU +#define I2S_TX_BITS_MOD_S 13 +/** I2S_TX_HALF_SAMPLE_BITS : R/W; bitpos: [23:18]; default: 15; + * I2S Tx half sample bits -1. + */ +#define I2S_TX_HALF_SAMPLE_BITS 0x0000003FU +#define I2S_TX_HALF_SAMPLE_BITS_M (I2S_TX_HALF_SAMPLE_BITS_V << I2S_TX_HALF_SAMPLE_BITS_S) +#define I2S_TX_HALF_SAMPLE_BITS_V 0x0000003FU +#define I2S_TX_HALF_SAMPLE_BITS_S 18 +/** I2S_TX_TDM_CHAN_BITS : R/W; bitpos: [28:24]; default: 15; + * The Tx bit number for each channel minus 1in TDM mode. + */ +#define I2S_TX_TDM_CHAN_BITS 0x0000001FU +#define I2S_TX_TDM_CHAN_BITS_M (I2S_TX_TDM_CHAN_BITS_V << I2S_TX_TDM_CHAN_BITS_S) +#define I2S_TX_TDM_CHAN_BITS_V 0x0000001FU +#define I2S_TX_TDM_CHAN_BITS_S 24 +/** I2S_TX_MSB_SHIFT : R/W; bitpos: [29]; default: 1; + * Set this bit to enable transmitter in Phillips standard mode + */ +#define I2S_TX_MSB_SHIFT (BIT(29)) +#define I2S_TX_MSB_SHIFT_M (I2S_TX_MSB_SHIFT_V << I2S_TX_MSB_SHIFT_S) +#define I2S_TX_MSB_SHIFT_V 0x00000001U +#define I2S_TX_MSB_SHIFT_S 29 +/** I2S_TX_BCK_NO_DLY : R/W; bitpos: [30]; default: 1; + * 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to + * generate pos/neg edge in master mode. + */ +#define I2S_TX_BCK_NO_DLY (BIT(30)) +#define I2S_TX_BCK_NO_DLY_M (I2S_TX_BCK_NO_DLY_V << I2S_TX_BCK_NO_DLY_S) +#define I2S_TX_BCK_NO_DLY_V 0x00000001U +#define I2S_TX_BCK_NO_DLY_S 30 + +/** I2S_RX_CLKM_CONF_REG register + * I2S RX clock configure register + */ +#define I2S_RX_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x30) +/** I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 2; + * Integral I2S clock divider value + */ +#define I2S_RX_CLKM_DIV_NUM 0x000000FFU +#define I2S_RX_CLKM_DIV_NUM_M (I2S_RX_CLKM_DIV_NUM_V << I2S_RX_CLKM_DIV_NUM_S) +#define I2S_RX_CLKM_DIV_NUM_V 0x000000FFU +#define I2S_RX_CLKM_DIV_NUM_S 0 +/** I2S_RX_CLK_ACTIVE : R/W; bitpos: [26]; default: 0; + * I2S Rx module clock enable signal. + */ +#define I2S_RX_CLK_ACTIVE (BIT(26)) +#define I2S_RX_CLK_ACTIVE_M (I2S_RX_CLK_ACTIVE_V << I2S_RX_CLK_ACTIVE_S) +#define I2S_RX_CLK_ACTIVE_V 0x00000001U +#define I2S_RX_CLK_ACTIVE_S 26 +/** I2S_RX_CLK_SEL : R/W; bitpos: [28:27]; default: 0; + * Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + */ +#define I2S_RX_CLK_SEL 0x00000003U +#define I2S_RX_CLK_SEL_M (I2S_RX_CLK_SEL_V << I2S_RX_CLK_SEL_S) +#define I2S_RX_CLK_SEL_V 0x00000003U +#define I2S_RX_CLK_SEL_S 27 +/** I2S_MCLK_SEL : R/W; bitpos: [29]; default: 0; + * 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as + * I2S_MCLK_OUT. + */ +#define I2S_MCLK_SEL (BIT(29)) +#define I2S_MCLK_SEL_M (I2S_MCLK_SEL_V << I2S_MCLK_SEL_S) +#define I2S_MCLK_SEL_V 0x00000001U +#define I2S_MCLK_SEL_S 29 + +/** I2S_TX_CLKM_CONF_REG register + * I2S TX clock configure register + */ +#define I2S_TX_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x34) +/** I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 2; + * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be + * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= + * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * + * (n+1)-div] + y * (n+1)-div. + */ +#define I2S_TX_CLKM_DIV_NUM 0x000000FFU +#define I2S_TX_CLKM_DIV_NUM_M (I2S_TX_CLKM_DIV_NUM_V << I2S_TX_CLKM_DIV_NUM_S) +#define I2S_TX_CLKM_DIV_NUM_V 0x000000FFU +#define I2S_TX_CLKM_DIV_NUM_S 0 +/** I2S_TX_CLK_ACTIVE : R/W; bitpos: [26]; default: 0; + * I2S Tx module clock enable signal. + */ +#define I2S_TX_CLK_ACTIVE (BIT(26)) +#define I2S_TX_CLK_ACTIVE_M (I2S_TX_CLK_ACTIVE_V << I2S_TX_CLK_ACTIVE_S) +#define I2S_TX_CLK_ACTIVE_V 0x00000001U +#define I2S_TX_CLK_ACTIVE_S 26 +/** I2S_TX_CLK_SEL : R/W; bitpos: [28:27]; default: 0; + * Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: + * I2S_MCLK_in. + */ +#define I2S_TX_CLK_SEL 0x00000003U +#define I2S_TX_CLK_SEL_M (I2S_TX_CLK_SEL_V << I2S_TX_CLK_SEL_S) +#define I2S_TX_CLK_SEL_V 0x00000003U +#define I2S_TX_CLK_SEL_S 27 +/** I2S_CLK_EN : R/W; bitpos: [29]; default: 0; + * Set this bit to enable clk gate + */ +#define I2S_CLK_EN (BIT(29)) +#define I2S_CLK_EN_M (I2S_CLK_EN_V << I2S_CLK_EN_S) +#define I2S_CLK_EN_V 0x00000001U +#define I2S_CLK_EN_S 29 + +/** I2S_RX_CLKM_DIV_CONF_REG register + * I2S RX module clock divider configure register + */ +#define I2S_RX_CLKM_DIV_CONF_REG(i) (REG_I2S_BASE(i) + 0x38) +/** I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_RX_CLKM_DIV_Z is (a-b). + */ +#define I2S_RX_CLKM_DIV_Z 0x000001FFU +#define I2S_RX_CLKM_DIV_Z_M (I2S_RX_CLKM_DIV_Z_V << I2S_RX_CLKM_DIV_Z_S) +#define I2S_RX_CLKM_DIV_Z_V 0x000001FFU +#define I2S_RX_CLKM_DIV_Z_S 0 +/** I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_RX_CLKM_DIV_Y is (a%(a-b)). + */ +#define I2S_RX_CLKM_DIV_Y 0x000001FFU +#define I2S_RX_CLKM_DIV_Y_M (I2S_RX_CLKM_DIV_Y_V << I2S_RX_CLKM_DIV_Y_S) +#define I2S_RX_CLKM_DIV_Y_V 0x000001FFU +#define I2S_RX_CLKM_DIV_Y_S 9 +/** I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define I2S_RX_CLKM_DIV_X 0x000001FFU +#define I2S_RX_CLKM_DIV_X_M (I2S_RX_CLKM_DIV_X_V << I2S_RX_CLKM_DIV_X_S) +#define I2S_RX_CLKM_DIV_X_V 0x000001FFU +#define I2S_RX_CLKM_DIV_X_S 18 +/** I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_RX_CLKM_DIV_YN1 is 1. + */ +#define I2S_RX_CLKM_DIV_YN1 (BIT(27)) +#define I2S_RX_CLKM_DIV_YN1_M (I2S_RX_CLKM_DIV_YN1_V << I2S_RX_CLKM_DIV_YN1_S) +#define I2S_RX_CLKM_DIV_YN1_V 0x00000001U +#define I2S_RX_CLKM_DIV_YN1_S 27 + +/** I2S_TX_CLKM_DIV_CONF_REG register + * I2S TX module clock divider configure register + */ +#define I2S_TX_CLKM_DIV_CONF_REG(i) (REG_I2S_BASE(i) + 0x3c) +/** I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_TX_CLKM_DIV_Z is (a-b). + */ +#define I2S_TX_CLKM_DIV_Z 0x000001FFU +#define I2S_TX_CLKM_DIV_Z_M (I2S_TX_CLKM_DIV_Z_V << I2S_TX_CLKM_DIV_Z_S) +#define I2S_TX_CLKM_DIV_Z_V 0x000001FFU +#define I2S_TX_CLKM_DIV_Z_S 0 +/** I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_TX_CLKM_DIV_Y is (a%(a-b)). + */ +#define I2S_TX_CLKM_DIV_Y 0x000001FFU +#define I2S_TX_CLKM_DIV_Y_M (I2S_TX_CLKM_DIV_Y_V << I2S_TX_CLKM_DIV_Y_S) +#define I2S_TX_CLKM_DIV_Y_V 0x000001FFU +#define I2S_TX_CLKM_DIV_Y_S 9 +/** I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define I2S_TX_CLKM_DIV_X 0x000001FFU +#define I2S_TX_CLKM_DIV_X_M (I2S_TX_CLKM_DIV_X_V << I2S_TX_CLKM_DIV_X_S) +#define I2S_TX_CLKM_DIV_X_V 0x000001FFU +#define I2S_TX_CLKM_DIV_X_S 18 +/** I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_TX_CLKM_DIV_YN1 is 1. + */ +#define I2S_TX_CLKM_DIV_YN1 (BIT(27)) +#define I2S_TX_CLKM_DIV_YN1_M (I2S_TX_CLKM_DIV_YN1_V << I2S_TX_CLKM_DIV_YN1_S) +#define I2S_TX_CLKM_DIV_YN1_V 0x00000001U +#define I2S_TX_CLKM_DIV_YN1_S 27 + +/** I2S_TX_PCM2PDM_CONF_REG register + * I2S TX PCM2PDM configuration register + */ +#define I2S_TX_PCM2PDM_CONF_REG(i) (REG_I2S_BASE(i) + 0x40) +/** I2S_TX_PDM_HP_BYPASS : R/W; bitpos: [0]; default: 0; + * I2S TX PDM bypass hp filter or not. The option has been removed. + */ +#define I2S_TX_PDM_HP_BYPASS (BIT(0)) +#define I2S_TX_PDM_HP_BYPASS_M (I2S_TX_PDM_HP_BYPASS_V << I2S_TX_PDM_HP_BYPASS_S) +#define I2S_TX_PDM_HP_BYPASS_V 0x00000001U +#define I2S_TX_PDM_HP_BYPASS_S 0 +/** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2; + * I2S TX PDM OSR2 value + */ +#define I2S_TX_PDM_SINC_OSR2 0x0000000FU +#define I2S_TX_PDM_SINC_OSR2_M (I2S_TX_PDM_SINC_OSR2_V << I2S_TX_PDM_SINC_OSR2_S) +#define I2S_TX_PDM_SINC_OSR2_V 0x0000000FU +#define I2S_TX_PDM_SINC_OSR2_S 1 +/** I2S_TX_PDM_PRESCALE : R/W; bitpos: [12:5]; default: 0; + * I2S TX PDM prescale for sigmadelta + */ +#define I2S_TX_PDM_PRESCALE 0x000000FFU +#define I2S_TX_PDM_PRESCALE_M (I2S_TX_PDM_PRESCALE_V << I2S_TX_PDM_PRESCALE_S) +#define I2S_TX_PDM_PRESCALE_V 0x000000FFU +#define I2S_TX_PDM_PRESCALE_S 5 +/** I2S_TX_PDM_HP_IN_SHIFT : R/W; bitpos: [14:13]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ +#define I2S_TX_PDM_HP_IN_SHIFT 0x00000003U +#define I2S_TX_PDM_HP_IN_SHIFT_M (I2S_TX_PDM_HP_IN_SHIFT_V << I2S_TX_PDM_HP_IN_SHIFT_S) +#define I2S_TX_PDM_HP_IN_SHIFT_V 0x00000003U +#define I2S_TX_PDM_HP_IN_SHIFT_S 13 +/** I2S_TX_PDM_LP_IN_SHIFT : R/W; bitpos: [16:15]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ +#define I2S_TX_PDM_LP_IN_SHIFT 0x00000003U +#define I2S_TX_PDM_LP_IN_SHIFT_M (I2S_TX_PDM_LP_IN_SHIFT_V << I2S_TX_PDM_LP_IN_SHIFT_S) +#define I2S_TX_PDM_LP_IN_SHIFT_V 0x00000003U +#define I2S_TX_PDM_LP_IN_SHIFT_S 15 +/** I2S_TX_PDM_SINC_IN_SHIFT : R/W; bitpos: [18:17]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ +#define I2S_TX_PDM_SINC_IN_SHIFT 0x00000003U +#define I2S_TX_PDM_SINC_IN_SHIFT_M (I2S_TX_PDM_SINC_IN_SHIFT_V << I2S_TX_PDM_SINC_IN_SHIFT_S) +#define I2S_TX_PDM_SINC_IN_SHIFT_V 0x00000003U +#define I2S_TX_PDM_SINC_IN_SHIFT_S 17 +/** I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W; bitpos: [20:19]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT 0x00000003U +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M (I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V << I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S) +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V 0x00000003U +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S 19 +/** I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W; bitpos: [21]; default: 0; + * I2S TX PDM sigmadelta dither2 value + */ +#define I2S_TX_PDM_SIGMADELTA_DITHER2 (BIT(21)) +#define I2S_TX_PDM_SIGMADELTA_DITHER2_M (I2S_TX_PDM_SIGMADELTA_DITHER2_V << I2S_TX_PDM_SIGMADELTA_DITHER2_S) +#define I2S_TX_PDM_SIGMADELTA_DITHER2_V 0x00000001U +#define I2S_TX_PDM_SIGMADELTA_DITHER2_S 21 +/** I2S_TX_PDM_SIGMADELTA_DITHER : R/W; bitpos: [22]; default: 1; + * I2S TX PDM sigmadelta dither value + */ +#define I2S_TX_PDM_SIGMADELTA_DITHER (BIT(22)) +#define I2S_TX_PDM_SIGMADELTA_DITHER_M (I2S_TX_PDM_SIGMADELTA_DITHER_V << I2S_TX_PDM_SIGMADELTA_DITHER_S) +#define I2S_TX_PDM_SIGMADELTA_DITHER_V 0x00000001U +#define I2S_TX_PDM_SIGMADELTA_DITHER_S 22 +/** I2S_TX_PDM_DAC_2OUT_EN : R/W; bitpos: [23]; default: 0; + * I2S TX PDM dac mode enable + */ +#define I2S_TX_PDM_DAC_2OUT_EN (BIT(23)) +#define I2S_TX_PDM_DAC_2OUT_EN_M (I2S_TX_PDM_DAC_2OUT_EN_V << I2S_TX_PDM_DAC_2OUT_EN_S) +#define I2S_TX_PDM_DAC_2OUT_EN_V 0x00000001U +#define I2S_TX_PDM_DAC_2OUT_EN_S 23 +/** I2S_TX_PDM_DAC_MODE_EN : R/W; bitpos: [24]; default: 0; + * I2S TX PDM dac 2channel enable + */ +#define I2S_TX_PDM_DAC_MODE_EN (BIT(24)) +#define I2S_TX_PDM_DAC_MODE_EN_M (I2S_TX_PDM_DAC_MODE_EN_V << I2S_TX_PDM_DAC_MODE_EN_S) +#define I2S_TX_PDM_DAC_MODE_EN_V 0x00000001U +#define I2S_TX_PDM_DAC_MODE_EN_S 24 +/** I2S_PCM2PDM_CONV_EN : R/W; bitpos: [25]; default: 0; + * I2S TX PDM Converter enable + */ +#define I2S_PCM2PDM_CONV_EN (BIT(25)) +#define I2S_PCM2PDM_CONV_EN_M (I2S_PCM2PDM_CONV_EN_V << I2S_PCM2PDM_CONV_EN_S) +#define I2S_PCM2PDM_CONV_EN_V 0x00000001U +#define I2S_PCM2PDM_CONV_EN_S 25 + +/** I2S_TX_PCM2PDM_CONF1_REG register + * I2S TX PCM2PDM configuration register + */ +#define I2S_TX_PCM2PDM_CONF1_REG(i) (REG_I2S_BASE(i) + 0x44) +/** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960; + * I2S TX PDM Fp + */ +#define I2S_TX_PDM_FP 0x000003FFU +#define I2S_TX_PDM_FP_M (I2S_TX_PDM_FP_V << I2S_TX_PDM_FP_S) +#define I2S_TX_PDM_FP_V 0x000003FFU +#define I2S_TX_PDM_FP_S 0 +/** I2S_TX_PDM_FS : R/W; bitpos: [19:10]; default: 480; + * I2S TX PDM Fs + */ +#define I2S_TX_PDM_FS 0x000003FFU +#define I2S_TX_PDM_FS_M (I2S_TX_PDM_FS_V << I2S_TX_PDM_FS_S) +#define I2S_TX_PDM_FS_V 0x000003FFU +#define I2S_TX_PDM_FS_S 10 +/** I2S_TX_IIR_HP_MULT12_5 : R/W; bitpos: [22:20]; default: 7; + * The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + + * I2S_TX_IIR_HP_MULT12_5[2:0]) + */ +#define I2S_TX_IIR_HP_MULT12_5 0x00000007U +#define I2S_TX_IIR_HP_MULT12_5_M (I2S_TX_IIR_HP_MULT12_5_V << I2S_TX_IIR_HP_MULT12_5_S) +#define I2S_TX_IIR_HP_MULT12_5_V 0x00000007U +#define I2S_TX_IIR_HP_MULT12_5_S 20 +/** I2S_TX_IIR_HP_MULT12_0 : R/W; bitpos: [25:23]; default: 7; + * The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + + * I2S_TX_IIR_HP_MULT12_0[2:0]) + */ +#define I2S_TX_IIR_HP_MULT12_0 0x00000007U +#define I2S_TX_IIR_HP_MULT12_0_M (I2S_TX_IIR_HP_MULT12_0_V << I2S_TX_IIR_HP_MULT12_0_S) +#define I2S_TX_IIR_HP_MULT12_0_V 0x00000007U +#define I2S_TX_IIR_HP_MULT12_0_S 23 + +/** I2S_RX_TDM_CTRL_REG register + * I2S TX TDM mode control register + */ +#define I2S_RX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x50) +/** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN0_EN (BIT(0)) +#define I2S_RX_TDM_PDM_CHAN0_EN_M (I2S_RX_TDM_PDM_CHAN0_EN_V << I2S_RX_TDM_PDM_CHAN0_EN_S) +#define I2S_RX_TDM_PDM_CHAN0_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN0_EN_S 0 +/** I2S_RX_TDM_PDM_CHAN1_EN : R/W; bitpos: [1]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN1_EN (BIT(1)) +#define I2S_RX_TDM_PDM_CHAN1_EN_M (I2S_RX_TDM_PDM_CHAN1_EN_V << I2S_RX_TDM_PDM_CHAN1_EN_S) +#define I2S_RX_TDM_PDM_CHAN1_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN1_EN_S 1 +/** I2S_RX_TDM_PDM_CHAN2_EN : R/W; bitpos: [2]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN2_EN (BIT(2)) +#define I2S_RX_TDM_PDM_CHAN2_EN_M (I2S_RX_TDM_PDM_CHAN2_EN_V << I2S_RX_TDM_PDM_CHAN2_EN_S) +#define I2S_RX_TDM_PDM_CHAN2_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN2_EN_S 2 +/** I2S_RX_TDM_PDM_CHAN3_EN : R/W; bitpos: [3]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN3_EN (BIT(3)) +#define I2S_RX_TDM_PDM_CHAN3_EN_M (I2S_RX_TDM_PDM_CHAN3_EN_V << I2S_RX_TDM_PDM_CHAN3_EN_S) +#define I2S_RX_TDM_PDM_CHAN3_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN3_EN_S 3 +/** I2S_RX_TDM_PDM_CHAN4_EN : R/W; bitpos: [4]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN4_EN (BIT(4)) +#define I2S_RX_TDM_PDM_CHAN4_EN_M (I2S_RX_TDM_PDM_CHAN4_EN_V << I2S_RX_TDM_PDM_CHAN4_EN_S) +#define I2S_RX_TDM_PDM_CHAN4_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN4_EN_S 4 +/** I2S_RX_TDM_PDM_CHAN5_EN : R/W; bitpos: [5]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN5_EN (BIT(5)) +#define I2S_RX_TDM_PDM_CHAN5_EN_M (I2S_RX_TDM_PDM_CHAN5_EN_V << I2S_RX_TDM_PDM_CHAN5_EN_S) +#define I2S_RX_TDM_PDM_CHAN5_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN5_EN_S 5 +/** I2S_RX_TDM_PDM_CHAN6_EN : R/W; bitpos: [6]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN6_EN (BIT(6)) +#define I2S_RX_TDM_PDM_CHAN6_EN_M (I2S_RX_TDM_PDM_CHAN6_EN_V << I2S_RX_TDM_PDM_CHAN6_EN_S) +#define I2S_RX_TDM_PDM_CHAN6_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN6_EN_S 6 +/** I2S_RX_TDM_PDM_CHAN7_EN : R/W; bitpos: [7]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN7_EN (BIT(7)) +#define I2S_RX_TDM_PDM_CHAN7_EN_M (I2S_RX_TDM_PDM_CHAN7_EN_V << I2S_RX_TDM_PDM_CHAN7_EN_S) +#define I2S_RX_TDM_PDM_CHAN7_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN7_EN_S 7 +/** I2S_RX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN8_EN (BIT(8)) +#define I2S_RX_TDM_CHAN8_EN_M (I2S_RX_TDM_CHAN8_EN_V << I2S_RX_TDM_CHAN8_EN_S) +#define I2S_RX_TDM_CHAN8_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN8_EN_S 8 +/** I2S_RX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN9_EN (BIT(9)) +#define I2S_RX_TDM_CHAN9_EN_M (I2S_RX_TDM_CHAN9_EN_V << I2S_RX_TDM_CHAN9_EN_S) +#define I2S_RX_TDM_CHAN9_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN9_EN_S 9 +/** I2S_RX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN10_EN (BIT(10)) +#define I2S_RX_TDM_CHAN10_EN_M (I2S_RX_TDM_CHAN10_EN_V << I2S_RX_TDM_CHAN10_EN_S) +#define I2S_RX_TDM_CHAN10_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN10_EN_S 10 +/** I2S_RX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN11_EN (BIT(11)) +#define I2S_RX_TDM_CHAN11_EN_M (I2S_RX_TDM_CHAN11_EN_V << I2S_RX_TDM_CHAN11_EN_S) +#define I2S_RX_TDM_CHAN11_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN11_EN_S 11 +/** I2S_RX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN12_EN (BIT(12)) +#define I2S_RX_TDM_CHAN12_EN_M (I2S_RX_TDM_CHAN12_EN_V << I2S_RX_TDM_CHAN12_EN_S) +#define I2S_RX_TDM_CHAN12_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN12_EN_S 12 +/** I2S_RX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN13_EN (BIT(13)) +#define I2S_RX_TDM_CHAN13_EN_M (I2S_RX_TDM_CHAN13_EN_V << I2S_RX_TDM_CHAN13_EN_S) +#define I2S_RX_TDM_CHAN13_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN13_EN_S 13 +/** I2S_RX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN14_EN (BIT(14)) +#define I2S_RX_TDM_CHAN14_EN_M (I2S_RX_TDM_CHAN14_EN_V << I2S_RX_TDM_CHAN14_EN_S) +#define I2S_RX_TDM_CHAN14_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN14_EN_S 14 +/** I2S_RX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN15_EN (BIT(15)) +#define I2S_RX_TDM_CHAN15_EN_M (I2S_RX_TDM_CHAN15_EN_V << I2S_RX_TDM_CHAN15_EN_S) +#define I2S_RX_TDM_CHAN15_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN15_EN_S 15 +/** I2S_RX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0; + * The total channel number of I2S TX TDM mode. + */ +#define I2S_RX_TDM_TOT_CHAN_NUM 0x0000000FU +#define I2S_RX_TDM_TOT_CHAN_NUM_M (I2S_RX_TDM_TOT_CHAN_NUM_V << I2S_RX_TDM_TOT_CHAN_NUM_S) +#define I2S_RX_TDM_TOT_CHAN_NUM_V 0x0000000FU +#define I2S_RX_TDM_TOT_CHAN_NUM_S 16 + +/** I2S_TX_TDM_CTRL_REG register + * I2S TX TDM mode control register + */ +#define I2S_TX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x54) +/** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN0_EN (BIT(0)) +#define I2S_TX_TDM_CHAN0_EN_M (I2S_TX_TDM_CHAN0_EN_V << I2S_TX_TDM_CHAN0_EN_S) +#define I2S_TX_TDM_CHAN0_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN0_EN_S 0 +/** I2S_TX_TDM_CHAN1_EN : R/W; bitpos: [1]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN1_EN (BIT(1)) +#define I2S_TX_TDM_CHAN1_EN_M (I2S_TX_TDM_CHAN1_EN_V << I2S_TX_TDM_CHAN1_EN_S) +#define I2S_TX_TDM_CHAN1_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN1_EN_S 1 +/** I2S_TX_TDM_CHAN2_EN : R/W; bitpos: [2]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN2_EN (BIT(2)) +#define I2S_TX_TDM_CHAN2_EN_M (I2S_TX_TDM_CHAN2_EN_V << I2S_TX_TDM_CHAN2_EN_S) +#define I2S_TX_TDM_CHAN2_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN2_EN_S 2 +/** I2S_TX_TDM_CHAN3_EN : R/W; bitpos: [3]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN3_EN (BIT(3)) +#define I2S_TX_TDM_CHAN3_EN_M (I2S_TX_TDM_CHAN3_EN_V << I2S_TX_TDM_CHAN3_EN_S) +#define I2S_TX_TDM_CHAN3_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN3_EN_S 3 +/** I2S_TX_TDM_CHAN4_EN : R/W; bitpos: [4]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN4_EN (BIT(4)) +#define I2S_TX_TDM_CHAN4_EN_M (I2S_TX_TDM_CHAN4_EN_V << I2S_TX_TDM_CHAN4_EN_S) +#define I2S_TX_TDM_CHAN4_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN4_EN_S 4 +/** I2S_TX_TDM_CHAN5_EN : R/W; bitpos: [5]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN5_EN (BIT(5)) +#define I2S_TX_TDM_CHAN5_EN_M (I2S_TX_TDM_CHAN5_EN_V << I2S_TX_TDM_CHAN5_EN_S) +#define I2S_TX_TDM_CHAN5_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN5_EN_S 5 +/** I2S_TX_TDM_CHAN6_EN : R/W; bitpos: [6]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN6_EN (BIT(6)) +#define I2S_TX_TDM_CHAN6_EN_M (I2S_TX_TDM_CHAN6_EN_V << I2S_TX_TDM_CHAN6_EN_S) +#define I2S_TX_TDM_CHAN6_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN6_EN_S 6 +/** I2S_TX_TDM_CHAN7_EN : R/W; bitpos: [7]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN7_EN (BIT(7)) +#define I2S_TX_TDM_CHAN7_EN_M (I2S_TX_TDM_CHAN7_EN_V << I2S_TX_TDM_CHAN7_EN_S) +#define I2S_TX_TDM_CHAN7_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN7_EN_S 7 +/** I2S_TX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN8_EN (BIT(8)) +#define I2S_TX_TDM_CHAN8_EN_M (I2S_TX_TDM_CHAN8_EN_V << I2S_TX_TDM_CHAN8_EN_S) +#define I2S_TX_TDM_CHAN8_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN8_EN_S 8 +/** I2S_TX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN9_EN (BIT(9)) +#define I2S_TX_TDM_CHAN9_EN_M (I2S_TX_TDM_CHAN9_EN_V << I2S_TX_TDM_CHAN9_EN_S) +#define I2S_TX_TDM_CHAN9_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN9_EN_S 9 +/** I2S_TX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN10_EN (BIT(10)) +#define I2S_TX_TDM_CHAN10_EN_M (I2S_TX_TDM_CHAN10_EN_V << I2S_TX_TDM_CHAN10_EN_S) +#define I2S_TX_TDM_CHAN10_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN10_EN_S 10 +/** I2S_TX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN11_EN (BIT(11)) +#define I2S_TX_TDM_CHAN11_EN_M (I2S_TX_TDM_CHAN11_EN_V << I2S_TX_TDM_CHAN11_EN_S) +#define I2S_TX_TDM_CHAN11_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN11_EN_S 11 +/** I2S_TX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN12_EN (BIT(12)) +#define I2S_TX_TDM_CHAN12_EN_M (I2S_TX_TDM_CHAN12_EN_V << I2S_TX_TDM_CHAN12_EN_S) +#define I2S_TX_TDM_CHAN12_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN12_EN_S 12 +/** I2S_TX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN13_EN (BIT(13)) +#define I2S_TX_TDM_CHAN13_EN_M (I2S_TX_TDM_CHAN13_EN_V << I2S_TX_TDM_CHAN13_EN_S) +#define I2S_TX_TDM_CHAN13_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN13_EN_S 13 +/** I2S_TX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN14_EN (BIT(14)) +#define I2S_TX_TDM_CHAN14_EN_M (I2S_TX_TDM_CHAN14_EN_V << I2S_TX_TDM_CHAN14_EN_S) +#define I2S_TX_TDM_CHAN14_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN14_EN_S 14 +/** I2S_TX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN15_EN (BIT(15)) +#define I2S_TX_TDM_CHAN15_EN_M (I2S_TX_TDM_CHAN15_EN_V << I2S_TX_TDM_CHAN15_EN_S) +#define I2S_TX_TDM_CHAN15_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN15_EN_S 15 +/** I2S_TX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0; + * The total channel number of I2S TX TDM mode. + */ +#define I2S_TX_TDM_TOT_CHAN_NUM 0x0000000FU +#define I2S_TX_TDM_TOT_CHAN_NUM_M (I2S_TX_TDM_TOT_CHAN_NUM_V << I2S_TX_TDM_TOT_CHAN_NUM_S) +#define I2S_TX_TDM_TOT_CHAN_NUM_V 0x0000000FU +#define I2S_TX_TDM_TOT_CHAN_NUM_S 16 +/** I2S_TX_TDM_SKIP_MSK_EN : R/W; bitpos: [20]; default: 0; + * When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and + * only the data of the enabled channels is sent, then this bit should be set. Clear + * it when all the data stored in DMA TX buffer is for enabled channels. + */ +#define I2S_TX_TDM_SKIP_MSK_EN (BIT(20)) +#define I2S_TX_TDM_SKIP_MSK_EN_M (I2S_TX_TDM_SKIP_MSK_EN_V << I2S_TX_TDM_SKIP_MSK_EN_S) +#define I2S_TX_TDM_SKIP_MSK_EN_V 0x00000001U +#define I2S_TX_TDM_SKIP_MSK_EN_S 20 + +/** I2S_RX_TIMING_REG register + * I2S RX timing control register + */ +#define I2S_RX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x58) +/** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0; + * The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_SD_IN_DM 0x00000003U +#define I2S_RX_SD_IN_DM_M (I2S_RX_SD_IN_DM_V << I2S_RX_SD_IN_DM_S) +#define I2S_RX_SD_IN_DM_V 0x00000003U +#define I2S_RX_SD_IN_DM_S 0 +/** I2S_RX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0; + * The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_WS_OUT_DM 0x00000003U +#define I2S_RX_WS_OUT_DM_M (I2S_RX_WS_OUT_DM_V << I2S_RX_WS_OUT_DM_S) +#define I2S_RX_WS_OUT_DM_V 0x00000003U +#define I2S_RX_WS_OUT_DM_S 16 +/** I2S_RX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0; + * The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_BCK_OUT_DM 0x00000003U +#define I2S_RX_BCK_OUT_DM_M (I2S_RX_BCK_OUT_DM_V << I2S_RX_BCK_OUT_DM_S) +#define I2S_RX_BCK_OUT_DM_V 0x00000003U +#define I2S_RX_BCK_OUT_DM_S 20 +/** I2S_RX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0; + * The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_WS_IN_DM 0x00000003U +#define I2S_RX_WS_IN_DM_M (I2S_RX_WS_IN_DM_V << I2S_RX_WS_IN_DM_S) +#define I2S_RX_WS_IN_DM_V 0x00000003U +#define I2S_RX_WS_IN_DM_S 24 +/** I2S_RX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0; + * The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_BCK_IN_DM 0x00000003U +#define I2S_RX_BCK_IN_DM_M (I2S_RX_BCK_IN_DM_V << I2S_RX_BCK_IN_DM_S) +#define I2S_RX_BCK_IN_DM_V 0x00000003U +#define I2S_RX_BCK_IN_DM_S 28 + +/** I2S_TX_TIMING_REG register + * I2S TX timing control register + */ +#define I2S_TX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x5c) +/** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0; + * The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_SD_OUT_DM 0x00000003U +#define I2S_TX_SD_OUT_DM_M (I2S_TX_SD_OUT_DM_V << I2S_TX_SD_OUT_DM_S) +#define I2S_TX_SD_OUT_DM_V 0x00000003U +#define I2S_TX_SD_OUT_DM_S 0 +/** I2S_TX_SD1_OUT_DM : R/W; bitpos: [5:4]; default: 0; + * The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_SD1_OUT_DM 0x00000003U +#define I2S_TX_SD1_OUT_DM_M (I2S_TX_SD1_OUT_DM_V << I2S_TX_SD1_OUT_DM_S) +#define I2S_TX_SD1_OUT_DM_V 0x00000003U +#define I2S_TX_SD1_OUT_DM_S 4 +/** I2S_TX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0; + * The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_WS_OUT_DM 0x00000003U +#define I2S_TX_WS_OUT_DM_M (I2S_TX_WS_OUT_DM_V << I2S_TX_WS_OUT_DM_S) +#define I2S_TX_WS_OUT_DM_V 0x00000003U +#define I2S_TX_WS_OUT_DM_S 16 +/** I2S_TX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0; + * The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_BCK_OUT_DM 0x00000003U +#define I2S_TX_BCK_OUT_DM_M (I2S_TX_BCK_OUT_DM_V << I2S_TX_BCK_OUT_DM_S) +#define I2S_TX_BCK_OUT_DM_V 0x00000003U +#define I2S_TX_BCK_OUT_DM_S 20 +/** I2S_TX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0; + * The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_WS_IN_DM 0x00000003U +#define I2S_TX_WS_IN_DM_M (I2S_TX_WS_IN_DM_V << I2S_TX_WS_IN_DM_S) +#define I2S_TX_WS_IN_DM_V 0x00000003U +#define I2S_TX_WS_IN_DM_S 24 +/** I2S_TX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0; + * The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_BCK_IN_DM 0x00000003U +#define I2S_TX_BCK_IN_DM_M (I2S_TX_BCK_IN_DM_V << I2S_TX_BCK_IN_DM_S) +#define I2S_TX_BCK_IN_DM_V 0x00000003U +#define I2S_TX_BCK_IN_DM_S 28 + +/** I2S_LC_HUNG_CONF_REG register + * I2S HUNG configure register. + */ +#define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x60) +/** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16; + * the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered + * when fifo hung counter is equal to this value + */ +#define I2S_LC_FIFO_TIMEOUT 0x000000FFU +#define I2S_LC_FIFO_TIMEOUT_M (I2S_LC_FIFO_TIMEOUT_V << I2S_LC_FIFO_TIMEOUT_S) +#define I2S_LC_FIFO_TIMEOUT_V 0x000000FFU +#define I2S_LC_FIFO_TIMEOUT_S 0 +/** I2S_LC_FIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0; + * The bits are used to scale tick counter threshold. The tick counter is reset when + * counter value >= 88000/2^i2s_lc_fifo_timeout_shift + */ +#define I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007U +#define I2S_LC_FIFO_TIMEOUT_SHIFT_M (I2S_LC_FIFO_TIMEOUT_SHIFT_V << I2S_LC_FIFO_TIMEOUT_SHIFT_S) +#define I2S_LC_FIFO_TIMEOUT_SHIFT_V 0x00000007U +#define I2S_LC_FIFO_TIMEOUT_SHIFT_S 8 +/** I2S_LC_FIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1; + * The enable bit for FIFO timeout + */ +#define I2S_LC_FIFO_TIMEOUT_ENA (BIT(11)) +#define I2S_LC_FIFO_TIMEOUT_ENA_M (I2S_LC_FIFO_TIMEOUT_ENA_V << I2S_LC_FIFO_TIMEOUT_ENA_S) +#define I2S_LC_FIFO_TIMEOUT_ENA_V 0x00000001U +#define I2S_LC_FIFO_TIMEOUT_ENA_S 11 + +/** I2S_RXEOF_NUM_REG register + * I2S RX data number control register. + */ +#define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x64) +/** I2S_RX_EOF_NUM : R/W; bitpos: [11:0]; default: 64; + * The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + + * 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + */ +#define I2S_RX_EOF_NUM 0x00000FFFU +#define I2S_RX_EOF_NUM_M (I2S_RX_EOF_NUM_V << I2S_RX_EOF_NUM_S) +#define I2S_RX_EOF_NUM_V 0x00000FFFU +#define I2S_RX_EOF_NUM_S 0 + +/** I2S_CONF_SIGLE_DATA_REG register + * I2S signal data register + */ +#define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x68) +/** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0; + * The configured constant channel data to be sent out. + */ +#define I2S_SINGLE_DATA 0xFFFFFFFFU +#define I2S_SINGLE_DATA_M (I2S_SINGLE_DATA_V << I2S_SINGLE_DATA_S) +#define I2S_SINGLE_DATA_V 0xFFFFFFFFU +#define I2S_SINGLE_DATA_S 0 + +/** I2S_STATE_REG register + * I2S TX status register + */ +#define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x6c) +/** I2S_TX_IDLE : RO; bitpos: [0]; default: 1; + * 1: i2s_tx is idle state. 0: i2s_tx is working. + */ +#define I2S_TX_IDLE (BIT(0)) +#define I2S_TX_IDLE_M (I2S_TX_IDLE_V << I2S_TX_IDLE_S) +#define I2S_TX_IDLE_V 0x00000001U +#define I2S_TX_IDLE_S 0 + +/** I2S_ETM_CONF_REG register + * I2S ETM configure register + */ +#define I2S_ETM_CONF_REG(i) (REG_I2S_BASE(i) + 0x70) +/** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [9:0]; default: 64; + * I2S ETM send x words event. When sending word number of + * reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. + */ +#define I2S_ETM_TX_SEND_WORD_NUM 0x000003FFU +#define I2S_ETM_TX_SEND_WORD_NUM_M (I2S_ETM_TX_SEND_WORD_NUM_V << I2S_ETM_TX_SEND_WORD_NUM_S) +#define I2S_ETM_TX_SEND_WORD_NUM_V 0x000003FFU +#define I2S_ETM_TX_SEND_WORD_NUM_S 0 +/** I2S_ETM_RX_RECEIVE_WORD_NUM : R/W; bitpos: [19:10]; default: 64; + * I2S ETM receive x words event. When receiving word number of + * reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. + */ +#define I2S_ETM_RX_RECEIVE_WORD_NUM 0x000003FFU +#define I2S_ETM_RX_RECEIVE_WORD_NUM_M (I2S_ETM_RX_RECEIVE_WORD_NUM_V << I2S_ETM_RX_RECEIVE_WORD_NUM_S) +#define I2S_ETM_RX_RECEIVE_WORD_NUM_V 0x000003FFU +#define I2S_ETM_RX_RECEIVE_WORD_NUM_S 10 + +/** I2S_DATE_REG register + * Version control register + */ +#define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0x80) +/** I2S_DATE : R/W; bitpos: [27:0]; default: 35655792; + * I2S version control register + */ +#define I2S_DATE 0x0FFFFFFFU +#define I2S_DATE_M (I2S_DATE_V << I2S_DATE_S) +#define I2S_DATE_V 0x0FFFFFFFU +#define I2S_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/i2s_struct.h b/components/soc/esp32c6/include/soc/i2s_struct.h new file mode 100644 index 0000000000..4b019c334a --- /dev/null +++ b/components/soc/esp32c6/include/soc/i2s_struct.h @@ -0,0 +1,1024 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Interrupt registers */ +/** Type of int_raw register + * I2S interrupt raw register, valid in level. + */ +typedef union { + struct { + /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_raw:1; + /** tx_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the i2s_tx_done_int interrupt + */ + uint32_t tx_done_int_raw:1; + /** rx_hung_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_raw:1; + /** tx_hung_int_raw : RO/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the i2s_tx_hung_int interrupt + */ + uint32_t tx_hung_int_raw:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} i2s_int_raw_reg_t; + +/** Type of int_st register + * I2S interrupt status register. + */ +typedef union { + struct { + /** rx_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_st:1; + /** tx_done_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the i2s_tx_done_int interrupt + */ + uint32_t tx_done_int_st:1; + /** rx_hung_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_st:1; + /** tx_hung_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the i2s_tx_hung_int interrupt + */ + uint32_t tx_hung_int_st:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} i2s_int_st_reg_t; + +/** Type of int_ena register + * I2S interrupt enable register. + */ +typedef union { + struct { + /** rx_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_ena:1; + /** tx_done_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the i2s_tx_done_int interrupt + */ + uint32_t tx_done_int_ena:1; + /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_ena:1; + /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the i2s_tx_hung_int interrupt + */ + uint32_t tx_hung_int_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} i2s_int_ena_reg_t; + +/** Type of int_clr register + * I2S interrupt clear register. + */ +typedef union { + struct { + /** rx_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_clr:1; + /** tx_done_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the i2s_tx_done_int interrupt + */ + uint32_t tx_done_int_clr:1; + /** rx_hung_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_clr:1; + /** tx_hung_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the i2s_tx_hung_int interrupt + */ + uint32_t tx_hung_int_clr:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} i2s_int_clr_reg_t; + + +/** Group: RX Control and configuration registers */ +/** Type of rx_conf register + * I2S RX configure register + */ +typedef union { + struct { + /** rx_reset : WT; bitpos: [0]; default: 0; + * Set this bit to reset receiver + */ + uint32_t rx_reset:1; + /** rx_fifo_reset : WT; bitpos: [1]; default: 0; + * Set this bit to reset Rx AFIFO + */ + uint32_t rx_fifo_reset:1; + /** rx_start : R/W/SC; bitpos: [2]; default: 0; + * Set this bit to start receiving data + */ + uint32_t rx_start:1; + /** rx_slave_mod : R/W; bitpos: [3]; default: 0; + * Set this bit to enable slave receiver mode + */ + uint32_t rx_slave_mod:1; + uint32_t reserved_4:1; + /** rx_mono : R/W; bitpos: [5]; default: 0; + * Set this bit to enable receiver in mono mode + */ + uint32_t rx_mono:1; + uint32_t reserved_6:1; + /** rx_big_endian : R/W; bitpos: [7]; default: 0; + * I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + */ + uint32_t rx_big_endian:1; + /** rx_update : R/W/SC; bitpos: [8]; default: 0; + * Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This + * bit will be cleared by hardware after update register done. + */ + uint32_t rx_update:1; + /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1; + * 1: The first channel data value is valid in I2S RX mono mode. 0: The second + * channel data value is valid in I2S RX mono mode. + */ + uint32_t rx_mono_fst_vld:1; + /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1; + * I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 + * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + */ + uint32_t rx_pcm_conf:2; + /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1; + * Set this bit to bypass Compress/Decompress module for received data. + */ + uint32_t rx_pcm_bypass:1; + /** rx_stop_mode : R/W; bitpos: [14:13]; default: 0; + * 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is + * 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + */ + uint32_t rx_stop_mode:2; + /** rx_left_align : R/W; bitpos: [15]; default: 1; + * 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + */ + uint32_t rx_left_align:1; + /** rx_24_fill_en : R/W; bitpos: [16]; default: 0; + * 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + */ + uint32_t rx_24_fill_en:1; + /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0; + * 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. + * 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + */ + uint32_t rx_ws_idle_pol:1; + /** rx_bit_order : R/W; bitpos: [18]; default: 0; + * I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB + * is received first. + */ + uint32_t rx_bit_order:1; + /** rx_tdm_en : R/W; bitpos: [19]; default: 0; + * 1: Enable I2S TDM Rx mode . 0: Disable. + */ + uint32_t rx_tdm_en:1; + /** rx_pdm_en : R/W; bitpos: [20]; default: 0; + * 1: Enable I2S PDM Rx mode . 0: Disable. + */ + uint32_t rx_pdm_en:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} i2s_rx_conf_reg_t; + +/** Type of rx_conf1 register + * I2S RX configure register 1 + */ +typedef union { + struct { + /** rx_tdm_ws_width : R/W; bitpos: [6:0]; default: 0; + * The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck + */ + uint32_t rx_tdm_ws_width:7; + /** rx_bck_div_num : R/W; bitpos: [12:7]; default: 6; + * Bit clock configuration bits in receiver mode. + */ + uint32_t rx_bck_div_num:6; + /** rx_bits_mod : R/W; bitpos: [17:13]; default: 15; + * Set the bits to configure the valid data bit length of I2S receiver channel. 7: all + * the valid channel data is in 8-bit-mode. 15: all the valid channel data is in + * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid + * channel data is in 32-bit-mode. + */ + uint32_t rx_bits_mod:5; + /** rx_half_sample_bits : R/W; bitpos: [23:18]; default: 15; + * I2S Rx half sample bits -1. + */ + uint32_t rx_half_sample_bits:6; + /** rx_tdm_chan_bits : R/W; bitpos: [28:24]; default: 15; + * The Rx bit number for each channel minus 1in TDM mode. + */ + uint32_t rx_tdm_chan_bits:5; + /** rx_msb_shift : R/W; bitpos: [29]; default: 1; + * Set this bit to enable receiver in Phillips standard mode + */ + uint32_t rx_msb_shift:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} i2s_rx_conf1_reg_t; + +/** Type of rx_clkm_conf register + * I2S RX clock configure register + */ +typedef union { + struct { + /** rx_clkm_div_num : R/W; bitpos: [7:0]; default: 2; + * Integral I2S clock divider value + */ + uint32_t rx_clkm_div_num:8; + uint32_t reserved_8:18; + /** rx_clk_active : R/W; bitpos: [26]; default: 0; + * I2S Rx module clock enable signal. + */ + uint32_t rx_clk_active:1; + /** rx_clk_sel : R/W; bitpos: [28:27]; default: 0; + * Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in. + */ + uint32_t rx_clk_sel:2; + /** mclk_sel : R/W; bitpos: [29]; default: 0; + * 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as + * I2S_MCLK_OUT. + */ + uint32_t mclk_sel:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} i2s_rx_clkm_conf_reg_t; + +/** Type of tx_pcm2pdm_conf register + * I2S TX PCM2PDM configuration register + */ +typedef union { + struct { + /** tx_pdm_hp_bypass : R/W; bitpos: [0]; default: 0; + * I2S TX PDM bypass hp filter or not. The option has been removed. + */ + uint32_t tx_pdm_hp_bypass:1; + /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2; + * I2S TX PDM OSR2 value + */ + uint32_t tx_pdm_sinc_osr2:4; + /** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0; + * I2S TX PDM prescale for sigmadelta + */ + uint32_t tx_pdm_prescale:8; + /** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ + uint32_t tx_pdm_hp_in_shift:2; + /** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ + uint32_t tx_pdm_lp_in_shift:2; + /** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ + uint32_t tx_pdm_sinc_in_shift:2; + /** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ + uint32_t tx_pdm_sigmadelta_in_shift:2; + /** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0; + * I2S TX PDM sigmadelta dither2 value + */ + uint32_t tx_pdm_sigmadelta_dither2:1; + /** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1; + * I2S TX PDM sigmadelta dither value + */ + uint32_t tx_pdm_sigmadelta_dither:1; + /** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0; + * I2S TX PDM dac mode enable + */ + uint32_t tx_pdm_dac_2out_en:1; + /** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0; + * I2S TX PDM dac 2channel enable + */ + uint32_t tx_pdm_dac_mode_en:1; + /** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0; + * I2S TX PDM Converter enable + */ + uint32_t pcm2pdm_conv_en:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} i2s_tx_pcm2pdm_conf_reg_t; + +/** Type of tx_pcm2pdm_conf1 register + * I2S TX PCM2PDM configuration register + */ +typedef union { + struct { + /** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960; + * I2S TX PDM Fp + */ + uint32_t tx_pdm_fp:10; + /** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480; + * I2S TX PDM Fs + */ + uint32_t tx_pdm_fs:10; + /** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7; + * The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + + * I2S_TX_IIR_HP_MULT12_5[2:0]) + */ + uint32_t tx_iir_hp_mult12_5:3; + /** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7; + * The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + + * I2S_TX_IIR_HP_MULT12_0[2:0]) + */ + uint32_t tx_iir_hp_mult12_0:3; + uint32_t reserved_26:6; + }; + uint32_t val; +} i2s_tx_pcm2pdm_conf1_reg_t; + +/** Type of rx_tdm_ctrl register + * I2S TX TDM mode control register + */ +typedef union { + struct { + /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan0_en:1; + /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan1_en:1; + /** rx_tdm_pdm_chan2_en : R/W; bitpos: [2]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan2_en:1; + /** rx_tdm_pdm_chan3_en : R/W; bitpos: [3]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan3_en:1; + /** rx_tdm_pdm_chan4_en : R/W; bitpos: [4]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan4_en:1; + /** rx_tdm_pdm_chan5_en : R/W; bitpos: [5]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan5_en:1; + /** rx_tdm_pdm_chan6_en : R/W; bitpos: [6]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan6_en:1; + /** rx_tdm_pdm_chan7_en : R/W; bitpos: [7]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan7_en:1; + /** rx_tdm_chan8_en : R/W; bitpos: [8]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan8_en:1; + /** rx_tdm_chan9_en : R/W; bitpos: [9]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan9_en:1; + /** rx_tdm_chan10_en : R/W; bitpos: [10]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan10_en:1; + /** rx_tdm_chan11_en : R/W; bitpos: [11]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan11_en:1; + /** rx_tdm_chan12_en : R/W; bitpos: [12]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan12_en:1; + /** rx_tdm_chan13_en : R/W; bitpos: [13]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan13_en:1; + /** rx_tdm_chan14_en : R/W; bitpos: [14]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan14_en:1; + /** rx_tdm_chan15_en : R/W; bitpos: [15]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan15_en:1; + /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0; + * The total channel number of I2S TX TDM mode. + */ + uint32_t rx_tdm_tot_chan_num:4; + uint32_t reserved_20:12; + }; + uint32_t val; +} i2s_rx_tdm_ctrl_reg_t; + +/** Type of rx_eof_num register + * I2S RX data number control register. + */ +typedef union { + struct { + /** rx_eof_num : R/W; bitpos: [11:0]; default: 64; + * The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + + * 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + */ + uint32_t rx_eof_num:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} i2s_rx_eof_num_reg_t; + + +/** Group: TX Control and configuration registers */ +/** Type of tx_conf register + * I2S TX configure register + */ +typedef union { + struct { + /** tx_reset : WT; bitpos: [0]; default: 0; + * Set this bit to reset transmitter + */ + uint32_t tx_reset:1; + /** tx_fifo_reset : WT; bitpos: [1]; default: 0; + * Set this bit to reset Tx AFIFO + */ + uint32_t tx_fifo_reset:1; + /** tx_start : R/W/SC; bitpos: [2]; default: 0; + * Set this bit to start transmitting data + */ + uint32_t tx_start:1; + /** tx_slave_mod : R/W; bitpos: [3]; default: 0; + * Set this bit to enable slave transmitter mode + */ + uint32_t tx_slave_mod:1; + uint32_t reserved_4:1; + /** tx_mono : R/W; bitpos: [5]; default: 0; + * Set this bit to enable transmitter in mono mode + */ + uint32_t tx_mono:1; + /** tx_chan_equal : R/W; bitpos: [6]; default: 0; + * 1: The value of Left channel data is equal to the value of right channel data in + * I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is + * reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. + */ + uint32_t tx_chan_equal:1; + /** tx_big_endian : R/W; bitpos: [7]; default: 0; + * I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr + * value. + */ + uint32_t tx_big_endian:1; + /** tx_update : R/W/SC; bitpos: [8]; default: 0; + * Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This + * bit will be cleared by hardware after update register done. + */ + uint32_t tx_update:1; + /** tx_mono_fst_vld : R/W; bitpos: [9]; default: 1; + * 1: The first channel data value is valid in I2S TX mono mode. 0: The second + * channel data value is valid in I2S TX mono mode. + */ + uint32_t tx_mono_fst_vld:1; + /** tx_pcm_conf : R/W; bitpos: [11:10]; default: 0; + * I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 + * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + */ + uint32_t tx_pcm_conf:2; + /** tx_pcm_bypass : R/W; bitpos: [12]; default: 1; + * Set this bit to bypass Compress/Decompress module for transmitted data. + */ + uint32_t tx_pcm_bypass:1; + /** tx_stop_en : R/W; bitpos: [13]; default: 1; + * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + */ + uint32_t tx_stop_en:1; + uint32_t reserved_14:1; + /** tx_left_align : R/W; bitpos: [15]; default: 1; + * 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + */ + uint32_t tx_left_align:1; + /** tx_24_fill_en : R/W; bitpos: [16]; default: 0; + * 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + */ + uint32_t tx_24_fill_en:1; + /** tx_ws_idle_pol : R/W; bitpos: [17]; default: 0; + * 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: + * WS should be 1 when sending left channel data, and WS is 0in right channel. + */ + uint32_t tx_ws_idle_pol:1; + /** tx_bit_order : R/W; bitpos: [18]; default: 0; + * I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is + * sent first. + */ + uint32_t tx_bit_order:1; + /** tx_tdm_en : R/W; bitpos: [19]; default: 0; + * 1: Enable I2S TDM Tx mode . 0: Disable. + */ + uint32_t tx_tdm_en:1; + /** tx_pdm_en : R/W; bitpos: [20]; default: 0; + * 1: Enable I2S PDM Tx mode . 0: Disable. + */ + uint32_t tx_pdm_en:1; + uint32_t reserved_21:3; + /** tx_chan_mod : R/W; bitpos: [26:24]; default: 0; + * I2S transmitter channel mode configuration bits. + */ + uint32_t tx_chan_mod:3; + /** sig_loopback : R/W; bitpos: [27]; default: 0; + * Enable signal loop back mode with transmitter module and receiver module sharing + * the same WS and BCK signals. + */ + uint32_t sig_loopback:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} i2s_tx_conf_reg_t; + +/** Type of tx_conf1 register + * I2S TX configure register 1 + */ +typedef union { + struct { + /** tx_tdm_ws_width : R/W; bitpos: [6:0]; default: 0; + * The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck + */ + uint32_t tx_tdm_ws_width:7; + /** tx_bck_div_num : R/W; bitpos: [12:7]; default: 6; + * Bit clock configuration bits in transmitter mode. + */ + uint32_t tx_bck_div_num:6; + /** tx_bits_mod : R/W; bitpos: [17:13]; default: 15; + * Set the bits to configure the valid data bit length of I2S transmitter channel. 7: + * all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in + * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid + * channel data is in 32-bit-mode. + */ + uint32_t tx_bits_mod:5; + /** tx_half_sample_bits : R/W; bitpos: [23:18]; default: 15; + * I2S Tx half sample bits -1. + */ + uint32_t tx_half_sample_bits:6; + /** tx_tdm_chan_bits : R/W; bitpos: [28:24]; default: 15; + * The Tx bit number for each channel minus 1in TDM mode. + */ + uint32_t tx_tdm_chan_bits:5; + /** tx_msb_shift : R/W; bitpos: [29]; default: 1; + * Set this bit to enable transmitter in Phillips standard mode + */ + uint32_t tx_msb_shift:1; + /** tx_bck_no_dly : R/W; bitpos: [30]; default: 1; + * 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to + * generate pos/neg edge in master mode. + */ + uint32_t tx_bck_no_dly:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} i2s_tx_conf1_reg_t; + +/** Type of tx_clkm_conf register + * I2S TX clock configure register + */ +typedef union { + struct { + /** tx_clkm_div_num : R/W; bitpos: [7:0]; default: 2; + * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be + * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= + * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * + * (n+1)-div] + y * (n+1)-div. + */ + uint32_t tx_clkm_div_num:8; + uint32_t reserved_8:18; + /** tx_clk_active : R/W; bitpos: [26]; default: 0; + * I2S Tx module clock enable signal. + */ + uint32_t tx_clk_active:1; + /** tx_clk_sel : R/W; bitpos: [28:27]; default: 0; + * Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: + * I2S_MCLK_in. + */ + uint32_t tx_clk_sel:2; + /** clk_en : R/W; bitpos: [29]; default: 0; + * Set this bit to enable clk gate + */ + uint32_t clk_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} i2s_tx_clkm_conf_reg_t; + +/** Type of tx_tdm_ctrl register + * I2S TX TDM mode control register + */ +typedef union { + struct { + /** tx_tdm_chan0_en : R/W; bitpos: [0]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan0_en:1; + /** tx_tdm_chan1_en : R/W; bitpos: [1]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan1_en:1; + /** tx_tdm_chan2_en : R/W; bitpos: [2]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan2_en:1; + /** tx_tdm_chan3_en : R/W; bitpos: [3]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan3_en:1; + /** tx_tdm_chan4_en : R/W; bitpos: [4]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan4_en:1; + /** tx_tdm_chan5_en : R/W; bitpos: [5]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan5_en:1; + /** tx_tdm_chan6_en : R/W; bitpos: [6]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan6_en:1; + /** tx_tdm_chan7_en : R/W; bitpos: [7]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan7_en:1; + /** tx_tdm_chan8_en : R/W; bitpos: [8]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan8_en:1; + /** tx_tdm_chan9_en : R/W; bitpos: [9]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan9_en:1; + /** tx_tdm_chan10_en : R/W; bitpos: [10]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan10_en:1; + /** tx_tdm_chan11_en : R/W; bitpos: [11]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan11_en:1; + /** tx_tdm_chan12_en : R/W; bitpos: [12]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan12_en:1; + /** tx_tdm_chan13_en : R/W; bitpos: [13]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan13_en:1; + /** tx_tdm_chan14_en : R/W; bitpos: [14]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan14_en:1; + /** tx_tdm_chan15_en : R/W; bitpos: [15]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan15_en:1; + /** tx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0; + * The total channel number of I2S TX TDM mode. + */ + uint32_t tx_tdm_tot_chan_num:4; + /** tx_tdm_skip_msk_en : R/W; bitpos: [20]; default: 0; + * When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and + * only the data of the enabled channels is sent, then this bit should be set. Clear + * it when all the data stored in DMA TX buffer is for enabled channels. + */ + uint32_t tx_tdm_skip_msk_en:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} i2s_tx_tdm_ctrl_reg_t; + + +/** Group: RX clock and timing registers */ +/** Type of rx_clkm_div_conf register + * I2S RX module clock divider configure register + */ +typedef union { + struct { + /** rx_clkm_div_z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_RX_CLKM_DIV_Z is (a-b). + */ + uint32_t rx_clkm_div_z:9; + /** rx_clkm_div_y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_RX_CLKM_DIV_Y is (a%(a-b)). + */ + uint32_t rx_clkm_div_y:9; + /** rx_clkm_div_x : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + */ + uint32_t rx_clkm_div_x:9; + /** rx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_RX_CLKM_DIV_YN1 is 1. + */ + uint32_t rx_clkm_div_yn1:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} i2s_rx_clkm_div_conf_reg_t; + +/** Type of rx_timing register + * I2S RX timing control register + */ +typedef union { + struct { + /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0; + * The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_sd_in_dm:2; + uint32_t reserved_2:14; + /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0; + * The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_ws_out_dm:2; + uint32_t reserved_18:2; + /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0; + * The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_bck_out_dm:2; + uint32_t reserved_22:2; + /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0; + * The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_ws_in_dm:2; + uint32_t reserved_26:2; + /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0; + * The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_bck_in_dm:2; + uint32_t reserved_30:2; + }; + uint32_t val; +} i2s_rx_timing_reg_t; + + +/** Group: TX clock and timing registers */ +/** Type of tx_clkm_div_conf register + * I2S TX module clock divider configure register + */ +typedef union { + struct { + /** tx_clkm_div_z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_TX_CLKM_DIV_Z is (a-b). + */ + uint32_t tx_clkm_div_z:9; + /** tx_clkm_div_y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_TX_CLKM_DIV_Y is (a%(a-b)). + */ + uint32_t tx_clkm_div_y:9; + /** tx_clkm_div_x : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + */ + uint32_t tx_clkm_div_x:9; + /** tx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_TX_CLKM_DIV_YN1 is 1. + */ + uint32_t tx_clkm_div_yn1:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} i2s_tx_clkm_div_conf_reg_t; + +/** Type of tx_timing register + * I2S TX timing control register + */ +typedef union { + struct { + /** tx_sd_out_dm : R/W; bitpos: [1:0]; default: 0; + * The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_sd_out_dm:2; + uint32_t reserved_2:2; + /** tx_sd1_out_dm : R/W; bitpos: [5:4]; default: 0; + * The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_sd1_out_dm:2; + uint32_t reserved_6:10; + /** tx_ws_out_dm : R/W; bitpos: [17:16]; default: 0; + * The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_ws_out_dm:2; + uint32_t reserved_18:2; + /** tx_bck_out_dm : R/W; bitpos: [21:20]; default: 0; + * The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_bck_out_dm:2; + uint32_t reserved_22:2; + /** tx_ws_in_dm : R/W; bitpos: [25:24]; default: 0; + * The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_ws_in_dm:2; + uint32_t reserved_26:2; + /** tx_bck_in_dm : R/W; bitpos: [29:28]; default: 0; + * The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_bck_in_dm:2; + uint32_t reserved_30:2; + }; + uint32_t val; +} i2s_tx_timing_reg_t; + + +/** Group: Control and configuration registers */ +/** Type of lc_hung_conf register + * I2S HUNG configure register. + */ +typedef union { + struct { + /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16; + * the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered + * when fifo hung counter is equal to this value + */ + uint32_t lc_fifo_timeout:8; + /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0; + * The bits are used to scale tick counter threshold. The tick counter is reset when + * counter value >= 88000/2^i2s_lc_fifo_timeout_shift + */ + uint32_t lc_fifo_timeout_shift:3; + /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1; + * The enable bit for FIFO timeout + */ + uint32_t lc_fifo_timeout_ena:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} i2s_lc_hung_conf_reg_t; + +/** Type of conf_single_data register + * I2S signal data register + */ +typedef union { + struct { + /** single_data : R/W; bitpos: [31:0]; default: 0; + * The configured constant channel data to be sent out. + */ + uint32_t single_data:32; + }; + uint32_t val; +} i2s_conf_single_data_reg_t; + + +/** Group: TX status registers */ +/** Type of state register + * I2S TX status register + */ +typedef union { + struct { + /** tx_idle : RO; bitpos: [0]; default: 1; + * 1: i2s_tx is idle state. 0: i2s_tx is working. + */ + uint32_t tx_idle:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} i2s_state_reg_t; + + +/** Group: ETM registers */ +/** Type of etm_conf register + * I2S ETM configure register + */ +typedef union { + struct { + /** etm_tx_send_word_num : R/W; bitpos: [9:0]; default: 64; + * I2S ETM send x words event. When sending word number of + * reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. + */ + uint32_t etm_tx_send_word_num:10; + /** etm_rx_receive_word_num : R/W; bitpos: [19:10]; default: 64; + * I2S ETM receive x words event. When receiving word number of + * reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. + */ + uint32_t etm_rx_receive_word_num:10; + uint32_t reserved_20:12; + }; + uint32_t val; +} i2s_etm_conf_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35655792; + * I2S version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} i2s_date_reg_t; + + +typedef struct i2s_dev_t { + uint32_t reserved_000[3]; + volatile i2s_int_raw_reg_t int_raw; + volatile i2s_int_st_reg_t int_st; + volatile i2s_int_ena_reg_t int_ena; + volatile i2s_int_clr_reg_t int_clr; + uint32_t reserved_01c; + volatile i2s_rx_conf_reg_t rx_conf; + volatile i2s_tx_conf_reg_t tx_conf; + volatile i2s_rx_conf1_reg_t rx_conf1; + volatile i2s_tx_conf1_reg_t tx_conf1; + volatile i2s_rx_clkm_conf_reg_t rx_clkm_conf; + volatile i2s_tx_clkm_conf_reg_t tx_clkm_conf; + volatile i2s_rx_clkm_div_conf_reg_t rx_clkm_div_conf; + volatile i2s_tx_clkm_div_conf_reg_t tx_clkm_div_conf; + volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf; + volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1; + uint32_t reserved_048[2]; + volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl; + volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl; + volatile i2s_rx_timing_reg_t rx_timing; + volatile i2s_tx_timing_reg_t tx_timing; + volatile i2s_lc_hung_conf_reg_t lc_hung_conf; + volatile i2s_rx_eof_num_reg_t rx_eof_num; + volatile i2s_conf_single_data_reg_t conf_single_data; + volatile i2s_state_reg_t state; + volatile i2s_etm_conf_reg_t etm_conf; + uint32_t reserved_074[3]; + volatile i2s_date_reg_t date; +} i2s_dev_t; + +extern i2s_dev_t I2S0; + +#ifndef __cplusplus +_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/interrupt_matrix_reg.h b/components/soc/esp32c6/include/soc/interrupt_matrix_reg.h new file mode 100644 index 0000000000..d5af256a4d --- /dev/null +++ b/components/soc/esp32c6/include/soc/interrupt_matrix_reg.h @@ -0,0 +1,999 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** INTMTX_CORE0_WIFI_MAC_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x0) +/** INTMTX_CORE0_WIFI_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_WIFI_MAC_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_M (INTMTX_CORE0_WIFI_MAC_INTR_MAP_V << INTMTX_CORE0_WIFI_MAC_INTR_MAP_S) +#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_S 0 + +/** INTMTX_CORE0_WIFI_MAC_NMI_MAP_REG register + * register description + */ +#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4) +/** INTMTX_CORE0_WIFI_MAC_NMI_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_WIFI_MAC_NMI_MAP 0x0000001FU +#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_M (INTMTX_CORE0_WIFI_MAC_NMI_MAP_V << INTMTX_CORE0_WIFI_MAC_NMI_MAP_S) +#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_V 0x0000001FU +#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_S 0 + +/** INTMTX_CORE0_WIFI_PWR_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8) +/** INTMTX_CORE0_WIFI_PWR_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_WIFI_PWR_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_M (INTMTX_CORE0_WIFI_PWR_INTR_MAP_V << INTMTX_CORE0_WIFI_PWR_INTR_MAP_S) +#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_S 0 + +/** INTMTX_CORE0_WIFI_BB_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_WIFI_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc) +/** INTMTX_CORE0_WIFI_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_WIFI_BB_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_WIFI_BB_INTR_MAP_M (INTMTX_CORE0_WIFI_BB_INTR_MAP_V << INTMTX_CORE0_WIFI_BB_INTR_MAP_S) +#define INTMTX_CORE0_WIFI_BB_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_WIFI_BB_INTR_MAP_S 0 + +/** INTMTX_CORE0_BT_MAC_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10) +/** INTMTX_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_BT_MAC_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_BT_MAC_INTR_MAP_M (INTMTX_CORE0_BT_MAC_INTR_MAP_V << INTMTX_CORE0_BT_MAC_INTR_MAP_S) +#define INTMTX_CORE0_BT_MAC_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_BT_MAC_INTR_MAP_S 0 + +/** INTMTX_CORE0_BT_BB_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x14) +/** INTMTX_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_BT_BB_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_BT_BB_INTR_MAP_M (INTMTX_CORE0_BT_BB_INTR_MAP_V << INTMTX_CORE0_BT_BB_INTR_MAP_S) +#define INTMTX_CORE0_BT_BB_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_BT_BB_INTR_MAP_S 0 + +/** INTMTX_CORE0_BT_BB_NMI_MAP_REG register + * register description + */ +#define INTMTX_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x18) +/** INTMTX_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_BT_BB_NMI_MAP 0x0000001FU +#define INTMTX_CORE0_BT_BB_NMI_MAP_M (INTMTX_CORE0_BT_BB_NMI_MAP_V << INTMTX_CORE0_BT_BB_NMI_MAP_S) +#define INTMTX_CORE0_BT_BB_NMI_MAP_V 0x0000001FU +#define INTMTX_CORE0_BT_BB_NMI_MAP_S 0 + +/** INTMTX_CORE0_LP_TIMER_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_LP_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x1c) +/** INTMTX_CORE0_LP_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_LP_TIMER_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_LP_TIMER_INTR_MAP_M (INTMTX_CORE0_LP_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_TIMER_INTR_MAP_S) +#define INTMTX_CORE0_LP_TIMER_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_LP_TIMER_INTR_MAP_S 0 + +/** INTMTX_CORE0_COEX_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x20) +/** INTMTX_CORE0_COEX_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_COEX_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_COEX_INTR_MAP_M (INTMTX_CORE0_COEX_INTR_MAP_V << INTMTX_CORE0_COEX_INTR_MAP_S) +#define INTMTX_CORE0_COEX_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_COEX_INTR_MAP_S 0 + +/** INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x24) +/** INTMTX_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_BLE_TIMER_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_M (INTMTX_CORE0_BLE_TIMER_INTR_MAP_V << INTMTX_CORE0_BLE_TIMER_INTR_MAP_S) +#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_S 0 + +/** INTMTX_CORE0_BLE_SEC_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x28) +/** INTMTX_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_BLE_SEC_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_BLE_SEC_INTR_MAP_M (INTMTX_CORE0_BLE_SEC_INTR_MAP_V << INTMTX_CORE0_BLE_SEC_INTR_MAP_S) +#define INTMTX_CORE0_BLE_SEC_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_BLE_SEC_INTR_MAP_S 0 + +/** INTMTX_CORE0_I2C_MST_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_I2C_MST_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x2c) +/** INTMTX_CORE0_I2C_MST_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_I2C_MST_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_I2C_MST_INTR_MAP_M (INTMTX_CORE0_I2C_MST_INTR_MAP_V << INTMTX_CORE0_I2C_MST_INTR_MAP_S) +#define INTMTX_CORE0_I2C_MST_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_I2C_MST_INTR_MAP_S 0 + +/** INTMTX_CORE0_ZB_MAC_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x30) +/** INTMTX_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_ZB_MAC_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_ZB_MAC_INTR_MAP_M (INTMTX_CORE0_ZB_MAC_INTR_MAP_V << INTMTX_CORE0_ZB_MAC_INTR_MAP_S) +#define INTMTX_CORE0_ZB_MAC_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_ZB_MAC_INTR_MAP_S 0 + +/** INTMTX_CORE0_PMU_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x34) +/** INTMTX_CORE0_PMU_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_PMU_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_PMU_INTR_MAP_M (INTMTX_CORE0_PMU_INTR_MAP_V << INTMTX_CORE0_PMU_INTR_MAP_S) +#define INTMTX_CORE0_PMU_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_PMU_INTR_MAP_S 0 + +/** INTMTX_CORE0_EFUSE_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x38) +/** INTMTX_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_EFUSE_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_EFUSE_INTR_MAP_M (INTMTX_CORE0_EFUSE_INTR_MAP_V << INTMTX_CORE0_EFUSE_INTR_MAP_S) +#define INTMTX_CORE0_EFUSE_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_EFUSE_INTR_MAP_S 0 + +/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x3c) +/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_M (INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S) +#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S 0 + +/** INTMTX_CORE0_LP_UART_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_LP_UART_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x40) +/** INTMTX_CORE0_LP_UART_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_LP_UART_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_LP_UART_INTR_MAP_M (INTMTX_CORE0_LP_UART_INTR_MAP_V << INTMTX_CORE0_LP_UART_INTR_MAP_S) +#define INTMTX_CORE0_LP_UART_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_LP_UART_INTR_MAP_S 0 + +/** INTMTX_CORE0_LP_I2C_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_LP_I2C_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x44) +/** INTMTX_CORE0_LP_I2C_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_LP_I2C_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_LP_I2C_INTR_MAP_M (INTMTX_CORE0_LP_I2C_INTR_MAP_V << INTMTX_CORE0_LP_I2C_INTR_MAP_S) +#define INTMTX_CORE0_LP_I2C_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_LP_I2C_INTR_MAP_S 0 + +/** INTMTX_CORE0_LP_WDT_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x48) +/** INTMTX_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_LP_WDT_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_LP_WDT_INTR_MAP_M (INTMTX_CORE0_LP_WDT_INTR_MAP_V << INTMTX_CORE0_LP_WDT_INTR_MAP_S) +#define INTMTX_CORE0_LP_WDT_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_LP_WDT_INTR_MAP_S 0 + +/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4c) +/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_M (INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S) +#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S 0 + +/** INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x50) +/** INTMTX_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_LP_APM_M0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_M (INTMTX_CORE0_LP_APM_M0_INTR_MAP_V << INTMTX_CORE0_LP_APM_M0_INTR_MAP_S) +#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_S 0 + +/** INTMTX_CORE0_LP_APM_M1_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x54) +/** INTMTX_CORE0_LP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_LP_APM_M1_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_M (INTMTX_CORE0_LP_APM_M1_INTR_MAP_V << INTMTX_CORE0_LP_APM_M1_INTR_MAP_S) +#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_S 0 + +/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register + * register description + */ +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x58) +/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000001FU +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S) +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x0000001FU +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0 + +/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register + * register description + */ +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x5c) +/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000001FU +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S) +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x0000001FU +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0 + +/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register + * register description + */ +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x60) +/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000001FU +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S) +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x0000001FU +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0 + +/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register + * register description + */ +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x64) +/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000001FU +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S) +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x0000001FU +#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0 + +/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x68) +/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_M (INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S) +#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S 0 + +/** INTMTX_CORE0_TRACE_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x6c) +/** INTMTX_CORE0_TRACE_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_TRACE_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_TRACE_INTR_MAP_M (INTMTX_CORE0_TRACE_INTR_MAP_V << INTMTX_CORE0_TRACE_INTR_MAP_S) +#define INTMTX_CORE0_TRACE_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_TRACE_INTR_MAP_S 0 + +/** INTMTX_CORE0_CACHE_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x70) +/** INTMTX_CORE0_CACHE_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_CACHE_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_CACHE_INTR_MAP_M (INTMTX_CORE0_CACHE_INTR_MAP_V << INTMTX_CORE0_CACHE_INTR_MAP_S) +#define INTMTX_CORE0_CACHE_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_CACHE_INTR_MAP_S 0 + +/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x74) +/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_M (INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S) +#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S 0 + +/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register + * register description + */ +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x78) +/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000001FU +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_M (INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S) +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x0000001FU +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0 + +/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register + * register description + */ +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7c) +/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001FU +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M (INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S) +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x0000001FU +#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 + +/** INTMTX_CORE0_PAU_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x80) +/** INTMTX_CORE0_PAU_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_PAU_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_PAU_INTR_MAP_M (INTMTX_CORE0_PAU_INTR_MAP_V << INTMTX_CORE0_PAU_INTR_MAP_S) +#define INTMTX_CORE0_PAU_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_PAU_INTR_MAP_S 0 + +/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x84) +/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_M (INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S) +#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S 0 + +/** INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x88) +/** INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_M (INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S) +#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S 0 + +/** INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8c) +/** INTMTX_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_HP_APM_M0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_M (INTMTX_CORE0_HP_APM_M0_INTR_MAP_V << INTMTX_CORE0_HP_APM_M0_INTR_MAP_S) +#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_S 0 + +/** INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x90) +/** INTMTX_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_HP_APM_M1_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_M (INTMTX_CORE0_HP_APM_M1_INTR_MAP_V << INTMTX_CORE0_HP_APM_M1_INTR_MAP_S) +#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_S 0 + +/** INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x94) +/** INTMTX_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_HP_APM_M2_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_M (INTMTX_CORE0_HP_APM_M2_INTR_MAP_V << INTMTX_CORE0_HP_APM_M2_INTR_MAP_S) +#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_S 0 + +/** INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x98) +/** INTMTX_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_HP_APM_M3_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_M (INTMTX_CORE0_HP_APM_M3_INTR_MAP_V << INTMTX_CORE0_HP_APM_M3_INTR_MAP_S) +#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_S 0 + +/** INTMTX_CORE0_LP_APM0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_LP_APM0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x9c) +/** INTMTX_CORE0_LP_APM0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_LP_APM0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_LP_APM0_INTR_MAP_M (INTMTX_CORE0_LP_APM0_INTR_MAP_V << INTMTX_CORE0_LP_APM0_INTR_MAP_S) +#define INTMTX_CORE0_LP_APM0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_LP_APM0_INTR_MAP_S 0 + +/** INTMTX_CORE0_MSPI_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa0) +/** INTMTX_CORE0_MSPI_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_MSPI_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_MSPI_INTR_MAP_M (INTMTX_CORE0_MSPI_INTR_MAP_V << INTMTX_CORE0_MSPI_INTR_MAP_S) +#define INTMTX_CORE0_MSPI_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_MSPI_INTR_MAP_S 0 + +/** INTMTX_CORE0_I2S1_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa4) +/** INTMTX_CORE0_I2S1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_I2S1_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_I2S1_INTR_MAP_M (INTMTX_CORE0_I2S1_INTR_MAP_V << INTMTX_CORE0_I2S1_INTR_MAP_S) +#define INTMTX_CORE0_I2S1_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_I2S1_INTR_MAP_S 0 + +/** INTMTX_CORE0_UHCI0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa8) +/** INTMTX_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_UHCI0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_UHCI0_INTR_MAP_M (INTMTX_CORE0_UHCI0_INTR_MAP_V << INTMTX_CORE0_UHCI0_INTR_MAP_S) +#define INTMTX_CORE0_UHCI0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_UHCI0_INTR_MAP_S 0 + +/** INTMTX_CORE0_UART0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xac) +/** INTMTX_CORE0_UART0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_UART0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_UART0_INTR_MAP_M (INTMTX_CORE0_UART0_INTR_MAP_V << INTMTX_CORE0_UART0_INTR_MAP_S) +#define INTMTX_CORE0_UART0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_UART0_INTR_MAP_S 0 + +/** INTMTX_CORE0_UART1_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb0) +/** INTMTX_CORE0_UART1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_UART1_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_UART1_INTR_MAP_M (INTMTX_CORE0_UART1_INTR_MAP_V << INTMTX_CORE0_UART1_INTR_MAP_S) +#define INTMTX_CORE0_UART1_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_UART1_INTR_MAP_S 0 + +/** INTMTX_CORE0_LEDC_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb4) +/** INTMTX_CORE0_LEDC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_LEDC_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_LEDC_INTR_MAP_M (INTMTX_CORE0_LEDC_INTR_MAP_V << INTMTX_CORE0_LEDC_INTR_MAP_S) +#define INTMTX_CORE0_LEDC_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_LEDC_INTR_MAP_S 0 + +/** INTMTX_CORE0_CAN0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb8) +/** INTMTX_CORE0_CAN0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_CAN0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_CAN0_INTR_MAP_M (INTMTX_CORE0_CAN0_INTR_MAP_V << INTMTX_CORE0_CAN0_INTR_MAP_S) +#define INTMTX_CORE0_CAN0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_CAN0_INTR_MAP_S 0 + +/** INTMTX_CORE0_CAN1_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_CAN1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xbc) +/** INTMTX_CORE0_CAN1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_CAN1_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_CAN1_INTR_MAP_M (INTMTX_CORE0_CAN1_INTR_MAP_V << INTMTX_CORE0_CAN1_INTR_MAP_S) +#define INTMTX_CORE0_CAN1_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_CAN1_INTR_MAP_S 0 + +/** INTMTX_CORE0_USB_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc0) +/** INTMTX_CORE0_USB_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_USB_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_USB_INTR_MAP_M (INTMTX_CORE0_USB_INTR_MAP_V << INTMTX_CORE0_USB_INTR_MAP_S) +#define INTMTX_CORE0_USB_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_USB_INTR_MAP_S 0 + +/** INTMTX_CORE0_RMT_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc4) +/** INTMTX_CORE0_RMT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_RMT_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_RMT_INTR_MAP_M (INTMTX_CORE0_RMT_INTR_MAP_V << INTMTX_CORE0_RMT_INTR_MAP_S) +#define INTMTX_CORE0_RMT_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_RMT_INTR_MAP_S 0 + +/** INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc8) +/** INTMTX_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_I2C_EXT0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_M (INTMTX_CORE0_I2C_EXT0_INTR_MAP_V << INTMTX_CORE0_I2C_EXT0_INTR_MAP_S) +#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_S 0 + +/** INTMTX_CORE0_TG0_T0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xcc) +/** INTMTX_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_TG0_T0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_TG0_T0_INTR_MAP_M (INTMTX_CORE0_TG0_T0_INTR_MAP_V << INTMTX_CORE0_TG0_T0_INTR_MAP_S) +#define INTMTX_CORE0_TG0_T0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_TG0_T0_INTR_MAP_S 0 + +/** INTMTX_CORE0_TG0_T1_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_TG0_T1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd0) +/** INTMTX_CORE0_TG0_T1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_TG0_T1_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_TG0_T1_INTR_MAP_M (INTMTX_CORE0_TG0_T1_INTR_MAP_V << INTMTX_CORE0_TG0_T1_INTR_MAP_S) +#define INTMTX_CORE0_TG0_T1_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_TG0_T1_INTR_MAP_S 0 + +/** INTMTX_CORE0_TG0_WDT_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd4) +/** INTMTX_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_TG0_WDT_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_TG0_WDT_INTR_MAP_M (INTMTX_CORE0_TG0_WDT_INTR_MAP_V << INTMTX_CORE0_TG0_WDT_INTR_MAP_S) +#define INTMTX_CORE0_TG0_WDT_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_TG0_WDT_INTR_MAP_S 0 + +/** INTMTX_CORE0_TG1_T0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd8) +/** INTMTX_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_TG1_T0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_TG1_T0_INTR_MAP_M (INTMTX_CORE0_TG1_T0_INTR_MAP_V << INTMTX_CORE0_TG1_T0_INTR_MAP_S) +#define INTMTX_CORE0_TG1_T0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_TG1_T0_INTR_MAP_S 0 + +/** INTMTX_CORE0_TG1_T1_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_TG1_T1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xdc) +/** INTMTX_CORE0_TG1_T1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_TG1_T1_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_TG1_T1_INTR_MAP_M (INTMTX_CORE0_TG1_T1_INTR_MAP_V << INTMTX_CORE0_TG1_T1_INTR_MAP_S) +#define INTMTX_CORE0_TG1_T1_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_TG1_T1_INTR_MAP_S 0 + +/** INTMTX_CORE0_TG1_WDT_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe0) +/** INTMTX_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_TG1_WDT_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_TG1_WDT_INTR_MAP_M (INTMTX_CORE0_TG1_WDT_INTR_MAP_V << INTMTX_CORE0_TG1_WDT_INTR_MAP_S) +#define INTMTX_CORE0_TG1_WDT_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_TG1_WDT_INTR_MAP_S 0 + +/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe4) +/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_M (INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S) +#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S 0 + +/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe8) +/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_M (INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S) +#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S 0 + +/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xec) +/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_M (INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S) +#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S 0 + +/** INTMTX_CORE0_APB_ADC_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf0) +/** INTMTX_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_APB_ADC_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_APB_ADC_INTR_MAP_M (INTMTX_CORE0_APB_ADC_INTR_MAP_V << INTMTX_CORE0_APB_ADC_INTR_MAP_S) +#define INTMTX_CORE0_APB_ADC_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_APB_ADC_INTR_MAP_S 0 + +/** INTMTX_CORE0_PWM_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_PWM_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf4) +/** INTMTX_CORE0_PWM_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_PWM_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_PWM_INTR_MAP_M (INTMTX_CORE0_PWM_INTR_MAP_V << INTMTX_CORE0_PWM_INTR_MAP_S) +#define INTMTX_CORE0_PWM_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_PWM_INTR_MAP_S 0 + +/** INTMTX_CORE0_PCNT_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf8) +/** INTMTX_CORE0_PCNT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_PCNT_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_PCNT_INTR_MAP_M (INTMTX_CORE0_PCNT_INTR_MAP_V << INTMTX_CORE0_PCNT_INTR_MAP_S) +#define INTMTX_CORE0_PCNT_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_PCNT_INTR_MAP_S 0 + +/** INTMTX_CORE0_PARL_IO_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_PARL_IO_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xfc) +/** INTMTX_CORE0_PARL_IO_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_PARL_IO_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_PARL_IO_INTR_MAP_M (INTMTX_CORE0_PARL_IO_INTR_MAP_V << INTMTX_CORE0_PARL_IO_INTR_MAP_S) +#define INTMTX_CORE0_PARL_IO_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_PARL_IO_INTR_MAP_S 0 + +/** INTMTX_CORE0_SLC0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x100) +/** INTMTX_CORE0_SLC0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_SLC0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_SLC0_INTR_MAP_M (INTMTX_CORE0_SLC0_INTR_MAP_V << INTMTX_CORE0_SLC0_INTR_MAP_S) +#define INTMTX_CORE0_SLC0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_SLC0_INTR_MAP_S 0 + +/** INTMTX_CORE0_SLC1_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x104) +/** INTMTX_CORE0_SLC1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_SLC1_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_SLC1_INTR_MAP_M (INTMTX_CORE0_SLC1_INTR_MAP_V << INTMTX_CORE0_SLC1_INTR_MAP_S) +#define INTMTX_CORE0_SLC1_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_SLC1_INTR_MAP_S 0 + +/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x108) +/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_M (INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S) +#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S 0 + +/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10c) +/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_M (INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S) +#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S 0 + +/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x110) +/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_M (INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S) +#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S 0 + +/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x114) +/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_M (INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S) +#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S 0 + +/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x118) +/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_M (INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S) +#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S 0 + +/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x11c) +/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_M (INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S) +#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S 0 + +/** INTMTX_CORE0_GPSPI2_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x120) +/** INTMTX_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_GPSPI2_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_GPSPI2_INTR_MAP_M (INTMTX_CORE0_GPSPI2_INTR_MAP_V << INTMTX_CORE0_GPSPI2_INTR_MAP_S) +#define INTMTX_CORE0_GPSPI2_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_GPSPI2_INTR_MAP_S 0 + +/** INTMTX_CORE0_AES_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x124) +/** INTMTX_CORE0_AES_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_AES_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_AES_INTR_MAP_M (INTMTX_CORE0_AES_INTR_MAP_V << INTMTX_CORE0_AES_INTR_MAP_S) +#define INTMTX_CORE0_AES_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_AES_INTR_MAP_S 0 + +/** INTMTX_CORE0_SHA_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x128) +/** INTMTX_CORE0_SHA_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_SHA_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_SHA_INTR_MAP_M (INTMTX_CORE0_SHA_INTR_MAP_V << INTMTX_CORE0_SHA_INTR_MAP_S) +#define INTMTX_CORE0_SHA_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_SHA_INTR_MAP_S 0 + +/** INTMTX_CORE0_RSA_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x12c) +/** INTMTX_CORE0_RSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_RSA_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_RSA_INTR_MAP_M (INTMTX_CORE0_RSA_INTR_MAP_V << INTMTX_CORE0_RSA_INTR_MAP_S) +#define INTMTX_CORE0_RSA_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_RSA_INTR_MAP_S 0 + +/** INTMTX_CORE0_ECC_INTR_MAP_REG register + * register description + */ +#define INTMTX_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x130) +/** INTMTX_CORE0_ECC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_ECC_INTR_MAP 0x0000001FU +#define INTMTX_CORE0_ECC_INTR_MAP_M (INTMTX_CORE0_ECC_INTR_MAP_V << INTMTX_CORE0_ECC_INTR_MAP_S) +#define INTMTX_CORE0_ECC_INTR_MAP_V 0x0000001FU +#define INTMTX_CORE0_ECC_INTR_MAP_S 0 + +/** INTMTX_CORE0_INT_STATUS_REG_0_REG register + * register description + */ +#define INTMTX_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x134) +/** INTMTX_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_INT_STATUS_0 0xFFFFFFFFU +#define INTMTX_CORE0_INT_STATUS_0_M (INTMTX_CORE0_INT_STATUS_0_V << INTMTX_CORE0_INT_STATUS_0_S) +#define INTMTX_CORE0_INT_STATUS_0_V 0xFFFFFFFFU +#define INTMTX_CORE0_INT_STATUS_0_S 0 + +/** INTMTX_CORE0_INT_STATUS_REG_1_REG register + * register description + */ +#define INTMTX_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x138) +/** INTMTX_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_INT_STATUS_1 0xFFFFFFFFU +#define INTMTX_CORE0_INT_STATUS_1_M (INTMTX_CORE0_INT_STATUS_1_V << INTMTX_CORE0_INT_STATUS_1_S) +#define INTMTX_CORE0_INT_STATUS_1_V 0xFFFFFFFFU +#define INTMTX_CORE0_INT_STATUS_1_S 0 + +/** INTMTX_CORE0_INT_STATUS_REG_2_REG register + * register description + */ +#define INTMTX_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x13c) +/** INTMTX_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0; + * Need add description + */ +#define INTMTX_CORE0_INT_STATUS_2 0xFFFFFFFFU +#define INTMTX_CORE0_INT_STATUS_2_M (INTMTX_CORE0_INT_STATUS_2_V << INTMTX_CORE0_INT_STATUS_2_S) +#define INTMTX_CORE0_INT_STATUS_2_V 0xFFFFFFFFU +#define INTMTX_CORE0_INT_STATUS_2_S 0 + +/** INTMTX_CORE0_CLOCK_GATE_REG register + * register description + */ +#define INTMTX_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x140) +/** INTMTX_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1; + * Need add description + */ +#define INTMTX_CORE0_REG_CLK_EN (BIT(0)) +#define INTMTX_CORE0_REG_CLK_EN_M (INTMTX_CORE0_REG_CLK_EN_V << INTMTX_CORE0_REG_CLK_EN_S) +#define INTMTX_CORE0_REG_CLK_EN_V 0x00000001U +#define INTMTX_CORE0_REG_CLK_EN_S 0 + +/** INTMTX_CORE0_INTERRUPT_REG_DATE_REG register + * register description + */ +#define INTMTX_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7fc) +/** INTMTX_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 35664144; + * Need add description + */ +#define INTMTX_CORE0_INTERRUPT_REG_DATE 0x0FFFFFFFU +#define INTMTX_CORE0_INTERRUPT_REG_DATE_M (INTMTX_CORE0_INTERRUPT_REG_DATE_V << INTMTX_CORE0_INTERRUPT_REG_DATE_S) +#define INTMTX_CORE0_INTERRUPT_REG_DATE_V 0x0FFFFFFFU +#define INTMTX_CORE0_INTERRUPT_REG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/interrupt_matrix_struct.h b/components/soc/esp32c6/include/soc/interrupt_matrix_struct.h new file mode 100644 index 0000000000..4af30c9493 --- /dev/null +++ b/components/soc/esp32c6/include/soc/interrupt_matrix_struct.h @@ -0,0 +1,1254 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of wifi_mac_intr_map register + * register description + */ +typedef union { + struct { + /** wifi_mac_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t wifi_mac_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_wifi_mac_intr_map_reg_t; + +/** Type of wifi_mac_nmi_map register + * register description + */ +typedef union { + struct { + /** wifi_mac_nmi_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t wifi_mac_nmi_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_wifi_mac_nmi_map_reg_t; + +/** Type of wifi_pwr_intr_map register + * register description + */ +typedef union { + struct { + /** wifi_pwr_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t wifi_pwr_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_wifi_pwr_intr_map_reg_t; + +/** Type of wifi_bb_intr_map register + * register description + */ +typedef union { + struct { + /** wifi_bb_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t wifi_bb_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_wifi_bb_intr_map_reg_t; + +/** Type of bt_mac_intr_map register + * register description + */ +typedef union { + struct { + /** bt_mac_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t bt_mac_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_bt_mac_intr_map_reg_t; + +/** Type of bt_bb_intr_map register + * register description + */ +typedef union { + struct { + /** bt_bb_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t bt_bb_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_bt_bb_intr_map_reg_t; + +/** Type of bt_bb_nmi_map register + * register description + */ +typedef union { + struct { + /** bt_bb_nmi_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t bt_bb_nmi_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_bt_bb_nmi_map_reg_t; + +/** Type of lp_timer_intr_map register + * register description + */ +typedef union { + struct { + /** lp_timer_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t lp_timer_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_lp_timer_intr_map_reg_t; + +/** Type of coex_intr_map register + * register description + */ +typedef union { + struct { + /** coex_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t coex_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_coex_intr_map_reg_t; + +/** Type of ble_timer_intr_map register + * register description + */ +typedef union { + struct { + /** ble_timer_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t ble_timer_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_ble_timer_intr_map_reg_t; + +/** Type of ble_sec_intr_map register + * register description + */ +typedef union { + struct { + /** ble_sec_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t ble_sec_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_ble_sec_intr_map_reg_t; + +/** Type of i2c_mst_intr_map register + * register description + */ +typedef union { + struct { + /** i2c_mst_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t i2c_mst_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_i2c_mst_intr_map_reg_t; + +/** Type of zb_mac_intr_map register + * register description + */ +typedef union { + struct { + /** zb_mac_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t zb_mac_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_zb_mac_intr_map_reg_t; + +/** Type of pmu_intr_map register + * register description + */ +typedef union { + struct { + /** pmu_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t pmu_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_pmu_intr_map_reg_t; + +/** Type of efuse_intr_map register + * register description + */ +typedef union { + struct { + /** efuse_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t efuse_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_efuse_intr_map_reg_t; + +/** Type of lp_rtc_timer_intr_map register + * register description + */ +typedef union { + struct { + /** lp_rtc_timer_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t lp_rtc_timer_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_lp_rtc_timer_intr_map_reg_t; + +/** Type of lp_uart_intr_map register + * register description + */ +typedef union { + struct { + /** lp_uart_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t lp_uart_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_lp_uart_intr_map_reg_t; + +/** Type of lp_i2c_intr_map register + * register description + */ +typedef union { + struct { + /** lp_i2c_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t lp_i2c_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_lp_i2c_intr_map_reg_t; + +/** Type of lp_wdt_intr_map register + * register description + */ +typedef union { + struct { + /** lp_wdt_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t lp_wdt_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_lp_wdt_intr_map_reg_t; + +/** Type of lp_peri_timeout_intr_map register + * register description + */ +typedef union { + struct { + /** lp_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t lp_peri_timeout_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_lp_peri_timeout_intr_map_reg_t; + +/** Type of lp_apm_m0_intr_map register + * register description + */ +typedef union { + struct { + /** lp_apm_m0_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t lp_apm_m0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_lp_apm_m0_intr_map_reg_t; + +/** Type of lp_apm_m1_intr_map register + * register description + */ +typedef union { + struct { + /** lp_apm_m1_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t lp_apm_m1_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_lp_apm_m1_intr_map_reg_t; + +/** Type of cpu_intr_from_cpu_0_map register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_0_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t cpu_intr_from_cpu_0_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_cpu_intr_from_cpu_0_map_reg_t; + +/** Type of cpu_intr_from_cpu_1_map register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_1_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t cpu_intr_from_cpu_1_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_cpu_intr_from_cpu_1_map_reg_t; + +/** Type of cpu_intr_from_cpu_2_map register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_2_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t cpu_intr_from_cpu_2_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_cpu_intr_from_cpu_2_map_reg_t; + +/** Type of cpu_intr_from_cpu_3_map register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_3_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t cpu_intr_from_cpu_3_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_cpu_intr_from_cpu_3_map_reg_t; + +/** Type of assist_debug_intr_map register + * register description + */ +typedef union { + struct { + /** assist_debug_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t assist_debug_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_assist_debug_intr_map_reg_t; + +/** Type of trace_intr_map register + * register description + */ +typedef union { + struct { + /** trace_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t trace_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_trace_intr_map_reg_t; + +/** Type of cache_intr_map register + * register description + */ +typedef union { + struct { + /** cache_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t cache_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_cache_intr_map_reg_t; + +/** Type of cpu_peri_timeout_intr_map register + * register description + */ +typedef union { + struct { + /** cpu_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t cpu_peri_timeout_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_cpu_peri_timeout_intr_map_reg_t; + +/** Type of gpio_interrupt_pro_map register + * register description + */ +typedef union { + struct { + /** gpio_interrupt_pro_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t gpio_interrupt_pro_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_gpio_interrupt_pro_map_reg_t; + +/** Type of gpio_interrupt_pro_nmi_map register + * register description + */ +typedef union { + struct { + /** gpio_interrupt_pro_nmi_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t gpio_interrupt_pro_nmi_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_gpio_interrupt_pro_nmi_map_reg_t; + +/** Type of pau_intr_map register + * register description + */ +typedef union { + struct { + /** pau_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t pau_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_pau_intr_map_reg_t; + +/** Type of hp_peri_timeout_intr_map register + * register description + */ +typedef union { + struct { + /** hp_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t hp_peri_timeout_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_hp_peri_timeout_intr_map_reg_t; + +/** Type of modem_peri_timeout_intr_map register + * register description + */ +typedef union { + struct { + /** modem_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t modem_peri_timeout_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_modem_peri_timeout_intr_map_reg_t; + +/** Type of hp_apm_m0_intr_map register + * register description + */ +typedef union { + struct { + /** hp_apm_m0_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t hp_apm_m0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_hp_apm_m0_intr_map_reg_t; + +/** Type of hp_apm_m1_intr_map register + * register description + */ +typedef union { + struct { + /** hp_apm_m1_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t hp_apm_m1_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_hp_apm_m1_intr_map_reg_t; + +/** Type of hp_apm_m2_intr_map register + * register description + */ +typedef union { + struct { + /** hp_apm_m2_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t hp_apm_m2_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_hp_apm_m2_intr_map_reg_t; + +/** Type of hp_apm_m3_intr_map register + * register description + */ +typedef union { + struct { + /** hp_apm_m3_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t hp_apm_m3_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_hp_apm_m3_intr_map_reg_t; + +/** Type of lp_apm0_intr_map register + * register description + */ +typedef union { + struct { + /** lp_apm0_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t lp_apm0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_lp_apm0_intr_map_reg_t; + +/** Type of mspi_intr_map register + * register description + */ +typedef union { + struct { + /** mspi_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t mspi_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_mspi_intr_map_reg_t; + +/** Type of i2s1_intr_map register + * register description + */ +typedef union { + struct { + /** i2s1_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t i2s1_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_i2s1_intr_map_reg_t; + +/** Type of uhci0_intr_map register + * register description + */ +typedef union { + struct { + /** uhci0_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t uhci0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_uhci0_intr_map_reg_t; + +/** Type of uart0_intr_map register + * register description + */ +typedef union { + struct { + /** uart0_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t uart0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_uart0_intr_map_reg_t; + +/** Type of uart1_intr_map register + * register description + */ +typedef union { + struct { + /** uart1_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t uart1_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_uart1_intr_map_reg_t; + +/** Type of ledc_intr_map register + * register description + */ +typedef union { + struct { + /** ledc_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t ledc_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_ledc_intr_map_reg_t; + +/** Type of can0_intr_map register + * register description + */ +typedef union { + struct { + /** can0_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t can0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_can0_intr_map_reg_t; + +/** Type of can1_intr_map register + * register description + */ +typedef union { + struct { + /** can1_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t can1_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_can1_intr_map_reg_t; + +/** Type of usb_intr_map register + * register description + */ +typedef union { + struct { + /** usb_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t usb_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_usb_intr_map_reg_t; + +/** Type of rmt_intr_map register + * register description + */ +typedef union { + struct { + /** rmt_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t rmt_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_rmt_intr_map_reg_t; + +/** Type of i2c_ext0_intr_map register + * register description + */ +typedef union { + struct { + /** i2c_ext0_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t i2c_ext0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_i2c_ext0_intr_map_reg_t; + +/** Type of tg0_t0_intr_map register + * register description + */ +typedef union { + struct { + /** tg0_t0_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t tg0_t0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_tg0_t0_intr_map_reg_t; + +/** Type of tg0_t1_intr_map register + * register description + */ +typedef union { + struct { + /** tg0_t1_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t tg0_t1_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_tg0_t1_intr_map_reg_t; + +/** Type of tg0_wdt_intr_map register + * register description + */ +typedef union { + struct { + /** tg0_wdt_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t tg0_wdt_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_tg0_wdt_intr_map_reg_t; + +/** Type of tg1_t0_intr_map register + * register description + */ +typedef union { + struct { + /** tg1_t0_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t tg1_t0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_tg1_t0_intr_map_reg_t; + +/** Type of tg1_t1_intr_map register + * register description + */ +typedef union { + struct { + /** tg1_t1_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t tg1_t1_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_tg1_t1_intr_map_reg_t; + +/** Type of tg1_wdt_intr_map register + * register description + */ +typedef union { + struct { + /** tg1_wdt_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t tg1_wdt_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_tg1_wdt_intr_map_reg_t; + +/** Type of systimer_target0_intr_map register + * register description + */ +typedef union { + struct { + /** systimer_target0_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t systimer_target0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_systimer_target0_intr_map_reg_t; + +/** Type of systimer_target1_intr_map register + * register description + */ +typedef union { + struct { + /** systimer_target1_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t systimer_target1_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_systimer_target1_intr_map_reg_t; + +/** Type of systimer_target2_intr_map register + * register description + */ +typedef union { + struct { + /** systimer_target2_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t systimer_target2_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_systimer_target2_intr_map_reg_t; + +/** Type of apb_adc_intr_map register + * register description + */ +typedef union { + struct { + /** apb_adc_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t apb_adc_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_apb_adc_intr_map_reg_t; + +/** Type of pwm_intr_map register + * register description + */ +typedef union { + struct { + /** pwm_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t pwm_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_pwm_intr_map_reg_t; + +/** Type of pcnt_intr_map register + * register description + */ +typedef union { + struct { + /** pcnt_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t pcnt_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_pcnt_intr_map_reg_t; + +/** Type of parl_io_intr_map register + * register description + */ +typedef union { + struct { + /** parl_io_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t parl_io_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_parl_io_intr_map_reg_t; + +/** Type of slc0_intr_map register + * register description + */ +typedef union { + struct { + /** slc0_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t slc0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_slc0_intr_map_reg_t; + +/** Type of slc1_intr_map register + * register description + */ +typedef union { + struct { + /** slc1_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t slc1_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_slc1_intr_map_reg_t; + +/** Type of dma_in_ch0_intr_map register + * register description + */ +typedef union { + struct { + /** dma_in_ch0_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t dma_in_ch0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_dma_in_ch0_intr_map_reg_t; + +/** Type of dma_in_ch1_intr_map register + * register description + */ +typedef union { + struct { + /** dma_in_ch1_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t dma_in_ch1_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_dma_in_ch1_intr_map_reg_t; + +/** Type of dma_in_ch2_intr_map register + * register description + */ +typedef union { + struct { + /** dma_in_ch2_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t dma_in_ch2_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_dma_in_ch2_intr_map_reg_t; + +/** Type of dma_out_ch0_intr_map register + * register description + */ +typedef union { + struct { + /** dma_out_ch0_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t dma_out_ch0_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_dma_out_ch0_intr_map_reg_t; + +/** Type of dma_out_ch1_intr_map register + * register description + */ +typedef union { + struct { + /** dma_out_ch1_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t dma_out_ch1_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_dma_out_ch1_intr_map_reg_t; + +/** Type of dma_out_ch2_intr_map register + * register description + */ +typedef union { + struct { + /** dma_out_ch2_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t dma_out_ch2_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_dma_out_ch2_intr_map_reg_t; + +/** Type of gpspi2_intr_map register + * register description + */ +typedef union { + struct { + /** gpspi2_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t gpspi2_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_gpspi2_intr_map_reg_t; + +/** Type of aes_intr_map register + * register description + */ +typedef union { + struct { + /** aes_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t aes_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_aes_intr_map_reg_t; + +/** Type of sha_intr_map register + * register description + */ +typedef union { + struct { + /** sha_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t sha_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_sha_intr_map_reg_t; + +/** Type of rsa_intr_map register + * register description + */ +typedef union { + struct { + /** rsa_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t rsa_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_rsa_intr_map_reg_t; + +/** Type of ecc_intr_map register + * register description + */ +typedef union { + struct { + /** ecc_intr_map : R/W; bitpos: [4:0]; default: 0; + * Need add description + */ + uint32_t ecc_intr_map:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} interrupt_matrix_ecc_intr_map_reg_t; + +/** Type of int_status_reg_0 register + * register description + */ +typedef union { + struct { + /** int_status_0 : RO; bitpos: [31:0]; default: 0; + * Need add description + */ + uint32_t int_status_0:32; + }; + uint32_t val; +} interrupt_matrix_int_status_reg_0_reg_t; + +/** Type of int_status_reg_1 register + * register description + */ +typedef union { + struct { + /** int_status_1 : RO; bitpos: [31:0]; default: 0; + * Need add description + */ + uint32_t int_status_1:32; + }; + uint32_t val; +} interrupt_matrix_int_status_reg_1_reg_t; + +/** Type of int_status_reg_2 register + * register description + */ +typedef union { + struct { + /** int_status_2 : RO; bitpos: [31:0]; default: 0; + * Need add description + */ + uint32_t int_status_2:32; + }; + uint32_t val; +} interrupt_matrix_int_status_reg_2_reg_t; + +/** Type of clock_gate register + * register description + */ +typedef union { + struct { + /** reg_clk_en : R/W; bitpos: [0]; default: 1; + * Need add description + */ + uint32_t reg_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} interrupt_matrix_clock_gate_reg_t; + +/** Type of interrupt_reg_date register + * register description + */ +typedef union { + struct { + /** interrupt_reg_date : R/W; bitpos: [27:0]; default: 35664144; + * Need add description + */ + uint32_t interrupt_reg_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} interrupt_matrix_interrupt_reg_date_reg_t; + + +typedef struct interrupt_matrix_dev_t { + volatile interrupt_matrix_wifi_mac_intr_map_reg_t wifi_mac_intr_map; + volatile interrupt_matrix_wifi_mac_nmi_map_reg_t wifi_mac_nmi_map; + volatile interrupt_matrix_wifi_pwr_intr_map_reg_t wifi_pwr_intr_map; + volatile interrupt_matrix_wifi_bb_intr_map_reg_t wifi_bb_intr_map; + volatile interrupt_matrix_bt_mac_intr_map_reg_t bt_mac_intr_map; + volatile interrupt_matrix_bt_bb_intr_map_reg_t bt_bb_intr_map; + volatile interrupt_matrix_bt_bb_nmi_map_reg_t bt_bb_nmi_map; + volatile interrupt_matrix_lp_timer_intr_map_reg_t lp_timer_intr_map; + volatile interrupt_matrix_coex_intr_map_reg_t coex_intr_map; + volatile interrupt_matrix_ble_timer_intr_map_reg_t ble_timer_intr_map; + volatile interrupt_matrix_ble_sec_intr_map_reg_t ble_sec_intr_map; + volatile interrupt_matrix_i2c_mst_intr_map_reg_t i2c_mst_intr_map; + volatile interrupt_matrix_zb_mac_intr_map_reg_t zb_mac_intr_map; + volatile interrupt_matrix_pmu_intr_map_reg_t pmu_intr_map; + volatile interrupt_matrix_efuse_intr_map_reg_t efuse_intr_map; + volatile interrupt_matrix_lp_rtc_timer_intr_map_reg_t lp_rtc_timer_intr_map; + volatile interrupt_matrix_lp_uart_intr_map_reg_t lp_uart_intr_map; + volatile interrupt_matrix_lp_i2c_intr_map_reg_t lp_i2c_intr_map; + volatile interrupt_matrix_lp_wdt_intr_map_reg_t lp_wdt_intr_map; + volatile interrupt_matrix_lp_peri_timeout_intr_map_reg_t lp_peri_timeout_intr_map; + volatile interrupt_matrix_lp_apm_m0_intr_map_reg_t lp_apm_m0_intr_map; + volatile interrupt_matrix_lp_apm_m1_intr_map_reg_t lp_apm_m1_intr_map; + volatile interrupt_matrix_cpu_intr_from_cpu_0_map_reg_t cpu_intr_from_cpu_0_map; + volatile interrupt_matrix_cpu_intr_from_cpu_1_map_reg_t cpu_intr_from_cpu_1_map; + volatile interrupt_matrix_cpu_intr_from_cpu_2_map_reg_t cpu_intr_from_cpu_2_map; + volatile interrupt_matrix_cpu_intr_from_cpu_3_map_reg_t cpu_intr_from_cpu_3_map; + volatile interrupt_matrix_assist_debug_intr_map_reg_t assist_debug_intr_map; + volatile interrupt_matrix_trace_intr_map_reg_t trace_intr_map; + volatile interrupt_matrix_cache_intr_map_reg_t cache_intr_map; + volatile interrupt_matrix_cpu_peri_timeout_intr_map_reg_t cpu_peri_timeout_intr_map; + volatile interrupt_matrix_gpio_interrupt_pro_map_reg_t gpio_interrupt_pro_map; + volatile interrupt_matrix_gpio_interrupt_pro_nmi_map_reg_t gpio_interrupt_pro_nmi_map; + volatile interrupt_matrix_pau_intr_map_reg_t pau_intr_map; + volatile interrupt_matrix_hp_peri_timeout_intr_map_reg_t hp_peri_timeout_intr_map; + volatile interrupt_matrix_modem_peri_timeout_intr_map_reg_t modem_peri_timeout_intr_map; + volatile interrupt_matrix_hp_apm_m0_intr_map_reg_t hp_apm_m0_intr_map; + volatile interrupt_matrix_hp_apm_m1_intr_map_reg_t hp_apm_m1_intr_map; + volatile interrupt_matrix_hp_apm_m2_intr_map_reg_t hp_apm_m2_intr_map; + volatile interrupt_matrix_hp_apm_m3_intr_map_reg_t hp_apm_m3_intr_map; + volatile interrupt_matrix_lp_apm0_intr_map_reg_t lp_apm0_intr_map; + volatile interrupt_matrix_mspi_intr_map_reg_t mspi_intr_map; + volatile interrupt_matrix_i2s1_intr_map_reg_t i2s1_intr_map; + volatile interrupt_matrix_uhci0_intr_map_reg_t uhci0_intr_map; + volatile interrupt_matrix_uart0_intr_map_reg_t uart0_intr_map; + volatile interrupt_matrix_uart1_intr_map_reg_t uart1_intr_map; + volatile interrupt_matrix_ledc_intr_map_reg_t ledc_intr_map; + volatile interrupt_matrix_can0_intr_map_reg_t can0_intr_map; + volatile interrupt_matrix_can1_intr_map_reg_t can1_intr_map; + volatile interrupt_matrix_usb_intr_map_reg_t usb_intr_map; + volatile interrupt_matrix_rmt_intr_map_reg_t rmt_intr_map; + volatile interrupt_matrix_i2c_ext0_intr_map_reg_t i2c_ext0_intr_map; + volatile interrupt_matrix_tg0_t0_intr_map_reg_t tg0_t0_intr_map; + volatile interrupt_matrix_tg0_t1_intr_map_reg_t tg0_t1_intr_map; + volatile interrupt_matrix_tg0_wdt_intr_map_reg_t tg0_wdt_intr_map; + volatile interrupt_matrix_tg1_t0_intr_map_reg_t tg1_t0_intr_map; + volatile interrupt_matrix_tg1_t1_intr_map_reg_t tg1_t1_intr_map; + volatile interrupt_matrix_tg1_wdt_intr_map_reg_t tg1_wdt_intr_map; + volatile interrupt_matrix_systimer_target0_intr_map_reg_t systimer_target0_intr_map; + volatile interrupt_matrix_systimer_target1_intr_map_reg_t systimer_target1_intr_map; + volatile interrupt_matrix_systimer_target2_intr_map_reg_t systimer_target2_intr_map; + volatile interrupt_matrix_apb_adc_intr_map_reg_t apb_adc_intr_map; + volatile interrupt_matrix_pwm_intr_map_reg_t pwm_intr_map; + volatile interrupt_matrix_pcnt_intr_map_reg_t pcnt_intr_map; + volatile interrupt_matrix_parl_io_intr_map_reg_t parl_io_intr_map; + volatile interrupt_matrix_slc0_intr_map_reg_t slc0_intr_map; + volatile interrupt_matrix_slc1_intr_map_reg_t slc1_intr_map; + volatile interrupt_matrix_dma_in_ch0_intr_map_reg_t dma_in_ch0_intr_map; + volatile interrupt_matrix_dma_in_ch1_intr_map_reg_t dma_in_ch1_intr_map; + volatile interrupt_matrix_dma_in_ch2_intr_map_reg_t dma_in_ch2_intr_map; + volatile interrupt_matrix_dma_out_ch0_intr_map_reg_t dma_out_ch0_intr_map; + volatile interrupt_matrix_dma_out_ch1_intr_map_reg_t dma_out_ch1_intr_map; + volatile interrupt_matrix_dma_out_ch2_intr_map_reg_t dma_out_ch2_intr_map; + volatile interrupt_matrix_gpspi2_intr_map_reg_t gpspi2_intr_map; + volatile interrupt_matrix_aes_intr_map_reg_t aes_intr_map; + volatile interrupt_matrix_sha_intr_map_reg_t sha_intr_map; + volatile interrupt_matrix_rsa_intr_map_reg_t rsa_intr_map; + volatile interrupt_matrix_ecc_intr_map_reg_t ecc_intr_map; + volatile interrupt_matrix_int_status_reg_0_reg_t int_status_reg_0; + volatile interrupt_matrix_int_status_reg_1_reg_t int_status_reg_1; + volatile interrupt_matrix_int_status_reg_2_reg_t int_status_reg_2; + volatile interrupt_matrix_clock_gate_reg_t clock_gate; + uint32_t reserved_144[430]; + volatile interrupt_matrix_interrupt_reg_date_reg_t interrupt_reg_date; +} interrupt_matrix_dev_t; + +extern interrupt_matrix_dev_t INTMTX; + +#ifndef __cplusplus +_Static_assert(sizeof(interrupt_matrix_dev_t) == 0x800, "Invalid size of interrupt_matrix_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/interrupt_reg.h b/components/soc/esp32c6/include/soc/interrupt_reg.h new file mode 100644 index 0000000000..d59eb394af --- /dev/null +++ b/components/soc/esp32c6/include/soc/interrupt_reg.h @@ -0,0 +1,19 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/interrupt_matrix_reg.h" +#include "soc/intpri_reg.h" +#include "soc/plic_reg.h" +#include "soc/soc_caps.h" + +// ESP32C6 should use the PLIC controller as the interrupt controller instead of INTC (SOC_INT_PLIC_SUPPORTED = y) +#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG PLIC_MXINT_ENABLE_REG +#define INTERRUPT_CORE0_CPU_INT_THRESH_REG PLIC_MXINT_THRESH_REG +#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG PLIC_MXINT_CLEAR_REG +#define INTERRUPT_CORE0_CPU_INT_TYPE_REG PLIC_MXINT_TYPE_REG +#define INTC_INT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4) + +#define DR_REG_INTERRUPT_BASE DR_REG_INTERRUPT_MATRIX_BASE diff --git a/components/soc/esp32c6/include/soc/intpri_reg.h b/components/soc/esp32c6/include/soc/intpri_reg.h new file mode 100644 index 0000000000..f4d9c51fc7 --- /dev/null +++ b/components/soc/esp32c6/include/soc/intpri_reg.h @@ -0,0 +1,574 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** INTPRI_CORE0_CPU_INT_ENABLE_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_ENABLE_REG (DR_REG_INTPRI_BASE + 0x0) +/** INTPRI_CORE0_CPU_INT_ENABLE : R/W; bitpos: [31:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_INT_ENABLE 0xFFFFFFFFU +#define INTPRI_CORE0_CPU_INT_ENABLE_M (INTPRI_CORE0_CPU_INT_ENABLE_V << INTPRI_CORE0_CPU_INT_ENABLE_S) +#define INTPRI_CORE0_CPU_INT_ENABLE_V 0xFFFFFFFFU +#define INTPRI_CORE0_CPU_INT_ENABLE_S 0 + +/** INTPRI_CORE0_CPU_INT_TYPE_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_TYPE_REG (DR_REG_INTPRI_BASE + 0x4) +/** INTPRI_CORE0_CPU_INT_TYPE : R/W; bitpos: [31:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_INT_TYPE 0xFFFFFFFFU +#define INTPRI_CORE0_CPU_INT_TYPE_M (INTPRI_CORE0_CPU_INT_TYPE_V << INTPRI_CORE0_CPU_INT_TYPE_S) +#define INTPRI_CORE0_CPU_INT_TYPE_V 0xFFFFFFFFU +#define INTPRI_CORE0_CPU_INT_TYPE_S 0 + +/** INTPRI_CORE0_CPU_INT_EIP_STATUS_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_EIP_STATUS_REG (DR_REG_INTPRI_BASE + 0x8) +/** INTPRI_CORE0_CPU_INT_EIP_STATUS : RO; bitpos: [31:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_INT_EIP_STATUS 0xFFFFFFFFU +#define INTPRI_CORE0_CPU_INT_EIP_STATUS_M (INTPRI_CORE0_CPU_INT_EIP_STATUS_V << INTPRI_CORE0_CPU_INT_EIP_STATUS_S) +#define INTPRI_CORE0_CPU_INT_EIP_STATUS_V 0xFFFFFFFFU +#define INTPRI_CORE0_CPU_INT_EIP_STATUS_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_0_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_0_REG (DR_REG_INTPRI_BASE + 0xc) +/** INTPRI_CORE0_CPU_PRI_0_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_0_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_0_MAP_M (INTPRI_CORE0_CPU_PRI_0_MAP_V << INTPRI_CORE0_CPU_PRI_0_MAP_S) +#define INTPRI_CORE0_CPU_PRI_0_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_0_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_1_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_1_REG (DR_REG_INTPRI_BASE + 0x10) +/** INTPRI_CORE0_CPU_PRI_1_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_1_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_1_MAP_M (INTPRI_CORE0_CPU_PRI_1_MAP_V << INTPRI_CORE0_CPU_PRI_1_MAP_S) +#define INTPRI_CORE0_CPU_PRI_1_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_1_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_2_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_2_REG (DR_REG_INTPRI_BASE + 0x14) +/** INTPRI_CORE0_CPU_PRI_2_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_2_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_2_MAP_M (INTPRI_CORE0_CPU_PRI_2_MAP_V << INTPRI_CORE0_CPU_PRI_2_MAP_S) +#define INTPRI_CORE0_CPU_PRI_2_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_2_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_3_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_3_REG (DR_REG_INTPRI_BASE + 0x18) +/** INTPRI_CORE0_CPU_PRI_3_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_3_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_3_MAP_M (INTPRI_CORE0_CPU_PRI_3_MAP_V << INTPRI_CORE0_CPU_PRI_3_MAP_S) +#define INTPRI_CORE0_CPU_PRI_3_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_3_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_4_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_4_REG (DR_REG_INTPRI_BASE + 0x1c) +/** INTPRI_CORE0_CPU_PRI_4_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_4_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_4_MAP_M (INTPRI_CORE0_CPU_PRI_4_MAP_V << INTPRI_CORE0_CPU_PRI_4_MAP_S) +#define INTPRI_CORE0_CPU_PRI_4_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_4_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_5_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_5_REG (DR_REG_INTPRI_BASE + 0x20) +/** INTPRI_CORE0_CPU_PRI_5_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_5_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_5_MAP_M (INTPRI_CORE0_CPU_PRI_5_MAP_V << INTPRI_CORE0_CPU_PRI_5_MAP_S) +#define INTPRI_CORE0_CPU_PRI_5_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_5_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_6_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_6_REG (DR_REG_INTPRI_BASE + 0x24) +/** INTPRI_CORE0_CPU_PRI_6_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_6_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_6_MAP_M (INTPRI_CORE0_CPU_PRI_6_MAP_V << INTPRI_CORE0_CPU_PRI_6_MAP_S) +#define INTPRI_CORE0_CPU_PRI_6_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_6_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_7_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_7_REG (DR_REG_INTPRI_BASE + 0x28) +/** INTPRI_CORE0_CPU_PRI_7_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_7_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_7_MAP_M (INTPRI_CORE0_CPU_PRI_7_MAP_V << INTPRI_CORE0_CPU_PRI_7_MAP_S) +#define INTPRI_CORE0_CPU_PRI_7_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_7_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_8_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_8_REG (DR_REG_INTPRI_BASE + 0x2c) +/** INTPRI_CORE0_CPU_PRI_8_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_8_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_8_MAP_M (INTPRI_CORE0_CPU_PRI_8_MAP_V << INTPRI_CORE0_CPU_PRI_8_MAP_S) +#define INTPRI_CORE0_CPU_PRI_8_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_8_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_9_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_9_REG (DR_REG_INTPRI_BASE + 0x30) +/** INTPRI_CORE0_CPU_PRI_9_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_9_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_9_MAP_M (INTPRI_CORE0_CPU_PRI_9_MAP_V << INTPRI_CORE0_CPU_PRI_9_MAP_S) +#define INTPRI_CORE0_CPU_PRI_9_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_9_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_10_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_10_REG (DR_REG_INTPRI_BASE + 0x34) +/** INTPRI_CORE0_CPU_PRI_10_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_10_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_10_MAP_M (INTPRI_CORE0_CPU_PRI_10_MAP_V << INTPRI_CORE0_CPU_PRI_10_MAP_S) +#define INTPRI_CORE0_CPU_PRI_10_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_10_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_11_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_11_REG (DR_REG_INTPRI_BASE + 0x38) +/** INTPRI_CORE0_CPU_PRI_11_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_11_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_11_MAP_M (INTPRI_CORE0_CPU_PRI_11_MAP_V << INTPRI_CORE0_CPU_PRI_11_MAP_S) +#define INTPRI_CORE0_CPU_PRI_11_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_11_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_12_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_12_REG (DR_REG_INTPRI_BASE + 0x3c) +/** INTPRI_CORE0_CPU_PRI_12_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_12_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_12_MAP_M (INTPRI_CORE0_CPU_PRI_12_MAP_V << INTPRI_CORE0_CPU_PRI_12_MAP_S) +#define INTPRI_CORE0_CPU_PRI_12_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_12_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_13_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_13_REG (DR_REG_INTPRI_BASE + 0x40) +/** INTPRI_CORE0_CPU_PRI_13_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_13_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_13_MAP_M (INTPRI_CORE0_CPU_PRI_13_MAP_V << INTPRI_CORE0_CPU_PRI_13_MAP_S) +#define INTPRI_CORE0_CPU_PRI_13_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_13_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_14_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_14_REG (DR_REG_INTPRI_BASE + 0x44) +/** INTPRI_CORE0_CPU_PRI_14_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_14_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_14_MAP_M (INTPRI_CORE0_CPU_PRI_14_MAP_V << INTPRI_CORE0_CPU_PRI_14_MAP_S) +#define INTPRI_CORE0_CPU_PRI_14_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_14_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_15_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_15_REG (DR_REG_INTPRI_BASE + 0x48) +/** INTPRI_CORE0_CPU_PRI_15_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_15_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_15_MAP_M (INTPRI_CORE0_CPU_PRI_15_MAP_V << INTPRI_CORE0_CPU_PRI_15_MAP_S) +#define INTPRI_CORE0_CPU_PRI_15_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_15_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_16_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_16_REG (DR_REG_INTPRI_BASE + 0x4c) +/** INTPRI_CORE0_CPU_PRI_16_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_16_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_16_MAP_M (INTPRI_CORE0_CPU_PRI_16_MAP_V << INTPRI_CORE0_CPU_PRI_16_MAP_S) +#define INTPRI_CORE0_CPU_PRI_16_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_16_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_17_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_17_REG (DR_REG_INTPRI_BASE + 0x50) +/** INTPRI_CORE0_CPU_PRI_17_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_17_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_17_MAP_M (INTPRI_CORE0_CPU_PRI_17_MAP_V << INTPRI_CORE0_CPU_PRI_17_MAP_S) +#define INTPRI_CORE0_CPU_PRI_17_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_17_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_18_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_18_REG (DR_REG_INTPRI_BASE + 0x54) +/** INTPRI_CORE0_CPU_PRI_18_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_18_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_18_MAP_M (INTPRI_CORE0_CPU_PRI_18_MAP_V << INTPRI_CORE0_CPU_PRI_18_MAP_S) +#define INTPRI_CORE0_CPU_PRI_18_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_18_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_19_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_19_REG (DR_REG_INTPRI_BASE + 0x58) +/** INTPRI_CORE0_CPU_PRI_19_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_19_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_19_MAP_M (INTPRI_CORE0_CPU_PRI_19_MAP_V << INTPRI_CORE0_CPU_PRI_19_MAP_S) +#define INTPRI_CORE0_CPU_PRI_19_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_19_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_20_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_20_REG (DR_REG_INTPRI_BASE + 0x5c) +/** INTPRI_CORE0_CPU_PRI_20_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_20_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_20_MAP_M (INTPRI_CORE0_CPU_PRI_20_MAP_V << INTPRI_CORE0_CPU_PRI_20_MAP_S) +#define INTPRI_CORE0_CPU_PRI_20_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_20_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_21_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_21_REG (DR_REG_INTPRI_BASE + 0x60) +/** INTPRI_CORE0_CPU_PRI_21_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_21_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_21_MAP_M (INTPRI_CORE0_CPU_PRI_21_MAP_V << INTPRI_CORE0_CPU_PRI_21_MAP_S) +#define INTPRI_CORE0_CPU_PRI_21_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_21_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_22_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_22_REG (DR_REG_INTPRI_BASE + 0x64) +/** INTPRI_CORE0_CPU_PRI_22_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_22_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_22_MAP_M (INTPRI_CORE0_CPU_PRI_22_MAP_V << INTPRI_CORE0_CPU_PRI_22_MAP_S) +#define INTPRI_CORE0_CPU_PRI_22_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_22_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_23_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_23_REG (DR_REG_INTPRI_BASE + 0x68) +/** INTPRI_CORE0_CPU_PRI_23_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_23_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_23_MAP_M (INTPRI_CORE0_CPU_PRI_23_MAP_V << INTPRI_CORE0_CPU_PRI_23_MAP_S) +#define INTPRI_CORE0_CPU_PRI_23_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_23_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_24_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_24_REG (DR_REG_INTPRI_BASE + 0x6c) +/** INTPRI_CORE0_CPU_PRI_24_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_24_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_24_MAP_M (INTPRI_CORE0_CPU_PRI_24_MAP_V << INTPRI_CORE0_CPU_PRI_24_MAP_S) +#define INTPRI_CORE0_CPU_PRI_24_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_24_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_25_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_25_REG (DR_REG_INTPRI_BASE + 0x70) +/** INTPRI_CORE0_CPU_PRI_25_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_25_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_25_MAP_M (INTPRI_CORE0_CPU_PRI_25_MAP_V << INTPRI_CORE0_CPU_PRI_25_MAP_S) +#define INTPRI_CORE0_CPU_PRI_25_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_25_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_26_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_26_REG (DR_REG_INTPRI_BASE + 0x74) +/** INTPRI_CORE0_CPU_PRI_26_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_26_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_26_MAP_M (INTPRI_CORE0_CPU_PRI_26_MAP_V << INTPRI_CORE0_CPU_PRI_26_MAP_S) +#define INTPRI_CORE0_CPU_PRI_26_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_26_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_27_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_27_REG (DR_REG_INTPRI_BASE + 0x78) +/** INTPRI_CORE0_CPU_PRI_27_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_27_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_27_MAP_M (INTPRI_CORE0_CPU_PRI_27_MAP_V << INTPRI_CORE0_CPU_PRI_27_MAP_S) +#define INTPRI_CORE0_CPU_PRI_27_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_27_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_28_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_28_REG (DR_REG_INTPRI_BASE + 0x7c) +/** INTPRI_CORE0_CPU_PRI_28_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_28_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_28_MAP_M (INTPRI_CORE0_CPU_PRI_28_MAP_V << INTPRI_CORE0_CPU_PRI_28_MAP_S) +#define INTPRI_CORE0_CPU_PRI_28_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_28_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_29_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_29_REG (DR_REG_INTPRI_BASE + 0x80) +/** INTPRI_CORE0_CPU_PRI_29_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_29_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_29_MAP_M (INTPRI_CORE0_CPU_PRI_29_MAP_V << INTPRI_CORE0_CPU_PRI_29_MAP_S) +#define INTPRI_CORE0_CPU_PRI_29_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_29_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_30_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_30_REG (DR_REG_INTPRI_BASE + 0x84) +/** INTPRI_CORE0_CPU_PRI_30_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_30_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_30_MAP_M (INTPRI_CORE0_CPU_PRI_30_MAP_V << INTPRI_CORE0_CPU_PRI_30_MAP_S) +#define INTPRI_CORE0_CPU_PRI_30_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_30_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_PRI_31_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_PRI_31_REG (DR_REG_INTPRI_BASE + 0x88) +/** INTPRI_CORE0_CPU_PRI_31_MAP : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_PRI_31_MAP 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_31_MAP_M (INTPRI_CORE0_CPU_PRI_31_MAP_V << INTPRI_CORE0_CPU_PRI_31_MAP_S) +#define INTPRI_CORE0_CPU_PRI_31_MAP_V 0x0000000FU +#define INTPRI_CORE0_CPU_PRI_31_MAP_S 0 + +/** INTPRI_CORE0_CPU_INT_THRESH_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_THRESH_REG (DR_REG_INTPRI_BASE + 0x8c) +/** INTPRI_CORE0_CPU_INT_THRESH : R/W; bitpos: [7:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_INT_THRESH 0x000000FFU +#define INTPRI_CORE0_CPU_INT_THRESH_M (INTPRI_CORE0_CPU_INT_THRESH_V << INTPRI_CORE0_CPU_INT_THRESH_S) +#define INTPRI_CORE0_CPU_INT_THRESH_V 0x000000FFU +#define INTPRI_CORE0_CPU_INT_THRESH_S 0 + +/** INTPRI_CPU_INTR_FROM_CPU_0_REG register + * register description + */ +#define INTPRI_CPU_INTR_FROM_CPU_0_REG (DR_REG_INTPRI_BASE + 0x90) +/** INTPRI_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0; + * Need add description + */ +#define INTPRI_CPU_INTR_FROM_CPU_0 (BIT(0)) +#define INTPRI_CPU_INTR_FROM_CPU_0_M (INTPRI_CPU_INTR_FROM_CPU_0_V << INTPRI_CPU_INTR_FROM_CPU_0_S) +#define INTPRI_CPU_INTR_FROM_CPU_0_V 0x00000001U +#define INTPRI_CPU_INTR_FROM_CPU_0_S 0 + +/** INTPRI_CPU_INTR_FROM_CPU_1_REG register + * register description + */ +#define INTPRI_CPU_INTR_FROM_CPU_1_REG (DR_REG_INTPRI_BASE + 0x94) +/** INTPRI_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0; + * Need add description + */ +#define INTPRI_CPU_INTR_FROM_CPU_1 (BIT(0)) +#define INTPRI_CPU_INTR_FROM_CPU_1_M (INTPRI_CPU_INTR_FROM_CPU_1_V << INTPRI_CPU_INTR_FROM_CPU_1_S) +#define INTPRI_CPU_INTR_FROM_CPU_1_V 0x00000001U +#define INTPRI_CPU_INTR_FROM_CPU_1_S 0 + +/** INTPRI_CPU_INTR_FROM_CPU_2_REG register + * register description + */ +#define INTPRI_CPU_INTR_FROM_CPU_2_REG (DR_REG_INTPRI_BASE + 0x98) +/** INTPRI_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0; + * Need add description + */ +#define INTPRI_CPU_INTR_FROM_CPU_2 (BIT(0)) +#define INTPRI_CPU_INTR_FROM_CPU_2_M (INTPRI_CPU_INTR_FROM_CPU_2_V << INTPRI_CPU_INTR_FROM_CPU_2_S) +#define INTPRI_CPU_INTR_FROM_CPU_2_V 0x00000001U +#define INTPRI_CPU_INTR_FROM_CPU_2_S 0 + +/** INTPRI_CPU_INTR_FROM_CPU_3_REG register + * register description + */ +#define INTPRI_CPU_INTR_FROM_CPU_3_REG (DR_REG_INTPRI_BASE + 0x9c) +/** INTPRI_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0; + * Need add description + */ +#define INTPRI_CPU_INTR_FROM_CPU_3 (BIT(0)) +#define INTPRI_CPU_INTR_FROM_CPU_3_M (INTPRI_CPU_INTR_FROM_CPU_3_V << INTPRI_CPU_INTR_FROM_CPU_3_S) +#define INTPRI_CPU_INTR_FROM_CPU_3_V 0x00000001U +#define INTPRI_CPU_INTR_FROM_CPU_3_S 0 + +/** INTPRI_DATE_REG register + * register description + */ +#define INTPRI_DATE_REG (DR_REG_INTPRI_BASE + 0xa0) +/** INTPRI_DATE : R/W; bitpos: [27:0]; default: 35655824; + * Need add description + */ +#define INTPRI_DATE 0x0FFFFFFFU +#define INTPRI_DATE_M (INTPRI_DATE_V << INTPRI_DATE_S) +#define INTPRI_DATE_V 0x0FFFFFFFU +#define INTPRI_DATE_S 0 + +/** INTPRI_CLOCK_GATE_REG register + * register description + */ +#define INTPRI_CLOCK_GATE_REG (DR_REG_INTPRI_BASE + 0xa4) +/** INTPRI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Need add description + */ +#define INTPRI_CLK_EN (BIT(0)) +#define INTPRI_CLK_EN_M (INTPRI_CLK_EN_V << INTPRI_CLK_EN_S) +#define INTPRI_CLK_EN_V 0x00000001U +#define INTPRI_CLK_EN_S 0 + +/** INTPRI_CORE0_CPU_INT_CLEAR_REG register + * register description + */ +#define INTPRI_CORE0_CPU_INT_CLEAR_REG (DR_REG_INTPRI_BASE + 0xa8) +/** INTPRI_CORE0_CPU_INT_CLEAR : R/W; bitpos: [31:0]; default: 0; + * Need add description + */ +#define INTPRI_CORE0_CPU_INT_CLEAR 0xFFFFFFFFU +#define INTPRI_CORE0_CPU_INT_CLEAR_M (INTPRI_CORE0_CPU_INT_CLEAR_V << INTPRI_CORE0_CPU_INT_CLEAR_S) +#define INTPRI_CORE0_CPU_INT_CLEAR_V 0xFFFFFFFFU +#define INTPRI_CORE0_CPU_INT_CLEAR_S 0 + +/** INTPRI_RND_ECO_REG register + * redcy eco register. + */ +#define INTPRI_RND_ECO_REG (DR_REG_INTPRI_BASE + 0xac) +/** INTPRI_REDCY_ENA : W/R; bitpos: [0]; default: 0; + * Only reserved for ECO. + */ +#define INTPRI_REDCY_ENA (BIT(0)) +#define INTPRI_REDCY_ENA_M (INTPRI_REDCY_ENA_V << INTPRI_REDCY_ENA_S) +#define INTPRI_REDCY_ENA_V 0x00000001U +#define INTPRI_REDCY_ENA_S 0 +/** INTPRI_REDCY_RESULT : RO; bitpos: [1]; default: 0; + * Only reserved for ECO. + */ +#define INTPRI_REDCY_RESULT (BIT(1)) +#define INTPRI_REDCY_RESULT_M (INTPRI_REDCY_RESULT_V << INTPRI_REDCY_RESULT_S) +#define INTPRI_REDCY_RESULT_V 0x00000001U +#define INTPRI_REDCY_RESULT_S 1 + +/** INTPRI_RND_ECO_LOW_REG register + * redcy eco low register. + */ +#define INTPRI_RND_ECO_LOW_REG (DR_REG_INTPRI_BASE + 0xb0) +/** INTPRI_REDCY_LOW : W/R; bitpos: [31:0]; default: 0; + * Only reserved for ECO. + */ +#define INTPRI_REDCY_LOW 0xFFFFFFFFU +#define INTPRI_REDCY_LOW_M (INTPRI_REDCY_LOW_V << INTPRI_REDCY_LOW_S) +#define INTPRI_REDCY_LOW_V 0xFFFFFFFFU +#define INTPRI_REDCY_LOW_S 0 + +/** INTPRI_RND_ECO_HIGH_REG register + * redcy eco high register. + */ +#define INTPRI_RND_ECO_HIGH_REG (DR_REG_INTPRI_BASE + 0x3fc) +/** INTPRI_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295; + * Only reserved for ECO. + */ +#define INTPRI_REDCY_HIGH 0xFFFFFFFFU +#define INTPRI_REDCY_HIGH_M (INTPRI_REDCY_HIGH_V << INTPRI_REDCY_HIGH_S) +#define INTPRI_REDCY_HIGH_V 0xFFFFFFFFU +#define INTPRI_REDCY_HIGH_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/intpri_struct.h b/components/soc/esp32c6/include/soc/intpri_struct.h new file mode 100644 index 0000000000..9454470cb2 --- /dev/null +++ b/components/soc/esp32c6/include/soc/intpri_struct.h @@ -0,0 +1,256 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of core0_cpu_int_enable register + * register description + */ +typedef union { + struct { + /** core0_cpu_int_enable : R/W; bitpos: [31:0]; default: 0; + * Need add description + */ + uint32_t core0_cpu_int_enable:32; + }; + uint32_t val; +} intpri_core0_cpu_int_enable_reg_t; + +/** Type of core0_cpu_int_type register + * register description + */ +typedef union { + struct { + /** core0_cpu_int_type : R/W; bitpos: [31:0]; default: 0; + * Need add description + */ + uint32_t core0_cpu_int_type:32; + }; + uint32_t val; +} intpri_core0_cpu_int_type_reg_t; + +/** Type of core0_cpu_int_eip_status register + * register description + */ +typedef union { + struct { + /** core0_cpu_int_eip_status : RO; bitpos: [31:0]; default: 0; + * Need add description + */ + uint32_t core0_cpu_int_eip_status:32; + }; + uint32_t val; +} intpri_core0_cpu_int_eip_status_reg_t; + +/** Type of core0_cpu_int_pri_n register + * register description + */ +typedef union { + struct { + /** map : R/W; bitpos: [3:0]; default: 0; + * Need add description + */ + uint32_t map:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} intpri_core0_cpu_int_pri_n_reg_t; + +/** Type of core0_cpu_int_thresh register + * register description + */ +typedef union { + struct { + /** core0_cpu_int_thresh : R/W; bitpos: [7:0]; default: 0; + * Need add description + */ + uint32_t core0_cpu_int_thresh:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} intpri_core0_cpu_int_thresh_reg_t; + +/** Type of clock_gate register + * register description + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Need add description + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} intpri_clock_gate_reg_t; + +/** Type of core0_cpu_int_clear register + * register description + */ +typedef union { + struct { + /** core0_cpu_int_clear : R/W; bitpos: [31:0]; default: 0; + * Need add description + */ + uint32_t core0_cpu_int_clear:32; + }; + uint32_t val; +} intpri_core0_cpu_int_clear_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of cpu_intr_from_cpu_0 register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_0 : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t cpu_intr_from_cpu_0:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} intpri_cpu_intr_from_cpu_0_reg_t; + +/** Type of cpu_intr_from_cpu_1 register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_1 : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t cpu_intr_from_cpu_1:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} intpri_cpu_intr_from_cpu_1_reg_t; + +/** Type of cpu_intr_from_cpu_2 register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_2 : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t cpu_intr_from_cpu_2:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} intpri_cpu_intr_from_cpu_2_reg_t; + +/** Type of cpu_intr_from_cpu_3 register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_3 : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t cpu_intr_from_cpu_3:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} intpri_cpu_intr_from_cpu_3_reg_t; + + +/** Group: Version Registers */ +/** Type of date register + * register description + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35655824; + * Need add description + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} intpri_date_reg_t; + + +/** Group: Redcy ECO Registers */ +/** Type of rnd_eco register + * redcy eco register. + */ +typedef union { + struct { + /** redcy_ena : W/R; bitpos: [0]; default: 0; + * Only reserved for ECO. + */ + uint32_t redcy_ena:1; + /** redcy_result : RO; bitpos: [1]; default: 0; + * Only reserved for ECO. + */ + uint32_t redcy_result:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} intpri_rnd_eco_reg_t; + +/** Type of rnd_eco_low register + * redcy eco low register. + */ +typedef union { + struct { + /** redcy_low : W/R; bitpos: [31:0]; default: 0; + * Only reserved for ECO. + */ + uint32_t redcy_low:32; + }; + uint32_t val; +} intpri_rnd_eco_low_reg_t; + +/** Type of rnd_eco_high register + * redcy eco high register. + */ +typedef union { + struct { + /** redcy_high : W/R; bitpos: [31:0]; default: 4294967295; + * Only reserved for ECO. + */ + uint32_t redcy_high:32; + }; + uint32_t val; +} intpri_rnd_eco_high_reg_t; + + +typedef struct intpri_dev_t { + volatile intpri_core0_cpu_int_enable_reg_t core0_cpu_int_enable; + volatile intpri_core0_cpu_int_type_reg_t core0_cpu_int_type; + volatile intpri_core0_cpu_int_eip_status_reg_t core0_cpu_int_eip_status; + volatile intpri_core0_cpu_int_pri_n_reg_t core0_cpu_int_pri[32]; + volatile intpri_core0_cpu_int_thresh_reg_t core0_cpu_int_thresh; + volatile intpri_cpu_intr_from_cpu_0_reg_t cpu_intr_from_cpu_0; + volatile intpri_cpu_intr_from_cpu_1_reg_t cpu_intr_from_cpu_1; + volatile intpri_cpu_intr_from_cpu_2_reg_t cpu_intr_from_cpu_2; + volatile intpri_cpu_intr_from_cpu_3_reg_t cpu_intr_from_cpu_3; + volatile intpri_date_reg_t date; + volatile intpri_clock_gate_reg_t clock_gate; + volatile intpri_core0_cpu_int_clear_reg_t core0_cpu_int_clear; + volatile intpri_rnd_eco_reg_t rnd_eco; + volatile intpri_rnd_eco_low_reg_t rnd_eco_low; + uint32_t reserved_0b4[210]; + volatile intpri_rnd_eco_high_reg_t rnd_eco_high; +} intpri_dev_t; + +extern intpri_dev_t INTPRI; + +#ifndef __cplusplus +_Static_assert(sizeof(intpri_dev_t) == 0x400, "Invalid size of intpri_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/io_mux_reg.h b/components/soc/esp32c6/include/soc/io_mux_reg.h new file mode 100644 index 0000000000..8a0a64acec --- /dev/null +++ b/components/soc/esp32c6/include/soc/io_mux_reg.h @@ -0,0 +1,348 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once +#include "soc.h" + +/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ +/* Output enable in sleep mode */ +#define SLP_OE (BIT(0)) +#define SLP_OE_M (BIT(0)) +#define SLP_OE_V 1 +#define SLP_OE_S 0 +/* Pin used for wakeup from sleep */ +#define SLP_SEL (BIT(1)) +#define SLP_SEL_M (BIT(1)) +#define SLP_SEL_V 1 +#define SLP_SEL_S 1 +/* Pulldown enable in sleep mode */ +#define SLP_PD (BIT(2)) +#define SLP_PD_M (BIT(2)) +#define SLP_PD_V 1 +#define SLP_PD_S 2 +/* Pullup enable in sleep mode */ +#define SLP_PU (BIT(3)) +#define SLP_PU_M (BIT(3)) +#define SLP_PU_V 1 +#define SLP_PU_S 3 +/* Input enable in sleep mode */ +#define SLP_IE (BIT(4)) +#define SLP_IE_M (BIT(4)) +#define SLP_IE_V 1 +#define SLP_IE_S 4 +/* Drive strength in sleep mode */ +#define SLP_DRV 0x3 +#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S) +#define SLP_DRV_V 0x3 +#define SLP_DRV_S 5 +/* Pulldown enable */ +#define FUN_PD (BIT(7)) +#define FUN_PD_M (BIT(7)) +#define FUN_PD_V 1 +#define FUN_PD_S 7 +/* Pullup enable */ +#define FUN_PU (BIT(8)) +#define FUN_PU_M (BIT(8)) +#define FUN_PU_V 1 +#define FUN_PU_S 8 +/* Input enable */ +#define FUN_IE (BIT(9)) +#define FUN_IE_M (FUN_IE_V << FUN_IE_S) +#define FUN_IE_V 1 +#define FUN_IE_S 9 +/* Drive strength */ +#define FUN_DRV 0x3 +#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S) +#define FUN_DRV_V 0x3 +#define FUN_DRV_S 10 +/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */ +#define MCU_SEL 0x7 +#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S) +#define MCU_SEL_V 0x7 +#define MCU_SEL_S 12 + +#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); +#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) +#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) +#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) + +#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_XTAL_32K_P_U +#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_XTAL_32K_N_U +#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U +#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U +#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_MTMS_U +#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_MTDI_U +#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_MTCK_U +#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_MTDO_U +#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U +#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U +#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U +#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_GPIO11_U +#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U +#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_GPIO13_U +#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_GPIO14_U +#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_GPIO15_U +#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_U0TXD_U +#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_U0RXD_U +#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_SDIO_CMD_U +#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_SDIO_CLK_U +#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_SDIO_DATA0_U +#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_SDIO_DATA1_U +#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_SDIO_DATA2_U +#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_SDIO_DATA3_U +#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_SPICS0_U +#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_SPIQ_U +#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_SPIWP_U +#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_VDD_SPI_U +#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_SPIHD_U +#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_SPICLK_U +#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_SPID_U + +#define PIN_FUNC_GPIO 1 + +#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) + +#define SPI_HD_GPIO_NUM 28 +#define SPI_WP_GPIO_NUM 26 +#define SPI_CS0_GPIO_NUM 24 +#define SPI_CLK_GPIO_NUM 29 +#define SPI_D_GPIO_NUM 30 +#define SPI_Q_GPIO_NUM 25 + +#define SD_CLK_GPIO_NUM 19 +#define SD_CMD_GPIO_NUM 18 +#define SD_DATA0_GPIO_NUM 20 +#define SD_DATA1_GPIO_NUM 21 +#define SD_DATA2_GPIO_NUM 22 +#define SD_DATA3_GPIO_NUM 23 + +#define MAX_RTC_GPIO_NUM 5 +#define MAX_PAD_GPIO_NUM 30 +#define MAX_GPIO_NUM 34 +#define DIG_IO_HOLD_BIT_SHIFT 32 + + +#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE +#define PIN_CTRL (REG_IO_MUX_BASE +0x00) +#define PAD_POWER_SEL BIT(15) +#define PAD_POWER_SEL_V 0x1 +#define PAD_POWER_SEL_M BIT(15) +#define PAD_POWER_SEL_S 15 + +#define PAD_POWER_SWITCH_DELAY 0x7 +#define PAD_POWER_SWITCH_DELAY_V 0x7 +#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S) +#define PAD_POWER_SWITCH_DELAY_S 12 + +#define CLK_OUT3 0xf +#define CLK_OUT3_V CLK_OUT3 +#define CLK_OUT3_S 8 +#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S) +#define CLK_OUT2 0xf +#define CLK_OUT2_V CLK_OUT2 +#define CLK_OUT2_S 4 +#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S) +#define CLK_OUT1 0xf +#define CLK_OUT1_V CLK_OUT1 +#define CLK_OUT1_S 0 +#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S) +// definitions above are inherited from previous version of code, should double check + +// definitions below are generated from pin_txt.csv +#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE + 0x4) +#define FUNC_XTAL_32K_P_GPIO0 1 +#define FUNC_XTAL_32K_P_GPIO0_0 0 + +#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE + 0x8) +#define FUNC_XTAL_32K_N_GPIO1 1 +#define FUNC_XTAL_32K_N_GPIO1_0 0 + +#define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE + 0xC) +#define FUNC_GPIO2_FSPIQ 2 +#define FUNC_GPIO2_GPIO2 1 +#define FUNC_GPIO2_GPIO2_0 0 + +#define PERIPHS_IO_MUX_GPIO3_U (REG_IO_MUX_BASE + 0x10) +#define FUNC_GPIO3_GPIO3 1 +#define FUNC_GPIO3_GPIO3_0 0 + +#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE + 0x14) +#define FUNC_MTMS_FSPIHD 2 +#define FUNC_MTMS_GPIO4 1 +#define FUNC_MTMS_MTMS 0 + +#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE + 0x18) +#define FUNC_MTDI_FSPIWP 2 +#define FUNC_MTDI_GPIO5 1 +#define FUNC_MTDI_MTDI 0 + +#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE + 0x1C) +#define FUNC_MTCK_FSPICLK 2 +#define FUNC_MTCK_GPIO6 1 +#define FUNC_MTCK_MTCK 0 + +#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE + 0x20) +#define FUNC_MTDO_FSPID 2 +#define FUNC_MTDO_GPIO7 1 +#define FUNC_MTDO_MTDO 0 + +#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE + 0x24) +#define FUNC_GPIO8_GPIO8 1 +#define FUNC_GPIO8_GPIO8_0 0 + +#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE + 0x28) +#define FUNC_GPIO9_GPIO9 1 +#define FUNC_GPIO9_GPIO9_0 0 + +#define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE + 0x2C) +#define FUNC_GPIO10_GPIO10 1 +#define FUNC_GPIO10_GPIO10_0 0 + +#define PERIPHS_IO_MUX_GPIO11_U (REG_IO_MUX_BASE + 0x30) +#define FUNC_GPIO11_GPIO11 1 +#define FUNC_GPIO11_GPIO11_0 0 + +#define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE + 0x34) +#define FUNC_GPIO12_GPIO12 1 +#define FUNC_GPIO12_GPIO12_0 0 + +#define PERIPHS_IO_MUX_GPIO13_U (REG_IO_MUX_BASE + 0x38) +#define FUNC_GPIO13_GPIO13 1 +#define FUNC_GPIO13_GPIO13_0 0 + +#define PERIPHS_IO_MUX_GPIO14_U (REG_IO_MUX_BASE + 0x3C) +#define FUNC_GPIO14_GPIO14 1 +#define FUNC_GPIO14_GPIO14_0 0 + +#define PERIPHS_IO_MUX_GPIO15_U (REG_IO_MUX_BASE + 0x40) +#define FUNC_GPIO15_GPIO15 1 +#define FUNC_GPIO15_GPIO15_0 0 + +#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE + 0x44) +#define FUNC_U0TXD_FSPICS0 2 +#define FUNC_U0TXD_GPIO16 1 +#define FUNC_U0TXD_U0TXD 0 + +#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE + 0x48) +#define FUNC_U0RXD_FSPICS1 2 +#define FUNC_U0RXD_GPIO17 1 +#define FUNC_U0RXD_U0RXD 0 + +#define PERIPHS_IO_MUX_SDIO_CMD_U (REG_IO_MUX_BASE + 0x4C) +#define FUNC_SDIO_CMD_FSPICS2 2 +#define FUNC_SDIO_CMD_GPIO18 1 +#define FUNC_SDIO_CMD_SDIO_CMD 0 + +#define PERIPHS_IO_MUX_SDIO_CLK_U (REG_IO_MUX_BASE + 0x50) +#define FUNC_SDIO_CLK_FSPICS3 2 +#define FUNC_SDIO_CLK_GPIO19 1 +#define FUNC_SDIO_CLK_SDIO_CLK 0 + +#define PERIPHS_IO_MUX_SDIO_DATA0_U (REG_IO_MUX_BASE + 0x54) +#define FUNC_SDIO_DATA0_FSPICS4 2 +#define FUNC_SDIO_DATA0_GPIO20 1 +#define FUNC_SDIO_DATA0_SDIO_DATA0 0 + +#define PERIPHS_IO_MUX_SDIO_DATA1_U (REG_IO_MUX_BASE + 0x58) +#define FUNC_SDIO_DATA1_FSPICS5 2 +#define FUNC_SDIO_DATA1_GPIO21 1 +#define FUNC_SDIO_DATA1_SDIO_DATA1 0 + +#define PERIPHS_IO_MUX_SDIO_DATA2_U (REG_IO_MUX_BASE + 0x5C) +#define FUNC_SDIO_DATA2_GPIO22 1 +#define FUNC_SDIO_DATA2_SDIO_DATA2 0 + +#define PERIPHS_IO_MUX_SDIO_DATA3_U (REG_IO_MUX_BASE + 0x60) +#define FUNC_SDIO_DATA3_GPIO23 1 +#define FUNC_SDIO_DATA3_SDIO_DATA3 0 + +#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE + 0x64) +#define FUNC_SPICS0_GPIO24 1 +#define FUNC_SPICS0_SPICS0 0 + +#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE + 0x68) +#define FUNC_SPIQ_GPIO25 1 +#define FUNC_SPIQ_SPIQ 0 + +#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE + 0x6C) +#define FUNC_SPIWP_GPIO26 1 +#define FUNC_SPIWP_SPIWP 0 + +#define PERIPHS_IO_MUX_VDD_SPI_U (REG_IO_MUX_BASE + 0x70) +#define FUNC_VDD_SPI_GPIO27 1 +#define FUNC_VDD_SPI_GPIO27_0 0 + +#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE + 0x74) +#define FUNC_SPIHD_GPIO28 1 +#define FUNC_SPIHD_SPIHD 0 + +#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE + 0x78) +#define FUNC_SPICLK_GPIO29 1 +#define FUNC_SPICLK_SPICLK 0 + +#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE + 0x7C) +#define FUNC_SPID_GPIO30 1 +#define FUNC_SPID_SPID 0 + +/** IO_MUX_PIN_CTRL_REG register + * Clock Output Configuration Register + */ +#define IO_MUX_PIN_CTRL_REG (REG_IO_MUX_BASE + 0x0) +/** IO_MUX_CLK_OUT1 : R/W; bitpos: [4:0]; default: 15; + * If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. + * CLK_OUT_out1 can be found in peripheral output signals. + */ +#define IO_MUX_CLK_OUT1 0x0000001FU +#define IO_MUX_CLK_OUT1_M (IO_MUX_CLK_OUT1_V << IO_MUX_CLK_OUT1_S) +#define IO_MUX_CLK_OUT1_V 0x0000001FU +#define IO_MUX_CLK_OUT1_S 0 +/** IO_MUX_CLK_OUT2 : R/W; bitpos: [9:5]; default: 15; + * If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. + * CLK_OUT_out2 can be found in peripheral output signals. + */ +#define IO_MUX_CLK_OUT2 0x0000001FU +#define IO_MUX_CLK_OUT2_M (IO_MUX_CLK_OUT2_V << IO_MUX_CLK_OUT2_S) +#define IO_MUX_CLK_OUT2_V 0x0000001FU +#define IO_MUX_CLK_OUT2_S 5 +/** IO_MUX_CLK_OUT3 : R/W; bitpos: [14:10]; default: 7; + * If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. + * CLK_OUT_out3 can be found in peripheral output signals. + */ +#define IO_MUX_CLK_OUT3 0x0000001FU +#define IO_MUX_CLK_OUT3_M (IO_MUX_CLK_OUT3_V << IO_MUX_CLK_OUT3_S) +#define IO_MUX_CLK_OUT3_V 0x0000001FU +#define IO_MUX_CLK_OUT3_S 10 + +/** IO_MUX_MODEM_DIAG_EN_REG register + * GPIO MATRIX Configure Register for modem diag + */ +#define IO_MUX_MODEM_DIAG_EN_REG (REG_IO_MUX_BASE + 0xbc) +/** IO_MUX_MODEM_DIAG_EN : R/W; bitpos: [31:0]; default: 0; + * bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i] into gpio + * matrix. 0:enable other signals into gpio matrix + */ +#define IO_MUX_MODEM_DIAG_EN 0xFFFFFFFFU +#define IO_MUX_MODEM_DIAG_EN_M (IO_MUX_MODEM_DIAG_EN_V << IO_MUX_MODEM_DIAG_EN_S) +#define IO_MUX_MODEM_DIAG_EN_V 0xFFFFFFFFU +#define IO_MUX_MODEM_DIAG_EN_S 0 + +/** IO_MUX_DATE_REG register + * IO MUX Version Control Register + */ +#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc) +/** IO_MUX_REG_DATE : R/W; bitpos: [27:0]; default: 35655776; + * Version control register + */ +#define IO_MUX_REG_DATE 0x0FFFFFFFU +#define IO_MUX_REG_DATE_M (IO_MUX_REG_DATE_V << IO_MUX_REG_DATE_S) +#define IO_MUX_REG_DATE_V 0x0FFFFFFFU +#define IO_MUX_REG_DATE_S 0 diff --git a/components/soc/esp32c6/include/soc/ledc_reg.h b/components/soc/esp32c6/include/soc/ledc_reg.h new file mode 100644 index 0000000000..a7c4311ad1 --- /dev/null +++ b/components/soc/esp32c6/include/soc/ledc_reg.h @@ -0,0 +1,2775 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LEDC_CH0_CONF0_REG register + * Configuration register 0 for channel 0 + */ +#define LEDC_CH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0) +/** LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 0. + * + * 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3 + */ +#define LEDC_TIMER_SEL_CH0 0x00000003U +#define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S) +#define LEDC_TIMER_SEL_CH0_V 0x00000003U +#define LEDC_TIMER_SEL_CH0_S 0 +/** LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 0. + */ +#define LEDC_SIG_OUT_EN_CH0 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S) +#define LEDC_SIG_OUT_EN_CH0_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH0_S 2 +/** LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 0 is inactive (when + * LEDC_SIG_OUT_EN_CH0 is 0). + */ +#define LEDC_IDLE_LV_CH0 (BIT(3)) +#define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S) +#define LEDC_IDLE_LV_CH0_V 0x00000001U +#define LEDC_IDLE_LV_CH0_S 3 +/** LEDC_PARA_UP_CH0 : WT; bitpos: [4]; default: 0; + * This bit is used to update LEDC_HPOINT_CH0, LEDC_DUTY_START_CH0, + * LEDC_SIG_OUT_EN_CH0, LEDC_TIMER_SEL_CH0, LEDC_DUTY_NUM_CH0, LEDC_DUTY_CYCLE_CH0, + * LEDC_DUTY_SCALE_CH0, LEDC_DUTY_INC_CH0, and LEDC_OVF_CNT_EN_CH0 fields for channel + * 0, and will be automatically cleared by hardware. + */ +#define LEDC_PARA_UP_CH0 (BIT(4)) +#define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S) +#define LEDC_PARA_UP_CH0_V 0x00000001U +#define LEDC_PARA_UP_CH0_S 4 +/** LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH0_INT interrupt will be triggered when channel 0 overflows for + * (LEDC_OVF_NUM_CH0 + 1) times. + */ +#define LEDC_OVF_NUM_CH0 0x000003FFU +#define LEDC_OVF_NUM_CH0_M (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S) +#define LEDC_OVF_NUM_CH0_V 0x000003FFU +#define LEDC_OVF_NUM_CH0_S 5 +/** LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 0. + */ +#define LEDC_OVF_CNT_EN_CH0 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S) +#define LEDC_OVF_CNT_EN_CH0_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH0_S 15 +/** LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 0. + */ +#define LEDC_OVF_CNT_RESET_CH0 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S) +#define LEDC_OVF_CNT_RESET_CH0_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH0_S 16 + +/** LEDC_CH0_HPOINT_REG register + * High point register for channel 0 + */ +#define LEDC_CH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x4) +/** LEDC_HPOINT_CH0 : R/W; bitpos: [19:0]; default: 0; + * The output value changes to high when the selected timers has reached the value + * specified by this register. + */ +#define LEDC_HPOINT_CH0 0x000FFFFFU +#define LEDC_HPOINT_CH0_M (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S) +#define LEDC_HPOINT_CH0_V 0x000FFFFFU +#define LEDC_HPOINT_CH0_S 0 + +/** LEDC_CH0_DUTY_REG register + * Initial duty cycle for channel 0 + */ +#define LEDC_CH0_DUTY_REG (DR_REG_LEDC_BASE + 0x8) +/** LEDC_DUTY_CH0 : R/W; bitpos: [24:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the Lpoint. + */ +#define LEDC_DUTY_CH0 0x01FFFFFFU +#define LEDC_DUTY_CH0_M (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S) +#define LEDC_DUTY_CH0_V 0x01FFFFFFU +#define LEDC_DUTY_CH0_S 0 + +/** LEDC_CH0_CONF1_REG register + * Configuration register 1 for channel 0 + */ +#define LEDC_CH0_CONF1_REG (DR_REG_LEDC_BASE + 0xc) +/** LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH0_CONF1_REG will start to take effect when this + * bit is set to 1. + */ +#define LEDC_DUTY_START_CH0 (BIT(31)) +#define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S) +#define LEDC_DUTY_START_CH0_V 0x00000001U +#define LEDC_DUTY_START_CH0_S 31 + +/** LEDC_CH0_DUTY_R_REG register + * Current duty cycle for channel 0 + */ +#define LEDC_CH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x10) +/** LEDC_DUTY_CH0_R : RO; bitpos: [24:0]; default: 0; + * This register stores the current duty of output signal on channel 0. + */ +#define LEDC_DUTY_CH0_R 0x01FFFFFFU +#define LEDC_DUTY_CH0_R_M (LEDC_DUTY_CH0_R_V << LEDC_DUTY_CH0_R_S) +#define LEDC_DUTY_CH0_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH0_R_S 0 + +/** LEDC_CH1_CONF0_REG register + * Configuration register 0 for channel 1 + */ +#define LEDC_CH1_CONF0_REG (DR_REG_LEDC_BASE + 0x14) +/** LEDC_TIMER_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 1. + * + * 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3 + */ +#define LEDC_TIMER_SEL_CH1 0x00000003U +#define LEDC_TIMER_SEL_CH1_M (LEDC_TIMER_SEL_CH1_V << LEDC_TIMER_SEL_CH1_S) +#define LEDC_TIMER_SEL_CH1_V 0x00000003U +#define LEDC_TIMER_SEL_CH1_S 0 +/** LEDC_SIG_OUT_EN_CH1 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 1. + */ +#define LEDC_SIG_OUT_EN_CH1 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH1_M (LEDC_SIG_OUT_EN_CH1_V << LEDC_SIG_OUT_EN_CH1_S) +#define LEDC_SIG_OUT_EN_CH1_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH1_S 2 +/** LEDC_IDLE_LV_CH1 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 1 is inactive (when + * LEDC_SIG_OUT_EN_CH1 is 0). + */ +#define LEDC_IDLE_LV_CH1 (BIT(3)) +#define LEDC_IDLE_LV_CH1_M (LEDC_IDLE_LV_CH1_V << LEDC_IDLE_LV_CH1_S) +#define LEDC_IDLE_LV_CH1_V 0x00000001U +#define LEDC_IDLE_LV_CH1_S 3 +/** LEDC_PARA_UP_CH1 : WT; bitpos: [4]; default: 0; + * This bit is used to update LEDC_HPOINT_CH1, LEDC_DUTY_START_CH1, + * LEDC_SIG_OUT_EN_CH1, LEDC_TIMER_SEL_CH1, LEDC_DUTY_NUM_CH1, LEDC_DUTY_CYCLE_CH1, + * LEDC_DUTY_SCALE_CH1, LEDC_DUTY_INC_CH1, and LEDC_OVF_CNT_EN_CH1 fields for channel + * 1, and will be automatically cleared by hardware. + */ +#define LEDC_PARA_UP_CH1 (BIT(4)) +#define LEDC_PARA_UP_CH1_M (LEDC_PARA_UP_CH1_V << LEDC_PARA_UP_CH1_S) +#define LEDC_PARA_UP_CH1_V 0x00000001U +#define LEDC_PARA_UP_CH1_S 4 +/** LEDC_OVF_NUM_CH1 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH1_INT interrupt will be triggered when channel 1 overflows for + * (LEDC_OVF_NUM_CH1 + 1) times. + */ +#define LEDC_OVF_NUM_CH1 0x000003FFU +#define LEDC_OVF_NUM_CH1_M (LEDC_OVF_NUM_CH1_V << LEDC_OVF_NUM_CH1_S) +#define LEDC_OVF_NUM_CH1_V 0x000003FFU +#define LEDC_OVF_NUM_CH1_S 5 +/** LEDC_OVF_CNT_EN_CH1 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 1. + */ +#define LEDC_OVF_CNT_EN_CH1 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH1_M (LEDC_OVF_CNT_EN_CH1_V << LEDC_OVF_CNT_EN_CH1_S) +#define LEDC_OVF_CNT_EN_CH1_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH1_S 15 +/** LEDC_OVF_CNT_RESET_CH1 : WT; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 1. + */ +#define LEDC_OVF_CNT_RESET_CH1 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH1_M (LEDC_OVF_CNT_RESET_CH1_V << LEDC_OVF_CNT_RESET_CH1_S) +#define LEDC_OVF_CNT_RESET_CH1_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH1_S 16 + +/** LEDC_CH1_HPOINT_REG register + * High point register for channel 1 + */ +#define LEDC_CH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x18) +/** LEDC_HPOINT_CH1 : R/W; bitpos: [19:0]; default: 0; + * The output value changes to high when the selected timers has reached the value + * specified by this register. + */ +#define LEDC_HPOINT_CH1 0x000FFFFFU +#define LEDC_HPOINT_CH1_M (LEDC_HPOINT_CH1_V << LEDC_HPOINT_CH1_S) +#define LEDC_HPOINT_CH1_V 0x000FFFFFU +#define LEDC_HPOINT_CH1_S 0 + +/** LEDC_CH1_DUTY_REG register + * Initial duty cycle for channel 1 + */ +#define LEDC_CH1_DUTY_REG (DR_REG_LEDC_BASE + 0x1c) +/** LEDC_DUTY_CH1 : R/W; bitpos: [24:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the Lpoint. + */ +#define LEDC_DUTY_CH1 0x01FFFFFFU +#define LEDC_DUTY_CH1_M (LEDC_DUTY_CH1_V << LEDC_DUTY_CH1_S) +#define LEDC_DUTY_CH1_V 0x01FFFFFFU +#define LEDC_DUTY_CH1_S 0 + +/** LEDC_CH1_CONF1_REG register + * Configuration register 1 for channel 1 + */ +#define LEDC_CH1_CONF1_REG (DR_REG_LEDC_BASE + 0x20) +/** LEDC_DUTY_START_CH1 : R/W/SC; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH1_CONF1_REG will start to take effect when this + * bit is set to 1. + */ +#define LEDC_DUTY_START_CH1 (BIT(31)) +#define LEDC_DUTY_START_CH1_M (LEDC_DUTY_START_CH1_V << LEDC_DUTY_START_CH1_S) +#define LEDC_DUTY_START_CH1_V 0x00000001U +#define LEDC_DUTY_START_CH1_S 31 + +/** LEDC_CH1_DUTY_R_REG register + * Current duty cycle for channel 1 + */ +#define LEDC_CH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x24) +/** LEDC_DUTY_CH1_R : RO; bitpos: [24:0]; default: 0; + * This register stores the current duty of output signal on channel 1. + */ +#define LEDC_DUTY_CH1_R 0x01FFFFFFU +#define LEDC_DUTY_CH1_R_M (LEDC_DUTY_CH1_R_V << LEDC_DUTY_CH1_R_S) +#define LEDC_DUTY_CH1_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH1_R_S 0 + +/** LEDC_CH2_CONF0_REG register + * Configuration register 0 for channel 2 + */ +#define LEDC_CH2_CONF0_REG (DR_REG_LEDC_BASE + 0x28) +/** LEDC_TIMER_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 2. + * + * 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3 + */ +#define LEDC_TIMER_SEL_CH2 0x00000003U +#define LEDC_TIMER_SEL_CH2_M (LEDC_TIMER_SEL_CH2_V << LEDC_TIMER_SEL_CH2_S) +#define LEDC_TIMER_SEL_CH2_V 0x00000003U +#define LEDC_TIMER_SEL_CH2_S 0 +/** LEDC_SIG_OUT_EN_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 2. + */ +#define LEDC_SIG_OUT_EN_CH2 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH2_M (LEDC_SIG_OUT_EN_CH2_V << LEDC_SIG_OUT_EN_CH2_S) +#define LEDC_SIG_OUT_EN_CH2_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH2_S 2 +/** LEDC_IDLE_LV_CH2 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 2 is inactive (when + * LEDC_SIG_OUT_EN_CH2 is 0). + */ +#define LEDC_IDLE_LV_CH2 (BIT(3)) +#define LEDC_IDLE_LV_CH2_M (LEDC_IDLE_LV_CH2_V << LEDC_IDLE_LV_CH2_S) +#define LEDC_IDLE_LV_CH2_V 0x00000001U +#define LEDC_IDLE_LV_CH2_S 3 +/** LEDC_PARA_UP_CH2 : WT; bitpos: [4]; default: 0; + * This bit is used to update LEDC_HPOINT_CH2, LEDC_DUTY_START_CH2, + * LEDC_SIG_OUT_EN_CH2, LEDC_TIMER_SEL_CH2, LEDC_DUTY_NUM_CH2, LEDC_DUTY_CYCLE_CH2, + * LEDC_DUTY_SCALE_CH2, LEDC_DUTY_INC_CH2, and LEDC_OVF_CNT_EN_CH2 fields for channel + * 2, and will be automatically cleared by hardware. + */ +#define LEDC_PARA_UP_CH2 (BIT(4)) +#define LEDC_PARA_UP_CH2_M (LEDC_PARA_UP_CH2_V << LEDC_PARA_UP_CH2_S) +#define LEDC_PARA_UP_CH2_V 0x00000001U +#define LEDC_PARA_UP_CH2_S 4 +/** LEDC_OVF_NUM_CH2 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH2_INT interrupt will be triggered when channel 2 overflows for + * (LEDC_OVF_NUM_CH2 + 1) times. + */ +#define LEDC_OVF_NUM_CH2 0x000003FFU +#define LEDC_OVF_NUM_CH2_M (LEDC_OVF_NUM_CH2_V << LEDC_OVF_NUM_CH2_S) +#define LEDC_OVF_NUM_CH2_V 0x000003FFU +#define LEDC_OVF_NUM_CH2_S 5 +/** LEDC_OVF_CNT_EN_CH2 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 2. + */ +#define LEDC_OVF_CNT_EN_CH2 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH2_M (LEDC_OVF_CNT_EN_CH2_V << LEDC_OVF_CNT_EN_CH2_S) +#define LEDC_OVF_CNT_EN_CH2_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH2_S 15 +/** LEDC_OVF_CNT_RESET_CH2 : WT; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 2. + */ +#define LEDC_OVF_CNT_RESET_CH2 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH2_M (LEDC_OVF_CNT_RESET_CH2_V << LEDC_OVF_CNT_RESET_CH2_S) +#define LEDC_OVF_CNT_RESET_CH2_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH2_S 16 + +/** LEDC_CH2_HPOINT_REG register + * High point register for channel 2 + */ +#define LEDC_CH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x2c) +/** LEDC_HPOINT_CH2 : R/W; bitpos: [19:0]; default: 0; + * The output value changes to high when the selected timers has reached the value + * specified by this register. + */ +#define LEDC_HPOINT_CH2 0x000FFFFFU +#define LEDC_HPOINT_CH2_M (LEDC_HPOINT_CH2_V << LEDC_HPOINT_CH2_S) +#define LEDC_HPOINT_CH2_V 0x000FFFFFU +#define LEDC_HPOINT_CH2_S 0 + +/** LEDC_CH2_DUTY_REG register + * Initial duty cycle for channel 2 + */ +#define LEDC_CH2_DUTY_REG (DR_REG_LEDC_BASE + 0x30) +/** LEDC_DUTY_CH2 : R/W; bitpos: [24:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the Lpoint. + */ +#define LEDC_DUTY_CH2 0x01FFFFFFU +#define LEDC_DUTY_CH2_M (LEDC_DUTY_CH2_V << LEDC_DUTY_CH2_S) +#define LEDC_DUTY_CH2_V 0x01FFFFFFU +#define LEDC_DUTY_CH2_S 0 + +/** LEDC_CH2_CONF1_REG register + * Configuration register 1 for channel 2 + */ +#define LEDC_CH2_CONF1_REG (DR_REG_LEDC_BASE + 0x34) +/** LEDC_DUTY_START_CH2 : R/W/SC; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH2_CONF1_REG will start to take effect when this + * bit is set to 1. + */ +#define LEDC_DUTY_START_CH2 (BIT(31)) +#define LEDC_DUTY_START_CH2_M (LEDC_DUTY_START_CH2_V << LEDC_DUTY_START_CH2_S) +#define LEDC_DUTY_START_CH2_V 0x00000001U +#define LEDC_DUTY_START_CH2_S 31 + +/** LEDC_CH2_DUTY_R_REG register + * Current duty cycle for channel 2 + */ +#define LEDC_CH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x38) +/** LEDC_DUTY_CH2_R : RO; bitpos: [24:0]; default: 0; + * This register stores the current duty of output signal on channel 2. + */ +#define LEDC_DUTY_CH2_R 0x01FFFFFFU +#define LEDC_DUTY_CH2_R_M (LEDC_DUTY_CH2_R_V << LEDC_DUTY_CH2_R_S) +#define LEDC_DUTY_CH2_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH2_R_S 0 + +/** LEDC_CH3_CONF0_REG register + * Configuration register 0 for channel 3 + */ +#define LEDC_CH3_CONF0_REG (DR_REG_LEDC_BASE + 0x3c) +/** LEDC_TIMER_SEL_CH3 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 3. + * + * 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3 + */ +#define LEDC_TIMER_SEL_CH3 0x00000003U +#define LEDC_TIMER_SEL_CH3_M (LEDC_TIMER_SEL_CH3_V << LEDC_TIMER_SEL_CH3_S) +#define LEDC_TIMER_SEL_CH3_V 0x00000003U +#define LEDC_TIMER_SEL_CH3_S 0 +/** LEDC_SIG_OUT_EN_CH3 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 3. + */ +#define LEDC_SIG_OUT_EN_CH3 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH3_M (LEDC_SIG_OUT_EN_CH3_V << LEDC_SIG_OUT_EN_CH3_S) +#define LEDC_SIG_OUT_EN_CH3_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH3_S 2 +/** LEDC_IDLE_LV_CH3 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 3 is inactive (when + * LEDC_SIG_OUT_EN_CH3 is 0). + */ +#define LEDC_IDLE_LV_CH3 (BIT(3)) +#define LEDC_IDLE_LV_CH3_M (LEDC_IDLE_LV_CH3_V << LEDC_IDLE_LV_CH3_S) +#define LEDC_IDLE_LV_CH3_V 0x00000001U +#define LEDC_IDLE_LV_CH3_S 3 +/** LEDC_PARA_UP_CH3 : WT; bitpos: [4]; default: 0; + * This bit is used to update LEDC_HPOINT_CH3, LEDC_DUTY_START_CH3, + * LEDC_SIG_OUT_EN_CH3, LEDC_TIMER_SEL_CH3, LEDC_DUTY_NUM_CH3, LEDC_DUTY_CYCLE_CH3, + * LEDC_DUTY_SCALE_CH3, LEDC_DUTY_INC_CH3, and LEDC_OVF_CNT_EN_CH3 fields for channel + * 3, and will be automatically cleared by hardware. + */ +#define LEDC_PARA_UP_CH3 (BIT(4)) +#define LEDC_PARA_UP_CH3_M (LEDC_PARA_UP_CH3_V << LEDC_PARA_UP_CH3_S) +#define LEDC_PARA_UP_CH3_V 0x00000001U +#define LEDC_PARA_UP_CH3_S 4 +/** LEDC_OVF_NUM_CH3 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH3_INT interrupt will be triggered when channel 3 overflows for + * (LEDC_OVF_NUM_CH3 + 1) times. + */ +#define LEDC_OVF_NUM_CH3 0x000003FFU +#define LEDC_OVF_NUM_CH3_M (LEDC_OVF_NUM_CH3_V << LEDC_OVF_NUM_CH3_S) +#define LEDC_OVF_NUM_CH3_V 0x000003FFU +#define LEDC_OVF_NUM_CH3_S 5 +/** LEDC_OVF_CNT_EN_CH3 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 3. + */ +#define LEDC_OVF_CNT_EN_CH3 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH3_M (LEDC_OVF_CNT_EN_CH3_V << LEDC_OVF_CNT_EN_CH3_S) +#define LEDC_OVF_CNT_EN_CH3_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH3_S 15 +/** LEDC_OVF_CNT_RESET_CH3 : WT; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 3. + */ +#define LEDC_OVF_CNT_RESET_CH3 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH3_M (LEDC_OVF_CNT_RESET_CH3_V << LEDC_OVF_CNT_RESET_CH3_S) +#define LEDC_OVF_CNT_RESET_CH3_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH3_S 16 + +/** LEDC_CH3_HPOINT_REG register + * High point register for channel 3 + */ +#define LEDC_CH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x40) +/** LEDC_HPOINT_CH3 : R/W; bitpos: [19:0]; default: 0; + * The output value changes to high when the selected timers has reached the value + * specified by this register. + */ +#define LEDC_HPOINT_CH3 0x000FFFFFU +#define LEDC_HPOINT_CH3_M (LEDC_HPOINT_CH3_V << LEDC_HPOINT_CH3_S) +#define LEDC_HPOINT_CH3_V 0x000FFFFFU +#define LEDC_HPOINT_CH3_S 0 + +/** LEDC_CH3_DUTY_REG register + * Initial duty cycle for channel 3 + */ +#define LEDC_CH3_DUTY_REG (DR_REG_LEDC_BASE + 0x44) +/** LEDC_DUTY_CH3 : R/W; bitpos: [24:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the Lpoint. + */ +#define LEDC_DUTY_CH3 0x01FFFFFFU +#define LEDC_DUTY_CH3_M (LEDC_DUTY_CH3_V << LEDC_DUTY_CH3_S) +#define LEDC_DUTY_CH3_V 0x01FFFFFFU +#define LEDC_DUTY_CH3_S 0 + +/** LEDC_CH3_CONF1_REG register + * Configuration register 1 for channel 3 + */ +#define LEDC_CH3_CONF1_REG (DR_REG_LEDC_BASE + 0x48) +/** LEDC_DUTY_START_CH3 : R/W/SC; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH3_CONF1_REG will start to take effect when this + * bit is set to 1. + */ +#define LEDC_DUTY_START_CH3 (BIT(31)) +#define LEDC_DUTY_START_CH3_M (LEDC_DUTY_START_CH3_V << LEDC_DUTY_START_CH3_S) +#define LEDC_DUTY_START_CH3_V 0x00000001U +#define LEDC_DUTY_START_CH3_S 31 + +/** LEDC_CH3_DUTY_R_REG register + * Current duty cycle for channel 3 + */ +#define LEDC_CH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x4c) +/** LEDC_DUTY_CH3_R : RO; bitpos: [24:0]; default: 0; + * This register stores the current duty of output signal on channel 3. + */ +#define LEDC_DUTY_CH3_R 0x01FFFFFFU +#define LEDC_DUTY_CH3_R_M (LEDC_DUTY_CH3_R_V << LEDC_DUTY_CH3_R_S) +#define LEDC_DUTY_CH3_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH3_R_S 0 + +/** LEDC_CH4_CONF0_REG register + * Configuration register 0 for channel 4 + */ +#define LEDC_CH4_CONF0_REG (DR_REG_LEDC_BASE + 0x50) +/** LEDC_TIMER_SEL_CH4 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 4. + * + * 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3 + */ +#define LEDC_TIMER_SEL_CH4 0x00000003U +#define LEDC_TIMER_SEL_CH4_M (LEDC_TIMER_SEL_CH4_V << LEDC_TIMER_SEL_CH4_S) +#define LEDC_TIMER_SEL_CH4_V 0x00000003U +#define LEDC_TIMER_SEL_CH4_S 0 +/** LEDC_SIG_OUT_EN_CH4 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 4. + */ +#define LEDC_SIG_OUT_EN_CH4 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH4_M (LEDC_SIG_OUT_EN_CH4_V << LEDC_SIG_OUT_EN_CH4_S) +#define LEDC_SIG_OUT_EN_CH4_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH4_S 2 +/** LEDC_IDLE_LV_CH4 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 4 is inactive (when + * LEDC_SIG_OUT_EN_CH4 is 0). + */ +#define LEDC_IDLE_LV_CH4 (BIT(3)) +#define LEDC_IDLE_LV_CH4_M (LEDC_IDLE_LV_CH4_V << LEDC_IDLE_LV_CH4_S) +#define LEDC_IDLE_LV_CH4_V 0x00000001U +#define LEDC_IDLE_LV_CH4_S 3 +/** LEDC_PARA_UP_CH4 : WT; bitpos: [4]; default: 0; + * This bit is used to update LEDC_HPOINT_CH4, LEDC_DUTY_START_CH4, + * LEDC_SIG_OUT_EN_CH4, LEDC_TIMER_SEL_CH4, LEDC_DUTY_NUM_CH4, LEDC_DUTY_CYCLE_CH4, + * LEDC_DUTY_SCALE_CH4, LEDC_DUTY_INC_CH4, and LEDC_OVF_CNT_EN_CH4 fields for channel + * 4, and will be automatically cleared by hardware. + */ +#define LEDC_PARA_UP_CH4 (BIT(4)) +#define LEDC_PARA_UP_CH4_M (LEDC_PARA_UP_CH4_V << LEDC_PARA_UP_CH4_S) +#define LEDC_PARA_UP_CH4_V 0x00000001U +#define LEDC_PARA_UP_CH4_S 4 +/** LEDC_OVF_NUM_CH4 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH4_INT interrupt will be triggered when channel 4 overflows for + * (LEDC_OVF_NUM_CH4 + 1) times. + */ +#define LEDC_OVF_NUM_CH4 0x000003FFU +#define LEDC_OVF_NUM_CH4_M (LEDC_OVF_NUM_CH4_V << LEDC_OVF_NUM_CH4_S) +#define LEDC_OVF_NUM_CH4_V 0x000003FFU +#define LEDC_OVF_NUM_CH4_S 5 +/** LEDC_OVF_CNT_EN_CH4 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 4. + */ +#define LEDC_OVF_CNT_EN_CH4 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH4_M (LEDC_OVF_CNT_EN_CH4_V << LEDC_OVF_CNT_EN_CH4_S) +#define LEDC_OVF_CNT_EN_CH4_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH4_S 15 +/** LEDC_OVF_CNT_RESET_CH4 : WT; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 4. + */ +#define LEDC_OVF_CNT_RESET_CH4 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH4_M (LEDC_OVF_CNT_RESET_CH4_V << LEDC_OVF_CNT_RESET_CH4_S) +#define LEDC_OVF_CNT_RESET_CH4_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH4_S 16 + +/** LEDC_CH4_HPOINT_REG register + * High point register for channel 4 + */ +#define LEDC_CH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x54) +/** LEDC_HPOINT_CH4 : R/W; bitpos: [19:0]; default: 0; + * The output value changes to high when the selected timers has reached the value + * specified by this register. + */ +#define LEDC_HPOINT_CH4 0x000FFFFFU +#define LEDC_HPOINT_CH4_M (LEDC_HPOINT_CH4_V << LEDC_HPOINT_CH4_S) +#define LEDC_HPOINT_CH4_V 0x000FFFFFU +#define LEDC_HPOINT_CH4_S 0 + +/** LEDC_CH4_DUTY_REG register + * Initial duty cycle for channel 4 + */ +#define LEDC_CH4_DUTY_REG (DR_REG_LEDC_BASE + 0x58) +/** LEDC_DUTY_CH4 : R/W; bitpos: [24:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the Lpoint. + */ +#define LEDC_DUTY_CH4 0x01FFFFFFU +#define LEDC_DUTY_CH4_M (LEDC_DUTY_CH4_V << LEDC_DUTY_CH4_S) +#define LEDC_DUTY_CH4_V 0x01FFFFFFU +#define LEDC_DUTY_CH4_S 0 + +/** LEDC_CH4_CONF1_REG register + * Configuration register 1 for channel 4 + */ +#define LEDC_CH4_CONF1_REG (DR_REG_LEDC_BASE + 0x5c) +/** LEDC_DUTY_START_CH4 : R/W/SC; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH4_CONF1_REG will start to take effect when this + * bit is set to 1. + */ +#define LEDC_DUTY_START_CH4 (BIT(31)) +#define LEDC_DUTY_START_CH4_M (LEDC_DUTY_START_CH4_V << LEDC_DUTY_START_CH4_S) +#define LEDC_DUTY_START_CH4_V 0x00000001U +#define LEDC_DUTY_START_CH4_S 31 + +/** LEDC_CH4_DUTY_R_REG register + * Current duty cycle for channel 4 + */ +#define LEDC_CH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x60) +/** LEDC_DUTY_CH4_R : RO; bitpos: [24:0]; default: 0; + * This register stores the current duty of output signal on channel 4. + */ +#define LEDC_DUTY_CH4_R 0x01FFFFFFU +#define LEDC_DUTY_CH4_R_M (LEDC_DUTY_CH4_R_V << LEDC_DUTY_CH4_R_S) +#define LEDC_DUTY_CH4_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH4_R_S 0 + +/** LEDC_CH5_CONF0_REG register + * Configuration register 0 for channel 5 + */ +#define LEDC_CH5_CONF0_REG (DR_REG_LEDC_BASE + 0x64) +/** LEDC_TIMER_SEL_CH5 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 5. + * + * 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3 + */ +#define LEDC_TIMER_SEL_CH5 0x00000003U +#define LEDC_TIMER_SEL_CH5_M (LEDC_TIMER_SEL_CH5_V << LEDC_TIMER_SEL_CH5_S) +#define LEDC_TIMER_SEL_CH5_V 0x00000003U +#define LEDC_TIMER_SEL_CH5_S 0 +/** LEDC_SIG_OUT_EN_CH5 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 5. + */ +#define LEDC_SIG_OUT_EN_CH5 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH5_M (LEDC_SIG_OUT_EN_CH5_V << LEDC_SIG_OUT_EN_CH5_S) +#define LEDC_SIG_OUT_EN_CH5_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH5_S 2 +/** LEDC_IDLE_LV_CH5 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 5 is inactive (when + * LEDC_SIG_OUT_EN_CH5 is 0). + */ +#define LEDC_IDLE_LV_CH5 (BIT(3)) +#define LEDC_IDLE_LV_CH5_M (LEDC_IDLE_LV_CH5_V << LEDC_IDLE_LV_CH5_S) +#define LEDC_IDLE_LV_CH5_V 0x00000001U +#define LEDC_IDLE_LV_CH5_S 3 +/** LEDC_PARA_UP_CH5 : WT; bitpos: [4]; default: 0; + * This bit is used to update LEDC_HPOINT_CH5, LEDC_DUTY_START_CH5, + * LEDC_SIG_OUT_EN_CH5, LEDC_TIMER_SEL_CH5, LEDC_DUTY_NUM_CH5, LEDC_DUTY_CYCLE_CH5, + * LEDC_DUTY_SCALE_CH5, LEDC_DUTY_INC_CH5, and LEDC_OVF_CNT_EN_CH5 fields for channel + * 5, and will be automatically cleared by hardware. + */ +#define LEDC_PARA_UP_CH5 (BIT(4)) +#define LEDC_PARA_UP_CH5_M (LEDC_PARA_UP_CH5_V << LEDC_PARA_UP_CH5_S) +#define LEDC_PARA_UP_CH5_V 0x00000001U +#define LEDC_PARA_UP_CH5_S 4 +/** LEDC_OVF_NUM_CH5 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH5_INT interrupt will be triggered when channel 5 overflows for + * (LEDC_OVF_NUM_CH5 + 1) times. + */ +#define LEDC_OVF_NUM_CH5 0x000003FFU +#define LEDC_OVF_NUM_CH5_M (LEDC_OVF_NUM_CH5_V << LEDC_OVF_NUM_CH5_S) +#define LEDC_OVF_NUM_CH5_V 0x000003FFU +#define LEDC_OVF_NUM_CH5_S 5 +/** LEDC_OVF_CNT_EN_CH5 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 5. + */ +#define LEDC_OVF_CNT_EN_CH5 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH5_M (LEDC_OVF_CNT_EN_CH5_V << LEDC_OVF_CNT_EN_CH5_S) +#define LEDC_OVF_CNT_EN_CH5_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH5_S 15 +/** LEDC_OVF_CNT_RESET_CH5 : WT; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 5. + */ +#define LEDC_OVF_CNT_RESET_CH5 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH5_M (LEDC_OVF_CNT_RESET_CH5_V << LEDC_OVF_CNT_RESET_CH5_S) +#define LEDC_OVF_CNT_RESET_CH5_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH5_S 16 + +/** LEDC_CH5_HPOINT_REG register + * High point register for channel 5 + */ +#define LEDC_CH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x68) +/** LEDC_HPOINT_CH5 : R/W; bitpos: [19:0]; default: 0; + * The output value changes to high when the selected timers has reached the value + * specified by this register. + */ +#define LEDC_HPOINT_CH5 0x000FFFFFU +#define LEDC_HPOINT_CH5_M (LEDC_HPOINT_CH5_V << LEDC_HPOINT_CH5_S) +#define LEDC_HPOINT_CH5_V 0x000FFFFFU +#define LEDC_HPOINT_CH5_S 0 + +/** LEDC_CH5_DUTY_REG register + * Initial duty cycle for channel 5 + */ +#define LEDC_CH5_DUTY_REG (DR_REG_LEDC_BASE + 0x6c) +/** LEDC_DUTY_CH5 : R/W; bitpos: [24:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the Lpoint. + */ +#define LEDC_DUTY_CH5 0x01FFFFFFU +#define LEDC_DUTY_CH5_M (LEDC_DUTY_CH5_V << LEDC_DUTY_CH5_S) +#define LEDC_DUTY_CH5_V 0x01FFFFFFU +#define LEDC_DUTY_CH5_S 0 + +/** LEDC_CH5_CONF1_REG register + * Configuration register 1 for channel 5 + */ +#define LEDC_CH5_CONF1_REG (DR_REG_LEDC_BASE + 0x70) +/** LEDC_DUTY_START_CH5 : R/W/SC; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH5_CONF1_REG will start to take effect when this + * bit is set to 1. + */ +#define LEDC_DUTY_START_CH5 (BIT(31)) +#define LEDC_DUTY_START_CH5_M (LEDC_DUTY_START_CH5_V << LEDC_DUTY_START_CH5_S) +#define LEDC_DUTY_START_CH5_V 0x00000001U +#define LEDC_DUTY_START_CH5_S 31 + +/** LEDC_CH5_DUTY_R_REG register + * Current duty cycle for channel 5 + */ +#define LEDC_CH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x74) +/** LEDC_DUTY_CH5_R : RO; bitpos: [24:0]; default: 0; + * This register stores the current duty of output signal on channel 5. + */ +#define LEDC_DUTY_CH5_R 0x01FFFFFFU +#define LEDC_DUTY_CH5_R_M (LEDC_DUTY_CH5_R_V << LEDC_DUTY_CH5_R_S) +#define LEDC_DUTY_CH5_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH5_R_S 0 + +/** LEDC_TIMER0_CONF_REG register + * Timer 0 configuration + */ +#define LEDC_TIMER0_CONF_REG (DR_REG_LEDC_BASE + 0xa0) +/** LEDC_TIMER0_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * This register is used to control the range of the counter in timer 0. + */ +#define LEDC_TIMER0_DUTY_RES 0x0000001FU +#define LEDC_TIMER0_DUTY_RES_M (LEDC_TIMER0_DUTY_RES_V << LEDC_TIMER0_DUTY_RES_S) +#define LEDC_TIMER0_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER0_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER0 : R/W; bitpos: [22:5]; default: 0; + * This register is used to configure the divisor for the divider in timer 0. + * + * The least significant eight bits represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER0 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER0_M (LEDC_CLK_DIV_TIMER0_V << LEDC_CLK_DIV_TIMER0_S) +#define LEDC_CLK_DIV_TIMER0_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER0_S 5 +/** LEDC_TIMER0_PAUSE : R/W; bitpos: [23]; default: 0; + * This bit is used to suspend the counter in timer 0. + */ +#define LEDC_TIMER0_PAUSE (BIT(23)) +#define LEDC_TIMER0_PAUSE_M (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S) +#define LEDC_TIMER0_PAUSE_V 0x00000001U +#define LEDC_TIMER0_PAUSE_S 23 +/** LEDC_TIMER0_RST : R/W; bitpos: [24]; default: 1; + * This bit is used to reset timer 0. The counter will show 0 after reset. + */ +#define LEDC_TIMER0_RST (BIT(24)) +#define LEDC_TIMER0_RST_M (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S) +#define LEDC_TIMER0_RST_V 0x00000001U +#define LEDC_TIMER0_RST_S 24 +/** LEDC_TICK_SEL_TIMER0 : R/W; bitpos: [25]; default: 0; + * This bit is used to select clock for timer 0. When this bit is set to 1 + * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. + * + * 1'h0: SLOW_CLK 1'h1: REF_TICK + */ +#define LEDC_TICK_SEL_TIMER0 (BIT(25)) +#define LEDC_TICK_SEL_TIMER0_M (LEDC_TICK_SEL_TIMER0_V << LEDC_TICK_SEL_TIMER0_S) +#define LEDC_TICK_SEL_TIMER0_V 0x00000001U +#define LEDC_TICK_SEL_TIMER0_S 25 +/** LEDC_TIMER0_PARA_UP : WT; bitpos: [26]; default: 0; + * Set this bit to update LEDC_CLK_DIV_TIMER0 and LEDC_TIMER0_DUTY_RES. + */ +#define LEDC_TIMER0_PARA_UP (BIT(26)) +#define LEDC_TIMER0_PARA_UP_M (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S) +#define LEDC_TIMER0_PARA_UP_V 0x00000001U +#define LEDC_TIMER0_PARA_UP_S 26 + +/** LEDC_TIMER0_VALUE_REG register + * Timer 0 current counter value + */ +#define LEDC_TIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0xa4) +/** LEDC_TIMER0_CNT : RO; bitpos: [19:0]; default: 0; + * This register stores the current counter value of timer 0. + */ +#define LEDC_TIMER0_CNT 0x000FFFFFU +#define LEDC_TIMER0_CNT_M (LEDC_TIMER0_CNT_V << LEDC_TIMER0_CNT_S) +#define LEDC_TIMER0_CNT_V 0x000FFFFFU +#define LEDC_TIMER0_CNT_S 0 + +/** LEDC_TIMER1_CONF_REG register + * Timer 1 configuration + */ +#define LEDC_TIMER1_CONF_REG (DR_REG_LEDC_BASE + 0xa8) +/** LEDC_TIMER1_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * This register is used to control the range of the counter in timer 1. + */ +#define LEDC_TIMER1_DUTY_RES 0x0000001FU +#define LEDC_TIMER1_DUTY_RES_M (LEDC_TIMER1_DUTY_RES_V << LEDC_TIMER1_DUTY_RES_S) +#define LEDC_TIMER1_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER1_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER1 : R/W; bitpos: [22:5]; default: 0; + * This register is used to configure the divisor for the divider in timer 1. + * + * The least significant eight bits represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER1 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER1_M (LEDC_CLK_DIV_TIMER1_V << LEDC_CLK_DIV_TIMER1_S) +#define LEDC_CLK_DIV_TIMER1_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER1_S 5 +/** LEDC_TIMER1_PAUSE : R/W; bitpos: [23]; default: 0; + * This bit is used to suspend the counter in timer 1. + */ +#define LEDC_TIMER1_PAUSE (BIT(23)) +#define LEDC_TIMER1_PAUSE_M (LEDC_TIMER1_PAUSE_V << LEDC_TIMER1_PAUSE_S) +#define LEDC_TIMER1_PAUSE_V 0x00000001U +#define LEDC_TIMER1_PAUSE_S 23 +/** LEDC_TIMER1_RST : R/W; bitpos: [24]; default: 1; + * This bit is used to reset timer 1. The counter will show 0 after reset. + */ +#define LEDC_TIMER1_RST (BIT(24)) +#define LEDC_TIMER1_RST_M (LEDC_TIMER1_RST_V << LEDC_TIMER1_RST_S) +#define LEDC_TIMER1_RST_V 0x00000001U +#define LEDC_TIMER1_RST_S 24 +/** LEDC_TICK_SEL_TIMER1 : R/W; bitpos: [25]; default: 0; + * This bit is used to select clock for timer 1. When this bit is set to 1 + * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. + * + * 1'h0: SLOW_CLK 1'h1: REF_TICK + */ +#define LEDC_TICK_SEL_TIMER1 (BIT(25)) +#define LEDC_TICK_SEL_TIMER1_M (LEDC_TICK_SEL_TIMER1_V << LEDC_TICK_SEL_TIMER1_S) +#define LEDC_TICK_SEL_TIMER1_V 0x00000001U +#define LEDC_TICK_SEL_TIMER1_S 25 +/** LEDC_TIMER1_PARA_UP : WT; bitpos: [26]; default: 0; + * Set this bit to update LEDC_CLK_DIV_TIMER1 and LEDC_TIMER1_DUTY_RES. + */ +#define LEDC_TIMER1_PARA_UP (BIT(26)) +#define LEDC_TIMER1_PARA_UP_M (LEDC_TIMER1_PARA_UP_V << LEDC_TIMER1_PARA_UP_S) +#define LEDC_TIMER1_PARA_UP_V 0x00000001U +#define LEDC_TIMER1_PARA_UP_S 26 + +/** LEDC_TIMER1_VALUE_REG register + * Timer 1 current counter value + */ +#define LEDC_TIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0xac) +/** LEDC_TIMER1_CNT : RO; bitpos: [19:0]; default: 0; + * This register stores the current counter value of timer 1. + */ +#define LEDC_TIMER1_CNT 0x000FFFFFU +#define LEDC_TIMER1_CNT_M (LEDC_TIMER1_CNT_V << LEDC_TIMER1_CNT_S) +#define LEDC_TIMER1_CNT_V 0x000FFFFFU +#define LEDC_TIMER1_CNT_S 0 + +/** LEDC_TIMER2_CONF_REG register + * Timer 2 configuration + */ +#define LEDC_TIMER2_CONF_REG (DR_REG_LEDC_BASE + 0xb0) +/** LEDC_TIMER2_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * This register is used to control the range of the counter in timer 2. + */ +#define LEDC_TIMER2_DUTY_RES 0x0000001FU +#define LEDC_TIMER2_DUTY_RES_M (LEDC_TIMER2_DUTY_RES_V << LEDC_TIMER2_DUTY_RES_S) +#define LEDC_TIMER2_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER2_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER2 : R/W; bitpos: [22:5]; default: 0; + * This register is used to configure the divisor for the divider in timer 2. + * + * The least significant eight bits represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER2 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER2_M (LEDC_CLK_DIV_TIMER2_V << LEDC_CLK_DIV_TIMER2_S) +#define LEDC_CLK_DIV_TIMER2_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER2_S 5 +/** LEDC_TIMER2_PAUSE : R/W; bitpos: [23]; default: 0; + * This bit is used to suspend the counter in timer 2. + */ +#define LEDC_TIMER2_PAUSE (BIT(23)) +#define LEDC_TIMER2_PAUSE_M (LEDC_TIMER2_PAUSE_V << LEDC_TIMER2_PAUSE_S) +#define LEDC_TIMER2_PAUSE_V 0x00000001U +#define LEDC_TIMER2_PAUSE_S 23 +/** LEDC_TIMER2_RST : R/W; bitpos: [24]; default: 1; + * This bit is used to reset timer 2. The counter will show 0 after reset. + */ +#define LEDC_TIMER2_RST (BIT(24)) +#define LEDC_TIMER2_RST_M (LEDC_TIMER2_RST_V << LEDC_TIMER2_RST_S) +#define LEDC_TIMER2_RST_V 0x00000001U +#define LEDC_TIMER2_RST_S 24 +/** LEDC_TICK_SEL_TIMER2 : R/W; bitpos: [25]; default: 0; + * This bit is used to select clock for timer 2. When this bit is set to 1 + * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. + * + * 1'h0: SLOW_CLK 1'h1: REF_TICK + */ +#define LEDC_TICK_SEL_TIMER2 (BIT(25)) +#define LEDC_TICK_SEL_TIMER2_M (LEDC_TICK_SEL_TIMER2_V << LEDC_TICK_SEL_TIMER2_S) +#define LEDC_TICK_SEL_TIMER2_V 0x00000001U +#define LEDC_TICK_SEL_TIMER2_S 25 +/** LEDC_TIMER2_PARA_UP : WT; bitpos: [26]; default: 0; + * Set this bit to update LEDC_CLK_DIV_TIMER2 and LEDC_TIMER2_DUTY_RES. + */ +#define LEDC_TIMER2_PARA_UP (BIT(26)) +#define LEDC_TIMER2_PARA_UP_M (LEDC_TIMER2_PARA_UP_V << LEDC_TIMER2_PARA_UP_S) +#define LEDC_TIMER2_PARA_UP_V 0x00000001U +#define LEDC_TIMER2_PARA_UP_S 26 + +/** LEDC_TIMER2_VALUE_REG register + * Timer 2 current counter value + */ +#define LEDC_TIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0xb4) +/** LEDC_TIMER2_CNT : RO; bitpos: [19:0]; default: 0; + * This register stores the current counter value of timer 2. + */ +#define LEDC_TIMER2_CNT 0x000FFFFFU +#define LEDC_TIMER2_CNT_M (LEDC_TIMER2_CNT_V << LEDC_TIMER2_CNT_S) +#define LEDC_TIMER2_CNT_V 0x000FFFFFU +#define LEDC_TIMER2_CNT_S 0 + +/** LEDC_TIMER3_CONF_REG register + * Timer 3 configuration + */ +#define LEDC_TIMER3_CONF_REG (DR_REG_LEDC_BASE + 0xb8) +/** LEDC_TIMER3_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * This register is used to control the range of the counter in timer 3. + */ +#define LEDC_TIMER3_DUTY_RES 0x0000001FU +#define LEDC_TIMER3_DUTY_RES_M (LEDC_TIMER3_DUTY_RES_V << LEDC_TIMER3_DUTY_RES_S) +#define LEDC_TIMER3_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER3_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER3 : R/W; bitpos: [22:5]; default: 0; + * This register is used to configure the divisor for the divider in timer 3. + * + * The least significant eight bits represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER3 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER3_M (LEDC_CLK_DIV_TIMER3_V << LEDC_CLK_DIV_TIMER3_S) +#define LEDC_CLK_DIV_TIMER3_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER3_S 5 +/** LEDC_TIMER3_PAUSE : R/W; bitpos: [23]; default: 0; + * This bit is used to suspend the counter in timer 3. + */ +#define LEDC_TIMER3_PAUSE (BIT(23)) +#define LEDC_TIMER3_PAUSE_M (LEDC_TIMER3_PAUSE_V << LEDC_TIMER3_PAUSE_S) +#define LEDC_TIMER3_PAUSE_V 0x00000001U +#define LEDC_TIMER3_PAUSE_S 23 +/** LEDC_TIMER3_RST : R/W; bitpos: [24]; default: 1; + * This bit is used to reset timer 3. The counter will show 0 after reset. + */ +#define LEDC_TIMER3_RST (BIT(24)) +#define LEDC_TIMER3_RST_M (LEDC_TIMER3_RST_V << LEDC_TIMER3_RST_S) +#define LEDC_TIMER3_RST_V 0x00000001U +#define LEDC_TIMER3_RST_S 24 +/** LEDC_TICK_SEL_TIMER3 : R/W; bitpos: [25]; default: 0; + * This bit is used to select clock for timer 3. When this bit is set to 1 + * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. + * + * 1'h0: SLOW_CLK 1'h1: REF_TICK + */ +#define LEDC_TICK_SEL_TIMER3 (BIT(25)) +#define LEDC_TICK_SEL_TIMER3_M (LEDC_TICK_SEL_TIMER3_V << LEDC_TICK_SEL_TIMER3_S) +#define LEDC_TICK_SEL_TIMER3_V 0x00000001U +#define LEDC_TICK_SEL_TIMER3_S 25 +/** LEDC_TIMER3_PARA_UP : WT; bitpos: [26]; default: 0; + * Set this bit to update LEDC_CLK_DIV_TIMER3 and LEDC_TIMER3_DUTY_RES. + */ +#define LEDC_TIMER3_PARA_UP (BIT(26)) +#define LEDC_TIMER3_PARA_UP_M (LEDC_TIMER3_PARA_UP_V << LEDC_TIMER3_PARA_UP_S) +#define LEDC_TIMER3_PARA_UP_V 0x00000001U +#define LEDC_TIMER3_PARA_UP_S 26 + +/** LEDC_TIMER3_VALUE_REG register + * Timer 3 current counter value + */ +#define LEDC_TIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0xbc) +/** LEDC_TIMER3_CNT : RO; bitpos: [19:0]; default: 0; + * This register stores the current counter value of timer 3. + */ +#define LEDC_TIMER3_CNT 0x000FFFFFU +#define LEDC_TIMER3_CNT_M (LEDC_TIMER3_CNT_V << LEDC_TIMER3_CNT_S) +#define LEDC_TIMER3_CNT_V 0x000FFFFFU +#define LEDC_TIMER3_CNT_S 0 + +/** LEDC_INT_RAW_REG register + * Raw interrupt status + */ +#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0xc0) +/** LEDC_TIMER0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * Triggered when the timer0 has reached its maximum counter value. + */ +#define LEDC_TIMER0_OVF_INT_RAW (BIT(0)) +#define LEDC_TIMER0_OVF_INT_RAW_M (LEDC_TIMER0_OVF_INT_RAW_V << LEDC_TIMER0_OVF_INT_RAW_S) +#define LEDC_TIMER0_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_RAW_S 0 +/** LEDC_TIMER1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * Triggered when the timer1 has reached its maximum counter value. + */ +#define LEDC_TIMER1_OVF_INT_RAW (BIT(1)) +#define LEDC_TIMER1_OVF_INT_RAW_M (LEDC_TIMER1_OVF_INT_RAW_V << LEDC_TIMER1_OVF_INT_RAW_S) +#define LEDC_TIMER1_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_RAW_S 1 +/** LEDC_TIMER2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * Triggered when the timer2 has reached its maximum counter value. + */ +#define LEDC_TIMER2_OVF_INT_RAW (BIT(2)) +#define LEDC_TIMER2_OVF_INT_RAW_M (LEDC_TIMER2_OVF_INT_RAW_V << LEDC_TIMER2_OVF_INT_RAW_S) +#define LEDC_TIMER2_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_RAW_S 2 +/** LEDC_TIMER3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * Triggered when the timer3 has reached its maximum counter value. + */ +#define LEDC_TIMER3_OVF_INT_RAW (BIT(3)) +#define LEDC_TIMER3_OVF_INT_RAW_M (LEDC_TIMER3_OVF_INT_RAW_V << LEDC_TIMER3_OVF_INT_RAW_S) +#define LEDC_TIMER3_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_RAW_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * Interrupt raw bit for channel 0. Triggered when the gradual change of duty has + * finished. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_M (LEDC_DUTY_CHNG_END_CH0_INT_RAW_V << LEDC_DUTY_CHNG_END_CH0_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * Interrupt raw bit for channel 1. Triggered when the gradual change of duty has + * finished. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_M (LEDC_DUTY_CHNG_END_CH1_INT_RAW_V << LEDC_DUTY_CHNG_END_CH1_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * Interrupt raw bit for channel 2. Triggered when the gradual change of duty has + * finished. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_M (LEDC_DUTY_CHNG_END_CH2_INT_RAW_V << LEDC_DUTY_CHNG_END_CH2_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * Interrupt raw bit for channel 3. Triggered when the gradual change of duty has + * finished. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_M (LEDC_DUTY_CHNG_END_CH3_INT_RAW_V << LEDC_DUTY_CHNG_END_CH3_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * Interrupt raw bit for channel 4. Triggered when the gradual change of duty has + * finished. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_M (LEDC_DUTY_CHNG_END_CH4_INT_RAW_V << LEDC_DUTY_CHNG_END_CH4_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * Interrupt raw bit for channel 5. Triggered when the gradual change of duty has + * finished. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_M (LEDC_DUTY_CHNG_END_CH5_INT_RAW_V << LEDC_DUTY_CHNG_END_CH5_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_S 9 +/** LEDC_OVF_CNT_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH0. + */ +#define LEDC_OVF_CNT_CH0_INT_RAW (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_RAW_M (LEDC_OVF_CNT_CH0_INT_RAW_V << LEDC_OVF_CNT_CH0_INT_RAW_S) +#define LEDC_OVF_CNT_CH0_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_RAW_S 12 +/** LEDC_OVF_CNT_CH1_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH1. + */ +#define LEDC_OVF_CNT_CH1_INT_RAW (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_RAW_M (LEDC_OVF_CNT_CH1_INT_RAW_V << LEDC_OVF_CNT_CH1_INT_RAW_S) +#define LEDC_OVF_CNT_CH1_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_RAW_S 13 +/** LEDC_OVF_CNT_CH2_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH2. + */ +#define LEDC_OVF_CNT_CH2_INT_RAW (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_RAW_M (LEDC_OVF_CNT_CH2_INT_RAW_V << LEDC_OVF_CNT_CH2_INT_RAW_S) +#define LEDC_OVF_CNT_CH2_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_RAW_S 14 +/** LEDC_OVF_CNT_CH3_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH3. + */ +#define LEDC_OVF_CNT_CH3_INT_RAW (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_RAW_M (LEDC_OVF_CNT_CH3_INT_RAW_V << LEDC_OVF_CNT_CH3_INT_RAW_S) +#define LEDC_OVF_CNT_CH3_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_RAW_S 15 +/** LEDC_OVF_CNT_CH4_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH4. + */ +#define LEDC_OVF_CNT_CH4_INT_RAW (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_RAW_M (LEDC_OVF_CNT_CH4_INT_RAW_V << LEDC_OVF_CNT_CH4_INT_RAW_S) +#define LEDC_OVF_CNT_CH4_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_RAW_S 16 +/** LEDC_OVF_CNT_CH5_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH5. + */ +#define LEDC_OVF_CNT_CH5_INT_RAW (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_RAW_M (LEDC_OVF_CNT_CH5_INT_RAW_V << LEDC_OVF_CNT_CH5_INT_RAW_S) +#define LEDC_OVF_CNT_CH5_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_RAW_S 17 + +/** LEDC_INT_ST_REG register + * Masked interrupt status + */ +#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0xc4) +/** LEDC_TIMER0_OVF_INT_ST : RO; bitpos: [0]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when + * LEDC_TIMER0_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER0_OVF_INT_ST (BIT(0)) +#define LEDC_TIMER0_OVF_INT_ST_M (LEDC_TIMER0_OVF_INT_ST_V << LEDC_TIMER0_OVF_INT_ST_S) +#define LEDC_TIMER0_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_ST_S 0 +/** LEDC_TIMER1_OVF_INT_ST : RO; bitpos: [1]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when + * LEDC_TIMER1_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER1_OVF_INT_ST (BIT(1)) +#define LEDC_TIMER1_OVF_INT_ST_M (LEDC_TIMER1_OVF_INT_ST_V << LEDC_TIMER1_OVF_INT_ST_S) +#define LEDC_TIMER1_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_ST_S 1 +/** LEDC_TIMER2_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when + * LEDC_TIMER2_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER2_OVF_INT_ST (BIT(2)) +#define LEDC_TIMER2_OVF_INT_ST_M (LEDC_TIMER2_OVF_INT_ST_V << LEDC_TIMER2_OVF_INT_ST_S) +#define LEDC_TIMER2_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_ST_S 2 +/** LEDC_TIMER3_OVF_INT_ST : RO; bitpos: [3]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when + * LEDC_TIMER3_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER3_OVF_INT_ST (BIT(3)) +#define LEDC_TIMER3_OVF_INT_ST_M (LEDC_TIMER3_OVF_INT_ST_V << LEDC_TIMER3_OVF_INT_ST_S) +#define LEDC_TIMER3_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_ST_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT + * interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_ST (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_M (LEDC_DUTY_CHNG_END_CH0_INT_ST_V << LEDC_DUTY_CHNG_END_CH0_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT + * interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_ST (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_M (LEDC_DUTY_CHNG_END_CH1_INT_ST_V << LEDC_DUTY_CHNG_END_CH1_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_ST : RO; bitpos: [6]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT + * interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_ST (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_M (LEDC_DUTY_CHNG_END_CH2_INT_ST_V << LEDC_DUTY_CHNG_END_CH2_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_ST : RO; bitpos: [7]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT + * interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_ST (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_M (LEDC_DUTY_CHNG_END_CH3_INT_ST_V << LEDC_DUTY_CHNG_END_CH3_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_ST : RO; bitpos: [8]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT + * interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_ST (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_M (LEDC_DUTY_CHNG_END_CH4_INT_ST_V << LEDC_DUTY_CHNG_END_CH4_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_ST : RO; bitpos: [9]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT + * interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_ST (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_M (LEDC_DUTY_CHNG_END_CH5_INT_ST_V << LEDC_DUTY_CHNG_END_CH5_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_S 9 +/** LEDC_OVF_CNT_CH0_INT_ST : RO; bitpos: [12]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when + * LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH0_INT_ST (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_ST_M (LEDC_OVF_CNT_CH0_INT_ST_V << LEDC_OVF_CNT_CH0_INT_ST_S) +#define LEDC_OVF_CNT_CH0_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_ST_S 12 +/** LEDC_OVF_CNT_CH1_INT_ST : RO; bitpos: [13]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when + * LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH1_INT_ST (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_ST_M (LEDC_OVF_CNT_CH1_INT_ST_V << LEDC_OVF_CNT_CH1_INT_ST_S) +#define LEDC_OVF_CNT_CH1_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_ST_S 13 +/** LEDC_OVF_CNT_CH2_INT_ST : RO; bitpos: [14]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when + * LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH2_INT_ST (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_ST_M (LEDC_OVF_CNT_CH2_INT_ST_V << LEDC_OVF_CNT_CH2_INT_ST_S) +#define LEDC_OVF_CNT_CH2_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_ST_S 14 +/** LEDC_OVF_CNT_CH3_INT_ST : RO; bitpos: [15]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when + * LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH3_INT_ST (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_ST_M (LEDC_OVF_CNT_CH3_INT_ST_V << LEDC_OVF_CNT_CH3_INT_ST_S) +#define LEDC_OVF_CNT_CH3_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_ST_S 15 +/** LEDC_OVF_CNT_CH4_INT_ST : RO; bitpos: [16]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when + * LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH4_INT_ST (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_ST_M (LEDC_OVF_CNT_CH4_INT_ST_V << LEDC_OVF_CNT_CH4_INT_ST_S) +#define LEDC_OVF_CNT_CH4_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_ST_S 16 +/** LEDC_OVF_CNT_CH5_INT_ST : RO; bitpos: [17]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when + * LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH5_INT_ST (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_ST_M (LEDC_OVF_CNT_CH5_INT_ST_V << LEDC_OVF_CNT_CH5_INT_ST_S) +#define LEDC_OVF_CNT_CH5_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_ST_S 17 + +/** LEDC_INT_ENA_REG register + * Interrupt enable bits + */ +#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0xc8) +/** LEDC_TIMER0_OVF_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. + */ +#define LEDC_TIMER0_OVF_INT_ENA (BIT(0)) +#define LEDC_TIMER0_OVF_INT_ENA_M (LEDC_TIMER0_OVF_INT_ENA_V << LEDC_TIMER0_OVF_INT_ENA_S) +#define LEDC_TIMER0_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_ENA_S 0 +/** LEDC_TIMER1_OVF_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. + */ +#define LEDC_TIMER1_OVF_INT_ENA (BIT(1)) +#define LEDC_TIMER1_OVF_INT_ENA_M (LEDC_TIMER1_OVF_INT_ENA_V << LEDC_TIMER1_OVF_INT_ENA_S) +#define LEDC_TIMER1_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_ENA_S 1 +/** LEDC_TIMER2_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. + */ +#define LEDC_TIMER2_OVF_INT_ENA (BIT(2)) +#define LEDC_TIMER2_OVF_INT_ENA_M (LEDC_TIMER2_OVF_INT_ENA_V << LEDC_TIMER2_OVF_INT_ENA_S) +#define LEDC_TIMER2_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_ENA_S 2 +/** LEDC_TIMER3_OVF_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. + */ +#define LEDC_TIMER3_OVF_INT_ENA (BIT(3)) +#define LEDC_TIMER3_OVF_INT_ENA_M (LEDC_TIMER3_OVF_INT_ENA_V << LEDC_TIMER3_OVF_INT_ENA_S) +#define LEDC_TIMER3_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_ENA_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_M (LEDC_DUTY_CHNG_END_CH0_INT_ENA_V << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_M (LEDC_DUTY_CHNG_END_CH1_INT_ENA_V << LEDC_DUTY_CHNG_END_CH1_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_M (LEDC_DUTY_CHNG_END_CH2_INT_ENA_V << LEDC_DUTY_CHNG_END_CH2_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_M (LEDC_DUTY_CHNG_END_CH3_INT_ENA_V << LEDC_DUTY_CHNG_END_CH3_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_M (LEDC_DUTY_CHNG_END_CH4_INT_ENA_V << LEDC_DUTY_CHNG_END_CH4_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_M (LEDC_DUTY_CHNG_END_CH5_INT_ENA_V << LEDC_DUTY_CHNG_END_CH5_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_S 9 +/** LEDC_OVF_CNT_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. + */ +#define LEDC_OVF_CNT_CH0_INT_ENA (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_ENA_M (LEDC_OVF_CNT_CH0_INT_ENA_V << LEDC_OVF_CNT_CH0_INT_ENA_S) +#define LEDC_OVF_CNT_CH0_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_ENA_S 12 +/** LEDC_OVF_CNT_CH1_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. + */ +#define LEDC_OVF_CNT_CH1_INT_ENA (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_ENA_M (LEDC_OVF_CNT_CH1_INT_ENA_V << LEDC_OVF_CNT_CH1_INT_ENA_S) +#define LEDC_OVF_CNT_CH1_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_ENA_S 13 +/** LEDC_OVF_CNT_CH2_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. + */ +#define LEDC_OVF_CNT_CH2_INT_ENA (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_ENA_M (LEDC_OVF_CNT_CH2_INT_ENA_V << LEDC_OVF_CNT_CH2_INT_ENA_S) +#define LEDC_OVF_CNT_CH2_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_ENA_S 14 +/** LEDC_OVF_CNT_CH3_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. + */ +#define LEDC_OVF_CNT_CH3_INT_ENA (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_ENA_M (LEDC_OVF_CNT_CH3_INT_ENA_V << LEDC_OVF_CNT_CH3_INT_ENA_S) +#define LEDC_OVF_CNT_CH3_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_ENA_S 15 +/** LEDC_OVF_CNT_CH4_INT_ENA : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. + */ +#define LEDC_OVF_CNT_CH4_INT_ENA (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_ENA_M (LEDC_OVF_CNT_CH4_INT_ENA_V << LEDC_OVF_CNT_CH4_INT_ENA_S) +#define LEDC_OVF_CNT_CH4_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_ENA_S 16 +/** LEDC_OVF_CNT_CH5_INT_ENA : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. + */ +#define LEDC_OVF_CNT_CH5_INT_ENA (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_ENA_M (LEDC_OVF_CNT_CH5_INT_ENA_V << LEDC_OVF_CNT_CH5_INT_ENA_S) +#define LEDC_OVF_CNT_CH5_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_ENA_S 17 + +/** LEDC_INT_CLR_REG register + * Interrupt clear bits + */ +#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0xcc) +/** LEDC_TIMER0_OVF_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. + */ +#define LEDC_TIMER0_OVF_INT_CLR (BIT(0)) +#define LEDC_TIMER0_OVF_INT_CLR_M (LEDC_TIMER0_OVF_INT_CLR_V << LEDC_TIMER0_OVF_INT_CLR_S) +#define LEDC_TIMER0_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_CLR_S 0 +/** LEDC_TIMER1_OVF_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. + */ +#define LEDC_TIMER1_OVF_INT_CLR (BIT(1)) +#define LEDC_TIMER1_OVF_INT_CLR_M (LEDC_TIMER1_OVF_INT_CLR_V << LEDC_TIMER1_OVF_INT_CLR_S) +#define LEDC_TIMER1_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_CLR_S 1 +/** LEDC_TIMER2_OVF_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. + */ +#define LEDC_TIMER2_OVF_INT_CLR (BIT(2)) +#define LEDC_TIMER2_OVF_INT_CLR_M (LEDC_TIMER2_OVF_INT_CLR_V << LEDC_TIMER2_OVF_INT_CLR_S) +#define LEDC_TIMER2_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_CLR_S 2 +/** LEDC_TIMER3_OVF_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. + */ +#define LEDC_TIMER3_OVF_INT_CLR (BIT(3)) +#define LEDC_TIMER3_OVF_INT_CLR_M (LEDC_TIMER3_OVF_INT_CLR_V << LEDC_TIMER3_OVF_INT_CLR_S) +#define LEDC_TIMER3_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_CLR_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_M (LEDC_DUTY_CHNG_END_CH0_INT_CLR_V << LEDC_DUTY_CHNG_END_CH0_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_M (LEDC_DUTY_CHNG_END_CH1_INT_CLR_V << LEDC_DUTY_CHNG_END_CH1_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_M (LEDC_DUTY_CHNG_END_CH2_INT_CLR_V << LEDC_DUTY_CHNG_END_CH2_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_M (LEDC_DUTY_CHNG_END_CH3_INT_CLR_V << LEDC_DUTY_CHNG_END_CH3_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_M (LEDC_DUTY_CHNG_END_CH4_INT_CLR_V << LEDC_DUTY_CHNG_END_CH4_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_M (LEDC_DUTY_CHNG_END_CH5_INT_CLR_V << LEDC_DUTY_CHNG_END_CH5_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_S 9 +/** LEDC_OVF_CNT_CH0_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. + */ +#define LEDC_OVF_CNT_CH0_INT_CLR (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_CLR_M (LEDC_OVF_CNT_CH0_INT_CLR_V << LEDC_OVF_CNT_CH0_INT_CLR_S) +#define LEDC_OVF_CNT_CH0_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_CLR_S 12 +/** LEDC_OVF_CNT_CH1_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. + */ +#define LEDC_OVF_CNT_CH1_INT_CLR (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_CLR_M (LEDC_OVF_CNT_CH1_INT_CLR_V << LEDC_OVF_CNT_CH1_INT_CLR_S) +#define LEDC_OVF_CNT_CH1_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_CLR_S 13 +/** LEDC_OVF_CNT_CH2_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. + */ +#define LEDC_OVF_CNT_CH2_INT_CLR (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_CLR_M (LEDC_OVF_CNT_CH2_INT_CLR_V << LEDC_OVF_CNT_CH2_INT_CLR_S) +#define LEDC_OVF_CNT_CH2_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_CLR_S 14 +/** LEDC_OVF_CNT_CH3_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. + */ +#define LEDC_OVF_CNT_CH3_INT_CLR (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_CLR_M (LEDC_OVF_CNT_CH3_INT_CLR_V << LEDC_OVF_CNT_CH3_INT_CLR_S) +#define LEDC_OVF_CNT_CH3_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_CLR_S 15 +/** LEDC_OVF_CNT_CH4_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. + */ +#define LEDC_OVF_CNT_CH4_INT_CLR (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_CLR_M (LEDC_OVF_CNT_CH4_INT_CLR_V << LEDC_OVF_CNT_CH4_INT_CLR_S) +#define LEDC_OVF_CNT_CH4_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_CLR_S 16 +/** LEDC_OVF_CNT_CH5_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. + */ +#define LEDC_OVF_CNT_CH5_INT_CLR (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_CLR_M (LEDC_OVF_CNT_CH5_INT_CLR_V << LEDC_OVF_CNT_CH5_INT_CLR_S) +#define LEDC_OVF_CNT_CH5_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_CLR_S 17 + +/** LEDC_CH0_GAMMA_WR_REG register + * Ledc ch0 gamma ram write register. + */ +#define LEDC_CH0_GAMMA_WR_REG (DR_REG_LEDC_BASE + 0x100) +/** LEDC_CH0_GAMMA_DUTY_INC : R/W; bitpos: [0]; default: 0; + * Ledc ch0 gamma duty inc of current ram write address.This register is used to + * increase or decrease the duty of output signal on channel 0. + * + * 1: Increase 0: Decrease. + */ +#define LEDC_CH0_GAMMA_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_DUTY_INC_M (LEDC_CH0_GAMMA_DUTY_INC_V << LEDC_CH0_GAMMA_DUTY_INC_S) +#define LEDC_CH0_GAMMA_DUTY_INC_V 0x00000001U +#define LEDC_CH0_GAMMA_DUTY_INC_S 0 +/** LEDC_CH0_GAMMA_DUTY_CYCLE : R/W; bitpos: [10:1]; default: 0; + * Ledc ch0 gamma duty cycle of current ram write address.The duty will change every + * LEDC_CH0_GAMMA_DUTY_CYCLE on channel 0. + */ +#define LEDC_CH0_GAMMA_DUTY_CYCLE 0x000003FFU +#define LEDC_CH0_GAMMA_DUTY_CYCLE_M (LEDC_CH0_GAMMA_DUTY_CYCLE_V << LEDC_CH0_GAMMA_DUTY_CYCLE_S) +#define LEDC_CH0_GAMMA_DUTY_CYCLE_V 0x000003FFU +#define LEDC_CH0_GAMMA_DUTY_CYCLE_S 1 +/** LEDC_CH0_GAMMA_SCALE : R/W; bitpos: [20:11]; default: 0; + * Ledc ch0 gamma scale of current ram write address.This register is used to + * configure the changing step scale of duty on channel 0. + */ +#define LEDC_CH0_GAMMA_SCALE 0x000003FFU +#define LEDC_CH0_GAMMA_SCALE_M (LEDC_CH0_GAMMA_SCALE_V << LEDC_CH0_GAMMA_SCALE_S) +#define LEDC_CH0_GAMMA_SCALE_V 0x000003FFU +#define LEDC_CH0_GAMMA_SCALE_S 11 +/** LEDC_CH0_GAMMA_DUTY_NUM : R/W; bitpos: [30:21]; default: 0; + * Ledc ch0 gamma duty num of current ram write address.This register is used to + * control the number of times the duty cycle will be changed. + */ +#define LEDC_CH0_GAMMA_DUTY_NUM 0x000003FFU +#define LEDC_CH0_GAMMA_DUTY_NUM_M (LEDC_CH0_GAMMA_DUTY_NUM_V << LEDC_CH0_GAMMA_DUTY_NUM_S) +#define LEDC_CH0_GAMMA_DUTY_NUM_V 0x000003FFU +#define LEDC_CH0_GAMMA_DUTY_NUM_S 21 + +/** LEDC_CH0_GAMMA_WR_ADDR_REG register + * Ledc ch0 gamma ram write address register. + */ +#define LEDC_CH0_GAMMA_WR_ADDR_REG (DR_REG_LEDC_BASE + 0x104) +/** LEDC_CH0_GAMMA_WR_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch0 gamma ram write address. + */ +#define LEDC_CH0_GAMMA_WR_ADDR 0x0000000FU +#define LEDC_CH0_GAMMA_WR_ADDR_M (LEDC_CH0_GAMMA_WR_ADDR_V << LEDC_CH0_GAMMA_WR_ADDR_S) +#define LEDC_CH0_GAMMA_WR_ADDR_V 0x0000000FU +#define LEDC_CH0_GAMMA_WR_ADDR_S 0 + +/** LEDC_CH0_GAMMA_RD_ADDR_REG register + * Ledc ch0 gamma ram read address register. + */ +#define LEDC_CH0_GAMMA_RD_ADDR_REG (DR_REG_LEDC_BASE + 0x108) +/** LEDC_CH0_GAMMA_RD_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch0 gamma ram read address. + */ +#define LEDC_CH0_GAMMA_RD_ADDR 0x0000000FU +#define LEDC_CH0_GAMMA_RD_ADDR_M (LEDC_CH0_GAMMA_RD_ADDR_V << LEDC_CH0_GAMMA_RD_ADDR_S) +#define LEDC_CH0_GAMMA_RD_ADDR_V 0x0000000FU +#define LEDC_CH0_GAMMA_RD_ADDR_S 0 + +/** LEDC_CH0_GAMMA_RD_DATA_REG register + * Ledc ch0 gamma ram read data register. + */ +#define LEDC_CH0_GAMMA_RD_DATA_REG (DR_REG_LEDC_BASE + 0x10c) +/** LEDC_CH0_GAMMA_RD_DATA : RO; bitpos: [30:0]; default: 0; + * Ledc ch0 gamma ram read data. + */ +#define LEDC_CH0_GAMMA_RD_DATA 0x7FFFFFFFU +#define LEDC_CH0_GAMMA_RD_DATA_M (LEDC_CH0_GAMMA_RD_DATA_V << LEDC_CH0_GAMMA_RD_DATA_S) +#define LEDC_CH0_GAMMA_RD_DATA_V 0x7FFFFFFFU +#define LEDC_CH0_GAMMA_RD_DATA_S 0 + +/** LEDC_CH1_GAMMA_WR_REG register + * Ledc ch1 gamma ram write register. + */ +#define LEDC_CH1_GAMMA_WR_REG (DR_REG_LEDC_BASE + 0x110) +/** LEDC_CH1_GAMMA_DUTY_INC : R/W; bitpos: [0]; default: 0; + * Ledc ch1 gamma duty inc of current ram write address.This register is used to + * increase or decrease the duty of output signal on channel 1. + * + * 1: Increase 0: Decrease. + */ +#define LEDC_CH1_GAMMA_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_DUTY_INC_M (LEDC_CH1_GAMMA_DUTY_INC_V << LEDC_CH1_GAMMA_DUTY_INC_S) +#define LEDC_CH1_GAMMA_DUTY_INC_V 0x00000001U +#define LEDC_CH1_GAMMA_DUTY_INC_S 0 +/** LEDC_CH1_GAMMA_DUTY_CYCLE : R/W; bitpos: [10:1]; default: 0; + * Ledc ch1 gamma duty cycle of current ram write address.The duty will change every + * LEDC_CH1_GAMMA_DUTY_CYCLE on channel 1. + */ +#define LEDC_CH1_GAMMA_DUTY_CYCLE 0x000003FFU +#define LEDC_CH1_GAMMA_DUTY_CYCLE_M (LEDC_CH1_GAMMA_DUTY_CYCLE_V << LEDC_CH1_GAMMA_DUTY_CYCLE_S) +#define LEDC_CH1_GAMMA_DUTY_CYCLE_V 0x000003FFU +#define LEDC_CH1_GAMMA_DUTY_CYCLE_S 1 +/** LEDC_CH1_GAMMA_SCALE : R/W; bitpos: [20:11]; default: 0; + * Ledc ch1 gamma scale of current ram write address.This register is used to + * configure the changing step scale of duty on channel 1. + */ +#define LEDC_CH1_GAMMA_SCALE 0x000003FFU +#define LEDC_CH1_GAMMA_SCALE_M (LEDC_CH1_GAMMA_SCALE_V << LEDC_CH1_GAMMA_SCALE_S) +#define LEDC_CH1_GAMMA_SCALE_V 0x000003FFU +#define LEDC_CH1_GAMMA_SCALE_S 11 +/** LEDC_CH1_GAMMA_DUTY_NUM : R/W; bitpos: [30:21]; default: 0; + * Ledc ch1 gamma duty num of current ram write address.This register is used to + * control the number of times the duty cycle will be changed. + */ +#define LEDC_CH1_GAMMA_DUTY_NUM 0x000003FFU +#define LEDC_CH1_GAMMA_DUTY_NUM_M (LEDC_CH1_GAMMA_DUTY_NUM_V << LEDC_CH1_GAMMA_DUTY_NUM_S) +#define LEDC_CH1_GAMMA_DUTY_NUM_V 0x000003FFU +#define LEDC_CH1_GAMMA_DUTY_NUM_S 21 + +/** LEDC_CH1_GAMMA_WR_ADDR_REG register + * Ledc ch1 gamma ram write address register. + */ +#define LEDC_CH1_GAMMA_WR_ADDR_REG (DR_REG_LEDC_BASE + 0x114) +/** LEDC_CH1_GAMMA_WR_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch1 gamma ram write address. + */ +#define LEDC_CH1_GAMMA_WR_ADDR 0x0000000FU +#define LEDC_CH1_GAMMA_WR_ADDR_M (LEDC_CH1_GAMMA_WR_ADDR_V << LEDC_CH1_GAMMA_WR_ADDR_S) +#define LEDC_CH1_GAMMA_WR_ADDR_V 0x0000000FU +#define LEDC_CH1_GAMMA_WR_ADDR_S 0 + +/** LEDC_CH1_GAMMA_RD_ADDR_REG register + * Ledc ch1 gamma ram read address register. + */ +#define LEDC_CH1_GAMMA_RD_ADDR_REG (DR_REG_LEDC_BASE + 0x118) +/** LEDC_CH1_GAMMA_RD_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch1 gamma ram read address. + */ +#define LEDC_CH1_GAMMA_RD_ADDR 0x0000000FU +#define LEDC_CH1_GAMMA_RD_ADDR_M (LEDC_CH1_GAMMA_RD_ADDR_V << LEDC_CH1_GAMMA_RD_ADDR_S) +#define LEDC_CH1_GAMMA_RD_ADDR_V 0x0000000FU +#define LEDC_CH1_GAMMA_RD_ADDR_S 0 + +/** LEDC_CH1_GAMMA_RD_DATA_REG register + * Ledc ch1 gamma ram read data register. + */ +#define LEDC_CH1_GAMMA_RD_DATA_REG (DR_REG_LEDC_BASE + 0x11c) +/** LEDC_CH1_GAMMA_RD_DATA : RO; bitpos: [30:0]; default: 0; + * Ledc ch1 gamma ram read data. + */ +#define LEDC_CH1_GAMMA_RD_DATA 0x7FFFFFFFU +#define LEDC_CH1_GAMMA_RD_DATA_M (LEDC_CH1_GAMMA_RD_DATA_V << LEDC_CH1_GAMMA_RD_DATA_S) +#define LEDC_CH1_GAMMA_RD_DATA_V 0x7FFFFFFFU +#define LEDC_CH1_GAMMA_RD_DATA_S 0 + +/** LEDC_CH2_GAMMA_WR_REG register + * Ledc ch2 gamma ram write register. + */ +#define LEDC_CH2_GAMMA_WR_REG (DR_REG_LEDC_BASE + 0x120) +/** LEDC_CH2_GAMMA_DUTY_INC : R/W; bitpos: [0]; default: 0; + * Ledc ch2 gamma duty inc of current ram write address.This register is used to + * increase or decrease the duty of output signal on channel 2. + * + * 1: Increase 0: Decrease. + */ +#define LEDC_CH2_GAMMA_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_DUTY_INC_M (LEDC_CH2_GAMMA_DUTY_INC_V << LEDC_CH2_GAMMA_DUTY_INC_S) +#define LEDC_CH2_GAMMA_DUTY_INC_V 0x00000001U +#define LEDC_CH2_GAMMA_DUTY_INC_S 0 +/** LEDC_CH2_GAMMA_DUTY_CYCLE : R/W; bitpos: [10:1]; default: 0; + * Ledc ch2 gamma duty cycle of current ram write address.The duty will change every + * LEDC_CH2_GAMMA_DUTY_CYCLE on channel 2. + */ +#define LEDC_CH2_GAMMA_DUTY_CYCLE 0x000003FFU +#define LEDC_CH2_GAMMA_DUTY_CYCLE_M (LEDC_CH2_GAMMA_DUTY_CYCLE_V << LEDC_CH2_GAMMA_DUTY_CYCLE_S) +#define LEDC_CH2_GAMMA_DUTY_CYCLE_V 0x000003FFU +#define LEDC_CH2_GAMMA_DUTY_CYCLE_S 1 +/** LEDC_CH2_GAMMA_SCALE : R/W; bitpos: [20:11]; default: 0; + * Ledc ch2 gamma scale of current ram write address.This register is used to + * configure the changing step scale of duty on channel 2. + */ +#define LEDC_CH2_GAMMA_SCALE 0x000003FFU +#define LEDC_CH2_GAMMA_SCALE_M (LEDC_CH2_GAMMA_SCALE_V << LEDC_CH2_GAMMA_SCALE_S) +#define LEDC_CH2_GAMMA_SCALE_V 0x000003FFU +#define LEDC_CH2_GAMMA_SCALE_S 11 +/** LEDC_CH2_GAMMA_DUTY_NUM : R/W; bitpos: [30:21]; default: 0; + * Ledc ch2 gamma duty num of current ram write address.This register is used to + * control the number of times the duty cycle will be changed. + */ +#define LEDC_CH2_GAMMA_DUTY_NUM 0x000003FFU +#define LEDC_CH2_GAMMA_DUTY_NUM_M (LEDC_CH2_GAMMA_DUTY_NUM_V << LEDC_CH2_GAMMA_DUTY_NUM_S) +#define LEDC_CH2_GAMMA_DUTY_NUM_V 0x000003FFU +#define LEDC_CH2_GAMMA_DUTY_NUM_S 21 + +/** LEDC_CH2_GAMMA_WR_ADDR_REG register + * Ledc ch2 gamma ram write address register. + */ +#define LEDC_CH2_GAMMA_WR_ADDR_REG (DR_REG_LEDC_BASE + 0x124) +/** LEDC_CH2_GAMMA_WR_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch2 gamma ram write address. + */ +#define LEDC_CH2_GAMMA_WR_ADDR 0x0000000FU +#define LEDC_CH2_GAMMA_WR_ADDR_M (LEDC_CH2_GAMMA_WR_ADDR_V << LEDC_CH2_GAMMA_WR_ADDR_S) +#define LEDC_CH2_GAMMA_WR_ADDR_V 0x0000000FU +#define LEDC_CH2_GAMMA_WR_ADDR_S 0 + +/** LEDC_CH2_GAMMA_RD_ADDR_REG register + * Ledc ch2 gamma ram read address register. + */ +#define LEDC_CH2_GAMMA_RD_ADDR_REG (DR_REG_LEDC_BASE + 0x128) +/** LEDC_CH2_GAMMA_RD_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch2 gamma ram read address. + */ +#define LEDC_CH2_GAMMA_RD_ADDR 0x0000000FU +#define LEDC_CH2_GAMMA_RD_ADDR_M (LEDC_CH2_GAMMA_RD_ADDR_V << LEDC_CH2_GAMMA_RD_ADDR_S) +#define LEDC_CH2_GAMMA_RD_ADDR_V 0x0000000FU +#define LEDC_CH2_GAMMA_RD_ADDR_S 0 + +/** LEDC_CH2_GAMMA_RD_DATA_REG register + * Ledc ch2 gamma ram read data register. + */ +#define LEDC_CH2_GAMMA_RD_DATA_REG (DR_REG_LEDC_BASE + 0x12c) +/** LEDC_CH2_GAMMA_RD_DATA : RO; bitpos: [30:0]; default: 0; + * Ledc ch2 gamma ram read data. + */ +#define LEDC_CH2_GAMMA_RD_DATA 0x7FFFFFFFU +#define LEDC_CH2_GAMMA_RD_DATA_M (LEDC_CH2_GAMMA_RD_DATA_V << LEDC_CH2_GAMMA_RD_DATA_S) +#define LEDC_CH2_GAMMA_RD_DATA_V 0x7FFFFFFFU +#define LEDC_CH2_GAMMA_RD_DATA_S 0 + +/** LEDC_CH3_GAMMA_WR_REG register + * Ledc ch3 gamma ram write register. + */ +#define LEDC_CH3_GAMMA_WR_REG (DR_REG_LEDC_BASE + 0x130) +/** LEDC_CH3_GAMMA_DUTY_INC : R/W; bitpos: [0]; default: 0; + * Ledc ch3 gamma duty inc of current ram write address.This register is used to + * increase or decrease the duty of output signal on channel 3. + * + * 1: Increase 0: Decrease. + */ +#define LEDC_CH3_GAMMA_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_DUTY_INC_M (LEDC_CH3_GAMMA_DUTY_INC_V << LEDC_CH3_GAMMA_DUTY_INC_S) +#define LEDC_CH3_GAMMA_DUTY_INC_V 0x00000001U +#define LEDC_CH3_GAMMA_DUTY_INC_S 0 +/** LEDC_CH3_GAMMA_DUTY_CYCLE : R/W; bitpos: [10:1]; default: 0; + * Ledc ch3 gamma duty cycle of current ram write address.The duty will change every + * LEDC_CH3_GAMMA_DUTY_CYCLE on channel 3. + */ +#define LEDC_CH3_GAMMA_DUTY_CYCLE 0x000003FFU +#define LEDC_CH3_GAMMA_DUTY_CYCLE_M (LEDC_CH3_GAMMA_DUTY_CYCLE_V << LEDC_CH3_GAMMA_DUTY_CYCLE_S) +#define LEDC_CH3_GAMMA_DUTY_CYCLE_V 0x000003FFU +#define LEDC_CH3_GAMMA_DUTY_CYCLE_S 1 +/** LEDC_CH3_GAMMA_SCALE : R/W; bitpos: [20:11]; default: 0; + * Ledc ch3 gamma scale of current ram write address.This register is used to + * configure the changing step scale of duty on channel 3. + */ +#define LEDC_CH3_GAMMA_SCALE 0x000003FFU +#define LEDC_CH3_GAMMA_SCALE_M (LEDC_CH3_GAMMA_SCALE_V << LEDC_CH3_GAMMA_SCALE_S) +#define LEDC_CH3_GAMMA_SCALE_V 0x000003FFU +#define LEDC_CH3_GAMMA_SCALE_S 11 +/** LEDC_CH3_GAMMA_DUTY_NUM : R/W; bitpos: [30:21]; default: 0; + * Ledc ch3 gamma duty num of current ram write address.This register is used to + * control the number of times the duty cycle will be changed. + */ +#define LEDC_CH3_GAMMA_DUTY_NUM 0x000003FFU +#define LEDC_CH3_GAMMA_DUTY_NUM_M (LEDC_CH3_GAMMA_DUTY_NUM_V << LEDC_CH3_GAMMA_DUTY_NUM_S) +#define LEDC_CH3_GAMMA_DUTY_NUM_V 0x000003FFU +#define LEDC_CH3_GAMMA_DUTY_NUM_S 21 + +/** LEDC_CH3_GAMMA_WR_ADDR_REG register + * Ledc ch3 gamma ram write address register. + */ +#define LEDC_CH3_GAMMA_WR_ADDR_REG (DR_REG_LEDC_BASE + 0x134) +/** LEDC_CH3_GAMMA_WR_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch3 gamma ram write address. + */ +#define LEDC_CH3_GAMMA_WR_ADDR 0x0000000FU +#define LEDC_CH3_GAMMA_WR_ADDR_M (LEDC_CH3_GAMMA_WR_ADDR_V << LEDC_CH3_GAMMA_WR_ADDR_S) +#define LEDC_CH3_GAMMA_WR_ADDR_V 0x0000000FU +#define LEDC_CH3_GAMMA_WR_ADDR_S 0 + +/** LEDC_CH3_GAMMA_RD_ADDR_REG register + * Ledc ch3 gamma ram read address register. + */ +#define LEDC_CH3_GAMMA_RD_ADDR_REG (DR_REG_LEDC_BASE + 0x138) +/** LEDC_CH3_GAMMA_RD_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch3 gamma ram read address. + */ +#define LEDC_CH3_GAMMA_RD_ADDR 0x0000000FU +#define LEDC_CH3_GAMMA_RD_ADDR_M (LEDC_CH3_GAMMA_RD_ADDR_V << LEDC_CH3_GAMMA_RD_ADDR_S) +#define LEDC_CH3_GAMMA_RD_ADDR_V 0x0000000FU +#define LEDC_CH3_GAMMA_RD_ADDR_S 0 + +/** LEDC_CH3_GAMMA_RD_DATA_REG register + * Ledc ch3 gamma ram read data register. + */ +#define LEDC_CH3_GAMMA_RD_DATA_REG (DR_REG_LEDC_BASE + 0x13c) +/** LEDC_CH3_GAMMA_RD_DATA : RO; bitpos: [30:0]; default: 0; + * Ledc ch3 gamma ram read data. + */ +#define LEDC_CH3_GAMMA_RD_DATA 0x7FFFFFFFU +#define LEDC_CH3_GAMMA_RD_DATA_M (LEDC_CH3_GAMMA_RD_DATA_V << LEDC_CH3_GAMMA_RD_DATA_S) +#define LEDC_CH3_GAMMA_RD_DATA_V 0x7FFFFFFFU +#define LEDC_CH3_GAMMA_RD_DATA_S 0 + +/** LEDC_CH4_GAMMA_WR_REG register + * Ledc ch4 gamma ram write register. + */ +#define LEDC_CH4_GAMMA_WR_REG (DR_REG_LEDC_BASE + 0x140) +/** LEDC_CH4_GAMMA_DUTY_INC : R/W; bitpos: [0]; default: 0; + * Ledc ch4 gamma duty inc of current ram write address.This register is used to + * increase or decrease the duty of output signal on channel 4. + * + * 1: Increase 0: Decrease. + */ +#define LEDC_CH4_GAMMA_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_DUTY_INC_M (LEDC_CH4_GAMMA_DUTY_INC_V << LEDC_CH4_GAMMA_DUTY_INC_S) +#define LEDC_CH4_GAMMA_DUTY_INC_V 0x00000001U +#define LEDC_CH4_GAMMA_DUTY_INC_S 0 +/** LEDC_CH4_GAMMA_DUTY_CYCLE : R/W; bitpos: [10:1]; default: 0; + * Ledc ch4 gamma duty cycle of current ram write address.The duty will change every + * LEDC_CH4_GAMMA_DUTY_CYCLE on channel 4. + */ +#define LEDC_CH4_GAMMA_DUTY_CYCLE 0x000003FFU +#define LEDC_CH4_GAMMA_DUTY_CYCLE_M (LEDC_CH4_GAMMA_DUTY_CYCLE_V << LEDC_CH4_GAMMA_DUTY_CYCLE_S) +#define LEDC_CH4_GAMMA_DUTY_CYCLE_V 0x000003FFU +#define LEDC_CH4_GAMMA_DUTY_CYCLE_S 1 +/** LEDC_CH4_GAMMA_SCALE : R/W; bitpos: [20:11]; default: 0; + * Ledc ch4 gamma scale of current ram write address.This register is used to + * configure the changing step scale of duty on channel 4. + */ +#define LEDC_CH4_GAMMA_SCALE 0x000003FFU +#define LEDC_CH4_GAMMA_SCALE_M (LEDC_CH4_GAMMA_SCALE_V << LEDC_CH4_GAMMA_SCALE_S) +#define LEDC_CH4_GAMMA_SCALE_V 0x000003FFU +#define LEDC_CH4_GAMMA_SCALE_S 11 +/** LEDC_CH4_GAMMA_DUTY_NUM : R/W; bitpos: [30:21]; default: 0; + * Ledc ch4 gamma duty num of current ram write address.This register is used to + * control the number of times the duty cycle will be changed. + */ +#define LEDC_CH4_GAMMA_DUTY_NUM 0x000003FFU +#define LEDC_CH4_GAMMA_DUTY_NUM_M (LEDC_CH4_GAMMA_DUTY_NUM_V << LEDC_CH4_GAMMA_DUTY_NUM_S) +#define LEDC_CH4_GAMMA_DUTY_NUM_V 0x000003FFU +#define LEDC_CH4_GAMMA_DUTY_NUM_S 21 + +/** LEDC_CH4_GAMMA_WR_ADDR_REG register + * Ledc ch4 gamma ram write address register. + */ +#define LEDC_CH4_GAMMA_WR_ADDR_REG (DR_REG_LEDC_BASE + 0x144) +/** LEDC_CH4_GAMMA_WR_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch4 gamma ram write address. + */ +#define LEDC_CH4_GAMMA_WR_ADDR 0x0000000FU +#define LEDC_CH4_GAMMA_WR_ADDR_M (LEDC_CH4_GAMMA_WR_ADDR_V << LEDC_CH4_GAMMA_WR_ADDR_S) +#define LEDC_CH4_GAMMA_WR_ADDR_V 0x0000000FU +#define LEDC_CH4_GAMMA_WR_ADDR_S 0 + +/** LEDC_CH4_GAMMA_RD_ADDR_REG register + * Ledc ch4 gamma ram read address register. + */ +#define LEDC_CH4_GAMMA_RD_ADDR_REG (DR_REG_LEDC_BASE + 0x148) +/** LEDC_CH4_GAMMA_RD_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch4 gamma ram read address. + */ +#define LEDC_CH4_GAMMA_RD_ADDR 0x0000000FU +#define LEDC_CH4_GAMMA_RD_ADDR_M (LEDC_CH4_GAMMA_RD_ADDR_V << LEDC_CH4_GAMMA_RD_ADDR_S) +#define LEDC_CH4_GAMMA_RD_ADDR_V 0x0000000FU +#define LEDC_CH4_GAMMA_RD_ADDR_S 0 + +/** LEDC_CH4_GAMMA_RD_DATA_REG register + * Ledc ch4 gamma ram read data register. + */ +#define LEDC_CH4_GAMMA_RD_DATA_REG (DR_REG_LEDC_BASE + 0x14c) +/** LEDC_CH4_GAMMA_RD_DATA : RO; bitpos: [30:0]; default: 0; + * Ledc ch4 gamma ram read data. + */ +#define LEDC_CH4_GAMMA_RD_DATA 0x7FFFFFFFU +#define LEDC_CH4_GAMMA_RD_DATA_M (LEDC_CH4_GAMMA_RD_DATA_V << LEDC_CH4_GAMMA_RD_DATA_S) +#define LEDC_CH4_GAMMA_RD_DATA_V 0x7FFFFFFFU +#define LEDC_CH4_GAMMA_RD_DATA_S 0 + +/** LEDC_CH5_GAMMA_WR_REG register + * Ledc ch5 gamma ram write register. + */ +#define LEDC_CH5_GAMMA_WR_REG (DR_REG_LEDC_BASE + 0x150) +/** LEDC_CH5_GAMMA_DUTY_INC : R/W; bitpos: [0]; default: 0; + * Ledc ch5 gamma duty inc of current ram write address.This register is used to + * increase or decrease the duty of output signal on channel 5. + * + * 1: Increase 0: Decrease. + */ +#define LEDC_CH5_GAMMA_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_DUTY_INC_M (LEDC_CH5_GAMMA_DUTY_INC_V << LEDC_CH5_GAMMA_DUTY_INC_S) +#define LEDC_CH5_GAMMA_DUTY_INC_V 0x00000001U +#define LEDC_CH5_GAMMA_DUTY_INC_S 0 +/** LEDC_CH5_GAMMA_DUTY_CYCLE : R/W; bitpos: [10:1]; default: 0; + * Ledc ch5 gamma duty cycle of current ram write address.The duty will change every + * LEDC_CH5_GAMMA_DUTY_CYCLE on channel 5. + */ +#define LEDC_CH5_GAMMA_DUTY_CYCLE 0x000003FFU +#define LEDC_CH5_GAMMA_DUTY_CYCLE_M (LEDC_CH5_GAMMA_DUTY_CYCLE_V << LEDC_CH5_GAMMA_DUTY_CYCLE_S) +#define LEDC_CH5_GAMMA_DUTY_CYCLE_V 0x000003FFU +#define LEDC_CH5_GAMMA_DUTY_CYCLE_S 1 +/** LEDC_CH5_GAMMA_SCALE : R/W; bitpos: [20:11]; default: 0; + * Ledc ch5 gamma scale of current ram write address.This register is used to + * configure the changing step scale of duty on channel 5. + */ +#define LEDC_CH5_GAMMA_SCALE 0x000003FFU +#define LEDC_CH5_GAMMA_SCALE_M (LEDC_CH5_GAMMA_SCALE_V << LEDC_CH5_GAMMA_SCALE_S) +#define LEDC_CH5_GAMMA_SCALE_V 0x000003FFU +#define LEDC_CH5_GAMMA_SCALE_S 11 +/** LEDC_CH5_GAMMA_DUTY_NUM : R/W; bitpos: [30:21]; default: 0; + * Ledc ch5 gamma duty num of current ram write address.This register is used to + * control the number of times the duty cycle will be changed. + */ +#define LEDC_CH5_GAMMA_DUTY_NUM 0x000003FFU +#define LEDC_CH5_GAMMA_DUTY_NUM_M (LEDC_CH5_GAMMA_DUTY_NUM_V << LEDC_CH5_GAMMA_DUTY_NUM_S) +#define LEDC_CH5_GAMMA_DUTY_NUM_V 0x000003FFU +#define LEDC_CH5_GAMMA_DUTY_NUM_S 21 + +/** LEDC_CH5_GAMMA_WR_ADDR_REG register + * Ledc ch5 gamma ram write address register. + */ +#define LEDC_CH5_GAMMA_WR_ADDR_REG (DR_REG_LEDC_BASE + 0x154) +/** LEDC_CH5_GAMMA_WR_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch5 gamma ram write address. + */ +#define LEDC_CH5_GAMMA_WR_ADDR 0x0000000FU +#define LEDC_CH5_GAMMA_WR_ADDR_M (LEDC_CH5_GAMMA_WR_ADDR_V << LEDC_CH5_GAMMA_WR_ADDR_S) +#define LEDC_CH5_GAMMA_WR_ADDR_V 0x0000000FU +#define LEDC_CH5_GAMMA_WR_ADDR_S 0 + +/** LEDC_CH5_GAMMA_RD_ADDR_REG register + * Ledc ch5 gamma ram read address register. + */ +#define LEDC_CH5_GAMMA_RD_ADDR_REG (DR_REG_LEDC_BASE + 0x158) +/** LEDC_CH5_GAMMA_RD_ADDR : R/W; bitpos: [3:0]; default: 0; + * Ledc ch5 gamma ram read address. + */ +#define LEDC_CH5_GAMMA_RD_ADDR 0x0000000FU +#define LEDC_CH5_GAMMA_RD_ADDR_M (LEDC_CH5_GAMMA_RD_ADDR_V << LEDC_CH5_GAMMA_RD_ADDR_S) +#define LEDC_CH5_GAMMA_RD_ADDR_V 0x0000000FU +#define LEDC_CH5_GAMMA_RD_ADDR_S 0 + +/** LEDC_CH5_GAMMA_RD_DATA_REG register + * Ledc ch5 gamma ram read data register. + */ +#define LEDC_CH5_GAMMA_RD_DATA_REG (DR_REG_LEDC_BASE + 0x15c) +/** LEDC_CH5_GAMMA_RD_DATA : RO; bitpos: [30:0]; default: 0; + * Ledc ch5 gamma ram read data. + */ +#define LEDC_CH5_GAMMA_RD_DATA 0x7FFFFFFFU +#define LEDC_CH5_GAMMA_RD_DATA_M (LEDC_CH5_GAMMA_RD_DATA_V << LEDC_CH5_GAMMA_RD_DATA_S) +#define LEDC_CH5_GAMMA_RD_DATA_V 0x7FFFFFFFU +#define LEDC_CH5_GAMMA_RD_DATA_S 0 + +/** LEDC_CH0_GAMMA_CONF_REG register + * Ledc ch0 gamma config register. + */ +#define LEDC_CH0_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x180) +/** LEDC_CH0_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Ledc ch0 gamma entry num. + */ +#define LEDC_CH0_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH0_GAMMA_ENTRY_NUM_M (LEDC_CH0_GAMMA_ENTRY_NUM_V << LEDC_CH0_GAMMA_ENTRY_NUM_S) +#define LEDC_CH0_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH0_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH0_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Ledc ch0 gamma pause, write 1 to pause. + */ +#define LEDC_CH0_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH0_GAMMA_PAUSE_M (LEDC_CH0_GAMMA_PAUSE_V << LEDC_CH0_GAMMA_PAUSE_S) +#define LEDC_CH0_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH0_GAMMA_PAUSE_S 5 +/** LEDC_CH0_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Ledc ch0 gamma resume, write 1 to resume. + */ +#define LEDC_CH0_GAMMA_RESUME (BIT(6)) +#define LEDC_CH0_GAMMA_RESUME_M (LEDC_CH0_GAMMA_RESUME_V << LEDC_CH0_GAMMA_RESUME_S) +#define LEDC_CH0_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH0_GAMMA_RESUME_S 6 + +/** LEDC_CH1_GAMMA_CONF_REG register + * Ledc ch1 gamma config register. + */ +#define LEDC_CH1_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x184) +/** LEDC_CH1_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Ledc ch1 gamma entry num. + */ +#define LEDC_CH1_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH1_GAMMA_ENTRY_NUM_M (LEDC_CH1_GAMMA_ENTRY_NUM_V << LEDC_CH1_GAMMA_ENTRY_NUM_S) +#define LEDC_CH1_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH1_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH1_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Ledc ch1 gamma pause, write 1 to pause. + */ +#define LEDC_CH1_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH1_GAMMA_PAUSE_M (LEDC_CH1_GAMMA_PAUSE_V << LEDC_CH1_GAMMA_PAUSE_S) +#define LEDC_CH1_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH1_GAMMA_PAUSE_S 5 +/** LEDC_CH1_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Ledc ch1 gamma resume, write 1 to resume. + */ +#define LEDC_CH1_GAMMA_RESUME (BIT(6)) +#define LEDC_CH1_GAMMA_RESUME_M (LEDC_CH1_GAMMA_RESUME_V << LEDC_CH1_GAMMA_RESUME_S) +#define LEDC_CH1_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH1_GAMMA_RESUME_S 6 + +/** LEDC_CH2_GAMMA_CONF_REG register + * Ledc ch2 gamma config register. + */ +#define LEDC_CH2_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x188) +/** LEDC_CH2_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Ledc ch2 gamma entry num. + */ +#define LEDC_CH2_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH2_GAMMA_ENTRY_NUM_M (LEDC_CH2_GAMMA_ENTRY_NUM_V << LEDC_CH2_GAMMA_ENTRY_NUM_S) +#define LEDC_CH2_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH2_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH2_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Ledc ch2 gamma pause, write 1 to pause. + */ +#define LEDC_CH2_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH2_GAMMA_PAUSE_M (LEDC_CH2_GAMMA_PAUSE_V << LEDC_CH2_GAMMA_PAUSE_S) +#define LEDC_CH2_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH2_GAMMA_PAUSE_S 5 +/** LEDC_CH2_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Ledc ch2 gamma resume, write 1 to resume. + */ +#define LEDC_CH2_GAMMA_RESUME (BIT(6)) +#define LEDC_CH2_GAMMA_RESUME_M (LEDC_CH2_GAMMA_RESUME_V << LEDC_CH2_GAMMA_RESUME_S) +#define LEDC_CH2_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH2_GAMMA_RESUME_S 6 + +/** LEDC_CH3_GAMMA_CONF_REG register + * Ledc ch3 gamma config register. + */ +#define LEDC_CH3_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x18c) +/** LEDC_CH3_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Ledc ch3 gamma entry num. + */ +#define LEDC_CH3_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH3_GAMMA_ENTRY_NUM_M (LEDC_CH3_GAMMA_ENTRY_NUM_V << LEDC_CH3_GAMMA_ENTRY_NUM_S) +#define LEDC_CH3_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH3_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH3_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Ledc ch3 gamma pause, write 1 to pause. + */ +#define LEDC_CH3_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH3_GAMMA_PAUSE_M (LEDC_CH3_GAMMA_PAUSE_V << LEDC_CH3_GAMMA_PAUSE_S) +#define LEDC_CH3_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH3_GAMMA_PAUSE_S 5 +/** LEDC_CH3_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Ledc ch3 gamma resume, write 1 to resume. + */ +#define LEDC_CH3_GAMMA_RESUME (BIT(6)) +#define LEDC_CH3_GAMMA_RESUME_M (LEDC_CH3_GAMMA_RESUME_V << LEDC_CH3_GAMMA_RESUME_S) +#define LEDC_CH3_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH3_GAMMA_RESUME_S 6 + +/** LEDC_CH4_GAMMA_CONF_REG register + * Ledc ch4 gamma config register. + */ +#define LEDC_CH4_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x190) +/** LEDC_CH4_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Ledc ch4 gamma entry num. + */ +#define LEDC_CH4_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH4_GAMMA_ENTRY_NUM_M (LEDC_CH4_GAMMA_ENTRY_NUM_V << LEDC_CH4_GAMMA_ENTRY_NUM_S) +#define LEDC_CH4_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH4_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH4_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Ledc ch4 gamma pause, write 1 to pause. + */ +#define LEDC_CH4_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH4_GAMMA_PAUSE_M (LEDC_CH4_GAMMA_PAUSE_V << LEDC_CH4_GAMMA_PAUSE_S) +#define LEDC_CH4_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH4_GAMMA_PAUSE_S 5 +/** LEDC_CH4_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Ledc ch4 gamma resume, write 1 to resume. + */ +#define LEDC_CH4_GAMMA_RESUME (BIT(6)) +#define LEDC_CH4_GAMMA_RESUME_M (LEDC_CH4_GAMMA_RESUME_V << LEDC_CH4_GAMMA_RESUME_S) +#define LEDC_CH4_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH4_GAMMA_RESUME_S 6 + +/** LEDC_CH5_GAMMA_CONF_REG register + * Ledc ch5 gamma config register. + */ +#define LEDC_CH5_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x194) +/** LEDC_CH5_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Ledc ch5 gamma entry num. + */ +#define LEDC_CH5_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH5_GAMMA_ENTRY_NUM_M (LEDC_CH5_GAMMA_ENTRY_NUM_V << LEDC_CH5_GAMMA_ENTRY_NUM_S) +#define LEDC_CH5_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH5_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH5_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Ledc ch5 gamma pause, write 1 to pause. + */ +#define LEDC_CH5_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH5_GAMMA_PAUSE_M (LEDC_CH5_GAMMA_PAUSE_V << LEDC_CH5_GAMMA_PAUSE_S) +#define LEDC_CH5_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH5_GAMMA_PAUSE_S 5 +/** LEDC_CH5_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Ledc ch5 gamma resume, write 1 to resume. + */ +#define LEDC_CH5_GAMMA_RESUME (BIT(6)) +#define LEDC_CH5_GAMMA_RESUME_M (LEDC_CH5_GAMMA_RESUME_V << LEDC_CH5_GAMMA_RESUME_S) +#define LEDC_CH5_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH5_GAMMA_RESUME_S 6 + +/** LEDC_EVT_TASK_EN0_REG register + * Ledc event task enable bit register0. + */ +#define LEDC_EVT_TASK_EN0_REG (DR_REG_LEDC_BASE + 0x1a0) +/** LEDC_EVT_DUTY_CHNG_END_CH0_EN : R/W; bitpos: [0]; default: 0; + * Ledc ch0 duty change end event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN (BIT(0)) +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_M (LEDC_EVT_DUTY_CHNG_END_CH0_EN_V << LEDC_EVT_DUTY_CHNG_END_CH0_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_S 0 +/** LEDC_EVT_DUTY_CHNG_END_CH1_EN : R/W; bitpos: [1]; default: 0; + * Ledc ch1 duty change end event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN (BIT(1)) +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_M (LEDC_EVT_DUTY_CHNG_END_CH1_EN_V << LEDC_EVT_DUTY_CHNG_END_CH1_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_S 1 +/** LEDC_EVT_DUTY_CHNG_END_CH2_EN : R/W; bitpos: [2]; default: 0; + * Ledc ch2 duty change end event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN (BIT(2)) +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_M (LEDC_EVT_DUTY_CHNG_END_CH2_EN_V << LEDC_EVT_DUTY_CHNG_END_CH2_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_S 2 +/** LEDC_EVT_DUTY_CHNG_END_CH3_EN : R/W; bitpos: [3]; default: 0; + * Ledc ch3 duty change end event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN (BIT(3)) +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_M (LEDC_EVT_DUTY_CHNG_END_CH3_EN_V << LEDC_EVT_DUTY_CHNG_END_CH3_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_S 3 +/** LEDC_EVT_DUTY_CHNG_END_CH4_EN : R/W; bitpos: [4]; default: 0; + * Ledc ch4 duty change end event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN (BIT(4)) +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_M (LEDC_EVT_DUTY_CHNG_END_CH4_EN_V << LEDC_EVT_DUTY_CHNG_END_CH4_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_S 4 +/** LEDC_EVT_DUTY_CHNG_END_CH5_EN : R/W; bitpos: [5]; default: 0; + * Ledc ch5 duty change end event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN (BIT(5)) +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_M (LEDC_EVT_DUTY_CHNG_END_CH5_EN_V << LEDC_EVT_DUTY_CHNG_END_CH5_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_S 5 +/** LEDC_EVT_OVF_CNT_PLS_CH0_EN : R/W; bitpos: [8]; default: 0; + * Ledc ch0 overflow count pulse event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN (BIT(8)) +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_M (LEDC_EVT_OVF_CNT_PLS_CH0_EN_V << LEDC_EVT_OVF_CNT_PLS_CH0_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_S 8 +/** LEDC_EVT_OVF_CNT_PLS_CH1_EN : R/W; bitpos: [9]; default: 0; + * Ledc ch1 overflow count pulse event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN (BIT(9)) +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_M (LEDC_EVT_OVF_CNT_PLS_CH1_EN_V << LEDC_EVT_OVF_CNT_PLS_CH1_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_S 9 +/** LEDC_EVT_OVF_CNT_PLS_CH2_EN : R/W; bitpos: [10]; default: 0; + * Ledc ch2 overflow count pulse event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN (BIT(10)) +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_M (LEDC_EVT_OVF_CNT_PLS_CH2_EN_V << LEDC_EVT_OVF_CNT_PLS_CH2_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_S 10 +/** LEDC_EVT_OVF_CNT_PLS_CH3_EN : R/W; bitpos: [11]; default: 0; + * Ledc ch3 overflow count pulse event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN (BIT(11)) +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_M (LEDC_EVT_OVF_CNT_PLS_CH3_EN_V << LEDC_EVT_OVF_CNT_PLS_CH3_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_S 11 +/** LEDC_EVT_OVF_CNT_PLS_CH4_EN : R/W; bitpos: [12]; default: 0; + * Ledc ch4 overflow count pulse event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN (BIT(12)) +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_M (LEDC_EVT_OVF_CNT_PLS_CH4_EN_V << LEDC_EVT_OVF_CNT_PLS_CH4_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_S 12 +/** LEDC_EVT_OVF_CNT_PLS_CH5_EN : R/W; bitpos: [13]; default: 0; + * Ledc ch5 overflow count pulse event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN (BIT(13)) +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_M (LEDC_EVT_OVF_CNT_PLS_CH5_EN_V << LEDC_EVT_OVF_CNT_PLS_CH5_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_S 13 +/** LEDC_EVT_TIME_OVF_TIMER0_EN : R/W; bitpos: [16]; default: 0; + * Ledc timer0 overflow event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_TIME_OVF_TIMER0_EN (BIT(16)) +#define LEDC_EVT_TIME_OVF_TIMER0_EN_M (LEDC_EVT_TIME_OVF_TIMER0_EN_V << LEDC_EVT_TIME_OVF_TIMER0_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER0_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER0_EN_S 16 +/** LEDC_EVT_TIME_OVF_TIMER1_EN : R/W; bitpos: [17]; default: 0; + * Ledc timer1 overflow event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_TIME_OVF_TIMER1_EN (BIT(17)) +#define LEDC_EVT_TIME_OVF_TIMER1_EN_M (LEDC_EVT_TIME_OVF_TIMER1_EN_V << LEDC_EVT_TIME_OVF_TIMER1_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER1_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER1_EN_S 17 +/** LEDC_EVT_TIME_OVF_TIMER2_EN : R/W; bitpos: [18]; default: 0; + * Ledc timer2 overflow event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_TIME_OVF_TIMER2_EN (BIT(18)) +#define LEDC_EVT_TIME_OVF_TIMER2_EN_M (LEDC_EVT_TIME_OVF_TIMER2_EN_V << LEDC_EVT_TIME_OVF_TIMER2_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER2_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER2_EN_S 18 +/** LEDC_EVT_TIME_OVF_TIMER3_EN : R/W; bitpos: [19]; default: 0; + * Ledc timer3 overflow event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_TIME_OVF_TIMER3_EN (BIT(19)) +#define LEDC_EVT_TIME_OVF_TIMER3_EN_M (LEDC_EVT_TIME_OVF_TIMER3_EN_V << LEDC_EVT_TIME_OVF_TIMER3_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER3_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER3_EN_S 19 +/** LEDC_EVT_TIME0_CMP_EN : R/W; bitpos: [20]; default: 0; + * Ledc timer0 compare event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_TIME0_CMP_EN (BIT(20)) +#define LEDC_EVT_TIME0_CMP_EN_M (LEDC_EVT_TIME0_CMP_EN_V << LEDC_EVT_TIME0_CMP_EN_S) +#define LEDC_EVT_TIME0_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME0_CMP_EN_S 20 +/** LEDC_EVT_TIME1_CMP_EN : R/W; bitpos: [21]; default: 0; + * Ledc timer1 compare event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_TIME1_CMP_EN (BIT(21)) +#define LEDC_EVT_TIME1_CMP_EN_M (LEDC_EVT_TIME1_CMP_EN_V << LEDC_EVT_TIME1_CMP_EN_S) +#define LEDC_EVT_TIME1_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME1_CMP_EN_S 21 +/** LEDC_EVT_TIME2_CMP_EN : R/W; bitpos: [22]; default: 0; + * Ledc timer2 compare event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_TIME2_CMP_EN (BIT(22)) +#define LEDC_EVT_TIME2_CMP_EN_M (LEDC_EVT_TIME2_CMP_EN_V << LEDC_EVT_TIME2_CMP_EN_S) +#define LEDC_EVT_TIME2_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME2_CMP_EN_S 22 +/** LEDC_EVT_TIME3_CMP_EN : R/W; bitpos: [23]; default: 0; + * Ledc timer3 compare event enable register, write 1 to enable this event. + */ +#define LEDC_EVT_TIME3_CMP_EN (BIT(23)) +#define LEDC_EVT_TIME3_CMP_EN_M (LEDC_EVT_TIME3_CMP_EN_V << LEDC_EVT_TIME3_CMP_EN_S) +#define LEDC_EVT_TIME3_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME3_CMP_EN_S 23 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN : R/W; bitpos: [24]; default: 0; + * Ledc ch0 duty scale update task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN (BIT(24)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S 24 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN : R/W; bitpos: [25]; default: 0; + * Ledc ch1 duty scale update task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN (BIT(25)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S 25 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN : R/W; bitpos: [26]; default: 0; + * Ledc ch2 duty scale update task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN (BIT(26)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S 26 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN : R/W; bitpos: [27]; default: 0; + * Ledc ch3 duty scale update task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN (BIT(27)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S 27 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN : R/W; bitpos: [28]; default: 0; + * Ledc ch4 duty scale update task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN (BIT(28)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S 28 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN : R/W; bitpos: [29]; default: 0; + * Ledc ch5 duty scale update task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN (BIT(29)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S 29 + +/** LEDC_EVT_TASK_EN1_REG register + * Ledc event task enable bit register1. + */ +#define LEDC_EVT_TASK_EN1_REG (DR_REG_LEDC_BASE + 0x1a4) +/** LEDC_TASK_TIMER0_RES_UPDATE_EN : R/W; bitpos: [0]; default: 0; + * Ledc timer0 res update task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER0_RES_UPDATE_EN (BIT(0)) +#define LEDC_TASK_TIMER0_RES_UPDATE_EN_M (LEDC_TASK_TIMER0_RES_UPDATE_EN_V << LEDC_TASK_TIMER0_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER0_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_RES_UPDATE_EN_S 0 +/** LEDC_TASK_TIMER1_RES_UPDATE_EN : R/W; bitpos: [1]; default: 0; + * Ledc timer1 res update task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER1_RES_UPDATE_EN (BIT(1)) +#define LEDC_TASK_TIMER1_RES_UPDATE_EN_M (LEDC_TASK_TIMER1_RES_UPDATE_EN_V << LEDC_TASK_TIMER1_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER1_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_RES_UPDATE_EN_S 1 +/** LEDC_TASK_TIMER2_RES_UPDATE_EN : R/W; bitpos: [2]; default: 0; + * Ledc timer2 res update task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER2_RES_UPDATE_EN (BIT(2)) +#define LEDC_TASK_TIMER2_RES_UPDATE_EN_M (LEDC_TASK_TIMER2_RES_UPDATE_EN_V << LEDC_TASK_TIMER2_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER2_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_RES_UPDATE_EN_S 2 +/** LEDC_TASK_TIMER3_RES_UPDATE_EN : R/W; bitpos: [3]; default: 0; + * Ledc timer3 res update task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER3_RES_UPDATE_EN (BIT(3)) +#define LEDC_TASK_TIMER3_RES_UPDATE_EN_M (LEDC_TASK_TIMER3_RES_UPDATE_EN_V << LEDC_TASK_TIMER3_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER3_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_RES_UPDATE_EN_S 3 +/** LEDC_TASK_TIMER0_CAP_EN : R/W; bitpos: [4]; default: 0; + * Ledc timer0 capture task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER0_CAP_EN (BIT(4)) +#define LEDC_TASK_TIMER0_CAP_EN_M (LEDC_TASK_TIMER0_CAP_EN_V << LEDC_TASK_TIMER0_CAP_EN_S) +#define LEDC_TASK_TIMER0_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_CAP_EN_S 4 +/** LEDC_TASK_TIMER1_CAP_EN : R/W; bitpos: [5]; default: 0; + * Ledc timer1 capture task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER1_CAP_EN (BIT(5)) +#define LEDC_TASK_TIMER1_CAP_EN_M (LEDC_TASK_TIMER1_CAP_EN_V << LEDC_TASK_TIMER1_CAP_EN_S) +#define LEDC_TASK_TIMER1_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_CAP_EN_S 5 +/** LEDC_TASK_TIMER2_CAP_EN : R/W; bitpos: [6]; default: 0; + * Ledc timer2 capture task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER2_CAP_EN (BIT(6)) +#define LEDC_TASK_TIMER2_CAP_EN_M (LEDC_TASK_TIMER2_CAP_EN_V << LEDC_TASK_TIMER2_CAP_EN_S) +#define LEDC_TASK_TIMER2_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_CAP_EN_S 6 +/** LEDC_TASK_TIMER3_CAP_EN : R/W; bitpos: [7]; default: 0; + * Ledc timer3 capture task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER3_CAP_EN (BIT(7)) +#define LEDC_TASK_TIMER3_CAP_EN_M (LEDC_TASK_TIMER3_CAP_EN_V << LEDC_TASK_TIMER3_CAP_EN_S) +#define LEDC_TASK_TIMER3_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_CAP_EN_S 7 +/** LEDC_TASK_SIG_OUT_DIS_CH0_EN : R/W; bitpos: [8]; default: 0; + * Ledc ch0 signal out disable task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN (BIT(8)) +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_M (LEDC_TASK_SIG_OUT_DIS_CH0_EN_V << LEDC_TASK_SIG_OUT_DIS_CH0_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_S 8 +/** LEDC_TASK_SIG_OUT_DIS_CH1_EN : R/W; bitpos: [9]; default: 0; + * Ledc ch1 signal out disable task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN (BIT(9)) +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_M (LEDC_TASK_SIG_OUT_DIS_CH1_EN_V << LEDC_TASK_SIG_OUT_DIS_CH1_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_S 9 +/** LEDC_TASK_SIG_OUT_DIS_CH2_EN : R/W; bitpos: [10]; default: 0; + * Ledc ch2 signal out disable task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN (BIT(10)) +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_M (LEDC_TASK_SIG_OUT_DIS_CH2_EN_V << LEDC_TASK_SIG_OUT_DIS_CH2_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_S 10 +/** LEDC_TASK_SIG_OUT_DIS_CH3_EN : R/W; bitpos: [11]; default: 0; + * Ledc ch3 signal out disable task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN (BIT(11)) +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_M (LEDC_TASK_SIG_OUT_DIS_CH3_EN_V << LEDC_TASK_SIG_OUT_DIS_CH3_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_S 11 +/** LEDC_TASK_SIG_OUT_DIS_CH4_EN : R/W; bitpos: [12]; default: 0; + * Ledc ch4 signal out disable task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN (BIT(12)) +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_M (LEDC_TASK_SIG_OUT_DIS_CH4_EN_V << LEDC_TASK_SIG_OUT_DIS_CH4_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_S 12 +/** LEDC_TASK_SIG_OUT_DIS_CH5_EN : R/W; bitpos: [13]; default: 0; + * Ledc ch5 signal out disable task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN (BIT(13)) +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_M (LEDC_TASK_SIG_OUT_DIS_CH5_EN_V << LEDC_TASK_SIG_OUT_DIS_CH5_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_S 13 +/** LEDC_TASK_OVF_CNT_RST_CH0_EN : R/W; bitpos: [16]; default: 0; + * Ledc ch0 overflow count reset task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_OVF_CNT_RST_CH0_EN (BIT(16)) +#define LEDC_TASK_OVF_CNT_RST_CH0_EN_M (LEDC_TASK_OVF_CNT_RST_CH0_EN_V << LEDC_TASK_OVF_CNT_RST_CH0_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH0_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH0_EN_S 16 +/** LEDC_TASK_OVF_CNT_RST_CH1_EN : R/W; bitpos: [17]; default: 0; + * Ledc ch1 overflow count reset task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_OVF_CNT_RST_CH1_EN (BIT(17)) +#define LEDC_TASK_OVF_CNT_RST_CH1_EN_M (LEDC_TASK_OVF_CNT_RST_CH1_EN_V << LEDC_TASK_OVF_CNT_RST_CH1_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH1_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH1_EN_S 17 +/** LEDC_TASK_OVF_CNT_RST_CH2_EN : R/W; bitpos: [18]; default: 0; + * Ledc ch2 overflow count reset task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_OVF_CNT_RST_CH2_EN (BIT(18)) +#define LEDC_TASK_OVF_CNT_RST_CH2_EN_M (LEDC_TASK_OVF_CNT_RST_CH2_EN_V << LEDC_TASK_OVF_CNT_RST_CH2_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH2_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH2_EN_S 18 +/** LEDC_TASK_OVF_CNT_RST_CH3_EN : R/W; bitpos: [19]; default: 0; + * Ledc ch3 overflow count reset task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_OVF_CNT_RST_CH3_EN (BIT(19)) +#define LEDC_TASK_OVF_CNT_RST_CH3_EN_M (LEDC_TASK_OVF_CNT_RST_CH3_EN_V << LEDC_TASK_OVF_CNT_RST_CH3_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH3_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH3_EN_S 19 +/** LEDC_TASK_OVF_CNT_RST_CH4_EN : R/W; bitpos: [20]; default: 0; + * Ledc ch4 overflow count reset task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_OVF_CNT_RST_CH4_EN (BIT(20)) +#define LEDC_TASK_OVF_CNT_RST_CH4_EN_M (LEDC_TASK_OVF_CNT_RST_CH4_EN_V << LEDC_TASK_OVF_CNT_RST_CH4_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH4_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH4_EN_S 20 +/** LEDC_TASK_OVF_CNT_RST_CH5_EN : R/W; bitpos: [21]; default: 0; + * Ledc ch5 overflow count reset task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_OVF_CNT_RST_CH5_EN (BIT(21)) +#define LEDC_TASK_OVF_CNT_RST_CH5_EN_M (LEDC_TASK_OVF_CNT_RST_CH5_EN_V << LEDC_TASK_OVF_CNT_RST_CH5_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH5_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH5_EN_S 21 +/** LEDC_TASK_TIMER0_RST_EN : R/W; bitpos: [24]; default: 0; + * Ledc timer0 reset task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER0_RST_EN (BIT(24)) +#define LEDC_TASK_TIMER0_RST_EN_M (LEDC_TASK_TIMER0_RST_EN_V << LEDC_TASK_TIMER0_RST_EN_S) +#define LEDC_TASK_TIMER0_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_RST_EN_S 24 +/** LEDC_TASK_TIMER1_RST_EN : R/W; bitpos: [25]; default: 0; + * Ledc timer1 reset task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER1_RST_EN (BIT(25)) +#define LEDC_TASK_TIMER1_RST_EN_M (LEDC_TASK_TIMER1_RST_EN_V << LEDC_TASK_TIMER1_RST_EN_S) +#define LEDC_TASK_TIMER1_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_RST_EN_S 25 +/** LEDC_TASK_TIMER2_RST_EN : R/W; bitpos: [26]; default: 0; + * Ledc timer2 reset task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER2_RST_EN (BIT(26)) +#define LEDC_TASK_TIMER2_RST_EN_M (LEDC_TASK_TIMER2_RST_EN_V << LEDC_TASK_TIMER2_RST_EN_S) +#define LEDC_TASK_TIMER2_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_RST_EN_S 26 +/** LEDC_TASK_TIMER3_RST_EN : R/W; bitpos: [27]; default: 0; + * Ledc timer3 reset task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER3_RST_EN (BIT(27)) +#define LEDC_TASK_TIMER3_RST_EN_M (LEDC_TASK_TIMER3_RST_EN_V << LEDC_TASK_TIMER3_RST_EN_S) +#define LEDC_TASK_TIMER3_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_RST_EN_S 27 +/** LEDC_TASK_TIMER0_PAUSE_RESUME_EN : R/W; bitpos: [28]; default: 0; + * Ledc timer0 pause resume task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN (BIT(28)) +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S 28 +/** LEDC_TASK_TIMER1_PAUSE_RESUME_EN : R/W; bitpos: [29]; default: 0; + * Ledc timer1 pause resume task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN (BIT(29)) +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S 29 +/** LEDC_TASK_TIMER2_PAUSE_RESUME_EN : R/W; bitpos: [30]; default: 0; + * Ledc timer2 pause resume task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN (BIT(30)) +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S 30 +/** LEDC_TASK_TIMER3_PAUSE_RESUME_EN : R/W; bitpos: [31]; default: 0; + * Ledc timer3 pause resume task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN (BIT(31)) +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S 31 + +/** LEDC_EVT_TASK_EN2_REG register + * Ledc event task enable bit register2. + */ +#define LEDC_EVT_TASK_EN2_REG (DR_REG_LEDC_BASE + 0x1a8) +/** LEDC_TASK_GAMMA_RESTART_CH0_EN : R/W; bitpos: [0]; default: 0; + * Ledc ch0 gamma restart task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESTART_CH0_EN (BIT(0)) +#define LEDC_TASK_GAMMA_RESTART_CH0_EN_M (LEDC_TASK_GAMMA_RESTART_CH0_EN_V << LEDC_TASK_GAMMA_RESTART_CH0_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH0_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH0_EN_S 0 +/** LEDC_TASK_GAMMA_RESTART_CH1_EN : R/W; bitpos: [1]; default: 0; + * Ledc ch1 gamma restart task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESTART_CH1_EN (BIT(1)) +#define LEDC_TASK_GAMMA_RESTART_CH1_EN_M (LEDC_TASK_GAMMA_RESTART_CH1_EN_V << LEDC_TASK_GAMMA_RESTART_CH1_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH1_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH1_EN_S 1 +/** LEDC_TASK_GAMMA_RESTART_CH2_EN : R/W; bitpos: [2]; default: 0; + * Ledc ch2 gamma restart task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESTART_CH2_EN (BIT(2)) +#define LEDC_TASK_GAMMA_RESTART_CH2_EN_M (LEDC_TASK_GAMMA_RESTART_CH2_EN_V << LEDC_TASK_GAMMA_RESTART_CH2_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH2_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH2_EN_S 2 +/** LEDC_TASK_GAMMA_RESTART_CH3_EN : R/W; bitpos: [3]; default: 0; + * Ledc ch3 gamma restart task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESTART_CH3_EN (BIT(3)) +#define LEDC_TASK_GAMMA_RESTART_CH3_EN_M (LEDC_TASK_GAMMA_RESTART_CH3_EN_V << LEDC_TASK_GAMMA_RESTART_CH3_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH3_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH3_EN_S 3 +/** LEDC_TASK_GAMMA_RESTART_CH4_EN : R/W; bitpos: [4]; default: 0; + * Ledc ch4 gamma restart task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESTART_CH4_EN (BIT(4)) +#define LEDC_TASK_GAMMA_RESTART_CH4_EN_M (LEDC_TASK_GAMMA_RESTART_CH4_EN_V << LEDC_TASK_GAMMA_RESTART_CH4_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH4_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH4_EN_S 4 +/** LEDC_TASK_GAMMA_RESTART_CH5_EN : R/W; bitpos: [5]; default: 0; + * Ledc ch5 gamma restart task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESTART_CH5_EN (BIT(5)) +#define LEDC_TASK_GAMMA_RESTART_CH5_EN_M (LEDC_TASK_GAMMA_RESTART_CH5_EN_V << LEDC_TASK_GAMMA_RESTART_CH5_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH5_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH5_EN_S 5 +/** LEDC_TASK_GAMMA_PAUSE_CH0_EN : R/W; bitpos: [8]; default: 0; + * Ledc ch0 gamma pause task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN (BIT(8)) +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_M (LEDC_TASK_GAMMA_PAUSE_CH0_EN_V << LEDC_TASK_GAMMA_PAUSE_CH0_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_S 8 +/** LEDC_TASK_GAMMA_PAUSE_CH1_EN : R/W; bitpos: [9]; default: 0; + * Ledc ch1 gamma pause task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN (BIT(9)) +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_M (LEDC_TASK_GAMMA_PAUSE_CH1_EN_V << LEDC_TASK_GAMMA_PAUSE_CH1_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_S 9 +/** LEDC_TASK_GAMMA_PAUSE_CH2_EN : R/W; bitpos: [10]; default: 0; + * Ledc ch2 gamma pause task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN (BIT(10)) +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_M (LEDC_TASK_GAMMA_PAUSE_CH2_EN_V << LEDC_TASK_GAMMA_PAUSE_CH2_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_S 10 +/** LEDC_TASK_GAMMA_PAUSE_CH3_EN : R/W; bitpos: [11]; default: 0; + * Ledc ch3 gamma pause task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN (BIT(11)) +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_M (LEDC_TASK_GAMMA_PAUSE_CH3_EN_V << LEDC_TASK_GAMMA_PAUSE_CH3_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_S 11 +/** LEDC_TASK_GAMMA_PAUSE_CH4_EN : R/W; bitpos: [12]; default: 0; + * Ledc ch4 gamma pause task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN (BIT(12)) +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_M (LEDC_TASK_GAMMA_PAUSE_CH4_EN_V << LEDC_TASK_GAMMA_PAUSE_CH4_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_S 12 +/** LEDC_TASK_GAMMA_PAUSE_CH5_EN : R/W; bitpos: [13]; default: 0; + * Ledc ch5 gamma pause task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN (BIT(13)) +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_M (LEDC_TASK_GAMMA_PAUSE_CH5_EN_V << LEDC_TASK_GAMMA_PAUSE_CH5_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_S 13 +/** LEDC_TASK_GAMMA_RESUME_CH0_EN : R/W; bitpos: [16]; default: 0; + * Ledc ch0 gamma resume task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESUME_CH0_EN (BIT(16)) +#define LEDC_TASK_GAMMA_RESUME_CH0_EN_M (LEDC_TASK_GAMMA_RESUME_CH0_EN_V << LEDC_TASK_GAMMA_RESUME_CH0_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH0_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH0_EN_S 16 +/** LEDC_TASK_GAMMA_RESUME_CH1_EN : R/W; bitpos: [17]; default: 0; + * Ledc ch1 gamma resume task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESUME_CH1_EN (BIT(17)) +#define LEDC_TASK_GAMMA_RESUME_CH1_EN_M (LEDC_TASK_GAMMA_RESUME_CH1_EN_V << LEDC_TASK_GAMMA_RESUME_CH1_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH1_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH1_EN_S 17 +/** LEDC_TASK_GAMMA_RESUME_CH2_EN : R/W; bitpos: [18]; default: 0; + * Ledc ch2 gamma resume task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESUME_CH2_EN (BIT(18)) +#define LEDC_TASK_GAMMA_RESUME_CH2_EN_M (LEDC_TASK_GAMMA_RESUME_CH2_EN_V << LEDC_TASK_GAMMA_RESUME_CH2_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH2_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH2_EN_S 18 +/** LEDC_TASK_GAMMA_RESUME_CH3_EN : R/W; bitpos: [19]; default: 0; + * Ledc ch3 gamma resume task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESUME_CH3_EN (BIT(19)) +#define LEDC_TASK_GAMMA_RESUME_CH3_EN_M (LEDC_TASK_GAMMA_RESUME_CH3_EN_V << LEDC_TASK_GAMMA_RESUME_CH3_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH3_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH3_EN_S 19 +/** LEDC_TASK_GAMMA_RESUME_CH4_EN : R/W; bitpos: [20]; default: 0; + * Ledc ch4 gamma resume task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESUME_CH4_EN (BIT(20)) +#define LEDC_TASK_GAMMA_RESUME_CH4_EN_M (LEDC_TASK_GAMMA_RESUME_CH4_EN_V << LEDC_TASK_GAMMA_RESUME_CH4_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH4_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH4_EN_S 20 +/** LEDC_TASK_GAMMA_RESUME_CH5_EN : R/W; bitpos: [21]; default: 0; + * Ledc ch5 gamma resume task enable register, write 1 to enable this task. + */ +#define LEDC_TASK_GAMMA_RESUME_CH5_EN (BIT(21)) +#define LEDC_TASK_GAMMA_RESUME_CH5_EN_M (LEDC_TASK_GAMMA_RESUME_CH5_EN_V << LEDC_TASK_GAMMA_RESUME_CH5_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH5_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH5_EN_S 21 + +/** LEDC_TIMER0_CMP_REG register + * Ledc timer0 compare value register. + */ +#define LEDC_TIMER0_CMP_REG (DR_REG_LEDC_BASE + 0x1b0) +/** LEDC_TIMER0_CMP : R/W; bitpos: [19:0]; default: 0; + * This register stores ledc timer0 compare value. + */ +#define LEDC_TIMER0_CMP 0x000FFFFFU +#define LEDC_TIMER0_CMP_M (LEDC_TIMER0_CMP_V << LEDC_TIMER0_CMP_S) +#define LEDC_TIMER0_CMP_V 0x000FFFFFU +#define LEDC_TIMER0_CMP_S 0 + +/** LEDC_TIMER1_CMP_REG register + * Ledc timer1 compare value register. + */ +#define LEDC_TIMER1_CMP_REG (DR_REG_LEDC_BASE + 0x1b4) +/** LEDC_TIMER1_CMP : R/W; bitpos: [19:0]; default: 0; + * This register stores ledc timer1 compare value. + */ +#define LEDC_TIMER1_CMP 0x000FFFFFU +#define LEDC_TIMER1_CMP_M (LEDC_TIMER1_CMP_V << LEDC_TIMER1_CMP_S) +#define LEDC_TIMER1_CMP_V 0x000FFFFFU +#define LEDC_TIMER1_CMP_S 0 + +/** LEDC_TIMER2_CMP_REG register + * Ledc timer2 compare value register. + */ +#define LEDC_TIMER2_CMP_REG (DR_REG_LEDC_BASE + 0x1b8) +/** LEDC_TIMER2_CMP : R/W; bitpos: [19:0]; default: 0; + * This register stores ledc timer2 compare value. + */ +#define LEDC_TIMER2_CMP 0x000FFFFFU +#define LEDC_TIMER2_CMP_M (LEDC_TIMER2_CMP_V << LEDC_TIMER2_CMP_S) +#define LEDC_TIMER2_CMP_V 0x000FFFFFU +#define LEDC_TIMER2_CMP_S 0 + +/** LEDC_TIMER3_CMP_REG register + * Ledc timer3 compare value register. + */ +#define LEDC_TIMER3_CMP_REG (DR_REG_LEDC_BASE + 0x1bc) +/** LEDC_TIMER3_CMP : R/W; bitpos: [19:0]; default: 0; + * This register stores ledc timer3 compare value. + */ +#define LEDC_TIMER3_CMP 0x000FFFFFU +#define LEDC_TIMER3_CMP_M (LEDC_TIMER3_CMP_V << LEDC_TIMER3_CMP_S) +#define LEDC_TIMER3_CMP_V 0x000FFFFFU +#define LEDC_TIMER3_CMP_S 0 + +/** LEDC_TIMER0_CNT_CAP_REG register + * Ledc timer0 count value capture register. + */ +#define LEDC_TIMER0_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x1c0) +/** LEDC_TIMER0_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * This register stores ledc timer0 count value. + */ +#define LEDC_TIMER0_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER0_CNT_CAP_M (LEDC_TIMER0_CNT_CAP_V << LEDC_TIMER0_CNT_CAP_S) +#define LEDC_TIMER0_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER0_CNT_CAP_S 0 + +/** LEDC_TIMER1_CNT_CAP_REG register + * Ledc timer1 count value capture register. + */ +#define LEDC_TIMER1_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x1c4) +/** LEDC_TIMER1_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * This register stores ledc timer1 count value. + */ +#define LEDC_TIMER1_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER1_CNT_CAP_M (LEDC_TIMER1_CNT_CAP_V << LEDC_TIMER1_CNT_CAP_S) +#define LEDC_TIMER1_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER1_CNT_CAP_S 0 + +/** LEDC_TIMER2_CNT_CAP_REG register + * Ledc timer2 count value capture register. + */ +#define LEDC_TIMER2_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x1c8) +/** LEDC_TIMER2_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * This register stores ledc timer2 count value. + */ +#define LEDC_TIMER2_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER2_CNT_CAP_M (LEDC_TIMER2_CNT_CAP_V << LEDC_TIMER2_CNT_CAP_S) +#define LEDC_TIMER2_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER2_CNT_CAP_S 0 + +/** LEDC_TIMER3_CNT_CAP_REG register + * Ledc timer3 count value capture register. + */ +#define LEDC_TIMER3_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x1cc) +/** LEDC_TIMER3_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * This register stores ledc timer3 count value. + */ +#define LEDC_TIMER3_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER3_CNT_CAP_M (LEDC_TIMER3_CNT_CAP_V << LEDC_TIMER3_CNT_CAP_S) +#define LEDC_TIMER3_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER3_CNT_CAP_S 0 + +/** LEDC_CONF_REG register + * Global ledc configuration register + */ +#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x1f0) +/** LEDC_APB_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * This bit is used to select clock source for the 4 timers . + * + * 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK + */ +#define LEDC_APB_CLK_SEL 0x00000003U +#define LEDC_APB_CLK_SEL_M (LEDC_APB_CLK_SEL_V << LEDC_APB_CLK_SEL_S) +#define LEDC_APB_CLK_SEL_V 0x00000003U +#define LEDC_APB_CLK_SEL_S 0 +/** LEDC_GAMMA_RAM_CLK_EN_CH0 : R/W; bitpos: [2]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH0 (BIT(2)) +#define LEDC_GAMMA_RAM_CLK_EN_CH0_M (LEDC_GAMMA_RAM_CLK_EN_CH0_V << LEDC_GAMMA_RAM_CLK_EN_CH0_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH0_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH0_S 2 +/** LEDC_GAMMA_RAM_CLK_EN_CH1 : R/W; bitpos: [3]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH1 (BIT(3)) +#define LEDC_GAMMA_RAM_CLK_EN_CH1_M (LEDC_GAMMA_RAM_CLK_EN_CH1_V << LEDC_GAMMA_RAM_CLK_EN_CH1_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH1_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH1_S 3 +/** LEDC_GAMMA_RAM_CLK_EN_CH2 : R/W; bitpos: [4]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH2 (BIT(4)) +#define LEDC_GAMMA_RAM_CLK_EN_CH2_M (LEDC_GAMMA_RAM_CLK_EN_CH2_V << LEDC_GAMMA_RAM_CLK_EN_CH2_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH2_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH2_S 4 +/** LEDC_GAMMA_RAM_CLK_EN_CH3 : R/W; bitpos: [5]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH3 (BIT(5)) +#define LEDC_GAMMA_RAM_CLK_EN_CH3_M (LEDC_GAMMA_RAM_CLK_EN_CH3_V << LEDC_GAMMA_RAM_CLK_EN_CH3_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH3_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH3_S 5 +/** LEDC_GAMMA_RAM_CLK_EN_CH4 : R/W; bitpos: [6]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH4 (BIT(6)) +#define LEDC_GAMMA_RAM_CLK_EN_CH4_M (LEDC_GAMMA_RAM_CLK_EN_CH4_V << LEDC_GAMMA_RAM_CLK_EN_CH4_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH4_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH4_S 6 +/** LEDC_GAMMA_RAM_CLK_EN_CH5 : R/W; bitpos: [7]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH5 (BIT(7)) +#define LEDC_GAMMA_RAM_CLK_EN_CH5_M (LEDC_GAMMA_RAM_CLK_EN_CH5_V << LEDC_GAMMA_RAM_CLK_EN_CH5_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH5_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH5_S 7 +/** LEDC_CLK_EN : R/W; bitpos: [31]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define LEDC_CLK_EN (BIT(31)) +#define LEDC_CLK_EN_M (LEDC_CLK_EN_V << LEDC_CLK_EN_S) +#define LEDC_CLK_EN_V 0x00000001U +#define LEDC_CLK_EN_S 31 + +/** LEDC_DATE_REG register + * Version control register + */ +#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x1fc) +/** LEDC_LEDC_DATE : R/W; bitpos: [27:0]; default: 34672976; + * This is the version control register. + */ +#define LEDC_LEDC_DATE 0x0FFFFFFFU +#define LEDC_LEDC_DATE_M (LEDC_LEDC_DATE_V << LEDC_LEDC_DATE_S) +#define LEDC_LEDC_DATE_V 0x0FFFFFFFU +#define LEDC_LEDC_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/ledc_struct.h b/components/soc/esp32c6/include/soc/ledc_struct.h new file mode 100644 index 0000000000..872315558e --- /dev/null +++ b/components/soc/esp32c6/include/soc/ledc_struct.h @@ -0,0 +1,1119 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of chn_conf0 register + * Configuration register 0 for channel n + */ +typedef union { + struct { + /** timer_sel : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel n. + * + * 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3 + */ + uint32_t timer_sel:2; + /** sig_out_en : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel n. + */ + uint32_t sig_out_en:1; + /** idle_lv : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel n is inactive (when + * LEDC_SIG_OUT_EN_CHn is 0). + */ + uint32_t idle_lv:1; + /** para_up : WT; bitpos: [4]; default: 0; + * This bit is used to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn, + * LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_DUTY_NUM_CHn, LEDC_DUTY_CYCLE_CHn, + * LEDC_DUTY_SCALE_CHn, LEDC_DUTY_INC_CHn, and LEDC_OVF_CNT_EN_CHn fields for channel + * n, and will be automatically cleared by hardware. + */ + uint32_t para_up:1; + /** ovf_num : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CHn_INT interrupt will be triggered when channel n overflows for + * (LEDC_OVF_NUM_CHn + 1) times. + */ + uint32_t ovf_num:10; + /** ovf_cnt_en : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel n. + */ + uint32_t ovf_cnt_en:1; + /** ovf_cnt_reset : WT; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel n. + */ + uint32_t ovf_cnt_reset:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} ledc_chn_conf0_reg_t; + +/** Type of chn_conf1 register + * Configuration register 1 for channel n + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** duty_start : R/W/SC; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CHn_CONF1_REG will start to take effect when this + * bit is set to 1. + */ + uint32_t duty_start:1; + }; + uint32_t val; +} ledc_chn_conf1_reg_t; + +/** Type of evt_task_en0 register + * Ledc event task enable bit register0. + */ +typedef union { + struct { + /** evt_duty_chng_end_ch0_en : R/W; bitpos: [0]; default: 0; + * Ledc ch0 duty change end event enable register, write 1 to enable this event. + */ + uint32_t evt_duty_chng_end_ch0_en:1; + /** evt_duty_chng_end_ch1_en : R/W; bitpos: [1]; default: 0; + * Ledc ch1 duty change end event enable register, write 1 to enable this event. + */ + uint32_t evt_duty_chng_end_ch1_en:1; + /** evt_duty_chng_end_ch2_en : R/W; bitpos: [2]; default: 0; + * Ledc ch2 duty change end event enable register, write 1 to enable this event. + */ + uint32_t evt_duty_chng_end_ch2_en:1; + /** evt_duty_chng_end_ch3_en : R/W; bitpos: [3]; default: 0; + * Ledc ch3 duty change end event enable register, write 1 to enable this event. + */ + uint32_t evt_duty_chng_end_ch3_en:1; + /** evt_duty_chng_end_ch4_en : R/W; bitpos: [4]; default: 0; + * Ledc ch4 duty change end event enable register, write 1 to enable this event. + */ + uint32_t evt_duty_chng_end_ch4_en:1; + /** evt_duty_chng_end_ch5_en : R/W; bitpos: [5]; default: 0; + * Ledc ch5 duty change end event enable register, write 1 to enable this event. + */ + uint32_t evt_duty_chng_end_ch5_en:1; + uint32_t reserved_6:2; + /** evt_ovf_cnt_pls_ch0_en : R/W; bitpos: [8]; default: 0; + * Ledc ch0 overflow count pulse event enable register, write 1 to enable this event. + */ + uint32_t evt_ovf_cnt_pls_ch0_en:1; + /** evt_ovf_cnt_pls_ch1_en : R/W; bitpos: [9]; default: 0; + * Ledc ch1 overflow count pulse event enable register, write 1 to enable this event. + */ + uint32_t evt_ovf_cnt_pls_ch1_en:1; + /** evt_ovf_cnt_pls_ch2_en : R/W; bitpos: [10]; default: 0; + * Ledc ch2 overflow count pulse event enable register, write 1 to enable this event. + */ + uint32_t evt_ovf_cnt_pls_ch2_en:1; + /** evt_ovf_cnt_pls_ch3_en : R/W; bitpos: [11]; default: 0; + * Ledc ch3 overflow count pulse event enable register, write 1 to enable this event. + */ + uint32_t evt_ovf_cnt_pls_ch3_en:1; + /** evt_ovf_cnt_pls_ch4_en : R/W; bitpos: [12]; default: 0; + * Ledc ch4 overflow count pulse event enable register, write 1 to enable this event. + */ + uint32_t evt_ovf_cnt_pls_ch4_en:1; + /** evt_ovf_cnt_pls_ch5_en : R/W; bitpos: [13]; default: 0; + * Ledc ch5 overflow count pulse event enable register, write 1 to enable this event. + */ + uint32_t evt_ovf_cnt_pls_ch5_en:1; + uint32_t reserved_14:2; + /** evt_time_ovf_timer0_en : R/W; bitpos: [16]; default: 0; + * Ledc timer0 overflow event enable register, write 1 to enable this event. + */ + uint32_t evt_time_ovf_timer0_en:1; + /** evt_time_ovf_timer1_en : R/W; bitpos: [17]; default: 0; + * Ledc timer1 overflow event enable register, write 1 to enable this event. + */ + uint32_t evt_time_ovf_timer1_en:1; + /** evt_time_ovf_timer2_en : R/W; bitpos: [18]; default: 0; + * Ledc timer2 overflow event enable register, write 1 to enable this event. + */ + uint32_t evt_time_ovf_timer2_en:1; + /** evt_time_ovf_timer3_en : R/W; bitpos: [19]; default: 0; + * Ledc timer3 overflow event enable register, write 1 to enable this event. + */ + uint32_t evt_time_ovf_timer3_en:1; + /** evt_time0_cmp_en : R/W; bitpos: [20]; default: 0; + * Ledc timer0 compare event enable register, write 1 to enable this event. + */ + uint32_t evt_time0_cmp_en:1; + /** evt_time1_cmp_en : R/W; bitpos: [21]; default: 0; + * Ledc timer1 compare event enable register, write 1 to enable this event. + */ + uint32_t evt_time1_cmp_en:1; + /** evt_time2_cmp_en : R/W; bitpos: [22]; default: 0; + * Ledc timer2 compare event enable register, write 1 to enable this event. + */ + uint32_t evt_time2_cmp_en:1; + /** evt_time3_cmp_en : R/W; bitpos: [23]; default: 0; + * Ledc timer3 compare event enable register, write 1 to enable this event. + */ + uint32_t evt_time3_cmp_en:1; + /** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0; + * Ledc ch0 duty scale update task enable register, write 1 to enable this task. + */ + uint32_t task_duty_scale_update_ch0_en:1; + /** task_duty_scale_update_ch1_en : R/W; bitpos: [25]; default: 0; + * Ledc ch1 duty scale update task enable register, write 1 to enable this task. + */ + uint32_t task_duty_scale_update_ch1_en:1; + /** task_duty_scale_update_ch2_en : R/W; bitpos: [26]; default: 0; + * Ledc ch2 duty scale update task enable register, write 1 to enable this task. + */ + uint32_t task_duty_scale_update_ch2_en:1; + /** task_duty_scale_update_ch3_en : R/W; bitpos: [27]; default: 0; + * Ledc ch3 duty scale update task enable register, write 1 to enable this task. + */ + uint32_t task_duty_scale_update_ch3_en:1; + /** task_duty_scale_update_ch4_en : R/W; bitpos: [28]; default: 0; + * Ledc ch4 duty scale update task enable register, write 1 to enable this task. + */ + uint32_t task_duty_scale_update_ch4_en:1; + /** task_duty_scale_update_ch5_en : R/W; bitpos: [29]; default: 0; + * Ledc ch5 duty scale update task enable register, write 1 to enable this task. + */ + uint32_t task_duty_scale_update_ch5_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} ledc_evt_task_en0_reg_t; + +/** Type of evt_task_en1 register + * Ledc event task enable bit register1. + */ +typedef union { + struct { + /** task_timer0_res_update_en : R/W; bitpos: [0]; default: 0; + * Ledc timer0 res update task enable register, write 1 to enable this task. + */ + uint32_t task_timer0_res_update_en:1; + /** task_timer1_res_update_en : R/W; bitpos: [1]; default: 0; + * Ledc timer1 res update task enable register, write 1 to enable this task. + */ + uint32_t task_timer1_res_update_en:1; + /** task_timer2_res_update_en : R/W; bitpos: [2]; default: 0; + * Ledc timer2 res update task enable register, write 1 to enable this task. + */ + uint32_t task_timer2_res_update_en:1; + /** task_timer3_res_update_en : R/W; bitpos: [3]; default: 0; + * Ledc timer3 res update task enable register, write 1 to enable this task. + */ + uint32_t task_timer3_res_update_en:1; + /** task_timer0_cap_en : R/W; bitpos: [4]; default: 0; + * Ledc timer0 capture task enable register, write 1 to enable this task. + */ + uint32_t task_timer0_cap_en:1; + /** task_timer1_cap_en : R/W; bitpos: [5]; default: 0; + * Ledc timer1 capture task enable register, write 1 to enable this task. + */ + uint32_t task_timer1_cap_en:1; + /** task_timer2_cap_en : R/W; bitpos: [6]; default: 0; + * Ledc timer2 capture task enable register, write 1 to enable this task. + */ + uint32_t task_timer2_cap_en:1; + /** task_timer3_cap_en : R/W; bitpos: [7]; default: 0; + * Ledc timer3 capture task enable register, write 1 to enable this task. + */ + uint32_t task_timer3_cap_en:1; + /** task_sig_out_dis_ch0_en : R/W; bitpos: [8]; default: 0; + * Ledc ch0 signal out disable task enable register, write 1 to enable this task. + */ + uint32_t task_sig_out_dis_ch0_en:1; + /** task_sig_out_dis_ch1_en : R/W; bitpos: [9]; default: 0; + * Ledc ch1 signal out disable task enable register, write 1 to enable this task. + */ + uint32_t task_sig_out_dis_ch1_en:1; + /** task_sig_out_dis_ch2_en : R/W; bitpos: [10]; default: 0; + * Ledc ch2 signal out disable task enable register, write 1 to enable this task. + */ + uint32_t task_sig_out_dis_ch2_en:1; + /** task_sig_out_dis_ch3_en : R/W; bitpos: [11]; default: 0; + * Ledc ch3 signal out disable task enable register, write 1 to enable this task. + */ + uint32_t task_sig_out_dis_ch3_en:1; + /** task_sig_out_dis_ch4_en : R/W; bitpos: [12]; default: 0; + * Ledc ch4 signal out disable task enable register, write 1 to enable this task. + */ + uint32_t task_sig_out_dis_ch4_en:1; + /** task_sig_out_dis_ch5_en : R/W; bitpos: [13]; default: 0; + * Ledc ch5 signal out disable task enable register, write 1 to enable this task. + */ + uint32_t task_sig_out_dis_ch5_en:1; + uint32_t reserved_14:2; + /** task_ovf_cnt_rst_ch0_en : R/W; bitpos: [16]; default: 0; + * Ledc ch0 overflow count reset task enable register, write 1 to enable this task. + */ + uint32_t task_ovf_cnt_rst_ch0_en:1; + /** task_ovf_cnt_rst_ch1_en : R/W; bitpos: [17]; default: 0; + * Ledc ch1 overflow count reset task enable register, write 1 to enable this task. + */ + uint32_t task_ovf_cnt_rst_ch1_en:1; + /** task_ovf_cnt_rst_ch2_en : R/W; bitpos: [18]; default: 0; + * Ledc ch2 overflow count reset task enable register, write 1 to enable this task. + */ + uint32_t task_ovf_cnt_rst_ch2_en:1; + /** task_ovf_cnt_rst_ch3_en : R/W; bitpos: [19]; default: 0; + * Ledc ch3 overflow count reset task enable register, write 1 to enable this task. + */ + uint32_t task_ovf_cnt_rst_ch3_en:1; + /** task_ovf_cnt_rst_ch4_en : R/W; bitpos: [20]; default: 0; + * Ledc ch4 overflow count reset task enable register, write 1 to enable this task. + */ + uint32_t task_ovf_cnt_rst_ch4_en:1; + /** task_ovf_cnt_rst_ch5_en : R/W; bitpos: [21]; default: 0; + * Ledc ch5 overflow count reset task enable register, write 1 to enable this task. + */ + uint32_t task_ovf_cnt_rst_ch5_en:1; + uint32_t reserved_22:2; + /** task_timer0_rst_en : R/W; bitpos: [24]; default: 0; + * Ledc timer0 reset task enable register, write 1 to enable this task. + */ + uint32_t task_timer0_rst_en:1; + /** task_timer1_rst_en : R/W; bitpos: [25]; default: 0; + * Ledc timer1 reset task enable register, write 1 to enable this task. + */ + uint32_t task_timer1_rst_en:1; + /** task_timer2_rst_en : R/W; bitpos: [26]; default: 0; + * Ledc timer2 reset task enable register, write 1 to enable this task. + */ + uint32_t task_timer2_rst_en:1; + /** task_timer3_rst_en : R/W; bitpos: [27]; default: 0; + * Ledc timer3 reset task enable register, write 1 to enable this task. + */ + uint32_t task_timer3_rst_en:1; + /** task_timer0_pause_resume_en : R/W; bitpos: [28]; default: 0; + * Ledc timer0 pause resume task enable register, write 1 to enable this task. + */ + uint32_t task_timer0_pause_resume_en:1; + /** task_timer1_pause_resume_en : R/W; bitpos: [29]; default: 0; + * Ledc timer1 pause resume task enable register, write 1 to enable this task. + */ + uint32_t task_timer1_pause_resume_en:1; + /** task_timer2_pause_resume_en : R/W; bitpos: [30]; default: 0; + * Ledc timer2 pause resume task enable register, write 1 to enable this task. + */ + uint32_t task_timer2_pause_resume_en:1; + /** task_timer3_pause_resume_en : R/W; bitpos: [31]; default: 0; + * Ledc timer3 pause resume task enable register, write 1 to enable this task. + */ + uint32_t task_timer3_pause_resume_en:1; + }; + uint32_t val; +} ledc_evt_task_en1_reg_t; + +/** Type of evt_task_en2 register + * Ledc event task enable bit register2. + */ +typedef union { + struct { + /** task_gamma_restart_ch0_en : R/W; bitpos: [0]; default: 0; + * Ledc ch0 gamma restart task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_restart_ch0_en:1; + /** task_gamma_restart_ch1_en : R/W; bitpos: [1]; default: 0; + * Ledc ch1 gamma restart task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_restart_ch1_en:1; + /** task_gamma_restart_ch2_en : R/W; bitpos: [2]; default: 0; + * Ledc ch2 gamma restart task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_restart_ch2_en:1; + /** task_gamma_restart_ch3_en : R/W; bitpos: [3]; default: 0; + * Ledc ch3 gamma restart task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_restart_ch3_en:1; + /** task_gamma_restart_ch4_en : R/W; bitpos: [4]; default: 0; + * Ledc ch4 gamma restart task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_restart_ch4_en:1; + /** task_gamma_restart_ch5_en : R/W; bitpos: [5]; default: 0; + * Ledc ch5 gamma restart task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_restart_ch5_en:1; + uint32_t reserved_6:2; + /** task_gamma_pause_ch0_en : R/W; bitpos: [8]; default: 0; + * Ledc ch0 gamma pause task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_pause_ch0_en:1; + /** task_gamma_pause_ch1_en : R/W; bitpos: [9]; default: 0; + * Ledc ch1 gamma pause task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_pause_ch1_en:1; + /** task_gamma_pause_ch2_en : R/W; bitpos: [10]; default: 0; + * Ledc ch2 gamma pause task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_pause_ch2_en:1; + /** task_gamma_pause_ch3_en : R/W; bitpos: [11]; default: 0; + * Ledc ch3 gamma pause task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_pause_ch3_en:1; + /** task_gamma_pause_ch4_en : R/W; bitpos: [12]; default: 0; + * Ledc ch4 gamma pause task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_pause_ch4_en:1; + /** task_gamma_pause_ch5_en : R/W; bitpos: [13]; default: 0; + * Ledc ch5 gamma pause task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_pause_ch5_en:1; + uint32_t reserved_14:2; + /** task_gamma_resume_ch0_en : R/W; bitpos: [16]; default: 0; + * Ledc ch0 gamma resume task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_resume_ch0_en:1; + /** task_gamma_resume_ch1_en : R/W; bitpos: [17]; default: 0; + * Ledc ch1 gamma resume task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_resume_ch1_en:1; + /** task_gamma_resume_ch2_en : R/W; bitpos: [18]; default: 0; + * Ledc ch2 gamma resume task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_resume_ch2_en:1; + /** task_gamma_resume_ch3_en : R/W; bitpos: [19]; default: 0; + * Ledc ch3 gamma resume task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_resume_ch3_en:1; + /** task_gamma_resume_ch4_en : R/W; bitpos: [20]; default: 0; + * Ledc ch4 gamma resume task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_resume_ch4_en:1; + /** task_gamma_resume_ch5_en : R/W; bitpos: [21]; default: 0; + * Ledc ch5 gamma resume task enable register, write 1 to enable this task. + */ + uint32_t task_gamma_resume_ch5_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} ledc_evt_task_en2_reg_t; + +/** Type of timern_cmp register + * Ledc timern compare value register. + */ +typedef union { + struct { + /** cmp : R/W; bitpos: [19:0]; default: 0; + * This register stores ledc timern compare value. + */ + uint32_t cmp:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_cmp_reg_t; + +/** Type of timern_cnt_cap register + * Ledc timern count value capture register. + */ +typedef union { + struct { + /** cnt_cap : RO; bitpos: [19:0]; default: 0; + * This register stores ledc timern count value. + */ + uint32_t cnt_cap:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_cnt_cap_reg_t; + +/** Type of conf register + * Global ledc configuration register + */ +typedef union { + struct { + /** apb_clk_sel : R/W; bitpos: [1:0]; default: 0; + * This bit is used to select clock source for the 4 timers . + * + * 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK + */ + uint32_t apb_clk_sel:2; + /** gamma_ram_clk_en_ch0 : R/W; bitpos: [2]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ + uint32_t gamma_ram_clk_en_ch0:1; + /** gamma_ram_clk_en_ch1 : R/W; bitpos: [3]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ + uint32_t gamma_ram_clk_en_ch1:1; + /** gamma_ram_clk_en_ch2 : R/W; bitpos: [4]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ + uint32_t gamma_ram_clk_en_ch2:1; + /** gamma_ram_clk_en_ch3 : R/W; bitpos: [5]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ + uint32_t gamma_ram_clk_en_ch3:1; + /** gamma_ram_clk_en_ch4 : R/W; bitpos: [6]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ + uint32_t gamma_ram_clk_en_ch4:1; + /** gamma_ram_clk_en_ch5 : R/W; bitpos: [7]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application + * writes or read gamma ram. + */ + uint32_t gamma_ram_clk_en_ch5:1; + uint32_t reserved_8:23; + /** clk_en : R/W; bitpos: [31]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + }; + uint32_t val; +} ledc_conf_reg_t; + + +/** Group: Hpoint Register */ +/** Type of chn_hpoint register + * High point register for channel n + */ +typedef union { + struct { + /** hpoint : R/W; bitpos: [19:0]; default: 0; + * The output value changes to high when the selected timers has reached the value + * specified by this register. + */ + uint32_t hpoint:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_chn_hpoint_reg_t; + + +/** Group: Duty Cycle Register */ +/** Type of chn_duty register + * Initial duty cycle for channel n + */ +typedef union { + struct { + /** duty : R/W; bitpos: [24:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the Lpoint. + */ + uint32_t duty:25; + uint32_t reserved_25:7; + }; + uint32_t val; +} ledc_chn_duty_reg_t; + +/** Type of chn_duty_r register + * Current duty cycle for channel n + */ +typedef union { + struct { + /** duty_r : RO; bitpos: [24:0]; default: 0; + * This register stores the current duty of output signal on channel n. + */ + uint32_t duty_r:25; + uint32_t reserved_25:7; + }; + uint32_t val; +} ledc_chn_duty_r_reg_t; + + +/** Group: Timer Register */ +/** Type of timern_conf register + * Timer n configuration + */ +typedef union { + struct { + /** duty_res : R/W; bitpos: [4:0]; default: 0; + * This register is used to control the range of the counter in timer n. + */ + uint32_t duty_res:5; + /** clk_div : R/W; bitpos: [22:5]; default: 0; + * This register is used to configure the divisor for the divider in timer n. + * + * The least significant eight bits represent the fractional part. + */ + uint32_t clk_div:18; + /** pause : R/W; bitpos: [23]; default: 0; + * This bit is used to suspend the counter in timer n. + */ + uint32_t pause:1; + /** rst : R/W; bitpos: [24]; default: 1; + * This bit is used to reset timer n. The counter will show 0 after reset. + */ + uint32_t rst:1; + /** tick_sel : R/W; bitpos: [25]; default: 0; + * This bit is used to select clock for timer n. When this bit is set to 1 + * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. + * + * 1'h0: SLOW_CLK 1'h1: REF_TICK + */ + uint32_t tick_sel:1; + /** para_up : WT; bitpos: [26]; default: 0; + * Set this bit to update LEDC_CLK_DIV_TIMERn and LEDC_TIMERn_DUTY_RES. + */ + uint32_t para_up:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} ledc_timerx_conf_reg_t; + +/** Type of timern_value register + * Timer n current counter value + */ +typedef union { + struct { + /** timer_cnt : RO; bitpos: [19:0]; default: 0; + * This register stores the current counter value of timer n. + */ + uint32_t timer_cnt:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timerx_value_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** timer0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * Triggered when the timer0 has reached its maximum counter value. + */ + uint32_t timer0_ovf_int_raw:1; + /** timer1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * Triggered when the timer1 has reached its maximum counter value. + */ + uint32_t timer1_ovf_int_raw:1; + /** timer2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * Triggered when the timer2 has reached its maximum counter value. + */ + uint32_t timer2_ovf_int_raw:1; + /** timer3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * Triggered when the timer3 has reached its maximum counter value. + */ + uint32_t timer3_ovf_int_raw:1; + /** duty_chng_end_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * Interrupt raw bit for channel 0. Triggered when the gradual change of duty has + * finished. + */ + uint32_t duty_chng_end_ch0_int_raw:1; + /** duty_chng_end_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * Interrupt raw bit for channel 1. Triggered when the gradual change of duty has + * finished. + */ + uint32_t duty_chng_end_ch1_int_raw:1; + /** duty_chng_end_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * Interrupt raw bit for channel 2. Triggered when the gradual change of duty has + * finished. + */ + uint32_t duty_chng_end_ch2_int_raw:1; + /** duty_chng_end_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * Interrupt raw bit for channel 3. Triggered when the gradual change of duty has + * finished. + */ + uint32_t duty_chng_end_ch3_int_raw:1; + /** duty_chng_end_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * Interrupt raw bit for channel 4. Triggered when the gradual change of duty has + * finished. + */ + uint32_t duty_chng_end_ch4_int_raw:1; + /** duty_chng_end_ch5_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * Interrupt raw bit for channel 5. Triggered when the gradual change of duty has + * finished. + */ + uint32_t duty_chng_end_ch5_int_raw:1; + uint32_t reserved_10:2; + /** ovf_cnt_ch0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH0. + */ + uint32_t ovf_cnt_ch0_int_raw:1; + /** ovf_cnt_ch1_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH1. + */ + uint32_t ovf_cnt_ch1_int_raw:1; + /** ovf_cnt_ch2_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH2. + */ + uint32_t ovf_cnt_ch2_int_raw:1; + /** ovf_cnt_ch3_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH3. + */ + uint32_t ovf_cnt_ch3_int_raw:1; + /** ovf_cnt_ch4_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH4. + */ + uint32_t ovf_cnt_ch4_int_raw:1; + /** ovf_cnt_ch5_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value + * specified by LEDC_OVF_NUM_CH5. + */ + uint32_t ovf_cnt_ch5_int_raw:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} ledc_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** timer0_ovf_int_st : RO; bitpos: [0]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when + * LEDC_TIMER0_OVF_INT_ENA is set to 1. + */ + uint32_t timer0_ovf_int_st:1; + /** timer1_ovf_int_st : RO; bitpos: [1]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when + * LEDC_TIMER1_OVF_INT_ENA is set to 1. + */ + uint32_t timer1_ovf_int_st:1; + /** timer2_ovf_int_st : RO; bitpos: [2]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when + * LEDC_TIMER2_OVF_INT_ENA is set to 1. + */ + uint32_t timer2_ovf_int_st:1; + /** timer3_ovf_int_st : RO; bitpos: [3]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when + * LEDC_TIMER3_OVF_INT_ENA is set to 1. + */ + uint32_t timer3_ovf_int_st:1; + /** duty_chng_end_ch0_int_st : RO; bitpos: [4]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT + * interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch0_int_st:1; + /** duty_chng_end_ch1_int_st : RO; bitpos: [5]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT + * interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch1_int_st:1; + /** duty_chng_end_ch2_int_st : RO; bitpos: [6]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT + * interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch2_int_st:1; + /** duty_chng_end_ch3_int_st : RO; bitpos: [7]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT + * interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch3_int_st:1; + /** duty_chng_end_ch4_int_st : RO; bitpos: [8]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT + * interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch4_int_st:1; + /** duty_chng_end_ch5_int_st : RO; bitpos: [9]; default: 0; + * This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT + * interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch5_int_st:1; + uint32_t reserved_10:2; + /** ovf_cnt_ch0_int_st : RO; bitpos: [12]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when + * LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch0_int_st:1; + /** ovf_cnt_ch1_int_st : RO; bitpos: [13]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when + * LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch1_int_st:1; + /** ovf_cnt_ch2_int_st : RO; bitpos: [14]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when + * LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch2_int_st:1; + /** ovf_cnt_ch3_int_st : RO; bitpos: [15]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when + * LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch3_int_st:1; + /** ovf_cnt_ch4_int_st : RO; bitpos: [16]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when + * LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch4_int_st:1; + /** ovf_cnt_ch5_int_st : RO; bitpos: [17]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when + * LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch5_int_st:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} ledc_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** timer0_ovf_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. + */ + uint32_t timer0_ovf_int_ena:1; + /** timer1_ovf_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. + */ + uint32_t timer1_ovf_int_ena:1; + /** timer2_ovf_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. + */ + uint32_t timer2_ovf_int_ena:1; + /** timer3_ovf_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. + */ + uint32_t timer3_ovf_int_ena:1; + /** duty_chng_end_ch0_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + */ + uint32_t duty_chng_end_ch0_int_ena:1; + /** duty_chng_end_ch1_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + */ + uint32_t duty_chng_end_ch1_int_ena:1; + /** duty_chng_end_ch2_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + */ + uint32_t duty_chng_end_ch2_int_ena:1; + /** duty_chng_end_ch3_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + */ + uint32_t duty_chng_end_ch3_int_ena:1; + /** duty_chng_end_ch4_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + */ + uint32_t duty_chng_end_ch4_int_ena:1; + /** duty_chng_end_ch5_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + */ + uint32_t duty_chng_end_ch5_int_ena:1; + uint32_t reserved_10:2; + /** ovf_cnt_ch0_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. + */ + uint32_t ovf_cnt_ch0_int_ena:1; + /** ovf_cnt_ch1_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. + */ + uint32_t ovf_cnt_ch1_int_ena:1; + /** ovf_cnt_ch2_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. + */ + uint32_t ovf_cnt_ch2_int_ena:1; + /** ovf_cnt_ch3_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. + */ + uint32_t ovf_cnt_ch3_int_ena:1; + /** ovf_cnt_ch4_int_ena : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. + */ + uint32_t ovf_cnt_ch4_int_ena:1; + /** ovf_cnt_ch5_int_ena : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. + */ + uint32_t ovf_cnt_ch5_int_ena:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} ledc_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** timer0_ovf_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. + */ + uint32_t timer0_ovf_int_clr:1; + /** timer1_ovf_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. + */ + uint32_t timer1_ovf_int_clr:1; + /** timer2_ovf_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. + */ + uint32_t timer2_ovf_int_clr:1; + /** timer3_ovf_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. + */ + uint32_t timer3_ovf_int_clr:1; + /** duty_chng_end_ch0_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + */ + uint32_t duty_chng_end_ch0_int_clr:1; + /** duty_chng_end_ch1_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + */ + uint32_t duty_chng_end_ch1_int_clr:1; + /** duty_chng_end_ch2_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + */ + uint32_t duty_chng_end_ch2_int_clr:1; + /** duty_chng_end_ch3_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + */ + uint32_t duty_chng_end_ch3_int_clr:1; + /** duty_chng_end_ch4_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + */ + uint32_t duty_chng_end_ch4_int_clr:1; + /** duty_chng_end_ch5_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + */ + uint32_t duty_chng_end_ch5_int_clr:1; + uint32_t reserved_10:2; + /** ovf_cnt_ch0_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. + */ + uint32_t ovf_cnt_ch0_int_clr:1; + /** ovf_cnt_ch1_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. + */ + uint32_t ovf_cnt_ch1_int_clr:1; + /** ovf_cnt_ch2_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. + */ + uint32_t ovf_cnt_ch2_int_clr:1; + /** ovf_cnt_ch3_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. + */ + uint32_t ovf_cnt_ch3_int_clr:1; + /** ovf_cnt_ch4_int_clr : WT; bitpos: [16]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. + */ + uint32_t ovf_cnt_ch4_int_clr:1; + /** ovf_cnt_ch5_int_clr : WT; bitpos: [17]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. + */ + uint32_t ovf_cnt_ch5_int_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} ledc_int_clr_reg_t; + + +/** Group: Gamma RAM Register */ +/** Type of chn_gamma_wr register + * Ledc chn gamma ram write register. + */ +typedef union { + struct { + /** gamma_duty_inc : R/W; bitpos: [0]; default: 0; + * Ledc chn gamma duty inc of current ram write address.This register is used to + * increase or decrease the duty of output signal on channel n. + * + * 1: Increase 0: Decrease. + */ + uint32_t gamma_duty_inc:1; + /** gamma_duty_cycle : R/W; bitpos: [10:1]; default: 0; + * Ledc chn gamma duty cycle of current ram write address.The duty will change every + * LEDC_CHn_GAMMA_DUTY_CYCLE on channel n. + */ + uint32_t gamma_duty_cycle:10; + /** gamma_scale : R/W; bitpos: [20:11]; default: 0; + * Ledc chn gamma scale of current ram write address.This register is used to + * configure the changing step scale of duty on channel n. + */ + uint32_t gamma_scale:10; + /** gamma_duty_num : R/W; bitpos: [30:21]; default: 0; + * Ledc chn gamma duty num of current ram write address.This register is used to + * control the number of times the duty cycle will be changed. + */ + uint32_t gamma_duty_num:10; + uint32_t reserved_31:1; + }; + uint32_t val; +} ledc_chn_gamma_wr_reg_t; + +/** Type of chn_gamma_wr_addr register + * Ledc chn gamma ram write address register. + */ +typedef union { + struct { + /** gamma_wr_addr : R/W; bitpos: [3:0]; default: 0; + * Ledc chn gamma ram write address. + */ + uint32_t gamma_wr_addr:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ledc_chn_gamma_wr_addr_reg_t; + +/** Type of chn_gamma_rd_addr register + * Ledc chn gamma ram read address register. + */ +typedef union { + struct { + /** gamma_rd_addr : R/W; bitpos: [3:0]; default: 0; + * Ledc chn gamma ram read address. + */ + uint32_t gamma_rd_addr:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ledc_chn_gamma_rd_addr_reg_t; + +/** Type of chn_gamma_rd_data register + * Ledc chn gamma ram read data register. + */ +typedef union { + struct { + /** gamma_rd_data : RO; bitpos: [30:0]; default: 0; + * Ledc chn gamma ram read data. + */ + uint32_t gamma_rd_data:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} ledc_chn_gamma_rd_data_reg_t; + + +/** Group: Gamma Config Register */ +/** Type of chn_gamma_conf register + * Ledc chn gamma config register. + */ +typedef union { + struct { + /** gamma_entry_num : R/W; bitpos: [4:0]; default: 0; + * Ledc chn gamma entry num. + */ + uint32_t gamma_entry_num:5; + /** gamma_pause : WT; bitpos: [5]; default: 0; + * Ledc chn gamma pause, write 1 to pause. + */ + uint32_t gamma_pause:1; + /** gamma_resume : WT; bitpos: [6]; default: 0; + * Ledc chn gamma resume, write 1 to resume. + */ + uint32_t gamma_resume:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} ledc_chn_gamma_conf_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** ledc_date : R/W; bitpos: [27:0]; default: 34672976; + * This is the version control register. + */ + uint32_t ledc_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} ledc_date_reg_t; + +typedef struct { + volatile ledc_chn_conf0_reg_t conf0; + volatile ledc_chn_hpoint_reg_t hpoint; + volatile ledc_chn_duty_reg_t duty; + volatile ledc_chn_conf1_reg_t conf1; + volatile ledc_chn_duty_r_reg_t duty_rd; +} ledc_chn_reg_t; + +typedef struct { + volatile ledc_chn_reg_t channel[6]; +} ledc_ch_group_reg_t; + +typedef struct { + volatile ledc_timerx_conf_reg_t conf; + volatile ledc_timerx_value_reg_t value; +} ledc_timerx_reg_t; + +typedef struct { + volatile ledc_timerx_reg_t timer[4]; +} ledc_timer_group_reg_t; + +typedef struct { + volatile ledc_chn_gamma_wr_reg_t wr; + volatile ledc_chn_gamma_wr_addr_reg_t wr_addr; + volatile ledc_chn_gamma_rd_addr_reg_t rd_addr; + volatile ledc_chn_gamma_rd_data_reg_t rd_data; +} ledc_chn_gamma_reg_t; + +typedef struct { + volatile ledc_chn_gamma_reg_t channel[6]; +} ledc_ch_gamma_group_reg_t; + +typedef struct { + volatile ledc_chn_gamma_conf_reg_t gamma_conf[6]; +} ledc_ch_gamma_conf_group_reg_t; + +typedef struct { + volatile ledc_timern_cmp_reg_t cmp[4]; +} ledc_timer_cmp_group_reg_t; + +typedef struct { + volatile ledc_timern_cnt_cap_reg_t cnt_cap[4]; +} ledc_timer_cnt_cap_group_reg_t; + +typedef struct ledc_dev_t { + volatile ledc_ch_group_reg_t channel_group[1]; + uint32_t reserved_078[10]; + volatile ledc_timer_group_reg_t timer_group[1]; + volatile ledc_int_raw_reg_t int_raw; + volatile ledc_int_st_reg_t int_st; + volatile ledc_int_ena_reg_t int_ena; + volatile ledc_int_clr_reg_t int_clr; + uint32_t reserved_0d0[12]; + volatile ledc_ch_gamma_group_reg_t channel_gamma_group[1]; + uint32_t reserved_160[8]; + volatile ledc_ch_gamma_conf_group_reg_t channel_gamma_conf_group[1]; + uint32_t reserved_198[2]; + volatile ledc_evt_task_en0_reg_t evt_task_en0; + volatile ledc_evt_task_en1_reg_t evt_task_en1; + volatile ledc_evt_task_en2_reg_t evt_task_en2; + uint32_t reserved_1ac; + volatile ledc_timer_cmp_group_reg_t timer_cmp_group[1]; + volatile ledc_timer_cnt_cap_group_reg_t timer_cnt_cap_group[1]; + uint32_t reserved_1d0[8]; + volatile ledc_conf_reg_t conf; + uint32_t reserved_1f4[2]; + volatile ledc_date_reg_t date; +} ledc_dev_t; + +extern ledc_dev_t LEDC; + +#ifndef __cplusplus +_Static_assert(sizeof(ledc_dev_t) == 0x200, "Invalid size of ledc_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_analog_peri_reg.h b/components/soc/esp32c6/include/soc/lp_analog_peri_reg.h new file mode 100644 index 0000000000..25848608d6 --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_analog_peri_reg.h @@ -0,0 +1,232 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNTL_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x0) +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA (BIT(6)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S 6 +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_PD_RF_ENA (BIT(7)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_PD_RF_ENA_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_PD_RF_ENA_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_PD_RF_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_PD_RF_ENA_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_PD_RF_ENA_S 7 +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_WAIT 0x000003FFU +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_WAIT_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_WAIT_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_WAIT_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_WAIT_V 0x000003FFU +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_WAIT_S 8 +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_WAIT 0x000003FFU +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_WAIT_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_WAIT_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_WAIT_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_WAIT_V 0x000003FFU +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_WAIT_S 18 +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNT_CLR (BIT(28)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNT_CLR_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNT_CLR_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNT_CLR_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNT_CLR_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNT_CLR_S 28 +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_ENA (BIT(29)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_ENA_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_ENA_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_ENA_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_ENA_S 29 +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_SEL (BIT(30)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_SEL_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_SEL_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_SEL_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_SEL_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_SEL_S 30 +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_ENA (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_ENA_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_ENA_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_ENA_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_ENA_S 31 + +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x4) +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA_S 31 + +/** LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x8) +/** LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_M (LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_V << LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_S 31 + +/** LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG (DR_REG_LP_ANALOG_PERI_BASE + 0xc) +/** LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA 0xFFFFFFFFU +#define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_M (LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_V << LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_V 0xFFFFFFFFU +#define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_S 0 + +#define LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST BIT(0) +#define LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST BIT(1) +#define LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST BIT(2) + +/** LP_ANALOG_PERI_LP_ANA_INT_RAW_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_INT_RAW_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x10) +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_RAW (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_RAW_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_RAW_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_RAW_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_RAW_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_RAW_S 31 + +/** LP_ANALOG_PERI_LP_ANA_INT_ST_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_INT_ST_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x14) +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ST (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ST_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ST_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ST_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ST_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ST_S 31 + +/** LP_ANALOG_PERI_LP_ANA_INT_ENA_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_INT_ENA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x18) +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ENA (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ENA_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ENA_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ENA_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ENA_S 31 + +/** LP_ANALOG_PERI_LP_ANA_INT_CLR_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_INT_CLR_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1c) +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_CLR (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_CLR_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_CLR_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_CLR_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_CLR_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_CLR_S 31 + +/** LP_ANALOG_PERI_LP_ANA_LP_INT_RAW_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_LP_INT_RAW_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x20) +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_RAW (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_RAW_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_RAW_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_RAW_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_RAW_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_RAW_S 31 + +/** LP_ANALOG_PERI_LP_ANA_LP_INT_ST_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_LP_INT_ST_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x24) +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ST (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ST_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ST_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ST_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ST_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ST_S 31 + +/** LP_ANALOG_PERI_LP_ANA_LP_INT_ENA_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_LP_INT_ENA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x28) +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA_S 31 + +/** LP_ANALOG_PERI_LP_ANA_LP_INT_CLR_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_LP_INT_CLR_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x2c) +/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR_S) +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR_S 31 + +/** LP_ANALOG_PERI_LP_ANA_DATE_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_DATE_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x3fc) +/** LP_ANALOG_PERI_LP_ANA_LP_ANALOG_PERI_LP_ANA_DATE : R/W; bitpos: [30:0]; default: 35660384; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_LP_ANALOG_PERI_LP_ANA_DATE 0x7FFFFFFFU +#define LP_ANALOG_PERI_LP_ANA_LP_ANALOG_PERI_LP_ANA_DATE_M (LP_ANALOG_PERI_LP_ANA_LP_ANALOG_PERI_LP_ANA_DATE_V << LP_ANALOG_PERI_LP_ANA_LP_ANALOG_PERI_LP_ANA_DATE_S) +#define LP_ANALOG_PERI_LP_ANA_LP_ANALOG_PERI_LP_ANA_DATE_V 0x7FFFFFFFU +#define LP_ANALOG_PERI_LP_ANA_LP_ANALOG_PERI_LP_ANA_DATE_S 0 +/** LP_ANALOG_PERI_LP_ANA_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANA_CLK_EN (BIT(31)) +#define LP_ANALOG_PERI_LP_ANA_CLK_EN_M (LP_ANALOG_PERI_LP_ANA_CLK_EN_V << LP_ANALOG_PERI_LP_ANA_CLK_EN_S) +#define LP_ANALOG_PERI_LP_ANA_CLK_EN_V 0x00000001U +#define LP_ANALOG_PERI_LP_ANA_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_analog_peri_struct.h b/components/soc/esp32c6/include/soc/lp_analog_peri_struct.h new file mode 100644 index 0000000000..92fda49f23 --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_analog_peri_struct.h @@ -0,0 +1,252 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of bod_mode0_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** bod_mode0_close_flash_ena : R/W; bitpos: [6]; default: 0; + * need_des + */ + uint32_t bod_mode0_close_flash_ena:1; + /** bod_mode0_pd_rf_ena : R/W; bitpos: [7]; default: 0; + * need_des + */ + uint32_t bod_mode0_pd_rf_ena:1; + /** bod_mode0_intr_wait : R/W; bitpos: [17:8]; default: 1; + * need_des + */ + uint32_t bod_mode0_intr_wait:10; + /** bod_mode0_reset_wait : R/W; bitpos: [27:18]; default: 1023; + * need_des + */ + uint32_t bod_mode0_reset_wait:10; + /** bod_mode0_cnt_clr : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t bod_mode0_cnt_clr:1; + /** bod_mode0_intr_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t bod_mode0_intr_ena:1; + /** bod_mode0_reset_sel : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t bod_mode0_reset_sel:1; + /** bod_mode0_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_reset_ena:1; + }; + uint32_t val; +} lp_ana_bod_mode0_cntl_reg_t; + +/** Type of bod_mode1_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode1_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode1_reset_ena:1; + }; + uint32_t val; +} lp_ana_bod_mode1_cntl_reg_t; + +/** Type of ck_glitch_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** ck_glitch_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ck_glitch_reset_ena:1; + }; + uint32_t val; +} lp_ana_ck_glitch_cntl_reg_t; + +/** Type of fib_enable register + * need_des + */ +typedef union { + struct { + /** ana_fib_ena : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t ana_fib_ena:32; + }; + uint32_t val; +} lp_ana_fib_enable_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0 : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0:1; + }; + uint32_t val; +} lp_ana_int_raw_reg_t; + +/** Type of int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0 : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0:1; + }; + uint32_t val; +} lp_ana_int_st_reg_t; + +/** Type of int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0 : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0:1; + }; + uint32_t val; +} lp_ana_int_ena_reg_t; + +/** Type of int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0 : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0:1; + }; + uint32_t val; +} lp_ana_int_clr_reg_t; + +/** Type of lp_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0 : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0:1; + }; + uint32_t val; +} lp_ana_lp_int_raw_reg_t; + +/** Type of lp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0 : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0:1; + }; + uint32_t val; +} lp_ana_lp_int_st_reg_t; + +/** Type of lp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0 : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0:1; + }; + uint32_t val; +} lp_ana_lp_int_ena_reg_t; + +/** Type of lp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0 : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0:1; + }; + uint32_t val; +} lp_ana_lp_int_clr_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** lp_ana_date : R/W; bitpos: [30:0]; default: 35660384; + * need_des + */ + uint32_t lp_ana_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_ana_date_reg_t; + + +typedef struct lp_ana_dev_t { + volatile lp_ana_bod_mode0_cntl_reg_t bod_mode0_cntl; + volatile lp_ana_bod_mode1_cntl_reg_t bod_mode1_cntl; + volatile lp_ana_ck_glitch_cntl_reg_t ck_glitch_cntl; + volatile lp_ana_fib_enable_reg_t fib_enable; + volatile lp_ana_int_raw_reg_t int_raw; + volatile lp_ana_int_st_reg_t int_st; + volatile lp_ana_int_ena_reg_t int_ena; + volatile lp_ana_int_clr_reg_t int_clr; + volatile lp_ana_lp_int_raw_reg_t lp_int_raw; + volatile lp_ana_lp_int_st_reg_t lp_int_st; + volatile lp_ana_lp_int_ena_reg_t lp_int_ena; + volatile lp_ana_lp_int_clr_reg_t lp_int_clr; + uint32_t reserved_030[243]; + volatile lp_ana_date_reg_t date; +} lp_ana_dev_t; + +extern lp_ana_dev_t LP_ANA_PERI; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_ana_dev_t) == 0x400, "Invalid size of lp_ana_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_aon_reg.h b/components/soc/esp32c6/include/soc/lp_aon_reg.h new file mode 100644 index 0000000000..41a015e82f --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_aon_reg.h @@ -0,0 +1,418 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_AON_STORE0_REG register + * need_des + */ +#define LP_AON_STORE0_REG (DR_REG_LP_AON_BASE + 0x0) +/** LP_AON_STORE0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_STORE0 0xFFFFFFFFU +#define LP_AON_STORE0_M (LP_AON_STORE0_V << LP_AON_STORE0_S) +#define LP_AON_STORE0_V 0xFFFFFFFFU +#define LP_AON_STORE0_S 0 + +/** LP_AON_STORE1_REG register + * need_des + */ +#define LP_AON_STORE1_REG (DR_REG_LP_AON_BASE + 0x4) +/** LP_AON_STORE1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_STORE1 0xFFFFFFFFU +#define LP_AON_STORE1_M (LP_AON_STORE1_V << LP_AON_STORE1_S) +#define LP_AON_STORE1_V 0xFFFFFFFFU +#define LP_AON_STORE1_S 0 + +/** LP_AON_STORE2_REG register + * need_des + */ +#define LP_AON_STORE2_REG (DR_REG_LP_AON_BASE + 0x8) +/** LP_AON_STORE2 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_STORE2 0xFFFFFFFFU +#define LP_AON_STORE2_M (LP_AON_STORE2_V << LP_AON_STORE2_S) +#define LP_AON_STORE2_V 0xFFFFFFFFU +#define LP_AON_STORE2_S 0 + +/** LP_AON_STORE3_REG register + * need_des + */ +#define LP_AON_STORE3_REG (DR_REG_LP_AON_BASE + 0xc) +/** LP_AON_STORE3 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_STORE3 0xFFFFFFFFU +#define LP_AON_STORE3_M (LP_AON_STORE3_V << LP_AON_STORE3_S) +#define LP_AON_STORE3_V 0xFFFFFFFFU +#define LP_AON_STORE3_S 0 + +/** LP_AON_STORE4_REG register + * need_des + */ +#define LP_AON_STORE4_REG (DR_REG_LP_AON_BASE + 0x10) +/** LP_AON_STORE4 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_STORE4 0xFFFFFFFFU +#define LP_AON_STORE4_M (LP_AON_STORE4_V << LP_AON_STORE4_S) +#define LP_AON_STORE4_V 0xFFFFFFFFU +#define LP_AON_STORE4_S 0 + +/** LP_AON_STORE5_REG register + * need_des + */ +#define LP_AON_STORE5_REG (DR_REG_LP_AON_BASE + 0x14) +/** LP_AON_STORE5 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_STORE5 0xFFFFFFFFU +#define LP_AON_STORE5_M (LP_AON_STORE5_V << LP_AON_STORE5_S) +#define LP_AON_STORE5_V 0xFFFFFFFFU +#define LP_AON_STORE5_S 0 + +/** LP_AON_STORE6_REG register + * need_des + */ +#define LP_AON_STORE6_REG (DR_REG_LP_AON_BASE + 0x18) +/** LP_AON_STORE6 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_STORE6 0xFFFFFFFFU +#define LP_AON_STORE6_M (LP_AON_STORE6_V << LP_AON_STORE6_S) +#define LP_AON_STORE6_V 0xFFFFFFFFU +#define LP_AON_STORE6_S 0 + +/** LP_AON_STORE7_REG register + * need_des + */ +#define LP_AON_STORE7_REG (DR_REG_LP_AON_BASE + 0x1c) +/** LP_AON_STORE7 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_STORE7 0xFFFFFFFFU +#define LP_AON_STORE7_M (LP_AON_STORE7_V << LP_AON_STORE7_S) +#define LP_AON_STORE7_V 0xFFFFFFFFU +#define LP_AON_STORE7_S 0 + +/** LP_AON_STORE8_REG register + * need_des + */ +#define LP_AON_STORE8_REG (DR_REG_LP_AON_BASE + 0x20) +/** LP_AON_STORE8 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_STORE8 0xFFFFFFFFU +#define LP_AON_STORE8_M (LP_AON_STORE8_V << LP_AON_STORE8_S) +#define LP_AON_STORE8_V 0xFFFFFFFFU +#define LP_AON_STORE8_S 0 + +/** LP_AON_STORE9_REG register + * need_des + */ +#define LP_AON_STORE9_REG (DR_REG_LP_AON_BASE + 0x24) +/** LP_AON_STORE9 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_STORE9 0xFFFFFFFFU +#define LP_AON_STORE9_M (LP_AON_STORE9_V << LP_AON_STORE9_S) +#define LP_AON_STORE9_V 0xFFFFFFFFU +#define LP_AON_STORE9_S 0 + +/** LP_AON_GPIO_MUX_REG register + * need_des + */ +#define LP_AON_GPIO_MUX_REG (DR_REG_LP_AON_BASE + 0x28) +/** LP_AON_GPIO_MUX_SEL : R/W; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_AON_GPIO_MUX_SEL 0x000000FFU +#define LP_AON_GPIO_MUX_SEL_M (LP_AON_GPIO_MUX_SEL_V << LP_AON_GPIO_MUX_SEL_S) +#define LP_AON_GPIO_MUX_SEL_V 0x000000FFU +#define LP_AON_GPIO_MUX_SEL_S 0 + +/** LP_AON_GPIO_HOLD0_REG register + * need_des + */ +#define LP_AON_GPIO_HOLD0_REG (DR_REG_LP_AON_BASE + 0x2c) +/** LP_AON_GPIO_HOLD0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_GPIO_HOLD0 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD0_M (LP_AON_GPIO_HOLD0_V << LP_AON_GPIO_HOLD0_S) +#define LP_AON_GPIO_HOLD0_V 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD0_S 0 + +/** LP_AON_GPIO_HOLD1_REG register + * need_des + */ +#define LP_AON_GPIO_HOLD1_REG (DR_REG_LP_AON_BASE + 0x30) +/** LP_AON_GPIO_HOLD1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_GPIO_HOLD1 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD1_M (LP_AON_GPIO_HOLD1_V << LP_AON_GPIO_HOLD1_S) +#define LP_AON_GPIO_HOLD1_V 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD1_S 0 + +/** LP_AON_SYS_CFG_REG register + * need_des + */ +#define LP_AON_SYS_CFG_REG (DR_REG_LP_AON_BASE + 0x34) +/** LP_AON_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_AON_FORCE_DOWNLOAD_BOOT (BIT(30)) +#define LP_AON_FORCE_DOWNLOAD_BOOT_M (LP_AON_FORCE_DOWNLOAD_BOOT_V << LP_AON_FORCE_DOWNLOAD_BOOT_S) +#define LP_AON_FORCE_DOWNLOAD_BOOT_V 0x00000001U +#define LP_AON_FORCE_DOWNLOAD_BOOT_S 30 +/** LP_AON_HPSYS_SW_RESET : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_HPSYS_SW_RESET (BIT(31)) +#define LP_AON_HPSYS_SW_RESET_M (LP_AON_HPSYS_SW_RESET_V << LP_AON_HPSYS_SW_RESET_S) +#define LP_AON_HPSYS_SW_RESET_V 0x00000001U +#define LP_AON_HPSYS_SW_RESET_S 31 + +/** LP_AON_CPUCORE0_CFG_REG register + * need_des + */ +#define LP_AON_CPUCORE0_CFG_REG (DR_REG_LP_AON_BASE + 0x38) +/** LP_AON_CPU_CORE0_SW_STALL : R/W; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_SW_STALL 0x000000FFU +#define LP_AON_CPU_CORE0_SW_STALL_M (LP_AON_CPU_CORE0_SW_STALL_V << LP_AON_CPU_CORE0_SW_STALL_S) +#define LP_AON_CPU_CORE0_SW_STALL_V 0x000000FFU +#define LP_AON_CPU_CORE0_SW_STALL_S 0 +/** LP_AON_CPU_CORE0_SW_RESET : WT; bitpos: [28]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_SW_RESET (BIT(28)) +#define LP_AON_CPU_CORE0_SW_RESET_M (LP_AON_CPU_CORE0_SW_RESET_V << LP_AON_CPU_CORE0_SW_RESET_S) +#define LP_AON_CPU_CORE0_SW_RESET_V 0x00000001U +#define LP_AON_CPU_CORE0_SW_RESET_S 28 +/** LP_AON_CPU_CORE0_OCD_HALT_ON_RESET : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET (BIT(29)) +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_M (LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V << LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S) +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V 0x00000001U +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S 29 +/** LP_AON_CPU_CORE0_STAT_VECTOR_SEL : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL (BIT(30)) +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_M (LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V << LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S) +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V 0x00000001U +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S 30 +/** LP_AON_CPU_CORE0_DRESET_MASK : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_DRESET_MASK (BIT(31)) +#define LP_AON_CPU_CORE0_DRESET_MASK_M (LP_AON_CPU_CORE0_DRESET_MASK_V << LP_AON_CPU_CORE0_DRESET_MASK_S) +#define LP_AON_CPU_CORE0_DRESET_MASK_V 0x00000001U +#define LP_AON_CPU_CORE0_DRESET_MASK_S 31 + +/** LP_AON_IO_MUX_REG register + * need_des + */ +#define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c) +/** LP_AON_IO_MUX_RESET_DISABLE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_IO_MUX_RESET_DISABLE (BIT(31)) +#define LP_AON_IO_MUX_RESET_DISABLE_M (LP_AON_IO_MUX_RESET_DISABLE_V << LP_AON_IO_MUX_RESET_DISABLE_S) +#define LP_AON_IO_MUX_RESET_DISABLE_V 0x00000001U +#define LP_AON_IO_MUX_RESET_DISABLE_S 31 + +/** LP_AON_EXT_WAKEUP_CNTL_REG register + * need_des + */ +#define LP_AON_EXT_WAKEUP_CNTL_REG (DR_REG_LP_AON_BASE + 0x40) +/** LP_AON_EXT_WAKEUP_STATUS : RO; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_STATUS 0x000000FFU +#define LP_AON_EXT_WAKEUP_STATUS_M (LP_AON_EXT_WAKEUP_STATUS_V << LP_AON_EXT_WAKEUP_STATUS_S) +#define LP_AON_EXT_WAKEUP_STATUS_V 0x000000FFU +#define LP_AON_EXT_WAKEUP_STATUS_S 0 +/** LP_AON_EXT_WAKEUP_STATUS_CLR : WT; bitpos: [14]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_STATUS_CLR (BIT(14)) +#define LP_AON_EXT_WAKEUP_STATUS_CLR_M (LP_AON_EXT_WAKEUP_STATUS_CLR_V << LP_AON_EXT_WAKEUP_STATUS_CLR_S) +#define LP_AON_EXT_WAKEUP_STATUS_CLR_V 0x00000001U +#define LP_AON_EXT_WAKEUP_STATUS_CLR_S 14 +/** LP_AON_EXT_WAKEUP_SEL : R/W; bitpos: [22:15]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_SEL 0x000000FFU +#define LP_AON_EXT_WAKEUP_SEL_M (LP_AON_EXT_WAKEUP_SEL_V << LP_AON_EXT_WAKEUP_SEL_S) +#define LP_AON_EXT_WAKEUP_SEL_V 0x000000FFU +#define LP_AON_EXT_WAKEUP_SEL_S 15 +/** LP_AON_EXT_WAKEUP_LV : R/W; bitpos: [30:23]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_LV 0x000000FFU +#define LP_AON_EXT_WAKEUP_LV_M (LP_AON_EXT_WAKEUP_LV_V << LP_AON_EXT_WAKEUP_LV_S) +#define LP_AON_EXT_WAKEUP_LV_V 0x000000FFU +#define LP_AON_EXT_WAKEUP_LV_S 23 +/** LP_AON_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_FILTER (BIT(31)) +#define LP_AON_EXT_WAKEUP_FILTER_M (LP_AON_EXT_WAKEUP_FILTER_V << LP_AON_EXT_WAKEUP_FILTER_S) +#define LP_AON_EXT_WAKEUP_FILTER_V 0x00000001U +#define LP_AON_EXT_WAKEUP_FILTER_S 31 + +/** LP_AON_USB_REG register + * need_des + */ +#define LP_AON_USB_REG (DR_REG_LP_AON_BASE + 0x44) +/** LP_AON_USB_RESET_DISABLE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_USB_RESET_DISABLE (BIT(31)) +#define LP_AON_USB_RESET_DISABLE_M (LP_AON_USB_RESET_DISABLE_V << LP_AON_USB_RESET_DISABLE_S) +#define LP_AON_USB_RESET_DISABLE_V 0x00000001U +#define LP_AON_USB_RESET_DISABLE_S 31 + +/** LP_AON_LPBUS_REG register + * need_des + */ +#define LP_AON_LPBUS_REG (DR_REG_LP_AON_BASE + 0x48) +/** LP_AON_FAST_MEM_WPULSE : R/W; bitpos: [18:16]; default: 0; + * This field controls fast memory WPULSE parameter. + */ +#define LP_AON_FAST_MEM_WPULSE 0x00000007U +#define LP_AON_FAST_MEM_WPULSE_M (LP_AON_FAST_MEM_WPULSE_V << LP_AON_FAST_MEM_WPULSE_S) +#define LP_AON_FAST_MEM_WPULSE_V 0x00000007U +#define LP_AON_FAST_MEM_WPULSE_S 16 +/** LP_AON_FAST_MEM_WA : R/W; bitpos: [21:19]; default: 4; + * This field controls fast memory WA parameter. + */ +#define LP_AON_FAST_MEM_WA 0x00000007U +#define LP_AON_FAST_MEM_WA_M (LP_AON_FAST_MEM_WA_V << LP_AON_FAST_MEM_WA_S) +#define LP_AON_FAST_MEM_WA_V 0x00000007U +#define LP_AON_FAST_MEM_WA_S 19 +/** LP_AON_FAST_MEM_RA : R/W; bitpos: [23:22]; default: 0; + * This field controls fast memory RA parameter. + */ +#define LP_AON_FAST_MEM_RA 0x00000003U +#define LP_AON_FAST_MEM_RA_M (LP_AON_FAST_MEM_RA_V << LP_AON_FAST_MEM_RA_S) +#define LP_AON_FAST_MEM_RA_V 0x00000003U +#define LP_AON_FAST_MEM_RA_S 22 +/** LP_AON_FAST_MEM_MUX_FSM_IDLE : RO; bitpos: [28]; default: 1; + * need_des + */ +#define LP_AON_FAST_MEM_MUX_FSM_IDLE (BIT(28)) +#define LP_AON_FAST_MEM_MUX_FSM_IDLE_M (LP_AON_FAST_MEM_MUX_FSM_IDLE_V << LP_AON_FAST_MEM_MUX_FSM_IDLE_S) +#define LP_AON_FAST_MEM_MUX_FSM_IDLE_V 0x00000001U +#define LP_AON_FAST_MEM_MUX_FSM_IDLE_S 28 +/** LP_AON_FAST_MEM_MUX_SEL_STATUS : RO; bitpos: [29]; default: 1; + * need_des + */ +#define LP_AON_FAST_MEM_MUX_SEL_STATUS (BIT(29)) +#define LP_AON_FAST_MEM_MUX_SEL_STATUS_M (LP_AON_FAST_MEM_MUX_SEL_STATUS_V << LP_AON_FAST_MEM_MUX_SEL_STATUS_S) +#define LP_AON_FAST_MEM_MUX_SEL_STATUS_V 0x00000001U +#define LP_AON_FAST_MEM_MUX_SEL_STATUS_S 29 +/** LP_AON_FAST_MEM_MUX_SEL_UPDATE : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_AON_FAST_MEM_MUX_SEL_UPDATE (BIT(30)) +#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_M (LP_AON_FAST_MEM_MUX_SEL_UPDATE_V << LP_AON_FAST_MEM_MUX_SEL_UPDATE_S) +#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_V 0x00000001U +#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_S 30 +/** LP_AON_FAST_MEM_MUX_SEL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LP_AON_FAST_MEM_MUX_SEL (BIT(31)) +#define LP_AON_FAST_MEM_MUX_SEL_M (LP_AON_FAST_MEM_MUX_SEL_V << LP_AON_FAST_MEM_MUX_SEL_S) +#define LP_AON_FAST_MEM_MUX_SEL_V 0x00000001U +#define LP_AON_FAST_MEM_MUX_SEL_S 31 + +/** LP_AON_SDIO_ACTIVE_REG register + * need_des + */ +#define LP_AON_SDIO_ACTIVE_REG (DR_REG_LP_AON_BASE + 0x4c) +/** LP_AON_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 10; + * need_des + */ +#define LP_AON_SDIO_ACT_DNUM 0x000003FFU +#define LP_AON_SDIO_ACT_DNUM_M (LP_AON_SDIO_ACT_DNUM_V << LP_AON_SDIO_ACT_DNUM_S) +#define LP_AON_SDIO_ACT_DNUM_V 0x000003FFU +#define LP_AON_SDIO_ACT_DNUM_S 22 + +/** LP_AON_LPCORE_REG register + * need_des + */ +#define LP_AON_LPCORE_REG (DR_REG_LP_AON_BASE + 0x50) +/** LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0; + * need_des + */ +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR (BIT(0)) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V 0x00000001U +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S 0 +/** LP_AON_LPCORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG (BIT(1)) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_S) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_V 0x00000001U +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_S 1 +/** LP_AON_LPCORE_DISABLE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_LPCORE_DISABLE (BIT(31)) +#define LP_AON_LPCORE_DISABLE_M (LP_AON_LPCORE_DISABLE_V << LP_AON_LPCORE_DISABLE_S) +#define LP_AON_LPCORE_DISABLE_V 0x00000001U +#define LP_AON_LPCORE_DISABLE_S 31 + +/** LP_AON_SAR_CCT_REG register + * need_des + */ +#define LP_AON_SAR_CCT_REG (DR_REG_LP_AON_BASE + 0x54) +/** LP_AON_SAR2_PWDET_CCT : R/W; bitpos: [31:29]; default: 0; + * need_des + */ +#define LP_AON_SAR2_PWDET_CCT 0x00000007U +#define LP_AON_SAR2_PWDET_CCT_M (LP_AON_SAR2_PWDET_CCT_V << LP_AON_SAR2_PWDET_CCT_S) +#define LP_AON_SAR2_PWDET_CCT_V 0x00000007U +#define LP_AON_SAR2_PWDET_CCT_S 29 + +/** LP_AON_DATE_REG register + * need_des + */ +#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc) +/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 35672704; + * need_des + */ +#define LP_AON_DATE 0x7FFFFFFFU +#define LP_AON_DATE_M (LP_AON_DATE_V << LP_AON_DATE_S) +#define LP_AON_DATE_V 0x7FFFFFFFU +#define LP_AON_DATE_S 0 +/** LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_CLK_EN (BIT(31)) +#define LP_AON_CLK_EN_M (LP_AON_CLK_EN_V << LP_AON_CLK_EN_S) +#define LP_AON_CLK_EN_V 0x00000001U +#define LP_AON_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_aon_struct.h b/components/soc/esp32c6/include/soc/lp_aon_struct.h new file mode 100644 index 0000000000..9f4e3b25d0 --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_aon_struct.h @@ -0,0 +1,306 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of store register + * need_des + */ +typedef union { + struct { + /** store : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t store:32; + }; + uint32_t val; +} lp_aon_store_reg_t; + +/** Type of gpio_mux register + * need_des + */ +typedef union { + struct { + /** gpio_mux_sel : R/W; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t gpio_mux_sel:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_aon_gpio_mux_reg_t; + +/** Type of gpio_hold0 register + * need_des + */ +typedef union { + struct { + /** gpio_hold0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t gpio_hold0:32; + }; + uint32_t val; +} lp_aon_gpio_hold0_reg_t; + +/** Type of gpio_hold1 register + * need_des + */ +typedef union { + struct { + /** gpio_hold1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t gpio_hold1:32; + }; + uint32_t val; +} lp_aon_gpio_hold1_reg_t; + +/** Type of sys_cfg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** force_download_boot : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t force_download_boot:1; + /** hpsys_sw_reset : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hpsys_sw_reset:1; + }; + uint32_t val; +} lp_aon_sys_cfg_reg_t; + +/** Type of cpucore0_cfg register + * need_des + */ +typedef union { + struct { + /** cpu_core0_sw_stall : R/W; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t cpu_core0_sw_stall:8; + uint32_t reserved_8:20; + /** cpu_core0_sw_reset : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t cpu_core0_sw_reset:1; + /** cpu_core0_ocd_halt_on_reset : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t cpu_core0_ocd_halt_on_reset:1; + /** cpu_core0_stat_vector_sel : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t cpu_core0_stat_vector_sel:1; + /** cpu_core0_dreset_mask : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t cpu_core0_dreset_mask:1; + }; + uint32_t val; +} lp_aon_cpucore0_cfg_reg_t; + +/** Type of io_mux register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** io_mux_reset_disable : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t io_mux_reset_disable:1; + }; + uint32_t val; +} lp_aon_io_mux_reg_t; + +/** Type of ext_wakeup_cntl register + * need_des + */ +typedef union { + struct { + /** ext_wakeup_status : RO; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t ext_wakeup_status:8; + uint32_t reserved_8:6; + /** ext_wakeup_status_clr : WT; bitpos: [14]; default: 0; + * need_des + */ + uint32_t ext_wakeup_status_clr:1; + /** ext_wakeup_sel : R/W; bitpos: [22:15]; default: 0; + * need_des + */ + uint32_t ext_wakeup_sel:8; + /** ext_wakeup_lv : R/W; bitpos: [30:23]; default: 0; + * need_des + */ + uint32_t ext_wakeup_lv:8; + /** ext_wakeup_filter : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ext_wakeup_filter:1; + }; + uint32_t val; +} lp_aon_ext_wakeup_cntl_reg_t; + +/** Type of usb register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** usb_reset_disable : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t usb_reset_disable:1; + }; + uint32_t val; +} lp_aon_usb_reg_t; + +/** Type of lpbus register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** fast_mem_wpulse : R/W; bitpos: [18:16]; default: 0; + * This field controls fast memory WPULSE parameter. + */ + uint32_t fast_mem_wpulse:3; + /** fast_mem_wa : R/W; bitpos: [21:19]; default: 4; + * This field controls fast memory WA parameter. + */ + uint32_t fast_mem_wa:3; + /** fast_mem_ra : R/W; bitpos: [23:22]; default: 0; + * This field controls fast memory RA parameter. + */ + uint32_t fast_mem_ra:2; + uint32_t reserved_24:4; + /** fast_mem_mux_fsm_idle : RO; bitpos: [28]; default: 1; + * need_des + */ + uint32_t fast_mem_mux_fsm_idle:1; + /** fast_mem_mux_sel_status : RO; bitpos: [29]; default: 1; + * need_des + */ + uint32_t fast_mem_mux_sel_status:1; + /** fast_mem_mux_sel_update : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t fast_mem_mux_sel_update:1; + /** fast_mem_mux_sel : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t fast_mem_mux_sel:1; + }; + uint32_t val; +} lp_aon_lpbus_reg_t; + +/** Type of sdio_active register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** sdio_act_dnum : R/W; bitpos: [31:22]; default: 10; + * need_des + */ + uint32_t sdio_act_dnum:10; + }; + uint32_t val; +} lp_aon_sdio_active_reg_t; + +/** Type of lpcore register + * need_des + */ +typedef union { + struct { + /** lpcore_etm_wakeup_flag_clr : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t lpcore_etm_wakeup_flag_clr:1; + /** lpcore_etm_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ + uint32_t lpcore_etm_wakeup_flag:1; + uint32_t reserved_2:29; + /** lpcore_disable : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lpcore_disable:1; + }; + uint32_t val; +} lp_aon_lpcore_reg_t; + +/** Type of sar_cct register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:29; + /** sar2_pwdet_cct : R/W; bitpos: [31:29]; default: 0; + * need_des + */ + uint32_t sar2_pwdet_cct:3; + }; + uint32_t val; +} lp_aon_sar_cct_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** date : R/W; bitpos: [30:0]; default: 35672704; + * need_des + */ + uint32_t date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_aon_date_reg_t; + + +typedef struct lp_aon_dev_t { + volatile lp_aon_store_reg_t store[10]; + volatile lp_aon_gpio_mux_reg_t gpio_mux; + volatile lp_aon_gpio_hold0_reg_t gpio_hold0; + volatile lp_aon_gpio_hold1_reg_t gpio_hold1; + volatile lp_aon_sys_cfg_reg_t sys_cfg; + volatile lp_aon_cpucore0_cfg_reg_t cpucore0_cfg; + volatile lp_aon_io_mux_reg_t io_mux; + volatile lp_aon_ext_wakeup_cntl_reg_t ext_wakeup_cntl; + volatile lp_aon_usb_reg_t usb; + volatile lp_aon_lpbus_reg_t lpbus; + volatile lp_aon_sdio_active_reg_t sdio_active; + volatile lp_aon_lpcore_reg_t lpcore; + volatile lp_aon_sar_cct_reg_t sar_cct; + uint32_t reserved_058[233]; + volatile lp_aon_date_reg_t date; +} lp_aon_dev_t; + +extern lp_aon_dev_t LP_AON; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_aon_dev_t) == 0x400, "Invalid size of lp_aon_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_apm0_reg.h b/components/soc/esp32c6/include/soc/lp_apm0_reg.h new file mode 100644 index 0000000000..05612739a5 --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_apm0_reg.h @@ -0,0 +1,506 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_APM0_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_APM0_BASE + 0x0) +/** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1; + * Region filter enable + */ +#define LP_APM0_REGION_FILTER_EN 0x0000000FU +#define LP_APM0_REGION_FILTER_EN_M (LP_APM0_REGION_FILTER_EN_V << LP_APM0_REGION_FILTER_EN_S) +#define LP_APM0_REGION_FILTER_EN_V 0x0000000FU +#define LP_APM0_REGION_FILTER_EN_S 0 + +/** LP_APM0_REGION0_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION0_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4) +/** LP_APM0_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ +#define LP_APM0_REGION0_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_START_M (LP_APM0_REGION0_ADDR_START_V << LP_APM0_REGION0_ADDR_START_S) +#define LP_APM0_REGION0_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_START_S 0 + +/** LP_APM0_REGION0_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION0_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x8) +/** LP_APM0_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ +#define LP_APM0_REGION0_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_END_M (LP_APM0_REGION0_ADDR_END_V << LP_APM0_REGION0_ADDR_END_S) +#define LP_APM0_REGION0_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_END_S 0 + +/** LP_APM0_REGION0_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION0_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0xc) +/** LP_APM0_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION0_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION0_R0_PMS_X_M (LP_APM0_REGION0_R0_PMS_X_V << LP_APM0_REGION0_R0_PMS_X_S) +#define LP_APM0_REGION0_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION0_R0_PMS_X_S 0 +/** LP_APM0_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION0_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION0_R0_PMS_W_M (LP_APM0_REGION0_R0_PMS_W_V << LP_APM0_REGION0_R0_PMS_W_S) +#define LP_APM0_REGION0_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION0_R0_PMS_W_S 1 +/** LP_APM0_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION0_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION0_R0_PMS_R_M (LP_APM0_REGION0_R0_PMS_R_V << LP_APM0_REGION0_R0_PMS_R_S) +#define LP_APM0_REGION0_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION0_R0_PMS_R_S 2 +/** LP_APM0_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION0_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION0_R1_PMS_X_M (LP_APM0_REGION0_R1_PMS_X_V << LP_APM0_REGION0_R1_PMS_X_S) +#define LP_APM0_REGION0_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION0_R1_PMS_X_S 4 +/** LP_APM0_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION0_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION0_R1_PMS_W_M (LP_APM0_REGION0_R1_PMS_W_V << LP_APM0_REGION0_R1_PMS_W_S) +#define LP_APM0_REGION0_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION0_R1_PMS_W_S 5 +/** LP_APM0_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION0_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION0_R1_PMS_R_M (LP_APM0_REGION0_R1_PMS_R_V << LP_APM0_REGION0_R1_PMS_R_S) +#define LP_APM0_REGION0_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION0_R1_PMS_R_S 6 +/** LP_APM0_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION0_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION0_R2_PMS_X_M (LP_APM0_REGION0_R2_PMS_X_V << LP_APM0_REGION0_R2_PMS_X_S) +#define LP_APM0_REGION0_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION0_R2_PMS_X_S 8 +/** LP_APM0_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION0_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION0_R2_PMS_W_M (LP_APM0_REGION0_R2_PMS_W_V << LP_APM0_REGION0_R2_PMS_W_S) +#define LP_APM0_REGION0_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION0_R2_PMS_W_S 9 +/** LP_APM0_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION0_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION0_R2_PMS_R_M (LP_APM0_REGION0_R2_PMS_R_V << LP_APM0_REGION0_R2_PMS_R_S) +#define LP_APM0_REGION0_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION0_R2_PMS_R_S 10 + +/** LP_APM0_REGION1_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION1_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x10) +/** LP_APM0_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ +#define LP_APM0_REGION1_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_START_M (LP_APM0_REGION1_ADDR_START_V << LP_APM0_REGION1_ADDR_START_S) +#define LP_APM0_REGION1_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_START_S 0 + +/** LP_APM0_REGION1_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION1_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x14) +/** LP_APM0_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ +#define LP_APM0_REGION1_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_END_M (LP_APM0_REGION1_ADDR_END_V << LP_APM0_REGION1_ADDR_END_S) +#define LP_APM0_REGION1_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_END_S 0 + +/** LP_APM0_REGION1_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION1_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x18) +/** LP_APM0_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION1_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION1_R0_PMS_X_M (LP_APM0_REGION1_R0_PMS_X_V << LP_APM0_REGION1_R0_PMS_X_S) +#define LP_APM0_REGION1_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION1_R0_PMS_X_S 0 +/** LP_APM0_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION1_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION1_R0_PMS_W_M (LP_APM0_REGION1_R0_PMS_W_V << LP_APM0_REGION1_R0_PMS_W_S) +#define LP_APM0_REGION1_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION1_R0_PMS_W_S 1 +/** LP_APM0_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION1_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION1_R0_PMS_R_M (LP_APM0_REGION1_R0_PMS_R_V << LP_APM0_REGION1_R0_PMS_R_S) +#define LP_APM0_REGION1_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION1_R0_PMS_R_S 2 +/** LP_APM0_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION1_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION1_R1_PMS_X_M (LP_APM0_REGION1_R1_PMS_X_V << LP_APM0_REGION1_R1_PMS_X_S) +#define LP_APM0_REGION1_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION1_R1_PMS_X_S 4 +/** LP_APM0_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION1_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION1_R1_PMS_W_M (LP_APM0_REGION1_R1_PMS_W_V << LP_APM0_REGION1_R1_PMS_W_S) +#define LP_APM0_REGION1_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION1_R1_PMS_W_S 5 +/** LP_APM0_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION1_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION1_R1_PMS_R_M (LP_APM0_REGION1_R1_PMS_R_V << LP_APM0_REGION1_R1_PMS_R_S) +#define LP_APM0_REGION1_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION1_R1_PMS_R_S 6 +/** LP_APM0_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION1_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION1_R2_PMS_X_M (LP_APM0_REGION1_R2_PMS_X_V << LP_APM0_REGION1_R2_PMS_X_S) +#define LP_APM0_REGION1_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION1_R2_PMS_X_S 8 +/** LP_APM0_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION1_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION1_R2_PMS_W_M (LP_APM0_REGION1_R2_PMS_W_V << LP_APM0_REGION1_R2_PMS_W_S) +#define LP_APM0_REGION1_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION1_R2_PMS_W_S 9 +/** LP_APM0_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION1_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION1_R2_PMS_R_M (LP_APM0_REGION1_R2_PMS_R_V << LP_APM0_REGION1_R2_PMS_R_S) +#define LP_APM0_REGION1_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION1_R2_PMS_R_S 10 + +/** LP_APM0_REGION2_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION2_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x1c) +/** LP_APM0_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ +#define LP_APM0_REGION2_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_START_M (LP_APM0_REGION2_ADDR_START_V << LP_APM0_REGION2_ADDR_START_S) +#define LP_APM0_REGION2_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_START_S 0 + +/** LP_APM0_REGION2_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION2_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x20) +/** LP_APM0_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ +#define LP_APM0_REGION2_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_END_M (LP_APM0_REGION2_ADDR_END_V << LP_APM0_REGION2_ADDR_END_S) +#define LP_APM0_REGION2_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_END_S 0 + +/** LP_APM0_REGION2_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION2_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x24) +/** LP_APM0_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION2_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION2_R0_PMS_X_M (LP_APM0_REGION2_R0_PMS_X_V << LP_APM0_REGION2_R0_PMS_X_S) +#define LP_APM0_REGION2_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION2_R0_PMS_X_S 0 +/** LP_APM0_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION2_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION2_R0_PMS_W_M (LP_APM0_REGION2_R0_PMS_W_V << LP_APM0_REGION2_R0_PMS_W_S) +#define LP_APM0_REGION2_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION2_R0_PMS_W_S 1 +/** LP_APM0_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION2_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION2_R0_PMS_R_M (LP_APM0_REGION2_R0_PMS_R_V << LP_APM0_REGION2_R0_PMS_R_S) +#define LP_APM0_REGION2_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION2_R0_PMS_R_S 2 +/** LP_APM0_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION2_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION2_R1_PMS_X_M (LP_APM0_REGION2_R1_PMS_X_V << LP_APM0_REGION2_R1_PMS_X_S) +#define LP_APM0_REGION2_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION2_R1_PMS_X_S 4 +/** LP_APM0_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION2_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION2_R1_PMS_W_M (LP_APM0_REGION2_R1_PMS_W_V << LP_APM0_REGION2_R1_PMS_W_S) +#define LP_APM0_REGION2_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION2_R1_PMS_W_S 5 +/** LP_APM0_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION2_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION2_R1_PMS_R_M (LP_APM0_REGION2_R1_PMS_R_V << LP_APM0_REGION2_R1_PMS_R_S) +#define LP_APM0_REGION2_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION2_R1_PMS_R_S 6 +/** LP_APM0_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION2_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION2_R2_PMS_X_M (LP_APM0_REGION2_R2_PMS_X_V << LP_APM0_REGION2_R2_PMS_X_S) +#define LP_APM0_REGION2_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION2_R2_PMS_X_S 8 +/** LP_APM0_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION2_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION2_R2_PMS_W_M (LP_APM0_REGION2_R2_PMS_W_V << LP_APM0_REGION2_R2_PMS_W_S) +#define LP_APM0_REGION2_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION2_R2_PMS_W_S 9 +/** LP_APM0_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION2_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION2_R2_PMS_R_M (LP_APM0_REGION2_R2_PMS_R_V << LP_APM0_REGION2_R2_PMS_R_S) +#define LP_APM0_REGION2_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION2_R2_PMS_R_S 10 + +/** LP_APM0_REGION3_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION3_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x28) +/** LP_APM0_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ +#define LP_APM0_REGION3_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_START_M (LP_APM0_REGION3_ADDR_START_V << LP_APM0_REGION3_ADDR_START_S) +#define LP_APM0_REGION3_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_START_S 0 + +/** LP_APM0_REGION3_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION3_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x2c) +/** LP_APM0_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ +#define LP_APM0_REGION3_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_END_M (LP_APM0_REGION3_ADDR_END_V << LP_APM0_REGION3_ADDR_END_S) +#define LP_APM0_REGION3_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_END_S 0 + +/** LP_APM0_REGION3_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION3_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x30) +/** LP_APM0_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION3_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION3_R0_PMS_X_M (LP_APM0_REGION3_R0_PMS_X_V << LP_APM0_REGION3_R0_PMS_X_S) +#define LP_APM0_REGION3_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION3_R0_PMS_X_S 0 +/** LP_APM0_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION3_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION3_R0_PMS_W_M (LP_APM0_REGION3_R0_PMS_W_V << LP_APM0_REGION3_R0_PMS_W_S) +#define LP_APM0_REGION3_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION3_R0_PMS_W_S 1 +/** LP_APM0_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION3_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION3_R0_PMS_R_M (LP_APM0_REGION3_R0_PMS_R_V << LP_APM0_REGION3_R0_PMS_R_S) +#define LP_APM0_REGION3_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION3_R0_PMS_R_S 2 +/** LP_APM0_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION3_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION3_R1_PMS_X_M (LP_APM0_REGION3_R1_PMS_X_V << LP_APM0_REGION3_R1_PMS_X_S) +#define LP_APM0_REGION3_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION3_R1_PMS_X_S 4 +/** LP_APM0_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION3_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION3_R1_PMS_W_M (LP_APM0_REGION3_R1_PMS_W_V << LP_APM0_REGION3_R1_PMS_W_S) +#define LP_APM0_REGION3_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION3_R1_PMS_W_S 5 +/** LP_APM0_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION3_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION3_R1_PMS_R_M (LP_APM0_REGION3_R1_PMS_R_V << LP_APM0_REGION3_R1_PMS_R_S) +#define LP_APM0_REGION3_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION3_R1_PMS_R_S 6 +/** LP_APM0_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION3_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION3_R2_PMS_X_M (LP_APM0_REGION3_R2_PMS_X_V << LP_APM0_REGION3_R2_PMS_X_S) +#define LP_APM0_REGION3_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION3_R2_PMS_X_S 8 +/** LP_APM0_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION3_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION3_R2_PMS_W_M (LP_APM0_REGION3_R2_PMS_W_V << LP_APM0_REGION3_R2_PMS_W_S) +#define LP_APM0_REGION3_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION3_R2_PMS_W_S 9 +/** LP_APM0_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION3_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION3_R2_PMS_R_M (LP_APM0_REGION3_R2_PMS_R_V << LP_APM0_REGION3_R2_PMS_R_S) +#define LP_APM0_REGION3_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION3_R2_PMS_R_S 10 + +/** LP_APM0_FUNC_CTRL_REG register + * PMS function control register + */ +#define LP_APM0_FUNC_CTRL_REG (DR_REG_LP_APM0_BASE + 0xc4) +/** LP_APM0_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define LP_APM0_M0_PMS_FUNC_EN (BIT(0)) +#define LP_APM0_M0_PMS_FUNC_EN_M (LP_APM0_M0_PMS_FUNC_EN_V << LP_APM0_M0_PMS_FUNC_EN_S) +#define LP_APM0_M0_PMS_FUNC_EN_V 0x00000001U +#define LP_APM0_M0_PMS_FUNC_EN_S 0 + +/** LP_APM0_M0_STATUS_REG register + * M0 status register + */ +#define LP_APM0_M0_STATUS_REG (DR_REG_LP_APM0_BASE + 0xc8) +/** LP_APM0_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define LP_APM0_M0_EXCEPTION_STATUS 0x00000003U +#define LP_APM0_M0_EXCEPTION_STATUS_M (LP_APM0_M0_EXCEPTION_STATUS_V << LP_APM0_M0_EXCEPTION_STATUS_S) +#define LP_APM0_M0_EXCEPTION_STATUS_V 0x00000003U +#define LP_APM0_M0_EXCEPTION_STATUS_S 0 + +/** LP_APM0_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define LP_APM0_M0_STATUS_CLR_REG (DR_REG_LP_APM0_BASE + 0xcc) +/** LP_APM0_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define LP_APM0_M0_REGION_STATUS_CLR (BIT(0)) +#define LP_APM0_M0_REGION_STATUS_CLR_M (LP_APM0_M0_REGION_STATUS_CLR_V << LP_APM0_M0_REGION_STATUS_CLR_S) +#define LP_APM0_M0_REGION_STATUS_CLR_V 0x00000001U +#define LP_APM0_M0_REGION_STATUS_CLR_S 0 + +/** LP_APM0_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM0_BASE + 0xd0) +/** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0; + * Exception region + */ +#define LP_APM0_M0_EXCEPTION_REGION 0x0000000FU +#define LP_APM0_M0_EXCEPTION_REGION_M (LP_APM0_M0_EXCEPTION_REGION_V << LP_APM0_M0_EXCEPTION_REGION_S) +#define LP_APM0_M0_EXCEPTION_REGION_V 0x0000000FU +#define LP_APM0_M0_EXCEPTION_REGION_S 0 +/** LP_APM0_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define LP_APM0_M0_EXCEPTION_MODE 0x00000003U +#define LP_APM0_M0_EXCEPTION_MODE_M (LP_APM0_M0_EXCEPTION_MODE_V << LP_APM0_M0_EXCEPTION_MODE_S) +#define LP_APM0_M0_EXCEPTION_MODE_V 0x00000003U +#define LP_APM0_M0_EXCEPTION_MODE_S 16 +/** LP_APM0_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define LP_APM0_M0_EXCEPTION_ID 0x0000001FU +#define LP_APM0_M0_EXCEPTION_ID_M (LP_APM0_M0_EXCEPTION_ID_V << LP_APM0_M0_EXCEPTION_ID_S) +#define LP_APM0_M0_EXCEPTION_ID_V 0x0000001FU +#define LP_APM0_M0_EXCEPTION_ID_S 18 + +/** LP_APM0_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define LP_APM0_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM0_BASE + 0xd4) +/** LP_APM0_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define LP_APM0_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define LP_APM0_M0_EXCEPTION_ADDR_M (LP_APM0_M0_EXCEPTION_ADDR_V << LP_APM0_M0_EXCEPTION_ADDR_S) +#define LP_APM0_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define LP_APM0_M0_EXCEPTION_ADDR_S 0 + +/** LP_APM0_INT_EN_REG register + * APM interrupt enable register + */ +#define LP_APM0_INT_EN_REG (DR_REG_LP_APM0_BASE + 0xd8) +/** LP_APM0_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ +#define LP_APM0_M0_APM_INT_EN (BIT(0)) +#define LP_APM0_M0_APM_INT_EN_M (LP_APM0_M0_APM_INT_EN_V << LP_APM0_M0_APM_INT_EN_S) +#define LP_APM0_M0_APM_INT_EN_V 0x00000001U +#define LP_APM0_M0_APM_INT_EN_S 0 + +/** LP_APM0_CLOCK_GATE_REG register + * clock gating register + */ +#define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_APM0_BASE + 0xdc) +/** LP_APM0_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define LP_APM0_CLK_EN (BIT(0)) +#define LP_APM0_CLK_EN_M (LP_APM0_CLK_EN_V << LP_APM0_CLK_EN_S) +#define LP_APM0_CLK_EN_V 0x00000001U +#define LP_APM0_CLK_EN_S 0 + +/** LP_APM0_DATE_REG register + * Version register + */ +#define LP_APM0_DATE_REG (DR_REG_LP_APM0_BASE + 0x7fc) +/** LP_APM0_DATE : R/W; bitpos: [27:0]; default: 35672640; + * reg_date + */ +#define LP_APM0_DATE 0x0FFFFFFFU +#define LP_APM0_DATE_M (LP_APM0_DATE_V << LP_APM0_DATE_S) +#define LP_APM0_DATE_V 0x0FFFFFFFU +#define LP_APM0_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_apm0_struct.h b/components/soc/esp32c6/include/soc/lp_apm0_struct.h new file mode 100644 index 0000000000..f9221bc0ff --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_apm0_struct.h @@ -0,0 +1,499 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** region_filter_en : R/W; bitpos: [3:0]; default: 1; + * Region filter enable + */ + uint32_t region_filter_en:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} lp_apm0_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of region0_addr_start register + * Region address register + */ +typedef union { + struct { + /** region0_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ + uint32_t region0_addr_start:32; + }; + uint32_t val; +} lp_apm0_region0_addr_start_reg_t; + +/** Type of region0_addr_end register + * Region address register + */ +typedef union { + struct { + /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ + uint32_t region0_addr_end:32; + }; + uint32_t val; +} lp_apm0_region0_addr_end_reg_t; + +/** Type of region1_addr_start register + * Region address register + */ +typedef union { + struct { + /** region1_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ + uint32_t region1_addr_start:32; + }; + uint32_t val; +} lp_apm0_region1_addr_start_reg_t; + +/** Type of region1_addr_end register + * Region address register + */ +typedef union { + struct { + /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ + uint32_t region1_addr_end:32; + }; + uint32_t val; +} lp_apm0_region1_addr_end_reg_t; + +/** Type of region2_addr_start register + * Region address register + */ +typedef union { + struct { + /** region2_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ + uint32_t region2_addr_start:32; + }; + uint32_t val; +} lp_apm0_region2_addr_start_reg_t; + +/** Type of region2_addr_end register + * Region address register + */ +typedef union { + struct { + /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ + uint32_t region2_addr_end:32; + }; + uint32_t val; +} lp_apm0_region2_addr_end_reg_t; + +/** Type of region3_addr_start register + * Region address register + */ +typedef union { + struct { + /** region3_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ + uint32_t region3_addr_start:32; + }; + uint32_t val; +} lp_apm0_region3_addr_start_reg_t; + +/** Type of region3_addr_end register + * Region address register + */ +typedef union { + struct { + /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ + uint32_t region3_addr_end:32; + }; + uint32_t val; +} lp_apm0_region3_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of region0_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region0_r0_pms_x:1; + /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region0_r0_pms_w:1; + /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region0_r0_pms_r:1; + uint32_t reserved_3:1; + /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region0_r1_pms_x:1; + /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region0_r1_pms_w:1; + /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region0_r1_pms_r:1; + uint32_t reserved_7:1; + /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region0_r2_pms_x:1; + /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region0_r2_pms_w:1; + /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region0_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm0_region0_pms_attr_reg_t; + +/** Type of region1_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region1_r0_pms_x:1; + /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region1_r0_pms_w:1; + /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region1_r0_pms_r:1; + uint32_t reserved_3:1; + /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region1_r1_pms_x:1; + /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region1_r1_pms_w:1; + /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region1_r1_pms_r:1; + uint32_t reserved_7:1; + /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region1_r2_pms_x:1; + /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region1_r2_pms_w:1; + /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region1_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm0_region1_pms_attr_reg_t; + +/** Type of region2_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region2_r0_pms_x:1; + /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region2_r0_pms_w:1; + /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region2_r0_pms_r:1; + uint32_t reserved_3:1; + /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region2_r1_pms_x:1; + /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region2_r1_pms_w:1; + /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region2_r1_pms_r:1; + uint32_t reserved_7:1; + /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region2_r2_pms_x:1; + /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region2_r2_pms_w:1; + /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region2_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm0_region2_pms_attr_reg_t; + +/** Type of region3_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region3_r0_pms_x:1; + /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region3_r0_pms_w:1; + /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region3_r0_pms_r:1; + uint32_t reserved_3:1; + /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region3_r1_pms_x:1; + /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region3_r1_pms_w:1; + /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region3_r1_pms_r:1; + uint32_t reserved_7:1; + /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region3_r2_pms_x:1; + /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region3_r2_pms_w:1; + /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region3_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm0_region3_pms_attr_reg_t; + + +/** Group: PMS function control register */ +/** Type of func_ctrl register + * PMS function control register + */ +typedef union { + struct { + /** m0_pms_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t m0_pms_func_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of m0_status register + * M0 status register + */ +typedef union { + struct { + /** m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm0_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** m0_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m0_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** m0_exception_region : RO; bitpos: [3:0]; default: 0; + * Exception region + */ + uint32_t m0_exception_region:4; + uint32_t reserved_4:12; + /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m0_exception_mode:2; + /** m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} lp_apm0_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m0_exception_addr:32; + }; + uint32_t val; +} lp_apm0_m0_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ + uint32_t m0_apm_int_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_int_en_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35672640; + * reg_date + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_apm0_date_reg_t; + + +typedef struct lp_apm0_dev_t { + volatile lp_apm0_region_filter_en_reg_t region_filter_en; + volatile lp_apm0_region0_addr_start_reg_t region0_addr_start; + volatile lp_apm0_region0_addr_end_reg_t region0_addr_end; + volatile lp_apm0_region0_pms_attr_reg_t region0_pms_attr; + volatile lp_apm0_region1_addr_start_reg_t region1_addr_start; + volatile lp_apm0_region1_addr_end_reg_t region1_addr_end; + volatile lp_apm0_region1_pms_attr_reg_t region1_pms_attr; + volatile lp_apm0_region2_addr_start_reg_t region2_addr_start; + volatile lp_apm0_region2_addr_end_reg_t region2_addr_end; + volatile lp_apm0_region2_pms_attr_reg_t region2_pms_attr; + volatile lp_apm0_region3_addr_start_reg_t region3_addr_start; + volatile lp_apm0_region3_addr_end_reg_t region3_addr_end; + volatile lp_apm0_region3_pms_attr_reg_t region3_pms_attr; + uint32_t reserved_034[36]; + volatile lp_apm0_func_ctrl_reg_t func_ctrl; + volatile lp_apm0_m0_status_reg_t m0_status; + volatile lp_apm0_m0_status_clr_reg_t m0_status_clr; + volatile lp_apm0_m0_exception_info0_reg_t m0_exception_info0; + volatile lp_apm0_m0_exception_info1_reg_t m0_exception_info1; + volatile lp_apm0_int_en_reg_t int_en; + volatile lp_apm0_clock_gate_reg_t clock_gate; + uint32_t reserved_0e0[455]; + volatile lp_apm0_date_reg_t date; +} lp_apm0_dev_t; + +extern lp_apm0_dev_t LP_APM0; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_apm0_dev_t) == 0x800, "Invalid size of lp_apm0_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_apm_reg.h b/components/soc/esp32c6/include/soc/lp_apm_reg.h new file mode 100644 index 0000000000..02eba5ffa9 --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_apm_reg.h @@ -0,0 +1,582 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_APM_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_APM_BASE + 0x0) +/** LP_APM_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1; + * Region filter enable + */ +#define LP_APM_REGION_FILTER_EN 0x0000000FU +#define LP_APM_REGION_FILTER_EN_M (LP_APM_REGION_FILTER_EN_V << LP_APM_REGION_FILTER_EN_S) +#define LP_APM_REGION_FILTER_EN_V 0x0000000FU +#define LP_APM_REGION_FILTER_EN_S 0 + +/** LP_APM_REGION0_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4) +/** LP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ +#define LP_APM_REGION0_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_START_M (LP_APM_REGION0_ADDR_START_V << LP_APM_REGION0_ADDR_START_S) +#define LP_APM_REGION0_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_START_S 0 + +/** LP_APM_REGION0_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x8) +/** LP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ +#define LP_APM_REGION0_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_END_M (LP_APM_REGION0_ADDR_END_V << LP_APM_REGION0_ADDR_END_S) +#define LP_APM_REGION0_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_END_S 0 + +/** LP_APM_REGION0_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION0_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0xc) +/** LP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM_REGION0_R0_PMS_X (BIT(0)) +#define LP_APM_REGION0_R0_PMS_X_M (LP_APM_REGION0_R0_PMS_X_V << LP_APM_REGION0_R0_PMS_X_S) +#define LP_APM_REGION0_R0_PMS_X_V 0x00000001U +#define LP_APM_REGION0_R0_PMS_X_S 0 +/** LP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM_REGION0_R0_PMS_W (BIT(1)) +#define LP_APM_REGION0_R0_PMS_W_M (LP_APM_REGION0_R0_PMS_W_V << LP_APM_REGION0_R0_PMS_W_S) +#define LP_APM_REGION0_R0_PMS_W_V 0x00000001U +#define LP_APM_REGION0_R0_PMS_W_S 1 +/** LP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM_REGION0_R0_PMS_R (BIT(2)) +#define LP_APM_REGION0_R0_PMS_R_M (LP_APM_REGION0_R0_PMS_R_V << LP_APM_REGION0_R0_PMS_R_S) +#define LP_APM_REGION0_R0_PMS_R_V 0x00000001U +#define LP_APM_REGION0_R0_PMS_R_S 2 +/** LP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM_REGION0_R1_PMS_X (BIT(4)) +#define LP_APM_REGION0_R1_PMS_X_M (LP_APM_REGION0_R1_PMS_X_V << LP_APM_REGION0_R1_PMS_X_S) +#define LP_APM_REGION0_R1_PMS_X_V 0x00000001U +#define LP_APM_REGION0_R1_PMS_X_S 4 +/** LP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM_REGION0_R1_PMS_W (BIT(5)) +#define LP_APM_REGION0_R1_PMS_W_M (LP_APM_REGION0_R1_PMS_W_V << LP_APM_REGION0_R1_PMS_W_S) +#define LP_APM_REGION0_R1_PMS_W_V 0x00000001U +#define LP_APM_REGION0_R1_PMS_W_S 5 +/** LP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM_REGION0_R1_PMS_R (BIT(6)) +#define LP_APM_REGION0_R1_PMS_R_M (LP_APM_REGION0_R1_PMS_R_V << LP_APM_REGION0_R1_PMS_R_S) +#define LP_APM_REGION0_R1_PMS_R_V 0x00000001U +#define LP_APM_REGION0_R1_PMS_R_S 6 +/** LP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM_REGION0_R2_PMS_X (BIT(8)) +#define LP_APM_REGION0_R2_PMS_X_M (LP_APM_REGION0_R2_PMS_X_V << LP_APM_REGION0_R2_PMS_X_S) +#define LP_APM_REGION0_R2_PMS_X_V 0x00000001U +#define LP_APM_REGION0_R2_PMS_X_S 8 +/** LP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM_REGION0_R2_PMS_W (BIT(9)) +#define LP_APM_REGION0_R2_PMS_W_M (LP_APM_REGION0_R2_PMS_W_V << LP_APM_REGION0_R2_PMS_W_S) +#define LP_APM_REGION0_R2_PMS_W_V 0x00000001U +#define LP_APM_REGION0_R2_PMS_W_S 9 +/** LP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM_REGION0_R2_PMS_R (BIT(10)) +#define LP_APM_REGION0_R2_PMS_R_M (LP_APM_REGION0_R2_PMS_R_V << LP_APM_REGION0_R2_PMS_R_S) +#define LP_APM_REGION0_R2_PMS_R_V 0x00000001U +#define LP_APM_REGION0_R2_PMS_R_S 10 + +/** LP_APM_REGION1_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x10) +/** LP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ +#define LP_APM_REGION1_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_START_M (LP_APM_REGION1_ADDR_START_V << LP_APM_REGION1_ADDR_START_S) +#define LP_APM_REGION1_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_START_S 0 + +/** LP_APM_REGION1_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x14) +/** LP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ +#define LP_APM_REGION1_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_END_M (LP_APM_REGION1_ADDR_END_V << LP_APM_REGION1_ADDR_END_S) +#define LP_APM_REGION1_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_END_S 0 + +/** LP_APM_REGION1_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION1_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x18) +/** LP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM_REGION1_R0_PMS_X (BIT(0)) +#define LP_APM_REGION1_R0_PMS_X_M (LP_APM_REGION1_R0_PMS_X_V << LP_APM_REGION1_R0_PMS_X_S) +#define LP_APM_REGION1_R0_PMS_X_V 0x00000001U +#define LP_APM_REGION1_R0_PMS_X_S 0 +/** LP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM_REGION1_R0_PMS_W (BIT(1)) +#define LP_APM_REGION1_R0_PMS_W_M (LP_APM_REGION1_R0_PMS_W_V << LP_APM_REGION1_R0_PMS_W_S) +#define LP_APM_REGION1_R0_PMS_W_V 0x00000001U +#define LP_APM_REGION1_R0_PMS_W_S 1 +/** LP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM_REGION1_R0_PMS_R (BIT(2)) +#define LP_APM_REGION1_R0_PMS_R_M (LP_APM_REGION1_R0_PMS_R_V << LP_APM_REGION1_R0_PMS_R_S) +#define LP_APM_REGION1_R0_PMS_R_V 0x00000001U +#define LP_APM_REGION1_R0_PMS_R_S 2 +/** LP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM_REGION1_R1_PMS_X (BIT(4)) +#define LP_APM_REGION1_R1_PMS_X_M (LP_APM_REGION1_R1_PMS_X_V << LP_APM_REGION1_R1_PMS_X_S) +#define LP_APM_REGION1_R1_PMS_X_V 0x00000001U +#define LP_APM_REGION1_R1_PMS_X_S 4 +/** LP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM_REGION1_R1_PMS_W (BIT(5)) +#define LP_APM_REGION1_R1_PMS_W_M (LP_APM_REGION1_R1_PMS_W_V << LP_APM_REGION1_R1_PMS_W_S) +#define LP_APM_REGION1_R1_PMS_W_V 0x00000001U +#define LP_APM_REGION1_R1_PMS_W_S 5 +/** LP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM_REGION1_R1_PMS_R (BIT(6)) +#define LP_APM_REGION1_R1_PMS_R_M (LP_APM_REGION1_R1_PMS_R_V << LP_APM_REGION1_R1_PMS_R_S) +#define LP_APM_REGION1_R1_PMS_R_V 0x00000001U +#define LP_APM_REGION1_R1_PMS_R_S 6 +/** LP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM_REGION1_R2_PMS_X (BIT(8)) +#define LP_APM_REGION1_R2_PMS_X_M (LP_APM_REGION1_R2_PMS_X_V << LP_APM_REGION1_R2_PMS_X_S) +#define LP_APM_REGION1_R2_PMS_X_V 0x00000001U +#define LP_APM_REGION1_R2_PMS_X_S 8 +/** LP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM_REGION1_R2_PMS_W (BIT(9)) +#define LP_APM_REGION1_R2_PMS_W_M (LP_APM_REGION1_R2_PMS_W_V << LP_APM_REGION1_R2_PMS_W_S) +#define LP_APM_REGION1_R2_PMS_W_V 0x00000001U +#define LP_APM_REGION1_R2_PMS_W_S 9 +/** LP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM_REGION1_R2_PMS_R (BIT(10)) +#define LP_APM_REGION1_R2_PMS_R_M (LP_APM_REGION1_R2_PMS_R_V << LP_APM_REGION1_R2_PMS_R_S) +#define LP_APM_REGION1_R2_PMS_R_V 0x00000001U +#define LP_APM_REGION1_R2_PMS_R_S 10 + +/** LP_APM_REGION2_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION2_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x1c) +/** LP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ +#define LP_APM_REGION2_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION2_ADDR_START_M (LP_APM_REGION2_ADDR_START_V << LP_APM_REGION2_ADDR_START_S) +#define LP_APM_REGION2_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION2_ADDR_START_S 0 + +/** LP_APM_REGION2_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION2_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x20) +/** LP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ +#define LP_APM_REGION2_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION2_ADDR_END_M (LP_APM_REGION2_ADDR_END_V << LP_APM_REGION2_ADDR_END_S) +#define LP_APM_REGION2_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION2_ADDR_END_S 0 + +/** LP_APM_REGION2_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION2_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x24) +/** LP_APM_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM_REGION2_R0_PMS_X (BIT(0)) +#define LP_APM_REGION2_R0_PMS_X_M (LP_APM_REGION2_R0_PMS_X_V << LP_APM_REGION2_R0_PMS_X_S) +#define LP_APM_REGION2_R0_PMS_X_V 0x00000001U +#define LP_APM_REGION2_R0_PMS_X_S 0 +/** LP_APM_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM_REGION2_R0_PMS_W (BIT(1)) +#define LP_APM_REGION2_R0_PMS_W_M (LP_APM_REGION2_R0_PMS_W_V << LP_APM_REGION2_R0_PMS_W_S) +#define LP_APM_REGION2_R0_PMS_W_V 0x00000001U +#define LP_APM_REGION2_R0_PMS_W_S 1 +/** LP_APM_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM_REGION2_R0_PMS_R (BIT(2)) +#define LP_APM_REGION2_R0_PMS_R_M (LP_APM_REGION2_R0_PMS_R_V << LP_APM_REGION2_R0_PMS_R_S) +#define LP_APM_REGION2_R0_PMS_R_V 0x00000001U +#define LP_APM_REGION2_R0_PMS_R_S 2 +/** LP_APM_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM_REGION2_R1_PMS_X (BIT(4)) +#define LP_APM_REGION2_R1_PMS_X_M (LP_APM_REGION2_R1_PMS_X_V << LP_APM_REGION2_R1_PMS_X_S) +#define LP_APM_REGION2_R1_PMS_X_V 0x00000001U +#define LP_APM_REGION2_R1_PMS_X_S 4 +/** LP_APM_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM_REGION2_R1_PMS_W (BIT(5)) +#define LP_APM_REGION2_R1_PMS_W_M (LP_APM_REGION2_R1_PMS_W_V << LP_APM_REGION2_R1_PMS_W_S) +#define LP_APM_REGION2_R1_PMS_W_V 0x00000001U +#define LP_APM_REGION2_R1_PMS_W_S 5 +/** LP_APM_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM_REGION2_R1_PMS_R (BIT(6)) +#define LP_APM_REGION2_R1_PMS_R_M (LP_APM_REGION2_R1_PMS_R_V << LP_APM_REGION2_R1_PMS_R_S) +#define LP_APM_REGION2_R1_PMS_R_V 0x00000001U +#define LP_APM_REGION2_R1_PMS_R_S 6 +/** LP_APM_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM_REGION2_R2_PMS_X (BIT(8)) +#define LP_APM_REGION2_R2_PMS_X_M (LP_APM_REGION2_R2_PMS_X_V << LP_APM_REGION2_R2_PMS_X_S) +#define LP_APM_REGION2_R2_PMS_X_V 0x00000001U +#define LP_APM_REGION2_R2_PMS_X_S 8 +/** LP_APM_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM_REGION2_R2_PMS_W (BIT(9)) +#define LP_APM_REGION2_R2_PMS_W_M (LP_APM_REGION2_R2_PMS_W_V << LP_APM_REGION2_R2_PMS_W_S) +#define LP_APM_REGION2_R2_PMS_W_V 0x00000001U +#define LP_APM_REGION2_R2_PMS_W_S 9 +/** LP_APM_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM_REGION2_R2_PMS_R (BIT(10)) +#define LP_APM_REGION2_R2_PMS_R_M (LP_APM_REGION2_R2_PMS_R_V << LP_APM_REGION2_R2_PMS_R_S) +#define LP_APM_REGION2_R2_PMS_R_V 0x00000001U +#define LP_APM_REGION2_R2_PMS_R_S 10 + +/** LP_APM_REGION3_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION3_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x28) +/** LP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ +#define LP_APM_REGION3_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION3_ADDR_START_M (LP_APM_REGION3_ADDR_START_V << LP_APM_REGION3_ADDR_START_S) +#define LP_APM_REGION3_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION3_ADDR_START_S 0 + +/** LP_APM_REGION3_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION3_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x2c) +/** LP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ +#define LP_APM_REGION3_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION3_ADDR_END_M (LP_APM_REGION3_ADDR_END_V << LP_APM_REGION3_ADDR_END_S) +#define LP_APM_REGION3_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION3_ADDR_END_S 0 + +/** LP_APM_REGION3_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION3_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x30) +/** LP_APM_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM_REGION3_R0_PMS_X (BIT(0)) +#define LP_APM_REGION3_R0_PMS_X_M (LP_APM_REGION3_R0_PMS_X_V << LP_APM_REGION3_R0_PMS_X_S) +#define LP_APM_REGION3_R0_PMS_X_V 0x00000001U +#define LP_APM_REGION3_R0_PMS_X_S 0 +/** LP_APM_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM_REGION3_R0_PMS_W (BIT(1)) +#define LP_APM_REGION3_R0_PMS_W_M (LP_APM_REGION3_R0_PMS_W_V << LP_APM_REGION3_R0_PMS_W_S) +#define LP_APM_REGION3_R0_PMS_W_V 0x00000001U +#define LP_APM_REGION3_R0_PMS_W_S 1 +/** LP_APM_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM_REGION3_R0_PMS_R (BIT(2)) +#define LP_APM_REGION3_R0_PMS_R_M (LP_APM_REGION3_R0_PMS_R_V << LP_APM_REGION3_R0_PMS_R_S) +#define LP_APM_REGION3_R0_PMS_R_V 0x00000001U +#define LP_APM_REGION3_R0_PMS_R_S 2 +/** LP_APM_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM_REGION3_R1_PMS_X (BIT(4)) +#define LP_APM_REGION3_R1_PMS_X_M (LP_APM_REGION3_R1_PMS_X_V << LP_APM_REGION3_R1_PMS_X_S) +#define LP_APM_REGION3_R1_PMS_X_V 0x00000001U +#define LP_APM_REGION3_R1_PMS_X_S 4 +/** LP_APM_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM_REGION3_R1_PMS_W (BIT(5)) +#define LP_APM_REGION3_R1_PMS_W_M (LP_APM_REGION3_R1_PMS_W_V << LP_APM_REGION3_R1_PMS_W_S) +#define LP_APM_REGION3_R1_PMS_W_V 0x00000001U +#define LP_APM_REGION3_R1_PMS_W_S 5 +/** LP_APM_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM_REGION3_R1_PMS_R (BIT(6)) +#define LP_APM_REGION3_R1_PMS_R_M (LP_APM_REGION3_R1_PMS_R_V << LP_APM_REGION3_R1_PMS_R_S) +#define LP_APM_REGION3_R1_PMS_R_V 0x00000001U +#define LP_APM_REGION3_R1_PMS_R_S 6 +/** LP_APM_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM_REGION3_R2_PMS_X (BIT(8)) +#define LP_APM_REGION3_R2_PMS_X_M (LP_APM_REGION3_R2_PMS_X_V << LP_APM_REGION3_R2_PMS_X_S) +#define LP_APM_REGION3_R2_PMS_X_V 0x00000001U +#define LP_APM_REGION3_R2_PMS_X_S 8 +/** LP_APM_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM_REGION3_R2_PMS_W (BIT(9)) +#define LP_APM_REGION3_R2_PMS_W_M (LP_APM_REGION3_R2_PMS_W_V << LP_APM_REGION3_R2_PMS_W_S) +#define LP_APM_REGION3_R2_PMS_W_V 0x00000001U +#define LP_APM_REGION3_R2_PMS_W_S 9 +/** LP_APM_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM_REGION3_R2_PMS_R (BIT(10)) +#define LP_APM_REGION3_R2_PMS_R_M (LP_APM_REGION3_R2_PMS_R_V << LP_APM_REGION3_R2_PMS_R_S) +#define LP_APM_REGION3_R2_PMS_R_V 0x00000001U +#define LP_APM_REGION3_R2_PMS_R_S 10 + +/** LP_APM_FUNC_CTRL_REG register + * PMS function control register + */ +#define LP_APM_FUNC_CTRL_REG (DR_REG_LP_APM_BASE + 0xc4) +/** LP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define LP_APM_M0_PMS_FUNC_EN (BIT(0)) +#define LP_APM_M0_PMS_FUNC_EN_M (LP_APM_M0_PMS_FUNC_EN_V << LP_APM_M0_PMS_FUNC_EN_S) +#define LP_APM_M0_PMS_FUNC_EN_V 0x00000001U +#define LP_APM_M0_PMS_FUNC_EN_S 0 +/** LP_APM_M1_PMS_FUNC_EN : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ +#define LP_APM_M1_PMS_FUNC_EN (BIT(1)) +#define LP_APM_M1_PMS_FUNC_EN_M (LP_APM_M1_PMS_FUNC_EN_V << LP_APM_M1_PMS_FUNC_EN_S) +#define LP_APM_M1_PMS_FUNC_EN_V 0x00000001U +#define LP_APM_M1_PMS_FUNC_EN_S 1 + +/** LP_APM_M0_STATUS_REG register + * M0 status register + */ +#define LP_APM_M0_STATUS_REG (DR_REG_LP_APM_BASE + 0xc8) +/** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define LP_APM_M0_EXCEPTION_STATUS 0x00000003U +#define LP_APM_M0_EXCEPTION_STATUS_M (LP_APM_M0_EXCEPTION_STATUS_V << LP_APM_M0_EXCEPTION_STATUS_S) +#define LP_APM_M0_EXCEPTION_STATUS_V 0x00000003U +#define LP_APM_M0_EXCEPTION_STATUS_S 0 + +/** LP_APM_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xcc) +/** LP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define LP_APM_M0_REGION_STATUS_CLR (BIT(0)) +#define LP_APM_M0_REGION_STATUS_CLR_M (LP_APM_M0_REGION_STATUS_CLR_V << LP_APM_M0_REGION_STATUS_CLR_S) +#define LP_APM_M0_REGION_STATUS_CLR_V 0x00000001U +#define LP_APM_M0_REGION_STATUS_CLR_S 0 + +/** LP_APM_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xd0) +/** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0; + * Exception region + */ +#define LP_APM_M0_EXCEPTION_REGION 0x0000000FU +#define LP_APM_M0_EXCEPTION_REGION_M (LP_APM_M0_EXCEPTION_REGION_V << LP_APM_M0_EXCEPTION_REGION_S) +#define LP_APM_M0_EXCEPTION_REGION_V 0x0000000FU +#define LP_APM_M0_EXCEPTION_REGION_S 0 +/** LP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define LP_APM_M0_EXCEPTION_MODE 0x00000003U +#define LP_APM_M0_EXCEPTION_MODE_M (LP_APM_M0_EXCEPTION_MODE_V << LP_APM_M0_EXCEPTION_MODE_S) +#define LP_APM_M0_EXCEPTION_MODE_V 0x00000003U +#define LP_APM_M0_EXCEPTION_MODE_S 16 +/** LP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define LP_APM_M0_EXCEPTION_ID 0x0000001FU +#define LP_APM_M0_EXCEPTION_ID_M (LP_APM_M0_EXCEPTION_ID_V << LP_APM_M0_EXCEPTION_ID_S) +#define LP_APM_M0_EXCEPTION_ID_V 0x0000001FU +#define LP_APM_M0_EXCEPTION_ID_S 18 + +/** LP_APM_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xd4) +/** LP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define LP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define LP_APM_M0_EXCEPTION_ADDR_M (LP_APM_M0_EXCEPTION_ADDR_V << LP_APM_M0_EXCEPTION_ADDR_S) +#define LP_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define LP_APM_M0_EXCEPTION_ADDR_S 0 + +/** LP_APM_M1_STATUS_REG register + * M1 status register + */ +#define LP_APM_M1_STATUS_REG (DR_REG_LP_APM_BASE + 0xd8) +/** LP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define LP_APM_M1_EXCEPTION_STATUS 0x00000003U +#define LP_APM_M1_EXCEPTION_STATUS_M (LP_APM_M1_EXCEPTION_STATUS_V << LP_APM_M1_EXCEPTION_STATUS_S) +#define LP_APM_M1_EXCEPTION_STATUS_V 0x00000003U +#define LP_APM_M1_EXCEPTION_STATUS_S 0 + +/** LP_APM_M1_STATUS_CLR_REG register + * M1 status clear register + */ +#define LP_APM_M1_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xdc) +/** LP_APM_M1_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define LP_APM_M1_REGION_STATUS_CLR (BIT(0)) +#define LP_APM_M1_REGION_STATUS_CLR_M (LP_APM_M1_REGION_STATUS_CLR_V << LP_APM_M1_REGION_STATUS_CLR_S) +#define LP_APM_M1_REGION_STATUS_CLR_V 0x00000001U +#define LP_APM_M1_REGION_STATUS_CLR_S 0 + +/** LP_APM_M1_EXCEPTION_INFO0_REG register + * M1 exception_info0 register + */ +#define LP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xe0) +/** LP_APM_M1_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0; + * Exception region + */ +#define LP_APM_M1_EXCEPTION_REGION 0x0000000FU +#define LP_APM_M1_EXCEPTION_REGION_M (LP_APM_M1_EXCEPTION_REGION_V << LP_APM_M1_EXCEPTION_REGION_S) +#define LP_APM_M1_EXCEPTION_REGION_V 0x0000000FU +#define LP_APM_M1_EXCEPTION_REGION_S 0 +/** LP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define LP_APM_M1_EXCEPTION_MODE 0x00000003U +#define LP_APM_M1_EXCEPTION_MODE_M (LP_APM_M1_EXCEPTION_MODE_V << LP_APM_M1_EXCEPTION_MODE_S) +#define LP_APM_M1_EXCEPTION_MODE_V 0x00000003U +#define LP_APM_M1_EXCEPTION_MODE_S 16 +/** LP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define LP_APM_M1_EXCEPTION_ID 0x0000001FU +#define LP_APM_M1_EXCEPTION_ID_M (LP_APM_M1_EXCEPTION_ID_V << LP_APM_M1_EXCEPTION_ID_S) +#define LP_APM_M1_EXCEPTION_ID_V 0x0000001FU +#define LP_APM_M1_EXCEPTION_ID_S 18 + +/** LP_APM_M1_EXCEPTION_INFO1_REG register + * M1 exception_info1 register + */ +#define LP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xe4) +/** LP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define LP_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU +#define LP_APM_M1_EXCEPTION_ADDR_M (LP_APM_M1_EXCEPTION_ADDR_V << LP_APM_M1_EXCEPTION_ADDR_S) +#define LP_APM_M1_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define LP_APM_M1_EXCEPTION_ADDR_S 0 + +/** LP_APM_INT_EN_REG register + * APM interrupt enable register + */ +#define LP_APM_INT_EN_REG (DR_REG_LP_APM_BASE + 0xe8) +/** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ +#define LP_APM_M0_APM_INT_EN (BIT(0)) +#define LP_APM_M0_APM_INT_EN_M (LP_APM_M0_APM_INT_EN_V << LP_APM_M0_APM_INT_EN_S) +#define LP_APM_M0_APM_INT_EN_V 0x00000001U +#define LP_APM_M0_APM_INT_EN_S 0 +/** LP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; + * APM M1 interrupt enable + */ +#define LP_APM_M1_APM_INT_EN (BIT(1)) +#define LP_APM_M1_APM_INT_EN_M (LP_APM_M1_APM_INT_EN_V << LP_APM_M1_APM_INT_EN_S) +#define LP_APM_M1_APM_INT_EN_V 0x00000001U +#define LP_APM_M1_APM_INT_EN_S 1 + +/** LP_APM_CLOCK_GATE_REG register + * clock gating register + */ +#define LP_APM_CLOCK_GATE_REG (DR_REG_LP_APM_BASE + 0xec) +/** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define LP_APM_CLK_EN (BIT(0)) +#define LP_APM_CLK_EN_M (LP_APM_CLK_EN_V << LP_APM_CLK_EN_S) +#define LP_APM_CLK_EN_V 0x00000001U +#define LP_APM_CLK_EN_S 0 + +/** LP_APM_DATE_REG register + * Version register + */ +#define LP_APM_DATE_REG (DR_REG_LP_APM_BASE + 0xfc) +/** LP_APM_DATE : R/W; bitpos: [27:0]; default: 35672640; + * reg_date + */ +#define LP_APM_DATE 0x0FFFFFFFU +#define LP_APM_DATE_M (LP_APM_DATE_V << LP_APM_DATE_S) +#define LP_APM_DATE_V 0x0FFFFFFFU +#define LP_APM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_apm_struct.h b/components/soc/esp32c6/include/soc/lp_apm_struct.h new file mode 100644 index 0000000000..7140a8800f --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_apm_struct.h @@ -0,0 +1,583 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** region_filter_en : R/W; bitpos: [3:0]; default: 1; + * Region filter enable + */ + uint32_t region_filter_en:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} lp_apm_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of region0_addr_start register + * Region address register + */ +typedef union { + struct { + /** region0_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ + uint32_t region0_addr_start:32; + }; + uint32_t val; +} lp_apm_region0_addr_start_reg_t; + +/** Type of region0_addr_end register + * Region address register + */ +typedef union { + struct { + /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ + uint32_t region0_addr_end:32; + }; + uint32_t val; +} lp_apm_region0_addr_end_reg_t; + +/** Type of region1_addr_start register + * Region address register + */ +typedef union { + struct { + /** region1_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ + uint32_t region1_addr_start:32; + }; + uint32_t val; +} lp_apm_region1_addr_start_reg_t; + +/** Type of region1_addr_end register + * Region address register + */ +typedef union { + struct { + /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ + uint32_t region1_addr_end:32; + }; + uint32_t val; +} lp_apm_region1_addr_end_reg_t; + +/** Type of region2_addr_start register + * Region address register + */ +typedef union { + struct { + /** region2_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ + uint32_t region2_addr_start:32; + }; + uint32_t val; +} lp_apm_region2_addr_start_reg_t; + +/** Type of region2_addr_end register + * Region address register + */ +typedef union { + struct { + /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ + uint32_t region2_addr_end:32; + }; + uint32_t val; +} lp_apm_region2_addr_end_reg_t; + +/** Type of region3_addr_start register + * Region address register + */ +typedef union { + struct { + /** region3_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ + uint32_t region3_addr_start:32; + }; + uint32_t val; +} lp_apm_region3_addr_start_reg_t; + +/** Type of region3_addr_end register + * Region address register + */ +typedef union { + struct { + /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ + uint32_t region3_addr_end:32; + }; + uint32_t val; +} lp_apm_region3_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of region0_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region0_r0_pms_x:1; + /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region0_r0_pms_w:1; + /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region0_r0_pms_r:1; + uint32_t reserved_3:1; + /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region0_r1_pms_x:1; + /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region0_r1_pms_w:1; + /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region0_r1_pms_r:1; + uint32_t reserved_7:1; + /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region0_r2_pms_x:1; + /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region0_r2_pms_w:1; + /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region0_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm_region0_pms_attr_reg_t; + +/** Type of region1_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region1_r0_pms_x:1; + /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region1_r0_pms_w:1; + /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region1_r0_pms_r:1; + uint32_t reserved_3:1; + /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region1_r1_pms_x:1; + /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region1_r1_pms_w:1; + /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region1_r1_pms_r:1; + uint32_t reserved_7:1; + /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region1_r2_pms_x:1; + /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region1_r2_pms_w:1; + /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region1_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm_region1_pms_attr_reg_t; + +/** Type of region2_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region2_r0_pms_x:1; + /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region2_r0_pms_w:1; + /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region2_r0_pms_r:1; + uint32_t reserved_3:1; + /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region2_r1_pms_x:1; + /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region2_r1_pms_w:1; + /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region2_r1_pms_r:1; + uint32_t reserved_7:1; + /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region2_r2_pms_x:1; + /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region2_r2_pms_w:1; + /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region2_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm_region2_pms_attr_reg_t; + +/** Type of region3_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region3_r0_pms_x:1; + /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region3_r0_pms_w:1; + /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region3_r0_pms_r:1; + uint32_t reserved_3:1; + /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region3_r1_pms_x:1; + /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region3_r1_pms_w:1; + /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region3_r1_pms_r:1; + uint32_t reserved_7:1; + /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region3_r2_pms_x:1; + /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region3_r2_pms_w:1; + /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region3_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm_region3_pms_attr_reg_t; + + +/** Group: PMS function control register */ +/** Type of func_ctrl register + * PMS function control register + */ +typedef union { + struct { + /** m0_pms_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t m0_pms_func_en:1; + /** m1_pms_func_en : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ + uint32_t m1_pms_func_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of m0_status register + * M0 status register + */ +typedef union { + struct { + /** m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** m0_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m0_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** m0_exception_region : RO; bitpos: [3:0]; default: 0; + * Exception region + */ + uint32_t m0_exception_region:4; + uint32_t reserved_4:12; + /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m0_exception_mode:2; + /** m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} lp_apm_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m0_exception_addr:32; + }; + uint32_t val; +} lp_apm_m0_exception_info1_reg_t; + + +/** Group: M1 status register */ +/** Type of m1_status register + * M1 status register + */ +typedef union { + struct { + /** m1_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m1_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm_m1_status_reg_t; + + +/** Group: M1 status clear register */ +/** Type of m1_status_clr register + * M1 status clear register + */ +typedef union { + struct { + /** m1_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m1_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_m1_status_clr_reg_t; + + +/** Group: M1 exception_info0 register */ +/** Type of m1_exception_info0 register + * M1 exception_info0 register + */ +typedef union { + struct { + /** m1_exception_region : RO; bitpos: [3:0]; default: 0; + * Exception region + */ + uint32_t m1_exception_region:4; + uint32_t reserved_4:12; + /** m1_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m1_exception_mode:2; + /** m1_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m1_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} lp_apm_m1_exception_info0_reg_t; + + +/** Group: M1 exception_info1 register */ +/** Type of m1_exception_info1 register + * M1 exception_info1 register + */ +typedef union { + struct { + /** m1_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m1_exception_addr:32; + }; + uint32_t val; +} lp_apm_m1_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ + uint32_t m0_apm_int_en:1; + /** m1_apm_int_en : R/W; bitpos: [1]; default: 0; + * APM M1 interrupt enable + */ + uint32_t m1_apm_int_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm_int_en_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35672640; + * reg_date + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_apm_date_reg_t; + + +typedef struct lp_apm_dev_t { + volatile lp_apm_region_filter_en_reg_t region_filter_en; + volatile lp_apm_region0_addr_start_reg_t region0_addr_start; + volatile lp_apm_region0_addr_end_reg_t region0_addr_end; + volatile lp_apm_region0_pms_attr_reg_t region0_pms_attr; + volatile lp_apm_region1_addr_start_reg_t region1_addr_start; + volatile lp_apm_region1_addr_end_reg_t region1_addr_end; + volatile lp_apm_region1_pms_attr_reg_t region1_pms_attr; + volatile lp_apm_region2_addr_start_reg_t region2_addr_start; + volatile lp_apm_region2_addr_end_reg_t region2_addr_end; + volatile lp_apm_region2_pms_attr_reg_t region2_pms_attr; + volatile lp_apm_region3_addr_start_reg_t region3_addr_start; + volatile lp_apm_region3_addr_end_reg_t region3_addr_end; + volatile lp_apm_region3_pms_attr_reg_t region3_pms_attr; + uint32_t reserved_034[36]; + volatile lp_apm_func_ctrl_reg_t func_ctrl; + volatile lp_apm_m0_status_reg_t m0_status; + volatile lp_apm_m0_status_clr_reg_t m0_status_clr; + volatile lp_apm_m0_exception_info0_reg_t m0_exception_info0; + volatile lp_apm_m0_exception_info1_reg_t m0_exception_info1; + volatile lp_apm_m1_status_reg_t m1_status; + volatile lp_apm_m1_status_clr_reg_t m1_status_clr; + volatile lp_apm_m1_exception_info0_reg_t m1_exception_info0; + volatile lp_apm_m1_exception_info1_reg_t m1_exception_info1; + volatile lp_apm_int_en_reg_t int_en; + volatile lp_apm_clock_gate_reg_t clock_gate; + uint32_t reserved_0f0[3]; + volatile lp_apm_date_reg_t date; +} lp_apm_dev_t; + +extern lp_apm_dev_t LP_APM; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_apm_dev_t) == 0x100, "Invalid size of lp_apm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_clkrst_reg.h b/components/soc/esp32c6/include/soc/lp_clkrst_reg.h new file mode 100644 index 0000000000..431fccf251 --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_clkrst_reg.h @@ -0,0 +1,382 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_CLKRST_LP_CLK_CONF_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0) +/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * need_des + */ +#define LP_CLKRST_SLOW_CLK_SEL 0x00000003U +#define LP_CLKRST_SLOW_CLK_SEL_M (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S) +#define LP_CLKRST_SLOW_CLK_SEL_V 0x00000003U +#define LP_CLKRST_SLOW_CLK_SEL_S 0 +/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define LP_CLKRST_FAST_CLK_SEL (BIT(2)) +#define LP_CLKRST_FAST_CLK_SEL_M (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S) +#define LP_CLKRST_FAST_CLK_SEL_V 0x00000001U +#define LP_CLKRST_FAST_CLK_SEL_S 2 +/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [10:3]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_PERI_DIV_NUM 0x000000FFU +#define LP_CLKRST_LP_PERI_DIV_NUM_M (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S) +#define LP_CLKRST_LP_PERI_DIV_NUM_V 0x000000FFU +#define LP_CLKRST_LP_PERI_DIV_NUM_S 3 + +/** LP_CLKRST_LP_CLK_PO_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4) +/** LP_CLKRST_AON_SLOW_OEN : R/W; bitpos: [0]; default: 1; + * need_des + */ +#define LP_CLKRST_AON_SLOW_OEN (BIT(0)) +#define LP_CLKRST_AON_SLOW_OEN_M (LP_CLKRST_AON_SLOW_OEN_V << LP_CLKRST_AON_SLOW_OEN_S) +#define LP_CLKRST_AON_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_AON_SLOW_OEN_S 0 +/** LP_CLKRST_AON_FAST_OEN : R/W; bitpos: [1]; default: 1; + * need_des + */ +#define LP_CLKRST_AON_FAST_OEN (BIT(1)) +#define LP_CLKRST_AON_FAST_OEN_M (LP_CLKRST_AON_FAST_OEN_V << LP_CLKRST_AON_FAST_OEN_S) +#define LP_CLKRST_AON_FAST_OEN_V 0x00000001U +#define LP_CLKRST_AON_FAST_OEN_S 1 +/** LP_CLKRST_SOSC_OEN : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define LP_CLKRST_SOSC_OEN (BIT(2)) +#define LP_CLKRST_SOSC_OEN_M (LP_CLKRST_SOSC_OEN_V << LP_CLKRST_SOSC_OEN_S) +#define LP_CLKRST_SOSC_OEN_V 0x00000001U +#define LP_CLKRST_SOSC_OEN_S 2 +/** LP_CLKRST_FOSC_OEN : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define LP_CLKRST_FOSC_OEN (BIT(3)) +#define LP_CLKRST_FOSC_OEN_M (LP_CLKRST_FOSC_OEN_V << LP_CLKRST_FOSC_OEN_S) +#define LP_CLKRST_FOSC_OEN_V 0x00000001U +#define LP_CLKRST_FOSC_OEN_S 3 +/** LP_CLKRST_OSC32K_OEN : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define LP_CLKRST_OSC32K_OEN (BIT(4)) +#define LP_CLKRST_OSC32K_OEN_M (LP_CLKRST_OSC32K_OEN_V << LP_CLKRST_OSC32K_OEN_S) +#define LP_CLKRST_OSC32K_OEN_V 0x00000001U +#define LP_CLKRST_OSC32K_OEN_S 4 +/** LP_CLKRST_XTAL32K_OEN : R/W; bitpos: [5]; default: 1; + * need_des + */ +#define LP_CLKRST_XTAL32K_OEN (BIT(5)) +#define LP_CLKRST_XTAL32K_OEN_M (LP_CLKRST_XTAL32K_OEN_V << LP_CLKRST_XTAL32K_OEN_S) +#define LP_CLKRST_XTAL32K_OEN_V 0x00000001U +#define LP_CLKRST_XTAL32K_OEN_S 5 +/** LP_CLKRST_CORE_EFUSE_OEN : R/W; bitpos: [6]; default: 1; + * need_des + */ +#define LP_CLKRST_CORE_EFUSE_OEN (BIT(6)) +#define LP_CLKRST_CORE_EFUSE_OEN_M (LP_CLKRST_CORE_EFUSE_OEN_V << LP_CLKRST_CORE_EFUSE_OEN_S) +#define LP_CLKRST_CORE_EFUSE_OEN_V 0x00000001U +#define LP_CLKRST_CORE_EFUSE_OEN_S 6 +/** LP_CLKRST_SLOW_OEN : R/W; bitpos: [7]; default: 1; + * need_des + */ +#define LP_CLKRST_SLOW_OEN (BIT(7)) +#define LP_CLKRST_SLOW_OEN_M (LP_CLKRST_SLOW_OEN_V << LP_CLKRST_SLOW_OEN_S) +#define LP_CLKRST_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_SLOW_OEN_S 7 +/** LP_CLKRST_FAST_OEN : R/W; bitpos: [8]; default: 1; + * need_des + */ +#define LP_CLKRST_FAST_OEN (BIT(8)) +#define LP_CLKRST_FAST_OEN_M (LP_CLKRST_FAST_OEN_V << LP_CLKRST_FAST_OEN_S) +#define LP_CLKRST_FAST_OEN_V 0x00000001U +#define LP_CLKRST_FAST_OEN_S 8 +/** LP_CLKRST_RNG_OEN : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define LP_CLKRST_RNG_OEN (BIT(9)) +#define LP_CLKRST_RNG_OEN_M (LP_CLKRST_RNG_OEN_V << LP_CLKRST_RNG_OEN_S) +#define LP_CLKRST_RNG_OEN_V 0x00000001U +#define LP_CLKRST_RNG_OEN_S 9 +/** LP_CLKRST_LPBUS_OEN : R/W; bitpos: [10]; default: 1; + * need_des + */ +#define LP_CLKRST_LPBUS_OEN (BIT(10)) +#define LP_CLKRST_LPBUS_OEN_M (LP_CLKRST_LPBUS_OEN_V << LP_CLKRST_LPBUS_OEN_S) +#define LP_CLKRST_LPBUS_OEN_V 0x00000001U +#define LP_CLKRST_LPBUS_OEN_S 10 + +/** LP_CLKRST_LP_CLK_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8) +/** LP_CLKRST_FAST_ORI_GATE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_FAST_ORI_GATE (BIT(31)) +#define LP_CLKRST_FAST_ORI_GATE_M (LP_CLKRST_FAST_ORI_GATE_V << LP_CLKRST_FAST_ORI_GATE_S) +#define LP_CLKRST_FAST_ORI_GATE_V 0x00000001U +#define LP_CLKRST_FAST_ORI_GATE_S 31 + +/** LP_CLKRST_LP_RST_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc) +/** LP_CLKRST_AON_EFUSE_CORE_RESET_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN (BIT(28)) +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_M (LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V << LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S) +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V 0x00000001U +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S 28 +/** LP_CLKRST_LP_TIMER_RESET_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_TIMER_RESET_EN (BIT(29)) +#define LP_CLKRST_LP_TIMER_RESET_EN_M (LP_CLKRST_LP_TIMER_RESET_EN_V << LP_CLKRST_LP_TIMER_RESET_EN_S) +#define LP_CLKRST_LP_TIMER_RESET_EN_V 0x00000001U +#define LP_CLKRST_LP_TIMER_RESET_EN_S 29 +/** LP_CLKRST_WDT_RESET_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_WDT_RESET_EN (BIT(30)) +#define LP_CLKRST_WDT_RESET_EN_M (LP_CLKRST_WDT_RESET_EN_V << LP_CLKRST_WDT_RESET_EN_S) +#define LP_CLKRST_WDT_RESET_EN_V 0x00000001U +#define LP_CLKRST_WDT_RESET_EN_S 30 +/** LP_CLKRST_ANA_PERI_RESET_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_ANA_PERI_RESET_EN (BIT(31)) +#define LP_CLKRST_ANA_PERI_RESET_EN_M (LP_CLKRST_ANA_PERI_RESET_EN_V << LP_CLKRST_ANA_PERI_RESET_EN_S) +#define LP_CLKRST_ANA_PERI_RESET_EN_V 0x00000001U +#define LP_CLKRST_ANA_PERI_RESET_EN_S 31 + +/** LP_CLKRST_RESET_CAUSE_REG register + * need_des + */ +#define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10) +/** LP_CLKRST_RESET_CAUSE : RO; bitpos: [4:0]; default: 0; + * need_des + */ +#define LP_CLKRST_RESET_CAUSE 0x0000001FU +#define LP_CLKRST_RESET_CAUSE_M (LP_CLKRST_RESET_CAUSE_V << LP_CLKRST_RESET_CAUSE_S) +#define LP_CLKRST_RESET_CAUSE_V 0x0000001FU +#define LP_CLKRST_RESET_CAUSE_S 0 +/** LP_CLKRST_CORE0_RESET_FLAG : RO; bitpos: [5]; default: 1; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_FLAG (BIT(5)) +#define LP_CLKRST_CORE0_RESET_FLAG_M (LP_CLKRST_CORE0_RESET_FLAG_V << LP_CLKRST_CORE0_RESET_FLAG_S) +#define LP_CLKRST_CORE0_RESET_FLAG_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_S 5 +/** LP_CLKRST_CORE0_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR (BIT(29)) +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_M (LP_CLKRST_CORE0_RESET_CAUSE_CLR_V << LP_CLKRST_CORE0_RESET_CAUSE_CLR_S) +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_S 29 +/** LP_CLKRST_CORE0_RESET_FLAG_SET : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_FLAG_SET (BIT(30)) +#define LP_CLKRST_CORE0_RESET_FLAG_SET_M (LP_CLKRST_CORE0_RESET_FLAG_SET_V << LP_CLKRST_CORE0_RESET_FLAG_SET_S) +#define LP_CLKRST_CORE0_RESET_FLAG_SET_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_SET_S 30 +/** LP_CLKRST_CORE0_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_FLAG_CLR (BIT(31)) +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_M (LP_CLKRST_CORE0_RESET_FLAG_CLR_V << LP_CLKRST_CORE0_RESET_FLAG_CLR_S) +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_S 31 + +/** LP_CLKRST_CPU_RESET_REG register + * need_des + */ +#define LP_CLKRST_CPU_RESET_REG (DR_REG_LP_CLKRST_BASE + 0x14) +/** LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1; + * need_des + */ +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH 0x00000007U +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_M (LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S) +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S 22 +/** LP_CLKRST_RTC_WDT_CPU_RESET_EN : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN (BIT(25)) +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_M (LP_CLKRST_RTC_WDT_CPU_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_RESET_EN_S) +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_V 0x00000001U +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_S 25 +/** LP_CLKRST_CPU_STALL_WAIT : R/W; bitpos: [30:26]; default: 1; + * need_des + */ +#define LP_CLKRST_CPU_STALL_WAIT 0x0000001FU +#define LP_CLKRST_CPU_STALL_WAIT_M (LP_CLKRST_CPU_STALL_WAIT_V << LP_CLKRST_CPU_STALL_WAIT_S) +#define LP_CLKRST_CPU_STALL_WAIT_V 0x0000001FU +#define LP_CLKRST_CPU_STALL_WAIT_S 26 +/** LP_CLKRST_CPU_STALL_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_CPU_STALL_EN (BIT(31)) +#define LP_CLKRST_CPU_STALL_EN_M (LP_CLKRST_CPU_STALL_EN_V << LP_CLKRST_CPU_STALL_EN_S) +#define LP_CLKRST_CPU_STALL_EN_V 0x00000001U +#define LP_CLKRST_CPU_STALL_EN_S 31 + +/** LP_CLKRST_FOSC_CNTL_REG register + * need_des + */ +#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x18) +/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 172; + * need_des + */ +#define LP_CLKRST_FOSC_DFREQ 0x000003FFU +#define LP_CLKRST_FOSC_DFREQ_M (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S) +#define LP_CLKRST_FOSC_DFREQ_V 0x000003FFU +#define LP_CLKRST_FOSC_DFREQ_S 22 + +/** LP_CLKRST_RC32K_CNTL_REG register + * need_des + */ +#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c) +/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:22]; default: 172; + * need_des + */ +#define LP_CLKRST_RC32K_DFREQ 0x000003FFU +#define LP_CLKRST_RC32K_DFREQ_M (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S) +#define LP_CLKRST_RC32K_DFREQ_V 0x000003FFU +#define LP_CLKRST_RC32K_DFREQ_S 22 + +/** LP_CLKRST_CLK_TO_HP_REG register + * need_des + */ +#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x20) +/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_XTAL32K (BIT(28)) +#define LP_CLKRST_ICG_HP_XTAL32K_M (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S) +#define LP_CLKRST_ICG_HP_XTAL32K_V 0x00000001U +#define LP_CLKRST_ICG_HP_XTAL32K_S 28 +/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_SOSC (BIT(29)) +#define LP_CLKRST_ICG_HP_SOSC_M (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S) +#define LP_CLKRST_ICG_HP_SOSC_V 0x00000001U +#define LP_CLKRST_ICG_HP_SOSC_S 29 +/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_OSC32K (BIT(30)) +#define LP_CLKRST_ICG_HP_OSC32K_M (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S) +#define LP_CLKRST_ICG_HP_OSC32K_V 0x00000001U +#define LP_CLKRST_ICG_HP_OSC32K_S 30 +/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_FOSC (BIT(31)) +#define LP_CLKRST_ICG_HP_FOSC_M (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S) +#define LP_CLKRST_ICG_HP_FOSC_V 0x00000001U +#define LP_CLKRST_ICG_HP_FOSC_S 31 + +/** LP_CLKRST_LPMEM_FORCE_REG register + * need_des + */ +#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x24) +/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_LPMEM_CLK_FORCE_ON (BIT(31)) +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S) +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V 0x00000001U +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S 31 + +/** LP_CLKRST_LPPERI_REG register + * need_des + */ +#define LP_CLKRST_LPPERI_REG (DR_REG_LP_CLKRST_BASE + 0x28) +/** LP_CLKRST_LP_I2C_CLK_SEL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_I2C_CLK_SEL (BIT(30)) +#define LP_CLKRST_LP_I2C_CLK_SEL_M (LP_CLKRST_LP_I2C_CLK_SEL_V << LP_CLKRST_LP_I2C_CLK_SEL_S) +#define LP_CLKRST_LP_I2C_CLK_SEL_V 0x00000001U +#define LP_CLKRST_LP_I2C_CLK_SEL_S 30 +/** LP_CLKRST_LP_UART_CLK_SEL : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_UART_CLK_SEL (BIT(31)) +#define LP_CLKRST_LP_UART_CLK_SEL_M (LP_CLKRST_LP_UART_CLK_SEL_V << LP_CLKRST_LP_UART_CLK_SEL_S) +#define LP_CLKRST_LP_UART_CLK_SEL_V 0x00000001U +#define LP_CLKRST_LP_UART_CLK_SEL_S 31 + +/** LP_CLKRST_XTAL32K_REG register + * need_des + */ +#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x2c) +/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3; + * need_des + */ +#define LP_CLKRST_DRES_XTAL32K 0x00000007U +#define LP_CLKRST_DRES_XTAL32K_M (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S) +#define LP_CLKRST_DRES_XTAL32K_V 0x00000007U +#define LP_CLKRST_DRES_XTAL32K_S 22 +/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3; + * need_des + */ +#define LP_CLKRST_DGM_XTAL32K 0x00000007U +#define LP_CLKRST_DGM_XTAL32K_M (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S) +#define LP_CLKRST_DGM_XTAL32K_V 0x00000007U +#define LP_CLKRST_DGM_XTAL32K_S 25 +/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_DBUF_XTAL32K (BIT(28)) +#define LP_CLKRST_DBUF_XTAL32K_M (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S) +#define LP_CLKRST_DBUF_XTAL32K_V 0x00000001U +#define LP_CLKRST_DBUF_XTAL32K_S 28 +/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3; + * need_des + */ +#define LP_CLKRST_DAC_XTAL32K 0x00000007U +#define LP_CLKRST_DAC_XTAL32K_M (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S) +#define LP_CLKRST_DAC_XTAL32K_V 0x00000007U +#define LP_CLKRST_DAC_XTAL32K_S 29 + +/** LP_CLKRST_DATE_REG register + * need_des + */ +#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc) +/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 35676304; + * need_des + */ +#define LP_CLKRST_CLKRST_DATE 0x7FFFFFFFU +#define LP_CLKRST_CLKRST_DATE_M (LP_CLKRST_CLKRST_DATE_V << LP_CLKRST_CLKRST_DATE_S) +#define LP_CLKRST_CLKRST_DATE_V 0x7FFFFFFFU +#define LP_CLKRST_CLKRST_DATE_S 0 +/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_EN (BIT(31)) +#define LP_CLKRST_CLK_EN_M (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S) +#define LP_CLKRST_CLK_EN_V 0x00000001U +#define LP_CLKRST_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_clkrst_struct.h b/components/soc/esp32c6/include/soc/lp_clkrst_struct.h new file mode 100644 index 0000000000..e32192899d --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_clkrst_struct.h @@ -0,0 +1,341 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of lp_clk_conf register + * need_des + */ +typedef union { + struct { + /** slow_clk_sel : R/W; bitpos: [1:0]; default: 0; + * need_des + */ + uint32_t slow_clk_sel:2; + /** fast_clk_sel : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t fast_clk_sel:1; + /** lp_peri_div_num : R/W; bitpos: [10:3]; default: 0; + * need_des + */ + uint32_t lp_peri_div_num:8; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_clkrst_lp_clk_conf_reg_t; + +/** Type of lp_clk_po_en register + * need_des + */ +typedef union { + struct { + /** aon_slow_oen : R/W; bitpos: [0]; default: 1; + * need_des + */ + uint32_t aon_slow_oen:1; + /** aon_fast_oen : R/W; bitpos: [1]; default: 1; + * need_des + */ + uint32_t aon_fast_oen:1; + /** sosc_oen : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t sosc_oen:1; + /** fosc_oen : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t fosc_oen:1; + /** osc32k_oen : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t osc32k_oen:1; + /** xtal32k_oen : R/W; bitpos: [5]; default: 1; + * need_des + */ + uint32_t xtal32k_oen:1; + /** core_efuse_oen : R/W; bitpos: [6]; default: 1; + * need_des + */ + uint32_t core_efuse_oen:1; + /** slow_oen : R/W; bitpos: [7]; default: 1; + * need_des + */ + uint32_t slow_oen:1; + /** fast_oen : R/W; bitpos: [8]; default: 1; + * need_des + */ + uint32_t fast_oen:1; + /** rng_oen : R/W; bitpos: [9]; default: 1; + * need_des + */ + uint32_t rng_oen:1; + /** lpbus_oen : R/W; bitpos: [10]; default: 1; + * need_des + */ + uint32_t lpbus_oen:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_clkrst_lp_clk_po_en_reg_t; + +/** Type of lp_clk_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** fast_ori_gate : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t fast_ori_gate:1; + }; + uint32_t val; +} lp_clkrst_lp_clk_en_reg_t; + +/** Type of lp_rst_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** aon_efuse_core_reset_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t aon_efuse_core_reset_en:1; + /** lp_timer_reset_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_timer_reset_en:1; + /** wdt_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t wdt_reset_en:1; + /** ana_peri_reset_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_peri_reset_en:1; + }; + uint32_t val; +} lp_clkrst_lp_rst_en_reg_t; + +/** Type of reset_cause register + * need_des + */ +typedef union { + struct { + /** reset_cause : RO; bitpos: [4:0]; default: 0; + * need_des + */ + uint32_t reset_cause:5; + /** core0_reset_flag : RO; bitpos: [5]; default: 1; + * need_des + */ + uint32_t core0_reset_flag:1; + uint32_t reserved_6:23; + /** core0_reset_cause_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t core0_reset_cause_clr:1; + /** core0_reset_flag_set : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t core0_reset_flag_set:1; + /** core0_reset_flag_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t core0_reset_flag_clr:1; + }; + uint32_t val; +} lp_clkrst_reset_cause_reg_t; + +/** Type of cpu_reset register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** rtc_wdt_cpu_reset_length : R/W; bitpos: [24:22]; default: 1; + * need_des + */ + uint32_t rtc_wdt_cpu_reset_length:3; + /** rtc_wdt_cpu_reset_en : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t rtc_wdt_cpu_reset_en:1; + /** cpu_stall_wait : R/W; bitpos: [30:26]; default: 1; + * need_des + */ + uint32_t cpu_stall_wait:5; + /** cpu_stall_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t cpu_stall_en:1; + }; + uint32_t val; +} lp_clkrst_cpu_reset_reg_t; + +/** Type of fosc_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** fosc_dfreq : R/W; bitpos: [31:22]; default: 172; + * need_des + */ + uint32_t fosc_dfreq:10; + }; + uint32_t val; +} lp_clkrst_fosc_cntl_reg_t; + +/** Type of rc32k_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** rc32k_dfreq : R/W; bitpos: [31:22]; default: 172; + * need_des + */ + uint32_t rc32k_dfreq:10; + }; + uint32_t val; +} lp_clkrst_rc32k_cntl_reg_t; + +/** Type of clk_to_hp register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1; + * need_des + */ + uint32_t icg_hp_xtal32k:1; + /** icg_hp_sosc : R/W; bitpos: [29]; default: 1; + * need_des + */ + uint32_t icg_hp_sosc:1; + /** icg_hp_osc32k : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t icg_hp_osc32k:1; + /** icg_hp_fosc : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t icg_hp_fosc:1; + }; + uint32_t val; +} lp_clkrst_clk_to_hp_reg_t; + +/** Type of lpmem_force register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lpmem_clk_force_on:1; + }; + uint32_t val; +} lp_clkrst_lpmem_force_reg_t; + +/** Type of lpperi register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** lp_i2c_clk_sel : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_i2c_clk_sel:1; + /** lp_uart_clk_sel : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_uart_clk_sel:1; + }; + uint32_t val; +} lp_clkrst_lpperi_reg_t; + +/** Type of xtal32k register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** dres_xtal32k : R/W; bitpos: [24:22]; default: 3; + * need_des + */ + uint32_t dres_xtal32k:3; + /** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3; + * need_des + */ + uint32_t dgm_xtal32k:3; + /** dbuf_xtal32k : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t dbuf_xtal32k:1; + /** dac_xtal32k : R/W; bitpos: [31:29]; default: 3; + * need_des + */ + uint32_t dac_xtal32k:3; + }; + uint32_t val; +} lp_clkrst_xtal32k_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** clkrst_date : R/W; bitpos: [30:0]; default: 35676304; + * need_des + */ + uint32_t clkrst_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_clkrst_date_reg_t; + + +typedef struct lp_clkrst_dev_t { + volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf; + volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en; + volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en; + volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en; + volatile lp_clkrst_reset_cause_reg_t reset_cause; + volatile lp_clkrst_cpu_reset_reg_t cpu_reset; + volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl; + volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl; + volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp; + volatile lp_clkrst_lpmem_force_reg_t lpmem_force; + volatile lp_clkrst_lpperi_reg_t lpperi; + volatile lp_clkrst_xtal32k_reg_t xtal32k; + uint32_t reserved_030[243]; + volatile lp_clkrst_date_reg_t date; +} lp_clkrst_dev_t; + +extern lp_clkrst_dev_t LP_CLKRST; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_i2c_ana_mst_reg.h b/components/soc/esp32c6/include/soc/lp_i2c_ana_mst_reg.h new file mode 100644 index 0000000000..20b432ea53 --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_i2c_ana_mst_reg.h @@ -0,0 +1,135 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_I2C_ANA_MST_I2C0_CTRL_REG register + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x0) +/** LP_I2C_ANA_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_CTRL 0x01FFFFFFU +#define LP_I2C_ANA_MST_I2C0_CTRL_M (LP_I2C_ANA_MST_I2C0_CTRL_V << LP_I2C_ANA_MST_I2C0_CTRL_S) +#define LP_I2C_ANA_MST_I2C0_CTRL_V 0x01FFFFFFU +#define LP_I2C_ANA_MST_I2C0_CTRL_S 0 +/** LP_I2C_ANA_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_BUSY (BIT(25)) +#define LP_I2C_ANA_MST_I2C0_BUSY_M (LP_I2C_ANA_MST_I2C0_BUSY_V << LP_I2C_ANA_MST_I2C0_BUSY_S) +#define LP_I2C_ANA_MST_I2C0_BUSY_V 0x00000001U +#define LP_I2C_ANA_MST_I2C0_BUSY_S 25 + +/** LP_I2C_ANA_MST_I2C0_CONF_REG register + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_CONF_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x4) +/** LP_I2C_ANA_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_CONF 0x00FFFFFFU +#define LP_I2C_ANA_MST_I2C0_CONF_M (LP_I2C_ANA_MST_I2C0_CONF_V << LP_I2C_ANA_MST_I2C0_CONF_S) +#define LP_I2C_ANA_MST_I2C0_CONF_V 0x00FFFFFFU +#define LP_I2C_ANA_MST_I2C0_CONF_S 0 +/** LP_I2C_ANA_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 7; + * reserved + */ +#define LP_I2C_ANA_MST_I2C0_STATUS 0x000000FFU +#define LP_I2C_ANA_MST_I2C0_STATUS_M (LP_I2C_ANA_MST_I2C0_STATUS_V << LP_I2C_ANA_MST_I2C0_STATUS_S) +#define LP_I2C_ANA_MST_I2C0_STATUS_V 0x000000FFU +#define LP_I2C_ANA_MST_I2C0_STATUS_S 24 + +/** LP_I2C_ANA_MST_I2C0_DATA_REG register + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_DATA_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x8) +/** LP_I2C_ANA_MST_I2C0_RDATA : RO; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_RDATA 0x000000FFU +#define LP_I2C_ANA_MST_I2C0_RDATA_M (LP_I2C_ANA_MST_I2C0_RDATA_V << LP_I2C_ANA_MST_I2C0_RDATA_S) +#define LP_I2C_ANA_MST_I2C0_RDATA_V 0x000000FFU +#define LP_I2C_ANA_MST_I2C0_RDATA_S 0 +/** LP_I2C_ANA_MST_I2C0_CLK_SEL : R/W; bitpos: [10:8]; default: 1; + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_CLK_SEL 0x00000007U +#define LP_I2C_ANA_MST_I2C0_CLK_SEL_M (LP_I2C_ANA_MST_I2C0_CLK_SEL_V << LP_I2C_ANA_MST_I2C0_CLK_SEL_S) +#define LP_I2C_ANA_MST_I2C0_CLK_SEL_V 0x00000007U +#define LP_I2C_ANA_MST_I2C0_CLK_SEL_S 8 +/** LP_I2C_ANA_MST_I2C_MST_SEL : R/W; bitpos: [11]; default: 1; + * need des + */ +#define LP_I2C_ANA_MST_I2C_MST_SEL (BIT(11)) +#define LP_I2C_ANA_MST_I2C_MST_SEL_M (LP_I2C_ANA_MST_I2C_MST_SEL_V << LP_I2C_ANA_MST_I2C_MST_SEL_S) +#define LP_I2C_ANA_MST_I2C_MST_SEL_V 0x00000001U +#define LP_I2C_ANA_MST_I2C_MST_SEL_S 11 + +/** LP_I2C_ANA_MST_ANA_CONF1_REG register + * need_des + */ +#define LP_I2C_ANA_MST_ANA_CONF1_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0xc) +/** LP_I2C_ANA_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_ANA_CONF1 0x00FFFFFFU +#define LP_I2C_ANA_MST_ANA_CONF1_M (LP_I2C_ANA_MST_ANA_CONF1_V << LP_I2C_ANA_MST_ANA_CONF1_S) +#define LP_I2C_ANA_MST_ANA_CONF1_V 0x00FFFFFFU +#define LP_I2C_ANA_MST_ANA_CONF1_S 0 + +/** LP_I2C_ANA_MST_NOUSE_REG register + * need_des + */ +#define LP_I2C_ANA_MST_NOUSE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x10) +/** LP_I2C_ANA_MST_I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_I2C_MST_NOUSE 0xFFFFFFFFU +#define LP_I2C_ANA_MST_I2C_MST_NOUSE_M (LP_I2C_ANA_MST_I2C_MST_NOUSE_V << LP_I2C_ANA_MST_I2C_MST_NOUSE_S) +#define LP_I2C_ANA_MST_I2C_MST_NOUSE_V 0xFFFFFFFFU +#define LP_I2C_ANA_MST_I2C_MST_NOUSE_S 0 + +/** LP_I2C_ANA_MST_DEVICE_EN_REG register + * need_des + */ +#define LP_I2C_ANA_MST_DEVICE_EN_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x14) +/** LP_I2C_ANA_MST_I2C_DEVICE_EN : R/W; bitpos: [11:0]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_I2C_DEVICE_EN 0x00000FFFU +#define LP_I2C_ANA_MST_I2C_DEVICE_EN_M (LP_I2C_ANA_MST_I2C_DEVICE_EN_V << LP_I2C_ANA_MST_I2C_DEVICE_EN_S) +#define LP_I2C_ANA_MST_I2C_DEVICE_EN_V 0x00000FFFU +#define LP_I2C_ANA_MST_I2C_DEVICE_EN_S 0 + +/** LP_I2C_ANA_MST_DATE_REG register + * need_des + */ +#define LP_I2C_ANA_MST_DATE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x3fc) +/** LP_I2C_ANA_MST_I2C_MAT_DATE : R/W; bitpos: [27:0]; default: 33583873; + * need_des + */ +#define LP_I2C_ANA_MST_I2C_MAT_DATE 0x0FFFFFFFU +#define LP_I2C_ANA_MST_I2C_MAT_DATE_M (LP_I2C_ANA_MST_I2C_MAT_DATE_V << LP_I2C_ANA_MST_I2C_MAT_DATE_S) +#define LP_I2C_ANA_MST_I2C_MAT_DATE_V 0x0FFFFFFFU +#define LP_I2C_ANA_MST_I2C_MAT_DATE_S 0 +/** LP_I2C_ANA_MST_I2C_MAT_CLK_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN (BIT(28)) +#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_M (LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V << LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S) +#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V 0x00000001U +#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S 28 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_i2c_ana_mst_struct.h b/components/soc/esp32c6/include/soc/lp_i2c_ana_mst_struct.h new file mode 100644 index 0000000000..86d7c9dd45 --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_i2c_ana_mst_struct.h @@ -0,0 +1,150 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of i2c0_ctrl register + * need_des + */ +typedef union { + struct { + /** i2c0_ctrl : R/W; bitpos: [24:0]; default: 0; + * need_des + */ + uint32_t i2c0_ctrl:25; + /** i2c0_busy : RO; bitpos: [25]; default: 0; + * need_des + */ + uint32_t i2c0_busy:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} lp_i2c_ana_mst_i2c0_ctrl_reg_t; + +/** Type of i2c0_conf register + * need_des + */ +typedef union { + struct { + /** i2c0_conf : R/W; bitpos: [23:0]; default: 0; + * need_des + */ + uint32_t i2c0_conf:24; + /** i2c0_status : RO; bitpos: [31:24]; default: 7; + * reserved + */ + uint32_t i2c0_status:8; + }; + uint32_t val; +} lp_i2c_ana_mst_i2c0_conf_reg_t; + +/** Type of i2c0_data register + * need_des + */ +typedef union { + struct { + /** i2c0_rdata : RO; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t i2c0_rdata:8; + /** i2c0_clk_sel : R/W; bitpos: [10:8]; default: 1; + * need_des + */ + uint32_t i2c0_clk_sel:3; + /** i2c_mst_sel : R/W; bitpos: [11]; default: 1; + * need des + */ + uint32_t i2c_mst_sel:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_i2c_ana_mst_i2c0_data_reg_t; + +/** Type of ana_conf1 register + * need_des + */ +typedef union { + struct { + /** ana_conf1 : R/W; bitpos: [23:0]; default: 0; + * need_des + */ + uint32_t ana_conf1:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} lp_i2c_ana_mst_ana_conf1_reg_t; + +/** Type of nouse register + * need_des + */ +typedef union { + struct { + /** i2c_mst_nouse : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t i2c_mst_nouse:32; + }; + uint32_t val; +} lp_i2c_ana_mst_nouse_reg_t; + +/** Type of device_en register + * need_des + */ +typedef union { + struct { + /** i2c_device_en : R/W; bitpos: [11:0]; default: 0; + * need_des + */ + uint32_t i2c_device_en:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_i2c_ana_mst_device_en_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** i2c_mat_date : R/W; bitpos: [27:0]; default: 33583873; + * need_des + */ + uint32_t i2c_mat_date:28; + /** i2c_mat_clk_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t i2c_mat_clk_en:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} lp_i2c_ana_mst_date_reg_t; + + +typedef struct lp_i2c_ana_mst_dev_t { + volatile lp_i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl; + volatile lp_i2c_ana_mst_i2c0_conf_reg_t i2c0_conf; + volatile lp_i2c_ana_mst_i2c0_data_reg_t i2c0_data; + volatile lp_i2c_ana_mst_ana_conf1_reg_t ana_conf1; + volatile lp_i2c_ana_mst_nouse_reg_t nouse; + volatile lp_i2c_ana_mst_device_en_reg_t device_en; + uint32_t reserved_018[249]; + volatile lp_i2c_ana_mst_date_reg_t date; +} lp_i2c_ana_mst_dev_t; + +extern lp_i2c_ana_mst_dev_t LP_I2C_ANA_MST; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_i2c_ana_mst_dev_t) == 0x400, "Invalid size of lp_i2c_ana_mst_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_i2c_reg.h b/components/soc/esp32c6/include/soc/lp_i2c_reg.h new file mode 100644 index 0000000000..53030da190 --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_i2c_reg.h @@ -0,0 +1,1235 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_I2C_SCL_LOW_PERIOD_REG register + * Configures the low level width of the SCL + * Clock + */ +#define LP_I2C_SCL_LOW_PERIOD_REG (DR_REG_LP_I2C_BASE + 0x0) +/** LP_I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SCL remains low in master mode, in + * I2C module clock cycles. + */ +#define LP_I2C_SCL_LOW_PERIOD 0x000001FFU +#define LP_I2C_SCL_LOW_PERIOD_M (LP_I2C_SCL_LOW_PERIOD_V << LP_I2C_SCL_LOW_PERIOD_S) +#define LP_I2C_SCL_LOW_PERIOD_V 0x000001FFU +#define LP_I2C_SCL_LOW_PERIOD_S 0 + +/** LP_I2C_CTR_REG register + * Transmission setting + */ +#define LP_I2C_CTR_REG (DR_REG_LP_I2C_BASE + 0x4) +/** LP_I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0; + * 1: direct output, 0: open drain output. + */ +#define LP_I2C_SDA_FORCE_OUT (BIT(0)) +#define LP_I2C_SDA_FORCE_OUT_M (LP_I2C_SDA_FORCE_OUT_V << LP_I2C_SDA_FORCE_OUT_S) +#define LP_I2C_SDA_FORCE_OUT_V 0x00000001U +#define LP_I2C_SDA_FORCE_OUT_S 0 +/** LP_I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0; + * 1: direct output, 0: open drain output. + */ +#define LP_I2C_SCL_FORCE_OUT (BIT(1)) +#define LP_I2C_SCL_FORCE_OUT_M (LP_I2C_SCL_FORCE_OUT_V << LP_I2C_SCL_FORCE_OUT_S) +#define LP_I2C_SCL_FORCE_OUT_V 0x00000001U +#define LP_I2C_SCL_FORCE_OUT_S 1 +/** LP_I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; + * This register is used to select the sample mode. + * 1: sample SDA data on the SCL low level. + * 0: sample SDA data on the SCL high level. + */ +#define LP_I2C_SAMPLE_SCL_LEVEL (BIT(2)) +#define LP_I2C_SAMPLE_SCL_LEVEL_M (LP_I2C_SAMPLE_SCL_LEVEL_V << LP_I2C_SAMPLE_SCL_LEVEL_S) +#define LP_I2C_SAMPLE_SCL_LEVEL_V 0x00000001U +#define LP_I2C_SAMPLE_SCL_LEVEL_S 2 +/** LP_I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; + * This register is used to configure the ACK value that need to sent by master when + * the rx_fifo_cnt has reached the threshold. + */ +#define LP_I2C_RX_FULL_ACK_LEVEL (BIT(3)) +#define LP_I2C_RX_FULL_ACK_LEVEL_M (LP_I2C_RX_FULL_ACK_LEVEL_V << LP_I2C_RX_FULL_ACK_LEVEL_S) +#define LP_I2C_RX_FULL_ACK_LEVEL_V 0x00000001U +#define LP_I2C_RX_FULL_ACK_LEVEL_S 3 +/** LP_I2C_TRANS_START : WT; bitpos: [5]; default: 0; + * Set this bit to start sending the data in txfifo. + */ +#define LP_I2C_TRANS_START (BIT(5)) +#define LP_I2C_TRANS_START_M (LP_I2C_TRANS_START_V << LP_I2C_TRANS_START_S) +#define LP_I2C_TRANS_START_V 0x00000001U +#define LP_I2C_TRANS_START_S 5 +/** LP_I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; + * This bit is used to control the sending mode for data needing to be sent. + * 1: send data from the least significant bit, + * 0: send data from the most significant bit. + */ +#define LP_I2C_TX_LSB_FIRST (BIT(6)) +#define LP_I2C_TX_LSB_FIRST_M (LP_I2C_TX_LSB_FIRST_V << LP_I2C_TX_LSB_FIRST_S) +#define LP_I2C_TX_LSB_FIRST_V 0x00000001U +#define LP_I2C_TX_LSB_FIRST_S 6 +/** LP_I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; + * This bit is used to control the storage mode for received data. + * 1: receive data from the least significant bit, + * 0: receive data from the most significant bit. + */ +#define LP_I2C_RX_LSB_FIRST (BIT(7)) +#define LP_I2C_RX_LSB_FIRST_M (LP_I2C_RX_LSB_FIRST_V << LP_I2C_RX_LSB_FIRST_S) +#define LP_I2C_RX_LSB_FIRST_V 0x00000001U +#define LP_I2C_RX_LSB_FIRST_S 7 +/** LP_I2C_CLK_EN : R/W; bitpos: [8]; default: 0; + * Reserved + */ +#define LP_I2C_CLK_EN (BIT(8)) +#define LP_I2C_CLK_EN_M (LP_I2C_CLK_EN_V << LP_I2C_CLK_EN_S) +#define LP_I2C_CLK_EN_V 0x00000001U +#define LP_I2C_CLK_EN_S 8 +/** LP_I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; + * This is the enable bit for arbitration_lost. + */ +#define LP_I2C_ARBITRATION_EN (BIT(9)) +#define LP_I2C_ARBITRATION_EN_M (LP_I2C_ARBITRATION_EN_V << LP_I2C_ARBITRATION_EN_S) +#define LP_I2C_ARBITRATION_EN_V 0x00000001U +#define LP_I2C_ARBITRATION_EN_S 9 +/** LP_I2C_FSM_RST : WT; bitpos: [10]; default: 0; + * This register is used to reset the scl FMS. + */ +#define LP_I2C_FSM_RST (BIT(10)) +#define LP_I2C_FSM_RST_M (LP_I2C_FSM_RST_V << LP_I2C_FSM_RST_S) +#define LP_I2C_FSM_RST_V 0x00000001U +#define LP_I2C_FSM_RST_S 10 +/** LP_I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; + * synchronization bit + */ +#define LP_I2C_CONF_UPGATE (BIT(11)) +#define LP_I2C_CONF_UPGATE_M (LP_I2C_CONF_UPGATE_V << LP_I2C_CONF_UPGATE_S) +#define LP_I2C_CONF_UPGATE_V 0x00000001U +#define LP_I2C_CONF_UPGATE_S 11 + +/** LP_I2C_SR_REG register + * Describe I2C work status. + */ +#define LP_I2C_SR_REG (DR_REG_LP_I2C_BASE + 0x8) +/** LP_I2C_RESP_REC : RO; bitpos: [0]; default: 0; + * The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + */ +#define LP_I2C_RESP_REC (BIT(0)) +#define LP_I2C_RESP_REC_M (LP_I2C_RESP_REC_V << LP_I2C_RESP_REC_S) +#define LP_I2C_RESP_REC_V 0x00000001U +#define LP_I2C_RESP_REC_S 0 +/** LP_I2C_ARB_LOST : RO; bitpos: [3]; default: 0; + * When the I2C controller loses control of SCL line, this register changes to 1. + */ +#define LP_I2C_ARB_LOST (BIT(3)) +#define LP_I2C_ARB_LOST_M (LP_I2C_ARB_LOST_V << LP_I2C_ARB_LOST_S) +#define LP_I2C_ARB_LOST_V 0x00000001U +#define LP_I2C_ARB_LOST_S 3 +/** LP_I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; + * 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. + */ +#define LP_I2C_BUS_BUSY (BIT(4)) +#define LP_I2C_BUS_BUSY_M (LP_I2C_BUS_BUSY_V << LP_I2C_BUS_BUSY_S) +#define LP_I2C_BUS_BUSY_V 0x00000001U +#define LP_I2C_BUS_BUSY_S 4 +/** LP_I2C_RXFIFO_CNT : RO; bitpos: [12:8]; default: 0; + * This field represents the amount of data needed to be sent. + */ +#define LP_I2C_RXFIFO_CNT 0x0000001FU +#define LP_I2C_RXFIFO_CNT_M (LP_I2C_RXFIFO_CNT_V << LP_I2C_RXFIFO_CNT_S) +#define LP_I2C_RXFIFO_CNT_V 0x0000001FU +#define LP_I2C_RXFIFO_CNT_S 8 +/** LP_I2C_TXFIFO_CNT : RO; bitpos: [22:18]; default: 0; + * This field stores the amount of received data in RAM. + */ +#define LP_I2C_TXFIFO_CNT 0x0000001FU +#define LP_I2C_TXFIFO_CNT_M (LP_I2C_TXFIFO_CNT_V << LP_I2C_TXFIFO_CNT_S) +#define LP_I2C_TXFIFO_CNT_V 0x0000001FU +#define LP_I2C_TXFIFO_CNT_S 18 +/** LP_I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; + * This field indicates the states of the I2C module state machine. + * 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: + * Wait ACK + */ +#define LP_I2C_SCL_MAIN_STATE_LAST 0x00000007U +#define LP_I2C_SCL_MAIN_STATE_LAST_M (LP_I2C_SCL_MAIN_STATE_LAST_V << LP_I2C_SCL_MAIN_STATE_LAST_S) +#define LP_I2C_SCL_MAIN_STATE_LAST_V 0x00000007U +#define LP_I2C_SCL_MAIN_STATE_LAST_S 24 +/** LP_I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; + * This field indicates the states of the state machine used to produce SCL. + * 0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop + */ +#define LP_I2C_SCL_STATE_LAST 0x00000007U +#define LP_I2C_SCL_STATE_LAST_M (LP_I2C_SCL_STATE_LAST_V << LP_I2C_SCL_STATE_LAST_S) +#define LP_I2C_SCL_STATE_LAST_V 0x00000007U +#define LP_I2C_SCL_STATE_LAST_S 28 + +/** LP_I2C_TO_REG register + * Setting time out control for receiving data. + */ +#define LP_I2C_TO_REG (DR_REG_LP_I2C_BASE + 0xc) +/** LP_I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; + * This register is used to configure the timeout for receiving a data bit in APB + * clock cycles. + */ +#define LP_I2C_TIME_OUT_VALUE 0x0000001FU +#define LP_I2C_TIME_OUT_VALUE_M (LP_I2C_TIME_OUT_VALUE_V << LP_I2C_TIME_OUT_VALUE_S) +#define LP_I2C_TIME_OUT_VALUE_V 0x0000001FU +#define LP_I2C_TIME_OUT_VALUE_S 0 +/** LP_I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; + * This is the enable bit for time out control. + */ +#define LP_I2C_TIME_OUT_EN (BIT(5)) +#define LP_I2C_TIME_OUT_EN_M (LP_I2C_TIME_OUT_EN_V << LP_I2C_TIME_OUT_EN_S) +#define LP_I2C_TIME_OUT_EN_V 0x00000001U +#define LP_I2C_TIME_OUT_EN_S 5 + +/** LP_I2C_FIFO_ST_REG register + * FIFO status register. + */ +#define LP_I2C_FIFO_ST_REG (DR_REG_LP_I2C_BASE + 0x14) +/** LP_I2C_RXFIFO_RADDR : RO; bitpos: [3:0]; default: 0; + * This is the offset address of the APB reading from rxfifo + */ +#define LP_I2C_RXFIFO_RADDR 0x0000000FU +#define LP_I2C_RXFIFO_RADDR_M (LP_I2C_RXFIFO_RADDR_V << LP_I2C_RXFIFO_RADDR_S) +#define LP_I2C_RXFIFO_RADDR_V 0x0000000FU +#define LP_I2C_RXFIFO_RADDR_S 0 +/** LP_I2C_RXFIFO_WADDR : RO; bitpos: [8:5]; default: 0; + * This is the offset address of i2c module receiving data and writing to rxfifo. + */ +#define LP_I2C_RXFIFO_WADDR 0x0000000FU +#define LP_I2C_RXFIFO_WADDR_M (LP_I2C_RXFIFO_WADDR_V << LP_I2C_RXFIFO_WADDR_S) +#define LP_I2C_RXFIFO_WADDR_V 0x0000000FU +#define LP_I2C_RXFIFO_WADDR_S 5 +/** LP_I2C_TXFIFO_RADDR : RO; bitpos: [13:10]; default: 0; + * This is the offset address of i2c module reading from txfifo. + */ +#define LP_I2C_TXFIFO_RADDR 0x0000000FU +#define LP_I2C_TXFIFO_RADDR_M (LP_I2C_TXFIFO_RADDR_V << LP_I2C_TXFIFO_RADDR_S) +#define LP_I2C_TXFIFO_RADDR_V 0x0000000FU +#define LP_I2C_TXFIFO_RADDR_S 10 +/** LP_I2C_TXFIFO_WADDR : RO; bitpos: [18:15]; default: 0; + * This is the offset address of APB bus writing to txfifo. + */ +#define LP_I2C_TXFIFO_WADDR 0x0000000FU +#define LP_I2C_TXFIFO_WADDR_M (LP_I2C_TXFIFO_WADDR_V << LP_I2C_TXFIFO_WADDR_S) +#define LP_I2C_TXFIFO_WADDR_V 0x0000000FU +#define LP_I2C_TXFIFO_WADDR_S 15 + +/** LP_I2C_FIFO_CONF_REG register + * FIFO configuration register. + */ +#define LP_I2C_FIFO_CONF_REG (DR_REG_LP_I2C_BASE + 0x18) +/** LP_I2C_RXFIFO_WM_THRHD : R/W; bitpos: [3:0]; default: 6; + * The water mark threshold of rx FIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than + * reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. + */ +#define LP_I2C_RXFIFO_WM_THRHD 0x0000000FU +#define LP_I2C_RXFIFO_WM_THRHD_M (LP_I2C_RXFIFO_WM_THRHD_V << LP_I2C_RXFIFO_WM_THRHD_S) +#define LP_I2C_RXFIFO_WM_THRHD_V 0x0000000FU +#define LP_I2C_RXFIFO_WM_THRHD_S 0 +/** LP_I2C_TXFIFO_WM_THRHD : R/W; bitpos: [8:5]; default: 2; + * The water mark threshold of tx FIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than + * reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. + */ +#define LP_I2C_TXFIFO_WM_THRHD 0x0000000FU +#define LP_I2C_TXFIFO_WM_THRHD_M (LP_I2C_TXFIFO_WM_THRHD_V << LP_I2C_TXFIFO_WM_THRHD_S) +#define LP_I2C_TXFIFO_WM_THRHD_V 0x0000000FU +#define LP_I2C_TXFIFO_WM_THRHD_S 5 +/** LP_I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0; + * Set this bit to enable APB nonfifo access. + */ +#define LP_I2C_NONFIFO_EN (BIT(10)) +#define LP_I2C_NONFIFO_EN_M (LP_I2C_NONFIFO_EN_V << LP_I2C_NONFIFO_EN_S) +#define LP_I2C_NONFIFO_EN_V 0x00000001U +#define LP_I2C_NONFIFO_EN_S 10 +/** LP_I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; + * Set this bit to reset rx-fifo. + */ +#define LP_I2C_RX_FIFO_RST (BIT(12)) +#define LP_I2C_RX_FIFO_RST_M (LP_I2C_RX_FIFO_RST_V << LP_I2C_RX_FIFO_RST_S) +#define LP_I2C_RX_FIFO_RST_V 0x00000001U +#define LP_I2C_RX_FIFO_RST_S 12 +/** LP_I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; + * Set this bit to reset tx-fifo. + */ +#define LP_I2C_TX_FIFO_RST (BIT(13)) +#define LP_I2C_TX_FIFO_RST_M (LP_I2C_TX_FIFO_RST_V << LP_I2C_TX_FIFO_RST_S) +#define LP_I2C_TX_FIFO_RST_V 0x00000001U +#define LP_I2C_TX_FIFO_RST_S 13 +/** LP_I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; + * The control enable bit of FIFO pointer in non-fifo access mode. This bit controls + * the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. + */ +#define LP_I2C_FIFO_PRT_EN (BIT(14)) +#define LP_I2C_FIFO_PRT_EN_M (LP_I2C_FIFO_PRT_EN_V << LP_I2C_FIFO_PRT_EN_S) +#define LP_I2C_FIFO_PRT_EN_V 0x00000001U +#define LP_I2C_FIFO_PRT_EN_S 14 + +/** LP_I2C_DATA_REG register + * Rx FIFO read data. + */ +#define LP_I2C_DATA_REG (DR_REG_LP_I2C_BASE + 0x1c) +/** LP_I2C_FIFO_RDATA : RO; bitpos: [7:0]; default: 0; + * The value of rx FIFO read data. + */ +#define LP_I2C_FIFO_RDATA 0x000000FFU +#define LP_I2C_FIFO_RDATA_M (LP_I2C_FIFO_RDATA_V << LP_I2C_FIFO_RDATA_S) +#define LP_I2C_FIFO_RDATA_V 0x000000FFU +#define LP_I2C_FIFO_RDATA_S 0 + +/** LP_I2C_INT_RAW_REG register + * Raw interrupt status + */ +#define LP_I2C_INT_RAW_REG (DR_REG_LP_I2C_BASE + 0x20) +/** LP_I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt bit for LP_I2C_RXFIFO_WM_INT interrupt. + */ +#define LP_I2C_RXFIFO_WM_INT_RAW (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_RAW_M (LP_I2C_RXFIFO_WM_INT_RAW_V << LP_I2C_RXFIFO_WM_INT_RAW_S) +#define LP_I2C_RXFIFO_WM_INT_RAW_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_RAW_S 0 +/** LP_I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt bit for LP_I2C_TXFIFO_WM_INT interrupt. + */ +#define LP_I2C_TXFIFO_WM_INT_RAW (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_RAW_M (LP_I2C_TXFIFO_WM_INT_RAW_V << LP_I2C_TXFIFO_WM_INT_RAW_S) +#define LP_I2C_TXFIFO_WM_INT_RAW_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_RAW_S 1 +/** LP_I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt bit for LP_I2C_RXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_RXFIFO_OVF_INT_RAW (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_RAW_M (LP_I2C_RXFIFO_OVF_INT_RAW_V << LP_I2C_RXFIFO_OVF_INT_RAW_S) +#define LP_I2C_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_RAW_S 2 +/** LP_I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt bit for the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_END_DETECT_INT_RAW (BIT(3)) +#define LP_I2C_END_DETECT_INT_RAW_M (LP_I2C_END_DETECT_INT_RAW_V << LP_I2C_END_DETECT_INT_RAW_S) +#define LP_I2C_END_DETECT_INT_RAW_V 0x00000001U +#define LP_I2C_END_DETECT_INT_RAW_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt bit for the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_M (LP_I2C_BYTE_TRANS_DONE_INT_RAW_V << LP_I2C_BYTE_TRANS_DONE_INT_RAW_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt bit for the LP_I2C_ARBITRATION_LOST_INT interrupt. + */ +#define LP_I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_RAW_M (LP_I2C_ARBITRATION_LOST_INT_RAW_V << LP_I2C_ARBITRATION_LOST_INT_RAW_S) +#define LP_I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_RAW_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt bit for LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_M (LP_I2C_MST_TXFIFO_UDF_INT_RAW_V << LP_I2C_MST_TXFIFO_UDF_INT_RAW_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt bit for the LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_RAW_M (LP_I2C_TRANS_COMPLETE_INT_RAW_V << LP_I2C_TRANS_COMPLETE_INT_RAW_S) +#define LP_I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_RAW_S 7 +/** LP_I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt bit for the LP_I2C_TIME_OUT_INT interrupt. + */ +#define LP_I2C_TIME_OUT_INT_RAW (BIT(8)) +#define LP_I2C_TIME_OUT_INT_RAW_M (LP_I2C_TIME_OUT_INT_RAW_V << LP_I2C_TIME_OUT_INT_RAW_S) +#define LP_I2C_TIME_OUT_INT_RAW_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_RAW_S 8 +/** LP_I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt bit for the LP_I2C_TRANS_START_INT interrupt. + */ +#define LP_I2C_TRANS_START_INT_RAW (BIT(9)) +#define LP_I2C_TRANS_START_INT_RAW_M (LP_I2C_TRANS_START_INT_RAW_V << LP_I2C_TRANS_START_INT_RAW_S) +#define LP_I2C_TRANS_START_INT_RAW_V 0x00000001U +#define LP_I2C_TRANS_START_INT_RAW_S 9 +/** LP_I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt bit for LP_I2C_SLAVE_STRETCH_INT interrupt. + */ +#define LP_I2C_NACK_INT_RAW (BIT(10)) +#define LP_I2C_NACK_INT_RAW_M (LP_I2C_NACK_INT_RAW_V << LP_I2C_NACK_INT_RAW_S) +#define LP_I2C_NACK_INT_RAW_V 0x00000001U +#define LP_I2C_NACK_INT_RAW_S 10 +/** LP_I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt bit for LP_I2C_TXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_TXFIFO_OVF_INT_RAW (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_RAW_M (LP_I2C_TXFIFO_OVF_INT_RAW_V << LP_I2C_TXFIFO_OVF_INT_RAW_S) +#define LP_I2C_TXFIFO_OVF_INT_RAW_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_RAW_S 11 +/** LP_I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt bit for LP_I2C_RXFIFO_UDF_INT interrupt. + */ +#define LP_I2C_RXFIFO_UDF_INT_RAW (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_RAW_M (LP_I2C_RXFIFO_UDF_INT_RAW_V << LP_I2C_RXFIFO_UDF_INT_RAW_S) +#define LP_I2C_RXFIFO_UDF_INT_RAW_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_RAW_S 12 +/** LP_I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt bit for LP_I2C_SCL_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_ST_TO_INT_RAW (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_RAW_M (LP_I2C_SCL_ST_TO_INT_RAW_V << LP_I2C_SCL_ST_TO_INT_RAW_S) +#define LP_I2C_SCL_ST_TO_INT_RAW_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_RAW_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt bit for LP_I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_M (LP_I2C_SCL_MAIN_ST_TO_INT_RAW_V << LP_I2C_SCL_MAIN_ST_TO_INT_RAW_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 +/** LP_I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt bit for LP_I2C_DET_START_INT interrupt. + */ +#define LP_I2C_DET_START_INT_RAW (BIT(15)) +#define LP_I2C_DET_START_INT_RAW_M (LP_I2C_DET_START_INT_RAW_V << LP_I2C_DET_START_INT_RAW_S) +#define LP_I2C_DET_START_INT_RAW_V 0x00000001U +#define LP_I2C_DET_START_INT_RAW_S 15 + +/** LP_I2C_INT_CLR_REG register + * Interrupt clear bits + */ +#define LP_I2C_INT_CLR_REG (DR_REG_LP_I2C_BASE + 0x24) +/** LP_I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear LP_I2C_RXFIFO_WM_INT interrupt. + */ +#define LP_I2C_RXFIFO_WM_INT_CLR (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_CLR_M (LP_I2C_RXFIFO_WM_INT_CLR_V << LP_I2C_RXFIFO_WM_INT_CLR_S) +#define LP_I2C_RXFIFO_WM_INT_CLR_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_CLR_S 0 +/** LP_I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear LP_I2C_TXFIFO_WM_INT interrupt. + */ +#define LP_I2C_TXFIFO_WM_INT_CLR (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_CLR_M (LP_I2C_TXFIFO_WM_INT_CLR_V << LP_I2C_TXFIFO_WM_INT_CLR_S) +#define LP_I2C_TXFIFO_WM_INT_CLR_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_CLR_S 1 +/** LP_I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear LP_I2C_RXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_RXFIFO_OVF_INT_CLR (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_CLR_M (LP_I2C_RXFIFO_OVF_INT_CLR_V << LP_I2C_RXFIFO_OVF_INT_CLR_S) +#define LP_I2C_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_CLR_S 2 +/** LP_I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_END_DETECT_INT_CLR (BIT(3)) +#define LP_I2C_END_DETECT_INT_CLR_M (LP_I2C_END_DETECT_INT_CLR_V << LP_I2C_END_DETECT_INT_CLR_S) +#define LP_I2C_END_DETECT_INT_CLR_V 0x00000001U +#define LP_I2C_END_DETECT_INT_CLR_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_M (LP_I2C_BYTE_TRANS_DONE_INT_CLR_V << LP_I2C_BYTE_TRANS_DONE_INT_CLR_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the LP_I2C_ARBITRATION_LOST_INT interrupt. + */ +#define LP_I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_CLR_M (LP_I2C_ARBITRATION_LOST_INT_CLR_V << LP_I2C_ARBITRATION_LOST_INT_CLR_S) +#define LP_I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_CLR_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_M (LP_I2C_MST_TXFIFO_UDF_INT_CLR_V << LP_I2C_MST_TXFIFO_UDF_INT_CLR_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_CLR_M (LP_I2C_TRANS_COMPLETE_INT_CLR_V << LP_I2C_TRANS_COMPLETE_INT_CLR_S) +#define LP_I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_CLR_S 7 +/** LP_I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the LP_I2C_TIME_OUT_INT interrupt. + */ +#define LP_I2C_TIME_OUT_INT_CLR (BIT(8)) +#define LP_I2C_TIME_OUT_INT_CLR_M (LP_I2C_TIME_OUT_INT_CLR_V << LP_I2C_TIME_OUT_INT_CLR_S) +#define LP_I2C_TIME_OUT_INT_CLR_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_CLR_S 8 +/** LP_I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the LP_I2C_TRANS_START_INT interrupt. + */ +#define LP_I2C_TRANS_START_INT_CLR (BIT(9)) +#define LP_I2C_TRANS_START_INT_CLR_M (LP_I2C_TRANS_START_INT_CLR_V << LP_I2C_TRANS_START_INT_CLR_S) +#define LP_I2C_TRANS_START_INT_CLR_V 0x00000001U +#define LP_I2C_TRANS_START_INT_CLR_S 9 +/** LP_I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear LP_I2C_SLAVE_STRETCH_INT interrupt. + */ +#define LP_I2C_NACK_INT_CLR (BIT(10)) +#define LP_I2C_NACK_INT_CLR_M (LP_I2C_NACK_INT_CLR_V << LP_I2C_NACK_INT_CLR_S) +#define LP_I2C_NACK_INT_CLR_V 0x00000001U +#define LP_I2C_NACK_INT_CLR_S 10 +/** LP_I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear LP_I2C_TXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_TXFIFO_OVF_INT_CLR (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_CLR_M (LP_I2C_TXFIFO_OVF_INT_CLR_V << LP_I2C_TXFIFO_OVF_INT_CLR_S) +#define LP_I2C_TXFIFO_OVF_INT_CLR_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_CLR_S 11 +/** LP_I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear LP_I2C_RXFIFO_UDF_INT interrupt. + */ +#define LP_I2C_RXFIFO_UDF_INT_CLR (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_CLR_M (LP_I2C_RXFIFO_UDF_INT_CLR_V << LP_I2C_RXFIFO_UDF_INT_CLR_S) +#define LP_I2C_RXFIFO_UDF_INT_CLR_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_CLR_S 12 +/** LP_I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear LP_I2C_SCL_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_ST_TO_INT_CLR (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_CLR_M (LP_I2C_SCL_ST_TO_INT_CLR_V << LP_I2C_SCL_ST_TO_INT_CLR_S) +#define LP_I2C_SCL_ST_TO_INT_CLR_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_CLR_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear LP_I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_M (LP_I2C_SCL_MAIN_ST_TO_INT_CLR_V << LP_I2C_SCL_MAIN_ST_TO_INT_CLR_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 +/** LP_I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear LP_I2C_DET_START_INT interrupt. + */ +#define LP_I2C_DET_START_INT_CLR (BIT(15)) +#define LP_I2C_DET_START_INT_CLR_M (LP_I2C_DET_START_INT_CLR_V << LP_I2C_DET_START_INT_CLR_S) +#define LP_I2C_DET_START_INT_CLR_V 0x00000001U +#define LP_I2C_DET_START_INT_CLR_S 15 + +/** LP_I2C_INT_ENA_REG register + * Interrupt enable bits + */ +#define LP_I2C_INT_ENA_REG (DR_REG_LP_I2C_BASE + 0x28) +/** LP_I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for LP_I2C_RXFIFO_WM_INT interrupt. + */ +#define LP_I2C_RXFIFO_WM_INT_ENA (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_ENA_M (LP_I2C_RXFIFO_WM_INT_ENA_V << LP_I2C_RXFIFO_WM_INT_ENA_S) +#define LP_I2C_RXFIFO_WM_INT_ENA_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_ENA_S 0 +/** LP_I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for LP_I2C_TXFIFO_WM_INT interrupt. + */ +#define LP_I2C_TXFIFO_WM_INT_ENA (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_ENA_M (LP_I2C_TXFIFO_WM_INT_ENA_V << LP_I2C_TXFIFO_WM_INT_ENA_S) +#define LP_I2C_TXFIFO_WM_INT_ENA_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_ENA_S 1 +/** LP_I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for LP_I2C_RXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_RXFIFO_OVF_INT_ENA (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_ENA_M (LP_I2C_RXFIFO_OVF_INT_ENA_V << LP_I2C_RXFIFO_OVF_INT_ENA_S) +#define LP_I2C_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_ENA_S 2 +/** LP_I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_END_DETECT_INT_ENA (BIT(3)) +#define LP_I2C_END_DETECT_INT_ENA_M (LP_I2C_END_DETECT_INT_ENA_V << LP_I2C_END_DETECT_INT_ENA_S) +#define LP_I2C_END_DETECT_INT_ENA_V 0x00000001U +#define LP_I2C_END_DETECT_INT_ENA_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_M (LP_I2C_BYTE_TRANS_DONE_INT_ENA_V << LP_I2C_BYTE_TRANS_DONE_INT_ENA_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the LP_I2C_ARBITRATION_LOST_INT interrupt. + */ +#define LP_I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_ENA_M (LP_I2C_ARBITRATION_LOST_INT_ENA_V << LP_I2C_ARBITRATION_LOST_INT_ENA_S) +#define LP_I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_ENA_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_M (LP_I2C_MST_TXFIFO_UDF_INT_ENA_V << LP_I2C_MST_TXFIFO_UDF_INT_ENA_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_ENA_M (LP_I2C_TRANS_COMPLETE_INT_ENA_V << LP_I2C_TRANS_COMPLETE_INT_ENA_S) +#define LP_I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_ENA_S 7 +/** LP_I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the LP_I2C_TIME_OUT_INT interrupt. + */ +#define LP_I2C_TIME_OUT_INT_ENA (BIT(8)) +#define LP_I2C_TIME_OUT_INT_ENA_M (LP_I2C_TIME_OUT_INT_ENA_V << LP_I2C_TIME_OUT_INT_ENA_S) +#define LP_I2C_TIME_OUT_INT_ENA_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_ENA_S 8 +/** LP_I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the LP_I2C_TRANS_START_INT interrupt. + */ +#define LP_I2C_TRANS_START_INT_ENA (BIT(9)) +#define LP_I2C_TRANS_START_INT_ENA_M (LP_I2C_TRANS_START_INT_ENA_V << LP_I2C_TRANS_START_INT_ENA_S) +#define LP_I2C_TRANS_START_INT_ENA_V 0x00000001U +#define LP_I2C_TRANS_START_INT_ENA_S 9 +/** LP_I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for LP_I2C_SLAVE_STRETCH_INT interrupt. + */ +#define LP_I2C_NACK_INT_ENA (BIT(10)) +#define LP_I2C_NACK_INT_ENA_M (LP_I2C_NACK_INT_ENA_V << LP_I2C_NACK_INT_ENA_S) +#define LP_I2C_NACK_INT_ENA_V 0x00000001U +#define LP_I2C_NACK_INT_ENA_S 10 +/** LP_I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for LP_I2C_TXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_TXFIFO_OVF_INT_ENA (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_ENA_M (LP_I2C_TXFIFO_OVF_INT_ENA_V << LP_I2C_TXFIFO_OVF_INT_ENA_S) +#define LP_I2C_TXFIFO_OVF_INT_ENA_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_ENA_S 11 +/** LP_I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for LP_I2C_RXFIFO_UDF_INT interrupt. + */ +#define LP_I2C_RXFIFO_UDF_INT_ENA (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_ENA_M (LP_I2C_RXFIFO_UDF_INT_ENA_V << LP_I2C_RXFIFO_UDF_INT_ENA_S) +#define LP_I2C_RXFIFO_UDF_INT_ENA_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_ENA_S 12 +/** LP_I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for LP_I2C_SCL_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_ST_TO_INT_ENA (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_ENA_M (LP_I2C_SCL_ST_TO_INT_ENA_V << LP_I2C_SCL_ST_TO_INT_ENA_S) +#define LP_I2C_SCL_ST_TO_INT_ENA_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_ENA_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for LP_I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_M (LP_I2C_SCL_MAIN_ST_TO_INT_ENA_V << LP_I2C_SCL_MAIN_ST_TO_INT_ENA_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 +/** LP_I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for LP_I2C_DET_START_INT interrupt. + */ +#define LP_I2C_DET_START_INT_ENA (BIT(15)) +#define LP_I2C_DET_START_INT_ENA_M (LP_I2C_DET_START_INT_ENA_V << LP_I2C_DET_START_INT_ENA_S) +#define LP_I2C_DET_START_INT_ENA_V 0x00000001U +#define LP_I2C_DET_START_INT_ENA_S 15 + +/** LP_I2C_INT_STATUS_REG register + * Status of captured I2C communication events + */ +#define LP_I2C_INT_STATUS_REG (DR_REG_LP_I2C_BASE + 0x2c) +/** LP_I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for LP_I2C_RXFIFO_WM_INT interrupt. + */ +#define LP_I2C_RXFIFO_WM_INT_ST (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_ST_M (LP_I2C_RXFIFO_WM_INT_ST_V << LP_I2C_RXFIFO_WM_INT_ST_S) +#define LP_I2C_RXFIFO_WM_INT_ST_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_ST_S 0 +/** LP_I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for LP_I2C_TXFIFO_WM_INT interrupt. + */ +#define LP_I2C_TXFIFO_WM_INT_ST (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_ST_M (LP_I2C_TXFIFO_WM_INT_ST_V << LP_I2C_TXFIFO_WM_INT_ST_S) +#define LP_I2C_TXFIFO_WM_INT_ST_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_ST_S 1 +/** LP_I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for LP_I2C_RXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_RXFIFO_OVF_INT_ST (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_ST_M (LP_I2C_RXFIFO_OVF_INT_ST_V << LP_I2C_RXFIFO_OVF_INT_ST_S) +#define LP_I2C_RXFIFO_OVF_INT_ST_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_ST_S 2 +/** LP_I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_END_DETECT_INT_ST (BIT(3)) +#define LP_I2C_END_DETECT_INT_ST_M (LP_I2C_END_DETECT_INT_ST_V << LP_I2C_END_DETECT_INT_ST_S) +#define LP_I2C_END_DETECT_INT_ST_V 0x00000001U +#define LP_I2C_END_DETECT_INT_ST_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for the LP_I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_ST_M (LP_I2C_BYTE_TRANS_DONE_INT_ST_V << LP_I2C_BYTE_TRANS_DONE_INT_ST_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_ST_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_ST_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for the LP_I2C_ARBITRATION_LOST_INT interrupt. + */ +#define LP_I2C_ARBITRATION_LOST_INT_ST (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_ST_M (LP_I2C_ARBITRATION_LOST_INT_ST_V << LP_I2C_ARBITRATION_LOST_INT_ST_S) +#define LP_I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_ST_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_ST_M (LP_I2C_MST_TXFIFO_UDF_INT_ST_V << LP_I2C_MST_TXFIFO_UDF_INT_ST_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_ST_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_ST_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for the LP_I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_TRANS_COMPLETE_INT_ST (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_ST_M (LP_I2C_TRANS_COMPLETE_INT_ST_V << LP_I2C_TRANS_COMPLETE_INT_ST_S) +#define LP_I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_ST_S 7 +/** LP_I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for the LP_I2C_TIME_OUT_INT interrupt. + */ +#define LP_I2C_TIME_OUT_INT_ST (BIT(8)) +#define LP_I2C_TIME_OUT_INT_ST_M (LP_I2C_TIME_OUT_INT_ST_V << LP_I2C_TIME_OUT_INT_ST_S) +#define LP_I2C_TIME_OUT_INT_ST_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_ST_S 8 +/** LP_I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for the LP_I2C_TRANS_START_INT interrupt. + */ +#define LP_I2C_TRANS_START_INT_ST (BIT(9)) +#define LP_I2C_TRANS_START_INT_ST_M (LP_I2C_TRANS_START_INT_ST_V << LP_I2C_TRANS_START_INT_ST_S) +#define LP_I2C_TRANS_START_INT_ST_V 0x00000001U +#define LP_I2C_TRANS_START_INT_ST_S 9 +/** LP_I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for LP_I2C_SLAVE_STRETCH_INT interrupt. + */ +#define LP_I2C_NACK_INT_ST (BIT(10)) +#define LP_I2C_NACK_INT_ST_M (LP_I2C_NACK_INT_ST_V << LP_I2C_NACK_INT_ST_S) +#define LP_I2C_NACK_INT_ST_V 0x00000001U +#define LP_I2C_NACK_INT_ST_S 10 +/** LP_I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for LP_I2C_TXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_TXFIFO_OVF_INT_ST (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_ST_M (LP_I2C_TXFIFO_OVF_INT_ST_V << LP_I2C_TXFIFO_OVF_INT_ST_S) +#define LP_I2C_TXFIFO_OVF_INT_ST_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_ST_S 11 +/** LP_I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for LP_I2C_RXFIFO_UDF_INT interrupt. + */ +#define LP_I2C_RXFIFO_UDF_INT_ST (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_ST_M (LP_I2C_RXFIFO_UDF_INT_ST_V << LP_I2C_RXFIFO_UDF_INT_ST_S) +#define LP_I2C_RXFIFO_UDF_INT_ST_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_ST_S 12 +/** LP_I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for LP_I2C_SCL_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_ST_TO_INT_ST (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_ST_M (LP_I2C_SCL_ST_TO_INT_ST_V << LP_I2C_SCL_ST_TO_INT_ST_S) +#define LP_I2C_SCL_ST_TO_INT_ST_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_ST_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for LP_I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_M (LP_I2C_SCL_MAIN_ST_TO_INT_ST_V << LP_I2C_SCL_MAIN_ST_TO_INT_ST_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_S 14 +/** LP_I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for LP_I2C_DET_START_INT interrupt. + */ +#define LP_I2C_DET_START_INT_ST (BIT(15)) +#define LP_I2C_DET_START_INT_ST_M (LP_I2C_DET_START_INT_ST_V << LP_I2C_DET_START_INT_ST_S) +#define LP_I2C_DET_START_INT_ST_V 0x00000001U +#define LP_I2C_DET_START_INT_ST_S 15 + +/** LP_I2C_SDA_HOLD_REG register + * Configures the hold time after a negative SCL edge. + */ +#define LP_I2C_SDA_HOLD_REG (DR_REG_LP_I2C_BASE + 0x30) +/** LP_I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure the time to hold the data after the negative + * edge of SCL, in I2C module clock cycles. + */ +#define LP_I2C_SDA_HOLD_TIME 0x000001FFU +#define LP_I2C_SDA_HOLD_TIME_M (LP_I2C_SDA_HOLD_TIME_V << LP_I2C_SDA_HOLD_TIME_S) +#define LP_I2C_SDA_HOLD_TIME_V 0x000001FFU +#define LP_I2C_SDA_HOLD_TIME_S 0 + +/** LP_I2C_SDA_SAMPLE_REG register + * Configures the sample time after a positive SCL edge. + */ +#define LP_I2C_SDA_SAMPLE_REG (DR_REG_LP_I2C_BASE + 0x34) +/** LP_I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SDA is sampled, in I2C module clock + * cycles. + */ +#define LP_I2C_SDA_SAMPLE_TIME 0x000001FFU +#define LP_I2C_SDA_SAMPLE_TIME_M (LP_I2C_SDA_SAMPLE_TIME_V << LP_I2C_SDA_SAMPLE_TIME_S) +#define LP_I2C_SDA_SAMPLE_TIME_V 0x000001FFU +#define LP_I2C_SDA_SAMPLE_TIME_S 0 + +/** LP_I2C_SCL_HIGH_PERIOD_REG register + * Configures the high level width of SCL + */ +#define LP_I2C_SCL_HIGH_PERIOD_REG (DR_REG_LP_I2C_BASE + 0x38) +/** LP_I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SCL setup to high level and remains + * high in master mode, in I2C module clock cycles. + */ +#define LP_I2C_SCL_HIGH_PERIOD 0x000001FFU +#define LP_I2C_SCL_HIGH_PERIOD_M (LP_I2C_SCL_HIGH_PERIOD_V << LP_I2C_SCL_HIGH_PERIOD_S) +#define LP_I2C_SCL_HIGH_PERIOD_V 0x000001FFU +#define LP_I2C_SCL_HIGH_PERIOD_S 0 +/** LP_I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; + * This register is used to configure for the SCL_FSM's waiting period for SCL high + * level in master mode, in I2C module clock cycles. + */ +#define LP_I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU +#define LP_I2C_SCL_WAIT_HIGH_PERIOD_M (LP_I2C_SCL_WAIT_HIGH_PERIOD_V << LP_I2C_SCL_WAIT_HIGH_PERIOD_S) +#define LP_I2C_SCL_WAIT_HIGH_PERIOD_V 0x0000007FU +#define LP_I2C_SCL_WAIT_HIGH_PERIOD_S 9 + +/** LP_I2C_SCL_START_HOLD_REG register + * Configures the delay between the SDA and SCL negative edge for a start condition + */ +#define LP_I2C_SCL_START_HOLD_REG (DR_REG_LP_I2C_BASE + 0x40) +/** LP_I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the negative edge + * of SDA and the negative edge of SCL for a START condition, in I2C module clock + * cycles. + */ +#define LP_I2C_SCL_START_HOLD_TIME 0x000001FFU +#define LP_I2C_SCL_START_HOLD_TIME_M (LP_I2C_SCL_START_HOLD_TIME_V << LP_I2C_SCL_START_HOLD_TIME_S) +#define LP_I2C_SCL_START_HOLD_TIME_V 0x000001FFU +#define LP_I2C_SCL_START_HOLD_TIME_S 0 + +/** LP_I2C_SCL_RSTART_SETUP_REG register + * Configures the delay between the positive + * edge of SCL and the negative edge of SDA + */ +#define LP_I2C_SCL_RSTART_SETUP_REG (DR_REG_LP_I2C_BASE + 0x44) +/** LP_I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the positive + * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module + * clock cycles. + */ +#define LP_I2C_SCL_RSTART_SETUP_TIME 0x000001FFU +#define LP_I2C_SCL_RSTART_SETUP_TIME_M (LP_I2C_SCL_RSTART_SETUP_TIME_V << LP_I2C_SCL_RSTART_SETUP_TIME_S) +#define LP_I2C_SCL_RSTART_SETUP_TIME_V 0x000001FFU +#define LP_I2C_SCL_RSTART_SETUP_TIME_S 0 + +/** LP_I2C_SCL_STOP_HOLD_REG register + * Configures the delay after the SCL clock + * edge for a stop condition + */ +#define LP_I2C_SCL_STOP_HOLD_REG (DR_REG_LP_I2C_BASE + 0x48) +/** LP_I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the delay after the STOP condition, + * in I2C module clock cycles. + */ +#define LP_I2C_SCL_STOP_HOLD_TIME 0x000001FFU +#define LP_I2C_SCL_STOP_HOLD_TIME_M (LP_I2C_SCL_STOP_HOLD_TIME_V << LP_I2C_SCL_STOP_HOLD_TIME_S) +#define LP_I2C_SCL_STOP_HOLD_TIME_V 0x000001FFU +#define LP_I2C_SCL_STOP_HOLD_TIME_S 0 + +/** LP_I2C_SCL_STOP_SETUP_REG register + * Configures the delay between the SDA and + * SCL positive edge for a stop condition + */ +#define LP_I2C_SCL_STOP_SETUP_REG (DR_REG_LP_I2C_BASE + 0x4c) +/** LP_I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the positive edge + * of SCL and the positive edge of SDA, in I2C module clock cycles. + */ +#define LP_I2C_SCL_STOP_SETUP_TIME 0x000001FFU +#define LP_I2C_SCL_STOP_SETUP_TIME_M (LP_I2C_SCL_STOP_SETUP_TIME_V << LP_I2C_SCL_STOP_SETUP_TIME_S) +#define LP_I2C_SCL_STOP_SETUP_TIME_V 0x000001FFU +#define LP_I2C_SCL_STOP_SETUP_TIME_S 0 + +/** LP_I2C_FILTER_CFG_REG register + * SCL and SDA filter configuration register + */ +#define LP_I2C_FILTER_CFG_REG (DR_REG_LP_I2C_BASE + 0x50) +/** LP_I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0; + * When a pulse on the SCL input has smaller width than this register value + * in I2C module clock cycles, the I2C controller will ignore that pulse. + */ +#define LP_I2C_SCL_FILTER_THRES 0x0000000FU +#define LP_I2C_SCL_FILTER_THRES_M (LP_I2C_SCL_FILTER_THRES_V << LP_I2C_SCL_FILTER_THRES_S) +#define LP_I2C_SCL_FILTER_THRES_V 0x0000000FU +#define LP_I2C_SCL_FILTER_THRES_S 0 +/** LP_I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0; + * When a pulse on the SDA input has smaller width than this register value + * in I2C module clock cycles, the I2C controller will ignore that pulse. + */ +#define LP_I2C_SDA_FILTER_THRES 0x0000000FU +#define LP_I2C_SDA_FILTER_THRES_M (LP_I2C_SDA_FILTER_THRES_V << LP_I2C_SDA_FILTER_THRES_S) +#define LP_I2C_SDA_FILTER_THRES_V 0x0000000FU +#define LP_I2C_SDA_FILTER_THRES_S 4 +/** LP_I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; + * This is the filter enable bit for SCL. + */ +#define LP_I2C_SCL_FILTER_EN (BIT(8)) +#define LP_I2C_SCL_FILTER_EN_M (LP_I2C_SCL_FILTER_EN_V << LP_I2C_SCL_FILTER_EN_S) +#define LP_I2C_SCL_FILTER_EN_V 0x00000001U +#define LP_I2C_SCL_FILTER_EN_S 8 +/** LP_I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; + * This is the filter enable bit for SDA. + */ +#define LP_I2C_SDA_FILTER_EN (BIT(9)) +#define LP_I2C_SDA_FILTER_EN_M (LP_I2C_SDA_FILTER_EN_V << LP_I2C_SDA_FILTER_EN_S) +#define LP_I2C_SDA_FILTER_EN_V 0x00000001U +#define LP_I2C_SDA_FILTER_EN_S 9 + +/** LP_I2C_CLK_CONF_REG register + * I2C CLK configuration register + */ +#define LP_I2C_CLK_CONF_REG (DR_REG_LP_I2C_BASE + 0x54) +/** LP_I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * the integral part of the fractional divisor for i2c module + */ +#define LP_I2C_SCLK_DIV_NUM 0x000000FFU +#define LP_I2C_SCLK_DIV_NUM_M (LP_I2C_SCLK_DIV_NUM_V << LP_I2C_SCLK_DIV_NUM_S) +#define LP_I2C_SCLK_DIV_NUM_V 0x000000FFU +#define LP_I2C_SCLK_DIV_NUM_S 0 +/** LP_I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0; + * the numerator of the fractional part of the fractional divisor for i2c module + */ +#define LP_I2C_SCLK_DIV_A 0x0000003FU +#define LP_I2C_SCLK_DIV_A_M (LP_I2C_SCLK_DIV_A_V << LP_I2C_SCLK_DIV_A_S) +#define LP_I2C_SCLK_DIV_A_V 0x0000003FU +#define LP_I2C_SCLK_DIV_A_S 8 +/** LP_I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0; + * the denominator of the fractional part of the fractional divisor for i2c module + */ +#define LP_I2C_SCLK_DIV_B 0x0000003FU +#define LP_I2C_SCLK_DIV_B_M (LP_I2C_SCLK_DIV_B_V << LP_I2C_SCLK_DIV_B_S) +#define LP_I2C_SCLK_DIV_B_V 0x0000003FU +#define LP_I2C_SCLK_DIV_B_S 14 +/** LP_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; + * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + */ +#define LP_I2C_SCLK_SEL (BIT(20)) +#define LP_I2C_SCLK_SEL_M (LP_I2C_SCLK_SEL_V << LP_I2C_SCLK_SEL_S) +#define LP_I2C_SCLK_SEL_V 0x00000001U +#define LP_I2C_SCLK_SEL_S 20 +/** LP_I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1; + * The clock switch for i2c module + */ +#define LP_I2C_SCLK_ACTIVE (BIT(21)) +#define LP_I2C_SCLK_ACTIVE_M (LP_I2C_SCLK_ACTIVE_V << LP_I2C_SCLK_ACTIVE_S) +#define LP_I2C_SCLK_ACTIVE_V 0x00000001U +#define LP_I2C_SCLK_ACTIVE_S 21 + +/** LP_I2C_COMD0_REG register + * I2C command register 0 + */ +#define LP_I2C_COMD0_REG (DR_REG_LP_I2C_BASE + 0x58) +/** LP_I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 0. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define LP_I2C_COMMAND0 0x00003FFFU +#define LP_I2C_COMMAND0_M (LP_I2C_COMMAND0_V << LP_I2C_COMMAND0_S) +#define LP_I2C_COMMAND0_V 0x00003FFFU +#define LP_I2C_COMMAND0_S 0 +/** LP_I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 0 is done in I2C Master mode, this bit changes to high + * level. + */ +#define LP_I2C_COMMAND0_DONE (BIT(31)) +#define LP_I2C_COMMAND0_DONE_M (LP_I2C_COMMAND0_DONE_V << LP_I2C_COMMAND0_DONE_S) +#define LP_I2C_COMMAND0_DONE_V 0x00000001U +#define LP_I2C_COMMAND0_DONE_S 31 + +/** LP_I2C_COMD1_REG register + * I2C command register 1 + */ +#define LP_I2C_COMD1_REG (DR_REG_LP_I2C_BASE + 0x5c) +/** LP_I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 1. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define LP_I2C_COMMAND1 0x00003FFFU +#define LP_I2C_COMMAND1_M (LP_I2C_COMMAND1_V << LP_I2C_COMMAND1_S) +#define LP_I2C_COMMAND1_V 0x00003FFFU +#define LP_I2C_COMMAND1_S 0 +/** LP_I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 1 is done in I2C Master mode, this bit changes to high + * level. + */ +#define LP_I2C_COMMAND1_DONE (BIT(31)) +#define LP_I2C_COMMAND1_DONE_M (LP_I2C_COMMAND1_DONE_V << LP_I2C_COMMAND1_DONE_S) +#define LP_I2C_COMMAND1_DONE_V 0x00000001U +#define LP_I2C_COMMAND1_DONE_S 31 + +/** LP_I2C_COMD2_REG register + * I2C command register 2 + */ +#define LP_I2C_COMD2_REG (DR_REG_LP_I2C_BASE + 0x60) +/** LP_I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 2. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define LP_I2C_COMMAND2 0x00003FFFU +#define LP_I2C_COMMAND2_M (LP_I2C_COMMAND2_V << LP_I2C_COMMAND2_S) +#define LP_I2C_COMMAND2_V 0x00003FFFU +#define LP_I2C_COMMAND2_S 0 +/** LP_I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 2 is done in I2C Master mode, this bit changes to high + * Level. + */ +#define LP_I2C_COMMAND2_DONE (BIT(31)) +#define LP_I2C_COMMAND2_DONE_M (LP_I2C_COMMAND2_DONE_V << LP_I2C_COMMAND2_DONE_S) +#define LP_I2C_COMMAND2_DONE_V 0x00000001U +#define LP_I2C_COMMAND2_DONE_S 31 + +/** LP_I2C_COMD3_REG register + * I2C command register 3 + */ +#define LP_I2C_COMD3_REG (DR_REG_LP_I2C_BASE + 0x64) +/** LP_I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 3. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define LP_I2C_COMMAND3 0x00003FFFU +#define LP_I2C_COMMAND3_M (LP_I2C_COMMAND3_V << LP_I2C_COMMAND3_S) +#define LP_I2C_COMMAND3_V 0x00003FFFU +#define LP_I2C_COMMAND3_S 0 +/** LP_I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 3 is done in I2C Master mode, this bit changes to high + * level. + */ +#define LP_I2C_COMMAND3_DONE (BIT(31)) +#define LP_I2C_COMMAND3_DONE_M (LP_I2C_COMMAND3_DONE_V << LP_I2C_COMMAND3_DONE_S) +#define LP_I2C_COMMAND3_DONE_V 0x00000001U +#define LP_I2C_COMMAND3_DONE_S 31 + +/** LP_I2C_COMD4_REG register + * I2C command register 4 + */ +#define LP_I2C_COMD4_REG (DR_REG_LP_I2C_BASE + 0x68) +/** LP_I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 4. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define LP_I2C_COMMAND4 0x00003FFFU +#define LP_I2C_COMMAND4_M (LP_I2C_COMMAND4_V << LP_I2C_COMMAND4_S) +#define LP_I2C_COMMAND4_V 0x00003FFFU +#define LP_I2C_COMMAND4_S 0 +/** LP_I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 4 is done in I2C Master mode, this bit changes to high + * level. + */ +#define LP_I2C_COMMAND4_DONE (BIT(31)) +#define LP_I2C_COMMAND4_DONE_M (LP_I2C_COMMAND4_DONE_V << LP_I2C_COMMAND4_DONE_S) +#define LP_I2C_COMMAND4_DONE_V 0x00000001U +#define LP_I2C_COMMAND4_DONE_S 31 + +/** LP_I2C_COMD5_REG register + * I2C command register 5 + */ +#define LP_I2C_COMD5_REG (DR_REG_LP_I2C_BASE + 0x6c) +/** LP_I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 5. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define LP_I2C_COMMAND5 0x00003FFFU +#define LP_I2C_COMMAND5_M (LP_I2C_COMMAND5_V << LP_I2C_COMMAND5_S) +#define LP_I2C_COMMAND5_V 0x00003FFFU +#define LP_I2C_COMMAND5_S 0 +/** LP_I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 5 is done in I2C Master mode, this bit changes to high level. + */ +#define LP_I2C_COMMAND5_DONE (BIT(31)) +#define LP_I2C_COMMAND5_DONE_M (LP_I2C_COMMAND5_DONE_V << LP_I2C_COMMAND5_DONE_S) +#define LP_I2C_COMMAND5_DONE_V 0x00000001U +#define LP_I2C_COMMAND5_DONE_S 31 + +/** LP_I2C_COMD6_REG register + * I2C command register 6 + */ +#define LP_I2C_COMD6_REG (DR_REG_LP_I2C_BASE + 0x70) +/** LP_I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 6. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define LP_I2C_COMMAND6 0x00003FFFU +#define LP_I2C_COMMAND6_M (LP_I2C_COMMAND6_V << LP_I2C_COMMAND6_S) +#define LP_I2C_COMMAND6_V 0x00003FFFU +#define LP_I2C_COMMAND6_S 0 +/** LP_I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 6 is done in I2C Master mode, this bit changes to high level. + */ +#define LP_I2C_COMMAND6_DONE (BIT(31)) +#define LP_I2C_COMMAND6_DONE_M (LP_I2C_COMMAND6_DONE_V << LP_I2C_COMMAND6_DONE_S) +#define LP_I2C_COMMAND6_DONE_V 0x00000001U +#define LP_I2C_COMMAND6_DONE_S 31 + +/** LP_I2C_COMD7_REG register + * I2C command register 7 + */ +#define LP_I2C_COMD7_REG (DR_REG_LP_I2C_BASE + 0x74) +/** LP_I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 7. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define LP_I2C_COMMAND7 0x00003FFFU +#define LP_I2C_COMMAND7_M (LP_I2C_COMMAND7_V << LP_I2C_COMMAND7_S) +#define LP_I2C_COMMAND7_V 0x00003FFFU +#define LP_I2C_COMMAND7_S 0 +/** LP_I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 7 is done in I2C Master mode, this bit changes to high level. + */ +#define LP_I2C_COMMAND7_DONE (BIT(31)) +#define LP_I2C_COMMAND7_DONE_M (LP_I2C_COMMAND7_DONE_V << LP_I2C_COMMAND7_DONE_S) +#define LP_I2C_COMMAND7_DONE_V 0x00000001U +#define LP_I2C_COMMAND7_DONE_S 31 + +/** LP_I2C_SCL_ST_TIME_OUT_REG register + * SCL status time out register + */ +#define LP_I2C_SCL_ST_TIME_OUT_REG (DR_REG_LP_I2C_BASE + 0x78) +/** LP_I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; + * The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + */ +#define LP_I2C_SCL_ST_TO_I2C 0x0000001FU +#define LP_I2C_SCL_ST_TO_LP_I2C_M (LP_I2C_SCL_ST_TO_LP_I2C_V << LP_I2C_SCL_ST_TO_LP_I2C_S) +#define LP_I2C_SCL_ST_TO_LP_I2C_V 0x0000001FU +#define LP_I2C_SCL_ST_TO_LP_I2C_S 0 + +/** LP_I2C_SCL_MAIN_ST_TIME_OUT_REG register + * SCL main status time out register + */ +#define LP_I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_LP_I2C_BASE + 0x7c) +/** LP_I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; + * The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more + * than 23 + */ +#define LP_I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU +#define LP_I2C_SCL_MAIN_ST_TO_LP_I2C_M (LP_I2C_SCL_MAIN_ST_TO_LP_I2C_V << LP_I2C_SCL_MAIN_ST_TO_LP_I2C_S) +#define LP_I2C_SCL_MAIN_ST_TO_LP_I2C_V 0x0000001FU +#define LP_I2C_SCL_MAIN_ST_TO_LP_I2C_S 0 + +/** LP_I2C_SCL_SP_CONF_REG register + * Power configuration register + */ +#define LP_I2C_SCL_SP_CONF_REG (DR_REG_LP_I2C_BASE + 0x80) +/** LP_I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0; + * When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses + * equals to reg_scl_rst_slv_num[4:0]. + */ +#define LP_I2C_SCL_RST_SLV_EN (BIT(0)) +#define LP_I2C_SCL_RST_SLV_EN_M (LP_I2C_SCL_RST_SLV_EN_V << LP_I2C_SCL_RST_SLV_EN_S) +#define LP_I2C_SCL_RST_SLV_EN_V 0x00000001U +#define LP_I2C_SCL_RST_SLV_EN_S 0 +/** LP_I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; + * Configure the pulses of SCL generated in I2C master mode. Valid when + * reg_scl_rst_slv_en is 1. + */ +#define LP_I2C_SCL_RST_SLV_NUM 0x0000001FU +#define LP_I2C_SCL_RST_SLV_NUM_M (LP_I2C_SCL_RST_SLV_NUM_V << LP_I2C_SCL_RST_SLV_NUM_S) +#define LP_I2C_SCL_RST_SLV_NUM_V 0x0000001FU +#define LP_I2C_SCL_RST_SLV_NUM_S 1 +/** LP_I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; + * The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power + * down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. + */ +#define LP_I2C_SCL_PD_EN (BIT(6)) +#define LP_I2C_SCL_PD_EN_M (LP_I2C_SCL_PD_EN_V << LP_I2C_SCL_PD_EN_S) +#define LP_I2C_SCL_PD_EN_V 0x00000001U +#define LP_I2C_SCL_PD_EN_S 6 +/** LP_I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; + * The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power + * down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. + */ +#define LP_I2C_SDA_PD_EN (BIT(7)) +#define LP_I2C_SDA_PD_EN_M (LP_I2C_SDA_PD_EN_V << LP_I2C_SDA_PD_EN_S) +#define LP_I2C_SDA_PD_EN_V 0x00000001U +#define LP_I2C_SDA_PD_EN_S 7 + +/** LP_I2C_DATE_REG register + * Version register + */ +#define LP_I2C_DATE_REG (DR_REG_LP_I2C_BASE + 0xf8) +/** LP_I2C_DATE : R/W; bitpos: [31:0]; default: 35656003; + * This is the the version register. + */ +#define LP_I2C_DATE 0xFFFFFFFFU +#define LP_I2C_DATE_M (LP_I2C_DATE_V << LP_I2C_DATE_S) +#define LP_I2C_DATE_V 0xFFFFFFFFU +#define LP_I2C_DATE_S 0 + +/** LP_I2C_TXFIFO_START_ADDR_REG register + * I2C TXFIFO base address register + */ +#define LP_I2C_TXFIFO_START_ADDR_REG (DR_REG_LP_I2C_BASE + 0x100) +/** LP_I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; + * This is the I2C txfifo first address. + */ +#define LP_I2C_TXFIFO_START_ADDR 0xFFFFFFFFU +#define LP_I2C_TXFIFO_START_ADDR_M (LP_I2C_TXFIFO_START_ADDR_V << LP_I2C_TXFIFO_START_ADDR_S) +#define LP_I2C_TXFIFO_START_ADDR_V 0xFFFFFFFFU +#define LP_I2C_TXFIFO_START_ADDR_S 0 + +/** LP_I2C_RXFIFO_START_ADDR_REG register + * I2C RXFIFO base address register + */ +#define LP_I2C_RXFIFO_START_ADDR_REG (DR_REG_LP_I2C_BASE + 0x180) +/** LP_I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; + * This is the I2C rxfifo first address. + */ +#define LP_I2C_RXFIFO_START_ADDR 0xFFFFFFFFU +#define LP_I2C_RXFIFO_START_ADDR_M (LP_I2C_RXFIFO_START_ADDR_V << LP_I2C_RXFIFO_START_ADDR_S) +#define LP_I2C_RXFIFO_START_ADDR_V 0xFFFFFFFFU +#define LP_I2C_RXFIFO_START_ADDR_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_i2c_struct.h b/components/soc/esp32c6/include/soc/lp_i2c_struct.h new file mode 100644 index 0000000000..5a0e4835ad --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_i2c_struct.h @@ -0,0 +1,1061 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Timing registers */ +/** Type of scl_low_period register + * Configures the low level width of the SCL + * Clock + */ +typedef union { + struct { + /** scl_low_period : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SCL remains low in master mode, in + * I2C module clock cycles. + */ + uint32_t scl_low_period:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_i2c_scl_low_period_reg_t; + +/** Type of sda_hold register + * Configures the hold time after a negative SCL edge. + */ +typedef union { + struct { + /** sda_hold_time : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure the time to hold the data after the negative + * edge of SCL, in I2C module clock cycles. + */ + uint32_t sda_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_i2c_sda_hold_reg_t; + +/** Type of sda_sample register + * Configures the sample time after a positive SCL edge. + */ +typedef union { + struct { + /** sda_sample_time : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SDA is sampled, in I2C module clock + * cycles. + */ + uint32_t sda_sample_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_i2c_sda_sample_reg_t; + +/** Type of scl_high_period register + * Configures the high level width of SCL + */ +typedef union { + struct { + /** scl_high_period : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SCL setup to high level and remains + * high in master mode, in I2C module clock cycles. + */ + uint32_t scl_high_period:9; + /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0; + * This register is used to configure for the SCL_FSM's waiting period for SCL high + * level in master mode, in I2C module clock cycles. + */ + uint32_t scl_wait_high_period:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_i2c_scl_high_period_reg_t; + +/** Type of scl_start_hold register + * Configures the delay between the SDA and SCL negative edge for a start condition + */ +typedef union { + struct { + /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the negative edge + * of SDA and the negative edge of SCL for a START condition, in I2C module clock + * cycles. + */ + uint32_t scl_start_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_i2c_scl_start_hold_reg_t; + +/** Type of scl_rstart_setup register + * Configures the delay between the positive + * edge of SCL and the negative edge of SDA + */ +typedef union { + struct { + /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the positive + * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module + * clock cycles. + */ + uint32_t scl_rstart_setup_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_i2c_scl_rstart_setup_reg_t; + +/** Type of scl_stop_hold register + * Configures the delay after the SCL clock + * edge for a stop condition + */ +typedef union { + struct { + /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the delay after the STOP condition, + * in I2C module clock cycles. + */ + uint32_t scl_stop_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_i2c_scl_stop_hold_reg_t; + +/** Type of scl_stop_setup register + * Configures the delay between the SDA and + * SCL positive edge for a stop condition + */ +typedef union { + struct { + /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the positive edge + * of SCL and the positive edge of SDA, in I2C module clock cycles. + */ + uint32_t scl_stop_setup_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_i2c_scl_stop_setup_reg_t; + +/** Type of scl_st_time_out register + * SCL status time out register + */ +typedef union { + struct { + /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16; + * The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + */ + uint32_t scl_st_to_i2c:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} lp_i2c_scl_st_time_out_reg_t; + +/** Type of scl_main_st_time_out register + * SCL main status time out register + */ +typedef union { + struct { + /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16; + * The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more + * than 23 + */ + uint32_t scl_main_st_to_i2c:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} lp_i2c_scl_main_st_time_out_reg_t; + + +/** Group: Configuration registers */ +/** Type of ctr register + * Transmission setting + */ +typedef union { + struct { + /** sda_force_out : R/W; bitpos: [0]; default: 0; + * 1: direct output, 0: open drain output. + */ + uint32_t sda_force_out:1; + /** scl_force_out : R/W; bitpos: [1]; default: 0; + * 1: direct output, 0: open drain output. + */ + uint32_t scl_force_out:1; + /** sample_scl_level : R/W; bitpos: [2]; default: 0; + * This register is used to select the sample mode. + * 1: sample SDA data on the SCL low level. + * 0: sample SDA data on the SCL high level. + */ + uint32_t sample_scl_level:1; + /** rx_full_ack_level : R/W; bitpos: [3]; default: 1; + * This register is used to configure the ACK value that need to sent by master when + * the rx_fifo_cnt has reached the threshold. + */ + uint32_t rx_full_ack_level:1; + uint32_t reserved_4:1; + /** trans_start : WT; bitpos: [5]; default: 0; + * Set this bit to start sending the data in txfifo. + */ + uint32_t trans_start:1; + /** tx_lsb_first : R/W; bitpos: [6]; default: 0; + * This bit is used to control the sending mode for data needing to be sent. + * 1: send data from the least significant bit, + * 0: send data from the most significant bit. + */ + uint32_t tx_lsb_first:1; + /** rx_lsb_first : R/W; bitpos: [7]; default: 0; + * This bit is used to control the storage mode for received data. + * 1: receive data from the least significant bit, + * 0: receive data from the most significant bit. + */ + uint32_t rx_lsb_first:1; + /** clk_en : R/W; bitpos: [8]; default: 0; + * Reserved + */ + uint32_t clk_en:1; + /** arbitration_en : R/W; bitpos: [9]; default: 1; + * This is the enable bit for arbitration_lost. + */ + uint32_t arbitration_en:1; + /** fsm_rst : WT; bitpos: [10]; default: 0; + * This register is used to reset the scl FMS. + */ + uint32_t fsm_rst:1; + /** conf_upgate : WT; bitpos: [11]; default: 0; + * synchronization bit + */ + uint32_t conf_upgate:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_i2c_ctr_reg_t; + +/** Type of to register + * Setting time out control for receiving data. + */ +typedef union { + struct { + /** time_out_value : R/W; bitpos: [4:0]; default: 16; + * This register is used to configure the timeout for receiving a data bit in APB + * clock cycles. + */ + uint32_t time_out_value:5; + /** time_out_en : R/W; bitpos: [5]; default: 0; + * This is the enable bit for time out control. + */ + uint32_t time_out_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} lp_i2c_to_reg_t; + +/** Type of fifo_conf register + * FIFO configuration register. + */ +typedef union { + struct { + /** rxfifo_wm_thrhd : R/W; bitpos: [3:0]; default: 6; + * The water mark threshold of rx FIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than + * reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. + */ + uint32_t rxfifo_wm_thrhd:4; + uint32_t reserved_4:1; + /** txfifo_wm_thrhd : R/W; bitpos: [8:5]; default: 2; + * The water mark threshold of tx FIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than + * reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. + */ + uint32_t txfifo_wm_thrhd:4; + uint32_t reserved_9:1; + /** nonfifo_en : R/W; bitpos: [10]; default: 0; + * Set this bit to enable APB nonfifo access. + */ + uint32_t nonfifo_en:1; + uint32_t reserved_11:1; + /** rx_fifo_rst : R/W; bitpos: [12]; default: 0; + * Set this bit to reset rx-fifo. + */ + uint32_t rx_fifo_rst:1; + /** tx_fifo_rst : R/W; bitpos: [13]; default: 0; + * Set this bit to reset tx-fifo. + */ + uint32_t tx_fifo_rst:1; + /** fifo_prt_en : R/W; bitpos: [14]; default: 1; + * The control enable bit of FIFO pointer in non-fifo access mode. This bit controls + * the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. + */ + uint32_t fifo_prt_en:1; + uint32_t reserved_15:17; + }; + uint32_t val; +} lp_i2c_fifo_conf_reg_t; + +/** Type of filter_cfg register + * SCL and SDA filter configuration register + */ +typedef union { + struct { + /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0; + * When a pulse on the SCL input has smaller width than this register value + * in I2C module clock cycles, the I2C controller will ignore that pulse. + */ + uint32_t scl_filter_thres:4; + /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0; + * When a pulse on the SDA input has smaller width than this register value + * in I2C module clock cycles, the I2C controller will ignore that pulse. + */ + uint32_t sda_filter_thres:4; + /** scl_filter_en : R/W; bitpos: [8]; default: 1; + * This is the filter enable bit for SCL. + */ + uint32_t scl_filter_en:1; + /** sda_filter_en : R/W; bitpos: [9]; default: 1; + * This is the filter enable bit for SDA. + */ + uint32_t sda_filter_en:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} lp_i2c_filter_cfg_reg_t; + +/** Type of clk_conf register + * I2C CLK configuration register + */ +typedef union { + struct { + /** sclk_div_num : R/W; bitpos: [7:0]; default: 0; + * the integral part of the fractional divisor for i2c module + */ + uint32_t sclk_div_num:8; + /** sclk_div_a : R/W; bitpos: [13:8]; default: 0; + * the numerator of the fractional part of the fractional divisor for i2c module + */ + uint32_t sclk_div_a:6; + /** sclk_div_b : R/W; bitpos: [19:14]; default: 0; + * the denominator of the fractional part of the fractional divisor for i2c module + */ + uint32_t sclk_div_b:6; + /** sclk_sel : R/W; bitpos: [20]; default: 0; + * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + */ + uint32_t sclk_sel:1; + /** sclk_active : R/W; bitpos: [21]; default: 1; + * The clock switch for i2c module + */ + uint32_t sclk_active:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} lp_i2c_clk_conf_reg_t; + +/** Type of scl_sp_conf register + * Power configuration register + */ +typedef union { + struct { + /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0; + * When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses + * equals to reg_scl_rst_slv_num[4:0]. + */ + uint32_t scl_rst_slv_en:1; + /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0; + * Configure the pulses of SCL generated in I2C master mode. Valid when + * reg_scl_rst_slv_en is 1. + */ + uint32_t scl_rst_slv_num:5; + /** scl_pd_en : R/W; bitpos: [6]; default: 0; + * The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power + * down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. + */ + uint32_t scl_pd_en:1; + /** sda_pd_en : R/W; bitpos: [7]; default: 0; + * The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power + * down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. + */ + uint32_t sda_pd_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_i2c_scl_sp_conf_reg_t; + + +/** Group: Status registers */ +/** Type of sr register + * Describe I2C work status. + */ +typedef union { + struct { + /** resp_rec : RO; bitpos: [0]; default: 0; + * The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + */ + uint32_t resp_rec:1; + uint32_t reserved_1:2; + /** arb_lost : RO; bitpos: [3]; default: 0; + * When the I2C controller loses control of SCL line, this register changes to 1. + */ + uint32_t arb_lost:1; + /** bus_busy : RO; bitpos: [4]; default: 0; + * 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. + */ + uint32_t bus_busy:1; + uint32_t reserved_5:3; + /** rxfifo_cnt : RO; bitpos: [12:8]; default: 0; + * This field represents the amount of data needed to be sent. + */ + uint32_t rxfifo_cnt:5; + uint32_t reserved_13:5; + /** txfifo_cnt : RO; bitpos: [22:18]; default: 0; + * This field stores the amount of received data in RAM. + */ + uint32_t txfifo_cnt:5; + uint32_t reserved_23:1; + /** scl_main_state_last : RO; bitpos: [26:24]; default: 0; + * This field indicates the states of the I2C module state machine. + * 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: + * Wait ACK + */ + uint32_t scl_main_state_last:3; + uint32_t reserved_27:1; + /** scl_state_last : RO; bitpos: [30:28]; default: 0; + * This field indicates the states of the state machine used to produce SCL. + * 0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop + */ + uint32_t scl_state_last:3; + uint32_t reserved_31:1; + }; + uint32_t val; +} lp_i2c_sr_reg_t; + +/** Type of fifo_st register + * FIFO status register. + */ +typedef union { + struct { + /** rxfifo_raddr : RO; bitpos: [3:0]; default: 0; + * This is the offset address of the APB reading from rxfifo + */ + uint32_t rxfifo_raddr:4; + uint32_t reserved_4:1; + /** rxfifo_waddr : RO; bitpos: [8:5]; default: 0; + * This is the offset address of i2c module receiving data and writing to rxfifo. + */ + uint32_t rxfifo_waddr:4; + uint32_t reserved_9:1; + /** txfifo_raddr : RO; bitpos: [13:10]; default: 0; + * This is the offset address of i2c module reading from txfifo. + */ + uint32_t txfifo_raddr:4; + uint32_t reserved_14:1; + /** txfifo_waddr : RO; bitpos: [18:15]; default: 0; + * This is the offset address of APB bus writing to txfifo. + */ + uint32_t txfifo_waddr:4; + uint32_t reserved_19:13; + }; + uint32_t val; +} lp_i2c_fifo_st_reg_t; + +/** Type of data register + * Rx FIFO read data. + */ +typedef union { + struct { + /** fifo_rdata : RO; bitpos: [7:0]; default: 0; + * The value of rx FIFO read data. + */ + uint32_t fifo_rdata:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_i2c_data_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_raw:1; + /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_raw:1; + /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_raw:1; + /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_raw:1; + /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_raw:1; + /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_raw:1; + /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_raw:1; + /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_raw:1; + /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_raw:1; + /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_raw:1; + /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_raw:1; + /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_raw:1; + /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_raw:1; + /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_raw:1; + /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_raw:1; + /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt bit for I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_raw:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_i2c_int_raw_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_clr:1; + /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_clr:1; + /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_clr:1; + /** end_detect_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_clr:1; + /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_clr:1; + /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_clr:1; + /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_clr:1; + /** trans_complete_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_clr:1; + /** time_out_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_clr:1; + /** trans_start_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_clr:1; + /** nack_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_clr:1; + /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_clr:1; + /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_clr:1; + /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_clr:1; + /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_clr:1; + /** det_start_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_clr:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_i2c_int_clr_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_ena:1; + /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_ena:1; + /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_ena:1; + /** end_detect_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_ena:1; + /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_ena:1; + /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_ena:1; + /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_ena:1; + /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_ena:1; + /** time_out_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_ena:1; + /** trans_start_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_ena:1; + /** nack_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_ena:1; + /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_ena:1; + /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_ena:1; + /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_ena:1; + /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_ena:1; + /** det_start_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_ena:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_i2c_int_ena_reg_t; + +/** Type of int_status register + * Status of captured I2C communication events + */ +typedef union { + struct { + /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_st:1; + /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_st:1; + /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_st:1; + /** end_detect_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_st:1; + /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_st:1; + /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_st:1; + /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_st:1; + /** trans_complete_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_st:1; + /** time_out_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_st:1; + /** trans_start_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_st:1; + /** nack_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_st:1; + /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_st:1; + /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_st:1; + /** scl_st_to_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_st:1; + /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_st:1; + /** det_start_int_st : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_st:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_i2c_int_status_reg_t; + + +/** Group: Command registers */ +/** Type of comd0 register + * I2C command register 0 + */ +typedef union { + struct { + /** command0 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 0. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command0:14; + uint32_t reserved_14:17; + /** command0_done : R/W/SS; bitpos: [31]; default: 0; + * When command 0 is done in I2C Master mode, this bit changes to high + * level. + */ + uint32_t command0_done:1; + }; + uint32_t val; +} lp_i2c_comd0_reg_t; + +/** Type of comd1 register + * I2C command register 1 + */ +typedef union { + struct { + /** command1 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 1. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command1:14; + uint32_t reserved_14:17; + /** command1_done : R/W/SS; bitpos: [31]; default: 0; + * When command 1 is done in I2C Master mode, this bit changes to high + * level. + */ + uint32_t command1_done:1; + }; + uint32_t val; +} lp_i2c_comd1_reg_t; + +/** Type of comd2 register + * I2C command register 2 + */ +typedef union { + struct { + /** command2 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 2. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command2:14; + uint32_t reserved_14:17; + /** command2_done : R/W/SS; bitpos: [31]; default: 0; + * When command 2 is done in I2C Master mode, this bit changes to high + * Level. + */ + uint32_t command2_done:1; + }; + uint32_t val; +} lp_i2c_comd2_reg_t; + +/** Type of comd3 register + * I2C command register 3 + */ +typedef union { + struct { + /** command3 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 3. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command3:14; + uint32_t reserved_14:17; + /** command3_done : R/W/SS; bitpos: [31]; default: 0; + * When command 3 is done in I2C Master mode, this bit changes to high + * level. + */ + uint32_t command3_done:1; + }; + uint32_t val; +} lp_i2c_comd3_reg_t; + +/** Type of comd4 register + * I2C command register 4 + */ +typedef union { + struct { + /** command4 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 4. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command4:14; + uint32_t reserved_14:17; + /** command4_done : R/W/SS; bitpos: [31]; default: 0; + * When command 4 is done in I2C Master mode, this bit changes to high + * level. + */ + uint32_t command4_done:1; + }; + uint32_t val; +} lp_i2c_comd4_reg_t; + +/** Type of comd5 register + * I2C command register 5 + */ +typedef union { + struct { + /** command5 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 5. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command5:14; + uint32_t reserved_14:17; + /** command5_done : R/W/SS; bitpos: [31]; default: 0; + * When command 5 is done in I2C Master mode, this bit changes to high level. + */ + uint32_t command5_done:1; + }; + uint32_t val; +} lp_i2c_comd5_reg_t; + +/** Type of comd6 register + * I2C command register 6 + */ +typedef union { + struct { + /** command6 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 6. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command6:14; + uint32_t reserved_14:17; + /** command6_done : R/W/SS; bitpos: [31]; default: 0; + * When command 6 is done in I2C Master mode, this bit changes to high level. + */ + uint32_t command6_done:1; + }; + uint32_t val; +} lp_i2c_comd6_reg_t; + +/** Type of comd7 register + * I2C command register 7 + */ +typedef union { + struct { + /** command7 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 7. It consists of three parts: + * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command7:14; + uint32_t reserved_14:17; + /** command7_done : R/W/SS; bitpos: [31]; default: 0; + * When command 7 is done in I2C Master mode, this bit changes to high level. + */ + uint32_t command7_done:1; + }; + uint32_t val; +} lp_i2c_comd7_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35656003; + * This is the the version register. + */ + uint32_t date:32; + }; + uint32_t val; +} lp_i2c_date_reg_t; + + +/** Group: Address register */ +/** Type of txfifo_start_addr register + * I2C TXFIFO base address register + */ +typedef union { + struct { + /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0; + * This is the I2C txfifo first address. + */ + uint32_t txfifo_start_addr:32; + }; + uint32_t val; +} lp_i2c_txfifo_start_addr_reg_t; + +/** Type of rxfifo_start_addr register + * I2C RXFIFO base address register + */ +typedef union { + struct { + /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0; + * This is the I2C rxfifo first address. + */ + uint32_t rxfifo_start_addr:32; + }; + uint32_t val; +} lp_i2c_rxfifo_start_addr_reg_t; + + +typedef struct lp_i2c_dev_t { + volatile lp_i2c_scl_low_period_reg_t scl_low_period; + volatile lp_i2c_ctr_reg_t ctr; + volatile lp_i2c_sr_reg_t sr; + volatile lp_i2c_to_reg_t to; + uint32_t reserved_010; + volatile lp_i2c_fifo_st_reg_t fifo_st; + volatile lp_i2c_fifo_conf_reg_t fifo_conf; + volatile lp_i2c_data_reg_t data; + volatile lp_i2c_int_raw_reg_t int_raw; + volatile lp_i2c_int_clr_reg_t int_clr; + volatile lp_i2c_int_ena_reg_t int_ena; + volatile lp_i2c_int_status_reg_t int_status; + volatile lp_i2c_sda_hold_reg_t sda_hold; + volatile lp_i2c_sda_sample_reg_t sda_sample; + volatile lp_i2c_scl_high_period_reg_t scl_high_period; + uint32_t reserved_03c; + volatile lp_i2c_scl_start_hold_reg_t scl_start_hold; + volatile lp_i2c_scl_rstart_setup_reg_t scl_rstart_setup; + volatile lp_i2c_scl_stop_hold_reg_t scl_stop_hold; + volatile lp_i2c_scl_stop_setup_reg_t scl_stop_setup; + volatile lp_i2c_filter_cfg_reg_t filter_cfg; + volatile lp_i2c_clk_conf_reg_t clk_conf; + volatile lp_i2c_comd0_reg_t comd0; + volatile lp_i2c_comd1_reg_t comd1; + volatile lp_i2c_comd2_reg_t comd2; + volatile lp_i2c_comd3_reg_t comd3; + volatile lp_i2c_comd4_reg_t comd4; + volatile lp_i2c_comd5_reg_t comd5; + volatile lp_i2c_comd6_reg_t comd6; + volatile lp_i2c_comd7_reg_t comd7; + volatile lp_i2c_scl_st_time_out_reg_t scl_st_time_out; + volatile lp_i2c_scl_main_st_time_out_reg_t scl_main_st_time_out; + volatile lp_i2c_scl_sp_conf_reg_t scl_sp_conf; + uint32_t reserved_084[29]; + volatile lp_i2c_date_reg_t date; + uint32_t reserved_0fc; + volatile lp_i2c_txfifo_start_addr_reg_t txfifo_start_addr; + uint32_t reserved_104[31]; + volatile lp_i2c_rxfifo_start_addr_reg_t rxfifo_start_addr; +} lp_i2c_dev_t; + +extern lp_i2c_dev_t LP_I2C; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_i2c_dev_t) == 0x184, "Invalid size of lp_i2c_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_io_reg.h b/components/soc/esp32c6/include/soc/lp_io_reg.h new file mode 100644 index 0000000000..e57282b97b --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_io_reg.h @@ -0,0 +1,1263 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_IO_OUT_DATA_REG register + * need des + */ +#define LP_IO_OUT_DATA_REG (DR_REG_LP_IO_BASE + 0x0) +/** LP_IO_LP_GPIO_OUT_DATA : R/W/WTC; bitpos: [7:0]; default: 0; + * set lp gpio output data + */ +#define LP_IO_LP_GPIO_OUT_DATA 0x000000FFU +#define LP_IO_LP_GPIO_OUT_DATA_M (LP_IO_LP_GPIO_OUT_DATA_V << LP_IO_LP_GPIO_OUT_DATA_S) +#define LP_IO_LP_GPIO_OUT_DATA_V 0x000000FFU +#define LP_IO_LP_GPIO_OUT_DATA_S 0 + +/** LP_IO_OUT_DATA_W1TS_REG register + * need des + */ +#define LP_IO_OUT_DATA_W1TS_REG (DR_REG_LP_IO_BASE + 0x4) +/** LP_IO_LP_GPIO_OUT_DATA_W1TS : WT; bitpos: [7:0]; default: 0; + * set one time output data + */ +#define LP_IO_LP_GPIO_OUT_DATA_W1TS 0x000000FFU +#define LP_IO_LP_GPIO_OUT_DATA_W1TS_M (LP_IO_LP_GPIO_OUT_DATA_W1TS_V << LP_IO_LP_GPIO_OUT_DATA_W1TS_S) +#define LP_IO_LP_GPIO_OUT_DATA_W1TS_V 0x000000FFU +#define LP_IO_LP_GPIO_OUT_DATA_W1TS_S 0 + +/** LP_IO_OUT_DATA_W1TC_REG register + * need des + */ +#define LP_IO_OUT_DATA_W1TC_REG (DR_REG_LP_IO_BASE + 0x8) +/** LP_IO_LP_GPIO_OUT_DATA_W1TC : WT; bitpos: [7:0]; default: 0; + * clear one time output data + */ +#define LP_IO_LP_GPIO_OUT_DATA_W1TC 0x000000FFU +#define LP_IO_LP_GPIO_OUT_DATA_W1TC_M (LP_IO_LP_GPIO_OUT_DATA_W1TC_V << LP_IO_LP_GPIO_OUT_DATA_W1TC_S) +#define LP_IO_LP_GPIO_OUT_DATA_W1TC_V 0x000000FFU +#define LP_IO_LP_GPIO_OUT_DATA_W1TC_S 0 + +/** LP_IO_OUT_ENABLE_REG register + * need des + */ +#define LP_IO_OUT_ENABLE_REG (DR_REG_LP_IO_BASE + 0xc) +/** LP_IO_LP_GPIO_ENABLE : R/W/WTC; bitpos: [7:0]; default: 0; + * set lp gpio output data + */ +#define LP_IO_LP_GPIO_ENABLE 0x000000FFU +#define LP_IO_LP_GPIO_ENABLE_M (LP_IO_LP_GPIO_ENABLE_V << LP_IO_LP_GPIO_ENABLE_S) +#define LP_IO_LP_GPIO_ENABLE_V 0x000000FFU +#define LP_IO_LP_GPIO_ENABLE_S 0 + +/** LP_IO_OUT_ENABLE_W1TS_REG register + * need des + */ +#define LP_IO_OUT_ENABLE_W1TS_REG (DR_REG_LP_IO_BASE + 0x10) +/** LP_IO_LP_GPIO_ENABLE_W1TS : WT; bitpos: [7:0]; default: 0; + * set one time output data + */ +#define LP_IO_LP_GPIO_ENABLE_W1TS 0x000000FFU +#define LP_IO_LP_GPIO_ENABLE_W1TS_M (LP_IO_LP_GPIO_ENABLE_W1TS_V << LP_IO_LP_GPIO_ENABLE_W1TS_S) +#define LP_IO_LP_GPIO_ENABLE_W1TS_V 0x000000FFU +#define LP_IO_LP_GPIO_ENABLE_W1TS_S 0 + +/** LP_IO_OUT_ENABLE_W1TC_REG register + * need des + */ +#define LP_IO_OUT_ENABLE_W1TC_REG (DR_REG_LP_IO_BASE + 0x14) +/** LP_IO_LP_GPIO_ENABLE_W1TC : WT; bitpos: [7:0]; default: 0; + * clear one time output data + */ +#define LP_IO_LP_GPIO_ENABLE_W1TC 0x000000FFU +#define LP_IO_LP_GPIO_ENABLE_W1TC_M (LP_IO_LP_GPIO_ENABLE_W1TC_V << LP_IO_LP_GPIO_ENABLE_W1TC_S) +#define LP_IO_LP_GPIO_ENABLE_W1TC_V 0x000000FFU +#define LP_IO_LP_GPIO_ENABLE_W1TC_S 0 + +/** LP_IO_STATUS_REG register + * need des + */ +#define LP_IO_STATUS_REG (DR_REG_LP_IO_BASE + 0x18) +/** LP_IO_LP_GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [7:0]; default: 0; + * set lp gpio output data + */ +#define LP_IO_LP_GPIO_STATUS_INTERRUPT 0x000000FFU +#define LP_IO_LP_GPIO_STATUS_INTERRUPT_M (LP_IO_LP_GPIO_STATUS_INTERRUPT_V << LP_IO_LP_GPIO_STATUS_INTERRUPT_S) +#define LP_IO_LP_GPIO_STATUS_INTERRUPT_V 0x000000FFU +#define LP_IO_LP_GPIO_STATUS_INTERRUPT_S 0 + +/** LP_IO_STATUS_W1TS_REG register + * need des + */ +#define LP_IO_STATUS_W1TS_REG (DR_REG_LP_IO_BASE + 0x1c) +/** LP_IO_LP_GPIO_STATUS_W1TS : WT; bitpos: [7:0]; default: 0; + * set one time output data + */ +#define LP_IO_LP_GPIO_STATUS_W1TS 0x000000FFU +#define LP_IO_LP_GPIO_STATUS_W1TS_M (LP_IO_LP_GPIO_STATUS_W1TS_V << LP_IO_LP_GPIO_STATUS_W1TS_S) +#define LP_IO_LP_GPIO_STATUS_W1TS_V 0x000000FFU +#define LP_IO_LP_GPIO_STATUS_W1TS_S 0 + +/** LP_IO_STATUS_W1TC_REG register + * need des + */ +#define LP_IO_STATUS_W1TC_REG (DR_REG_LP_IO_BASE + 0x20) +/** LP_IO_LP_GPIO_STATUS_W1TC : WT; bitpos: [7:0]; default: 0; + * clear one time output data + */ +#define LP_IO_LP_GPIO_STATUS_W1TC 0x000000FFU +#define LP_IO_LP_GPIO_STATUS_W1TC_M (LP_IO_LP_GPIO_STATUS_W1TC_V << LP_IO_LP_GPIO_STATUS_W1TC_S) +#define LP_IO_LP_GPIO_STATUS_W1TC_V 0x000000FFU +#define LP_IO_LP_GPIO_STATUS_W1TC_S 0 + +/** LP_IO_IN_REG register + * need des + */ +#define LP_IO_IN_REG (DR_REG_LP_IO_BASE + 0x24) +/** LP_IO_LP_GPIO_IN_DATA_NEXT : RO; bitpos: [7:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO_IN_DATA_NEXT 0x000000FFU +#define LP_IO_LP_GPIO_IN_DATA_NEXT_M (LP_IO_LP_GPIO_IN_DATA_NEXT_V << LP_IO_LP_GPIO_IN_DATA_NEXT_S) +#define LP_IO_LP_GPIO_IN_DATA_NEXT_V 0x000000FFU +#define LP_IO_LP_GPIO_IN_DATA_NEXT_S 0 + +/** LP_IO_PIN0_REG register + * need des + */ +#define LP_IO_PIN0_REG (DR_REG_LP_IO_BASE + 0x28) +/** LP_IO_LP_GPIO0_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO0_SYNC_BYPASS_M (LP_IO_LP_GPIO0_SYNC_BYPASS_V << LP_IO_LP_GPIO0_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO0_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO0_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO0_PAD_DRIVER_M (LP_IO_LP_GPIO0_PAD_DRIVER_V << LP_IO_LP_GPIO0_PAD_DRIVER_S) +#define LP_IO_LP_GPIO0_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO0_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO0_INT_TYPE_M (LP_IO_LP_GPIO0_INT_TYPE_V << LP_IO_LP_GPIO0_INT_TYPE_S) +#define LP_IO_LP_GPIO0_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO0_INT_TYPE_S 7 +/** LP_IO_LP_GPIO0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO0_WAKEUP_ENABLE_M (LP_IO_LP_GPIO0_WAKEUP_ENABLE_V << LP_IO_LP_GPIO0_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO0_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO0_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO0_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO0_FILTER_EN_M (LP_IO_LP_GPIO0_FILTER_EN_V << LP_IO_LP_GPIO0_FILTER_EN_S) +#define LP_IO_LP_GPIO0_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO0_FILTER_EN_S 11 + +/** LP_IO_PIN1_REG register + * need des + */ +#define LP_IO_PIN1_REG (DR_REG_LP_IO_BASE + 0x2c) +/** LP_IO_LP_GPIO1_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO1_SYNC_BYPASS_M (LP_IO_LP_GPIO1_SYNC_BYPASS_V << LP_IO_LP_GPIO1_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO1_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO1_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO1_PAD_DRIVER_M (LP_IO_LP_GPIO1_PAD_DRIVER_V << LP_IO_LP_GPIO1_PAD_DRIVER_S) +#define LP_IO_LP_GPIO1_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO1_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO1_INT_TYPE_M (LP_IO_LP_GPIO1_INT_TYPE_V << LP_IO_LP_GPIO1_INT_TYPE_S) +#define LP_IO_LP_GPIO1_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO1_INT_TYPE_S 7 +/** LP_IO_LP_GPIO1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO1_WAKEUP_ENABLE_M (LP_IO_LP_GPIO1_WAKEUP_ENABLE_V << LP_IO_LP_GPIO1_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO1_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO1_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO1_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO1_FILTER_EN_M (LP_IO_LP_GPIO1_FILTER_EN_V << LP_IO_LP_GPIO1_FILTER_EN_S) +#define LP_IO_LP_GPIO1_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO1_FILTER_EN_S 11 + +/** LP_IO_PIN2_REG register + * need des + */ +#define LP_IO_PIN2_REG (DR_REG_LP_IO_BASE + 0x30) +/** LP_IO_LP_GPIO2_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO2_SYNC_BYPASS_M (LP_IO_LP_GPIO2_SYNC_BYPASS_V << LP_IO_LP_GPIO2_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO2_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO2_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO2_PAD_DRIVER_M (LP_IO_LP_GPIO2_PAD_DRIVER_V << LP_IO_LP_GPIO2_PAD_DRIVER_S) +#define LP_IO_LP_GPIO2_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO2_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO2_INT_TYPE_M (LP_IO_LP_GPIO2_INT_TYPE_V << LP_IO_LP_GPIO2_INT_TYPE_S) +#define LP_IO_LP_GPIO2_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO2_INT_TYPE_S 7 +/** LP_IO_LP_GPIO2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO2_WAKEUP_ENABLE_M (LP_IO_LP_GPIO2_WAKEUP_ENABLE_V << LP_IO_LP_GPIO2_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO2_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO2_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO2_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO2_FILTER_EN_M (LP_IO_LP_GPIO2_FILTER_EN_V << LP_IO_LP_GPIO2_FILTER_EN_S) +#define LP_IO_LP_GPIO2_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO2_FILTER_EN_S 11 + +/** LP_IO_PIN3_REG register + * need des + */ +#define LP_IO_PIN3_REG (DR_REG_LP_IO_BASE + 0x34) +/** LP_IO_LP_GPIO3_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO3_SYNC_BYPASS_M (LP_IO_LP_GPIO3_SYNC_BYPASS_V << LP_IO_LP_GPIO3_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO3_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO3_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO3_PAD_DRIVER_M (LP_IO_LP_GPIO3_PAD_DRIVER_V << LP_IO_LP_GPIO3_PAD_DRIVER_S) +#define LP_IO_LP_GPIO3_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO3_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO3_INT_TYPE_M (LP_IO_LP_GPIO3_INT_TYPE_V << LP_IO_LP_GPIO3_INT_TYPE_S) +#define LP_IO_LP_GPIO3_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO3_INT_TYPE_S 7 +/** LP_IO_LP_GPIO3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO3_WAKEUP_ENABLE_M (LP_IO_LP_GPIO3_WAKEUP_ENABLE_V << LP_IO_LP_GPIO3_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO3_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO3_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO3_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO3_FILTER_EN_M (LP_IO_LP_GPIO3_FILTER_EN_V << LP_IO_LP_GPIO3_FILTER_EN_S) +#define LP_IO_LP_GPIO3_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO3_FILTER_EN_S 11 + +/** LP_IO_PIN4_REG register + * need des + */ +#define LP_IO_PIN4_REG (DR_REG_LP_IO_BASE + 0x38) +/** LP_IO_LP_GPIO4_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO4_SYNC_BYPASS_M (LP_IO_LP_GPIO4_SYNC_BYPASS_V << LP_IO_LP_GPIO4_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO4_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO4_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO4_PAD_DRIVER_M (LP_IO_LP_GPIO4_PAD_DRIVER_V << LP_IO_LP_GPIO4_PAD_DRIVER_S) +#define LP_IO_LP_GPIO4_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO4_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO4_INT_TYPE_M (LP_IO_LP_GPIO4_INT_TYPE_V << LP_IO_LP_GPIO4_INT_TYPE_S) +#define LP_IO_LP_GPIO4_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO4_INT_TYPE_S 7 +/** LP_IO_LP_GPIO4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO4_WAKEUP_ENABLE_M (LP_IO_LP_GPIO4_WAKEUP_ENABLE_V << LP_IO_LP_GPIO4_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO4_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO4_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO4_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO4_FILTER_EN_M (LP_IO_LP_GPIO4_FILTER_EN_V << LP_IO_LP_GPIO4_FILTER_EN_S) +#define LP_IO_LP_GPIO4_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO4_FILTER_EN_S 11 + +/** LP_IO_PIN5_REG register + * need des + */ +#define LP_IO_PIN5_REG (DR_REG_LP_IO_BASE + 0x3c) +/** LP_IO_LP_GPIO5_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO5_SYNC_BYPASS_M (LP_IO_LP_GPIO5_SYNC_BYPASS_V << LP_IO_LP_GPIO5_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO5_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO5_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO5_PAD_DRIVER_M (LP_IO_LP_GPIO5_PAD_DRIVER_V << LP_IO_LP_GPIO5_PAD_DRIVER_S) +#define LP_IO_LP_GPIO5_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO5_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO5_INT_TYPE_M (LP_IO_LP_GPIO5_INT_TYPE_V << LP_IO_LP_GPIO5_INT_TYPE_S) +#define LP_IO_LP_GPIO5_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO5_INT_TYPE_S 7 +/** LP_IO_LP_GPIO5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO5_WAKEUP_ENABLE_M (LP_IO_LP_GPIO5_WAKEUP_ENABLE_V << LP_IO_LP_GPIO5_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO5_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO5_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO5_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO5_FILTER_EN_M (LP_IO_LP_GPIO5_FILTER_EN_V << LP_IO_LP_GPIO5_FILTER_EN_S) +#define LP_IO_LP_GPIO5_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO5_FILTER_EN_S 11 + +/** LP_IO_PIN6_REG register + * need des + */ +#define LP_IO_PIN6_REG (DR_REG_LP_IO_BASE + 0x40) +/** LP_IO_LP_GPIO6_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO6_SYNC_BYPASS_M (LP_IO_LP_GPIO6_SYNC_BYPASS_V << LP_IO_LP_GPIO6_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO6_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO6_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO6_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO6_PAD_DRIVER_M (LP_IO_LP_GPIO6_PAD_DRIVER_V << LP_IO_LP_GPIO6_PAD_DRIVER_S) +#define LP_IO_LP_GPIO6_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO6_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO6_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO6_INT_TYPE_M (LP_IO_LP_GPIO6_INT_TYPE_V << LP_IO_LP_GPIO6_INT_TYPE_S) +#define LP_IO_LP_GPIO6_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO6_INT_TYPE_S 7 +/** LP_IO_LP_GPIO6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO6_WAKEUP_ENABLE_M (LP_IO_LP_GPIO6_WAKEUP_ENABLE_V << LP_IO_LP_GPIO6_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO6_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO6_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO6_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO6_FILTER_EN_M (LP_IO_LP_GPIO6_FILTER_EN_V << LP_IO_LP_GPIO6_FILTER_EN_S) +#define LP_IO_LP_GPIO6_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO6_FILTER_EN_S 11 + +/** LP_IO_PIN7_REG register + * need des + */ +#define LP_IO_PIN7_REG (DR_REG_LP_IO_BASE + 0x44) +/** LP_IO_LP_GPIO7_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO7_SYNC_BYPASS_M (LP_IO_LP_GPIO7_SYNC_BYPASS_V << LP_IO_LP_GPIO7_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO7_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO7_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO7_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO7_PAD_DRIVER_M (LP_IO_LP_GPIO7_PAD_DRIVER_V << LP_IO_LP_GPIO7_PAD_DRIVER_S) +#define LP_IO_LP_GPIO7_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO7_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO7_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO7_INT_TYPE_M (LP_IO_LP_GPIO7_INT_TYPE_V << LP_IO_LP_GPIO7_INT_TYPE_S) +#define LP_IO_LP_GPIO7_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO7_INT_TYPE_S 7 +/** LP_IO_LP_GPIO7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO7_WAKEUP_ENABLE_M (LP_IO_LP_GPIO7_WAKEUP_ENABLE_V << LP_IO_LP_GPIO7_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO7_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO7_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO7_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO7_FILTER_EN_M (LP_IO_LP_GPIO7_FILTER_EN_V << LP_IO_LP_GPIO7_FILTER_EN_S) +#define LP_IO_LP_GPIO7_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO7_FILTER_EN_S 11 + +/** LP_IO_GPIO0_REG register + * need des + */ +#define LP_IO_GPIO0_REG (DR_REG_LP_IO_BASE + 0x48) +/** LP_IO_LP_GPIO0_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO0_MCU_OE_M (LP_IO_LP_GPIO0_MCU_OE_V << LP_IO_LP_GPIO0_MCU_OE_S) +#define LP_IO_LP_GPIO0_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO0_MCU_OE_S 0 +/** LP_IO_LP_GPIO0_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO0_SLP_SEL_M (LP_IO_LP_GPIO0_SLP_SEL_V << LP_IO_LP_GPIO0_SLP_SEL_S) +#define LP_IO_LP_GPIO0_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO0_SLP_SEL_S 1 +/** LP_IO_LP_GPIO0_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO0_MCU_WPD_M (LP_IO_LP_GPIO0_MCU_WPD_V << LP_IO_LP_GPIO0_MCU_WPD_S) +#define LP_IO_LP_GPIO0_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO0_MCU_WPD_S 2 +/** LP_IO_LP_GPIO0_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO0_MCU_WPU_M (LP_IO_LP_GPIO0_MCU_WPU_V << LP_IO_LP_GPIO0_MCU_WPU_S) +#define LP_IO_LP_GPIO0_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO0_MCU_WPU_S 3 +/** LP_IO_LP_GPIO0_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO0_MCU_IE_M (LP_IO_LP_GPIO0_MCU_IE_V << LP_IO_LP_GPIO0_MCU_IE_S) +#define LP_IO_LP_GPIO0_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO0_MCU_IE_S 4 +/** LP_IO_LP_GPIO0_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO0_MCU_DRV_M (LP_IO_LP_GPIO0_MCU_DRV_V << LP_IO_LP_GPIO0_MCU_DRV_S) +#define LP_IO_LP_GPIO0_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO0_MCU_DRV_S 5 +/** LP_IO_LP_GPIO0_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO0_FUN_WPD_M (LP_IO_LP_GPIO0_FUN_WPD_V << LP_IO_LP_GPIO0_FUN_WPD_S) +#define LP_IO_LP_GPIO0_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO0_FUN_WPD_S 7 +/** LP_IO_LP_GPIO0_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO0_FUN_WPU_M (LP_IO_LP_GPIO0_FUN_WPU_V << LP_IO_LP_GPIO0_FUN_WPU_S) +#define LP_IO_LP_GPIO0_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO0_FUN_WPU_S 8 +/** LP_IO_LP_GPIO0_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO0_FUN_IE_M (LP_IO_LP_GPIO0_FUN_IE_V << LP_IO_LP_GPIO0_FUN_IE_S) +#define LP_IO_LP_GPIO0_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO0_FUN_IE_S 9 +/** LP_IO_LP_GPIO0_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO0_FUN_DRV_M (LP_IO_LP_GPIO0_FUN_DRV_V << LP_IO_LP_GPIO0_FUN_DRV_S) +#define LP_IO_LP_GPIO0_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO0_FUN_DRV_S 10 +/** LP_IO_LP_GPIO0_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO0_MCU_SEL_M (LP_IO_LP_GPIO0_MCU_SEL_V << LP_IO_LP_GPIO0_MCU_SEL_S) +#define LP_IO_LP_GPIO0_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO0_MCU_SEL_S 12 + +/** LP_IO_GPIO1_REG register + * need des + */ +#define LP_IO_GPIO1_REG (DR_REG_LP_IO_BASE + 0x4c) +/** LP_IO_LP_GPIO1_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO1_MCU_OE_M (LP_IO_LP_GPIO1_MCU_OE_V << LP_IO_LP_GPIO1_MCU_OE_S) +#define LP_IO_LP_GPIO1_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO1_MCU_OE_S 0 +/** LP_IO_LP_GPIO1_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO1_SLP_SEL_M (LP_IO_LP_GPIO1_SLP_SEL_V << LP_IO_LP_GPIO1_SLP_SEL_S) +#define LP_IO_LP_GPIO1_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO1_SLP_SEL_S 1 +/** LP_IO_LP_GPIO1_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO1_MCU_WPD_M (LP_IO_LP_GPIO1_MCU_WPD_V << LP_IO_LP_GPIO1_MCU_WPD_S) +#define LP_IO_LP_GPIO1_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO1_MCU_WPD_S 2 +/** LP_IO_LP_GPIO1_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO1_MCU_WPU_M (LP_IO_LP_GPIO1_MCU_WPU_V << LP_IO_LP_GPIO1_MCU_WPU_S) +#define LP_IO_LP_GPIO1_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO1_MCU_WPU_S 3 +/** LP_IO_LP_GPIO1_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO1_MCU_IE_M (LP_IO_LP_GPIO1_MCU_IE_V << LP_IO_LP_GPIO1_MCU_IE_S) +#define LP_IO_LP_GPIO1_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO1_MCU_IE_S 4 +/** LP_IO_LP_GPIO1_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO1_MCU_DRV_M (LP_IO_LP_GPIO1_MCU_DRV_V << LP_IO_LP_GPIO1_MCU_DRV_S) +#define LP_IO_LP_GPIO1_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO1_MCU_DRV_S 5 +/** LP_IO_LP_GPIO1_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO1_FUN_WPD_M (LP_IO_LP_GPIO1_FUN_WPD_V << LP_IO_LP_GPIO1_FUN_WPD_S) +#define LP_IO_LP_GPIO1_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO1_FUN_WPD_S 7 +/** LP_IO_LP_GPIO1_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO1_FUN_WPU_M (LP_IO_LP_GPIO1_FUN_WPU_V << LP_IO_LP_GPIO1_FUN_WPU_S) +#define LP_IO_LP_GPIO1_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO1_FUN_WPU_S 8 +/** LP_IO_LP_GPIO1_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO1_FUN_IE_M (LP_IO_LP_GPIO1_FUN_IE_V << LP_IO_LP_GPIO1_FUN_IE_S) +#define LP_IO_LP_GPIO1_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO1_FUN_IE_S 9 +/** LP_IO_LP_GPIO1_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO1_FUN_DRV_M (LP_IO_LP_GPIO1_FUN_DRV_V << LP_IO_LP_GPIO1_FUN_DRV_S) +#define LP_IO_LP_GPIO1_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO1_FUN_DRV_S 10 +/** LP_IO_LP_GPIO1_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO1_MCU_SEL_M (LP_IO_LP_GPIO1_MCU_SEL_V << LP_IO_LP_GPIO1_MCU_SEL_S) +#define LP_IO_LP_GPIO1_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO1_MCU_SEL_S 12 + +/** LP_IO_GPIO2_REG register + * need des + */ +#define LP_IO_GPIO2_REG (DR_REG_LP_IO_BASE + 0x50) +/** LP_IO_LP_GPIO2_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO2_MCU_OE_M (LP_IO_LP_GPIO2_MCU_OE_V << LP_IO_LP_GPIO2_MCU_OE_S) +#define LP_IO_LP_GPIO2_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO2_MCU_OE_S 0 +/** LP_IO_LP_GPIO2_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO2_SLP_SEL_M (LP_IO_LP_GPIO2_SLP_SEL_V << LP_IO_LP_GPIO2_SLP_SEL_S) +#define LP_IO_LP_GPIO2_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO2_SLP_SEL_S 1 +/** LP_IO_LP_GPIO2_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO2_MCU_WPD_M (LP_IO_LP_GPIO2_MCU_WPD_V << LP_IO_LP_GPIO2_MCU_WPD_S) +#define LP_IO_LP_GPIO2_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO2_MCU_WPD_S 2 +/** LP_IO_LP_GPIO2_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO2_MCU_WPU_M (LP_IO_LP_GPIO2_MCU_WPU_V << LP_IO_LP_GPIO2_MCU_WPU_S) +#define LP_IO_LP_GPIO2_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO2_MCU_WPU_S 3 +/** LP_IO_LP_GPIO2_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO2_MCU_IE_M (LP_IO_LP_GPIO2_MCU_IE_V << LP_IO_LP_GPIO2_MCU_IE_S) +#define LP_IO_LP_GPIO2_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO2_MCU_IE_S 4 +/** LP_IO_LP_GPIO2_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO2_MCU_DRV_M (LP_IO_LP_GPIO2_MCU_DRV_V << LP_IO_LP_GPIO2_MCU_DRV_S) +#define LP_IO_LP_GPIO2_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO2_MCU_DRV_S 5 +/** LP_IO_LP_GPIO2_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO2_FUN_WPD_M (LP_IO_LP_GPIO2_FUN_WPD_V << LP_IO_LP_GPIO2_FUN_WPD_S) +#define LP_IO_LP_GPIO2_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO2_FUN_WPD_S 7 +/** LP_IO_LP_GPIO2_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO2_FUN_WPU_M (LP_IO_LP_GPIO2_FUN_WPU_V << LP_IO_LP_GPIO2_FUN_WPU_S) +#define LP_IO_LP_GPIO2_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO2_FUN_WPU_S 8 +/** LP_IO_LP_GPIO2_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO2_FUN_IE_M (LP_IO_LP_GPIO2_FUN_IE_V << LP_IO_LP_GPIO2_FUN_IE_S) +#define LP_IO_LP_GPIO2_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO2_FUN_IE_S 9 +/** LP_IO_LP_GPIO2_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO2_FUN_DRV_M (LP_IO_LP_GPIO2_FUN_DRV_V << LP_IO_LP_GPIO2_FUN_DRV_S) +#define LP_IO_LP_GPIO2_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO2_FUN_DRV_S 10 +/** LP_IO_LP_GPIO2_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO2_MCU_SEL_M (LP_IO_LP_GPIO2_MCU_SEL_V << LP_IO_LP_GPIO2_MCU_SEL_S) +#define LP_IO_LP_GPIO2_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO2_MCU_SEL_S 12 + +/** LP_IO_GPIO3_REG register + * need des + */ +#define LP_IO_GPIO3_REG (DR_REG_LP_IO_BASE + 0x54) +/** LP_IO_LP_GPIO3_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO3_MCU_OE_M (LP_IO_LP_GPIO3_MCU_OE_V << LP_IO_LP_GPIO3_MCU_OE_S) +#define LP_IO_LP_GPIO3_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO3_MCU_OE_S 0 +/** LP_IO_LP_GPIO3_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO3_SLP_SEL_M (LP_IO_LP_GPIO3_SLP_SEL_V << LP_IO_LP_GPIO3_SLP_SEL_S) +#define LP_IO_LP_GPIO3_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO3_SLP_SEL_S 1 +/** LP_IO_LP_GPIO3_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO3_MCU_WPD_M (LP_IO_LP_GPIO3_MCU_WPD_V << LP_IO_LP_GPIO3_MCU_WPD_S) +#define LP_IO_LP_GPIO3_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO3_MCU_WPD_S 2 +/** LP_IO_LP_GPIO3_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO3_MCU_WPU_M (LP_IO_LP_GPIO3_MCU_WPU_V << LP_IO_LP_GPIO3_MCU_WPU_S) +#define LP_IO_LP_GPIO3_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO3_MCU_WPU_S 3 +/** LP_IO_LP_GPIO3_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO3_MCU_IE_M (LP_IO_LP_GPIO3_MCU_IE_V << LP_IO_LP_GPIO3_MCU_IE_S) +#define LP_IO_LP_GPIO3_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO3_MCU_IE_S 4 +/** LP_IO_LP_GPIO3_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO3_MCU_DRV_M (LP_IO_LP_GPIO3_MCU_DRV_V << LP_IO_LP_GPIO3_MCU_DRV_S) +#define LP_IO_LP_GPIO3_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO3_MCU_DRV_S 5 +/** LP_IO_LP_GPIO3_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO3_FUN_WPD_M (LP_IO_LP_GPIO3_FUN_WPD_V << LP_IO_LP_GPIO3_FUN_WPD_S) +#define LP_IO_LP_GPIO3_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO3_FUN_WPD_S 7 +/** LP_IO_LP_GPIO3_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO3_FUN_WPU_M (LP_IO_LP_GPIO3_FUN_WPU_V << LP_IO_LP_GPIO3_FUN_WPU_S) +#define LP_IO_LP_GPIO3_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO3_FUN_WPU_S 8 +/** LP_IO_LP_GPIO3_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO3_FUN_IE_M (LP_IO_LP_GPIO3_FUN_IE_V << LP_IO_LP_GPIO3_FUN_IE_S) +#define LP_IO_LP_GPIO3_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO3_FUN_IE_S 9 +/** LP_IO_LP_GPIO3_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO3_FUN_DRV_M (LP_IO_LP_GPIO3_FUN_DRV_V << LP_IO_LP_GPIO3_FUN_DRV_S) +#define LP_IO_LP_GPIO3_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO3_FUN_DRV_S 10 +/** LP_IO_LP_GPIO3_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO3_MCU_SEL_M (LP_IO_LP_GPIO3_MCU_SEL_V << LP_IO_LP_GPIO3_MCU_SEL_S) +#define LP_IO_LP_GPIO3_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO3_MCU_SEL_S 12 + +/** LP_IO_GPIO4_REG register + * need des + */ +#define LP_IO_GPIO4_REG (DR_REG_LP_IO_BASE + 0x58) +/** LP_IO_LP_GPIO4_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO4_MCU_OE_M (LP_IO_LP_GPIO4_MCU_OE_V << LP_IO_LP_GPIO4_MCU_OE_S) +#define LP_IO_LP_GPIO4_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO4_MCU_OE_S 0 +/** LP_IO_LP_GPIO4_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO4_SLP_SEL_M (LP_IO_LP_GPIO4_SLP_SEL_V << LP_IO_LP_GPIO4_SLP_SEL_S) +#define LP_IO_LP_GPIO4_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO4_SLP_SEL_S 1 +/** LP_IO_LP_GPIO4_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO4_MCU_WPD_M (LP_IO_LP_GPIO4_MCU_WPD_V << LP_IO_LP_GPIO4_MCU_WPD_S) +#define LP_IO_LP_GPIO4_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO4_MCU_WPD_S 2 +/** LP_IO_LP_GPIO4_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO4_MCU_WPU_M (LP_IO_LP_GPIO4_MCU_WPU_V << LP_IO_LP_GPIO4_MCU_WPU_S) +#define LP_IO_LP_GPIO4_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO4_MCU_WPU_S 3 +/** LP_IO_LP_GPIO4_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO4_MCU_IE_M (LP_IO_LP_GPIO4_MCU_IE_V << LP_IO_LP_GPIO4_MCU_IE_S) +#define LP_IO_LP_GPIO4_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO4_MCU_IE_S 4 +/** LP_IO_LP_GPIO4_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO4_MCU_DRV_M (LP_IO_LP_GPIO4_MCU_DRV_V << LP_IO_LP_GPIO4_MCU_DRV_S) +#define LP_IO_LP_GPIO4_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO4_MCU_DRV_S 5 +/** LP_IO_LP_GPIO4_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO4_FUN_WPD_M (LP_IO_LP_GPIO4_FUN_WPD_V << LP_IO_LP_GPIO4_FUN_WPD_S) +#define LP_IO_LP_GPIO4_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO4_FUN_WPD_S 7 +/** LP_IO_LP_GPIO4_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO4_FUN_WPU_M (LP_IO_LP_GPIO4_FUN_WPU_V << LP_IO_LP_GPIO4_FUN_WPU_S) +#define LP_IO_LP_GPIO4_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO4_FUN_WPU_S 8 +/** LP_IO_LP_GPIO4_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO4_FUN_IE_M (LP_IO_LP_GPIO4_FUN_IE_V << LP_IO_LP_GPIO4_FUN_IE_S) +#define LP_IO_LP_GPIO4_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO4_FUN_IE_S 9 +/** LP_IO_LP_GPIO4_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO4_FUN_DRV_M (LP_IO_LP_GPIO4_FUN_DRV_V << LP_IO_LP_GPIO4_FUN_DRV_S) +#define LP_IO_LP_GPIO4_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO4_FUN_DRV_S 10 +/** LP_IO_LP_GPIO4_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO4_MCU_SEL_M (LP_IO_LP_GPIO4_MCU_SEL_V << LP_IO_LP_GPIO4_MCU_SEL_S) +#define LP_IO_LP_GPIO4_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO4_MCU_SEL_S 12 + +/** LP_IO_GPIO5_REG register + * need des + */ +#define LP_IO_GPIO5_REG (DR_REG_LP_IO_BASE + 0x5c) +/** LP_IO_LP_GPIO5_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO5_MCU_OE_M (LP_IO_LP_GPIO5_MCU_OE_V << LP_IO_LP_GPIO5_MCU_OE_S) +#define LP_IO_LP_GPIO5_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO5_MCU_OE_S 0 +/** LP_IO_LP_GPIO5_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO5_SLP_SEL_M (LP_IO_LP_GPIO5_SLP_SEL_V << LP_IO_LP_GPIO5_SLP_SEL_S) +#define LP_IO_LP_GPIO5_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO5_SLP_SEL_S 1 +/** LP_IO_LP_GPIO5_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO5_MCU_WPD_M (LP_IO_LP_GPIO5_MCU_WPD_V << LP_IO_LP_GPIO5_MCU_WPD_S) +#define LP_IO_LP_GPIO5_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO5_MCU_WPD_S 2 +/** LP_IO_LP_GPIO5_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO5_MCU_WPU_M (LP_IO_LP_GPIO5_MCU_WPU_V << LP_IO_LP_GPIO5_MCU_WPU_S) +#define LP_IO_LP_GPIO5_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO5_MCU_WPU_S 3 +/** LP_IO_LP_GPIO5_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO5_MCU_IE_M (LP_IO_LP_GPIO5_MCU_IE_V << LP_IO_LP_GPIO5_MCU_IE_S) +#define LP_IO_LP_GPIO5_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO5_MCU_IE_S 4 +/** LP_IO_LP_GPIO5_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO5_MCU_DRV_M (LP_IO_LP_GPIO5_MCU_DRV_V << LP_IO_LP_GPIO5_MCU_DRV_S) +#define LP_IO_LP_GPIO5_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO5_MCU_DRV_S 5 +/** LP_IO_LP_GPIO5_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO5_FUN_WPD_M (LP_IO_LP_GPIO5_FUN_WPD_V << LP_IO_LP_GPIO5_FUN_WPD_S) +#define LP_IO_LP_GPIO5_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO5_FUN_WPD_S 7 +/** LP_IO_LP_GPIO5_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO5_FUN_WPU_M (LP_IO_LP_GPIO5_FUN_WPU_V << LP_IO_LP_GPIO5_FUN_WPU_S) +#define LP_IO_LP_GPIO5_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO5_FUN_WPU_S 8 +/** LP_IO_LP_GPIO5_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO5_FUN_IE_M (LP_IO_LP_GPIO5_FUN_IE_V << LP_IO_LP_GPIO5_FUN_IE_S) +#define LP_IO_LP_GPIO5_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO5_FUN_IE_S 9 +/** LP_IO_LP_GPIO5_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO5_FUN_DRV_M (LP_IO_LP_GPIO5_FUN_DRV_V << LP_IO_LP_GPIO5_FUN_DRV_S) +#define LP_IO_LP_GPIO5_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO5_FUN_DRV_S 10 +/** LP_IO_LP_GPIO5_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO5_MCU_SEL_M (LP_IO_LP_GPIO5_MCU_SEL_V << LP_IO_LP_GPIO5_MCU_SEL_S) +#define LP_IO_LP_GPIO5_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO5_MCU_SEL_S 12 + +/** LP_IO_GPIO6_REG register + * need des + */ +#define LP_IO_GPIO6_REG (DR_REG_LP_IO_BASE + 0x60) +/** LP_IO_LP_GPIO6_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO6_MCU_OE_M (LP_IO_LP_GPIO6_MCU_OE_V << LP_IO_LP_GPIO6_MCU_OE_S) +#define LP_IO_LP_GPIO6_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO6_MCU_OE_S 0 +/** LP_IO_LP_GPIO6_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO6_SLP_SEL_M (LP_IO_LP_GPIO6_SLP_SEL_V << LP_IO_LP_GPIO6_SLP_SEL_S) +#define LP_IO_LP_GPIO6_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO6_SLP_SEL_S 1 +/** LP_IO_LP_GPIO6_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO6_MCU_WPD_M (LP_IO_LP_GPIO6_MCU_WPD_V << LP_IO_LP_GPIO6_MCU_WPD_S) +#define LP_IO_LP_GPIO6_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO6_MCU_WPD_S 2 +/** LP_IO_LP_GPIO6_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO6_MCU_WPU_M (LP_IO_LP_GPIO6_MCU_WPU_V << LP_IO_LP_GPIO6_MCU_WPU_S) +#define LP_IO_LP_GPIO6_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO6_MCU_WPU_S 3 +/** LP_IO_LP_GPIO6_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO6_MCU_IE_M (LP_IO_LP_GPIO6_MCU_IE_V << LP_IO_LP_GPIO6_MCU_IE_S) +#define LP_IO_LP_GPIO6_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO6_MCU_IE_S 4 +/** LP_IO_LP_GPIO6_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO6_MCU_DRV_M (LP_IO_LP_GPIO6_MCU_DRV_V << LP_IO_LP_GPIO6_MCU_DRV_S) +#define LP_IO_LP_GPIO6_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO6_MCU_DRV_S 5 +/** LP_IO_LP_GPIO6_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO6_FUN_WPD_M (LP_IO_LP_GPIO6_FUN_WPD_V << LP_IO_LP_GPIO6_FUN_WPD_S) +#define LP_IO_LP_GPIO6_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO6_FUN_WPD_S 7 +/** LP_IO_LP_GPIO6_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO6_FUN_WPU_M (LP_IO_LP_GPIO6_FUN_WPU_V << LP_IO_LP_GPIO6_FUN_WPU_S) +#define LP_IO_LP_GPIO6_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO6_FUN_WPU_S 8 +/** LP_IO_LP_GPIO6_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO6_FUN_IE_M (LP_IO_LP_GPIO6_FUN_IE_V << LP_IO_LP_GPIO6_FUN_IE_S) +#define LP_IO_LP_GPIO6_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO6_FUN_IE_S 9 +/** LP_IO_LP_GPIO6_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO6_FUN_DRV_M (LP_IO_LP_GPIO6_FUN_DRV_V << LP_IO_LP_GPIO6_FUN_DRV_S) +#define LP_IO_LP_GPIO6_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO6_FUN_DRV_S 10 +/** LP_IO_LP_GPIO6_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO6_MCU_SEL_M (LP_IO_LP_GPIO6_MCU_SEL_V << LP_IO_LP_GPIO6_MCU_SEL_S) +#define LP_IO_LP_GPIO6_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO6_MCU_SEL_S 12 + +/** LP_IO_GPIO7_REG register + * need des + */ +#define LP_IO_GPIO7_REG (DR_REG_LP_IO_BASE + 0x64) +/** LP_IO_LP_GPIO7_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO7_MCU_OE_M (LP_IO_LP_GPIO7_MCU_OE_V << LP_IO_LP_GPIO7_MCU_OE_S) +#define LP_IO_LP_GPIO7_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO7_MCU_OE_S 0 +/** LP_IO_LP_GPIO7_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO7_SLP_SEL_M (LP_IO_LP_GPIO7_SLP_SEL_V << LP_IO_LP_GPIO7_SLP_SEL_S) +#define LP_IO_LP_GPIO7_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO7_SLP_SEL_S 1 +/** LP_IO_LP_GPIO7_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO7_MCU_WPD_M (LP_IO_LP_GPIO7_MCU_WPD_V << LP_IO_LP_GPIO7_MCU_WPD_S) +#define LP_IO_LP_GPIO7_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO7_MCU_WPD_S 2 +/** LP_IO_LP_GPIO7_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO7_MCU_WPU_M (LP_IO_LP_GPIO7_MCU_WPU_V << LP_IO_LP_GPIO7_MCU_WPU_S) +#define LP_IO_LP_GPIO7_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO7_MCU_WPU_S 3 +/** LP_IO_LP_GPIO7_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO7_MCU_IE_M (LP_IO_LP_GPIO7_MCU_IE_V << LP_IO_LP_GPIO7_MCU_IE_S) +#define LP_IO_LP_GPIO7_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO7_MCU_IE_S 4 +/** LP_IO_LP_GPIO7_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO7_MCU_DRV_M (LP_IO_LP_GPIO7_MCU_DRV_V << LP_IO_LP_GPIO7_MCU_DRV_S) +#define LP_IO_LP_GPIO7_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO7_MCU_DRV_S 5 +/** LP_IO_LP_GPIO7_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO7_FUN_WPD_M (LP_IO_LP_GPIO7_FUN_WPD_V << LP_IO_LP_GPIO7_FUN_WPD_S) +#define LP_IO_LP_GPIO7_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO7_FUN_WPD_S 7 +/** LP_IO_LP_GPIO7_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO7_FUN_WPU_M (LP_IO_LP_GPIO7_FUN_WPU_V << LP_IO_LP_GPIO7_FUN_WPU_S) +#define LP_IO_LP_GPIO7_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO7_FUN_WPU_S 8 +/** LP_IO_LP_GPIO7_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO7_FUN_IE_M (LP_IO_LP_GPIO7_FUN_IE_V << LP_IO_LP_GPIO7_FUN_IE_S) +#define LP_IO_LP_GPIO7_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO7_FUN_IE_S 9 +/** LP_IO_LP_GPIO7_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO7_FUN_DRV_M (LP_IO_LP_GPIO7_FUN_DRV_V << LP_IO_LP_GPIO7_FUN_DRV_S) +#define LP_IO_LP_GPIO7_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO7_FUN_DRV_S 10 +/** LP_IO_LP_GPIO7_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO7_MCU_SEL_M (LP_IO_LP_GPIO7_MCU_SEL_V << LP_IO_LP_GPIO7_MCU_SEL_S) +#define LP_IO_LP_GPIO7_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO7_MCU_SEL_S 12 + +/** LP_IO_STATUS_INTERRUPT_REG register + * need des + */ +#define LP_IO_STATUS_INTERRUPT_REG (DR_REG_LP_IO_BASE + 0x68) +/** LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [7:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT 0x000000FFU +#define LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT_M (LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT_V << LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT_S) +#define LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT_V 0x000000FFU +#define LP_IO_LP_GPIO_STATUS_INTERRUPT_NEXT_S 0 + +/** LP_IO_DEBUG_SEL0_REG register + * need des + */ +#define LP_IO_DEBUG_SEL0_REG (DR_REG_LP_IO_BASE + 0x6c) +/** LP_IO_LP_DEBUG_SEL0 : R/W; bitpos: [6:0]; default: 0; + * need des + */ +#define LP_IO_LP_DEBUG_SEL0 0x0000007FU +#define LP_IO_LP_DEBUG_SEL0_M (LP_IO_LP_DEBUG_SEL0_V << LP_IO_LP_DEBUG_SEL0_S) +#define LP_IO_LP_DEBUG_SEL0_V 0x0000007FU +#define LP_IO_LP_DEBUG_SEL0_S 0 +/** LP_IO_LP_DEBUG_SEL1 : R/W; bitpos: [13:7]; default: 0; + * need des + */ +#define LP_IO_LP_DEBUG_SEL1 0x0000007FU +#define LP_IO_LP_DEBUG_SEL1_M (LP_IO_LP_DEBUG_SEL1_V << LP_IO_LP_DEBUG_SEL1_S) +#define LP_IO_LP_DEBUG_SEL1_V 0x0000007FU +#define LP_IO_LP_DEBUG_SEL1_S 7 +/** LP_IO_LP_DEBUG_SEL2 : R/W; bitpos: [20:14]; default: 0; + * need des + */ +#define LP_IO_LP_DEBUG_SEL2 0x0000007FU +#define LP_IO_LP_DEBUG_SEL2_M (LP_IO_LP_DEBUG_SEL2_V << LP_IO_LP_DEBUG_SEL2_S) +#define LP_IO_LP_DEBUG_SEL2_V 0x0000007FU +#define LP_IO_LP_DEBUG_SEL2_S 14 +/** LP_IO_LP_DEBUG_SEL3 : R/W; bitpos: [27:21]; default: 0; + * need des + */ +#define LP_IO_LP_DEBUG_SEL3 0x0000007FU +#define LP_IO_LP_DEBUG_SEL3_M (LP_IO_LP_DEBUG_SEL3_V << LP_IO_LP_DEBUG_SEL3_S) +#define LP_IO_LP_DEBUG_SEL3_V 0x0000007FU +#define LP_IO_LP_DEBUG_SEL3_S 21 + +/** LP_IO_DEBUG_SEL1_REG register + * need des + */ +#define LP_IO_DEBUG_SEL1_REG (DR_REG_LP_IO_BASE + 0x70) +/** LP_IO_LP_DEBUG_SEL4 : R/W; bitpos: [6:0]; default: 0; + * need des + */ +#define LP_IO_LP_DEBUG_SEL4 0x0000007FU +#define LP_IO_LP_DEBUG_SEL4_M (LP_IO_LP_DEBUG_SEL4_V << LP_IO_LP_DEBUG_SEL4_S) +#define LP_IO_LP_DEBUG_SEL4_V 0x0000007FU +#define LP_IO_LP_DEBUG_SEL4_S 0 + +/** LP_IO_LPI2C_REG register + * need des + */ +#define LP_IO_LPI2C_REG (DR_REG_LP_IO_BASE + 0x74) +/** LP_IO_LP_I2C_SDA_IE : R/W; bitpos: [30]; default: 1; + * need des + */ +#define LP_IO_LP_I2C_SDA_IE (BIT(30)) +#define LP_IO_LP_I2C_SDA_IE_M (LP_IO_LP_I2C_SDA_IE_V << LP_IO_LP_I2C_SDA_IE_S) +#define LP_IO_LP_I2C_SDA_IE_V 0x00000001U +#define LP_IO_LP_I2C_SDA_IE_S 30 +/** LP_IO_LP_I2C_SCL_IE : R/W; bitpos: [31]; default: 1; + * need des + */ +#define LP_IO_LP_I2C_SCL_IE (BIT(31)) +#define LP_IO_LP_I2C_SCL_IE_M (LP_IO_LP_I2C_SCL_IE_V << LP_IO_LP_I2C_SCL_IE_S) +#define LP_IO_LP_I2C_SCL_IE_V 0x00000001U +#define LP_IO_LP_I2C_SCL_IE_S 31 + +/** LP_IO_DATE_REG register + * need des + */ +#define LP_IO_DATE_REG (DR_REG_LP_IO_BASE + 0x3fc) +/** LP_IO_LP_IO_DATE : R/W; bitpos: [30:0]; default: 35660032; + * need des + */ +#define LP_IO_LP_IO_DATE 0x7FFFFFFFU +#define LP_IO_LP_IO_DATE_M (LP_IO_LP_IO_DATE_V << LP_IO_LP_IO_DATE_S) +#define LP_IO_LP_IO_DATE_V 0x7FFFFFFFU +#define LP_IO_LP_IO_DATE_S 0 +/** LP_IO_CLK_EN : R/W; bitpos: [31]; default: 0; + * need des + */ +#define LP_IO_CLK_EN (BIT(31)) +#define LP_IO_CLK_EN_M (LP_IO_CLK_EN_V << LP_IO_CLK_EN_S) +#define LP_IO_CLK_EN_V 0x00000001U +#define LP_IO_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_io_struct.h b/components/soc/esp32c6/include/soc/lp_io_struct.h new file mode 100644 index 0000000000..cfaa3127cf --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_io_struct.h @@ -0,0 +1,362 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of out_data register + * need des + */ +typedef union { + struct { + /** out_data : R/W/WTC; bitpos: [7:0]; default: 0; + * set lp gpio output data + */ + uint32_t out_data:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_out_data_reg_t; + +/** Type of out_data_w1ts register + * need des + */ +typedef union { + struct { + /** out_data_w1ts : WT; bitpos: [7:0]; default: 0; + * set one time output data + */ + uint32_t out_data_w1ts:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_out_data_w1ts_reg_t; + +/** Type of out_data_w1tc register + * need des + */ +typedef union { + struct { + /** out_data_w1tc : WT; bitpos: [7:0]; default: 0; + * clear one time output data + */ + uint32_t out_data_w1tc:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_out_data_w1tc_reg_t; + +/** Type of out_enable register + * need des + */ +typedef union { + struct { + /** enable : R/W/WTC; bitpos: [7:0]; default: 0; + * set lp gpio output data + */ + uint32_t enable:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_out_enable_reg_t; + +/** Type of out_enable_w1ts register + * need des + */ +typedef union { + struct { + /** enable_w1ts : WT; bitpos: [7:0]; default: 0; + * set one time output data + */ + uint32_t enable_w1ts:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_out_enable_w1ts_reg_t; + +/** Type of out_enable_w1tc register + * need des + */ +typedef union { + struct { + /** enable_w1tc : WT; bitpos: [7:0]; default: 0; + * clear one time output data + */ + uint32_t enable_w1tc:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_out_enable_w1tc_reg_t; + +/** Type of status register + * need des + */ +typedef union { + struct { + /** status_interrupt : R/W/WTC; bitpos: [7:0]; default: 0; + * set lp gpio output data + */ + uint32_t status_interrupt:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_status_reg_t; + +/** Type of status_w1ts register + * need des + */ +typedef union { + struct { + /** status_w1ts : WT; bitpos: [7:0]; default: 0; + * set one time output data + */ + uint32_t status_w1ts:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_status_w1ts_reg_t; + +/** Type of status_w1tc register + * need des + */ +typedef union { + struct { + /** status_w1tc : WT; bitpos: [7:0]; default: 0; + * clear one time output data + */ + uint32_t status_w1tc:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_status_w1tc_reg_t; + +/** Type of in register + * need des + */ +typedef union { + struct { + /** in_data_next : RO; bitpos: [7:0]; default: 0; + * need des + */ + uint32_t in_data_next:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_in_reg_t; + +/** Type of pin register + * need des + */ +typedef union { + struct { + /** sync_bypass : R/W; bitpos: [1:0]; default: 0; + * need des + */ + uint32_t sync_bypass:2; + /** pad_driver : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t pad_driver:1; + /** edge_wakeup_clr : WT; bitpos: [3]; default: 0; + * need des + */ + uint32_t edge_wakeup_clr:1; + uint32_t reserved_4:3; + /** int_type : R/W; bitpos: [9:7]; default: 0; + * need des + */ + uint32_t int_type:3; + /** wakeup_enable : R/W; bitpos: [10]; default: 0; + * need des + */ + uint32_t wakeup_enable:1; + /** filter_en : R/W; bitpos: [11]; default: 0; + * need des + */ + uint32_t filter_en:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_io_pin_reg_t; + +/** Type of gpio register + * need des + */ +typedef union { + struct { + /** mcu_oe : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t mcu_oe:1; + /** slp_sel : R/W; bitpos: [1]; default: 0; + * need des + */ + uint32_t slp_sel:1; + /** mcu_wpd : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t mcu_wpd:1; + /** mcu_wpu : R/W; bitpos: [3]; default: 0; + * need des + */ + uint32_t mcu_wpu:1; + /** mcu_ie : R/W; bitpos: [4]; default: 0; + * need des + */ + uint32_t mcu_ie:1; + /** mcu_drv : R/W; bitpos: [6:5]; default: 0; + * need des + */ + uint32_t mcu_drv:2; + /** fun_wpd : R/W; bitpos: [7]; default: 0; + * need des + */ + uint32_t fun_wpd:1; + /** fun_wpu : R/W; bitpos: [8]; default: 0; + * need des + */ + uint32_t fun_wpu:1; + /** fun_ie : R/W; bitpos: [9]; default: 0; + * need des + */ + uint32_t fun_ie:1; + /** fun_drv : R/W; bitpos: [11:10]; default: 0; + * need des + */ + uint32_t fun_drv:2; + /** mcu_sel : R/W; bitpos: [14:12]; default: 0; + * need des + */ + uint32_t mcu_sel:3; + uint32_t reserved_15:17; + }; + uint32_t val; +} lp_io_gpio_reg_t; + +/** Type of status_interrupt register + * need des + */ +typedef union { + struct { + /** status_interrupt_next : RO; bitpos: [7:0]; default: 0; + * need des + */ + uint32_t status_interrupt_next:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_status_interrupt_reg_t; + +/** Type of debug_sel0 register + * need des + */ +typedef union { + struct { + /** debug_sel0 : R/W; bitpos: [6:0]; default: 0; + * need des + */ + uint32_t debug_sel0:7; + /** debug_sel1 : R/W; bitpos: [13:7]; default: 0; + * need des + */ + uint32_t debug_sel1:7; + /** debug_sel2 : R/W; bitpos: [20:14]; default: 0; + * need des + */ + uint32_t debug_sel2:7; + /** debug_sel3 : R/W; bitpos: [27:21]; default: 0; + * need des + */ + uint32_t debug_sel3:7; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_io_debug_sel0_reg_t; + +/** Type of debug_sel1 register + * need des + */ +typedef union { + struct { + /** debug_sel4 : R/W; bitpos: [6:0]; default: 0; + * need des + */ + uint32_t debug_sel4:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lp_io_debug_sel1_reg_t; + +/** Type of lpi2c register + * need des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** lp_i2c_sda_ie : R/W; bitpos: [30]; default: 1; + * need des + */ + uint32_t lp_i2c_sda_ie:1; + /** lp_i2c_scl_ie : R/W; bitpos: [31]; default: 1; + * need des + */ + uint32_t lp_i2c_scl_ie:1; + }; + uint32_t val; +} lp_io_lpi2c_reg_t; + +/** Type of date register + * need des + */ +typedef union { + struct { + /** lp_io_date : R/W; bitpos: [30:0]; default: 35660032; + * need des + */ + uint32_t lp_io_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_io_date_reg_t; + + +typedef struct lp_io_dev_t { + volatile lp_io_out_data_reg_t out_data; + volatile lp_io_out_data_w1ts_reg_t out_data_w1ts; + volatile lp_io_out_data_w1tc_reg_t out_data_w1tc; + volatile lp_io_out_enable_reg_t out_enable; + volatile lp_io_out_enable_w1ts_reg_t out_enable_w1ts; + volatile lp_io_out_enable_w1tc_reg_t out_enable_w1tc; + volatile lp_io_status_reg_t status; + volatile lp_io_status_w1ts_reg_t status_w1ts; + volatile lp_io_status_w1tc_reg_t status_w1tc; + volatile lp_io_in_reg_t in; + volatile lp_io_pin_reg_t pin[8]; + volatile lp_io_gpio_reg_t gpio[8]; + volatile lp_io_status_interrupt_reg_t status_interrupt; + volatile lp_io_debug_sel0_reg_t debug_sel0; + volatile lp_io_debug_sel1_reg_t debug_sel1; + volatile lp_io_lpi2c_reg_t lpi2c; + uint32_t reserved_078[225]; + volatile lp_io_date_reg_t date; +} lp_io_dev_t; + +extern lp_io_dev_t LP_IO; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_io_dev_t) == 0x400, "Invalid size of lp_io_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_tee_reg.h b/components/soc/esp32c6/include/soc/lp_tee_reg.h new file mode 100644 index 0000000000..0c91c59d55 --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_tee_reg.h @@ -0,0 +1,65 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_TEE_M0_MODE_CTRL_REG register + * Tee mode control register + */ +#define LP_TEE_M0_MODE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x0) +/** LP_TEE_M0_MODE : R/W; bitpos: [1:0]; default: 3; + * M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define LP_TEE_M0_MODE 0x00000003U +#define LP_TEE_M0_MODE_M (LP_TEE_M0_MODE_V << LP_TEE_M0_MODE_S) +#define LP_TEE_M0_MODE_V 0x00000003U +#define LP_TEE_M0_MODE_S 0 + +/** LP_TEE_CLOCK_GATE_REG register + * Clock gating register + */ +#define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_TEE_BASE + 0x4) +/** LP_TEE_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define LP_TEE_CLK_EN (BIT(0)) +#define LP_TEE_CLK_EN_M (LP_TEE_CLK_EN_V << LP_TEE_CLK_EN_S) +#define LP_TEE_CLK_EN_V 0x00000001U +#define LP_TEE_CLK_EN_S 0 + +/** LP_TEE_FORCE_ACC_HP_REG register + * need_des + */ +#define LP_TEE_FORCE_ACC_HP_REG (DR_REG_LP_TEE_BASE + 0x90) +/** LP_TEE_FORCE_ACC_HPMEM_EN : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define LP_TEE_FORCE_ACC_HPMEM_EN (BIT(0)) +#define LP_TEE_FORCE_ACC_HPMEM_EN_M (LP_TEE_FORCE_ACC_HPMEM_EN_V << LP_TEE_FORCE_ACC_HPMEM_EN_S) +#define LP_TEE_FORCE_ACC_HPMEM_EN_V 0x00000001U +#define LP_TEE_FORCE_ACC_HPMEM_EN_S 0 + +/** LP_TEE_DATE_REG register + * Version register + */ +#define LP_TEE_DATE_REG (DR_REG_LP_TEE_BASE + 0xfc) +/** LP_TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35672688; + * reg_tee_date + */ +#define LP_TEE_DATE_REG 0x0FFFFFFFU +#define LP_TEE_DATE_REG_M (LP_TEE_DATE_REG_V << LP_TEE_DATE_REG_S) +#define LP_TEE_DATE_REG_V 0x0FFFFFFFU +#define LP_TEE_DATE_REG_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_tee_struct.h b/components/soc/esp32c6/include/soc/lp_tee_struct.h new file mode 100644 index 0000000000..b02b368693 --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_tee_struct.h @@ -0,0 +1,95 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Tee mode control register */ +/** Type of m0_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m0_mode : R/W; bitpos: [1:0]; default: 3; + * M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m0_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_tee_m0_mode_ctrl_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * Clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_tee_clock_gate_reg_t; + + +/** Group: configure_register */ +/** Type of force_acc_hp register + * need_des + */ +typedef union { + struct { + /** force_acc_hpmem_en : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_acc_hpmem_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_tee_force_acc_hp_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date_reg : R/W; bitpos: [27:0]; default: 35672688; + * reg_tee_date + */ + uint32_t date_reg:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_tee_date_reg_t; + + +typedef struct lp_tee_dev_t { + volatile lp_tee_m0_mode_ctrl_reg_t m0_mode_ctrl; + volatile lp_tee_clock_gate_reg_t clock_gate; + uint32_t reserved_008[34]; + volatile lp_tee_force_acc_hp_reg_t force_acc_hp; + uint32_t reserved_094[26]; + volatile lp_tee_date_reg_t date; +} lp_tee_dev_t; + +extern lp_tee_dev_t LP_TEE; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_tee_dev_t) == 0x100, "Invalid size of lp_tee_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_timer_reg.h b/components/soc/esp32c6/include/soc/lp_timer_reg.h new file mode 100644 index 0000000000..482330cd41 --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_timer_reg.h @@ -0,0 +1,342 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_TIMER_TAR0_LOW_REG register + * need_des + */ +#define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0) +/** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_M (LP_TIMER_MAIN_TIMER_TAR_LOW0_V << LP_TIMER_MAIN_TIMER_TAR_LOW0_S) +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_S 0 + +/** LP_TIMER_TAR0_HIGH_REG register + * need_des + */ +#define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x4) +/** LP_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_M (LP_TIMER_MAIN_TIMER_TAR_HIGH0_V << LP_TIMER_MAIN_TIMER_TAR_HIGH0_S) +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_S 0 +/** LP_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31)) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_M (LP_TIMER_MAIN_TIMER_TAR_EN0_V << LP_TIMER_MAIN_TIMER_TAR_EN0_S) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_TAR_EN0_S 31 + +/** LP_TIMER_TAR1_LOW_REG register + * need_des + */ +#define LP_TIMER_TAR1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x8) +/** LP_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_M (LP_TIMER_MAIN_TIMER_TAR_LOW1_V << LP_TIMER_MAIN_TIMER_TAR_LOW1_S) +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_S 0 + +/** LP_TIMER_TAR1_HIGH_REG register + * need_des + */ +#define LP_TIMER_TAR1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0xc) +/** LP_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_M (LP_TIMER_MAIN_TIMER_TAR_HIGH1_V << LP_TIMER_MAIN_TIMER_TAR_HIGH1_S) +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_S 0 +/** LP_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31)) +#define LP_TIMER_MAIN_TIMER_TAR_EN1_M (LP_TIMER_MAIN_TIMER_TAR_EN1_V << LP_TIMER_MAIN_TIMER_TAR_EN1_S) +#define LP_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_TAR_EN1_S 31 + +/** LP_TIMER_UPDATE_REG register + * need_des + */ +#define LP_TIMER_UPDATE_REG (DR_REG_LP_TIMER_BASE + 0x10) +/** LP_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_UPDATE (BIT(28)) +#define LP_TIMER_MAIN_TIMER_UPDATE_M (LP_TIMER_MAIN_TIMER_UPDATE_V << LP_TIMER_MAIN_TIMER_UPDATE_S) +#define LP_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_UPDATE_S 28 +/** LP_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29)) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_M (LP_TIMER_MAIN_TIMER_XTAL_OFF_V << LP_TIMER_MAIN_TIMER_XTAL_OFF_S) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_S 29 +/** LP_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_SYS_STALL (BIT(30)) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_M (LP_TIMER_MAIN_TIMER_SYS_STALL_V << LP_TIMER_MAIN_TIMER_SYS_STALL_S) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_STALL_S 30 +/** LP_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_SYS_RST (BIT(31)) +#define LP_TIMER_MAIN_TIMER_SYS_RST_M (LP_TIMER_MAIN_TIMER_SYS_RST_V << LP_TIMER_MAIN_TIMER_SYS_RST_S) +#define LP_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_RST_S 31 + +/** LP_TIMER_MAIN_BUF0_LOW_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x14) +/** LP_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_M (LP_TIMER_MAIN_TIMER_BUF0_LOW_V << LP_TIMER_MAIN_TIMER_BUF0_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_S 0 + +/** LP_TIMER_MAIN_BUF0_HIGH_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x18) +/** LP_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_M (LP_TIMER_MAIN_TIMER_BUF0_HIGH_V << LP_TIMER_MAIN_TIMER_BUF0_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_S 0 + +/** LP_TIMER_MAIN_BUF1_LOW_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x1c) +/** LP_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_M (LP_TIMER_MAIN_TIMER_BUF1_LOW_V << LP_TIMER_MAIN_TIMER_BUF1_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_S 0 + +/** LP_TIMER_MAIN_BUF1_HIGH_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x20) +/** LP_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_M (LP_TIMER_MAIN_TIMER_BUF1_HIGH_V << LP_TIMER_MAIN_TIMER_BUF1_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_S 0 + +/** LP_TIMER_MAIN_OVERFLOW_REG register + * need_des + */ +#define LP_TIMER_MAIN_OVERFLOW_REG (DR_REG_LP_TIMER_BASE + 0x24) +/** LP_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31)) +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_M (LP_TIMER_MAIN_TIMER_ALARM_LOAD_V << LP_TIMER_MAIN_TIMER_ALARM_LOAD_S) +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_S 31 + +/** LP_TIMER_INT_RAW_REG register + * need_des + */ +#define LP_TIMER_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x28) +/** LP_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_RAW (BIT(30)) +#define LP_TIMER_OVERFLOW_RAW_M (LP_TIMER_OVERFLOW_RAW_V << LP_TIMER_OVERFLOW_RAW_S) +#define LP_TIMER_OVERFLOW_RAW_V 0x00000001U +#define LP_TIMER_OVERFLOW_RAW_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_RAW (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_M (LP_TIMER_SOC_WAKEUP_INT_RAW_V << LP_TIMER_SOC_WAKEUP_INT_RAW_S) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_RAW_S 31 + +/** LP_TIMER_INT_ST_REG register + * need_des + */ +#define LP_TIMER_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x2c) +/** LP_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_ST (BIT(30)) +#define LP_TIMER_OVERFLOW_ST_M (LP_TIMER_OVERFLOW_ST_V << LP_TIMER_OVERFLOW_ST_S) +#define LP_TIMER_OVERFLOW_ST_V 0x00000001U +#define LP_TIMER_OVERFLOW_ST_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_ST (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ST_M (LP_TIMER_SOC_WAKEUP_INT_ST_V << LP_TIMER_SOC_WAKEUP_INT_ST_S) +#define LP_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ST_S 31 + +/** LP_TIMER_INT_ENA_REG register + * need_des + */ +#define LP_TIMER_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x30) +/** LP_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_ENA (BIT(30)) +#define LP_TIMER_OVERFLOW_ENA_M (LP_TIMER_OVERFLOW_ENA_V << LP_TIMER_OVERFLOW_ENA_S) +#define LP_TIMER_OVERFLOW_ENA_V 0x00000001U +#define LP_TIMER_OVERFLOW_ENA_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_ENA (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_M (LP_TIMER_SOC_WAKEUP_INT_ENA_V << LP_TIMER_SOC_WAKEUP_INT_ENA_S) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ENA_S 31 + +/** LP_TIMER_INT_CLR_REG register + * need_des + */ +#define LP_TIMER_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x34) +/** LP_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_CLR (BIT(30)) +#define LP_TIMER_OVERFLOW_CLR_M (LP_TIMER_OVERFLOW_CLR_V << LP_TIMER_OVERFLOW_CLR_S) +#define LP_TIMER_OVERFLOW_CLR_V 0x00000001U +#define LP_TIMER_OVERFLOW_CLR_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_CLR (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_M (LP_TIMER_SOC_WAKEUP_INT_CLR_V << LP_TIMER_SOC_WAKEUP_INT_CLR_S) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_CLR_S 31 + +/** LP_TIMER_LP_INT_RAW_REG register + * need_des + */ +#define LP_TIMER_LP_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x38) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_LP_INT_RAW_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_S 31 + +/** LP_TIMER_LP_INT_ST_REG register + * need_des + */ +#define LP_TIMER_LP_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x3c) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_LP_INT_ST_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_S 31 + +/** LP_TIMER_LP_INT_ENA_REG register + * need_des + */ +#define LP_TIMER_LP_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x40) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_LP_INT_ENA_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_S 31 + +/** LP_TIMER_LP_INT_CLR_REG register + * need_des + */ +#define LP_TIMER_LP_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x44) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_LP_INT_CLR_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_S 31 + +/** LP_TIMER_DATE_REG register + * need_des + */ +#define LP_TIMER_DATE_REG (DR_REG_LP_TIMER_BASE + 0x3fc) +/** LP_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976; + * need_des + */ +#define LP_TIMER_DATE 0x7FFFFFFFU +#define LP_TIMER_DATE_M (LP_TIMER_DATE_V << LP_TIMER_DATE_S) +#define LP_TIMER_DATE_V 0x7FFFFFFFU +#define LP_TIMER_DATE_S 0 +/** LP_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_CLK_EN (BIT(31)) +#define LP_TIMER_CLK_EN_M (LP_TIMER_CLK_EN_V << LP_TIMER_CLK_EN_S) +#define LP_TIMER_CLK_EN_V 0x00000001U +#define LP_TIMER_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_timer_struct.h b/components/soc/esp32c6/include/soc/lp_timer_struct.h new file mode 100644 index 0000000000..a45c0b407e --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_timer_struct.h @@ -0,0 +1,363 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of tar0_low register + * need_des + */ +typedef union { + struct { + /** main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t main_timer_tar_low0:32; + }; + uint32_t val; +} lp_timer_tar0_low_reg_t; + +/** Type of tar0_high register + * need_des + */ +typedef union { + struct { + /** main_timer_tar_high0 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t main_timer_tar_high0:16; + uint32_t reserved_16:15; + /** main_timer_tar_en0 : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_tar_en0:1; + }; + uint32_t val; +} lp_timer_tar0_high_reg_t; + +/** Type of tar1_low register + * need_des + */ +typedef union { + struct { + /** main_timer_tar_low1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t main_timer_tar_low1:32; + }; + uint32_t val; +} lp_timer_tar1_low_reg_t; + +/** Type of tar1_high register + * need_des + */ +typedef union { + struct { + /** main_timer_tar_high1 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t main_timer_tar_high1:16; + uint32_t reserved_16:15; + /** main_timer_tar_en1 : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_tar_en1:1; + }; + uint32_t val; +} lp_timer_tar1_high_reg_t; + +/** Type of update register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** main_timer_update : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t main_timer_update:1; + /** main_timer_xtal_off : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t main_timer_xtal_off:1; + /** main_timer_sys_stall : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_sys_stall:1; + /** main_timer_sys_rst : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_sys_rst:1; + }; + uint32_t val; +} lp_timer_update_reg_t; + +/** Type of main_buf0_low register + * need_des + */ +typedef union { + struct { + /** main_timer_buf0_low : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t main_timer_buf0_low:32; + }; + uint32_t val; +} lp_timer_main_buf0_low_reg_t; + +/** Type of main_buf0_high register + * need_des + */ +typedef union { + struct { + /** main_timer_buf0_high : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t main_timer_buf0_high:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_timer_main_buf0_high_reg_t; + +/** Type of main_buf1_low register + * need_des + */ +typedef union { + struct { + /** main_timer_buf1_low : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t main_timer_buf1_low:32; + }; + uint32_t val; +} lp_timer_main_buf1_low_reg_t; + +/** Type of main_buf1_high register + * need_des + */ +typedef union { + struct { + /** main_timer_buf1_high : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t main_timer_buf1_high:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_timer_main_buf1_high_reg_t; + +/** Type of main_overflow register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** main_timer_alarm_load : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_alarm_load:1; + }; + uint32_t val; +} lp_timer_main_overflow_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_raw:1; + /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_raw:1; + }; + uint32_t val; +} lp_timer_int_raw_reg_t; + +/** Type of int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_st:1; + /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_st:1; + }; + uint32_t val; +} lp_timer_int_st_reg_t; + +/** Type of int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_ena:1; + /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_ena:1; + }; + uint32_t val; +} lp_timer_int_ena_reg_t; + +/** Type of int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_clr:1; + /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_clr:1; + }; + uint32_t val; +} lp_timer_int_clr_reg_t; + +/** Type of lp_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_overflow_lp_int_raw:1; + /** main_timer_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_lp_int_raw:1; + }; + uint32_t val; +} lp_timer_lp_int_raw_reg_t; + +/** Type of lp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_overflow_lp_int_st:1; + /** main_timer_lp_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_lp_int_st:1; + }; + uint32_t val; +} lp_timer_lp_int_st_reg_t; + +/** Type of lp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_overflow_lp_int_ena:1; + /** main_timer_lp_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_lp_int_ena:1; + }; + uint32_t val; +} lp_timer_lp_int_ena_reg_t; + +/** Type of lp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_overflow_lp_int_clr:1; + /** main_timer_lp_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_lp_int_clr:1; + }; + uint32_t val; +} lp_timer_lp_int_clr_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** date : R/W; bitpos: [30:0]; default: 34672976; + * need_des + */ + uint32_t date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_timer_date_reg_t; + + +typedef struct lp_timer_dev_t { + volatile lp_timer_tar0_low_reg_t tar0_low; + volatile lp_timer_tar0_high_reg_t tar0_high; + volatile lp_timer_tar1_low_reg_t tar1_low; + volatile lp_timer_tar1_high_reg_t tar1_high; + volatile lp_timer_update_reg_t update; + volatile lp_timer_main_buf0_low_reg_t main_buf0_low; + volatile lp_timer_main_buf0_high_reg_t main_buf0_high; + volatile lp_timer_main_buf1_low_reg_t main_buf1_low; + volatile lp_timer_main_buf1_high_reg_t main_buf1_high; + volatile lp_timer_main_overflow_reg_t main_overflow; + volatile lp_timer_int_raw_reg_t int_raw; + volatile lp_timer_int_st_reg_t int_st; + volatile lp_timer_int_ena_reg_t int_ena; + volatile lp_timer_int_clr_reg_t int_clr; + volatile lp_timer_lp_int_raw_reg_t lp_int_raw; + volatile lp_timer_lp_int_st_reg_t lp_int_st; + volatile lp_timer_lp_int_ena_reg_t lp_int_ena; + volatile lp_timer_lp_int_clr_reg_t lp_int_clr; + uint32_t reserved_048[237]; + volatile lp_timer_date_reg_t date; +} lp_timer_dev_t; + +extern lp_timer_dev_t LP_TIMER; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_timer_dev_t) == 0x400, "Invalid size of lp_timer_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_uart_reg.h b/components/soc/esp32c6/include/soc/lp_uart_reg.h new file mode 100644 index 0000000000..b67fa1b59e --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_uart_reg.h @@ -0,0 +1,1381 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_UART_FIFO_REG register + * FIFO data register + */ +#define LP_UART_FIFO_REG (DR_REG_LP_UART_BASE + 0x0) +/** LP_UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; + * UART $n accesses FIFO via this register. + */ +#define LP_UART_RXFIFO_RD_BYTE 0x000000FFU +#define LP_UART_RXFIFO_RD_BYTE_M (LP_UART_RXFIFO_RD_BYTE_V << LP_UART_RXFIFO_RD_BYTE_S) +#define LP_UART_RXFIFO_RD_BYTE_V 0x000000FFU +#define LP_UART_RXFIFO_RD_BYTE_S 0 + +/** LP_UART_INT_RAW_REG register + * Raw interrupt status + */ +#define LP_UART_INT_RAW_REG (DR_REG_LP_UART_BASE + 0x4) +/** LP_UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * what rxfifo_full_thrhd specifies. + */ +#define LP_UART_RXFIFO_FULL_INT_RAW (BIT(0)) +#define LP_UART_RXFIFO_FULL_INT_RAW_M (LP_UART_RXFIFO_FULL_INT_RAW_V << LP_UART_RXFIFO_FULL_INT_RAW_S) +#define LP_UART_RXFIFO_FULL_INT_RAW_V 0x00000001U +#define LP_UART_RXFIFO_FULL_INT_RAW_S 0 +/** LP_UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1; + * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is + * less than what txfifo_empty_thrhd specifies . + */ +#define LP_UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define LP_UART_TXFIFO_EMPTY_INT_RAW_M (LP_UART_TXFIFO_EMPTY_INT_RAW_V << LP_UART_TXFIFO_EMPTY_INT_RAW_S) +#define LP_UART_TXFIFO_EMPTY_INT_RAW_V 0x00000001U +#define LP_UART_TXFIFO_EMPTY_INT_RAW_S 1 +/** LP_UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error in + * the data. + */ +#define LP_UART_PARITY_ERR_INT_RAW (BIT(2)) +#define LP_UART_PARITY_ERR_INT_RAW_M (LP_UART_PARITY_ERR_INT_RAW_V << LP_UART_PARITY_ERR_INT_RAW_S) +#define LP_UART_PARITY_ERR_INT_RAW_V 0x00000001U +#define LP_UART_PARITY_ERR_INT_RAW_S 2 +/** LP_UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * . + */ +#define LP_UART_FRM_ERR_INT_RAW (BIT(3)) +#define LP_UART_FRM_ERR_INT_RAW_M (LP_UART_FRM_ERR_INT_RAW_V << LP_UART_FRM_ERR_INT_RAW_S) +#define LP_UART_FRM_ERR_INT_RAW_V 0x00000001U +#define LP_UART_FRM_ERR_INT_RAW_S 3 +/** LP_UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * the FIFO can store. + */ +#define LP_UART_RXFIFO_OVF_INT_RAW (BIT(4)) +#define LP_UART_RXFIFO_OVF_INT_RAW_M (LP_UART_RXFIFO_OVF_INT_RAW_V << LP_UART_RXFIFO_OVF_INT_RAW_S) +#define LP_UART_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define LP_UART_RXFIFO_OVF_INT_RAW_S 4 +/** LP_UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * DSRn signal. + */ +#define LP_UART_DSR_CHG_INT_RAW (BIT(5)) +#define LP_UART_DSR_CHG_INT_RAW_M (LP_UART_DSR_CHG_INT_RAW_V << LP_UART_DSR_CHG_INT_RAW_S) +#define LP_UART_DSR_CHG_INT_RAW_V 0x00000001U +#define LP_UART_DSR_CHG_INT_RAW_S 5 +/** LP_UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * CTSn signal. + */ +#define LP_UART_CTS_CHG_INT_RAW (BIT(6)) +#define LP_UART_CTS_CHG_INT_RAW_M (LP_UART_CTS_CHG_INT_RAW_V << LP_UART_CTS_CHG_INT_RAW_S) +#define LP_UART_CTS_CHG_INT_RAW_V 0x00000001U +#define LP_UART_CTS_CHG_INT_RAW_S 6 +/** LP_UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 after the stop + * bit. + */ +#define LP_UART_BRK_DET_INT_RAW (BIT(7)) +#define LP_UART_BRK_DET_INT_RAW_M (LP_UART_BRK_DET_INT_RAW_V << LP_UART_BRK_DET_INT_RAW_S) +#define LP_UART_BRK_DET_INT_RAW_V 0x00000001U +#define LP_UART_BRK_DET_INT_RAW_S 7 +/** LP_UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more time than + * rx_tout_thrhd to receive a byte. + */ +#define LP_UART_RXFIFO_TOUT_INT_RAW (BIT(8)) +#define LP_UART_RXFIFO_TOUT_INT_RAW_M (LP_UART_RXFIFO_TOUT_INT_RAW_V << LP_UART_RXFIFO_TOUT_INT_RAW_S) +#define LP_UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U +#define LP_UART_RXFIFO_TOUT_INT_RAW_S 8 +/** LP_UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver recevies Xon char when + * uart_sw_flow_con_en is set to 1. + */ +#define LP_UART_SW_XON_INT_RAW (BIT(9)) +#define LP_UART_SW_XON_INT_RAW_M (LP_UART_SW_XON_INT_RAW_V << LP_UART_SW_XON_INT_RAW_S) +#define LP_UART_SW_XON_INT_RAW_V 0x00000001U +#define LP_UART_SW_XON_INT_RAW_S 9 +/** LP_UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xoff char when + * uart_sw_flow_con_en is set to 1. + */ +#define LP_UART_SW_XOFF_INT_RAW (BIT(10)) +#define LP_UART_SW_XOFF_INT_RAW_M (LP_UART_SW_XOFF_INT_RAW_V << LP_UART_SW_XOFF_INT_RAW_S) +#define LP_UART_SW_XOFF_INT_RAW_V 0x00000001U +#define LP_UART_SW_XOFF_INT_RAW_S 10 +/** LP_UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a glitch in the + * middle of a start bit. + */ +#define LP_UART_GLITCH_DET_INT_RAW (BIT(11)) +#define LP_UART_GLITCH_DET_INT_RAW_M (LP_UART_GLITCH_DET_INT_RAW_V << LP_UART_GLITCH_DET_INT_RAW_S) +#define LP_UART_GLITCH_DET_INT_RAW_V 0x00000001U +#define LP_UART_GLITCH_DET_INT_RAW_S 11 +/** LP_UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes sending + * NULL characters after all data in Tx-FIFO are sent. + */ +#define LP_UART_TX_BRK_DONE_INT_RAW (BIT(12)) +#define LP_UART_TX_BRK_DONE_INT_RAW_M (LP_UART_TX_BRK_DONE_INT_RAW_V << LP_UART_TX_BRK_DONE_INT_RAW_S) +#define LP_UART_TX_BRK_DONE_INT_RAW_V 0x00000001U +#define LP_UART_TX_BRK_DONE_INT_RAW_S 12 +/** LP_UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept the shortest + * duration after sending the last data. + */ +#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) +#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_M (LP_UART_TX_BRK_IDLE_DONE_INT_RAW_V << LP_UART_TX_BRK_IDLE_DONE_INT_RAW_S) +#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x00000001U +#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 +/** LP_UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has send out all data + * in FIFO. + */ +#define LP_UART_TX_DONE_INT_RAW (BIT(14)) +#define LP_UART_TX_DONE_INT_RAW_M (LP_UART_TX_DONE_INT_RAW_V << LP_UART_TX_DONE_INT_RAW_S) +#define LP_UART_TX_DONE_INT_RAW_V 0x00000001U +#define LP_UART_TX_DONE_INT_RAW_S 14 +/** LP_UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the configured + * at_cmd char. + */ +#define LP_UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) +#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_M (LP_UART_AT_CMD_CHAR_DET_INT_RAW_V << LP_UART_AT_CMD_CHAR_DET_INT_RAW_S) +#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_V 0x00000001U +#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_S 18 +/** LP_UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes more times + * than what reg_active_threshold specifies in light sleeping mode. + */ +#define LP_UART_WAKEUP_INT_RAW (BIT(19)) +#define LP_UART_WAKEUP_INT_RAW_M (LP_UART_WAKEUP_INT_RAW_V << LP_UART_WAKEUP_INT_RAW_S) +#define LP_UART_WAKEUP_INT_RAW_V 0x00000001U +#define LP_UART_WAKEUP_INT_RAW_S 19 + +/** LP_UART_INT_ST_REG register + * Masked interrupt status + */ +#define LP_UART_INT_ST_REG (DR_REG_LP_UART_BASE + 0x8) +/** LP_UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0; + * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + */ +#define LP_UART_RXFIFO_FULL_INT_ST (BIT(0)) +#define LP_UART_RXFIFO_FULL_INT_ST_M (LP_UART_RXFIFO_FULL_INT_ST_V << LP_UART_RXFIFO_FULL_INT_ST_S) +#define LP_UART_RXFIFO_FULL_INT_ST_V 0x00000001U +#define LP_UART_RXFIFO_FULL_INT_ST_S 0 +/** LP_UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0; + * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set + * to 1. + */ +#define LP_UART_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define LP_UART_TXFIFO_EMPTY_INT_ST_M (LP_UART_TXFIFO_EMPTY_INT_ST_V << LP_UART_TXFIFO_EMPTY_INT_ST_S) +#define LP_UART_TXFIFO_EMPTY_INT_ST_V 0x00000001U +#define LP_UART_TXFIFO_EMPTY_INT_ST_S 1 +/** LP_UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0; + * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + */ +#define LP_UART_PARITY_ERR_INT_ST (BIT(2)) +#define LP_UART_PARITY_ERR_INT_ST_M (LP_UART_PARITY_ERR_INT_ST_V << LP_UART_PARITY_ERR_INT_ST_S) +#define LP_UART_PARITY_ERR_INT_ST_V 0x00000001U +#define LP_UART_PARITY_ERR_INT_ST_S 2 +/** LP_UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0; + * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + */ +#define LP_UART_FRM_ERR_INT_ST (BIT(3)) +#define LP_UART_FRM_ERR_INT_ST_M (LP_UART_FRM_ERR_INT_ST_V << LP_UART_FRM_ERR_INT_ST_S) +#define LP_UART_FRM_ERR_INT_ST_V 0x00000001U +#define LP_UART_FRM_ERR_INT_ST_S 3 +/** LP_UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0; + * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + */ +#define LP_UART_RXFIFO_OVF_INT_ST (BIT(4)) +#define LP_UART_RXFIFO_OVF_INT_ST_M (LP_UART_RXFIFO_OVF_INT_ST_V << LP_UART_RXFIFO_OVF_INT_ST_S) +#define LP_UART_RXFIFO_OVF_INT_ST_V 0x00000001U +#define LP_UART_RXFIFO_OVF_INT_ST_S 4 +/** LP_UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0; + * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + */ +#define LP_UART_DSR_CHG_INT_ST (BIT(5)) +#define LP_UART_DSR_CHG_INT_ST_M (LP_UART_DSR_CHG_INT_ST_V << LP_UART_DSR_CHG_INT_ST_S) +#define LP_UART_DSR_CHG_INT_ST_V 0x00000001U +#define LP_UART_DSR_CHG_INT_ST_S 5 +/** LP_UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0; + * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + */ +#define LP_UART_CTS_CHG_INT_ST (BIT(6)) +#define LP_UART_CTS_CHG_INT_ST_M (LP_UART_CTS_CHG_INT_ST_V << LP_UART_CTS_CHG_INT_ST_S) +#define LP_UART_CTS_CHG_INT_ST_V 0x00000001U +#define LP_UART_CTS_CHG_INT_ST_S 6 +/** LP_UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0; + * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + */ +#define LP_UART_BRK_DET_INT_ST (BIT(7)) +#define LP_UART_BRK_DET_INT_ST_M (LP_UART_BRK_DET_INT_ST_V << LP_UART_BRK_DET_INT_ST_S) +#define LP_UART_BRK_DET_INT_ST_V 0x00000001U +#define LP_UART_BRK_DET_INT_ST_S 7 +/** LP_UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0; + * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + */ +#define LP_UART_RXFIFO_TOUT_INT_ST (BIT(8)) +#define LP_UART_RXFIFO_TOUT_INT_ST_M (LP_UART_RXFIFO_TOUT_INT_ST_V << LP_UART_RXFIFO_TOUT_INT_ST_S) +#define LP_UART_RXFIFO_TOUT_INT_ST_V 0x00000001U +#define LP_UART_RXFIFO_TOUT_INT_ST_S 8 +/** LP_UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0; + * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + */ +#define LP_UART_SW_XON_INT_ST (BIT(9)) +#define LP_UART_SW_XON_INT_ST_M (LP_UART_SW_XON_INT_ST_V << LP_UART_SW_XON_INT_ST_S) +#define LP_UART_SW_XON_INT_ST_V 0x00000001U +#define LP_UART_SW_XON_INT_ST_S 9 +/** LP_UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0; + * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + */ +#define LP_UART_SW_XOFF_INT_ST (BIT(10)) +#define LP_UART_SW_XOFF_INT_ST_M (LP_UART_SW_XOFF_INT_ST_V << LP_UART_SW_XOFF_INT_ST_S) +#define LP_UART_SW_XOFF_INT_ST_V 0x00000001U +#define LP_UART_SW_XOFF_INT_ST_S 10 +/** LP_UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0; + * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + */ +#define LP_UART_GLITCH_DET_INT_ST (BIT(11)) +#define LP_UART_GLITCH_DET_INT_ST_M (LP_UART_GLITCH_DET_INT_ST_V << LP_UART_GLITCH_DET_INT_ST_S) +#define LP_UART_GLITCH_DET_INT_ST_V 0x00000001U +#define LP_UART_GLITCH_DET_INT_ST_S 11 +/** LP_UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0; + * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + */ +#define LP_UART_TX_BRK_DONE_INT_ST (BIT(12)) +#define LP_UART_TX_BRK_DONE_INT_ST_M (LP_UART_TX_BRK_DONE_INT_ST_V << LP_UART_TX_BRK_DONE_INT_ST_S) +#define LP_UART_TX_BRK_DONE_INT_ST_V 0x00000001U +#define LP_UART_TX_BRK_DONE_INT_ST_S 12 +/** LP_UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; + * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * is set to 1. + */ +#define LP_UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) +#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_M (LP_UART_TX_BRK_IDLE_DONE_INT_ST_V << LP_UART_TX_BRK_IDLE_DONE_INT_ST_S) +#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_V 0x00000001U +#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_S 13 +/** LP_UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + */ +#define LP_UART_TX_DONE_INT_ST (BIT(14)) +#define LP_UART_TX_DONE_INT_ST_M (LP_UART_TX_DONE_INT_ST_V << LP_UART_TX_DONE_INT_ST_S) +#define LP_UART_TX_DONE_INT_ST_V 0x00000001U +#define LP_UART_TX_DONE_INT_ST_S 14 +/** LP_UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0; + * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set + * to 1. + */ +#define LP_UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) +#define LP_UART_AT_CMD_CHAR_DET_INT_ST_M (LP_UART_AT_CMD_CHAR_DET_INT_ST_V << LP_UART_AT_CMD_CHAR_DET_INT_ST_S) +#define LP_UART_AT_CMD_CHAR_DET_INT_ST_V 0x00000001U +#define LP_UART_AT_CMD_CHAR_DET_INT_ST_S 18 +/** LP_UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0; + * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + */ +#define LP_UART_WAKEUP_INT_ST (BIT(19)) +#define LP_UART_WAKEUP_INT_ST_M (LP_UART_WAKEUP_INT_ST_V << LP_UART_WAKEUP_INT_ST_S) +#define LP_UART_WAKEUP_INT_ST_V 0x00000001U +#define LP_UART_WAKEUP_INT_ST_S 19 + +/** LP_UART_INT_ENA_REG register + * Interrupt enable bits + */ +#define LP_UART_INT_ENA_REG (DR_REG_LP_UART_BASE + 0xc) +/** LP_UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0; + * This is the enable bit for rxfifo_full_int_st register. + */ +#define LP_UART_RXFIFO_FULL_INT_ENA (BIT(0)) +#define LP_UART_RXFIFO_FULL_INT_ENA_M (LP_UART_RXFIFO_FULL_INT_ENA_V << LP_UART_RXFIFO_FULL_INT_ENA_S) +#define LP_UART_RXFIFO_FULL_INT_ENA_V 0x00000001U +#define LP_UART_RXFIFO_FULL_INT_ENA_S 0 +/** LP_UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0; + * This is the enable bit for txfifo_empty_int_st register. + */ +#define LP_UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define LP_UART_TXFIFO_EMPTY_INT_ENA_M (LP_UART_TXFIFO_EMPTY_INT_ENA_V << LP_UART_TXFIFO_EMPTY_INT_ENA_S) +#define LP_UART_TXFIFO_EMPTY_INT_ENA_V 0x00000001U +#define LP_UART_TXFIFO_EMPTY_INT_ENA_S 1 +/** LP_UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0; + * This is the enable bit for parity_err_int_st register. + */ +#define LP_UART_PARITY_ERR_INT_ENA (BIT(2)) +#define LP_UART_PARITY_ERR_INT_ENA_M (LP_UART_PARITY_ERR_INT_ENA_V << LP_UART_PARITY_ERR_INT_ENA_S) +#define LP_UART_PARITY_ERR_INT_ENA_V 0x00000001U +#define LP_UART_PARITY_ERR_INT_ENA_S 2 +/** LP_UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0; + * This is the enable bit for frm_err_int_st register. + */ +#define LP_UART_FRM_ERR_INT_ENA (BIT(3)) +#define LP_UART_FRM_ERR_INT_ENA_M (LP_UART_FRM_ERR_INT_ENA_V << LP_UART_FRM_ERR_INT_ENA_S) +#define LP_UART_FRM_ERR_INT_ENA_V 0x00000001U +#define LP_UART_FRM_ERR_INT_ENA_S 3 +/** LP_UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; + * This is the enable bit for rxfifo_ovf_int_st register. + */ +#define LP_UART_RXFIFO_OVF_INT_ENA (BIT(4)) +#define LP_UART_RXFIFO_OVF_INT_ENA_M (LP_UART_RXFIFO_OVF_INT_ENA_V << LP_UART_RXFIFO_OVF_INT_ENA_S) +#define LP_UART_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define LP_UART_RXFIFO_OVF_INT_ENA_S 4 +/** LP_UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0; + * This is the enable bit for dsr_chg_int_st register. + */ +#define LP_UART_DSR_CHG_INT_ENA (BIT(5)) +#define LP_UART_DSR_CHG_INT_ENA_M (LP_UART_DSR_CHG_INT_ENA_V << LP_UART_DSR_CHG_INT_ENA_S) +#define LP_UART_DSR_CHG_INT_ENA_V 0x00000001U +#define LP_UART_DSR_CHG_INT_ENA_S 5 +/** LP_UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0; + * This is the enable bit for cts_chg_int_st register. + */ +#define LP_UART_CTS_CHG_INT_ENA (BIT(6)) +#define LP_UART_CTS_CHG_INT_ENA_M (LP_UART_CTS_CHG_INT_ENA_V << LP_UART_CTS_CHG_INT_ENA_S) +#define LP_UART_CTS_CHG_INT_ENA_V 0x00000001U +#define LP_UART_CTS_CHG_INT_ENA_S 6 +/** LP_UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0; + * This is the enable bit for brk_det_int_st register. + */ +#define LP_UART_BRK_DET_INT_ENA (BIT(7)) +#define LP_UART_BRK_DET_INT_ENA_M (LP_UART_BRK_DET_INT_ENA_V << LP_UART_BRK_DET_INT_ENA_S) +#define LP_UART_BRK_DET_INT_ENA_V 0x00000001U +#define LP_UART_BRK_DET_INT_ENA_S 7 +/** LP_UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * This is the enable bit for rxfifo_tout_int_st register. + */ +#define LP_UART_RXFIFO_TOUT_INT_ENA (BIT(8)) +#define LP_UART_RXFIFO_TOUT_INT_ENA_M (LP_UART_RXFIFO_TOUT_INT_ENA_V << LP_UART_RXFIFO_TOUT_INT_ENA_S) +#define LP_UART_RXFIFO_TOUT_INT_ENA_V 0x00000001U +#define LP_UART_RXFIFO_TOUT_INT_ENA_S 8 +/** LP_UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0; + * This is the enable bit for sw_xon_int_st register. + */ +#define LP_UART_SW_XON_INT_ENA (BIT(9)) +#define LP_UART_SW_XON_INT_ENA_M (LP_UART_SW_XON_INT_ENA_V << LP_UART_SW_XON_INT_ENA_S) +#define LP_UART_SW_XON_INT_ENA_V 0x00000001U +#define LP_UART_SW_XON_INT_ENA_S 9 +/** LP_UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0; + * This is the enable bit for sw_xoff_int_st register. + */ +#define LP_UART_SW_XOFF_INT_ENA (BIT(10)) +#define LP_UART_SW_XOFF_INT_ENA_M (LP_UART_SW_XOFF_INT_ENA_V << LP_UART_SW_XOFF_INT_ENA_S) +#define LP_UART_SW_XOFF_INT_ENA_V 0x00000001U +#define LP_UART_SW_XOFF_INT_ENA_S 10 +/** LP_UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0; + * This is the enable bit for glitch_det_int_st register. + */ +#define LP_UART_GLITCH_DET_INT_ENA (BIT(11)) +#define LP_UART_GLITCH_DET_INT_ENA_M (LP_UART_GLITCH_DET_INT_ENA_V << LP_UART_GLITCH_DET_INT_ENA_S) +#define LP_UART_GLITCH_DET_INT_ENA_V 0x00000001U +#define LP_UART_GLITCH_DET_INT_ENA_S 11 +/** LP_UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; + * This is the enable bit for tx_brk_done_int_st register. + */ +#define LP_UART_TX_BRK_DONE_INT_ENA (BIT(12)) +#define LP_UART_TX_BRK_DONE_INT_ENA_M (LP_UART_TX_BRK_DONE_INT_ENA_V << LP_UART_TX_BRK_DONE_INT_ENA_S) +#define LP_UART_TX_BRK_DONE_INT_ENA_V 0x00000001U +#define LP_UART_TX_BRK_DONE_INT_ENA_S 12 +/** LP_UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; + * This is the enable bit for tx_brk_idle_done_int_st register. + */ +#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) +#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_M (LP_UART_TX_BRK_IDLE_DONE_INT_ENA_V << LP_UART_TX_BRK_IDLE_DONE_INT_ENA_S) +#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x00000001U +#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 +/** LP_UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * This is the enable bit for tx_done_int_st register. + */ +#define LP_UART_TX_DONE_INT_ENA (BIT(14)) +#define LP_UART_TX_DONE_INT_ENA_M (LP_UART_TX_DONE_INT_ENA_V << LP_UART_TX_DONE_INT_ENA_S) +#define LP_UART_TX_DONE_INT_ENA_V 0x00000001U +#define LP_UART_TX_DONE_INT_ENA_S 14 +/** LP_UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0; + * This is the enable bit for at_cmd_char_det_int_st register. + */ +#define LP_UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) +#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_M (LP_UART_AT_CMD_CHAR_DET_INT_ENA_V << LP_UART_AT_CMD_CHAR_DET_INT_ENA_S) +#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_V 0x00000001U +#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_S 18 +/** LP_UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0; + * This is the enable bit for uart_wakeup_int_st register. + */ +#define LP_UART_WAKEUP_INT_ENA (BIT(19)) +#define LP_UART_WAKEUP_INT_ENA_M (LP_UART_WAKEUP_INT_ENA_V << LP_UART_WAKEUP_INT_ENA_S) +#define LP_UART_WAKEUP_INT_ENA_V 0x00000001U +#define LP_UART_WAKEUP_INT_ENA_S 19 + +/** LP_UART_INT_CLR_REG register + * Interrupt clear bits + */ +#define LP_UART_INT_CLR_REG (DR_REG_LP_UART_BASE + 0x10) +/** LP_UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the rxfifo_full_int_raw interrupt. + */ +#define LP_UART_RXFIFO_FULL_INT_CLR (BIT(0)) +#define LP_UART_RXFIFO_FULL_INT_CLR_M (LP_UART_RXFIFO_FULL_INT_CLR_V << LP_UART_RXFIFO_FULL_INT_CLR_S) +#define LP_UART_RXFIFO_FULL_INT_CLR_V 0x00000001U +#define LP_UART_RXFIFO_FULL_INT_CLR_S 0 +/** LP_UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear txfifo_empty_int_raw interrupt. + */ +#define LP_UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define LP_UART_TXFIFO_EMPTY_INT_CLR_M (LP_UART_TXFIFO_EMPTY_INT_CLR_V << LP_UART_TXFIFO_EMPTY_INT_CLR_S) +#define LP_UART_TXFIFO_EMPTY_INT_CLR_V 0x00000001U +#define LP_UART_TXFIFO_EMPTY_INT_CLR_S 1 +/** LP_UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear parity_err_int_raw interrupt. + */ +#define LP_UART_PARITY_ERR_INT_CLR (BIT(2)) +#define LP_UART_PARITY_ERR_INT_CLR_M (LP_UART_PARITY_ERR_INT_CLR_V << LP_UART_PARITY_ERR_INT_CLR_S) +#define LP_UART_PARITY_ERR_INT_CLR_V 0x00000001U +#define LP_UART_PARITY_ERR_INT_CLR_S 2 +/** LP_UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear frm_err_int_raw interrupt. + */ +#define LP_UART_FRM_ERR_INT_CLR (BIT(3)) +#define LP_UART_FRM_ERR_INT_CLR_M (LP_UART_FRM_ERR_INT_CLR_V << LP_UART_FRM_ERR_INT_CLR_S) +#define LP_UART_FRM_ERR_INT_CLR_V 0x00000001U +#define LP_UART_FRM_ERR_INT_CLR_S 3 +/** LP_UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear rxfifo_ovf_int_raw interrupt. + */ +#define LP_UART_RXFIFO_OVF_INT_CLR (BIT(4)) +#define LP_UART_RXFIFO_OVF_INT_CLR_M (LP_UART_RXFIFO_OVF_INT_CLR_V << LP_UART_RXFIFO_OVF_INT_CLR_S) +#define LP_UART_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define LP_UART_RXFIFO_OVF_INT_CLR_S 4 +/** LP_UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the dsr_chg_int_raw interrupt. + */ +#define LP_UART_DSR_CHG_INT_CLR (BIT(5)) +#define LP_UART_DSR_CHG_INT_CLR_M (LP_UART_DSR_CHG_INT_CLR_V << LP_UART_DSR_CHG_INT_CLR_S) +#define LP_UART_DSR_CHG_INT_CLR_V 0x00000001U +#define LP_UART_DSR_CHG_INT_CLR_S 5 +/** LP_UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the cts_chg_int_raw interrupt. + */ +#define LP_UART_CTS_CHG_INT_CLR (BIT(6)) +#define LP_UART_CTS_CHG_INT_CLR_M (LP_UART_CTS_CHG_INT_CLR_V << LP_UART_CTS_CHG_INT_CLR_S) +#define LP_UART_CTS_CHG_INT_CLR_V 0x00000001U +#define LP_UART_CTS_CHG_INT_CLR_S 6 +/** LP_UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the brk_det_int_raw interrupt. + */ +#define LP_UART_BRK_DET_INT_CLR (BIT(7)) +#define LP_UART_BRK_DET_INT_CLR_M (LP_UART_BRK_DET_INT_CLR_V << LP_UART_BRK_DET_INT_CLR_S) +#define LP_UART_BRK_DET_INT_CLR_V 0x00000001U +#define LP_UART_BRK_DET_INT_CLR_S 7 +/** LP_UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the rxfifo_tout_int_raw interrupt. + */ +#define LP_UART_RXFIFO_TOUT_INT_CLR (BIT(8)) +#define LP_UART_RXFIFO_TOUT_INT_CLR_M (LP_UART_RXFIFO_TOUT_INT_CLR_V << LP_UART_RXFIFO_TOUT_INT_CLR_S) +#define LP_UART_RXFIFO_TOUT_INT_CLR_V 0x00000001U +#define LP_UART_RXFIFO_TOUT_INT_CLR_S 8 +/** LP_UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the sw_xon_int_raw interrupt. + */ +#define LP_UART_SW_XON_INT_CLR (BIT(9)) +#define LP_UART_SW_XON_INT_CLR_M (LP_UART_SW_XON_INT_CLR_V << LP_UART_SW_XON_INT_CLR_S) +#define LP_UART_SW_XON_INT_CLR_V 0x00000001U +#define LP_UART_SW_XON_INT_CLR_S 9 +/** LP_UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the sw_xoff_int_raw interrupt. + */ +#define LP_UART_SW_XOFF_INT_CLR (BIT(10)) +#define LP_UART_SW_XOFF_INT_CLR_M (LP_UART_SW_XOFF_INT_CLR_V << LP_UART_SW_XOFF_INT_CLR_S) +#define LP_UART_SW_XOFF_INT_CLR_V 0x00000001U +#define LP_UART_SW_XOFF_INT_CLR_S 10 +/** LP_UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the glitch_det_int_raw interrupt. + */ +#define LP_UART_GLITCH_DET_INT_CLR (BIT(11)) +#define LP_UART_GLITCH_DET_INT_CLR_M (LP_UART_GLITCH_DET_INT_CLR_V << LP_UART_GLITCH_DET_INT_CLR_S) +#define LP_UART_GLITCH_DET_INT_CLR_V 0x00000001U +#define LP_UART_GLITCH_DET_INT_CLR_S 11 +/** LP_UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the tx_brk_done_int_raw interrupt.. + */ +#define LP_UART_TX_BRK_DONE_INT_CLR (BIT(12)) +#define LP_UART_TX_BRK_DONE_INT_CLR_M (LP_UART_TX_BRK_DONE_INT_CLR_V << LP_UART_TX_BRK_DONE_INT_CLR_S) +#define LP_UART_TX_BRK_DONE_INT_CLR_V 0x00000001U +#define LP_UART_TX_BRK_DONE_INT_CLR_S 12 +/** LP_UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + */ +#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) +#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_M (LP_UART_TX_BRK_IDLE_DONE_INT_CLR_V << LP_UART_TX_BRK_IDLE_DONE_INT_CLR_S) +#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x00000001U +#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 +/** LP_UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the tx_done_int_raw interrupt. + */ +#define LP_UART_TX_DONE_INT_CLR (BIT(14)) +#define LP_UART_TX_DONE_INT_CLR_M (LP_UART_TX_DONE_INT_CLR_V << LP_UART_TX_DONE_INT_CLR_S) +#define LP_UART_TX_DONE_INT_CLR_V 0x00000001U +#define LP_UART_TX_DONE_INT_CLR_S 14 +/** LP_UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear the at_cmd_char_det_int_raw interrupt. + */ +#define LP_UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) +#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_M (LP_UART_AT_CMD_CHAR_DET_INT_CLR_V << LP_UART_AT_CMD_CHAR_DET_INT_CLR_S) +#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_V 0x00000001U +#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_S 18 +/** LP_UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear the uart_wakeup_int_raw interrupt. + */ +#define LP_UART_WAKEUP_INT_CLR (BIT(19)) +#define LP_UART_WAKEUP_INT_CLR_M (LP_UART_WAKEUP_INT_CLR_V << LP_UART_WAKEUP_INT_CLR_S) +#define LP_UART_WAKEUP_INT_CLR_V 0x00000001U +#define LP_UART_WAKEUP_INT_CLR_S 19 + +/** LP_UART_CLKDIV_SYNC_REG register + * Clock divider configuration + */ +#define LP_UART_CLKDIV_SYNC_REG (DR_REG_LP_UART_BASE + 0x14) +/** LP_UART_CLKDIV : R/W; bitpos: [11:0]; default: 694; + * The integral part of the frequency divider factor. + */ +#define LP_UART_CLKDIV 0x00000FFFU +#define LP_UART_CLKDIV_M (LP_UART_CLKDIV_V << LP_UART_CLKDIV_S) +#define LP_UART_CLKDIV_V 0x00000FFFU +#define LP_UART_CLKDIV_S 0 +/** LP_UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0; + * The decimal part of the frequency divider factor. + */ +#define LP_UART_CLKDIV_FRAG 0x0000000FU +#define LP_UART_CLKDIV_FRAG_M (LP_UART_CLKDIV_FRAG_V << LP_UART_CLKDIV_FRAG_S) +#define LP_UART_CLKDIV_FRAG_V 0x0000000FU +#define LP_UART_CLKDIV_FRAG_S 20 + +/** LP_UART_RX_FILT_REG register + * Rx Filter configuration + */ +#define LP_UART_RX_FILT_REG (DR_REG_LP_UART_BASE + 0x18) +/** LP_UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8; + * when input pulse width is lower than this value the pulse is ignored. + */ +#define LP_UART_GLITCH_FILT 0x000000FFU +#define LP_UART_GLITCH_FILT_M (LP_UART_GLITCH_FILT_V << LP_UART_GLITCH_FILT_S) +#define LP_UART_GLITCH_FILT_V 0x000000FFU +#define LP_UART_GLITCH_FILT_S 0 +/** LP_UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0; + * Set this bit to enable Rx signal filter. + */ +#define LP_UART_GLITCH_FILT_EN (BIT(8)) +#define LP_UART_GLITCH_FILT_EN_M (LP_UART_GLITCH_FILT_EN_V << LP_UART_GLITCH_FILT_EN_S) +#define LP_UART_GLITCH_FILT_EN_V 0x00000001U +#define LP_UART_GLITCH_FILT_EN_S 8 + +/** LP_UART_STATUS_REG register + * UART status register + */ +#define LP_UART_STATUS_REG (DR_REG_LP_UART_BASE + 0x1c) +/** LP_UART_RXFIFO_CNT : RO; bitpos: [7:3]; default: 0; + * Stores the byte number of valid data in Rx-FIFO. + */ +#define LP_UART_RXFIFO_CNT 0x0000001FU +#define LP_UART_RXFIFO_CNT_M (LP_UART_RXFIFO_CNT_V << LP_UART_RXFIFO_CNT_S) +#define LP_UART_RXFIFO_CNT_V 0x0000001FU +#define LP_UART_RXFIFO_CNT_S 3 +/** LP_UART_DSRN : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal uart dsr signal. + */ +#define LP_UART_DSRN (BIT(13)) +#define LP_UART_DSRN_M (LP_UART_DSRN_V << LP_UART_DSRN_S) +#define LP_UART_DSRN_V 0x00000001U +#define LP_UART_DSRN_S 13 +/** LP_UART_CTSN : RO; bitpos: [14]; default: 1; + * This register represent the level value of the internal uart cts signal. + */ +#define LP_UART_CTSN (BIT(14)) +#define LP_UART_CTSN_M (LP_UART_CTSN_V << LP_UART_CTSN_S) +#define LP_UART_CTSN_V 0x00000001U +#define LP_UART_CTSN_S 14 +/** LP_UART_RXD : RO; bitpos: [15]; default: 1; + * This register represent the level value of the internal uart rxd signal. + */ +#define LP_UART_RXD (BIT(15)) +#define LP_UART_RXD_M (LP_UART_RXD_V << LP_UART_RXD_S) +#define LP_UART_RXD_V 0x00000001U +#define LP_UART_RXD_S 15 +/** LP_UART_TXFIFO_CNT : RO; bitpos: [23:19]; default: 0; + * Stores the byte number of data in Tx-FIFO. + */ +#define LP_UART_TXFIFO_CNT 0x0000001FU +#define LP_UART_TXFIFO_CNT_M (LP_UART_TXFIFO_CNT_V << LP_UART_TXFIFO_CNT_S) +#define LP_UART_TXFIFO_CNT_V 0x0000001FU +#define LP_UART_TXFIFO_CNT_S 19 +/** LP_UART_DTRN : RO; bitpos: [29]; default: 1; + * This bit represents the level of the internal uart dtr signal. + */ +#define LP_UART_DTRN (BIT(29)) +#define LP_UART_DTRN_M (LP_UART_DTRN_V << LP_UART_DTRN_S) +#define LP_UART_DTRN_V 0x00000001U +#define LP_UART_DTRN_S 29 +/** LP_UART_RTSN : RO; bitpos: [30]; default: 1; + * This bit represents the level of the internal uart rts signal. + */ +#define LP_UART_RTSN (BIT(30)) +#define LP_UART_RTSN_M (LP_UART_RTSN_V << LP_UART_RTSN_S) +#define LP_UART_RTSN_V 0x00000001U +#define LP_UART_RTSN_S 30 +/** LP_UART_TXD : RO; bitpos: [31]; default: 1; + * This bit represents the level of the internal uart txd signal. + */ +#define LP_UART_TXD (BIT(31)) +#define LP_UART_TXD_M (LP_UART_TXD_V << LP_UART_TXD_S) +#define LP_UART_TXD_V 0x00000001U +#define LP_UART_TXD_S 31 + +/** LP_UART_CONF0_SYNC_REG register + * Configuration register 0 + */ +#define LP_UART_CONF0_SYNC_REG (DR_REG_LP_UART_BASE + 0x20) +/** LP_UART_PARITY : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check mode. + */ +#define LP_UART_PARITY (BIT(0)) +#define LP_UART_PARITY_M (LP_UART_PARITY_V << LP_UART_PARITY_S) +#define LP_UART_PARITY_V 0x00000001U +#define LP_UART_PARITY_S 0 +/** LP_UART_PARITY_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to enable uart parity check. + */ +#define LP_UART_PARITY_EN (BIT(1)) +#define LP_UART_PARITY_EN_M (LP_UART_PARITY_EN_V << LP_UART_PARITY_EN_S) +#define LP_UART_PARITY_EN_V 0x00000001U +#define LP_UART_PARITY_EN_S 1 +/** LP_UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3; + * This register is used to set the length of data. + */ +#define LP_UART_BIT_NUM 0x00000003U +#define LP_UART_BIT_NUM_M (LP_UART_BIT_NUM_V << LP_UART_BIT_NUM_S) +#define LP_UART_BIT_NUM_V 0x00000003U +#define LP_UART_BIT_NUM_S 2 +/** LP_UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1; + * This register is used to set the length of stop bit. + */ +#define LP_UART_STOP_BIT_NUM 0x00000003U +#define LP_UART_STOP_BIT_NUM_M (LP_UART_STOP_BIT_NUM_V << LP_UART_STOP_BIT_NUM_S) +#define LP_UART_STOP_BIT_NUM_V 0x00000003U +#define LP_UART_STOP_BIT_NUM_S 4 +/** LP_UART_TXD_BRK : R/W; bitpos: [6]; default: 0; + * Set this bit to enbale transmitter to send NULL when the process of sending data + * is done. + */ +#define LP_UART_TXD_BRK (BIT(6)) +#define LP_UART_TXD_BRK_M (LP_UART_TXD_BRK_V << LP_UART_TXD_BRK_S) +#define LP_UART_TXD_BRK_V 0x00000001U +#define LP_UART_TXD_BRK_S 6 +/** LP_UART_LOOPBACK : R/W; bitpos: [12]; default: 0; + * Set this bit to enable uart loopback test mode. + */ +#define LP_UART_LOOPBACK (BIT(12)) +#define LP_UART_LOOPBACK_M (LP_UART_LOOPBACK_V << LP_UART_LOOPBACK_S) +#define LP_UART_LOOPBACK_V 0x00000001U +#define LP_UART_LOOPBACK_S 12 +/** LP_UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0; + * Set this bit to enable flow control function for transmitter. + */ +#define LP_UART_TX_FLOW_EN (BIT(13)) +#define LP_UART_TX_FLOW_EN_M (LP_UART_TX_FLOW_EN_V << LP_UART_TX_FLOW_EN_S) +#define LP_UART_TX_FLOW_EN_V 0x00000001U +#define LP_UART_TX_FLOW_EN_S 13 +/** LP_UART_RXD_INV : R/W; bitpos: [15]; default: 0; + * Set this bit to inverse the level value of uart rxd signal. + */ +#define LP_UART_RXD_INV (BIT(15)) +#define LP_UART_RXD_INV_M (LP_UART_RXD_INV_V << LP_UART_RXD_INV_S) +#define LP_UART_RXD_INV_V 0x00000001U +#define LP_UART_RXD_INV_S 15 +/** LP_UART_TXD_INV : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart txd signal. + */ +#define LP_UART_TXD_INV (BIT(16)) +#define LP_UART_TXD_INV_M (LP_UART_TXD_INV_V << LP_UART_TXD_INV_S) +#define LP_UART_TXD_INV_V 0x00000001U +#define LP_UART_TXD_INV_S 16 +/** LP_UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0; + * Disable UART Rx data overflow detect. + */ +#define LP_UART_DIS_RX_DAT_OVF (BIT(17)) +#define LP_UART_DIS_RX_DAT_OVF_M (LP_UART_DIS_RX_DAT_OVF_V << LP_UART_DIS_RX_DAT_OVF_S) +#define LP_UART_DIS_RX_DAT_OVF_V 0x00000001U +#define LP_UART_DIS_RX_DAT_OVF_S 17 +/** LP_UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver + * stores the data even if the received data is wrong. + */ +#define LP_UART_ERR_WR_MASK (BIT(18)) +#define LP_UART_ERR_WR_MASK_M (LP_UART_ERR_WR_MASK_V << LP_UART_ERR_WR_MASK_S) +#define LP_UART_ERR_WR_MASK_V 0x00000001U +#define LP_UART_ERR_WR_MASK_S 18 +/** LP_UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 1; + * UART memory clock gate enable signal. + */ +#define LP_UART_MEM_CLK_EN (BIT(20)) +#define LP_UART_MEM_CLK_EN_M (LP_UART_MEM_CLK_EN_V << LP_UART_MEM_CLK_EN_S) +#define LP_UART_MEM_CLK_EN_V 0x00000001U +#define LP_UART_MEM_CLK_EN_S 20 +/** LP_UART_SW_RTS : R/W; bitpos: [21]; default: 0; + * This register is used to configure the software rts signal which is used in + * software flow control. + */ +#define LP_UART_SW_RTS (BIT(21)) +#define LP_UART_SW_RTS_M (LP_UART_SW_RTS_V << LP_UART_SW_RTS_S) +#define LP_UART_SW_RTS_V 0x00000001U +#define LP_UART_SW_RTS_S 21 +/** LP_UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0; + * Set this bit to reset the uart receive-FIFO. + */ +#define LP_UART_RXFIFO_RST (BIT(22)) +#define LP_UART_RXFIFO_RST_M (LP_UART_RXFIFO_RST_V << LP_UART_RXFIFO_RST_S) +#define LP_UART_RXFIFO_RST_V 0x00000001U +#define LP_UART_RXFIFO_RST_S 22 +/** LP_UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0; + * Set this bit to reset the uart transmit-FIFO. + */ +#define LP_UART_TXFIFO_RST (BIT(23)) +#define LP_UART_TXFIFO_RST_M (LP_UART_TXFIFO_RST_V << LP_UART_TXFIFO_RST_S) +#define LP_UART_TXFIFO_RST_V 0x00000001U +#define LP_UART_TXFIFO_RST_S 23 + +/** LP_UART_CONF1_REG register + * Configuration register 1 + */ +#define LP_UART_CONF1_REG (DR_REG_LP_UART_BASE + 0x24) +/** LP_UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:3]; default: 12; + * It will produce rxfifo_full_int interrupt when receiver receives more data than + * this register value. + */ +#define LP_UART_RXFIFO_FULL_THRHD 0x0000001FU +#define LP_UART_RXFIFO_FULL_THRHD_M (LP_UART_RXFIFO_FULL_THRHD_V << LP_UART_RXFIFO_FULL_THRHD_S) +#define LP_UART_RXFIFO_FULL_THRHD_V 0x0000001FU +#define LP_UART_RXFIFO_FULL_THRHD_S 3 +/** LP_UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:11]; default: 12; + * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less + * than this register value. + */ +#define LP_UART_TXFIFO_EMPTY_THRHD 0x0000001FU +#define LP_UART_TXFIFO_EMPTY_THRHD_M (LP_UART_TXFIFO_EMPTY_THRHD_V << LP_UART_TXFIFO_EMPTY_THRHD_S) +#define LP_UART_TXFIFO_EMPTY_THRHD_V 0x0000001FU +#define LP_UART_TXFIFO_EMPTY_THRHD_S 11 +/** LP_UART_CTS_INV : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart cts signal. + */ +#define LP_UART_CTS_INV (BIT(16)) +#define LP_UART_CTS_INV_M (LP_UART_CTS_INV_V << LP_UART_CTS_INV_S) +#define LP_UART_CTS_INV_V 0x00000001U +#define LP_UART_CTS_INV_S 16 +/** LP_UART_DSR_INV : R/W; bitpos: [17]; default: 0; + * Set this bit to inverse the level value of uart dsr signal. + */ +#define LP_UART_DSR_INV (BIT(17)) +#define LP_UART_DSR_INV_M (LP_UART_DSR_INV_V << LP_UART_DSR_INV_S) +#define LP_UART_DSR_INV_V 0x00000001U +#define LP_UART_DSR_INV_S 17 +/** LP_UART_RTS_INV : R/W; bitpos: [18]; default: 0; + * Set this bit to inverse the level value of uart rts signal. + */ +#define LP_UART_RTS_INV (BIT(18)) +#define LP_UART_RTS_INV_M (LP_UART_RTS_INV_V << LP_UART_RTS_INV_S) +#define LP_UART_RTS_INV_V 0x00000001U +#define LP_UART_RTS_INV_S 18 +/** LP_UART_DTR_INV : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of uart dtr signal. + */ +#define LP_UART_DTR_INV (BIT(19)) +#define LP_UART_DTR_INV_M (LP_UART_DTR_INV_V << LP_UART_DTR_INV_S) +#define LP_UART_DTR_INV_V 0x00000001U +#define LP_UART_DTR_INV_S 19 +/** LP_UART_SW_DTR : R/W; bitpos: [20]; default: 0; + * This register is used to configure the software dtr signal which is used in + * software flow control. + */ +#define LP_UART_SW_DTR (BIT(20)) +#define LP_UART_SW_DTR_M (LP_UART_SW_DTR_V << LP_UART_SW_DTR_S) +#define LP_UART_SW_DTR_V 0x00000001U +#define LP_UART_SW_DTR_S 20 +/** LP_UART_CLK_EN : R/W; bitpos: [21]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define LP_UART_CLK_EN (BIT(21)) +#define LP_UART_CLK_EN_M (LP_UART_CLK_EN_V << LP_UART_CLK_EN_S) +#define LP_UART_CLK_EN_V 0x00000001U +#define LP_UART_CLK_EN_S 21 + +/** LP_UART_HWFC_CONF_SYNC_REG register + * Hardware flow-control configuration + */ +#define LP_UART_HWFC_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x2c) +/** LP_UART_RX_FLOW_THRHD : R/W; bitpos: [7:3]; default: 0; + * This register is used to configure the maximum amount of data that can be received + * when hardware flow control works. + */ +#define LP_UART_RX_FLOW_THRHD 0x0000001FU +#define LP_UART_RX_FLOW_THRHD_M (LP_UART_RX_FLOW_THRHD_V << LP_UART_RX_FLOW_THRHD_S) +#define LP_UART_RX_FLOW_THRHD_V 0x0000001FU +#define LP_UART_RX_FLOW_THRHD_S 3 +/** LP_UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0; + * This is the flow enable bit for UART receiver. + */ +#define LP_UART_RX_FLOW_EN (BIT(8)) +#define LP_UART_RX_FLOW_EN_M (LP_UART_RX_FLOW_EN_V << LP_UART_RX_FLOW_EN_S) +#define LP_UART_RX_FLOW_EN_V 0x00000001U +#define LP_UART_RX_FLOW_EN_S 8 + +/** LP_UART_SLEEP_CONF0_REG register + * UART sleep configure register 0 + */ +#define LP_UART_SLEEP_CONF0_REG (DR_REG_LP_UART_BASE + 0x30) +/** LP_UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified wake up char1 to wake up + */ +#define LP_UART_WK_CHAR1 0x000000FFU +#define LP_UART_WK_CHAR1_M (LP_UART_WK_CHAR1_V << LP_UART_WK_CHAR1_S) +#define LP_UART_WK_CHAR1_V 0x000000FFU +#define LP_UART_WK_CHAR1_S 0 +/** LP_UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0; + * This register restores the specified wake up char2 to wake up + */ +#define LP_UART_WK_CHAR2 0x000000FFU +#define LP_UART_WK_CHAR2_M (LP_UART_WK_CHAR2_V << LP_UART_WK_CHAR2_S) +#define LP_UART_WK_CHAR2_V 0x000000FFU +#define LP_UART_WK_CHAR2_S 8 +/** LP_UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0; + * This register restores the specified wake up char3 to wake up + */ +#define LP_UART_WK_CHAR3 0x000000FFU +#define LP_UART_WK_CHAR3_M (LP_UART_WK_CHAR3_V << LP_UART_WK_CHAR3_S) +#define LP_UART_WK_CHAR3_V 0x000000FFU +#define LP_UART_WK_CHAR3_S 16 +/** LP_UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0; + * This register restores the specified wake up char4 to wake up + */ +#define LP_UART_WK_CHAR4 0x000000FFU +#define LP_UART_WK_CHAR4_M (LP_UART_WK_CHAR4_V << LP_UART_WK_CHAR4_S) +#define LP_UART_WK_CHAR4_V 0x000000FFU +#define LP_UART_WK_CHAR4_S 24 + +/** LP_UART_SLEEP_CONF1_REG register + * UART sleep configure register 1 + */ +#define LP_UART_SLEEP_CONF1_REG (DR_REG_LP_UART_BASE + 0x34) +/** LP_UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified char0 to wake up + */ +#define LP_UART_WK_CHAR0 0x000000FFU +#define LP_UART_WK_CHAR0_M (LP_UART_WK_CHAR0_V << LP_UART_WK_CHAR0_S) +#define LP_UART_WK_CHAR0_V 0x000000FFU +#define LP_UART_WK_CHAR0_S 0 + +/** LP_UART_SLEEP_CONF2_REG register + * UART sleep configure register 2 + */ +#define LP_UART_SLEEP_CONF2_REG (DR_REG_LP_UART_BASE + 0x38) +/** LP_UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240; + * The uart is activated from light sleeping mode when the input rxd edge changes more + * times than this register value. + */ +#define LP_UART_ACTIVE_THRESHOLD 0x000003FFU +#define LP_UART_ACTIVE_THRESHOLD_M (LP_UART_ACTIVE_THRESHOLD_V << LP_UART_ACTIVE_THRESHOLD_S) +#define LP_UART_ACTIVE_THRESHOLD_V 0x000003FFU +#define LP_UART_ACTIVE_THRESHOLD_S 0 +/** LP_UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:13]; default: 1; + * In wake up mode 1 this field is used to set the received data number threshold to + * wake up chip. + */ +#define LP_UART_RX_WAKE_UP_THRHD 0x0000001FU +#define LP_UART_RX_WAKE_UP_THRHD_M (LP_UART_RX_WAKE_UP_THRHD_V << LP_UART_RX_WAKE_UP_THRHD_S) +#define LP_UART_RX_WAKE_UP_THRHD_V 0x0000001FU +#define LP_UART_RX_WAKE_UP_THRHD_S 13 +/** LP_UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5; + * This register is used to select number of wake up char. + */ +#define LP_UART_WK_CHAR_NUM 0x00000007U +#define LP_UART_WK_CHAR_NUM_M (LP_UART_WK_CHAR_NUM_V << LP_UART_WK_CHAR_NUM_S) +#define LP_UART_WK_CHAR_NUM_V 0x00000007U +#define LP_UART_WK_CHAR_NUM_S 18 +/** LP_UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0; + * This register is used to mask wake up char. + */ +#define LP_UART_WK_CHAR_MASK 0x0000001FU +#define LP_UART_WK_CHAR_MASK_M (LP_UART_WK_CHAR_MASK_V << LP_UART_WK_CHAR_MASK_S) +#define LP_UART_WK_CHAR_MASK_V 0x0000001FU +#define LP_UART_WK_CHAR_MASK_S 21 +/** LP_UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0; + * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: + * received data number larger than + */ +#define LP_UART_WK_MODE_SEL 0x00000003U +#define LP_UART_WK_MODE_SEL_M (LP_UART_WK_MODE_SEL_V << LP_UART_WK_MODE_SEL_S) +#define LP_UART_WK_MODE_SEL_V 0x00000003U +#define LP_UART_WK_MODE_SEL_S 26 + +/** LP_UART_SWFC_CONF0_SYNC_REG register + * Software flow-control character configuration + */ +#define LP_UART_SWFC_CONF0_SYNC_REG (DR_REG_LP_UART_BASE + 0x3c) +/** LP_UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17; + * This register stores the Xon flow control char. + */ +#define LP_UART_XON_CHAR 0x000000FFU +#define LP_UART_XON_CHAR_M (LP_UART_XON_CHAR_V << LP_UART_XON_CHAR_S) +#define LP_UART_XON_CHAR_V 0x000000FFU +#define LP_UART_XON_CHAR_S 0 +/** LP_UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19; + * This register stores the Xoff flow control char. + */ +#define LP_UART_XOFF_CHAR 0x000000FFU +#define LP_UART_XOFF_CHAR_M (LP_UART_XOFF_CHAR_V << LP_UART_XOFF_CHAR_S) +#define LP_UART_XOFF_CHAR_V 0x000000FFU +#define LP_UART_XOFF_CHAR_S 8 +/** LP_UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0; + * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In + * this status, UART Tx can not transmit XOFF even the received data number is larger + * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when + * UART Tx is disabled. + */ +#define LP_UART_XON_XOFF_STILL_SEND (BIT(16)) +#define LP_UART_XON_XOFF_STILL_SEND_M (LP_UART_XON_XOFF_STILL_SEND_V << LP_UART_XON_XOFF_STILL_SEND_S) +#define LP_UART_XON_XOFF_STILL_SEND_V 0x00000001U +#define LP_UART_XON_XOFF_STILL_SEND_S 16 +/** LP_UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0; + * Set this bit to enable software flow control. It is used with register sw_xon or + * sw_xoff. + */ +#define LP_UART_SW_FLOW_CON_EN (BIT(17)) +#define LP_UART_SW_FLOW_CON_EN_M (LP_UART_SW_FLOW_CON_EN_V << LP_UART_SW_FLOW_CON_EN_S) +#define LP_UART_SW_FLOW_CON_EN_V 0x00000001U +#define LP_UART_SW_FLOW_CON_EN_S 17 +/** LP_UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0; + * Set this bit to remove flow control char from the received data. + */ +#define LP_UART_XONOFF_DEL (BIT(18)) +#define LP_UART_XONOFF_DEL_M (LP_UART_XONOFF_DEL_V << LP_UART_XONOFF_DEL_S) +#define LP_UART_XONOFF_DEL_V 0x00000001U +#define LP_UART_XONOFF_DEL_S 18 +/** LP_UART_FORCE_XON : R/W; bitpos: [19]; default: 0; + * Set this bit to enable the transmitter to go on sending data. + */ +#define LP_UART_FORCE_XON (BIT(19)) +#define LP_UART_FORCE_XON_M (LP_UART_FORCE_XON_V << LP_UART_FORCE_XON_S) +#define LP_UART_FORCE_XON_V 0x00000001U +#define LP_UART_FORCE_XON_S 19 +/** LP_UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0; + * Set this bit to stop the transmitter from sending data. + */ +#define LP_UART_FORCE_XOFF (BIT(20)) +#define LP_UART_FORCE_XOFF_M (LP_UART_FORCE_XOFF_V << LP_UART_FORCE_XOFF_S) +#define LP_UART_FORCE_XOFF_V 0x00000001U +#define LP_UART_FORCE_XOFF_S 20 +/** LP_UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0; + * Set this bit to send Xon char. It is cleared by hardware automatically. + */ +#define LP_UART_SEND_XON (BIT(21)) +#define LP_UART_SEND_XON_M (LP_UART_SEND_XON_V << LP_UART_SEND_XON_S) +#define LP_UART_SEND_XON_V 0x00000001U +#define LP_UART_SEND_XON_S 21 +/** LP_UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0; + * Set this bit to send Xoff char. It is cleared by hardware automatically. + */ +#define LP_UART_SEND_XOFF (BIT(22)) +#define LP_UART_SEND_XOFF_M (LP_UART_SEND_XOFF_V << LP_UART_SEND_XOFF_S) +#define LP_UART_SEND_XOFF_V 0x00000001U +#define LP_UART_SEND_XOFF_S 22 + +/** LP_UART_SWFC_CONF1_REG register + * Software flow-control character configuration + */ +#define LP_UART_SWFC_CONF1_REG (DR_REG_LP_UART_BASE + 0x40) +/** LP_UART_XON_THRESHOLD : R/W; bitpos: [7:3]; default: 0; + * When the data amount in Rx-FIFO is less than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xon char. + */ +#define LP_UART_XON_THRESHOLD 0x0000001FU +#define LP_UART_XON_THRESHOLD_M (LP_UART_XON_THRESHOLD_V << LP_UART_XON_THRESHOLD_S) +#define LP_UART_XON_THRESHOLD_V 0x0000001FU +#define LP_UART_XON_THRESHOLD_S 3 +/** LP_UART_XOFF_THRESHOLD : R/W; bitpos: [15:11]; default: 12; + * When the data amount in Rx-FIFO is more than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xoff char. + */ +#define LP_UART_XOFF_THRESHOLD 0x0000001FU +#define LP_UART_XOFF_THRESHOLD_M (LP_UART_XOFF_THRESHOLD_V << LP_UART_XOFF_THRESHOLD_S) +#define LP_UART_XOFF_THRESHOLD_V 0x0000001FU +#define LP_UART_XOFF_THRESHOLD_S 11 + +/** LP_UART_TXBRK_CONF_SYNC_REG register + * Tx Break character configuration + */ +#define LP_UART_TXBRK_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x44) +/** LP_UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10; + * This register is used to configure the number of 0 to be sent after the process of + * sending data is done. It is active when txd_brk is set to 1. + */ +#define LP_UART_TX_BRK_NUM 0x000000FFU +#define LP_UART_TX_BRK_NUM_M (LP_UART_TX_BRK_NUM_V << LP_UART_TX_BRK_NUM_S) +#define LP_UART_TX_BRK_NUM_V 0x000000FFU +#define LP_UART_TX_BRK_NUM_S 0 + +/** LP_UART_IDLE_CONF_SYNC_REG register + * Frame-end idle configuration + */ +#define LP_UART_IDLE_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x48) +/** LP_UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256; + * It will produce frame end signal when receiver takes more time to receive one byte + * data than this register value. + */ +#define LP_UART_RX_IDLE_THRHD 0x000003FFU +#define LP_UART_RX_IDLE_THRHD_M (LP_UART_RX_IDLE_THRHD_V << LP_UART_RX_IDLE_THRHD_S) +#define LP_UART_RX_IDLE_THRHD_V 0x000003FFU +#define LP_UART_RX_IDLE_THRHD_S 0 +/** LP_UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256; + * This register is used to configure the duration time between transfers. + */ +#define LP_UART_TX_IDLE_NUM 0x000003FFU +#define LP_UART_TX_IDLE_NUM_M (LP_UART_TX_IDLE_NUM_V << LP_UART_TX_IDLE_NUM_S) +#define LP_UART_TX_IDLE_NUM_V 0x000003FFU +#define LP_UART_TX_IDLE_NUM_S 10 + +/** LP_UART_RS485_CONF_SYNC_REG register + * RS485 mode configuration + */ +#define LP_UART_RS485_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x4c) +/** LP_UART_DL0_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ +#define LP_UART_DL0_EN (BIT(1)) +#define LP_UART_DL0_EN_M (LP_UART_DL0_EN_V << LP_UART_DL0_EN_S) +#define LP_UART_DL0_EN_V 0x00000001U +#define LP_UART_DL0_EN_S 1 +/** LP_UART_DL1_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ +#define LP_UART_DL1_EN (BIT(2)) +#define LP_UART_DL1_EN_M (LP_UART_DL1_EN_V << LP_UART_DL1_EN_S) +#define LP_UART_DL1_EN_V 0x00000001U +#define LP_UART_DL1_EN_S 2 + +/** LP_UART_AT_CMD_PRECNT_SYNC_REG register + * Pre-sequence timing configuration + */ +#define LP_UART_AT_CMD_PRECNT_SYNC_REG (DR_REG_LP_UART_BASE + 0x50) +/** LP_UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the idle duration time before the first at_cmd + * is received by receiver. + */ +#define LP_UART_PRE_IDLE_NUM 0x0000FFFFU +#define LP_UART_PRE_IDLE_NUM_M (LP_UART_PRE_IDLE_NUM_V << LP_UART_PRE_IDLE_NUM_S) +#define LP_UART_PRE_IDLE_NUM_V 0x0000FFFFU +#define LP_UART_PRE_IDLE_NUM_S 0 + +/** LP_UART_AT_CMD_POSTCNT_SYNC_REG register + * Post-sequence timing configuration + */ +#define LP_UART_AT_CMD_POSTCNT_SYNC_REG (DR_REG_LP_UART_BASE + 0x54) +/** LP_UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the duration time between the last at_cmd and + * the next data. + */ +#define LP_UART_POST_IDLE_NUM 0x0000FFFFU +#define LP_UART_POST_IDLE_NUM_M (LP_UART_POST_IDLE_NUM_V << LP_UART_POST_IDLE_NUM_S) +#define LP_UART_POST_IDLE_NUM_V 0x0000FFFFU +#define LP_UART_POST_IDLE_NUM_S 0 + +/** LP_UART_AT_CMD_GAPTOUT_SYNC_REG register + * Timeout configuration + */ +#define LP_UART_AT_CMD_GAPTOUT_SYNC_REG (DR_REG_LP_UART_BASE + 0x58) +/** LP_UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11; + * This register is used to configure the duration time between the at_cmd chars. + */ +#define LP_UART_RX_GAP_TOUT 0x0000FFFFU +#define LP_UART_RX_GAP_TOUT_M (LP_UART_RX_GAP_TOUT_V << LP_UART_RX_GAP_TOUT_S) +#define LP_UART_RX_GAP_TOUT_V 0x0000FFFFU +#define LP_UART_RX_GAP_TOUT_S 0 + +/** LP_UART_AT_CMD_CHAR_SYNC_REG register + * AT escape sequence detection configuration + */ +#define LP_UART_AT_CMD_CHAR_SYNC_REG (DR_REG_LP_UART_BASE + 0x5c) +/** LP_UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43; + * This register is used to configure the content of at_cmd char. + */ +#define LP_UART_AT_CMD_CHAR 0x000000FFU +#define LP_UART_AT_CMD_CHAR_M (LP_UART_AT_CMD_CHAR_V << LP_UART_AT_CMD_CHAR_S) +#define LP_UART_AT_CMD_CHAR_V 0x000000FFU +#define LP_UART_AT_CMD_CHAR_S 0 +/** LP_UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3; + * This register is used to configure the num of continuous at_cmd chars received by + * receiver. + */ +#define LP_UART_CHAR_NUM 0x000000FFU +#define LP_UART_CHAR_NUM_M (LP_UART_CHAR_NUM_V << LP_UART_CHAR_NUM_S) +#define LP_UART_CHAR_NUM_V 0x000000FFU +#define LP_UART_CHAR_NUM_S 8 + +/** LP_UART_MEM_CONF_REG register + * UART memory power configuration + */ +#define LP_UART_MEM_CONF_REG (DR_REG_LP_UART_BASE + 0x60) +/** LP_UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0; + * Set this bit to force power down UART memory. + */ +#define LP_UART_MEM_FORCE_PD (BIT(25)) +#define LP_UART_MEM_FORCE_PD_M (LP_UART_MEM_FORCE_PD_V << LP_UART_MEM_FORCE_PD_S) +#define LP_UART_MEM_FORCE_PD_V 0x00000001U +#define LP_UART_MEM_FORCE_PD_S 25 +/** LP_UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0; + * Set this bit to force power up UART memory. + */ +#define LP_UART_MEM_FORCE_PU (BIT(26)) +#define LP_UART_MEM_FORCE_PU_M (LP_UART_MEM_FORCE_PU_V << LP_UART_MEM_FORCE_PU_S) +#define LP_UART_MEM_FORCE_PU_V 0x00000001U +#define LP_UART_MEM_FORCE_PU_S 26 + +/** LP_UART_TOUT_CONF_SYNC_REG register + * UART threshold and allocation configuration + */ +#define LP_UART_TOUT_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x64) +/** LP_UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; + * This is the enble bit for uart receiver's timeout function. + */ +#define LP_UART_RX_TOUT_EN (BIT(0)) +#define LP_UART_RX_TOUT_EN_M (LP_UART_RX_TOUT_EN_V << LP_UART_RX_TOUT_EN_S) +#define LP_UART_RX_TOUT_EN_V 0x00000001U +#define LP_UART_RX_TOUT_EN_S 0 +/** LP_UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control works. + */ +#define LP_UART_RX_TOUT_FLOW_DIS (BIT(1)) +#define LP_UART_RX_TOUT_FLOW_DIS_M (LP_UART_RX_TOUT_FLOW_DIS_V << LP_UART_RX_TOUT_FLOW_DIS_S) +#define LP_UART_RX_TOUT_FLOW_DIS_V 0x00000001U +#define LP_UART_RX_TOUT_FLOW_DIS_S 1 +/** LP_UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10; + * This register is used to configure the threshold time that receiver takes to + * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver + * takes more time to receive one byte with rx_tout_en set to 1. + */ +#define LP_UART_RX_TOUT_THRHD 0x000003FFU +#define LP_UART_RX_TOUT_THRHD_M (LP_UART_RX_TOUT_THRHD_V << LP_UART_RX_TOUT_THRHD_S) +#define LP_UART_RX_TOUT_THRHD_V 0x000003FFU +#define LP_UART_RX_TOUT_THRHD_S 2 + +/** LP_UART_MEM_TX_STATUS_REG register + * Tx-SRAM write and read offset address. + */ +#define LP_UART_MEM_TX_STATUS_REG (DR_REG_LP_UART_BASE + 0x68) +/** LP_UART_TX_SRAM_WADDR : RO; bitpos: [7:3]; default: 0; + * This register stores the offset write address in Tx-SRAM. + */ +#define LP_UART_TX_SRAM_WADDR 0x0000001FU +#define LP_UART_TX_SRAM_WADDR_M (LP_UART_TX_SRAM_WADDR_V << LP_UART_TX_SRAM_WADDR_S) +#define LP_UART_TX_SRAM_WADDR_V 0x0000001FU +#define LP_UART_TX_SRAM_WADDR_S 3 +/** LP_UART_TX_SRAM_RADDR : RO; bitpos: [16:12]; default: 0; + * This register stores the offset read address in Tx-SRAM. + */ +#define LP_UART_TX_SRAM_RADDR 0x0000001FU +#define LP_UART_TX_SRAM_RADDR_M (LP_UART_TX_SRAM_RADDR_V << LP_UART_TX_SRAM_RADDR_S) +#define LP_UART_TX_SRAM_RADDR_V 0x0000001FU +#define LP_UART_TX_SRAM_RADDR_S 12 + +/** LP_UART_MEM_RX_STATUS_REG register + * Rx-SRAM write and read offset address. + */ +#define LP_UART_MEM_RX_STATUS_REG (DR_REG_LP_UART_BASE + 0x6c) +/** LP_UART_RX_SRAM_RADDR : RO; bitpos: [7:3]; default: 16; + * This register stores the offset read address in RX-SRAM. + */ +#define LP_UART_RX_SRAM_RADDR 0x0000001FU +#define LP_UART_RX_SRAM_RADDR_M (LP_UART_RX_SRAM_RADDR_V << LP_UART_RX_SRAM_RADDR_S) +#define LP_UART_RX_SRAM_RADDR_V 0x0000001FU +#define LP_UART_RX_SRAM_RADDR_S 3 +/** LP_UART_RX_SRAM_WADDR : RO; bitpos: [16:12]; default: 16; + * This register stores the offset write address in Rx-SRAM. + */ +#define LP_UART_RX_SRAM_WADDR 0x0000001FU +#define LP_UART_RX_SRAM_WADDR_M (LP_UART_RX_SRAM_WADDR_V << LP_UART_RX_SRAM_WADDR_S) +#define LP_UART_RX_SRAM_WADDR_V 0x0000001FU +#define LP_UART_RX_SRAM_WADDR_S 12 + +/** LP_UART_FSM_STATUS_REG register + * UART transmit and receive status. + */ +#define LP_UART_FSM_STATUS_REG (DR_REG_LP_UART_BASE + 0x70) +/** LP_UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0; + * This is the status register of receiver. + */ +#define LP_UART_ST_URX_OUT 0x0000000FU +#define LP_UART_ST_URX_OUT_M (LP_UART_ST_URX_OUT_V << LP_UART_ST_URX_OUT_S) +#define LP_UART_ST_URX_OUT_V 0x0000000FU +#define LP_UART_ST_URX_OUT_S 0 +/** LP_UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0; + * This is the status register of transmitter. + */ +#define LP_UART_ST_UTX_OUT 0x0000000FU +#define LP_UART_ST_UTX_OUT_M (LP_UART_ST_UTX_OUT_V << LP_UART_ST_UTX_OUT_S) +#define LP_UART_ST_UTX_OUT_V 0x0000000FU +#define LP_UART_ST_UTX_OUT_S 4 + +/** LP_UART_CLK_CONF_REG register + * UART core clock configuration + */ +#define LP_UART_CLK_CONF_REG (DR_REG_LP_UART_BASE + 0x88) +/** LP_UART_SCLK_DIV_B : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor. + */ +#define LP_UART_SCLK_DIV_B 0x0000003FU +#define LP_UART_SCLK_DIV_B_M (LP_UART_SCLK_DIV_B_V << LP_UART_SCLK_DIV_B_S) +#define LP_UART_SCLK_DIV_B_V 0x0000003FU +#define LP_UART_SCLK_DIV_B_S 0 +/** LP_UART_SCLK_DIV_A : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor. + */ +#define LP_UART_SCLK_DIV_A 0x0000003FU +#define LP_UART_SCLK_DIV_A_M (LP_UART_SCLK_DIV_A_V << LP_UART_SCLK_DIV_A_S) +#define LP_UART_SCLK_DIV_A_V 0x0000003FU +#define LP_UART_SCLK_DIV_A_S 6 +/** LP_UART_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1; + * The integral part of the frequency divider factor. + */ +#define LP_UART_SCLK_DIV_NUM 0x000000FFU +#define LP_UART_SCLK_DIV_NUM_M (LP_UART_SCLK_DIV_NUM_V << LP_UART_SCLK_DIV_NUM_S) +#define LP_UART_SCLK_DIV_NUM_V 0x000000FFU +#define LP_UART_SCLK_DIV_NUM_S 12 +/** LP_UART_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; + * UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL. + */ +#define LP_UART_SCLK_SEL 0x00000003U +#define LP_UART_SCLK_SEL_M (LP_UART_SCLK_SEL_V << LP_UART_SCLK_SEL_S) +#define LP_UART_SCLK_SEL_V 0x00000003U +#define LP_UART_SCLK_SEL_S 20 +/** LP_UART_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set this bit to enable UART Tx/Rx clock. + */ +#define LP_UART_SCLK_EN (BIT(22)) +#define LP_UART_SCLK_EN_M (LP_UART_SCLK_EN_V << LP_UART_SCLK_EN_S) +#define LP_UART_SCLK_EN_V 0x00000001U +#define LP_UART_SCLK_EN_S 22 +/** LP_UART_RST_CORE : R/W; bitpos: [23]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx/Rx. + */ +#define LP_UART_RST_CORE (BIT(23)) +#define LP_UART_RST_CORE_M (LP_UART_RST_CORE_V << LP_UART_RST_CORE_S) +#define LP_UART_RST_CORE_V 0x00000001U +#define LP_UART_RST_CORE_S 23 +/** LP_UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; + * Set this bit to enable UART Tx clock. + */ +#define LP_UART_TX_SCLK_EN (BIT(24)) +#define LP_UART_TX_SCLK_EN_M (LP_UART_TX_SCLK_EN_V << LP_UART_TX_SCLK_EN_S) +#define LP_UART_TX_SCLK_EN_V 0x00000001U +#define LP_UART_TX_SCLK_EN_S 24 +/** LP_UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1; + * Set this bit to enable UART Rx clock. + */ +#define LP_UART_RX_SCLK_EN (BIT(25)) +#define LP_UART_RX_SCLK_EN_M (LP_UART_RX_SCLK_EN_V << LP_UART_RX_SCLK_EN_S) +#define LP_UART_RX_SCLK_EN_V 0x00000001U +#define LP_UART_RX_SCLK_EN_S 25 +/** LP_UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx. + */ +#define LP_UART_TX_RST_CORE (BIT(26)) +#define LP_UART_TX_RST_CORE_M (LP_UART_TX_RST_CORE_V << LP_UART_TX_RST_CORE_S) +#define LP_UART_TX_RST_CORE_V 0x00000001U +#define LP_UART_TX_RST_CORE_S 26 +/** LP_UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0; + * Write 1 then write 0 to this bit to reset UART Rx. + */ +#define LP_UART_RX_RST_CORE (BIT(27)) +#define LP_UART_RX_RST_CORE_M (LP_UART_RX_RST_CORE_V << LP_UART_RX_RST_CORE_S) +#define LP_UART_RX_RST_CORE_V 0x00000001U +#define LP_UART_RX_RST_CORE_S 27 + +/** LP_UART_DATE_REG register + * UART Version register + */ +#define LP_UART_DATE_REG (DR_REG_LP_UART_BASE + 0x8c) +/** LP_UART_DATE : R/W; bitpos: [31:0]; default: 35656288; + * This is the version register. + */ +#define LP_UART_DATE 0xFFFFFFFFU +#define LP_UART_DATE_M (LP_UART_DATE_V << LP_UART_DATE_S) +#define LP_UART_DATE_V 0xFFFFFFFFU +#define LP_UART_DATE_S 0 + +/** LP_UART_AFIFO_STATUS_REG register + * UART AFIFO Status + */ +#define LP_UART_AFIFO_STATUS_REG (DR_REG_LP_UART_BASE + 0x90) +/** LP_UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0; + * Full signal of APB TX AFIFO. + */ +#define LP_UART_TX_AFIFO_FULL (BIT(0)) +#define LP_UART_TX_AFIFO_FULL_M (LP_UART_TX_AFIFO_FULL_V << LP_UART_TX_AFIFO_FULL_S) +#define LP_UART_TX_AFIFO_FULL_V 0x00000001U +#define LP_UART_TX_AFIFO_FULL_S 0 +/** LP_UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1; + * Empty signal of APB TX AFIFO. + */ +#define LP_UART_TX_AFIFO_EMPTY (BIT(1)) +#define LP_UART_TX_AFIFO_EMPTY_M (LP_UART_TX_AFIFO_EMPTY_V << LP_UART_TX_AFIFO_EMPTY_S) +#define LP_UART_TX_AFIFO_EMPTY_V 0x00000001U +#define LP_UART_TX_AFIFO_EMPTY_S 1 +/** LP_UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0; + * Full signal of APB RX AFIFO. + */ +#define LP_UART_RX_AFIFO_FULL (BIT(2)) +#define LP_UART_RX_AFIFO_FULL_M (LP_UART_RX_AFIFO_FULL_V << LP_UART_RX_AFIFO_FULL_S) +#define LP_UART_RX_AFIFO_FULL_V 0x00000001U +#define LP_UART_RX_AFIFO_FULL_S 2 +/** LP_UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1; + * Empty signal of APB RX AFIFO. + */ +#define LP_UART_RX_AFIFO_EMPTY (BIT(3)) +#define LP_UART_RX_AFIFO_EMPTY_M (LP_UART_RX_AFIFO_EMPTY_V << LP_UART_RX_AFIFO_EMPTY_S) +#define LP_UART_RX_AFIFO_EMPTY_V 0x00000001U +#define LP_UART_RX_AFIFO_EMPTY_S 3 + +/** LP_UART_REG_UPDATE_REG register + * UART Registers Configuration Update register + */ +#define LP_UART_REG_UPDATE_REG (DR_REG_LP_UART_BASE + 0x98) +/** LP_UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0; + * Software write 1 would synchronize registers into UART Core clock domain and would + * be cleared by hardware after synchronization is done. + */ +#define LP_UART_REG_UPDATE (BIT(0)) +#define LP_UART_REG_UPDATE_M (LP_UART_REG_UPDATE_V << LP_UART_REG_UPDATE_S) +#define LP_UART_REG_UPDATE_V 0x00000001U +#define LP_UART_REG_UPDATE_S 0 + +/** LP_UART_ID_REG register + * UART ID register + */ +#define LP_UART_ID_REG (DR_REG_LP_UART_BASE + 0x9c) +/** LP_UART_ID : R/W; bitpos: [31:0]; default: 1280; + * This register is used to configure the uart_id. + */ +#define LP_UART_ID 0xFFFFFFFFU +#define LP_UART_ID_M (LP_UART_ID_V << LP_UART_ID_S) +#define LP_UART_ID_V 0xFFFFFFFFU +#define LP_UART_ID_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_uart_struct.h b/components/soc/esp32c6/include/soc/lp_uart_struct.h new file mode 100644 index 0000000000..dfe2da6e3e --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_uart_struct.h @@ -0,0 +1,1127 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: FIFO Configuration */ +/** Type of fifo register + * FIFO data register + */ +typedef union { + struct { + /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0; + * UART $n accesses FIFO via this register. + */ + uint32_t rxfifo_rd_byte:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_uart_fifo_reg_t; + +/** Type of mem_conf register + * UART memory power configuration + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** mem_force_pd : R/W; bitpos: [25]; default: 0; + * Set this bit to force power down UART memory. + */ + uint32_t mem_force_pd:1; + /** mem_force_pu : R/W; bitpos: [26]; default: 0; + * Set this bit to force power up UART memory. + */ + uint32_t mem_force_pu:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} lp_uart_mem_conf_reg_t; + +/** Type of tout_conf_sync register + * UART threshold and allocation configuration + */ +typedef union { + struct { + /** rx_tout_en : R/W; bitpos: [0]; default: 0; + * This is the enble bit for uart receiver's timeout function. + */ + uint32_t rx_tout_en:1; + /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control works. + */ + uint32_t rx_tout_flow_dis:1; + /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10; + * This register is used to configure the threshold time that receiver takes to + * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver + * takes more time to receive one byte with rx_tout_en set to 1. + */ + uint32_t rx_tout_thrhd:10; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_uart_tout_conf_sync_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * what rxfifo_full_thrhd specifies. + */ + uint32_t rxfifo_full_int_raw:1; + /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1; + * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is + * less than what txfifo_empty_thrhd specifies . + */ + uint32_t txfifo_empty_int_raw:1; + /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error in + * the data. + */ + uint32_t parity_err_int_raw:1; + /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * . + */ + uint32_t frm_err_int_raw:1; + /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * the FIFO can store. + */ + uint32_t rxfifo_ovf_int_raw:1; + /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * DSRn signal. + */ + uint32_t dsr_chg_int_raw:1; + /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * CTSn signal. + */ + uint32_t cts_chg_int_raw:1; + /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 after the stop + * bit. + */ + uint32_t brk_det_int_raw:1; + /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more time than + * rx_tout_thrhd to receive a byte. + */ + uint32_t rxfifo_tout_int_raw:1; + /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver recevies Xon char when + * uart_sw_flow_con_en is set to 1. + */ + uint32_t sw_xon_int_raw:1; + /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xoff char when + * uart_sw_flow_con_en is set to 1. + */ + uint32_t sw_xoff_int_raw:1; + /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a glitch in the + * middle of a start bit. + */ + uint32_t glitch_det_int_raw:1; + /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes sending + * NULL characters after all data in Tx-FIFO are sent. + */ + uint32_t tx_brk_done_int_raw:1; + /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept the shortest + * duration after sending the last data. + */ + uint32_t tx_brk_idle_done_int_raw:1; + /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has send out all data + * in FIFO. + */ + uint32_t tx_done_int_raw:1; + uint32_t reserved_15:3; + /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the configured + * at_cmd char. + */ + uint32_t at_cmd_char_det_int_raw:1; + /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes more times + * than what reg_active_threshold specifies in light sleeping mode. + */ + uint32_t wakeup_int_raw:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} lp_uart_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0; + * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + */ + uint32_t rxfifo_full_int_st:1; + /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0; + * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set + * to 1. + */ + uint32_t txfifo_empty_int_st:1; + /** parity_err_int_st : RO; bitpos: [2]; default: 0; + * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + */ + uint32_t parity_err_int_st:1; + /** frm_err_int_st : RO; bitpos: [3]; default: 0; + * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + */ + uint32_t frm_err_int_st:1; + /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0; + * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + */ + uint32_t rxfifo_ovf_int_st:1; + /** dsr_chg_int_st : RO; bitpos: [5]; default: 0; + * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + */ + uint32_t dsr_chg_int_st:1; + /** cts_chg_int_st : RO; bitpos: [6]; default: 0; + * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + */ + uint32_t cts_chg_int_st:1; + /** brk_det_int_st : RO; bitpos: [7]; default: 0; + * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + */ + uint32_t brk_det_int_st:1; + /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0; + * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + */ + uint32_t rxfifo_tout_int_st:1; + /** sw_xon_int_st : RO; bitpos: [9]; default: 0; + * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + */ + uint32_t sw_xon_int_st:1; + /** sw_xoff_int_st : RO; bitpos: [10]; default: 0; + * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + */ + uint32_t sw_xoff_int_st:1; + /** glitch_det_int_st : RO; bitpos: [11]; default: 0; + * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + */ + uint32_t glitch_det_int_st:1; + /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0; + * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + */ + uint32_t tx_brk_done_int_st:1; + /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0; + * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * is set to 1. + */ + uint32_t tx_brk_idle_done_int_st:1; + /** tx_done_int_st : RO; bitpos: [14]; default: 0; + * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + */ + uint32_t tx_done_int_st:1; + uint32_t reserved_15:3; + /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0; + * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set + * to 1. + */ + uint32_t at_cmd_char_det_int_st:1; + /** wakeup_int_st : RO; bitpos: [19]; default: 0; + * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + */ + uint32_t wakeup_int_st:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} lp_uart_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0; + * This is the enable bit for rxfifo_full_int_st register. + */ + uint32_t rxfifo_full_int_ena:1; + /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0; + * This is the enable bit for txfifo_empty_int_st register. + */ + uint32_t txfifo_empty_int_ena:1; + /** parity_err_int_ena : R/W; bitpos: [2]; default: 0; + * This is the enable bit for parity_err_int_st register. + */ + uint32_t parity_err_int_ena:1; + /** frm_err_int_ena : R/W; bitpos: [3]; default: 0; + * This is the enable bit for frm_err_int_st register. + */ + uint32_t frm_err_int_ena:1; + /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0; + * This is the enable bit for rxfifo_ovf_int_st register. + */ + uint32_t rxfifo_ovf_int_ena:1; + /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0; + * This is the enable bit for dsr_chg_int_st register. + */ + uint32_t dsr_chg_int_ena:1; + /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0; + * This is the enable bit for cts_chg_int_st register. + */ + uint32_t cts_chg_int_ena:1; + /** brk_det_int_ena : R/W; bitpos: [7]; default: 0; + * This is the enable bit for brk_det_int_st register. + */ + uint32_t brk_det_int_ena:1; + /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0; + * This is the enable bit for rxfifo_tout_int_st register. + */ + uint32_t rxfifo_tout_int_ena:1; + /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0; + * This is the enable bit for sw_xon_int_st register. + */ + uint32_t sw_xon_int_ena:1; + /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0; + * This is the enable bit for sw_xoff_int_st register. + */ + uint32_t sw_xoff_int_ena:1; + /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0; + * This is the enable bit for glitch_det_int_st register. + */ + uint32_t glitch_det_int_ena:1; + /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0; + * This is the enable bit for tx_brk_done_int_st register. + */ + uint32_t tx_brk_done_int_ena:1; + /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0; + * This is the enable bit for tx_brk_idle_done_int_st register. + */ + uint32_t tx_brk_idle_done_int_ena:1; + /** tx_done_int_ena : R/W; bitpos: [14]; default: 0; + * This is the enable bit for tx_done_int_st register. + */ + uint32_t tx_done_int_ena:1; + uint32_t reserved_15:3; + /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0; + * This is the enable bit for at_cmd_char_det_int_st register. + */ + uint32_t at_cmd_char_det_int_ena:1; + /** wakeup_int_ena : R/W; bitpos: [19]; default: 0; + * This is the enable bit for uart_wakeup_int_st register. + */ + uint32_t wakeup_int_ena:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} lp_uart_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the rxfifo_full_int_raw interrupt. + */ + uint32_t rxfifo_full_int_clr:1; + /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear txfifo_empty_int_raw interrupt. + */ + uint32_t txfifo_empty_int_clr:1; + /** parity_err_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear parity_err_int_raw interrupt. + */ + uint32_t parity_err_int_clr:1; + /** frm_err_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear frm_err_int_raw interrupt. + */ + uint32_t frm_err_int_clr:1; + /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear rxfifo_ovf_int_raw interrupt. + */ + uint32_t rxfifo_ovf_int_clr:1; + /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the dsr_chg_int_raw interrupt. + */ + uint32_t dsr_chg_int_clr:1; + /** cts_chg_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the cts_chg_int_raw interrupt. + */ + uint32_t cts_chg_int_clr:1; + /** brk_det_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the brk_det_int_raw interrupt. + */ + uint32_t brk_det_int_clr:1; + /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the rxfifo_tout_int_raw interrupt. + */ + uint32_t rxfifo_tout_int_clr:1; + /** sw_xon_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the sw_xon_int_raw interrupt. + */ + uint32_t sw_xon_int_clr:1; + /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear the sw_xoff_int_raw interrupt. + */ + uint32_t sw_xoff_int_clr:1; + /** glitch_det_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the glitch_det_int_raw interrupt. + */ + uint32_t glitch_det_int_clr:1; + /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear the tx_brk_done_int_raw interrupt.. + */ + uint32_t tx_brk_done_int_clr:1; + /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + */ + uint32_t tx_brk_idle_done_int_clr:1; + /** tx_done_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear the tx_done_int_raw interrupt. + */ + uint32_t tx_done_int_clr:1; + uint32_t reserved_15:3; + /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear the at_cmd_char_det_int_raw interrupt. + */ + uint32_t at_cmd_char_det_int_clr:1; + /** wakeup_int_clr : WT; bitpos: [19]; default: 0; + * Set this bit to clear the uart_wakeup_int_raw interrupt. + */ + uint32_t wakeup_int_clr:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} lp_uart_int_clr_reg_t; + + +/** Group: Configuration Register */ +/** Type of clkdiv_sync register + * Clock divider configuration + */ +typedef union { + struct { + /** clkdiv : R/W; bitpos: [11:0]; default: 694; + * The integral part of the frequency divider factor. + */ + uint32_t clkdiv:12; + uint32_t reserved_12:8; + /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0; + * The decimal part of the frequency divider factor. + */ + uint32_t clkdiv_frag:4; + uint32_t reserved_24:8; + }; + uint32_t val; +} lp_uart_clkdiv_sync_reg_t; + +/** Type of rx_filt register + * Rx Filter configuration + */ +typedef union { + struct { + /** glitch_filt : R/W; bitpos: [7:0]; default: 8; + * when input pulse width is lower than this value the pulse is ignored. + */ + uint32_t glitch_filt:8; + /** glitch_filt_en : R/W; bitpos: [8]; default: 0; + * Set this bit to enable Rx signal filter. + */ + uint32_t glitch_filt_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_uart_rx_filt_reg_t; + +/** Type of conf0_sync register + * Configuration register 0 + */ +typedef union { + struct { + /** parity : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check mode. + */ + uint32_t parity:1; + /** parity_en : R/W; bitpos: [1]; default: 0; + * Set this bit to enable uart parity check. + */ + uint32_t parity_en:1; + /** bit_num : R/W; bitpos: [3:2]; default: 3; + * This register is used to set the length of data. + */ + uint32_t bit_num:2; + /** stop_bit_num : R/W; bitpos: [5:4]; default: 1; + * This register is used to set the length of stop bit. + */ + uint32_t stop_bit_num:2; + /** txd_brk : R/W; bitpos: [6]; default: 0; + * Set this bit to enbale transmitter to send NULL when the process of sending data + * is done. + */ + uint32_t txd_brk:1; + uint32_t reserved_7:5; + /** loopback : R/W; bitpos: [12]; default: 0; + * Set this bit to enable uart loopback test mode. + */ + uint32_t loopback:1; + /** tx_flow_en : R/W; bitpos: [13]; default: 0; + * Set this bit to enable flow control function for transmitter. + */ + uint32_t tx_flow_en:1; + uint32_t reserved_14:1; + /** rxd_inv : R/W; bitpos: [15]; default: 0; + * Set this bit to inverse the level value of uart rxd signal. + */ + uint32_t rxd_inv:1; + /** txd_inv : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart txd signal. + */ + uint32_t txd_inv:1; + /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0; + * Disable UART Rx data overflow detect. + */ + uint32_t dis_rx_dat_ovf:1; + /** err_wr_mask : R/W; bitpos: [18]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver + * stores the data even if the received data is wrong. + */ + uint32_t err_wr_mask:1; + uint32_t reserved_19:1; + /** mem_clk_en : R/W; bitpos: [20]; default: 1; + * UART memory clock gate enable signal. + */ + uint32_t mem_clk_en:1; + /** sw_rts : R/W; bitpos: [21]; default: 0; + * This register is used to configure the software rts signal which is used in + * software flow control. + */ + uint32_t sw_rts:1; + /** rxfifo_rst : R/W; bitpos: [22]; default: 0; + * Set this bit to reset the uart receive-FIFO. + */ + uint32_t rxfifo_rst:1; + /** txfifo_rst : R/W; bitpos: [23]; default: 0; + * Set this bit to reset the uart transmit-FIFO. + */ + uint32_t txfifo_rst:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} lp_uart_conf0_sync_reg_t; + +/** Type of conf1 register + * Configuration register 1 + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** rxfifo_full_thrhd : R/W; bitpos: [7:3]; default: 12; + * It will produce rxfifo_full_int interrupt when receiver receives more data than + * this register value. + */ + uint32_t rxfifo_full_thrhd:5; + uint32_t reserved_8:3; + /** txfifo_empty_thrhd : R/W; bitpos: [15:11]; default: 12; + * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less + * than this register value. + */ + uint32_t txfifo_empty_thrhd:5; + /** cts_inv : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart cts signal. + */ + uint32_t cts_inv:1; + /** dsr_inv : R/W; bitpos: [17]; default: 0; + * Set this bit to inverse the level value of uart dsr signal. + */ + uint32_t dsr_inv:1; + /** rts_inv : R/W; bitpos: [18]; default: 0; + * Set this bit to inverse the level value of uart rts signal. + */ + uint32_t rts_inv:1; + /** dtr_inv : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of uart dtr signal. + */ + uint32_t dtr_inv:1; + /** sw_dtr : R/W; bitpos: [20]; default: 0; + * This register is used to configure the software dtr signal which is used in + * software flow control. + */ + uint32_t sw_dtr:1; + /** clk_en : R/W; bitpos: [21]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} lp_uart_conf1_reg_t; + +/** Type of hwfc_conf_sync register + * Hardware flow-control configuration + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** rx_flow_thrhd : R/W; bitpos: [7:3]; default: 0; + * This register is used to configure the maximum amount of data that can be received + * when hardware flow control works. + */ + uint32_t rx_flow_thrhd:5; + /** rx_flow_en : R/W; bitpos: [8]; default: 0; + * This is the flow enable bit for UART receiver. + */ + uint32_t rx_flow_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_uart_hwfc_conf_sync_reg_t; + +/** Type of sleep_conf0 register + * UART sleep configure register 0 + */ +typedef union { + struct { + /** wk_char1 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified wake up char1 to wake up + */ + uint32_t wk_char1:8; + /** wk_char2 : R/W; bitpos: [15:8]; default: 0; + * This register restores the specified wake up char2 to wake up + */ + uint32_t wk_char2:8; + /** wk_char3 : R/W; bitpos: [23:16]; default: 0; + * This register restores the specified wake up char3 to wake up + */ + uint32_t wk_char3:8; + /** wk_char4 : R/W; bitpos: [31:24]; default: 0; + * This register restores the specified wake up char4 to wake up + */ + uint32_t wk_char4:8; + }; + uint32_t val; +} lp_uart_sleep_conf0_reg_t; + +/** Type of sleep_conf1 register + * UART sleep configure register 1 + */ +typedef union { + struct { + /** wk_char0 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified char0 to wake up + */ + uint32_t wk_char0:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_uart_sleep_conf1_reg_t; + +/** Type of sleep_conf2 register + * UART sleep configure register 2 + */ +typedef union { + struct { + /** active_threshold : R/W; bitpos: [9:0]; default: 240; + * The uart is activated from light sleeping mode when the input rxd edge changes more + * times than this register value. + */ + uint32_t active_threshold:10; + uint32_t reserved_10:3; + /** rx_wake_up_thrhd : R/W; bitpos: [17:13]; default: 1; + * In wake up mode 1 this field is used to set the received data number threshold to + * wake up chip. + */ + uint32_t rx_wake_up_thrhd:5; + /** wk_char_num : R/W; bitpos: [20:18]; default: 5; + * This register is used to select number of wake up char. + */ + uint32_t wk_char_num:3; + /** wk_char_mask : R/W; bitpos: [25:21]; default: 0; + * This register is used to mask wake up char. + */ + uint32_t wk_char_mask:5; + /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0; + * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: + * received data number larger than + */ + uint32_t wk_mode_sel:2; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_uart_sleep_conf2_reg_t; + +/** Type of swfc_conf0_sync register + * Software flow-control character configuration + */ +typedef union { + struct { + /** xon_char : R/W; bitpos: [7:0]; default: 17; + * This register stores the Xon flow control char. + */ + uint32_t xon_char:8; + /** xoff_char : R/W; bitpos: [15:8]; default: 19; + * This register stores the Xoff flow control char. + */ + uint32_t xoff_char:8; + /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0; + * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In + * this status, UART Tx can not transmit XOFF even the received data number is larger + * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when + * UART Tx is disabled. + */ + uint32_t xon_xoff_still_send:1; + /** sw_flow_con_en : R/W; bitpos: [17]; default: 0; + * Set this bit to enable software flow control. It is used with register sw_xon or + * sw_xoff. + */ + uint32_t sw_flow_con_en:1; + /** xonoff_del : R/W; bitpos: [18]; default: 0; + * Set this bit to remove flow control char from the received data. + */ + uint32_t xonoff_del:1; + /** force_xon : R/W; bitpos: [19]; default: 0; + * Set this bit to enable the transmitter to go on sending data. + */ + uint32_t force_xon:1; + /** force_xoff : R/W; bitpos: [20]; default: 0; + * Set this bit to stop the transmitter from sending data. + */ + uint32_t force_xoff:1; + /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0; + * Set this bit to send Xon char. It is cleared by hardware automatically. + */ + uint32_t send_xon:1; + /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0; + * Set this bit to send Xoff char. It is cleared by hardware automatically. + */ + uint32_t send_xoff:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} lp_uart_swfc_conf0_sync_reg_t; + +/** Type of swfc_conf1 register + * Software flow-control character configuration + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** xon_threshold : R/W; bitpos: [7:3]; default: 0; + * When the data amount in Rx-FIFO is less than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xon char. + */ + uint32_t xon_threshold:5; + uint32_t reserved_8:3; + /** xoff_threshold : R/W; bitpos: [15:11]; default: 12; + * When the data amount in Rx-FIFO is more than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xoff char. + */ + uint32_t xoff_threshold:5; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_uart_swfc_conf1_reg_t; + +/** Type of txbrk_conf_sync register + * Tx Break character configuration + */ +typedef union { + struct { + /** tx_brk_num : R/W; bitpos: [7:0]; default: 10; + * This register is used to configure the number of 0 to be sent after the process of + * sending data is done. It is active when txd_brk is set to 1. + */ + uint32_t tx_brk_num:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_uart_txbrk_conf_sync_reg_t; + +/** Type of idle_conf_sync register + * Frame-end idle configuration + */ +typedef union { + struct { + /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256; + * It will produce frame end signal when receiver takes more time to receive one byte + * data than this register value. + */ + uint32_t rx_idle_thrhd:10; + /** tx_idle_num : R/W; bitpos: [19:10]; default: 256; + * This register is used to configure the duration time between transfers. + */ + uint32_t tx_idle_num:10; + uint32_t reserved_20:12; + }; + uint32_t val; +} lp_uart_idle_conf_sync_reg_t; + +/** Type of rs485_conf_sync register + * RS485 mode configuration + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** dl0_en : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + uint32_t dl0_en:1; + /** dl1_en : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + uint32_t dl1_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} lp_uart_rs485_conf_sync_reg_t; + +/** Type of clk_conf register + * UART core clock configuration + */ +typedef union { + struct { + /** sclk_div_b : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor. + */ + uint32_t sclk_div_b:6; + /** sclk_div_a : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor. + */ + uint32_t sclk_div_a:6; + /** sclk_div_num : R/W; bitpos: [19:12]; default: 1; + * The integral part of the frequency divider factor. + */ + uint32_t sclk_div_num:8; + /** sclk_sel : R/W; bitpos: [21:20]; default: 3; + * UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL. + */ + uint32_t sclk_sel:2; + /** sclk_en : R/W; bitpos: [22]; default: 1; + * Set this bit to enable UART Tx/Rx clock. + */ + uint32_t sclk_en:1; + /** rst_core : R/W; bitpos: [23]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx/Rx. + */ + uint32_t rst_core:1; + /** tx_sclk_en : R/W; bitpos: [24]; default: 1; + * Set this bit to enable UART Tx clock. + */ + uint32_t tx_sclk_en:1; + /** rx_sclk_en : R/W; bitpos: [25]; default: 1; + * Set this bit to enable UART Rx clock. + */ + uint32_t rx_sclk_en:1; + /** tx_rst_core : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx. + */ + uint32_t tx_rst_core:1; + /** rx_rst_core : R/W; bitpos: [27]; default: 0; + * Write 1 then write 0 to this bit to reset UART Rx. + */ + uint32_t rx_rst_core:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_uart_clk_conf_reg_t; + + +/** Group: Status Register */ +/** Type of status register + * UART status register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** rxfifo_cnt : RO; bitpos: [7:3]; default: 0; + * Stores the byte number of valid data in Rx-FIFO. + */ + uint32_t rxfifo_cnt:5; + uint32_t reserved_8:5; + /** dsrn : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal uart dsr signal. + */ + uint32_t dsrn:1; + /** ctsn : RO; bitpos: [14]; default: 1; + * This register represent the level value of the internal uart cts signal. + */ + uint32_t ctsn:1; + /** rxd : RO; bitpos: [15]; default: 1; + * This register represent the level value of the internal uart rxd signal. + */ + uint32_t rxd:1; + uint32_t reserved_16:3; + /** txfifo_cnt : RO; bitpos: [23:19]; default: 0; + * Stores the byte number of data in Tx-FIFO. + */ + uint32_t txfifo_cnt:5; + uint32_t reserved_24:5; + /** dtrn : RO; bitpos: [29]; default: 1; + * This bit represents the level of the internal uart dtr signal. + */ + uint32_t dtrn:1; + /** rtsn : RO; bitpos: [30]; default: 1; + * This bit represents the level of the internal uart rts signal. + */ + uint32_t rtsn:1; + /** txd : RO; bitpos: [31]; default: 1; + * This bit represents the level of the internal uart txd signal. + */ + uint32_t txd:1; + }; + uint32_t val; +} lp_uart_status_reg_t; + +/** Type of mem_tx_status register + * Tx-SRAM write and read offset address. + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** tx_sram_waddr : RO; bitpos: [7:3]; default: 0; + * This register stores the offset write address in Tx-SRAM. + */ + uint32_t tx_sram_waddr:5; + uint32_t reserved_8:4; + /** tx_sram_raddr : RO; bitpos: [16:12]; default: 0; + * This register stores the offset read address in Tx-SRAM. + */ + uint32_t tx_sram_raddr:5; + uint32_t reserved_17:15; + }; + uint32_t val; +} lp_uart_mem_tx_status_reg_t; + +/** Type of mem_rx_status register + * Rx-SRAM write and read offset address. + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** rx_sram_raddr : RO; bitpos: [7:3]; default: 16; + * This register stores the offset read address in RX-SRAM. + */ + uint32_t rx_sram_raddr:5; + uint32_t reserved_8:4; + /** rx_sram_waddr : RO; bitpos: [16:12]; default: 16; + * This register stores the offset write address in Rx-SRAM. + */ + uint32_t rx_sram_waddr:5; + uint32_t reserved_17:15; + }; + uint32_t val; +} lp_uart_mem_rx_status_reg_t; + +/** Type of fsm_status register + * UART transmit and receive status. + */ +typedef union { + struct { + /** st_urx_out : RO; bitpos: [3:0]; default: 0; + * This is the status register of receiver. + */ + uint32_t st_urx_out:4; + /** st_utx_out : RO; bitpos: [7:4]; default: 0; + * This is the status register of transmitter. + */ + uint32_t st_utx_out:4; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_uart_fsm_status_reg_t; + +/** Type of afifo_status register + * UART AFIFO Status + */ +typedef union { + struct { + /** tx_afifo_full : RO; bitpos: [0]; default: 0; + * Full signal of APB TX AFIFO. + */ + uint32_t tx_afifo_full:1; + /** tx_afifo_empty : RO; bitpos: [1]; default: 1; + * Empty signal of APB TX AFIFO. + */ + uint32_t tx_afifo_empty:1; + /** rx_afifo_full : RO; bitpos: [2]; default: 0; + * Full signal of APB RX AFIFO. + */ + uint32_t rx_afifo_full:1; + /** rx_afifo_empty : RO; bitpos: [3]; default: 1; + * Empty signal of APB RX AFIFO. + */ + uint32_t rx_afifo_empty:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} lp_uart_afifo_status_reg_t; + + +/** Group: AT Escape Sequence Selection Configuration */ +/** Type of at_cmd_precnt_sync register + * Pre-sequence timing configuration + */ +typedef union { + struct { + /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the idle duration time before the first at_cmd + * is received by receiver. + */ + uint32_t pre_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_uart_at_cmd_precnt_sync_reg_t; + +/** Type of at_cmd_postcnt_sync register + * Post-sequence timing configuration + */ +typedef union { + struct { + /** post_idle_num : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the duration time between the last at_cmd and + * the next data. + */ + uint32_t post_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_uart_at_cmd_postcnt_sync_reg_t; + +/** Type of at_cmd_gaptout_sync register + * Timeout configuration + */ +typedef union { + struct { + /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11; + * This register is used to configure the duration time between the at_cmd chars. + */ + uint32_t rx_gap_tout:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_uart_at_cmd_gaptout_sync_reg_t; + +/** Type of at_cmd_char_sync register + * AT escape sequence detection configuration + */ +typedef union { + struct { + /** at_cmd_char : R/W; bitpos: [7:0]; default: 43; + * This register is used to configure the content of at_cmd char. + */ + uint32_t at_cmd_char:8; + /** char_num : R/W; bitpos: [15:8]; default: 3; + * This register is used to configure the num of continuous at_cmd chars received by + * receiver. + */ + uint32_t char_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_uart_at_cmd_char_sync_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * UART Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35656288; + * This is the version register. + */ + uint32_t date:32; + }; + uint32_t val; +} lp_uart_date_reg_t; + +/** Type of reg_update register + * UART Registers Configuration Update register + */ +typedef union { + struct { + /** reg_update : R/W/SC; bitpos: [0]; default: 0; + * Software write 1 would synchronize registers into UART Core clock domain and would + * be cleared by hardware after synchronization is done. + */ + uint32_t reg_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_uart_reg_update_reg_t; + +/** Type of id register + * UART ID register + */ +typedef union { + struct { + /** id : R/W; bitpos: [31:0]; default: 1280; + * This register is used to configure the uart_id. + */ + uint32_t id:32; + }; + uint32_t val; +} lp_uart_id_reg_t; + + +typedef struct lp_uart_dev_t { + volatile lp_uart_fifo_reg_t fifo; + volatile lp_uart_int_raw_reg_t int_raw; + volatile lp_uart_int_st_reg_t int_st; + volatile lp_uart_int_ena_reg_t int_ena; + volatile lp_uart_int_clr_reg_t int_clr; + volatile lp_uart_clkdiv_sync_reg_t clkdiv_sync; + volatile lp_uart_rx_filt_reg_t rx_filt; + volatile lp_uart_status_reg_t status; + volatile lp_uart_conf0_sync_reg_t conf0_sync; + volatile lp_uart_conf1_reg_t conf1; + uint32_t reserved_028; + volatile lp_uart_hwfc_conf_sync_reg_t hwfc_conf_sync; + volatile lp_uart_sleep_conf0_reg_t sleep_conf0; + volatile lp_uart_sleep_conf1_reg_t sleep_conf1; + volatile lp_uart_sleep_conf2_reg_t sleep_conf2; + volatile lp_uart_swfc_conf0_sync_reg_t swfc_conf0_sync; + volatile lp_uart_swfc_conf1_reg_t swfc_conf1; + volatile lp_uart_txbrk_conf_sync_reg_t txbrk_conf_sync; + volatile lp_uart_idle_conf_sync_reg_t idle_conf_sync; + volatile lp_uart_rs485_conf_sync_reg_t rs485_conf_sync; + volatile lp_uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync; + volatile lp_uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync; + volatile lp_uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync; + volatile lp_uart_at_cmd_char_sync_reg_t at_cmd_char_sync; + volatile lp_uart_mem_conf_reg_t mem_conf; + volatile lp_uart_tout_conf_sync_reg_t tout_conf_sync; + volatile lp_uart_mem_tx_status_reg_t mem_tx_status; + volatile lp_uart_mem_rx_status_reg_t mem_rx_status; + volatile lp_uart_fsm_status_reg_t fsm_status; + uint32_t reserved_074[5]; + volatile lp_uart_clk_conf_reg_t clk_conf; + volatile lp_uart_date_reg_t date; + volatile lp_uart_afifo_status_reg_t afifo_status; + uint32_t reserved_094; + volatile lp_uart_reg_update_reg_t reg_update; + volatile lp_uart_id_reg_t id; +} lp_uart_dev_t; + +extern lp_uart_dev_t LP_UART; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_uart_dev_t) == 0xa0, "Invalid size of lp_uart_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_wdt_reg.h b/components/soc/esp32c6/include/soc/lp_wdt_reg.h new file mode 100644 index 0000000000..5c9a78dac9 --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_wdt_reg.h @@ -0,0 +1,354 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: IDF-5730 (better to move to wdt_types.h?) +/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */ +#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1 +/* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG to write-enable the wdt registers */ +#define RTC_CNTL_SWD_WKEY_VALUE 0x8F1D312A + +/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */ +#define RTC_WDT_RESET_LENGTH_100_NS 0 +#define RTC_WDT_RESET_LENGTH_200_NS 1 +#define RTC_WDT_RESET_LENGTH_300_NS 2 +#define RTC_WDT_RESET_LENGTH_400_NS 3 +#define RTC_WDT_RESET_LENGTH_500_NS 4 +#define RTC_WDT_RESET_LENGTH_800_NS 5 +#define RTC_WDT_RESET_LENGTH_1600_NS 6 +#define RTC_WDT_RESET_LENGTH_3200_NS 7 + +/** LP_WDT_CONFIG0_REG register + * need_des + */ +#define LP_WDT_CONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0) +/** LP_WDT_WDT_CHIP_RESET_WIDTH : R/W; bitpos: [7:0]; default: 20; + * need_des + */ +#define LP_WDT_WDT_CHIP_RESET_WIDTH 0x000000FFU +#define LP_WDT_WDT_CHIP_RESET_WIDTH_M (LP_WDT_WDT_CHIP_RESET_WIDTH_V << LP_WDT_WDT_CHIP_RESET_WIDTH_S) +#define LP_WDT_WDT_CHIP_RESET_WIDTH_V 0x000000FFU +#define LP_WDT_WDT_CHIP_RESET_WIDTH_S 0 +/** LP_WDT_WDT_CHIP_RESET_EN : R/W; bitpos: [8]; default: 0; + * need_des + */ +#define LP_WDT_WDT_CHIP_RESET_EN (BIT(8)) +#define LP_WDT_WDT_CHIP_RESET_EN_M (LP_WDT_WDT_CHIP_RESET_EN_V << LP_WDT_WDT_CHIP_RESET_EN_S) +#define LP_WDT_WDT_CHIP_RESET_EN_V 0x00000001U +#define LP_WDT_WDT_CHIP_RESET_EN_S 8 +/** LP_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define LP_WDT_WDT_PAUSE_IN_SLP (BIT(9)) +#define LP_WDT_WDT_PAUSE_IN_SLP_M (LP_WDT_WDT_PAUSE_IN_SLP_V << LP_WDT_WDT_PAUSE_IN_SLP_S) +#define LP_WDT_WDT_PAUSE_IN_SLP_V 0x00000001U +#define LP_WDT_WDT_PAUSE_IN_SLP_S 9 +/** LP_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define LP_WDT_WDT_APPCPU_RESET_EN (BIT(10)) +#define LP_WDT_WDT_APPCPU_RESET_EN_M (LP_WDT_WDT_APPCPU_RESET_EN_V << LP_WDT_WDT_APPCPU_RESET_EN_S) +#define LP_WDT_WDT_APPCPU_RESET_EN_V 0x00000001U +#define LP_WDT_WDT_APPCPU_RESET_EN_S 10 +/** LP_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define LP_WDT_WDT_PROCPU_RESET_EN (BIT(11)) +#define LP_WDT_WDT_PROCPU_RESET_EN_M (LP_WDT_WDT_PROCPU_RESET_EN_V << LP_WDT_WDT_PROCPU_RESET_EN_S) +#define LP_WDT_WDT_PROCPU_RESET_EN_V 0x00000001U +#define LP_WDT_WDT_PROCPU_RESET_EN_S 11 +/** LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1; + * need_des + */ +#define LP_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12)) +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M (LP_WDT_WDT_FLASHBOOT_MOD_EN_V << LP_WDT_WDT_FLASHBOOT_MOD_EN_S) +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V 0x00000001U +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_S 12 +/** LP_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1; + * need_des + */ +#define LP_WDT_WDT_SYS_RESET_LENGTH 0x00000007U +#define LP_WDT_WDT_SYS_RESET_LENGTH_M (LP_WDT_WDT_SYS_RESET_LENGTH_V << LP_WDT_WDT_SYS_RESET_LENGTH_S) +#define LP_WDT_WDT_SYS_RESET_LENGTH_V 0x00000007U +#define LP_WDT_WDT_SYS_RESET_LENGTH_S 13 +/** LP_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1; + * need_des + */ +#define LP_WDT_WDT_CPU_RESET_LENGTH 0x00000007U +#define LP_WDT_WDT_CPU_RESET_LENGTH_M (LP_WDT_WDT_CPU_RESET_LENGTH_V << LP_WDT_WDT_CPU_RESET_LENGTH_S) +#define LP_WDT_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define LP_WDT_WDT_CPU_RESET_LENGTH_S 16 +/** LP_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG3 0x00000007U +#define LP_WDT_WDT_STG3_M (LP_WDT_WDT_STG3_V << LP_WDT_WDT_STG3_S) +#define LP_WDT_WDT_STG3_V 0x00000007U +#define LP_WDT_WDT_STG3_S 19 +/** LP_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG2 0x00000007U +#define LP_WDT_WDT_STG2_M (LP_WDT_WDT_STG2_V << LP_WDT_WDT_STG2_S) +#define LP_WDT_WDT_STG2_V 0x00000007U +#define LP_WDT_WDT_STG2_S 22 +/** LP_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG1 0x00000007U +#define LP_WDT_WDT_STG1_M (LP_WDT_WDT_STG1_V << LP_WDT_WDT_STG1_S) +#define LP_WDT_WDT_STG1_V 0x00000007U +#define LP_WDT_WDT_STG1_S 25 +/** LP_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG0 0x00000007U +#define LP_WDT_WDT_STG0_M (LP_WDT_WDT_STG0_V << LP_WDT_WDT_STG0_S) +#define LP_WDT_WDT_STG0_V 0x00000007U +#define LP_WDT_WDT_STG0_S 28 +/** LP_WDT_WDT_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_WDT_EN (BIT(31)) +#define LP_WDT_WDT_EN_M (LP_WDT_WDT_EN_V << LP_WDT_WDT_EN_S) +#define LP_WDT_WDT_EN_V 0x00000001U +#define LP_WDT_WDT_EN_S 31 + +/** LP_WDT_CONFIG1_REG register + * need_des + */ +#define LP_WDT_CONFIG1_REG (DR_REG_LP_WDT_BASE + 0x4) +/** LP_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000; + * need_des + */ +#define LP_WDT_WDT_STG0_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG0_HOLD_M (LP_WDT_WDT_STG0_HOLD_V << LP_WDT_WDT_STG0_HOLD_S) +#define LP_WDT_WDT_STG0_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG0_HOLD_S 0 + +/** LP_WDT_CONFIG2_REG register + * need_des + */ +#define LP_WDT_CONFIG2_REG (DR_REG_LP_WDT_BASE + 0x8) +/** LP_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000; + * need_des + */ +#define LP_WDT_WDT_STG1_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG1_HOLD_M (LP_WDT_WDT_STG1_HOLD_V << LP_WDT_WDT_STG1_HOLD_S) +#define LP_WDT_WDT_STG1_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG1_HOLD_S 0 + +/** LP_WDT_CONFIG3_REG register + * need_des + */ +#define LP_WDT_CONFIG3_REG (DR_REG_LP_WDT_BASE + 0xc) +/** LP_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ +#define LP_WDT_WDT_STG2_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG2_HOLD_M (LP_WDT_WDT_STG2_HOLD_V << LP_WDT_WDT_STG2_HOLD_S) +#define LP_WDT_WDT_STG2_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG2_HOLD_S 0 + +/** LP_WDT_CONFIG4_REG register + * need_des + */ +#define LP_WDT_CONFIG4_REG (DR_REG_LP_WDT_BASE + 0x10) +/** LP_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ +#define LP_WDT_WDT_STG3_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG3_HOLD_M (LP_WDT_WDT_STG3_HOLD_V << LP_WDT_WDT_STG3_HOLD_S) +#define LP_WDT_WDT_STG3_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG3_HOLD_S 0 + +/** LP_WDT_FEED_REG register + * need_des + */ +#define LP_WDT_FEED_REG (DR_REG_LP_WDT_BASE + 0x14) +/** LP_WDT_RTC_WDT_FEED : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_RTC_WDT_FEED (BIT(31)) +#define LP_WDT_RTC_WDT_FEED_M (LP_WDT_RTC_WDT_FEED_V << LP_WDT_RTC_WDT_FEED_S) +#define LP_WDT_RTC_WDT_FEED_V 0x00000001U +#define LP_WDT_RTC_WDT_FEED_S 31 + +/** LP_WDT_WPROTECT_REG register + * need_des + */ +#define LP_WDT_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x18) +/** LP_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_WDT_WDT_WKEY 0xFFFFFFFFU +#define LP_WDT_WDT_WKEY_M (LP_WDT_WDT_WKEY_V << LP_WDT_WDT_WKEY_S) +#define LP_WDT_WDT_WKEY_V 0xFFFFFFFFU +#define LP_WDT_WDT_WKEY_S 0 + +/** LP_WDT_SWD_CONFIG_REG register + * need_des + */ +#define LP_WDT_SWD_CONFIG_REG (DR_REG_LP_WDT_BASE + 0x1c) +/** LP_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0; + * need_des + */ +#define LP_WDT_SWD_RESET_FLAG (BIT(0)) +#define LP_WDT_SWD_RESET_FLAG_M (LP_WDT_SWD_RESET_FLAG_V << LP_WDT_SWD_RESET_FLAG_S) +#define LP_WDT_SWD_RESET_FLAG_V 0x00000001U +#define LP_WDT_SWD_RESET_FLAG_S 0 +/** LP_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0; + * need_des + */ +#define LP_WDT_SWD_AUTO_FEED_EN (BIT(18)) +#define LP_WDT_SWD_AUTO_FEED_EN_M (LP_WDT_SWD_AUTO_FEED_EN_V << LP_WDT_SWD_AUTO_FEED_EN_S) +#define LP_WDT_SWD_AUTO_FEED_EN_V 0x00000001U +#define LP_WDT_SWD_AUTO_FEED_EN_S 18 +/** LP_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0; + * need_des + */ +#define LP_WDT_SWD_RST_FLAG_CLR (BIT(19)) +#define LP_WDT_SWD_RST_FLAG_CLR_M (LP_WDT_SWD_RST_FLAG_CLR_V << LP_WDT_SWD_RST_FLAG_CLR_S) +#define LP_WDT_SWD_RST_FLAG_CLR_V 0x00000001U +#define LP_WDT_SWD_RST_FLAG_CLR_S 19 +/** LP_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300; + * need_des + */ +#define LP_WDT_SWD_SIGNAL_WIDTH 0x000003FFU +#define LP_WDT_SWD_SIGNAL_WIDTH_M (LP_WDT_SWD_SIGNAL_WIDTH_V << LP_WDT_SWD_SIGNAL_WIDTH_S) +#define LP_WDT_SWD_SIGNAL_WIDTH_V 0x000003FFU +#define LP_WDT_SWD_SIGNAL_WIDTH_S 20 +/** LP_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SWD_DISABLE (BIT(30)) +#define LP_WDT_SWD_DISABLE_M (LP_WDT_SWD_DISABLE_V << LP_WDT_SWD_DISABLE_S) +#define LP_WDT_SWD_DISABLE_V 0x00000001U +#define LP_WDT_SWD_DISABLE_S 30 +/** LP_WDT_SWD_FEED : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_SWD_FEED (BIT(31)) +#define LP_WDT_SWD_FEED_M (LP_WDT_SWD_FEED_V << LP_WDT_SWD_FEED_S) +#define LP_WDT_SWD_FEED_V 0x00000001U +#define LP_WDT_SWD_FEED_S 31 + +/** LP_WDT_SWD_WPROTECT_REG register + * need_des + */ +#define LP_WDT_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x20) +/** LP_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_WDT_SWD_WKEY 0xFFFFFFFFU +#define LP_WDT_SWD_WKEY_M (LP_WDT_SWD_WKEY_V << LP_WDT_SWD_WKEY_S) +#define LP_WDT_SWD_WKEY_V 0xFFFFFFFFU +#define LP_WDT_SWD_WKEY_S 0 + +/** LP_WDT_INT_RAW_REG register + * need_des + */ +#define LP_WDT_INT_RAW_REG (DR_REG_LP_WDT_BASE + 0x24) +/** LP_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_RAW (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_RAW_M (LP_WDT_SUPER_WDT_INT_RAW_V << LP_WDT_SUPER_WDT_INT_RAW_S) +#define LP_WDT_SUPER_WDT_INT_RAW_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_RAW_S 30 +/** LP_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_RAW (BIT(31)) +#define LP_WDT_LP_WDT_INT_RAW_M (LP_WDT_LP_WDT_INT_RAW_V << LP_WDT_LP_WDT_INT_RAW_S) +#define LP_WDT_LP_WDT_INT_RAW_V 0x00000001U +#define LP_WDT_LP_WDT_INT_RAW_S 31 + +/** LP_WDT_INT_ST_REG register + * need_des + */ +#define LP_WDT_INT_ST_REG (DR_REG_LP_WDT_BASE + 0x28) +/** LP_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_ST (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_ST_M (LP_WDT_SUPER_WDT_INT_ST_V << LP_WDT_SUPER_WDT_INT_ST_S) +#define LP_WDT_SUPER_WDT_INT_ST_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_ST_S 30 +/** LP_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_ST (BIT(31)) +#define LP_WDT_LP_WDT_INT_ST_M (LP_WDT_LP_WDT_INT_ST_V << LP_WDT_LP_WDT_INT_ST_S) +#define LP_WDT_LP_WDT_INT_ST_V 0x00000001U +#define LP_WDT_LP_WDT_INT_ST_S 31 + +/** LP_WDT_INT_ENA_REG register + * need_des + */ +#define LP_WDT_INT_ENA_REG (DR_REG_LP_WDT_BASE + 0x2c) +/** LP_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_ENA (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_ENA_M (LP_WDT_SUPER_WDT_INT_ENA_V << LP_WDT_SUPER_WDT_INT_ENA_S) +#define LP_WDT_SUPER_WDT_INT_ENA_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_ENA_S 30 +/** LP_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_ENA (BIT(31)) +#define LP_WDT_LP_WDT_INT_ENA_M (LP_WDT_LP_WDT_INT_ENA_V << LP_WDT_LP_WDT_INT_ENA_S) +#define LP_WDT_LP_WDT_INT_ENA_V 0x00000001U +#define LP_WDT_LP_WDT_INT_ENA_S 31 + +/** LP_WDT_INT_CLR_REG register + * need_des + */ +#define LP_WDT_INT_CLR_REG (DR_REG_LP_WDT_BASE + 0x30) +/** LP_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_CLR (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_CLR_M (LP_WDT_SUPER_WDT_INT_CLR_V << LP_WDT_SUPER_WDT_INT_CLR_S) +#define LP_WDT_SUPER_WDT_INT_CLR_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_CLR_S 30 +/** LP_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_CLR (BIT(31)) +#define LP_WDT_LP_WDT_INT_CLR_M (LP_WDT_LP_WDT_INT_CLR_V << LP_WDT_LP_WDT_INT_CLR_S) +#define LP_WDT_LP_WDT_INT_CLR_V 0x00000001U +#define LP_WDT_LP_WDT_INT_CLR_S 31 + +/** LP_WDT_DATE_REG register + * need_des + */ +#define LP_WDT_DATE_REG (DR_REG_LP_WDT_BASE + 0x3fc) +/** LP_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 34676864; + * need_des + */ +#define LP_WDT_LP_WDT_DATE 0x7FFFFFFFU +#define LP_WDT_LP_WDT_DATE_M (LP_WDT_LP_WDT_DATE_V << LP_WDT_LP_WDT_DATE_S) +#define LP_WDT_LP_WDT_DATE_V 0x7FFFFFFFU +#define LP_WDT_LP_WDT_DATE_S 0 +/** LP_WDT_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_CLK_EN (BIT(31)) +#define LP_WDT_CLK_EN_M (LP_WDT_CLK_EN_V << LP_WDT_CLK_EN_S) +#define LP_WDT_CLK_EN_V 0x00000001U +#define LP_WDT_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lp_wdt_struct.h b/components/soc/esp32c6/include/soc/lp_wdt_struct.h new file mode 100644 index 0000000000..67740dbd74 --- /dev/null +++ b/components/soc/esp32c6/include/soc/lp_wdt_struct.h @@ -0,0 +1,317 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of config0 register + * need_des + */ +typedef union { + struct { + /** wdt_chip_reset_width : R/W; bitpos: [7:0]; default: 20; + * need_des + */ + uint32_t wdt_chip_reset_width:8; + /** wdt_chip_reset_en : R/W; bitpos: [8]; default: 0; + * need_des + */ + uint32_t wdt_chip_reset_en:1; + /** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1; + * need_des + */ + uint32_t wdt_pause_in_slp:1; + /** wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t wdt_appcpu_reset_en:1; + /** wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t wdt_procpu_reset_en:1; + /** wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1; + * need_des + */ + uint32_t wdt_flashboot_mod_en:1; + /** wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1; + * need_des + */ + uint32_t wdt_sys_reset_length:3; + /** wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1; + * need_des + */ + uint32_t wdt_cpu_reset_length:3; + /** wdt_stg3 : R/W; bitpos: [21:19]; default: 0; + * need_des + */ + uint32_t wdt_stg3:3; + /** wdt_stg2 : R/W; bitpos: [24:22]; default: 0; + * need_des + */ + uint32_t wdt_stg2:3; + /** wdt_stg1 : R/W; bitpos: [27:25]; default: 0; + * need_des + */ + uint32_t wdt_stg1:3; + /** wdt_stg0 : R/W; bitpos: [30:28]; default: 0; + * need_des + */ + uint32_t wdt_stg0:3; + /** wdt_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t wdt_en:1; + }; + uint32_t val; +} lp_wdt_config0_reg_t; + +/** Type of config1 register + * need_des + */ +typedef union { + struct { + /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000; + * need_des + */ + uint32_t wdt_stg0_hold:32; + }; + uint32_t val; +} lp_wdt_config1_reg_t; + +/** Type of config2 register + * need_des + */ +typedef union { + struct { + /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000; + * need_des + */ + uint32_t wdt_stg1_hold:32; + }; + uint32_t val; +} lp_wdt_config2_reg_t; + +/** Type of config3 register + * need_des + */ +typedef union { + struct { + /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ + uint32_t wdt_stg2_hold:32; + }; + uint32_t val; +} lp_wdt_config3_reg_t; + +/** Type of config4 register + * need_des + */ +typedef union { + struct { + /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ + uint32_t wdt_stg3_hold:32; + }; + uint32_t val; +} lp_wdt_config4_reg_t; + +/** Type of feed register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** rtc_wdt_feed : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t rtc_wdt_feed:1; + }; + uint32_t val; +} lp_wdt_feed_reg_t; + +/** Type of wprotect register + * need_des + */ +typedef union { + struct { + /** wdt_wkey : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t wdt_wkey:32; + }; + uint32_t val; +} lp_wdt_wprotect_reg_t; + +/** Type of swd_config register + * need_des + */ +typedef union { + struct { + /** swd_reset_flag : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t swd_reset_flag:1; + uint32_t reserved_1:17; + /** swd_auto_feed_en : R/W; bitpos: [18]; default: 0; + * need_des + */ + uint32_t swd_auto_feed_en:1; + /** swd_rst_flag_clr : WT; bitpos: [19]; default: 0; + * need_des + */ + uint32_t swd_rst_flag_clr:1; + /** swd_signal_width : R/W; bitpos: [29:20]; default: 300; + * need_des + */ + uint32_t swd_signal_width:10; + /** swd_disable : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t swd_disable:1; + /** swd_feed : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t swd_feed:1; + }; + uint32_t val; +} lp_wdt_swd_config_reg_t; + +/** Type of swd_wprotect register + * need_des + */ +typedef union { + struct { + /** swd_wkey : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t swd_wkey:32; + }; + uint32_t val; +} lp_wdt_swd_wprotect_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t super_wdt_int_raw:1; + /** lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_wdt_int_raw:1; + }; + uint32_t val; +} lp_wdt_int_raw_reg_t; + +/** Type of int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t super_wdt_int_st:1; + /** lp_wdt_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_wdt_int_st:1; + }; + uint32_t val; +} lp_wdt_int_st_reg_t; + +/** Type of int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t super_wdt_int_ena:1; + /** lp_wdt_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_wdt_int_ena:1; + }; + uint32_t val; +} lp_wdt_int_ena_reg_t; + +/** Type of int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t super_wdt_int_clr:1; + /** lp_wdt_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_wdt_int_clr:1; + }; + uint32_t val; +} lp_wdt_int_clr_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** lp_wdt_date : R/W; bitpos: [30:0]; default: 34676864; + * need_des + */ + uint32_t lp_wdt_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_wdt_date_reg_t; + + +typedef struct lp_wdt_dev_t { + volatile lp_wdt_config0_reg_t config0; + volatile lp_wdt_config1_reg_t config1; + volatile lp_wdt_config2_reg_t config2; + volatile lp_wdt_config3_reg_t config3; + volatile lp_wdt_config4_reg_t config4; + volatile lp_wdt_feed_reg_t feed; + volatile lp_wdt_wprotect_reg_t wprotect; + volatile lp_wdt_swd_config_reg_t swd_config; + volatile lp_wdt_swd_wprotect_reg_t swd_wprotect; + volatile lp_wdt_int_raw_reg_t int_raw; + volatile lp_wdt_int_st_reg_t int_st; + volatile lp_wdt_int_ena_reg_t int_ena; + volatile lp_wdt_int_clr_reg_t int_clr; + uint32_t reserved_034[242]; + volatile lp_wdt_date_reg_t date; +} lp_wdt_dev_t; + +extern lp_wdt_dev_t LP_WDT; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_wdt_dev_t) == 0x400, "Invalid size of lp_wdt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lpperi_reg.h b/components/soc/esp32c6/include/soc/lpperi_reg.h new file mode 100644 index 0000000000..80b4d32f86 --- /dev/null +++ b/components/soc/esp32c6/include/soc/lpperi_reg.h @@ -0,0 +1,284 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LPPERI_CLK_EN_REG register + * need_des + */ +#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0) +/** LPPERI_RNG_CK_EN : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define LPPERI_RNG_CK_EN (BIT(24)) +#define LPPERI_RNG_CK_EN_M (LPPERI_RNG_CK_EN_V << LPPERI_RNG_CK_EN_S) +#define LPPERI_RNG_CK_EN_V 0x00000001U +#define LPPERI_RNG_CK_EN_S 24 +/** LPPERI_OTP_DBG_CK_EN : R/W; bitpos: [25]; default: 1; + * need_des + */ +#define LPPERI_OTP_DBG_CK_EN (BIT(25)) +#define LPPERI_OTP_DBG_CK_EN_M (LPPERI_OTP_DBG_CK_EN_V << LPPERI_OTP_DBG_CK_EN_S) +#define LPPERI_OTP_DBG_CK_EN_V 0x00000001U +#define LPPERI_OTP_DBG_CK_EN_S 25 +/** LPPERI_LP_UART_CK_EN : R/W; bitpos: [26]; default: 1; + * need_des + */ +#define LPPERI_LP_UART_CK_EN (BIT(26)) +#define LPPERI_LP_UART_CK_EN_M (LPPERI_LP_UART_CK_EN_V << LPPERI_LP_UART_CK_EN_S) +#define LPPERI_LP_UART_CK_EN_V 0x00000001U +#define LPPERI_LP_UART_CK_EN_S 26 +/** LPPERI_LP_IO_CK_EN : R/W; bitpos: [27]; default: 1; + * need_des + */ +#define LPPERI_LP_IO_CK_EN (BIT(27)) +#define LPPERI_LP_IO_CK_EN_M (LPPERI_LP_IO_CK_EN_V << LPPERI_LP_IO_CK_EN_S) +#define LPPERI_LP_IO_CK_EN_V 0x00000001U +#define LPPERI_LP_IO_CK_EN_S 27 +/** LPPERI_LP_EXT_I2C_CK_EN : R/W; bitpos: [28]; default: 1; + * need_des + */ +#define LPPERI_LP_EXT_I2C_CK_EN (BIT(28)) +#define LPPERI_LP_EXT_I2C_CK_EN_M (LPPERI_LP_EXT_I2C_CK_EN_V << LPPERI_LP_EXT_I2C_CK_EN_S) +#define LPPERI_LP_EXT_I2C_CK_EN_V 0x00000001U +#define LPPERI_LP_EXT_I2C_CK_EN_S 28 +/** LPPERI_LP_ANA_I2C_CK_EN : R/W; bitpos: [29]; default: 1; + * need_des + */ +#define LPPERI_LP_ANA_I2C_CK_EN (BIT(29)) +#define LPPERI_LP_ANA_I2C_CK_EN_M (LPPERI_LP_ANA_I2C_CK_EN_V << LPPERI_LP_ANA_I2C_CK_EN_S) +#define LPPERI_LP_ANA_I2C_CK_EN_V 0x00000001U +#define LPPERI_LP_ANA_I2C_CK_EN_S 29 +/** LPPERI_EFUSE_CK_EN : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define LPPERI_EFUSE_CK_EN (BIT(30)) +#define LPPERI_EFUSE_CK_EN_M (LPPERI_EFUSE_CK_EN_V << LPPERI_EFUSE_CK_EN_S) +#define LPPERI_EFUSE_CK_EN_V 0x00000001U +#define LPPERI_EFUSE_CK_EN_S 30 +/** LPPERI_LP_CPU_CK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_LP_CPU_CK_EN (BIT(31)) +#define LPPERI_LP_CPU_CK_EN_M (LPPERI_LP_CPU_CK_EN_V << LPPERI_LP_CPU_CK_EN_S) +#define LPPERI_LP_CPU_CK_EN_V 0x00000001U +#define LPPERI_LP_CPU_CK_EN_S 31 + +/** LPPERI_RESET_EN_REG register + * need_des + */ +#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x4) +/** LPPERI_BUS_RESET_EN : WT; bitpos: [23]; default: 0; + * need_des + */ +#define LPPERI_BUS_RESET_EN (BIT(23)) +#define LPPERI_BUS_RESET_EN_M (LPPERI_BUS_RESET_EN_V << LPPERI_BUS_RESET_EN_S) +#define LPPERI_BUS_RESET_EN_V 0x00000001U +#define LPPERI_BUS_RESET_EN_S 23 +/** LPPERI_OTP_DBG_RESET_EN : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define LPPERI_OTP_DBG_RESET_EN (BIT(25)) +#define LPPERI_OTP_DBG_RESET_EN_M (LPPERI_OTP_DBG_RESET_EN_V << LPPERI_OTP_DBG_RESET_EN_S) +#define LPPERI_OTP_DBG_RESET_EN_V 0x00000001U +#define LPPERI_OTP_DBG_RESET_EN_S 25 +/** LPPERI_LP_UART_RESET_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define LPPERI_LP_UART_RESET_EN (BIT(26)) +#define LPPERI_LP_UART_RESET_EN_M (LPPERI_LP_UART_RESET_EN_V << LPPERI_LP_UART_RESET_EN_S) +#define LPPERI_LP_UART_RESET_EN_V 0x00000001U +#define LPPERI_LP_UART_RESET_EN_S 26 +/** LPPERI_LP_IO_RESET_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LPPERI_LP_IO_RESET_EN (BIT(27)) +#define LPPERI_LP_IO_RESET_EN_M (LPPERI_LP_IO_RESET_EN_V << LPPERI_LP_IO_RESET_EN_S) +#define LPPERI_LP_IO_RESET_EN_V 0x00000001U +#define LPPERI_LP_IO_RESET_EN_S 27 +/** LPPERI_LP_EXT_I2C_RESET_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LPPERI_LP_EXT_I2C_RESET_EN (BIT(28)) +#define LPPERI_LP_EXT_I2C_RESET_EN_M (LPPERI_LP_EXT_I2C_RESET_EN_V << LPPERI_LP_EXT_I2C_RESET_EN_S) +#define LPPERI_LP_EXT_I2C_RESET_EN_V 0x00000001U +#define LPPERI_LP_EXT_I2C_RESET_EN_S 28 +/** LPPERI_LP_ANA_I2C_RESET_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LPPERI_LP_ANA_I2C_RESET_EN (BIT(29)) +#define LPPERI_LP_ANA_I2C_RESET_EN_M (LPPERI_LP_ANA_I2C_RESET_EN_V << LPPERI_LP_ANA_I2C_RESET_EN_S) +#define LPPERI_LP_ANA_I2C_RESET_EN_V 0x00000001U +#define LPPERI_LP_ANA_I2C_RESET_EN_S 29 +/** LPPERI_EFUSE_RESET_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_EFUSE_RESET_EN (BIT(30)) +#define LPPERI_EFUSE_RESET_EN_M (LPPERI_EFUSE_RESET_EN_V << LPPERI_EFUSE_RESET_EN_S) +#define LPPERI_EFUSE_RESET_EN_V 0x00000001U +#define LPPERI_EFUSE_RESET_EN_S 30 +/** LPPERI_LP_CPU_RESET_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_LP_CPU_RESET_EN (BIT(31)) +#define LPPERI_LP_CPU_RESET_EN_M (LPPERI_LP_CPU_RESET_EN_V << LPPERI_LP_CPU_RESET_EN_S) +#define LPPERI_LP_CPU_RESET_EN_V 0x00000001U +#define LPPERI_LP_CPU_RESET_EN_S 31 + +/** LPPERI_RNG_DATA_REG register + * need_des + */ +#define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + 0x8) +/** LPPERI_RND_DATA : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LPPERI_RND_DATA 0xFFFFFFFFU +#define LPPERI_RND_DATA_M (LPPERI_RND_DATA_V << LPPERI_RND_DATA_S) +#define LPPERI_RND_DATA_V 0xFFFFFFFFU +#define LPPERI_RND_DATA_S 0 + +/** LPPERI_CPU_REG register + * need_des + */ +#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0xc) +/** LPPERI_LPCORE_DBGM_UNAVALIABLE : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_LPCORE_DBGM_UNAVALIABLE (BIT(31)) +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_M (LPPERI_LPCORE_DBGM_UNAVALIABLE_V << LPPERI_LPCORE_DBGM_UNAVALIABLE_S) +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_V 0x00000001U +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_S 31 + +/** LPPERI_BUS_TIMEOUT_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + 0x10) +/** LPPERI_LP_PERI_TIMEOUT_THRES : R/W; bitpos: [29:14]; default: 65535; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_THRES 0x0000FFFFU +#define LPPERI_LP_PERI_TIMEOUT_THRES_M (LPPERI_LP_PERI_TIMEOUT_THRES_V << LPPERI_LP_PERI_TIMEOUT_THRES_S) +#define LPPERI_LP_PERI_TIMEOUT_THRES_V 0x0000FFFFU +#define LPPERI_LP_PERI_TIMEOUT_THRES_S 14 +/** LPPERI_LP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR (BIT(30)) +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_M (LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V << LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S) +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S 30 +/** LPPERI_LP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN (BIT(31)) +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_M (LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V << LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S) +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S 31 + +/** LPPERI_BUS_TIMEOUT_ADDR_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + 0x14) +/** LPPERI_LP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU +#define LPPERI_LP_PERI_TIMEOUT_ADDR_M (LPPERI_LP_PERI_TIMEOUT_ADDR_V << LPPERI_LP_PERI_TIMEOUT_ADDR_S) +#define LPPERI_LP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU +#define LPPERI_LP_PERI_TIMEOUT_ADDR_S 0 + +/** LPPERI_BUS_TIMEOUT_UID_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + 0x18) +/** LPPERI_LP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_UID 0x0000007FU +#define LPPERI_LP_PERI_TIMEOUT_UID_M (LPPERI_LP_PERI_TIMEOUT_UID_V << LPPERI_LP_PERI_TIMEOUT_UID_S) +#define LPPERI_LP_PERI_TIMEOUT_UID_V 0x0000007FU +#define LPPERI_LP_PERI_TIMEOUT_UID_S 0 + +/** LPPERI_MEM_CTRL_REG register + * need_des + */ +#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x1c) +/** LPPERI_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_FLAG_CLR (BIT(0)) +#define LPPERI_UART_WAKEUP_FLAG_CLR_M (LPPERI_UART_WAKEUP_FLAG_CLR_V << LPPERI_UART_WAKEUP_FLAG_CLR_S) +#define LPPERI_UART_WAKEUP_FLAG_CLR_V 0x00000001U +#define LPPERI_UART_WAKEUP_FLAG_CLR_S 0 +/** LPPERI_UART_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_FLAG (BIT(1)) +#define LPPERI_UART_WAKEUP_FLAG_M (LPPERI_UART_WAKEUP_FLAG_V << LPPERI_UART_WAKEUP_FLAG_S) +#define LPPERI_UART_WAKEUP_FLAG_V 0x00000001U +#define LPPERI_UART_WAKEUP_FLAG_S 1 +/** LPPERI_UART_WAKEUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_EN (BIT(29)) +#define LPPERI_UART_WAKEUP_EN_M (LPPERI_UART_WAKEUP_EN_V << LPPERI_UART_WAKEUP_EN_S) +#define LPPERI_UART_WAKEUP_EN_V 0x00000001U +#define LPPERI_UART_WAKEUP_EN_S 29 +/** LPPERI_UART_MEM_FORCE_PD : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_UART_MEM_FORCE_PD (BIT(30)) +#define LPPERI_UART_MEM_FORCE_PD_M (LPPERI_UART_MEM_FORCE_PD_V << LPPERI_UART_MEM_FORCE_PD_S) +#define LPPERI_UART_MEM_FORCE_PD_V 0x00000001U +#define LPPERI_UART_MEM_FORCE_PD_S 30 +/** LPPERI_UART_MEM_FORCE_PU : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_UART_MEM_FORCE_PU (BIT(31)) +#define LPPERI_UART_MEM_FORCE_PU_M (LPPERI_UART_MEM_FORCE_PU_V << LPPERI_UART_MEM_FORCE_PU_S) +#define LPPERI_UART_MEM_FORCE_PU_V 0x00000001U +#define LPPERI_UART_MEM_FORCE_PU_S 31 + +/** LPPERI_INTERRUPT_SOURCE_REG register + * need_des + */ +#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + 0x20) +/** LPPERI_LP_INTERRUPT_SOURCE : RO; bitpos: [5:0]; default: 0; + * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, + * lp_io_int + */ +#define LPPERI_LP_INTERRUPT_SOURCE 0x0000003FU +#define LPPERI_LP_INTERRUPT_SOURCE_M (LPPERI_LP_INTERRUPT_SOURCE_V << LPPERI_LP_INTERRUPT_SOURCE_S) +#define LPPERI_LP_INTERRUPT_SOURCE_V 0x0000003FU +#define LPPERI_LP_INTERRUPT_SOURCE_S 0 + +/** LPPERI_DATE_REG register + * need_des + */ +#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc) +/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 35676464; + * need_des + */ +#define LPPERI_LPPERI_DATE 0x7FFFFFFFU +#define LPPERI_LPPERI_DATE_M (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S) +#define LPPERI_LPPERI_DATE_V 0x7FFFFFFFU +#define LPPERI_LPPERI_DATE_S 0 +/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_CLK_EN (BIT(31)) +#define LPPERI_CLK_EN_M (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S) +#define LPPERI_CLK_EN_V 0x00000001U +#define LPPERI_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/lpperi_struct.h b/components/soc/esp32c6/include/soc/lpperi_struct.h new file mode 100644 index 0000000000..278301712c --- /dev/null +++ b/components/soc/esp32c6/include/soc/lpperi_struct.h @@ -0,0 +1,262 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of clk_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** rng_ck_en : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t rng_ck_en:1; + /** otp_dbg_ck_en : R/W; bitpos: [25]; default: 1; + * need_des + */ + uint32_t otp_dbg_ck_en:1; + /** lp_uart_ck_en : R/W; bitpos: [26]; default: 1; + * need_des + */ + uint32_t lp_uart_ck_en:1; + /** lp_io_ck_en : R/W; bitpos: [27]; default: 1; + * need_des + */ + uint32_t lp_io_ck_en:1; + /** lp_ext_i2c_ck_en : R/W; bitpos: [28]; default: 1; + * need_des + */ + uint32_t lp_ext_i2c_ck_en:1; + /** lp_ana_i2c_ck_en : R/W; bitpos: [29]; default: 1; + * need_des + */ + uint32_t lp_ana_i2c_ck_en:1; + /** efuse_ck_en : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t efuse_ck_en:1; + /** lp_cpu_ck_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_ck_en:1; + }; + uint32_t val; +} lpperi_clk_en_reg_t; + +/** Type of reset_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** bus_reset_en : WT; bitpos: [23]; default: 0; + * need_des + */ + uint32_t bus_reset_en:1; + uint32_t reserved_24:1; + /** otp_dbg_reset_en : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t otp_dbg_reset_en:1; + /** lp_uart_reset_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t lp_uart_reset_en:1; + /** lp_io_reset_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_io_reset_en:1; + /** lp_ext_i2c_reset_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t lp_ext_i2c_reset_en:1; + /** lp_ana_i2c_reset_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_ana_i2c_reset_en:1; + /** efuse_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t efuse_reset_en:1; + /** lp_cpu_reset_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_reset_en:1; + }; + uint32_t val; +} lpperi_reset_en_reg_t; + +/** Type of rng_data register + * need_des + */ +typedef union { + struct { + /** rnd_data : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t rnd_data:32; + }; + uint32_t val; +} lpperi_rng_data_reg_t; + +/** Type of cpu register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lpcore_dbgm_unavaliable : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lpcore_dbgm_unavaliable:1; + }; + uint32_t val; +} lpperi_cpu_reg_t; + +/** Type of bus_timeout register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:14; + /** lp_peri_timeout_thres : R/W; bitpos: [29:14]; default: 65535; + * need_des + */ + uint32_t lp_peri_timeout_thres:16; + /** lp_peri_timeout_int_clear : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_int_clear:1; + /** lp_peri_timeout_protect_en : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lp_peri_timeout_protect_en:1; + }; + uint32_t val; +} lpperi_bus_timeout_reg_t; + +/** Type of bus_timeout_addr register + * need_des + */ +typedef union { + struct { + /** lp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_addr:32; + }; + uint32_t val; +} lpperi_bus_timeout_addr_reg_t; + +/** Type of bus_timeout_uid register + * need_des + */ +typedef union { + struct { + /** lp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_uid:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lpperi_bus_timeout_uid_reg_t; + +/** Type of mem_ctrl register + * need_des + */ +typedef union { + struct { + /** uart_wakeup_flag_clr : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t uart_wakeup_flag_clr:1; + /** uart_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ + uint32_t uart_wakeup_flag:1; + uint32_t reserved_2:27; + /** uart_wakeup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t uart_wakeup_en:1; + /** uart_mem_force_pd : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t uart_mem_force_pd:1; + /** uart_mem_force_pu : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t uart_mem_force_pu:1; + }; + uint32_t val; +} lpperi_mem_ctrl_reg_t; + +/** Type of interrupt_source register + * need_des + */ +typedef union { + struct { + /** lp_interrupt_source : RO; bitpos: [5:0]; default: 0; + * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, + * lp_io_int + */ + uint32_t lp_interrupt_source:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lpperi_interrupt_source_reg_t; + + +/** Group: Version register */ +/** Type of date register + * need_des + */ +typedef union { + struct { + /** lpperi_date : R/W; bitpos: [30:0]; default: 35676464; + * need_des + */ + uint32_t lpperi_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lpperi_date_reg_t; + + +typedef struct lpperi_dev_t { + volatile lpperi_clk_en_reg_t clk_en; + volatile lpperi_reset_en_reg_t reset_en; + volatile lpperi_rng_data_reg_t rng_data; + volatile lpperi_cpu_reg_t cpu; + volatile lpperi_bus_timeout_reg_t bus_timeout; + volatile lpperi_bus_timeout_addr_reg_t bus_timeout_addr; + volatile lpperi_bus_timeout_uid_reg_t bus_timeout_uid; + volatile lpperi_mem_ctrl_reg_t mem_ctrl; + volatile lpperi_interrupt_source_reg_t interrupt_source; + uint32_t reserved_024[246]; + volatile lpperi_date_reg_t date; +} lpperi_dev_t; + +extern lpperi_dev_t LPPERI; + +#ifndef __cplusplus +_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/mcpwm_reg.h b/components/soc/esp32c6/include/soc/mcpwm_reg.h new file mode 100644 index 0000000000..4eacabbc9c --- /dev/null +++ b/components/soc/esp32c6/include/soc/mcpwm_reg.h @@ -0,0 +1,4137 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** MCPWM_CLK_CFG_REG register + * PWM clock prescaler register. + */ +#define MCPWM_CLK_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0) +/** MCPWM_CLK_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1) + */ +#define MCPWM_CLK_PRESCALE 0x000000FFU +#define MCPWM_CLK_PRESCALE_M (MCPWM_CLK_PRESCALE_V << MCPWM_CLK_PRESCALE_S) +#define MCPWM_CLK_PRESCALE_V 0x000000FFU +#define MCPWM_CLK_PRESCALE_S 0 + +/** MCPWM_TIMER0_CFG0_REG register + * PWM timer0 period and update method configuration register. + */ +#define MCPWM_TIMER0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x4) +/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1) + */ +#define MCPWM_TIMER0_PRESCALE 0x000000FFU +#define MCPWM_TIMER0_PRESCALE_M (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S) +#define MCPWM_TIMER0_PRESCALE_V 0x000000FFU +#define MCPWM_TIMER0_PRESCALE_S 0 +/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255; + * period shadow register of PWM timer0 + */ +#define MCPWM_TIMER0_PERIOD 0x0000FFFFU +#define MCPWM_TIMER0_PERIOD_M (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S) +#define MCPWM_TIMER0_PERIOD_V 0x0000FFFFU +#define MCPWM_TIMER0_PERIOD_S 8 +/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; + * Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2: + * sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + */ +#define MCPWM_TIMER0_PERIOD_UPMETHOD 0x00000003U +#define MCPWM_TIMER0_PERIOD_UPMETHOD_M (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S) +#define MCPWM_TIMER0_PERIOD_UPMETHOD_V 0x00000003U +#define MCPWM_TIMER0_PERIOD_UPMETHOD_S 24 + +/** MCPWM_TIMER0_CFG1_REG register + * PWM timer0 working mode and start/stop control configuration register. + */ +#define MCPWM_TIMER0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x8) +/** MCPWM_TIMER0_START : R/W/SC; bitpos: [2:0]; default: 0; + * PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: + * if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 + * starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP + * here and below means the event that happens when the timer equals to period + */ +#define MCPWM_TIMER0_START 0x00000007U +#define MCPWM_TIMER0_START_M (MCPWM_TIMER0_START_V << MCPWM_TIMER0_START_S) +#define MCPWM_TIMER0_START_V 0x00000007U +#define MCPWM_TIMER0_START_S 0 +/** MCPWM_TIMER0_MOD : R/W; bitpos: [4:3]; default: 0; + * PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down + * mode + */ +#define MCPWM_TIMER0_MOD 0x00000003U +#define MCPWM_TIMER0_MOD_M (MCPWM_TIMER0_MOD_V << MCPWM_TIMER0_MOD_S) +#define MCPWM_TIMER0_MOD_V 0x00000003U +#define MCPWM_TIMER0_MOD_S 3 + +/** MCPWM_TIMER0_SYNC_REG register + * PWM timer0 sync function configuration register. + */ +#define MCPWM_TIMER0_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0xc) +/** MCPWM_TIMER0_SYNCI_EN : R/W; bitpos: [0]; default: 0; + * When set, timer reloading with phase on sync input event is enabled. + */ +#define MCPWM_TIMER0_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER0_SYNCI_EN_M (MCPWM_TIMER0_SYNCI_EN_V << MCPWM_TIMER0_SYNCI_EN_S) +#define MCPWM_TIMER0_SYNCI_EN_V 0x00000001U +#define MCPWM_TIMER0_SYNCI_EN_S 0 +/** MCPWM_TIMER0_SYNC_SW : R/W; bitpos: [1]; default: 0; + * Toggling this bit will trigger a software sync. + */ +#define MCPWM_TIMER0_SYNC_SW (BIT(1)) +#define MCPWM_TIMER0_SYNC_SW_M (MCPWM_TIMER0_SYNC_SW_V << MCPWM_TIMER0_SYNC_SW_S) +#define MCPWM_TIMER0_SYNC_SW_V 0x00000001U +#define MCPWM_TIMER0_SYNC_SW_S 1 +/** MCPWM_TIMER0_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; + * PWM timer0 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always + * generate when toggling the reg_timer0_sync_sw bit + */ +#define MCPWM_TIMER0_SYNCO_SEL 0x00000003U +#define MCPWM_TIMER0_SYNCO_SEL_M (MCPWM_TIMER0_SYNCO_SEL_V << MCPWM_TIMER0_SYNCO_SEL_S) +#define MCPWM_TIMER0_SYNCO_SEL_V 0x00000003U +#define MCPWM_TIMER0_SYNCO_SEL_S 2 +/** MCPWM_TIMER0_PHASE : R/W; bitpos: [19:4]; default: 0; + * phase for timer reload on sync event + */ +#define MCPWM_TIMER0_PHASE 0x0000FFFFU +#define MCPWM_TIMER0_PHASE_M (MCPWM_TIMER0_PHASE_V << MCPWM_TIMER0_PHASE_S) +#define MCPWM_TIMER0_PHASE_V 0x0000FFFFU +#define MCPWM_TIMER0_PHASE_S 4 +/** MCPWM_TIMER0_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; + * Configure the PWM timer0's direction when timer0 mode is up-down mode: + * 0-increase,1-decrease + */ +#define MCPWM_TIMER0_PHASE_DIRECTION (BIT(20)) +#define MCPWM_TIMER0_PHASE_DIRECTION_M (MCPWM_TIMER0_PHASE_DIRECTION_V << MCPWM_TIMER0_PHASE_DIRECTION_S) +#define MCPWM_TIMER0_PHASE_DIRECTION_V 0x00000001U +#define MCPWM_TIMER0_PHASE_DIRECTION_S 20 + +/** MCPWM_TIMER0_STATUS_REG register + * PWM timer0 status register. + */ +#define MCPWM_TIMER0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x10) +/** MCPWM_TIMER0_VALUE : RO; bitpos: [15:0]; default: 0; + * current PWM timer0 counter value + */ +#define MCPWM_TIMER0_VALUE 0x0000FFFFU +#define MCPWM_TIMER0_VALUE_M (MCPWM_TIMER0_VALUE_V << MCPWM_TIMER0_VALUE_S) +#define MCPWM_TIMER0_VALUE_V 0x0000FFFFU +#define MCPWM_TIMER0_VALUE_S 0 +/** MCPWM_TIMER0_DIRECTION : RO; bitpos: [16]; default: 0; + * current PWM timer0 counter direction, 0: increment 1: decrement + */ +#define MCPWM_TIMER0_DIRECTION (BIT(16)) +#define MCPWM_TIMER0_DIRECTION_M (MCPWM_TIMER0_DIRECTION_V << MCPWM_TIMER0_DIRECTION_S) +#define MCPWM_TIMER0_DIRECTION_V 0x00000001U +#define MCPWM_TIMER0_DIRECTION_S 16 + +/** MCPWM_TIMER1_CFG0_REG register + * PWM timer1 period and update method configuration register. + */ +#define MCPWM_TIMER1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x14) +/** MCPWM_TIMER1_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * period of PT0_clk = Period of PWM_clk * (PWM_timer1_PRESCALE + 1) + */ +#define MCPWM_TIMER1_PRESCALE 0x000000FFU +#define MCPWM_TIMER1_PRESCALE_M (MCPWM_TIMER1_PRESCALE_V << MCPWM_TIMER1_PRESCALE_S) +#define MCPWM_TIMER1_PRESCALE_V 0x000000FFU +#define MCPWM_TIMER1_PRESCALE_S 0 +/** MCPWM_TIMER1_PERIOD : R/W; bitpos: [23:8]; default: 255; + * period shadow register of PWM timer1 + */ +#define MCPWM_TIMER1_PERIOD 0x0000FFFFU +#define MCPWM_TIMER1_PERIOD_M (MCPWM_TIMER1_PERIOD_V << MCPWM_TIMER1_PERIOD_S) +#define MCPWM_TIMER1_PERIOD_V 0x0000FFFFU +#define MCPWM_TIMER1_PERIOD_S 8 +/** MCPWM_TIMER1_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; + * Update method for active register of PWM timer1 period, 0: immediate, 1: TEZ, 2: + * sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + */ +#define MCPWM_TIMER1_PERIOD_UPMETHOD 0x00000003U +#define MCPWM_TIMER1_PERIOD_UPMETHOD_M (MCPWM_TIMER1_PERIOD_UPMETHOD_V << MCPWM_TIMER1_PERIOD_UPMETHOD_S) +#define MCPWM_TIMER1_PERIOD_UPMETHOD_V 0x00000003U +#define MCPWM_TIMER1_PERIOD_UPMETHOD_S 24 + +/** MCPWM_TIMER1_CFG1_REG register + * PWM timer1 working mode and start/stop control configuration register. + */ +#define MCPWM_TIMER1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x18) +/** MCPWM_TIMER1_START : R/W/SC; bitpos: [2:0]; default: 0; + * PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ, 1: + * if timer1 starts, then stops at TEP, 2: PWM timer1 starts and runs on, 3: timer1 + * starts and stops at the next TEZ, 4: timer1 starts and stops at the next TEP. TEP + * here and below means the event that happens when the timer equals to period + */ +#define MCPWM_TIMER1_START 0x00000007U +#define MCPWM_TIMER1_START_M (MCPWM_TIMER1_START_V << MCPWM_TIMER1_START_S) +#define MCPWM_TIMER1_START_V 0x00000007U +#define MCPWM_TIMER1_START_S 0 +/** MCPWM_TIMER1_MOD : R/W; bitpos: [4:3]; default: 0; + * PWM timer1 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down + * mode + */ +#define MCPWM_TIMER1_MOD 0x00000003U +#define MCPWM_TIMER1_MOD_M (MCPWM_TIMER1_MOD_V << MCPWM_TIMER1_MOD_S) +#define MCPWM_TIMER1_MOD_V 0x00000003U +#define MCPWM_TIMER1_MOD_S 3 + +/** MCPWM_TIMER1_SYNC_REG register + * PWM timer1 sync function configuration register. + */ +#define MCPWM_TIMER1_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x1c) +/** MCPWM_TIMER1_SYNCI_EN : R/W; bitpos: [0]; default: 0; + * When set, timer reloading with phase on sync input event is enabled. + */ +#define MCPWM_TIMER1_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER1_SYNCI_EN_M (MCPWM_TIMER1_SYNCI_EN_V << MCPWM_TIMER1_SYNCI_EN_S) +#define MCPWM_TIMER1_SYNCI_EN_V 0x00000001U +#define MCPWM_TIMER1_SYNCI_EN_S 0 +/** MCPWM_TIMER1_SYNC_SW : R/W; bitpos: [1]; default: 0; + * Toggling this bit will trigger a software sync. + */ +#define MCPWM_TIMER1_SYNC_SW (BIT(1)) +#define MCPWM_TIMER1_SYNC_SW_M (MCPWM_TIMER1_SYNC_SW_V << MCPWM_TIMER1_SYNC_SW_S) +#define MCPWM_TIMER1_SYNC_SW_V 0x00000001U +#define MCPWM_TIMER1_SYNC_SW_S 1 +/** MCPWM_TIMER1_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; + * PWM timer1 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always + * generate when toggling the reg_timer1_sync_sw bit + */ +#define MCPWM_TIMER1_SYNCO_SEL 0x00000003U +#define MCPWM_TIMER1_SYNCO_SEL_M (MCPWM_TIMER1_SYNCO_SEL_V << MCPWM_TIMER1_SYNCO_SEL_S) +#define MCPWM_TIMER1_SYNCO_SEL_V 0x00000003U +#define MCPWM_TIMER1_SYNCO_SEL_S 2 +/** MCPWM_TIMER1_PHASE : R/W; bitpos: [19:4]; default: 0; + * phase for timer reload on sync event + */ +#define MCPWM_TIMER1_PHASE 0x0000FFFFU +#define MCPWM_TIMER1_PHASE_M (MCPWM_TIMER1_PHASE_V << MCPWM_TIMER1_PHASE_S) +#define MCPWM_TIMER1_PHASE_V 0x0000FFFFU +#define MCPWM_TIMER1_PHASE_S 4 +/** MCPWM_TIMER1_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; + * Configure the PWM timer1's direction when timer1 mode is up-down mode: + * 0-increase,1-decrease + */ +#define MCPWM_TIMER1_PHASE_DIRECTION (BIT(20)) +#define MCPWM_TIMER1_PHASE_DIRECTION_M (MCPWM_TIMER1_PHASE_DIRECTION_V << MCPWM_TIMER1_PHASE_DIRECTION_S) +#define MCPWM_TIMER1_PHASE_DIRECTION_V 0x00000001U +#define MCPWM_TIMER1_PHASE_DIRECTION_S 20 + +/** MCPWM_TIMER1_STATUS_REG register + * PWM timer1 status register. + */ +#define MCPWM_TIMER1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x20) +/** MCPWM_TIMER1_VALUE : RO; bitpos: [15:0]; default: 0; + * current PWM timer1 counter value + */ +#define MCPWM_TIMER1_VALUE 0x0000FFFFU +#define MCPWM_TIMER1_VALUE_M (MCPWM_TIMER1_VALUE_V << MCPWM_TIMER1_VALUE_S) +#define MCPWM_TIMER1_VALUE_V 0x0000FFFFU +#define MCPWM_TIMER1_VALUE_S 0 +/** MCPWM_TIMER1_DIRECTION : RO; bitpos: [16]; default: 0; + * current PWM timer1 counter direction, 0: increment 1: decrement + */ +#define MCPWM_TIMER1_DIRECTION (BIT(16)) +#define MCPWM_TIMER1_DIRECTION_M (MCPWM_TIMER1_DIRECTION_V << MCPWM_TIMER1_DIRECTION_S) +#define MCPWM_TIMER1_DIRECTION_V 0x00000001U +#define MCPWM_TIMER1_DIRECTION_S 16 + +/** MCPWM_TIMER2_CFG0_REG register + * PWM timer2 period and update method configuration register. + */ +#define MCPWM_TIMER2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x24) +/** MCPWM_TIMER2_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * period of PT0_clk = Period of PWM_clk * (PWM_timer2_PRESCALE + 1) + */ +#define MCPWM_TIMER2_PRESCALE 0x000000FFU +#define MCPWM_TIMER2_PRESCALE_M (MCPWM_TIMER2_PRESCALE_V << MCPWM_TIMER2_PRESCALE_S) +#define MCPWM_TIMER2_PRESCALE_V 0x000000FFU +#define MCPWM_TIMER2_PRESCALE_S 0 +/** MCPWM_TIMER2_PERIOD : R/W; bitpos: [23:8]; default: 255; + * period shadow register of PWM timer2 + */ +#define MCPWM_TIMER2_PERIOD 0x0000FFFFU +#define MCPWM_TIMER2_PERIOD_M (MCPWM_TIMER2_PERIOD_V << MCPWM_TIMER2_PERIOD_S) +#define MCPWM_TIMER2_PERIOD_V 0x0000FFFFU +#define MCPWM_TIMER2_PERIOD_S 8 +/** MCPWM_TIMER2_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; + * Update method for active register of PWM timer2 period, 0: immediate, 1: TEZ, 2: + * sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + */ +#define MCPWM_TIMER2_PERIOD_UPMETHOD 0x00000003U +#define MCPWM_TIMER2_PERIOD_UPMETHOD_M (MCPWM_TIMER2_PERIOD_UPMETHOD_V << MCPWM_TIMER2_PERIOD_UPMETHOD_S) +#define MCPWM_TIMER2_PERIOD_UPMETHOD_V 0x00000003U +#define MCPWM_TIMER2_PERIOD_UPMETHOD_S 24 + +/** MCPWM_TIMER2_CFG1_REG register + * PWM timer2 working mode and start/stop control configuration register. + */ +#define MCPWM_TIMER2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x28) +/** MCPWM_TIMER2_START : R/W/SC; bitpos: [2:0]; default: 0; + * PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ, 1: + * if timer2 starts, then stops at TEP, 2: PWM timer2 starts and runs on, 3: timer2 + * starts and stops at the next TEZ, 4: timer2 starts and stops at the next TEP. TEP + * here and below means the event that happens when the timer equals to period + */ +#define MCPWM_TIMER2_START 0x00000007U +#define MCPWM_TIMER2_START_M (MCPWM_TIMER2_START_V << MCPWM_TIMER2_START_S) +#define MCPWM_TIMER2_START_V 0x00000007U +#define MCPWM_TIMER2_START_S 0 +/** MCPWM_TIMER2_MOD : R/W; bitpos: [4:3]; default: 0; + * PWM timer2 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down + * mode + */ +#define MCPWM_TIMER2_MOD 0x00000003U +#define MCPWM_TIMER2_MOD_M (MCPWM_TIMER2_MOD_V << MCPWM_TIMER2_MOD_S) +#define MCPWM_TIMER2_MOD_V 0x00000003U +#define MCPWM_TIMER2_MOD_S 3 + +/** MCPWM_TIMER2_SYNC_REG register + * PWM timer2 sync function configuration register. + */ +#define MCPWM_TIMER2_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x2c) +/** MCPWM_TIMER2_SYNCI_EN : R/W; bitpos: [0]; default: 0; + * When set, timer reloading with phase on sync input event is enabled. + */ +#define MCPWM_TIMER2_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER2_SYNCI_EN_M (MCPWM_TIMER2_SYNCI_EN_V << MCPWM_TIMER2_SYNCI_EN_S) +#define MCPWM_TIMER2_SYNCI_EN_V 0x00000001U +#define MCPWM_TIMER2_SYNCI_EN_S 0 +/** MCPWM_TIMER2_SYNC_SW : R/W; bitpos: [1]; default: 0; + * Toggling this bit will trigger a software sync. + */ +#define MCPWM_TIMER2_SYNC_SW (BIT(1)) +#define MCPWM_TIMER2_SYNC_SW_M (MCPWM_TIMER2_SYNC_SW_V << MCPWM_TIMER2_SYNC_SW_S) +#define MCPWM_TIMER2_SYNC_SW_V 0x00000001U +#define MCPWM_TIMER2_SYNC_SW_S 1 +/** MCPWM_TIMER2_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; + * PWM timer2 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always + * generate when toggling the reg_timer0_sync_sw bit + */ +#define MCPWM_TIMER2_SYNCO_SEL 0x00000003U +#define MCPWM_TIMER2_SYNCO_SEL_M (MCPWM_TIMER2_SYNCO_SEL_V << MCPWM_TIMER2_SYNCO_SEL_S) +#define MCPWM_TIMER2_SYNCO_SEL_V 0x00000003U +#define MCPWM_TIMER2_SYNCO_SEL_S 2 +/** MCPWM_TIMER2_PHASE : R/W; bitpos: [19:4]; default: 0; + * phase for timer reload on sync event + */ +#define MCPWM_TIMER2_PHASE 0x0000FFFFU +#define MCPWM_TIMER2_PHASE_M (MCPWM_TIMER2_PHASE_V << MCPWM_TIMER2_PHASE_S) +#define MCPWM_TIMER2_PHASE_V 0x0000FFFFU +#define MCPWM_TIMER2_PHASE_S 4 +/** MCPWM_TIMER2_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; + * Configure the PWM timer2's direction when timer2 mode is up-down mode: + * 0-increase,1-decrease + */ +#define MCPWM_TIMER2_PHASE_DIRECTION (BIT(20)) +#define MCPWM_TIMER2_PHASE_DIRECTION_M (MCPWM_TIMER2_PHASE_DIRECTION_V << MCPWM_TIMER2_PHASE_DIRECTION_S) +#define MCPWM_TIMER2_PHASE_DIRECTION_V 0x00000001U +#define MCPWM_TIMER2_PHASE_DIRECTION_S 20 + +/** MCPWM_TIMER2_STATUS_REG register + * PWM timer2 status register. + */ +#define MCPWM_TIMER2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x30) +/** MCPWM_TIMER2_VALUE : RO; bitpos: [15:0]; default: 0; + * current PWM timer2 counter value + */ +#define MCPWM_TIMER2_VALUE 0x0000FFFFU +#define MCPWM_TIMER2_VALUE_M (MCPWM_TIMER2_VALUE_V << MCPWM_TIMER2_VALUE_S) +#define MCPWM_TIMER2_VALUE_V 0x0000FFFFU +#define MCPWM_TIMER2_VALUE_S 0 +/** MCPWM_TIMER2_DIRECTION : RO; bitpos: [16]; default: 0; + * current PWM timer2 counter direction, 0: increment 1: decrement + */ +#define MCPWM_TIMER2_DIRECTION (BIT(16)) +#define MCPWM_TIMER2_DIRECTION_M (MCPWM_TIMER2_DIRECTION_V << MCPWM_TIMER2_DIRECTION_S) +#define MCPWM_TIMER2_DIRECTION_V 0x00000001U +#define MCPWM_TIMER2_DIRECTION_S 16 + +/** MCPWM_TIMER_SYNCI_CFG_REG register + * Synchronization input selection for three PWM timers. + */ +#define MCPWM_TIMER_SYNCI_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x34) +/** MCPWM_TIMER0_SYNCISEL : R/W; bitpos: [2:0]; default: 0; + * select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ +#define MCPWM_TIMER0_SYNCISEL 0x00000007U +#define MCPWM_TIMER0_SYNCISEL_M (MCPWM_TIMER0_SYNCISEL_V << MCPWM_TIMER0_SYNCISEL_S) +#define MCPWM_TIMER0_SYNCISEL_V 0x00000007U +#define MCPWM_TIMER0_SYNCISEL_S 0 +/** MCPWM_TIMER1_SYNCISEL : R/W; bitpos: [5:3]; default: 0; + * select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ +#define MCPWM_TIMER1_SYNCISEL 0x00000007U +#define MCPWM_TIMER1_SYNCISEL_M (MCPWM_TIMER1_SYNCISEL_V << MCPWM_TIMER1_SYNCISEL_S) +#define MCPWM_TIMER1_SYNCISEL_V 0x00000007U +#define MCPWM_TIMER1_SYNCISEL_S 3 +/** MCPWM_TIMER2_SYNCISEL : R/W; bitpos: [8:6]; default: 0; + * select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ +#define MCPWM_TIMER2_SYNCISEL 0x00000007U +#define MCPWM_TIMER2_SYNCISEL_M (MCPWM_TIMER2_SYNCISEL_V << MCPWM_TIMER2_SYNCISEL_S) +#define MCPWM_TIMER2_SYNCISEL_V 0x00000007U +#define MCPWM_TIMER2_SYNCISEL_S 6 +/** MCPWM_EXTERNAL_SYNCI0_INVERT : R/W; bitpos: [9]; default: 0; + * invert SYNC0 from GPIO matrix + */ +#define MCPWM_EXTERNAL_SYNCI0_INVERT (BIT(9)) +#define MCPWM_EXTERNAL_SYNCI0_INVERT_M (MCPWM_EXTERNAL_SYNCI0_INVERT_V << MCPWM_EXTERNAL_SYNCI0_INVERT_S) +#define MCPWM_EXTERNAL_SYNCI0_INVERT_V 0x00000001U +#define MCPWM_EXTERNAL_SYNCI0_INVERT_S 9 +/** MCPWM_EXTERNAL_SYNCI1_INVERT : R/W; bitpos: [10]; default: 0; + * invert SYNC1 from GPIO matrix + */ +#define MCPWM_EXTERNAL_SYNCI1_INVERT (BIT(10)) +#define MCPWM_EXTERNAL_SYNCI1_INVERT_M (MCPWM_EXTERNAL_SYNCI1_INVERT_V << MCPWM_EXTERNAL_SYNCI1_INVERT_S) +#define MCPWM_EXTERNAL_SYNCI1_INVERT_V 0x00000001U +#define MCPWM_EXTERNAL_SYNCI1_INVERT_S 10 +/** MCPWM_EXTERNAL_SYNCI2_INVERT : R/W; bitpos: [11]; default: 0; + * invert SYNC2 from GPIO matrix + */ +#define MCPWM_EXTERNAL_SYNCI2_INVERT (BIT(11)) +#define MCPWM_EXTERNAL_SYNCI2_INVERT_M (MCPWM_EXTERNAL_SYNCI2_INVERT_V << MCPWM_EXTERNAL_SYNCI2_INVERT_S) +#define MCPWM_EXTERNAL_SYNCI2_INVERT_V 0x00000001U +#define MCPWM_EXTERNAL_SYNCI2_INVERT_S 11 + +/** MCPWM_OPERATOR_TIMERSEL_REG register + * Select specific timer for PWM operators. + */ +#define MCPWM_OPERATOR_TIMERSEL_REG(i) (REG_MCPWM_BASE(i) + 0x38) +/** MCPWM_OPERATOR0_TIMERSEL : R/W; bitpos: [1:0]; default: 0; + * Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: + * timer1, 2: timer2 + */ +#define MCPWM_OPERATOR0_TIMERSEL 0x00000003U +#define MCPWM_OPERATOR0_TIMERSEL_M (MCPWM_OPERATOR0_TIMERSEL_V << MCPWM_OPERATOR0_TIMERSEL_S) +#define MCPWM_OPERATOR0_TIMERSEL_V 0x00000003U +#define MCPWM_OPERATOR0_TIMERSEL_S 0 +/** MCPWM_OPERATOR1_TIMERSEL : R/W; bitpos: [3:2]; default: 0; + * Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: + * timer1, 2: timer2 + */ +#define MCPWM_OPERATOR1_TIMERSEL 0x00000003U +#define MCPWM_OPERATOR1_TIMERSEL_M (MCPWM_OPERATOR1_TIMERSEL_V << MCPWM_OPERATOR1_TIMERSEL_S) +#define MCPWM_OPERATOR1_TIMERSEL_V 0x00000003U +#define MCPWM_OPERATOR1_TIMERSEL_S 2 +/** MCPWM_OPERATOR2_TIMERSEL : R/W; bitpos: [5:4]; default: 0; + * Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: + * timer1, 2: timer2 + */ +#define MCPWM_OPERATOR2_TIMERSEL 0x00000003U +#define MCPWM_OPERATOR2_TIMERSEL_M (MCPWM_OPERATOR2_TIMERSEL_V << MCPWM_OPERATOR2_TIMERSEL_S) +#define MCPWM_OPERATOR2_TIMERSEL_V 0x00000003U +#define MCPWM_OPERATOR2_TIMERSEL_S 4 + +/** MCPWM_GEN0_STMP_CFG_REG register + * Transfer status and update method for time stamp registers A and B + */ +#define MCPWM_GEN0_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x3c) +/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 0 time stamp A's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_CMPR0_A_UPMETHOD 0x0000000FU +#define MCPWM_CMPR0_A_UPMETHOD_M (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S) +#define MCPWM_CMPR0_A_UPMETHOD_V 0x0000000FU +#define MCPWM_CMPR0_A_UPMETHOD_S 0 +/** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for PWM generator 0 time stamp B's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_CMPR0_B_UPMETHOD 0x0000000FU +#define MCPWM_CMPR0_B_UPMETHOD_M (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S) +#define MCPWM_CMPR0_B_UPMETHOD_V 0x0000000FU +#define MCPWM_CMPR0_B_UPMETHOD_S 4 +/** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is + * filled and waiting to be transferred to A's active reg. If cleared, A's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_CMPR0_A_SHDW_FULL (BIT(8)) +#define MCPWM_CMPR0_A_SHDW_FULL_M (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S) +#define MCPWM_CMPR0_A_SHDW_FULL_V 0x00000001U +#define MCPWM_CMPR0_A_SHDW_FULL_S 8 +/** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; + * Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is + * filled and waiting to be transferred to B's active reg. If cleared, B's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_CMPR0_B_SHDW_FULL (BIT(9)) +#define MCPWM_CMPR0_B_SHDW_FULL_M (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S) +#define MCPWM_CMPR0_B_SHDW_FULL_V 0x00000001U +#define MCPWM_CMPR0_B_SHDW_FULL_S 9 + +/** MCPWM_GEN0_TSTMP_A_REG register + * Shadow register for register A. + */ +#define MCPWM_GEN0_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x40) +/** MCPWM_CMPR0_A : R/W; bitpos: [15:0]; default: 0; + * PWM generator 0 time stamp A's shadow register + */ +#define MCPWM_CMPR0_A 0x0000FFFFU +#define MCPWM_CMPR0_A_M (MCPWM_CMPR0_A_V << MCPWM_CMPR0_A_S) +#define MCPWM_CMPR0_A_V 0x0000FFFFU +#define MCPWM_CMPR0_A_S 0 + +/** MCPWM_GEN0_TSTMP_B_REG register + * Shadow register for register B. + */ +#define MCPWM_GEN0_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x44) +/** MCPWM_CMPR0_B : R/W; bitpos: [15:0]; default: 0; + * PWM generator 0 time stamp B's shadow register + */ +#define MCPWM_CMPR0_B 0x0000FFFFU +#define MCPWM_CMPR0_B_M (MCPWM_CMPR0_B_V << MCPWM_CMPR0_B_S) +#define MCPWM_CMPR0_B_V 0x0000FFFFU +#define MCPWM_CMPR0_B_S 0 + +/** MCPWM_GEN0_CFG0_REG register + * Fault event T0 and T1 handling + */ +#define MCPWM_GEN0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x48) +/** MCPWM_GEN0_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 0's active register of configuration. When all bits + * are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to + * 1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update + */ +#define MCPWM_GEN0_CFG_UPMETHOD 0x0000000FU +#define MCPWM_GEN0_CFG_UPMETHOD_M (MCPWM_GEN0_CFG_UPMETHOD_V << MCPWM_GEN0_CFG_UPMETHOD_S) +#define MCPWM_GEN0_CFG_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN0_CFG_UPMETHOD_S 0 +/** MCPWM_GEN0_T0_SEL : R/W; bitpos: [6:4]; default: 0; + * Source selection for PWM generator 0 event_t0, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN0_T0_SEL 0x00000007U +#define MCPWM_GEN0_T0_SEL_M (MCPWM_GEN0_T0_SEL_V << MCPWM_GEN0_T0_SEL_S) +#define MCPWM_GEN0_T0_SEL_V 0x00000007U +#define MCPWM_GEN0_T0_SEL_S 4 +/** MCPWM_GEN0_T1_SEL : R/W; bitpos: [9:7]; default: 0; + * Source selection for PWM generator 0 event_t1, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN0_T1_SEL 0x00000007U +#define MCPWM_GEN0_T1_SEL_M (MCPWM_GEN0_T1_SEL_V << MCPWM_GEN0_T1_SEL_S) +#define MCPWM_GEN0_T1_SEL_V 0x00000007U +#define MCPWM_GEN0_T1_SEL_S 7 + +/** MCPWM_GEN0_FORCE_REG register + * Permissives to force PWM0A and PWM0B outputs by software + */ +#define MCPWM_GEN0_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x4c) +/** MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; + * Updating method for continuous software force of PWM generator0. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when + * bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, + * when bit5 is set to 1: disable update. (TEA/B here and below means an event + * generated when the timer's value equals to that of register A/B.) + */ +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD 0x0000003FU +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M (MCPWM_GEN0_CNTUFORCE_UPMETHOD_V << MCPWM_GEN0_CNTUFORCE_UPMETHOD_S) +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V 0x0000003FU +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN0_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; + * Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN0_A_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN0_A_CNTUFORCE_MODE_M (MCPWM_GEN0_A_CNTUFORCE_MODE_V << MCPWM_GEN0_A_CNTUFORCE_MODE_S) +#define MCPWM_GEN0_A_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_A_CNTUFORCE_MODE_S 6 +/** MCPWM_GEN0_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; + * Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN0_B_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN0_B_CNTUFORCE_MODE_M (MCPWM_GEN0_B_CNTUFORCE_MODE_V << MCPWM_GEN0_B_CNTUFORCE_MODE_S) +#define MCPWM_GEN0_B_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_B_CNTUFORCE_MODE_S 8 +/** MCPWM_GEN0_A_NCIFORCE : R/W; bitpos: [10]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM0A, a toggle will + * trigger a force event. + */ +#define MCPWM_GEN0_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN0_A_NCIFORCE_M (MCPWM_GEN0_A_NCIFORCE_V << MCPWM_GEN0_A_NCIFORCE_S) +#define MCPWM_GEN0_A_NCIFORCE_V 0x00000001U +#define MCPWM_GEN0_A_NCIFORCE_S 10 +/** MCPWM_GEN0_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; + * non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN0_A_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN0_A_NCIFORCE_MODE_M (MCPWM_GEN0_A_NCIFORCE_MODE_V << MCPWM_GEN0_A_NCIFORCE_MODE_S) +#define MCPWM_GEN0_A_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_A_NCIFORCE_MODE_S 11 +/** MCPWM_GEN0_B_NCIFORCE : R/W; bitpos: [13]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM0B, a toggle will + * trigger a force event. + */ +#define MCPWM_GEN0_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN0_B_NCIFORCE_M (MCPWM_GEN0_B_NCIFORCE_V << MCPWM_GEN0_B_NCIFORCE_S) +#define MCPWM_GEN0_B_NCIFORCE_V 0x00000001U +#define MCPWM_GEN0_B_NCIFORCE_S 13 +/** MCPWM_GEN0_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; + * non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN0_B_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN0_B_NCIFORCE_MODE_M (MCPWM_GEN0_B_NCIFORCE_MODE_V << MCPWM_GEN0_B_NCIFORCE_MODE_S) +#define MCPWM_GEN0_B_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_B_NCIFORCE_MODE_S 14 + +/** MCPWM_GEN0_A_REG register + * Actions triggered by events on PWM0A + */ +#define MCPWM_GEN0_A_REG(i) (REG_MCPWM_BASE(i) + 0x50) +/** MCPWM_GEN0_A_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM0A triggered by event TEZ when timer increasing + */ +#define MCPWM_GEN0_A_UTEZ 0x00000003U +#define MCPWM_GEN0_A_UTEZ_M (MCPWM_GEN0_A_UTEZ_V << MCPWM_GEN0_A_UTEZ_S) +#define MCPWM_GEN0_A_UTEZ_V 0x00000003U +#define MCPWM_GEN0_A_UTEZ_S 0 +/** MCPWM_GEN0_A_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM0A triggered by event TEP when timer increasing + */ +#define MCPWM_GEN0_A_UTEP 0x00000003U +#define MCPWM_GEN0_A_UTEP_M (MCPWM_GEN0_A_UTEP_V << MCPWM_GEN0_A_UTEP_S) +#define MCPWM_GEN0_A_UTEP_V 0x00000003U +#define MCPWM_GEN0_A_UTEP_S 2 +/** MCPWM_GEN0_A_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM0A triggered by event TEA when timer increasing + */ +#define MCPWM_GEN0_A_UTEA 0x00000003U +#define MCPWM_GEN0_A_UTEA_M (MCPWM_GEN0_A_UTEA_V << MCPWM_GEN0_A_UTEA_S) +#define MCPWM_GEN0_A_UTEA_V 0x00000003U +#define MCPWM_GEN0_A_UTEA_S 4 +/** MCPWM_GEN0_A_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM0A triggered by event TEB when timer increasing + */ +#define MCPWM_GEN0_A_UTEB 0x00000003U +#define MCPWM_GEN0_A_UTEB_M (MCPWM_GEN0_A_UTEB_V << MCPWM_GEN0_A_UTEB_S) +#define MCPWM_GEN0_A_UTEB_V 0x00000003U +#define MCPWM_GEN0_A_UTEB_S 6 +/** MCPWM_GEN0_A_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM0A triggered by event_t0 when timer increasing + */ +#define MCPWM_GEN0_A_UT0 0x00000003U +#define MCPWM_GEN0_A_UT0_M (MCPWM_GEN0_A_UT0_V << MCPWM_GEN0_A_UT0_S) +#define MCPWM_GEN0_A_UT0_V 0x00000003U +#define MCPWM_GEN0_A_UT0_S 8 +/** MCPWM_GEN0_A_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM0A triggered by event_t1 when timer increasing + */ +#define MCPWM_GEN0_A_UT1 0x00000003U +#define MCPWM_GEN0_A_UT1_M (MCPWM_GEN0_A_UT1_V << MCPWM_GEN0_A_UT1_S) +#define MCPWM_GEN0_A_UT1_V 0x00000003U +#define MCPWM_GEN0_A_UT1_S 10 +/** MCPWM_GEN0_A_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM0A triggered by event TEZ when timer decreasing + */ +#define MCPWM_GEN0_A_DTEZ 0x00000003U +#define MCPWM_GEN0_A_DTEZ_M (MCPWM_GEN0_A_DTEZ_V << MCPWM_GEN0_A_DTEZ_S) +#define MCPWM_GEN0_A_DTEZ_V 0x00000003U +#define MCPWM_GEN0_A_DTEZ_S 12 +/** MCPWM_GEN0_A_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM0A triggered by event TEP when timer decreasing + */ +#define MCPWM_GEN0_A_DTEP 0x00000003U +#define MCPWM_GEN0_A_DTEP_M (MCPWM_GEN0_A_DTEP_V << MCPWM_GEN0_A_DTEP_S) +#define MCPWM_GEN0_A_DTEP_V 0x00000003U +#define MCPWM_GEN0_A_DTEP_S 14 +/** MCPWM_GEN0_A_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM0A triggered by event TEA when timer decreasing + */ +#define MCPWM_GEN0_A_DTEA 0x00000003U +#define MCPWM_GEN0_A_DTEA_M (MCPWM_GEN0_A_DTEA_V << MCPWM_GEN0_A_DTEA_S) +#define MCPWM_GEN0_A_DTEA_V 0x00000003U +#define MCPWM_GEN0_A_DTEA_S 16 +/** MCPWM_GEN0_A_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM0A triggered by event TEB when timer decreasing + */ +#define MCPWM_GEN0_A_DTEB 0x00000003U +#define MCPWM_GEN0_A_DTEB_M (MCPWM_GEN0_A_DTEB_V << MCPWM_GEN0_A_DTEB_S) +#define MCPWM_GEN0_A_DTEB_V 0x00000003U +#define MCPWM_GEN0_A_DTEB_S 18 +/** MCPWM_GEN0_A_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM0A triggered by event_t0 when timer decreasing + */ +#define MCPWM_GEN0_A_DT0 0x00000003U +#define MCPWM_GEN0_A_DT0_M (MCPWM_GEN0_A_DT0_V << MCPWM_GEN0_A_DT0_S) +#define MCPWM_GEN0_A_DT0_V 0x00000003U +#define MCPWM_GEN0_A_DT0_S 20 +/** MCPWM_GEN0_A_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_A_DT1 0x00000003U +#define MCPWM_GEN0_A_DT1_M (MCPWM_GEN0_A_DT1_V << MCPWM_GEN0_A_DT1_S) +#define MCPWM_GEN0_A_DT1_V 0x00000003U +#define MCPWM_GEN0_A_DT1_S 22 + +/** MCPWM_GEN0_B_REG register + * Actions triggered by events on PWM0B + */ +#define MCPWM_GEN0_B_REG(i) (REG_MCPWM_BASE(i) + 0x54) +/** MCPWM_GEN0_B_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM0B triggered by event TEZ when timer increasing + */ +#define MCPWM_GEN0_B_UTEZ 0x00000003U +#define MCPWM_GEN0_B_UTEZ_M (MCPWM_GEN0_B_UTEZ_V << MCPWM_GEN0_B_UTEZ_S) +#define MCPWM_GEN0_B_UTEZ_V 0x00000003U +#define MCPWM_GEN0_B_UTEZ_S 0 +/** MCPWM_GEN0_B_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM0B triggered by event TEP when timer increasing + */ +#define MCPWM_GEN0_B_UTEP 0x00000003U +#define MCPWM_GEN0_B_UTEP_M (MCPWM_GEN0_B_UTEP_V << MCPWM_GEN0_B_UTEP_S) +#define MCPWM_GEN0_B_UTEP_V 0x00000003U +#define MCPWM_GEN0_B_UTEP_S 2 +/** MCPWM_GEN0_B_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM0B triggered by event TEA when timer increasing + */ +#define MCPWM_GEN0_B_UTEA 0x00000003U +#define MCPWM_GEN0_B_UTEA_M (MCPWM_GEN0_B_UTEA_V << MCPWM_GEN0_B_UTEA_S) +#define MCPWM_GEN0_B_UTEA_V 0x00000003U +#define MCPWM_GEN0_B_UTEA_S 4 +/** MCPWM_GEN0_B_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM0B triggered by event TEB when timer increasing + */ +#define MCPWM_GEN0_B_UTEB 0x00000003U +#define MCPWM_GEN0_B_UTEB_M (MCPWM_GEN0_B_UTEB_V << MCPWM_GEN0_B_UTEB_S) +#define MCPWM_GEN0_B_UTEB_V 0x00000003U +#define MCPWM_GEN0_B_UTEB_S 6 +/** MCPWM_GEN0_B_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM0B triggered by event_t0 when timer increasing + */ +#define MCPWM_GEN0_B_UT0 0x00000003U +#define MCPWM_GEN0_B_UT0_M (MCPWM_GEN0_B_UT0_V << MCPWM_GEN0_B_UT0_S) +#define MCPWM_GEN0_B_UT0_V 0x00000003U +#define MCPWM_GEN0_B_UT0_S 8 +/** MCPWM_GEN0_B_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM0B triggered by event_t1 when timer increasing + */ +#define MCPWM_GEN0_B_UT1 0x00000003U +#define MCPWM_GEN0_B_UT1_M (MCPWM_GEN0_B_UT1_V << MCPWM_GEN0_B_UT1_S) +#define MCPWM_GEN0_B_UT1_V 0x00000003U +#define MCPWM_GEN0_B_UT1_S 10 +/** MCPWM_GEN0_B_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM0B triggered by event TEZ when timer decreasing + */ +#define MCPWM_GEN0_B_DTEZ 0x00000003U +#define MCPWM_GEN0_B_DTEZ_M (MCPWM_GEN0_B_DTEZ_V << MCPWM_GEN0_B_DTEZ_S) +#define MCPWM_GEN0_B_DTEZ_V 0x00000003U +#define MCPWM_GEN0_B_DTEZ_S 12 +/** MCPWM_GEN0_B_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM0B triggered by event TEP when timer decreasing + */ +#define MCPWM_GEN0_B_DTEP 0x00000003U +#define MCPWM_GEN0_B_DTEP_M (MCPWM_GEN0_B_DTEP_V << MCPWM_GEN0_B_DTEP_S) +#define MCPWM_GEN0_B_DTEP_V 0x00000003U +#define MCPWM_GEN0_B_DTEP_S 14 +/** MCPWM_GEN0_B_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM0B triggered by event TEA when timer decreasing + */ +#define MCPWM_GEN0_B_DTEA 0x00000003U +#define MCPWM_GEN0_B_DTEA_M (MCPWM_GEN0_B_DTEA_V << MCPWM_GEN0_B_DTEA_S) +#define MCPWM_GEN0_B_DTEA_V 0x00000003U +#define MCPWM_GEN0_B_DTEA_S 16 +/** MCPWM_GEN0_B_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM0B triggered by event TEB when timer decreasing + */ +#define MCPWM_GEN0_B_DTEB 0x00000003U +#define MCPWM_GEN0_B_DTEB_M (MCPWM_GEN0_B_DTEB_V << MCPWM_GEN0_B_DTEB_S) +#define MCPWM_GEN0_B_DTEB_V 0x00000003U +#define MCPWM_GEN0_B_DTEB_S 18 +/** MCPWM_GEN0_B_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM0B triggered by event_t0 when timer decreasing + */ +#define MCPWM_GEN0_B_DT0 0x00000003U +#define MCPWM_GEN0_B_DT0_M (MCPWM_GEN0_B_DT0_V << MCPWM_GEN0_B_DT0_S) +#define MCPWM_GEN0_B_DT0_V 0x00000003U +#define MCPWM_GEN0_B_DT0_S 20 +/** MCPWM_GEN0_B_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM0B triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN0_B_DT1 0x00000003U +#define MCPWM_GEN0_B_DT1_M (MCPWM_GEN0_B_DT1_V << MCPWM_GEN0_B_DT1_S) +#define MCPWM_GEN0_B_DT1_V 0x00000003U +#define MCPWM_GEN0_B_DT1_S 22 + +/** MCPWM_DT0_CFG_REG register + * dead time type selection and configuration + */ +#define MCPWM_DT0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x58) +/** MCPWM_DB0_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for FED (rising edge delay) active register. 0: immediate, when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DB0_FED_UPMETHOD 0x0000000FU +#define MCPWM_DB0_FED_UPMETHOD_M (MCPWM_DB0_FED_UPMETHOD_V << MCPWM_DB0_FED_UPMETHOD_S) +#define MCPWM_DB0_FED_UPMETHOD_V 0x0000000FU +#define MCPWM_DB0_FED_UPMETHOD_S 0 +/** MCPWM_DB0_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for RED (rising edge delay) active register. 0: immediate, when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DB0_RED_UPMETHOD 0x0000000FU +#define MCPWM_DB0_RED_UPMETHOD_M (MCPWM_DB0_RED_UPMETHOD_V << MCPWM_DB0_RED_UPMETHOD_S) +#define MCPWM_DB0_RED_UPMETHOD_V 0x0000000FU +#define MCPWM_DB0_RED_UPMETHOD_S 4 +/** MCPWM_DB0_DEB_MODE : R/W; bitpos: [8]; default: 0; + * S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, + * 1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ +#define MCPWM_DB0_DEB_MODE (BIT(8)) +#define MCPWM_DB0_DEB_MODE_M (MCPWM_DB0_DEB_MODE_V << MCPWM_DB0_DEB_MODE_S) +#define MCPWM_DB0_DEB_MODE_V 0x00000001U +#define MCPWM_DB0_DEB_MODE_S 8 +/** MCPWM_DB0_A_OUTSWAP : R/W; bitpos: [9]; default: 0; + * S6 in table + */ +#define MCPWM_DB0_A_OUTSWAP (BIT(9)) +#define MCPWM_DB0_A_OUTSWAP_M (MCPWM_DB0_A_OUTSWAP_V << MCPWM_DB0_A_OUTSWAP_S) +#define MCPWM_DB0_A_OUTSWAP_V 0x00000001U +#define MCPWM_DB0_A_OUTSWAP_S 9 +/** MCPWM_DB0_B_OUTSWAP : R/W; bitpos: [10]; default: 0; + * S7 in table + */ +#define MCPWM_DB0_B_OUTSWAP (BIT(10)) +#define MCPWM_DB0_B_OUTSWAP_M (MCPWM_DB0_B_OUTSWAP_V << MCPWM_DB0_B_OUTSWAP_S) +#define MCPWM_DB0_B_OUTSWAP_V 0x00000001U +#define MCPWM_DB0_B_OUTSWAP_S 10 +/** MCPWM_DB0_RED_INSEL : R/W; bitpos: [11]; default: 0; + * S4 in table + */ +#define MCPWM_DB0_RED_INSEL (BIT(11)) +#define MCPWM_DB0_RED_INSEL_M (MCPWM_DB0_RED_INSEL_V << MCPWM_DB0_RED_INSEL_S) +#define MCPWM_DB0_RED_INSEL_V 0x00000001U +#define MCPWM_DB0_RED_INSEL_S 11 +/** MCPWM_DB0_FED_INSEL : R/W; bitpos: [12]; default: 0; + * S5 in table + */ +#define MCPWM_DB0_FED_INSEL (BIT(12)) +#define MCPWM_DB0_FED_INSEL_M (MCPWM_DB0_FED_INSEL_V << MCPWM_DB0_FED_INSEL_S) +#define MCPWM_DB0_FED_INSEL_V 0x00000001U +#define MCPWM_DB0_FED_INSEL_S 12 +/** MCPWM_DB0_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; + * S2 in table + */ +#define MCPWM_DB0_RED_OUTINVERT (BIT(13)) +#define MCPWM_DB0_RED_OUTINVERT_M (MCPWM_DB0_RED_OUTINVERT_V << MCPWM_DB0_RED_OUTINVERT_S) +#define MCPWM_DB0_RED_OUTINVERT_V 0x00000001U +#define MCPWM_DB0_RED_OUTINVERT_S 13 +/** MCPWM_DB0_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; + * S3 in table + */ +#define MCPWM_DB0_FED_OUTINVERT (BIT(14)) +#define MCPWM_DB0_FED_OUTINVERT_M (MCPWM_DB0_FED_OUTINVERT_V << MCPWM_DB0_FED_OUTINVERT_S) +#define MCPWM_DB0_FED_OUTINVERT_V 0x00000001U +#define MCPWM_DB0_FED_OUTINVERT_S 14 +/** MCPWM_DB0_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; + * S1 in table + */ +#define MCPWM_DB0_A_OUTBYPASS (BIT(15)) +#define MCPWM_DB0_A_OUTBYPASS_M (MCPWM_DB0_A_OUTBYPASS_V << MCPWM_DB0_A_OUTBYPASS_S) +#define MCPWM_DB0_A_OUTBYPASS_V 0x00000001U +#define MCPWM_DB0_A_OUTBYPASS_S 15 +/** MCPWM_DB0_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; + * S0 in table + */ +#define MCPWM_DB0_B_OUTBYPASS (BIT(16)) +#define MCPWM_DB0_B_OUTBYPASS_M (MCPWM_DB0_B_OUTBYPASS_V << MCPWM_DB0_B_OUTBYPASS_S) +#define MCPWM_DB0_B_OUTBYPASS_V 0x00000001U +#define MCPWM_DB0_B_OUTBYPASS_S 16 +/** MCPWM_DB0_CLK_SEL : R/W; bitpos: [17]; default: 0; + * Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk + */ +#define MCPWM_DB0_CLK_SEL (BIT(17)) +#define MCPWM_DB0_CLK_SEL_M (MCPWM_DB0_CLK_SEL_V << MCPWM_DB0_CLK_SEL_S) +#define MCPWM_DB0_CLK_SEL_V 0x00000001U +#define MCPWM_DB0_CLK_SEL_S 17 + +/** MCPWM_DT0_FED_CFG_REG register + * Shadow register for falling edge delay (FED). + */ +#define MCPWM_DT0_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x5c) +/** MCPWM_DB0_FED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for FED + */ +#define MCPWM_DB0_FED 0x0000FFFFU +#define MCPWM_DB0_FED_M (MCPWM_DB0_FED_V << MCPWM_DB0_FED_S) +#define MCPWM_DB0_FED_V 0x0000FFFFU +#define MCPWM_DB0_FED_S 0 + +/** MCPWM_DT0_RED_CFG_REG register + * Shadow register for rising edge delay (RED). + */ +#define MCPWM_DT0_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x60) +/** MCPWM_DB0_RED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for RED + */ +#define MCPWM_DB0_RED 0x0000FFFFU +#define MCPWM_DB0_RED_M (MCPWM_DB0_RED_V << MCPWM_DB0_RED_S) +#define MCPWM_DB0_RED_V 0x0000FFFFU +#define MCPWM_DB0_RED_S 0 + +/** MCPWM_CARRIER0_CFG_REG register + * Carrier enable and configuratoin + */ +#define MCPWM_CARRIER0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x64) +/** MCPWM_CHOPPER0_EN : R/W; bitpos: [0]; default: 0; + * When set, carrier0 function is enabled. When cleared, carrier0 is bypassed + */ +#define MCPWM_CHOPPER0_EN (BIT(0)) +#define MCPWM_CHOPPER0_EN_M (MCPWM_CHOPPER0_EN_V << MCPWM_CHOPPER0_EN_S) +#define MCPWM_CHOPPER0_EN_V 0x00000001U +#define MCPWM_CHOPPER0_EN_S 0 +/** MCPWM_CHOPPER0_PRESCALE : R/W; bitpos: [4:1]; default: 0; + * PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * + * (PWM_CARRIER0_PRESCALE + 1) + */ +#define MCPWM_CHOPPER0_PRESCALE 0x0000000FU +#define MCPWM_CHOPPER0_PRESCALE_M (MCPWM_CHOPPER0_PRESCALE_V << MCPWM_CHOPPER0_PRESCALE_S) +#define MCPWM_CHOPPER0_PRESCALE_V 0x0000000FU +#define MCPWM_CHOPPER0_PRESCALE_S 1 +/** MCPWM_CHOPPER0_DUTY : R/W; bitpos: [7:5]; default: 0; + * carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + */ +#define MCPWM_CHOPPER0_DUTY 0x00000007U +#define MCPWM_CHOPPER0_DUTY_M (MCPWM_CHOPPER0_DUTY_V << MCPWM_CHOPPER0_DUTY_S) +#define MCPWM_CHOPPER0_DUTY_V 0x00000007U +#define MCPWM_CHOPPER0_DUTY_S 5 +/** MCPWM_CHOPPER0_OSHTWTH : R/W; bitpos: [11:8]; default: 0; + * width of the first pulse in number of periods of the carrier + */ +#define MCPWM_CHOPPER0_OSHTWTH 0x0000000FU +#define MCPWM_CHOPPER0_OSHTWTH_M (MCPWM_CHOPPER0_OSHTWTH_V << MCPWM_CHOPPER0_OSHTWTH_S) +#define MCPWM_CHOPPER0_OSHTWTH_V 0x0000000FU +#define MCPWM_CHOPPER0_OSHTWTH_S 8 +/** MCPWM_CHOPPER0_OUT_INVERT : R/W; bitpos: [12]; default: 0; + * when set, invert the output of PWM0A and PWM0B for this submodule + */ +#define MCPWM_CHOPPER0_OUT_INVERT (BIT(12)) +#define MCPWM_CHOPPER0_OUT_INVERT_M (MCPWM_CHOPPER0_OUT_INVERT_V << MCPWM_CHOPPER0_OUT_INVERT_S) +#define MCPWM_CHOPPER0_OUT_INVERT_V 0x00000001U +#define MCPWM_CHOPPER0_OUT_INVERT_S 12 +/** MCPWM_CHOPPER0_IN_INVERT : R/W; bitpos: [13]; default: 0; + * when set, invert the input of PWM0A and PWM0B for this submodule + */ +#define MCPWM_CHOPPER0_IN_INVERT (BIT(13)) +#define MCPWM_CHOPPER0_IN_INVERT_M (MCPWM_CHOPPER0_IN_INVERT_V << MCPWM_CHOPPER0_IN_INVERT_S) +#define MCPWM_CHOPPER0_IN_INVERT_V 0x00000001U +#define MCPWM_CHOPPER0_IN_INVERT_S 13 + +/** MCPWM_FH0_CFG0_REG register + * Actions on PWM0A and PWM0B trip events + */ +#define MCPWM_FH0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x68) +/** MCPWM_TZ0_SW_CBC : R/W; bitpos: [0]; default: 0; + * Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ0_SW_CBC (BIT(0)) +#define MCPWM_TZ0_SW_CBC_M (MCPWM_TZ0_SW_CBC_V << MCPWM_TZ0_SW_CBC_S) +#define MCPWM_TZ0_SW_CBC_V 0x00000001U +#define MCPWM_TZ0_SW_CBC_S 0 +/** MCPWM_TZ0_F2_CBC : R/W; bitpos: [1]; default: 0; + * event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ0_F2_CBC (BIT(1)) +#define MCPWM_TZ0_F2_CBC_M (MCPWM_TZ0_F2_CBC_V << MCPWM_TZ0_F2_CBC_S) +#define MCPWM_TZ0_F2_CBC_V 0x00000001U +#define MCPWM_TZ0_F2_CBC_S 1 +/** MCPWM_TZ0_F1_CBC : R/W; bitpos: [2]; default: 0; + * event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ0_F1_CBC (BIT(2)) +#define MCPWM_TZ0_F1_CBC_M (MCPWM_TZ0_F1_CBC_V << MCPWM_TZ0_F1_CBC_S) +#define MCPWM_TZ0_F1_CBC_V 0x00000001U +#define MCPWM_TZ0_F1_CBC_S 2 +/** MCPWM_TZ0_F0_CBC : R/W; bitpos: [3]; default: 0; + * event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ0_F0_CBC (BIT(3)) +#define MCPWM_TZ0_F0_CBC_M (MCPWM_TZ0_F0_CBC_V << MCPWM_TZ0_F0_CBC_S) +#define MCPWM_TZ0_F0_CBC_V 0x00000001U +#define MCPWM_TZ0_F0_CBC_S 3 +/** MCPWM_TZ0_SW_OST : R/W; bitpos: [4]; default: 0; + * Enable register for software force one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ0_SW_OST (BIT(4)) +#define MCPWM_TZ0_SW_OST_M (MCPWM_TZ0_SW_OST_V << MCPWM_TZ0_SW_OST_S) +#define MCPWM_TZ0_SW_OST_V 0x00000001U +#define MCPWM_TZ0_SW_OST_S 4 +/** MCPWM_TZ0_F2_OST : R/W; bitpos: [5]; default: 0; + * event_f2 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ0_F2_OST (BIT(5)) +#define MCPWM_TZ0_F2_OST_M (MCPWM_TZ0_F2_OST_V << MCPWM_TZ0_F2_OST_S) +#define MCPWM_TZ0_F2_OST_V 0x00000001U +#define MCPWM_TZ0_F2_OST_S 5 +/** MCPWM_TZ0_F1_OST : R/W; bitpos: [6]; default: 0; + * event_f1 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ0_F1_OST (BIT(6)) +#define MCPWM_TZ0_F1_OST_M (MCPWM_TZ0_F1_OST_V << MCPWM_TZ0_F1_OST_S) +#define MCPWM_TZ0_F1_OST_V 0x00000001U +#define MCPWM_TZ0_F1_OST_S 6 +/** MCPWM_TZ0_F0_OST : R/W; bitpos: [7]; default: 0; + * event_f0 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ0_F0_OST (BIT(7)) +#define MCPWM_TZ0_F0_OST_M (MCPWM_TZ0_F0_OST_V << MCPWM_TZ0_F0_OST_S) +#define MCPWM_TZ0_F0_OST_V 0x00000001U +#define MCPWM_TZ0_F0_OST_S 7 +/** MCPWM_TZ0_A_CBC_D : R/W; bitpos: [9:8]; default: 0; + * Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ0_A_CBC_D 0x00000003U +#define MCPWM_TZ0_A_CBC_D_M (MCPWM_TZ0_A_CBC_D_V << MCPWM_TZ0_A_CBC_D_S) +#define MCPWM_TZ0_A_CBC_D_V 0x00000003U +#define MCPWM_TZ0_A_CBC_D_S 8 +/** MCPWM_TZ0_A_CBC_U : R/W; bitpos: [11:10]; default: 0; + * Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ0_A_CBC_U 0x00000003U +#define MCPWM_TZ0_A_CBC_U_M (MCPWM_TZ0_A_CBC_U_V << MCPWM_TZ0_A_CBC_U_S) +#define MCPWM_TZ0_A_CBC_U_V 0x00000003U +#define MCPWM_TZ0_A_CBC_U_S 10 +/** MCPWM_TZ0_A_OST_D : R/W; bitpos: [13:12]; default: 0; + * One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ0_A_OST_D 0x00000003U +#define MCPWM_TZ0_A_OST_D_M (MCPWM_TZ0_A_OST_D_V << MCPWM_TZ0_A_OST_D_S) +#define MCPWM_TZ0_A_OST_D_V 0x00000003U +#define MCPWM_TZ0_A_OST_D_S 12 +/** MCPWM_TZ0_A_OST_U : R/W; bitpos: [15:14]; default: 0; + * One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ0_A_OST_U 0x00000003U +#define MCPWM_TZ0_A_OST_U_M (MCPWM_TZ0_A_OST_U_V << MCPWM_TZ0_A_OST_U_S) +#define MCPWM_TZ0_A_OST_U_V 0x00000003U +#define MCPWM_TZ0_A_OST_U_S 14 +/** MCPWM_TZ0_B_CBC_D : R/W; bitpos: [17:16]; default: 0; + * Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ0_B_CBC_D 0x00000003U +#define MCPWM_TZ0_B_CBC_D_M (MCPWM_TZ0_B_CBC_D_V << MCPWM_TZ0_B_CBC_D_S) +#define MCPWM_TZ0_B_CBC_D_V 0x00000003U +#define MCPWM_TZ0_B_CBC_D_S 16 +/** MCPWM_TZ0_B_CBC_U : R/W; bitpos: [19:18]; default: 0; + * Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is + * increasing. 0: do nothing,1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ0_B_CBC_U 0x00000003U +#define MCPWM_TZ0_B_CBC_U_M (MCPWM_TZ0_B_CBC_U_V << MCPWM_TZ0_B_CBC_U_S) +#define MCPWM_TZ0_B_CBC_U_V 0x00000003U +#define MCPWM_TZ0_B_CBC_U_S 18 +/** MCPWM_TZ0_B_OST_D : R/W; bitpos: [21:20]; default: 0; + * One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ0_B_OST_D 0x00000003U +#define MCPWM_TZ0_B_OST_D_M (MCPWM_TZ0_B_OST_D_V << MCPWM_TZ0_B_OST_D_S) +#define MCPWM_TZ0_B_OST_D_V 0x00000003U +#define MCPWM_TZ0_B_OST_D_S 20 +/** MCPWM_TZ0_B_OST_U : R/W; bitpos: [23:22]; default: 0; + * One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ0_B_OST_U 0x00000003U +#define MCPWM_TZ0_B_OST_U_M (MCPWM_TZ0_B_OST_U_V << MCPWM_TZ0_B_OST_U_S) +#define MCPWM_TZ0_B_OST_U_V 0x00000003U +#define MCPWM_TZ0_B_OST_U_S 22 + +/** MCPWM_FH0_CFG1_REG register + * Software triggers for fault handler actions + */ +#define MCPWM_FH0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x6c) +/** MCPWM_TZ0_CLR_OST : R/W; bitpos: [0]; default: 0; + * a rising edge will clear on going one-shot mode action + */ +#define MCPWM_TZ0_CLR_OST (BIT(0)) +#define MCPWM_TZ0_CLR_OST_M (MCPWM_TZ0_CLR_OST_V << MCPWM_TZ0_CLR_OST_S) +#define MCPWM_TZ0_CLR_OST_V 0x00000001U +#define MCPWM_TZ0_CLR_OST_S 0 +/** MCPWM_TZ0_CBCPULSE : R/W; bitpos: [2:1]; default: 0; + * cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, + * when bit1 is set to 1:TEP + */ +#define MCPWM_TZ0_CBCPULSE 0x00000003U +#define MCPWM_TZ0_CBCPULSE_M (MCPWM_TZ0_CBCPULSE_V << MCPWM_TZ0_CBCPULSE_S) +#define MCPWM_TZ0_CBCPULSE_V 0x00000003U +#define MCPWM_TZ0_CBCPULSE_S 1 +/** MCPWM_TZ0_FORCE_CBC : R/W; bitpos: [3]; default: 0; + * a toggle trigger a cycle-by-cycle mode action + */ +#define MCPWM_TZ0_FORCE_CBC (BIT(3)) +#define MCPWM_TZ0_FORCE_CBC_M (MCPWM_TZ0_FORCE_CBC_V << MCPWM_TZ0_FORCE_CBC_S) +#define MCPWM_TZ0_FORCE_CBC_V 0x00000001U +#define MCPWM_TZ0_FORCE_CBC_S 3 +/** MCPWM_TZ0_FORCE_OST : R/W; bitpos: [4]; default: 0; + * a toggle (software negate its value) triggers a one-shot mode action + */ +#define MCPWM_TZ0_FORCE_OST (BIT(4)) +#define MCPWM_TZ0_FORCE_OST_M (MCPWM_TZ0_FORCE_OST_V << MCPWM_TZ0_FORCE_OST_S) +#define MCPWM_TZ0_FORCE_OST_V 0x00000001U +#define MCPWM_TZ0_FORCE_OST_S 4 + +/** MCPWM_FH0_STATUS_REG register + * Status of fault events. + */ +#define MCPWM_FH0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x70) +/** MCPWM_TZ0_CBC_ON : RO; bitpos: [0]; default: 0; + * Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + */ +#define MCPWM_TZ0_CBC_ON (BIT(0)) +#define MCPWM_TZ0_CBC_ON_M (MCPWM_TZ0_CBC_ON_V << MCPWM_TZ0_CBC_ON_S) +#define MCPWM_TZ0_CBC_ON_V 0x00000001U +#define MCPWM_TZ0_CBC_ON_S 0 +/** MCPWM_TZ0_OST_ON : RO; bitpos: [1]; default: 0; + * Set and reset by hardware. If set, an one-shot mode action is on going + */ +#define MCPWM_TZ0_OST_ON (BIT(1)) +#define MCPWM_TZ0_OST_ON_M (MCPWM_TZ0_OST_ON_V << MCPWM_TZ0_OST_ON_S) +#define MCPWM_TZ0_OST_ON_V 0x00000001U +#define MCPWM_TZ0_OST_ON_S 1 + +/** MCPWM_GEN1_STMP_CFG_REG register + * Transfer status and update method for time stamp registers A and B + */ +#define MCPWM_GEN1_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x74) +/** MCPWM_CMPR1_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 1 time stamp A's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_CMPR1_A_UPMETHOD 0x0000000FU +#define MCPWM_CMPR1_A_UPMETHOD_M (MCPWM_CMPR1_A_UPMETHOD_V << MCPWM_CMPR1_A_UPMETHOD_S) +#define MCPWM_CMPR1_A_UPMETHOD_V 0x0000000FU +#define MCPWM_CMPR1_A_UPMETHOD_S 0 +/** MCPWM_CMPR1_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for PWM generator 1 time stamp B's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_CMPR1_B_UPMETHOD 0x0000000FU +#define MCPWM_CMPR1_B_UPMETHOD_M (MCPWM_CMPR1_B_UPMETHOD_V << MCPWM_CMPR1_B_UPMETHOD_S) +#define MCPWM_CMPR1_B_UPMETHOD_V 0x0000000FU +#define MCPWM_CMPR1_B_UPMETHOD_S 4 +/** MCPWM_CMPR1_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is + * filled and waiting to be transferred to A's active reg. If cleared, A's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_CMPR1_A_SHDW_FULL (BIT(8)) +#define MCPWM_CMPR1_A_SHDW_FULL_M (MCPWM_CMPR1_A_SHDW_FULL_V << MCPWM_CMPR1_A_SHDW_FULL_S) +#define MCPWM_CMPR1_A_SHDW_FULL_V 0x00000001U +#define MCPWM_CMPR1_A_SHDW_FULL_S 8 +/** MCPWM_CMPR1_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; + * Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is + * filled and waiting to be transferred to B's active reg. If cleared, B's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_CMPR1_B_SHDW_FULL (BIT(9)) +#define MCPWM_CMPR1_B_SHDW_FULL_M (MCPWM_CMPR1_B_SHDW_FULL_V << MCPWM_CMPR1_B_SHDW_FULL_S) +#define MCPWM_CMPR1_B_SHDW_FULL_V 0x00000001U +#define MCPWM_CMPR1_B_SHDW_FULL_S 9 + +/** MCPWM_GEN1_TSTMP_A_REG register + * Shadow register for register A. + */ +#define MCPWM_GEN1_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x78) +/** MCPWM_CMPR1_A : R/W; bitpos: [15:0]; default: 0; + * PWM generator 1 time stamp A's shadow register + */ +#define MCPWM_CMPR1_A 0x0000FFFFU +#define MCPWM_CMPR1_A_M (MCPWM_CMPR1_A_V << MCPWM_CMPR1_A_S) +#define MCPWM_CMPR1_A_V 0x0000FFFFU +#define MCPWM_CMPR1_A_S 0 + +/** MCPWM_GEN1_TSTMP_B_REG register + * Shadow register for register B. + */ +#define MCPWM_GEN1_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x7c) +/** MCPWM_CMPR1_B : R/W; bitpos: [15:0]; default: 0; + * PWM generator 1 time stamp B's shadow register + */ +#define MCPWM_CMPR1_B 0x0000FFFFU +#define MCPWM_CMPR1_B_M (MCPWM_CMPR1_B_V << MCPWM_CMPR1_B_S) +#define MCPWM_CMPR1_B_V 0x0000FFFFU +#define MCPWM_CMPR1_B_S 0 + +/** MCPWM_GEN1_CFG0_REG register + * Fault event T0 and T1 handling + */ +#define MCPWM_GEN1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x80) +/** MCPWM_GEN1_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 1's active register of configuration. When all bits + * are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to + * 1:sync;when bit3 is set to 1:disable the update. + */ +#define MCPWM_GEN1_CFG_UPMETHOD 0x0000000FU +#define MCPWM_GEN1_CFG_UPMETHOD_M (MCPWM_GEN1_CFG_UPMETHOD_V << MCPWM_GEN1_CFG_UPMETHOD_S) +#define MCPWM_GEN1_CFG_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN1_CFG_UPMETHOD_S 0 +/** MCPWM_GEN1_T0_SEL : R/W; bitpos: [6:4]; default: 0; + * Source selection for PWM generator 1 event_t0, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN1_T0_SEL 0x00000007U +#define MCPWM_GEN1_T0_SEL_M (MCPWM_GEN1_T0_SEL_V << MCPWM_GEN1_T0_SEL_S) +#define MCPWM_GEN1_T0_SEL_V 0x00000007U +#define MCPWM_GEN1_T0_SEL_S 4 +/** MCPWM_GEN1_T1_SEL : R/W; bitpos: [9:7]; default: 0; + * Source selection for PWM generator 1 event_t1, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN1_T1_SEL 0x00000007U +#define MCPWM_GEN1_T1_SEL_M (MCPWM_GEN1_T1_SEL_V << MCPWM_GEN1_T1_SEL_S) +#define MCPWM_GEN1_T1_SEL_V 0x00000007U +#define MCPWM_GEN1_T1_SEL_S 7 + +/** MCPWM_GEN1_FORCE_REG register + * Permissives to force PWM1A and PWM1B outputs by software + */ +#define MCPWM_GEN1_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x84) +/** MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; + * Updating method for continuous software force of PWM generator 1. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when + * bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, + * when bit5 is set to 1: disable update. (TEA/B here and below means an event + * generated when the timer's value equals to that of register A/B.) + */ +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD 0x0000003FU +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M (MCPWM_GEN1_CNTUFORCE_UPMETHOD_V << MCPWM_GEN1_CNTUFORCE_UPMETHOD_S) +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V 0x0000003FU +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN1_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; + * Continuous software force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN1_A_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN1_A_CNTUFORCE_MODE_M (MCPWM_GEN1_A_CNTUFORCE_MODE_V << MCPWM_GEN1_A_CNTUFORCE_MODE_S) +#define MCPWM_GEN1_A_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_A_CNTUFORCE_MODE_S 6 +/** MCPWM_GEN1_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; + * Continuous software force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN1_B_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN1_B_CNTUFORCE_MODE_M (MCPWM_GEN1_B_CNTUFORCE_MODE_V << MCPWM_GEN1_B_CNTUFORCE_MODE_S) +#define MCPWM_GEN1_B_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_B_CNTUFORCE_MODE_S 8 +/** MCPWM_GEN1_A_NCIFORCE : R/W; bitpos: [10]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM1A, a toggle will + * trigger a force event. + */ +#define MCPWM_GEN1_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN1_A_NCIFORCE_M (MCPWM_GEN1_A_NCIFORCE_V << MCPWM_GEN1_A_NCIFORCE_S) +#define MCPWM_GEN1_A_NCIFORCE_V 0x00000001U +#define MCPWM_GEN1_A_NCIFORCE_S 10 +/** MCPWM_GEN1_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; + * non-continuous immediate software force mode for PWM1A, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN1_A_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN1_A_NCIFORCE_MODE_M (MCPWM_GEN1_A_NCIFORCE_MODE_V << MCPWM_GEN1_A_NCIFORCE_MODE_S) +#define MCPWM_GEN1_A_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_A_NCIFORCE_MODE_S 11 +/** MCPWM_GEN1_B_NCIFORCE : R/W; bitpos: [13]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM1B, a toggle will + * trigger a force event. + */ +#define MCPWM_GEN1_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN1_B_NCIFORCE_M (MCPWM_GEN1_B_NCIFORCE_V << MCPWM_GEN1_B_NCIFORCE_S) +#define MCPWM_GEN1_B_NCIFORCE_V 0x00000001U +#define MCPWM_GEN1_B_NCIFORCE_S 13 +/** MCPWM_GEN1_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; + * non-continuous immediate software force mode for PWM1B, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN1_B_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN1_B_NCIFORCE_MODE_M (MCPWM_GEN1_B_NCIFORCE_MODE_V << MCPWM_GEN1_B_NCIFORCE_MODE_S) +#define MCPWM_GEN1_B_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_B_NCIFORCE_MODE_S 14 + +/** MCPWM_GEN1_A_REG register + * Actions triggered by events on PWM1A + */ +#define MCPWM_GEN1_A_REG(i) (REG_MCPWM_BASE(i) + 0x88) +/** MCPWM_GEN1_A_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM1A triggered by event TEZ when timer increasing + */ +#define MCPWM_GEN1_A_UTEZ 0x00000003U +#define MCPWM_GEN1_A_UTEZ_M (MCPWM_GEN1_A_UTEZ_V << MCPWM_GEN1_A_UTEZ_S) +#define MCPWM_GEN1_A_UTEZ_V 0x00000003U +#define MCPWM_GEN1_A_UTEZ_S 0 +/** MCPWM_GEN1_A_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM1A triggered by event TEP when timer increasing + */ +#define MCPWM_GEN1_A_UTEP 0x00000003U +#define MCPWM_GEN1_A_UTEP_M (MCPWM_GEN1_A_UTEP_V << MCPWM_GEN1_A_UTEP_S) +#define MCPWM_GEN1_A_UTEP_V 0x00000003U +#define MCPWM_GEN1_A_UTEP_S 2 +/** MCPWM_GEN1_A_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM1A triggered by event TEA when timer increasing + */ +#define MCPWM_GEN1_A_UTEA 0x00000003U +#define MCPWM_GEN1_A_UTEA_M (MCPWM_GEN1_A_UTEA_V << MCPWM_GEN1_A_UTEA_S) +#define MCPWM_GEN1_A_UTEA_V 0x00000003U +#define MCPWM_GEN1_A_UTEA_S 4 +/** MCPWM_GEN1_A_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM1A triggered by event TEB when timer increasing + */ +#define MCPWM_GEN1_A_UTEB 0x00000003U +#define MCPWM_GEN1_A_UTEB_M (MCPWM_GEN1_A_UTEB_V << MCPWM_GEN1_A_UTEB_S) +#define MCPWM_GEN1_A_UTEB_V 0x00000003U +#define MCPWM_GEN1_A_UTEB_S 6 +/** MCPWM_GEN1_A_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM1A triggered by event_t0 when timer increasing + */ +#define MCPWM_GEN1_A_UT0 0x00000003U +#define MCPWM_GEN1_A_UT0_M (MCPWM_GEN1_A_UT0_V << MCPWM_GEN1_A_UT0_S) +#define MCPWM_GEN1_A_UT0_V 0x00000003U +#define MCPWM_GEN1_A_UT0_S 8 +/** MCPWM_GEN1_A_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM1A triggered by event_t1 when timer increasing + */ +#define MCPWM_GEN1_A_UT1 0x00000003U +#define MCPWM_GEN1_A_UT1_M (MCPWM_GEN1_A_UT1_V << MCPWM_GEN1_A_UT1_S) +#define MCPWM_GEN1_A_UT1_V 0x00000003U +#define MCPWM_GEN1_A_UT1_S 10 +/** MCPWM_GEN1_A_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM1A triggered by event TEZ when timer decreasing + */ +#define MCPWM_GEN1_A_DTEZ 0x00000003U +#define MCPWM_GEN1_A_DTEZ_M (MCPWM_GEN1_A_DTEZ_V << MCPWM_GEN1_A_DTEZ_S) +#define MCPWM_GEN1_A_DTEZ_V 0x00000003U +#define MCPWM_GEN1_A_DTEZ_S 12 +/** MCPWM_GEN1_A_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM1A triggered by event TEP when timer decreasing + */ +#define MCPWM_GEN1_A_DTEP 0x00000003U +#define MCPWM_GEN1_A_DTEP_M (MCPWM_GEN1_A_DTEP_V << MCPWM_GEN1_A_DTEP_S) +#define MCPWM_GEN1_A_DTEP_V 0x00000003U +#define MCPWM_GEN1_A_DTEP_S 14 +/** MCPWM_GEN1_A_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM1A triggered by event TEA when timer decreasing + */ +#define MCPWM_GEN1_A_DTEA 0x00000003U +#define MCPWM_GEN1_A_DTEA_M (MCPWM_GEN1_A_DTEA_V << MCPWM_GEN1_A_DTEA_S) +#define MCPWM_GEN1_A_DTEA_V 0x00000003U +#define MCPWM_GEN1_A_DTEA_S 16 +/** MCPWM_GEN1_A_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM1A triggered by event TEB when timer decreasing + */ +#define MCPWM_GEN1_A_DTEB 0x00000003U +#define MCPWM_GEN1_A_DTEB_M (MCPWM_GEN1_A_DTEB_V << MCPWM_GEN1_A_DTEB_S) +#define MCPWM_GEN1_A_DTEB_V 0x00000003U +#define MCPWM_GEN1_A_DTEB_S 18 +/** MCPWM_GEN1_A_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM1A triggered by event_t0 when timer decreasing + */ +#define MCPWM_GEN1_A_DT0 0x00000003U +#define MCPWM_GEN1_A_DT0_M (MCPWM_GEN1_A_DT0_V << MCPWM_GEN1_A_DT0_S) +#define MCPWM_GEN1_A_DT0_V 0x00000003U +#define MCPWM_GEN1_A_DT0_S 20 +/** MCPWM_GEN1_A_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM1A triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_A_DT1 0x00000003U +#define MCPWM_GEN1_A_DT1_M (MCPWM_GEN1_A_DT1_V << MCPWM_GEN1_A_DT1_S) +#define MCPWM_GEN1_A_DT1_V 0x00000003U +#define MCPWM_GEN1_A_DT1_S 22 + +/** MCPWM_GEN1_B_REG register + * Actions triggered by events on PWM1B + */ +#define MCPWM_GEN1_B_REG(i) (REG_MCPWM_BASE(i) + 0x8c) +/** MCPWM_GEN1_B_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM1B triggered by event TEZ when timer increasing + */ +#define MCPWM_GEN1_B_UTEZ 0x00000003U +#define MCPWM_GEN1_B_UTEZ_M (MCPWM_GEN1_B_UTEZ_V << MCPWM_GEN1_B_UTEZ_S) +#define MCPWM_GEN1_B_UTEZ_V 0x00000003U +#define MCPWM_GEN1_B_UTEZ_S 0 +/** MCPWM_GEN1_B_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM1B triggered by event TEP when timer increasing + */ +#define MCPWM_GEN1_B_UTEP 0x00000003U +#define MCPWM_GEN1_B_UTEP_M (MCPWM_GEN1_B_UTEP_V << MCPWM_GEN1_B_UTEP_S) +#define MCPWM_GEN1_B_UTEP_V 0x00000003U +#define MCPWM_GEN1_B_UTEP_S 2 +/** MCPWM_GEN1_B_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM1B triggered by event TEA when timer increasing + */ +#define MCPWM_GEN1_B_UTEA 0x00000003U +#define MCPWM_GEN1_B_UTEA_M (MCPWM_GEN1_B_UTEA_V << MCPWM_GEN1_B_UTEA_S) +#define MCPWM_GEN1_B_UTEA_V 0x00000003U +#define MCPWM_GEN1_B_UTEA_S 4 +/** MCPWM_GEN1_B_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM1B triggered by event TEB when timer increasing + */ +#define MCPWM_GEN1_B_UTEB 0x00000003U +#define MCPWM_GEN1_B_UTEB_M (MCPWM_GEN1_B_UTEB_V << MCPWM_GEN1_B_UTEB_S) +#define MCPWM_GEN1_B_UTEB_V 0x00000003U +#define MCPWM_GEN1_B_UTEB_S 6 +/** MCPWM_GEN1_B_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM1B triggered by event_t0 when timer increasing + */ +#define MCPWM_GEN1_B_UT0 0x00000003U +#define MCPWM_GEN1_B_UT0_M (MCPWM_GEN1_B_UT0_V << MCPWM_GEN1_B_UT0_S) +#define MCPWM_GEN1_B_UT0_V 0x00000003U +#define MCPWM_GEN1_B_UT0_S 8 +/** MCPWM_GEN1_B_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM1B triggered by event_t1 when timer increasing + */ +#define MCPWM_GEN1_B_UT1 0x00000003U +#define MCPWM_GEN1_B_UT1_M (MCPWM_GEN1_B_UT1_V << MCPWM_GEN1_B_UT1_S) +#define MCPWM_GEN1_B_UT1_V 0x00000003U +#define MCPWM_GEN1_B_UT1_S 10 +/** MCPWM_GEN1_B_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM1B triggered by event TEZ when timer decreasing + */ +#define MCPWM_GEN1_B_DTEZ 0x00000003U +#define MCPWM_GEN1_B_DTEZ_M (MCPWM_GEN1_B_DTEZ_V << MCPWM_GEN1_B_DTEZ_S) +#define MCPWM_GEN1_B_DTEZ_V 0x00000003U +#define MCPWM_GEN1_B_DTEZ_S 12 +/** MCPWM_GEN1_B_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM1B triggered by event TEP when timer decreasing + */ +#define MCPWM_GEN1_B_DTEP 0x00000003U +#define MCPWM_GEN1_B_DTEP_M (MCPWM_GEN1_B_DTEP_V << MCPWM_GEN1_B_DTEP_S) +#define MCPWM_GEN1_B_DTEP_V 0x00000003U +#define MCPWM_GEN1_B_DTEP_S 14 +/** MCPWM_GEN1_B_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM1B triggered by event TEA when timer decreasing + */ +#define MCPWM_GEN1_B_DTEA 0x00000003U +#define MCPWM_GEN1_B_DTEA_M (MCPWM_GEN1_B_DTEA_V << MCPWM_GEN1_B_DTEA_S) +#define MCPWM_GEN1_B_DTEA_V 0x00000003U +#define MCPWM_GEN1_B_DTEA_S 16 +/** MCPWM_GEN1_B_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM1B triggered by event TEB when timer decreasing + */ +#define MCPWM_GEN1_B_DTEB 0x00000003U +#define MCPWM_GEN1_B_DTEB_M (MCPWM_GEN1_B_DTEB_V << MCPWM_GEN1_B_DTEB_S) +#define MCPWM_GEN1_B_DTEB_V 0x00000003U +#define MCPWM_GEN1_B_DTEB_S 18 +/** MCPWM_GEN1_B_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM1B triggered by event_t0 when timer decreasing + */ +#define MCPWM_GEN1_B_DT0 0x00000003U +#define MCPWM_GEN1_B_DT0_M (MCPWM_GEN1_B_DT0_V << MCPWM_GEN1_B_DT0_S) +#define MCPWM_GEN1_B_DT0_V 0x00000003U +#define MCPWM_GEN1_B_DT0_S 20 +/** MCPWM_GEN1_B_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM1B triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN1_B_DT1 0x00000003U +#define MCPWM_GEN1_B_DT1_M (MCPWM_GEN1_B_DT1_V << MCPWM_GEN1_B_DT1_S) +#define MCPWM_GEN1_B_DT1_V 0x00000003U +#define MCPWM_GEN1_B_DT1_S 22 + +/** MCPWM_DT1_CFG_REG register + * dead time type selection and configuration + */ +#define MCPWM_DT1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x90) +/** MCPWM_DB1_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for FED (falling edge delay) active register. 0: immediate, when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DB1_FED_UPMETHOD 0x0000000FU +#define MCPWM_DB1_FED_UPMETHOD_M (MCPWM_DB1_FED_UPMETHOD_V << MCPWM_DB1_FED_UPMETHOD_S) +#define MCPWM_DB1_FED_UPMETHOD_V 0x0000000FU +#define MCPWM_DB1_FED_UPMETHOD_S 0 +/** MCPWM_DB1_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for RED (rising edge delay) active register. 0: immediate,when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DB1_RED_UPMETHOD 0x0000000FU +#define MCPWM_DB1_RED_UPMETHOD_M (MCPWM_DB1_RED_UPMETHOD_V << MCPWM_DB1_RED_UPMETHOD_S) +#define MCPWM_DB1_RED_UPMETHOD_V 0x0000000FU +#define MCPWM_DB1_RED_UPMETHOD_S 4 +/** MCPWM_DB1_DEB_MODE : R/W; bitpos: [8]; default: 0; + * S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, + * 1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ +#define MCPWM_DB1_DEB_MODE (BIT(8)) +#define MCPWM_DB1_DEB_MODE_M (MCPWM_DB1_DEB_MODE_V << MCPWM_DB1_DEB_MODE_S) +#define MCPWM_DB1_DEB_MODE_V 0x00000001U +#define MCPWM_DB1_DEB_MODE_S 8 +/** MCPWM_DB1_A_OUTSWAP : R/W; bitpos: [9]; default: 0; + * S6 in table + */ +#define MCPWM_DB1_A_OUTSWAP (BIT(9)) +#define MCPWM_DB1_A_OUTSWAP_M (MCPWM_DB1_A_OUTSWAP_V << MCPWM_DB1_A_OUTSWAP_S) +#define MCPWM_DB1_A_OUTSWAP_V 0x00000001U +#define MCPWM_DB1_A_OUTSWAP_S 9 +/** MCPWM_DB1_B_OUTSWAP : R/W; bitpos: [10]; default: 0; + * S7 in table + */ +#define MCPWM_DB1_B_OUTSWAP (BIT(10)) +#define MCPWM_DB1_B_OUTSWAP_M (MCPWM_DB1_B_OUTSWAP_V << MCPWM_DB1_B_OUTSWAP_S) +#define MCPWM_DB1_B_OUTSWAP_V 0x00000001U +#define MCPWM_DB1_B_OUTSWAP_S 10 +/** MCPWM_DB1_RED_INSEL : R/W; bitpos: [11]; default: 0; + * S4 in table + */ +#define MCPWM_DB1_RED_INSEL (BIT(11)) +#define MCPWM_DB1_RED_INSEL_M (MCPWM_DB1_RED_INSEL_V << MCPWM_DB1_RED_INSEL_S) +#define MCPWM_DB1_RED_INSEL_V 0x00000001U +#define MCPWM_DB1_RED_INSEL_S 11 +/** MCPWM_DB1_FED_INSEL : R/W; bitpos: [12]; default: 0; + * S5 in table + */ +#define MCPWM_DB1_FED_INSEL (BIT(12)) +#define MCPWM_DB1_FED_INSEL_M (MCPWM_DB1_FED_INSEL_V << MCPWM_DB1_FED_INSEL_S) +#define MCPWM_DB1_FED_INSEL_V 0x00000001U +#define MCPWM_DB1_FED_INSEL_S 12 +/** MCPWM_DB1_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; + * S2 in table + */ +#define MCPWM_DB1_RED_OUTINVERT (BIT(13)) +#define MCPWM_DB1_RED_OUTINVERT_M (MCPWM_DB1_RED_OUTINVERT_V << MCPWM_DB1_RED_OUTINVERT_S) +#define MCPWM_DB1_RED_OUTINVERT_V 0x00000001U +#define MCPWM_DB1_RED_OUTINVERT_S 13 +/** MCPWM_DB1_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; + * S3 in table + */ +#define MCPWM_DB1_FED_OUTINVERT (BIT(14)) +#define MCPWM_DB1_FED_OUTINVERT_M (MCPWM_DB1_FED_OUTINVERT_V << MCPWM_DB1_FED_OUTINVERT_S) +#define MCPWM_DB1_FED_OUTINVERT_V 0x00000001U +#define MCPWM_DB1_FED_OUTINVERT_S 14 +/** MCPWM_DB1_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; + * S1 in table + */ +#define MCPWM_DB1_A_OUTBYPASS (BIT(15)) +#define MCPWM_DB1_A_OUTBYPASS_M (MCPWM_DB1_A_OUTBYPASS_V << MCPWM_DB1_A_OUTBYPASS_S) +#define MCPWM_DB1_A_OUTBYPASS_V 0x00000001U +#define MCPWM_DB1_A_OUTBYPASS_S 15 +/** MCPWM_DB1_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; + * S0 in table + */ +#define MCPWM_DB1_B_OUTBYPASS (BIT(16)) +#define MCPWM_DB1_B_OUTBYPASS_M (MCPWM_DB1_B_OUTBYPASS_V << MCPWM_DB1_B_OUTBYPASS_S) +#define MCPWM_DB1_B_OUTBYPASS_V 0x00000001U +#define MCPWM_DB1_B_OUTBYPASS_S 16 +/** MCPWM_DB1_CLK_SEL : R/W; bitpos: [17]; default: 0; + * Dead time generator 1 clock selection. 0: PWM_clk, 1: PT_clk + */ +#define MCPWM_DB1_CLK_SEL (BIT(17)) +#define MCPWM_DB1_CLK_SEL_M (MCPWM_DB1_CLK_SEL_V << MCPWM_DB1_CLK_SEL_S) +#define MCPWM_DB1_CLK_SEL_V 0x00000001U +#define MCPWM_DB1_CLK_SEL_S 17 + +/** MCPWM_DT1_FED_CFG_REG register + * Shadow register for falling edge delay (FED). + */ +#define MCPWM_DT1_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x94) +/** MCPWM_DB1_FED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for FED + */ +#define MCPWM_DB1_FED 0x0000FFFFU +#define MCPWM_DB1_FED_M (MCPWM_DB1_FED_V << MCPWM_DB1_FED_S) +#define MCPWM_DB1_FED_V 0x0000FFFFU +#define MCPWM_DB1_FED_S 0 + +/** MCPWM_DT1_RED_CFG_REG register + * Shadow register for rising edge delay (RED). + */ +#define MCPWM_DT1_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x98) +/** MCPWM_DB1_RED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for RED + */ +#define MCPWM_DB1_RED 0x0000FFFFU +#define MCPWM_DB1_RED_M (MCPWM_DB1_RED_V << MCPWM_DB1_RED_S) +#define MCPWM_DB1_RED_V 0x0000FFFFU +#define MCPWM_DB1_RED_S 0 + +/** MCPWM_CARRIER1_CFG_REG register + * Carrier enable and configuratoin + */ +#define MCPWM_CARRIER1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x9c) +/** MCPWM_CHOPPER1_EN : R/W; bitpos: [0]; default: 0; + * When set, carrier1 function is enabled. When cleared, carrier1 is bypassed + */ +#define MCPWM_CHOPPER1_EN (BIT(0)) +#define MCPWM_CHOPPER1_EN_M (MCPWM_CHOPPER1_EN_V << MCPWM_CHOPPER1_EN_S) +#define MCPWM_CHOPPER1_EN_V 0x00000001U +#define MCPWM_CHOPPER1_EN_S 0 +/** MCPWM_CHOPPER1_PRESCALE : R/W; bitpos: [4:1]; default: 0; + * PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * + * (PWM_CARRIER0_PRESCALE + 1) + */ +#define MCPWM_CHOPPER1_PRESCALE 0x0000000FU +#define MCPWM_CHOPPER1_PRESCALE_M (MCPWM_CHOPPER1_PRESCALE_V << MCPWM_CHOPPER1_PRESCALE_S) +#define MCPWM_CHOPPER1_PRESCALE_V 0x0000000FU +#define MCPWM_CHOPPER1_PRESCALE_S 1 +/** MCPWM_CHOPPER1_DUTY : R/W; bitpos: [7:5]; default: 0; + * carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + */ +#define MCPWM_CHOPPER1_DUTY 0x00000007U +#define MCPWM_CHOPPER1_DUTY_M (MCPWM_CHOPPER1_DUTY_V << MCPWM_CHOPPER1_DUTY_S) +#define MCPWM_CHOPPER1_DUTY_V 0x00000007U +#define MCPWM_CHOPPER1_DUTY_S 5 +/** MCPWM_CHOPPER1_OSHTWTH : R/W; bitpos: [11:8]; default: 0; + * width of the first pulse in number of periods of the carrier + */ +#define MCPWM_CHOPPER1_OSHTWTH 0x0000000FU +#define MCPWM_CHOPPER1_OSHTWTH_M (MCPWM_CHOPPER1_OSHTWTH_V << MCPWM_CHOPPER1_OSHTWTH_S) +#define MCPWM_CHOPPER1_OSHTWTH_V 0x0000000FU +#define MCPWM_CHOPPER1_OSHTWTH_S 8 +/** MCPWM_CHOPPER1_OUT_INVERT : R/W; bitpos: [12]; default: 0; + * when set, invert the output of PWM1A and PWM1B for this submodule + */ +#define MCPWM_CHOPPER1_OUT_INVERT (BIT(12)) +#define MCPWM_CHOPPER1_OUT_INVERT_M (MCPWM_CHOPPER1_OUT_INVERT_V << MCPWM_CHOPPER1_OUT_INVERT_S) +#define MCPWM_CHOPPER1_OUT_INVERT_V 0x00000001U +#define MCPWM_CHOPPER1_OUT_INVERT_S 12 +/** MCPWM_CHOPPER1_IN_INVERT : R/W; bitpos: [13]; default: 0; + * when set, invert the input of PWM1A and PWM1B for this submodule + */ +#define MCPWM_CHOPPER1_IN_INVERT (BIT(13)) +#define MCPWM_CHOPPER1_IN_INVERT_M (MCPWM_CHOPPER1_IN_INVERT_V << MCPWM_CHOPPER1_IN_INVERT_S) +#define MCPWM_CHOPPER1_IN_INVERT_V 0x00000001U +#define MCPWM_CHOPPER1_IN_INVERT_S 13 + +/** MCPWM_FH1_CFG0_REG register + * Actions on PWM1A and PWM1B trip events + */ +#define MCPWM_FH1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xa0) +/** MCPWM_TZ1_SW_CBC : R/W; bitpos: [0]; default: 0; + * Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ1_SW_CBC (BIT(0)) +#define MCPWM_TZ1_SW_CBC_M (MCPWM_TZ1_SW_CBC_V << MCPWM_TZ1_SW_CBC_S) +#define MCPWM_TZ1_SW_CBC_V 0x00000001U +#define MCPWM_TZ1_SW_CBC_S 0 +/** MCPWM_TZ1_F2_CBC : R/W; bitpos: [1]; default: 0; + * event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ1_F2_CBC (BIT(1)) +#define MCPWM_TZ1_F2_CBC_M (MCPWM_TZ1_F2_CBC_V << MCPWM_TZ1_F2_CBC_S) +#define MCPWM_TZ1_F2_CBC_V 0x00000001U +#define MCPWM_TZ1_F2_CBC_S 1 +/** MCPWM_TZ1_F1_CBC : R/W; bitpos: [2]; default: 0; + * event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ1_F1_CBC (BIT(2)) +#define MCPWM_TZ1_F1_CBC_M (MCPWM_TZ1_F1_CBC_V << MCPWM_TZ1_F1_CBC_S) +#define MCPWM_TZ1_F1_CBC_V 0x00000001U +#define MCPWM_TZ1_F1_CBC_S 2 +/** MCPWM_TZ1_F0_CBC : R/W; bitpos: [3]; default: 0; + * event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ1_F0_CBC (BIT(3)) +#define MCPWM_TZ1_F0_CBC_M (MCPWM_TZ1_F0_CBC_V << MCPWM_TZ1_F0_CBC_S) +#define MCPWM_TZ1_F0_CBC_V 0x00000001U +#define MCPWM_TZ1_F0_CBC_S 3 +/** MCPWM_TZ1_SW_OST : R/W; bitpos: [4]; default: 0; + * Enable register for software force one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ1_SW_OST (BIT(4)) +#define MCPWM_TZ1_SW_OST_M (MCPWM_TZ1_SW_OST_V << MCPWM_TZ1_SW_OST_S) +#define MCPWM_TZ1_SW_OST_V 0x00000001U +#define MCPWM_TZ1_SW_OST_S 4 +/** MCPWM_TZ1_F2_OST : R/W; bitpos: [5]; default: 0; + * event_f2 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ1_F2_OST (BIT(5)) +#define MCPWM_TZ1_F2_OST_M (MCPWM_TZ1_F2_OST_V << MCPWM_TZ1_F2_OST_S) +#define MCPWM_TZ1_F2_OST_V 0x00000001U +#define MCPWM_TZ1_F2_OST_S 5 +/** MCPWM_TZ1_F1_OST : R/W; bitpos: [6]; default: 0; + * event_f1 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ1_F1_OST (BIT(6)) +#define MCPWM_TZ1_F1_OST_M (MCPWM_TZ1_F1_OST_V << MCPWM_TZ1_F1_OST_S) +#define MCPWM_TZ1_F1_OST_V 0x00000001U +#define MCPWM_TZ1_F1_OST_S 6 +/** MCPWM_TZ1_F0_OST : R/W; bitpos: [7]; default: 0; + * event_f0 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ1_F0_OST (BIT(7)) +#define MCPWM_TZ1_F0_OST_M (MCPWM_TZ1_F0_OST_V << MCPWM_TZ1_F0_OST_S) +#define MCPWM_TZ1_F0_OST_V 0x00000001U +#define MCPWM_TZ1_F0_OST_S 7 +/** MCPWM_TZ1_A_CBC_D : R/W; bitpos: [9:8]; default: 0; + * Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ1_A_CBC_D 0x00000003U +#define MCPWM_TZ1_A_CBC_D_M (MCPWM_TZ1_A_CBC_D_V << MCPWM_TZ1_A_CBC_D_S) +#define MCPWM_TZ1_A_CBC_D_V 0x00000003U +#define MCPWM_TZ1_A_CBC_D_S 8 +/** MCPWM_TZ1_A_CBC_U : R/W; bitpos: [11:10]; default: 0; + * Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ1_A_CBC_U 0x00000003U +#define MCPWM_TZ1_A_CBC_U_M (MCPWM_TZ1_A_CBC_U_V << MCPWM_TZ1_A_CBC_U_S) +#define MCPWM_TZ1_A_CBC_U_V 0x00000003U +#define MCPWM_TZ1_A_CBC_U_S 10 +/** MCPWM_TZ1_A_OST_D : R/W; bitpos: [13:12]; default: 0; + * One-shot mode action on PWM1A when fault event occurs and timer is decreasing. 0: + * do nothing,1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ1_A_OST_D 0x00000003U +#define MCPWM_TZ1_A_OST_D_M (MCPWM_TZ1_A_OST_D_V << MCPWM_TZ1_A_OST_D_S) +#define MCPWM_TZ1_A_OST_D_V 0x00000003U +#define MCPWM_TZ1_A_OST_D_S 12 +/** MCPWM_TZ1_A_OST_U : R/W; bitpos: [15:14]; default: 0; + * One-shot mode action on PWM1A when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ1_A_OST_U 0x00000003U +#define MCPWM_TZ1_A_OST_U_M (MCPWM_TZ1_A_OST_U_V << MCPWM_TZ1_A_OST_U_S) +#define MCPWM_TZ1_A_OST_U_V 0x00000003U +#define MCPWM_TZ1_A_OST_U_S 14 +/** MCPWM_TZ1_B_CBC_D : R/W; bitpos: [17:16]; default: 0; + * Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ1_B_CBC_D 0x00000003U +#define MCPWM_TZ1_B_CBC_D_M (MCPWM_TZ1_B_CBC_D_V << MCPWM_TZ1_B_CBC_D_S) +#define MCPWM_TZ1_B_CBC_D_V 0x00000003U +#define MCPWM_TZ1_B_CBC_D_S 16 +/** MCPWM_TZ1_B_CBC_U : R/W; bitpos: [19:18]; default: 0; + * Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ1_B_CBC_U 0x00000003U +#define MCPWM_TZ1_B_CBC_U_M (MCPWM_TZ1_B_CBC_U_V << MCPWM_TZ1_B_CBC_U_S) +#define MCPWM_TZ1_B_CBC_U_V 0x00000003U +#define MCPWM_TZ1_B_CBC_U_S 18 +/** MCPWM_TZ1_B_OST_D : R/W; bitpos: [21:20]; default: 0; + * One-shot mode action on PWM1B when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ1_B_OST_D 0x00000003U +#define MCPWM_TZ1_B_OST_D_M (MCPWM_TZ1_B_OST_D_V << MCPWM_TZ1_B_OST_D_S) +#define MCPWM_TZ1_B_OST_D_V 0x00000003U +#define MCPWM_TZ1_B_OST_D_S 20 +/** MCPWM_TZ1_B_OST_U : R/W; bitpos: [23:22]; default: 0; + * One-shot mode action on PWM1B when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ1_B_OST_U 0x00000003U +#define MCPWM_TZ1_B_OST_U_M (MCPWM_TZ1_B_OST_U_V << MCPWM_TZ1_B_OST_U_S) +#define MCPWM_TZ1_B_OST_U_V 0x00000003U +#define MCPWM_TZ1_B_OST_U_S 22 + +/** MCPWM_FH1_CFG1_REG register + * Software triggers for fault handler actions + */ +#define MCPWM_FH1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0xa4) +/** MCPWM_TZ1_CLR_OST : R/W; bitpos: [0]; default: 0; + * a rising edge will clear on going one-shot mode action + */ +#define MCPWM_TZ1_CLR_OST (BIT(0)) +#define MCPWM_TZ1_CLR_OST_M (MCPWM_TZ1_CLR_OST_V << MCPWM_TZ1_CLR_OST_S) +#define MCPWM_TZ1_CLR_OST_V 0x00000001U +#define MCPWM_TZ1_CLR_OST_S 0 +/** MCPWM_TZ1_CBCPULSE : R/W; bitpos: [2:1]; default: 0; + * cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, + * when bit1 is set to 1:TEP + */ +#define MCPWM_TZ1_CBCPULSE 0x00000003U +#define MCPWM_TZ1_CBCPULSE_M (MCPWM_TZ1_CBCPULSE_V << MCPWM_TZ1_CBCPULSE_S) +#define MCPWM_TZ1_CBCPULSE_V 0x00000003U +#define MCPWM_TZ1_CBCPULSE_S 1 +/** MCPWM_TZ1_FORCE_CBC : R/W; bitpos: [3]; default: 0; + * a toggle trigger a cycle-by-cycle mode action + */ +#define MCPWM_TZ1_FORCE_CBC (BIT(3)) +#define MCPWM_TZ1_FORCE_CBC_M (MCPWM_TZ1_FORCE_CBC_V << MCPWM_TZ1_FORCE_CBC_S) +#define MCPWM_TZ1_FORCE_CBC_V 0x00000001U +#define MCPWM_TZ1_FORCE_CBC_S 3 +/** MCPWM_TZ1_FORCE_OST : R/W; bitpos: [4]; default: 0; + * a toggle (software negate its value) triggers a one-shot mode action + */ +#define MCPWM_TZ1_FORCE_OST (BIT(4)) +#define MCPWM_TZ1_FORCE_OST_M (MCPWM_TZ1_FORCE_OST_V << MCPWM_TZ1_FORCE_OST_S) +#define MCPWM_TZ1_FORCE_OST_V 0x00000001U +#define MCPWM_TZ1_FORCE_OST_S 4 + +/** MCPWM_FH1_STATUS_REG register + * Status of fault events. + */ +#define MCPWM_FH1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xa8) +/** MCPWM_TZ1_CBC_ON : RO; bitpos: [0]; default: 0; + * Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + */ +#define MCPWM_TZ1_CBC_ON (BIT(0)) +#define MCPWM_TZ1_CBC_ON_M (MCPWM_TZ1_CBC_ON_V << MCPWM_TZ1_CBC_ON_S) +#define MCPWM_TZ1_CBC_ON_V 0x00000001U +#define MCPWM_TZ1_CBC_ON_S 0 +/** MCPWM_TZ1_OST_ON : RO; bitpos: [1]; default: 0; + * Set and reset by hardware. If set, an one-shot mode action is on going + */ +#define MCPWM_TZ1_OST_ON (BIT(1)) +#define MCPWM_TZ1_OST_ON_M (MCPWM_TZ1_OST_ON_V << MCPWM_TZ1_OST_ON_S) +#define MCPWM_TZ1_OST_ON_V 0x00000001U +#define MCPWM_TZ1_OST_ON_S 1 + +/** MCPWM_GEN2_STMP_CFG_REG register + * Transfer status and update method for time stamp registers A and B + */ +#define MCPWM_GEN2_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xac) +/** MCPWM_CMPR2_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 2 time stamp A's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_CMPR2_A_UPMETHOD 0x0000000FU +#define MCPWM_CMPR2_A_UPMETHOD_M (MCPWM_CMPR2_A_UPMETHOD_V << MCPWM_CMPR2_A_UPMETHOD_S) +#define MCPWM_CMPR2_A_UPMETHOD_V 0x0000000FU +#define MCPWM_CMPR2_A_UPMETHOD_S 0 +/** MCPWM_CMPR2_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for PWM generator 2 time stamp B's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ +#define MCPWM_CMPR2_B_UPMETHOD 0x0000000FU +#define MCPWM_CMPR2_B_UPMETHOD_M (MCPWM_CMPR2_B_UPMETHOD_V << MCPWM_CMPR2_B_UPMETHOD_S) +#define MCPWM_CMPR2_B_UPMETHOD_V 0x0000000FU +#define MCPWM_CMPR2_B_UPMETHOD_S 4 +/** MCPWM_CMPR2_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is + * filled and waiting to be transferred to A's active reg. If cleared, A's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_CMPR2_A_SHDW_FULL (BIT(8)) +#define MCPWM_CMPR2_A_SHDW_FULL_M (MCPWM_CMPR2_A_SHDW_FULL_V << MCPWM_CMPR2_A_SHDW_FULL_S) +#define MCPWM_CMPR2_A_SHDW_FULL_V 0x00000001U +#define MCPWM_CMPR2_A_SHDW_FULL_S 8 +/** MCPWM_CMPR2_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; + * Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is + * filled and waiting to be transferred to B's active reg. If cleared, B's active reg + * has been updated with shadow register latest value + */ +#define MCPWM_CMPR2_B_SHDW_FULL (BIT(9)) +#define MCPWM_CMPR2_B_SHDW_FULL_M (MCPWM_CMPR2_B_SHDW_FULL_V << MCPWM_CMPR2_B_SHDW_FULL_S) +#define MCPWM_CMPR2_B_SHDW_FULL_V 0x00000001U +#define MCPWM_CMPR2_B_SHDW_FULL_S 9 + +/** MCPWM_GEN2_TSTMP_A_REG register + * Shadow register for register A. + */ +#define MCPWM_GEN2_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0xb0) +/** MCPWM_CMPR2_A : R/W; bitpos: [15:0]; default: 0; + * PWM generator 2 time stamp A's shadow register + */ +#define MCPWM_CMPR2_A 0x0000FFFFU +#define MCPWM_CMPR2_A_M (MCPWM_CMPR2_A_V << MCPWM_CMPR2_A_S) +#define MCPWM_CMPR2_A_V 0x0000FFFFU +#define MCPWM_CMPR2_A_S 0 + +/** MCPWM_GEN2_TSTMP_B_REG register + * Shadow register for register B. + */ +#define MCPWM_GEN2_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0xb4) +/** MCPWM_CMPR2_B : R/W; bitpos: [15:0]; default: 0; + * PWM generator 2 time stamp B's shadow register + */ +#define MCPWM_CMPR2_B 0x0000FFFFU +#define MCPWM_CMPR2_B_M (MCPWM_CMPR2_B_V << MCPWM_CMPR2_B_S) +#define MCPWM_CMPR2_B_V 0x0000FFFFU +#define MCPWM_CMPR2_B_S 0 + +/** MCPWM_GEN2_CFG0_REG register + * Fault event T0 and T1 handling + */ +#define MCPWM_GEN2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xb8) +/** MCPWM_GEN2_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator 2's active register of configuration. 0: + * immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is + * set to 1:disable the update. + */ +#define MCPWM_GEN2_CFG_UPMETHOD 0x0000000FU +#define MCPWM_GEN2_CFG_UPMETHOD_M (MCPWM_GEN2_CFG_UPMETHOD_V << MCPWM_GEN2_CFG_UPMETHOD_S) +#define MCPWM_GEN2_CFG_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN2_CFG_UPMETHOD_S 0 +/** MCPWM_GEN2_T0_SEL : R/W; bitpos: [6:4]; default: 0; + * Source selection for PWM generator 2 event_t0, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN2_T0_SEL 0x00000007U +#define MCPWM_GEN2_T0_SEL_M (MCPWM_GEN2_T0_SEL_V << MCPWM_GEN2_T0_SEL_S) +#define MCPWM_GEN2_T0_SEL_V 0x00000007U +#define MCPWM_GEN2_T0_SEL_S 4 +/** MCPWM_GEN2_T1_SEL : R/W; bitpos: [9:7]; default: 0; + * Source selection for PWM generator 2 event_t1, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ +#define MCPWM_GEN2_T1_SEL 0x00000007U +#define MCPWM_GEN2_T1_SEL_M (MCPWM_GEN2_T1_SEL_V << MCPWM_GEN2_T1_SEL_S) +#define MCPWM_GEN2_T1_SEL_V 0x00000007U +#define MCPWM_GEN2_T1_SEL_S 7 + +/** MCPWM_GEN2_FORCE_REG register + * Permissives to force PWM2A and PWM2B outputs by software + */ +#define MCPWM_GEN2_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0xbc) +/** MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; + * Updating method for continuous software force of PWM generator 2. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ,when bit1 is set to 1: TEP, when + * bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, + * when bit5 is set to 1: disable update. (TEA/B here and below means an event + * generated when the timer's value equals to that of register A/B.) + */ +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD 0x0000003FU +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M (MCPWM_GEN2_CNTUFORCE_UPMETHOD_V << MCPWM_GEN2_CNTUFORCE_UPMETHOD_S) +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V 0x0000003FU +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN2_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; + * Continuous software force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN2_A_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN2_A_CNTUFORCE_MODE_M (MCPWM_GEN2_A_CNTUFORCE_MODE_V << MCPWM_GEN2_A_CNTUFORCE_MODE_S) +#define MCPWM_GEN2_A_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_A_CNTUFORCE_MODE_S 6 +/** MCPWM_GEN2_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; + * Continuous software force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled + */ +#define MCPWM_GEN2_B_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN2_B_CNTUFORCE_MODE_M (MCPWM_GEN2_B_CNTUFORCE_MODE_V << MCPWM_GEN2_B_CNTUFORCE_MODE_S) +#define MCPWM_GEN2_B_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_B_CNTUFORCE_MODE_S 8 +/** MCPWM_GEN2_A_NCIFORCE : R/W; bitpos: [10]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM2A, a toggle will + * trigger a force event. + */ +#define MCPWM_GEN2_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN2_A_NCIFORCE_M (MCPWM_GEN2_A_NCIFORCE_V << MCPWM_GEN2_A_NCIFORCE_S) +#define MCPWM_GEN2_A_NCIFORCE_V 0x00000001U +#define MCPWM_GEN2_A_NCIFORCE_S 10 +/** MCPWM_GEN2_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; + * non-continuous immediate software force mode for PWM2A, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN2_A_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN2_A_NCIFORCE_MODE_M (MCPWM_GEN2_A_NCIFORCE_MODE_V << MCPWM_GEN2_A_NCIFORCE_MODE_S) +#define MCPWM_GEN2_A_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_A_NCIFORCE_MODE_S 11 +/** MCPWM_GEN2_B_NCIFORCE : R/W; bitpos: [13]; default: 0; + * Trigger of non-continuous immediate software-force event for PWM2B, a toggle will + * trigger a force event. + */ +#define MCPWM_GEN2_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN2_B_NCIFORCE_M (MCPWM_GEN2_B_NCIFORCE_V << MCPWM_GEN2_B_NCIFORCE_S) +#define MCPWM_GEN2_B_NCIFORCE_V 0x00000001U +#define MCPWM_GEN2_B_NCIFORCE_S 13 +/** MCPWM_GEN2_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; + * non-continuous immediate software force mode for PWM2B, 0: disabled, 1: low, 2: + * high, 3: disabled + */ +#define MCPWM_GEN2_B_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN2_B_NCIFORCE_MODE_M (MCPWM_GEN2_B_NCIFORCE_MODE_V << MCPWM_GEN2_B_NCIFORCE_MODE_S) +#define MCPWM_GEN2_B_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_B_NCIFORCE_MODE_S 14 + +/** MCPWM_GEN2_A_REG register + * Actions triggered by events on PWM2A + */ +#define MCPWM_GEN2_A_REG(i) (REG_MCPWM_BASE(i) + 0xc0) +/** MCPWM_GEN2_A_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM2A triggered by event TEZ when timer increasing + */ +#define MCPWM_GEN2_A_UTEZ 0x00000003U +#define MCPWM_GEN2_A_UTEZ_M (MCPWM_GEN2_A_UTEZ_V << MCPWM_GEN2_A_UTEZ_S) +#define MCPWM_GEN2_A_UTEZ_V 0x00000003U +#define MCPWM_GEN2_A_UTEZ_S 0 +/** MCPWM_GEN2_A_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM2A triggered by event TEP when timer increasing + */ +#define MCPWM_GEN2_A_UTEP 0x00000003U +#define MCPWM_GEN2_A_UTEP_M (MCPWM_GEN2_A_UTEP_V << MCPWM_GEN2_A_UTEP_S) +#define MCPWM_GEN2_A_UTEP_V 0x00000003U +#define MCPWM_GEN2_A_UTEP_S 2 +/** MCPWM_GEN2_A_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM2A triggered by event TEA when timer increasing + */ +#define MCPWM_GEN2_A_UTEA 0x00000003U +#define MCPWM_GEN2_A_UTEA_M (MCPWM_GEN2_A_UTEA_V << MCPWM_GEN2_A_UTEA_S) +#define MCPWM_GEN2_A_UTEA_V 0x00000003U +#define MCPWM_GEN2_A_UTEA_S 4 +/** MCPWM_GEN2_A_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM2A triggered by event TEB when timer increasing + */ +#define MCPWM_GEN2_A_UTEB 0x00000003U +#define MCPWM_GEN2_A_UTEB_M (MCPWM_GEN2_A_UTEB_V << MCPWM_GEN2_A_UTEB_S) +#define MCPWM_GEN2_A_UTEB_V 0x00000003U +#define MCPWM_GEN2_A_UTEB_S 6 +/** MCPWM_GEN2_A_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM2A triggered by event_t0 when timer increasing + */ +#define MCPWM_GEN2_A_UT0 0x00000003U +#define MCPWM_GEN2_A_UT0_M (MCPWM_GEN2_A_UT0_V << MCPWM_GEN2_A_UT0_S) +#define MCPWM_GEN2_A_UT0_V 0x00000003U +#define MCPWM_GEN2_A_UT0_S 8 +/** MCPWM_GEN2_A_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM2A triggered by event_t1 when timer increasing + */ +#define MCPWM_GEN2_A_UT1 0x00000003U +#define MCPWM_GEN2_A_UT1_M (MCPWM_GEN2_A_UT1_V << MCPWM_GEN2_A_UT1_S) +#define MCPWM_GEN2_A_UT1_V 0x00000003U +#define MCPWM_GEN2_A_UT1_S 10 +/** MCPWM_GEN2_A_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM2A triggered by event TEZ when timer decreasing + */ +#define MCPWM_GEN2_A_DTEZ 0x00000003U +#define MCPWM_GEN2_A_DTEZ_M (MCPWM_GEN2_A_DTEZ_V << MCPWM_GEN2_A_DTEZ_S) +#define MCPWM_GEN2_A_DTEZ_V 0x00000003U +#define MCPWM_GEN2_A_DTEZ_S 12 +/** MCPWM_GEN2_A_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM2A triggered by event TEP when timer decreasing + */ +#define MCPWM_GEN2_A_DTEP 0x00000003U +#define MCPWM_GEN2_A_DTEP_M (MCPWM_GEN2_A_DTEP_V << MCPWM_GEN2_A_DTEP_S) +#define MCPWM_GEN2_A_DTEP_V 0x00000003U +#define MCPWM_GEN2_A_DTEP_S 14 +/** MCPWM_GEN2_A_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM2A triggered by event TEA when timer decreasing + */ +#define MCPWM_GEN2_A_DTEA 0x00000003U +#define MCPWM_GEN2_A_DTEA_M (MCPWM_GEN2_A_DTEA_V << MCPWM_GEN2_A_DTEA_S) +#define MCPWM_GEN2_A_DTEA_V 0x00000003U +#define MCPWM_GEN2_A_DTEA_S 16 +/** MCPWM_GEN2_A_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM2A triggered by event TEB when timer decreasing + */ +#define MCPWM_GEN2_A_DTEB 0x00000003U +#define MCPWM_GEN2_A_DTEB_M (MCPWM_GEN2_A_DTEB_V << MCPWM_GEN2_A_DTEB_S) +#define MCPWM_GEN2_A_DTEB_V 0x00000003U +#define MCPWM_GEN2_A_DTEB_S 18 +/** MCPWM_GEN2_A_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM2A triggered by event_t0 when timer decreasing + */ +#define MCPWM_GEN2_A_DT0 0x00000003U +#define MCPWM_GEN2_A_DT0_M (MCPWM_GEN2_A_DT0_V << MCPWM_GEN2_A_DT0_S) +#define MCPWM_GEN2_A_DT0_V 0x00000003U +#define MCPWM_GEN2_A_DT0_S 20 +/** MCPWM_GEN2_A_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM2A triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_A_DT1 0x00000003U +#define MCPWM_GEN2_A_DT1_M (MCPWM_GEN2_A_DT1_V << MCPWM_GEN2_A_DT1_S) +#define MCPWM_GEN2_A_DT1_V 0x00000003U +#define MCPWM_GEN2_A_DT1_S 22 + +/** MCPWM_GEN2_B_REG register + * Actions triggered by events on PWM2B + */ +#define MCPWM_GEN2_B_REG(i) (REG_MCPWM_BASE(i) + 0xc4) +/** MCPWM_GEN2_B_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Action on PWM2B triggered by event TEZ when timer increasing + */ +#define MCPWM_GEN2_B_UTEZ 0x00000003U +#define MCPWM_GEN2_B_UTEZ_M (MCPWM_GEN2_B_UTEZ_V << MCPWM_GEN2_B_UTEZ_S) +#define MCPWM_GEN2_B_UTEZ_V 0x00000003U +#define MCPWM_GEN2_B_UTEZ_S 0 +/** MCPWM_GEN2_B_UTEP : R/W; bitpos: [3:2]; default: 0; + * Action on PWM2B triggered by event TEP when timer increasing + */ +#define MCPWM_GEN2_B_UTEP 0x00000003U +#define MCPWM_GEN2_B_UTEP_M (MCPWM_GEN2_B_UTEP_V << MCPWM_GEN2_B_UTEP_S) +#define MCPWM_GEN2_B_UTEP_V 0x00000003U +#define MCPWM_GEN2_B_UTEP_S 2 +/** MCPWM_GEN2_B_UTEA : R/W; bitpos: [5:4]; default: 0; + * Action on PWM2B triggered by event TEA when timer increasing + */ +#define MCPWM_GEN2_B_UTEA 0x00000003U +#define MCPWM_GEN2_B_UTEA_M (MCPWM_GEN2_B_UTEA_V << MCPWM_GEN2_B_UTEA_S) +#define MCPWM_GEN2_B_UTEA_V 0x00000003U +#define MCPWM_GEN2_B_UTEA_S 4 +/** MCPWM_GEN2_B_UTEB : R/W; bitpos: [7:6]; default: 0; + * Action on PWM2B triggered by event TEB when timer increasing + */ +#define MCPWM_GEN2_B_UTEB 0x00000003U +#define MCPWM_GEN2_B_UTEB_M (MCPWM_GEN2_B_UTEB_V << MCPWM_GEN2_B_UTEB_S) +#define MCPWM_GEN2_B_UTEB_V 0x00000003U +#define MCPWM_GEN2_B_UTEB_S 6 +/** MCPWM_GEN2_B_UT0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWM2B triggered by event_t0 when timer increasing + */ +#define MCPWM_GEN2_B_UT0 0x00000003U +#define MCPWM_GEN2_B_UT0_M (MCPWM_GEN2_B_UT0_V << MCPWM_GEN2_B_UT0_S) +#define MCPWM_GEN2_B_UT0_V 0x00000003U +#define MCPWM_GEN2_B_UT0_S 8 +/** MCPWM_GEN2_B_UT1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWM2B triggered by event_t1 when timer increasing + */ +#define MCPWM_GEN2_B_UT1 0x00000003U +#define MCPWM_GEN2_B_UT1_M (MCPWM_GEN2_B_UT1_V << MCPWM_GEN2_B_UT1_S) +#define MCPWM_GEN2_B_UT1_V 0x00000003U +#define MCPWM_GEN2_B_UT1_S 10 +/** MCPWM_GEN2_B_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Action on PWM2B triggered by event TEZ when timer decreasing + */ +#define MCPWM_GEN2_B_DTEZ 0x00000003U +#define MCPWM_GEN2_B_DTEZ_M (MCPWM_GEN2_B_DTEZ_V << MCPWM_GEN2_B_DTEZ_S) +#define MCPWM_GEN2_B_DTEZ_V 0x00000003U +#define MCPWM_GEN2_B_DTEZ_S 12 +/** MCPWM_GEN2_B_DTEP : R/W; bitpos: [15:14]; default: 0; + * Action on PWM2B triggered by event TEP when timer decreasing + */ +#define MCPWM_GEN2_B_DTEP 0x00000003U +#define MCPWM_GEN2_B_DTEP_M (MCPWM_GEN2_B_DTEP_V << MCPWM_GEN2_B_DTEP_S) +#define MCPWM_GEN2_B_DTEP_V 0x00000003U +#define MCPWM_GEN2_B_DTEP_S 14 +/** MCPWM_GEN2_B_DTEA : R/W; bitpos: [17:16]; default: 0; + * Action on PWM2B triggered by event TEA when timer decreasing + */ +#define MCPWM_GEN2_B_DTEA 0x00000003U +#define MCPWM_GEN2_B_DTEA_M (MCPWM_GEN2_B_DTEA_V << MCPWM_GEN2_B_DTEA_S) +#define MCPWM_GEN2_B_DTEA_V 0x00000003U +#define MCPWM_GEN2_B_DTEA_S 16 +/** MCPWM_GEN2_B_DTEB : R/W; bitpos: [19:18]; default: 0; + * Action on PWM2B triggered by event TEB when timer decreasing + */ +#define MCPWM_GEN2_B_DTEB 0x00000003U +#define MCPWM_GEN2_B_DTEB_M (MCPWM_GEN2_B_DTEB_V << MCPWM_GEN2_B_DTEB_S) +#define MCPWM_GEN2_B_DTEB_V 0x00000003U +#define MCPWM_GEN2_B_DTEB_S 18 +/** MCPWM_GEN2_B_DT0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWM2B triggered by event_t0 when timer decreasing + */ +#define MCPWM_GEN2_B_DT0 0x00000003U +#define MCPWM_GEN2_B_DT0_M (MCPWM_GEN2_B_DT0_V << MCPWM_GEN2_B_DT0_S) +#define MCPWM_GEN2_B_DT0_V 0x00000003U +#define MCPWM_GEN2_B_DT0_S 20 +/** MCPWM_GEN2_B_DT1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWM2B triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ +#define MCPWM_GEN2_B_DT1 0x00000003U +#define MCPWM_GEN2_B_DT1_M (MCPWM_GEN2_B_DT1_V << MCPWM_GEN2_B_DT1_S) +#define MCPWM_GEN2_B_DT1_V 0x00000003U +#define MCPWM_GEN2_B_DT1_S 22 + +/** MCPWM_DT2_CFG_REG register + * dead time type selection and configuration + */ +#define MCPWM_DT2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xc8) +/** MCPWM_DB2_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Update method for FED (falling edge delay) active register. 0: immediate,when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DB2_FED_UPMETHOD 0x0000000FU +#define MCPWM_DB2_FED_UPMETHOD_M (MCPWM_DB2_FED_UPMETHOD_V << MCPWM_DB2_FED_UPMETHOD_S) +#define MCPWM_DB2_FED_UPMETHOD_V 0x0000000FU +#define MCPWM_DB2_FED_UPMETHOD_S 0 +/** MCPWM_DB2_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Update method for RED (rising edge delay) active register. 0: immediate,when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ +#define MCPWM_DB2_RED_UPMETHOD 0x0000000FU +#define MCPWM_DB2_RED_UPMETHOD_M (MCPWM_DB2_RED_UPMETHOD_V << MCPWM_DB2_RED_UPMETHOD_S) +#define MCPWM_DB2_RED_UPMETHOD_V 0x0000000FU +#define MCPWM_DB2_RED_UPMETHOD_S 4 +/** MCPWM_DB2_DEB_MODE : R/W; bitpos: [8]; default: 0; + * S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, + * 1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ +#define MCPWM_DB2_DEB_MODE (BIT(8)) +#define MCPWM_DB2_DEB_MODE_M (MCPWM_DB2_DEB_MODE_V << MCPWM_DB2_DEB_MODE_S) +#define MCPWM_DB2_DEB_MODE_V 0x00000001U +#define MCPWM_DB2_DEB_MODE_S 8 +/** MCPWM_DB2_A_OUTSWAP : R/W; bitpos: [9]; default: 0; + * S6 in table + */ +#define MCPWM_DB2_A_OUTSWAP (BIT(9)) +#define MCPWM_DB2_A_OUTSWAP_M (MCPWM_DB2_A_OUTSWAP_V << MCPWM_DB2_A_OUTSWAP_S) +#define MCPWM_DB2_A_OUTSWAP_V 0x00000001U +#define MCPWM_DB2_A_OUTSWAP_S 9 +/** MCPWM_DB2_B_OUTSWAP : R/W; bitpos: [10]; default: 0; + * S7 in table + */ +#define MCPWM_DB2_B_OUTSWAP (BIT(10)) +#define MCPWM_DB2_B_OUTSWAP_M (MCPWM_DB2_B_OUTSWAP_V << MCPWM_DB2_B_OUTSWAP_S) +#define MCPWM_DB2_B_OUTSWAP_V 0x00000001U +#define MCPWM_DB2_B_OUTSWAP_S 10 +/** MCPWM_DB2_RED_INSEL : R/W; bitpos: [11]; default: 0; + * S4 in table + */ +#define MCPWM_DB2_RED_INSEL (BIT(11)) +#define MCPWM_DB2_RED_INSEL_M (MCPWM_DB2_RED_INSEL_V << MCPWM_DB2_RED_INSEL_S) +#define MCPWM_DB2_RED_INSEL_V 0x00000001U +#define MCPWM_DB2_RED_INSEL_S 11 +/** MCPWM_DB2_FED_INSEL : R/W; bitpos: [12]; default: 0; + * S5 in table + */ +#define MCPWM_DB2_FED_INSEL (BIT(12)) +#define MCPWM_DB2_FED_INSEL_M (MCPWM_DB2_FED_INSEL_V << MCPWM_DB2_FED_INSEL_S) +#define MCPWM_DB2_FED_INSEL_V 0x00000001U +#define MCPWM_DB2_FED_INSEL_S 12 +/** MCPWM_DB2_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; + * S2 in table + */ +#define MCPWM_DB2_RED_OUTINVERT (BIT(13)) +#define MCPWM_DB2_RED_OUTINVERT_M (MCPWM_DB2_RED_OUTINVERT_V << MCPWM_DB2_RED_OUTINVERT_S) +#define MCPWM_DB2_RED_OUTINVERT_V 0x00000001U +#define MCPWM_DB2_RED_OUTINVERT_S 13 +/** MCPWM_DB2_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; + * S3 in table + */ +#define MCPWM_DB2_FED_OUTINVERT (BIT(14)) +#define MCPWM_DB2_FED_OUTINVERT_M (MCPWM_DB2_FED_OUTINVERT_V << MCPWM_DB2_FED_OUTINVERT_S) +#define MCPWM_DB2_FED_OUTINVERT_V 0x00000001U +#define MCPWM_DB2_FED_OUTINVERT_S 14 +/** MCPWM_DB2_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; + * S1 in table + */ +#define MCPWM_DB2_A_OUTBYPASS (BIT(15)) +#define MCPWM_DB2_A_OUTBYPASS_M (MCPWM_DB2_A_OUTBYPASS_V << MCPWM_DB2_A_OUTBYPASS_S) +#define MCPWM_DB2_A_OUTBYPASS_V 0x00000001U +#define MCPWM_DB2_A_OUTBYPASS_S 15 +/** MCPWM_DB2_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; + * S0 in table + */ +#define MCPWM_DB2_B_OUTBYPASS (BIT(16)) +#define MCPWM_DB2_B_OUTBYPASS_M (MCPWM_DB2_B_OUTBYPASS_V << MCPWM_DB2_B_OUTBYPASS_S) +#define MCPWM_DB2_B_OUTBYPASS_V 0x00000001U +#define MCPWM_DB2_B_OUTBYPASS_S 16 +/** MCPWM_DB2_CLK_SEL : R/W; bitpos: [17]; default: 0; + * Dead time generator 2 clock selection. 0: PWM_clk, 1: PT_clk + */ +#define MCPWM_DB2_CLK_SEL (BIT(17)) +#define MCPWM_DB2_CLK_SEL_M (MCPWM_DB2_CLK_SEL_V << MCPWM_DB2_CLK_SEL_S) +#define MCPWM_DB2_CLK_SEL_V 0x00000001U +#define MCPWM_DB2_CLK_SEL_S 17 + +/** MCPWM_DT2_FED_CFG_REG register + * Shadow register for falling edge delay (FED). + */ +#define MCPWM_DT2_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xcc) +/** MCPWM_DB2_FED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for FED + */ +#define MCPWM_DB2_FED 0x0000FFFFU +#define MCPWM_DB2_FED_M (MCPWM_DB2_FED_V << MCPWM_DB2_FED_S) +#define MCPWM_DB2_FED_V 0x0000FFFFU +#define MCPWM_DB2_FED_S 0 + +/** MCPWM_DT2_RED_CFG_REG register + * Shadow register for rising edge delay (RED). + */ +#define MCPWM_DT2_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xd0) +/** MCPWM_DB2_RED : R/W; bitpos: [15:0]; default: 0; + * Shadow register for RED + */ +#define MCPWM_DB2_RED 0x0000FFFFU +#define MCPWM_DB2_RED_M (MCPWM_DB2_RED_V << MCPWM_DB2_RED_S) +#define MCPWM_DB2_RED_V 0x0000FFFFU +#define MCPWM_DB2_RED_S 0 + +/** MCPWM_CARRIER2_CFG_REG register + * Carrier enable and configuratoin + */ +#define MCPWM_CARRIER2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xd4) +/** MCPWM_CHOPPER2_EN : R/W; bitpos: [0]; default: 0; + * When set, carrier2 function is enabled. When cleared, carrier2 is bypassed + */ +#define MCPWM_CHOPPER2_EN (BIT(0)) +#define MCPWM_CHOPPER2_EN_M (MCPWM_CHOPPER2_EN_V << MCPWM_CHOPPER2_EN_S) +#define MCPWM_CHOPPER2_EN_V 0x00000001U +#define MCPWM_CHOPPER2_EN_S 0 +/** MCPWM_CHOPPER2_PRESCALE : R/W; bitpos: [4:1]; default: 0; + * PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * + * (PWM_CARRIER0_PRESCALE + 1) + */ +#define MCPWM_CHOPPER2_PRESCALE 0x0000000FU +#define MCPWM_CHOPPER2_PRESCALE_M (MCPWM_CHOPPER2_PRESCALE_V << MCPWM_CHOPPER2_PRESCALE_S) +#define MCPWM_CHOPPER2_PRESCALE_V 0x0000000FU +#define MCPWM_CHOPPER2_PRESCALE_S 1 +/** MCPWM_CHOPPER2_DUTY : R/W; bitpos: [7:5]; default: 0; + * carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + */ +#define MCPWM_CHOPPER2_DUTY 0x00000007U +#define MCPWM_CHOPPER2_DUTY_M (MCPWM_CHOPPER2_DUTY_V << MCPWM_CHOPPER2_DUTY_S) +#define MCPWM_CHOPPER2_DUTY_V 0x00000007U +#define MCPWM_CHOPPER2_DUTY_S 5 +/** MCPWM_CHOPPER2_OSHTWTH : R/W; bitpos: [11:8]; default: 0; + * width of the first pulse in number of periods of the carrier + */ +#define MCPWM_CHOPPER2_OSHTWTH 0x0000000FU +#define MCPWM_CHOPPER2_OSHTWTH_M (MCPWM_CHOPPER2_OSHTWTH_V << MCPWM_CHOPPER2_OSHTWTH_S) +#define MCPWM_CHOPPER2_OSHTWTH_V 0x0000000FU +#define MCPWM_CHOPPER2_OSHTWTH_S 8 +/** MCPWM_CHOPPER2_OUT_INVERT : R/W; bitpos: [12]; default: 0; + * when set, invert the output of PWM2A and PWM2B for this submodule + */ +#define MCPWM_CHOPPER2_OUT_INVERT (BIT(12)) +#define MCPWM_CHOPPER2_OUT_INVERT_M (MCPWM_CHOPPER2_OUT_INVERT_V << MCPWM_CHOPPER2_OUT_INVERT_S) +#define MCPWM_CHOPPER2_OUT_INVERT_V 0x00000001U +#define MCPWM_CHOPPER2_OUT_INVERT_S 12 +/** MCPWM_CHOPPER2_IN_INVERT : R/W; bitpos: [13]; default: 0; + * when set, invert the input of PWM2A and PWM2B for this submodule + */ +#define MCPWM_CHOPPER2_IN_INVERT (BIT(13)) +#define MCPWM_CHOPPER2_IN_INVERT_M (MCPWM_CHOPPER2_IN_INVERT_V << MCPWM_CHOPPER2_IN_INVERT_S) +#define MCPWM_CHOPPER2_IN_INVERT_V 0x00000001U +#define MCPWM_CHOPPER2_IN_INVERT_S 13 + +/** MCPWM_FH2_CFG0_REG register + * Actions on PWM2A and PWM2B trip events + */ +#define MCPWM_FH2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xd8) +/** MCPWM_TZ2_SW_CBC : R/W; bitpos: [0]; default: 0; + * Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ2_SW_CBC (BIT(0)) +#define MCPWM_TZ2_SW_CBC_M (MCPWM_TZ2_SW_CBC_V << MCPWM_TZ2_SW_CBC_S) +#define MCPWM_TZ2_SW_CBC_V 0x00000001U +#define MCPWM_TZ2_SW_CBC_S 0 +/** MCPWM_TZ2_F2_CBC : R/W; bitpos: [1]; default: 0; + * event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ2_F2_CBC (BIT(1)) +#define MCPWM_TZ2_F2_CBC_M (MCPWM_TZ2_F2_CBC_V << MCPWM_TZ2_F2_CBC_S) +#define MCPWM_TZ2_F2_CBC_V 0x00000001U +#define MCPWM_TZ2_F2_CBC_S 1 +/** MCPWM_TZ2_F1_CBC : R/W; bitpos: [2]; default: 0; + * event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ2_F1_CBC (BIT(2)) +#define MCPWM_TZ2_F1_CBC_M (MCPWM_TZ2_F1_CBC_V << MCPWM_TZ2_F1_CBC_S) +#define MCPWM_TZ2_F1_CBC_V 0x00000001U +#define MCPWM_TZ2_F1_CBC_S 2 +/** MCPWM_TZ2_F0_CBC : R/W; bitpos: [3]; default: 0; + * event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ2_F0_CBC (BIT(3)) +#define MCPWM_TZ2_F0_CBC_M (MCPWM_TZ2_F0_CBC_V << MCPWM_TZ2_F0_CBC_S) +#define MCPWM_TZ2_F0_CBC_V 0x00000001U +#define MCPWM_TZ2_F0_CBC_S 3 +/** MCPWM_TZ2_SW_OST : R/W; bitpos: [4]; default: 0; + * Enable register for software force one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ2_SW_OST (BIT(4)) +#define MCPWM_TZ2_SW_OST_M (MCPWM_TZ2_SW_OST_V << MCPWM_TZ2_SW_OST_S) +#define MCPWM_TZ2_SW_OST_V 0x00000001U +#define MCPWM_TZ2_SW_OST_S 4 +/** MCPWM_TZ2_F2_OST : R/W; bitpos: [5]; default: 0; + * event_f2 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ2_F2_OST (BIT(5)) +#define MCPWM_TZ2_F2_OST_M (MCPWM_TZ2_F2_OST_V << MCPWM_TZ2_F2_OST_S) +#define MCPWM_TZ2_F2_OST_V 0x00000001U +#define MCPWM_TZ2_F2_OST_S 5 +/** MCPWM_TZ2_F1_OST : R/W; bitpos: [6]; default: 0; + * event_f1 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ2_F1_OST (BIT(6)) +#define MCPWM_TZ2_F1_OST_M (MCPWM_TZ2_F1_OST_V << MCPWM_TZ2_F1_OST_S) +#define MCPWM_TZ2_F1_OST_V 0x00000001U +#define MCPWM_TZ2_F1_OST_S 6 +/** MCPWM_TZ2_F0_OST : R/W; bitpos: [7]; default: 0; + * event_f0 will trigger one-shot mode action. 0: disable, 1: enable + */ +#define MCPWM_TZ2_F0_OST (BIT(7)) +#define MCPWM_TZ2_F0_OST_M (MCPWM_TZ2_F0_OST_V << MCPWM_TZ2_F0_OST_S) +#define MCPWM_TZ2_F0_OST_V 0x00000001U +#define MCPWM_TZ2_F0_OST_S 7 +/** MCPWM_TZ2_A_CBC_D : R/W; bitpos: [9:8]; default: 0; + * Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ2_A_CBC_D 0x00000003U +#define MCPWM_TZ2_A_CBC_D_M (MCPWM_TZ2_A_CBC_D_V << MCPWM_TZ2_A_CBC_D_S) +#define MCPWM_TZ2_A_CBC_D_V 0x00000003U +#define MCPWM_TZ2_A_CBC_D_S 8 +/** MCPWM_TZ2_A_CBC_U : R/W; bitpos: [11:10]; default: 0; + * Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ2_A_CBC_U 0x00000003U +#define MCPWM_TZ2_A_CBC_U_M (MCPWM_TZ2_A_CBC_U_V << MCPWM_TZ2_A_CBC_U_S) +#define MCPWM_TZ2_A_CBC_U_V 0x00000003U +#define MCPWM_TZ2_A_CBC_U_S 10 +/** MCPWM_TZ2_A_OST_D : R/W; bitpos: [13:12]; default: 0; + * One-shot mode action on PWM2A when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ2_A_OST_D 0x00000003U +#define MCPWM_TZ2_A_OST_D_M (MCPWM_TZ2_A_OST_D_V << MCPWM_TZ2_A_OST_D_S) +#define MCPWM_TZ2_A_OST_D_V 0x00000003U +#define MCPWM_TZ2_A_OST_D_S 12 +/** MCPWM_TZ2_A_OST_U : R/W; bitpos: [15:14]; default: 0; + * One-shot mode action on PWM2A when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ2_A_OST_U 0x00000003U +#define MCPWM_TZ2_A_OST_U_M (MCPWM_TZ2_A_OST_U_V << MCPWM_TZ2_A_OST_U_S) +#define MCPWM_TZ2_A_OST_U_V 0x00000003U +#define MCPWM_TZ2_A_OST_U_S 14 +/** MCPWM_TZ2_B_CBC_D : R/W; bitpos: [17:16]; default: 0; + * Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ2_B_CBC_D 0x00000003U +#define MCPWM_TZ2_B_CBC_D_M (MCPWM_TZ2_B_CBC_D_V << MCPWM_TZ2_B_CBC_D_S) +#define MCPWM_TZ2_B_CBC_D_V 0x00000003U +#define MCPWM_TZ2_B_CBC_D_S 16 +/** MCPWM_TZ2_B_CBC_U : R/W; bitpos: [19:18]; default: 0; + * Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ2_B_CBC_U 0x00000003U +#define MCPWM_TZ2_B_CBC_U_M (MCPWM_TZ2_B_CBC_U_V << MCPWM_TZ2_B_CBC_U_S) +#define MCPWM_TZ2_B_CBC_U_V 0x00000003U +#define MCPWM_TZ2_B_CBC_U_S 18 +/** MCPWM_TZ2_B_OST_D : R/W; bitpos: [21:20]; default: 0; + * One-shot mode action on PWM2B when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ2_B_OST_D 0x00000003U +#define MCPWM_TZ2_B_OST_D_M (MCPWM_TZ2_B_OST_D_V << MCPWM_TZ2_B_OST_D_S) +#define MCPWM_TZ2_B_OST_D_V 0x00000003U +#define MCPWM_TZ2_B_OST_D_S 20 +/** MCPWM_TZ2_B_OST_U : R/W; bitpos: [23:22]; default: 0; + * One-shot mode action on PWM2B when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ +#define MCPWM_TZ2_B_OST_U 0x00000003U +#define MCPWM_TZ2_B_OST_U_M (MCPWM_TZ2_B_OST_U_V << MCPWM_TZ2_B_OST_U_S) +#define MCPWM_TZ2_B_OST_U_V 0x00000003U +#define MCPWM_TZ2_B_OST_U_S 22 + +/** MCPWM_FH2_CFG1_REG register + * Software triggers for fault handler actions + */ +#define MCPWM_FH2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0xdc) +/** MCPWM_TZ2_CLR_OST : R/W; bitpos: [0]; default: 0; + * a rising edge will clear on going one-shot mode action + */ +#define MCPWM_TZ2_CLR_OST (BIT(0)) +#define MCPWM_TZ2_CLR_OST_M (MCPWM_TZ2_CLR_OST_V << MCPWM_TZ2_CLR_OST_S) +#define MCPWM_TZ2_CLR_OST_V 0x00000001U +#define MCPWM_TZ2_CLR_OST_S 0 +/** MCPWM_TZ2_CBCPULSE : R/W; bitpos: [2:1]; default: 0; + * cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, + * when bit1 is set to 1:TEP + */ +#define MCPWM_TZ2_CBCPULSE 0x00000003U +#define MCPWM_TZ2_CBCPULSE_M (MCPWM_TZ2_CBCPULSE_V << MCPWM_TZ2_CBCPULSE_S) +#define MCPWM_TZ2_CBCPULSE_V 0x00000003U +#define MCPWM_TZ2_CBCPULSE_S 1 +/** MCPWM_TZ2_FORCE_CBC : R/W; bitpos: [3]; default: 0; + * a toggle trigger a cycle-by-cycle mode action + */ +#define MCPWM_TZ2_FORCE_CBC (BIT(3)) +#define MCPWM_TZ2_FORCE_CBC_M (MCPWM_TZ2_FORCE_CBC_V << MCPWM_TZ2_FORCE_CBC_S) +#define MCPWM_TZ2_FORCE_CBC_V 0x00000001U +#define MCPWM_TZ2_FORCE_CBC_S 3 +/** MCPWM_TZ2_FORCE_OST : R/W; bitpos: [4]; default: 0; + * a toggle (software negate its value) triggers a one-shot mode action + */ +#define MCPWM_TZ2_FORCE_OST (BIT(4)) +#define MCPWM_TZ2_FORCE_OST_M (MCPWM_TZ2_FORCE_OST_V << MCPWM_TZ2_FORCE_OST_S) +#define MCPWM_TZ2_FORCE_OST_V 0x00000001U +#define MCPWM_TZ2_FORCE_OST_S 4 + +/** MCPWM_FH2_STATUS_REG register + * Status of fault events. + */ +#define MCPWM_FH2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xe0) +/** MCPWM_TZ2_CBC_ON : RO; bitpos: [0]; default: 0; + * Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + */ +#define MCPWM_TZ2_CBC_ON (BIT(0)) +#define MCPWM_TZ2_CBC_ON_M (MCPWM_TZ2_CBC_ON_V << MCPWM_TZ2_CBC_ON_S) +#define MCPWM_TZ2_CBC_ON_V 0x00000001U +#define MCPWM_TZ2_CBC_ON_S 0 +/** MCPWM_TZ2_OST_ON : RO; bitpos: [1]; default: 0; + * Set and reset by hardware. If set, an one-shot mode action is on going + */ +#define MCPWM_TZ2_OST_ON (BIT(1)) +#define MCPWM_TZ2_OST_ON_M (MCPWM_TZ2_OST_ON_V << MCPWM_TZ2_OST_ON_S) +#define MCPWM_TZ2_OST_ON_V 0x00000001U +#define MCPWM_TZ2_OST_ON_S 1 + +/** MCPWM_FAULT_DETECT_REG register + * Fault detection configuration and status + */ +#define MCPWM_FAULT_DETECT_REG(i) (REG_MCPWM_BASE(i) + 0xe4) +/** MCPWM_F0_EN : R/W; bitpos: [0]; default: 0; + * When set, event_f0 generation is enabled + */ +#define MCPWM_F0_EN (BIT(0)) +#define MCPWM_F0_EN_M (MCPWM_F0_EN_V << MCPWM_F0_EN_S) +#define MCPWM_F0_EN_V 0x00000001U +#define MCPWM_F0_EN_S 0 +/** MCPWM_F1_EN : R/W; bitpos: [1]; default: 0; + * When set, event_f1 generation is enabled + */ +#define MCPWM_F1_EN (BIT(1)) +#define MCPWM_F1_EN_M (MCPWM_F1_EN_V << MCPWM_F1_EN_S) +#define MCPWM_F1_EN_V 0x00000001U +#define MCPWM_F1_EN_S 1 +/** MCPWM_F2_EN : R/W; bitpos: [2]; default: 0; + * When set, event_f2 generation is enabled + */ +#define MCPWM_F2_EN (BIT(2)) +#define MCPWM_F2_EN_M (MCPWM_F2_EN_V << MCPWM_F2_EN_S) +#define MCPWM_F2_EN_V 0x00000001U +#define MCPWM_F2_EN_S 2 +/** MCPWM_F0_POLE : R/W; bitpos: [3]; default: 0; + * Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: + * level high + */ +#define MCPWM_F0_POLE (BIT(3)) +#define MCPWM_F0_POLE_M (MCPWM_F0_POLE_V << MCPWM_F0_POLE_S) +#define MCPWM_F0_POLE_V 0x00000001U +#define MCPWM_F0_POLE_S 3 +/** MCPWM_F1_POLE : R/W; bitpos: [4]; default: 0; + * Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: + * level high + */ +#define MCPWM_F1_POLE (BIT(4)) +#define MCPWM_F1_POLE_M (MCPWM_F1_POLE_V << MCPWM_F1_POLE_S) +#define MCPWM_F1_POLE_V 0x00000001U +#define MCPWM_F1_POLE_S 4 +/** MCPWM_F2_POLE : R/W; bitpos: [5]; default: 0; + * Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: + * level high + */ +#define MCPWM_F2_POLE (BIT(5)) +#define MCPWM_F2_POLE_M (MCPWM_F2_POLE_V << MCPWM_F2_POLE_S) +#define MCPWM_F2_POLE_V 0x00000001U +#define MCPWM_F2_POLE_S 5 +/** MCPWM_EVENT_F0 : RO; bitpos: [6]; default: 0; + * Set and reset by hardware. If set, event_f0 is on going + */ +#define MCPWM_EVENT_F0 (BIT(6)) +#define MCPWM_EVENT_F0_M (MCPWM_EVENT_F0_V << MCPWM_EVENT_F0_S) +#define MCPWM_EVENT_F0_V 0x00000001U +#define MCPWM_EVENT_F0_S 6 +/** MCPWM_EVENT_F1 : RO; bitpos: [7]; default: 0; + * Set and reset by hardware. If set, event_f1 is on going + */ +#define MCPWM_EVENT_F1 (BIT(7)) +#define MCPWM_EVENT_F1_M (MCPWM_EVENT_F1_V << MCPWM_EVENT_F1_S) +#define MCPWM_EVENT_F1_V 0x00000001U +#define MCPWM_EVENT_F1_S 7 +/** MCPWM_EVENT_F2 : RO; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, event_f2 is on going + */ +#define MCPWM_EVENT_F2 (BIT(8)) +#define MCPWM_EVENT_F2_M (MCPWM_EVENT_F2_V << MCPWM_EVENT_F2_S) +#define MCPWM_EVENT_F2_V 0x00000001U +#define MCPWM_EVENT_F2_S 8 + +/** MCPWM_CAP_TIMER_CFG_REG register + * Configure capture timer + */ +#define MCPWM_CAP_TIMER_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xe8) +/** MCPWM_CAP_TIMER_EN : R/W; bitpos: [0]; default: 0; + * When set, capture timer incrementing under APB_clk is enabled. + */ +#define MCPWM_CAP_TIMER_EN (BIT(0)) +#define MCPWM_CAP_TIMER_EN_M (MCPWM_CAP_TIMER_EN_V << MCPWM_CAP_TIMER_EN_S) +#define MCPWM_CAP_TIMER_EN_V 0x00000001U +#define MCPWM_CAP_TIMER_EN_S 0 +/** MCPWM_CAP_SYNCI_EN : R/W; bitpos: [1]; default: 0; + * When set, capture timer sync is enabled. + */ +#define MCPWM_CAP_SYNCI_EN (BIT(1)) +#define MCPWM_CAP_SYNCI_EN_M (MCPWM_CAP_SYNCI_EN_V << MCPWM_CAP_SYNCI_EN_S) +#define MCPWM_CAP_SYNCI_EN_V 0x00000001U +#define MCPWM_CAP_SYNCI_EN_S 1 +/** MCPWM_CAP_SYNCI_SEL : R/W; bitpos: [4:2]; default: 0; + * capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 + * sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, + * 6: SYNC2 from GPIO matrix + */ +#define MCPWM_CAP_SYNCI_SEL 0x00000007U +#define MCPWM_CAP_SYNCI_SEL_M (MCPWM_CAP_SYNCI_SEL_V << MCPWM_CAP_SYNCI_SEL_S) +#define MCPWM_CAP_SYNCI_SEL_V 0x00000007U +#define MCPWM_CAP_SYNCI_SEL_S 2 +/** MCPWM_CAP_SYNC_SW : WT; bitpos: [5]; default: 0; + * When reg_cap_synci_en is 1, write 1 will trigger a capture timer sync, capture + * timer is loaded with value in phase register. + */ +#define MCPWM_CAP_SYNC_SW (BIT(5)) +#define MCPWM_CAP_SYNC_SW_M (MCPWM_CAP_SYNC_SW_V << MCPWM_CAP_SYNC_SW_S) +#define MCPWM_CAP_SYNC_SW_V 0x00000001U +#define MCPWM_CAP_SYNC_SW_S 5 + +/** MCPWM_CAP_TIMER_PHASE_REG register + * Phase for capture timer sync + */ +#define MCPWM_CAP_TIMER_PHASE_REG(i) (REG_MCPWM_BASE(i) + 0xec) +/** MCPWM_CAP_PHASE : R/W; bitpos: [31:0]; default: 0; + * Phase value for capture timer sync operation. + */ +#define MCPWM_CAP_PHASE 0xFFFFFFFFU +#define MCPWM_CAP_PHASE_M (MCPWM_CAP_PHASE_V << MCPWM_CAP_PHASE_S) +#define MCPWM_CAP_PHASE_V 0xFFFFFFFFU +#define MCPWM_CAP_PHASE_S 0 + +/** MCPWM_CAP_CH0_CFG_REG register + * Capture channel 0 configuration and enable + */ +#define MCPWM_CAP_CH0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf0) +/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0; + * When set, capture on channel 0 is enabled + */ +#define MCPWM_CAP0_EN (BIT(0)) +#define MCPWM_CAP0_EN_M (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S) +#define MCPWM_CAP0_EN_V 0x00000001U +#define MCPWM_CAP0_EN_S 0 +/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0; + * Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable + * capture on the negative edge, When bit1 is set to 1: enable capture on the positive + * edge. + */ +#define MCPWM_CAP0_MODE 0x00000003U +#define MCPWM_CAP0_MODE_M (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S) +#define MCPWM_CAP0_MODE_V 0x00000003U +#define MCPWM_CAP0_MODE_S 1 +/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0; + * Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + + * 1 + */ +#define MCPWM_CAP0_PRESCALE 0x000000FFU +#define MCPWM_CAP0_PRESCALE_M (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S) +#define MCPWM_CAP0_PRESCALE_V 0x000000FFU +#define MCPWM_CAP0_PRESCALE_S 3 +/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0; + * when set, CAP0 form GPIO matrix is inverted before prescale + */ +#define MCPWM_CAP0_IN_INVERT (BIT(11)) +#define MCPWM_CAP0_IN_INVERT_M (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S) +#define MCPWM_CAP0_IN_INVERT_V 0x00000001U +#define MCPWM_CAP0_IN_INVERT_S 11 +/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0; + * Write 1 will trigger a software forced capture on channel 0 + */ +#define MCPWM_CAP0_SW (BIT(12)) +#define MCPWM_CAP0_SW_M (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S) +#define MCPWM_CAP0_SW_V 0x00000001U +#define MCPWM_CAP0_SW_S 12 + +/** MCPWM_CAP_CH1_CFG_REG register + * Capture channel 1 configuration and enable + */ +#define MCPWM_CAP_CH1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf4) +/** MCPWM_CAP1_EN : R/W; bitpos: [0]; default: 0; + * When set, capture on channel 2 is enabled + */ +#define MCPWM_CAP1_EN (BIT(0)) +#define MCPWM_CAP1_EN_M (MCPWM_CAP1_EN_V << MCPWM_CAP1_EN_S) +#define MCPWM_CAP1_EN_V 0x00000001U +#define MCPWM_CAP1_EN_S 0 +/** MCPWM_CAP1_MODE : R/W; bitpos: [2:1]; default: 0; + * Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable + * capture on the negative edge, When bit1 is set to 1: enable capture on the positive + * edge. + */ +#define MCPWM_CAP1_MODE 0x00000003U +#define MCPWM_CAP1_MODE_M (MCPWM_CAP1_MODE_V << MCPWM_CAP1_MODE_S) +#define MCPWM_CAP1_MODE_V 0x00000003U +#define MCPWM_CAP1_MODE_S 1 +/** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0; + * Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + + * 1 + */ +#define MCPWM_CAP1_PRESCALE 0x000000FFU +#define MCPWM_CAP1_PRESCALE_M (MCPWM_CAP1_PRESCALE_V << MCPWM_CAP1_PRESCALE_S) +#define MCPWM_CAP1_PRESCALE_V 0x000000FFU +#define MCPWM_CAP1_PRESCALE_S 3 +/** MCPWM_CAP1_IN_INVERT : R/W; bitpos: [11]; default: 0; + * when set, CAP1 form GPIO matrix is inverted before prescale + */ +#define MCPWM_CAP1_IN_INVERT (BIT(11)) +#define MCPWM_CAP1_IN_INVERT_M (MCPWM_CAP1_IN_INVERT_V << MCPWM_CAP1_IN_INVERT_S) +#define MCPWM_CAP1_IN_INVERT_V 0x00000001U +#define MCPWM_CAP1_IN_INVERT_S 11 +/** MCPWM_CAP1_SW : WT; bitpos: [12]; default: 0; + * Write 1 will trigger a software forced capture on channel 1 + */ +#define MCPWM_CAP1_SW (BIT(12)) +#define MCPWM_CAP1_SW_M (MCPWM_CAP1_SW_V << MCPWM_CAP1_SW_S) +#define MCPWM_CAP1_SW_V 0x00000001U +#define MCPWM_CAP1_SW_S 12 + +/** MCPWM_CAP_CH2_CFG_REG register + * Capture channel 2 configuration and enable + */ +#define MCPWM_CAP_CH2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf8) +/** MCPWM_CAP2_EN : R/W; bitpos: [0]; default: 0; + * When set, capture on channel 2 is enabled + */ +#define MCPWM_CAP2_EN (BIT(0)) +#define MCPWM_CAP2_EN_M (MCPWM_CAP2_EN_V << MCPWM_CAP2_EN_S) +#define MCPWM_CAP2_EN_V 0x00000001U +#define MCPWM_CAP2_EN_S 0 +/** MCPWM_CAP2_MODE : R/W; bitpos: [2:1]; default: 0; + * Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable + * capture on the negative edge, When bit1 is set to 1: enable capture on the positive + * edge. + */ +#define MCPWM_CAP2_MODE 0x00000003U +#define MCPWM_CAP2_MODE_M (MCPWM_CAP2_MODE_V << MCPWM_CAP2_MODE_S) +#define MCPWM_CAP2_MODE_V 0x00000003U +#define MCPWM_CAP2_MODE_S 1 +/** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0; + * Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE + + * 1 + */ +#define MCPWM_CAP2_PRESCALE 0x000000FFU +#define MCPWM_CAP2_PRESCALE_M (MCPWM_CAP2_PRESCALE_V << MCPWM_CAP2_PRESCALE_S) +#define MCPWM_CAP2_PRESCALE_V 0x000000FFU +#define MCPWM_CAP2_PRESCALE_S 3 +/** MCPWM_CAP2_IN_INVERT : R/W; bitpos: [11]; default: 0; + * when set, CAP2 form GPIO matrix is inverted before prescale + */ +#define MCPWM_CAP2_IN_INVERT (BIT(11)) +#define MCPWM_CAP2_IN_INVERT_M (MCPWM_CAP2_IN_INVERT_V << MCPWM_CAP2_IN_INVERT_S) +#define MCPWM_CAP2_IN_INVERT_V 0x00000001U +#define MCPWM_CAP2_IN_INVERT_S 11 +/** MCPWM_CAP2_SW : WT; bitpos: [12]; default: 0; + * Write 1 will trigger a software forced capture on channel 2 + */ +#define MCPWM_CAP2_SW (BIT(12)) +#define MCPWM_CAP2_SW_M (MCPWM_CAP2_SW_V << MCPWM_CAP2_SW_S) +#define MCPWM_CAP2_SW_V 0x00000001U +#define MCPWM_CAP2_SW_S 12 + +/** MCPWM_CAP_CH0_REG register + * ch0 capture value status register + */ +#define MCPWM_CAP_CH0_REG(i) (REG_MCPWM_BASE(i) + 0xfc) +/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0; + * Value of last capture on channel 0 + */ +#define MCPWM_CAP0_VALUE 0xFFFFFFFFU +#define MCPWM_CAP0_VALUE_M (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S) +#define MCPWM_CAP0_VALUE_V 0xFFFFFFFFU +#define MCPWM_CAP0_VALUE_S 0 + +/** MCPWM_CAP_CH1_REG register + * ch1 capture value status register + */ +#define MCPWM_CAP_CH1_REG(i) (REG_MCPWM_BASE(i) + 0x100) +/** MCPWM_CAP1_VALUE : RO; bitpos: [31:0]; default: 0; + * Value of last capture on channel 1 + */ +#define MCPWM_CAP1_VALUE 0xFFFFFFFFU +#define MCPWM_CAP1_VALUE_M (MCPWM_CAP1_VALUE_V << MCPWM_CAP1_VALUE_S) +#define MCPWM_CAP1_VALUE_V 0xFFFFFFFFU +#define MCPWM_CAP1_VALUE_S 0 + +/** MCPWM_CAP_CH2_REG register + * ch2 capture value status register + */ +#define MCPWM_CAP_CH2_REG(i) (REG_MCPWM_BASE(i) + 0x104) +/** MCPWM_CAP2_VALUE : RO; bitpos: [31:0]; default: 0; + * Value of last capture on channel 2 + */ +#define MCPWM_CAP2_VALUE 0xFFFFFFFFU +#define MCPWM_CAP2_VALUE_M (MCPWM_CAP2_VALUE_V << MCPWM_CAP2_VALUE_S) +#define MCPWM_CAP2_VALUE_V 0xFFFFFFFFU +#define MCPWM_CAP2_VALUE_S 0 + +/** MCPWM_CAP_STATUS_REG register + * Edge of last capture trigger + */ +#define MCPWM_CAP_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x108) +/** MCPWM_CAP0_EDGE : RO; bitpos: [0]; default: 0; + * Edge of last capture trigger on channel 0, 0: posedge, 1: negedge + */ +#define MCPWM_CAP0_EDGE (BIT(0)) +#define MCPWM_CAP0_EDGE_M (MCPWM_CAP0_EDGE_V << MCPWM_CAP0_EDGE_S) +#define MCPWM_CAP0_EDGE_V 0x00000001U +#define MCPWM_CAP0_EDGE_S 0 +/** MCPWM_CAP1_EDGE : RO; bitpos: [1]; default: 0; + * Edge of last capture trigger on channel 1, 0: posedge, 1: negedge + */ +#define MCPWM_CAP1_EDGE (BIT(1)) +#define MCPWM_CAP1_EDGE_M (MCPWM_CAP1_EDGE_V << MCPWM_CAP1_EDGE_S) +#define MCPWM_CAP1_EDGE_V 0x00000001U +#define MCPWM_CAP1_EDGE_S 1 +/** MCPWM_CAP2_EDGE : RO; bitpos: [2]; default: 0; + * Edge of last capture trigger on channel 2, 0: posedge, 1: negedge + */ +#define MCPWM_CAP2_EDGE (BIT(2)) +#define MCPWM_CAP2_EDGE_M (MCPWM_CAP2_EDGE_V << MCPWM_CAP2_EDGE_S) +#define MCPWM_CAP2_EDGE_V 0x00000001U +#define MCPWM_CAP2_EDGE_S 2 + +/** MCPWM_UPDATE_CFG_REG register + * Enable update. + */ +#define MCPWM_UPDATE_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x10c) +/** MCPWM_GLOBAL_UP_EN : R/W; bitpos: [0]; default: 1; + * The global enable of update of all active registers in MCPWM module + */ +#define MCPWM_GLOBAL_UP_EN (BIT(0)) +#define MCPWM_GLOBAL_UP_EN_M (MCPWM_GLOBAL_UP_EN_V << MCPWM_GLOBAL_UP_EN_S) +#define MCPWM_GLOBAL_UP_EN_V 0x00000001U +#define MCPWM_GLOBAL_UP_EN_S 0 +/** MCPWM_GLOBAL_FORCE_UP : R/W; bitpos: [1]; default: 0; + * a toggle (software invert its value) will trigger a forced update of all active + * registers in MCPWM module + */ +#define MCPWM_GLOBAL_FORCE_UP (BIT(1)) +#define MCPWM_GLOBAL_FORCE_UP_M (MCPWM_GLOBAL_FORCE_UP_V << MCPWM_GLOBAL_FORCE_UP_S) +#define MCPWM_GLOBAL_FORCE_UP_V 0x00000001U +#define MCPWM_GLOBAL_FORCE_UP_S 1 +/** MCPWM_OP0_UP_EN : R/W; bitpos: [2]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 + * are enabled + */ +#define MCPWM_OP0_UP_EN (BIT(2)) +#define MCPWM_OP0_UP_EN_M (MCPWM_OP0_UP_EN_V << MCPWM_OP0_UP_EN_S) +#define MCPWM_OP0_UP_EN_V 0x00000001U +#define MCPWM_OP0_UP_EN_S 2 +/** MCPWM_OP0_FORCE_UP : R/W; bitpos: [3]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 0 + */ +#define MCPWM_OP0_FORCE_UP (BIT(3)) +#define MCPWM_OP0_FORCE_UP_M (MCPWM_OP0_FORCE_UP_V << MCPWM_OP0_FORCE_UP_S) +#define MCPWM_OP0_FORCE_UP_V 0x00000001U +#define MCPWM_OP0_FORCE_UP_S 3 +/** MCPWM_OP1_UP_EN : R/W; bitpos: [4]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 + * are enabled + */ +#define MCPWM_OP1_UP_EN (BIT(4)) +#define MCPWM_OP1_UP_EN_M (MCPWM_OP1_UP_EN_V << MCPWM_OP1_UP_EN_S) +#define MCPWM_OP1_UP_EN_V 0x00000001U +#define MCPWM_OP1_UP_EN_S 4 +/** MCPWM_OP1_FORCE_UP : R/W; bitpos: [5]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 1 + */ +#define MCPWM_OP1_FORCE_UP (BIT(5)) +#define MCPWM_OP1_FORCE_UP_M (MCPWM_OP1_FORCE_UP_V << MCPWM_OP1_FORCE_UP_S) +#define MCPWM_OP1_FORCE_UP_V 0x00000001U +#define MCPWM_OP1_FORCE_UP_S 5 +/** MCPWM_OP2_UP_EN : R/W; bitpos: [6]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 + * are enabled + */ +#define MCPWM_OP2_UP_EN (BIT(6)) +#define MCPWM_OP2_UP_EN_M (MCPWM_OP2_UP_EN_V << MCPWM_OP2_UP_EN_S) +#define MCPWM_OP2_UP_EN_V 0x00000001U +#define MCPWM_OP2_UP_EN_S 6 +/** MCPWM_OP2_FORCE_UP : R/W; bitpos: [7]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 2 + */ +#define MCPWM_OP2_FORCE_UP (BIT(7)) +#define MCPWM_OP2_FORCE_UP_M (MCPWM_OP2_FORCE_UP_V << MCPWM_OP2_FORCE_UP_S) +#define MCPWM_OP2_FORCE_UP_V 0x00000001U +#define MCPWM_OP2_FORCE_UP_S 7 + +/** MCPWM_INT_ENA_REG register + * Interrupt enable bits + */ +#define MCPWM_INT_ENA_REG(i) (REG_MCPWM_BASE(i) + 0x110) +/** MCPWM_TIMER0_STOP_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable bit for the interrupt triggered when the timer 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_ENA (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ENA_M (MCPWM_TIMER0_STOP_INT_ENA_V << MCPWM_TIMER0_STOP_INT_ENA_S) +#define MCPWM_TIMER0_STOP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER0_STOP_INT_ENA_S 0 +/** MCPWM_TIMER1_STOP_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable bit for the interrupt triggered when the timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_ENA (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ENA_M (MCPWM_TIMER1_STOP_INT_ENA_V << MCPWM_TIMER1_STOP_INT_ENA_S) +#define MCPWM_TIMER1_STOP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_ENA_S 1 +/** MCPWM_TIMER2_STOP_INT_ENA : R/W; bitpos: [2]; default: 0; + * The enable bit for the interrupt triggered when the timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_ENA (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ENA_M (MCPWM_TIMER2_STOP_INT_ENA_V << MCPWM_TIMER2_STOP_INT_ENA_S) +#define MCPWM_TIMER2_STOP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_ENA_S 2 +/** MCPWM_TIMER0_TEZ_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_ENA (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ENA_M (MCPWM_TIMER0_TEZ_INT_ENA_V << MCPWM_TIMER0_TEZ_INT_ENA_S) +#define MCPWM_TIMER0_TEZ_INT_ENA_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_ENA_S 3 +/** MCPWM_TIMER1_TEZ_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_ENA (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ENA_M (MCPWM_TIMER1_TEZ_INT_ENA_V << MCPWM_TIMER1_TEZ_INT_ENA_S) +#define MCPWM_TIMER1_TEZ_INT_ENA_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_ENA_S 4 +/** MCPWM_TIMER2_TEZ_INT_ENA : R/W; bitpos: [5]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_ENA (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ENA_M (MCPWM_TIMER2_TEZ_INT_ENA_V << MCPWM_TIMER2_TEZ_INT_ENA_S) +#define MCPWM_TIMER2_TEZ_INT_ENA_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_ENA_S 5 +/** MCPWM_TIMER0_TEP_INT_ENA : R/W; bitpos: [6]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_ENA (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ENA_M (MCPWM_TIMER0_TEP_INT_ENA_V << MCPWM_TIMER0_TEP_INT_ENA_S) +#define MCPWM_TIMER0_TEP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_ENA_S 6 +/** MCPWM_TIMER1_TEP_INT_ENA : R/W; bitpos: [7]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_ENA (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ENA_M (MCPWM_TIMER1_TEP_INT_ENA_V << MCPWM_TIMER1_TEP_INT_ENA_S) +#define MCPWM_TIMER1_TEP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_ENA_S 7 +/** MCPWM_TIMER2_TEP_INT_ENA : R/W; bitpos: [8]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_ENA (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ENA_M (MCPWM_TIMER2_TEP_INT_ENA_V << MCPWM_TIMER2_TEP_INT_ENA_S) +#define MCPWM_TIMER2_TEP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_ENA_S 8 +/** MCPWM_FAULT0_INT_ENA : R/W; bitpos: [9]; default: 0; + * The enable bit for the interrupt triggered when event_f0 starts. + */ +#define MCPWM_FAULT0_INT_ENA (BIT(9)) +#define MCPWM_FAULT0_INT_ENA_M (MCPWM_FAULT0_INT_ENA_V << MCPWM_FAULT0_INT_ENA_S) +#define MCPWM_FAULT0_INT_ENA_V 0x00000001U +#define MCPWM_FAULT0_INT_ENA_S 9 +/** MCPWM_FAULT1_INT_ENA : R/W; bitpos: [10]; default: 0; + * The enable bit for the interrupt triggered when event_f1 starts. + */ +#define MCPWM_FAULT1_INT_ENA (BIT(10)) +#define MCPWM_FAULT1_INT_ENA_M (MCPWM_FAULT1_INT_ENA_V << MCPWM_FAULT1_INT_ENA_S) +#define MCPWM_FAULT1_INT_ENA_V 0x00000001U +#define MCPWM_FAULT1_INT_ENA_S 10 +/** MCPWM_FAULT2_INT_ENA : R/W; bitpos: [11]; default: 0; + * The enable bit for the interrupt triggered when event_f2 starts. + */ +#define MCPWM_FAULT2_INT_ENA (BIT(11)) +#define MCPWM_FAULT2_INT_ENA_M (MCPWM_FAULT2_INT_ENA_V << MCPWM_FAULT2_INT_ENA_S) +#define MCPWM_FAULT2_INT_ENA_V 0x00000001U +#define MCPWM_FAULT2_INT_ENA_S 11 +/** MCPWM_FAULT0_CLR_INT_ENA : R/W; bitpos: [12]; default: 0; + * The enable bit for the interrupt triggered when event_f0 ends. + */ +#define MCPWM_FAULT0_CLR_INT_ENA (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ENA_M (MCPWM_FAULT0_CLR_INT_ENA_V << MCPWM_FAULT0_CLR_INT_ENA_S) +#define MCPWM_FAULT0_CLR_INT_ENA_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_ENA_S 12 +/** MCPWM_FAULT1_CLR_INT_ENA : R/W; bitpos: [13]; default: 0; + * The enable bit for the interrupt triggered when event_f1 ends. + */ +#define MCPWM_FAULT1_CLR_INT_ENA (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ENA_M (MCPWM_FAULT1_CLR_INT_ENA_V << MCPWM_FAULT1_CLR_INT_ENA_S) +#define MCPWM_FAULT1_CLR_INT_ENA_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_ENA_S 13 +/** MCPWM_FAULT2_CLR_INT_ENA : R/W; bitpos: [14]; default: 0; + * The enable bit for the interrupt triggered when event_f2 ends. + */ +#define MCPWM_FAULT2_CLR_INT_ENA (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ENA_M (MCPWM_FAULT2_CLR_INT_ENA_V << MCPWM_FAULT2_CLR_INT_ENA_S) +#define MCPWM_FAULT2_CLR_INT_ENA_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_ENA_S 14 +/** MCPWM_CMPR0_TEA_INT_ENA : R/W; bitpos: [15]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 0 TEA event + */ +#define MCPWM_CMPR0_TEA_INT_ENA (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_ENA_M (MCPWM_CMPR0_TEA_INT_ENA_V << MCPWM_CMPR0_TEA_INT_ENA_S) +#define MCPWM_CMPR0_TEA_INT_ENA_V 0x00000001U +#define MCPWM_CMPR0_TEA_INT_ENA_S 15 +/** MCPWM_CMPR1_TEA_INT_ENA : R/W; bitpos: [16]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 1 TEA event + */ +#define MCPWM_CMPR1_TEA_INT_ENA (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_ENA_M (MCPWM_CMPR1_TEA_INT_ENA_V << MCPWM_CMPR1_TEA_INT_ENA_S) +#define MCPWM_CMPR1_TEA_INT_ENA_V 0x00000001U +#define MCPWM_CMPR1_TEA_INT_ENA_S 16 +/** MCPWM_CMPR2_TEA_INT_ENA : R/W; bitpos: [17]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 2 TEA event + */ +#define MCPWM_CMPR2_TEA_INT_ENA (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_ENA_M (MCPWM_CMPR2_TEA_INT_ENA_V << MCPWM_CMPR2_TEA_INT_ENA_S) +#define MCPWM_CMPR2_TEA_INT_ENA_V 0x00000001U +#define MCPWM_CMPR2_TEA_INT_ENA_S 17 +/** MCPWM_CMPR0_TEB_INT_ENA : R/W; bitpos: [18]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 0 TEB event + */ +#define MCPWM_CMPR0_TEB_INT_ENA (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_ENA_M (MCPWM_CMPR0_TEB_INT_ENA_V << MCPWM_CMPR0_TEB_INT_ENA_S) +#define MCPWM_CMPR0_TEB_INT_ENA_V 0x00000001U +#define MCPWM_CMPR0_TEB_INT_ENA_S 18 +/** MCPWM_CMPR1_TEB_INT_ENA : R/W; bitpos: [19]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 1 TEB event + */ +#define MCPWM_CMPR1_TEB_INT_ENA (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_ENA_M (MCPWM_CMPR1_TEB_INT_ENA_V << MCPWM_CMPR1_TEB_INT_ENA_S) +#define MCPWM_CMPR1_TEB_INT_ENA_V 0x00000001U +#define MCPWM_CMPR1_TEB_INT_ENA_S 19 +/** MCPWM_CMPR2_TEB_INT_ENA : R/W; bitpos: [20]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 2 TEB event + */ +#define MCPWM_CMPR2_TEB_INT_ENA (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_ENA_M (MCPWM_CMPR2_TEB_INT_ENA_V << MCPWM_CMPR2_TEB_INT_ENA_S) +#define MCPWM_CMPR2_TEB_INT_ENA_V 0x00000001U +#define MCPWM_CMPR2_TEB_INT_ENA_S 20 +/** MCPWM_TZ0_CBC_INT_ENA : R/W; bitpos: [21]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + */ +#define MCPWM_TZ0_CBC_INT_ENA (BIT(21)) +#define MCPWM_TZ0_CBC_INT_ENA_M (MCPWM_TZ0_CBC_INT_ENA_V << MCPWM_TZ0_CBC_INT_ENA_S) +#define MCPWM_TZ0_CBC_INT_ENA_V 0x00000001U +#define MCPWM_TZ0_CBC_INT_ENA_S 21 +/** MCPWM_TZ1_CBC_INT_ENA : R/W; bitpos: [22]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + */ +#define MCPWM_TZ1_CBC_INT_ENA (BIT(22)) +#define MCPWM_TZ1_CBC_INT_ENA_M (MCPWM_TZ1_CBC_INT_ENA_V << MCPWM_TZ1_CBC_INT_ENA_S) +#define MCPWM_TZ1_CBC_INT_ENA_V 0x00000001U +#define MCPWM_TZ1_CBC_INT_ENA_S 22 +/** MCPWM_TZ2_CBC_INT_ENA : R/W; bitpos: [23]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + */ +#define MCPWM_TZ2_CBC_INT_ENA (BIT(23)) +#define MCPWM_TZ2_CBC_INT_ENA_M (MCPWM_TZ2_CBC_INT_ENA_V << MCPWM_TZ2_CBC_INT_ENA_S) +#define MCPWM_TZ2_CBC_INT_ENA_V 0x00000001U +#define MCPWM_TZ2_CBC_INT_ENA_S 23 +/** MCPWM_TZ0_OST_INT_ENA : R/W; bitpos: [24]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM0. + */ +#define MCPWM_TZ0_OST_INT_ENA (BIT(24)) +#define MCPWM_TZ0_OST_INT_ENA_M (MCPWM_TZ0_OST_INT_ENA_V << MCPWM_TZ0_OST_INT_ENA_S) +#define MCPWM_TZ0_OST_INT_ENA_V 0x00000001U +#define MCPWM_TZ0_OST_INT_ENA_S 24 +/** MCPWM_TZ1_OST_INT_ENA : R/W; bitpos: [25]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM1. + */ +#define MCPWM_TZ1_OST_INT_ENA (BIT(25)) +#define MCPWM_TZ1_OST_INT_ENA_M (MCPWM_TZ1_OST_INT_ENA_V << MCPWM_TZ1_OST_INT_ENA_S) +#define MCPWM_TZ1_OST_INT_ENA_V 0x00000001U +#define MCPWM_TZ1_OST_INT_ENA_S 25 +/** MCPWM_TZ2_OST_INT_ENA : R/W; bitpos: [26]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM2. + */ +#define MCPWM_TZ2_OST_INT_ENA (BIT(26)) +#define MCPWM_TZ2_OST_INT_ENA_M (MCPWM_TZ2_OST_INT_ENA_V << MCPWM_TZ2_OST_INT_ENA_S) +#define MCPWM_TZ2_OST_INT_ENA_V 0x00000001U +#define MCPWM_TZ2_OST_INT_ENA_S 26 +/** MCPWM_CAP0_INT_ENA : R/W; bitpos: [27]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 0. + */ +#define MCPWM_CAP0_INT_ENA (BIT(27)) +#define MCPWM_CAP0_INT_ENA_M (MCPWM_CAP0_INT_ENA_V << MCPWM_CAP0_INT_ENA_S) +#define MCPWM_CAP0_INT_ENA_V 0x00000001U +#define MCPWM_CAP0_INT_ENA_S 27 +/** MCPWM_CAP1_INT_ENA : R/W; bitpos: [28]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 1. + */ +#define MCPWM_CAP1_INT_ENA (BIT(28)) +#define MCPWM_CAP1_INT_ENA_M (MCPWM_CAP1_INT_ENA_V << MCPWM_CAP1_INT_ENA_S) +#define MCPWM_CAP1_INT_ENA_V 0x00000001U +#define MCPWM_CAP1_INT_ENA_S 28 +/** MCPWM_CAP2_INT_ENA : R/W; bitpos: [29]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 2. + */ +#define MCPWM_CAP2_INT_ENA (BIT(29)) +#define MCPWM_CAP2_INT_ENA_M (MCPWM_CAP2_INT_ENA_V << MCPWM_CAP2_INT_ENA_S) +#define MCPWM_CAP2_INT_ENA_V 0x00000001U +#define MCPWM_CAP2_INT_ENA_S 29 + +/** MCPWM_INT_RAW_REG register + * Raw interrupt status + */ +#define MCPWM_INT_RAW_REG(i) (REG_MCPWM_BASE(i) + 0x114) +/** MCPWM_TIMER0_STOP_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw status bit for the interrupt triggered when the timer 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_RAW (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_RAW_M (MCPWM_TIMER0_STOP_INT_RAW_V << MCPWM_TIMER0_STOP_INT_RAW_S) +#define MCPWM_TIMER0_STOP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER0_STOP_INT_RAW_S 0 +/** MCPWM_TIMER1_STOP_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw status bit for the interrupt triggered when the timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_RAW (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_RAW_M (MCPWM_TIMER1_STOP_INT_RAW_V << MCPWM_TIMER1_STOP_INT_RAW_S) +#define MCPWM_TIMER1_STOP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_RAW_S 1 +/** MCPWM_TIMER2_STOP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw status bit for the interrupt triggered when the timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_RAW (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_RAW_M (MCPWM_TIMER2_STOP_INT_RAW_V << MCPWM_TIMER2_STOP_INT_RAW_S) +#define MCPWM_TIMER2_STOP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_RAW_S 2 +/** MCPWM_TIMER0_TEZ_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_RAW (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_RAW_M (MCPWM_TIMER0_TEZ_INT_RAW_V << MCPWM_TIMER0_TEZ_INT_RAW_S) +#define MCPWM_TIMER0_TEZ_INT_RAW_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_RAW_S 3 +/** MCPWM_TIMER1_TEZ_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_RAW (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_RAW_M (MCPWM_TIMER1_TEZ_INT_RAW_V << MCPWM_TIMER1_TEZ_INT_RAW_S) +#define MCPWM_TIMER1_TEZ_INT_RAW_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_RAW_S 4 +/** MCPWM_TIMER2_TEZ_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_RAW (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_RAW_M (MCPWM_TIMER2_TEZ_INT_RAW_V << MCPWM_TIMER2_TEZ_INT_RAW_S) +#define MCPWM_TIMER2_TEZ_INT_RAW_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_RAW_S 5 +/** MCPWM_TIMER0_TEP_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_RAW (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_RAW_M (MCPWM_TIMER0_TEP_INT_RAW_V << MCPWM_TIMER0_TEP_INT_RAW_S) +#define MCPWM_TIMER0_TEP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_RAW_S 6 +/** MCPWM_TIMER1_TEP_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_RAW (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_RAW_M (MCPWM_TIMER1_TEP_INT_RAW_V << MCPWM_TIMER1_TEP_INT_RAW_S) +#define MCPWM_TIMER1_TEP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_RAW_S 7 +/** MCPWM_TIMER2_TEP_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_RAW (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_RAW_M (MCPWM_TIMER2_TEP_INT_RAW_V << MCPWM_TIMER2_TEP_INT_RAW_S) +#define MCPWM_TIMER2_TEP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_RAW_S 8 +/** MCPWM_FAULT0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw status bit for the interrupt triggered when event_f0 starts. + */ +#define MCPWM_FAULT0_INT_RAW (BIT(9)) +#define MCPWM_FAULT0_INT_RAW_M (MCPWM_FAULT0_INT_RAW_V << MCPWM_FAULT0_INT_RAW_S) +#define MCPWM_FAULT0_INT_RAW_V 0x00000001U +#define MCPWM_FAULT0_INT_RAW_S 9 +/** MCPWM_FAULT1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw status bit for the interrupt triggered when event_f1 starts. + */ +#define MCPWM_FAULT1_INT_RAW (BIT(10)) +#define MCPWM_FAULT1_INT_RAW_M (MCPWM_FAULT1_INT_RAW_V << MCPWM_FAULT1_INT_RAW_S) +#define MCPWM_FAULT1_INT_RAW_V 0x00000001U +#define MCPWM_FAULT1_INT_RAW_S 10 +/** MCPWM_FAULT2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw status bit for the interrupt triggered when event_f2 starts. + */ +#define MCPWM_FAULT2_INT_RAW (BIT(11)) +#define MCPWM_FAULT2_INT_RAW_M (MCPWM_FAULT2_INT_RAW_V << MCPWM_FAULT2_INT_RAW_S) +#define MCPWM_FAULT2_INT_RAW_V 0x00000001U +#define MCPWM_FAULT2_INT_RAW_S 11 +/** MCPWM_FAULT0_CLR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw status bit for the interrupt triggered when event_f0 ends. + */ +#define MCPWM_FAULT0_CLR_INT_RAW (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_RAW_M (MCPWM_FAULT0_CLR_INT_RAW_V << MCPWM_FAULT0_CLR_INT_RAW_S) +#define MCPWM_FAULT0_CLR_INT_RAW_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_RAW_S 12 +/** MCPWM_FAULT1_CLR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw status bit for the interrupt triggered when event_f1 ends. + */ +#define MCPWM_FAULT1_CLR_INT_RAW (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_RAW_M (MCPWM_FAULT1_CLR_INT_RAW_V << MCPWM_FAULT1_CLR_INT_RAW_S) +#define MCPWM_FAULT1_CLR_INT_RAW_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_RAW_S 13 +/** MCPWM_FAULT2_CLR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw status bit for the interrupt triggered when event_f2 ends. + */ +#define MCPWM_FAULT2_CLR_INT_RAW (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_RAW_M (MCPWM_FAULT2_CLR_INT_RAW_V << MCPWM_FAULT2_CLR_INT_RAW_S) +#define MCPWM_FAULT2_CLR_INT_RAW_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_RAW_S 14 +/** MCPWM_CMPR0_TEA_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 0 TEA event + */ +#define MCPWM_CMPR0_TEA_INT_RAW (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_RAW_M (MCPWM_CMPR0_TEA_INT_RAW_V << MCPWM_CMPR0_TEA_INT_RAW_S) +#define MCPWM_CMPR0_TEA_INT_RAW_V 0x00000001U +#define MCPWM_CMPR0_TEA_INT_RAW_S 15 +/** MCPWM_CMPR1_TEA_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 1 TEA event + */ +#define MCPWM_CMPR1_TEA_INT_RAW (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_RAW_M (MCPWM_CMPR1_TEA_INT_RAW_V << MCPWM_CMPR1_TEA_INT_RAW_S) +#define MCPWM_CMPR1_TEA_INT_RAW_V 0x00000001U +#define MCPWM_CMPR1_TEA_INT_RAW_S 16 +/** MCPWM_CMPR2_TEA_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 2 TEA event + */ +#define MCPWM_CMPR2_TEA_INT_RAW (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_RAW_M (MCPWM_CMPR2_TEA_INT_RAW_V << MCPWM_CMPR2_TEA_INT_RAW_S) +#define MCPWM_CMPR2_TEA_INT_RAW_V 0x00000001U +#define MCPWM_CMPR2_TEA_INT_RAW_S 17 +/** MCPWM_CMPR0_TEB_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 0 TEB event + */ +#define MCPWM_CMPR0_TEB_INT_RAW (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_RAW_M (MCPWM_CMPR0_TEB_INT_RAW_V << MCPWM_CMPR0_TEB_INT_RAW_S) +#define MCPWM_CMPR0_TEB_INT_RAW_V 0x00000001U +#define MCPWM_CMPR0_TEB_INT_RAW_S 18 +/** MCPWM_CMPR1_TEB_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 1 TEB event + */ +#define MCPWM_CMPR1_TEB_INT_RAW (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_RAW_M (MCPWM_CMPR1_TEB_INT_RAW_V << MCPWM_CMPR1_TEB_INT_RAW_S) +#define MCPWM_CMPR1_TEB_INT_RAW_V 0x00000001U +#define MCPWM_CMPR1_TEB_INT_RAW_S 19 +/** MCPWM_CMPR2_TEB_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 2 TEB event + */ +#define MCPWM_CMPR2_TEB_INT_RAW (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_RAW_M (MCPWM_CMPR2_TEB_INT_RAW_V << MCPWM_CMPR2_TEB_INT_RAW_S) +#define MCPWM_CMPR2_TEB_INT_RAW_V 0x00000001U +#define MCPWM_CMPR2_TEB_INT_RAW_S 20 +/** MCPWM_TZ0_CBC_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM0. + */ +#define MCPWM_TZ0_CBC_INT_RAW (BIT(21)) +#define MCPWM_TZ0_CBC_INT_RAW_M (MCPWM_TZ0_CBC_INT_RAW_V << MCPWM_TZ0_CBC_INT_RAW_S) +#define MCPWM_TZ0_CBC_INT_RAW_V 0x00000001U +#define MCPWM_TZ0_CBC_INT_RAW_S 21 +/** MCPWM_TZ1_CBC_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM1. + */ +#define MCPWM_TZ1_CBC_INT_RAW (BIT(22)) +#define MCPWM_TZ1_CBC_INT_RAW_M (MCPWM_TZ1_CBC_INT_RAW_V << MCPWM_TZ1_CBC_INT_RAW_S) +#define MCPWM_TZ1_CBC_INT_RAW_V 0x00000001U +#define MCPWM_TZ1_CBC_INT_RAW_S 22 +/** MCPWM_TZ2_CBC_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM2. + */ +#define MCPWM_TZ2_CBC_INT_RAW (BIT(23)) +#define MCPWM_TZ2_CBC_INT_RAW_M (MCPWM_TZ2_CBC_INT_RAW_V << MCPWM_TZ2_CBC_INT_RAW_S) +#define MCPWM_TZ2_CBC_INT_RAW_V 0x00000001U +#define MCPWM_TZ2_CBC_INT_RAW_S 23 +/** MCPWM_TZ0_OST_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM0. + */ +#define MCPWM_TZ0_OST_INT_RAW (BIT(24)) +#define MCPWM_TZ0_OST_INT_RAW_M (MCPWM_TZ0_OST_INT_RAW_V << MCPWM_TZ0_OST_INT_RAW_S) +#define MCPWM_TZ0_OST_INT_RAW_V 0x00000001U +#define MCPWM_TZ0_OST_INT_RAW_S 24 +/** MCPWM_TZ1_OST_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM1. + */ +#define MCPWM_TZ1_OST_INT_RAW (BIT(25)) +#define MCPWM_TZ1_OST_INT_RAW_M (MCPWM_TZ1_OST_INT_RAW_V << MCPWM_TZ1_OST_INT_RAW_S) +#define MCPWM_TZ1_OST_INT_RAW_V 0x00000001U +#define MCPWM_TZ1_OST_INT_RAW_S 25 +/** MCPWM_TZ2_OST_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM2. + */ +#define MCPWM_TZ2_OST_INT_RAW (BIT(26)) +#define MCPWM_TZ2_OST_INT_RAW_M (MCPWM_TZ2_OST_INT_RAW_V << MCPWM_TZ2_OST_INT_RAW_S) +#define MCPWM_TZ2_OST_INT_RAW_V 0x00000001U +#define MCPWM_TZ2_OST_INT_RAW_S 26 +/** MCPWM_CAP0_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 0. + */ +#define MCPWM_CAP0_INT_RAW (BIT(27)) +#define MCPWM_CAP0_INT_RAW_M (MCPWM_CAP0_INT_RAW_V << MCPWM_CAP0_INT_RAW_S) +#define MCPWM_CAP0_INT_RAW_V 0x00000001U +#define MCPWM_CAP0_INT_RAW_S 27 +/** MCPWM_CAP1_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 1. + */ +#define MCPWM_CAP1_INT_RAW (BIT(28)) +#define MCPWM_CAP1_INT_RAW_M (MCPWM_CAP1_INT_RAW_V << MCPWM_CAP1_INT_RAW_S) +#define MCPWM_CAP1_INT_RAW_V 0x00000001U +#define MCPWM_CAP1_INT_RAW_S 28 +/** MCPWM_CAP2_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 2. + */ +#define MCPWM_CAP2_INT_RAW (BIT(29)) +#define MCPWM_CAP2_INT_RAW_M (MCPWM_CAP2_INT_RAW_V << MCPWM_CAP2_INT_RAW_S) +#define MCPWM_CAP2_INT_RAW_V 0x00000001U +#define MCPWM_CAP2_INT_RAW_S 29 + +/** MCPWM_INT_ST_REG register + * Masked interrupt status + */ +#define MCPWM_INT_ST_REG(i) (REG_MCPWM_BASE(i) + 0x118) +/** MCPWM_TIMER0_STOP_INT_ST : RO; bitpos: [0]; default: 0; + * The masked status bit for the interrupt triggered when the timer 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_ST (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ST_M (MCPWM_TIMER0_STOP_INT_ST_V << MCPWM_TIMER0_STOP_INT_ST_S) +#define MCPWM_TIMER0_STOP_INT_ST_V 0x00000001U +#define MCPWM_TIMER0_STOP_INT_ST_S 0 +/** MCPWM_TIMER1_STOP_INT_ST : RO; bitpos: [1]; default: 0; + * The masked status bit for the interrupt triggered when the timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_ST (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ST_M (MCPWM_TIMER1_STOP_INT_ST_V << MCPWM_TIMER1_STOP_INT_ST_S) +#define MCPWM_TIMER1_STOP_INT_ST_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_ST_S 1 +/** MCPWM_TIMER2_STOP_INT_ST : RO; bitpos: [2]; default: 0; + * The masked status bit for the interrupt triggered when the timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_ST (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ST_M (MCPWM_TIMER2_STOP_INT_ST_V << MCPWM_TIMER2_STOP_INT_ST_S) +#define MCPWM_TIMER2_STOP_INT_ST_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_ST_S 2 +/** MCPWM_TIMER0_TEZ_INT_ST : RO; bitpos: [3]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_ST (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ST_M (MCPWM_TIMER0_TEZ_INT_ST_V << MCPWM_TIMER0_TEZ_INT_ST_S) +#define MCPWM_TIMER0_TEZ_INT_ST_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_ST_S 3 +/** MCPWM_TIMER1_TEZ_INT_ST : RO; bitpos: [4]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_ST (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ST_M (MCPWM_TIMER1_TEZ_INT_ST_V << MCPWM_TIMER1_TEZ_INT_ST_S) +#define MCPWM_TIMER1_TEZ_INT_ST_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_ST_S 4 +/** MCPWM_TIMER2_TEZ_INT_ST : RO; bitpos: [5]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_ST (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ST_M (MCPWM_TIMER2_TEZ_INT_ST_V << MCPWM_TIMER2_TEZ_INT_ST_S) +#define MCPWM_TIMER2_TEZ_INT_ST_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_ST_S 5 +/** MCPWM_TIMER0_TEP_INT_ST : RO; bitpos: [6]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_ST (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ST_M (MCPWM_TIMER0_TEP_INT_ST_V << MCPWM_TIMER0_TEP_INT_ST_S) +#define MCPWM_TIMER0_TEP_INT_ST_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_ST_S 6 +/** MCPWM_TIMER1_TEP_INT_ST : RO; bitpos: [7]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_ST (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ST_M (MCPWM_TIMER1_TEP_INT_ST_V << MCPWM_TIMER1_TEP_INT_ST_S) +#define MCPWM_TIMER1_TEP_INT_ST_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_ST_S 7 +/** MCPWM_TIMER2_TEP_INT_ST : RO; bitpos: [8]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_ST (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ST_M (MCPWM_TIMER2_TEP_INT_ST_V << MCPWM_TIMER2_TEP_INT_ST_S) +#define MCPWM_TIMER2_TEP_INT_ST_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_ST_S 8 +/** MCPWM_FAULT0_INT_ST : RO; bitpos: [9]; default: 0; + * The masked status bit for the interrupt triggered when event_f0 starts. + */ +#define MCPWM_FAULT0_INT_ST (BIT(9)) +#define MCPWM_FAULT0_INT_ST_M (MCPWM_FAULT0_INT_ST_V << MCPWM_FAULT0_INT_ST_S) +#define MCPWM_FAULT0_INT_ST_V 0x00000001U +#define MCPWM_FAULT0_INT_ST_S 9 +/** MCPWM_FAULT1_INT_ST : RO; bitpos: [10]; default: 0; + * The masked status bit for the interrupt triggered when event_f1 starts. + */ +#define MCPWM_FAULT1_INT_ST (BIT(10)) +#define MCPWM_FAULT1_INT_ST_M (MCPWM_FAULT1_INT_ST_V << MCPWM_FAULT1_INT_ST_S) +#define MCPWM_FAULT1_INT_ST_V 0x00000001U +#define MCPWM_FAULT1_INT_ST_S 10 +/** MCPWM_FAULT2_INT_ST : RO; bitpos: [11]; default: 0; + * The masked status bit for the interrupt triggered when event_f2 starts. + */ +#define MCPWM_FAULT2_INT_ST (BIT(11)) +#define MCPWM_FAULT2_INT_ST_M (MCPWM_FAULT2_INT_ST_V << MCPWM_FAULT2_INT_ST_S) +#define MCPWM_FAULT2_INT_ST_V 0x00000001U +#define MCPWM_FAULT2_INT_ST_S 11 +/** MCPWM_FAULT0_CLR_INT_ST : RO; bitpos: [12]; default: 0; + * The masked status bit for the interrupt triggered when event_f0 ends. + */ +#define MCPWM_FAULT0_CLR_INT_ST (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ST_M (MCPWM_FAULT0_CLR_INT_ST_V << MCPWM_FAULT0_CLR_INT_ST_S) +#define MCPWM_FAULT0_CLR_INT_ST_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_ST_S 12 +/** MCPWM_FAULT1_CLR_INT_ST : RO; bitpos: [13]; default: 0; + * The masked status bit for the interrupt triggered when event_f1 ends. + */ +#define MCPWM_FAULT1_CLR_INT_ST (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ST_M (MCPWM_FAULT1_CLR_INT_ST_V << MCPWM_FAULT1_CLR_INT_ST_S) +#define MCPWM_FAULT1_CLR_INT_ST_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_ST_S 13 +/** MCPWM_FAULT2_CLR_INT_ST : RO; bitpos: [14]; default: 0; + * The masked status bit for the interrupt triggered when event_f2 ends. + */ +#define MCPWM_FAULT2_CLR_INT_ST (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ST_M (MCPWM_FAULT2_CLR_INT_ST_V << MCPWM_FAULT2_CLR_INT_ST_S) +#define MCPWM_FAULT2_CLR_INT_ST_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_ST_S 14 +/** MCPWM_CMPR0_TEA_INT_ST : RO; bitpos: [15]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 0 TEA event + */ +#define MCPWM_CMPR0_TEA_INT_ST (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_ST_M (MCPWM_CMPR0_TEA_INT_ST_V << MCPWM_CMPR0_TEA_INT_ST_S) +#define MCPWM_CMPR0_TEA_INT_ST_V 0x00000001U +#define MCPWM_CMPR0_TEA_INT_ST_S 15 +/** MCPWM_CMPR1_TEA_INT_ST : RO; bitpos: [16]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 1 TEA event + */ +#define MCPWM_CMPR1_TEA_INT_ST (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_ST_M (MCPWM_CMPR1_TEA_INT_ST_V << MCPWM_CMPR1_TEA_INT_ST_S) +#define MCPWM_CMPR1_TEA_INT_ST_V 0x00000001U +#define MCPWM_CMPR1_TEA_INT_ST_S 16 +/** MCPWM_CMPR2_TEA_INT_ST : RO; bitpos: [17]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 2 TEA event + */ +#define MCPWM_CMPR2_TEA_INT_ST (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_ST_M (MCPWM_CMPR2_TEA_INT_ST_V << MCPWM_CMPR2_TEA_INT_ST_S) +#define MCPWM_CMPR2_TEA_INT_ST_V 0x00000001U +#define MCPWM_CMPR2_TEA_INT_ST_S 17 +/** MCPWM_CMPR0_TEB_INT_ST : RO; bitpos: [18]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 0 TEB event + */ +#define MCPWM_CMPR0_TEB_INT_ST (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_ST_M (MCPWM_CMPR0_TEB_INT_ST_V << MCPWM_CMPR0_TEB_INT_ST_S) +#define MCPWM_CMPR0_TEB_INT_ST_V 0x00000001U +#define MCPWM_CMPR0_TEB_INT_ST_S 18 +/** MCPWM_CMPR1_TEB_INT_ST : RO; bitpos: [19]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 1 TEB event + */ +#define MCPWM_CMPR1_TEB_INT_ST (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_ST_M (MCPWM_CMPR1_TEB_INT_ST_V << MCPWM_CMPR1_TEB_INT_ST_S) +#define MCPWM_CMPR1_TEB_INT_ST_V 0x00000001U +#define MCPWM_CMPR1_TEB_INT_ST_S 19 +/** MCPWM_CMPR2_TEB_INT_ST : RO; bitpos: [20]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 2 TEB event + */ +#define MCPWM_CMPR2_TEB_INT_ST (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_ST_M (MCPWM_CMPR2_TEB_INT_ST_V << MCPWM_CMPR2_TEB_INT_ST_S) +#define MCPWM_CMPR2_TEB_INT_ST_V 0x00000001U +#define MCPWM_CMPR2_TEB_INT_ST_S 20 +/** MCPWM_TZ0_CBC_INT_ST : RO; bitpos: [21]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM0. + */ +#define MCPWM_TZ0_CBC_INT_ST (BIT(21)) +#define MCPWM_TZ0_CBC_INT_ST_M (MCPWM_TZ0_CBC_INT_ST_V << MCPWM_TZ0_CBC_INT_ST_S) +#define MCPWM_TZ0_CBC_INT_ST_V 0x00000001U +#define MCPWM_TZ0_CBC_INT_ST_S 21 +/** MCPWM_TZ1_CBC_INT_ST : RO; bitpos: [22]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM1. + */ +#define MCPWM_TZ1_CBC_INT_ST (BIT(22)) +#define MCPWM_TZ1_CBC_INT_ST_M (MCPWM_TZ1_CBC_INT_ST_V << MCPWM_TZ1_CBC_INT_ST_S) +#define MCPWM_TZ1_CBC_INT_ST_V 0x00000001U +#define MCPWM_TZ1_CBC_INT_ST_S 22 +/** MCPWM_TZ2_CBC_INT_ST : RO; bitpos: [23]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM2. + */ +#define MCPWM_TZ2_CBC_INT_ST (BIT(23)) +#define MCPWM_TZ2_CBC_INT_ST_M (MCPWM_TZ2_CBC_INT_ST_V << MCPWM_TZ2_CBC_INT_ST_S) +#define MCPWM_TZ2_CBC_INT_ST_V 0x00000001U +#define MCPWM_TZ2_CBC_INT_ST_S 23 +/** MCPWM_TZ0_OST_INT_ST : RO; bitpos: [24]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM0. + */ +#define MCPWM_TZ0_OST_INT_ST (BIT(24)) +#define MCPWM_TZ0_OST_INT_ST_M (MCPWM_TZ0_OST_INT_ST_V << MCPWM_TZ0_OST_INT_ST_S) +#define MCPWM_TZ0_OST_INT_ST_V 0x00000001U +#define MCPWM_TZ0_OST_INT_ST_S 24 +/** MCPWM_TZ1_OST_INT_ST : RO; bitpos: [25]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM1. + */ +#define MCPWM_TZ1_OST_INT_ST (BIT(25)) +#define MCPWM_TZ1_OST_INT_ST_M (MCPWM_TZ1_OST_INT_ST_V << MCPWM_TZ1_OST_INT_ST_S) +#define MCPWM_TZ1_OST_INT_ST_V 0x00000001U +#define MCPWM_TZ1_OST_INT_ST_S 25 +/** MCPWM_TZ2_OST_INT_ST : RO; bitpos: [26]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM2. + */ +#define MCPWM_TZ2_OST_INT_ST (BIT(26)) +#define MCPWM_TZ2_OST_INT_ST_M (MCPWM_TZ2_OST_INT_ST_V << MCPWM_TZ2_OST_INT_ST_S) +#define MCPWM_TZ2_OST_INT_ST_V 0x00000001U +#define MCPWM_TZ2_OST_INT_ST_S 26 +/** MCPWM_CAP0_INT_ST : RO; bitpos: [27]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 0. + */ +#define MCPWM_CAP0_INT_ST (BIT(27)) +#define MCPWM_CAP0_INT_ST_M (MCPWM_CAP0_INT_ST_V << MCPWM_CAP0_INT_ST_S) +#define MCPWM_CAP0_INT_ST_V 0x00000001U +#define MCPWM_CAP0_INT_ST_S 27 +/** MCPWM_CAP1_INT_ST : RO; bitpos: [28]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 1. + */ +#define MCPWM_CAP1_INT_ST (BIT(28)) +#define MCPWM_CAP1_INT_ST_M (MCPWM_CAP1_INT_ST_V << MCPWM_CAP1_INT_ST_S) +#define MCPWM_CAP1_INT_ST_V 0x00000001U +#define MCPWM_CAP1_INT_ST_S 28 +/** MCPWM_CAP2_INT_ST : RO; bitpos: [29]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 2. + */ +#define MCPWM_CAP2_INT_ST (BIT(29)) +#define MCPWM_CAP2_INT_ST_M (MCPWM_CAP2_INT_ST_V << MCPWM_CAP2_INT_ST_S) +#define MCPWM_CAP2_INT_ST_V 0x00000001U +#define MCPWM_CAP2_INT_ST_S 29 + +/** MCPWM_INT_CLR_REG register + * Interrupt clear bits + */ +#define MCPWM_INT_CLR_REG(i) (REG_MCPWM_BASE(i) + 0x11c) +/** MCPWM_TIMER0_STOP_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_CLR (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_CLR_M (MCPWM_TIMER0_STOP_INT_CLR_V << MCPWM_TIMER0_STOP_INT_CLR_S) +#define MCPWM_TIMER0_STOP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER0_STOP_INT_CLR_S 0 +/** MCPWM_TIMER1_STOP_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_CLR (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_CLR_M (MCPWM_TIMER1_STOP_INT_CLR_V << MCPWM_TIMER1_STOP_INT_CLR_S) +#define MCPWM_TIMER1_STOP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_CLR_S 1 +/** MCPWM_TIMER2_STOP_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_CLR (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_CLR_M (MCPWM_TIMER2_STOP_INT_CLR_V << MCPWM_TIMER2_STOP_INT_CLR_S) +#define MCPWM_TIMER2_STOP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_CLR_S 2 +/** MCPWM_TIMER0_TEZ_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_CLR (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_CLR_M (MCPWM_TIMER0_TEZ_INT_CLR_V << MCPWM_TIMER0_TEZ_INT_CLR_S) +#define MCPWM_TIMER0_TEZ_INT_CLR_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_CLR_S 3 +/** MCPWM_TIMER1_TEZ_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_CLR (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_CLR_M (MCPWM_TIMER1_TEZ_INT_CLR_V << MCPWM_TIMER1_TEZ_INT_CLR_S) +#define MCPWM_TIMER1_TEZ_INT_CLR_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_CLR_S 4 +/** MCPWM_TIMER2_TEZ_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_CLR (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_CLR_M (MCPWM_TIMER2_TEZ_INT_CLR_V << MCPWM_TIMER2_TEZ_INT_CLR_S) +#define MCPWM_TIMER2_TEZ_INT_CLR_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_CLR_S 5 +/** MCPWM_TIMER0_TEP_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_CLR (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_CLR_M (MCPWM_TIMER0_TEP_INT_CLR_V << MCPWM_TIMER0_TEP_INT_CLR_S) +#define MCPWM_TIMER0_TEP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_CLR_S 6 +/** MCPWM_TIMER1_TEP_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_CLR (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_CLR_M (MCPWM_TIMER1_TEP_INT_CLR_V << MCPWM_TIMER1_TEP_INT_CLR_S) +#define MCPWM_TIMER1_TEP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_CLR_S 7 +/** MCPWM_TIMER2_TEP_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_CLR (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_CLR_M (MCPWM_TIMER2_TEP_INT_CLR_V << MCPWM_TIMER2_TEP_INT_CLR_S) +#define MCPWM_TIMER2_TEP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_CLR_S 8 +/** MCPWM_FAULT0_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the interrupt triggered when event_f0 starts. + */ +#define MCPWM_FAULT0_INT_CLR (BIT(9)) +#define MCPWM_FAULT0_INT_CLR_M (MCPWM_FAULT0_INT_CLR_V << MCPWM_FAULT0_INT_CLR_S) +#define MCPWM_FAULT0_INT_CLR_V 0x00000001U +#define MCPWM_FAULT0_INT_CLR_S 9 +/** MCPWM_FAULT1_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the interrupt triggered when event_f1 starts. + */ +#define MCPWM_FAULT1_INT_CLR (BIT(10)) +#define MCPWM_FAULT1_INT_CLR_M (MCPWM_FAULT1_INT_CLR_V << MCPWM_FAULT1_INT_CLR_S) +#define MCPWM_FAULT1_INT_CLR_V 0x00000001U +#define MCPWM_FAULT1_INT_CLR_S 10 +/** MCPWM_FAULT2_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the interrupt triggered when event_f2 starts. + */ +#define MCPWM_FAULT2_INT_CLR (BIT(11)) +#define MCPWM_FAULT2_INT_CLR_M (MCPWM_FAULT2_INT_CLR_V << MCPWM_FAULT2_INT_CLR_S) +#define MCPWM_FAULT2_INT_CLR_V 0x00000001U +#define MCPWM_FAULT2_INT_CLR_S 11 +/** MCPWM_FAULT0_CLR_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the interrupt triggered when event_f0 ends. + */ +#define MCPWM_FAULT0_CLR_INT_CLR (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_CLR_M (MCPWM_FAULT0_CLR_INT_CLR_V << MCPWM_FAULT0_CLR_INT_CLR_S) +#define MCPWM_FAULT0_CLR_INT_CLR_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_CLR_S 12 +/** MCPWM_FAULT1_CLR_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the interrupt triggered when event_f1 ends. + */ +#define MCPWM_FAULT1_CLR_INT_CLR (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_CLR_M (MCPWM_FAULT1_CLR_INT_CLR_V << MCPWM_FAULT1_CLR_INT_CLR_S) +#define MCPWM_FAULT1_CLR_INT_CLR_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_CLR_S 13 +/** MCPWM_FAULT2_CLR_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the interrupt triggered when event_f2 ends. + */ +#define MCPWM_FAULT2_CLR_INT_CLR (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_CLR_M (MCPWM_FAULT2_CLR_INT_CLR_V << MCPWM_FAULT2_CLR_INT_CLR_S) +#define MCPWM_FAULT2_CLR_INT_CLR_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_CLR_S 14 +/** MCPWM_CMPR0_TEA_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event + */ +#define MCPWM_CMPR0_TEA_INT_CLR (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_CLR_M (MCPWM_CMPR0_TEA_INT_CLR_V << MCPWM_CMPR0_TEA_INT_CLR_S) +#define MCPWM_CMPR0_TEA_INT_CLR_V 0x00000001U +#define MCPWM_CMPR0_TEA_INT_CLR_S 15 +/** MCPWM_CMPR1_TEA_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event + */ +#define MCPWM_CMPR1_TEA_INT_CLR (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_CLR_M (MCPWM_CMPR1_TEA_INT_CLR_V << MCPWM_CMPR1_TEA_INT_CLR_S) +#define MCPWM_CMPR1_TEA_INT_CLR_V 0x00000001U +#define MCPWM_CMPR1_TEA_INT_CLR_S 16 +/** MCPWM_CMPR2_TEA_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event + */ +#define MCPWM_CMPR2_TEA_INT_CLR (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_CLR_M (MCPWM_CMPR2_TEA_INT_CLR_V << MCPWM_CMPR2_TEA_INT_CLR_S) +#define MCPWM_CMPR2_TEA_INT_CLR_V 0x00000001U +#define MCPWM_CMPR2_TEA_INT_CLR_S 17 +/** MCPWM_CMPR0_TEB_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event + */ +#define MCPWM_CMPR0_TEB_INT_CLR (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_CLR_M (MCPWM_CMPR0_TEB_INT_CLR_V << MCPWM_CMPR0_TEB_INT_CLR_S) +#define MCPWM_CMPR0_TEB_INT_CLR_V 0x00000001U +#define MCPWM_CMPR0_TEB_INT_CLR_S 18 +/** MCPWM_CMPR1_TEB_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event + */ +#define MCPWM_CMPR1_TEB_INT_CLR (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_CLR_M (MCPWM_CMPR1_TEB_INT_CLR_V << MCPWM_CMPR1_TEB_INT_CLR_S) +#define MCPWM_CMPR1_TEB_INT_CLR_V 0x00000001U +#define MCPWM_CMPR1_TEB_INT_CLR_S 19 +/** MCPWM_CMPR2_TEB_INT_CLR : WT; bitpos: [20]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event + */ +#define MCPWM_CMPR2_TEB_INT_CLR (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_CLR_M (MCPWM_CMPR2_TEB_INT_CLR_V << MCPWM_CMPR2_TEB_INT_CLR_S) +#define MCPWM_CMPR2_TEB_INT_CLR_V 0x00000001U +#define MCPWM_CMPR2_TEB_INT_CLR_S 20 +/** MCPWM_TZ0_CBC_INT_CLR : WT; bitpos: [21]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM0. + */ +#define MCPWM_TZ0_CBC_INT_CLR (BIT(21)) +#define MCPWM_TZ0_CBC_INT_CLR_M (MCPWM_TZ0_CBC_INT_CLR_V << MCPWM_TZ0_CBC_INT_CLR_S) +#define MCPWM_TZ0_CBC_INT_CLR_V 0x00000001U +#define MCPWM_TZ0_CBC_INT_CLR_S 21 +/** MCPWM_TZ1_CBC_INT_CLR : WT; bitpos: [22]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM1. + */ +#define MCPWM_TZ1_CBC_INT_CLR (BIT(22)) +#define MCPWM_TZ1_CBC_INT_CLR_M (MCPWM_TZ1_CBC_INT_CLR_V << MCPWM_TZ1_CBC_INT_CLR_S) +#define MCPWM_TZ1_CBC_INT_CLR_V 0x00000001U +#define MCPWM_TZ1_CBC_INT_CLR_S 22 +/** MCPWM_TZ2_CBC_INT_CLR : WT; bitpos: [23]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM2. + */ +#define MCPWM_TZ2_CBC_INT_CLR (BIT(23)) +#define MCPWM_TZ2_CBC_INT_CLR_M (MCPWM_TZ2_CBC_INT_CLR_V << MCPWM_TZ2_CBC_INT_CLR_S) +#define MCPWM_TZ2_CBC_INT_CLR_V 0x00000001U +#define MCPWM_TZ2_CBC_INT_CLR_S 23 +/** MCPWM_TZ0_OST_INT_CLR : WT; bitpos: [24]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0. + */ +#define MCPWM_TZ0_OST_INT_CLR (BIT(24)) +#define MCPWM_TZ0_OST_INT_CLR_M (MCPWM_TZ0_OST_INT_CLR_V << MCPWM_TZ0_OST_INT_CLR_S) +#define MCPWM_TZ0_OST_INT_CLR_V 0x00000001U +#define MCPWM_TZ0_OST_INT_CLR_S 24 +/** MCPWM_TZ1_OST_INT_CLR : WT; bitpos: [25]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1. + */ +#define MCPWM_TZ1_OST_INT_CLR (BIT(25)) +#define MCPWM_TZ1_OST_INT_CLR_M (MCPWM_TZ1_OST_INT_CLR_V << MCPWM_TZ1_OST_INT_CLR_S) +#define MCPWM_TZ1_OST_INT_CLR_V 0x00000001U +#define MCPWM_TZ1_OST_INT_CLR_S 25 +/** MCPWM_TZ2_OST_INT_CLR : WT; bitpos: [26]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2. + */ +#define MCPWM_TZ2_OST_INT_CLR (BIT(26)) +#define MCPWM_TZ2_OST_INT_CLR_M (MCPWM_TZ2_OST_INT_CLR_V << MCPWM_TZ2_OST_INT_CLR_S) +#define MCPWM_TZ2_OST_INT_CLR_V 0x00000001U +#define MCPWM_TZ2_OST_INT_CLR_S 26 +/** MCPWM_CAP0_INT_CLR : WT; bitpos: [27]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 0. + */ +#define MCPWM_CAP0_INT_CLR (BIT(27)) +#define MCPWM_CAP0_INT_CLR_M (MCPWM_CAP0_INT_CLR_V << MCPWM_CAP0_INT_CLR_S) +#define MCPWM_CAP0_INT_CLR_V 0x00000001U +#define MCPWM_CAP0_INT_CLR_S 27 +/** MCPWM_CAP1_INT_CLR : WT; bitpos: [28]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 1. + */ +#define MCPWM_CAP1_INT_CLR (BIT(28)) +#define MCPWM_CAP1_INT_CLR_M (MCPWM_CAP1_INT_CLR_V << MCPWM_CAP1_INT_CLR_S) +#define MCPWM_CAP1_INT_CLR_V 0x00000001U +#define MCPWM_CAP1_INT_CLR_S 28 +/** MCPWM_CAP2_INT_CLR : WT; bitpos: [29]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 2. + */ +#define MCPWM_CAP2_INT_CLR (BIT(29)) +#define MCPWM_CAP2_INT_CLR_M (MCPWM_CAP2_INT_CLR_V << MCPWM_CAP2_INT_CLR_S) +#define MCPWM_CAP2_INT_CLR_V 0x00000001U +#define MCPWM_CAP2_INT_CLR_S 29 + +/** MCPWM_EVT_EN_REG register + * MCPWM event enable register + */ +#define MCPWM_EVT_EN_REG(i) (REG_MCPWM_BASE(i) + 0x120) +/** MCPWM_EVT_TIMER0_STOP_EN : R/W; bitpos: [0]; default: 0; + * set this bit high to enable timer0 stop event generate + */ +#define MCPWM_EVT_TIMER0_STOP_EN (BIT(0)) +#define MCPWM_EVT_TIMER0_STOP_EN_M (MCPWM_EVT_TIMER0_STOP_EN_V << MCPWM_EVT_TIMER0_STOP_EN_S) +#define MCPWM_EVT_TIMER0_STOP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER0_STOP_EN_S 0 +/** MCPWM_EVT_TIMER1_STOP_EN : R/W; bitpos: [1]; default: 0; + * set this bit high to enable timer1 stop event generate + */ +#define MCPWM_EVT_TIMER1_STOP_EN (BIT(1)) +#define MCPWM_EVT_TIMER1_STOP_EN_M (MCPWM_EVT_TIMER1_STOP_EN_V << MCPWM_EVT_TIMER1_STOP_EN_S) +#define MCPWM_EVT_TIMER1_STOP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER1_STOP_EN_S 1 +/** MCPWM_EVT_TIMER2_STOP_EN : R/W; bitpos: [2]; default: 0; + * set this bit high to enable timer2 stop event generate + */ +#define MCPWM_EVT_TIMER2_STOP_EN (BIT(2)) +#define MCPWM_EVT_TIMER2_STOP_EN_M (MCPWM_EVT_TIMER2_STOP_EN_V << MCPWM_EVT_TIMER2_STOP_EN_S) +#define MCPWM_EVT_TIMER2_STOP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER2_STOP_EN_S 2 +/** MCPWM_EVT_TIMER0_TEZ_EN : R/W; bitpos: [3]; default: 0; + * set this bit high to enable timer0 equal zero event generate + */ +#define MCPWM_EVT_TIMER0_TEZ_EN (BIT(3)) +#define MCPWM_EVT_TIMER0_TEZ_EN_M (MCPWM_EVT_TIMER0_TEZ_EN_V << MCPWM_EVT_TIMER0_TEZ_EN_S) +#define MCPWM_EVT_TIMER0_TEZ_EN_V 0x00000001U +#define MCPWM_EVT_TIMER0_TEZ_EN_S 3 +/** MCPWM_EVT_TIMER1_TEZ_EN : R/W; bitpos: [4]; default: 0; + * set this bit high to enable timer1 equal zero event generate + */ +#define MCPWM_EVT_TIMER1_TEZ_EN (BIT(4)) +#define MCPWM_EVT_TIMER1_TEZ_EN_M (MCPWM_EVT_TIMER1_TEZ_EN_V << MCPWM_EVT_TIMER1_TEZ_EN_S) +#define MCPWM_EVT_TIMER1_TEZ_EN_V 0x00000001U +#define MCPWM_EVT_TIMER1_TEZ_EN_S 4 +/** MCPWM_EVT_TIMER2_TEZ_EN : R/W; bitpos: [5]; default: 0; + * set this bit high to enable timer2 equal zero event generate + */ +#define MCPWM_EVT_TIMER2_TEZ_EN (BIT(5)) +#define MCPWM_EVT_TIMER2_TEZ_EN_M (MCPWM_EVT_TIMER2_TEZ_EN_V << MCPWM_EVT_TIMER2_TEZ_EN_S) +#define MCPWM_EVT_TIMER2_TEZ_EN_V 0x00000001U +#define MCPWM_EVT_TIMER2_TEZ_EN_S 5 +/** MCPWM_EVT_TIMER0_TEP_EN : R/W; bitpos: [6]; default: 0; + * set this bit high to enable timer0 equal period event generate + */ +#define MCPWM_EVT_TIMER0_TEP_EN (BIT(6)) +#define MCPWM_EVT_TIMER0_TEP_EN_M (MCPWM_EVT_TIMER0_TEP_EN_V << MCPWM_EVT_TIMER0_TEP_EN_S) +#define MCPWM_EVT_TIMER0_TEP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER0_TEP_EN_S 6 +/** MCPWM_EVT_TIMER1_TEP_EN : R/W; bitpos: [7]; default: 0; + * set this bit high to enable timer1 equal period event generate + */ +#define MCPWM_EVT_TIMER1_TEP_EN (BIT(7)) +#define MCPWM_EVT_TIMER1_TEP_EN_M (MCPWM_EVT_TIMER1_TEP_EN_V << MCPWM_EVT_TIMER1_TEP_EN_S) +#define MCPWM_EVT_TIMER1_TEP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER1_TEP_EN_S 7 +/** MCPWM_EVT_TIMER2_TEP_EN : R/W; bitpos: [8]; default: 0; + * set this bit high to enable timer2 equal period event generate + */ +#define MCPWM_EVT_TIMER2_TEP_EN (BIT(8)) +#define MCPWM_EVT_TIMER2_TEP_EN_M (MCPWM_EVT_TIMER2_TEP_EN_V << MCPWM_EVT_TIMER2_TEP_EN_S) +#define MCPWM_EVT_TIMER2_TEP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER2_TEP_EN_S 8 +/** MCPWM_EVT_OP0_TEA_EN : R/W; bitpos: [9]; default: 0; + * set this bit high to enable PWM generator0 timer equal a event generate + */ +#define MCPWM_EVT_OP0_TEA_EN (BIT(9)) +#define MCPWM_EVT_OP0_TEA_EN_M (MCPWM_EVT_OP0_TEA_EN_V << MCPWM_EVT_OP0_TEA_EN_S) +#define MCPWM_EVT_OP0_TEA_EN_V 0x00000001U +#define MCPWM_EVT_OP0_TEA_EN_S 9 +/** MCPWM_EVT_OP1_TEA_EN : R/W; bitpos: [10]; default: 0; + * set this bit high to enable PWM generator1 timer equal a event generate + */ +#define MCPWM_EVT_OP1_TEA_EN (BIT(10)) +#define MCPWM_EVT_OP1_TEA_EN_M (MCPWM_EVT_OP1_TEA_EN_V << MCPWM_EVT_OP1_TEA_EN_S) +#define MCPWM_EVT_OP1_TEA_EN_V 0x00000001U +#define MCPWM_EVT_OP1_TEA_EN_S 10 +/** MCPWM_EVT_OP2_TEA_EN : R/W; bitpos: [11]; default: 0; + * set this bit high to enable PWM generator2 timer equal a event generate + */ +#define MCPWM_EVT_OP2_TEA_EN (BIT(11)) +#define MCPWM_EVT_OP2_TEA_EN_M (MCPWM_EVT_OP2_TEA_EN_V << MCPWM_EVT_OP2_TEA_EN_S) +#define MCPWM_EVT_OP2_TEA_EN_V 0x00000001U +#define MCPWM_EVT_OP2_TEA_EN_S 11 +/** MCPWM_EVT_OP0_TEB_EN : R/W; bitpos: [12]; default: 0; + * set this bit high to enable PWM generator0 timer equal b event generate + */ +#define MCPWM_EVT_OP0_TEB_EN (BIT(12)) +#define MCPWM_EVT_OP0_TEB_EN_M (MCPWM_EVT_OP0_TEB_EN_V << MCPWM_EVT_OP0_TEB_EN_S) +#define MCPWM_EVT_OP0_TEB_EN_V 0x00000001U +#define MCPWM_EVT_OP0_TEB_EN_S 12 +/** MCPWM_EVT_OP1_TEB_EN : R/W; bitpos: [13]; default: 0; + * set this bit high to enable PWM generator1 timer equal b event generate + */ +#define MCPWM_EVT_OP1_TEB_EN (BIT(13)) +#define MCPWM_EVT_OP1_TEB_EN_M (MCPWM_EVT_OP1_TEB_EN_V << MCPWM_EVT_OP1_TEB_EN_S) +#define MCPWM_EVT_OP1_TEB_EN_V 0x00000001U +#define MCPWM_EVT_OP1_TEB_EN_S 13 +/** MCPWM_EVT_OP2_TEB_EN : R/W; bitpos: [14]; default: 0; + * set this bit high to enable PWM generator2 timer equal b event generate + */ +#define MCPWM_EVT_OP2_TEB_EN (BIT(14)) +#define MCPWM_EVT_OP2_TEB_EN_M (MCPWM_EVT_OP2_TEB_EN_V << MCPWM_EVT_OP2_TEB_EN_S) +#define MCPWM_EVT_OP2_TEB_EN_V 0x00000001U +#define MCPWM_EVT_OP2_TEB_EN_S 14 +/** MCPWM_EVT_F0_EN : R/W; bitpos: [15]; default: 0; + * set this bit high to enable fault0 event generate + */ +#define MCPWM_EVT_F0_EN (BIT(15)) +#define MCPWM_EVT_F0_EN_M (MCPWM_EVT_F0_EN_V << MCPWM_EVT_F0_EN_S) +#define MCPWM_EVT_F0_EN_V 0x00000001U +#define MCPWM_EVT_F0_EN_S 15 +/** MCPWM_EVT_F1_EN : R/W; bitpos: [16]; default: 0; + * set this bit high to enable fault1 event generate + */ +#define MCPWM_EVT_F1_EN (BIT(16)) +#define MCPWM_EVT_F1_EN_M (MCPWM_EVT_F1_EN_V << MCPWM_EVT_F1_EN_S) +#define MCPWM_EVT_F1_EN_V 0x00000001U +#define MCPWM_EVT_F1_EN_S 16 +/** MCPWM_EVT_F2_EN : R/W; bitpos: [17]; default: 0; + * set this bit high to enable fault2 event generate + */ +#define MCPWM_EVT_F2_EN (BIT(17)) +#define MCPWM_EVT_F2_EN_M (MCPWM_EVT_F2_EN_V << MCPWM_EVT_F2_EN_S) +#define MCPWM_EVT_F2_EN_V 0x00000001U +#define MCPWM_EVT_F2_EN_S 17 +/** MCPWM_EVT_F0_CLR_EN : R/W; bitpos: [18]; default: 0; + * set this bit high to enable fault0 clear event generate + */ +#define MCPWM_EVT_F0_CLR_EN (BIT(18)) +#define MCPWM_EVT_F0_CLR_EN_M (MCPWM_EVT_F0_CLR_EN_V << MCPWM_EVT_F0_CLR_EN_S) +#define MCPWM_EVT_F0_CLR_EN_V 0x00000001U +#define MCPWM_EVT_F0_CLR_EN_S 18 +/** MCPWM_EVT_F1_CLR_EN : R/W; bitpos: [19]; default: 0; + * set this bit high to enable fault1 clear event generate + */ +#define MCPWM_EVT_F1_CLR_EN (BIT(19)) +#define MCPWM_EVT_F1_CLR_EN_M (MCPWM_EVT_F1_CLR_EN_V << MCPWM_EVT_F1_CLR_EN_S) +#define MCPWM_EVT_F1_CLR_EN_V 0x00000001U +#define MCPWM_EVT_F1_CLR_EN_S 19 +/** MCPWM_EVT_F2_CLR_EN : R/W; bitpos: [20]; default: 0; + * set this bit high to enable fault2 clear event generate + */ +#define MCPWM_EVT_F2_CLR_EN (BIT(20)) +#define MCPWM_EVT_F2_CLR_EN_M (MCPWM_EVT_F2_CLR_EN_V << MCPWM_EVT_F2_CLR_EN_S) +#define MCPWM_EVT_F2_CLR_EN_V 0x00000001U +#define MCPWM_EVT_F2_CLR_EN_S 20 +/** MCPWM_EVT_TZ0_CBC_EN : R/W; bitpos: [21]; default: 0; + * set this bit high to enable cycle by cycle trip0 event generate + */ +#define MCPWM_EVT_TZ0_CBC_EN (BIT(21)) +#define MCPWM_EVT_TZ0_CBC_EN_M (MCPWM_EVT_TZ0_CBC_EN_V << MCPWM_EVT_TZ0_CBC_EN_S) +#define MCPWM_EVT_TZ0_CBC_EN_V 0x00000001U +#define MCPWM_EVT_TZ0_CBC_EN_S 21 +/** MCPWM_EVT_TZ1_CBC_EN : R/W; bitpos: [22]; default: 0; + * set this bit high to enable cycle by cycle trip1 event generate + */ +#define MCPWM_EVT_TZ1_CBC_EN (BIT(22)) +#define MCPWM_EVT_TZ1_CBC_EN_M (MCPWM_EVT_TZ1_CBC_EN_V << MCPWM_EVT_TZ1_CBC_EN_S) +#define MCPWM_EVT_TZ1_CBC_EN_V 0x00000001U +#define MCPWM_EVT_TZ1_CBC_EN_S 22 +/** MCPWM_EVT_TZ2_CBC_EN : R/W; bitpos: [23]; default: 0; + * set this bit high to enable cycle by cycle trip2 event generate + */ +#define MCPWM_EVT_TZ2_CBC_EN (BIT(23)) +#define MCPWM_EVT_TZ2_CBC_EN_M (MCPWM_EVT_TZ2_CBC_EN_V << MCPWM_EVT_TZ2_CBC_EN_S) +#define MCPWM_EVT_TZ2_CBC_EN_V 0x00000001U +#define MCPWM_EVT_TZ2_CBC_EN_S 23 +/** MCPWM_EVT_TZ0_OST_EN : R/W; bitpos: [24]; default: 0; + * set this bit high to enable one shot trip0 event generate + */ +#define MCPWM_EVT_TZ0_OST_EN (BIT(24)) +#define MCPWM_EVT_TZ0_OST_EN_M (MCPWM_EVT_TZ0_OST_EN_V << MCPWM_EVT_TZ0_OST_EN_S) +#define MCPWM_EVT_TZ0_OST_EN_V 0x00000001U +#define MCPWM_EVT_TZ0_OST_EN_S 24 +/** MCPWM_EVT_TZ1_OST_EN : R/W; bitpos: [25]; default: 0; + * set this bit high to enable one shot trip1 event generate + */ +#define MCPWM_EVT_TZ1_OST_EN (BIT(25)) +#define MCPWM_EVT_TZ1_OST_EN_M (MCPWM_EVT_TZ1_OST_EN_V << MCPWM_EVT_TZ1_OST_EN_S) +#define MCPWM_EVT_TZ1_OST_EN_V 0x00000001U +#define MCPWM_EVT_TZ1_OST_EN_S 25 +/** MCPWM_EVT_TZ2_OST_EN : R/W; bitpos: [26]; default: 0; + * set this bit high to enable one shot trip2 event generate + */ +#define MCPWM_EVT_TZ2_OST_EN (BIT(26)) +#define MCPWM_EVT_TZ2_OST_EN_M (MCPWM_EVT_TZ2_OST_EN_V << MCPWM_EVT_TZ2_OST_EN_S) +#define MCPWM_EVT_TZ2_OST_EN_V 0x00000001U +#define MCPWM_EVT_TZ2_OST_EN_S 26 +/** MCPWM_EVT_CAP0_EN : R/W; bitpos: [27]; default: 0; + * set this bit high to enable capture0 event generate + */ +#define MCPWM_EVT_CAP0_EN (BIT(27)) +#define MCPWM_EVT_CAP0_EN_M (MCPWM_EVT_CAP0_EN_V << MCPWM_EVT_CAP0_EN_S) +#define MCPWM_EVT_CAP0_EN_V 0x00000001U +#define MCPWM_EVT_CAP0_EN_S 27 +/** MCPWM_EVT_CAP1_EN : R/W; bitpos: [28]; default: 0; + * set this bit high to enable capture1 event generate + */ +#define MCPWM_EVT_CAP1_EN (BIT(28)) +#define MCPWM_EVT_CAP1_EN_M (MCPWM_EVT_CAP1_EN_V << MCPWM_EVT_CAP1_EN_S) +#define MCPWM_EVT_CAP1_EN_V 0x00000001U +#define MCPWM_EVT_CAP1_EN_S 28 +/** MCPWM_EVT_CAP2_EN : R/W; bitpos: [29]; default: 0; + * set this bit high to enable capture2 event generate + */ +#define MCPWM_EVT_CAP2_EN (BIT(29)) +#define MCPWM_EVT_CAP2_EN_M (MCPWM_EVT_CAP2_EN_V << MCPWM_EVT_CAP2_EN_S) +#define MCPWM_EVT_CAP2_EN_V 0x00000001U +#define MCPWM_EVT_CAP2_EN_S 29 + +/** MCPWM_TASK_EN_REG register + * MCPWM task enable register + */ +#define MCPWM_TASK_EN_REG(i) (REG_MCPWM_BASE(i) + 0x124) +/** MCPWM_TASK_CMPR0_A_UP_EN : R/W; bitpos: [0]; default: 0; + * set this bit high to enable PWM generator0 timer stamp A's shadow register update + * task receive + */ +#define MCPWM_TASK_CMPR0_A_UP_EN (BIT(0)) +#define MCPWM_TASK_CMPR0_A_UP_EN_M (MCPWM_TASK_CMPR0_A_UP_EN_V << MCPWM_TASK_CMPR0_A_UP_EN_S) +#define MCPWM_TASK_CMPR0_A_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR0_A_UP_EN_S 0 +/** MCPWM_TASK_CMPR1_A_UP_EN : R/W; bitpos: [1]; default: 0; + * set this bit high to enable PWM generator1 timer stamp A's shadow register update + * task receive + */ +#define MCPWM_TASK_CMPR1_A_UP_EN (BIT(1)) +#define MCPWM_TASK_CMPR1_A_UP_EN_M (MCPWM_TASK_CMPR1_A_UP_EN_V << MCPWM_TASK_CMPR1_A_UP_EN_S) +#define MCPWM_TASK_CMPR1_A_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR1_A_UP_EN_S 1 +/** MCPWM_TASK_CMPR2_A_UP_EN : R/W; bitpos: [2]; default: 0; + * set this bit high to enable PWM generator2 timer stamp A's shadow register update + * task receive + */ +#define MCPWM_TASK_CMPR2_A_UP_EN (BIT(2)) +#define MCPWM_TASK_CMPR2_A_UP_EN_M (MCPWM_TASK_CMPR2_A_UP_EN_V << MCPWM_TASK_CMPR2_A_UP_EN_S) +#define MCPWM_TASK_CMPR2_A_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR2_A_UP_EN_S 2 +/** MCPWM_TASK_CMPR0_B_UP_EN : R/W; bitpos: [3]; default: 0; + * set this bit high to enable PWM generator0 timer stamp B's shadow register update + * task receive + */ +#define MCPWM_TASK_CMPR0_B_UP_EN (BIT(3)) +#define MCPWM_TASK_CMPR0_B_UP_EN_M (MCPWM_TASK_CMPR0_B_UP_EN_V << MCPWM_TASK_CMPR0_B_UP_EN_S) +#define MCPWM_TASK_CMPR0_B_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR0_B_UP_EN_S 3 +/** MCPWM_TASK_CMPR1_B_UP_EN : R/W; bitpos: [4]; default: 0; + * set this bit high to enable PWM generator1 timer stamp B's shadow register update + * task receive + */ +#define MCPWM_TASK_CMPR1_B_UP_EN (BIT(4)) +#define MCPWM_TASK_CMPR1_B_UP_EN_M (MCPWM_TASK_CMPR1_B_UP_EN_V << MCPWM_TASK_CMPR1_B_UP_EN_S) +#define MCPWM_TASK_CMPR1_B_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR1_B_UP_EN_S 4 +/** MCPWM_TASK_CMPR2_B_UP_EN : R/W; bitpos: [5]; default: 0; + * set this bit high to enable PWM generator2 timer stamp B's shadow register update + * task receive + */ +#define MCPWM_TASK_CMPR2_B_UP_EN (BIT(5)) +#define MCPWM_TASK_CMPR2_B_UP_EN_M (MCPWM_TASK_CMPR2_B_UP_EN_V << MCPWM_TASK_CMPR2_B_UP_EN_S) +#define MCPWM_TASK_CMPR2_B_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR2_B_UP_EN_S 5 +/** MCPWM_TASK_GEN_STOP_EN : R/W; bitpos: [6]; default: 0; + * set this bit high to enable all PWM generate stop task receive + */ +#define MCPWM_TASK_GEN_STOP_EN (BIT(6)) +#define MCPWM_TASK_GEN_STOP_EN_M (MCPWM_TASK_GEN_STOP_EN_V << MCPWM_TASK_GEN_STOP_EN_S) +#define MCPWM_TASK_GEN_STOP_EN_V 0x00000001U +#define MCPWM_TASK_GEN_STOP_EN_S 6 +/** MCPWM_TASK_TIMER0_SYNC_EN : R/W; bitpos: [7]; default: 0; + * set this bit high to enable timer0 sync task receive + */ +#define MCPWM_TASK_TIMER0_SYNC_EN (BIT(7)) +#define MCPWM_TASK_TIMER0_SYNC_EN_M (MCPWM_TASK_TIMER0_SYNC_EN_V << MCPWM_TASK_TIMER0_SYNC_EN_S) +#define MCPWM_TASK_TIMER0_SYNC_EN_V 0x00000001U +#define MCPWM_TASK_TIMER0_SYNC_EN_S 7 +/** MCPWM_TASK_TIMER1_SYNC_EN : R/W; bitpos: [8]; default: 0; + * set this bit high to enable timer1 sync task receive + */ +#define MCPWM_TASK_TIMER1_SYNC_EN (BIT(8)) +#define MCPWM_TASK_TIMER1_SYNC_EN_M (MCPWM_TASK_TIMER1_SYNC_EN_V << MCPWM_TASK_TIMER1_SYNC_EN_S) +#define MCPWM_TASK_TIMER1_SYNC_EN_V 0x00000001U +#define MCPWM_TASK_TIMER1_SYNC_EN_S 8 +/** MCPWM_TASK_TIMER2_SYNC_EN : R/W; bitpos: [9]; default: 0; + * set this bit high to enable timer2 sync task receive + */ +#define MCPWM_TASK_TIMER2_SYNC_EN (BIT(9)) +#define MCPWM_TASK_TIMER2_SYNC_EN_M (MCPWM_TASK_TIMER2_SYNC_EN_V << MCPWM_TASK_TIMER2_SYNC_EN_S) +#define MCPWM_TASK_TIMER2_SYNC_EN_V 0x00000001U +#define MCPWM_TASK_TIMER2_SYNC_EN_S 9 +/** MCPWM_TASK_TIMER0_PERIOD_UP_EN : R/W; bitpos: [10]; default: 0; + * set this bit high to enable timer0 period update task receive + */ +#define MCPWM_TASK_TIMER0_PERIOD_UP_EN (BIT(10)) +#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_M (MCPWM_TASK_TIMER0_PERIOD_UP_EN_V << MCPWM_TASK_TIMER0_PERIOD_UP_EN_S) +#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_V 0x00000001U +#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_S 10 +/** MCPWM_TASK_TIMER1_PERIOD_UP_EN : R/W; bitpos: [11]; default: 0; + * set this bit high to enable timer1 period update task receive + */ +#define MCPWM_TASK_TIMER1_PERIOD_UP_EN (BIT(11)) +#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_M (MCPWM_TASK_TIMER1_PERIOD_UP_EN_V << MCPWM_TASK_TIMER1_PERIOD_UP_EN_S) +#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_V 0x00000001U +#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_S 11 +/** MCPWM_TASK_TIMER2_PERIOD_UP_EN : R/W; bitpos: [12]; default: 0; + * set this bit high to enable timer2 period update task receive + */ +#define MCPWM_TASK_TIMER2_PERIOD_UP_EN (BIT(12)) +#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_M (MCPWM_TASK_TIMER2_PERIOD_UP_EN_V << MCPWM_TASK_TIMER2_PERIOD_UP_EN_S) +#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_V 0x00000001U +#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_S 12 +/** MCPWM_TASK_TZ0_OST_EN : R/W; bitpos: [13]; default: 0; + * set this bit high to enable one shot trip0 task receive + */ +#define MCPWM_TASK_TZ0_OST_EN (BIT(13)) +#define MCPWM_TASK_TZ0_OST_EN_M (MCPWM_TASK_TZ0_OST_EN_V << MCPWM_TASK_TZ0_OST_EN_S) +#define MCPWM_TASK_TZ0_OST_EN_V 0x00000001U +#define MCPWM_TASK_TZ0_OST_EN_S 13 +/** MCPWM_TASK_TZ1_OST_EN : R/W; bitpos: [14]; default: 0; + * set this bit high to enable one shot trip1 task receive + */ +#define MCPWM_TASK_TZ1_OST_EN (BIT(14)) +#define MCPWM_TASK_TZ1_OST_EN_M (MCPWM_TASK_TZ1_OST_EN_V << MCPWM_TASK_TZ1_OST_EN_S) +#define MCPWM_TASK_TZ1_OST_EN_V 0x00000001U +#define MCPWM_TASK_TZ1_OST_EN_S 14 +/** MCPWM_TASK_TZ2_OST_EN : R/W; bitpos: [15]; default: 0; + * set this bit high to enable one shot trip2 task receive + */ +#define MCPWM_TASK_TZ2_OST_EN (BIT(15)) +#define MCPWM_TASK_TZ2_OST_EN_M (MCPWM_TASK_TZ2_OST_EN_V << MCPWM_TASK_TZ2_OST_EN_S) +#define MCPWM_TASK_TZ2_OST_EN_V 0x00000001U +#define MCPWM_TASK_TZ2_OST_EN_S 15 +/** MCPWM_TASK_CLR0_OST_EN : R/W; bitpos: [16]; default: 0; + * set this bit high to enable one shot trip0 clear task receive + */ +#define MCPWM_TASK_CLR0_OST_EN (BIT(16)) +#define MCPWM_TASK_CLR0_OST_EN_M (MCPWM_TASK_CLR0_OST_EN_V << MCPWM_TASK_CLR0_OST_EN_S) +#define MCPWM_TASK_CLR0_OST_EN_V 0x00000001U +#define MCPWM_TASK_CLR0_OST_EN_S 16 +/** MCPWM_TASK_CLR1_OST_EN : R/W; bitpos: [17]; default: 0; + * set this bit high to enable one shot trip1 clear task receive + */ +#define MCPWM_TASK_CLR1_OST_EN (BIT(17)) +#define MCPWM_TASK_CLR1_OST_EN_M (MCPWM_TASK_CLR1_OST_EN_V << MCPWM_TASK_CLR1_OST_EN_S) +#define MCPWM_TASK_CLR1_OST_EN_V 0x00000001U +#define MCPWM_TASK_CLR1_OST_EN_S 17 +/** MCPWM_TASK_CLR2_OST_EN : R/W; bitpos: [18]; default: 0; + * set this bit high to enable one shot trip2 clear task receive + */ +#define MCPWM_TASK_CLR2_OST_EN (BIT(18)) +#define MCPWM_TASK_CLR2_OST_EN_M (MCPWM_TASK_CLR2_OST_EN_V << MCPWM_TASK_CLR2_OST_EN_S) +#define MCPWM_TASK_CLR2_OST_EN_V 0x00000001U +#define MCPWM_TASK_CLR2_OST_EN_S 18 +/** MCPWM_TASK_CAP0_EN : R/W; bitpos: [19]; default: 0; + * set this bit high to enable capture0 task receive + */ +#define MCPWM_TASK_CAP0_EN (BIT(19)) +#define MCPWM_TASK_CAP0_EN_M (MCPWM_TASK_CAP0_EN_V << MCPWM_TASK_CAP0_EN_S) +#define MCPWM_TASK_CAP0_EN_V 0x00000001U +#define MCPWM_TASK_CAP0_EN_S 19 +/** MCPWM_TASK_CAP1_EN : R/W; bitpos: [20]; default: 0; + * set this bit high to enable capture1 task receive + */ +#define MCPWM_TASK_CAP1_EN (BIT(20)) +#define MCPWM_TASK_CAP1_EN_M (MCPWM_TASK_CAP1_EN_V << MCPWM_TASK_CAP1_EN_S) +#define MCPWM_TASK_CAP1_EN_V 0x00000001U +#define MCPWM_TASK_CAP1_EN_S 20 +/** MCPWM_TASK_CAP2_EN : R/W; bitpos: [21]; default: 0; + * set this bit high to enable capture2 task receive + */ +#define MCPWM_TASK_CAP2_EN (BIT(21)) +#define MCPWM_TASK_CAP2_EN_M (MCPWM_TASK_CAP2_EN_V << MCPWM_TASK_CAP2_EN_S) +#define MCPWM_TASK_CAP2_EN_V 0x00000001U +#define MCPWM_TASK_CAP2_EN_S 21 + +/** MCPWM_CLK_REG register + * MCPWM APB configuration register + */ +#define MCPWM_CLK_REG(i) (REG_MCPWM_BASE(i) + 0x128) +/** MCPWM_CLK_EN : R/W; bitpos: [0]; default: 0; + * Force clock on for this register file + */ +#define MCPWM_CLK_EN (BIT(0)) +#define MCPWM_CLK_EN_M (MCPWM_CLK_EN_V << MCPWM_CLK_EN_S) +#define MCPWM_CLK_EN_V 0x00000001U +#define MCPWM_CLK_EN_S 0 + +/** MCPWM_VERSION_REG register + * Version register. + */ +#define MCPWM_VERSION_REG(i) (REG_MCPWM_BASE(i) + 0x12c) +/** MCPWM_DATE : R/W; bitpos: [27:0]; default: 35656256; + * Version of this register file + */ +#define MCPWM_DATE 0x0FFFFFFFU +#define MCPWM_DATE_M (MCPWM_DATE_V << MCPWM_DATE_S) +#define MCPWM_DATE_V 0x0FFFFFFFU +#define MCPWM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/mcpwm_struct.h b/components/soc/esp32c6/include/soc/mcpwm_struct.h new file mode 100644 index 0000000000..2d98b4e26e --- /dev/null +++ b/components/soc/esp32c6/include/soc/mcpwm_struct.h @@ -0,0 +1,1694 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Prescaler configuration */ +/** Type of clk_cfg register + * PWM clock prescaler register. + */ +typedef union { + struct { + /** clk_prescale : R/W; bitpos: [7:0]; default: 0; + * Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1) + */ + uint32_t clk_prescale:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} mcpwm_clk_cfg_reg_t; + + +/** Group: MCPWM Timer Configuration and status */ +/** Type of timer_cfg0 register + * PWM timer period and update method configuration register. + */ +typedef union { + struct { + /** timer_prescale : R/W; bitpos: [7:0]; default: 0; + * period of PT0_clk = Period of PWM_clk * (PWM_TIMER_PRESCALE + 1) + */ + uint32_t timer_prescale:8; + /** timer_period : R/W; bitpos: [23:8]; default: 255; + * period shadow register of PWM timer + */ + uint32_t timer_period:16; + /** timer_period_upmethod : R/W; bitpos: [25:24]; default: 0; + * Update method for active register of PWM timer period, 0: immediate, 1: TEZ, 2: + * sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + */ + uint32_t timer_period_upmethod:2; + uint32_t reserved_26:6; + }; + uint32_t val; +} mcpwm_timer_cfg0_reg_t; + +/** Type of timer_cfg1 register + * PWM timer0 working mode and start/stop control configuration register. + */ +typedef union { + struct { + /** timer_start : R/W/SC; bitpos: [2:0]; default: 0; + * PWM timer start and stop control. 0: if PWM timer starts, then stops at TEZ, 1: + * if timer0 starts, then stops at TEP, 2: PWM timer starts and runs on, 3: timer + * starts and stops at the next TEZ, 4: timer starts and stops at the next TEP. TEP + * here and below means the event that happens when the timer equals to period + */ + uint32_t timer_start:3; + /** timer_mod : R/W; bitpos: [4:3]; default: 0; + * PWM timer working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down + * mode + */ + uint32_t timer_mod:2; + uint32_t reserved_5:27; + }; + uint32_t val; +} mcpwm_timer_cfg1_reg_t; + +/** Type of timer_sync register + * PWM timer sync function configuration register. + */ +typedef union { + struct { + /** timer_synci_en : R/W; bitpos: [0]; default: 0; + * When set, timer reloading with phase on sync input event is enabled. + */ + uint32_t timer_synci_en:1; + /** timer_sync_sw : R/W; bitpos: [1]; default: 0; + * Toggling this bit will trigger a software sync. + */ + uint32_t timer_sync_sw:1; + /** timer_synco_sel : R/W; bitpos: [3:2]; default: 0; + * PWM timer sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always + * generate when toggling the reg_timer0_sync_sw bit + */ + uint32_t timer_synco_sel:2; + /** timer_phase : R/W; bitpos: [19:4]; default: 0; + * phase for timer reload on sync event + */ + uint32_t timer_phase:16; + /** timer_phase_direction : R/W; bitpos: [20]; default: 0; + * Configure the PWM timer0's direction when timer mode is up-down mode: + * 0-increase,1-decrease + */ + uint32_t timer_phase_direction:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} mcpwm_timer_sync_reg_t; + +/** Type of timer_status register + * PWM timer status register. + */ +typedef union { + struct { + /** timer_value : RO; bitpos: [15:0]; default: 0; + * current PWM timer counter value + */ + uint32_t timer_value:16; + /** timer_direction : RO; bitpos: [16]; default: 0; + * current PWM timer counter direction, 0: increment 1: decrement + */ + uint32_t timer_direction:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} mcpwm_timer_status_reg_t; + + +/** Group: Common configuration for MCPWM timers */ +/** Type of timer_synci_cfg register + * Synchronization input selection for three PWM timers. + */ +typedef union { + struct { + /** timer0_syncisel : R/W; bitpos: [2:0]; default: 0; + * select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ + uint32_t timer0_syncisel:3; + /** timer1_syncisel : R/W; bitpos: [5:3]; default: 0; + * select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ + uint32_t timer1_syncisel:3; + /** timer2_syncisel : R/W; bitpos: [8:6]; default: 0; + * select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, + * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: + * SYNC2 from GPIO matrix, other values: no sync input selected + */ + uint32_t timer2_syncisel:3; + /** external_synci0_invert : R/W; bitpos: [9]; default: 0; + * invert SYNC0 from GPIO matrix + */ + uint32_t external_synci0_invert:1; + /** external_synci1_invert : R/W; bitpos: [10]; default: 0; + * invert SYNC1 from GPIO matrix + */ + uint32_t external_synci1_invert:1; + /** external_synci2_invert : R/W; bitpos: [11]; default: 0; + * invert SYNC2 from GPIO matrix + */ + uint32_t external_synci2_invert:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} mcpwm_timer_synci_cfg_reg_t; + +/** Type of operator_timersel register + * Select specific timer for PWM operators. + */ +typedef union { + struct { + /** operator0_timersel : R/W; bitpos: [1:0]; default: 0; + * Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: + * timer1, 2: timer2 + */ + uint32_t operator0_timersel:2; + /** operator1_timersel : R/W; bitpos: [3:2]; default: 0; + * Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: + * timer1, 2: timer2 + */ + uint32_t operator1_timersel:2; + /** operator2_timersel : R/W; bitpos: [5:4]; default: 0; + * Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: + * timer1, 2: timer2 + */ + uint32_t operator2_timersel:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} mcpwm_operator_timersel_reg_t; + + +/** Group: MCPWM Operator Configuration and Status */ +/** Type of gen_stmp_cfg register + * Transfer status and update method for time stamp registers A and B + */ +typedef union { + struct { + /** cmpr_a_upmethod : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator time stamp A's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ + uint32_t cmpr_a_upmethod:4; + /** cmpr_b_upmethod : R/W; bitpos: [7:4]; default: 0; + * Update method for PWM generator time stamp B's active register. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when + * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + */ + uint32_t cmpr_b_upmethod:4; + /** cmpr_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, PWM generator time stamp A's shadow reg is + * filled and waiting to be transferred to A's active reg. If cleared, A's active reg + * has been updated with shadow register latest value + */ + uint32_t cmpr_a_shdw_full:1; + /** cmpr_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0; + * Set and reset by hardware. If set, PWM generator time stamp B's shadow reg is + * filled and waiting to be transferred to B's active reg. If cleared, B's active reg + * has been updated with shadow register latest value + */ + uint32_t cmpr_b_shdw_full:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} mcpwm_gen_stmp_cfg_reg_t; + +/** Type of gen_tstmp register + * Shadow register for register B. + */ +typedef union { + struct { + /** cmpr : R/W; bitpos: [15:0]; default: 0; + * PWM generator time stamp's shadow register + */ + uint32_t cmpr:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_gen_tstmp_reg_t; + +/** Type of gen_cfg0 register + * Fault event T0 and T1 handling + */ +typedef union { + struct { + /** gen_cfg_upmethod : R/W; bitpos: [3:0]; default: 0; + * Update method for PWM generator's active register of configuration. When all bits + * are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to + * 1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update + */ + uint32_t gen_cfg_upmethod:4; + /** gen_t0_sel : R/W; bitpos: [6:4]; default: 0; + * Source selection for PWM generator event_t0, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ + uint32_t gen_t0_sel:3; + /** gen_t1_sel : R/W; bitpos: [9:7]; default: 0; + * Source selection for PWM generator event_t1, take effect immediately, 0: + * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + */ + uint32_t gen_t1_sel:3; + uint32_t reserved_10:22; + }; + uint32_t val; +} mcpwm_gen_cfg0_reg_t; + +/** Type of gen_force register + * Permissives to force PWM0A and PWM0B outputs by software + */ +typedef union { + struct { + /** gen_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32; + * Updating method for continuous software force of PWM generator. When all bits are + * set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when + * bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, + * when bit5 is set to 1: disable update. (TEA/B here and below means an event + * generated when the timer's value equals to that of register A/B.) + */ + uint32_t gen_cntuforce_upmethod:6; + /** gen_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0; + * Continuous software force mode for PWMnA. 0: disabled, 1: low, 2: high, 3: disabled + */ + uint32_t gen_a_cntuforce_mode:2; + /** gen_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0; + * Continuous software force mode for PWMnB. 0: disabled, 1: low, 2: high, 3: disabled + */ + uint32_t gen_b_cntuforce_mode:2; + /** gen_a_nciforce : R/W; bitpos: [10]; default: 0; + * Trigger of non-continuous immediate software-force event for PWMnA, a toggle will + * trigger a force event. + */ + uint32_t gen_a_nciforce:1; + /** gen_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0; + * non-continuous immediate software force mode for PWMnA, 0: disabled, 1: low, 2: + * high, 3: disabled + */ + uint32_t gen_a_nciforce_mode:2; + /** gen_b_nciforce : R/W; bitpos: [13]; default: 0; + * Trigger of non-continuous immediate software-force event for PWMnB, a toggle will + * trigger a force event. + */ + uint32_t gen_b_nciforce:1; + /** gen_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0; + * non-continuous immediate software force mode for PWMnB, 0: disabled, 1: low, 2: + * high, 3: disabled + */ + uint32_t gen_b_nciforce_mode:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_gen_force_reg_t; + +/** Type of gen register + * Actions triggered by events on PWM0B + */ +typedef union { + struct { + /** gen_utez : R/W; bitpos: [1:0]; default: 0; + * Action on PWMnA/B triggered by event TEZ when timer increasing + */ + uint32_t gen_utez:2; + /** gen_utep : R/W; bitpos: [3:2]; default: 0; + * Action on PWMnA/B triggered by event TEP when timer increasing + */ + uint32_t gen_utep:2; + /** gen_utea : R/W; bitpos: [5:4]; default: 0; + * Action on PWMnA/B triggered by event TEA when timer increasing + */ + uint32_t gen_utea:2; + /** gen_uteb : R/W; bitpos: [7:6]; default: 0; + * Action on PWMnA/B triggered by event TEB when timer increasing + */ + uint32_t gen_uteb:2; + /** gen_ut0 : R/W; bitpos: [9:8]; default: 0; + * Action on PWMnA/B triggered by event_t0 when timer increasing + */ + uint32_t gen_ut0:2; + /** gen_ut1 : R/W; bitpos: [11:10]; default: 0; + * Action on PWMnA/B triggered by event_t1 when timer increasing + */ + uint32_t gen_ut1:2; + /** gen_dtez : R/W; bitpos: [13:12]; default: 0; + * Action on PWMnA/B triggered by event TEZ when timer decreasing + */ + uint32_t gen_dtez:2; + /** gen_dtep : R/W; bitpos: [15:14]; default: 0; + * Action on PWMnA/B triggered by event TEP when timer decreasing + */ + uint32_t gen_dtep:2; + /** gen_dtea : R/W; bitpos: [17:16]; default: 0; + * Action on PWMnA/B triggered by event TEA when timer decreasing + */ + uint32_t gen_dtea:2; + /** gen_dteb : R/W; bitpos: [19:18]; default: 0; + * Action on PWMnA/B triggered by event TEB when timer decreasing + */ + uint32_t gen_dteb:2; + /** gen_dt0 : R/W; bitpos: [21:20]; default: 0; + * Action on PWMnA/B triggered by event_t0 when timer decreasing + */ + uint32_t gen_dt0:2; + /** gen_dt1 : R/W; bitpos: [23:22]; default: 0; + * Action on PWMnA/B triggered by event_t1 when timer decreasing. 0: no change, 1: low, + * 2: high, 3: toggle + */ + uint32_t gen_dt1:2; + uint32_t reserved_24:8; + }; + uint32_t val; +} mcpwm_gen_reg_t; + +/** Type of dt_cfg register + * dead time type selection and configuration + */ +typedef union { + struct { + /** db_fed_upmethod : R/W; bitpos: [3:0]; default: 0; + * Update method for FED (rising edge delay) active register. 0: immediate, when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ + uint32_t db_fed_upmethod:4; + /** db_red_upmethod : R/W; bitpos: [7:4]; default: 0; + * Update method for RED (rising edge delay) active register. 0: immediate, when bit0 + * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when + * bit3 is set to 1: disable the update + */ + uint32_t db_red_upmethod:4; + /** db_deb_mode : R/W; bitpos: [8]; default: 0; + * S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, + * 1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ + uint32_t db_deb_mode:1; + /** db_a_outswap : R/W; bitpos: [9]; default: 0; + * S6 in table + */ + uint32_t db_a_outswap:1; + /** db_b_outswap : R/W; bitpos: [10]; default: 0; + * S7 in table + */ + uint32_t db_b_outswap:1; + /** db_red_insel : R/W; bitpos: [11]; default: 0; + * S4 in table + */ + uint32_t db_red_insel:1; + /** db_fed_insel : R/W; bitpos: [12]; default: 0; + * S5 in table + */ + uint32_t db_fed_insel:1; + /** db_red_outinvert : R/W; bitpos: [13]; default: 0; + * S2 in table + */ + uint32_t db_red_outinvert:1; + /** db_fed_outinvert : R/W; bitpos: [14]; default: 0; + * S3 in table + */ + uint32_t db_fed_outinvert:1; + /** db_a_outbypass : R/W; bitpos: [15]; default: 1; + * S1 in table + */ + uint32_t db_a_outbypass:1; + /** db_b_outbypass : R/W; bitpos: [16]; default: 1; + * S0 in table + */ + uint32_t db_b_outbypass:1; + /** db_clk_sel : R/W; bitpos: [17]; default: 0; + * Dead time generator n clock selection. 0: PWM_clk, 1: PT_clk + */ + uint32_t db_clk_sel:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} mcpwm_dt_cfg_reg_t; + +/** Type of dt_fed_cfg register + * Shadow register for falling edge delay (FED). + */ +typedef union { + struct { + /** db_fed : R/W; bitpos: [15:0]; default: 0; + * Shadow register for FED + */ + uint32_t db_fed:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_dt_fed_cfg_reg_t; + +/** Type of dt_red_cfg register + * Shadow register for rising edge delay (RED). + */ +typedef union { + struct { + /** db_red : R/W; bitpos: [15:0]; default: 0; + * Shadow register for RED + */ + uint32_t db_red:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_dt_red_cfg_reg_t; + +/** Type of carrier_cfg register + * Carrier enable and configuratoin + */ +typedef union { + struct { + /** chopper_en : R/W; bitpos: [0]; default: 0; + * When set, carrier0 function is enabled. When cleared, carrier0 is bypassed + */ + uint32_t chopper_en:1; + /** chopper_prescale : R/W; bitpos: [4:1]; default: 0; + * PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * + * (PWM_CARRIER0_PRESCALE + 1) + */ + uint32_t chopper_prescale:4; + /** chopper_duty : R/W; bitpos: [7:5]; default: 0; + * carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + */ + uint32_t chopper_duty:3; + /** chopper_oshtwth : R/W; bitpos: [11:8]; default: 0; + * width of the first pulse in number of periods of the carrier + */ + uint32_t chopper_oshtwth:4; + /** chopper_out_invert : R/W; bitpos: [12]; default: 0; + * when set, invert the output of PWM0A and PWM0B for this submodule + */ + uint32_t chopper_out_invert:1; + /** chopper_in_invert : R/W; bitpos: [13]; default: 0; + * when set, invert the input of PWM0A and PWM0B for this submodule + */ + uint32_t chopper_in_invert:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} mcpwm_carrier_cfg_reg_t; + +/** Type of fh_cfg0 register + * Actions on PWM0A and PWM0B trip events + */ +typedef union { + struct { + /** tz_sw_cbc : R/W; bitpos: [0]; default: 0; + * Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + */ + uint32_t tz_sw_cbc:1; + /** tz_f2_cbc : R/W; bitpos: [1]; default: 0; + * event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ + uint32_t tz_f2_cbc:1; + /** tz_f1_cbc : R/W; bitpos: [2]; default: 0; + * event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ + uint32_t tz_f1_cbc:1; + /** tz_f0_cbc : R/W; bitpos: [3]; default: 0; + * event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + */ + uint32_t tz_f0_cbc:1; + /** tz_sw_ost : R/W; bitpos: [4]; default: 0; + * Enable register for software force one-shot mode action. 0: disable, 1: enable + */ + uint32_t tz_sw_ost:1; + /** tz_f2_ost : R/W; bitpos: [5]; default: 0; + * event_f2 will trigger one-shot mode action. 0: disable, 1: enable + */ + uint32_t tz_f2_ost:1; + /** tz_f1_ost : R/W; bitpos: [6]; default: 0; + * event_f1 will trigger one-shot mode action. 0: disable, 1: enable + */ + uint32_t tz_f1_ost:1; + /** tz_f0_ost : R/W; bitpos: [7]; default: 0; + * event_f0 will trigger one-shot mode action. 0: disable, 1: enable + */ + uint32_t tz_f0_ost:1; + /** tz_a_cbc_d : R/W; bitpos: [9:8]; default: 0; + * Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t tz_a_cbc_d:2; + /** tz_a_cbc_u : R/W; bitpos: [11:10]; default: 0; + * Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is + * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t tz_a_cbc_u:2; + /** tz_a_ost_d : R/W; bitpos: [13:12]; default: 0; + * One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t tz_a_ost_d:2; + /** tz_a_ost_u : R/W; bitpos: [15:14]; default: 0; + * One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t tz_a_ost_u:2; + /** tz_b_cbc_d : R/W; bitpos: [17:16]; default: 0; + * Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is + * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t tz_b_cbc_d:2; + /** tz_b_cbc_u : R/W; bitpos: [19:18]; default: 0; + * Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is + * increasing. 0: do nothing,1: force low, 2: force high, 3: toggle + */ + uint32_t tz_b_cbc_u:2; + /** tz_b_ost_d : R/W; bitpos: [21:20]; default: 0; + * One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t tz_b_ost_d:2; + /** tz_b_ost_u : R/W; bitpos: [23:22]; default: 0; + * One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: + * do nothing, 1: force low, 2: force high, 3: toggle + */ + uint32_t tz_b_ost_u:2; + uint32_t reserved_24:8; + }; + uint32_t val; +} mcpwm_fh_cfg0_reg_t; + +/** Type of fh_cfg1 register + * Software triggers for fault handler actions + */ +typedef union { + struct { + /** tz_clr_ost : R/W; bitpos: [0]; default: 0; + * a rising edge will clear on going one-shot mode action + */ + uint32_t tz_clr_ost:1; + /** tz_cbcpulse : R/W; bitpos: [2:1]; default: 0; + * cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, + * when bit1 is set to 1:TEP + */ + uint32_t tz_cbcpulse:2; + /** tz_force_cbc : R/W; bitpos: [3]; default: 0; + * a toggle trigger a cycle-by-cycle mode action + */ + uint32_t tz_force_cbc:1; + /** tz_force_ost : R/W; bitpos: [4]; default: 0; + * a toggle (software negate its value) triggers a one-shot mode action + */ + uint32_t tz_force_ost:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} mcpwm_fh_cfg1_reg_t; + +/** Type of fh_status register + * Status of fault events. + */ +typedef union { + struct { + /** tz_cbc_on : RO; bitpos: [0]; default: 0; + * Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + */ + uint32_t tz_cbc_on:1; + /** tz_ost_on : RO; bitpos: [1]; default: 0; + * Set and reset by hardware. If set, an one-shot mode action is on going + */ + uint32_t tz_ost_on:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} mcpwm_fh_status_reg_t; + + +/** Group: Fault Detection Configuration and Status */ +/** Type of fault_detect register + * Fault detection configuration and status + */ +typedef union { + struct { + /** f0_en : R/W; bitpos: [0]; default: 0; + * When set, event_f0 generation is enabled + */ + uint32_t f0_en:1; + /** f1_en : R/W; bitpos: [1]; default: 0; + * When set, event_f1 generation is enabled + */ + uint32_t f1_en:1; + /** f2_en : R/W; bitpos: [2]; default: 0; + * When set, event_f2 generation is enabled + */ + uint32_t f2_en:1; + /** f0_pole : R/W; bitpos: [3]; default: 0; + * Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: + * level high + */ + uint32_t f0_pole:1; + /** f1_pole : R/W; bitpos: [4]; default: 0; + * Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: + * level high + */ + uint32_t f1_pole:1; + /** f2_pole : R/W; bitpos: [5]; default: 0; + * Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: + * level high + */ + uint32_t f2_pole:1; + /** event_f0 : RO; bitpos: [6]; default: 0; + * Set and reset by hardware. If set, event_f0 is on going + */ + uint32_t event_f0:1; + /** event_f1 : RO; bitpos: [7]; default: 0; + * Set and reset by hardware. If set, event_f1 is on going + */ + uint32_t event_f1:1; + /** event_f2 : RO; bitpos: [8]; default: 0; + * Set and reset by hardware. If set, event_f2 is on going + */ + uint32_t event_f2:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} mcpwm_fault_detect_reg_t; + + +/** Group: Capture Configuration and Status */ +/** Type of cap_timer_cfg register + * Configure capture timer + */ +typedef union { + struct { + /** cap_timer_en : R/W; bitpos: [0]; default: 0; + * When set, capture timer incrementing under APB_clk is enabled. + */ + uint32_t cap_timer_en:1; + /** cap_synci_en : R/W; bitpos: [1]; default: 0; + * When set, capture timer sync is enabled. + */ + uint32_t cap_synci_en:1; + /** cap_synci_sel : R/W; bitpos: [4:2]; default: 0; + * capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 + * sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, + * 6: SYNC2 from GPIO matrix + */ + uint32_t cap_synci_sel:3; + /** cap_sync_sw : WT; bitpos: [5]; default: 0; + * When reg_cap_synci_en is 1, write 1 will trigger a capture timer sync, capture + * timer is loaded with value in phase register. + */ + uint32_t cap_sync_sw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} mcpwm_cap_timer_cfg_reg_t; + +/** Type of cap_timer_phase register + * Phase for capture timer sync + */ +typedef union { + struct { + /** cap_phase : R/W; bitpos: [31:0]; default: 0; + * Phase value for capture timer sync operation. + */ + uint32_t cap_phase:32; + }; + uint32_t val; +} mcpwm_cap_timer_phase_reg_t; + +/** Type of cap_chn_cfg register + * Capture channel n configuration and enable + */ +typedef union { + struct { + /** capn_en : R/W; bitpos: [0]; default: 0; + * When set, capture on channel 0 is enabled + */ + uint32_t capn_en:1; + /** capn_mode : R/W; bitpos: [2:1]; default: 0; + * Edge of capture on channel n after prescaling. When bit0 is set to 1: enable + * capture on the negative edge, When bit1 is set to 1: enable capture on the positive + * edge. + */ + uint32_t capn_mode:2; + /** capn_prescale : R/W; bitpos: [10:3]; default: 0; + * Value of prescaling on possitive edge of CAPn. Prescale value = PWM_CAP0_PRESCALE + + * 1 + */ + uint32_t capn_prescale:8; + /** capn_in_invert : R/W; bitpos: [11]; default: 0; + * when set, CAPn form GPIO matrix is inverted before prescale + */ + uint32_t capn_in_invert:1; + /** capn_sw : WT; bitpos: [12]; default: 0; + * Write 1 will trigger a software forced capture on channel n + */ + uint32_t capn_sw:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} mcpwm_cap_chn_cfg_reg_t; + +/** Type of cap_chn register + * chn capture value status register + */ +typedef union { + struct { + /** capn_value : RO; bitpos: [31:0]; default: 0; + * Value of last capture on channel n + */ + uint32_t capn_value:32; + }; + uint32_t val; +} mcpwm_cap_chn_reg_t; + +/** Type of cap_status register + * Edge of last capture trigger + */ +typedef union { + struct { + /** cap0_edge : RO; bitpos: [0]; default: 0; + * Edge of last capture trigger on channel 0, 0: posedge, 1: negedge + */ + uint32_t cap0_edge:1; + /** cap1_edge : RO; bitpos: [1]; default: 0; + * Edge of last capture trigger on channel 1, 0: posedge, 1: negedge + */ + uint32_t cap1_edge:1; + /** cap2_edge : RO; bitpos: [2]; default: 0; + * Edge of last capture trigger on channel 2, 0: posedge, 1: negedge + */ + uint32_t cap2_edge:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} mcpwm_cap_status_reg_t; + + +/** Group: Enable update of active registers */ +/** Type of update_cfg register + * Enable update. + */ +typedef union { + struct { + /** global_up_en : R/W; bitpos: [0]; default: 1; + * The global enable of update of all active registers in MCPWM module + */ + uint32_t global_up_en:1; + /** global_force_up : R/W; bitpos: [1]; default: 0; + * a toggle (software invert its value) will trigger a forced update of all active + * registers in MCPWM module + */ + uint32_t global_force_up:1; + /** op0_up_en : R/W; bitpos: [2]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 + * are enabled + */ + uint32_t op0_up_en:1; + /** op0_force_up : R/W; bitpos: [3]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 0 + */ + uint32_t op0_force_up:1; + /** op1_up_en : R/W; bitpos: [4]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 + * are enabled + */ + uint32_t op1_up_en:1; + /** op1_force_up : R/W; bitpos: [5]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 1 + */ + uint32_t op1_force_up:1; + /** op2_up_en : R/W; bitpos: [6]; default: 1; + * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 + * are enabled + */ + uint32_t op2_up_en:1; + /** op2_force_up : R/W; bitpos: [7]; default: 0; + * a toggle (software invert its value) will trigger a forced update of active + * registers in PWM operator 2 + */ + uint32_t op2_force_up:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} mcpwm_update_cfg_reg_t; + + +/** Group: Manage Interrupts */ +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** timer0_stop_int_ena : R/W; bitpos: [0]; default: 0; + * The enable bit for the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_ena:1; + /** timer1_stop_int_ena : R/W; bitpos: [1]; default: 0; + * The enable bit for the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_ena:1; + /** timer2_stop_int_ena : R/W; bitpos: [2]; default: 0; + * The enable bit for the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_ena:1; + /** timer0_tez_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_ena:1; + /** timer1_tez_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_ena:1; + /** timer2_tez_int_ena : R/W; bitpos: [5]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_ena:1; + /** timer0_tep_int_ena : R/W; bitpos: [6]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_ena:1; + /** timer1_tep_int_ena : R/W; bitpos: [7]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_ena:1; + /** timer2_tep_int_ena : R/W; bitpos: [8]; default: 0; + * The enable bit for the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_ena:1; + /** fault0_int_ena : R/W; bitpos: [9]; default: 0; + * The enable bit for the interrupt triggered when event_f0 starts. + */ + uint32_t fault0_int_ena:1; + /** fault1_int_ena : R/W; bitpos: [10]; default: 0; + * The enable bit for the interrupt triggered when event_f1 starts. + */ + uint32_t fault1_int_ena:1; + /** fault2_int_ena : R/W; bitpos: [11]; default: 0; + * The enable bit for the interrupt triggered when event_f2 starts. + */ + uint32_t fault2_int_ena:1; + /** fault0_clr_int_ena : R/W; bitpos: [12]; default: 0; + * The enable bit for the interrupt triggered when event_f0 ends. + */ + uint32_t fault0_clr_int_ena:1; + /** fault1_clr_int_ena : R/W; bitpos: [13]; default: 0; + * The enable bit for the interrupt triggered when event_f1 ends. + */ + uint32_t fault1_clr_int_ena:1; + /** fault2_clr_int_ena : R/W; bitpos: [14]; default: 0; + * The enable bit for the interrupt triggered when event_f2 ends. + */ + uint32_t fault2_clr_int_ena:1; + /** cmpr0_tea_int_ena : R/W; bitpos: [15]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 0 TEA event + */ + uint32_t cmpr0_tea_int_ena:1; + /** cmpr1_tea_int_ena : R/W; bitpos: [16]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 1 TEA event + */ + uint32_t cmpr1_tea_int_ena:1; + /** cmpr2_tea_int_ena : R/W; bitpos: [17]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 2 TEA event + */ + uint32_t cmpr2_tea_int_ena:1; + /** cmpr0_teb_int_ena : R/W; bitpos: [18]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 0 TEB event + */ + uint32_t cmpr0_teb_int_ena:1; + /** cmpr1_teb_int_ena : R/W; bitpos: [19]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 1 TEB event + */ + uint32_t cmpr1_teb_int_ena:1; + /** cmpr2_teb_int_ena : R/W; bitpos: [20]; default: 0; + * The enable bit for the interrupt triggered by a PWM operator 2 TEB event + */ + uint32_t cmpr2_teb_int_ena:1; + /** tz0_cbc_int_ena : R/W; bitpos: [21]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + */ + uint32_t tz0_cbc_int_ena:1; + /** tz1_cbc_int_ena : R/W; bitpos: [22]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + */ + uint32_t tz1_cbc_int_ena:1; + /** tz2_cbc_int_ena : R/W; bitpos: [23]; default: 0; + * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + */ + uint32_t tz2_cbc_int_ena:1; + /** tz0_ost_int_ena : R/W; bitpos: [24]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM0. + */ + uint32_t tz0_ost_int_ena:1; + /** tz1_ost_int_ena : R/W; bitpos: [25]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM1. + */ + uint32_t tz1_ost_int_ena:1; + /** tz2_ost_int_ena : R/W; bitpos: [26]; default: 0; + * The enable bit for the interrupt triggered by a one-shot mode action on PWM2. + */ + uint32_t tz2_ost_int_ena:1; + /** cap0_int_ena : R/W; bitpos: [27]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 0. + */ + uint32_t cap0_int_ena:1; + /** cap1_int_ena : R/W; bitpos: [28]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 1. + */ + uint32_t cap1_int_ena:1; + /** cap2_int_ena : R/W; bitpos: [29]; default: 0; + * The enable bit for the interrupt triggered by capture on channel 2. + */ + uint32_t cap2_int_ena:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_ena_reg_t; + +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** timer0_stop_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw status bit for the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_raw:1; + /** timer1_stop_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw status bit for the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_raw:1; + /** timer2_stop_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw status bit for the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_raw:1; + /** timer0_tez_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_raw:1; + /** timer1_tez_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_raw:1; + /** timer2_tez_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_raw:1; + /** timer0_tep_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_raw:1; + /** timer1_tep_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_raw:1; + /** timer2_tep_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw status bit for the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_raw:1; + /** fault0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw status bit for the interrupt triggered when event_f0 starts. + */ + uint32_t fault0_int_raw:1; + /** fault1_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw status bit for the interrupt triggered when event_f1 starts. + */ + uint32_t fault1_int_raw:1; + /** fault2_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw status bit for the interrupt triggered when event_f2 starts. + */ + uint32_t fault2_int_raw:1; + /** fault0_clr_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw status bit for the interrupt triggered when event_f0 ends. + */ + uint32_t fault0_clr_int_raw:1; + /** fault1_clr_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw status bit for the interrupt triggered when event_f1 ends. + */ + uint32_t fault1_clr_int_raw:1; + /** fault2_clr_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw status bit for the interrupt triggered when event_f2 ends. + */ + uint32_t fault2_clr_int_raw:1; + /** cmpr0_tea_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 0 TEA event + */ + uint32_t cmpr0_tea_int_raw:1; + /** cmpr1_tea_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 1 TEA event + */ + uint32_t cmpr1_tea_int_raw:1; + /** cmpr2_tea_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 2 TEA event + */ + uint32_t cmpr2_tea_int_raw:1; + /** cmpr0_teb_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 0 TEB event + */ + uint32_t cmpr0_teb_int_raw:1; + /** cmpr1_teb_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 1 TEB event + */ + uint32_t cmpr1_teb_int_raw:1; + /** cmpr2_teb_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw status bit for the interrupt triggered by a PWM operator 2 TEB event + */ + uint32_t cmpr2_teb_int_raw:1; + /** tz0_cbc_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM0. + */ + uint32_t tz0_cbc_int_raw:1; + /** tz1_cbc_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM1. + */ + uint32_t tz1_cbc_int_raw:1; + /** tz2_cbc_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on + * PWM2. + */ + uint32_t tz2_cbc_int_raw:1; + /** tz0_ost_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM0. + */ + uint32_t tz0_ost_int_raw:1; + /** tz1_ost_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM1. + */ + uint32_t tz1_ost_int_raw:1; + /** tz2_ost_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * The raw status bit for the interrupt triggered by a one-shot mode action on PWM2. + */ + uint32_t tz2_ost_int_raw:1; + /** cap0_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 0. + */ + uint32_t cap0_int_raw:1; + /** cap1_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 1. + */ + uint32_t cap1_int_raw:1; + /** cap2_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * The raw status bit for the interrupt triggered by capture on channel 2. + */ + uint32_t cap2_int_raw:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** timer0_stop_int_st : RO; bitpos: [0]; default: 0; + * The masked status bit for the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_st:1; + /** timer1_stop_int_st : RO; bitpos: [1]; default: 0; + * The masked status bit for the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_st:1; + /** timer2_stop_int_st : RO; bitpos: [2]; default: 0; + * The masked status bit for the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_st:1; + /** timer0_tez_int_st : RO; bitpos: [3]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_st:1; + /** timer1_tez_int_st : RO; bitpos: [4]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_st:1; + /** timer2_tez_int_st : RO; bitpos: [5]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_st:1; + /** timer0_tep_int_st : RO; bitpos: [6]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_st:1; + /** timer1_tep_int_st : RO; bitpos: [7]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_st:1; + /** timer2_tep_int_st : RO; bitpos: [8]; default: 0; + * The masked status bit for the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_st:1; + /** fault0_int_st : RO; bitpos: [9]; default: 0; + * The masked status bit for the interrupt triggered when event_f0 starts. + */ + uint32_t fault0_int_st:1; + /** fault1_int_st : RO; bitpos: [10]; default: 0; + * The masked status bit for the interrupt triggered when event_f1 starts. + */ + uint32_t fault1_int_st:1; + /** fault2_int_st : RO; bitpos: [11]; default: 0; + * The masked status bit for the interrupt triggered when event_f2 starts. + */ + uint32_t fault2_int_st:1; + /** fault0_clr_int_st : RO; bitpos: [12]; default: 0; + * The masked status bit for the interrupt triggered when event_f0 ends. + */ + uint32_t fault0_clr_int_st:1; + /** fault1_clr_int_st : RO; bitpos: [13]; default: 0; + * The masked status bit for the interrupt triggered when event_f1 ends. + */ + uint32_t fault1_clr_int_st:1; + /** fault2_clr_int_st : RO; bitpos: [14]; default: 0; + * The masked status bit for the interrupt triggered when event_f2 ends. + */ + uint32_t fault2_clr_int_st:1; + /** cmpr0_tea_int_st : RO; bitpos: [15]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 0 TEA event + */ + uint32_t cmpr0_tea_int_st:1; + /** cmpr1_tea_int_st : RO; bitpos: [16]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 1 TEA event + */ + uint32_t cmpr1_tea_int_st:1; + /** cmpr2_tea_int_st : RO; bitpos: [17]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 2 TEA event + */ + uint32_t cmpr2_tea_int_st:1; + /** cmpr0_teb_int_st : RO; bitpos: [18]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 0 TEB event + */ + uint32_t cmpr0_teb_int_st:1; + /** cmpr1_teb_int_st : RO; bitpos: [19]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 1 TEB event + */ + uint32_t cmpr1_teb_int_st:1; + /** cmpr2_teb_int_st : RO; bitpos: [20]; default: 0; + * The masked status bit for the interrupt triggered by a PWM operator 2 TEB event + */ + uint32_t cmpr2_teb_int_st:1; + /** tz0_cbc_int_st : RO; bitpos: [21]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM0. + */ + uint32_t tz0_cbc_int_st:1; + /** tz1_cbc_int_st : RO; bitpos: [22]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM1. + */ + uint32_t tz1_cbc_int_st:1; + /** tz2_cbc_int_st : RO; bitpos: [23]; default: 0; + * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action + * on PWM2. + */ + uint32_t tz2_cbc_int_st:1; + /** tz0_ost_int_st : RO; bitpos: [24]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM0. + */ + uint32_t tz0_ost_int_st:1; + /** tz1_ost_int_st : RO; bitpos: [25]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM1. + */ + uint32_t tz1_ost_int_st:1; + /** tz2_ost_int_st : RO; bitpos: [26]; default: 0; + * The masked status bit for the interrupt triggered by a one-shot mode action on PWM2. + */ + uint32_t tz2_ost_int_st:1; + /** cap0_int_st : RO; bitpos: [27]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 0. + */ + uint32_t cap0_int_st:1; + /** cap1_int_st : RO; bitpos: [28]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 1. + */ + uint32_t cap1_int_st:1; + /** cap2_int_st : RO; bitpos: [29]; default: 0; + * The masked status bit for the interrupt triggered by capture on channel 2. + */ + uint32_t cap2_int_st:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_st_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** timer0_stop_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_clr:1; + /** timer1_stop_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_clr:1; + /** timer2_stop_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_clr:1; + /** timer0_tez_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_clr:1; + /** timer1_tez_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_clr:1; + /** timer2_tez_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_clr:1; + /** timer0_tep_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_clr:1; + /** timer1_tep_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_clr:1; + /** timer2_tep_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_clr:1; + /** fault0_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the interrupt triggered when event_f0 starts. + */ + uint32_t fault0_int_clr:1; + /** fault1_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear the interrupt triggered when event_f1 starts. + */ + uint32_t fault1_int_clr:1; + /** fault2_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the interrupt triggered when event_f2 starts. + */ + uint32_t fault2_int_clr:1; + /** fault0_clr_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear the interrupt triggered when event_f0 ends. + */ + uint32_t fault0_clr_int_clr:1; + /** fault1_clr_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear the interrupt triggered when event_f1 ends. + */ + uint32_t fault1_clr_int_clr:1; + /** fault2_clr_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear the interrupt triggered when event_f2 ends. + */ + uint32_t fault2_clr_int_clr:1; + /** cmpr0_tea_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event + */ + uint32_t cmpr0_tea_int_clr:1; + /** cmpr1_tea_int_clr : WT; bitpos: [16]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event + */ + uint32_t cmpr1_tea_int_clr:1; + /** cmpr2_tea_int_clr : WT; bitpos: [17]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event + */ + uint32_t cmpr2_tea_int_clr:1; + /** cmpr0_teb_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event + */ + uint32_t cmpr0_teb_int_clr:1; + /** cmpr1_teb_int_clr : WT; bitpos: [19]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event + */ + uint32_t cmpr1_teb_int_clr:1; + /** cmpr2_teb_int_clr : WT; bitpos: [20]; default: 0; + * Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event + */ + uint32_t cmpr2_teb_int_clr:1; + /** tz0_cbc_int_clr : WT; bitpos: [21]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM0. + */ + uint32_t tz0_cbc_int_clr:1; + /** tz1_cbc_int_clr : WT; bitpos: [22]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM1. + */ + uint32_t tz1_cbc_int_clr:1; + /** tz2_cbc_int_clr : WT; bitpos: [23]; default: 0; + * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on + * PWM2. + */ + uint32_t tz2_cbc_int_clr:1; + /** tz0_ost_int_clr : WT; bitpos: [24]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0. + */ + uint32_t tz0_ost_int_clr:1; + /** tz1_ost_int_clr : WT; bitpos: [25]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1. + */ + uint32_t tz1_ost_int_clr:1; + /** tz2_ost_int_clr : WT; bitpos: [26]; default: 0; + * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2. + */ + uint32_t tz2_ost_int_clr:1; + /** cap0_int_clr : WT; bitpos: [27]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 0. + */ + uint32_t cap0_int_clr:1; + /** cap1_int_clr : WT; bitpos: [28]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 1. + */ + uint32_t cap1_int_clr:1; + /** cap2_int_clr : WT; bitpos: [29]; default: 0; + * Set this bit to clear the interrupt triggered by capture on channel 2. + */ + uint32_t cap2_int_clr:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_clr_reg_t; + + +/** Group: MCPWM event enable register */ +/** Type of evt_en register + * MCPWM event enable register + */ +typedef union { + struct { + /** evt_timer0_stop_en : R/W; bitpos: [0]; default: 0; + * set this bit high to enable timer0 stop event generate + */ + uint32_t evt_timer0_stop_en:1; + /** evt_timer1_stop_en : R/W; bitpos: [1]; default: 0; + * set this bit high to enable timer1 stop event generate + */ + uint32_t evt_timer1_stop_en:1; + /** evt_timer2_stop_en : R/W; bitpos: [2]; default: 0; + * set this bit high to enable timer2 stop event generate + */ + uint32_t evt_timer2_stop_en:1; + /** evt_timer0_tez_en : R/W; bitpos: [3]; default: 0; + * set this bit high to enable timer0 equal zero event generate + */ + uint32_t evt_timer0_tez_en:1; + /** evt_timer1_tez_en : R/W; bitpos: [4]; default: 0; + * set this bit high to enable timer1 equal zero event generate + */ + uint32_t evt_timer1_tez_en:1; + /** evt_timer2_tez_en : R/W; bitpos: [5]; default: 0; + * set this bit high to enable timer2 equal zero event generate + */ + uint32_t evt_timer2_tez_en:1; + /** evt_timer0_tep_en : R/W; bitpos: [6]; default: 0; + * set this bit high to enable timer0 equal period event generate + */ + uint32_t evt_timer0_tep_en:1; + /** evt_timer1_tep_en : R/W; bitpos: [7]; default: 0; + * set this bit high to enable timer1 equal period event generate + */ + uint32_t evt_timer1_tep_en:1; + /** evt_timer2_tep_en : R/W; bitpos: [8]; default: 0; + * set this bit high to enable timer2 equal period event generate + */ + uint32_t evt_timer2_tep_en:1; + /** evt_op0_tea_en : R/W; bitpos: [9]; default: 0; + * set this bit high to enable PWM generator0 timer equal a event generate + */ + uint32_t evt_op0_tea_en:1; + /** evt_op1_tea_en : R/W; bitpos: [10]; default: 0; + * set this bit high to enable PWM generator1 timer equal a event generate + */ + uint32_t evt_op1_tea_en:1; + /** evt_op2_tea_en : R/W; bitpos: [11]; default: 0; + * set this bit high to enable PWM generator2 timer equal a event generate + */ + uint32_t evt_op2_tea_en:1; + /** evt_op0_teb_en : R/W; bitpos: [12]; default: 0; + * set this bit high to enable PWM generator0 timer equal b event generate + */ + uint32_t evt_op0_teb_en:1; + /** evt_op1_teb_en : R/W; bitpos: [13]; default: 0; + * set this bit high to enable PWM generator1 timer equal b event generate + */ + uint32_t evt_op1_teb_en:1; + /** evt_op2_teb_en : R/W; bitpos: [14]; default: 0; + * set this bit high to enable PWM generator2 timer equal b event generate + */ + uint32_t evt_op2_teb_en:1; + /** evt_f0_en : R/W; bitpos: [15]; default: 0; + * set this bit high to enable fault0 event generate + */ + uint32_t evt_f0_en:1; + /** evt_f1_en : R/W; bitpos: [16]; default: 0; + * set this bit high to enable fault1 event generate + */ + uint32_t evt_f1_en:1; + /** evt_f2_en : R/W; bitpos: [17]; default: 0; + * set this bit high to enable fault2 event generate + */ + uint32_t evt_f2_en:1; + /** evt_f0_clr_en : R/W; bitpos: [18]; default: 0; + * set this bit high to enable fault0 clear event generate + */ + uint32_t evt_f0_clr_en:1; + /** evt_f1_clr_en : R/W; bitpos: [19]; default: 0; + * set this bit high to enable fault1 clear event generate + */ + uint32_t evt_f1_clr_en:1; + /** evt_f2_clr_en : R/W; bitpos: [20]; default: 0; + * set this bit high to enable fault2 clear event generate + */ + uint32_t evt_f2_clr_en:1; + /** evt_tz0_cbc_en : R/W; bitpos: [21]; default: 0; + * set this bit high to enable cycle by cycle trip0 event generate + */ + uint32_t evt_tz0_cbc_en:1; + /** evt_tz1_cbc_en : R/W; bitpos: [22]; default: 0; + * set this bit high to enable cycle by cycle trip1 event generate + */ + uint32_t evt_tz1_cbc_en:1; + /** evt_tz2_cbc_en : R/W; bitpos: [23]; default: 0; + * set this bit high to enable cycle by cycle trip2 event generate + */ + uint32_t evt_tz2_cbc_en:1; + /** evt_tz0_ost_en : R/W; bitpos: [24]; default: 0; + * set this bit high to enable one shot trip0 event generate + */ + uint32_t evt_tz0_ost_en:1; + /** evt_tz1_ost_en : R/W; bitpos: [25]; default: 0; + * set this bit high to enable one shot trip1 event generate + */ + uint32_t evt_tz1_ost_en:1; + /** evt_tz2_ost_en : R/W; bitpos: [26]; default: 0; + * set this bit high to enable one shot trip2 event generate + */ + uint32_t evt_tz2_ost_en:1; + /** evt_cap0_en : R/W; bitpos: [27]; default: 0; + * set this bit high to enable capture0 event generate + */ + uint32_t evt_cap0_en:1; + /** evt_cap1_en : R/W; bitpos: [28]; default: 0; + * set this bit high to enable capture1 event generate + */ + uint32_t evt_cap1_en:1; + /** evt_cap2_en : R/W; bitpos: [29]; default: 0; + * set this bit high to enable capture2 event generate + */ + uint32_t evt_cap2_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_evt_en_reg_t; + + +/** Group: MCPWM task enable register */ +/** Type of task_en register + * MCPWM task enable register + */ +typedef union { + struct { + /** task_cmpr0_a_up_en : R/W; bitpos: [0]; default: 0; + * set this bit high to enable PWM generator0 timer stamp A's shadow register update + * task receive + */ + uint32_t task_cmpr0_a_up_en:1; + /** task_cmpr1_a_up_en : R/W; bitpos: [1]; default: 0; + * set this bit high to enable PWM generator1 timer stamp A's shadow register update + * task receive + */ + uint32_t task_cmpr1_a_up_en:1; + /** task_cmpr2_a_up_en : R/W; bitpos: [2]; default: 0; + * set this bit high to enable PWM generator2 timer stamp A's shadow register update + * task receive + */ + uint32_t task_cmpr2_a_up_en:1; + /** task_cmpr0_b_up_en : R/W; bitpos: [3]; default: 0; + * set this bit high to enable PWM generator0 timer stamp B's shadow register update + * task receive + */ + uint32_t task_cmpr0_b_up_en:1; + /** task_cmpr1_b_up_en : R/W; bitpos: [4]; default: 0; + * set this bit high to enable PWM generator1 timer stamp B's shadow register update + * task receive + */ + uint32_t task_cmpr1_b_up_en:1; + /** task_cmpr2_b_up_en : R/W; bitpos: [5]; default: 0; + * set this bit high to enable PWM generator2 timer stamp B's shadow register update + * task receive + */ + uint32_t task_cmpr2_b_up_en:1; + /** task_gen_stop_en : R/W; bitpos: [6]; default: 0; + * set this bit high to enable all PWM generate stop task receive + */ + uint32_t task_gen_stop_en:1; + /** task_timer0_sync_en : R/W; bitpos: [7]; default: 0; + * set this bit high to enable timer0 sync task receive + */ + uint32_t task_timer0_sync_en:1; + /** task_timer1_sync_en : R/W; bitpos: [8]; default: 0; + * set this bit high to enable timer1 sync task receive + */ + uint32_t task_timer1_sync_en:1; + /** task_timer2_sync_en : R/W; bitpos: [9]; default: 0; + * set this bit high to enable timer2 sync task receive + */ + uint32_t task_timer2_sync_en:1; + /** task_timer0_period_up_en : R/W; bitpos: [10]; default: 0; + * set this bit high to enable timer0 period update task receive + */ + uint32_t task_timer0_period_up_en:1; + /** task_timer1_period_up_en : R/W; bitpos: [11]; default: 0; + * set this bit high to enable timer1 period update task receive + */ + uint32_t task_timer1_period_up_en:1; + /** task_timer2_period_up_en : R/W; bitpos: [12]; default: 0; + * set this bit high to enable timer2 period update task receive + */ + uint32_t task_timer2_period_up_en:1; + /** task_tz0_ost_en : R/W; bitpos: [13]; default: 0; + * set this bit high to enable one shot trip0 task receive + */ + uint32_t task_tz0_ost_en:1; + /** task_tz1_ost_en : R/W; bitpos: [14]; default: 0; + * set this bit high to enable one shot trip1 task receive + */ + uint32_t task_tz1_ost_en:1; + /** task_tz2_ost_en : R/W; bitpos: [15]; default: 0; + * set this bit high to enable one shot trip2 task receive + */ + uint32_t task_tz2_ost_en:1; + /** task_clr0_ost_en : R/W; bitpos: [16]; default: 0; + * set this bit high to enable one shot trip0 clear task receive + */ + uint32_t task_clr0_ost_en:1; + /** task_clr1_ost_en : R/W; bitpos: [17]; default: 0; + * set this bit high to enable one shot trip1 clear task receive + */ + uint32_t task_clr1_ost_en:1; + /** task_clr2_ost_en : R/W; bitpos: [18]; default: 0; + * set this bit high to enable one shot trip2 clear task receive + */ + uint32_t task_clr2_ost_en:1; + /** task_cap0_en : R/W; bitpos: [19]; default: 0; + * set this bit high to enable capture0 task receive + */ + uint32_t task_cap0_en:1; + /** task_cap1_en : R/W; bitpos: [20]; default: 0; + * set this bit high to enable capture1 task receive + */ + uint32_t task_cap1_en:1; + /** task_cap2_en : R/W; bitpos: [21]; default: 0; + * set this bit high to enable capture2 task receive + */ + uint32_t task_cap2_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} mcpwm_task_en_reg_t; + + +/** Group: MCPWM APB configuration register */ +/** Type of clk register + * MCPWM APB configuration register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Force clock on for this register file + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} mcpwm_clk_reg_t; + + +/** Group: Version Register */ +/** Type of version register + * Version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35656256; + * Version of this register file + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} mcpwm_version_reg_t; + +typedef struct { + mcpwm_timer_cfg0_reg_t timer_cfg0; + mcpwm_timer_cfg1_reg_t timer_cfg1; + mcpwm_timer_sync_reg_t timer_sync; + mcpwm_timer_status_reg_t timer_status; +} mcpwm_timer_regs_t; + +typedef struct { + mcpwm_gen_stmp_cfg_reg_t gen_stmp_cfg; + mcpwm_gen_tstmp_reg_t timestamp[2]; + mcpwm_gen_cfg0_reg_t gen_cfg0; + mcpwm_gen_force_reg_t gen_force; + mcpwm_gen_reg_t generator[2]; + mcpwm_dt_cfg_reg_t dt_cfg; + mcpwm_dt_fed_cfg_reg_t dt_fed_cfg; + mcpwm_dt_red_cfg_reg_t dt_red_cfg; + mcpwm_carrier_cfg_reg_t carrier_cfg; + mcpwm_fh_cfg0_reg_t fh_cfg0; + mcpwm_fh_cfg1_reg_t fh_cfg1; + mcpwm_fh_status_reg_t fh_status; +} mcpwm_operator_reg_t; + +typedef struct mcpwm_dev_t { + volatile mcpwm_clk_cfg_reg_t clk_cfg; + volatile mcpwm_timer_regs_t timer[3]; + volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg; + volatile mcpwm_operator_timersel_reg_t operator_timersel; + volatile mcpwm_operator_reg_t operators[3]; + volatile mcpwm_fault_detect_reg_t fault_detect; + volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg; + volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase; + volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3]; + volatile mcpwm_cap_chn_reg_t cap_chn[3]; + volatile mcpwm_cap_status_reg_t cap_status; + volatile mcpwm_update_cfg_reg_t update_cfg; + volatile mcpwm_int_ena_reg_t int_ena; + volatile mcpwm_int_raw_reg_t int_raw; + volatile mcpwm_int_st_reg_t int_st; + volatile mcpwm_int_clr_reg_t int_clr; + volatile mcpwm_evt_en_reg_t evt_en; + volatile mcpwm_task_en_reg_t task_en; + volatile mcpwm_clk_reg_t clk; + volatile mcpwm_version_reg_t version; +} mcpwm_dev_t; + +extern mcpwm_dev_t MCPWM; + +#ifndef __cplusplus +_Static_assert(sizeof(mcpwm_dev_t) == 0x130, "Invalid size of mcpwm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/mem_monitor_reg.h b/components/soc/esp32c6/include/soc/mem_monitor_reg.h new file mode 100644 index 0000000000..fccde61ad7 --- /dev/null +++ b/components/soc/esp32c6/include/soc/mem_monitor_reg.h @@ -0,0 +1,184 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** MEM_MONITOR_LOG_SETTING_REG register + * log config regsiter + */ +#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0) +/** MEM_MONITOR_LOG_ENA : R/W; bitpos: [2:0]; default: 0; + * enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA. + */ +#define MEM_MONITOR_LOG_ENA 0x00000007U +#define MEM_MONITOR_LOG_ENA_M (MEM_MONITOR_LOG_ENA_V << MEM_MONITOR_LOG_ENA_S) +#define MEM_MONITOR_LOG_ENA_V 0x00000007U +#define MEM_MONITOR_LOG_ENA_S 0 +/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [6:3]; default: 0; + * This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100: + * HALFWORD monitor, 4'b1000: BYTE monitor. + */ +#define MEM_MONITOR_LOG_MODE 0x0000000FU +#define MEM_MONITOR_LOG_MODE_M (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S) +#define MEM_MONITOR_LOG_MODE_V 0x0000000FU +#define MEM_MONITOR_LOG_MODE_S 3 +/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [7]; default: 1; + * Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END + */ +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE (BIT(7)) +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S) +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V 0x00000001U +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 7 + +/** MEM_MONITOR_LOG_CHECK_DATA_REG register + * check data regsiter + */ +#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x4) +/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0; + * The special check data, when write this special data, it will trigger logging. + */ +#define MEM_MONITOR_LOG_CHECK_DATA 0xFFFFFFFFU +#define MEM_MONITOR_LOG_CHECK_DATA_M (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S) +#define MEM_MONITOR_LOG_CHECK_DATA_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_CHECK_DATA_S 0 + +/** MEM_MONITOR_LOG_DATA_MASK_REG register + * check data mask register + */ +#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0x8) +/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0; + * byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1 + * mask second byte, and so on. + */ +#define MEM_MONITOR_LOG_DATA_MASK 0x0000000FU +#define MEM_MONITOR_LOG_DATA_MASK_M (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S) +#define MEM_MONITOR_LOG_DATA_MASK_V 0x0000000FU +#define MEM_MONITOR_LOG_DATA_MASK_S 0 + +/** MEM_MONITOR_LOG_MIN_REG register + * log boundary regsiter + */ +#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0xc) +/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0; + * the min address of log range + */ +#define MEM_MONITOR_LOG_MIN 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MIN_M (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S) +#define MEM_MONITOR_LOG_MIN_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MIN_S 0 + +/** MEM_MONITOR_LOG_MAX_REG register + * log boundary regsiter + */ +#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x10) +/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0; + * the max address of log range + */ +#define MEM_MONITOR_LOG_MAX 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MAX_M (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S) +#define MEM_MONITOR_LOG_MAX_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MAX_S 0 + +/** MEM_MONITOR_LOG_MEM_START_REG register + * log message store range register + */ +#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x14) +/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0; + * the start address of writing logging message + */ +#define MEM_MONITOR_LOG_MEM_START 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_START_M (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S) +#define MEM_MONITOR_LOG_MEM_START_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_START_S 0 + +/** MEM_MONITOR_LOG_MEM_END_REG register + * log message store range register + */ +#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x18) +/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0; + * the end address of writing logging message + */ +#define MEM_MONITOR_LOG_MEM_END 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_END_M (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S) +#define MEM_MONITOR_LOG_MEM_END_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_END_S 0 + +/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register + * current writing address. + */ +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x1c) +/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0; + * means next writing address + */ +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S) +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S 0 + +/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register + * writing address update + */ +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x20) +/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0; + * Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, + * MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START + */ +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE (BIT(0)) +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S) +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V 0x00000001U +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S 0 + +/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register + * full flag status register + */ +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x24) +/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0; + * 1 means memory write loop at least one time at the range of MEM_START and MEM_END + */ +#define MEM_MONITOR_LOG_MEM_FULL_FLAG (BIT(0)) +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S) +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V 0x00000001U +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S 0 +/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0; + * Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG + */ +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG (BIT(1)) +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S) +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V 0x00000001U +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S 1 + +/** MEM_MONITOR_CLOCK_GATE_REG register + * clock gate force on register + */ +#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x28) +/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to force on the clk of mem_monitor register + */ +#define MEM_MONITOR_CLK_EN (BIT(0)) +#define MEM_MONITOR_CLK_EN_M (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S) +#define MEM_MONITOR_CLK_EN_V 0x00000001U +#define MEM_MONITOR_CLK_EN_S 0 + +/** MEM_MONITOR_DATE_REG register + * version register + */ +#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3fc) +/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 35660096; + * version register + */ +#define MEM_MONITOR_DATE 0x0FFFFFFFU +#define MEM_MONITOR_DATE_M (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S) +#define MEM_MONITOR_DATE_V 0x0FFFFFFFU +#define MEM_MONITOR_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/mem_monitor_struct.h b/components/soc/esp32c6/include/soc/mem_monitor_struct.h new file mode 100644 index 0000000000..6fd735edf5 --- /dev/null +++ b/components/soc/esp32c6/include/soc/mem_monitor_struct.h @@ -0,0 +1,220 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configuration registers */ +/** Type of log_setting register + * log config regsiter + */ +typedef union { + struct { + /** log_ena : R/W; bitpos: [2:0]; default: 0; + * enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA. + */ + uint32_t log_ena:3; + /** log_mode : R/W; bitpos: [6:3]; default: 0; + * This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100: + * HALFWORD monitor, 4'b1000: BYTE monitor. + */ + uint32_t log_mode:4; + /** log_mem_loop_enable : R/W; bitpos: [7]; default: 1; + * Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END + */ + uint32_t log_mem_loop_enable:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} mem_monitor_log_setting_reg_t; + +/** Type of log_check_data register + * check data regsiter + */ +typedef union { + struct { + /** log_check_data : R/W; bitpos: [31:0]; default: 0; + * The special check data, when write this special data, it will trigger logging. + */ + uint32_t log_check_data:32; + }; + uint32_t val; +} mem_monitor_log_check_data_reg_t; + +/** Type of log_data_mask register + * check data mask register + */ +typedef union { + struct { + /** log_data_mask : R/W; bitpos: [3:0]; default: 0; + * byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1 + * mask second byte, and so on. + */ + uint32_t log_data_mask:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} mem_monitor_log_data_mask_reg_t; + +/** Type of log_min register + * log boundary regsiter + */ +typedef union { + struct { + /** log_min : R/W; bitpos: [31:0]; default: 0; + * the min address of log range + */ + uint32_t log_min:32; + }; + uint32_t val; +} mem_monitor_log_min_reg_t; + +/** Type of log_max register + * log boundary regsiter + */ +typedef union { + struct { + /** log_max : R/W; bitpos: [31:0]; default: 0; + * the max address of log range + */ + uint32_t log_max:32; + }; + uint32_t val; +} mem_monitor_log_max_reg_t; + +/** Type of log_mem_start register + * log message store range register + */ +typedef union { + struct { + /** log_mem_start : R/W; bitpos: [31:0]; default: 0; + * the start address of writing logging message + */ + uint32_t log_mem_start:32; + }; + uint32_t val; +} mem_monitor_log_mem_start_reg_t; + +/** Type of log_mem_end register + * log message store range register + */ +typedef union { + struct { + /** log_mem_end : R/W; bitpos: [31:0]; default: 0; + * the end address of writing logging message + */ + uint32_t log_mem_end:32; + }; + uint32_t val; +} mem_monitor_log_mem_end_reg_t; + +/** Type of log_mem_current_addr register + * current writing address. + */ +typedef union { + struct { + /** log_mem_current_addr : RO; bitpos: [31:0]; default: 0; + * means next writing address + */ + uint32_t log_mem_current_addr:32; + }; + uint32_t val; +} mem_monitor_log_mem_current_addr_reg_t; + +/** Type of log_mem_addr_update register + * writing address update + */ +typedef union { + struct { + /** log_mem_addr_update : WT; bitpos: [0]; default: 0; + * Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, + * MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START + */ + uint32_t log_mem_addr_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} mem_monitor_log_mem_addr_update_reg_t; + +/** Type of log_mem_full_flag register + * full flag status register + */ +typedef union { + struct { + /** log_mem_full_flag : RO; bitpos: [0]; default: 0; + * 1 means memory write loop at least one time at the range of MEM_START and MEM_END + */ + uint32_t log_mem_full_flag:1; + /** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0; + * Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG + */ + uint32_t clr_log_mem_full_flag:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} mem_monitor_log_mem_full_flag_reg_t; + + +/** Group: clk register */ +/** Type of clock_gate register + * clock gate force on register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Set 1 to force on the clk of mem_monitor register + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} mem_monitor_clock_gate_reg_t; + + +/** Group: version register */ +/** Type of date register + * version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35660096; + * version register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} mem_monitor_date_reg_t; + + +typedef struct mem_monitor_dev_t { + volatile mem_monitor_log_setting_reg_t log_setting; + volatile mem_monitor_log_check_data_reg_t log_check_data; + volatile mem_monitor_log_data_mask_reg_t log_data_mask; + volatile mem_monitor_log_min_reg_t log_min; + volatile mem_monitor_log_max_reg_t log_max; + volatile mem_monitor_log_mem_start_reg_t log_mem_start; + volatile mem_monitor_log_mem_end_reg_t log_mem_end; + volatile mem_monitor_log_mem_current_addr_reg_t log_mem_current_addr; + volatile mem_monitor_log_mem_addr_update_reg_t log_mem_addr_update; + volatile mem_monitor_log_mem_full_flag_reg_t log_mem_full_flag; + volatile mem_monitor_clock_gate_reg_t clock_gate; + uint32_t reserved_02c[244]; + volatile mem_monitor_date_reg_t date; +} mem_monitor_dev_t; + +extern mem_monitor_dev_t MEM_MONITOR; + +#ifndef __cplusplus +_Static_assert(sizeof(mem_monitor_dev_t) == 0x400, "Invalid size of mem_monitor_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/memprot_defs.h b/components/soc/esp32c6/include/soc/memprot_defs.h new file mode 100644 index 0000000000..6db06a8b26 --- /dev/null +++ b/components/soc/esp32c6/include/soc/memprot_defs.h @@ -0,0 +1,91 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc/soc.h" +#include "esp32c6/rom/cache.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef union { + struct { + uint32_t cat0 : 2; + uint32_t cat1 : 2; + uint32_t cat2 : 2; + uint32_t res0 : 8; + uint32_t splitaddr : 8; + uint32_t res1 : 10; + }; + uint32_t val; +} constrain_reg_fields_t; + +#ifndef I_D_SRAM_SEGMENT_SIZE +#define I_D_SRAM_SEGMENT_SIZE 0x20000 +#endif + +#define I_D_SPLIT_LINE_SHIFT 0x9 +#define I_D_FAULT_ADDR_SHIFT 0x2 + +#define DRAM_SRAM_START 0x3FC7C000 + +//IRAM0 + +//16kB (ICACHE) +#define IRAM0_SRAM_LEVEL_0_LOW SOC_IRAM_LOW //0x40370000 +#define IRAM0_SRAM_LEVEL_0_HIGH (IRAM0_SRAM_LEVEL_0_LOW + CACHE_MEMORY_IBANK_SIZE - 0x1) //0x4037FFFF + +//128kB (LEVEL 1) +#define IRAM0_SRAM_LEVEL_1_LOW (IRAM0_SRAM_LEVEL_0_HIGH + 0x1) //0x40380000 +#define IRAM0_SRAM_LEVEL_1_HIGH (IRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x4039FFFF + +//128kB (LEVEL 2) +#define IRAM0_SRAM_LEVEL_2_LOW (IRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x403A0000 +#define IRAM0_SRAM_LEVEL_2_HIGH (IRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403BFFFF + +//128kB (LEVEL 3) +#define IRAM0_SRAM_LEVEL_3_LOW (IRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x403C0000 +#define IRAM0_SRAM_LEVEL_3_HIGH (IRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403DFFFF + +//permission bits +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_F 0x4 + +//DRAM0 + +//16kB ICACHE not available from DRAM0 + +//128kB (LEVEL 1) +#define DRAM0_SRAM_LEVEL_1_LOW SOC_DRAM_LOW //0x3FC80000 +#define DRAM0_SRAM_LEVEL_1_HIGH (DRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FC9FFFF + +//128kB (LEVEL 2) +#define DRAM0_SRAM_LEVEL_2_LOW (DRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x3FCA0000 +#define DRAM0_SRAM_LEVEL_2_HIGH (DRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCBFFFF + +//128kB (LEVEL 3) +#define DRAM0_SRAM_LEVEL_3_LOW (DRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x3FCC0000 +#define DRAM0_SRAM_LEVEL_3_HIGH (DRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCDFFFF + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2 + +//RTC FAST + +//permission bits +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_W 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_R 0x2 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F 0x4 + +#define AREA_LOW 0 +#define AREA_HIGH 1 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/mmu.h b/components/soc/esp32c6/include/soc/mmu.h new file mode 100644 index 0000000000..4ce5d7326f --- /dev/null +++ b/components/soc/esp32c6/include/soc/mmu.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/ext_mem_defs.h" +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Defined for flash mmap */ +#define SOC_MMU_REGIONS_COUNT 1 +#define SOC_MMU_PAGES_PER_REGION 256 +#define SOC_MMU_IROM0_PAGES_START (CACHE_IROM_MMU_START / sizeof(uint32_t)) +#define SOC_MMU_IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t)) +#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t)) +#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t)) +#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL +#define SOC_MMU_ADDR_MASK (MMU_VALID - 1) +#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash +#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE +#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW +#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START +#define SOC_MMU_VADDR0_START_ADDR (SOC_IROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE)) +#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/otp_debug_reg.h b/components/soc/esp32c6/include/soc/otp_debug_reg.h new file mode 100644 index 0000000000..6d0e84c69f --- /dev/null +++ b/components/soc/esp32c6/include/soc/otp_debug_reg.h @@ -0,0 +1,1600 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** OTP_DEBUG_WR_DIS_REG register + * Otp debuger block0 data register1. + */ +#define OTP_DEBUG_WR_DIS_REG (DR_REG_OTP_DEBUG_BASE + 0x0) +/** OTP_DEBUG_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0; + * Otp block0 write disable data. + */ +#define OTP_DEBUG_BLOCK0_WR_DIS 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_WR_DIS_M (OTP_DEBUG_BLOCK0_WR_DIS_V << OTP_DEBUG_BLOCK0_WR_DIS_S) +#define OTP_DEBUG_BLOCK0_WR_DIS_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_WR_DIS_S 0 + +/** OTP_DEBUG_BLK0_BACKUP1_W1_REG register + * Otp debuger block0 data register2. + */ +#define OTP_DEBUG_BLK0_BACKUP1_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x4) +/** OTP_DEBUG_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word1 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP1_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W1_M (OTP_DEBUG_BLOCK0_BACKUP1_W1_V << OTP_DEBUG_BLOCK0_BACKUP1_W1_S) +#define OTP_DEBUG_BLOCK0_BACKUP1_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W1_S 0 + +/** OTP_DEBUG_BLK0_BACKUP1_W2_REG register + * Otp debuger block0 data register3. + */ +#define OTP_DEBUG_BLK0_BACKUP1_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x8) +/** OTP_DEBUG_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word2 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP1_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W2_M (OTP_DEBUG_BLOCK0_BACKUP1_W2_V << OTP_DEBUG_BLOCK0_BACKUP1_W2_S) +#define OTP_DEBUG_BLOCK0_BACKUP1_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W2_S 0 + +/** OTP_DEBUG_BLK0_BACKUP1_W3_REG register + * Otp debuger block0 data register4. + */ +#define OTP_DEBUG_BLK0_BACKUP1_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xc) +/** OTP_DEBUG_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word3 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP1_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W3_M (OTP_DEBUG_BLOCK0_BACKUP1_W3_V << OTP_DEBUG_BLOCK0_BACKUP1_W3_S) +#define OTP_DEBUG_BLOCK0_BACKUP1_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W3_S 0 + +/** OTP_DEBUG_BLK0_BACKUP1_W4_REG register + * Otp debuger block0 data register5. + */ +#define OTP_DEBUG_BLK0_BACKUP1_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x10) +/** OTP_DEBUG_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word4 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP1_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W4_M (OTP_DEBUG_BLOCK0_BACKUP1_W4_V << OTP_DEBUG_BLOCK0_BACKUP1_W4_S) +#define OTP_DEBUG_BLOCK0_BACKUP1_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W4_S 0 + +/** OTP_DEBUG_BLK0_BACKUP1_W5_REG register + * Otp debuger block0 data register6. + */ +#define OTP_DEBUG_BLK0_BACKUP1_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x14) +/** OTP_DEBUG_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word5 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP1_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W5_M (OTP_DEBUG_BLOCK0_BACKUP1_W5_V << OTP_DEBUG_BLOCK0_BACKUP1_W5_S) +#define OTP_DEBUG_BLOCK0_BACKUP1_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W5_S 0 + +/** OTP_DEBUG_BLK0_BACKUP2_W1_REG register + * Otp debuger block0 data register7. + */ +#define OTP_DEBUG_BLK0_BACKUP2_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x18) +/** OTP_DEBUG_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word1 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP2_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W1_M (OTP_DEBUG_BLOCK0_BACKUP2_W1_V << OTP_DEBUG_BLOCK0_BACKUP2_W1_S) +#define OTP_DEBUG_BLOCK0_BACKUP2_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W1_S 0 + +/** OTP_DEBUG_BLK0_BACKUP2_W2_REG register + * Otp debuger block0 data register8. + */ +#define OTP_DEBUG_BLK0_BACKUP2_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1c) +/** OTP_DEBUG_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word2 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP2_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W2_M (OTP_DEBUG_BLOCK0_BACKUP2_W2_V << OTP_DEBUG_BLOCK0_BACKUP2_W2_S) +#define OTP_DEBUG_BLOCK0_BACKUP2_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W2_S 0 + +/** OTP_DEBUG_BLK0_BACKUP2_W3_REG register + * Otp debuger block0 data register9. + */ +#define OTP_DEBUG_BLK0_BACKUP2_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x20) +/** OTP_DEBUG_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word3 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP2_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W3_M (OTP_DEBUG_BLOCK0_BACKUP2_W3_V << OTP_DEBUG_BLOCK0_BACKUP2_W3_S) +#define OTP_DEBUG_BLOCK0_BACKUP2_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W3_S 0 + +/** OTP_DEBUG_BLK0_BACKUP2_W4_REG register + * Otp debuger block0 data register10. + */ +#define OTP_DEBUG_BLK0_BACKUP2_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x24) +/** OTP_DEBUG_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word4 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP2_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W4_M (OTP_DEBUG_BLOCK0_BACKUP2_W4_V << OTP_DEBUG_BLOCK0_BACKUP2_W4_S) +#define OTP_DEBUG_BLOCK0_BACKUP2_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W4_S 0 + +/** OTP_DEBUG_BLK0_BACKUP2_W5_REG register + * Otp debuger block0 data register11. + */ +#define OTP_DEBUG_BLK0_BACKUP2_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x28) +/** OTP_DEBUG_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word5 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP2_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W5_M (OTP_DEBUG_BLOCK0_BACKUP2_W5_V << OTP_DEBUG_BLOCK0_BACKUP2_W5_S) +#define OTP_DEBUG_BLOCK0_BACKUP2_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W5_S 0 + +/** OTP_DEBUG_BLK0_BACKUP3_W1_REG register + * Otp debuger block0 data register12. + */ +#define OTP_DEBUG_BLK0_BACKUP3_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x2c) +/** OTP_DEBUG_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word1 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP3_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W1_M (OTP_DEBUG_BLOCK0_BACKUP3_W1_V << OTP_DEBUG_BLOCK0_BACKUP3_W1_S) +#define OTP_DEBUG_BLOCK0_BACKUP3_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W1_S 0 + +/** OTP_DEBUG_BLK0_BACKUP3_W2_REG register + * Otp debuger block0 data register13. + */ +#define OTP_DEBUG_BLK0_BACKUP3_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x30) +/** OTP_DEBUG_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word2 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP3_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W2_M (OTP_DEBUG_BLOCK0_BACKUP3_W2_V << OTP_DEBUG_BLOCK0_BACKUP3_W2_S) +#define OTP_DEBUG_BLOCK0_BACKUP3_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W2_S 0 + +/** OTP_DEBUG_BLK0_BACKUP3_W3_REG register + * Otp debuger block0 data register14. + */ +#define OTP_DEBUG_BLK0_BACKUP3_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x34) +/** OTP_DEBUG_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word3 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP3_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W3_M (OTP_DEBUG_BLOCK0_BACKUP3_W3_V << OTP_DEBUG_BLOCK0_BACKUP3_W3_S) +#define OTP_DEBUG_BLOCK0_BACKUP3_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W3_S 0 + +/** OTP_DEBUG_BLK0_BACKUP3_W4_REG register + * Otp debuger block0 data register15. + */ +#define OTP_DEBUG_BLK0_BACKUP3_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x38) +/** OTP_DEBUG_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word4 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP3_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W4_M (OTP_DEBUG_BLOCK0_BACKUP3_W4_V << OTP_DEBUG_BLOCK0_BACKUP3_W4_S) +#define OTP_DEBUG_BLOCK0_BACKUP3_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W4_S 0 + +/** OTP_DEBUG_BLK0_BACKUP3_W5_REG register + * Otp debuger block0 data register16. + */ +#define OTP_DEBUG_BLK0_BACKUP3_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x3c) +/** OTP_DEBUG_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word5 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP3_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W5_M (OTP_DEBUG_BLOCK0_BACKUP3_W5_V << OTP_DEBUG_BLOCK0_BACKUP3_W5_S) +#define OTP_DEBUG_BLOCK0_BACKUP3_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W5_S 0 + +/** OTP_DEBUG_BLK0_BACKUP4_W1_REG register + * Otp debuger block0 data register17. + */ +#define OTP_DEBUG_BLK0_BACKUP4_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x40) +/** OTP_DEBUG_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word1 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP4_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W1_M (OTP_DEBUG_BLOCK0_BACKUP4_W1_V << OTP_DEBUG_BLOCK0_BACKUP4_W1_S) +#define OTP_DEBUG_BLOCK0_BACKUP4_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W1_S 0 + +/** OTP_DEBUG_BLK0_BACKUP4_W2_REG register + * Otp debuger block0 data register18. + */ +#define OTP_DEBUG_BLK0_BACKUP4_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x44) +/** OTP_DEBUG_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word2 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP4_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W2_M (OTP_DEBUG_BLOCK0_BACKUP4_W2_V << OTP_DEBUG_BLOCK0_BACKUP4_W2_S) +#define OTP_DEBUG_BLOCK0_BACKUP4_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W2_S 0 + +/** OTP_DEBUG_BLK0_BACKUP4_W3_REG register + * Otp debuger block0 data register19. + */ +#define OTP_DEBUG_BLK0_BACKUP4_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x48) +/** OTP_DEBUG_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word3 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP4_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W3_M (OTP_DEBUG_BLOCK0_BACKUP4_W3_V << OTP_DEBUG_BLOCK0_BACKUP4_W3_S) +#define OTP_DEBUG_BLOCK0_BACKUP4_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W3_S 0 + +/** OTP_DEBUG_BLK0_BACKUP4_W4_REG register + * Otp debuger block0 data register20. + */ +#define OTP_DEBUG_BLK0_BACKUP4_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x4c) +/** OTP_DEBUG_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word4 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP4_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W4_M (OTP_DEBUG_BLOCK0_BACKUP4_W4_V << OTP_DEBUG_BLOCK0_BACKUP4_W4_S) +#define OTP_DEBUG_BLOCK0_BACKUP4_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W4_S 0 + +/** OTP_DEBUG_BLK0_BACKUP4_W5_REG register + * Otp debuger block0 data register21. + */ +#define OTP_DEBUG_BLK0_BACKUP4_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x50) +/** OTP_DEBUG_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word5 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP4_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W5_M (OTP_DEBUG_BLOCK0_BACKUP4_W5_V << OTP_DEBUG_BLOCK0_BACKUP4_W5_S) +#define OTP_DEBUG_BLOCK0_BACKUP4_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W5_S 0 + +/** OTP_DEBUG_BLK1_W1_REG register + * Otp debuger block1 data register1. + */ +#define OTP_DEBUG_BLK1_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x54) +/** OTP_DEBUG_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word1 data. + */ +#define OTP_DEBUG_BLOCK1_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W1_M (OTP_DEBUG_BLOCK1_W1_V << OTP_DEBUG_BLOCK1_W1_S) +#define OTP_DEBUG_BLOCK1_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W1_S 0 + +/** OTP_DEBUG_BLK1_W2_REG register + * Otp debuger block1 data register2. + */ +#define OTP_DEBUG_BLK1_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x58) +/** OTP_DEBUG_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word2 data. + */ +#define OTP_DEBUG_BLOCK1_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W2_M (OTP_DEBUG_BLOCK1_W2_V << OTP_DEBUG_BLOCK1_W2_S) +#define OTP_DEBUG_BLOCK1_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W2_S 0 + +/** OTP_DEBUG_BLK1_W3_REG register + * Otp debuger block1 data register3. + */ +#define OTP_DEBUG_BLK1_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x5c) +/** OTP_DEBUG_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word3 data. + */ +#define OTP_DEBUG_BLOCK1_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W3_M (OTP_DEBUG_BLOCK1_W3_V << OTP_DEBUG_BLOCK1_W3_S) +#define OTP_DEBUG_BLOCK1_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W3_S 0 + +/** OTP_DEBUG_BLK1_W4_REG register + * Otp debuger block1 data register4. + */ +#define OTP_DEBUG_BLK1_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x60) +/** OTP_DEBUG_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word4 data. + */ +#define OTP_DEBUG_BLOCK1_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W4_M (OTP_DEBUG_BLOCK1_W4_V << OTP_DEBUG_BLOCK1_W4_S) +#define OTP_DEBUG_BLOCK1_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W4_S 0 + +/** OTP_DEBUG_BLK1_W5_REG register + * Otp debuger block1 data register5. + */ +#define OTP_DEBUG_BLK1_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x64) +/** OTP_DEBUG_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word5 data. + */ +#define OTP_DEBUG_BLOCK1_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W5_M (OTP_DEBUG_BLOCK1_W5_V << OTP_DEBUG_BLOCK1_W5_S) +#define OTP_DEBUG_BLOCK1_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W5_S 0 + +/** OTP_DEBUG_BLK1_W6_REG register + * Otp debuger block1 data register6. + */ +#define OTP_DEBUG_BLK1_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x68) +/** OTP_DEBUG_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word6 data. + */ +#define OTP_DEBUG_BLOCK1_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W6_M (OTP_DEBUG_BLOCK1_W6_V << OTP_DEBUG_BLOCK1_W6_S) +#define OTP_DEBUG_BLOCK1_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W6_S 0 + +/** OTP_DEBUG_BLK1_W7_REG register + * Otp debuger block1 data register7. + */ +#define OTP_DEBUG_BLK1_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x6c) +/** OTP_DEBUG_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word7 data. + */ +#define OTP_DEBUG_BLOCK1_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W7_M (OTP_DEBUG_BLOCK1_W7_V << OTP_DEBUG_BLOCK1_W7_S) +#define OTP_DEBUG_BLOCK1_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W7_S 0 + +/** OTP_DEBUG_BLK1_W8_REG register + * Otp debuger block1 data register8. + */ +#define OTP_DEBUG_BLK1_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x70) +/** OTP_DEBUG_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word8 data. + */ +#define OTP_DEBUG_BLOCK1_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W8_M (OTP_DEBUG_BLOCK1_W8_V << OTP_DEBUG_BLOCK1_W8_S) +#define OTP_DEBUG_BLOCK1_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W8_S 0 + +/** OTP_DEBUG_BLK1_W9_REG register + * Otp debuger block1 data register9. + */ +#define OTP_DEBUG_BLK1_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x74) +/** OTP_DEBUG_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word9 data. + */ +#define OTP_DEBUG_BLOCK1_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W9_M (OTP_DEBUG_BLOCK1_W9_V << OTP_DEBUG_BLOCK1_W9_S) +#define OTP_DEBUG_BLOCK1_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W9_S 0 + +/** OTP_DEBUG_BLK2_W1_REG register + * Otp debuger block2 data register1. + */ +#define OTP_DEBUG_BLK2_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x78) +/** OTP_DEBUG_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word1 data. + */ +#define OTP_DEBUG_BLOCK2_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W1_M (OTP_DEBUG_BLOCK2_W1_V << OTP_DEBUG_BLOCK2_W1_S) +#define OTP_DEBUG_BLOCK2_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W1_S 0 + +/** OTP_DEBUG_BLK2_W2_REG register + * Otp debuger block2 data register2. + */ +#define OTP_DEBUG_BLK2_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x7c) +/** OTP_DEBUG_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word2 data. + */ +#define OTP_DEBUG_BLOCK2_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W2_M (OTP_DEBUG_BLOCK2_W2_V << OTP_DEBUG_BLOCK2_W2_S) +#define OTP_DEBUG_BLOCK2_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W2_S 0 + +/** OTP_DEBUG_BLK2_W3_REG register + * Otp debuger block2 data register3. + */ +#define OTP_DEBUG_BLK2_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x80) +/** OTP_DEBUG_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word3 data. + */ +#define OTP_DEBUG_BLOCK2_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W3_M (OTP_DEBUG_BLOCK2_W3_V << OTP_DEBUG_BLOCK2_W3_S) +#define OTP_DEBUG_BLOCK2_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W3_S 0 + +/** OTP_DEBUG_BLK2_W4_REG register + * Otp debuger block2 data register4. + */ +#define OTP_DEBUG_BLK2_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x84) +/** OTP_DEBUG_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word4 data. + */ +#define OTP_DEBUG_BLOCK2_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W4_M (OTP_DEBUG_BLOCK2_W4_V << OTP_DEBUG_BLOCK2_W4_S) +#define OTP_DEBUG_BLOCK2_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W4_S 0 + +/** OTP_DEBUG_BLK2_W5_REG register + * Otp debuger block2 data register5. + */ +#define OTP_DEBUG_BLK2_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x88) +/** OTP_DEBUG_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word5 data. + */ +#define OTP_DEBUG_BLOCK2_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W5_M (OTP_DEBUG_BLOCK2_W5_V << OTP_DEBUG_BLOCK2_W5_S) +#define OTP_DEBUG_BLOCK2_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W5_S 0 + +/** OTP_DEBUG_BLK2_W6_REG register + * Otp debuger block2 data register6. + */ +#define OTP_DEBUG_BLK2_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x8c) +/** OTP_DEBUG_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word6 data. + */ +#define OTP_DEBUG_BLOCK2_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W6_M (OTP_DEBUG_BLOCK2_W6_V << OTP_DEBUG_BLOCK2_W6_S) +#define OTP_DEBUG_BLOCK2_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W6_S 0 + +/** OTP_DEBUG_BLK2_W7_REG register + * Otp debuger block2 data register7. + */ +#define OTP_DEBUG_BLK2_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x90) +/** OTP_DEBUG_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word7 data. + */ +#define OTP_DEBUG_BLOCK2_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W7_M (OTP_DEBUG_BLOCK2_W7_V << OTP_DEBUG_BLOCK2_W7_S) +#define OTP_DEBUG_BLOCK2_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W7_S 0 + +/** OTP_DEBUG_BLK2_W8_REG register + * Otp debuger block2 data register8. + */ +#define OTP_DEBUG_BLK2_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x94) +/** OTP_DEBUG_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word8 data. + */ +#define OTP_DEBUG_BLOCK2_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W8_M (OTP_DEBUG_BLOCK2_W8_V << OTP_DEBUG_BLOCK2_W8_S) +#define OTP_DEBUG_BLOCK2_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W8_S 0 + +/** OTP_DEBUG_BLK2_W9_REG register + * Otp debuger block2 data register9. + */ +#define OTP_DEBUG_BLK2_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x98) +/** OTP_DEBUG_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word9 data. + */ +#define OTP_DEBUG_BLOCK2_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W9_M (OTP_DEBUG_BLOCK2_W9_V << OTP_DEBUG_BLOCK2_W9_S) +#define OTP_DEBUG_BLOCK2_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W9_S 0 + +/** OTP_DEBUG_BLK2_W10_REG register + * Otp debuger block2 data register10. + */ +#define OTP_DEBUG_BLK2_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x9c) +/** OTP_DEBUG_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word10 data. + */ +#define OTP_DEBUG_BLOCK2_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W10_M (OTP_DEBUG_BLOCK2_W10_V << OTP_DEBUG_BLOCK2_W10_S) +#define OTP_DEBUG_BLOCK2_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W10_S 0 + +/** OTP_DEBUG_BLK2_W11_REG register + * Otp debuger block2 data register11. + */ +#define OTP_DEBUG_BLK2_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xa0) +/** OTP_DEBUG_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word11 data. + */ +#define OTP_DEBUG_BLOCK2_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W11_M (OTP_DEBUG_BLOCK2_W11_V << OTP_DEBUG_BLOCK2_W11_S) +#define OTP_DEBUG_BLOCK2_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W11_S 0 + +/** OTP_DEBUG_BLK3_W1_REG register + * Otp debuger block3 data register1. + */ +#define OTP_DEBUG_BLK3_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xa4) +/** OTP_DEBUG_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word1 data. + */ +#define OTP_DEBUG_BLOCK3_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W1_M (OTP_DEBUG_BLOCK3_W1_V << OTP_DEBUG_BLOCK3_W1_S) +#define OTP_DEBUG_BLOCK3_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W1_S 0 + +/** OTP_DEBUG_BLK3_W2_REG register + * Otp debuger block3 data register2. + */ +#define OTP_DEBUG_BLK3_W2_REG (DR_REG_OTP_DEBUG_BASE + 0xa8) +/** OTP_DEBUG_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word2 data. + */ +#define OTP_DEBUG_BLOCK3_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W2_M (OTP_DEBUG_BLOCK3_W2_V << OTP_DEBUG_BLOCK3_W2_S) +#define OTP_DEBUG_BLOCK3_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W2_S 0 + +/** OTP_DEBUG_BLK3_W3_REG register + * Otp debuger block3 data register3. + */ +#define OTP_DEBUG_BLK3_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xac) +/** OTP_DEBUG_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word3 data. + */ +#define OTP_DEBUG_BLOCK3_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W3_M (OTP_DEBUG_BLOCK3_W3_V << OTP_DEBUG_BLOCK3_W3_S) +#define OTP_DEBUG_BLOCK3_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W3_S 0 + +/** OTP_DEBUG_BLK3_W4_REG register + * Otp debuger block3 data register4. + */ +#define OTP_DEBUG_BLK3_W4_REG (DR_REG_OTP_DEBUG_BASE + 0xb0) +/** OTP_DEBUG_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word4 data. + */ +#define OTP_DEBUG_BLOCK3_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W4_M (OTP_DEBUG_BLOCK3_W4_V << OTP_DEBUG_BLOCK3_W4_S) +#define OTP_DEBUG_BLOCK3_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W4_S 0 + +/** OTP_DEBUG_BLK3_W5_REG register + * Otp debuger block3 data register5. + */ +#define OTP_DEBUG_BLK3_W5_REG (DR_REG_OTP_DEBUG_BASE + 0xb4) +/** OTP_DEBUG_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word5 data. + */ +#define OTP_DEBUG_BLOCK3_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W5_M (OTP_DEBUG_BLOCK3_W5_V << OTP_DEBUG_BLOCK3_W5_S) +#define OTP_DEBUG_BLOCK3_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W5_S 0 + +/** OTP_DEBUG_BLK3_W6_REG register + * Otp debuger block3 data register6. + */ +#define OTP_DEBUG_BLK3_W6_REG (DR_REG_OTP_DEBUG_BASE + 0xb8) +/** OTP_DEBUG_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word6 data. + */ +#define OTP_DEBUG_BLOCK3_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W6_M (OTP_DEBUG_BLOCK3_W6_V << OTP_DEBUG_BLOCK3_W6_S) +#define OTP_DEBUG_BLOCK3_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W6_S 0 + +/** OTP_DEBUG_BLK3_W7_REG register + * Otp debuger block3 data register7. + */ +#define OTP_DEBUG_BLK3_W7_REG (DR_REG_OTP_DEBUG_BASE + 0xbc) +/** OTP_DEBUG_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word7 data. + */ +#define OTP_DEBUG_BLOCK3_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W7_M (OTP_DEBUG_BLOCK3_W7_V << OTP_DEBUG_BLOCK3_W7_S) +#define OTP_DEBUG_BLOCK3_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W7_S 0 + +/** OTP_DEBUG_BLK3_W8_REG register + * Otp debuger block3 data register8. + */ +#define OTP_DEBUG_BLK3_W8_REG (DR_REG_OTP_DEBUG_BASE + 0xc0) +/** OTP_DEBUG_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word8 data. + */ +#define OTP_DEBUG_BLOCK3_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W8_M (OTP_DEBUG_BLOCK3_W8_V << OTP_DEBUG_BLOCK3_W8_S) +#define OTP_DEBUG_BLOCK3_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W8_S 0 + +/** OTP_DEBUG_BLK3_W9_REG register + * Otp debuger block3 data register9. + */ +#define OTP_DEBUG_BLK3_W9_REG (DR_REG_OTP_DEBUG_BASE + 0xc4) +/** OTP_DEBUG_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word9 data. + */ +#define OTP_DEBUG_BLOCK3_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W9_M (OTP_DEBUG_BLOCK3_W9_V << OTP_DEBUG_BLOCK3_W9_S) +#define OTP_DEBUG_BLOCK3_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W9_S 0 + +/** OTP_DEBUG_BLK3_W10_REG register + * Otp debuger block3 data register10. + */ +#define OTP_DEBUG_BLK3_W10_REG (DR_REG_OTP_DEBUG_BASE + 0xc8) +/** OTP_DEBUG_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word10 data. + */ +#define OTP_DEBUG_BLOCK3_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W10_M (OTP_DEBUG_BLOCK3_W10_V << OTP_DEBUG_BLOCK3_W10_S) +#define OTP_DEBUG_BLOCK3_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W10_S 0 + +/** OTP_DEBUG_BLK3_W11_REG register + * Otp debuger block3 data register11. + */ +#define OTP_DEBUG_BLK3_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xcc) +/** OTP_DEBUG_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word11 data. + */ +#define OTP_DEBUG_BLOCK3_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W11_M (OTP_DEBUG_BLOCK3_W11_V << OTP_DEBUG_BLOCK3_W11_S) +#define OTP_DEBUG_BLOCK3_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W11_S 0 + +/** OTP_DEBUG_BLK4_W1_REG register + * Otp debuger block4 data register1. + */ +#define OTP_DEBUG_BLK4_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xd0) +/** OTP_DEBUG_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word1 data. + */ +#define OTP_DEBUG_BLOCK4_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W1_M (OTP_DEBUG_BLOCK4_W1_V << OTP_DEBUG_BLOCK4_W1_S) +#define OTP_DEBUG_BLOCK4_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W1_S 0 + +/** OTP_DEBUG_BLK4_W2_REG register + * Otp debuger block4 data register2. + */ +#define OTP_DEBUG_BLK4_W2_REG (DR_REG_OTP_DEBUG_BASE + 0xd4) +/** OTP_DEBUG_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word2 data. + */ +#define OTP_DEBUG_BLOCK4_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W2_M (OTP_DEBUG_BLOCK4_W2_V << OTP_DEBUG_BLOCK4_W2_S) +#define OTP_DEBUG_BLOCK4_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W2_S 0 + +/** OTP_DEBUG_BLK4_W3_REG register + * Otp debuger block4 data register3. + */ +#define OTP_DEBUG_BLK4_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xd8) +/** OTP_DEBUG_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word3 data. + */ +#define OTP_DEBUG_BLOCK4_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W3_M (OTP_DEBUG_BLOCK4_W3_V << OTP_DEBUG_BLOCK4_W3_S) +#define OTP_DEBUG_BLOCK4_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W3_S 0 + +/** OTP_DEBUG_BLK4_W4_REG register + * Otp debuger block4 data register4. + */ +#define OTP_DEBUG_BLK4_W4_REG (DR_REG_OTP_DEBUG_BASE + 0xdc) +/** OTP_DEBUG_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word4 data. + */ +#define OTP_DEBUG_BLOCK4_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W4_M (OTP_DEBUG_BLOCK4_W4_V << OTP_DEBUG_BLOCK4_W4_S) +#define OTP_DEBUG_BLOCK4_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W4_S 0 + +/** OTP_DEBUG_BLK4_W5_REG register + * Otp debuger block4 data register5. + */ +#define OTP_DEBUG_BLK4_W5_REG (DR_REG_OTP_DEBUG_BASE + 0xe0) +/** OTP_DEBUG_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word5 data. + */ +#define OTP_DEBUG_BLOCK4_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W5_M (OTP_DEBUG_BLOCK4_W5_V << OTP_DEBUG_BLOCK4_W5_S) +#define OTP_DEBUG_BLOCK4_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W5_S 0 + +/** OTP_DEBUG_BLK4_W6_REG register + * Otp debuger block4 data register6. + */ +#define OTP_DEBUG_BLK4_W6_REG (DR_REG_OTP_DEBUG_BASE + 0xe4) +/** OTP_DEBUG_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word6 data. + */ +#define OTP_DEBUG_BLOCK4_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W6_M (OTP_DEBUG_BLOCK4_W6_V << OTP_DEBUG_BLOCK4_W6_S) +#define OTP_DEBUG_BLOCK4_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W6_S 0 + +/** OTP_DEBUG_BLK4_W7_REG register + * Otp debuger block4 data register7. + */ +#define OTP_DEBUG_BLK4_W7_REG (DR_REG_OTP_DEBUG_BASE + 0xe8) +/** OTP_DEBUG_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word7 data. + */ +#define OTP_DEBUG_BLOCK4_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W7_M (OTP_DEBUG_BLOCK4_W7_V << OTP_DEBUG_BLOCK4_W7_S) +#define OTP_DEBUG_BLOCK4_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W7_S 0 + +/** OTP_DEBUG_BLK4_W8_REG register + * Otp debuger block4 data register8. + */ +#define OTP_DEBUG_BLK4_W8_REG (DR_REG_OTP_DEBUG_BASE + 0xec) +/** OTP_DEBUG_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word8 data. + */ +#define OTP_DEBUG_BLOCK4_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W8_M (OTP_DEBUG_BLOCK4_W8_V << OTP_DEBUG_BLOCK4_W8_S) +#define OTP_DEBUG_BLOCK4_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W8_S 0 + +/** OTP_DEBUG_BLK4_W9_REG register + * Otp debuger block4 data register9. + */ +#define OTP_DEBUG_BLK4_W9_REG (DR_REG_OTP_DEBUG_BASE + 0xf0) +/** OTP_DEBUG_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word9 data. + */ +#define OTP_DEBUG_BLOCK4_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W9_M (OTP_DEBUG_BLOCK4_W9_V << OTP_DEBUG_BLOCK4_W9_S) +#define OTP_DEBUG_BLOCK4_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W9_S 0 + +/** OTP_DEBUG_BLK4_W10_REG register + * Otp debuger block4 data registe10. + */ +#define OTP_DEBUG_BLK4_W10_REG (DR_REG_OTP_DEBUG_BASE + 0xf4) +/** OTP_DEBUG_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word10 data. + */ +#define OTP_DEBUG_BLOCK4_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W10_M (OTP_DEBUG_BLOCK4_W10_V << OTP_DEBUG_BLOCK4_W10_S) +#define OTP_DEBUG_BLOCK4_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W10_S 0 + +/** OTP_DEBUG_BLK4_W11_REG register + * Otp debuger block4 data register11. + */ +#define OTP_DEBUG_BLK4_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xf8) +/** OTP_DEBUG_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word11 data. + */ +#define OTP_DEBUG_BLOCK4_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W11_M (OTP_DEBUG_BLOCK4_W11_V << OTP_DEBUG_BLOCK4_W11_S) +#define OTP_DEBUG_BLOCK4_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W11_S 0 + +/** OTP_DEBUG_BLK5_W1_REG register + * Otp debuger block5 data register1. + */ +#define OTP_DEBUG_BLK5_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xfc) +/** OTP_DEBUG_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word1 data. + */ +#define OTP_DEBUG_BLOCK5_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W1_M (OTP_DEBUG_BLOCK5_W1_V << OTP_DEBUG_BLOCK5_W1_S) +#define OTP_DEBUG_BLOCK5_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W1_S 0 + +/** OTP_DEBUG_BLK5_W2_REG register + * Otp debuger block5 data register2. + */ +#define OTP_DEBUG_BLK5_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x100) +/** OTP_DEBUG_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word2 data. + */ +#define OTP_DEBUG_BLOCK5_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W2_M (OTP_DEBUG_BLOCK5_W2_V << OTP_DEBUG_BLOCK5_W2_S) +#define OTP_DEBUG_BLOCK5_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W2_S 0 + +/** OTP_DEBUG_BLK5_W3_REG register + * Otp debuger block5 data register3. + */ +#define OTP_DEBUG_BLK5_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x104) +/** OTP_DEBUG_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word3 data. + */ +#define OTP_DEBUG_BLOCK5_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W3_M (OTP_DEBUG_BLOCK5_W3_V << OTP_DEBUG_BLOCK5_W3_S) +#define OTP_DEBUG_BLOCK5_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W3_S 0 + +/** OTP_DEBUG_BLK5_W4_REG register + * Otp debuger block5 data register4. + */ +#define OTP_DEBUG_BLK5_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x108) +/** OTP_DEBUG_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word4 data. + */ +#define OTP_DEBUG_BLOCK5_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W4_M (OTP_DEBUG_BLOCK5_W4_V << OTP_DEBUG_BLOCK5_W4_S) +#define OTP_DEBUG_BLOCK5_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W4_S 0 + +/** OTP_DEBUG_BLK5_W5_REG register + * Otp debuger block5 data register5. + */ +#define OTP_DEBUG_BLK5_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x10c) +/** OTP_DEBUG_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word5 data. + */ +#define OTP_DEBUG_BLOCK5_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W5_M (OTP_DEBUG_BLOCK5_W5_V << OTP_DEBUG_BLOCK5_W5_S) +#define OTP_DEBUG_BLOCK5_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W5_S 0 + +/** OTP_DEBUG_BLK5_W6_REG register + * Otp debuger block5 data register6. + */ +#define OTP_DEBUG_BLK5_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x110) +/** OTP_DEBUG_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word6 data. + */ +#define OTP_DEBUG_BLOCK5_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W6_M (OTP_DEBUG_BLOCK5_W6_V << OTP_DEBUG_BLOCK5_W6_S) +#define OTP_DEBUG_BLOCK5_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W6_S 0 + +/** OTP_DEBUG_BLK5_W7_REG register + * Otp debuger block5 data register7. + */ +#define OTP_DEBUG_BLK5_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x114) +/** OTP_DEBUG_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word7 data. + */ +#define OTP_DEBUG_BLOCK5_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W7_M (OTP_DEBUG_BLOCK5_W7_V << OTP_DEBUG_BLOCK5_W7_S) +#define OTP_DEBUG_BLOCK5_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W7_S 0 + +/** OTP_DEBUG_BLK5_W8_REG register + * Otp debuger block5 data register8. + */ +#define OTP_DEBUG_BLK5_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x118) +/** OTP_DEBUG_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word8 data. + */ +#define OTP_DEBUG_BLOCK5_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W8_M (OTP_DEBUG_BLOCK5_W8_V << OTP_DEBUG_BLOCK5_W8_S) +#define OTP_DEBUG_BLOCK5_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W8_S 0 + +/** OTP_DEBUG_BLK5_W9_REG register + * Otp debuger block5 data register9. + */ +#define OTP_DEBUG_BLK5_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x11c) +/** OTP_DEBUG_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word9 data. + */ +#define OTP_DEBUG_BLOCK5_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W9_M (OTP_DEBUG_BLOCK5_W9_V << OTP_DEBUG_BLOCK5_W9_S) +#define OTP_DEBUG_BLOCK5_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W9_S 0 + +/** OTP_DEBUG_BLK5_W10_REG register + * Otp debuger block5 data register10. + */ +#define OTP_DEBUG_BLK5_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x120) +/** OTP_DEBUG_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word10 data. + */ +#define OTP_DEBUG_BLOCK5_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W10_M (OTP_DEBUG_BLOCK5_W10_V << OTP_DEBUG_BLOCK5_W10_S) +#define OTP_DEBUG_BLOCK5_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W10_S 0 + +/** OTP_DEBUG_BLK5_W11_REG register + * Otp debuger block5 data register11. + */ +#define OTP_DEBUG_BLK5_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x124) +/** OTP_DEBUG_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word11 data. + */ +#define OTP_DEBUG_BLOCK5_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W11_M (OTP_DEBUG_BLOCK5_W11_V << OTP_DEBUG_BLOCK5_W11_S) +#define OTP_DEBUG_BLOCK5_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W11_S 0 + +/** OTP_DEBUG_BLK6_W1_REG register + * Otp debuger block6 data register1. + */ +#define OTP_DEBUG_BLK6_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x128) +/** OTP_DEBUG_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word1 data. + */ +#define OTP_DEBUG_BLOCK6_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W1_M (OTP_DEBUG_BLOCK6_W1_V << OTP_DEBUG_BLOCK6_W1_S) +#define OTP_DEBUG_BLOCK6_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W1_S 0 + +/** OTP_DEBUG_BLK6_W2_REG register + * Otp debuger block6 data register2. + */ +#define OTP_DEBUG_BLK6_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x12c) +/** OTP_DEBUG_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word2 data. + */ +#define OTP_DEBUG_BLOCK6_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W2_M (OTP_DEBUG_BLOCK6_W2_V << OTP_DEBUG_BLOCK6_W2_S) +#define OTP_DEBUG_BLOCK6_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W2_S 0 + +/** OTP_DEBUG_BLK6_W3_REG register + * Otp debuger block6 data register3. + */ +#define OTP_DEBUG_BLK6_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x130) +/** OTP_DEBUG_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word3 data. + */ +#define OTP_DEBUG_BLOCK6_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W3_M (OTP_DEBUG_BLOCK6_W3_V << OTP_DEBUG_BLOCK6_W3_S) +#define OTP_DEBUG_BLOCK6_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W3_S 0 + +/** OTP_DEBUG_BLK6_W4_REG register + * Otp debuger block6 data register4. + */ +#define OTP_DEBUG_BLK6_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x134) +/** OTP_DEBUG_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word4 data. + */ +#define OTP_DEBUG_BLOCK6_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W4_M (OTP_DEBUG_BLOCK6_W4_V << OTP_DEBUG_BLOCK6_W4_S) +#define OTP_DEBUG_BLOCK6_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W4_S 0 + +/** OTP_DEBUG_BLK6_W5_REG register + * Otp debuger block6 data register5. + */ +#define OTP_DEBUG_BLK6_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x138) +/** OTP_DEBUG_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word5 data. + */ +#define OTP_DEBUG_BLOCK6_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W5_M (OTP_DEBUG_BLOCK6_W5_V << OTP_DEBUG_BLOCK6_W5_S) +#define OTP_DEBUG_BLOCK6_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W5_S 0 + +/** OTP_DEBUG_BLK6_W6_REG register + * Otp debuger block6 data register6. + */ +#define OTP_DEBUG_BLK6_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x13c) +/** OTP_DEBUG_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word6 data. + */ +#define OTP_DEBUG_BLOCK6_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W6_M (OTP_DEBUG_BLOCK6_W6_V << OTP_DEBUG_BLOCK6_W6_S) +#define OTP_DEBUG_BLOCK6_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W6_S 0 + +/** OTP_DEBUG_BLK6_W7_REG register + * Otp debuger block6 data register7. + */ +#define OTP_DEBUG_BLK6_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x140) +/** OTP_DEBUG_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word7 data. + */ +#define OTP_DEBUG_BLOCK6_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W7_M (OTP_DEBUG_BLOCK6_W7_V << OTP_DEBUG_BLOCK6_W7_S) +#define OTP_DEBUG_BLOCK6_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W7_S 0 + +/** OTP_DEBUG_BLK6_W8_REG register + * Otp debuger block6 data register8. + */ +#define OTP_DEBUG_BLK6_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x144) +/** OTP_DEBUG_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word8 data. + */ +#define OTP_DEBUG_BLOCK6_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W8_M (OTP_DEBUG_BLOCK6_W8_V << OTP_DEBUG_BLOCK6_W8_S) +#define OTP_DEBUG_BLOCK6_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W8_S 0 + +/** OTP_DEBUG_BLK6_W9_REG register + * Otp debuger block6 data register9. + */ +#define OTP_DEBUG_BLK6_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x148) +/** OTP_DEBUG_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word9 data. + */ +#define OTP_DEBUG_BLOCK6_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W9_M (OTP_DEBUG_BLOCK6_W9_V << OTP_DEBUG_BLOCK6_W9_S) +#define OTP_DEBUG_BLOCK6_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W9_S 0 + +/** OTP_DEBUG_BLK6_W10_REG register + * Otp debuger block6 data register10. + */ +#define OTP_DEBUG_BLK6_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x14c) +/** OTP_DEBUG_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word10 data. + */ +#define OTP_DEBUG_BLOCK6_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W10_M (OTP_DEBUG_BLOCK6_W10_V << OTP_DEBUG_BLOCK6_W10_S) +#define OTP_DEBUG_BLOCK6_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W10_S 0 + +/** OTP_DEBUG_BLK6_W11_REG register + * Otp debuger block6 data register11. + */ +#define OTP_DEBUG_BLK6_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x150) +/** OTP_DEBUG_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word11 data. + */ +#define OTP_DEBUG_BLOCK6_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W11_M (OTP_DEBUG_BLOCK6_W11_V << OTP_DEBUG_BLOCK6_W11_S) +#define OTP_DEBUG_BLOCK6_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W11_S 0 + +/** OTP_DEBUG_BLK7_W1_REG register + * Otp debuger block7 data register1. + */ +#define OTP_DEBUG_BLK7_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x154) +/** OTP_DEBUG_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word1 data. + */ +#define OTP_DEBUG_BLOCK7_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W1_M (OTP_DEBUG_BLOCK7_W1_V << OTP_DEBUG_BLOCK7_W1_S) +#define OTP_DEBUG_BLOCK7_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W1_S 0 + +/** OTP_DEBUG_BLK7_W2_REG register + * Otp debuger block7 data register2. + */ +#define OTP_DEBUG_BLK7_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x158) +/** OTP_DEBUG_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word2 data. + */ +#define OTP_DEBUG_BLOCK7_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W2_M (OTP_DEBUG_BLOCK7_W2_V << OTP_DEBUG_BLOCK7_W2_S) +#define OTP_DEBUG_BLOCK7_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W2_S 0 + +/** OTP_DEBUG_BLK7_W3_REG register + * Otp debuger block7 data register3. + */ +#define OTP_DEBUG_BLK7_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x15c) +/** OTP_DEBUG_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word3 data. + */ +#define OTP_DEBUG_BLOCK7_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W3_M (OTP_DEBUG_BLOCK7_W3_V << OTP_DEBUG_BLOCK7_W3_S) +#define OTP_DEBUG_BLOCK7_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W3_S 0 + +/** OTP_DEBUG_BLK7_W4_REG register + * Otp debuger block7 data register4. + */ +#define OTP_DEBUG_BLK7_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x160) +/** OTP_DEBUG_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word4 data. + */ +#define OTP_DEBUG_BLOCK7_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W4_M (OTP_DEBUG_BLOCK7_W4_V << OTP_DEBUG_BLOCK7_W4_S) +#define OTP_DEBUG_BLOCK7_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W4_S 0 + +/** OTP_DEBUG_BLK7_W5_REG register + * Otp debuger block7 data register5. + */ +#define OTP_DEBUG_BLK7_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x164) +/** OTP_DEBUG_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word5 data. + */ +#define OTP_DEBUG_BLOCK7_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W5_M (OTP_DEBUG_BLOCK7_W5_V << OTP_DEBUG_BLOCK7_W5_S) +#define OTP_DEBUG_BLOCK7_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W5_S 0 + +/** OTP_DEBUG_BLK7_W6_REG register + * Otp debuger block7 data register6. + */ +#define OTP_DEBUG_BLK7_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x168) +/** OTP_DEBUG_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word6 data. + */ +#define OTP_DEBUG_BLOCK7_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W6_M (OTP_DEBUG_BLOCK7_W6_V << OTP_DEBUG_BLOCK7_W6_S) +#define OTP_DEBUG_BLOCK7_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W6_S 0 + +/** OTP_DEBUG_BLK7_W7_REG register + * Otp debuger block7 data register7. + */ +#define OTP_DEBUG_BLK7_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x16c) +/** OTP_DEBUG_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word7 data. + */ +#define OTP_DEBUG_BLOCK7_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W7_M (OTP_DEBUG_BLOCK7_W7_V << OTP_DEBUG_BLOCK7_W7_S) +#define OTP_DEBUG_BLOCK7_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W7_S 0 + +/** OTP_DEBUG_BLK7_W8_REG register + * Otp debuger block7 data register8. + */ +#define OTP_DEBUG_BLK7_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x170) +/** OTP_DEBUG_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word8 data. + */ +#define OTP_DEBUG_BLOCK7_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W8_M (OTP_DEBUG_BLOCK7_W8_V << OTP_DEBUG_BLOCK7_W8_S) +#define OTP_DEBUG_BLOCK7_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W8_S 0 + +/** OTP_DEBUG_BLK7_W9_REG register + * Otp debuger block7 data register9. + */ +#define OTP_DEBUG_BLK7_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x174) +/** OTP_DEBUG_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word9 data. + */ +#define OTP_DEBUG_BLOCK7_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W9_M (OTP_DEBUG_BLOCK7_W9_V << OTP_DEBUG_BLOCK7_W9_S) +#define OTP_DEBUG_BLOCK7_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W9_S 0 + +/** OTP_DEBUG_BLK7_W10_REG register + * Otp debuger block7 data register10. + */ +#define OTP_DEBUG_BLK7_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x178) +/** OTP_DEBUG_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word10 data. + */ +#define OTP_DEBUG_BLOCK7_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W10_M (OTP_DEBUG_BLOCK7_W10_V << OTP_DEBUG_BLOCK7_W10_S) +#define OTP_DEBUG_BLOCK7_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W10_S 0 + +/** OTP_DEBUG_BLK7_W11_REG register + * Otp debuger block7 data register11. + */ +#define OTP_DEBUG_BLK7_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x17c) +/** OTP_DEBUG_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word11 data. + */ +#define OTP_DEBUG_BLOCK7_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W11_M (OTP_DEBUG_BLOCK7_W11_V << OTP_DEBUG_BLOCK7_W11_S) +#define OTP_DEBUG_BLOCK7_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W11_S 0 + +/** OTP_DEBUG_BLK8_W1_REG register + * Otp debuger block8 data register1. + */ +#define OTP_DEBUG_BLK8_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x180) +/** OTP_DEBUG_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word1 data. + */ +#define OTP_DEBUG_BLOCK8_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W1_M (OTP_DEBUG_BLOCK8_W1_V << OTP_DEBUG_BLOCK8_W1_S) +#define OTP_DEBUG_BLOCK8_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W1_S 0 + +/** OTP_DEBUG_BLK8_W2_REG register + * Otp debuger block8 data register2. + */ +#define OTP_DEBUG_BLK8_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x184) +/** OTP_DEBUG_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word2 data. + */ +#define OTP_DEBUG_BLOCK8_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W2_M (OTP_DEBUG_BLOCK8_W2_V << OTP_DEBUG_BLOCK8_W2_S) +#define OTP_DEBUG_BLOCK8_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W2_S 0 + +/** OTP_DEBUG_BLK8_W3_REG register + * Otp debuger block8 data register3. + */ +#define OTP_DEBUG_BLK8_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x188) +/** OTP_DEBUG_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word3 data. + */ +#define OTP_DEBUG_BLOCK8_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W3_M (OTP_DEBUG_BLOCK8_W3_V << OTP_DEBUG_BLOCK8_W3_S) +#define OTP_DEBUG_BLOCK8_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W3_S 0 + +/** OTP_DEBUG_BLK8_W4_REG register + * Otp debuger block8 data register4. + */ +#define OTP_DEBUG_BLK8_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x18c) +/** OTP_DEBUG_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word4 data. + */ +#define OTP_DEBUG_BLOCK8_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W4_M (OTP_DEBUG_BLOCK8_W4_V << OTP_DEBUG_BLOCK8_W4_S) +#define OTP_DEBUG_BLOCK8_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W4_S 0 + +/** OTP_DEBUG_BLK8_W5_REG register + * Otp debuger block8 data register5. + */ +#define OTP_DEBUG_BLK8_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x190) +/** OTP_DEBUG_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word5 data. + */ +#define OTP_DEBUG_BLOCK8_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W5_M (OTP_DEBUG_BLOCK8_W5_V << OTP_DEBUG_BLOCK8_W5_S) +#define OTP_DEBUG_BLOCK8_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W5_S 0 + +/** OTP_DEBUG_BLK8_W6_REG register + * Otp debuger block8 data register6. + */ +#define OTP_DEBUG_BLK8_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x194) +/** OTP_DEBUG_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word6 data. + */ +#define OTP_DEBUG_BLOCK8_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W6_M (OTP_DEBUG_BLOCK8_W6_V << OTP_DEBUG_BLOCK8_W6_S) +#define OTP_DEBUG_BLOCK8_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W6_S 0 + +/** OTP_DEBUG_BLK8_W7_REG register + * Otp debuger block8 data register7. + */ +#define OTP_DEBUG_BLK8_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x198) +/** OTP_DEBUG_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word7 data. + */ +#define OTP_DEBUG_BLOCK8_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W7_M (OTP_DEBUG_BLOCK8_W7_V << OTP_DEBUG_BLOCK8_W7_S) +#define OTP_DEBUG_BLOCK8_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W7_S 0 + +/** OTP_DEBUG_BLK8_W8_REG register + * Otp debuger block8 data register8. + */ +#define OTP_DEBUG_BLK8_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x19c) +/** OTP_DEBUG_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word8 data. + */ +#define OTP_DEBUG_BLOCK8_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W8_M (OTP_DEBUG_BLOCK8_W8_V << OTP_DEBUG_BLOCK8_W8_S) +#define OTP_DEBUG_BLOCK8_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W8_S 0 + +/** OTP_DEBUG_BLK8_W9_REG register + * Otp debuger block8 data register9. + */ +#define OTP_DEBUG_BLK8_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1a0) +/** OTP_DEBUG_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word9 data. + */ +#define OTP_DEBUG_BLOCK8_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W9_M (OTP_DEBUG_BLOCK8_W9_V << OTP_DEBUG_BLOCK8_W9_S) +#define OTP_DEBUG_BLOCK8_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W9_S 0 + +/** OTP_DEBUG_BLK8_W10_REG register + * Otp debuger block8 data register10. + */ +#define OTP_DEBUG_BLK8_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1a4) +/** OTP_DEBUG_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word10 data. + */ +#define OTP_DEBUG_BLOCK8_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W10_M (OTP_DEBUG_BLOCK8_W10_V << OTP_DEBUG_BLOCK8_W10_S) +#define OTP_DEBUG_BLOCK8_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W10_S 0 + +/** OTP_DEBUG_BLK8_W11_REG register + * Otp debuger block8 data register11. + */ +#define OTP_DEBUG_BLK8_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x1a8) +/** OTP_DEBUG_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word11 data. + */ +#define OTP_DEBUG_BLOCK8_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W11_M (OTP_DEBUG_BLOCK8_W11_V << OTP_DEBUG_BLOCK8_W11_S) +#define OTP_DEBUG_BLOCK8_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W11_S 0 + +/** OTP_DEBUG_BLK9_W1_REG register + * Otp debuger block9 data register1. + */ +#define OTP_DEBUG_BLK9_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x1ac) +/** OTP_DEBUG_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word1 data. + */ +#define OTP_DEBUG_BLOCK9_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W1_M (OTP_DEBUG_BLOCK9_W1_V << OTP_DEBUG_BLOCK9_W1_S) +#define OTP_DEBUG_BLOCK9_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W1_S 0 + +/** OTP_DEBUG_BLK9_W2_REG register + * Otp debuger block9 data register2. + */ +#define OTP_DEBUG_BLK9_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1b0) +/** OTP_DEBUG_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word2 data. + */ +#define OTP_DEBUG_BLOCK9_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W2_M (OTP_DEBUG_BLOCK9_W2_V << OTP_DEBUG_BLOCK9_W2_S) +#define OTP_DEBUG_BLOCK9_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W2_S 0 + +/** OTP_DEBUG_BLK9_W3_REG register + * Otp debuger block9 data register3. + */ +#define OTP_DEBUG_BLK9_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x1b4) +/** OTP_DEBUG_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word3 data. + */ +#define OTP_DEBUG_BLOCK9_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W3_M (OTP_DEBUG_BLOCK9_W3_V << OTP_DEBUG_BLOCK9_W3_S) +#define OTP_DEBUG_BLOCK9_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W3_S 0 + +/** OTP_DEBUG_BLK9_W4_REG register + * Otp debuger block9 data register4. + */ +#define OTP_DEBUG_BLK9_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x1b8) +/** OTP_DEBUG_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word4 data. + */ +#define OTP_DEBUG_BLOCK9_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W4_M (OTP_DEBUG_BLOCK9_W4_V << OTP_DEBUG_BLOCK9_W4_S) +#define OTP_DEBUG_BLOCK9_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W4_S 0 + +/** OTP_DEBUG_BLK9_W5_REG register + * Otp debuger block9 data register5. + */ +#define OTP_DEBUG_BLK9_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x1bc) +/** OTP_DEBUG_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word5 data. + */ +#define OTP_DEBUG_BLOCK9_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W5_M (OTP_DEBUG_BLOCK9_W5_V << OTP_DEBUG_BLOCK9_W5_S) +#define OTP_DEBUG_BLOCK9_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W5_S 0 + +/** OTP_DEBUG_BLK9_W6_REG register + * Otp debuger block9 data register6. + */ +#define OTP_DEBUG_BLK9_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x1c0) +/** OTP_DEBUG_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word6 data. + */ +#define OTP_DEBUG_BLOCK9_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W6_M (OTP_DEBUG_BLOCK9_W6_V << OTP_DEBUG_BLOCK9_W6_S) +#define OTP_DEBUG_BLOCK9_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W6_S 0 + +/** OTP_DEBUG_BLK9_W7_REG register + * Otp debuger block9 data register7. + */ +#define OTP_DEBUG_BLK9_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x1c4) +/** OTP_DEBUG_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word7 data. + */ +#define OTP_DEBUG_BLOCK9_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W7_M (OTP_DEBUG_BLOCK9_W7_V << OTP_DEBUG_BLOCK9_W7_S) +#define OTP_DEBUG_BLOCK9_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W7_S 0 + +/** OTP_DEBUG_BLK9_W8_REG register + * Otp debuger block9 data register8. + */ +#define OTP_DEBUG_BLK9_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x1c8) +/** OTP_DEBUG_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word8 data. + */ +#define OTP_DEBUG_BLOCK9_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W8_M (OTP_DEBUG_BLOCK9_W8_V << OTP_DEBUG_BLOCK9_W8_S) +#define OTP_DEBUG_BLOCK9_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W8_S 0 + +/** OTP_DEBUG_BLK9_W9_REG register + * Otp debuger block9 data register9. + */ +#define OTP_DEBUG_BLK9_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1cc) +/** OTP_DEBUG_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word9 data. + */ +#define OTP_DEBUG_BLOCK9_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W9_M (OTP_DEBUG_BLOCK9_W9_V << OTP_DEBUG_BLOCK9_W9_S) +#define OTP_DEBUG_BLOCK9_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W9_S 0 + +/** OTP_DEBUG_BLK9_W10_REG register + * Otp debuger block9 data register10. + */ +#define OTP_DEBUG_BLK9_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1d0) +/** OTP_DEBUG_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word10 data. + */ +#define OTP_DEBUG_BLOCK9_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W10_M (OTP_DEBUG_BLOCK9_W10_V << OTP_DEBUG_BLOCK9_W10_S) +#define OTP_DEBUG_BLOCK9_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W10_S 0 + +/** OTP_DEBUG_BLK9_W11_REG register + * Otp debuger block9 data register11. + */ +#define OTP_DEBUG_BLK9_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x1d4) +/** OTP_DEBUG_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word11 data. + */ +#define OTP_DEBUG_BLOCK9_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W11_M (OTP_DEBUG_BLOCK9_W11_V << OTP_DEBUG_BLOCK9_W11_S) +#define OTP_DEBUG_BLOCK9_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W11_S 0 + +/** OTP_DEBUG_BLK10_W1_REG register + * Otp debuger block10 data register1. + */ +#define OTP_DEBUG_BLK10_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x1d8) +/** OTP_DEBUG_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word1 data. + */ +#define OTP_DEBUG_BLOCK10_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W1_M (OTP_DEBUG_BLOCK10_W1_V << OTP_DEBUG_BLOCK10_W1_S) +#define OTP_DEBUG_BLOCK10_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W1_S 0 + +/** OTP_DEBUG_BLK10_W2_REG register + * Otp debuger block10 data register2. + */ +#define OTP_DEBUG_BLK10_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1dc) +/** OTP_DEBUG_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word2 data. + */ +#define OTP_DEBUG_BLOCK10_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W2_M (OTP_DEBUG_BLOCK10_W2_V << OTP_DEBUG_BLOCK10_W2_S) +#define OTP_DEBUG_BLOCK10_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W2_S 0 + +/** OTP_DEBUG_BLK10_W3_REG register + * Otp debuger block10 data register3. + */ +#define OTP_DEBUG_BLK10_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x1e0) +/** OTP_DEBUG_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word3 data. + */ +#define OTP_DEBUG_BLOCK10_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W3_M (OTP_DEBUG_BLOCK10_W3_V << OTP_DEBUG_BLOCK10_W3_S) +#define OTP_DEBUG_BLOCK10_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W3_S 0 + +/** OTP_DEBUG_BLK10_W4_REG register + * Otp debuger block10 data register4. + */ +#define OTP_DEBUG_BLK10_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x1e4) +/** OTP_DEBUG_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word4 data. + */ +#define OTP_DEBUG_BLOCK10_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W4_M (OTP_DEBUG_BLOCK10_W4_V << OTP_DEBUG_BLOCK10_W4_S) +#define OTP_DEBUG_BLOCK10_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W4_S 0 + +/** OTP_DEBUG_BLK10_W5_REG register + * Otp debuger block10 data register5. + */ +#define OTP_DEBUG_BLK10_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x1e8) +/** OTP_DEBUG_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word5 data. + */ +#define OTP_DEBUG_BLOCK10_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W5_M (OTP_DEBUG_BLOCK10_W5_V << OTP_DEBUG_BLOCK10_W5_S) +#define OTP_DEBUG_BLOCK10_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W5_S 0 + +/** OTP_DEBUG_BLK10_W6_REG register + * Otp debuger block10 data register6. + */ +#define OTP_DEBUG_BLK10_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x1ec) +/** OTP_DEBUG_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word6 data. + */ +#define OTP_DEBUG_BLOCK10_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W6_M (OTP_DEBUG_BLOCK10_W6_V << OTP_DEBUG_BLOCK10_W6_S) +#define OTP_DEBUG_BLOCK10_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W6_S 0 + +/** OTP_DEBUG_BLK10_W7_REG register + * Otp debuger block10 data register7. + */ +#define OTP_DEBUG_BLK10_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x1f0) +/** OTP_DEBUG_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word7 data. + */ +#define OTP_DEBUG_BLOCK10_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W7_M (OTP_DEBUG_BLOCK10_W7_V << OTP_DEBUG_BLOCK10_W7_S) +#define OTP_DEBUG_BLOCK10_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W7_S 0 + +/** OTP_DEBUG_BLK10_W8_REG register + * Otp debuger block10 data register8. + */ +#define OTP_DEBUG_BLK10_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x1f4) +/** OTP_DEBUG_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word8 data. + */ +#define OTP_DEBUG_BLOCK10_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W8_M (OTP_DEBUG_BLOCK10_W8_V << OTP_DEBUG_BLOCK10_W8_S) +#define OTP_DEBUG_BLOCK10_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W8_S 0 + +/** OTP_DEBUG_BLK10_W9_REG register + * Otp debuger block10 data register9. + */ +#define OTP_DEBUG_BLK10_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1f8) +/** OTP_DEBUG_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word9 data. + */ +#define OTP_DEBUG_BLOCK10_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W9_M (OTP_DEBUG_BLOCK10_W9_V << OTP_DEBUG_BLOCK10_W9_S) +#define OTP_DEBUG_BLOCK10_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W9_S 0 + +/** OTP_DEBUG_BLK10_W10_REG register + * Otp debuger block10 data register10. + */ +#define OTP_DEBUG_BLK10_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1fc) +/** OTP_DEBUG_BLOCK19_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word10 data. + */ +#define OTP_DEBUG_BLOCK19_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK19_W10_M (OTP_DEBUG_BLOCK19_W10_V << OTP_DEBUG_BLOCK19_W10_S) +#define OTP_DEBUG_BLOCK19_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK19_W10_S 0 + +/** OTP_DEBUG_BLK10_W11_REG register + * Otp debuger block10 data register11. + */ +#define OTP_DEBUG_BLK10_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x200) +/** OTP_DEBUG_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word11 data. + */ +#define OTP_DEBUG_BLOCK10_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W11_M (OTP_DEBUG_BLOCK10_W11_V << OTP_DEBUG_BLOCK10_W11_S) +#define OTP_DEBUG_BLOCK10_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W11_S 0 + +/** OTP_DEBUG_CLK_REG register + * Otp debuger clk_en configuration register. + */ +#define OTP_DEBUG_CLK_REG (DR_REG_OTP_DEBUG_BASE + 0x204) +/** OTP_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 0; + * Force clock on for this register file. + */ +#define OTP_DEBUG_CLK_EN (BIT(0)) +#define OTP_DEBUG_CLK_EN_M (OTP_DEBUG_CLK_EN_V << OTP_DEBUG_CLK_EN_S) +#define OTP_DEBUG_CLK_EN_V 0x00000001U +#define OTP_DEBUG_CLK_EN_S 0 + +/** OTP_DEBUG_APB2OTP_EN_REG register + * Otp_debuger apb2otp enable configuration register. + */ +#define OTP_DEBUG_APB2OTP_EN_REG (DR_REG_OTP_DEBUG_BASE + 0x208) +/** OTP_DEBUG_APB2OTP_EN : R/W; bitpos: [0]; default: 0; + * Debug mode enable signal. + */ +#define OTP_DEBUG_APB2OTP_EN (BIT(0)) +#define OTP_DEBUG_APB2OTP_EN_M (OTP_DEBUG_APB2OTP_EN_V << OTP_DEBUG_APB2OTP_EN_S) +#define OTP_DEBUG_APB2OTP_EN_V 0x00000001U +#define OTP_DEBUG_APB2OTP_EN_S 0 + +/** OTP_DEBUG_DATE_REG register + * eFuse version register. + */ +#define OTP_DEBUG_DATE_REG (DR_REG_OTP_DEBUG_BASE + 0x20c) +/** OTP_DEBUG_DATE : R/W; bitpos: [27:0]; default: 539037736; + * Stores otp_debug version. + */ +#define OTP_DEBUG_DATE 0x0FFFFFFFU +#define OTP_DEBUG_DATE_M (OTP_DEBUG_DATE_V << OTP_DEBUG_DATE_S) +#define OTP_DEBUG_DATE_V 0x0FFFFFFFU +#define OTP_DEBUG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/otp_debug_struct.h b/components/soc/esp32c6/include/soc/otp_debug_struct.h new file mode 100644 index 0000000000..5b0737475f --- /dev/null +++ b/components/soc/esp32c6/include/soc/otp_debug_struct.h @@ -0,0 +1,2137 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: OTP_DEBUG Block0 Write Disable Data */ +/** Type of wr_dis register + * Otp debuger block0 data register1. + */ +typedef union { + struct { + /** block0_wr_dis : RO; bitpos: [31:0]; default: 0; + * Otp block0 write disable data. + */ + uint32_t block0_wr_dis:32; + }; + uint32_t val; +} otp_debug_wr_dis_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup1 Word1 Data */ +/** Type of blk0_backup1_w1 register + * Otp debuger block0 data register2. + */ +typedef union { + struct { + /** block0_backup1_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word1 data. + */ + uint32_t block0_backup1_w1:32; + }; + uint32_t val; +} otp_debug_blk0_backup1_w1_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup1 Word2 Data */ +/** Type of blk0_backup1_w2 register + * Otp debuger block0 data register3. + */ +typedef union { + struct { + /** block0_backup1_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word2 data. + */ + uint32_t block0_backup1_w2:32; + }; + uint32_t val; +} otp_debug_blk0_backup1_w2_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup1 Word3 Data */ +/** Type of blk0_backup1_w3 register + * Otp debuger block0 data register4. + */ +typedef union { + struct { + /** block0_backup1_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word3 data. + */ + uint32_t block0_backup1_w3:32; + }; + uint32_t val; +} otp_debug_blk0_backup1_w3_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup1 Word4 Data */ +/** Type of blk0_backup1_w4 register + * Otp debuger block0 data register5. + */ +typedef union { + struct { + /** block0_backup1_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word4 data. + */ + uint32_t block0_backup1_w4:32; + }; + uint32_t val; +} otp_debug_blk0_backup1_w4_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup1 Word5 Data */ +/** Type of blk0_backup1_w5 register + * Otp debuger block0 data register6. + */ +typedef union { + struct { + /** block0_backup1_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word5 data. + */ + uint32_t block0_backup1_w5:32; + }; + uint32_t val; +} otp_debug_blk0_backup1_w5_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup2 Word1 Data */ +/** Type of blk0_backup2_w1 register + * Otp debuger block0 data register7. + */ +typedef union { + struct { + /** block0_backup2_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word1 data. + */ + uint32_t block0_backup2_w1:32; + }; + uint32_t val; +} otp_debug_blk0_backup2_w1_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup2 Word2 Data */ +/** Type of blk0_backup2_w2 register + * Otp debuger block0 data register8. + */ +typedef union { + struct { + /** block0_backup2_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word2 data. + */ + uint32_t block0_backup2_w2:32; + }; + uint32_t val; +} otp_debug_blk0_backup2_w2_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup2 Word3 Data */ +/** Type of blk0_backup2_w3 register + * Otp debuger block0 data register9. + */ +typedef union { + struct { + /** block0_backup2_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word3 data. + */ + uint32_t block0_backup2_w3:32; + }; + uint32_t val; +} otp_debug_blk0_backup2_w3_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup2 Word4 Data */ +/** Type of blk0_backup2_w4 register + * Otp debuger block0 data register10. + */ +typedef union { + struct { + /** block0_backup2_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word4 data. + */ + uint32_t block0_backup2_w4:32; + }; + uint32_t val; +} otp_debug_blk0_backup2_w4_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup2 Word5 Data */ +/** Type of blk0_backup2_w5 register + * Otp debuger block0 data register11. + */ +typedef union { + struct { + /** block0_backup2_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word5 data. + */ + uint32_t block0_backup2_w5:32; + }; + uint32_t val; +} otp_debug_blk0_backup2_w5_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup3 Word1 Data */ +/** Type of blk0_backup3_w1 register + * Otp debuger block0 data register12. + */ +typedef union { + struct { + /** block0_backup3_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word1 data. + */ + uint32_t block0_backup3_w1:32; + }; + uint32_t val; +} otp_debug_blk0_backup3_w1_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup3 Word2 Data */ +/** Type of blk0_backup3_w2 register + * Otp debuger block0 data register13. + */ +typedef union { + struct { + /** block0_backup3_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word2 data. + */ + uint32_t block0_backup3_w2:32; + }; + uint32_t val; +} otp_debug_blk0_backup3_w2_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup3 Word3 Data */ +/** Type of blk0_backup3_w3 register + * Otp debuger block0 data register14. + */ +typedef union { + struct { + /** block0_backup3_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word3 data. + */ + uint32_t block0_backup3_w3:32; + }; + uint32_t val; +} otp_debug_blk0_backup3_w3_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup3 Word4 Data */ +/** Type of blk0_backup3_w4 register + * Otp debuger block0 data register15. + */ +typedef union { + struct { + /** block0_backup3_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word4 data. + */ + uint32_t block0_backup3_w4:32; + }; + uint32_t val; +} otp_debug_blk0_backup3_w4_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup3 Word5 Data */ +/** Type of blk0_backup3_w5 register + * Otp debuger block0 data register16. + */ +typedef union { + struct { + /** block0_backup3_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word5 data. + */ + uint32_t block0_backup3_w5:32; + }; + uint32_t val; +} otp_debug_blk0_backup3_w5_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup4 Word1 Data */ +/** Type of blk0_backup4_w1 register + * Otp debuger block0 data register17. + */ +typedef union { + struct { + /** block0_backup4_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word1 data. + */ + uint32_t block0_backup4_w1:32; + }; + uint32_t val; +} otp_debug_blk0_backup4_w1_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup4 Word2 Data */ +/** Type of blk0_backup4_w2 register + * Otp debuger block0 data register18. + */ +typedef union { + struct { + /** block0_backup4_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word2 data. + */ + uint32_t block0_backup4_w2:32; + }; + uint32_t val; +} otp_debug_blk0_backup4_w2_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup4 Word3 Data */ +/** Type of blk0_backup4_w3 register + * Otp debuger block0 data register19. + */ +typedef union { + struct { + /** block0_backup4_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word3 data. + */ + uint32_t block0_backup4_w3:32; + }; + uint32_t val; +} otp_debug_blk0_backup4_w3_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup4 Word4 Data */ +/** Type of blk0_backup4_w4 register + * Otp debuger block0 data register20. + */ +typedef union { + struct { + /** block0_backup4_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word4 data. + */ + uint32_t block0_backup4_w4:32; + }; + uint32_t val; +} otp_debug_blk0_backup4_w4_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup4 Word5 Data */ +/** Type of blk0_backup4_w5 register + * Otp debuger block0 data register21. + */ +typedef union { + struct { + /** block0_backup4_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word5 data. + */ + uint32_t block0_backup4_w5:32; + }; + uint32_t val; +} otp_debug_blk0_backup4_w5_reg_t; + + +/** Group: OTP_DEBUG Block1 Word1 Data */ +/** Type of blk1_w1 register + * Otp debuger block1 data register1. + */ +typedef union { + struct { + /** block1_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word1 data. + */ + uint32_t block1_w1:32; + }; + uint32_t val; +} otp_debug_blk1_w1_reg_t; + + +/** Group: OTP_DEBUG Block1 Word2 Data */ +/** Type of blk1_w2 register + * Otp debuger block1 data register2. + */ +typedef union { + struct { + /** block1_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word2 data. + */ + uint32_t block1_w2:32; + }; + uint32_t val; +} otp_debug_blk1_w2_reg_t; + + +/** Group: OTP_DEBUG Block1 Word3 Data */ +/** Type of blk1_w3 register + * Otp debuger block1 data register3. + */ +typedef union { + struct { + /** block1_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word3 data. + */ + uint32_t block1_w3:32; + }; + uint32_t val; +} otp_debug_blk1_w3_reg_t; + + +/** Group: OTP_DEBUG Block1 Word4 Data */ +/** Type of blk1_w4 register + * Otp debuger block1 data register4. + */ +typedef union { + struct { + /** block1_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word4 data. + */ + uint32_t block1_w4:32; + }; + uint32_t val; +} otp_debug_blk1_w4_reg_t; + + +/** Group: OTP_DEBUG Block1 Word5 Data */ +/** Type of blk1_w5 register + * Otp debuger block1 data register5. + */ +typedef union { + struct { + /** block1_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word5 data. + */ + uint32_t block1_w5:32; + }; + uint32_t val; +} otp_debug_blk1_w5_reg_t; + + +/** Group: OTP_DEBUG Block1 Word6 Data */ +/** Type of blk1_w6 register + * Otp debuger block1 data register6. + */ +typedef union { + struct { + /** block1_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word6 data. + */ + uint32_t block1_w6:32; + }; + uint32_t val; +} otp_debug_blk1_w6_reg_t; + + +/** Group: OTP_DEBUG Block1 Word7 Data */ +/** Type of blk1_w7 register + * Otp debuger block1 data register7. + */ +typedef union { + struct { + /** block1_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word7 data. + */ + uint32_t block1_w7:32; + }; + uint32_t val; +} otp_debug_blk1_w7_reg_t; + + +/** Group: OTP_DEBUG Block1 Word8 Data */ +/** Type of blk1_w8 register + * Otp debuger block1 data register8. + */ +typedef union { + struct { + /** block1_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word8 data. + */ + uint32_t block1_w8:32; + }; + uint32_t val; +} otp_debug_blk1_w8_reg_t; + + +/** Group: OTP_DEBUG Block1 Word9 Data */ +/** Type of blk1_w9 register + * Otp debuger block1 data register9. + */ +typedef union { + struct { + /** block1_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word9 data. + */ + uint32_t block1_w9:32; + }; + uint32_t val; +} otp_debug_blk1_w9_reg_t; + + +/** Group: OTP_DEBUG Block2 Word1 Data */ +/** Type of blk2_w1 register + * Otp debuger block2 data register1. + */ +typedef union { + struct { + /** block2_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word1 data. + */ + uint32_t block2_w1:32; + }; + uint32_t val; +} otp_debug_blk2_w1_reg_t; + + +/** Group: OTP_DEBUG Block2 Word2 Data */ +/** Type of blk2_w2 register + * Otp debuger block2 data register2. + */ +typedef union { + struct { + /** block2_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word2 data. + */ + uint32_t block2_w2:32; + }; + uint32_t val; +} otp_debug_blk2_w2_reg_t; + + +/** Group: OTP_DEBUG Block2 Word3 Data */ +/** Type of blk2_w3 register + * Otp debuger block2 data register3. + */ +typedef union { + struct { + /** block2_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word3 data. + */ + uint32_t block2_w3:32; + }; + uint32_t val; +} otp_debug_blk2_w3_reg_t; + + +/** Group: OTP_DEBUG Block2 Word4 Data */ +/** Type of blk2_w4 register + * Otp debuger block2 data register4. + */ +typedef union { + struct { + /** block2_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word4 data. + */ + uint32_t block2_w4:32; + }; + uint32_t val; +} otp_debug_blk2_w4_reg_t; + + +/** Group: OTP_DEBUG Block2 Word5 Data */ +/** Type of blk2_w5 register + * Otp debuger block2 data register5. + */ +typedef union { + struct { + /** block2_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word5 data. + */ + uint32_t block2_w5:32; + }; + uint32_t val; +} otp_debug_blk2_w5_reg_t; + + +/** Group: OTP_DEBUG Block2 Word6 Data */ +/** Type of blk2_w6 register + * Otp debuger block2 data register6. + */ +typedef union { + struct { + /** block2_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word6 data. + */ + uint32_t block2_w6:32; + }; + uint32_t val; +} otp_debug_blk2_w6_reg_t; + + +/** Group: OTP_DEBUG Block2 Word7 Data */ +/** Type of blk2_w7 register + * Otp debuger block2 data register7. + */ +typedef union { + struct { + /** block2_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word7 data. + */ + uint32_t block2_w7:32; + }; + uint32_t val; +} otp_debug_blk2_w7_reg_t; + + +/** Group: OTP_DEBUG Block2 Word8 Data */ +/** Type of blk2_w8 register + * Otp debuger block2 data register8. + */ +typedef union { + struct { + /** block2_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word8 data. + */ + uint32_t block2_w8:32; + }; + uint32_t val; +} otp_debug_blk2_w8_reg_t; + + +/** Group: OTP_DEBUG Block2 Word9 Data */ +/** Type of blk2_w9 register + * Otp debuger block2 data register9. + */ +typedef union { + struct { + /** block2_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word9 data. + */ + uint32_t block2_w9:32; + }; + uint32_t val; +} otp_debug_blk2_w9_reg_t; + + +/** Group: OTP_DEBUG Block2 Word10 Data */ +/** Type of blk2_w10 register + * Otp debuger block2 data register10. + */ +typedef union { + struct { + /** block2_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word10 data. + */ + uint32_t block2_w10:32; + }; + uint32_t val; +} otp_debug_blk2_w10_reg_t; + + +/** Group: OTP_DEBUG Block2 Word11 Data */ +/** Type of blk2_w11 register + * Otp debuger block2 data register11. + */ +typedef union { + struct { + /** block2_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word11 data. + */ + uint32_t block2_w11:32; + }; + uint32_t val; +} otp_debug_blk2_w11_reg_t; + +/** Type of blk10_w11 register + * Otp debuger block10 data register11. + */ +typedef union { + struct { + /** block10_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word11 data. + */ + uint32_t block10_w11:32; + }; + uint32_t val; +} otp_debug_blk10_w11_reg_t; + + +/** Group: OTP_DEBUG Block3 Word1 Data */ +/** Type of blk3_w1 register + * Otp debuger block3 data register1. + */ +typedef union { + struct { + /** block3_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word1 data. + */ + uint32_t block3_w1:32; + }; + uint32_t val; +} otp_debug_blk3_w1_reg_t; + + +/** Group: OTP_DEBUG Block3 Word2 Data */ +/** Type of blk3_w2 register + * Otp debuger block3 data register2. + */ +typedef union { + struct { + /** block3_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word2 data. + */ + uint32_t block3_w2:32; + }; + uint32_t val; +} otp_debug_blk3_w2_reg_t; + + +/** Group: OTP_DEBUG Block3 Word3 Data */ +/** Type of blk3_w3 register + * Otp debuger block3 data register3. + */ +typedef union { + struct { + /** block3_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word3 data. + */ + uint32_t block3_w3:32; + }; + uint32_t val; +} otp_debug_blk3_w3_reg_t; + + +/** Group: OTP_DEBUG Block3 Word4 Data */ +/** Type of blk3_w4 register + * Otp debuger block3 data register4. + */ +typedef union { + struct { + /** block3_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word4 data. + */ + uint32_t block3_w4:32; + }; + uint32_t val; +} otp_debug_blk3_w4_reg_t; + + +/** Group: OTP_DEBUG Block3 Word5 Data */ +/** Type of blk3_w5 register + * Otp debuger block3 data register5. + */ +typedef union { + struct { + /** block3_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word5 data. + */ + uint32_t block3_w5:32; + }; + uint32_t val; +} otp_debug_blk3_w5_reg_t; + + +/** Group: OTP_DEBUG Block3 Word6 Data */ +/** Type of blk3_w6 register + * Otp debuger block3 data register6. + */ +typedef union { + struct { + /** block3_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word6 data. + */ + uint32_t block3_w6:32; + }; + uint32_t val; +} otp_debug_blk3_w6_reg_t; + + +/** Group: OTP_DEBUG Block3 Word7 Data */ +/** Type of blk3_w7 register + * Otp debuger block3 data register7. + */ +typedef union { + struct { + /** block3_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word7 data. + */ + uint32_t block3_w7:32; + }; + uint32_t val; +} otp_debug_blk3_w7_reg_t; + + +/** Group: OTP_DEBUG Block3 Word8 Data */ +/** Type of blk3_w8 register + * Otp debuger block3 data register8. + */ +typedef union { + struct { + /** block3_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word8 data. + */ + uint32_t block3_w8:32; + }; + uint32_t val; +} otp_debug_blk3_w8_reg_t; + + +/** Group: OTP_DEBUG Block3 Word9 Data */ +/** Type of blk3_w9 register + * Otp debuger block3 data register9. + */ +typedef union { + struct { + /** block3_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word9 data. + */ + uint32_t block3_w9:32; + }; + uint32_t val; +} otp_debug_blk3_w9_reg_t; + + +/** Group: OTP_DEBUG Block3 Word10 Data */ +/** Type of blk3_w10 register + * Otp debuger block3 data register10. + */ +typedef union { + struct { + /** block3_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word10 data. + */ + uint32_t block3_w10:32; + }; + uint32_t val; +} otp_debug_blk3_w10_reg_t; + + +/** Group: OTP_DEBUG Block3 Word11 Data */ +/** Type of blk3_w11 register + * Otp debuger block3 data register11. + */ +typedef union { + struct { + /** block3_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word11 data. + */ + uint32_t block3_w11:32; + }; + uint32_t val; +} otp_debug_blk3_w11_reg_t; + + +/** Group: OTP_DEBUG Block4 Word1 Data */ +/** Type of blk4_w1 register + * Otp debuger block4 data register1. + */ +typedef union { + struct { + /** block4_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word1 data. + */ + uint32_t block4_w1:32; + }; + uint32_t val; +} otp_debug_blk4_w1_reg_t; + + +/** Group: OTP_DEBUG Block4 Word2 Data */ +/** Type of blk4_w2 register + * Otp debuger block4 data register2. + */ +typedef union { + struct { + /** block4_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word2 data. + */ + uint32_t block4_w2:32; + }; + uint32_t val; +} otp_debug_blk4_w2_reg_t; + + +/** Group: OTP_DEBUG Block4 Word3 Data */ +/** Type of blk4_w3 register + * Otp debuger block4 data register3. + */ +typedef union { + struct { + /** block4_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word3 data. + */ + uint32_t block4_w3:32; + }; + uint32_t val; +} otp_debug_blk4_w3_reg_t; + + +/** Group: OTP_DEBUG Block4 Word4 Data */ +/** Type of blk4_w4 register + * Otp debuger block4 data register4. + */ +typedef union { + struct { + /** block4_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word4 data. + */ + uint32_t block4_w4:32; + }; + uint32_t val; +} otp_debug_blk4_w4_reg_t; + + +/** Group: OTP_DEBUG Block4 Word5 Data */ +/** Type of blk4_w5 register + * Otp debuger block4 data register5. + */ +typedef union { + struct { + /** block4_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word5 data. + */ + uint32_t block4_w5:32; + }; + uint32_t val; +} otp_debug_blk4_w5_reg_t; + + +/** Group: OTP_DEBUG Block4 Word6 Data */ +/** Type of blk4_w6 register + * Otp debuger block4 data register6. + */ +typedef union { + struct { + /** block4_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word6 data. + */ + uint32_t block4_w6:32; + }; + uint32_t val; +} otp_debug_blk4_w6_reg_t; + + +/** Group: OTP_DEBUG Block4 Word7 Data */ +/** Type of blk4_w7 register + * Otp debuger block4 data register7. + */ +typedef union { + struct { + /** block4_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word7 data. + */ + uint32_t block4_w7:32; + }; + uint32_t val; +} otp_debug_blk4_w7_reg_t; + + +/** Group: OTP_DEBUG Block4 Word8 Data */ +/** Type of blk4_w8 register + * Otp debuger block4 data register8. + */ +typedef union { + struct { + /** block4_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word8 data. + */ + uint32_t block4_w8:32; + }; + uint32_t val; +} otp_debug_blk4_w8_reg_t; + + +/** Group: OTP_DEBUG Block4 Word9 Data */ +/** Type of blk4_w9 register + * Otp debuger block4 data register9. + */ +typedef union { + struct { + /** block4_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word9 data. + */ + uint32_t block4_w9:32; + }; + uint32_t val; +} otp_debug_blk4_w9_reg_t; + + +/** Group: OTP_DEBUG Block4 Word10 Data */ +/** Type of blk4_w10 register + * Otp debuger block4 data registe10. + */ +typedef union { + struct { + /** block4_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word10 data. + */ + uint32_t block4_w10:32; + }; + uint32_t val; +} otp_debug_blk4_w10_reg_t; + + +/** Group: OTP_DEBUG Block4 Word11 Data */ +/** Type of blk4_w11 register + * Otp debuger block4 data register11. + */ +typedef union { + struct { + /** block4_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word11 data. + */ + uint32_t block4_w11:32; + }; + uint32_t val; +} otp_debug_blk4_w11_reg_t; + + +/** Group: OTP_DEBUG Block5 Word1 Data */ +/** Type of blk5_w1 register + * Otp debuger block5 data register1. + */ +typedef union { + struct { + /** block5_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word1 data. + */ + uint32_t block5_w1:32; + }; + uint32_t val; +} otp_debug_blk5_w1_reg_t; + + +/** Group: OTP_DEBUG Block5 Word2 Data */ +/** Type of blk5_w2 register + * Otp debuger block5 data register2. + */ +typedef union { + struct { + /** block5_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word2 data. + */ + uint32_t block5_w2:32; + }; + uint32_t val; +} otp_debug_blk5_w2_reg_t; + + +/** Group: OTP_DEBUG Block5 Word3 Data */ +/** Type of blk5_w3 register + * Otp debuger block5 data register3. + */ +typedef union { + struct { + /** block5_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word3 data. + */ + uint32_t block5_w3:32; + }; + uint32_t val; +} otp_debug_blk5_w3_reg_t; + + +/** Group: OTP_DEBUG Block5 Word4 Data */ +/** Type of blk5_w4 register + * Otp debuger block5 data register4. + */ +typedef union { + struct { + /** block5_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word4 data. + */ + uint32_t block5_w4:32; + }; + uint32_t val; +} otp_debug_blk5_w4_reg_t; + + +/** Group: OTP_DEBUG Block5 Word5 Data */ +/** Type of blk5_w5 register + * Otp debuger block5 data register5. + */ +typedef union { + struct { + /** block5_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word5 data. + */ + uint32_t block5_w5:32; + }; + uint32_t val; +} otp_debug_blk5_w5_reg_t; + + +/** Group: OTP_DEBUG Block5 Word6 Data */ +/** Type of blk5_w6 register + * Otp debuger block5 data register6. + */ +typedef union { + struct { + /** block5_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word6 data. + */ + uint32_t block5_w6:32; + }; + uint32_t val; +} otp_debug_blk5_w6_reg_t; + + +/** Group: OTP_DEBUG Block5 Word7 Data */ +/** Type of blk5_w7 register + * Otp debuger block5 data register7. + */ +typedef union { + struct { + /** block5_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word7 data. + */ + uint32_t block5_w7:32; + }; + uint32_t val; +} otp_debug_blk5_w7_reg_t; + + +/** Group: OTP_DEBUG Block5 Word8 Data */ +/** Type of blk5_w8 register + * Otp debuger block5 data register8. + */ +typedef union { + struct { + /** block5_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word8 data. + */ + uint32_t block5_w8:32; + }; + uint32_t val; +} otp_debug_blk5_w8_reg_t; + + +/** Group: OTP_DEBUG Block5 Word9 Data */ +/** Type of blk5_w9 register + * Otp debuger block5 data register9. + */ +typedef union { + struct { + /** block5_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word9 data. + */ + uint32_t block5_w9:32; + }; + uint32_t val; +} otp_debug_blk5_w9_reg_t; + + +/** Group: OTP_DEBUG Block5 Word10 Data */ +/** Type of blk5_w10 register + * Otp debuger block5 data register10. + */ +typedef union { + struct { + /** block5_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word10 data. + */ + uint32_t block5_w10:32; + }; + uint32_t val; +} otp_debug_blk5_w10_reg_t; + + +/** Group: OTP_DEBUG Block5 Word11 Data */ +/** Type of blk5_w11 register + * Otp debuger block5 data register11. + */ +typedef union { + struct { + /** block5_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word11 data. + */ + uint32_t block5_w11:32; + }; + uint32_t val; +} otp_debug_blk5_w11_reg_t; + + +/** Group: OTP_DEBUG Block6 Word1 Data */ +/** Type of blk6_w1 register + * Otp debuger block6 data register1. + */ +typedef union { + struct { + /** block6_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word1 data. + */ + uint32_t block6_w1:32; + }; + uint32_t val; +} otp_debug_blk6_w1_reg_t; + + +/** Group: OTP_DEBUG Block6 Word2 Data */ +/** Type of blk6_w2 register + * Otp debuger block6 data register2. + */ +typedef union { + struct { + /** block6_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word2 data. + */ + uint32_t block6_w2:32; + }; + uint32_t val; +} otp_debug_blk6_w2_reg_t; + + +/** Group: OTP_DEBUG Block6 Word3 Data */ +/** Type of blk6_w3 register + * Otp debuger block6 data register3. + */ +typedef union { + struct { + /** block6_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word3 data. + */ + uint32_t block6_w3:32; + }; + uint32_t val; +} otp_debug_blk6_w3_reg_t; + + +/** Group: OTP_DEBUG Block6 Word4 Data */ +/** Type of blk6_w4 register + * Otp debuger block6 data register4. + */ +typedef union { + struct { + /** block6_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word4 data. + */ + uint32_t block6_w4:32; + }; + uint32_t val; +} otp_debug_blk6_w4_reg_t; + + +/** Group: OTP_DEBUG Block6 Word5 Data */ +/** Type of blk6_w5 register + * Otp debuger block6 data register5. + */ +typedef union { + struct { + /** block6_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word5 data. + */ + uint32_t block6_w5:32; + }; + uint32_t val; +} otp_debug_blk6_w5_reg_t; + + +/** Group: OTP_DEBUG Block6 Word6 Data */ +/** Type of blk6_w6 register + * Otp debuger block6 data register6. + */ +typedef union { + struct { + /** block6_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word6 data. + */ + uint32_t block6_w6:32; + }; + uint32_t val; +} otp_debug_blk6_w6_reg_t; + + +/** Group: OTP_DEBUG Block6 Word7 Data */ +/** Type of blk6_w7 register + * Otp debuger block6 data register7. + */ +typedef union { + struct { + /** block6_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word7 data. + */ + uint32_t block6_w7:32; + }; + uint32_t val; +} otp_debug_blk6_w7_reg_t; + + +/** Group: OTP_DEBUG Block6 Word8 Data */ +/** Type of blk6_w8 register + * Otp debuger block6 data register8. + */ +typedef union { + struct { + /** block6_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word8 data. + */ + uint32_t block6_w8:32; + }; + uint32_t val; +} otp_debug_blk6_w8_reg_t; + + +/** Group: OTP_DEBUG Block6 Word9 Data */ +/** Type of blk6_w9 register + * Otp debuger block6 data register9. + */ +typedef union { + struct { + /** block6_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word9 data. + */ + uint32_t block6_w9:32; + }; + uint32_t val; +} otp_debug_blk6_w9_reg_t; + + +/** Group: OTP_DEBUG Block6 Word10 Data */ +/** Type of blk6_w10 register + * Otp debuger block6 data register10. + */ +typedef union { + struct { + /** block6_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word10 data. + */ + uint32_t block6_w10:32; + }; + uint32_t val; +} otp_debug_blk6_w10_reg_t; + + +/** Group: OTP_DEBUG Block6 Word11 Data */ +/** Type of blk6_w11 register + * Otp debuger block6 data register11. + */ +typedef union { + struct { + /** block6_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word11 data. + */ + uint32_t block6_w11:32; + }; + uint32_t val; +} otp_debug_blk6_w11_reg_t; + + +/** Group: OTP_DEBUG Block7 Word1 Data */ +/** Type of blk7_w1 register + * Otp debuger block7 data register1. + */ +typedef union { + struct { + /** block7_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word1 data. + */ + uint32_t block7_w1:32; + }; + uint32_t val; +} otp_debug_blk7_w1_reg_t; + + +/** Group: OTP_DEBUG Block7 Word2 Data */ +/** Type of blk7_w2 register + * Otp debuger block7 data register2. + */ +typedef union { + struct { + /** block7_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word2 data. + */ + uint32_t block7_w2:32; + }; + uint32_t val; +} otp_debug_blk7_w2_reg_t; + + +/** Group: OTP_DEBUG Block7 Word3 Data */ +/** Type of blk7_w3 register + * Otp debuger block7 data register3. + */ +typedef union { + struct { + /** block7_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word3 data. + */ + uint32_t block7_w3:32; + }; + uint32_t val; +} otp_debug_blk7_w3_reg_t; + + +/** Group: OTP_DEBUG Block7 Word4 Data */ +/** Type of blk7_w4 register + * Otp debuger block7 data register4. + */ +typedef union { + struct { + /** block7_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word4 data. + */ + uint32_t block7_w4:32; + }; + uint32_t val; +} otp_debug_blk7_w4_reg_t; + + +/** Group: OTP_DEBUG Block7 Word5 Data */ +/** Type of blk7_w5 register + * Otp debuger block7 data register5. + */ +typedef union { + struct { + /** block7_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word5 data. + */ + uint32_t block7_w5:32; + }; + uint32_t val; +} otp_debug_blk7_w5_reg_t; + + +/** Group: OTP_DEBUG Block7 Word6 Data */ +/** Type of blk7_w6 register + * Otp debuger block7 data register6. + */ +typedef union { + struct { + /** block7_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word6 data. + */ + uint32_t block7_w6:32; + }; + uint32_t val; +} otp_debug_blk7_w6_reg_t; + + +/** Group: OTP_DEBUG Block7 Word7 Data */ +/** Type of blk7_w7 register + * Otp debuger block7 data register7. + */ +typedef union { + struct { + /** block7_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word7 data. + */ + uint32_t block7_w7:32; + }; + uint32_t val; +} otp_debug_blk7_w7_reg_t; + + +/** Group: OTP_DEBUG Block7 Word8 Data */ +/** Type of blk7_w8 register + * Otp debuger block7 data register8. + */ +typedef union { + struct { + /** block7_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word8 data. + */ + uint32_t block7_w8:32; + }; + uint32_t val; +} otp_debug_blk7_w8_reg_t; + + +/** Group: OTP_DEBUG Block7 Word9 Data */ +/** Type of blk7_w9 register + * Otp debuger block7 data register9. + */ +typedef union { + struct { + /** block7_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word9 data. + */ + uint32_t block7_w9:32; + }; + uint32_t val; +} otp_debug_blk7_w9_reg_t; + + +/** Group: OTP_DEBUG Block7 Word10 Data */ +/** Type of blk7_w10 register + * Otp debuger block7 data register10. + */ +typedef union { + struct { + /** block7_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word10 data. + */ + uint32_t block7_w10:32; + }; + uint32_t val; +} otp_debug_blk7_w10_reg_t; + + +/** Group: OTP_DEBUG Block7 Word11 Data */ +/** Type of blk7_w11 register + * Otp debuger block7 data register11. + */ +typedef union { + struct { + /** block7_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word11 data. + */ + uint32_t block7_w11:32; + }; + uint32_t val; +} otp_debug_blk7_w11_reg_t; + + +/** Group: OTP_DEBUG Block8 Word1 Data */ +/** Type of blk8_w1 register + * Otp debuger block8 data register1. + */ +typedef union { + struct { + /** block8_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word1 data. + */ + uint32_t block8_w1:32; + }; + uint32_t val; +} otp_debug_blk8_w1_reg_t; + + +/** Group: OTP_DEBUG Block8 Word2 Data */ +/** Type of blk8_w2 register + * Otp debuger block8 data register2. + */ +typedef union { + struct { + /** block8_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word2 data. + */ + uint32_t block8_w2:32; + }; + uint32_t val; +} otp_debug_blk8_w2_reg_t; + + +/** Group: OTP_DEBUG Block8 Word3 Data */ +/** Type of blk8_w3 register + * Otp debuger block8 data register3. + */ +typedef union { + struct { + /** block8_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word3 data. + */ + uint32_t block8_w3:32; + }; + uint32_t val; +} otp_debug_blk8_w3_reg_t; + + +/** Group: OTP_DEBUG Block8 Word4 Data */ +/** Type of blk8_w4 register + * Otp debuger block8 data register4. + */ +typedef union { + struct { + /** block8_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word4 data. + */ + uint32_t block8_w4:32; + }; + uint32_t val; +} otp_debug_blk8_w4_reg_t; + + +/** Group: OTP_DEBUG Block8 Word5 Data */ +/** Type of blk8_w5 register + * Otp debuger block8 data register5. + */ +typedef union { + struct { + /** block8_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word5 data. + */ + uint32_t block8_w5:32; + }; + uint32_t val; +} otp_debug_blk8_w5_reg_t; + + +/** Group: OTP_DEBUG Block8 Word6 Data */ +/** Type of blk8_w6 register + * Otp debuger block8 data register6. + */ +typedef union { + struct { + /** block8_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word6 data. + */ + uint32_t block8_w6:32; + }; + uint32_t val; +} otp_debug_blk8_w6_reg_t; + + +/** Group: OTP_DEBUG Block8 Word7 Data */ +/** Type of blk8_w7 register + * Otp debuger block8 data register7. + */ +typedef union { + struct { + /** block8_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word7 data. + */ + uint32_t block8_w7:32; + }; + uint32_t val; +} otp_debug_blk8_w7_reg_t; + + +/** Group: OTP_DEBUG Block8 Word8 Data */ +/** Type of blk8_w8 register + * Otp debuger block8 data register8. + */ +typedef union { + struct { + /** block8_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word8 data. + */ + uint32_t block8_w8:32; + }; + uint32_t val; +} otp_debug_blk8_w8_reg_t; + + +/** Group: OTP_DEBUG Block8 Word9 Data */ +/** Type of blk8_w9 register + * Otp debuger block8 data register9. + */ +typedef union { + struct { + /** block8_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word9 data. + */ + uint32_t block8_w9:32; + }; + uint32_t val; +} otp_debug_blk8_w9_reg_t; + + +/** Group: OTP_DEBUG Block8 Word10 Data */ +/** Type of blk8_w10 register + * Otp debuger block8 data register10. + */ +typedef union { + struct { + /** block8_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word10 data. + */ + uint32_t block8_w10:32; + }; + uint32_t val; +} otp_debug_blk8_w10_reg_t; + + +/** Group: OTP_DEBUG Block8 Word11 Data */ +/** Type of blk8_w11 register + * Otp debuger block8 data register11. + */ +typedef union { + struct { + /** block8_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word11 data. + */ + uint32_t block8_w11:32; + }; + uint32_t val; +} otp_debug_blk8_w11_reg_t; + + +/** Group: OTP_DEBUG Block9 Word1 Data */ +/** Type of blk9_w1 register + * Otp debuger block9 data register1. + */ +typedef union { + struct { + /** block9_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word1 data. + */ + uint32_t block9_w1:32; + }; + uint32_t val; +} otp_debug_blk9_w1_reg_t; + + +/** Group: OTP_DEBUG Block9 Word2 Data */ +/** Type of blk9_w2 register + * Otp debuger block9 data register2. + */ +typedef union { + struct { + /** block9_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word2 data. + */ + uint32_t block9_w2:32; + }; + uint32_t val; +} otp_debug_blk9_w2_reg_t; + + +/** Group: OTP_DEBUG Block9 Word3 Data */ +/** Type of blk9_w3 register + * Otp debuger block9 data register3. + */ +typedef union { + struct { + /** block9_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word3 data. + */ + uint32_t block9_w3:32; + }; + uint32_t val; +} otp_debug_blk9_w3_reg_t; + + +/** Group: OTP_DEBUG Block9 Word4 Data */ +/** Type of blk9_w4 register + * Otp debuger block9 data register4. + */ +typedef union { + struct { + /** block9_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word4 data. + */ + uint32_t block9_w4:32; + }; + uint32_t val; +} otp_debug_blk9_w4_reg_t; + + +/** Group: OTP_DEBUG Block9 Word5 Data */ +/** Type of blk9_w5 register + * Otp debuger block9 data register5. + */ +typedef union { + struct { + /** block9_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word5 data. + */ + uint32_t block9_w5:32; + }; + uint32_t val; +} otp_debug_blk9_w5_reg_t; + + +/** Group: OTP_DEBUG Block9 Word6 Data */ +/** Type of blk9_w6 register + * Otp debuger block9 data register6. + */ +typedef union { + struct { + /** block9_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word6 data. + */ + uint32_t block9_w6:32; + }; + uint32_t val; +} otp_debug_blk9_w6_reg_t; + + +/** Group: OTP_DEBUG Block9 Word7 Data */ +/** Type of blk9_w7 register + * Otp debuger block9 data register7. + */ +typedef union { + struct { + /** block9_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word7 data. + */ + uint32_t block9_w7:32; + }; + uint32_t val; +} otp_debug_blk9_w7_reg_t; + + +/** Group: OTP_DEBUG Block9 Word8 Data */ +/** Type of blk9_w8 register + * Otp debuger block9 data register8. + */ +typedef union { + struct { + /** block9_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word8 data. + */ + uint32_t block9_w8:32; + }; + uint32_t val; +} otp_debug_blk9_w8_reg_t; + + +/** Group: OTP_DEBUG Block9 Word9 Data */ +/** Type of blk9_w9 register + * Otp debuger block9 data register9. + */ +typedef union { + struct { + /** block9_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word9 data. + */ + uint32_t block9_w9:32; + }; + uint32_t val; +} otp_debug_blk9_w9_reg_t; + + +/** Group: OTP_DEBUG Block9 Word10 Data */ +/** Type of blk9_w10 register + * Otp debuger block9 data register10. + */ +typedef union { + struct { + /** block9_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word10 data. + */ + uint32_t block9_w10:32; + }; + uint32_t val; +} otp_debug_blk9_w10_reg_t; + + +/** Group: OTP_DEBUG Block9 Word11 Data */ +/** Type of blk9_w11 register + * Otp debuger block9 data register11. + */ +typedef union { + struct { + /** block9_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word11 data. + */ + uint32_t block9_w11:32; + }; + uint32_t val; +} otp_debug_blk9_w11_reg_t; + + +/** Group: OTP_DEBUG Block10 Word1 Data */ +/** Type of blk10_w1 register + * Otp debuger block10 data register1. + */ +typedef union { + struct { + /** block10_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word1 data. + */ + uint32_t block10_w1:32; + }; + uint32_t val; +} otp_debug_blk10_w1_reg_t; + + +/** Group: OTP_DEBUG Block10 Word2 Data */ +/** Type of blk10_w2 register + * Otp debuger block10 data register2. + */ +typedef union { + struct { + /** block10_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word2 data. + */ + uint32_t block10_w2:32; + }; + uint32_t val; +} otp_debug_blk10_w2_reg_t; + + +/** Group: OTP_DEBUG Block10 Word3 Data */ +/** Type of blk10_w3 register + * Otp debuger block10 data register3. + */ +typedef union { + struct { + /** block10_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word3 data. + */ + uint32_t block10_w3:32; + }; + uint32_t val; +} otp_debug_blk10_w3_reg_t; + + +/** Group: OTP_DEBUG Block10 Word4 Data */ +/** Type of blk10_w4 register + * Otp debuger block10 data register4. + */ +typedef union { + struct { + /** block10_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word4 data. + */ + uint32_t block10_w4:32; + }; + uint32_t val; +} otp_debug_blk10_w4_reg_t; + + +/** Group: OTP_DEBUG Block10 Word5 Data */ +/** Type of blk10_w5 register + * Otp debuger block10 data register5. + */ +typedef union { + struct { + /** block10_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word5 data. + */ + uint32_t block10_w5:32; + }; + uint32_t val; +} otp_debug_blk10_w5_reg_t; + + +/** Group: OTP_DEBUG Block10 Word6 Data */ +/** Type of blk10_w6 register + * Otp debuger block10 data register6. + */ +typedef union { + struct { + /** block10_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word6 data. + */ + uint32_t block10_w6:32; + }; + uint32_t val; +} otp_debug_blk10_w6_reg_t; + + +/** Group: OTP_DEBUG Block10 Word7 Data */ +/** Type of blk10_w7 register + * Otp debuger block10 data register7. + */ +typedef union { + struct { + /** block10_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word7 data. + */ + uint32_t block10_w7:32; + }; + uint32_t val; +} otp_debug_blk10_w7_reg_t; + + +/** Group: OTP_DEBUG Block10 Word8 Data */ +/** Type of blk10_w8 register + * Otp debuger block10 data register8. + */ +typedef union { + struct { + /** block10_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word8 data. + */ + uint32_t block10_w8:32; + }; + uint32_t val; +} otp_debug_blk10_w8_reg_t; + + +/** Group: OTP_DEBUG Block10 Word9 Data */ +/** Type of blk10_w9 register + * Otp debuger block10 data register9. + */ +typedef union { + struct { + /** block10_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word9 data. + */ + uint32_t block10_w9:32; + }; + uint32_t val; +} otp_debug_blk10_w9_reg_t; + + +/** Group: OTP_DEBUG Block10 Word10 Data */ +/** Type of blk10_w10 register + * Otp debuger block10 data register10. + */ +typedef union { + struct { + /** block19_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word10 data. + */ + uint32_t block19_w10:32; + }; + uint32_t val; +} otp_debug_blk10_w10_reg_t; + + +/** Group: OTP_DEBUG Clock_en Configuration Register */ +/** Type of clk register + * Otp debuger clk_en configuration register. + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Force clock on for this register file. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} otp_debug_clk_reg_t; + + +/** Group: OTP_DEBUG Apb2otp Enable Singal */ +/** Type of apb2otp_en register + * Otp_debuger apb2otp enable configuration register. + */ +typedef union { + struct { + /** apb2otp_en : R/W; bitpos: [0]; default: 0; + * Debug mode enable signal. + */ + uint32_t apb2otp_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} otp_debug_apb2otp_en_reg_t; + + +/** Group: OTP_DEBUG Version Register */ +/** Type of date register + * eFuse version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 539037736; + * Stores otp_debug version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} otp_debug_date_reg_t; + + +typedef struct otp_debug_dev_t { + volatile otp_debug_wr_dis_reg_t wr_dis; + volatile otp_debug_blk0_backup1_w1_reg_t blk0_backup1_w1; + volatile otp_debug_blk0_backup1_w2_reg_t blk0_backup1_w2; + volatile otp_debug_blk0_backup1_w3_reg_t blk0_backup1_w3; + volatile otp_debug_blk0_backup1_w4_reg_t blk0_backup1_w4; + volatile otp_debug_blk0_backup1_w5_reg_t blk0_backup1_w5; + volatile otp_debug_blk0_backup2_w1_reg_t blk0_backup2_w1; + volatile otp_debug_blk0_backup2_w2_reg_t blk0_backup2_w2; + volatile otp_debug_blk0_backup2_w3_reg_t blk0_backup2_w3; + volatile otp_debug_blk0_backup2_w4_reg_t blk0_backup2_w4; + volatile otp_debug_blk0_backup2_w5_reg_t blk0_backup2_w5; + volatile otp_debug_blk0_backup3_w1_reg_t blk0_backup3_w1; + volatile otp_debug_blk0_backup3_w2_reg_t blk0_backup3_w2; + volatile otp_debug_blk0_backup3_w3_reg_t blk0_backup3_w3; + volatile otp_debug_blk0_backup3_w4_reg_t blk0_backup3_w4; + volatile otp_debug_blk0_backup3_w5_reg_t blk0_backup3_w5; + volatile otp_debug_blk0_backup4_w1_reg_t blk0_backup4_w1; + volatile otp_debug_blk0_backup4_w2_reg_t blk0_backup4_w2; + volatile otp_debug_blk0_backup4_w3_reg_t blk0_backup4_w3; + volatile otp_debug_blk0_backup4_w4_reg_t blk0_backup4_w4; + volatile otp_debug_blk0_backup4_w5_reg_t blk0_backup4_w5; + volatile otp_debug_blk1_w1_reg_t blk1_w1; + volatile otp_debug_blk1_w2_reg_t blk1_w2; + volatile otp_debug_blk1_w3_reg_t blk1_w3; + volatile otp_debug_blk1_w4_reg_t blk1_w4; + volatile otp_debug_blk1_w5_reg_t blk1_w5; + volatile otp_debug_blk1_w6_reg_t blk1_w6; + volatile otp_debug_blk1_w7_reg_t blk1_w7; + volatile otp_debug_blk1_w8_reg_t blk1_w8; + volatile otp_debug_blk1_w9_reg_t blk1_w9; + volatile otp_debug_blk2_w1_reg_t blk2_w1; + volatile otp_debug_blk2_w2_reg_t blk2_w2; + volatile otp_debug_blk2_w3_reg_t blk2_w3; + volatile otp_debug_blk2_w4_reg_t blk2_w4; + volatile otp_debug_blk2_w5_reg_t blk2_w5; + volatile otp_debug_blk2_w6_reg_t blk2_w6; + volatile otp_debug_blk2_w7_reg_t blk2_w7; + volatile otp_debug_blk2_w8_reg_t blk2_w8; + volatile otp_debug_blk2_w9_reg_t blk2_w9; + volatile otp_debug_blk2_w10_reg_t blk2_w10; + volatile otp_debug_blk2_w11_reg_t blk2_w11; + volatile otp_debug_blk3_w1_reg_t blk3_w1; + volatile otp_debug_blk3_w2_reg_t blk3_w2; + volatile otp_debug_blk3_w3_reg_t blk3_w3; + volatile otp_debug_blk3_w4_reg_t blk3_w4; + volatile otp_debug_blk3_w5_reg_t blk3_w5; + volatile otp_debug_blk3_w6_reg_t blk3_w6; + volatile otp_debug_blk3_w7_reg_t blk3_w7; + volatile otp_debug_blk3_w8_reg_t blk3_w8; + volatile otp_debug_blk3_w9_reg_t blk3_w9; + volatile otp_debug_blk3_w10_reg_t blk3_w10; + volatile otp_debug_blk3_w11_reg_t blk3_w11; + volatile otp_debug_blk4_w1_reg_t blk4_w1; + volatile otp_debug_blk4_w2_reg_t blk4_w2; + volatile otp_debug_blk4_w3_reg_t blk4_w3; + volatile otp_debug_blk4_w4_reg_t blk4_w4; + volatile otp_debug_blk4_w5_reg_t blk4_w5; + volatile otp_debug_blk4_w6_reg_t blk4_w6; + volatile otp_debug_blk4_w7_reg_t blk4_w7; + volatile otp_debug_blk4_w8_reg_t blk4_w8; + volatile otp_debug_blk4_w9_reg_t blk4_w9; + volatile otp_debug_blk4_w10_reg_t blk4_w10; + volatile otp_debug_blk4_w11_reg_t blk4_w11; + volatile otp_debug_blk5_w1_reg_t blk5_w1; + volatile otp_debug_blk5_w2_reg_t blk5_w2; + volatile otp_debug_blk5_w3_reg_t blk5_w3; + volatile otp_debug_blk5_w4_reg_t blk5_w4; + volatile otp_debug_blk5_w5_reg_t blk5_w5; + volatile otp_debug_blk5_w6_reg_t blk5_w6; + volatile otp_debug_blk5_w7_reg_t blk5_w7; + volatile otp_debug_blk5_w8_reg_t blk5_w8; + volatile otp_debug_blk5_w9_reg_t blk5_w9; + volatile otp_debug_blk5_w10_reg_t blk5_w10; + volatile otp_debug_blk5_w11_reg_t blk5_w11; + volatile otp_debug_blk6_w1_reg_t blk6_w1; + volatile otp_debug_blk6_w2_reg_t blk6_w2; + volatile otp_debug_blk6_w3_reg_t blk6_w3; + volatile otp_debug_blk6_w4_reg_t blk6_w4; + volatile otp_debug_blk6_w5_reg_t blk6_w5; + volatile otp_debug_blk6_w6_reg_t blk6_w6; + volatile otp_debug_blk6_w7_reg_t blk6_w7; + volatile otp_debug_blk6_w8_reg_t blk6_w8; + volatile otp_debug_blk6_w9_reg_t blk6_w9; + volatile otp_debug_blk6_w10_reg_t blk6_w10; + volatile otp_debug_blk6_w11_reg_t blk6_w11; + volatile otp_debug_blk7_w1_reg_t blk7_w1; + volatile otp_debug_blk7_w2_reg_t blk7_w2; + volatile otp_debug_blk7_w3_reg_t blk7_w3; + volatile otp_debug_blk7_w4_reg_t blk7_w4; + volatile otp_debug_blk7_w5_reg_t blk7_w5; + volatile otp_debug_blk7_w6_reg_t blk7_w6; + volatile otp_debug_blk7_w7_reg_t blk7_w7; + volatile otp_debug_blk7_w8_reg_t blk7_w8; + volatile otp_debug_blk7_w9_reg_t blk7_w9; + volatile otp_debug_blk7_w10_reg_t blk7_w10; + volatile otp_debug_blk7_w11_reg_t blk7_w11; + volatile otp_debug_blk8_w1_reg_t blk8_w1; + volatile otp_debug_blk8_w2_reg_t blk8_w2; + volatile otp_debug_blk8_w3_reg_t blk8_w3; + volatile otp_debug_blk8_w4_reg_t blk8_w4; + volatile otp_debug_blk8_w5_reg_t blk8_w5; + volatile otp_debug_blk8_w6_reg_t blk8_w6; + volatile otp_debug_blk8_w7_reg_t blk8_w7; + volatile otp_debug_blk8_w8_reg_t blk8_w8; + volatile otp_debug_blk8_w9_reg_t blk8_w9; + volatile otp_debug_blk8_w10_reg_t blk8_w10; + volatile otp_debug_blk8_w11_reg_t blk8_w11; + volatile otp_debug_blk9_w1_reg_t blk9_w1; + volatile otp_debug_blk9_w2_reg_t blk9_w2; + volatile otp_debug_blk9_w3_reg_t blk9_w3; + volatile otp_debug_blk9_w4_reg_t blk9_w4; + volatile otp_debug_blk9_w5_reg_t blk9_w5; + volatile otp_debug_blk9_w6_reg_t blk9_w6; + volatile otp_debug_blk9_w7_reg_t blk9_w7; + volatile otp_debug_blk9_w8_reg_t blk9_w8; + volatile otp_debug_blk9_w9_reg_t blk9_w9; + volatile otp_debug_blk9_w10_reg_t blk9_w10; + volatile otp_debug_blk9_w11_reg_t blk9_w11; + volatile otp_debug_blk10_w1_reg_t blk10_w1; + volatile otp_debug_blk10_w2_reg_t blk10_w2; + volatile otp_debug_blk10_w3_reg_t blk10_w3; + volatile otp_debug_blk10_w4_reg_t blk10_w4; + volatile otp_debug_blk10_w5_reg_t blk10_w5; + volatile otp_debug_blk10_w6_reg_t blk10_w6; + volatile otp_debug_blk10_w7_reg_t blk10_w7; + volatile otp_debug_blk10_w8_reg_t blk10_w8; + volatile otp_debug_blk10_w9_reg_t blk10_w9; + volatile otp_debug_blk10_w10_reg_t blk10_w10; + volatile otp_debug_blk10_w11_reg_t blk10_w11; + volatile otp_debug_clk_reg_t clk; + volatile otp_debug_apb2otp_en_reg_t apb2otp_en; + volatile otp_debug_date_reg_t date; +} otp_debug_dev_t; + +extern otp_debug_dev_t OTP_DEBUG; + +#ifndef __cplusplus +_Static_assert(sizeof(otp_debug_dev_t) == 0x210, "Invalid size of otp_debug_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/parl_io_reg.h b/components/soc/esp32c6/include/soc/parl_io_reg.h new file mode 100644 index 0000000000..7377e9788b --- /dev/null +++ b/components/soc/esp32c6/include/soc/parl_io_reg.h @@ -0,0 +1,383 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PARL_IO_RX_CFG0_REG register + * Parallel RX module configuration register0. + */ +#define PARL_IO_RX_CFG0_REG (DR_REG_PARL_IO_BASE + 0x0) +/** PARL_IO_RX_EOF_GEN_SEL : R/W; bitpos: [0]; default: 0; + * Write 0 to select eof generated manchnism by configured data byte length. Write 1 + * to select eof generated manchnism by external enable signal. + */ +#define PARL_IO_RX_EOF_GEN_SEL (BIT(0)) +#define PARL_IO_RX_EOF_GEN_SEL_M (PARL_IO_RX_EOF_GEN_SEL_V << PARL_IO_RX_EOF_GEN_SEL_S) +#define PARL_IO_RX_EOF_GEN_SEL_V 0x00000001U +#define PARL_IO_RX_EOF_GEN_SEL_S 0 +/** PARL_IO_RX_START : R/W; bitpos: [1]; default: 0; + * Write 1 to start rx global data sampling. + */ +#define PARL_IO_RX_START (BIT(1)) +#define PARL_IO_RX_START_M (PARL_IO_RX_START_V << PARL_IO_RX_START_S) +#define PARL_IO_RX_START_V 0x00000001U +#define PARL_IO_RX_START_S 1 +/** PARL_IO_RX_DATA_BYTELEN : R/W; bitpos: [17:2]; default: 0; + * Configures rx receieved data byte length. + */ +#define PARL_IO_RX_DATA_BYTELEN 0x0000FFFFU +#define PARL_IO_RX_DATA_BYTELEN_M (PARL_IO_RX_DATA_BYTELEN_V << PARL_IO_RX_DATA_BYTELEN_S) +#define PARL_IO_RX_DATA_BYTELEN_V 0x0000FFFFU +#define PARL_IO_RX_DATA_BYTELEN_S 2 +/** PARL_IO_RX_SW_EN : R/W; bitpos: [18]; default: 0; + * Write 1 to enable software data sampling. + */ +#define PARL_IO_RX_SW_EN (BIT(18)) +#define PARL_IO_RX_SW_EN_M (PARL_IO_RX_SW_EN_V << PARL_IO_RX_SW_EN_S) +#define PARL_IO_RX_SW_EN_V 0x00000001U +#define PARL_IO_RX_SW_EN_S 18 +/** PARL_IO_RX_PULSE_SUBMODE_SEL : R/W; bitpos: [22:19]; default: 0; + * Pulse submode selection. + * 0000: positive pulse start(data bit included) && positive pulse end(data bit + * included) + * 0001: positive pulse start(data bit included) && positive pulse end (data bit + * excluded) + * 0010: positive pulse start(data bit excluded) && positive pulse end (data bit + * included) + * 0011: positive pulse start(data bit excluded) && positive pulse end (data bit + * excluded) + * 0100: positive pulse start(data bit included) && length end + * 0101: positive pulse start(data bit excluded) && length end + * 0110: negative pulse start(data bit included) && negative pulse end(data bit + * included) + * 0111: negative pulse start(data bit included) && negative pulse end (data bit + * excluded) + * 1000: negative pulse start(data bit excluded) && negative pulse end (data bit + * included) + * 1001: negative pulse start(data bit excluded) && negative pulse end (data bit + * excluded) + * 1010: negative pulse start(data bit included) && length end + * 1011: negative pulse start(data bit excluded) && length end + */ +#define PARL_IO_RX_PULSE_SUBMODE_SEL 0x0000000FU +#define PARL_IO_RX_PULSE_SUBMODE_SEL_M (PARL_IO_RX_PULSE_SUBMODE_SEL_V << PARL_IO_RX_PULSE_SUBMODE_SEL_S) +#define PARL_IO_RX_PULSE_SUBMODE_SEL_V 0x0000000FU +#define PARL_IO_RX_PULSE_SUBMODE_SEL_S 19 +/** PARL_IO_RX_LEVEL_SUBMODE_SEL : R/W; bitpos: [23]; default: 0; + * Write 0 to sample data at high level of external enable signal. Write 1 to sample + * data at low level of external enable signal. + */ +#define PARL_IO_RX_LEVEL_SUBMODE_SEL (BIT(23)) +#define PARL_IO_RX_LEVEL_SUBMODE_SEL_M (PARL_IO_RX_LEVEL_SUBMODE_SEL_V << PARL_IO_RX_LEVEL_SUBMODE_SEL_S) +#define PARL_IO_RX_LEVEL_SUBMODE_SEL_V 0x00000001U +#define PARL_IO_RX_LEVEL_SUBMODE_SEL_S 23 +/** PARL_IO_RX_SMP_MODE_SEL : R/W; bitpos: [25:24]; default: 0; + * Rx data sampling mode selection. + * 000: external level enable mode + * 001: external pulse enable mode + * 010: internal software enable mode + */ +#define PARL_IO_RX_SMP_MODE_SEL 0x00000003U +#define PARL_IO_RX_SMP_MODE_SEL_M (PARL_IO_RX_SMP_MODE_SEL_V << PARL_IO_RX_SMP_MODE_SEL_S) +#define PARL_IO_RX_SMP_MODE_SEL_V 0x00000003U +#define PARL_IO_RX_SMP_MODE_SEL_S 24 +/** PARL_IO_RX_CLK_EDGE_SEL : R/W; bitpos: [26]; default: 0; + * Write 0 to enable sampling data on the rising edge of rx clock. Write 0 to enable + * sampling data on the falling edge of rx clock. + */ +#define PARL_IO_RX_CLK_EDGE_SEL (BIT(26)) +#define PARL_IO_RX_CLK_EDGE_SEL_M (PARL_IO_RX_CLK_EDGE_SEL_V << PARL_IO_RX_CLK_EDGE_SEL_S) +#define PARL_IO_RX_CLK_EDGE_SEL_V 0x00000001U +#define PARL_IO_RX_CLK_EDGE_SEL_S 26 +/** PARL_IO_RX_BIT_PACK_ORDER : R/W; bitpos: [27]; default: 0; + * Write 0 to pack bits into 1byte from MSB when data bus width is 4/2/1 bits. Write 0 + * to pack bits into 1byte from LSB when data bus width is 4/2/1 bits. + */ +#define PARL_IO_RX_BIT_PACK_ORDER (BIT(27)) +#define PARL_IO_RX_BIT_PACK_ORDER_M (PARL_IO_RX_BIT_PACK_ORDER_V << PARL_IO_RX_BIT_PACK_ORDER_S) +#define PARL_IO_RX_BIT_PACK_ORDER_V 0x00000001U +#define PARL_IO_RX_BIT_PACK_ORDER_S 27 +/** PARL_IO_RX_BUS_WID_SEL : R/W; bitpos: [30:28]; default: 0; + * Rx data bus width selection. + * 100: bus width is 1 bit + * 011: bus width is 2 bits + * 010: bus width is 4 bits + * 001: bus width is 8 bits + * 000: bus width is 16 bits + */ +#define PARL_IO_RX_BUS_WID_SEL 0x00000007U +#define PARL_IO_RX_BUS_WID_SEL_M (PARL_IO_RX_BUS_WID_SEL_V << PARL_IO_RX_BUS_WID_SEL_S) +#define PARL_IO_RX_BUS_WID_SEL_V 0x00000007U +#define PARL_IO_RX_BUS_WID_SEL_S 28 +/** PARL_IO_RX_FIFO_SRST : R/W; bitpos: [31]; default: 0; + * Write 1 to enable soft reset of async fifo in rx module. + */ +#define PARL_IO_RX_FIFO_SRST (BIT(31)) +#define PARL_IO_RX_FIFO_SRST_M (PARL_IO_RX_FIFO_SRST_V << PARL_IO_RX_FIFO_SRST_S) +#define PARL_IO_RX_FIFO_SRST_V 0x00000001U +#define PARL_IO_RX_FIFO_SRST_S 31 + +/** PARL_IO_RX_CFG1_REG register + * Parallel RX module configuration register1. + */ +#define PARL_IO_RX_CFG1_REG (DR_REG_PARL_IO_BASE + 0x4) +/** PARL_IO_RX_REG_UPDATE : WT; bitpos: [2]; default: 0; + * Write 1 to update rx register configuration signals. + */ +#define PARL_IO_RX_REG_UPDATE (BIT(2)) +#define PARL_IO_RX_REG_UPDATE_M (PARL_IO_RX_REG_UPDATE_V << PARL_IO_RX_REG_UPDATE_S) +#define PARL_IO_RX_REG_UPDATE_V 0x00000001U +#define PARL_IO_RX_REG_UPDATE_S 2 +/** PARL_IO_RX_TIMEOUT_EN : R/W; bitpos: [3]; default: 1; + * Write 1 to enable timeout count to generate error eof. + */ +#define PARL_IO_RX_TIMEOUT_EN (BIT(3)) +#define PARL_IO_RX_TIMEOUT_EN_M (PARL_IO_RX_TIMEOUT_EN_V << PARL_IO_RX_TIMEOUT_EN_S) +#define PARL_IO_RX_TIMEOUT_EN_V 0x00000001U +#define PARL_IO_RX_TIMEOUT_EN_S 3 +/** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [15:12]; default: 15; + * Configures rx external enable signal selection from 16 data lines. + */ +#define PARL_IO_RX_EXT_EN_SEL 0x0000000FU +#define PARL_IO_RX_EXT_EN_SEL_M (PARL_IO_RX_EXT_EN_SEL_V << PARL_IO_RX_EXT_EN_SEL_S) +#define PARL_IO_RX_EXT_EN_SEL_V 0x0000000FU +#define PARL_IO_RX_EXT_EN_SEL_S 12 +/** PARL_IO_RX_TIMEOUT_THRESHOLD : R/W; bitpos: [31:16]; default: 4095; + * Configures rx threshold of timeout counter. + */ +#define PARL_IO_RX_TIMEOUT_THRESHOLD 0x0000FFFFU +#define PARL_IO_RX_TIMEOUT_THRESHOLD_M (PARL_IO_RX_TIMEOUT_THRESHOLD_V << PARL_IO_RX_TIMEOUT_THRESHOLD_S) +#define PARL_IO_RX_TIMEOUT_THRESHOLD_V 0x0000FFFFU +#define PARL_IO_RX_TIMEOUT_THRESHOLD_S 16 + +/** PARL_IO_TX_CFG0_REG register + * Parallel TX module configuration register0. + */ +#define PARL_IO_TX_CFG0_REG (DR_REG_PARL_IO_BASE + 0x8) +/** PARL_IO_TX_BYTELEN : R/W; bitpos: [17:2]; default: 0; + * Configures tx sending data byte length. + */ +#define PARL_IO_TX_BYTELEN 0x0000FFFFU +#define PARL_IO_TX_BYTELEN_M (PARL_IO_TX_BYTELEN_V << PARL_IO_TX_BYTELEN_S) +#define PARL_IO_TX_BYTELEN_V 0x0000FFFFU +#define PARL_IO_TX_BYTELEN_S 2 +/** PARL_IO_TX_GATING_EN : R/W; bitpos: [18]; default: 0; + * Write 1 to enable output tx clock gating. + */ +#define PARL_IO_TX_GATING_EN (BIT(18)) +#define PARL_IO_TX_GATING_EN_M (PARL_IO_TX_GATING_EN_V << PARL_IO_TX_GATING_EN_S) +#define PARL_IO_TX_GATING_EN_V 0x00000001U +#define PARL_IO_TX_GATING_EN_S 18 +/** PARL_IO_TX_START : R/W; bitpos: [19]; default: 0; + * Write 1 to start tx global data output. + */ +#define PARL_IO_TX_START (BIT(19)) +#define PARL_IO_TX_START_M (PARL_IO_TX_START_V << PARL_IO_TX_START_S) +#define PARL_IO_TX_START_V 0x00000001U +#define PARL_IO_TX_START_S 19 +/** PARL_IO_TX_HW_VALID_EN : R/W; bitpos: [20]; default: 0; + * Write 1 to enable tx hardware data valid signal. + */ +#define PARL_IO_TX_HW_VALID_EN (BIT(20)) +#define PARL_IO_TX_HW_VALID_EN_M (PARL_IO_TX_HW_VALID_EN_V << PARL_IO_TX_HW_VALID_EN_S) +#define PARL_IO_TX_HW_VALID_EN_V 0x00000001U +#define PARL_IO_TX_HW_VALID_EN_S 20 +/** PARL_IO_TX_SMP_EDGE_SEL : R/W; bitpos: [25]; default: 0; + * Write 0 to enable sampling data on the rising edge of tx clock. Write 0 to enable + * sampling data on the falling edge of tx clock. + */ +#define PARL_IO_TX_SMP_EDGE_SEL (BIT(25)) +#define PARL_IO_TX_SMP_EDGE_SEL_M (PARL_IO_TX_SMP_EDGE_SEL_V << PARL_IO_TX_SMP_EDGE_SEL_S) +#define PARL_IO_TX_SMP_EDGE_SEL_V 0x00000001U +#define PARL_IO_TX_SMP_EDGE_SEL_S 25 +/** PARL_IO_TX_BIT_UNPACK_ORDER : R/W; bitpos: [26]; default: 0; + * Write 0 to unpack bits from 1byte from MSB when data bus width is 4/2/1 bits. Write + * 0 to unpack bits from 1byte from LSB when data bus width is 4/2/1 bits. + */ +#define PARL_IO_TX_BIT_UNPACK_ORDER (BIT(26)) +#define PARL_IO_TX_BIT_UNPACK_ORDER_M (PARL_IO_TX_BIT_UNPACK_ORDER_V << PARL_IO_TX_BIT_UNPACK_ORDER_S) +#define PARL_IO_TX_BIT_UNPACK_ORDER_V 0x00000001U +#define PARL_IO_TX_BIT_UNPACK_ORDER_S 26 +/** PARL_IO_TX_BUS_WID_SEL : R/W; bitpos: [29:27]; default: 0; + * Tx data bus width selection. + * 100: bus width is 1 bit + * 011: bus width is 2 bits + * 010: bus width is 4 bits + * 001: bus width is 8 bits + * 000: bus width is 16 bits + */ +#define PARL_IO_TX_BUS_WID_SEL 0x00000007U +#define PARL_IO_TX_BUS_WID_SEL_M (PARL_IO_TX_BUS_WID_SEL_V << PARL_IO_TX_BUS_WID_SEL_S) +#define PARL_IO_TX_BUS_WID_SEL_V 0x00000007U +#define PARL_IO_TX_BUS_WID_SEL_S 27 +/** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0; + * Write 1 to enable soft reset of async fifo in tx module. + */ +#define PARL_IO_TX_FIFO_SRST (BIT(30)) +#define PARL_IO_TX_FIFO_SRST_M (PARL_IO_TX_FIFO_SRST_V << PARL_IO_TX_FIFO_SRST_S) +#define PARL_IO_TX_FIFO_SRST_V 0x00000001U +#define PARL_IO_TX_FIFO_SRST_S 30 + +/** PARL_IO_TX_CFG1_REG register + * Parallel TX module configuration register1. + */ +#define PARL_IO_TX_CFG1_REG (DR_REG_PARL_IO_BASE + 0xc) +/** PARL_IO_TX_IDLE_VALUE : R/W; bitpos: [31:16]; default: 0; + * Configures data value on tx bus when IDLE state. + */ +#define PARL_IO_TX_IDLE_VALUE 0x0000FFFFU +#define PARL_IO_TX_IDLE_VALUE_M (PARL_IO_TX_IDLE_VALUE_V << PARL_IO_TX_IDLE_VALUE_S) +#define PARL_IO_TX_IDLE_VALUE_V 0x0000FFFFU +#define PARL_IO_TX_IDLE_VALUE_S 16 + +/** PARL_IO_ST_REG register + * Parallel IO module status register0. + */ +#define PARL_IO_ST_REG (DR_REG_PARL_IO_BASE + 0x10) +/** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0; + * Represents the status that tx is ready. + */ +#define PARL_IO_TX_READY (BIT(31)) +#define PARL_IO_TX_READY_M (PARL_IO_TX_READY_V << PARL_IO_TX_READY_S) +#define PARL_IO_TX_READY_V 0x00000001U +#define PARL_IO_TX_READY_S 31 + +/** PARL_IO_INT_ENA_REG register + * Parallel IO interrupt enable singal configuration register. + */ +#define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x14) +/** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable TX_FIFO_REMPTY_INTR. + */ +#define PARL_IO_TX_FIFO_REMPTY_INT_ENA (BIT(0)) +#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_M (PARL_IO_TX_FIFO_REMPTY_INT_ENA_V << PARL_IO_TX_FIFO_REMPTY_INT_ENA_S) +#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_V 0x00000001U +#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_S 0 +/** PARL_IO_RX_FIFO_WFULL_INT_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to enable RX_FIFO_WFULL_INTR. + */ +#define PARL_IO_RX_FIFO_WFULL_INT_ENA (BIT(1)) +#define PARL_IO_RX_FIFO_WFULL_INT_ENA_M (PARL_IO_RX_FIFO_WFULL_INT_ENA_V << PARL_IO_RX_FIFO_WFULL_INT_ENA_S) +#define PARL_IO_RX_FIFO_WFULL_INT_ENA_V 0x00000001U +#define PARL_IO_RX_FIFO_WFULL_INT_ENA_S 1 +/** PARL_IO_TX_EOF_INT_ENA : R/W; bitpos: [2]; default: 0; + * Write 1 to enable TX_EOF_INTR. + */ +#define PARL_IO_TX_EOF_INT_ENA (BIT(2)) +#define PARL_IO_TX_EOF_INT_ENA_M (PARL_IO_TX_EOF_INT_ENA_V << PARL_IO_TX_EOF_INT_ENA_S) +#define PARL_IO_TX_EOF_INT_ENA_V 0x00000001U +#define PARL_IO_TX_EOF_INT_ENA_S 2 + +/** PARL_IO_INT_RAW_REG register + * Parallel IO interrupt raw singal status register. + */ +#define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x18) +/** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of TX_FIFO_REMPTY_INTR. + */ +#define PARL_IO_TX_FIFO_REMPTY_INT_RAW (BIT(0)) +#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_M (PARL_IO_TX_FIFO_REMPTY_INT_RAW_V << PARL_IO_TX_FIFO_REMPTY_INT_RAW_S) +#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_V 0x00000001U +#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_S 0 +/** PARL_IO_RX_FIFO_WFULL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of RX_FIFO_WFULL_INTR. + */ +#define PARL_IO_RX_FIFO_WFULL_INT_RAW (BIT(1)) +#define PARL_IO_RX_FIFO_WFULL_INT_RAW_M (PARL_IO_RX_FIFO_WFULL_INT_RAW_V << PARL_IO_RX_FIFO_WFULL_INT_RAW_S) +#define PARL_IO_RX_FIFO_WFULL_INT_RAW_V 0x00000001U +#define PARL_IO_RX_FIFO_WFULL_INT_RAW_S 1 +/** PARL_IO_TX_EOF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of TX_EOF_INTR. + */ +#define PARL_IO_TX_EOF_INT_RAW (BIT(2)) +#define PARL_IO_TX_EOF_INT_RAW_M (PARL_IO_TX_EOF_INT_RAW_V << PARL_IO_TX_EOF_INT_RAW_S) +#define PARL_IO_TX_EOF_INT_RAW_V 0x00000001U +#define PARL_IO_TX_EOF_INT_RAW_S 2 + +/** PARL_IO_INT_ST_REG register + * Parallel IO interrupt singal status register. + */ +#define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x1c) +/** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status of TX_FIFO_REMPTY_INTR. + */ +#define PARL_IO_TX_FIFO_REMPTY_INT_ST (BIT(0)) +#define PARL_IO_TX_FIFO_REMPTY_INT_ST_M (PARL_IO_TX_FIFO_REMPTY_INT_ST_V << PARL_IO_TX_FIFO_REMPTY_INT_ST_S) +#define PARL_IO_TX_FIFO_REMPTY_INT_ST_V 0x00000001U +#define PARL_IO_TX_FIFO_REMPTY_INT_ST_S 0 +/** PARL_IO_RX_FIFO_WFULL_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status of RX_FIFO_WFULL_INTR. + */ +#define PARL_IO_RX_FIFO_WFULL_INT_ST (BIT(1)) +#define PARL_IO_RX_FIFO_WFULL_INT_ST_M (PARL_IO_RX_FIFO_WFULL_INT_ST_V << PARL_IO_RX_FIFO_WFULL_INT_ST_S) +#define PARL_IO_RX_FIFO_WFULL_INT_ST_V 0x00000001U +#define PARL_IO_RX_FIFO_WFULL_INT_ST_S 1 +/** PARL_IO_TX_EOF_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status of TX_EOF_INTR. + */ +#define PARL_IO_TX_EOF_INT_ST (BIT(2)) +#define PARL_IO_TX_EOF_INT_ST_M (PARL_IO_TX_EOF_INT_ST_V << PARL_IO_TX_EOF_INT_ST_S) +#define PARL_IO_TX_EOF_INT_ST_V 0x00000001U +#define PARL_IO_TX_EOF_INT_ST_S 2 + +/** PARL_IO_INT_CLR_REG register + * Parallel IO interrupt clear singal configuration register. + */ +#define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x20) +/** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear TX_FIFO_REMPTY_INTR. + */ +#define PARL_IO_TX_FIFO_REMPTY_INT_CLR (BIT(0)) +#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_M (PARL_IO_TX_FIFO_REMPTY_INT_CLR_V << PARL_IO_TX_FIFO_REMPTY_INT_CLR_S) +#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_V 0x00000001U +#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_S 0 +/** PARL_IO_RX_FIFO_WFULL_INT_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear RX_FIFO_WFULL_INTR. + */ +#define PARL_IO_RX_FIFO_WFULL_INT_CLR (BIT(1)) +#define PARL_IO_RX_FIFO_WFULL_INT_CLR_M (PARL_IO_RX_FIFO_WFULL_INT_CLR_V << PARL_IO_RX_FIFO_WFULL_INT_CLR_S) +#define PARL_IO_RX_FIFO_WFULL_INT_CLR_V 0x00000001U +#define PARL_IO_RX_FIFO_WFULL_INT_CLR_S 1 +/** PARL_IO_TX_EOF_INT_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear TX_EOF_INTR. + */ +#define PARL_IO_TX_EOF_INT_CLR (BIT(2)) +#define PARL_IO_TX_EOF_INT_CLR_M (PARL_IO_TX_EOF_INT_CLR_V << PARL_IO_TX_EOF_INT_CLR_S) +#define PARL_IO_TX_EOF_INT_CLR_V 0x00000001U +#define PARL_IO_TX_EOF_INT_CLR_S 2 + +/** PARL_IO_CLK_REG register + * Parallel IO clk configuration register + */ +#define PARL_IO_CLK_REG (DR_REG_PARL_IO_BASE + 0x120) +/** PARL_IO_CLK_EN : R/W; bitpos: [0]; default: 0; + * Force clock on for this register file + */ +#define PARL_IO_CLK_EN (BIT(0)) +#define PARL_IO_CLK_EN_M (PARL_IO_CLK_EN_V << PARL_IO_CLK_EN_S) +#define PARL_IO_CLK_EN_V 0x00000001U +#define PARL_IO_CLK_EN_S 0 + +/** PARL_IO_VERSION_REG register + * Version register. + */ +#define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc) +/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 35660352; + * Version of this register file + */ +#define PARL_IO_DATE 0x0FFFFFFFU +#define PARL_IO_DATE_M (PARL_IO_DATE_V << PARL_IO_DATE_S) +#define PARL_IO_DATE_V 0x0FFFFFFFU +#define PARL_IO_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/parl_io_struct.h b/components/soc/esp32c6/include/soc/parl_io_struct.h new file mode 100644 index 0000000000..816a7de3ef --- /dev/null +++ b/components/soc/esp32c6/include/soc/parl_io_struct.h @@ -0,0 +1,360 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: PARL_IO RX Configuration0 */ +/** Type of rx_cfg0 register + * Parallel RX module configuration register0. + */ +typedef union { + struct { + /** rx_eof_gen_sel : R/W; bitpos: [0]; default: 0; + * Write 0 to select eof generated manchnism by configured data byte length. Write 1 + * to select eof generated manchnism by external enable signal. + */ + uint32_t rx_eof_gen_sel:1; + /** rx_start : R/W; bitpos: [1]; default: 0; + * Write 1 to start rx global data sampling. + */ + uint32_t rx_start:1; + /** rx_data_bytelen : R/W; bitpos: [17:2]; default: 0; + * Configures rx receieved data byte length. + */ + uint32_t rx_data_bytelen:16; + /** rx_sw_en : R/W; bitpos: [18]; default: 0; + * Write 1 to enable software data sampling. + */ + uint32_t rx_sw_en:1; + /** rx_pulse_submode_sel : R/W; bitpos: [22:19]; default: 0; + * Pulse submode selection. + * 0000: positive pulse start(data bit included) && positive pulse end(data bit + * included) + * 0001: positive pulse start(data bit included) && positive pulse end (data bit + * excluded) + * 0010: positive pulse start(data bit excluded) && positive pulse end (data bit + * included) + * 0011: positive pulse start(data bit excluded) && positive pulse end (data bit + * excluded) + * 0100: positive pulse start(data bit included) && length end + * 0101: positive pulse start(data bit excluded) && length end + * 0110: negative pulse start(data bit included) && negative pulse end(data bit + * included) + * 0111: negative pulse start(data bit included) && negative pulse end (data bit + * excluded) + * 1000: negative pulse start(data bit excluded) && negative pulse end (data bit + * included) + * 1001: negative pulse start(data bit excluded) && negative pulse end (data bit + * excluded) + * 1010: negative pulse start(data bit included) && length end + * 1011: negative pulse start(data bit excluded) && length end + */ + uint32_t rx_pulse_submode_sel:4; + /** rx_level_submode_sel : R/W; bitpos: [23]; default: 0; + * Write 0 to sample data at high level of external enable signal. Write 1 to sample + * data at low level of external enable signal. + */ + uint32_t rx_level_submode_sel:1; + /** rx_smp_mode_sel : R/W; bitpos: [25:24]; default: 0; + * Rx data sampling mode selection. + * 000: external level enable mode + * 001: external pulse enable mode + * 010: internal software enable mode + */ + uint32_t rx_smp_mode_sel:2; + /** rx_clk_edge_sel : R/W; bitpos: [26]; default: 0; + * Write 0 to enable sampling data on the rising edge of rx clock. Write 0 to enable + * sampling data on the falling edge of rx clock. + */ + uint32_t rx_clk_edge_sel:1; + /** rx_bit_pack_order : R/W; bitpos: [27]; default: 0; + * Write 0 to pack bits into 1byte from MSB when data bus width is 4/2/1 bits. Write 0 + * to pack bits into 1byte from LSB when data bus width is 4/2/1 bits. + */ + uint32_t rx_bit_pack_order:1; + /** rx_bus_wid_sel : R/W; bitpos: [30:28]; default: 0; + * Rx data bus width selection. + * 100: bus width is 1 bit + * 011: bus width is 2 bits + * 010: bus width is 4 bits + * 001: bus width is 8 bits + * 000: bus width is 16 bits + */ + uint32_t rx_bus_wid_sel:3; + /** rx_fifo_srst : R/W; bitpos: [31]; default: 0; + * Write 1 to enable soft reset of async fifo in rx module. + */ + uint32_t rx_fifo_srst:1; + }; + uint32_t val; +} parl_io_rx_cfg0_reg_t; + + +/** Group: PARL_IO RX Configuration1 */ +/** Type of rx_cfg1 register + * Parallel RX module configuration register1. + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** rx_reg_update : WT; bitpos: [2]; default: 0; + * Write 1 to update rx register configuration signals. + */ + uint32_t rx_reg_update:1; + /** rx_timeout_en : R/W; bitpos: [3]; default: 1; + * Write 1 to enable timeout count to generate error eof. + */ + uint32_t rx_timeout_en:1; + uint32_t reserved_4:8; + /** rx_ext_en_sel : R/W; bitpos: [15:12]; default: 15; + * Configures rx external enable signal selection from 16 data lines. + */ + uint32_t rx_ext_en_sel:4; + /** rx_timeout_threshold : R/W; bitpos: [31:16]; default: 4095; + * Configures rx threshold of timeout counter. + */ + uint32_t rx_timeout_threshold:16; + }; + uint32_t val; +} parl_io_rx_cfg1_reg_t; + + +/** Group: PARL_IO TX Configuration0 */ +/** Type of tx_cfg0 register + * Parallel TX module configuration register0. + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** tx_bytelen : R/W; bitpos: [17:2]; default: 0; + * Configures tx sending data byte length. + */ + uint32_t tx_bytelen:16; + /** tx_gating_en : R/W; bitpos: [18]; default: 0; + * Write 1 to enable output tx clock gating. + */ + uint32_t tx_gating_en:1; + /** tx_start : R/W; bitpos: [19]; default: 0; + * Write 1 to start tx global data output. + */ + uint32_t tx_start:1; + /** tx_hw_valid_en : R/W; bitpos: [20]; default: 0; + * Write 1 to enable tx hardware data valid signal. + */ + uint32_t tx_hw_valid_en:1; + uint32_t reserved_21:4; + /** tx_smp_edge_sel : R/W; bitpos: [25]; default: 0; + * Write 0 to enable sampling data on the rising edge of tx clock. Write 0 to enable + * sampling data on the falling edge of tx clock. + */ + uint32_t tx_smp_edge_sel:1; + /** tx_bit_unpack_order : R/W; bitpos: [26]; default: 0; + * Write 0 to unpack bits from 1byte from MSB when data bus width is 4/2/1 bits. Write + * 0 to unpack bits from 1byte from LSB when data bus width is 4/2/1 bits. + */ + uint32_t tx_bit_unpack_order:1; + /** tx_bus_wid_sel : R/W; bitpos: [29:27]; default: 0; + * Tx data bus width selection. + * 100: bus width is 1 bit + * 011: bus width is 2 bits + * 010: bus width is 4 bits + * 001: bus width is 8 bits + * 000: bus width is 16 bits + */ + uint32_t tx_bus_wid_sel:3; + /** tx_fifo_srst : R/W; bitpos: [30]; default: 0; + * Write 1 to enable soft reset of async fifo in tx module. + */ + uint32_t tx_fifo_srst:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} parl_io_tx_cfg0_reg_t; + + +/** Group: PARL_IO TX Configuration1 */ +/** Type of tx_cfg1 register + * Parallel TX module configuration register1. + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** tx_idle_value : R/W; bitpos: [31:16]; default: 0; + * Configures data value on tx bus when IDLE state. + */ + uint32_t tx_idle_value:16; + }; + uint32_t val; +} parl_io_tx_cfg1_reg_t; + + +/** Group: PARL_IO TX Status0 */ +/** Type of st register + * Parallel IO module status register0. + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** tx_ready : RO; bitpos: [31]; default: 0; + * Represents the status that tx is ready. + */ + uint32_t tx_ready:1; + }; + uint32_t val; +} parl_io_st_reg_t; + + +/** Group: PARL_IO Interrupt Configuration and Status */ +/** Type of int_ena register + * Parallel IO interrupt enable singal configuration register. + */ +typedef union { + struct { + /** tx_fifo_rempty_int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable TX_FIFO_REMPTY_INTR. + */ + uint32_t tx_fifo_rempty_int_ena:1; + /** rx_fifo_wfull_int_ena : R/W; bitpos: [1]; default: 0; + * Write 1 to enable RX_FIFO_WFULL_INTR. + */ + uint32_t rx_fifo_wfull_int_ena:1; + /** tx_eof_int_ena : R/W; bitpos: [2]; default: 0; + * Write 1 to enable TX_EOF_INTR. + */ + uint32_t tx_eof_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} parl_io_int_ena_reg_t; + +/** Type of int_raw register + * Parallel IO interrupt raw singal status register. + */ +typedef union { + struct { + /** tx_fifo_rempty_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of TX_FIFO_REMPTY_INTR. + */ + uint32_t tx_fifo_rempty_int_raw:1; + /** rx_fifo_wfull_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of RX_FIFO_WFULL_INTR. + */ + uint32_t rx_fifo_wfull_int_raw:1; + /** tx_eof_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of TX_EOF_INTR. + */ + uint32_t tx_eof_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} parl_io_int_raw_reg_t; + +/** Type of int_st register + * Parallel IO interrupt singal status register. + */ +typedef union { + struct { + /** tx_fifo_rempty_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status of TX_FIFO_REMPTY_INTR. + */ + uint32_t tx_fifo_rempty_int_st:1; + /** rx_fifo_wfull_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status of RX_FIFO_WFULL_INTR. + */ + uint32_t rx_fifo_wfull_int_st:1; + /** tx_eof_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status of TX_EOF_INTR. + */ + uint32_t tx_eof_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} parl_io_int_st_reg_t; + +/** Type of int_clr register + * Parallel IO interrupt clear singal configuration register. + */ +typedef union { + struct { + /** tx_fifo_rempty_int_clr : WT; bitpos: [0]; default: 0; + * Write 1 to clear TX_FIFO_REMPTY_INTR. + */ + uint32_t tx_fifo_rempty_int_clr:1; + /** rx_fifo_wfull_int_clr : WT; bitpos: [1]; default: 0; + * Write 1 to clear RX_FIFO_WFULL_INTR. + */ + uint32_t rx_fifo_wfull_int_clr:1; + /** tx_eof_int_clr : WT; bitpos: [2]; default: 0; + * Write 1 to clear TX_EOF_INTR. + */ + uint32_t tx_eof_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} parl_io_int_clr_reg_t; + + +/** Group: PARL_IO Clock Gating Configuration */ +/** Type of clk register + * Parallel IO clk configuration register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Force clock on for this register file + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} parl_io_clk_reg_t; + + +/** Group: PARL_IO Version Register */ +/** Type of version register + * Version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35660352; + * Version of this register file + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} parl_io_version_reg_t; + + +typedef struct parl_io_dev_t { + volatile parl_io_rx_cfg0_reg_t rx_cfg0; + volatile parl_io_rx_cfg1_reg_t rx_cfg1; + volatile parl_io_tx_cfg0_reg_t tx_cfg0; + volatile parl_io_tx_cfg1_reg_t tx_cfg1; + volatile parl_io_st_reg_t st; + volatile parl_io_int_ena_reg_t int_ena; + volatile parl_io_int_raw_reg_t int_raw; + volatile parl_io_int_st_reg_t int_st; + volatile parl_io_int_clr_reg_t int_clr; + uint32_t reserved_024[63]; + volatile parl_io_clk_reg_t clk; + uint32_t reserved_124[182]; + volatile parl_io_version_reg_t version; +} parl_io_dev_t; + +extern parl_io_dev_t PARL_IO; + +#ifndef __cplusplus +_Static_assert(sizeof(parl_io_dev_t) == 0x400, "Invalid size of parl_io_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/pau_reg.h b/components/soc/esp32c6/include/soc/pau_reg.h new file mode 100644 index 0000000000..a2f7ad9a89 --- /dev/null +++ b/components/soc/esp32c6/include/soc/pau_reg.h @@ -0,0 +1,356 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PAU_REGDMA_CONF_REG register + * Peri backup control register + */ +#define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0) +/** PAU_FLOW_ERR : RO; bitpos: [2:0]; default: 0; + * backup error type + */ +#define PAU_FLOW_ERR 0x00000007U +#define PAU_FLOW_ERR_M (PAU_FLOW_ERR_V << PAU_FLOW_ERR_S) +#define PAU_FLOW_ERR_V 0x00000007U +#define PAU_FLOW_ERR_S 0 +/** PAU_START : WT; bitpos: [3]; default: 0; + * backup start signal + */ +#define PAU_START (BIT(3)) +#define PAU_START_M (PAU_START_V << PAU_START_S) +#define PAU_START_V 0x00000001U +#define PAU_START_S 3 +/** PAU_TO_MEM : R/W; bitpos: [4]; default: 0; + * backup direction(reg to mem / mem to reg) + */ +#define PAU_TO_MEM (BIT(4)) +#define PAU_TO_MEM_M (PAU_TO_MEM_V << PAU_TO_MEM_S) +#define PAU_TO_MEM_V 0x00000001U +#define PAU_TO_MEM_S 4 +/** PAU_LINK_SEL : R/W; bitpos: [6:5]; default: 0; + * Link select + */ +#define PAU_LINK_SEL 0x00000003U +#define PAU_LINK_SEL_M (PAU_LINK_SEL_V << PAU_LINK_SEL_S) +#define PAU_LINK_SEL_V 0x00000003U +#define PAU_LINK_SEL_S 5 +/** PAU_START_MAC : WT; bitpos: [7]; default: 0; + * mac sw backup start signal + */ +#define PAU_START_MAC (BIT(7)) +#define PAU_START_MAC_M (PAU_START_MAC_V << PAU_START_MAC_S) +#define PAU_START_MAC_V 0x00000001U +#define PAU_START_MAC_S 7 +/** PAU_TO_MEM_MAC : R/W; bitpos: [8]; default: 0; + * mac sw backup direction(reg to mem / mem to reg) + */ +#define PAU_TO_MEM_MAC (BIT(8)) +#define PAU_TO_MEM_MAC_M (PAU_TO_MEM_MAC_V << PAU_TO_MEM_MAC_S) +#define PAU_TO_MEM_MAC_V 0x00000001U +#define PAU_TO_MEM_MAC_S 8 +/** PAU_SEL_MAC : R/W; bitpos: [9]; default: 0; + * mac hw/sw select + */ +#define PAU_SEL_MAC (BIT(9)) +#define PAU_SEL_MAC_M (PAU_SEL_MAC_V << PAU_SEL_MAC_S) +#define PAU_SEL_MAC_V 0x00000001U +#define PAU_SEL_MAC_S 9 + +/** PAU_REGDMA_CLK_CONF_REG register + * Clock control register + */ +#define PAU_REGDMA_CLK_CONF_REG (DR_REG_PAU_BASE + 0x4) +/** PAU_CLK_EN : R/W; bitpos: [0]; default: 0; + * clock enable + */ +#define PAU_CLK_EN (BIT(0)) +#define PAU_CLK_EN_M (PAU_CLK_EN_V << PAU_CLK_EN_S) +#define PAU_CLK_EN_V 0x00000001U +#define PAU_CLK_EN_S 0 + +/** PAU_REGDMA_ETM_CTRL_REG register + * ETM start ctrl reg + */ +#define PAU_REGDMA_ETM_CTRL_REG (DR_REG_PAU_BASE + 0x8) +/** PAU_ETM_START_0 : WT; bitpos: [0]; default: 0; + * etm_start_0 reg + */ +#define PAU_ETM_START_0 (BIT(0)) +#define PAU_ETM_START_0_M (PAU_ETM_START_0_V << PAU_ETM_START_0_S) +#define PAU_ETM_START_0_V 0x00000001U +#define PAU_ETM_START_0_S 0 +/** PAU_ETM_START_1 : WT; bitpos: [1]; default: 0; + * etm_start_1 reg + */ +#define PAU_ETM_START_1 (BIT(1)) +#define PAU_ETM_START_1_M (PAU_ETM_START_1_V << PAU_ETM_START_1_S) +#define PAU_ETM_START_1_V 0x00000001U +#define PAU_ETM_START_1_S 1 +/** PAU_ETM_START_2 : WT; bitpos: [2]; default: 0; + * etm_start_2 reg + */ +#define PAU_ETM_START_2 (BIT(2)) +#define PAU_ETM_START_2_M (PAU_ETM_START_2_V << PAU_ETM_START_2_S) +#define PAU_ETM_START_2_V 0x00000001U +#define PAU_ETM_START_2_S 2 +/** PAU_ETM_START_3 : WT; bitpos: [3]; default: 0; + * etm_start_3 reg + */ +#define PAU_ETM_START_3 (BIT(3)) +#define PAU_ETM_START_3_M (PAU_ETM_START_3_V << PAU_ETM_START_3_S) +#define PAU_ETM_START_3_V 0x00000001U +#define PAU_ETM_START_3_S 3 + +/** PAU_REGDMA_LINK_0_ADDR_REG register + * link_0_addr + */ +#define PAU_REGDMA_LINK_0_ADDR_REG (DR_REG_PAU_BASE + 0xc) +/** PAU_LINK_ADDR_0 : R/W; bitpos: [31:0]; default: 0; + * link_0_addr reg + */ +#define PAU_LINK_ADDR_0 0xFFFFFFFFU +#define PAU_LINK_ADDR_0_M (PAU_LINK_ADDR_0_V << PAU_LINK_ADDR_0_S) +#define PAU_LINK_ADDR_0_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_0_S 0 + +/** PAU_REGDMA_LINK_1_ADDR_REG register + * Link_1_addr + */ +#define PAU_REGDMA_LINK_1_ADDR_REG (DR_REG_PAU_BASE + 0x10) +/** PAU_LINK_ADDR_1 : R/W; bitpos: [31:0]; default: 0; + * Link_1_addr reg + */ +#define PAU_LINK_ADDR_1 0xFFFFFFFFU +#define PAU_LINK_ADDR_1_M (PAU_LINK_ADDR_1_V << PAU_LINK_ADDR_1_S) +#define PAU_LINK_ADDR_1_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_1_S 0 + +/** PAU_REGDMA_LINK_2_ADDR_REG register + * Link_2_addr + */ +#define PAU_REGDMA_LINK_2_ADDR_REG (DR_REG_PAU_BASE + 0x14) +/** PAU_LINK_ADDR_2 : R/W; bitpos: [31:0]; default: 0; + * Link_2_addr reg + */ +#define PAU_LINK_ADDR_2 0xFFFFFFFFU +#define PAU_LINK_ADDR_2_M (PAU_LINK_ADDR_2_V << PAU_LINK_ADDR_2_S) +#define PAU_LINK_ADDR_2_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_2_S 0 + +/** PAU_REGDMA_LINK_3_ADDR_REG register + * Link_3_addr + */ +#define PAU_REGDMA_LINK_3_ADDR_REG (DR_REG_PAU_BASE + 0x18) +/** PAU_LINK_ADDR_3 : R/W; bitpos: [31:0]; default: 0; + * Link_3_addr reg + */ +#define PAU_LINK_ADDR_3 0xFFFFFFFFU +#define PAU_LINK_ADDR_3_M (PAU_LINK_ADDR_3_V << PAU_LINK_ADDR_3_S) +#define PAU_LINK_ADDR_3_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_3_S 0 + +/** PAU_REGDMA_LINK_MAC_ADDR_REG register + * Link_mac_addr + */ +#define PAU_REGDMA_LINK_MAC_ADDR_REG (DR_REG_PAU_BASE + 0x1c) +/** PAU_LINK_ADDR_MAC : R/W; bitpos: [31:0]; default: 0; + * Link_mac_addr reg + */ +#define PAU_LINK_ADDR_MAC 0xFFFFFFFFU +#define PAU_LINK_ADDR_MAC_M (PAU_LINK_ADDR_MAC_V << PAU_LINK_ADDR_MAC_S) +#define PAU_LINK_ADDR_MAC_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_MAC_S 0 + +/** PAU_REGDMA_CURRENT_LINK_ADDR_REG register + * current link addr + */ +#define PAU_REGDMA_CURRENT_LINK_ADDR_REG (DR_REG_PAU_BASE + 0x20) +/** PAU_CURRENT_LINK_ADDR : RO; bitpos: [31:0]; default: 0; + * current link addr reg + */ +#define PAU_CURRENT_LINK_ADDR 0xFFFFFFFFU +#define PAU_CURRENT_LINK_ADDR_M (PAU_CURRENT_LINK_ADDR_V << PAU_CURRENT_LINK_ADDR_S) +#define PAU_CURRENT_LINK_ADDR_V 0xFFFFFFFFU +#define PAU_CURRENT_LINK_ADDR_S 0 + +/** PAU_REGDMA_BACKUP_ADDR_REG register + * Backup addr + */ +#define PAU_REGDMA_BACKUP_ADDR_REG (DR_REG_PAU_BASE + 0x24) +/** PAU_BACKUP_ADDR : RO; bitpos: [31:0]; default: 0; + * backup addr reg + */ +#define PAU_BACKUP_ADDR 0xFFFFFFFFU +#define PAU_BACKUP_ADDR_M (PAU_BACKUP_ADDR_V << PAU_BACKUP_ADDR_S) +#define PAU_BACKUP_ADDR_V 0xFFFFFFFFU +#define PAU_BACKUP_ADDR_S 0 + +/** PAU_REGDMA_MEM_ADDR_REG register + * mem addr + */ +#define PAU_REGDMA_MEM_ADDR_REG (DR_REG_PAU_BASE + 0x28) +/** PAU_MEM_ADDR : RO; bitpos: [31:0]; default: 0; + * mem addr reg + */ +#define PAU_MEM_ADDR 0xFFFFFFFFU +#define PAU_MEM_ADDR_M (PAU_MEM_ADDR_V << PAU_MEM_ADDR_S) +#define PAU_MEM_ADDR_V 0xFFFFFFFFU +#define PAU_MEM_ADDR_S 0 + +/** PAU_REGDMA_BKP_CONF_REG register + * backup config + */ +#define PAU_REGDMA_BKP_CONF_REG (DR_REG_PAU_BASE + 0x2c) +/** PAU_READ_INTERVAL : R/W; bitpos: [6:0]; default: 32; + * Link read_interval + */ +#define PAU_READ_INTERVAL 0x0000007FU +#define PAU_READ_INTERVAL_M (PAU_READ_INTERVAL_V << PAU_READ_INTERVAL_S) +#define PAU_READ_INTERVAL_V 0x0000007FU +#define PAU_READ_INTERVAL_S 0 +/** PAU_LINK_TOUT_THRES : R/W; bitpos: [16:7]; default: 50; + * link wait timeout threshold + */ +#define PAU_LINK_TOUT_THRES 0x000003FFU +#define PAU_LINK_TOUT_THRES_M (PAU_LINK_TOUT_THRES_V << PAU_LINK_TOUT_THRES_S) +#define PAU_LINK_TOUT_THRES_V 0x000003FFU +#define PAU_LINK_TOUT_THRES_S 7 +/** PAU_BURST_LIMIT : R/W; bitpos: [21:17]; default: 8; + * burst limit + */ +#define PAU_BURST_LIMIT 0x0000001FU +#define PAU_BURST_LIMIT_M (PAU_BURST_LIMIT_V << PAU_BURST_LIMIT_S) +#define PAU_BURST_LIMIT_V 0x0000001FU +#define PAU_BURST_LIMIT_S 17 +/** PAU_BACKUP_TOUT_THRES : R/W; bitpos: [31:22]; default: 500; + * Backup timeout threshold + */ +#define PAU_BACKUP_TOUT_THRES 0x000003FFU +#define PAU_BACKUP_TOUT_THRES_M (PAU_BACKUP_TOUT_THRES_V << PAU_BACKUP_TOUT_THRES_S) +#define PAU_BACKUP_TOUT_THRES_V 0x000003FFU +#define PAU_BACKUP_TOUT_THRES_S 22 + +/** PAU_RETENTION_LINK_BASE_REG register + * retention dma link base + */ +#define PAU_RETENTION_LINK_BASE_REG (DR_REG_PAU_BASE + 0x30) +/** PAU_LINK_BASE_ADDR : R/W; bitpos: [26:0]; default: 0; + * retention dma link base + */ +#define PAU_LINK_BASE_ADDR 0x07FFFFFFU +#define PAU_LINK_BASE_ADDR_M (PAU_LINK_BASE_ADDR_V << PAU_LINK_BASE_ADDR_S) +#define PAU_LINK_BASE_ADDR_V 0x07FFFFFFU +#define PAU_LINK_BASE_ADDR_S 0 + +/** PAU_RETENTION_CFG_REG register + * retention_cfg + */ +#define PAU_RETENTION_CFG_REG (DR_REG_PAU_BASE + 0x34) +/** PAU_RET_INV_CFG : R/W; bitpos: [31:0]; default: 4294967295; + * retention inv scan out + */ +#define PAU_RET_INV_CFG 0xFFFFFFFFU +#define PAU_RET_INV_CFG_M (PAU_RET_INV_CFG_V << PAU_RET_INV_CFG_S) +#define PAU_RET_INV_CFG_V 0xFFFFFFFFU +#define PAU_RET_INV_CFG_S 0 + +/** PAU_INT_ENA_REG register + * Read only register for error and done + */ +#define PAU_INT_ENA_REG (DR_REG_PAU_BASE + 0x38) +/** PAU_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_ENA (BIT(0)) +#define PAU_DONE_INT_ENA_M (PAU_DONE_INT_ENA_V << PAU_DONE_INT_ENA_S) +#define PAU_DONE_INT_ENA_V 0x00000001U +#define PAU_DONE_INT_ENA_S 0 +/** PAU_ERROR_INT_ENA : R/W; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_ENA (BIT(1)) +#define PAU_ERROR_INT_ENA_M (PAU_ERROR_INT_ENA_V << PAU_ERROR_INT_ENA_S) +#define PAU_ERROR_INT_ENA_V 0x00000001U +#define PAU_ERROR_INT_ENA_S 1 + +/** PAU_INT_RAW_REG register + * Read only register for error and done + */ +#define PAU_INT_RAW_REG (DR_REG_PAU_BASE + 0x3c) +/** PAU_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_RAW (BIT(0)) +#define PAU_DONE_INT_RAW_M (PAU_DONE_INT_RAW_V << PAU_DONE_INT_RAW_S) +#define PAU_DONE_INT_RAW_V 0x00000001U +#define PAU_DONE_INT_RAW_S 0 +/** PAU_ERROR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_RAW (BIT(1)) +#define PAU_ERROR_INT_RAW_M (PAU_ERROR_INT_RAW_V << PAU_ERROR_INT_RAW_S) +#define PAU_ERROR_INT_RAW_V 0x00000001U +#define PAU_ERROR_INT_RAW_S 1 + +/** PAU_INT_CLR_REG register + * Read only register for error and done + */ +#define PAU_INT_CLR_REG (DR_REG_PAU_BASE + 0x40) +/** PAU_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_CLR (BIT(0)) +#define PAU_DONE_INT_CLR_M (PAU_DONE_INT_CLR_V << PAU_DONE_INT_CLR_S) +#define PAU_DONE_INT_CLR_V 0x00000001U +#define PAU_DONE_INT_CLR_S 0 +/** PAU_ERROR_INT_CLR : WT; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_CLR (BIT(1)) +#define PAU_ERROR_INT_CLR_M (PAU_ERROR_INT_CLR_V << PAU_ERROR_INT_CLR_S) +#define PAU_ERROR_INT_CLR_V 0x00000001U +#define PAU_ERROR_INT_CLR_S 1 + +/** PAU_INT_ST_REG register + * Read only register for error and done + */ +#define PAU_INT_ST_REG (DR_REG_PAU_BASE + 0x44) +/** PAU_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_ST (BIT(0)) +#define PAU_DONE_INT_ST_M (PAU_DONE_INT_ST_V << PAU_DONE_INT_ST_S) +#define PAU_DONE_INT_ST_V 0x00000001U +#define PAU_DONE_INT_ST_S 0 +/** PAU_ERROR_INT_ST : RO; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_ST (BIT(1)) +#define PAU_ERROR_INT_ST_M (PAU_ERROR_INT_ST_V << PAU_ERROR_INT_ST_S) +#define PAU_ERROR_INT_ST_V 0x00000001U +#define PAU_ERROR_INT_ST_S 1 + +/** PAU_DATE_REG register + * Date register. + */ +#define PAU_DATE_REG (DR_REG_PAU_BASE + 0x3fc) +/** PAU_DATE : R/W; bitpos: [27:0]; default: 35663984; + * REGDMA date information/ REGDMA version information. + */ +#define PAU_DATE 0x0FFFFFFFU +#define PAU_DATE_M (PAU_DATE_V << PAU_DATE_S) +#define PAU_DATE_V 0x0FFFFFFFU +#define PAU_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/pau_struct.h b/components/soc/esp32c6/include/soc/pau_struct.h new file mode 100644 index 0000000000..ae1435d506 --- /dev/null +++ b/components/soc/esp32c6/include/soc/pau_struct.h @@ -0,0 +1,368 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of regdma_conf register + * Peri backup control register + */ +typedef union { + struct { + /** flow_err : RO; bitpos: [2:0]; default: 0; + * backup error type + */ + uint32_t flow_err:3; + /** start : WT; bitpos: [3]; default: 0; + * backup start signal + */ + uint32_t start:1; + /** to_mem : R/W; bitpos: [4]; default: 0; + * backup direction(reg to mem / mem to reg) + */ + uint32_t to_mem:1; + /** link_sel : R/W; bitpos: [6:5]; default: 0; + * Link select + */ + uint32_t link_sel:2; + /** start_mac : WT; bitpos: [7]; default: 0; + * mac sw backup start signal + */ + uint32_t start_mac:1; + /** to_mem_mac : R/W; bitpos: [8]; default: 0; + * mac sw backup direction(reg to mem / mem to reg) + */ + uint32_t to_mem_mac:1; + /** sel_mac : R/W; bitpos: [9]; default: 0; + * mac hw/sw select + */ + uint32_t sel_mac:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} pau_regdma_conf_reg_t; + +/** Type of regdma_clk_conf register + * Clock control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * clock enable + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} pau_regdma_clk_conf_reg_t; + +/** Type of regdma_etm_ctrl register + * ETM start ctrl reg + */ +typedef union { + struct { + /** etm_start_0 : WT; bitpos: [0]; default: 0; + * etm_start_0 reg + */ + uint32_t etm_start_0:1; + /** etm_start_1 : WT; bitpos: [1]; default: 0; + * etm_start_1 reg + */ + uint32_t etm_start_1:1; + /** etm_start_2 : WT; bitpos: [2]; default: 0; + * etm_start_2 reg + */ + uint32_t etm_start_2:1; + /** etm_start_3 : WT; bitpos: [3]; default: 0; + * etm_start_3 reg + */ + uint32_t etm_start_3:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pau_regdma_etm_ctrl_reg_t; + +/** Type of regdma_link_0_addr register + * link_0_addr + */ +typedef union { + struct { + /** link_addr_0 : R/W; bitpos: [31:0]; default: 0; + * link_0_addr reg + */ + uint32_t link_addr_0:32; + }; + uint32_t val; +} pau_regdma_link_0_addr_reg_t; + +/** Type of regdma_link_1_addr register + * Link_1_addr + */ +typedef union { + struct { + /** link_addr_1 : R/W; bitpos: [31:0]; default: 0; + * Link_1_addr reg + */ + uint32_t link_addr_1:32; + }; + uint32_t val; +} pau_regdma_link_1_addr_reg_t; + +/** Type of regdma_link_2_addr register + * Link_2_addr + */ +typedef union { + struct { + /** link_addr_2 : R/W; bitpos: [31:0]; default: 0; + * Link_2_addr reg + */ + uint32_t link_addr_2:32; + }; + uint32_t val; +} pau_regdma_link_2_addr_reg_t; + +/** Type of regdma_link_3_addr register + * Link_3_addr + */ +typedef union { + struct { + /** link_addr_3 : R/W; bitpos: [31:0]; default: 0; + * Link_3_addr reg + */ + uint32_t link_addr_3:32; + }; + uint32_t val; +} pau_regdma_link_3_addr_reg_t; + +/** Type of regdma_link_mac_addr register + * Link_mac_addr + */ +typedef union { + struct { + /** link_addr_mac : R/W; bitpos: [31:0]; default: 0; + * Link_mac_addr reg + */ + uint32_t link_addr_mac:32; + }; + uint32_t val; +} pau_regdma_link_mac_addr_reg_t; + +/** Type of regdma_current_link_addr register + * current link addr + */ +typedef union { + struct { + /** current_link_addr : RO; bitpos: [31:0]; default: 0; + * current link addr reg + */ + uint32_t current_link_addr:32; + }; + uint32_t val; +} pau_regdma_current_link_addr_reg_t; + +/** Type of regdma_backup_addr register + * Backup addr + */ +typedef union { + struct { + /** backup_addr : RO; bitpos: [31:0]; default: 0; + * backup addr reg + */ + uint32_t backup_addr:32; + }; + uint32_t val; +} pau_regdma_backup_addr_reg_t; + +/** Type of regdma_mem_addr register + * mem addr + */ +typedef union { + struct { + /** mem_addr : RO; bitpos: [31:0]; default: 0; + * mem addr reg + */ + uint32_t mem_addr:32; + }; + uint32_t val; +} pau_regdma_mem_addr_reg_t; + +/** Type of regdma_bkp_conf register + * backup config + */ +typedef union { + struct { + /** read_interval : R/W; bitpos: [6:0]; default: 32; + * Link read_interval + */ + uint32_t read_interval:7; + /** link_tout_thres : R/W; bitpos: [16:7]; default: 50; + * link wait timeout threshold + */ + uint32_t link_tout_thres:10; + /** burst_limit : R/W; bitpos: [21:17]; default: 8; + * burst limit + */ + uint32_t burst_limit:5; + /** backup_tout_thres : R/W; bitpos: [31:22]; default: 500; + * Backup timeout threshold + */ + uint32_t backup_tout_thres:10; + }; + uint32_t val; +} pau_regdma_bkp_conf_reg_t; + +/** Type of retention_link_base register + * retention dma link base + */ +typedef union { + struct { + /** link_base_addr : R/W; bitpos: [26:0]; default: 0; + * retention dma link base + */ + uint32_t link_base_addr:27; + uint32_t reserved_27:5; + }; + uint32_t val; +} pau_retention_link_base_reg_t; + +/** Type of retention_cfg register + * retention_cfg + */ +typedef union { + struct { + /** ret_inv_cfg : R/W; bitpos: [31:0]; default: 4294967295; + * retention inv scan out + */ + uint32_t ret_inv_cfg:32; + }; + uint32_t val; +} pau_retention_cfg_reg_t; + +/** Type of int_ena register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_ena : R/W; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_ena:1; + /** error_int_ena : R/W; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_ena_reg_t; + +/** Type of int_raw register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_raw:1; + /** error_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_raw_reg_t; + +/** Type of int_clr register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_clr : WT; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_clr:1; + /** error_int_clr : WT; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_clr_reg_t; + +/** Type of int_st register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_st : RO; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_st:1; + /** error_int_st : RO; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_st_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35663984; + * REGDMA date information/ REGDMA version information. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} pau_date_reg_t; + + +typedef struct pau_dev_t { + volatile pau_regdma_conf_reg_t regdma_conf; + volatile pau_regdma_clk_conf_reg_t regdma_clk_conf; + volatile pau_regdma_etm_ctrl_reg_t regdma_etm_ctrl; + volatile pau_regdma_link_0_addr_reg_t regdma_link_0_addr; + volatile pau_regdma_link_1_addr_reg_t regdma_link_1_addr; + volatile pau_regdma_link_2_addr_reg_t regdma_link_2_addr; + volatile pau_regdma_link_3_addr_reg_t regdma_link_3_addr; + volatile pau_regdma_link_mac_addr_reg_t regdma_link_mac_addr; + volatile pau_regdma_current_link_addr_reg_t regdma_current_link_addr; + volatile pau_regdma_backup_addr_reg_t regdma_backup_addr; + volatile pau_regdma_mem_addr_reg_t regdma_mem_addr; + volatile pau_regdma_bkp_conf_reg_t regdma_bkp_conf; + volatile pau_retention_link_base_reg_t retention_link_base; + volatile pau_retention_cfg_reg_t retention_cfg; + volatile pau_int_ena_reg_t int_ena; + volatile pau_int_raw_reg_t int_raw; + volatile pau_int_clr_reg_t int_clr; + volatile pau_int_st_reg_t int_st; + uint32_t reserved_048[237]; + volatile pau_date_reg_t date; +} pau_dev_t; + +extern pau_dev_t PAU; + +#ifndef __cplusplus +_Static_assert(sizeof(pau_dev_t) == 0x400, "Invalid size of pau_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/pcnt_reg.h b/components/soc/esp32c6/include/soc/pcnt_reg.h new file mode 100644 index 0000000000..cd59eade79 --- /dev/null +++ b/components/soc/esp32c6/include/soc/pcnt_reg.h @@ -0,0 +1,1226 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PCNT_U0_CONF0_REG register + * Configuration register 0 for unit 0 + */ +#define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0) +/** PCNT_FILTER_THRES_U0 : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ +#define PCNT_FILTER_THRES_U0 0x000003FFU +#define PCNT_FILTER_THRES_U0_M (PCNT_FILTER_THRES_U0_V << PCNT_FILTER_THRES_U0_S) +#define PCNT_FILTER_THRES_U0_V 0x000003FFU +#define PCNT_FILTER_THRES_U0_S 0 +/** PCNT_FILTER_EN_U0 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 0's input filter. + */ +#define PCNT_FILTER_EN_U0 (BIT(10)) +#define PCNT_FILTER_EN_U0_M (PCNT_FILTER_EN_U0_V << PCNT_FILTER_EN_U0_S) +#define PCNT_FILTER_EN_U0_V 0x00000001U +#define PCNT_FILTER_EN_U0_S 10 +/** PCNT_THR_ZERO_EN_U0 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 0's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U0 (BIT(11)) +#define PCNT_THR_ZERO_EN_U0_M (PCNT_THR_ZERO_EN_U0_V << PCNT_THR_ZERO_EN_U0_S) +#define PCNT_THR_ZERO_EN_U0_V 0x00000001U +#define PCNT_THR_ZERO_EN_U0_S 11 +/** PCNT_THR_H_LIM_EN_U0 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 0's thr_h_lim comparator. + */ +#define PCNT_THR_H_LIM_EN_U0 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U0_M (PCNT_THR_H_LIM_EN_U0_V << PCNT_THR_H_LIM_EN_U0_S) +#define PCNT_THR_H_LIM_EN_U0_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U0_S 12 +/** PCNT_THR_L_LIM_EN_U0 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 0's thr_l_lim comparator. + */ +#define PCNT_THR_L_LIM_EN_U0 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U0_M (PCNT_THR_L_LIM_EN_U0_V << PCNT_THR_L_LIM_EN_U0_S) +#define PCNT_THR_L_LIM_EN_U0_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U0_S 13 +/** PCNT_THR_THRES0_EN_U0 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 0's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U0 (BIT(14)) +#define PCNT_THR_THRES0_EN_U0_M (PCNT_THR_THRES0_EN_U0_V << PCNT_THR_THRES0_EN_U0_S) +#define PCNT_THR_THRES0_EN_U0_V 0x00000001U +#define PCNT_THR_THRES0_EN_U0_S 14 +/** PCNT_THR_THRES1_EN_U0 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 0's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U0 (BIT(15)) +#define PCNT_THR_THRES1_EN_U0_M (PCNT_THR_THRES1_EN_U0_V << PCNT_THR_THRES1_EN_U0_S) +#define PCNT_THR_THRES1_EN_U0_V 0x00000001U +#define PCNT_THR_THRES1_EN_U0_S 15 +/** PCNT_CH0_NEG_MODE_U0 : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_NEG_MODE_U0 0x00000003U +#define PCNT_CH0_NEG_MODE_U0_M (PCNT_CH0_NEG_MODE_U0_V << PCNT_CH0_NEG_MODE_U0_S) +#define PCNT_CH0_NEG_MODE_U0_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U0_S 16 +/** PCNT_CH0_POS_MODE_U0 : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_POS_MODE_U0 0x00000003U +#define PCNT_CH0_POS_MODE_U0_M (PCNT_CH0_POS_MODE_U0_V << PCNT_CH0_POS_MODE_U0_S) +#define PCNT_CH0_POS_MODE_U0_V 0x00000003U +#define PCNT_CH0_POS_MODE_U0_S 18 +/** PCNT_CH0_HCTRL_MODE_U0 : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U0 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U0_M (PCNT_CH0_HCTRL_MODE_U0_V << PCNT_CH0_HCTRL_MODE_U0_S) +#define PCNT_CH0_HCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U0_S 20 +/** PCNT_CH0_LCTRL_MODE_U0 : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U0 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U0_M (PCNT_CH0_LCTRL_MODE_U0_V << PCNT_CH0_LCTRL_MODE_U0_S) +#define PCNT_CH0_LCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U0_S 22 +/** PCNT_CH1_NEG_MODE_U0 : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_NEG_MODE_U0 0x00000003U +#define PCNT_CH1_NEG_MODE_U0_M (PCNT_CH1_NEG_MODE_U0_V << PCNT_CH1_NEG_MODE_U0_S) +#define PCNT_CH1_NEG_MODE_U0_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U0_S 24 +/** PCNT_CH1_POS_MODE_U0 : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_POS_MODE_U0 0x00000003U +#define PCNT_CH1_POS_MODE_U0_M (PCNT_CH1_POS_MODE_U0_V << PCNT_CH1_POS_MODE_U0_S) +#define PCNT_CH1_POS_MODE_U0_V 0x00000003U +#define PCNT_CH1_POS_MODE_U0_S 26 +/** PCNT_CH1_HCTRL_MODE_U0 : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U0 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U0_M (PCNT_CH1_HCTRL_MODE_U0_V << PCNT_CH1_HCTRL_MODE_U0_S) +#define PCNT_CH1_HCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U0_S 28 +/** PCNT_CH1_LCTRL_MODE_U0 : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U0 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U0_M (PCNT_CH1_LCTRL_MODE_U0_V << PCNT_CH1_LCTRL_MODE_U0_S) +#define PCNT_CH1_LCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U0_S 30 + +/** PCNT_U0_CONF1_REG register + * Configuration register 1 for unit 0 + */ +#define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x4) +/** PCNT_CNT_THRES0_U0 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit 0. + */ +#define PCNT_CNT_THRES0_U0 0x0000FFFFU +#define PCNT_CNT_THRES0_U0_M (PCNT_CNT_THRES0_U0_V << PCNT_CNT_THRES0_U0_S) +#define PCNT_CNT_THRES0_U0_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U0_S 0 +/** PCNT_CNT_THRES1_U0 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit 0. + */ +#define PCNT_CNT_THRES1_U0 0x0000FFFFU +#define PCNT_CNT_THRES1_U0_M (PCNT_CNT_THRES1_U0_V << PCNT_CNT_THRES1_U0_S) +#define PCNT_CNT_THRES1_U0_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U0_S 16 + +/** PCNT_U0_CONF2_REG register + * Configuration register 2 for unit 0 + */ +#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x8) +/** PCNT_CNT_H_LIM_U0 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit 0. + */ +#define PCNT_CNT_H_LIM_U0 0x0000FFFFU +#define PCNT_CNT_H_LIM_U0_M (PCNT_CNT_H_LIM_U0_V << PCNT_CNT_H_LIM_U0_S) +#define PCNT_CNT_H_LIM_U0_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U0_S 0 +/** PCNT_CNT_L_LIM_U0 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit 0. + */ +#define PCNT_CNT_L_LIM_U0 0x0000FFFFU +#define PCNT_CNT_L_LIM_U0_M (PCNT_CNT_L_LIM_U0_V << PCNT_CNT_L_LIM_U0_S) +#define PCNT_CNT_L_LIM_U0_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U0_S 16 + +/** PCNT_U1_CONF0_REG register + * Configuration register 0 for unit 1 + */ +#define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0xc) +/** PCNT_FILTER_THRES_U1 : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ +#define PCNT_FILTER_THRES_U1 0x000003FFU +#define PCNT_FILTER_THRES_U1_M (PCNT_FILTER_THRES_U1_V << PCNT_FILTER_THRES_U1_S) +#define PCNT_FILTER_THRES_U1_V 0x000003FFU +#define PCNT_FILTER_THRES_U1_S 0 +/** PCNT_FILTER_EN_U1 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 1's input filter. + */ +#define PCNT_FILTER_EN_U1 (BIT(10)) +#define PCNT_FILTER_EN_U1_M (PCNT_FILTER_EN_U1_V << PCNT_FILTER_EN_U1_S) +#define PCNT_FILTER_EN_U1_V 0x00000001U +#define PCNT_FILTER_EN_U1_S 10 +/** PCNT_THR_ZERO_EN_U1 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 1's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U1 (BIT(11)) +#define PCNT_THR_ZERO_EN_U1_M (PCNT_THR_ZERO_EN_U1_V << PCNT_THR_ZERO_EN_U1_S) +#define PCNT_THR_ZERO_EN_U1_V 0x00000001U +#define PCNT_THR_ZERO_EN_U1_S 11 +/** PCNT_THR_H_LIM_EN_U1 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 1's thr_h_lim comparator. + */ +#define PCNT_THR_H_LIM_EN_U1 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U1_M (PCNT_THR_H_LIM_EN_U1_V << PCNT_THR_H_LIM_EN_U1_S) +#define PCNT_THR_H_LIM_EN_U1_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U1_S 12 +/** PCNT_THR_L_LIM_EN_U1 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 1's thr_l_lim comparator. + */ +#define PCNT_THR_L_LIM_EN_U1 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U1_M (PCNT_THR_L_LIM_EN_U1_V << PCNT_THR_L_LIM_EN_U1_S) +#define PCNT_THR_L_LIM_EN_U1_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U1_S 13 +/** PCNT_THR_THRES0_EN_U1 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 1's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U1 (BIT(14)) +#define PCNT_THR_THRES0_EN_U1_M (PCNT_THR_THRES0_EN_U1_V << PCNT_THR_THRES0_EN_U1_S) +#define PCNT_THR_THRES0_EN_U1_V 0x00000001U +#define PCNT_THR_THRES0_EN_U1_S 14 +/** PCNT_THR_THRES1_EN_U1 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 1's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U1 (BIT(15)) +#define PCNT_THR_THRES1_EN_U1_M (PCNT_THR_THRES1_EN_U1_V << PCNT_THR_THRES1_EN_U1_S) +#define PCNT_THR_THRES1_EN_U1_V 0x00000001U +#define PCNT_THR_THRES1_EN_U1_S 15 +/** PCNT_CH0_NEG_MODE_U1 : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_NEG_MODE_U1 0x00000003U +#define PCNT_CH0_NEG_MODE_U1_M (PCNT_CH0_NEG_MODE_U1_V << PCNT_CH0_NEG_MODE_U1_S) +#define PCNT_CH0_NEG_MODE_U1_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U1_S 16 +/** PCNT_CH0_POS_MODE_U1 : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_POS_MODE_U1 0x00000003U +#define PCNT_CH0_POS_MODE_U1_M (PCNT_CH0_POS_MODE_U1_V << PCNT_CH0_POS_MODE_U1_S) +#define PCNT_CH0_POS_MODE_U1_V 0x00000003U +#define PCNT_CH0_POS_MODE_U1_S 18 +/** PCNT_CH0_HCTRL_MODE_U1 : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U1 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U1_M (PCNT_CH0_HCTRL_MODE_U1_V << PCNT_CH0_HCTRL_MODE_U1_S) +#define PCNT_CH0_HCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U1_S 20 +/** PCNT_CH0_LCTRL_MODE_U1 : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U1 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U1_M (PCNT_CH0_LCTRL_MODE_U1_V << PCNT_CH0_LCTRL_MODE_U1_S) +#define PCNT_CH0_LCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U1_S 22 +/** PCNT_CH1_NEG_MODE_U1 : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_NEG_MODE_U1 0x00000003U +#define PCNT_CH1_NEG_MODE_U1_M (PCNT_CH1_NEG_MODE_U1_V << PCNT_CH1_NEG_MODE_U1_S) +#define PCNT_CH1_NEG_MODE_U1_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U1_S 24 +/** PCNT_CH1_POS_MODE_U1 : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_POS_MODE_U1 0x00000003U +#define PCNT_CH1_POS_MODE_U1_M (PCNT_CH1_POS_MODE_U1_V << PCNT_CH1_POS_MODE_U1_S) +#define PCNT_CH1_POS_MODE_U1_V 0x00000003U +#define PCNT_CH1_POS_MODE_U1_S 26 +/** PCNT_CH1_HCTRL_MODE_U1 : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U1 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U1_M (PCNT_CH1_HCTRL_MODE_U1_V << PCNT_CH1_HCTRL_MODE_U1_S) +#define PCNT_CH1_HCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U1_S 28 +/** PCNT_CH1_LCTRL_MODE_U1 : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U1 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U1_M (PCNT_CH1_LCTRL_MODE_U1_V << PCNT_CH1_LCTRL_MODE_U1_S) +#define PCNT_CH1_LCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U1_S 30 + +/** PCNT_U1_CONF1_REG register + * Configuration register 1 for unit 1 + */ +#define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x10) +/** PCNT_CNT_THRES0_U1 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit 1. + */ +#define PCNT_CNT_THRES0_U1 0x0000FFFFU +#define PCNT_CNT_THRES0_U1_M (PCNT_CNT_THRES0_U1_V << PCNT_CNT_THRES0_U1_S) +#define PCNT_CNT_THRES0_U1_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U1_S 0 +/** PCNT_CNT_THRES1_U1 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit 1. + */ +#define PCNT_CNT_THRES1_U1 0x0000FFFFU +#define PCNT_CNT_THRES1_U1_M (PCNT_CNT_THRES1_U1_V << PCNT_CNT_THRES1_U1_S) +#define PCNT_CNT_THRES1_U1_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U1_S 16 + +/** PCNT_U1_CONF2_REG register + * Configuration register 2 for unit 1 + */ +#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x14) +/** PCNT_CNT_H_LIM_U1 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit 1. + */ +#define PCNT_CNT_H_LIM_U1 0x0000FFFFU +#define PCNT_CNT_H_LIM_U1_M (PCNT_CNT_H_LIM_U1_V << PCNT_CNT_H_LIM_U1_S) +#define PCNT_CNT_H_LIM_U1_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U1_S 0 +/** PCNT_CNT_L_LIM_U1 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit 1. + */ +#define PCNT_CNT_L_LIM_U1 0x0000FFFFU +#define PCNT_CNT_L_LIM_U1_M (PCNT_CNT_L_LIM_U1_V << PCNT_CNT_L_LIM_U1_S) +#define PCNT_CNT_L_LIM_U1_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U1_S 16 + +/** PCNT_U2_CONF0_REG register + * Configuration register 0 for unit 2 + */ +#define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x18) +/** PCNT_FILTER_THRES_U2 : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ +#define PCNT_FILTER_THRES_U2 0x000003FFU +#define PCNT_FILTER_THRES_U2_M (PCNT_FILTER_THRES_U2_V << PCNT_FILTER_THRES_U2_S) +#define PCNT_FILTER_THRES_U2_V 0x000003FFU +#define PCNT_FILTER_THRES_U2_S 0 +/** PCNT_FILTER_EN_U2 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 2's input filter. + */ +#define PCNT_FILTER_EN_U2 (BIT(10)) +#define PCNT_FILTER_EN_U2_M (PCNT_FILTER_EN_U2_V << PCNT_FILTER_EN_U2_S) +#define PCNT_FILTER_EN_U2_V 0x00000001U +#define PCNT_FILTER_EN_U2_S 10 +/** PCNT_THR_ZERO_EN_U2 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 2's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U2 (BIT(11)) +#define PCNT_THR_ZERO_EN_U2_M (PCNT_THR_ZERO_EN_U2_V << PCNT_THR_ZERO_EN_U2_S) +#define PCNT_THR_ZERO_EN_U2_V 0x00000001U +#define PCNT_THR_ZERO_EN_U2_S 11 +/** PCNT_THR_H_LIM_EN_U2 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 2's thr_h_lim comparator. + */ +#define PCNT_THR_H_LIM_EN_U2 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U2_M (PCNT_THR_H_LIM_EN_U2_V << PCNT_THR_H_LIM_EN_U2_S) +#define PCNT_THR_H_LIM_EN_U2_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U2_S 12 +/** PCNT_THR_L_LIM_EN_U2 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 2's thr_l_lim comparator. + */ +#define PCNT_THR_L_LIM_EN_U2 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U2_M (PCNT_THR_L_LIM_EN_U2_V << PCNT_THR_L_LIM_EN_U2_S) +#define PCNT_THR_L_LIM_EN_U2_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U2_S 13 +/** PCNT_THR_THRES0_EN_U2 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 2's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U2 (BIT(14)) +#define PCNT_THR_THRES0_EN_U2_M (PCNT_THR_THRES0_EN_U2_V << PCNT_THR_THRES0_EN_U2_S) +#define PCNT_THR_THRES0_EN_U2_V 0x00000001U +#define PCNT_THR_THRES0_EN_U2_S 14 +/** PCNT_THR_THRES1_EN_U2 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 2's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U2 (BIT(15)) +#define PCNT_THR_THRES1_EN_U2_M (PCNT_THR_THRES1_EN_U2_V << PCNT_THR_THRES1_EN_U2_S) +#define PCNT_THR_THRES1_EN_U2_V 0x00000001U +#define PCNT_THR_THRES1_EN_U2_S 15 +/** PCNT_CH0_NEG_MODE_U2 : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_NEG_MODE_U2 0x00000003U +#define PCNT_CH0_NEG_MODE_U2_M (PCNT_CH0_NEG_MODE_U2_V << PCNT_CH0_NEG_MODE_U2_S) +#define PCNT_CH0_NEG_MODE_U2_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U2_S 16 +/** PCNT_CH0_POS_MODE_U2 : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_POS_MODE_U2 0x00000003U +#define PCNT_CH0_POS_MODE_U2_M (PCNT_CH0_POS_MODE_U2_V << PCNT_CH0_POS_MODE_U2_S) +#define PCNT_CH0_POS_MODE_U2_V 0x00000003U +#define PCNT_CH0_POS_MODE_U2_S 18 +/** PCNT_CH0_HCTRL_MODE_U2 : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U2 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U2_M (PCNT_CH0_HCTRL_MODE_U2_V << PCNT_CH0_HCTRL_MODE_U2_S) +#define PCNT_CH0_HCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U2_S 20 +/** PCNT_CH0_LCTRL_MODE_U2 : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U2 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U2_M (PCNT_CH0_LCTRL_MODE_U2_V << PCNT_CH0_LCTRL_MODE_U2_S) +#define PCNT_CH0_LCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U2_S 22 +/** PCNT_CH1_NEG_MODE_U2 : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_NEG_MODE_U2 0x00000003U +#define PCNT_CH1_NEG_MODE_U2_M (PCNT_CH1_NEG_MODE_U2_V << PCNT_CH1_NEG_MODE_U2_S) +#define PCNT_CH1_NEG_MODE_U2_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U2_S 24 +/** PCNT_CH1_POS_MODE_U2 : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_POS_MODE_U2 0x00000003U +#define PCNT_CH1_POS_MODE_U2_M (PCNT_CH1_POS_MODE_U2_V << PCNT_CH1_POS_MODE_U2_S) +#define PCNT_CH1_POS_MODE_U2_V 0x00000003U +#define PCNT_CH1_POS_MODE_U2_S 26 +/** PCNT_CH1_HCTRL_MODE_U2 : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U2 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U2_M (PCNT_CH1_HCTRL_MODE_U2_V << PCNT_CH1_HCTRL_MODE_U2_S) +#define PCNT_CH1_HCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U2_S 28 +/** PCNT_CH1_LCTRL_MODE_U2 : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U2 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U2_M (PCNT_CH1_LCTRL_MODE_U2_V << PCNT_CH1_LCTRL_MODE_U2_S) +#define PCNT_CH1_LCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U2_S 30 + +/** PCNT_U2_CONF1_REG register + * Configuration register 1 for unit 2 + */ +#define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x1c) +/** PCNT_CNT_THRES0_U2 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit 2. + */ +#define PCNT_CNT_THRES0_U2 0x0000FFFFU +#define PCNT_CNT_THRES0_U2_M (PCNT_CNT_THRES0_U2_V << PCNT_CNT_THRES0_U2_S) +#define PCNT_CNT_THRES0_U2_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U2_S 0 +/** PCNT_CNT_THRES1_U2 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit 2. + */ +#define PCNT_CNT_THRES1_U2 0x0000FFFFU +#define PCNT_CNT_THRES1_U2_M (PCNT_CNT_THRES1_U2_V << PCNT_CNT_THRES1_U2_S) +#define PCNT_CNT_THRES1_U2_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U2_S 16 + +/** PCNT_U2_CONF2_REG register + * Configuration register 2 for unit 2 + */ +#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x20) +/** PCNT_CNT_H_LIM_U2 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit 2. + */ +#define PCNT_CNT_H_LIM_U2 0x0000FFFFU +#define PCNT_CNT_H_LIM_U2_M (PCNT_CNT_H_LIM_U2_V << PCNT_CNT_H_LIM_U2_S) +#define PCNT_CNT_H_LIM_U2_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U2_S 0 +/** PCNT_CNT_L_LIM_U2 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit 2. + */ +#define PCNT_CNT_L_LIM_U2 0x0000FFFFU +#define PCNT_CNT_L_LIM_U2_M (PCNT_CNT_L_LIM_U2_V << PCNT_CNT_L_LIM_U2_S) +#define PCNT_CNT_L_LIM_U2_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U2_S 16 + +/** PCNT_U3_CONF0_REG register + * Configuration register 0 for unit 3 + */ +#define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x24) +/** PCNT_FILTER_THRES_U3 : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ +#define PCNT_FILTER_THRES_U3 0x000003FFU +#define PCNT_FILTER_THRES_U3_M (PCNT_FILTER_THRES_U3_V << PCNT_FILTER_THRES_U3_S) +#define PCNT_FILTER_THRES_U3_V 0x000003FFU +#define PCNT_FILTER_THRES_U3_S 0 +/** PCNT_FILTER_EN_U3 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 3's input filter. + */ +#define PCNT_FILTER_EN_U3 (BIT(10)) +#define PCNT_FILTER_EN_U3_M (PCNT_FILTER_EN_U3_V << PCNT_FILTER_EN_U3_S) +#define PCNT_FILTER_EN_U3_V 0x00000001U +#define PCNT_FILTER_EN_U3_S 10 +/** PCNT_THR_ZERO_EN_U3 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 3's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U3 (BIT(11)) +#define PCNT_THR_ZERO_EN_U3_M (PCNT_THR_ZERO_EN_U3_V << PCNT_THR_ZERO_EN_U3_S) +#define PCNT_THR_ZERO_EN_U3_V 0x00000001U +#define PCNT_THR_ZERO_EN_U3_S 11 +/** PCNT_THR_H_LIM_EN_U3 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 3's thr_h_lim comparator. + */ +#define PCNT_THR_H_LIM_EN_U3 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U3_M (PCNT_THR_H_LIM_EN_U3_V << PCNT_THR_H_LIM_EN_U3_S) +#define PCNT_THR_H_LIM_EN_U3_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U3_S 12 +/** PCNT_THR_L_LIM_EN_U3 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 3's thr_l_lim comparator. + */ +#define PCNT_THR_L_LIM_EN_U3 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U3_M (PCNT_THR_L_LIM_EN_U3_V << PCNT_THR_L_LIM_EN_U3_S) +#define PCNT_THR_L_LIM_EN_U3_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U3_S 13 +/** PCNT_THR_THRES0_EN_U3 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 3's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U3 (BIT(14)) +#define PCNT_THR_THRES0_EN_U3_M (PCNT_THR_THRES0_EN_U3_V << PCNT_THR_THRES0_EN_U3_S) +#define PCNT_THR_THRES0_EN_U3_V 0x00000001U +#define PCNT_THR_THRES0_EN_U3_S 14 +/** PCNT_THR_THRES1_EN_U3 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 3's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U3 (BIT(15)) +#define PCNT_THR_THRES1_EN_U3_M (PCNT_THR_THRES1_EN_U3_V << PCNT_THR_THRES1_EN_U3_S) +#define PCNT_THR_THRES1_EN_U3_V 0x00000001U +#define PCNT_THR_THRES1_EN_U3_S 15 +/** PCNT_CH0_NEG_MODE_U3 : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_NEG_MODE_U3 0x00000003U +#define PCNT_CH0_NEG_MODE_U3_M (PCNT_CH0_NEG_MODE_U3_V << PCNT_CH0_NEG_MODE_U3_S) +#define PCNT_CH0_NEG_MODE_U3_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U3_S 16 +/** PCNT_CH0_POS_MODE_U3 : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_POS_MODE_U3 0x00000003U +#define PCNT_CH0_POS_MODE_U3_M (PCNT_CH0_POS_MODE_U3_V << PCNT_CH0_POS_MODE_U3_S) +#define PCNT_CH0_POS_MODE_U3_V 0x00000003U +#define PCNT_CH0_POS_MODE_U3_S 18 +/** PCNT_CH0_HCTRL_MODE_U3 : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U3 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U3_M (PCNT_CH0_HCTRL_MODE_U3_V << PCNT_CH0_HCTRL_MODE_U3_S) +#define PCNT_CH0_HCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U3_S 20 +/** PCNT_CH0_LCTRL_MODE_U3 : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U3 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U3_M (PCNT_CH0_LCTRL_MODE_U3_V << PCNT_CH0_LCTRL_MODE_U3_S) +#define PCNT_CH0_LCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U3_S 22 +/** PCNT_CH1_NEG_MODE_U3 : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_NEG_MODE_U3 0x00000003U +#define PCNT_CH1_NEG_MODE_U3_M (PCNT_CH1_NEG_MODE_U3_V << PCNT_CH1_NEG_MODE_U3_S) +#define PCNT_CH1_NEG_MODE_U3_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U3_S 24 +/** PCNT_CH1_POS_MODE_U3 : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_POS_MODE_U3 0x00000003U +#define PCNT_CH1_POS_MODE_U3_M (PCNT_CH1_POS_MODE_U3_V << PCNT_CH1_POS_MODE_U3_S) +#define PCNT_CH1_POS_MODE_U3_V 0x00000003U +#define PCNT_CH1_POS_MODE_U3_S 26 +/** PCNT_CH1_HCTRL_MODE_U3 : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U3 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U3_M (PCNT_CH1_HCTRL_MODE_U3_V << PCNT_CH1_HCTRL_MODE_U3_S) +#define PCNT_CH1_HCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U3_S 28 +/** PCNT_CH1_LCTRL_MODE_U3 : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U3 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U3_M (PCNT_CH1_LCTRL_MODE_U3_V << PCNT_CH1_LCTRL_MODE_U3_S) +#define PCNT_CH1_LCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U3_S 30 + +/** PCNT_U3_CONF1_REG register + * Configuration register 1 for unit 3 + */ +#define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x28) +/** PCNT_CNT_THRES0_U3 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit 3. + */ +#define PCNT_CNT_THRES0_U3 0x0000FFFFU +#define PCNT_CNT_THRES0_U3_M (PCNT_CNT_THRES0_U3_V << PCNT_CNT_THRES0_U3_S) +#define PCNT_CNT_THRES0_U3_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U3_S 0 +/** PCNT_CNT_THRES1_U3 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit 3. + */ +#define PCNT_CNT_THRES1_U3 0x0000FFFFU +#define PCNT_CNT_THRES1_U3_M (PCNT_CNT_THRES1_U3_V << PCNT_CNT_THRES1_U3_S) +#define PCNT_CNT_THRES1_U3_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U3_S 16 + +/** PCNT_U3_CONF2_REG register + * Configuration register 2 for unit 3 + */ +#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x2c) +/** PCNT_CNT_H_LIM_U3 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit 3. + */ +#define PCNT_CNT_H_LIM_U3 0x0000FFFFU +#define PCNT_CNT_H_LIM_U3_M (PCNT_CNT_H_LIM_U3_V << PCNT_CNT_H_LIM_U3_S) +#define PCNT_CNT_H_LIM_U3_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U3_S 0 +/** PCNT_CNT_L_LIM_U3 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit 3. + */ +#define PCNT_CNT_L_LIM_U3 0x0000FFFFU +#define PCNT_CNT_L_LIM_U3_M (PCNT_CNT_L_LIM_U3_V << PCNT_CNT_L_LIM_U3_S) +#define PCNT_CNT_L_LIM_U3_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U3_S 16 + +/** PCNT_U0_CNT_REG register + * Counter value for unit 0 + */ +#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x30) +/** PCNT_PULSE_CNT_U0 : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit 0. + */ +#define PCNT_PULSE_CNT_U0 0x0000FFFFU +#define PCNT_PULSE_CNT_U0_M (PCNT_PULSE_CNT_U0_V << PCNT_PULSE_CNT_U0_S) +#define PCNT_PULSE_CNT_U0_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U0_S 0 + +/** PCNT_U1_CNT_REG register + * Counter value for unit 1 + */ +#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x34) +/** PCNT_PULSE_CNT_U1 : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit 1. + */ +#define PCNT_PULSE_CNT_U1 0x0000FFFFU +#define PCNT_PULSE_CNT_U1_M (PCNT_PULSE_CNT_U1_V << PCNT_PULSE_CNT_U1_S) +#define PCNT_PULSE_CNT_U1_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U1_S 0 + +/** PCNT_U2_CNT_REG register + * Counter value for unit 2 + */ +#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x38) +/** PCNT_PULSE_CNT_U2 : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit 2. + */ +#define PCNT_PULSE_CNT_U2 0x0000FFFFU +#define PCNT_PULSE_CNT_U2_M (PCNT_PULSE_CNT_U2_V << PCNT_PULSE_CNT_U2_S) +#define PCNT_PULSE_CNT_U2_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U2_S 0 + +/** PCNT_U3_CNT_REG register + * Counter value for unit 3 + */ +#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x3c) +/** PCNT_PULSE_CNT_U3 : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit 3. + */ +#define PCNT_PULSE_CNT_U3 0x0000FFFFU +#define PCNT_PULSE_CNT_U3_M (PCNT_PULSE_CNT_U3_V << PCNT_PULSE_CNT_U3_S) +#define PCNT_PULSE_CNT_U3_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U3_S 0 + +/** PCNT_INT_RAW_REG register + * Interrupt raw status register + */ +#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x40) +/** PCNT_CNT_THR_EVENT_U0_INT_RAW : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_RAW (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M (PCNT_CNT_THR_EVENT_U0_INT_RAW_V << PCNT_CNT_THR_EVENT_U0_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_RAW : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_RAW (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M (PCNT_CNT_THR_EVENT_U1_INT_RAW_V << PCNT_CNT_THR_EVENT_U1_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_RAW : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_RAW (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M (PCNT_CNT_THR_EVENT_U2_INT_RAW_V << PCNT_CNT_THR_EVENT_U2_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_RAW : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_RAW (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M (PCNT_CNT_THR_EVENT_U3_INT_RAW_V << PCNT_CNT_THR_EVENT_U3_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S 3 + +/** PCNT_INT_ST_REG register + * Interrupt status register + */ +#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x44) +/** PCNT_CNT_THR_EVENT_U0_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_ST (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_M (PCNT_CNT_THR_EVENT_U0_INT_ST_V << PCNT_CNT_THR_EVENT_U0_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_ST_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_ST (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_M (PCNT_CNT_THR_EVENT_U1_INT_ST_V << PCNT_CNT_THR_EVENT_U1_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_ST_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_ST (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_M (PCNT_CNT_THR_EVENT_U2_INT_ST_V << PCNT_CNT_THR_EVENT_U2_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_ST_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_ST (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_M (PCNT_CNT_THR_EVENT_U3_INT_ST_V << PCNT_CNT_THR_EVENT_U3_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_ST_S 3 + +/** PCNT_INT_ENA_REG register + * Interrupt enable register + */ +#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x48) +/** PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_ENA (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M (PCNT_CNT_THR_EVENT_U0_INT_ENA_V << PCNT_CNT_THR_EVENT_U0_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_ENA (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M (PCNT_CNT_THR_EVENT_U1_INT_ENA_V << PCNT_CNT_THR_EVENT_U1_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_ENA (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M (PCNT_CNT_THR_EVENT_U2_INT_ENA_V << PCNT_CNT_THR_EVENT_U2_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_ENA (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M (PCNT_CNT_THR_EVENT_U3_INT_ENA_V << PCNT_CNT_THR_EVENT_U3_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S 3 + +/** PCNT_INT_CLR_REG register + * Interrupt clear register + */ +#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x4c) +/** PCNT_CNT_THR_EVENT_U0_INT_CLR : WO; bitpos: [0]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_CLR (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M (PCNT_CNT_THR_EVENT_U0_INT_CLR_V << PCNT_CNT_THR_EVENT_U0_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_CLR : WO; bitpos: [1]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_CLR (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M (PCNT_CNT_THR_EVENT_U1_INT_CLR_V << PCNT_CNT_THR_EVENT_U1_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_CLR : WO; bitpos: [2]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_CLR (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M (PCNT_CNT_THR_EVENT_U2_INT_CLR_V << PCNT_CNT_THR_EVENT_U2_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_CLR : WO; bitpos: [3]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_CLR (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M (PCNT_CNT_THR_EVENT_U3_INT_CLR_V << PCNT_CNT_THR_EVENT_U3_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S 3 + +/** PCNT_U0_STATUS_REG register + * PNCT UNIT0 status register + */ +#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x50) +/** PCNT_CNT_THR_ZERO_MODE_U0 : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_U0 corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ +#define PCNT_CNT_THR_ZERO_MODE_U0 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U0_M (PCNT_CNT_THR_ZERO_MODE_U0_V << PCNT_CNT_THR_ZERO_MODE_U0_S) +#define PCNT_CNT_THR_ZERO_MODE_U0_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U0_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U0 : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_U0 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES1_LAT_U0 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U0_M (PCNT_CNT_THR_THRES1_LAT_U0_V << PCNT_CNT_THR_THRES1_LAT_U0_S) +#define PCNT_CNT_THR_THRES1_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U0_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U0 : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_U0 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES0_LAT_U0 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U0_M (PCNT_CNT_THR_THRES0_LAT_U0_V << PCNT_CNT_THR_THRES0_LAT_U0_S) +#define PCNT_CNT_THR_THRES0_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U0_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U0 : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_U0 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_L_LIM_LAT_U0 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U0_M (PCNT_CNT_THR_L_LIM_LAT_U0_V << PCNT_CNT_THR_L_LIM_LAT_U0_S) +#define PCNT_CNT_THR_L_LIM_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U0_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U0 : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_U0 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_H_LIM_LAT_U0 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U0_M (PCNT_CNT_THR_H_LIM_LAT_U0_V << PCNT_CNT_THR_H_LIM_LAT_U0_S) +#define PCNT_CNT_THR_H_LIM_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U0_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U0 : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_U0 when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ +#define PCNT_CNT_THR_ZERO_LAT_U0 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U0_M (PCNT_CNT_THR_ZERO_LAT_U0_V << PCNT_CNT_THR_ZERO_LAT_U0_S) +#define PCNT_CNT_THR_ZERO_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U0_S 6 + +/** PCNT_U1_STATUS_REG register + * PNCT UNIT1 status register + */ +#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x54) +/** PCNT_CNT_THR_ZERO_MODE_U1 : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_U1 corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ +#define PCNT_CNT_THR_ZERO_MODE_U1 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U1_M (PCNT_CNT_THR_ZERO_MODE_U1_V << PCNT_CNT_THR_ZERO_MODE_U1_S) +#define PCNT_CNT_THR_ZERO_MODE_U1_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U1_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U1 : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_U1 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES1_LAT_U1 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U1_M (PCNT_CNT_THR_THRES1_LAT_U1_V << PCNT_CNT_THR_THRES1_LAT_U1_S) +#define PCNT_CNT_THR_THRES1_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U1_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U1 : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_U1 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES0_LAT_U1 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U1_M (PCNT_CNT_THR_THRES0_LAT_U1_V << PCNT_CNT_THR_THRES0_LAT_U1_S) +#define PCNT_CNT_THR_THRES0_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U1_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U1 : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_U1 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_L_LIM_LAT_U1 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U1_M (PCNT_CNT_THR_L_LIM_LAT_U1_V << PCNT_CNT_THR_L_LIM_LAT_U1_S) +#define PCNT_CNT_THR_L_LIM_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U1_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U1 : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_U1 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_H_LIM_LAT_U1 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U1_M (PCNT_CNT_THR_H_LIM_LAT_U1_V << PCNT_CNT_THR_H_LIM_LAT_U1_S) +#define PCNT_CNT_THR_H_LIM_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U1_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U1 : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_U1 when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ +#define PCNT_CNT_THR_ZERO_LAT_U1 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U1_M (PCNT_CNT_THR_ZERO_LAT_U1_V << PCNT_CNT_THR_ZERO_LAT_U1_S) +#define PCNT_CNT_THR_ZERO_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U1_S 6 + +/** PCNT_U2_STATUS_REG register + * PNCT UNIT2 status register + */ +#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x58) +/** PCNT_CNT_THR_ZERO_MODE_U2 : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_U2 corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ +#define PCNT_CNT_THR_ZERO_MODE_U2 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U2_M (PCNT_CNT_THR_ZERO_MODE_U2_V << PCNT_CNT_THR_ZERO_MODE_U2_S) +#define PCNT_CNT_THR_ZERO_MODE_U2_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U2_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U2 : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_U2 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES1_LAT_U2 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U2_M (PCNT_CNT_THR_THRES1_LAT_U2_V << PCNT_CNT_THR_THRES1_LAT_U2_S) +#define PCNT_CNT_THR_THRES1_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U2_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U2 : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_U2 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES0_LAT_U2 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U2_M (PCNT_CNT_THR_THRES0_LAT_U2_V << PCNT_CNT_THR_THRES0_LAT_U2_S) +#define PCNT_CNT_THR_THRES0_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U2_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U2 : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_U2 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_L_LIM_LAT_U2 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U2_M (PCNT_CNT_THR_L_LIM_LAT_U2_V << PCNT_CNT_THR_L_LIM_LAT_U2_S) +#define PCNT_CNT_THR_L_LIM_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U2_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U2 : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_U2 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_H_LIM_LAT_U2 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U2_M (PCNT_CNT_THR_H_LIM_LAT_U2_V << PCNT_CNT_THR_H_LIM_LAT_U2_S) +#define PCNT_CNT_THR_H_LIM_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U2_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U2 : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_U2 when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ +#define PCNT_CNT_THR_ZERO_LAT_U2 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U2_M (PCNT_CNT_THR_ZERO_LAT_U2_V << PCNT_CNT_THR_ZERO_LAT_U2_S) +#define PCNT_CNT_THR_ZERO_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U2_S 6 + +/** PCNT_U3_STATUS_REG register + * PNCT UNIT3 status register + */ +#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x5c) +/** PCNT_CNT_THR_ZERO_MODE_U3 : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_U3 corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ +#define PCNT_CNT_THR_ZERO_MODE_U3 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U3_M (PCNT_CNT_THR_ZERO_MODE_U3_V << PCNT_CNT_THR_ZERO_MODE_U3_S) +#define PCNT_CNT_THR_ZERO_MODE_U3_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U3_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U3 : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_U3 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES1_LAT_U3 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U3_M (PCNT_CNT_THR_THRES1_LAT_U3_V << PCNT_CNT_THR_THRES1_LAT_U3_S) +#define PCNT_CNT_THR_THRES1_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U3_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U3 : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_U3 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES0_LAT_U3 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U3_M (PCNT_CNT_THR_THRES0_LAT_U3_V << PCNT_CNT_THR_THRES0_LAT_U3_S) +#define PCNT_CNT_THR_THRES0_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U3_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U3 : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_U3 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_L_LIM_LAT_U3 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U3_M (PCNT_CNT_THR_L_LIM_LAT_U3_V << PCNT_CNT_THR_L_LIM_LAT_U3_S) +#define PCNT_CNT_THR_L_LIM_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U3_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U3 : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_U3 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_H_LIM_LAT_U3 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U3_M (PCNT_CNT_THR_H_LIM_LAT_U3_V << PCNT_CNT_THR_H_LIM_LAT_U3_S) +#define PCNT_CNT_THR_H_LIM_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U3_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U3 : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_U3 when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ +#define PCNT_CNT_THR_ZERO_LAT_U3 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U3_M (PCNT_CNT_THR_ZERO_LAT_U3_V << PCNT_CNT_THR_ZERO_LAT_U3_S) +#define PCNT_CNT_THR_ZERO_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U3_S 6 + +/** PCNT_CTRL_REG register + * Control register for all counters + */ +#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x60) +/** PCNT_PULSE_CNT_RST_U0 : R/W; bitpos: [0]; default: 1; + * Set this bit to clear unit 0's counter. + */ +#define PCNT_PULSE_CNT_RST_U0 (BIT(0)) +#define PCNT_PULSE_CNT_RST_U0_M (PCNT_PULSE_CNT_RST_U0_V << PCNT_PULSE_CNT_RST_U0_S) +#define PCNT_PULSE_CNT_RST_U0_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U0_S 0 +/** PCNT_CNT_PAUSE_U0 : R/W; bitpos: [1]; default: 0; + * Set this bit to freeze unit 0's counter. + */ +#define PCNT_CNT_PAUSE_U0 (BIT(1)) +#define PCNT_CNT_PAUSE_U0_M (PCNT_CNT_PAUSE_U0_V << PCNT_CNT_PAUSE_U0_S) +#define PCNT_CNT_PAUSE_U0_V 0x00000001U +#define PCNT_CNT_PAUSE_U0_S 1 +/** PCNT_PULSE_CNT_RST_U1 : R/W; bitpos: [2]; default: 1; + * Set this bit to clear unit 1's counter. + */ +#define PCNT_PULSE_CNT_RST_U1 (BIT(2)) +#define PCNT_PULSE_CNT_RST_U1_M (PCNT_PULSE_CNT_RST_U1_V << PCNT_PULSE_CNT_RST_U1_S) +#define PCNT_PULSE_CNT_RST_U1_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U1_S 2 +/** PCNT_CNT_PAUSE_U1 : R/W; bitpos: [3]; default: 0; + * Set this bit to freeze unit 1's counter. + */ +#define PCNT_CNT_PAUSE_U1 (BIT(3)) +#define PCNT_CNT_PAUSE_U1_M (PCNT_CNT_PAUSE_U1_V << PCNT_CNT_PAUSE_U1_S) +#define PCNT_CNT_PAUSE_U1_V 0x00000001U +#define PCNT_CNT_PAUSE_U1_S 3 +/** PCNT_PULSE_CNT_RST_U2 : R/W; bitpos: [4]; default: 1; + * Set this bit to clear unit 2's counter. + */ +#define PCNT_PULSE_CNT_RST_U2 (BIT(4)) +#define PCNT_PULSE_CNT_RST_U2_M (PCNT_PULSE_CNT_RST_U2_V << PCNT_PULSE_CNT_RST_U2_S) +#define PCNT_PULSE_CNT_RST_U2_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U2_S 4 +/** PCNT_CNT_PAUSE_U2 : R/W; bitpos: [5]; default: 0; + * Set this bit to freeze unit 2's counter. + */ +#define PCNT_CNT_PAUSE_U2 (BIT(5)) +#define PCNT_CNT_PAUSE_U2_M (PCNT_CNT_PAUSE_U2_V << PCNT_CNT_PAUSE_U2_S) +#define PCNT_CNT_PAUSE_U2_V 0x00000001U +#define PCNT_CNT_PAUSE_U2_S 5 +/** PCNT_PULSE_CNT_RST_U3 : R/W; bitpos: [6]; default: 1; + * Set this bit to clear unit 3's counter. + */ +#define PCNT_PULSE_CNT_RST_U3 (BIT(6)) +#define PCNT_PULSE_CNT_RST_U3_M (PCNT_PULSE_CNT_RST_U3_V << PCNT_PULSE_CNT_RST_U3_S) +#define PCNT_PULSE_CNT_RST_U3_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U3_S 6 +/** PCNT_CNT_PAUSE_U3 : R/W; bitpos: [7]; default: 0; + * Set this bit to freeze unit 3's counter. + */ +#define PCNT_CNT_PAUSE_U3 (BIT(7)) +#define PCNT_CNT_PAUSE_U3_M (PCNT_CNT_PAUSE_U3_V << PCNT_CNT_PAUSE_U3_S) +#define PCNT_CNT_PAUSE_U3_V 0x00000001U +#define PCNT_CNT_PAUSE_U3_S 7 +/** PCNT_CLK_EN : R/W; bitpos: [16]; default: 0; + * The registers clock gate enable signal of PCNT module. 1: the registers can be read + * and written by application. 0: the registers can not be read or written by + * application + */ +#define PCNT_CLK_EN (BIT(16)) +#define PCNT_CLK_EN_M (PCNT_CLK_EN_V << PCNT_CLK_EN_S) +#define PCNT_CLK_EN_V 0x00000001U +#define PCNT_CLK_EN_S 16 + +/** PCNT_DATE_REG register + * PCNT version control register + */ +#define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0xfc) +/** PCNT_DATE : R/W; bitpos: [31:0]; default: 419898881; + * This is the PCNT version control register. + */ +#define PCNT_DATE 0xFFFFFFFFU +#define PCNT_DATE_M (PCNT_DATE_V << PCNT_DATE_S) +#define PCNT_DATE_V 0xFFFFFFFFU +#define PCNT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/pcnt_struct.h b/components/soc/esp32c6/include/soc/pcnt_struct.h new file mode 100644 index 0000000000..13ddb0b672 --- /dev/null +++ b/components/soc/esp32c6/include/soc/pcnt_struct.h @@ -0,0 +1,404 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of un_conf0 register + * Configuration register 0 for unit n + */ +typedef union { + struct { + /** filter_thres : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ + uint32_t filter_thres:10; + /** filter_en : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit n's input filter. + */ + uint32_t filter_en:1; + /** thr_zero_en : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit n's zero comparator. + */ + uint32_t thr_zero_en:1; + /** thr_h_lim_en : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit n's thr_h_lim comparator. + */ + uint32_t thr_h_lim_en:1; + /** thr_l_lim_en : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit n's thr_l_lim comparator. + */ + uint32_t thr_l_lim_en:1; + /** thr_thres0_en : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit n's thres0 comparator. + */ + uint32_t thr_thres0_en:1; + /** thr_thres1_en : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit n's thres1 comparator. + */ + uint32_t thr_thres1_en:1; + /** ch0_neg_mode : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ + uint32_t ch0_neg_mode:2; + /** ch0_pos_mode : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ + uint32_t ch0_pos_mode:2; + /** ch0_hctrl_mode : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch0_hctrl_mode:2; + /** ch0_lctrl_mode : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch0_lctrl_mode:2; + /** ch1_neg_mode : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ + uint32_t ch1_neg_mode:2; + /** ch1_pos_mode : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ + uint32_t ch1_pos_mode:2; + /** ch1_hctrl_mode : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch1_hctrl_mode:2; + /** ch1_lctrl_mode : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch1_lctrl_mode:2; + }; + uint32_t val; +} pcnt_un_conf0_reg_t; + +/** Type of un_conf1 register + * Configuration register 1 for unit n + */ +typedef union { + struct { + /** cnt_thres0 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit n. + */ + uint32_t cnt_thres0:16; + /** cnt_thres1 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit n. + */ + uint32_t cnt_thres1:16; + }; + uint32_t val; +} pcnt_un_conf1_reg_t; + +/** Type of un_conf2 register + * Configuration register 2 for unit n + */ +typedef union { + struct { + /** cnt_h_lim : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit n. + */ + uint32_t cnt_h_lim:16; + /** cnt_l_lim : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit n. + */ + uint32_t cnt_l_lim:16; + }; + uint32_t val; +} pcnt_un_conf2_reg_t; + +/** Type of ctrl register + * Control register for all counters + */ +typedef union { + struct { + /** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1; + * Set this bit to clear unit 0's counter. + */ + uint32_t pulse_cnt_rst_u0:1; + /** cnt_pause_u0 : R/W; bitpos: [1]; default: 0; + * Set this bit to freeze unit 0's counter. + */ + uint32_t cnt_pause_u0:1; + /** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1; + * Set this bit to clear unit 1's counter. + */ + uint32_t pulse_cnt_rst_u1:1; + /** cnt_pause_u1 : R/W; bitpos: [3]; default: 0; + * Set this bit to freeze unit 1's counter. + */ + uint32_t cnt_pause_u1:1; + /** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1; + * Set this bit to clear unit 2's counter. + */ + uint32_t pulse_cnt_rst_u2:1; + /** cnt_pause_u2 : R/W; bitpos: [5]; default: 0; + * Set this bit to freeze unit 2's counter. + */ + uint32_t cnt_pause_u2:1; + /** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1; + * Set this bit to clear unit 3's counter. + */ + uint32_t pulse_cnt_rst_u3:1; + /** cnt_pause_u3 : R/W; bitpos: [7]; default: 0; + * Set this bit to freeze unit 3's counter. + */ + uint32_t cnt_pause_u3:1; + uint32_t reserved_8:8; + /** clk_en : R/W; bitpos: [16]; default: 0; + * The registers clock gate enable signal of PCNT module. 1: the registers can be read + * and written by application. 0: the registers can not be read or written by + * application + */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} pcnt_ctrl_reg_t; + + +/** Group: Status Register */ +/** Type of un_cnt register + * Counter value for unit n + */ +typedef union { + struct { + /** pulse_cnt : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit n. + */ + uint32_t pulse_cnt:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} pcnt_un_cnt_reg_t; + +/** Type of un_status register + * PNCT UNITn status register + */ +typedef union { + struct { + /** cnt_thr_zero_mode : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_Un corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ + uint32_t cnt_thr_zero_mode:2; + /** cnt_thr_thres1_lat : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_Un when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ + uint32_t cnt_thr_thres1_lat:1; + /** cnt_thr_thres0_lat : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_Un when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ + uint32_t cnt_thr_thres0_lat:1; + /** cnt_thr_l_lim_lat : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_Un when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ + uint32_t cnt_thr_l_lim_lat:1; + /** cnt_thr_h_lim_lat : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_Un when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ + uint32_t cnt_thr_h_lim_lat:1; + /** cnt_thr_zero_lat : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_Un when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ + uint32_t cnt_thr_zero_lat:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} pcnt_un_status_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Interrupt raw status register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_raw : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_raw:1; + /** cnt_thr_event_u1_int_raw : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_raw:1; + /** cnt_thr_event_u2_int_raw : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_raw:1; + /** cnt_thr_event_u3_int_raw : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_raw:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_raw_reg_t; + +/** Type of int_st register + * Interrupt status register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_st:1; + /** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_st:1; + /** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_st:1; + /** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_st:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_ena:1; + /** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_ena:1; + /** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_ena:1; + /** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_clr : WO; bitpos: [0]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_clr:1; + /** cnt_thr_event_u1_int_clr : WO; bitpos: [1]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_clr:1; + /** cnt_thr_event_u2_int_clr : WO; bitpos: [2]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_clr:1; + /** cnt_thr_event_u3_int_clr : WO; bitpos: [3]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_clr:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_clr_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * PCNT version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 419898881; + * This is the PCNT version control register. + */ + uint32_t date:32; + }; + uint32_t val; +} pcnt_date_reg_t; + +typedef struct pcnt_dev_t { + volatile struct { + pcnt_un_conf0_reg_t conf0; + pcnt_un_conf1_reg_t conf1; + pcnt_un_conf2_reg_t conf2; + } conf_unit[4]; + volatile pcnt_un_cnt_reg_t cnt_unit[4]; + volatile pcnt_int_raw_reg_t int_raw; + volatile pcnt_int_st_reg_t int_st; + volatile pcnt_int_ena_reg_t int_ena; + volatile pcnt_int_clr_reg_t int_clr; + volatile pcnt_un_status_reg_t status_unit[4]; + volatile pcnt_ctrl_reg_t ctrl; + uint32_t reserved_064[38]; + volatile pcnt_date_reg_t date; +} pcnt_dev_t; + +extern pcnt_dev_t PCNT; + +#ifndef __cplusplus +_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/pcr_reg.h b/components/soc/esp32c6/include/soc/pcr_reg.h new file mode 100644 index 0000000000..35a77baaab --- /dev/null +++ b/components/soc/esp32c6/include/soc/pcr_reg.h @@ -0,0 +1,2065 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PCR_UART0_CONF_REG register + * UART0 configuration register + */ +#define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0) +/** PCR_UART0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart0 apb clock + */ +#define PCR_UART0_CLK_EN (BIT(0)) +#define PCR_UART0_CLK_EN_M (PCR_UART0_CLK_EN_V << PCR_UART0_CLK_EN_S) +#define PCR_UART0_CLK_EN_V 0x00000001U +#define PCR_UART0_CLK_EN_S 0 +/** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart0 module + */ +#define PCR_UART0_RST_EN (BIT(1)) +#define PCR_UART0_RST_EN_M (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S) +#define PCR_UART0_RST_EN_V 0x00000001U +#define PCR_UART0_RST_EN_S 1 + +/** PCR_UART0_SCLK_CONF_REG register + * UART0_SCLK configuration register + */ +#define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4) +/** PCR_UART0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_A 0x0000003FU +#define PCR_UART0_SCLK_DIV_A_M (PCR_UART0_SCLK_DIV_A_V << PCR_UART0_SCLK_DIV_A_S) +#define PCR_UART0_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART0_SCLK_DIV_A_S 0 +/** PCR_UART0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_B 0x0000003FU +#define PCR_UART0_SCLK_DIV_B_M (PCR_UART0_SCLK_DIV_B_V << PCR_UART0_SCLK_DIV_B_S) +#define PCR_UART0_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART0_SCLK_DIV_B_S 6 +/** PCR_UART0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART0_SCLK_DIV_NUM_M (PCR_UART0_SCLK_DIV_NUM_V << PCR_UART0_SCLK_DIV_NUM_S) +#define PCR_UART0_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART0_SCLK_DIV_NUM_S 12 +/** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ +#define PCR_UART0_SCLK_SEL 0x00000003U +#define PCR_UART0_SCLK_SEL_M (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S) +#define PCR_UART0_SCLK_SEL_V 0x00000003U +#define PCR_UART0_SCLK_SEL_S 20 +/** PCR_UART0_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ +#define PCR_UART0_SCLK_EN (BIT(22)) +#define PCR_UART0_SCLK_EN_M (PCR_UART0_SCLK_EN_V << PCR_UART0_SCLK_EN_S) +#define PCR_UART0_SCLK_EN_V 0x00000001U +#define PCR_UART0_SCLK_EN_S 22 + +/** PCR_UART0_PD_CTRL_REG register + * UART0 power control register + */ +#define PCR_UART0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x8) +/** PCR_UART0_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART0 memory. + */ +#define PCR_UART0_MEM_FORCE_PU (BIT(1)) +#define PCR_UART0_MEM_FORCE_PU_M (PCR_UART0_MEM_FORCE_PU_V << PCR_UART0_MEM_FORCE_PU_S) +#define PCR_UART0_MEM_FORCE_PU_V 0x00000001U +#define PCR_UART0_MEM_FORCE_PU_S 1 +/** PCR_UART0_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART0 memory. + */ +#define PCR_UART0_MEM_FORCE_PD (BIT(2)) +#define PCR_UART0_MEM_FORCE_PD_M (PCR_UART0_MEM_FORCE_PD_V << PCR_UART0_MEM_FORCE_PD_S) +#define PCR_UART0_MEM_FORCE_PD_V 0x00000001U +#define PCR_UART0_MEM_FORCE_PD_S 2 + +/** PCR_UART1_CONF_REG register + * UART1 configuration register + */ +#define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc) +/** PCR_UART1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart1 apb clock + */ +#define PCR_UART1_CLK_EN (BIT(0)) +#define PCR_UART1_CLK_EN_M (PCR_UART1_CLK_EN_V << PCR_UART1_CLK_EN_S) +#define PCR_UART1_CLK_EN_V 0x00000001U +#define PCR_UART1_CLK_EN_S 0 +/** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart1 module + */ +#define PCR_UART1_RST_EN (BIT(1)) +#define PCR_UART1_RST_EN_M (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S) +#define PCR_UART1_RST_EN_V 0x00000001U +#define PCR_UART1_RST_EN_S 1 + +/** PCR_UART1_SCLK_CONF_REG register + * UART1_SCLK configuration register + */ +#define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10) +/** PCR_UART1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_A 0x0000003FU +#define PCR_UART1_SCLK_DIV_A_M (PCR_UART1_SCLK_DIV_A_V << PCR_UART1_SCLK_DIV_A_S) +#define PCR_UART1_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART1_SCLK_DIV_A_S 0 +/** PCR_UART1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_B 0x0000003FU +#define PCR_UART1_SCLK_DIV_B_M (PCR_UART1_SCLK_DIV_B_V << PCR_UART1_SCLK_DIV_B_S) +#define PCR_UART1_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART1_SCLK_DIV_B_S 6 +/** PCR_UART1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART1_SCLK_DIV_NUM_M (PCR_UART1_SCLK_DIV_NUM_V << PCR_UART1_SCLK_DIV_NUM_S) +#define PCR_UART1_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART1_SCLK_DIV_NUM_S 12 +/** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ +#define PCR_UART1_SCLK_SEL 0x00000003U +#define PCR_UART1_SCLK_SEL_M (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S) +#define PCR_UART1_SCLK_SEL_V 0x00000003U +#define PCR_UART1_SCLK_SEL_S 20 +/** PCR_UART1_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ +#define PCR_UART1_SCLK_EN (BIT(22)) +#define PCR_UART1_SCLK_EN_M (PCR_UART1_SCLK_EN_V << PCR_UART1_SCLK_EN_S) +#define PCR_UART1_SCLK_EN_V 0x00000001U +#define PCR_UART1_SCLK_EN_S 22 + +/** PCR_UART1_PD_CTRL_REG register + * UART1 power control register + */ +#define PCR_UART1_PD_CTRL_REG (DR_REG_PCR_BASE + 0x14) +/** PCR_UART1_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART1 memory. + */ +#define PCR_UART1_MEM_FORCE_PU (BIT(1)) +#define PCR_UART1_MEM_FORCE_PU_M (PCR_UART1_MEM_FORCE_PU_V << PCR_UART1_MEM_FORCE_PU_S) +#define PCR_UART1_MEM_FORCE_PU_V 0x00000001U +#define PCR_UART1_MEM_FORCE_PU_S 1 +/** PCR_UART1_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART1 memory. + */ +#define PCR_UART1_MEM_FORCE_PD (BIT(2)) +#define PCR_UART1_MEM_FORCE_PD_M (PCR_UART1_MEM_FORCE_PD_V << PCR_UART1_MEM_FORCE_PD_S) +#define PCR_UART1_MEM_FORCE_PD_V 0x00000001U +#define PCR_UART1_MEM_FORCE_PD_S 2 + +/** PCR_MSPI_CONF_REG register + * MSPI configuration register + */ +#define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x18) +/** PCR_MSPI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mspi clock, include mspi pll clock + */ +#define PCR_MSPI_CLK_EN (BIT(0)) +#define PCR_MSPI_CLK_EN_M (PCR_MSPI_CLK_EN_V << PCR_MSPI_CLK_EN_S) +#define PCR_MSPI_CLK_EN_V 0x00000001U +#define PCR_MSPI_CLK_EN_S 0 +/** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mspi module + */ +#define PCR_MSPI_RST_EN (BIT(1)) +#define PCR_MSPI_RST_EN_M (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S) +#define PCR_MSPI_RST_EN_V 0x00000001U +#define PCR_MSPI_RST_EN_S 1 +/** PCR_MSPI_PLL_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable mspi pll clock + */ +#define PCR_MSPI_PLL_CLK_EN (BIT(2)) +#define PCR_MSPI_PLL_CLK_EN_M (PCR_MSPI_PLL_CLK_EN_V << PCR_MSPI_PLL_CLK_EN_S) +#define PCR_MSPI_PLL_CLK_EN_V 0x00000001U +#define PCR_MSPI_PLL_CLK_EN_S 2 + +/** PCR_MSPI_CLK_CONF_REG register + * MSPI_CLK configuration register + */ +#define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c) +/** PCR_MSPI_FAST_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed + * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a + * low-speed clock-source such as XTAL/FOSC. + */ +#define PCR_MSPI_FAST_LS_DIV_NUM 0x000000FFU +#define PCR_MSPI_FAST_LS_DIV_NUM_M (PCR_MSPI_FAST_LS_DIV_NUM_V << PCR_MSPI_FAST_LS_DIV_NUM_S) +#define PCR_MSPI_FAST_LS_DIV_NUM_V 0x000000FFU +#define PCR_MSPI_FAST_LS_DIV_NUM_S 0 +/** PCR_MSPI_FAST_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3; + * Set as one within (3,4,5) to generate div4(default)/div5/div6 of high-speed + * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a + * high-speed clock-source such as SPLL. + */ +#define PCR_MSPI_FAST_HS_DIV_NUM 0x000000FFU +#define PCR_MSPI_FAST_HS_DIV_NUM_M (PCR_MSPI_FAST_HS_DIV_NUM_V << PCR_MSPI_FAST_HS_DIV_NUM_S) +#define PCR_MSPI_FAST_HS_DIV_NUM_V 0x000000FFU +#define PCR_MSPI_FAST_HS_DIV_NUM_S 8 + +/** PCR_I2C_CONF_REG register + * I2C configuration register + */ +#define PCR_I2C_CONF_REG (DR_REG_PCR_BASE + 0x20) +/** PCR_I2C_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2c apb clock + */ +#define PCR_I2C_CLK_EN (BIT(0)) +#define PCR_I2C_CLK_EN_M (PCR_I2C_CLK_EN_V << PCR_I2C_CLK_EN_S) +#define PCR_I2C_CLK_EN_V 0x00000001U +#define PCR_I2C_CLK_EN_S 0 +/** PCR_I2C_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2c module + */ +#define PCR_I2C_RST_EN (BIT(1)) +#define PCR_I2C_RST_EN_M (PCR_I2C_RST_EN_V << PCR_I2C_RST_EN_S) +#define PCR_I2C_RST_EN_V 0x00000001U +#define PCR_I2C_RST_EN_S 1 + +/** PCR_I2C_SCLK_CONF_REG register + * I2C_SCLK configuration register + */ +#define PCR_I2C_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x24) +/** PCR_I2C_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C_SCLK_DIV_A 0x0000003FU +#define PCR_I2C_SCLK_DIV_A_M (PCR_I2C_SCLK_DIV_A_V << PCR_I2C_SCLK_DIV_A_S) +#define PCR_I2C_SCLK_DIV_A_V 0x0000003FU +#define PCR_I2C_SCLK_DIV_A_S 0 +/** PCR_I2C_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C_SCLK_DIV_B 0x0000003FU +#define PCR_I2C_SCLK_DIV_B_M (PCR_I2C_SCLK_DIV_B_V << PCR_I2C_SCLK_DIV_B_S) +#define PCR_I2C_SCLK_DIV_B_V 0x0000003FU +#define PCR_I2C_SCLK_DIV_B_S 6 +/** PCR_I2C_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C_SCLK_DIV_NUM 0x000000FFU +#define PCR_I2C_SCLK_DIV_NUM_M (PCR_I2C_SCLK_DIV_NUM_V << PCR_I2C_SCLK_DIV_NUM_S) +#define PCR_I2C_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_I2C_SCLK_DIV_NUM_S 12 +/** PCR_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_I2C_SCLK_SEL (BIT(20)) +#define PCR_I2C_SCLK_SEL_M (PCR_I2C_SCLK_SEL_V << PCR_I2C_SCLK_SEL_S) +#define PCR_I2C_SCLK_SEL_V 0x00000001U +#define PCR_I2C_SCLK_SEL_S 20 +/** PCR_I2C_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2c function clock + */ +#define PCR_I2C_SCLK_EN (BIT(22)) +#define PCR_I2C_SCLK_EN_M (PCR_I2C_SCLK_EN_V << PCR_I2C_SCLK_EN_S) +#define PCR_I2C_SCLK_EN_V 0x00000001U +#define PCR_I2C_SCLK_EN_S 22 + +/** PCR_UHCI_CONF_REG register + * UHCI configuration register + */ +#define PCR_UHCI_CONF_REG (DR_REG_PCR_BASE + 0x28) +/** PCR_UHCI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uhci clock + */ +#define PCR_UHCI_CLK_EN (BIT(0)) +#define PCR_UHCI_CLK_EN_M (PCR_UHCI_CLK_EN_V << PCR_UHCI_CLK_EN_S) +#define PCR_UHCI_CLK_EN_V 0x00000001U +#define PCR_UHCI_CLK_EN_S 0 +/** PCR_UHCI_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uhci module + */ +#define PCR_UHCI_RST_EN (BIT(1)) +#define PCR_UHCI_RST_EN_M (PCR_UHCI_RST_EN_V << PCR_UHCI_RST_EN_S) +#define PCR_UHCI_RST_EN_V 0x00000001U +#define PCR_UHCI_RST_EN_S 1 + +/** PCR_RMT_CONF_REG register + * RMT configuration register + */ +#define PCR_RMT_CONF_REG (DR_REG_PCR_BASE + 0x2c) +/** PCR_RMT_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rmt apb clock + */ +#define PCR_RMT_CLK_EN (BIT(0)) +#define PCR_RMT_CLK_EN_M (PCR_RMT_CLK_EN_V << PCR_RMT_CLK_EN_S) +#define PCR_RMT_CLK_EN_V 0x00000001U +#define PCR_RMT_CLK_EN_S 0 +/** PCR_RMT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rmt module + */ +#define PCR_RMT_RST_EN (BIT(1)) +#define PCR_RMT_RST_EN_M (PCR_RMT_RST_EN_V << PCR_RMT_RST_EN_S) +#define PCR_RMT_RST_EN_V 0x00000001U +#define PCR_RMT_RST_EN_S 1 + +/** PCR_RMT_SCLK_CONF_REG register + * RMT_SCLK configuration register + */ +#define PCR_RMT_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x30) +/** PCR_RMT_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_A 0x0000003FU +#define PCR_RMT_SCLK_DIV_A_M (PCR_RMT_SCLK_DIV_A_V << PCR_RMT_SCLK_DIV_A_S) +#define PCR_RMT_SCLK_DIV_A_V 0x0000003FU +#define PCR_RMT_SCLK_DIV_A_S 0 +/** PCR_RMT_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_B 0x0000003FU +#define PCR_RMT_SCLK_DIV_B_M (PCR_RMT_SCLK_DIV_B_V << PCR_RMT_SCLK_DIV_B_S) +#define PCR_RMT_SCLK_DIV_B_V 0x0000003FU +#define PCR_RMT_SCLK_DIV_B_S 6 +/** PCR_RMT_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1; + * The integral part of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_NUM 0x000000FFU +#define PCR_RMT_SCLK_DIV_NUM_M (PCR_RMT_SCLK_DIV_NUM_V << PCR_RMT_SCLK_DIV_NUM_S) +#define PCR_RMT_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_RMT_SCLK_DIV_NUM_S 12 +/** PCR_RMT_SCLK_SEL : R/W; bitpos: [21:20]; default: 1; + * set this field to select clock-source. 0: do not select anyone clock, 1(default): + * 80MHz, 2: FOSC, 3: XTAL. + */ +#define PCR_RMT_SCLK_SEL 0x00000003U +#define PCR_RMT_SCLK_SEL_M (PCR_RMT_SCLK_SEL_V << PCR_RMT_SCLK_SEL_S) +#define PCR_RMT_SCLK_SEL_V 0x00000003U +#define PCR_RMT_SCLK_SEL_S 20 +/** PCR_RMT_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable rmt function clock + */ +#define PCR_RMT_SCLK_EN (BIT(22)) +#define PCR_RMT_SCLK_EN_M (PCR_RMT_SCLK_EN_V << PCR_RMT_SCLK_EN_S) +#define PCR_RMT_SCLK_EN_V 0x00000001U +#define PCR_RMT_SCLK_EN_S 22 + +/** PCR_LEDC_CONF_REG register + * LEDC configuration register + */ +#define PCR_LEDC_CONF_REG (DR_REG_PCR_BASE + 0x34) +/** PCR_LEDC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ledc apb clock + */ +#define PCR_LEDC_CLK_EN (BIT(0)) +#define PCR_LEDC_CLK_EN_M (PCR_LEDC_CLK_EN_V << PCR_LEDC_CLK_EN_S) +#define PCR_LEDC_CLK_EN_V 0x00000001U +#define PCR_LEDC_CLK_EN_S 0 +/** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ledc module + */ +#define PCR_LEDC_RST_EN (BIT(1)) +#define PCR_LEDC_RST_EN_M (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S) +#define PCR_LEDC_RST_EN_V 0x00000001U +#define PCR_LEDC_RST_EN_S 1 + +/** PCR_LEDC_SCLK_CONF_REG register + * LEDC_SCLK configuration register + */ +#define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x38) +/** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): do not select anyone clock, 1: + * 80MHz, 2: FOSC, 3: XTAL. + */ +#define PCR_LEDC_SCLK_SEL 0x00000003U +#define PCR_LEDC_SCLK_SEL_M (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S) +#define PCR_LEDC_SCLK_SEL_V 0x00000003U +#define PCR_LEDC_SCLK_SEL_S 20 +/** PCR_LEDC_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable ledc function clock + */ +#define PCR_LEDC_SCLK_EN (BIT(22)) +#define PCR_LEDC_SCLK_EN_M (PCR_LEDC_SCLK_EN_V << PCR_LEDC_SCLK_EN_S) +#define PCR_LEDC_SCLK_EN_V 0x00000001U +#define PCR_LEDC_SCLK_EN_S 22 + +/** PCR_TIMERGROUP0_CONF_REG register + * TIMERGROUP0 configuration register + */ +#define PCR_TIMERGROUP0_CONF_REG (DR_REG_PCR_BASE + 0x3c) +/** PCR_TG0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group0 apb clock + */ +#define PCR_TG0_CLK_EN (BIT(0)) +#define PCR_TG0_CLK_EN_M (PCR_TG0_CLK_EN_V << PCR_TG0_CLK_EN_S) +#define PCR_TG0_CLK_EN_V 0x00000001U +#define PCR_TG0_CLK_EN_S 0 +/** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group0 module + */ +#define PCR_TG0_RST_EN (BIT(1)) +#define PCR_TG0_RST_EN_M (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S) +#define PCR_TG0_RST_EN_V 0x00000001U +#define PCR_TG0_RST_EN_S 1 + +/** PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register + * TIMERGROUP0_TIMER_CLK configuration register + */ +#define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x40) +/** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG0_TIMER_CLK_SEL 0x00000003U +#define PCR_TG0_TIMER_CLK_SEL_M (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S) +#define PCR_TG0_TIMER_CLK_SEL_V 0x00000003U +#define PCR_TG0_TIMER_CLK_SEL_S 20 +/** PCR_TG0_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 timer clock + */ +#define PCR_TG0_TIMER_CLK_EN (BIT(22)) +#define PCR_TG0_TIMER_CLK_EN_M (PCR_TG0_TIMER_CLK_EN_V << PCR_TG0_TIMER_CLK_EN_S) +#define PCR_TG0_TIMER_CLK_EN_V 0x00000001U +#define PCR_TG0_TIMER_CLK_EN_S 22 + +/** PCR_TIMERGROUP0_WDT_CLK_CONF_REG register + * TIMERGROUP0_WDT_CLK configuration register + */ +#define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x44) +/** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG0_WDT_CLK_SEL 0x00000003U +#define PCR_TG0_WDT_CLK_SEL_M (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S) +#define PCR_TG0_WDT_CLK_SEL_V 0x00000003U +#define PCR_TG0_WDT_CLK_SEL_S 20 +/** PCR_TG0_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ +#define PCR_TG0_WDT_CLK_EN (BIT(22)) +#define PCR_TG0_WDT_CLK_EN_M (PCR_TG0_WDT_CLK_EN_V << PCR_TG0_WDT_CLK_EN_S) +#define PCR_TG0_WDT_CLK_EN_V 0x00000001U +#define PCR_TG0_WDT_CLK_EN_S 22 + +/** PCR_TIMERGROUP1_CONF_REG register + * TIMERGROUP1 configuration register + */ +#define PCR_TIMERGROUP1_CONF_REG (DR_REG_PCR_BASE + 0x48) +/** PCR_TG1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group1 apb clock + */ +#define PCR_TG1_CLK_EN (BIT(0)) +#define PCR_TG1_CLK_EN_M (PCR_TG1_CLK_EN_V << PCR_TG1_CLK_EN_S) +#define PCR_TG1_CLK_EN_V 0x00000001U +#define PCR_TG1_CLK_EN_S 0 +/** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 module + */ +#define PCR_TG1_RST_EN (BIT(1)) +#define PCR_TG1_RST_EN_M (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S) +#define PCR_TG1_RST_EN_V 0x00000001U +#define PCR_TG1_RST_EN_S 1 + +/** PCR_TIMERGROUP1_TIMER_CLK_CONF_REG register + * TIMERGROUP1_TIMER_CLK configuration register + */ +#define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x4c) +/** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG1_TIMER_CLK_SEL 0x00000003U +#define PCR_TG1_TIMER_CLK_SEL_M (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S) +#define PCR_TG1_TIMER_CLK_SEL_V 0x00000003U +#define PCR_TG1_TIMER_CLK_SEL_S 20 +/** PCR_TG1_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group1 timer clock + */ +#define PCR_TG1_TIMER_CLK_EN (BIT(22)) +#define PCR_TG1_TIMER_CLK_EN_M (PCR_TG1_TIMER_CLK_EN_V << PCR_TG1_TIMER_CLK_EN_S) +#define PCR_TG1_TIMER_CLK_EN_V 0x00000001U +#define PCR_TG1_TIMER_CLK_EN_S 22 + +/** PCR_TIMERGROUP1_WDT_CLK_CONF_REG register + * TIMERGROUP1_WDT_CLK configuration register + */ +#define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x50) +/** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG1_WDT_CLK_SEL 0x00000003U +#define PCR_TG1_WDT_CLK_SEL_M (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S) +#define PCR_TG1_WDT_CLK_SEL_V 0x00000003U +#define PCR_TG1_WDT_CLK_SEL_S 20 +/** PCR_TG1_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ +#define PCR_TG1_WDT_CLK_EN (BIT(22)) +#define PCR_TG1_WDT_CLK_EN_M (PCR_TG1_WDT_CLK_EN_V << PCR_TG1_WDT_CLK_EN_S) +#define PCR_TG1_WDT_CLK_EN_V 0x00000001U +#define PCR_TG1_WDT_CLK_EN_S 22 + +/** PCR_SYSTIMER_CONF_REG register + * SYSTIMER configuration register + */ +#define PCR_SYSTIMER_CONF_REG (DR_REG_PCR_BASE + 0x54) +/** PCR_SYSTIMER_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable systimer apb clock + */ +#define PCR_SYSTIMER_CLK_EN (BIT(0)) +#define PCR_SYSTIMER_CLK_EN_M (PCR_SYSTIMER_CLK_EN_V << PCR_SYSTIMER_CLK_EN_S) +#define PCR_SYSTIMER_CLK_EN_V 0x00000001U +#define PCR_SYSTIMER_CLK_EN_S 0 +/** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset systimer module + */ +#define PCR_SYSTIMER_RST_EN (BIT(1)) +#define PCR_SYSTIMER_RST_EN_M (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S) +#define PCR_SYSTIMER_RST_EN_V 0x00000001U +#define PCR_SYSTIMER_RST_EN_S 1 + +/** PCR_SYSTIMER_FUNC_CLK_CONF_REG register + * SYSTIMER_FUNC_CLK configuration register + */ +#define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x58) +/** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_SYSTIMER_FUNC_CLK_SEL (BIT(20)) +#define PCR_SYSTIMER_FUNC_CLK_SEL_M (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S) +#define PCR_SYSTIMER_FUNC_CLK_SEL_V 0x00000001U +#define PCR_SYSTIMER_FUNC_CLK_SEL_S 20 +/** PCR_SYSTIMER_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable systimer function clock + */ +#define PCR_SYSTIMER_FUNC_CLK_EN (BIT(22)) +#define PCR_SYSTIMER_FUNC_CLK_EN_M (PCR_SYSTIMER_FUNC_CLK_EN_V << PCR_SYSTIMER_FUNC_CLK_EN_S) +#define PCR_SYSTIMER_FUNC_CLK_EN_V 0x00000001U +#define PCR_SYSTIMER_FUNC_CLK_EN_S 22 + +/** PCR_TWAI0_CONF_REG register + * TWAI0 configuration register + */ +#define PCR_TWAI0_CONF_REG (DR_REG_PCR_BASE + 0x5c) +/** PCR_TWAI0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable twai0 apb clock + */ +#define PCR_TWAI0_CLK_EN (BIT(0)) +#define PCR_TWAI0_CLK_EN_M (PCR_TWAI0_CLK_EN_V << PCR_TWAI0_CLK_EN_S) +#define PCR_TWAI0_CLK_EN_V 0x00000001U +#define PCR_TWAI0_CLK_EN_S 0 +/** PCR_TWAI0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset twai0 module + */ +#define PCR_TWAI0_RST_EN (BIT(1)) +#define PCR_TWAI0_RST_EN_M (PCR_TWAI0_RST_EN_V << PCR_TWAI0_RST_EN_S) +#define PCR_TWAI0_RST_EN_V 0x00000001U +#define PCR_TWAI0_RST_EN_S 1 + +/** PCR_TWAI0_FUNC_CLK_CONF_REG register + * TWAI0_FUNC_CLK configuration register + */ +#define PCR_TWAI0_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x60) +/** PCR_TWAI0_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_TWAI0_FUNC_CLK_SEL (BIT(20)) +#define PCR_TWAI0_FUNC_CLK_SEL_M (PCR_TWAI0_FUNC_CLK_SEL_V << PCR_TWAI0_FUNC_CLK_SEL_S) +#define PCR_TWAI0_FUNC_CLK_SEL_V 0x00000001U +#define PCR_TWAI0_FUNC_CLK_SEL_S 20 +/** PCR_TWAI0_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable twai0 function clock + */ +#define PCR_TWAI0_FUNC_CLK_EN (BIT(22)) +#define PCR_TWAI0_FUNC_CLK_EN_M (PCR_TWAI0_FUNC_CLK_EN_V << PCR_TWAI0_FUNC_CLK_EN_S) +#define PCR_TWAI0_FUNC_CLK_EN_V 0x00000001U +#define PCR_TWAI0_FUNC_CLK_EN_S 22 + +/** PCR_TWAI1_CONF_REG register + * TWAI1 configuration register + */ +#define PCR_TWAI1_CONF_REG (DR_REG_PCR_BASE + 0x64) +/** PCR_TWAI1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable twai1 apb clock + */ +#define PCR_TWAI1_CLK_EN (BIT(0)) +#define PCR_TWAI1_CLK_EN_M (PCR_TWAI1_CLK_EN_V << PCR_TWAI1_CLK_EN_S) +#define PCR_TWAI1_CLK_EN_V 0x00000001U +#define PCR_TWAI1_CLK_EN_S 0 +/** PCR_TWAI1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset twai1 module + */ +#define PCR_TWAI1_RST_EN (BIT(1)) +#define PCR_TWAI1_RST_EN_M (PCR_TWAI1_RST_EN_V << PCR_TWAI1_RST_EN_S) +#define PCR_TWAI1_RST_EN_V 0x00000001U +#define PCR_TWAI1_RST_EN_S 1 + +/** PCR_TWAI1_FUNC_CLK_CONF_REG register + * TWAI1_FUNC_CLK configuration register + */ +#define PCR_TWAI1_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x68) +/** PCR_TWAI1_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_TWAI1_FUNC_CLK_SEL (BIT(20)) +#define PCR_TWAI1_FUNC_CLK_SEL_M (PCR_TWAI1_FUNC_CLK_SEL_V << PCR_TWAI1_FUNC_CLK_SEL_S) +#define PCR_TWAI1_FUNC_CLK_SEL_V 0x00000001U +#define PCR_TWAI1_FUNC_CLK_SEL_S 20 +/** PCR_TWAI1_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable twai1 function clock + */ +#define PCR_TWAI1_FUNC_CLK_EN (BIT(22)) +#define PCR_TWAI1_FUNC_CLK_EN_M (PCR_TWAI1_FUNC_CLK_EN_V << PCR_TWAI1_FUNC_CLK_EN_S) +#define PCR_TWAI1_FUNC_CLK_EN_V 0x00000001U +#define PCR_TWAI1_FUNC_CLK_EN_S 22 + +/** PCR_I2S_CONF_REG register + * I2S configuration register + */ +#define PCR_I2S_CONF_REG (DR_REG_PCR_BASE + 0x6c) +/** PCR_I2S_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2s apb clock + */ +#define PCR_I2S_CLK_EN (BIT(0)) +#define PCR_I2S_CLK_EN_M (PCR_I2S_CLK_EN_V << PCR_I2S_CLK_EN_S) +#define PCR_I2S_CLK_EN_V 0x00000001U +#define PCR_I2S_CLK_EN_S 0 +/** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2s module + */ +#define PCR_I2S_RST_EN (BIT(1)) +#define PCR_I2S_RST_EN_M (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S) +#define PCR_I2S_RST_EN_V 0x00000001U +#define PCR_I2S_RST_EN_S 1 + +/** PCR_I2S_TX_CLKM_CONF_REG register + * I2S_TX_CLKM configuration register + */ +#define PCR_I2S_TX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x70) +/** PCR_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; + * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be + * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= + * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * + * (n+1)-div] + y * (n+1)-div. + */ +#define PCR_I2S_TX_CLKM_DIV_NUM 0x000000FFU +#define PCR_I2S_TX_CLKM_DIV_NUM_M (PCR_I2S_TX_CLKM_DIV_NUM_V << PCR_I2S_TX_CLKM_DIV_NUM_S) +#define PCR_I2S_TX_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_I2S_TX_CLKM_DIV_NUM_S 12 +/** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: + * I2S_MCLK_in. + */ +#define PCR_I2S_TX_CLKM_SEL 0x00000003U +#define PCR_I2S_TX_CLKM_SEL_M (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S) +#define PCR_I2S_TX_CLKM_SEL_V 0x00000003U +#define PCR_I2S_TX_CLKM_SEL_S 20 +/** PCR_I2S_TX_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_tx function clock + */ +#define PCR_I2S_TX_CLKM_EN (BIT(22)) +#define PCR_I2S_TX_CLKM_EN_M (PCR_I2S_TX_CLKM_EN_V << PCR_I2S_TX_CLKM_EN_S) +#define PCR_I2S_TX_CLKM_EN_V 0x00000001U +#define PCR_I2S_TX_CLKM_EN_S 22 + +/** PCR_I2S_TX_CLKM_DIV_CONF_REG register + * I2S_TX_CLKM_DIV configuration register + */ +#define PCR_I2S_TX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x74) +/** PCR_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_TX_CLKM_DIV_Z is (a-b). + */ +#define PCR_I2S_TX_CLKM_DIV_Z 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Z_M (PCR_I2S_TX_CLKM_DIV_Z_V << PCR_I2S_TX_CLKM_DIV_Z_S) +#define PCR_I2S_TX_CLKM_DIV_Z_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Z_S 0 +/** PCR_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_TX_CLKM_DIV_Y is (a%(a-b)). + */ +#define PCR_I2S_TX_CLKM_DIV_Y 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Y_M (PCR_I2S_TX_CLKM_DIV_Y_V << PCR_I2S_TX_CLKM_DIV_Y_S) +#define PCR_I2S_TX_CLKM_DIV_Y_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Y_S 9 +/** PCR_I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define PCR_I2S_TX_CLKM_DIV_X 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_X_M (PCR_I2S_TX_CLKM_DIV_X_V << PCR_I2S_TX_CLKM_DIV_X_S) +#define PCR_I2S_TX_CLKM_DIV_X_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_X_S 18 +/** PCR_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_TX_CLKM_DIV_YN1 is 1. + */ +#define PCR_I2S_TX_CLKM_DIV_YN1 (BIT(27)) +#define PCR_I2S_TX_CLKM_DIV_YN1_M (PCR_I2S_TX_CLKM_DIV_YN1_V << PCR_I2S_TX_CLKM_DIV_YN1_S) +#define PCR_I2S_TX_CLKM_DIV_YN1_V 0x00000001U +#define PCR_I2S_TX_CLKM_DIV_YN1_S 27 + +/** PCR_I2S_RX_CLKM_CONF_REG register + * I2S_RX_CLKM configuration register + */ +#define PCR_I2S_RX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x78) +/** PCR_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; + * Integral I2S clock divider value + */ +#define PCR_I2S_RX_CLKM_DIV_NUM 0x000000FFU +#define PCR_I2S_RX_CLKM_DIV_NUM_M (PCR_I2S_RX_CLKM_DIV_NUM_V << PCR_I2S_RX_CLKM_DIV_NUM_S) +#define PCR_I2S_RX_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_I2S_RX_CLKM_DIV_NUM_S 12 +/** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + */ +#define PCR_I2S_RX_CLKM_SEL 0x00000003U +#define PCR_I2S_RX_CLKM_SEL_M (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S) +#define PCR_I2S_RX_CLKM_SEL_V 0x00000003U +#define PCR_I2S_RX_CLKM_SEL_S 20 +/** PCR_I2S_RX_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_rx function clock + */ +#define PCR_I2S_RX_CLKM_EN (BIT(22)) +#define PCR_I2S_RX_CLKM_EN_M (PCR_I2S_RX_CLKM_EN_V << PCR_I2S_RX_CLKM_EN_S) +#define PCR_I2S_RX_CLKM_EN_V 0x00000001U +#define PCR_I2S_RX_CLKM_EN_S 22 +/** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0; + * This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx + */ +#define PCR_I2S_MCLK_SEL (BIT(23)) +#define PCR_I2S_MCLK_SEL_M (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S) +#define PCR_I2S_MCLK_SEL_V 0x00000001U +#define PCR_I2S_MCLK_SEL_S 23 + +/** PCR_I2S_RX_CLKM_DIV_CONF_REG register + * I2S_RX_CLKM_DIV configuration register + */ +#define PCR_I2S_RX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x7c) +/** PCR_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_RX_CLKM_DIV_Z is (a-b). + */ +#define PCR_I2S_RX_CLKM_DIV_Z 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Z_M (PCR_I2S_RX_CLKM_DIV_Z_V << PCR_I2S_RX_CLKM_DIV_Z_S) +#define PCR_I2S_RX_CLKM_DIV_Z_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Z_S 0 +/** PCR_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_RX_CLKM_DIV_Y is (a%(a-b)). + */ +#define PCR_I2S_RX_CLKM_DIV_Y 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Y_M (PCR_I2S_RX_CLKM_DIV_Y_V << PCR_I2S_RX_CLKM_DIV_Y_S) +#define PCR_I2S_RX_CLKM_DIV_Y_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Y_S 9 +/** PCR_I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define PCR_I2S_RX_CLKM_DIV_X 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_X_M (PCR_I2S_RX_CLKM_DIV_X_V << PCR_I2S_RX_CLKM_DIV_X_S) +#define PCR_I2S_RX_CLKM_DIV_X_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_X_S 18 +/** PCR_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_RX_CLKM_DIV_YN1 is 1. + */ +#define PCR_I2S_RX_CLKM_DIV_YN1 (BIT(27)) +#define PCR_I2S_RX_CLKM_DIV_YN1_M (PCR_I2S_RX_CLKM_DIV_YN1_V << PCR_I2S_RX_CLKM_DIV_YN1_S) +#define PCR_I2S_RX_CLKM_DIV_YN1_V 0x00000001U +#define PCR_I2S_RX_CLKM_DIV_YN1_S 27 + +/** PCR_SARADC_CONF_REG register + * SARADC configuration register + */ +#define PCR_SARADC_CONF_REG (DR_REG_PCR_BASE + 0x80) +/** PCR_SARADC_CLK_EN : R/W; bitpos: [0]; default: 1; + * no use + */ +#define PCR_SARADC_CLK_EN (BIT(0)) +#define PCR_SARADC_CLK_EN_M (PCR_SARADC_CLK_EN_V << PCR_SARADC_CLK_EN_S) +#define PCR_SARADC_CLK_EN_V 0x00000001U +#define PCR_SARADC_CLK_EN_S 0 +/** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset function_register of saradc module + */ +#define PCR_SARADC_RST_EN (BIT(1)) +#define PCR_SARADC_RST_EN_M (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S) +#define PCR_SARADC_RST_EN_V 0x00000001U +#define PCR_SARADC_RST_EN_S 1 +/** PCR_SARADC_REG_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable saradc apb clock + */ +#define PCR_SARADC_REG_CLK_EN (BIT(2)) +#define PCR_SARADC_REG_CLK_EN_M (PCR_SARADC_REG_CLK_EN_V << PCR_SARADC_REG_CLK_EN_S) +#define PCR_SARADC_REG_CLK_EN_V 0x00000001U +#define PCR_SARADC_REG_CLK_EN_S 2 +/** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0; + * Set 0 to reset apb_register of saradc module + */ +#define PCR_SARADC_REG_RST_EN (BIT(3)) +#define PCR_SARADC_REG_RST_EN_M (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S) +#define PCR_SARADC_REG_RST_EN_V 0x00000001U +#define PCR_SARADC_REG_RST_EN_S 3 + +/** PCR_SARADC_CLKM_CONF_REG register + * SARADC_CLKM configuration register + */ +#define PCR_SARADC_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x84) +/** PCR_SARADC_CLKM_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_A 0x0000003FU +#define PCR_SARADC_CLKM_DIV_A_M (PCR_SARADC_CLKM_DIV_A_V << PCR_SARADC_CLKM_DIV_A_S) +#define PCR_SARADC_CLKM_DIV_A_V 0x0000003FU +#define PCR_SARADC_CLKM_DIV_A_S 0 +/** PCR_SARADC_CLKM_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_B 0x0000003FU +#define PCR_SARADC_CLKM_DIV_B_M (PCR_SARADC_CLKM_DIV_B_V << PCR_SARADC_CLKM_DIV_B_S) +#define PCR_SARADC_CLKM_DIV_B_V 0x0000003FU +#define PCR_SARADC_CLKM_DIV_B_S 6 +/** PCR_SARADC_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_NUM 0x000000FFU +#define PCR_SARADC_CLKM_DIV_NUM_M (PCR_SARADC_CLKM_DIV_NUM_V << PCR_SARADC_CLKM_DIV_NUM_S) +#define PCR_SARADC_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_SARADC_CLKM_DIV_NUM_S 12 +/** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_SARADC_CLKM_SEL 0x00000003U +#define PCR_SARADC_CLKM_SEL_M (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S) +#define PCR_SARADC_CLKM_SEL_V 0x00000003U +#define PCR_SARADC_CLKM_SEL_S 20 +/** PCR_SARADC_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable saradc function clock + */ +#define PCR_SARADC_CLKM_EN (BIT(22)) +#define PCR_SARADC_CLKM_EN_M (PCR_SARADC_CLKM_EN_V << PCR_SARADC_CLKM_EN_S) +#define PCR_SARADC_CLKM_EN_V 0x00000001U +#define PCR_SARADC_CLKM_EN_S 22 + +/** PCR_TSENS_CLK_CONF_REG register + * TSENS_CLK configuration register + */ +#define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x88) +/** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): FOSC, 1: XTAL. + */ +#define PCR_TSENS_CLK_SEL (BIT(20)) +#define PCR_TSENS_CLK_SEL_M (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S) +#define PCR_TSENS_CLK_SEL_V 0x00000001U +#define PCR_TSENS_CLK_SEL_S 20 +/** PCR_TSENS_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable tsens clock + */ +#define PCR_TSENS_CLK_EN (BIT(22)) +#define PCR_TSENS_CLK_EN_M (PCR_TSENS_CLK_EN_V << PCR_TSENS_CLK_EN_S) +#define PCR_TSENS_CLK_EN_V 0x00000001U +#define PCR_TSENS_CLK_EN_S 22 +/** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0; + * Set 0 to reset tsens module + */ +#define PCR_TSENS_RST_EN (BIT(23)) +#define PCR_TSENS_RST_EN_M (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S) +#define PCR_TSENS_RST_EN_V 0x00000001U +#define PCR_TSENS_RST_EN_S 23 + +/** PCR_USB_DEVICE_CONF_REG register + * USB_DEVICE configuration register + */ +#define PCR_USB_DEVICE_CONF_REG (DR_REG_PCR_BASE + 0x8c) +/** PCR_USB_DEVICE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable usb_device clock + */ +#define PCR_USB_DEVICE_CLK_EN (BIT(0)) +#define PCR_USB_DEVICE_CLK_EN_M (PCR_USB_DEVICE_CLK_EN_V << PCR_USB_DEVICE_CLK_EN_S) +#define PCR_USB_DEVICE_CLK_EN_V 0x00000001U +#define PCR_USB_DEVICE_CLK_EN_S 0 +/** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset usb_device module + */ +#define PCR_USB_DEVICE_RST_EN (BIT(1)) +#define PCR_USB_DEVICE_RST_EN_M (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S) +#define PCR_USB_DEVICE_RST_EN_V 0x00000001U +#define PCR_USB_DEVICE_RST_EN_S 1 + +/** PCR_INTMTX_CONF_REG register + * INTMTX configuration register + */ +#define PCR_INTMTX_CONF_REG (DR_REG_PCR_BASE + 0x90) +/** PCR_INTMTX_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable intmtx clock + */ +#define PCR_INTMTX_CLK_EN (BIT(0)) +#define PCR_INTMTX_CLK_EN_M (PCR_INTMTX_CLK_EN_V << PCR_INTMTX_CLK_EN_S) +#define PCR_INTMTX_CLK_EN_V 0x00000001U +#define PCR_INTMTX_CLK_EN_S 0 +/** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset intmtx module + */ +#define PCR_INTMTX_RST_EN (BIT(1)) +#define PCR_INTMTX_RST_EN_M (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S) +#define PCR_INTMTX_RST_EN_V 0x00000001U +#define PCR_INTMTX_RST_EN_S 1 + +/** PCR_PCNT_CONF_REG register + * PCNT configuration register + */ +#define PCR_PCNT_CONF_REG (DR_REG_PCR_BASE + 0x94) +/** PCR_PCNT_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable pcnt clock + */ +#define PCR_PCNT_CLK_EN (BIT(0)) +#define PCR_PCNT_CLK_EN_M (PCR_PCNT_CLK_EN_V << PCR_PCNT_CLK_EN_S) +#define PCR_PCNT_CLK_EN_V 0x00000001U +#define PCR_PCNT_CLK_EN_S 0 +/** PCR_PCNT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset pcnt module + */ +#define PCR_PCNT_RST_EN (BIT(1)) +#define PCR_PCNT_RST_EN_M (PCR_PCNT_RST_EN_V << PCR_PCNT_RST_EN_S) +#define PCR_PCNT_RST_EN_V 0x00000001U +#define PCR_PCNT_RST_EN_S 1 + +/** PCR_ETM_CONF_REG register + * ETM configuration register + */ +#define PCR_ETM_CONF_REG (DR_REG_PCR_BASE + 0x98) +/** PCR_ETM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable etm clock + */ +#define PCR_ETM_CLK_EN (BIT(0)) +#define PCR_ETM_CLK_EN_M (PCR_ETM_CLK_EN_V << PCR_ETM_CLK_EN_S) +#define PCR_ETM_CLK_EN_V 0x00000001U +#define PCR_ETM_CLK_EN_S 0 +/** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset etm module + */ +#define PCR_ETM_RST_EN (BIT(1)) +#define PCR_ETM_RST_EN_M (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S) +#define PCR_ETM_RST_EN_V 0x00000001U +#define PCR_ETM_RST_EN_S 1 + +/** PCR_PWM_CONF_REG register + * PWM configuration register + */ +#define PCR_PWM_CONF_REG (DR_REG_PCR_BASE + 0x9c) +/** PCR_PWM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable pwm clock + */ +#define PCR_PWM_CLK_EN (BIT(0)) +#define PCR_PWM_CLK_EN_M (PCR_PWM_CLK_EN_V << PCR_PWM_CLK_EN_S) +#define PCR_PWM_CLK_EN_V 0x00000001U +#define PCR_PWM_CLK_EN_S 0 +/** PCR_PWM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset pwm module + */ +#define PCR_PWM_RST_EN (BIT(1)) +#define PCR_PWM_RST_EN_M (PCR_PWM_RST_EN_V << PCR_PWM_RST_EN_S) +#define PCR_PWM_RST_EN_V 0x00000001U +#define PCR_PWM_RST_EN_S 1 + +/** PCR_PWM_CLK_CONF_REG register + * PWM_CLK configuration register + */ +#define PCR_PWM_CLK_CONF_REG (DR_REG_PCR_BASE + 0xa0) +/** PCR_PWM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the pwm function clock. + */ +#define PCR_PWM_DIV_NUM 0x000000FFU +#define PCR_PWM_DIV_NUM_M (PCR_PWM_DIV_NUM_V << PCR_PWM_DIV_NUM_S) +#define PCR_PWM_DIV_NUM_V 0x000000FFU +#define PCR_PWM_DIV_NUM_S 12 +/** PCR_PWM_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): do not select anyone clock, 1: + * 160MHz, 2: XTAL, 3: FOSC. + */ +#define PCR_PWM_CLKM_SEL 0x00000003U +#define PCR_PWM_CLKM_SEL_M (PCR_PWM_CLKM_SEL_V << PCR_PWM_CLKM_SEL_S) +#define PCR_PWM_CLKM_SEL_V 0x00000003U +#define PCR_PWM_CLKM_SEL_S 20 +/** PCR_PWM_CLKM_EN : R/W; bitpos: [22]; default: 1; + * set this field as 1 to activate pwm clkm. + */ +#define PCR_PWM_CLKM_EN (BIT(22)) +#define PCR_PWM_CLKM_EN_M (PCR_PWM_CLKM_EN_V << PCR_PWM_CLKM_EN_S) +#define PCR_PWM_CLKM_EN_V 0x00000001U +#define PCR_PWM_CLKM_EN_S 22 + +/** PCR_PARL_IO_CONF_REG register + * PARL_IO configuration register + */ +#define PCR_PARL_IO_CONF_REG (DR_REG_PCR_BASE + 0xa4) +/** PCR_PARL_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable parl apb clock + */ +#define PCR_PARL_CLK_EN (BIT(0)) +#define PCR_PARL_CLK_EN_M (PCR_PARL_CLK_EN_V << PCR_PARL_CLK_EN_S) +#define PCR_PARL_CLK_EN_V 0x00000001U +#define PCR_PARL_CLK_EN_S 0 +/** PCR_PARL_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset parl apb reg + */ +#define PCR_PARL_RST_EN (BIT(1)) +#define PCR_PARL_RST_EN_M (PCR_PARL_RST_EN_V << PCR_PARL_RST_EN_S) +#define PCR_PARL_RST_EN_V 0x00000001U +#define PCR_PARL_RST_EN_S 1 + +/** PCR_PARL_CLK_RX_CONF_REG register + * PARL_CLK_RX configuration register + */ +#define PCR_PARL_CLK_RX_CONF_REG (DR_REG_PCR_BASE + 0xa8) +/** PCR_PARL_CLK_RX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl rx clock. + */ +#define PCR_PARL_CLK_RX_DIV_NUM 0x0000FFFFU +#define PCR_PARL_CLK_RX_DIV_NUM_M (PCR_PARL_CLK_RX_DIV_NUM_V << PCR_PARL_CLK_RX_DIV_NUM_S) +#define PCR_PARL_CLK_RX_DIV_NUM_V 0x0000FFFFU +#define PCR_PARL_CLK_RX_DIV_NUM_S 0 +/** PCR_PARL_CLK_RX_SEL : R/W; bitpos: [17:16]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * user clock from pad. + */ +#define PCR_PARL_CLK_RX_SEL 0x00000003U +#define PCR_PARL_CLK_RX_SEL_M (PCR_PARL_CLK_RX_SEL_V << PCR_PARL_CLK_RX_SEL_S) +#define PCR_PARL_CLK_RX_SEL_V 0x00000003U +#define PCR_PARL_CLK_RX_SEL_S 16 +/** PCR_PARL_CLK_RX_EN : R/W; bitpos: [18]; default: 1; + * Set 1 to enable parl rx clock + */ +#define PCR_PARL_CLK_RX_EN (BIT(18)) +#define PCR_PARL_CLK_RX_EN_M (PCR_PARL_CLK_RX_EN_V << PCR_PARL_CLK_RX_EN_S) +#define PCR_PARL_CLK_RX_EN_V 0x00000001U +#define PCR_PARL_CLK_RX_EN_S 18 +/** PCR_PARL_RX_RST_EN : R/W; bitpos: [19]; default: 0; + * Set 0 to reset parl rx module + */ +#define PCR_PARL_RX_RST_EN (BIT(19)) +#define PCR_PARL_RX_RST_EN_M (PCR_PARL_RX_RST_EN_V << PCR_PARL_RX_RST_EN_S) +#define PCR_PARL_RX_RST_EN_V 0x00000001U +#define PCR_PARL_RX_RST_EN_S 19 + +/** PCR_PARL_CLK_TX_CONF_REG register + * PARL_CLK_TX configuration register + */ +#define PCR_PARL_CLK_TX_CONF_REG (DR_REG_PCR_BASE + 0xac) +/** PCR_PARL_CLK_TX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl tx clock. + */ +#define PCR_PARL_CLK_TX_DIV_NUM 0x0000FFFFU +#define PCR_PARL_CLK_TX_DIV_NUM_M (PCR_PARL_CLK_TX_DIV_NUM_V << PCR_PARL_CLK_TX_DIV_NUM_S) +#define PCR_PARL_CLK_TX_DIV_NUM_V 0x0000FFFFU +#define PCR_PARL_CLK_TX_DIV_NUM_S 0 +/** PCR_PARL_CLK_TX_SEL : R/W; bitpos: [17:16]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * user clock from pad. + */ +#define PCR_PARL_CLK_TX_SEL 0x00000003U +#define PCR_PARL_CLK_TX_SEL_M (PCR_PARL_CLK_TX_SEL_V << PCR_PARL_CLK_TX_SEL_S) +#define PCR_PARL_CLK_TX_SEL_V 0x00000003U +#define PCR_PARL_CLK_TX_SEL_S 16 +/** PCR_PARL_CLK_TX_EN : R/W; bitpos: [18]; default: 1; + * Set 1 to enable parl tx clock + */ +#define PCR_PARL_CLK_TX_EN (BIT(18)) +#define PCR_PARL_CLK_TX_EN_M (PCR_PARL_CLK_TX_EN_V << PCR_PARL_CLK_TX_EN_S) +#define PCR_PARL_CLK_TX_EN_V 0x00000001U +#define PCR_PARL_CLK_TX_EN_S 18 +/** PCR_PARL_TX_RST_EN : R/W; bitpos: [19]; default: 0; + * Set 0 to reset parl tx module + */ +#define PCR_PARL_TX_RST_EN (BIT(19)) +#define PCR_PARL_TX_RST_EN_M (PCR_PARL_TX_RST_EN_V << PCR_PARL_TX_RST_EN_S) +#define PCR_PARL_TX_RST_EN_V 0x00000001U +#define PCR_PARL_TX_RST_EN_S 19 + +/** PCR_SDIO_SLAVE_CONF_REG register + * SDIO_SLAVE configuration register + */ +#define PCR_SDIO_SLAVE_CONF_REG (DR_REG_PCR_BASE + 0xb0) +/** PCR_SDIO_SLAVE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sdio_slave clock + */ +#define PCR_SDIO_SLAVE_CLK_EN (BIT(0)) +#define PCR_SDIO_SLAVE_CLK_EN_M (PCR_SDIO_SLAVE_CLK_EN_V << PCR_SDIO_SLAVE_CLK_EN_S) +#define PCR_SDIO_SLAVE_CLK_EN_V 0x00000001U +#define PCR_SDIO_SLAVE_CLK_EN_S 0 +/** PCR_SDIO_SLAVE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset sdio_slave module + */ +#define PCR_SDIO_SLAVE_RST_EN (BIT(1)) +#define PCR_SDIO_SLAVE_RST_EN_M (PCR_SDIO_SLAVE_RST_EN_V << PCR_SDIO_SLAVE_RST_EN_S) +#define PCR_SDIO_SLAVE_RST_EN_V 0x00000001U +#define PCR_SDIO_SLAVE_RST_EN_S 1 + +/** PCR_PVT_MONITOR_CONF_REG register + * PVT_MONITOR configuration register + */ +#define PCR_PVT_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xb4) +/** PCR_PVT_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable apb clock of pvt module + */ +#define PCR_PVT_MONITOR_CLK_EN (BIT(0)) +#define PCR_PVT_MONITOR_CLK_EN_M (PCR_PVT_MONITOR_CLK_EN_V << PCR_PVT_MONITOR_CLK_EN_S) +#define PCR_PVT_MONITOR_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_CLK_EN_S 0 +/** PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset all pvt monitor module + */ +#define PCR_PVT_MONITOR_RST_EN (BIT(1)) +#define PCR_PVT_MONITOR_RST_EN_M (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S) +#define PCR_PVT_MONITOR_RST_EN_V 0x00000001U +#define PCR_PVT_MONITOR_RST_EN_S 1 +/** PCR_PVT_MONITOR_SITE1_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable function clock of modem pvt module + */ +#define PCR_PVT_MONITOR_SITE1_CLK_EN (BIT(2)) +#define PCR_PVT_MONITOR_SITE1_CLK_EN_M (PCR_PVT_MONITOR_SITE1_CLK_EN_V << PCR_PVT_MONITOR_SITE1_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE1_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE1_CLK_EN_S 2 +/** PCR_PVT_MONITOR_SITE2_CLK_EN : R/W; bitpos: [3]; default: 1; + * Set 1 to enable function clock of cpu pvt module + */ +#define PCR_PVT_MONITOR_SITE2_CLK_EN (BIT(3)) +#define PCR_PVT_MONITOR_SITE2_CLK_EN_M (PCR_PVT_MONITOR_SITE2_CLK_EN_V << PCR_PVT_MONITOR_SITE2_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE2_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE2_CLK_EN_S 3 +/** PCR_PVT_MONITOR_SITE3_CLK_EN : R/W; bitpos: [4]; default: 1; + * Set 1 to enable function clock of hp_peri pvt module + */ +#define PCR_PVT_MONITOR_SITE3_CLK_EN (BIT(4)) +#define PCR_PVT_MONITOR_SITE3_CLK_EN_M (PCR_PVT_MONITOR_SITE3_CLK_EN_V << PCR_PVT_MONITOR_SITE3_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE3_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE3_CLK_EN_S 4 + +/** PCR_PVT_MONITOR_FUNC_CLK_CONF_REG register + * PVT_MONITOR function clock configuration register + */ +#define PCR_PVT_MONITOR_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0xb8) +/** PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM : R/W; bitpos: [3:0]; default: 0; + * The integral part of the frequency divider factor of the pvt_monitor function clock. + */ +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM 0x0000000FU +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_M (PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V << PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S) +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V 0x0000000FU +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S 0 +/** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL + * divided by 3. + */ +#define PCR_PVT_MONITOR_FUNC_CLK_SEL (BIT(20)) +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_M (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S) +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_V 0x00000001U +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_S 20 +/** PCR_PVT_MONITOR_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable source clock of pvt sitex + */ +#define PCR_PVT_MONITOR_FUNC_CLK_EN (BIT(22)) +#define PCR_PVT_MONITOR_FUNC_CLK_EN_M (PCR_PVT_MONITOR_FUNC_CLK_EN_V << PCR_PVT_MONITOR_FUNC_CLK_EN_S) +#define PCR_PVT_MONITOR_FUNC_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_FUNC_CLK_EN_S 22 + +/** PCR_GDMA_CONF_REG register + * GDMA configuration register + */ +#define PCR_GDMA_CONF_REG (DR_REG_PCR_BASE + 0xbc) +/** PCR_GDMA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable gdma clock + */ +#define PCR_GDMA_CLK_EN (BIT(0)) +#define PCR_GDMA_CLK_EN_M (PCR_GDMA_CLK_EN_V << PCR_GDMA_CLK_EN_S) +#define PCR_GDMA_CLK_EN_V 0x00000001U +#define PCR_GDMA_CLK_EN_S 0 +/** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset gdma module + */ +#define PCR_GDMA_RST_EN (BIT(1)) +#define PCR_GDMA_RST_EN_M (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S) +#define PCR_GDMA_RST_EN_V 0x00000001U +#define PCR_GDMA_RST_EN_S 1 + +/** PCR_SPI2_CONF_REG register + * SPI2 configuration register + */ +#define PCR_SPI2_CONF_REG (DR_REG_PCR_BASE + 0xc0) +/** PCR_SPI2_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable spi2 apb clock + */ +#define PCR_SPI2_CLK_EN (BIT(0)) +#define PCR_SPI2_CLK_EN_M (PCR_SPI2_CLK_EN_V << PCR_SPI2_CLK_EN_S) +#define PCR_SPI2_CLK_EN_V 0x00000001U +#define PCR_SPI2_CLK_EN_S 0 +/** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset spi2 module + */ +#define PCR_SPI2_RST_EN (BIT(1)) +#define PCR_SPI2_RST_EN_M (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S) +#define PCR_SPI2_RST_EN_V 0x00000001U +#define PCR_SPI2_RST_EN_S 1 + +/** PCR_SPI2_CLKM_CONF_REG register + * SPI2_CLKM configuration register + */ +#define PCR_SPI2_CLKM_CONF_REG (DR_REG_PCR_BASE + 0xc4) +/** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_SPI2_CLKM_SEL 0x00000003U +#define PCR_SPI2_CLKM_SEL_M (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S) +#define PCR_SPI2_CLKM_SEL_V 0x00000003U +#define PCR_SPI2_CLKM_SEL_S 20 +/** PCR_SPI2_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable spi2 function clock + */ +#define PCR_SPI2_CLKM_EN (BIT(22)) +#define PCR_SPI2_CLKM_EN_M (PCR_SPI2_CLKM_EN_V << PCR_SPI2_CLKM_EN_S) +#define PCR_SPI2_CLKM_EN_V 0x00000001U +#define PCR_SPI2_CLKM_EN_S 22 + +/** PCR_AES_CONF_REG register + * AES configuration register + */ +#define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0xc8) +/** PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable aes clock + */ +#define PCR_AES_CLK_EN (BIT(0)) +#define PCR_AES_CLK_EN_M (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S) +#define PCR_AES_CLK_EN_V 0x00000001U +#define PCR_AES_CLK_EN_S 0 +/** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset aes module + */ +#define PCR_AES_RST_EN (BIT(1)) +#define PCR_AES_RST_EN_M (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S) +#define PCR_AES_RST_EN_V 0x00000001U +#define PCR_AES_RST_EN_S 1 + +/** PCR_SHA_CONF_REG register + * SHA configuration register + */ +#define PCR_SHA_CONF_REG (DR_REG_PCR_BASE + 0xcc) +/** PCR_SHA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sha clock + */ +#define PCR_SHA_CLK_EN (BIT(0)) +#define PCR_SHA_CLK_EN_M (PCR_SHA_CLK_EN_V << PCR_SHA_CLK_EN_S) +#define PCR_SHA_CLK_EN_V 0x00000001U +#define PCR_SHA_CLK_EN_S 0 +/** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset sha module + */ +#define PCR_SHA_RST_EN (BIT(1)) +#define PCR_SHA_RST_EN_M (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S) +#define PCR_SHA_RST_EN_V 0x00000001U +#define PCR_SHA_RST_EN_S 1 + +/** PCR_RSA_CONF_REG register + * RSA configuration register + */ +#define PCR_RSA_CONF_REG (DR_REG_PCR_BASE + 0xd0) +/** PCR_RSA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rsa clock + */ +#define PCR_RSA_CLK_EN (BIT(0)) +#define PCR_RSA_CLK_EN_M (PCR_RSA_CLK_EN_V << PCR_RSA_CLK_EN_S) +#define PCR_RSA_CLK_EN_V 0x00000001U +#define PCR_RSA_CLK_EN_S 0 +/** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rsa module + */ +#define PCR_RSA_RST_EN (BIT(1)) +#define PCR_RSA_RST_EN_M (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S) +#define PCR_RSA_RST_EN_V 0x00000001U +#define PCR_RSA_RST_EN_S 1 + +/** PCR_RSA_PD_CTRL_REG register + * RSA power control register + */ +#define PCR_RSA_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd4) +/** PCR_RSA_MEM_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to power down rsa internal memory. + */ +#define PCR_RSA_MEM_PD (BIT(0)) +#define PCR_RSA_MEM_PD_M (PCR_RSA_MEM_PD_V << PCR_RSA_MEM_PD_S) +#define PCR_RSA_MEM_PD_V 0x00000001U +#define PCR_RSA_MEM_PD_S 0 +/** PCR_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up rsa internal memory + */ +#define PCR_RSA_MEM_FORCE_PU (BIT(1)) +#define PCR_RSA_MEM_FORCE_PU_M (PCR_RSA_MEM_FORCE_PU_V << PCR_RSA_MEM_FORCE_PU_S) +#define PCR_RSA_MEM_FORCE_PU_V 0x00000001U +#define PCR_RSA_MEM_FORCE_PU_S 1 +/** PCR_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down rsa internal memory. + */ +#define PCR_RSA_MEM_FORCE_PD (BIT(2)) +#define PCR_RSA_MEM_FORCE_PD_M (PCR_RSA_MEM_FORCE_PD_V << PCR_RSA_MEM_FORCE_PD_S) +#define PCR_RSA_MEM_FORCE_PD_V 0x00000001U +#define PCR_RSA_MEM_FORCE_PD_S 2 + +/** PCR_ECC_CONF_REG register + * ECC configuration register + */ +#define PCR_ECC_CONF_REG (DR_REG_PCR_BASE + 0xd8) +/** PCR_ECC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecc clock + */ +#define PCR_ECC_CLK_EN (BIT(0)) +#define PCR_ECC_CLK_EN_M (PCR_ECC_CLK_EN_V << PCR_ECC_CLK_EN_S) +#define PCR_ECC_CLK_EN_V 0x00000001U +#define PCR_ECC_CLK_EN_S 0 +/** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ecc module + */ +#define PCR_ECC_RST_EN (BIT(1)) +#define PCR_ECC_RST_EN_M (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S) +#define PCR_ECC_RST_EN_V 0x00000001U +#define PCR_ECC_RST_EN_S 1 + +/** PCR_ECC_PD_CTRL_REG register + * ECC power control register + */ +#define PCR_ECC_PD_CTRL_REG (DR_REG_PCR_BASE + 0xdc) +/** PCR_ECC_MEM_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to power down ecc internal memory. + */ +#define PCR_ECC_MEM_PD (BIT(0)) +#define PCR_ECC_MEM_PD_M (PCR_ECC_MEM_PD_V << PCR_ECC_MEM_PD_S) +#define PCR_ECC_MEM_PD_V 0x00000001U +#define PCR_ECC_MEM_PD_S 0 +/** PCR_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up ecc internal memory + */ +#define PCR_ECC_MEM_FORCE_PU (BIT(1)) +#define PCR_ECC_MEM_FORCE_PU_M (PCR_ECC_MEM_FORCE_PU_V << PCR_ECC_MEM_FORCE_PU_S) +#define PCR_ECC_MEM_FORCE_PU_V 0x00000001U +#define PCR_ECC_MEM_FORCE_PU_S 1 +/** PCR_ECC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down ecc internal memory. + */ +#define PCR_ECC_MEM_FORCE_PD (BIT(2)) +#define PCR_ECC_MEM_FORCE_PD_M (PCR_ECC_MEM_FORCE_PD_V << PCR_ECC_MEM_FORCE_PD_S) +#define PCR_ECC_MEM_FORCE_PD_V 0x00000001U +#define PCR_ECC_MEM_FORCE_PD_S 2 + +/** PCR_DS_CONF_REG register + * DS configuration register + */ +#define PCR_DS_CONF_REG (DR_REG_PCR_BASE + 0xe0) +/** PCR_DS_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ds clock + */ +#define PCR_DS_CLK_EN (BIT(0)) +#define PCR_DS_CLK_EN_M (PCR_DS_CLK_EN_V << PCR_DS_CLK_EN_S) +#define PCR_DS_CLK_EN_V 0x00000001U +#define PCR_DS_CLK_EN_S 0 +/** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ds module + */ +#define PCR_DS_RST_EN (BIT(1)) +#define PCR_DS_RST_EN_M (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S) +#define PCR_DS_RST_EN_V 0x00000001U +#define PCR_DS_RST_EN_S 1 + +/** PCR_HMAC_CONF_REG register + * HMAC configuration register + */ +#define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xe4) +/** PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable hmac clock + */ +#define PCR_HMAC_CLK_EN (BIT(0)) +#define PCR_HMAC_CLK_EN_M (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S) +#define PCR_HMAC_CLK_EN_V 0x00000001U +#define PCR_HMAC_CLK_EN_S 0 +/** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset hmac module + */ +#define PCR_HMAC_RST_EN (BIT(1)) +#define PCR_HMAC_RST_EN_M (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S) +#define PCR_HMAC_RST_EN_V 0x00000001U +#define PCR_HMAC_RST_EN_S 1 + +/** PCR_IOMUX_CONF_REG register + * IOMUX configuration register + */ +#define PCR_IOMUX_CONF_REG (DR_REG_PCR_BASE + 0xe8) +/** PCR_IOMUX_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable iomux apb clock + */ +#define PCR_IOMUX_CLK_EN (BIT(0)) +#define PCR_IOMUX_CLK_EN_M (PCR_IOMUX_CLK_EN_V << PCR_IOMUX_CLK_EN_S) +#define PCR_IOMUX_CLK_EN_V 0x00000001U +#define PCR_IOMUX_CLK_EN_S 0 +/** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset iomux module + */ +#define PCR_IOMUX_RST_EN (BIT(1)) +#define PCR_IOMUX_RST_EN_M (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S) +#define PCR_IOMUX_RST_EN_V 0x00000001U +#define PCR_IOMUX_RST_EN_S 1 + +/** PCR_IOMUX_CLK_CONF_REG register + * IOMUX_CLK configuration register + */ +#define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xec) +/** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 3; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ +#define PCR_IOMUX_FUNC_CLK_SEL 0x00000003U +#define PCR_IOMUX_FUNC_CLK_SEL_M (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S) +#define PCR_IOMUX_FUNC_CLK_SEL_V 0x00000003U +#define PCR_IOMUX_FUNC_CLK_SEL_S 20 +/** PCR_IOMUX_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable iomux function clock + */ +#define PCR_IOMUX_FUNC_CLK_EN (BIT(22)) +#define PCR_IOMUX_FUNC_CLK_EN_M (PCR_IOMUX_FUNC_CLK_EN_V << PCR_IOMUX_FUNC_CLK_EN_S) +#define PCR_IOMUX_FUNC_CLK_EN_V 0x00000001U +#define PCR_IOMUX_FUNC_CLK_EN_S 22 + +/** PCR_MEM_MONITOR_CONF_REG register + * MEM_MONITOR configuration register + */ +#define PCR_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xf0) +/** PCR_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mem_monitor clock + */ +#define PCR_MEM_MONITOR_CLK_EN (BIT(0)) +#define PCR_MEM_MONITOR_CLK_EN_M (PCR_MEM_MONITOR_CLK_EN_V << PCR_MEM_MONITOR_CLK_EN_S) +#define PCR_MEM_MONITOR_CLK_EN_V 0x00000001U +#define PCR_MEM_MONITOR_CLK_EN_S 0 +/** PCR_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mem_monitor module + */ +#define PCR_MEM_MONITOR_RST_EN (BIT(1)) +#define PCR_MEM_MONITOR_RST_EN_M (PCR_MEM_MONITOR_RST_EN_V << PCR_MEM_MONITOR_RST_EN_S) +#define PCR_MEM_MONITOR_RST_EN_V 0x00000001U +#define PCR_MEM_MONITOR_RST_EN_S 1 + +/** PCR_REGDMA_CONF_REG register + * REGDMA configuration register + */ +#define PCR_REGDMA_CONF_REG (DR_REG_PCR_BASE + 0xf4) +/** PCR_REGDMA_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable regdma clock + */ +#define PCR_REGDMA_CLK_EN (BIT(0)) +#define PCR_REGDMA_CLK_EN_M (PCR_REGDMA_CLK_EN_V << PCR_REGDMA_CLK_EN_S) +#define PCR_REGDMA_CLK_EN_V 0x00000001U +#define PCR_REGDMA_CLK_EN_S 0 +/** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset regdma module + */ +#define PCR_REGDMA_RST_EN (BIT(1)) +#define PCR_REGDMA_RST_EN_M (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S) +#define PCR_REGDMA_RST_EN_V 0x00000001U +#define PCR_REGDMA_RST_EN_S 1 + +/** PCR_RETENTION_CONF_REG register + * retention configuration register + */ +#define PCR_RETENTION_CONF_REG (DR_REG_PCR_BASE + 0xf8) +/** PCR_RETENTION_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable retention clock + */ +#define PCR_RETENTION_CLK_EN (BIT(0)) +#define PCR_RETENTION_CLK_EN_M (PCR_RETENTION_CLK_EN_V << PCR_RETENTION_CLK_EN_S) +#define PCR_RETENTION_CLK_EN_V 0x00000001U +#define PCR_RETENTION_CLK_EN_S 0 +/** PCR_RETENTION_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset retention module + */ +#define PCR_RETENTION_RST_EN (BIT(1)) +#define PCR_RETENTION_RST_EN_M (PCR_RETENTION_RST_EN_V << PCR_RETENTION_RST_EN_S) +#define PCR_RETENTION_RST_EN_V 0x00000001U +#define PCR_RETENTION_RST_EN_S 1 + +/** PCR_TRACE_CONF_REG register + * TRACE configuration register + */ +#define PCR_TRACE_CONF_REG (DR_REG_PCR_BASE + 0xfc) +/** PCR_TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable trace clock + */ +#define PCR_TRACE_CLK_EN (BIT(0)) +#define PCR_TRACE_CLK_EN_M (PCR_TRACE_CLK_EN_V << PCR_TRACE_CLK_EN_S) +#define PCR_TRACE_CLK_EN_V 0x00000001U +#define PCR_TRACE_CLK_EN_S 0 +/** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset trace module + */ +#define PCR_TRACE_RST_EN (BIT(1)) +#define PCR_TRACE_RST_EN_M (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S) +#define PCR_TRACE_RST_EN_V 0x00000001U +#define PCR_TRACE_RST_EN_S 1 + +/** PCR_ASSIST_CONF_REG register + * ASSIST configuration register + */ +#define PCR_ASSIST_CONF_REG (DR_REG_PCR_BASE + 0x100) +/** PCR_ASSIST_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable assist clock + */ +#define PCR_ASSIST_CLK_EN (BIT(0)) +#define PCR_ASSIST_CLK_EN_M (PCR_ASSIST_CLK_EN_V << PCR_ASSIST_CLK_EN_S) +#define PCR_ASSIST_CLK_EN_V 0x00000001U +#define PCR_ASSIST_CLK_EN_S 0 +/** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset assist module + */ +#define PCR_ASSIST_RST_EN (BIT(1)) +#define PCR_ASSIST_RST_EN_M (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S) +#define PCR_ASSIST_RST_EN_V 0x00000001U +#define PCR_ASSIST_RST_EN_S 1 + +/** PCR_CACHE_CONF_REG register + * CACHE configuration register + */ +#define PCR_CACHE_CONF_REG (DR_REG_PCR_BASE + 0x104) +/** PCR_CACHE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable cache clock + */ +#define PCR_CACHE_CLK_EN (BIT(0)) +#define PCR_CACHE_CLK_EN_M (PCR_CACHE_CLK_EN_V << PCR_CACHE_CLK_EN_S) +#define PCR_CACHE_CLK_EN_V 0x00000001U +#define PCR_CACHE_CLK_EN_S 0 +/** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cache module + */ +#define PCR_CACHE_RST_EN (BIT(1)) +#define PCR_CACHE_RST_EN_M (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S) +#define PCR_CACHE_RST_EN_V 0x00000001U +#define PCR_CACHE_RST_EN_S 1 + +/** PCR_MODEM_APB_CONF_REG register + * MODEM_APB configuration register + */ +#define PCR_MODEM_APB_CONF_REG (DR_REG_PCR_BASE + 0x108) +/** PCR_MODEM_APB_CLK_EN : R/W; bitpos: [0]; default: 1; + * This field indicates if modem_apb clock is enable. 0: disable, 1: enable(default). + */ +#define PCR_MODEM_APB_CLK_EN (BIT(0)) +#define PCR_MODEM_APB_CLK_EN_M (PCR_MODEM_APB_CLK_EN_V << PCR_MODEM_APB_CLK_EN_S) +#define PCR_MODEM_APB_CLK_EN_V 0x00000001U +#define PCR_MODEM_APB_CLK_EN_S 0 +/** PCR_MODEM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set this file as 1 to reset modem-subsystem. + */ +#define PCR_MODEM_RST_EN (BIT(1)) +#define PCR_MODEM_RST_EN_M (PCR_MODEM_RST_EN_V << PCR_MODEM_RST_EN_S) +#define PCR_MODEM_RST_EN_V 0x00000001U +#define PCR_MODEM_RST_EN_S 1 + +/** PCR_TIMEOUT_CONF_REG register + * TIMEOUT configuration register + */ +#define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0x10c) +/** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cpu_peri timeout module + */ +#define PCR_CPU_TIMEOUT_RST_EN (BIT(1)) +#define PCR_CPU_TIMEOUT_RST_EN_M (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S) +#define PCR_CPU_TIMEOUT_RST_EN_V 0x00000001U +#define PCR_CPU_TIMEOUT_RST_EN_S 1 +/** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0; + * Set 0 to reset hp_peri timeout module and hp_modem timeout module + */ +#define PCR_HP_TIMEOUT_RST_EN (BIT(2)) +#define PCR_HP_TIMEOUT_RST_EN_M (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S) +#define PCR_HP_TIMEOUT_RST_EN_V 0x00000001U +#define PCR_HP_TIMEOUT_RST_EN_S 2 + +/** PCR_SYSCLK_CONF_REG register + * SYSCLK configuration register + */ +#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x110) +/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0; + * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed + * clock-source such as XTAL/FOSC. + */ +#define PCR_LS_DIV_NUM 0x000000FFU +#define PCR_LS_DIV_NUM_M (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S) +#define PCR_LS_DIV_NUM_V 0x000000FFU +#define PCR_LS_DIV_NUM_S 0 +/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2; + * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + */ +#define PCR_HS_DIV_NUM 0x000000FFU +#define PCR_HS_DIV_NUM_M (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S) +#define PCR_HS_DIV_NUM_V 0x000000FFU +#define PCR_HS_DIV_NUM_S 8 +/** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved. + */ +#define PCR_SOC_CLK_SEL 0x00000003U +#define PCR_SOC_CLK_SEL_M (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S) +#define PCR_SOC_CLK_SEL_V 0x00000003U +#define PCR_SOC_CLK_SEL_S 16 +/** PCR_CLK_XTAL_FREQ : RO; bitpos: [30:24]; default: 40; + * This field indicates the frequency(MHz) of XTAL. + */ +#define PCR_CLK_XTAL_FREQ 0x0000007FU +#define PCR_CLK_XTAL_FREQ_M (PCR_CLK_XTAL_FREQ_V << PCR_CLK_XTAL_FREQ_S) +#define PCR_CLK_XTAL_FREQ_V 0x0000007FU +#define PCR_CLK_XTAL_FREQ_S 24 + +/** PCR_CPU_WAITI_CONF_REG register + * CPU_WAITI configuration register + */ +#define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0x114) +/** PCR_CPUPERIOD_SEL : HRO; bitpos: [1:0]; default: 1; + * Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM + */ +#define PCR_CPUPERIOD_SEL 0x00000003U +#define PCR_CPUPERIOD_SEL_M (PCR_CPUPERIOD_SEL_V << PCR_CPUPERIOD_SEL_S) +#define PCR_CPUPERIOD_SEL_V 0x00000003U +#define PCR_CPUPERIOD_SEL_S 0 +/** PCR_PLL_FREQ_SEL : HRO; bitpos: [2]; default: 1; + * Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM + */ +#define PCR_PLL_FREQ_SEL (BIT(2)) +#define PCR_PLL_FREQ_SEL_M (PCR_PLL_FREQ_SEL_V << PCR_PLL_FREQ_SEL_S) +#define PCR_PLL_FREQ_SEL_V 0x00000001U +#define PCR_PLL_FREQ_SEL_S 2 +/** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; + * Set 1 to force cpu_waiti_clk enable. + */ +#define PCR_CPU_WAIT_MODE_FORCE_ON (BIT(3)) +#define PCR_CPU_WAIT_MODE_FORCE_ON_M (PCR_CPU_WAIT_MODE_FORCE_ON_V << PCR_CPU_WAIT_MODE_FORCE_ON_S) +#define PCR_CPU_WAIT_MODE_FORCE_ON_V 0x00000001U +#define PCR_CPU_WAIT_MODE_FORCE_ON_S 3 +/** PCR_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0; + * This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk + * will close + */ +#define PCR_CPU_WAITI_DELAY_NUM 0x0000000FU +#define PCR_CPU_WAITI_DELAY_NUM_M (PCR_CPU_WAITI_DELAY_NUM_V << PCR_CPU_WAITI_DELAY_NUM_S) +#define PCR_CPU_WAITI_DELAY_NUM_V 0x0000000FU +#define PCR_CPU_WAITI_DELAY_NUM_S 4 + +/** PCR_CPU_FREQ_CONF_REG register + * CPU_FREQ configuration register + */ +#define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118) +/** PCR_CPU_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed + * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_LS_DIV_NUM. + */ +#define PCR_CPU_LS_DIV_NUM 0x000000FFU +#define PCR_CPU_LS_DIV_NUM_M (PCR_CPU_LS_DIV_NUM_V << PCR_CPU_LS_DIV_NUM_S) +#define PCR_CPU_LS_DIV_NUM_V 0x000000FFU +#define PCR_CPU_LS_DIV_NUM_S 0 +/** PCR_CPU_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 0; + * Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for high-speed + * clock-source such as SPLL, and should be used together with PCR_AHB_HS_DIV_NUM. + */ +#define PCR_CPU_HS_DIV_NUM 0x000000FFU +#define PCR_CPU_HS_DIV_NUM_M (PCR_CPU_HS_DIV_NUM_V << PCR_CPU_HS_DIV_NUM_S) +#define PCR_CPU_HS_DIV_NUM_V 0x000000FFU +#define PCR_CPU_HS_DIV_NUM_S 8 +/** PCR_CPU_HS_120M_FORCE : R/W; bitpos: [16]; default: 0; + * Given that PCR_CPU_HS_DIV_NUM is 0, set this field as 1 to force clk_cpu at 120MHz. + * Only avaliable when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL. + */ +#define PCR_CPU_HS_120M_FORCE (BIT(16)) +#define PCR_CPU_HS_120M_FORCE_M (PCR_CPU_HS_120M_FORCE_V << PCR_CPU_HS_120M_FORCE_S) +#define PCR_CPU_HS_120M_FORCE_V 0x00000001U +#define PCR_CPU_HS_120M_FORCE_S 16 + +/** PCR_AHB_FREQ_CONF_REG register + * AHB_FREQ configuration register + */ +#define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c) +/** PCR_AHB_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set as one within (0,1,3,7) to generate clk_ahb drived by clk_hproot. The clk_ahb + * is div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for + * low-speed clock-source such as XTAL/FOSC, and should be used together with + * PCR_CPU_LS_DIV_NUM. + */ +#define PCR_AHB_LS_DIV_NUM 0x000000FFU +#define PCR_AHB_LS_DIV_NUM_M (PCR_AHB_LS_DIV_NUM_V << PCR_AHB_LS_DIV_NUM_S) +#define PCR_AHB_LS_DIV_NUM_V 0x000000FFU +#define PCR_AHB_LS_DIV_NUM_S 0 +/** PCR_AHB_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3; + * Set as one within (3,7,15) to generate clk_ahb drived by clk_hproot. The clk_ahb is + * div4(default)/div8/div16 of clk_hproot. This field is only avaliable for high-speed + * clock-source such as SPLL, and should be used together with PCR_CPU_HS_DIV_NUM. + */ +#define PCR_AHB_HS_DIV_NUM 0x000000FFU +#define PCR_AHB_HS_DIV_NUM_M (PCR_AHB_HS_DIV_NUM_V << PCR_AHB_HS_DIV_NUM_S) +#define PCR_AHB_HS_DIV_NUM_V 0x000000FFU +#define PCR_AHB_HS_DIV_NUM_S 8 + +/** PCR_APB_FREQ_CONF_REG register + * APB_FREQ configuration register + */ +#define PCR_APB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x120) +/** PCR_APB_DECREASE_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be + * automatically down to clk_apb_decrease only when no access is on apb-bus, and will + * recover to the previous frequency when a new access appears on apb-bus. Set as one + * within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note + * that enable this function will reduce performance. Users can set this field as zero + * to disable the auto-decrease-apb-freq function. By default, this function is + * disable. + */ +#define PCR_APB_DECREASE_DIV_NUM 0x000000FFU +#define PCR_APB_DECREASE_DIV_NUM_M (PCR_APB_DECREASE_DIV_NUM_V << PCR_APB_DECREASE_DIV_NUM_S) +#define PCR_APB_DECREASE_DIV_NUM_V 0x000000FFU +#define PCR_APB_DECREASE_DIV_NUM_S 0 +/** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0; + * Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is + * div1(default)/div2/div4 of clk_ahb. + */ +#define PCR_APB_DIV_NUM 0x000000FFU +#define PCR_APB_DIV_NUM_M (PCR_APB_DIV_NUM_V << PCR_APB_DIV_NUM_S) +#define PCR_APB_DIV_NUM_V 0x000000FFU +#define PCR_APB_DIV_NUM_S 8 + +/** PCR_SYSCLK_FREQ_QUERY_0_REG register + * SYSCLK frequency query 0 register + */ +#define PCR_SYSCLK_FREQ_QUERY_0_REG (DR_REG_PCR_BASE + 0x124) +/** PCR_FOSC_FREQ : HRO; bitpos: [7:0]; default: 20; + * This field indicates the frequency(MHz) of FOSC. + */ +#define PCR_FOSC_FREQ 0x000000FFU +#define PCR_FOSC_FREQ_M (PCR_FOSC_FREQ_V << PCR_FOSC_FREQ_S) +#define PCR_FOSC_FREQ_V 0x000000FFU +#define PCR_FOSC_FREQ_S 0 +/** PCR_PLL_FREQ : HRO; bitpos: [17:8]; default: 480; + * This field indicates the frequency(MHz) of SPLL. + */ +#define PCR_PLL_FREQ 0x000003FFU +#define PCR_PLL_FREQ_M (PCR_PLL_FREQ_V << PCR_PLL_FREQ_S) +#define PCR_PLL_FREQ_V 0x000003FFU +#define PCR_PLL_FREQ_S 8 + +/** PCR_PLL_DIV_CLK_EN_REG register + * SPLL DIV clock-gating configuration register + */ +#define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x128) +/** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1; + * This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_240M_CLK_EN (BIT(0)) +#define PCR_PLL_240M_CLK_EN_M (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S) +#define PCR_PLL_240M_CLK_EN_V 0x00000001U +#define PCR_PLL_240M_CLK_EN_S 0 +/** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1; + * This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_160M_CLK_EN (BIT(1)) +#define PCR_PLL_160M_CLK_EN_M (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S) +#define PCR_PLL_160M_CLK_EN_V 0x00000001U +#define PCR_PLL_160M_CLK_EN_S 1 +/** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1; + * This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_120M_CLK_EN (BIT(2)) +#define PCR_PLL_120M_CLK_EN_M (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S) +#define PCR_PLL_120M_CLK_EN_V 0x00000001U +#define PCR_PLL_120M_CLK_EN_S 2 +/** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1; + * This field is used to open 80 MHz clock (div6 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_80M_CLK_EN (BIT(3)) +#define PCR_PLL_80M_CLK_EN_M (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S) +#define PCR_PLL_80M_CLK_EN_V 0x00000001U +#define PCR_PLL_80M_CLK_EN_S 3 +/** PCR_PLL_48M_CLK_EN : R/W; bitpos: [4]; default: 1; + * This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_48M_CLK_EN (BIT(4)) +#define PCR_PLL_48M_CLK_EN_M (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S) +#define PCR_PLL_48M_CLK_EN_V 0x00000001U +#define PCR_PLL_48M_CLK_EN_S 4 +/** PCR_PLL_40M_CLK_EN : R/W; bitpos: [5]; default: 1; + * This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_40M_CLK_EN (BIT(5)) +#define PCR_PLL_40M_CLK_EN_M (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S) +#define PCR_PLL_40M_CLK_EN_V 0x00000001U +#define PCR_PLL_40M_CLK_EN_S 5 +/** PCR_PLL_20M_CLK_EN : R/W; bitpos: [6]; default: 1; + * This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_20M_CLK_EN (BIT(6)) +#define PCR_PLL_20M_CLK_EN_M (PCR_PLL_20M_CLK_EN_V << PCR_PLL_20M_CLK_EN_S) +#define PCR_PLL_20M_CLK_EN_V 0x00000001U +#define PCR_PLL_20M_CLK_EN_S 6 + +/** PCR_CTRL_CLK_OUT_EN_REG register + * CLK_OUT_EN configuration register + */ +#define PCR_CTRL_CLK_OUT_EN_REG (DR_REG_PCR_BASE + 0x12c) +/** PCR_CLK20_OEN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable 20m clock + */ +#define PCR_CLK20_OEN (BIT(0)) +#define PCR_CLK20_OEN_M (PCR_CLK20_OEN_V << PCR_CLK20_OEN_S) +#define PCR_CLK20_OEN_V 0x00000001U +#define PCR_CLK20_OEN_S 0 +/** PCR_CLK22_OEN : R/W; bitpos: [1]; default: 1; + * Set 1 to enable 22m clock + */ +#define PCR_CLK22_OEN (BIT(1)) +#define PCR_CLK22_OEN_M (PCR_CLK22_OEN_V << PCR_CLK22_OEN_S) +#define PCR_CLK22_OEN_V 0x00000001U +#define PCR_CLK22_OEN_S 1 +/** PCR_CLK44_OEN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable 44m clock + */ +#define PCR_CLK44_OEN (BIT(2)) +#define PCR_CLK44_OEN_M (PCR_CLK44_OEN_V << PCR_CLK44_OEN_S) +#define PCR_CLK44_OEN_V 0x00000001U +#define PCR_CLK44_OEN_S 2 +/** PCR_CLK_BB_OEN : R/W; bitpos: [3]; default: 1; + * Set 1 to enable bb clock + */ +#define PCR_CLK_BB_OEN (BIT(3)) +#define PCR_CLK_BB_OEN_M (PCR_CLK_BB_OEN_V << PCR_CLK_BB_OEN_S) +#define PCR_CLK_BB_OEN_V 0x00000001U +#define PCR_CLK_BB_OEN_S 3 +/** PCR_CLK80_OEN : R/W; bitpos: [4]; default: 1; + * Set 1 to enable 80m clock + */ +#define PCR_CLK80_OEN (BIT(4)) +#define PCR_CLK80_OEN_M (PCR_CLK80_OEN_V << PCR_CLK80_OEN_S) +#define PCR_CLK80_OEN_V 0x00000001U +#define PCR_CLK80_OEN_S 4 +/** PCR_CLK160_OEN : R/W; bitpos: [5]; default: 1; + * Set 1 to enable 160m clock + */ +#define PCR_CLK160_OEN (BIT(5)) +#define PCR_CLK160_OEN_M (PCR_CLK160_OEN_V << PCR_CLK160_OEN_S) +#define PCR_CLK160_OEN_V 0x00000001U +#define PCR_CLK160_OEN_S 5 +/** PCR_CLK_320M_OEN : R/W; bitpos: [6]; default: 1; + * Set 1 to enable 320m clock + */ +#define PCR_CLK_320M_OEN (BIT(6)) +#define PCR_CLK_320M_OEN_M (PCR_CLK_320M_OEN_V << PCR_CLK_320M_OEN_S) +#define PCR_CLK_320M_OEN_V 0x00000001U +#define PCR_CLK_320M_OEN_S 6 +/** PCR_CLK_ADC_INF_OEN : R/W; bitpos: [7]; default: 1; + * Reserved + */ +#define PCR_CLK_ADC_INF_OEN (BIT(7)) +#define PCR_CLK_ADC_INF_OEN_M (PCR_CLK_ADC_INF_OEN_V << PCR_CLK_ADC_INF_OEN_S) +#define PCR_CLK_ADC_INF_OEN_V 0x00000001U +#define PCR_CLK_ADC_INF_OEN_S 7 +/** PCR_CLK_DAC_CPU_OEN : R/W; bitpos: [8]; default: 1; + * Reserved + */ +#define PCR_CLK_DAC_CPU_OEN (BIT(8)) +#define PCR_CLK_DAC_CPU_OEN_M (PCR_CLK_DAC_CPU_OEN_V << PCR_CLK_DAC_CPU_OEN_S) +#define PCR_CLK_DAC_CPU_OEN_V 0x00000001U +#define PCR_CLK_DAC_CPU_OEN_S 8 +/** PCR_CLK40X_BB_OEN : R/W; bitpos: [9]; default: 1; + * Set 1 to enable 40x_bb clock + */ +#define PCR_CLK40X_BB_OEN (BIT(9)) +#define PCR_CLK40X_BB_OEN_M (PCR_CLK40X_BB_OEN_V << PCR_CLK40X_BB_OEN_S) +#define PCR_CLK40X_BB_OEN_V 0x00000001U +#define PCR_CLK40X_BB_OEN_S 9 +/** PCR_CLK_XTAL_OEN : R/W; bitpos: [10]; default: 1; + * Set 1 to enable xtal clock + */ +#define PCR_CLK_XTAL_OEN (BIT(10)) +#define PCR_CLK_XTAL_OEN_M (PCR_CLK_XTAL_OEN_V << PCR_CLK_XTAL_OEN_S) +#define PCR_CLK_XTAL_OEN_V 0x00000001U +#define PCR_CLK_XTAL_OEN_S 10 + +/** PCR_CTRL_TICK_CONF_REG register + * TICK configuration register + */ +#define PCR_CTRL_TICK_CONF_REG (DR_REG_PCR_BASE + 0x130) +/** PCR_XTAL_TICK_NUM : R/W; bitpos: [7:0]; default: 39; + * ******* Description *********** + */ +#define PCR_XTAL_TICK_NUM 0x000000FFU +#define PCR_XTAL_TICK_NUM_M (PCR_XTAL_TICK_NUM_V << PCR_XTAL_TICK_NUM_S) +#define PCR_XTAL_TICK_NUM_V 0x000000FFU +#define PCR_XTAL_TICK_NUM_S 0 +/** PCR_FOSC_TICK_NUM : R/W; bitpos: [15:8]; default: 7; + * ******* Description *********** + */ +#define PCR_FOSC_TICK_NUM 0x000000FFU +#define PCR_FOSC_TICK_NUM_M (PCR_FOSC_TICK_NUM_V << PCR_FOSC_TICK_NUM_S) +#define PCR_FOSC_TICK_NUM_V 0x000000FFU +#define PCR_FOSC_TICK_NUM_S 8 +/** PCR_TICK_ENABLE : R/W; bitpos: [16]; default: 1; + * ******* Description *********** + */ +#define PCR_TICK_ENABLE (BIT(16)) +#define PCR_TICK_ENABLE_M (PCR_TICK_ENABLE_V << PCR_TICK_ENABLE_S) +#define PCR_TICK_ENABLE_V 0x00000001U +#define PCR_TICK_ENABLE_S 16 +/** PCR_RST_TICK_CNT : R/W; bitpos: [17]; default: 0; + * ******* Description *********** + */ +#define PCR_RST_TICK_CNT (BIT(17)) +#define PCR_RST_TICK_CNT_M (PCR_RST_TICK_CNT_V << PCR_RST_TICK_CNT_S) +#define PCR_RST_TICK_CNT_V 0x00000001U +#define PCR_RST_TICK_CNT_S 17 + +/** PCR_CTRL_32K_CONF_REG register + * 32KHz clock configuration register + */ +#define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x134) +/** PCR_32K_SEL : R/W; bitpos: [1:0]; default: 0; + * This field indicates which one 32KHz clock will be used by MODEM_SYSTEM and + * timergroup. 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. + */ +#define PCR_32K_SEL 0x00000003U +#define PCR_32K_SEL_M (PCR_32K_SEL_V << PCR_32K_SEL_S) +#define PCR_32K_SEL_V 0x00000003U +#define PCR_32K_SEL_S 0 + +/** PCR_SRAM_POWER_CONF_REG register + * HP SRAM/ROM configuration register + */ +#define PCR_SRAM_POWER_CONF_REG (DR_REG_PCR_BASE + 0x138) +/** PCR_SRAM_FORCE_PU : R/W; bitpos: [3:0]; default: 15; + * Set this bit to force power up SRAM + */ +#define PCR_SRAM_FORCE_PU 0x0000000FU +#define PCR_SRAM_FORCE_PU_M (PCR_SRAM_FORCE_PU_V << PCR_SRAM_FORCE_PU_S) +#define PCR_SRAM_FORCE_PU_V 0x0000000FU +#define PCR_SRAM_FORCE_PU_S 0 +/** PCR_SRAM_FORCE_PD : R/W; bitpos: [7:4]; default: 0; + * Set this bit to force power down SRAM. + */ +#define PCR_SRAM_FORCE_PD 0x0000000FU +#define PCR_SRAM_FORCE_PD_M (PCR_SRAM_FORCE_PD_V << PCR_SRAM_FORCE_PD_S) +#define PCR_SRAM_FORCE_PD_V 0x0000000FU +#define PCR_SRAM_FORCE_PD_S 4 +/** PCR_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [11:8]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A + * gate-clock will be used when accessing the SRAM. + */ +#define PCR_SRAM_CLKGATE_FORCE_ON 0x0000000FU +#define PCR_SRAM_CLKGATE_FORCE_ON_M (PCR_SRAM_CLKGATE_FORCE_ON_V << PCR_SRAM_CLKGATE_FORCE_ON_S) +#define PCR_SRAM_CLKGATE_FORCE_ON_V 0x0000000FU +#define PCR_SRAM_CLKGATE_FORCE_ON_S 8 +/** PCR_ROM_FORCE_PU : R/W; bitpos: [14:12]; default: 7; + * Set this bit to force power up ROM + */ +#define PCR_ROM_FORCE_PU 0x00000007U +#define PCR_ROM_FORCE_PU_M (PCR_ROM_FORCE_PU_V << PCR_ROM_FORCE_PU_S) +#define PCR_ROM_FORCE_PU_V 0x00000007U +#define PCR_ROM_FORCE_PU_S 12 +/** PCR_ROM_FORCE_PD : R/W; bitpos: [17:15]; default: 0; + * Set this bit to force power down ROM. + */ +#define PCR_ROM_FORCE_PD 0x00000007U +#define PCR_ROM_FORCE_PD_M (PCR_ROM_FORCE_PD_V << PCR_ROM_FORCE_PD_S) +#define PCR_ROM_FORCE_PD_V 0x00000007U +#define PCR_ROM_FORCE_PD_S 15 +/** PCR_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [20:18]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A + * gate-clock will be used when accessing the ROM. + */ +#define PCR_ROM_CLKGATE_FORCE_ON 0x00000007U +#define PCR_ROM_CLKGATE_FORCE_ON_M (PCR_ROM_CLKGATE_FORCE_ON_V << PCR_ROM_CLKGATE_FORCE_ON_S) +#define PCR_ROM_CLKGATE_FORCE_ON_V 0x00000007U +#define PCR_ROM_CLKGATE_FORCE_ON_S 18 + +/** PCR_RESET_EVENT_BYPASS_REG register + * reset event bypass backdoor configuration register + */ +#define PCR_RESET_EVENT_BYPASS_REG (DR_REG_PCR_BASE + 0xff0) +/** PCR_RESET_EVENT_BYPASS_APM : R/W; bitpos: [0]; default: 0; + * This field is used to control reset event relationship for + * tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset + * by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg + * will not only be reset by power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS_APM (BIT(0)) +#define PCR_RESET_EVENT_BYPASS_APM_M (PCR_RESET_EVENT_BYPASS_APM_V << PCR_RESET_EVENT_BYPASS_APM_S) +#define PCR_RESET_EVENT_BYPASS_APM_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_APM_S 0 +/** PCR_RESET_EVENT_BYPASS : R/W; bitpos: [1]; default: 1; + * This field is used to control reset event relationship for system-bus. 1: system + * bus (including arbiter/router) will only be reset by power-reset. some reset event + * will be bypass. 0: system bus (including arbiter/router) will not only be reset by + * power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS (BIT(1)) +#define PCR_RESET_EVENT_BYPASS_M (PCR_RESET_EVENT_BYPASS_V << PCR_RESET_EVENT_BYPASS_S) +#define PCR_RESET_EVENT_BYPASS_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_S 1 + +/** PCR_FPGA_DEBUG_REG register + * fpga debug register + */ +#define PCR_FPGA_DEBUG_REG (DR_REG_PCR_BASE + 0xff4) +/** PCR_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295; + * Only used in fpga debug. + */ +#define PCR_FPGA_DEBUG 0xFFFFFFFFU +#define PCR_FPGA_DEBUG_M (PCR_FPGA_DEBUG_V << PCR_FPGA_DEBUG_S) +#define PCR_FPGA_DEBUG_V 0xFFFFFFFFU +#define PCR_FPGA_DEBUG_S 0 + +/** PCR_CLOCK_GATE_REG register + * PCR clock gating configure register + */ +#define PCR_CLOCK_GATE_REG (DR_REG_PCR_BASE + 0xff8) +/** PCR_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to force on clock gating. + */ +#define PCR_CLK_EN (BIT(0)) +#define PCR_CLK_EN_M (PCR_CLK_EN_V << PCR_CLK_EN_S) +#define PCR_CLK_EN_V 0x00000001U +#define PCR_CLK_EN_S 0 + +/** PCR_DATE_REG register + * Date register. + */ +#define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc) +/** PCR_DATE : R/W; bitpos: [27:0]; default: 35676496; + * PCR version information. + */ +#define PCR_DATE 0x0FFFFFFFU +#define PCR_DATE_M (PCR_DATE_V << PCR_DATE_S) +#define PCR_DATE_V 0x0FFFFFFFU +#define PCR_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/pcr_struct.h b/components/soc/esp32c6/include/soc/pcr_struct.h new file mode 100644 index 0000000000..e7a1a13fa8 --- /dev/null +++ b/components/soc/esp32c6/include/soc/pcr_struct.h @@ -0,0 +1,1932 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of uart0_conf register + * UART0 configuration register + */ +typedef union { + struct { + /** uart0_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart0 apb clock + */ + uint32_t uart0_clk_en:1; + /** uart0_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart0 module + */ + uint32_t uart0_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_uart0_conf_reg_t; + +/** Type of uart0_sclk_conf register + * UART0_SCLK configuration register + */ +typedef union { + struct { + /** uart0_sclk_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart0 function clock. + */ + uint32_t uart0_sclk_div_a:6; + /** uart0_sclk_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart0 function clock. + */ + uint32_t uart0_sclk_div_b:6; + /** uart0_sclk_div_num : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart0 function clock. + */ + uint32_t uart0_sclk_div_num:8; + /** uart0_sclk_sel : R/W; bitpos: [21:20]; default: 3; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ + uint32_t uart0_sclk_sel:2; + /** uart0_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ + uint32_t uart0_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_uart0_sclk_conf_reg_t; + +/** Type of uart0_pd_ctrl register + * UART0 power control register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** uart0_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART0 memory. + */ + uint32_t uart0_mem_force_pu:1; + /** uart0_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART0 memory. + */ + uint32_t uart0_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_uart0_pd_ctrl_reg_t; + +/** Type of uart1_conf register + * UART1 configuration register + */ +typedef union { + struct { + /** uart1_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart1 apb clock + */ + uint32_t uart1_clk_en:1; + /** uart1_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart1 module + */ + uint32_t uart1_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_uart1_conf_reg_t; + +/** Type of uart1_sclk_conf register + * UART1_SCLK configuration register + */ +typedef union { + struct { + /** uart1_sclk_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart1 function clock. + */ + uint32_t uart1_sclk_div_a:6; + /** uart1_sclk_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart1 function clock. + */ + uint32_t uart1_sclk_div_b:6; + /** uart1_sclk_div_num : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart1 function clock. + */ + uint32_t uart1_sclk_div_num:8; + /** uart1_sclk_sel : R/W; bitpos: [21:20]; default: 3; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ + uint32_t uart1_sclk_sel:2; + /** uart1_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ + uint32_t uart1_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_uart1_sclk_conf_reg_t; + +/** Type of uart1_pd_ctrl register + * UART1 power control register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** uart1_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART1 memory. + */ + uint32_t uart1_mem_force_pu:1; + /** uart1_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART1 memory. + */ + uint32_t uart1_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_uart1_pd_ctrl_reg_t; + +/** Type of mspi_conf register + * MSPI configuration register + */ +typedef union { + struct { + /** mspi_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mspi clock, include mspi pll clock + */ + uint32_t mspi_clk_en:1; + /** mspi_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mspi module + */ + uint32_t mspi_rst_en:1; + /** mspi_pll_clk_en : R/W; bitpos: [2]; default: 1; + * Set 1 to enable mspi pll clock + */ + uint32_t mspi_pll_clk_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_mspi_conf_reg_t; + +/** Type of mspi_clk_conf register + * MSPI_CLK configuration register + */ +typedef union { + struct { + /** mspi_fast_ls_div_num : R/W; bitpos: [7:0]; default: 0; + * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed + * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a + * low-speed clock-source such as XTAL/FOSC. + */ + uint32_t mspi_fast_ls_div_num:8; + /** mspi_fast_hs_div_num : R/W; bitpos: [15:8]; default: 3; + * Set as one within (3,4,5) to generate div4(default)/div5/div6 of high-speed + * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a + * high-speed clock-source such as SPLL. + */ + uint32_t mspi_fast_hs_div_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} pcr_mspi_clk_conf_reg_t; + +/** Type of i2c_conf register + * I2C configuration register + */ +typedef union { + struct { + /** i2c_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2c apb clock + */ + uint32_t i2c_clk_en:1; + /** i2c_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2c module + */ + uint32_t i2c_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_i2c_conf_reg_t; + +/** Type of i2c_sclk_conf register + * I2C_SCLK configuration register + */ +typedef union { + struct { + /** i2c_sclk_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the i2c function clock. + */ + uint32_t i2c_sclk_div_a:6; + /** i2c_sclk_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the i2c function clock. + */ + uint32_t i2c_sclk_div_b:6; + /** i2c_sclk_div_num : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the i2c function clock. + */ + uint32_t i2c_sclk_div_num:8; + /** i2c_sclk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ + uint32_t i2c_sclk_sel:1; + uint32_t reserved_21:1; + /** i2c_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2c function clock + */ + uint32_t i2c_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_i2c_sclk_conf_reg_t; + +/** Type of uhci_conf register + * UHCI configuration register + */ +typedef union { + struct { + /** uhci_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uhci clock + */ + uint32_t uhci_clk_en:1; + /** uhci_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uhci module + */ + uint32_t uhci_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_uhci_conf_reg_t; + +/** Type of rmt_conf register + * RMT configuration register + */ +typedef union { + struct { + /** rmt_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rmt apb clock + */ + uint32_t rmt_clk_en:1; + /** rmt_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rmt module + */ + uint32_t rmt_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_rmt_conf_reg_t; + +/** Type of rmt_sclk_conf register + * RMT_SCLK configuration register + */ +typedef union { + struct { + /** rmt_sclk_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the rmt function clock. + */ + uint32_t rmt_sclk_div_a:6; + /** rmt_sclk_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the rmt function clock. + */ + uint32_t rmt_sclk_div_b:6; + /** rmt_sclk_div_num : R/W; bitpos: [19:12]; default: 1; + * The integral part of the frequency divider factor of the rmt function clock. + */ + uint32_t rmt_sclk_div_num:8; + /** rmt_sclk_sel : R/W; bitpos: [21:20]; default: 1; + * set this field to select clock-source. 0: do not select anyone clock, 1(default): + * 80MHz, 2: FOSC, 3: XTAL. + */ + uint32_t rmt_sclk_sel:2; + /** rmt_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable rmt function clock + */ + uint32_t rmt_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_rmt_sclk_conf_reg_t; + +/** Type of ledc_conf register + * LEDC configuration register + */ +typedef union { + struct { + /** ledc_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ledc apb clock + */ + uint32_t ledc_clk_en:1; + /** ledc_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ledc module + */ + uint32_t ledc_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_ledc_conf_reg_t; + +/** Type of ledc_sclk_conf register + * LEDC_SCLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** ledc_sclk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): do not select anyone clock, 1: + * 80MHz, 2: FOSC, 3: XTAL. + */ + uint32_t ledc_sclk_sel:2; + /** ledc_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable ledc function clock + */ + uint32_t ledc_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_ledc_sclk_conf_reg_t; + +/** Type of timergroup0_conf register + * TIMERGROUP0 configuration register + */ +typedef union { + struct { + /** tg0_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group0 apb clock + */ + uint32_t tg0_clk_en:1; + /** tg0_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group0 module + */ + uint32_t tg0_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_timergroup0_conf_reg_t; + +/** Type of timergroup0_timer_clk_conf register + * TIMERGROUP0_TIMER_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tg0_timer_clk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t tg0_timer_clk_sel:2; + /** tg0_timer_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 timer clock + */ + uint32_t tg0_timer_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_timergroup0_timer_clk_conf_reg_t; + +/** Type of timergroup0_wdt_clk_conf register + * TIMERGROUP0_WDT_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tg0_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t tg0_wdt_clk_sel:2; + /** tg0_wdt_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ + uint32_t tg0_wdt_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_timergroup0_wdt_clk_conf_reg_t; + +/** Type of timergroup1_conf register + * TIMERGROUP1 configuration register + */ +typedef union { + struct { + /** tg1_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group1 apb clock + */ + uint32_t tg1_clk_en:1; + /** tg1_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 module + */ + uint32_t tg1_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_timergroup1_conf_reg_t; + +/** Type of timergroup1_timer_clk_conf register + * TIMERGROUP1_TIMER_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tg1_timer_clk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t tg1_timer_clk_sel:2; + /** tg1_timer_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group1 timer clock + */ + uint32_t tg1_timer_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_timergroup1_timer_clk_conf_reg_t; + +/** Type of timergroup1_wdt_clk_conf register + * TIMERGROUP1_WDT_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tg1_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t tg1_wdt_clk_sel:2; + /** tg1_wdt_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ + uint32_t tg1_wdt_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_timergroup1_wdt_clk_conf_reg_t; + +/** Type of systimer_conf register + * SYSTIMER configuration register + */ +typedef union { + struct { + /** systimer_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable systimer apb clock + */ + uint32_t systimer_clk_en:1; + /** systimer_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset systimer module + */ + uint32_t systimer_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_systimer_conf_reg_t; + +/** Type of systimer_func_clk_conf register + * SYSTIMER_FUNC_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** systimer_func_clk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ + uint32_t systimer_func_clk_sel:1; + uint32_t reserved_21:1; + /** systimer_func_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable systimer function clock + */ + uint32_t systimer_func_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_systimer_func_clk_conf_reg_t; + +/** Type of twai0_conf register + * TWAI0 configuration register + */ +typedef union { + struct { + /** twai0_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable twai0 apb clock + */ + uint32_t twai0_clk_en:1; + /** twai0_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset twai0 module + */ + uint32_t twai0_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_twai0_conf_reg_t; + +/** Type of twai0_func_clk_conf register + * TWAI0_FUNC_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** twai0_func_clk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ + uint32_t twai0_func_clk_sel:1; + uint32_t reserved_21:1; + /** twai0_func_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable twai0 function clock + */ + uint32_t twai0_func_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_twai0_func_clk_conf_reg_t; + +/** Type of twai1_conf register + * TWAI1 configuration register + */ +typedef union { + struct { + /** twai1_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable twai1 apb clock + */ + uint32_t twai1_clk_en:1; + /** twai1_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset twai1 module + */ + uint32_t twai1_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_twai1_conf_reg_t; + +/** Type of twai1_func_clk_conf register + * TWAI1_FUNC_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** twai1_func_clk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ + uint32_t twai1_func_clk_sel:1; + uint32_t reserved_21:1; + /** twai1_func_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable twai1 function clock + */ + uint32_t twai1_func_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_twai1_func_clk_conf_reg_t; + +/** Type of i2s_conf register + * I2S configuration register + */ +typedef union { + struct { + /** i2s_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2s apb clock + */ + uint32_t i2s_clk_en:1; + /** i2s_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2s module + */ + uint32_t i2s_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_i2s_conf_reg_t; + +/** Type of i2s_tx_clkm_conf register + * I2S_TX_CLKM configuration register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** i2s_tx_clkm_div_num : R/W; bitpos: [19:12]; default: 2; + * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be + * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= + * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * + * (n+1)-div] + y * (n+1)-div. + */ + uint32_t i2s_tx_clkm_div_num:8; + /** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: + * I2S_MCLK_in. + */ + uint32_t i2s_tx_clkm_sel:2; + /** i2s_tx_clkm_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_tx function clock + */ + uint32_t i2s_tx_clkm_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_i2s_tx_clkm_conf_reg_t; + +/** Type of i2s_tx_clkm_div_conf register + * I2S_TX_CLKM_DIV configuration register + */ +typedef union { + struct { + /** i2s_tx_clkm_div_z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_TX_CLKM_DIV_Z is (a-b). + */ + uint32_t i2s_tx_clkm_div_z:9; + /** i2s_tx_clkm_div_y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_TX_CLKM_DIV_Y is (a%(a-b)). + */ + uint32_t i2s_tx_clkm_div_y:9; + /** i2s_tx_clkm_div_x : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + */ + uint32_t i2s_tx_clkm_div_x:9; + /** i2s_tx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_TX_CLKM_DIV_YN1 is 1. + */ + uint32_t i2s_tx_clkm_div_yn1:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} pcr_i2s_tx_clkm_div_conf_reg_t; + +/** Type of i2s_rx_clkm_conf register + * I2S_RX_CLKM configuration register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** i2s_rx_clkm_div_num : R/W; bitpos: [19:12]; default: 2; + * Integral I2S clock divider value + */ + uint32_t i2s_rx_clkm_div_num:8; + /** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in. + */ + uint32_t i2s_rx_clkm_sel:2; + /** i2s_rx_clkm_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_rx function clock + */ + uint32_t i2s_rx_clkm_en:1; + /** i2s_mclk_sel : R/W; bitpos: [23]; default: 0; + * This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx + */ + uint32_t i2s_mclk_sel:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} pcr_i2s_rx_clkm_conf_reg_t; + +/** Type of i2s_rx_clkm_div_conf register + * I2S_RX_CLKM_DIV configuration register + */ +typedef union { + struct { + /** i2s_rx_clkm_div_z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_RX_CLKM_DIV_Z is (a-b). + */ + uint32_t i2s_rx_clkm_div_z:9; + /** i2s_rx_clkm_div_y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_RX_CLKM_DIV_Y is (a%(a-b)). + */ + uint32_t i2s_rx_clkm_div_y:9; + /** i2s_rx_clkm_div_x : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + */ + uint32_t i2s_rx_clkm_div_x:9; + /** i2s_rx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_RX_CLKM_DIV_YN1 is 1. + */ + uint32_t i2s_rx_clkm_div_yn1:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} pcr_i2s_rx_clkm_div_conf_reg_t; + +/** Type of saradc_conf register + * SARADC configuration register + */ +typedef union { + struct { + /** saradc_clk_en : R/W; bitpos: [0]; default: 1; + * no use + */ + uint32_t saradc_clk_en:1; + /** saradc_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset function_register of saradc module + */ + uint32_t saradc_rst_en:1; + /** saradc_reg_clk_en : R/W; bitpos: [2]; default: 1; + * Set 1 to enable saradc apb clock + */ + uint32_t saradc_reg_clk_en:1; + /** saradc_reg_rst_en : R/W; bitpos: [3]; default: 0; + * Set 0 to reset apb_register of saradc module + */ + uint32_t saradc_reg_rst_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcr_saradc_conf_reg_t; + +/** Type of saradc_clkm_conf register + * SARADC_CLKM configuration register + */ +typedef union { + struct { + /** saradc_clkm_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the saradc function clock. + */ + uint32_t saradc_clkm_div_a:6; + /** saradc_clkm_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the saradc function clock. + */ + uint32_t saradc_clkm_div_b:6; + /** saradc_clkm_div_num : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the saradc function clock. + */ + uint32_t saradc_clkm_div_num:8; + /** saradc_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t saradc_clkm_sel:2; + /** saradc_clkm_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable saradc function clock + */ + uint32_t saradc_clkm_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_saradc_clkm_conf_reg_t; + +/** Type of tsens_clk_conf register + * TSENS_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tsens_clk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): FOSC, 1: XTAL. + */ + uint32_t tsens_clk_sel:1; + uint32_t reserved_21:1; + /** tsens_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable tsens clock + */ + uint32_t tsens_clk_en:1; + /** tsens_rst_en : R/W; bitpos: [23]; default: 0; + * Set 0 to reset tsens module + */ + uint32_t tsens_rst_en:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} pcr_tsens_clk_conf_reg_t; + +/** Type of usb_device_conf register + * USB_DEVICE configuration register + */ +typedef union { + struct { + /** usb_device_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable usb_device clock + */ + uint32_t usb_device_clk_en:1; + /** usb_device_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset usb_device module + */ + uint32_t usb_device_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_usb_device_conf_reg_t; + +/** Type of intmtx_conf register + * INTMTX configuration register + */ +typedef union { + struct { + /** intmtx_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable intmtx clock + */ + uint32_t intmtx_clk_en:1; + /** intmtx_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset intmtx module + */ + uint32_t intmtx_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_intmtx_conf_reg_t; + +/** Type of pcnt_conf register + * PCNT configuration register + */ +typedef union { + struct { + /** pcnt_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable pcnt clock + */ + uint32_t pcnt_clk_en:1; + /** pcnt_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset pcnt module + */ + uint32_t pcnt_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_pcnt_conf_reg_t; + +/** Type of etm_conf register + * ETM configuration register + */ +typedef union { + struct { + /** etm_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable etm clock + */ + uint32_t etm_clk_en:1; + /** etm_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset etm module + */ + uint32_t etm_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_etm_conf_reg_t; + +/** Type of pwm_conf register + * PWM configuration register + */ +typedef union { + struct { + /** pwm_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable pwm clock + */ + uint32_t pwm_clk_en:1; + /** pwm_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset pwm module + */ + uint32_t pwm_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_pwm_conf_reg_t; + +/** Type of pwm_clk_conf register + * PWM_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** pwm_div_num : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the pwm function clock. + */ + uint32_t pwm_div_num:8; + /** pwm_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): do not select anyone clock, 1: + * 160MHz, 2: XTAL, 3: FOSC. + */ + uint32_t pwm_clkm_sel:2; + /** pwm_clkm_en : R/W; bitpos: [22]; default: 1; + * set this field as 1 to activate pwm clkm. + */ + uint32_t pwm_clkm_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_pwm_clk_conf_reg_t; + +/** Type of parl_io_conf register + * PARL_IO configuration register + */ +typedef union { + struct { + /** parl_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable parl apb clock + */ + uint32_t parl_clk_en:1; + /** parl_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset parl apb reg + */ + uint32_t parl_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_parl_io_conf_reg_t; + +/** Type of parl_clk_rx_conf register + * PARL_CLK_RX configuration register + */ +typedef union { + struct { + /** parl_clk_rx_div_num : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl rx clock. + */ + uint32_t parl_clk_rx_div_num:16; + /** parl_clk_rx_sel : R/W; bitpos: [17:16]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * user clock from pad. + */ + uint32_t parl_clk_rx_sel:2; + /** parl_clk_rx_en : R/W; bitpos: [18]; default: 1; + * Set 1 to enable parl rx clock + */ + uint32_t parl_clk_rx_en:1; + /** parl_rx_rst_en : R/W; bitpos: [19]; default: 0; + * Set 0 to reset parl rx module + */ + uint32_t parl_rx_rst_en:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} pcr_parl_clk_rx_conf_reg_t; + +/** Type of parl_clk_tx_conf register + * PARL_CLK_TX configuration register + */ +typedef union { + struct { + /** parl_clk_tx_div_num : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl tx clock. + */ + uint32_t parl_clk_tx_div_num:16; + /** parl_clk_tx_sel : R/W; bitpos: [17:16]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * user clock from pad. + */ + uint32_t parl_clk_tx_sel:2; + /** parl_clk_tx_en : R/W; bitpos: [18]; default: 1; + * Set 1 to enable parl tx clock + */ + uint32_t parl_clk_tx_en:1; + /** parl_tx_rst_en : R/W; bitpos: [19]; default: 0; + * Set 0 to reset parl tx module + */ + uint32_t parl_tx_rst_en:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} pcr_parl_clk_tx_conf_reg_t; + +/** Type of sdio_slave_conf register + * SDIO_SLAVE configuration register + */ +typedef union { + struct { + /** sdio_slave_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sdio_slave clock + */ + uint32_t sdio_slave_clk_en:1; + /** sdio_slave_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset sdio_slave module + */ + uint32_t sdio_slave_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_sdio_slave_conf_reg_t; + +/** Type of pvt_monitor_conf register + * PVT_MONITOR configuration register + */ +typedef union { + struct { + /** pvt_monitor_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable apb clock of pvt module + */ + uint32_t pvt_monitor_clk_en:1; + /** pvt_monitor_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset all pvt monitor module + */ + uint32_t pvt_monitor_rst_en:1; + /** pvt_monitor_site1_clk_en : R/W; bitpos: [2]; default: 1; + * Set 1 to enable function clock of modem pvt module + */ + uint32_t pvt_monitor_site1_clk_en:1; + /** pvt_monitor_site2_clk_en : R/W; bitpos: [3]; default: 1; + * Set 1 to enable function clock of cpu pvt module + */ + uint32_t pvt_monitor_site2_clk_en:1; + /** pvt_monitor_site3_clk_en : R/W; bitpos: [4]; default: 1; + * Set 1 to enable function clock of hp_peri pvt module + */ + uint32_t pvt_monitor_site3_clk_en:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} pcr_pvt_monitor_conf_reg_t; + +/** Type of pvt_monitor_func_clk_conf register + * PVT_MONITOR function clock configuration register + */ +typedef union { + struct { + /** pvt_monitor_func_clk_div_num : R/W; bitpos: [3:0]; default: 0; + * The integral part of the frequency divider factor of the pvt_monitor function clock. + */ + uint32_t pvt_monitor_func_clk_div_num:4; + uint32_t reserved_4:16; + /** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL + * divided by 3. + */ + uint32_t pvt_monitor_func_clk_sel:1; + uint32_t reserved_21:1; + /** pvt_monitor_func_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable source clock of pvt sitex + */ + uint32_t pvt_monitor_func_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_pvt_monitor_func_clk_conf_reg_t; + +/** Type of gdma_conf register + * GDMA configuration register + */ +typedef union { + struct { + /** gdma_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable gdma clock + */ + uint32_t gdma_clk_en:1; + /** gdma_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset gdma module + */ + uint32_t gdma_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_gdma_conf_reg_t; + +/** Type of spi2_conf register + * SPI2 configuration register + */ +typedef union { + struct { + /** spi2_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable spi2 apb clock + */ + uint32_t spi2_clk_en:1; + /** spi2_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset spi2 module + */ + uint32_t spi2_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_spi2_conf_reg_t; + +/** Type of spi2_clkm_conf register + * SPI2_CLKM configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** spi2_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t spi2_clkm_sel:2; + /** spi2_clkm_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable spi2 function clock + */ + uint32_t spi2_clkm_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_spi2_clkm_conf_reg_t; + +/** Type of aes_conf register + * AES configuration register + */ +typedef union { + struct { + /** aes_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable aes clock + */ + uint32_t aes_clk_en:1; + /** aes_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset aes module + */ + uint32_t aes_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_aes_conf_reg_t; + +/** Type of sha_conf register + * SHA configuration register + */ +typedef union { + struct { + /** sha_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sha clock + */ + uint32_t sha_clk_en:1; + /** sha_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset sha module + */ + uint32_t sha_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_sha_conf_reg_t; + +/** Type of rsa_conf register + * RSA configuration register + */ +typedef union { + struct { + /** rsa_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rsa clock + */ + uint32_t rsa_clk_en:1; + /** rsa_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rsa module + */ + uint32_t rsa_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_rsa_conf_reg_t; + +/** Type of rsa_pd_ctrl register + * RSA power control register + */ +typedef union { + struct { + /** rsa_mem_pd : R/W; bitpos: [0]; default: 0; + * Set this bit to power down rsa internal memory. + */ + uint32_t rsa_mem_pd:1; + /** rsa_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up rsa internal memory + */ + uint32_t rsa_mem_force_pu:1; + /** rsa_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down rsa internal memory. + */ + uint32_t rsa_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_rsa_pd_ctrl_reg_t; + +/** Type of ecc_conf register + * ECC configuration register + */ +typedef union { + struct { + /** ecc_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecc clock + */ + uint32_t ecc_clk_en:1; + /** ecc_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ecc module + */ + uint32_t ecc_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_ecc_conf_reg_t; + +/** Type of ecc_pd_ctrl register + * ECC power control register + */ +typedef union { + struct { + /** ecc_mem_pd : R/W; bitpos: [0]; default: 0; + * Set this bit to power down ecc internal memory. + */ + uint32_t ecc_mem_pd:1; + /** ecc_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up ecc internal memory + */ + uint32_t ecc_mem_force_pu:1; + /** ecc_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down ecc internal memory. + */ + uint32_t ecc_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_ecc_pd_ctrl_reg_t; + +/** Type of ds_conf register + * DS configuration register + */ +typedef union { + struct { + /** ds_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ds clock + */ + uint32_t ds_clk_en:1; + /** ds_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ds module + */ + uint32_t ds_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_ds_conf_reg_t; + +/** Type of hmac_conf register + * HMAC configuration register + */ +typedef union { + struct { + /** hmac_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable hmac clock + */ + uint32_t hmac_clk_en:1; + /** hmac_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset hmac module + */ + uint32_t hmac_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_hmac_conf_reg_t; + +/** Type of iomux_conf register + * IOMUX configuration register + */ +typedef union { + struct { + /** iomux_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable iomux apb clock + */ + uint32_t iomux_clk_en:1; + /** iomux_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset iomux module + */ + uint32_t iomux_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_iomux_conf_reg_t; + +/** Type of iomux_clk_conf register + * IOMUX_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** iomux_func_clk_sel : R/W; bitpos: [21:20]; default: 3; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ + uint32_t iomux_func_clk_sel:2; + /** iomux_func_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable iomux function clock + */ + uint32_t iomux_func_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_iomux_clk_conf_reg_t; + +/** Type of mem_monitor_conf register + * MEM_MONITOR configuration register + */ +typedef union { + struct { + /** mem_monitor_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mem_monitor clock + */ + uint32_t mem_monitor_clk_en:1; + /** mem_monitor_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mem_monitor module + */ + uint32_t mem_monitor_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_mem_monitor_conf_reg_t; + +/** Type of regdma_conf register + * REGDMA configuration register + */ +typedef union { + struct { + /** regdma_clk_en : R/W; bitpos: [0]; default: 0; + * Set 1 to enable regdma clock + */ + uint32_t regdma_clk_en:1; + /** regdma_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset regdma module + */ + uint32_t regdma_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_regdma_conf_reg_t; + +/** Type of retention_conf register + * retention configuration register + */ +typedef union { + struct { + /** retention_clk_en : R/W; bitpos: [0]; default: 0; + * Set 1 to enable retention clock + */ + uint32_t retention_clk_en:1; + /** retention_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset retention module + */ + uint32_t retention_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_retention_conf_reg_t; + +/** Type of trace_conf register + * TRACE configuration register + */ +typedef union { + struct { + /** trace_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable trace clock + */ + uint32_t trace_clk_en:1; + /** trace_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset trace module + */ + uint32_t trace_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_trace_conf_reg_t; + +/** Type of assist_conf register + * ASSIST configuration register + */ +typedef union { + struct { + /** assist_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable assist clock + */ + uint32_t assist_clk_en:1; + /** assist_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset assist module + */ + uint32_t assist_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_assist_conf_reg_t; + +/** Type of cache_conf register + * CACHE configuration register + */ +typedef union { + struct { + /** cache_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable cache clock + */ + uint32_t cache_clk_en:1; + /** cache_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cache module + */ + uint32_t cache_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_cache_conf_reg_t; + +/** Type of modem_apb_conf register + * MODEM_APB configuration register + */ +typedef union { + struct { + /** modem_apb_clk_en : R/W; bitpos: [0]; default: 1; + * This field indicates if modem_apb clock is enable. 0: disable, 1: enable(default). + */ + uint32_t modem_apb_clk_en:1; + /** modem_rst_en : R/W; bitpos: [1]; default: 0; + * Set this file as 1 to reset modem-subsystem. + */ + uint32_t modem_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_modem_apb_conf_reg_t; + +/** Type of timeout_conf register + * TIMEOUT configuration register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** cpu_timeout_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cpu_peri timeout module + */ + uint32_t cpu_timeout_rst_en:1; + /** hp_timeout_rst_en : R/W; bitpos: [2]; default: 0; + * Set 0 to reset hp_peri timeout module and hp_modem timeout module + */ + uint32_t hp_timeout_rst_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_timeout_conf_reg_t; + +/** Type of sysclk_conf register + * SYSCLK configuration register + */ +typedef union { + struct { + /** ls_div_num : HRO; bitpos: [7:0]; default: 0; + * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed + * clock-source such as XTAL/FOSC. + */ + uint32_t ls_div_num:8; + /** hs_div_num : HRO; bitpos: [15:8]; default: 2; + * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + */ + uint32_t hs_div_num:8; + /** soc_clk_sel : R/W; bitpos: [17:16]; default: 0; + * This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved. + */ + uint32_t soc_clk_sel:2; + uint32_t reserved_18:6; + /** clk_xtal_freq : RO; bitpos: [30:24]; default: 40; + * This field indicates the frequency(MHz) of XTAL. + */ + uint32_t clk_xtal_freq:7; + uint32_t reserved_31:1; + }; + uint32_t val; +} pcr_sysclk_conf_reg_t; + +/** Type of cpu_waiti_conf register + * CPU_WAITI configuration register + */ +typedef union { + struct { + /** cpuperiod_sel : HRO; bitpos: [1:0]; default: 1; + * Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM + */ + uint32_t cpuperiod_sel:2; + /** pll_freq_sel : HRO; bitpos: [2]; default: 1; + * Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM + */ + uint32_t pll_freq_sel:1; + /** cpu_wait_mode_force_on : R/W; bitpos: [3]; default: 1; + * Set 1 to force cpu_waiti_clk enable. + */ + uint32_t cpu_wait_mode_force_on:1; + /** cpu_waiti_delay_num : R/W; bitpos: [7:4]; default: 0; + * This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk + * will close + */ + uint32_t cpu_waiti_delay_num:4; + uint32_t reserved_8:24; + }; + uint32_t val; +} pcr_cpu_waiti_conf_reg_t; + +/** Type of cpu_freq_conf register + * CPU_FREQ configuration register + */ +typedef union { + struct { + /** cpu_ls_div_num : R/W; bitpos: [7:0]; default: 0; + * Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed + * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_LS_DIV_NUM. + */ + uint32_t cpu_ls_div_num:8; + /** cpu_hs_div_num : R/W; bitpos: [15:8]; default: 0; + * Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for high-speed + * clock-source such as SPLL, and should be used together with PCR_AHB_HS_DIV_NUM. + */ + uint32_t cpu_hs_div_num:8; + /** cpu_hs_120m_force : R/W; bitpos: [16]; default: 0; + * Given that PCR_CPU_HS_DIV_NUM is 0, set this field as 1 to force clk_cpu at 120MHz. + * Only avaliable when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL. + */ + uint32_t cpu_hs_120m_force:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} pcr_cpu_freq_conf_reg_t; + +/** Type of ahb_freq_conf register + * AHB_FREQ configuration register + */ +typedef union { + struct { + /** ahb_ls_div_num : R/W; bitpos: [7:0]; default: 0; + * Set as one within (0,1,3,7) to generate clk_ahb drived by clk_hproot. The clk_ahb + * is div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for + * low-speed clock-source such as XTAL/FOSC, and should be used together with + * PCR_CPU_LS_DIV_NUM. + */ + uint32_t ahb_ls_div_num:8; + /** ahb_hs_div_num : R/W; bitpos: [15:8]; default: 3; + * Set as one within (3,7,15) to generate clk_ahb drived by clk_hproot. The clk_ahb is + * div4(default)/div8/div16 of clk_hproot. This field is only avaliable for high-speed + * clock-source such as SPLL, and should be used together with PCR_CPU_HS_DIV_NUM. + */ + uint32_t ahb_hs_div_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} pcr_ahb_freq_conf_reg_t; + +/** Type of apb_freq_conf register + * APB_FREQ configuration register + */ +typedef union { + struct { + /** apb_decrease_div_num : R/W; bitpos: [7:0]; default: 0; + * If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be + * automatically down to clk_apb_decrease only when no access is on apb-bus, and will + * recover to the previous frequency when a new access appears on apb-bus. Set as one + * within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note + * that enable this function will reduce performance. Users can set this field as zero + * to disable the auto-decrease-apb-freq function. By default, this function is + * disable. + */ + uint32_t apb_decrease_div_num:8; + /** apb_div_num : R/W; bitpos: [15:8]; default: 0; + * Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is + * div1(default)/div2/div4 of clk_ahb. + */ + uint32_t apb_div_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} pcr_apb_freq_conf_reg_t; + +/** Type of pll_div_clk_en register + * SPLL DIV clock-gating configuration register + */ +typedef union { + struct { + /** pll_240m_clk_en : R/W; bitpos: [0]; default: 1; + * This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_240m_clk_en:1; + /** pll_160m_clk_en : R/W; bitpos: [1]; default: 1; + * This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_160m_clk_en:1; + /** pll_120m_clk_en : R/W; bitpos: [2]; default: 1; + * This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_120m_clk_en:1; + /** pll_80m_clk_en : R/W; bitpos: [3]; default: 1; + * This field is used to open 80 MHz clock (div6 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_80m_clk_en:1; + /** pll_48m_clk_en : R/W; bitpos: [4]; default: 1; + * This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_48m_clk_en:1; + /** pll_40m_clk_en : R/W; bitpos: [5]; default: 1; + * This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_40m_clk_en:1; + /** pll_20m_clk_en : R/W; bitpos: [6]; default: 1; + * This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_20m_clk_en:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} pcr_pll_div_clk_en_reg_t; + +/** Type of ctrl_clk_out_en register + * CLK_OUT_EN configuration register + */ +typedef union { + struct { + /** clk20_oen : R/W; bitpos: [0]; default: 1; + * Set 1 to enable 20m clock + */ + uint32_t clk20_oen:1; + /** clk22_oen : R/W; bitpos: [1]; default: 1; + * Set 1 to enable 22m clock + */ + uint32_t clk22_oen:1; + /** clk44_oen : R/W; bitpos: [2]; default: 1; + * Set 1 to enable 44m clock + */ + uint32_t clk44_oen:1; + /** clk_bb_oen : R/W; bitpos: [3]; default: 1; + * Set 1 to enable bb clock + */ + uint32_t clk_bb_oen:1; + /** clk80_oen : R/W; bitpos: [4]; default: 1; + * Set 1 to enable 80m clock + */ + uint32_t clk80_oen:1; + /** clk160_oen : R/W; bitpos: [5]; default: 1; + * Set 1 to enable 160m clock + */ + uint32_t clk160_oen:1; + /** clk_320m_oen : R/W; bitpos: [6]; default: 1; + * Set 1 to enable 320m clock + */ + uint32_t clk_320m_oen:1; + /** clk_adc_inf_oen : R/W; bitpos: [7]; default: 1; + * Reserved + */ + uint32_t clk_adc_inf_oen:1; + /** clk_dac_cpu_oen : R/W; bitpos: [8]; default: 1; + * Reserved + */ + uint32_t clk_dac_cpu_oen:1; + /** clk40x_bb_oen : R/W; bitpos: [9]; default: 1; + * Set 1 to enable 40x_bb clock + */ + uint32_t clk40x_bb_oen:1; + /** clk_xtal_oen : R/W; bitpos: [10]; default: 1; + * Set 1 to enable xtal clock + */ + uint32_t clk_xtal_oen:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} pcr_ctrl_clk_out_en_reg_t; + +/** Type of ctrl_tick_conf register + * TICK configuration register + */ +typedef union { + struct { + /** xtal_tick_num : R/W; bitpos: [7:0]; default: 39; + * ******* Description *********** + */ + uint32_t xtal_tick_num:8; + /** fosc_tick_num : R/W; bitpos: [15:8]; default: 7; + * ******* Description *********** + */ + uint32_t fosc_tick_num:8; + /** tick_enable : R/W; bitpos: [16]; default: 1; + * ******* Description *********** + */ + uint32_t tick_enable:1; + /** rst_tick_cnt : R/W; bitpos: [17]; default: 0; + * ******* Description *********** + */ + uint32_t rst_tick_cnt:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} pcr_ctrl_tick_conf_reg_t; + +/** Type of ctrl_32k_conf register + * 32KHz clock configuration register + */ +typedef union { + struct { + /** clk_32k_sel : R/W; bitpos: [1:0]; default: 0; + * This field indicates which one 32KHz clock will be used by MODEM_SYSTEM and + * timergroup. 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. + */ + uint32_t clk_32k_sel:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_ctrl_32k_conf_reg_t; + +/** Type of sram_power_conf register + * HP SRAM/ROM configuration register + */ +typedef union { + struct { + /** sram_force_pu : R/W; bitpos: [3:0]; default: 15; + * Set this bit to force power up SRAM + */ + uint32_t sram_force_pu:4; + /** sram_force_pd : R/W; bitpos: [7:4]; default: 0; + * Set this bit to force power down SRAM. + */ + uint32_t sram_force_pd:4; + /** sram_clkgate_force_on : R/W; bitpos: [11:8]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A + * gate-clock will be used when accessing the SRAM. + */ + uint32_t sram_clkgate_force_on:4; + /** rom_force_pu : R/W; bitpos: [14:12]; default: 7; + * Set this bit to force power up ROM + */ + uint32_t rom_force_pu:3; + /** rom_force_pd : R/W; bitpos: [17:15]; default: 0; + * Set this bit to force power down ROM. + */ + uint32_t rom_force_pd:3; + /** rom_clkgate_force_on : R/W; bitpos: [20:18]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A + * gate-clock will be used when accessing the ROM. + */ + uint32_t rom_clkgate_force_on:3; + uint32_t reserved_21:11; + }; + uint32_t val; +} pcr_sram_power_conf_reg_t; + +/** Type of reset_event_bypass register + * reset event bypass backdoor configuration register + */ +typedef union { + struct { + /** reset_event_bypass_apm : R/W; bitpos: [0]; default: 0; + * This field is used to control reset event relationship for + * tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset + * by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg + * will not only be reset by power-reset, but also some reset event. + */ + uint32_t reset_event_bypass_apm:1; + /** reset_event_bypass : R/W; bitpos: [1]; default: 1; + * This field is used to control reset event relationship for system-bus. 1: system + * bus (including arbiter/router) will only be reset by power-reset. some reset event + * will be bypass. 0: system bus (including arbiter/router) will not only be reset by + * power-reset, but also some reset event. + */ + uint32_t reset_event_bypass:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_reset_event_bypass_reg_t; + +/** Type of clock_gate register + * PCR clock gating configure register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to force on clock gating. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} pcr_clock_gate_reg_t; + + +/** Group: Frequency Statistics Register */ +/** Type of sysclk_freq_query_0 register + * SYSCLK frequency query 0 register + */ +typedef union { + struct { + /** fosc_freq : HRO; bitpos: [7:0]; default: 20; + * This field indicates the frequency(MHz) of FOSC. + */ + uint32_t fosc_freq:8; + /** pll_freq : HRO; bitpos: [17:8]; default: 480; + * This field indicates the frequency(MHz) of SPLL. + */ + uint32_t pll_freq:10; + uint32_t reserved_18:14; + }; + uint32_t val; +} pcr_sysclk_freq_query_0_reg_t; + + +/** Group: FPGA Debug Register */ +/** Type of fpga_debug register + * fpga debug register + */ +typedef union { + struct { + /** fpga_debug : R/W; bitpos: [31:0]; default: 4294967295; + * Only used in fpga debug. + */ + uint32_t fpga_debug:32; + }; + uint32_t val; +} pcr_fpga_debug_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35676496; + * PCR version information. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} pcr_date_reg_t; + + +typedef struct pcr_dev_t { + volatile pcr_uart0_conf_reg_t uart0_conf; + volatile pcr_uart0_sclk_conf_reg_t uart0_sclk_conf; + volatile pcr_uart0_pd_ctrl_reg_t uart0_pd_ctrl; + volatile pcr_uart1_conf_reg_t uart1_conf; + volatile pcr_uart1_sclk_conf_reg_t uart1_sclk_conf; + volatile pcr_uart1_pd_ctrl_reg_t uart1_pd_ctrl; + volatile pcr_mspi_conf_reg_t mspi_conf; + volatile pcr_mspi_clk_conf_reg_t mspi_clk_conf; + volatile pcr_i2c_conf_reg_t i2c_conf; + volatile pcr_i2c_sclk_conf_reg_t i2c_sclk_conf; + volatile pcr_uhci_conf_reg_t uhci_conf; + volatile pcr_rmt_conf_reg_t rmt_conf; + volatile pcr_rmt_sclk_conf_reg_t rmt_sclk_conf; + volatile pcr_ledc_conf_reg_t ledc_conf; + volatile pcr_ledc_sclk_conf_reg_t ledc_sclk_conf; + volatile pcr_timergroup0_conf_reg_t timergroup0_conf; + volatile pcr_timergroup0_timer_clk_conf_reg_t timergroup0_timer_clk_conf; + volatile pcr_timergroup0_wdt_clk_conf_reg_t timergroup0_wdt_clk_conf; + volatile pcr_timergroup1_conf_reg_t timergroup1_conf; + volatile pcr_timergroup1_timer_clk_conf_reg_t timergroup1_timer_clk_conf; + volatile pcr_timergroup1_wdt_clk_conf_reg_t timergroup1_wdt_clk_conf; + volatile pcr_systimer_conf_reg_t systimer_conf; + volatile pcr_systimer_func_clk_conf_reg_t systimer_func_clk_conf; + volatile pcr_twai0_conf_reg_t twai0_conf; + volatile pcr_twai0_func_clk_conf_reg_t twai0_func_clk_conf; + volatile pcr_twai1_conf_reg_t twai1_conf; + volatile pcr_twai1_func_clk_conf_reg_t twai1_func_clk_conf; + volatile pcr_i2s_conf_reg_t i2s_conf; + volatile pcr_i2s_tx_clkm_conf_reg_t i2s_tx_clkm_conf; + volatile pcr_i2s_tx_clkm_div_conf_reg_t i2s_tx_clkm_div_conf; + volatile pcr_i2s_rx_clkm_conf_reg_t i2s_rx_clkm_conf; + volatile pcr_i2s_rx_clkm_div_conf_reg_t i2s_rx_clkm_div_conf; + volatile pcr_saradc_conf_reg_t saradc_conf; + volatile pcr_saradc_clkm_conf_reg_t saradc_clkm_conf; + volatile pcr_tsens_clk_conf_reg_t tsens_clk_conf; + volatile pcr_usb_device_conf_reg_t usb_device_conf; + volatile pcr_intmtx_conf_reg_t intmtx_conf; + volatile pcr_pcnt_conf_reg_t pcnt_conf; + volatile pcr_etm_conf_reg_t etm_conf; + volatile pcr_pwm_conf_reg_t pwm_conf; + volatile pcr_pwm_clk_conf_reg_t pwm_clk_conf; + volatile pcr_parl_io_conf_reg_t parl_io_conf; + volatile pcr_parl_clk_rx_conf_reg_t parl_clk_rx_conf; + volatile pcr_parl_clk_tx_conf_reg_t parl_clk_tx_conf; + volatile pcr_sdio_slave_conf_reg_t sdio_slave_conf; + volatile pcr_pvt_monitor_conf_reg_t pvt_monitor_conf; + volatile pcr_pvt_monitor_func_clk_conf_reg_t pvt_monitor_func_clk_conf; + volatile pcr_gdma_conf_reg_t gdma_conf; + volatile pcr_spi2_conf_reg_t spi2_conf; + volatile pcr_spi2_clkm_conf_reg_t spi2_clkm_conf; + volatile pcr_aes_conf_reg_t aes_conf; + volatile pcr_sha_conf_reg_t sha_conf; + volatile pcr_rsa_conf_reg_t rsa_conf; + volatile pcr_rsa_pd_ctrl_reg_t rsa_pd_ctrl; + volatile pcr_ecc_conf_reg_t ecc_conf; + volatile pcr_ecc_pd_ctrl_reg_t ecc_pd_ctrl; + volatile pcr_ds_conf_reg_t ds_conf; + volatile pcr_hmac_conf_reg_t hmac_conf; + volatile pcr_iomux_conf_reg_t iomux_conf; + volatile pcr_iomux_clk_conf_reg_t iomux_clk_conf; + volatile pcr_mem_monitor_conf_reg_t mem_monitor_conf; + volatile pcr_regdma_conf_reg_t regdma_conf; + volatile pcr_retention_conf_reg_t retention_conf; + volatile pcr_trace_conf_reg_t trace_conf; + volatile pcr_assist_conf_reg_t assist_conf; + volatile pcr_cache_conf_reg_t cache_conf; + volatile pcr_modem_apb_conf_reg_t modem_apb_conf; + volatile pcr_timeout_conf_reg_t timeout_conf; + volatile pcr_sysclk_conf_reg_t sysclk_conf; + volatile pcr_cpu_waiti_conf_reg_t cpu_waiti_conf; + volatile pcr_cpu_freq_conf_reg_t cpu_freq_conf; + volatile pcr_ahb_freq_conf_reg_t ahb_freq_conf; + volatile pcr_apb_freq_conf_reg_t apb_freq_conf; + volatile pcr_sysclk_freq_query_0_reg_t sysclk_freq_query_0; + volatile pcr_pll_div_clk_en_reg_t pll_div_clk_en; + volatile pcr_ctrl_clk_out_en_reg_t ctrl_clk_out_en; + volatile pcr_ctrl_tick_conf_reg_t ctrl_tick_conf; + volatile pcr_ctrl_32k_conf_reg_t ctrl_32k_conf; + volatile pcr_sram_power_conf_reg_t sram_power_conf; + uint32_t reserved_13c[941]; + volatile pcr_reset_event_bypass_reg_t reset_event_bypass; + volatile pcr_fpga_debug_reg_t fpga_debug; + volatile pcr_clock_gate_reg_t clock_gate; + volatile pcr_date_reg_t date; +} pcr_dev_t; + +extern pcr_dev_t PCR; + +#ifndef __cplusplus +_Static_assert(sizeof(pcr_dev_t) == 0x1000, "Invalid size of pcr_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/periph_defs.h b/components/soc/esp32c6/include/soc/periph_defs.h new file mode 100644 index 0000000000..2360268684 --- /dev/null +++ b/components/soc/esp32c6/include/soc/periph_defs.h @@ -0,0 +1,129 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PERIPH_LEDC_MODULE = 0, + PERIPH_UART0_MODULE, + PERIPH_UART1_MODULE, + PERIPH_USB_DEVICE_MODULE, + PERIPH_I2C0_MODULE, + PERIPH_I2S1_MODULE, + PERIPH_TIMG0_MODULE, + PERIPH_TIMG1_MODULE, + PERIPH_UHCI0_MODULE, + PERIPH_RMT_MODULE, + PERIPH_PCNT_MODULE, + PERIPH_SPI_MODULE, //SPI1 + PERIPH_SPI2_MODULE, //SPI2 + PERIPH_TWAI0_MODULE, + PERIPH_TWAI1_MODULE, + PERIPH_RNG_MODULE, + PERIPH_WIFI_MODULE, + PERIPH_BT_MODULE, + PERIPH_WIFI_BT_COMMON_MODULE, + PERIPH_BT_BASEBAND_MODULE, + PERIPH_BT_LC_MODULE, + PERIPH_RSA_MODULE, + PERIPH_AES_MODULE, + PERIPH_SHA_MODULE, + PERIPH_HMAC_MODULE, + PERIPH_DS_MODULE, + PERIPH_GDMA_MODULE, + PERIPH_SYSTIMER_MODULE, + PERIPH_SARADC_MODULE, + PERIPH_MODULE_MAX +} periph_module_t; + +typedef enum { + ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ + ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ + ETS_WIFI_PWR_INTR_SOURCE, /**< */ + ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/ + ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/ + ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/ + ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ + ETS_LP_TIMER_INTR_SOURCE, + ETS_COEX_INTR_SOURCE, + ETS_BLE_TIMER_INTR_SOURCE, + ETS_BLE_SEC_INTR_SOURCE, + ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/ + ETS_ZB_MAC_SOURCE, + ETS_PMU_INTR_SOURCE, + ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ + ETS_LP_RTC_TIMER_INTR_SOURCE, + ETS_LP_UART_INTR_SOURCE, + ETS_LP_I2C_INTR_SOURCE, + ETS_LP_WDT_INTR_SOURCE, + ETS_LP_PERI_TIMEOUT_INTR_SOURCE, + ETS_LP_APM_M0_INTR_SOURCE, + ETS_LP_APM_M1_INTR_SOURCE, + ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ + ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ + ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ + ETS_TRACE_INTR_SOURCE, + ETS_CACHE_INTR_SOURCE, + ETS_CPU_PERI_TIMEOUT_INTR_SOURCE, + ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/ + ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ + ETS_PAU_INTR_SOURCE, + ETS_HP_PERI_TIMEOUT_INTR_SOURCE, + ETS_MODEM_PERI_TIMEOUT_INTR_SOURCE, + ETS_HP_APM_M0_INTR_SOURCE, + ETS_HP_APM_M1_INTR_SOURCE, + ETS_HP_APM_M2_INTR_SOURCE, + ETS_HP_APM_M3_INTR_SOURCE, + ETS_LP_APM0_INTR_SOURCE, + ETS_MSPI_INTR_SOURCE, + ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/ + ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/ + ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/ + ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ + ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/ + ETS_TWAI0_INTR_SOURCE, /**< interrupt of can0, level*/ + ETS_TWAI1_INTR_SOURCE, /**< interrupt of can1, level*/ + ETS_USB_SERIAL_JTAG_INTR_SOURCE, /**< interrupt of USB, level*/ + ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ + ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ + ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/ + ETS_TG0_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, level*/ + ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/ + ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/ + ETS_TG1_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, level*/ + ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ + ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/ + ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/ + ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/ + ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/ + ETS_PWM_INTR_SOURCE, + ETS_PCNT_INTR_SOURCE, + ETS_PARL_IO_INTR_SOURCE, + ETS_SLC0_INTR_SOURCE, + ETS_SLC_INTR_SOURCE, + ETS_DMA_IN_CH0_INTR_SOURCE, /**< interrupt of general DMA IN channel 0, LEVEL*/ + ETS_DMA_IN_CH1_INTR_SOURCE, /**< interrupt of general DMA IN channel 1, LEVEL*/ + ETS_DMA_IN_CH2_INTR_SOURCE, /**< interrupt of general DMA IN channel 2, LEVEL*/ + ETS_DMA_OUT_CH0_INTR_SOURCE, /**< interrupt of general DMA OUT channel 0, LEVEL*/ + ETS_DMA_OUT_CH1_INTR_SOURCE, /**< interrupt of general DMA OUT channel 1, LEVEL*/ + ETS_DMA_OUT_CH2_INTR_SOURCE, /**< interrupt of general DMA OUT channel 2, LEVEL*/ + ETS_GSPI2_INTR_SOURCE, + ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/ + ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ + ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ + ETS_ECC_INTR_SOURCE, /**< interrupt of ECC accelerator, level*/ + ETS_MAX_INTR_SOURCE, +} periph_interrput_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/plic_reg.h b/components/soc/esp32c6/include/soc/plic_reg.h new file mode 100644 index 0000000000..dff45b9605 --- /dev/null +++ b/components/soc/esp32c6/include/soc/plic_reg.h @@ -0,0 +1,631 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +#define PLIC_MXINT_CONF_REG ( 0x200013FC ) +#define PLIC_UXINT_CONF_REG ( 0x200017FC ) + +#define PLIC_MXINT_PRI_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4) +#define PLIC_UXINT_PRI_REG(n) (PLIC_UXINT0_PRI_REG + (n)*4) + +/*PLIC MX*/ +#define PLIC_MXINT_ENABLE_REG (DR_REG_PLIC_MX_BASE + 0x0) +/* PLIC_CPU_MXINT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT_ENABLE 0xFFFFFFFF +#define PLIC_CPU_MXINT_ENABLE_M ((PLIC_CPU_MXINT_ENABLE_V)<<(PLIC_CPU_MXINT_ENABLE_S)) +#define PLIC_CPU_MXINT_ENABLE_V 0xFFFFFFFF +#define PLIC_CPU_MXINT_ENABLE_S 0 + +#define PLIC_MXINT_TYPE_REG (DR_REG_PLIC_MX_BASE + 0x4) +/* PLIC_CPU_MXINT_TYPE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT_TYPE 0xFFFFFFFF +#define PLIC_CPU_MXINT_TYPE_M ((PLIC_CPU_MXINT_TYPE_V)<<(PLIC_CPU_MXINT_TYPE_S)) +#define PLIC_CPU_MXINT_TYPE_V 0xFFFFFFFF +#define PLIC_CPU_MXINT_TYPE_S 0 + +#define PLIC_MXINT_CLEAR_REG (DR_REG_PLIC_MX_BASE + 0x8) +/* PLIC_CPU_MXINT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT_CLEAR 0xFFFFFFFF +#define PLIC_CPU_MXINT_CLEAR_M ((PLIC_CPU_MXINT_CLEAR_V)<<(PLIC_CPU_MXINT_CLEAR_S)) +#define PLIC_CPU_MXINT_CLEAR_V 0xFFFFFFFF +#define PLIC_CPU_MXINT_CLEAR_S 0 + +#define PLIC_EMIP_STATUS_REG (DR_REG_PLIC_MX_BASE + 0xC) +/* PLIC_CPU_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_EIP_STATUS 0xFFFFFFFF +#define PLIC_CPU_EIP_STATUS_M ((PLIC_CPU_EIP_STATUS_V)<<(PLIC_CPU_EIP_STATUS_S)) +#define PLIC_CPU_EIP_STATUS_V 0xFFFFFFFF +#define PLIC_CPU_EIP_STATUS_S 0 + +#define PLIC_MXINT0_PRI_REG (DR_REG_PLIC_MX_BASE + 0x10) +/* PLIC_CPU_MXINT0_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT0_PRI 0x0000000F +#define PLIC_CPU_MXINT0_PRI_M ((PLIC_CPU_MXINT0_PRI_V)<<(PLIC_CPU_MXINT0_PRI_S)) +#define PLIC_CPU_MXINT0_PRI_V 0xF +#define PLIC_CPU_MXINT0_PRI_S 0 + +#define PLIC_MXINT1_PRI_REG (DR_REG_PLIC_MX_BASE + 0x14) +/* PLIC_CPU_MXINT1_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT1_PRI 0x0000000F +#define PLIC_CPU_MXINT1_PRI_M ((PLIC_CPU_MXINT1_PRI_V)<<(PLIC_CPU_MXINT1_PRI_S)) +#define PLIC_CPU_MXINT1_PRI_V 0xF +#define PLIC_CPU_MXINT1_PRI_S 0 + +#define PLIC_MXINT2_PRI_REG (DR_REG_PLIC_MX_BASE + 0x18) +/* PLIC_CPU_MXINT2_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT2_PRI 0x0000000F +#define PLIC_CPU_MXINT2_PRI_M ((PLIC_CPU_MXINT2_PRI_V)<<(PLIC_CPU_MXINT2_PRI_S)) +#define PLIC_CPU_MXINT2_PRI_V 0xF +#define PLIC_CPU_MXINT2_PRI_S 0 + +#define PLIC_MXINT3_PRI_REG (DR_REG_PLIC_MX_BASE + 0x1C) +/* PLIC_CPU_MXINT3_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT3_PRI 0x0000000F +#define PLIC_CPU_MXINT3_PRI_M ((PLIC_CPU_MXINT3_PRI_V)<<(PLIC_CPU_MXINT3_PRI_S)) +#define PLIC_CPU_MXINT3_PRI_V 0xF +#define PLIC_CPU_MXINT3_PRI_S 0 + +#define PLIC_MXINT4_PRI_REG (DR_REG_PLIC_MX_BASE + 0x20) +/* PLIC_CPU_MXINT4_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT4_PRI 0x0000000F +#define PLIC_CPU_MXINT4_PRI_M ((PLIC_CPU_MXINT4_PRI_V)<<(PLIC_CPU_MXINT4_PRI_S)) +#define PLIC_CPU_MXINT4_PRI_V 0xF +#define PLIC_CPU_MXINT4_PRI_S 0 + +#define PLIC_MXINT5_PRI_REG (DR_REG_PLIC_MX_BASE + 0x24) +/* PLIC_CPU_MXINT5_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT5_PRI 0x0000000F +#define PLIC_CPU_MXINT5_PRI_M ((PLIC_CPU_MXINT5_PRI_V)<<(PLIC_CPU_MXINT5_PRI_S)) +#define PLIC_CPU_MXINT5_PRI_V 0xF +#define PLIC_CPU_MXINT5_PRI_S 0 + +#define PLIC_MXINT6_PRI_REG (DR_REG_PLIC_MX_BASE + 0x28) +/* PLIC_CPU_MXINT6_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT6_PRI 0x0000000F +#define PLIC_CPU_MXINT6_PRI_M ((PLIC_CPU_MXINT6_PRI_V)<<(PLIC_CPU_MXINT6_PRI_S)) +#define PLIC_CPU_MXINT6_PRI_V 0xF +#define PLIC_CPU_MXINT6_PRI_S 0 + +#define PLIC_MXINT7_PRI_REG (DR_REG_PLIC_MX_BASE + 0x2C) +/* PLIC_CPU_MXINT7_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT7_PRI 0x0000000F +#define PLIC_CPU_MXINT7_PRI_M ((PLIC_CPU_MXINT7_PRI_V)<<(PLIC_CPU_MXINT7_PRI_S)) +#define PLIC_CPU_MXINT7_PRI_V 0xF +#define PLIC_CPU_MXINT7_PRI_S 0 + +#define PLIC_MXINT8_PRI_REG (DR_REG_PLIC_MX_BASE + 0x30) +/* PLIC_CPU_MXINT8_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT8_PRI 0x0000000F +#define PLIC_CPU_MXINT8_PRI_M ((PLIC_CPU_MXINT8_PRI_V)<<(PLIC_CPU_MXINT8_PRI_S)) +#define PLIC_CPU_MXINT8_PRI_V 0xF +#define PLIC_CPU_MXINT8_PRI_S 0 + +#define PLIC_MXINT9_PRI_REG (DR_REG_PLIC_MX_BASE + 0x34) +/* PLIC_CPU_MXINT9_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT9_PRI 0x0000000F +#define PLIC_CPU_MXINT9_PRI_M ((PLIC_CPU_MXINT9_PRI_V)<<(PLIC_CPU_MXINT9_PRI_S)) +#define PLIC_CPU_MXINT9_PRI_V 0xF +#define PLIC_CPU_MXINT9_PRI_S 0 + +#define PLIC_MXINT10_PRI_REG (DR_REG_PLIC_MX_BASE + 0x38) +/* PLIC_CPU_MXINT10_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT10_PRI 0x0000000F +#define PLIC_CPU_MXINT10_PRI_M ((PLIC_CPU_MXINT10_PRI_V)<<(PLIC_CPU_MXINT10_PRI_S)) +#define PLIC_CPU_MXINT10_PRI_V 0xF +#define PLIC_CPU_MXINT10_PRI_S 0 + +#define PLIC_MXINT11_PRI_REG (DR_REG_PLIC_MX_BASE + 0x3C) +/* PLIC_CPU_MXINT11_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT11_PRI 0x0000000F +#define PLIC_CPU_MXINT11_PRI_M ((PLIC_CPU_MXINT11_PRI_V)<<(PLIC_CPU_MXINT11_PRI_S)) +#define PLIC_CPU_MXINT11_PRI_V 0xF +#define PLIC_CPU_MXINT11_PRI_S 0 + +#define PLIC_MXINT12_PRI_REG (DR_REG_PLIC_MX_BASE + 0x40) +/* PLIC_CPU_MXINT12_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT12_PRI 0x0000000F +#define PLIC_CPU_MXINT12_PRI_M ((PLIC_CPU_MXINT12_PRI_V)<<(PLIC_CPU_MXINT12_PRI_S)) +#define PLIC_CPU_MXINT12_PRI_V 0xF +#define PLIC_CPU_MXINT12_PRI_S 0 + +#define PLIC_MXINT13_PRI_REG (DR_REG_PLIC_MX_BASE + 0x44) +/* PLIC_CPU_MXINT13_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT13_PRI 0x0000000F +#define PLIC_CPU_MXINT13_PRI_M ((PLIC_CPU_MXINT13_PRI_V)<<(PLIC_CPU_MXINT13_PRI_S)) +#define PLIC_CPU_MXINT13_PRI_V 0xF +#define PLIC_CPU_MXINT13_PRI_S 0 + +#define PLIC_MXINT14_PRI_REG (DR_REG_PLIC_MX_BASE + 0x48) +/* PLIC_CPU_MXINT14_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT14_PRI 0x0000000F +#define PLIC_CPU_MXINT14_PRI_M ((PLIC_CPU_MXINT14_PRI_V)<<(PLIC_CPU_MXINT14_PRI_S)) +#define PLIC_CPU_MXINT14_PRI_V 0xF +#define PLIC_CPU_MXINT14_PRI_S 0 + +#define PLIC_MXINT15_PRI_REG (DR_REG_PLIC_MX_BASE + 0x4C) +/* PLIC_CPU_MXINT15_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT15_PRI 0x0000000F +#define PLIC_CPU_MXINT15_PRI_M ((PLIC_CPU_MXINT15_PRI_V)<<(PLIC_CPU_MXINT15_PRI_S)) +#define PLIC_CPU_MXINT15_PRI_V 0xF +#define PLIC_CPU_MXINT15_PRI_S 0 + +#define PLIC_MXINT16_PRI_REG (DR_REG_PLIC_MX_BASE + 0x50) +/* PLIC_CPU_MXINT16_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT16_PRI 0x0000000F +#define PLIC_CPU_MXINT16_PRI_M ((PLIC_CPU_MXINT16_PRI_V)<<(PLIC_CPU_MXINT16_PRI_S)) +#define PLIC_CPU_MXINT16_PRI_V 0xF +#define PLIC_CPU_MXINT16_PRI_S 0 + +#define PLIC_MXINT17_PRI_REG (DR_REG_PLIC_MX_BASE + 0x54) +/* PLIC_CPU_MXINT17_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT17_PRI 0x0000000F +#define PLIC_CPU_MXINT17_PRI_M ((PLIC_CPU_MXINT17_PRI_V)<<(PLIC_CPU_MXINT17_PRI_S)) +#define PLIC_CPU_MXINT17_PRI_V 0xF +#define PLIC_CPU_MXINT17_PRI_S 0 + +#define PLIC_MXINT18_PRI_REG (DR_REG_PLIC_MX_BASE + 0x58) +/* PLIC_CPU_MXINT18_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT18_PRI 0x0000000F +#define PLIC_CPU_MXINT18_PRI_M ((PLIC_CPU_MXINT18_PRI_V)<<(PLIC_CPU_MXINT18_PRI_S)) +#define PLIC_CPU_MXINT18_PRI_V 0xF +#define PLIC_CPU_MXINT18_PRI_S 0 + +#define PLIC_MXINT19_PRI_REG (DR_REG_PLIC_MX_BASE + 0x5C) +/* PLIC_CPU_MXINT19_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT19_PRI 0x0000000F +#define PLIC_CPU_MXINT19_PRI_M ((PLIC_CPU_MXINT19_PRI_V)<<(PLIC_CPU_MXINT19_PRI_S)) +#define PLIC_CPU_MXINT19_PRI_V 0xF +#define PLIC_CPU_MXINT19_PRI_S 0 + +#define PLIC_MXINT20_PRI_REG (DR_REG_PLIC_MX_BASE + 0x60) +/* PLIC_CPU_MXINT20_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT20_PRI 0x0000000F +#define PLIC_CPU_MXINT20_PRI_M ((PLIC_CPU_MXINT20_PRI_V)<<(PLIC_CPU_MXINT20_PRI_S)) +#define PLIC_CPU_MXINT20_PRI_V 0xF +#define PLIC_CPU_MXINT20_PRI_S 0 + +#define PLIC_MXINT21_PRI_REG (DR_REG_PLIC_MX_BASE + 0x64) +/* PLIC_CPU_MXINT21_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT21_PRI 0x0000000F +#define PLIC_CPU_MXINT21_PRI_M ((PLIC_CPU_MXINT21_PRI_V)<<(PLIC_CPU_MXINT21_PRI_S)) +#define PLIC_CPU_MXINT21_PRI_V 0xF +#define PLIC_CPU_MXINT21_PRI_S 0 + +#define PLIC_MXINT22_PRI_REG (DR_REG_PLIC_MX_BASE + 0x68) +/* PLIC_CPU_MXINT22_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT22_PRI 0x0000000F +#define PLIC_CPU_MXINT22_PRI_M ((PLIC_CPU_MXINT22_PRI_V)<<(PLIC_CPU_MXINT22_PRI_S)) +#define PLIC_CPU_MXINT22_PRI_V 0xF +#define PLIC_CPU_MXINT22_PRI_S 0 + +#define PLIC_MXINT23_PRI_REG (DR_REG_PLIC_MX_BASE + 0x6C) +/* PLIC_CPU_MXINT23_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT23_PRI 0x0000000F +#define PLIC_CPU_MXINT23_PRI_M ((PLIC_CPU_MXINT23_PRI_V)<<(PLIC_CPU_MXINT23_PRI_S)) +#define PLIC_CPU_MXINT23_PRI_V 0xF +#define PLIC_CPU_MXINT23_PRI_S 0 + +#define PLIC_MXINT24_PRI_REG (DR_REG_PLIC_MX_BASE + 0x70) +/* PLIC_CPU_MXINT24_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT24_PRI 0x0000000F +#define PLIC_CPU_MXINT24_PRI_M ((PLIC_CPU_MXINT24_PRI_V)<<(PLIC_CPU_MXINT24_PRI_S)) +#define PLIC_CPU_MXINT24_PRI_V 0xF +#define PLIC_CPU_MXINT24_PRI_S 0 + +#define PLIC_MXINT25_PRI_REG (DR_REG_PLIC_MX_BASE + 0x74) +/* PLIC_CPU_MXINT25_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT25_PRI 0x0000000F +#define PLIC_CPU_MXINT25_PRI_M ((PLIC_CPU_MXINT25_PRI_V)<<(PLIC_CPU_MXINT25_PRI_S)) +#define PLIC_CPU_MXINT25_PRI_V 0xF +#define PLIC_CPU_MXINT25_PRI_S 0 + +#define PLIC_MXINT26_PRI_REG (DR_REG_PLIC_MX_BASE + 0x78) +/* PLIC_CPU_MXINT26_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT26_PRI 0x0000000F +#define PLIC_CPU_MXINT26_PRI_M ((PLIC_CPU_MXINT26_PRI_V)<<(PLIC_CPU_MXINT26_PRI_S)) +#define PLIC_CPU_MXINT26_PRI_V 0xF +#define PLIC_CPU_MXINT26_PRI_S 0 + +#define PLIC_MXINT27_PRI_REG (DR_REG_PLIC_MX_BASE + 0x7C) +/* PLIC_CPU_MXINT27_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT27_PRI 0x0000000F +#define PLIC_CPU_MXINT27_PRI_M ((PLIC_CPU_MXINT27_PRI_V)<<(PLIC_CPU_MXINT27_PRI_S)) +#define PLIC_CPU_MXINT27_PRI_V 0xF +#define PLIC_CPU_MXINT27_PRI_S 0 + +#define PLIC_MXINT28_PRI_REG (DR_REG_PLIC_MX_BASE + 0x80) +/* PLIC_CPU_MXINT28_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT28_PRI 0x0000000F +#define PLIC_CPU_MXINT28_PRI_M ((PLIC_CPU_MXINT28_PRI_V)<<(PLIC_CPU_MXINT28_PRI_S)) +#define PLIC_CPU_MXINT28_PRI_V 0xF +#define PLIC_CPU_MXINT28_PRI_S 0 + +#define PLIC_MXINT29_PRI_REG (DR_REG_PLIC_MX_BASE + 0x84) +/* PLIC_CPU_MXINT29_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT29_PRI 0x0000000F +#define PLIC_CPU_MXINT29_PRI_M ((PLIC_CPU_MXINT29_PRI_V)<<(PLIC_CPU_MXINT29_PRI_S)) +#define PLIC_CPU_MXINT29_PRI_V 0xF +#define PLIC_CPU_MXINT29_PRI_S 0 + +#define PLIC_MXINT30_PRI_REG (DR_REG_PLIC_MX_BASE + 0x88) +/* PLIC_CPU_MXINT30_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT30_PRI 0x0000000F +#define PLIC_CPU_MXINT30_PRI_M ((PLIC_CPU_MXINT30_PRI_V)<<(PLIC_CPU_MXINT30_PRI_S)) +#define PLIC_CPU_MXINT30_PRI_V 0xF +#define PLIC_CPU_MXINT30_PRI_S 0 + +#define PLIC_MXINT31_PRI_REG (DR_REG_PLIC_MX_BASE + 0x8C) +/* PLIC_CPU_MXINT31_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT31_PRI 0x0000000F +#define PLIC_CPU_MXINT31_PRI_M ((PLIC_CPU_MXINT31_PRI_V)<<(PLIC_CPU_MXINT31_PRI_S)) +#define PLIC_CPU_MXINT31_PRI_V 0xF +#define PLIC_CPU_MXINT31_PRI_S 0 + +#define PLIC_MXINT_THRESH_REG (DR_REG_PLIC_MX_BASE + 0x90) +/* PLIC_CPU_MXINT_THRESH : R/W ;bitpos:[7:0] ;default: 8'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT_THRESH 0x000000FF +#define PLIC_CPU_MXINT_THRESH_M ((PLIC_CPU_MXINT_THRESH_V)<<(PLIC_CPU_MXINT_THRESH_S)) +#define PLIC_CPU_MXINT_THRESH_V 0xFF +#define PLIC_CPU_MXINT_THRESH_S 0 + +#define PLIC_MXINT_CLAIM_REG (DR_REG_PLIC_MX_BASE + 0x94) +/* PLIC_LP_INTR_FLAG : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag.*/ +#define PLIC_CPU_MXINT_CLAIM 0xFFFFFFFF +#define PLIC_CPU_MXINT_CLAIM_M ((PLIC_CPU_MXINT_CLAIM_V)<<(PLIC_CPU_MXINT_CLAIM_S)) +#define PLIC_CPU_MXINT_CLAIM_V 0xFFFFFFFF +#define PLIC_CPU_MXINT_CLAIM_S 0 + +/*PLIC UX*/ +#define PLIC_UXINT_ENABLE_REG (DR_REG_PLIC_UX_BASE + 0x0) +/* PLIC_CPU_UXINT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT_ENABLE 0xFFFFFFFF +#define PLIC_CPU_UXINT_ENABLE_M ((PLIC_CPU_UXINT_ENABLE_V)<<(PLIC_CPU_UXINT_ENABLE_S)) +#define PLIC_CPU_UXINT_ENABLE_V 0xFFFFFFFF +#define PLIC_CPU_UXINT_ENABLE_S 0 + +#define PLIC_UXINT_TYPE_REG (DR_REG_PLIC_UX_BASE + 0x4) +/* PLIC_CPU_UXINT_TYPE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT_TYPE 0xFFFFFFFF +#define PLIC_CPU_UXINT_TYPE_M ((PLIC_CPU_UXINT_TYPE_V)<<(PLIC_CPU_UXINT_TYPE_S)) +#define PLIC_CPU_UXINT_TYPE_V 0xFFFFFFFF +#define PLIC_CPU_UXINT_TYPE_S 0 + +#define PLIC_UXINT_CLEAR_REG (DR_REG_PLIC_UX_BASE + 0x8) +/* PLIC_CPU_UXINT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT_CLEAR 0xFFFFFFFF +#define PLIC_CPU_UXINT_CLEAR_M ((PLIC_CPU_UXINT_CLEAR_V)<<(PLIC_CPU_UXINT_CLEAR_S)) +#define PLIC_CPU_UXINT_CLEAR_V 0xFFFFFFFF +#define PLIC_CPU_UXINT_CLEAR_S 0 + +#define PLIC_EUIP_STATUS_REG (DR_REG_PLIC_UX_BASE + 0xC) +/* PLIC_CPU_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_EIP_STATUS 0xFFFFFFFF +#define PLIC_CPU_EIP_STATUS_M ((PLIC_CPU_EIP_STATUS_V)<<(PLIC_CPU_EIP_STATUS_S)) +#define PLIC_CPU_EIP_STATUS_V 0xFFFFFFFF +#define PLIC_CPU_EIP_STATUS_S 0 + +#define PLIC_UXINT0_PRI_REG (DR_REG_PLIC_UX_BASE + 0x10) +/* PLIC_CPU_UXINT0_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT0_PRI 0x0000000F +#define PLIC_CPU_UXINT0_PRI_M ((PLIC_CPU_UXINT0_PRI_V)<<(PLIC_CPU_UXINT0_PRI_S)) +#define PLIC_CPU_UXINT0_PRI_V 0xF +#define PLIC_CPU_UXINT0_PRI_S 0 + +#define PLIC_UXINT1_PRI_REG (DR_REG_PLIC_UX_BASE + 0x14) +/* PLIC_CPU_UXINT1_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT1_PRI 0x0000000F +#define PLIC_CPU_UXINT1_PRI_M ((PLIC_CPU_UXINT1_PRI_V)<<(PLIC_CPU_UXINT1_PRI_S)) +#define PLIC_CPU_UXINT1_PRI_V 0xF +#define PLIC_CPU_UXINT1_PRI_S 0 + +#define PLIC_UXINT2_PRI_REG (DR_REG_PLIC_UX_BASE + 0x18) +/* PLIC_CPU_UXINT2_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT2_PRI 0x0000000F +#define PLIC_CPU_UXINT2_PRI_M ((PLIC_CPU_UXINT2_PRI_V)<<(PLIC_CPU_UXINT2_PRI_S)) +#define PLIC_CPU_UXINT2_PRI_V 0xF +#define PLIC_CPU_UXINT2_PRI_S 0 + +#define PLIC_UXINT3_PRI_REG (DR_REG_PLIC_UX_BASE + 0x1C) +/* PLIC_CPU_UXINT3_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT3_PRI 0x0000000F +#define PLIC_CPU_UXINT3_PRI_M ((PLIC_CPU_UXINT3_PRI_V)<<(PLIC_CPU_UXINT3_PRI_S)) +#define PLIC_CPU_UXINT3_PRI_V 0xF +#define PLIC_CPU_UXINT3_PRI_S 0 + +#define PLIC_UXINT4_PRI_REG (DR_REG_PLIC_UX_BASE + 0x20) +/* PLIC_CPU_UXINT4_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT4_PRI 0x0000000F +#define PLIC_CPU_UXINT4_PRI_M ((PLIC_CPU_UXINT4_PRI_V)<<(PLIC_CPU_UXINT4_PRI_S)) +#define PLIC_CPU_UXINT4_PRI_V 0xF +#define PLIC_CPU_UXINT4_PRI_S 0 + +#define PLIC_UXINT5_PRI_REG (DR_REG_PLIC_UX_BASE + 0x24) +/* PLIC_CPU_UXINT5_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT5_PRI 0x0000000F +#define PLIC_CPU_UXINT5_PRI_M ((PLIC_CPU_UXINT5_PRI_V)<<(PLIC_CPU_UXINT5_PRI_S)) +#define PLIC_CPU_UXINT5_PRI_V 0xF +#define PLIC_CPU_UXINT5_PRI_S 0 + +#define PLIC_UXINT6_PRI_REG (DR_REG_PLIC_UX_BASE + 0x28) +/* PLIC_CPU_UXINT6_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT6_PRI 0x0000000F +#define PLIC_CPU_UXINT6_PRI_M ((PLIC_CPU_UXINT6_PRI_V)<<(PLIC_CPU_UXINT6_PRI_S)) +#define PLIC_CPU_UXINT6_PRI_V 0xF +#define PLIC_CPU_UXINT6_PRI_S 0 + +#define PLIC_UXINT7_PRI_REG (DR_REG_PLIC_UX_BASE + 0x2C) +/* PLIC_CPU_UXINT7_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT7_PRI 0x0000000F +#define PLIC_CPU_UXINT7_PRI_M ((PLIC_CPU_UXINT7_PRI_V)<<(PLIC_CPU_UXINT7_PRI_S)) +#define PLIC_CPU_UXINT7_PRI_V 0xF +#define PLIC_CPU_UXINT7_PRI_S 0 + +#define PLIC_UXINT8_PRI_REG (DR_REG_PLIC_UX_BASE + 0x30) +/* PLIC_CPU_UXINT8_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT8_PRI 0x0000000F +#define PLIC_CPU_UXINT8_PRI_M ((PLIC_CPU_UXINT8_PRI_V)<<(PLIC_CPU_UXINT8_PRI_S)) +#define PLIC_CPU_UXINT8_PRI_V 0xF +#define PLIC_CPU_UXINT8_PRI_S 0 + +#define PLIC_UXINT9_PRI_REG (DR_REG_PLIC_UX_BASE + 0x34) +/* PLIC_CPU_UXINT9_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT9_PRI 0x0000000F +#define PLIC_CPU_UXINT9_PRI_M ((PLIC_CPU_UXINT9_PRI_V)<<(PLIC_CPU_UXINT9_PRI_S)) +#define PLIC_CPU_UXINT9_PRI_V 0xF +#define PLIC_CPU_UXINT9_PRI_S 0 + +#define PLIC_UXINT10_PRI_REG (DR_REG_PLIC_UX_BASE + 0x38) +/* PLIC_CPU_UXINT10_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT10_PRI 0x0000000F +#define PLIC_CPU_UXINT10_PRI_M ((PLIC_CPU_UXINT10_PRI_V)<<(PLIC_CPU_UXINT10_PRI_S)) +#define PLIC_CPU_UXINT10_PRI_V 0xF +#define PLIC_CPU_UXINT10_PRI_S 0 + +#define PLIC_UXINT11_PRI_REG (DR_REG_PLIC_UX_BASE + 0x3C) +/* PLIC_CPU_UXINT11_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT11_PRI 0x0000000F +#define PLIC_CPU_UXINT11_PRI_M ((PLIC_CPU_UXINT11_PRI_V)<<(PLIC_CPU_UXINT11_PRI_S)) +#define PLIC_CPU_UXINT11_PRI_V 0xF +#define PLIC_CPU_UXINT11_PRI_S 0 + +#define PLIC_UXINT12_PRI_REG (DR_REG_PLIC_UX_BASE + 0x40) +/* PLIC_CPU_UXINT12_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT12_PRI 0x0000000F +#define PLIC_CPU_UXINT12_PRI_M ((PLIC_CPU_UXINT12_PRI_V)<<(PLIC_CPU_UXINT12_PRI_S)) +#define PLIC_CPU_UXINT12_PRI_V 0xF +#define PLIC_CPU_UXINT12_PRI_S 0 + +#define PLIC_UXINT13_PRI_REG (DR_REG_PLIC_UX_BASE + 0x44) +/* PLIC_CPU_UXINT13_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT13_PRI 0x0000000F +#define PLIC_CPU_UXINT13_PRI_M ((PLIC_CPU_UXINT13_PRI_V)<<(PLIC_CPU_UXINT13_PRI_S)) +#define PLIC_CPU_UXINT13_PRI_V 0xF +#define PLIC_CPU_UXINT13_PRI_S 0 + +#define PLIC_UXINT14_PRI_REG (DR_REG_PLIC_UX_BASE + 0x48) +/* PLIC_CPU_UXINT14_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT14_PRI 0x0000000F +#define PLIC_CPU_UXINT14_PRI_M ((PLIC_CPU_UXINT14_PRI_V)<<(PLIC_CPU_UXINT14_PRI_S)) +#define PLIC_CPU_UXINT14_PRI_V 0xF +#define PLIC_CPU_UXINT14_PRI_S 0 + +#define PLIC_UXINT15_PRI_REG (DR_REG_PLIC_UX_BASE + 0x4C) +/* PLIC_CPU_UXINT15_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT15_PRI 0x0000000F +#define PLIC_CPU_UXINT15_PRI_M ((PLIC_CPU_UXINT15_PRI_V)<<(PLIC_CPU_UXINT15_PRI_S)) +#define PLIC_CPU_UXINT15_PRI_V 0xF +#define PLIC_CPU_UXINT15_PRI_S 0 + +#define PLIC_UXINT16_PRI_REG (DR_REG_PLIC_UX_BASE + 0x50) +/* PLIC_CPU_UXINT16_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT16_PRI 0x0000000F +#define PLIC_CPU_UXINT16_PRI_M ((PLIC_CPU_UXINT16_PRI_V)<<(PLIC_CPU_UXINT16_PRI_S)) +#define PLIC_CPU_UXINT16_PRI_V 0xF +#define PLIC_CPU_UXINT16_PRI_S 0 + +#define PLIC_UXINT17_PRI_REG (DR_REG_PLIC_UX_BASE + 0x54) +/* PLIC_CPU_UXINT17_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT17_PRI 0x0000000F +#define PLIC_CPU_UXINT17_PRI_M ((PLIC_CPU_UXINT17_PRI_V)<<(PLIC_CPU_UXINT17_PRI_S)) +#define PLIC_CPU_UXINT17_PRI_V 0xF +#define PLIC_CPU_UXINT17_PRI_S 0 + +#define PLIC_UXINT18_PRI_REG (DR_REG_PLIC_UX_BASE + 0x58) +/* PLIC_CPU_UXINT18_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT18_PRI 0x0000000F +#define PLIC_CPU_UXINT18_PRI_M ((PLIC_CPU_UXINT18_PRI_V)<<(PLIC_CPU_UXINT18_PRI_S)) +#define PLIC_CPU_UXINT18_PRI_V 0xF +#define PLIC_CPU_UXINT18_PRI_S 0 + +#define PLIC_UXINT19_PRI_REG (DR_REG_PLIC_UX_BASE + 0x5C) +/* PLIC_CPU_UXINT19_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT19_PRI 0x0000000F +#define PLIC_CPU_UXINT19_PRI_M ((PLIC_CPU_UXINT19_PRI_V)<<(PLIC_CPU_UXINT19_PRI_S)) +#define PLIC_CPU_UXINT19_PRI_V 0xF +#define PLIC_CPU_UXINT19_PRI_S 0 + +#define PLIC_UXINT20_PRI_REG (DR_REG_PLIC_UX_BASE + 0x60) +/* PLIC_CPU_UXINT20_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT20_PRI 0x0000000F +#define PLIC_CPU_UXINT20_PRI_M ((PLIC_CPU_UXINT20_PRI_V)<<(PLIC_CPU_UXINT20_PRI_S)) +#define PLIC_CPU_UXINT20_PRI_V 0xF +#define PLIC_CPU_UXINT20_PRI_S 0 + +#define PLIC_UXINT21_PRI_REG (DR_REG_PLIC_UX_BASE + 0x64) +/* PLIC_CPU_UXINT21_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT21_PRI 0x0000000F +#define PLIC_CPU_UXINT21_PRI_M ((PLIC_CPU_UXINT21_PRI_V)<<(PLIC_CPU_UXINT21_PRI_S)) +#define PLIC_CPU_UXINT21_PRI_V 0xF +#define PLIC_CPU_UXINT21_PRI_S 0 + +#define PLIC_UXINT22_PRI_REG (DR_REG_PLIC_UX_BASE + 0x68) +/* PLIC_CPU_UXINT22_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT22_PRI 0x0000000F +#define PLIC_CPU_UXINT22_PRI_M ((PLIC_CPU_UXINT22_PRI_V)<<(PLIC_CPU_UXINT22_PRI_S)) +#define PLIC_CPU_UXINT22_PRI_V 0xF +#define PLIC_CPU_UXINT22_PRI_S 0 + +#define PLIC_UXINT23_PRI_REG (DR_REG_PLIC_UX_BASE + 0x6C) +/* PLIC_CPU_UXINT23_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT23_PRI 0x0000000F +#define PLIC_CPU_UXINT23_PRI_M ((PLIC_CPU_UXINT23_PRI_V)<<(PLIC_CPU_UXINT23_PRI_S)) +#define PLIC_CPU_UXINT23_PRI_V 0xF +#define PLIC_CPU_UXINT23_PRI_S 0 + +#define PLIC_UXINT24_PRI_REG (DR_REG_PLIC_UX_BASE + 0x70) +/* PLIC_CPU_UXINT24_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT24_PRI 0x0000000F +#define PLIC_CPU_UXINT24_PRI_M ((PLIC_CPU_UXINT24_PRI_V)<<(PLIC_CPU_UXINT24_PRI_S)) +#define PLIC_CPU_UXINT24_PRI_V 0xF +#define PLIC_CPU_UXINT24_PRI_S 0 + +#define PLIC_UXINT25_PRI_REG (DR_REG_PLIC_UX_BASE + 0x74) +/* PLIC_CPU_UXINT25_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT25_PRI 0x0000000F +#define PLIC_CPU_UXINT25_PRI_M ((PLIC_CPU_UXINT25_PRI_V)<<(PLIC_CPU_UXINT25_PRI_S)) +#define PLIC_CPU_UXINT25_PRI_V 0xF +#define PLIC_CPU_UXINT25_PRI_S 0 + +#define PLIC_UXINT26_PRI_REG (DR_REG_PLIC_UX_BASE + 0x78) +/* PLIC_CPU_UXINT26_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT26_PRI 0x0000000F +#define PLIC_CPU_UXINT26_PRI_M ((PLIC_CPU_UXINT26_PRI_V)<<(PLIC_CPU_UXINT26_PRI_S)) +#define PLIC_CPU_UXINT26_PRI_V 0xF +#define PLIC_CPU_UXINT26_PRI_S 0 + +#define PLIC_UXINT27_PRI_REG (DR_REG_PLIC_UX_BASE + 0x7C) +/* PLIC_CPU_UXINT27_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT27_PRI 0x0000000F +#define PLIC_CPU_UXINT27_PRI_M ((PLIC_CPU_UXINT27_PRI_V)<<(PLIC_CPU_UXINT27_PRI_S)) +#define PLIC_CPU_UXINT27_PRI_V 0xF +#define PLIC_CPU_UXINT27_PRI_S 0 + +#define PLIC_UXINT28_PRI_REG (DR_REG_PLIC_UX_BASE + 0x80) +/* PLIC_CPU_UXINT28_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT28_PRI 0x0000000F +#define PLIC_CPU_UXINT28_PRI_M ((PLIC_CPU_UXINT28_PRI_V)<<(PLIC_CPU_UXINT28_PRI_S)) +#define PLIC_CPU_UXINT28_PRI_V 0xF +#define PLIC_CPU_UXINT28_PRI_S 0 + +#define PLIC_UXINT29_PRI_REG (DR_REG_PLIC_UX_BASE + 0x84) +/* PLIC_CPU_UXINT29_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT29_PRI 0x0000000F +#define PLIC_CPU_UXINT29_PRI_M ((PLIC_CPU_UXINT29_PRI_V)<<(PLIC_CPU_UXINT29_PRI_S)) +#define PLIC_CPU_UXINT29_PRI_V 0xF +#define PLIC_CPU_UXINT29_PRI_S 0 + +#define PLIC_UXINT30_PRI_REG (DR_REG_PLIC_UX_BASE + 0x88) +/* PLIC_CPU_UXINT30_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT30_PRI 0x0000000F +#define PLIC_CPU_UXINT30_PRI_M ((PLIC_CPU_UXINT30_PRI_V)<<(PLIC_CPU_UXINT30_PRI_S)) +#define PLIC_CPU_UXINT30_PRI_V 0xF +#define PLIC_CPU_UXINT30_PRI_S 0 + +#define PLIC_UXINT31_PRI_REG (DR_REG_PLIC_UX_BASE + 0x8C) +/* PLIC_CPU_UXINT31_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT31_PRI 0x0000000F +#define PLIC_CPU_UXINT31_PRI_M ((PLIC_CPU_UXINT31_PRI_V)<<(PLIC_CPU_UXINT31_PRI_S)) +#define PLIC_CPU_UXINT31_PRI_V 0xF +#define PLIC_CPU_UXINT31_PRI_S 0 + +#define PLIC_UXINT_THRESH_REG (DR_REG_PLIC_UX_BASE + 0x90) +/* PLIC_CPU_UXINT_THRESH : R/W ;bitpos:[7:0] ;default: 8'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT_THRESH 0x000000FF +#define PLIC_CPU_UXINT_THRESH_M ((PLIC_CPU_UXINT_THRESH_V)<<(PLIC_CPU_UXINT_THRESH_S)) +#define PLIC_CPU_UXINT_THRESH_V 0xFF +#define PLIC_CPU_UXINT_THRESH_S 0 + +#define PLIC_UXINT_CLAIM_REG (DR_REG_PLIC_UX_BASE + 0x94) +/* PLIC_CPU_UXINT_CLAIM : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT_CLAIM 0xFFFFFFFF +#define PLIC_CPU_UXINT_CLAIM_M ((PLIC_CPU_UXINT_CLAIM_V)<<(PLIC_CPU_UXINT_CLAIM_S)) +#define PLIC_CPU_UXINT_CLAIM_V 0xFFFFFFFF +#define PLIC_CPU_UXINT_CLAIM_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/pmu_icg_mapping.h b/components/soc/esp32c6/include/soc/pmu_icg_mapping.h new file mode 100644 index 0000000000..edced509c4 --- /dev/null +++ b/components/soc/esp32c6/include/soc/pmu_icg_mapping.h @@ -0,0 +1,68 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _SOC_ICG_MAP_H_ +#define _SOC_ICG_MAP_H_ + +#define PMU_ICG_APB_ENA_CAN0 18 +#define PMU_ICG_APB_ENA_CAN1 19 +#define PMU_ICG_APB_ENA_GDMA 1 +#define PMU_ICG_APB_ENA_I2C 13 +#define PMU_ICG_APB_ENA_I2S 4 +#define PMU_ICG_APB_ENA_INTMTX 3 +#define PMU_ICG_APB_ENA_IOMUX 26 +#define PMU_ICG_APB_ENA_LEDC 14 +#define PMU_ICG_APB_ENA_MEM_MONITOR 25 +#define PMU_ICG_APB_ENA_MSPI 5 +#define PMU_ICG_APB_ENA_PARL 23 +#define PMU_ICG_APB_ENA_PCNT 20 +#define PMU_ICG_APB_ENA_PVT_MONITOR 27 +#define PMU_ICG_APB_ENA_PWM 21 +#define PMU_ICG_APB_ENA_REGDMA 24 +#define PMU_ICG_APB_ENA_RMT 15 +#define PMU_ICG_APB_ENA_SARADC 9 +#define PMU_ICG_APB_ENA_SEC 0 +#define PMU_ICG_APB_ENA_SOC_ETM 22 +#define PMU_ICG_APB_ENA_SPI2 2 +#define PMU_ICG_APB_ENA_SYSTIMER 16 +#define PMU_ICG_APB_ENA_TG0 11 +#define PMU_ICG_APB_ENA_TG1 12 +#define PMU_ICG_APB_ENA_UART0 6 +#define PMU_ICG_APB_ENA_UART1 7 +#define PMU_ICG_APB_ENA_UHCI 8 +#define PMU_ICG_APB_ENA_USB_DEVICE 17 +#define PMU_ICG_FUNC_ENA_CAN0 31 +#define PMU_ICG_FUNC_ENA_CAN1 30 +#define PMU_ICG_FUNC_ENA_I2C 29 +#define PMU_ICG_FUNC_ENA_I2S_RX 2 +#define PMU_ICG_FUNC_ENA_I2S_TX 7 +#define PMU_ICG_FUNC_ENA_IOMUX 28 +#define PMU_ICG_FUNC_ENA_LEDC 27 +#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10 +#define PMU_ICG_FUNC_ENA_MSPI 26 +#define PMU_ICG_FUNC_ENA_PARL_RX 25 +#define PMU_ICG_FUNC_ENA_PARL_TX 24 +#define PMU_ICG_FUNC_ENA_PVT_MONITOR 23 +#define PMU_ICG_FUNC_ENA_PWM 22 +#define PMU_ICG_FUNC_ENA_RMT 21 +#define PMU_ICG_FUNC_ENA_SARADC 20 +#define PMU_ICG_FUNC_ENA_SEC 19 +#define PMU_ICG_FUNC_ENA_SPI2 1 +#define PMU_ICG_FUNC_ENA_SYSTIMER 18 +#define PMU_ICG_FUNC_ENA_TG0 14 +#define PMU_ICG_FUNC_ENA_TG1 13 +#define PMU_ICG_FUNC_ENA_TSENS 12 +#define PMU_ICG_FUNC_ENA_UART0 3 +#define PMU_ICG_FUNC_ENA_UART1 4 +#define PMU_ICG_FUNC_ENA_USB_DEVICE 6 +#define PMU_ICG_FUNC_ENA_GDMA 0 +#define PMU_ICG_FUNC_ENA_SOC_ETM 16 +#define PMU_ICG_FUNC_ENA_REGDMA 8 +#define PMU_ICG_FUNC_ENA_RETENTION 9 +#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11 +#define PMU_ICG_FUNC_ENA_UHCI 5 +#define PMU_ICG_FUNC_ENA_HPCORE 17 +#define PMU_ICG_FUNC_ENA_HPBUS 15 +#endif /* _SOC_ICG_MAP_H_ */ diff --git a/components/soc/esp32c6/include/soc/pmu_reg.h b/components/soc/esp32c6/include/soc/pmu_reg.h new file mode 100644 index 0000000000..fb444e1e3d --- /dev/null +++ b/components/soc/esp32c6/include/soc/pmu_reg.h @@ -0,0 +1,3381 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PMU_HP_ACTIVE_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_ACTIVE_DIG_POWER_REG (DR_REG_PMU_BASE + 0x0) +/** PMU_HP_ACTIVE_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN (BIT(21)) +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_M (PMU_HP_ACTIVE_VDD_SPI_PD_EN_V << PMU_HP_ACTIVE_VDD_SPI_PD_EN_S) +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_S 21 +/** PMU_HP_ACTIVE_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_ACTIVE_HP_MEM_DSLP_M (PMU_HP_ACTIVE_HP_MEM_DSLP_V << PMU_HP_ACTIVE_HP_MEM_DSLP_S) +#define PMU_HP_ACTIVE_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_ACTIVE_HP_MEM_DSLP_S 22 +/** PMU_HP_ACTIVE_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN 0x0000000FU +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_M (PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V << PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V 0x0000000FU +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN (BIT(27)) +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_M (PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V << PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_ACTIVE_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_M (PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V << PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_ACTIVE_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN (BIT(30)) +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_M (PMU_HP_ACTIVE_PD_HP_AON_PD_EN_V << PMU_HP_ACTIVE_PD_HP_AON_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_S 30 +/** PMU_HP_ACTIVE_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_M (PMU_HP_ACTIVE_PD_TOP_PD_EN_V << PMU_HP_ACTIVE_PD_TOP_PD_EN_S) +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_S 31 + +/** PMU_HP_ACTIVE_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x4) +/** PMU_HP_ACTIVE_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_M (PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V << PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S) +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_ACTIVE_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x8) +/** PMU_HP_ACTIVE_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_M (PMU_HP_ACTIVE_DIG_ICG_APB_EN_V << PMU_HP_ACTIVE_DIG_ICG_APB_EN_S) +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_ACTIVE_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_MODEM_REG (DR_REG_PMU_BASE + 0xc) +/** PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_M (PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V << PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_ACTIVE_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x10) +/** PMU_HP_ACTIVE_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_M (PMU_HP_ACTIVE_UART_WAKEUP_EN_V << PMU_HP_ACTIVE_UART_WAKEUP_EN_S) +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_S 24 +/** PMU_HP_ACTIVE_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_M (PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S) +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_ACTIVE_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_M (PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S) +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_ACTIVE_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_M (PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V << PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S) +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_ACTIVE_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_M (PMU_HP_ACTIVE_DIG_PAUSE_WDT_V << PMU_HP_ACTIVE_DIG_PAUSE_WDT_S) +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_S 28 +/** PMU_HP_ACTIVE_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_ACTIVE_DIG_CPU_STALL_M (PMU_HP_ACTIVE_DIG_CPU_STALL_V << PMU_HP_ACTIVE_DIG_CPU_STALL_S) +#define PMU_HP_ACTIVE_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_CPU_STALL_S 29 + +/** PMU_HP_ACTIVE_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x14) +/** PMU_HP_ACTIVE_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_I2C_ISO_EN (BIT(26)) +#define PMU_HP_ACTIVE_I2C_ISO_EN_M (PMU_HP_ACTIVE_I2C_ISO_EN_V << PMU_HP_ACTIVE_I2C_ISO_EN_S) +#define PMU_HP_ACTIVE_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_ACTIVE_I2C_ISO_EN_S 26 +/** PMU_HP_ACTIVE_I2C_RETENTION : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_I2C_RETENTION (BIT(27)) +#define PMU_HP_ACTIVE_I2C_RETENTION_M (PMU_HP_ACTIVE_I2C_RETENTION_V << PMU_HP_ACTIVE_I2C_RETENTION_S) +#define PMU_HP_ACTIVE_I2C_RETENTION_V 0x00000001U +#define PMU_HP_ACTIVE_I2C_RETENTION_S 27 +/** PMU_HP_ACTIVE_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BB_I2C (BIT(28)) +#define PMU_HP_ACTIVE_XPD_BB_I2C_M (PMU_HP_ACTIVE_XPD_BB_I2C_V << PMU_HP_ACTIVE_XPD_BB_I2C_S) +#define PMU_HP_ACTIVE_XPD_BB_I2C_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BB_I2C_S 28 +/** PMU_HP_ACTIVE_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C (BIT(29)) +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_M (PMU_HP_ACTIVE_XPD_BBPLL_I2C_V << PMU_HP_ACTIVE_XPD_BBPLL_I2C_S) +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_S 29 +/** PMU_HP_ACTIVE_XPD_BBPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BBPLL (BIT(30)) +#define PMU_HP_ACTIVE_XPD_BBPLL_M (PMU_HP_ACTIVE_XPD_BBPLL_V << PMU_HP_ACTIVE_XPD_BBPLL_S) +#define PMU_HP_ACTIVE_XPD_BBPLL_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BBPLL_S 30 + +/** PMU_HP_ACTIVE_BIAS_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BIAS_REG (DR_REG_PMU_BASE + 0x18) +/** PMU_HP_ACTIVE_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BIAS (BIT(25)) +#define PMU_HP_ACTIVE_XPD_BIAS_M (PMU_HP_ACTIVE_XPD_BIAS_V << PMU_HP_ACTIVE_XPD_BIAS_S) +#define PMU_HP_ACTIVE_XPD_BIAS_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BIAS_S 25 +/** PMU_HP_ACTIVE_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DBG_ATTEN 0x0000000FU +#define PMU_HP_ACTIVE_DBG_ATTEN_M (PMU_HP_ACTIVE_DBG_ATTEN_V << PMU_HP_ACTIVE_DBG_ATTEN_S) +#define PMU_HP_ACTIVE_DBG_ATTEN_V 0x0000000FU +#define PMU_HP_ACTIVE_DBG_ATTEN_S 26 +/** PMU_HP_ACTIVE_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_CUR (BIT(30)) +#define PMU_HP_ACTIVE_PD_CUR_M (PMU_HP_ACTIVE_PD_CUR_V << PMU_HP_ACTIVE_PD_CUR_S) +#define PMU_HP_ACTIVE_PD_CUR_V 0x00000001U +#define PMU_HP_ACTIVE_PD_CUR_S 30 +/** PMU_HP_ACTIVE_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_BIAS_SLEEP (BIT(31)) +#define PMU_HP_ACTIVE_BIAS_SLEEP_M (PMU_HP_ACTIVE_BIAS_SLEEP_V << PMU_HP_ACTIVE_BIAS_SLEEP_S) +#define PMU_HP_ACTIVE_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_ACTIVE_BIAS_SLEEP_S 31 + +/** PMU_HP_ACTIVE_BACKUP_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_REG (DR_REG_PMU_BASE + 0x1c) +/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S 4 +/** PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S 6 +/** PMU_HP_ACTIVE_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_RETENTION_MODE (BIT(10)) +#define PMU_HP_ACTIVE_RETENTION_MODE_M (PMU_HP_ACTIVE_RETENTION_MODE_V << PMU_HP_ACTIVE_RETENTION_MODE_S) +#define PMU_HP_ACTIVE_RETENTION_MODE_V 0x00000001U +#define PMU_HP_ACTIVE_RETENTION_MODE_S 10 +/** PMU_HP_SLEEP2ACTIVE_RETENTION_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN (BIT(11)) +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_M (PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V << PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S) +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V 0x00000001U +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S 11 +/** PMU_HP_MODEM2ACTIVE_RETENTION_EN : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN (BIT(12)) +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_M (PMU_HP_MODEM2ACTIVE_RETENTION_EN_V << PMU_HP_MODEM2ACTIVE_RETENTION_EN_S) +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_V 0x00000001U +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_S 12 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S 14 +/** PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S 16 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE 0x00000007U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V 0x00000007U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S 20 +/** PMU_HP_MODEM2ACTIVE_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE 0x00000007U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V 0x00000007U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S 23 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN (BIT(29)) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_M (PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V << PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V 0x00000001U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S 29 +/** PMU_HP_MODEM2ACTIVE_BACKUP_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN (BIT(30)) +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_M (PMU_HP_MODEM2ACTIVE_BACKUP_EN_V << PMU_HP_MODEM2ACTIVE_BACKUP_EN_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_V 0x00000001U +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_S 30 + +/** PMU_HP_ACTIVE_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x20) +/** PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_M (PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V << PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_ACTIVE_SYSCLK_REG register + * need_des + */ +#define PMU_HP_ACTIVE_SYSCLK_REG (DR_REG_PMU_BASE + 0x24) +/** PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_M (PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V << PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_M (PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V << PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_ACTIVE_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_M (PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V << PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S) +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_ACTIVE_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_ACTIVE_ICG_SLP_SEL_M (PMU_HP_ACTIVE_ICG_SLP_SEL_V << PMU_HP_ACTIVE_ICG_SLP_SEL_S) +#define PMU_HP_ACTIVE_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_ICG_SLP_SEL_S 29 +/** PMU_HP_ACTIVE_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_M (PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V << PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_ACTIVE_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x28) +/** PMU_LP_DBIAS_VOL : RO; bitpos: [8:4]; default: 24; + * need_des + */ +#define PMU_LP_DBIAS_VOL 0x0000001FU +#define PMU_LP_DBIAS_VOL_M (PMU_LP_DBIAS_VOL_V << PMU_LP_DBIAS_VOL_S) +#define PMU_LP_DBIAS_VOL_V 0x0000001FU +#define PMU_LP_DBIAS_VOL_S 4 +/** PMU_HP_DBIAS_VOL : RO; bitpos: [13:9]; default: 24; + * need_des + */ +#define PMU_HP_DBIAS_VOL 0x0000001FU +#define PMU_HP_DBIAS_VOL_M (PMU_HP_DBIAS_VOL_V << PMU_HP_DBIAS_VOL_S) +#define PMU_HP_DBIAS_VOL_V 0x0000001FU +#define PMU_HP_DBIAS_VOL_S 9 +/** PMU_DIG_REGULATOR0_DBIAS_SEL : R/W; bitpos: [14]; default: 1; + * need_des + */ +#define PMU_DIG_REGULATOR0_DBIAS_SEL (BIT(14)) +#define PMU_DIG_REGULATOR0_DBIAS_SEL_M (PMU_DIG_REGULATOR0_DBIAS_SEL_V << PMU_DIG_REGULATOR0_DBIAS_SEL_S) +#define PMU_DIG_REGULATOR0_DBIAS_SEL_V 0x00000001U +#define PMU_DIG_REGULATOR0_DBIAS_SEL_S 14 +/** PMU_DIG_DBIAS_INIT : WT; bitpos: [15]; default: 0; + * need_des + */ +#define PMU_DIG_DBIAS_INIT (BIT(15)) +#define PMU_DIG_DBIAS_INIT_M (PMU_DIG_DBIAS_INIT_V << PMU_DIG_DBIAS_INIT_S) +#define PMU_DIG_DBIAS_INIT_V 0x00000001U +#define PMU_DIG_DBIAS_INIT_S 15 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_ACTIVE_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_S 18 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_ACTIVE_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_ACTIVE_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x2c) +/** PMU_HP_ACTIVE_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B 0x00FFFFFFU +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_M (PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V << PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V 0x00FFFFFFU +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S 8 + +/** PMU_HP_ACTIVE_XTAL_REG register + * need_des + */ +#define PMU_HP_ACTIVE_XTAL_REG (DR_REG_PMU_BASE + 0x30) +/** PMU_HP_ACTIVE_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_XTAL (BIT(31)) +#define PMU_HP_ACTIVE_XPD_XTAL_M (PMU_HP_ACTIVE_XPD_XTAL_V << PMU_HP_ACTIVE_XPD_XTAL_S) +#define PMU_HP_ACTIVE_XPD_XTAL_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_XTAL_S 31 + +/** PMU_HP_MODEM_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_MODEM_DIG_POWER_REG (DR_REG_PMU_BASE + 0x34) +/** PMU_HP_MODEM_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_VDD_SPI_PD_EN (BIT(21)) +#define PMU_HP_MODEM_VDD_SPI_PD_EN_M (PMU_HP_MODEM_VDD_SPI_PD_EN_V << PMU_HP_MODEM_VDD_SPI_PD_EN_S) +#define PMU_HP_MODEM_VDD_SPI_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_VDD_SPI_PD_EN_S 21 +/** PMU_HP_MODEM_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_MODEM_HP_MEM_DSLP_M (PMU_HP_MODEM_HP_MEM_DSLP_V << PMU_HP_MODEM_HP_MEM_DSLP_S) +#define PMU_HP_MODEM_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_MODEM_HP_MEM_DSLP_S 22 +/** PMU_HP_MODEM_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN 0x0000000FU +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_M (PMU_HP_MODEM_PD_HP_MEM_PD_EN_V << PMU_HP_MODEM_PD_HP_MEM_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_V 0x0000000FU +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_MODEM_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN (BIT(27)) +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_M (PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V << PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_MODEM_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_M (PMU_HP_MODEM_PD_HP_CPU_PD_EN_V << PMU_HP_MODEM_PD_HP_CPU_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_MODEM_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_AON_PD_EN (BIT(30)) +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_M (PMU_HP_MODEM_PD_HP_AON_PD_EN_V << PMU_HP_MODEM_PD_HP_AON_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_S 30 +/** PMU_HP_MODEM_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_MODEM_PD_TOP_PD_EN_M (PMU_HP_MODEM_PD_TOP_PD_EN_V << PMU_HP_MODEM_PD_TOP_PD_EN_S) +#define PMU_HP_MODEM_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_TOP_PD_EN_S 31 + +/** PMU_HP_MODEM_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x38) +/** PMU_HP_MODEM_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_M (PMU_HP_MODEM_DIG_ICG_FUNC_EN_V << PMU_HP_MODEM_DIG_ICG_FUNC_EN_S) +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_MODEM_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x3c) +/** PMU_HP_MODEM_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_APB_EN_M (PMU_HP_MODEM_DIG_ICG_APB_EN_V << PMU_HP_MODEM_DIG_ICG_APB_EN_S) +#define PMU_HP_MODEM_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_MODEM_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x40) +/** PMU_HP_MODEM_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_M (PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V << PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_MODEM_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x44) +/** PMU_HP_MODEM_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_MODEM_UART_WAKEUP_EN_M (PMU_HP_MODEM_UART_WAKEUP_EN_V << PMU_HP_MODEM_UART_WAKEUP_EN_S) +#define PMU_HP_MODEM_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_MODEM_UART_WAKEUP_EN_S 24 +/** PMU_HP_MODEM_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_M (PMU_HP_MODEM_LP_PAD_HOLD_ALL_V << PMU_HP_MODEM_LP_PAD_HOLD_ALL_S) +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_MODEM_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_M (PMU_HP_MODEM_HP_PAD_HOLD_ALL_V << PMU_HP_MODEM_HP_PAD_HOLD_ALL_S) +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_MODEM_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_M (PMU_HP_MODEM_DIG_PAD_SLP_SEL_V << PMU_HP_MODEM_DIG_PAD_SLP_SEL_S) +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_MODEM_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_MODEM_DIG_PAUSE_WDT_M (PMU_HP_MODEM_DIG_PAUSE_WDT_V << PMU_HP_MODEM_DIG_PAUSE_WDT_S) +#define PMU_HP_MODEM_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_MODEM_DIG_PAUSE_WDT_S 28 +/** PMU_HP_MODEM_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_MODEM_DIG_CPU_STALL_M (PMU_HP_MODEM_DIG_CPU_STALL_V << PMU_HP_MODEM_DIG_CPU_STALL_S) +#define PMU_HP_MODEM_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_MODEM_DIG_CPU_STALL_S 29 + +/** PMU_HP_MODEM_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x48) +/** PMU_HP_MODEM_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_I2C_ISO_EN (BIT(26)) +#define PMU_HP_MODEM_I2C_ISO_EN_M (PMU_HP_MODEM_I2C_ISO_EN_V << PMU_HP_MODEM_I2C_ISO_EN_S) +#define PMU_HP_MODEM_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_MODEM_I2C_ISO_EN_S 26 +/** PMU_HP_MODEM_I2C_RETENTION : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_I2C_RETENTION (BIT(27)) +#define PMU_HP_MODEM_I2C_RETENTION_M (PMU_HP_MODEM_I2C_RETENTION_V << PMU_HP_MODEM_I2C_RETENTION_S) +#define PMU_HP_MODEM_I2C_RETENTION_V 0x00000001U +#define PMU_HP_MODEM_I2C_RETENTION_S 27 +/** PMU_HP_MODEM_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BB_I2C (BIT(28)) +#define PMU_HP_MODEM_XPD_BB_I2C_M (PMU_HP_MODEM_XPD_BB_I2C_V << PMU_HP_MODEM_XPD_BB_I2C_S) +#define PMU_HP_MODEM_XPD_BB_I2C_V 0x00000001U +#define PMU_HP_MODEM_XPD_BB_I2C_S 28 +/** PMU_HP_MODEM_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BBPLL_I2C (BIT(29)) +#define PMU_HP_MODEM_XPD_BBPLL_I2C_M (PMU_HP_MODEM_XPD_BBPLL_I2C_V << PMU_HP_MODEM_XPD_BBPLL_I2C_S) +#define PMU_HP_MODEM_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_HP_MODEM_XPD_BBPLL_I2C_S 29 +/** PMU_HP_MODEM_XPD_BBPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BBPLL (BIT(30)) +#define PMU_HP_MODEM_XPD_BBPLL_M (PMU_HP_MODEM_XPD_BBPLL_V << PMU_HP_MODEM_XPD_BBPLL_S) +#define PMU_HP_MODEM_XPD_BBPLL_V 0x00000001U +#define PMU_HP_MODEM_XPD_BBPLL_S 30 + +/** PMU_HP_MODEM_BIAS_REG register + * need_des + */ +#define PMU_HP_MODEM_BIAS_REG (DR_REG_PMU_BASE + 0x4c) +/** PMU_HP_MODEM_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BIAS (BIT(25)) +#define PMU_HP_MODEM_XPD_BIAS_M (PMU_HP_MODEM_XPD_BIAS_V << PMU_HP_MODEM_XPD_BIAS_S) +#define PMU_HP_MODEM_XPD_BIAS_V 0x00000001U +#define PMU_HP_MODEM_XPD_BIAS_S 25 +/** PMU_HP_MODEM_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DBG_ATTEN 0x0000000FU +#define PMU_HP_MODEM_DBG_ATTEN_M (PMU_HP_MODEM_DBG_ATTEN_V << PMU_HP_MODEM_DBG_ATTEN_S) +#define PMU_HP_MODEM_DBG_ATTEN_V 0x0000000FU +#define PMU_HP_MODEM_DBG_ATTEN_S 26 +/** PMU_HP_MODEM_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_CUR (BIT(30)) +#define PMU_HP_MODEM_PD_CUR_M (PMU_HP_MODEM_PD_CUR_V << PMU_HP_MODEM_PD_CUR_S) +#define PMU_HP_MODEM_PD_CUR_V 0x00000001U +#define PMU_HP_MODEM_PD_CUR_S 30 +/** PMU_HP_MODEM_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_BIAS_SLEEP (BIT(31)) +#define PMU_HP_MODEM_BIAS_SLEEP_M (PMU_HP_MODEM_BIAS_SLEEP_V << PMU_HP_MODEM_BIAS_SLEEP_S) +#define PMU_HP_MODEM_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_MODEM_BIAS_SLEEP_S 31 + +/** PMU_HP_MODEM_BACKUP_REG register + * need_des + */ +#define PMU_HP_MODEM_BACKUP_REG (DR_REG_PMU_BASE + 0x50) +/** PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S 4 +/** PMU_HP_MODEM_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_RETENTION_MODE (BIT(10)) +#define PMU_HP_MODEM_RETENTION_MODE_M (PMU_HP_MODEM_RETENTION_MODE_V << PMU_HP_MODEM_RETENTION_MODE_S) +#define PMU_HP_MODEM_RETENTION_MODE_V 0x00000001U +#define PMU_HP_MODEM_RETENTION_MODE_S 10 +/** PMU_HP_SLEEP2MODEM_RETENTION_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_RETENTION_EN (BIT(11)) +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_M (PMU_HP_SLEEP2MODEM_RETENTION_EN_V << PMU_HP_SLEEP2MODEM_RETENTION_EN_S) +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_V 0x00000001U +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_S 11 +/** PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S 14 +/** PMU_HP_SLEEP2MODEM_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE 0x00000007U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODE_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_V 0x00000007U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_S 20 +/** PMU_HP_SLEEP2MODEM_BACKUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_EN (BIT(29)) +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_M (PMU_HP_SLEEP2MODEM_BACKUP_EN_V << PMU_HP_SLEEP2MODEM_BACKUP_EN_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_V 0x00000001U +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_S 29 + +/** PMU_HP_MODEM_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_MODEM_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x54) +/** PMU_HP_MODEM_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_M (PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V << PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_MODEM_SYSCLK_REG register + * need_des + */ +#define PMU_HP_MODEM_SYSCLK_REG (DR_REG_PMU_BASE + 0x58) +/** PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_M (PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V << PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_MODEM_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_M (PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V << PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_MODEM_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_M (PMU_HP_MODEM_SYS_CLK_SLP_SEL_V << PMU_HP_MODEM_SYS_CLK_SLP_SEL_S) +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_MODEM_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_MODEM_ICG_SLP_SEL_M (PMU_HP_MODEM_ICG_SLP_SEL_V << PMU_HP_MODEM_ICG_SLP_SEL_S) +#define PMU_HP_MODEM_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_ICG_SLP_SEL_S 29 +/** PMU_HP_MODEM_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_M (PMU_HP_MODEM_DIG_SYS_CLK_SEL_V << PMU_HP_MODEM_DIG_SYS_CLK_SEL_S) +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_MODEM_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x5c) +/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_MODEM_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_MODEM_HP_REGULATOR_XPD_M (PMU_HP_MODEM_HP_REGULATOR_XPD_V << PMU_HP_MODEM_HP_REGULATOR_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_XPD_S 18 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_MODEM_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_MODEM_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x60) +/** PMU_HP_MODEM_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B 0x00FFFFFFU +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_M (PMU_HP_MODEM_HP_REGULATOR_DRV_B_V << PMU_HP_MODEM_HP_REGULATOR_DRV_B_S) +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_V 0x00FFFFFFU +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_S 8 + +/** PMU_HP_MODEM_XTAL_REG register + * need_des + */ +#define PMU_HP_MODEM_XTAL_REG (DR_REG_PMU_BASE + 0x64) +/** PMU_HP_MODEM_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_XPD_XTAL (BIT(31)) +#define PMU_HP_MODEM_XPD_XTAL_M (PMU_HP_MODEM_XPD_XTAL_V << PMU_HP_MODEM_XPD_XTAL_S) +#define PMU_HP_MODEM_XPD_XTAL_V 0x00000001U +#define PMU_HP_MODEM_XPD_XTAL_S 31 + +/** PMU_HP_SLEEP_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_DIG_POWER_REG (DR_REG_PMU_BASE + 0x68) +/** PMU_HP_SLEEP_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_VDD_SPI_PD_EN (BIT(21)) +#define PMU_HP_SLEEP_VDD_SPI_PD_EN_M (PMU_HP_SLEEP_VDD_SPI_PD_EN_V << PMU_HP_SLEEP_VDD_SPI_PD_EN_S) +#define PMU_HP_SLEEP_VDD_SPI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_VDD_SPI_PD_EN_S 21 +/** PMU_HP_SLEEP_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_SLEEP_HP_MEM_DSLP_M (PMU_HP_SLEEP_HP_MEM_DSLP_V << PMU_HP_SLEEP_HP_MEM_DSLP_S) +#define PMU_HP_SLEEP_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_SLEEP_HP_MEM_DSLP_S 22 +/** PMU_HP_SLEEP_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN 0x0000000FU +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_M (PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V << PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V 0x0000000FU +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_SLEEP_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN (BIT(27)) +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_M (PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V << PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_SLEEP_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_M (PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V << PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_SLEEP_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN (BIT(30)) +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_M (PMU_HP_SLEEP_PD_HP_AON_PD_EN_V << PMU_HP_SLEEP_PD_HP_AON_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_S 30 +/** PMU_HP_SLEEP_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_SLEEP_PD_TOP_PD_EN_M (PMU_HP_SLEEP_PD_TOP_PD_EN_V << PMU_HP_SLEEP_PD_TOP_PD_EN_S) +#define PMU_HP_SLEEP_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_TOP_PD_EN_S 31 + +/** PMU_HP_SLEEP_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x6c) +/** PMU_HP_SLEEP_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_M (PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V << PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S) +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_SLEEP_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x70) +/** PMU_HP_SLEEP_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_M (PMU_HP_SLEEP_DIG_ICG_APB_EN_V << PMU_HP_SLEEP_DIG_ICG_APB_EN_S) +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_SLEEP_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x74) +/** PMU_HP_SLEEP_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_M (PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V << PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_SLEEP_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x78) +/** PMU_HP_SLEEP_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_SLEEP_UART_WAKEUP_EN_M (PMU_HP_SLEEP_UART_WAKEUP_EN_V << PMU_HP_SLEEP_UART_WAKEUP_EN_S) +#define PMU_HP_SLEEP_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_SLEEP_UART_WAKEUP_EN_S 24 +/** PMU_HP_SLEEP_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_M (PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S) +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_SLEEP_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_M (PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S) +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_SLEEP_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_M (PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V << PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S) +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_SLEEP_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_M (PMU_HP_SLEEP_DIG_PAUSE_WDT_V << PMU_HP_SLEEP_DIG_PAUSE_WDT_S) +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_S 28 +/** PMU_HP_SLEEP_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_SLEEP_DIG_CPU_STALL_M (PMU_HP_SLEEP_DIG_CPU_STALL_V << PMU_HP_SLEEP_DIG_CPU_STALL_S) +#define PMU_HP_SLEEP_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_SLEEP_DIG_CPU_STALL_S 29 + +/** PMU_HP_SLEEP_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x7c) +/** PMU_HP_SLEEP_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_I2C_ISO_EN (BIT(26)) +#define PMU_HP_SLEEP_I2C_ISO_EN_M (PMU_HP_SLEEP_I2C_ISO_EN_V << PMU_HP_SLEEP_I2C_ISO_EN_S) +#define PMU_HP_SLEEP_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_SLEEP_I2C_ISO_EN_S 26 +/** PMU_HP_SLEEP_I2C_RETENTION : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_I2C_RETENTION (BIT(27)) +#define PMU_HP_SLEEP_I2C_RETENTION_M (PMU_HP_SLEEP_I2C_RETENTION_V << PMU_HP_SLEEP_I2C_RETENTION_S) +#define PMU_HP_SLEEP_I2C_RETENTION_V 0x00000001U +#define PMU_HP_SLEEP_I2C_RETENTION_S 27 +/** PMU_HP_SLEEP_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BB_I2C (BIT(28)) +#define PMU_HP_SLEEP_XPD_BB_I2C_M (PMU_HP_SLEEP_XPD_BB_I2C_V << PMU_HP_SLEEP_XPD_BB_I2C_S) +#define PMU_HP_SLEEP_XPD_BB_I2C_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BB_I2C_S 28 +/** PMU_HP_SLEEP_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BBPLL_I2C (BIT(29)) +#define PMU_HP_SLEEP_XPD_BBPLL_I2C_M (PMU_HP_SLEEP_XPD_BBPLL_I2C_V << PMU_HP_SLEEP_XPD_BBPLL_I2C_S) +#define PMU_HP_SLEEP_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BBPLL_I2C_S 29 +/** PMU_HP_SLEEP_XPD_BBPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BBPLL (BIT(30)) +#define PMU_HP_SLEEP_XPD_BBPLL_M (PMU_HP_SLEEP_XPD_BBPLL_V << PMU_HP_SLEEP_XPD_BBPLL_S) +#define PMU_HP_SLEEP_XPD_BBPLL_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BBPLL_S 30 + +/** PMU_HP_SLEEP_BIAS_REG register + * need_des + */ +#define PMU_HP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0x80) +/** PMU_HP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BIAS (BIT(25)) +#define PMU_HP_SLEEP_XPD_BIAS_M (PMU_HP_SLEEP_XPD_BIAS_V << PMU_HP_SLEEP_XPD_BIAS_S) +#define PMU_HP_SLEEP_XPD_BIAS_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BIAS_S 25 +/** PMU_HP_SLEEP_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DBG_ATTEN 0x0000000FU +#define PMU_HP_SLEEP_DBG_ATTEN_M (PMU_HP_SLEEP_DBG_ATTEN_V << PMU_HP_SLEEP_DBG_ATTEN_S) +#define PMU_HP_SLEEP_DBG_ATTEN_V 0x0000000FU +#define PMU_HP_SLEEP_DBG_ATTEN_S 26 +/** PMU_HP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_CUR (BIT(30)) +#define PMU_HP_SLEEP_PD_CUR_M (PMU_HP_SLEEP_PD_CUR_V << PMU_HP_SLEEP_PD_CUR_S) +#define PMU_HP_SLEEP_PD_CUR_V 0x00000001U +#define PMU_HP_SLEEP_PD_CUR_S 30 +/** PMU_HP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_BIAS_SLEEP (BIT(31)) +#define PMU_HP_SLEEP_BIAS_SLEEP_M (PMU_HP_SLEEP_BIAS_SLEEP_V << PMU_HP_SLEEP_BIAS_SLEEP_S) +#define PMU_HP_SLEEP_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_SLEEP_BIAS_SLEEP_S 31 + +/** PMU_HP_SLEEP_BACKUP_REG register + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_REG (DR_REG_PMU_BASE + 0x84) +/** PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S 6 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [9:8]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S 8 +/** PMU_HP_SLEEP_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_RETENTION_MODE (BIT(10)) +#define PMU_HP_SLEEP_RETENTION_MODE_M (PMU_HP_SLEEP_RETENTION_MODE_V << PMU_HP_SLEEP_RETENTION_MODE_S) +#define PMU_HP_SLEEP_RETENTION_MODE_V 0x00000001U +#define PMU_HP_SLEEP_RETENTION_MODE_S 10 +/** PMU_HP_MODEM2SLEEP_RETENTION_EN : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_RETENTION_EN (BIT(12)) +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_M (PMU_HP_MODEM2SLEEP_RETENTION_EN_V << PMU_HP_MODEM2SLEEP_RETENTION_EN_S) +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_V 0x00000001U +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_S 12 +/** PMU_HP_ACTIVE2SLEEP_RETENTION_EN : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN (BIT(13)) +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_M (PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V << PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S) +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V 0x00000001U +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S 13 +/** PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S 16 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [19:18]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S 18 +/** PMU_HP_MODEM2SLEEP_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE 0x00000007U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODE_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_V 0x00000007U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_S 23 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODE : R/W; bitpos: [28:26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE 0x00000007U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V 0x00000007U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S 26 +/** PMU_HP_MODEM2SLEEP_BACKUP_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_EN (BIT(30)) +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_M (PMU_HP_MODEM2SLEEP_BACKUP_EN_V << PMU_HP_MODEM2SLEEP_BACKUP_EN_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_V 0x00000001U +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_S 30 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN (BIT(31)) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_M (PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V << PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V 0x00000001U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S 31 + +/** PMU_HP_SLEEP_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x88) +/** PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_M (PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V << PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_SLEEP_SYSCLK_REG register + * need_des + */ +#define PMU_HP_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0x8c) +/** PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_M (PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V << PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_SLEEP_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_M (PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V << PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_SLEEP_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_M (PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V << PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S) +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_SLEEP_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_SLEEP_ICG_SLP_SEL_M (PMU_HP_SLEEP_ICG_SLP_SEL_V << PMU_HP_SLEEP_ICG_SLP_SEL_S) +#define PMU_HP_SLEEP_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_ICG_SLP_SEL_S 29 +/** PMU_HP_SLEEP_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_M (PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V << PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S) +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_SLEEP_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x90) +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_SLEEP_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_S 18 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_SLEEP_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_SLEEP_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x94) +/** PMU_HP_SLEEP_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B 0x00FFFFFFU +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_M (PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S) +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V 0x00FFFFFFU +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S 8 + +/** PMU_HP_SLEEP_XTAL_REG register + * need_des + */ +#define PMU_HP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0x98) +/** PMU_HP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_XPD_XTAL (BIT(31)) +#define PMU_HP_SLEEP_XPD_XTAL_M (PMU_HP_SLEEP_XPD_XTAL_V << PMU_HP_SLEEP_XPD_XTAL_S) +#define PMU_HP_SLEEP_XPD_XTAL_V 0x00000001U +#define PMU_HP_SLEEP_XPD_XTAL_S 31 + +/** PMU_HP_SLEEP_LP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x9c) +/** PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD (BIT(21)) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V 0x00000001U +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S 21 +/** PMU_HP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_XPD (BIT(22)) +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_M (PMU_HP_SLEEP_LP_REGULATOR_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_XPD_S) +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_S 22 +/** PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 +/** PMU_HP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S) +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_SLEEP_LP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xa0) +/** PMU_HP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_M (PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S) +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S 28 + +/** PMU_HP_SLEEP_LP_DCDC_RESERVE_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_DCDC_RESERVE_REG (DR_REG_PMU_BASE + 0xa4) +/** PMU_HP_SLEEP_LP_DCDC_RESERVE : WT; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_DCDC_RESERVE 0xFFFFFFFFU +#define PMU_HP_SLEEP_LP_DCDC_RESERVE_M (PMU_HP_SLEEP_LP_DCDC_RESERVE_V << PMU_HP_SLEEP_LP_DCDC_RESERVE_S) +#define PMU_HP_SLEEP_LP_DCDC_RESERVE_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_LP_DCDC_RESERVE_S 0 + +/** PMU_HP_SLEEP_LP_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xa8) +/** PMU_HP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_MEM_DSLP (BIT(30)) +#define PMU_HP_SLEEP_LP_MEM_DSLP_M (PMU_HP_SLEEP_LP_MEM_DSLP_V << PMU_HP_SLEEP_LP_MEM_DSLP_S) +#define PMU_HP_SLEEP_LP_MEM_DSLP_V 0x00000001U +#define PMU_HP_SLEEP_LP_MEM_DSLP_S 30 +/** PMU_HP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN (BIT(31)) +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_M (PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S) +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S 31 + +/** PMU_HP_SLEEP_LP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xac) +/** PMU_HP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_XTAL32K (BIT(28)) +#define PMU_HP_SLEEP_XPD_XTAL32K_M (PMU_HP_SLEEP_XPD_XTAL32K_V << PMU_HP_SLEEP_XPD_XTAL32K_S) +#define PMU_HP_SLEEP_XPD_XTAL32K_V 0x00000001U +#define PMU_HP_SLEEP_XPD_XTAL32K_S 28 +/** PMU_HP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_RC32K (BIT(29)) +#define PMU_HP_SLEEP_XPD_RC32K_M (PMU_HP_SLEEP_XPD_RC32K_V << PMU_HP_SLEEP_XPD_RC32K_S) +#define PMU_HP_SLEEP_XPD_RC32K_V 0x00000001U +#define PMU_HP_SLEEP_XPD_RC32K_S 29 +/** PMU_HP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_XPD_FOSC_CLK (BIT(30)) +#define PMU_HP_SLEEP_XPD_FOSC_CLK_M (PMU_HP_SLEEP_XPD_FOSC_CLK_V << PMU_HP_SLEEP_XPD_FOSC_CLK_S) +#define PMU_HP_SLEEP_XPD_FOSC_CLK_V 0x00000001U +#define PMU_HP_SLEEP_XPD_FOSC_CLK_S 30 +/** PMU_HP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_OSC_CLK (BIT(31)) +#define PMU_HP_SLEEP_PD_OSC_CLK_M (PMU_HP_SLEEP_PD_OSC_CLK_V << PMU_HP_SLEEP_PD_OSC_CLK_S) +#define PMU_HP_SLEEP_PD_OSC_CLK_V 0x00000001U +#define PMU_HP_SLEEP_PD_OSC_CLK_S 31 + +/** PMU_LP_SLEEP_LP_BIAS_RESERVE_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_BIAS_RESERVE_REG (DR_REG_PMU_BASE + 0xb0) +/** PMU_LP_SLEEP_LP_BIAS_RESERVE : WT; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_BIAS_RESERVE 0xFFFFFFFFU +#define PMU_LP_SLEEP_LP_BIAS_RESERVE_M (PMU_LP_SLEEP_LP_BIAS_RESERVE_V << PMU_LP_SLEEP_LP_BIAS_RESERVE_S) +#define PMU_LP_SLEEP_LP_BIAS_RESERVE_V 0xFFFFFFFFU +#define PMU_LP_SLEEP_LP_BIAS_RESERVE_S 0 + +/** PMU_LP_SLEEP_LP_REGULATOR0_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0xb4) +/** PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD (BIT(21)) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V 0x00000001U +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S 21 +/** PMU_LP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_XPD (BIT(22)) +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_M (PMU_LP_SLEEP_LP_REGULATOR_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_XPD_S) +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_V 0x00000001U +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_S 22 +/** PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 +/** PMU_LP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S) +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S 27 + +/** PMU_LP_SLEEP_LP_REGULATOR1_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xb8) +/** PMU_LP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:28]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_M (PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S) +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S 28 + +/** PMU_LP_SLEEP_XTAL_REG register + * need_des + */ +#define PMU_LP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0xbc) +/** PMU_LP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_XPD_XTAL (BIT(31)) +#define PMU_LP_SLEEP_XPD_XTAL_M (PMU_LP_SLEEP_XPD_XTAL_V << PMU_LP_SLEEP_XPD_XTAL_S) +#define PMU_LP_SLEEP_XPD_XTAL_V 0x00000001U +#define PMU_LP_SLEEP_XPD_XTAL_S 31 + +/** PMU_LP_SLEEP_LP_DIG_POWER_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xc0) +/** PMU_LP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_MEM_DSLP (BIT(30)) +#define PMU_LP_SLEEP_LP_MEM_DSLP_M (PMU_LP_SLEEP_LP_MEM_DSLP_V << PMU_LP_SLEEP_LP_MEM_DSLP_S) +#define PMU_LP_SLEEP_LP_MEM_DSLP_V 0x00000001U +#define PMU_LP_SLEEP_LP_MEM_DSLP_S 30 +/** PMU_LP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN (BIT(31)) +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_M (PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S) +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V 0x00000001U +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S 31 + +/** PMU_LP_SLEEP_LP_CK_POWER_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xc4) +/** PMU_LP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_XTAL32K (BIT(28)) +#define PMU_LP_SLEEP_XPD_XTAL32K_M (PMU_LP_SLEEP_XPD_XTAL32K_V << PMU_LP_SLEEP_XPD_XTAL32K_S) +#define PMU_LP_SLEEP_XPD_XTAL32K_V 0x00000001U +#define PMU_LP_SLEEP_XPD_XTAL32K_S 28 +/** PMU_LP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_RC32K (BIT(29)) +#define PMU_LP_SLEEP_XPD_RC32K_M (PMU_LP_SLEEP_XPD_RC32K_V << PMU_LP_SLEEP_XPD_RC32K_S) +#define PMU_LP_SLEEP_XPD_RC32K_V 0x00000001U +#define PMU_LP_SLEEP_XPD_RC32K_S 29 +/** PMU_LP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_XPD_FOSC_CLK (BIT(30)) +#define PMU_LP_SLEEP_XPD_FOSC_CLK_M (PMU_LP_SLEEP_XPD_FOSC_CLK_V << PMU_LP_SLEEP_XPD_FOSC_CLK_S) +#define PMU_LP_SLEEP_XPD_FOSC_CLK_V 0x00000001U +#define PMU_LP_SLEEP_XPD_FOSC_CLK_S 30 +/** PMU_LP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_OSC_CLK (BIT(31)) +#define PMU_LP_SLEEP_PD_OSC_CLK_M (PMU_LP_SLEEP_PD_OSC_CLK_V << PMU_LP_SLEEP_PD_OSC_CLK_S) +#define PMU_LP_SLEEP_PD_OSC_CLK_V 0x00000001U +#define PMU_LP_SLEEP_PD_OSC_CLK_S 31 + +/** PMU_LP_SLEEP_BIAS_REG register + * need_des + */ +#define PMU_LP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0xc8) +/** PMU_LP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_BIAS (BIT(25)) +#define PMU_LP_SLEEP_XPD_BIAS_M (PMU_LP_SLEEP_XPD_BIAS_V << PMU_LP_SLEEP_XPD_BIAS_S) +#define PMU_LP_SLEEP_XPD_BIAS_V 0x00000001U +#define PMU_LP_SLEEP_XPD_BIAS_S 25 +/** PMU_LP_SLEEP_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_DBG_ATTEN 0x0000000FU +#define PMU_LP_SLEEP_DBG_ATTEN_M (PMU_LP_SLEEP_DBG_ATTEN_V << PMU_LP_SLEEP_DBG_ATTEN_S) +#define PMU_LP_SLEEP_DBG_ATTEN_V 0x0000000FU +#define PMU_LP_SLEEP_DBG_ATTEN_S 26 +/** PMU_LP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_CUR (BIT(30)) +#define PMU_LP_SLEEP_PD_CUR_M (PMU_LP_SLEEP_PD_CUR_V << PMU_LP_SLEEP_PD_CUR_S) +#define PMU_LP_SLEEP_PD_CUR_V 0x00000001U +#define PMU_LP_SLEEP_PD_CUR_S 30 +/** PMU_LP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_BIAS_SLEEP (BIT(31)) +#define PMU_LP_SLEEP_BIAS_SLEEP_M (PMU_LP_SLEEP_BIAS_SLEEP_V << PMU_LP_SLEEP_BIAS_SLEEP_S) +#define PMU_LP_SLEEP_BIAS_SLEEP_V 0x00000001U +#define PMU_LP_SLEEP_BIAS_SLEEP_S 31 + +/** PMU_IMM_HP_CK_POWER_REG register + * need_des + */ +#define PMU_IMM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0xcc) +/** PMU_TIE_LOW_GLOBAL_BBPLL_ICG : WT; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG (BIT(0)) +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_M (PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V << PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S) +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V 0x00000001U +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S 0 +/** PMU_TIE_LOW_GLOBAL_XTAL_ICG : WT; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG (BIT(1)) +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_M (PMU_TIE_LOW_GLOBAL_XTAL_ICG_V << PMU_TIE_LOW_GLOBAL_XTAL_ICG_S) +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_V 0x00000001U +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_S 1 +/** PMU_TIE_LOW_I2C_RETENTION : WT; bitpos: [2]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_I2C_RETENTION (BIT(2)) +#define PMU_TIE_LOW_I2C_RETENTION_M (PMU_TIE_LOW_I2C_RETENTION_V << PMU_TIE_LOW_I2C_RETENTION_S) +#define PMU_TIE_LOW_I2C_RETENTION_V 0x00000001U +#define PMU_TIE_LOW_I2C_RETENTION_S 2 +/** PMU_TIE_LOW_XPD_BB_I2C : WT; bitpos: [3]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_BB_I2C (BIT(3)) +#define PMU_TIE_LOW_XPD_BB_I2C_M (PMU_TIE_LOW_XPD_BB_I2C_V << PMU_TIE_LOW_XPD_BB_I2C_S) +#define PMU_TIE_LOW_XPD_BB_I2C_V 0x00000001U +#define PMU_TIE_LOW_XPD_BB_I2C_S 3 +/** PMU_TIE_LOW_XPD_BBPLL_I2C : WT; bitpos: [4]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_BBPLL_I2C (BIT(4)) +#define PMU_TIE_LOW_XPD_BBPLL_I2C_M (PMU_TIE_LOW_XPD_BBPLL_I2C_V << PMU_TIE_LOW_XPD_BBPLL_I2C_S) +#define PMU_TIE_LOW_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_TIE_LOW_XPD_BBPLL_I2C_S 4 +/** PMU_TIE_LOW_XPD_BBPLL : WT; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_BBPLL (BIT(5)) +#define PMU_TIE_LOW_XPD_BBPLL_M (PMU_TIE_LOW_XPD_BBPLL_V << PMU_TIE_LOW_XPD_BBPLL_S) +#define PMU_TIE_LOW_XPD_BBPLL_V 0x00000001U +#define PMU_TIE_LOW_XPD_BBPLL_S 5 +/** PMU_TIE_LOW_XPD_XTAL : WT; bitpos: [6]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_XTAL (BIT(6)) +#define PMU_TIE_LOW_XPD_XTAL_M (PMU_TIE_LOW_XPD_XTAL_V << PMU_TIE_LOW_XPD_XTAL_S) +#define PMU_TIE_LOW_XPD_XTAL_V 0x00000001U +#define PMU_TIE_LOW_XPD_XTAL_S 6 +/** PMU_TIE_HIGH_GLOBAL_BBPLL_ICG : WT; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG (BIT(25)) +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_M (PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V << PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S) +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V 0x00000001U +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S 25 +/** PMU_TIE_HIGH_GLOBAL_XTAL_ICG : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG (BIT(26)) +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_M (PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V << PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S) +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V 0x00000001U +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S 26 +/** PMU_TIE_HIGH_I2C_RETENTION : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_I2C_RETENTION (BIT(27)) +#define PMU_TIE_HIGH_I2C_RETENTION_M (PMU_TIE_HIGH_I2C_RETENTION_V << PMU_TIE_HIGH_I2C_RETENTION_S) +#define PMU_TIE_HIGH_I2C_RETENTION_V 0x00000001U +#define PMU_TIE_HIGH_I2C_RETENTION_S 27 +/** PMU_TIE_HIGH_XPD_BB_I2C : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_BB_I2C (BIT(28)) +#define PMU_TIE_HIGH_XPD_BB_I2C_M (PMU_TIE_HIGH_XPD_BB_I2C_V << PMU_TIE_HIGH_XPD_BB_I2C_S) +#define PMU_TIE_HIGH_XPD_BB_I2C_V 0x00000001U +#define PMU_TIE_HIGH_XPD_BB_I2C_S 28 +/** PMU_TIE_HIGH_XPD_BBPLL_I2C : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_BBPLL_I2C (BIT(29)) +#define PMU_TIE_HIGH_XPD_BBPLL_I2C_M (PMU_TIE_HIGH_XPD_BBPLL_I2C_V << PMU_TIE_HIGH_XPD_BBPLL_I2C_S) +#define PMU_TIE_HIGH_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_TIE_HIGH_XPD_BBPLL_I2C_S 29 +/** PMU_TIE_HIGH_XPD_BBPLL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_BBPLL (BIT(30)) +#define PMU_TIE_HIGH_XPD_BBPLL_M (PMU_TIE_HIGH_XPD_BBPLL_V << PMU_TIE_HIGH_XPD_BBPLL_S) +#define PMU_TIE_HIGH_XPD_BBPLL_V 0x00000001U +#define PMU_TIE_HIGH_XPD_BBPLL_S 30 +/** PMU_TIE_HIGH_XPD_XTAL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_XTAL (BIT(31)) +#define PMU_TIE_HIGH_XPD_XTAL_M (PMU_TIE_HIGH_XPD_XTAL_V << PMU_TIE_HIGH_XPD_XTAL_S) +#define PMU_TIE_HIGH_XPD_XTAL_V 0x00000001U +#define PMU_TIE_HIGH_XPD_XTAL_S 31 + +/** PMU_IMM_SLEEP_SYSCLK_REG register + * need_des + */ +#define PMU_IMM_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0xd0) +/** PMU_UPDATE_DIG_ICG_SWITCH : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_SWITCH (BIT(28)) +#define PMU_UPDATE_DIG_ICG_SWITCH_M (PMU_UPDATE_DIG_ICG_SWITCH_V << PMU_UPDATE_DIG_ICG_SWITCH_S) +#define PMU_UPDATE_DIG_ICG_SWITCH_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_SWITCH_S 28 +/** PMU_TIE_LOW_ICG_SLP_SEL : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_ICG_SLP_SEL (BIT(29)) +#define PMU_TIE_LOW_ICG_SLP_SEL_M (PMU_TIE_LOW_ICG_SLP_SEL_V << PMU_TIE_LOW_ICG_SLP_SEL_S) +#define PMU_TIE_LOW_ICG_SLP_SEL_V 0x00000001U +#define PMU_TIE_LOW_ICG_SLP_SEL_S 29 +/** PMU_TIE_HIGH_ICG_SLP_SEL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_ICG_SLP_SEL (BIT(30)) +#define PMU_TIE_HIGH_ICG_SLP_SEL_M (PMU_TIE_HIGH_ICG_SLP_SEL_V << PMU_TIE_HIGH_ICG_SLP_SEL_S) +#define PMU_TIE_HIGH_ICG_SLP_SEL_V 0x00000001U +#define PMU_TIE_HIGH_ICG_SLP_SEL_S 30 +/** PMU_UPDATE_DIG_SYS_CLK_SEL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_SYS_CLK_SEL (BIT(31)) +#define PMU_UPDATE_DIG_SYS_CLK_SEL_M (PMU_UPDATE_DIG_SYS_CLK_SEL_V << PMU_UPDATE_DIG_SYS_CLK_SEL_S) +#define PMU_UPDATE_DIG_SYS_CLK_SEL_V 0x00000001U +#define PMU_UPDATE_DIG_SYS_CLK_SEL_S 31 + +/** PMU_IMM_HP_FUNC_ICG_REG register + * need_des + */ +#define PMU_IMM_HP_FUNC_ICG_REG (DR_REG_PMU_BASE + 0xd4) +/** PMU_UPDATE_DIG_ICG_FUNC_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_FUNC_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_FUNC_EN_M (PMU_UPDATE_DIG_ICG_FUNC_EN_V << PMU_UPDATE_DIG_ICG_FUNC_EN_S) +#define PMU_UPDATE_DIG_ICG_FUNC_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_FUNC_EN_S 31 + +/** PMU_IMM_HP_APB_ICG_REG register + * need_des + */ +#define PMU_IMM_HP_APB_ICG_REG (DR_REG_PMU_BASE + 0xd8) +/** PMU_UPDATE_DIG_ICG_APB_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_APB_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_APB_EN_M (PMU_UPDATE_DIG_ICG_APB_EN_V << PMU_UPDATE_DIG_ICG_APB_EN_S) +#define PMU_UPDATE_DIG_ICG_APB_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_APB_EN_S 31 + +/** PMU_IMM_MODEM_ICG_REG register + * need_des + */ +#define PMU_IMM_MODEM_ICG_REG (DR_REG_PMU_BASE + 0xdc) +/** PMU_UPDATE_DIG_ICG_MODEM_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_MODEM_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_MODEM_EN_M (PMU_UPDATE_DIG_ICG_MODEM_EN_V << PMU_UPDATE_DIG_ICG_MODEM_EN_S) +#define PMU_UPDATE_DIG_ICG_MODEM_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_MODEM_EN_S 31 + +/** PMU_IMM_LP_ICG_REG register + * need_des + */ +#define PMU_IMM_LP_ICG_REG (DR_REG_PMU_BASE + 0xe0) +/** PMU_TIE_LOW_LP_ROOTCLK_SEL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_LP_ROOTCLK_SEL (BIT(30)) +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_M (PMU_TIE_LOW_LP_ROOTCLK_SEL_V << PMU_TIE_LOW_LP_ROOTCLK_SEL_S) +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_V 0x00000001U +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_S 30 +/** PMU_TIE_HIGH_LP_ROOTCLK_SEL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL (BIT(31)) +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_M (PMU_TIE_HIGH_LP_ROOTCLK_SEL_V << PMU_TIE_HIGH_LP_ROOTCLK_SEL_S) +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_V 0x00000001U +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_S 31 + +/** PMU_IMM_PAD_HOLD_ALL_REG register + * need_des + */ +#define PMU_IMM_PAD_HOLD_ALL_REG (DR_REG_PMU_BASE + 0xe4) +/** PMU_TIE_HIGH_LP_PAD_HOLD_ALL : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL (BIT(28)) +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_M (PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S) +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S 28 +/** PMU_TIE_LOW_LP_PAD_HOLD_ALL : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL (BIT(29)) +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_M (PMU_TIE_LOW_LP_PAD_HOLD_ALL_V << PMU_TIE_LOW_LP_PAD_HOLD_ALL_S) +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_S 29 +/** PMU_TIE_HIGH_HP_PAD_HOLD_ALL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL (BIT(30)) +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_M (PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S) +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S 30 +/** PMU_TIE_LOW_HP_PAD_HOLD_ALL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL (BIT(31)) +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_M (PMU_TIE_LOW_HP_PAD_HOLD_ALL_V << PMU_TIE_LOW_HP_PAD_HOLD_ALL_S) +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_S 31 + +/** PMU_IMM_I2C_ISO_REG register + * need_des + */ +#define PMU_IMM_I2C_ISO_REG (DR_REG_PMU_BASE + 0xe8) +/** PMU_TIE_HIGH_I2C_ISO_EN : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_I2C_ISO_EN (BIT(30)) +#define PMU_TIE_HIGH_I2C_ISO_EN_M (PMU_TIE_HIGH_I2C_ISO_EN_V << PMU_TIE_HIGH_I2C_ISO_EN_S) +#define PMU_TIE_HIGH_I2C_ISO_EN_V 0x00000001U +#define PMU_TIE_HIGH_I2C_ISO_EN_S 30 +/** PMU_TIE_LOW_I2C_ISO_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_I2C_ISO_EN (BIT(31)) +#define PMU_TIE_LOW_I2C_ISO_EN_M (PMU_TIE_LOW_I2C_ISO_EN_V << PMU_TIE_LOW_I2C_ISO_EN_S) +#define PMU_TIE_LOW_I2C_ISO_EN_V 0x00000001U +#define PMU_TIE_LOW_I2C_ISO_EN_S 31 + +/** PMU_POWER_WAIT_TIMER0_REG register + * need_des + */ +#define PMU_POWER_WAIT_TIMER0_REG (DR_REG_PMU_BASE + 0xec) +/** PMU_DG_HP_POWERDOWN_TIMER : R/W; bitpos: [13:5]; default: 255; + * need_des + */ +#define PMU_DG_HP_POWERDOWN_TIMER 0x000001FFU +#define PMU_DG_HP_POWERDOWN_TIMER_M (PMU_DG_HP_POWERDOWN_TIMER_V << PMU_DG_HP_POWERDOWN_TIMER_S) +#define PMU_DG_HP_POWERDOWN_TIMER_V 0x000001FFU +#define PMU_DG_HP_POWERDOWN_TIMER_S 5 +/** PMU_DG_HP_POWERUP_TIMER : R/W; bitpos: [22:14]; default: 255; + * need_des + */ +#define PMU_DG_HP_POWERUP_TIMER 0x000001FFU +#define PMU_DG_HP_POWERUP_TIMER_M (PMU_DG_HP_POWERUP_TIMER_V << PMU_DG_HP_POWERUP_TIMER_S) +#define PMU_DG_HP_POWERUP_TIMER_V 0x000001FFU +#define PMU_DG_HP_POWERUP_TIMER_S 14 +/** PMU_DG_HP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; + * need_des + */ +#define PMU_DG_HP_WAIT_TIMER 0x000001FFU +#define PMU_DG_HP_WAIT_TIMER_M (PMU_DG_HP_WAIT_TIMER_V << PMU_DG_HP_WAIT_TIMER_S) +#define PMU_DG_HP_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_HP_WAIT_TIMER_S 23 + +/** PMU_POWER_WAIT_TIMER1_REG register + * need_des + */ +#define PMU_POWER_WAIT_TIMER1_REG (DR_REG_PMU_BASE + 0xf0) +/** PMU_DG_LP_POWERDOWN_TIMER : R/W; bitpos: [15:9]; default: 255; + * need_des + */ +#define PMU_DG_LP_POWERDOWN_TIMER 0x0000007FU +#define PMU_DG_LP_POWERDOWN_TIMER_M (PMU_DG_LP_POWERDOWN_TIMER_V << PMU_DG_LP_POWERDOWN_TIMER_S) +#define PMU_DG_LP_POWERDOWN_TIMER_V 0x0000007FU +#define PMU_DG_LP_POWERDOWN_TIMER_S 9 +/** PMU_DG_LP_POWERUP_TIMER : R/W; bitpos: [22:16]; default: 255; + * need_des + */ +#define PMU_DG_LP_POWERUP_TIMER 0x0000007FU +#define PMU_DG_LP_POWERUP_TIMER_M (PMU_DG_LP_POWERUP_TIMER_V << PMU_DG_LP_POWERUP_TIMER_S) +#define PMU_DG_LP_POWERUP_TIMER_V 0x0000007FU +#define PMU_DG_LP_POWERUP_TIMER_S 16 +/** PMU_DG_LP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; + * need_des + */ +#define PMU_DG_LP_WAIT_TIMER 0x000001FFU +#define PMU_DG_LP_WAIT_TIMER_M (PMU_DG_LP_WAIT_TIMER_V << PMU_DG_LP_WAIT_TIMER_S) +#define PMU_DG_LP_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_LP_WAIT_TIMER_S 23 + +/** PMU_POWER_PD_TOP_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_TOP_CNTL_REG (DR_REG_PMU_BASE + 0xf4) +/** PMU_FORCE_TOP_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_RESET (BIT(0)) +#define PMU_FORCE_TOP_RESET_M (PMU_FORCE_TOP_RESET_V << PMU_FORCE_TOP_RESET_S) +#define PMU_FORCE_TOP_RESET_V 0x00000001U +#define PMU_FORCE_TOP_RESET_S 0 +/** PMU_FORCE_TOP_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_ISO (BIT(1)) +#define PMU_FORCE_TOP_ISO_M (PMU_FORCE_TOP_ISO_V << PMU_FORCE_TOP_ISO_S) +#define PMU_FORCE_TOP_ISO_V 0x00000001U +#define PMU_FORCE_TOP_ISO_S 1 +/** PMU_FORCE_TOP_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_PU (BIT(2)) +#define PMU_FORCE_TOP_PU_M (PMU_FORCE_TOP_PU_V << PMU_FORCE_TOP_PU_S) +#define PMU_FORCE_TOP_PU_V 0x00000001U +#define PMU_FORCE_TOP_PU_S 2 +/** PMU_FORCE_TOP_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_NO_RESET (BIT(3)) +#define PMU_FORCE_TOP_NO_RESET_M (PMU_FORCE_TOP_NO_RESET_V << PMU_FORCE_TOP_NO_RESET_S) +#define PMU_FORCE_TOP_NO_RESET_V 0x00000001U +#define PMU_FORCE_TOP_NO_RESET_S 3 +/** PMU_FORCE_TOP_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_NO_ISO (BIT(4)) +#define PMU_FORCE_TOP_NO_ISO_M (PMU_FORCE_TOP_NO_ISO_V << PMU_FORCE_TOP_NO_ISO_S) +#define PMU_FORCE_TOP_NO_ISO_V 0x00000001U +#define PMU_FORCE_TOP_NO_ISO_S 4 +/** PMU_FORCE_TOP_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_PD (BIT(5)) +#define PMU_FORCE_TOP_PD_M (PMU_FORCE_TOP_PD_V << PMU_FORCE_TOP_PD_S) +#define PMU_FORCE_TOP_PD_V 0x00000001U +#define PMU_FORCE_TOP_PD_S 5 +/** PMU_PD_TOP_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_TOP_MASK 0x0000001FU +#define PMU_PD_TOP_MASK_M (PMU_PD_TOP_MASK_V << PMU_PD_TOP_MASK_S) +#define PMU_PD_TOP_MASK_V 0x0000001FU +#define PMU_PD_TOP_MASK_S 6 +/** PMU_PD_TOP_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_TOP_PD_MASK 0x0000001FU +#define PMU_PD_TOP_PD_MASK_M (PMU_PD_TOP_PD_MASK_V << PMU_PD_TOP_PD_MASK_S) +#define PMU_PD_TOP_PD_MASK_V 0x0000001FU +#define PMU_PD_TOP_PD_MASK_S 27 + +/** PMU_POWER_PD_HPAON_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_HPAON_CNTL_REG (DR_REG_PMU_BASE + 0xf8) +/** PMU_FORCE_HP_AON_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_AON_RESET (BIT(0)) +#define PMU_FORCE_HP_AON_RESET_M (PMU_FORCE_HP_AON_RESET_V << PMU_FORCE_HP_AON_RESET_S) +#define PMU_FORCE_HP_AON_RESET_V 0x00000001U +#define PMU_FORCE_HP_AON_RESET_S 0 +/** PMU_FORCE_HP_AON_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_AON_ISO (BIT(1)) +#define PMU_FORCE_HP_AON_ISO_M (PMU_FORCE_HP_AON_ISO_V << PMU_FORCE_HP_AON_ISO_S) +#define PMU_FORCE_HP_AON_ISO_V 0x00000001U +#define PMU_FORCE_HP_AON_ISO_S 1 +/** PMU_FORCE_HP_AON_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_AON_PU (BIT(2)) +#define PMU_FORCE_HP_AON_PU_M (PMU_FORCE_HP_AON_PU_V << PMU_FORCE_HP_AON_PU_S) +#define PMU_FORCE_HP_AON_PU_V 0x00000001U +#define PMU_FORCE_HP_AON_PU_S 2 +/** PMU_FORCE_HP_AON_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_AON_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_AON_NO_RESET_M (PMU_FORCE_HP_AON_NO_RESET_V << PMU_FORCE_HP_AON_NO_RESET_S) +#define PMU_FORCE_HP_AON_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_AON_NO_RESET_S 3 +/** PMU_FORCE_HP_AON_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_AON_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_AON_NO_ISO_M (PMU_FORCE_HP_AON_NO_ISO_V << PMU_FORCE_HP_AON_NO_ISO_S) +#define PMU_FORCE_HP_AON_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_AON_NO_ISO_S 4 +/** PMU_FORCE_HP_AON_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_AON_PD (BIT(5)) +#define PMU_FORCE_HP_AON_PD_M (PMU_FORCE_HP_AON_PD_V << PMU_FORCE_HP_AON_PD_S) +#define PMU_FORCE_HP_AON_PD_V 0x00000001U +#define PMU_FORCE_HP_AON_PD_S 5 +/** PMU_PD_HP_AON_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_HP_AON_MASK 0x0000001FU +#define PMU_PD_HP_AON_MASK_M (PMU_PD_HP_AON_MASK_V << PMU_PD_HP_AON_MASK_S) +#define PMU_PD_HP_AON_MASK_V 0x0000001FU +#define PMU_PD_HP_AON_MASK_S 6 +/** PMU_PD_HP_AON_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_AON_PD_MASK 0x0000001FU +#define PMU_PD_HP_AON_PD_MASK_M (PMU_PD_HP_AON_PD_MASK_V << PMU_PD_HP_AON_PD_MASK_S) +#define PMU_PD_HP_AON_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_AON_PD_MASK_S 27 + +/** PMU_POWER_PD_HPCPU_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_HPCPU_CNTL_REG (DR_REG_PMU_BASE + 0xfc) +/** PMU_FORCE_HP_CPU_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_RESET (BIT(0)) +#define PMU_FORCE_HP_CPU_RESET_M (PMU_FORCE_HP_CPU_RESET_V << PMU_FORCE_HP_CPU_RESET_S) +#define PMU_FORCE_HP_CPU_RESET_V 0x00000001U +#define PMU_FORCE_HP_CPU_RESET_S 0 +/** PMU_FORCE_HP_CPU_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_ISO (BIT(1)) +#define PMU_FORCE_HP_CPU_ISO_M (PMU_FORCE_HP_CPU_ISO_V << PMU_FORCE_HP_CPU_ISO_S) +#define PMU_FORCE_HP_CPU_ISO_V 0x00000001U +#define PMU_FORCE_HP_CPU_ISO_S 1 +/** PMU_FORCE_HP_CPU_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_PU (BIT(2)) +#define PMU_FORCE_HP_CPU_PU_M (PMU_FORCE_HP_CPU_PU_V << PMU_FORCE_HP_CPU_PU_S) +#define PMU_FORCE_HP_CPU_PU_V 0x00000001U +#define PMU_FORCE_HP_CPU_PU_S 2 +/** PMU_FORCE_HP_CPU_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_CPU_NO_RESET_M (PMU_FORCE_HP_CPU_NO_RESET_V << PMU_FORCE_HP_CPU_NO_RESET_S) +#define PMU_FORCE_HP_CPU_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_CPU_NO_RESET_S 3 +/** PMU_FORCE_HP_CPU_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_CPU_NO_ISO_M (PMU_FORCE_HP_CPU_NO_ISO_V << PMU_FORCE_HP_CPU_NO_ISO_S) +#define PMU_FORCE_HP_CPU_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_CPU_NO_ISO_S 4 +/** PMU_FORCE_HP_CPU_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_PD (BIT(5)) +#define PMU_FORCE_HP_CPU_PD_M (PMU_FORCE_HP_CPU_PD_V << PMU_FORCE_HP_CPU_PD_S) +#define PMU_FORCE_HP_CPU_PD_V 0x00000001U +#define PMU_FORCE_HP_CPU_PD_S 5 +/** PMU_PD_HP_CPU_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_HP_CPU_MASK 0x0000001FU +#define PMU_PD_HP_CPU_MASK_M (PMU_PD_HP_CPU_MASK_V << PMU_PD_HP_CPU_MASK_S) +#define PMU_PD_HP_CPU_MASK_V 0x0000001FU +#define PMU_PD_HP_CPU_MASK_S 6 +/** PMU_PD_HP_CPU_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_CPU_PD_MASK 0x0000001FU +#define PMU_PD_HP_CPU_PD_MASK_M (PMU_PD_HP_CPU_PD_MASK_V << PMU_PD_HP_CPU_PD_MASK_S) +#define PMU_PD_HP_CPU_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_CPU_PD_MASK_S 27 + +/** PMU_POWER_PD_HPPERI_RESERVE_REG register + * need_des + */ +#define PMU_POWER_PD_HPPERI_RESERVE_REG (DR_REG_PMU_BASE + 0x100) +/** PMU_HP_PERI_RESERVE : WT; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_PERI_RESERVE 0xFFFFFFFFU +#define PMU_HP_PERI_RESERVE_M (PMU_HP_PERI_RESERVE_V << PMU_HP_PERI_RESERVE_S) +#define PMU_HP_PERI_RESERVE_V 0xFFFFFFFFU +#define PMU_HP_PERI_RESERVE_S 0 + +/** PMU_POWER_PD_HPWIFI_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_HPWIFI_CNTL_REG (DR_REG_PMU_BASE + 0x104) +/** PMU_FORCE_HP_WIFI_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_WIFI_RESET (BIT(0)) +#define PMU_FORCE_HP_WIFI_RESET_M (PMU_FORCE_HP_WIFI_RESET_V << PMU_FORCE_HP_WIFI_RESET_S) +#define PMU_FORCE_HP_WIFI_RESET_V 0x00000001U +#define PMU_FORCE_HP_WIFI_RESET_S 0 +/** PMU_FORCE_HP_WIFI_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_WIFI_ISO (BIT(1)) +#define PMU_FORCE_HP_WIFI_ISO_M (PMU_FORCE_HP_WIFI_ISO_V << PMU_FORCE_HP_WIFI_ISO_S) +#define PMU_FORCE_HP_WIFI_ISO_V 0x00000001U +#define PMU_FORCE_HP_WIFI_ISO_S 1 +/** PMU_FORCE_HP_WIFI_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_WIFI_PU (BIT(2)) +#define PMU_FORCE_HP_WIFI_PU_M (PMU_FORCE_HP_WIFI_PU_V << PMU_FORCE_HP_WIFI_PU_S) +#define PMU_FORCE_HP_WIFI_PU_V 0x00000001U +#define PMU_FORCE_HP_WIFI_PU_S 2 +/** PMU_FORCE_HP_WIFI_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_WIFI_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_WIFI_NO_RESET_M (PMU_FORCE_HP_WIFI_NO_RESET_V << PMU_FORCE_HP_WIFI_NO_RESET_S) +#define PMU_FORCE_HP_WIFI_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_WIFI_NO_RESET_S 3 +/** PMU_FORCE_HP_WIFI_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_WIFI_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_WIFI_NO_ISO_M (PMU_FORCE_HP_WIFI_NO_ISO_V << PMU_FORCE_HP_WIFI_NO_ISO_S) +#define PMU_FORCE_HP_WIFI_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_WIFI_NO_ISO_S 4 +/** PMU_FORCE_HP_WIFI_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_WIFI_PD (BIT(5)) +#define PMU_FORCE_HP_WIFI_PD_M (PMU_FORCE_HP_WIFI_PD_V << PMU_FORCE_HP_WIFI_PD_S) +#define PMU_FORCE_HP_WIFI_PD_V 0x00000001U +#define PMU_FORCE_HP_WIFI_PD_S 5 +/** PMU_PD_HP_WIFI_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_HP_WIFI_MASK 0x0000001FU +#define PMU_PD_HP_WIFI_MASK_M (PMU_PD_HP_WIFI_MASK_V << PMU_PD_HP_WIFI_MASK_S) +#define PMU_PD_HP_WIFI_MASK_V 0x0000001FU +#define PMU_PD_HP_WIFI_MASK_S 6 +/** PMU_PD_HP_WIFI_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_WIFI_PD_MASK 0x0000001FU +#define PMU_PD_HP_WIFI_PD_MASK_M (PMU_PD_HP_WIFI_PD_MASK_V << PMU_PD_HP_WIFI_PD_MASK_S) +#define PMU_PD_HP_WIFI_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_WIFI_PD_MASK_S 27 + +/** PMU_POWER_PD_LPPERI_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_LPPERI_CNTL_REG (DR_REG_PMU_BASE + 0x108) +/** PMU_FORCE_LP_PERI_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_RESET (BIT(0)) +#define PMU_FORCE_LP_PERI_RESET_M (PMU_FORCE_LP_PERI_RESET_V << PMU_FORCE_LP_PERI_RESET_S) +#define PMU_FORCE_LP_PERI_RESET_V 0x00000001U +#define PMU_FORCE_LP_PERI_RESET_S 0 +/** PMU_FORCE_LP_PERI_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_ISO (BIT(1)) +#define PMU_FORCE_LP_PERI_ISO_M (PMU_FORCE_LP_PERI_ISO_V << PMU_FORCE_LP_PERI_ISO_S) +#define PMU_FORCE_LP_PERI_ISO_V 0x00000001U +#define PMU_FORCE_LP_PERI_ISO_S 1 +/** PMU_FORCE_LP_PERI_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_PU (BIT(2)) +#define PMU_FORCE_LP_PERI_PU_M (PMU_FORCE_LP_PERI_PU_V << PMU_FORCE_LP_PERI_PU_S) +#define PMU_FORCE_LP_PERI_PU_V 0x00000001U +#define PMU_FORCE_LP_PERI_PU_S 2 +/** PMU_FORCE_LP_PERI_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_NO_RESET (BIT(3)) +#define PMU_FORCE_LP_PERI_NO_RESET_M (PMU_FORCE_LP_PERI_NO_RESET_V << PMU_FORCE_LP_PERI_NO_RESET_S) +#define PMU_FORCE_LP_PERI_NO_RESET_V 0x00000001U +#define PMU_FORCE_LP_PERI_NO_RESET_S 3 +/** PMU_FORCE_LP_PERI_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_NO_ISO (BIT(4)) +#define PMU_FORCE_LP_PERI_NO_ISO_M (PMU_FORCE_LP_PERI_NO_ISO_V << PMU_FORCE_LP_PERI_NO_ISO_S) +#define PMU_FORCE_LP_PERI_NO_ISO_V 0x00000001U +#define PMU_FORCE_LP_PERI_NO_ISO_S 4 +/** PMU_FORCE_LP_PERI_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_PD (BIT(5)) +#define PMU_FORCE_LP_PERI_PD_M (PMU_FORCE_LP_PERI_PD_V << PMU_FORCE_LP_PERI_PD_S) +#define PMU_FORCE_LP_PERI_PD_V 0x00000001U +#define PMU_FORCE_LP_PERI_PD_S 5 + +/** PMU_POWER_PD_MEM_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_MEM_CNTL_REG (DR_REG_PMU_BASE + 0x10c) +/** PMU_FORCE_HP_MEM_ISO : R/W; bitpos: [3:0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_MEM_ISO 0x0000000FU +#define PMU_FORCE_HP_MEM_ISO_M (PMU_FORCE_HP_MEM_ISO_V << PMU_FORCE_HP_MEM_ISO_S) +#define PMU_FORCE_HP_MEM_ISO_V 0x0000000FU +#define PMU_FORCE_HP_MEM_ISO_S 0 +/** PMU_FORCE_HP_MEM_PD : R/W; bitpos: [7:4]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_MEM_PD 0x0000000FU +#define PMU_FORCE_HP_MEM_PD_M (PMU_FORCE_HP_MEM_PD_V << PMU_FORCE_HP_MEM_PD_S) +#define PMU_FORCE_HP_MEM_PD_V 0x0000000FU +#define PMU_FORCE_HP_MEM_PD_S 4 +/** PMU_FORCE_HP_MEM_NO_ISO : R/W; bitpos: [27:24]; default: 15; + * need_des + */ +#define PMU_FORCE_HP_MEM_NO_ISO 0x0000000FU +#define PMU_FORCE_HP_MEM_NO_ISO_M (PMU_FORCE_HP_MEM_NO_ISO_V << PMU_FORCE_HP_MEM_NO_ISO_S) +#define PMU_FORCE_HP_MEM_NO_ISO_V 0x0000000FU +#define PMU_FORCE_HP_MEM_NO_ISO_S 24 +/** PMU_FORCE_HP_MEM_PU : R/W; bitpos: [31:28]; default: 15; + * need_des + */ +#define PMU_FORCE_HP_MEM_PU 0x0000000FU +#define PMU_FORCE_HP_MEM_PU_M (PMU_FORCE_HP_MEM_PU_V << PMU_FORCE_HP_MEM_PU_S) +#define PMU_FORCE_HP_MEM_PU_V 0x0000000FU +#define PMU_FORCE_HP_MEM_PU_S 28 + +/** PMU_POWER_PD_MEM_MASK_REG register + * need_des + */ +#define PMU_POWER_PD_MEM_MASK_REG (DR_REG_PMU_BASE + 0x110) +/** PMU_PD_HP_MEM2_PD_MASK : R/W; bitpos: [4:0]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM2_PD_MASK 0x0000001FU +#define PMU_PD_HP_MEM2_PD_MASK_M (PMU_PD_HP_MEM2_PD_MASK_V << PMU_PD_HP_MEM2_PD_MASK_S) +#define PMU_PD_HP_MEM2_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM2_PD_MASK_S 0 +/** PMU_PD_HP_MEM1_PD_MASK : R/W; bitpos: [9:5]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM1_PD_MASK 0x0000001FU +#define PMU_PD_HP_MEM1_PD_MASK_M (PMU_PD_HP_MEM1_PD_MASK_V << PMU_PD_HP_MEM1_PD_MASK_S) +#define PMU_PD_HP_MEM1_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM1_PD_MASK_S 5 +/** PMU_PD_HP_MEM0_PD_MASK : R/W; bitpos: [14:10]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM0_PD_MASK 0x0000001FU +#define PMU_PD_HP_MEM0_PD_MASK_M (PMU_PD_HP_MEM0_PD_MASK_V << PMU_PD_HP_MEM0_PD_MASK_S) +#define PMU_PD_HP_MEM0_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM0_PD_MASK_S 10 +/** PMU_PD_HP_MEM2_MASK : R/W; bitpos: [21:17]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM2_MASK 0x0000001FU +#define PMU_PD_HP_MEM2_MASK_M (PMU_PD_HP_MEM2_MASK_V << PMU_PD_HP_MEM2_MASK_S) +#define PMU_PD_HP_MEM2_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM2_MASK_S 17 +/** PMU_PD_HP_MEM1_MASK : R/W; bitpos: [26:22]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM1_MASK 0x0000001FU +#define PMU_PD_HP_MEM1_MASK_M (PMU_PD_HP_MEM1_MASK_V << PMU_PD_HP_MEM1_MASK_S) +#define PMU_PD_HP_MEM1_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM1_MASK_S 22 +/** PMU_PD_HP_MEM0_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM0_MASK 0x0000001FU +#define PMU_PD_HP_MEM0_MASK_M (PMU_PD_HP_MEM0_MASK_V << PMU_PD_HP_MEM0_MASK_S) +#define PMU_PD_HP_MEM0_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM0_MASK_S 27 + +/** PMU_POWER_HP_PAD_REG register + * need_des + */ +#define PMU_POWER_HP_PAD_REG (DR_REG_PMU_BASE + 0x114) +/** PMU_FORCE_HP_PAD_NO_ISO_ALL : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PAD_NO_ISO_ALL (BIT(0)) +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_M (PMU_FORCE_HP_PAD_NO_ISO_ALL_V << PMU_FORCE_HP_PAD_NO_ISO_ALL_S) +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_V 0x00000001U +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_S 0 +/** PMU_FORCE_HP_PAD_ISO_ALL : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PAD_ISO_ALL (BIT(1)) +#define PMU_FORCE_HP_PAD_ISO_ALL_M (PMU_FORCE_HP_PAD_ISO_ALL_V << PMU_FORCE_HP_PAD_ISO_ALL_S) +#define PMU_FORCE_HP_PAD_ISO_ALL_V 0x00000001U +#define PMU_FORCE_HP_PAD_ISO_ALL_S 1 + +/** PMU_POWER_VDD_SPI_CNTL_REG register + * need_des + */ +#define PMU_POWER_VDD_SPI_CNTL_REG (DR_REG_PMU_BASE + 0x118) +/** PMU_VDD_SPI_PWR_WAIT : R/W; bitpos: [28:18]; default: 255; + * need_des + */ +#define PMU_VDD_SPI_PWR_WAIT 0x000007FFU +#define PMU_VDD_SPI_PWR_WAIT_M (PMU_VDD_SPI_PWR_WAIT_V << PMU_VDD_SPI_PWR_WAIT_S) +#define PMU_VDD_SPI_PWR_WAIT_V 0x000007FFU +#define PMU_VDD_SPI_PWR_WAIT_S 18 +/** PMU_VDD_SPI_PWR_SW : R/W; bitpos: [30:29]; default: 3; + * need_des + */ +#define PMU_VDD_SPI_PWR_SW 0x00000003U +#define PMU_VDD_SPI_PWR_SW_M (PMU_VDD_SPI_PWR_SW_V << PMU_VDD_SPI_PWR_SW_S) +#define PMU_VDD_SPI_PWR_SW_V 0x00000003U +#define PMU_VDD_SPI_PWR_SW_S 29 +/** PMU_VDD_SPI_PWR_SEL_SW : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_VDD_SPI_PWR_SEL_SW (BIT(31)) +#define PMU_VDD_SPI_PWR_SEL_SW_M (PMU_VDD_SPI_PWR_SEL_SW_V << PMU_VDD_SPI_PWR_SEL_SW_S) +#define PMU_VDD_SPI_PWR_SEL_SW_V 0x00000001U +#define PMU_VDD_SPI_PWR_SEL_SW_S 31 + +/** PMU_POWER_CK_WAIT_CNTL_REG register + * need_des + */ +#define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x11c) +/** PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 256; + * need_des + */ +#define PMU_WAIT_XTL_STABLE 0x0000FFFFU +#define PMU_WAIT_XTL_STABLE_M (PMU_WAIT_XTL_STABLE_V << PMU_WAIT_XTL_STABLE_S) +#define PMU_WAIT_XTL_STABLE_V 0x0000FFFFU +#define PMU_WAIT_XTL_STABLE_S 0 +/** PMU_WAIT_PLL_STABLE : R/W; bitpos: [31:16]; default: 256; + * need_des + */ +#define PMU_WAIT_PLL_STABLE 0x0000FFFFU +#define PMU_WAIT_PLL_STABLE_M (PMU_WAIT_PLL_STABLE_V << PMU_WAIT_PLL_STABLE_S) +#define PMU_WAIT_PLL_STABLE_V 0x0000FFFFU +#define PMU_WAIT_PLL_STABLE_S 16 + +/** PMU_SLP_WAKEUP_CNTL0_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL0_REG (DR_REG_PMU_BASE + 0x120) +/** PMU_SLEEP_REQ : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLEEP_REQ (BIT(31)) +#define PMU_SLEEP_REQ_M (PMU_SLEEP_REQ_V << PMU_SLEEP_REQ_S) +#define PMU_SLEEP_REQ_V 0x00000001U +#define PMU_SLEEP_REQ_S 31 + +/** PMU_SLP_WAKEUP_CNTL1_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL1_REG (DR_REG_PMU_BASE + 0x124) +/** PMU_SLEEP_REJECT_ENA : R/W; bitpos: [30:0]; default: 0; + * need_des + */ +#define PMU_SLEEP_REJECT_ENA 0x7FFFFFFFU +#define PMU_SLEEP_REJECT_ENA_M (PMU_SLEEP_REJECT_ENA_V << PMU_SLEEP_REJECT_ENA_S) +#define PMU_SLEEP_REJECT_ENA_V 0x7FFFFFFFU +#define PMU_SLEEP_REJECT_ENA_S 0 +/** PMU_SLP_REJECT_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLP_REJECT_EN (BIT(31)) +#define PMU_SLP_REJECT_EN_M (PMU_SLP_REJECT_EN_V << PMU_SLP_REJECT_EN_S) +#define PMU_SLP_REJECT_EN_V 0x00000001U +#define PMU_SLP_REJECT_EN_S 31 + +/** PMU_SLP_WAKEUP_CNTL2_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL2_REG (DR_REG_PMU_BASE + 0x128) +/** PMU_WAKEUP_ENA : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_WAKEUP_ENA 0xFFFFFFFFU +#define PMU_WAKEUP_ENA_M (PMU_WAKEUP_ENA_V << PMU_WAKEUP_ENA_S) +#define PMU_WAKEUP_ENA_V 0xFFFFFFFFU +#define PMU_WAKEUP_ENA_S 0 + +/** PMU_SLP_WAKEUP_CNTL3_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL3_REG (DR_REG_PMU_BASE + 0x12c) +/** PMU_LP_MIN_SLP_VAL : R/W; bitpos: [7:0]; default: 0; + * need_des + */ +#define PMU_LP_MIN_SLP_VAL 0x000000FFU +#define PMU_LP_MIN_SLP_VAL_M (PMU_LP_MIN_SLP_VAL_V << PMU_LP_MIN_SLP_VAL_S) +#define PMU_LP_MIN_SLP_VAL_V 0x000000FFU +#define PMU_LP_MIN_SLP_VAL_S 0 +/** PMU_HP_MIN_SLP_VAL : R/W; bitpos: [15:8]; default: 0; + * need_des + */ +#define PMU_HP_MIN_SLP_VAL 0x000000FFU +#define PMU_HP_MIN_SLP_VAL_M (PMU_HP_MIN_SLP_VAL_V << PMU_HP_MIN_SLP_VAL_S) +#define PMU_HP_MIN_SLP_VAL_V 0x000000FFU +#define PMU_HP_MIN_SLP_VAL_S 8 +/** PMU_SLEEP_PRT_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_SLEEP_PRT_SEL 0x00000003U +#define PMU_SLEEP_PRT_SEL_M (PMU_SLEEP_PRT_SEL_V << PMU_SLEEP_PRT_SEL_S) +#define PMU_SLEEP_PRT_SEL_V 0x00000003U +#define PMU_SLEEP_PRT_SEL_S 16 + +/** PMU_SLP_WAKEUP_CNTL4_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL4_REG (DR_REG_PMU_BASE + 0x130) +/** PMU_SLP_REJECT_CAUSE_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLP_REJECT_CAUSE_CLR (BIT(31)) +#define PMU_SLP_REJECT_CAUSE_CLR_M (PMU_SLP_REJECT_CAUSE_CLR_V << PMU_SLP_REJECT_CAUSE_CLR_S) +#define PMU_SLP_REJECT_CAUSE_CLR_V 0x00000001U +#define PMU_SLP_REJECT_CAUSE_CLR_S 31 + +/** PMU_SLP_WAKEUP_CNTL5_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL5_REG (DR_REG_PMU_BASE + 0x134) +/** PMU_MODEM_WAIT_TARGET : R/W; bitpos: [19:0]; default: 128; + * need_des + */ +#define PMU_MODEM_WAIT_TARGET 0x000FFFFFU +#define PMU_MODEM_WAIT_TARGET_M (PMU_MODEM_WAIT_TARGET_V << PMU_MODEM_WAIT_TARGET_S) +#define PMU_MODEM_WAIT_TARGET_V 0x000FFFFFU +#define PMU_MODEM_WAIT_TARGET_S 0 +/** PMU_LP_ANA_WAIT_TARGET : R/W; bitpos: [31:24]; default: 1; + * need_des + */ +#define PMU_LP_ANA_WAIT_TARGET 0x000000FFU +#define PMU_LP_ANA_WAIT_TARGET_M (PMU_LP_ANA_WAIT_TARGET_V << PMU_LP_ANA_WAIT_TARGET_S) +#define PMU_LP_ANA_WAIT_TARGET_V 0x000000FFU +#define PMU_LP_ANA_WAIT_TARGET_S 24 + +/** PMU_SLP_WAKEUP_CNTL6_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL6_REG (DR_REG_PMU_BASE + 0x138) +/** PMU_SOC_WAKEUP_WAIT : R/W; bitpos: [19:0]; default: 128; + * need_des + */ +#define PMU_SOC_WAKEUP_WAIT 0x000FFFFFU +#define PMU_SOC_WAKEUP_WAIT_M (PMU_SOC_WAKEUP_WAIT_V << PMU_SOC_WAKEUP_WAIT_S) +#define PMU_SOC_WAKEUP_WAIT_V 0x000FFFFFU +#define PMU_SOC_WAKEUP_WAIT_S 0 +/** PMU_SOC_WAKEUP_WAIT_CFG : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_WAIT_CFG 0x00000003U +#define PMU_SOC_WAKEUP_WAIT_CFG_M (PMU_SOC_WAKEUP_WAIT_CFG_V << PMU_SOC_WAKEUP_WAIT_CFG_S) +#define PMU_SOC_WAKEUP_WAIT_CFG_V 0x00000003U +#define PMU_SOC_WAKEUP_WAIT_CFG_S 30 + +/** PMU_SLP_WAKEUP_CNTL7_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL7_REG (DR_REG_PMU_BASE + 0x13c) +/** PMU_ANA_WAIT_TARGET : R/W; bitpos: [31:16]; default: 1; + * need_des + */ +#define PMU_ANA_WAIT_TARGET 0x0000FFFFU +#define PMU_ANA_WAIT_TARGET_M (PMU_ANA_WAIT_TARGET_V << PMU_ANA_WAIT_TARGET_S) +#define PMU_ANA_WAIT_TARGET_V 0x0000FFFFU +#define PMU_ANA_WAIT_TARGET_S 16 + +/** PMU_SLP_WAKEUP_STATUS0_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_STATUS0_REG (DR_REG_PMU_BASE + 0x140) +/** PMU_WAKEUP_CAUSE : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_WAKEUP_CAUSE 0xFFFFFFFFU +#define PMU_WAKEUP_CAUSE_M (PMU_WAKEUP_CAUSE_V << PMU_WAKEUP_CAUSE_S) +#define PMU_WAKEUP_CAUSE_V 0xFFFFFFFFU +#define PMU_WAKEUP_CAUSE_S 0 + +/** PMU_SLP_WAKEUP_STATUS1_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_STATUS1_REG (DR_REG_PMU_BASE + 0x144) +/** PMU_REJECT_CAUSE : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_REJECT_CAUSE 0xFFFFFFFFU +#define PMU_REJECT_CAUSE_M (PMU_REJECT_CAUSE_V << PMU_REJECT_CAUSE_S) +#define PMU_REJECT_CAUSE_V 0xFFFFFFFFU +#define PMU_REJECT_CAUSE_S 0 + +/** PMU_HP_CK_POWERON_REG register + * need_des + */ +#define PMU_HP_CK_POWERON_REG (DR_REG_PMU_BASE + 0x148) +/** PMU_I2C_POR_WAIT_TARGET : R/W; bitpos: [7:0]; default: 50; + * need_des + */ +#define PMU_I2C_POR_WAIT_TARGET 0x000000FFU +#define PMU_I2C_POR_WAIT_TARGET_M (PMU_I2C_POR_WAIT_TARGET_V << PMU_I2C_POR_WAIT_TARGET_S) +#define PMU_I2C_POR_WAIT_TARGET_V 0x000000FFU +#define PMU_I2C_POR_WAIT_TARGET_S 0 + +/** PMU_HP_CK_CNTL_REG register + * need_des + */ +#define PMU_HP_CK_CNTL_REG (DR_REG_PMU_BASE + 0x14c) +/** PMU_MODIFY_ICG_CNTL_WAIT : R/W; bitpos: [7:0]; default: 10; + * need_des + */ +#define PMU_MODIFY_ICG_CNTL_WAIT 0x000000FFU +#define PMU_MODIFY_ICG_CNTL_WAIT_M (PMU_MODIFY_ICG_CNTL_WAIT_V << PMU_MODIFY_ICG_CNTL_WAIT_S) +#define PMU_MODIFY_ICG_CNTL_WAIT_V 0x000000FFU +#define PMU_MODIFY_ICG_CNTL_WAIT_S 0 +/** PMU_SWITCH_ICG_CNTL_WAIT : R/W; bitpos: [15:8]; default: 10; + * need_des + */ +#define PMU_SWITCH_ICG_CNTL_WAIT 0x000000FFU +#define PMU_SWITCH_ICG_CNTL_WAIT_M (PMU_SWITCH_ICG_CNTL_WAIT_V << PMU_SWITCH_ICG_CNTL_WAIT_S) +#define PMU_SWITCH_ICG_CNTL_WAIT_V 0x000000FFU +#define PMU_SWITCH_ICG_CNTL_WAIT_S 8 + +/** PMU_POR_STATUS_REG register + * need_des + */ +#define PMU_POR_STATUS_REG (DR_REG_PMU_BASE + 0x150) +/** PMU_POR_DONE : RO; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_POR_DONE (BIT(31)) +#define PMU_POR_DONE_M (PMU_POR_DONE_V << PMU_POR_DONE_S) +#define PMU_POR_DONE_V 0x00000001U +#define PMU_POR_DONE_S 31 + +/** PMU_RF_PWC_REG register + * need_des + */ +#define PMU_RF_PWC_REG (DR_REG_PMU_BASE + 0x154) +/** PMU_PERIF_I2C_RSTB : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_PERIF_I2C_RSTB (BIT(26)) +#define PMU_PERIF_I2C_RSTB_M (PMU_PERIF_I2C_RSTB_V << PMU_PERIF_I2C_RSTB_S) +#define PMU_PERIF_I2C_RSTB_V 0x00000001U +#define PMU_PERIF_I2C_RSTB_S 26 +/** PMU_XPD_PERIF_I2C : R/W; bitpos: [27]; default: 1; + * need_des + */ +#define PMU_XPD_PERIF_I2C (BIT(27)) +#define PMU_XPD_PERIF_I2C_M (PMU_XPD_PERIF_I2C_V << PMU_XPD_PERIF_I2C_S) +#define PMU_XPD_PERIF_I2C_V 0x00000001U +#define PMU_XPD_PERIF_I2C_S 27 +/** PMU_XPD_TXRF_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_XPD_TXRF_I2C (BIT(28)) +#define PMU_XPD_TXRF_I2C_M (PMU_XPD_TXRF_I2C_V << PMU_XPD_TXRF_I2C_S) +#define PMU_XPD_TXRF_I2C_V 0x00000001U +#define PMU_XPD_TXRF_I2C_S 28 +/** PMU_XPD_RFRX_PBUS : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_XPD_RFRX_PBUS (BIT(29)) +#define PMU_XPD_RFRX_PBUS_M (PMU_XPD_RFRX_PBUS_V << PMU_XPD_RFRX_PBUS_S) +#define PMU_XPD_RFRX_PBUS_V 0x00000001U +#define PMU_XPD_RFRX_PBUS_S 29 +/** PMU_XPD_CKGEN_I2C : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_XPD_CKGEN_I2C (BIT(30)) +#define PMU_XPD_CKGEN_I2C_M (PMU_XPD_CKGEN_I2C_V << PMU_XPD_CKGEN_I2C_S) +#define PMU_XPD_CKGEN_I2C_V 0x00000001U +#define PMU_XPD_CKGEN_I2C_S 30 +/** PMU_XPD_PLL_I2C : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_XPD_PLL_I2C (BIT(31)) +#define PMU_XPD_PLL_I2C_M (PMU_XPD_PLL_I2C_V << PMU_XPD_PLL_I2C_S) +#define PMU_XPD_PLL_I2C_V 0x00000001U +#define PMU_XPD_PLL_I2C_S 31 + +/** PMU_BACKUP_CFG_REG register + * need_des + */ +#define PMU_BACKUP_CFG_REG (DR_REG_PMU_BASE + 0x158) +/** PMU_BACKUP_SYS_CLK_NO_DIV : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_BACKUP_SYS_CLK_NO_DIV (BIT(31)) +#define PMU_BACKUP_SYS_CLK_NO_DIV_M (PMU_BACKUP_SYS_CLK_NO_DIV_V << PMU_BACKUP_SYS_CLK_NO_DIV_S) +#define PMU_BACKUP_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_BACKUP_SYS_CLK_NO_DIV_S 31 + +/** PMU_INT_RAW_REG register + * need_des + */ +#define PMU_INT_RAW_REG (DR_REG_PMU_BASE + 0x15c) +/** PMU_LP_CPU_EXC_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_RAW (BIT(27)) +#define PMU_LP_CPU_EXC_INT_RAW_M (PMU_LP_CPU_EXC_INT_RAW_V << PMU_LP_CPU_EXC_INT_RAW_S) +#define PMU_LP_CPU_EXC_INT_RAW_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_RAW_S 27 +/** PMU_SDIO_IDLE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_RAW (BIT(28)) +#define PMU_SDIO_IDLE_INT_RAW_M (PMU_SDIO_IDLE_INT_RAW_V << PMU_SDIO_IDLE_INT_RAW_S) +#define PMU_SDIO_IDLE_INT_RAW_V 0x00000001U +#define PMU_SDIO_IDLE_INT_RAW_S 28 +/** PMU_SW_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_RAW (BIT(29)) +#define PMU_SW_INT_RAW_M (PMU_SW_INT_RAW_V << PMU_SW_INT_RAW_S) +#define PMU_SW_INT_RAW_V 0x00000001U +#define PMU_SW_INT_RAW_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_RAW (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_RAW_M (PMU_SOC_SLEEP_REJECT_INT_RAW_V << PMU_SOC_SLEEP_REJECT_INT_RAW_S) +#define PMU_SOC_SLEEP_REJECT_INT_RAW_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_RAW_S 30 +/** PMU_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_RAW (BIT(31)) +#define PMU_SOC_WAKEUP_INT_RAW_M (PMU_SOC_WAKEUP_INT_RAW_V << PMU_SOC_WAKEUP_INT_RAW_S) +#define PMU_SOC_WAKEUP_INT_RAW_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_RAW_S 31 + +/** PMU_HP_INT_ST_REG register + * need_des + */ +#define PMU_HP_INT_ST_REG (DR_REG_PMU_BASE + 0x160) +/** PMU_LP_CPU_EXC_INT_ST : RO; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_ST (BIT(27)) +#define PMU_LP_CPU_EXC_INT_ST_M (PMU_LP_CPU_EXC_INT_ST_V << PMU_LP_CPU_EXC_INT_ST_S) +#define PMU_LP_CPU_EXC_INT_ST_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_ST_S 27 +/** PMU_SDIO_IDLE_INT_ST : RO; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_ST (BIT(28)) +#define PMU_SDIO_IDLE_INT_ST_M (PMU_SDIO_IDLE_INT_ST_V << PMU_SDIO_IDLE_INT_ST_S) +#define PMU_SDIO_IDLE_INT_ST_V 0x00000001U +#define PMU_SDIO_IDLE_INT_ST_S 28 +/** PMU_SW_INT_ST : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_ST (BIT(29)) +#define PMU_SW_INT_ST_M (PMU_SW_INT_ST_V << PMU_SW_INT_ST_S) +#define PMU_SW_INT_ST_V 0x00000001U +#define PMU_SW_INT_ST_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_ST (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_ST_M (PMU_SOC_SLEEP_REJECT_INT_ST_V << PMU_SOC_SLEEP_REJECT_INT_ST_S) +#define PMU_SOC_SLEEP_REJECT_INT_ST_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_ST_S 30 +/** PMU_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_ST (BIT(31)) +#define PMU_SOC_WAKEUP_INT_ST_M (PMU_SOC_WAKEUP_INT_ST_V << PMU_SOC_WAKEUP_INT_ST_S) +#define PMU_SOC_WAKEUP_INT_ST_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_ST_S 31 + +/** PMU_HP_INT_ENA_REG register + * need_des + */ +#define PMU_HP_INT_ENA_REG (DR_REG_PMU_BASE + 0x164) +/** PMU_LP_CPU_EXC_INT_ENA : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_ENA (BIT(27)) +#define PMU_LP_CPU_EXC_INT_ENA_M (PMU_LP_CPU_EXC_INT_ENA_V << PMU_LP_CPU_EXC_INT_ENA_S) +#define PMU_LP_CPU_EXC_INT_ENA_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_ENA_S 27 +/** PMU_SDIO_IDLE_INT_ENA : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_ENA (BIT(28)) +#define PMU_SDIO_IDLE_INT_ENA_M (PMU_SDIO_IDLE_INT_ENA_V << PMU_SDIO_IDLE_INT_ENA_S) +#define PMU_SDIO_IDLE_INT_ENA_V 0x00000001U +#define PMU_SDIO_IDLE_INT_ENA_S 28 +/** PMU_SW_INT_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_ENA (BIT(29)) +#define PMU_SW_INT_ENA_M (PMU_SW_INT_ENA_V << PMU_SW_INT_ENA_S) +#define PMU_SW_INT_ENA_V 0x00000001U +#define PMU_SW_INT_ENA_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_ENA (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_ENA_M (PMU_SOC_SLEEP_REJECT_INT_ENA_V << PMU_SOC_SLEEP_REJECT_INT_ENA_S) +#define PMU_SOC_SLEEP_REJECT_INT_ENA_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_ENA_S 30 +/** PMU_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_ENA (BIT(31)) +#define PMU_SOC_WAKEUP_INT_ENA_M (PMU_SOC_WAKEUP_INT_ENA_V << PMU_SOC_WAKEUP_INT_ENA_S) +#define PMU_SOC_WAKEUP_INT_ENA_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_ENA_S 31 + +/** PMU_HP_INT_CLR_REG register + * need_des + */ +#define PMU_HP_INT_CLR_REG (DR_REG_PMU_BASE + 0x168) +/** PMU_LP_CPU_EXC_INT_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_CLR (BIT(27)) +#define PMU_LP_CPU_EXC_INT_CLR_M (PMU_LP_CPU_EXC_INT_CLR_V << PMU_LP_CPU_EXC_INT_CLR_S) +#define PMU_LP_CPU_EXC_INT_CLR_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_CLR_S 27 +/** PMU_SDIO_IDLE_INT_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_CLR (BIT(28)) +#define PMU_SDIO_IDLE_INT_CLR_M (PMU_SDIO_IDLE_INT_CLR_V << PMU_SDIO_IDLE_INT_CLR_S) +#define PMU_SDIO_IDLE_INT_CLR_V 0x00000001U +#define PMU_SDIO_IDLE_INT_CLR_S 28 +/** PMU_SW_INT_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_CLR (BIT(29)) +#define PMU_SW_INT_CLR_M (PMU_SW_INT_CLR_V << PMU_SW_INT_CLR_S) +#define PMU_SW_INT_CLR_V 0x00000001U +#define PMU_SW_INT_CLR_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_CLR (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_CLR_M (PMU_SOC_SLEEP_REJECT_INT_CLR_V << PMU_SOC_SLEEP_REJECT_INT_CLR_S) +#define PMU_SOC_SLEEP_REJECT_INT_CLR_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_CLR_S 30 +/** PMU_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_CLR (BIT(31)) +#define PMU_SOC_WAKEUP_INT_CLR_M (PMU_SOC_WAKEUP_INT_CLR_V << PMU_SOC_WAKEUP_INT_CLR_S) +#define PMU_SOC_WAKEUP_INT_CLR_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_CLR_S 31 + +/** PMU_LP_INT_RAW_REG register + * need_des + */ +#define PMU_LP_INT_RAW_REG (DR_REG_PMU_BASE + 0x16c) +/** PMU_LP_CPU_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_RAW (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_RAW_M (PMU_LP_CPU_WAKEUP_INT_RAW_V << PMU_LP_CPU_WAKEUP_INT_RAW_S) +#define PMU_LP_CPU_WAKEUP_INT_RAW_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_RAW_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_M (PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_V << PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_M (PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_V << PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_M (PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_V << PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_M (PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_V << PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S 30 +/** PMU_HP_SW_TRIGGER_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_RAW (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_RAW_M (PMU_HP_SW_TRIGGER_INT_RAW_V << PMU_HP_SW_TRIGGER_INT_RAW_S) +#define PMU_HP_SW_TRIGGER_INT_RAW_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_RAW_S 31 + +/** PMU_LP_INT_ST_REG register + * need_des + */ +#define PMU_LP_INT_ST_REG (DR_REG_PMU_BASE + 0x170) +/** PMU_LP_CPU_WAKEUP_INT_ST : RO; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_ST (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_ST_M (PMU_LP_CPU_WAKEUP_INT_ST_V << PMU_LP_CPU_WAKEUP_INT_ST_S) +#define PMU_LP_CPU_WAKEUP_INT_ST_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_ST_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_ST : RO; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_M (PMU_SLEEP_SWITCH_MODEM_END_INT_ST_V << PMU_SLEEP_SWITCH_MODEM_END_INT_ST_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_M (PMU_MODEM_SWITCH_SLEEP_END_INT_ST_V << PMU_MODEM_SWITCH_SLEEP_END_INT_ST_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_ST : RO; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_M (PMU_SLEEP_SWITCH_MODEM_START_INT_ST_V << PMU_SLEEP_SWITCH_MODEM_START_INT_ST_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_M (PMU_MODEM_SWITCH_SLEEP_START_INT_ST_V << PMU_MODEM_SWITCH_SLEEP_START_INT_ST_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S 30 +/** PMU_HP_SW_TRIGGER_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_ST (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_ST_M (PMU_HP_SW_TRIGGER_INT_ST_V << PMU_HP_SW_TRIGGER_INT_ST_S) +#define PMU_HP_SW_TRIGGER_INT_ST_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_ST_S 31 + +/** PMU_LP_INT_ENA_REG register + * need_des + */ +#define PMU_LP_INT_ENA_REG (DR_REG_PMU_BASE + 0x174) +/** PMU_LP_CPU_WAKEUP_INT_ENA : R/W; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_ENA (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_ENA_M (PMU_LP_CPU_WAKEUP_INT_ENA_V << PMU_LP_CPU_WAKEUP_INT_ENA_S) +#define PMU_LP_CPU_WAKEUP_INT_ENA_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_ENA_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_ENA : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_M (PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_V << PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_M (PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_V << PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_ENA : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_M (PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_V << PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_M (PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_V << PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S 30 +/** PMU_HP_SW_TRIGGER_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_ENA (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_ENA_M (PMU_HP_SW_TRIGGER_INT_ENA_V << PMU_HP_SW_TRIGGER_INT_ENA_S) +#define PMU_HP_SW_TRIGGER_INT_ENA_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_ENA_S 31 + +/** PMU_LP_INT_CLR_REG register + * need_des + */ +#define PMU_LP_INT_CLR_REG (DR_REG_PMU_BASE + 0x178) +/** PMU_LP_CPU_WAKEUP_INT_CLR : WT; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_CLR (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_CLR_M (PMU_LP_CPU_WAKEUP_INT_CLR_V << PMU_LP_CPU_WAKEUP_INT_CLR_S) +#define PMU_LP_CPU_WAKEUP_INT_CLR_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_CLR_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_CLR : WT; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_M (PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_V << PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_M (PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_V << PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_M (PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_V << PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_M (PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_V << PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S 30 +/** PMU_HP_SW_TRIGGER_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_CLR (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_CLR_M (PMU_HP_SW_TRIGGER_INT_CLR_V << PMU_HP_SW_TRIGGER_INT_CLR_S) +#define PMU_HP_SW_TRIGGER_INT_CLR_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_CLR_S 31 + +/** PMU_LP_CPU_PWR0_REG register + * need_des + */ +#define PMU_LP_CPU_PWR0_REG (DR_REG_PMU_BASE + 0x17c) +/** PMU_LP_CPU_WAITI_RDY : RO; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAITI_RDY (BIT(0)) +#define PMU_LP_CPU_WAITI_RDY_M (PMU_LP_CPU_WAITI_RDY_V << PMU_LP_CPU_WAITI_RDY_S) +#define PMU_LP_CPU_WAITI_RDY_V 0x00000001U +#define PMU_LP_CPU_WAITI_RDY_S 0 +/** PMU_LP_CPU_STALL_RDY : RO; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_LP_CPU_STALL_RDY (BIT(1)) +#define PMU_LP_CPU_STALL_RDY_M (PMU_LP_CPU_STALL_RDY_V << PMU_LP_CPU_STALL_RDY_S) +#define PMU_LP_CPU_STALL_RDY_V 0x00000001U +#define PMU_LP_CPU_STALL_RDY_S 1 +/** PMU_LP_CPU_FORCE_STALL : R/W; bitpos: [18]; default: 0; + * need_des + */ +#define PMU_LP_CPU_FORCE_STALL (BIT(18)) +#define PMU_LP_CPU_FORCE_STALL_M (PMU_LP_CPU_FORCE_STALL_V << PMU_LP_CPU_FORCE_STALL_S) +#define PMU_LP_CPU_FORCE_STALL_V 0x00000001U +#define PMU_LP_CPU_FORCE_STALL_S 18 +/** PMU_LP_CPU_SLP_WAITI_FLAG_EN : R/W; bitpos: [19]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN (BIT(19)) +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_M (PMU_LP_CPU_SLP_WAITI_FLAG_EN_V << PMU_LP_CPU_SLP_WAITI_FLAG_EN_S) +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_S 19 +/** PMU_LP_CPU_SLP_STALL_FLAG_EN : R/W; bitpos: [20]; default: 1; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_FLAG_EN (BIT(20)) +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_M (PMU_LP_CPU_SLP_STALL_FLAG_EN_V << PMU_LP_CPU_SLP_STALL_FLAG_EN_S) +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_S 20 +/** PMU_LP_CPU_SLP_STALL_WAIT : R/W; bitpos: [28:21]; default: 255; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_WAIT 0x000000FFU +#define PMU_LP_CPU_SLP_STALL_WAIT_M (PMU_LP_CPU_SLP_STALL_WAIT_V << PMU_LP_CPU_SLP_STALL_WAIT_S) +#define PMU_LP_CPU_SLP_STALL_WAIT_V 0x000000FFU +#define PMU_LP_CPU_SLP_STALL_WAIT_S 21 +/** PMU_LP_CPU_SLP_STALL_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_EN (BIT(29)) +#define PMU_LP_CPU_SLP_STALL_EN_M (PMU_LP_CPU_SLP_STALL_EN_V << PMU_LP_CPU_SLP_STALL_EN_S) +#define PMU_LP_CPU_SLP_STALL_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_STALL_EN_S 29 +/** PMU_LP_CPU_SLP_RESET_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_RESET_EN (BIT(30)) +#define PMU_LP_CPU_SLP_RESET_EN_M (PMU_LP_CPU_SLP_RESET_EN_V << PMU_LP_CPU_SLP_RESET_EN_S) +#define PMU_LP_CPU_SLP_RESET_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_RESET_EN_S 30 +/** PMU_LP_CPU_SLP_BYPASS_INTR_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN (BIT(31)) +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_M (PMU_LP_CPU_SLP_BYPASS_INTR_EN_V << PMU_LP_CPU_SLP_BYPASS_INTR_EN_S) +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_S 31 + +/** PMU_LP_CPU_PWR1_REG register + * need_des + */ +#define PMU_LP_CPU_PWR1_REG (DR_REG_PMU_BASE + 0x180) +/** PMU_LP_CPU_WAKEUP_EN : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_EN 0x0000FFFFU +#define PMU_LP_CPU_WAKEUP_EN_M (PMU_LP_CPU_WAKEUP_EN_V << PMU_LP_CPU_WAKEUP_EN_S) +#define PMU_LP_CPU_WAKEUP_EN_V 0x0000FFFFU +#define PMU_LP_CPU_WAKEUP_EN_S 0 +/** PMU_LP_CPU_SLEEP_REQ : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLEEP_REQ (BIT(31)) +#define PMU_LP_CPU_SLEEP_REQ_M (PMU_LP_CPU_SLEEP_REQ_V << PMU_LP_CPU_SLEEP_REQ_S) +#define PMU_LP_CPU_SLEEP_REQ_V 0x00000001U +#define PMU_LP_CPU_SLEEP_REQ_S 31 + +/** PMU_HP_LP_CPU_COMM_REG register + * need_des + */ +#define PMU_HP_LP_CPU_COMM_REG (DR_REG_PMU_BASE + 0x184) +/** PMU_LP_TRIGGER_HP : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_TRIGGER_HP (BIT(30)) +#define PMU_LP_TRIGGER_HP_M (PMU_LP_TRIGGER_HP_V << PMU_LP_TRIGGER_HP_S) +#define PMU_LP_TRIGGER_HP_V 0x00000001U +#define PMU_LP_TRIGGER_HP_S 30 +/** PMU_HP_TRIGGER_LP : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_TRIGGER_LP (BIT(31)) +#define PMU_HP_TRIGGER_LP_M (PMU_HP_TRIGGER_LP_V << PMU_HP_TRIGGER_LP_S) +#define PMU_HP_TRIGGER_LP_V 0x00000001U +#define PMU_HP_TRIGGER_LP_S 31 + +/** PMU_HP_REGULATOR_CFG_REG register + * need_des + */ +#define PMU_HP_REGULATOR_CFG_REG (DR_REG_PMU_BASE + 0x188) +/** PMU_DIG_REGULATOR_EN_CAL : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_DIG_REGULATOR_EN_CAL (BIT(31)) +#define PMU_DIG_REGULATOR_EN_CAL_M (PMU_DIG_REGULATOR_EN_CAL_V << PMU_DIG_REGULATOR_EN_CAL_S) +#define PMU_DIG_REGULATOR_EN_CAL_V 0x00000001U +#define PMU_DIG_REGULATOR_EN_CAL_S 31 + +/** PMU_MAIN_STATE_REG register + * need_des + */ +#define PMU_MAIN_STATE_REG (DR_REG_PMU_BASE + 0x18c) +/** PMU_MAIN_LAST_ST_STATE : RO; bitpos: [17:11]; default: 1; + * need_des + */ +#define PMU_MAIN_LAST_ST_STATE 0x0000007FU +#define PMU_MAIN_LAST_ST_STATE_M (PMU_MAIN_LAST_ST_STATE_V << PMU_MAIN_LAST_ST_STATE_S) +#define PMU_MAIN_LAST_ST_STATE_V 0x0000007FU +#define PMU_MAIN_LAST_ST_STATE_S 11 +/** PMU_MAIN_TAR_ST_STATE : RO; bitpos: [24:18]; default: 4; + * need_des + */ +#define PMU_MAIN_TAR_ST_STATE 0x0000007FU +#define PMU_MAIN_TAR_ST_STATE_M (PMU_MAIN_TAR_ST_STATE_V << PMU_MAIN_TAR_ST_STATE_S) +#define PMU_MAIN_TAR_ST_STATE_V 0x0000007FU +#define PMU_MAIN_TAR_ST_STATE_S 18 +/** PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 4; + * need_des + */ +#define PMU_MAIN_CUR_ST_STATE 0x0000007FU +#define PMU_MAIN_CUR_ST_STATE_M (PMU_MAIN_CUR_ST_STATE_V << PMU_MAIN_CUR_ST_STATE_S) +#define PMU_MAIN_CUR_ST_STATE_V 0x0000007FU +#define PMU_MAIN_CUR_ST_STATE_S 25 + +/** PMU_PWR_STATE_REG register + * need_des + */ +#define PMU_PWR_STATE_REG (DR_REG_PMU_BASE + 0x190) +/** PMU_BACKUP_ST_STATE : RO; bitpos: [17:13]; default: 1; + * need_des + */ +#define PMU_BACKUP_ST_STATE 0x0000001FU +#define PMU_BACKUP_ST_STATE_M (PMU_BACKUP_ST_STATE_V << PMU_BACKUP_ST_STATE_S) +#define PMU_BACKUP_ST_STATE_V 0x0000001FU +#define PMU_BACKUP_ST_STATE_S 13 +/** PMU_LP_PWR_ST_STATE : RO; bitpos: [22:18]; default: 0; + * need_des + */ +#define PMU_LP_PWR_ST_STATE 0x0000001FU +#define PMU_LP_PWR_ST_STATE_M (PMU_LP_PWR_ST_STATE_V << PMU_LP_PWR_ST_STATE_S) +#define PMU_LP_PWR_ST_STATE_V 0x0000001FU +#define PMU_LP_PWR_ST_STATE_S 18 +/** PMU_HP_PWR_ST_STATE : RO; bitpos: [31:23]; default: 1; + * need_des + */ +#define PMU_HP_PWR_ST_STATE 0x000001FFU +#define PMU_HP_PWR_ST_STATE_M (PMU_HP_PWR_ST_STATE_V << PMU_HP_PWR_ST_STATE_S) +#define PMU_HP_PWR_ST_STATE_V 0x000001FFU +#define PMU_HP_PWR_ST_STATE_S 23 + +/** PMU_CLK_STATE0_REG register + * need_des + */ +#define PMU_CLK_STATE0_REG (DR_REG_PMU_BASE + 0x194) +/** PMU_STABLE_XPD_BBPLL_STATE : RO; bitpos: [0]; default: 1; + * need_des + */ +#define PMU_STABLE_XPD_BBPLL_STATE (BIT(0)) +#define PMU_STABLE_XPD_BBPLL_STATE_M (PMU_STABLE_XPD_BBPLL_STATE_V << PMU_STABLE_XPD_BBPLL_STATE_S) +#define PMU_STABLE_XPD_BBPLL_STATE_V 0x00000001U +#define PMU_STABLE_XPD_BBPLL_STATE_S 0 +/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [1]; default: 1; + * need_des + */ +#define PMU_STABLE_XPD_XTAL_STATE (BIT(1)) +#define PMU_STABLE_XPD_XTAL_STATE_M (PMU_STABLE_XPD_XTAL_STATE_V << PMU_STABLE_XPD_XTAL_STATE_S) +#define PMU_STABLE_XPD_XTAL_STATE_V 0x00000001U +#define PMU_STABLE_XPD_XTAL_STATE_S 1 +/** PMU_SYS_CLK_SLP_SEL_STATE : RO; bitpos: [15]; default: 0; + * need_des + */ +#define PMU_SYS_CLK_SLP_SEL_STATE (BIT(15)) +#define PMU_SYS_CLK_SLP_SEL_STATE_M (PMU_SYS_CLK_SLP_SEL_STATE_V << PMU_SYS_CLK_SLP_SEL_STATE_S) +#define PMU_SYS_CLK_SLP_SEL_STATE_V 0x00000001U +#define PMU_SYS_CLK_SLP_SEL_STATE_S 15 +/** PMU_SYS_CLK_SEL_STATE : RO; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_SYS_CLK_SEL_STATE 0x00000003U +#define PMU_SYS_CLK_SEL_STATE_M (PMU_SYS_CLK_SEL_STATE_V << PMU_SYS_CLK_SEL_STATE_S) +#define PMU_SYS_CLK_SEL_STATE_V 0x00000003U +#define PMU_SYS_CLK_SEL_STATE_S 16 +/** PMU_SYS_CLK_NO_DIV_STATE : RO; bitpos: [18]; default: 0; + * need_des + */ +#define PMU_SYS_CLK_NO_DIV_STATE (BIT(18)) +#define PMU_SYS_CLK_NO_DIV_STATE_M (PMU_SYS_CLK_NO_DIV_STATE_V << PMU_SYS_CLK_NO_DIV_STATE_S) +#define PMU_SYS_CLK_NO_DIV_STATE_V 0x00000001U +#define PMU_SYS_CLK_NO_DIV_STATE_S 18 +/** PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [19]; default: 0; + * need_des + */ +#define PMU_ICG_SYS_CLK_EN_STATE (BIT(19)) +#define PMU_ICG_SYS_CLK_EN_STATE_M (PMU_ICG_SYS_CLK_EN_STATE_V << PMU_ICG_SYS_CLK_EN_STATE_S) +#define PMU_ICG_SYS_CLK_EN_STATE_V 0x00000001U +#define PMU_ICG_SYS_CLK_EN_STATE_S 19 +/** PMU_ICG_MODEM_SWITCH_STATE : RO; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_ICG_MODEM_SWITCH_STATE (BIT(20)) +#define PMU_ICG_MODEM_SWITCH_STATE_M (PMU_ICG_MODEM_SWITCH_STATE_V << PMU_ICG_MODEM_SWITCH_STATE_S) +#define PMU_ICG_MODEM_SWITCH_STATE_V 0x00000001U +#define PMU_ICG_MODEM_SWITCH_STATE_S 20 +/** PMU_ICG_MODEM_CODE_STATE : RO; bitpos: [22:21]; default: 0; + * need_des + */ +#define PMU_ICG_MODEM_CODE_STATE 0x00000003U +#define PMU_ICG_MODEM_CODE_STATE_M (PMU_ICG_MODEM_CODE_STATE_V << PMU_ICG_MODEM_CODE_STATE_S) +#define PMU_ICG_MODEM_CODE_STATE_V 0x00000003U +#define PMU_ICG_MODEM_CODE_STATE_S 21 +/** PMU_ICG_SLP_SEL_STATE : RO; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_ICG_SLP_SEL_STATE (BIT(23)) +#define PMU_ICG_SLP_SEL_STATE_M (PMU_ICG_SLP_SEL_STATE_V << PMU_ICG_SLP_SEL_STATE_S) +#define PMU_ICG_SLP_SEL_STATE_V 0x00000001U +#define PMU_ICG_SLP_SEL_STATE_S 23 +/** PMU_ICG_GLOBAL_XTAL_STATE : RO; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_ICG_GLOBAL_XTAL_STATE (BIT(24)) +#define PMU_ICG_GLOBAL_XTAL_STATE_M (PMU_ICG_GLOBAL_XTAL_STATE_V << PMU_ICG_GLOBAL_XTAL_STATE_S) +#define PMU_ICG_GLOBAL_XTAL_STATE_V 0x00000001U +#define PMU_ICG_GLOBAL_XTAL_STATE_S 24 +/** PMU_ICG_GLOBAL_PLL_STATE : RO; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ICG_GLOBAL_PLL_STATE (BIT(25)) +#define PMU_ICG_GLOBAL_PLL_STATE_M (PMU_ICG_GLOBAL_PLL_STATE_V << PMU_ICG_GLOBAL_PLL_STATE_S) +#define PMU_ICG_GLOBAL_PLL_STATE_V 0x00000001U +#define PMU_ICG_GLOBAL_PLL_STATE_S 25 +/** PMU_ANA_I2C_ISO_EN_STATE : RO; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_ANA_I2C_ISO_EN_STATE (BIT(26)) +#define PMU_ANA_I2C_ISO_EN_STATE_M (PMU_ANA_I2C_ISO_EN_STATE_V << PMU_ANA_I2C_ISO_EN_STATE_S) +#define PMU_ANA_I2C_ISO_EN_STATE_V 0x00000001U +#define PMU_ANA_I2C_ISO_EN_STATE_S 26 +/** PMU_ANA_I2C_RETENTION_STATE : RO; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_ANA_I2C_RETENTION_STATE (BIT(27)) +#define PMU_ANA_I2C_RETENTION_STATE_M (PMU_ANA_I2C_RETENTION_STATE_V << PMU_ANA_I2C_RETENTION_STATE_S) +#define PMU_ANA_I2C_RETENTION_STATE_V 0x00000001U +#define PMU_ANA_I2C_RETENTION_STATE_S 27 +/** PMU_ANA_XPD_BB_I2C_STATE : RO; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_ANA_XPD_BB_I2C_STATE (BIT(28)) +#define PMU_ANA_XPD_BB_I2C_STATE_M (PMU_ANA_XPD_BB_I2C_STATE_V << PMU_ANA_XPD_BB_I2C_STATE_S) +#define PMU_ANA_XPD_BB_I2C_STATE_V 0x00000001U +#define PMU_ANA_XPD_BB_I2C_STATE_S 28 +/** PMU_ANA_XPD_BBPLL_I2C_STATE : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_ANA_XPD_BBPLL_I2C_STATE (BIT(29)) +#define PMU_ANA_XPD_BBPLL_I2C_STATE_M (PMU_ANA_XPD_BBPLL_I2C_STATE_V << PMU_ANA_XPD_BBPLL_I2C_STATE_S) +#define PMU_ANA_XPD_BBPLL_I2C_STATE_V 0x00000001U +#define PMU_ANA_XPD_BBPLL_I2C_STATE_S 29 +/** PMU_ANA_XPD_BBPLL_STATE : RO; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ANA_XPD_BBPLL_STATE (BIT(30)) +#define PMU_ANA_XPD_BBPLL_STATE_M (PMU_ANA_XPD_BBPLL_STATE_V << PMU_ANA_XPD_BBPLL_STATE_S) +#define PMU_ANA_XPD_BBPLL_STATE_V 0x00000001U +#define PMU_ANA_XPD_BBPLL_STATE_S 30 +/** PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_ANA_XPD_XTAL_STATE (BIT(31)) +#define PMU_ANA_XPD_XTAL_STATE_M (PMU_ANA_XPD_XTAL_STATE_V << PMU_ANA_XPD_XTAL_STATE_S) +#define PMU_ANA_XPD_XTAL_STATE_V 0x00000001U +#define PMU_ANA_XPD_XTAL_STATE_S 31 + +/** PMU_CLK_STATE1_REG register + * need_des + */ +#define PMU_CLK_STATE1_REG (DR_REG_PMU_BASE + 0x198) +/** PMU_ICG_FUNC_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_ICG_FUNC_EN_STATE 0xFFFFFFFFU +#define PMU_ICG_FUNC_EN_STATE_M (PMU_ICG_FUNC_EN_STATE_V << PMU_ICG_FUNC_EN_STATE_S) +#define PMU_ICG_FUNC_EN_STATE_V 0xFFFFFFFFU +#define PMU_ICG_FUNC_EN_STATE_S 0 + +/** PMU_CLK_STATE2_REG register + * need_des + */ +#define PMU_CLK_STATE2_REG (DR_REG_PMU_BASE + 0x19c) +/** PMU_ICG_APB_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_ICG_APB_EN_STATE 0xFFFFFFFFU +#define PMU_ICG_APB_EN_STATE_M (PMU_ICG_APB_EN_STATE_V << PMU_ICG_APB_EN_STATE_S) +#define PMU_ICG_APB_EN_STATE_V 0xFFFFFFFFU +#define PMU_ICG_APB_EN_STATE_S 0 + +/** PMU_VDD_SPI_STATUS_REG register + * need_des + */ +#define PMU_VDD_SPI_STATUS_REG (DR_REG_PMU_BASE + 0x1a0) +/** PMU_STABLE_VDD_SPI_PWR_DRV : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_STABLE_VDD_SPI_PWR_DRV (BIT(31)) +#define PMU_STABLE_VDD_SPI_PWR_DRV_M (PMU_STABLE_VDD_SPI_PWR_DRV_V << PMU_STABLE_VDD_SPI_PWR_DRV_S) +#define PMU_STABLE_VDD_SPI_PWR_DRV_V 0x00000001U +#define PMU_STABLE_VDD_SPI_PWR_DRV_S 31 + +/** PMU_DATE_REG register + * need_des + */ +#define PMU_DATE_REG (DR_REG_PMU_BASE + 0x3fc) +/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 35676752; + * need_des + */ +#define PMU_PMU_DATE 0x7FFFFFFFU +#define PMU_PMU_DATE_M (PMU_PMU_DATE_V << PMU_PMU_DATE_S) +#define PMU_PMU_DATE_V 0x7FFFFFFFU +#define PMU_PMU_DATE_S 0 +/** PMU_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_CLK_EN (BIT(31)) +#define PMU_CLK_EN_M (PMU_CLK_EN_V << PMU_CLK_EN_S) +#define PMU_CLK_EN_V 0x00000001U +#define PMU_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/pmu_struct.h b/components/soc/esp32c6/include/soc/pmu_struct.h new file mode 100644 index 0000000000..f265b8fd00 --- /dev/null +++ b/components/soc/esp32c6/include/soc/pmu_struct.h @@ -0,0 +1,2818 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of hp_active_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_active_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t hp_active_vdd_spi_pd_en:1; + /** hp_active_hp_mem_dslp : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_active_hp_mem_dslp:1; + /** hp_active_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_mem_pd_en:4; + /** hp_active_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_wifi_pd_en:1; + uint32_t reserved_28:1; + /** hp_active_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_cpu_pd_en:1; + /** hp_active_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_aon_pd_en:1; + /** hp_active_pd_top_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active_pd_top_pd_en:1; + }; + uint32_t val; +} pmu_hp_active_dig_power_reg_t; + +/** Type of hp_active_icg_hp_func register + * need_des + */ +typedef union { + struct { + /** hp_active_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_active_dig_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_active_icg_hp_func_reg_t; + +/** Type of hp_active_icg_hp_apb register + * need_des + */ +typedef union { + struct { + /** hp_active_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_active_dig_icg_apb_en:32; + }; + uint32_t val; +} pmu_hp_active_icg_hp_apb_reg_t; + +/** Type of hp_active_icg_modem register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_active_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_active_dig_icg_modem_code:2; + }; + uint32_t val; +} pmu_hp_active_icg_modem_reg_t; + +/** Type of hp_active_hp_sys_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** hp_active_uart_wakeup_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t hp_active_uart_wakeup_en:1; + /** hp_active_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_active_lp_pad_hold_all:1; + /** hp_active_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_active_hp_pad_hold_all:1; + /** hp_active_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_dig_pad_slp_sel:1; + /** hp_active_dig_pause_wdt : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_dig_pause_wdt:1; + /** hp_active_dig_cpu_stall : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_dig_cpu_stall:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_active_hp_sys_cntl_reg_t; + +/** Type of hp_active_hp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_active_i2c_iso_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_active_i2c_iso_en:1; + /** hp_active_i2c_retention : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_i2c_retention:1; + /** hp_active_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bb_i2c:1; + /** hp_active_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bbpll_i2c:1; + /** hp_active_xpd_bbpll : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bbpll:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_active_hp_ck_power_reg_t; + +/** Type of hp_active_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** hp_active_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bias:1; + /** hp_active_dbg_atten : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t hp_active_dbg_atten:4; + /** hp_active_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_active_pd_cur:1; + /** hp_active_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active_bias_sleep:1; + }; + uint32_t val; +} pmu_hp_active_bias_reg_t; + +/** Type of hp_active_backup register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** hp_sleep2active_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_modem_clk_code:2; + /** hp_modem2active_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_modem_clk_code:2; + uint32_t reserved_8:2; + /** hp_active_retention_mode : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_active_retention_mode:1; + /** hp_sleep2active_retention_en : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_retention_en:1; + /** hp_modem2active_retention_en : R/W; bitpos: [12]; default: 0; + * need_des + */ + uint32_t hp_modem2active_retention_en:1; + uint32_t reserved_13:1; + /** hp_sleep2active_backup_clk_sel : R/W; bitpos: [15:14]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_clk_sel:2; + /** hp_modem2active_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_clk_sel:2; + uint32_t reserved_18:2; + /** hp_sleep2active_backup_mode : R/W; bitpos: [22:20]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_mode:3; + /** hp_modem2active_backup_mode : R/W; bitpos: [25:23]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_mode:3; + uint32_t reserved_26:3; + /** hp_sleep2active_backup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_en:1; + /** hp_modem2active_backup_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_en:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_active_backup_reg_t; + +/** Type of hp_active_backup_clk register + * need_des + */ +typedef union { + struct { + /** hp_active_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_active_backup_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_active_backup_clk_reg_t; + +/** Type of hp_active_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_active_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_active_dig_sys_clk_no_div:1; + /** hp_active_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_icg_sys_clock_en:1; + /** hp_active_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_sys_clk_slp_sel:1; + /** hp_active_icg_slp_sel : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_icg_slp_sel:1; + /** hp_active_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_active_dig_sys_clk_sel:2; + }; + uint32_t val; +} pmu_hp_active_sysclk_reg_t; + +/** Type of hp_active_hp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** lp_dbias_vol : RO; bitpos: [8:4]; default: 24; + * need_des + */ + uint32_t lp_dbias_vol:5; + /** hp_dbias_vol : RO; bitpos: [13:9]; default: 24; + * need_des + */ + uint32_t hp_dbias_vol:5; + /** dig_regulator0_dbias_sel : R/W; bitpos: [14]; default: 1; + * need_des + */ + uint32_t dig_regulator0_dbias_sel:1; + /** dig_dbias_init : WT; bitpos: [15]; default: 0; + * need_des + */ + uint32_t dig_dbias_init:1; + /** hp_active_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_mem_xpd:1; + /** hp_active_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_logic_xpd:1; + /** hp_active_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_xpd:1; + /** hp_active_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_mem_dbias:4; + /** hp_active_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_logic_dbias:4; + /** hp_active_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t hp_active_hp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_active_hp_regulator0_reg_t; + +/** Type of hp_active_hp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** hp_active_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; + * need_des + */ + uint32_t hp_active_hp_regulator_drv_b:24; + }; + uint32_t val; +} pmu_hp_active_hp_regulator1_reg_t; + +/** Type of hp_active_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** hp_active_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t hp_active_xpd_xtal:1; + }; + uint32_t val; +} pmu_hp_active_xtal_reg_t; + +/** Type of hp_modem_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_modem_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t hp_modem_vdd_spi_pd_en:1; + /** hp_modem_hp_mem_dslp : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_mem_dslp:1; + /** hp_modem_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_mem_pd_en:4; + /** hp_modem_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_wifi_pd_en:1; + uint32_t reserved_28:1; + /** hp_modem_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_cpu_pd_en:1; + /** hp_modem_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_aon_pd_en:1; + /** hp_modem_pd_top_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_top_pd_en:1; + }; + uint32_t val; +} pmu_hp_modem_dig_power_reg_t; + +/** Type of hp_modem_icg_hp_func register + * need_des + */ +typedef union { + struct { + /** hp_modem_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_modem_dig_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_modem_icg_hp_func_reg_t; + +/** Type of hp_modem_icg_hp_apb register + * need_des + */ +typedef union { + struct { + /** hp_modem_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_modem_dig_icg_apb_en:32; + }; + uint32_t val; +} pmu_hp_modem_icg_hp_apb_reg_t; + +/** Type of hp_modem_icg_modem register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_modem_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_icg_modem_code:2; + }; + uint32_t val; +} pmu_hp_modem_icg_modem_reg_t; + +/** Type of hp_modem_hp_sys_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** hp_modem_uart_wakeup_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t hp_modem_uart_wakeup_en:1; + /** hp_modem_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_modem_lp_pad_hold_all:1; + /** hp_modem_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_pad_hold_all:1; + /** hp_modem_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_pad_slp_sel:1; + /** hp_modem_dig_pause_wdt : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_pause_wdt:1; + /** hp_modem_dig_cpu_stall : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_cpu_stall:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_modem_hp_sys_cntl_reg_t; + +/** Type of hp_modem_hp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_modem_i2c_iso_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_modem_i2c_iso_en:1; + /** hp_modem_i2c_retention : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_modem_i2c_retention:1; + /** hp_modem_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_bb_i2c:1; + /** hp_modem_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_bbpll_i2c:1; + /** hp_modem_xpd_bbpll : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_bbpll:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_modem_hp_ck_power_reg_t; + +/** Type of hp_modem_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** hp_modem_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_bias:1; + /** hp_modem_dbg_atten : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t hp_modem_dbg_atten:4; + /** hp_modem_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_cur:1; + /** hp_modem_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_modem_bias_sleep:1; + }; + uint32_t val; +} pmu_hp_modem_bias_reg_t; + +/** Type of hp_modem_backup register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** hp_sleep2modem_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_modem_clk_code:2; + uint32_t reserved_6:4; + /** hp_modem_retention_mode : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_modem_retention_mode:1; + /** hp_sleep2modem_retention_en : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_retention_en:1; + uint32_t reserved_12:2; + /** hp_sleep2modem_backup_clk_sel : R/W; bitpos: [15:14]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_clk_sel:2; + uint32_t reserved_16:4; + /** hp_sleep2modem_backup_mode : R/W; bitpos: [22:20]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_mode:3; + uint32_t reserved_23:6; + /** hp_sleep2modem_backup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_modem_backup_reg_t; + +/** Type of hp_modem_backup_clk register + * need_des + */ +typedef union { + struct { + /** hp_modem_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_modem_backup_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_modem_backup_clk_reg_t; + +/** Type of hp_modem_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_modem_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_sys_clk_no_div:1; + /** hp_modem_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_modem_icg_sys_clock_en:1; + /** hp_modem_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_modem_sys_clk_slp_sel:1; + /** hp_modem_icg_slp_sel : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_modem_icg_slp_sel:1; + /** hp_modem_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_sys_clk_sel:2; + }; + uint32_t val; +} pmu_hp_modem_sysclk_reg_t; + +/** Type of hp_modem_hp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** hp_modem_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_mem_xpd:1; + /** hp_modem_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_logic_xpd:1; + /** hp_modem_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; + * need_des + */ + uint32_t hp_modem_hp_regulator_xpd:1; + /** hp_modem_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_mem_dbias:4; + /** hp_modem_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_logic_dbias:4; + /** hp_modem_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t hp_modem_hp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_modem_hp_regulator0_reg_t; + +/** Type of hp_modem_hp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** hp_modem_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_regulator_drv_b:24; + }; + uint32_t val; +} pmu_hp_modem_hp_regulator1_reg_t; + +/** Type of hp_modem_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** hp_modem_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t hp_modem_xpd_xtal:1; + }; + uint32_t val; +} pmu_hp_modem_xtal_reg_t; + +/** Type of hp_sleep_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_sleep_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t hp_sleep_vdd_spi_pd_en:1; + /** hp_sleep_hp_mem_dslp : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_mem_dslp:1; + /** hp_sleep_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_mem_pd_en:4; + /** hp_sleep_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_wifi_pd_en:1; + uint32_t reserved_28:1; + /** hp_sleep_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_cpu_pd_en:1; + /** hp_sleep_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_aon_pd_en:1; + /** hp_sleep_pd_top_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_top_pd_en:1; + }; + uint32_t val; +} pmu_hp_sleep_dig_power_reg_t; + +/** Type of hp_sleep_icg_hp_func register + * need_des + */ +typedef union { + struct { + /** hp_sleep_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_sleep_dig_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_sleep_icg_hp_func_reg_t; + +/** Type of hp_sleep_icg_hp_apb register + * need_des + */ +typedef union { + struct { + /** hp_sleep_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_sleep_dig_icg_apb_en:32; + }; + uint32_t val; +} pmu_hp_sleep_icg_hp_apb_reg_t; + +/** Type of hp_sleep_icg_modem register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_sleep_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_icg_modem_code:2; + }; + uint32_t val; +} pmu_hp_sleep_icg_modem_reg_t; + +/** Type of hp_sleep_hp_sys_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** hp_sleep_uart_wakeup_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t hp_sleep_uart_wakeup_en:1; + /** hp_sleep_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_pad_hold_all:1; + /** hp_sleep_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_pad_hold_all:1; + /** hp_sleep_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_pad_slp_sel:1; + /** hp_sleep_dig_pause_wdt : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_pause_wdt:1; + /** hp_sleep_dig_cpu_stall : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_cpu_stall:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_sleep_hp_sys_cntl_reg_t; + +/** Type of hp_sleep_hp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_sleep_i2c_iso_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_i2c_iso_en:1; + /** hp_sleep_i2c_retention : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_i2c_retention:1; + /** hp_sleep_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bb_i2c:1; + /** hp_sleep_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bbpll_i2c:1; + /** hp_sleep_xpd_bbpll : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bbpll:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_sleep_hp_ck_power_reg_t; + +/** Type of hp_sleep_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** hp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bias:1; + /** hp_sleep_dbg_atten : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t hp_sleep_dbg_atten:4; + /** hp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_cur:1; + /** hp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_bias_sleep:1; + }; + uint32_t val; +} pmu_hp_sleep_bias_reg_t; + +/** Type of hp_sleep_backup register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** hp_modem2sleep_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_modem_clk_code:2; + /** hp_active2sleep_backup_modem_clk_code : R/W; bitpos: [9:8]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_modem_clk_code:2; + /** hp_sleep_retention_mode : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_sleep_retention_mode:1; + uint32_t reserved_11:1; + /** hp_modem2sleep_retention_en : R/W; bitpos: [12]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_retention_en:1; + /** hp_active2sleep_retention_en : R/W; bitpos: [13]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_retention_en:1; + uint32_t reserved_14:2; + /** hp_modem2sleep_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_clk_sel:2; + /** hp_active2sleep_backup_clk_sel : R/W; bitpos: [19:18]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_clk_sel:2; + uint32_t reserved_20:3; + /** hp_modem2sleep_backup_mode : R/W; bitpos: [25:23]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_mode:3; + /** hp_active2sleep_backup_mode : R/W; bitpos: [28:26]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_mode:3; + uint32_t reserved_29:1; + /** hp_modem2sleep_backup_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_en:1; + /** hp_active2sleep_backup_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_en:1; + }; + uint32_t val; +} pmu_hp_sleep_backup_reg_t; + +/** Type of hp_sleep_backup_clk register + * need_des + */ +typedef union { + struct { + /** hp_sleep_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_sleep_backup_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_sleep_backup_clk_reg_t; + +/** Type of hp_sleep_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_sleep_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_sys_clk_no_div:1; + /** hp_sleep_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_icg_sys_clock_en:1; + /** hp_sleep_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_sys_clk_slp_sel:1; + /** hp_sleep_icg_slp_sel : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_icg_slp_sel:1; + /** hp_sleep_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_sys_clk_sel:2; + }; + uint32_t val; +} pmu_hp_sleep_sysclk_reg_t; + +/** Type of hp_sleep_hp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** hp_sleep_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_mem_xpd:1; + /** hp_sleep_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_logic_xpd:1; + /** hp_sleep_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_xpd:1; + /** hp_sleep_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_mem_dbias:4; + /** hp_sleep_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_logic_dbias:4; + /** hp_sleep_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t hp_sleep_hp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_sleep_hp_regulator0_reg_t; + +/** Type of hp_sleep_hp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** hp_sleep_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_regulator_drv_b:24; + }; + uint32_t val; +} pmu_hp_sleep_hp_regulator1_reg_t; + +/** Type of hp_sleep_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** hp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t hp_sleep_xpd_xtal:1; + }; + uint32_t val; +} pmu_hp_sleep_xtal_reg_t; + +/** Type of hp_sleep_lp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; + * need_des + */ + uint32_t hp_sleep_lp_regulator_slp_xpd:1; + /** hp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; + * need_des + */ + uint32_t hp_sleep_lp_regulator_xpd:1; + /** hp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t hp_sleep_lp_regulator_slp_dbias:4; + /** hp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t hp_sleep_lp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_sleep_lp_regulator0_reg_t; + +/** Type of hp_sleep_lp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** hp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_regulator_drv_b:4; + }; + uint32_t val; +} pmu_hp_sleep_lp_regulator1_reg_t; + +/** Type of hp_sleep_lp_dcdc_reserve register + * need_des + */ +typedef union { + struct { + /** hp_sleep_lp_dcdc_reserve : WT; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_dcdc_reserve:32; + }; + uint32_t val; +} pmu_hp_sleep_lp_dcdc_reserve_reg_t; + +/** Type of hp_sleep_lp_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_mem_dslp:1; + /** hp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_lp_peri_pd_en:1; + }; + uint32_t val; +} pmu_hp_sleep_lp_dig_power_reg_t; + +/** Type of hp_sleep_lp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** hp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_xtal32k:1; + /** hp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_rc32k:1; + /** hp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t hp_sleep_xpd_fosc_clk:1; + /** hp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_osc_clk:1; + }; + uint32_t val; +} pmu_hp_sleep_lp_ck_power_reg_t; + +/** Type of lp_sleep_lp_bias_reserve register + * need_des + */ +typedef union { + struct { + /** lp_sleep_lp_bias_reserve : WT; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_sleep_lp_bias_reserve:32; + }; + uint32_t val; +} pmu_lp_sleep_lp_bias_reserve_reg_t; + +/** Type of lp_sleep_lp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** lp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; + * need_des + */ + uint32_t lp_sleep_lp_regulator_slp_xpd:1; + /** lp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; + * need_des + */ + uint32_t lp_sleep_lp_regulator_xpd:1; + /** lp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t lp_sleep_lp_regulator_slp_dbias:4; + /** lp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t lp_sleep_lp_regulator_dbias:5; + }; + uint32_t val; +} pmu_lp_sleep_lp_regulator0_reg_t; + +/** Type of lp_sleep_lp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** lp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; + * need_des + */ + uint32_t lp_sleep_lp_regulator_drv_b:4; + }; + uint32_t val; +} pmu_lp_sleep_lp_regulator1_reg_t; + +/** Type of lp_sleep_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lp_sleep_xpd_xtal:1; + }; + uint32_t val; +} pmu_lp_sleep_xtal_reg_t; + +/** Type of lp_sleep_lp_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** lp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_sleep_lp_mem_dslp:1; + /** lp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_lp_peri_pd_en:1; + }; + uint32_t val; +} pmu_lp_sleep_lp_dig_power_reg_t; + +/** Type of lp_sleep_lp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** lp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_xtal32k:1; + /** lp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_rc32k:1; + /** lp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t lp_sleep_xpd_fosc_clk:1; + /** lp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_osc_clk:1; + }; + uint32_t val; +} pmu_lp_sleep_lp_ck_power_reg_t; + +/** Type of lp_sleep_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** lp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_bias:1; + /** lp_sleep_dbg_atten : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t lp_sleep_dbg_atten:4; + /** lp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_cur:1; + /** lp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_bias_sleep:1; + }; + uint32_t val; +} pmu_lp_sleep_bias_reg_t; + +/** Type of imm_hp_ck_power register + * need_des + */ +typedef union { + struct { + /** tie_low_global_bbpll_icg : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t tie_low_global_bbpll_icg:1; + /** tie_low_global_xtal_icg : WT; bitpos: [1]; default: 0; + * need_des + */ + uint32_t tie_low_global_xtal_icg:1; + /** tie_low_i2c_retention : WT; bitpos: [2]; default: 0; + * need_des + */ + uint32_t tie_low_i2c_retention:1; + /** tie_low_xpd_bb_i2c : WT; bitpos: [3]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_bb_i2c:1; + /** tie_low_xpd_bbpll_i2c : WT; bitpos: [4]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_bbpll_i2c:1; + /** tie_low_xpd_bbpll : WT; bitpos: [5]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_bbpll:1; + /** tie_low_xpd_xtal : WT; bitpos: [6]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_xtal:1; + uint32_t reserved_7:18; + /** tie_high_global_bbpll_icg : WT; bitpos: [25]; default: 0; + * need_des + */ + uint32_t tie_high_global_bbpll_icg:1; + /** tie_high_global_xtal_icg : WT; bitpos: [26]; default: 0; + * need_des + */ + uint32_t tie_high_global_xtal_icg:1; + /** tie_high_i2c_retention : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t tie_high_i2c_retention:1; + /** tie_high_xpd_bb_i2c : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_bb_i2c:1; + /** tie_high_xpd_bbpll_i2c : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_bbpll_i2c:1; + /** tie_high_xpd_bbpll : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_bbpll:1; + /** tie_high_xpd_xtal : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_xtal:1; + }; + uint32_t val; +} pmu_imm_hp_ck_power_reg_t; + +/** Type of imm_sleep_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** update_dig_icg_switch : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t update_dig_icg_switch:1; + /** tie_low_icg_slp_sel : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t tie_low_icg_slp_sel:1; + /** tie_high_icg_slp_sel : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_icg_slp_sel:1; + /** update_dig_sys_clk_sel : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_sys_clk_sel:1; + }; + uint32_t val; +} pmu_imm_sleep_sysclk_reg_t; + +/** Type of imm_hp_func_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_func_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_func_en:1; + }; + uint32_t val; +} pmu_imm_hp_func_icg_reg_t; + +/** Type of imm_hp_apb_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_apb_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_apb_en:1; + }; + uint32_t val; +} pmu_imm_hp_apb_icg_reg_t; + +/** Type of imm_modem_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_modem_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_modem_en:1; + }; + uint32_t val; +} pmu_imm_modem_icg_reg_t; + +/** Type of imm_lp_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tie_low_lp_rootclk_sel : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_low_lp_rootclk_sel:1; + /** tie_high_lp_rootclk_sel : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_high_lp_rootclk_sel:1; + }; + uint32_t val; +} pmu_imm_lp_icg_reg_t; + +/** Type of imm_pad_hold_all register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** tie_high_lp_pad_hold_all : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t tie_high_lp_pad_hold_all:1; + /** tie_low_lp_pad_hold_all : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t tie_low_lp_pad_hold_all:1; + /** tie_high_hp_pad_hold_all : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_hp_pad_hold_all:1; + /** tie_low_hp_pad_hold_all : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_low_hp_pad_hold_all:1; + }; + uint32_t val; +} pmu_imm_pad_hold_all_reg_t; + +/** Type of imm_i2c_iso register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tie_high_i2c_iso_en : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_i2c_iso_en:1; + /** tie_low_i2c_iso_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_low_i2c_iso_en:1; + }; + uint32_t val; +} pmu_imm_i2c_iso_reg_t; + +/** Type of power_wait_timer0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** dg_hp_powerdown_timer : R/W; bitpos: [13:5]; default: 255; + * need_des + */ + uint32_t dg_hp_powerdown_timer:9; + /** dg_hp_powerup_timer : R/W; bitpos: [22:14]; default: 255; + * need_des + */ + uint32_t dg_hp_powerup_timer:9; + /** dg_hp_wait_timer : R/W; bitpos: [31:23]; default: 255; + * need_des + */ + uint32_t dg_hp_wait_timer:9; + }; + uint32_t val; +} pmu_power_wait_timer0_reg_t; + +/** Type of power_wait_timer1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** dg_lp_powerdown_timer : R/W; bitpos: [15:9]; default: 255; + * need_des + */ + uint32_t dg_lp_powerdown_timer:7; + /** dg_lp_powerup_timer : R/W; bitpos: [22:16]; default: 255; + * need_des + */ + uint32_t dg_lp_powerup_timer:7; + /** dg_lp_wait_timer : R/W; bitpos: [31:23]; default: 255; + * need_des + */ + uint32_t dg_lp_wait_timer:9; + }; + uint32_t val; +} pmu_power_wait_timer1_reg_t; + +/** Type of power_pd_top_cntl register + * need_des + */ +typedef union { + struct { + /** force_top_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_top_reset:1; + /** force_top_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_top_iso:1; + /** force_top_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_top_pu:1; + /** force_top_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_top_no_reset:1; + /** force_top_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_top_no_iso:1; + /** force_top_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_top_pd:1; + /** pd_top_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_top_mask:5; + uint32_t reserved_11:16; + /** pd_top_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_top_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_top_cntl_reg_t; + +/** Type of power_pd_hpaon_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_aon_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_aon_reset:1; + /** force_hp_aon_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_aon_iso:1; + /** force_hp_aon_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_aon_pu:1; + /** force_hp_aon_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_aon_no_reset:1; + /** force_hp_aon_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_aon_no_iso:1; + /** force_hp_aon_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_aon_pd:1; + /** pd_hp_aon_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_aon_mask:5; + uint32_t reserved_11:16; + /** pd_hp_aon_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_aon_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpaon_cntl_reg_t; + +/** Type of power_pd_hpcpu_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_cpu_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_reset:1; + /** force_hp_cpu_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_iso:1; + /** force_hp_cpu_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_pu:1; + /** force_hp_cpu_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_no_reset:1; + /** force_hp_cpu_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_no_iso:1; + /** force_hp_cpu_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_pd:1; + /** pd_hp_cpu_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_cpu_mask:5; + uint32_t reserved_11:16; + /** pd_hp_cpu_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_cpu_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpcpu_cntl_reg_t; + +/** Type of power_pd_hpperi_reserve register + * need_des + */ +typedef union { + struct { + /** hp_peri_reserve : WT; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_peri_reserve:32; + }; + uint32_t val; +} pmu_power_pd_hpperi_reserve_reg_t; + +/** Type of power_pd_hpwifi_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_wifi_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_wifi_reset:1; + /** force_hp_wifi_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_wifi_iso:1; + /** force_hp_wifi_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_wifi_pu:1; + /** force_hp_wifi_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_wifi_no_reset:1; + /** force_hp_wifi_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_wifi_no_iso:1; + /** force_hp_wifi_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_wifi_pd:1; + /** pd_hp_wifi_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_wifi_mask:5; + uint32_t reserved_11:16; + /** pd_hp_wifi_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_wifi_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpwifi_cntl_reg_t; + +/** Type of power_pd_lpperi_cntl register + * need_des + */ +typedef union { + struct { + /** force_lp_peri_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_lp_peri_reset:1; + /** force_lp_peri_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_lp_peri_iso:1; + /** force_lp_peri_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_lp_peri_pu:1; + /** force_lp_peri_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_lp_peri_no_reset:1; + /** force_lp_peri_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_lp_peri_no_iso:1; + /** force_lp_peri_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_lp_peri_pd:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} pmu_power_pd_lpperi_cntl_reg_t; + +/** Type of power_pd_mem_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_mem_iso : R/W; bitpos: [3:0]; default: 0; + * need_des + */ + uint32_t force_hp_mem_iso:4; + /** force_hp_mem_pd : R/W; bitpos: [7:4]; default: 0; + * need_des + */ + uint32_t force_hp_mem_pd:4; + uint32_t reserved_8:16; + /** force_hp_mem_no_iso : R/W; bitpos: [27:24]; default: 15; + * need_des + */ + uint32_t force_hp_mem_no_iso:4; + /** force_hp_mem_pu : R/W; bitpos: [31:28]; default: 15; + * need_des + */ + uint32_t force_hp_mem_pu:4; + }; + uint32_t val; +} pmu_power_pd_mem_cntl_reg_t; + +/** Type of power_pd_mem_mask register + * need_des + */ +typedef union { + struct { + /** pd_hp_mem2_pd_mask : R/W; bitpos: [4:0]; default: 0; + * need_des + */ + uint32_t pd_hp_mem2_pd_mask:5; + /** pd_hp_mem1_pd_mask : R/W; bitpos: [9:5]; default: 0; + * need_des + */ + uint32_t pd_hp_mem1_pd_mask:5; + /** pd_hp_mem0_pd_mask : R/W; bitpos: [14:10]; default: 0; + * need_des + */ + uint32_t pd_hp_mem0_pd_mask:5; + uint32_t reserved_15:2; + /** pd_hp_mem2_mask : R/W; bitpos: [21:17]; default: 0; + * need_des + */ + uint32_t pd_hp_mem2_mask:5; + /** pd_hp_mem1_mask : R/W; bitpos: [26:22]; default: 0; + * need_des + */ + uint32_t pd_hp_mem1_mask:5; + /** pd_hp_mem0_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_mem0_mask:5; + }; + uint32_t val; +} pmu_power_pd_mem_mask_reg_t; + +/** Type of power_hp_pad register + * need_des + */ +typedef union { + struct { + /** force_hp_pad_no_iso_all : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_pad_no_iso_all:1; + /** force_hp_pad_iso_all : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_pad_iso_all:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pmu_power_hp_pad_reg_t; + +/** Type of power_vdd_spi_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:18; + /** vdd_spi_pwr_wait : R/W; bitpos: [28:18]; default: 255; + * need_des + */ + uint32_t vdd_spi_pwr_wait:11; + /** vdd_spi_pwr_sw : R/W; bitpos: [30:29]; default: 3; + * need_des + */ + uint32_t vdd_spi_pwr_sw:2; + /** vdd_spi_pwr_sel_sw : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t vdd_spi_pwr_sel_sw:1; + }; + uint32_t val; +} pmu_power_vdd_spi_cntl_reg_t; + +/** Type of power_ck_wait_cntl register + * need_des + */ +typedef union { + struct { + /** wait_xtl_stable : R/W; bitpos: [15:0]; default: 256; + * need_des + */ + uint32_t wait_xtl_stable:16; + /** wait_pll_stable : R/W; bitpos: [31:16]; default: 256; + * need_des + */ + uint32_t wait_pll_stable:16; + }; + uint32_t val; +} pmu_power_ck_wait_cntl_reg_t; + +/** Type of slp_wakeup_cntl0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** sleep_req : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t sleep_req:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl0_reg_t; + +/** Type of slp_wakeup_cntl1 register + * need_des + */ +typedef union { + struct { + /** sleep_reject_ena : R/W; bitpos: [30:0]; default: 0; + * need_des + */ + uint32_t sleep_reject_ena:31; + /** slp_reject_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t slp_reject_en:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl1_reg_t; + +/** Type of slp_wakeup_cntl2 register + * need_des + */ +typedef union { + struct { + /** wakeup_ena : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t wakeup_ena:32; + }; + uint32_t val; +} pmu_slp_wakeup_cntl2_reg_t; + +/** Type of slp_wakeup_cntl3 register + * need_des + */ +typedef union { + struct { + /** lp_min_slp_val : R/W; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t lp_min_slp_val:8; + /** hp_min_slp_val : R/W; bitpos: [15:8]; default: 0; + * need_des + */ + uint32_t hp_min_slp_val:8; + /** sleep_prt_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t sleep_prt_sel:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} pmu_slp_wakeup_cntl3_reg_t; + +/** Type of slp_wakeup_cntl4 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** slp_reject_cause_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t slp_reject_cause_clr:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl4_reg_t; + +/** Type of slp_wakeup_cntl5 register + * need_des + */ +typedef union { + struct { + /** modem_wait_target : R/W; bitpos: [19:0]; default: 128; + * need_des + */ + uint32_t modem_wait_target:20; + uint32_t reserved_20:4; + /** lp_ana_wait_target : R/W; bitpos: [31:24]; default: 1; + * need_des + */ + uint32_t lp_ana_wait_target:8; + }; + uint32_t val; +} pmu_slp_wakeup_cntl5_reg_t; + +/** Type of slp_wakeup_cntl6 register + * need_des + */ +typedef union { + struct { + /** soc_wakeup_wait : R/W; bitpos: [19:0]; default: 128; + * need_des + */ + uint32_t soc_wakeup_wait:20; + uint32_t reserved_20:10; + /** soc_wakeup_wait_cfg : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t soc_wakeup_wait_cfg:2; + }; + uint32_t val; +} pmu_slp_wakeup_cntl6_reg_t; + +/** Type of slp_wakeup_cntl7 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** ana_wait_target : R/W; bitpos: [31:16]; default: 1; + * need_des + */ + uint32_t ana_wait_target:16; + }; + uint32_t val; +} pmu_slp_wakeup_cntl7_reg_t; + +/** Type of slp_wakeup_status0 register + * need_des + */ +typedef union { + struct { + /** wakeup_cause : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t wakeup_cause:32; + }; + uint32_t val; +} pmu_slp_wakeup_status0_reg_t; + +/** Type of slp_wakeup_status1 register + * need_des + */ +typedef union { + struct { + /** reject_cause : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t reject_cause:32; + }; + uint32_t val; +} pmu_slp_wakeup_status1_reg_t; + +/** Type of hp_ck_poweron register + * need_des + */ +typedef union { + struct { + /** i2c_por_wait_target : R/W; bitpos: [7:0]; default: 50; + * need_des + */ + uint32_t i2c_por_wait_target:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} pmu_hp_ck_poweron_reg_t; + +/** Type of hp_ck_cntl register + * need_des + */ +typedef union { + struct { + /** modify_icg_cntl_wait : R/W; bitpos: [7:0]; default: 10; + * need_des + */ + uint32_t modify_icg_cntl_wait:8; + /** switch_icg_cntl_wait : R/W; bitpos: [15:8]; default: 10; + * need_des + */ + uint32_t switch_icg_cntl_wait:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} pmu_hp_ck_cntl_reg_t; + +/** Type of por_status register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** por_done : RO; bitpos: [31]; default: 1; + * need_des + */ + uint32_t por_done:1; + }; + uint32_t val; +} pmu_por_status_reg_t; + +/** Type of rf_pwc register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** perif_i2c_rstb : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t perif_i2c_rstb:1; + /** xpd_perif_i2c : R/W; bitpos: [27]; default: 1; + * need_des + */ + uint32_t xpd_perif_i2c:1; + /** xpd_txrf_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t xpd_txrf_i2c:1; + /** xpd_rfrx_pbus : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t xpd_rfrx_pbus:1; + /** xpd_ckgen_i2c : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t xpd_ckgen_i2c:1; + /** xpd_pll_i2c : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t xpd_pll_i2c:1; + }; + uint32_t val; +} pmu_rf_pwc_reg_t; + +/** Type of backup_cfg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** backup_sys_clk_no_div : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t backup_sys_clk_no_div:1; + }; + uint32_t val; +} pmu_backup_cfg_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_raw:1; + /** sdio_idle_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_raw:1; + /** sw_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_raw:1; + /** soc_sleep_reject_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_raw:1; + /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_raw:1; + }; + uint32_t val; +} pmu_int_raw_reg_t; + +/** Type of hp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_st : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_st:1; + /** sdio_idle_int_st : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_st:1; + /** sw_int_st : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_st:1; + /** soc_sleep_reject_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_st:1; + /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_st:1; + }; + uint32_t val; +} pmu_hp_int_st_reg_t; + +/** Type of hp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_ena : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_ena:1; + /** sdio_idle_int_ena : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_ena:1; + /** sw_int_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_ena:1; + /** soc_sleep_reject_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_ena:1; + /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_ena:1; + }; + uint32_t val; +} pmu_hp_int_ena_reg_t; + +/** Type of hp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_clr : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_clr:1; + /** sdio_idle_int_clr : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_clr:1; + /** sw_int_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_clr:1; + /** soc_sleep_reject_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_clr:1; + /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_clr:1; + }; + uint32_t val; +} pmu_hp_int_clr_reg_t; + +/** Type of lp_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_raw:1; + /** modem_switch_active_end_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_raw:1; + /** sleep_switch_active_end_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_raw:1; + /** sleep_switch_modem_end_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_raw:1; + /** modem_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_raw:1; + /** active_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_raw:1; + /** modem_switch_active_start_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_raw:1; + /** sleep_switch_active_start_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_raw:1; + /** sleep_switch_modem_start_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_raw:1; + /** modem_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_raw:1; + /** active_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_raw:1; + /** hp_sw_trigger_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_raw:1; + }; + uint32_t val; +} pmu_lp_int_raw_reg_t; + +/** Type of lp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_st : RO; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_st:1; + /** modem_switch_active_end_int_st : RO; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_st:1; + /** sleep_switch_active_end_int_st : RO; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_st:1; + /** sleep_switch_modem_end_int_st : RO; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_st:1; + /** modem_switch_sleep_end_int_st : RO; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_st:1; + /** active_switch_sleep_end_int_st : RO; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_st:1; + /** modem_switch_active_start_int_st : RO; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_st:1; + /** sleep_switch_active_start_int_st : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_st:1; + /** sleep_switch_modem_start_int_st : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_st:1; + /** modem_switch_sleep_start_int_st : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_st:1; + /** active_switch_sleep_start_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_st:1; + /** hp_sw_trigger_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_st:1; + }; + uint32_t val; +} pmu_lp_int_st_reg_t; + +/** Type of lp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_ena : R/W; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_ena:1; + /** modem_switch_active_end_int_ena : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_ena:1; + /** sleep_switch_active_end_int_ena : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_ena:1; + /** sleep_switch_modem_end_int_ena : R/W; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_ena:1; + /** modem_switch_sleep_end_int_ena : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_ena:1; + /** active_switch_sleep_end_int_ena : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_ena:1; + /** modem_switch_active_start_int_ena : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_ena:1; + /** sleep_switch_active_start_int_ena : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_ena:1; + /** sleep_switch_modem_start_int_ena : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_ena:1; + /** modem_switch_sleep_start_int_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_ena:1; + /** active_switch_sleep_start_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_ena:1; + /** hp_sw_trigger_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_ena:1; + }; + uint32_t val; +} pmu_lp_int_ena_reg_t; + +/** Type of lp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_clr : WT; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_clr:1; + /** modem_switch_active_end_int_clr : WT; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_clr:1; + /** sleep_switch_active_end_int_clr : WT; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_clr:1; + /** sleep_switch_modem_end_int_clr : WT; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_clr:1; + /** modem_switch_sleep_end_int_clr : WT; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_clr:1; + /** active_switch_sleep_end_int_clr : WT; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_clr:1; + /** modem_switch_active_start_int_clr : WT; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_clr:1; + /** sleep_switch_active_start_int_clr : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_clr:1; + /** sleep_switch_modem_start_int_clr : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_clr:1; + /** modem_switch_sleep_start_int_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_clr:1; + /** active_switch_sleep_start_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_clr:1; + /** hp_sw_trigger_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_clr:1; + }; + uint32_t val; +} pmu_lp_int_clr_reg_t; + +/** Type of lp_cpu_pwr0 register + * need_des + */ +typedef union { + struct { + /** lp_cpu_waiti_rdy : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t lp_cpu_waiti_rdy:1; + /** lp_cpu_stall_rdy : RO; bitpos: [1]; default: 0; + * need_des + */ + uint32_t lp_cpu_stall_rdy:1; + uint32_t reserved_2:16; + /** lp_cpu_force_stall : R/W; bitpos: [18]; default: 0; + * need_des + */ + uint32_t lp_cpu_force_stall:1; + /** lp_cpu_slp_waiti_flag_en : R/W; bitpos: [19]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_waiti_flag_en:1; + /** lp_cpu_slp_stall_flag_en : R/W; bitpos: [20]; default: 1; + * need_des + */ + uint32_t lp_cpu_slp_stall_flag_en:1; + /** lp_cpu_slp_stall_wait : R/W; bitpos: [28:21]; default: 255; + * need_des + */ + uint32_t lp_cpu_slp_stall_wait:8; + /** lp_cpu_slp_stall_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_stall_en:1; + /** lp_cpu_slp_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_reset_en:1; + /** lp_cpu_slp_bypass_intr_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_bypass_intr_en:1; + }; + uint32_t val; +} pmu_lp_cpu_pwr0_reg_t; + +/** Type of lp_cpu_pwr1 register + * need_des + */ +typedef union { + struct { + /** lp_cpu_wakeup_en : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_en:16; + uint32_t reserved_16:15; + /** lp_cpu_sleep_req : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_sleep_req:1; + }; + uint32_t val; +} pmu_lp_cpu_pwr1_reg_t; + +/** Type of hp_lp_cpu_comm register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** lp_trigger_hp : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_trigger_hp:1; + /** hp_trigger_lp : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_trigger_lp:1; + }; + uint32_t val; +} pmu_hp_lp_cpu_comm_reg_t; + +/** Type of hp_regulator_cfg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** dig_regulator_en_cal : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t dig_regulator_en_cal:1; + }; + uint32_t val; +} pmu_hp_regulator_cfg_reg_t; + +/** Type of main_state register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:11; + /** main_last_st_state : RO; bitpos: [17:11]; default: 1; + * need_des + */ + uint32_t main_last_st_state:7; + /** main_tar_st_state : RO; bitpos: [24:18]; default: 4; + * need_des + */ + uint32_t main_tar_st_state:7; + /** main_cur_st_state : RO; bitpos: [31:25]; default: 4; + * need_des + */ + uint32_t main_cur_st_state:7; + }; + uint32_t val; +} pmu_main_state_reg_t; + +/** Type of pwr_state register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:13; + /** backup_st_state : RO; bitpos: [17:13]; default: 1; + * need_des + */ + uint32_t backup_st_state:5; + /** lp_pwr_st_state : RO; bitpos: [22:18]; default: 0; + * need_des + */ + uint32_t lp_pwr_st_state:5; + /** hp_pwr_st_state : RO; bitpos: [31:23]; default: 1; + * need_des + */ + uint32_t hp_pwr_st_state:9; + }; + uint32_t val; +} pmu_pwr_state_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** pmu_date : R/W; bitpos: [30:0]; default: 35676752; + * need_des + */ + uint32_t pmu_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} pmu_date_reg_t; + + +/** Group: status_register */ +/** Type of clk_state0 register + * need_des + */ +typedef union { + struct { + /** stable_xpd_bbpll_state : RO; bitpos: [0]; default: 1; + * need_des + */ + uint32_t stable_xpd_bbpll_state:1; + /** stable_xpd_xtal_state : RO; bitpos: [1]; default: 1; + * need_des + */ + uint32_t stable_xpd_xtal_state:1; + uint32_t reserved_2:13; + /** sys_clk_slp_sel_state : RO; bitpos: [15]; default: 0; + * need_des + */ + uint32_t sys_clk_slp_sel_state:1; + /** sys_clk_sel_state : RO; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t sys_clk_sel_state:2; + /** sys_clk_no_div_state : RO; bitpos: [18]; default: 0; + * need_des + */ + uint32_t sys_clk_no_div_state:1; + /** icg_sys_clk_en_state : RO; bitpos: [19]; default: 0; + * need_des + */ + uint32_t icg_sys_clk_en_state:1; + /** icg_modem_switch_state : RO; bitpos: [20]; default: 0; + * need_des + */ + uint32_t icg_modem_switch_state:1; + /** icg_modem_code_state : RO; bitpos: [22:21]; default: 0; + * need_des + */ + uint32_t icg_modem_code_state:2; + /** icg_slp_sel_state : RO; bitpos: [23]; default: 0; + * need_des + */ + uint32_t icg_slp_sel_state:1; + /** icg_global_xtal_state : RO; bitpos: [24]; default: 0; + * need_des + */ + uint32_t icg_global_xtal_state:1; + /** icg_global_pll_state : RO; bitpos: [25]; default: 0; + * need_des + */ + uint32_t icg_global_pll_state:1; + /** ana_i2c_iso_en_state : RO; bitpos: [26]; default: 0; + * need_des + */ + uint32_t ana_i2c_iso_en_state:1; + /** ana_i2c_retention_state : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_i2c_retention_state:1; + /** ana_xpd_bb_i2c_state : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t ana_xpd_bb_i2c_state:1; + /** ana_xpd_bbpll_i2c_state : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t ana_xpd_bbpll_i2c_state:1; + /** ana_xpd_bbpll_state : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t ana_xpd_bbpll_state:1; + /** ana_xpd_xtal_state : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_xpd_xtal_state:1; + }; + uint32_t val; +} pmu_clk_state0_reg_t; + +/** Type of clk_state1 register + * need_des + */ +typedef union { + struct { + /** icg_func_en_state : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t icg_func_en_state:32; + }; + uint32_t val; +} pmu_clk_state1_reg_t; + +/** Type of clk_state2 register + * need_des + */ +typedef union { + struct { + /** icg_apb_en_state : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t icg_apb_en_state:32; + }; + uint32_t val; +} pmu_clk_state2_reg_t; + +/** Type of vdd_spi_status register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** stable_vdd_spi_pwr_drv : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t stable_vdd_spi_pwr_drv:1; + }; + uint32_t val; +} pmu_vdd_spi_status_reg_t; + + +typedef struct pmu_dev_t { + volatile pmu_hp_active_dig_power_reg_t hp_active_dig_power; + volatile pmu_hp_active_icg_hp_func_reg_t hp_active_icg_hp_func; + volatile pmu_hp_active_icg_hp_apb_reg_t hp_active_icg_hp_apb; + volatile pmu_hp_active_icg_modem_reg_t hp_active_icg_modem; + volatile pmu_hp_active_hp_sys_cntl_reg_t hp_active_hp_sys_cntl; + volatile pmu_hp_active_hp_ck_power_reg_t hp_active_hp_ck_power; + volatile pmu_hp_active_bias_reg_t hp_active_bias; + volatile pmu_hp_active_backup_reg_t hp_active_backup; + volatile pmu_hp_active_backup_clk_reg_t hp_active_backup_clk; + volatile pmu_hp_active_sysclk_reg_t hp_active_sysclk; + volatile pmu_hp_active_hp_regulator0_reg_t hp_active_hp_regulator0; + volatile pmu_hp_active_hp_regulator1_reg_t hp_active_hp_regulator1; + volatile pmu_hp_active_xtal_reg_t hp_active_xtal; + volatile pmu_hp_modem_dig_power_reg_t hp_modem_dig_power; + volatile pmu_hp_modem_icg_hp_func_reg_t hp_modem_icg_hp_func; + volatile pmu_hp_modem_icg_hp_apb_reg_t hp_modem_icg_hp_apb; + volatile pmu_hp_modem_icg_modem_reg_t hp_modem_icg_modem; + volatile pmu_hp_modem_hp_sys_cntl_reg_t hp_modem_hp_sys_cntl; + volatile pmu_hp_modem_hp_ck_power_reg_t hp_modem_hp_ck_power; + volatile pmu_hp_modem_bias_reg_t hp_modem_bias; + volatile pmu_hp_modem_backup_reg_t hp_modem_backup; + volatile pmu_hp_modem_backup_clk_reg_t hp_modem_backup_clk; + volatile pmu_hp_modem_sysclk_reg_t hp_modem_sysclk; + volatile pmu_hp_modem_hp_regulator0_reg_t hp_modem_hp_regulator0; + volatile pmu_hp_modem_hp_regulator1_reg_t hp_modem_hp_regulator1; + volatile pmu_hp_modem_xtal_reg_t hp_modem_xtal; + volatile pmu_hp_sleep_dig_power_reg_t hp_sleep_dig_power; + volatile pmu_hp_sleep_icg_hp_func_reg_t hp_sleep_icg_hp_func; + volatile pmu_hp_sleep_icg_hp_apb_reg_t hp_sleep_icg_hp_apb; + volatile pmu_hp_sleep_icg_modem_reg_t hp_sleep_icg_modem; + volatile pmu_hp_sleep_hp_sys_cntl_reg_t hp_sleep_hp_sys_cntl; + volatile pmu_hp_sleep_hp_ck_power_reg_t hp_sleep_hp_ck_power; + volatile pmu_hp_sleep_bias_reg_t hp_sleep_bias; + volatile pmu_hp_sleep_backup_reg_t hp_sleep_backup; + volatile pmu_hp_sleep_backup_clk_reg_t hp_sleep_backup_clk; + volatile pmu_hp_sleep_sysclk_reg_t hp_sleep_sysclk; + volatile pmu_hp_sleep_hp_regulator0_reg_t hp_sleep_hp_regulator0; + volatile pmu_hp_sleep_hp_regulator1_reg_t hp_sleep_hp_regulator1; + volatile pmu_hp_sleep_xtal_reg_t hp_sleep_xtal; + volatile pmu_hp_sleep_lp_regulator0_reg_t hp_sleep_lp_regulator0; + volatile pmu_hp_sleep_lp_regulator1_reg_t hp_sleep_lp_regulator1; + volatile pmu_hp_sleep_lp_dcdc_reserve_reg_t hp_sleep_lp_dcdc_reserve; + volatile pmu_hp_sleep_lp_dig_power_reg_t hp_sleep_lp_dig_power; + volatile pmu_hp_sleep_lp_ck_power_reg_t hp_sleep_lp_ck_power; + volatile pmu_lp_sleep_lp_bias_reserve_reg_t lp_sleep_lp_bias_reserve; + volatile pmu_lp_sleep_lp_regulator0_reg_t lp_sleep_lp_regulator0; + volatile pmu_lp_sleep_lp_regulator1_reg_t lp_sleep_lp_regulator1; + volatile pmu_lp_sleep_xtal_reg_t lp_sleep_xtal; + volatile pmu_lp_sleep_lp_dig_power_reg_t lp_sleep_lp_dig_power; + volatile pmu_lp_sleep_lp_ck_power_reg_t lp_sleep_lp_ck_power; + volatile pmu_lp_sleep_bias_reg_t lp_sleep_bias; + volatile pmu_imm_hp_ck_power_reg_t imm_hp_ck_power; + volatile pmu_imm_sleep_sysclk_reg_t imm_sleep_sysclk; + volatile pmu_imm_hp_func_icg_reg_t imm_hp_func_icg; + volatile pmu_imm_hp_apb_icg_reg_t imm_hp_apb_icg; + volatile pmu_imm_modem_icg_reg_t imm_modem_icg; + volatile pmu_imm_lp_icg_reg_t imm_lp_icg; + volatile pmu_imm_pad_hold_all_reg_t imm_pad_hold_all; + volatile pmu_imm_i2c_iso_reg_t imm_i2c_iso; + volatile pmu_power_wait_timer0_reg_t power_wait_timer0; + volatile pmu_power_wait_timer1_reg_t power_wait_timer1; + volatile pmu_power_pd_top_cntl_reg_t power_pd_top_cntl; + volatile pmu_power_pd_hpaon_cntl_reg_t power_pd_hpaon_cntl; + volatile pmu_power_pd_hpcpu_cntl_reg_t power_pd_hpcpu_cntl; + volatile pmu_power_pd_hpperi_reserve_reg_t power_pd_hpperi_reserve; + volatile pmu_power_pd_hpwifi_cntl_reg_t power_pd_hpwifi_cntl; + volatile pmu_power_pd_lpperi_cntl_reg_t power_pd_lpperi_cntl; + volatile pmu_power_pd_mem_cntl_reg_t power_pd_mem_cntl; + volatile pmu_power_pd_mem_mask_reg_t power_pd_mem_mask; + volatile pmu_power_hp_pad_reg_t power_hp_pad; + volatile pmu_power_vdd_spi_cntl_reg_t power_vdd_spi_cntl; + volatile pmu_power_ck_wait_cntl_reg_t power_ck_wait_cntl; + volatile pmu_slp_wakeup_cntl0_reg_t slp_wakeup_cntl0; + volatile pmu_slp_wakeup_cntl1_reg_t slp_wakeup_cntl1; + volatile pmu_slp_wakeup_cntl2_reg_t slp_wakeup_cntl2; + volatile pmu_slp_wakeup_cntl3_reg_t slp_wakeup_cntl3; + volatile pmu_slp_wakeup_cntl4_reg_t slp_wakeup_cntl4; + volatile pmu_slp_wakeup_cntl5_reg_t slp_wakeup_cntl5; + volatile pmu_slp_wakeup_cntl6_reg_t slp_wakeup_cntl6; + volatile pmu_slp_wakeup_cntl7_reg_t slp_wakeup_cntl7; + volatile pmu_slp_wakeup_status0_reg_t slp_wakeup_status0; + volatile pmu_slp_wakeup_status1_reg_t slp_wakeup_status1; + volatile pmu_hp_ck_poweron_reg_t hp_ck_poweron; + volatile pmu_hp_ck_cntl_reg_t hp_ck_cntl; + volatile pmu_por_status_reg_t por_status; + volatile pmu_rf_pwc_reg_t rf_pwc; + volatile pmu_backup_cfg_reg_t backup_cfg; + volatile pmu_int_raw_reg_t int_raw; + volatile pmu_hp_int_st_reg_t hp_int_st; + volatile pmu_hp_int_ena_reg_t hp_int_ena; + volatile pmu_hp_int_clr_reg_t hp_int_clr; + volatile pmu_lp_int_raw_reg_t lp_int_raw; + volatile pmu_lp_int_st_reg_t lp_int_st; + volatile pmu_lp_int_ena_reg_t lp_int_ena; + volatile pmu_lp_int_clr_reg_t lp_int_clr; + volatile pmu_lp_cpu_pwr0_reg_t lp_cpu_pwr0; + volatile pmu_lp_cpu_pwr1_reg_t lp_cpu_pwr1; + volatile pmu_hp_lp_cpu_comm_reg_t hp_lp_cpu_comm; + volatile pmu_hp_regulator_cfg_reg_t hp_regulator_cfg; + volatile pmu_main_state_reg_t main_state; + volatile pmu_pwr_state_reg_t pwr_state; + volatile pmu_clk_state0_reg_t clk_state0; + volatile pmu_clk_state1_reg_t clk_state1; + volatile pmu_clk_state2_reg_t clk_state2; + volatile pmu_vdd_spi_status_reg_t vdd_spi_status; + uint32_t reserved_1a4[150]; + volatile pmu_date_reg_t date; +} pmu_dev_t; + +extern pmu_dev_t PMU; + +#ifndef __cplusplus +_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/reg_base.h b/components/soc/esp32c6/include/soc/reg_base.h new file mode 100644 index 0000000000..c0ca354c00 --- /dev/null +++ b/components/soc/esp32c6/include/soc/reg_base.h @@ -0,0 +1,78 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DR_REG_PLIC_MX_BASE 0x20001000 +#define DR_REG_PLIC_UX_BASE 0x20001400 +#define DR_REG_CLINT_M_BASE 0x20001800 +#define DR_REG_CLINT_U_BASE 0x20001C00 + +#define DR_REG_UART_BASE 0x60000000 +#define DR_REG_UART1_BASE 0x60001000 +#define DR_REG_SPI0_BASE 0x60002000 +#define DR_REG_SPI1_BASE 0x60003000 +#define DR_REG_I2C_EXT_BASE 0x60004000 +#define DR_REG_UHCI0_BASE 0x60005000 +#define DR_REG_RMT_BASE 0x60006000 +#define DR_REG_LEDC_BASE 0x60007000 +#define DR_REG_TIMERGROUP0_BASE 0x60008000 +#define DR_REG_TIMERGROUP1_BASE 0x60009000 +#define DR_REG_SYSTIMER_BASE 0x6000A000 +#define DR_REG_TWAI0_BASE 0x6000B000 +#define DR_REG_I2S_BASE 0x6000C000 +#define DR_REG_TWAI1_BASE 0x6000D000 +#define DR_REG_APB_SARADC_BASE 0x6000E000 +#define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000 +#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000 +#define DR_REG_ATOMIC_BASE 0x60011000 +#define DR_REG_PCNT_BASE 0x60012000 +#define DR_REG_SOC_ETM_BASE 0x60013000 +#define DR_REG_MCPWM_BASE 0x60014000 +#define DR_REG_PARL_IO_BASE 0x60015000 +#define DR_REG_HINF_BASE 0x60016000 +#define DR_REG_SLC_BASE 0x60017000 +#define DR_REG_SLCHOST_BASE 0x60018000 +#define DR_REG_PVT_MONITOR_BASE 0x60019000 +#define DR_REG_GDMA_BASE 0x60080000 +#define DR_REG_SPI2_BASE 0x60081000 +#define DR_REG_AES_BASE 0x60088000 +#define DR_REG_SHA_BASE 0x60089000 +#define DR_REG_RSA_BASE 0x6008A000 +#define DR_REG_ECC_MULT_BASE 0x6008B000 +#define DR_REG_DS_BASE 0x6008C000 +#define DR_REG_HMAC_BASE 0x6008D000 +#define DR_REG_IO_MUX_BASE 0x60090000 +#define DR_REG_GPIO_BASE 0x60091000 +#define DR_REG_GPIO_EXT_BASE 0x60091f00 //ESP32C6-TODO +#define DR_REG_MEM_MONITOR_BASE 0x60092000 +#define DR_REG_PAU_BASE 0x60093000 +#define DR_REG_HP_SYSTEM_BASE 0x60095000 +#define DR_REG_PCR_BASE 0x60096000 +#define DR_REG_TEE_BASE 0x60098000 +#define DR_REG_HP_APM_BASE 0x60099000 +#define DR_REG_LP_APM0_BASE 0x60099800 +#define DR_REG_MISC_BASE 0x6009F000 + +#define DR_REG_PMU_BASE 0x600B0000 +#define DR_REG_LP_CLKRST_BASE 0x600B0400 +#define DR_REG_EFUSE_BASE 0x600B0800 +#define DR_REG_LP_TIMER_BASE 0x600B0C00 +#define DR_REG_LP_AON_BASE 0x600B1000 +#define DR_REG_LP_UART_BASE 0x600B1400 +#define DR_REG_LP_I2C_BASE 0x600B1800 +#define DR_REG_LP_WDT_BASE 0x600B1C00 +#define DR_REG_LP_IO_BASE 0x600B2000 +#define DR_REG_LP_I2C_ANA_MST_BASE 0x600B2400 +#define DR_REG_LPPERI_BASE 0x600B2800 +#define DR_REG_LP_ANALOG_PERI_BASE 0x600B2C00 +#define DR_REG_LP_TEE_BASE 0x600B3400 +#define DR_REG_LP_APM_BASE 0x600B3800 +#define DR_REG_OPT_DEBUG_BASE 0x600B3C00 + +#define DR_REG_TRACE_BASE 0x600C0000 +#define DR_REG_ASSIST_DEBUG_BASE 0x600C2000 +#define DR_REG_CPU_BUS_MONITOR_BASE 0x600C2000 +#define DR_REG_INTPRI_BASE 0x600C5000 +#define DR_REG_EXTMEM_BASE 0x600C8000 diff --git a/components/soc/esp32c6/include/soc/regi2c_bbpll.h b/components/soc/esp32c6/include/soc/regi2c_bbpll.h new file mode 100644 index 0000000000..3adc301b9a --- /dev/null +++ b/components/soc/esp32c6/include/soc/regi2c_bbpll.h @@ -0,0 +1,175 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_bbpll.h + * @brief Register definitions for digital PLL (BBPLL) + * + * This file lists register fields of BBPLL, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h, by + * rtc_clk_cpu_freq_set function in rtc_clk.c. + */ + +#define I2C_BBPLL 0x66 +#define I2C_BBPLL_HOSTID 0 + +#define I2C_BBPLL_IR_CAL_DELAY 0 +#define I2C_BBPLL_IR_CAL_DELAY_MSB 3 +#define I2C_BBPLL_IR_CAL_DELAY_LSB 0 + +#define I2C_BBPLL_IR_CAL_CK_DIV 0 +#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7 +#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4 + +#define I2C_BBPLL_IR_CAL_EXT_CAP 1 +#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3 +#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0 + +#define I2C_BBPLL_IR_CAL_ENX_CAP 1 +#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4 +#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4 + +#define I2C_BBPLL_IR_CAL_RSTB 1 +#define I2C_BBPLL_IR_CAL_RSTB_MSB 5 +#define I2C_BBPLL_IR_CAL_RSTB_LSB 5 + +#define I2C_BBPLL_IR_CAL_START 1 +#define I2C_BBPLL_IR_CAL_START_MSB 6 +#define I2C_BBPLL_IR_CAL_START_LSB 6 + +#define I2C_BBPLL_IR_CAL_UNSTOP 1 +#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7 +#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7 + +#define I2C_BBPLL_OC_REF_DIV 2 +#define I2C_BBPLL_OC_REF_DIV_MSB 3 +#define I2C_BBPLL_OC_REF_DIV_LSB 0 + +#define I2C_BBPLL_OC_DCHGP 2 +#define I2C_BBPLL_OC_DCHGP_MSB 6 +#define I2C_BBPLL_OC_DCHGP_LSB 4 + +#define I2C_BBPLL_OC_ENB_FCAL 2 +#define I2C_BBPLL_OC_ENB_FCAL_MSB 7 +#define I2C_BBPLL_OC_ENB_FCAL_LSB 7 + +#define I2C_BBPLL_OC_DIV_7_0 3 +#define I2C_BBPLL_OC_DIV_7_0_MSB 7 +#define I2C_BBPLL_OC_DIV_7_0_LSB 0 + +#define I2C_BBPLL_RSTB_DIV_ADC 4 +#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0 +#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0 + +#define I2C_BBPLL_MODE_HF 4 +#define I2C_BBPLL_MODE_HF_MSB 1 +#define I2C_BBPLL_MODE_HF_LSB 1 + +#define I2C_BBPLL_DIV_ADC 4 +#define I2C_BBPLL_DIV_ADC_MSB 3 +#define I2C_BBPLL_DIV_ADC_LSB 2 + +#define I2C_BBPLL_DIV_DAC 4 +#define I2C_BBPLL_DIV_DAC_MSB 4 +#define I2C_BBPLL_DIV_DAC_LSB 4 + +#define I2C_BBPLL_DIV_CPU 4 +#define I2C_BBPLL_DIV_CPU_MSB 5 +#define I2C_BBPLL_DIV_CPU_LSB 5 + +#define I2C_BBPLL_OC_ENB_VCON 4 +#define I2C_BBPLL_OC_ENB_VCON_MSB 6 +#define I2C_BBPLL_OC_ENB_VCON_LSB 6 + +#define I2C_BBPLL_OC_TSCHGP 4 +#define I2C_BBPLL_OC_TSCHGP_MSB 7 +#define I2C_BBPLL_OC_TSCHGP_LSB 7 + +#define I2C_BBPLL_OC_DR1 5 +#define I2C_BBPLL_OC_DR1_MSB 2 +#define I2C_BBPLL_OC_DR1_LSB 0 + +#define I2C_BBPLL_OC_DR3 5 +#define I2C_BBPLL_OC_DR3_MSB 6 +#define I2C_BBPLL_OC_DR3_LSB 4 + +#define I2C_BBPLL_EN_USB 5 +#define I2C_BBPLL_EN_USB_MSB 7 +#define I2C_BBPLL_EN_USB_LSB 7 + +#define I2C_BBPLL_OC_DCUR 6 +#define I2C_BBPLL_OC_DCUR_MSB 2 +#define I2C_BBPLL_OC_DCUR_LSB 0 + +#define I2C_BBPLL_INC_CUR 6 +#define I2C_BBPLL_INC_CUR_MSB 3 +#define I2C_BBPLL_INC_CUR_LSB 3 + +#define I2C_BBPLL_OC_DHREF_SEL 6 +#define I2C_BBPLL_OC_DHREF_SEL_MSB 5 +#define I2C_BBPLL_OC_DHREF_SEL_LSB 4 + +#define I2C_BBPLL_OC_DLREF_SEL 6 +#define I2C_BBPLL_OC_DLREF_SEL_MSB 7 +#define I2C_BBPLL_OC_DLREF_SEL_LSB 6 + +#define I2C_BBPLL_OR_CAL_CAP 8 +#define I2C_BBPLL_OR_CAL_CAP_MSB 3 +#define I2C_BBPLL_OR_CAL_CAP_LSB 0 + +#define I2C_BBPLL_OR_CAL_UDF 8 +#define I2C_BBPLL_OR_CAL_UDF_MSB 4 +#define I2C_BBPLL_OR_CAL_UDF_LSB 4 + +#define I2C_BBPLL_OR_CAL_OVF 8 +#define I2C_BBPLL_OR_CAL_OVF_MSB 5 +#define I2C_BBPLL_OR_CAL_OVF_LSB 5 + +#define I2C_BBPLL_OR_CAL_END 8 +#define I2C_BBPLL_OR_CAL_END_MSB 6 +#define I2C_BBPLL_OR_CAL_END_LSB 6 + +#define I2C_BBPLL_OR_LOCK 8 +#define I2C_BBPLL_OR_LOCK_MSB 7 +#define I2C_BBPLL_OR_LOCK_LSB 7 + +#define I2C_BBPLL_OC_VCO_DBIAS 9 +#define I2C_BBPLL_OC_VCO_DBIAS_MSB 1 +#define I2C_BBPLL_OC_VCO_DBIAS_LSB 0 + +#define I2C_BBPLL_BBADC_DELAY2 9 +#define I2C_BBPLL_BBADC_DELAY2_MSB 3 +#define I2C_BBPLL_BBADC_DELAY2_LSB 2 + +#define I2C_BBPLL_BBADC_DVDD 9 +#define I2C_BBPLL_BBADC_DVDD_MSB 5 +#define I2C_BBPLL_BBADC_DVDD_LSB 4 + +#define I2C_BBPLL_BBADC_DREF 9 +#define I2C_BBPLL_BBADC_DREF_MSB 7 +#define I2C_BBPLL_BBADC_DREF_LSB 6 + +#define I2C_BBPLL_BBADC_DCUR 10 +#define I2C_BBPLL_BBADC_DCUR_MSB 1 +#define I2C_BBPLL_BBADC_DCUR_LSB 0 + +#define I2C_BBPLL_BBADC_INPUT_SHORT 10 +#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2 +#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2 + +#define I2C_BBPLL_ENT_PLL 10 +#define I2C_BBPLL_ENT_PLL_MSB 3 +#define I2C_BBPLL_ENT_PLL_LSB 3 + +#define I2C_BBPLL_DTEST 10 +#define I2C_BBPLL_DTEST_MSB 5 +#define I2C_BBPLL_DTEST_LSB 4 + +#define I2C_BBPLL_ENT_ADC 10 +#define I2C_BBPLL_ENT_ADC_MSB 7 +#define I2C_BBPLL_ENT_ADC_LSB 6 diff --git a/components/soc/esp32c6/include/soc/regi2c_bias.h b/components/soc/esp32c6/include/soc/regi2c_bias.h new file mode 100644 index 0000000000..512cb54989 --- /dev/null +++ b/components/soc/esp32c6/include/soc/regi2c_bias.h @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_bias.h + * @brief Register definitions for bias + * + * This file lists register fields of BIAS. These definitions are used via macros defined in regi2c_ctrl.h, by + * bootloader_hardware_init function in bootloader_esp32c3.c. + */ + +#define I2C_BIAS 0X6A +#define I2C_BIAS_HOSTID 0 + +#define I2C_BIAS_DREG_1P1_PVT 1 +#define I2C_BIAS_DREG_1P1_PVT_MSB 3 +#define I2C_BIAS_DREG_1P1_PVT_LSB 0 diff --git a/components/soc/esp32c6/include/soc/regi2c_brownout.h b/components/soc/esp32c6/include/soc/regi2c_brownout.h new file mode 100644 index 0000000000..635ad74782 --- /dev/null +++ b/components/soc/esp32c6/include/soc/regi2c_brownout.h @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_brownout.h + * @brief Register definitions for brownout detector + * + * This file lists register fields of the brownout detector, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h. + */ + +#define I2C_BOD 0x61 +#define I2C_BOD_HOSTID 0 + +#define I2C_BOD_THRESHOLD 0x5 +#define I2C_BOD_THRESHOLD_MSB 2 +#define I2C_BOD_THRESHOLD_LSB 0 diff --git a/components/soc/esp32c6/include/soc/regi2c_defs.h b/components/soc/esp32c6/include/soc/regi2c_defs.h new file mode 100644 index 0000000000..9ff42a0da6 --- /dev/null +++ b/components/soc/esp32c6/include/soc/regi2c_defs.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_bit_defs.h" + +/* Analog function control register */ +#define I2C_MST_ANA_CONF0_REG 0x6000E040 +#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) +#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) + +#define ANA_CONFIG_REG 0x6000E044 +#define ANA_CONFIG_S (8) +#define ANA_CONFIG_M (0x3FF) + +#define ANA_I2C_SAR_FORCE_PD BIT(18) +#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */ + + +#define ANA_CONFIG2_REG 0x6000E048 +#define ANA_CONFIG2_M BIT(18) + +#define ANA_I2C_SAR_FORCE_PU BIT(16) + +/** + * Restore regi2c analog calibration related configuration registers. + * This is a workaround, and is fixed on later chips + */ +#define REGI2C_ANA_CALI_PD_WORKAROUND 1 +#define REGI2C_ANA_CALI_BYTE_NUM 8 diff --git a/components/soc/esp32c6/include/soc/regi2c_lp_bias.h b/components/soc/esp32c6/include/soc/regi2c_lp_bias.h new file mode 100644 index 0000000000..4c69ac7d26 --- /dev/null +++ b/components/soc/esp32c6/include/soc/regi2c_lp_bias.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_lp_bias.h + * @brief Register definitions for analog to calibrate o_code for getting a more precise voltage. + * + * This file lists register fields of low power dbais, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h, by + * rtc_init function in rtc_init.c. + */ + +#define I2C_ULP 0x61 +#define I2C_ULP_HOSTID 0 + +#define I2C_ULP_IR_RESETB 0 +#define I2C_ULP_IR_RESETB_MSB 0 +#define I2C_ULP_IR_RESETB_LSB 0 + +#define I2C_ULP_IR_FORCE_XPD_CK 0 +#define I2C_ULP_IR_FORCE_XPD_CK_MSB 2 +#define I2C_ULP_IR_FORCE_XPD_CK_LSB 2 + +#define I2C_ULP_IR_FORCE_XPD_IPH 0 +#define I2C_ULP_IR_FORCE_XPD_IPH_MSB 4 +#define I2C_ULP_IR_FORCE_XPD_IPH_LSB 4 + +#define I2C_ULP_IR_DISABLE_WATCHDOG_CK 0 +#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_MSB 6 +#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_LSB 6 + +#define I2C_ULP_O_DONE_FLAG 3 +#define I2C_ULP_O_DONE_FLAG_MSB 0 +#define I2C_ULP_O_DONE_FLAG_LSB 0 + +#define I2C_ULP_BG_O_DONE_FLAG 3 +#define I2C_ULP_BG_O_DONE_FLAG_MSB 3 +#define I2C_ULP_BG_O_DONE_FLAG_LSB 3 + +#define I2C_ULP_OCODE 4 +#define I2C_ULP_OCODE_MSB 7 +#define I2C_ULP_OCODE_LSB 0 + +#define I2C_ULP_IR_FORCE_CODE 5 +#define I2C_ULP_IR_FORCE_CODE_MSB 6 +#define I2C_ULP_IR_FORCE_CODE_LSB 6 + +#define I2C_ULP_EXT_CODE 6 +#define I2C_ULP_EXT_CODE_MSB 7 +#define I2C_ULP_EXT_CODE_LSB 0 diff --git a/components/soc/esp32c6/include/soc/regi2c_saradc.h b/components/soc/esp32c6/include/soc/regi2c_saradc.h new file mode 100644 index 0000000000..c7137f3bb0 --- /dev/null +++ b/components/soc/esp32c6/include/soc/regi2c_saradc.h @@ -0,0 +1,79 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_saradc.h + * @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC. + * + * This file lists register fields of SAR, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h, by + * function in adc_ll.h. + */ + +#define I2C_SAR_ADC 0X69 +#define I2C_SAR_ADC_HOSTID 0 + +#define ADC_SAR1_ENCAL_GND_ADDR 0x7 +#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5 +#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5 + +#define ADC_SAR2_ENCAL_GND_ADDR 0x7 +#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7 +#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7 + +#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1 +#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3 +#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0 + +#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0 +#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7 +#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0 + +#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4 +#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3 +#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0 + +#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3 +#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7 +#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0 + +#define ADC_SAR1_DREF_ADDR 0x2 +#define ADC_SAR1_DREF_ADDR_MSB 0x6 +#define ADC_SAR1_DREF_ADDR_LSB 0x4 + +#define ADC_SAR2_DREF_ADDR 0x5 +#define ADC_SAR2_DREF_ADDR_MSB 0x6 +#define ADC_SAR2_DREF_ADDR_LSB 0x4 + +#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2 +#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2 +#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0 + +#define ADC_SARADC_DTEST_RTC_ADDR 0x7 +#define ADC_SARADC_DTEST_RTC_ADDR_MSB 1 +#define ADC_SARADC_DTEST_RTC_ADDR_LSB 0 + +#define ADC_SARADC_ENT_TSENS_ADDR 0x7 +#define ADC_SARADC_ENT_TSENS_ADDR_MSB 2 +#define ADC_SARADC_ENT_TSENS_ADDR_LSB 2 + +#define ADC_SARADC_ENT_RTC_ADDR 0x7 +#define ADC_SARADC_ENT_RTC_ADDR_MSB 3 +#define ADC_SARADC_ENT_RTC_ADDR_LSB 3 + +#define ADC_SARADC1_ENCAL_REF_ADDR 0x7 +#define ADC_SARADC1_ENCAL_REF_ADDR_MSB 4 +#define ADC_SARADC1_ENCAL_REF_ADDR_LSB 4 + +#define ADC_SARADC2_ENCAL_REF_ADDR 0x7 +#define ADC_SARADC2_ENCAL_REF_ADDR_MSB 6 +#define ADC_SARADC2_ENCAL_REF_ADDR_LSB 6 + +#define I2C_SARADC_TSENS_DAC 0x6 +#define I2C_SARADC_TSENS_DAC_MSB 3 +#define I2C_SARADC_TSENS_DAC_LSB 0 diff --git a/components/soc/esp32c6/include/soc/reset_reasons.h b/components/soc/esp32c6/include/soc/reset_reasons.h new file mode 100644 index 0000000000..bd9831d5dd --- /dev/null +++ b/components/soc/esp32c6/include/soc/reset_reasons.h @@ -0,0 +1,56 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +//+-----------------------------------------------Terminology---------------------------------------------+ +//| | +//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector | +//| | +//| Core Reset: Reset the whole digital system except RTC sub-system | +//| | +//| System Reset: Reset the whole digital system, including RTC sub-system | +//| | +//| Chip Reset: Reset the whole chip, including the analog part | +//| | +//+-------------------------------------------------------------------------------------------------------+ + +#ifdef __cplusplus +extern "C" { +#endif + + +// TODO: IDF-5719 +/** + * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason} + * @note refer to TRM: chapter + */ +typedef enum { + RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset + RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip + RESET_REASON_CORE_SW = 0x03, // Software resets the digital core (hp system) by LP_AON_HPSYS_SW_RESET + RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core (hp system) + RESET_REASON_CORE_SDIO = 0x06, // SDIO module resets the digital core (hp system) + RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core (hp system) + RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core (hp system) + RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core (hp system) + RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0 + RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by LP_AON_CPU_CORE0_SW_RESET + RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0 + RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core + RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module + RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0 + RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module + RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core (hp system) + RESET_REASON_CORE_USB_UART = 0x15, // USB UART resets the digital core (hp system) + RESET_REASON_CORE_USB_JTAG = 0x16, // USB JTAG resets the digital core (hp system) + RESET_REASON_CPU0_JTAG = 0x18, // JTAG resets the CPU 0 +} soc_reset_reason_t; + + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/rmt_reg.h b/components/soc/esp32c6/include/soc/rmt_reg.h new file mode 100644 index 0000000000..0bc75f17fc --- /dev/null +++ b/components/soc/esp32c6/include/soc/rmt_reg.h @@ -0,0 +1,1519 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** RMT_CH0DATA_REG register + * The read and write data register for CHANNEL0 by apb fifo access. + */ +#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0) +/** RMT_CH0DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel 0 via APB FIFO. + */ +#define RMT_CH0DATA 0xFFFFFFFFU +#define RMT_CH0DATA_M (RMT_CH0DATA_V << RMT_CH0DATA_S) +#define RMT_CH0DATA_V 0xFFFFFFFFU +#define RMT_CH0DATA_S 0 + +/** RMT_CH1DATA_REG register + * The read and write data register for CHANNEL1 by apb fifo access. + */ +#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x4) +/** RMT_CH1DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel 1 via APB FIFO. + */ +#define RMT_CH1DATA 0xFFFFFFFFU +#define RMT_CH1DATA_M (RMT_CH1DATA_V << RMT_CH1DATA_S) +#define RMT_CH1DATA_V 0xFFFFFFFFU +#define RMT_CH1DATA_S 0 + +/** RMT_CH2DATA_REG register + * The read and write data register for CHANNEL2 by apb fifo access. + */ +#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x8) +/** RMT_CH2DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel 2 via APB FIFO. + */ +#define RMT_CH2DATA 0xFFFFFFFFU +#define RMT_CH2DATA_M (RMT_CH2DATA_V << RMT_CH2DATA_S) +#define RMT_CH2DATA_V 0xFFFFFFFFU +#define RMT_CH2DATA_S 0 + +/** RMT_CH3DATA_REG register + * The read and write data register for CHANNEL3 by apb fifo access. + */ +#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0xc) +/** RMT_CH3DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel 3 via APB FIFO. + */ +#define RMT_CH3DATA 0xFFFFFFFFU +#define RMT_CH3DATA_M (RMT_CH3DATA_V << RMT_CH3DATA_S) +#define RMT_CH3DATA_V 0xFFFFFFFFU +#define RMT_CH3DATA_S 0 + +/** RMT_CH0CONF0_REG register + * Channel 0 configure register 0 + */ +#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x10) +/** RMT_TX_START_CH0 : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNEL0. + */ +#define RMT_TX_START_CH0 (BIT(0)) +#define RMT_TX_START_CH0_M (RMT_TX_START_CH0_V << RMT_TX_START_CH0_S) +#define RMT_TX_START_CH0_V 0x00000001U +#define RMT_TX_START_CH0_S 0 +/** RMT_MEM_RD_RST_CH0 : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNEL0 by accessing transmitter. + */ +#define RMT_MEM_RD_RST_CH0 (BIT(1)) +#define RMT_MEM_RD_RST_CH0_M (RMT_MEM_RD_RST_CH0_V << RMT_MEM_RD_RST_CH0_S) +#define RMT_MEM_RD_RST_CH0_V 0x00000001U +#define RMT_MEM_RD_RST_CH0_S 1 +/** RMT_APB_MEM_RST_CH0 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL0 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH0 (BIT(2)) +#define RMT_APB_MEM_RST_CH0_M (RMT_APB_MEM_RST_CH0_V << RMT_APB_MEM_RST_CH0_S) +#define RMT_APB_MEM_RST_CH0_V 0x00000001U +#define RMT_APB_MEM_RST_CH0_S 2 +/** RMT_TX_CONTI_MODE_CH0 : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNEL0. + */ +#define RMT_TX_CONTI_MODE_CH0 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH0_M (RMT_TX_CONTI_MODE_CH0_V << RMT_TX_CONTI_MODE_CH0_S) +#define RMT_TX_CONTI_MODE_CH0_V 0x00000001U +#define RMT_TX_CONTI_MODE_CH0_S 3 +/** RMT_MEM_TX_WRAP_EN_CH0 : R/W; bitpos: [4]; default: 0; + * This is the channel 0 enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ +#define RMT_MEM_TX_WRAP_EN_CH0 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH0_M (RMT_MEM_TX_WRAP_EN_CH0_V << RMT_MEM_TX_WRAP_EN_CH0_S) +#define RMT_MEM_TX_WRAP_EN_CH0_V 0x00000001U +#define RMT_MEM_TX_WRAP_EN_CH0_S 4 +/** RMT_IDLE_OUT_LV_CH0 : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNEL0 when the latter is in + * IDLE state. + */ +#define RMT_IDLE_OUT_LV_CH0 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH0_M (RMT_IDLE_OUT_LV_CH0_V << RMT_IDLE_OUT_LV_CH0_S) +#define RMT_IDLE_OUT_LV_CH0_V 0x00000001U +#define RMT_IDLE_OUT_LV_CH0_S 5 +/** RMT_IDLE_OUT_EN_CH0 : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNEL0 in IDLE state. + */ +#define RMT_IDLE_OUT_EN_CH0 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH0_M (RMT_IDLE_OUT_EN_CH0_V << RMT_IDLE_OUT_EN_CH0_S) +#define RMT_IDLE_OUT_EN_CH0_V 0x00000001U +#define RMT_IDLE_OUT_EN_CH0_S 6 +/** RMT_TX_STOP_CH0 : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNEL0 sending data out. + */ +#define RMT_TX_STOP_CH0 (BIT(7)) +#define RMT_TX_STOP_CH0_M (RMT_TX_STOP_CH0_V << RMT_TX_STOP_CH0_S) +#define RMT_TX_STOP_CH0_V 0x00000001U +#define RMT_TX_STOP_CH0_S 7 +/** RMT_DIV_CNT_CH0 : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNEL0. + */ +#define RMT_DIV_CNT_CH0 0x000000FFU +#define RMT_DIV_CNT_CH0_M (RMT_DIV_CNT_CH0_V << RMT_DIV_CNT_CH0_S) +#define RMT_DIV_CNT_CH0_V 0x000000FFU +#define RMT_DIV_CNT_CH0_S 8 +/** RMT_MEM_SIZE_CH0 : R/W; bitpos: [18:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL0. + */ +#define RMT_MEM_SIZE_CH0 0x00000007U +#define RMT_MEM_SIZE_CH0_M (RMT_MEM_SIZE_CH0_V << RMT_MEM_SIZE_CH0_S) +#define RMT_MEM_SIZE_CH0_V 0x00000007U +#define RMT_MEM_SIZE_CH0_S 16 +/** RMT_CARRIER_EFF_EN_CH0 : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNEL0. 0: Add carrier modulation on the output signal at all state for CHANNEL0. + * Only valid when RMT_CARRIER_EN_CH0 is 1. + */ +#define RMT_CARRIER_EFF_EN_CH0 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH0_M (RMT_CARRIER_EFF_EN_CH0_V << RMT_CARRIER_EFF_EN_CH0_S) +#define RMT_CARRIER_EFF_EN_CH0_V 0x00000001U +#define RMT_CARRIER_EFF_EN_CH0_S 20 +/** RMT_CARRIER_EN_CH0 : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL0. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH0 (BIT(21)) +#define RMT_CARRIER_EN_CH0_M (RMT_CARRIER_EN_CH0_V << RMT_CARRIER_EN_CH0_S) +#define RMT_CARRIER_EN_CH0_V 0x00000001U +#define RMT_CARRIER_EN_CH0_S 21 +/** RMT_CARRIER_OUT_LV_CH0 : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL0. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH0 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH0_M (RMT_CARRIER_OUT_LV_CH0_V << RMT_CARRIER_OUT_LV_CH0_S) +#define RMT_CARRIER_OUT_LV_CH0_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH0_S 22 +/** RMT_AFIFO_RST_CH0 : WT; bitpos: [23]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_CH0 (BIT(23)) +#define RMT_AFIFO_RST_CH0_M (RMT_AFIFO_RST_CH0_V << RMT_AFIFO_RST_CH0_S) +#define RMT_AFIFO_RST_CH0_V 0x00000001U +#define RMT_AFIFO_RST_CH0_S 23 +/** RMT_CONF_UPDATE_CH0 : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNEL0 + */ +#define RMT_CONF_UPDATE_CH0 (BIT(24)) +#define RMT_CONF_UPDATE_CH0_M (RMT_CONF_UPDATE_CH0_V << RMT_CONF_UPDATE_CH0_S) +#define RMT_CONF_UPDATE_CH0_V 0x00000001U +#define RMT_CONF_UPDATE_CH0_S 24 + +/** RMT_CH1CONF0_REG register + * Channel 1 configure register 0 + */ +#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x14) +/** RMT_TX_START_CH1 : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNEL1. + */ +#define RMT_TX_START_CH1 (BIT(0)) +#define RMT_TX_START_CH1_M (RMT_TX_START_CH1_V << RMT_TX_START_CH1_S) +#define RMT_TX_START_CH1_V 0x00000001U +#define RMT_TX_START_CH1_S 0 +/** RMT_MEM_RD_RST_CH1 : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNEL1 by accessing transmitter. + */ +#define RMT_MEM_RD_RST_CH1 (BIT(1)) +#define RMT_MEM_RD_RST_CH1_M (RMT_MEM_RD_RST_CH1_V << RMT_MEM_RD_RST_CH1_S) +#define RMT_MEM_RD_RST_CH1_V 0x00000001U +#define RMT_MEM_RD_RST_CH1_S 1 +/** RMT_APB_MEM_RST_CH1 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL1 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH1 (BIT(2)) +#define RMT_APB_MEM_RST_CH1_M (RMT_APB_MEM_RST_CH1_V << RMT_APB_MEM_RST_CH1_S) +#define RMT_APB_MEM_RST_CH1_V 0x00000001U +#define RMT_APB_MEM_RST_CH1_S 2 +/** RMT_TX_CONTI_MODE_CH1 : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNEL1. + */ +#define RMT_TX_CONTI_MODE_CH1 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH1_M (RMT_TX_CONTI_MODE_CH1_V << RMT_TX_CONTI_MODE_CH1_S) +#define RMT_TX_CONTI_MODE_CH1_V 0x00000001U +#define RMT_TX_CONTI_MODE_CH1_S 3 +/** RMT_MEM_TX_WRAP_EN_CH1 : R/W; bitpos: [4]; default: 0; + * This is the channel 1 enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ +#define RMT_MEM_TX_WRAP_EN_CH1 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH1_M (RMT_MEM_TX_WRAP_EN_CH1_V << RMT_MEM_TX_WRAP_EN_CH1_S) +#define RMT_MEM_TX_WRAP_EN_CH1_V 0x00000001U +#define RMT_MEM_TX_WRAP_EN_CH1_S 4 +/** RMT_IDLE_OUT_LV_CH1 : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNEL1 when the latter is in + * IDLE state. + */ +#define RMT_IDLE_OUT_LV_CH1 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH1_M (RMT_IDLE_OUT_LV_CH1_V << RMT_IDLE_OUT_LV_CH1_S) +#define RMT_IDLE_OUT_LV_CH1_V 0x00000001U +#define RMT_IDLE_OUT_LV_CH1_S 5 +/** RMT_IDLE_OUT_EN_CH1 : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNEL1 in IDLE state. + */ +#define RMT_IDLE_OUT_EN_CH1 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH1_M (RMT_IDLE_OUT_EN_CH1_V << RMT_IDLE_OUT_EN_CH1_S) +#define RMT_IDLE_OUT_EN_CH1_V 0x00000001U +#define RMT_IDLE_OUT_EN_CH1_S 6 +/** RMT_TX_STOP_CH1 : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNEL1 sending data out. + */ +#define RMT_TX_STOP_CH1 (BIT(7)) +#define RMT_TX_STOP_CH1_M (RMT_TX_STOP_CH1_V << RMT_TX_STOP_CH1_S) +#define RMT_TX_STOP_CH1_V 0x00000001U +#define RMT_TX_STOP_CH1_S 7 +/** RMT_DIV_CNT_CH1 : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNEL1. + */ +#define RMT_DIV_CNT_CH1 0x000000FFU +#define RMT_DIV_CNT_CH1_M (RMT_DIV_CNT_CH1_V << RMT_DIV_CNT_CH1_S) +#define RMT_DIV_CNT_CH1_V 0x000000FFU +#define RMT_DIV_CNT_CH1_S 8 +/** RMT_MEM_SIZE_CH1 : R/W; bitpos: [18:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL1. + */ +#define RMT_MEM_SIZE_CH1 0x00000007U +#define RMT_MEM_SIZE_CH1_M (RMT_MEM_SIZE_CH1_V << RMT_MEM_SIZE_CH1_S) +#define RMT_MEM_SIZE_CH1_V 0x00000007U +#define RMT_MEM_SIZE_CH1_S 16 +/** RMT_CARRIER_EFF_EN_CH1 : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNEL1. 0: Add carrier modulation on the output signal at all state for CHANNEL1. + * Only valid when RMT_CARRIER_EN_CH1 is 1. + */ +#define RMT_CARRIER_EFF_EN_CH1 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH1_M (RMT_CARRIER_EFF_EN_CH1_V << RMT_CARRIER_EFF_EN_CH1_S) +#define RMT_CARRIER_EFF_EN_CH1_V 0x00000001U +#define RMT_CARRIER_EFF_EN_CH1_S 20 +/** RMT_CARRIER_EN_CH1 : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL1. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH1 (BIT(21)) +#define RMT_CARRIER_EN_CH1_M (RMT_CARRIER_EN_CH1_V << RMT_CARRIER_EN_CH1_S) +#define RMT_CARRIER_EN_CH1_V 0x00000001U +#define RMT_CARRIER_EN_CH1_S 21 +/** RMT_CARRIER_OUT_LV_CH1 : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL1. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH1 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH1_M (RMT_CARRIER_OUT_LV_CH1_V << RMT_CARRIER_OUT_LV_CH1_S) +#define RMT_CARRIER_OUT_LV_CH1_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH1_S 22 +/** RMT_AFIFO_RST_CH1 : WT; bitpos: [23]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_CH1 (BIT(23)) +#define RMT_AFIFO_RST_CH1_M (RMT_AFIFO_RST_CH1_V << RMT_AFIFO_RST_CH1_S) +#define RMT_AFIFO_RST_CH1_V 0x00000001U +#define RMT_AFIFO_RST_CH1_S 23 +/** RMT_CONF_UPDATE_CH1 : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNEL1 + */ +#define RMT_CONF_UPDATE_CH1 (BIT(24)) +#define RMT_CONF_UPDATE_CH1_M (RMT_CONF_UPDATE_CH1_V << RMT_CONF_UPDATE_CH1_S) +#define RMT_CONF_UPDATE_CH1_V 0x00000001U +#define RMT_CONF_UPDATE_CH1_S 24 + +/** RMT_CH2CONF0_REG register + * Channel 2 configure register 0 + */ +#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x18) +/** RMT_DIV_CNT_CH2 : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNEL2. + */ +#define RMT_DIV_CNT_CH2 0x000000FFU +#define RMT_DIV_CNT_CH2_M (RMT_DIV_CNT_CH2_V << RMT_DIV_CNT_CH2_S) +#define RMT_DIV_CNT_CH2_V 0x000000FFU +#define RMT_DIV_CNT_CH2_S 0 +/** RMT_IDLE_THRES_CH2 : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ +#define RMT_IDLE_THRES_CH2 0x00007FFFU +#define RMT_IDLE_THRES_CH2_M (RMT_IDLE_THRES_CH2_V << RMT_IDLE_THRES_CH2_S) +#define RMT_IDLE_THRES_CH2_V 0x00007FFFU +#define RMT_IDLE_THRES_CH2_S 8 +/** RMT_MEM_SIZE_CH2 : R/W; bitpos: [25:23]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL2. + */ +#define RMT_MEM_SIZE_CH2 0x00000007U +#define RMT_MEM_SIZE_CH2_M (RMT_MEM_SIZE_CH2_V << RMT_MEM_SIZE_CH2_S) +#define RMT_MEM_SIZE_CH2_V 0x00000007U +#define RMT_MEM_SIZE_CH2_S 23 +/** RMT_CARRIER_EN_CH2 : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL2. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH2 (BIT(28)) +#define RMT_CARRIER_EN_CH2_M (RMT_CARRIER_EN_CH2_V << RMT_CARRIER_EN_CH2_S) +#define RMT_CARRIER_EN_CH2_V 0x00000001U +#define RMT_CARRIER_EN_CH2_S 28 +/** RMT_CARRIER_OUT_LV_CH2 : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL2. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH2 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH2_M (RMT_CARRIER_OUT_LV_CH2_V << RMT_CARRIER_OUT_LV_CH2_S) +#define RMT_CARRIER_OUT_LV_CH2_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH2_S 29 + +/** RMT_CH2CONF1_REG register + * Channel 2 configure register 1 + */ +#define RMT_CH2CONF1_REG (DR_REG_RMT_BASE + 0x1c) +/** RMT_RX_EN_CH2 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNEL2. + */ +#define RMT_RX_EN_CH2 (BIT(0)) +#define RMT_RX_EN_CH2_M (RMT_RX_EN_CH2_V << RMT_RX_EN_CH2_S) +#define RMT_RX_EN_CH2_V 0x00000001U +#define RMT_RX_EN_CH2_S 0 +/** RMT_MEM_WR_RST_CH2 : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNEL2 by accessing receiver. + */ +#define RMT_MEM_WR_RST_CH2 (BIT(1)) +#define RMT_MEM_WR_RST_CH2_M (RMT_MEM_WR_RST_CH2_V << RMT_MEM_WR_RST_CH2_S) +#define RMT_MEM_WR_RST_CH2_V 0x00000001U +#define RMT_MEM_WR_RST_CH2_S 1 +/** RMT_APB_MEM_RST_CH2 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL2 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH2 (BIT(2)) +#define RMT_APB_MEM_RST_CH2_M (RMT_APB_MEM_RST_CH2_V << RMT_APB_MEM_RST_CH2_S) +#define RMT_APB_MEM_RST_CH2_V 0x00000001U +#define RMT_APB_MEM_RST_CH2_S 2 +/** RMT_MEM_OWNER_CH2 : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNEL2's ram block. + * + * 1'h1: Receiver is using the ram. + * + * 1'h0: APB bus is using the ram. + */ +#define RMT_MEM_OWNER_CH2 (BIT(3)) +#define RMT_MEM_OWNER_CH2_M (RMT_MEM_OWNER_CH2_V << RMT_MEM_OWNER_CH2_S) +#define RMT_MEM_OWNER_CH2_V 0x00000001U +#define RMT_MEM_OWNER_CH2_S 3 +/** RMT_RX_FILTER_EN_CH2 : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNEL2. + */ +#define RMT_RX_FILTER_EN_CH2 (BIT(4)) +#define RMT_RX_FILTER_EN_CH2_M (RMT_RX_FILTER_EN_CH2_V << RMT_RX_FILTER_EN_CH2_S) +#define RMT_RX_FILTER_EN_CH2_V 0x00000001U +#define RMT_RX_FILTER_EN_CH2_S 4 +/** RMT_RX_FILTER_THRES_CH2 : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ +#define RMT_RX_FILTER_THRES_CH2 0x000000FFU +#define RMT_RX_FILTER_THRES_CH2_M (RMT_RX_FILTER_THRES_CH2_V << RMT_RX_FILTER_THRES_CH2_S) +#define RMT_RX_FILTER_THRES_CH2_V 0x000000FFU +#define RMT_RX_FILTER_THRES_CH2_S 5 +/** RMT_MEM_RX_WRAP_EN_CH2 : R/W; bitpos: [13]; default: 0; + * This is the channel 2 enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ +#define RMT_MEM_RX_WRAP_EN_CH2 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH2_M (RMT_MEM_RX_WRAP_EN_CH2_V << RMT_MEM_RX_WRAP_EN_CH2_S) +#define RMT_MEM_RX_WRAP_EN_CH2_V 0x00000001U +#define RMT_MEM_RX_WRAP_EN_CH2_S 13 +/** RMT_AFIFO_RST_CH2 : WT; bitpos: [14]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_CH2 (BIT(14)) +#define RMT_AFIFO_RST_CH2_M (RMT_AFIFO_RST_CH2_V << RMT_AFIFO_RST_CH2_S) +#define RMT_AFIFO_RST_CH2_V 0x00000001U +#define RMT_AFIFO_RST_CH2_S 14 +/** RMT_CONF_UPDATE_CH2 : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNEL2 + */ +#define RMT_CONF_UPDATE_CH2 (BIT(15)) +#define RMT_CONF_UPDATE_CH2_M (RMT_CONF_UPDATE_CH2_V << RMT_CONF_UPDATE_CH2_S) +#define RMT_CONF_UPDATE_CH2_V 0x00000001U +#define RMT_CONF_UPDATE_CH2_S 15 + +/** RMT_CH3CONF0_REG register + * Channel 3 configure register 0 + */ +#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x20) +/** RMT_DIV_CNT_CH3 : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNEL3. + */ +#define RMT_DIV_CNT_CH3 0x000000FFU +#define RMT_DIV_CNT_CH3_M (RMT_DIV_CNT_CH3_V << RMT_DIV_CNT_CH3_S) +#define RMT_DIV_CNT_CH3_V 0x000000FFU +#define RMT_DIV_CNT_CH3_S 0 +/** RMT_IDLE_THRES_CH3 : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ +#define RMT_IDLE_THRES_CH3 0x00007FFFU +#define RMT_IDLE_THRES_CH3_M (RMT_IDLE_THRES_CH3_V << RMT_IDLE_THRES_CH3_S) +#define RMT_IDLE_THRES_CH3_V 0x00007FFFU +#define RMT_IDLE_THRES_CH3_S 8 +/** RMT_MEM_SIZE_CH3 : R/W; bitpos: [25:23]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL3. + */ +#define RMT_MEM_SIZE_CH3 0x00000007U +#define RMT_MEM_SIZE_CH3_M (RMT_MEM_SIZE_CH3_V << RMT_MEM_SIZE_CH3_S) +#define RMT_MEM_SIZE_CH3_V 0x00000007U +#define RMT_MEM_SIZE_CH3_S 23 +/** RMT_CARRIER_EN_CH3 : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL3. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH3 (BIT(28)) +#define RMT_CARRIER_EN_CH3_M (RMT_CARRIER_EN_CH3_V << RMT_CARRIER_EN_CH3_S) +#define RMT_CARRIER_EN_CH3_V 0x00000001U +#define RMT_CARRIER_EN_CH3_S 28 +/** RMT_CARRIER_OUT_LV_CH3 : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL3. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH3 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH3_M (RMT_CARRIER_OUT_LV_CH3_V << RMT_CARRIER_OUT_LV_CH3_S) +#define RMT_CARRIER_OUT_LV_CH3_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH3_S 29 + +/** RMT_CH3CONF1_REG register + * Channel 3 configure register 1 + */ +#define RMT_CH3CONF1_REG (DR_REG_RMT_BASE + 0x24) +/** RMT_RX_EN_CH3 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNEL3. + */ +#define RMT_RX_EN_CH3 (BIT(0)) +#define RMT_RX_EN_CH3_M (RMT_RX_EN_CH3_V << RMT_RX_EN_CH3_S) +#define RMT_RX_EN_CH3_V 0x00000001U +#define RMT_RX_EN_CH3_S 0 +/** RMT_MEM_WR_RST_CH3 : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNEL3 by accessing receiver. + */ +#define RMT_MEM_WR_RST_CH3 (BIT(1)) +#define RMT_MEM_WR_RST_CH3_M (RMT_MEM_WR_RST_CH3_V << RMT_MEM_WR_RST_CH3_S) +#define RMT_MEM_WR_RST_CH3_V 0x00000001U +#define RMT_MEM_WR_RST_CH3_S 1 +/** RMT_APB_MEM_RST_CH3 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL3 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH3 (BIT(2)) +#define RMT_APB_MEM_RST_CH3_M (RMT_APB_MEM_RST_CH3_V << RMT_APB_MEM_RST_CH3_S) +#define RMT_APB_MEM_RST_CH3_V 0x00000001U +#define RMT_APB_MEM_RST_CH3_S 2 +/** RMT_MEM_OWNER_CH3 : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNEL3's ram block. + * + * 1'h1: Receiver is using the ram. + * + * 1'h0: APB bus is using the ram. + */ +#define RMT_MEM_OWNER_CH3 (BIT(3)) +#define RMT_MEM_OWNER_CH3_M (RMT_MEM_OWNER_CH3_V << RMT_MEM_OWNER_CH3_S) +#define RMT_MEM_OWNER_CH3_V 0x00000001U +#define RMT_MEM_OWNER_CH3_S 3 +/** RMT_RX_FILTER_EN_CH3 : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNEL3. + */ +#define RMT_RX_FILTER_EN_CH3 (BIT(4)) +#define RMT_RX_FILTER_EN_CH3_M (RMT_RX_FILTER_EN_CH3_V << RMT_RX_FILTER_EN_CH3_S) +#define RMT_RX_FILTER_EN_CH3_V 0x00000001U +#define RMT_RX_FILTER_EN_CH3_S 4 +/** RMT_RX_FILTER_THRES_CH3 : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ +#define RMT_RX_FILTER_THRES_CH3 0x000000FFU +#define RMT_RX_FILTER_THRES_CH3_M (RMT_RX_FILTER_THRES_CH3_V << RMT_RX_FILTER_THRES_CH3_S) +#define RMT_RX_FILTER_THRES_CH3_V 0x000000FFU +#define RMT_RX_FILTER_THRES_CH3_S 5 +/** RMT_MEM_RX_WRAP_EN_CH3 : R/W; bitpos: [13]; default: 0; + * This is the channel 3 enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ +#define RMT_MEM_RX_WRAP_EN_CH3 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH3_M (RMT_MEM_RX_WRAP_EN_CH3_V << RMT_MEM_RX_WRAP_EN_CH3_S) +#define RMT_MEM_RX_WRAP_EN_CH3_V 0x00000001U +#define RMT_MEM_RX_WRAP_EN_CH3_S 13 +/** RMT_AFIFO_RST_CH3 : WT; bitpos: [14]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_CH3 (BIT(14)) +#define RMT_AFIFO_RST_CH3_M (RMT_AFIFO_RST_CH3_V << RMT_AFIFO_RST_CH3_S) +#define RMT_AFIFO_RST_CH3_V 0x00000001U +#define RMT_AFIFO_RST_CH3_S 14 +/** RMT_CONF_UPDATE_CH3 : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNEL3 + */ +#define RMT_CONF_UPDATE_CH3 (BIT(15)) +#define RMT_CONF_UPDATE_CH3_M (RMT_CONF_UPDATE_CH3_V << RMT_CONF_UPDATE_CH3_S) +#define RMT_CONF_UPDATE_CH3_V 0x00000001U +#define RMT_CONF_UPDATE_CH3_S 15 + +/** RMT_CH0STATUS_REG register + * Channel 0 status register + */ +#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x28) +/** RMT_MEM_RADDR_EX_CH0 : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNEL0 is + * using the RAM. + */ +#define RMT_MEM_RADDR_EX_CH0 0x000001FFU +#define RMT_MEM_RADDR_EX_CH0_M (RMT_MEM_RADDR_EX_CH0_V << RMT_MEM_RADDR_EX_CH0_S) +#define RMT_MEM_RADDR_EX_CH0_V 0x000001FFU +#define RMT_MEM_RADDR_EX_CH0_S 0 +/** RMT_STATE_CH0 : RO; bitpos: [11:9]; default: 0; + * This register records the FSM status of CHANNEL0. + */ +#define RMT_STATE_CH0 0x00000007U +#define RMT_STATE_CH0_M (RMT_STATE_CH0_V << RMT_STATE_CH0_S) +#define RMT_STATE_CH0_V 0x00000007U +#define RMT_STATE_CH0_S 9 +/** RMT_APB_MEM_WADDR_CH0 : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ +#define RMT_APB_MEM_WADDR_CH0 0x000001FFU +#define RMT_APB_MEM_WADDR_CH0_M (RMT_APB_MEM_WADDR_CH0_V << RMT_APB_MEM_WADDR_CH0_S) +#define RMT_APB_MEM_WADDR_CH0_V 0x000001FFU +#define RMT_APB_MEM_WADDR_CH0_S 12 +/** RMT_APB_MEM_RD_ERR_CH0 : RO; bitpos: [21]; default: 0; + * This status bit will be set if the offset address out of memory size when reading + * via APB bus. + */ +#define RMT_APB_MEM_RD_ERR_CH0 (BIT(21)) +#define RMT_APB_MEM_RD_ERR_CH0_M (RMT_APB_MEM_RD_ERR_CH0_V << RMT_APB_MEM_RD_ERR_CH0_S) +#define RMT_APB_MEM_RD_ERR_CH0_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH0_S 21 +/** RMT_MEM_EMPTY_CH0 : RO; bitpos: [22]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ +#define RMT_MEM_EMPTY_CH0 (BIT(22)) +#define RMT_MEM_EMPTY_CH0_M (RMT_MEM_EMPTY_CH0_V << RMT_MEM_EMPTY_CH0_S) +#define RMT_MEM_EMPTY_CH0_V 0x00000001U +#define RMT_MEM_EMPTY_CH0_S 22 +/** RMT_APB_MEM_WR_ERR_CH0 : RO; bitpos: [23]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ +#define RMT_APB_MEM_WR_ERR_CH0 (BIT(23)) +#define RMT_APB_MEM_WR_ERR_CH0_M (RMT_APB_MEM_WR_ERR_CH0_V << RMT_APB_MEM_WR_ERR_CH0_S) +#define RMT_APB_MEM_WR_ERR_CH0_V 0x00000001U +#define RMT_APB_MEM_WR_ERR_CH0_S 23 +/** RMT_APB_MEM_RADDR_CH0 : RO; bitpos: [31:24]; default: 0; + * This register records the memory address offset when reading RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_CH0 0x000000FFU +#define RMT_APB_MEM_RADDR_CH0_M (RMT_APB_MEM_RADDR_CH0_V << RMT_APB_MEM_RADDR_CH0_S) +#define RMT_APB_MEM_RADDR_CH0_V 0x000000FFU +#define RMT_APB_MEM_RADDR_CH0_S 24 + +/** RMT_CH1STATUS_REG register + * Channel 1 status register + */ +#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x2c) +/** RMT_MEM_RADDR_EX_CH1 : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNEL1 is + * using the RAM. + */ +#define RMT_MEM_RADDR_EX_CH1 0x000001FFU +#define RMT_MEM_RADDR_EX_CH1_M (RMT_MEM_RADDR_EX_CH1_V << RMT_MEM_RADDR_EX_CH1_S) +#define RMT_MEM_RADDR_EX_CH1_V 0x000001FFU +#define RMT_MEM_RADDR_EX_CH1_S 0 +/** RMT_STATE_CH1 : RO; bitpos: [11:9]; default: 0; + * This register records the FSM status of CHANNEL1. + */ +#define RMT_STATE_CH1 0x00000007U +#define RMT_STATE_CH1_M (RMT_STATE_CH1_V << RMT_STATE_CH1_S) +#define RMT_STATE_CH1_V 0x00000007U +#define RMT_STATE_CH1_S 9 +/** RMT_APB_MEM_WADDR_CH1 : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ +#define RMT_APB_MEM_WADDR_CH1 0x000001FFU +#define RMT_APB_MEM_WADDR_CH1_M (RMT_APB_MEM_WADDR_CH1_V << RMT_APB_MEM_WADDR_CH1_S) +#define RMT_APB_MEM_WADDR_CH1_V 0x000001FFU +#define RMT_APB_MEM_WADDR_CH1_S 12 +/** RMT_APB_MEM_RD_ERR_CH1 : RO; bitpos: [21]; default: 0; + * This status bit will be set if the offset address out of memory size when reading + * via APB bus. + */ +#define RMT_APB_MEM_RD_ERR_CH1 (BIT(21)) +#define RMT_APB_MEM_RD_ERR_CH1_M (RMT_APB_MEM_RD_ERR_CH1_V << RMT_APB_MEM_RD_ERR_CH1_S) +#define RMT_APB_MEM_RD_ERR_CH1_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH1_S 21 +/** RMT_MEM_EMPTY_CH1 : RO; bitpos: [22]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ +#define RMT_MEM_EMPTY_CH1 (BIT(22)) +#define RMT_MEM_EMPTY_CH1_M (RMT_MEM_EMPTY_CH1_V << RMT_MEM_EMPTY_CH1_S) +#define RMT_MEM_EMPTY_CH1_V 0x00000001U +#define RMT_MEM_EMPTY_CH1_S 22 +/** RMT_APB_MEM_WR_ERR_CH1 : RO; bitpos: [23]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ +#define RMT_APB_MEM_WR_ERR_CH1 (BIT(23)) +#define RMT_APB_MEM_WR_ERR_CH1_M (RMT_APB_MEM_WR_ERR_CH1_V << RMT_APB_MEM_WR_ERR_CH1_S) +#define RMT_APB_MEM_WR_ERR_CH1_V 0x00000001U +#define RMT_APB_MEM_WR_ERR_CH1_S 23 +/** RMT_APB_MEM_RADDR_CH1 : RO; bitpos: [31:24]; default: 0; + * This register records the memory address offset when reading RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_CH1 0x000000FFU +#define RMT_APB_MEM_RADDR_CH1_M (RMT_APB_MEM_RADDR_CH1_V << RMT_APB_MEM_RADDR_CH1_S) +#define RMT_APB_MEM_RADDR_CH1_V 0x000000FFU +#define RMT_APB_MEM_RADDR_CH1_S 24 + +/** RMT_CH2STATUS_REG register + * Channel 2 status register + */ +#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x30) +/** RMT_MEM_WADDR_EX_CH2 : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when receiver of CHANNEL2 is using + * the RAM. + */ +#define RMT_MEM_WADDR_EX_CH2 0x000001FFU +#define RMT_MEM_WADDR_EX_CH2_M (RMT_MEM_WADDR_EX_CH2_V << RMT_MEM_WADDR_EX_CH2_S) +#define RMT_MEM_WADDR_EX_CH2_V 0x000001FFU +#define RMT_MEM_WADDR_EX_CH2_S 0 +/** RMT_APB_MEM_RADDR_CH2 : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when reads RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_CH2 0x000001FFU +#define RMT_APB_MEM_RADDR_CH2_M (RMT_APB_MEM_RADDR_CH2_V << RMT_APB_MEM_RADDR_CH2_S) +#define RMT_APB_MEM_RADDR_CH2_V 0x000001FFU +#define RMT_APB_MEM_RADDR_CH2_S 12 +/** RMT_STATE_CH2 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL2. + */ +#define RMT_STATE_CH2 0x00000007U +#define RMT_STATE_CH2_M (RMT_STATE_CH2_V << RMT_STATE_CH2_S) +#define RMT_STATE_CH2_V 0x00000007U +#define RMT_STATE_CH2_S 22 +/** RMT_MEM_OWNER_ERR_CH2 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ +#define RMT_MEM_OWNER_ERR_CH2 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH2_M (RMT_MEM_OWNER_ERR_CH2_V << RMT_MEM_OWNER_ERR_CH2_S) +#define RMT_MEM_OWNER_ERR_CH2_V 0x00000001U +#define RMT_MEM_OWNER_ERR_CH2_S 25 +/** RMT_MEM_FULL_CH2 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ +#define RMT_MEM_FULL_CH2 (BIT(26)) +#define RMT_MEM_FULL_CH2_M (RMT_MEM_FULL_CH2_V << RMT_MEM_FULL_CH2_S) +#define RMT_MEM_FULL_CH2_V 0x00000001U +#define RMT_MEM_FULL_CH2_S 26 +/** RMT_APB_MEM_RD_ERR_CH2 : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ +#define RMT_APB_MEM_RD_ERR_CH2 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH2_M (RMT_APB_MEM_RD_ERR_CH2_V << RMT_APB_MEM_RD_ERR_CH2_S) +#define RMT_APB_MEM_RD_ERR_CH2_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH2_S 27 + +/** RMT_CH3STATUS_REG register + * Channel 3 status register + */ +#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x34) +/** RMT_MEM_WADDR_EX_CH3 : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when receiver of CHANNEL3 is using + * the RAM. + */ +#define RMT_MEM_WADDR_EX_CH3 0x000001FFU +#define RMT_MEM_WADDR_EX_CH3_M (RMT_MEM_WADDR_EX_CH3_V << RMT_MEM_WADDR_EX_CH3_S) +#define RMT_MEM_WADDR_EX_CH3_V 0x000001FFU +#define RMT_MEM_WADDR_EX_CH3_S 0 +/** RMT_APB_MEM_RADDR_CH3 : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when reads RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_CH3 0x000001FFU +#define RMT_APB_MEM_RADDR_CH3_M (RMT_APB_MEM_RADDR_CH3_V << RMT_APB_MEM_RADDR_CH3_S) +#define RMT_APB_MEM_RADDR_CH3_V 0x000001FFU +#define RMT_APB_MEM_RADDR_CH3_S 12 +/** RMT_STATE_CH3 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL3. + */ +#define RMT_STATE_CH3 0x00000007U +#define RMT_STATE_CH3_M (RMT_STATE_CH3_V << RMT_STATE_CH3_S) +#define RMT_STATE_CH3_V 0x00000007U +#define RMT_STATE_CH3_S 22 +/** RMT_MEM_OWNER_ERR_CH3 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ +#define RMT_MEM_OWNER_ERR_CH3 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH3_M (RMT_MEM_OWNER_ERR_CH3_V << RMT_MEM_OWNER_ERR_CH3_S) +#define RMT_MEM_OWNER_ERR_CH3_V 0x00000001U +#define RMT_MEM_OWNER_ERR_CH3_S 25 +/** RMT_MEM_FULL_CH3 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ +#define RMT_MEM_FULL_CH3 (BIT(26)) +#define RMT_MEM_FULL_CH3_M (RMT_MEM_FULL_CH3_V << RMT_MEM_FULL_CH3_S) +#define RMT_MEM_FULL_CH3_V 0x00000001U +#define RMT_MEM_FULL_CH3_S 26 +/** RMT_APB_MEM_RD_ERR_CH3 : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ +#define RMT_APB_MEM_RD_ERR_CH3 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH3_M (RMT_APB_MEM_RD_ERR_CH3_V << RMT_APB_MEM_RD_ERR_CH3_S) +#define RMT_APB_MEM_RD_ERR_CH3_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH3_S 27 + +/** RMT_INT_RAW_REG register + * Raw interrupt status + */ +#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x38) +/** RMT_CH0_TX_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmission done. + */ +#define RMT_CH0_TX_END_INT_RAW (BIT(0)) +#define RMT_CH0_TX_END_INT_RAW_M (RMT_CH0_TX_END_INT_RAW_V << RMT_CH0_TX_END_INT_RAW_S) +#define RMT_CH0_TX_END_INT_RAW_V 0x00000001U +#define RMT_CH0_TX_END_INT_RAW_S 0 +/** RMT_CH1_TX_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmission done. + */ +#define RMT_CH1_TX_END_INT_RAW (BIT(1)) +#define RMT_CH1_TX_END_INT_RAW_M (RMT_CH1_TX_END_INT_RAW_V << RMT_CH1_TX_END_INT_RAW_S) +#define RMT_CH1_TX_END_INT_RAW_V 0x00000001U +#define RMT_CH1_TX_END_INT_RAW_S 1 +/** RMT_CH2_RX_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when reception done. + */ +#define RMT_CH2_RX_END_INT_RAW (BIT(2)) +#define RMT_CH2_RX_END_INT_RAW_M (RMT_CH2_RX_END_INT_RAW_V << RMT_CH2_RX_END_INT_RAW_S) +#define RMT_CH2_RX_END_INT_RAW_V 0x00000001U +#define RMT_CH2_RX_END_INT_RAW_S 2 +/** RMT_CH3_RX_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when reception done. + */ +#define RMT_CH3_RX_END_INT_RAW (BIT(3)) +#define RMT_CH3_RX_END_INT_RAW_M (RMT_CH3_RX_END_INT_RAW_V << RMT_CH3_RX_END_INT_RAW_S) +#define RMT_CH3_RX_END_INT_RAW_V 0x00000001U +#define RMT_CH3_RX_END_INT_RAW_S 3 +/** RMT_CH0_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when error occurs. + */ +#define RMT_CH0_ERR_INT_RAW (BIT(4)) +#define RMT_CH0_ERR_INT_RAW_M (RMT_CH0_ERR_INT_RAW_V << RMT_CH0_ERR_INT_RAW_S) +#define RMT_CH0_ERR_INT_RAW_V 0x00000001U +#define RMT_CH0_ERR_INT_RAW_S 4 +/** RMT_CH1_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when error occurs. + */ +#define RMT_CH1_ERR_INT_RAW (BIT(5)) +#define RMT_CH1_ERR_INT_RAW_M (RMT_CH1_ERR_INT_RAW_V << RMT_CH1_ERR_INT_RAW_S) +#define RMT_CH1_ERR_INT_RAW_V 0x00000001U +#define RMT_CH1_ERR_INT_RAW_S 5 +/** RMT_CH2_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when error occurs. + */ +#define RMT_CH2_ERR_INT_RAW (BIT(6)) +#define RMT_CH2_ERR_INT_RAW_M (RMT_CH2_ERR_INT_RAW_V << RMT_CH2_ERR_INT_RAW_S) +#define RMT_CH2_ERR_INT_RAW_V 0x00000001U +#define RMT_CH2_ERR_INT_RAW_S 6 +/** RMT_CH3_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when error occurs. + */ +#define RMT_CH3_ERR_INT_RAW (BIT(7)) +#define RMT_CH3_ERR_INT_RAW_M (RMT_CH3_ERR_INT_RAW_V << RMT_CH3_ERR_INT_RAW_S) +#define RMT_CH3_ERR_INT_RAW_V 0x00000001U +#define RMT_CH3_ERR_INT_RAW_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than + * configured value. + */ +#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (RMT_CH0_TX_THR_EVENT_INT_RAW_V << RMT_CH0_TX_THR_EVENT_INT_RAW_S) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than + * configured value. + */ +#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (RMT_CH1_TX_THR_EVENT_INT_RAW_V << RMT_CH1_TX_THR_EVENT_INT_RAW_S) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 9 +/** RMT_CH2_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than + * configured value. + */ +#define RMT_CH2_RX_THR_EVENT_INT_RAW (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_RAW_M (RMT_CH2_RX_THR_EVENT_INT_RAW_V << RMT_CH2_RX_THR_EVENT_INT_RAW_S) +#define RMT_CH2_RX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH2_RX_THR_EVENT_INT_RAW_S 10 +/** RMT_CH3_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than + * configured value. + */ +#define RMT_CH3_RX_THR_EVENT_INT_RAW (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_RAW_M (RMT_CH3_RX_THR_EVENT_INT_RAW_V << RMT_CH3_RX_THR_EVENT_INT_RAW_S) +#define RMT_CH3_RX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH3_RX_THR_EVENT_INT_RAW_S 11 +/** RMT_CH0_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the + * configured threshold value. + */ +#define RMT_CH0_TX_LOOP_INT_RAW (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_RAW_M (RMT_CH0_TX_LOOP_INT_RAW_V << RMT_CH0_TX_LOOP_INT_RAW_S) +#define RMT_CH0_TX_LOOP_INT_RAW_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_RAW_S 12 +/** RMT_CH1_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the + * configured threshold value. + */ +#define RMT_CH1_TX_LOOP_INT_RAW (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_RAW_M (RMT_CH1_TX_LOOP_INT_RAW_V << RMT_CH1_TX_LOOP_INT_RAW_S) +#define RMT_CH1_TX_LOOP_INT_RAW_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_RAW_S 13 + +/** RMT_INT_ST_REG register + * Masked interrupt status + */ +#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x3c) +/** RMT_CH0_TX_END_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for CH0_TX_END_INT. + */ +#define RMT_CH0_TX_END_INT_ST (BIT(0)) +#define RMT_CH0_TX_END_INT_ST_M (RMT_CH0_TX_END_INT_ST_V << RMT_CH0_TX_END_INT_ST_S) +#define RMT_CH0_TX_END_INT_ST_V 0x00000001U +#define RMT_CH0_TX_END_INT_ST_S 0 +/** RMT_CH1_TX_END_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for CH1_TX_END_INT. + */ +#define RMT_CH1_TX_END_INT_ST (BIT(1)) +#define RMT_CH1_TX_END_INT_ST_M (RMT_CH1_TX_END_INT_ST_V << RMT_CH1_TX_END_INT_ST_S) +#define RMT_CH1_TX_END_INT_ST_V 0x00000001U +#define RMT_CH1_TX_END_INT_ST_S 1 +/** RMT_CH2_RX_END_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for CH2_RX_END_INT. + */ +#define RMT_CH2_RX_END_INT_ST (BIT(2)) +#define RMT_CH2_RX_END_INT_ST_M (RMT_CH2_RX_END_INT_ST_V << RMT_CH2_RX_END_INT_ST_S) +#define RMT_CH2_RX_END_INT_ST_V 0x00000001U +#define RMT_CH2_RX_END_INT_ST_S 2 +/** RMT_CH3_RX_END_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for CH3_RX_END_INT. + */ +#define RMT_CH3_RX_END_INT_ST (BIT(3)) +#define RMT_CH3_RX_END_INT_ST_M (RMT_CH3_RX_END_INT_ST_V << RMT_CH3_RX_END_INT_ST_S) +#define RMT_CH3_RX_END_INT_ST_V 0x00000001U +#define RMT_CH3_RX_END_INT_ST_S 3 +/** RMT_CH0_ERR_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ +#define RMT_CH0_ERR_INT_ST (BIT(4)) +#define RMT_CH0_ERR_INT_ST_M (RMT_CH0_ERR_INT_ST_V << RMT_CH0_ERR_INT_ST_S) +#define RMT_CH0_ERR_INT_ST_V 0x00000001U +#define RMT_CH0_ERR_INT_ST_S 4 +/** RMT_CH1_ERR_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ +#define RMT_CH1_ERR_INT_ST (BIT(5)) +#define RMT_CH1_ERR_INT_ST_M (RMT_CH1_ERR_INT_ST_V << RMT_CH1_ERR_INT_ST_S) +#define RMT_CH1_ERR_INT_ST_V 0x00000001U +#define RMT_CH1_ERR_INT_ST_S 5 +/** RMT_CH2_ERR_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ +#define RMT_CH2_ERR_INT_ST (BIT(6)) +#define RMT_CH2_ERR_INT_ST_M (RMT_CH2_ERR_INT_ST_V << RMT_CH2_ERR_INT_ST_S) +#define RMT_CH2_ERR_INT_ST_V 0x00000001U +#define RMT_CH2_ERR_INT_ST_S 6 +/** RMT_CH3_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ +#define RMT_CH3_ERR_INT_ST (BIT(7)) +#define RMT_CH3_ERR_INT_ST_M (RMT_CH3_ERR_INT_ST_V << RMT_CH3_ERR_INT_ST_S) +#define RMT_CH3_ERR_INT_ST_V 0x00000001U +#define RMT_CH3_ERR_INT_ST_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + */ +#define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ST_M (RMT_CH0_TX_THR_EVENT_INT_ST_V << RMT_CH0_TX_THR_EVENT_INT_ST_S) +#define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_ST_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for CH1_TX_THR_EVENT_INT. + */ +#define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ST_M (RMT_CH1_TX_THR_EVENT_INT_ST_V << RMT_CH1_TX_THR_EVENT_INT_ST_S) +#define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_ST_S 9 +/** RMT_CH2_RX_THR_EVENT_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for CH2_RX_THR_EVENT_INT. + */ +#define RMT_CH2_RX_THR_EVENT_INT_ST (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_ST_M (RMT_CH2_RX_THR_EVENT_INT_ST_V << RMT_CH2_RX_THR_EVENT_INT_ST_S) +#define RMT_CH2_RX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH2_RX_THR_EVENT_INT_ST_S 10 +/** RMT_CH3_RX_THR_EVENT_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for CH3_RX_THR_EVENT_INT. + */ +#define RMT_CH3_RX_THR_EVENT_INT_ST (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_ST_M (RMT_CH3_RX_THR_EVENT_INT_ST_V << RMT_CH3_RX_THR_EVENT_INT_ST_S) +#define RMT_CH3_RX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH3_RX_THR_EVENT_INT_ST_S 11 +/** RMT_CH0_TX_LOOP_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for CH0_TX_LOOP_INT. + */ +#define RMT_CH0_TX_LOOP_INT_ST (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ST_M (RMT_CH0_TX_LOOP_INT_ST_V << RMT_CH0_TX_LOOP_INT_ST_S) +#define RMT_CH0_TX_LOOP_INT_ST_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_ST_S 12 +/** RMT_CH1_TX_LOOP_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for CH1_TX_LOOP_INT. + */ +#define RMT_CH1_TX_LOOP_INT_ST (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ST_M (RMT_CH1_TX_LOOP_INT_ST_V << RMT_CH1_TX_LOOP_INT_ST_S) +#define RMT_CH1_TX_LOOP_INT_ST_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_ST_S 13 + +/** RMT_INT_ENA_REG register + * Interrupt enable bits + */ +#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x40) +/** RMT_CH0_TX_END_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for CH0_TX_END_INT. + */ +#define RMT_CH0_TX_END_INT_ENA (BIT(0)) +#define RMT_CH0_TX_END_INT_ENA_M (RMT_CH0_TX_END_INT_ENA_V << RMT_CH0_TX_END_INT_ENA_S) +#define RMT_CH0_TX_END_INT_ENA_V 0x00000001U +#define RMT_CH0_TX_END_INT_ENA_S 0 +/** RMT_CH1_TX_END_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for CH1_TX_END_INT. + */ +#define RMT_CH1_TX_END_INT_ENA (BIT(1)) +#define RMT_CH1_TX_END_INT_ENA_M (RMT_CH1_TX_END_INT_ENA_V << RMT_CH1_TX_END_INT_ENA_S) +#define RMT_CH1_TX_END_INT_ENA_V 0x00000001U +#define RMT_CH1_TX_END_INT_ENA_S 1 +/** RMT_CH2_RX_END_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for CH2_RX_END_INT. + */ +#define RMT_CH2_RX_END_INT_ENA (BIT(2)) +#define RMT_CH2_RX_END_INT_ENA_M (RMT_CH2_RX_END_INT_ENA_V << RMT_CH2_RX_END_INT_ENA_S) +#define RMT_CH2_RX_END_INT_ENA_V 0x00000001U +#define RMT_CH2_RX_END_INT_ENA_S 2 +/** RMT_CH3_RX_END_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for CH3_RX_END_INT. + */ +#define RMT_CH3_RX_END_INT_ENA (BIT(3)) +#define RMT_CH3_RX_END_INT_ENA_M (RMT_CH3_RX_END_INT_ENA_V << RMT_CH3_RX_END_INT_ENA_S) +#define RMT_CH3_RX_END_INT_ENA_V 0x00000001U +#define RMT_CH3_RX_END_INT_ENA_S 3 +/** RMT_CH0_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ +#define RMT_CH0_ERR_INT_ENA (BIT(4)) +#define RMT_CH0_ERR_INT_ENA_M (RMT_CH0_ERR_INT_ENA_V << RMT_CH0_ERR_INT_ENA_S) +#define RMT_CH0_ERR_INT_ENA_V 0x00000001U +#define RMT_CH0_ERR_INT_ENA_S 4 +/** RMT_CH1_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ +#define RMT_CH1_ERR_INT_ENA (BIT(5)) +#define RMT_CH1_ERR_INT_ENA_M (RMT_CH1_ERR_INT_ENA_V << RMT_CH1_ERR_INT_ENA_S) +#define RMT_CH1_ERR_INT_ENA_V 0x00000001U +#define RMT_CH1_ERR_INT_ENA_S 5 +/** RMT_CH2_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ +#define RMT_CH2_ERR_INT_ENA (BIT(6)) +#define RMT_CH2_ERR_INT_ENA_M (RMT_CH2_ERR_INT_ENA_V << RMT_CH2_ERR_INT_ENA_S) +#define RMT_CH2_ERR_INT_ENA_V 0x00000001U +#define RMT_CH2_ERR_INT_ENA_S 6 +/** RMT_CH3_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ +#define RMT_CH3_ERR_INT_ENA (BIT(7)) +#define RMT_CH3_ERR_INT_ENA_M (RMT_CH3_ERR_INT_ENA_V << RMT_CH3_ERR_INT_ENA_S) +#define RMT_CH3_ERR_INT_ENA_V 0x00000001U +#define RMT_CH3_ERR_INT_ENA_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for CH0_TX_THR_EVENT_INT. + */ +#define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_M (RMT_CH0_TX_THR_EVENT_INT_ENA_V << RMT_CH0_TX_THR_EVENT_INT_ENA_S) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_ENA_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for CH1_TX_THR_EVENT_INT. + */ +#define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_M (RMT_CH1_TX_THR_EVENT_INT_ENA_V << RMT_CH1_TX_THR_EVENT_INT_ENA_S) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_ENA_S 9 +/** RMT_CH2_RX_THR_EVENT_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for CH2_RX_THR_EVENT_INT. + */ +#define RMT_CH2_RX_THR_EVENT_INT_ENA (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_ENA_M (RMT_CH2_RX_THR_EVENT_INT_ENA_V << RMT_CH2_RX_THR_EVENT_INT_ENA_S) +#define RMT_CH2_RX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH2_RX_THR_EVENT_INT_ENA_S 10 +/** RMT_CH3_RX_THR_EVENT_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for CH3_RX_THR_EVENT_INT. + */ +#define RMT_CH3_RX_THR_EVENT_INT_ENA (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_ENA_M (RMT_CH3_RX_THR_EVENT_INT_ENA_V << RMT_CH3_RX_THR_EVENT_INT_ENA_S) +#define RMT_CH3_RX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH3_RX_THR_EVENT_INT_ENA_S 11 +/** RMT_CH0_TX_LOOP_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for CH0_TX_LOOP_INT. + */ +#define RMT_CH0_TX_LOOP_INT_ENA (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ENA_M (RMT_CH0_TX_LOOP_INT_ENA_V << RMT_CH0_TX_LOOP_INT_ENA_S) +#define RMT_CH0_TX_LOOP_INT_ENA_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_ENA_S 12 +/** RMT_CH1_TX_LOOP_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for CH1_TX_LOOP_INT. + */ +#define RMT_CH1_TX_LOOP_INT_ENA (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ENA_M (RMT_CH1_TX_LOOP_INT_ENA_V << RMT_CH1_TX_LOOP_INT_ENA_S) +#define RMT_CH1_TX_LOOP_INT_ENA_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_ENA_S 13 + +/** RMT_INT_CLR_REG register + * Interrupt clear bits + */ +#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x44) +/** RMT_CH0_TX_END_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear theCH0_TX_END_INT interrupt. + */ +#define RMT_CH0_TX_END_INT_CLR (BIT(0)) +#define RMT_CH0_TX_END_INT_CLR_M (RMT_CH0_TX_END_INT_CLR_V << RMT_CH0_TX_END_INT_CLR_S) +#define RMT_CH0_TX_END_INT_CLR_V 0x00000001U +#define RMT_CH0_TX_END_INT_CLR_S 0 +/** RMT_CH1_TX_END_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear theCH1_TX_END_INT interrupt. + */ +#define RMT_CH1_TX_END_INT_CLR (BIT(1)) +#define RMT_CH1_TX_END_INT_CLR_M (RMT_CH1_TX_END_INT_CLR_V << RMT_CH1_TX_END_INT_CLR_S) +#define RMT_CH1_TX_END_INT_CLR_V 0x00000001U +#define RMT_CH1_TX_END_INT_CLR_S 1 +/** RMT_CH2_RX_END_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear theCH2_RX_END_INT interrupt. + */ +#define RMT_CH2_RX_END_INT_CLR (BIT(2)) +#define RMT_CH2_RX_END_INT_CLR_M (RMT_CH2_RX_END_INT_CLR_V << RMT_CH2_RX_END_INT_CLR_S) +#define RMT_CH2_RX_END_INT_CLR_V 0x00000001U +#define RMT_CH2_RX_END_INT_CLR_S 2 +/** RMT_CH3_RX_END_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear theCH3_RX_END_INT interrupt. + */ +#define RMT_CH3_RX_END_INT_CLR (BIT(3)) +#define RMT_CH3_RX_END_INT_CLR_M (RMT_CH3_RX_END_INT_CLR_V << RMT_CH3_RX_END_INT_CLR_S) +#define RMT_CH3_RX_END_INT_CLR_V 0x00000001U +#define RMT_CH3_RX_END_INT_CLR_S 3 +/** RMT_CH0_ERR_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ +#define RMT_CH0_ERR_INT_CLR (BIT(4)) +#define RMT_CH0_ERR_INT_CLR_M (RMT_CH0_ERR_INT_CLR_V << RMT_CH0_ERR_INT_CLR_S) +#define RMT_CH0_ERR_INT_CLR_V 0x00000001U +#define RMT_CH0_ERR_INT_CLR_S 4 +/** RMT_CH1_ERR_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ +#define RMT_CH1_ERR_INT_CLR (BIT(5)) +#define RMT_CH1_ERR_INT_CLR_M (RMT_CH1_ERR_INT_CLR_V << RMT_CH1_ERR_INT_CLR_S) +#define RMT_CH1_ERR_INT_CLR_V 0x00000001U +#define RMT_CH1_ERR_INT_CLR_S 5 +/** RMT_CH2_ERR_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ +#define RMT_CH2_ERR_INT_CLR (BIT(6)) +#define RMT_CH2_ERR_INT_CLR_M (RMT_CH2_ERR_INT_CLR_V << RMT_CH2_ERR_INT_CLR_S) +#define RMT_CH2_ERR_INT_CLR_V 0x00000001U +#define RMT_CH2_ERR_INT_CLR_S 6 +/** RMT_CH3_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ +#define RMT_CH3_ERR_INT_CLR (BIT(7)) +#define RMT_CH3_ERR_INT_CLR_M (RMT_CH3_ERR_INT_CLR_V << RMT_CH3_ERR_INT_CLR_S) +#define RMT_CH3_ERR_INT_CLR_V 0x00000001U +#define RMT_CH3_ERR_INT_CLR_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. + */ +#define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_M (RMT_CH0_TX_THR_EVENT_INT_CLR_V << RMT_CH0_TX_THR_EVENT_INT_CLR_S) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_CLR_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. + */ +#define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_M (RMT_CH1_TX_THR_EVENT_INT_CLR_V << RMT_CH1_TX_THR_EVENT_INT_CLR_S) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_CLR_S 9 +/** RMT_CH2_RX_THR_EVENT_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt. + */ +#define RMT_CH2_RX_THR_EVENT_INT_CLR (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_CLR_M (RMT_CH2_RX_THR_EVENT_INT_CLR_V << RMT_CH2_RX_THR_EVENT_INT_CLR_S) +#define RMT_CH2_RX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH2_RX_THR_EVENT_INT_CLR_S 10 +/** RMT_CH3_RX_THR_EVENT_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt. + */ +#define RMT_CH3_RX_THR_EVENT_INT_CLR (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_CLR_M (RMT_CH3_RX_THR_EVENT_INT_CLR_V << RMT_CH3_RX_THR_EVENT_INT_CLR_S) +#define RMT_CH3_RX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH3_RX_THR_EVENT_INT_CLR_S 11 +/** RMT_CH0_TX_LOOP_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear theCH0_TX_LOOP_INT interrupt. + */ +#define RMT_CH0_TX_LOOP_INT_CLR (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_CLR_M (RMT_CH0_TX_LOOP_INT_CLR_V << RMT_CH0_TX_LOOP_INT_CLR_S) +#define RMT_CH0_TX_LOOP_INT_CLR_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_CLR_S 12 +/** RMT_CH1_TX_LOOP_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear theCH1_TX_LOOP_INT interrupt. + */ +#define RMT_CH1_TX_LOOP_INT_CLR (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_CLR_M (RMT_CH1_TX_LOOP_INT_CLR_V << RMT_CH1_TX_LOOP_INT_CLR_S) +#define RMT_CH1_TX_LOOP_INT_CLR_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_CLR_S 13 + +/** RMT_CH0CARRIER_DUTY_REG register + * Channel 0 duty cycle configuration register + */ +#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x48) +/** RMT_CARRIER_LOW_CH0 : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNEL0. + */ +#define RMT_CARRIER_LOW_CH0 0x0000FFFFU +#define RMT_CARRIER_LOW_CH0_M (RMT_CARRIER_LOW_CH0_V << RMT_CARRIER_LOW_CH0_S) +#define RMT_CARRIER_LOW_CH0_V 0x0000FFFFU +#define RMT_CARRIER_LOW_CH0_S 0 +/** RMT_CARRIER_HIGH_CH0 : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNEL0. + */ +#define RMT_CARRIER_HIGH_CH0 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH0_M (RMT_CARRIER_HIGH_CH0_V << RMT_CARRIER_HIGH_CH0_S) +#define RMT_CARRIER_HIGH_CH0_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH0_S 16 + +/** RMT_CH1CARRIER_DUTY_REG register + * Channel 1 duty cycle configuration register + */ +#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x4c) +/** RMT_CARRIER_LOW_CH1 : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNEL1. + */ +#define RMT_CARRIER_LOW_CH1 0x0000FFFFU +#define RMT_CARRIER_LOW_CH1_M (RMT_CARRIER_LOW_CH1_V << RMT_CARRIER_LOW_CH1_S) +#define RMT_CARRIER_LOW_CH1_V 0x0000FFFFU +#define RMT_CARRIER_LOW_CH1_S 0 +/** RMT_CARRIER_HIGH_CH1 : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNEL1. + */ +#define RMT_CARRIER_HIGH_CH1 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH1_M (RMT_CARRIER_HIGH_CH1_V << RMT_CARRIER_HIGH_CH1_S) +#define RMT_CARRIER_HIGH_CH1_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH1_S 16 + +/** RMT_CH2_RX_CARRIER_RM_REG register + * Channel 2 carrier remove register + */ +#define RMT_CH2_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x50) +/** RMT_CARRIER_LOW_THRES_CH2 : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CH2 + 1) for channel 2. + */ +#define RMT_CARRIER_LOW_THRES_CH2 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH2_M (RMT_CARRIER_LOW_THRES_CH2_V << RMT_CARRIER_LOW_THRES_CH2_S) +#define RMT_CARRIER_LOW_THRES_CH2_V 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH2_S 0 +/** RMT_CARRIER_HIGH_THRES_CH2 : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CH2 + 1) for channel 2. + */ +#define RMT_CARRIER_HIGH_THRES_CH2 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH2_M (RMT_CARRIER_HIGH_THRES_CH2_V << RMT_CARRIER_HIGH_THRES_CH2_S) +#define RMT_CARRIER_HIGH_THRES_CH2_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH2_S 16 + +/** RMT_CH3_RX_CARRIER_RM_REG register + * Channel 3 carrier remove register + */ +#define RMT_CH3_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x54) +/** RMT_CARRIER_LOW_THRES_CH3 : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CH3 + 1) for channel 3. + */ +#define RMT_CARRIER_LOW_THRES_CH3 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH3_M (RMT_CARRIER_LOW_THRES_CH3_V << RMT_CARRIER_LOW_THRES_CH3_S) +#define RMT_CARRIER_LOW_THRES_CH3_V 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH3_S 0 +/** RMT_CARRIER_HIGH_THRES_CH3 : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CH3 + 1) for channel 3. + */ +#define RMT_CARRIER_HIGH_THRES_CH3 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH3_M (RMT_CARRIER_HIGH_THRES_CH3_V << RMT_CARRIER_HIGH_THRES_CH3_S) +#define RMT_CARRIER_HIGH_THRES_CH3_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH3_S 16 + +/** RMT_CH0_TX_LIM_REG register + * Channel 0 Tx event configuration register + */ +#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0x58) +/** RMT_TX_LIM_CH0 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL0 can send out. + */ +#define RMT_TX_LIM_CH0 0x000001FFU +#define RMT_TX_LIM_CH0_M (RMT_TX_LIM_CH0_V << RMT_TX_LIM_CH0_S) +#define RMT_TX_LIM_CH0_V 0x000001FFU +#define RMT_TX_LIM_CH0_S 0 +/** RMT_TX_LOOP_NUM_CH0 : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ +#define RMT_TX_LOOP_NUM_CH0 0x000003FFU +#define RMT_TX_LOOP_NUM_CH0_M (RMT_TX_LOOP_NUM_CH0_V << RMT_TX_LOOP_NUM_CH0_S) +#define RMT_TX_LOOP_NUM_CH0_V 0x000003FFU +#define RMT_TX_LOOP_NUM_CH0_S 9 +/** RMT_TX_LOOP_CNT_EN_CH0 : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ +#define RMT_TX_LOOP_CNT_EN_CH0 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH0_M (RMT_TX_LOOP_CNT_EN_CH0_V << RMT_TX_LOOP_CNT_EN_CH0_S) +#define RMT_TX_LOOP_CNT_EN_CH0_V 0x00000001U +#define RMT_TX_LOOP_CNT_EN_CH0_S 19 +/** RMT_LOOP_COUNT_RESET_CH0 : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ +#define RMT_LOOP_COUNT_RESET_CH0 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH0_M (RMT_LOOP_COUNT_RESET_CH0_V << RMT_LOOP_COUNT_RESET_CH0_S) +#define RMT_LOOP_COUNT_RESET_CH0_V 0x00000001U +#define RMT_LOOP_COUNT_RESET_CH0_S 20 +/** RMT_LOOP_STOP_EN_CH0 : R/W; bitpos: [21]; default: 0; + * This bit is used to enable the loop send stop function after the loop counter + * counts to loop number for CHANNEL0. + */ +#define RMT_LOOP_STOP_EN_CH0 (BIT(21)) +#define RMT_LOOP_STOP_EN_CH0_M (RMT_LOOP_STOP_EN_CH0_V << RMT_LOOP_STOP_EN_CH0_S) +#define RMT_LOOP_STOP_EN_CH0_V 0x00000001U +#define RMT_LOOP_STOP_EN_CH0_S 21 + +/** RMT_CH1_TX_LIM_REG register + * Channel 1 Tx event configuration register + */ +#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x5c) +/** RMT_TX_LIM_CH1 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL1 can send out. + */ +#define RMT_TX_LIM_CH1 0x000001FFU +#define RMT_TX_LIM_CH1_M (RMT_TX_LIM_CH1_V << RMT_TX_LIM_CH1_S) +#define RMT_TX_LIM_CH1_V 0x000001FFU +#define RMT_TX_LIM_CH1_S 0 +/** RMT_TX_LOOP_NUM_CH1 : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ +#define RMT_TX_LOOP_NUM_CH1 0x000003FFU +#define RMT_TX_LOOP_NUM_CH1_M (RMT_TX_LOOP_NUM_CH1_V << RMT_TX_LOOP_NUM_CH1_S) +#define RMT_TX_LOOP_NUM_CH1_V 0x000003FFU +#define RMT_TX_LOOP_NUM_CH1_S 9 +/** RMT_TX_LOOP_CNT_EN_CH1 : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ +#define RMT_TX_LOOP_CNT_EN_CH1 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH1_M (RMT_TX_LOOP_CNT_EN_CH1_V << RMT_TX_LOOP_CNT_EN_CH1_S) +#define RMT_TX_LOOP_CNT_EN_CH1_V 0x00000001U +#define RMT_TX_LOOP_CNT_EN_CH1_S 19 +/** RMT_LOOP_COUNT_RESET_CH1 : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ +#define RMT_LOOP_COUNT_RESET_CH1 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH1_M (RMT_LOOP_COUNT_RESET_CH1_V << RMT_LOOP_COUNT_RESET_CH1_S) +#define RMT_LOOP_COUNT_RESET_CH1_V 0x00000001U +#define RMT_LOOP_COUNT_RESET_CH1_S 20 +/** RMT_LOOP_STOP_EN_CH1 : R/W; bitpos: [21]; default: 0; + * This bit is used to enable the loop send stop function after the loop counter + * counts to loop number for CHANNEL1. + */ +#define RMT_LOOP_STOP_EN_CH1 (BIT(21)) +#define RMT_LOOP_STOP_EN_CH1_M (RMT_LOOP_STOP_EN_CH1_V << RMT_LOOP_STOP_EN_CH1_S) +#define RMT_LOOP_STOP_EN_CH1_V 0x00000001U +#define RMT_LOOP_STOP_EN_CH1_S 21 + +/** RMT_CH2_RX_LIM_REG register + * Channel 2 Rx event configuration register + */ +#define RMT_CH2_RX_LIM_REG (DR_REG_RMT_BASE + 0x60) +/** RMT_RMT_RX_LIM_CH2 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL2 can receive. + */ +#define RMT_RMT_RX_LIM_CH2 0x000001FFU +#define RMT_RMT_RX_LIM_CH2_M (RMT_RMT_RX_LIM_CH2_V << RMT_RMT_RX_LIM_CH2_S) +#define RMT_RMT_RX_LIM_CH2_V 0x000001FFU +#define RMT_RMT_RX_LIM_CH2_S 0 + +/** RMT_CH3_RX_LIM_REG register + * Channel 3 Rx event configuration register + */ +#define RMT_CH3_RX_LIM_REG (DR_REG_RMT_BASE + 0x64) +/** RMT_RMT_RX_LIM_CH2 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL3 can receive. + */ +#define RMT_RMT_RX_LIM_CH2 0x000001FFU +#define RMT_RMT_RX_LIM_CH2_M (RMT_RMT_RX_LIM_CH2_V << RMT_RMT_RX_LIM_CH2_S) +#define RMT_RMT_RX_LIM_CH2_V 0x000001FFU +#define RMT_RMT_RX_LIM_CH2_S 0 + +/** RMT_SYS_CONF_REG register + * RMT apb configuration register + */ +#define RMT_SYS_CONF_REG (DR_REG_RMT_BASE + 0x68) +/** RMT_APB_FIFO_MASK : R/W; bitpos: [0]; default: 0; + * 1'h1: access memory directly. 1'h0: access memory by FIFO. + */ +#define RMT_APB_FIFO_MASK (BIT(0)) +#define RMT_APB_FIFO_MASK_M (RMT_APB_FIFO_MASK_V << RMT_APB_FIFO_MASK_S) +#define RMT_APB_FIFO_MASK_V 0x00000001U +#define RMT_APB_FIFO_MASK_S 0 +/** RMT_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0; + * Set this bit to enable the clock for RMT memory. + */ +#define RMT_MEM_CLK_FORCE_ON (BIT(1)) +#define RMT_MEM_CLK_FORCE_ON_M (RMT_MEM_CLK_FORCE_ON_V << RMT_MEM_CLK_FORCE_ON_S) +#define RMT_MEM_CLK_FORCE_ON_V 0x00000001U +#define RMT_MEM_CLK_FORCE_ON_S 1 +/** RMT_RMT_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to power down RMT memory. + */ +#define RMT_RMT_MEM_FORCE_PD (BIT(2)) +#define RMT_RMT_MEM_FORCE_PD_M (RMT_RMT_MEM_FORCE_PD_V << RMT_RMT_MEM_FORCE_PD_S) +#define RMT_RMT_MEM_FORCE_PD_V 0x00000001U +#define RMT_RMT_MEM_FORCE_PD_S 2 +/** RMT_RMT_MEM_FORCE_PU : R/W; bitpos: [3]; default: 0; + * 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory + * when RMT is in light sleep mode. + */ +#define RMT_RMT_MEM_FORCE_PU (BIT(3)) +#define RMT_RMT_MEM_FORCE_PU_M (RMT_RMT_MEM_FORCE_PU_V << RMT_RMT_MEM_FORCE_PU_S) +#define RMT_RMT_MEM_FORCE_PU_V 0x00000001U +#define RMT_RMT_MEM_FORCE_PU_S 3 +/** RMT_RMT_SCLK_DIV_NUM : R/W; bitpos: [11:4]; default: 1; + * the integral part of the fractional divisor + */ +#define RMT_RMT_SCLK_DIV_NUM 0x000000FFU +#define RMT_RMT_SCLK_DIV_NUM_M (RMT_RMT_SCLK_DIV_NUM_V << RMT_RMT_SCLK_DIV_NUM_S) +#define RMT_RMT_SCLK_DIV_NUM_V 0x000000FFU +#define RMT_RMT_SCLK_DIV_NUM_S 4 +/** RMT_RMT_SCLK_DIV_A : R/W; bitpos: [17:12]; default: 0; + * the numerator of the fractional part of the fractional divisor + */ +#define RMT_RMT_SCLK_DIV_A 0x0000003FU +#define RMT_RMT_SCLK_DIV_A_M (RMT_RMT_SCLK_DIV_A_V << RMT_RMT_SCLK_DIV_A_S) +#define RMT_RMT_SCLK_DIV_A_V 0x0000003FU +#define RMT_RMT_SCLK_DIV_A_S 12 +/** RMT_RMT_SCLK_DIV_B : R/W; bitpos: [23:18]; default: 0; + * the denominator of the fractional part of the fractional divisor + */ +#define RMT_RMT_SCLK_DIV_B 0x0000003FU +#define RMT_RMT_SCLK_DIV_B_M (RMT_RMT_SCLK_DIV_B_V << RMT_RMT_SCLK_DIV_B_S) +#define RMT_RMT_SCLK_DIV_B_V 0x0000003FU +#define RMT_RMT_SCLK_DIV_B_S 18 +/** RMT_RMT_SCLK_SEL : R/W; bitpos: [25:24]; default: 1; + * choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL + */ +#define RMT_RMT_SCLK_SEL 0x00000003U +#define RMT_RMT_SCLK_SEL_M (RMT_RMT_SCLK_SEL_V << RMT_RMT_SCLK_SEL_S) +#define RMT_RMT_SCLK_SEL_V 0x00000003U +#define RMT_RMT_SCLK_SEL_S 24 +/** RMT_RMT_SCLK_ACTIVE : R/W; bitpos: [26]; default: 1; + * rmt_sclk switch + */ +#define RMT_RMT_SCLK_ACTIVE (BIT(26)) +#define RMT_RMT_SCLK_ACTIVE_M (RMT_RMT_SCLK_ACTIVE_V << RMT_RMT_SCLK_ACTIVE_S) +#define RMT_RMT_SCLK_ACTIVE_V 0x00000001U +#define RMT_RMT_SCLK_ACTIVE_S 26 +/** RMT_CLK_EN : R/W; bitpos: [31]; default: 0; + * RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: + * Power down the drive clock of registers + */ +#define RMT_CLK_EN (BIT(31)) +#define RMT_CLK_EN_M (RMT_CLK_EN_V << RMT_CLK_EN_S) +#define RMT_CLK_EN_V 0x00000001U +#define RMT_CLK_EN_S 31 + +/** RMT_TX_SIM_REG register + * RMT TX synchronous register + */ +#define RMT_TX_SIM_REG (DR_REG_RMT_BASE + 0x6c) +/** RMT_TX_SIM_CH0 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable CHANNEL0 to start sending data synchronously with other + * enabled channels. + */ +#define RMT_TX_SIM_CH0 (BIT(0)) +#define RMT_TX_SIM_CH0_M (RMT_TX_SIM_CH0_V << RMT_TX_SIM_CH0_S) +#define RMT_TX_SIM_CH0_V 0x00000001U +#define RMT_TX_SIM_CH0_S 0 +/** RMT_TX_SIM_CH1 : R/W; bitpos: [1]; default: 0; + * Set this bit to enable CHANNEL1 to start sending data synchronously with other + * enabled channels. + */ +#define RMT_TX_SIM_CH1 (BIT(1)) +#define RMT_TX_SIM_CH1_M (RMT_TX_SIM_CH1_V << RMT_TX_SIM_CH1_S) +#define RMT_TX_SIM_CH1_V 0x00000001U +#define RMT_TX_SIM_CH1_S 1 +/** RMT_TX_SIM_EN : R/W; bitpos: [2]; default: 0; + * This register is used to enable multiple of channels to start sending data + * synchronously. + */ +#define RMT_TX_SIM_EN (BIT(2)) +#define RMT_TX_SIM_EN_M (RMT_TX_SIM_EN_V << RMT_TX_SIM_EN_S) +#define RMT_TX_SIM_EN_V 0x00000001U +#define RMT_TX_SIM_EN_S 2 + +/** RMT_REF_CNT_RST_REG register + * RMT clock divider reset register + */ +#define RMT_REF_CNT_RST_REG (DR_REG_RMT_BASE + 0x70) +/** RMT_REF_CNT_RST_CH0 : WT; bitpos: [0]; default: 0; + * This register is used to reset the clock divider of CHANNEL0. + */ +#define RMT_REF_CNT_RST_CH0 (BIT(0)) +#define RMT_REF_CNT_RST_CH0_M (RMT_REF_CNT_RST_CH0_V << RMT_REF_CNT_RST_CH0_S) +#define RMT_REF_CNT_RST_CH0_V 0x00000001U +#define RMT_REF_CNT_RST_CH0_S 0 +/** RMT_REF_CNT_RST_CH1 : WT; bitpos: [1]; default: 0; + * This register is used to reset the clock divider of CHANNEL1. + */ +#define RMT_REF_CNT_RST_CH1 (BIT(1)) +#define RMT_REF_CNT_RST_CH1_M (RMT_REF_CNT_RST_CH1_V << RMT_REF_CNT_RST_CH1_S) +#define RMT_REF_CNT_RST_CH1_V 0x00000001U +#define RMT_REF_CNT_RST_CH1_S 1 +/** RMT_REF_CNT_RST_CH2 : WT; bitpos: [2]; default: 0; + * This register is used to reset the clock divider of CHANNEL2. + */ +#define RMT_REF_CNT_RST_CH2 (BIT(2)) +#define RMT_REF_CNT_RST_CH2_M (RMT_REF_CNT_RST_CH2_V << RMT_REF_CNT_RST_CH2_S) +#define RMT_REF_CNT_RST_CH2_V 0x00000001U +#define RMT_REF_CNT_RST_CH2_S 2 +/** RMT_REF_CNT_RST_CH3 : WT; bitpos: [3]; default: 0; + * This register is used to reset the clock divider of CHANNEL3. + */ +#define RMT_REF_CNT_RST_CH3 (BIT(3)) +#define RMT_REF_CNT_RST_CH3_M (RMT_REF_CNT_RST_CH3_V << RMT_REF_CNT_RST_CH3_S) +#define RMT_REF_CNT_RST_CH3_V 0x00000001U +#define RMT_REF_CNT_RST_CH3_S 3 + +/** RMT_DATE_REG register + * RMT version register + */ +#define RMT_DATE_REG (DR_REG_RMT_BASE + 0xcc) +/** RMT_RMT_DATE : R/W; bitpos: [27:0]; default: 34636307; + * This is the version register. + */ +#define RMT_RMT_DATE 0x0FFFFFFFU +#define RMT_RMT_DATE_M (RMT_RMT_DATE_V << RMT_RMT_DATE_S) +#define RMT_RMT_DATE_V 0x0FFFFFFFU +#define RMT_RMT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/rmt_struct.h b/components/soc/esp32c6/include/soc/rmt_struct.h new file mode 100644 index 0000000000..0f67600841 --- /dev/null +++ b/components/soc/esp32c6/include/soc/rmt_struct.h @@ -0,0 +1,808 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: FIFO R/W registers */ +/** Type of chndata register + * The read and write data register for CHANNELn by apb fifo access. + */ +typedef union { + struct { + /** chndata : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel n via APB FIFO. + */ + uint32_t chndata:32; + }; + uint32_t val; +} rmt_chndata_reg_t; + +/** Type of chmdata register + * The read and write data register for CHANNEL$n by apb fifo access. + */ +typedef union { + struct { + /** chmdata : RO; bitpos: [31:0]; default: 0; + * Read and write data for channel $n via APB FIFO. + */ + uint32_t chmdata: 32; + }; + uint32_t val; +} rmt_chmdata_reg_t; + + +/** Group: Configuration registers */ +/** Type of chnconf0 register + * Channel n configure register 0 + */ +typedef union { + struct { + /** tx_start_chn : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNELn. + */ + uint32_t tx_start_chn:1; + /** mem_rd_rst_chn : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNELn by accessing transmitter. + */ + uint32_t mem_rd_rst_chn:1; + /** apb_mem_rst_chn : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNELn by accessing apb fifo. + */ + uint32_t apb_mem_rst_chn:1; + /** tx_conti_mode_chn : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNELn. + */ + uint32_t tx_conti_mode_chn:1; + /** mem_tx_wrap_en_chn : R/W; bitpos: [4]; default: 0; + * This is the channel n enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ + uint32_t mem_tx_wrap_en_chn:1; + /** idle_out_lv_chn : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNELn when the latter is in + * IDLE state. + */ + uint32_t idle_out_lv_chn:1; + /** idle_out_en_chn : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNELn in IDLE state. + */ + uint32_t idle_out_en_chn:1; + /** tx_stop_chn : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNELn sending data out. + */ + uint32_t tx_stop_chn:1; + /** div_cnt_chn : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNELn. + */ + uint32_t div_cnt_chn:8; + /** mem_size_chn : R/W; bitpos: [18:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNELn. + */ + uint32_t mem_size_chn:3; + uint32_t reserved_19:1; + /** carrier_eff_en_chn : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNELn. 0: Add carrier modulation on the output signal at all state for CHANNELn. + * Only valid when RMT_CARRIER_EN_CHn is 1. + */ + uint32_t carrier_eff_en_chn:1; + /** carrier_en_chn : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNELn. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ + uint32_t carrier_en_chn:1; + /** carrier_out_lv_chn : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNELn. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ + uint32_t carrier_out_lv_chn:1; + /** afifo_rst_chn : WT; bitpos: [23]; default: 0; + * Reserved + */ + uint32_t afifo_rst_chn:1; + /** conf_update_chn : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNELn + */ + uint32_t conf_update_chn:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} rmt_chnconf0_reg_t; + +/** Type of chmconf0 register + * Channel m configure register 0 + */ +typedef union { + struct { + /** div_cnt_chm : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNELm. + */ + uint32_t div_cnt_chm:8; + /** idle_thres_chm : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ + uint32_t idle_thres_chm:15; + /** mem_size_chm : R/W; bitpos: [25:23]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNELm. + */ + uint32_t mem_size_chm:3; + uint32_t reserved_26:2; + /** carrier_en_chm : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNELm. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ + uint32_t carrier_en_chm:1; + /** carrier_out_lv_chm : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNELm. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ + uint32_t carrier_out_lv_chm:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} rmt_chmconf0_reg_t; + +/** Type of chmconf1 register + * Channel m configure register 1 + */ +typedef union { + struct { + /** rx_en_chm : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNELm. + */ + uint32_t rx_en_chm:1; + /** mem_wr_rst_chm : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNELm by accessing receiver. + */ + uint32_t mem_wr_rst_chm:1; + /** apb_mem_rst_chm : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNELm by accessing apb fifo. + */ + uint32_t apb_mem_rst_chm:1; + /** mem_owner_chm : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNELm's ram block. + * + * 1'h1: Receiver is using the ram. + * + * 1'h0: APB bus is using the ram. + */ + uint32_t mem_owner_chm:1; + /** rx_filter_en_chm : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNELm. + */ + uint32_t rx_filter_en_chm:1; + /** rx_filter_thres_chm : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ + uint32_t rx_filter_thres_chm:8; + /** mem_rx_wrap_en_chm : R/W; bitpos: [13]; default: 0; + * This is the channel m enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ + uint32_t mem_rx_wrap_en_chm:1; + /** afifo_rst_chm : WT; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t afifo_rst_chm:1; + /** conf_update_chm : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNELm + */ + uint32_t conf_update_chm:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} rmt_chmconf1_reg_t; + +/** Type of sys_conf register + * RMT apb configuration register + */ +typedef union { + struct { + /** apb_fifo_mask : R/W; bitpos: [0]; default: 0; + * 1'h1: access memory directly. 1'h0: access memory by FIFO. + */ + uint32_t apb_fifo_mask:1; + /** mem_clk_force_on : R/W; bitpos: [1]; default: 0; + * Set this bit to enable the clock for RMT memory. + */ + uint32_t mem_clk_force_on:1; + /** mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to power down RMT memory. + */ + uint32_t mem_force_pd:1; + /** mem_force_pu : R/W; bitpos: [3]; default: 0; + * 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory + * when RMT is in light sleep mode. + */ + uint32_t mem_force_pu:1; + /** sclk_div_num : R/W; bitpos: [11:4]; default: 1; + * the integral part of the fractional divisor + */ + uint32_t sclk_div_num:8; + /** sclk_div_a : R/W; bitpos: [17:12]; default: 0; + * the numerator of the fractional part of the fractional divisor + */ + uint32_t sclk_div_a:6; + /** sclk_div_b : R/W; bitpos: [23:18]; default: 0; + * the denominator of the fractional part of the fractional divisor + */ + uint32_t sclk_div_b:6; + /** sclk_sel : R/W; bitpos: [25:24]; default: 1; + * choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL + */ + uint32_t sclk_sel:2; + /** sclk_active : R/W; bitpos: [26]; default: 1; + * rmt_sclk switch + */ + uint32_t sclk_active:1; + uint32_t reserved_27:4; + /** clk_en : R/W; bitpos: [31]; default: 0; + * RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: + * Power down the drive clock of registers + */ + uint32_t clk_en:1; + }; + uint32_t val; +} rmt_sys_conf_reg_t; + +/** Type of ref_cnt_rst register + * RMT clock divider reset register + */ +typedef union { + struct { + /** ref_cnt_rst_ch0 : WT; bitpos: [0]; default: 0; + * This register is used to reset the clock divider of CHANNEL0. + */ + uint32_t ref_cnt_rst_ch0:1; + /** ref_cnt_rst_ch1 : WT; bitpos: [1]; default: 0; + * This register is used to reset the clock divider of CHANNEL1. + */ + uint32_t ref_cnt_rst_ch1:1; + /** ref_cnt_rst_ch2 : WT; bitpos: [2]; default: 0; + * This register is used to reset the clock divider of CHANNEL2. + */ + uint32_t ref_cnt_rst_ch2:1; + /** ref_cnt_rst_ch3 : WT; bitpos: [3]; default: 0; + * This register is used to reset the clock divider of CHANNEL3. + */ + uint32_t ref_cnt_rst_ch3:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} rmt_ref_cnt_rst_reg_t; + + +/** Group: Status registers */ +/** Type of chnstatus register + * Channel n status register + */ +typedef union { + struct { + /** mem_raddr_ex_chn : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNELn is + * using the RAM. + */ + uint32_t mem_raddr_ex_chn:9; + /** state_chn : RO; bitpos: [11:9]; default: 0; + * This register records the FSM status of CHANNELn. + */ + uint32_t state_chn:3; + /** apb_mem_waddr_chn : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ + uint32_t apb_mem_waddr_chn:9; + /** apb_mem_rd_err_chn : RO; bitpos: [21]; default: 0; + * This status bit will be set if the offset address out of memory size when reading + * via APB bus. + */ + uint32_t apb_mem_rd_err_chn:1; + /** mem_empty_chn : RO; bitpos: [22]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ + uint32_t mem_empty_chn:1; + /** apb_mem_wr_err_chn : RO; bitpos: [23]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ + uint32_t apb_mem_wr_err_chn:1; + /** apb_mem_raddr_chn : RO; bitpos: [31:24]; default: 0; + * This register records the memory address offset when reading RAM over APB bus. + */ + uint32_t apb_mem_raddr_chn:8; + }; + uint32_t val; +} rmt_chnstatus_reg_t; + +/** Type of chmstatus register + * Channel m status register + */ +typedef union { + struct { + /** mem_waddr_ex_chm : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when receiver of CHANNELm is using + * the RAM. + */ + uint32_t mem_waddr_ex_chm:9; + uint32_t reserved_9:3; + /** apb_mem_raddr_chm : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when reads RAM over APB bus. + */ + uint32_t apb_mem_raddr_chm:9; + uint32_t reserved_21:1; + /** state_chm : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNELm. + */ + uint32_t state_chm:3; + /** mem_owner_err_chm : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ + uint32_t mem_owner_err_chm:1; + /** mem_full_chm : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ + uint32_t mem_full_chm:1; + /** apb_mem_rd_err_chm : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ + uint32_t apb_mem_rd_err_chm:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} rmt_chmstatus_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** ch0_tx_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmission done. + */ + uint32_t ch0_tx_end_int_raw:1; + /** ch1_tx_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmission done. + */ + uint32_t ch1_tx_end_int_raw:1; + /** ch2_rx_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when reception done. + */ + uint32_t ch2_rx_end_int_raw:1; + /** ch3_rx_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when reception done. + */ + uint32_t ch3_rx_end_int_raw:1; + /** ch0_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ + uint32_t ch0_err_int_raw:1; + /** ch1_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ + uint32_t ch1_err_int_raw:1; + /** ch2_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ + uint32_t ch2_err_int_raw:1; + /** ch3_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ + uint32_t ch3_err_int_raw:1; + /** ch0_tx_thr_event_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than + * configured value. + */ + uint32_t ch0_tx_thr_event_int_raw:1; + /** ch1_tx_thr_event_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than + * configured value. + */ + uint32_t ch1_tx_thr_event_int_raw:1; + /** ch2_rx_thr_event_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than + * configured value. + */ + uint32_t ch2_rx_thr_event_int_raw:1; + /** ch3_rx_thr_event_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than + * configured value. + */ + uint32_t ch3_rx_thr_event_int_raw:1; + /** ch0_tx_loop_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the + * configured threshold value. + */ + uint32_t ch0_tx_loop_int_raw:1; + /** ch1_tx_loop_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the + * configured threshold value. + */ + uint32_t ch1_tx_loop_int_raw:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} rmt_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** ch0_tx_end_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for CH0_TX_END_INT. + */ + uint32_t ch0_tx_end_int_st:1; + /** ch1_tx_end_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for CH1_TX_END_INT. + */ + uint32_t ch1_tx_end_int_st:1; + /** ch2_rx_end_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for CH2_RX_END_INT. + */ + uint32_t ch2_rx_end_int_st:1; + /** ch3_rx_end_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for CH3_RX_END_INT. + */ + uint32_t ch3_rx_end_int_st:1; + /** ch0_err_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ + uint32_t ch0_err_int_st:1; + /** ch1_err_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ + uint32_t ch1_err_int_st:1; + /** ch2_err_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ + uint32_t ch2_err_int_st:1; + /** ch3_err_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ + uint32_t ch3_err_int_st:1; + /** ch0_tx_thr_event_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + */ + uint32_t ch0_tx_thr_event_int_st:1; + /** ch1_tx_thr_event_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for CH1_TX_THR_EVENT_INT. + */ + uint32_t ch1_tx_thr_event_int_st:1; + /** ch2_rx_thr_event_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for CH2_RX_THR_EVENT_INT. + */ + uint32_t ch2_rx_thr_event_int_st:1; + /** ch3_rx_thr_event_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for CH3_RX_THR_EVENT_INT. + */ + uint32_t ch3_rx_thr_event_int_st:1; + /** ch0_tx_loop_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for CH0_TX_LOOP_INT. + */ + uint32_t ch0_tx_loop_int_st:1; + /** ch1_tx_loop_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for CH1_TX_LOOP_INT. + */ + uint32_t ch1_tx_loop_int_st:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} rmt_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** ch0_tx_end_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for CH0_TX_END_INT. + */ + uint32_t ch0_tx_end_int_ena:1; + /** ch1_tx_end_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for CH1_TX_END_INT. + */ + uint32_t ch1_tx_end_int_ena:1; + /** ch2_rx_end_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for CH2_RX_END_INT. + */ + uint32_t ch2_rx_end_int_ena:1; + /** ch3_rx_end_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for CH3_RX_END_INT. + */ + uint32_t ch3_rx_end_int_ena:1; + /** ch0_err_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ + uint32_t ch0_err_int_ena:1; + /** ch1_err_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ + uint32_t ch1_err_int_ena:1; + /** ch2_err_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ + uint32_t ch2_err_int_ena:1; + /** ch3_err_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ + uint32_t ch3_err_int_ena:1; + /** ch0_tx_thr_event_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for CH0_TX_THR_EVENT_INT. + */ + uint32_t ch0_tx_thr_event_int_ena:1; + /** ch1_tx_thr_event_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for CH1_TX_THR_EVENT_INT. + */ + uint32_t ch1_tx_thr_event_int_ena:1; + /** ch2_rx_thr_event_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for CH2_RX_THR_EVENT_INT. + */ + uint32_t ch2_rx_thr_event_int_ena:1; + /** ch3_rx_thr_event_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for CH3_RX_THR_EVENT_INT. + */ + uint32_t ch3_rx_thr_event_int_ena:1; + /** ch0_tx_loop_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for CH0_TX_LOOP_INT. + */ + uint32_t ch0_tx_loop_int_ena:1; + /** ch1_tx_loop_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for CH1_TX_LOOP_INT. + */ + uint32_t ch1_tx_loop_int_ena:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} rmt_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** ch0_tx_end_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear theCH0_TX_END_INT interrupt. + */ + uint32_t ch0_tx_end_int_clr:1; + /** ch1_tx_end_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear theCH1_TX_END_INT interrupt. + */ + uint32_t ch1_tx_end_int_clr:1; + /** ch2_rx_end_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear theCH2_RX_END_INT interrupt. + */ + uint32_t ch2_rx_end_int_clr:1; + /** ch3_rx_end_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear theCH3_RX_END_INT interrupt. + */ + uint32_t ch3_rx_end_int_clr:1; + /** ch0_err_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ + uint32_t ch0_err_int_clr:1; + /** ch1_err_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ + uint32_t ch1_err_int_clr:1; + /** ch2_err_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ + uint32_t ch2_err_int_clr:1; + /** ch3_err_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ + uint32_t ch3_err_int_clr:1; + /** ch0_tx_thr_event_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. + */ + uint32_t ch0_tx_thr_event_int_clr:1; + /** ch1_tx_thr_event_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. + */ + uint32_t ch1_tx_thr_event_int_clr:1; + /** ch2_rx_thr_event_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt. + */ + uint32_t ch2_rx_thr_event_int_clr:1; + /** ch3_rx_thr_event_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt. + */ + uint32_t ch3_rx_thr_event_int_clr:1; + /** ch0_tx_loop_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear theCH0_TX_LOOP_INT interrupt. + */ + uint32_t ch0_tx_loop_int_clr:1; + /** ch1_tx_loop_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear theCH1_TX_LOOP_INT interrupt. + */ + uint32_t ch1_tx_loop_int_clr:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} rmt_int_clr_reg_t; + + +/** Group: Carrier wave duty cycle registers */ +/** Type of chncarrier_duty register + * Channel n duty cycle configuration register + */ +typedef union { + struct { + /** carrier_low_chn : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNELn. + */ + uint32_t carrier_low_chn:16; + /** carrier_high_chn : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNELn. + */ + uint32_t carrier_high_chn:16; + }; + uint32_t val; +} rmt_chncarrier_duty_reg_t; + +/** Type of chm_rx_carrier_rm register + * Channel m carrier remove register + */ +typedef union { + struct { + /** carrier_low_thres_chm : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CHm + 1) for channel m. + */ + uint32_t carrier_low_thres_chm:16; + /** carrier_high_thres_chm : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CHm + 1) for channel m. + */ + uint32_t carrier_high_thres_chm:16; + }; + uint32_t val; +} rmt_chm_rx_carrier_rm_reg_t; + + +/** Group: Tx event configuration registers */ +/** Type of chn_tx_lim register + * Channel n Tx event configuration register + */ +typedef union { + struct { + /** tx_lim_chn : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNELn can send out. + */ + uint32_t tx_lim_chn:9; + /** tx_loop_num_chn : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ + uint32_t tx_loop_num_chn:10; + /** tx_loop_cnt_en_chn : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ + uint32_t tx_loop_cnt_en_chn:1; + /** loop_count_reset_chn : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ + uint32_t loop_count_reset_chn:1; + /** loop_stop_en_chn : R/W; bitpos: [21]; default: 0; + * This bit is used to enable the loop send stop function after the loop counter + * counts to loop number for CHANNELn. + */ + uint32_t loop_stop_en_chn:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} rmt_chn_tx_lim_reg_t; + +/** Type of tx_sim register + * RMT TX synchronous register + */ +typedef union { + struct { + /** tx_sim_ch0 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable CHANNEL0 to start sending data synchronously with other + * enabled channels. + */ + uint32_t tx_sim_ch0:1; + /** tx_sim_ch1 : R/W; bitpos: [1]; default: 0; + * Set this bit to enable CHANNEL1 to start sending data synchronously with other + * enabled channels. + */ + uint32_t tx_sim_ch1:1; + /** tx_sim_en : R/W; bitpos: [2]; default: 0; + * This register is used to enable multiple of channels to start sending data + * synchronously. + */ + uint32_t tx_sim_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} rmt_tx_sim_reg_t; + + +/** Group: Rx event configuration registers */ +/** Type of chm_rx_lim register + * Channel m Rx event configuration register + */ +typedef union { + struct { + /** rmt_rx_lim_chm : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNELm can receive. + */ + uint32_t rmt_rx_lim_chm:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} rmt_chm_rx_lim_reg_t; + + +/** Group: Version register */ +/** Type of date register + * RMT version register + */ +typedef union { + struct { + /** rmt_date : R/W; bitpos: [27:0]; default: 34636307; + * This is the version register. + */ + uint32_t rmt_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} rmt_date_reg_t; + + +typedef struct rmt_dev_t { + volatile rmt_chndata_reg_t chndata[2]; + volatile rmt_chmdata_reg_t chmdata[2]; + volatile rmt_chnconf0_reg_t chnconf0[2]; + volatile struct { + rmt_chmconf0_reg_t conf0; + rmt_chmconf1_reg_t conf1; + } chmconf[2]; + volatile rmt_chnstatus_reg_t chnstatus[2]; + volatile rmt_chmstatus_reg_t chmstatus[2]; + volatile rmt_int_raw_reg_t int_raw; + volatile rmt_int_st_reg_t int_st; + volatile rmt_int_ena_reg_t int_ena; + volatile rmt_int_clr_reg_t int_clr; + volatile rmt_chncarrier_duty_reg_t chncarrier_duty[2]; + volatile rmt_chm_rx_carrier_rm_reg_t chm_rx_carrier_rm[2]; + volatile rmt_chn_tx_lim_reg_t chn_tx_lim[2]; + volatile rmt_chm_rx_lim_reg_t chm_rx_lim[2]; + volatile rmt_sys_conf_reg_t sys_conf; + volatile rmt_tx_sim_reg_t tx_sim; + volatile rmt_ref_cnt_rst_reg_t ref_cnt_rst; + uint32_t reserved_074[22]; + volatile rmt_date_reg_t date; +} rmt_dev_t; + +extern rmt_dev_t RMT; + +#ifndef __cplusplus +_Static_assert(sizeof(rmt_dev_t) == 0xd0, "Invalid size of rmt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/rsa_reg.h b/components/soc/esp32c6/include/soc/rsa_reg.h new file mode 100644 index 0000000000..0faea4cde0 --- /dev/null +++ b/components/soc/esp32c6/include/soc/rsa_reg.h @@ -0,0 +1,233 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** RSA_M_MEM register + * Represents M + */ +#define RSA_M_MEM (DR_REG_RSA_BASE + 0x0) +#define RSA_M_MEM_SIZE_BYTES 16 + +/** RSA_Z_MEM register + * Represents Z + */ +#define RSA_Z_MEM (DR_REG_RSA_BASE + 0x200) +#define RSA_Z_MEM_SIZE_BYTES 16 + +/** RSA_Y_MEM register + * Represents Y + */ +#define RSA_Y_MEM (DR_REG_RSA_BASE + 0x400) +#define RSA_Y_MEM_SIZE_BYTES 16 + +/** RSA_X_MEM register + * Represents X + */ +#define RSA_X_MEM (DR_REG_RSA_BASE + 0x600) +#define RSA_X_MEM_SIZE_BYTES 16 + +/** RSA_M_PRIME_REG register + * Represents M' + */ +#define RSA_M_PRIME_REG (DR_REG_RSA_BASE + 0x800) +/** RSA_M_PRIME : R/W; bitpos: [31:0]; default: 0; + * Represents M' + */ +#define RSA_M_PRIME 0xFFFFFFFFU +#define RSA_M_PRIME_M (RSA_M_PRIME_V << RSA_M_PRIME_S) +#define RSA_M_PRIME_V 0xFFFFFFFFU +#define RSA_M_PRIME_S 0 + +/** RSA_MODE_REG register + * Configures RSA length + */ +#define RSA_MODE_REG (DR_REG_RSA_BASE + 0x804) +/** RSA_MODE : R/W; bitpos: [6:0]; default: 0; + * Configures the RSA length. + */ +#define RSA_MODE 0x0000007FU +#define RSA_MODE_M (RSA_MODE_V << RSA_MODE_S) +#define RSA_MODE_V 0x0000007FU +#define RSA_MODE_S 0 + +/** RSA_QUERY_CLEAN_REG register + * RSA clean register + */ +#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808) +/** RSA_QUERY_CLEAN : RO; bitpos: [0]; default: 0; + * Represents whether or not the RSA memory completes initialization. + * + * 0: Not complete + * + * 1: Completed + * + */ +#define RSA_QUERY_CLEAN (BIT(0)) +#define RSA_QUERY_CLEAN_M (RSA_QUERY_CLEAN_V << RSA_QUERY_CLEAN_S) +#define RSA_QUERY_CLEAN_V 0x00000001U +#define RSA_QUERY_CLEAN_S 0 + +/** RSA_SET_START_MODEXP_REG register + * Starts modular exponentiation + */ +#define RSA_SET_START_MODEXP_REG (DR_REG_RSA_BASE + 0x80c) +/** RSA_SET_START_MODEXP : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the modular exponentiation. + * + * 0: No effect + * + * 1: Start + * + */ +#define RSA_SET_START_MODEXP (BIT(0)) +#define RSA_SET_START_MODEXP_M (RSA_SET_START_MODEXP_V << RSA_SET_START_MODEXP_S) +#define RSA_SET_START_MODEXP_V 0x00000001U +#define RSA_SET_START_MODEXP_S 0 + +/** RSA_SET_START_MODMULT_REG register + * Starts modular multiplication + */ +#define RSA_SET_START_MODMULT_REG (DR_REG_RSA_BASE + 0x810) +/** RSA_SET_START_MODMULT : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the modular multiplication. + * + * 0: No effect + * + * 1: Start + * + */ +#define RSA_SET_START_MODMULT (BIT(0)) +#define RSA_SET_START_MODMULT_M (RSA_SET_START_MODMULT_V << RSA_SET_START_MODMULT_S) +#define RSA_SET_START_MODMULT_V 0x00000001U +#define RSA_SET_START_MODMULT_S 0 + +/** RSA_SET_START_MULT_REG register + * Starts multiplication + */ +#define RSA_SET_START_MULT_REG (DR_REG_RSA_BASE + 0x814) +/** RSA_SET_START_MULT : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the multiplication. + * + * 0: No effect + * + * 1: Start + * + */ +#define RSA_SET_START_MULT (BIT(0)) +#define RSA_SET_START_MULT_M (RSA_SET_START_MULT_V << RSA_SET_START_MULT_S) +#define RSA_SET_START_MULT_V 0x00000001U +#define RSA_SET_START_MULT_S 0 + +/** RSA_QUERY_IDLE_REG register + * Represents the RSA status + */ +#define RSA_QUERY_IDLE_REG (DR_REG_RSA_BASE + 0x818) +/** RSA_QUERY_IDLE : RO; bitpos: [0]; default: 0; + * Represents the RSA status. + * + * 0: Busy + * + * 1: Idle + * + */ +#define RSA_QUERY_IDLE (BIT(0)) +#define RSA_QUERY_IDLE_M (RSA_QUERY_IDLE_V << RSA_QUERY_IDLE_S) +#define RSA_QUERY_IDLE_V 0x00000001U +#define RSA_QUERY_IDLE_S 0 + +/** RSA_INT_CLR_REG register + * Clears RSA interrupt + */ +#define RSA_INT_CLR_REG (DR_REG_RSA_BASE + 0x81c) +/** RSA_CLEAR_INTERRUPT : WT; bitpos: [0]; default: 0; + * Write 1 to clear the RSA interrupt. + */ +#define RSA_CLEAR_INTERRUPT (BIT(0)) +#define RSA_CLEAR_INTERRUPT_M (RSA_CLEAR_INTERRUPT_V << RSA_CLEAR_INTERRUPT_S) +#define RSA_CLEAR_INTERRUPT_V 0x00000001U +#define RSA_CLEAR_INTERRUPT_S 0 + +/** RSA_CONSTANT_TIME_REG register + * Configures the constant_time option + */ +#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820) +/** RSA_CONSTANT_TIME : R/W; bitpos: [0]; default: 1; + * Configures the constant_time option. + * + * 0: Acceleration + * + * 1: No acceleration (default) + * + */ +#define RSA_CONSTANT_TIME (BIT(0)) +#define RSA_CONSTANT_TIME_M (RSA_CONSTANT_TIME_V << RSA_CONSTANT_TIME_S) +#define RSA_CONSTANT_TIME_V 0x00000001U +#define RSA_CONSTANT_TIME_S 0 + +/** RSA_SEARCH_ENABLE_REG register + * Configures the search option + */ +#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824) +/** RSA_SEARCH_ENABLE : R/W; bitpos: [0]; default: 0; + * Configure the search option. + * + * 0: No acceleration (default) + * + * 1: Acceleration + * + * This option should be used together with RSA_SEARCH_POS. + */ +#define RSA_SEARCH_ENABLE (BIT(0)) +#define RSA_SEARCH_ENABLE_M (RSA_SEARCH_ENABLE_V << RSA_SEARCH_ENABLE_S) +#define RSA_SEARCH_ENABLE_V 0x00000001U +#define RSA_SEARCH_ENABLE_S 0 + +/** RSA_SEARCH_POS_REG register + * Configures the search position + */ +#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828) +/** RSA_SEARCH_POS : R/W; bitpos: [11:0]; default: 0; + * Configures the starting address to start search. This field should be used together + * with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high. + */ +#define RSA_SEARCH_POS 0x00000FFFU +#define RSA_SEARCH_POS_M (RSA_SEARCH_POS_V << RSA_SEARCH_POS_S) +#define RSA_SEARCH_POS_V 0x00000FFFU +#define RSA_SEARCH_POS_S 0 + +/** RSA_INT_ENA_REG register + * Enables the RSA interrupt + */ +#define RSA_INT_ENA_REG (DR_REG_RSA_BASE + 0x82c) +/** RSA_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable the RSA interrupt. + */ +#define RSA_INT_ENA (BIT(0)) +#define RSA_INT_ENA_M (RSA_INT_ENA_V << RSA_INT_ENA_S) +#define RSA_INT_ENA_V 0x00000001U +#define RSA_INT_ENA_S 0 + +/** RSA_DATE_REG register + * Version control register + */ +#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x830) +/** RSA_DATE : R/W; bitpos: [29:0]; default: 538969624; + * Version control register. + */ +#define RSA_DATE 0x3FFFFFFFU +#define RSA_DATE_M (RSA_DATE_V << RSA_DATE_S) +#define RSA_DATE_V 0x3FFFFFFFU +#define RSA_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/rsa_struct.h b/components/soc/esp32c6/include/soc/rsa_struct.h new file mode 100644 index 0000000000..9d67e0c790 --- /dev/null +++ b/components/soc/esp32c6/include/soc/rsa_struct.h @@ -0,0 +1,273 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Memory */ + +/** Group: Control / Configuration Registers */ +/** Type of m_prime register + * Represents M' + */ +typedef union { + struct { + /** m_prime : R/W; bitpos: [31:0]; default: 0; + * Represents M' + */ + uint32_t m_prime:32; + }; + uint32_t val; +} rsa_m_prime_reg_t; + +/** Type of mode register + * Configures RSA length + */ +typedef union { + struct { + /** mode : R/W; bitpos: [6:0]; default: 0; + * Configures the RSA length. + */ + uint32_t mode:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} rsa_mode_reg_t; + +/** Type of set_start_modexp register + * Starts modular exponentiation + */ +typedef union { + struct { + /** set_start_modexp : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the modular exponentiation. + * + * 0: No effect + * + * 1: Start + * + */ + uint32_t set_start_modexp:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_set_start_modexp_reg_t; + +/** Type of set_start_modmult register + * Starts modular multiplication + */ +typedef union { + struct { + /** set_start_modmult : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the modular multiplication. + * + * 0: No effect + * + * 1: Start + * + */ + uint32_t set_start_modmult:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_set_start_modmult_reg_t; + +/** Type of set_start_mult register + * Starts multiplication + */ +typedef union { + struct { + /** set_start_mult : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the multiplication. + * + * 0: No effect + * + * 1: Start + * + */ + uint32_t set_start_mult:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_set_start_mult_reg_t; + +/** Type of query_idle register + * Represents the RSA status + */ +typedef union { + struct { + /** query_idle : RO; bitpos: [0]; default: 0; + * Represents the RSA status. + * + * 0: Busy + * + * 1: Idle + * + */ + uint32_t query_idle:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_query_idle_reg_t; + +/** Type of constant_time register + * Configures the constant_time option + */ +typedef union { + struct { + /** constant_time : R/W; bitpos: [0]; default: 1; + * Configures the constant_time option. + * + * 0: Acceleration + * + * 1: No acceleration (default) + * + */ + uint32_t constant_time:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_constant_time_reg_t; + +/** Type of search_enable register + * Configures the search option + */ +typedef union { + struct { + /** search_enable : R/W; bitpos: [0]; default: 0; + * Configure the search option. + * + * 0: No acceleration (default) + * + * 1: Acceleration + * + * This option should be used together with RSA_SEARCH_POS. + */ + uint32_t search_enable:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_search_enable_reg_t; + +/** Type of search_pos register + * Configures the search position + */ +typedef union { + struct { + /** search_pos : R/W; bitpos: [11:0]; default: 0; + * Configures the starting address to start search. This field should be used together + * with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high. + */ + uint32_t search_pos:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} rsa_search_pos_reg_t; + + +/** Group: Status Register */ +/** Type of query_clean register + * RSA clean register + */ +typedef union { + struct { + /** query_clean : RO; bitpos: [0]; default: 0; + * Represents whether or not the RSA memory completes initialization. + * + * 0: Not complete + * + * 1: Completed + * + */ + uint32_t query_clean:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_query_clean_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_clr register + * Clears RSA interrupt + */ +typedef union { + struct { + /** clear_interrupt : WT; bitpos: [0]; default: 0; + * Write 1 to clear the RSA interrupt. + */ + uint32_t clear_interrupt:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_int_clr_reg_t; + +/** Type of int_ena register + * Enables the RSA interrupt + */ +typedef union { + struct { + /** int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable the RSA interrupt. + */ + uint32_t int_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_int_ena_reg_t; + + +/** Group: Version Control Register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 538969624; + * Version control register. + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} rsa_date_reg_t; + + +typedef struct rsa_dev_t { + volatile uint32_t m[4]; + uint32_t reserved_010[124]; + volatile uint32_t z[4]; + uint32_t reserved_210[124]; + volatile uint32_t y[4]; + uint32_t reserved_410[124]; + volatile uint32_t x[4]; + uint32_t reserved_610[124]; + volatile rsa_m_prime_reg_t m_prime; + volatile rsa_mode_reg_t mode; + volatile rsa_query_clean_reg_t query_clean; + volatile rsa_set_start_modexp_reg_t set_start_modexp; + volatile rsa_set_start_modmult_reg_t set_start_modmult; + volatile rsa_set_start_mult_reg_t set_start_mult; + volatile rsa_query_idle_reg_t query_idle; + volatile rsa_int_clr_reg_t int_clr; + volatile rsa_constant_time_reg_t constant_time; + volatile rsa_search_enable_reg_t search_enable; + volatile rsa_search_pos_reg_t search_pos; + volatile rsa_int_ena_reg_t int_ena; + volatile rsa_date_reg_t date; +} rsa_dev_t; + +extern rsa_dev_t RSA; + +#ifndef __cplusplus +_Static_assert(sizeof(rsa_dev_t) == 0x834, "Invalid size of rsa_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/rtc.h b/components/soc/esp32c6/include/soc/rtc.h new file mode 100644 index 0000000000..af4bd822de --- /dev/null +++ b/components/soc/esp32c6/include/soc/rtc.h @@ -0,0 +1,832 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include +#include "soc/soc.h" +#include "soc/clk_tree_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file rtc.h + * @brief Low-level RTC power, clock, and sleep functions. + * + * Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral. + * RTC_CNTL peripheral handles many functions: + * - enables/disables clocks and power to various parts of the chip; this is + * done using direct register access (forcing power up or power down) or by + * allowing state machines to control power and clocks automatically + * - handles sleep and wakeup functions + * - maintains a 48-bit counter which can be used for timekeeping + * + * These functions are not thread safe, and should not be viewed as high level + * APIs. For example, while this file provides a function which can switch + * CPU frequency, this function is on its own is not sufficient to implement + * frequency switching in ESP-IDF context: some coordination with RTOS, + * peripheral drivers, and WiFi/BT stacks is also required. + * + * These functions will normally not be used in applications directly. + * ESP-IDF provides, or will provide, drivers and other facilities to use + * RTC subsystem functionality. + * + * The functions are loosely split into the following groups: + * - rtc_clk: clock switching, calibration + * - rtc_time: reading RTC counter, conversion between counter values and time + * - rtc_sleep: entry into sleep modes + * - rtc_init: initialization + */ + +#define MHZ (1000000) + +#define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) +#define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12) +#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) + +#define OTHER_BLOCKS_POWERUP 1 +#define OTHER_BLOCKS_WAIT 1 + +/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, + * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. + */ +#define RTC_CNTL_DBIAS_SLP 5 //sleep dig_dbias & rtc_dbias +#define RTC_CNTL_DBIAS_0V90 13 //digital voltage +#define RTC_CNTL_DBIAS_0V95 16 +#define RTC_CNTL_DBIAS_1V00 18 +#define RTC_CNTL_DBIAS_1V05 20 +#define RTC_CNTL_DBIAS_1V10 23 +#define RTC_CNTL_DBIAS_1V15 25 +#define RTC_CNTL_DBIAS_1V20 28 +#define RTC_CNTL_DBIAS_1V25 30 +#define RTC_CNTL_DBIAS_1V30 31 //voltage is about 1.34v in fact + +/* Delays for various clock sources to be enabled/switched. + * All values are in microseconds. + */ +#define SOC_DELAY_RTC_FAST_CLK_SWITCH 3 +#define SOC_DELAY_RTC_SLOW_CLK_SWITCH 300 +#define SOC_DELAY_RC_FAST_ENABLE 50 +#define SOC_DELAY_RC_FAST_DIGI_SWITCH 5 + +/* Core voltage: + * Currently, ESP32C3 never adjust its wake voltage in runtime + * Only sets dig/rtc voltage dbias at startup time + */ +#define DIG_DBIAS_80M RTC_CNTL_DBIAS_1V20 +#define DIG_DBIAS_160M RTC_CNTL_DBIAS_1V20 +#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 +#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 + +#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 +#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 +#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 +#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5 + +#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100 +#define RTC_CNTL_SCK_DCAP_DEFAULT 255 + +/* Various delays to be programmed into power control state machines */ +#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250) +#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) +#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4) +#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5) +#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1) +#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1) + +/* +set sleep_init default param +*/ +#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5 +#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 +#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_SLEEP_ON 0 +#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 +#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0 +#define RTC_CNTL_PD_CUR_SLEEP_ON 0 +#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 +#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 + +/* +The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value +storing in efuse (based on ATE 5k ECO3 chips) +*/ +#define K_RTC_MID_MUL10000 215 +#define K_DIG_MID_MUL10000 213 +#define V_RTC_MID_MUL10000 10800 +#define V_DIG_MID_MUL10000 10860 + +/** + * @brief Possible main XTAL frequency values. + * + * Enum values should be equal to frequency in MHz. + */ +typedef enum { + RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL +} rtc_xtal_freq_t; + +/** + * @brief CPU clock configuration structure + */ +typedef struct rtc_cpu_freq_config_s { + soc_cpu_clk_src_t source; //!< The clock from which CPU clock is derived + uint32_t source_freq_mhz; //!< Source clock frequency + uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div + uint32_t freq_mhz; //!< CPU clock frequency +} rtc_cpu_freq_config_t; + +#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal + +#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO +#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO + +/** + * @brief Clock source to be calibrated using rtc_clk_cal function + */ +typedef enum { + RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK + RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256 + RTC_CAL_32K_XTAL = 2, //!< External 32 kHz XTAL + RTC_CAL_INTERNAL_OSC = 3 //!< Internal 150 kHz oscillator +} rtc_cal_sel_t; + +/** + * Initialization parameters for rtc_clk_init + */ +typedef struct { + rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency + uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz + soc_rtc_fast_clk_src_t fast_clk_src : 2; //!< RTC_FAST_CLK clock source to choose + soc_rtc_slow_clk_src_t slow_clk_src : 2; //!< RTC_SLOW_CLK clock source to choose + uint32_t clk_rtc_clk_div : 8; + uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) + uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency) + uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) +} rtc_clk_config_t; + +/** + * Default initializer for rtc_clk_config_t + */ +#define RTC_CLK_CONFIG_DEFAULT() { \ + .xtal_freq = CONFIG_XTAL_FREQ, \ + .cpu_freq_mhz = 80, \ + .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \ + .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \ + .clk_rtc_clk_div = 0, \ + .clk_8m_clk_div = 0, \ + .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ + .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \ +} + +typedef struct { + uint16_t wifi_powerup_cycles : 7; + uint16_t wifi_wait_cycles : 9; + uint16_t bt_powerup_cycles : 7; + uint16_t bt_wait_cycles : 9; + uint16_t cpu_top_powerup_cycles : 7; + uint16_t cpu_top_wait_cycles : 9; + uint16_t dg_wrap_powerup_cycles : 7; + uint16_t dg_wrap_wait_cycles : 9; + uint16_t dg_peri_powerup_cycles : 7; + uint16_t dg_peri_wait_cycles : 9; +} rtc_init_config_t; + +#define RTC_INIT_CONFIG_DEFAULT() { \ + .wifi_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .wifi_wait_cycles = OTHER_BLOCKS_WAIT, \ + .bt_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .bt_wait_cycles = OTHER_BLOCKS_WAIT, \ + .cpu_top_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .cpu_top_wait_cycles = OTHER_BLOCKS_WAIT, \ + .dg_wrap_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .dg_wrap_wait_cycles = OTHER_BLOCKS_WAIT, \ + .dg_peri_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .dg_peri_wait_cycles = OTHER_BLOCKS_WAIT, \ +} + +void rtc_clk_divider_set(uint32_t div); + +void rtc_clk_8m_divider_set(uint32_t div); + +/** + * Initialize clocks and set CPU frequency + * + * @param cfg clock configuration as rtc_clk_config_t + */ +void rtc_clk_init(rtc_clk_config_t cfg); + +/** + * @brief Get main XTAL frequency + * + * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to + * rtc_clk_init function + * + * @return XTAL frequency, one of rtc_xtal_freq_t + */ +rtc_xtal_freq_t rtc_clk_xtal_freq_get(void); + +/** + * @brief Update XTAL frequency + * + * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored + * after startup. + * + * @param xtal_freq New frequency value + */ +void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq); + +/** + * @brief Enable or disable 32 kHz XTAL oscillator + * @param en true to enable, false to disable + */ +void rtc_clk_32k_enable(bool en); + +/** + * @brief Configure 32 kHz XTAL oscillator to accept external clock signal + */ +void rtc_clk_32k_enable_external(void); + +/** + * @brief Get the state of 32k XTAL oscillator + * @return true if 32k XTAL oscillator has been enabled + */ +bool rtc_clk_32k_enabled(void); + +/** + * @brief Enable 32k oscillator, configuring it for fast startup time. + * Note: to achieve higher frequency stability, rtc_clk_32k_enable function + * must be called one the 32k XTAL oscillator has started up. This function + * will initially disable the 32k XTAL oscillator, so it should not be called + * when the system is using 32k XTAL as RTC_SLOW_CLK. + * + * @param cycle Number of 32kHz cycles to bootstrap external crystal. + * If 0, no square wave will be used to bootstrap crystal oscillation. + */ +void rtc_clk_32k_bootstrap(uint32_t cycle); + +/** + * @brief Enable or disable 8 MHz internal oscillator + * + * Output from 8 MHz internal oscillator is passed into a configurable + * divider, which by default divides the input clock frequency by 256. + * Output of the divider may be used as RTC_SLOW_CLK source. + * Output of the divider is referred to in register descriptions and code as + * 8md256 or simply d256. Divider values other than 256 may be configured, but + * this facility is not currently needed, so is not exposed in the code. + * + * When 8MHz/256 divided output is not needed, the divider should be disabled + * to reduce power consumption. + * + * @param clk_8m_en true to enable 8MHz generator + * @param d256_en true to enable /256 divider + */ +void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en); + +/** + * @brief Get the state of 8 MHz internal oscillator + * @return true if the oscillator is enabled + */ +bool rtc_clk_8m_enabled(void); + +/** + * @brief Get the state of /256 divider which is applied to 8MHz clock + * @return true if the divided output is enabled + */ +bool rtc_clk_8md256_enabled(void); + +/** + * @brief Select source for RTC_SLOW_CLK + * @param clk_src clock source (one of soc_rtc_slow_clk_src_t values) + */ +void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src); + +/** + * @brief Get the RTC_SLOW_CLK source + * @return currently selected clock source (one of soc_rtc_slow_clk_src_t values) + */ +soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void); + +/** + * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz + * + * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns ~150000 + * - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768 + * - if SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 is selected, returns ~68000 + * + * rtc_clk_cal function can be used to get more precise value by comparing + * RTC_SLOW_CLK frequency to the frequency of main XTAL. + * + * @return RTC_SLOW_CLK frequency, in Hz + */ +uint32_t rtc_clk_slow_freq_get_hz(void); + +/** + * @brief Select source for RTC_FAST_CLK + * @param clk_src clock source (one of soc_rtc_fast_clk_src_t values) + */ +void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src); + +/** + * @brief Get the RTC_FAST_CLK source + * @return currently selected clock source (one of soc_rtc_fast_clk_src_t values) + */ +soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void); + +/** + * @brief Get CPU frequency config for a given frequency + * @param freq_mhz Frequency in MHz + * @param[out] out_config Output, CPU frequency configuration structure + * @return true if frequency can be obtained, false otherwise + */ +bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config); + +/** + * @brief Switch CPU frequency + * + * This function sets CPU frequency according to the given configuration + * structure. It enables PLLs, if necessary. + * + * @note This function in not intended to be called by applications in FreeRTOS + * environment. This is because it does not adjust various timers based on the + * new CPU frequency. + * + * @param config CPU frequency configuration structure + */ +void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config); + +/** + * @brief Switch CPU frequency (optimized for speed) + * + * This function is a faster equivalent of rtc_clk_cpu_freq_set_config. + * It works faster because it does not disable PLLs when switching from PLL to + * XTAL and does not enabled them when switching back. If PLL is not already + * enabled when this function is called to switch from XTAL to PLL frequency, + * or the PLL which is enabled is the wrong one, this function will fall back + * to calling rtc_clk_cpu_freq_set_config. + * + * Unlike rtc_clk_cpu_freq_set_config, this function relies on static data, + * so it is less safe to use it e.g. from a panic handler (when memory might + * be corrupted). + * + * @note This function in not intended to be called by applications in FreeRTOS + * environment. This is because it does not adjust various timers based on the + * new CPU frequency. + * + * @param config CPU frequency configuration structure + */ +void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config); + +/** + * @brief Get the currently used CPU frequency configuration + * @param[out] out_config Output, CPU frequency configuration structure + */ +void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); + +/** + * @brief Switch CPU clock source to XTAL + * + * Short form for filling in rtc_cpu_freq_config_t structure and calling + * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed. + * Assumes that XTAL frequency has been determined — don't call in startup code. + */ +void rtc_clk_cpu_freq_set_xtal(void); + +/** + * @brief Store new APB frequency value into RTC_APB_FREQ_REG + * + * This function doesn't change any hardware clocks. + * + * Functions which perform frequency switching and change APB frequency call + * this function to update the value of APB frequency stored in RTC_APB_FREQ_REG + * (one of RTC general purpose retention registers). This should not normally + * be called from application code. + * + * @param apb_freq new APB frequency, in Hz + */ +void rtc_clk_apb_freq_update(uint32_t apb_freq); + +/** + * @brief Get the current stored APB frequency. + * @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz. + */ +uint32_t rtc_clk_apb_freq_get(void); + +uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles); + +/** + * @brief Measure RTC slow clock's period, based on main XTAL frequency + * + * This function will time out and return 0 if the time for the given number + * of cycles to be counted exceeds the expected time twice. This may happen if + * 32k XTAL is being calibrated, but the oscillator has not started up (due to + * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board). + * + * @param cal_clk clock to be measured + * @param slow_clk_cycles number of slow clock cycles to average + * @return average slow clock period in microseconds, Q13.19 fixed point format, + * or 0 if calibration has timed out + */ +uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); + +/** + * @brief Measure ratio between XTAL frequency and RTC slow clock frequency + * @param cal_clk slow clock to be measured + * @param slow_clk_cycles number of slow clock cycles to average + * @return average ratio between XTAL frequency and slow clock frequency, + * Q13.19 fixed point format, or 0 if calibration has timed out. + */ +uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); + +/** + * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles + * @param time_in_us Time interval in microseconds + * @param slow_clk_period Period of slow clock in microseconds, Q13.19 + * fixed point format (as returned by rtc_slowck_cali). + * @return number of slow clock cycles + */ +uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period); + +/** + * @brief Convert time interval from RTC_SLOW_CLK to microseconds + * @param time_in_us Time interval in RTC_SLOW_CLK cycles + * @param slow_clk_period Period of slow clock in microseconds, Q13.19 + * fixed point format (as returned by rtc_slowck_cali). + * @return time interval in microseconds + */ +uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period); + +/** + * @brief Get current value of RTC counter + * + * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK + * cycles. Counter value is not writable by software. The value is not adjusted + * when switching to a different RTC_SLOW_CLK source. + * + * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute + * + * @return current value of RTC counter + */ +uint64_t rtc_time_get(void); + +uint64_t rtc_light_slp_time_get(void); + +uint64_t rtc_deep_slp_time_get(void); + +/** + * @brief Busy loop until next RTC_SLOW_CLK cycle + * + * This function returns not earlier than the next RTC_SLOW_CLK clock cycle. + * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return + * one RTC_SLOW_CLK cycle later. + */ +void rtc_clk_wait_for_slow_cycle(void); + +/** + * @brief Enable the rtc digital 8M clock + * + * This function is used to enable the digital rtc 8M clock to support peripherals. + * For enabling the analog 8M clock, using `rtc_clk_8M_enable` function above. + */ +void rtc_dig_clk8m_enable(void); + +/** + * @brief Disable the rtc digital 8M clock + * + * This function is used to disable the digital rtc 8M clock, which is only used to support peripherals. + */ +void rtc_dig_clk8m_disable(void); + +/** + * @brief Get whether the rtc digital 8M clock is enabled + */ +bool rtc_dig_8m_enabled(void); + +/** + * @brief Calculate the real clock value after the clock calibration + * + * @param cal_val Average slow clock period in microseconds, fixed point value as returned from `rtc_clk_cal` + * @return Frequency of the clock in Hz + */ +uint32_t rtc_clk_freq_cal(uint32_t cal_val); + +/** + * @brief Power down flags for rtc_sleep_pd function + */ +typedef struct { + uint32_t dig_fpu : 1; //!< Set to 1 to power UP digital part in sleep + uint32_t rtc_fpu : 1; //!< Set to 1 to power UP RTC memories in sleep + uint32_t cpu_fpu : 1; //!< Set to 1 to power UP digital memories and CPU in sleep + uint32_t i2s_fpu : 1; //!< Set to 1 to power UP I2S in sleep + uint32_t bb_fpu : 1; //!< Set to 1 to power UP WiFi in sleep + uint32_t nrx_fpu : 1; //!< Set to 1 to power UP WiFi in sleep + uint32_t fe_fpu : 1; //!< Set to 1 to power UP WiFi in sleep + uint32_t sram_fpu : 1; //!< Set to 1 to power UP SRAM in sleep + uint32_t rom_ram_fpu : 1; //!< Set to 1 to power UP ROM/IRAM0_DRAM0 in sleep +} rtc_sleep_pu_config_t; + +/** + * Initializer for rtc_sleep_pu_config_t which sets all flags to the same value + */ +#define RTC_SLEEP_PU_CONFIG_ALL(val) {\ + .dig_fpu = (val), \ + .rtc_fpu = (val), \ + .cpu_fpu = (val), \ + .i2s_fpu = (val), \ + .bb_fpu = (val), \ + .nrx_fpu = (val), \ + .fe_fpu = (val), \ + .sram_fpu = (val), \ + .rom_ram_fpu = (val), \ +} + +void rtc_sleep_pu(rtc_sleep_pu_config_t cfg); + +/** + * @brief sleep configuration for rtc_sleep_init function + */ +typedef struct { + uint32_t lslp_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (digital domain memory) + uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used) + uint32_t rtc_fastmem_pd_en : 1; //!< power down RTC fast memory + uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory + uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals + uint32_t wifi_pd_en : 1; //!< power down WiFi + uint32_t bt_pd_en : 1; //!< power down BT + uint32_t cpu_pd_en : 1; //!< power down CPU, but not restart when lightsleep. + uint32_t int_8m_pd_en : 1; //!< Power down Internal 8M oscillator + uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals + uint32_t deep_slp : 1; //!< power down digital domain + uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode + uint32_t dig_dbias_wak : 5; //!< set bias for digital domain, in active mode + uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode + uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode + uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode + uint32_t dbg_atten_monitor : 4; //!< voltage parameter, in monitor mode + uint32_t bias_sleep_monitor : 1; //!< circuit control parameter, in monitor mode + uint32_t dbg_atten_slp : 4; //!< voltage parameter, in sleep mode + uint32_t bias_sleep_slp : 1; //!< circuit control parameter, in sleep mode + uint32_t pd_cur_monitor : 1; //!< circuit control parameter, in monitor mode + uint32_t pd_cur_slp : 1; //!< circuit control parameter, in sleep mode + uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator + uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep + uint32_t deep_slp_reject : 1; //!< enable deep sleep reject + uint32_t light_slp_reject : 1; //!< enable light sleep reject +} rtc_sleep_config_t; + +#define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain) +#define RTC_SLEEP_PD_RTC_PERIPH BIT(1) //!< Power down RTC peripherals +#define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory +#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) //!< Power down RTC FAST memory +#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU +#define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator +#define RTC_SLEEP_PD_WIFI BIT(6) //!< Power down WIFI +#define RTC_SLEEP_PD_BT BIT(7) //!< Power down BT +#define RTC_SLEEP_PD_CPU BIT(8) //!< Power down CPU when in lightsleep, but not restart +#define RTC_SLEEP_PD_DIG_PERIPH BIT(9) //!< Power down DIG peripherals +#define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 8M oscillator +#define RTC_SLEEP_PD_XTAL BIT(11) //!< Power down main XTAL + +//These flags are not power domains, but will affect some sleep parameters +#define RTC_SLEEP_DIG_USE_8M BIT(16) +#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17) +#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature + +/** + * Default initializer for rtc_sleep_config_t + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use) based on a combination of RTC_SLEEP_PD_x flags. + * + * @param RTC_SLEEP_PD_x flags combined using bitwise OR + */ +void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config); + +/** + * @brief Prepare the chip to enter sleep mode + * + * This function configures various power control state machines to handle + * entry into light sleep or deep sleep mode, switches APB and CPU clock source + * (usually to XTAL), and sets bias voltages for digital and RTC power domains. + * + * This function does not actually enter sleep mode; this is done using + * rtc_sleep_start function. Software may do some other actions between + * rtc_sleep_init and rtc_sleep_start, such as set wakeup timer and configure + * wakeup sources. + * @param cfg sleep mode configuration + */ +void rtc_sleep_init(rtc_sleep_config_t cfg); + +/** + * @brief Low level initialize for rtc state machine waiting cycles after waking up + * + * This function configures the cycles chip need to wait for internal 8MHz + * oscillator and external 40MHz crystal. As we configure fixed time for waiting + * crystal, we need to pass period to calculate cycles. Now this function only + * used in lightsleep mode. + * + * @param slowclk_period re-calibrated slow clock period + */ +void rtc_sleep_low_init(uint32_t slowclk_period); + +/** + * @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source + * @param t value of RTC counter at which wakeup from sleep will happen; + * only the lower 48 bits are used + */ +void rtc_sleep_set_wakeup_time(uint64_t t); + +#define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup +#define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup +#define RTC_WIFI_TRIG_EN BIT(5) //!< WIFI wakeup (light sleep only) +#define RTC_UART0_TRIG_EN BIT(6) //!< UART0 wakeup (light sleep only) +#define RTC_UART1_TRIG_EN BIT(7) //!< UART1 wakeup (light sleep only) +#define RTC_BT_TRIG_EN BIT(10) //!< BT wakeup (light sleep only) +#define RTC_XTAL32K_DEAD_TRIG_EN BIT(12) +#define RTC_USB_TRIG_EN BIT(14) +#define RTC_BROWNOUT_DET_TRIG_EN BIT(16) + +/** + * RTC_SLEEP_REJECT_MASK records sleep reject sources supported by chip + */ +#define RTC_SLEEP_REJECT_MASK (RTC_GPIO_TRIG_EN | \ + RTC_TIMER_TRIG_EN | \ + RTC_WIFI_TRIG_EN | \ + RTC_UART0_TRIG_EN | \ + RTC_UART1_TRIG_EN | \ + RTC_BT_TRIG_EN | \ + RTC_XTAL32K_DEAD_TRIG_EN | \ + RTC_USB_TRIG_EN | \ + RTC_BROWNOUT_DET_TRIG_EN) + +/** + * @brief Enter deep or light sleep mode + * + * This function enters the sleep mode previously configured using rtc_sleep_init + * function. Before entering sleep, software should configure wake up sources + * appropriately (set up GPIO wakeup registers, timer wakeup registers, + * and so on). + * + * If deep sleep mode was configured using rtc_sleep_init, and sleep is not + * rejected by hardware (based on reject_opt flags), this function never returns. + * When the chip wakes up from deep sleep, CPU is reset and execution starts + * from ROM bootloader. + * + * If light sleep mode was configured using rtc_sleep_init, this function + * returns on wakeup, or if sleep is rejected by hardware. + * + * @param wakeup_opt bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags + * combined with OR) + * @param reject_opt bit mask of sleep reject reasons: + * - RTC_CNTL_GPIO_REJECT_EN + * - RTC_CNTL_SDIO_REJECT_EN + * These flags are used to prevent entering sleep when e.g. + * an external host is communicating via SDIO slave + * @return non-zero if sleep was rejected by hardware + */ +uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu); + +/** + * @brief Enter deep sleep mode + * + * Similar to rtc_sleep_start(), but additionally uses hardware to calculate the CRC value + * of RTC FAST memory. On wake, this CRC is used to determine if a deep sleep wake + * stub is valid to execute (if a wake address is set). + * + * No RAM is accessed while calculating the CRC and going into deep sleep, which makes + * this function safe to use even if the caller's stack is in RTC FAST memory. + * + * @note If no deep sleep wake stub address is set then calling rtc_sleep_start() will + * have the same effect and takes less time as CRC calculation is skipped. + * + * @note This function should only be called after rtc_sleep_init() has been called to + * configure the system for deep sleep. + * + * @param wakeup_opt - same as for rtc_sleep_start + * @param reject_opt - same as for rtc_sleep_start + * + * @return non-zero if sleep was rejected by hardware + */ +uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt); + +/** + * RTC power and clock control initialization settings + */ +typedef struct { + uint32_t ck8m_wait : 8; //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready + uint32_t xtal_wait : 8; //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready + uint32_t pll_wait : 8; //!< Number of rtc_fast_clk cycles to wait for PLL to be ready + uint32_t clkctl_init : 1; //!< Perform clock control related initialization + uint32_t pwrctl_init : 1; //!< Perform power control related initialization + uint32_t rtc_dboost_fpd : 1; //!< Force power down RTC_DBOOST + uint32_t xtal_fpu : 1; + uint32_t bbpll_fpu : 1; + uint32_t cpu_waiti_clk_gate : 1; + uint32_t cali_ocode : 1; //!< Calibrate Ocode to make bangap voltage more precise. +} rtc_config_t; + +/** + * Default initializer of rtc_config_t. + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use). + */ +#define RTC_CONFIG_DEFAULT() {\ + .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \ + .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \ + .pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \ + .clkctl_init = 1, \ + .pwrctl_init = 1, \ + .rtc_dboost_fpd = 1, \ + .xtal_fpu = 0, \ + .bbpll_fpu = 0, \ + .cpu_waiti_clk_gate = 1, \ + .cali_ocode = 0\ +} + +/** + * Initialize RTC clock and power control related functions + * @param cfg configuration options as rtc_config_t + */ +void rtc_init(rtc_config_t cfg); + +/** + * Structure describing vddsdio configuration + */ +typedef struct { + uint32_t force : 1; //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins. + uint32_t enable : 1; //!< Enable VDDSDIO regulator + uint32_t tieh : 1; //!< Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V + uint32_t drefh : 2; //!< Tuning parameter for VDDSDIO regulator + uint32_t drefm : 2; //!< Tuning parameter for VDDSDIO regulator + uint32_t drefl : 2; //!< Tuning parameter for VDDSDIO regulator +} rtc_vddsdio_config_t; + +/** + * Get current VDDSDIO configuration + * If VDDSDIO configuration is overridden by RTC, get values from RTC + * Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE + * Otherwise, use default values and the level of MTDI bootstrapping pin. + * @return currently used VDDSDIO configuration + */ +rtc_vddsdio_config_t rtc_vddsdio_get_config(void); + +/** + * Set new VDDSDIO configuration using RTC registers. + * If config.force == 1, this overrides configuration done using bootstrapping + * pins and EFUSE. + * + * @param config new VDDSDIO configuration + */ +void rtc_vddsdio_set_config(rtc_vddsdio_config_t config); + + +// -------------------------- CLOCK TREE DEFS ALIAS ---------------------------- +// **WARNING**: The following are only for backwards compatibility. +// Please use the declarations in soc/clk_tree_defs.h instead. +/** + * @brief CPU clock source + */ +typedef soc_cpu_clk_src_t rtc_cpu_freq_src_t; +#define RTC_CPU_FREQ_SRC_XTAL SOC_CPU_CLK_SRC_XTAL //!< XTAL +#define RTC_CPU_FREQ_SRC_PLL SOC_CPU_CLK_SRC_PLL //!< PLL (480M or 320M) +#define RTC_CPU_FREQ_SRC_8M SOC_CPU_CLK_SRC_RC_FAST //!< Internal 17.5M RTC oscillator + +/** + * @brief RTC SLOW_CLK frequency values + */ +typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t; +#define RTC_SLOW_FREQ_RTC SOC_RTC_SLOW_CLK_SRC_RC_SLOW //!< Internal 150 kHz RC oscillator +#define RTC_SLOW_FREQ_32K_XTAL SOC_RTC_SLOW_CLK_SRC_XTAL32K //!< External 32 kHz XTAL +#define RTC_SLOW_FREQ_8MD256 SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 //!< Internal 17.5 MHz RC oscillator, divided by 256 + +/** + * @brief RTC FAST_CLK frequency values + */ +typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t; +#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2 +#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 17.5 MHz RC oscillator + +/* Alias of frequency related macros */ +#define RTC_FAST_CLK_FREQ_APPROX SOC_CLK_RC_FAST_FREQ_APPROX +#define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX +#define RTC_SLOW_CLK_FREQ_150K SOC_CLK_RC_SLOW_FREQ_APPROX +#define RTC_SLOW_CLK_FREQ_8MD256 SOC_CLK_RC_FAST_D256_FREQ_APPROX +#define RTC_SLOW_CLK_FREQ_32K SOC_CLK_XTAL32K_FREQ_APPROX + +/* Alias of deprecated function names */ +#define rtc_clk_slow_freq_set(slow_freq) rtc_clk_slow_src_set(slow_freq) +#define rtc_clk_slow_freq_get() rtc_clk_slow_src_get() +#define rtc_clk_fast_freq_set(fast_freq) rtc_clk_fast_src_set(fast_freq) +#define rtc_clk_fast_freq_get() rtc_clk_fast_src_get() + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/sha_reg.h b/components/soc/esp32c6/include/soc/sha_reg.h new file mode 100644 index 0000000000..265f510472 --- /dev/null +++ b/components/soc/esp32c6/include/soc/sha_reg.h @@ -0,0 +1,172 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SHA_MODE_REG register + * Initial configuration register. + */ +#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0) +/** SHA_MODE : R/W; bitpos: [2:0]; default: 0; + * Sha mode. + */ +#define SHA_MODE 0x00000007U +#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S) +#define SHA_MODE_V 0x00000007U +#define SHA_MODE_S 0 + +/** SHA_T_STRING_REG register + * SHA 512/t configuration register 0. + */ +#define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4) +/** SHA_T_STRING : R/W; bitpos: [31:0]; default: 0; + * Sha t_string (used if and only if mode == SHA_512/t). + */ +#define SHA_T_STRING 0xFFFFFFFFU +#define SHA_T_STRING_M (SHA_T_STRING_V << SHA_T_STRING_S) +#define SHA_T_STRING_V 0xFFFFFFFFU +#define SHA_T_STRING_S 0 + +/** SHA_T_LENGTH_REG register + * SHA 512/t configuration register 1. + */ +#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8) +/** SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0; + * Sha t_length (used if and only if mode == SHA_512/t). + */ +#define SHA_T_LENGTH 0x0000003FU +#define SHA_T_LENGTH_M (SHA_T_LENGTH_V << SHA_T_LENGTH_S) +#define SHA_T_LENGTH_V 0x0000003FU +#define SHA_T_LENGTH_S 0 + +/** SHA_DMA_BLOCK_NUM_REG register + * DMA configuration register 0. + */ +#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc) +/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0; + * Dma-sha block number. + */ +#define SHA_DMA_BLOCK_NUM 0x0000003FU +#define SHA_DMA_BLOCK_NUM_M (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S) +#define SHA_DMA_BLOCK_NUM_V 0x0000003FU +#define SHA_DMA_BLOCK_NUM_S 0 + +/** SHA_START_REG register + * Typical SHA configuration register 0. + */ +#define SHA_START_REG (DR_REG_SHA_BASE + 0x10) +/** SHA_START : RO; bitpos: [31:1]; default: 0; + * Reserved. + */ +#define SHA_START 0x7FFFFFFFU +#define SHA_START_M (SHA_START_V << SHA_START_S) +#define SHA_START_V 0x7FFFFFFFU +#define SHA_START_S 1 + +/** SHA_CONTINUE_REG register + * Typical SHA configuration register 1. + */ +#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14) +/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0; + * Reserved. + */ +#define SHA_CONTINUE 0x7FFFFFFFU +#define SHA_CONTINUE_M (SHA_CONTINUE_V << SHA_CONTINUE_S) +#define SHA_CONTINUE_V 0x7FFFFFFFU +#define SHA_CONTINUE_S 1 + +/** SHA_BUSY_REG register + * Busy register. + */ +#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18) +/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0; + * Sha busy state. 1'b0: idle. 1'b1: busy. + */ +#define SHA_BUSY_STATE (BIT(0)) +#define SHA_BUSY_STATE_M (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S) +#define SHA_BUSY_STATE_V 0x00000001U +#define SHA_BUSY_STATE_S 0 + +/** SHA_DMA_START_REG register + * DMA configuration register 1. + */ +#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c) +/** SHA_DMA_START : WO; bitpos: [0]; default: 0; + * Start dma-sha. + */ +#define SHA_DMA_START (BIT(0)) +#define SHA_DMA_START_M (SHA_DMA_START_V << SHA_DMA_START_S) +#define SHA_DMA_START_V 0x00000001U +#define SHA_DMA_START_S 0 + +/** SHA_DMA_CONTINUE_REG register + * DMA configuration register 2. + */ +#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20) +/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0; + * Continue dma-sha. + */ +#define SHA_DMA_CONTINUE (BIT(0)) +#define SHA_DMA_CONTINUE_M (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S) +#define SHA_DMA_CONTINUE_V 0x00000001U +#define SHA_DMA_CONTINUE_S 0 + +/** SHA_CLEAR_IRQ_REG register + * Interrupt clear register. + */ +#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24) +/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0; + * Clear sha interrupt. + */ +#define SHA_CLEAR_INTERRUPT (BIT(0)) +#define SHA_CLEAR_INTERRUPT_M (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S) +#define SHA_CLEAR_INTERRUPT_V 0x00000001U +#define SHA_CLEAR_INTERRUPT_S 0 + +/** SHA_IRQ_ENA_REG register + * Interrupt enable register. + */ +#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28) +/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0; + * Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable. + */ +#define SHA_INTERRUPT_ENA (BIT(0)) +#define SHA_INTERRUPT_ENA_M (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S) +#define SHA_INTERRUPT_ENA_V 0x00000001U +#define SHA_INTERRUPT_ENA_S 0 + +/** SHA_DATE_REG register + * Date register. + */ +#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c) +/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713; + * Sha date information/ sha version information. + */ +#define SHA_DATE 0x3FFFFFFFU +#define SHA_DATE_M (SHA_DATE_V << SHA_DATE_S) +#define SHA_DATE_V 0x3FFFFFFFU +#define SHA_DATE_S 0 + +/** SHA_H_MEM register + * Sha H memory which contains intermediate hash or finial hash. + */ +#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40) +#define SHA_H_MEM_SIZE_BYTES 64 + +/** SHA_M_MEM register + * Sha M memory which contains message. + */ +#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80) +#define SHA_M_MEM_SIZE_BYTES 64 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/sha_struct.h b/components/soc/esp32c6/include/soc/sha_struct.h new file mode 100644 index 0000000000..f6aa1726ac --- /dev/null +++ b/components/soc/esp32c6/include/soc/sha_struct.h @@ -0,0 +1,216 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of mode register + * Initial configuration register. + */ +typedef union { + struct { + /** mode : R/W; bitpos: [2:0]; default: 0; + * Sha mode. + */ + uint32_t mode:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} sha_mode_reg_t; + +/** Type of t_string register + * SHA 512/t configuration register 0. + */ +typedef union { + struct { + /** t_string : R/W; bitpos: [31:0]; default: 0; + * Sha t_string (used if and only if mode == SHA_512/t). + */ + uint32_t t_string:32; + }; + uint32_t val; +} sha_t_string_reg_t; + +/** Type of t_length register + * SHA 512/t configuration register 1. + */ +typedef union { + struct { + /** t_length : R/W; bitpos: [5:0]; default: 0; + * Sha t_length (used if and only if mode == SHA_512/t). + */ + uint32_t t_length:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} sha_t_length_reg_t; + +/** Type of dma_block_num register + * DMA configuration register 0. + */ +typedef union { + struct { + /** dma_block_num : R/W; bitpos: [5:0]; default: 0; + * Dma-sha block number. + */ + uint32_t dma_block_num:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} sha_dma_block_num_reg_t; + +/** Type of start register + * Typical SHA configuration register 0. + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** start : RO; bitpos: [31:1]; default: 0; + * Reserved. + */ + uint32_t start:31; + }; + uint32_t val; +} sha_start_reg_t; + +/** Type of continue register + * Typical SHA configuration register 1. + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** conti : RO; bitpos: [31:1]; default: 0; + * Reserved. + */ + uint32_t conti:31; + }; + uint32_t val; +} sha_continue_reg_t; + +/** Type of dma_start register + * DMA configuration register 1. + */ +typedef union { + struct { + /** dma_start : WO; bitpos: [0]; default: 0; + * Start dma-sha. + */ + uint32_t dma_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_dma_start_reg_t; + +/** Type of dma_continue register + * DMA configuration register 2. + */ +typedef union { + struct { + /** dma_continue : WO; bitpos: [0]; default: 0; + * Continue dma-sha. + */ + uint32_t dma_continue:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_dma_continue_reg_t; + + +/** Group: Status Register */ +/** Type of busy register + * Busy register. + */ +typedef union { + struct { + /** busy_state : RO; bitpos: [0]; default: 0; + * Sha busy state. 1'b0: idle. 1'b1: busy. + */ + uint32_t busy_state:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_busy_reg_t; + + +/** Group: Interrupt Register */ +/** Type of clear_irq register + * Interrupt clear register. + */ +typedef union { + struct { + /** clear_interrupt : WO; bitpos: [0]; default: 0; + * Clear sha interrupt. + */ + uint32_t clear_interrupt:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_clear_irq_reg_t; + +/** Type of irq_ena register + * Interrupt enable register. + */ +typedef union { + struct { + /** interrupt_ena : R/W; bitpos: [0]; default: 0; + * Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable. + */ + uint32_t interrupt_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_irq_ena_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 538972713; + * Sha date information/ sha version information. + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} sha_date_reg_t; + + +/** Group: memory type */ + +typedef struct sha_dev_t { + volatile sha_mode_reg_t mode; + volatile sha_t_string_reg_t t_string; + volatile sha_t_length_reg_t t_length; + volatile sha_dma_block_num_reg_t dma_block_num; + volatile sha_start_reg_t start; + volatile sha_continue_reg_t conti; + volatile sha_busy_reg_t busy; + volatile sha_dma_start_reg_t dma_start; + volatile sha_dma_continue_reg_t dma_continue; + volatile sha_clear_irq_reg_t clear_irq; + volatile sha_irq_ena_reg_t irq_ena; + volatile sha_date_reg_t date; + uint32_t reserved_030[4]; + volatile uint32_t h[16]; + volatile uint32_t m[16]; +} sha_dev_t; + +extern sha_dev_t SHA; + +#ifndef __cplusplus +_Static_assert(sizeof(sha_dev_t) == 0xc0, "Invalid size of sha_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/slc_reg.h b/components/soc/esp32c6/include/soc/slc_reg.h new file mode 100644 index 0000000000..7d3a9ce6ef --- /dev/null +++ b/components/soc/esp32c6/include/soc/slc_reg.h @@ -0,0 +1,4301 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SDIO_SLCCONF0_REG register + * ******* Description *********** + */ +#define SDIO_SLCCONF0_REG (DR_REG_SLC_BASE + 0x0) +/** SDIO_SLC0_TX_RST : R/W; bitpos: [0]; default: 0; + * Set 1 to reset tx fsm in dma slc0. + */ +#define SDIO_SLC0_TX_RST (BIT(0)) +#define SDIO_SLC0_TX_RST_M (SDIO_SLC0_TX_RST_V << SDIO_SLC0_TX_RST_S) +#define SDIO_SLC0_TX_RST_V 0x00000001U +#define SDIO_SLC0_TX_RST_S 0 +/** SDIO_SLC0_RX_RST : R/W; bitpos: [1]; default: 0; + * Set 1 to reset rx fsm in dma slc0. + */ +#define SDIO_SLC0_RX_RST (BIT(1)) +#define SDIO_SLC0_RX_RST_M (SDIO_SLC0_RX_RST_V << SDIO_SLC0_RX_RST_S) +#define SDIO_SLC0_RX_RST_V 0x00000001U +#define SDIO_SLC0_RX_RST_S 1 +/** SDIO_SLC_AHBM_FIFO_RST : R/W; bitpos: [2]; default: 0; + * reset the command fifo of AHB bus of sdio slave + */ +#define SDIO_SLC_AHBM_FIFO_RST (BIT(2)) +#define SDIO_SLC_AHBM_FIFO_RST_M (SDIO_SLC_AHBM_FIFO_RST_V << SDIO_SLC_AHBM_FIFO_RST_S) +#define SDIO_SLC_AHBM_FIFO_RST_V 0x00000001U +#define SDIO_SLC_AHBM_FIFO_RST_S 2 +/** SDIO_SLC_AHBM_RST : R/W; bitpos: [3]; default: 0; + * reset the AHB bus of sdio slave + */ +#define SDIO_SLC_AHBM_RST (BIT(3)) +#define SDIO_SLC_AHBM_RST_M (SDIO_SLC_AHBM_RST_V << SDIO_SLC_AHBM_RST_S) +#define SDIO_SLC_AHBM_RST_V 0x00000001U +#define SDIO_SLC_AHBM_RST_S 3 +/** SDIO_SLC0_TX_LOOP_TEST : R/W; bitpos: [4]; default: 0; + * owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner. + */ +#define SDIO_SLC0_TX_LOOP_TEST (BIT(4)) +#define SDIO_SLC0_TX_LOOP_TEST_M (SDIO_SLC0_TX_LOOP_TEST_V << SDIO_SLC0_TX_LOOP_TEST_S) +#define SDIO_SLC0_TX_LOOP_TEST_V 0x00000001U +#define SDIO_SLC0_TX_LOOP_TEST_S 4 +/** SDIO_SLC0_RX_LOOP_TEST : R/W; bitpos: [5]; default: 0; + * owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner. + */ +#define SDIO_SLC0_RX_LOOP_TEST (BIT(5)) +#define SDIO_SLC0_RX_LOOP_TEST_M (SDIO_SLC0_RX_LOOP_TEST_V << SDIO_SLC0_RX_LOOP_TEST_S) +#define SDIO_SLC0_RX_LOOP_TEST_V 0x00000001U +#define SDIO_SLC0_RX_LOOP_TEST_S 5 +/** SDIO_SLC0_RX_AUTO_WRBACK : R/W; bitpos: [6]; default: 0; + * Set 1 to enable change the owner bit of rx link descriptor + */ +#define SDIO_SLC0_RX_AUTO_WRBACK (BIT(6)) +#define SDIO_SLC0_RX_AUTO_WRBACK_M (SDIO_SLC0_RX_AUTO_WRBACK_V << SDIO_SLC0_RX_AUTO_WRBACK_S) +#define SDIO_SLC0_RX_AUTO_WRBACK_V 0x00000001U +#define SDIO_SLC0_RX_AUTO_WRBACK_S 6 +/** SDIO_SLC0_RX_NO_RESTART_CLR : R/W; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_NO_RESTART_CLR (BIT(7)) +#define SDIO_SLC0_RX_NO_RESTART_CLR_M (SDIO_SLC0_RX_NO_RESTART_CLR_V << SDIO_SLC0_RX_NO_RESTART_CLR_S) +#define SDIO_SLC0_RX_NO_RESTART_CLR_V 0x00000001U +#define SDIO_SLC0_RX_NO_RESTART_CLR_S 7 +/** SDIO_SLC0_RXDSCR_BURST_EN : R/W; bitpos: [8]; default: 1; + * 0- AHB burst type is single when slave read rx-descriptor from memory through + * slc0,1-AHB burst type is not single when slave read rx-descriptor from memory + * through slc0 + */ +#define SDIO_SLC0_RXDSCR_BURST_EN (BIT(8)) +#define SDIO_SLC0_RXDSCR_BURST_EN_M (SDIO_SLC0_RXDSCR_BURST_EN_V << SDIO_SLC0_RXDSCR_BURST_EN_S) +#define SDIO_SLC0_RXDSCR_BURST_EN_V 0x00000001U +#define SDIO_SLC0_RXDSCR_BURST_EN_S 8 +/** SDIO_SLC0_RXDATA_BURST_EN : R/W; bitpos: [9]; default: 1; + * 0- AHB burst type is single when slave receives data from memory,1-AHB burst type + * is not single when slave receives data from memory + */ +#define SDIO_SLC0_RXDATA_BURST_EN (BIT(9)) +#define SDIO_SLC0_RXDATA_BURST_EN_M (SDIO_SLC0_RXDATA_BURST_EN_V << SDIO_SLC0_RXDATA_BURST_EN_S) +#define SDIO_SLC0_RXDATA_BURST_EN_V 0x00000001U +#define SDIO_SLC0_RXDATA_BURST_EN_S 9 +/** SDIO_SLC0_RXLINK_AUTO_RET : R/W; bitpos: [10]; default: 1; + * enable the function that when host reading packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ +#define SDIO_SLC0_RXLINK_AUTO_RET (BIT(10)) +#define SDIO_SLC0_RXLINK_AUTO_RET_M (SDIO_SLC0_RXLINK_AUTO_RET_V << SDIO_SLC0_RXLINK_AUTO_RET_S) +#define SDIO_SLC0_RXLINK_AUTO_RET_V 0x00000001U +#define SDIO_SLC0_RXLINK_AUTO_RET_S 10 +/** SDIO_SLC0_TXLINK_AUTO_RET : R/W; bitpos: [11]; default: 1; + * enable the function that when host sending packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ +#define SDIO_SLC0_TXLINK_AUTO_RET (BIT(11)) +#define SDIO_SLC0_TXLINK_AUTO_RET_M (SDIO_SLC0_TXLINK_AUTO_RET_V << SDIO_SLC0_TXLINK_AUTO_RET_S) +#define SDIO_SLC0_TXLINK_AUTO_RET_V 0x00000001U +#define SDIO_SLC0_TXLINK_AUTO_RET_S 11 +/** SDIO_SLC0_TXDSCR_BURST_EN : R/W; bitpos: [12]; default: 1; + * 0- AHB burst type is single when slave read tx-descriptor from memory through + * slc0,1-AHB burst type is not single when slave read tx-descriptor from memory + * through slc0 + */ +#define SDIO_SLC0_TXDSCR_BURST_EN (BIT(12)) +#define SDIO_SLC0_TXDSCR_BURST_EN_M (SDIO_SLC0_TXDSCR_BURST_EN_V << SDIO_SLC0_TXDSCR_BURST_EN_S) +#define SDIO_SLC0_TXDSCR_BURST_EN_V 0x00000001U +#define SDIO_SLC0_TXDSCR_BURST_EN_S 12 +/** SDIO_SLC0_TXDATA_BURST_EN : R/W; bitpos: [13]; default: 1; + * 0- AHB burst type is single when slave send data to memory,1-AHB burst type is not + * single when slave send data to memory + */ +#define SDIO_SLC0_TXDATA_BURST_EN (BIT(13)) +#define SDIO_SLC0_TXDATA_BURST_EN_M (SDIO_SLC0_TXDATA_BURST_EN_V << SDIO_SLC0_TXDATA_BURST_EN_S) +#define SDIO_SLC0_TXDATA_BURST_EN_V 0x00000001U +#define SDIO_SLC0_TXDATA_BURST_EN_S 13 +/** SDIO_SLC0_TOKEN_AUTO_CLR : R/W; bitpos: [14]; default: 1; + * auto clear slc0_token1 enable + */ +#define SDIO_SLC0_TOKEN_AUTO_CLR (BIT(14)) +#define SDIO_SLC0_TOKEN_AUTO_CLR_M (SDIO_SLC0_TOKEN_AUTO_CLR_V << SDIO_SLC0_TOKEN_AUTO_CLR_S) +#define SDIO_SLC0_TOKEN_AUTO_CLR_V 0x00000001U +#define SDIO_SLC0_TOKEN_AUTO_CLR_S 14 +/** SDIO_SLC0_TOKEN_SEL : R/W; bitpos: [15]; default: 1; + * reserved + */ +#define SDIO_SLC0_TOKEN_SEL (BIT(15)) +#define SDIO_SLC0_TOKEN_SEL_M (SDIO_SLC0_TOKEN_SEL_V << SDIO_SLC0_TOKEN_SEL_S) +#define SDIO_SLC0_TOKEN_SEL_V 0x00000001U +#define SDIO_SLC0_TOKEN_SEL_S 15 +/** SDIO_SLC1_TX_RST : R/W; bitpos: [16]; default: 0; + * Set 1 to reset tx fsm in dma slc0. + */ +#define SDIO_SLC1_TX_RST (BIT(16)) +#define SDIO_SLC1_TX_RST_M (SDIO_SLC1_TX_RST_V << SDIO_SLC1_TX_RST_S) +#define SDIO_SLC1_TX_RST_V 0x00000001U +#define SDIO_SLC1_TX_RST_S 16 +/** SDIO_SLC1_RX_RST : R/W; bitpos: [17]; default: 0; + * Set 1 to reset rx fsm in dma slc0. + */ +#define SDIO_SLC1_RX_RST (BIT(17)) +#define SDIO_SLC1_RX_RST_M (SDIO_SLC1_RX_RST_V << SDIO_SLC1_RX_RST_S) +#define SDIO_SLC1_RX_RST_V 0x00000001U +#define SDIO_SLC1_RX_RST_S 17 +/** SDIO_SLC0_WR_RETRY_MASK_EN : R/W; bitpos: [18]; default: 1; + * reserved + */ +#define SDIO_SLC0_WR_RETRY_MASK_EN (BIT(18)) +#define SDIO_SLC0_WR_RETRY_MASK_EN_M (SDIO_SLC0_WR_RETRY_MASK_EN_V << SDIO_SLC0_WR_RETRY_MASK_EN_S) +#define SDIO_SLC0_WR_RETRY_MASK_EN_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_MASK_EN_S 18 +/** SDIO_SLC1_WR_RETRY_MASK_EN : R/W; bitpos: [19]; default: 1; + * reserved + */ +#define SDIO_SLC1_WR_RETRY_MASK_EN (BIT(19)) +#define SDIO_SLC1_WR_RETRY_MASK_EN_M (SDIO_SLC1_WR_RETRY_MASK_EN_V << SDIO_SLC1_WR_RETRY_MASK_EN_S) +#define SDIO_SLC1_WR_RETRY_MASK_EN_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_MASK_EN_S 19 +/** SDIO_SLC1_TX_LOOP_TEST : R/W; bitpos: [20]; default: 1; + * owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner. + */ +#define SDIO_SLC1_TX_LOOP_TEST (BIT(20)) +#define SDIO_SLC1_TX_LOOP_TEST_M (SDIO_SLC1_TX_LOOP_TEST_V << SDIO_SLC1_TX_LOOP_TEST_S) +#define SDIO_SLC1_TX_LOOP_TEST_V 0x00000001U +#define SDIO_SLC1_TX_LOOP_TEST_S 20 +/** SDIO_SLC1_RX_LOOP_TEST : R/W; bitpos: [21]; default: 1; + * owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner. + */ +#define SDIO_SLC1_RX_LOOP_TEST (BIT(21)) +#define SDIO_SLC1_RX_LOOP_TEST_M (SDIO_SLC1_RX_LOOP_TEST_V << SDIO_SLC1_RX_LOOP_TEST_S) +#define SDIO_SLC1_RX_LOOP_TEST_V 0x00000001U +#define SDIO_SLC1_RX_LOOP_TEST_S 21 +/** SDIO_SLC1_RX_AUTO_WRBACK : R/W; bitpos: [22]; default: 0; + * Set 1 to enable change the owner bit of rx link descriptor + */ +#define SDIO_SLC1_RX_AUTO_WRBACK (BIT(22)) +#define SDIO_SLC1_RX_AUTO_WRBACK_M (SDIO_SLC1_RX_AUTO_WRBACK_V << SDIO_SLC1_RX_AUTO_WRBACK_S) +#define SDIO_SLC1_RX_AUTO_WRBACK_V 0x00000001U +#define SDIO_SLC1_RX_AUTO_WRBACK_S 22 +/** SDIO_SLC1_RX_NO_RESTART_CLR : R/W; bitpos: [23]; default: 0; + * ******* Description *********** + */ +#define SDIO_SLC1_RX_NO_RESTART_CLR (BIT(23)) +#define SDIO_SLC1_RX_NO_RESTART_CLR_M (SDIO_SLC1_RX_NO_RESTART_CLR_V << SDIO_SLC1_RX_NO_RESTART_CLR_S) +#define SDIO_SLC1_RX_NO_RESTART_CLR_V 0x00000001U +#define SDIO_SLC1_RX_NO_RESTART_CLR_S 23 +/** SDIO_SLC1_RXDSCR_BURST_EN : R/W; bitpos: [24]; default: 1; + * 0- AHB burst type is single when slave read rx-descriptor from memory through + * slc1,1-AHB burst type is not single when slave read rx-descriptor from memory + * through slc1 + */ +#define SDIO_SLC1_RXDSCR_BURST_EN (BIT(24)) +#define SDIO_SLC1_RXDSCR_BURST_EN_M (SDIO_SLC1_RXDSCR_BURST_EN_V << SDIO_SLC1_RXDSCR_BURST_EN_S) +#define SDIO_SLC1_RXDSCR_BURST_EN_V 0x00000001U +#define SDIO_SLC1_RXDSCR_BURST_EN_S 24 +/** SDIO_SLC1_RXDATA_BURST_EN : R/W; bitpos: [25]; default: 1; + * 0- AHB burst type is single when slave receives data from memory,1-AHB burst type + * is not single when slave receives data from memory + */ +#define SDIO_SLC1_RXDATA_BURST_EN (BIT(25)) +#define SDIO_SLC1_RXDATA_BURST_EN_M (SDIO_SLC1_RXDATA_BURST_EN_V << SDIO_SLC1_RXDATA_BURST_EN_S) +#define SDIO_SLC1_RXDATA_BURST_EN_V 0x00000001U +#define SDIO_SLC1_RXDATA_BURST_EN_S 25 +/** SDIO_SLC1_RXLINK_AUTO_RET : R/W; bitpos: [26]; default: 1; + * enable the function that when host reading packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ +#define SDIO_SLC1_RXLINK_AUTO_RET (BIT(26)) +#define SDIO_SLC1_RXLINK_AUTO_RET_M (SDIO_SLC1_RXLINK_AUTO_RET_V << SDIO_SLC1_RXLINK_AUTO_RET_S) +#define SDIO_SLC1_RXLINK_AUTO_RET_V 0x00000001U +#define SDIO_SLC1_RXLINK_AUTO_RET_S 26 +/** SDIO_SLC1_TXLINK_AUTO_RET : R/W; bitpos: [27]; default: 1; + * enable the function that when host sending packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ +#define SDIO_SLC1_TXLINK_AUTO_RET (BIT(27)) +#define SDIO_SLC1_TXLINK_AUTO_RET_M (SDIO_SLC1_TXLINK_AUTO_RET_V << SDIO_SLC1_TXLINK_AUTO_RET_S) +#define SDIO_SLC1_TXLINK_AUTO_RET_V 0x00000001U +#define SDIO_SLC1_TXLINK_AUTO_RET_S 27 +/** SDIO_SLC1_TXDSCR_BURST_EN : R/W; bitpos: [28]; default: 1; + * 0- AHB burst type is single when slave read tx-descriptor from memory through + * slc1,1-AHB burst type is not single when slave read tx-descriptor from memory + * through slc1 + */ +#define SDIO_SLC1_TXDSCR_BURST_EN (BIT(28)) +#define SDIO_SLC1_TXDSCR_BURST_EN_M (SDIO_SLC1_TXDSCR_BURST_EN_V << SDIO_SLC1_TXDSCR_BURST_EN_S) +#define SDIO_SLC1_TXDSCR_BURST_EN_V 0x00000001U +#define SDIO_SLC1_TXDSCR_BURST_EN_S 28 +/** SDIO_SLC1_TXDATA_BURST_EN : R/W; bitpos: [29]; default: 1; + * 0- AHB burst type is single when slave send data to memory,1-AHB burst type is not + * single when slave send data to memory + */ +#define SDIO_SLC1_TXDATA_BURST_EN (BIT(29)) +#define SDIO_SLC1_TXDATA_BURST_EN_M (SDIO_SLC1_TXDATA_BURST_EN_V << SDIO_SLC1_TXDATA_BURST_EN_S) +#define SDIO_SLC1_TXDATA_BURST_EN_V 0x00000001U +#define SDIO_SLC1_TXDATA_BURST_EN_S 29 +/** SDIO_SLC1_TOKEN_AUTO_CLR : R/W; bitpos: [30]; default: 1; + * auto clear slc1_token1 enable + */ +#define SDIO_SLC1_TOKEN_AUTO_CLR (BIT(30)) +#define SDIO_SLC1_TOKEN_AUTO_CLR_M (SDIO_SLC1_TOKEN_AUTO_CLR_V << SDIO_SLC1_TOKEN_AUTO_CLR_S) +#define SDIO_SLC1_TOKEN_AUTO_CLR_V 0x00000001U +#define SDIO_SLC1_TOKEN_AUTO_CLR_S 30 +/** SDIO_SLC1_TOKEN_SEL : R/W; bitpos: [31]; default: 1; + * reserved + */ +#define SDIO_SLC1_TOKEN_SEL (BIT(31)) +#define SDIO_SLC1_TOKEN_SEL_M (SDIO_SLC1_TOKEN_SEL_V << SDIO_SLC1_TOKEN_SEL_S) +#define SDIO_SLC1_TOKEN_SEL_V 0x00000001U +#define SDIO_SLC1_TOKEN_SEL_S 31 + +/** SDIO_SLC0INT_RAW_REG register + * ******* Description *********** + */ +#define SDIO_SLC0INT_RAW_REG (DR_REG_SLC_BASE + 0x4) +/** SDIO_SLC_FRHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT0_INT_RAW (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_RAW_M (SDIO_SLC_FRHOST_BIT0_INT_RAW_V << SDIO_SLC_FRHOST_BIT0_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT0_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_RAW_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT1_INT_RAW (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_RAW_M (SDIO_SLC_FRHOST_BIT1_INT_RAW_V << SDIO_SLC_FRHOST_BIT1_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT1_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_RAW_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT2_INT_RAW (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_RAW_M (SDIO_SLC_FRHOST_BIT2_INT_RAW_V << SDIO_SLC_FRHOST_BIT2_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT2_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_RAW_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT3_INT_RAW (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_RAW_M (SDIO_SLC_FRHOST_BIT3_INT_RAW_V << SDIO_SLC_FRHOST_BIT3_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT3_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_RAW_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT4_INT_RAW (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_RAW_M (SDIO_SLC_FRHOST_BIT4_INT_RAW_V << SDIO_SLC_FRHOST_BIT4_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT4_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_RAW_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT5_INT_RAW (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_RAW_M (SDIO_SLC_FRHOST_BIT5_INT_RAW_V << SDIO_SLC_FRHOST_BIT5_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT5_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_RAW_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT6_INT_RAW (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_RAW_M (SDIO_SLC_FRHOST_BIT6_INT_RAW_V << SDIO_SLC_FRHOST_BIT6_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT6_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_RAW_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT7_INT_RAW (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_RAW_M (SDIO_SLC_FRHOST_BIT7_INT_RAW_V << SDIO_SLC_FRHOST_BIT7_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT7_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_RAW_S 7 +/** SDIO_SLC0_RX_START_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_START_INT_RAW (BIT(8)) +#define SDIO_SLC0_RX_START_INT_RAW_M (SDIO_SLC0_RX_START_INT_RAW_V << SDIO_SLC0_RX_START_INT_RAW_S) +#define SDIO_SLC0_RX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_RAW_S 8 +/** SDIO_SLC0_TX_START_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_START_INT_RAW (BIT(9)) +#define SDIO_SLC0_TX_START_INT_RAW_M (SDIO_SLC0_TX_START_INT_RAW_V << SDIO_SLC0_TX_START_INT_RAW_S) +#define SDIO_SLC0_TX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_RAW_S 9 +/** SDIO_SLC0_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_UDF_INT_RAW (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_RAW_M (SDIO_SLC0_RX_UDF_INT_RAW_V << SDIO_SLC0_RX_UDF_INT_RAW_S) +#define SDIO_SLC0_RX_UDF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_RAW_S 10 +/** SDIO_SLC0_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_OVF_INT_RAW (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_RAW_M (SDIO_SLC0_TX_OVF_INT_RAW_V << SDIO_SLC0_TX_OVF_INT_RAW_S) +#define SDIO_SLC0_TX_OVF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_RAW_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_M (SDIO_SLC0_TOKEN0_1TO0_INT_RAW_V << SDIO_SLC0_TOKEN0_1TO0_INT_RAW_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_M (SDIO_SLC0_TOKEN1_1TO0_INT_RAW_V << SDIO_SLC0_TOKEN1_1TO0_INT_RAW_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_S 13 +/** SDIO_SLC0_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit of slc0 finishing receiving data to one buffer + */ +#define SDIO_SLC0_TX_DONE_INT_RAW (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_RAW_M (SDIO_SLC0_TX_DONE_INT_RAW_V << SDIO_SLC0_TX_DONE_INT_RAW_S) +#define SDIO_SLC0_TX_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_RAW_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit of slc0 finishing receiving data + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_RAW (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_M (SDIO_SLC0_TX_SUC_EOF_INT_RAW_V << SDIO_SLC0_TX_SUC_EOF_INT_RAW_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_S 15 +/** SDIO_SLC0_RX_DONE_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The raw interrupt bit of slc0 finishing sending data from one buffer + */ +#define SDIO_SLC0_RX_DONE_INT_RAW (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_RAW_M (SDIO_SLC0_RX_DONE_INT_RAW_V << SDIO_SLC0_RX_DONE_INT_RAW_S) +#define SDIO_SLC0_RX_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_RAW_S 16 +/** SDIO_SLC0_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The raw interrupt bit of slc0 finishing sending data + */ +#define SDIO_SLC0_RX_EOF_INT_RAW (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_RAW_M (SDIO_SLC0_RX_EOF_INT_RAW_V << SDIO_SLC0_RX_EOF_INT_RAW_S) +#define SDIO_SLC0_RX_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_RAW_S 17 +/** SDIO_SLC0_TOHOST_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOHOST_INT_RAW (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_RAW_M (SDIO_SLC0_TOHOST_INT_RAW_V << SDIO_SLC0_TOHOST_INT_RAW_S) +#define SDIO_SLC0_TOHOST_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_RAW_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The raw interrupt bit of slc0 tx link descriptor error + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_M (SDIO_SLC0_TX_DSCR_ERR_INT_RAW_V << SDIO_SLC0_TX_DSCR_ERR_INT_RAW_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * The raw interrupt bit of slc0 rx link descriptor error + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_M (SDIO_SLC0_RX_DSCR_ERR_INT_RAW_V << SDIO_SLC0_RX_DSCR_ERR_INT_RAW_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_RAW (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_M (SDIO_SLC0_HOST_RD_ACK_INT_RAW_V << SDIO_SLC0_HOST_RD_ACK_INT_RAW_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_M (SDIO_SLC0_WR_RETRY_DONE_INT_RAW_V << SDIO_SLC0_WR_RETRY_DONE_INT_RAW_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_RAW (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_M (SDIO_SLC0_TX_ERR_EOF_INT_RAW_V << SDIO_SLC0_TX_ERR_EOF_INT_RAW_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_S 24 +/** SDIO_CMD_DTC_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * reserved + */ +#define SDIO_CMD_DTC_INT_RAW (BIT(25)) +#define SDIO_CMD_DTC_INT_RAW_M (SDIO_CMD_DTC_INT_RAW_V << SDIO_CMD_DTC_INT_RAW_S) +#define SDIO_CMD_DTC_INT_RAW_V 0x00000001U +#define SDIO_CMD_DTC_INT_RAW_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_M (SDIO_SLC0_RX_QUICK_EOF_INT_RAW_V << SDIO_SLC0_RX_QUICK_EOF_INT_RAW_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_S 27 +/** SDIO_HDA_RECV_DONE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * reserved + */ +#define SDIO_HDA_RECV_DONE_INT_RAW (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_RAW_M (SDIO_HDA_RECV_DONE_INT_RAW_V << SDIO_HDA_RECV_DONE_INT_RAW_S) +#define SDIO_HDA_RECV_DONE_INT_RAW_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_RAW_S 28 + +/** SDIO_SLC0INT_ST_REG register + * ******* Description *********** + */ +#define SDIO_SLC0INT_ST_REG (DR_REG_SLC_BASE + 0x8) +/** SDIO_SLC_FRHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT0_INT_ST (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_ST_M (SDIO_SLC_FRHOST_BIT0_INT_ST_V << SDIO_SLC_FRHOST_BIT0_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT0_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_ST_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT1_INT_ST (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_ST_M (SDIO_SLC_FRHOST_BIT1_INT_ST_V << SDIO_SLC_FRHOST_BIT1_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT1_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_ST_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT2_INT_ST (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_ST_M (SDIO_SLC_FRHOST_BIT2_INT_ST_V << SDIO_SLC_FRHOST_BIT2_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT2_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_ST_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT3_INT_ST (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_ST_M (SDIO_SLC_FRHOST_BIT3_INT_ST_V << SDIO_SLC_FRHOST_BIT3_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT3_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_ST_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT4_INT_ST (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_ST_M (SDIO_SLC_FRHOST_BIT4_INT_ST_V << SDIO_SLC_FRHOST_BIT4_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT4_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_ST_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT5_INT_ST (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_ST_M (SDIO_SLC_FRHOST_BIT5_INT_ST_V << SDIO_SLC_FRHOST_BIT5_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT5_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_ST_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT6_INT_ST (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_ST_M (SDIO_SLC_FRHOST_BIT6_INT_ST_V << SDIO_SLC_FRHOST_BIT6_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT6_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_ST_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT7_INT_ST (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_ST_M (SDIO_SLC_FRHOST_BIT7_INT_ST_V << SDIO_SLC_FRHOST_BIT7_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT7_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_ST_S 7 +/** SDIO_SLC0_RX_START_INT_ST : RO; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_START_INT_ST (BIT(8)) +#define SDIO_SLC0_RX_START_INT_ST_M (SDIO_SLC0_RX_START_INT_ST_V << SDIO_SLC0_RX_START_INT_ST_S) +#define SDIO_SLC0_RX_START_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_ST_S 8 +/** SDIO_SLC0_TX_START_INT_ST : RO; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_START_INT_ST (BIT(9)) +#define SDIO_SLC0_TX_START_INT_ST_M (SDIO_SLC0_TX_START_INT_ST_V << SDIO_SLC0_TX_START_INT_ST_S) +#define SDIO_SLC0_TX_START_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_ST_S 9 +/** SDIO_SLC0_RX_UDF_INT_ST : RO; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_UDF_INT_ST (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_ST_M (SDIO_SLC0_RX_UDF_INT_ST_V << SDIO_SLC0_RX_UDF_INT_ST_S) +#define SDIO_SLC0_RX_UDF_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_ST_S 10 +/** SDIO_SLC0_TX_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_OVF_INT_ST (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_ST_M (SDIO_SLC0_TX_OVF_INT_ST_V << SDIO_SLC0_TX_OVF_INT_ST_S) +#define SDIO_SLC0_TX_OVF_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_ST_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_ST : RO; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_M (SDIO_SLC0_TOKEN0_1TO0_INT_ST_V << SDIO_SLC0_TOKEN0_1TO0_INT_ST_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_ST : RO; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_M (SDIO_SLC0_TOKEN1_1TO0_INT_ST_V << SDIO_SLC0_TOKEN1_1TO0_INT_ST_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_S 13 +/** SDIO_SLC0_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DONE_INT_ST (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_ST_M (SDIO_SLC0_TX_DONE_INT_ST_V << SDIO_SLC0_TX_DONE_INT_ST_S) +#define SDIO_SLC0_TX_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_ST_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_ST : RO; bitpos: [15]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_ST (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_ST_M (SDIO_SLC0_TX_SUC_EOF_INT_ST_V << SDIO_SLC0_TX_SUC_EOF_INT_ST_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_ST_S 15 +/** SDIO_SLC0_RX_DONE_INT_ST : RO; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_DONE_INT_ST (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_ST_M (SDIO_SLC0_RX_DONE_INT_ST_V << SDIO_SLC0_RX_DONE_INT_ST_S) +#define SDIO_SLC0_RX_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_ST_S 16 +/** SDIO_SLC0_RX_EOF_INT_ST : RO; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_EOF_INT_ST (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_ST_M (SDIO_SLC0_RX_EOF_INT_ST_V << SDIO_SLC0_RX_EOF_INT_ST_S) +#define SDIO_SLC0_RX_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_ST_S 17 +/** SDIO_SLC0_TOHOST_INT_ST : RO; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOHOST_INT_ST (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_ST_M (SDIO_SLC0_TOHOST_INT_ST_V << SDIO_SLC0_TOHOST_INT_ST_S) +#define SDIO_SLC0_TOHOST_INT_ST_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_ST_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_ST : RO; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_M (SDIO_SLC0_TX_DSCR_ERR_INT_ST_V << SDIO_SLC0_TX_DSCR_ERR_INT_ST_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_ST : RO; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_M (SDIO_SLC0_RX_DSCR_ERR_INT_ST_V << SDIO_SLC0_RX_DSCR_ERR_INT_ST_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ST : RO; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_ST : RO; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_ST (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_ST_M (SDIO_SLC0_HOST_RD_ACK_INT_ST_V << SDIO_SLC0_HOST_RD_ACK_INT_ST_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_ST_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_ST_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_ST : RO; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_M (SDIO_SLC0_WR_RETRY_DONE_INT_ST_V << SDIO_SLC0_WR_RETRY_DONE_INT_ST_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_ST : RO; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_ST (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_ST_M (SDIO_SLC0_TX_ERR_EOF_INT_ST_V << SDIO_SLC0_TX_ERR_EOF_INT_ST_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_ST_S 24 +/** SDIO_CMD_DTC_INT_ST : RO; bitpos: [25]; default: 0; + * reserved + */ +#define SDIO_CMD_DTC_INT_ST (BIT(25)) +#define SDIO_CMD_DTC_INT_ST_M (SDIO_CMD_DTC_INT_ST_V << SDIO_CMD_DTC_INT_ST_S) +#define SDIO_CMD_DTC_INT_ST_V 0x00000001U +#define SDIO_CMD_DTC_INT_ST_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_ST : RO; bitpos: [26]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_M (SDIO_SLC0_RX_QUICK_EOF_INT_ST_V << SDIO_SLC0_RX_QUICK_EOF_INT_ST_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST : RO; bitpos: [27]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_S 27 +/** SDIO_HDA_RECV_DONE_INT_ST : RO; bitpos: [28]; default: 0; + * reserved + */ +#define SDIO_HDA_RECV_DONE_INT_ST (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_ST_M (SDIO_HDA_RECV_DONE_INT_ST_V << SDIO_HDA_RECV_DONE_INT_ST_S) +#define SDIO_HDA_RECV_DONE_INT_ST_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_ST_S 28 + +/** SDIO_SLC0INT_ENA_REG register + * ******* Description *********** + */ +#define SDIO_SLC0INT_ENA_REG (DR_REG_SLC_BASE + 0xc) +/** SDIO_SLC_FRHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT0_INT_ENA (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_ENA_M (SDIO_SLC_FRHOST_BIT0_INT_ENA_V << SDIO_SLC_FRHOST_BIT0_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_ENA_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT1_INT_ENA (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_ENA_M (SDIO_SLC_FRHOST_BIT1_INT_ENA_V << SDIO_SLC_FRHOST_BIT1_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_ENA_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT2_INT_ENA (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_ENA_M (SDIO_SLC_FRHOST_BIT2_INT_ENA_V << SDIO_SLC_FRHOST_BIT2_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_ENA_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT3_INT_ENA (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_ENA_M (SDIO_SLC_FRHOST_BIT3_INT_ENA_V << SDIO_SLC_FRHOST_BIT3_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_ENA_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT4_INT_ENA (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_ENA_M (SDIO_SLC_FRHOST_BIT4_INT_ENA_V << SDIO_SLC_FRHOST_BIT4_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT4_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_ENA_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT5_INT_ENA (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_ENA_M (SDIO_SLC_FRHOST_BIT5_INT_ENA_V << SDIO_SLC_FRHOST_BIT5_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT5_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_ENA_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT6_INT_ENA (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_ENA_M (SDIO_SLC_FRHOST_BIT6_INT_ENA_V << SDIO_SLC_FRHOST_BIT6_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT6_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_ENA_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT7_INT_ENA (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_ENA_M (SDIO_SLC_FRHOST_BIT7_INT_ENA_V << SDIO_SLC_FRHOST_BIT7_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT7_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_ENA_S 7 +/** SDIO_SLC0_RX_START_INT_ENA : R/W; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_START_INT_ENA (BIT(8)) +#define SDIO_SLC0_RX_START_INT_ENA_M (SDIO_SLC0_RX_START_INT_ENA_V << SDIO_SLC0_RX_START_INT_ENA_S) +#define SDIO_SLC0_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_ENA_S 8 +/** SDIO_SLC0_TX_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_START_INT_ENA (BIT(9)) +#define SDIO_SLC0_TX_START_INT_ENA_M (SDIO_SLC0_TX_START_INT_ENA_V << SDIO_SLC0_TX_START_INT_ENA_S) +#define SDIO_SLC0_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_ENA_S 9 +/** SDIO_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_UDF_INT_ENA (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_ENA_M (SDIO_SLC0_RX_UDF_INT_ENA_V << SDIO_SLC0_RX_UDF_INT_ENA_S) +#define SDIO_SLC0_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_ENA_S 10 +/** SDIO_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_OVF_INT_ENA (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_ENA_M (SDIO_SLC0_TX_OVF_INT_ENA_V << SDIO_SLC0_TX_OVF_INT_ENA_S) +#define SDIO_SLC0_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_ENA_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_M (SDIO_SLC0_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC0_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_M (SDIO_SLC0_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC0_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_S 13 +/** SDIO_SLC0_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DONE_INT_ENA (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_ENA_M (SDIO_SLC0_TX_DONE_INT_ENA_V << SDIO_SLC0_TX_DONE_INT_ENA_S) +#define SDIO_SLC0_TX_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_ENA_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_ENA : R/W; bitpos: [15]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_M (SDIO_SLC0_TX_SUC_EOF_INT_ENA_V << SDIO_SLC0_TX_SUC_EOF_INT_ENA_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_S 15 +/** SDIO_SLC0_RX_DONE_INT_ENA : R/W; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_DONE_INT_ENA (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_ENA_M (SDIO_SLC0_RX_DONE_INT_ENA_V << SDIO_SLC0_RX_DONE_INT_ENA_S) +#define SDIO_SLC0_RX_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_ENA_S 16 +/** SDIO_SLC0_RX_EOF_INT_ENA : R/W; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_EOF_INT_ENA (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_ENA_M (SDIO_SLC0_RX_EOF_INT_ENA_V << SDIO_SLC0_RX_EOF_INT_ENA_S) +#define SDIO_SLC0_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_ENA_S 17 +/** SDIO_SLC0_TOHOST_INT_ENA : R/W; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOHOST_INT_ENA (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_ENA_M (SDIO_SLC0_TOHOST_INT_ENA_V << SDIO_SLC0_TOHOST_INT_ENA_S) +#define SDIO_SLC0_TOHOST_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_ENA_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_ENA : R/W; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_M (SDIO_SLC0_TX_DSCR_ERR_INT_ENA_V << SDIO_SLC0_TX_DSCR_ERR_INT_ENA_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_ENA : R/W; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_M (SDIO_SLC0_RX_DSCR_ERR_INT_ENA_V << SDIO_SLC0_RX_DSCR_ERR_INT_ENA_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA : R/W; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_ENA : R/W; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_M (SDIO_SLC0_HOST_RD_ACK_INT_ENA_V << SDIO_SLC0_HOST_RD_ACK_INT_ENA_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_ENA : R/W; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_M (SDIO_SLC0_WR_RETRY_DONE_INT_ENA_V << SDIO_SLC0_WR_RETRY_DONE_INT_ENA_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_ENA : R/W; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_M (SDIO_SLC0_TX_ERR_EOF_INT_ENA_V << SDIO_SLC0_TX_ERR_EOF_INT_ENA_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_S 24 +/** SDIO_CMD_DTC_INT_ENA : R/W; bitpos: [25]; default: 0; + * reserved + */ +#define SDIO_CMD_DTC_INT_ENA (BIT(25)) +#define SDIO_CMD_DTC_INT_ENA_M (SDIO_CMD_DTC_INT_ENA_V << SDIO_CMD_DTC_INT_ENA_S) +#define SDIO_CMD_DTC_INT_ENA_V 0x00000001U +#define SDIO_CMD_DTC_INT_ENA_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_ENA : R/W; bitpos: [26]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_M (SDIO_SLC0_RX_QUICK_EOF_INT_ENA_V << SDIO_SLC0_RX_QUICK_EOF_INT_ENA_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA : R/W; bitpos: [27]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_S 27 +/** SDIO_HDA_RECV_DONE_INT_ENA : R/W; bitpos: [28]; default: 0; + * reserved + */ +#define SDIO_HDA_RECV_DONE_INT_ENA (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_ENA_M (SDIO_HDA_RECV_DONE_INT_ENA_V << SDIO_HDA_RECV_DONE_INT_ENA_S) +#define SDIO_HDA_RECV_DONE_INT_ENA_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_ENA_S 28 + +/** SDIO_SLC0INT_CLR_REG register + * ******* Description *********** + */ +#define SDIO_SLC0INT_CLR_REG (DR_REG_SLC_BASE + 0x10) +/** SDIO_SLC_FRHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT0_INT_CLR (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_CLR_M (SDIO_SLC_FRHOST_BIT0_INT_CLR_V << SDIO_SLC_FRHOST_BIT0_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT0_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_CLR_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT1_INT_CLR (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_CLR_M (SDIO_SLC_FRHOST_BIT1_INT_CLR_V << SDIO_SLC_FRHOST_BIT1_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT1_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_CLR_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT2_INT_CLR (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_CLR_M (SDIO_SLC_FRHOST_BIT2_INT_CLR_V << SDIO_SLC_FRHOST_BIT2_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT2_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_CLR_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT3_INT_CLR (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_CLR_M (SDIO_SLC_FRHOST_BIT3_INT_CLR_V << SDIO_SLC_FRHOST_BIT3_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT3_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_CLR_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT4_INT_CLR (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_CLR_M (SDIO_SLC_FRHOST_BIT4_INT_CLR_V << SDIO_SLC_FRHOST_BIT4_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT4_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_CLR_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT5_INT_CLR (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_CLR_M (SDIO_SLC_FRHOST_BIT5_INT_CLR_V << SDIO_SLC_FRHOST_BIT5_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT5_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_CLR_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT6_INT_CLR (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_CLR_M (SDIO_SLC_FRHOST_BIT6_INT_CLR_V << SDIO_SLC_FRHOST_BIT6_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT6_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_CLR_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT7_INT_CLR (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_CLR_M (SDIO_SLC_FRHOST_BIT7_INT_CLR_V << SDIO_SLC_FRHOST_BIT7_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT7_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_CLR_S 7 +/** SDIO_SLC0_RX_START_INT_CLR : WT; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_START_INT_CLR (BIT(8)) +#define SDIO_SLC0_RX_START_INT_CLR_M (SDIO_SLC0_RX_START_INT_CLR_V << SDIO_SLC0_RX_START_INT_CLR_S) +#define SDIO_SLC0_RX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_CLR_S 8 +/** SDIO_SLC0_TX_START_INT_CLR : WT; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_START_INT_CLR (BIT(9)) +#define SDIO_SLC0_TX_START_INT_CLR_M (SDIO_SLC0_TX_START_INT_CLR_V << SDIO_SLC0_TX_START_INT_CLR_S) +#define SDIO_SLC0_TX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_CLR_S 9 +/** SDIO_SLC0_RX_UDF_INT_CLR : WT; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_UDF_INT_CLR (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_CLR_M (SDIO_SLC0_RX_UDF_INT_CLR_V << SDIO_SLC0_RX_UDF_INT_CLR_S) +#define SDIO_SLC0_RX_UDF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_CLR_S 10 +/** SDIO_SLC0_TX_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_OVF_INT_CLR (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_CLR_M (SDIO_SLC0_TX_OVF_INT_CLR_V << SDIO_SLC0_TX_OVF_INT_CLR_S) +#define SDIO_SLC0_TX_OVF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_CLR_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_CLR : WT; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_M (SDIO_SLC0_TOKEN0_1TO0_INT_CLR_V << SDIO_SLC0_TOKEN0_1TO0_INT_CLR_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_CLR : WT; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_M (SDIO_SLC0_TOKEN1_1TO0_INT_CLR_V << SDIO_SLC0_TOKEN1_1TO0_INT_CLR_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_S 13 +/** SDIO_SLC0_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DONE_INT_CLR (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_CLR_M (SDIO_SLC0_TX_DONE_INT_CLR_V << SDIO_SLC0_TX_DONE_INT_CLR_S) +#define SDIO_SLC0_TX_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_CLR_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_CLR : WT; bitpos: [15]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_CLR (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_M (SDIO_SLC0_TX_SUC_EOF_INT_CLR_V << SDIO_SLC0_TX_SUC_EOF_INT_CLR_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_S 15 +/** SDIO_SLC0_RX_DONE_INT_CLR : WT; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_DONE_INT_CLR (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_CLR_M (SDIO_SLC0_RX_DONE_INT_CLR_V << SDIO_SLC0_RX_DONE_INT_CLR_S) +#define SDIO_SLC0_RX_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_CLR_S 16 +/** SDIO_SLC0_RX_EOF_INT_CLR : WT; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_EOF_INT_CLR (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_CLR_M (SDIO_SLC0_RX_EOF_INT_CLR_V << SDIO_SLC0_RX_EOF_INT_CLR_S) +#define SDIO_SLC0_RX_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_CLR_S 17 +/** SDIO_SLC0_TOHOST_INT_CLR : WT; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOHOST_INT_CLR (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_CLR_M (SDIO_SLC0_TOHOST_INT_CLR_V << SDIO_SLC0_TOHOST_INT_CLR_S) +#define SDIO_SLC0_TOHOST_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_CLR_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_CLR : WT; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_M (SDIO_SLC0_TX_DSCR_ERR_INT_CLR_V << SDIO_SLC0_TX_DSCR_ERR_INT_CLR_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_CLR : WT; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_M (SDIO_SLC0_RX_DSCR_ERR_INT_CLR_V << SDIO_SLC0_RX_DSCR_ERR_INT_CLR_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR : WT; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_CLR : WT; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_CLR (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_M (SDIO_SLC0_HOST_RD_ACK_INT_CLR_V << SDIO_SLC0_HOST_RD_ACK_INT_CLR_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_CLR : WT; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_M (SDIO_SLC0_WR_RETRY_DONE_INT_CLR_V << SDIO_SLC0_WR_RETRY_DONE_INT_CLR_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_CLR : WT; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_CLR (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_M (SDIO_SLC0_TX_ERR_EOF_INT_CLR_V << SDIO_SLC0_TX_ERR_EOF_INT_CLR_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_S 24 +/** SDIO_CMD_DTC_INT_CLR : WT; bitpos: [25]; default: 0; + * reserved + */ +#define SDIO_CMD_DTC_INT_CLR (BIT(25)) +#define SDIO_CMD_DTC_INT_CLR_M (SDIO_CMD_DTC_INT_CLR_V << SDIO_CMD_DTC_INT_CLR_S) +#define SDIO_CMD_DTC_INT_CLR_V 0x00000001U +#define SDIO_CMD_DTC_INT_CLR_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_CLR : WT; bitpos: [26]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_M (SDIO_SLC0_RX_QUICK_EOF_INT_CLR_V << SDIO_SLC0_RX_QUICK_EOF_INT_CLR_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR : WT; bitpos: [27]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_S 27 +/** SDIO_HDA_RECV_DONE_INT_CLR : WT; bitpos: [28]; default: 0; + * reserved + */ +#define SDIO_HDA_RECV_DONE_INT_CLR (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_CLR_M (SDIO_HDA_RECV_DONE_INT_CLR_V << SDIO_HDA_RECV_DONE_INT_CLR_S) +#define SDIO_HDA_RECV_DONE_INT_CLR_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_CLR_S 28 + +/** SDIO_SLC1INT_RAW_REG register + * reserved + */ +#define SDIO_SLC1INT_RAW_REG (DR_REG_SLC_BASE + 0x14) +/** SDIO_SLC_FRHOST_BIT8_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT8_INT_RAW (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_RAW_M (SDIO_SLC_FRHOST_BIT8_INT_RAW_V << SDIO_SLC_FRHOST_BIT8_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT8_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_RAW_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT9_INT_RAW (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_RAW_M (SDIO_SLC_FRHOST_BIT9_INT_RAW_V << SDIO_SLC_FRHOST_BIT9_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT9_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_RAW_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT10_INT_RAW (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_RAW_M (SDIO_SLC_FRHOST_BIT10_INT_RAW_V << SDIO_SLC_FRHOST_BIT10_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT10_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_RAW_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT11_INT_RAW (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_RAW_M (SDIO_SLC_FRHOST_BIT11_INT_RAW_V << SDIO_SLC_FRHOST_BIT11_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT11_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_RAW_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT12_INT_RAW (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_RAW_M (SDIO_SLC_FRHOST_BIT12_INT_RAW_V << SDIO_SLC_FRHOST_BIT12_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT12_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_RAW_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT13_INT_RAW (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_RAW_M (SDIO_SLC_FRHOST_BIT13_INT_RAW_V << SDIO_SLC_FRHOST_BIT13_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT13_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_RAW_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT14_INT_RAW (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_RAW_M (SDIO_SLC_FRHOST_BIT14_INT_RAW_V << SDIO_SLC_FRHOST_BIT14_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT14_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_RAW_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT15_INT_RAW (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_RAW_M (SDIO_SLC_FRHOST_BIT15_INT_RAW_V << SDIO_SLC_FRHOST_BIT15_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT15_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_RAW_S 7 +/** SDIO_SLC1_RX_START_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_START_INT_RAW (BIT(8)) +#define SDIO_SLC1_RX_START_INT_RAW_M (SDIO_SLC1_RX_START_INT_RAW_V << SDIO_SLC1_RX_START_INT_RAW_S) +#define SDIO_SLC1_RX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_RAW_S 8 +/** SDIO_SLC1_TX_START_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_START_INT_RAW (BIT(9)) +#define SDIO_SLC1_TX_START_INT_RAW_M (SDIO_SLC1_TX_START_INT_RAW_V << SDIO_SLC1_TX_START_INT_RAW_S) +#define SDIO_SLC1_TX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_RAW_S 9 +/** SDIO_SLC1_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_UDF_INT_RAW (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_RAW_M (SDIO_SLC1_RX_UDF_INT_RAW_V << SDIO_SLC1_RX_UDF_INT_RAW_S) +#define SDIO_SLC1_RX_UDF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_RAW_S 10 +/** SDIO_SLC1_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_OVF_INT_RAW (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_RAW_M (SDIO_SLC1_TX_OVF_INT_RAW_V << SDIO_SLC1_TX_OVF_INT_RAW_S) +#define SDIO_SLC1_TX_OVF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_RAW_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_M (SDIO_SLC1_TOKEN0_1TO0_INT_RAW_V << SDIO_SLC1_TOKEN0_1TO0_INT_RAW_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_M (SDIO_SLC1_TOKEN1_1TO0_INT_RAW_V << SDIO_SLC1_TOKEN1_1TO0_INT_RAW_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_S 13 +/** SDIO_SLC1_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DONE_INT_RAW (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_RAW_M (SDIO_SLC1_TX_DONE_INT_RAW_V << SDIO_SLC1_TX_DONE_INT_RAW_S) +#define SDIO_SLC1_TX_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_RAW_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_RAW (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_M (SDIO_SLC1_TX_SUC_EOF_INT_RAW_V << SDIO_SLC1_TX_SUC_EOF_INT_RAW_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_S 15 +/** SDIO_SLC1_RX_DONE_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DONE_INT_RAW (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_RAW_M (SDIO_SLC1_RX_DONE_INT_RAW_V << SDIO_SLC1_RX_DONE_INT_RAW_S) +#define SDIO_SLC1_RX_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_RAW_S 16 +/** SDIO_SLC1_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_EOF_INT_RAW (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_RAW_M (SDIO_SLC1_RX_EOF_INT_RAW_V << SDIO_SLC1_RX_EOF_INT_RAW_S) +#define SDIO_SLC1_RX_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_RAW_S 17 +/** SDIO_SLC1_TOHOST_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOHOST_INT_RAW (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_RAW_M (SDIO_SLC1_TOHOST_INT_RAW_V << SDIO_SLC1_TOHOST_INT_RAW_S) +#define SDIO_SLC1_TOHOST_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_RAW_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_M (SDIO_SLC1_TX_DSCR_ERR_INT_RAW_V << SDIO_SLC1_TX_DSCR_ERR_INT_RAW_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_M (SDIO_SLC1_RX_DSCR_ERR_INT_RAW_V << SDIO_SLC1_RX_DSCR_ERR_INT_RAW_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_RAW (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_M (SDIO_SLC1_HOST_RD_ACK_INT_RAW_V << SDIO_SLC1_HOST_RD_ACK_INT_RAW_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_M (SDIO_SLC1_WR_RETRY_DONE_INT_RAW_V << SDIO_SLC1_WR_RETRY_DONE_INT_RAW_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_RAW (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_M (SDIO_SLC1_TX_ERR_EOF_INT_RAW_V << SDIO_SLC1_TX_ERR_EOF_INT_RAW_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_S 24 + +/** SDIO_SLC1INT_ST_REG register + * reserved + */ +#define SDIO_SLC1INT_ST_REG (DR_REG_SLC_BASE + 0x18) +/** SDIO_SLC_FRHOST_BIT8_INT_ST : RO; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT8_INT_ST (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_ST_M (SDIO_SLC_FRHOST_BIT8_INT_ST_V << SDIO_SLC_FRHOST_BIT8_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT8_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_ST_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_ST : RO; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT9_INT_ST (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_ST_M (SDIO_SLC_FRHOST_BIT9_INT_ST_V << SDIO_SLC_FRHOST_BIT9_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT9_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_ST_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_ST : RO; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT10_INT_ST (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_ST_M (SDIO_SLC_FRHOST_BIT10_INT_ST_V << SDIO_SLC_FRHOST_BIT10_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT10_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_ST_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_ST : RO; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT11_INT_ST (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_ST_M (SDIO_SLC_FRHOST_BIT11_INT_ST_V << SDIO_SLC_FRHOST_BIT11_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT11_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_ST_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_ST : RO; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT12_INT_ST (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_ST_M (SDIO_SLC_FRHOST_BIT12_INT_ST_V << SDIO_SLC_FRHOST_BIT12_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT12_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_ST_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_ST : RO; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT13_INT_ST (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_ST_M (SDIO_SLC_FRHOST_BIT13_INT_ST_V << SDIO_SLC_FRHOST_BIT13_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT13_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_ST_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_ST : RO; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT14_INT_ST (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_ST_M (SDIO_SLC_FRHOST_BIT14_INT_ST_V << SDIO_SLC_FRHOST_BIT14_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT14_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_ST_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_ST : RO; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT15_INT_ST (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_ST_M (SDIO_SLC_FRHOST_BIT15_INT_ST_V << SDIO_SLC_FRHOST_BIT15_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT15_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_ST_S 7 +/** SDIO_SLC1_RX_START_INT_ST : RO; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_START_INT_ST (BIT(8)) +#define SDIO_SLC1_RX_START_INT_ST_M (SDIO_SLC1_RX_START_INT_ST_V << SDIO_SLC1_RX_START_INT_ST_S) +#define SDIO_SLC1_RX_START_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_ST_S 8 +/** SDIO_SLC1_TX_START_INT_ST : RO; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_START_INT_ST (BIT(9)) +#define SDIO_SLC1_TX_START_INT_ST_M (SDIO_SLC1_TX_START_INT_ST_V << SDIO_SLC1_TX_START_INT_ST_S) +#define SDIO_SLC1_TX_START_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_ST_S 9 +/** SDIO_SLC1_RX_UDF_INT_ST : RO; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_UDF_INT_ST (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_ST_M (SDIO_SLC1_RX_UDF_INT_ST_V << SDIO_SLC1_RX_UDF_INT_ST_S) +#define SDIO_SLC1_RX_UDF_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_ST_S 10 +/** SDIO_SLC1_TX_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_OVF_INT_ST (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_ST_M (SDIO_SLC1_TX_OVF_INT_ST_V << SDIO_SLC1_TX_OVF_INT_ST_S) +#define SDIO_SLC1_TX_OVF_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_ST_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_ST : RO; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_M (SDIO_SLC1_TOKEN0_1TO0_INT_ST_V << SDIO_SLC1_TOKEN0_1TO0_INT_ST_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_ST : RO; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_M (SDIO_SLC1_TOKEN1_1TO0_INT_ST_V << SDIO_SLC1_TOKEN1_1TO0_INT_ST_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_S 13 +/** SDIO_SLC1_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DONE_INT_ST (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_ST_M (SDIO_SLC1_TX_DONE_INT_ST_V << SDIO_SLC1_TX_DONE_INT_ST_S) +#define SDIO_SLC1_TX_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_ST_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_ST : RO; bitpos: [15]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_ST (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_ST_M (SDIO_SLC1_TX_SUC_EOF_INT_ST_V << SDIO_SLC1_TX_SUC_EOF_INT_ST_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_ST_S 15 +/** SDIO_SLC1_RX_DONE_INT_ST : RO; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DONE_INT_ST (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_ST_M (SDIO_SLC1_RX_DONE_INT_ST_V << SDIO_SLC1_RX_DONE_INT_ST_S) +#define SDIO_SLC1_RX_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_ST_S 16 +/** SDIO_SLC1_RX_EOF_INT_ST : RO; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_EOF_INT_ST (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_ST_M (SDIO_SLC1_RX_EOF_INT_ST_V << SDIO_SLC1_RX_EOF_INT_ST_S) +#define SDIO_SLC1_RX_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_ST_S 17 +/** SDIO_SLC1_TOHOST_INT_ST : RO; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOHOST_INT_ST (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_ST_M (SDIO_SLC1_TOHOST_INT_ST_V << SDIO_SLC1_TOHOST_INT_ST_S) +#define SDIO_SLC1_TOHOST_INT_ST_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_ST_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_ST : RO; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_M (SDIO_SLC1_TX_DSCR_ERR_INT_ST_V << SDIO_SLC1_TX_DSCR_ERR_INT_ST_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_ST : RO; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_M (SDIO_SLC1_RX_DSCR_ERR_INT_ST_V << SDIO_SLC1_RX_DSCR_ERR_INT_ST_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ST : RO; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_ST : RO; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_ST (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_ST_M (SDIO_SLC1_HOST_RD_ACK_INT_ST_V << SDIO_SLC1_HOST_RD_ACK_INT_ST_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_ST_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_ST_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_ST : RO; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_M (SDIO_SLC1_WR_RETRY_DONE_INT_ST_V << SDIO_SLC1_WR_RETRY_DONE_INT_ST_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_ST : RO; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_ST (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_ST_M (SDIO_SLC1_TX_ERR_EOF_INT_ST_V << SDIO_SLC1_TX_ERR_EOF_INT_ST_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_ST_S 24 + +/** SDIO_SLC1INT_ENA_REG register + * reserved + */ +#define SDIO_SLC1INT_ENA_REG (DR_REG_SLC_BASE + 0x1c) +/** SDIO_SLC_FRHOST_BIT8_INT_ENA : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT8_INT_ENA (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_ENA_M (SDIO_SLC_FRHOST_BIT8_INT_ENA_V << SDIO_SLC_FRHOST_BIT8_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT8_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_ENA_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_ENA : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT9_INT_ENA (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_ENA_M (SDIO_SLC_FRHOST_BIT9_INT_ENA_V << SDIO_SLC_FRHOST_BIT9_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT9_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_ENA_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_ENA : R/W; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT10_INT_ENA (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_ENA_M (SDIO_SLC_FRHOST_BIT10_INT_ENA_V << SDIO_SLC_FRHOST_BIT10_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT10_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_ENA_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_ENA : R/W; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT11_INT_ENA (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_ENA_M (SDIO_SLC_FRHOST_BIT11_INT_ENA_V << SDIO_SLC_FRHOST_BIT11_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT11_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_ENA_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_ENA : R/W; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT12_INT_ENA (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_ENA_M (SDIO_SLC_FRHOST_BIT12_INT_ENA_V << SDIO_SLC_FRHOST_BIT12_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT12_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_ENA_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_ENA : R/W; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT13_INT_ENA (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_ENA_M (SDIO_SLC_FRHOST_BIT13_INT_ENA_V << SDIO_SLC_FRHOST_BIT13_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT13_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_ENA_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_ENA : R/W; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT14_INT_ENA (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_ENA_M (SDIO_SLC_FRHOST_BIT14_INT_ENA_V << SDIO_SLC_FRHOST_BIT14_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT14_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_ENA_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_ENA : R/W; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT15_INT_ENA (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_ENA_M (SDIO_SLC_FRHOST_BIT15_INT_ENA_V << SDIO_SLC_FRHOST_BIT15_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT15_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_ENA_S 7 +/** SDIO_SLC1_RX_START_INT_ENA : R/W; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_START_INT_ENA (BIT(8)) +#define SDIO_SLC1_RX_START_INT_ENA_M (SDIO_SLC1_RX_START_INT_ENA_V << SDIO_SLC1_RX_START_INT_ENA_S) +#define SDIO_SLC1_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_ENA_S 8 +/** SDIO_SLC1_TX_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_START_INT_ENA (BIT(9)) +#define SDIO_SLC1_TX_START_INT_ENA_M (SDIO_SLC1_TX_START_INT_ENA_V << SDIO_SLC1_TX_START_INT_ENA_S) +#define SDIO_SLC1_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_ENA_S 9 +/** SDIO_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_UDF_INT_ENA (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_ENA_M (SDIO_SLC1_RX_UDF_INT_ENA_V << SDIO_SLC1_RX_UDF_INT_ENA_S) +#define SDIO_SLC1_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_ENA_S 10 +/** SDIO_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_OVF_INT_ENA (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_ENA_M (SDIO_SLC1_TX_OVF_INT_ENA_V << SDIO_SLC1_TX_OVF_INT_ENA_S) +#define SDIO_SLC1_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_ENA_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_M (SDIO_SLC1_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC1_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_M (SDIO_SLC1_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC1_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_S 13 +/** SDIO_SLC1_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DONE_INT_ENA (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_ENA_M (SDIO_SLC1_TX_DONE_INT_ENA_V << SDIO_SLC1_TX_DONE_INT_ENA_S) +#define SDIO_SLC1_TX_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_ENA_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_ENA : R/W; bitpos: [15]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_M (SDIO_SLC1_TX_SUC_EOF_INT_ENA_V << SDIO_SLC1_TX_SUC_EOF_INT_ENA_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_S 15 +/** SDIO_SLC1_RX_DONE_INT_ENA : R/W; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DONE_INT_ENA (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_ENA_M (SDIO_SLC1_RX_DONE_INT_ENA_V << SDIO_SLC1_RX_DONE_INT_ENA_S) +#define SDIO_SLC1_RX_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_ENA_S 16 +/** SDIO_SLC1_RX_EOF_INT_ENA : R/W; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_EOF_INT_ENA (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_ENA_M (SDIO_SLC1_RX_EOF_INT_ENA_V << SDIO_SLC1_RX_EOF_INT_ENA_S) +#define SDIO_SLC1_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_ENA_S 17 +/** SDIO_SLC1_TOHOST_INT_ENA : R/W; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOHOST_INT_ENA (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_ENA_M (SDIO_SLC1_TOHOST_INT_ENA_V << SDIO_SLC1_TOHOST_INT_ENA_S) +#define SDIO_SLC1_TOHOST_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_ENA_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_ENA : R/W; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_M (SDIO_SLC1_TX_DSCR_ERR_INT_ENA_V << SDIO_SLC1_TX_DSCR_ERR_INT_ENA_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_ENA : R/W; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_M (SDIO_SLC1_RX_DSCR_ERR_INT_ENA_V << SDIO_SLC1_RX_DSCR_ERR_INT_ENA_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA : R/W; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_ENA : R/W; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_M (SDIO_SLC1_HOST_RD_ACK_INT_ENA_V << SDIO_SLC1_HOST_RD_ACK_INT_ENA_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_ENA : R/W; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_M (SDIO_SLC1_WR_RETRY_DONE_INT_ENA_V << SDIO_SLC1_WR_RETRY_DONE_INT_ENA_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_ENA : R/W; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_M (SDIO_SLC1_TX_ERR_EOF_INT_ENA_V << SDIO_SLC1_TX_ERR_EOF_INT_ENA_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_S 24 + +/** SDIO_SLC1INT_CLR_REG register + * reserved + */ +#define SDIO_SLC1INT_CLR_REG (DR_REG_SLC_BASE + 0x20) +/** SDIO_SLC_FRHOST_BIT8_INT_CLR : WT; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT8_INT_CLR (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_CLR_M (SDIO_SLC_FRHOST_BIT8_INT_CLR_V << SDIO_SLC_FRHOST_BIT8_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT8_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_CLR_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_CLR : WT; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT9_INT_CLR (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_CLR_M (SDIO_SLC_FRHOST_BIT9_INT_CLR_V << SDIO_SLC_FRHOST_BIT9_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT9_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_CLR_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_CLR : WT; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT10_INT_CLR (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_CLR_M (SDIO_SLC_FRHOST_BIT10_INT_CLR_V << SDIO_SLC_FRHOST_BIT10_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT10_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_CLR_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_CLR : WT; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT11_INT_CLR (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_CLR_M (SDIO_SLC_FRHOST_BIT11_INT_CLR_V << SDIO_SLC_FRHOST_BIT11_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT11_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_CLR_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_CLR : WT; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT12_INT_CLR (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_CLR_M (SDIO_SLC_FRHOST_BIT12_INT_CLR_V << SDIO_SLC_FRHOST_BIT12_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT12_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_CLR_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_CLR : WT; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT13_INT_CLR (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_CLR_M (SDIO_SLC_FRHOST_BIT13_INT_CLR_V << SDIO_SLC_FRHOST_BIT13_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT13_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_CLR_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_CLR : WT; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT14_INT_CLR (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_CLR_M (SDIO_SLC_FRHOST_BIT14_INT_CLR_V << SDIO_SLC_FRHOST_BIT14_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT14_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_CLR_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_CLR : WT; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT15_INT_CLR (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_CLR_M (SDIO_SLC_FRHOST_BIT15_INT_CLR_V << SDIO_SLC_FRHOST_BIT15_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT15_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_CLR_S 7 +/** SDIO_SLC1_RX_START_INT_CLR : WT; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_START_INT_CLR (BIT(8)) +#define SDIO_SLC1_RX_START_INT_CLR_M (SDIO_SLC1_RX_START_INT_CLR_V << SDIO_SLC1_RX_START_INT_CLR_S) +#define SDIO_SLC1_RX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_CLR_S 8 +/** SDIO_SLC1_TX_START_INT_CLR : WT; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_START_INT_CLR (BIT(9)) +#define SDIO_SLC1_TX_START_INT_CLR_M (SDIO_SLC1_TX_START_INT_CLR_V << SDIO_SLC1_TX_START_INT_CLR_S) +#define SDIO_SLC1_TX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_CLR_S 9 +/** SDIO_SLC1_RX_UDF_INT_CLR : WT; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_UDF_INT_CLR (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_CLR_M (SDIO_SLC1_RX_UDF_INT_CLR_V << SDIO_SLC1_RX_UDF_INT_CLR_S) +#define SDIO_SLC1_RX_UDF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_CLR_S 10 +/** SDIO_SLC1_TX_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_OVF_INT_CLR (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_CLR_M (SDIO_SLC1_TX_OVF_INT_CLR_V << SDIO_SLC1_TX_OVF_INT_CLR_S) +#define SDIO_SLC1_TX_OVF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_CLR_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_CLR : WT; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_M (SDIO_SLC1_TOKEN0_1TO0_INT_CLR_V << SDIO_SLC1_TOKEN0_1TO0_INT_CLR_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_CLR : WT; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_M (SDIO_SLC1_TOKEN1_1TO0_INT_CLR_V << SDIO_SLC1_TOKEN1_1TO0_INT_CLR_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_S 13 +/** SDIO_SLC1_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DONE_INT_CLR (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_CLR_M (SDIO_SLC1_TX_DONE_INT_CLR_V << SDIO_SLC1_TX_DONE_INT_CLR_S) +#define SDIO_SLC1_TX_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_CLR_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_CLR : WT; bitpos: [15]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_CLR (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_M (SDIO_SLC1_TX_SUC_EOF_INT_CLR_V << SDIO_SLC1_TX_SUC_EOF_INT_CLR_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_S 15 +/** SDIO_SLC1_RX_DONE_INT_CLR : WT; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DONE_INT_CLR (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_CLR_M (SDIO_SLC1_RX_DONE_INT_CLR_V << SDIO_SLC1_RX_DONE_INT_CLR_S) +#define SDIO_SLC1_RX_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_CLR_S 16 +/** SDIO_SLC1_RX_EOF_INT_CLR : WT; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_EOF_INT_CLR (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_CLR_M (SDIO_SLC1_RX_EOF_INT_CLR_V << SDIO_SLC1_RX_EOF_INT_CLR_S) +#define SDIO_SLC1_RX_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_CLR_S 17 +/** SDIO_SLC1_TOHOST_INT_CLR : WT; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOHOST_INT_CLR (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_CLR_M (SDIO_SLC1_TOHOST_INT_CLR_V << SDIO_SLC1_TOHOST_INT_CLR_S) +#define SDIO_SLC1_TOHOST_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_CLR_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_CLR : WT; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_M (SDIO_SLC1_TX_DSCR_ERR_INT_CLR_V << SDIO_SLC1_TX_DSCR_ERR_INT_CLR_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_CLR : WT; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_M (SDIO_SLC1_RX_DSCR_ERR_INT_CLR_V << SDIO_SLC1_RX_DSCR_ERR_INT_CLR_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR : WT; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_CLR : WT; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_CLR (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_M (SDIO_SLC1_HOST_RD_ACK_INT_CLR_V << SDIO_SLC1_HOST_RD_ACK_INT_CLR_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_CLR : WT; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_M (SDIO_SLC1_WR_RETRY_DONE_INT_CLR_V << SDIO_SLC1_WR_RETRY_DONE_INT_CLR_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_CLR : WT; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_CLR (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_M (SDIO_SLC1_TX_ERR_EOF_INT_CLR_V << SDIO_SLC1_TX_ERR_EOF_INT_CLR_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_S 24 + +/** SDIO_SLCRX_STATUS_REG register + * ******* Description *********** + */ +#define SDIO_SLCRX_STATUS_REG (DR_REG_SLC_BASE + 0x24) +/** SDIO_SLC0_RX_FULL : RO; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_FULL (BIT(0)) +#define SDIO_SLC0_RX_FULL_M (SDIO_SLC0_RX_FULL_V << SDIO_SLC0_RX_FULL_S) +#define SDIO_SLC0_RX_FULL_V 0x00000001U +#define SDIO_SLC0_RX_FULL_S 0 +/** SDIO_SLC0_RX_EMPTY : RO; bitpos: [1]; default: 1; + * reserved + */ +#define SDIO_SLC0_RX_EMPTY (BIT(1)) +#define SDIO_SLC0_RX_EMPTY_M (SDIO_SLC0_RX_EMPTY_V << SDIO_SLC0_RX_EMPTY_S) +#define SDIO_SLC0_RX_EMPTY_V 0x00000001U +#define SDIO_SLC0_RX_EMPTY_S 1 +/** SDIO_SLC0_RX_BUF_LEN : RO; bitpos: [15:2]; default: 0; + * the current buffer length when slc0 reads data from rx link + */ +#define SDIO_SLC0_RX_BUF_LEN 0x00003FFFU +#define SDIO_SLC0_RX_BUF_LEN_M (SDIO_SLC0_RX_BUF_LEN_V << SDIO_SLC0_RX_BUF_LEN_S) +#define SDIO_SLC0_RX_BUF_LEN_V 0x00003FFFU +#define SDIO_SLC0_RX_BUF_LEN_S 2 +/** SDIO_SLC1_RX_FULL : RO; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_FULL (BIT(16)) +#define SDIO_SLC1_RX_FULL_M (SDIO_SLC1_RX_FULL_V << SDIO_SLC1_RX_FULL_S) +#define SDIO_SLC1_RX_FULL_V 0x00000001U +#define SDIO_SLC1_RX_FULL_S 16 +/** SDIO_SLC1_RX_EMPTY : RO; bitpos: [17]; default: 1; + * reserved + */ +#define SDIO_SLC1_RX_EMPTY (BIT(17)) +#define SDIO_SLC1_RX_EMPTY_M (SDIO_SLC1_RX_EMPTY_V << SDIO_SLC1_RX_EMPTY_S) +#define SDIO_SLC1_RX_EMPTY_V 0x00000001U +#define SDIO_SLC1_RX_EMPTY_S 17 +/** SDIO_SLC1_RX_BUF_LEN : RO; bitpos: [31:18]; default: 0; + * the current buffer length when slc1 reads data from rx link + */ +#define SDIO_SLC1_RX_BUF_LEN 0x00003FFFU +#define SDIO_SLC1_RX_BUF_LEN_M (SDIO_SLC1_RX_BUF_LEN_V << SDIO_SLC1_RX_BUF_LEN_S) +#define SDIO_SLC1_RX_BUF_LEN_V 0x00003FFFU +#define SDIO_SLC1_RX_BUF_LEN_S 18 + +/** SDIO_SLC0RXFIFO_PUSH_REG register + * ******* Description *********** + */ +#define SDIO_SLC0RXFIFO_PUSH_REG (DR_REG_SLC_BASE + 0x28) +/** SDIO_SLC0_RXFIFO_WDATA : R/W; bitpos: [8:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RXFIFO_WDATA 0x000001FFU +#define SDIO_SLC0_RXFIFO_WDATA_M (SDIO_SLC0_RXFIFO_WDATA_V << SDIO_SLC0_RXFIFO_WDATA_S) +#define SDIO_SLC0_RXFIFO_WDATA_V 0x000001FFU +#define SDIO_SLC0_RXFIFO_WDATA_S 0 +/** SDIO_SLC0_RXFIFO_PUSH : R/W/SC; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC0_RXFIFO_PUSH (BIT(16)) +#define SDIO_SLC0_RXFIFO_PUSH_M (SDIO_SLC0_RXFIFO_PUSH_V << SDIO_SLC0_RXFIFO_PUSH_S) +#define SDIO_SLC0_RXFIFO_PUSH_V 0x00000001U +#define SDIO_SLC0_RXFIFO_PUSH_S 16 + +/** SDIO_SLC1RXFIFO_PUSH_REG register + * reserved + */ +#define SDIO_SLC1RXFIFO_PUSH_REG (DR_REG_SLC_BASE + 0x2c) +/** SDIO_SLC1_RXFIFO_WDATA : R/W; bitpos: [8:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_RXFIFO_WDATA 0x000001FFU +#define SDIO_SLC1_RXFIFO_WDATA_M (SDIO_SLC1_RXFIFO_WDATA_V << SDIO_SLC1_RXFIFO_WDATA_S) +#define SDIO_SLC1_RXFIFO_WDATA_V 0x000001FFU +#define SDIO_SLC1_RXFIFO_WDATA_S 0 +/** SDIO_SLC1_RXFIFO_PUSH : R/W/SC; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC1_RXFIFO_PUSH (BIT(16)) +#define SDIO_SLC1_RXFIFO_PUSH_M (SDIO_SLC1_RXFIFO_PUSH_V << SDIO_SLC1_RXFIFO_PUSH_S) +#define SDIO_SLC1_RXFIFO_PUSH_V 0x00000001U +#define SDIO_SLC1_RXFIFO_PUSH_S 16 + +/** SDIO_SLCTX_STATUS_REG register + * ******* Description *********** + */ +#define SDIO_SLCTX_STATUS_REG (DR_REG_SLC_BASE + 0x30) +/** SDIO_SLC0_TX_FULL : RO; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_FULL (BIT(0)) +#define SDIO_SLC0_TX_FULL_M (SDIO_SLC0_TX_FULL_V << SDIO_SLC0_TX_FULL_S) +#define SDIO_SLC0_TX_FULL_V 0x00000001U +#define SDIO_SLC0_TX_FULL_S 0 +/** SDIO_SLC0_TX_EMPTY : RO; bitpos: [1]; default: 1; + * reserved + */ +#define SDIO_SLC0_TX_EMPTY (BIT(1)) +#define SDIO_SLC0_TX_EMPTY_M (SDIO_SLC0_TX_EMPTY_V << SDIO_SLC0_TX_EMPTY_S) +#define SDIO_SLC0_TX_EMPTY_V 0x00000001U +#define SDIO_SLC0_TX_EMPTY_S 1 +/** SDIO_SLC1_TX_FULL : RO; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_FULL (BIT(16)) +#define SDIO_SLC1_TX_FULL_M (SDIO_SLC1_TX_FULL_V << SDIO_SLC1_TX_FULL_S) +#define SDIO_SLC1_TX_FULL_V 0x00000001U +#define SDIO_SLC1_TX_FULL_S 16 +/** SDIO_SLC1_TX_EMPTY : RO; bitpos: [17]; default: 1; + * reserved + */ +#define SDIO_SLC1_TX_EMPTY (BIT(17)) +#define SDIO_SLC1_TX_EMPTY_M (SDIO_SLC1_TX_EMPTY_V << SDIO_SLC1_TX_EMPTY_S) +#define SDIO_SLC1_TX_EMPTY_V 0x00000001U +#define SDIO_SLC1_TX_EMPTY_S 17 + +/** SDIO_SLC0TXFIFO_POP_REG register + * reserved + */ +#define SDIO_SLC0TXFIFO_POP_REG (DR_REG_SLC_BASE + 0x34) +/** SDIO_SLC0_TXFIFO_RDATA : RO; bitpos: [10:0]; default: 1024; + * reserved + */ +#define SDIO_SLC0_TXFIFO_RDATA 0x000007FFU +#define SDIO_SLC0_TXFIFO_RDATA_M (SDIO_SLC0_TXFIFO_RDATA_V << SDIO_SLC0_TXFIFO_RDATA_S) +#define SDIO_SLC0_TXFIFO_RDATA_V 0x000007FFU +#define SDIO_SLC0_TXFIFO_RDATA_S 0 +/** SDIO_SLC0_TXFIFO_POP : R/W/SC; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXFIFO_POP (BIT(16)) +#define SDIO_SLC0_TXFIFO_POP_M (SDIO_SLC0_TXFIFO_POP_V << SDIO_SLC0_TXFIFO_POP_S) +#define SDIO_SLC0_TXFIFO_POP_V 0x00000001U +#define SDIO_SLC0_TXFIFO_POP_S 16 + +/** SDIO_SLC1TXFIFO_POP_REG register + * reserved + */ +#define SDIO_SLC1TXFIFO_POP_REG (DR_REG_SLC_BASE + 0x38) +/** SDIO_SLC1_TXFIFO_RDATA : RO; bitpos: [10:0]; default: 1024; + * reserved + */ +#define SDIO_SLC1_TXFIFO_RDATA 0x000007FFU +#define SDIO_SLC1_TXFIFO_RDATA_M (SDIO_SLC1_TXFIFO_RDATA_V << SDIO_SLC1_TXFIFO_RDATA_S) +#define SDIO_SLC1_TXFIFO_RDATA_V 0x000007FFU +#define SDIO_SLC1_TXFIFO_RDATA_S 0 +/** SDIO_SLC1_TXFIFO_POP : R/W/SC; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXFIFO_POP (BIT(16)) +#define SDIO_SLC1_TXFIFO_POP_M (SDIO_SLC1_TXFIFO_POP_V << SDIO_SLC1_TXFIFO_POP_S) +#define SDIO_SLC1_TXFIFO_POP_V 0x00000001U +#define SDIO_SLC1_TXFIFO_POP_S 16 + +/** SDIO_SLC0RX_LINK_REG register + * reserved + */ +#define SDIO_SLC0RX_LINK_REG (DR_REG_SLC_BASE + 0x3c) +/** SDIO_SLC0_RXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; + * reserved + */ +#define SDIO_SLC0_RXLINK_STOP (BIT(28)) +#define SDIO_SLC0_RXLINK_STOP_M (SDIO_SLC0_RXLINK_STOP_V << SDIO_SLC0_RXLINK_STOP_S) +#define SDIO_SLC0_RXLINK_STOP_V 0x00000001U +#define SDIO_SLC0_RXLINK_STOP_S 28 +/** SDIO_SLC0_RXLINK_START : R/W/SC; bitpos: [29]; default: 0; + * reserved + */ +#define SDIO_SLC0_RXLINK_START (BIT(29)) +#define SDIO_SLC0_RXLINK_START_M (SDIO_SLC0_RXLINK_START_V << SDIO_SLC0_RXLINK_START_S) +#define SDIO_SLC0_RXLINK_START_V 0x00000001U +#define SDIO_SLC0_RXLINK_START_S 29 +/** SDIO_SLC0_RXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; + * reserved + */ +#define SDIO_SLC0_RXLINK_RESTART (BIT(30)) +#define SDIO_SLC0_RXLINK_RESTART_M (SDIO_SLC0_RXLINK_RESTART_V << SDIO_SLC0_RXLINK_RESTART_S) +#define SDIO_SLC0_RXLINK_RESTART_V 0x00000001U +#define SDIO_SLC0_RXLINK_RESTART_S 30 +/** SDIO_SLC0_RXLINK_PARK : RO; bitpos: [31]; default: 1; + * reserved + */ +#define SDIO_SLC0_RXLINK_PARK (BIT(31)) +#define SDIO_SLC0_RXLINK_PARK_M (SDIO_SLC0_RXLINK_PARK_V << SDIO_SLC0_RXLINK_PARK_S) +#define SDIO_SLC0_RXLINK_PARK_V 0x00000001U +#define SDIO_SLC0_RXLINK_PARK_S 31 + +/** SDIO_SLC0RX_LINK_ADDR_REG register + * reserved + */ +#define SDIO_SLC0RX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x40) +/** SDIO_SLC0_RXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RXLINK_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_ADDR_M (SDIO_SLC0_RXLINK_ADDR_V << SDIO_SLC0_RXLINK_ADDR_S) +#define SDIO_SLC0_RXLINK_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_ADDR_S 0 + +/** SDIO_SLC0TX_LINK_REG register + * reserved + */ +#define SDIO_SLC0TX_LINK_REG (DR_REG_SLC_BASE + 0x44) +/** SDIO_SLC0_TXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXLINK_STOP (BIT(28)) +#define SDIO_SLC0_TXLINK_STOP_M (SDIO_SLC0_TXLINK_STOP_V << SDIO_SLC0_TXLINK_STOP_S) +#define SDIO_SLC0_TXLINK_STOP_V 0x00000001U +#define SDIO_SLC0_TXLINK_STOP_S 28 +/** SDIO_SLC0_TXLINK_START : R/W/SC; bitpos: [29]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXLINK_START (BIT(29)) +#define SDIO_SLC0_TXLINK_START_M (SDIO_SLC0_TXLINK_START_V << SDIO_SLC0_TXLINK_START_S) +#define SDIO_SLC0_TXLINK_START_V 0x00000001U +#define SDIO_SLC0_TXLINK_START_S 29 +/** SDIO_SLC0_TXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXLINK_RESTART (BIT(30)) +#define SDIO_SLC0_TXLINK_RESTART_M (SDIO_SLC0_TXLINK_RESTART_V << SDIO_SLC0_TXLINK_RESTART_S) +#define SDIO_SLC0_TXLINK_RESTART_V 0x00000001U +#define SDIO_SLC0_TXLINK_RESTART_S 30 +/** SDIO_SLC0_TXLINK_PARK : RO; bitpos: [31]; default: 1; + * reserved + */ +#define SDIO_SLC0_TXLINK_PARK (BIT(31)) +#define SDIO_SLC0_TXLINK_PARK_M (SDIO_SLC0_TXLINK_PARK_V << SDIO_SLC0_TXLINK_PARK_S) +#define SDIO_SLC0_TXLINK_PARK_V 0x00000001U +#define SDIO_SLC0_TXLINK_PARK_S 31 + +/** SDIO_SLC0TX_LINK_ADDR_REG register + * reserved + */ +#define SDIO_SLC0TX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x48) +/** SDIO_SLC0_TXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXLINK_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_ADDR_M (SDIO_SLC0_TXLINK_ADDR_V << SDIO_SLC0_TXLINK_ADDR_S) +#define SDIO_SLC0_TXLINK_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_ADDR_S 0 + +/** SDIO_SLC1RX_LINK_REG register + * reserved + */ +#define SDIO_SLC1RX_LINK_REG (DR_REG_SLC_BASE + 0x4c) +/** SDIO_SLC1_BT_PACKET : R/W; bitpos: [20]; default: 1; + * reserved + */ +#define SDIO_SLC1_BT_PACKET (BIT(20)) +#define SDIO_SLC1_BT_PACKET_M (SDIO_SLC1_BT_PACKET_V << SDIO_SLC1_BT_PACKET_S) +#define SDIO_SLC1_BT_PACKET_V 0x00000001U +#define SDIO_SLC1_BT_PACKET_S 20 +/** SDIO_SLC1_RXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; + * reserved + */ +#define SDIO_SLC1_RXLINK_STOP (BIT(28)) +#define SDIO_SLC1_RXLINK_STOP_M (SDIO_SLC1_RXLINK_STOP_V << SDIO_SLC1_RXLINK_STOP_S) +#define SDIO_SLC1_RXLINK_STOP_V 0x00000001U +#define SDIO_SLC1_RXLINK_STOP_S 28 +/** SDIO_SLC1_RXLINK_START : R/W/SC; bitpos: [29]; default: 0; + * reserved + */ +#define SDIO_SLC1_RXLINK_START (BIT(29)) +#define SDIO_SLC1_RXLINK_START_M (SDIO_SLC1_RXLINK_START_V << SDIO_SLC1_RXLINK_START_S) +#define SDIO_SLC1_RXLINK_START_V 0x00000001U +#define SDIO_SLC1_RXLINK_START_S 29 +/** SDIO_SLC1_RXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; + * reserved + */ +#define SDIO_SLC1_RXLINK_RESTART (BIT(30)) +#define SDIO_SLC1_RXLINK_RESTART_M (SDIO_SLC1_RXLINK_RESTART_V << SDIO_SLC1_RXLINK_RESTART_S) +#define SDIO_SLC1_RXLINK_RESTART_V 0x00000001U +#define SDIO_SLC1_RXLINK_RESTART_S 30 +/** SDIO_SLC1_RXLINK_PARK : RO; bitpos: [31]; default: 1; + * reserved + */ +#define SDIO_SLC1_RXLINK_PARK (BIT(31)) +#define SDIO_SLC1_RXLINK_PARK_M (SDIO_SLC1_RXLINK_PARK_V << SDIO_SLC1_RXLINK_PARK_S) +#define SDIO_SLC1_RXLINK_PARK_V 0x00000001U +#define SDIO_SLC1_RXLINK_PARK_S 31 + +/** SDIO_SLC1RX_LINK_ADDR_REG register + * reserved + */ +#define SDIO_SLC1RX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x50) +/** SDIO_SLC1_RXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_RXLINK_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_ADDR_M (SDIO_SLC1_RXLINK_ADDR_V << SDIO_SLC1_RXLINK_ADDR_S) +#define SDIO_SLC1_RXLINK_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_ADDR_S 0 + +/** SDIO_SLC1TX_LINK_REG register + * reserved + */ +#define SDIO_SLC1TX_LINK_REG (DR_REG_SLC_BASE + 0x54) +/** SDIO_SLC1_TXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXLINK_STOP (BIT(28)) +#define SDIO_SLC1_TXLINK_STOP_M (SDIO_SLC1_TXLINK_STOP_V << SDIO_SLC1_TXLINK_STOP_S) +#define SDIO_SLC1_TXLINK_STOP_V 0x00000001U +#define SDIO_SLC1_TXLINK_STOP_S 28 +/** SDIO_SLC1_TXLINK_START : R/W/SC; bitpos: [29]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXLINK_START (BIT(29)) +#define SDIO_SLC1_TXLINK_START_M (SDIO_SLC1_TXLINK_START_V << SDIO_SLC1_TXLINK_START_S) +#define SDIO_SLC1_TXLINK_START_V 0x00000001U +#define SDIO_SLC1_TXLINK_START_S 29 +/** SDIO_SLC1_TXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXLINK_RESTART (BIT(30)) +#define SDIO_SLC1_TXLINK_RESTART_M (SDIO_SLC1_TXLINK_RESTART_V << SDIO_SLC1_TXLINK_RESTART_S) +#define SDIO_SLC1_TXLINK_RESTART_V 0x00000001U +#define SDIO_SLC1_TXLINK_RESTART_S 30 +/** SDIO_SLC1_TXLINK_PARK : RO; bitpos: [31]; default: 1; + * reserved + */ +#define SDIO_SLC1_TXLINK_PARK (BIT(31)) +#define SDIO_SLC1_TXLINK_PARK_M (SDIO_SLC1_TXLINK_PARK_V << SDIO_SLC1_TXLINK_PARK_S) +#define SDIO_SLC1_TXLINK_PARK_V 0x00000001U +#define SDIO_SLC1_TXLINK_PARK_S 31 + +/** SDIO_SLC1TX_LINK_ADDR_REG register + * reserved + */ +#define SDIO_SLC1TX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x58) +/** SDIO_SLC1_TXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXLINK_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_ADDR_M (SDIO_SLC1_TXLINK_ADDR_V << SDIO_SLC1_TXLINK_ADDR_S) +#define SDIO_SLC1_TXLINK_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_ADDR_S 0 + +/** SDIO_SLCINTVEC_TOHOST_REG register + * reserved + */ +#define SDIO_SLCINTVEC_TOHOST_REG (DR_REG_SLC_BASE + 0x5c) +/** SDIO_SLC0_TOHOST_INTVEC : WT; bitpos: [7:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOHOST_INTVEC 0x000000FFU +#define SDIO_SLC0_TOHOST_INTVEC_M (SDIO_SLC0_TOHOST_INTVEC_V << SDIO_SLC0_TOHOST_INTVEC_S) +#define SDIO_SLC0_TOHOST_INTVEC_V 0x000000FFU +#define SDIO_SLC0_TOHOST_INTVEC_S 0 +/** SDIO_SLC1_TOHOST_INTVEC : WT; bitpos: [23:16]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOHOST_INTVEC 0x000000FFU +#define SDIO_SLC1_TOHOST_INTVEC_M (SDIO_SLC1_TOHOST_INTVEC_V << SDIO_SLC1_TOHOST_INTVEC_S) +#define SDIO_SLC1_TOHOST_INTVEC_V 0x000000FFU +#define SDIO_SLC1_TOHOST_INTVEC_S 16 + +/** SDIO_SLC0TOKEN0_REG register + * reserved + */ +#define SDIO_SLC0TOKEN0_REG (DR_REG_SLC_BASE + 0x60) +/** SDIO_SLC0_TOKEN0_WDATA : WT; bitpos: [11:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN0_WDATA 0x00000FFFU +#define SDIO_SLC0_TOKEN0_WDATA_M (SDIO_SLC0_TOKEN0_WDATA_V << SDIO_SLC0_TOKEN0_WDATA_S) +#define SDIO_SLC0_TOKEN0_WDATA_V 0x00000FFFU +#define SDIO_SLC0_TOKEN0_WDATA_S 0 +/** SDIO_SLC0_TOKEN0_WR : WT; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN0_WR (BIT(12)) +#define SDIO_SLC0_TOKEN0_WR_M (SDIO_SLC0_TOKEN0_WR_V << SDIO_SLC0_TOKEN0_WR_S) +#define SDIO_SLC0_TOKEN0_WR_V 0x00000001U +#define SDIO_SLC0_TOKEN0_WR_S 12 +/** SDIO_SLC0_TOKEN0_INC : WT; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN0_INC (BIT(13)) +#define SDIO_SLC0_TOKEN0_INC_M (SDIO_SLC0_TOKEN0_INC_V << SDIO_SLC0_TOKEN0_INC_S) +#define SDIO_SLC0_TOKEN0_INC_V 0x00000001U +#define SDIO_SLC0_TOKEN0_INC_S 13 +/** SDIO_SLC0_TOKEN0_INC_MORE : WT; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN0_INC_MORE (BIT(14)) +#define SDIO_SLC0_TOKEN0_INC_MORE_M (SDIO_SLC0_TOKEN0_INC_MORE_V << SDIO_SLC0_TOKEN0_INC_MORE_S) +#define SDIO_SLC0_TOKEN0_INC_MORE_V 0x00000001U +#define SDIO_SLC0_TOKEN0_INC_MORE_S 14 +/** SDIO_SLC0_TOKEN0 : RO; bitpos: [27:16]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN0 0x00000FFFU +#define SDIO_SLC0_TOKEN0_M (SDIO_SLC0_TOKEN0_V << SDIO_SLC0_TOKEN0_S) +#define SDIO_SLC0_TOKEN0_V 0x00000FFFU +#define SDIO_SLC0_TOKEN0_S 16 + +/** SDIO_SLC0TOKEN1_REG register + * reserved + */ +#define SDIO_SLC0TOKEN1_REG (DR_REG_SLC_BASE + 0x64) +/** SDIO_SLC0_TOKEN1_WDATA : WT; bitpos: [11:0]; default: 0; + * slc0 token1 wdata + */ +#define SDIO_SLC0_TOKEN1_WDATA 0x00000FFFU +#define SDIO_SLC0_TOKEN1_WDATA_M (SDIO_SLC0_TOKEN1_WDATA_V << SDIO_SLC0_TOKEN1_WDATA_S) +#define SDIO_SLC0_TOKEN1_WDATA_V 0x00000FFFU +#define SDIO_SLC0_TOKEN1_WDATA_S 0 +/** SDIO_SLC0_TOKEN1_WR : WT; bitpos: [12]; default: 0; + * update slc0_token1_wdata into slc0 token1 + */ +#define SDIO_SLC0_TOKEN1_WR (BIT(12)) +#define SDIO_SLC0_TOKEN1_WR_M (SDIO_SLC0_TOKEN1_WR_V << SDIO_SLC0_TOKEN1_WR_S) +#define SDIO_SLC0_TOKEN1_WR_V 0x00000001U +#define SDIO_SLC0_TOKEN1_WR_S 12 +/** SDIO_SLC0_TOKEN1_INC : WT; bitpos: [13]; default: 0; + * slc0_token1 becomes to 1 when auto clear slc0_token1, else add 1 to slc0_token1 + */ +#define SDIO_SLC0_TOKEN1_INC (BIT(13)) +#define SDIO_SLC0_TOKEN1_INC_M (SDIO_SLC0_TOKEN1_INC_V << SDIO_SLC0_TOKEN1_INC_S) +#define SDIO_SLC0_TOKEN1_INC_V 0x00000001U +#define SDIO_SLC0_TOKEN1_INC_S 13 +/** SDIO_SLC0_TOKEN1_INC_MORE : WT; bitpos: [14]; default: 0; + * slc0_token1 becomes to slc0_token1_wdata when auto clear slc0_token1, else add + * slc0_token1_wdata to slc0_token1 + */ +#define SDIO_SLC0_TOKEN1_INC_MORE (BIT(14)) +#define SDIO_SLC0_TOKEN1_INC_MORE_M (SDIO_SLC0_TOKEN1_INC_MORE_V << SDIO_SLC0_TOKEN1_INC_MORE_S) +#define SDIO_SLC0_TOKEN1_INC_MORE_V 0x00000001U +#define SDIO_SLC0_TOKEN1_INC_MORE_S 14 +/** SDIO_SLC0_TOKEN1 : RO; bitpos: [27:16]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN1 0x00000FFFU +#define SDIO_SLC0_TOKEN1_M (SDIO_SLC0_TOKEN1_V << SDIO_SLC0_TOKEN1_S) +#define SDIO_SLC0_TOKEN1_V 0x00000FFFU +#define SDIO_SLC0_TOKEN1_S 16 + +/** SDIO_SLC1TOKEN0_REG register + * ******* Description *********** + */ +#define SDIO_SLC1TOKEN0_REG (DR_REG_SLC_BASE + 0x68) +/** SDIO_SLC1_TOKEN0_WDATA : WT; bitpos: [11:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN0_WDATA 0x00000FFFU +#define SDIO_SLC1_TOKEN0_WDATA_M (SDIO_SLC1_TOKEN0_WDATA_V << SDIO_SLC1_TOKEN0_WDATA_S) +#define SDIO_SLC1_TOKEN0_WDATA_V 0x00000FFFU +#define SDIO_SLC1_TOKEN0_WDATA_S 0 +/** SDIO_SLC1_TOKEN0_WR : WT; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN0_WR (BIT(12)) +#define SDIO_SLC1_TOKEN0_WR_M (SDIO_SLC1_TOKEN0_WR_V << SDIO_SLC1_TOKEN0_WR_S) +#define SDIO_SLC1_TOKEN0_WR_V 0x00000001U +#define SDIO_SLC1_TOKEN0_WR_S 12 +/** SDIO_SLC1_TOKEN0_INC : WT; bitpos: [13]; default: 0; + * Add 1 to slc1_token0 + */ +#define SDIO_SLC1_TOKEN0_INC (BIT(13)) +#define SDIO_SLC1_TOKEN0_INC_M (SDIO_SLC1_TOKEN0_INC_V << SDIO_SLC1_TOKEN0_INC_S) +#define SDIO_SLC1_TOKEN0_INC_V 0x00000001U +#define SDIO_SLC1_TOKEN0_INC_S 13 +/** SDIO_SLC1_TOKEN0_INC_MORE : WT; bitpos: [14]; default: 0; + * Add slc1_token0_wdata to slc1_token0 + */ +#define SDIO_SLC1_TOKEN0_INC_MORE (BIT(14)) +#define SDIO_SLC1_TOKEN0_INC_MORE_M (SDIO_SLC1_TOKEN0_INC_MORE_V << SDIO_SLC1_TOKEN0_INC_MORE_S) +#define SDIO_SLC1_TOKEN0_INC_MORE_V 0x00000001U +#define SDIO_SLC1_TOKEN0_INC_MORE_S 14 +/** SDIO_SLC1_TOKEN0 : RO; bitpos: [27:16]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN0 0x00000FFFU +#define SDIO_SLC1_TOKEN0_M (SDIO_SLC1_TOKEN0_V << SDIO_SLC1_TOKEN0_S) +#define SDIO_SLC1_TOKEN0_V 0x00000FFFU +#define SDIO_SLC1_TOKEN0_S 16 + +/** SDIO_SLC1TOKEN1_REG register + * reserved + */ +#define SDIO_SLC1TOKEN1_REG (DR_REG_SLC_BASE + 0x6c) +/** SDIO_SLC1_TOKEN1_WDATA : WT; bitpos: [11:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN1_WDATA 0x00000FFFU +#define SDIO_SLC1_TOKEN1_WDATA_M (SDIO_SLC1_TOKEN1_WDATA_V << SDIO_SLC1_TOKEN1_WDATA_S) +#define SDIO_SLC1_TOKEN1_WDATA_V 0x00000FFFU +#define SDIO_SLC1_TOKEN1_WDATA_S 0 +/** SDIO_SLC1_TOKEN1_WR : WT; bitpos: [12]; default: 0; + * update slc1_token1_wdata into slc1 token1 + */ +#define SDIO_SLC1_TOKEN1_WR (BIT(12)) +#define SDIO_SLC1_TOKEN1_WR_M (SDIO_SLC1_TOKEN1_WR_V << SDIO_SLC1_TOKEN1_WR_S) +#define SDIO_SLC1_TOKEN1_WR_V 0x00000001U +#define SDIO_SLC1_TOKEN1_WR_S 12 +/** SDIO_SLC1_TOKEN1_INC : WT; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN1_INC (BIT(13)) +#define SDIO_SLC1_TOKEN1_INC_M (SDIO_SLC1_TOKEN1_INC_V << SDIO_SLC1_TOKEN1_INC_S) +#define SDIO_SLC1_TOKEN1_INC_V 0x00000001U +#define SDIO_SLC1_TOKEN1_INC_S 13 +/** SDIO_SLC1_TOKEN1_INC_MORE : WT; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN1_INC_MORE (BIT(14)) +#define SDIO_SLC1_TOKEN1_INC_MORE_M (SDIO_SLC1_TOKEN1_INC_MORE_V << SDIO_SLC1_TOKEN1_INC_MORE_S) +#define SDIO_SLC1_TOKEN1_INC_MORE_V 0x00000001U +#define SDIO_SLC1_TOKEN1_INC_MORE_S 14 +/** SDIO_SLC1_TOKEN1 : RO; bitpos: [27:16]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN1 0x00000FFFU +#define SDIO_SLC1_TOKEN1_M (SDIO_SLC1_TOKEN1_V << SDIO_SLC1_TOKEN1_S) +#define SDIO_SLC1_TOKEN1_V 0x00000FFFU +#define SDIO_SLC1_TOKEN1_S 16 + +/** SDIO_SLCCONF1_REG register + * reserved + */ +#define SDIO_SLCCONF1_REG (DR_REG_SLC_BASE + 0x70) +/** SDIO_SLC0_CHECK_OWNER : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC0_CHECK_OWNER (BIT(0)) +#define SDIO_SLC0_CHECK_OWNER_M (SDIO_SLC0_CHECK_OWNER_V << SDIO_SLC0_CHECK_OWNER_S) +#define SDIO_SLC0_CHECK_OWNER_V 0x00000001U +#define SDIO_SLC0_CHECK_OWNER_S 0 +/** SDIO_SLC0_TX_CHECK_SUM_EN : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_CHECK_SUM_EN (BIT(1)) +#define SDIO_SLC0_TX_CHECK_SUM_EN_M (SDIO_SLC0_TX_CHECK_SUM_EN_V << SDIO_SLC0_TX_CHECK_SUM_EN_S) +#define SDIO_SLC0_TX_CHECK_SUM_EN_V 0x00000001U +#define SDIO_SLC0_TX_CHECK_SUM_EN_S 1 +/** SDIO_SLC0_RX_CHECK_SUM_EN : R/W; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_CHECK_SUM_EN (BIT(2)) +#define SDIO_SLC0_RX_CHECK_SUM_EN_M (SDIO_SLC0_RX_CHECK_SUM_EN_V << SDIO_SLC0_RX_CHECK_SUM_EN_S) +#define SDIO_SLC0_RX_CHECK_SUM_EN_V 0x00000001U +#define SDIO_SLC0_RX_CHECK_SUM_EN_S 2 +/** SDIO_SDIO_CMD_HOLD_EN : R/W; bitpos: [3]; default: 1; + * reserved + */ +#define SDIO_SDIO_CMD_HOLD_EN (BIT(3)) +#define SDIO_SDIO_CMD_HOLD_EN_M (SDIO_SDIO_CMD_HOLD_EN_V << SDIO_SDIO_CMD_HOLD_EN_S) +#define SDIO_SDIO_CMD_HOLD_EN_V 0x00000001U +#define SDIO_SDIO_CMD_HOLD_EN_S 3 +/** SDIO_SLC0_LEN_AUTO_CLR : R/W; bitpos: [4]; default: 1; + * reserved + */ +#define SDIO_SLC0_LEN_AUTO_CLR (BIT(4)) +#define SDIO_SLC0_LEN_AUTO_CLR_M (SDIO_SLC0_LEN_AUTO_CLR_V << SDIO_SLC0_LEN_AUTO_CLR_S) +#define SDIO_SLC0_LEN_AUTO_CLR_V 0x00000001U +#define SDIO_SLC0_LEN_AUTO_CLR_S 4 +/** SDIO_SLC0_TX_STITCH_EN : R/W; bitpos: [5]; default: 1; + * reserved + */ +#define SDIO_SLC0_TX_STITCH_EN (BIT(5)) +#define SDIO_SLC0_TX_STITCH_EN_M (SDIO_SLC0_TX_STITCH_EN_V << SDIO_SLC0_TX_STITCH_EN_S) +#define SDIO_SLC0_TX_STITCH_EN_V 0x00000001U +#define SDIO_SLC0_TX_STITCH_EN_S 5 +/** SDIO_SLC0_RX_STITCH_EN : R/W; bitpos: [6]; default: 1; + * reserved + */ +#define SDIO_SLC0_RX_STITCH_EN (BIT(6)) +#define SDIO_SLC0_RX_STITCH_EN_M (SDIO_SLC0_RX_STITCH_EN_V << SDIO_SLC0_RX_STITCH_EN_S) +#define SDIO_SLC0_RX_STITCH_EN_V 0x00000001U +#define SDIO_SLC0_RX_STITCH_EN_S 6 +/** SDIO_SLC1_CHECK_OWNER : R/W; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC1_CHECK_OWNER (BIT(16)) +#define SDIO_SLC1_CHECK_OWNER_M (SDIO_SLC1_CHECK_OWNER_V << SDIO_SLC1_CHECK_OWNER_S) +#define SDIO_SLC1_CHECK_OWNER_V 0x00000001U +#define SDIO_SLC1_CHECK_OWNER_S 16 +/** SDIO_SLC1_TX_CHECK_SUM_EN : R/W; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_CHECK_SUM_EN (BIT(17)) +#define SDIO_SLC1_TX_CHECK_SUM_EN_M (SDIO_SLC1_TX_CHECK_SUM_EN_V << SDIO_SLC1_TX_CHECK_SUM_EN_S) +#define SDIO_SLC1_TX_CHECK_SUM_EN_V 0x00000001U +#define SDIO_SLC1_TX_CHECK_SUM_EN_S 17 +/** SDIO_SLC1_RX_CHECK_SUM_EN : R/W; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_CHECK_SUM_EN (BIT(18)) +#define SDIO_SLC1_RX_CHECK_SUM_EN_M (SDIO_SLC1_RX_CHECK_SUM_EN_V << SDIO_SLC1_RX_CHECK_SUM_EN_S) +#define SDIO_SLC1_RX_CHECK_SUM_EN_V 0x00000001U +#define SDIO_SLC1_RX_CHECK_SUM_EN_S 18 +/** SDIO_HOST_INT_LEVEL_SEL : R/W; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_HOST_INT_LEVEL_SEL (BIT(19)) +#define SDIO_HOST_INT_LEVEL_SEL_M (SDIO_HOST_INT_LEVEL_SEL_V << SDIO_HOST_INT_LEVEL_SEL_S) +#define SDIO_HOST_INT_LEVEL_SEL_V 0x00000001U +#define SDIO_HOST_INT_LEVEL_SEL_S 19 +/** SDIO_SLC1_TX_STITCH_EN : R/W; bitpos: [20]; default: 1; + * reserved + */ +#define SDIO_SLC1_TX_STITCH_EN (BIT(20)) +#define SDIO_SLC1_TX_STITCH_EN_M (SDIO_SLC1_TX_STITCH_EN_V << SDIO_SLC1_TX_STITCH_EN_S) +#define SDIO_SLC1_TX_STITCH_EN_V 0x00000001U +#define SDIO_SLC1_TX_STITCH_EN_S 20 +/** SDIO_SLC1_RX_STITCH_EN : R/W; bitpos: [21]; default: 1; + * reserved + */ +#define SDIO_SLC1_RX_STITCH_EN (BIT(21)) +#define SDIO_SLC1_RX_STITCH_EN_M (SDIO_SLC1_RX_STITCH_EN_V << SDIO_SLC1_RX_STITCH_EN_S) +#define SDIO_SLC1_RX_STITCH_EN_V 0x00000001U +#define SDIO_SLC1_RX_STITCH_EN_S 21 +/** SDIO_SDIO_CLK_EN : R/W; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SDIO_CLK_EN (BIT(22)) +#define SDIO_SDIO_CLK_EN_M (SDIO_SDIO_CLK_EN_V << SDIO_SDIO_CLK_EN_S) +#define SDIO_SDIO_CLK_EN_V 0x00000001U +#define SDIO_SDIO_CLK_EN_S 22 + +/** SDIO_SLC0_STATE0_REG register + * reserved + */ +#define SDIO_SLC0_STATE0_REG (DR_REG_SLC_BASE + 0x74) +/** SDIO_SLC0_STATE0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_STATE0 0xFFFFFFFFU +#define SDIO_SLC0_STATE0_M (SDIO_SLC0_STATE0_V << SDIO_SLC0_STATE0_S) +#define SDIO_SLC0_STATE0_V 0xFFFFFFFFU +#define SDIO_SLC0_STATE0_S 0 + +/** SDIO_SLC0_STATE1_REG register + * ******* Description *********** + */ +#define SDIO_SLC0_STATE1_REG (DR_REG_SLC_BASE + 0x78) +/** SDIO_SLC0_STATE1 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21] + * rx_link fsm state, [30:24] rx_fifo_cnt + */ +#define SDIO_SLC0_STATE1 0xFFFFFFFFU +#define SDIO_SLC0_STATE1_M (SDIO_SLC0_STATE1_V << SDIO_SLC0_STATE1_S) +#define SDIO_SLC0_STATE1_V 0xFFFFFFFFU +#define SDIO_SLC0_STATE1_S 0 + +/** SDIO_SLC1_STATE0_REG register + * ******* Description *********** + */ +#define SDIO_SLC1_STATE0_REG (DR_REG_SLC_BASE + 0x7c) +/** SDIO_SLC1_STATE0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_STATE0 0xFFFFFFFFU +#define SDIO_SLC1_STATE0_M (SDIO_SLC1_STATE0_V << SDIO_SLC1_STATE0_S) +#define SDIO_SLC1_STATE0_V 0xFFFFFFFFU +#define SDIO_SLC1_STATE0_S 0 + +/** SDIO_SLC1_STATE1_REG register + * ******* Description *********** + */ +#define SDIO_SLC1_STATE1_REG (DR_REG_SLC_BASE + 0x80) +/** SDIO_SLC1_STATE1 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21] + * rx_link fsm state, [30:24] rx_fifo_cnt + */ +#define SDIO_SLC1_STATE1 0xFFFFFFFFU +#define SDIO_SLC1_STATE1_M (SDIO_SLC1_STATE1_V << SDIO_SLC1_STATE1_S) +#define SDIO_SLC1_STATE1_V 0xFFFFFFFFU +#define SDIO_SLC1_STATE1_S 0 + +/** SDIO_SLCBRIDGE_CONF_REG register + * ******* Description *********** + */ +#define SDIO_SLCBRIDGE_CONF_REG (DR_REG_SLC_BASE + 0x84) +/** SDIO_SLC_TXEOF_ENA : R/W; bitpos: [5:0]; default: 32; + * reserved + */ +#define SDIO_SLC_TXEOF_ENA 0x0000003FU +#define SDIO_SLC_TXEOF_ENA_M (SDIO_SLC_TXEOF_ENA_V << SDIO_SLC_TXEOF_ENA_S) +#define SDIO_SLC_TXEOF_ENA_V 0x0000003FU +#define SDIO_SLC_TXEOF_ENA_S 0 +/** SDIO_SLC_FIFO_MAP_ENA : R/W; bitpos: [11:8]; default: 7; + * reserved + */ +#define SDIO_SLC_FIFO_MAP_ENA 0x0000000FU +#define SDIO_SLC_FIFO_MAP_ENA_M (SDIO_SLC_FIFO_MAP_ENA_V << SDIO_SLC_FIFO_MAP_ENA_S) +#define SDIO_SLC_FIFO_MAP_ENA_V 0x0000000FU +#define SDIO_SLC_FIFO_MAP_ENA_S 8 +/** SDIO_SLC0_TX_DUMMY_MODE : R/W; bitpos: [12]; default: 1; + * reserved + */ +#define SDIO_SLC0_TX_DUMMY_MODE (BIT(12)) +#define SDIO_SLC0_TX_DUMMY_MODE_M (SDIO_SLC0_TX_DUMMY_MODE_V << SDIO_SLC0_TX_DUMMY_MODE_S) +#define SDIO_SLC0_TX_DUMMY_MODE_V 0x00000001U +#define SDIO_SLC0_TX_DUMMY_MODE_S 12 +/** SDIO_SLC_HDA_MAP_128K : R/W; bitpos: [13]; default: 1; + * reserved + */ +#define SDIO_SLC_HDA_MAP_128K (BIT(13)) +#define SDIO_SLC_HDA_MAP_128K_M (SDIO_SLC_HDA_MAP_128K_V << SDIO_SLC_HDA_MAP_128K_S) +#define SDIO_SLC_HDA_MAP_128K_V 0x00000001U +#define SDIO_SLC_HDA_MAP_128K_S 13 +/** SDIO_SLC1_TX_DUMMY_MODE : R/W; bitpos: [14]; default: 1; + * reserved + */ +#define SDIO_SLC1_TX_DUMMY_MODE (BIT(14)) +#define SDIO_SLC1_TX_DUMMY_MODE_M (SDIO_SLC1_TX_DUMMY_MODE_V << SDIO_SLC1_TX_DUMMY_MODE_S) +#define SDIO_SLC1_TX_DUMMY_MODE_V 0x00000001U +#define SDIO_SLC1_TX_DUMMY_MODE_S 14 +/** SDIO_SLC_TX_PUSH_IDLE_NUM : R/W; bitpos: [31:16]; default: 10; + * reserved + */ +#define SDIO_SLC_TX_PUSH_IDLE_NUM 0x0000FFFFU +#define SDIO_SLC_TX_PUSH_IDLE_NUM_M (SDIO_SLC_TX_PUSH_IDLE_NUM_V << SDIO_SLC_TX_PUSH_IDLE_NUM_S) +#define SDIO_SLC_TX_PUSH_IDLE_NUM_V 0x0000FFFFU +#define SDIO_SLC_TX_PUSH_IDLE_NUM_S 16 + +/** SDIO_SLC0_TO_EOF_DES_ADDR_REG register + * reserved + */ +#define SDIO_SLC0_TO_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x88) +/** SDIO_SLC0_TO_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TO_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TO_EOF_DES_ADDR_M (SDIO_SLC0_TO_EOF_DES_ADDR_V << SDIO_SLC0_TO_EOF_DES_ADDR_S) +#define SDIO_SLC0_TO_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TO_EOF_DES_ADDR_S 0 + +/** SDIO_SLC0_TX_EOF_DES_ADDR_REG register + * reserved + */ +#define SDIO_SLC0_TX_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x8c) +/** SDIO_SLC0_TX_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_M (SDIO_SLC0_TX_SUC_EOF_DES_ADDR_V << SDIO_SLC0_TX_SUC_EOF_DES_ADDR_S) +#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_S 0 + +/** SDIO_SLC0_TO_EOF_BFR_DES_ADDR_REG register + * reserved + */ +#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SLC_BASE + 0x90) +/** SDIO_SLC0_TO_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_M (SDIO_SLC0_TO_EOF_BFR_DES_ADDR_V << SDIO_SLC0_TO_EOF_BFR_DES_ADDR_S) +#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_S 0 + +/** SDIO_SLC1_TO_EOF_DES_ADDR_REG register + * reserved + */ +#define SDIO_SLC1_TO_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x94) +/** SDIO_SLC1_TO_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TO_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TO_EOF_DES_ADDR_M (SDIO_SLC1_TO_EOF_DES_ADDR_V << SDIO_SLC1_TO_EOF_DES_ADDR_S) +#define SDIO_SLC1_TO_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TO_EOF_DES_ADDR_S 0 + +/** SDIO_SLC1_TX_EOF_DES_ADDR_REG register + * reserved + */ +#define SDIO_SLC1_TX_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x98) +/** SDIO_SLC1_TX_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_M (SDIO_SLC1_TX_SUC_EOF_DES_ADDR_V << SDIO_SLC1_TX_SUC_EOF_DES_ADDR_S) +#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_S 0 + +/** SDIO_SLC1_TO_EOF_BFR_DES_ADDR_REG register + * reserved + */ +#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SLC_BASE + 0x9c) +/** SDIO_SLC1_TO_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_M (SDIO_SLC1_TO_EOF_BFR_DES_ADDR_V << SDIO_SLC1_TO_EOF_BFR_DES_ADDR_S) +#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_S 0 + +/** SDIO_SLC_AHB_TEST_REG register + * reserved + */ +#define SDIO_SLC_AHB_TEST_REG (DR_REG_SLC_BASE + 0xa0) +/** SDIO_SLC_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0; + * reserved + */ +#define SDIO_SLC_AHB_TESTMODE 0x00000007U +#define SDIO_SLC_AHB_TESTMODE_M (SDIO_SLC_AHB_TESTMODE_V << SDIO_SLC_AHB_TESTMODE_S) +#define SDIO_SLC_AHB_TESTMODE_V 0x00000007U +#define SDIO_SLC_AHB_TESTMODE_S 0 +/** SDIO_SLC_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0; + * reserved + */ +#define SDIO_SLC_AHB_TESTADDR 0x00000003U +#define SDIO_SLC_AHB_TESTADDR_M (SDIO_SLC_AHB_TESTADDR_V << SDIO_SLC_AHB_TESTADDR_S) +#define SDIO_SLC_AHB_TESTADDR_V 0x00000003U +#define SDIO_SLC_AHB_TESTADDR_S 4 + +/** SDIO_SLC_SDIO_ST_REG register + * reserved + */ +#define SDIO_SLC_SDIO_ST_REG (DR_REG_SLC_BASE + 0xa4) +/** SDIO_CMD_ST : RO; bitpos: [2:0]; default: 0; + * reserved + */ +#define SDIO_CMD_ST 0x00000007U +#define SDIO_CMD_ST_M (SDIO_CMD_ST_V << SDIO_CMD_ST_S) +#define SDIO_CMD_ST_V 0x00000007U +#define SDIO_CMD_ST_S 0 +/** SDIO_FUNC_ST : RO; bitpos: [7:4]; default: 0; + * reserved + */ +#define SDIO_FUNC_ST 0x0000000FU +#define SDIO_FUNC_ST_M (SDIO_FUNC_ST_V << SDIO_FUNC_ST_S) +#define SDIO_FUNC_ST_V 0x0000000FU +#define SDIO_FUNC_ST_S 4 +/** SDIO_SDIO_WAKEUP : RO; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SDIO_WAKEUP (BIT(8)) +#define SDIO_SDIO_WAKEUP_M (SDIO_SDIO_WAKEUP_V << SDIO_SDIO_WAKEUP_S) +#define SDIO_SDIO_WAKEUP_V 0x00000001U +#define SDIO_SDIO_WAKEUP_S 8 +/** SDIO_BUS_ST : RO; bitpos: [14:12]; default: 0; + * reserved + */ +#define SDIO_BUS_ST 0x00000007U +#define SDIO_BUS_ST_M (SDIO_BUS_ST_V << SDIO_BUS_ST_S) +#define SDIO_BUS_ST_V 0x00000007U +#define SDIO_BUS_ST_S 12 +/** SDIO_FUNC1_ACC_STATE : RO; bitpos: [20:16]; default: 0; + * reserved + */ +#define SDIO_FUNC1_ACC_STATE 0x0000001FU +#define SDIO_FUNC1_ACC_STATE_M (SDIO_FUNC1_ACC_STATE_V << SDIO_FUNC1_ACC_STATE_S) +#define SDIO_FUNC1_ACC_STATE_V 0x0000001FU +#define SDIO_FUNC1_ACC_STATE_S 16 +/** SDIO_FUNC2_ACC_STATE : RO; bitpos: [28:24]; default: 0; + * reserved + */ +#define SDIO_FUNC2_ACC_STATE 0x0000001FU +#define SDIO_FUNC2_ACC_STATE_M (SDIO_FUNC2_ACC_STATE_V << SDIO_FUNC2_ACC_STATE_S) +#define SDIO_FUNC2_ACC_STATE_V 0x0000001FU +#define SDIO_FUNC2_ACC_STATE_S 24 + +/** SDIO_SLC_RX_DSCR_CONF_REG register + * reserved + */ +#define SDIO_SLC_RX_DSCR_CONF_REG (DR_REG_SLC_BASE + 0xa8) +/** SDIO_SLC0_TOKEN_NO_REPLACE : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN_NO_REPLACE (BIT(0)) +#define SDIO_SLC0_TOKEN_NO_REPLACE_M (SDIO_SLC0_TOKEN_NO_REPLACE_V << SDIO_SLC0_TOKEN_NO_REPLACE_S) +#define SDIO_SLC0_TOKEN_NO_REPLACE_V 0x00000001U +#define SDIO_SLC0_TOKEN_NO_REPLACE_S 0 +/** SDIO_SLC0_INFOR_NO_REPLACE : R/W; bitpos: [1]; default: 1; + * reserved + */ +#define SDIO_SLC0_INFOR_NO_REPLACE (BIT(1)) +#define SDIO_SLC0_INFOR_NO_REPLACE_M (SDIO_SLC0_INFOR_NO_REPLACE_V << SDIO_SLC0_INFOR_NO_REPLACE_S) +#define SDIO_SLC0_INFOR_NO_REPLACE_V 0x00000001U +#define SDIO_SLC0_INFOR_NO_REPLACE_S 1 +/** SDIO_SLC0_RX_FILL_MODE : R/W; bitpos: [2]; default: 0; + * slc0 rx pop end control: 0-automatically end when pop finish, 1- end when the next + * pop doesn't occur after 255 cycles since the current pop + */ +#define SDIO_SLC0_RX_FILL_MODE (BIT(2)) +#define SDIO_SLC0_RX_FILL_MODE_M (SDIO_SLC0_RX_FILL_MODE_V << SDIO_SLC0_RX_FILL_MODE_S) +#define SDIO_SLC0_RX_FILL_MODE_V 0x00000001U +#define SDIO_SLC0_RX_FILL_MODE_S 2 +/** SDIO_SLC0_RX_EOF_MODE : R/W; bitpos: [3]; default: 1; + * 0-slc0 rx_push_eof, 1-slc0 rx_pop_eof + */ +#define SDIO_SLC0_RX_EOF_MODE (BIT(3)) +#define SDIO_SLC0_RX_EOF_MODE_M (SDIO_SLC0_RX_EOF_MODE_V << SDIO_SLC0_RX_EOF_MODE_S) +#define SDIO_SLC0_RX_EOF_MODE_V 0x00000001U +#define SDIO_SLC0_RX_EOF_MODE_S 3 +/** SDIO_SLC0_RX_FILL_EN : R/W; bitpos: [4]; default: 1; + * reserved + */ +#define SDIO_SLC0_RX_FILL_EN (BIT(4)) +#define SDIO_SLC0_RX_FILL_EN_M (SDIO_SLC0_RX_FILL_EN_V << SDIO_SLC0_RX_FILL_EN_S) +#define SDIO_SLC0_RX_FILL_EN_V 0x00000001U +#define SDIO_SLC0_RX_FILL_EN_S 4 +/** SDIO_SLC0_RD_RETRY_THRESHOLD : R/W; bitpos: [15:5]; default: 128; + * reserved + */ +#define SDIO_SLC0_RD_RETRY_THRESHOLD 0x000007FFU +#define SDIO_SLC0_RD_RETRY_THRESHOLD_M (SDIO_SLC0_RD_RETRY_THRESHOLD_V << SDIO_SLC0_RD_RETRY_THRESHOLD_S) +#define SDIO_SLC0_RD_RETRY_THRESHOLD_V 0x000007FFU +#define SDIO_SLC0_RD_RETRY_THRESHOLD_S 5 +/** SDIO_SLC1_TOKEN_NO_REPLACE : R/W; bitpos: [16]; default: 1; + * reserved + */ +#define SDIO_SLC1_TOKEN_NO_REPLACE (BIT(16)) +#define SDIO_SLC1_TOKEN_NO_REPLACE_M (SDIO_SLC1_TOKEN_NO_REPLACE_V << SDIO_SLC1_TOKEN_NO_REPLACE_S) +#define SDIO_SLC1_TOKEN_NO_REPLACE_V 0x00000001U +#define SDIO_SLC1_TOKEN_NO_REPLACE_S 16 +/** SDIO_SLC1_INFOR_NO_REPLACE : R/W; bitpos: [17]; default: 1; + * reserved + */ +#define SDIO_SLC1_INFOR_NO_REPLACE (BIT(17)) +#define SDIO_SLC1_INFOR_NO_REPLACE_M (SDIO_SLC1_INFOR_NO_REPLACE_V << SDIO_SLC1_INFOR_NO_REPLACE_S) +#define SDIO_SLC1_INFOR_NO_REPLACE_V 0x00000001U +#define SDIO_SLC1_INFOR_NO_REPLACE_S 17 +/** SDIO_SLC1_RX_FILL_MODE : R/W; bitpos: [18]; default: 0; + * slc1 rx pop end control: 0-automatically end when pop finish, 1- end when the next + * pop doesn't occur after 255 cycles since the current pop + */ +#define SDIO_SLC1_RX_FILL_MODE (BIT(18)) +#define SDIO_SLC1_RX_FILL_MODE_M (SDIO_SLC1_RX_FILL_MODE_V << SDIO_SLC1_RX_FILL_MODE_S) +#define SDIO_SLC1_RX_FILL_MODE_V 0x00000001U +#define SDIO_SLC1_RX_FILL_MODE_S 18 +/** SDIO_SLC1_RX_EOF_MODE : R/W; bitpos: [19]; default: 1; + * 0-slc1 rx_push_eof, 1-slc1 rx_pop_eof + */ +#define SDIO_SLC1_RX_EOF_MODE (BIT(19)) +#define SDIO_SLC1_RX_EOF_MODE_M (SDIO_SLC1_RX_EOF_MODE_V << SDIO_SLC1_RX_EOF_MODE_S) +#define SDIO_SLC1_RX_EOF_MODE_V 0x00000001U +#define SDIO_SLC1_RX_EOF_MODE_S 19 +/** SDIO_SLC1_RX_FILL_EN : R/W; bitpos: [20]; default: 1; + * reserved + */ +#define SDIO_SLC1_RX_FILL_EN (BIT(20)) +#define SDIO_SLC1_RX_FILL_EN_M (SDIO_SLC1_RX_FILL_EN_V << SDIO_SLC1_RX_FILL_EN_S) +#define SDIO_SLC1_RX_FILL_EN_V 0x00000001U +#define SDIO_SLC1_RX_FILL_EN_S 20 +/** SDIO_SLC1_RD_RETRY_THRESHOLD : R/W; bitpos: [31:21]; default: 128; + * reserved + */ +#define SDIO_SLC1_RD_RETRY_THRESHOLD 0x000007FFU +#define SDIO_SLC1_RD_RETRY_THRESHOLD_M (SDIO_SLC1_RD_RETRY_THRESHOLD_V << SDIO_SLC1_RD_RETRY_THRESHOLD_S) +#define SDIO_SLC1_RD_RETRY_THRESHOLD_V 0x000007FFU +#define SDIO_SLC1_RD_RETRY_THRESHOLD_S 21 + +/** SDIO_SLC0_TXLINK_DSCR_REG register + * ******* Description *********** + */ +#define SDIO_SLC0_TXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xac) +/** SDIO_SLC0_TXLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXLINK_DSCR 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_M (SDIO_SLC0_TXLINK_DSCR_V << SDIO_SLC0_TXLINK_DSCR_S) +#define SDIO_SLC0_TXLINK_DSCR_V 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_S 0 + +/** SDIO_SLC0_TXLINK_DSCR_BF0_REG register + * ******* Description *********** + */ +#define SDIO_SLC0_TXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xb0) +/** SDIO_SLC0_TXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXLINK_DSCR_BF0 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_BF0_M (SDIO_SLC0_TXLINK_DSCR_BF0_V << SDIO_SLC0_TXLINK_DSCR_BF0_S) +#define SDIO_SLC0_TXLINK_DSCR_BF0_V 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_BF0_S 0 + +/** SDIO_SLC0_TXLINK_DSCR_BF1_REG register + * reserved + */ +#define SDIO_SLC0_TXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xb4) +/** SDIO_SLC0_TXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXLINK_DSCR_BF1 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_BF1_M (SDIO_SLC0_TXLINK_DSCR_BF1_V << SDIO_SLC0_TXLINK_DSCR_BF1_S) +#define SDIO_SLC0_TXLINK_DSCR_BF1_V 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_BF1_S 0 + +/** SDIO_SLC0_RXLINK_DSCR_REG register + * ******* Description *********** + */ +#define SDIO_SLC0_RXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xb8) +/** SDIO_SLC0_RXLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * the third word of slc0 link descriptor, or known as the next descriptor address + */ +#define SDIO_SLC0_RXLINK_DSCR 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_M (SDIO_SLC0_RXLINK_DSCR_V << SDIO_SLC0_RXLINK_DSCR_S) +#define SDIO_SLC0_RXLINK_DSCR_V 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_S 0 + +/** SDIO_SLC0_RXLINK_DSCR_BF0_REG register + * ******* Description *********** + */ +#define SDIO_SLC0_RXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xbc) +/** SDIO_SLC0_RXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RXLINK_DSCR_BF0 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_BF0_M (SDIO_SLC0_RXLINK_DSCR_BF0_V << SDIO_SLC0_RXLINK_DSCR_BF0_S) +#define SDIO_SLC0_RXLINK_DSCR_BF0_V 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_BF0_S 0 + +/** SDIO_SLC0_RXLINK_DSCR_BF1_REG register + * reserved + */ +#define SDIO_SLC0_RXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xc0) +/** SDIO_SLC0_RXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RXLINK_DSCR_BF1 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_BF1_M (SDIO_SLC0_RXLINK_DSCR_BF1_V << SDIO_SLC0_RXLINK_DSCR_BF1_S) +#define SDIO_SLC0_RXLINK_DSCR_BF1_V 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_BF1_S 0 + +/** SDIO_SLC1_TXLINK_DSCR_REG register + * reserved + */ +#define SDIO_SLC1_TXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xc4) +/** SDIO_SLC1_TXLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXLINK_DSCR 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_M (SDIO_SLC1_TXLINK_DSCR_V << SDIO_SLC1_TXLINK_DSCR_S) +#define SDIO_SLC1_TXLINK_DSCR_V 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_S 0 + +/** SDIO_SLC1_TXLINK_DSCR_BF0_REG register + * reserved + */ +#define SDIO_SLC1_TXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xc8) +/** SDIO_SLC1_TXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXLINK_DSCR_BF0 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_BF0_M (SDIO_SLC1_TXLINK_DSCR_BF0_V << SDIO_SLC1_TXLINK_DSCR_BF0_S) +#define SDIO_SLC1_TXLINK_DSCR_BF0_V 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_BF0_S 0 + +/** SDIO_SLC1_TXLINK_DSCR_BF1_REG register + * reserved + */ +#define SDIO_SLC1_TXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xcc) +/** SDIO_SLC1_TXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXLINK_DSCR_BF1 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_BF1_M (SDIO_SLC1_TXLINK_DSCR_BF1_V << SDIO_SLC1_TXLINK_DSCR_BF1_S) +#define SDIO_SLC1_TXLINK_DSCR_BF1_V 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_BF1_S 0 + +/** SDIO_SLC1_RXLINK_DSCR_REG register + * ******* Description *********** + */ +#define SDIO_SLC1_RXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xd0) +/** SDIO_SLC1_RXLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * the third word of slc1 link descriptor, or known as the next descriptor address + */ +#define SDIO_SLC1_RXLINK_DSCR 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_M (SDIO_SLC1_RXLINK_DSCR_V << SDIO_SLC1_RXLINK_DSCR_S) +#define SDIO_SLC1_RXLINK_DSCR_V 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_S 0 + +/** SDIO_SLC1_RXLINK_DSCR_BF0_REG register + * ******* Description *********** + */ +#define SDIO_SLC1_RXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xd4) +/** SDIO_SLC1_RXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_RXLINK_DSCR_BF0 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_BF0_M (SDIO_SLC1_RXLINK_DSCR_BF0_V << SDIO_SLC1_RXLINK_DSCR_BF0_S) +#define SDIO_SLC1_RXLINK_DSCR_BF0_V 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_BF0_S 0 + +/** SDIO_SLC1_RXLINK_DSCR_BF1_REG register + * reserved + */ +#define SDIO_SLC1_RXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xd8) +/** SDIO_SLC1_RXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_RXLINK_DSCR_BF1 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_BF1_M (SDIO_SLC1_RXLINK_DSCR_BF1_V << SDIO_SLC1_RXLINK_DSCR_BF1_S) +#define SDIO_SLC1_RXLINK_DSCR_BF1_V 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_BF1_S 0 + +/** SDIO_SLC0_TX_ERREOF_DES_ADDR_REG register + * reserved + */ +#define SDIO_SLC0_TX_ERREOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0xdc) +/** SDIO_SLC0_TX_ERR_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_M (SDIO_SLC0_TX_ERR_EOF_DES_ADDR_V << SDIO_SLC0_TX_ERR_EOF_DES_ADDR_S) +#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_S 0 + +/** SDIO_SLC1_TX_ERREOF_DES_ADDR_REG register + * reserved + */ +#define SDIO_SLC1_TX_ERREOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0xe0) +/** SDIO_SLC1_TX_ERR_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_M (SDIO_SLC1_TX_ERR_EOF_DES_ADDR_V << SDIO_SLC1_TX_ERR_EOF_DES_ADDR_S) +#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_S 0 + +/** SDIO_SLC_TOKEN_LAT_REG register + * reserved + */ +#define SDIO_SLC_TOKEN_LAT_REG (DR_REG_SLC_BASE + 0xe4) +/** SDIO_SLC0_TOKEN : RO; bitpos: [11:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN 0x00000FFFU +#define SDIO_SLC0_TOKEN_M (SDIO_SLC0_TOKEN_V << SDIO_SLC0_TOKEN_S) +#define SDIO_SLC0_TOKEN_V 0x00000FFFU +#define SDIO_SLC0_TOKEN_S 0 +/** SDIO_SLC1_TOKEN : RO; bitpos: [27:16]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN 0x00000FFFU +#define SDIO_SLC1_TOKEN_M (SDIO_SLC1_TOKEN_V << SDIO_SLC1_TOKEN_S) +#define SDIO_SLC1_TOKEN_V 0x00000FFFU +#define SDIO_SLC1_TOKEN_S 16 + +/** SDIO_SLC_TX_DSCR_CONF_REG register + * reserved + */ +#define SDIO_SLC_TX_DSCR_CONF_REG (DR_REG_SLC_BASE + 0xe8) +/** SDIO_SLC_WR_RETRY_THRESHOLD : R/W; bitpos: [10:0]; default: 128; + * reserved + */ +#define SDIO_SLC_WR_RETRY_THRESHOLD 0x000007FFU +#define SDIO_SLC_WR_RETRY_THRESHOLD_M (SDIO_SLC_WR_RETRY_THRESHOLD_V << SDIO_SLC_WR_RETRY_THRESHOLD_S) +#define SDIO_SLC_WR_RETRY_THRESHOLD_V 0x000007FFU +#define SDIO_SLC_WR_RETRY_THRESHOLD_S 0 + +/** SDIO_SLC_CMD_INFOR0_REG register + * reserved + */ +#define SDIO_SLC_CMD_INFOR0_REG (DR_REG_SLC_BASE + 0xec) +/** SDIO_CMD_CONTENT0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_CMD_CONTENT0 0xFFFFFFFFU +#define SDIO_CMD_CONTENT0_M (SDIO_CMD_CONTENT0_V << SDIO_CMD_CONTENT0_S) +#define SDIO_CMD_CONTENT0_V 0xFFFFFFFFU +#define SDIO_CMD_CONTENT0_S 0 + +/** SDIO_SLC_CMD_INFOR1_REG register + * reserved + */ +#define SDIO_SLC_CMD_INFOR1_REG (DR_REG_SLC_BASE + 0xf0) +/** SDIO_CMD_CONTENT1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_CMD_CONTENT1 0xFFFFFFFFU +#define SDIO_CMD_CONTENT1_M (SDIO_CMD_CONTENT1_V << SDIO_CMD_CONTENT1_S) +#define SDIO_CMD_CONTENT1_V 0xFFFFFFFFU +#define SDIO_CMD_CONTENT1_S 0 + +/** SDIO_SLC0_LEN_CONF_REG register + * reserved + */ +#define SDIO_SLC0_LEN_CONF_REG (DR_REG_SLC_BASE + 0xf4) +/** SDIO_SLC0_LEN_WDATA : WT; bitpos: [19:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_LEN_WDATA 0x000FFFFFU +#define SDIO_SLC0_LEN_WDATA_M (SDIO_SLC0_LEN_WDATA_V << SDIO_SLC0_LEN_WDATA_S) +#define SDIO_SLC0_LEN_WDATA_V 0x000FFFFFU +#define SDIO_SLC0_LEN_WDATA_S 0 +/** SDIO_SLC0_LEN_WR : WT; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC0_LEN_WR (BIT(20)) +#define SDIO_SLC0_LEN_WR_M (SDIO_SLC0_LEN_WR_V << SDIO_SLC0_LEN_WR_S) +#define SDIO_SLC0_LEN_WR_V 0x00000001U +#define SDIO_SLC0_LEN_WR_S 20 +/** SDIO_SLC0_LEN_INC : WT; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC0_LEN_INC (BIT(21)) +#define SDIO_SLC0_LEN_INC_M (SDIO_SLC0_LEN_INC_V << SDIO_SLC0_LEN_INC_S) +#define SDIO_SLC0_LEN_INC_V 0x00000001U +#define SDIO_SLC0_LEN_INC_S 21 +/** SDIO_SLC0_LEN_INC_MORE : WT; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC0_LEN_INC_MORE (BIT(22)) +#define SDIO_SLC0_LEN_INC_MORE_M (SDIO_SLC0_LEN_INC_MORE_V << SDIO_SLC0_LEN_INC_MORE_S) +#define SDIO_SLC0_LEN_INC_MORE_V 0x00000001U +#define SDIO_SLC0_LEN_INC_MORE_S 22 +/** SDIO_SLC0_RX_PACKET_LOAD_EN : WT; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_PACKET_LOAD_EN (BIT(23)) +#define SDIO_SLC0_RX_PACKET_LOAD_EN_M (SDIO_SLC0_RX_PACKET_LOAD_EN_V << SDIO_SLC0_RX_PACKET_LOAD_EN_S) +#define SDIO_SLC0_RX_PACKET_LOAD_EN_V 0x00000001U +#define SDIO_SLC0_RX_PACKET_LOAD_EN_S 23 +/** SDIO_SLC0_TX_PACKET_LOAD_EN : WT; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_PACKET_LOAD_EN (BIT(24)) +#define SDIO_SLC0_TX_PACKET_LOAD_EN_M (SDIO_SLC0_TX_PACKET_LOAD_EN_V << SDIO_SLC0_TX_PACKET_LOAD_EN_S) +#define SDIO_SLC0_TX_PACKET_LOAD_EN_V 0x00000001U +#define SDIO_SLC0_TX_PACKET_LOAD_EN_S 24 +/** SDIO_SLC0_RX_GET_USED_DSCR : WT; bitpos: [25]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_GET_USED_DSCR (BIT(25)) +#define SDIO_SLC0_RX_GET_USED_DSCR_M (SDIO_SLC0_RX_GET_USED_DSCR_V << SDIO_SLC0_RX_GET_USED_DSCR_S) +#define SDIO_SLC0_RX_GET_USED_DSCR_V 0x00000001U +#define SDIO_SLC0_RX_GET_USED_DSCR_S 25 +/** SDIO_SLC0_TX_GET_USED_DSCR : WT; bitpos: [26]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_GET_USED_DSCR (BIT(26)) +#define SDIO_SLC0_TX_GET_USED_DSCR_M (SDIO_SLC0_TX_GET_USED_DSCR_V << SDIO_SLC0_TX_GET_USED_DSCR_S) +#define SDIO_SLC0_TX_GET_USED_DSCR_V 0x00000001U +#define SDIO_SLC0_TX_GET_USED_DSCR_S 26 +/** SDIO_SLC0_RX_NEW_PKT_IND : RO; bitpos: [27]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_NEW_PKT_IND (BIT(27)) +#define SDIO_SLC0_RX_NEW_PKT_IND_M (SDIO_SLC0_RX_NEW_PKT_IND_V << SDIO_SLC0_RX_NEW_PKT_IND_S) +#define SDIO_SLC0_RX_NEW_PKT_IND_V 0x00000001U +#define SDIO_SLC0_RX_NEW_PKT_IND_S 27 +/** SDIO_SLC0_TX_NEW_PKT_IND : RO; bitpos: [28]; default: 1; + * reserved + */ +#define SDIO_SLC0_TX_NEW_PKT_IND (BIT(28)) +#define SDIO_SLC0_TX_NEW_PKT_IND_M (SDIO_SLC0_TX_NEW_PKT_IND_V << SDIO_SLC0_TX_NEW_PKT_IND_S) +#define SDIO_SLC0_TX_NEW_PKT_IND_V 0x00000001U +#define SDIO_SLC0_TX_NEW_PKT_IND_S 28 +/** SDIO_SLC0_RX_PACKET_LOAD_EN_ST : R/WTC/SC; bitpos: [29]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST (BIT(29)) +#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_M (SDIO_SLC0_RX_PACKET_LOAD_EN_ST_V << SDIO_SLC0_RX_PACKET_LOAD_EN_ST_S) +#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_V 0x00000001U +#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_S 29 +/** SDIO_SLC0_TX_PACKET_LOAD_EN_ST : R/WTC/SC; bitpos: [30]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST (BIT(30)) +#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_M (SDIO_SLC0_TX_PACKET_LOAD_EN_ST_V << SDIO_SLC0_TX_PACKET_LOAD_EN_ST_S) +#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_V 0x00000001U +#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_S 30 + +/** SDIO_SLC0_LENGTH_REG register + * reserved + */ +#define SDIO_SLC0_LENGTH_REG (DR_REG_SLC_BASE + 0xf8) +/** SDIO_SLC0_LEN : RO; bitpos: [19:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_LEN 0x000FFFFFU +#define SDIO_SLC0_LEN_M (SDIO_SLC0_LEN_V << SDIO_SLC0_LEN_S) +#define SDIO_SLC0_LEN_V 0x000FFFFFU +#define SDIO_SLC0_LEN_S 0 + +/** SDIO_SLC0_TXPKT_H_DSCR_REG register + * reserved + */ +#define SDIO_SLC0_TXPKT_H_DSCR_REG (DR_REG_SLC_BASE + 0xfc) +/** SDIO_SLC0_TX_PKT_H_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_H_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_H_DSCR_ADDR_S) +#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_S 0 + +/** SDIO_SLC0_TXPKT_E_DSCR_REG register + * reserved + */ +#define SDIO_SLC0_TXPKT_E_DSCR_REG (DR_REG_SLC_BASE + 0x100) +/** SDIO_SLC0_TX_PKT_E_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_E_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_E_DSCR_ADDR_S) +#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_S 0 + +/** SDIO_SLC0_RXPKT_H_DSCR_REG register + * reserved + */ +#define SDIO_SLC0_RXPKT_H_DSCR_REG (DR_REG_SLC_BASE + 0x104) +/** SDIO_SLC0_RX_PKT_H_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_H_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_H_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_S 0 + +/** SDIO_SLC0_RXPKT_E_DSCR_REG register + * reserved + */ +#define SDIO_SLC0_RXPKT_E_DSCR_REG (DR_REG_SLC_BASE + 0x108) +/** SDIO_SLC0_RX_PKT_E_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_E_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_E_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_S 0 + +/** SDIO_SLC0_TXPKTU_H_DSCR_REG register + * reserved + */ +#define SDIO_SLC0_TXPKTU_H_DSCR_REG (DR_REG_SLC_BASE + 0x10c) +/** SDIO_SLC0_TX_PKT_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_START_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_START_DSCR_ADDR_S) +#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_S 0 + +/** SDIO_SLC0_TXPKTU_E_DSCR_REG register + * reserved + */ +#define SDIO_SLC0_TXPKTU_E_DSCR_REG (DR_REG_SLC_BASE + 0x110) +/** SDIO_SLC0_TX_PKT_END_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_END_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_END_DSCR_ADDR_S) +#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_S 0 + +/** SDIO_SLC0_RXPKTU_H_DSCR_REG register + * reserved + */ +#define SDIO_SLC0_RXPKTU_H_DSCR_REG (DR_REG_SLC_BASE + 0x114) +/** SDIO_SLC0_RX_PKT_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_START_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_START_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_S 0 + +/** SDIO_SLC0_RXPKTU_E_DSCR_REG register + * reserved + */ +#define SDIO_SLC0_RXPKTU_E_DSCR_REG (DR_REG_SLC_BASE + 0x118) +/** SDIO_SLC0_RX_PKT_END_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_END_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_END_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_S 0 + +/** SDIO_SLC_SEQ_POSITION_REG register + * reserved + */ +#define SDIO_SLC_SEQ_POSITION_REG (DR_REG_SLC_BASE + 0x11c) +/** SDIO_SLC0_SEQ_POSITION : R/W; bitpos: [7:0]; default: 9; + * reserved + */ +#define SDIO_SLC0_SEQ_POSITION 0x000000FFU +#define SDIO_SLC0_SEQ_POSITION_M (SDIO_SLC0_SEQ_POSITION_V << SDIO_SLC0_SEQ_POSITION_S) +#define SDIO_SLC0_SEQ_POSITION_V 0x000000FFU +#define SDIO_SLC0_SEQ_POSITION_S 0 +/** SDIO_SLC1_SEQ_POSITION : R/W; bitpos: [15:8]; default: 5; + * reserved + */ +#define SDIO_SLC1_SEQ_POSITION 0x000000FFU +#define SDIO_SLC1_SEQ_POSITION_M (SDIO_SLC1_SEQ_POSITION_V << SDIO_SLC1_SEQ_POSITION_S) +#define SDIO_SLC1_SEQ_POSITION_V 0x000000FFU +#define SDIO_SLC1_SEQ_POSITION_S 8 + +/** SDIO_SLC0_DSCR_REC_CONF_REG register + * reserved + */ +#define SDIO_SLC0_DSCR_REC_CONF_REG (DR_REG_SLC_BASE + 0x120) +/** SDIO_SLC0_RX_DSCR_REC_LIM : R/W; bitpos: [9:0]; default: 1023; + * reserved + */ +#define SDIO_SLC0_RX_DSCR_REC_LIM 0x000003FFU +#define SDIO_SLC0_RX_DSCR_REC_LIM_M (SDIO_SLC0_RX_DSCR_REC_LIM_V << SDIO_SLC0_RX_DSCR_REC_LIM_S) +#define SDIO_SLC0_RX_DSCR_REC_LIM_V 0x000003FFU +#define SDIO_SLC0_RX_DSCR_REC_LIM_S 0 + +/** SDIO_SLC_SDIO_CRC_ST0_REG register + * reserved + */ +#define SDIO_SLC_SDIO_CRC_ST0_REG (DR_REG_SLC_BASE + 0x124) +/** SDIO_DAT0_CRC_ERR_CNT : RO; bitpos: [7:0]; default: 0; + * reserved + */ +#define SDIO_DAT0_CRC_ERR_CNT 0x000000FFU +#define SDIO_DAT0_CRC_ERR_CNT_M (SDIO_DAT0_CRC_ERR_CNT_V << SDIO_DAT0_CRC_ERR_CNT_S) +#define SDIO_DAT0_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_DAT0_CRC_ERR_CNT_S 0 +/** SDIO_DAT1_CRC_ERR_CNT : RO; bitpos: [15:8]; default: 0; + * reserved + */ +#define SDIO_DAT1_CRC_ERR_CNT 0x000000FFU +#define SDIO_DAT1_CRC_ERR_CNT_M (SDIO_DAT1_CRC_ERR_CNT_V << SDIO_DAT1_CRC_ERR_CNT_S) +#define SDIO_DAT1_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_DAT1_CRC_ERR_CNT_S 8 +/** SDIO_DAT2_CRC_ERR_CNT : RO; bitpos: [23:16]; default: 0; + * reserved + */ +#define SDIO_DAT2_CRC_ERR_CNT 0x000000FFU +#define SDIO_DAT2_CRC_ERR_CNT_M (SDIO_DAT2_CRC_ERR_CNT_V << SDIO_DAT2_CRC_ERR_CNT_S) +#define SDIO_DAT2_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_DAT2_CRC_ERR_CNT_S 16 +/** SDIO_DAT3_CRC_ERR_CNT : RO; bitpos: [31:24]; default: 0; + * reserved + */ +#define SDIO_DAT3_CRC_ERR_CNT 0x000000FFU +#define SDIO_DAT3_CRC_ERR_CNT_M (SDIO_DAT3_CRC_ERR_CNT_V << SDIO_DAT3_CRC_ERR_CNT_S) +#define SDIO_DAT3_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_DAT3_CRC_ERR_CNT_S 24 + +/** SDIO_SLC_SDIO_CRC_ST1_REG register + * reserved + */ +#define SDIO_SLC_SDIO_CRC_ST1_REG (DR_REG_SLC_BASE + 0x128) +/** SDIO_CMD_CRC_ERR_CNT : RO; bitpos: [7:0]; default: 0; + * reserved + */ +#define SDIO_CMD_CRC_ERR_CNT 0x000000FFU +#define SDIO_CMD_CRC_ERR_CNT_M (SDIO_CMD_CRC_ERR_CNT_V << SDIO_CMD_CRC_ERR_CNT_S) +#define SDIO_CMD_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_CMD_CRC_ERR_CNT_S 0 +/** SDIO_ERR_CNT_CLR : R/W; bitpos: [31]; default: 0; + * reserved + */ +#define SDIO_ERR_CNT_CLR (BIT(31)) +#define SDIO_ERR_CNT_CLR_M (SDIO_ERR_CNT_CLR_V << SDIO_ERR_CNT_CLR_S) +#define SDIO_ERR_CNT_CLR_V 0x00000001U +#define SDIO_ERR_CNT_CLR_S 31 + +/** SDIO_SLC0_EOF_START_DES_REG register + * reserved + */ +#define SDIO_SLC0_EOF_START_DES_REG (DR_REG_SLC_BASE + 0x12c) +/** SDIO_SLC0_EOF_START_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_EOF_START_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_EOF_START_DES_ADDR_M (SDIO_SLC0_EOF_START_DES_ADDR_V << SDIO_SLC0_EOF_START_DES_ADDR_S) +#define SDIO_SLC0_EOF_START_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_EOF_START_DES_ADDR_S 0 + +/** SDIO_SLC0_PUSH_DSCR_ADDR_REG register + * ******* Description *********** + */ +#define SDIO_SLC0_PUSH_DSCR_ADDR_REG (DR_REG_SLC_BASE + 0x130) +/** SDIO_SLC0_RX_PUSH_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 gets a link descriptor, aligned with word + */ +#define SDIO_SLC0_RX_PUSH_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_M (SDIO_SLC0_RX_PUSH_DSCR_ADDR_V << SDIO_SLC0_RX_PUSH_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_S 0 + +/** SDIO_SLC0_DONE_DSCR_ADDR_REG register + * ******* Description *********** + */ +#define SDIO_SLC0_DONE_DSCR_ADDR_REG (DR_REG_SLC_BASE + 0x134) +/** SDIO_SLC0_RX_DONE_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 finishes reading data from one buffer, + * aligned with word + */ +#define SDIO_SLC0_RX_DONE_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_DONE_DSCR_ADDR_M (SDIO_SLC0_RX_DONE_DSCR_ADDR_V << SDIO_SLC0_RX_DONE_DSCR_ADDR_S) +#define SDIO_SLC0_RX_DONE_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_DONE_DSCR_ADDR_S 0 + +/** SDIO_SLC0_SUB_START_DES_REG register + * ******* Description *********** + */ +#define SDIO_SLC0_SUB_START_DES_REG (DR_REG_SLC_BASE + 0x138) +/** SDIO_SLC0_SUB_PAC_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 gets a link descriptor, aligned with word + */ +#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_M (SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_V << SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_S) +#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_S 0 + +/** SDIO_SLC0_DSCR_CNT_REG register + * ******* Description *********** + */ +#define SDIO_SLC0_DSCR_CNT_REG (DR_REG_SLC_BASE + 0x13c) +/** SDIO_SLC0_RX_DSCR_CNT_LAT : RO; bitpos: [9:0]; default: 0; + * the number of descriptors got by slc0 when it tries to read data from memory + */ +#define SDIO_SLC0_RX_DSCR_CNT_LAT 0x000003FFU +#define SDIO_SLC0_RX_DSCR_CNT_LAT_M (SDIO_SLC0_RX_DSCR_CNT_LAT_V << SDIO_SLC0_RX_DSCR_CNT_LAT_S) +#define SDIO_SLC0_RX_DSCR_CNT_LAT_V 0x000003FFU +#define SDIO_SLC0_RX_DSCR_CNT_LAT_S 0 +/** SDIO_SLC0_RX_GET_EOF_OCC : RO; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_GET_EOF_OCC (BIT(16)) +#define SDIO_SLC0_RX_GET_EOF_OCC_M (SDIO_SLC0_RX_GET_EOF_OCC_V << SDIO_SLC0_RX_GET_EOF_OCC_S) +#define SDIO_SLC0_RX_GET_EOF_OCC_V 0x00000001U +#define SDIO_SLC0_RX_GET_EOF_OCC_S 16 + +/** SDIO_SLC0_LEN_LIM_CONF_REG register + * ******* Description *********** + */ +#define SDIO_SLC0_LEN_LIM_CONF_REG (DR_REG_SLC_BASE + 0x140) +/** SDIO_SLC0_LEN_LIM : R/W; bitpos: [19:0]; default: 21504; + * reserved + */ +#define SDIO_SLC0_LEN_LIM 0x000FFFFFU +#define SDIO_SLC0_LEN_LIM_M (SDIO_SLC0_LEN_LIM_V << SDIO_SLC0_LEN_LIM_S) +#define SDIO_SLC0_LEN_LIM_V 0x000FFFFFU +#define SDIO_SLC0_LEN_LIM_S 0 + +/** SDIO_SLC0INT_ST1_REG register + * reserved + */ +#define SDIO_SLC0INT_ST1_REG (DR_REG_SLC_BASE + 0x144) +/** SDIO_SLC_FRHOST_BIT0_INT_ST1 : RO; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT0_INT_ST1 (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_ST1_M (SDIO_SLC_FRHOST_BIT0_INT_ST1_V << SDIO_SLC_FRHOST_BIT0_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT0_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_ST1_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_ST1 : RO; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT1_INT_ST1 (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_ST1_M (SDIO_SLC_FRHOST_BIT1_INT_ST1_V << SDIO_SLC_FRHOST_BIT1_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT1_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_ST1_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_ST1 : RO; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT2_INT_ST1 (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_ST1_M (SDIO_SLC_FRHOST_BIT2_INT_ST1_V << SDIO_SLC_FRHOST_BIT2_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT2_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_ST1_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_ST1 : RO; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT3_INT_ST1 (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_ST1_M (SDIO_SLC_FRHOST_BIT3_INT_ST1_V << SDIO_SLC_FRHOST_BIT3_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT3_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_ST1_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_ST1 : RO; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT4_INT_ST1 (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_ST1_M (SDIO_SLC_FRHOST_BIT4_INT_ST1_V << SDIO_SLC_FRHOST_BIT4_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT4_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_ST1_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_ST1 : RO; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT5_INT_ST1 (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_ST1_M (SDIO_SLC_FRHOST_BIT5_INT_ST1_V << SDIO_SLC_FRHOST_BIT5_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT5_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_ST1_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_ST1 : RO; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT6_INT_ST1 (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_ST1_M (SDIO_SLC_FRHOST_BIT6_INT_ST1_V << SDIO_SLC_FRHOST_BIT6_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT6_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_ST1_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_ST1 : RO; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT7_INT_ST1 (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_ST1_M (SDIO_SLC_FRHOST_BIT7_INT_ST1_V << SDIO_SLC_FRHOST_BIT7_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT7_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_ST1_S 7 +/** SDIO_SLC0_RX_START_INT_ST1 : RO; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_START_INT_ST1 (BIT(8)) +#define SDIO_SLC0_RX_START_INT_ST1_M (SDIO_SLC0_RX_START_INT_ST1_V << SDIO_SLC0_RX_START_INT_ST1_S) +#define SDIO_SLC0_RX_START_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_ST1_S 8 +/** SDIO_SLC0_TX_START_INT_ST1 : RO; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_START_INT_ST1 (BIT(9)) +#define SDIO_SLC0_TX_START_INT_ST1_M (SDIO_SLC0_TX_START_INT_ST1_V << SDIO_SLC0_TX_START_INT_ST1_S) +#define SDIO_SLC0_TX_START_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_ST1_S 9 +/** SDIO_SLC0_RX_UDF_INT_ST1 : RO; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_UDF_INT_ST1 (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_ST1_M (SDIO_SLC0_RX_UDF_INT_ST1_V << SDIO_SLC0_RX_UDF_INT_ST1_S) +#define SDIO_SLC0_RX_UDF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_ST1_S 10 +/** SDIO_SLC0_TX_OVF_INT_ST1 : RO; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_OVF_INT_ST1 (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_ST1_M (SDIO_SLC0_TX_OVF_INT_ST1_V << SDIO_SLC0_TX_OVF_INT_ST1_S) +#define SDIO_SLC0_TX_OVF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_ST1_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_ST1 : RO; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1 (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_M (SDIO_SLC0_TOKEN0_1TO0_INT_ST1_V << SDIO_SLC0_TOKEN0_1TO0_INT_ST1_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_ST1 : RO; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1 (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_M (SDIO_SLC0_TOKEN1_1TO0_INT_ST1_V << SDIO_SLC0_TOKEN1_1TO0_INT_ST1_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_S 13 +/** SDIO_SLC0_TX_DONE_INT_ST1 : RO; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DONE_INT_ST1 (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_ST1_M (SDIO_SLC0_TX_DONE_INT_ST1_V << SDIO_SLC0_TX_DONE_INT_ST1_S) +#define SDIO_SLC0_TX_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_ST1_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_ST1 : RO; bitpos: [15]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_ST1 (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_M (SDIO_SLC0_TX_SUC_EOF_INT_ST1_V << SDIO_SLC0_TX_SUC_EOF_INT_ST1_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_S 15 +/** SDIO_SLC0_RX_DONE_INT_ST1 : RO; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_DONE_INT_ST1 (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_ST1_M (SDIO_SLC0_RX_DONE_INT_ST1_V << SDIO_SLC0_RX_DONE_INT_ST1_S) +#define SDIO_SLC0_RX_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_ST1_S 16 +/** SDIO_SLC0_RX_EOF_INT_ST1 : RO; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_EOF_INT_ST1 (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_ST1_M (SDIO_SLC0_RX_EOF_INT_ST1_V << SDIO_SLC0_RX_EOF_INT_ST1_S) +#define SDIO_SLC0_RX_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_ST1_S 17 +/** SDIO_SLC0_TOHOST_INT_ST1 : RO; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOHOST_INT_ST1 (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_ST1_M (SDIO_SLC0_TOHOST_INT_ST1_V << SDIO_SLC0_TOHOST_INT_ST1_S) +#define SDIO_SLC0_TOHOST_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_ST1_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_ST1 : RO; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1 (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_M (SDIO_SLC0_TX_DSCR_ERR_INT_ST1_V << SDIO_SLC0_TX_DSCR_ERR_INT_ST1_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_ST1 : RO; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1 (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_M (SDIO_SLC0_RX_DSCR_ERR_INT_ST1_V << SDIO_SLC0_RX_DSCR_ERR_INT_ST1_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1 : RO; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1 (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_ST1 : RO; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_ST1 (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_M (SDIO_SLC0_HOST_RD_ACK_INT_ST1_V << SDIO_SLC0_HOST_RD_ACK_INT_ST1_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_ST1 : RO; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1 (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_M (SDIO_SLC0_WR_RETRY_DONE_INT_ST1_V << SDIO_SLC0_WR_RETRY_DONE_INT_ST1_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_ST1 : RO; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_ST1 (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_M (SDIO_SLC0_TX_ERR_EOF_INT_ST1_V << SDIO_SLC0_TX_ERR_EOF_INT_ST1_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_S 24 +/** SDIO_CMD_DTC_INT_ST1 : RO; bitpos: [25]; default: 0; + * reserved + */ +#define SDIO_CMD_DTC_INT_ST1 (BIT(25)) +#define SDIO_CMD_DTC_INT_ST1_M (SDIO_CMD_DTC_INT_ST1_V << SDIO_CMD_DTC_INT_ST1_S) +#define SDIO_CMD_DTC_INT_ST1_V 0x00000001U +#define SDIO_CMD_DTC_INT_ST1_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_ST1 : RO; bitpos: [26]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1 (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_M (SDIO_SLC0_RX_QUICK_EOF_INT_ST1_V << SDIO_SLC0_RX_QUICK_EOF_INT_ST1_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1 (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_S 27 +/** SDIO_HDA_RECV_DONE_INT_ST1 : RO; bitpos: [28]; default: 0; + * reserved + */ +#define SDIO_HDA_RECV_DONE_INT_ST1 (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_ST1_M (SDIO_HDA_RECV_DONE_INT_ST1_V << SDIO_HDA_RECV_DONE_INT_ST1_S) +#define SDIO_HDA_RECV_DONE_INT_ST1_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_ST1_S 28 + +/** SDIO_SLC0INT_ENA1_REG register + * reserved + */ +#define SDIO_SLC0INT_ENA1_REG (DR_REG_SLC_BASE + 0x148) +/** SDIO_SLC_FRHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT0_INT_ENA1 (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_M (SDIO_SLC_FRHOST_BIT0_INT_ENA1_V << SDIO_SLC_FRHOST_BIT0_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT1_INT_ENA1 (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_M (SDIO_SLC_FRHOST_BIT1_INT_ENA1_V << SDIO_SLC_FRHOST_BIT1_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT2_INT_ENA1 (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_M (SDIO_SLC_FRHOST_BIT2_INT_ENA1_V << SDIO_SLC_FRHOST_BIT2_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT3_INT_ENA1 (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_M (SDIO_SLC_FRHOST_BIT3_INT_ENA1_V << SDIO_SLC_FRHOST_BIT3_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT4_INT_ENA1 (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_M (SDIO_SLC_FRHOST_BIT4_INT_ENA1_V << SDIO_SLC_FRHOST_BIT4_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT5_INT_ENA1 (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_M (SDIO_SLC_FRHOST_BIT5_INT_ENA1_V << SDIO_SLC_FRHOST_BIT5_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT6_INT_ENA1 (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_M (SDIO_SLC_FRHOST_BIT6_INT_ENA1_V << SDIO_SLC_FRHOST_BIT6_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT7_INT_ENA1 (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_M (SDIO_SLC_FRHOST_BIT7_INT_ENA1_V << SDIO_SLC_FRHOST_BIT7_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_S 7 +/** SDIO_SLC0_RX_START_INT_ENA1 : R/W; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_START_INT_ENA1 (BIT(8)) +#define SDIO_SLC0_RX_START_INT_ENA1_M (SDIO_SLC0_RX_START_INT_ENA1_V << SDIO_SLC0_RX_START_INT_ENA1_S) +#define SDIO_SLC0_RX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_ENA1_S 8 +/** SDIO_SLC0_TX_START_INT_ENA1 : R/W; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_START_INT_ENA1 (BIT(9)) +#define SDIO_SLC0_TX_START_INT_ENA1_M (SDIO_SLC0_TX_START_INT_ENA1_V << SDIO_SLC0_TX_START_INT_ENA1_S) +#define SDIO_SLC0_TX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_ENA1_S 9 +/** SDIO_SLC0_RX_UDF_INT_ENA1 : R/W; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_UDF_INT_ENA1 (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_ENA1_M (SDIO_SLC0_RX_UDF_INT_ENA1_V << SDIO_SLC0_RX_UDF_INT_ENA1_S) +#define SDIO_SLC0_RX_UDF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_ENA1_S 10 +/** SDIO_SLC0_TX_OVF_INT_ENA1 : R/W; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_OVF_INT_ENA1 (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_ENA1_M (SDIO_SLC0_TX_OVF_INT_ENA1_V << SDIO_SLC0_TX_OVF_INT_ENA1_S) +#define SDIO_SLC0_TX_OVF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_ENA1_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1 (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_M (SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1 (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_M (SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_S 13 +/** SDIO_SLC0_TX_DONE_INT_ENA1 : R/W; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DONE_INT_ENA1 (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_ENA1_M (SDIO_SLC0_TX_DONE_INT_ENA1_V << SDIO_SLC0_TX_DONE_INT_ENA1_S) +#define SDIO_SLC0_TX_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_ENA1_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_ENA1 : R/W; bitpos: [15]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1 (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_M (SDIO_SLC0_TX_SUC_EOF_INT_ENA1_V << SDIO_SLC0_TX_SUC_EOF_INT_ENA1_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_S 15 +/** SDIO_SLC0_RX_DONE_INT_ENA1 : R/W; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_DONE_INT_ENA1 (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_ENA1_M (SDIO_SLC0_RX_DONE_INT_ENA1_V << SDIO_SLC0_RX_DONE_INT_ENA1_S) +#define SDIO_SLC0_RX_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_ENA1_S 16 +/** SDIO_SLC0_RX_EOF_INT_ENA1 : R/W; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_EOF_INT_ENA1 (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_ENA1_M (SDIO_SLC0_RX_EOF_INT_ENA1_V << SDIO_SLC0_RX_EOF_INT_ENA1_S) +#define SDIO_SLC0_RX_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_ENA1_S 17 +/** SDIO_SLC0_TOHOST_INT_ENA1 : R/W; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOHOST_INT_ENA1 (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_ENA1_M (SDIO_SLC0_TOHOST_INT_ENA1_V << SDIO_SLC0_TOHOST_INT_ENA1_S) +#define SDIO_SLC0_TOHOST_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_ENA1_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1 (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_M (SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_V << SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1 (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_M (SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_V << SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1 : R/W; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1 (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_ENA1 : R/W; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1 (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_M (SDIO_SLC0_HOST_RD_ACK_INT_ENA1_V << SDIO_SLC0_HOST_RD_ACK_INT_ENA1_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_ENA1 : R/W; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1 (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_M (SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_V << SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_ENA1 : R/W; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1 (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_M (SDIO_SLC0_TX_ERR_EOF_INT_ENA1_V << SDIO_SLC0_TX_ERR_EOF_INT_ENA1_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_S 24 +/** SDIO_CMD_DTC_INT_ENA1 : R/W; bitpos: [25]; default: 0; + * reserved + */ +#define SDIO_CMD_DTC_INT_ENA1 (BIT(25)) +#define SDIO_CMD_DTC_INT_ENA1_M (SDIO_CMD_DTC_INT_ENA1_V << SDIO_CMD_DTC_INT_ENA1_S) +#define SDIO_CMD_DTC_INT_ENA1_V 0x00000001U +#define SDIO_CMD_DTC_INT_ENA1_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_ENA1 : R/W; bitpos: [26]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1 (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_M (SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_V << SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1 : R/W; bitpos: [27]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1 (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S 27 +/** SDIO_HDA_RECV_DONE_INT_ENA1 : R/W; bitpos: [28]; default: 0; + * reserved + */ +#define SDIO_HDA_RECV_DONE_INT_ENA1 (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_ENA1_M (SDIO_HDA_RECV_DONE_INT_ENA1_V << SDIO_HDA_RECV_DONE_INT_ENA1_S) +#define SDIO_HDA_RECV_DONE_INT_ENA1_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_ENA1_S 28 + +/** SDIO_SLC1INT_ST1_REG register + * reserved + */ +#define SDIO_SLC1INT_ST1_REG (DR_REG_SLC_BASE + 0x14c) +/** SDIO_SLC_FRHOST_BIT8_INT_ST1 : RO; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT8_INT_ST1 (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_ST1_M (SDIO_SLC_FRHOST_BIT8_INT_ST1_V << SDIO_SLC_FRHOST_BIT8_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT8_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_ST1_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_ST1 : RO; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT9_INT_ST1 (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_ST1_M (SDIO_SLC_FRHOST_BIT9_INT_ST1_V << SDIO_SLC_FRHOST_BIT9_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT9_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_ST1_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_ST1 : RO; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT10_INT_ST1 (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_ST1_M (SDIO_SLC_FRHOST_BIT10_INT_ST1_V << SDIO_SLC_FRHOST_BIT10_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT10_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_ST1_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_ST1 : RO; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT11_INT_ST1 (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_ST1_M (SDIO_SLC_FRHOST_BIT11_INT_ST1_V << SDIO_SLC_FRHOST_BIT11_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT11_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_ST1_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_ST1 : RO; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT12_INT_ST1 (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_ST1_M (SDIO_SLC_FRHOST_BIT12_INT_ST1_V << SDIO_SLC_FRHOST_BIT12_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT12_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_ST1_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_ST1 : RO; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT13_INT_ST1 (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_ST1_M (SDIO_SLC_FRHOST_BIT13_INT_ST1_V << SDIO_SLC_FRHOST_BIT13_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT13_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_ST1_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_ST1 : RO; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT14_INT_ST1 (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_ST1_M (SDIO_SLC_FRHOST_BIT14_INT_ST1_V << SDIO_SLC_FRHOST_BIT14_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT14_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_ST1_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_ST1 : RO; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT15_INT_ST1 (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_ST1_M (SDIO_SLC_FRHOST_BIT15_INT_ST1_V << SDIO_SLC_FRHOST_BIT15_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT15_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_ST1_S 7 +/** SDIO_SLC1_RX_START_INT_ST1 : RO; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_START_INT_ST1 (BIT(8)) +#define SDIO_SLC1_RX_START_INT_ST1_M (SDIO_SLC1_RX_START_INT_ST1_V << SDIO_SLC1_RX_START_INT_ST1_S) +#define SDIO_SLC1_RX_START_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_ST1_S 8 +/** SDIO_SLC1_TX_START_INT_ST1 : RO; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_START_INT_ST1 (BIT(9)) +#define SDIO_SLC1_TX_START_INT_ST1_M (SDIO_SLC1_TX_START_INT_ST1_V << SDIO_SLC1_TX_START_INT_ST1_S) +#define SDIO_SLC1_TX_START_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_ST1_S 9 +/** SDIO_SLC1_RX_UDF_INT_ST1 : RO; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_UDF_INT_ST1 (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_ST1_M (SDIO_SLC1_RX_UDF_INT_ST1_V << SDIO_SLC1_RX_UDF_INT_ST1_S) +#define SDIO_SLC1_RX_UDF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_ST1_S 10 +/** SDIO_SLC1_TX_OVF_INT_ST1 : RO; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_OVF_INT_ST1 (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_ST1_M (SDIO_SLC1_TX_OVF_INT_ST1_V << SDIO_SLC1_TX_OVF_INT_ST1_S) +#define SDIO_SLC1_TX_OVF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_ST1_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_ST1 : RO; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1 (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_M (SDIO_SLC1_TOKEN0_1TO0_INT_ST1_V << SDIO_SLC1_TOKEN0_1TO0_INT_ST1_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_ST1 : RO; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1 (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_M (SDIO_SLC1_TOKEN1_1TO0_INT_ST1_V << SDIO_SLC1_TOKEN1_1TO0_INT_ST1_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_S 13 +/** SDIO_SLC1_TX_DONE_INT_ST1 : RO; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DONE_INT_ST1 (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_ST1_M (SDIO_SLC1_TX_DONE_INT_ST1_V << SDIO_SLC1_TX_DONE_INT_ST1_S) +#define SDIO_SLC1_TX_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_ST1_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_ST1 : RO; bitpos: [15]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_ST1 (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_M (SDIO_SLC1_TX_SUC_EOF_INT_ST1_V << SDIO_SLC1_TX_SUC_EOF_INT_ST1_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_S 15 +/** SDIO_SLC1_RX_DONE_INT_ST1 : RO; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DONE_INT_ST1 (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_ST1_M (SDIO_SLC1_RX_DONE_INT_ST1_V << SDIO_SLC1_RX_DONE_INT_ST1_S) +#define SDIO_SLC1_RX_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_ST1_S 16 +/** SDIO_SLC1_RX_EOF_INT_ST1 : RO; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_EOF_INT_ST1 (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_ST1_M (SDIO_SLC1_RX_EOF_INT_ST1_V << SDIO_SLC1_RX_EOF_INT_ST1_S) +#define SDIO_SLC1_RX_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_ST1_S 17 +/** SDIO_SLC1_TOHOST_INT_ST1 : RO; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOHOST_INT_ST1 (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_ST1_M (SDIO_SLC1_TOHOST_INT_ST1_V << SDIO_SLC1_TOHOST_INT_ST1_S) +#define SDIO_SLC1_TOHOST_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_ST1_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_ST1 : RO; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1 (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_M (SDIO_SLC1_TX_DSCR_ERR_INT_ST1_V << SDIO_SLC1_TX_DSCR_ERR_INT_ST1_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_ST1 : RO; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1 (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_M (SDIO_SLC1_RX_DSCR_ERR_INT_ST1_V << SDIO_SLC1_RX_DSCR_ERR_INT_ST1_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1 : RO; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1 (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_ST1 : RO; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_ST1 (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_M (SDIO_SLC1_HOST_RD_ACK_INT_ST1_V << SDIO_SLC1_HOST_RD_ACK_INT_ST1_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_ST1 : RO; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1 (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_M (SDIO_SLC1_WR_RETRY_DONE_INT_ST1_V << SDIO_SLC1_WR_RETRY_DONE_INT_ST1_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_ST1 : RO; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_ST1 (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_M (SDIO_SLC1_TX_ERR_EOF_INT_ST1_V << SDIO_SLC1_TX_ERR_EOF_INT_ST1_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_S 24 + +/** SDIO_SLC1INT_ENA1_REG register + * reserved + */ +#define SDIO_SLC1INT_ENA1_REG (DR_REG_SLC_BASE + 0x150) +/** SDIO_SLC_FRHOST_BIT8_INT_ENA1 : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT8_INT_ENA1 (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_M (SDIO_SLC_FRHOST_BIT8_INT_ENA1_V << SDIO_SLC_FRHOST_BIT8_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_ENA1 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT9_INT_ENA1 (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_M (SDIO_SLC_FRHOST_BIT9_INT_ENA1_V << SDIO_SLC_FRHOST_BIT9_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_ENA1 : R/W; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT10_INT_ENA1 (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_M (SDIO_SLC_FRHOST_BIT10_INT_ENA1_V << SDIO_SLC_FRHOST_BIT10_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_ENA1 : R/W; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT11_INT_ENA1 (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_M (SDIO_SLC_FRHOST_BIT11_INT_ENA1_V << SDIO_SLC_FRHOST_BIT11_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_ENA1 : R/W; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT12_INT_ENA1 (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_M (SDIO_SLC_FRHOST_BIT12_INT_ENA1_V << SDIO_SLC_FRHOST_BIT12_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_ENA1 : R/W; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT13_INT_ENA1 (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_M (SDIO_SLC_FRHOST_BIT13_INT_ENA1_V << SDIO_SLC_FRHOST_BIT13_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_ENA1 : R/W; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT14_INT_ENA1 (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_M (SDIO_SLC_FRHOST_BIT14_INT_ENA1_V << SDIO_SLC_FRHOST_BIT14_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_ENA1 : R/W; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT15_INT_ENA1 (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_M (SDIO_SLC_FRHOST_BIT15_INT_ENA1_V << SDIO_SLC_FRHOST_BIT15_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_S 7 +/** SDIO_SLC1_RX_START_INT_ENA1 : R/W; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_START_INT_ENA1 (BIT(8)) +#define SDIO_SLC1_RX_START_INT_ENA1_M (SDIO_SLC1_RX_START_INT_ENA1_V << SDIO_SLC1_RX_START_INT_ENA1_S) +#define SDIO_SLC1_RX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_ENA1_S 8 +/** SDIO_SLC1_TX_START_INT_ENA1 : R/W; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_START_INT_ENA1 (BIT(9)) +#define SDIO_SLC1_TX_START_INT_ENA1_M (SDIO_SLC1_TX_START_INT_ENA1_V << SDIO_SLC1_TX_START_INT_ENA1_S) +#define SDIO_SLC1_TX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_ENA1_S 9 +/** SDIO_SLC1_RX_UDF_INT_ENA1 : R/W; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_UDF_INT_ENA1 (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_ENA1_M (SDIO_SLC1_RX_UDF_INT_ENA1_V << SDIO_SLC1_RX_UDF_INT_ENA1_S) +#define SDIO_SLC1_RX_UDF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_ENA1_S 10 +/** SDIO_SLC1_TX_OVF_INT_ENA1 : R/W; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_OVF_INT_ENA1 (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_ENA1_M (SDIO_SLC1_TX_OVF_INT_ENA1_V << SDIO_SLC1_TX_OVF_INT_ENA1_S) +#define SDIO_SLC1_TX_OVF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_ENA1_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1 (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_M (SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1 (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_M (SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_S 13 +/** SDIO_SLC1_TX_DONE_INT_ENA1 : R/W; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DONE_INT_ENA1 (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_ENA1_M (SDIO_SLC1_TX_DONE_INT_ENA1_V << SDIO_SLC1_TX_DONE_INT_ENA1_S) +#define SDIO_SLC1_TX_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_ENA1_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_ENA1 : R/W; bitpos: [15]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1 (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_M (SDIO_SLC1_TX_SUC_EOF_INT_ENA1_V << SDIO_SLC1_TX_SUC_EOF_INT_ENA1_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_S 15 +/** SDIO_SLC1_RX_DONE_INT_ENA1 : R/W; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DONE_INT_ENA1 (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_ENA1_M (SDIO_SLC1_RX_DONE_INT_ENA1_V << SDIO_SLC1_RX_DONE_INT_ENA1_S) +#define SDIO_SLC1_RX_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_ENA1_S 16 +/** SDIO_SLC1_RX_EOF_INT_ENA1 : R/W; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_EOF_INT_ENA1 (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_ENA1_M (SDIO_SLC1_RX_EOF_INT_ENA1_V << SDIO_SLC1_RX_EOF_INT_ENA1_S) +#define SDIO_SLC1_RX_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_ENA1_S 17 +/** SDIO_SLC1_TOHOST_INT_ENA1 : R/W; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOHOST_INT_ENA1 (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_ENA1_M (SDIO_SLC1_TOHOST_INT_ENA1_V << SDIO_SLC1_TOHOST_INT_ENA1_S) +#define SDIO_SLC1_TOHOST_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_ENA1_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1 (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_M (SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_V << SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1 (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_M (SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_V << SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1 : R/W; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1 (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_ENA1 : R/W; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1 (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_M (SDIO_SLC1_HOST_RD_ACK_INT_ENA1_V << SDIO_SLC1_HOST_RD_ACK_INT_ENA1_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_ENA1 : R/W; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1 (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_M (SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_V << SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_ENA1 : R/W; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1 (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_M (SDIO_SLC1_TX_ERR_EOF_INT_ENA1_V << SDIO_SLC1_TX_ERR_EOF_INT_ENA1_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_S 24 + +/** SDIO_SLC0_TX_SHAREMEM_START_REG register + * reserved + */ +#define SDIO_SLC0_TX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x154) +/** SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC0_TX_SHAREMEM_END_REG register + * reserved + */ +#define SDIO_SLC0_TX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x158) +/** SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ +#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_S) +#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_S 0 + +/** SDIO_SLC0_RX_SHAREMEM_START_REG register + * reserved + */ +#define SDIO_SLC0_RX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x15c) +/** SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC0_RX_SHAREMEM_END_REG register + * reserved + */ +#define SDIO_SLC0_RX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x160) +/** SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ +#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_S) +#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_S 0 + +/** SDIO_SLC1_TX_SHAREMEM_START_REG register + * reserved + */ +#define SDIO_SLC1_TX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x164) +/** SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC1_TX_SHAREMEM_END_REG register + * reserved + */ +#define SDIO_SLC1_TX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x168) +/** SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ +#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_S) +#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_S 0 + +/** SDIO_SLC1_RX_SHAREMEM_START_REG register + * reserved + */ +#define SDIO_SLC1_RX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x16c) +/** SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC1_RX_SHAREMEM_END_REG register + * reserved + */ +#define SDIO_SLC1_RX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x170) +/** SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ +#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_S) +#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_S 0 + +/** SDIO_HDA_TX_SHAREMEM_START_REG register + * reserved + */ +#define SDIO_HDA_TX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x174) +/** SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_M (SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_HDA_RX_SHAREMEM_START_REG register + * reserved + */ +#define SDIO_HDA_RX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x178) +/** SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_M (SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC_BURST_LEN_REG register + * reserved + */ +#define SDIO_SLC_BURST_LEN_REG (DR_REG_SLC_BASE + 0x17c) +/** SDIO_SLC0_TXDATA_BURST_LEN : R/W; bitpos: [0]; default: 1; + * 0-incr4,1-incr8 + */ +#define SDIO_SLC0_TXDATA_BURST_LEN (BIT(0)) +#define SDIO_SLC0_TXDATA_BURST_LEN_M (SDIO_SLC0_TXDATA_BURST_LEN_V << SDIO_SLC0_TXDATA_BURST_LEN_S) +#define SDIO_SLC0_TXDATA_BURST_LEN_V 0x00000001U +#define SDIO_SLC0_TXDATA_BURST_LEN_S 0 +/** SDIO_SLC0_RXDATA_BURST_LEN : R/W; bitpos: [1]; default: 1; + * 0-incr4,1-incr8 + */ +#define SDIO_SLC0_RXDATA_BURST_LEN (BIT(1)) +#define SDIO_SLC0_RXDATA_BURST_LEN_M (SDIO_SLC0_RXDATA_BURST_LEN_V << SDIO_SLC0_RXDATA_BURST_LEN_S) +#define SDIO_SLC0_RXDATA_BURST_LEN_V 0x00000001U +#define SDIO_SLC0_RXDATA_BURST_LEN_S 1 +/** SDIO_SLC1_TXDATA_BURST_LEN : R/W; bitpos: [2]; default: 1; + * 0-incr4,1-incr8 + */ +#define SDIO_SLC1_TXDATA_BURST_LEN (BIT(2)) +#define SDIO_SLC1_TXDATA_BURST_LEN_M (SDIO_SLC1_TXDATA_BURST_LEN_V << SDIO_SLC1_TXDATA_BURST_LEN_S) +#define SDIO_SLC1_TXDATA_BURST_LEN_V 0x00000001U +#define SDIO_SLC1_TXDATA_BURST_LEN_S 2 +/** SDIO_SLC1_RXDATA_BURST_LEN : R/W; bitpos: [3]; default: 1; + * 0-incr4,1-incr8 + */ +#define SDIO_SLC1_RXDATA_BURST_LEN (BIT(3)) +#define SDIO_SLC1_RXDATA_BURST_LEN_M (SDIO_SLC1_RXDATA_BURST_LEN_V << SDIO_SLC1_RXDATA_BURST_LEN_S) +#define SDIO_SLC1_RXDATA_BURST_LEN_V 0x00000001U +#define SDIO_SLC1_RXDATA_BURST_LEN_S 3 + +/** SDIO_SLCDATE_REG register + * ******* Description *********** + */ +#define SDIO_SLCDATE_REG (DR_REG_SLC_BASE + 0x1f8) +/** SDIO_SLC_DATE : R/W; bitpos: [31:0]; default: 554182400; + * reserved + */ +#define SDIO_SLC_DATE 0xFFFFFFFFU +#define SDIO_SLC_DATE_M (SDIO_SLC_DATE_V << SDIO_SLC_DATE_S) +#define SDIO_SLC_DATE_V 0xFFFFFFFFU +#define SDIO_SLC_DATE_S 0 + +/** SDIO_SLCID_REG register + * ******* Description *********** + */ +#define SDIO_SLCID_REG (DR_REG_SLC_BASE + 0x1fc) +/** SDIO_SLC_ID : R/W; bitpos: [31:0]; default: 256; + * reserved + */ +#define SDIO_SLC_ID 0xFFFFFFFFU +#define SDIO_SLC_ID_M (SDIO_SLC_ID_V << SDIO_SLC_ID_S) +#define SDIO_SLC_ID_V 0xFFFFFFFFU +#define SDIO_SLC_ID_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/slc_struct.h b/components/soc/esp32c6/include/soc/slc_struct.h new file mode 100644 index 0000000000..8cc3e1b865 --- /dev/null +++ b/components/soc/esp32c6/include/soc/slc_struct.h @@ -0,0 +1,3253 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration registers */ +/** Type of slcconf0 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_tx_rst : R/W; bitpos: [0]; default: 0; + * Set 1 to reset tx fsm in dma slc0. + */ + uint32_t slc0_tx_rst:1; + /** slc0_rx_rst : R/W; bitpos: [1]; default: 0; + * Set 1 to reset rx fsm in dma slc0. + */ + uint32_t slc0_rx_rst:1; + /** slc_ahbm_fifo_rst : R/W; bitpos: [2]; default: 0; + * reset the command fifo of AHB bus of sdio slave + */ + uint32_t slc_ahbm_fifo_rst:1; + /** slc_ahbm_rst : R/W; bitpos: [3]; default: 0; + * reset the AHB bus of sdio slave + */ + uint32_t slc_ahbm_rst:1; + /** slc0_tx_loop_test : R/W; bitpos: [4]; default: 0; + * owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner. + */ + uint32_t slc0_tx_loop_test:1; + /** slc0_rx_loop_test : R/W; bitpos: [5]; default: 0; + * owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner. + */ + uint32_t slc0_rx_loop_test:1; + /** slc0_rx_auto_wrback : R/W; bitpos: [6]; default: 0; + * Set 1 to enable change the owner bit of rx link descriptor + */ + uint32_t slc0_rx_auto_wrback:1; + /** slc0_rx_no_restart_clr : R/W; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc0_rx_no_restart_clr:1; + /** slc0_rxdscr_burst_en : R/W; bitpos: [8]; default: 1; + * 0- AHB burst type is single when slave read rx-descriptor from memory through + * slc0,1-AHB burst type is not single when slave read rx-descriptor from memory + * through slc0 + */ + uint32_t slc0_rxdscr_burst_en:1; + /** slc0_rxdata_burst_en : R/W; bitpos: [9]; default: 1; + * 0- AHB burst type is single when slave receives data from memory,1-AHB burst type + * is not single when slave receives data from memory + */ + uint32_t slc0_rxdata_burst_en:1; + /** slc0_rxlink_auto_ret : R/W; bitpos: [10]; default: 1; + * enable the function that when host reading packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ + uint32_t slc0_rxlink_auto_ret:1; + /** slc0_txlink_auto_ret : R/W; bitpos: [11]; default: 1; + * enable the function that when host sending packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ + uint32_t slc0_txlink_auto_ret:1; + /** slc0_txdscr_burst_en : R/W; bitpos: [12]; default: 1; + * 0- AHB burst type is single when slave read tx-descriptor from memory through + * slc0,1-AHB burst type is not single when slave read tx-descriptor from memory + * through slc0 + */ + uint32_t slc0_txdscr_burst_en:1; + /** slc0_txdata_burst_en : R/W; bitpos: [13]; default: 1; + * 0- AHB burst type is single when slave send data to memory,1-AHB burst type is not + * single when slave send data to memory + */ + uint32_t slc0_txdata_burst_en:1; + /** slc0_token_auto_clr : R/W; bitpos: [14]; default: 1; + * auto clear slc0_token1 enable + */ + uint32_t slc0_token_auto_clr:1; + /** slc0_token_sel : R/W; bitpos: [15]; default: 1; + * reserved + */ + uint32_t slc0_token_sel:1; + /** slc1_tx_rst : R/W; bitpos: [16]; default: 0; + * Set 1 to reset tx fsm in dma slc0. + */ + uint32_t slc1_tx_rst:1; + /** slc1_rx_rst : R/W; bitpos: [17]; default: 0; + * Set 1 to reset rx fsm in dma slc0. + */ + uint32_t slc1_rx_rst:1; + /** slc0_wr_retry_mask_en : R/W; bitpos: [18]; default: 1; + * reserved + */ + uint32_t slc0_wr_retry_mask_en:1; + /** slc1_wr_retry_mask_en : R/W; bitpos: [19]; default: 1; + * reserved + */ + uint32_t slc1_wr_retry_mask_en:1; + /** slc1_tx_loop_test : R/W; bitpos: [20]; default: 1; + * owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner. + */ + uint32_t slc1_tx_loop_test:1; + /** slc1_rx_loop_test : R/W; bitpos: [21]; default: 1; + * owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner. + */ + uint32_t slc1_rx_loop_test:1; + /** slc1_rx_auto_wrback : R/W; bitpos: [22]; default: 0; + * Set 1 to enable change the owner bit of rx link descriptor + */ + uint32_t slc1_rx_auto_wrback:1; + /** slc1_rx_no_restart_clr : R/W; bitpos: [23]; default: 0; + * ******* Description *********** + */ + uint32_t slc1_rx_no_restart_clr:1; + /** slc1_rxdscr_burst_en : R/W; bitpos: [24]; default: 1; + * 0- AHB burst type is single when slave read rx-descriptor from memory through + * slc1,1-AHB burst type is not single when slave read rx-descriptor from memory + * through slc1 + */ + uint32_t slc1_rxdscr_burst_en:1; + /** slc1_rxdata_burst_en : R/W; bitpos: [25]; default: 1; + * 0- AHB burst type is single when slave receives data from memory,1-AHB burst type + * is not single when slave receives data from memory + */ + uint32_t slc1_rxdata_burst_en:1; + /** slc1_rxlink_auto_ret : R/W; bitpos: [26]; default: 1; + * enable the function that when host reading packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ + uint32_t slc1_rxlink_auto_ret:1; + /** slc1_txlink_auto_ret : R/W; bitpos: [27]; default: 1; + * enable the function that when host sending packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ + uint32_t slc1_txlink_auto_ret:1; + /** slc1_txdscr_burst_en : R/W; bitpos: [28]; default: 1; + * 0- AHB burst type is single when slave read tx-descriptor from memory through + * slc1,1-AHB burst type is not single when slave read tx-descriptor from memory + * through slc1 + */ + uint32_t slc1_txdscr_burst_en:1; + /** slc1_txdata_burst_en : R/W; bitpos: [29]; default: 1; + * 0- AHB burst type is single when slave send data to memory,1-AHB burst type is not + * single when slave send data to memory + */ + uint32_t slc1_txdata_burst_en:1; + /** slc1_token_auto_clr : R/W; bitpos: [30]; default: 1; + * auto clear slc1_token1 enable + */ + uint32_t slc1_token_auto_clr:1; + /** slc1_token_sel : R/W; bitpos: [31]; default: 1; + * reserved + */ + uint32_t slc1_token_sel:1; + }; + uint32_t val; +} sdio_slcconf0_reg_t; + +/** Type of slc0rxfifo_push register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_rxfifo_wdata : R/W; bitpos: [8:0]; default: 0; + * reserved + */ + uint32_t slc0_rxfifo_wdata:9; + uint32_t reserved_9:7; + /** slc0_rxfifo_push : R/W/SC; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc0_rxfifo_push:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc0rxfifo_push_reg_t; + +/** Type of slc1rxfifo_push register + * reserved + */ +typedef union { + struct { + /** slc1_rxfifo_wdata : R/W; bitpos: [8:0]; default: 0; + * reserved + */ + uint32_t slc1_rxfifo_wdata:9; + uint32_t reserved_9:7; + /** slc1_rxfifo_push : R/W/SC; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc1_rxfifo_push:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc1rxfifo_push_reg_t; + +/** Type of slc0rx_link register + * reserved + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** slc0_rxlink_stop : R/W/SC; bitpos: [28]; default: 0; + * reserved + */ + uint32_t slc0_rxlink_stop:1; + /** slc0_rxlink_start : R/W/SC; bitpos: [29]; default: 0; + * reserved + */ + uint32_t slc0_rxlink_start:1; + /** slc0_rxlink_restart : R/W/SC; bitpos: [30]; default: 0; + * reserved + */ + uint32_t slc0_rxlink_restart:1; + /** slc0_rxlink_park : RO; bitpos: [31]; default: 1; + * reserved + */ + uint32_t slc0_rxlink_park:1; + }; + uint32_t val; +} sdio_slc0rx_link_reg_t; + +/** Type of slc0rx_link_addr register + * reserved + */ +typedef union { + struct { + /** slc0_rxlink_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_rxlink_addr:32; + }; + uint32_t val; +} sdio_slc0rx_link_addr_reg_t; + +/** Type of slc0tx_link register + * reserved + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** slc0_txlink_stop : R/W/SC; bitpos: [28]; default: 0; + * reserved + */ + uint32_t slc0_txlink_stop:1; + /** slc0_txlink_start : R/W/SC; bitpos: [29]; default: 0; + * reserved + */ + uint32_t slc0_txlink_start:1; + /** slc0_txlink_restart : R/W/SC; bitpos: [30]; default: 0; + * reserved + */ + uint32_t slc0_txlink_restart:1; + /** slc0_txlink_park : RO; bitpos: [31]; default: 1; + * reserved + */ + uint32_t slc0_txlink_park:1; + }; + uint32_t val; +} sdio_slc0tx_link_reg_t; + +/** Type of slc0tx_link_addr register + * reserved + */ +typedef union { + struct { + /** slc0_txlink_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_txlink_addr:32; + }; + uint32_t val; +} sdio_slc0tx_link_addr_reg_t; + +/** Type of slc1rx_link register + * reserved + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** slc1_bt_packet : R/W; bitpos: [20]; default: 1; + * reserved + */ + uint32_t slc1_bt_packet:1; + uint32_t reserved_21:7; + /** slc1_rxlink_stop : R/W/SC; bitpos: [28]; default: 0; + * reserved + */ + uint32_t slc1_rxlink_stop:1; + /** slc1_rxlink_start : R/W/SC; bitpos: [29]; default: 0; + * reserved + */ + uint32_t slc1_rxlink_start:1; + /** slc1_rxlink_restart : R/W/SC; bitpos: [30]; default: 0; + * reserved + */ + uint32_t slc1_rxlink_restart:1; + /** slc1_rxlink_park : RO; bitpos: [31]; default: 1; + * reserved + */ + uint32_t slc1_rxlink_park:1; + }; + uint32_t val; +} sdio_slc1rx_link_reg_t; + +/** Type of slc1rx_link_addr register + * reserved + */ +typedef union { + struct { + /** slc1_rxlink_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_rxlink_addr:32; + }; + uint32_t val; +} sdio_slc1rx_link_addr_reg_t; + +/** Type of slc1tx_link register + * reserved + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** slc1_txlink_stop : R/W/SC; bitpos: [28]; default: 0; + * reserved + */ + uint32_t slc1_txlink_stop:1; + /** slc1_txlink_start : R/W/SC; bitpos: [29]; default: 0; + * reserved + */ + uint32_t slc1_txlink_start:1; + /** slc1_txlink_restart : R/W/SC; bitpos: [30]; default: 0; + * reserved + */ + uint32_t slc1_txlink_restart:1; + /** slc1_txlink_park : RO; bitpos: [31]; default: 1; + * reserved + */ + uint32_t slc1_txlink_park:1; + }; + uint32_t val; +} sdio_slc1tx_link_reg_t; + +/** Type of slc1tx_link_addr register + * reserved + */ +typedef union { + struct { + /** slc1_txlink_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_txlink_addr:32; + }; + uint32_t val; +} sdio_slc1tx_link_addr_reg_t; + +/** Type of slcintvec_tohost register + * reserved + */ +typedef union { + struct { + /** slc0_tohost_intvec : WT; bitpos: [7:0]; default: 0; + * reserved + */ + uint32_t slc0_tohost_intvec:8; + uint32_t reserved_8:8; + /** slc1_tohost_intvec : WT; bitpos: [23:16]; default: 0; + * reserved + */ + uint32_t slc1_tohost_intvec:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} sdio_slcintvec_tohost_reg_t; + +/** Type of slc0token0 register + * reserved + */ +typedef union { + struct { + /** slc0_token0_wdata : WT; bitpos: [11:0]; default: 0; + * reserved + */ + uint32_t slc0_token0_wdata:12; + /** slc0_token0_wr : WT; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc0_token0_wr:1; + /** slc0_token0_inc : WT; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc0_token0_inc:1; + /** slc0_token0_inc_more : WT; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc0_token0_inc_more:1; + uint32_t reserved_15:1; + /** slc0_token0 : RO; bitpos: [27:16]; default: 0; + * reserved + */ + uint32_t slc0_token0:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc0token0_reg_t; + +/** Type of slc0token1 register + * reserved + */ +typedef union { + struct { + /** slc0_token1_wdata : WT; bitpos: [11:0]; default: 0; + * slc0 token1 wdata + */ + uint32_t slc0_token1_wdata:12; + /** slc0_token1_wr : WT; bitpos: [12]; default: 0; + * update slc0_token1_wdata into slc0 token1 + */ + uint32_t slc0_token1_wr:1; + /** slc0_token1_inc : WT; bitpos: [13]; default: 0; + * slc0_token1 becomes to 1 when auto clear slc0_token1, else add 1 to slc0_token1 + */ + uint32_t slc0_token1_inc:1; + /** slc0_token1_inc_more : WT; bitpos: [14]; default: 0; + * slc0_token1 becomes to slc0_token1_wdata when auto clear slc0_token1, else add + * slc0_token1_wdata to slc0_token1 + */ + uint32_t slc0_token1_inc_more:1; + uint32_t reserved_15:1; + /** slc0_token1 : RO; bitpos: [27:16]; default: 0; + * reserved + */ + uint32_t slc0_token1:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc0token1_reg_t; + +/** Type of slc1token0 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc1_token0_wdata : WT; bitpos: [11:0]; default: 0; + * reserved + */ + uint32_t slc1_token0_wdata:12; + /** slc1_token0_wr : WT; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc1_token0_wr:1; + /** slc1_token0_inc : WT; bitpos: [13]; default: 0; + * Add 1 to slc1_token0 + */ + uint32_t slc1_token0_inc:1; + /** slc1_token0_inc_more : WT; bitpos: [14]; default: 0; + * Add slc1_token0_wdata to slc1_token0 + */ + uint32_t slc1_token0_inc_more:1; + uint32_t reserved_15:1; + /** slc1_token0 : RO; bitpos: [27:16]; default: 0; + * reserved + */ + uint32_t slc1_token0:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc1token0_reg_t; + +/** Type of slc1token1 register + * reserved + */ +typedef union { + struct { + /** slc1_token1_wdata : WT; bitpos: [11:0]; default: 0; + * reserved + */ + uint32_t slc1_token1_wdata:12; + /** slc1_token1_wr : WT; bitpos: [12]; default: 0; + * update slc1_token1_wdata into slc1 token1 + */ + uint32_t slc1_token1_wr:1; + /** slc1_token1_inc : WT; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc1_token1_inc:1; + /** slc1_token1_inc_more : WT; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc1_token1_inc_more:1; + uint32_t reserved_15:1; + /** slc1_token1 : RO; bitpos: [27:16]; default: 0; + * reserved + */ + uint32_t slc1_token1:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc1token1_reg_t; + +/** Type of slcconf1 register + * reserved + */ +typedef union { + struct { + /** slc0_check_owner : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc0_check_owner:1; + /** slc0_tx_check_sum_en : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc0_tx_check_sum_en:1; + /** slc0_rx_check_sum_en : R/W; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc0_rx_check_sum_en:1; + /** sdio_cmd_hold_en : R/W; bitpos: [3]; default: 1; + * reserved + */ + uint32_t sdio_cmd_hold_en:1; + /** slc0_len_auto_clr : R/W; bitpos: [4]; default: 1; + * reserved + */ + uint32_t slc0_len_auto_clr:1; + /** slc0_tx_stitch_en : R/W; bitpos: [5]; default: 1; + * reserved + */ + uint32_t slc0_tx_stitch_en:1; + /** slc0_rx_stitch_en : R/W; bitpos: [6]; default: 1; + * reserved + */ + uint32_t slc0_rx_stitch_en:1; + uint32_t reserved_7:9; + /** slc1_check_owner : R/W; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc1_check_owner:1; + /** slc1_tx_check_sum_en : R/W; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc1_tx_check_sum_en:1; + /** slc1_rx_check_sum_en : R/W; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc1_rx_check_sum_en:1; + /** host_int_level_sel : R/W; bitpos: [19]; default: 0; + * reserved + */ + uint32_t host_int_level_sel:1; + /** slc1_tx_stitch_en : R/W; bitpos: [20]; default: 1; + * reserved + */ + uint32_t slc1_tx_stitch_en:1; + /** slc1_rx_stitch_en : R/W; bitpos: [21]; default: 1; + * reserved + */ + uint32_t slc1_rx_stitch_en:1; + /** sdio_clk_en : R/W; bitpos: [22]; default: 0; + * reserved + */ + uint32_t sdio_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} sdio_slcconf1_reg_t; + +/** Type of slcbridge_conf register + * ******* Description *********** + */ +typedef union { + struct { + /** slc_txeof_ena : R/W; bitpos: [5:0]; default: 32; + * reserved + */ + uint32_t slc_txeof_ena:6; + uint32_t reserved_6:2; + /** slc_fifo_map_ena : R/W; bitpos: [11:8]; default: 7; + * reserved + */ + uint32_t slc_fifo_map_ena:4; + /** slc0_tx_dummy_mode : R/W; bitpos: [12]; default: 1; + * reserved + */ + uint32_t slc0_tx_dummy_mode:1; + /** slc_hda_map_128k : R/W; bitpos: [13]; default: 1; + * reserved + */ + uint32_t slc_hda_map_128k:1; + /** slc1_tx_dummy_mode : R/W; bitpos: [14]; default: 1; + * reserved + */ + uint32_t slc1_tx_dummy_mode:1; + uint32_t reserved_15:1; + /** slc_tx_push_idle_num : R/W; bitpos: [31:16]; default: 10; + * reserved + */ + uint32_t slc_tx_push_idle_num:16; + }; + uint32_t val; +} sdio_slcbridge_conf_reg_t; + +/** Type of slc0_to_eof_des_addr register + * reserved + */ +typedef union { + struct { + /** slc0_to_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_to_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc0_to_eof_des_addr_reg_t; + +/** Type of slc0_tx_eof_des_addr register + * reserved + */ +typedef union { + struct { + /** slc0_tx_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_tx_suc_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc0_tx_eof_des_addr_reg_t; + +/** Type of slc0_to_eof_bfr_des_addr register + * reserved + */ +typedef union { + struct { + /** slc0_to_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_to_eof_bfr_des_addr:32; + }; + uint32_t val; +} sdio_slc0_to_eof_bfr_des_addr_reg_t; + +/** Type of slc1_to_eof_des_addr register + * reserved + */ +typedef union { + struct { + /** slc1_to_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_to_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc1_to_eof_des_addr_reg_t; + +/** Type of slc1_tx_eof_des_addr register + * reserved + */ +typedef union { + struct { + /** slc1_tx_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_tx_suc_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc1_tx_eof_des_addr_reg_t; + +/** Type of slc1_to_eof_bfr_des_addr register + * reserved + */ +typedef union { + struct { + /** slc1_to_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_to_eof_bfr_des_addr:32; + }; + uint32_t val; +} sdio_slc1_to_eof_bfr_des_addr_reg_t; + +/** Type of slc_rx_dscr_conf register + * reserved + */ +typedef union { + struct { + /** slc0_token_no_replace : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc0_token_no_replace:1; + /** slc0_infor_no_replace : R/W; bitpos: [1]; default: 1; + * reserved + */ + uint32_t slc0_infor_no_replace:1; + /** slc0_rx_fill_mode : R/W; bitpos: [2]; default: 0; + * slc0 rx pop end control: 0-automatically end when pop finish, 1- end when the next + * pop doesn't occur after 255 cycles since the current pop + */ + uint32_t slc0_rx_fill_mode:1; + /** slc0_rx_eof_mode : R/W; bitpos: [3]; default: 1; + * 0-slc0 rx_push_eof, 1-slc0 rx_pop_eof + */ + uint32_t slc0_rx_eof_mode:1; + /** slc0_rx_fill_en : R/W; bitpos: [4]; default: 1; + * reserved + */ + uint32_t slc0_rx_fill_en:1; + /** slc0_rd_retry_threshold : R/W; bitpos: [15:5]; default: 128; + * reserved + */ + uint32_t slc0_rd_retry_threshold:11; + /** slc1_token_no_replace : R/W; bitpos: [16]; default: 1; + * reserved + */ + uint32_t slc1_token_no_replace:1; + /** slc1_infor_no_replace : R/W; bitpos: [17]; default: 1; + * reserved + */ + uint32_t slc1_infor_no_replace:1; + /** slc1_rx_fill_mode : R/W; bitpos: [18]; default: 0; + * slc1 rx pop end control: 0-automatically end when pop finish, 1- end when the next + * pop doesn't occur after 255 cycles since the current pop + */ + uint32_t slc1_rx_fill_mode:1; + /** slc1_rx_eof_mode : R/W; bitpos: [19]; default: 1; + * 0-slc1 rx_push_eof, 1-slc1 rx_pop_eof + */ + uint32_t slc1_rx_eof_mode:1; + /** slc1_rx_fill_en : R/W; bitpos: [20]; default: 1; + * reserved + */ + uint32_t slc1_rx_fill_en:1; + /** slc1_rd_retry_threshold : R/W; bitpos: [31:21]; default: 128; + * reserved + */ + uint32_t slc1_rd_retry_threshold:11; + }; + uint32_t val; +} sdio_slc_rx_dscr_conf_reg_t; + +/** Type of slc_tx_dscr_conf register + * reserved + */ +typedef union { + struct { + /** slc_wr_retry_threshold : R/W; bitpos: [10:0]; default: 128; + * reserved + */ + uint32_t slc_wr_retry_threshold:11; + uint32_t reserved_11:21; + }; + uint32_t val; +} sdio_slc_tx_dscr_conf_reg_t; + +/** Type of slc0_len_conf register + * reserved + */ +typedef union { + struct { + /** slc0_len_wdata : WT; bitpos: [19:0]; default: 0; + * reserved + */ + uint32_t slc0_len_wdata:20; + /** slc0_len_wr : WT; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc0_len_wr:1; + /** slc0_len_inc : WT; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc0_len_inc:1; + /** slc0_len_inc_more : WT; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc0_len_inc_more:1; + /** slc0_rx_packet_load_en : WT; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc0_rx_packet_load_en:1; + /** slc0_tx_packet_load_en : WT; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc0_tx_packet_load_en:1; + /** slc0_rx_get_used_dscr : WT; bitpos: [25]; default: 0; + * reserved + */ + uint32_t slc0_rx_get_used_dscr:1; + /** slc0_tx_get_used_dscr : WT; bitpos: [26]; default: 0; + * reserved + */ + uint32_t slc0_tx_get_used_dscr:1; + /** slc0_rx_new_pkt_ind : RO; bitpos: [27]; default: 0; + * reserved + */ + uint32_t slc0_rx_new_pkt_ind:1; + /** slc0_tx_new_pkt_ind : RO; bitpos: [28]; default: 1; + * reserved + */ + uint32_t slc0_tx_new_pkt_ind:1; + /** slc0_rx_packet_load_en_st : R/WTC/SC; bitpos: [29]; default: 0; + * reserved + */ + uint32_t slc0_rx_packet_load_en_st:1; + /** slc0_tx_packet_load_en_st : R/WTC/SC; bitpos: [30]; default: 0; + * reserved + */ + uint32_t slc0_tx_packet_load_en_st:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} sdio_slc0_len_conf_reg_t; + +/** Type of slc0_txpkt_h_dscr register + * reserved + */ +typedef union { + struct { + /** slc0_tx_pkt_h_dscr_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_tx_pkt_h_dscr_addr:32; + }; + uint32_t val; +} sdio_slc0_txpkt_h_dscr_reg_t; + +/** Type of slc0_txpkt_e_dscr register + * reserved + */ +typedef union { + struct { + /** slc0_tx_pkt_e_dscr_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_tx_pkt_e_dscr_addr:32; + }; + uint32_t val; +} sdio_slc0_txpkt_e_dscr_reg_t; + +/** Type of slc0_rxpkt_h_dscr register + * reserved + */ +typedef union { + struct { + /** slc0_rx_pkt_h_dscr_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_rx_pkt_h_dscr_addr:32; + }; + uint32_t val; +} sdio_slc0_rxpkt_h_dscr_reg_t; + +/** Type of slc0_rxpkt_e_dscr register + * reserved + */ +typedef union { + struct { + /** slc0_rx_pkt_e_dscr_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_rx_pkt_e_dscr_addr:32; + }; + uint32_t val; +} sdio_slc0_rxpkt_e_dscr_reg_t; + +/** Type of slc0_txpktu_h_dscr register + * reserved + */ +typedef union { + struct { + /** slc0_tx_pkt_start_dscr_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_tx_pkt_start_dscr_addr:32; + }; + uint32_t val; +} sdio_slc0_txpktu_h_dscr_reg_t; + +/** Type of slc0_txpktu_e_dscr register + * reserved + */ +typedef union { + struct { + /** slc0_tx_pkt_end_dscr_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_tx_pkt_end_dscr_addr:32; + }; + uint32_t val; +} sdio_slc0_txpktu_e_dscr_reg_t; + +/** Type of slc0_rxpktu_h_dscr register + * reserved + */ +typedef union { + struct { + /** slc0_rx_pkt_start_dscr_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_rx_pkt_start_dscr_addr:32; + }; + uint32_t val; +} sdio_slc0_rxpktu_h_dscr_reg_t; + +/** Type of slc0_rxpktu_e_dscr register + * reserved + */ +typedef union { + struct { + /** slc0_rx_pkt_end_dscr_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_rx_pkt_end_dscr_addr:32; + }; + uint32_t val; +} sdio_slc0_rxpktu_e_dscr_reg_t; + +/** Type of slc_seq_position register + * reserved + */ +typedef union { + struct { + /** slc0_seq_position : R/W; bitpos: [7:0]; default: 9; + * reserved + */ + uint32_t slc0_seq_position:8; + /** slc1_seq_position : R/W; bitpos: [15:8]; default: 5; + * reserved + */ + uint32_t slc1_seq_position:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} sdio_slc_seq_position_reg_t; + +/** Type of slc0_dscr_rec_conf register + * reserved + */ +typedef union { + struct { + /** slc0_rx_dscr_rec_lim : R/W; bitpos: [9:0]; default: 1023; + * reserved + */ + uint32_t slc0_rx_dscr_rec_lim:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} sdio_slc0_dscr_rec_conf_reg_t; + +/** Type of slc_sdio_crc_st1 register + * reserved + */ +typedef union { + struct { + /** cmd_crc_err_cnt : RO; bitpos: [7:0]; default: 0; + * reserved + */ + uint32_t cmd_crc_err_cnt:8; + uint32_t reserved_8:23; + /** err_cnt_clr : R/W; bitpos: [31]; default: 0; + * reserved + */ + uint32_t err_cnt_clr:1; + }; + uint32_t val; +} sdio_slc_sdio_crc_st1_reg_t; + +/** Type of slc0_len_lim_conf register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_len_lim : R/W; bitpos: [19:0]; default: 21504; + * reserved + */ + uint32_t slc0_len_lim:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} sdio_slc0_len_lim_conf_reg_t; + +/** Type of slc0_tx_sharemem_start register + * reserved + */ +typedef union { + struct { + /** sdio_slc0_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t sdio_slc0_tx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc0_tx_sharemem_start_reg_t; + +/** Type of slc0_tx_sharemem_end register + * reserved + */ +typedef union { + struct { + /** sdio_slc0_tx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ + uint32_t sdio_slc0_tx_sharemem_end_addr:32; + }; + uint32_t val; +} sdio_slc0_tx_sharemem_end_reg_t; + +/** Type of slc0_rx_sharemem_start register + * reserved + */ +typedef union { + struct { + /** sdio_slc0_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t sdio_slc0_rx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc0_rx_sharemem_start_reg_t; + +/** Type of slc0_rx_sharemem_end register + * reserved + */ +typedef union { + struct { + /** sdio_slc0_rx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ + uint32_t sdio_slc0_rx_sharemem_end_addr:32; + }; + uint32_t val; +} sdio_slc0_rx_sharemem_end_reg_t; + +/** Type of slc1_tx_sharemem_start register + * reserved + */ +typedef union { + struct { + /** sdio_slc1_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t sdio_slc1_tx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc1_tx_sharemem_start_reg_t; + +/** Type of slc1_tx_sharemem_end register + * reserved + */ +typedef union { + struct { + /** sdio_slc1_tx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ + uint32_t sdio_slc1_tx_sharemem_end_addr:32; + }; + uint32_t val; +} sdio_slc1_tx_sharemem_end_reg_t; + +/** Type of slc1_rx_sharemem_start register + * reserved + */ +typedef union { + struct { + /** sdio_slc1_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t sdio_slc1_rx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc1_rx_sharemem_start_reg_t; + +/** Type of slc1_rx_sharemem_end register + * reserved + */ +typedef union { + struct { + /** sdio_slc1_rx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ + uint32_t sdio_slc1_rx_sharemem_end_addr:32; + }; + uint32_t val; +} sdio_slc1_rx_sharemem_end_reg_t; + +/** Type of hda_tx_sharemem_start register + * reserved + */ +typedef union { + struct { + /** sdio_hda_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t sdio_hda_tx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_hda_tx_sharemem_start_reg_t; + +/** Type of hda_rx_sharemem_start register + * reserved + */ +typedef union { + struct { + /** sdio_hda_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t sdio_hda_rx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_hda_rx_sharemem_start_reg_t; + +/** Type of slc_burst_len register + * reserved + */ +typedef union { + struct { + /** slc0_txdata_burst_len : R/W; bitpos: [0]; default: 1; + * 0-incr4,1-incr8 + */ + uint32_t slc0_txdata_burst_len:1; + /** slc0_rxdata_burst_len : R/W; bitpos: [1]; default: 1; + * 0-incr4,1-incr8 + */ + uint32_t slc0_rxdata_burst_len:1; + /** slc1_txdata_burst_len : R/W; bitpos: [2]; default: 1; + * 0-incr4,1-incr8 + */ + uint32_t slc1_txdata_burst_len:1; + /** slc1_rxdata_burst_len : R/W; bitpos: [3]; default: 1; + * 0-incr4,1-incr8 + */ + uint32_t slc1_rxdata_burst_len:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} sdio_slc_burst_len_reg_t; + +/** Type of slcid register + * ******* Description *********** + */ +typedef union { + struct { + /** slc_id : R/W; bitpos: [31:0]; default: 256; + * reserved + */ + uint32_t slc_id:32; + }; + uint32_t val; +} sdio_slcid_reg_t; + + +/** Group: Interrupt registers */ +/** Type of slc0int_raw register + * ******* Description *********** + */ +typedef union { + struct { + /** slc_frhost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit0_int_raw:1; + /** slc_frhost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit1_int_raw:1; + /** slc_frhost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit2_int_raw:1; + /** slc_frhost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit3_int_raw:1; + /** slc_frhost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit4_int_raw:1; + /** slc_frhost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit5_int_raw:1; + /** slc_frhost_bit6_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit6_int_raw:1; + /** slc_frhost_bit7_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit7_int_raw:1; + /** slc0_rx_start_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc0_rx_start_int_raw:1; + /** slc0_tx_start_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc0_tx_start_int_raw:1; + /** slc0_rx_udf_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc0_rx_udf_int_raw:1; + /** slc0_tx_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc0_tx_ovf_int_raw:1; + /** slc0_token0_1to0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc0_token0_1to0_int_raw:1; + /** slc0_token1_1to0_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc0_token1_1to0_int_raw:1; + /** slc0_tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit of slc0 finishing receiving data to one buffer + */ + uint32_t slc0_tx_done_int_raw:1; + /** slc0_tx_suc_eof_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit of slc0 finishing receiving data + */ + uint32_t slc0_tx_suc_eof_int_raw:1; + /** slc0_rx_done_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw interrupt bit of slc0 finishing sending data from one buffer + */ + uint32_t slc0_rx_done_int_raw:1; + /** slc0_rx_eof_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw interrupt bit of slc0 finishing sending data + */ + uint32_t slc0_rx_eof_int_raw:1; + /** slc0_tohost_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc0_tohost_int_raw:1; + /** slc0_tx_dscr_err_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw interrupt bit of slc0 tx link descriptor error + */ + uint32_t slc0_tx_dscr_err_int_raw:1; + /** slc0_rx_dscr_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw interrupt bit of slc0 rx link descriptor error + */ + uint32_t slc0_rx_dscr_err_int_raw:1; + /** slc0_tx_dscr_empty_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc0_tx_dscr_empty_int_raw:1; + /** slc0_host_rd_ack_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc0_host_rd_ack_int_raw:1; + /** slc0_wr_retry_done_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc0_wr_retry_done_int_raw:1; + /** slc0_tx_err_eof_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc0_tx_err_eof_int_raw:1; + /** cmd_dtc_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * reserved + */ + uint32_t cmd_dtc_int_raw:1; + /** slc0_rx_quick_eof_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * reserved + */ + uint32_t slc0_rx_quick_eof_int_raw:1; + /** slc0_host_pop_eof_err_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * reserved + */ + uint32_t slc0_host_pop_eof_err_int_raw:1; + /** hda_recv_done_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * reserved + */ + uint32_t hda_recv_done_int_raw:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc0int_raw_reg_t; + +/** Type of slc0int_st register + * ******* Description *********** + */ +typedef union { + struct { + /** slc_frhost_bit0_int_st : RO; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit0_int_st:1; + /** slc_frhost_bit1_int_st : RO; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit1_int_st:1; + /** slc_frhost_bit2_int_st : RO; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit2_int_st:1; + /** slc_frhost_bit3_int_st : RO; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit3_int_st:1; + /** slc_frhost_bit4_int_st : RO; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit4_int_st:1; + /** slc_frhost_bit5_int_st : RO; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit5_int_st:1; + /** slc_frhost_bit6_int_st : RO; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit6_int_st:1; + /** slc_frhost_bit7_int_st : RO; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit7_int_st:1; + /** slc0_rx_start_int_st : RO; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc0_rx_start_int_st:1; + /** slc0_tx_start_int_st : RO; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc0_tx_start_int_st:1; + /** slc0_rx_udf_int_st : RO; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc0_rx_udf_int_st:1; + /** slc0_tx_ovf_int_st : RO; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc0_tx_ovf_int_st:1; + /** slc0_token0_1to0_int_st : RO; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc0_token0_1to0_int_st:1; + /** slc0_token1_1to0_int_st : RO; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc0_token1_1to0_int_st:1; + /** slc0_tx_done_int_st : RO; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc0_tx_done_int_st:1; + /** slc0_tx_suc_eof_int_st : RO; bitpos: [15]; default: 0; + * reserved + */ + uint32_t slc0_tx_suc_eof_int_st:1; + /** slc0_rx_done_int_st : RO; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc0_rx_done_int_st:1; + /** slc0_rx_eof_int_st : RO; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc0_rx_eof_int_st:1; + /** slc0_tohost_int_st : RO; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc0_tohost_int_st:1; + /** slc0_tx_dscr_err_int_st : RO; bitpos: [19]; default: 0; + * reserved + */ + uint32_t slc0_tx_dscr_err_int_st:1; + /** slc0_rx_dscr_err_int_st : RO; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc0_rx_dscr_err_int_st:1; + /** slc0_tx_dscr_empty_int_st : RO; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc0_tx_dscr_empty_int_st:1; + /** slc0_host_rd_ack_int_st : RO; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc0_host_rd_ack_int_st:1; + /** slc0_wr_retry_done_int_st : RO; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc0_wr_retry_done_int_st:1; + /** slc0_tx_err_eof_int_st : RO; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc0_tx_err_eof_int_st:1; + /** cmd_dtc_int_st : RO; bitpos: [25]; default: 0; + * reserved + */ + uint32_t cmd_dtc_int_st:1; + /** slc0_rx_quick_eof_int_st : RO; bitpos: [26]; default: 0; + * reserved + */ + uint32_t slc0_rx_quick_eof_int_st:1; + /** slc0_host_pop_eof_err_int_st : RO; bitpos: [27]; default: 0; + * reserved + */ + uint32_t slc0_host_pop_eof_err_int_st:1; + /** hda_recv_done_int_st : RO; bitpos: [28]; default: 0; + * reserved + */ + uint32_t hda_recv_done_int_st:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc0int_st_reg_t; + +/** Type of slc0int_ena register + * ******* Description *********** + */ +typedef union { + struct { + /** slc_frhost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit0_int_ena:1; + /** slc_frhost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit1_int_ena:1; + /** slc_frhost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit2_int_ena:1; + /** slc_frhost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit3_int_ena:1; + /** slc_frhost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit4_int_ena:1; + /** slc_frhost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit5_int_ena:1; + /** slc_frhost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit6_int_ena:1; + /** slc_frhost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit7_int_ena:1; + /** slc0_rx_start_int_ena : R/W; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc0_rx_start_int_ena:1; + /** slc0_tx_start_int_ena : R/W; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc0_tx_start_int_ena:1; + /** slc0_rx_udf_int_ena : R/W; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc0_rx_udf_int_ena:1; + /** slc0_tx_ovf_int_ena : R/W; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc0_tx_ovf_int_ena:1; + /** slc0_token0_1to0_int_ena : R/W; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc0_token0_1to0_int_ena:1; + /** slc0_token1_1to0_int_ena : R/W; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc0_token1_1to0_int_ena:1; + /** slc0_tx_done_int_ena : R/W; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc0_tx_done_int_ena:1; + /** slc0_tx_suc_eof_int_ena : R/W; bitpos: [15]; default: 0; + * reserved + */ + uint32_t slc0_tx_suc_eof_int_ena:1; + /** slc0_rx_done_int_ena : R/W; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc0_rx_done_int_ena:1; + /** slc0_rx_eof_int_ena : R/W; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc0_rx_eof_int_ena:1; + /** slc0_tohost_int_ena : R/W; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc0_tohost_int_ena:1; + /** slc0_tx_dscr_err_int_ena : R/W; bitpos: [19]; default: 0; + * reserved + */ + uint32_t slc0_tx_dscr_err_int_ena:1; + /** slc0_rx_dscr_err_int_ena : R/W; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc0_rx_dscr_err_int_ena:1; + /** slc0_tx_dscr_empty_int_ena : R/W; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc0_tx_dscr_empty_int_ena:1; + /** slc0_host_rd_ack_int_ena : R/W; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc0_host_rd_ack_int_ena:1; + /** slc0_wr_retry_done_int_ena : R/W; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc0_wr_retry_done_int_ena:1; + /** slc0_tx_err_eof_int_ena : R/W; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc0_tx_err_eof_int_ena:1; + /** cmd_dtc_int_ena : R/W; bitpos: [25]; default: 0; + * reserved + */ + uint32_t cmd_dtc_int_ena:1; + /** slc0_rx_quick_eof_int_ena : R/W; bitpos: [26]; default: 0; + * reserved + */ + uint32_t slc0_rx_quick_eof_int_ena:1; + /** slc0_host_pop_eof_err_int_ena : R/W; bitpos: [27]; default: 0; + * reserved + */ + uint32_t slc0_host_pop_eof_err_int_ena:1; + /** hda_recv_done_int_ena : R/W; bitpos: [28]; default: 0; + * reserved + */ + uint32_t hda_recv_done_int_ena:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc0int_ena_reg_t; + +/** Type of slc0int_clr register + * ******* Description *********** + */ +typedef union { + struct { + /** slc_frhost_bit0_int_clr : WT; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit0_int_clr:1; + /** slc_frhost_bit1_int_clr : WT; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit1_int_clr:1; + /** slc_frhost_bit2_int_clr : WT; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit2_int_clr:1; + /** slc_frhost_bit3_int_clr : WT; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit3_int_clr:1; + /** slc_frhost_bit4_int_clr : WT; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit4_int_clr:1; + /** slc_frhost_bit5_int_clr : WT; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit5_int_clr:1; + /** slc_frhost_bit6_int_clr : WT; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit6_int_clr:1; + /** slc_frhost_bit7_int_clr : WT; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit7_int_clr:1; + /** slc0_rx_start_int_clr : WT; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc0_rx_start_int_clr:1; + /** slc0_tx_start_int_clr : WT; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc0_tx_start_int_clr:1; + /** slc0_rx_udf_int_clr : WT; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc0_rx_udf_int_clr:1; + /** slc0_tx_ovf_int_clr : WT; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc0_tx_ovf_int_clr:1; + /** slc0_token0_1to0_int_clr : WT; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc0_token0_1to0_int_clr:1; + /** slc0_token1_1to0_int_clr : WT; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc0_token1_1to0_int_clr:1; + /** slc0_tx_done_int_clr : WT; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc0_tx_done_int_clr:1; + /** slc0_tx_suc_eof_int_clr : WT; bitpos: [15]; default: 0; + * reserved + */ + uint32_t slc0_tx_suc_eof_int_clr:1; + /** slc0_rx_done_int_clr : WT; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc0_rx_done_int_clr:1; + /** slc0_rx_eof_int_clr : WT; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc0_rx_eof_int_clr:1; + /** slc0_tohost_int_clr : WT; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc0_tohost_int_clr:1; + /** slc0_tx_dscr_err_int_clr : WT; bitpos: [19]; default: 0; + * reserved + */ + uint32_t slc0_tx_dscr_err_int_clr:1; + /** slc0_rx_dscr_err_int_clr : WT; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc0_rx_dscr_err_int_clr:1; + /** slc0_tx_dscr_empty_int_clr : WT; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc0_tx_dscr_empty_int_clr:1; + /** slc0_host_rd_ack_int_clr : WT; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc0_host_rd_ack_int_clr:1; + /** slc0_wr_retry_done_int_clr : WT; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc0_wr_retry_done_int_clr:1; + /** slc0_tx_err_eof_int_clr : WT; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc0_tx_err_eof_int_clr:1; + /** cmd_dtc_int_clr : WT; bitpos: [25]; default: 0; + * reserved + */ + uint32_t cmd_dtc_int_clr:1; + /** slc0_rx_quick_eof_int_clr : WT; bitpos: [26]; default: 0; + * reserved + */ + uint32_t slc0_rx_quick_eof_int_clr:1; + /** slc0_host_pop_eof_err_int_clr : WT; bitpos: [27]; default: 0; + * reserved + */ + uint32_t slc0_host_pop_eof_err_int_clr:1; + /** hda_recv_done_int_clr : WT; bitpos: [28]; default: 0; + * reserved + */ + uint32_t hda_recv_done_int_clr:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc0int_clr_reg_t; + +/** Type of slc1int_raw register + * reserved + */ +typedef union { + struct { + /** slc_frhost_bit8_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit8_int_raw:1; + /** slc_frhost_bit9_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit9_int_raw:1; + /** slc_frhost_bit10_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit10_int_raw:1; + /** slc_frhost_bit11_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit11_int_raw:1; + /** slc_frhost_bit12_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit12_int_raw:1; + /** slc_frhost_bit13_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit13_int_raw:1; + /** slc_frhost_bit14_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit14_int_raw:1; + /** slc_frhost_bit15_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit15_int_raw:1; + /** slc1_rx_start_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc1_rx_start_int_raw:1; + /** slc1_tx_start_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc1_tx_start_int_raw:1; + /** slc1_rx_udf_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc1_rx_udf_int_raw:1; + /** slc1_tx_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc1_tx_ovf_int_raw:1; + /** slc1_token0_1to0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc1_token0_1to0_int_raw:1; + /** slc1_token1_1to0_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc1_token1_1to0_int_raw:1; + /** slc1_tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc1_tx_done_int_raw:1; + /** slc1_tx_suc_eof_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * reserved + */ + uint32_t slc1_tx_suc_eof_int_raw:1; + /** slc1_rx_done_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc1_rx_done_int_raw:1; + /** slc1_rx_eof_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc1_rx_eof_int_raw:1; + /** slc1_tohost_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc1_tohost_int_raw:1; + /** slc1_tx_dscr_err_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_err_int_raw:1; + /** slc1_rx_dscr_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc1_rx_dscr_err_int_raw:1; + /** slc1_tx_dscr_empty_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_empty_int_raw:1; + /** slc1_host_rd_ack_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc1_host_rd_ack_int_raw:1; + /** slc1_wr_retry_done_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc1_wr_retry_done_int_raw:1; + /** slc1_tx_err_eof_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc1_tx_err_eof_int_raw:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc1int_raw_reg_t; + +/** Type of slc1int_st register + * reserved + */ +typedef union { + struct { + /** slc_frhost_bit8_int_st : RO; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit8_int_st:1; + /** slc_frhost_bit9_int_st : RO; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit9_int_st:1; + /** slc_frhost_bit10_int_st : RO; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit10_int_st:1; + /** slc_frhost_bit11_int_st : RO; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit11_int_st:1; + /** slc_frhost_bit12_int_st : RO; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit12_int_st:1; + /** slc_frhost_bit13_int_st : RO; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit13_int_st:1; + /** slc_frhost_bit14_int_st : RO; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit14_int_st:1; + /** slc_frhost_bit15_int_st : RO; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit15_int_st:1; + /** slc1_rx_start_int_st : RO; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc1_rx_start_int_st:1; + /** slc1_tx_start_int_st : RO; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc1_tx_start_int_st:1; + /** slc1_rx_udf_int_st : RO; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc1_rx_udf_int_st:1; + /** slc1_tx_ovf_int_st : RO; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc1_tx_ovf_int_st:1; + /** slc1_token0_1to0_int_st : RO; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc1_token0_1to0_int_st:1; + /** slc1_token1_1to0_int_st : RO; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc1_token1_1to0_int_st:1; + /** slc1_tx_done_int_st : RO; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc1_tx_done_int_st:1; + /** slc1_tx_suc_eof_int_st : RO; bitpos: [15]; default: 0; + * reserved + */ + uint32_t slc1_tx_suc_eof_int_st:1; + /** slc1_rx_done_int_st : RO; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc1_rx_done_int_st:1; + /** slc1_rx_eof_int_st : RO; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc1_rx_eof_int_st:1; + /** slc1_tohost_int_st : RO; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc1_tohost_int_st:1; + /** slc1_tx_dscr_err_int_st : RO; bitpos: [19]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_err_int_st:1; + /** slc1_rx_dscr_err_int_st : RO; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc1_rx_dscr_err_int_st:1; + /** slc1_tx_dscr_empty_int_st : RO; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_empty_int_st:1; + /** slc1_host_rd_ack_int_st : RO; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc1_host_rd_ack_int_st:1; + /** slc1_wr_retry_done_int_st : RO; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc1_wr_retry_done_int_st:1; + /** slc1_tx_err_eof_int_st : RO; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc1_tx_err_eof_int_st:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc1int_st_reg_t; + +/** Type of slc1int_ena register + * reserved + */ +typedef union { + struct { + /** slc_frhost_bit8_int_ena : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit8_int_ena:1; + /** slc_frhost_bit9_int_ena : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit9_int_ena:1; + /** slc_frhost_bit10_int_ena : R/W; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit10_int_ena:1; + /** slc_frhost_bit11_int_ena : R/W; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit11_int_ena:1; + /** slc_frhost_bit12_int_ena : R/W; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit12_int_ena:1; + /** slc_frhost_bit13_int_ena : R/W; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit13_int_ena:1; + /** slc_frhost_bit14_int_ena : R/W; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit14_int_ena:1; + /** slc_frhost_bit15_int_ena : R/W; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit15_int_ena:1; + /** slc1_rx_start_int_ena : R/W; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc1_rx_start_int_ena:1; + /** slc1_tx_start_int_ena : R/W; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc1_tx_start_int_ena:1; + /** slc1_rx_udf_int_ena : R/W; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc1_rx_udf_int_ena:1; + /** slc1_tx_ovf_int_ena : R/W; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc1_tx_ovf_int_ena:1; + /** slc1_token0_1to0_int_ena : R/W; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc1_token0_1to0_int_ena:1; + /** slc1_token1_1to0_int_ena : R/W; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc1_token1_1to0_int_ena:1; + /** slc1_tx_done_int_ena : R/W; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc1_tx_done_int_ena:1; + /** slc1_tx_suc_eof_int_ena : R/W; bitpos: [15]; default: 0; + * reserved + */ + uint32_t slc1_tx_suc_eof_int_ena:1; + /** slc1_rx_done_int_ena : R/W; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc1_rx_done_int_ena:1; + /** slc1_rx_eof_int_ena : R/W; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc1_rx_eof_int_ena:1; + /** slc1_tohost_int_ena : R/W; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc1_tohost_int_ena:1; + /** slc1_tx_dscr_err_int_ena : R/W; bitpos: [19]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_err_int_ena:1; + /** slc1_rx_dscr_err_int_ena : R/W; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc1_rx_dscr_err_int_ena:1; + /** slc1_tx_dscr_empty_int_ena : R/W; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_empty_int_ena:1; + /** slc1_host_rd_ack_int_ena : R/W; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc1_host_rd_ack_int_ena:1; + /** slc1_wr_retry_done_int_ena : R/W; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc1_wr_retry_done_int_ena:1; + /** slc1_tx_err_eof_int_ena : R/W; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc1_tx_err_eof_int_ena:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc1int_ena_reg_t; + +/** Type of slc1int_clr register + * reserved + */ +typedef union { + struct { + /** slc_frhost_bit8_int_clr : WT; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit8_int_clr:1; + /** slc_frhost_bit9_int_clr : WT; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit9_int_clr:1; + /** slc_frhost_bit10_int_clr : WT; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit10_int_clr:1; + /** slc_frhost_bit11_int_clr : WT; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit11_int_clr:1; + /** slc_frhost_bit12_int_clr : WT; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit12_int_clr:1; + /** slc_frhost_bit13_int_clr : WT; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit13_int_clr:1; + /** slc_frhost_bit14_int_clr : WT; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit14_int_clr:1; + /** slc_frhost_bit15_int_clr : WT; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit15_int_clr:1; + /** slc1_rx_start_int_clr : WT; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc1_rx_start_int_clr:1; + /** slc1_tx_start_int_clr : WT; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc1_tx_start_int_clr:1; + /** slc1_rx_udf_int_clr : WT; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc1_rx_udf_int_clr:1; + /** slc1_tx_ovf_int_clr : WT; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc1_tx_ovf_int_clr:1; + /** slc1_token0_1to0_int_clr : WT; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc1_token0_1to0_int_clr:1; + /** slc1_token1_1to0_int_clr : WT; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc1_token1_1to0_int_clr:1; + /** slc1_tx_done_int_clr : WT; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc1_tx_done_int_clr:1; + /** slc1_tx_suc_eof_int_clr : WT; bitpos: [15]; default: 0; + * reserved + */ + uint32_t slc1_tx_suc_eof_int_clr:1; + /** slc1_rx_done_int_clr : WT; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc1_rx_done_int_clr:1; + /** slc1_rx_eof_int_clr : WT; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc1_rx_eof_int_clr:1; + /** slc1_tohost_int_clr : WT; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc1_tohost_int_clr:1; + /** slc1_tx_dscr_err_int_clr : WT; bitpos: [19]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_err_int_clr:1; + /** slc1_rx_dscr_err_int_clr : WT; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc1_rx_dscr_err_int_clr:1; + /** slc1_tx_dscr_empty_int_clr : WT; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_empty_int_clr:1; + /** slc1_host_rd_ack_int_clr : WT; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc1_host_rd_ack_int_clr:1; + /** slc1_wr_retry_done_int_clr : WT; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc1_wr_retry_done_int_clr:1; + /** slc1_tx_err_eof_int_clr : WT; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc1_tx_err_eof_int_clr:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc1int_clr_reg_t; + +/** Type of slc0int_st1 register + * reserved + */ +typedef union { + struct { + /** slc_frhost_bit0_int_st1 : RO; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit0_int_st1:1; + /** slc_frhost_bit1_int_st1 : RO; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit1_int_st1:1; + /** slc_frhost_bit2_int_st1 : RO; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit2_int_st1:1; + /** slc_frhost_bit3_int_st1 : RO; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit3_int_st1:1; + /** slc_frhost_bit4_int_st1 : RO; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit4_int_st1:1; + /** slc_frhost_bit5_int_st1 : RO; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit5_int_st1:1; + /** slc_frhost_bit6_int_st1 : RO; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit6_int_st1:1; + /** slc_frhost_bit7_int_st1 : RO; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit7_int_st1:1; + /** slc0_rx_start_int_st1 : RO; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc0_rx_start_int_st1:1; + /** slc0_tx_start_int_st1 : RO; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc0_tx_start_int_st1:1; + /** slc0_rx_udf_int_st1 : RO; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc0_rx_udf_int_st1:1; + /** slc0_tx_ovf_int_st1 : RO; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc0_tx_ovf_int_st1:1; + /** slc0_token0_1to0_int_st1 : RO; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc0_token0_1to0_int_st1:1; + /** slc0_token1_1to0_int_st1 : RO; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc0_token1_1to0_int_st1:1; + /** slc0_tx_done_int_st1 : RO; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc0_tx_done_int_st1:1; + /** slc0_tx_suc_eof_int_st1 : RO; bitpos: [15]; default: 0; + * reserved + */ + uint32_t slc0_tx_suc_eof_int_st1:1; + /** slc0_rx_done_int_st1 : RO; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc0_rx_done_int_st1:1; + /** slc0_rx_eof_int_st1 : RO; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc0_rx_eof_int_st1:1; + /** slc0_tohost_int_st1 : RO; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc0_tohost_int_st1:1; + /** slc0_tx_dscr_err_int_st1 : RO; bitpos: [19]; default: 0; + * reserved + */ + uint32_t slc0_tx_dscr_err_int_st1:1; + /** slc0_rx_dscr_err_int_st1 : RO; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc0_rx_dscr_err_int_st1:1; + /** slc0_tx_dscr_empty_int_st1 : RO; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc0_tx_dscr_empty_int_st1:1; + /** slc0_host_rd_ack_int_st1 : RO; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc0_host_rd_ack_int_st1:1; + /** slc0_wr_retry_done_int_st1 : RO; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc0_wr_retry_done_int_st1:1; + /** slc0_tx_err_eof_int_st1 : RO; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc0_tx_err_eof_int_st1:1; + /** cmd_dtc_int_st1 : RO; bitpos: [25]; default: 0; + * reserved + */ + uint32_t cmd_dtc_int_st1:1; + /** slc0_rx_quick_eof_int_st1 : RO; bitpos: [26]; default: 0; + * reserved + */ + uint32_t slc0_rx_quick_eof_int_st1:1; + /** slc0_host_pop_eof_err_int_st1 : RO; bitpos: [27]; default: 0; + * reserved + */ + uint32_t slc0_host_pop_eof_err_int_st1:1; + /** hda_recv_done_int_st1 : RO; bitpos: [28]; default: 0; + * reserved + */ + uint32_t hda_recv_done_int_st1:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc0int_st1_reg_t; + +/** Type of slc0int_ena1 register + * reserved + */ +typedef union { + struct { + /** slc_frhost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit0_int_ena1:1; + /** slc_frhost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit1_int_ena1:1; + /** slc_frhost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit2_int_ena1:1; + /** slc_frhost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit3_int_ena1:1; + /** slc_frhost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit4_int_ena1:1; + /** slc_frhost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit5_int_ena1:1; + /** slc_frhost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit6_int_ena1:1; + /** slc_frhost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit7_int_ena1:1; + /** slc0_rx_start_int_ena1 : R/W; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc0_rx_start_int_ena1:1; + /** slc0_tx_start_int_ena1 : R/W; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc0_tx_start_int_ena1:1; + /** slc0_rx_udf_int_ena1 : R/W; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc0_rx_udf_int_ena1:1; + /** slc0_tx_ovf_int_ena1 : R/W; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc0_tx_ovf_int_ena1:1; + /** slc0_token0_1to0_int_ena1 : R/W; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc0_token0_1to0_int_ena1:1; + /** slc0_token1_1to0_int_ena1 : R/W; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc0_token1_1to0_int_ena1:1; + /** slc0_tx_done_int_ena1 : R/W; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc0_tx_done_int_ena1:1; + /** slc0_tx_suc_eof_int_ena1 : R/W; bitpos: [15]; default: 0; + * reserved + */ + uint32_t slc0_tx_suc_eof_int_ena1:1; + /** slc0_rx_done_int_ena1 : R/W; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc0_rx_done_int_ena1:1; + /** slc0_rx_eof_int_ena1 : R/W; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc0_rx_eof_int_ena1:1; + /** slc0_tohost_int_ena1 : R/W; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc0_tohost_int_ena1:1; + /** slc0_tx_dscr_err_int_ena1 : R/W; bitpos: [19]; default: 0; + * reserved + */ + uint32_t slc0_tx_dscr_err_int_ena1:1; + /** slc0_rx_dscr_err_int_ena1 : R/W; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc0_rx_dscr_err_int_ena1:1; + /** slc0_tx_dscr_empty_int_ena1 : R/W; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc0_tx_dscr_empty_int_ena1:1; + /** slc0_host_rd_ack_int_ena1 : R/W; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc0_host_rd_ack_int_ena1:1; + /** slc0_wr_retry_done_int_ena1 : R/W; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc0_wr_retry_done_int_ena1:1; + /** slc0_tx_err_eof_int_ena1 : R/W; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc0_tx_err_eof_int_ena1:1; + /** cmd_dtc_int_ena1 : R/W; bitpos: [25]; default: 0; + * reserved + */ + uint32_t cmd_dtc_int_ena1:1; + /** slc0_rx_quick_eof_int_ena1 : R/W; bitpos: [26]; default: 0; + * reserved + */ + uint32_t slc0_rx_quick_eof_int_ena1:1; + /** slc0_host_pop_eof_err_int_ena1 : R/W; bitpos: [27]; default: 0; + * reserved + */ + uint32_t slc0_host_pop_eof_err_int_ena1:1; + /** hda_recv_done_int_ena1 : R/W; bitpos: [28]; default: 0; + * reserved + */ + uint32_t hda_recv_done_int_ena1:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc0int_ena1_reg_t; + +/** Type of slc1int_st1 register + * reserved + */ +typedef union { + struct { + /** slc_frhost_bit8_int_st1 : RO; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit8_int_st1:1; + /** slc_frhost_bit9_int_st1 : RO; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit9_int_st1:1; + /** slc_frhost_bit10_int_st1 : RO; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit10_int_st1:1; + /** slc_frhost_bit11_int_st1 : RO; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit11_int_st1:1; + /** slc_frhost_bit12_int_st1 : RO; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit12_int_st1:1; + /** slc_frhost_bit13_int_st1 : RO; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit13_int_st1:1; + /** slc_frhost_bit14_int_st1 : RO; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit14_int_st1:1; + /** slc_frhost_bit15_int_st1 : RO; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit15_int_st1:1; + /** slc1_rx_start_int_st1 : RO; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc1_rx_start_int_st1:1; + /** slc1_tx_start_int_st1 : RO; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc1_tx_start_int_st1:1; + /** slc1_rx_udf_int_st1 : RO; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc1_rx_udf_int_st1:1; + /** slc1_tx_ovf_int_st1 : RO; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc1_tx_ovf_int_st1:1; + /** slc1_token0_1to0_int_st1 : RO; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc1_token0_1to0_int_st1:1; + /** slc1_token1_1to0_int_st1 : RO; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc1_token1_1to0_int_st1:1; + /** slc1_tx_done_int_st1 : RO; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc1_tx_done_int_st1:1; + /** slc1_tx_suc_eof_int_st1 : RO; bitpos: [15]; default: 0; + * reserved + */ + uint32_t slc1_tx_suc_eof_int_st1:1; + /** slc1_rx_done_int_st1 : RO; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc1_rx_done_int_st1:1; + /** slc1_rx_eof_int_st1 : RO; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc1_rx_eof_int_st1:1; + /** slc1_tohost_int_st1 : RO; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc1_tohost_int_st1:1; + /** slc1_tx_dscr_err_int_st1 : RO; bitpos: [19]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_err_int_st1:1; + /** slc1_rx_dscr_err_int_st1 : RO; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc1_rx_dscr_err_int_st1:1; + /** slc1_tx_dscr_empty_int_st1 : RO; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_empty_int_st1:1; + /** slc1_host_rd_ack_int_st1 : RO; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc1_host_rd_ack_int_st1:1; + /** slc1_wr_retry_done_int_st1 : RO; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc1_wr_retry_done_int_st1:1; + /** slc1_tx_err_eof_int_st1 : RO; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc1_tx_err_eof_int_st1:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc1int_st1_reg_t; + +/** Type of slc1int_ena1 register + * reserved + */ +typedef union { + struct { + /** slc_frhost_bit8_int_ena1 : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit8_int_ena1:1; + /** slc_frhost_bit9_int_ena1 : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit9_int_ena1:1; + /** slc_frhost_bit10_int_ena1 : R/W; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit10_int_ena1:1; + /** slc_frhost_bit11_int_ena1 : R/W; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit11_int_ena1:1; + /** slc_frhost_bit12_int_ena1 : R/W; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit12_int_ena1:1; + /** slc_frhost_bit13_int_ena1 : R/W; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit13_int_ena1:1; + /** slc_frhost_bit14_int_ena1 : R/W; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit14_int_ena1:1; + /** slc_frhost_bit15_int_ena1 : R/W; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit15_int_ena1:1; + /** slc1_rx_start_int_ena1 : R/W; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc1_rx_start_int_ena1:1; + /** slc1_tx_start_int_ena1 : R/W; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc1_tx_start_int_ena1:1; + /** slc1_rx_udf_int_ena1 : R/W; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc1_rx_udf_int_ena1:1; + /** slc1_tx_ovf_int_ena1 : R/W; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc1_tx_ovf_int_ena1:1; + /** slc1_token0_1to0_int_ena1 : R/W; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc1_token0_1to0_int_ena1:1; + /** slc1_token1_1to0_int_ena1 : R/W; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc1_token1_1to0_int_ena1:1; + /** slc1_tx_done_int_ena1 : R/W; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc1_tx_done_int_ena1:1; + /** slc1_tx_suc_eof_int_ena1 : R/W; bitpos: [15]; default: 0; + * reserved + */ + uint32_t slc1_tx_suc_eof_int_ena1:1; + /** slc1_rx_done_int_ena1 : R/W; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc1_rx_done_int_ena1:1; + /** slc1_rx_eof_int_ena1 : R/W; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc1_rx_eof_int_ena1:1; + /** slc1_tohost_int_ena1 : R/W; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc1_tohost_int_ena1:1; + /** slc1_tx_dscr_err_int_ena1 : R/W; bitpos: [19]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_err_int_ena1:1; + /** slc1_rx_dscr_err_int_ena1 : R/W; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc1_rx_dscr_err_int_ena1:1; + /** slc1_tx_dscr_empty_int_ena1 : R/W; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_empty_int_ena1:1; + /** slc1_host_rd_ack_int_ena1 : R/W; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc1_host_rd_ack_int_ena1:1; + /** slc1_wr_retry_done_int_ena1 : R/W; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc1_wr_retry_done_int_ena1:1; + /** slc1_tx_err_eof_int_ena1 : R/W; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc1_tx_err_eof_int_ena1:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc1int_ena1_reg_t; + + +/** Group: Status registers */ +/** Type of slcrx_status register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_rx_full : RO; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc0_rx_full:1; + /** slc0_rx_empty : RO; bitpos: [1]; default: 1; + * reserved + */ + uint32_t slc0_rx_empty:1; + /** slc0_rx_buf_len : RO; bitpos: [15:2]; default: 0; + * the current buffer length when slc0 reads data from rx link + */ + uint32_t slc0_rx_buf_len:14; + /** slc1_rx_full : RO; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc1_rx_full:1; + /** slc1_rx_empty : RO; bitpos: [17]; default: 1; + * reserved + */ + uint32_t slc1_rx_empty:1; + /** slc1_rx_buf_len : RO; bitpos: [31:18]; default: 0; + * the current buffer length when slc1 reads data from rx link + */ + uint32_t slc1_rx_buf_len:14; + }; + uint32_t val; +} sdio_slcrx_status_reg_t; + +/** Type of slctx_status register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_tx_full : RO; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc0_tx_full:1; + /** slc0_tx_empty : RO; bitpos: [1]; default: 1; + * reserved + */ + uint32_t slc0_tx_empty:1; + uint32_t reserved_2:14; + /** slc1_tx_full : RO; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc1_tx_full:1; + /** slc1_tx_empty : RO; bitpos: [17]; default: 1; + * reserved + */ + uint32_t slc1_tx_empty:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} sdio_slctx_status_reg_t; + +/** Type of slc0_state0 register + * reserved + */ +typedef union { + struct { + /** slc0_state0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_state0:32; + }; + uint32_t val; +} sdio_slc0_state0_reg_t; + +/** Type of slc0_state1 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_state1 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21] + * rx_link fsm state, [30:24] rx_fifo_cnt + */ + uint32_t slc0_state1:32; + }; + uint32_t val; +} sdio_slc0_state1_reg_t; + +/** Type of slc1_state0 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc1_state0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_state0:32; + }; + uint32_t val; +} sdio_slc1_state0_reg_t; + +/** Type of slc1_state1 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc1_state1 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21] + * rx_link fsm state, [30:24] rx_fifo_cnt + */ + uint32_t slc1_state1:32; + }; + uint32_t val; +} sdio_slc1_state1_reg_t; + +/** Type of slc_sdio_st register + * reserved + */ +typedef union { + struct { + /** cmd_st : RO; bitpos: [2:0]; default: 0; + * reserved + */ + uint32_t cmd_st:3; + uint32_t reserved_3:1; + /** func_st : RO; bitpos: [7:4]; default: 0; + * reserved + */ + uint32_t func_st:4; + /** sdio_wakeup : RO; bitpos: [8]; default: 0; + * reserved + */ + uint32_t sdio_wakeup:1; + uint32_t reserved_9:3; + /** bus_st : RO; bitpos: [14:12]; default: 0; + * reserved + */ + uint32_t bus_st:3; + uint32_t reserved_15:1; + /** func1_acc_state : RO; bitpos: [20:16]; default: 0; + * reserved + */ + uint32_t func1_acc_state:5; + uint32_t reserved_21:3; + /** func2_acc_state : RO; bitpos: [28:24]; default: 0; + * reserved + */ + uint32_t func2_acc_state:5; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc_sdio_st_reg_t; + +/** Type of slc0_txlink_dscr register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_txlink_dscr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_txlink_dscr:32; + }; + uint32_t val; +} sdio_slc0_txlink_dscr_reg_t; + +/** Type of slc0_txlink_dscr_bf0 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_txlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_txlink_dscr_bf0:32; + }; + uint32_t val; +} sdio_slc0_txlink_dscr_bf0_reg_t; + +/** Type of slc0_txlink_dscr_bf1 register + * reserved + */ +typedef union { + struct { + /** slc0_txlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_txlink_dscr_bf1:32; + }; + uint32_t val; +} sdio_slc0_txlink_dscr_bf1_reg_t; + +/** Type of slc0_rxlink_dscr register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_rxlink_dscr : RO; bitpos: [31:0]; default: 0; + * the third word of slc0 link descriptor, or known as the next descriptor address + */ + uint32_t slc0_rxlink_dscr:32; + }; + uint32_t val; +} sdio_slc0_rxlink_dscr_reg_t; + +/** Type of slc0_rxlink_dscr_bf0 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_rxlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_rxlink_dscr_bf0:32; + }; + uint32_t val; +} sdio_slc0_rxlink_dscr_bf0_reg_t; + +/** Type of slc0_rxlink_dscr_bf1 register + * reserved + */ +typedef union { + struct { + /** slc0_rxlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_rxlink_dscr_bf1:32; + }; + uint32_t val; +} sdio_slc0_rxlink_dscr_bf1_reg_t; + +/** Type of slc1_txlink_dscr register + * reserved + */ +typedef union { + struct { + /** slc1_txlink_dscr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_txlink_dscr:32; + }; + uint32_t val; +} sdio_slc1_txlink_dscr_reg_t; + +/** Type of slc1_txlink_dscr_bf0 register + * reserved + */ +typedef union { + struct { + /** slc1_txlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_txlink_dscr_bf0:32; + }; + uint32_t val; +} sdio_slc1_txlink_dscr_bf0_reg_t; + +/** Type of slc1_txlink_dscr_bf1 register + * reserved + */ +typedef union { + struct { + /** slc1_txlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_txlink_dscr_bf1:32; + }; + uint32_t val; +} sdio_slc1_txlink_dscr_bf1_reg_t; + +/** Type of slc1_rxlink_dscr register + * ******* Description *********** + */ +typedef union { + struct { + /** slc1_rxlink_dscr : RO; bitpos: [31:0]; default: 0; + * the third word of slc1 link descriptor, or known as the next descriptor address + */ + uint32_t slc1_rxlink_dscr:32; + }; + uint32_t val; +} sdio_slc1_rxlink_dscr_reg_t; + +/** Type of slc1_rxlink_dscr_bf0 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc1_rxlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_rxlink_dscr_bf0:32; + }; + uint32_t val; +} sdio_slc1_rxlink_dscr_bf0_reg_t; + +/** Type of slc1_rxlink_dscr_bf1 register + * reserved + */ +typedef union { + struct { + /** slc1_rxlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_rxlink_dscr_bf1:32; + }; + uint32_t val; +} sdio_slc1_rxlink_dscr_bf1_reg_t; + +/** Type of slc0_tx_erreof_des_addr register + * reserved + */ +typedef union { + struct { + /** slc0_tx_err_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_tx_err_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc0_tx_erreof_des_addr_reg_t; + +/** Type of slc1_tx_erreof_des_addr register + * reserved + */ +typedef union { + struct { + /** slc1_tx_err_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_tx_err_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc1_tx_erreof_des_addr_reg_t; + +/** Type of slc_token_lat register + * reserved + */ +typedef union { + struct { + /** slc0_token : RO; bitpos: [11:0]; default: 0; + * reserved + */ + uint32_t slc0_token:12; + uint32_t reserved_12:4; + /** slc1_token : RO; bitpos: [27:16]; default: 0; + * reserved + */ + uint32_t slc1_token:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_token_lat_reg_t; + +/** Type of slc_cmd_infor0 register + * reserved + */ +typedef union { + struct { + /** cmd_content0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t cmd_content0:32; + }; + uint32_t val; +} sdio_slc_cmd_infor0_reg_t; + +/** Type of slc_cmd_infor1 register + * reserved + */ +typedef union { + struct { + /** cmd_content1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t cmd_content1:32; + }; + uint32_t val; +} sdio_slc_cmd_infor1_reg_t; + +/** Type of slc0_length register + * reserved + */ +typedef union { + struct { + /** slc0_len : RO; bitpos: [19:0]; default: 0; + * reserved + */ + uint32_t slc0_len:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} sdio_slc0_length_reg_t; + +/** Type of slc_sdio_crc_st0 register + * reserved + */ +typedef union { + struct { + /** dat0_crc_err_cnt : RO; bitpos: [7:0]; default: 0; + * reserved + */ + uint32_t dat0_crc_err_cnt:8; + /** dat1_crc_err_cnt : RO; bitpos: [15:8]; default: 0; + * reserved + */ + uint32_t dat1_crc_err_cnt:8; + /** dat2_crc_err_cnt : RO; bitpos: [23:16]; default: 0; + * reserved + */ + uint32_t dat2_crc_err_cnt:8; + /** dat3_crc_err_cnt : RO; bitpos: [31:24]; default: 0; + * reserved + */ + uint32_t dat3_crc_err_cnt:8; + }; + uint32_t val; +} sdio_slc_sdio_crc_st0_reg_t; + +/** Type of slc0_eof_start_des register + * reserved + */ +typedef union { + struct { + /** slc0_eof_start_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_eof_start_des_addr:32; + }; + uint32_t val; +} sdio_slc0_eof_start_des_reg_t; + +/** Type of slc0_push_dscr_addr register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_rx_push_dscr_addr : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 gets a link descriptor, aligned with word + */ + uint32_t slc0_rx_push_dscr_addr:32; + }; + uint32_t val; +} sdio_slc0_push_dscr_addr_reg_t; + +/** Type of slc0_done_dscr_addr register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_rx_done_dscr_addr : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 finishes reading data from one buffer, + * aligned with word + */ + uint32_t slc0_rx_done_dscr_addr:32; + }; + uint32_t val; +} sdio_slc0_done_dscr_addr_reg_t; + +/** Type of slc0_sub_start_des register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_sub_pac_start_dscr_addr : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 gets a link descriptor, aligned with word + */ + uint32_t slc0_sub_pac_start_dscr_addr:32; + }; + uint32_t val; +} sdio_slc0_sub_start_des_reg_t; + +/** Type of slc0_dscr_cnt register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_rx_dscr_cnt_lat : RO; bitpos: [9:0]; default: 0; + * the number of descriptors got by slc0 when it tries to read data from memory + */ + uint32_t slc0_rx_dscr_cnt_lat:10; + uint32_t reserved_10:6; + /** slc0_rx_get_eof_occ : RO; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc0_rx_get_eof_occ:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc0_dscr_cnt_reg_t; + + +/** Group: Debud registers */ +/** Type of slc0txfifo_pop register + * reserved + */ +typedef union { + struct { + /** slc0_txfifo_rdata : RO; bitpos: [10:0]; default: 1024; + * reserved + */ + uint32_t slc0_txfifo_rdata:11; + uint32_t reserved_11:5; + /** slc0_txfifo_pop : R/W/SC; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc0_txfifo_pop:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc0txfifo_pop_reg_t; + +/** Type of slc1txfifo_pop register + * reserved + */ +typedef union { + struct { + /** slc1_txfifo_rdata : RO; bitpos: [10:0]; default: 1024; + * reserved + */ + uint32_t slc1_txfifo_rdata:11; + uint32_t reserved_11:5; + /** slc1_txfifo_pop : R/W/SC; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc1_txfifo_pop:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc1txfifo_pop_reg_t; + +/** Type of slc_ahb_test register + * reserved + */ +typedef union { + struct { + /** slc_ahb_testmode : R/W; bitpos: [2:0]; default: 0; + * reserved + */ + uint32_t slc_ahb_testmode:3; + uint32_t reserved_3:1; + /** slc_ahb_testaddr : R/W; bitpos: [5:4]; default: 0; + * reserved + */ + uint32_t slc_ahb_testaddr:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} sdio_slc_ahb_test_reg_t; + + +/** Group: Version registers */ +/** Type of slcdate register + * ******* Description *********** + */ +typedef union { + struct { + /** slc_date : R/W; bitpos: [31:0]; default: 554182400; + * reserved + */ + uint32_t slc_date:32; + }; + uint32_t val; +} sdio_slcdate_reg_t; + + +typedef struct slc_dev_t { + volatile sdio_slcconf0_reg_t slcconf0; + volatile sdio_slc0int_raw_reg_t slc0int_raw; + volatile sdio_slc0int_st_reg_t slc0int_st; + volatile sdio_slc0int_ena_reg_t slc0int_ena; + volatile sdio_slc0int_clr_reg_t slc0int_clr; + volatile sdio_slc1int_raw_reg_t slc1int_raw; + volatile sdio_slc1int_st_reg_t slc1int_st; + volatile sdio_slc1int_ena_reg_t slc1int_ena; + volatile sdio_slc1int_clr_reg_t slc1int_clr; + volatile sdio_slcrx_status_reg_t slcrx_status; + volatile sdio_slc0rxfifo_push_reg_t slc0rxfifo_push; + volatile sdio_slc1rxfifo_push_reg_t slc1rxfifo_push; + volatile sdio_slctx_status_reg_t slctx_status; + volatile sdio_slc0txfifo_pop_reg_t slc0txfifo_pop; + volatile sdio_slc1txfifo_pop_reg_t slc1txfifo_pop; + volatile sdio_slc0rx_link_reg_t slc0rx_link; + volatile sdio_slc0rx_link_addr_reg_t slc0rx_link_addr; + volatile sdio_slc0tx_link_reg_t slc0tx_link; + volatile sdio_slc0tx_link_addr_reg_t slc0tx_link_addr; + volatile sdio_slc1rx_link_reg_t slc1rx_link; + volatile sdio_slc1rx_link_addr_reg_t slc1rx_link_addr; + volatile sdio_slc1tx_link_reg_t slc1tx_link; + volatile sdio_slc1tx_link_addr_reg_t slc1tx_link_addr; + volatile sdio_slcintvec_tohost_reg_t slcintvec_tohost; + volatile sdio_slc0token0_reg_t slc0token0; + volatile sdio_slc0token1_reg_t slc0token1; + volatile sdio_slc1token0_reg_t slc1token0; + volatile sdio_slc1token1_reg_t slc1token1; + volatile sdio_slcconf1_reg_t slcconf1; + volatile sdio_slc0_state0_reg_t slc0_state0; + volatile sdio_slc0_state1_reg_t slc0_state1; + volatile sdio_slc1_state0_reg_t slc1_state0; + volatile sdio_slc1_state1_reg_t slc1_state1; + volatile sdio_slcbridge_conf_reg_t slcbridge_conf; + volatile sdio_slc0_to_eof_des_addr_reg_t slc0_to_eof_des_addr; + volatile sdio_slc0_tx_eof_des_addr_reg_t slc0_tx_eof_des_addr; + volatile sdio_slc0_to_eof_bfr_des_addr_reg_t slc0_to_eof_bfr_des_addr; + volatile sdio_slc1_to_eof_des_addr_reg_t slc1_to_eof_des_addr; + volatile sdio_slc1_tx_eof_des_addr_reg_t slc1_tx_eof_des_addr; + volatile sdio_slc1_to_eof_bfr_des_addr_reg_t slc1_to_eof_bfr_des_addr; + volatile sdio_slc_ahb_test_reg_t slc_ahb_test; + volatile sdio_slc_sdio_st_reg_t slc_sdio_st; + volatile sdio_slc_rx_dscr_conf_reg_t slc_rx_dscr_conf; + volatile sdio_slc0_txlink_dscr_reg_t slc0_txlink_dscr; + volatile sdio_slc0_txlink_dscr_bf0_reg_t slc0_txlink_dscr_bf0; + volatile sdio_slc0_txlink_dscr_bf1_reg_t slc0_txlink_dscr_bf1; + volatile sdio_slc0_rxlink_dscr_reg_t slc0_rxlink_dscr; + volatile sdio_slc0_rxlink_dscr_bf0_reg_t slc0_rxlink_dscr_bf0; + volatile sdio_slc0_rxlink_dscr_bf1_reg_t slc0_rxlink_dscr_bf1; + volatile sdio_slc1_txlink_dscr_reg_t slc1_txlink_dscr; + volatile sdio_slc1_txlink_dscr_bf0_reg_t slc1_txlink_dscr_bf0; + volatile sdio_slc1_txlink_dscr_bf1_reg_t slc1_txlink_dscr_bf1; + volatile sdio_slc1_rxlink_dscr_reg_t slc1_rxlink_dscr; + volatile sdio_slc1_rxlink_dscr_bf0_reg_t slc1_rxlink_dscr_bf0; + volatile sdio_slc1_rxlink_dscr_bf1_reg_t slc1_rxlink_dscr_bf1; + volatile sdio_slc0_tx_erreof_des_addr_reg_t slc0_tx_erreof_des_addr; + volatile sdio_slc1_tx_erreof_des_addr_reg_t slc1_tx_erreof_des_addr; + volatile sdio_slc_token_lat_reg_t slc_token_lat; + volatile sdio_slc_tx_dscr_conf_reg_t slc_tx_dscr_conf; + volatile sdio_slc_cmd_infor0_reg_t slc_cmd_infor0; + volatile sdio_slc_cmd_infor1_reg_t slc_cmd_infor1; + volatile sdio_slc0_len_conf_reg_t slc0_len_conf; + volatile sdio_slc0_length_reg_t slc0_length; + volatile sdio_slc0_txpkt_h_dscr_reg_t slc0_txpkt_h_dscr; + volatile sdio_slc0_txpkt_e_dscr_reg_t slc0_txpkt_e_dscr; + volatile sdio_slc0_rxpkt_h_dscr_reg_t slc0_rxpkt_h_dscr; + volatile sdio_slc0_rxpkt_e_dscr_reg_t slc0_rxpkt_e_dscr; + volatile sdio_slc0_txpktu_h_dscr_reg_t slc0_txpktu_h_dscr; + volatile sdio_slc0_txpktu_e_dscr_reg_t slc0_txpktu_e_dscr; + volatile sdio_slc0_rxpktu_h_dscr_reg_t slc0_rxpktu_h_dscr; + volatile sdio_slc0_rxpktu_e_dscr_reg_t slc0_rxpktu_e_dscr; + volatile sdio_slc_seq_position_reg_t slc_seq_position; + volatile sdio_slc0_dscr_rec_conf_reg_t slc0_dscr_rec_conf; + volatile sdio_slc_sdio_crc_st0_reg_t slc_sdio_crc_st0; + volatile sdio_slc_sdio_crc_st1_reg_t slc_sdio_crc_st1; + volatile sdio_slc0_eof_start_des_reg_t slc0_eof_start_des; + volatile sdio_slc0_push_dscr_addr_reg_t slc0_push_dscr_addr; + volatile sdio_slc0_done_dscr_addr_reg_t slc0_done_dscr_addr; + volatile sdio_slc0_sub_start_des_reg_t slc0_sub_start_des; + volatile sdio_slc0_dscr_cnt_reg_t slc0_dscr_cnt; + volatile sdio_slc0_len_lim_conf_reg_t slc0_len_lim_conf; + volatile sdio_slc0int_st1_reg_t slc0int_st1; + volatile sdio_slc0int_ena1_reg_t slc0int_ena1; + volatile sdio_slc1int_st1_reg_t slc1int_st1; + volatile sdio_slc1int_ena1_reg_t slc1int_ena1; + volatile sdio_slc0_tx_sharemem_start_reg_t slc0_tx_sharemem_start; + volatile sdio_slc0_tx_sharemem_end_reg_t slc0_tx_sharemem_end; + volatile sdio_slc0_rx_sharemem_start_reg_t slc0_rx_sharemem_start; + volatile sdio_slc0_rx_sharemem_end_reg_t slc0_rx_sharemem_end; + volatile sdio_slc1_tx_sharemem_start_reg_t slc1_tx_sharemem_start; + volatile sdio_slc1_tx_sharemem_end_reg_t slc1_tx_sharemem_end; + volatile sdio_slc1_rx_sharemem_start_reg_t slc1_rx_sharemem_start; + volatile sdio_slc1_rx_sharemem_end_reg_t slc1_rx_sharemem_end; + volatile sdio_hda_tx_sharemem_start_reg_t hda_tx_sharemem_start; + volatile sdio_hda_rx_sharemem_start_reg_t hda_rx_sharemem_start; + volatile sdio_slc_burst_len_reg_t slc_burst_len; + uint32_t reserved_180[30]; + volatile sdio_slcdate_reg_t slcdate; + volatile sdio_slcid_reg_t slcid; +} slc_dev_t; + +extern slc_dev_t SLC; + +#ifndef __cplusplus +_Static_assert(sizeof(slc_dev_t) == 0x200, "Invalid size of slc_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/soc.h b/components/soc/esp32c6/include/soc/soc.h new file mode 100644 index 0000000000..03aea5fb27 --- /dev/null +++ b/components/soc/esp32c6/include/soc/soc.h @@ -0,0 +1,246 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifndef __ASSEMBLER__ +#include +#include "esp_assert.h" +#endif + +#include "esp_bit_defs.h" +#include "reg_base.h" + +#define PRO_CPU_NUM (0) + +#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) // only one UHCI on C6 +#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000) // UART0 and UART1 +#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000) +#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) +#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C6 +#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 +#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1 +#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE) // only one GPSPI on C6 +#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C6 +#define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE) // only one MCPWM on C6 +#define REG_TWAI_BASE(i) (DR_REG_TWAI_BASE + (i) * 0x2000) // TWAI0 and TWAI1 + +//Registers Operation {{ +#define ETS_UNCACHED_ADDR(addr) (addr) +#define ETS_CACHED_ADDR(addr) (addr) + +#ifndef __ASSEMBLER__ + +//write value to register +#define REG_WRITE(_r, _v) do { \ + (*(volatile uint32_t *)(_r)) = (_v); \ + } while(0) + +//read value from register +#define REG_READ(_r) ({ \ + (*(volatile uint32_t *)(_r)); \ + }) + +//get bit or get bits from register +#define REG_GET_BIT(_r, _b) ({ \ + (*(volatile uint32_t*)(_r) & (_b)); \ + }) + +//set bit or set bits to register +#define REG_SET_BIT(_r, _b) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) | (_b); \ + } while(0) + +//clear bit or clear bits of register +#define REG_CLR_BIT(_r, _b) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) & (~(_b)); \ + } while(0) + +//set bits of register controlled by mask +#define REG_SET_BITS(_r, _b, _m) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)); \ + } while(0) + +//get field from register, uses field _S & _V to determine mask +#define REG_GET_FIELD(_r, _f) ({ \ + ((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \ + }) + +//set field of a register from variable, uses field _S & _V to determine mask +#define REG_SET_FIELD(_r, _f, _v) do { \ + REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))); \ + } while(0) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//read value from register +#define READ_PERI_REG(addr) ({ \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \ + }) + +//write value to register +#define WRITE_PERI_REG(addr, val) do { \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \ + } while(0) + +//clear bits of register controlled by mask +#define CLEAR_PERI_REG_MASK(reg, mask) do { \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \ + } while(0) + +//set bits of register controlled by mask +#define SET_PERI_REG_MASK(reg, mask) do { \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \ + } while(0) + +//get bits of register controlled by mask +#define GET_PERI_REG_MASK(reg, mask) ({ \ + (READ_PERI_REG(reg) & (mask)); \ + }) + +//get bits of register controlled by highest bit and lowest bit +#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \ + ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \ + }) + +//set bits of register controlled by mask and shift +#define SET_PERI_REG_BITS(reg,bit_map,value,shift) do { \ + WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) ); \ + } while(0) + +//get field of register +#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \ + ((READ_PERI_REG(reg)>>(shift))&(mask)); \ + }) + +#endif /* !__ASSEMBLER__ */ +//}} + +//Periheral Clock {{ +#define APB_CLK_FREQ_ROM ( 40*1000000 ) +#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM +#define EFUSE_CLK_FREQ_ROM ( 20*1000000) +#define CPU_CLK_FREQ APB_CLK_FREQ +#if CONFIG_IDF_ENV_FPGA +#define APB_CLK_FREQ ( 40*1000000 ) +#else +#define APB_CLK_FREQ ( 80*1000000 ) +#endif +#define REF_CLK_FREQ ( 1000000 ) +#define RTC_CLK_FREQ (20*1000000) +#define XTAL_CLK_FREQ (40*1000000) +#define UART_CLK_FREQ APB_CLK_FREQ +#define WDT_CLK_FREQ APB_CLK_FREQ +#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16 +#define SPI_CLK_DIV 4 +#define TICKS_PER_US_ROM 40 // CPU is 80MHz +#define GPIO_MATRIX_DELAY_NS 0 +//}} + +/* Overall memory map */ +/* Note: We should not use MACROs similar in cache_memory.h + * those are defined during run-time. But the MACROs here + * should be defined statically! + */ + +#define SOC_IROM_LOW 0x42000000 +#define SOC_IROM_HIGH (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<7)) +#define SOC_DROM_LOW SOC_IROM_HIGH +#define SOC_DROM_HIGH (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<8)) +#define SOC_IROM_MASK_LOW 0x40000000 +#define SOC_IROM_MASK_HIGH 0x4004AC00 +#define SOC_DROM_MASK_LOW 0x4004AC00 +#define SOC_DROM_MASK_HIGH 0x40050000 +#define SOC_IRAM_LOW 0x40800000 +#define SOC_IRAM_HIGH 0x40880000 +#define SOC_DRAM_LOW 0x40800000 +#define SOC_DRAM_HIGH 0x40880000 +#define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-C6 only has 16k LP memory +#define SOC_RTC_IRAM_HIGH 0x50004000 +#define SOC_RTC_DRAM_LOW 0x50000000 +#define SOC_RTC_DRAM_HIGH 0x50004000 +#define SOC_RTC_DATA_LOW 0x50000000 +#define SOC_RTC_DATA_HIGH 0x50004000 + +//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. +#define SOC_DIRAM_IRAM_LOW 0x40800000 +#define SOC_DIRAM_IRAM_HIGH 0x40880000 +#define SOC_DIRAM_DRAM_LOW 0x40800000 +#define SOC_DIRAM_DRAM_HIGH 0x40880000 + +// Region of memory accessible via DMA. See esp_ptr_dma_capable(). +#define SOC_DMA_LOW 0x40800000 +#define SOC_DMA_HIGH 0x40880000 + +// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible(). +#define SOC_BYTE_ACCESSIBLE_LOW 0x40800000 +#define SOC_BYTE_ACCESSIBLE_HIGH 0x40880000 + +//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs +//(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). +#define SOC_MEM_INTERNAL_LOW 0x40800000 +#define SOC_MEM_INTERNAL_HIGH 0x40880000 +#define SOC_MEM_INTERNAL_LOW1 0x40800000 +#define SOC_MEM_INTERNAL_HIGH1 0x40880000 + +#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space + +// Region of address space that holds peripherals +#define SOC_PERIPHERAL_LOW 0x60000000 +#define SOC_PERIPHERAL_HIGH 0x60100000 + +// Debug region, not used by software +#define SOC_DEBUG_LOW 0x20000000 +#define SOC_DEBUG_HIGH 0x28000000 + +// Start (highest address) of ROM boot stack, only relevant during early boot +#define SOC_ROM_STACK_START 0x4087e610 +#define SOC_ROM_STACK_SIZE 0x2000 + +//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW. +//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG. + +//CPU0 Interrupt number reserved in riscv/vector.S, not touch this. +#define ETS_T1_WDT_INUM 24 +#define ETS_CACHEERR_INUM 25 +#define ETS_MEMPROT_ERR_INUM 26 +//CPU0 Max valid interrupt number +#define ETS_MAX_INUM 31 + +//CPU0 Interrupt number used in ROM, should be cancelled in SDK +#define ETS_SLC_INUM 1 +#define ETS_UART0_INUM 5 +#define ETS_UART1_INUM 5 +#define ETS_SPI2_INUM 1 +//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here. +#define ETS_GPIO_INUM 4 + +//Other interrupt number should be managed by the user + +//Invalid interrupt for number interrupt matrix +#define ETS_INVALID_INUM 0 + +//Interrupt medium level, used for INT WDT for example +#define SOC_INTERRUPT_LEVEL_MEDIUM 4 + +// Interrupt number for the Interrupt watchdog +#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM) diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h new file mode 100644 index 0000000000..bdd7165252 --- /dev/null +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -0,0 +1,409 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The long term plan is to have a single soc_caps.h for each peripheral. +// During the refactoring and multichip support development process, we +// seperate these information into periph_caps.h for each peripheral and +// include them here. + +/* + * These defines are parsed and imported as kconfig variables via the script + * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py` + * + * If this file is changed the script will automatically run the script + * and generate the kconfig variables as part of the pre-commit hooks. + * + * It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32c6/include/soc/'` + * + * For more information see `tools/gen_soc_caps_kconfig/README.md` + * +*/ + +#pragma once + +/*-------------------------- COMMON CAPS ---------------------------------------*/ +// #define SOC_ADC_SUPPORTED 1 // TODO: IDF-5310 +#define SOC_DEDICATED_GPIO_SUPPORTED 1 +#define SOC_GDMA_SUPPORTED 1 +#define SOC_PCNT_SUPPORTED 1 +// #define SOC_TWAI_SUPPORTED 1 // TODO: IDF-5313 +#define SOC_BT_SUPPORTED 1 +#define SOC_ASYNC_MEMCPY_SUPPORTED 1 +#define SOC_USB_SERIAL_JTAG_SUPPORTED 1 +// #define SOC_TEMP_SENSOR_SUPPORTED 1 // TODO: IDF-5322 +// #define SOC_WIFI_SUPPORTED 1 // TODO: IDF-5679 +#define SOC_SUPPORTS_SECURE_DL_MODE 1 +//#define SOC_RISCV_COPROC_SUPPORTED 1 // TODO: IDF-5816 +#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 +#define SOC_RTC_FAST_MEM_SUPPORTED 1 +#define SOC_RTC_MEM_SUPPORTED 1 +#define SOC_I2S_SUPPORTED 1 +#define SOC_RMT_SUPPORTED 1 +#define SOC_SDM_SUPPORTED 1 +// #define SOC_LEDC_SUPPORTED 1 // TODO: IDF-5328 +// #define SOC_I2C_SUPPORTED 1 // TODO: IDF-5326 +#define SOC_SYSTIMER_SUPPORTED 1 +#define SOC_SUPPORT_COEXISTENCE 1 +// #define SOC_AES_SUPPORTED 1 // TODO: IDF-5356 +// #define SOC_MPI_SUPPORTED 1 +// #define SOC_SHA_SUPPORTED 1 // TODO: IDF-5353 +// #define SOC_HMAC_SUPPORTED 1 // TODO: IDF-5355 +// #define SOC_DIG_SIGN_SUPPORTED 1 // TODO: IDF-5360 +#define SOC_FLASH_ENC_SUPPORTED 1 +#define SOC_SECURE_BOOT_SUPPORTED 1 +// #define SOC_MEMPROT_SUPPORTED 1 // TODO: IDF-5684 + +/*-------------------------- XTAL CAPS ---------------------------------------*/ +#define SOC_XTAL_SUPPORT_40M 1 + +// TODO: IDF-5356 (Copy from esp32c3, need check) +/*-------------------------- AES CAPS -----------------------------------------*/ +#define SOC_AES_SUPPORT_DMA (1) + +/* Has a centralized DMA, which is shared with all peripherals */ +#define SOC_AES_GDMA (1) + +#define SOC_AES_SUPPORT_AES_128 (1) +#define SOC_AES_SUPPORT_AES_256 (1) + +// TODO: IDF-5310 (Copy from esp32c3, need check) +/*-------------------------- ADC CAPS -------------------------------*/ +/*!< SAR ADC Module*/ +#define SOC_ADC_DIG_CTRL_SUPPORTED 1 +#define SOC_ADC_ARBITER_SUPPORTED 1 +#define SOC_ADC_FILTER_SUPPORTED 1 +#define SOC_ADC_MONITOR_SUPPORTED 1 +#define SOC_ADC_PERIPH_NUM (2) +#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1) +#define SOC_ADC_MAX_CHANNEL_NUM (5) +#define SOC_ADC_ATTEN_NUM (4) + +/*!< Digital */ +#define SOC_ADC_DIGI_CONTROLLER_NUM (1U) +#define SOC_ADC_PATT_LEN_MAX (8) /*!< One pattern table, each contains 8 items. Each item takes 1 byte */ +#define SOC_ADC_DIGI_MAX_BITWIDTH (12) +#define SOC_ADC_DIGI_FILTER_NUM (2) +#define SOC_ADC_DIGI_MONITOR_NUM (2) +/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 */ +#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 +#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 + +/*!< RTC */ +#define SOC_ADC_RTC_MIN_BITWIDTH (12) +#define SOC_ADC_RTC_MAX_BITWIDTH (12) + +/*!< Calibration */ +#define SOC_ADC_CALIBRATION_V1_SUPPORTED (0) /*!< support HW offset calibration version 1*/ + +// ESP32C6-TODO: Copy from esp32c6, need check +/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ +#define SOC_APB_BACKUP_DMA (0) + +/*-------------------------- BROWNOUT CAPS -----------------------------------*/ +#define SOC_BROWNOUT_RESET_SUPPORTED 1 + +/*-------------------------- CACHE CAPS --------------------------------------*/ +#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data + +/*-------------------------- CPU CAPS ----------------------------------------*/ +#define SOC_CPU_CORES_NUM (1U) +#define SOC_CPU_INTR_NUM 32 +#define SOC_CPU_HAS_FLEXIBLE_INTC 1 +#define SOC_INT_PLIC_SUPPORTED 1 //riscv platform-level interrupt controller + +#define SOC_CPU_BREAKPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes + +// TODO: IDF-5339 (Copy from esp32c3, need check) +/*-------------------------- MMU CAPS ----------------------------------------*/ +#define SOC_MMU_PAGE_SIZE_CONFIGURABLE (1) + +// TODO: IDF-5360 (Copy from esp32c3, need check) +/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ +/** The maximum length of a Digital Signature in bits. */ +#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072) + +/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */ +#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16) + +/** Maximum wait time for DS parameter decryption key. If overdue, then key error. + See TRM DS chapter for more details */ +#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) + +// TODO: IDF-5319 (Copy from esp32c3, need check) +/*-------------------------- GDMA CAPS -------------------------------------*/ +#define SOC_GDMA_GROUPS (1U) // Number of GDMA groups +#define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group + +// TODO: IDF-5321 (Copy from esp32c3, need check) +/*-------------------------- GPIO CAPS ---------------------------------------*/ +// ESP32-C6 has 1 GPIO peripheral +#define SOC_GPIO_PORT (1U) +#define SOC_GPIO_PIN_COUNT (31) + +// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC +// On ESP32-C6, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers. +#define SOC_GPIO_SUPPORTS_RTC_INDEPENDENT (1) +// Force hold is a new function of ESP32-C6 +#define SOC_GPIO_SUPPORT_FORCE_HOLD (1) +// GPIO0~5 on ESP32C6 can support chip deep sleep wakeup +#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) + +#define SOC_GPIO_VALID_GPIO_MASK ((1U<> 3) +#define SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3) + +#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)) + +/*-------------------------- RTCIO CAPS --------------------------------------*/ +/* No dedicated RTCIO subsystem on ESP32-C6. RTC functions are still supported + * for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */ +#define SOC_RTCIO_PIN_COUNT (0U) + +// TODO: IDF-5359 (Copy from esp32c3, need check) +/*--------------------------- RSA CAPS ---------------------------------------*/ +#define SOC_RSA_MAX_BIT_LEN (3072) + +// TODO: IDF-5353 (Copy from esp32c3, need check) +/*--------------------------- SHA CAPS ---------------------------------------*/ + +/* Max amount of bytes in a single DMA operation is 4095, + for SHA this means that the biggest safe amount of bytes is + 31 blocks of 128 bytes = 3968 +*/ +#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968) +#define SOC_SHA_SUPPORT_DMA (1) + +/* The SHA engine is able to resume hashing from a user */ +#define SOC_SHA_SUPPORT_RESUME (1) + +/* Has a centralized DMA, which is shared with all peripherals */ +#define SOC_SHA_GDMA (1) + +/* Supported HW algorithms */ +#define SOC_SHA_SUPPORT_SHA1 (1) +#define SOC_SHA_SUPPORT_SHA224 (1) +#define SOC_SHA_SUPPORT_SHA256 (1) + +/*-------------------------- Sigma Delta Modulator CAPS -----------------*/ +#define SOC_SDM_GROUPS 1U +#define SOC_SDM_CHANNELS_PER_GROUP 4 + +// TODO: IDF-5334 (Copy from esp32c3, need check) +/*-------------------------- SPI CAPS ----------------------------------------*/ +#define SOC_SPI_PERIPH_NUM 2 +#define SOC_SPI_PERIPH_CS_NUM(i) 6 +#define SOC_SPI_MAX_CS_NUM 6 + +#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 + +#define SOC_SPI_SUPPORT_DDRCLK 1 +#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 +#define SOC_SPI_SUPPORT_CD_SIG 1 +#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 +#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 + +// Peripheral supports DIO, DOUT, QIO, or QOUT +// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, +#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) + +#define SOC_MEMSPI_IS_INDEPENDENT 1 +#define SOC_SPI_MAX_PRE_DIVIDER 16 + +// TODO: IDF-5333 (Copy from esp32c3, need check) +/*-------------------------- SPI MEM CAPS ---------------------------------------*/ +#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) +#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) +#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1) +#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1) +#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) +#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) + +#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 +#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 +#define SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED 1 +#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 + +// TODO: IDF-5323 (Copy from esp32c3, need check) +/*-------------------------- SYSTIMER CAPS ----------------------------------*/ +#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units +#define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part +#define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part +#define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed: 2.5 +#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt +#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current) + +/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ +#define SOC_TIMER_GROUPS (2) +#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U) +#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) +#define SOC_TIMER_GROUP_SUPPORT_XTAL (1) +#define SOC_TIMER_GROUP_SUPPORT_APB (1) +#define SOC_TIMER_GROUP_TOTAL_TIMERS (2) +#define SOC_TIMER_SUPPORT_ETM (1) + +// TODO: IDF-5313 (Copy from esp32c3, need check) +/*-------------------------- TWAI CAPS ---------------------------------------*/ +#define SOC_TWAI_BRP_MIN 2 +#define SOC_TWAI_BRP_MAX 16384 +#define SOC_TWAI_SUPPORTS_RX_STATUS 1 + +// TODO: IDF-5357 (Copy from esp32c3, need check) +/*-------------------------- Secure Boot CAPS----------------------------*/ +#define SOC_SECURE_BOOT_V2_RSA 1 +#define SOC_SECURE_BOOT_V2_ECC 1 +#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 +#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 +#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1 + +// TODO: IDF-5358 (Copy from esp32c3, need check) +/*-------------------------- Flash Encryption CAPS----------------------------*/ +#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32) +#define SOC_FLASH_ENCRYPTION_XTS_AES 1 +#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 + +// TODO: IDF-5684 (Copy from esp32c3, need check) +/*-------------------------- MEMPROT CAPS ------------------------------------*/ +#define SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE 16 +#define SOC_MEMPROT_MEM_ALIGN_SIZE 512 + +// TODO: IDF-5338 (Copy from esp32c3, need check) +/*-------------------------- UART CAPS ---------------------------------------*/ +// ESP32-C6 has 2 UARTs +#define SOC_UART_NUM (2) +#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ +#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ + +#define SOC_UART_SUPPORT_APB_CLK (1) /*!< Support APB as the clock source */ +#define SOC_UART_SUPPORT_RTC_CLK (0) /*!< Support RTC clock as the clock source */ // TODO: IDF-5338 +#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ +// #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ // TODO: IDF-5338 +#define SOC_UART_REQUIRE_CORE_RESET (1) + +// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled +#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) + +// TODO: IDF-5679 (Copy from esp32c3, need check) +/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/ +#define SOC_COEX_HW_PTI (1) + +// TODO: IDF-5680 (Copy from esp32c3, need check) +/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ +#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) +#define SOC_MAC_BB_PD_MEM_SIZE (192*4) + +// TODO: IDF-5679 (Copy from esp32c3, need check) +/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/ +#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12) + +// TODO: IDF-5351 (Copy from esp32c3, need check) +/*-------------------------- Power Management CAPS ----------------------------*/ +#define SOC_PM_SUPPORT_WIFI_WAKEUP (1) + +#define SOC_PM_SUPPORT_BT_WAKEUP (1) + +#define SOC_PM_SUPPORT_CPU_PD (1) + +#define SOC_PM_SUPPORT_WIFI_PD (1) + +#define SOC_PM_SUPPORT_BT_PD (1) + +// TODO: IDF-5322 (Copy from esp32c3, need check) +/*-------------------------- Temperature Sensor CAPS -------------------------------------*/ +#define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1) +#define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1) + +// TODO: IDF-5679 (Copy from esp32c3, need check) +/*------------------------------------ WI-FI CAPS ------------------------------------*/ +#define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */ +#define SOC_WIFI_FTM_SUPPORT (1) /*!< Support FTM */ +#define SOC_WIFI_GCMP_SUPPORT (1) /*!< Support GCMP(GCMP128 and GCMP256) */ +#define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */ +#define SOC_WIFI_CSI_SUPPORT (1) /*!< Support CSI */ +#define SOC_WIFI_MESH_SUPPORT (1) /*!< Support WIFI MESH */ diff --git a/components/soc/esp32c6/include/soc/soc_etm_reg.h b/components/soc/esp32c6/include/soc/soc_etm_reg.h new file mode 100644 index 0000000000..07b3cf52ea --- /dev/null +++ b/components/soc/esp32c6/include/soc/soc_etm_reg.h @@ -0,0 +1,2320 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SOC_ETM_CH_ENA_AD0_REG register + * channel enable register + */ +#define SOC_ETM_CH_ENA_AD0_REG (DR_REG_SOC_ETM_BASE + 0x0) +/** SOC_ETM_CH_ENA0 : R/WTC/WTS; bitpos: [0]; default: 0; + * ch0 enable + */ +#define SOC_ETM_CH_ENA0 (BIT(0)) +#define SOC_ETM_CH_ENA0_M (SOC_ETM_CH_ENA0_V << SOC_ETM_CH_ENA0_S) +#define SOC_ETM_CH_ENA0_V 0x00000001U +#define SOC_ETM_CH_ENA0_S 0 +/** SOC_ETM_CH_ENA1 : R/WTC/WTS; bitpos: [1]; default: 0; + * ch1 enable + */ +#define SOC_ETM_CH_ENA1 (BIT(1)) +#define SOC_ETM_CH_ENA1_M (SOC_ETM_CH_ENA1_V << SOC_ETM_CH_ENA1_S) +#define SOC_ETM_CH_ENA1_V 0x00000001U +#define SOC_ETM_CH_ENA1_S 1 +/** SOC_ETM_CH_ENA2 : R/WTC/WTS; bitpos: [2]; default: 0; + * ch2 enable + */ +#define SOC_ETM_CH_ENA2 (BIT(2)) +#define SOC_ETM_CH_ENA2_M (SOC_ETM_CH_ENA2_V << SOC_ETM_CH_ENA2_S) +#define SOC_ETM_CH_ENA2_V 0x00000001U +#define SOC_ETM_CH_ENA2_S 2 +/** SOC_ETM_CH_ENA3 : R/WTC/WTS; bitpos: [3]; default: 0; + * ch3 enable + */ +#define SOC_ETM_CH_ENA3 (BIT(3)) +#define SOC_ETM_CH_ENA3_M (SOC_ETM_CH_ENA3_V << SOC_ETM_CH_ENA3_S) +#define SOC_ETM_CH_ENA3_V 0x00000001U +#define SOC_ETM_CH_ENA3_S 3 +/** SOC_ETM_CH_ENA4 : R/WTC/WTS; bitpos: [4]; default: 0; + * ch4 enable + */ +#define SOC_ETM_CH_ENA4 (BIT(4)) +#define SOC_ETM_CH_ENA4_M (SOC_ETM_CH_ENA4_V << SOC_ETM_CH_ENA4_S) +#define SOC_ETM_CH_ENA4_V 0x00000001U +#define SOC_ETM_CH_ENA4_S 4 +/** SOC_ETM_CH_ENA5 : R/WTC/WTS; bitpos: [5]; default: 0; + * ch5 enable + */ +#define SOC_ETM_CH_ENA5 (BIT(5)) +#define SOC_ETM_CH_ENA5_M (SOC_ETM_CH_ENA5_V << SOC_ETM_CH_ENA5_S) +#define SOC_ETM_CH_ENA5_V 0x00000001U +#define SOC_ETM_CH_ENA5_S 5 +/** SOC_ETM_CH_ENA6 : R/WTC/WTS; bitpos: [6]; default: 0; + * ch6 enable + */ +#define SOC_ETM_CH_ENA6 (BIT(6)) +#define SOC_ETM_CH_ENA6_M (SOC_ETM_CH_ENA6_V << SOC_ETM_CH_ENA6_S) +#define SOC_ETM_CH_ENA6_V 0x00000001U +#define SOC_ETM_CH_ENA6_S 6 +/** SOC_ETM_CH_ENA7 : R/WTC/WTS; bitpos: [7]; default: 0; + * ch7 enable + */ +#define SOC_ETM_CH_ENA7 (BIT(7)) +#define SOC_ETM_CH_ENA7_M (SOC_ETM_CH_ENA7_V << SOC_ETM_CH_ENA7_S) +#define SOC_ETM_CH_ENA7_V 0x00000001U +#define SOC_ETM_CH_ENA7_S 7 +/** SOC_ETM_CH_ENA8 : R/WTC/WTS; bitpos: [8]; default: 0; + * ch8 enable + */ +#define SOC_ETM_CH_ENA8 (BIT(8)) +#define SOC_ETM_CH_ENA8_M (SOC_ETM_CH_ENA8_V << SOC_ETM_CH_ENA8_S) +#define SOC_ETM_CH_ENA8_V 0x00000001U +#define SOC_ETM_CH_ENA8_S 8 +/** SOC_ETM_CH_ENA9 : R/WTC/WTS; bitpos: [9]; default: 0; + * ch9 enable + */ +#define SOC_ETM_CH_ENA9 (BIT(9)) +#define SOC_ETM_CH_ENA9_M (SOC_ETM_CH_ENA9_V << SOC_ETM_CH_ENA9_S) +#define SOC_ETM_CH_ENA9_V 0x00000001U +#define SOC_ETM_CH_ENA9_S 9 +/** SOC_ETM_CH_ENA10 : R/WTC/WTS; bitpos: [10]; default: 0; + * ch10 enable + */ +#define SOC_ETM_CH_ENA10 (BIT(10)) +#define SOC_ETM_CH_ENA10_M (SOC_ETM_CH_ENA10_V << SOC_ETM_CH_ENA10_S) +#define SOC_ETM_CH_ENA10_V 0x00000001U +#define SOC_ETM_CH_ENA10_S 10 +/** SOC_ETM_CH_ENA11 : R/WTC/WTS; bitpos: [11]; default: 0; + * ch11 enable + */ +#define SOC_ETM_CH_ENA11 (BIT(11)) +#define SOC_ETM_CH_ENA11_M (SOC_ETM_CH_ENA11_V << SOC_ETM_CH_ENA11_S) +#define SOC_ETM_CH_ENA11_V 0x00000001U +#define SOC_ETM_CH_ENA11_S 11 +/** SOC_ETM_CH_ENA12 : R/WTC/WTS; bitpos: [12]; default: 0; + * ch12 enable + */ +#define SOC_ETM_CH_ENA12 (BIT(12)) +#define SOC_ETM_CH_ENA12_M (SOC_ETM_CH_ENA12_V << SOC_ETM_CH_ENA12_S) +#define SOC_ETM_CH_ENA12_V 0x00000001U +#define SOC_ETM_CH_ENA12_S 12 +/** SOC_ETM_CH_ENA13 : R/WTC/WTS; bitpos: [13]; default: 0; + * ch13 enable + */ +#define SOC_ETM_CH_ENA13 (BIT(13)) +#define SOC_ETM_CH_ENA13_M (SOC_ETM_CH_ENA13_V << SOC_ETM_CH_ENA13_S) +#define SOC_ETM_CH_ENA13_V 0x00000001U +#define SOC_ETM_CH_ENA13_S 13 +/** SOC_ETM_CH_ENA14 : R/WTC/WTS; bitpos: [14]; default: 0; + * ch14 enable + */ +#define SOC_ETM_CH_ENA14 (BIT(14)) +#define SOC_ETM_CH_ENA14_M (SOC_ETM_CH_ENA14_V << SOC_ETM_CH_ENA14_S) +#define SOC_ETM_CH_ENA14_V 0x00000001U +#define SOC_ETM_CH_ENA14_S 14 +/** SOC_ETM_CH_ENA15 : R/WTC/WTS; bitpos: [15]; default: 0; + * ch15 enable + */ +#define SOC_ETM_CH_ENA15 (BIT(15)) +#define SOC_ETM_CH_ENA15_M (SOC_ETM_CH_ENA15_V << SOC_ETM_CH_ENA15_S) +#define SOC_ETM_CH_ENA15_V 0x00000001U +#define SOC_ETM_CH_ENA15_S 15 +/** SOC_ETM_CH_ENA16 : R/WTC/WTS; bitpos: [16]; default: 0; + * ch16 enable + */ +#define SOC_ETM_CH_ENA16 (BIT(16)) +#define SOC_ETM_CH_ENA16_M (SOC_ETM_CH_ENA16_V << SOC_ETM_CH_ENA16_S) +#define SOC_ETM_CH_ENA16_V 0x00000001U +#define SOC_ETM_CH_ENA16_S 16 +/** SOC_ETM_CH_ENA17 : R/WTC/WTS; bitpos: [17]; default: 0; + * ch17 enable + */ +#define SOC_ETM_CH_ENA17 (BIT(17)) +#define SOC_ETM_CH_ENA17_M (SOC_ETM_CH_ENA17_V << SOC_ETM_CH_ENA17_S) +#define SOC_ETM_CH_ENA17_V 0x00000001U +#define SOC_ETM_CH_ENA17_S 17 +/** SOC_ETM_CH_ENA18 : R/WTC/WTS; bitpos: [18]; default: 0; + * ch18 enable + */ +#define SOC_ETM_CH_ENA18 (BIT(18)) +#define SOC_ETM_CH_ENA18_M (SOC_ETM_CH_ENA18_V << SOC_ETM_CH_ENA18_S) +#define SOC_ETM_CH_ENA18_V 0x00000001U +#define SOC_ETM_CH_ENA18_S 18 +/** SOC_ETM_CH_ENA19 : R/WTC/WTS; bitpos: [19]; default: 0; + * ch19 enable + */ +#define SOC_ETM_CH_ENA19 (BIT(19)) +#define SOC_ETM_CH_ENA19_M (SOC_ETM_CH_ENA19_V << SOC_ETM_CH_ENA19_S) +#define SOC_ETM_CH_ENA19_V 0x00000001U +#define SOC_ETM_CH_ENA19_S 19 +/** SOC_ETM_CH_ENA20 : R/WTC/WTS; bitpos: [20]; default: 0; + * ch20 enable + */ +#define SOC_ETM_CH_ENA20 (BIT(20)) +#define SOC_ETM_CH_ENA20_M (SOC_ETM_CH_ENA20_V << SOC_ETM_CH_ENA20_S) +#define SOC_ETM_CH_ENA20_V 0x00000001U +#define SOC_ETM_CH_ENA20_S 20 +/** SOC_ETM_CH_ENA21 : R/WTC/WTS; bitpos: [21]; default: 0; + * ch21 enable + */ +#define SOC_ETM_CH_ENA21 (BIT(21)) +#define SOC_ETM_CH_ENA21_M (SOC_ETM_CH_ENA21_V << SOC_ETM_CH_ENA21_S) +#define SOC_ETM_CH_ENA21_V 0x00000001U +#define SOC_ETM_CH_ENA21_S 21 +/** SOC_ETM_CH_ENA22 : R/WTC/WTS; bitpos: [22]; default: 0; + * ch22 enable + */ +#define SOC_ETM_CH_ENA22 (BIT(22)) +#define SOC_ETM_CH_ENA22_M (SOC_ETM_CH_ENA22_V << SOC_ETM_CH_ENA22_S) +#define SOC_ETM_CH_ENA22_V 0x00000001U +#define SOC_ETM_CH_ENA22_S 22 +/** SOC_ETM_CH_ENA23 : R/WTC/WTS; bitpos: [23]; default: 0; + * ch23 enable + */ +#define SOC_ETM_CH_ENA23 (BIT(23)) +#define SOC_ETM_CH_ENA23_M (SOC_ETM_CH_ENA23_V << SOC_ETM_CH_ENA23_S) +#define SOC_ETM_CH_ENA23_V 0x00000001U +#define SOC_ETM_CH_ENA23_S 23 +/** SOC_ETM_CH_ENA24 : R/WTC/WTS; bitpos: [24]; default: 0; + * ch24 enable + */ +#define SOC_ETM_CH_ENA24 (BIT(24)) +#define SOC_ETM_CH_ENA24_M (SOC_ETM_CH_ENA24_V << SOC_ETM_CH_ENA24_S) +#define SOC_ETM_CH_ENA24_V 0x00000001U +#define SOC_ETM_CH_ENA24_S 24 +/** SOC_ETM_CH_ENA25 : R/WTC/WTS; bitpos: [25]; default: 0; + * ch25 enable + */ +#define SOC_ETM_CH_ENA25 (BIT(25)) +#define SOC_ETM_CH_ENA25_M (SOC_ETM_CH_ENA25_V << SOC_ETM_CH_ENA25_S) +#define SOC_ETM_CH_ENA25_V 0x00000001U +#define SOC_ETM_CH_ENA25_S 25 +/** SOC_ETM_CH_ENA26 : R/WTC/WTS; bitpos: [26]; default: 0; + * ch26 enable + */ +#define SOC_ETM_CH_ENA26 (BIT(26)) +#define SOC_ETM_CH_ENA26_M (SOC_ETM_CH_ENA26_V << SOC_ETM_CH_ENA26_S) +#define SOC_ETM_CH_ENA26_V 0x00000001U +#define SOC_ETM_CH_ENA26_S 26 +/** SOC_ETM_CH_ENA27 : R/WTC/WTS; bitpos: [27]; default: 0; + * ch27 enable + */ +#define SOC_ETM_CH_ENA27 (BIT(27)) +#define SOC_ETM_CH_ENA27_M (SOC_ETM_CH_ENA27_V << SOC_ETM_CH_ENA27_S) +#define SOC_ETM_CH_ENA27_V 0x00000001U +#define SOC_ETM_CH_ENA27_S 27 +/** SOC_ETM_CH_ENA28 : R/WTC/WTS; bitpos: [28]; default: 0; + * ch28 enable + */ +#define SOC_ETM_CH_ENA28 (BIT(28)) +#define SOC_ETM_CH_ENA28_M (SOC_ETM_CH_ENA28_V << SOC_ETM_CH_ENA28_S) +#define SOC_ETM_CH_ENA28_V 0x00000001U +#define SOC_ETM_CH_ENA28_S 28 +/** SOC_ETM_CH_ENA29 : R/WTC/WTS; bitpos: [29]; default: 0; + * ch29 enable + */ +#define SOC_ETM_CH_ENA29 (BIT(29)) +#define SOC_ETM_CH_ENA29_M (SOC_ETM_CH_ENA29_V << SOC_ETM_CH_ENA29_S) +#define SOC_ETM_CH_ENA29_V 0x00000001U +#define SOC_ETM_CH_ENA29_S 29 +/** SOC_ETM_CH_ENA30 : R/WTC/WTS; bitpos: [30]; default: 0; + * ch30 enable + */ +#define SOC_ETM_CH_ENA30 (BIT(30)) +#define SOC_ETM_CH_ENA30_M (SOC_ETM_CH_ENA30_V << SOC_ETM_CH_ENA30_S) +#define SOC_ETM_CH_ENA30_V 0x00000001U +#define SOC_ETM_CH_ENA30_S 30 +/** SOC_ETM_CH_ENA31 : R/WTC/WTS; bitpos: [31]; default: 0; + * ch31 enable + */ +#define SOC_ETM_CH_ENA31 (BIT(31)) +#define SOC_ETM_CH_ENA31_M (SOC_ETM_CH_ENA31_V << SOC_ETM_CH_ENA31_S) +#define SOC_ETM_CH_ENA31_V 0x00000001U +#define SOC_ETM_CH_ENA31_S 31 + +/** SOC_ETM_CH_ENA_AD0_SET_REG register + * channel enable set register + */ +#define SOC_ETM_CH_ENA_AD0_SET_REG (DR_REG_SOC_ETM_BASE + 0x4) +/** SOC_ETM_CH_SET0 : WT; bitpos: [0]; default: 0; + * ch0 set + */ +#define SOC_ETM_CH_SET0 (BIT(0)) +#define SOC_ETM_CH_SET0_M (SOC_ETM_CH_SET0_V << SOC_ETM_CH_SET0_S) +#define SOC_ETM_CH_SET0_V 0x00000001U +#define SOC_ETM_CH_SET0_S 0 +/** SOC_ETM_CH_SET1 : WT; bitpos: [1]; default: 0; + * ch1 set + */ +#define SOC_ETM_CH_SET1 (BIT(1)) +#define SOC_ETM_CH_SET1_M (SOC_ETM_CH_SET1_V << SOC_ETM_CH_SET1_S) +#define SOC_ETM_CH_SET1_V 0x00000001U +#define SOC_ETM_CH_SET1_S 1 +/** SOC_ETM_CH_SET2 : WT; bitpos: [2]; default: 0; + * ch2 set + */ +#define SOC_ETM_CH_SET2 (BIT(2)) +#define SOC_ETM_CH_SET2_M (SOC_ETM_CH_SET2_V << SOC_ETM_CH_SET2_S) +#define SOC_ETM_CH_SET2_V 0x00000001U +#define SOC_ETM_CH_SET2_S 2 +/** SOC_ETM_CH_SET3 : WT; bitpos: [3]; default: 0; + * ch3 set + */ +#define SOC_ETM_CH_SET3 (BIT(3)) +#define SOC_ETM_CH_SET3_M (SOC_ETM_CH_SET3_V << SOC_ETM_CH_SET3_S) +#define SOC_ETM_CH_SET3_V 0x00000001U +#define SOC_ETM_CH_SET3_S 3 +/** SOC_ETM_CH_SET4 : WT; bitpos: [4]; default: 0; + * ch4 set + */ +#define SOC_ETM_CH_SET4 (BIT(4)) +#define SOC_ETM_CH_SET4_M (SOC_ETM_CH_SET4_V << SOC_ETM_CH_SET4_S) +#define SOC_ETM_CH_SET4_V 0x00000001U +#define SOC_ETM_CH_SET4_S 4 +/** SOC_ETM_CH_SET5 : WT; bitpos: [5]; default: 0; + * ch5 set + */ +#define SOC_ETM_CH_SET5 (BIT(5)) +#define SOC_ETM_CH_SET5_M (SOC_ETM_CH_SET5_V << SOC_ETM_CH_SET5_S) +#define SOC_ETM_CH_SET5_V 0x00000001U +#define SOC_ETM_CH_SET5_S 5 +/** SOC_ETM_CH_SET6 : WT; bitpos: [6]; default: 0; + * ch6 set + */ +#define SOC_ETM_CH_SET6 (BIT(6)) +#define SOC_ETM_CH_SET6_M (SOC_ETM_CH_SET6_V << SOC_ETM_CH_SET6_S) +#define SOC_ETM_CH_SET6_V 0x00000001U +#define SOC_ETM_CH_SET6_S 6 +/** SOC_ETM_CH_SET7 : WT; bitpos: [7]; default: 0; + * ch7 set + */ +#define SOC_ETM_CH_SET7 (BIT(7)) +#define SOC_ETM_CH_SET7_M (SOC_ETM_CH_SET7_V << SOC_ETM_CH_SET7_S) +#define SOC_ETM_CH_SET7_V 0x00000001U +#define SOC_ETM_CH_SET7_S 7 +/** SOC_ETM_CH_SET8 : WT; bitpos: [8]; default: 0; + * ch8 set + */ +#define SOC_ETM_CH_SET8 (BIT(8)) +#define SOC_ETM_CH_SET8_M (SOC_ETM_CH_SET8_V << SOC_ETM_CH_SET8_S) +#define SOC_ETM_CH_SET8_V 0x00000001U +#define SOC_ETM_CH_SET8_S 8 +/** SOC_ETM_CH_SET9 : WT; bitpos: [9]; default: 0; + * ch9 set + */ +#define SOC_ETM_CH_SET9 (BIT(9)) +#define SOC_ETM_CH_SET9_M (SOC_ETM_CH_SET9_V << SOC_ETM_CH_SET9_S) +#define SOC_ETM_CH_SET9_V 0x00000001U +#define SOC_ETM_CH_SET9_S 9 +/** SOC_ETM_CH_SET10 : WT; bitpos: [10]; default: 0; + * ch10 set + */ +#define SOC_ETM_CH_SET10 (BIT(10)) +#define SOC_ETM_CH_SET10_M (SOC_ETM_CH_SET10_V << SOC_ETM_CH_SET10_S) +#define SOC_ETM_CH_SET10_V 0x00000001U +#define SOC_ETM_CH_SET10_S 10 +/** SOC_ETM_CH_SET11 : WT; bitpos: [11]; default: 0; + * ch11 set + */ +#define SOC_ETM_CH_SET11 (BIT(11)) +#define SOC_ETM_CH_SET11_M (SOC_ETM_CH_SET11_V << SOC_ETM_CH_SET11_S) +#define SOC_ETM_CH_SET11_V 0x00000001U +#define SOC_ETM_CH_SET11_S 11 +/** SOC_ETM_CH_SET12 : WT; bitpos: [12]; default: 0; + * ch12 set + */ +#define SOC_ETM_CH_SET12 (BIT(12)) +#define SOC_ETM_CH_SET12_M (SOC_ETM_CH_SET12_V << SOC_ETM_CH_SET12_S) +#define SOC_ETM_CH_SET12_V 0x00000001U +#define SOC_ETM_CH_SET12_S 12 +/** SOC_ETM_CH_SET13 : WT; bitpos: [13]; default: 0; + * ch13 set + */ +#define SOC_ETM_CH_SET13 (BIT(13)) +#define SOC_ETM_CH_SET13_M (SOC_ETM_CH_SET13_V << SOC_ETM_CH_SET13_S) +#define SOC_ETM_CH_SET13_V 0x00000001U +#define SOC_ETM_CH_SET13_S 13 +/** SOC_ETM_CH_SET14 : WT; bitpos: [14]; default: 0; + * ch14 set + */ +#define SOC_ETM_CH_SET14 (BIT(14)) +#define SOC_ETM_CH_SET14_M (SOC_ETM_CH_SET14_V << SOC_ETM_CH_SET14_S) +#define SOC_ETM_CH_SET14_V 0x00000001U +#define SOC_ETM_CH_SET14_S 14 +/** SOC_ETM_CH_SET15 : WT; bitpos: [15]; default: 0; + * ch15 set + */ +#define SOC_ETM_CH_SET15 (BIT(15)) +#define SOC_ETM_CH_SET15_M (SOC_ETM_CH_SET15_V << SOC_ETM_CH_SET15_S) +#define SOC_ETM_CH_SET15_V 0x00000001U +#define SOC_ETM_CH_SET15_S 15 +/** SOC_ETM_CH_SET16 : WT; bitpos: [16]; default: 0; + * ch16 set + */ +#define SOC_ETM_CH_SET16 (BIT(16)) +#define SOC_ETM_CH_SET16_M (SOC_ETM_CH_SET16_V << SOC_ETM_CH_SET16_S) +#define SOC_ETM_CH_SET16_V 0x00000001U +#define SOC_ETM_CH_SET16_S 16 +/** SOC_ETM_CH_SET17 : WT; bitpos: [17]; default: 0; + * ch17 set + */ +#define SOC_ETM_CH_SET17 (BIT(17)) +#define SOC_ETM_CH_SET17_M (SOC_ETM_CH_SET17_V << SOC_ETM_CH_SET17_S) +#define SOC_ETM_CH_SET17_V 0x00000001U +#define SOC_ETM_CH_SET17_S 17 +/** SOC_ETM_CH_SET18 : WT; bitpos: [18]; default: 0; + * ch18 set + */ +#define SOC_ETM_CH_SET18 (BIT(18)) +#define SOC_ETM_CH_SET18_M (SOC_ETM_CH_SET18_V << SOC_ETM_CH_SET18_S) +#define SOC_ETM_CH_SET18_V 0x00000001U +#define SOC_ETM_CH_SET18_S 18 +/** SOC_ETM_CH_SET19 : WT; bitpos: [19]; default: 0; + * ch19 set + */ +#define SOC_ETM_CH_SET19 (BIT(19)) +#define SOC_ETM_CH_SET19_M (SOC_ETM_CH_SET19_V << SOC_ETM_CH_SET19_S) +#define SOC_ETM_CH_SET19_V 0x00000001U +#define SOC_ETM_CH_SET19_S 19 +/** SOC_ETM_CH_SET20 : WT; bitpos: [20]; default: 0; + * ch20 set + */ +#define SOC_ETM_CH_SET20 (BIT(20)) +#define SOC_ETM_CH_SET20_M (SOC_ETM_CH_SET20_V << SOC_ETM_CH_SET20_S) +#define SOC_ETM_CH_SET20_V 0x00000001U +#define SOC_ETM_CH_SET20_S 20 +/** SOC_ETM_CH_SET21 : WT; bitpos: [21]; default: 0; + * ch21 set + */ +#define SOC_ETM_CH_SET21 (BIT(21)) +#define SOC_ETM_CH_SET21_M (SOC_ETM_CH_SET21_V << SOC_ETM_CH_SET21_S) +#define SOC_ETM_CH_SET21_V 0x00000001U +#define SOC_ETM_CH_SET21_S 21 +/** SOC_ETM_CH_SET22 : WT; bitpos: [22]; default: 0; + * ch22 set + */ +#define SOC_ETM_CH_SET22 (BIT(22)) +#define SOC_ETM_CH_SET22_M (SOC_ETM_CH_SET22_V << SOC_ETM_CH_SET22_S) +#define SOC_ETM_CH_SET22_V 0x00000001U +#define SOC_ETM_CH_SET22_S 22 +/** SOC_ETM_CH_SET23 : WT; bitpos: [23]; default: 0; + * ch23 set + */ +#define SOC_ETM_CH_SET23 (BIT(23)) +#define SOC_ETM_CH_SET23_M (SOC_ETM_CH_SET23_V << SOC_ETM_CH_SET23_S) +#define SOC_ETM_CH_SET23_V 0x00000001U +#define SOC_ETM_CH_SET23_S 23 +/** SOC_ETM_CH_SET24 : WT; bitpos: [24]; default: 0; + * ch24 set + */ +#define SOC_ETM_CH_SET24 (BIT(24)) +#define SOC_ETM_CH_SET24_M (SOC_ETM_CH_SET24_V << SOC_ETM_CH_SET24_S) +#define SOC_ETM_CH_SET24_V 0x00000001U +#define SOC_ETM_CH_SET24_S 24 +/** SOC_ETM_CH_SET25 : WT; bitpos: [25]; default: 0; + * ch25 set + */ +#define SOC_ETM_CH_SET25 (BIT(25)) +#define SOC_ETM_CH_SET25_M (SOC_ETM_CH_SET25_V << SOC_ETM_CH_SET25_S) +#define SOC_ETM_CH_SET25_V 0x00000001U +#define SOC_ETM_CH_SET25_S 25 +/** SOC_ETM_CH_SET26 : WT; bitpos: [26]; default: 0; + * ch26 set + */ +#define SOC_ETM_CH_SET26 (BIT(26)) +#define SOC_ETM_CH_SET26_M (SOC_ETM_CH_SET26_V << SOC_ETM_CH_SET26_S) +#define SOC_ETM_CH_SET26_V 0x00000001U +#define SOC_ETM_CH_SET26_S 26 +/** SOC_ETM_CH_SET27 : WT; bitpos: [27]; default: 0; + * ch27 set + */ +#define SOC_ETM_CH_SET27 (BIT(27)) +#define SOC_ETM_CH_SET27_M (SOC_ETM_CH_SET27_V << SOC_ETM_CH_SET27_S) +#define SOC_ETM_CH_SET27_V 0x00000001U +#define SOC_ETM_CH_SET27_S 27 +/** SOC_ETM_CH_SET28 : WT; bitpos: [28]; default: 0; + * ch28 set + */ +#define SOC_ETM_CH_SET28 (BIT(28)) +#define SOC_ETM_CH_SET28_M (SOC_ETM_CH_SET28_V << SOC_ETM_CH_SET28_S) +#define SOC_ETM_CH_SET28_V 0x00000001U +#define SOC_ETM_CH_SET28_S 28 +/** SOC_ETM_CH_SET29 : WT; bitpos: [29]; default: 0; + * ch29 set + */ +#define SOC_ETM_CH_SET29 (BIT(29)) +#define SOC_ETM_CH_SET29_M (SOC_ETM_CH_SET29_V << SOC_ETM_CH_SET29_S) +#define SOC_ETM_CH_SET29_V 0x00000001U +#define SOC_ETM_CH_SET29_S 29 +/** SOC_ETM_CH_SET30 : WT; bitpos: [30]; default: 0; + * ch30 set + */ +#define SOC_ETM_CH_SET30 (BIT(30)) +#define SOC_ETM_CH_SET30_M (SOC_ETM_CH_SET30_V << SOC_ETM_CH_SET30_S) +#define SOC_ETM_CH_SET30_V 0x00000001U +#define SOC_ETM_CH_SET30_S 30 +/** SOC_ETM_CH_SET31 : WT; bitpos: [31]; default: 0; + * ch31 set + */ +#define SOC_ETM_CH_SET31 (BIT(31)) +#define SOC_ETM_CH_SET31_M (SOC_ETM_CH_SET31_V << SOC_ETM_CH_SET31_S) +#define SOC_ETM_CH_SET31_V 0x00000001U +#define SOC_ETM_CH_SET31_S 31 + +/** SOC_ETM_CH_ENA_AD0_CLR_REG register + * channel enable clear register + */ +#define SOC_ETM_CH_ENA_AD0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x8) +/** SOC_ETM_CH_CLR0 : WT; bitpos: [0]; default: 0; + * ch0 clear + */ +#define SOC_ETM_CH_CLR0 (BIT(0)) +#define SOC_ETM_CH_CLR0_M (SOC_ETM_CH_CLR0_V << SOC_ETM_CH_CLR0_S) +#define SOC_ETM_CH_CLR0_V 0x00000001U +#define SOC_ETM_CH_CLR0_S 0 +/** SOC_ETM_CH_CLR1 : WT; bitpos: [1]; default: 0; + * ch1 clear + */ +#define SOC_ETM_CH_CLR1 (BIT(1)) +#define SOC_ETM_CH_CLR1_M (SOC_ETM_CH_CLR1_V << SOC_ETM_CH_CLR1_S) +#define SOC_ETM_CH_CLR1_V 0x00000001U +#define SOC_ETM_CH_CLR1_S 1 +/** SOC_ETM_CH_CLR2 : WT; bitpos: [2]; default: 0; + * ch2 clear + */ +#define SOC_ETM_CH_CLR2 (BIT(2)) +#define SOC_ETM_CH_CLR2_M (SOC_ETM_CH_CLR2_V << SOC_ETM_CH_CLR2_S) +#define SOC_ETM_CH_CLR2_V 0x00000001U +#define SOC_ETM_CH_CLR2_S 2 +/** SOC_ETM_CH_CLR3 : WT; bitpos: [3]; default: 0; + * ch3 clear + */ +#define SOC_ETM_CH_CLR3 (BIT(3)) +#define SOC_ETM_CH_CLR3_M (SOC_ETM_CH_CLR3_V << SOC_ETM_CH_CLR3_S) +#define SOC_ETM_CH_CLR3_V 0x00000001U +#define SOC_ETM_CH_CLR3_S 3 +/** SOC_ETM_CH_CLR4 : WT; bitpos: [4]; default: 0; + * ch4 clear + */ +#define SOC_ETM_CH_CLR4 (BIT(4)) +#define SOC_ETM_CH_CLR4_M (SOC_ETM_CH_CLR4_V << SOC_ETM_CH_CLR4_S) +#define SOC_ETM_CH_CLR4_V 0x00000001U +#define SOC_ETM_CH_CLR4_S 4 +/** SOC_ETM_CH_CLR5 : WT; bitpos: [5]; default: 0; + * ch5 clear + */ +#define SOC_ETM_CH_CLR5 (BIT(5)) +#define SOC_ETM_CH_CLR5_M (SOC_ETM_CH_CLR5_V << SOC_ETM_CH_CLR5_S) +#define SOC_ETM_CH_CLR5_V 0x00000001U +#define SOC_ETM_CH_CLR5_S 5 +/** SOC_ETM_CH_CLR6 : WT; bitpos: [6]; default: 0; + * ch6 clear + */ +#define SOC_ETM_CH_CLR6 (BIT(6)) +#define SOC_ETM_CH_CLR6_M (SOC_ETM_CH_CLR6_V << SOC_ETM_CH_CLR6_S) +#define SOC_ETM_CH_CLR6_V 0x00000001U +#define SOC_ETM_CH_CLR6_S 6 +/** SOC_ETM_CH_CLR7 : WT; bitpos: [7]; default: 0; + * ch7 clear + */ +#define SOC_ETM_CH_CLR7 (BIT(7)) +#define SOC_ETM_CH_CLR7_M (SOC_ETM_CH_CLR7_V << SOC_ETM_CH_CLR7_S) +#define SOC_ETM_CH_CLR7_V 0x00000001U +#define SOC_ETM_CH_CLR7_S 7 +/** SOC_ETM_CH_CLR8 : WT; bitpos: [8]; default: 0; + * ch8 clear + */ +#define SOC_ETM_CH_CLR8 (BIT(8)) +#define SOC_ETM_CH_CLR8_M (SOC_ETM_CH_CLR8_V << SOC_ETM_CH_CLR8_S) +#define SOC_ETM_CH_CLR8_V 0x00000001U +#define SOC_ETM_CH_CLR8_S 8 +/** SOC_ETM_CH_CLR9 : WT; bitpos: [9]; default: 0; + * ch9 clear + */ +#define SOC_ETM_CH_CLR9 (BIT(9)) +#define SOC_ETM_CH_CLR9_M (SOC_ETM_CH_CLR9_V << SOC_ETM_CH_CLR9_S) +#define SOC_ETM_CH_CLR9_V 0x00000001U +#define SOC_ETM_CH_CLR9_S 9 +/** SOC_ETM_CH_CLR10 : WT; bitpos: [10]; default: 0; + * ch10 clear + */ +#define SOC_ETM_CH_CLR10 (BIT(10)) +#define SOC_ETM_CH_CLR10_M (SOC_ETM_CH_CLR10_V << SOC_ETM_CH_CLR10_S) +#define SOC_ETM_CH_CLR10_V 0x00000001U +#define SOC_ETM_CH_CLR10_S 10 +/** SOC_ETM_CH_CLR11 : WT; bitpos: [11]; default: 0; + * ch11 clear + */ +#define SOC_ETM_CH_CLR11 (BIT(11)) +#define SOC_ETM_CH_CLR11_M (SOC_ETM_CH_CLR11_V << SOC_ETM_CH_CLR11_S) +#define SOC_ETM_CH_CLR11_V 0x00000001U +#define SOC_ETM_CH_CLR11_S 11 +/** SOC_ETM_CH_CLR12 : WT; bitpos: [12]; default: 0; + * ch12 clear + */ +#define SOC_ETM_CH_CLR12 (BIT(12)) +#define SOC_ETM_CH_CLR12_M (SOC_ETM_CH_CLR12_V << SOC_ETM_CH_CLR12_S) +#define SOC_ETM_CH_CLR12_V 0x00000001U +#define SOC_ETM_CH_CLR12_S 12 +/** SOC_ETM_CH_CLR13 : WT; bitpos: [13]; default: 0; + * ch13 clear + */ +#define SOC_ETM_CH_CLR13 (BIT(13)) +#define SOC_ETM_CH_CLR13_M (SOC_ETM_CH_CLR13_V << SOC_ETM_CH_CLR13_S) +#define SOC_ETM_CH_CLR13_V 0x00000001U +#define SOC_ETM_CH_CLR13_S 13 +/** SOC_ETM_CH_CLR14 : WT; bitpos: [14]; default: 0; + * ch14 clear + */ +#define SOC_ETM_CH_CLR14 (BIT(14)) +#define SOC_ETM_CH_CLR14_M (SOC_ETM_CH_CLR14_V << SOC_ETM_CH_CLR14_S) +#define SOC_ETM_CH_CLR14_V 0x00000001U +#define SOC_ETM_CH_CLR14_S 14 +/** SOC_ETM_CH_CLR15 : WT; bitpos: [15]; default: 0; + * ch15 clear + */ +#define SOC_ETM_CH_CLR15 (BIT(15)) +#define SOC_ETM_CH_CLR15_M (SOC_ETM_CH_CLR15_V << SOC_ETM_CH_CLR15_S) +#define SOC_ETM_CH_CLR15_V 0x00000001U +#define SOC_ETM_CH_CLR15_S 15 +/** SOC_ETM_CH_CLR16 : WT; bitpos: [16]; default: 0; + * ch16 clear + */ +#define SOC_ETM_CH_CLR16 (BIT(16)) +#define SOC_ETM_CH_CLR16_M (SOC_ETM_CH_CLR16_V << SOC_ETM_CH_CLR16_S) +#define SOC_ETM_CH_CLR16_V 0x00000001U +#define SOC_ETM_CH_CLR16_S 16 +/** SOC_ETM_CH_CLR17 : WT; bitpos: [17]; default: 0; + * ch17 clear + */ +#define SOC_ETM_CH_CLR17 (BIT(17)) +#define SOC_ETM_CH_CLR17_M (SOC_ETM_CH_CLR17_V << SOC_ETM_CH_CLR17_S) +#define SOC_ETM_CH_CLR17_V 0x00000001U +#define SOC_ETM_CH_CLR17_S 17 +/** SOC_ETM_CH_CLR18 : WT; bitpos: [18]; default: 0; + * ch18 clear + */ +#define SOC_ETM_CH_CLR18 (BIT(18)) +#define SOC_ETM_CH_CLR18_M (SOC_ETM_CH_CLR18_V << SOC_ETM_CH_CLR18_S) +#define SOC_ETM_CH_CLR18_V 0x00000001U +#define SOC_ETM_CH_CLR18_S 18 +/** SOC_ETM_CH_CLR19 : WT; bitpos: [19]; default: 0; + * ch19 clear + */ +#define SOC_ETM_CH_CLR19 (BIT(19)) +#define SOC_ETM_CH_CLR19_M (SOC_ETM_CH_CLR19_V << SOC_ETM_CH_CLR19_S) +#define SOC_ETM_CH_CLR19_V 0x00000001U +#define SOC_ETM_CH_CLR19_S 19 +/** SOC_ETM_CH_CLR20 : WT; bitpos: [20]; default: 0; + * ch20 clear + */ +#define SOC_ETM_CH_CLR20 (BIT(20)) +#define SOC_ETM_CH_CLR20_M (SOC_ETM_CH_CLR20_V << SOC_ETM_CH_CLR20_S) +#define SOC_ETM_CH_CLR20_V 0x00000001U +#define SOC_ETM_CH_CLR20_S 20 +/** SOC_ETM_CH_CLR21 : WT; bitpos: [21]; default: 0; + * ch21 clear + */ +#define SOC_ETM_CH_CLR21 (BIT(21)) +#define SOC_ETM_CH_CLR21_M (SOC_ETM_CH_CLR21_V << SOC_ETM_CH_CLR21_S) +#define SOC_ETM_CH_CLR21_V 0x00000001U +#define SOC_ETM_CH_CLR21_S 21 +/** SOC_ETM_CH_CLR22 : WT; bitpos: [22]; default: 0; + * ch22 clear + */ +#define SOC_ETM_CH_CLR22 (BIT(22)) +#define SOC_ETM_CH_CLR22_M (SOC_ETM_CH_CLR22_V << SOC_ETM_CH_CLR22_S) +#define SOC_ETM_CH_CLR22_V 0x00000001U +#define SOC_ETM_CH_CLR22_S 22 +/** SOC_ETM_CH_CLR23 : WT; bitpos: [23]; default: 0; + * ch23 clear + */ +#define SOC_ETM_CH_CLR23 (BIT(23)) +#define SOC_ETM_CH_CLR23_M (SOC_ETM_CH_CLR23_V << SOC_ETM_CH_CLR23_S) +#define SOC_ETM_CH_CLR23_V 0x00000001U +#define SOC_ETM_CH_CLR23_S 23 +/** SOC_ETM_CH_CLR24 : WT; bitpos: [24]; default: 0; + * ch24 clear + */ +#define SOC_ETM_CH_CLR24 (BIT(24)) +#define SOC_ETM_CH_CLR24_M (SOC_ETM_CH_CLR24_V << SOC_ETM_CH_CLR24_S) +#define SOC_ETM_CH_CLR24_V 0x00000001U +#define SOC_ETM_CH_CLR24_S 24 +/** SOC_ETM_CH_CLR25 : WT; bitpos: [25]; default: 0; + * ch25 clear + */ +#define SOC_ETM_CH_CLR25 (BIT(25)) +#define SOC_ETM_CH_CLR25_M (SOC_ETM_CH_CLR25_V << SOC_ETM_CH_CLR25_S) +#define SOC_ETM_CH_CLR25_V 0x00000001U +#define SOC_ETM_CH_CLR25_S 25 +/** SOC_ETM_CH_CLR26 : WT; bitpos: [26]; default: 0; + * ch26 clear + */ +#define SOC_ETM_CH_CLR26 (BIT(26)) +#define SOC_ETM_CH_CLR26_M (SOC_ETM_CH_CLR26_V << SOC_ETM_CH_CLR26_S) +#define SOC_ETM_CH_CLR26_V 0x00000001U +#define SOC_ETM_CH_CLR26_S 26 +/** SOC_ETM_CH_CLR27 : WT; bitpos: [27]; default: 0; + * ch27 clear + */ +#define SOC_ETM_CH_CLR27 (BIT(27)) +#define SOC_ETM_CH_CLR27_M (SOC_ETM_CH_CLR27_V << SOC_ETM_CH_CLR27_S) +#define SOC_ETM_CH_CLR27_V 0x00000001U +#define SOC_ETM_CH_CLR27_S 27 +/** SOC_ETM_CH_CLR28 : WT; bitpos: [28]; default: 0; + * ch28 clear + */ +#define SOC_ETM_CH_CLR28 (BIT(28)) +#define SOC_ETM_CH_CLR28_M (SOC_ETM_CH_CLR28_V << SOC_ETM_CH_CLR28_S) +#define SOC_ETM_CH_CLR28_V 0x00000001U +#define SOC_ETM_CH_CLR28_S 28 +/** SOC_ETM_CH_CLR29 : WT; bitpos: [29]; default: 0; + * ch29 clear + */ +#define SOC_ETM_CH_CLR29 (BIT(29)) +#define SOC_ETM_CH_CLR29_M (SOC_ETM_CH_CLR29_V << SOC_ETM_CH_CLR29_S) +#define SOC_ETM_CH_CLR29_V 0x00000001U +#define SOC_ETM_CH_CLR29_S 29 +/** SOC_ETM_CH_CLR30 : WT; bitpos: [30]; default: 0; + * ch30 clear + */ +#define SOC_ETM_CH_CLR30 (BIT(30)) +#define SOC_ETM_CH_CLR30_M (SOC_ETM_CH_CLR30_V << SOC_ETM_CH_CLR30_S) +#define SOC_ETM_CH_CLR30_V 0x00000001U +#define SOC_ETM_CH_CLR30_S 30 +/** SOC_ETM_CH_CLR31 : WT; bitpos: [31]; default: 0; + * ch31 clear + */ +#define SOC_ETM_CH_CLR31 (BIT(31)) +#define SOC_ETM_CH_CLR31_M (SOC_ETM_CH_CLR31_V << SOC_ETM_CH_CLR31_S) +#define SOC_ETM_CH_CLR31_V 0x00000001U +#define SOC_ETM_CH_CLR31_S 31 + +/** SOC_ETM_CH_ENA_AD1_REG register + * channel enable register + */ +#define SOC_ETM_CH_ENA_AD1_REG (DR_REG_SOC_ETM_BASE + 0xc) +/** SOC_ETM_CH_ENA32 : R/WTC/WTS; bitpos: [0]; default: 0; + * ch32 enable + */ +#define SOC_ETM_CH_ENA32 (BIT(0)) +#define SOC_ETM_CH_ENA32_M (SOC_ETM_CH_ENA32_V << SOC_ETM_CH_ENA32_S) +#define SOC_ETM_CH_ENA32_V 0x00000001U +#define SOC_ETM_CH_ENA32_S 0 +/** SOC_ETM_CH_ENA33 : R/WTC/WTS; bitpos: [1]; default: 0; + * ch33 enable + */ +#define SOC_ETM_CH_ENA33 (BIT(1)) +#define SOC_ETM_CH_ENA33_M (SOC_ETM_CH_ENA33_V << SOC_ETM_CH_ENA33_S) +#define SOC_ETM_CH_ENA33_V 0x00000001U +#define SOC_ETM_CH_ENA33_S 1 +/** SOC_ETM_CH_ENA34 : R/WTC/WTS; bitpos: [2]; default: 0; + * ch34 enable + */ +#define SOC_ETM_CH_ENA34 (BIT(2)) +#define SOC_ETM_CH_ENA34_M (SOC_ETM_CH_ENA34_V << SOC_ETM_CH_ENA34_S) +#define SOC_ETM_CH_ENA34_V 0x00000001U +#define SOC_ETM_CH_ENA34_S 2 +/** SOC_ETM_CH_ENA35 : R/WTC/WTS; bitpos: [3]; default: 0; + * ch35 enable + */ +#define SOC_ETM_CH_ENA35 (BIT(3)) +#define SOC_ETM_CH_ENA35_M (SOC_ETM_CH_ENA35_V << SOC_ETM_CH_ENA35_S) +#define SOC_ETM_CH_ENA35_V 0x00000001U +#define SOC_ETM_CH_ENA35_S 3 +/** SOC_ETM_CH_ENA36 : R/WTC/WTS; bitpos: [4]; default: 0; + * ch36 enable + */ +#define SOC_ETM_CH_ENA36 (BIT(4)) +#define SOC_ETM_CH_ENA36_M (SOC_ETM_CH_ENA36_V << SOC_ETM_CH_ENA36_S) +#define SOC_ETM_CH_ENA36_V 0x00000001U +#define SOC_ETM_CH_ENA36_S 4 +/** SOC_ETM_CH_ENA37 : R/WTC/WTS; bitpos: [5]; default: 0; + * ch37 enable + */ +#define SOC_ETM_CH_ENA37 (BIT(5)) +#define SOC_ETM_CH_ENA37_M (SOC_ETM_CH_ENA37_V << SOC_ETM_CH_ENA37_S) +#define SOC_ETM_CH_ENA37_V 0x00000001U +#define SOC_ETM_CH_ENA37_S 5 +/** SOC_ETM_CH_ENA38 : R/WTC/WTS; bitpos: [6]; default: 0; + * ch38 enable + */ +#define SOC_ETM_CH_ENA38 (BIT(6)) +#define SOC_ETM_CH_ENA38_M (SOC_ETM_CH_ENA38_V << SOC_ETM_CH_ENA38_S) +#define SOC_ETM_CH_ENA38_V 0x00000001U +#define SOC_ETM_CH_ENA38_S 6 +/** SOC_ETM_CH_ENA39 : R/WTC/WTS; bitpos: [7]; default: 0; + * ch39 enable + */ +#define SOC_ETM_CH_ENA39 (BIT(7)) +#define SOC_ETM_CH_ENA39_M (SOC_ETM_CH_ENA39_V << SOC_ETM_CH_ENA39_S) +#define SOC_ETM_CH_ENA39_V 0x00000001U +#define SOC_ETM_CH_ENA39_S 7 +/** SOC_ETM_CH_ENA40 : R/WTC/WTS; bitpos: [8]; default: 0; + * ch40 enable + */ +#define SOC_ETM_CH_ENA40 (BIT(8)) +#define SOC_ETM_CH_ENA40_M (SOC_ETM_CH_ENA40_V << SOC_ETM_CH_ENA40_S) +#define SOC_ETM_CH_ENA40_V 0x00000001U +#define SOC_ETM_CH_ENA40_S 8 +/** SOC_ETM_CH_ENA41 : R/WTC/WTS; bitpos: [9]; default: 0; + * ch41 enable + */ +#define SOC_ETM_CH_ENA41 (BIT(9)) +#define SOC_ETM_CH_ENA41_M (SOC_ETM_CH_ENA41_V << SOC_ETM_CH_ENA41_S) +#define SOC_ETM_CH_ENA41_V 0x00000001U +#define SOC_ETM_CH_ENA41_S 9 +/** SOC_ETM_CH_ENA42 : R/WTC/WTS; bitpos: [10]; default: 0; + * ch42 enable + */ +#define SOC_ETM_CH_ENA42 (BIT(10)) +#define SOC_ETM_CH_ENA42_M (SOC_ETM_CH_ENA42_V << SOC_ETM_CH_ENA42_S) +#define SOC_ETM_CH_ENA42_V 0x00000001U +#define SOC_ETM_CH_ENA42_S 10 +/** SOC_ETM_CH_ENA43 : R/WTC/WTS; bitpos: [11]; default: 0; + * ch43 enable + */ +#define SOC_ETM_CH_ENA43 (BIT(11)) +#define SOC_ETM_CH_ENA43_M (SOC_ETM_CH_ENA43_V << SOC_ETM_CH_ENA43_S) +#define SOC_ETM_CH_ENA43_V 0x00000001U +#define SOC_ETM_CH_ENA43_S 11 +/** SOC_ETM_CH_ENA44 : R/WTC/WTS; bitpos: [12]; default: 0; + * ch44 enable + */ +#define SOC_ETM_CH_ENA44 (BIT(12)) +#define SOC_ETM_CH_ENA44_M (SOC_ETM_CH_ENA44_V << SOC_ETM_CH_ENA44_S) +#define SOC_ETM_CH_ENA44_V 0x00000001U +#define SOC_ETM_CH_ENA44_S 12 +/** SOC_ETM_CH_ENA45 : R/WTC/WTS; bitpos: [13]; default: 0; + * ch45 enable + */ +#define SOC_ETM_CH_ENA45 (BIT(13)) +#define SOC_ETM_CH_ENA45_M (SOC_ETM_CH_ENA45_V << SOC_ETM_CH_ENA45_S) +#define SOC_ETM_CH_ENA45_V 0x00000001U +#define SOC_ETM_CH_ENA45_S 13 +/** SOC_ETM_CH_ENA46 : R/WTC/WTS; bitpos: [14]; default: 0; + * ch46 enable + */ +#define SOC_ETM_CH_ENA46 (BIT(14)) +#define SOC_ETM_CH_ENA46_M (SOC_ETM_CH_ENA46_V << SOC_ETM_CH_ENA46_S) +#define SOC_ETM_CH_ENA46_V 0x00000001U +#define SOC_ETM_CH_ENA46_S 14 +/** SOC_ETM_CH_ENA47 : R/WTC/WTS; bitpos: [15]; default: 0; + * ch47 enable + */ +#define SOC_ETM_CH_ENA47 (BIT(15)) +#define SOC_ETM_CH_ENA47_M (SOC_ETM_CH_ENA47_V << SOC_ETM_CH_ENA47_S) +#define SOC_ETM_CH_ENA47_V 0x00000001U +#define SOC_ETM_CH_ENA47_S 15 +/** SOC_ETM_CH_ENA48 : R/WTC/WTS; bitpos: [16]; default: 0; + * ch48 enable + */ +#define SOC_ETM_CH_ENA48 (BIT(16)) +#define SOC_ETM_CH_ENA48_M (SOC_ETM_CH_ENA48_V << SOC_ETM_CH_ENA48_S) +#define SOC_ETM_CH_ENA48_V 0x00000001U +#define SOC_ETM_CH_ENA48_S 16 +/** SOC_ETM_CH_ENA49 : R/WTC/WTS; bitpos: [17]; default: 0; + * ch49 enable + */ +#define SOC_ETM_CH_ENA49 (BIT(17)) +#define SOC_ETM_CH_ENA49_M (SOC_ETM_CH_ENA49_V << SOC_ETM_CH_ENA49_S) +#define SOC_ETM_CH_ENA49_V 0x00000001U +#define SOC_ETM_CH_ENA49_S 17 + +/** SOC_ETM_CH_ENA_AD1_SET_REG register + * channel enable set register + */ +#define SOC_ETM_CH_ENA_AD1_SET_REG (DR_REG_SOC_ETM_BASE + 0x10) +/** SOC_ETM_CH_SET32 : WT; bitpos: [0]; default: 0; + * ch32 set + */ +#define SOC_ETM_CH_SET32 (BIT(0)) +#define SOC_ETM_CH_SET32_M (SOC_ETM_CH_SET32_V << SOC_ETM_CH_SET32_S) +#define SOC_ETM_CH_SET32_V 0x00000001U +#define SOC_ETM_CH_SET32_S 0 +/** SOC_ETM_CH_SET33 : WT; bitpos: [1]; default: 0; + * ch33 set + */ +#define SOC_ETM_CH_SET33 (BIT(1)) +#define SOC_ETM_CH_SET33_M (SOC_ETM_CH_SET33_V << SOC_ETM_CH_SET33_S) +#define SOC_ETM_CH_SET33_V 0x00000001U +#define SOC_ETM_CH_SET33_S 1 +/** SOC_ETM_CH_SET34 : WT; bitpos: [2]; default: 0; + * ch34 set + */ +#define SOC_ETM_CH_SET34 (BIT(2)) +#define SOC_ETM_CH_SET34_M (SOC_ETM_CH_SET34_V << SOC_ETM_CH_SET34_S) +#define SOC_ETM_CH_SET34_V 0x00000001U +#define SOC_ETM_CH_SET34_S 2 +/** SOC_ETM_CH_SET35 : WT; bitpos: [3]; default: 0; + * ch35 set + */ +#define SOC_ETM_CH_SET35 (BIT(3)) +#define SOC_ETM_CH_SET35_M (SOC_ETM_CH_SET35_V << SOC_ETM_CH_SET35_S) +#define SOC_ETM_CH_SET35_V 0x00000001U +#define SOC_ETM_CH_SET35_S 3 +/** SOC_ETM_CH_SET36 : WT; bitpos: [4]; default: 0; + * ch36 set + */ +#define SOC_ETM_CH_SET36 (BIT(4)) +#define SOC_ETM_CH_SET36_M (SOC_ETM_CH_SET36_V << SOC_ETM_CH_SET36_S) +#define SOC_ETM_CH_SET36_V 0x00000001U +#define SOC_ETM_CH_SET36_S 4 +/** SOC_ETM_CH_SET37 : WT; bitpos: [5]; default: 0; + * ch37 set + */ +#define SOC_ETM_CH_SET37 (BIT(5)) +#define SOC_ETM_CH_SET37_M (SOC_ETM_CH_SET37_V << SOC_ETM_CH_SET37_S) +#define SOC_ETM_CH_SET37_V 0x00000001U +#define SOC_ETM_CH_SET37_S 5 +/** SOC_ETM_CH_SET38 : WT; bitpos: [6]; default: 0; + * ch38 set + */ +#define SOC_ETM_CH_SET38 (BIT(6)) +#define SOC_ETM_CH_SET38_M (SOC_ETM_CH_SET38_V << SOC_ETM_CH_SET38_S) +#define SOC_ETM_CH_SET38_V 0x00000001U +#define SOC_ETM_CH_SET38_S 6 +/** SOC_ETM_CH_SET39 : WT; bitpos: [7]; default: 0; + * ch39 set + */ +#define SOC_ETM_CH_SET39 (BIT(7)) +#define SOC_ETM_CH_SET39_M (SOC_ETM_CH_SET39_V << SOC_ETM_CH_SET39_S) +#define SOC_ETM_CH_SET39_V 0x00000001U +#define SOC_ETM_CH_SET39_S 7 +/** SOC_ETM_CH_SET40 : WT; bitpos: [8]; default: 0; + * ch40 set + */ +#define SOC_ETM_CH_SET40 (BIT(8)) +#define SOC_ETM_CH_SET40_M (SOC_ETM_CH_SET40_V << SOC_ETM_CH_SET40_S) +#define SOC_ETM_CH_SET40_V 0x00000001U +#define SOC_ETM_CH_SET40_S 8 +/** SOC_ETM_CH_SET41 : WT; bitpos: [9]; default: 0; + * ch41 set + */ +#define SOC_ETM_CH_SET41 (BIT(9)) +#define SOC_ETM_CH_SET41_M (SOC_ETM_CH_SET41_V << SOC_ETM_CH_SET41_S) +#define SOC_ETM_CH_SET41_V 0x00000001U +#define SOC_ETM_CH_SET41_S 9 +/** SOC_ETM_CH_SET42 : WT; bitpos: [10]; default: 0; + * ch42 set + */ +#define SOC_ETM_CH_SET42 (BIT(10)) +#define SOC_ETM_CH_SET42_M (SOC_ETM_CH_SET42_V << SOC_ETM_CH_SET42_S) +#define SOC_ETM_CH_SET42_V 0x00000001U +#define SOC_ETM_CH_SET42_S 10 +/** SOC_ETM_CH_SET43 : WT; bitpos: [11]; default: 0; + * ch43 set + */ +#define SOC_ETM_CH_SET43 (BIT(11)) +#define SOC_ETM_CH_SET43_M (SOC_ETM_CH_SET43_V << SOC_ETM_CH_SET43_S) +#define SOC_ETM_CH_SET43_V 0x00000001U +#define SOC_ETM_CH_SET43_S 11 +/** SOC_ETM_CH_SET44 : WT; bitpos: [12]; default: 0; + * ch44 set + */ +#define SOC_ETM_CH_SET44 (BIT(12)) +#define SOC_ETM_CH_SET44_M (SOC_ETM_CH_SET44_V << SOC_ETM_CH_SET44_S) +#define SOC_ETM_CH_SET44_V 0x00000001U +#define SOC_ETM_CH_SET44_S 12 +/** SOC_ETM_CH_SET45 : WT; bitpos: [13]; default: 0; + * ch45 set + */ +#define SOC_ETM_CH_SET45 (BIT(13)) +#define SOC_ETM_CH_SET45_M (SOC_ETM_CH_SET45_V << SOC_ETM_CH_SET45_S) +#define SOC_ETM_CH_SET45_V 0x00000001U +#define SOC_ETM_CH_SET45_S 13 +/** SOC_ETM_CH_SET46 : WT; bitpos: [14]; default: 0; + * ch46 set + */ +#define SOC_ETM_CH_SET46 (BIT(14)) +#define SOC_ETM_CH_SET46_M (SOC_ETM_CH_SET46_V << SOC_ETM_CH_SET46_S) +#define SOC_ETM_CH_SET46_V 0x00000001U +#define SOC_ETM_CH_SET46_S 14 +/** SOC_ETM_CH_SET47 : WT; bitpos: [15]; default: 0; + * ch47 set + */ +#define SOC_ETM_CH_SET47 (BIT(15)) +#define SOC_ETM_CH_SET47_M (SOC_ETM_CH_SET47_V << SOC_ETM_CH_SET47_S) +#define SOC_ETM_CH_SET47_V 0x00000001U +#define SOC_ETM_CH_SET47_S 15 +/** SOC_ETM_CH_SET48 : WT; bitpos: [16]; default: 0; + * ch48 set + */ +#define SOC_ETM_CH_SET48 (BIT(16)) +#define SOC_ETM_CH_SET48_M (SOC_ETM_CH_SET48_V << SOC_ETM_CH_SET48_S) +#define SOC_ETM_CH_SET48_V 0x00000001U +#define SOC_ETM_CH_SET48_S 16 +/** SOC_ETM_CH_SET49 : WT; bitpos: [17]; default: 0; + * ch49 set + */ +#define SOC_ETM_CH_SET49 (BIT(17)) +#define SOC_ETM_CH_SET49_M (SOC_ETM_CH_SET49_V << SOC_ETM_CH_SET49_S) +#define SOC_ETM_CH_SET49_V 0x00000001U +#define SOC_ETM_CH_SET49_S 17 + +/** SOC_ETM_CH_ENA_AD1_CLR_REG register + * channel enable clear register + */ +#define SOC_ETM_CH_ENA_AD1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x14) +/** SOC_ETM_CH_CLR32 : WT; bitpos: [0]; default: 0; + * ch32 clear + */ +#define SOC_ETM_CH_CLR32 (BIT(0)) +#define SOC_ETM_CH_CLR32_M (SOC_ETM_CH_CLR32_V << SOC_ETM_CH_CLR32_S) +#define SOC_ETM_CH_CLR32_V 0x00000001U +#define SOC_ETM_CH_CLR32_S 0 +/** SOC_ETM_CH_CLR33 : WT; bitpos: [1]; default: 0; + * ch33 clear + */ +#define SOC_ETM_CH_CLR33 (BIT(1)) +#define SOC_ETM_CH_CLR33_M (SOC_ETM_CH_CLR33_V << SOC_ETM_CH_CLR33_S) +#define SOC_ETM_CH_CLR33_V 0x00000001U +#define SOC_ETM_CH_CLR33_S 1 +/** SOC_ETM_CH_CLR34 : WT; bitpos: [2]; default: 0; + * ch34 clear + */ +#define SOC_ETM_CH_CLR34 (BIT(2)) +#define SOC_ETM_CH_CLR34_M (SOC_ETM_CH_CLR34_V << SOC_ETM_CH_CLR34_S) +#define SOC_ETM_CH_CLR34_V 0x00000001U +#define SOC_ETM_CH_CLR34_S 2 +/** SOC_ETM_CH_CLR35 : WT; bitpos: [3]; default: 0; + * ch35 clear + */ +#define SOC_ETM_CH_CLR35 (BIT(3)) +#define SOC_ETM_CH_CLR35_M (SOC_ETM_CH_CLR35_V << SOC_ETM_CH_CLR35_S) +#define SOC_ETM_CH_CLR35_V 0x00000001U +#define SOC_ETM_CH_CLR35_S 3 +/** SOC_ETM_CH_CLR36 : WT; bitpos: [4]; default: 0; + * ch36 clear + */ +#define SOC_ETM_CH_CLR36 (BIT(4)) +#define SOC_ETM_CH_CLR36_M (SOC_ETM_CH_CLR36_V << SOC_ETM_CH_CLR36_S) +#define SOC_ETM_CH_CLR36_V 0x00000001U +#define SOC_ETM_CH_CLR36_S 4 +/** SOC_ETM_CH_CLR37 : WT; bitpos: [5]; default: 0; + * ch37 clear + */ +#define SOC_ETM_CH_CLR37 (BIT(5)) +#define SOC_ETM_CH_CLR37_M (SOC_ETM_CH_CLR37_V << SOC_ETM_CH_CLR37_S) +#define SOC_ETM_CH_CLR37_V 0x00000001U +#define SOC_ETM_CH_CLR37_S 5 +/** SOC_ETM_CH_CLR38 : WT; bitpos: [6]; default: 0; + * ch38 clear + */ +#define SOC_ETM_CH_CLR38 (BIT(6)) +#define SOC_ETM_CH_CLR38_M (SOC_ETM_CH_CLR38_V << SOC_ETM_CH_CLR38_S) +#define SOC_ETM_CH_CLR38_V 0x00000001U +#define SOC_ETM_CH_CLR38_S 6 +/** SOC_ETM_CH_CLR39 : WT; bitpos: [7]; default: 0; + * ch39 clear + */ +#define SOC_ETM_CH_CLR39 (BIT(7)) +#define SOC_ETM_CH_CLR39_M (SOC_ETM_CH_CLR39_V << SOC_ETM_CH_CLR39_S) +#define SOC_ETM_CH_CLR39_V 0x00000001U +#define SOC_ETM_CH_CLR39_S 7 +/** SOC_ETM_CH_CLR40 : WT; bitpos: [8]; default: 0; + * ch40 clear + */ +#define SOC_ETM_CH_CLR40 (BIT(8)) +#define SOC_ETM_CH_CLR40_M (SOC_ETM_CH_CLR40_V << SOC_ETM_CH_CLR40_S) +#define SOC_ETM_CH_CLR40_V 0x00000001U +#define SOC_ETM_CH_CLR40_S 8 +/** SOC_ETM_CH_CLR41 : WT; bitpos: [9]; default: 0; + * ch41 clear + */ +#define SOC_ETM_CH_CLR41 (BIT(9)) +#define SOC_ETM_CH_CLR41_M (SOC_ETM_CH_CLR41_V << SOC_ETM_CH_CLR41_S) +#define SOC_ETM_CH_CLR41_V 0x00000001U +#define SOC_ETM_CH_CLR41_S 9 +/** SOC_ETM_CH_CLR42 : WT; bitpos: [10]; default: 0; + * ch42 clear + */ +#define SOC_ETM_CH_CLR42 (BIT(10)) +#define SOC_ETM_CH_CLR42_M (SOC_ETM_CH_CLR42_V << SOC_ETM_CH_CLR42_S) +#define SOC_ETM_CH_CLR42_V 0x00000001U +#define SOC_ETM_CH_CLR42_S 10 +/** SOC_ETM_CH_CLR43 : WT; bitpos: [11]; default: 0; + * ch43 clear + */ +#define SOC_ETM_CH_CLR43 (BIT(11)) +#define SOC_ETM_CH_CLR43_M (SOC_ETM_CH_CLR43_V << SOC_ETM_CH_CLR43_S) +#define SOC_ETM_CH_CLR43_V 0x00000001U +#define SOC_ETM_CH_CLR43_S 11 +/** SOC_ETM_CH_CLR44 : WT; bitpos: [12]; default: 0; + * ch44 clear + */ +#define SOC_ETM_CH_CLR44 (BIT(12)) +#define SOC_ETM_CH_CLR44_M (SOC_ETM_CH_CLR44_V << SOC_ETM_CH_CLR44_S) +#define SOC_ETM_CH_CLR44_V 0x00000001U +#define SOC_ETM_CH_CLR44_S 12 +/** SOC_ETM_CH_CLR45 : WT; bitpos: [13]; default: 0; + * ch45 clear + */ +#define SOC_ETM_CH_CLR45 (BIT(13)) +#define SOC_ETM_CH_CLR45_M (SOC_ETM_CH_CLR45_V << SOC_ETM_CH_CLR45_S) +#define SOC_ETM_CH_CLR45_V 0x00000001U +#define SOC_ETM_CH_CLR45_S 13 +/** SOC_ETM_CH_CLR46 : WT; bitpos: [14]; default: 0; + * ch46 clear + */ +#define SOC_ETM_CH_CLR46 (BIT(14)) +#define SOC_ETM_CH_CLR46_M (SOC_ETM_CH_CLR46_V << SOC_ETM_CH_CLR46_S) +#define SOC_ETM_CH_CLR46_V 0x00000001U +#define SOC_ETM_CH_CLR46_S 14 +/** SOC_ETM_CH_CLR47 : WT; bitpos: [15]; default: 0; + * ch47 clear + */ +#define SOC_ETM_CH_CLR47 (BIT(15)) +#define SOC_ETM_CH_CLR47_M (SOC_ETM_CH_CLR47_V << SOC_ETM_CH_CLR47_S) +#define SOC_ETM_CH_CLR47_V 0x00000001U +#define SOC_ETM_CH_CLR47_S 15 +/** SOC_ETM_CH_CLR48 : WT; bitpos: [16]; default: 0; + * ch48 clear + */ +#define SOC_ETM_CH_CLR48 (BIT(16)) +#define SOC_ETM_CH_CLR48_M (SOC_ETM_CH_CLR48_V << SOC_ETM_CH_CLR48_S) +#define SOC_ETM_CH_CLR48_V 0x00000001U +#define SOC_ETM_CH_CLR48_S 16 +/** SOC_ETM_CH_CLR49 : WT; bitpos: [17]; default: 0; + * ch49 clear + */ +#define SOC_ETM_CH_CLR49 (BIT(17)) +#define SOC_ETM_CH_CLR49_M (SOC_ETM_CH_CLR49_V << SOC_ETM_CH_CLR49_S) +#define SOC_ETM_CH_CLR49_V 0x00000001U +#define SOC_ETM_CH_CLR49_S 17 + +/** SOC_ETM_CH0_EVT_ID_REG register + * channel0 event id register + */ +#define SOC_ETM_CH0_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x18) +/** SOC_ETM_CH0_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch0_evt_id + */ +#define SOC_ETM_CH0_EVT_ID 0x000000FFU +#define SOC_ETM_CH0_EVT_ID_M (SOC_ETM_CH0_EVT_ID_V << SOC_ETM_CH0_EVT_ID_S) +#define SOC_ETM_CH0_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH0_EVT_ID_S 0 + +/** SOC_ETM_CH0_TASK_ID_REG register + * channel0 task id register + */ +#define SOC_ETM_CH0_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1c) +/** SOC_ETM_CH0_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch0_task_id + */ +#define SOC_ETM_CH0_TASK_ID 0x000000FFU +#define SOC_ETM_CH0_TASK_ID_M (SOC_ETM_CH0_TASK_ID_V << SOC_ETM_CH0_TASK_ID_S) +#define SOC_ETM_CH0_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH0_TASK_ID_S 0 + +/** SOC_ETM_CH1_EVT_ID_REG register + * channel1 event id register + */ +#define SOC_ETM_CH1_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x20) +/** SOC_ETM_CH1_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch1_evt_id + */ +#define SOC_ETM_CH1_EVT_ID 0x000000FFU +#define SOC_ETM_CH1_EVT_ID_M (SOC_ETM_CH1_EVT_ID_V << SOC_ETM_CH1_EVT_ID_S) +#define SOC_ETM_CH1_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH1_EVT_ID_S 0 + +/** SOC_ETM_CH1_TASK_ID_REG register + * channel1 task id register + */ +#define SOC_ETM_CH1_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x24) +/** SOC_ETM_CH1_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch1_task_id + */ +#define SOC_ETM_CH1_TASK_ID 0x000000FFU +#define SOC_ETM_CH1_TASK_ID_M (SOC_ETM_CH1_TASK_ID_V << SOC_ETM_CH1_TASK_ID_S) +#define SOC_ETM_CH1_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH1_TASK_ID_S 0 + +/** SOC_ETM_CH2_EVT_ID_REG register + * channel2 event id register + */ +#define SOC_ETM_CH2_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x28) +/** SOC_ETM_CH2_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch2_evt_id + */ +#define SOC_ETM_CH2_EVT_ID 0x000000FFU +#define SOC_ETM_CH2_EVT_ID_M (SOC_ETM_CH2_EVT_ID_V << SOC_ETM_CH2_EVT_ID_S) +#define SOC_ETM_CH2_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH2_EVT_ID_S 0 + +/** SOC_ETM_CH2_TASK_ID_REG register + * channel2 task id register + */ +#define SOC_ETM_CH2_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x2c) +/** SOC_ETM_CH2_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch2_task_id + */ +#define SOC_ETM_CH2_TASK_ID 0x000000FFU +#define SOC_ETM_CH2_TASK_ID_M (SOC_ETM_CH2_TASK_ID_V << SOC_ETM_CH2_TASK_ID_S) +#define SOC_ETM_CH2_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH2_TASK_ID_S 0 + +/** SOC_ETM_CH3_EVT_ID_REG register + * channel3 event id register + */ +#define SOC_ETM_CH3_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x30) +/** SOC_ETM_CH3_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch3_evt_id + */ +#define SOC_ETM_CH3_EVT_ID 0x000000FFU +#define SOC_ETM_CH3_EVT_ID_M (SOC_ETM_CH3_EVT_ID_V << SOC_ETM_CH3_EVT_ID_S) +#define SOC_ETM_CH3_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH3_EVT_ID_S 0 + +/** SOC_ETM_CH3_TASK_ID_REG register + * channel3 task id register + */ +#define SOC_ETM_CH3_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x34) +/** SOC_ETM_CH3_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch3_task_id + */ +#define SOC_ETM_CH3_TASK_ID 0x000000FFU +#define SOC_ETM_CH3_TASK_ID_M (SOC_ETM_CH3_TASK_ID_V << SOC_ETM_CH3_TASK_ID_S) +#define SOC_ETM_CH3_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH3_TASK_ID_S 0 + +/** SOC_ETM_CH4_EVT_ID_REG register + * channel4 event id register + */ +#define SOC_ETM_CH4_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x38) +/** SOC_ETM_CH4_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch4_evt_id + */ +#define SOC_ETM_CH4_EVT_ID 0x000000FFU +#define SOC_ETM_CH4_EVT_ID_M (SOC_ETM_CH4_EVT_ID_V << SOC_ETM_CH4_EVT_ID_S) +#define SOC_ETM_CH4_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH4_EVT_ID_S 0 + +/** SOC_ETM_CH4_TASK_ID_REG register + * channel4 task id register + */ +#define SOC_ETM_CH4_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x3c) +/** SOC_ETM_CH4_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch4_task_id + */ +#define SOC_ETM_CH4_TASK_ID 0x000000FFU +#define SOC_ETM_CH4_TASK_ID_M (SOC_ETM_CH4_TASK_ID_V << SOC_ETM_CH4_TASK_ID_S) +#define SOC_ETM_CH4_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH4_TASK_ID_S 0 + +/** SOC_ETM_CH5_EVT_ID_REG register + * channel5 event id register + */ +#define SOC_ETM_CH5_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x40) +/** SOC_ETM_CH5_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch5_evt_id + */ +#define SOC_ETM_CH5_EVT_ID 0x000000FFU +#define SOC_ETM_CH5_EVT_ID_M (SOC_ETM_CH5_EVT_ID_V << SOC_ETM_CH5_EVT_ID_S) +#define SOC_ETM_CH5_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH5_EVT_ID_S 0 + +/** SOC_ETM_CH5_TASK_ID_REG register + * channel5 task id register + */ +#define SOC_ETM_CH5_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x44) +/** SOC_ETM_CH5_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch5_task_id + */ +#define SOC_ETM_CH5_TASK_ID 0x000000FFU +#define SOC_ETM_CH5_TASK_ID_M (SOC_ETM_CH5_TASK_ID_V << SOC_ETM_CH5_TASK_ID_S) +#define SOC_ETM_CH5_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH5_TASK_ID_S 0 + +/** SOC_ETM_CH6_EVT_ID_REG register + * channel6 event id register + */ +#define SOC_ETM_CH6_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x48) +/** SOC_ETM_CH6_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch6_evt_id + */ +#define SOC_ETM_CH6_EVT_ID 0x000000FFU +#define SOC_ETM_CH6_EVT_ID_M (SOC_ETM_CH6_EVT_ID_V << SOC_ETM_CH6_EVT_ID_S) +#define SOC_ETM_CH6_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH6_EVT_ID_S 0 + +/** SOC_ETM_CH6_TASK_ID_REG register + * channel6 task id register + */ +#define SOC_ETM_CH6_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x4c) +/** SOC_ETM_CH6_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch6_task_id + */ +#define SOC_ETM_CH6_TASK_ID 0x000000FFU +#define SOC_ETM_CH6_TASK_ID_M (SOC_ETM_CH6_TASK_ID_V << SOC_ETM_CH6_TASK_ID_S) +#define SOC_ETM_CH6_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH6_TASK_ID_S 0 + +/** SOC_ETM_CH7_EVT_ID_REG register + * channel7 event id register + */ +#define SOC_ETM_CH7_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x50) +/** SOC_ETM_CH7_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch7_evt_id + */ +#define SOC_ETM_CH7_EVT_ID 0x000000FFU +#define SOC_ETM_CH7_EVT_ID_M (SOC_ETM_CH7_EVT_ID_V << SOC_ETM_CH7_EVT_ID_S) +#define SOC_ETM_CH7_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH7_EVT_ID_S 0 + +/** SOC_ETM_CH7_TASK_ID_REG register + * channel7 task id register + */ +#define SOC_ETM_CH7_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x54) +/** SOC_ETM_CH7_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch7_task_id + */ +#define SOC_ETM_CH7_TASK_ID 0x000000FFU +#define SOC_ETM_CH7_TASK_ID_M (SOC_ETM_CH7_TASK_ID_V << SOC_ETM_CH7_TASK_ID_S) +#define SOC_ETM_CH7_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH7_TASK_ID_S 0 + +/** SOC_ETM_CH8_EVT_ID_REG register + * channel8 event id register + */ +#define SOC_ETM_CH8_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x58) +/** SOC_ETM_CH8_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch8_evt_id + */ +#define SOC_ETM_CH8_EVT_ID 0x000000FFU +#define SOC_ETM_CH8_EVT_ID_M (SOC_ETM_CH8_EVT_ID_V << SOC_ETM_CH8_EVT_ID_S) +#define SOC_ETM_CH8_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH8_EVT_ID_S 0 + +/** SOC_ETM_CH8_TASK_ID_REG register + * channel8 task id register + */ +#define SOC_ETM_CH8_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x5c) +/** SOC_ETM_CH8_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch8_task_id + */ +#define SOC_ETM_CH8_TASK_ID 0x000000FFU +#define SOC_ETM_CH8_TASK_ID_M (SOC_ETM_CH8_TASK_ID_V << SOC_ETM_CH8_TASK_ID_S) +#define SOC_ETM_CH8_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH8_TASK_ID_S 0 + +/** SOC_ETM_CH9_EVT_ID_REG register + * channel9 event id register + */ +#define SOC_ETM_CH9_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x60) +/** SOC_ETM_CH9_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch9_evt_id + */ +#define SOC_ETM_CH9_EVT_ID 0x000000FFU +#define SOC_ETM_CH9_EVT_ID_M (SOC_ETM_CH9_EVT_ID_V << SOC_ETM_CH9_EVT_ID_S) +#define SOC_ETM_CH9_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH9_EVT_ID_S 0 + +/** SOC_ETM_CH9_TASK_ID_REG register + * channel9 task id register + */ +#define SOC_ETM_CH9_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x64) +/** SOC_ETM_CH9_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch9_task_id + */ +#define SOC_ETM_CH9_TASK_ID 0x000000FFU +#define SOC_ETM_CH9_TASK_ID_M (SOC_ETM_CH9_TASK_ID_V << SOC_ETM_CH9_TASK_ID_S) +#define SOC_ETM_CH9_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH9_TASK_ID_S 0 + +/** SOC_ETM_CH10_EVT_ID_REG register + * channel10 event id register + */ +#define SOC_ETM_CH10_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x68) +/** SOC_ETM_CH10_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch10_evt_id + */ +#define SOC_ETM_CH10_EVT_ID 0x000000FFU +#define SOC_ETM_CH10_EVT_ID_M (SOC_ETM_CH10_EVT_ID_V << SOC_ETM_CH10_EVT_ID_S) +#define SOC_ETM_CH10_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH10_EVT_ID_S 0 + +/** SOC_ETM_CH10_TASK_ID_REG register + * channel10 task id register + */ +#define SOC_ETM_CH10_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x6c) +/** SOC_ETM_CH10_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch10_task_id + */ +#define SOC_ETM_CH10_TASK_ID 0x000000FFU +#define SOC_ETM_CH10_TASK_ID_M (SOC_ETM_CH10_TASK_ID_V << SOC_ETM_CH10_TASK_ID_S) +#define SOC_ETM_CH10_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH10_TASK_ID_S 0 + +/** SOC_ETM_CH11_EVT_ID_REG register + * channel11 event id register + */ +#define SOC_ETM_CH11_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x70) +/** SOC_ETM_CH11_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch11_evt_id + */ +#define SOC_ETM_CH11_EVT_ID 0x000000FFU +#define SOC_ETM_CH11_EVT_ID_M (SOC_ETM_CH11_EVT_ID_V << SOC_ETM_CH11_EVT_ID_S) +#define SOC_ETM_CH11_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH11_EVT_ID_S 0 + +/** SOC_ETM_CH11_TASK_ID_REG register + * channel11 task id register + */ +#define SOC_ETM_CH11_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x74) +/** SOC_ETM_CH11_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch11_task_id + */ +#define SOC_ETM_CH11_TASK_ID 0x000000FFU +#define SOC_ETM_CH11_TASK_ID_M (SOC_ETM_CH11_TASK_ID_V << SOC_ETM_CH11_TASK_ID_S) +#define SOC_ETM_CH11_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH11_TASK_ID_S 0 + +/** SOC_ETM_CH12_EVT_ID_REG register + * channel12 event id register + */ +#define SOC_ETM_CH12_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x78) +/** SOC_ETM_CH12_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch12_evt_id + */ +#define SOC_ETM_CH12_EVT_ID 0x000000FFU +#define SOC_ETM_CH12_EVT_ID_M (SOC_ETM_CH12_EVT_ID_V << SOC_ETM_CH12_EVT_ID_S) +#define SOC_ETM_CH12_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH12_EVT_ID_S 0 + +/** SOC_ETM_CH12_TASK_ID_REG register + * channel12 task id register + */ +#define SOC_ETM_CH12_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x7c) +/** SOC_ETM_CH12_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch12_task_id + */ +#define SOC_ETM_CH12_TASK_ID 0x000000FFU +#define SOC_ETM_CH12_TASK_ID_M (SOC_ETM_CH12_TASK_ID_V << SOC_ETM_CH12_TASK_ID_S) +#define SOC_ETM_CH12_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH12_TASK_ID_S 0 + +/** SOC_ETM_CH13_EVT_ID_REG register + * channel13 event id register + */ +#define SOC_ETM_CH13_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x80) +/** SOC_ETM_CH13_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch13_evt_id + */ +#define SOC_ETM_CH13_EVT_ID 0x000000FFU +#define SOC_ETM_CH13_EVT_ID_M (SOC_ETM_CH13_EVT_ID_V << SOC_ETM_CH13_EVT_ID_S) +#define SOC_ETM_CH13_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH13_EVT_ID_S 0 + +/** SOC_ETM_CH13_TASK_ID_REG register + * channel13 task id register + */ +#define SOC_ETM_CH13_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x84) +/** SOC_ETM_CH13_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch13_task_id + */ +#define SOC_ETM_CH13_TASK_ID 0x000000FFU +#define SOC_ETM_CH13_TASK_ID_M (SOC_ETM_CH13_TASK_ID_V << SOC_ETM_CH13_TASK_ID_S) +#define SOC_ETM_CH13_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH13_TASK_ID_S 0 + +/** SOC_ETM_CH14_EVT_ID_REG register + * channel14 event id register + */ +#define SOC_ETM_CH14_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x88) +/** SOC_ETM_CH14_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch14_evt_id + */ +#define SOC_ETM_CH14_EVT_ID 0x000000FFU +#define SOC_ETM_CH14_EVT_ID_M (SOC_ETM_CH14_EVT_ID_V << SOC_ETM_CH14_EVT_ID_S) +#define SOC_ETM_CH14_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH14_EVT_ID_S 0 + +/** SOC_ETM_CH14_TASK_ID_REG register + * channel14 task id register + */ +#define SOC_ETM_CH14_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x8c) +/** SOC_ETM_CH14_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch14_task_id + */ +#define SOC_ETM_CH14_TASK_ID 0x000000FFU +#define SOC_ETM_CH14_TASK_ID_M (SOC_ETM_CH14_TASK_ID_V << SOC_ETM_CH14_TASK_ID_S) +#define SOC_ETM_CH14_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH14_TASK_ID_S 0 + +/** SOC_ETM_CH15_EVT_ID_REG register + * channel15 event id register + */ +#define SOC_ETM_CH15_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x90) +/** SOC_ETM_CH15_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch15_evt_id + */ +#define SOC_ETM_CH15_EVT_ID 0x000000FFU +#define SOC_ETM_CH15_EVT_ID_M (SOC_ETM_CH15_EVT_ID_V << SOC_ETM_CH15_EVT_ID_S) +#define SOC_ETM_CH15_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH15_EVT_ID_S 0 + +/** SOC_ETM_CH15_TASK_ID_REG register + * channel15 task id register + */ +#define SOC_ETM_CH15_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x94) +/** SOC_ETM_CH15_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch15_task_id + */ +#define SOC_ETM_CH15_TASK_ID 0x000000FFU +#define SOC_ETM_CH15_TASK_ID_M (SOC_ETM_CH15_TASK_ID_V << SOC_ETM_CH15_TASK_ID_S) +#define SOC_ETM_CH15_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH15_TASK_ID_S 0 + +/** SOC_ETM_CH16_EVT_ID_REG register + * channel16 event id register + */ +#define SOC_ETM_CH16_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x98) +/** SOC_ETM_CH16_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch16_evt_id + */ +#define SOC_ETM_CH16_EVT_ID 0x000000FFU +#define SOC_ETM_CH16_EVT_ID_M (SOC_ETM_CH16_EVT_ID_V << SOC_ETM_CH16_EVT_ID_S) +#define SOC_ETM_CH16_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH16_EVT_ID_S 0 + +/** SOC_ETM_CH16_TASK_ID_REG register + * channel16 task id register + */ +#define SOC_ETM_CH16_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x9c) +/** SOC_ETM_CH16_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch16_task_id + */ +#define SOC_ETM_CH16_TASK_ID 0x000000FFU +#define SOC_ETM_CH16_TASK_ID_M (SOC_ETM_CH16_TASK_ID_V << SOC_ETM_CH16_TASK_ID_S) +#define SOC_ETM_CH16_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH16_TASK_ID_S 0 + +/** SOC_ETM_CH17_EVT_ID_REG register + * channel17 event id register + */ +#define SOC_ETM_CH17_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa0) +/** SOC_ETM_CH17_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch17_evt_id + */ +#define SOC_ETM_CH17_EVT_ID 0x000000FFU +#define SOC_ETM_CH17_EVT_ID_M (SOC_ETM_CH17_EVT_ID_V << SOC_ETM_CH17_EVT_ID_S) +#define SOC_ETM_CH17_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH17_EVT_ID_S 0 + +/** SOC_ETM_CH17_TASK_ID_REG register + * channel17 task id register + */ +#define SOC_ETM_CH17_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xa4) +/** SOC_ETM_CH17_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch17_task_id + */ +#define SOC_ETM_CH17_TASK_ID 0x000000FFU +#define SOC_ETM_CH17_TASK_ID_M (SOC_ETM_CH17_TASK_ID_V << SOC_ETM_CH17_TASK_ID_S) +#define SOC_ETM_CH17_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH17_TASK_ID_S 0 + +/** SOC_ETM_CH18_EVT_ID_REG register + * channel18 event id register + */ +#define SOC_ETM_CH18_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa8) +/** SOC_ETM_CH18_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch18_evt_id + */ +#define SOC_ETM_CH18_EVT_ID 0x000000FFU +#define SOC_ETM_CH18_EVT_ID_M (SOC_ETM_CH18_EVT_ID_V << SOC_ETM_CH18_EVT_ID_S) +#define SOC_ETM_CH18_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH18_EVT_ID_S 0 + +/** SOC_ETM_CH18_TASK_ID_REG register + * channel18 task id register + */ +#define SOC_ETM_CH18_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xac) +/** SOC_ETM_CH18_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch18_task_id + */ +#define SOC_ETM_CH18_TASK_ID 0x000000FFU +#define SOC_ETM_CH18_TASK_ID_M (SOC_ETM_CH18_TASK_ID_V << SOC_ETM_CH18_TASK_ID_S) +#define SOC_ETM_CH18_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH18_TASK_ID_S 0 + +/** SOC_ETM_CH19_EVT_ID_REG register + * channel19 event id register + */ +#define SOC_ETM_CH19_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb0) +/** SOC_ETM_CH19_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch19_evt_id + */ +#define SOC_ETM_CH19_EVT_ID 0x000000FFU +#define SOC_ETM_CH19_EVT_ID_M (SOC_ETM_CH19_EVT_ID_V << SOC_ETM_CH19_EVT_ID_S) +#define SOC_ETM_CH19_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH19_EVT_ID_S 0 + +/** SOC_ETM_CH19_TASK_ID_REG register + * channel19 task id register + */ +#define SOC_ETM_CH19_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xb4) +/** SOC_ETM_CH19_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch19_task_id + */ +#define SOC_ETM_CH19_TASK_ID 0x000000FFU +#define SOC_ETM_CH19_TASK_ID_M (SOC_ETM_CH19_TASK_ID_V << SOC_ETM_CH19_TASK_ID_S) +#define SOC_ETM_CH19_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH19_TASK_ID_S 0 + +/** SOC_ETM_CH20_EVT_ID_REG register + * channel20 event id register + */ +#define SOC_ETM_CH20_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb8) +/** SOC_ETM_CH20_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch20_evt_id + */ +#define SOC_ETM_CH20_EVT_ID 0x000000FFU +#define SOC_ETM_CH20_EVT_ID_M (SOC_ETM_CH20_EVT_ID_V << SOC_ETM_CH20_EVT_ID_S) +#define SOC_ETM_CH20_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH20_EVT_ID_S 0 + +/** SOC_ETM_CH20_TASK_ID_REG register + * channel20 task id register + */ +#define SOC_ETM_CH20_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xbc) +/** SOC_ETM_CH20_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch20_task_id + */ +#define SOC_ETM_CH20_TASK_ID 0x000000FFU +#define SOC_ETM_CH20_TASK_ID_M (SOC_ETM_CH20_TASK_ID_V << SOC_ETM_CH20_TASK_ID_S) +#define SOC_ETM_CH20_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH20_TASK_ID_S 0 + +/** SOC_ETM_CH21_EVT_ID_REG register + * channel21 event id register + */ +#define SOC_ETM_CH21_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc0) +/** SOC_ETM_CH21_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch21_evt_id + */ +#define SOC_ETM_CH21_EVT_ID 0x000000FFU +#define SOC_ETM_CH21_EVT_ID_M (SOC_ETM_CH21_EVT_ID_V << SOC_ETM_CH21_EVT_ID_S) +#define SOC_ETM_CH21_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH21_EVT_ID_S 0 + +/** SOC_ETM_CH21_TASK_ID_REG register + * channel21 task id register + */ +#define SOC_ETM_CH21_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xc4) +/** SOC_ETM_CH21_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch21_task_id + */ +#define SOC_ETM_CH21_TASK_ID 0x000000FFU +#define SOC_ETM_CH21_TASK_ID_M (SOC_ETM_CH21_TASK_ID_V << SOC_ETM_CH21_TASK_ID_S) +#define SOC_ETM_CH21_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH21_TASK_ID_S 0 + +/** SOC_ETM_CH22_EVT_ID_REG register + * channel22 event id register + */ +#define SOC_ETM_CH22_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc8) +/** SOC_ETM_CH22_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch22_evt_id + */ +#define SOC_ETM_CH22_EVT_ID 0x000000FFU +#define SOC_ETM_CH22_EVT_ID_M (SOC_ETM_CH22_EVT_ID_V << SOC_ETM_CH22_EVT_ID_S) +#define SOC_ETM_CH22_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH22_EVT_ID_S 0 + +/** SOC_ETM_CH22_TASK_ID_REG register + * channel22 task id register + */ +#define SOC_ETM_CH22_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xcc) +/** SOC_ETM_CH22_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch22_task_id + */ +#define SOC_ETM_CH22_TASK_ID 0x000000FFU +#define SOC_ETM_CH22_TASK_ID_M (SOC_ETM_CH22_TASK_ID_V << SOC_ETM_CH22_TASK_ID_S) +#define SOC_ETM_CH22_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH22_TASK_ID_S 0 + +/** SOC_ETM_CH23_EVT_ID_REG register + * channel23 event id register + */ +#define SOC_ETM_CH23_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd0) +/** SOC_ETM_CH23_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch23_evt_id + */ +#define SOC_ETM_CH23_EVT_ID 0x000000FFU +#define SOC_ETM_CH23_EVT_ID_M (SOC_ETM_CH23_EVT_ID_V << SOC_ETM_CH23_EVT_ID_S) +#define SOC_ETM_CH23_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH23_EVT_ID_S 0 + +/** SOC_ETM_CH23_TASK_ID_REG register + * channel23 task id register + */ +#define SOC_ETM_CH23_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xd4) +/** SOC_ETM_CH23_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch23_task_id + */ +#define SOC_ETM_CH23_TASK_ID 0x000000FFU +#define SOC_ETM_CH23_TASK_ID_M (SOC_ETM_CH23_TASK_ID_V << SOC_ETM_CH23_TASK_ID_S) +#define SOC_ETM_CH23_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH23_TASK_ID_S 0 + +/** SOC_ETM_CH24_EVT_ID_REG register + * channel24 event id register + */ +#define SOC_ETM_CH24_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd8) +/** SOC_ETM_CH24_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch24_evt_id + */ +#define SOC_ETM_CH24_EVT_ID 0x000000FFU +#define SOC_ETM_CH24_EVT_ID_M (SOC_ETM_CH24_EVT_ID_V << SOC_ETM_CH24_EVT_ID_S) +#define SOC_ETM_CH24_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH24_EVT_ID_S 0 + +/** SOC_ETM_CH24_TASK_ID_REG register + * channel24 task id register + */ +#define SOC_ETM_CH24_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xdc) +/** SOC_ETM_CH24_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch24_task_id + */ +#define SOC_ETM_CH24_TASK_ID 0x000000FFU +#define SOC_ETM_CH24_TASK_ID_M (SOC_ETM_CH24_TASK_ID_V << SOC_ETM_CH24_TASK_ID_S) +#define SOC_ETM_CH24_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH24_TASK_ID_S 0 + +/** SOC_ETM_CH25_EVT_ID_REG register + * channel25 event id register + */ +#define SOC_ETM_CH25_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe0) +/** SOC_ETM_CH25_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch25_evt_id + */ +#define SOC_ETM_CH25_EVT_ID 0x000000FFU +#define SOC_ETM_CH25_EVT_ID_M (SOC_ETM_CH25_EVT_ID_V << SOC_ETM_CH25_EVT_ID_S) +#define SOC_ETM_CH25_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH25_EVT_ID_S 0 + +/** SOC_ETM_CH25_TASK_ID_REG register + * channel25 task id register + */ +#define SOC_ETM_CH25_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xe4) +/** SOC_ETM_CH25_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch25_task_id + */ +#define SOC_ETM_CH25_TASK_ID 0x000000FFU +#define SOC_ETM_CH25_TASK_ID_M (SOC_ETM_CH25_TASK_ID_V << SOC_ETM_CH25_TASK_ID_S) +#define SOC_ETM_CH25_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH25_TASK_ID_S 0 + +/** SOC_ETM_CH26_EVT_ID_REG register + * channel26 event id register + */ +#define SOC_ETM_CH26_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe8) +/** SOC_ETM_CH26_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch26_evt_id + */ +#define SOC_ETM_CH26_EVT_ID 0x000000FFU +#define SOC_ETM_CH26_EVT_ID_M (SOC_ETM_CH26_EVT_ID_V << SOC_ETM_CH26_EVT_ID_S) +#define SOC_ETM_CH26_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH26_EVT_ID_S 0 + +/** SOC_ETM_CH26_TASK_ID_REG register + * channel26 task id register + */ +#define SOC_ETM_CH26_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xec) +/** SOC_ETM_CH26_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch26_task_id + */ +#define SOC_ETM_CH26_TASK_ID 0x000000FFU +#define SOC_ETM_CH26_TASK_ID_M (SOC_ETM_CH26_TASK_ID_V << SOC_ETM_CH26_TASK_ID_S) +#define SOC_ETM_CH26_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH26_TASK_ID_S 0 + +/** SOC_ETM_CH27_EVT_ID_REG register + * channel27 event id register + */ +#define SOC_ETM_CH27_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf0) +/** SOC_ETM_CH27_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch27_evt_id + */ +#define SOC_ETM_CH27_EVT_ID 0x000000FFU +#define SOC_ETM_CH27_EVT_ID_M (SOC_ETM_CH27_EVT_ID_V << SOC_ETM_CH27_EVT_ID_S) +#define SOC_ETM_CH27_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH27_EVT_ID_S 0 + +/** SOC_ETM_CH27_TASK_ID_REG register + * channel27 task id register + */ +#define SOC_ETM_CH27_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xf4) +/** SOC_ETM_CH27_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch27_task_id + */ +#define SOC_ETM_CH27_TASK_ID 0x000000FFU +#define SOC_ETM_CH27_TASK_ID_M (SOC_ETM_CH27_TASK_ID_V << SOC_ETM_CH27_TASK_ID_S) +#define SOC_ETM_CH27_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH27_TASK_ID_S 0 + +/** SOC_ETM_CH28_EVT_ID_REG register + * channel28 event id register + */ +#define SOC_ETM_CH28_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf8) +/** SOC_ETM_CH28_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch28_evt_id + */ +#define SOC_ETM_CH28_EVT_ID 0x000000FFU +#define SOC_ETM_CH28_EVT_ID_M (SOC_ETM_CH28_EVT_ID_V << SOC_ETM_CH28_EVT_ID_S) +#define SOC_ETM_CH28_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH28_EVT_ID_S 0 + +/** SOC_ETM_CH28_TASK_ID_REG register + * channel28 task id register + */ +#define SOC_ETM_CH28_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xfc) +/** SOC_ETM_CH28_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch28_task_id + */ +#define SOC_ETM_CH28_TASK_ID 0x000000FFU +#define SOC_ETM_CH28_TASK_ID_M (SOC_ETM_CH28_TASK_ID_V << SOC_ETM_CH28_TASK_ID_S) +#define SOC_ETM_CH28_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH28_TASK_ID_S 0 + +/** SOC_ETM_CH29_EVT_ID_REG register + * channel29 event id register + */ +#define SOC_ETM_CH29_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x100) +/** SOC_ETM_CH29_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch29_evt_id + */ +#define SOC_ETM_CH29_EVT_ID 0x000000FFU +#define SOC_ETM_CH29_EVT_ID_M (SOC_ETM_CH29_EVT_ID_V << SOC_ETM_CH29_EVT_ID_S) +#define SOC_ETM_CH29_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH29_EVT_ID_S 0 + +/** SOC_ETM_CH29_TASK_ID_REG register + * channel29 task id register + */ +#define SOC_ETM_CH29_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x104) +/** SOC_ETM_CH29_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch29_task_id + */ +#define SOC_ETM_CH29_TASK_ID 0x000000FFU +#define SOC_ETM_CH29_TASK_ID_M (SOC_ETM_CH29_TASK_ID_V << SOC_ETM_CH29_TASK_ID_S) +#define SOC_ETM_CH29_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH29_TASK_ID_S 0 + +/** SOC_ETM_CH30_EVT_ID_REG register + * channel30 event id register + */ +#define SOC_ETM_CH30_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x108) +/** SOC_ETM_CH30_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch30_evt_id + */ +#define SOC_ETM_CH30_EVT_ID 0x000000FFU +#define SOC_ETM_CH30_EVT_ID_M (SOC_ETM_CH30_EVT_ID_V << SOC_ETM_CH30_EVT_ID_S) +#define SOC_ETM_CH30_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH30_EVT_ID_S 0 + +/** SOC_ETM_CH30_TASK_ID_REG register + * channel30 task id register + */ +#define SOC_ETM_CH30_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x10c) +/** SOC_ETM_CH30_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch30_task_id + */ +#define SOC_ETM_CH30_TASK_ID 0x000000FFU +#define SOC_ETM_CH30_TASK_ID_M (SOC_ETM_CH30_TASK_ID_V << SOC_ETM_CH30_TASK_ID_S) +#define SOC_ETM_CH30_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH30_TASK_ID_S 0 + +/** SOC_ETM_CH31_EVT_ID_REG register + * channel31 event id register + */ +#define SOC_ETM_CH31_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x110) +/** SOC_ETM_CH31_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch31_evt_id + */ +#define SOC_ETM_CH31_EVT_ID 0x000000FFU +#define SOC_ETM_CH31_EVT_ID_M (SOC_ETM_CH31_EVT_ID_V << SOC_ETM_CH31_EVT_ID_S) +#define SOC_ETM_CH31_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH31_EVT_ID_S 0 + +/** SOC_ETM_CH31_TASK_ID_REG register + * channel31 task id register + */ +#define SOC_ETM_CH31_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x114) +/** SOC_ETM_CH31_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch31_task_id + */ +#define SOC_ETM_CH31_TASK_ID 0x000000FFU +#define SOC_ETM_CH31_TASK_ID_M (SOC_ETM_CH31_TASK_ID_V << SOC_ETM_CH31_TASK_ID_S) +#define SOC_ETM_CH31_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH31_TASK_ID_S 0 + +/** SOC_ETM_CH32_EVT_ID_REG register + * channel32 event id register + */ +#define SOC_ETM_CH32_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x118) +/** SOC_ETM_CH32_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch32_evt_id + */ +#define SOC_ETM_CH32_EVT_ID 0x000000FFU +#define SOC_ETM_CH32_EVT_ID_M (SOC_ETM_CH32_EVT_ID_V << SOC_ETM_CH32_EVT_ID_S) +#define SOC_ETM_CH32_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH32_EVT_ID_S 0 + +/** SOC_ETM_CH32_TASK_ID_REG register + * channel32 task id register + */ +#define SOC_ETM_CH32_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x11c) +/** SOC_ETM_CH32_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch32_task_id + */ +#define SOC_ETM_CH32_TASK_ID 0x000000FFU +#define SOC_ETM_CH32_TASK_ID_M (SOC_ETM_CH32_TASK_ID_V << SOC_ETM_CH32_TASK_ID_S) +#define SOC_ETM_CH32_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH32_TASK_ID_S 0 + +/** SOC_ETM_CH33_EVT_ID_REG register + * channel33 event id register + */ +#define SOC_ETM_CH33_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x120) +/** SOC_ETM_CH33_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch33_evt_id + */ +#define SOC_ETM_CH33_EVT_ID 0x000000FFU +#define SOC_ETM_CH33_EVT_ID_M (SOC_ETM_CH33_EVT_ID_V << SOC_ETM_CH33_EVT_ID_S) +#define SOC_ETM_CH33_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH33_EVT_ID_S 0 + +/** SOC_ETM_CH33_TASK_ID_REG register + * channel33 task id register + */ +#define SOC_ETM_CH33_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x124) +/** SOC_ETM_CH33_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch33_task_id + */ +#define SOC_ETM_CH33_TASK_ID 0x000000FFU +#define SOC_ETM_CH33_TASK_ID_M (SOC_ETM_CH33_TASK_ID_V << SOC_ETM_CH33_TASK_ID_S) +#define SOC_ETM_CH33_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH33_TASK_ID_S 0 + +/** SOC_ETM_CH34_EVT_ID_REG register + * channel34 event id register + */ +#define SOC_ETM_CH34_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x128) +/** SOC_ETM_CH34_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch34_evt_id + */ +#define SOC_ETM_CH34_EVT_ID 0x000000FFU +#define SOC_ETM_CH34_EVT_ID_M (SOC_ETM_CH34_EVT_ID_V << SOC_ETM_CH34_EVT_ID_S) +#define SOC_ETM_CH34_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH34_EVT_ID_S 0 + +/** SOC_ETM_CH34_TASK_ID_REG register + * channel34 task id register + */ +#define SOC_ETM_CH34_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x12c) +/** SOC_ETM_CH34_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch34_task_id + */ +#define SOC_ETM_CH34_TASK_ID 0x000000FFU +#define SOC_ETM_CH34_TASK_ID_M (SOC_ETM_CH34_TASK_ID_V << SOC_ETM_CH34_TASK_ID_S) +#define SOC_ETM_CH34_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH34_TASK_ID_S 0 + +/** SOC_ETM_CH35_EVT_ID_REG register + * channel35 event id register + */ +#define SOC_ETM_CH35_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x130) +/** SOC_ETM_CH35_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch35_evt_id + */ +#define SOC_ETM_CH35_EVT_ID 0x000000FFU +#define SOC_ETM_CH35_EVT_ID_M (SOC_ETM_CH35_EVT_ID_V << SOC_ETM_CH35_EVT_ID_S) +#define SOC_ETM_CH35_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH35_EVT_ID_S 0 + +/** SOC_ETM_CH35_TASK_ID_REG register + * channel35 task id register + */ +#define SOC_ETM_CH35_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x134) +/** SOC_ETM_CH35_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch35_task_id + */ +#define SOC_ETM_CH35_TASK_ID 0x000000FFU +#define SOC_ETM_CH35_TASK_ID_M (SOC_ETM_CH35_TASK_ID_V << SOC_ETM_CH35_TASK_ID_S) +#define SOC_ETM_CH35_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH35_TASK_ID_S 0 + +/** SOC_ETM_CH36_EVT_ID_REG register + * channel36 event id register + */ +#define SOC_ETM_CH36_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x138) +/** SOC_ETM_CH36_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch36_evt_id + */ +#define SOC_ETM_CH36_EVT_ID 0x000000FFU +#define SOC_ETM_CH36_EVT_ID_M (SOC_ETM_CH36_EVT_ID_V << SOC_ETM_CH36_EVT_ID_S) +#define SOC_ETM_CH36_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH36_EVT_ID_S 0 + +/** SOC_ETM_CH36_TASK_ID_REG register + * channel36 task id register + */ +#define SOC_ETM_CH36_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x13c) +/** SOC_ETM_CH36_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch36_task_id + */ +#define SOC_ETM_CH36_TASK_ID 0x000000FFU +#define SOC_ETM_CH36_TASK_ID_M (SOC_ETM_CH36_TASK_ID_V << SOC_ETM_CH36_TASK_ID_S) +#define SOC_ETM_CH36_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH36_TASK_ID_S 0 + +/** SOC_ETM_CH37_EVT_ID_REG register + * channel37 event id register + */ +#define SOC_ETM_CH37_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x140) +/** SOC_ETM_CH37_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch37_evt_id + */ +#define SOC_ETM_CH37_EVT_ID 0x000000FFU +#define SOC_ETM_CH37_EVT_ID_M (SOC_ETM_CH37_EVT_ID_V << SOC_ETM_CH37_EVT_ID_S) +#define SOC_ETM_CH37_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH37_EVT_ID_S 0 + +/** SOC_ETM_CH37_TASK_ID_REG register + * channel37 task id register + */ +#define SOC_ETM_CH37_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x144) +/** SOC_ETM_CH37_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch37_task_id + */ +#define SOC_ETM_CH37_TASK_ID 0x000000FFU +#define SOC_ETM_CH37_TASK_ID_M (SOC_ETM_CH37_TASK_ID_V << SOC_ETM_CH37_TASK_ID_S) +#define SOC_ETM_CH37_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH37_TASK_ID_S 0 + +/** SOC_ETM_CH38_EVT_ID_REG register + * channel38 event id register + */ +#define SOC_ETM_CH38_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x148) +/** SOC_ETM_CH38_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch38_evt_id + */ +#define SOC_ETM_CH38_EVT_ID 0x000000FFU +#define SOC_ETM_CH38_EVT_ID_M (SOC_ETM_CH38_EVT_ID_V << SOC_ETM_CH38_EVT_ID_S) +#define SOC_ETM_CH38_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH38_EVT_ID_S 0 + +/** SOC_ETM_CH38_TASK_ID_REG register + * channel38 task id register + */ +#define SOC_ETM_CH38_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x14c) +/** SOC_ETM_CH38_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch38_task_id + */ +#define SOC_ETM_CH38_TASK_ID 0x000000FFU +#define SOC_ETM_CH38_TASK_ID_M (SOC_ETM_CH38_TASK_ID_V << SOC_ETM_CH38_TASK_ID_S) +#define SOC_ETM_CH38_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH38_TASK_ID_S 0 + +/** SOC_ETM_CH39_EVT_ID_REG register + * channel39 event id register + */ +#define SOC_ETM_CH39_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x150) +/** SOC_ETM_CH39_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch39_evt_id + */ +#define SOC_ETM_CH39_EVT_ID 0x000000FFU +#define SOC_ETM_CH39_EVT_ID_M (SOC_ETM_CH39_EVT_ID_V << SOC_ETM_CH39_EVT_ID_S) +#define SOC_ETM_CH39_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH39_EVT_ID_S 0 + +/** SOC_ETM_CH39_TASK_ID_REG register + * channel39 task id register + */ +#define SOC_ETM_CH39_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x154) +/** SOC_ETM_CH39_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch39_task_id + */ +#define SOC_ETM_CH39_TASK_ID 0x000000FFU +#define SOC_ETM_CH39_TASK_ID_M (SOC_ETM_CH39_TASK_ID_V << SOC_ETM_CH39_TASK_ID_S) +#define SOC_ETM_CH39_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH39_TASK_ID_S 0 + +/** SOC_ETM_CH40_EVT_ID_REG register + * channel40 event id register + */ +#define SOC_ETM_CH40_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x158) +/** SOC_ETM_CH40_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch40_evt_id + */ +#define SOC_ETM_CH40_EVT_ID 0x000000FFU +#define SOC_ETM_CH40_EVT_ID_M (SOC_ETM_CH40_EVT_ID_V << SOC_ETM_CH40_EVT_ID_S) +#define SOC_ETM_CH40_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH40_EVT_ID_S 0 + +/** SOC_ETM_CH40_TASK_ID_REG register + * channel40 task id register + */ +#define SOC_ETM_CH40_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x15c) +/** SOC_ETM_CH40_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch40_task_id + */ +#define SOC_ETM_CH40_TASK_ID 0x000000FFU +#define SOC_ETM_CH40_TASK_ID_M (SOC_ETM_CH40_TASK_ID_V << SOC_ETM_CH40_TASK_ID_S) +#define SOC_ETM_CH40_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH40_TASK_ID_S 0 + +/** SOC_ETM_CH41_EVT_ID_REG register + * channel41 event id register + */ +#define SOC_ETM_CH41_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x160) +/** SOC_ETM_CH41_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch41_evt_id + */ +#define SOC_ETM_CH41_EVT_ID 0x000000FFU +#define SOC_ETM_CH41_EVT_ID_M (SOC_ETM_CH41_EVT_ID_V << SOC_ETM_CH41_EVT_ID_S) +#define SOC_ETM_CH41_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH41_EVT_ID_S 0 + +/** SOC_ETM_CH41_TASK_ID_REG register + * channel41 task id register + */ +#define SOC_ETM_CH41_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x164) +/** SOC_ETM_CH41_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch41_task_id + */ +#define SOC_ETM_CH41_TASK_ID 0x000000FFU +#define SOC_ETM_CH41_TASK_ID_M (SOC_ETM_CH41_TASK_ID_V << SOC_ETM_CH41_TASK_ID_S) +#define SOC_ETM_CH41_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH41_TASK_ID_S 0 + +/** SOC_ETM_CH42_EVT_ID_REG register + * channel42 event id register + */ +#define SOC_ETM_CH42_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x168) +/** SOC_ETM_CH42_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch42_evt_id + */ +#define SOC_ETM_CH42_EVT_ID 0x000000FFU +#define SOC_ETM_CH42_EVT_ID_M (SOC_ETM_CH42_EVT_ID_V << SOC_ETM_CH42_EVT_ID_S) +#define SOC_ETM_CH42_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH42_EVT_ID_S 0 + +/** SOC_ETM_CH42_TASK_ID_REG register + * channel42 task id register + */ +#define SOC_ETM_CH42_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x16c) +/** SOC_ETM_CH42_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch42_task_id + */ +#define SOC_ETM_CH42_TASK_ID 0x000000FFU +#define SOC_ETM_CH42_TASK_ID_M (SOC_ETM_CH42_TASK_ID_V << SOC_ETM_CH42_TASK_ID_S) +#define SOC_ETM_CH42_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH42_TASK_ID_S 0 + +/** SOC_ETM_CH43_EVT_ID_REG register + * channel43 event id register + */ +#define SOC_ETM_CH43_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x170) +/** SOC_ETM_CH43_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch43_evt_id + */ +#define SOC_ETM_CH43_EVT_ID 0x000000FFU +#define SOC_ETM_CH43_EVT_ID_M (SOC_ETM_CH43_EVT_ID_V << SOC_ETM_CH43_EVT_ID_S) +#define SOC_ETM_CH43_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH43_EVT_ID_S 0 + +/** SOC_ETM_CH43_TASK_ID_REG register + * channel43 task id register + */ +#define SOC_ETM_CH43_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x174) +/** SOC_ETM_CH43_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch43_task_id + */ +#define SOC_ETM_CH43_TASK_ID 0x000000FFU +#define SOC_ETM_CH43_TASK_ID_M (SOC_ETM_CH43_TASK_ID_V << SOC_ETM_CH43_TASK_ID_S) +#define SOC_ETM_CH43_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH43_TASK_ID_S 0 + +/** SOC_ETM_CH44_EVT_ID_REG register + * channel44 event id register + */ +#define SOC_ETM_CH44_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x178) +/** SOC_ETM_CH44_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch44_evt_id + */ +#define SOC_ETM_CH44_EVT_ID 0x000000FFU +#define SOC_ETM_CH44_EVT_ID_M (SOC_ETM_CH44_EVT_ID_V << SOC_ETM_CH44_EVT_ID_S) +#define SOC_ETM_CH44_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH44_EVT_ID_S 0 + +/** SOC_ETM_CH44_TASK_ID_REG register + * channel44 task id register + */ +#define SOC_ETM_CH44_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x17c) +/** SOC_ETM_CH44_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch44_task_id + */ +#define SOC_ETM_CH44_TASK_ID 0x000000FFU +#define SOC_ETM_CH44_TASK_ID_M (SOC_ETM_CH44_TASK_ID_V << SOC_ETM_CH44_TASK_ID_S) +#define SOC_ETM_CH44_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH44_TASK_ID_S 0 + +/** SOC_ETM_CH45_EVT_ID_REG register + * channel45 event id register + */ +#define SOC_ETM_CH45_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x180) +/** SOC_ETM_CH45_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch45_evt_id + */ +#define SOC_ETM_CH45_EVT_ID 0x000000FFU +#define SOC_ETM_CH45_EVT_ID_M (SOC_ETM_CH45_EVT_ID_V << SOC_ETM_CH45_EVT_ID_S) +#define SOC_ETM_CH45_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH45_EVT_ID_S 0 + +/** SOC_ETM_CH45_TASK_ID_REG register + * channel45 task id register + */ +#define SOC_ETM_CH45_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x184) +/** SOC_ETM_CH45_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch45_task_id + */ +#define SOC_ETM_CH45_TASK_ID 0x000000FFU +#define SOC_ETM_CH45_TASK_ID_M (SOC_ETM_CH45_TASK_ID_V << SOC_ETM_CH45_TASK_ID_S) +#define SOC_ETM_CH45_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH45_TASK_ID_S 0 + +/** SOC_ETM_CH46_EVT_ID_REG register + * channel46 event id register + */ +#define SOC_ETM_CH46_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x188) +/** SOC_ETM_CH46_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch46_evt_id + */ +#define SOC_ETM_CH46_EVT_ID 0x000000FFU +#define SOC_ETM_CH46_EVT_ID_M (SOC_ETM_CH46_EVT_ID_V << SOC_ETM_CH46_EVT_ID_S) +#define SOC_ETM_CH46_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH46_EVT_ID_S 0 + +/** SOC_ETM_CH46_TASK_ID_REG register + * channel46 task id register + */ +#define SOC_ETM_CH46_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x18c) +/** SOC_ETM_CH46_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch46_task_id + */ +#define SOC_ETM_CH46_TASK_ID 0x000000FFU +#define SOC_ETM_CH46_TASK_ID_M (SOC_ETM_CH46_TASK_ID_V << SOC_ETM_CH46_TASK_ID_S) +#define SOC_ETM_CH46_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH46_TASK_ID_S 0 + +/** SOC_ETM_CH47_EVT_ID_REG register + * channel47 event id register + */ +#define SOC_ETM_CH47_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x190) +/** SOC_ETM_CH47_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch47_evt_id + */ +#define SOC_ETM_CH47_EVT_ID 0x000000FFU +#define SOC_ETM_CH47_EVT_ID_M (SOC_ETM_CH47_EVT_ID_V << SOC_ETM_CH47_EVT_ID_S) +#define SOC_ETM_CH47_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH47_EVT_ID_S 0 + +/** SOC_ETM_CH47_TASK_ID_REG register + * channel47 task id register + */ +#define SOC_ETM_CH47_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x194) +/** SOC_ETM_CH47_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch47_task_id + */ +#define SOC_ETM_CH47_TASK_ID 0x000000FFU +#define SOC_ETM_CH47_TASK_ID_M (SOC_ETM_CH47_TASK_ID_V << SOC_ETM_CH47_TASK_ID_S) +#define SOC_ETM_CH47_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH47_TASK_ID_S 0 + +/** SOC_ETM_CH48_EVT_ID_REG register + * channel48 event id register + */ +#define SOC_ETM_CH48_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x198) +/** SOC_ETM_CH48_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch48_evt_id + */ +#define SOC_ETM_CH48_EVT_ID 0x000000FFU +#define SOC_ETM_CH48_EVT_ID_M (SOC_ETM_CH48_EVT_ID_V << SOC_ETM_CH48_EVT_ID_S) +#define SOC_ETM_CH48_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH48_EVT_ID_S 0 + +/** SOC_ETM_CH48_TASK_ID_REG register + * channel48 task id register + */ +#define SOC_ETM_CH48_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x19c) +/** SOC_ETM_CH48_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch48_task_id + */ +#define SOC_ETM_CH48_TASK_ID 0x000000FFU +#define SOC_ETM_CH48_TASK_ID_M (SOC_ETM_CH48_TASK_ID_V << SOC_ETM_CH48_TASK_ID_S) +#define SOC_ETM_CH48_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH48_TASK_ID_S 0 + +/** SOC_ETM_CH49_EVT_ID_REG register + * channel49 event id register + */ +#define SOC_ETM_CH49_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a0) +/** SOC_ETM_CH49_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * ch49_evt_id + */ +#define SOC_ETM_CH49_EVT_ID 0x000000FFU +#define SOC_ETM_CH49_EVT_ID_M (SOC_ETM_CH49_EVT_ID_V << SOC_ETM_CH49_EVT_ID_S) +#define SOC_ETM_CH49_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH49_EVT_ID_S 0 + +/** SOC_ETM_CH49_TASK_ID_REG register + * channel49 task id register + */ +#define SOC_ETM_CH49_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a4) +/** SOC_ETM_CH49_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * ch49_task_id + */ +#define SOC_ETM_CH49_TASK_ID 0x000000FFU +#define SOC_ETM_CH49_TASK_ID_M (SOC_ETM_CH49_TASK_ID_V << SOC_ETM_CH49_TASK_ID_S) +#define SOC_ETM_CH49_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH49_TASK_ID_S 0 + +/** SOC_ETM_CLK_EN_REG register + * etm clock enable register + */ +#define SOC_ETM_CLK_EN_REG (DR_REG_SOC_ETM_BASE + 0x1a8) +/** SOC_ETM_CLK_EN : R/W; bitpos: [0]; default: 0; + * clock enable + */ +#define SOC_ETM_CLK_EN (BIT(0)) +#define SOC_ETM_CLK_EN_M (SOC_ETM_CLK_EN_V << SOC_ETM_CLK_EN_S) +#define SOC_ETM_CLK_EN_V 0x00000001U +#define SOC_ETM_CLK_EN_S 0 + +/** SOC_ETM_DATE_REG register + * etm date register + */ +#define SOC_ETM_DATE_REG (DR_REG_SOC_ETM_BASE + 0x1ac) +/** SOC_ETM_DATE : R/W; bitpos: [27:0]; default: 35664018; + * date + */ +#define SOC_ETM_DATE 0x0FFFFFFFU +#define SOC_ETM_DATE_M (SOC_ETM_DATE_V << SOC_ETM_DATE_S) +#define SOC_ETM_DATE_V 0x0FFFFFFFU +#define SOC_ETM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/soc_etm_source.h b/components/soc/esp32c6/include/soc/soc_etm_source.h new file mode 100644 index 0000000000..9ecde2c030 --- /dev/null +++ b/components/soc/esp32c6/include/soc/soc_etm_source.h @@ -0,0 +1,337 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#define GPIO_EVT_CH0_RISE_EDGE 1 +#define GPIO_EVT_CH1_RISE_EDGE 2 +#define GPIO_EVT_CH2_RISE_EDGE 3 +#define GPIO_EVT_CH3_RISE_EDGE 4 +#define GPIO_EVT_CH4_RISE_EDGE 5 +#define GPIO_EVT_CH5_RISE_EDGE 6 +#define GPIO_EVT_CH6_RISE_EDGE 7 +#define GPIO_EVT_CH7_RISE_EDGE 8 +#define GPIO_EVT_CH0_FALL_EDGE 9 +#define GPIO_EVT_CH1_FALL_EDGE 10 +#define GPIO_EVT_CH2_FALL_EDGE 11 +#define GPIO_EVT_CH3_FALL_EDGE 12 +#define GPIO_EVT_CH4_FALL_EDGE 13 +#define GPIO_EVT_CH5_FALL_EDGE 14 +#define GPIO_EVT_CH6_FALL_EDGE 15 +#define GPIO_EVT_CH7_FALL_EDGE 16 +#define GPIO_EVT_CH0_ANY_EDGE 17 +#define GPIO_EVT_CH1_ANY_EDGE 18 +#define GPIO_EVT_CH2_ANY_EDGE 19 +#define GPIO_EVT_CH3_ANY_EDGE 20 +#define GPIO_EVT_CH4_ANY_EDGE 21 +#define GPIO_EVT_CH5_ANY_EDGE 22 +#define GPIO_EVT_CH6_ANY_EDGE 23 +#define GPIO_EVT_CH7_ANY_EDGE 24 +#define LEDC_EVT_DUTY_CHNG_END_CH0 25 +#define LEDC_EVT_DUTY_CHNG_END_CH1 26 +#define LEDC_EVT_DUTY_CHNG_END_CH2 27 +#define LEDC_EVT_DUTY_CHNG_END_CH3 28 +#define LEDC_EVT_DUTY_CHNG_END_CH4 29 +#define LEDC_EVT_DUTY_CHNG_END_CH5 30 +#define LEDC_EVT_OVF_CNT_PLS_CH0 31 +#define LEDC_EVT_OVF_CNT_PLS_CH1 32 +#define LEDC_EVT_OVF_CNT_PLS_CH2 33 +#define LEDC_EVT_OVF_CNT_PLS_CH3 34 +#define LEDC_EVT_OVF_CNT_PLS_CH4 35 +#define LEDC_EVT_OVF_CNT_PLS_CH5 36 +#define LEDC_EVT_TIME_OVF_TIMER0 37 +#define LEDC_EVT_TIME_OVF_TIMER1 38 +#define LEDC_EVT_TIME_OVF_TIMER2 39 +#define LEDC_EVT_TIME_OVF_TIMER3 40 +#define LEDC_EVT_TIMER0_CMP 41 +#define LEDC_EVT_TIMER1_CMP 42 +#define LEDC_EVT_TIMER2_CMP 43 +#define LEDC_EVT_TIMER3_CMP 44 +#define PCNT_EVT_CNT_EQ_THRESH 45 +#define PCNT_EVT_CNT_EQ_LMT 46 +#define PCNT_EVT_CNT_EQ_ZERO 47 +#define TIMER0_EVT_CNT_CMP_TIMER0 48 +#define TIMER1_EVT_CNT_CMP_TIMER0 49 +#define SYSTIMER_EVT_CNT_CMP0 50 +#define SYSTIMER_EVT_CNT_CMP1 51 +#define SYSTIMER_EVT_CNT_CMP2 52 +#define RMT_EVT_TX_END 53 +#define RMT_EVT_TX_LOOP 54 +#define RMT_EVT_RX_END 55 +#define RMT_EVT_TX_THRESH 56 +#define RMT_EVT_RX_THRESH 57 +#define MCPWM_EVT_TIMER0_STOP 58 +#define MCPWM_EVT_TIMER1_STOP 59 +#define MCPWM_EVT_TIMER2_STOP 60 +#define MCPWM_EVT_TIMER0_TEZ 61 +#define MCPWM_EVT_TIMER1_TEZ 62 +#define MCPWM_EVT_TIMER2_TEZ 63 +#define MCPWM_EVT_TIMER0_TEP 64 +#define MCPWM_EVT_TIMER1_TEP 65 +#define MCPWM_EVT_TIMER2_TEP 66 +#define MCPWM_EVT_OP0_TEA 67 +#define MCPWM_EVT_OP1_TEA 68 +#define MCPWM_EVT_OP2_TEA 69 +#define MCPWM_EVT_OP0_TEB 70 +#define MCPWM_EVT_OP1_TEB 71 +#define MCPWM_EVT_OP2_TEB 72 +#define MCPWM_EVT_F0 73 +#define MCPWM_EVT_F1 74 +#define MCPWM_EVT_F2 75 +#define MCPWM_EVT_F0_CLR 76 +#define MCPWM_EVT_F1_CLR 77 +#define MCPWM_EVT_F2_CLR 78 +#define MCPWM_EVT_TZ0_CBC 79 +#define MCPWM_EVT_TZ1_CBC 80 +#define MCPWM_EVT_TZ2_CBC 81 +#define MCPWM_EVT_TZ0_OST 82 +#define MCPWM_EVT_TZ1_OST 83 +#define MCPWM_EVT_TZ2_OST 84 +#define MCPWM_EVT_CAP0 85 +#define MCPWM_EVT_CAP1 86 +#define MCPWM_EVT_CAP2 87 +#define ADC_EVT_CONV_CMPLT0 88 +#define ADC_EVT_EQ_ABOVE_THRESH0 89 +#define ADC_EVT_EQ_ABOVE_THRESH1 90 +#define ADC_EVT_EQ_BELOW_THRESH0 91 +#define ADC_EVT_EQ_BELOW_THRESH1 92 +#define ADC_EVT_RESULT_DONE0 93 +#define ADC_EVT_STOPPED0 94 +#define ADC_EVT_STARTED0 95 +#define REGDMA_EVT_DONE0 96 +#define REGDMA_EVT_DONE1 97 +#define REGDMA_EVT_DONE2 98 +#define REGDMA_EVT_DONE3 99 +#define REGDMA_EVT_ERR0 100 +#define REGDMA_EVT_ERR1 101 +#define REGDMA_EVT_ERR2 102 +#define REGDMA_EVT_ERR3 103 +#define PDMA_EVT_TX_DONE 104 +#define PDMA_EVT_OUT_EOF 105 +#define PDMA_EVT_IN_SUC_EOF 106 +#define PDMA_EVT_FULL_OR_EMPTY 107 +#define PDMA_EVT_ALL_DONE 108 +#define PDMA_EVT_RX_DONE 109 +#define TMPSNSR_EVT_OVER_LIMIT 110 +#define UART_EVT_REC_DATA_OVF0 111 +#define UART_EVT_REC_DATA_OVF1 112 +#define UART_EVT_TX_DONE0 113 +#define UART_EVT_TX_DONE1 114 +#define UART_EVT_TIMEOUT0 115 +#define UART_EVT_TIMEOUT1 116 +#define UART_EVT_ERR0 117 +#define UART_EVT_ERR1 118 +#define UART_EVT_CTS0 119 +#define UART_EVT_CTS1 120 +#define UART_EVT_TX_EMPTY0 121 +#define UART_EVT_TX_EMPTY1 122 +#define UART_EVT_AT_PATTERNS0 123 +#define UART_EVT_AT_PATTERNS1 124 +#define SPI_EVT_STOPPED 125 +#define I2S_EVT_RX_DONE 126 +#define I2S_EVT_TX_DONE 127 +#define I2S_EVT_X_WORDS_RECEIVED 128 +#define I2S_EVT_X_WORDS_SENT 129 +#define I2C_EVT_TRANS_DONE 130 +#define LCDCAM_EVT_TRANS_DONE 131 +#define CAN_EVT_TRANS_DONE 132 +#define ULP_EVT_ERR_INTR 133 +#define ULP_EVT_START_INTR 134 +#define RTC_EVT_TICK 135 +#define RTC_EVT_OVF 136 +#define RTC_EVT_CMP 137 +#define GDMA_EVT_IN_DONE_CH0 138 +#define GDMA_EVT_IN_DONE_CH1 139 +#define GDMA_EVT_IN_DONE_CH2 140 +#define GDMA_EVT_IN_SUC_EOF_CH0 141 +#define GDMA_EVT_IN_SUC_EOF_CH1 142 +#define GDMA_EVT_IN_SUC_EOF_CH2 143 +#define GDMA_EVT_IN_FIFO_EMPTY_CH0 144 +#define GDMA_EVT_IN_FIFO_EMPTY_CH1 145 +#define GDMA_EVT_IN_FIFO_EMPTY_CH2 146 +#define GDMA_EVT_IN_FIFO_FULL_CH0 147 +#define GDMA_EVT_IN_FIFO_FULL_CH1 148 +#define GDMA_EVT_IN_FIFO_FULL_CH2 149 +#define GDMA_EVT_OUT_DONE_CH0 150 +#define GDMA_EVT_OUT_DONE_CH1 151 +#define GDMA_EVT_OUT_DONE_CH2 152 +#define GDMA_EVT_OUT_EOF_CH0 153 +#define GDMA_EVT_OUT_EOF_CH1 154 +#define GDMA_EVT_OUT_EOF_CH2 155 +#define GDMA_EVT_OUT_TOTAL_EOF_CH0 156 +#define GDMA_EVT_OUT_TOTAL_EOF_CH1 157 +#define GDMA_EVT_OUT_TOTAL_EOF_CH2 158 +#define GDMA_EVT_OUT_FIFO_EMPTY_CH0 159 +#define GDMA_EVT_OUT_FIFO_EMPTY_CH1 160 +#define GDMA_EVT_OUT_FIFO_EMPTY_CH2 161 +#define GDMA_EVT_OUT_FIFO_FULL_CH0 162 +#define GDMA_EVT_OUT_FIFO_FULL_CH1 163 +#define GDMA_EVT_OUT_FIFO_FULL_CH2 164 +#define PMU_EVT_SLEEP_WEEKUP 165 +#define GPIO_TASK_CH0_SET 1 +#define GPIO_TASK_CH1_SET 2 +#define GPIO_TASK_CH2_SET 3 +#define GPIO_TASK_CH3_SET 4 +#define GPIO_TASK_CH4_SET 5 +#define GPIO_TASK_CH5_SET 6 +#define GPIO_TASK_CH6_SET 7 +#define GPIO_TASK_CH7_SET 8 +#define GPIO_TASK_CH0_CLEAR 9 +#define GPIO_TASK_CH1_CLEAR 10 +#define GPIO_TASK_CH2_CLEAR 11 +#define GPIO_TASK_CH3_CLEAR 12 +#define GPIO_TASK_CH4_CLEAR 13 +#define GPIO_TASK_CH5_CLEAR 14 +#define GPIO_TASK_CH6_CLEAR 15 +#define GPIO_TASK_CH7_CLEAR 16 +#define GPIO_TASK_CH0_TOGGLE 17 +#define GPIO_TASK_CH1_TOGGLE 18 +#define GPIO_TASK_CH2_TOGGLE 19 +#define GPIO_TASK_CH3_TOGGLE 20 +#define GPIO_TASK_CH4_TOGGLE 21 +#define GPIO_TASK_CH5_TOGGLE 22 +#define GPIO_TASK_CH6_TOGGLE 23 +#define GPIO_TASK_CH7_TOGGLE 24 +#define LEDC_TASK_TIMER0_RES_UPDATE 25 +#define LEDC_TASK_TIMER1_RES_UPDATE 26 +#define LEDC_TASK_TIMER2_RES_UPDATE 27 +#define LEDC_TASK_TIMER3_RES_UPDATE 28 +#define LEDC_TASK_RESERVED0 29 +#define LEDC_TASK_RESERVED1 30 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0 31 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1 32 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2 33 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3 34 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4 35 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5 36 +#define LEDC_TASK_TIMER0_CAP 37 +#define LEDC_TASK_TIMER1_CAP 38 +#define LEDC_TASK_TIMER2_CAP 39 +#define LEDC_TASK_TIMER3_CAP 40 +#define LEDC_TASK_SIG_OUT_DIS_CH0 41 +#define LEDC_TASK_SIG_OUT_DIS_CH1 42 +#define LEDC_TASK_SIG_OUT_DIS_CH2 43 +#define LEDC_TASK_SIG_OUT_DIS_CH3 44 +#define LEDC_TASK_SIG_OUT_DIS_CH4 45 +#define LEDC_TASK_SIG_OUT_DIS_CH5 46 +#define LEDC_TASK_OVF_CNT_RST_CH0 47 +#define LEDC_TASK_OVF_CNT_RST_CH1 48 +#define LEDC_TASK_OVF_CNT_RST_CH2 49 +#define LEDC_TASK_OVF_CNT_RST_CH3 50 +#define LEDC_TASK_OVF_CNT_RST_CH4 51 +#define LEDC_TASK_OVF_CNT_RST_CH5 52 +#define LEDC_TASK_TIMER0_RST 53 +#define LEDC_TASK_TIMER1_RST 54 +#define LEDC_TASK_TIMER2_RST 55 +#define LEDC_TASK_TIMER3_RST 56 +#define LEDC_TASK_TIMER0_RESUME 57 +#define LEDC_TASK_TIMER1_RESUME 58 +#define LEDC_TASK_TIMER2_RESUME 59 +#define LEDC_TASK_TIMER3_RESUME 60 +#define LEDC_TASK_TIMER0_PAUSE 61 +#define LEDC_TASK_TIMER1_PAUSE 62 +#define LEDC_TASK_TIMER2_PAUSE 63 +#define LEDC_TASK_TIMER3_PAUSE 64 +#define LEDC_TASK_GAMMA_RESTART_CH0 65 +#define LEDC_TASK_GAMMA_RESTART_CH1 66 +#define LEDC_TASK_GAMMA_RESTART_CH2 67 +#define LEDC_TASK_GAMMA_RESTART_CH3 68 +#define LEDC_TASK_GAMMA_RESTART_CH4 69 +#define LEDC_TASK_GAMMA_RESTART_CH5 70 +#define LEDC_TASK_GAMMA_PAUSE_CH0 71 +#define LEDC_TASK_GAMMA_PAUSE_CH1 72 +#define LEDC_TASK_GAMMA_PAUSE_CH2 73 +#define LEDC_TASK_GAMMA_PAUSE_CH3 74 +#define LEDC_TASK_GAMMA_PAUSE_CH4 75 +#define LEDC_TASK_GAMMA_PAUSE_CH5 76 +#define LEDC_TASK_GAMMA_RESUME_CH0 77 +#define LEDC_TASK_GAMMA_RESUME_CH1 78 +#define LEDC_TASK_GAMMA_RESUME_CH2 79 +#define LEDC_TASK_GAMMA_RESUME_CH3 80 +#define LEDC_TASK_GAMMA_RESUME_CH4 81 +#define LEDC_TASK_GAMMA_RESUME_CH5 82 +#define PCNT_TASK_START 83 +#define PCNT_TASK_STOP 84 +#define PCNT_TASK_CNT_INC 85 +#define PCNT_TASK_CNT_DEC 86 +#define PCNT_TASK_CNT_RST 87 +#define TIMER0_TASK_CNT_START_TIMER0 88 +#define TIMER1_TASK_CNT_START_TIMER0 89 +#define TIMER0_TASK_ALARM_START_TIMER0 90 +#define TIMER1_TASK_ALARM_START_TIMER0 91 +#define TIMER0_TASK_CNT_STOP_TIMER0 92 +#define TIMER1_TASK_CNT_STOP_TIMER0 93 +#define TIMER0_TASK_CNT_RELOAD_TIMER0 94 +#define TIMER1_TASK_CNT_RELOAD_TIMER0 95 +#define TIMER0_TASK_CNT_CAP_TIMER0 96 +#define TIMER1_TASK_CNT_CAP_TIMER0 97 +#define RMT_TASK_TX_START 98 +#define RMT_TASK_TX_STOP 99 +#define RMT_TASK_RX_DONE 100 +#define RMT_TASK_RX_START 101 +#define MCPWM_TASK_CMPR0_A_UP 102 +#define MCPWM_TASK_CMPR1_A_UP 103 +#define MCPWM_TASK_CMPR2_A_UP 104 +#define MCPWM_TASK_CMPR0_B_UP 105 +#define MCPWM_TASK_CMPR1_B_UP 106 +#define MCPWM_TASK_CMPR2_B_UP 107 +#define MCPWM_TASK_GEN_STOP 108 +#define MCPWM_TASK_TIMER0_SYN 109 +#define MCPWM_TASK_TIMER1_SYN 110 +#define MCPWM_TASK_TIMER2_SYN 111 +#define MCPWM_TASK_TIMER0_PERIOD_UP 112 +#define MCPWM_TASK_TIMER1_PERIOD_UP 113 +#define MCPWM_TASK_TIMER2_PERIOD_UP 114 +#define MCPWM_TASK_TZ0_OST 115 +#define MCPWM_TASK_TZ1_OST 116 +#define MCPWM_TASK_TZ2_OST 117 +#define MCPWM_TASK_CLR0_OST 118 +#define MCPWM_TASK_CLR1_OST 119 +#define MCPWM_TASK_CLR2_OST 120 +#define MCPWM_TASK_CAP0 121 +#define MCPWM_TASK_CAP1 122 +#define MCPWM_TASK_CAP2 123 +#define ADC_TASK_SAMPLE0 124 +#define ADC_TASK_SAMPLE1 125 +#define ADC_TASK_START0 126 +#define ADC_TASK_STOP0 127 +#define REGDMA_TASK_START0 128 +#define REGDMA_TASK_START1 129 +#define REGDMA_TASK_START2 130 +#define REGDMA_TASK_START3 131 +#define PDMA_TASK_START_TX 132 +#define PDMA_TASK_START_RX 133 +#define PDMA_TASK_STOP 134 +#define TMPSNSR_TASK_START_SAMPLE 135 +#define TMPSNSR_TASK_STOP_SAMPLE 136 +#define UART_TASK_TX_START0 137 +#define UART_TASK_TX_START1 138 +#define UART_TASK_TX_STOP0 139 +#define UART_TASK_TX_STOP1 140 +#define UART_TASK_RX_START0 141 +#define UART_TASK_RX_START1 142 +#define UART_TASK_RX_STOP0 143 +#define UART_TASK_RX_STOP1 144 +#define SPI_TASK_TX_START 145 +#define SPI_TASK_SLAVE_HD 146 +#define SPI_TASK_STOP 147 +#define I2S_TASK_START_RX 148 +#define I2S_TASK_START_TX 149 +#define I2S_TASK_STOP_RX 150 +#define I2S_TASK_STOP_TX 151 +#define I2C_TASK_START_TRANS 152 +#define CAN_TASK_TRANS_START 153 +#define ULP_TASK_WAKEUP_CPU 154 +#define RTC_TASK_START 155 +#define RTC_TASK_STOP 156 +#define RTC_TASK_CLR 157 +#define RTC_TASK_TRIGGERFLW 158 +#define GDMA_TASK_IN_START_CH0 159 +#define GDMA_TASK_IN_START_CH1 160 +#define GDMA_TASK_IN_START_CH2 161 +#define GDMA_TASK_OUT_START_CH0 162 +#define GDMA_TASK_OUT_START_CH1 163 +#define GDMA_TASK_OUT_START_CH2 164 +#define PMU_TASK_SLEEP_REQ 165 diff --git a/components/soc/esp32c6/include/soc/soc_etm_struct.h b/components/soc/esp32c6/include/soc/soc_etm_struct.h new file mode 100644 index 0000000000..5e8f2dea6b --- /dev/null +++ b/components/soc/esp32c6/include/soc/soc_etm_struct.h @@ -0,0 +1,753 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of ch_ena_ad0 register + * channel enable register + */ +typedef union { + struct { + /** ch_ena0 : R/WTC/WTS; bitpos: [0]; default: 0; + * ch0 enable + */ + uint32_t ch_ena0:1; + /** ch_ena1 : R/WTC/WTS; bitpos: [1]; default: 0; + * ch1 enable + */ + uint32_t ch_ena1:1; + /** ch_ena2 : R/WTC/WTS; bitpos: [2]; default: 0; + * ch2 enable + */ + uint32_t ch_ena2:1; + /** ch_ena3 : R/WTC/WTS; bitpos: [3]; default: 0; + * ch3 enable + */ + uint32_t ch_ena3:1; + /** ch_ena4 : R/WTC/WTS; bitpos: [4]; default: 0; + * ch4 enable + */ + uint32_t ch_ena4:1; + /** ch_ena5 : R/WTC/WTS; bitpos: [5]; default: 0; + * ch5 enable + */ + uint32_t ch_ena5:1; + /** ch_ena6 : R/WTC/WTS; bitpos: [6]; default: 0; + * ch6 enable + */ + uint32_t ch_ena6:1; + /** ch_ena7 : R/WTC/WTS; bitpos: [7]; default: 0; + * ch7 enable + */ + uint32_t ch_ena7:1; + /** ch_ena8 : R/WTC/WTS; bitpos: [8]; default: 0; + * ch8 enable + */ + uint32_t ch_ena8:1; + /** ch_ena9 : R/WTC/WTS; bitpos: [9]; default: 0; + * ch9 enable + */ + uint32_t ch_ena9:1; + /** ch_ena10 : R/WTC/WTS; bitpos: [10]; default: 0; + * ch10 enable + */ + uint32_t ch_ena10:1; + /** ch_ena11 : R/WTC/WTS; bitpos: [11]; default: 0; + * ch11 enable + */ + uint32_t ch_ena11:1; + /** ch_ena12 : R/WTC/WTS; bitpos: [12]; default: 0; + * ch12 enable + */ + uint32_t ch_ena12:1; + /** ch_ena13 : R/WTC/WTS; bitpos: [13]; default: 0; + * ch13 enable + */ + uint32_t ch_ena13:1; + /** ch_ena14 : R/WTC/WTS; bitpos: [14]; default: 0; + * ch14 enable + */ + uint32_t ch_ena14:1; + /** ch_ena15 : R/WTC/WTS; bitpos: [15]; default: 0; + * ch15 enable + */ + uint32_t ch_ena15:1; + /** ch_ena16 : R/WTC/WTS; bitpos: [16]; default: 0; + * ch16 enable + */ + uint32_t ch_ena16:1; + /** ch_ena17 : R/WTC/WTS; bitpos: [17]; default: 0; + * ch17 enable + */ + uint32_t ch_ena17:1; + /** ch_ena18 : R/WTC/WTS; bitpos: [18]; default: 0; + * ch18 enable + */ + uint32_t ch_ena18:1; + /** ch_ena19 : R/WTC/WTS; bitpos: [19]; default: 0; + * ch19 enable + */ + uint32_t ch_ena19:1; + /** ch_ena20 : R/WTC/WTS; bitpos: [20]; default: 0; + * ch20 enable + */ + uint32_t ch_ena20:1; + /** ch_ena21 : R/WTC/WTS; bitpos: [21]; default: 0; + * ch21 enable + */ + uint32_t ch_ena21:1; + /** ch_ena22 : R/WTC/WTS; bitpos: [22]; default: 0; + * ch22 enable + */ + uint32_t ch_ena22:1; + /** ch_ena23 : R/WTC/WTS; bitpos: [23]; default: 0; + * ch23 enable + */ + uint32_t ch_ena23:1; + /** ch_ena24 : R/WTC/WTS; bitpos: [24]; default: 0; + * ch24 enable + */ + uint32_t ch_ena24:1; + /** ch_ena25 : R/WTC/WTS; bitpos: [25]; default: 0; + * ch25 enable + */ + uint32_t ch_ena25:1; + /** ch_ena26 : R/WTC/WTS; bitpos: [26]; default: 0; + * ch26 enable + */ + uint32_t ch_ena26:1; + /** ch_ena27 : R/WTC/WTS; bitpos: [27]; default: 0; + * ch27 enable + */ + uint32_t ch_ena27:1; + /** ch_ena28 : R/WTC/WTS; bitpos: [28]; default: 0; + * ch28 enable + */ + uint32_t ch_ena28:1; + /** ch_ena29 : R/WTC/WTS; bitpos: [29]; default: 0; + * ch29 enable + */ + uint32_t ch_ena29:1; + /** ch_ena30 : R/WTC/WTS; bitpos: [30]; default: 0; + * ch30 enable + */ + uint32_t ch_ena30:1; + /** ch_ena31 : R/WTC/WTS; bitpos: [31]; default: 0; + * ch31 enable + */ + uint32_t ch_ena31:1; + }; + uint32_t val; +} soc_etm_ch_ena_ad0_reg_t; + +/** Type of ch_ena_ad0_set register + * channel enable set register + */ +typedef union { + struct { + /** ch_set0 : WT; bitpos: [0]; default: 0; + * ch0 set + */ + uint32_t ch_set0:1; + /** ch_set1 : WT; bitpos: [1]; default: 0; + * ch1 set + */ + uint32_t ch_set1:1; + /** ch_set2 : WT; bitpos: [2]; default: 0; + * ch2 set + */ + uint32_t ch_set2:1; + /** ch_set3 : WT; bitpos: [3]; default: 0; + * ch3 set + */ + uint32_t ch_set3:1; + /** ch_set4 : WT; bitpos: [4]; default: 0; + * ch4 set + */ + uint32_t ch_set4:1; + /** ch_set5 : WT; bitpos: [5]; default: 0; + * ch5 set + */ + uint32_t ch_set5:1; + /** ch_set6 : WT; bitpos: [6]; default: 0; + * ch6 set + */ + uint32_t ch_set6:1; + /** ch_set7 : WT; bitpos: [7]; default: 0; + * ch7 set + */ + uint32_t ch_set7:1; + /** ch_set8 : WT; bitpos: [8]; default: 0; + * ch8 set + */ + uint32_t ch_set8:1; + /** ch_set9 : WT; bitpos: [9]; default: 0; + * ch9 set + */ + uint32_t ch_set9:1; + /** ch_set10 : WT; bitpos: [10]; default: 0; + * ch10 set + */ + uint32_t ch_set10:1; + /** ch_set11 : WT; bitpos: [11]; default: 0; + * ch11 set + */ + uint32_t ch_set11:1; + /** ch_set12 : WT; bitpos: [12]; default: 0; + * ch12 set + */ + uint32_t ch_set12:1; + /** ch_set13 : WT; bitpos: [13]; default: 0; + * ch13 set + */ + uint32_t ch_set13:1; + /** ch_set14 : WT; bitpos: [14]; default: 0; + * ch14 set + */ + uint32_t ch_set14:1; + /** ch_set15 : WT; bitpos: [15]; default: 0; + * ch15 set + */ + uint32_t ch_set15:1; + /** ch_set16 : WT; bitpos: [16]; default: 0; + * ch16 set + */ + uint32_t ch_set16:1; + /** ch_set17 : WT; bitpos: [17]; default: 0; + * ch17 set + */ + uint32_t ch_set17:1; + /** ch_set18 : WT; bitpos: [18]; default: 0; + * ch18 set + */ + uint32_t ch_set18:1; + /** ch_set19 : WT; bitpos: [19]; default: 0; + * ch19 set + */ + uint32_t ch_set19:1; + /** ch_set20 : WT; bitpos: [20]; default: 0; + * ch20 set + */ + uint32_t ch_set20:1; + /** ch_set21 : WT; bitpos: [21]; default: 0; + * ch21 set + */ + uint32_t ch_set21:1; + /** ch_set22 : WT; bitpos: [22]; default: 0; + * ch22 set + */ + uint32_t ch_set22:1; + /** ch_set23 : WT; bitpos: [23]; default: 0; + * ch23 set + */ + uint32_t ch_set23:1; + /** ch_set24 : WT; bitpos: [24]; default: 0; + * ch24 set + */ + uint32_t ch_set24:1; + /** ch_set25 : WT; bitpos: [25]; default: 0; + * ch25 set + */ + uint32_t ch_set25:1; + /** ch_set26 : WT; bitpos: [26]; default: 0; + * ch26 set + */ + uint32_t ch_set26:1; + /** ch_set27 : WT; bitpos: [27]; default: 0; + * ch27 set + */ + uint32_t ch_set27:1; + /** ch_set28 : WT; bitpos: [28]; default: 0; + * ch28 set + */ + uint32_t ch_set28:1; + /** ch_set29 : WT; bitpos: [29]; default: 0; + * ch29 set + */ + uint32_t ch_set29:1; + /** ch_set30 : WT; bitpos: [30]; default: 0; + * ch30 set + */ + uint32_t ch_set30:1; + /** ch_set31 : WT; bitpos: [31]; default: 0; + * ch31 set + */ + uint32_t ch_set31:1; + }; + uint32_t val; +} soc_etm_ch_ena_ad0_set_reg_t; + +/** Type of ch_ena_ad0_clr register + * channel enable clear register + */ +typedef union { + struct { + /** ch_clr0 : WT; bitpos: [0]; default: 0; + * ch0 clear + */ + uint32_t ch_clr0:1; + /** ch_clr1 : WT; bitpos: [1]; default: 0; + * ch1 clear + */ + uint32_t ch_clr1:1; + /** ch_clr2 : WT; bitpos: [2]; default: 0; + * ch2 clear + */ + uint32_t ch_clr2:1; + /** ch_clr3 : WT; bitpos: [3]; default: 0; + * ch3 clear + */ + uint32_t ch_clr3:1; + /** ch_clr4 : WT; bitpos: [4]; default: 0; + * ch4 clear + */ + uint32_t ch_clr4:1; + /** ch_clr5 : WT; bitpos: [5]; default: 0; + * ch5 clear + */ + uint32_t ch_clr5:1; + /** ch_clr6 : WT; bitpos: [6]; default: 0; + * ch6 clear + */ + uint32_t ch_clr6:1; + /** ch_clr7 : WT; bitpos: [7]; default: 0; + * ch7 clear + */ + uint32_t ch_clr7:1; + /** ch_clr8 : WT; bitpos: [8]; default: 0; + * ch8 clear + */ + uint32_t ch_clr8:1; + /** ch_clr9 : WT; bitpos: [9]; default: 0; + * ch9 clear + */ + uint32_t ch_clr9:1; + /** ch_clr10 : WT; bitpos: [10]; default: 0; + * ch10 clear + */ + uint32_t ch_clr10:1; + /** ch_clr11 : WT; bitpos: [11]; default: 0; + * ch11 clear + */ + uint32_t ch_clr11:1; + /** ch_clr12 : WT; bitpos: [12]; default: 0; + * ch12 clear + */ + uint32_t ch_clr12:1; + /** ch_clr13 : WT; bitpos: [13]; default: 0; + * ch13 clear + */ + uint32_t ch_clr13:1; + /** ch_clr14 : WT; bitpos: [14]; default: 0; + * ch14 clear + */ + uint32_t ch_clr14:1; + /** ch_clr15 : WT; bitpos: [15]; default: 0; + * ch15 clear + */ + uint32_t ch_clr15:1; + /** ch_clr16 : WT; bitpos: [16]; default: 0; + * ch16 clear + */ + uint32_t ch_clr16:1; + /** ch_clr17 : WT; bitpos: [17]; default: 0; + * ch17 clear + */ + uint32_t ch_clr17:1; + /** ch_clr18 : WT; bitpos: [18]; default: 0; + * ch18 clear + */ + uint32_t ch_clr18:1; + /** ch_clr19 : WT; bitpos: [19]; default: 0; + * ch19 clear + */ + uint32_t ch_clr19:1; + /** ch_clr20 : WT; bitpos: [20]; default: 0; + * ch20 clear + */ + uint32_t ch_clr20:1; + /** ch_clr21 : WT; bitpos: [21]; default: 0; + * ch21 clear + */ + uint32_t ch_clr21:1; + /** ch_clr22 : WT; bitpos: [22]; default: 0; + * ch22 clear + */ + uint32_t ch_clr22:1; + /** ch_clr23 : WT; bitpos: [23]; default: 0; + * ch23 clear + */ + uint32_t ch_clr23:1; + /** ch_clr24 : WT; bitpos: [24]; default: 0; + * ch24 clear + */ + uint32_t ch_clr24:1; + /** ch_clr25 : WT; bitpos: [25]; default: 0; + * ch25 clear + */ + uint32_t ch_clr25:1; + /** ch_clr26 : WT; bitpos: [26]; default: 0; + * ch26 clear + */ + uint32_t ch_clr26:1; + /** ch_clr27 : WT; bitpos: [27]; default: 0; + * ch27 clear + */ + uint32_t ch_clr27:1; + /** ch_clr28 : WT; bitpos: [28]; default: 0; + * ch28 clear + */ + uint32_t ch_clr28:1; + /** ch_clr29 : WT; bitpos: [29]; default: 0; + * ch29 clear + */ + uint32_t ch_clr29:1; + /** ch_clr30 : WT; bitpos: [30]; default: 0; + * ch30 clear + */ + uint32_t ch_clr30:1; + /** ch_clr31 : WT; bitpos: [31]; default: 0; + * ch31 clear + */ + uint32_t ch_clr31:1; + }; + uint32_t val; +} soc_etm_ch_ena_ad0_clr_reg_t; + +/** Type of ch_ena_ad1 register + * channel enable register + */ +typedef union { + struct { + /** ch_ena32 : R/WTC/WTS; bitpos: [0]; default: 0; + * ch32 enable + */ + uint32_t ch_ena32:1; + /** ch_ena33 : R/WTC/WTS; bitpos: [1]; default: 0; + * ch33 enable + */ + uint32_t ch_ena33:1; + /** ch_ena34 : R/WTC/WTS; bitpos: [2]; default: 0; + * ch34 enable + */ + uint32_t ch_ena34:1; + /** ch_ena35 : R/WTC/WTS; bitpos: [3]; default: 0; + * ch35 enable + */ + uint32_t ch_ena35:1; + /** ch_ena36 : R/WTC/WTS; bitpos: [4]; default: 0; + * ch36 enable + */ + uint32_t ch_ena36:1; + /** ch_ena37 : R/WTC/WTS; bitpos: [5]; default: 0; + * ch37 enable + */ + uint32_t ch_ena37:1; + /** ch_ena38 : R/WTC/WTS; bitpos: [6]; default: 0; + * ch38 enable + */ + uint32_t ch_ena38:1; + /** ch_ena39 : R/WTC/WTS; bitpos: [7]; default: 0; + * ch39 enable + */ + uint32_t ch_ena39:1; + /** ch_ena40 : R/WTC/WTS; bitpos: [8]; default: 0; + * ch40 enable + */ + uint32_t ch_ena40:1; + /** ch_ena41 : R/WTC/WTS; bitpos: [9]; default: 0; + * ch41 enable + */ + uint32_t ch_ena41:1; + /** ch_ena42 : R/WTC/WTS; bitpos: [10]; default: 0; + * ch42 enable + */ + uint32_t ch_ena42:1; + /** ch_ena43 : R/WTC/WTS; bitpos: [11]; default: 0; + * ch43 enable + */ + uint32_t ch_ena43:1; + /** ch_ena44 : R/WTC/WTS; bitpos: [12]; default: 0; + * ch44 enable + */ + uint32_t ch_ena44:1; + /** ch_ena45 : R/WTC/WTS; bitpos: [13]; default: 0; + * ch45 enable + */ + uint32_t ch_ena45:1; + /** ch_ena46 : R/WTC/WTS; bitpos: [14]; default: 0; + * ch46 enable + */ + uint32_t ch_ena46:1; + /** ch_ena47 : R/WTC/WTS; bitpos: [15]; default: 0; + * ch47 enable + */ + uint32_t ch_ena47:1; + /** ch_ena48 : R/WTC/WTS; bitpos: [16]; default: 0; + * ch48 enable + */ + uint32_t ch_ena48:1; + /** ch_ena49 : R/WTC/WTS; bitpos: [17]; default: 0; + * ch49 enable + */ + uint32_t ch_ena49:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} soc_etm_ch_ena_ad1_reg_t; + +/** Type of ch_ena_ad1_set register + * channel enable set register + */ +typedef union { + struct { + /** ch_set32 : WT; bitpos: [0]; default: 0; + * ch32 set + */ + uint32_t ch_set32:1; + /** ch_set33 : WT; bitpos: [1]; default: 0; + * ch33 set + */ + uint32_t ch_set33:1; + /** ch_set34 : WT; bitpos: [2]; default: 0; + * ch34 set + */ + uint32_t ch_set34:1; + /** ch_set35 : WT; bitpos: [3]; default: 0; + * ch35 set + */ + uint32_t ch_set35:1; + /** ch_set36 : WT; bitpos: [4]; default: 0; + * ch36 set + */ + uint32_t ch_set36:1; + /** ch_set37 : WT; bitpos: [5]; default: 0; + * ch37 set + */ + uint32_t ch_set37:1; + /** ch_set38 : WT; bitpos: [6]; default: 0; + * ch38 set + */ + uint32_t ch_set38:1; + /** ch_set39 : WT; bitpos: [7]; default: 0; + * ch39 set + */ + uint32_t ch_set39:1; + /** ch_set40 : WT; bitpos: [8]; default: 0; + * ch40 set + */ + uint32_t ch_set40:1; + /** ch_set41 : WT; bitpos: [9]; default: 0; + * ch41 set + */ + uint32_t ch_set41:1; + /** ch_set42 : WT; bitpos: [10]; default: 0; + * ch42 set + */ + uint32_t ch_set42:1; + /** ch_set43 : WT; bitpos: [11]; default: 0; + * ch43 set + */ + uint32_t ch_set43:1; + /** ch_set44 : WT; bitpos: [12]; default: 0; + * ch44 set + */ + uint32_t ch_set44:1; + /** ch_set45 : WT; bitpos: [13]; default: 0; + * ch45 set + */ + uint32_t ch_set45:1; + /** ch_set46 : WT; bitpos: [14]; default: 0; + * ch46 set + */ + uint32_t ch_set46:1; + /** ch_set47 : WT; bitpos: [15]; default: 0; + * ch47 set + */ + uint32_t ch_set47:1; + /** ch_set48 : WT; bitpos: [16]; default: 0; + * ch48 set + */ + uint32_t ch_set48:1; + /** ch_set49 : WT; bitpos: [17]; default: 0; + * ch49 set + */ + uint32_t ch_set49:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} soc_etm_ch_ena_ad1_set_reg_t; + +/** Type of ch_ena_ad1_clr register + * channel enable clear register + */ +typedef union { + struct { + /** ch_clr32 : WT; bitpos: [0]; default: 0; + * ch32 clear + */ + uint32_t ch_clr32:1; + /** ch_clr33 : WT; bitpos: [1]; default: 0; + * ch33 clear + */ + uint32_t ch_clr33:1; + /** ch_clr34 : WT; bitpos: [2]; default: 0; + * ch34 clear + */ + uint32_t ch_clr34:1; + /** ch_clr35 : WT; bitpos: [3]; default: 0; + * ch35 clear + */ + uint32_t ch_clr35:1; + /** ch_clr36 : WT; bitpos: [4]; default: 0; + * ch36 clear + */ + uint32_t ch_clr36:1; + /** ch_clr37 : WT; bitpos: [5]; default: 0; + * ch37 clear + */ + uint32_t ch_clr37:1; + /** ch_clr38 : WT; bitpos: [6]; default: 0; + * ch38 clear + */ + uint32_t ch_clr38:1; + /** ch_clr39 : WT; bitpos: [7]; default: 0; + * ch39 clear + */ + uint32_t ch_clr39:1; + /** ch_clr40 : WT; bitpos: [8]; default: 0; + * ch40 clear + */ + uint32_t ch_clr40:1; + /** ch_clr41 : WT; bitpos: [9]; default: 0; + * ch41 clear + */ + uint32_t ch_clr41:1; + /** ch_clr42 : WT; bitpos: [10]; default: 0; + * ch42 clear + */ + uint32_t ch_clr42:1; + /** ch_clr43 : WT; bitpos: [11]; default: 0; + * ch43 clear + */ + uint32_t ch_clr43:1; + /** ch_clr44 : WT; bitpos: [12]; default: 0; + * ch44 clear + */ + uint32_t ch_clr44:1; + /** ch_clr45 : WT; bitpos: [13]; default: 0; + * ch45 clear + */ + uint32_t ch_clr45:1; + /** ch_clr46 : WT; bitpos: [14]; default: 0; + * ch46 clear + */ + uint32_t ch_clr46:1; + /** ch_clr47 : WT; bitpos: [15]; default: 0; + * ch47 clear + */ + uint32_t ch_clr47:1; + /** ch_clr48 : WT; bitpos: [16]; default: 0; + * ch48 clear + */ + uint32_t ch_clr48:1; + /** ch_clr49 : WT; bitpos: [17]; default: 0; + * ch49 clear + */ + uint32_t ch_clr49:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} soc_etm_ch_ena_ad1_clr_reg_t; + +/** Type of chn_evt_id register + * channeln event id register + */ +typedef union { + struct { + /** evt_id : R/W; bitpos: [7:0]; default: 0; + * chn_evt_id + */ + uint32_t evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_chn_evt_id_reg_t; + +/** Type of chn_task_id register + * channeln task id register + */ +typedef union { + struct { + /** task_id : R/W; bitpos: [7:0]; default: 0; + * chn_task_id + */ + uint32_t task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_chn_task_id_reg_t; + +/** Type of clk_en register + * etm clock enable register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * clock enable + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} soc_etm_clk_en_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * etm date register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35664018; + * date + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} soc_etm_date_reg_t; + + +typedef struct soc_etm_dev_t { + volatile soc_etm_ch_ena_ad0_reg_t ch_ena_ad0; + volatile soc_etm_ch_ena_ad0_set_reg_t ch_ena_ad0_set; + volatile soc_etm_ch_ena_ad0_clr_reg_t ch_ena_ad0_clr; + volatile soc_etm_ch_ena_ad1_reg_t ch_ena_ad1; + volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set; + volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr; + volatile struct { + soc_etm_chn_evt_id_reg_t evt_id; + soc_etm_chn_task_id_reg_t task_id; + } channel[50]; + volatile soc_etm_clk_en_reg_t clk_en; + volatile soc_etm_date_reg_t date; +} soc_etm_dev_t; + +extern soc_etm_dev_t SOC_ETM; + +#ifndef __cplusplus +_Static_assert(sizeof(soc_etm_dev_t) == 0x1b0, "Invalid size of soc_etm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/soc_pins.h b/components/soc/esp32c6/include/soc/soc_pins.h new file mode 100644 index 0000000000..914f22122d --- /dev/null +++ b/components/soc/esp32c6/include/soc/soc_pins.h @@ -0,0 +1,16 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Pin definition header file. The long term plan is to have a single soc_pins.h for all + * peripherals. Now we temporarily separate these information into periph_pins/channels.h for each + * peripheral and include them here to avoid developing conflicts in those header files. + */ + +#pragma once + +#include "soc/gpio_pins.h" +#include "soc/spi_pins.h" diff --git a/components/soc/esp32c6/include/soc/spi_mem_reg.h b/components/soc/esp32c6/include/soc/spi_mem_reg.h new file mode 100644 index 0000000000..0b0fff856e --- /dev/null +++ b/components/soc/esp32c6/include/soc/spi_mem_reg.h @@ -0,0 +1,3203 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI_MEM_CMD_REG register + * SPI0 FSM status register + * SPI1 memory command register + */ +#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0) +/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Read flash enable. Read flash operation will be triggered when the bit is set. T +he bit will be cleared once the operation done. 1: enable 0: disable..*/ +#define SPI_MEM_FLASH_READ (BIT(31)) +#define SPI_MEM_FLASH_READ_M (BIT(31)) +#define SPI_MEM_FLASH_READ_V 0x1 +#define SPI_MEM_FLASH_READ_S 31 +/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Write flash enable. Write enable command will be sent when the bit is set. The +bit will be cleared once the operation done. 1: enable 0: disable..*/ +#define SPI_MEM_FLASH_WREN (BIT(30)) +#define SPI_MEM_FLASH_WREN_M (BIT(30)) +#define SPI_MEM_FLASH_WREN_V 0x1 +#define SPI_MEM_FLASH_WREN_S 30 +/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Write flash disable. Write disable command will be sent when the bit is set. The + bit will be cleared once the operation done. 1: enable 0: disable..*/ +#define SPI_MEM_FLASH_WRDI (BIT(29)) +#define SPI_MEM_FLASH_WRDI_M (BIT(29)) +#define SPI_MEM_FLASH_WRDI_V 0x1 +#define SPI_MEM_FLASH_WRDI_S 29 +/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will b +e cleared once the operation done. 1: enable 0: disable..*/ +#define SPI_MEM_FLASH_RDID (BIT(28)) +#define SPI_MEM_FLASH_RDID_M (BIT(28)) +#define SPI_MEM_FLASH_RDID_V 0x1 +#define SPI_MEM_FLASH_RDID_S 28 +/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Read status register-1. Read status operation will be triggered when the bit is + set. The bit will be cleared once the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_RDSR (BIT(27)) +#define SPI_MEM_FLASH_RDSR_M (BIT(27)) +#define SPI_MEM_FLASH_RDSR_V 0x1 +#define SPI_MEM_FLASH_RDSR_S 27 +/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Write status register enable. Write status operation will be triggered when t +he bit is set. The bit will be cleared once the operation done.1: enable 0: disa +ble..*/ +#define SPI_MEM_FLASH_WRSR (BIT(26)) +#define SPI_MEM_FLASH_WRSR_M (BIT(26)) +#define SPI_MEM_FLASH_WRSR_V 0x1 +#define SPI_MEM_FLASH_WRSR_S 26 +/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Page program enable(1 byte ~256 bytes data to be programmed). Page program opera +tion will be triggered when the bit is set. The bit will be cleared once the op +eration done .1: enable 0: disable..*/ +#define SPI_MEM_FLASH_PP (BIT(25)) +#define SPI_MEM_FLASH_PP_M (BIT(25)) +#define SPI_MEM_FLASH_PP_V 0x1 +#define SPI_MEM_FLASH_PP_S 25 +/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Sector erase enable(4KB). Sector erase operation will be triggered when the bit +is set. The bit will be cleared once the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_SE (BIT(24)) +#define SPI_MEM_FLASH_SE_M (BIT(24)) +#define SPI_MEM_FLASH_SE_V 0x1 +#define SPI_MEM_FLASH_SE_S 24 +/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Block erase enable(32KB) . Block erase operation will be triggered when the bit + is set. The bit will be cleared once the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_BE (BIT(23)) +#define SPI_MEM_FLASH_BE_M (BIT(23)) +#define SPI_MEM_FLASH_BE_V 0x1 +#define SPI_MEM_FLASH_BE_S 23 +/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Chip erase enable. Chip erase operation will be triggered when the bit is set. T +he bit will be cleared once the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_CE (BIT(22)) +#define SPI_MEM_FLASH_CE_M (BIT(22)) +#define SPI_MEM_FLASH_CE_V 0x1 +#define SPI_MEM_FLASH_CE_S 22 +/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Drive Flash into power down. An operation will be triggered when the bit is set +. The bit will be cleared once the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_DP (BIT(21)) +#define SPI_MEM_FLASH_DP_M (BIT(21)) +#define SPI_MEM_FLASH_DP_V 0x1 +#define SPI_MEM_FLASH_DP_S 21 +/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ +/*description: This bit combined with reg_resandres bit releases Flash from the power-down stat +e or high performance mode and obtains the devices ID. The bit will be cleared o +nce the operation done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_RES (BIT(20)) +#define SPI_MEM_FLASH_RES_M (BIT(20)) +#define SPI_MEM_FLASH_RES_V 0x1 +#define SPI_MEM_FLASH_RES_S 20 +/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Drive Flash into high performance mode. The bit will be cleared once the operat +ion done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_HPM (BIT(19)) +#define SPI_MEM_FLASH_HPM_M (BIT(19)) +#define SPI_MEM_FLASH_HPM_V 0x1 +#define SPI_MEM_FLASH_HPM_S 19 +/* SPI_MEM_USR : HRO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operat +ion will be triggered when the bit is set. The bit will be cleared once the oper +ation done.1: enable 0: disable..*/ +#define SPI_MEM_USR (BIT(18)) +#define SPI_MEM_USR_M (BIT(18)) +#define SPI_MEM_USR_V 0x1 +#define SPI_MEM_USR_S 18 +/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */ +/*description: In user mode, it is set to indicate that program/erase operation will be trigger +ed. The bit is combined with spi_mem_usr bit. The bit will be cleared once the o +peration done.1: enable 0: disable..*/ +#define SPI_MEM_FLASH_PE (BIT(17)) +#define SPI_MEM_FLASH_PE_M (BIT(17)) +#define SPI_MEM_FLASH_PE_V 0x1 +#define SPI_MEM_FLASH_PE_S 17 +/* SPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */ +/*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation sta +te, 2: send command state, 3: send address state, 4: wait state, 5: read data st +ate, 6:write data state, 7: done state, 8: read data end state..*/ +#define SPI_MEM_SLV_ST 0x0000000F +#define SPI_MEM_SLV_ST_M ((SPI_MEM_SLV_ST_V)<<(SPI_MEM_SLV_ST_S)) +#define SPI_MEM_SLV_ST_V 0xF +#define SPI_MEM_SLV_ST_S 4 +/* SPI_MEM_MST_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT +, 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA se +nt data is stored in SPI0 TX FIFO, 5: SPI0 write data state..*/ +#define SPI_MEM_MST_ST 0x0000000F +#define SPI_MEM_MST_ST_M ((SPI_MEM_MST_ST_V)<<(SPI_MEM_MST_ST_S)) +#define SPI_MEM_MST_ST_V 0xF +#define SPI_MEM_MST_ST_S 0 + +#define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4) +/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: In user mode, it is the memory address. other then the bit0-bit23 is the memory +address, the bit24-bit31 are the byte length of a transfer..*/ +#define SPI_MEM_USR_ADDR_VALUE 0xFFFFFFFF +#define SPI_MEM_USR_ADDR_VALUE_M ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S)) +#define SPI_MEM_USR_ADDR_VALUE_V 0xFFFFFFFF +#define SPI_MEM_USR_ADDR_VALUE_S 0 + +#define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8) +/* SPI_MEM_DATA_IE_ALWAYS_ON : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are a +lways 1. 0: Others..*/ +#define SPI_MEM_DATA_IE_ALWAYS_ON (BIT(31)) +#define SPI_MEM_DATA_IE_ALWAYS_ON_M (BIT(31)) +#define SPI_MEM_DATA_IE_ALWAYS_ON_V 0x1 +#define SPI_MEM_DATA_IE_ALWAYS_ON_S 31 +/* SPI_MEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are alway +s 1. 0: Others..*/ +#define SPI_MEM_DQS_IE_ALWAYS_ON (BIT(30)) +#define SPI_MEM_DQS_IE_ALWAYS_ON_M (BIT(30)) +#define SPI_MEM_DQS_IE_ALWAYS_ON_V 0x1 +#define SPI_MEM_DQS_IE_ALWAYS_ON_S 30 +/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: In the read operations address phase and read-data phase apply 4 signals. 1: ena +ble 0: disable..*/ +#define SPI_MEM_FREAD_QIO (BIT(24)) +#define SPI_MEM_FREAD_QIO_M (BIT(24)) +#define SPI_MEM_FREAD_QIO_V 0x1 +#define SPI_MEM_FREAD_QIO_S 24 +/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: In the read operations address phase and read-data phase apply 2 signals. 1: ena +ble 0: disable..*/ +#define SPI_MEM_FREAD_DIO (BIT(23)) +#define SPI_MEM_FREAD_DIO_M (BIT(23)) +#define SPI_MEM_FREAD_DIO_V 0x1 +#define SPI_MEM_FREAD_DIO_S 23 +/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: two bytes data will be written to status register when it is set. 1: enable 0: d +isable..*/ +#define SPI_MEM_WRSR_2B (BIT(22)) +#define SPI_MEM_WRSR_2B_M (BIT(22)) +#define SPI_MEM_WRSR_2B_V 0x1 +#define SPI_MEM_WRSR_2B_S 22 +/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: Write protect signal output when SPI is idle. 1: output high, 0: output low..*/ +#define SPI_MEM_WP_REG (BIT(21)) +#define SPI_MEM_WP_REG_M (BIT(21)) +#define SPI_MEM_WP_REG_V 0x1 +#define SPI_MEM_WP_REG_S 21 +/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable..*/ +#define SPI_MEM_FREAD_QUAD (BIT(20)) +#define SPI_MEM_FREAD_QUAD_M (BIT(20)) +#define SPI_MEM_FREAD_QUAD_V 0x1 +#define SPI_MEM_FREAD_QUAD_S 20 +/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */ +/*description: The bit is used to set MOSI line polarity, 1: high 0, low.*/ +#define SPI_MEM_D_POL (BIT(19)) +#define SPI_MEM_D_POL_M (BIT(19)) +#define SPI_MEM_D_POL_V 0x1 +#define SPI_MEM_D_POL_S 19 +/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: The bit is used to set MISO line polarity, 1: high 0, low.*/ +#define SPI_MEM_Q_POL (BIT(18)) +#define SPI_MEM_Q_POL_M (BIT(18)) +#define SPI_MEM_Q_POL_V 0x1 +#define SPI_MEM_Q_POL_S 18 +/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */ +/*description: The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with +spi_mem_flash_res bit. 1: enable 0: disable..*/ +#define SPI_MEM_RESANDRES (BIT(15)) +#define SPI_MEM_RESANDRES_M (BIT(15)) +#define SPI_MEM_RESANDRES_V 0x1 +#define SPI_MEM_RESANDRES_S 15 +/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable..*/ +#define SPI_MEM_FREAD_DUAL (BIT(14)) +#define SPI_MEM_FREAD_DUAL_M (BIT(14)) +#define SPI_MEM_FREAD_DUAL_V 0x1 +#define SPI_MEM_FREAD_DUAL_S 14 +/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QO +UT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/ +#define SPI_MEM_FASTRD_MODE (BIT(13)) +#define SPI_MEM_FASTRD_MODE_M (BIT(13)) +#define SPI_MEM_FASTRD_MODE_V 0x1 +#define SPI_MEM_FASTRD_MODE_S 13 +/* SPI_MEM_TX_CRC_EN : HRO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disabl +e.*/ +#define SPI_MEM_TX_CRC_EN (BIT(11)) +#define SPI_MEM_TX_CRC_EN_M (BIT(11)) +#define SPI_MEM_TX_CRC_EN_V 0x1 +#define SPI_MEM_TX_CRC_EN_S 11 +/* SPI_MEM_FCS_CRC_EN : HRO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: For SPI1, initialize crc32 module before writing encrypted data to flash. Activ +e low..*/ +#define SPI_MEM_FCS_CRC_EN (BIT(10)) +#define SPI_MEM_FCS_CRC_EN_M (BIT(10)) +#define SPI_MEM_FCS_CRC_EN_V 0x1 +#define SPI_MEM_FCS_CRC_EN_S 10 +/* SPI_MEM_FCMD_OCT : HRO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Apply 8 signals during command phase 1:enable 0: disable.*/ +#define SPI_MEM_FCMD_OCT (BIT(9)) +#define SPI_MEM_FCMD_OCT_M (BIT(9)) +#define SPI_MEM_FCMD_OCT_V 0x1 +#define SPI_MEM_FCMD_OCT_S 9 +/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Apply 4 signals during command phase 1:enable 0: disable.*/ +#define SPI_MEM_FCMD_QUAD (BIT(8)) +#define SPI_MEM_FCMD_QUAD_M (BIT(8)) +#define SPI_MEM_FCMD_QUAD_V 0x1 +#define SPI_MEM_FCMD_QUAD_S 8 +/* SPI_MEM_FADDR_OCT : HRO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Apply 8 signals during address phase 1:enable 0: disable.*/ +#define SPI_MEM_FADDR_OCT (BIT(6)) +#define SPI_MEM_FADDR_OCT_M (BIT(6)) +#define SPI_MEM_FADDR_OCT_V 0x1 +#define SPI_MEM_FADDR_OCT_S 6 +/* SPI_MEM_FDIN_OCT : HRO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Apply 8 signals during read-data phase 1:enable 0: disable.*/ +#define SPI_MEM_FDIN_OCT (BIT(5)) +#define SPI_MEM_FDIN_OCT_M (BIT(5)) +#define SPI_MEM_FDIN_OCT_V 0x1 +#define SPI_MEM_FDIN_OCT_S 5 +/* SPI_MEM_FDOUT_OCT : HRO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Apply 8 signals during write-data phase 1:enable 0: disable.*/ +#define SPI_MEM_FDOUT_OCT (BIT(4)) +#define SPI_MEM_FDOUT_OCT_M (BIT(4)) +#define SPI_MEM_FDOUT_OCT_V 0x1 +#define SPI_MEM_FDOUT_OCT_S 4 +/* SPI_MEM_FDUMMY_WOUT : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] +is output by the MSPI controller in the second half part of dummy phase. It is u +sed to pre-drive flash..*/ +#define SPI_MEM_FDUMMY_WOUT (BIT(3)) +#define SPI_MEM_FDUMMY_WOUT_M (BIT(3)) +#define SPI_MEM_FDUMMY_WOUT_V 0x1 +#define SPI_MEM_FDUMMY_WOUT_S 3 +/* SPI_MEM_FDUMMY_RIN : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] i +s output by the MSPI controller in the first half part of dummy phase. It is use +d to mask invalid SPI_DQS in the half part of dummy phase..*/ +#define SPI_MEM_FDUMMY_RIN (BIT(2)) +#define SPI_MEM_FDUMMY_RIN_M (BIT(2)) +#define SPI_MEM_FDUMMY_RIN_V 0x1 +#define SPI_MEM_FDUMMY_RIN_S 2 +/* SPI_MEM_WDUMMY_ALWAYS_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le +vel of SPI_IO[7:0] is output by the MSPI controller..*/ +#define SPI_MEM_WDUMMY_ALWAYS_OUT (BIT(1)) +#define SPI_MEM_WDUMMY_ALWAYS_OUT_M (BIT(1)) +#define SPI_MEM_WDUMMY_ALWAYS_OUT_V 0x1 +#define SPI_MEM_WDUMMY_ALWAYS_OUT_S 1 +/* SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : HRO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le +vel of SPI_DQS is output by the MSPI controller..*/ +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT (BIT(0)) +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M (BIT(0)) +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V 0x1 +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S 0 + +#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xC) +/* SPI_MEM_TXFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to + send signals to AXI. Set this bit to reset these FIFO..*/ +#define SPI_MEM_TXFIFO_RST (BIT(31)) +#define SPI_MEM_TXFIFO_RST_M (BIT(31)) +#define SPI_MEM_TXFIFO_RST_V 0x1 +#define SPI_MEM_TXFIFO_RST_S 31 +/* SPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to + receive signals from AXI. Set this bit to reset these FIFO..*/ +#define SPI_MEM_RXFIFO_RST (BIT(30)) +#define SPI_MEM_RXFIFO_RST_M (BIT(30)) +#define SPI_MEM_RXFIFO_RST_V 0x1 +#define SPI_MEM_RXFIFO_RST_S 30 +/* SPI_MEM_FAST_WRITE_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: Set this bit to write data faster, do not wait write data has been stored in tx_ +bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored +in tx_bus_fifo_l2..*/ +#define SPI_MEM_FAST_WRITE_EN (BIT(29)) +#define SPI_MEM_FAST_WRITE_EN_M (BIT(29)) +#define SPI_MEM_FAST_WRITE_EN_V 0x1 +#define SPI_MEM_FAST_WRITE_EN_S 29 +/* SPI_MEM_DUAL_RAM_EN : HRO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at +the same time..*/ +#define SPI_MEM_DUAL_RAM_EN (BIT(28)) +#define SPI_MEM_DUAL_RAM_EN_M (BIT(28)) +#define SPI_MEM_DUAL_RAM_EN_V 0x1 +#define SPI_MEM_DUAL_RAM_EN_S 28 +/* SPI_MEM_RAM0_EN : HRO ;bitpos:[27] ;default: 1'b1 ; */ +/*description: When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be ac +cessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 wi +ll be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be ac +cessed at the same time..*/ +#define SPI_MEM_RAM0_EN (BIT(27)) +#define SPI_MEM_RAM0_EN_M (BIT(27)) +#define SPI_MEM_RAM0_EN_V 0x1 +#define SPI_MEM_RAM0_EN_S 27 +/* SPI_MEM_AW_SPLICE_EN : HRO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to enable AXI Write Splice-transfer..*/ +#define SPI_MEM_AW_SPLICE_EN (BIT(26)) +#define SPI_MEM_AW_SPLICE_EN_M (BIT(26)) +#define SPI_MEM_AW_SPLICE_EN_V 0x1 +#define SPI_MEM_AW_SPLICE_EN_S 26 +/* SPI_MEM_AR_SPLICE_EN : HRO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Set this bit to enable AXI Read Splice-transfer..*/ +#define SPI_MEM_AR_SPLICE_EN (BIT(25)) +#define SPI_MEM_AR_SPLICE_EN_M (BIT(25)) +#define SPI_MEM_AR_SPLICE_EN_V 0x1 +#define SPI_MEM_AR_SPLICE_EN_S 25 +/* SPI_MEM_RRESP_ECC_ERR_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY + when there is a ECC error in AXI read data. The ECC error information is record +ed in SPI_MEM_ECC_ERR_ADDR_REG..*/ +#define SPI_MEM_RRESP_ECC_ERR_EN (BIT(24)) +#define SPI_MEM_RRESP_ECC_ERR_EN_M (BIT(24)) +#define SPI_MEM_RRESP_ECC_ERR_EN_V 0x1 +#define SPI_MEM_RRESP_ECC_ERR_EN_S 24 +/* SPI_MEM_AXI_RDATA_BACK_FAST : HRO ;bitpos:[23] ;default: 1'b1 ; */ +/*description: 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: R +eply AXI read data to AXI bus when all the read data is available..*/ +#define SPI_MEM_AXI_RDATA_BACK_FAST (BIT(23)) +#define SPI_MEM_AXI_RDATA_BACK_FAST_M (BIT(23)) +#define SPI_MEM_AXI_RDATA_BACK_FAST_V 0x1 +#define SPI_MEM_AXI_RDATA_BACK_FAST_S 23 +/* SPI_MEM_AW_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR..*/ +#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN (BIT(22)) +#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_M (BIT(22)) +#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_V 0x1 +#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_S 22 +/* SPI_MEM_AR_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and repl +y the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR..*/ +#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN (BIT(21)) +#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_M (BIT(21)) +#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_V 0x1 +#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_S 21 +/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */ +/*description: After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 5 +12) SPI_CLK cycles..*/ +#define SPI_MEM_CS_HOLD_DLY_RES 0x000003FF +#define SPI_MEM_CS_HOLD_DLY_RES_M ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S)) +#define SPI_MEM_CS_HOLD_DLY_RES_V 0x3FF +#define SPI_MEM_CS_HOLD_DLY_RES_S 2 +/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye +d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti +ve 3: SPI clock is alwasy on..*/ +#define SPI_MEM_CLK_MODE 0x00000003 +#define SPI_MEM_CLK_MODE_M ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S)) +#define SPI_MEM_CLK_MODE_V 0x3 +#define SPI_MEM_CLK_MODE_S 0 + +#define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x10) +/* SPI_MEM_SYNC_RESET : WT ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The spi0_mst_st and spi0_slv_st will be reset..*/ +#define SPI_MEM_SYNC_RESET (BIT(31)) +#define SPI_MEM_SYNC_RESET_M (BIT(31)) +#define SPI_MEM_SYNC_RESET_V 0x1 +#define SPI_MEM_SYNC_RESET_S 31 +/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */ +/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran +sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core + clock cycles..*/ +#define SPI_MEM_CS_HOLD_DELAY 0x0000003F +#define SPI_MEM_CS_HOLD_DELAY_M ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S)) +#define SPI_MEM_CS_HOLD_DELAY_V 0x3F +#define SPI_MEM_CS_HOLD_DELAY_S 25 +/* SPI_MEM_SPLIT_TRANS_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Set this bit to enable SPI0 split one AXI read flash transfer into two SPI trans +fers when one transfer will cross flash or EXT_RAM page corner, valid no matter +whether there is an ECC region or not..*/ +#define SPI_MEM_SPLIT_TRANS_EN (BIT(24)) +#define SPI_MEM_SPLIT_TRANS_EN_M (BIT(24)) +#define SPI_MEM_SPLIT_TRANS_EN_V 0x1 +#define SPI_MEM_SPLIT_TRANS_EN_S 24 +/* SPI_MEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe +n accesses flash..*/ +#define SPI_MEM_ECC_16TO18_BYTE_EN (BIT(14)) +#define SPI_MEM_ECC_16TO18_BYTE_EN_M (BIT(14)) +#define SPI_MEM_ECC_16TO18_BYTE_EN_V 0x1 +#define SPI_MEM_ECC_16TO18_BYTE_EN_S 14 +/* SPI_MEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[13] ;default: 1'b1 ; */ +/*description: 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner w +hen accesses flash..*/ +#define SPI_MEM_ECC_SKIP_PAGE_CORNER (BIT(13)) +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M (BIT(13)) +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V 0x1 +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S 13 +/* SPI_MEM_ECC_CS_HOLD_TIME : HRO ;bitpos:[12:10] ;default: 3'd3 ; */ +/*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC + mode when accessed flash..*/ +#define SPI_MEM_ECC_CS_HOLD_TIME 0x00000007 +#define SPI_MEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_ECC_CS_HOLD_TIME_S)) +#define SPI_MEM_ECC_CS_HOLD_TIME_V 0x7 +#define SPI_MEM_ECC_CS_HOLD_TIME_S 10 +/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */ +/*description: SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined wi +th SPI_MEM_CS_HOLD bit..*/ +#define SPI_MEM_CS_HOLD_TIME 0x0000001F +#define SPI_MEM_CS_HOLD_TIME_M ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S)) +#define SPI_MEM_CS_HOLD_TIME_V 0x1F +#define SPI_MEM_CS_HOLD_TIME_S 5 +/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */ +/*description: (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_ME +M_CS_SETUP bit..*/ +#define SPI_MEM_CS_SETUP_TIME 0x0000001F +#define SPI_MEM_CS_SETUP_TIME_M ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S)) +#define SPI_MEM_CS_SETUP_TIME_V 0x1F +#define SPI_MEM_CS_SETUP_TIME_S 0 + +#define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14) +/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module + clock..*/ +#define SPI_MEM_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_CLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_MEM_CLK_EQU_SYSCLK_V 0x1 +#define SPI_MEM_CLK_EQU_SYSCLK_S 31 +/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */ +/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + system/(spi_mem_clkcnt_N+1).*/ +#define SPI_MEM_CLKCNT_N 0x000000FF +#define SPI_MEM_CLKCNT_N_M ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S)) +#define SPI_MEM_CLKCNT_N_V 0xFF +#define SPI_MEM_CLKCNT_N_S 16 +/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ +/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/ +#define SPI_MEM_CLKCNT_H 0x000000FF +#define SPI_MEM_CLKCNT_H_M ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S)) +#define SPI_MEM_CLKCNT_H_V 0xFF +#define SPI_MEM_CLKCNT_H_S 8 +/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */ +/*description: In the master mode it must be equal to spi_mem_clkcnt_N..*/ +#define SPI_MEM_CLKCNT_L 0x000000FF +#define SPI_MEM_CLKCNT_L_M ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S)) +#define SPI_MEM_CLKCNT_L_V 0xFF +#define SPI_MEM_CLKCNT_L_S 0 + +#define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18) +/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: This bit enable the command phase of an operation..*/ +#define SPI_MEM_USR_COMMAND (BIT(31)) +#define SPI_MEM_USR_COMMAND_M (BIT(31)) +#define SPI_MEM_USR_COMMAND_V 0x1 +#define SPI_MEM_USR_COMMAND_S 31 +/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: This bit enable the address phase of an operation..*/ +#define SPI_MEM_USR_ADDR (BIT(30)) +#define SPI_MEM_USR_ADDR_M (BIT(30)) +#define SPI_MEM_USR_ADDR_V 0x1 +#define SPI_MEM_USR_ADDR_S 30 +/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: This bit enable the dummy phase of an operation..*/ +#define SPI_MEM_USR_DUMMY (BIT(29)) +#define SPI_MEM_USR_DUMMY_M (BIT(29)) +#define SPI_MEM_USR_DUMMY_V 0x1 +#define SPI_MEM_USR_DUMMY_S 29 +/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: This bit enable the read-data phase of an operation..*/ +#define SPI_MEM_USR_MISO (BIT(28)) +#define SPI_MEM_USR_MISO_M (BIT(28)) +#define SPI_MEM_USR_MISO_V 0x1 +#define SPI_MEM_USR_MISO_S 28 +/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: This bit enable the write-data phase of an operation..*/ +#define SPI_MEM_USR_MOSI (BIT(27)) +#define SPI_MEM_USR_MOSI_M (BIT(27)) +#define SPI_MEM_USR_MOSI_V 0x1 +#define SPI_MEM_USR_MOSI_S 27 +/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: spi clock is disable in dummy phase when the bit is enable..*/ +#define SPI_MEM_USR_DUMMY_IDLE (BIT(26)) +#define SPI_MEM_USR_DUMMY_IDLE_M (BIT(26)) +#define SPI_MEM_USR_DUMMY_IDLE_V 0x1 +#define SPI_MEM_USR_DUMMY_IDLE_S 26 +/* SPI_MEM_USR_MOSI_HIGHPART : HRO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. +1: enable 0: disable..*/ +#define SPI_MEM_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_MEM_USR_MOSI_HIGHPART_M (BIT(25)) +#define SPI_MEM_USR_MOSI_HIGHPART_V 0x1 +#define SPI_MEM_USR_MOSI_HIGHPART_S 25 +/* SPI_MEM_USR_MISO_HIGHPART : HRO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1 +: enable 0: disable..*/ +#define SPI_MEM_USR_MISO_HIGHPART (BIT(24)) +#define SPI_MEM_USR_MISO_HIGHPART_M (BIT(24)) +#define SPI_MEM_USR_MISO_HIGHPART_V 0x1 +#define SPI_MEM_USR_MISO_HIGHPART_S 24 +/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: In the write operations address phase and read-data phase apply 4 signals..*/ +#define SPI_MEM_FWRITE_QIO (BIT(15)) +#define SPI_MEM_FWRITE_QIO_M (BIT(15)) +#define SPI_MEM_FWRITE_QIO_V 0x1 +#define SPI_MEM_FWRITE_QIO_S 15 +/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: In the write operations address phase and read-data phase apply 2 signals..*/ +#define SPI_MEM_FWRITE_DIO (BIT(14)) +#define SPI_MEM_FWRITE_DIO_M (BIT(14)) +#define SPI_MEM_FWRITE_DIO_V 0x1 +#define SPI_MEM_FWRITE_DIO_S 14 +/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 4 signals.*/ +#define SPI_MEM_FWRITE_QUAD (BIT(13)) +#define SPI_MEM_FWRITE_QUAD_M (BIT(13)) +#define SPI_MEM_FWRITE_QUAD_V 0x1 +#define SPI_MEM_FWRITE_QUAD_S 13 +/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 2 signals.*/ +#define SPI_MEM_FWRITE_DUAL (BIT(12)) +#define SPI_MEM_FWRITE_DUAL_M (BIT(12)) +#define SPI_MEM_FWRITE_DUAL_V 0x1 +#define SPI_MEM_FWRITE_DUAL_S 12 +/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3..*/ +#define SPI_MEM_CK_OUT_EDGE (BIT(9)) +#define SPI_MEM_CK_OUT_EDGE_M (BIT(9)) +#define SPI_MEM_CK_OUT_EDGE_V 0x1 +#define SPI_MEM_CK_OUT_EDGE_S 9 +/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: spi cs is enable when spi is in prepare phase. 1: enable 0: disable..*/ +#define SPI_MEM_CS_SETUP (BIT(7)) +#define SPI_MEM_CS_SETUP_M (BIT(7)) +#define SPI_MEM_CS_SETUP_V 0x1 +#define SPI_MEM_CS_SETUP_S 7 +/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: spi cs keep low when spi is in done phase. 1: enable 0: disable..*/ +#define SPI_MEM_CS_HOLD (BIT(6)) +#define SPI_MEM_CS_HOLD_M (BIT(6)) +#define SPI_MEM_CS_HOLD_V 0x1 +#define SPI_MEM_CS_HOLD_S 6 + +#define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x1C) +/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */ +/*description: The length in bits of address phase. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_USR_ADDR_BITLEN 0x0000003F +#define SPI_MEM_USR_ADDR_BITLEN_M ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S)) +#define SPI_MEM_USR_ADDR_BITLEN_V 0x3F +#define SPI_MEM_USR_ADDR_BITLEN_S 26 +/* SPI_MEM_USR_DBYTELEN : HRO ;bitpos:[8:6] ;default: 3'd1 ; */ +/*description: SPI0 USR_CMD read or write data byte length -1.*/ +#define SPI_MEM_USR_DBYTELEN 0x00000007 +#define SPI_MEM_USR_DBYTELEN_M ((SPI_MEM_USR_DBYTELEN_V)<<(SPI_MEM_USR_DBYTELEN_S)) +#define SPI_MEM_USR_DBYTELEN_V 0x7 +#define SPI_MEM_USR_DBYTELEN_S 6 +/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */ +/*description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cy +cle_num-1)..*/ +#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_USR_DUMMY_CYCLELEN_M ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S)) +#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 + +#define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20) +/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ +/*description: The length in bits of command phase. The register value shall be (bit_num-1).*/ +#define SPI_MEM_USR_COMMAND_BITLEN 0x0000000F +#define SPI_MEM_USR_COMMAND_BITLEN_M ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S)) +#define SPI_MEM_USR_COMMAND_BITLEN_V 0xF +#define SPI_MEM_USR_COMMAND_BITLEN_S 28 +/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: The value of command..*/ +#define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFF +#define SPI_MEM_USR_COMMAND_VALUE_M ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S)) +#define SPI_MEM_USR_COMMAND_VALUE_V 0xFFFF +#define SPI_MEM_USR_COMMAND_VALUE_S 0 + +#define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x24) +/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: The length in bits of write-data. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_USR_MOSI_DBITLEN 0x000003FF +#define SPI_MEM_USR_MOSI_DBITLEN_M ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S)) +#define SPI_MEM_USR_MOSI_DBITLEN_V 0x3FF +#define SPI_MEM_USR_MOSI_DBITLEN_S 0 + +#define SPI_MEM_MISO_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x28) +/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: The length in bits of read-data. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_USR_MISO_DBITLEN 0x000003FF +#define SPI_MEM_USR_MISO_DBITLEN_M ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S)) +#define SPI_MEM_USR_MISO_DBITLEN_V 0x3FF +#define SPI_MEM_USR_MISO_DBITLEN_S 0 + +#define SPI_MEM_RD_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x2C) +/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */ +/*description: Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode b +it..*/ +#define SPI_MEM_WB_MODE 0x000000FF +#define SPI_MEM_WB_MODE_M ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S)) +#define SPI_MEM_WB_MODE_V 0xFF +#define SPI_MEM_WB_MODE_S 16 +/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit..*/ +#define SPI_MEM_STATUS 0x0000FFFF +#define SPI_MEM_STATUS_M ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S)) +#define SPI_MEM_STATUS_V 0xFFFF +#define SPI_MEM_STATUS_S 0 + +#define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x34) +/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: SPI_CS line keep low when the bit is set..*/ +#define SPI_MEM_CS_KEEP_ACTIVE (BIT(10)) +#define SPI_MEM_CS_KEEP_ACTIVE_M (BIT(10)) +#define SPI_MEM_CS_KEEP_ACTIVE_V 0x1 +#define SPI_MEM_CS_KEEP_ACTIVE_S 10 +/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: 1: SPI_CLK line is high when idle 0: spi clk line is low when idle.*/ +#define SPI_MEM_CK_IDLE_EDGE (BIT(9)) +#define SPI_MEM_CK_IDLE_EDGE_M (BIT(9)) +#define SPI_MEM_CK_IDLE_EDGE_V 0x1 +#define SPI_MEM_CK_IDLE_EDGE_S 9 +/* SPI_MEM_SSUB_PIN : HRO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: For SPI0, sram is connected to SUBPINs..*/ +#define SPI_MEM_SSUB_PIN (BIT(8)) +#define SPI_MEM_SSUB_PIN_M (BIT(8)) +#define SPI_MEM_SSUB_PIN_V 0x1 +#define SPI_MEM_SSUB_PIN_S 8 +/* SPI_MEM_FSUB_PIN : HRO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: For SPI0, flash is connected to SUBPINs..*/ +#define SPI_MEM_FSUB_PIN (BIT(7)) +#define SPI_MEM_FSUB_PIN_M (BIT(7)) +#define SPI_MEM_FSUB_PIN_V 0x1 +#define SPI_MEM_FSUB_PIN_S 7 +/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI d +evice, such as flash, external RAM and so on..*/ +#define SPI_MEM_CS1_DIS (BIT(1)) +#define SPI_MEM_CS1_DIS_M (BIT(1)) +#define SPI_MEM_CS1_DIS_V 0x1 +#define SPI_MEM_CS1_DIS_S 1 +/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI d +evice, such as flash, external RAM and so on..*/ +#define SPI_MEM_CS0_DIS (BIT(0)) +#define SPI_MEM_CS0_DIS_M (BIT(0)) +#define SPI_MEM_CS0_DIS_V 0x1 +#define SPI_MEM_CS0_DIS_S 0 + +#define SPI_MEM_TX_CRC_REG(i) (REG_SPI_MEM_BASE(i) + 0x38) +/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: For SPI1, the value of crc32..*/ +#define SPI_MEM_TX_CRC_DATA 0xFFFFFFFF +#define SPI_MEM_TX_CRC_DATA_M ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S)) +#define SPI_MEM_TX_CRC_DATA_V 0xFFFFFFFF +#define SPI_MEM_TX_CRC_DATA_S 0 + +#define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x3C) +/* SPI_MEM_CLOSE_AXI_INF_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: Set this bit to close AXI read/write transfer to MSPI, which means that only SLV +_ERR will be replied to BRESP/RRESP..*/ +#define SPI_MEM_CLOSE_AXI_INF_EN (BIT(31)) +#define SPI_MEM_CLOSE_AXI_INF_EN_M (BIT(31)) +#define SPI_MEM_CLOSE_AXI_INF_EN_V 0x1 +#define SPI_MEM_CLOSE_AXI_INF_EN_S 31 +/* SPI_MEM_SAME_AW_AR_ADDR_CHK_EN : HRO ;bitpos:[30] ;default: 1'b1 ; */ +/*description: Set this bit to check AXI read/write the same address region..*/ +#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN (BIT(30)) +#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_M (BIT(30)) +#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_V 0x1 +#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_S 30 +/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is + the same with spi_mem_fread_qio..*/ +#define SPI_MEM_FADDR_QUAD (BIT(8)) +#define SPI_MEM_FADDR_QUAD_M (BIT(8)) +#define SPI_MEM_FADDR_QUAD_V 0x1 +#define SPI_MEM_FADDR_QUAD_S 8 +/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is th +e same with spi_mem_fread_qio..*/ +#define SPI_MEM_FDOUT_QUAD (BIT(7)) +#define SPI_MEM_FDOUT_QUAD_M (BIT(7)) +#define SPI_MEM_FDOUT_QUAD_V 0x1 +#define SPI_MEM_FDOUT_QUAD_S 7 +/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the + same with spi_mem_fread_qio..*/ +#define SPI_MEM_FDIN_QUAD (BIT(6)) +#define SPI_MEM_FDIN_QUAD_M (BIT(6)) +#define SPI_MEM_FDIN_QUAD_V 0x1 +#define SPI_MEM_FDIN_QUAD_S 6 +/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is + the same with spi_mem_fread_dio..*/ +#define SPI_MEM_FADDR_DUAL (BIT(5)) +#define SPI_MEM_FADDR_DUAL_M (BIT(5)) +#define SPI_MEM_FADDR_DUAL_V 0x1 +#define SPI_MEM_FADDR_DUAL_S 5 +/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the + same with spi_mem_fread_dio..*/ +#define SPI_MEM_FDOUT_DUAL (BIT(4)) +#define SPI_MEM_FDOUT_DUAL_M (BIT(4)) +#define SPI_MEM_FDOUT_DUAL_V 0x1 +#define SPI_MEM_FDOUT_DUAL_S 4 +/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the +same with spi_mem_fread_dio..*/ +#define SPI_MEM_FDIN_DUAL (BIT(3)) +#define SPI_MEM_FDIN_DUAL_M (BIT(3)) +#define SPI_MEM_FDIN_DUAL_V 0x1 +#define SPI_MEM_FDIN_DUAL_S 3 +/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: For SPI0, cache read flash for user define command, 1: enable, 0:disable..*/ +#define SPI_MEM_CACHE_FLASH_USR_CMD (BIT(2)) +#define SPI_MEM_CACHE_FLASH_USR_CMD_M (BIT(2)) +#define SPI_MEM_CACHE_FLASH_USR_CMD_V 0x1 +#define SPI_MEM_CACHE_FLASH_USR_CMD_S 2 +/* SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable..*/ +#define SPI_MEM_CACHE_USR_ADDR_4BYTE (BIT(1)) +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M (BIT(1)) +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V 0x1 +#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S 1 +/* SPI_MEM_AXI_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For SPI0, AXI master access enable, 1: enable, 0:disable..*/ +#define SPI_MEM_AXI_REQ_EN (BIT(0)) +#define SPI_MEM_AXI_REQ_EN_M (BIT(0)) +#define SPI_MEM_AXI_REQ_EN_V 0x1 +#define SPI_MEM_AXI_REQ_EN_S 0 + +#define SPI_MEM_CACHE_SCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x40) +/* SPI_MEM_SRAM_WDUMMY_CYCLELEN : HRO ;bitpos:[27:22] ;default: 6'b1 ; */ +/*description: For SPI0, In the external RAM mode, it is the length in bits of write dummy phas +e. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_WDUMMY_CYCLELEN_S)) +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S 22 +/* SPI_MEM_SRAM_OCT : HRO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: reserved.*/ +#define SPI_MEM_SRAM_OCT (BIT(21)) +#define SPI_MEM_SRAM_OCT_M (BIT(21)) +#define SPI_MEM_SRAM_OCT_V 0x1 +#define SPI_MEM_SRAM_OCT_S 21 +/* SPI_MEM_CACHE_SRAM_USR_WCMD : HRO ;bitpos:[20] ;default: 1'b1 ; */ +/*description: For SPI0, In the external RAM mode cache write sram for user define command.*/ +#define SPI_MEM_CACHE_SRAM_USR_WCMD (BIT(20)) +#define SPI_MEM_CACHE_SRAM_USR_WCMD_M (BIT(20)) +#define SPI_MEM_CACHE_SRAM_USR_WCMD_V 0x1 +#define SPI_MEM_CACHE_SRAM_USR_WCMD_S 20 +/* SPI_MEM_SRAM_ADDR_BITLEN : HRO ;bitpos:[19:14] ;default: 6'd23 ; */ +/*description: For SPI0, In the external RAM mode, it is the length in bits of address phase. T +he register value shall be (bit_num-1)..*/ +#define SPI_MEM_SRAM_ADDR_BITLEN 0x0000003F +#define SPI_MEM_SRAM_ADDR_BITLEN_M ((SPI_MEM_SRAM_ADDR_BITLEN_V)<<(SPI_MEM_SRAM_ADDR_BITLEN_S)) +#define SPI_MEM_SRAM_ADDR_BITLEN_V 0x3F +#define SPI_MEM_SRAM_ADDR_BITLEN_S 14 +/* SPI_MEM_SRAM_RDUMMY_CYCLELEN : HRO ;bitpos:[11:6] ;default: 6'b1 ; */ +/*description: For SPI0, In the external RAM mode, it is the length in bits of read dummy phase +. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_RDUMMY_CYCLELEN_S)) +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6 +/* SPI_MEM_CACHE_SRAM_USR_RCMD : HRO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: For SPI0, In the external RAM mode cache read external RAM for user define comma +nd..*/ +#define SPI_MEM_CACHE_SRAM_USR_RCMD (BIT(5)) +#define SPI_MEM_CACHE_SRAM_USR_RCMD_M (BIT(5)) +#define SPI_MEM_CACHE_SRAM_USR_RCMD_V 0x1 +#define SPI_MEM_CACHE_SRAM_USR_RCMD_S 5 +/* SPI_MEM_USR_RD_SRAM_DUMMY : HRO ;bitpos:[4] ;default: 1'b1 ; */ +/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read + operations..*/ +#define SPI_MEM_USR_RD_SRAM_DUMMY (BIT(4)) +#define SPI_MEM_USR_RD_SRAM_DUMMY_M (BIT(4)) +#define SPI_MEM_USR_RD_SRAM_DUMMY_V 0x1 +#define SPI_MEM_USR_RD_SRAM_DUMMY_S 4 +/* SPI_MEM_USR_WR_SRAM_DUMMY : HRO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for writ +e operations..*/ +#define SPI_MEM_USR_WR_SRAM_DUMMY (BIT(3)) +#define SPI_MEM_USR_WR_SRAM_DUMMY_M (BIT(3)) +#define SPI_MEM_USR_WR_SRAM_DUMMY_V 0x1 +#define SPI_MEM_USR_WR_SRAM_DUMMY_S 3 +/* SPI_MEM_USR_SRAM_QIO : HRO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disab +le.*/ +#define SPI_MEM_USR_SRAM_QIO (BIT(2)) +#define SPI_MEM_USR_SRAM_QIO_M (BIT(2)) +#define SPI_MEM_USR_SRAM_QIO_V 0x1 +#define SPI_MEM_USR_SRAM_QIO_S 2 +/* SPI_MEM_USR_SRAM_DIO : HRO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disab +le.*/ +#define SPI_MEM_USR_SRAM_DIO (BIT(1)) +#define SPI_MEM_USR_SRAM_DIO_M (BIT(1)) +#define SPI_MEM_USR_SRAM_DIO_V 0x1 +#define SPI_MEM_USR_SRAM_DIO_S 1 +/* SPI_MEM_CACHE_USR_SADDR_4BYTE : HRO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: en +able, 0:disable..*/ +#define SPI_MEM_CACHE_USR_SADDR_4BYTE (BIT(0)) +#define SPI_MEM_CACHE_USR_SADDR_4BYTE_M (BIT(0)) +#define SPI_MEM_CACHE_USR_SADDR_4BYTE_V 0x1 +#define SPI_MEM_CACHE_USR_SADDR_4BYTE_S 0 + +#define SPI_MEM_SRAM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x44) +/* SPI_MEM_SMEM_DATA_IE_ALWAYS_ON : HRO ;bitpos:[31] ;default: 1'b1 ; */ +/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0 +] are always 1. 0: Others..*/ +#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON (BIT(31)) +#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_M (BIT(31)) +#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_V 0x1 +#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_S 31 +/* SPI_MEM_SMEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b1 ; */ +/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS ar +e always 1. 0: Others..*/ +#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON (BIT(30)) +#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_M (BIT(30)) +#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_V 0x1 +#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_S 30 +/* SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT : HRO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM, + the level of SPI_IO[7:0] is output by the MSPI controller..*/ +#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT (BIT(25)) +#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_M (BIT(25)) +#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_V 0x1 +#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_S 25 +/* SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM, + the level of SPI_DQS is output by the MSPI controller..*/ +#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT (BIT(24)) +#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_M (BIT(24)) +#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_V 0x1 +#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_S 24 +/* SPI_MEM_SDUMMY_WOUT : HRO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: In the dummy phase of a MSPI write data transfer when accesses to external RAM, +the signal level of SPI bus is output by the MSPI controller..*/ +#define SPI_MEM_SDUMMY_WOUT (BIT(23)) +#define SPI_MEM_SDUMMY_WOUT_M (BIT(23)) +#define SPI_MEM_SDUMMY_WOUT_V 0x1 +#define SPI_MEM_SDUMMY_WOUT_S 23 +/* SPI_MEM_SDUMMY_RIN : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: In the dummy phase of a MSPI read data transfer when accesses to external RAM, t +he signal level of SPI bus is output by the MSPI controller..*/ +#define SPI_MEM_SDUMMY_RIN (BIT(22)) +#define SPI_MEM_SDUMMY_RIN_M (BIT(22)) +#define SPI_MEM_SDUMMY_RIN_V 0x1 +#define SPI_MEM_SDUMMY_RIN_S 22 +/* SPI_MEM_SCMD_OCT : HRO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable..*/ +#define SPI_MEM_SCMD_OCT (BIT(21)) +#define SPI_MEM_SCMD_OCT_M (BIT(21)) +#define SPI_MEM_SCMD_OCT_V 0x1 +#define SPI_MEM_SCMD_OCT_S 21 +/* SPI_MEM_SADDR_OCT : HRO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable..*/ +#define SPI_MEM_SADDR_OCT (BIT(20)) +#define SPI_MEM_SADDR_OCT_M (BIT(20)) +#define SPI_MEM_SADDR_OCT_V 0x1 +#define SPI_MEM_SADDR_OCT_S 20 +/* SPI_MEM_SDOUT_OCT : HRO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable..*/ +#define SPI_MEM_SDOUT_OCT (BIT(19)) +#define SPI_MEM_SDOUT_OCT_M (BIT(19)) +#define SPI_MEM_SDOUT_OCT_V 0x1 +#define SPI_MEM_SDOUT_OCT_S 19 +/* SPI_MEM_SDIN_OCT : HRO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable..*/ +#define SPI_MEM_SDIN_OCT (BIT(18)) +#define SPI_MEM_SDIN_OCT_M (BIT(18)) +#define SPI_MEM_SDIN_OCT_V 0x1 +#define SPI_MEM_SDIN_OCT_S 18 +/* SPI_MEM_SCMD_QUAD : HRO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit + is the same with spi_mem_usr_sram_qio..*/ +#define SPI_MEM_SCMD_QUAD (BIT(17)) +#define SPI_MEM_SCMD_QUAD_M (BIT(17)) +#define SPI_MEM_SCMD_QUAD_V 0x1 +#define SPI_MEM_SCMD_QUAD_S 17 +/* SPI_MEM_SADDR_QUAD : HRO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The + bit is the same with spi_mem_usr_sram_qio..*/ +#define SPI_MEM_SADDR_QUAD (BIT(16)) +#define SPI_MEM_SADDR_QUAD_M (BIT(16)) +#define SPI_MEM_SADDR_QUAD_V 0x1 +#define SPI_MEM_SADDR_QUAD_S 16 +/* SPI_MEM_SDOUT_QUAD : HRO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bi +t is the same with spi_mem_usr_sram_qio..*/ +#define SPI_MEM_SDOUT_QUAD (BIT(15)) +#define SPI_MEM_SDOUT_QUAD_M (BIT(15)) +#define SPI_MEM_SDOUT_QUAD_V 0x1 +#define SPI_MEM_SDOUT_QUAD_S 15 +/* SPI_MEM_SDIN_QUAD : HRO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit + is the same with spi_mem_usr_sram_qio..*/ +#define SPI_MEM_SDIN_QUAD (BIT(14)) +#define SPI_MEM_SDIN_QUAD_M (BIT(14)) +#define SPI_MEM_SDIN_QUAD_V 0x1 +#define SPI_MEM_SDIN_QUAD_S 14 +/* SPI_MEM_SADDR_DUAL : HRO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The + bit is the same with spi_mem_usr_sram_dio..*/ +#define SPI_MEM_SADDR_DUAL (BIT(12)) +#define SPI_MEM_SADDR_DUAL_M (BIT(12)) +#define SPI_MEM_SADDR_DUAL_V 0x1 +#define SPI_MEM_SADDR_DUAL_S 12 +/* SPI_MEM_SDOUT_DUAL : HRO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bi +t is the same with spi_mem_usr_sram_dio..*/ +#define SPI_MEM_SDOUT_DUAL (BIT(11)) +#define SPI_MEM_SDOUT_DUAL_M (BIT(11)) +#define SPI_MEM_SDOUT_DUAL_V 0x1 +#define SPI_MEM_SDOUT_DUAL_S 11 +/* SPI_MEM_SDIN_DUAL : HRO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit + is the same with spi_mem_usr_sram_dio..*/ +#define SPI_MEM_SDIN_DUAL (BIT(10)) +#define SPI_MEM_SDIN_DUAL_M (BIT(10)) +#define SPI_MEM_SDIN_DUAL_V 0x1 +#define SPI_MEM_SDIN_DUAL_S 10 +/* SPI_MEM_SWB_MODE : HRO ;bitpos:[9:2] ;default: 8'b0 ; */ +/*description: Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd +_mode bit..*/ +#define SPI_MEM_SWB_MODE 0x000000FF +#define SPI_MEM_SWB_MODE_M ((SPI_MEM_SWB_MODE_V)<<(SPI_MEM_SWB_MODE_S)) +#define SPI_MEM_SWB_MODE_V 0xFF +#define SPI_MEM_SWB_MODE_S 2 +/* SPI_MEM_SCLK_MODE : HRO ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye +d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti +ve 3: SPI clock is always on..*/ +#define SPI_MEM_SCLK_MODE 0x00000003 +#define SPI_MEM_SCLK_MODE_M ((SPI_MEM_SCLK_MODE_V)<<(SPI_MEM_SCLK_MODE_S)) +#define SPI_MEM_SCLK_MODE_V 0x3 +#define SPI_MEM_SCLK_MODE_S 0 + +#define SPI_MEM_SRAM_DRD_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x48) +/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : HRO ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: For SPI0,When cache mode is enable it is the length in bits of command phase for + sram. The register value shall be (bit_num-1)..*/ +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S)) +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 +/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : HRO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: For SPI0,When cache mode is enable it is the read command value of command phase + for sram..*/ +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S)) +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 + +#define SPI_MEM_SRAM_DWR_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x4C) +/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : HRO ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: For SPI0,When cache mode is enable it is the in bits of command phase for sram. + The register value shall be (bit_num-1)..*/ +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S)) +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 +/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : HRO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: For SPI0,When cache mode is enable it is the write command value of command phas +e for sram..*/ +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S)) +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 + +#define SPI_MEM_SRAM_CLK_REG(i) (REG_SPI_MEM_BASE(i) + 0x50) +/* SPI_MEM_SCLK_EQU_SYSCLK : HRO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_c +lk is divided from system clock..*/ +#define SPI_MEM_SCLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_SCLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_MEM_SCLK_EQU_SYSCLK_V 0x1 +#define SPI_MEM_SCLK_EQU_SYSCLK_S 31 +/* SPI_MEM_SCLKCNT_N : HRO ;bitpos:[23:16] ;default: 8'h3 ; */ +/*description: For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_c +lk frequency is system/(spi_mem_clkcnt_N+1).*/ +#define SPI_MEM_SCLKCNT_N 0x000000FF +#define SPI_MEM_SCLKCNT_N_M ((SPI_MEM_SCLKCNT_N_V)<<(SPI_MEM_SCLKCNT_N_S)) +#define SPI_MEM_SCLKCNT_N_V 0xFF +#define SPI_MEM_SCLKCNT_N_S 16 +/* SPI_MEM_SCLKCNT_H : HRO ;bitpos:[15:8] ;default: 8'h1 ; */ +/*description: For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/ +#define SPI_MEM_SCLKCNT_H 0x000000FF +#define SPI_MEM_SCLKCNT_H_M ((SPI_MEM_SCLKCNT_H_V)<<(SPI_MEM_SCLKCNT_H_S)) +#define SPI_MEM_SCLKCNT_H_V 0xFF +#define SPI_MEM_SCLKCNT_H_S 8 +/* SPI_MEM_SCLKCNT_L : HRO ;bitpos:[7:0] ;default: 8'h3 ; */ +/*description: For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N..*/ +#define SPI_MEM_SCLKCNT_L 0x000000FF +#define SPI_MEM_SCLKCNT_L_M ((SPI_MEM_SCLKCNT_L_V)<<(SPI_MEM_SCLKCNT_L_S)) +#define SPI_MEM_SCLKCNT_L_V 0xFF +#define SPI_MEM_SCLKCNT_L_S 0 + +#define SPI_MEM_FSM_REG(i) (REG_SPI_MEM_BASE(i) + 0x54) +/* SPI_MEM_LOCK_DELAY_TIME : R/W ;bitpos:[11:7] ;default: 5'd4 ; */ +/*description: The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1..*/ +#define SPI_MEM_LOCK_DELAY_TIME 0x0000001F +#define SPI_MEM_LOCK_DELAY_TIME_M ((SPI_MEM_LOCK_DELAY_TIME_V)<<(SPI_MEM_LOCK_DELAY_TIME_S)) +#define SPI_MEM_LOCK_DELAY_TIME_V 0x1F +#define SPI_MEM_LOCK_DELAY_TIME_S 7 + +#define SPI_MEM_W0_REG(i) (REG_SPI_MEM_BASE(i) + 0x58) +/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF0 0xFFFFFFFF +#define SPI_MEM_BUF0_M ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S)) +#define SPI_MEM_BUF0_V 0xFFFFFFFF +#define SPI_MEM_BUF0_S 0 + +#define SPI_MEM_W1_REG(i) (REG_SPI_MEM_BASE(i) + 0x5C) +/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF1 0xFFFFFFFF +#define SPI_MEM_BUF1_M ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S)) +#define SPI_MEM_BUF1_V 0xFFFFFFFF +#define SPI_MEM_BUF1_S 0 + +#define SPI_MEM_W2_REG(i) (REG_SPI_MEM_BASE(i) + 0x60) +/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF2 0xFFFFFFFF +#define SPI_MEM_BUF2_M ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S)) +#define SPI_MEM_BUF2_V 0xFFFFFFFF +#define SPI_MEM_BUF2_S 0 + +#define SPI_MEM_W3_REG(i) (REG_SPI_MEM_BASE(i) + 0x64) +/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF3 0xFFFFFFFF +#define SPI_MEM_BUF3_M ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S)) +#define SPI_MEM_BUF3_V 0xFFFFFFFF +#define SPI_MEM_BUF3_S 0 + +#define SPI_MEM_W4_REG(i) (REG_SPI_MEM_BASE(i) + 0x68) +/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF4 0xFFFFFFFF +#define SPI_MEM_BUF4_M ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S)) +#define SPI_MEM_BUF4_V 0xFFFFFFFF +#define SPI_MEM_BUF4_S 0 + +#define SPI_MEM_W5_REG(i) (REG_SPI_MEM_BASE(i) + 0x6C) +/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF5 0xFFFFFFFF +#define SPI_MEM_BUF5_M ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S)) +#define SPI_MEM_BUF5_V 0xFFFFFFFF +#define SPI_MEM_BUF5_S 0 + +#define SPI_MEM_W6_REG(i) (REG_SPI_MEM_BASE(i) + 0x70) +/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF6 0xFFFFFFFF +#define SPI_MEM_BUF6_M ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S)) +#define SPI_MEM_BUF6_V 0xFFFFFFFF +#define SPI_MEM_BUF6_S 0 + +#define SPI_MEM_W7_REG(i) (REG_SPI_MEM_BASE(i) + 0x74) +/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF7 0xFFFFFFFF +#define SPI_MEM_BUF7_M ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S)) +#define SPI_MEM_BUF7_V 0xFFFFFFFF +#define SPI_MEM_BUF7_S 0 + +#define SPI_MEM_W8_REG(i) (REG_SPI_MEM_BASE(i) + 0x78) +/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF8 0xFFFFFFFF +#define SPI_MEM_BUF8_M ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S)) +#define SPI_MEM_BUF8_V 0xFFFFFFFF +#define SPI_MEM_BUF8_S 0 + +#define SPI_MEM_W9_REG(i) (REG_SPI_MEM_BASE(i) + 0x7C) +/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF9 0xFFFFFFFF +#define SPI_MEM_BUF9_M ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S)) +#define SPI_MEM_BUF9_V 0xFFFFFFFF +#define SPI_MEM_BUF9_S 0 + +#define SPI_MEM_W10_REG(i) (REG_SPI_MEM_BASE(i) + 0x80) +/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF10 0xFFFFFFFF +#define SPI_MEM_BUF10_M ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S)) +#define SPI_MEM_BUF10_V 0xFFFFFFFF +#define SPI_MEM_BUF10_S 0 + +#define SPI_MEM_W11_REG(i) (REG_SPI_MEM_BASE(i) + 0x84) +/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF11 0xFFFFFFFF +#define SPI_MEM_BUF11_M ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S)) +#define SPI_MEM_BUF11_V 0xFFFFFFFF +#define SPI_MEM_BUF11_S 0 + +#define SPI_MEM_W12_REG(i) (REG_SPI_MEM_BASE(i) + 0x88) +/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF12 0xFFFFFFFF +#define SPI_MEM_BUF12_M ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S)) +#define SPI_MEM_BUF12_V 0xFFFFFFFF +#define SPI_MEM_BUF12_S 0 + +#define SPI_MEM_W13_REG(i) (REG_SPI_MEM_BASE(i) + 0x8C) +/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF13 0xFFFFFFFF +#define SPI_MEM_BUF13_M ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S)) +#define SPI_MEM_BUF13_V 0xFFFFFFFF +#define SPI_MEM_BUF13_S 0 + +#define SPI_MEM_W14_REG(i) (REG_SPI_MEM_BASE(i) + 0x90) +/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF14 0xFFFFFFFF +#define SPI_MEM_BUF14_M ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S)) +#define SPI_MEM_BUF14_V 0xFFFFFFFF +#define SPI_MEM_BUF14_S 0 + +#define SPI_MEM_W15_REG(i) (REG_SPI_MEM_BASE(i) + 0x94) +/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer.*/ +#define SPI_MEM_BUF15 0xFFFFFFFF +#define SPI_MEM_BUF15_M ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S)) +#define SPI_MEM_BUF15_V 0xFFFFFFFF +#define SPI_MEM_BUF15_S 0 + +#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x98) +/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[31:16] ;default: 16'h05 ; */ +/*description: The command value to wait flash idle(RDSR)..*/ +#define SPI_MEM_WAITI_CMD 0x0000FFFF +#define SPI_MEM_WAITI_CMD_M ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S)) +#define SPI_MEM_WAITI_CMD_V 0xFFFF +#define SPI_MEM_WAITI_CMD_S 16 +/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */ +/*description: The dummy cycle length when wait flash idle(RDSR)..*/ +#define SPI_MEM_WAITI_DUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S)) +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S 10 +/* SPI_MEM_WAITI_CMD_2B : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: 1:The wait idle command bit length is 16. 0: The wait idle command bit length is + 8..*/ +#define SPI_MEM_WAITI_CMD_2B (BIT(9)) +#define SPI_MEM_WAITI_CMD_2B_M (BIT(9)) +#define SPI_MEM_WAITI_CMD_2B_V 0x1 +#define SPI_MEM_WAITI_CMD_2B_S 9 +/* SPI_MEM_WAITI_ADDR_CYCLELEN : R/W ;bitpos:[4:3] ;default: 2'b0 ; */ +/*description: When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI +_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when +SPI_MEM_WAITI_ADDR_EN is cleared..*/ +#define SPI_MEM_WAITI_ADDR_CYCLELEN 0x00000003 +#define SPI_MEM_WAITI_ADDR_CYCLELEN_M ((SPI_MEM_WAITI_ADDR_CYCLELEN_V)<<(SPI_MEM_WAITI_ADDR_CYCLELEN_S)) +#define SPI_MEM_WAITI_ADDR_CYCLELEN_V 0x3 +#define SPI_MEM_WAITI_ADDR_CYCLELEN_S 3 +/* SPI_MEM_WAITI_ADDR_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out ad +dress in RDSR or read SUS command transfer..*/ +#define SPI_MEM_WAITI_ADDR_EN (BIT(2)) +#define SPI_MEM_WAITI_ADDR_EN_M (BIT(2)) +#define SPI_MEM_WAITI_ADDR_EN_V 0x1 +#define SPI_MEM_WAITI_ADDR_EN_S 2 +/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The dummy phase enable when wait flash idle (RDSR).*/ +#define SPI_MEM_WAITI_DUMMY (BIT(1)) +#define SPI_MEM_WAITI_DUMMY_M (BIT(1)) +#define SPI_MEM_WAITI_DUMMY_V 0x1 +#define SPI_MEM_WAITI_DUMMY_S 1 +/* SPI_MEM_WAITI_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto + Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto +Suspend/Resume are not supported..*/ +#define SPI_MEM_WAITI_EN (BIT(0)) +#define SPI_MEM_WAITI_EN_M (BIT(0)) +#define SPI_MEM_WAITI_EN_V 0x1 +#define SPI_MEM_WAITI_EN_S 0 + +#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x9C) +/* SPI_MEM_SUS_TIMEOUT_CNT : R/W ;bitpos:[31:25] ;default: 7'h4 ; */ +/*description: When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, + it will be treated as check pass..*/ +#define SPI_MEM_SUS_TIMEOUT_CNT 0x0000007F +#define SPI_MEM_SUS_TIMEOUT_CNT_M ((SPI_MEM_SUS_TIMEOUT_CNT_V)<<(SPI_MEM_SUS_TIMEOUT_CNT_S)) +#define SPI_MEM_SUS_TIMEOUT_CNT_V 0x7F +#define SPI_MEM_SUS_TIMEOUT_CNT_S 25 +/* SPI_MEM_PES_END_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend statu +s of flash. 0: Only need to check WIP is 0..*/ +#define SPI_MEM_PES_END_EN (BIT(24)) +#define SPI_MEM_PES_END_EN_M (BIT(24)) +#define SPI_MEM_PES_END_EN_V 0x1 +#define SPI_MEM_PES_END_EN_S 24 +/* SPI_MEM_PER_END_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status + of flash. 0: Only need to check WIP is 0..*/ +#define SPI_MEM_PER_END_EN (BIT(23)) +#define SPI_MEM_PER_END_EN_M (BIT(23)) +#define SPI_MEM_PER_END_EN_V 0x1 +#define SPI_MEM_PER_END_EN_S 23 +/* SPI_MEM_FMEM_RD_SUS_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte w +hen check flash SUS/SUS1/SUS2 status bit.*/ +#define SPI_MEM_FMEM_RD_SUS_2B (BIT(22)) +#define SPI_MEM_FMEM_RD_SUS_2B_M (BIT(22)) +#define SPI_MEM_FMEM_RD_SUS_2B_V 0x1 +#define SPI_MEM_FMEM_RD_SUS_2B_S 22 +/* SPI_MEM_PESR_END_MSK : R/W ;bitpos:[21:6] ;default: 16'h80 ; */ +/*description: The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is +status_in[15:0](only status_in[7:0] is valid when only one byte of data is read +out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS +2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]..*/ +#define SPI_MEM_PESR_END_MSK 0x0000FFFF +#define SPI_MEM_PESR_END_MSK_M ((SPI_MEM_PESR_END_MSK_V)<<(SPI_MEM_PESR_END_MSK_S)) +#define SPI_MEM_PESR_END_MSK_V 0xFFFF +#define SPI_MEM_PESR_END_MSK_S 6 +/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable Auto-suspending function..*/ +#define SPI_MEM_FLASH_PES_EN (BIT(5)) +#define SPI_MEM_FLASH_PES_EN_M (BIT(5)) +#define SPI_MEM_FLASH_PES_EN_V 0x1 +#define SPI_MEM_FLASH_PES_EN_S 5 +/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to enable PES end triggers PER transfer option. If this bit is 0, a +pplication should send PER after PES is done..*/ +#define SPI_MEM_PES_PER_EN (BIT(4)) +#define SPI_MEM_PES_PER_EN_M (BIT(4)) +#define SPI_MEM_PES_PER_EN_V 0x1 +#define SPI_MEM_PES_PER_EN_S 4 +/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after +program erase suspend command is sent. 0: SPI1 does not wait after program erase + suspend command is sent..*/ +#define SPI_MEM_FLASH_PES_WAIT_EN (BIT(3)) +#define SPI_MEM_FLASH_PES_WAIT_EN_M (BIT(3)) +#define SPI_MEM_FLASH_PES_WAIT_EN_V 0x1 +#define SPI_MEM_FLASH_PES_WAIT_EN_S 3 +/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after +program erase resume command is sent. 0: SPI1 does not wait after program erase +resume command is sent..*/ +#define SPI_MEM_FLASH_PER_WAIT_EN (BIT(2)) +#define SPI_MEM_FLASH_PER_WAIT_EN_M (BIT(2)) +#define SPI_MEM_FLASH_PER_WAIT_EN_V 0x1 +#define SPI_MEM_FLASH_PER_WAIT_EN_S 2 +/* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */ +/*description: program erase suspend bit, program erase suspend operation will be triggered whe +n the bit is set. The bit will be cleared once the operation done.1: enable 0: d +isable..*/ +#define SPI_MEM_FLASH_PES (BIT(1)) +#define SPI_MEM_FLASH_PES_M (BIT(1)) +#define SPI_MEM_FLASH_PES_V 0x1 +#define SPI_MEM_FLASH_PES_S 1 +/* SPI_MEM_FLASH_PER : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */ +/*description: program erase resume bit, program erase suspend operation will be triggered when + the bit is set. The bit will be cleared once the operation done.1: enable 0: di +sable..*/ +#define SPI_MEM_FLASH_PER (BIT(0)) +#define SPI_MEM_FLASH_PER_M (BIT(0)) +#define SPI_MEM_FLASH_PER_V 0x1 +#define SPI_MEM_FLASH_PER_S 0 + +#define SPI_MEM_FLASH_SUS_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0xA0) +/* SPI_MEM_WAIT_PESR_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h05 ; */ +/*description: Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS +/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash +..*/ +#define SPI_MEM_WAIT_PESR_COMMAND 0x0000FFFF +#define SPI_MEM_WAIT_PESR_COMMAND_M ((SPI_MEM_WAIT_PESR_COMMAND_V)<<(SPI_MEM_WAIT_PESR_COMMAND_S)) +#define SPI_MEM_WAIT_PESR_COMMAND_V 0xFFFF +#define SPI_MEM_WAIT_PESR_COMMAND_S 16 +/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[15:0] ;default: 16'h7575 ; */ +/*description: Program/Erase suspend command..*/ +#define SPI_MEM_FLASH_PES_COMMAND 0x0000FFFF +#define SPI_MEM_FLASH_PES_COMMAND_M ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S)) +#define SPI_MEM_FLASH_PES_COMMAND_V 0xFFFF +#define SPI_MEM_FLASH_PES_COMMAND_S 0 + +#define SPI_MEM_SUS_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0xA4) +/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h7a7a ; */ +/*description: Program/Erase resume command..*/ +#define SPI_MEM_FLASH_PER_COMMAND 0x0000FFFF +#define SPI_MEM_FLASH_PER_COMMAND_M ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S)) +#define SPI_MEM_FLASH_PER_COMMAND_V 0xFFFF +#define SPI_MEM_FLASH_PER_COMMAND_S 16 +/* SPI_MEM_FLASH_PESR_CMD_2B : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit leng +th of Program/Erase Suspend/Resume command is 8..*/ +#define SPI_MEM_FLASH_PESR_CMD_2B (BIT(15)) +#define SPI_MEM_FLASH_PESR_CMD_2B_M (BIT(15)) +#define SPI_MEM_FLASH_PESR_CMD_2B_V 0x1 +#define SPI_MEM_FLASH_PESR_CMD_2B_S 15 +/* SPI_MEM_SPI0_LOCK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it..*/ +#define SPI_MEM_SPI0_LOCK_EN (BIT(7)) +#define SPI_MEM_SPI0_LOCK_EN_M (BIT(7)) +#define SPI_MEM_SPI0_LOCK_EN_V 0x1 +#define SPI_MEM_SPI0_LOCK_EN_S 7 +/* SPI_MEM_FLASH_PES_DLY_128 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_ +RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM +_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent..*/ +#define SPI_MEM_FLASH_PES_DLY_128 (BIT(6)) +#define SPI_MEM_FLASH_PES_DLY_128_M (BIT(6)) +#define SPI_MEM_FLASH_PES_DLY_128_V 0x1 +#define SPI_MEM_FLASH_PES_DLY_128_S 6 +/* SPI_MEM_FLASH_PER_DLY_128 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_ +RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM +_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent..*/ +#define SPI_MEM_FLASH_PER_DLY_128 (BIT(5)) +#define SPI_MEM_FLASH_PER_DLY_128_M (BIT(5)) +#define SPI_MEM_FLASH_PER_DLY_128_V 0x1 +#define SPI_MEM_FLASH_PER_DLY_128_S 5 +/* SPI_MEM_FLASH_DP_DLY_128 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP com +mand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles +after DP command is sent..*/ +#define SPI_MEM_FLASH_DP_DLY_128 (BIT(4)) +#define SPI_MEM_FLASH_DP_DLY_128_M (BIT(4)) +#define SPI_MEM_FLASH_DP_DLY_128_V 0x1 +#define SPI_MEM_FLASH_DP_DLY_128_S 4 +/* SPI_MEM_FLASH_RES_DLY_128 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES co +mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + after RES command is sent..*/ +#define SPI_MEM_FLASH_RES_DLY_128 (BIT(3)) +#define SPI_MEM_FLASH_RES_DLY_128_M (BIT(3)) +#define SPI_MEM_FLASH_RES_DLY_128_V 0x1 +#define SPI_MEM_FLASH_RES_DLY_128_S 3 +/* SPI_MEM_FLASH_HPM_DLY_128 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM co +mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + after HPM command is sent..*/ +#define SPI_MEM_FLASH_HPM_DLY_128 (BIT(2)) +#define SPI_MEM_FLASH_HPM_DLY_128_M (BIT(2)) +#define SPI_MEM_FLASH_HPM_DLY_128_V 0x1 +#define SPI_MEM_FLASH_HPM_DLY_128_S 2 +/* SPI_MEM_WAIT_PESR_CMD_2B : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: + SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit..*/ +#define SPI_MEM_WAIT_PESR_CMD_2B (BIT(1)) +#define SPI_MEM_WAIT_PESR_CMD_2B_M (BIT(1)) +#define SPI_MEM_WAIT_PESR_CMD_2B_V 0x1 +#define SPI_MEM_WAIT_PESR_CMD_2B_S 1 +/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The status of flash suspend, only used in SPI1..*/ +#define SPI_MEM_FLASH_SUS (BIT(0)) +#define SPI_MEM_FLASH_SUS_M (BIT(0)) +#define SPI_MEM_FLASH_SUS_V 0x1 +#define SPI_MEM_FLASH_SUS_S 0 + +#define SPI_MEM_INT_ENA_REG(i) (REG_SPI_MEM_BASE(i) + 0xC0) +/* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt..*/ +#define SPI_MEM_BROWN_OUT_INT_ENA (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_ENA_M (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_ENA_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_ENA_S 10 +/* SPI_MEM_AXI_WADDR_ERR_INT__ENA : HRO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_M (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_V 0x1 +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_S 9 +/* SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : HRO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V 0x1 +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S 8 +/* SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V 0x1 +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S 7 +/* SPI_MEM_PMS_REJECT_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_PMS_REJECT_INT interrupt..*/ +#define SPI_MEM_PMS_REJECT_INT_ENA (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ENA_M (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ENA_V 0x1 +#define SPI_MEM_PMS_REJECT_INT_ENA_S 6 +/* SPI_MEM_ECC_ERR_INT_ENA : HRO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt..*/ +#define SPI_MEM_ECC_ERR_INT_ENA (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ENA_M (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ENA_V 0x1 +#define SPI_MEM_ECC_ERR_INT_ENA_S 5 +/* SPI_MEM_MST_ST_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt..*/ +#define SPI_MEM_MST_ST_END_INT_ENA (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ENA_M (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ENA_V 0x1 +#define SPI_MEM_MST_ST_END_INT_ENA_S 4 +/* SPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt..*/ +#define SPI_MEM_SLV_ST_END_INT_ENA (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ENA_M (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ENA_V 0x1 +#define SPI_MEM_SLV_ST_END_INT_ENA_S 3 +/* SPI_MEM_WPE_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_WPE_END_INT interrupt..*/ +#define SPI_MEM_WPE_END_INT_ENA (BIT(2)) +#define SPI_MEM_WPE_END_INT_ENA_M (BIT(2)) +#define SPI_MEM_WPE_END_INT_ENA_V 0x1 +#define SPI_MEM_WPE_END_INT_ENA_S 2 +/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_PES_END_INT interrupt..*/ +#define SPI_MEM_PES_END_INT_ENA (BIT(1)) +#define SPI_MEM_PES_END_INT_ENA_M (BIT(1)) +#define SPI_MEM_PES_END_INT_ENA_V 0x1 +#define SPI_MEM_PES_END_INT_ENA_S 1 +/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_PER_END_INT interrupt..*/ +#define SPI_MEM_PER_END_INT_ENA (BIT(0)) +#define SPI_MEM_PER_END_INT_ENA_M (BIT(0)) +#define SPI_MEM_PER_END_INT_ENA_V 0x1 +#define SPI_MEM_PER_END_INT_ENA_S 0 + +#define SPI_MEM_INT_CLR_REG(i) (REG_SPI_MEM_BASE(i) + 0xC4) +/* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/ +#define SPI_MEM_BROWN_OUT_INT_CLR (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_CLR_M (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_CLR_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_CLR_S 10 +/* SPI_MEM_AXI_WADDR_ERR_INT_CLR : HRO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V 0x1 +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S 9 +/* SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : HRO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V 0x1 +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S 8 +/* SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V 0x1 +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S 7 +/* SPI_MEM_PMS_REJECT_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_PMS_REJECT_INT interrupt..*/ +#define SPI_MEM_PMS_REJECT_INT_CLR (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_CLR_M (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_CLR_V 0x1 +#define SPI_MEM_PMS_REJECT_INT_CLR_S 6 +/* SPI_MEM_ECC_ERR_INT_CLR : HRO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt..*/ +#define SPI_MEM_ECC_ERR_INT_CLR (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_CLR_M (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_CLR_V 0x1 +#define SPI_MEM_ECC_ERR_INT_CLR_S 5 +/* SPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt..*/ +#define SPI_MEM_MST_ST_END_INT_CLR (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_CLR_M (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_CLR_V 0x1 +#define SPI_MEM_MST_ST_END_INT_CLR_S 4 +/* SPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt..*/ +#define SPI_MEM_SLV_ST_END_INT_CLR (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_CLR_M (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_CLR_V 0x1 +#define SPI_MEM_SLV_ST_END_INT_CLR_S 3 +/* SPI_MEM_WPE_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_WPE_END_INT interrupt..*/ +#define SPI_MEM_WPE_END_INT_CLR (BIT(2)) +#define SPI_MEM_WPE_END_INT_CLR_M (BIT(2)) +#define SPI_MEM_WPE_END_INT_CLR_V 0x1 +#define SPI_MEM_WPE_END_INT_CLR_S 2 +/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_PES_END_INT interrupt..*/ +#define SPI_MEM_PES_END_INT_CLR (BIT(1)) +#define SPI_MEM_PES_END_INT_CLR_M (BIT(1)) +#define SPI_MEM_PES_END_INT_CLR_V 0x1 +#define SPI_MEM_PES_END_INT_CLR_S 1 +/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MEM_PER_END_INT interrupt..*/ +#define SPI_MEM_PER_END_INT_CLR (BIT(0)) +#define SPI_MEM_PER_END_INT_CLR_M (BIT(0)) +#define SPI_MEM_PER_END_INT_CLR_V 0x1 +#define SPI_MEM_PER_END_INT_CLR_S 0 + +#define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xC8) +/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that +chip is loosing power and RTC module sends out brown out close flash request to +SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered + and MSPI returns to idle state. 0: Others..*/ +#define SPI_MEM_BROWN_OUT_INT_RAW (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_RAW_M (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_RAW_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_RAW_S 10 +/* SPI_MEM_AXI_WADDR_ERR_INT_RAW : HRO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write + address is invalid by compared to MMU configuration. 0: Others..*/ +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V 0x1 +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S 9 +/* SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : HRO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI wr +ite flash request is received. 0: Others..*/ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V 0x1 +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S 8 +/* SPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read +address is invalid by compared to MMU configuration. 0: Others..*/ +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V 0x1 +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S 7 +/* SPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access +is rejected. 0: Others..*/ +#define SPI_MEM_PMS_REJECT_INT_RAW (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_RAW_M (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_RAW_V 0x1 +#define SPI_MEM_PMS_REJECT_INT_RAW_S 6 +/* SPI_MEM_ECC_ERR_INT_RAW : HRO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is s +et and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error + times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM +. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, t +his bit is triggered when the error times of SPI0/1 ECC read external RAM are eq +ual or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SP +I_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times +of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_E +RR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleare +d, this bit will not be triggered..*/ +#define SPI_MEM_ECC_ERR_INT_RAW (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_RAW_M (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_RAW_V 0x1 +#define SPI_MEM_ECC_ERR_INT_RAW_S 5 +/* SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st +is changed from non idle state to idle state. 0: Others..*/ +#define SPI_MEM_MST_ST_END_INT_RAW (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_RAW_M (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_RAW_V 0x1 +#define SPI_MEM_MST_ST_END_INT_RAW_S 4 +/* SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st +is changed from non idle state to idle state. It means that SPI_CS raises high. +0: Others.*/ +#define SPI_MEM_SLV_ST_END_INT_RAW (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_RAW_M (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_RAW_V 0x1 +#define SPI_MEM_SLV_ST_END_INT_RAW_S 3 +/* SPI_MEM_WPE_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/C +E is sent and flash is already idle. 0: Others..*/ +#define SPI_MEM_WPE_END_INT_RAW (BIT(2)) +#define SPI_MEM_WPE_END_INT_RAW_M (BIT(2)) +#define SPI_MEM_WPE_END_INT_RAW_V 0x1 +#define SPI_MEM_WPE_END_INT_RAW_S 2 +/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend com +mand (0x75) is sent and flash is suspended successfully. 0: Others..*/ +#define SPI_MEM_PES_END_INT_RAW (BIT(1)) +#define SPI_MEM_PES_END_INT_RAW_M (BIT(1)) +#define SPI_MEM_PES_END_INT_RAW_V 0x1 +#define SPI_MEM_PES_END_INT_RAW_S 1 +/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume com +mand (0x7A) is sent and flash is resumed successfully. 0: Others..*/ +#define SPI_MEM_PER_END_INT_RAW (BIT(0)) +#define SPI_MEM_PER_END_INT_RAW_M (BIT(0)) +#define SPI_MEM_PER_END_INT_RAW_V 0x1 +#define SPI_MEM_PER_END_INT_RAW_S 0 + +#define SPI_MEM_INT_ST_REG(i) (REG_SPI_MEM_BASE(i) + 0xCC) +/* SPI_MEM_BROWN_OUT_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/ +#define SPI_MEM_BROWN_OUT_INT_ST (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_ST_M (BIT(10)) +#define SPI_MEM_BROWN_OUT_INT_ST_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_ST_S 10 +/* SPI_MEM_AXI_WADDR_ERR_INT_ST : HRO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WADDR_ERR_INT_ST (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_M (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_V 0x1 +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_S 9 +/* SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : HRO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V 0x1 +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S 8 +/* SPI_MEM_AXI_RADDR_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/ +#define SPI_MEM_AXI_RADDR_ERR_INT_ST (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_M (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_V 0x1 +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_S 7 +/* SPI_MEM_PMS_REJECT_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_PMS_REJECT_INT interrupt..*/ +#define SPI_MEM_PMS_REJECT_INT_ST (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ST_M (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ST_V 0x1 +#define SPI_MEM_PMS_REJECT_INT_ST_S 6 +/* SPI_MEM_ECC_ERR_INT_ST : HRO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_ECC_ERR_INT interrupt..*/ +#define SPI_MEM_ECC_ERR_INT_ST (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ST_M (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ST_V 0x1 +#define SPI_MEM_ECC_ERR_INT_ST_S 5 +/* SPI_MEM_MST_ST_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_MST_ST_END_INT interrupt..*/ +#define SPI_MEM_MST_ST_END_INT_ST (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ST_M (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ST_V 0x1 +#define SPI_MEM_MST_ST_END_INT_ST_S 4 +/* SPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt..*/ +#define SPI_MEM_SLV_ST_END_INT_ST (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ST_M (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ST_V 0x1 +#define SPI_MEM_SLV_ST_END_INT_ST_S 3 +/* SPI_MEM_WPE_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_WPE_END_INT interrupt..*/ +#define SPI_MEM_WPE_END_INT_ST (BIT(2)) +#define SPI_MEM_WPE_END_INT_ST_M (BIT(2)) +#define SPI_MEM_WPE_END_INT_ST_V 0x1 +#define SPI_MEM_WPE_END_INT_ST_S 2 +/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_PES_END_INT interrupt..*/ +#define SPI_MEM_PES_END_INT_ST (BIT(1)) +#define SPI_MEM_PES_END_INT_ST_M (BIT(1)) +#define SPI_MEM_PES_END_INT_ST_V 0x1 +#define SPI_MEM_PES_END_INT_ST_S 1 +/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MEM_PER_END_INT interrupt..*/ +#define SPI_MEM_PER_END_INT_ST (BIT(0)) +#define SPI_MEM_PER_END_INT_ST_M (BIT(0)) +#define SPI_MEM_PER_END_INT_ST_V 0x1 +#define SPI_MEM_PER_END_INT_ST_S 0 + +#define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xD4) +/* SPI_MEM_FMEM_HYPERBUS_CA : HRO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to enable HyperRAM address out when accesses to flash, which means +ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}..*/ +#define SPI_MEM_FMEM_HYPERBUS_CA (BIT(30)) +#define SPI_MEM_FMEM_HYPERBUS_CA_M (BIT(30)) +#define SPI_MEM_FMEM_HYPERBUS_CA_V 0x1 +#define SPI_MEM_FMEM_HYPERBUS_CA_S 30 +/* SPI_MEM_FMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to enable octa_ram address out when accesses to flash, which means +ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0} +..*/ +#define SPI_MEM_FMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_MEM_FMEM_OCTA_RAM_ADDR_M (BIT(29)) +#define SPI_MEM_FMEM_OCTA_RAM_ADDR_V 0x1 +#define SPI_MEM_FMEM_OCTA_RAM_ADDR_S 29 +/* SPI_MEM_FMEM_CLK_DIFF_INV : HRO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to invert SPI_DIFF when accesses to flash. ..*/ +#define SPI_MEM_FMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_MEM_FMEM_CLK_DIFF_INV_M (BIT(28)) +#define SPI_MEM_FMEM_CLK_DIFF_INV_V 0x1 +#define SPI_MEM_FMEM_CLK_DIFF_INV_S 28 +/* SPI_MEM_FMEM_HYPERBUS_DUMMY_2X : HRO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a +ccesses flash or SPI1 accesses flash or sram..*/ +#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) +#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V 0x1 +#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S 27 +/* SPI_MEM_FMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR +..*/ +#define SPI_MEM_FMEM_DQS_CA_IN (BIT(26)) +#define SPI_MEM_FMEM_DQS_CA_IN_M (BIT(26)) +#define SPI_MEM_FMEM_DQS_CA_IN_V 0x1 +#define SPI_MEM_FMEM_DQS_CA_IN_S 26 +/* SPI_MEM_FMEM_CLK_DIFF_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Set this bit to enable the differential SPI_CLK#..*/ +#define SPI_MEM_FMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_MEM_FMEM_CLK_DIFF_EN_M (BIT(24)) +#define SPI_MEM_FMEM_CLK_DIFF_EN_V 0x1 +#define SPI_MEM_FMEM_CLK_DIFF_EN_S 24 +/* SPI_MEM_FMEM_DDR_DQS_LOOP : HRO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi +0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or +SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n +egative edge of SPI_DQS..*/ +#define SPI_MEM_FMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_FMEM_DDR_DQS_LOOP_M (BIT(21)) +#define SPI_MEM_FMEM_DDR_DQS_LOOP_V 0x1 +#define SPI_MEM_FMEM_DDR_DQS_LOOP_S 21 +/* SPI_MEM_FMEM_USR_DDR_DQS_THD : HRO ;bitpos:[20:14] ;default: 7'b0 ; */ +/*description: The delay number of data strobe which from memory based on SPI clock..*/ +#define SPI_MEM_FMEM_USR_DDR_DQS_THD 0x0000007F +#define SPI_MEM_FMEM_USR_DDR_DQS_THD_M ((SPI_MEM_FMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_FMEM_USR_DDR_DQS_THD_S)) +#define SPI_MEM_FMEM_USR_DDR_DQS_THD_V 0x7F +#define SPI_MEM_FMEM_USR_DDR_DQS_THD_S 14 +/* SPI_MEM_FMEM_RX_DDR_MSK_EN : HRO ;bitpos:[13] ;default: 1'h1 ; */ +/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when +accesses to flash..*/ +#define SPI_MEM_FMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_MEM_FMEM_RX_DDR_MSK_EN_M (BIT(13)) +#define SPI_MEM_FMEM_RX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_FMEM_RX_DDR_MSK_EN_S 13 +/* SPI_MEM_FMEM_TX_DDR_MSK_EN : HRO ;bitpos:[12] ;default: 1'h1 ; */ +/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + accesses to flash..*/ +#define SPI_MEM_FMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_MEM_FMEM_TX_DDR_MSK_EN_M (BIT(12)) +#define SPI_MEM_FMEM_TX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_FMEM_TX_DDR_MSK_EN_S 12 +/* SPI_MEM_FMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */ +/*description: It is the minimum output data length in the panda device..*/ +#define SPI_MEM_FMEM_OUTMINBYTELEN 0x0000007F +#define SPI_MEM_FMEM_OUTMINBYTELEN_M ((SPI_MEM_FMEM_OUTMINBYTELEN_V)<<(SPI_MEM_FMEM_OUTMINBYTELEN_S)) +#define SPI_MEM_FMEM_OUTMINBYTELEN_V 0x7F +#define SPI_MEM_FMEM_OUTMINBYTELEN_S 5 +/* SPI_MEM_FMEM_DDR_CMD_DIS : HRO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: the bit is used to disable dual edge in command phase when DDR mode..*/ +#define SPI_MEM_FMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_FMEM_DDR_CMD_DIS_M (BIT(4)) +#define SPI_MEM_FMEM_DDR_CMD_DIS_V 0x1 +#define SPI_MEM_FMEM_DDR_CMD_DIS_S 4 +/* SPI_MEM_FMEM_DDR_WDAT_SWP : HRO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/ +#define SPI_MEM_FMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_FMEM_DDR_WDAT_SWP_M (BIT(3)) +#define SPI_MEM_FMEM_DDR_WDAT_SWP_V 0x1 +#define SPI_MEM_FMEM_DDR_WDAT_SWP_S 3 +/* SPI_MEM_FMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/ +#define SPI_MEM_FMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_FMEM_DDR_RDAT_SWP_M (BIT(2)) +#define SPI_MEM_FMEM_DDR_RDAT_SWP_V 0x1 +#define SPI_MEM_FMEM_DDR_RDAT_SWP_S 2 +/* SPI_MEM_FMEM_VAR_DUMMY : HRO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/ +#define SPI_MEM_FMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_FMEM_VAR_DUMMY_M (BIT(1)) +#define SPI_MEM_FMEM_VAR_DUMMY_V 0x1 +#define SPI_MEM_FMEM_VAR_DUMMY_S 1 +/* SPI_MEM_FMEM_DDR_EN : HRO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: 1: in DDR mode, 0 in SDR mode.*/ +#define SPI_MEM_FMEM_DDR_EN (BIT(0)) +#define SPI_MEM_FMEM_DDR_EN_M (BIT(0)) +#define SPI_MEM_FMEM_DDR_EN_V 0x1 +#define SPI_MEM_FMEM_DDR_EN_S 0 + +#define SPI_MEM_SPI_SMEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xD8) +/* SPI_MEM_SMEM_HYPERBUS_CA : HRO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to enable HyperRAM address out when accesses to external RAM, which + means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1 +]}..*/ +#define SPI_MEM_SMEM_HYPERBUS_CA (BIT(30)) +#define SPI_MEM_SMEM_HYPERBUS_CA_M (BIT(30)) +#define SPI_MEM_SMEM_HYPERBUS_CA_V 0x1 +#define SPI_MEM_SMEM_HYPERBUS_CA_S 30 +/* SPI_MEM_SMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to enable octa_ram address out when accesses to external RAM, which + means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1] +, 1'b0}..*/ +#define SPI_MEM_SMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_MEM_SMEM_OCTA_RAM_ADDR_M (BIT(29)) +#define SPI_MEM_SMEM_OCTA_RAM_ADDR_V 0x1 +#define SPI_MEM_SMEM_OCTA_RAM_ADDR_S 29 +/* SPI_MEM_SMEM_CLK_DIFF_INV : HRO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to invert SPI_DIFF when accesses to external RAM. ..*/ +#define SPI_MEM_SMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_MEM_SMEM_CLK_DIFF_INV_M (BIT(28)) +#define SPI_MEM_SMEM_CLK_DIFF_INV_V 0x1 +#define SPI_MEM_SMEM_CLK_DIFF_INV_S 28 +/* SPI_MEM_SMEM_HYPERBUS_DUMMY_2X : HRO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a +ccesses flash or SPI1 accesses flash or sram..*/ +#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) +#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_V 0x1 +#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_S 27 +/* SPI_MEM_SMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR +..*/ +#define SPI_MEM_SMEM_DQS_CA_IN (BIT(26)) +#define SPI_MEM_SMEM_DQS_CA_IN_M (BIT(26)) +#define SPI_MEM_SMEM_DQS_CA_IN_V 0x1 +#define SPI_MEM_SMEM_DQS_CA_IN_S 26 +/* SPI_MEM_SMEM_CLK_DIFF_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Set this bit to enable the differential SPI_CLK#..*/ +#define SPI_MEM_SMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_MEM_SMEM_CLK_DIFF_EN_M (BIT(24)) +#define SPI_MEM_SMEM_CLK_DIFF_EN_V 0x1 +#define SPI_MEM_SMEM_CLK_DIFF_EN_S 24 +/* SPI_MEM_SMEM_DDR_DQS_LOOP : HRO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi +0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or +SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n +egative edge of SPI_DQS..*/ +#define SPI_MEM_SMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_SMEM_DDR_DQS_LOOP_M (BIT(21)) +#define SPI_MEM_SMEM_DDR_DQS_LOOP_V 0x1 +#define SPI_MEM_SMEM_DDR_DQS_LOOP_S 21 +/* SPI_MEM_SMEM_USR_DDR_DQS_THD : HRO ;bitpos:[20:14] ;default: 7'b0 ; */ +/*description: The delay number of data strobe which from memory based on SPI clock..*/ +#define SPI_MEM_SMEM_USR_DDR_DQS_THD 0x0000007F +#define SPI_MEM_SMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SMEM_USR_DDR_DQS_THD_S)) +#define SPI_MEM_SMEM_USR_DDR_DQS_THD_V 0x7F +#define SPI_MEM_SMEM_USR_DDR_DQS_THD_S 14 +/* SPI_MEM_SMEM_RX_DDR_MSK_EN : HRO ;bitpos:[13] ;default: 1'h1 ; */ +/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when +accesses to external RAM..*/ +#define SPI_MEM_SMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_MEM_SMEM_RX_DDR_MSK_EN_M (BIT(13)) +#define SPI_MEM_SMEM_RX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_SMEM_RX_DDR_MSK_EN_S 13 +/* SPI_MEM_SMEM_TX_DDR_MSK_EN : HRO ;bitpos:[12] ;default: 1'h1 ; */ +/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + accesses to external RAM..*/ +#define SPI_MEM_SMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_MEM_SMEM_TX_DDR_MSK_EN_M (BIT(12)) +#define SPI_MEM_SMEM_TX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_SMEM_TX_DDR_MSK_EN_S 12 +/* SPI_MEM_SMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */ +/*description: It is the minimum output data length in the DDR psram..*/ +#define SPI_MEM_SMEM_OUTMINBYTELEN 0x0000007F +#define SPI_MEM_SMEM_OUTMINBYTELEN_M ((SPI_MEM_SMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SMEM_OUTMINBYTELEN_S)) +#define SPI_MEM_SMEM_OUTMINBYTELEN_V 0x7F +#define SPI_MEM_SMEM_OUTMINBYTELEN_S 5 +/* SPI_MEM_SMEM_DDR_CMD_DIS : HRO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: the bit is used to disable dual edge in command phase when DDR mode..*/ +#define SPI_MEM_SMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_SMEM_DDR_CMD_DIS_M (BIT(4)) +#define SPI_MEM_SMEM_DDR_CMD_DIS_V 0x1 +#define SPI_MEM_SMEM_DDR_CMD_DIS_S 4 +/* SPI_MEM_SMEM_DDR_WDAT_SWP : HRO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/ +#define SPI_MEM_SMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_SMEM_DDR_WDAT_SWP_M (BIT(3)) +#define SPI_MEM_SMEM_DDR_WDAT_SWP_V 0x1 +#define SPI_MEM_SMEM_DDR_WDAT_SWP_S 3 +/* SPI_MEM_SMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/ +#define SPI_MEM_SMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_SMEM_DDR_RDAT_SWP_M (BIT(2)) +#define SPI_MEM_SMEM_DDR_RDAT_SWP_V 0x1 +#define SPI_MEM_SMEM_DDR_RDAT_SWP_S 2 +/* SPI_MEM_SMEM_VAR_DUMMY : HRO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/ +#define SPI_MEM_SMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_SMEM_VAR_DUMMY_M (BIT(1)) +#define SPI_MEM_SMEM_VAR_DUMMY_V 0x1 +#define SPI_MEM_SMEM_VAR_DUMMY_S 1 +/* SPI_MEM_SMEM_DDR_EN : HRO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: 1: in DDR mode, 0 in SDR mode.*/ +#define SPI_MEM_SMEM_DDR_EN (BIT(0)) +#define SPI_MEM_SMEM_DDR_EN_M (BIT(0)) +#define SPI_MEM_SMEM_DDR_EN_V 0x1 +#define SPI_MEM_SMEM_DDR_EN_S 0 + +#define SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x100) +/* SPI_MEM_FMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash + ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ +PMS$n_SIZE_REG..*/ +#define SPI_MEM_FMEM_PMS0_ECC (BIT(2)) +#define SPI_MEM_FMEM_PMS0_ECC_M (BIT(2)) +#define SPI_MEM_FMEM_PMS0_ECC_V 0x1 +#define SPI_MEM_FMEM_PMS0_ECC_S 2 +/* SPI_MEM_FMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS0_WR_ATTR (BIT(1)) +#define SPI_MEM_FMEM_PMS0_WR_ATTR_M (BIT(1)) +#define SPI_MEM_FMEM_PMS0_WR_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS0_WR_ATTR_S 1 +/* SPI_MEM_FMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS0_RD_ATTR (BIT(0)) +#define SPI_MEM_FMEM_PMS0_RD_ATTR_M (BIT(0)) +#define SPI_MEM_FMEM_PMS0_RD_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS0_RD_ATTR_S 0 + +#define SPI_MEM_SPI_FMEM_PMS1_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x104) +/* SPI_MEM_FMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash + ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ +PMS$n_SIZE_REG..*/ +#define SPI_MEM_FMEM_PMS1_ECC (BIT(2)) +#define SPI_MEM_FMEM_PMS1_ECC_M (BIT(2)) +#define SPI_MEM_FMEM_PMS1_ECC_V 0x1 +#define SPI_MEM_FMEM_PMS1_ECC_S 2 +/* SPI_MEM_FMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS1_WR_ATTR (BIT(1)) +#define SPI_MEM_FMEM_PMS1_WR_ATTR_M (BIT(1)) +#define SPI_MEM_FMEM_PMS1_WR_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS1_WR_ATTR_S 1 +/* SPI_MEM_FMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS1_RD_ATTR (BIT(0)) +#define SPI_MEM_FMEM_PMS1_RD_ATTR_M (BIT(0)) +#define SPI_MEM_FMEM_PMS1_RD_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS1_RD_ATTR_S 0 + +#define SPI_MEM_SPI_FMEM_PMS2_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x108) +/* SPI_MEM_FMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash + ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ +PMS$n_SIZE_REG..*/ +#define SPI_MEM_FMEM_PMS2_ECC (BIT(2)) +#define SPI_MEM_FMEM_PMS2_ECC_M (BIT(2)) +#define SPI_MEM_FMEM_PMS2_ECC_V 0x1 +#define SPI_MEM_FMEM_PMS2_ECC_S 2 +/* SPI_MEM_FMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS2_WR_ATTR (BIT(1)) +#define SPI_MEM_FMEM_PMS2_WR_ATTR_M (BIT(1)) +#define SPI_MEM_FMEM_PMS2_WR_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS2_WR_ATTR_S 1 +/* SPI_MEM_FMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS2_RD_ATTR (BIT(0)) +#define SPI_MEM_FMEM_PMS2_RD_ATTR_M (BIT(0)) +#define SPI_MEM_FMEM_PMS2_RD_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS2_RD_ATTR_S 0 + +#define SPI_MEM_SPI_FMEM_PMS3_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x10C) +/* SPI_MEM_FMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash + ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ +PMS$n_SIZE_REG..*/ +#define SPI_MEM_FMEM_PMS3_ECC (BIT(2)) +#define SPI_MEM_FMEM_PMS3_ECC_M (BIT(2)) +#define SPI_MEM_FMEM_PMS3_ECC_V 0x1 +#define SPI_MEM_FMEM_PMS3_ECC_S 2 +/* SPI_MEM_FMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS3_WR_ATTR (BIT(1)) +#define SPI_MEM_FMEM_PMS3_WR_ATTR_M (BIT(1)) +#define SPI_MEM_FMEM_PMS3_WR_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS3_WR_ATTR_S 1 +/* SPI_MEM_FMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_FMEM_PMS3_RD_ATTR (BIT(0)) +#define SPI_MEM_FMEM_PMS3_RD_ATTR_M (BIT(0)) +#define SPI_MEM_FMEM_PMS3_RD_ATTR_V 0x1 +#define SPI_MEM_FMEM_PMS3_RD_ATTR_S 0 + +#define SPI_MEM_SPI_FMEM_PMS0_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x110) +/* SPI_MEM_FMEM_PMS0_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: SPI1 flash ACE section $n start address value.*/ +#define SPI_MEM_FMEM_PMS0_ADDR_S 0x03FFFFFF +#define SPI_MEM_FMEM_PMS0_ADDR_S_M ((SPI_MEM_FMEM_PMS0_ADDR_S_V)<<(SPI_MEM_FMEM_PMS0_ADDR_S_S)) +#define SPI_MEM_FMEM_PMS0_ADDR_S_V 0x3FFFFFF +#define SPI_MEM_FMEM_PMS0_ADDR_S_S 0 + +#define SPI_MEM_SPI_FMEM_PMS1_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x114) +/* SPI_MEM_FMEM_PMS1_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'hffffff ; */ +/*description: SPI1 flash ACE section $n start address value.*/ +#define SPI_MEM_FMEM_PMS1_ADDR_S 0x03FFFFFF +#define SPI_MEM_FMEM_PMS1_ADDR_S_M ((SPI_MEM_FMEM_PMS1_ADDR_S_V)<<(SPI_MEM_FMEM_PMS1_ADDR_S_S)) +#define SPI_MEM_FMEM_PMS1_ADDR_S_V 0x3FFFFFF +#define SPI_MEM_FMEM_PMS1_ADDR_S_S 0 + +#define SPI_MEM_SPI_FMEM_PMS2_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x118) +/* SPI_MEM_FMEM_PMS2_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h1ffffff ; */ +/*description: SPI1 flash ACE section $n start address value.*/ +#define SPI_MEM_FMEM_PMS2_ADDR_S 0x03FFFFFF +#define SPI_MEM_FMEM_PMS2_ADDR_S_M ((SPI_MEM_FMEM_PMS2_ADDR_S_V)<<(SPI_MEM_FMEM_PMS2_ADDR_S_S)) +#define SPI_MEM_FMEM_PMS2_ADDR_S_V 0x3FFFFFF +#define SPI_MEM_FMEM_PMS2_ADDR_S_S 0 + +#define SPI_MEM_SPI_FMEM_PMS3_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x11C) +/* SPI_MEM_FMEM_PMS3_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h2ffffff ; */ +/*description: SPI1 flash ACE section $n start address value.*/ +#define SPI_MEM_FMEM_PMS3_ADDR_S 0x03FFFFFF +#define SPI_MEM_FMEM_PMS3_ADDR_S_M ((SPI_MEM_FMEM_PMS3_ADDR_S_V)<<(SPI_MEM_FMEM_PMS3_ADDR_S_S)) +#define SPI_MEM_FMEM_PMS3_ADDR_S_V 0x3FFFFFF +#define SPI_MEM_FMEM_PMS3_ADDR_S_S 0 + +#define SPI_MEM_SPI_FMEM_PMS0_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x120) +/* SPI_MEM_FMEM_PMS0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ +/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS +$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ +#define SPI_MEM_FMEM_PMS0_SIZE 0x00003FFF +#define SPI_MEM_FMEM_PMS0_SIZE_M ((SPI_MEM_FMEM_PMS0_SIZE_V)<<(SPI_MEM_FMEM_PMS0_SIZE_S)) +#define SPI_MEM_FMEM_PMS0_SIZE_V 0x3FFF +#define SPI_MEM_FMEM_PMS0_SIZE_S 0 + +#define SPI_MEM_SPI_FMEM_PMS1_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x124) +/* SPI_MEM_FMEM_PMS1_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ +/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS +$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ +#define SPI_MEM_FMEM_PMS1_SIZE 0x00003FFF +#define SPI_MEM_FMEM_PMS1_SIZE_M ((SPI_MEM_FMEM_PMS1_SIZE_V)<<(SPI_MEM_FMEM_PMS1_SIZE_S)) +#define SPI_MEM_FMEM_PMS1_SIZE_V 0x3FFF +#define SPI_MEM_FMEM_PMS1_SIZE_S 0 + +#define SPI_MEM_SPI_FMEM_PMS2_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x128) +/* SPI_MEM_FMEM_PMS2_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ +/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS +$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ +#define SPI_MEM_FMEM_PMS2_SIZE 0x00003FFF +#define SPI_MEM_FMEM_PMS2_SIZE_M ((SPI_MEM_FMEM_PMS2_SIZE_V)<<(SPI_MEM_FMEM_PMS2_SIZE_S)) +#define SPI_MEM_FMEM_PMS2_SIZE_V 0x3FFF +#define SPI_MEM_FMEM_PMS2_SIZE_S 0 + +#define SPI_MEM_SPI_FMEM_PMS3_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x12C) +/* SPI_MEM_FMEM_PMS3_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ +/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS +$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ +#define SPI_MEM_FMEM_PMS3_SIZE 0x00003FFF +#define SPI_MEM_FMEM_PMS3_SIZE_M ((SPI_MEM_FMEM_PMS3_SIZE_V)<<(SPI_MEM_FMEM_PMS3_SIZE_S)) +#define SPI_MEM_FMEM_PMS3_SIZE_V 0x3FFF +#define SPI_MEM_FMEM_PMS3_SIZE_S 0 + +#define SPI_MEM_SPI_SMEM_PMS0_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x130) +/* SPI_MEM_SMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th +e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG + and SPI_SMEM_PMS$n_SIZE_REG..*/ +#define SPI_MEM_SMEM_PMS0_ECC (BIT(2)) +#define SPI_MEM_SMEM_PMS0_ECC_M (BIT(2)) +#define SPI_MEM_SMEM_PMS0_ECC_V 0x1 +#define SPI_MEM_SMEM_PMS0_ECC_S 2 +/* SPI_MEM_SMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS0_WR_ATTR (BIT(1)) +#define SPI_MEM_SMEM_PMS0_WR_ATTR_M (BIT(1)) +#define SPI_MEM_SMEM_PMS0_WR_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS0_WR_ATTR_S 1 +/* SPI_MEM_SMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS0_RD_ATTR (BIT(0)) +#define SPI_MEM_SMEM_PMS0_RD_ATTR_M (BIT(0)) +#define SPI_MEM_SMEM_PMS0_RD_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS0_RD_ATTR_S 0 + +#define SPI_MEM_SPI_SMEM_PMS1_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x134) +/* SPI_MEM_SMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th +e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG + and SPI_SMEM_PMS$n_SIZE_REG..*/ +#define SPI_MEM_SMEM_PMS1_ECC (BIT(2)) +#define SPI_MEM_SMEM_PMS1_ECC_M (BIT(2)) +#define SPI_MEM_SMEM_PMS1_ECC_V 0x1 +#define SPI_MEM_SMEM_PMS1_ECC_S 2 +/* SPI_MEM_SMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS1_WR_ATTR (BIT(1)) +#define SPI_MEM_SMEM_PMS1_WR_ATTR_M (BIT(1)) +#define SPI_MEM_SMEM_PMS1_WR_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS1_WR_ATTR_S 1 +/* SPI_MEM_SMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS1_RD_ATTR (BIT(0)) +#define SPI_MEM_SMEM_PMS1_RD_ATTR_M (BIT(0)) +#define SPI_MEM_SMEM_PMS1_RD_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS1_RD_ATTR_S 0 + +#define SPI_MEM_SPI_SMEM_PMS2_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x138) +/* SPI_MEM_SMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th +e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG + and SPI_SMEM_PMS$n_SIZE_REG..*/ +#define SPI_MEM_SMEM_PMS2_ECC (BIT(2)) +#define SPI_MEM_SMEM_PMS2_ECC_M (BIT(2)) +#define SPI_MEM_SMEM_PMS2_ECC_V 0x1 +#define SPI_MEM_SMEM_PMS2_ECC_S 2 +/* SPI_MEM_SMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS2_WR_ATTR (BIT(1)) +#define SPI_MEM_SMEM_PMS2_WR_ATTR_M (BIT(1)) +#define SPI_MEM_SMEM_PMS2_WR_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS2_WR_ATTR_S 1 +/* SPI_MEM_SMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS2_RD_ATTR (BIT(0)) +#define SPI_MEM_SMEM_PMS2_RD_ATTR_M (BIT(0)) +#define SPI_MEM_SMEM_PMS2_RD_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS2_RD_ATTR_S 0 + +#define SPI_MEM_SPI_SMEM_PMS3_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x13C) +/* SPI_MEM_SMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th +e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG + and SPI_SMEM_PMS$n_SIZE_REG..*/ +#define SPI_MEM_SMEM_PMS3_ECC (BIT(2)) +#define SPI_MEM_SMEM_PMS3_ECC_M (BIT(2)) +#define SPI_MEM_SMEM_PMS3_ECC_V 0x1 +#define SPI_MEM_SMEM_PMS3_ECC_S 2 +/* SPI_MEM_SMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS3_WR_ATTR (BIT(1)) +#define SPI_MEM_SMEM_PMS3_WR_ATTR_M (BIT(1)) +#define SPI_MEM_SMEM_PMS3_WR_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS3_WR_ATTR_S 1 +/* SPI_MEM_SMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/ +#define SPI_MEM_SMEM_PMS3_RD_ATTR (BIT(0)) +#define SPI_MEM_SMEM_PMS3_RD_ATTR_M (BIT(0)) +#define SPI_MEM_SMEM_PMS3_RD_ATTR_V 0x1 +#define SPI_MEM_SMEM_PMS3_RD_ATTR_S 0 + +#define SPI_MEM_SPI_SMEM_PMS0_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x140) +/* SPI_MEM_SMEM_PMS0_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: SPI1 external RAM ACE section $n start address value.*/ +#define SPI_MEM_SMEM_PMS0_ADDR_S 0x03FFFFFF +#define SPI_MEM_SMEM_PMS0_ADDR_S_M ((SPI_MEM_SMEM_PMS0_ADDR_S_V)<<(SPI_MEM_SMEM_PMS0_ADDR_S_S)) +#define SPI_MEM_SMEM_PMS0_ADDR_S_V 0x3FFFFFF +#define SPI_MEM_SMEM_PMS0_ADDR_S_S 0 + +#define SPI_MEM_SPI_SMEM_PMS1_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x144) +/* SPI_MEM_SMEM_PMS1_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'hffffff ; */ +/*description: SPI1 external RAM ACE section $n start address value.*/ +#define SPI_MEM_SMEM_PMS1_ADDR_S 0x03FFFFFF +#define SPI_MEM_SMEM_PMS1_ADDR_S_M ((SPI_MEM_SMEM_PMS1_ADDR_S_V)<<(SPI_MEM_SMEM_PMS1_ADDR_S_S)) +#define SPI_MEM_SMEM_PMS1_ADDR_S_V 0x3FFFFFF +#define SPI_MEM_SMEM_PMS1_ADDR_S_S 0 + +#define SPI_MEM_SPI_SMEM_PMS2_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x148) +/* SPI_MEM_SMEM_PMS2_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h1ffffff ; */ +/*description: SPI1 external RAM ACE section $n start address value.*/ +#define SPI_MEM_SMEM_PMS2_ADDR_S 0x03FFFFFF +#define SPI_MEM_SMEM_PMS2_ADDR_S_M ((SPI_MEM_SMEM_PMS2_ADDR_S_V)<<(SPI_MEM_SMEM_PMS2_ADDR_S_S)) +#define SPI_MEM_SMEM_PMS2_ADDR_S_V 0x3FFFFFF +#define SPI_MEM_SMEM_PMS2_ADDR_S_S 0 + +#define SPI_MEM_SPI_SMEM_PMS3_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x14C) +/* SPI_MEM_SMEM_PMS3_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h2ffffff ; */ +/*description: SPI1 external RAM ACE section $n start address value.*/ +#define SPI_MEM_SMEM_PMS3_ADDR_S 0x03FFFFFF +#define SPI_MEM_SMEM_PMS3_ADDR_S_M ((SPI_MEM_SMEM_PMS3_ADDR_S_V)<<(SPI_MEM_SMEM_PMS3_ADDR_S_S)) +#define SPI_MEM_SMEM_PMS3_ADDR_S_V 0x3FFFFFF +#define SPI_MEM_SMEM_PMS3_ADDR_S_S 0 + +#define SPI_MEM_SPI_SMEM_PMS0_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x150) +/* SPI_MEM_SMEM_PMS0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ +/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S +MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ +#define SPI_MEM_SMEM_PMS0_SIZE 0x00003FFF +#define SPI_MEM_SMEM_PMS0_SIZE_M ((SPI_MEM_SMEM_PMS0_SIZE_V)<<(SPI_MEM_SMEM_PMS0_SIZE_S)) +#define SPI_MEM_SMEM_PMS0_SIZE_V 0x3FFF +#define SPI_MEM_SMEM_PMS0_SIZE_S 0 + +#define SPI_MEM_SPI_SMEM_PMS1_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x154) +/* SPI_MEM_SMEM_PMS1_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ +/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S +MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ +#define SPI_MEM_SMEM_PMS1_SIZE 0x00003FFF +#define SPI_MEM_SMEM_PMS1_SIZE_M ((SPI_MEM_SMEM_PMS1_SIZE_V)<<(SPI_MEM_SMEM_PMS1_SIZE_S)) +#define SPI_MEM_SMEM_PMS1_SIZE_V 0x3FFF +#define SPI_MEM_SMEM_PMS1_SIZE_S 0 + +#define SPI_MEM_SPI_SMEM_PMS2_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x158) +/* SPI_MEM_SMEM_PMS2_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ +/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S +MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ +#define SPI_MEM_SMEM_PMS2_SIZE 0x00003FFF +#define SPI_MEM_SMEM_PMS2_SIZE_M ((SPI_MEM_SMEM_PMS2_SIZE_V)<<(SPI_MEM_SMEM_PMS2_SIZE_S)) +#define SPI_MEM_SMEM_PMS2_SIZE_V 0x3FFF +#define SPI_MEM_SMEM_PMS2_SIZE_S 0 + +#define SPI_MEM_SPI_SMEM_PMS3_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x15C) +/* SPI_MEM_SMEM_PMS3_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */ +/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S +MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ +#define SPI_MEM_SMEM_PMS3_SIZE 0x00003FFF +#define SPI_MEM_SMEM_PMS3_SIZE_M ((SPI_MEM_SMEM_PMS3_SIZE_V)<<(SPI_MEM_SMEM_PMS3_SIZE_S)) +#define SPI_MEM_SMEM_PMS3_SIZE_V 0x3FFF +#define SPI_MEM_SMEM_PMS3_SIZE_S 0 + +#define SPI_MEM_PMS_REJECT_REG(i) (REG_SPI_MEM_BASE(i) + 0x164) +/* SPI_MEM_PMS_IVD : R/SS/WTC ;bitpos:[31] ;default: 1'h0 ; */ +/*description: 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit + error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/ +#define SPI_MEM_PMS_IVD (BIT(31)) +#define SPI_MEM_PMS_IVD_M (BIT(31)) +#define SPI_MEM_PMS_IVD_V 0x1 +#define SPI_MEM_PMS_IVD_S 31 +/* SPI_MEM_PMS_MULTI_HIT : R/SS/WTC ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 1: SPI1 access is rejected because of address miss. 0: No address miss error. It + is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/ +#define SPI_MEM_PMS_MULTI_HIT (BIT(30)) +#define SPI_MEM_PMS_MULTI_HIT_M (BIT(30)) +#define SPI_MEM_PMS_MULTI_HIT_V 0x1 +#define SPI_MEM_PMS_MULTI_HIT_S 30 +/* SPI_MEM_PMS_ST : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */ +/*description: 1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_M +EM_PMS_REJECT_INT_CLR bit is set..*/ +#define SPI_MEM_PMS_ST (BIT(29)) +#define SPI_MEM_PMS_ST_M (BIT(29)) +#define SPI_MEM_PMS_ST_V 0x1 +#define SPI_MEM_PMS_ST_S 29 +/* SPI_MEM_PMS_LD : R/SS/WTC ;bitpos:[28] ;default: 1'b0 ; */ +/*description: 1: SPI1 write access error. 0: No write access error. It is cleared by when SPI +_MEM_PMS_REJECT_INT_CLR bit is set..*/ +#define SPI_MEM_PMS_LD (BIT(28)) +#define SPI_MEM_PMS_LD_M (BIT(28)) +#define SPI_MEM_PMS_LD_V 0x1 +#define SPI_MEM_PMS_LD_S 28 +/* SPI_MEM_PM_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to enable SPI0/1 transfer permission control function..*/ +#define SPI_MEM_PM_EN (BIT(26)) +#define SPI_MEM_PM_EN_M (BIT(26)) +#define SPI_MEM_PM_EN_V 0x1 +#define SPI_MEM_PM_EN_S 26 +/* SPI_MEM_REJECT_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: This bits show the first SPI1 access error address. It is cleared by when SPI_M +EM_PMS_REJECT_INT_CLR bit is set..*/ +#define SPI_MEM_REJECT_ADDR 0x03FFFFFF +#define SPI_MEM_REJECT_ADDR_M ((SPI_MEM_REJECT_ADDR_V)<<(SPI_MEM_REJECT_ADDR_S)) +#define SPI_MEM_REJECT_ADDR_V 0x3FFFFFF +#define SPI_MEM_REJECT_ADDR_S 0 + +#define SPI_MEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x168) +/* SPI_MEM_ECC_ERR_BITS : HRO ;bitpos:[31:25] ;default: 7'd0 ; */ +/*description: Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding + to byte 0 bit 0 to byte 15 bit 7).*/ +#define SPI_MEM_ECC_ERR_BITS 0x0000007F +#define SPI_MEM_ECC_ERR_BITS_M ((SPI_MEM_ECC_ERR_BITS_V)<<(SPI_MEM_ECC_ERR_BITS_S)) +#define SPI_MEM_ECC_ERR_BITS_V 0x7F +#define SPI_MEM_ECC_ERR_BITS_S 25 +/* SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : HRO ;bitpos:[24] ;default: 1'b1 ; */ +/*description: 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is upd +ated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADD +R record the first ECC error information..*/ +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN (BIT(24)) +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M (BIT(24)) +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V 0x1 +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S 24 +/* SPI_MEM_USR_ECC_ADDR_EN : HRO ;bitpos:[21] ;default: 1'd0 ; */ +/*description: Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer..*/ +#define SPI_MEM_USR_ECC_ADDR_EN (BIT(21)) +#define SPI_MEM_USR_ECC_ADDR_EN_M (BIT(21)) +#define SPI_MEM_USR_ECC_ADDR_EN_V 0x1 +#define SPI_MEM_USR_ECC_ADDR_EN_S 21 +/* SPI_MEM_FMEM_ECC_ADDR_EN : HRO ;bitpos:[20] ;default: 1'd0 ; */ +/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t +he ECC region or non-ECC region of flash. If there is no ECC region in flash, th +is bit should be 0. Otherwise, this bit should be 1..*/ +#define SPI_MEM_FMEM_ECC_ADDR_EN (BIT(20)) +#define SPI_MEM_FMEM_ECC_ADDR_EN_M (BIT(20)) +#define SPI_MEM_FMEM_ECC_ADDR_EN_V 0x1 +#define SPI_MEM_FMEM_ECC_ADDR_EN_S 20 +/* SPI_MEM_FMEM_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: +1024 bytes. 3: 2048 bytes..*/ +#define SPI_MEM_FMEM_PAGE_SIZE 0x00000003 +#define SPI_MEM_FMEM_PAGE_SIZE_M ((SPI_MEM_FMEM_PAGE_SIZE_V)<<(SPI_MEM_FMEM_PAGE_SIZE_S)) +#define SPI_MEM_FMEM_PAGE_SIZE_V 0x3 +#define SPI_MEM_FMEM_PAGE_SIZE_S 18 +/* SPI_MEM_FMEM_ECC_ERR_INT_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to flas +h..*/ +#define SPI_MEM_FMEM_ECC_ERR_INT_EN (BIT(17)) +#define SPI_MEM_FMEM_ECC_ERR_INT_EN_M (BIT(17)) +#define SPI_MEM_FMEM_ECC_ERR_INT_EN_V 0x1 +#define SPI_MEM_FMEM_ECC_ERR_INT_EN_S 17 +/* SPI_MEM_FMEM_ECC_ERR_INT_NUM : HRO ;bitpos:[16:11] ;default: 6'd10 ; */ +/*description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interr +upt..*/ +#define SPI_MEM_FMEM_ECC_ERR_INT_NUM 0x0000003F +#define SPI_MEM_FMEM_ECC_ERR_INT_NUM_M ((SPI_MEM_FMEM_ECC_ERR_INT_NUM_V)<<(SPI_MEM_FMEM_ECC_ERR_INT_NUM_S)) +#define SPI_MEM_FMEM_ECC_ERR_INT_NUM_V 0x3F +#define SPI_MEM_FMEM_ECC_ERR_INT_NUM_S 11 + +#define SPI_MEM_ECC_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x16C) +/* SPI_MEM_ECC_ERR_CNT : HRO ;bitpos:[31:26] ;default: 6'd0 ; */ +/*description: This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ +ECC_ERR_INT_CLR bit is set..*/ +#define SPI_MEM_ECC_ERR_CNT 0x0000003F +#define SPI_MEM_ECC_ERR_CNT_M ((SPI_MEM_ECC_ERR_CNT_V)<<(SPI_MEM_ECC_ERR_CNT_S)) +#define SPI_MEM_ECC_ERR_CNT_V 0x3F +#define SPI_MEM_ECC_ERR_CNT_S 26 +/* SPI_MEM_ECC_ERR_ADDR : HRO ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ +ECC_ERR_INT_CLR bit is set..*/ +#define SPI_MEM_ECC_ERR_ADDR 0x03FFFFFF +#define SPI_MEM_ECC_ERR_ADDR_M ((SPI_MEM_ECC_ERR_ADDR_V)<<(SPI_MEM_ECC_ERR_ADDR_S)) +#define SPI_MEM_ECC_ERR_ADDR_V 0x3FFFFFF +#define SPI_MEM_ECC_ERR_ADDR_S 0 + +#define SPI_MEM_AXI_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x170) +/* SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */ +/*description: This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO +and RDATA_AFIFO are empty and spi0_mst_st is IDLE..*/ +#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY (BIT(31)) +#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_M (BIT(31)) +#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_V 0x1 +#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_S 31 +/* SPI_MEM_WBLEN_AFIFO_REMPTY : RO ;bitpos:[30] ;default: 1'b1 ; */ +/*description: 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending..*/ +#define SPI_MEM_WBLEN_AFIFO_REMPTY (BIT(30)) +#define SPI_MEM_WBLEN_AFIFO_REMPTY_M (BIT(30)) +#define SPI_MEM_WBLEN_AFIFO_REMPTY_V 0x1 +#define SPI_MEM_WBLEN_AFIFO_REMPTY_S 30 +/* SPI_MEM_WDATA_AFIFO_REMPTY : RO ;bitpos:[29] ;default: 1'b1 ; */ +/*description: 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending..*/ +#define SPI_MEM_WDATA_AFIFO_REMPTY (BIT(29)) +#define SPI_MEM_WDATA_AFIFO_REMPTY_M (BIT(29)) +#define SPI_MEM_WDATA_AFIFO_REMPTY_V 0x1 +#define SPI_MEM_WDATA_AFIFO_REMPTY_S 29 +/* SPI_MEM_RADDR_AFIFO_REMPTY : RO ;bitpos:[28] ;default: 1'b1 ; */ +/*description: 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending..*/ +#define SPI_MEM_RADDR_AFIFO_REMPTY (BIT(28)) +#define SPI_MEM_RADDR_AFIFO_REMPTY_M (BIT(28)) +#define SPI_MEM_RADDR_AFIFO_REMPTY_V 0x1 +#define SPI_MEM_RADDR_AFIFO_REMPTY_S 28 +/* SPI_MEM_RDATA_AFIFO_REMPTY : RO ;bitpos:[27] ;default: 1'b1 ; */ +/*description: 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending..*/ +#define SPI_MEM_RDATA_AFIFO_REMPTY (BIT(27)) +#define SPI_MEM_RDATA_AFIFO_REMPTY_M (BIT(27)) +#define SPI_MEM_RDATA_AFIFO_REMPTY_V 0x1 +#define SPI_MEM_RDATA_AFIFO_REMPTY_S 27 +/* SPI_MEM_ALL_FIFO_EMPTY : RO ;bitpos:[26] ;default: 1'b1 ; */ +/*description: The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers + and SPI0 transfers are done. 0: Others..*/ +#define SPI_MEM_ALL_FIFO_EMPTY (BIT(26)) +#define SPI_MEM_ALL_FIFO_EMPTY_M (BIT(26)) +#define SPI_MEM_ALL_FIFO_EMPTY_V 0x1 +#define SPI_MEM_ALL_FIFO_EMPTY_S 26 +/* SPI_MEM_AXI_ERR_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: This bits show the first AXI write/read invalid error or AXI write flash error a +ddress. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLAS +H_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set..*/ +#define SPI_MEM_AXI_ERR_ADDR 0x03FFFFFF +#define SPI_MEM_AXI_ERR_ADDR_M ((SPI_MEM_AXI_ERR_ADDR_V)<<(SPI_MEM_AXI_ERR_ADDR_S)) +#define SPI_MEM_AXI_ERR_ADDR_V 0x3FFFFFF +#define SPI_MEM_AXI_ERR_ADDR_S 0 + +#define SPI_MEM_SPI_SMEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x174) +/* SPI_MEM_SMEM_ECC_ADDR_EN : HRO ;bitpos:[20] ;default: 1'd0 ; */ +/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t +he ECC region or non-ECC region of external RAM. If there is no ECC region in ex +ternal RAM, this bit should be 0. Otherwise, this bit should be 1..*/ +#define SPI_MEM_SMEM_ECC_ADDR_EN (BIT(20)) +#define SPI_MEM_SMEM_ECC_ADDR_EN_M (BIT(20)) +#define SPI_MEM_SMEM_ECC_ADDR_EN_V 0x1 +#define SPI_MEM_SMEM_ECC_ADDR_EN_S 20 +/* SPI_MEM_SMEM_PAGE_SIZE : HRO ;bitpos:[19:18] ;default: 2'd2 ; */ +/*description: Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 byt +es. 2: 1024 bytes. 3: 2048 bytes..*/ +#define SPI_MEM_SMEM_PAGE_SIZE 0x00000003 +#define SPI_MEM_SMEM_PAGE_SIZE_M ((SPI_MEM_SMEM_PAGE_SIZE_V)<<(SPI_MEM_SMEM_PAGE_SIZE_S)) +#define SPI_MEM_SMEM_PAGE_SIZE_V 0x3 +#define SPI_MEM_SMEM_PAGE_SIZE_S 18 +/* SPI_MEM_SMEM_ECC_ERR_INT_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to exte +rnal RAM..*/ +#define SPI_MEM_SMEM_ECC_ERR_INT_EN (BIT(17)) +#define SPI_MEM_SMEM_ECC_ERR_INT_EN_M (BIT(17)) +#define SPI_MEM_SMEM_ECC_ERR_INT_EN_V 0x1 +#define SPI_MEM_SMEM_ECC_ERR_INT_EN_S 17 + +#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x180) +/* SPI_MEM_TIMING_CALI_UPDATE : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to update delay mode, delay num and extra dummy in MSPI..*/ +#define SPI_MEM_TIMING_CALI_UPDATE (BIT(6)) +#define SPI_MEM_TIMING_CALI_UPDATE_M (BIT(6)) +#define SPI_MEM_TIMING_CALI_UPDATE_V 0x1 +#define SPI_MEM_TIMING_CALI_UPDATE_S 6 +/* SPI_MEM_DLL_TIMING_CALI : HRO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to f +lash..*/ +#define SPI_MEM_DLL_TIMING_CALI (BIT(5)) +#define SPI_MEM_DLL_TIMING_CALI_M (BIT(5)) +#define SPI_MEM_DLL_TIMING_CALI_V 0x1 +#define SPI_MEM_DLL_TIMING_CALI_S 5 +/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ +/*description: add extra dummy spi clock cycle length for spi clock calibration..*/ +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007 +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S)) +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x7 +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 +/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to enable timing auto-calibration for all reading operations..*/ +#define SPI_MEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_TIMING_CALI_M (BIT(1)) +#define SPI_MEM_TIMING_CALI_V 0x1 +#define SPI_MEM_TIMING_CALI_S 1 +/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to enable timing adjust clock for all reading operations..*/ +#define SPI_MEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_TIMING_CLK_ENA_M (BIT(0)) +#define SPI_MEM_TIMING_CLK_ENA_V 0x1 +#define SPI_MEM_TIMING_CLK_ENA_S 0 + +#define SPI_MEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x184) +/* SPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp +ut with the spi_clk.*/ +#define SPI_MEM_DINS_MODE 0x00000007 +#define SPI_MEM_DINS_MODE_M ((SPI_MEM_DINS_MODE_V)<<(SPI_MEM_DINS_MODE_S)) +#define SPI_MEM_DINS_MODE_V 0x7 +#define SPI_MEM_DINS_MODE_S 24 +/* SPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp +ut with the spi_clk.*/ +#define SPI_MEM_DIN7_MODE 0x00000007 +#define SPI_MEM_DIN7_MODE_M ((SPI_MEM_DIN7_MODE_V)<<(SPI_MEM_DIN7_MODE_S)) +#define SPI_MEM_DIN7_MODE_V 0x7 +#define SPI_MEM_DIN7_MODE_S 21 +/* SPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp +ut with the spi_clk.*/ +#define SPI_MEM_DIN6_MODE 0x00000007 +#define SPI_MEM_DIN6_MODE_M ((SPI_MEM_DIN6_MODE_V)<<(SPI_MEM_DIN6_MODE_S)) +#define SPI_MEM_DIN6_MODE_V 0x7 +#define SPI_MEM_DIN6_MODE_S 18 +/* SPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp +ut with the spi_clk.*/ +#define SPI_MEM_DIN5_MODE 0x00000007 +#define SPI_MEM_DIN5_MODE_M ((SPI_MEM_DIN5_MODE_V)<<(SPI_MEM_DIN5_MODE_S)) +#define SPI_MEM_DIN5_MODE_V 0x7 +#define SPI_MEM_DIN5_MODE_S 15 +/* SPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp +ut with the spi_clk.*/ +#define SPI_MEM_DIN4_MODE 0x00000007 +#define SPI_MEM_DIN4_MODE_M ((SPI_MEM_DIN4_MODE_V)<<(SPI_MEM_DIN4_MODE_S)) +#define SPI_MEM_DIN4_MODE_V 0x7 +#define SPI_MEM_DIN4_MODE_S 12 +/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_DIN3_MODE 0x00000007 +#define SPI_MEM_DIN3_MODE_M ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S)) +#define SPI_MEM_DIN3_MODE_V 0x7 +#define SPI_MEM_DIN3_MODE_S 9 +/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_DIN2_MODE 0x00000007 +#define SPI_MEM_DIN2_MODE_M ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S)) +#define SPI_MEM_DIN2_MODE_V 0x7 +#define SPI_MEM_DIN2_MODE_S 6 +/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_DIN1_MODE 0x00000007 +#define SPI_MEM_DIN1_MODE_M ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S)) +#define SPI_MEM_DIN1_MODE_V 0x7 +#define SPI_MEM_DIN1_MODE_S 3 +/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_DIN0_MODE 0x00000007 +#define SPI_MEM_DIN0_MODE_M ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S)) +#define SPI_MEM_DIN0_MODE_V 0x7 +#define SPI_MEM_DIN0_MODE_S 0 + +#define SPI_MEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x188) +/* SPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DINS_NUM 0x00000003 +#define SPI_MEM_DINS_NUM_M ((SPI_MEM_DINS_NUM_V)<<(SPI_MEM_DINS_NUM_S)) +#define SPI_MEM_DINS_NUM_V 0x3 +#define SPI_MEM_DINS_NUM_S 16 +/* SPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN7_NUM 0x00000003 +#define SPI_MEM_DIN7_NUM_M ((SPI_MEM_DIN7_NUM_V)<<(SPI_MEM_DIN7_NUM_S)) +#define SPI_MEM_DIN7_NUM_V 0x3 +#define SPI_MEM_DIN7_NUM_S 14 +/* SPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN6_NUM 0x00000003 +#define SPI_MEM_DIN6_NUM_M ((SPI_MEM_DIN6_NUM_V)<<(SPI_MEM_DIN6_NUM_S)) +#define SPI_MEM_DIN6_NUM_V 0x3 +#define SPI_MEM_DIN6_NUM_S 12 +/* SPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN5_NUM 0x00000003 +#define SPI_MEM_DIN5_NUM_M ((SPI_MEM_DIN5_NUM_V)<<(SPI_MEM_DIN5_NUM_S)) +#define SPI_MEM_DIN5_NUM_V 0x3 +#define SPI_MEM_DIN5_NUM_S 10 +/* SPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN4_NUM 0x00000003 +#define SPI_MEM_DIN4_NUM_M ((SPI_MEM_DIN4_NUM_V)<<(SPI_MEM_DIN4_NUM_S)) +#define SPI_MEM_DIN4_NUM_V 0x3 +#define SPI_MEM_DIN4_NUM_S 8 +/* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN3_NUM 0x00000003 +#define SPI_MEM_DIN3_NUM_M ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S)) +#define SPI_MEM_DIN3_NUM_V 0x3 +#define SPI_MEM_DIN3_NUM_S 6 +/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN2_NUM 0x00000003 +#define SPI_MEM_DIN2_NUM_M ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S)) +#define SPI_MEM_DIN2_NUM_V 0x3 +#define SPI_MEM_DIN2_NUM_S 4 +/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN1_NUM 0x00000003 +#define SPI_MEM_DIN1_NUM_M ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S)) +#define SPI_MEM_DIN1_NUM_V 0x3 +#define SPI_MEM_DIN1_NUM_S 2 +/* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_DIN0_NUM 0x00000003 +#define SPI_MEM_DIN0_NUM_M ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S)) +#define SPI_MEM_DIN0_NUM_V 0x3 +#define SPI_MEM_DIN0_NUM_S 0 + +#define SPI_MEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x18C) +/* SPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the spi_clk.*/ +#define SPI_MEM_DOUTS_MODE (BIT(8)) +#define SPI_MEM_DOUTS_MODE_M (BIT(8)) +#define SPI_MEM_DOUTS_MODE_V 0x1 +#define SPI_MEM_DOUTS_MODE_S 8 +/* SPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the spi_clk.*/ +#define SPI_MEM_DOUT7_MODE (BIT(7)) +#define SPI_MEM_DOUT7_MODE_M (BIT(7)) +#define SPI_MEM_DOUT7_MODE_V 0x1 +#define SPI_MEM_DOUT7_MODE_S 7 +/* SPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the spi_clk.*/ +#define SPI_MEM_DOUT6_MODE (BIT(6)) +#define SPI_MEM_DOUT6_MODE_M (BIT(6)) +#define SPI_MEM_DOUT6_MODE_V 0x1 +#define SPI_MEM_DOUT6_MODE_S 6 +/* SPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the spi_clk.*/ +#define SPI_MEM_DOUT5_MODE (BIT(5)) +#define SPI_MEM_DOUT5_MODE_M (BIT(5)) +#define SPI_MEM_DOUT5_MODE_V 0x1 +#define SPI_MEM_DOUT5_MODE_S 5 +/* SPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the spi_clk.*/ +#define SPI_MEM_DOUT4_MODE (BIT(4)) +#define SPI_MEM_DOUT4_MODE_M (BIT(4)) +#define SPI_MEM_DOUT4_MODE_V 0x1 +#define SPI_MEM_DOUT4_MODE_S 4 +/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_DOUT3_MODE (BIT(3)) +#define SPI_MEM_DOUT3_MODE_M (BIT(3)) +#define SPI_MEM_DOUT3_MODE_V 0x1 +#define SPI_MEM_DOUT3_MODE_S 3 +/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_DOUT2_MODE (BIT(2)) +#define SPI_MEM_DOUT2_MODE_M (BIT(2)) +#define SPI_MEM_DOUT2_MODE_V 0x1 +#define SPI_MEM_DOUT2_MODE_S 2 +/* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_DOUT1_MODE (BIT(1)) +#define SPI_MEM_DOUT1_MODE_M (BIT(1)) +#define SPI_MEM_DOUT1_MODE_V 0x1 +#define SPI_MEM_DOUT1_MODE_S 1 +/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_DOUT0_MODE (BIT(0)) +#define SPI_MEM_DOUT0_MODE_M (BIT(0)) +#define SPI_MEM_DOUT0_MODE_V 0x1 +#define SPI_MEM_DOUT0_MODE_S 0 + +#define SPI_MEM_SPI_SMEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x190) +/* SPI_MEM_SMEM_DLL_TIMING_CALI : HRO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to E +XT_RAM..*/ +#define SPI_MEM_SMEM_DLL_TIMING_CALI (BIT(5)) +#define SPI_MEM_SMEM_DLL_TIMING_CALI_M (BIT(5)) +#define SPI_MEM_SMEM_DLL_TIMING_CALI_V 0x1 +#define SPI_MEM_SMEM_DLL_TIMING_CALI_S 5 +/* SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN : HRO ;bitpos:[4:2] ;default: 3'd0 ; */ +/*description: For sram, add extra dummy spi clock cycle length for spi clock calibration..*/ +#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007 +#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_S)) +#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x7 +#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 +/* SPI_MEM_SMEM_TIMING_CALI : HRO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For sram, the bit is used to enable timing auto-calibration for all reading oper +ations..*/ +#define SPI_MEM_SMEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_SMEM_TIMING_CALI_M (BIT(1)) +#define SPI_MEM_SMEM_TIMING_CALI_V 0x1 +#define SPI_MEM_SMEM_TIMING_CALI_S 1 +/* SPI_MEM_SMEM_TIMING_CLK_ENA : HRO ;bitpos:[0] ;default: 1'b1 ; */ +/*description: For sram, the bit is used to enable timing adjust clock for all reading operatio +ns..*/ +#define SPI_MEM_SMEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_SMEM_TIMING_CLK_ENA_M (BIT(0)) +#define SPI_MEM_SMEM_TIMING_CLK_ENA_V 0x1 +#define SPI_MEM_SMEM_TIMING_CLK_ENA_S 0 + +#define SPI_MEM_SPI_SMEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x194) +/* SPI_MEM_SMEM_DINS_MODE : HRO ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DINS_MODE 0x00000007 +#define SPI_MEM_SMEM_DINS_MODE_M ((SPI_MEM_SMEM_DINS_MODE_V)<<(SPI_MEM_SMEM_DINS_MODE_S)) +#define SPI_MEM_SMEM_DINS_MODE_V 0x7 +#define SPI_MEM_SMEM_DINS_MODE_S 24 +/* SPI_MEM_SMEM_DIN7_MODE : HRO ;bitpos:[23:21] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN7_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN7_MODE_M ((SPI_MEM_SMEM_DIN7_MODE_V)<<(SPI_MEM_SMEM_DIN7_MODE_S)) +#define SPI_MEM_SMEM_DIN7_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN7_MODE_S 21 +/* SPI_MEM_SMEM_DIN6_MODE : HRO ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN6_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN6_MODE_M ((SPI_MEM_SMEM_DIN6_MODE_V)<<(SPI_MEM_SMEM_DIN6_MODE_S)) +#define SPI_MEM_SMEM_DIN6_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN6_MODE_S 18 +/* SPI_MEM_SMEM_DIN5_MODE : HRO ;bitpos:[17:15] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN5_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN5_MODE_M ((SPI_MEM_SMEM_DIN5_MODE_V)<<(SPI_MEM_SMEM_DIN5_MODE_S)) +#define SPI_MEM_SMEM_DIN5_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN5_MODE_S 15 +/* SPI_MEM_SMEM_DIN4_MODE : HRO ;bitpos:[14:12] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN4_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN4_MODE_M ((SPI_MEM_SMEM_DIN4_MODE_V)<<(SPI_MEM_SMEM_DIN4_MODE_S)) +#define SPI_MEM_SMEM_DIN4_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN4_MODE_S 12 +/* SPI_MEM_SMEM_DIN3_MODE : HRO ;bitpos:[11:9] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN3_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN3_MODE_M ((SPI_MEM_SMEM_DIN3_MODE_V)<<(SPI_MEM_SMEM_DIN3_MODE_S)) +#define SPI_MEM_SMEM_DIN3_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN3_MODE_S 9 +/* SPI_MEM_SMEM_DIN2_MODE : HRO ;bitpos:[8:6] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN2_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN2_MODE_M ((SPI_MEM_SMEM_DIN2_MODE_V)<<(SPI_MEM_SMEM_DIN2_MODE_S)) +#define SPI_MEM_SMEM_DIN2_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN2_MODE_S 6 +/* SPI_MEM_SMEM_DIN1_MODE : HRO ;bitpos:[5:3] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN1_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN1_MODE_M ((SPI_MEM_SMEM_DIN1_MODE_V)<<(SPI_MEM_SMEM_DIN1_MODE_S)) +#define SPI_MEM_SMEM_DIN1_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN1_MODE_S 3 +/* SPI_MEM_SMEM_DIN0_MODE : HRO ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DIN0_MODE 0x00000007 +#define SPI_MEM_SMEM_DIN0_MODE_M ((SPI_MEM_SMEM_DIN0_MODE_V)<<(SPI_MEM_SMEM_DIN0_MODE_S)) +#define SPI_MEM_SMEM_DIN0_MODE_V 0x7 +#define SPI_MEM_SMEM_DIN0_MODE_S 0 + +#define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x198) +/* SPI_MEM_SMEM_DINS_NUM : HRO ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: input without delayed, +1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in +put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w +ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DINS_NUM 0x00000003 +#define SPI_MEM_SMEM_DINS_NUM_M ((SPI_MEM_SMEM_DINS_NUM_V)<<(SPI_MEM_SMEM_DINS_NUM_S)) +#define SPI_MEM_SMEM_DINS_NUM_V 0x3 +#define SPI_MEM_SMEM_DINS_NUM_S 16 +/* SPI_MEM_SMEM_DIN7_NUM : HRO ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN7_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN7_NUM_M ((SPI_MEM_SMEM_DIN7_NUM_V)<<(SPI_MEM_SMEM_DIN7_NUM_S)) +#define SPI_MEM_SMEM_DIN7_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN7_NUM_S 14 +/* SPI_MEM_SMEM_DIN6_NUM : HRO ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN6_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN6_NUM_M ((SPI_MEM_SMEM_DIN6_NUM_V)<<(SPI_MEM_SMEM_DIN6_NUM_S)) +#define SPI_MEM_SMEM_DIN6_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN6_NUM_S 12 +/* SPI_MEM_SMEM_DIN5_NUM : HRO ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN5_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN5_NUM_M ((SPI_MEM_SMEM_DIN5_NUM_V)<<(SPI_MEM_SMEM_DIN5_NUM_S)) +#define SPI_MEM_SMEM_DIN5_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN5_NUM_S 10 +/* SPI_MEM_SMEM_DIN4_NUM : HRO ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN4_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN4_NUM_M ((SPI_MEM_SMEM_DIN4_NUM_V)<<(SPI_MEM_SMEM_DIN4_NUM_S)) +#define SPI_MEM_SMEM_DIN4_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN4_NUM_S 8 +/* SPI_MEM_SMEM_DIN3_NUM : HRO ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN3_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN3_NUM_M ((SPI_MEM_SMEM_DIN3_NUM_V)<<(SPI_MEM_SMEM_DIN3_NUM_S)) +#define SPI_MEM_SMEM_DIN3_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN3_NUM_S 6 +/* SPI_MEM_SMEM_DIN2_NUM : HRO ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN2_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN2_NUM_M ((SPI_MEM_SMEM_DIN2_NUM_V)<<(SPI_MEM_SMEM_DIN2_NUM_S)) +#define SPI_MEM_SMEM_DIN2_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN2_NUM_S 4 +/* SPI_MEM_SMEM_DIN1_NUM : HRO ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN1_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN1_NUM_M ((SPI_MEM_SMEM_DIN1_NUM_V)<<(SPI_MEM_SMEM_DIN1_NUM_S)) +#define SPI_MEM_SMEM_DIN1_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN1_NUM_S 2 +/* SPI_MEM_SMEM_DIN0_NUM : HRO ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: +delayed by 2 cycles,....*/ +#define SPI_MEM_SMEM_DIN0_NUM 0x00000003 +#define SPI_MEM_SMEM_DIN0_NUM_M ((SPI_MEM_SMEM_DIN0_NUM_V)<<(SPI_MEM_SMEM_DIN0_NUM_S)) +#define SPI_MEM_SMEM_DIN0_NUM_V 0x3 +#define SPI_MEM_SMEM_DIN0_NUM_S 0 + +#define SPI_MEM_SPI_SMEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x19C) +/* SPI_MEM_SMEM_DOUTS_MODE : HRO ;bitpos:[8] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUTS_MODE (BIT(8)) +#define SPI_MEM_SMEM_DOUTS_MODE_M (BIT(8)) +#define SPI_MEM_SMEM_DOUTS_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUTS_MODE_S 8 +/* SPI_MEM_SMEM_DOUT7_MODE : HRO ;bitpos:[7] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT7_MODE (BIT(7)) +#define SPI_MEM_SMEM_DOUT7_MODE_M (BIT(7)) +#define SPI_MEM_SMEM_DOUT7_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT7_MODE_S 7 +/* SPI_MEM_SMEM_DOUT6_MODE : HRO ;bitpos:[6] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT6_MODE (BIT(6)) +#define SPI_MEM_SMEM_DOUT6_MODE_M (BIT(6)) +#define SPI_MEM_SMEM_DOUT6_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT6_MODE_S 6 +/* SPI_MEM_SMEM_DOUT5_MODE : HRO ;bitpos:[5] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT5_MODE (BIT(5)) +#define SPI_MEM_SMEM_DOUT5_MODE_M (BIT(5)) +#define SPI_MEM_SMEM_DOUT5_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT5_MODE_S 5 +/* SPI_MEM_SMEM_DOUT4_MODE : HRO ;bitpos:[4] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT4_MODE (BIT(4)) +#define SPI_MEM_SMEM_DOUT4_MODE_M (BIT(4)) +#define SPI_MEM_SMEM_DOUT4_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT4_MODE_S 4 +/* SPI_MEM_SMEM_DOUT3_MODE : HRO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT3_MODE (BIT(3)) +#define SPI_MEM_SMEM_DOUT3_MODE_M (BIT(3)) +#define SPI_MEM_SMEM_DOUT3_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT3_MODE_S 3 +/* SPI_MEM_SMEM_DOUT2_MODE : HRO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT2_MODE (BIT(2)) +#define SPI_MEM_SMEM_DOUT2_MODE_M (BIT(2)) +#define SPI_MEM_SMEM_DOUT2_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT2_MODE_S 2 +/* SPI_MEM_SMEM_DOUT1_MODE : HRO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT1_MODE (BIT(1)) +#define SPI_MEM_SMEM_DOUT1_MODE_M (BIT(1)) +#define SPI_MEM_SMEM_DOUT1_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT1_MODE_S 1 +/* SPI_MEM_SMEM_DOUT0_MODE : HRO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles, 0: output without delayed +, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp +ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ +#define SPI_MEM_SMEM_DOUT0_MODE (BIT(0)) +#define SPI_MEM_SMEM_DOUT0_MODE_M (BIT(0)) +#define SPI_MEM_SMEM_DOUT0_MODE_V 0x1 +#define SPI_MEM_SMEM_DOUT0_MODE_S 0 + +#define SPI_MEM_SPI_SMEM_AC_REG(i) (REG_SPI_MEM_BASE(i) + 0x1A0) +/* SPI_MEM_SMEM_SPLIT_TRANS_EN : HRO ;bitpos:[31] ;default: 1'b1 ; */ +/*description: Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI + transfers when one transfer will cross flash/EXT_RAM page corner, valid no matt +er whether there is an ECC region or not..*/ +#define SPI_MEM_SMEM_SPLIT_TRANS_EN (BIT(31)) +#define SPI_MEM_SMEM_SPLIT_TRANS_EN_M (BIT(31)) +#define SPI_MEM_SMEM_SPLIT_TRANS_EN_V 0x1 +#define SPI_MEM_SMEM_SPLIT_TRANS_EN_S 31 +/* SPI_MEM_SMEM_CS_HOLD_DELAY : HRO ;bitpos:[30:25] ;default: 6'd0 ; */ +/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran +sfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) M +SPI core clock cycles..*/ +#define SPI_MEM_SMEM_CS_HOLD_DELAY 0x0000003F +#define SPI_MEM_SMEM_CS_HOLD_DELAY_M ((SPI_MEM_SMEM_CS_HOLD_DELAY_V)<<(SPI_MEM_SMEM_CS_HOLD_DELAY_S)) +#define SPI_MEM_SMEM_CS_HOLD_DELAY_V 0x3F +#define SPI_MEM_SMEM_CS_HOLD_DELAY_S 25 +/* SPI_MEM_SMEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe +n accesses external RAM..*/ +#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) +#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_M (BIT(16)) +#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_V 0x1 +#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_S 16 +/* SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[15] ;default: 1'b1 ; */ +/*description: 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner wh +en accesses external RAM..*/ +#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15)) +#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_M (BIT(15)) +#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_V 0x1 +#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_S 15 +/* SPI_MEM_SMEM_ECC_CS_HOLD_TIME : HRO ;bitpos:[14:12] ;default: 3'd3 ; */ +/*description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold c +ycles in ECC mode when accessed external RAM..*/ +#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME 0x00000007 +#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_SMEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_SMEM_ECC_CS_HOLD_TIME_S)) +#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_V 0x7 +#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_S 12 +/* SPI_MEM_SMEM_CS_HOLD_TIME : HRO ;bitpos:[11:7] ;default: 5'h1 ; */ +/*description: For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits a +re combined with spi_mem_cs_hold bit..*/ +#define SPI_MEM_SMEM_CS_HOLD_TIME 0x0000001F +#define SPI_MEM_SMEM_CS_HOLD_TIME_M ((SPI_MEM_SMEM_CS_HOLD_TIME_V)<<(SPI_MEM_SMEM_CS_HOLD_TIME_S)) +#define SPI_MEM_SMEM_CS_HOLD_TIME_V 0x1F +#define SPI_MEM_SMEM_CS_HOLD_TIME_S 7 +/* SPI_MEM_SMEM_CS_SETUP_TIME : HRO ;bitpos:[6:2] ;default: 5'h1 ; */ +/*description: For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with s +pi_mem_cs_setup bit..*/ +#define SPI_MEM_SMEM_CS_SETUP_TIME 0x0000001F +#define SPI_MEM_SMEM_CS_SETUP_TIME_M ((SPI_MEM_SMEM_CS_SETUP_TIME_V)<<(SPI_MEM_SMEM_CS_SETUP_TIME_S)) +#define SPI_MEM_SMEM_CS_SETUP_TIME_V 0x1F +#define SPI_MEM_SMEM_CS_SETUP_TIME_S 2 +/* SPI_MEM_SMEM_CS_HOLD : HRO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disab +le..*/ +#define SPI_MEM_SMEM_CS_HOLD (BIT(1)) +#define SPI_MEM_SMEM_CS_HOLD_M (BIT(1)) +#define SPI_MEM_SMEM_CS_HOLD_V 0x1 +#define SPI_MEM_SMEM_CS_HOLD_S 1 +/* SPI_MEM_SMEM_CS_SETUP : HRO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: d +isable..*/ +#define SPI_MEM_SMEM_CS_SETUP (BIT(0)) +#define SPI_MEM_SMEM_CS_SETUP_M (BIT(0)) +#define SPI_MEM_SMEM_CS_SETUP_V 0x1 +#define SPI_MEM_SMEM_CS_SETUP_S 0 + +#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x200) +/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Register clock gate enable signal. 1: Enable. 0: Disable..*/ +#define SPI_MEM_CLK_EN (BIT(0)) +#define SPI_MEM_CLK_EN_M (BIT(0)) +#define SPI_MEM_CLK_EN_V 0x1 +#define SPI_MEM_CLK_EN_S 0 + +#define SPI_MEM_XTS_PLAIN_BASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x300) +/* SPI_MEM_XTS_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This field is only used to generate include file in c case. This field is useles +s. Please do not use this field..*/ +#define SPI_MEM_XTS_PLAIN 0xFFFFFFFF +#define SPI_MEM_XTS_PLAIN_M ((SPI_MEM_XTS_PLAIN_V)<<(SPI_MEM_XTS_PLAIN_S)) +#define SPI_MEM_XTS_PLAIN_V 0xFFFFFFFF +#define SPI_MEM_XTS_PLAIN_S 0 + +#define SPI_MEM_XTS_LINESIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x340) +/* SPI_MEM_XTS_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This bits stores the line-size parameter which will be used in manual encryption + calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, + 1: 32-bytes, 2: 64-bytes, 3:reserved..*/ +#define SPI_MEM_XTS_LINESIZE 0x00000003 +#define SPI_MEM_XTS_LINESIZE_M ((SPI_MEM_XTS_LINESIZE_V)<<(SPI_MEM_XTS_LINESIZE_S)) +#define SPI_MEM_XTS_LINESIZE_V 0x3 +#define SPI_MEM_XTS_LINESIZE_S 0 + +#define SPI_MEM_XTS_DESTINATION_REG(i) (REG_SPI_MEM_BASE(i) + 0x344) +/* SPI_MEM_XTS_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit stores the destination parameter which will be used in manual encryptio +n calculation. 0: flash(default), 1: psram(reserved). Only default value can be +used..*/ +#define SPI_MEM_XTS_DESTINATION (BIT(0)) +#define SPI_MEM_XTS_DESTINATION_M (BIT(0)) +#define SPI_MEM_XTS_DESTINATION_V 0x1 +#define SPI_MEM_XTS_DESTINATION_S 0 + +#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(i) (REG_SPI_MEM_BASE(i) + 0x348) +/* SPI_MEM_XTS_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: This bits stores the physical-address parameter which will be used in manual enc +ryption calculation. This value should aligned with byte number decided by line- +size parameter..*/ +#define SPI_MEM_XTS_PHYSICAL_ADDRESS 0x03FFFFFF +#define SPI_MEM_XTS_PHYSICAL_ADDRESS_M ((SPI_MEM_XTS_PHYSICAL_ADDRESS_V)<<(SPI_MEM_XTS_PHYSICAL_ADDRESS_S)) +#define SPI_MEM_XTS_PHYSICAL_ADDRESS_V 0x3FFFFFF +#define SPI_MEM_XTS_PHYSICAL_ADDRESS_S 0 + +#define SPI_MEM_XTS_TRIGGER_REG(i) (REG_SPI_MEM_BASE(i) + 0x34C) +/* SPI_MEM_XTS_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to trigger the process of manual encryption calculation. This actio +n should only be asserted when manual encryption status is 0. After this action, + manual encryption status becomes 1. After calculation is done, manual encryptio +n status becomes 2..*/ +#define SPI_MEM_XTS_TRIGGER (BIT(0)) +#define SPI_MEM_XTS_TRIGGER_M (BIT(0)) +#define SPI_MEM_XTS_TRIGGER_V 0x1 +#define SPI_MEM_XTS_TRIGGER_S 0 + +#define SPI_MEM_XTS_RELEASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x350) +/* SPI_MEM_XTS_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to release encrypted result to mspi. This action should only be ass +erted when manual encryption status is 2. After this action, manual encryption s +tatus will become 3..*/ +#define SPI_MEM_XTS_RELEASE (BIT(0)) +#define SPI_MEM_XTS_RELEASE_M (BIT(0)) +#define SPI_MEM_XTS_RELEASE_V 0x1 +#define SPI_MEM_XTS_RELEASE_S 0 + +#define SPI_MEM_XTS_DESTROY_REG(i) (REG_SPI_MEM_BASE(i) + 0x354) +/* SPI_MEM_XTS_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to destroy encrypted result. This action should be asserted only wh +en manual encryption status is 3. After this action, manual encryption status wi +ll become 0..*/ +#define SPI_MEM_XTS_DESTROY (BIT(0)) +#define SPI_MEM_XTS_DESTROY_M (BIT(0)) +#define SPI_MEM_XTS_DESTROY_V 0x1 +#define SPI_MEM_XTS_DESTROY_S 0 + +#define SPI_MEM_XTS_STATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x358) +/* SPI_MEM_XTS_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption + calculation, 2: encryption calculation is done but the encrypted result is invi +sible to mspi, 3: the encrypted result is visible to mspi..*/ +#define SPI_MEM_XTS_STATE 0x00000003 +#define SPI_MEM_XTS_STATE_M ((SPI_MEM_XTS_STATE_V)<<(SPI_MEM_XTS_STATE_S)) +#define SPI_MEM_XTS_STATE_V 0x3 +#define SPI_MEM_XTS_STATE_S 0 + +#define SPI_MEM_XTS_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x35C) +/* SPI_MEM_XTS_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */ +/*description: This bits stores the last modified-time of manual encryption feature..*/ +#define SPI_MEM_XTS_DATE 0x3FFFFFFF +#define SPI_MEM_XTS_DATE_M ((SPI_MEM_XTS_DATE_V)<<(SPI_MEM_XTS_DATE_S)) +#define SPI_MEM_XTS_DATE_V 0x3FFFFFFF +#define SPI_MEM_XTS_DATE_S 0 + +#define SPI_MEM_MMU_ITEM_CONTENT_REG(i) (REG_SPI_MEM_BASE(i) + 0x37C) +/* SPI_MEM_MMU_ITEM_CONTENT : R/W ;bitpos:[31:0] ;default: 32'h037c ; */ +/*description: MSPI-MMU item content.*/ +#define SPI_MEM_MMU_ITEM_CONTENT 0xFFFFFFFF +#define SPI_MEM_MMU_ITEM_CONTENT_M ((SPI_MEM_MMU_ITEM_CONTENT_V)<<(SPI_MEM_MMU_ITEM_CONTENT_S)) +#define SPI_MEM_MMU_ITEM_CONTENT_V 0xFFFFFFFF +#define SPI_MEM_MMU_ITEM_CONTENT_S 0 + +#define SPI_MEM_MMU_ITEM_INDEX_REG(i) (REG_SPI_MEM_BASE(i) + 0x380) +/* SPI_MEM_MMU_ITEM_INDEX : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: MSPI-MMU item index.*/ +#define SPI_MEM_MMU_ITEM_INDEX 0xFFFFFFFF +#define SPI_MEM_MMU_ITEM_INDEX_M ((SPI_MEM_MMU_ITEM_INDEX_V)<<(SPI_MEM_MMU_ITEM_INDEX_S)) +#define SPI_MEM_MMU_ITEM_INDEX_V 0xFFFFFFFF +#define SPI_MEM_MMU_ITEM_INDEX_S 0 + +#define SPI_MEM_MMU_POWER_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x384) +/* SPI_MEM_RDN_RESULT : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: MSPI module clock domain and AXI clock domain ECO register result register.*/ +#define SPI_MEM_RDN_RESULT (BIT(31)) +#define SPI_MEM_RDN_RESULT_M (BIT(31)) +#define SPI_MEM_RDN_RESULT_V 0x1 +#define SPI_MEM_RDN_RESULT_S 31 +/* SPI_MEM_RDN_ENA : HRO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: ECO register enable bit.*/ +#define SPI_MEM_RDN_ENA (BIT(30)) +#define SPI_MEM_RDN_ENA_M (BIT(30)) +#define SPI_MEM_RDN_ENA_V 0x1 +#define SPI_MEM_RDN_ENA_S 30 +/* SPI_MEM_AUX_CTRL : HRO ;bitpos:[29:16] ;default: 14'h1320 ; */ +/*description: MMU PSRAM aux control register.*/ +#define SPI_MEM_AUX_CTRL 0x00003FFF +#define SPI_MEM_AUX_CTRL_M ((SPI_MEM_AUX_CTRL_V)<<(SPI_MEM_AUX_CTRL_S)) +#define SPI_MEM_AUX_CTRL_V 0x3FFF +#define SPI_MEM_AUX_CTRL_S 16 +/* SPI_MEM_MMU_PAGE_SIZE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */ +/*description: 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8.*/ +#define SPI_MEM_MMU_PAGE_SIZE 0x00000003 +#define SPI_MEM_MMU_PAGE_SIZE_M ((SPI_MEM_MMU_PAGE_SIZE_V)<<(SPI_MEM_MMU_PAGE_SIZE_S)) +#define SPI_MEM_MMU_PAGE_SIZE_V 0x3 +#define SPI_MEM_MMU_PAGE_SIZE_S 3 +/* SPI_MEM_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: Set this bit to force mmu-memory powerup, in this case, the power should also be + controlled by rtc..*/ +#define SPI_MEM_MMU_MEM_FORCE_PU (BIT(2)) +#define SPI_MEM_MMU_MEM_FORCE_PU_M (BIT(2)) +#define SPI_MEM_MMU_MEM_FORCE_PU_V 0x1 +#define SPI_MEM_MMU_MEM_FORCE_PU_S 2 +/* SPI_MEM_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to force mmu-memory powerdown.*/ +#define SPI_MEM_MMU_MEM_FORCE_PD (BIT(1)) +#define SPI_MEM_MMU_MEM_FORCE_PD_M (BIT(1)) +#define SPI_MEM_MMU_MEM_FORCE_PD_V 0x1 +#define SPI_MEM_MMU_MEM_FORCE_PD_S 1 +/* SPI_MEM_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to enable mmu-memory clock force on.*/ +#define SPI_MEM_MMU_MEM_FORCE_ON (BIT(0)) +#define SPI_MEM_MMU_MEM_FORCE_ON_M (BIT(0)) +#define SPI_MEM_MMU_MEM_FORCE_ON_V 0x1 +#define SPI_MEM_MMU_MEM_FORCE_ON_S 0 + +#define SPI_MEM_DPA_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x388) +/* SPI_MEM_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP +T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/ +#define SPI_MEM_CRYPT_DPA_SELECT_REGISTER (BIT(4)) +#define SPI_MEM_CRYPT_DPA_SELECT_REGISTER_M (BIT(4)) +#define SPI_MEM_CRYPT_DPA_SELECT_REGISTER_V 0x1 +#define SPI_MEM_CRYPT_DPA_SELECT_REGISTER_S 4 +/* SPI_MEM_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc +ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us +ing key 1..*/ +#define SPI_MEM_CRYPT_CALC_D_DPA_EN (BIT(3)) +#define SPI_MEM_CRYPT_CALC_D_DPA_EN_M (BIT(3)) +#define SPI_MEM_CRYPT_CALC_D_DPA_EN_V 0x1 +#define SPI_MEM_CRYPT_CALC_D_DPA_EN_S 3 +/* SPI_MEM_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ +/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1- +7: The bigger the number is, the more secure the cryption is. (Note that the per +formance of cryption will decrease together with this number increasing).*/ +#define SPI_MEM_CRYPT_SECURITY_LEVEL 0x00000007 +#define SPI_MEM_CRYPT_SECURITY_LEVEL_M ((SPI_MEM_CRYPT_SECURITY_LEVEL_V)<<(SPI_MEM_CRYPT_SECURITY_LEVEL_S)) +#define SPI_MEM_CRYPT_SECURITY_LEVEL_V 0x7 +#define SPI_MEM_CRYPT_SECURITY_LEVEL_S 0 + +#define SPI_MEM_REGISTERRND_ECO_HIGH_REG(i) (REG_SPI_MEM_BASE(i) + 0x3F0) +/* SPI_MEM_REGISTERRND_ECO_HIGH : RO ;bitpos:[31:0] ;default: 32'h037c ; */ +/*description: ECO high register.*/ +#define SPI_MEM_REGISTERRND_ECO_HIGH 0xFFFFFFFF +#define SPI_MEM_REGISTERRND_ECO_HIGH_M ((SPI_MEM_REGISTERRND_ECO_HIGH_V)<<(SPI_MEM_REGISTERRND_ECO_HIGH_S)) +#define SPI_MEM_REGISTERRND_ECO_HIGH_V 0xFFFFFFFF +#define SPI_MEM_REGISTERRND_ECO_HIGH_S 0 + +#define SPI_MEM_REGISTERRND_ECO_LOW_REG(i) (REG_SPI_MEM_BASE(i) + 0x3F4) +/* SPI_MEM_REGISTERRND_ECO_LOW : RO ;bitpos:[31:0] ;default: 32'h037c ; */ +/*description: ECO low register.*/ +#define SPI_MEM_REGISTERRND_ECO_LOW 0xFFFFFFFF +#define SPI_MEM_REGISTERRND_ECO_LOW_M ((SPI_MEM_REGISTERRND_ECO_LOW_V)<<(SPI_MEM_REGISTERRND_ECO_LOW_S)) +#define SPI_MEM_REGISTERRND_ECO_LOW_V 0xFFFFFFFF +#define SPI_MEM_REGISTERRND_ECO_LOW_S 0 + +#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3FC) +/* SPI_MEM_DATE : R/W; bitpos: [27:0] ;default: 35663920; */ +/*description: SPI0 register version..*/ +/* SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 35660128; */ +/*description: SPI1 register version..*/ +#define SPI_MEM_DATE 0x0FFFFFFF +#define SPI_MEM_DATE_M ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S)) +#define SPI_MEM_DATE_V 0xFFFFFFF +#define SPI_MEM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/spi_mem_struct.h b/components/soc/esp32c6/include/soc/spi_mem_struct.h new file mode 100644 index 0000000000..9e2f7c1d3b --- /dev/null +++ b/components/soc/esp32c6/include/soc/spi_mem_struct.h @@ -0,0 +1,1081 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct spi_mem_dev_s { + union { + struct { + uint32_t mst_st : 4; /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.*/ + uint32_t slv_st : 4; /*The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.*/ + uint32_t reserved8 : 9; /*reserved*/ + uint32_t flash_pe : 1; /*In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t usr : 1; /*SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_hpm : 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_res : 1; /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_dp : 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_ce : 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_be : 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_se : 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_pp : 1; /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */ + uint32_t flash_wrsr : 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_rdsr : 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_rdid : 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ + uint32_t flash_wrdi : 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ + uint32_t flash_wren : 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ + uint32_t flash_read : 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ + }; + uint32_t val; + } cmd; + uint32_t addr; + union { + struct { + uint32_t wdummy_dqs_always_out : 1; /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller.*/ + uint32_t wdummy_always_out : 1; /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller.*/ + uint32_t fdummy_rin : 1; /*In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase.*/ + uint32_t fdummy_wout : 1; /*In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash.*/ + uint32_t fdout_oct : 1; /*Apply 8 signals during write-data phase 1:enable 0: disable*/ + uint32_t fdin_oct : 1; /*Apply 8 signals during read-data phase 1:enable 0: disable*/ + uint32_t faddr_oct : 1; /*Apply 8 signals during address phase 1:enable 0: disable*/ + uint32_t reserved7 : 1; /*reserved*/ + uint32_t fcmd_quad : 1; /*Apply 4 signals during command phase 1:enable 0: disable*/ + uint32_t fcmd_oct : 1; /*Apply 8 signals during command phase 1:enable 0: disable*/ + uint32_t fcs_crc_en : 1; /*For SPI1, initialize crc32 module before writing encrypted data to flash. Active low.*/ + uint32_t tx_crc_en : 1; /*For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/ + uint32_t reserved12 : 1; /*reserved*/ + uint32_t fastrd_mode : 1; /*This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. */ + uint32_t fread_dual : 1; /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. */ + uint32_t resandres : 1; /*The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */ + uint32_t reserved16 : 2; /*reserved*/ + uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: high 0, low*/ + uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: high 0, low*/ + uint32_t fread_quad : 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. */ + uint32_t wp : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. */ + uint32_t wrsr_2b : 1; /*two bytes data will be written to status register when it is set. 1: enable 0: disable. */ + uint32_t fread_dio : 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. */ + uint32_t fread_qio : 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. */ + uint32_t reserved25 : 5; /*reserved*/ + uint32_t dqs_ie_always_on : 1; /*When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/ + uint32_t data_ie_always_on : 1; /*When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/ + }; + uint32_t val; + } ctrl; + union { + struct { + uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ + uint32_t cs_hold_dly_res : 10; /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/ + uint32_t reserved2 : 9; /*reserved*/ + uint32_t reg_ar_size0_1_support_en : 1; /*1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.*/ + uint32_t reg_aw_size0_1_support_en : 1; /*1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.*/ + uint32_t reg_axi_rdata_back_fast : 1; /*1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available.*/ + uint32_t rresp_ecc_err_en : 1; /*1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG.*/ + uint32_t ar_splice_en : 1; /*Set this bit to enable AXI Read Splice-transfer.*/ + uint32_t aw_splice_en : 1; /*Set this bit to enable AXI Write Splice-transfer.*/ + uint32_t ram0_en : 1; /*When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/ + uint32_t dual_ram_en : 1; /*Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/ + uint32_t fast_write_en : 1; /*Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in tx_bus_fifo_l2.*/ + uint32_t rxfifo_rst : 1; /*The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI. Set this bit to reset these FIFO.*/ + uint32_t txfifo_rst : 1; /*The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO.*/ + }; + uint32_t val; + } ctrl1; + union { + struct { + uint32_t cs_setup_time : 5; /*(cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit.*/ + uint32_t cs_hold_time : 5; /*SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit.*/ + uint32_t ecc_cs_hold_time : 3; /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash.*/ + uint32_t ecc_skip_page_corner : 1; /*1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash.*/ + uint32_t ecc_16to18_byte_en : 1; /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash.*/ + uint32_t reserved15 : 9; /*reserved*/ + uint32_t split_trans_en : 1; /*Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/ + uint32_t cs_hold_delay : 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/ + uint32_t sync_reset : 1; /*The spi0_mst_st and spi0_slv_st will be reset.*/ + }; + uint32_t val; + } ctrl2; + union { + struct { + uint32_t clkcnt_l : 8; /*In the master mode it must be equal to spi_mem_clkcnt_N. */ + uint32_t clkcnt_h : 8; /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ + uint32_t clkcnt_n : 8; /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/ + uint32_t reserved24 : 7; /*In the master mode it is pre-divider of spi_mem_clk. */ + uint32_t clk_equ_sysclk : 1; /*1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock.*/ + }; + uint32_t val; + } clock; + union { + struct { + uint32_t reserved0 : 6; /*reserved*/ + uint32_t cs_hold : 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable. */ + uint32_t cs_setup : 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable. */ + uint32_t reserved8 : 1; /*reserved*/ + uint32_t ck_out_edge : 1; /*The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3.*/ + uint32_t reserved10 : 2; /*reserved*/ + uint32_t fwrite_dual : 1; /*In the write operations read-data phase apply 2 signals*/ + uint32_t fwrite_quad : 1; /*In the write operations read-data phase apply 4 signals*/ + uint32_t fwrite_dio : 1; /*In the write operations address phase and read-data phase apply 2 signals.*/ + uint32_t fwrite_qio : 1; /*In the write operations address phase and read-data phase apply 4 signals.*/ + uint32_t reserved16 : 8; /*reserved*/ + uint32_t usr_miso_highpart : 1; /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */ + uint32_t usr_mosi_highpart : 1; /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */ + uint32_t usr_dummy_idle : 1; /*spi clock is disable in dummy phase when the bit is enable.*/ + uint32_t usr_mosi : 1; /*This bit enable the write-data phase of an operation.*/ + uint32_t usr_miso : 1; /*This bit enable the read-data phase of an operation.*/ + uint32_t usr_dummy : 1; /*This bit enable the dummy phase of an operation.*/ + uint32_t usr_addr : 1; /*This bit enable the address phase of an operation.*/ + uint32_t usr_command : 1; /*This bit enable the command phase of an operation.*/ + }; + uint32_t val; + } user; + union { + struct { + uint32_t usr_dummy_cyclelen : 6; /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/ + uint32_t usr_dbytelen : 3; /*SPI0 USR_CMD read or write data byte length -1*/ + uint32_t reserved9 : 17; /*reserved*/ + uint32_t usr_addr_bitlen : 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/ + }; + uint32_t val; + } user1; + union { + struct { + uint32_t usr_command_value : 16; /*The value of command.*/ + uint32_t reserved16 : 12; /*reserved*/ + uint32_t usr_command_bitlen : 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/ + }; + uint32_t val; + } user2; + union { + struct { + uint32_t usr_mosi_bit_len : 10; /*The length in bits of write-data. The register value shall be (bit_num-1).*/ + uint32_t reserved10 : 22; /*reserved*/ + }; + uint32_t val; + } mosi_dlen; + union { + struct { + uint32_t usr_miso_bit_len : 10; /*The length in bits of read-data. The register value shall be (bit_num-1).*/ + uint32_t reserved10 : 22; /*reserved*/ + }; + uint32_t val; + } miso_dlen; + union { + struct { + uint32_t status : 16; /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/ + uint32_t wb_mode : 8; /*Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.*/ + uint32_t reserved24 : 8; /*reserved*/ + }; + uint32_t val; + } rd_status; + uint32_t reserved_30; + union { + struct { + uint32_t cs0_dis : 1; /*SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.*/ + uint32_t cs1_dis : 1; /*SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.*/ + uint32_t reserved0 : 5; /*reserved*/ + uint32_t fsub_pin : 1; /*For SPI0, flash is connected to SUBPINs.*/ + uint32_t ssub_pin : 1; /*For SPI0, sram is connected to SUBPINs.*/ + uint32_t ck_idle_edge : 1; /*1: SPI_CLK line is high when idle 0: spi clk line is low when idle */ + uint32_t cs_keep_active : 1; /*SPI_CS line keep low when the bit is set.*/ + uint32_t reserved11 : 21; /*reserved*/ + }; + uint32_t val; + } misc; + uint32_t tx_crc; + union { + struct { + uint32_t axi_req_en : 1; /*For SPI0, AXI master access enable, 1: enable, 0:disable.*/ + uint32_t usr_addr_4byte : 1; /*For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable.*/ + uint32_t flash_usr_cmd : 1; /*For SPI0, cache read flash for user define command, 1: enable, 0:disable.*/ + uint32_t fdin_dual : 1; /*For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ + uint32_t fdout_dual : 1; /*For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ + uint32_t faddr_dual : 1; /*For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ + uint32_t fdin_quad : 1; /*For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ + uint32_t fdout_quad : 1; /*For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ + uint32_t faddr_quad : 1; /*For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ + uint32_t reserved9 : 21; /*reserved*/ + uint32_t reg_same_aw_ar_addr_chk_en : 1; /*Set this bit to check AXI read/write the same address region.*/ + uint32_t reg_close_axi_inf_en : 1; /*Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP.*/ + }; + uint32_t val; + } cache_fctrl; + union { + struct { + uint32_t usr_saddr_4byte : 1; /*For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable.*/ + uint32_t usr_sram_dio : 1; /*For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable*/ + uint32_t usr_sram_qio : 1; /*For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable*/ + uint32_t usr_wr_sram_dummy : 1; /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations.*/ + uint32_t usr_rd_sram_dummy : 1; /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations.*/ + uint32_t sram_usr_rcmd : 1; /*For SPI0, In the external RAM mode cache read external RAM for user define command.*/ + uint32_t sram_rdummy_cyclelen : 6; /*For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1).*/ + uint32_t reserved12 : 2; /*reserved*/ + uint32_t sram_addr_bitlen : 6; /*For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1).*/ + uint32_t sram_usr_wcmd : 1; /*For SPI0, In the external RAM mode cache write sram for user define command*/ + uint32_t sram_oct : 1; /*reserved*/ + uint32_t sram_wdummy_cyclelen : 6; /*For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1).*/ + uint32_t reserved28 : 4; /*reserved*/ + }; + uint32_t val; + } cache_sctrl; + union { + struct { + uint32_t sclk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/ + uint32_t swb_mode : 8; /*Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit.*/ + uint32_t sdin_dual : 1; /*For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/ + uint32_t sdout_dual : 1; /*For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/ + uint32_t saddr_dual : 1; /*For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/ + uint32_t reserved13 : 1; /*reserved*/ + uint32_t sdin_quad : 1; /*For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ + uint32_t sdout_quad : 1; /*For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ + uint32_t saddr_quad : 1; /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ + uint32_t scmd_quad : 1; /*For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ + uint32_t sdin_oct : 1; /*For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. */ + uint32_t sdout_oct : 1; /*For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. */ + uint32_t saddr_oct : 1; /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. */ + uint32_t scmd_oct : 1; /*For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. */ + uint32_t sdummy_rin : 1; /*In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/ + uint32_t sdummy_wout : 1; /*In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/ + uint32_t reg_smem_wdummy_dqs_always_out: 1; /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller.*/ + uint32_t reg_smem_wdummy_always_out : 1; /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller.*/ + uint32_t reserved26 : 4; /*reserved*/ + uint32_t reg_smem_dqs_ie_always_on : 1; /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/ + uint32_t reg_smem_data_ie_always_on : 1; /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/ + }; + uint32_t val; + } sram_cmd; + union { + struct { + uint32_t sram_usr_rd_cmd_value : 16; /*For SPI0,When cache mode is enable it is the read command value of command phase for sram.*/ + uint32_t reserved16 : 12; /*reserved*/ + uint32_t sram_usr_rd_cmd_bitlen : 4; /*For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1).*/ + }; + uint32_t val; + } sram_drd_cmd; + union { + struct { + uint32_t sram_usr_wr_cmd_value : 16; /*For SPI0,When cache mode is enable it is the write command value of command phase for sram.*/ + uint32_t reserved16 : 12; /*reserved*/ + uint32_t sram_usr_wr_cmd_bitlen : 4; /*For SPI0,When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1).*/ + }; + uint32_t val; + } sram_dwr_cmd; + union { + struct { + uint32_t sclkcnt_l : 8; /*For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N.*/ + uint32_t sclkcnt_h : 8; /*For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ + uint32_t sclkcnt_n : 8; /*For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/ + uint32_t reserved24 : 7; /*reserved*/ + uint32_t sclk_equ_sysclk : 1; /*For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/ + }; + uint32_t val; + } sram_clk; + union { + struct { + uint32_t reserved0 : 7; /*reserved*/ + uint32_t lock_delay_time : 5; /*The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.*/ + uint32_t reserved12 : 20; /*reserved*/ + }; + uint32_t val; + } fsm; + uint32_t data_buf[16]; + union { + struct { + uint32_t waiti_en : 1; /*1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported.*/ + uint32_t waiti_dummy : 1; /*The dummy phase enable when wait flash idle (RDSR)*/ + uint32_t waiti_addr_en : 1; /*1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer.*/ + uint32_t waiti_addr_cyclelen : 2; /*When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared.*/ + uint32_t reserved5 : 4; /*reserved*/ + uint32_t waiti_cmd_2b : 1; /*1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.*/ + uint32_t waiti_dummy_cyclelen : 6; /*The dummy cycle length when wait flash idle(RDSR).*/ + uint32_t waiti_cmd : 16; /*The command value to wait flash idle(RDSR).*/ + }; + uint32_t val; + } flash_waiti_ctrl; + union { + struct { + uint32_t flash_per : 1; /*program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_pes : 1; /*program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ + uint32_t flash_per_wait_en : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. */ + uint32_t flash_pes_wait_en : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. */ + uint32_t pes_per_en : 1; /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.*/ + uint32_t flash_pes_en : 1; /*Set this bit to enable Auto-suspending function.*/ + uint32_t pesr_end_msk : 16; /*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/ + uint32_t frd_sus_2b : 1; /*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit*/ + uint32_t per_end_en : 1; /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/ + uint32_t pes_end_en : 1; /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/ + uint32_t sus_timeout_cnt : 7; /*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.*/ + }; + uint32_t val; + } flash_sus_ctrl; + union { + struct { + uint32_t flash_pes_command : 16; /*Program/Erase suspend command.*/ + uint32_t wait_pesr_command : 16; /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/ + }; + uint32_t val; + } flash_sus_cmd; + union { + struct { + uint32_t flash_sus : 1; /*The status of flash suspend, only used in SPI1.*/ + uint32_t wait_pesr_cmd_2b : 1; /*1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.*/ + uint32_t flash_hpm_dly_128 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/ + uint32_t flash_res_dly_128 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/ + uint32_t flash_dp_dly_128 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/ + uint32_t flash_per_dly_128 : 1; /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/ + uint32_t flash_pes_dly_128 : 1; /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/ + uint32_t spi0_lock_en : 1; /*1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.*/ + uint32_t reserved8 : 7; /*reserved*/ + uint32_t flash_pesr_cmd_2b : 1; /*1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8.*/ + uint32_t flash_per_command : 16; /*Program/Erase resume command.*/ + }; + uint32_t val; + } sus_status; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + union { + struct { + uint32_t per_end_en : 1; /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/ + uint32_t pes_end_en : 1; /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/ + uint32_t wpe_end_en : 1; /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/ + uint32_t slv_st_end_en : 1; /*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ + uint32_t mst_st_end_en : 1; /*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/ + uint32_t ecc_err_en : 1; /*The enable bit for SPI_MEM_ECC_ERR_INT interrupt.*/ + uint32_t pms_reject_en : 1; /*The enable bit for SPI_MEM_PMS_REJECT_INT interrupt.*/ + uint32_t axi_raddr_err_en : 1; /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/ + uint32_t axi_wr_flash_err_en : 1; /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/ + uint32_t axi_waddr_err_en : 1; /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/ + uint32_t brown_out_en : 1; /*The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.*/ + uint32_t reserved11 : 21; /*reserved*/ + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t per_end : 1; /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/ + uint32_t pes_end : 1; /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/ + uint32_t wpe_end : 1; /*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/ + uint32_t slv_st_end : 1; /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ + uint32_t mst_st_end : 1; /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/ + uint32_t ecc_err : 1; /*The clear bit for SPI_MEM_ECC_ERR_INT interrupt.*/ + uint32_t pms_reject : 1; /*The clear bit for SPI_MEM_PMS_REJECT_INT interrupt.*/ + uint32_t axi_raddr_err : 1; /*The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/ + uint32_t axi_wr_flash_err : 1; /*The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/ + uint32_t axi_waddr_err : 1; /*The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/ + uint32_t brown_out : 1; /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/ + uint32_t reserved11 : 21; /*reserved*/ + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t per_end : 1; /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.*/ + uint32_t pes_end : 1; /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.*/ + uint32_t wpe_end : 1; /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/ + uint32_t slv_st_end : 1; /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/ + uint32_t mst_st_end : 1; /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others.*/ + uint32_t ecc_err : 1; /*The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered.*/ + uint32_t pms_reject : 1; /*The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others.*/ + uint32_t axi_raddr_err : 1; /*The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others.*/ + uint32_t axi_wr_flash_err : 1; /*The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others.*/ + uint32_t axi_waddr_err : 1; /*The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others.*/ + uint32_t brown_out : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/ + uint32_t reserved11 : 21; /*reserved*/ + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t per_end : 1; /*The status bit for SPI_MEM_PER_END_INT interrupt.*/ + uint32_t pes_end : 1; /*The status bit for SPI_MEM_PES_END_INT interrupt.*/ + uint32_t wpe_end : 1; /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/ + uint32_t slv_st_end : 1; /*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ + uint32_t mst_st_end : 1; /*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/ + uint32_t ecc_err : 1; /*The status bit for SPI_MEM_ECC_ERR_INT interrupt.*/ + uint32_t pms_reject : 1; /*The status bit for SPI_MEM_PMS_REJECT_INT interrupt.*/ + uint32_t axi_raddr_err : 1; /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/ + uint32_t axi_wr_flash_err : 1; /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/ + uint32_t axi_waddr_err : 1; /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/ + uint32_t brown_out : 1; /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/ + uint32_t reserved11 : 21; /*reserved*/ + }; + uint32_t val; + } int_st; + uint32_t reserved_d0; + union { + struct { + uint32_t reg_fmem_ddr_en : 1; /*1: in DDR mode, 0 in SDR mode*/ + uint32_t reg_fmem_var_dummy : 1; /*Set the bit to enable variable dummy cycle in spi DDR mode.*/ + uint32_t reg_fmem_ddr_rdat_swp : 1; /*Set the bit to reorder rx data of the word in spi DDR mode.*/ + uint32_t reg_fmem_ddr_wdat_swp : 1; /*Set the bit to reorder tx data of the word in spi DDR mode.*/ + uint32_t reg_fmem_ddr_cmd_dis : 1; /*the bit is used to disable dual edge in command phase when DDR mode.*/ + uint32_t reg_fmem_outminbytelen : 7; /*It is the minimum output data length in the panda device.*/ + uint32_t reg_fmem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash.*/ + uint32_t reg_fmem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash.*/ + uint32_t reg_fmem_usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI clock.*/ + uint32_t reg_fmem_ddr_dqs_loop : 1; /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/ + uint32_t reserved22 : 2; /*reserved*/ + uint32_t reg_fmem_clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/ + uint32_t reserved25 : 1; /*reserved*/ + uint32_t reg_fmem_dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/ + uint32_t reg_fmem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/ + uint32_t reg_fmem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to flash. .*/ + uint32_t reg_fmem_octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/ + uint32_t reg_fmem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/ + uint32_t reserved31 : 1; /*reserved*/ + }; + uint32_t val; + } ddr; + union { + struct { + uint32_t reg_smem_ddr_en : 1; /*1: in DDR mode, 0 in SDR mode*/ + uint32_t reg_smem_var_dummy : 1; /*Set the bit to enable variable dummy cycle in spi DDR mode.*/ + uint32_t reg_smem_ddr_rdat_swp : 1; /*Set the bit to reorder rx data of the word in spi DDR mode.*/ + uint32_t reg_smem_ddr_wdat_swp : 1; /*Set the bit to reorder tx data of the word in spi DDR mode.*/ + uint32_t reg_smem_ddr_cmd_dis : 1; /*the bit is used to disable dual edge in command phase when DDR mode.*/ + uint32_t reg_smem_outminbytelen : 7; /*It is the minimum output data length in the DDR psram.*/ + uint32_t reg_smem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM.*/ + uint32_t reg_smem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM.*/ + uint32_t reg_smem_usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI clock.*/ + uint32_t reg_smem_ddr_dqs_loop : 1; /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/ + uint32_t reserved22 : 2; /*reserved*/ + uint32_t reg_smem_clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/ + uint32_t reserved25 : 1; /*reserved*/ + uint32_t reg_smem_dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/ + uint32_t reg_smem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/ + uint32_t reg_smem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to external RAM. .*/ + uint32_t reg_smem_octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/ + uint32_t reg_smem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/ + uint32_t reserved31 : 1; /*reserved*/ + }; + uint32_t val; + } spi_smem_ddr; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t reserved_fc; + union { + struct { + uint32_t reg_fmem_pms0_rd_attr : 1; /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms0_wr_attr : 1; /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms0_ecc : 1; /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms0_attr; + union { + struct { + uint32_t reg_fmem_pms1_rd_attr : 1; /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms1_wr_attr : 1; /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms1_ecc : 1; /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms1_attr; + union { + struct { + uint32_t reg_fmem_pms2_rd_attr : 1; /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms2_wr_attr : 1; /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms2_ecc : 1; /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms2_attr; + union { + struct { + uint32_t reg_fmem_pms3_rd_attr : 1; /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms3_wr_attr : 1; /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/ + uint32_t reg_fmem_pms3_ecc : 1; /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms3_attr; + union { + struct { + uint32_t reg_fmem_pms0_addr_s : 26; /*SPI1 flash ACE section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms0_addr; + union { + struct { + uint32_t reg_fmem_pms1_addr_s : 26; /*SPI1 flash ACE section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms1_addr; + union { + struct { + uint32_t reg_fmem_pms2_addr_s : 26; /*SPI1 flash ACE section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms2_addr; + union { + struct { + uint32_t reg_fmem_pms3_addr_s : 26; /*SPI1 flash ACE section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms3_addr; + union { + struct { + uint32_t reg_fmem_pms0_size : 14; /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms0_size; + union { + struct { + uint32_t reg_fmem_pms1_size : 14; /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms1_size; + union { + struct { + uint32_t reg_fmem_pms2_size : 14; /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms2_size; + union { + struct { + uint32_t reg_fmem_pms3_size : 14; /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_fmem_pms3_size; + union { + struct { + uint32_t reg_smem_pms0_rd_attr : 1; /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms0_wr_attr : 1; /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms0_ecc : 1; /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms0_attr; + union { + struct { + uint32_t reg_smem_pms1_rd_attr : 1; /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms1_wr_attr : 1; /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms1_ecc : 1; /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms1_attr; + union { + struct { + uint32_t reg_smem_pms2_rd_attr : 1; /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms2_wr_attr : 1; /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms2_ecc : 1; /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms2_attr; + union { + struct { + uint32_t reg_smem_pms3_rd_attr : 1; /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms3_wr_attr : 1; /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/ + uint32_t reg_smem_pms3_ecc : 1; /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/ + uint32_t reserved3 : 29; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms3_attr; + union { + struct { + uint32_t reg_smem_pms0_addr_s : 26; /*SPI1 external RAM ACE section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms0_addr; + union { + struct { + uint32_t reg_smem_pms1_addr_s : 26; /*SPI1 external RAM ACE section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms1_addr; + union { + struct { + uint32_t reg_smem_pms2_addr_s : 26; /*SPI1 external RAM ACE section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms2_addr; + union { + struct { + uint32_t reg_smem_pms3_addr_s : 26; /*SPI1 external RAM ACE section $n start address value*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms3_addr; + union { + struct { + uint32_t reg_smem_pms0_size : 14; /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms0_size; + union { + struct { + uint32_t reg_smem_pms1_size : 14; /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms1_size; + union { + struct { + uint32_t reg_smem_pms2_size : 14; /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms2_size; + union { + struct { + uint32_t reg_smem_pms3_size : 14; /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/ + uint32_t reserved14 : 18; /*reserved*/ + }; + uint32_t val; + } spi_smem_pms3_size; + uint32_t reserved_160; + union { + struct { + uint32_t reject_addr : 26; /*This bits show the first SPI1 access error address. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ + uint32_t pm_en : 1; /*Set this bit to enable SPI0/1 transfer permission control function.*/ + uint32_t reserved27 : 1; /*reserved*/ + uint32_t pms_ld : 1; /*1: SPI1 write access error. 0: No write access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ + uint32_t pms_st : 1; /*1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ + uint32_t pms_multi_hit : 1; /*1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ + uint32_t pms_ivd : 1; /*1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ + }; + uint32_t val; + } pms_reject; + union { + struct { + uint32_t reserved0 : 11; /*reserved*/ + uint32_t ecc_err_int_num : 6; /*Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.*/ + uint32_t reg_fmem_ecc_err_int_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when accesses to flash.*/ + uint32_t reg_fmem_page_size : 2; /*Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/ + uint32_t reg_fmem_ecc_addr_en : 1; /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1.*/ + uint32_t usr_ecc_addr_en : 1; /*Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer.*/ + uint32_t reserved22 : 2; /*reserved*/ + uint32_t ecc_continue_record_err_en : 1; /*1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information.*/ + uint32_t ecc_err_bits : 7; /*Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7)*/ + }; + uint32_t val; + } ecc_ctrl; + union { + struct { + uint32_t ecc_err_addr : 26; /*This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. */ + uint32_t ecc_err_cnt : 6; /*This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. */ + }; + uint32_t val; + } ecc_err_addr; + union { + struct { + uint32_t axi_err_addr : 26; /*This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. */ + uint32_t all_fifo_empty : 1; /*The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others.*/ + uint32_t reg_rdata_afifo_rempty : 1; /*1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.*/ + uint32_t reg_raddr_afifo_rempty : 1; /*1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.*/ + uint32_t reg_wdata_afifo_rempty : 1; /*1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.*/ + uint32_t reg_wblen_afifo_rempty : 1; /*1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.*/ + uint32_t reg_all_axi_trans_afifo_empty : 1; /*This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE.*/ + }; + uint32_t val; + } axi_err_addr; + union { + struct { + uint32_t reserved0 : 17; /*reserved*/ + uint32_t reg_smem_ecc_err_int_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.*/ + uint32_t reg_smem_page_size : 2; /*Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/ + uint32_t reg_smem_ecc_addr_en : 1; /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1.*/ + uint32_t reserved21 : 11; /*reserved*/ + }; + uint32_t val; + } spi_smem_ecc_ctrl; + uint32_t reserved_178; + uint32_t reserved_17c; + union { + struct { + uint32_t timing_clk_ena : 1; /*The bit is used to enable timing adjust clock for all reading operations.*/ + uint32_t timing_cali : 1; /*The bit is used to enable timing auto-calibration for all reading operations.*/ + uint32_t extra_dummy_cyclelen : 3; /*add extra dummy spi clock cycle length for spi clock calibration.*/ + uint32_t dll_timing_cali : 1; /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash.*/ + uint32_t timing_cali_update : 1; /*Set this bit to update delay mode, delay num and extra dummy in MSPI.*/ + uint32_t reserved7 : 25; /*reserved*/ + }; + uint32_t val; + } timing_cali; + union { + struct { + uint32_t din0_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din1_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din2_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din3_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t din4_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ + uint32_t din5_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ + uint32_t din6_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ + uint32_t din7_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ + uint32_t dins_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ + uint32_t reserved27 : 5; /*reserved*/ + }; + uint32_t val; + } din_mode; + union { + struct { + uint32_t din0_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din1_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din2_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din3_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din4_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din5_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din6_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t din7_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t dins_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reserved18 : 14; /*reserved*/ + }; + uint32_t val; + } din_num; + union { + struct { + uint32_t dout0_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout1_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout2_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout3_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t dout4_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ + uint32_t dout5_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ + uint32_t dout6_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ + uint32_t dout7_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ + uint32_t douts_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ + uint32_t reserved9 : 23; /*reserved*/ + }; + uint32_t val; + } dout_mode; + union { + struct { + uint32_t reg_smem_timing_clk_ena : 1; /*For sram, the bit is used to enable timing adjust clock for all reading operations.*/ + uint32_t reg_smem_timing_cali : 1; /*For sram, the bit is used to enable timing auto-calibration for all reading operations.*/ + uint32_t reg_smem_extra_dummy_cyclelen : 3; /*For sram, add extra dummy spi clock cycle length for spi clock calibration.*/ + uint32_t reg_smem_dll_timing_cali : 1; /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM.*/ + uint32_t reserved6 : 26; /*reserved*/ + }; + uint32_t val; + } spi_smem_timing_cali; + union { + struct { + uint32_t reg_smem_din0_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din1_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din2_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din3_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din4_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din5_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din6_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_din7_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reg_smem_dins_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reserved27 : 5; /*reserved*/ + }; + uint32_t val; + } spi_smem_din_mode; + union { + struct { + uint32_t reg_smem_din0_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din1_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din2_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din3_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din4_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din5_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din6_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_din7_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ + uint32_t reg_smem_dins_num : 2; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ + uint32_t reserved18 : 14; /*reserved*/ + }; + uint32_t val; + } spi_smem_din_num; + union { + struct { + uint32_t reg_smem_dout0_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout1_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout2_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout3_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout4_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout5_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout6_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_dout7_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reg_smem_douts_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ + uint32_t reserved9 : 23; /*reserved*/ + }; + uint32_t val; + } spi_smem_dout_mode; + union { + struct { + uint32_t reg_smem_cs_setup : 1; /*For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable. */ + uint32_t reg_smem_cs_hold : 1; /*For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. */ + uint32_t reg_smem_cs_setup_time : 5; /*For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/ + uint32_t reg_smem_cs_hold_time : 5; /*For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/ + uint32_t reg_smem_ecc_cs_hold_time : 3; /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM.*/ + uint32_t reg_smem_ecc_skip_page_corner : 1; /*1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM.*/ + uint32_t reg_smem_ecc_16to18_byte_en : 1; /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM.*/ + uint32_t reserved17 : 8; /*reserved*/ + uint32_t reg_smem_cs_hold_delay : 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/ + uint32_t reg_smem_split_trans_en : 1; /*Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/ + }; + uint32_t val; + } spi_smem_ac; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + union { + struct { + uint32_t reg_clk_en : 1; /*Register clock gate enable signal. 1: Enable. 0: Disable.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } clock_gate; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t xts_plain_base; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + union { + struct { + uint32_t reg_xts_linesize : 2; /*This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved.*/ + uint32_t reserved2 : 30; /*reserved*/ + }; + uint32_t val; + } xts_linesize; + union { + struct { + uint32_t reg_xts_destination : 1; /*This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } xts_destination; + union { + struct { + uint32_t reg_xts_physical_address : 26; /*This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter.*/ + uint32_t reserved26 : 6; /*reserved*/ + }; + uint32_t val; + } xts_physical_address; + union { + struct { + uint32_t reg_xts_trigger : 1; /*Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } xts_trigger; + union { + struct { + uint32_t reg_xts_release : 1; /*Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } xts_release; + union { + struct { + uint32_t reg_xts_destroy : 1; /*Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } xts_destroy; + union { + struct { + uint32_t reg_xts_state : 2; /*This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi.*/ + uint32_t reserved2 : 30; /*reserved*/ + }; + uint32_t val; + } xts_state; + union { + struct { + uint32_t reg_xts_date : 30; /*This bits stores the last modified-time of manual encryption feature.*/ + uint32_t reserved30 : 2; /*reserved*/ + }; + uint32_t val; + } xts_date; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t mmu_item_content; + uint32_t mmu_item_index; + union { + struct { + uint32_t reg_mmu_mem_force_on : 1; /*Set this bit to enable mmu-memory clock force on*/ + uint32_t reg_mmu_mem_force_pd : 1; /*Set this bit to force mmu-memory powerdown*/ + uint32_t reg_mmu_mem_force_pu : 1; /*Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc.*/ + uint32_t reg_mmu_page_size : 2; /*0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8*/ + uint32_t reserved5 : 11; /*reserved*/ + uint32_t aux_ctrl : 14; /*MMU PSRAM aux control register*/ + uint32_t rdn_ena : 1; /*ECO register enable bit*/ + uint32_t rdn_result : 1; /*MSPI module clock domain and AXI clock domain ECO register result register*/ + }; + uint32_t val; + } mmu_power_ctrl; + union { + struct { + uint32_t reg_crypt_security_level : 3; /*Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/ + uint32_t reg_crypt_calc_d_dpa_en : 1; /*Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1.*/ + uint32_t reg_crypt_dpa_selectister : 1; /*1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.*/ + uint32_t reserved5 : 27; /*reserved*/ + }; + uint32_t val; + } dpa_ctrl; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t spi_memisterrnd_eco_high; + uint32_t spi_memisterrnd_eco_low; + uint32_t reserved_3f8; + union { + struct { + uint32_t date : 28; /*SPI0/1 register version.*/ + uint32_t reserved28 : 4; /*reserved*/ + }; + uint32_t val; + } date; +} spi_mem_dev_t; + +extern spi_mem_dev_t SPIMEM0; +extern spi_mem_dev_t SPIMEM1; + +#ifndef __cplusplus +_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "Invalid size of spi_mem_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/spi_pins.h b/components/soc/esp32c6/include/soc/spi_pins.h new file mode 100644 index 0000000000..a2fd8ef943 --- /dev/null +++ b/components/soc/esp32c6/include/soc/spi_pins.h @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_SPI_PINS_H_ +#define _SOC_SPI_PINS_H_ + +#define SPI_FUNC_NUM 0 +#define SPI_IOMUX_PIN_NUM_HD 12 +#define SPI_IOMUX_PIN_NUM_CS 14 +#define SPI_IOMUX_PIN_NUM_MOSI 16 +#define SPI_IOMUX_PIN_NUM_CLK 15 +#define SPI_IOMUX_PIN_NUM_MISO 17 +#define SPI_IOMUX_PIN_NUM_WP 13 + +#define SPI2_FUNC_NUM 2 +#define SPI2_IOMUX_PIN_NUM_MISO 2 +#define SPI2_IOMUX_PIN_NUM_HD 4 +#define SPI2_IOMUX_PIN_NUM_WP 5 +#define SPI2_IOMUX_PIN_NUM_CLK 6 +#define SPI2_IOMUX_PIN_NUM_MOSI 7 +#define SPI2_IOMUX_PIN_NUM_CS 10 + +#endif diff --git a/components/soc/esp32c6/include/soc/spi_reg.h b/components/soc/esp32c6/include/soc/spi_reg.h new file mode 100644 index 0000000000..544b54abd1 --- /dev/null +++ b/components/soc/esp32c6/include/soc/spi_reg.h @@ -0,0 +1,2108 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI_CMD_REG register + * Command control register + */ +#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) +/** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0; + * Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + */ +#define SPI_CONF_BITLEN 0x0003FFFFU +#define SPI_CONF_BITLEN_M (SPI_CONF_BITLEN_V << SPI_CONF_BITLEN_S) +#define SPI_CONF_BITLEN_V 0x0003FFFFU +#define SPI_CONF_BITLEN_S 0 +/** SPI_UPDATE : WT; bitpos: [23]; default: 0; + * Set this bit to synchronize SPI registers from APB clock domain into SPI module + * clock domain, which is only used in SPI master mode. + */ +#define SPI_UPDATE (BIT(23)) +#define SPI_UPDATE_M (SPI_UPDATE_V << SPI_UPDATE_S) +#define SPI_UPDATE_V 0x00000001U +#define SPI_UPDATE_S 23 +/** SPI_USR : R/W/SC; bitpos: [24]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. Can not be + * changed by CONF_buf. + */ +#define SPI_USR (BIT(24)) +#define SPI_USR_M (SPI_USR_V << SPI_USR_S) +#define SPI_USR_V 0x00000001U +#define SPI_USR_S 24 + +/** SPI_ADDR_REG register + * Address value register + */ +#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4) +/** SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0; + * Address to slave. Can be configured in CONF state. + */ +#define SPI_USR_ADDR_VALUE 0xFFFFFFFFU +#define SPI_USR_ADDR_VALUE_M (SPI_USR_ADDR_VALUE_V << SPI_USR_ADDR_VALUE_S) +#define SPI_USR_ADDR_VALUE_V 0xFFFFFFFFU +#define SPI_USR_ADDR_VALUE_S 0 + +/** SPI_CTRL_REG register + * SPI control register + */ +#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8) +/** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0; + * 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, + * the FSPI bus signals are output. Can be configured in CONF state. + */ +#define SPI_DUMMY_OUT (BIT(3)) +#define SPI_DUMMY_OUT_M (SPI_DUMMY_OUT_V << SPI_DUMMY_OUT_S) +#define SPI_DUMMY_OUT_V 0x00000001U +#define SPI_DUMMY_OUT_S 3 +/** SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0; + * Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FADDR_DUAL (BIT(5)) +#define SPI_FADDR_DUAL_M (SPI_FADDR_DUAL_V << SPI_FADDR_DUAL_S) +#define SPI_FADDR_DUAL_V 0x00000001U +#define SPI_FADDR_DUAL_S 5 +/** SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0; + * Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FADDR_QUAD (BIT(6)) +#define SPI_FADDR_QUAD_M (SPI_FADDR_QUAD_V << SPI_FADDR_QUAD_S) +#define SPI_FADDR_QUAD_V 0x00000001U +#define SPI_FADDR_QUAD_S 6 +/** SPI_FADDR_OCT : HRO; bitpos: [7]; default: 0; + * Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FADDR_OCT (BIT(7)) +#define SPI_FADDR_OCT_M (SPI_FADDR_OCT_V << SPI_FADDR_OCT_S) +#define SPI_FADDR_OCT_V 0x00000001U +#define SPI_FADDR_OCT_S 7 +/** SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0; + * Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FCMD_DUAL (BIT(8)) +#define SPI_FCMD_DUAL_M (SPI_FCMD_DUAL_V << SPI_FCMD_DUAL_S) +#define SPI_FCMD_DUAL_V 0x00000001U +#define SPI_FCMD_DUAL_S 8 +/** SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FCMD_QUAD (BIT(9)) +#define SPI_FCMD_QUAD_M (SPI_FCMD_QUAD_V << SPI_FCMD_QUAD_S) +#define SPI_FCMD_QUAD_V 0x00000001U +#define SPI_FCMD_QUAD_S 9 +/** SPI_FCMD_OCT : HRO; bitpos: [10]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FCMD_OCT (BIT(10)) +#define SPI_FCMD_OCT_M (SPI_FCMD_OCT_V << SPI_FCMD_OCT_S) +#define SPI_FCMD_OCT_V 0x00000001U +#define SPI_FCMD_OCT_S 10 +/** SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ +#define SPI_FREAD_DUAL (BIT(14)) +#define SPI_FREAD_DUAL_M (SPI_FREAD_DUAL_V << SPI_FREAD_DUAL_S) +#define SPI_FREAD_DUAL_V 0x00000001U +#define SPI_FREAD_DUAL_S 14 +/** SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ +#define SPI_FREAD_QUAD (BIT(15)) +#define SPI_FREAD_QUAD_M (SPI_FREAD_QUAD_V << SPI_FREAD_QUAD_S) +#define SPI_FREAD_QUAD_V 0x00000001U +#define SPI_FREAD_QUAD_S 15 +/** SPI_FREAD_OCT : HRO; bitpos: [16]; default: 0; + * In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ +#define SPI_FREAD_OCT (BIT(16)) +#define SPI_FREAD_OCT_M (SPI_FREAD_OCT_V << SPI_FREAD_OCT_S) +#define SPI_FREAD_OCT_V 0x00000001U +#define SPI_FREAD_OCT_S 16 +/** SPI_Q_POL : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ +#define SPI_Q_POL (BIT(18)) +#define SPI_Q_POL_M (SPI_Q_POL_V << SPI_Q_POL_S) +#define SPI_Q_POL_V 0x00000001U +#define SPI_Q_POL_S 18 +/** SPI_D_POL : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ +#define SPI_D_POL (BIT(19)) +#define SPI_D_POL_M (SPI_D_POL_V << SPI_D_POL_S) +#define SPI_D_POL_V 0x00000001U +#define SPI_D_POL_S 19 +/** SPI_HOLD_POL : R/W; bitpos: [20]; default: 1; + * SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be + * configured in CONF state. + */ +#define SPI_HOLD_POL (BIT(20)) +#define SPI_HOLD_POL_M (SPI_HOLD_POL_V << SPI_HOLD_POL_S) +#define SPI_HOLD_POL_V 0x00000001U +#define SPI_HOLD_POL_S 20 +/** SPI_WP_POL : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. Can + * be configured in CONF state. + */ +#define SPI_WP_POL (BIT(21)) +#define SPI_WP_POL_M (SPI_WP_POL_V << SPI_WP_POL_S) +#define SPI_WP_POL_V 0x00000001U +#define SPI_WP_POL_S 21 +/** SPI_RD_BIT_ORDER : R/W; bitpos: [24:23]; default: 0; + * In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF + * state. + */ +#define SPI_RD_BIT_ORDER 0x00000003U +#define SPI_RD_BIT_ORDER_M (SPI_RD_BIT_ORDER_V << SPI_RD_BIT_ORDER_S) +#define SPI_RD_BIT_ORDER_V 0x00000003U +#define SPI_RD_BIT_ORDER_S 23 +/** SPI_WR_BIT_ORDER : R/W; bitpos: [26:25]; default: 0; + * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be + * configured in CONF state. + */ +#define SPI_WR_BIT_ORDER 0x00000003U +#define SPI_WR_BIT_ORDER_M (SPI_WR_BIT_ORDER_V << SPI_WR_BIT_ORDER_S) +#define SPI_WR_BIT_ORDER_V 0x00000003U +#define SPI_WR_BIT_ORDER_S 25 + +/** SPI_CLOCK_REG register + * SPI clock control register + */ +#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xc) +/** SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3; + * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be + * 0. Can be configured in CONF state. + */ +#define SPI_CLKCNT_L 0x0000003FU +#define SPI_CLKCNT_L_M (SPI_CLKCNT_L_V << SPI_CLKCNT_L_S) +#define SPI_CLKCNT_L_V 0x0000003FU +#define SPI_CLKCNT_L_S 0 +/** SPI_CLKCNT_H : R/W; bitpos: [11:6]; default: 1; + * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it + * must be 0. Can be configured in CONF state. + */ +#define SPI_CLKCNT_H 0x0000003FU +#define SPI_CLKCNT_H_M (SPI_CLKCNT_H_V << SPI_CLKCNT_H_S) +#define SPI_CLKCNT_H_V 0x0000003FU +#define SPI_CLKCNT_H_S 6 +/** SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3; + * In the master mode it is the divider of spi_clk. So spi_clk frequency is + * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + */ +#define SPI_CLKCNT_N 0x0000003FU +#define SPI_CLKCNT_N_M (SPI_CLKCNT_N_V << SPI_CLKCNT_N_S) +#define SPI_CLKCNT_N_V 0x0000003FU +#define SPI_CLKCNT_N_S 12 +/** SPI_CLKDIV_PRE : R/W; bitpos: [21:18]; default: 0; + * In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + */ +#define SPI_CLKDIV_PRE 0x0000000FU +#define SPI_CLKDIV_PRE_M (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S) +#define SPI_CLKDIV_PRE_V 0x0000000FU +#define SPI_CLKDIV_PRE_S 18 +/** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1; + * In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system + * clock. Can be configured in CONF state. + */ +#define SPI_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_M (SPI_CLK_EQU_SYSCLK_V << SPI_CLK_EQU_SYSCLK_S) +#define SPI_CLK_EQU_SYSCLK_V 0x00000001U +#define SPI_CLK_EQU_SYSCLK_S 31 + +/** SPI_USER_REG register + * SPI USER control register + */ +#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10) +/** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0; + * Set the bit to enable full duplex communication. 1: enable 0: disable. Can be + * configured in CONF state. + */ +#define SPI_DOUTDIN (BIT(0)) +#define SPI_DOUTDIN_M (SPI_DOUTDIN_V << SPI_DOUTDIN_S) +#define SPI_DOUTDIN_V 0x00000001U +#define SPI_DOUTDIN_S 0 +/** SPI_QPI_MODE : R/W/SS/SC; bitpos: [3]; default: 0; + * Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. + * Can be configured in CONF state. + */ +#define SPI_QPI_MODE (BIT(3)) +#define SPI_QPI_MODE_M (SPI_QPI_MODE_V << SPI_QPI_MODE_S) +#define SPI_QPI_MODE_V 0x00000001U +#define SPI_QPI_MODE_S 3 +/** SPI_OPI_MODE : HRO; bitpos: [4]; default: 0; + * Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. + * Can be configured in CONF state. + */ +#define SPI_OPI_MODE (BIT(4)) +#define SPI_OPI_MODE_M (SPI_OPI_MODE_V << SPI_OPI_MODE_S) +#define SPI_OPI_MODE_V 0x00000001U +#define SPI_OPI_MODE_S 4 +/** SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0; + * In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = + * spi_ck_i. 1:tsck = !spi_ck_i. + */ +#define SPI_TSCK_I_EDGE (BIT(5)) +#define SPI_TSCK_I_EDGE_M (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S) +#define SPI_TSCK_I_EDGE_V 0x00000001U +#define SPI_TSCK_I_EDGE_S 5 +/** SPI_CS_HOLD : R/W; bitpos: [6]; default: 1; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ +#define SPI_CS_HOLD (BIT(6)) +#define SPI_CS_HOLD_M (SPI_CS_HOLD_V << SPI_CS_HOLD_S) +#define SPI_CS_HOLD_V 0x00000001U +#define SPI_CS_HOLD_S 6 +/** SPI_CS_SETUP : R/W; bitpos: [7]; default: 1; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ +#define SPI_CS_SETUP (BIT(7)) +#define SPI_CS_SETUP_M (SPI_CS_SETUP_V << SPI_CS_SETUP_S) +#define SPI_CS_SETUP_V 0x00000001U +#define SPI_CS_SETUP_S 7 +/** SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0; + * In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = + * !spi_ck_i. 1:rsck = spi_ck_i. + */ +#define SPI_RSCK_I_EDGE (BIT(8)) +#define SPI_RSCK_I_EDGE_M (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S) +#define SPI_RSCK_I_EDGE_V 0x00000001U +#define SPI_RSCK_I_EDGE_S 8 +/** SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can + * be configured in CONF state. + */ +#define SPI_CK_OUT_EDGE (BIT(9)) +#define SPI_CK_OUT_EDGE_M (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S) +#define SPI_CK_OUT_EDGE_V 0x00000001U +#define SPI_CK_OUT_EDGE_S 9 +/** SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals. Can be configured in CONF + * state. + */ +#define SPI_FWRITE_DUAL (BIT(12)) +#define SPI_FWRITE_DUAL_M (SPI_FWRITE_DUAL_V << SPI_FWRITE_DUAL_S) +#define SPI_FWRITE_DUAL_V 0x00000001U +#define SPI_FWRITE_DUAL_S 12 +/** SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals. Can be configured in CONF + * state. + */ +#define SPI_FWRITE_QUAD (BIT(13)) +#define SPI_FWRITE_QUAD_M (SPI_FWRITE_QUAD_V << SPI_FWRITE_QUAD_S) +#define SPI_FWRITE_QUAD_V 0x00000001U +#define SPI_FWRITE_QUAD_S 13 +/** SPI_FWRITE_OCT : HRO; bitpos: [14]; default: 0; + * In the write operations read-data phase apply 8 signals. Can be configured in CONF + * state. + */ +#define SPI_FWRITE_OCT (BIT(14)) +#define SPI_FWRITE_OCT_M (SPI_FWRITE_OCT_V << SPI_FWRITE_OCT_S) +#define SPI_FWRITE_OCT_V 0x00000001U +#define SPI_FWRITE_OCT_S 14 +/** SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0; + * 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans + * will continue. 0: The seg-trans will end after the current SPI seg-trans or this is + * not seg-trans mode. Can be configured in CONF state. + */ +#define SPI_USR_CONF_NXT (BIT(15)) +#define SPI_USR_CONF_NXT_M (SPI_USR_CONF_NXT_V << SPI_USR_CONF_NXT_S) +#define SPI_USR_CONF_NXT_V 0x00000001U +#define SPI_USR_CONF_NXT_S 15 +/** SPI_SIO : R/W; bitpos: [17]; default: 0; + * Set the bit to enable 3-line half duplex communication mosi and miso signals share + * the same pin. 1: enable 0: disable. Can be configured in CONF state. + */ +#define SPI_SIO (BIT(17)) +#define SPI_SIO_M (SPI_SIO_V << SPI_SIO_S) +#define SPI_SIO_V 0x00000001U +#define SPI_SIO_S 17 +/** SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: + * disable. Can be configured in CONF state. + */ +#define SPI_USR_MISO_HIGHPART (BIT(24)) +#define SPI_USR_MISO_HIGHPART_M (SPI_USR_MISO_HIGHPART_V << SPI_USR_MISO_HIGHPART_S) +#define SPI_USR_MISO_HIGHPART_V 0x00000001U +#define SPI_USR_MISO_HIGHPART_S 24 +/** SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable + * 0: disable. Can be configured in CONF state. + */ +#define SPI_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_M (SPI_USR_MOSI_HIGHPART_V << SPI_USR_MOSI_HIGHPART_S) +#define SPI_USR_MOSI_HIGHPART_V 0x00000001U +#define SPI_USR_MOSI_HIGHPART_S 25 +/** SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. Can be configured in + * CONF state. + */ +#define SPI_USR_DUMMY_IDLE (BIT(26)) +#define SPI_USR_DUMMY_IDLE_M (SPI_USR_DUMMY_IDLE_V << SPI_USR_DUMMY_IDLE_S) +#define SPI_USR_DUMMY_IDLE_V 0x00000001U +#define SPI_USR_DUMMY_IDLE_S 26 +/** SPI_USR_MOSI : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. Can be configured in CONF + * state. + */ +#define SPI_USR_MOSI (BIT(27)) +#define SPI_USR_MOSI_M (SPI_USR_MOSI_V << SPI_USR_MOSI_S) +#define SPI_USR_MOSI_V 0x00000001U +#define SPI_USR_MOSI_S 27 +/** SPI_USR_MISO : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. Can be configured in CONF + * state. + */ +#define SPI_USR_MISO (BIT(28)) +#define SPI_USR_MISO_M (SPI_USR_MISO_V << SPI_USR_MISO_S) +#define SPI_USR_MISO_V 0x00000001U +#define SPI_USR_MISO_S 28 +/** SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. Can be configured in CONF state. + */ +#define SPI_USR_DUMMY (BIT(29)) +#define SPI_USR_DUMMY_M (SPI_USR_DUMMY_V << SPI_USR_DUMMY_S) +#define SPI_USR_DUMMY_V 0x00000001U +#define SPI_USR_DUMMY_S 29 +/** SPI_USR_ADDR : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. Can be configured in CONF state. + */ +#define SPI_USR_ADDR (BIT(30)) +#define SPI_USR_ADDR_M (SPI_USR_ADDR_V << SPI_USR_ADDR_S) +#define SPI_USR_ADDR_V 0x00000001U +#define SPI_USR_ADDR_S 30 +/** SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. Can be configured in CONF state. + */ +#define SPI_USR_COMMAND (BIT(31)) +#define SPI_USR_COMMAND_M (SPI_USR_COMMAND_V << SPI_USR_COMMAND_S) +#define SPI_USR_COMMAND_V 0x00000001U +#define SPI_USR_COMMAND_S 31 + +/** SPI_USER1_REG register + * SPI USER control register 1 + */ +#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14) +/** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7; + * The length in spi_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). Can be configured in CONF state. + */ +#define SPI_USR_DUMMY_CYCLELEN 0x000000FFU +#define SPI_USR_DUMMY_CYCLELEN_M (SPI_USR_DUMMY_CYCLELEN_V << SPI_USR_DUMMY_CYCLELEN_S) +#define SPI_USR_DUMMY_CYCLELEN_V 0x000000FFU +#define SPI_USR_DUMMY_CYCLELEN_S 0 +/** SPI_MST_WFULL_ERR_END_EN : R/W; bitpos: [16]; default: 1; + * 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master + * FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in + * GP-SPI master FD/HD-mode. + */ +#define SPI_MST_WFULL_ERR_END_EN (BIT(16)) +#define SPI_MST_WFULL_ERR_END_EN_M (SPI_MST_WFULL_ERR_END_EN_V << SPI_MST_WFULL_ERR_END_EN_S) +#define SPI_MST_WFULL_ERR_END_EN_V 0x00000001U +#define SPI_MST_WFULL_ERR_END_EN_S 16 +/** SPI_CS_SETUP_TIME : R/W; bitpos: [21:17]; default: 0; + * (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup + * bit. Can be configured in CONF state. + */ +#define SPI_CS_SETUP_TIME 0x0000001FU +#define SPI_CS_SETUP_TIME_M (SPI_CS_SETUP_TIME_V << SPI_CS_SETUP_TIME_S) +#define SPI_CS_SETUP_TIME_V 0x0000001FU +#define SPI_CS_SETUP_TIME_S 17 +/** SPI_CS_HOLD_TIME : R/W; bitpos: [26:22]; default: 1; + * delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. + * Can be configured in CONF state. + */ +#define SPI_CS_HOLD_TIME 0x0000001FU +#define SPI_CS_HOLD_TIME_M (SPI_CS_HOLD_TIME_V << SPI_CS_HOLD_TIME_S) +#define SPI_CS_HOLD_TIME_V 0x0000001FU +#define SPI_CS_HOLD_TIME_S 22 +/** SPI_USR_ADDR_BITLEN : R/W; bitpos: [31:27]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ +#define SPI_USR_ADDR_BITLEN 0x0000001FU +#define SPI_USR_ADDR_BITLEN_M (SPI_USR_ADDR_BITLEN_V << SPI_USR_ADDR_BITLEN_S) +#define SPI_USR_ADDR_BITLEN_V 0x0000001FU +#define SPI_USR_ADDR_BITLEN_S 27 + +/** SPI_USER2_REG register + * SPI USER control register 2 + */ +#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x18) +/** SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; + * The value of command. Can be configured in CONF state. + */ +#define SPI_USR_COMMAND_VALUE 0x0000FFFFU +#define SPI_USR_COMMAND_VALUE_M (SPI_USR_COMMAND_VALUE_V << SPI_USR_COMMAND_VALUE_S) +#define SPI_USR_COMMAND_VALUE_V 0x0000FFFFU +#define SPI_USR_COMMAND_VALUE_S 0 +/** SPI_MST_REMPTY_ERR_END_EN : R/W; bitpos: [27]; default: 1; + * 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI + * master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error + * is valid in GP-SPI master FD/HD-mode. + */ +#define SPI_MST_REMPTY_ERR_END_EN (BIT(27)) +#define SPI_MST_REMPTY_ERR_END_EN_M (SPI_MST_REMPTY_ERR_END_EN_V << SPI_MST_REMPTY_ERR_END_EN_S) +#define SPI_MST_REMPTY_ERR_END_EN_V 0x00000001U +#define SPI_MST_REMPTY_ERR_END_EN_S 27 +/** SPI_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ +#define SPI_USR_COMMAND_BITLEN 0x0000000FU +#define SPI_USR_COMMAND_BITLEN_M (SPI_USR_COMMAND_BITLEN_V << SPI_USR_COMMAND_BITLEN_S) +#define SPI_USR_COMMAND_BITLEN_V 0x0000000FU +#define SPI_USR_COMMAND_BITLEN_S 28 + +/** SPI_MS_DLEN_REG register + * SPI data bit length control register + */ +#define SPI_MS_DLEN_REG(i) (REG_SPI_BASE(i) + 0x1c) +/** SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0; + * The value of these bits is the configured SPI transmission data bit length in + * master mode DMA controlled transfer or CPU controlled transfer. The value is also + * the configured bit length in slave mode DMA RX controlled transfer. The register + * value shall be (bit_num-1). Can be configured in CONF state. + */ +#define SPI_MS_DATA_BITLEN 0x0003FFFFU +#define SPI_MS_DATA_BITLEN_M (SPI_MS_DATA_BITLEN_V << SPI_MS_DATA_BITLEN_S) +#define SPI_MS_DATA_BITLEN_V 0x0003FFFFU +#define SPI_MS_DATA_BITLEN_S 0 + +/** SPI_MISC_REG register + * SPI misc register + */ +#define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20) +/** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS0_DIS (BIT(0)) +#define SPI_CS0_DIS_M (SPI_CS0_DIS_V << SPI_CS0_DIS_S) +#define SPI_CS0_DIS_V 0x00000001U +#define SPI_CS0_DIS_S 0 +/** SPI_CS1_DIS : R/W; bitpos: [1]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS1_DIS (BIT(1)) +#define SPI_CS1_DIS_M (SPI_CS1_DIS_V << SPI_CS1_DIS_S) +#define SPI_CS1_DIS_V 0x00000001U +#define SPI_CS1_DIS_S 1 +/** SPI_CS2_DIS : R/W; bitpos: [2]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS2_DIS (BIT(2)) +#define SPI_CS2_DIS_M (SPI_CS2_DIS_V << SPI_CS2_DIS_S) +#define SPI_CS2_DIS_V 0x00000001U +#define SPI_CS2_DIS_S 2 +/** SPI_CS3_DIS : R/W; bitpos: [3]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS3_DIS (BIT(3)) +#define SPI_CS3_DIS_M (SPI_CS3_DIS_V << SPI_CS3_DIS_S) +#define SPI_CS3_DIS_V 0x00000001U +#define SPI_CS3_DIS_S 3 +/** SPI_CS4_DIS : R/W; bitpos: [4]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS4_DIS (BIT(4)) +#define SPI_CS4_DIS_M (SPI_CS4_DIS_V << SPI_CS4_DIS_S) +#define SPI_CS4_DIS_V 0x00000001U +#define SPI_CS4_DIS_S 4 +/** SPI_CS5_DIS : R/W; bitpos: [5]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS5_DIS (BIT(5)) +#define SPI_CS5_DIS_M (SPI_CS5_DIS_V << SPI_CS5_DIS_S) +#define SPI_CS5_DIS_V 0x00000001U +#define SPI_CS5_DIS_S 5 +/** SPI_CK_DIS : R/W; bitpos: [6]; default: 0; + * 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + */ +#define SPI_CK_DIS (BIT(6)) +#define SPI_CK_DIS_M (SPI_CK_DIS_V << SPI_CK_DIS_S) +#define SPI_CK_DIS_V 0x00000001U +#define SPI_CK_DIS_S 6 +/** SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0; + * In the master mode the bits are the polarity of spi cs line, the value is + * equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + */ +#define SPI_MASTER_CS_POL 0x0000003FU +#define SPI_MASTER_CS_POL_M (SPI_MASTER_CS_POL_V << SPI_MASTER_CS_POL_S) +#define SPI_MASTER_CS_POL_V 0x0000003FU +#define SPI_MASTER_CS_POL_S 7 +/** SPI_CLK_DATA_DTR_EN : HRO; bitpos: [16]; default: 0; + * 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR + * mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + */ +#define SPI_CLK_DATA_DTR_EN (BIT(16)) +#define SPI_CLK_DATA_DTR_EN_M (SPI_CLK_DATA_DTR_EN_V << SPI_CLK_DATA_DTR_EN_S) +#define SPI_CLK_DATA_DTR_EN_V 0x00000001U +#define SPI_CLK_DATA_DTR_EN_S 16 +/** SPI_DATA_DTR_EN : HRO; bitpos: [17]; default: 0; + * 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. + * Can be configured in CONF state. + */ +#define SPI_DATA_DTR_EN (BIT(17)) +#define SPI_DATA_DTR_EN_M (SPI_DATA_DTR_EN_V << SPI_DATA_DTR_EN_S) +#define SPI_DATA_DTR_EN_V 0x00000001U +#define SPI_DATA_DTR_EN_S 17 +/** SPI_ADDR_DTR_EN : HRO; bitpos: [18]; default: 0; + * 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be + * configured in CONF state. + */ +#define SPI_ADDR_DTR_EN (BIT(18)) +#define SPI_ADDR_DTR_EN_M (SPI_ADDR_DTR_EN_V << SPI_ADDR_DTR_EN_S) +#define SPI_ADDR_DTR_EN_V 0x00000001U +#define SPI_ADDR_DTR_EN_S 18 +/** SPI_CMD_DTR_EN : HRO; bitpos: [19]; default: 0; + * 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be + * configured in CONF state. + */ +#define SPI_CMD_DTR_EN (BIT(19)) +#define SPI_CMD_DTR_EN_M (SPI_CMD_DTR_EN_V << SPI_CMD_DTR_EN_S) +#define SPI_CMD_DTR_EN_V 0x00000001U +#define SPI_CMD_DTR_EN_S 19 +/** SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0; + * spi slave input cs polarity select. 1: inv 0: not change. Can be configured in + * CONF state. + */ +#define SPI_SLAVE_CS_POL (BIT(23)) +#define SPI_SLAVE_CS_POL_M (SPI_SLAVE_CS_POL_V << SPI_SLAVE_CS_POL_S) +#define SPI_SLAVE_CS_POL_V 0x00000001U +#define SPI_SLAVE_CS_POL_S 23 +/** SPI_DQS_IDLE_EDGE : HRO; bitpos: [24]; default: 0; + * The default value of spi_dqs. Can be configured in CONF state. + */ +#define SPI_DQS_IDLE_EDGE (BIT(24)) +#define SPI_DQS_IDLE_EDGE_M (SPI_DQS_IDLE_EDGE_V << SPI_DQS_IDLE_EDGE_S) +#define SPI_DQS_IDLE_EDGE_V 0x00000001U +#define SPI_DQS_IDLE_EDGE_S 24 +/** SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be + * configured in CONF state. + */ +#define SPI_CK_IDLE_EDGE (BIT(29)) +#define SPI_CK_IDLE_EDGE_M (SPI_CK_IDLE_EDGE_V << SPI_CK_IDLE_EDGE_S) +#define SPI_CK_IDLE_EDGE_V 0x00000001U +#define SPI_CK_IDLE_EDGE_S 29 +/** SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0; + * spi cs line keep low when the bit is set. Can be configured in CONF state. + */ +#define SPI_CS_KEEP_ACTIVE (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_M (SPI_CS_KEEP_ACTIVE_V << SPI_CS_KEEP_ACTIVE_S) +#define SPI_CS_KEEP_ACTIVE_V 0x00000001U +#define SPI_CS_KEEP_ACTIVE_S 30 +/** SPI_QUAD_DIN_PIN_SWAP : R/W; bitpos: [31]; default: 0; + * 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: + * spi quad input swap disable. Can be configured in CONF state. + */ +#define SPI_QUAD_DIN_PIN_SWAP (BIT(31)) +#define SPI_QUAD_DIN_PIN_SWAP_M (SPI_QUAD_DIN_PIN_SWAP_V << SPI_QUAD_DIN_PIN_SWAP_S) +#define SPI_QUAD_DIN_PIN_SWAP_V 0x00000001U +#define SPI_QUAD_DIN_PIN_SWAP_S 31 + +/** SPI_DIN_MODE_REG register + * SPI input delay mode configuration + */ +#define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24) +/** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN0_MODE 0x00000003U +#define SPI_DIN0_MODE_M (SPI_DIN0_MODE_V << SPI_DIN0_MODE_S) +#define SPI_DIN0_MODE_V 0x00000003U +#define SPI_DIN0_MODE_S 0 +/** SPI_DIN1_MODE : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN1_MODE 0x00000003U +#define SPI_DIN1_MODE_M (SPI_DIN1_MODE_V << SPI_DIN1_MODE_S) +#define SPI_DIN1_MODE_V 0x00000003U +#define SPI_DIN1_MODE_S 2 +/** SPI_DIN2_MODE : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN2_MODE 0x00000003U +#define SPI_DIN2_MODE_M (SPI_DIN2_MODE_V << SPI_DIN2_MODE_S) +#define SPI_DIN2_MODE_V 0x00000003U +#define SPI_DIN2_MODE_S 4 +/** SPI_DIN3_MODE : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN3_MODE 0x00000003U +#define SPI_DIN3_MODE_M (SPI_DIN3_MODE_V << SPI_DIN3_MODE_S) +#define SPI_DIN3_MODE_V 0x00000003U +#define SPI_DIN3_MODE_S 6 +/** SPI_DIN4_MODE : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN4_MODE 0x00000003U +#define SPI_DIN4_MODE_M (SPI_DIN4_MODE_V << SPI_DIN4_MODE_S) +#define SPI_DIN4_MODE_V 0x00000003U +#define SPI_DIN4_MODE_S 8 +/** SPI_DIN5_MODE : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN5_MODE 0x00000003U +#define SPI_DIN5_MODE_M (SPI_DIN5_MODE_V << SPI_DIN5_MODE_S) +#define SPI_DIN5_MODE_V 0x00000003U +#define SPI_DIN5_MODE_S 10 +/** SPI_DIN6_MODE : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN6_MODE 0x00000003U +#define SPI_DIN6_MODE_M (SPI_DIN6_MODE_V << SPI_DIN6_MODE_S) +#define SPI_DIN6_MODE_V 0x00000003U +#define SPI_DIN6_MODE_S 12 +/** SPI_DIN7_MODE : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN7_MODE 0x00000003U +#define SPI_DIN7_MODE_M (SPI_DIN7_MODE_V << SPI_DIN7_MODE_S) +#define SPI_DIN7_MODE_V 0x00000003U +#define SPI_DIN7_MODE_S 14 +/** SPI_TIMING_HCLK_ACTIVE : R/W; bitpos: [16]; default: 0; + * 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF + * state. + */ +#define SPI_TIMING_HCLK_ACTIVE (BIT(16)) +#define SPI_TIMING_HCLK_ACTIVE_M (SPI_TIMING_HCLK_ACTIVE_V << SPI_TIMING_HCLK_ACTIVE_S) +#define SPI_TIMING_HCLK_ACTIVE_V 0x00000001U +#define SPI_TIMING_HCLK_ACTIVE_S 16 + +/** SPI_DIN_NUM_REG register + * SPI input delay number configuration + */ +#define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x28) +/** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN0_NUM 0x00000003U +#define SPI_DIN0_NUM_M (SPI_DIN0_NUM_V << SPI_DIN0_NUM_S) +#define SPI_DIN0_NUM_V 0x00000003U +#define SPI_DIN0_NUM_S 0 +/** SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN1_NUM 0x00000003U +#define SPI_DIN1_NUM_M (SPI_DIN1_NUM_V << SPI_DIN1_NUM_S) +#define SPI_DIN1_NUM_V 0x00000003U +#define SPI_DIN1_NUM_S 2 +/** SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN2_NUM 0x00000003U +#define SPI_DIN2_NUM_M (SPI_DIN2_NUM_V << SPI_DIN2_NUM_S) +#define SPI_DIN2_NUM_V 0x00000003U +#define SPI_DIN2_NUM_S 4 +/** SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN3_NUM 0x00000003U +#define SPI_DIN3_NUM_M (SPI_DIN3_NUM_V << SPI_DIN3_NUM_S) +#define SPI_DIN3_NUM_V 0x00000003U +#define SPI_DIN3_NUM_S 6 +/** SPI_DIN4_NUM : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN4_NUM 0x00000003U +#define SPI_DIN4_NUM_M (SPI_DIN4_NUM_V << SPI_DIN4_NUM_S) +#define SPI_DIN4_NUM_V 0x00000003U +#define SPI_DIN4_NUM_S 8 +/** SPI_DIN5_NUM : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN5_NUM 0x00000003U +#define SPI_DIN5_NUM_M (SPI_DIN5_NUM_V << SPI_DIN5_NUM_S) +#define SPI_DIN5_NUM_V 0x00000003U +#define SPI_DIN5_NUM_S 10 +/** SPI_DIN6_NUM : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN6_NUM 0x00000003U +#define SPI_DIN6_NUM_M (SPI_DIN6_NUM_V << SPI_DIN6_NUM_S) +#define SPI_DIN6_NUM_V 0x00000003U +#define SPI_DIN6_NUM_S 12 +/** SPI_DIN7_NUM : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN7_NUM 0x00000003U +#define SPI_DIN7_NUM_M (SPI_DIN7_NUM_V << SPI_DIN7_NUM_S) +#define SPI_DIN7_NUM_V 0x00000003U +#define SPI_DIN7_NUM_S 14 + +/** SPI_DOUT_MODE_REG register + * SPI output delay mode configuration + */ +#define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x2c) +/** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT0_MODE (BIT(0)) +#define SPI_DOUT0_MODE_M (SPI_DOUT0_MODE_V << SPI_DOUT0_MODE_S) +#define SPI_DOUT0_MODE_V 0x00000001U +#define SPI_DOUT0_MODE_S 0 +/** SPI_DOUT1_MODE : R/W; bitpos: [1]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT1_MODE (BIT(1)) +#define SPI_DOUT1_MODE_M (SPI_DOUT1_MODE_V << SPI_DOUT1_MODE_S) +#define SPI_DOUT1_MODE_V 0x00000001U +#define SPI_DOUT1_MODE_S 1 +/** SPI_DOUT2_MODE : R/W; bitpos: [2]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT2_MODE (BIT(2)) +#define SPI_DOUT2_MODE_M (SPI_DOUT2_MODE_V << SPI_DOUT2_MODE_S) +#define SPI_DOUT2_MODE_V 0x00000001U +#define SPI_DOUT2_MODE_S 2 +/** SPI_DOUT3_MODE : R/W; bitpos: [3]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT3_MODE (BIT(3)) +#define SPI_DOUT3_MODE_M (SPI_DOUT3_MODE_V << SPI_DOUT3_MODE_S) +#define SPI_DOUT3_MODE_V 0x00000001U +#define SPI_DOUT3_MODE_S 3 +/** SPI_DOUT4_MODE : HRO; bitpos: [4]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT4_MODE (BIT(4)) +#define SPI_DOUT4_MODE_M (SPI_DOUT4_MODE_V << SPI_DOUT4_MODE_S) +#define SPI_DOUT4_MODE_V 0x00000001U +#define SPI_DOUT4_MODE_S 4 +/** SPI_DOUT5_MODE : HRO; bitpos: [5]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT5_MODE (BIT(5)) +#define SPI_DOUT5_MODE_M (SPI_DOUT5_MODE_V << SPI_DOUT5_MODE_S) +#define SPI_DOUT5_MODE_V 0x00000001U +#define SPI_DOUT5_MODE_S 5 +/** SPI_DOUT6_MODE : HRO; bitpos: [6]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT6_MODE (BIT(6)) +#define SPI_DOUT6_MODE_M (SPI_DOUT6_MODE_V << SPI_DOUT6_MODE_S) +#define SPI_DOUT6_MODE_V 0x00000001U +#define SPI_DOUT6_MODE_S 6 +/** SPI_DOUT7_MODE : HRO; bitpos: [7]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT7_MODE (BIT(7)) +#define SPI_DOUT7_MODE_M (SPI_DOUT7_MODE_V << SPI_DOUT7_MODE_S) +#define SPI_DOUT7_MODE_V 0x00000001U +#define SPI_DOUT7_MODE_S 7 +/** SPI_D_DQS_MODE : HRO; bitpos: [8]; default: 0; + * The output signal SPI_DQS is delayed by the SPI module clock, 0: output without + * delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_D_DQS_MODE (BIT(8)) +#define SPI_D_DQS_MODE_M (SPI_D_DQS_MODE_V << SPI_D_DQS_MODE_S) +#define SPI_D_DQS_MODE_V 0x00000001U +#define SPI_D_DQS_MODE_S 8 + +/** SPI_DMA_CONF_REG register + * SPI DMA control register + */ +#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x30) +/** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1; + * Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: + * DMA TX FIFO is ready for sending data. + */ +#define SPI_DMA_OUTFIFO_EMPTY (BIT(0)) +#define SPI_DMA_OUTFIFO_EMPTY_M (SPI_DMA_OUTFIFO_EMPTY_V << SPI_DMA_OUTFIFO_EMPTY_S) +#define SPI_DMA_OUTFIFO_EMPTY_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_S 0 +/** SPI_DMA_INFIFO_FULL : RO; bitpos: [1]; default: 1; + * Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. + * 0: DMA RX FIFO is ready for receiving data. + */ +#define SPI_DMA_INFIFO_FULL (BIT(1)) +#define SPI_DMA_INFIFO_FULL_M (SPI_DMA_INFIFO_FULL_V << SPI_DMA_INFIFO_FULL_S) +#define SPI_DMA_INFIFO_FULL_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_S 1 +/** SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0; + * Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + */ +#define SPI_DMA_SLV_SEG_TRANS_EN (BIT(18)) +#define SPI_DMA_SLV_SEG_TRANS_EN_M (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S) +#define SPI_DMA_SLV_SEG_TRANS_EN_V 0x00000001U +#define SPI_DMA_SLV_SEG_TRANS_EN_S 18 +/** SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0; + * 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: + * spi_dma_infifo_full_vld is cleared by spi_trans_done. + */ +#define SPI_SLV_RX_SEG_TRANS_CLR_EN (BIT(19)) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M (SPI_SLV_RX_SEG_TRANS_CLR_EN_V << SPI_SLV_RX_SEG_TRANS_CLR_EN_S) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V 0x00000001U +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S 19 +/** SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0; + * 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: + * spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + */ +#define SPI_SLV_TX_SEG_TRANS_CLR_EN (BIT(20)) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M (SPI_SLV_TX_SEG_TRANS_CLR_EN_V << SPI_SLV_TX_SEG_TRANS_CLR_EN_S) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V 0x00000001U +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S 20 +/** SPI_RX_EOF_EN : R/W; bitpos: [21]; default: 0; + * 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to + * the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: + * spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or + * spi_dma_seg_trans_done in seg-trans. + */ +#define SPI_RX_EOF_EN (BIT(21)) +#define SPI_RX_EOF_EN_M (SPI_RX_EOF_EN_V << SPI_RX_EOF_EN_S) +#define SPI_RX_EOF_EN_V 0x00000001U +#define SPI_RX_EOF_EN_S 21 +/** SPI_DMA_RX_ENA : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI DMA controlled receive data mode. + */ +#define SPI_DMA_RX_ENA (BIT(27)) +#define SPI_DMA_RX_ENA_M (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S) +#define SPI_DMA_RX_ENA_V 0x00000001U +#define SPI_DMA_RX_ENA_S 27 +/** SPI_DMA_TX_ENA : R/W; bitpos: [28]; default: 0; + * Set this bit to enable SPI DMA controlled send data mode. + */ +#define SPI_DMA_TX_ENA (BIT(28)) +#define SPI_DMA_TX_ENA_M (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S) +#define SPI_DMA_TX_ENA_V 0x00000001U +#define SPI_DMA_TX_ENA_S 28 +/** SPI_RX_AFIFO_RST : WT; bitpos: [29]; default: 0; + * Set this bit to reset RX AFIFO, which is used to receive data in SPI master and + * slave mode transfer. + */ +#define SPI_RX_AFIFO_RST (BIT(29)) +#define SPI_RX_AFIFO_RST_M (SPI_RX_AFIFO_RST_V << SPI_RX_AFIFO_RST_S) +#define SPI_RX_AFIFO_RST_V 0x00000001U +#define SPI_RX_AFIFO_RST_S 29 +/** SPI_BUF_AFIFO_RST : WT; bitpos: [30]; default: 0; + * Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU + * controlled mode transfer and master mode transfer. + */ +#define SPI_BUF_AFIFO_RST (BIT(30)) +#define SPI_BUF_AFIFO_RST_M (SPI_BUF_AFIFO_RST_V << SPI_BUF_AFIFO_RST_S) +#define SPI_BUF_AFIFO_RST_V 0x00000001U +#define SPI_BUF_AFIFO_RST_S 30 +/** SPI_DMA_AFIFO_RST : WT; bitpos: [31]; default: 0; + * Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA + * controlled mode transfer. + */ +#define SPI_DMA_AFIFO_RST (BIT(31)) +#define SPI_DMA_AFIFO_RST_M (SPI_DMA_AFIFO_RST_V << SPI_DMA_AFIFO_RST_S) +#define SPI_DMA_AFIFO_RST_V 0x00000001U +#define SPI_DMA_AFIFO_RST_S 31 + +/** SPI_DMA_INT_ENA_REG register + * SPI interrupt enable register + */ +#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x34) +/** SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M (SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V << SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S 1 +/** SPI_SLV_EX_QPI_INT_ENA : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI slave Ex_QPI interrupt. + */ +#define SPI_SLV_EX_QPI_INT_ENA (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ENA_M (SPI_SLV_EX_QPI_INT_ENA_V << SPI_SLV_EX_QPI_INT_ENA_S) +#define SPI_SLV_EX_QPI_INT_ENA_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_ENA_S 2 +/** SPI_SLV_EN_QPI_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI slave En_QPI interrupt. + */ +#define SPI_SLV_EN_QPI_INT_ENA (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ENA_M (SPI_SLV_EN_QPI_INT_ENA_V << SPI_SLV_EN_QPI_INT_ENA_S) +#define SPI_SLV_EN_QPI_INT_ENA_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_ENA_S 3 +/** SPI_SLV_CMD7_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI slave CMD7 interrupt. + */ +#define SPI_SLV_CMD7_INT_ENA (BIT(4)) +#define SPI_SLV_CMD7_INT_ENA_M (SPI_SLV_CMD7_INT_ENA_V << SPI_SLV_CMD7_INT_ENA_S) +#define SPI_SLV_CMD7_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD7_INT_ENA_S 4 +/** SPI_SLV_CMD8_INT_ENA : R/W; bitpos: [5]; default: 0; + * The enable bit for SPI slave CMD8 interrupt. + */ +#define SPI_SLV_CMD8_INT_ENA (BIT(5)) +#define SPI_SLV_CMD8_INT_ENA_M (SPI_SLV_CMD8_INT_ENA_V << SPI_SLV_CMD8_INT_ENA_S) +#define SPI_SLV_CMD8_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD8_INT_ENA_S 5 +/** SPI_SLV_CMD9_INT_ENA : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI slave CMD9 interrupt. + */ +#define SPI_SLV_CMD9_INT_ENA (BIT(6)) +#define SPI_SLV_CMD9_INT_ENA_M (SPI_SLV_CMD9_INT_ENA_V << SPI_SLV_CMD9_INT_ENA_S) +#define SPI_SLV_CMD9_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD9_INT_ENA_S 6 +/** SPI_SLV_CMDA_INT_ENA : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI slave CMDA interrupt. + */ +#define SPI_SLV_CMDA_INT_ENA (BIT(7)) +#define SPI_SLV_CMDA_INT_ENA_M (SPI_SLV_CMDA_INT_ENA_V << SPI_SLV_CMDA_INT_ENA_S) +#define SPI_SLV_CMDA_INT_ENA_V 0x00000001U +#define SPI_SLV_CMDA_INT_ENA_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_ENA : R/W; bitpos: [8]; default: 0; + * The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_ENA (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ENA_M (SPI_SLV_RD_DMA_DONE_INT_ENA_V << SPI_SLV_RD_DMA_DONE_INT_ENA_S) +#define SPI_SLV_RD_DMA_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_ENA_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_ENA : R/W; bitpos: [9]; default: 0; + * The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_ENA (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ENA_M (SPI_SLV_WR_DMA_DONE_INT_ENA_V << SPI_SLV_WR_DMA_DONE_INT_ENA_S) +#define SPI_SLV_WR_DMA_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_ENA_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_ENA : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_ENA (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ENA_M (SPI_SLV_RD_BUF_DONE_INT_ENA_V << SPI_SLV_RD_BUF_DONE_INT_ENA_S) +#define SPI_SLV_RD_BUF_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_ENA_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_ENA : R/W; bitpos: [11]; default: 0; + * The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_ENA (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ENA_M (SPI_SLV_WR_BUF_DONE_INT_ENA_V << SPI_SLV_WR_BUF_DONE_INT_ENA_S) +#define SPI_SLV_WR_BUF_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_ENA_S 11 +/** SPI_TRANS_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; + * The enable bit for SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_ENA (BIT(12)) +#define SPI_TRANS_DONE_INT_ENA_M (SPI_TRANS_DONE_INT_ENA_V << SPI_TRANS_DONE_INT_ENA_S) +#define SPI_TRANS_DONE_INT_ENA_V 0x00000001U +#define SPI_TRANS_DONE_INT_ENA_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; + * The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M (SPI_DMA_SEG_TRANS_DONE_INT_ENA_V << SPI_DMA_SEG_TRANS_DONE_INT_ENA_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S 13 +/** SPI_SEG_MAGIC_ERR_INT_ENA : R/W; bitpos: [14]; default: 0; + * The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ +#define SPI_SEG_MAGIC_ERR_INT_ENA (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ENA_M (SPI_SEG_MAGIC_ERR_INT_ENA_V << SPI_SEG_MAGIC_ERR_INT_ENA_S) +#define SPI_SEG_MAGIC_ERR_INT_ENA_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_ENA_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W; bitpos: [15]; default: 0; + * The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M (SPI_SLV_BUF_ADDR_ERR_INT_ENA_V << SPI_SLV_BUF_ADDR_ERR_INT_ENA_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S 15 +/** SPI_SLV_CMD_ERR_INT_ENA : R/W; bitpos: [16]; default: 0; + * The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_ENA (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ENA_M (SPI_SLV_CMD_ERR_INT_ENA_V << SPI_SLV_CMD_ERR_INT_ENA_S) +#define SPI_SLV_CMD_ERR_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_ENA_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W; bitpos: [17]; default: 0; + * The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W; bitpos: [18]; default: 0; + * The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S 18 +/** SPI_APP2_INT_ENA : R/W; bitpos: [19]; default: 0; + * The enable bit for SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_ENA (BIT(19)) +#define SPI_APP2_INT_ENA_M (SPI_APP2_INT_ENA_V << SPI_APP2_INT_ENA_S) +#define SPI_APP2_INT_ENA_V 0x00000001U +#define SPI_APP2_INT_ENA_S 19 +/** SPI_APP1_INT_ENA : R/W; bitpos: [20]; default: 0; + * The enable bit for SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_ENA (BIT(20)) +#define SPI_APP1_INT_ENA_M (SPI_APP1_INT_ENA_V << SPI_APP1_INT_ENA_S) +#define SPI_APP1_INT_ENA_V 0x00000001U +#define SPI_APP1_INT_ENA_S 20 + +/** SPI_DMA_INT_CLR_REG register + * SPI interrupt clear register + */ +#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x38) +/** SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0; + * The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M (SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V << SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT; bitpos: [1]; default: 0; + * The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S 1 +/** SPI_SLV_EX_QPI_INT_CLR : WT; bitpos: [2]; default: 0; + * The clear bit for SPI slave Ex_QPI interrupt. + */ +#define SPI_SLV_EX_QPI_INT_CLR (BIT(2)) +#define SPI_SLV_EX_QPI_INT_CLR_M (SPI_SLV_EX_QPI_INT_CLR_V << SPI_SLV_EX_QPI_INT_CLR_S) +#define SPI_SLV_EX_QPI_INT_CLR_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_CLR_S 2 +/** SPI_SLV_EN_QPI_INT_CLR : WT; bitpos: [3]; default: 0; + * The clear bit for SPI slave En_QPI interrupt. + */ +#define SPI_SLV_EN_QPI_INT_CLR (BIT(3)) +#define SPI_SLV_EN_QPI_INT_CLR_M (SPI_SLV_EN_QPI_INT_CLR_V << SPI_SLV_EN_QPI_INT_CLR_S) +#define SPI_SLV_EN_QPI_INT_CLR_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_CLR_S 3 +/** SPI_SLV_CMD7_INT_CLR : WT; bitpos: [4]; default: 0; + * The clear bit for SPI slave CMD7 interrupt. + */ +#define SPI_SLV_CMD7_INT_CLR (BIT(4)) +#define SPI_SLV_CMD7_INT_CLR_M (SPI_SLV_CMD7_INT_CLR_V << SPI_SLV_CMD7_INT_CLR_S) +#define SPI_SLV_CMD7_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD7_INT_CLR_S 4 +/** SPI_SLV_CMD8_INT_CLR : WT; bitpos: [5]; default: 0; + * The clear bit for SPI slave CMD8 interrupt. + */ +#define SPI_SLV_CMD8_INT_CLR (BIT(5)) +#define SPI_SLV_CMD8_INT_CLR_M (SPI_SLV_CMD8_INT_CLR_V << SPI_SLV_CMD8_INT_CLR_S) +#define SPI_SLV_CMD8_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD8_INT_CLR_S 5 +/** SPI_SLV_CMD9_INT_CLR : WT; bitpos: [6]; default: 0; + * The clear bit for SPI slave CMD9 interrupt. + */ +#define SPI_SLV_CMD9_INT_CLR (BIT(6)) +#define SPI_SLV_CMD9_INT_CLR_M (SPI_SLV_CMD9_INT_CLR_V << SPI_SLV_CMD9_INT_CLR_S) +#define SPI_SLV_CMD9_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD9_INT_CLR_S 6 +/** SPI_SLV_CMDA_INT_CLR : WT; bitpos: [7]; default: 0; + * The clear bit for SPI slave CMDA interrupt. + */ +#define SPI_SLV_CMDA_INT_CLR (BIT(7)) +#define SPI_SLV_CMDA_INT_CLR_M (SPI_SLV_CMDA_INT_CLR_V << SPI_SLV_CMDA_INT_CLR_S) +#define SPI_SLV_CMDA_INT_CLR_V 0x00000001U +#define SPI_SLV_CMDA_INT_CLR_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_CLR : WT; bitpos: [8]; default: 0; + * The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_CLR (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_CLR_M (SPI_SLV_RD_DMA_DONE_INT_CLR_V << SPI_SLV_RD_DMA_DONE_INT_CLR_S) +#define SPI_SLV_RD_DMA_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_CLR_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_CLR : WT; bitpos: [9]; default: 0; + * The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_CLR (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_CLR_M (SPI_SLV_WR_DMA_DONE_INT_CLR_V << SPI_SLV_WR_DMA_DONE_INT_CLR_S) +#define SPI_SLV_WR_DMA_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_CLR_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_CLR : WT; bitpos: [10]; default: 0; + * The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_CLR (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_CLR_M (SPI_SLV_RD_BUF_DONE_INT_CLR_V << SPI_SLV_RD_BUF_DONE_INT_CLR_S) +#define SPI_SLV_RD_BUF_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_CLR_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_CLR : WT; bitpos: [11]; default: 0; + * The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_CLR (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_CLR_M (SPI_SLV_WR_BUF_DONE_INT_CLR_V << SPI_SLV_WR_BUF_DONE_INT_CLR_S) +#define SPI_SLV_WR_BUF_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_CLR_S 11 +/** SPI_TRANS_DONE_INT_CLR : WT; bitpos: [12]; default: 0; + * The clear bit for SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_CLR (BIT(12)) +#define SPI_TRANS_DONE_INT_CLR_M (SPI_TRANS_DONE_INT_CLR_V << SPI_TRANS_DONE_INT_CLR_S) +#define SPI_TRANS_DONE_INT_CLR_V 0x00000001U +#define SPI_TRANS_DONE_INT_CLR_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT; bitpos: [13]; default: 0; + * The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M (SPI_DMA_SEG_TRANS_DONE_INT_CLR_V << SPI_DMA_SEG_TRANS_DONE_INT_CLR_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S 13 +/** SPI_SEG_MAGIC_ERR_INT_CLR : WT; bitpos: [14]; default: 0; + * The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ +#define SPI_SEG_MAGIC_ERR_INT_CLR (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_CLR_M (SPI_SEG_MAGIC_ERR_INT_CLR_V << SPI_SEG_MAGIC_ERR_INT_CLR_S) +#define SPI_SEG_MAGIC_ERR_INT_CLR_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_CLR_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT; bitpos: [15]; default: 0; + * The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M (SPI_SLV_BUF_ADDR_ERR_INT_CLR_V << SPI_SLV_BUF_ADDR_ERR_INT_CLR_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S 15 +/** SPI_SLV_CMD_ERR_INT_CLR : WT; bitpos: [16]; default: 0; + * The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_CLR (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_CLR_M (SPI_SLV_CMD_ERR_INT_CLR_V << SPI_SLV_CMD_ERR_INT_CLR_S) +#define SPI_SLV_CMD_ERR_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_CLR_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT; bitpos: [17]; default: 0; + * The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT; bitpos: [18]; default: 0; + * The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S 18 +/** SPI_APP2_INT_CLR : WT; bitpos: [19]; default: 0; + * The clear bit for SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_CLR (BIT(19)) +#define SPI_APP2_INT_CLR_M (SPI_APP2_INT_CLR_V << SPI_APP2_INT_CLR_S) +#define SPI_APP2_INT_CLR_V 0x00000001U +#define SPI_APP2_INT_CLR_S 19 +/** SPI_APP1_INT_CLR : WT; bitpos: [20]; default: 0; + * The clear bit for SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_CLR (BIT(20)) +#define SPI_APP1_INT_CLR_M (SPI_APP1_INT_CLR_V << SPI_APP1_INT_CLR_S) +#define SPI_APP1_INT_CLR_V 0x00000001U +#define SPI_APP1_INT_CLR_S 20 + +/** SPI_DMA_INT_RAW_REG register + * SPI interrupt raw register + */ +#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x3c) +/** SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the + * receive data. 0: Others. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M (SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V << SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in + * master mode and send out all 0 in slave mode. 0: Others. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S 1 +/** SPI_SLV_EX_QPI_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission + * is ended. 0: Others. + */ +#define SPI_SLV_EX_QPI_INT_RAW (BIT(2)) +#define SPI_SLV_EX_QPI_INT_RAW_M (SPI_SLV_EX_QPI_INT_RAW_V << SPI_SLV_EX_QPI_INT_RAW_S) +#define SPI_SLV_EX_QPI_INT_RAW_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_RAW_S 2 +/** SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission + * is ended. 0: Others. + */ +#define SPI_SLV_EN_QPI_INT_RAW (BIT(3)) +#define SPI_SLV_EN_QPI_INT_RAW_M (SPI_SLV_EN_QPI_INT_RAW_V << SPI_SLV_EN_QPI_INT_RAW_S) +#define SPI_SLV_EN_QPI_INT_RAW_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_RAW_S 3 +/** SPI_SLV_CMD7_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is + * ended. 0: Others. + */ +#define SPI_SLV_CMD7_INT_RAW (BIT(4)) +#define SPI_SLV_CMD7_INT_RAW_M (SPI_SLV_CMD7_INT_RAW_V << SPI_SLV_CMD7_INT_RAW_S) +#define SPI_SLV_CMD7_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD7_INT_RAW_S 4 +/** SPI_SLV_CMD8_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is + * ended. 0: Others. + */ +#define SPI_SLV_CMD8_INT_RAW (BIT(5)) +#define SPI_SLV_CMD8_INT_RAW_M (SPI_SLV_CMD8_INT_RAW_V << SPI_SLV_CMD8_INT_RAW_S) +#define SPI_SLV_CMD8_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD8_INT_RAW_S 5 +/** SPI_SLV_CMD9_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is + * ended. 0: Others. + */ +#define SPI_SLV_CMD9_INT_RAW (BIT(6)) +#define SPI_SLV_CMD9_INT_RAW_M (SPI_SLV_CMD9_INT_RAW_V << SPI_SLV_CMD9_INT_RAW_S) +#define SPI_SLV_CMD9_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD9_INT_RAW_S 6 +/** SPI_SLV_CMDA_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is + * ended. 0: Others. + */ +#define SPI_SLV_CMDA_INT_RAW (BIT(7)) +#define SPI_SLV_CMDA_INT_RAW_M (SPI_SLV_CMDA_INT_RAW_V << SPI_SLV_CMDA_INT_RAW_S) +#define SPI_SLV_CMDA_INT_RAW_V 0x00000001U +#define SPI_SLV_CMDA_INT_RAW_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA + * transmission is ended. 0: Others. + */ +#define SPI_SLV_RD_DMA_DONE_INT_RAW (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_RAW_M (SPI_SLV_RD_DMA_DONE_INT_RAW_V << SPI_SLV_RD_DMA_DONE_INT_RAW_S) +#define SPI_SLV_RD_DMA_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_RAW_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA + * transmission is ended. 0: Others. + */ +#define SPI_SLV_WR_DMA_DONE_INT_RAW (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_RAW_M (SPI_SLV_WR_DMA_DONE_INT_RAW_V << SPI_SLV_WR_DMA_DONE_INT_RAW_S) +#define SPI_SLV_WR_DMA_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_RAW_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF + * transmission is ended. 0: Others. + */ +#define SPI_SLV_RD_BUF_DONE_INT_RAW (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_RAW_M (SPI_SLV_RD_BUF_DONE_INT_RAW_V << SPI_SLV_RD_BUF_DONE_INT_RAW_S) +#define SPI_SLV_RD_BUF_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_RAW_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF + * transmission is ended. 0: Others. + */ +#define SPI_SLV_WR_BUF_DONE_INT_RAW (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_RAW_M (SPI_SLV_WR_BUF_DONE_INT_RAW_V << SPI_SLV_WR_BUF_DONE_INT_RAW_S) +#define SPI_SLV_WR_BUF_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_RAW_S 11 +/** SPI_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is + * ended. 0: others. + */ +#define SPI_TRANS_DONE_INT_RAW (BIT(12)) +#define SPI_TRANS_DONE_INT_RAW_M (SPI_TRANS_DONE_INT_RAW_V << SPI_TRANS_DONE_INT_RAW_S) +#define SPI_TRANS_DONE_INT_RAW_V 0x00000001U +#define SPI_TRANS_DONE_INT_RAW_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA + * full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. + * And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans + * is not ended or not occurred. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M (SPI_DMA_SEG_TRANS_DONE_INT_RAW_V << SPI_DMA_SEG_TRANS_DONE_INT_RAW_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S 13 +/** SPI_SEG_MAGIC_ERR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer + * is error in the DMA seg-conf-trans. 0: others. + */ +#define SPI_SEG_MAGIC_ERR_INT_RAW (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_RAW_M (SPI_SEG_MAGIC_ERR_INT_RAW_V << SPI_SEG_MAGIC_ERR_INT_RAW_S) +#define SPI_SEG_MAGIC_ERR_INT_RAW_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_RAW_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address + * of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is + * bigger than 63. 0: Others. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M (SPI_SLV_BUF_ADDR_ERR_INT_RAW_V << SPI_SLV_BUF_ADDR_ERR_INT_RAW_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S 15 +/** SPI_SLV_CMD_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the + * current SPI slave HD mode transmission is not supported. 0: Others. + */ +#define SPI_SLV_CMD_ERR_INT_RAW (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_RAW_M (SPI_SLV_CMD_ERR_INT_RAW_V << SPI_SLV_CMD_ERR_INT_RAW_S) +#define SPI_SLV_CMD_ERR_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_RAW_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO + * write-full error when SPI inputs data in master mode. 0: Others. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF + * AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S 18 +/** SPI_APP2_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + */ +#define SPI_APP2_INT_RAW (BIT(19)) +#define SPI_APP2_INT_RAW_M (SPI_APP2_INT_RAW_V << SPI_APP2_INT_RAW_S) +#define SPI_APP2_INT_RAW_V 0x00000001U +#define SPI_APP2_INT_RAW_S 19 +/** SPI_APP1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + */ +#define SPI_APP1_INT_RAW (BIT(20)) +#define SPI_APP1_INT_RAW_M (SPI_APP1_INT_RAW_V << SPI_APP1_INT_RAW_S) +#define SPI_APP1_INT_RAW_V 0x00000001U +#define SPI_APP1_INT_RAW_S 20 + +/** SPI_DMA_INT_ST_REG register + * SPI interrupt status register + */ +#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x40) +/** SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0; + * The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M (SPI_DMA_INFIFO_FULL_ERR_INT_ST_V << SPI_DMA_INFIFO_FULL_ERR_INT_ST_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO; bitpos: [1]; default: 0; + * The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S 1 +/** SPI_SLV_EX_QPI_INT_ST : RO; bitpos: [2]; default: 0; + * The status bit for SPI slave Ex_QPI interrupt. + */ +#define SPI_SLV_EX_QPI_INT_ST (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ST_M (SPI_SLV_EX_QPI_INT_ST_V << SPI_SLV_EX_QPI_INT_ST_S) +#define SPI_SLV_EX_QPI_INT_ST_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_ST_S 2 +/** SPI_SLV_EN_QPI_INT_ST : RO; bitpos: [3]; default: 0; + * The status bit for SPI slave En_QPI interrupt. + */ +#define SPI_SLV_EN_QPI_INT_ST (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ST_M (SPI_SLV_EN_QPI_INT_ST_V << SPI_SLV_EN_QPI_INT_ST_S) +#define SPI_SLV_EN_QPI_INT_ST_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_ST_S 3 +/** SPI_SLV_CMD7_INT_ST : RO; bitpos: [4]; default: 0; + * The status bit for SPI slave CMD7 interrupt. + */ +#define SPI_SLV_CMD7_INT_ST (BIT(4)) +#define SPI_SLV_CMD7_INT_ST_M (SPI_SLV_CMD7_INT_ST_V << SPI_SLV_CMD7_INT_ST_S) +#define SPI_SLV_CMD7_INT_ST_V 0x00000001U +#define SPI_SLV_CMD7_INT_ST_S 4 +/** SPI_SLV_CMD8_INT_ST : RO; bitpos: [5]; default: 0; + * The status bit for SPI slave CMD8 interrupt. + */ +#define SPI_SLV_CMD8_INT_ST (BIT(5)) +#define SPI_SLV_CMD8_INT_ST_M (SPI_SLV_CMD8_INT_ST_V << SPI_SLV_CMD8_INT_ST_S) +#define SPI_SLV_CMD8_INT_ST_V 0x00000001U +#define SPI_SLV_CMD8_INT_ST_S 5 +/** SPI_SLV_CMD9_INT_ST : RO; bitpos: [6]; default: 0; + * The status bit for SPI slave CMD9 interrupt. + */ +#define SPI_SLV_CMD9_INT_ST (BIT(6)) +#define SPI_SLV_CMD9_INT_ST_M (SPI_SLV_CMD9_INT_ST_V << SPI_SLV_CMD9_INT_ST_S) +#define SPI_SLV_CMD9_INT_ST_V 0x00000001U +#define SPI_SLV_CMD9_INT_ST_S 6 +/** SPI_SLV_CMDA_INT_ST : RO; bitpos: [7]; default: 0; + * The status bit for SPI slave CMDA interrupt. + */ +#define SPI_SLV_CMDA_INT_ST (BIT(7)) +#define SPI_SLV_CMDA_INT_ST_M (SPI_SLV_CMDA_INT_ST_V << SPI_SLV_CMDA_INT_ST_S) +#define SPI_SLV_CMDA_INT_ST_V 0x00000001U +#define SPI_SLV_CMDA_INT_ST_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_ST : RO; bitpos: [8]; default: 0; + * The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_ST (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ST_M (SPI_SLV_RD_DMA_DONE_INT_ST_V << SPI_SLV_RD_DMA_DONE_INT_ST_S) +#define SPI_SLV_RD_DMA_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_ST_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_ST : RO; bitpos: [9]; default: 0; + * The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_ST (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ST_M (SPI_SLV_WR_DMA_DONE_INT_ST_V << SPI_SLV_WR_DMA_DONE_INT_ST_S) +#define SPI_SLV_WR_DMA_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_ST_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_ST : RO; bitpos: [10]; default: 0; + * The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_ST (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ST_M (SPI_SLV_RD_BUF_DONE_INT_ST_V << SPI_SLV_RD_BUF_DONE_INT_ST_S) +#define SPI_SLV_RD_BUF_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_ST_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_ST : RO; bitpos: [11]; default: 0; + * The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_ST (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ST_M (SPI_SLV_WR_BUF_DONE_INT_ST_V << SPI_SLV_WR_BUF_DONE_INT_ST_S) +#define SPI_SLV_WR_BUF_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_ST_S 11 +/** SPI_TRANS_DONE_INT_ST : RO; bitpos: [12]; default: 0; + * The status bit for SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_ST (BIT(12)) +#define SPI_TRANS_DONE_INT_ST_M (SPI_TRANS_DONE_INT_ST_V << SPI_TRANS_DONE_INT_ST_S) +#define SPI_TRANS_DONE_INT_ST_V 0x00000001U +#define SPI_TRANS_DONE_INT_ST_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_ST : RO; bitpos: [13]; default: 0; + * The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_ST (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M (SPI_DMA_SEG_TRANS_DONE_INT_ST_V << SPI_DMA_SEG_TRANS_DONE_INT_ST_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S 13 +/** SPI_SEG_MAGIC_ERR_INT_ST : RO; bitpos: [14]; default: 0; + * The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ +#define SPI_SEG_MAGIC_ERR_INT_ST (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ST_M (SPI_SEG_MAGIC_ERR_INT_ST_V << SPI_SEG_MAGIC_ERR_INT_ST_S) +#define SPI_SEG_MAGIC_ERR_INT_ST_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_ST_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_ST : RO; bitpos: [15]; default: 0; + * The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_ST (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M (SPI_SLV_BUF_ADDR_ERR_INT_ST_V << SPI_SLV_BUF_ADDR_ERR_INT_ST_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S 15 +/** SPI_SLV_CMD_ERR_INT_ST : RO; bitpos: [16]; default: 0; + * The status bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_ST (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ST_M (SPI_SLV_CMD_ERR_INT_ST_V << SPI_SLV_CMD_ERR_INT_ST_S) +#define SPI_SLV_CMD_ERR_INT_ST_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_ST_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO; bitpos: [17]; default: 0; + * The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO; bitpos: [18]; default: 0; + * The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S 18 +/** SPI_APP2_INT_ST : RO; bitpos: [19]; default: 0; + * The status bit for SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_ST (BIT(19)) +#define SPI_APP2_INT_ST_M (SPI_APP2_INT_ST_V << SPI_APP2_INT_ST_S) +#define SPI_APP2_INT_ST_V 0x00000001U +#define SPI_APP2_INT_ST_S 19 +/** SPI_APP1_INT_ST : RO; bitpos: [20]; default: 0; + * The status bit for SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_ST (BIT(20)) +#define SPI_APP1_INT_ST_M (SPI_APP1_INT_ST_V << SPI_APP1_INT_ST_S) +#define SPI_APP1_INT_ST_V 0x00000001U +#define SPI_APP1_INT_ST_S 20 + +/** SPI_DMA_INT_SET_REG register + * SPI interrupt software set register + */ +#define SPI_DMA_INT_SET_REG(i) (REG_SPI_BASE(i) + 0x44) +/** SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT; bitpos: [0]; default: 0; + * The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M (SPI_DMA_INFIFO_FULL_ERR_INT_SET_V << SPI_DMA_INFIFO_FULL_ERR_INT_SET_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT; bitpos: [1]; default: 0; + * The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S 1 +/** SPI_SLV_EX_QPI_INT_SET : WT; bitpos: [2]; default: 0; + * The software set bit for SPI slave Ex_QPI interrupt. + */ +#define SPI_SLV_EX_QPI_INT_SET (BIT(2)) +#define SPI_SLV_EX_QPI_INT_SET_M (SPI_SLV_EX_QPI_INT_SET_V << SPI_SLV_EX_QPI_INT_SET_S) +#define SPI_SLV_EX_QPI_INT_SET_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_SET_S 2 +/** SPI_SLV_EN_QPI_INT_SET : WT; bitpos: [3]; default: 0; + * The software set bit for SPI slave En_QPI interrupt. + */ +#define SPI_SLV_EN_QPI_INT_SET (BIT(3)) +#define SPI_SLV_EN_QPI_INT_SET_M (SPI_SLV_EN_QPI_INT_SET_V << SPI_SLV_EN_QPI_INT_SET_S) +#define SPI_SLV_EN_QPI_INT_SET_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_SET_S 3 +/** SPI_SLV_CMD7_INT_SET : WT; bitpos: [4]; default: 0; + * The software set bit for SPI slave CMD7 interrupt. + */ +#define SPI_SLV_CMD7_INT_SET (BIT(4)) +#define SPI_SLV_CMD7_INT_SET_M (SPI_SLV_CMD7_INT_SET_V << SPI_SLV_CMD7_INT_SET_S) +#define SPI_SLV_CMD7_INT_SET_V 0x00000001U +#define SPI_SLV_CMD7_INT_SET_S 4 +/** SPI_SLV_CMD8_INT_SET : WT; bitpos: [5]; default: 0; + * The software set bit for SPI slave CMD8 interrupt. + */ +#define SPI_SLV_CMD8_INT_SET (BIT(5)) +#define SPI_SLV_CMD8_INT_SET_M (SPI_SLV_CMD8_INT_SET_V << SPI_SLV_CMD8_INT_SET_S) +#define SPI_SLV_CMD8_INT_SET_V 0x00000001U +#define SPI_SLV_CMD8_INT_SET_S 5 +/** SPI_SLV_CMD9_INT_SET : WT; bitpos: [6]; default: 0; + * The software set bit for SPI slave CMD9 interrupt. + */ +#define SPI_SLV_CMD9_INT_SET (BIT(6)) +#define SPI_SLV_CMD9_INT_SET_M (SPI_SLV_CMD9_INT_SET_V << SPI_SLV_CMD9_INT_SET_S) +#define SPI_SLV_CMD9_INT_SET_V 0x00000001U +#define SPI_SLV_CMD9_INT_SET_S 6 +/** SPI_SLV_CMDA_INT_SET : WT; bitpos: [7]; default: 0; + * The software set bit for SPI slave CMDA interrupt. + */ +#define SPI_SLV_CMDA_INT_SET (BIT(7)) +#define SPI_SLV_CMDA_INT_SET_M (SPI_SLV_CMDA_INT_SET_V << SPI_SLV_CMDA_INT_SET_S) +#define SPI_SLV_CMDA_INT_SET_V 0x00000001U +#define SPI_SLV_CMDA_INT_SET_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_SET : WT; bitpos: [8]; default: 0; + * The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_SET (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_SET_M (SPI_SLV_RD_DMA_DONE_INT_SET_V << SPI_SLV_RD_DMA_DONE_INT_SET_S) +#define SPI_SLV_RD_DMA_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_SET_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_SET : WT; bitpos: [9]; default: 0; + * The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_SET (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_SET_M (SPI_SLV_WR_DMA_DONE_INT_SET_V << SPI_SLV_WR_DMA_DONE_INT_SET_S) +#define SPI_SLV_WR_DMA_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_SET_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_SET : WT; bitpos: [10]; default: 0; + * The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_SET (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_SET_M (SPI_SLV_RD_BUF_DONE_INT_SET_V << SPI_SLV_RD_BUF_DONE_INT_SET_S) +#define SPI_SLV_RD_BUF_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_SET_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_SET : WT; bitpos: [11]; default: 0; + * The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_SET (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_SET_M (SPI_SLV_WR_BUF_DONE_INT_SET_V << SPI_SLV_WR_BUF_DONE_INT_SET_S) +#define SPI_SLV_WR_BUF_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_SET_S 11 +/** SPI_TRANS_DONE_INT_SET : WT; bitpos: [12]; default: 0; + * The software set bit for SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_SET (BIT(12)) +#define SPI_TRANS_DONE_INT_SET_M (SPI_TRANS_DONE_INT_SET_V << SPI_TRANS_DONE_INT_SET_S) +#define SPI_TRANS_DONE_INT_SET_V 0x00000001U +#define SPI_TRANS_DONE_INT_SET_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_SET : WT; bitpos: [13]; default: 0; + * The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_SET (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M (SPI_DMA_SEG_TRANS_DONE_INT_SET_V << SPI_DMA_SEG_TRANS_DONE_INT_SET_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S 13 +/** SPI_SEG_MAGIC_ERR_INT_SET : WT; bitpos: [14]; default: 0; + * The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ +#define SPI_SEG_MAGIC_ERR_INT_SET (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_SET_M (SPI_SEG_MAGIC_ERR_INT_SET_V << SPI_SEG_MAGIC_ERR_INT_SET_S) +#define SPI_SEG_MAGIC_ERR_INT_SET_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_SET_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_SET : WT; bitpos: [15]; default: 0; + * The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_SET (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M (SPI_SLV_BUF_ADDR_ERR_INT_SET_V << SPI_SLV_BUF_ADDR_ERR_INT_SET_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S 15 +/** SPI_SLV_CMD_ERR_INT_SET : WT; bitpos: [16]; default: 0; + * The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_SET (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_SET_M (SPI_SLV_CMD_ERR_INT_SET_V << SPI_SLV_CMD_ERR_INT_SET_S) +#define SPI_SLV_CMD_ERR_INT_SET_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_SET_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT; bitpos: [17]; default: 0; + * The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT; bitpos: [18]; default: 0; + * The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S 18 +/** SPI_APP2_INT_SET : WT; bitpos: [19]; default: 0; + * The software set bit for SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_SET (BIT(19)) +#define SPI_APP2_INT_SET_M (SPI_APP2_INT_SET_V << SPI_APP2_INT_SET_S) +#define SPI_APP2_INT_SET_V 0x00000001U +#define SPI_APP2_INT_SET_S 19 +/** SPI_APP1_INT_SET : WT; bitpos: [20]; default: 0; + * The software set bit for SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_SET (BIT(20)) +#define SPI_APP1_INT_SET_M (SPI_APP1_INT_SET_V << SPI_APP1_INT_SET_S) +#define SPI_APP1_INT_SET_V 0x00000001U +#define SPI_APP1_INT_SET_S 20 + +/** SPI_W0_REG register + * SPI CPU-controlled buffer0 + */ +#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x98) +/** SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF0 0xFFFFFFFFU +#define SPI_BUF0_M (SPI_BUF0_V << SPI_BUF0_S) +#define SPI_BUF0_V 0xFFFFFFFFU +#define SPI_BUF0_S 0 + +/** SPI_W1_REG register + * SPI CPU-controlled buffer1 + */ +#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x9c) +/** SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF1 0xFFFFFFFFU +#define SPI_BUF1_M (SPI_BUF1_V << SPI_BUF1_S) +#define SPI_BUF1_V 0xFFFFFFFFU +#define SPI_BUF1_S 0 + +/** SPI_W2_REG register + * SPI CPU-controlled buffer2 + */ +#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0xa0) +/** SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF2 0xFFFFFFFFU +#define SPI_BUF2_M (SPI_BUF2_V << SPI_BUF2_S) +#define SPI_BUF2_V 0xFFFFFFFFU +#define SPI_BUF2_S 0 + +/** SPI_W3_REG register + * SPI CPU-controlled buffer3 + */ +#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0xa4) +/** SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF3 0xFFFFFFFFU +#define SPI_BUF3_M (SPI_BUF3_V << SPI_BUF3_S) +#define SPI_BUF3_V 0xFFFFFFFFU +#define SPI_BUF3_S 0 + +/** SPI_W4_REG register + * SPI CPU-controlled buffer4 + */ +#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0xa8) +/** SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF4 0xFFFFFFFFU +#define SPI_BUF4_M (SPI_BUF4_V << SPI_BUF4_S) +#define SPI_BUF4_V 0xFFFFFFFFU +#define SPI_BUF4_S 0 + +/** SPI_W5_REG register + * SPI CPU-controlled buffer5 + */ +#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0xac) +/** SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF5 0xFFFFFFFFU +#define SPI_BUF5_M (SPI_BUF5_V << SPI_BUF5_S) +#define SPI_BUF5_V 0xFFFFFFFFU +#define SPI_BUF5_S 0 + +/** SPI_W6_REG register + * SPI CPU-controlled buffer6 + */ +#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0xb0) +/** SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF6 0xFFFFFFFFU +#define SPI_BUF6_M (SPI_BUF6_V << SPI_BUF6_S) +#define SPI_BUF6_V 0xFFFFFFFFU +#define SPI_BUF6_S 0 + +/** SPI_W7_REG register + * SPI CPU-controlled buffer7 + */ +#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0xb4) +/** SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF7 0xFFFFFFFFU +#define SPI_BUF7_M (SPI_BUF7_V << SPI_BUF7_S) +#define SPI_BUF7_V 0xFFFFFFFFU +#define SPI_BUF7_S 0 + +/** SPI_W8_REG register + * SPI CPU-controlled buffer8 + */ +#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xb8) +/** SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF8 0xFFFFFFFFU +#define SPI_BUF8_M (SPI_BUF8_V << SPI_BUF8_S) +#define SPI_BUF8_V 0xFFFFFFFFU +#define SPI_BUF8_S 0 + +/** SPI_W9_REG register + * SPI CPU-controlled buffer9 + */ +#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xbc) +/** SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF9 0xFFFFFFFFU +#define SPI_BUF9_M (SPI_BUF9_V << SPI_BUF9_S) +#define SPI_BUF9_V 0xFFFFFFFFU +#define SPI_BUF9_S 0 + +/** SPI_W10_REG register + * SPI CPU-controlled buffer10 + */ +#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xc0) +/** SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF10 0xFFFFFFFFU +#define SPI_BUF10_M (SPI_BUF10_V << SPI_BUF10_S) +#define SPI_BUF10_V 0xFFFFFFFFU +#define SPI_BUF10_S 0 + +/** SPI_W11_REG register + * SPI CPU-controlled buffer11 + */ +#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xc4) +/** SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF11 0xFFFFFFFFU +#define SPI_BUF11_M (SPI_BUF11_V << SPI_BUF11_S) +#define SPI_BUF11_V 0xFFFFFFFFU +#define SPI_BUF11_S 0 + +/** SPI_W12_REG register + * SPI CPU-controlled buffer12 + */ +#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xc8) +/** SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF12 0xFFFFFFFFU +#define SPI_BUF12_M (SPI_BUF12_V << SPI_BUF12_S) +#define SPI_BUF12_V 0xFFFFFFFFU +#define SPI_BUF12_S 0 + +/** SPI_W13_REG register + * SPI CPU-controlled buffer13 + */ +#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xcc) +/** SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF13 0xFFFFFFFFU +#define SPI_BUF13_M (SPI_BUF13_V << SPI_BUF13_S) +#define SPI_BUF13_V 0xFFFFFFFFU +#define SPI_BUF13_S 0 + +/** SPI_W14_REG register + * SPI CPU-controlled buffer14 + */ +#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xd0) +/** SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF14 0xFFFFFFFFU +#define SPI_BUF14_M (SPI_BUF14_V << SPI_BUF14_S) +#define SPI_BUF14_V 0xFFFFFFFFU +#define SPI_BUF14_S 0 + +/** SPI_W15_REG register + * SPI CPU-controlled buffer15 + */ +#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xd4) +/** SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF15 0xFFFFFFFFU +#define SPI_BUF15_M (SPI_BUF15_V << SPI_BUF15_S) +#define SPI_BUF15_V 0xFFFFFFFFU +#define SPI_BUF15_S 0 + +/** SPI_SLAVE_REG register + * SPI slave control register + */ +#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0xe0) +/** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is alwasy on. Can be configured in CONF state. + */ +#define SPI_CLK_MODE 0x00000003U +#define SPI_CLK_MODE_M (SPI_CLK_MODE_V << SPI_CLK_MODE_S) +#define SPI_CLK_MODE_V 0x00000003U +#define SPI_CLK_MODE_S 0 +/** SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0; + * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: + * support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + */ +#define SPI_CLK_MODE_13 (BIT(2)) +#define SPI_CLK_MODE_13_M (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S) +#define SPI_CLK_MODE_13_V 0x00000001U +#define SPI_CLK_MODE_13_S 2 +/** SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0; + * It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge + * 0: output data at tsck posedge + */ +#define SPI_RSCK_DATA_OUT (BIT(3)) +#define SPI_RSCK_DATA_OUT_M (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S) +#define SPI_RSCK_DATA_OUT_V 0x00000001U +#define SPI_RSCK_DATA_OUT_S 3 +/** SPI_SLV_RDDMA_BITLEN_EN : R/W; bitpos: [8]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * DMA controlled mode(Rd_DMA). 0: others + */ +#define SPI_SLV_RDDMA_BITLEN_EN (BIT(8)) +#define SPI_SLV_RDDMA_BITLEN_EN_M (SPI_SLV_RDDMA_BITLEN_EN_V << SPI_SLV_RDDMA_BITLEN_EN_S) +#define SPI_SLV_RDDMA_BITLEN_EN_V 0x00000001U +#define SPI_SLV_RDDMA_BITLEN_EN_S 8 +/** SPI_SLV_WRDMA_BITLEN_EN : R/W; bitpos: [9]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in DMA controlled mode(Wr_DMA). 0: others + */ +#define SPI_SLV_WRDMA_BITLEN_EN (BIT(9)) +#define SPI_SLV_WRDMA_BITLEN_EN_M (SPI_SLV_WRDMA_BITLEN_EN_V << SPI_SLV_WRDMA_BITLEN_EN_S) +#define SPI_SLV_WRDMA_BITLEN_EN_V 0x00000001U +#define SPI_SLV_WRDMA_BITLEN_EN_S 9 +/** SPI_SLV_RDBUF_BITLEN_EN : R/W; bitpos: [10]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * CPU controlled mode(Rd_BUF). 0: others + */ +#define SPI_SLV_RDBUF_BITLEN_EN (BIT(10)) +#define SPI_SLV_RDBUF_BITLEN_EN_M (SPI_SLV_RDBUF_BITLEN_EN_V << SPI_SLV_RDBUF_BITLEN_EN_S) +#define SPI_SLV_RDBUF_BITLEN_EN_V 0x00000001U +#define SPI_SLV_RDBUF_BITLEN_EN_S 10 +/** SPI_SLV_WRBUF_BITLEN_EN : R/W; bitpos: [11]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in CPU controlled mode(Wr_BUF). 0: others + */ +#define SPI_SLV_WRBUF_BITLEN_EN (BIT(11)) +#define SPI_SLV_WRBUF_BITLEN_EN_M (SPI_SLV_WRBUF_BITLEN_EN_V << SPI_SLV_WRBUF_BITLEN_EN_S) +#define SPI_SLV_WRBUF_BITLEN_EN_V 0x00000001U +#define SPI_SLV_WRBUF_BITLEN_EN_S 11 +/** SPI_DMA_SEG_MAGIC_VALUE : R/W; bitpos: [25:22]; default: 10; + * The magic value of BM table in master DMA seg-trans. + */ +#define SPI_DMA_SEG_MAGIC_VALUE 0x0000000FU +#define SPI_DMA_SEG_MAGIC_VALUE_M (SPI_DMA_SEG_MAGIC_VALUE_V << SPI_DMA_SEG_MAGIC_VALUE_S) +#define SPI_DMA_SEG_MAGIC_VALUE_V 0x0000000FU +#define SPI_DMA_SEG_MAGIC_VALUE_S 22 +/** SPI_SLAVE_MODE : R/W; bitpos: [26]; default: 0; + * Set SPI work mode. 1: slave mode 0: master mode. + */ +#define SPI_SLAVE_MODE (BIT(26)) +#define SPI_SLAVE_MODE_M (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S) +#define SPI_SLAVE_MODE_V 0x00000001U +#define SPI_SLAVE_MODE_S 26 +/** SPI_SOFT_RESET : WT; bitpos: [27]; default: 0; + * Software reset enable, reset the spi clock line cs line and data lines. Can be + * configured in CONF state. + */ +#define SPI_SOFT_RESET (BIT(27)) +#define SPI_SOFT_RESET_M (SPI_SOFT_RESET_V << SPI_SOFT_RESET_S) +#define SPI_SOFT_RESET_V 0x00000001U +#define SPI_SOFT_RESET_S 27 +/** SPI_USR_CONF : R/W; bitpos: [28]; default: 0; + * 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans + * will start. 0: This is not seg-trans mode. + */ +#define SPI_USR_CONF (BIT(28)) +#define SPI_USR_CONF_M (SPI_USR_CONF_V << SPI_USR_CONF_S) +#define SPI_USR_CONF_V 0x00000001U +#define SPI_USR_CONF_S 28 +/** SPI_MST_FD_WAIT_DMA_TX_DATA : R/W; bitpos: [29]; default: 0; + * In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before + * starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI + * transfer. + */ +#define SPI_MST_FD_WAIT_DMA_TX_DATA (BIT(29)) +#define SPI_MST_FD_WAIT_DMA_TX_DATA_M (SPI_MST_FD_WAIT_DMA_TX_DATA_V << SPI_MST_FD_WAIT_DMA_TX_DATA_S) +#define SPI_MST_FD_WAIT_DMA_TX_DATA_V 0x00000001U +#define SPI_MST_FD_WAIT_DMA_TX_DATA_S 29 + +/** SPI_SLAVE1_REG register + * SPI slave control register 1 + */ +#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0xe4) +/** SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0; + * The transferred data bit length in SPI slave FD and HD mode. + */ +#define SPI_SLV_DATA_BITLEN 0x0003FFFFU +#define SPI_SLV_DATA_BITLEN_M (SPI_SLV_DATA_BITLEN_V << SPI_SLV_DATA_BITLEN_S) +#define SPI_SLV_DATA_BITLEN_V 0x0003FFFFU +#define SPI_SLV_DATA_BITLEN_S 0 +/** SPI_SLV_LAST_COMMAND : R/W/SS; bitpos: [25:18]; default: 0; + * In the slave mode it is the value of command. + */ +#define SPI_SLV_LAST_COMMAND 0x000000FFU +#define SPI_SLV_LAST_COMMAND_M (SPI_SLV_LAST_COMMAND_V << SPI_SLV_LAST_COMMAND_S) +#define SPI_SLV_LAST_COMMAND_V 0x000000FFU +#define SPI_SLV_LAST_COMMAND_S 18 +/** SPI_SLV_LAST_ADDR : R/W/SS; bitpos: [31:26]; default: 0; + * In the slave mode it is the value of address. + */ +#define SPI_SLV_LAST_ADDR 0x0000003FU +#define SPI_SLV_LAST_ADDR_M (SPI_SLV_LAST_ADDR_V << SPI_SLV_LAST_ADDR_S) +#define SPI_SLV_LAST_ADDR_V 0x0000003FU +#define SPI_SLV_LAST_ADDR_S 26 + +/** SPI_CLK_GATE_REG register + * SPI module clock and register clock control + */ +#define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0xe8) +/** SPI_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to enable clk gate + */ +#define SPI_CLK_EN (BIT(0)) +#define SPI_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S) +#define SPI_CLK_EN_V 0x00000001U +#define SPI_CLK_EN_S 0 +/** SPI_MST_CLK_ACTIVE : R/W; bitpos: [1]; default: 0; + * Set this bit to power on the SPI module clock. + */ +#define SPI_MST_CLK_ACTIVE (BIT(1)) +#define SPI_MST_CLK_ACTIVE_M (SPI_MST_CLK_ACTIVE_V << SPI_MST_CLK_ACTIVE_S) +#define SPI_MST_CLK_ACTIVE_V 0x00000001U +#define SPI_MST_CLK_ACTIVE_S 1 +/** SPI_MST_CLK_SEL : R/W; bitpos: [2]; default: 0; + * This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. + * 0: XTAL CLK. + */ +#define SPI_MST_CLK_SEL (BIT(2)) +#define SPI_MST_CLK_SEL_M (SPI_MST_CLK_SEL_V << SPI_MST_CLK_SEL_S) +#define SPI_MST_CLK_SEL_V 0x00000001U +#define SPI_MST_CLK_SEL_S 2 + +/** SPI_DATE_REG register + * Version control + */ +#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0xf0) +/** SPI_DATE : R/W; bitpos: [27:0]; default: 35656448; + * SPI register version. + */ +#define SPI_DATE 0x0FFFFFFFU +#define SPI_DATE_M (SPI_DATE_V << SPI_DATE_S) +#define SPI_DATE_V 0x0FFFFFFFU +#define SPI_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/spi_struct.h b/components/soc/esp32c6/include/soc/spi_struct.h new file mode 100644 index 0000000000..14b6be86c1 --- /dev/null +++ b/components/soc/esp32c6/include/soc/spi_struct.h @@ -0,0 +1,1400 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: User-defined control registers */ +/** Type of cmd register + * Command control register + */ +typedef union { + struct { + /** conf_bitlen : R/W; bitpos: [17:0]; default: 0; + * Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + */ + uint32_t conf_bitlen:18; + uint32_t reserved_18:5; + /** update : WT; bitpos: [23]; default: 0; + * Set this bit to synchronize SPI registers from APB clock domain into SPI module + * clock domain, which is only used in SPI master mode. + */ + uint32_t update:1; + /** usr : R/W/SC; bitpos: [24]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. Can not be + * changed by CONF_buf. + */ + uint32_t usr:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} spi_cmd_reg_t; + +/** Type of addr register + * Address value register + */ +typedef union { + struct { + /** usr_addr_value : R/W; bitpos: [31:0]; default: 0; + * Address to slave. Can be configured in CONF state. + */ + uint32_t usr_addr_value:32; + }; + uint32_t val; +} spi_addr_reg_t; + +/** Type of user register + * SPI USER control register + */ +typedef union { + struct { + /** doutdin : R/W; bitpos: [0]; default: 0; + * Set the bit to enable full duplex communication. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t doutdin:1; + uint32_t reserved_1:2; + /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0; + * Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. + * Can be configured in CONF state. + */ + uint32_t qpi_mode:1; + /** opi_mode : HRO; bitpos: [4]; default: 0; + * Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. + * Can be configured in CONF state. + */ + uint32_t opi_mode:1; + /** tsck_i_edge : R/W; bitpos: [5]; default: 0; + * In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = + * spi_ck_i. 1:tsck = !spi_ck_i. + */ + uint32_t tsck_i_edge:1; + /** cs_hold : R/W; bitpos: [6]; default: 1; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t cs_hold:1; + /** cs_setup : R/W; bitpos: [7]; default: 1; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t cs_setup:1; + /** rsck_i_edge : R/W; bitpos: [8]; default: 0; + * In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = + * !spi_ck_i. 1:rsck = spi_ck_i. + */ + uint32_t rsck_i_edge:1; + /** ck_out_edge : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can + * be configured in CONF state. + */ + uint32_t ck_out_edge:1; + uint32_t reserved_10:2; + /** fwrite_dual : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_dual:1; + /** fwrite_quad : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_quad:1; + /** fwrite_oct : HRO; bitpos: [14]; default: 0; + * In the write operations read-data phase apply 8 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_oct:1; + /** usr_conf_nxt : R/W; bitpos: [15]; default: 0; + * 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans + * will continue. 0: The seg-trans will end after the current SPI seg-trans or this is + * not seg-trans mode. Can be configured in CONF state. + */ + uint32_t usr_conf_nxt:1; + uint32_t reserved_16:1; + /** sio : R/W; bitpos: [17]; default: 0; + * Set the bit to enable 3-line half duplex communication mosi and miso signals share + * the same pin. 1: enable 0: disable. Can be configured in CONF state. + */ + uint32_t sio:1; + uint32_t reserved_18:6; + /** usr_miso_highpart : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: + * disable. Can be configured in CONF state. + */ + uint32_t usr_miso_highpart:1; + /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable + * 0: disable. Can be configured in CONF state. + */ + uint32_t usr_mosi_highpart:1; + /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. Can be configured in + * CONF state. + */ + uint32_t usr_dummy_idle:1; + /** usr_mosi : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. Can be configured in CONF + * state. + */ + uint32_t usr_mosi:1; + /** usr_miso : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. Can be configured in CONF + * state. + */ + uint32_t usr_miso:1; + /** usr_dummy : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_dummy:1; + /** usr_addr : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_addr:1; + /** usr_command : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_command:1; + }; + uint32_t val; +} spi_user_reg_t; + +/** Type of user1 register + * SPI USER control register 1 + */ +typedef union { + struct { + /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7; + * The length in spi_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). Can be configured in CONF state. + */ + uint32_t usr_dummy_cyclelen:8; + uint32_t reserved_8:8; + /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1; + * 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master + * FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in + * GP-SPI master FD/HD-mode. + */ + uint32_t mst_wfull_err_end_en:1; + /** cs_setup_time : R/W; bitpos: [21:17]; default: 0; + * (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup + * bit. Can be configured in CONF state. + */ + uint32_t cs_setup_time:5; + /** cs_hold_time : R/W; bitpos: [26:22]; default: 1; + * delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. + * Can be configured in CONF state. + */ + uint32_t cs_hold_time:5; + /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ + uint32_t usr_addr_bitlen:5; + }; + uint32_t val; +} spi_user1_reg_t; + +/** Type of user2 register + * SPI USER control register 2 + */ +typedef union { + struct { + /** usr_command_value : R/W; bitpos: [15:0]; default: 0; + * The value of command. Can be configured in CONF state. + */ + uint32_t usr_command_value:16; + uint32_t reserved_16:11; + /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1; + * 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI + * master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error + * is valid in GP-SPI master FD/HD-mode. + */ + uint32_t mst_rempty_err_end_en:1; + /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ + uint32_t usr_command_bitlen:4; + }; + uint32_t val; +} spi_user2_reg_t; + + +/** Group: Control and configuration registers */ +/** Type of ctrl register + * SPI control register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** dummy_out : R/W; bitpos: [3]; default: 0; + * 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, + * the FSPI bus signals are output. Can be configured in CONF state. + */ + uint32_t dummy_out:1; + uint32_t reserved_4:1; + /** faddr_dual : R/W; bitpos: [5]; default: 0; + * Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_dual:1; + /** faddr_quad : R/W; bitpos: [6]; default: 0; + * Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_quad:1; + /** faddr_oct : HRO; bitpos: [7]; default: 0; + * Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_oct:1; + /** fcmd_dual : R/W; bitpos: [8]; default: 0; + * Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_dual:1; + /** fcmd_quad : R/W; bitpos: [9]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_quad:1; + /** fcmd_oct : HRO; bitpos: [10]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_oct:1; + uint32_t reserved_11:3; + /** fread_dual : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_dual:1; + /** fread_quad : R/W; bitpos: [15]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_quad:1; + /** fread_oct : HRO; bitpos: [16]; default: 0; + * In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_oct:1; + uint32_t reserved_17:1; + /** q_pol : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ + uint32_t q_pol:1; + /** d_pol : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ + uint32_t d_pol:1; + /** hold_pol : R/W; bitpos: [20]; default: 1; + * SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be + * configured in CONF state. + */ + uint32_t hold_pol:1; + /** wp_pol : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. Can + * be configured in CONF state. + */ + uint32_t wp_pol:1; + uint32_t reserved_22:1; + /** rd_bit_order : R/W; bitpos: [24:23]; default: 0; + * In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF + * state. + */ + uint32_t rd_bit_order:2; + /** wr_bit_order : R/W; bitpos: [26:25]; default: 0; + * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be + * configured in CONF state. + */ + uint32_t wr_bit_order:2; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_ctrl_reg_t; + +/** Type of ms_dlen register + * SPI data bit length control register + */ +typedef union { + struct { + /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0; + * The value of these bits is the configured SPI transmission data bit length in + * master mode DMA controlled transfer or CPU controlled transfer. The value is also + * the configured bit length in slave mode DMA RX controlled transfer. The register + * value shall be (bit_num-1). Can be configured in CONF state. + */ + uint32_t ms_data_bitlen:18; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_ms_dlen_reg_t; + +/** Type of misc register + * SPI misc register + */ +typedef union { + struct { + /** cs0_dis : R/W; bitpos: [0]; default: 0; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs0_dis:1; + /** cs1_dis : R/W; bitpos: [1]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs1_dis:1; + /** cs2_dis : R/W; bitpos: [2]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs2_dis:1; + /** cs3_dis : R/W; bitpos: [3]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs3_dis:1; + /** cs4_dis : R/W; bitpos: [4]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs4_dis:1; + /** cs5_dis : R/W; bitpos: [5]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs5_dis:1; + /** ck_dis : R/W; bitpos: [6]; default: 0; + * 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + */ + uint32_t ck_dis:1; + /** master_cs_pol : R/W; bitpos: [12:7]; default: 0; + * In the master mode the bits are the polarity of spi cs line, the value is + * equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + */ + uint32_t master_cs_pol:6; + uint32_t reserved_13:3; + /** clk_data_dtr_en : HRO; bitpos: [16]; default: 0; + * 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR + * mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + */ + uint32_t clk_data_dtr_en:1; + /** data_dtr_en : HRO; bitpos: [17]; default: 0; + * 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. + * Can be configured in CONF state. + */ + uint32_t data_dtr_en:1; + /** addr_dtr_en : HRO; bitpos: [18]; default: 0; + * 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be + * configured in CONF state. + */ + uint32_t addr_dtr_en:1; + /** cmd_dtr_en : HRO; bitpos: [19]; default: 0; + * 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be + * configured in CONF state. + */ + uint32_t cmd_dtr_en:1; + uint32_t reserved_20:3; + /** slave_cs_pol : R/W; bitpos: [23]; default: 0; + * spi slave input cs polarity select. 1: inv 0: not change. Can be configured in + * CONF state. + */ + uint32_t slave_cs_pol:1; + /** dqs_idle_edge : HRO; bitpos: [24]; default: 0; + * The default value of spi_dqs. Can be configured in CONF state. + */ + uint32_t dqs_idle_edge:1; + uint32_t reserved_25:4; + /** ck_idle_edge : R/W; bitpos: [29]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be + * configured in CONF state. + */ + uint32_t ck_idle_edge:1; + /** cs_keep_active : R/W; bitpos: [30]; default: 0; + * spi cs line keep low when the bit is set. Can be configured in CONF state. + */ + uint32_t cs_keep_active:1; + /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0; + * 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: + * spi quad input swap disable. Can be configured in CONF state. + */ + uint32_t quad_din_pin_swap:1; + }; + uint32_t val; +} spi_misc_reg_t; + +/** Type of dma_conf register + * SPI DMA control register + */ +typedef union { + struct { + /** dma_outfifo_empty : RO; bitpos: [0]; default: 1; + * Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: + * DMA TX FIFO is ready for sending data. + */ + uint32_t dma_outfifo_empty:1; + /** dma_infifo_full : RO; bitpos: [1]; default: 1; + * Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. + * 0: DMA RX FIFO is ready for receiving data. + */ + uint32_t dma_infifo_full:1; + uint32_t reserved_2:16; + /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0; + * Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + */ + uint32_t dma_slv_seg_trans_en:1; + /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0; + * 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: + * spi_dma_infifo_full_vld is cleared by spi_trans_done. + */ + uint32_t slv_rx_seg_trans_clr_en:1; + /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0; + * 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: + * spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + */ + uint32_t slv_tx_seg_trans_clr_en:1; + /** rx_eof_en : R/W; bitpos: [21]; default: 0; + * 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to + * the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: + * spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or + * spi_dma_seg_trans_done in seg-trans. + */ + uint32_t rx_eof_en:1; + uint32_t reserved_22:5; + /** dma_rx_ena : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI DMA controlled receive data mode. + */ + uint32_t dma_rx_ena:1; + /** dma_tx_ena : R/W; bitpos: [28]; default: 0; + * Set this bit to enable SPI DMA controlled send data mode. + */ + uint32_t dma_tx_ena:1; + /** rx_afifo_rst : WT; bitpos: [29]; default: 0; + * Set this bit to reset RX AFIFO, which is used to receive data in SPI master and + * slave mode transfer. + */ + uint32_t rx_afifo_rst:1; + /** buf_afifo_rst : WT; bitpos: [30]; default: 0; + * Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU + * controlled mode transfer and master mode transfer. + */ + uint32_t buf_afifo_rst:1; + /** dma_afifo_rst : WT; bitpos: [31]; default: 0; + * Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA + * controlled mode transfer. + */ + uint32_t dma_afifo_rst:1; + }; + uint32_t val; +} spi_dma_conf_reg_t; + +/** Type of slave register + * SPI slave control register + */ +typedef union { + struct { + /** clk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is alwasy on. Can be configured in CONF state. + */ + uint32_t clk_mode:2; + /** clk_mode_13 : R/W; bitpos: [2]; default: 0; + * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: + * support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + */ + uint32_t clk_mode_13:1; + /** rsck_data_out : R/W; bitpos: [3]; default: 0; + * It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge + * 0: output data at tsck posedge + */ + uint32_t rsck_data_out:1; + uint32_t reserved_4:4; + /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * DMA controlled mode(Rd_DMA). 0: others + */ + uint32_t slv_rddma_bitlen_en:1; + /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in DMA controlled mode(Wr_DMA). 0: others + */ + uint32_t slv_wrdma_bitlen_en:1; + /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * CPU controlled mode(Rd_BUF). 0: others + */ + uint32_t slv_rdbuf_bitlen_en:1; + /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in CPU controlled mode(Wr_BUF). 0: others + */ + uint32_t slv_wrbuf_bitlen_en:1; + uint32_t reserved_12:10; + /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10; + * The magic value of BM table in master DMA seg-trans. + */ + uint32_t dma_seg_magic_value:4; + /** slave_mode : R/W; bitpos: [26]; default: 0; + * Set SPI work mode. 1: slave mode 0: master mode. + */ + uint32_t slave_mode:1; + /** soft_reset : WT; bitpos: [27]; default: 0; + * Software reset enable, reset the spi clock line cs line and data lines. Can be + * configured in CONF state. + */ + uint32_t soft_reset:1; + /** usr_conf : R/W; bitpos: [28]; default: 0; + * 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans + * will start. 0: This is not seg-trans mode. + */ + uint32_t usr_conf:1; + /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0; + * In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before + * starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI + * transfer. + */ + uint32_t mst_fd_wait_dma_tx_data:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_slave_reg_t; + +/** Type of slave1 register + * SPI slave control register 1 + */ +typedef union { + struct { + /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0; + * The transferred data bit length in SPI slave FD and HD mode. + */ + uint32_t slv_data_bitlen:18; + /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0; + * In the slave mode it is the value of command. + */ + uint32_t slv_last_command:8; + /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0; + * In the slave mode it is the value of address. + */ + uint32_t slv_last_addr:6; + }; + uint32_t val; +} spi_slave1_reg_t; + + +/** Group: Clock control registers */ +/** Type of clock register + * SPI clock control register + */ +typedef union { + struct { + /** clkcnt_l : R/W; bitpos: [5:0]; default: 3; + * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be + * 0. Can be configured in CONF state. + */ + uint32_t clkcnt_l:6; + /** clkcnt_h : R/W; bitpos: [11:6]; default: 1; + * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it + * must be 0. Can be configured in CONF state. + */ + uint32_t clkcnt_h:6; + /** clkcnt_n : R/W; bitpos: [17:12]; default: 3; + * In the master mode it is the divider of spi_clk. So spi_clk frequency is + * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + */ + uint32_t clkcnt_n:6; + /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0; + * In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + */ + uint32_t clkdiv_pre:4; + uint32_t reserved_22:9; + /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1; + * In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system + * clock. Can be configured in CONF state. + */ + uint32_t clk_equ_sysclk:1; + }; + uint32_t val; +} spi_clock_reg_t; + +/** Type of clk_gate register + * SPI module clock and register clock control + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Set this bit to enable clk gate + */ + uint32_t clk_en:1; + /** mst_clk_active : R/W; bitpos: [1]; default: 0; + * Set this bit to power on the SPI module clock. + */ + uint32_t mst_clk_active:1; + /** mst_clk_sel : R/W; bitpos: [2]; default: 0; + * This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. + * 0: XTAL CLK. + */ + uint32_t mst_clk_sel:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} spi_clk_gate_reg_t; + + +/** Group: Timing registers */ +/** Type of din_mode register + * SPI input delay mode configuration + */ +typedef union { + struct { + /** din0_mode : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din0_mode:2; + /** din1_mode : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din1_mode:2; + /** din2_mode : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din2_mode:2; + /** din3_mode : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din3_mode:2; + /** din4_mode : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din4_mode:2; + /** din5_mode : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din5_mode:2; + /** din6_mode : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din6_mode:2; + /** din7_mode : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din7_mode:2; + /** timing_hclk_active : R/W; bitpos: [16]; default: 0; + * 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF + * state. + */ + uint32_t timing_hclk_active:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} spi_din_mode_reg_t; + +/** Type of din_num register + * SPI input delay number configuration + */ +typedef union { + struct { + /** din0_num : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din0_num:2; + /** din1_num : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din1_num:2; + /** din2_num : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din2_num:2; + /** din3_num : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din3_num:2; + /** din4_num : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din4_num:2; + /** din5_num : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din5_num:2; + /** din6_num : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din6_num:2; + /** din7_num : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din7_num:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} spi_din_num_reg_t; + +/** Type of dout_mode register + * SPI output delay mode configuration + */ +typedef union { + struct { + /** dout0_mode : R/W; bitpos: [0]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout0_mode:1; + /** dout1_mode : R/W; bitpos: [1]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout1_mode:1; + /** dout2_mode : R/W; bitpos: [2]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout2_mode:1; + /** dout3_mode : R/W; bitpos: [3]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout3_mode:1; + /** dout4_mode : HRO; bitpos: [4]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout4_mode:1; + /** dout5_mode : HRO; bitpos: [5]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout5_mode:1; + /** dout6_mode : HRO; bitpos: [6]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout6_mode:1; + /** dout7_mode : HRO; bitpos: [7]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout7_mode:1; + /** d_dqs_mode : HRO; bitpos: [8]; default: 0; + * The output signal SPI_DQS is delayed by the SPI module clock, 0: output without + * delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t d_dqs_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_dout_mode_reg_t; + + +/** Group: Interrupt registers */ +/** Type of dma_int_ena register + * SPI interrupt enable register + */ +typedef union { + struct { + /** dma_infifo_full_err : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err:1; + /** dma_outfifo_empty_err : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err:1; + /** slv_ex_qpi : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi:1; + /** slv_en_qpi : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi:1; + /** slv_cmd7 : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7:1; + /** slv_cmd8 : R/W; bitpos: [5]; default: 0; + * The enable bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8:1; + /** slv_cmd9 : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9:1; + /** slv_cmda : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda:1; + /** slv_rd_dma_done : R/W; bitpos: [8]; default: 0; + * The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done:1; + /** slv_wr_dma_done : R/W; bitpos: [9]; default: 0; + * The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done:1; + /** slv_rd_buf_done : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done:1; + /** slv_wr_buf_done : R/W; bitpos: [11]; default: 0; + * The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done:1; + /** trans_done : R/W; bitpos: [12]; default: 0; + * The enable bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done:1; + /** dma_seg_trans_done : R/W; bitpos: [13]; default: 0; + * The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done:1; + /** seg_magic_err : R/W; bitpos: [14]; default: 0; + * The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err:1; + /** slv_buf_addr_err : R/W; bitpos: [15]; default: 0; + * The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err:1; + /** slv_cmd_err : R/W; bitpos: [16]; default: 0; + * The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err:1; + /** mst_rx_afifo_wfull_err : R/W; bitpos: [17]; default: 0; + * The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err:1; + /** mst_tx_afifo_rempty_err : R/W; bitpos: [18]; default: 0; + * The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err:1; + /** app2 : R/W; bitpos: [19]; default: 0; + * The enable bit for SPI_APP2_INT interrupt. + */ + uint32_t app2:1; + /** app1 : R/W; bitpos: [20]; default: 0; + * The enable bit for SPI_APP1_INT interrupt. + */ + uint32_t app1:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_ena_reg_t; + +/** Type of dma_int_clr register + * SPI interrupt clear register + */ +typedef union { + struct { + /** dma_infifo_full_err : WT; bitpos: [0]; default: 0; + * The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err:1; + /** dma_outfifo_empty_err : WT; bitpos: [1]; default: 0; + * The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err:1; + /** slv_ex_qpi : WT; bitpos: [2]; default: 0; + * The clear bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi:1; + /** slv_en_qpi : WT; bitpos: [3]; default: 0; + * The clear bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi:1; + /** slv_cmd7 : WT; bitpos: [4]; default: 0; + * The clear bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7:1; + /** slv_cmd8 : WT; bitpos: [5]; default: 0; + * The clear bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8:1; + /** slv_cmd9 : WT; bitpos: [6]; default: 0; + * The clear bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9:1; + /** slv_cmda : WT; bitpos: [7]; default: 0; + * The clear bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda:1; + /** slv_rd_dma_done : WT; bitpos: [8]; default: 0; + * The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done:1; + /** slv_wr_dma_done : WT; bitpos: [9]; default: 0; + * The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done:1; + /** slv_rd_buf_done : WT; bitpos: [10]; default: 0; + * The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done:1; + /** slv_wr_buf_done : WT; bitpos: [11]; default: 0; + * The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done:1; + /** trans_done : WT; bitpos: [12]; default: 0; + * The clear bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done:1; + /** dma_seg_trans_done : WT; bitpos: [13]; default: 0; + * The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done:1; + /** seg_magic_err : WT; bitpos: [14]; default: 0; + * The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err:1; + /** slv_buf_addr_err : WT; bitpos: [15]; default: 0; + * The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err:1; + /** slv_cmd_err : WT; bitpos: [16]; default: 0; + * The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err:1; + /** mst_rx_afifo_wfull_err : WT; bitpos: [17]; default: 0; + * The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err:1; + /** mst_tx_afifo_rempty_err : WT; bitpos: [18]; default: 0; + * The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err:1; + /** app2 : WT; bitpos: [19]; default: 0; + * The clear bit for SPI_APP2_INT interrupt. + */ + uint32_t app2:1; + /** app1 : WT; bitpos: [20]; default: 0; + * The clear bit for SPI_APP1_INT interrupt. + */ + uint32_t app1:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_clr_reg_t; + +/** Type of dma_int_raw register + * SPI interrupt raw register + */ +typedef union { + struct { + /** dma_infifo_full_err : R/WTC/SS; bitpos: [0]; default: 0; + * 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the + * receive data. 0: Others. + */ + uint32_t dma_infifo_full_err:1; + /** dma_outfifo_empty_err : R/WTC/SS; bitpos: [1]; default: 0; + * 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in + * master mode and send out all 0 in slave mode. 0: Others. + */ + uint32_t dma_outfifo_empty_err:1; + /** slv_ex_qpi : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission + * is ended. 0: Others. + */ + uint32_t slv_ex_qpi:1; + /** slv_en_qpi : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission + * is ended. 0: Others. + */ + uint32_t slv_en_qpi:1; + /** slv_cmd7 : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd7:1; + /** slv_cmd8 : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd8:1; + /** slv_cmd9 : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd9:1; + /** slv_cmda : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is + * ended. 0: Others. + */ + uint32_t slv_cmda:1; + /** slv_rd_dma_done : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA + * transmission is ended. 0: Others. + */ + uint32_t slv_rd_dma_done:1; + /** slv_wr_dma_done : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA + * transmission is ended. 0: Others. + */ + uint32_t slv_wr_dma_done:1; + /** slv_rd_buf_done : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF + * transmission is ended. 0: Others. + */ + uint32_t slv_rd_buf_done:1; + /** slv_wr_buf_done : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF + * transmission is ended. 0: Others. + */ + uint32_t slv_wr_buf_done:1; + /** trans_done : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is + * ended. 0: others. + */ + uint32_t trans_done:1; + /** dma_seg_trans_done : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA + * full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. + * And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans + * is not ended or not occurred. + */ + uint32_t dma_seg_trans_done:1; + /** seg_magic_err : R/WTC/SS; bitpos: [14]; default: 0; + * The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer + * is error in the DMA seg-conf-trans. 0: others. + */ + uint32_t seg_magic_err:1; + /** slv_buf_addr_err : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address + * of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is + * bigger than 63. 0: Others. + */ + uint32_t slv_buf_addr_err:1; + /** slv_cmd_err : R/WTC/SS; bitpos: [16]; default: 0; + * The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the + * current SPI slave HD mode transmission is not supported. 0: Others. + */ + uint32_t slv_cmd_err:1; + /** mst_rx_afifo_wfull_err : R/WTC/SS; bitpos: [17]; default: 0; + * The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO + * write-full error when SPI inputs data in master mode. 0: Others. + */ + uint32_t mst_rx_afifo_wfull_err:1; + /** mst_tx_afifo_rempty_err : R/WTC/SS; bitpos: [18]; default: 0; + * The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF + * AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + */ + uint32_t mst_tx_afifo_rempty_err:1; + /** app2 : R/WTC/SS; bitpos: [19]; default: 0; + * The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + */ + uint32_t app2:1; + /** app1 : R/WTC/SS; bitpos: [20]; default: 0; + * The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + */ + uint32_t app1:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_raw_reg_t; + +/** Type of dma_int_st register + * SPI interrupt status register + */ +typedef union { + struct { + /** dma_infifo_full_err : RO; bitpos: [0]; default: 0; + * The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err:1; + /** dma_outfifo_empty_err : RO; bitpos: [1]; default: 0; + * The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err:1; + /** slv_ex_qpi : RO; bitpos: [2]; default: 0; + * The status bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi:1; + /** slv_en_qpi : RO; bitpos: [3]; default: 0; + * The status bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi:1; + /** slv_cmd7 : RO; bitpos: [4]; default: 0; + * The status bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7:1; + /** slv_cmd8 : RO; bitpos: [5]; default: 0; + * The status bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8:1; + /** slv_cmd9 : RO; bitpos: [6]; default: 0; + * The status bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9:1; + /** slv_cmda : RO; bitpos: [7]; default: 0; + * The status bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda:1; + /** slv_rd_dma_done : RO; bitpos: [8]; default: 0; + * The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done:1; + /** slv_wr_dma_done : RO; bitpos: [9]; default: 0; + * The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done:1; + /** slv_rd_buf_done : RO; bitpos: [10]; default: 0; + * The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done:1; + /** slv_wr_buf_done : RO; bitpos: [11]; default: 0; + * The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done:1; + /** trans_done : RO; bitpos: [12]; default: 0; + * The status bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done:1; + /** dma_seg_trans_done : RO; bitpos: [13]; default: 0; + * The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done:1; + /** seg_magic_err : RO; bitpos: [14]; default: 0; + * The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err:1; + /** slv_buf_addr_err : RO; bitpos: [15]; default: 0; + * The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err:1; + /** slv_cmd_err : RO; bitpos: [16]; default: 0; + * The status bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err:1; + /** mst_rx_afifo_wfull_err : RO; bitpos: [17]; default: 0; + * The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err:1; + /** mst_tx_afifo_rempty_err : RO; bitpos: [18]; default: 0; + * The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err:1; + /** app2 : RO; bitpos: [19]; default: 0; + * The status bit for SPI_APP2_INT interrupt. + */ + uint32_t app2:1; + /** app1 : RO; bitpos: [20]; default: 0; + * The status bit for SPI_APP1_INT interrupt. + */ + uint32_t app1:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_st_reg_t; + +/** Type of dma_int_set register + * SPI interrupt software set register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_set : WT; bitpos: [0]; default: 0; + * The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_set:1; + /** dma_outfifo_empty_err_int_set : WT; bitpos: [1]; default: 0; + * The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_set:1; + /** slv_ex_qpi_int_set : WT; bitpos: [2]; default: 0; + * The software set bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_set:1; + /** slv_en_qpi_int_set : WT; bitpos: [3]; default: 0; + * The software set bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_set:1; + /** slv_cmd7_int_set : WT; bitpos: [4]; default: 0; + * The software set bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_set:1; + /** slv_cmd8_int_set : WT; bitpos: [5]; default: 0; + * The software set bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_set:1; + /** slv_cmd9_int_set : WT; bitpos: [6]; default: 0; + * The software set bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_set:1; + /** slv_cmda_int_set : WT; bitpos: [7]; default: 0; + * The software set bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_set:1; + /** slv_rd_dma_done_int_set : WT; bitpos: [8]; default: 0; + * The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_set:1; + /** slv_wr_dma_done_int_set : WT; bitpos: [9]; default: 0; + * The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_set:1; + /** slv_rd_buf_done_int_set : WT; bitpos: [10]; default: 0; + * The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_set:1; + /** slv_wr_buf_done_int_set : WT; bitpos: [11]; default: 0; + * The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_set:1; + /** trans_done_int_set : WT; bitpos: [12]; default: 0; + * The software set bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_set:1; + /** dma_seg_trans_done_int_set : WT; bitpos: [13]; default: 0; + * The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_set:1; + /** seg_magic_err_int_set : WT; bitpos: [14]; default: 0; + * The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_set:1; + /** slv_buf_addr_err_int_set : WT; bitpos: [15]; default: 0; + * The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_set:1; + /** slv_cmd_err_int_set : WT; bitpos: [16]; default: 0; + * The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_set:1; + /** mst_rx_afifo_wfull_err_int_set : WT; bitpos: [17]; default: 0; + * The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_set:1; + /** mst_tx_afifo_rempty_err_int_set : WT; bitpos: [18]; default: 0; + * The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_set:1; + /** app2_int_set : WT; bitpos: [19]; default: 0; + * The software set bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_set:1; + /** app1_int_set : WT; bitpos: [20]; default: 0; + * The software set bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_set:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_set_reg_t; + + +/** Group: CPU-controlled data buffer */ +/** Type of wn register + * SPI CPU-controlled buffer + */ +typedef union { + struct { + /** buf : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf:32; + }; + uint32_t val; +} spi_wn_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35656448; + * SPI register version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_date_reg_t; + + +typedef struct spi_dev_t { + volatile spi_cmd_reg_t cmd; + volatile spi_addr_reg_t addr; + volatile spi_ctrl_reg_t ctrl; + volatile spi_clock_reg_t clock; + volatile spi_user_reg_t user; + volatile spi_user1_reg_t user1; + volatile spi_user2_reg_t user2; + volatile spi_ms_dlen_reg_t ms_dlen; + volatile spi_misc_reg_t misc; + volatile spi_din_mode_reg_t din_mode; + volatile spi_din_num_reg_t din_num; + volatile spi_dout_mode_reg_t dout_mode; + volatile spi_dma_conf_reg_t dma_conf; + volatile spi_dma_int_ena_reg_t dma_int_ena; + volatile spi_dma_int_clr_reg_t dma_int_clr; + volatile spi_dma_int_raw_reg_t dma_int_raw; + volatile spi_dma_int_st_reg_t dma_int_st; + volatile spi_dma_int_set_reg_t dma_int_set; + uint32_t reserved_048[20]; + volatile spi_wn_reg_t data_buf[16]; + uint32_t reserved_0d8[2]; + volatile spi_slave_reg_t slave; + volatile spi_slave1_reg_t slave1; + volatile spi_clk_gate_reg_t clk_gate; + uint32_t reserved_0ec; + volatile spi_date_reg_t date; +} spi_dev_t; + +extern spi_dev_t GPSPI2; + +#ifndef __cplusplus +_Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/system_reg.h b/components/soc/esp32c6/include/soc/system_reg.h new file mode 100644 index 0000000000..4ed6ac2ac2 --- /dev/null +++ b/components/soc/esp32c6/include/soc/system_reg.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/hp_system_reg.h" + +// TODO: IDF-5720 +#include "intpri_reg.h" +#define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG +#define SYSTEM_CPU_INTR_FROM_CPU_0 INTPRI_CPU_INTR_FROM_CPU_0 diff --git a/components/soc/esp32c6/include/soc/systimer_reg.h b/components/soc/esp32c6/include/soc/systimer_reg.h new file mode 100644 index 0000000000..9cccb760cc --- /dev/null +++ b/components/soc/esp32c6/include/soc/systimer_reg.h @@ -0,0 +1,637 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SYSTIMER_CONF_REG register + * Configure system timer clock + */ +#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0) +/** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0; + * systimer clock force on + */ +#define SYSTIMER_SYSTIMER_CLK_FO (BIT(0)) +#define SYSTIMER_SYSTIMER_CLK_FO_M (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S) +#define SYSTIMER_SYSTIMER_CLK_FO_V 0x00000001U +#define SYSTIMER_SYSTIMER_CLK_FO_S 0 +/** SYSTIMER_ETM_EN : R/W; bitpos: [1]; default: 0; + * enable systimer's etm task and event + */ +#define SYSTIMER_ETM_EN (BIT(1)) +#define SYSTIMER_ETM_EN_M (SYSTIMER_ETM_EN_V << SYSTIMER_ETM_EN_S) +#define SYSTIMER_ETM_EN_V 0x00000001U +#define SYSTIMER_ETM_EN_S 1 +/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0; + * target2 work enable + */ +#define SYSTIMER_TARGET2_WORK_EN (BIT(22)) +#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S) +#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001U +#define SYSTIMER_TARGET2_WORK_EN_S 22 +/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0; + * target1 work enable + */ +#define SYSTIMER_TARGET1_WORK_EN (BIT(23)) +#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S) +#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001U +#define SYSTIMER_TARGET1_WORK_EN_S 23 +/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0; + * target0 work enable + */ +#define SYSTIMER_TARGET0_WORK_EN (BIT(24)) +#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S) +#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001U +#define SYSTIMER_TARGET0_WORK_EN_S 24 +/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1; + * If timer unit1 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 +/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1; + * If timer unit1 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 +/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0; + * If timer unit0 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 +/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0; + * If timer unit0 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 +/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0; + * timer unit1 work enable + */ +#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29 +/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1; + * timer unit0 work enable + */ +#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30 +/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ +#define SYSTIMER_CLK_EN (BIT(31)) +#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S) +#define SYSTIMER_CLK_EN_V 0x00000001U +#define SYSTIMER_CLK_EN_S 31 + +/** SYSTIMER_UNIT0_OP_REG register + * system timer unit0 value update register + */ +#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4) +/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0; + * update timer_unit0 + */ +#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S) +#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30 + +/** SYSTIMER_UNIT1_OP_REG register + * system timer unit1 value update register + */ +#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8) +/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0; + * update timer unit1 + */ +#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S) +#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30 + +/** SYSTIMER_UNIT0_LOAD_HI_REG register + * system timer unit0 value high load register + */ +#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc) +/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit0 load high 20 bits + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0 + +/** SYSTIMER_UNIT0_LOAD_LO_REG register + * system timer unit0 value low load register + */ +#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10) +/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit0 load low 32 bits + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0 + +/** SYSTIMER_UNIT1_LOAD_HI_REG register + * system timer unit1 value high load register + */ +#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14) +/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit1 load high 20 bits + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0 + +/** SYSTIMER_UNIT1_LOAD_LO_REG register + * system timer unit1 value low load register + */ +#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18) +/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit1 load low 32 bits + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0 + +/** SYSTIMER_TARGET0_HI_REG register + * system timer comp0 value high register + */ +#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c) +/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget0 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S) +#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET0_HI_S 0 + +/** SYSTIMER_TARGET0_LO_REG register + * system timer comp0 value low register + */ +#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20) +/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget0 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S) +#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET0_LO_S 0 + +/** SYSTIMER_TARGET1_HI_REG register + * system timer comp1 value high register + */ +#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24) +/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget1 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S) +#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET1_HI_S 0 + +/** SYSTIMER_TARGET1_LO_REG register + * system timer comp1 value low register + */ +#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28) +/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget1 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S) +#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET1_LO_S 0 + +/** SYSTIMER_TARGET2_HI_REG register + * system timer comp2 value high register + */ +#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c) +/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget2 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S) +#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET2_HI_S 0 + +/** SYSTIMER_TARGET2_LO_REG register + * system timer comp2 value low register + */ +#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30) +/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget2 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S) +#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET2_LO_S 0 + +/** SYSTIMER_TARGET0_CONF_REG register + * system timer comp0 target mode register + */ +#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34) +/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target0 period + */ +#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFFU +#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S) +#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFFU +#define SYSTIMER_TARGET0_PERIOD_S 0 +/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target0 to period mode + */ +#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S) +#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001U +#define SYSTIMER_TARGET0_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001U +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_TARGET1_CONF_REG register + * system timer comp1 target mode register + */ +#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38) +/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target1 period + */ +#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFFU +#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S) +#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFFU +#define SYSTIMER_TARGET1_PERIOD_S 0 +/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target1 to period mode + */ +#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S) +#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001U +#define SYSTIMER_TARGET1_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001U +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_TARGET2_CONF_REG register + * system timer comp2 target mode register + */ +#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c) +/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target2 period + */ +#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFFU +#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S) +#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFFU +#define SYSTIMER_TARGET2_PERIOD_S 0 +/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target2 to period mode + */ +#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S) +#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001U +#define SYSTIMER_TARGET2_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001U +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_UNIT0_VALUE_HI_REG register + * system timer unit0 value high register + */ +#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40) +/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bits + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0 + +/** SYSTIMER_UNIT0_VALUE_LO_REG register + * system timer unit0 value low register + */ +#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44) +/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bits + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0 + +/** SYSTIMER_UNIT1_VALUE_HI_REG register + * system timer unit1 value high register + */ +#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48) +/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bits + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0 + +/** SYSTIMER_UNIT1_VALUE_LO_REG register + * system timer unit1 value low register + */ +#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c) +/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bits + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0 + +/** SYSTIMER_COMP0_LOAD_REG register + * system timer comp0 conf sync register + */ +#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50) +/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0; + * timer comp0 sync enable signal + */ +#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S) +#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_COMP0_LOAD_S 0 + +/** SYSTIMER_COMP1_LOAD_REG register + * system timer comp1 conf sync register + */ +#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54) +/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0; + * timer comp1 sync enable signal + */ +#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S) +#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_COMP1_LOAD_S 0 + +/** SYSTIMER_COMP2_LOAD_REG register + * system timer comp2 conf sync register + */ +#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58) +/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0; + * timer comp2 sync enable signal + */ +#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S) +#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_COMP2_LOAD_S 0 + +/** SYSTIMER_UNIT0_LOAD_REG register + * system timer unit0 conf sync register + */ +#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c) +/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0; + * timer unit0 sync enable signal + */ +#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_LOAD_S 0 + +/** SYSTIMER_UNIT1_LOAD_REG register + * system timer unit1 conf sync register + */ +#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60) +/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0; + * timer unit1 sync enable signal + */ +#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_LOAD_S 0 + +/** SYSTIMER_INT_ENA_REG register + * systimer interrupt enable register + */ +#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64) +/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0; + * interupt0 enable + */ +#define SYSTIMER_TARGET0_INT_ENA (BIT(0)) +#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S) +#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001U +#define SYSTIMER_TARGET0_INT_ENA_S 0 +/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0; + * interupt1 enable + */ +#define SYSTIMER_TARGET1_INT_ENA (BIT(1)) +#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S) +#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001U +#define SYSTIMER_TARGET1_INT_ENA_S 1 +/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0; + * interupt2 enable + */ +#define SYSTIMER_TARGET2_INT_ENA (BIT(2)) +#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S) +#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001U +#define SYSTIMER_TARGET2_INT_ENA_S 2 + +/** SYSTIMER_INT_RAW_REG register + * systimer interrupt raw register + */ +#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68) +/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * interupt0 raw + */ +#define SYSTIMER_TARGET0_INT_RAW (BIT(0)) +#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S) +#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001U +#define SYSTIMER_TARGET0_INT_RAW_S 0 +/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * interupt1 raw + */ +#define SYSTIMER_TARGET1_INT_RAW (BIT(1)) +#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S) +#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001U +#define SYSTIMER_TARGET1_INT_RAW_S 1 +/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * interupt2 raw + */ +#define SYSTIMER_TARGET2_INT_RAW (BIT(2)) +#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S) +#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001U +#define SYSTIMER_TARGET2_INT_RAW_S 2 + +/** SYSTIMER_INT_CLR_REG register + * systimer interrupt clear register + */ +#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c) +/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0; + * interupt0 clear + */ +#define SYSTIMER_TARGET0_INT_CLR (BIT(0)) +#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S) +#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001U +#define SYSTIMER_TARGET0_INT_CLR_S 0 +/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0; + * interupt1 clear + */ +#define SYSTIMER_TARGET1_INT_CLR (BIT(1)) +#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S) +#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001U +#define SYSTIMER_TARGET1_INT_CLR_S 1 +/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0; + * interupt2 clear + */ +#define SYSTIMER_TARGET2_INT_CLR (BIT(2)) +#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S) +#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001U +#define SYSTIMER_TARGET2_INT_CLR_S 2 + +/** SYSTIMER_INT_ST_REG register + * systimer interrupt status register + */ +#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70) +/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0; + * interupt0 status + */ +#define SYSTIMER_TARGET0_INT_ST (BIT(0)) +#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S) +#define SYSTIMER_TARGET0_INT_ST_V 0x00000001U +#define SYSTIMER_TARGET0_INT_ST_S 0 +/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0; + * interupt1 status + */ +#define SYSTIMER_TARGET1_INT_ST (BIT(1)) +#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S) +#define SYSTIMER_TARGET1_INT_ST_V 0x00000001U +#define SYSTIMER_TARGET1_INT_ST_S 1 +/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0; + * interupt2 status + */ +#define SYSTIMER_TARGET2_INT_ST (BIT(2)) +#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S) +#define SYSTIMER_TARGET2_INT_ST_V 0x00000001U +#define SYSTIMER_TARGET2_INT_ST_S 2 + +/** SYSTIMER_REAL_TARGET0_LO_REG register + * system timer comp0 actual target value low register + */ +#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74) +/** SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ +#define SYSTIMER_TARGET0_LO_RO 0xFFFFFFFFU +#define SYSTIMER_TARGET0_LO_RO_M (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S) +#define SYSTIMER_TARGET0_LO_RO_V 0xFFFFFFFFU +#define SYSTIMER_TARGET0_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET0_HI_REG register + * system timer comp0 actual target value high register + */ +#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78) +/** SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ +#define SYSTIMER_TARGET0_HI_RO 0x000FFFFFU +#define SYSTIMER_TARGET0_HI_RO_M (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S) +#define SYSTIMER_TARGET0_HI_RO_V 0x000FFFFFU +#define SYSTIMER_TARGET0_HI_RO_S 0 + +/** SYSTIMER_REAL_TARGET1_LO_REG register + * system timer comp1 actual target value low register + */ +#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c) +/** SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ +#define SYSTIMER_TARGET1_LO_RO 0xFFFFFFFFU +#define SYSTIMER_TARGET1_LO_RO_M (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S) +#define SYSTIMER_TARGET1_LO_RO_V 0xFFFFFFFFU +#define SYSTIMER_TARGET1_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET1_HI_REG register + * system timer comp1 actual target value high register + */ +#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80) +/** SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ +#define SYSTIMER_TARGET1_HI_RO 0x000FFFFFU +#define SYSTIMER_TARGET1_HI_RO_M (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S) +#define SYSTIMER_TARGET1_HI_RO_V 0x000FFFFFU +#define SYSTIMER_TARGET1_HI_RO_S 0 + +/** SYSTIMER_REAL_TARGET2_LO_REG register + * system timer comp2 actual target value low register + */ +#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84) +/** SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ +#define SYSTIMER_TARGET2_LO_RO 0xFFFFFFFFU +#define SYSTIMER_TARGET2_LO_RO_M (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S) +#define SYSTIMER_TARGET2_LO_RO_V 0xFFFFFFFFU +#define SYSTIMER_TARGET2_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET2_HI_REG register + * system timer comp2 actual target value high register + */ +#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88) +/** SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ +#define SYSTIMER_TARGET2_HI_RO 0x000FFFFFU +#define SYSTIMER_TARGET2_HI_RO_M (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S) +#define SYSTIMER_TARGET2_HI_RO_V 0x000FFFFFU +#define SYSTIMER_TARGET2_HI_RO_S 0 + +/** SYSTIMER_DATE_REG register + * system timer version control register + */ +#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc) +/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 35655795; + * systimer register version + */ +#define SYSTIMER_DATE 0xFFFFFFFFU +#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S) +#define SYSTIMER_DATE_V 0xFFFFFFFFU +#define SYSTIMER_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/systimer_struct.h b/components/soc/esp32c6/include/soc/systimer_struct.h new file mode 100644 index 0000000000..0e0e1f8f34 --- /dev/null +++ b/components/soc/esp32c6/include/soc/systimer_struct.h @@ -0,0 +1,379 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: SYSTEM TIMER CLK CONTROL REGISTER */ +/** Type of conf register + * Configure system timer clock + */ +typedef union { + struct { + /** systimer_clk_fo : R/W; bitpos: [0]; default: 0; + * systimer clock force on + */ + uint32_t systimer_clk_fo:1; + /** etm_en : R/W; bitpos: [1]; default: 0; + * enable systimer's etm task and event + */ + uint32_t etm_en:1; + uint32_t reserved_2:20; + /** target2_work_en : R/W; bitpos: [22]; default: 0; + * target2 work enable + */ + uint32_t target2_work_en:1; + /** target1_work_en : R/W; bitpos: [23]; default: 0; + * target1 work enable + */ + uint32_t target1_work_en:1; + /** target0_work_en : R/W; bitpos: [24]; default: 0; + * target0 work enable + */ + uint32_t target0_work_en:1; + /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1; + * If timer unit1 is stalled when core1 stalled + */ + uint32_t timer_unit1_core1_stall_en:1; + /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1; + * If timer unit1 is stalled when core0 stalled + */ + uint32_t timer_unit1_core0_stall_en:1; + /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0; + * If timer unit0 is stalled when core1 stalled + */ + uint32_t timer_unit0_core1_stall_en:1; + /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0; + * If timer unit0 is stalled when core0 stalled + */ + uint32_t timer_unit0_core0_stall_en:1; + /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0; + * timer unit1 work enable + */ + uint32_t timer_unit1_work_en:1; + /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1; + * timer unit0 work enable + */ + uint32_t timer_unit0_work_en:1; + /** clk_en : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ + uint32_t clk_en:1; + }; + uint32_t val; +} systimer_conf_reg_t; + + +/** Group: SYSTEM TIMER UNIT CONTROL AND CONFIGURATION REGISTER */ +/** Type of unit_op register + * system timer unit value update register + */ +typedef union { + struct { + uint32_t reserved_0: 29; + /** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ + uint32_t timer_unit_value_valid: 1; + /** timer_unit_update : WT; bitpos: [30]; default: 0; + * update timer_unit + */ + uint32_t timer_unit_update: 1; + uint32_t reserved31: 1; + }; + uint32_t val; +} systimer_unit_op_reg_t; + +/** Type of unit_load register + * system timer unit value high and low load register + */ +typedef struct { + union { + struct { + /** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0; + * timer unit load high 20 bit + */ + uint32_t timer_unit_load_hi: 20; + uint32_t reserved20: 12; + }; + uint32_t val; + } hi; + union { + struct { + /** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0; + * timer unit load low 32 bit + */ + uint32_t timer_unit_load_lo: 32; + }; + uint32_t val; + } lo; +} systimer_unit_load_val_reg_t; + +/** Type of unit_value_hi register + * system timer unit value high and low register + */ +typedef struct { + union { + struct { + /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0; + * timer read value high 20 bit + */ + uint32_t timer_unit_value_hi: 20; + uint32_t reserved20: 12; + }; + uint32_t val; + } hi; + union { + struct { + /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0; + * timer read value low 32 bit + */ + uint32_t timer_unit_value_lo: 32; + }; + uint32_t val; + } lo; +} systimer_unit_value_reg_t; + +/** Type of unit_load register + * system timer unit conf sync register + */ +typedef union { + struct { + /** timer_unit_load : WT; bitpos: [0]; default: 0; + * timer unit load value + */ + uint32_t timer_unit_load: 1; + uint32_t reserved1: 31; + }; + uint32_t val; +} systimer_unit_load_reg_t; + + +/** Group: SYSTEM TIMER COMP CONTROL AND CONFIGURATION REGISTER */ +/** Type of target register + * system timer comp value high and low register + */ +typedef struct { + union { + struct { + /** timer_target_hi : R/W; bitpos: [19:0]; default: 0; + * timer target high 20 bit + */ + uint32_t timer_target_hi: 20; + uint32_t reserved20: 12; + }; + uint32_t val; + } hi; + union { + struct { + /** timer_target_lo : R/W; bitpos: [31:0]; default: 0; + * timer target low 32 bit + */ + uint32_t timer_target_lo: 32; + }; + uint32_t val; + } lo; +} systimer_target_val_reg_t; + +/** Type of target_conf register + * system timer comp target mode register + */ +typedef union { + struct { + /** target_period : R/W; bitpos: [25:0]; default: 0; + * target period + */ + uint32_t target_period: 26; + uint32_t reserved_26: 4; + /** target_period_mode : R/W; bitpos: [30]; default: 0; + * Set target to period mode + */ + uint32_t target_period_mode: 1; + /** target_timer_unit_sel : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ + uint32_t target_timer_unit_sel: 1; + }; + uint32_t val; +} systimer_target_conf_reg_t; + +/** Type of comp_load register + * system timer comp conf sync register + */ +typedef union { + struct { + /** timer_comp_load : WT; bitpos: [0]; default: 0; + * timer comp sync enable signal + */ + uint32_t timer_comp_load: 1; + uint32_t reserved1: 31; + }; + uint32_t val; +} systimer_comp_load_reg_t; + + +/** Group: SYSTEM TIMER INTERRUPT REGISTER */ +/** Type of int_ena register + * systimer interrupt enable register + */ +typedef union { + struct { + /** target0_int_ena : R/W; bitpos: [0]; default: 0; + * interupt0 enable + */ + uint32_t target0_int_ena:1; + /** target1_int_ena : R/W; bitpos: [1]; default: 0; + * interupt1 enable + */ + uint32_t target1_int_ena:1; + /** target2_int_ena : R/W; bitpos: [2]; default: 0; + * interupt2 enable + */ + uint32_t target2_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_ena_reg_t; + +/** Type of int_raw register + * systimer interrupt raw register + */ +typedef union { + struct { + /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * interupt0 raw + */ + uint32_t target0_int_raw:1; + /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * interupt1 raw + */ + uint32_t target1_int_raw:1; + /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * interupt2 raw + */ + uint32_t target2_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_raw_reg_t; + +/** Type of int_clr register + * systimer interrupt clear register + */ +typedef union { + struct { + /** target0_int_clr : WT; bitpos: [0]; default: 0; + * interupt0 clear + */ + uint32_t target0_int_clr:1; + /** target1_int_clr : WT; bitpos: [1]; default: 0; + * interupt1 clear + */ + uint32_t target1_int_clr:1; + /** target2_int_clr : WT; bitpos: [2]; default: 0; + * interupt2 clear + */ + uint32_t target2_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_clr_reg_t; + +/** Type of int_st register + * systimer interrupt status register + */ +typedef union { + struct { + /** target0_int_st : RO; bitpos: [0]; default: 0; + * interupt0 status + */ + uint32_t target0_int_st:1; + /** target1_int_st : RO; bitpos: [1]; default: 0; + * interupt1 status + */ + uint32_t target1_int_st:1; + /** target2_int_st : RO; bitpos: [2]; default: 0; + * interupt2 status + */ + uint32_t target2_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_st_reg_t; + + +/** Group: SYSTEM TIMER COMP STATUS REGISTER */ +/** Type of real_target_hi/lo register + * system timer comp actual target value low register + */ +typedef struct { + union { + struct { + /** target_lo_ro : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32 bits + */ + uint32_t target_lo_ro: 32; + }; + uint32_t val; + } lo; + union { + struct { + /** target_hi_ro : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20 bits + */ + uint32_t target_hi_ro: 20; + uint32_t reserved20: 12; + }; + uint32_t val; + } hi; +} systimer_real_target_reg_t; + + +/** Group: VERSION REGISTER */ +/** Type of date register + * system timer version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35655795; + * systimer register version + */ + uint32_t date: 32; + }; + uint32_t val; +} systimer_date_reg_t; + + +typedef struct systimer_dev_t { + volatile systimer_conf_reg_t conf; + volatile systimer_unit_op_reg_t unit_op[2]; + volatile systimer_unit_load_val_reg_t unit_load_val[2]; + volatile systimer_target_val_reg_t target_val[3]; + volatile systimer_target_conf_reg_t target_conf[3]; + volatile systimer_unit_value_reg_t unit_val[2]; + volatile systimer_comp_load_reg_t comp_load[3]; + volatile systimer_unit_load_reg_t unit_load[2]; + volatile systimer_int_ena_reg_t int_ena; + volatile systimer_int_raw_reg_t int_raw; + volatile systimer_int_clr_reg_t int_clr; + volatile systimer_int_st_reg_t int_st; + volatile systimer_real_target_reg_t real_target[3]; + uint32_t reserved_08c[28]; + volatile systimer_date_reg_t date; +} systimer_dev_t; + +extern systimer_dev_t SYSTIMER; + +#ifndef __cplusplus +_Static_assert(sizeof(systimer_dev_t) == 0x100, "Invalid size of systimer_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/tee_reg.h b/components/soc/esp32c6/include/soc/tee_reg.h new file mode 100644 index 0000000000..fd340089ee --- /dev/null +++ b/components/soc/esp32c6/include/soc/tee_reg.h @@ -0,0 +1,456 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TEE_M0_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M0_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x0) +/** TEE_M0_MODE : R/W; bitpos: [1:0]; default: 0; + * M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M0_MODE 0x00000003U +#define TEE_M0_MODE_M (TEE_M0_MODE_V << TEE_M0_MODE_S) +#define TEE_M0_MODE_V 0x00000003U +#define TEE_M0_MODE_S 0 + +/** TEE_M1_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M1_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4) +/** TEE_M1_MODE : R/W; bitpos: [1:0]; default: 3; + * M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M1_MODE 0x00000003U +#define TEE_M1_MODE_M (TEE_M1_MODE_V << TEE_M1_MODE_S) +#define TEE_M1_MODE_V 0x00000003U +#define TEE_M1_MODE_S 0 + +/** TEE_M2_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M2_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x8) +/** TEE_M2_MODE : R/W; bitpos: [1:0]; default: 0; + * M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M2_MODE 0x00000003U +#define TEE_M2_MODE_M (TEE_M2_MODE_V << TEE_M2_MODE_S) +#define TEE_M2_MODE_V 0x00000003U +#define TEE_M2_MODE_S 0 + +/** TEE_M3_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M3_MODE_CTRL_REG (DR_REG_TEE_BASE + 0xc) +/** TEE_M3_MODE : R/W; bitpos: [1:0]; default: 3; + * M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M3_MODE 0x00000003U +#define TEE_M3_MODE_M (TEE_M3_MODE_V << TEE_M3_MODE_S) +#define TEE_M3_MODE_V 0x00000003U +#define TEE_M3_MODE_S 0 + +/** TEE_M4_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M4_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x10) +/** TEE_M4_MODE : R/W; bitpos: [1:0]; default: 3; + * M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M4_MODE 0x00000003U +#define TEE_M4_MODE_M (TEE_M4_MODE_V << TEE_M4_MODE_S) +#define TEE_M4_MODE_V 0x00000003U +#define TEE_M4_MODE_S 0 + +/** TEE_M5_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M5_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x14) +/** TEE_M5_MODE : R/W; bitpos: [1:0]; default: 3; + * M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M5_MODE 0x00000003U +#define TEE_M5_MODE_M (TEE_M5_MODE_V << TEE_M5_MODE_S) +#define TEE_M5_MODE_V 0x00000003U +#define TEE_M5_MODE_S 0 + +/** TEE_M6_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M6_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x18) +/** TEE_M6_MODE : R/W; bitpos: [1:0]; default: 3; + * M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M6_MODE 0x00000003U +#define TEE_M6_MODE_M (TEE_M6_MODE_V << TEE_M6_MODE_S) +#define TEE_M6_MODE_V 0x00000003U +#define TEE_M6_MODE_S 0 + +/** TEE_M7_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M7_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x1c) +/** TEE_M7_MODE : R/W; bitpos: [1:0]; default: 3; + * M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M7_MODE 0x00000003U +#define TEE_M7_MODE_M (TEE_M7_MODE_V << TEE_M7_MODE_S) +#define TEE_M7_MODE_V 0x00000003U +#define TEE_M7_MODE_S 0 + +/** TEE_M8_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M8_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x20) +/** TEE_M8_MODE : R/W; bitpos: [1:0]; default: 3; + * M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M8_MODE 0x00000003U +#define TEE_M8_MODE_M (TEE_M8_MODE_V << TEE_M8_MODE_S) +#define TEE_M8_MODE_V 0x00000003U +#define TEE_M8_MODE_S 0 + +/** TEE_M9_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M9_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x24) +/** TEE_M9_MODE : R/W; bitpos: [1:0]; default: 3; + * M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M9_MODE 0x00000003U +#define TEE_M9_MODE_M (TEE_M9_MODE_V << TEE_M9_MODE_S) +#define TEE_M9_MODE_V 0x00000003U +#define TEE_M9_MODE_S 0 + +/** TEE_M10_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M10_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x28) +/** TEE_M10_MODE : R/W; bitpos: [1:0]; default: 3; + * M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M10_MODE 0x00000003U +#define TEE_M10_MODE_M (TEE_M10_MODE_V << TEE_M10_MODE_S) +#define TEE_M10_MODE_V 0x00000003U +#define TEE_M10_MODE_S 0 + +/** TEE_M11_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M11_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x2c) +/** TEE_M11_MODE : R/W; bitpos: [1:0]; default: 3; + * M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M11_MODE 0x00000003U +#define TEE_M11_MODE_M (TEE_M11_MODE_V << TEE_M11_MODE_S) +#define TEE_M11_MODE_V 0x00000003U +#define TEE_M11_MODE_S 0 + +/** TEE_M12_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M12_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x30) +/** TEE_M12_MODE : R/W; bitpos: [1:0]; default: 3; + * M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M12_MODE 0x00000003U +#define TEE_M12_MODE_M (TEE_M12_MODE_V << TEE_M12_MODE_S) +#define TEE_M12_MODE_V 0x00000003U +#define TEE_M12_MODE_S 0 + +/** TEE_M13_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M13_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x34) +/** TEE_M13_MODE : R/W; bitpos: [1:0]; default: 3; + * M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M13_MODE 0x00000003U +#define TEE_M13_MODE_M (TEE_M13_MODE_V << TEE_M13_MODE_S) +#define TEE_M13_MODE_V 0x00000003U +#define TEE_M13_MODE_S 0 + +/** TEE_M14_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M14_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x38) +/** TEE_M14_MODE : R/W; bitpos: [1:0]; default: 3; + * M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M14_MODE 0x00000003U +#define TEE_M14_MODE_M (TEE_M14_MODE_V << TEE_M14_MODE_S) +#define TEE_M14_MODE_V 0x00000003U +#define TEE_M14_MODE_S 0 + +/** TEE_M15_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M15_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x3c) +/** TEE_M15_MODE : R/W; bitpos: [1:0]; default: 3; + * M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M15_MODE 0x00000003U +#define TEE_M15_MODE_M (TEE_M15_MODE_V << TEE_M15_MODE_S) +#define TEE_M15_MODE_V 0x00000003U +#define TEE_M15_MODE_S 0 + +/** TEE_M16_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M16_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x40) +/** TEE_M16_MODE : R/W; bitpos: [1:0]; default: 3; + * M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M16_MODE 0x00000003U +#define TEE_M16_MODE_M (TEE_M16_MODE_V << TEE_M16_MODE_S) +#define TEE_M16_MODE_V 0x00000003U +#define TEE_M16_MODE_S 0 + +/** TEE_M17_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M17_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x44) +/** TEE_M17_MODE : R/W; bitpos: [1:0]; default: 3; + * M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M17_MODE 0x00000003U +#define TEE_M17_MODE_M (TEE_M17_MODE_V << TEE_M17_MODE_S) +#define TEE_M17_MODE_V 0x00000003U +#define TEE_M17_MODE_S 0 + +/** TEE_M18_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M18_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x48) +/** TEE_M18_MODE : R/W; bitpos: [1:0]; default: 3; + * M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M18_MODE 0x00000003U +#define TEE_M18_MODE_M (TEE_M18_MODE_V << TEE_M18_MODE_S) +#define TEE_M18_MODE_V 0x00000003U +#define TEE_M18_MODE_S 0 + +/** TEE_M19_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M19_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4c) +/** TEE_M19_MODE : R/W; bitpos: [1:0]; default: 3; + * M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M19_MODE 0x00000003U +#define TEE_M19_MODE_M (TEE_M19_MODE_V << TEE_M19_MODE_S) +#define TEE_M19_MODE_V 0x00000003U +#define TEE_M19_MODE_S 0 + +/** TEE_M20_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M20_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x50) +/** TEE_M20_MODE : R/W; bitpos: [1:0]; default: 3; + * M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M20_MODE 0x00000003U +#define TEE_M20_MODE_M (TEE_M20_MODE_V << TEE_M20_MODE_S) +#define TEE_M20_MODE_V 0x00000003U +#define TEE_M20_MODE_S 0 + +/** TEE_M21_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M21_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x54) +/** TEE_M21_MODE : R/W; bitpos: [1:0]; default: 3; + * M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M21_MODE 0x00000003U +#define TEE_M21_MODE_M (TEE_M21_MODE_V << TEE_M21_MODE_S) +#define TEE_M21_MODE_V 0x00000003U +#define TEE_M21_MODE_S 0 + +/** TEE_M22_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M22_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x58) +/** TEE_M22_MODE : R/W; bitpos: [1:0]; default: 3; + * M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M22_MODE 0x00000003U +#define TEE_M22_MODE_M (TEE_M22_MODE_V << TEE_M22_MODE_S) +#define TEE_M22_MODE_V 0x00000003U +#define TEE_M22_MODE_S 0 + +/** TEE_M23_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M23_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x5c) +/** TEE_M23_MODE : R/W; bitpos: [1:0]; default: 3; + * M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M23_MODE 0x00000003U +#define TEE_M23_MODE_M (TEE_M23_MODE_V << TEE_M23_MODE_S) +#define TEE_M23_MODE_V 0x00000003U +#define TEE_M23_MODE_S 0 + +/** TEE_M24_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M24_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x60) +/** TEE_M24_MODE : R/W; bitpos: [1:0]; default: 3; + * M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M24_MODE 0x00000003U +#define TEE_M24_MODE_M (TEE_M24_MODE_V << TEE_M24_MODE_S) +#define TEE_M24_MODE_V 0x00000003U +#define TEE_M24_MODE_S 0 + +/** TEE_M25_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M25_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x64) +/** TEE_M25_MODE : R/W; bitpos: [1:0]; default: 3; + * M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M25_MODE 0x00000003U +#define TEE_M25_MODE_M (TEE_M25_MODE_V << TEE_M25_MODE_S) +#define TEE_M25_MODE_V 0x00000003U +#define TEE_M25_MODE_S 0 + +/** TEE_M26_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M26_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x68) +/** TEE_M26_MODE : R/W; bitpos: [1:0]; default: 3; + * M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M26_MODE 0x00000003U +#define TEE_M26_MODE_M (TEE_M26_MODE_V << TEE_M26_MODE_S) +#define TEE_M26_MODE_V 0x00000003U +#define TEE_M26_MODE_S 0 + +/** TEE_M27_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M27_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x6c) +/** TEE_M27_MODE : R/W; bitpos: [1:0]; default: 3; + * M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M27_MODE 0x00000003U +#define TEE_M27_MODE_M (TEE_M27_MODE_V << TEE_M27_MODE_S) +#define TEE_M27_MODE_V 0x00000003U +#define TEE_M27_MODE_S 0 + +/** TEE_M28_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M28_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x70) +/** TEE_M28_MODE : R/W; bitpos: [1:0]; default: 3; + * M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M28_MODE 0x00000003U +#define TEE_M28_MODE_M (TEE_M28_MODE_V << TEE_M28_MODE_S) +#define TEE_M28_MODE_V 0x00000003U +#define TEE_M28_MODE_S 0 + +/** TEE_M29_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M29_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x74) +/** TEE_M29_MODE : R/W; bitpos: [1:0]; default: 3; + * M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M29_MODE 0x00000003U +#define TEE_M29_MODE_M (TEE_M29_MODE_V << TEE_M29_MODE_S) +#define TEE_M29_MODE_V 0x00000003U +#define TEE_M29_MODE_S 0 + +/** TEE_M30_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M30_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x78) +/** TEE_M30_MODE : R/W; bitpos: [1:0]; default: 3; + * M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M30_MODE 0x00000003U +#define TEE_M30_MODE_M (TEE_M30_MODE_V << TEE_M30_MODE_S) +#define TEE_M30_MODE_V 0x00000003U +#define TEE_M30_MODE_S 0 + +/** TEE_M31_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M31_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x7c) +/** TEE_M31_MODE : R/W; bitpos: [1:0]; default: 3; + * M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M31_MODE 0x00000003U +#define TEE_M31_MODE_M (TEE_M31_MODE_V << TEE_M31_MODE_S) +#define TEE_M31_MODE_V 0x00000003U +#define TEE_M31_MODE_S 0 + +/** TEE_CLOCK_GATE_REG register + * Clock gating register + */ +#define TEE_CLOCK_GATE_REG (DR_REG_TEE_BASE + 0x80) +/** TEE_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define TEE_CLK_EN (BIT(0)) +#define TEE_CLK_EN_M (TEE_CLK_EN_V << TEE_CLK_EN_S) +#define TEE_CLK_EN_V 0x00000001U +#define TEE_CLK_EN_S 0 + +/** TEE_DATE_REG register + * Version register + */ +#define TEE_DATE_REG (DR_REG_TEE_BASE + 0xffc) +/** TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35672706; + * reg_tee_date + */ +#define TEE_DATE_REG 0x0FFFFFFFU +#define TEE_DATE_REG_M (TEE_DATE_REG_V << TEE_DATE_REG_S) +#define TEE_DATE_REG_V 0x0FFFFFFFU +#define TEE_DATE_REG_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/tee_struct.h b/components/soc/esp32c6/include/soc/tee_struct.h new file mode 100644 index 0000000000..576bde7ec1 --- /dev/null +++ b/components/soc/esp32c6/include/soc/tee_struct.h @@ -0,0 +1,573 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Tee mode control register */ +/** Type of m0_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m0_mode : R/W; bitpos: [1:0]; default: 0; + * M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m0_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m0_mode_ctrl_reg_t; + +/** Type of m1_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m1_mode : R/W; bitpos: [1:0]; default: 3; + * M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m1_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m1_mode_ctrl_reg_t; + +/** Type of m2_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m2_mode : R/W; bitpos: [1:0]; default: 0; + * M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m2_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m2_mode_ctrl_reg_t; + +/** Type of m3_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m3_mode : R/W; bitpos: [1:0]; default: 3; + * M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m3_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m3_mode_ctrl_reg_t; + +/** Type of m4_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m4_mode : R/W; bitpos: [1:0]; default: 3; + * M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m4_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m4_mode_ctrl_reg_t; + +/** Type of m5_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m5_mode : R/W; bitpos: [1:0]; default: 3; + * M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m5_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m5_mode_ctrl_reg_t; + +/** Type of m6_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m6_mode : R/W; bitpos: [1:0]; default: 3; + * M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m6_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m6_mode_ctrl_reg_t; + +/** Type of m7_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m7_mode : R/W; bitpos: [1:0]; default: 3; + * M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m7_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m7_mode_ctrl_reg_t; + +/** Type of m8_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m8_mode : R/W; bitpos: [1:0]; default: 3; + * M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m8_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m8_mode_ctrl_reg_t; + +/** Type of m9_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m9_mode : R/W; bitpos: [1:0]; default: 3; + * M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m9_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m9_mode_ctrl_reg_t; + +/** Type of m10_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m10_mode : R/W; bitpos: [1:0]; default: 3; + * M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m10_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m10_mode_ctrl_reg_t; + +/** Type of m11_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m11_mode : R/W; bitpos: [1:0]; default: 3; + * M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m11_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m11_mode_ctrl_reg_t; + +/** Type of m12_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m12_mode : R/W; bitpos: [1:0]; default: 3; + * M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m12_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m12_mode_ctrl_reg_t; + +/** Type of m13_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m13_mode : R/W; bitpos: [1:0]; default: 3; + * M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m13_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m13_mode_ctrl_reg_t; + +/** Type of m14_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m14_mode : R/W; bitpos: [1:0]; default: 3; + * M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m14_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m14_mode_ctrl_reg_t; + +/** Type of m15_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m15_mode : R/W; bitpos: [1:0]; default: 3; + * M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m15_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m15_mode_ctrl_reg_t; + +/** Type of m16_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m16_mode : R/W; bitpos: [1:0]; default: 3; + * M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m16_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m16_mode_ctrl_reg_t; + +/** Type of m17_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m17_mode : R/W; bitpos: [1:0]; default: 3; + * M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m17_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m17_mode_ctrl_reg_t; + +/** Type of m18_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m18_mode : R/W; bitpos: [1:0]; default: 3; + * M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m18_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m18_mode_ctrl_reg_t; + +/** Type of m19_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m19_mode : R/W; bitpos: [1:0]; default: 3; + * M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m19_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m19_mode_ctrl_reg_t; + +/** Type of m20_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m20_mode : R/W; bitpos: [1:0]; default: 3; + * M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m20_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m20_mode_ctrl_reg_t; + +/** Type of m21_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m21_mode : R/W; bitpos: [1:0]; default: 3; + * M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m21_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m21_mode_ctrl_reg_t; + +/** Type of m22_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m22_mode : R/W; bitpos: [1:0]; default: 3; + * M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m22_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m22_mode_ctrl_reg_t; + +/** Type of m23_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m23_mode : R/W; bitpos: [1:0]; default: 3; + * M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m23_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m23_mode_ctrl_reg_t; + +/** Type of m24_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m24_mode : R/W; bitpos: [1:0]; default: 3; + * M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m24_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m24_mode_ctrl_reg_t; + +/** Type of m25_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m25_mode : R/W; bitpos: [1:0]; default: 3; + * M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m25_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m25_mode_ctrl_reg_t; + +/** Type of m26_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m26_mode : R/W; bitpos: [1:0]; default: 3; + * M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m26_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m26_mode_ctrl_reg_t; + +/** Type of m27_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m27_mode : R/W; bitpos: [1:0]; default: 3; + * M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m27_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m27_mode_ctrl_reg_t; + +/** Type of m28_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m28_mode : R/W; bitpos: [1:0]; default: 3; + * M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m28_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m28_mode_ctrl_reg_t; + +/** Type of m29_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m29_mode : R/W; bitpos: [1:0]; default: 3; + * M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m29_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m29_mode_ctrl_reg_t; + +/** Type of m30_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m30_mode : R/W; bitpos: [1:0]; default: 3; + * M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m30_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m30_mode_ctrl_reg_t; + +/** Type of m31_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m31_mode : R/W; bitpos: [1:0]; default: 3; + * M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m31_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} tee_m31_mode_ctrl_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * Clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tee_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date_reg : R/W; bitpos: [27:0]; default: 35672706; + * reg_tee_date + */ + uint32_t date_reg:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} tee_date_reg_t; + + +typedef struct tee_dev_t { + volatile tee_m0_mode_ctrl_reg_t m0_mode_ctrl; + volatile tee_m1_mode_ctrl_reg_t m1_mode_ctrl; + volatile tee_m2_mode_ctrl_reg_t m2_mode_ctrl; + volatile tee_m3_mode_ctrl_reg_t m3_mode_ctrl; + volatile tee_m4_mode_ctrl_reg_t m4_mode_ctrl; + volatile tee_m5_mode_ctrl_reg_t m5_mode_ctrl; + volatile tee_m6_mode_ctrl_reg_t m6_mode_ctrl; + volatile tee_m7_mode_ctrl_reg_t m7_mode_ctrl; + volatile tee_m8_mode_ctrl_reg_t m8_mode_ctrl; + volatile tee_m9_mode_ctrl_reg_t m9_mode_ctrl; + volatile tee_m10_mode_ctrl_reg_t m10_mode_ctrl; + volatile tee_m11_mode_ctrl_reg_t m11_mode_ctrl; + volatile tee_m12_mode_ctrl_reg_t m12_mode_ctrl; + volatile tee_m13_mode_ctrl_reg_t m13_mode_ctrl; + volatile tee_m14_mode_ctrl_reg_t m14_mode_ctrl; + volatile tee_m15_mode_ctrl_reg_t m15_mode_ctrl; + volatile tee_m16_mode_ctrl_reg_t m16_mode_ctrl; + volatile tee_m17_mode_ctrl_reg_t m17_mode_ctrl; + volatile tee_m18_mode_ctrl_reg_t m18_mode_ctrl; + volatile tee_m19_mode_ctrl_reg_t m19_mode_ctrl; + volatile tee_m20_mode_ctrl_reg_t m20_mode_ctrl; + volatile tee_m21_mode_ctrl_reg_t m21_mode_ctrl; + volatile tee_m22_mode_ctrl_reg_t m22_mode_ctrl; + volatile tee_m23_mode_ctrl_reg_t m23_mode_ctrl; + volatile tee_m24_mode_ctrl_reg_t m24_mode_ctrl; + volatile tee_m25_mode_ctrl_reg_t m25_mode_ctrl; + volatile tee_m26_mode_ctrl_reg_t m26_mode_ctrl; + volatile tee_m27_mode_ctrl_reg_t m27_mode_ctrl; + volatile tee_m28_mode_ctrl_reg_t m28_mode_ctrl; + volatile tee_m29_mode_ctrl_reg_t m29_mode_ctrl; + volatile tee_m30_mode_ctrl_reg_t m30_mode_ctrl; + volatile tee_m31_mode_ctrl_reg_t m31_mode_ctrl; + volatile tee_clock_gate_reg_t clock_gate; + uint32_t reserved_084[990]; + volatile tee_date_reg_t date; +} tee_dev_t; + +extern tee_dev_t TEE; + +#ifndef __cplusplus +_Static_assert(sizeof(tee_dev_t) == 0x1000, "Invalid size of tee_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/timer_group_reg.h b/components/soc/esp32c6/include/soc/timer_group_reg.h new file mode 100644 index 0000000000..df5c8ffb32 --- /dev/null +++ b/components/soc/esp32c6/include/soc/timer_group_reg.h @@ -0,0 +1,591 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */ +#define TIMG_WDT_WKEY_VALUE 0x50D83AA1 + +/* Possible values for TIMG_WDT_STGx */ +#define TIMG_WDT_STG_SEL_OFF 0 +#define TIMG_WDT_STG_SEL_INT 1 +#define TIMG_WDT_STG_SEL_RESET_CPU 2 +#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3 + +#define TIMG_WDT_RESET_LENGTH_100_NS 0 +#define TIMG_WDT_RESET_LENGTH_200_NS 1 +#define TIMG_WDT_RESET_LENGTH_300_NS 2 +#define TIMG_WDT_RESET_LENGTH_400_NS 3 +#define TIMG_WDT_RESET_LENGTH_500_NS 4 +#define TIMG_WDT_RESET_LENGTH_800_NS 5 +#define TIMG_WDT_RESET_LENGTH_1600_NS 6 +#define TIMG_WDT_RESET_LENGTH_3200_NS 7 +/* Possible values for TIMG_WDT_STGx */ +#define TIMG_WDT_STG_SEL_OFF 0 +#define TIMG_WDT_STG_SEL_INT 1 +#define TIMG_WDT_STG_SEL_RESET_CPU 2 +#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3 + + +/** TIMG_T0CONFIG_REG register + * Timer 0 configuration register + */ +#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0) +/** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0; + * 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source + * clock of timer group. + */ +#define TIMG_T0_USE_XTAL (BIT(9)) +#define TIMG_T0_USE_XTAL_M (TIMG_T0_USE_XTAL_V << TIMG_T0_USE_XTAL_S) +#define TIMG_T0_USE_XTAL_V 0x00000001U +#define TIMG_T0_USE_XTAL_S 9 +/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0; + * When set, the alarm is enabled. This bit is automatically cleared once an + * alarm occurs. + */ +#define TIMG_T0_ALARM_EN (BIT(10)) +#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S) +#define TIMG_T0_ALARM_EN_V 0x00000001U +#define TIMG_T0_ALARM_EN_S 10 +/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0; + * When set, Timer 0 's clock divider counter will be reset. + */ +#define TIMG_T0_DIVCNT_RST (BIT(12)) +#define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S) +#define TIMG_T0_DIVCNT_RST_V 0x00000001U +#define TIMG_T0_DIVCNT_RST_S 12 +/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1; + * Timer 0 clock (T0_clk) prescaler value. + */ +#define TIMG_T0_DIVIDER 0x0000FFFFU +#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S) +#define TIMG_T0_DIVIDER_V 0x0000FFFFU +#define TIMG_T0_DIVIDER_S 13 +/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1; + * When set, timer 0 auto-reload at alarm is enabled. + */ +#define TIMG_T0_AUTORELOAD (BIT(29)) +#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S) +#define TIMG_T0_AUTORELOAD_V 0x00000001U +#define TIMG_T0_AUTORELOAD_S 29 +/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1; + * When set, the timer 0 time-base counter will increment every clock tick. When + * cleared, the timer 0 time-base counter will decrement. + */ +#define TIMG_T0_INCREASE (BIT(30)) +#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S) +#define TIMG_T0_INCREASE_V 0x00000001U +#define TIMG_T0_INCREASE_S 30 +/** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0; + * When set, the timer 0 time-base counter is enabled. + */ +#define TIMG_T0_EN (BIT(31)) +#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S) +#define TIMG_T0_EN_V 0x00000001U +#define TIMG_T0_EN_S 31 + +/** TIMG_T0LO_REG register + * Timer 0 current value, low 32 bits + */ +#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4) +/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter + * of timer 0 can be read here. + */ +#define TIMG_T0_LO 0xFFFFFFFFU +#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S) +#define TIMG_T0_LO_V 0xFFFFFFFFU +#define TIMG_T0_LO_S 0 + +/** TIMG_T0HI_REG register + * Timer 0 current value, high 22 bits + */ +#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8) +/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0; + * After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter + * of timer 0 can be read here. + */ +#define TIMG_T0_HI 0x003FFFFFU +#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S) +#define TIMG_T0_HI_V 0x003FFFFFU +#define TIMG_T0_HI_S 0 + +/** TIMG_T0UPDATE_REG register + * Write to copy current timer value to TIMGn_T0_(LO/HI)_REG + */ +#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xc) +/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0; + * After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched. + */ +#define TIMG_T0_UPDATE (BIT(31)) +#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S) +#define TIMG_T0_UPDATE_V 0x00000001U +#define TIMG_T0_UPDATE_S 31 + +/** TIMG_T0ALARMLO_REG register + * Timer 0 alarm value, low 32 bits + */ +#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10) +/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0; + * Timer 0 alarm trigger time-base counter value, low 32 bits. + */ +#define TIMG_T0_ALARM_LO 0xFFFFFFFFU +#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S) +#define TIMG_T0_ALARM_LO_V 0xFFFFFFFFU +#define TIMG_T0_ALARM_LO_S 0 + +/** TIMG_T0ALARMHI_REG register + * Timer 0 alarm value, high bits + */ +#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14) +/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0; + * Timer 0 alarm trigger time-base counter value, high 22 bits. + */ +#define TIMG_T0_ALARM_HI 0x003FFFFFU +#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S) +#define TIMG_T0_ALARM_HI_V 0x003FFFFFU +#define TIMG_T0_ALARM_HI_S 0 + +/** TIMG_T0LOADLO_REG register + * Timer 0 reload value, low 32 bits + */ +#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18) +/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * Low 32 bits of the value that a reload will load onto timer 0 time-base + * Counter. + */ +#define TIMG_T0_LOAD_LO 0xFFFFFFFFU +#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S) +#define TIMG_T0_LOAD_LO_V 0xFFFFFFFFU +#define TIMG_T0_LOAD_LO_S 0 + +/** TIMG_T0LOADHI_REG register + * Timer 0 reload value, high 22 bits + */ +#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1c) +/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0; + * High 22 bits of the value that a reload will load onto timer 0 time-base + * counter. + */ +#define TIMG_T0_LOAD_HI 0x003FFFFFU +#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S) +#define TIMG_T0_LOAD_HI_V 0x003FFFFFU +#define TIMG_T0_LOAD_HI_S 0 + +/** TIMG_T0LOAD_REG register + * Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG + */ +#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x20) +/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0; + * + * Write any value to trigger a timer 0 time-base counter reload. + */ +#define TIMG_T0_LOAD 0xFFFFFFFFU +#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S) +#define TIMG_T0_LOAD_V 0xFFFFFFFFU +#define TIMG_T0_LOAD_S 0 + +/** TIMG_WDTCONFIG0_REG register + * Watchdog timer configuration register + */ +#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x48) +/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0; + * WDT reset CPU enable. + */ +#define TIMG_WDT_APPCPU_RESET_EN (BIT(12)) +#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S) +#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U +#define TIMG_WDT_APPCPU_RESET_EN_S 12 +/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0; + * WDT reset CPU enable. + */ +#define TIMG_WDT_PROCPU_RESET_EN (BIT(13)) +#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S) +#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U +#define TIMG_WDT_PROCPU_RESET_EN_S 13 +/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1; + * When set, Flash boot protection is enabled. + */ +#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S) +#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U +#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 +/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1; + * System reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ +#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U +#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S) +#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U +#define TIMG_WDT_SYS_RESET_LENGTH_S 15 +/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1; + * CPU reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ +#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U +#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S) +#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define TIMG_WDT_CPU_RESET_LENGTH_S 18 +/** TIMG_WDT_USE_XTAL : R/W; bitpos: [21]; default: 0; + * choose WDT clock:0-apb_clk, 1-xtal_clk. + */ +#define TIMG_WDT_USE_XTAL (BIT(21)) +#define TIMG_WDT_USE_XTAL_M (TIMG_WDT_USE_XTAL_V << TIMG_WDT_USE_XTAL_S) +#define TIMG_WDT_USE_XTAL_V 0x00000001U +#define TIMG_WDT_USE_XTAL_S 21 +/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0; + * update the WDT configuration registers + */ +#define TIMG_WDT_CONF_UPDATE_EN (BIT(22)) +#define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S) +#define TIMG_WDT_CONF_UPDATE_EN_V 0x00000001U +#define TIMG_WDT_CONF_UPDATE_EN_S 22 +/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0; + * Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG3 0x00000003U +#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S) +#define TIMG_WDT_STG3_V 0x00000003U +#define TIMG_WDT_STG3_S 23 +/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0; + * Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG2 0x00000003U +#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S) +#define TIMG_WDT_STG2_V 0x00000003U +#define TIMG_WDT_STG2_S 25 +/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0; + * Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG1 0x00000003U +#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S) +#define TIMG_WDT_STG1_V 0x00000003U +#define TIMG_WDT_STG1_S 27 +/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0; + * Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG0 0x00000003U +#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S) +#define TIMG_WDT_STG0_V 0x00000003U +#define TIMG_WDT_STG0_S 29 +/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0; + * When set, MWDT is enabled. + */ +#define TIMG_WDT_EN (BIT(31)) +#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S) +#define TIMG_WDT_EN_V 0x00000001U +#define TIMG_WDT_EN_S 31 + +/** TIMG_WDTCONFIG1_REG register + * Watchdog timer prescaler register + */ +#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x4c) +/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0; + * When set, WDT 's clock divider counter will be reset. + */ +#define TIMG_WDT_DIVCNT_RST (BIT(0)) +#define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S) +#define TIMG_WDT_DIVCNT_RST_V 0x00000001U +#define TIMG_WDT_DIVCNT_RST_S 0 +/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1; + * MWDT clock prescaler value. MWDT clock period = 12.5 ns * + * TIMG_WDT_CLK_PRESCALE. + */ +#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU +#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S) +#define TIMG_WDT_CLK_PRESCALE_V 0x0000FFFFU +#define TIMG_WDT_CLK_PRESCALE_S 16 + +/** TIMG_WDTCONFIG2_REG register + * Watchdog timer stage 0 timeout value + */ +#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x50) +/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000; + * Stage 0 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S) +#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG0_HOLD_S 0 + +/** TIMG_WDTCONFIG3_REG register + * Watchdog timer stage 1 timeout value + */ +#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x54) +/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727; + * Stage 1 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S) +#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG1_HOLD_S 0 + +/** TIMG_WDTCONFIG4_REG register + * Watchdog timer stage 2 timeout value + */ +#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x58) +/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575; + * Stage 2 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S) +#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG2_HOLD_S 0 + +/** TIMG_WDTCONFIG5_REG register + * Watchdog timer stage 3 timeout value + */ +#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x5c) +/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575; + * Stage 3 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S) +#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG3_HOLD_S 0 + +/** TIMG_WDTFEED_REG register + * Write to feed the watchdog timer + */ +#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x60) +/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0; + * Write any value to feed the MWDT. (WO) + */ +#define TIMG_WDT_FEED 0xFFFFFFFFU +#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S) +#define TIMG_WDT_FEED_V 0xFFFFFFFFU +#define TIMG_WDT_FEED_S 0 + +/** TIMG_WDTWPROTECT_REG register + * Watchdog write protect register + */ +#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x64) +/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065; + * If the register contains a different value than its reset value, write + * protection is enabled. + */ +#define TIMG_WDT_WKEY 0xFFFFFFFFU +#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S) +#define TIMG_WDT_WKEY_V 0xFFFFFFFFU +#define TIMG_WDT_WKEY_S 0 + +/** TIMG_RTCCALICFG_REG register + * RTC calibration configure register + */ +#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x68) +/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1; + * 0: one-shot frequency calculation,1: periodic frequency calculation, + */ +#define TIMG_RTC_CALI_START_CYCLING (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S) +#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U +#define TIMG_RTC_CALI_START_CYCLING_S 12 +/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 0; + * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + */ +#define TIMG_RTC_CALI_CLK_SEL 0x00000003U +#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S) +#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U +#define TIMG_RTC_CALI_CLK_SEL_S 13 +/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0; + * indicate one-shot frequency calculation is done. + */ +#define TIMG_RTC_CALI_RDY (BIT(15)) +#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S) +#define TIMG_RTC_CALI_RDY_V 0x00000001U +#define TIMG_RTC_CALI_RDY_S 15 +/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1; + * Configure the time to calculate RTC slow clock's frequency. + */ +#define TIMG_RTC_CALI_MAX 0x00007FFFU +#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S) +#define TIMG_RTC_CALI_MAX_V 0x00007FFFU +#define TIMG_RTC_CALI_MAX_S 16 +/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0; + * Set this bit to start one-shot frequency calculation. + */ +#define TIMG_RTC_CALI_START (BIT(31)) +#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S) +#define TIMG_RTC_CALI_START_V 0x00000001U +#define TIMG_RTC_CALI_START_S 31 + +/** TIMG_RTCCALICFG1_REG register + * RTC calibration configure1 register + */ +#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x6c) +/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0; + * indicate periodic frequency calculation is done. + */ +#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0)) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0 +/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0; + * When one-shot or periodic frequency calculation is done, read this value to + * calculate RTC slow clock's frequency. + */ +#define TIMG_RTC_CALI_VALUE 0x01FFFFFFU +#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S) +#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFFU +#define TIMG_RTC_CALI_VALUE_S 7 + +/** TIMG_INT_ENA_TIMERS_REG register + * Interrupt enable bits + */ +#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x70) +/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_ENA (BIT(0)) +#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S) +#define TIMG_T0_INT_ENA_V 0x00000001U +#define TIMG_T0_INT_ENA_S 0 +/** TIMG_WDT_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_ENA (BIT(1)) +#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S) +#define TIMG_WDT_INT_ENA_V 0x00000001U +#define TIMG_WDT_INT_ENA_S 1 + +/** TIMG_INT_RAW_TIMERS_REG register + * Raw interrupt status + */ +#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x74) +/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_RAW (BIT(0)) +#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S) +#define TIMG_T0_INT_RAW_V 0x00000001U +#define TIMG_T0_INT_RAW_S 0 +/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; + * The raw interrupt status bit for the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_RAW (BIT(1)) +#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S) +#define TIMG_WDT_INT_RAW_V 0x00000001U +#define TIMG_WDT_INT_RAW_S 1 + +/** TIMG_INT_ST_TIMERS_REG register + * Masked interrupt status + */ +#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x78) +/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_ST (BIT(0)) +#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S) +#define TIMG_T0_INT_ST_V 0x00000001U +#define TIMG_T0_INT_ST_S 0 +/** TIMG_WDT_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_ST (BIT(1)) +#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S) +#define TIMG_WDT_INT_ST_V 0x00000001U +#define TIMG_WDT_INT_ST_S 1 + +/** TIMG_INT_CLR_TIMERS_REG register + * Interrupt clear bits + */ +#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x7c) +/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_CLR (BIT(0)) +#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S) +#define TIMG_T0_INT_CLR_V 0x00000001U +#define TIMG_T0_INT_CLR_S 0 +/** TIMG_WDT_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_CLR (BIT(1)) +#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S) +#define TIMG_WDT_INT_CLR_V 0x00000001U +#define TIMG_WDT_INT_CLR_S 1 + +/** TIMG_RTCCALICFG2_REG register + * Timer group calibration register + */ +#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x80) +/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0; + * RTC calibration timeout indicator + */ +#define TIMG_RTC_CALI_TIMEOUT (BIT(0)) +#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S) +#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U +#define TIMG_RTC_CALI_TIMEOUT_S 0 +/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3; + * Cycles that release calibration timeout reset + */ +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S) +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3 +/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431; + * Threshold value for the RTC calibration timer. If the calibration timer's value + * exceeds this threshold, a timeout is triggered. + */ +#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU +#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S) +#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU +#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7 + +/** TIMG_NTIMERS_DATE_REG register + * Timer version control register + */ +#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0xf8) +/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35676274; + * Timer version control register + */ +#define TIMG_NTIMGS_DATE 0x0FFFFFFFU +#define TIMG_NTIMGS_DATE_M (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S) +#define TIMG_NTIMGS_DATE_V 0x0FFFFFFFU +#define TIMG_NTIMGS_DATE_S 0 + +/** TIMG_REGCLK_REG register + * Timer group clock gate register + */ +#define TIMG_REGCLK_REG(i) (REG_TIMG_BASE(i) + 0xfc) +/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1; + * enable timer's etm task and event + */ +#define TIMG_ETM_EN (BIT(28)) +#define TIMG_ETM_EN_M (TIMG_ETM_EN_V << TIMG_ETM_EN_S) +#define TIMG_ETM_EN_V 0x00000001U +#define TIMG_ETM_EN_S 28 +/** TIMG_WDT_CLK_IS_ACTIVE : R/W; bitpos: [29]; default: 1; + * enable WDT's clock + */ +#define TIMG_WDT_CLK_IS_ACTIVE (BIT(29)) +#define TIMG_WDT_CLK_IS_ACTIVE_M (TIMG_WDT_CLK_IS_ACTIVE_V << TIMG_WDT_CLK_IS_ACTIVE_S) +#define TIMG_WDT_CLK_IS_ACTIVE_V 0x00000001U +#define TIMG_WDT_CLK_IS_ACTIVE_S 29 +/** TIMG_TIMER_CLK_IS_ACTIVE : R/W; bitpos: [30]; default: 1; + * enable Timer $x's clock + */ +#define TIMG_TIMER_CLK_IS_ACTIVE (BIT(30)) +#define TIMG_TIMER_CLK_IS_ACTIVE_M (TIMG_TIMER_CLK_IS_ACTIVE_V << TIMG_TIMER_CLK_IS_ACTIVE_S) +#define TIMG_TIMER_CLK_IS_ACTIVE_V 0x00000001U +#define TIMG_TIMER_CLK_IS_ACTIVE_S 30 +/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0; + * Register clock gate signal. 1: Registers can be read and written to by software. 0: + * Registers can not be read or written to by software. + */ +#define TIMG_CLK_EN (BIT(31)) +#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S) +#define TIMG_CLK_EN_V 0x00000001U +#define TIMG_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/timer_group_struct.h b/components/soc/esp32c6/include/soc/timer_group_struct.h new file mode 100644 index 0000000000..15e16e6d2e --- /dev/null +++ b/components/soc/esp32c6/include/soc/timer_group_struct.h @@ -0,0 +1,568 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: T0 Control and configuration registers */ +/** Type of txconfig register + * Timer x configuration register + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** tx_use_xtal : R/W; bitpos: [9]; default: 0; + * 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source + * clock of timer group. + */ + uint32_t tx_use_xtal:1; + /** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0; + * When set, the alarm is enabled. This bit is automatically cleared once an + * alarm occurs. + */ + uint32_t tx_alarm_en:1; + uint32_t reserved_11:1; + /** tx_divcnt_rst : WT; bitpos: [12]; default: 0; + * When set, Timer x 's clock divider counter will be reset. + */ + uint32_t tx_divcnt_rst:1; + /** tx_divider : R/W; bitpos: [28:13]; default: 1; + * Timer x clock (Tx_clk) prescaler value. + */ + uint32_t tx_divider:16; + /** tx_autoreload : R/W; bitpos: [29]; default: 1; + * When set, timer x auto-reload at alarm is enabled. + */ + uint32_t tx_autoreload:1; + /** tx_increase : R/W; bitpos: [30]; default: 1; + * When set, the timer x time-base counter will increment every clock tick. When + * cleared, the timer x time-base counter will decrement. + */ + uint32_t tx_increase:1; + /** tx_en : R/W/SS/SC; bitpos: [31]; default: 0; + * When set, the timer x time-base counter is enabled. + */ + uint32_t tx_en:1; + }; + uint32_t val; +} timg_txconfig_reg_t; + +/** Type of txlo register + * Timer x current value, low 32 bits + */ +typedef union { + struct { + /** tx_lo : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter + * of timer x can be read here. + */ + uint32_t tx_lo:32; + }; + uint32_t val; +} timg_txlo_reg_t; + +/** Type of txhi register + * Timer x current value, high 22 bits + */ +typedef union { + struct { + /** tx_hi : RO; bitpos: [21:0]; default: 0; + * After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter + * of timer x can be read here. + */ + uint32_t tx_hi:22; + uint32_t reserved_22:10; + }; + uint32_t val; +} timg_txhi_reg_t; + +/** Type of txupdate register + * Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** tx_update : R/W/SC; bitpos: [31]; default: 0; + * After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched. + */ + uint32_t tx_update:1; + }; + uint32_t val; +} timg_txupdate_reg_t; + +/** Type of txalarmlo register + * Timer x alarm value, low 32 bits + */ +typedef union { + struct { + /** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0; + * Timer x alarm trigger time-base counter value, low 32 bits. + */ + uint32_t tx_alarm_lo:32; + }; + uint32_t val; +} timg_txalarmlo_reg_t; + +/** Type of txalarmhi register + * Timer x alarm value, high bits + */ +typedef union { + struct { + /** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0; + * Timer x alarm trigger time-base counter value, high 22 bits. + */ + uint32_t tx_alarm_hi:22; + uint32_t reserved_22:10; + }; + uint32_t val; +} timg_txalarmhi_reg_t; + +/** Type of txloadlo register + * Timer x reload value, low 32 bits + */ +typedef union { + struct { + /** tx_load_lo : R/W; bitpos: [31:0]; default: 0; + * Low 32 bits of the value that a reload will load onto timer x time-base + * Counter. + */ + uint32_t tx_load_lo:32; + }; + uint32_t val; +} timg_txloadlo_reg_t; + +/** Type of txloadhi register + * Timer x reload value, high 22 bits + */ +typedef union { + struct { + /** tx_load_hi : R/W; bitpos: [21:0]; default: 0; + * High 22 bits of the value that a reload will load onto timer x time-base + * counter. + */ + uint32_t tx_load_hi:22; + uint32_t reserved_22:10; + }; + uint32_t val; +} timg_txloadhi_reg_t; + +/** Type of txload register + * Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG + */ +typedef union { + struct { + /** tx_load : WT; bitpos: [31:0]; default: 0; + * + * Write any value to trigger a timer x time-base counter reload. + */ + uint32_t tx_load:32; + }; + uint32_t val; +} timg_txload_reg_t; + + +/** Group: WDT Control and configuration registers */ +/** Type of wdtconfig0 register + * Watchdog timer configuration register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0; + * WDT reset CPU enable. + */ + uint32_t wdt_appcpu_reset_en:1; + /** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0; + * WDT reset CPU enable. + */ + uint32_t wdt_procpu_reset_en:1; + /** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1; + * When set, Flash boot protection is enabled. + */ + uint32_t wdt_flashboot_mod_en:1; + /** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1; + * System reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ + uint32_t wdt_sys_reset_length:3; + /** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1; + * CPU reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ + uint32_t wdt_cpu_reset_length:3; + /** wdt_use_xtal : R/W; bitpos: [21]; default: 0; + * choose WDT clock:0-apb_clk, 1-xtal_clk. + */ + uint32_t wdt_use_xtal:1; + /** wdt_conf_update_en : WT; bitpos: [22]; default: 0; + * update the WDT configuration registers + */ + uint32_t wdt_conf_update_en:1; + /** wdt_stg3 : R/W; bitpos: [24:23]; default: 0; + * Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg3:2; + /** wdt_stg2 : R/W; bitpos: [26:25]; default: 0; + * Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg2:2; + /** wdt_stg1 : R/W; bitpos: [28:27]; default: 0; + * Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg1:2; + /** wdt_stg0 : R/W; bitpos: [30:29]; default: 0; + * Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg0:2; + /** wdt_en : R/W; bitpos: [31]; default: 0; + * When set, MWDT is enabled. + */ + uint32_t wdt_en:1; + }; + uint32_t val; +} timg_wdtconfig0_reg_t; + +/** Type of wdtconfig1 register + * Watchdog timer prescaler register + */ +typedef union { + struct { + /** wdt_divcnt_rst : WT; bitpos: [0]; default: 0; + * When set, WDT 's clock divider counter will be reset. + */ + uint32_t wdt_divcnt_rst:1; + uint32_t reserved_1:15; + /** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1; + * MWDT clock prescaler value. MWDT clock period = 12.5 ns * + * TIMG_WDT_CLK_PRESCALE. + */ + uint32_t wdt_clk_prescale:16; + }; + uint32_t val; +} timg_wdtconfig1_reg_t; + +/** Type of wdtconfig2 register + * Watchdog timer stage 0 timeout value + */ +typedef union { + struct { + /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000; + * Stage 0 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg0_hold:32; + }; + uint32_t val; +} timg_wdtconfig2_reg_t; + +/** Type of wdtconfig3 register + * Watchdog timer stage 1 timeout value + */ +typedef union { + struct { + /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727; + * Stage 1 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg1_hold:32; + }; + uint32_t val; +} timg_wdtconfig3_reg_t; + +/** Type of wdtconfig4 register + * Watchdog timer stage 2 timeout value + */ +typedef union { + struct { + /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575; + * Stage 2 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg2_hold:32; + }; + uint32_t val; +} timg_wdtconfig4_reg_t; + +/** Type of wdtconfig5 register + * Watchdog timer stage 3 timeout value + */ +typedef union { + struct { + /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575; + * Stage 3 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg3_hold:32; + }; + uint32_t val; +} timg_wdtconfig5_reg_t; + +/** Type of wdtfeed register + * Write to feed the watchdog timer + */ +typedef union { + struct { + /** wdt_feed : WT; bitpos: [31:0]; default: 0; + * Write any value to feed the MWDT. (WO) + */ + uint32_t wdt_feed:32; + }; + uint32_t val; +} timg_wdtfeed_reg_t; + +/** Type of wdtwprotect register + * Watchdog write protect register + */ +typedef union { + struct { + /** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065; + * If the register contains a different value than its reset value, write + * protection is enabled. + */ + uint32_t wdt_wkey:32; + }; + uint32_t val; +} timg_wdtwprotect_reg_t; + + +/** Group: RTC CALI Control and configuration registers */ +/** Type of rtccalicfg register + * RTC calibration configure register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1; + * 0: one-shot frequency calculation,1: periodic frequency calculation, + */ + uint32_t rtc_cali_start_cycling:1; + /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0; + * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + */ + uint32_t rtc_cali_clk_sel:2; + /** rtc_cali_rdy : RO; bitpos: [15]; default: 0; + * indicate one-shot frequency calculation is done. + */ + uint32_t rtc_cali_rdy:1; + /** rtc_cali_max : R/W; bitpos: [30:16]; default: 1; + * Configure the time to calculate RTC slow clock's frequency. + */ + uint32_t rtc_cali_max:15; + /** rtc_cali_start : R/W; bitpos: [31]; default: 0; + * Set this bit to start one-shot frequency calculation. + */ + uint32_t rtc_cali_start:1; + }; + uint32_t val; +} timg_rtccalicfg_reg_t; + +/** Type of rtccalicfg1 register + * RTC calibration configure1 register + */ +typedef union { + struct { + /** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0; + * indicate periodic frequency calculation is done. + */ + uint32_t rtc_cali_cycling_data_vld:1; + uint32_t reserved_1:6; + /** rtc_cali_value : RO; bitpos: [31:7]; default: 0; + * When one-shot or periodic frequency calculation is done, read this value to + * calculate RTC slow clock's frequency. + */ + uint32_t rtc_cali_value:25; + }; + uint32_t val; +} timg_rtccalicfg1_reg_t; + +/** Type of rtccalicfg2 register + * Timer group calibration register + */ +typedef union { + struct { + /** rtc_cali_timeout : RO; bitpos: [0]; default: 0; + * RTC calibration timeout indicator + */ + uint32_t rtc_cali_timeout:1; + uint32_t reserved_1:2; + /** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3; + * Cycles that release calibration timeout reset + */ + uint32_t rtc_cali_timeout_rst_cnt:4; + /** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431; + * Threshold value for the RTC calibration timer. If the calibration timer's value + * exceeds this threshold, a timeout is triggered. + */ + uint32_t rtc_cali_timeout_thres:25; + }; + uint32_t val; +} timg_rtccalicfg2_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_ena_timers register + * Interrupt enable bits + */ +typedef union { + struct { + /** t0_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_ena:1; + /** wdt_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} timg_int_ena_timers_reg_t; + +/** Type of int_raw_timers register + * Raw interrupt status + */ +typedef union { + struct { + /** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_raw:1; + /** wdt_int_raw : R/SS/WTC; bitpos: [1]; default: 0; + * The raw interrupt status bit for the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} timg_int_raw_timers_reg_t; + +/** Type of int_st_timers register + * Masked interrupt status + */ +typedef union { + struct { + /** t0_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_st:1; + /** wdt_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} timg_int_st_timers_reg_t; + +/** Type of int_clr_timers register + * Interrupt clear bits + */ +typedef union { + struct { + /** t0_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_clr:1; + /** wdt_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} timg_int_clr_timers_reg_t; + + +/** Group: Version register */ +/** Type of ntimers_date register + * Timer version control register + */ +typedef union { + struct { + /** ntimgs_date : R/W; bitpos: [27:0]; default: 35676274; + * Timer version control register + */ + uint32_t ntimgs_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} timg_ntimers_date_reg_t; + + +/** Group: Clock configuration registers */ +/** Type of regclk register + * Timer group clock gate register + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** etm_en : R/W; bitpos: [28]; default: 1; + * enable timer's etm task and event + */ + uint32_t etm_en:1; + /** wdt_clk_is_active : R/W; bitpos: [29]; default: 1; + * enable WDT's clock + */ + uint32_t wdt_clk_is_active:1; + /** timer_clk_is_active : R/W; bitpos: [30]; default: 1; + * enable Timer $x's clock + */ + uint32_t timer_clk_is_active:1; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Register clock gate signal. 1: Registers can be read and written to by software. 0: + * Registers can not be read or written to by software. + */ + uint32_t clk_en:1; + }; + uint32_t val; +} timg_regclk_reg_t; + + +typedef struct { + volatile timg_txconfig_reg_t config; + volatile timg_txlo_reg_t lo; + volatile timg_txhi_reg_t hi; + volatile timg_txupdate_reg_t update; + volatile timg_txalarmlo_reg_t alarmlo; + volatile timg_txalarmhi_reg_t alarmhi; + volatile timg_txloadlo_reg_t loadlo; + volatile timg_txloadhi_reg_t loadhi; + volatile timg_txload_reg_t load; +} timg_hwtimer_reg_t; + + +typedef struct timg_dev_t { + volatile timg_hwtimer_reg_t hw_timer[1]; + uint32_t reserved_024[9]; + volatile timg_wdtconfig0_reg_t wdtconfig0; + volatile timg_wdtconfig1_reg_t wdtconfig1; + volatile timg_wdtconfig2_reg_t wdtconfig2; + volatile timg_wdtconfig3_reg_t wdtconfig3; + volatile timg_wdtconfig4_reg_t wdtconfig4; + volatile timg_wdtconfig5_reg_t wdtconfig5; + volatile timg_wdtfeed_reg_t wdtfeed; + volatile timg_wdtwprotect_reg_t wdtwprotect; + volatile timg_rtccalicfg_reg_t rtccalicfg; + volatile timg_rtccalicfg1_reg_t rtccalicfg1; + volatile timg_int_ena_timers_reg_t int_ena_timers; + volatile timg_int_raw_timers_reg_t int_raw_timers; + volatile timg_int_st_timers_reg_t int_st_timers; + volatile timg_int_clr_timers_reg_t int_clr_timers; + volatile timg_rtccalicfg2_reg_t rtccalicfg2; + uint32_t reserved_084[29]; + volatile timg_ntimers_date_reg_t ntimers_date; + volatile timg_regclk_reg_t regclk; +} timg_dev_t; + +extern timg_dev_t TIMERG0; +extern timg_dev_t TIMERG1; + +#ifndef __cplusplus +_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/trace_reg.h b/components/soc/esp32c6/include/soc/trace_reg.h new file mode 100644 index 0000000000..a5c3eda9dc --- /dev/null +++ b/components/soc/esp32c6/include/soc/trace_reg.h @@ -0,0 +1,219 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TRACE_MEM_START_ADDR_REG register + * mem start addr + */ +#define TRACE_MEM_START_ADDR_REG (DR_REG_TRACE_BASE + 0x0) +/** TRACE_MEM_STAET_ADDR : R/W; bitpos: [31:0]; default: 0; + * The start address of trace memory + */ +#define TRACE_MEM_STAET_ADDR 0xFFFFFFFFU +#define TRACE_MEM_STAET_ADDR_M (TRACE_MEM_STAET_ADDR_V << TRACE_MEM_STAET_ADDR_S) +#define TRACE_MEM_STAET_ADDR_V 0xFFFFFFFFU +#define TRACE_MEM_STAET_ADDR_S 0 + +/** TRACE_MEM_END_ADDR_REG register + * mem end addr + */ +#define TRACE_MEM_END_ADDR_REG (DR_REG_TRACE_BASE + 0x4) +/** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * The end address of trace memory + */ +#define TRACE_MEM_END_ADDR 0xFFFFFFFFU +#define TRACE_MEM_END_ADDR_M (TRACE_MEM_END_ADDR_V << TRACE_MEM_END_ADDR_S) +#define TRACE_MEM_END_ADDR_V 0xFFFFFFFFU +#define TRACE_MEM_END_ADDR_S 0 + +/** TRACE_MEM_CURRENT_ADDR_REG register + * mem current addr + */ +#define TRACE_MEM_CURRENT_ADDR_REG (DR_REG_TRACE_BASE + 0x8) +/** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0; + * current_mem_addr,indicate that next writing addr + */ +#define TRACE_MEM_CURRENT_ADDR 0xFFFFFFFFU +#define TRACE_MEM_CURRENT_ADDR_M (TRACE_MEM_CURRENT_ADDR_V << TRACE_MEM_CURRENT_ADDR_S) +#define TRACE_MEM_CURRENT_ADDR_V 0xFFFFFFFFU +#define TRACE_MEM_CURRENT_ADDR_S 0 + +/** TRACE_MEM_ADDR_UPDATE_REG register + * mem addr update + */ +#define TRACE_MEM_ADDR_UPDATE_REG (DR_REG_TRACE_BASE + 0xc) +/** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0; + * when set this reg, the current_mem_addr will update to start_addr + */ +#define TRACE_MEM_CURRENT_ADDR_UPDATE (BIT(0)) +#define TRACE_MEM_CURRENT_ADDR_UPDATE_M (TRACE_MEM_CURRENT_ADDR_UPDATE_V << TRACE_MEM_CURRENT_ADDR_UPDATE_S) +#define TRACE_MEM_CURRENT_ADDR_UPDATE_V 0x00000001U +#define TRACE_MEM_CURRENT_ADDR_UPDATE_S 0 + +/** TRACE_FIFO_STATUS_REG register + * fifo status register + */ +#define TRACE_FIFO_STATUS_REG (DR_REG_TRACE_BASE + 0x10) +/** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1; + * 1 indicate that fifo is empty + */ +#define TRACE_FIFO_EMPTY (BIT(0)) +#define TRACE_FIFO_EMPTY_M (TRACE_FIFO_EMPTY_V << TRACE_FIFO_EMPTY_S) +#define TRACE_FIFO_EMPTY_V 0x00000001U +#define TRACE_FIFO_EMPTY_S 0 +/** TRACE_WORK_STATUS : RO; bitpos: [1]; default: 0; + * mem_full interrupt status + */ +#define TRACE_WORK_STATUS (BIT(1)) +#define TRACE_WORK_STATUS_M (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S) +#define TRACE_WORK_STATUS_V 0x00000001U +#define TRACE_WORK_STATUS_S 1 + +/** TRACE_INTR_ENA_REG register + * interrupt enable register + */ +#define TRACE_INTR_ENA_REG (DR_REG_TRACE_BASE + 0x14) +/** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0; + * Set 1 enable fifo_overflow interrupt + */ +#define TRACE_FIFO_OVERFLOW_INTR_ENA (BIT(0)) +#define TRACE_FIFO_OVERFLOW_INTR_ENA_M (TRACE_FIFO_OVERFLOW_INTR_ENA_V << TRACE_FIFO_OVERFLOW_INTR_ENA_S) +#define TRACE_FIFO_OVERFLOW_INTR_ENA_V 0x00000001U +#define TRACE_FIFO_OVERFLOW_INTR_ENA_S 0 +/** TRACE_MEM_FULL_INTR_ENA : R/W; bitpos: [1]; default: 0; + * Set 1 enable mem_full interrupt + */ +#define TRACE_MEM_FULL_INTR_ENA (BIT(1)) +#define TRACE_MEM_FULL_INTR_ENA_M (TRACE_MEM_FULL_INTR_ENA_V << TRACE_MEM_FULL_INTR_ENA_S) +#define TRACE_MEM_FULL_INTR_ENA_V 0x00000001U +#define TRACE_MEM_FULL_INTR_ENA_S 1 + +/** TRACE_INTR_RAW_REG register + * interrupt status register + */ +#define TRACE_INTR_RAW_REG (DR_REG_TRACE_BASE + 0x18) +/** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0; + * fifo_overflow interrupt status + */ +#define TRACE_FIFO_OVERFLOW_INTR_RAW (BIT(0)) +#define TRACE_FIFO_OVERFLOW_INTR_RAW_M (TRACE_FIFO_OVERFLOW_INTR_RAW_V << TRACE_FIFO_OVERFLOW_INTR_RAW_S) +#define TRACE_FIFO_OVERFLOW_INTR_RAW_V 0x00000001U +#define TRACE_FIFO_OVERFLOW_INTR_RAW_S 0 +/** TRACE_MEM_FULL_INTR_RAW : RO; bitpos: [1]; default: 0; + * mem_full interrupt status + */ +#define TRACE_MEM_FULL_INTR_RAW (BIT(1)) +#define TRACE_MEM_FULL_INTR_RAW_M (TRACE_MEM_FULL_INTR_RAW_V << TRACE_MEM_FULL_INTR_RAW_S) +#define TRACE_MEM_FULL_INTR_RAW_V 0x00000001U +#define TRACE_MEM_FULL_INTR_RAW_S 1 + +/** TRACE_INTR_CLR_REG register + * interrupt clear register + */ +#define TRACE_INTR_CLR_REG (DR_REG_TRACE_BASE + 0x1c) +/** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0; + * Set 1 clr fifo overflow interrupt + */ +#define TRACE_FIFO_OVERFLOW_INTR_CLR (BIT(0)) +#define TRACE_FIFO_OVERFLOW_INTR_CLR_M (TRACE_FIFO_OVERFLOW_INTR_CLR_V << TRACE_FIFO_OVERFLOW_INTR_CLR_S) +#define TRACE_FIFO_OVERFLOW_INTR_CLR_V 0x00000001U +#define TRACE_FIFO_OVERFLOW_INTR_CLR_S 0 +/** TRACE_MEM_FULL_INTR_CLR : WT; bitpos: [1]; default: 0; + * Set 1 clr mem full interrupt + */ +#define TRACE_MEM_FULL_INTR_CLR (BIT(1)) +#define TRACE_MEM_FULL_INTR_CLR_M (TRACE_MEM_FULL_INTR_CLR_V << TRACE_MEM_FULL_INTR_CLR_S) +#define TRACE_MEM_FULL_INTR_CLR_V 0x00000001U +#define TRACE_MEM_FULL_INTR_CLR_S 1 + +/** TRACE_TRIGGER_REG register + * trigger register + */ +#define TRACE_TRIGGER_REG (DR_REG_TRACE_BASE + 0x20) +/** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0; + * [0] set 1 start trace. + */ +#define TRACE_TRIGGER_ON (BIT(0)) +#define TRACE_TRIGGER_ON_M (TRACE_TRIGGER_ON_V << TRACE_TRIGGER_ON_S) +#define TRACE_TRIGGER_ON_V 0x00000001U +#define TRACE_TRIGGER_ON_S 0 +/** TRACE_TRIGGER_OFF : WT; bitpos: [1]; default: 0; + * set 1 stop trace. + */ +#define TRACE_TRIGGER_OFF (BIT(1)) +#define TRACE_TRIGGER_OFF_M (TRACE_TRIGGER_OFF_V << TRACE_TRIGGER_OFF_S) +#define TRACE_TRIGGER_OFF_V 0x00000001U +#define TRACE_TRIGGER_OFF_S 1 +/** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1; + * if this reg is 1, trace will loop wrtie trace_mem. If is 0, when mem_current_addr + * at mem_end_addr, it will stop at the mem_end_addr + */ +#define TRACE_MEM_LOOP (BIT(2)) +#define TRACE_MEM_LOOP_M (TRACE_MEM_LOOP_V << TRACE_MEM_LOOP_S) +#define TRACE_MEM_LOOP_V 0x00000001U +#define TRACE_MEM_LOOP_S 2 +/** TRACE_RESTART_ENA : R/W; bitpos: [3]; default: 1; + * enable encoder auto-restart, when lost package, the encoder will end, if enable + * auto-restart, when fifo empty, encoder will restart and send a sync package. + */ +#define TRACE_RESTART_ENA (BIT(3)) +#define TRACE_RESTART_ENA_M (TRACE_RESTART_ENA_V << TRACE_RESTART_ENA_S) +#define TRACE_RESTART_ENA_V 0x00000001U +#define TRACE_RESTART_ENA_S 3 + +/** TRACE_RESYNC_PROLONGED_REG register + * resync configuration register + */ +#define TRACE_RESYNC_PROLONGED_REG (DR_REG_TRACE_BASE + 0x24) +/** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128; + * count number, when count to this value, send a sync package + */ +#define TRACE_RESYNC_PROLONGED 0x00FFFFFFU +#define TRACE_RESYNC_PROLONGED_M (TRACE_RESYNC_PROLONGED_V << TRACE_RESYNC_PROLONGED_S) +#define TRACE_RESYNC_PROLONGED_V 0x00FFFFFFU +#define TRACE_RESYNC_PROLONGED_S 0 +/** TRACE_RESYNC_MODE : R/W; bitpos: [24]; default: 0; + * resyc mode sel: 0: default, cycle count 1: package num count + */ +#define TRACE_RESYNC_MODE (BIT(24)) +#define TRACE_RESYNC_MODE_M (TRACE_RESYNC_MODE_V << TRACE_RESYNC_MODE_S) +#define TRACE_RESYNC_MODE_V 0x00000001U +#define TRACE_RESYNC_MODE_S 24 + +/** TRACE_CLOCK_GATE_REG register + * Clock gate control register + */ +#define TRACE_CLOCK_GATE_REG (DR_REG_TRACE_BASE + 0x28) +/** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; + * The bit is used to enable clock gate when access all registers in this module. + */ +#define TRACE_CLK_EN (BIT(0)) +#define TRACE_CLK_EN_M (TRACE_CLK_EN_V << TRACE_CLK_EN_S) +#define TRACE_CLK_EN_V 0x00000001U +#define TRACE_CLK_EN_S 0 + +/** TRACE_DATE_REG register + * Version control register + */ +#define TRACE_DATE_REG (DR_REG_TRACE_BASE + 0x3fc) +/** TRACE_DATE : R/W; bitpos: [27:0]; default: 35663920; + * version control register. Note that this default value stored is the latest date + * when the hardware logic was updated. + */ +#define TRACE_DATE 0x0FFFFFFFU +#define TRACE_DATE_M (TRACE_DATE_V << TRACE_DATE_S) +#define TRACE_DATE_V 0x0FFFFFFFU +#define TRACE_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/trace_struct.h b/components/soc/esp32c6/include/soc/trace_struct.h new file mode 100644 index 0000000000..3b8330b6b0 --- /dev/null +++ b/components/soc/esp32c6/include/soc/trace_struct.h @@ -0,0 +1,249 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Trace memory configuration registers */ +/** Type of mem_start_addr register + * mem start addr + */ +typedef union { + struct { + /** mem_start_addr : R/W; bitpos: [31:0]; default: 0; + * The start address of trace memory + */ + uint32_t mem_start_addr:32; + }; + uint32_t val; +} trace_mem_start_addr_reg_t; + +/** Type of mem_end_addr register + * mem end addr + */ +typedef union { + struct { + /** mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * The end address of trace memory + */ + uint32_t mem_end_addr:32; + }; + uint32_t val; +} trace_mem_end_addr_reg_t; + +/** Type of mem_current_addr register + * mem current addr + */ +typedef union { + struct { + /** mem_current_addr : RO; bitpos: [31:0]; default: 0; + * current_mem_addr,indicate that next writing addr + */ + uint32_t mem_current_addr:32; + }; + uint32_t val; +} trace_mem_current_addr_reg_t; + +/** Type of mem_addr_update register + * mem addr update + */ +typedef union { + struct { + /** mem_current_addr_update : WT; bitpos: [0]; default: 0; + * when set this reg, the current_mem_addr will update to start_addr + */ + uint32_t mem_current_addr_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} trace_mem_addr_update_reg_t; + + +/** Group: Trace fifo status register */ +/** Type of fifo_status register + * fifo status register + */ +typedef union { + struct { + /** fifo_empty : RO; bitpos: [0]; default: 1; + * 1 indicate that fifo is empty + */ + uint32_t fifo_empty:1; + /** work_status : RO; bitpos: [1]; default: 0; + * mem_full interrupt status + */ + uint32_t work_status:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} trace_fifo_status_reg_t; + + +/** Group: Trace interrupt configuration registers */ +/** Type of intr_ena register + * interrupt enable register + */ +typedef union { + struct { + /** fifo_overflow_intr_ena : R/W; bitpos: [0]; default: 0; + * Set 1 enable fifo_overflow interrupt + */ + uint32_t fifo_overflow_intr_ena:1; + /** mem_full_intr_ena : R/W; bitpos: [1]; default: 0; + * Set 1 enable mem_full interrupt + */ + uint32_t mem_full_intr_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} trace_intr_ena_reg_t; + +/** Type of intr_raw register + * interrupt status register + */ +typedef union { + struct { + /** fifo_overflow_intr_raw : RO; bitpos: [0]; default: 0; + * fifo_overflow interrupt status + */ + uint32_t fifo_overflow_intr_raw:1; + /** mem_full_intr_raw : RO; bitpos: [1]; default: 0; + * mem_full interrupt status + */ + uint32_t mem_full_intr_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} trace_intr_raw_reg_t; + +/** Type of intr_clr register + * interrupt clear register + */ +typedef union { + struct { + /** fifo_overflow_intr_clr : WT; bitpos: [0]; default: 0; + * Set 1 clr fifo overflow interrupt + */ + uint32_t fifo_overflow_intr_clr:1; + /** mem_full_intr_clr : WT; bitpos: [1]; default: 0; + * Set 1 clr mem full interrupt + */ + uint32_t mem_full_intr_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} trace_intr_clr_reg_t; + + +/** Group: Trace configuration register */ +/** Type of trigger register + * trigger register + */ +typedef union { + struct { + /** trigger_on : WT; bitpos: [0]; default: 0; + * [0] set 1 start trace. + */ + uint32_t trigger_on:1; + /** trigger_off : WT; bitpos: [1]; default: 0; + * set 1 stop trace. + */ + uint32_t trigger_off:1; + /** mem_loop : R/W; bitpos: [2]; default: 1; + * if this reg is 1, trace will loop wrtie trace_mem. If is 0, when mem_current_addr + * at mem_end_addr, it will stop at the mem_end_addr + */ + uint32_t mem_loop:1; + /** restart_ena : R/W; bitpos: [3]; default: 1; + * enable encoder auto-restart, when lost package, the encoder will end, if enable + * auto-restart, when fifo empty, encoder will restart and send a sync package. + */ + uint32_t restart_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} trace_trigger_reg_t; + +/** Type of resync_prolonged register + * resync configuration register + */ +typedef union { + struct { + /** resync_prolonged : R/W; bitpos: [23:0]; default: 128; + * count number, when count to this value, send a sync package + */ + uint32_t resync_prolonged:24; + /** resync_mode : R/W; bitpos: [24]; default: 0; + * resyc mode sel: 0: default, cycle count 1: package num count + */ + uint32_t resync_mode:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} trace_resync_prolonged_reg_t; + + +/** Group: Clock Gate Control and configuration register */ +/** Type of clock_gate register + * Clock gate control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * The bit is used to enable clock gate when access all registers in this module. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} trace_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35663920; + * version control register. Note that this default value stored is the latest date + * when the hardware logic was updated. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} trace_date_reg_t; + + +typedef struct trace_dev_t { + volatile trace_mem_start_addr_reg_t mem_start_addr; + volatile trace_mem_end_addr_reg_t mem_end_addr; + volatile trace_mem_current_addr_reg_t mem_current_addr; + volatile trace_mem_addr_update_reg_t mem_addr_update; + volatile trace_fifo_status_reg_t fifo_status; + volatile trace_intr_ena_reg_t intr_ena; + volatile trace_intr_raw_reg_t intr_raw; + volatile trace_intr_clr_reg_t intr_clr; + volatile trace_trigger_reg_t trigger; + volatile trace_resync_prolonged_reg_t resync_prolonged; + volatile trace_clock_gate_reg_t clock_gate; + uint32_t reserved_02c[244]; + volatile trace_date_reg_t date; +} trace_dev_t; + +extern trace_dev_t TRACE; + +#ifndef __cplusplus +_Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/twai_reg.h b/components/soc/esp32c6/include/soc/twai_reg.h new file mode 100644 index 0000000000..4bd39d7ae6 --- /dev/null +++ b/components/soc/esp32c6/include/soc/twai_reg.h @@ -0,0 +1,740 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TWAI_MODE_REG register + * TWAI mode register. + */ +#define TWAI_MODE_REG(i) (REG_TWAI_BASE(i) + 0x0) +/** TWAI_RESET_MODE : R/W; bitpos: [0]; default: 1; + * 1: reset, detection of a set reset mode bit results in aborting the current + * transmission/reception of a message and entering the reset mode. 0: normal, on the + * '1-to-0' transition of the reset mode bit, the TWAI controller returns to the + * operating mode. + */ +#define TWAI_RESET_MODE (BIT(0)) +#define TWAI_RESET_MODE_M (TWAI_RESET_MODE_V << TWAI_RESET_MODE_S) +#define TWAI_RESET_MODE_V 0x00000001U +#define TWAI_RESET_MODE_S 0 +/** TWAI_LISTEN_ONLY_MODE : R/W; bitpos: [1]; default: 0; + * 1: listen only, in this mode the TWAI controller would give no acknowledge to the + * TWAI-bus, even if a message is received successfully. The error counters are + * stopped at the current value. 0: normal. + */ +#define TWAI_LISTEN_ONLY_MODE (BIT(1)) +#define TWAI_LISTEN_ONLY_MODE_M (TWAI_LISTEN_ONLY_MODE_V << TWAI_LISTEN_ONLY_MODE_S) +#define TWAI_LISTEN_ONLY_MODE_V 0x00000001U +#define TWAI_LISTEN_ONLY_MODE_S 1 +/** TWAI_SELF_TEST_MODE : R/W; bitpos: [2]; default: 0; + * 1: self test, in this mode a full node test is possible without any other active + * node on the bus using the self reception request command. The TWAI controller will + * perform a successful transmission, even if there is no acknowledge received. 0: + * normal, an acknowledge is required for successful transmission. + */ +#define TWAI_SELF_TEST_MODE (BIT(2)) +#define TWAI_SELF_TEST_MODE_M (TWAI_SELF_TEST_MODE_V << TWAI_SELF_TEST_MODE_S) +#define TWAI_SELF_TEST_MODE_V 0x00000001U +#define TWAI_SELF_TEST_MODE_S 2 +/** TWAI_ACCEPTANCE_FILTER_MODE : R/W; bitpos: [3]; default: 0; + * 1:single, the single acceptance filter option is enabled (one filter with the + * length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled + * (two filters, each with the length of 16 bit are active). + */ +#define TWAI_ACCEPTANCE_FILTER_MODE (BIT(3)) +#define TWAI_ACCEPTANCE_FILTER_MODE_M (TWAI_ACCEPTANCE_FILTER_MODE_V << TWAI_ACCEPTANCE_FILTER_MODE_S) +#define TWAI_ACCEPTANCE_FILTER_MODE_V 0x00000001U +#define TWAI_ACCEPTANCE_FILTER_MODE_S 3 + +/** TWAI_CMD_REG register + * TWAI command register. + */ +#define TWAI_CMD_REG(i) (REG_TWAI_BASE(i) + 0x4) +/** TWAI_TX_REQUEST : WO; bitpos: [0]; default: 0; + * 1: present, a message shall be transmitted. 0: absent + */ +#define TWAI_TX_REQUEST (BIT(0)) +#define TWAI_TX_REQUEST_M (TWAI_TX_REQUEST_V << TWAI_TX_REQUEST_S) +#define TWAI_TX_REQUEST_V 0x00000001U +#define TWAI_TX_REQUEST_S 0 +/** TWAI_ABORT_TX : WO; bitpos: [1]; default: 0; + * 1: present, if not already in progress, a pending transmission request is + * cancelled. 0: absent + */ +#define TWAI_ABORT_TX (BIT(1)) +#define TWAI_ABORT_TX_M (TWAI_ABORT_TX_V << TWAI_ABORT_TX_S) +#define TWAI_ABORT_TX_V 0x00000001U +#define TWAI_ABORT_TX_S 1 +/** TWAI_RELEASE_BUFFER : WO; bitpos: [2]; default: 0; + * 1: released, the receive buffer, representing the message memory space in the + * RXFIFO is released. 0: no action + */ +#define TWAI_RELEASE_BUFFER (BIT(2)) +#define TWAI_RELEASE_BUFFER_M (TWAI_RELEASE_BUFFER_V << TWAI_RELEASE_BUFFER_S) +#define TWAI_RELEASE_BUFFER_V 0x00000001U +#define TWAI_RELEASE_BUFFER_S 2 +/** TWAI_CLEAR_DATA_OVERRUN : WO; bitpos: [3]; default: 0; + * 1: clear, the data overrun status bit is cleared. 0: no action. + */ +#define TWAI_CLEAR_DATA_OVERRUN (BIT(3)) +#define TWAI_CLEAR_DATA_OVERRUN_M (TWAI_CLEAR_DATA_OVERRUN_V << TWAI_CLEAR_DATA_OVERRUN_S) +#define TWAI_CLEAR_DATA_OVERRUN_V 0x00000001U +#define TWAI_CLEAR_DATA_OVERRUN_S 3 +/** TWAI_SELF_RX_REQUEST : WO; bitpos: [4]; default: 0; + * 1: present, a message shall be transmitted and received simultaneously. 0: absent. + */ +#define TWAI_SELF_RX_REQUEST (BIT(4)) +#define TWAI_SELF_RX_REQUEST_M (TWAI_SELF_RX_REQUEST_V << TWAI_SELF_RX_REQUEST_S) +#define TWAI_SELF_RX_REQUEST_V 0x00000001U +#define TWAI_SELF_RX_REQUEST_S 4 + +/** TWAI_STATUS_REG register + * TWAI status register. + */ +#define TWAI_STATUS_REG(i) (REG_TWAI_BASE(i) + 0x8) +/** TWAI_STATUS_RECEIVE_BUFFER : RO; bitpos: [0]; default: 0; + * 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no + * message is available + */ +#define TWAI_STATUS_RECEIVE_BUFFER (BIT(0)) +#define TWAI_STATUS_RECEIVE_BUFFER_M (TWAI_STATUS_RECEIVE_BUFFER_V << TWAI_STATUS_RECEIVE_BUFFER_S) +#define TWAI_STATUS_RECEIVE_BUFFER_V 0x00000001U +#define TWAI_STATUS_RECEIVE_BUFFER_S 0 +/** TWAI_STATUS_OVERRUN : RO; bitpos: [1]; default: 0; + * 1: overrun, a message was lost because there was not enough space for that message + * in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data + * overrun command was given + */ +#define TWAI_STATUS_OVERRUN (BIT(1)) +#define TWAI_STATUS_OVERRUN_M (TWAI_STATUS_OVERRUN_V << TWAI_STATUS_OVERRUN_S) +#define TWAI_STATUS_OVERRUN_V 0x00000001U +#define TWAI_STATUS_OVERRUN_S 1 +/** TWAI_STATUS_TRANSMIT_BUFFER : RO; bitpos: [2]; default: 0; + * 1: released, the CPU may write a message into the transmit buffer. 0: locked, the + * CPU cannot access the transmit buffer, a message is either waiting for transmission + * or is in the process of being transmitted + */ +#define TWAI_STATUS_TRANSMIT_BUFFER (BIT(2)) +#define TWAI_STATUS_TRANSMIT_BUFFER_M (TWAI_STATUS_TRANSMIT_BUFFER_V << TWAI_STATUS_TRANSMIT_BUFFER_S) +#define TWAI_STATUS_TRANSMIT_BUFFER_V 0x00000001U +#define TWAI_STATUS_TRANSMIT_BUFFER_S 2 +/** TWAI_STATUS_TRANSMISSION_COMPLETE : RO; bitpos: [3]; default: 0; + * 1: complete, last requested transmission has been successfully completed. 0: + * incomplete, previously requested transmission is not yet completed + */ +#define TWAI_STATUS_TRANSMISSION_COMPLETE (BIT(3)) +#define TWAI_STATUS_TRANSMISSION_COMPLETE_M (TWAI_STATUS_TRANSMISSION_COMPLETE_V << TWAI_STATUS_TRANSMISSION_COMPLETE_S) +#define TWAI_STATUS_TRANSMISSION_COMPLETE_V 0x00000001U +#define TWAI_STATUS_TRANSMISSION_COMPLETE_S 3 +/** TWAI_STATUS_RECEIVE : RO; bitpos: [4]; default: 0; + * 1: receive, the TWAI controller is receiving a message. 0: idle + */ +#define TWAI_STATUS_RECEIVE (BIT(4)) +#define TWAI_STATUS_RECEIVE_M (TWAI_STATUS_RECEIVE_V << TWAI_STATUS_RECEIVE_S) +#define TWAI_STATUS_RECEIVE_V 0x00000001U +#define TWAI_STATUS_RECEIVE_S 4 +/** TWAI_STATUS_TRANSMIT : RO; bitpos: [5]; default: 0; + * 1: transmit, the TWAI controller is transmitting a message. 0: idle + */ +#define TWAI_STATUS_TRANSMIT (BIT(5)) +#define TWAI_STATUS_TRANSMIT_M (TWAI_STATUS_TRANSMIT_V << TWAI_STATUS_TRANSMIT_S) +#define TWAI_STATUS_TRANSMIT_V 0x00000001U +#define TWAI_STATUS_TRANSMIT_S 5 +/** TWAI_STATUS_ERR : RO; bitpos: [6]; default: 0; + * 1: error, at least one of the error counters has reached or exceeded the CPU + * warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error + * counters are below the warning limit + */ +#define TWAI_STATUS_ERR (BIT(6)) +#define TWAI_STATUS_ERR_M (TWAI_STATUS_ERR_V << TWAI_STATUS_ERR_S) +#define TWAI_STATUS_ERR_V 0x00000001U +#define TWAI_STATUS_ERR_S 6 +/** TWAI_STATUS_NODE_BUS_OFF : RO; bitpos: [7]; default: 0; + * 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the + * TWAI controller is involved in bus activities + */ +#define TWAI_STATUS_NODE_BUS_OFF (BIT(7)) +#define TWAI_STATUS_NODE_BUS_OFF_M (TWAI_STATUS_NODE_BUS_OFF_V << TWAI_STATUS_NODE_BUS_OFF_S) +#define TWAI_STATUS_NODE_BUS_OFF_V 0x00000001U +#define TWAI_STATUS_NODE_BUS_OFF_S 7 +/** TWAI_STATUS_MISS : RO; bitpos: [8]; default: 0; + * 1: current message is destroyed because of FIFO overflow. + */ +#define TWAI_STATUS_MISS (BIT(8)) +#define TWAI_STATUS_MISS_M (TWAI_STATUS_MISS_V << TWAI_STATUS_MISS_S) +#define TWAI_STATUS_MISS_V 0x00000001U +#define TWAI_STATUS_MISS_S 8 + +/** TWAI_INTERRUPT_REG register + * Interrupt signals' register. + */ +#define TWAI_INTERRUPT_REG(i) (REG_TWAI_BASE(i) + 0xc) +/** TWAI_RECEIVE_INT_ST : RO; bitpos: [0]; default: 0; + * 1: this bit is set while the receive FIFO is not empty and the RIE bit is set + * within the interrupt enable register. 0: reset + */ +#define TWAI_RECEIVE_INT_ST (BIT(0)) +#define TWAI_RECEIVE_INT_ST_M (TWAI_RECEIVE_INT_ST_V << TWAI_RECEIVE_INT_ST_S) +#define TWAI_RECEIVE_INT_ST_V 0x00000001U +#define TWAI_RECEIVE_INT_ST_S 0 +/** TWAI_TRANSMIT_INT_ST : RO; bitpos: [1]; default: 0; + * 1: this bit is set whenever the transmit buffer status changes from '0-to-1' + * (released) and the TIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_TRANSMIT_INT_ST (BIT(1)) +#define TWAI_TRANSMIT_INT_ST_M (TWAI_TRANSMIT_INT_ST_V << TWAI_TRANSMIT_INT_ST_S) +#define TWAI_TRANSMIT_INT_ST_V 0x00000001U +#define TWAI_TRANSMIT_INT_ST_S 1 +/** TWAI_ERR_WARNING_INT_ST : RO; bitpos: [2]; default: 0; + * 1: this bit is set on every change (set and clear) of either the error status or + * bus status bits and the EIE bit is set within the interrupt enable register. 0: + * reset + */ +#define TWAI_ERR_WARNING_INT_ST (BIT(2)) +#define TWAI_ERR_WARNING_INT_ST_M (TWAI_ERR_WARNING_INT_ST_V << TWAI_ERR_WARNING_INT_ST_S) +#define TWAI_ERR_WARNING_INT_ST_V 0x00000001U +#define TWAI_ERR_WARNING_INT_ST_S 2 +/** TWAI_DATA_OVERRUN_INT_ST : RO; bitpos: [3]; default: 0; + * 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the + * DOIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_DATA_OVERRUN_INT_ST (BIT(3)) +#define TWAI_DATA_OVERRUN_INT_ST_M (TWAI_DATA_OVERRUN_INT_ST_V << TWAI_DATA_OVERRUN_INT_ST_S) +#define TWAI_DATA_OVERRUN_INT_ST_V 0x00000001U +#define TWAI_DATA_OVERRUN_INT_ST_S 3 +/** TWAI_ERR_PASSIVE_INT_ST : RO; bitpos: [5]; default: 0; + * 1: this bit is set whenever the TWAI controller has reached the error passive + * status (at least one error counter exceeds the protocol-defined level of 127) or if + * the TWAI controller is in the error passive status and enters the error active + * status again and the EPIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_ERR_PASSIVE_INT_ST (BIT(5)) +#define TWAI_ERR_PASSIVE_INT_ST_M (TWAI_ERR_PASSIVE_INT_ST_V << TWAI_ERR_PASSIVE_INT_ST_S) +#define TWAI_ERR_PASSIVE_INT_ST_V 0x00000001U +#define TWAI_ERR_PASSIVE_INT_ST_S 5 +/** TWAI_ARBITRATION_LOST_INT_ST : RO; bitpos: [6]; default: 0; + * 1: this bit is set when the TWAI controller lost the arbitration and becomes a + * receiver and the ALIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_ARBITRATION_LOST_INT_ST (BIT(6)) +#define TWAI_ARBITRATION_LOST_INT_ST_M (TWAI_ARBITRATION_LOST_INT_ST_V << TWAI_ARBITRATION_LOST_INT_ST_S) +#define TWAI_ARBITRATION_LOST_INT_ST_V 0x00000001U +#define TWAI_ARBITRATION_LOST_INT_ST_S 6 +/** TWAI_BUS_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and + * the BEIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_BUS_ERR_INT_ST (BIT(7)) +#define TWAI_BUS_ERR_INT_ST_M (TWAI_BUS_ERR_INT_ST_V << TWAI_BUS_ERR_INT_ST_S) +#define TWAI_BUS_ERR_INT_ST_V 0x00000001U +#define TWAI_BUS_ERR_INT_ST_S 7 +/** TWAI_IDLE_INT_ST : RO; bitpos: [8]; default: 0; + * 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and + * this interrupt enable bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_IDLE_INT_ST (BIT(8)) +#define TWAI_IDLE_INT_ST_M (TWAI_IDLE_INT_ST_V << TWAI_IDLE_INT_ST_S) +#define TWAI_IDLE_INT_ST_V 0x00000001U +#define TWAI_IDLE_INT_ST_S 8 + +/** TWAI_INTERRUPT_ENABLE_REG register + * Interrupt enable register. + */ +#define TWAI_INTERRUPT_ENABLE_REG(i) (REG_TWAI_BASE(i) + 0x10) +/** TWAI_EXT_RECEIVE_INT_ENA : R/W; bitpos: [0]; default: 0; + * 1: enabled, when the receive buffer status is 'full' the TWAI controller requests + * the respective interrupt. 0: disable + */ +#define TWAI_EXT_RECEIVE_INT_ENA (BIT(0)) +#define TWAI_EXT_RECEIVE_INT_ENA_M (TWAI_EXT_RECEIVE_INT_ENA_V << TWAI_EXT_RECEIVE_INT_ENA_S) +#define TWAI_EXT_RECEIVE_INT_ENA_V 0x00000001U +#define TWAI_EXT_RECEIVE_INT_ENA_S 0 +/** TWAI_EXT_TRANSMIT_INT_ENA : R/W; bitpos: [1]; default: 0; + * 1: enabled, when a message has been successfully transmitted or the transmit buffer + * is accessible again (e.g. after an abort transmission command), the TWAI controller + * requests the respective interrupt. 0: disable + */ +#define TWAI_EXT_TRANSMIT_INT_ENA (BIT(1)) +#define TWAI_EXT_TRANSMIT_INT_ENA_M (TWAI_EXT_TRANSMIT_INT_ENA_V << TWAI_EXT_TRANSMIT_INT_ENA_S) +#define TWAI_EXT_TRANSMIT_INT_ENA_V 0x00000001U +#define TWAI_EXT_TRANSMIT_INT_ENA_S 1 +/** TWAI_EXT_ERR_WARNING_INT_ENA : R/W; bitpos: [2]; default: 0; + * 1: enabled, if the error or bus status change (see status register. Table 14), the + * TWAI controllerrequests the respective interrupt. 0: disable + */ +#define TWAI_EXT_ERR_WARNING_INT_ENA (BIT(2)) +#define TWAI_EXT_ERR_WARNING_INT_ENA_M (TWAI_EXT_ERR_WARNING_INT_ENA_V << TWAI_EXT_ERR_WARNING_INT_ENA_S) +#define TWAI_EXT_ERR_WARNING_INT_ENA_V 0x00000001U +#define TWAI_EXT_ERR_WARNING_INT_ENA_S 2 +/** TWAI_EXT_DATA_OVERRUN_INT_ENA : R/W; bitpos: [3]; default: 0; + * 1: enabled, if the data overrun status bit is set (see status register. Table 14), + * the TWAI controllerrequests the respective interrupt. 0: disable + */ +#define TWAI_EXT_DATA_OVERRUN_INT_ENA (BIT(3)) +#define TWAI_EXT_DATA_OVERRUN_INT_ENA_M (TWAI_EXT_DATA_OVERRUN_INT_ENA_V << TWAI_EXT_DATA_OVERRUN_INT_ENA_S) +#define TWAI_EXT_DATA_OVERRUN_INT_ENA_V 0x00000001U +#define TWAI_EXT_DATA_OVERRUN_INT_ENA_S 3 +/** TWAI_ERR_PASSIVE_INT_ENA : R/W; bitpos: [5]; default: 0; + * 1: enabled, if the error status of the TWAI controller changes from error active to + * error passive or vice versa, the respective interrupt is requested. 0: disable + */ +#define TWAI_ERR_PASSIVE_INT_ENA (BIT(5)) +#define TWAI_ERR_PASSIVE_INT_ENA_M (TWAI_ERR_PASSIVE_INT_ENA_V << TWAI_ERR_PASSIVE_INT_ENA_S) +#define TWAI_ERR_PASSIVE_INT_ENA_V 0x00000001U +#define TWAI_ERR_PASSIVE_INT_ENA_S 5 +/** TWAI_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [6]; default: 0; + * 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt + * is requested. 0: disable + */ +#define TWAI_ARBITRATION_LOST_INT_ENA (BIT(6)) +#define TWAI_ARBITRATION_LOST_INT_ENA_M (TWAI_ARBITRATION_LOST_INT_ENA_V << TWAI_ARBITRATION_LOST_INT_ENA_S) +#define TWAI_ARBITRATION_LOST_INT_ENA_V 0x00000001U +#define TWAI_ARBITRATION_LOST_INT_ENA_S 6 +/** TWAI_BUS_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * 1: enabled, if an bus error has been detected, the TWAI controller requests the + * respective interrupt. 0: disable + */ +#define TWAI_BUS_ERR_INT_ENA (BIT(7)) +#define TWAI_BUS_ERR_INT_ENA_M (TWAI_BUS_ERR_INT_ENA_V << TWAI_BUS_ERR_INT_ENA_S) +#define TWAI_BUS_ERR_INT_ENA_V 0x00000001U +#define TWAI_BUS_ERR_INT_ENA_S 7 +/** TWAI_IDLE_INT_ENA : RO; bitpos: [8]; default: 0; + * 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the + * respective interrupt. 0: disable + */ +#define TWAI_IDLE_INT_ENA (BIT(8)) +#define TWAI_IDLE_INT_ENA_M (TWAI_IDLE_INT_ENA_V << TWAI_IDLE_INT_ENA_S) +#define TWAI_IDLE_INT_ENA_V 0x00000001U +#define TWAI_IDLE_INT_ENA_S 8 + +/** TWAI_BUS_TIMING_0_REG register + * Bit timing configuration register 0. + */ +#define TWAI_BUS_TIMING_0_REG(i) (REG_TWAI_BASE(i) + 0x18) +/** TWAI_BAUD_PRESC : R/W; bitpos: [13:0]; default: 0; + * The period of the TWAI system clock is programmable and determines the individual + * bit timing. Software has R/W permission in reset mode and RO permission in + * operation mode. + */ +#define TWAI_BAUD_PRESC 0x00003FFFU +#define TWAI_BAUD_PRESC_M (TWAI_BAUD_PRESC_V << TWAI_BAUD_PRESC_S) +#define TWAI_BAUD_PRESC_V 0x00003FFFU +#define TWAI_BAUD_PRESC_S 0 +/** TWAI_SYNC_JUMP_WIDTH : R/W; bitpos: [15:14]; default: 0; + * The synchronization jump width defines the maximum number of clock cycles a bit + * period may be shortened or lengthened. Software has R/W permission in reset mode + * and RO in operation mode. + */ +#define TWAI_SYNC_JUMP_WIDTH 0x00000003U +#define TWAI_SYNC_JUMP_WIDTH_M (TWAI_SYNC_JUMP_WIDTH_V << TWAI_SYNC_JUMP_WIDTH_S) +#define TWAI_SYNC_JUMP_WIDTH_V 0x00000003U +#define TWAI_SYNC_JUMP_WIDTH_S 14 + +/** TWAI_BUS_TIMING_1_REG register + * Bit timing configuration register 1. + */ +#define TWAI_BUS_TIMING_1_REG(i) (REG_TWAI_BASE(i) + 0x1c) +/** TWAI_TIME_SEGMENT1 : R/W; bitpos: [3:0]; default: 0; + * The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ +#define TWAI_TIME_SEGMENT1 0x0000000FU +#define TWAI_TIME_SEGMENT1_M (TWAI_TIME_SEGMENT1_V << TWAI_TIME_SEGMENT1_S) +#define TWAI_TIME_SEGMENT1_V 0x0000000FU +#define TWAI_TIME_SEGMENT1_S 0 +/** TWAI_TIME_SEGMENT2 : R/W; bitpos: [6:4]; default: 0; + * The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ +#define TWAI_TIME_SEGMENT2 0x00000007U +#define TWAI_TIME_SEGMENT2_M (TWAI_TIME_SEGMENT2_V << TWAI_TIME_SEGMENT2_S) +#define TWAI_TIME_SEGMENT2_V 0x00000007U +#define TWAI_TIME_SEGMENT2_S 4 +/** TWAI_TIME_SAMPLING : R/W; bitpos: [7]; default: 0; + * 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. + * Software has R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_TIME_SAMPLING (BIT(7)) +#define TWAI_TIME_SAMPLING_M (TWAI_TIME_SAMPLING_V << TWAI_TIME_SAMPLING_S) +#define TWAI_TIME_SAMPLING_V 0x00000001U +#define TWAI_TIME_SAMPLING_S 7 + +/** TWAI_ARB_LOST_CAP_REG register + * TWAI arbiter lost capture register. + */ +#define TWAI_ARB_LOST_CAP_REG(i) (REG_TWAI_BASE(i) + 0x2c) +/** TWAI_ARBITRATION_LOST_CAPTURE : RO; bitpos: [4:0]; default: 0; + * This register contains information about the bit position of losing arbitration. + */ +#define TWAI_ARBITRATION_LOST_CAPTURE 0x0000001FU +#define TWAI_ARBITRATION_LOST_CAPTURE_M (TWAI_ARBITRATION_LOST_CAPTURE_V << TWAI_ARBITRATION_LOST_CAPTURE_S) +#define TWAI_ARBITRATION_LOST_CAPTURE_V 0x0000001FU +#define TWAI_ARBITRATION_LOST_CAPTURE_S 0 + +/** TWAI_ERR_CODE_CAP_REG register + * TWAI error info capture register. + */ +#define TWAI_ERR_CODE_CAP_REG(i) (REG_TWAI_BASE(i) + 0x30) +/** TWAI_ERR_CAPTURE_CODE_SEGMENT : RO; bitpos: [4:0]; default: 0; + * This register contains information about the location of errors on the bus. + */ +#define TWAI_ERR_CAPTURE_CODE_SEGMENT 0x0000001FU +#define TWAI_ERR_CAPTURE_CODE_SEGMENT_M (TWAI_ERR_CAPTURE_CODE_SEGMENT_V << TWAI_ERR_CAPTURE_CODE_SEGMENT_S) +#define TWAI_ERR_CAPTURE_CODE_SEGMENT_V 0x0000001FU +#define TWAI_ERR_CAPTURE_CODE_SEGMENT_S 0 +/** TWAI_ERR_CAPTURE_CODE_DIRECTION : RO; bitpos: [5]; default: 0; + * 1: RX, error occurred during reception. 0: TX, error occurred during transmission. + */ +#define TWAI_ERR_CAPTURE_CODE_DIRECTION (BIT(5)) +#define TWAI_ERR_CAPTURE_CODE_DIRECTION_M (TWAI_ERR_CAPTURE_CODE_DIRECTION_V << TWAI_ERR_CAPTURE_CODE_DIRECTION_S) +#define TWAI_ERR_CAPTURE_CODE_DIRECTION_V 0x00000001U +#define TWAI_ERR_CAPTURE_CODE_DIRECTION_S 5 +/** TWAI_ERR_CAPTURE_CODE_TYPE : RO; bitpos: [7:6]; default: 0; + * 00: bit error. 01: form error. 10:stuff error. 11:other type of error. + */ +#define TWAI_ERR_CAPTURE_CODE_TYPE 0x00000003U +#define TWAI_ERR_CAPTURE_CODE_TYPE_M (TWAI_ERR_CAPTURE_CODE_TYPE_V << TWAI_ERR_CAPTURE_CODE_TYPE_S) +#define TWAI_ERR_CAPTURE_CODE_TYPE_V 0x00000003U +#define TWAI_ERR_CAPTURE_CODE_TYPE_S 6 + +/** TWAI_ERR_WARNING_LIMIT_REG register + * TWAI error threshold configuration register. + */ +#define TWAI_ERR_WARNING_LIMIT_REG(i) (REG_TWAI_BASE(i) + 0x34) +/** TWAI_ERR_WARNING_LIMIT : R/W; bitpos: [7:0]; default: 96; + * The threshold that trigger error warning interrupt when this interrupt is enabled. + * Software has R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_ERR_WARNING_LIMIT 0x000000FFU +#define TWAI_ERR_WARNING_LIMIT_M (TWAI_ERR_WARNING_LIMIT_V << TWAI_ERR_WARNING_LIMIT_S) +#define TWAI_ERR_WARNING_LIMIT_V 0x000000FFU +#define TWAI_ERR_WARNING_LIMIT_S 0 + +/** TWAI_RX_ERR_CNT_REG register + * Rx error counter register. + */ +#define TWAI_RX_ERR_CNT_REG(i) (REG_TWAI_BASE(i) + 0x38) +/** TWAI_RX_ERR_CNT : R/W; bitpos: [7:0]; default: 0; + * The RX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_RX_ERR_CNT 0x000000FFU +#define TWAI_RX_ERR_CNT_M (TWAI_RX_ERR_CNT_V << TWAI_RX_ERR_CNT_S) +#define TWAI_RX_ERR_CNT_V 0x000000FFU +#define TWAI_RX_ERR_CNT_S 0 + +/** TWAI_TX_ERR_CNT_REG register + * Tx error counter register. + */ +#define TWAI_TX_ERR_CNT_REG(i) (REG_TWAI_BASE(i) + 0x3c) +/** TWAI_TX_ERR_CNT : R/W; bitpos: [7:0]; default: 0; + * The TX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_TX_ERR_CNT 0x000000FFU +#define TWAI_TX_ERR_CNT_M (TWAI_TX_ERR_CNT_V << TWAI_TX_ERR_CNT_S) +#define TWAI_TX_ERR_CNT_V 0x000000FFU +#define TWAI_TX_ERR_CNT_S 0 + +/** TWAI_DATA_0_REG register + * Data register 0. + */ +#define TWAI_DATA_0_REG(i) (REG_TWAI_BASE(i) + 0x40) +/** TWAI_DATA_0 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 0 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 0 and when + * software initiate read operation, it is rx data register 0. + */ +#define TWAI_DATA_0 0x000000FFU +#define TWAI_DATA_0_M (TWAI_DATA_0_V << TWAI_DATA_0_S) +#define TWAI_DATA_0_V 0x000000FFU +#define TWAI_DATA_0_S 0 + +/** TWAI_DATA_1_REG register + * Data register 1. + */ +#define TWAI_DATA_1_REG(i) (REG_TWAI_BASE(i) + 0x44) +/** TWAI_DATA_1 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 1 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 1 and when + * software initiate read operation, it is rx data register 1. + */ +#define TWAI_DATA_1 0x000000FFU +#define TWAI_DATA_1_M (TWAI_DATA_1_V << TWAI_DATA_1_S) +#define TWAI_DATA_1_V 0x000000FFU +#define TWAI_DATA_1_S 0 + +/** TWAI_DATA_2_REG register + * Data register 2. + */ +#define TWAI_DATA_2_REG(i) (REG_TWAI_BASE(i) + 0x48) +/** TWAI_DATA_2 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 2 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 2 and when + * software initiate read operation, it is rx data register 2. + */ +#define TWAI_DATA_2 0x000000FFU +#define TWAI_DATA_2_M (TWAI_DATA_2_V << TWAI_DATA_2_S) +#define TWAI_DATA_2_V 0x000000FFU +#define TWAI_DATA_2_S 0 + +/** TWAI_DATA_3_REG register + * Data register 3. + */ +#define TWAI_DATA_3_REG(i) (REG_TWAI_BASE(i) + 0x4c) +/** TWAI_DATA_3 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 3 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 3 and when + * software initiate read operation, it is rx data register 3. + */ +#define TWAI_DATA_3 0x000000FFU +#define TWAI_DATA_3_M (TWAI_DATA_3_V << TWAI_DATA_3_S) +#define TWAI_DATA_3_V 0x000000FFU +#define TWAI_DATA_3_S 0 + +/** TWAI_DATA_4_REG register + * Data register 4. + */ +#define TWAI_DATA_4_REG(i) (REG_TWAI_BASE(i) + 0x50) +/** TWAI_DATA_4 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 0 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 4 and when + * software initiate read operation, it is rx data register 4. + */ +#define TWAI_DATA_4 0x000000FFU +#define TWAI_DATA_4_M (TWAI_DATA_4_V << TWAI_DATA_4_S) +#define TWAI_DATA_4_V 0x000000FFU +#define TWAI_DATA_4_S 0 + +/** TWAI_DATA_5_REG register + * Data register 5. + */ +#define TWAI_DATA_5_REG(i) (REG_TWAI_BASE(i) + 0x54) +/** TWAI_DATA_5 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 1 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 5 and when + * software initiate read operation, it is rx data register 5. + */ +#define TWAI_DATA_5 0x000000FFU +#define TWAI_DATA_5_M (TWAI_DATA_5_V << TWAI_DATA_5_S) +#define TWAI_DATA_5_V 0x000000FFU +#define TWAI_DATA_5_S 0 + +/** TWAI_DATA_6_REG register + * Data register 6. + */ +#define TWAI_DATA_6_REG(i) (REG_TWAI_BASE(i) + 0x58) +/** TWAI_DATA_6 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 2 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 6 and when + * software initiate read operation, it is rx data register 6. + */ +#define TWAI_DATA_6 0x000000FFU +#define TWAI_DATA_6_M (TWAI_DATA_6_V << TWAI_DATA_6_S) +#define TWAI_DATA_6_V 0x000000FFU +#define TWAI_DATA_6_S 0 + +/** TWAI_DATA_7_REG register + * Data register 7. + */ +#define TWAI_DATA_7_REG(i) (REG_TWAI_BASE(i) + 0x5c) +/** TWAI_DATA_7 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 3 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 7 and when + * software initiate read operation, it is rx data register 7. + */ +#define TWAI_DATA_7 0x000000FFU +#define TWAI_DATA_7_M (TWAI_DATA_7_V << TWAI_DATA_7_S) +#define TWAI_DATA_7_V 0x000000FFU +#define TWAI_DATA_7_S 0 + +/** TWAI_DATA_8_REG register + * Data register 8. + */ +#define TWAI_DATA_8_REG(i) (REG_TWAI_BASE(i) + 0x60) +/** TWAI_DATA_8 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 8 and when software initiate read operation, it + * is rx data register 8. + */ +#define TWAI_DATA_8 0x000000FFU +#define TWAI_DATA_8_M (TWAI_DATA_8_V << TWAI_DATA_8_S) +#define TWAI_DATA_8_V 0x000000FFU +#define TWAI_DATA_8_S 0 + +/** TWAI_DATA_9_REG register + * Data register 9. + */ +#define TWAI_DATA_9_REG(i) (REG_TWAI_BASE(i) + 0x64) +/** TWAI_DATA_9 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 9 and when software initiate read operation, it + * is rx data register 9. + */ +#define TWAI_DATA_9 0x000000FFU +#define TWAI_DATA_9_M (TWAI_DATA_9_V << TWAI_DATA_9_S) +#define TWAI_DATA_9_V 0x000000FFU +#define TWAI_DATA_9_S 0 + +/** TWAI_DATA_10_REG register + * Data register 10. + */ +#define TWAI_DATA_10_REG(i) (REG_TWAI_BASE(i) + 0x68) +/** TWAI_DATA_10 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 10 and when software initiate read operation, it + * is rx data register 10. + */ +#define TWAI_DATA_10 0x000000FFU +#define TWAI_DATA_10_M (TWAI_DATA_10_V << TWAI_DATA_10_S) +#define TWAI_DATA_10_V 0x000000FFU +#define TWAI_DATA_10_S 0 + +/** TWAI_DATA_11_REG register + * Data register 11. + */ +#define TWAI_DATA_11_REG(i) (REG_TWAI_BASE(i) + 0x6c) +/** TWAI_DATA_11 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 11 and when software initiate read operation, it + * is rx data register 11. + */ +#define TWAI_DATA_11 0x000000FFU +#define TWAI_DATA_11_M (TWAI_DATA_11_V << TWAI_DATA_11_S) +#define TWAI_DATA_11_V 0x000000FFU +#define TWAI_DATA_11_S 0 + +/** TWAI_DATA_12_REG register + * Data register 12. + */ +#define TWAI_DATA_12_REG(i) (REG_TWAI_BASE(i) + 0x70) +/** TWAI_DATA_12 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 12 and when software initiate read operation, it + * is rx data register 12. + */ +#define TWAI_DATA_12 0x000000FFU +#define TWAI_DATA_12_M (TWAI_DATA_12_V << TWAI_DATA_12_S) +#define TWAI_DATA_12_V 0x000000FFU +#define TWAI_DATA_12_S 0 + +/** TWAI_RX_MESSAGE_COUNTER_REG register + * Received message counter register. + */ +#define TWAI_RX_MESSAGE_COUNTER_REG(i) (REG_TWAI_BASE(i) + 0x74) +/** TWAI_RX_MESSAGE_COUNTER : RO; bitpos: [6:0]; default: 0; + * Reflects the number of messages available within the RXFIFO. The value is + * incremented with each receive event and decremented by the release receive buffer + * command. + */ +#define TWAI_RX_MESSAGE_COUNTER 0x0000007FU +#define TWAI_RX_MESSAGE_COUNTER_M (TWAI_RX_MESSAGE_COUNTER_V << TWAI_RX_MESSAGE_COUNTER_S) +#define TWAI_RX_MESSAGE_COUNTER_V 0x0000007FU +#define TWAI_RX_MESSAGE_COUNTER_S 0 + +/** TWAI_CLOCK_DIVIDER_REG register + * Clock divider register. + */ +#define TWAI_CLOCK_DIVIDER_REG(i) (REG_TWAI_BASE(i) + 0x7c) +/** TWAI_CD : R/W; bitpos: [7:0]; default: 0; + * These bits are used to define the frequency at the external CLKOUT pin. + */ +#define TWAI_CD 0x000000FFU +#define TWAI_CD_M (TWAI_CD_V << TWAI_CD_S) +#define TWAI_CD_V 0x000000FFU +#define TWAI_CD_S 0 +/** TWAI_CLOCK_OFF : R/W; bitpos: [8]; default: 0; + * 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has + * R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_CLOCK_OFF (BIT(8)) +#define TWAI_CLOCK_OFF_M (TWAI_CLOCK_OFF_V << TWAI_CLOCK_OFF_S) +#define TWAI_CLOCK_OFF_V 0x00000001U +#define TWAI_CLOCK_OFF_S 8 + +/** TWAI_SW_STANDBY_CFG_REG register + * Software configure standby pin directly. + */ +#define TWAI_SW_STANDBY_CFG_REG(i) (REG_TWAI_BASE(i) + 0x80) +/** TWAI_SW_STANDBY_EN : R/W; bitpos: [0]; default: 0; + * Enable standby pin. + */ +#define TWAI_SW_STANDBY_EN (BIT(0)) +#define TWAI_SW_STANDBY_EN_M (TWAI_SW_STANDBY_EN_V << TWAI_SW_STANDBY_EN_S) +#define TWAI_SW_STANDBY_EN_V 0x00000001U +#define TWAI_SW_STANDBY_EN_S 0 +/** TWAI_SW_STANDBY_CLR : R/W; bitpos: [1]; default: 1; + * Clear standby pin. + */ +#define TWAI_SW_STANDBY_CLR (BIT(1)) +#define TWAI_SW_STANDBY_CLR_M (TWAI_SW_STANDBY_CLR_V << TWAI_SW_STANDBY_CLR_S) +#define TWAI_SW_STANDBY_CLR_V 0x00000001U +#define TWAI_SW_STANDBY_CLR_S 1 + +/** TWAI_HW_CFG_REG register + * Hardware configure standby pin. + */ +#define TWAI_HW_CFG_REG(i) (REG_TWAI_BASE(i) + 0x84) +/** TWAI_HW_STANDBY_EN : R/W; bitpos: [0]; default: 0; + * Enable function that hardware control standby pin. + */ +#define TWAI_HW_STANDBY_EN (BIT(0)) +#define TWAI_HW_STANDBY_EN_M (TWAI_HW_STANDBY_EN_V << TWAI_HW_STANDBY_EN_S) +#define TWAI_HW_STANDBY_EN_V 0x00000001U +#define TWAI_HW_STANDBY_EN_S 0 + +/** TWAI_HW_STANDBY_CNT_REG register + * Configure standby counter. + */ +#define TWAI_HW_STANDBY_CNT_REG(i) (REG_TWAI_BASE(i) + 0x88) +/** TWAI_STANDBY_WAIT_CNT : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN + * is enabled. + */ +#define TWAI_STANDBY_WAIT_CNT 0xFFFFFFFFU +#define TWAI_STANDBY_WAIT_CNT_M (TWAI_STANDBY_WAIT_CNT_V << TWAI_STANDBY_WAIT_CNT_S) +#define TWAI_STANDBY_WAIT_CNT_V 0xFFFFFFFFU +#define TWAI_STANDBY_WAIT_CNT_S 0 + +/** TWAI_IDLE_INTR_CNT_REG register + * Configure idle interrupt counter. + */ +#define TWAI_IDLE_INTR_CNT_REG(i) (REG_TWAI_BASE(i) + 0x8c) +/** TWAI_IDLE_INTR_CNT : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before triggering idle interrupt. + */ +#define TWAI_IDLE_INTR_CNT 0xFFFFFFFFU +#define TWAI_IDLE_INTR_CNT_M (TWAI_IDLE_INTR_CNT_V << TWAI_IDLE_INTR_CNT_S) +#define TWAI_IDLE_INTR_CNT_V 0xFFFFFFFFU +#define TWAI_IDLE_INTR_CNT_S 0 + +/** TWAI_ECO_CFG_REG register + * ECO configuration register. + */ +#define TWAI_ECO_CFG_REG(i) (REG_TWAI_BASE(i) + 0x90) +/** TWAI_RDN_ENA : R/W; bitpos: [0]; default: 0; + * Enable eco module. + */ +#define TWAI_RDN_ENA (BIT(0)) +#define TWAI_RDN_ENA_M (TWAI_RDN_ENA_V << TWAI_RDN_ENA_S) +#define TWAI_RDN_ENA_V 0x00000001U +#define TWAI_RDN_ENA_S 0 +/** TWAI_RDN_RESULT : RO; bitpos: [1]; default: 1; + * Output of eco module. + */ +#define TWAI_RDN_RESULT (BIT(1)) +#define TWAI_RDN_RESULT_M (TWAI_RDN_RESULT_V << TWAI_RDN_RESULT_S) +#define TWAI_RDN_RESULT_V 0x00000001U +#define TWAI_RDN_RESULT_S 1 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/twai_struct.h b/components/soc/esp32c6/include/soc/twai_struct.h new file mode 100644 index 0000000000..11220fc1f2 --- /dev/null +++ b/components/soc/esp32c6/include/soc/twai_struct.h @@ -0,0 +1,541 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of mode register + * TWAI mode register. + */ +typedef union { + struct { + /** reset_mode : R/W; bitpos: [0]; default: 1; + * 1: reset, detection of a set reset mode bit results in aborting the current + * transmission/reception of a message and entering the reset mode. 0: normal, on the + * '1-to-0' transition of the reset mode bit, the TWAI controller returns to the + * operating mode. + */ + uint32_t reset_mode:1; + /** listen_only_mode : R/W; bitpos: [1]; default: 0; + * 1: listen only, in this mode the TWAI controller would give no acknowledge to the + * TWAI-bus, even if a message is received successfully. The error counters are + * stopped at the current value. 0: normal. + */ + uint32_t listen_only_mode:1; + /** self_test_mode : R/W; bitpos: [2]; default: 0; + * 1: self test, in this mode a full node test is possible without any other active + * node on the bus using the self reception request command. The TWAI controller will + * perform a successful transmission, even if there is no acknowledge received. 0: + * normal, an acknowledge is required for successful transmission. + */ + uint32_t self_test_mode:1; + /** acceptance_filter_mode : R/W; bitpos: [3]; default: 0; + * 1:single, the single acceptance filter option is enabled (one filter with the + * length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled + * (two filters, each with the length of 16 bit are active). + */ + uint32_t acceptance_filter_mode:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} twai_mode_reg_t; + +/** Type of cmd register + * TWAI command register. + */ +typedef union { + struct { + /** tx_request : WO; bitpos: [0]; default: 0; + * 1: present, a message shall be transmitted. 0: absent + */ + uint32_t tx_request:1; + /** abort_tx : WO; bitpos: [1]; default: 0; + * 1: present, if not already in progress, a pending transmission request is + * cancelled. 0: absent + */ + uint32_t abort_tx:1; + /** release_buffer : WO; bitpos: [2]; default: 0; + * 1: released, the receive buffer, representing the message memory space in the + * RXFIFO is released. 0: no action + */ + uint32_t release_buffer:1; + /** clear_data_overrun : WO; bitpos: [3]; default: 0; + * 1: clear, the data overrun status bit is cleared. 0: no action. + */ + uint32_t clear_data_overrun:1; + /** self_rx_request : WO; bitpos: [4]; default: 0; + * 1: present, a message shall be transmitted and received simultaneously. 0: absent. + */ + uint32_t self_rx_request:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} twai_cmd_reg_t; + +/** Type of bus_timing_0 register + * Bit timing configuration register 0. + */ +typedef union { + struct { + /** baud_presc : R/W; bitpos: [13:0]; default: 0; + * The period of the TWAI system clock is programmable and determines the individual + * bit timing. Software has R/W permission in reset mode and RO permission in + * operation mode. + */ + uint32_t baud_presc:14; + /** sync_jump_width : R/W; bitpos: [15:14]; default: 0; + * The synchronization jump width defines the maximum number of clock cycles a bit + * period may be shortened or lengthened. Software has R/W permission in reset mode + * and RO in operation mode. + */ + uint32_t sync_jump_width:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} twai_bus_timing_0_reg_t; + +/** Type of bus_timing_1 register + * Bit timing configuration register 1. + */ +typedef union { + struct { + /** time_segment1 : R/W; bitpos: [3:0]; default: 0; + * The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ + uint32_t time_segment1:4; + /** time_segment2 : R/W; bitpos: [6:4]; default: 0; + * The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ + uint32_t time_segment2:3; + /** time_sampling : R/W; bitpos: [7]; default: 0; + * 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. + * Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t time_sampling:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_bus_timing_1_reg_t; + +/** Type of err_warning_limit register + * TWAI error threshold configuration register. + */ +typedef union { + struct { + /** err_warning_limit : R/W; bitpos: [7:0]; default: 96; + * The threshold that trigger error warning interrupt when this interrupt is enabled. + * Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t err_warning_limit:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_err_warning_limit_reg_t; + +/** Type of clock_divider register + * Clock divider register. + */ +typedef union { + struct { + /** cd : R/W; bitpos: [7:0]; default: 0; + * These bits are used to define the frequency at the external CLKOUT pin. + */ + uint32_t cd:8; + /** clock_off : R/W; bitpos: [8]; default: 0; + * 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has + * R/W permission in reset mode and RO in operation mode. + */ + uint32_t clock_off:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_clock_divider_reg_t; + +/** Type of sw_standby_cfg register + * Software configure standby pin directly. + */ +typedef union { + struct { + /** sw_standby_en : R/W; bitpos: [0]; default: 0; + * Enable standby pin. + */ + uint32_t sw_standby_en:1; + /** sw_standby_clr : R/W; bitpos: [1]; default: 1; + * Clear standby pin. + */ + uint32_t sw_standby_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} twai_sw_standby_cfg_reg_t; + +/** Type of hw_cfg register + * Hardware configure standby pin. + */ +typedef union { + struct { + /** hw_standby_en : R/W; bitpos: [0]; default: 0; + * Enable function that hardware control standby pin. + */ + uint32_t hw_standby_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} twai_hw_cfg_reg_t; + +/** Type of hw_standby_cnt register + * Configure standby counter. + */ +typedef union { + struct { + /** standby_wait_cnt : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN + * is enabled. + */ + uint32_t standby_wait_cnt:32; + }; + uint32_t val; +} twai_hw_standby_cnt_reg_t; + +/** Type of idle_intr_cnt register + * Configure idle interrupt counter. + */ +typedef union { + struct { + /** idle_intr_cnt : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before triggering idle interrupt. + */ + uint32_t idle_intr_cnt:32; + }; + uint32_t val; +} twai_idle_intr_cnt_reg_t; + +/** Type of eco_cfg register + * ECO configuration register. + */ +typedef union { + struct { + /** rdn_ena : R/W; bitpos: [0]; default: 0; + * Enable eco module. + */ + uint32_t rdn_ena:1; + /** rdn_result : RO; bitpos: [1]; default: 1; + * Output of eco module. + */ + uint32_t rdn_result:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} twai_eco_cfg_reg_t; + + +/** Group: Status Registers */ +/** Type of status register + * TWAI status register. + */ +typedef union { + struct { + /** status_receive_buffer : RO; bitpos: [0]; default: 0; + * 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no + * message is available + */ + uint32_t status_receive_buffer:1; + /** status_overrun : RO; bitpos: [1]; default: 0; + * 1: overrun, a message was lost because there was not enough space for that message + * in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data + * overrun command was given + */ + uint32_t status_overrun:1; + /** status_transmit_buffer : RO; bitpos: [2]; default: 0; + * 1: released, the CPU may write a message into the transmit buffer. 0: locked, the + * CPU cannot access the transmit buffer, a message is either waiting for transmission + * or is in the process of being transmitted + */ + uint32_t status_transmit_buffer:1; + /** status_transmission_complete : RO; bitpos: [3]; default: 0; + * 1: complete, last requested transmission has been successfully completed. 0: + * incomplete, previously requested transmission is not yet completed + */ + uint32_t status_transmission_complete:1; + /** status_receive : RO; bitpos: [4]; default: 0; + * 1: receive, the TWAI controller is receiving a message. 0: idle + */ + uint32_t status_receive:1; + /** status_transmit : RO; bitpos: [5]; default: 0; + * 1: transmit, the TWAI controller is transmitting a message. 0: idle + */ + uint32_t status_transmit:1; + /** status_err : RO; bitpos: [6]; default: 0; + * 1: error, at least one of the error counters has reached or exceeded the CPU + * warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error + * counters are below the warning limit + */ + uint32_t status_err:1; + /** status_node_bus_off : RO; bitpos: [7]; default: 0; + * 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the + * TWAI controller is involved in bus activities + */ + uint32_t status_node_bus_off:1; + /** status_miss : RO; bitpos: [8]; default: 0; + * 1: current message is destroyed because of FIFO overflow. + */ + uint32_t status_miss:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_status_reg_t; + +/** Type of arb_lost_cap register + * TWAI arbiter lost capture register. + */ +typedef union { + struct { + /** arbitration_lost_capture : RO; bitpos: [4:0]; default: 0; + * This register contains information about the bit position of losing arbitration. + */ + uint32_t arbitration_lost_capture:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} twai_arb_lost_cap_reg_t; + +/** Type of err_code_cap register + * TWAI error info capture register. + */ +typedef union { + struct { + /** err_capture_code_segment : RO; bitpos: [4:0]; default: 0; + * This register contains information about the location of errors on the bus. + */ + uint32_t err_capture_code_segment:5; + /** err_capture_code_direction : RO; bitpos: [5]; default: 0; + * 1: RX, error occurred during reception. 0: TX, error occurred during transmission. + */ + uint32_t err_capture_code_direction:1; + /** err_capture_code_type : RO; bitpos: [7:6]; default: 0; + * 00: bit error. 01: form error. 10:stuff error. 11:other type of error. + */ + uint32_t err_capture_code_type:2; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_err_code_cap_reg_t; + +/** Type of rx_err_cnt register + * Rx error counter register. + */ +typedef union { + struct { + /** rx_err_cnt : R/W; bitpos: [7:0]; default: 0; + * The RX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t rx_err_cnt:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_rx_err_cnt_reg_t; + +/** Type of tx_err_cnt register + * Tx error counter register. + */ +typedef union { + struct { + /** tx_err_cnt : R/W; bitpos: [7:0]; default: 0; + * The TX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t tx_err_cnt:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_tx_err_cnt_reg_t; + +/** Type of rx_message_counter register + * Received message counter register. + */ +typedef union { + struct { + /** rx_message_counter : RO; bitpos: [6:0]; default: 0; + * Reflects the number of messages available within the RXFIFO. The value is + * incremented with each receive event and decremented by the release receive buffer + * command. + */ + uint32_t rx_message_counter:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} twai_rx_message_counter_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of interrupt register + * Interrupt signals' register. + */ +typedef union { + struct { + /** receive_int_st : RO; bitpos: [0]; default: 0; + * 1: this bit is set while the receive FIFO is not empty and the RIE bit is set + * within the interrupt enable register. 0: reset + */ + uint32_t receive_int_st:1; + /** transmit_int_st : RO; bitpos: [1]; default: 0; + * 1: this bit is set whenever the transmit buffer status changes from '0-to-1' + * (released) and the TIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t transmit_int_st:1; + /** err_warning_int_st : RO; bitpos: [2]; default: 0; + * 1: this bit is set on every change (set and clear) of either the error status or + * bus status bits and the EIE bit is set within the interrupt enable register. 0: + * reset + */ + uint32_t err_warning_int_st:1; + /** data_overrun_int_st : RO; bitpos: [3]; default: 0; + * 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the + * DOIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t data_overrun_int_st:1; + uint32_t reserved_4:1; + /** err_passive_int_st : RO; bitpos: [5]; default: 0; + * 1: this bit is set whenever the TWAI controller has reached the error passive + * status (at least one error counter exceeds the protocol-defined level of 127) or if + * the TWAI controller is in the error passive status and enters the error active + * status again and the EPIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t err_passive_int_st:1; + /** arbitration_lost_int_st : RO; bitpos: [6]; default: 0; + * 1: this bit is set when the TWAI controller lost the arbitration and becomes a + * receiver and the ALIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t arbitration_lost_int_st:1; + /** bus_err_int_st : RO; bitpos: [7]; default: 0; + * 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and + * the BEIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t bus_err_int_st:1; + /** idle_int_st : RO; bitpos: [8]; default: 0; + * 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and + * this interrupt enable bit is set within the interrupt enable register. 0: reset + */ + uint32_t idle_int_st:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_interrupt_reg_t; + +/** Type of interrupt_enable register + * Interrupt enable register. + */ +typedef union { + struct { + /** ext_receive_int_ena : R/W; bitpos: [0]; default: 0; + * 1: enabled, when the receive buffer status is 'full' the TWAI controller requests + * the respective interrupt. 0: disable + */ + uint32_t ext_receive_int_ena:1; + /** ext_transmit_int_ena : R/W; bitpos: [1]; default: 0; + * 1: enabled, when a message has been successfully transmitted or the transmit buffer + * is accessible again (e.g. after an abort transmission command), the TWAI controller + * requests the respective interrupt. 0: disable + */ + uint32_t ext_transmit_int_ena:1; + /** ext_err_warning_int_ena : R/W; bitpos: [2]; default: 0; + * 1: enabled, if the error or bus status change (see status register. Table 14), the + * TWAI controllerrequests the respective interrupt. 0: disable + */ + uint32_t ext_err_warning_int_ena:1; + /** ext_data_overrun_int_ena : R/W; bitpos: [3]; default: 0; + * 1: enabled, if the data overrun status bit is set (see status register. Table 14), + * the TWAI controllerrequests the respective interrupt. 0: disable + */ + uint32_t ext_data_overrun_int_ena:1; + uint32_t reserved_4:1; + /** err_passive_int_ena : R/W; bitpos: [5]; default: 0; + * 1: enabled, if the error status of the TWAI controller changes from error active to + * error passive or vice versa, the respective interrupt is requested. 0: disable + */ + uint32_t err_passive_int_ena:1; + /** arbitration_lost_int_ena : R/W; bitpos: [6]; default: 0; + * 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt + * is requested. 0: disable + */ + uint32_t arbitration_lost_int_ena:1; + /** bus_err_int_ena : R/W; bitpos: [7]; default: 0; + * 1: enabled, if an bus error has been detected, the TWAI controller requests the + * respective interrupt. 0: disable + */ + uint32_t bus_err_int_ena:1; + /** idle_int_ena : RO; bitpos: [8]; default: 0; + * 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the + * respective interrupt. 0: disable + */ + uint32_t idle_int_ena:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_interrupt_enable_reg_t; + + +/** Group: Data Registers */ +/** Type of buffer register + * TX RX Buffer. + */ +typedef union { + struct { + /** byte : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 0 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 0 and when + * software initiate read operation, it is rx data register 0. + */ + uint32_t byte:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_tx_rx_buffer_reg_t; + + +typedef struct twai_dev_s { + volatile twai_mode_reg_t mode; + volatile twai_cmd_reg_t cmd; + volatile twai_status_reg_t status; + volatile twai_interrupt_reg_t interrupt; + volatile twai_interrupt_enable_reg_t interrupt_enable; + uint32_t reserved_014; + volatile twai_bus_timing_0_reg_t bus_timing_0; + volatile twai_bus_timing_1_reg_t bus_timing_1; + uint32_t reserved_020[3]; + volatile twai_arb_lost_cap_reg_t arb_lost_cap; + volatile twai_err_code_cap_reg_t err_code_cap; + volatile twai_err_warning_limit_reg_t err_warning_limit; + volatile twai_rx_err_cnt_reg_t rx_err_cnt; + volatile twai_tx_err_cnt_reg_t tx_err_cnt; + volatile twai_tx_rx_buffer_reg_t tx_rx_buffer[13]; + volatile twai_rx_message_counter_reg_t rx_message_counter; + uint32_t reserved_078; + volatile twai_clock_divider_reg_t clock_divider; + volatile twai_sw_standby_cfg_reg_t sw_standby_cfg; + volatile twai_hw_cfg_reg_t hw_cfg; + volatile twai_hw_standby_cnt_reg_t hw_standby_cnt; + volatile twai_idle_intr_cnt_reg_t idle_intr_cnt; + volatile twai_eco_cfg_reg_t eco_cfg; +} twai_dev_t; + +extern twai_dev_t TWAI0; +extern twai_dev_t TWAI1; + +#ifndef __cplusplus +_Static_assert(sizeof(twai_dev_t) == 0x94, "Invalid size of twai_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/uart_channel.h b/components/soc/esp32c6/include/soc/uart_channel.h new file mode 100644 index 0000000000..b81bfc432d --- /dev/null +++ b/components/soc/esp32c6/include/soc/uart_channel.h @@ -0,0 +1,21 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C3. + +#ifndef _SOC_UART_CHANNEL_H +#define _SOC_UART_CHANNEL_H + +//UART channels +#define UART_GPIO21_DIRECT_CHANNEL UART_NUM_0 +#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 21 +#define UART_GPIO20_DIRECT_CHANNEL UART_NUM_0 +#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 20 + +#define UART_TXD_GPIO21_DIRECT_CHANNEL UART_GPIO21_DIRECT_CHANNEL +#define UART_RXD_GPIO20_DIRECT_CHANNEL UART_GPIO20_DIRECT_CHANNEL + +#endif diff --git a/components/soc/esp32c6/include/soc/uart_pins.h b/components/soc/esp32c6/include/soc/uart_pins.h new file mode 100644 index 0000000000..cafc2c7380 --- /dev/null +++ b/components/soc/esp32c6/include/soc/uart_pins.h @@ -0,0 +1,36 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc/io_mux_reg.h" + +/* Specify the number of pins for UART */ +#define SOC_UART_PINS_COUNT (4) + +/* Specify the GPIO pin number for each UART signal in the IOMUX */ +#define U0RXD_GPIO_NUM 17 +#define U0TXD_GPIO_NUM 16 +#define U0RTS_GPIO_NUM (-1) +#define U0CTS_GPIO_NUM (-1) + +#define U1RXD_GPIO_NUM (-1) +#define U1TXD_GPIO_NUM (-1) +#define U1RTS_GPIO_NUM (-1) +#define U1CTS_GPIO_NUM (-1) + +/* The following defines are necessary for reconfiguring the UART + * to use IOMUX, at runtime. */ +#define U0TXD_MUX_FUNC (FUNC_U0TXD_U0TXD) +#define U0RXD_MUX_FUNC (FUNC_U0RXD_U0RXD) +/* No func for the following pins, they shall not be used */ +#define U0RTS_MUX_FUNC (-1) +#define U0CTS_MUX_FUNC (-1) +/* Same goes for UART1 */ +#define U1TXD_MUX_FUNC (-1) +#define U1RXD_MUX_FUNC (-1) +#define U1RTS_MUX_FUNC (-1) +#define U1CTS_MUX_FUNC (-1) diff --git a/components/soc/esp32c6/include/soc/uart_reg.h b/components/soc/esp32c6/include/soc/uart_reg.h new file mode 100644 index 0000000000..958b2e51df --- /dev/null +++ b/components/soc/esp32c6/include/soc/uart_reg.h @@ -0,0 +1,1621 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** UART_FIFO_REG register + * FIFO data register + */ +#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) +/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; + * UART $n accesses FIFO via this register. + */ +#define UART_RXFIFO_RD_BYTE 0x000000FFU +#define UART_RXFIFO_RD_BYTE_M (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S) +#define UART_RXFIFO_RD_BYTE_V 0x000000FFU +#define UART_RXFIFO_RD_BYTE_S 0 + +/** UART_INT_RAW_REG register + * Raw interrupt status + */ +#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) +/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * what rxfifo_full_thrhd specifies. + */ +#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_M (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S) +#define UART_RXFIFO_FULL_INT_RAW_V 0x00000001U +#define UART_RXFIFO_FULL_INT_RAW_S 0 +/** UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1; + * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is + * less than what txfifo_empty_thrhd specifies . + */ +#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_M (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S) +#define UART_TXFIFO_EMPTY_INT_RAW_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_RAW_S 1 +/** UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error in + * the data. + */ +#define UART_PARITY_ERR_INT_RAW (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_M (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S) +#define UART_PARITY_ERR_INT_RAW_V 0x00000001U +#define UART_PARITY_ERR_INT_RAW_S 2 +/** UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * . + */ +#define UART_FRM_ERR_INT_RAW (BIT(3)) +#define UART_FRM_ERR_INT_RAW_M (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S) +#define UART_FRM_ERR_INT_RAW_V 0x00000001U +#define UART_FRM_ERR_INT_RAW_S 3 +/** UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * the FIFO can store. + */ +#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_M (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S) +#define UART_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define UART_RXFIFO_OVF_INT_RAW_S 4 +/** UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * DSRn signal. + */ +#define UART_DSR_CHG_INT_RAW (BIT(5)) +#define UART_DSR_CHG_INT_RAW_M (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S) +#define UART_DSR_CHG_INT_RAW_V 0x00000001U +#define UART_DSR_CHG_INT_RAW_S 5 +/** UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * CTSn signal. + */ +#define UART_CTS_CHG_INT_RAW (BIT(6)) +#define UART_CTS_CHG_INT_RAW_M (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S) +#define UART_CTS_CHG_INT_RAW_V 0x00000001U +#define UART_CTS_CHG_INT_RAW_S 6 +/** UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 after the stop + * bit. + */ +#define UART_BRK_DET_INT_RAW (BIT(7)) +#define UART_BRK_DET_INT_RAW_M (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S) +#define UART_BRK_DET_INT_RAW_V 0x00000001U +#define UART_BRK_DET_INT_RAW_S 7 +/** UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more time than + * rx_tout_thrhd to receive a byte. + */ +#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_M (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S) +#define UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_RAW_S 8 +/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver recevies Xon char when + * uart_sw_flow_con_en is set to 1. + */ +#define UART_SW_XON_INT_RAW (BIT(9)) +#define UART_SW_XON_INT_RAW_M (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S) +#define UART_SW_XON_INT_RAW_V 0x00000001U +#define UART_SW_XON_INT_RAW_S 9 +/** UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xoff char when + * uart_sw_flow_con_en is set to 1. + */ +#define UART_SW_XOFF_INT_RAW (BIT(10)) +#define UART_SW_XOFF_INT_RAW_M (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S) +#define UART_SW_XOFF_INT_RAW_V 0x00000001U +#define UART_SW_XOFF_INT_RAW_S 10 +/** UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a glitch in the + * middle of a start bit. + */ +#define UART_GLITCH_DET_INT_RAW (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_M (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S) +#define UART_GLITCH_DET_INT_RAW_V 0x00000001U +#define UART_GLITCH_DET_INT_RAW_S 11 +/** UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes sending + * NULL characters after all data in Tx-FIFO are sent. + */ +#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_M (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S) +#define UART_TX_BRK_DONE_INT_RAW_V 0x00000001U +#define UART_TX_BRK_DONE_INT_RAW_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept the shortest + * duration after sending the last data. + */ +#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 +/** UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has send out all data + * in FIFO. + */ +#define UART_TX_DONE_INT_RAW (BIT(14)) +#define UART_TX_DONE_INT_RAW_M (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S) +#define UART_TX_DONE_INT_RAW_V 0x00000001U +#define UART_TX_DONE_INT_RAW_S 14 +/** UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error + * from the echo of transmitter in rs485 mode. + */ +#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_M (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S) +#define UART_RS485_PARITY_ERR_INT_RAW_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_RAW_S 15 +/** UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * from the echo of transmitter in rs485 mode. + */ +#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_M (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S) +#define UART_RS485_FRM_ERR_INT_RAW_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_RAW_S 16 +/** UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * This interrupt raw bit turns to high level when detects a clash between transmitter + * and receiver in rs485 mode. + */ +#define UART_RS485_CLASH_INT_RAW (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_M (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S) +#define UART_RS485_CLASH_INT_RAW_V 0x00000001U +#define UART_RS485_CLASH_INT_RAW_S 17 +/** UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the configured + * at_cmd char. + */ +#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_M (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S) +#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 +/** UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes more times + * than what reg_active_threshold specifies in light sleeping mode. + */ +#define UART_WAKEUP_INT_RAW (BIT(19)) +#define UART_WAKEUP_INT_RAW_M (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S) +#define UART_WAKEUP_INT_RAW_V 0x00000001U +#define UART_WAKEUP_INT_RAW_S 19 + +/** UART_INT_ST_REG register + * Masked interrupt status + */ +#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) +/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0; + * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + */ +#define UART_RXFIFO_FULL_INT_ST (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_M (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S) +#define UART_RXFIFO_FULL_INT_ST_V 0x00000001U +#define UART_RXFIFO_FULL_INT_ST_S 0 +/** UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0; + * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set + * to 1. + */ +#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_M (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S) +#define UART_TXFIFO_EMPTY_INT_ST_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_ST_S 1 +/** UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0; + * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + */ +#define UART_PARITY_ERR_INT_ST (BIT(2)) +#define UART_PARITY_ERR_INT_ST_M (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S) +#define UART_PARITY_ERR_INT_ST_V 0x00000001U +#define UART_PARITY_ERR_INT_ST_S 2 +/** UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0; + * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + */ +#define UART_FRM_ERR_INT_ST (BIT(3)) +#define UART_FRM_ERR_INT_ST_M (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S) +#define UART_FRM_ERR_INT_ST_V 0x00000001U +#define UART_FRM_ERR_INT_ST_S 3 +/** UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0; + * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + */ +#define UART_RXFIFO_OVF_INT_ST (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_M (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S) +#define UART_RXFIFO_OVF_INT_ST_V 0x00000001U +#define UART_RXFIFO_OVF_INT_ST_S 4 +/** UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0; + * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + */ +#define UART_DSR_CHG_INT_ST (BIT(5)) +#define UART_DSR_CHG_INT_ST_M (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S) +#define UART_DSR_CHG_INT_ST_V 0x00000001U +#define UART_DSR_CHG_INT_ST_S 5 +/** UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0; + * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + */ +#define UART_CTS_CHG_INT_ST (BIT(6)) +#define UART_CTS_CHG_INT_ST_M (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S) +#define UART_CTS_CHG_INT_ST_V 0x00000001U +#define UART_CTS_CHG_INT_ST_S 6 +/** UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0; + * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + */ +#define UART_BRK_DET_INT_ST (BIT(7)) +#define UART_BRK_DET_INT_ST_M (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S) +#define UART_BRK_DET_INT_ST_V 0x00000001U +#define UART_BRK_DET_INT_ST_S 7 +/** UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0; + * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + */ +#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_M (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S) +#define UART_RXFIFO_TOUT_INT_ST_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_ST_S 8 +/** UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0; + * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + */ +#define UART_SW_XON_INT_ST (BIT(9)) +#define UART_SW_XON_INT_ST_M (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S) +#define UART_SW_XON_INT_ST_V 0x00000001U +#define UART_SW_XON_INT_ST_S 9 +/** UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0; + * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + */ +#define UART_SW_XOFF_INT_ST (BIT(10)) +#define UART_SW_XOFF_INT_ST_M (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S) +#define UART_SW_XOFF_INT_ST_V 0x00000001U +#define UART_SW_XOFF_INT_ST_S 10 +/** UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0; + * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + */ +#define UART_GLITCH_DET_INT_ST (BIT(11)) +#define UART_GLITCH_DET_INT_ST_M (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S) +#define UART_GLITCH_DET_INT_ST_V 0x00000001U +#define UART_GLITCH_DET_INT_ST_S 11 +/** UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0; + * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + */ +#define UART_TX_BRK_DONE_INT_ST (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_M (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S) +#define UART_TX_BRK_DONE_INT_ST_V 0x00000001U +#define UART_TX_BRK_DONE_INT_ST_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; + * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * is set to 1. + */ +#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_M (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S) +#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 +/** UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + */ +#define UART_TX_DONE_INT_ST (BIT(14)) +#define UART_TX_DONE_INT_ST_M (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S) +#define UART_TX_DONE_INT_ST_V 0x00000001U +#define UART_TX_DONE_INT_ST_S 14 +/** UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0; + * This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is + * set to 1. + */ +#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_M (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S) +#define UART_RS485_PARITY_ERR_INT_ST_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_ST_S 15 +/** UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0; + * This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set + * to 1. + */ +#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_M (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S) +#define UART_RS485_FRM_ERR_INT_ST_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_ST_S 16 +/** UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0; + * This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + */ +#define UART_RS485_CLASH_INT_ST (BIT(17)) +#define UART_RS485_CLASH_INT_ST_M (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S) +#define UART_RS485_CLASH_INT_ST_V 0x00000001U +#define UART_RS485_CLASH_INT_ST_S 17 +/** UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0; + * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set + * to 1. + */ +#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_M (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S) +#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 +/** UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0; + * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + */ +#define UART_WAKEUP_INT_ST (BIT(19)) +#define UART_WAKEUP_INT_ST_M (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S) +#define UART_WAKEUP_INT_ST_V 0x00000001U +#define UART_WAKEUP_INT_ST_S 19 + +/** UART_INT_ENA_REG register + * Interrupt enable bits + */ +#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc) +/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0; + * This is the enable bit for rxfifo_full_int_st register. + */ +#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_M (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S) +#define UART_RXFIFO_FULL_INT_ENA_V 0x00000001U +#define UART_RXFIFO_FULL_INT_ENA_S 0 +/** UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0; + * This is the enable bit for txfifo_empty_int_st register. + */ +#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_M (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S) +#define UART_TXFIFO_EMPTY_INT_ENA_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_ENA_S 1 +/** UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0; + * This is the enable bit for parity_err_int_st register. + */ +#define UART_PARITY_ERR_INT_ENA (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_M (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S) +#define UART_PARITY_ERR_INT_ENA_V 0x00000001U +#define UART_PARITY_ERR_INT_ENA_S 2 +/** UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0; + * This is the enable bit for frm_err_int_st register. + */ +#define UART_FRM_ERR_INT_ENA (BIT(3)) +#define UART_FRM_ERR_INT_ENA_M (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S) +#define UART_FRM_ERR_INT_ENA_V 0x00000001U +#define UART_FRM_ERR_INT_ENA_S 3 +/** UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; + * This is the enable bit for rxfifo_ovf_int_st register. + */ +#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_M (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S) +#define UART_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define UART_RXFIFO_OVF_INT_ENA_S 4 +/** UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0; + * This is the enable bit for dsr_chg_int_st register. + */ +#define UART_DSR_CHG_INT_ENA (BIT(5)) +#define UART_DSR_CHG_INT_ENA_M (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S) +#define UART_DSR_CHG_INT_ENA_V 0x00000001U +#define UART_DSR_CHG_INT_ENA_S 5 +/** UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0; + * This is the enable bit for cts_chg_int_st register. + */ +#define UART_CTS_CHG_INT_ENA (BIT(6)) +#define UART_CTS_CHG_INT_ENA_M (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S) +#define UART_CTS_CHG_INT_ENA_V 0x00000001U +#define UART_CTS_CHG_INT_ENA_S 6 +/** UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0; + * This is the enable bit for brk_det_int_st register. + */ +#define UART_BRK_DET_INT_ENA (BIT(7)) +#define UART_BRK_DET_INT_ENA_M (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S) +#define UART_BRK_DET_INT_ENA_V 0x00000001U +#define UART_BRK_DET_INT_ENA_S 7 +/** UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * This is the enable bit for rxfifo_tout_int_st register. + */ +#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_M (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S) +#define UART_RXFIFO_TOUT_INT_ENA_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_ENA_S 8 +/** UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0; + * This is the enable bit for sw_xon_int_st register. + */ +#define UART_SW_XON_INT_ENA (BIT(9)) +#define UART_SW_XON_INT_ENA_M (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S) +#define UART_SW_XON_INT_ENA_V 0x00000001U +#define UART_SW_XON_INT_ENA_S 9 +/** UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0; + * This is the enable bit for sw_xoff_int_st register. + */ +#define UART_SW_XOFF_INT_ENA (BIT(10)) +#define UART_SW_XOFF_INT_ENA_M (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S) +#define UART_SW_XOFF_INT_ENA_V 0x00000001U +#define UART_SW_XOFF_INT_ENA_S 10 +/** UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0; + * This is the enable bit for glitch_det_int_st register. + */ +#define UART_GLITCH_DET_INT_ENA (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_M (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S) +#define UART_GLITCH_DET_INT_ENA_V 0x00000001U +#define UART_GLITCH_DET_INT_ENA_S 11 +/** UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; + * This is the enable bit for tx_brk_done_int_st register. + */ +#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_M (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S) +#define UART_TX_BRK_DONE_INT_ENA_V 0x00000001U +#define UART_TX_BRK_DONE_INT_ENA_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; + * This is the enable bit for tx_brk_idle_done_int_st register. + */ +#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 +/** UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * This is the enable bit for tx_done_int_st register. + */ +#define UART_TX_DONE_INT_ENA (BIT(14)) +#define UART_TX_DONE_INT_ENA_M (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S) +#define UART_TX_DONE_INT_ENA_V 0x00000001U +#define UART_TX_DONE_INT_ENA_S 14 +/** UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ +#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_M (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S) +#define UART_RS485_PARITY_ERR_INT_ENA_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_ENA_S 15 +/** UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ +#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_M (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S) +#define UART_RS485_FRM_ERR_INT_ENA_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_ENA_S 16 +/** UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0; + * This is the enable bit for rs485_clash_int_st register. + */ +#define UART_RS485_CLASH_INT_ENA (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_M (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S) +#define UART_RS485_CLASH_INT_ENA_V 0x00000001U +#define UART_RS485_CLASH_INT_ENA_S 17 +/** UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0; + * This is the enable bit for at_cmd_char_det_int_st register. + */ +#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_M (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S) +#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 +/** UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0; + * This is the enable bit for uart_wakeup_int_st register. + */ +#define UART_WAKEUP_INT_ENA (BIT(19)) +#define UART_WAKEUP_INT_ENA_M (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S) +#define UART_WAKEUP_INT_ENA_V 0x00000001U +#define UART_WAKEUP_INT_ENA_S 19 + +/** UART_INT_CLR_REG register + * Interrupt clear bits + */ +#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) +/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the rxfifo_full_int_raw interrupt. + */ +#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_M (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S) +#define UART_RXFIFO_FULL_INT_CLR_V 0x00000001U +#define UART_RXFIFO_FULL_INT_CLR_S 0 +/** UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear txfifo_empty_int_raw interrupt. + */ +#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_M (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S) +#define UART_TXFIFO_EMPTY_INT_CLR_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_CLR_S 1 +/** UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear parity_err_int_raw interrupt. + */ +#define UART_PARITY_ERR_INT_CLR (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_M (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S) +#define UART_PARITY_ERR_INT_CLR_V 0x00000001U +#define UART_PARITY_ERR_INT_CLR_S 2 +/** UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear frm_err_int_raw interrupt. + */ +#define UART_FRM_ERR_INT_CLR (BIT(3)) +#define UART_FRM_ERR_INT_CLR_M (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S) +#define UART_FRM_ERR_INT_CLR_V 0x00000001U +#define UART_FRM_ERR_INT_CLR_S 3 +/** UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear rxfifo_ovf_int_raw interrupt. + */ +#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_M (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S) +#define UART_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define UART_RXFIFO_OVF_INT_CLR_S 4 +/** UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the dsr_chg_int_raw interrupt. + */ +#define UART_DSR_CHG_INT_CLR (BIT(5)) +#define UART_DSR_CHG_INT_CLR_M (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S) +#define UART_DSR_CHG_INT_CLR_V 0x00000001U +#define UART_DSR_CHG_INT_CLR_S 5 +/** UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the cts_chg_int_raw interrupt. + */ +#define UART_CTS_CHG_INT_CLR (BIT(6)) +#define UART_CTS_CHG_INT_CLR_M (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S) +#define UART_CTS_CHG_INT_CLR_V 0x00000001U +#define UART_CTS_CHG_INT_CLR_S 6 +/** UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the brk_det_int_raw interrupt. + */ +#define UART_BRK_DET_INT_CLR (BIT(7)) +#define UART_BRK_DET_INT_CLR_M (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S) +#define UART_BRK_DET_INT_CLR_V 0x00000001U +#define UART_BRK_DET_INT_CLR_S 7 +/** UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the rxfifo_tout_int_raw interrupt. + */ +#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_M (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S) +#define UART_RXFIFO_TOUT_INT_CLR_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_CLR_S 8 +/** UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the sw_xon_int_raw interrupt. + */ +#define UART_SW_XON_INT_CLR (BIT(9)) +#define UART_SW_XON_INT_CLR_M (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S) +#define UART_SW_XON_INT_CLR_V 0x00000001U +#define UART_SW_XON_INT_CLR_S 9 +/** UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the sw_xoff_int_raw interrupt. + */ +#define UART_SW_XOFF_INT_CLR (BIT(10)) +#define UART_SW_XOFF_INT_CLR_M (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S) +#define UART_SW_XOFF_INT_CLR_V 0x00000001U +#define UART_SW_XOFF_INT_CLR_S 10 +/** UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the glitch_det_int_raw interrupt. + */ +#define UART_GLITCH_DET_INT_CLR (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_M (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S) +#define UART_GLITCH_DET_INT_CLR_V 0x00000001U +#define UART_GLITCH_DET_INT_CLR_S 11 +/** UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the tx_brk_done_int_raw interrupt.. + */ +#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_M (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S) +#define UART_TX_BRK_DONE_INT_CLR_V 0x00000001U +#define UART_TX_BRK_DONE_INT_CLR_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + */ +#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 +/** UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the tx_done_int_raw interrupt. + */ +#define UART_TX_DONE_INT_CLR (BIT(14)) +#define UART_TX_DONE_INT_CLR_M (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S) +#define UART_TX_DONE_INT_CLR_V 0x00000001U +#define UART_TX_DONE_INT_CLR_S 14 +/** UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear the rs485_parity_err_int_raw interrupt. + */ +#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_M (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S) +#define UART_RS485_PARITY_ERR_INT_CLR_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_CLR_S 15 +/** UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear the rs485_frm_err_int_raw interrupt. + */ +#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_M (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S) +#define UART_RS485_FRM_ERR_INT_CLR_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_CLR_S 16 +/** UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear the rs485_clash_int_raw interrupt. + */ +#define UART_RS485_CLASH_INT_CLR (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_M (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S) +#define UART_RS485_CLASH_INT_CLR_V 0x00000001U +#define UART_RS485_CLASH_INT_CLR_S 17 +/** UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear the at_cmd_char_det_int_raw interrupt. + */ +#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_M (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S) +#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 +/** UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear the uart_wakeup_int_raw interrupt. + */ +#define UART_WAKEUP_INT_CLR (BIT(19)) +#define UART_WAKEUP_INT_CLR_M (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S) +#define UART_WAKEUP_INT_CLR_V 0x00000001U +#define UART_WAKEUP_INT_CLR_S 19 + +/** UART_CLKDIV_SYNC_REG register + * Clock divider configuration + */ +#define UART_CLKDIV_SYNC_REG(i) (REG_UART_BASE(i) + 0x14) +/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694; + * The integral part of the frequency divider factor. + */ +#define UART_CLKDIV 0x00000FFFU +#define UART_CLKDIV_M (UART_CLKDIV_V << UART_CLKDIV_S) +#define UART_CLKDIV_V 0x00000FFFU +#define UART_CLKDIV_S 0 +/** UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0; + * The decimal part of the frequency divider factor. + */ +#define UART_CLKDIV_FRAG 0x0000000FU +#define UART_CLKDIV_FRAG_M (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S) +#define UART_CLKDIV_FRAG_V 0x0000000FU +#define UART_CLKDIV_FRAG_S 20 + +/** UART_RX_FILT_REG register + * Rx Filter configuration + */ +#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18) +/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8; + * when input pulse width is lower than this value the pulse is ignored. + */ +#define UART_GLITCH_FILT 0x000000FFU +#define UART_GLITCH_FILT_M (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S) +#define UART_GLITCH_FILT_V 0x000000FFU +#define UART_GLITCH_FILT_S 0 +/** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0; + * Set this bit to enable Rx signal filter. + */ +#define UART_GLITCH_FILT_EN (BIT(8)) +#define UART_GLITCH_FILT_EN_M (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S) +#define UART_GLITCH_FILT_EN_V 0x00000001U +#define UART_GLITCH_FILT_EN_S 8 + +/** UART_STATUS_REG register + * UART status register + */ +#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c) +/** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0; + * Stores the byte number of valid data in Rx-FIFO. + */ +#define UART_RXFIFO_CNT 0x000000FFU +#define UART_RXFIFO_CNT_M (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S) +#define UART_RXFIFO_CNT_V 0x000000FFU +#define UART_RXFIFO_CNT_S 0 +/** UART_DSRN : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal uart dsr signal. + */ +#define UART_DSRN (BIT(13)) +#define UART_DSRN_M (UART_DSRN_V << UART_DSRN_S) +#define UART_DSRN_V 0x00000001U +#define UART_DSRN_S 13 +/** UART_CTSN : RO; bitpos: [14]; default: 1; + * This register represent the level value of the internal uart cts signal. + */ +#define UART_CTSN (BIT(14)) +#define UART_CTSN_M (UART_CTSN_V << UART_CTSN_S) +#define UART_CTSN_V 0x00000001U +#define UART_CTSN_S 14 +/** UART_RXD : RO; bitpos: [15]; default: 1; + * This register represent the level value of the internal uart rxd signal. + */ +#define UART_RXD (BIT(15)) +#define UART_RXD_M (UART_RXD_V << UART_RXD_S) +#define UART_RXD_V 0x00000001U +#define UART_RXD_S 15 +/** UART_TXFIFO_CNT : RO; bitpos: [23:16]; default: 0; + * Stores the byte number of data in Tx-FIFO. + */ +#define UART_TXFIFO_CNT 0x000000FFU +#define UART_TXFIFO_CNT_M (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S) +#define UART_TXFIFO_CNT_V 0x000000FFU +#define UART_TXFIFO_CNT_S 16 +/** UART_DTRN : RO; bitpos: [29]; default: 1; + * This bit represents the level of the internal uart dtr signal. + */ +#define UART_DTRN (BIT(29)) +#define UART_DTRN_M (UART_DTRN_V << UART_DTRN_S) +#define UART_DTRN_V 0x00000001U +#define UART_DTRN_S 29 +/** UART_RTSN : RO; bitpos: [30]; default: 1; + * This bit represents the level of the internal uart rts signal. + */ +#define UART_RTSN (BIT(30)) +#define UART_RTSN_M (UART_RTSN_V << UART_RTSN_S) +#define UART_RTSN_V 0x00000001U +#define UART_RTSN_S 30 +/** UART_TXD : RO; bitpos: [31]; default: 1; + * This bit represents the level of the internal uart txd signal. + */ +#define UART_TXD (BIT(31)) +#define UART_TXD_M (UART_TXD_V << UART_TXD_S) +#define UART_TXD_V 0x00000001U +#define UART_TXD_S 31 + +/** UART_CONF0_SYNC_REG register + * a + */ +#define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20) +/** UART_PARITY : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check mode. + */ +#define UART_PARITY (BIT(0)) +#define UART_PARITY_M (UART_PARITY_V << UART_PARITY_S) +#define UART_PARITY_V 0x00000001U +#define UART_PARITY_S 0 +/** UART_PARITY_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to enable uart parity check. + */ +#define UART_PARITY_EN (BIT(1)) +#define UART_PARITY_EN_M (UART_PARITY_EN_V << UART_PARITY_EN_S) +#define UART_PARITY_EN_V 0x00000001U +#define UART_PARITY_EN_S 1 +/** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3; + * This register is used to set the length of data. + */ +#define UART_BIT_NUM 0x00000003U +#define UART_BIT_NUM_M (UART_BIT_NUM_V << UART_BIT_NUM_S) +#define UART_BIT_NUM_V 0x00000003U +#define UART_BIT_NUM_S 2 +/** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1; + * This register is used to set the length of stop bit. + */ +#define UART_STOP_BIT_NUM 0x00000003U +#define UART_STOP_BIT_NUM_M (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S) +#define UART_STOP_BIT_NUM_V 0x00000003U +#define UART_STOP_BIT_NUM_S 4 +/** UART_TXD_BRK : R/W; bitpos: [6]; default: 0; + * Set this bit to enbale transmitter to send NULL when the process of sending data + * is done. + */ +#define UART_TXD_BRK (BIT(6)) +#define UART_TXD_BRK_M (UART_TXD_BRK_V << UART_TXD_BRK_S) +#define UART_TXD_BRK_V 0x00000001U +#define UART_TXD_BRK_S 6 +/** UART_IRDA_DPLX : R/W; bitpos: [7]; default: 0; + * Set this bit to enable IrDA loopback mode. + */ +#define UART_IRDA_DPLX (BIT(7)) +#define UART_IRDA_DPLX_M (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S) +#define UART_IRDA_DPLX_V 0x00000001U +#define UART_IRDA_DPLX_S 7 +/** UART_IRDA_TX_EN : R/W; bitpos: [8]; default: 0; + * This is the start enable bit for IrDA transmitter. + */ +#define UART_IRDA_TX_EN (BIT(8)) +#define UART_IRDA_TX_EN_M (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S) +#define UART_IRDA_TX_EN_V 0x00000001U +#define UART_IRDA_TX_EN_S 8 +/** UART_IRDA_WCTL : R/W; bitpos: [9]; default: 0; + * 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA + * transmitter's 11th bit to 0. + */ +#define UART_IRDA_WCTL (BIT(9)) +#define UART_IRDA_WCTL_M (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S) +#define UART_IRDA_WCTL_V 0x00000001U +#define UART_IRDA_WCTL_S 9 +/** UART_IRDA_TX_INV : R/W; bitpos: [10]; default: 0; + * Set this bit to invert the level of IrDA transmitter. + */ +#define UART_IRDA_TX_INV (BIT(10)) +#define UART_IRDA_TX_INV_M (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S) +#define UART_IRDA_TX_INV_V 0x00000001U +#define UART_IRDA_TX_INV_S 10 +/** UART_IRDA_RX_INV : R/W; bitpos: [11]; default: 0; + * Set this bit to invert the level of IrDA receiver. + */ +#define UART_IRDA_RX_INV (BIT(11)) +#define UART_IRDA_RX_INV_M (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S) +#define UART_IRDA_RX_INV_V 0x00000001U +#define UART_IRDA_RX_INV_S 11 +/** UART_LOOPBACK : R/W; bitpos: [12]; default: 0; + * Set this bit to enable uart loopback test mode. + */ +#define UART_LOOPBACK (BIT(12)) +#define UART_LOOPBACK_M (UART_LOOPBACK_V << UART_LOOPBACK_S) +#define UART_LOOPBACK_V 0x00000001U +#define UART_LOOPBACK_S 12 +/** UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0; + * Set this bit to enable flow control function for transmitter. + */ +#define UART_TX_FLOW_EN (BIT(13)) +#define UART_TX_FLOW_EN_M (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S) +#define UART_TX_FLOW_EN_V 0x00000001U +#define UART_TX_FLOW_EN_S 13 +/** UART_IRDA_EN : R/W; bitpos: [14]; default: 0; + * Set this bit to enable IrDA protocol. + */ +#define UART_IRDA_EN (BIT(14)) +#define UART_IRDA_EN_M (UART_IRDA_EN_V << UART_IRDA_EN_S) +#define UART_IRDA_EN_V 0x00000001U +#define UART_IRDA_EN_S 14 +/** UART_RXD_INV : R/W; bitpos: [15]; default: 0; + * Set this bit to inverse the level value of uart rxd signal. + */ +#define UART_RXD_INV (BIT(15)) +#define UART_RXD_INV_M (UART_RXD_INV_V << UART_RXD_INV_S) +#define UART_RXD_INV_V 0x00000001U +#define UART_RXD_INV_S 15 +/** UART_TXD_INV : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart txd signal. + */ +#define UART_TXD_INV (BIT(16)) +#define UART_TXD_INV_M (UART_TXD_INV_V << UART_TXD_INV_S) +#define UART_TXD_INV_V 0x00000001U +#define UART_TXD_INV_S 16 +/** UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0; + * Disable UART Rx data overflow detect. + */ +#define UART_DIS_RX_DAT_OVF (BIT(17)) +#define UART_DIS_RX_DAT_OVF_M (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S) +#define UART_DIS_RX_DAT_OVF_V 0x00000001U +#define UART_DIS_RX_DAT_OVF_S 17 +/** UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver + * stores the data even if the received data is wrong. + */ +#define UART_ERR_WR_MASK (BIT(18)) +#define UART_ERR_WR_MASK_M (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S) +#define UART_ERR_WR_MASK_V 0x00000001U +#define UART_ERR_WR_MASK_S 18 +/** UART_AUTOBAUD_EN : R/W; bitpos: [19]; default: 0; + * This is the enable bit for detecting baudrate. + */ +#define UART_AUTOBAUD_EN (BIT(19)) +#define UART_AUTOBAUD_EN_M (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S) +#define UART_AUTOBAUD_EN_V 0x00000001U +#define UART_AUTOBAUD_EN_S 19 +/** UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 1; + * UART memory clock gate enable signal. + */ +#define UART_MEM_CLK_EN (BIT(20)) +#define UART_MEM_CLK_EN_M (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S) +#define UART_MEM_CLK_EN_V 0x00000001U +#define UART_MEM_CLK_EN_S 20 +/** UART_SW_RTS : R/W; bitpos: [21]; default: 0; + * This register is used to configure the software rts signal which is used in + * software flow control. + */ +#define UART_SW_RTS (BIT(21)) +#define UART_SW_RTS_M (UART_SW_RTS_V << UART_SW_RTS_S) +#define UART_SW_RTS_V 0x00000001U +#define UART_SW_RTS_S 21 +/** UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0; + * Set this bit to reset the uart receive-FIFO. + */ +#define UART_RXFIFO_RST (BIT(22)) +#define UART_RXFIFO_RST_M (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S) +#define UART_RXFIFO_RST_V 0x00000001U +#define UART_RXFIFO_RST_S 22 +/** UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0; + * Set this bit to reset the uart transmit-FIFO. + */ +#define UART_TXFIFO_RST (BIT(23)) +#define UART_TXFIFO_RST_M (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S) +#define UART_TXFIFO_RST_V 0x00000001U +#define UART_TXFIFO_RST_S 23 + +/** UART_CONF1_REG register + * Configuration register 1 + */ +#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) +/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96; + * It will produce rxfifo_full_int interrupt when receiver receives more data than + * this register value. + */ +#define UART_RXFIFO_FULL_THRHD 0x000000FFU +#define UART_RXFIFO_FULL_THRHD_M (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S) +#define UART_RXFIFO_FULL_THRHD_V 0x000000FFU +#define UART_RXFIFO_FULL_THRHD_S 0 +/** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:8]; default: 96; + * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less + * than this register value. + */ +#define UART_TXFIFO_EMPTY_THRHD 0x000000FFU +#define UART_TXFIFO_EMPTY_THRHD_M (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S) +#define UART_TXFIFO_EMPTY_THRHD_V 0x000000FFU +#define UART_TXFIFO_EMPTY_THRHD_S 8 +/** UART_CTS_INV : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart cts signal. + */ +#define UART_CTS_INV (BIT(16)) +#define UART_CTS_INV_M (UART_CTS_INV_V << UART_CTS_INV_S) +#define UART_CTS_INV_V 0x00000001U +#define UART_CTS_INV_S 16 +/** UART_DSR_INV : R/W; bitpos: [17]; default: 0; + * Set this bit to inverse the level value of uart dsr signal. + */ +#define UART_DSR_INV (BIT(17)) +#define UART_DSR_INV_M (UART_DSR_INV_V << UART_DSR_INV_S) +#define UART_DSR_INV_V 0x00000001U +#define UART_DSR_INV_S 17 +/** UART_RTS_INV : R/W; bitpos: [18]; default: 0; + * Set this bit to inverse the level value of uart rts signal. + */ +#define UART_RTS_INV (BIT(18)) +#define UART_RTS_INV_M (UART_RTS_INV_V << UART_RTS_INV_S) +#define UART_RTS_INV_V 0x00000001U +#define UART_RTS_INV_S 18 +/** UART_DTR_INV : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of uart dtr signal. + */ +#define UART_DTR_INV (BIT(19)) +#define UART_DTR_INV_M (UART_DTR_INV_V << UART_DTR_INV_S) +#define UART_DTR_INV_V 0x00000001U +#define UART_DTR_INV_S 19 +/** UART_SW_DTR : R/W; bitpos: [20]; default: 0; + * This register is used to configure the software dtr signal which is used in + * software flow control. + */ +#define UART_SW_DTR (BIT(20)) +#define UART_SW_DTR_M (UART_SW_DTR_V << UART_SW_DTR_S) +#define UART_SW_DTR_V 0x00000001U +#define UART_SW_DTR_S 20 +/** UART_CLK_EN : R/W; bitpos: [21]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define UART_CLK_EN (BIT(21)) +#define UART_CLK_EN_M (UART_CLK_EN_V << UART_CLK_EN_S) +#define UART_CLK_EN_V 0x00000001U +#define UART_CLK_EN_S 21 + +/** UART_HWFC_CONF_SYNC_REG register + * Hardware flow-control configuration + */ +#define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c) +/** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0; + * This register is used to configure the maximum amount of data that can be received + * when hardware flow control works. + */ +#define UART_RX_FLOW_THRHD 0x000000FFU +#define UART_RX_FLOW_THRHD_M (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S) +#define UART_RX_FLOW_THRHD_V 0x000000FFU +#define UART_RX_FLOW_THRHD_S 0 +/** UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0; + * This is the flow enable bit for UART receiver. + */ +#define UART_RX_FLOW_EN (BIT(8)) +#define UART_RX_FLOW_EN_M (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S) +#define UART_RX_FLOW_EN_V 0x00000001U +#define UART_RX_FLOW_EN_S 8 + +/** UART_SLEEP_CONF0_REG register + * UART sleep configure register 0 + */ +#define UART_SLEEP_CONF0_REG(i) (REG_UART_BASE(i) + 0x30) +/** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified wake up char1 to wake up + */ +#define UART_WK_CHAR1 0x000000FFU +#define UART_WK_CHAR1_M (UART_WK_CHAR1_V << UART_WK_CHAR1_S) +#define UART_WK_CHAR1_V 0x000000FFU +#define UART_WK_CHAR1_S 0 +/** UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0; + * This register restores the specified wake up char2 to wake up + */ +#define UART_WK_CHAR2 0x000000FFU +#define UART_WK_CHAR2_M (UART_WK_CHAR2_V << UART_WK_CHAR2_S) +#define UART_WK_CHAR2_V 0x000000FFU +#define UART_WK_CHAR2_S 8 +/** UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0; + * This register restores the specified wake up char3 to wake up + */ +#define UART_WK_CHAR3 0x000000FFU +#define UART_WK_CHAR3_M (UART_WK_CHAR3_V << UART_WK_CHAR3_S) +#define UART_WK_CHAR3_V 0x000000FFU +#define UART_WK_CHAR3_S 16 +/** UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0; + * This register restores the specified wake up char4 to wake up + */ +#define UART_WK_CHAR4 0x000000FFU +#define UART_WK_CHAR4_M (UART_WK_CHAR4_V << UART_WK_CHAR4_S) +#define UART_WK_CHAR4_V 0x000000FFU +#define UART_WK_CHAR4_S 24 + +/** UART_SLEEP_CONF1_REG register + * UART sleep configure register 1 + */ +#define UART_SLEEP_CONF1_REG(i) (REG_UART_BASE(i) + 0x34) +/** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified char0 to wake up + */ +#define UART_WK_CHAR0 0x000000FFU +#define UART_WK_CHAR0_M (UART_WK_CHAR0_V << UART_WK_CHAR0_S) +#define UART_WK_CHAR0_V 0x000000FFU +#define UART_WK_CHAR0_S 0 + +/** UART_SLEEP_CONF2_REG register + * UART sleep configure register 2 + */ +#define UART_SLEEP_CONF2_REG(i) (REG_UART_BASE(i) + 0x38) +/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240; + * The uart is activated from light sleeping mode when the input rxd edge changes more + * times than this register value. + */ +#define UART_ACTIVE_THRESHOLD 0x000003FFU +#define UART_ACTIVE_THRESHOLD_M (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S) +#define UART_ACTIVE_THRESHOLD_V 0x000003FFU +#define UART_ACTIVE_THRESHOLD_S 0 +/** UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:10]; default: 1; + * In wake up mode 1 this field is used to set the received data number threshold to + * wake up chip. + */ +#define UART_RX_WAKE_UP_THRHD 0x000000FFU +#define UART_RX_WAKE_UP_THRHD_M (UART_RX_WAKE_UP_THRHD_V << UART_RX_WAKE_UP_THRHD_S) +#define UART_RX_WAKE_UP_THRHD_V 0x000000FFU +#define UART_RX_WAKE_UP_THRHD_S 10 +/** UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5; + * This register is used to select number of wake up char. + */ +#define UART_WK_CHAR_NUM 0x00000007U +#define UART_WK_CHAR_NUM_M (UART_WK_CHAR_NUM_V << UART_WK_CHAR_NUM_S) +#define UART_WK_CHAR_NUM_V 0x00000007U +#define UART_WK_CHAR_NUM_S 18 +/** UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0; + * This register is used to mask wake up char. + */ +#define UART_WK_CHAR_MASK 0x0000001FU +#define UART_WK_CHAR_MASK_M (UART_WK_CHAR_MASK_V << UART_WK_CHAR_MASK_S) +#define UART_WK_CHAR_MASK_V 0x0000001FU +#define UART_WK_CHAR_MASK_S 21 +/** UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0; + * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: + * received data number larger than + */ +#define UART_WK_MODE_SEL 0x00000003U +#define UART_WK_MODE_SEL_M (UART_WK_MODE_SEL_V << UART_WK_MODE_SEL_S) +#define UART_WK_MODE_SEL_V 0x00000003U +#define UART_WK_MODE_SEL_S 26 + +/** UART_SWFC_CONF0_SYNC_REG register + * Software flow-control character configuration + */ +#define UART_SWFC_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x3c) +/** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17; + * This register stores the Xon flow control char. + */ +#define UART_XON_CHAR 0x000000FFU +#define UART_XON_CHAR_M (UART_XON_CHAR_V << UART_XON_CHAR_S) +#define UART_XON_CHAR_V 0x000000FFU +#define UART_XON_CHAR_S 0 +/** UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19; + * This register stores the Xoff flow control char. + */ +#define UART_XOFF_CHAR 0x000000FFU +#define UART_XOFF_CHAR_M (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S) +#define UART_XOFF_CHAR_V 0x000000FFU +#define UART_XOFF_CHAR_S 8 +/** UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0; + * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In + * this status, UART Tx can not transmit XOFF even the received data number is larger + * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when + * UART Tx is disabled. + */ +#define UART_XON_XOFF_STILL_SEND (BIT(16)) +#define UART_XON_XOFF_STILL_SEND_M (UART_XON_XOFF_STILL_SEND_V << UART_XON_XOFF_STILL_SEND_S) +#define UART_XON_XOFF_STILL_SEND_V 0x00000001U +#define UART_XON_XOFF_STILL_SEND_S 16 +/** UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0; + * Set this bit to enable software flow control. It is used with register sw_xon or + * sw_xoff. + */ +#define UART_SW_FLOW_CON_EN (BIT(17)) +#define UART_SW_FLOW_CON_EN_M (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S) +#define UART_SW_FLOW_CON_EN_V 0x00000001U +#define UART_SW_FLOW_CON_EN_S 17 +/** UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0; + * Set this bit to remove flow control char from the received data. + */ +#define UART_XONOFF_DEL (BIT(18)) +#define UART_XONOFF_DEL_M (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S) +#define UART_XONOFF_DEL_V 0x00000001U +#define UART_XONOFF_DEL_S 18 +/** UART_FORCE_XON : R/W; bitpos: [19]; default: 0; + * Set this bit to enable the transmitter to go on sending data. + */ +#define UART_FORCE_XON (BIT(19)) +#define UART_FORCE_XON_M (UART_FORCE_XON_V << UART_FORCE_XON_S) +#define UART_FORCE_XON_V 0x00000001U +#define UART_FORCE_XON_S 19 +/** UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0; + * Set this bit to stop the transmitter from sending data. + */ +#define UART_FORCE_XOFF (BIT(20)) +#define UART_FORCE_XOFF_M (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S) +#define UART_FORCE_XOFF_V 0x00000001U +#define UART_FORCE_XOFF_S 20 +/** UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0; + * Set this bit to send Xon char. It is cleared by hardware automatically. + */ +#define UART_SEND_XON (BIT(21)) +#define UART_SEND_XON_M (UART_SEND_XON_V << UART_SEND_XON_S) +#define UART_SEND_XON_V 0x00000001U +#define UART_SEND_XON_S 21 +/** UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0; + * Set this bit to send Xoff char. It is cleared by hardware automatically. + */ +#define UART_SEND_XOFF (BIT(22)) +#define UART_SEND_XOFF_M (UART_SEND_XOFF_V << UART_SEND_XOFF_S) +#define UART_SEND_XOFF_V 0x00000001U +#define UART_SEND_XOFF_S 22 + +/** UART_SWFC_CONF1_REG register + * Software flow-control character configuration + */ +#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40) +/** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0; + * When the data amount in Rx-FIFO is less than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xon char. + */ +#define UART_XON_THRESHOLD 0x000000FFU +#define UART_XON_THRESHOLD_M (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S) +#define UART_XON_THRESHOLD_V 0x000000FFU +#define UART_XON_THRESHOLD_S 0 +/** UART_XOFF_THRESHOLD : R/W; bitpos: [15:8]; default: 224; + * When the data amount in Rx-FIFO is more than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xoff char. + */ +#define UART_XOFF_THRESHOLD 0x000000FFU +#define UART_XOFF_THRESHOLD_M (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S) +#define UART_XOFF_THRESHOLD_V 0x000000FFU +#define UART_XOFF_THRESHOLD_S 8 + +/** UART_TXBRK_CONF_SYNC_REG register + * Tx Break character configuration + */ +#define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44) +/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10; + * This register is used to configure the number of 0 to be sent after the process of + * sending data is done. It is active when txd_brk is set to 1. + */ +#define UART_TX_BRK_NUM 0x000000FFU +#define UART_TX_BRK_NUM_M (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S) +#define UART_TX_BRK_NUM_V 0x000000FFU +#define UART_TX_BRK_NUM_S 0 + +/** UART_IDLE_CONF_SYNC_REG register + * Frame-end idle configuration + */ +#define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48) +/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256; + * It will produce frame end signal when receiver takes more time to receive one byte + * data than this register value. + */ +#define UART_RX_IDLE_THRHD 0x000003FFU +#define UART_RX_IDLE_THRHD_M (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S) +#define UART_RX_IDLE_THRHD_V 0x000003FFU +#define UART_RX_IDLE_THRHD_S 0 +/** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256; + * This register is used to configure the duration time between transfers. + */ +#define UART_TX_IDLE_NUM 0x000003FFU +#define UART_TX_IDLE_NUM_M (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S) +#define UART_TX_IDLE_NUM_V 0x000003FFU +#define UART_TX_IDLE_NUM_S 10 + +/** UART_RS485_CONF_SYNC_REG register + * RS485 mode configuration + */ +#define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c) +/** UART_RS485_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to choose the rs485 mode. + */ +#define UART_RS485_EN (BIT(0)) +#define UART_RS485_EN_M (UART_RS485_EN_V << UART_RS485_EN_S) +#define UART_RS485_EN_V 0x00000001U +#define UART_RS485_EN_S 0 +/** UART_DL0_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ +#define UART_DL0_EN (BIT(1)) +#define UART_DL0_EN_M (UART_DL0_EN_V << UART_DL0_EN_S) +#define UART_DL0_EN_V 0x00000001U +#define UART_DL0_EN_S 1 +/** UART_DL1_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ +#define UART_DL1_EN (BIT(2)) +#define UART_DL1_EN_M (UART_DL1_EN_V << UART_DL1_EN_S) +#define UART_DL1_EN_V 0x00000001U +#define UART_DL1_EN_S 2 +/** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0; + * Set this bit to enable receiver could receive data when the transmitter is + * transmitting data in rs485 mode. + */ +#define UART_RS485TX_RX_EN (BIT(3)) +#define UART_RS485TX_RX_EN_M (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S) +#define UART_RS485TX_RX_EN_V 0x00000001U +#define UART_RS485TX_RX_EN_S 3 +/** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0; + * 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + */ +#define UART_RS485RXBY_TX_EN (BIT(4)) +#define UART_RS485RXBY_TX_EN_M (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S) +#define UART_RS485RXBY_TX_EN_V 0x00000001U +#define UART_RS485RXBY_TX_EN_S 4 +/** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0; + * This register is used to delay the receiver's internal data signal. + */ +#define UART_RS485_RX_DLY_NUM (BIT(5)) +#define UART_RS485_RX_DLY_NUM_M (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S) +#define UART_RS485_RX_DLY_NUM_V 0x00000001U +#define UART_RS485_RX_DLY_NUM_S 5 +/** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0; + * This register is used to delay the transmitter's internal data signal. + */ +#define UART_RS485_TX_DLY_NUM 0x0000000FU +#define UART_RS485_TX_DLY_NUM_M (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S) +#define UART_RS485_TX_DLY_NUM_V 0x0000000FU +#define UART_RS485_TX_DLY_NUM_S 6 + +/** UART_AT_CMD_PRECNT_SYNC_REG register + * Pre-sequence timing configuration + */ +#define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50) +/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the idle duration time before the first at_cmd + * is received by receiver. + */ +#define UART_PRE_IDLE_NUM 0x0000FFFFU +#define UART_PRE_IDLE_NUM_M (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S) +#define UART_PRE_IDLE_NUM_V 0x0000FFFFU +#define UART_PRE_IDLE_NUM_S 0 + +/** UART_AT_CMD_POSTCNT_SYNC_REG register + * Post-sequence timing configuration + */ +#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54) +/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the duration time between the last at_cmd and + * the next data. + */ +#define UART_POST_IDLE_NUM 0x0000FFFFU +#define UART_POST_IDLE_NUM_M (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S) +#define UART_POST_IDLE_NUM_V 0x0000FFFFU +#define UART_POST_IDLE_NUM_S 0 + +/** UART_AT_CMD_GAPTOUT_SYNC_REG register + * Timeout configuration + */ +#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58) +/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11; + * This register is used to configure the duration time between the at_cmd chars. + */ +#define UART_RX_GAP_TOUT 0x0000FFFFU +#define UART_RX_GAP_TOUT_M (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S) +#define UART_RX_GAP_TOUT_V 0x0000FFFFU +#define UART_RX_GAP_TOUT_S 0 + +/** UART_AT_CMD_CHAR_SYNC_REG register + * AT escape sequence detection configuration + */ +#define UART_AT_CMD_CHAR_SYNC_REG(i) (REG_UART_BASE(i) + 0x5c) +/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43; + * This register is used to configure the content of at_cmd char. + */ +#define UART_AT_CMD_CHAR 0x000000FFU +#define UART_AT_CMD_CHAR_M (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S) +#define UART_AT_CMD_CHAR_V 0x000000FFU +#define UART_AT_CMD_CHAR_S 0 +/** UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3; + * This register is used to configure the num of continuous at_cmd chars received by + * receiver. + */ +#define UART_CHAR_NUM 0x000000FFU +#define UART_CHAR_NUM_M (UART_CHAR_NUM_V << UART_CHAR_NUM_S) +#define UART_CHAR_NUM_V 0x000000FFU +#define UART_CHAR_NUM_S 8 + +/** UART_MEM_CONF_REG register + * UART memory power configuration + */ +#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60) +/** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0; + * Set this bit to force power down UART memory. + */ +#define UART_MEM_FORCE_PD (BIT(25)) +#define UART_MEM_FORCE_PD_M (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S) +#define UART_MEM_FORCE_PD_V 0x00000001U +#define UART_MEM_FORCE_PD_S 25 +/** UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0; + * Set this bit to force power up UART memory. + */ +#define UART_MEM_FORCE_PU (BIT(26)) +#define UART_MEM_FORCE_PU_M (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S) +#define UART_MEM_FORCE_PU_V 0x00000001U +#define UART_MEM_FORCE_PU_S 26 + +/** UART_TOUT_CONF_SYNC_REG register + * UART threshold and allocation configuration + */ +#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64) +/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; + * This is the enble bit for uart receiver's timeout function. + */ +#define UART_RX_TOUT_EN (BIT(0)) +#define UART_RX_TOUT_EN_M (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S) +#define UART_RX_TOUT_EN_V 0x00000001U +#define UART_RX_TOUT_EN_S 0 +/** UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control works. + */ +#define UART_RX_TOUT_FLOW_DIS (BIT(1)) +#define UART_RX_TOUT_FLOW_DIS_M (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S) +#define UART_RX_TOUT_FLOW_DIS_V 0x00000001U +#define UART_RX_TOUT_FLOW_DIS_S 1 +/** UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10; + * This register is used to configure the threshold time that receiver takes to + * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver + * takes more time to receive one byte with rx_tout_en set to 1. + */ +#define UART_RX_TOUT_THRHD 0x000003FFU +#define UART_RX_TOUT_THRHD_M (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S) +#define UART_RX_TOUT_THRHD_V 0x000003FFU +#define UART_RX_TOUT_THRHD_S 2 + +/** UART_MEM_TX_STATUS_REG register + * Tx-SRAM write and read offset address. + */ +#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68) +/** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0; + * This register stores the offset write address in Tx-SRAM. + */ +#define UART_TX_SRAM_WADDR 0x000000FFU +#define UART_TX_SRAM_WADDR_M (UART_TX_SRAM_WADDR_V << UART_TX_SRAM_WADDR_S) +#define UART_TX_SRAM_WADDR_V 0x000000FFU +#define UART_TX_SRAM_WADDR_S 0 +/** UART_TX_SRAM_RADDR : RO; bitpos: [16:9]; default: 0; + * This register stores the offset read address in Tx-SRAM. + */ +#define UART_TX_SRAM_RADDR 0x000000FFU +#define UART_TX_SRAM_RADDR_M (UART_TX_SRAM_RADDR_V << UART_TX_SRAM_RADDR_S) +#define UART_TX_SRAM_RADDR_V 0x000000FFU +#define UART_TX_SRAM_RADDR_S 9 + +/** UART_MEM_RX_STATUS_REG register + * Rx-SRAM write and read offset address. + */ +#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c) +/** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128; + * This register stores the offset read address in RX-SRAM. + */ +#define UART_RX_SRAM_RADDR 0x000000FFU +#define UART_RX_SRAM_RADDR_M (UART_RX_SRAM_RADDR_V << UART_RX_SRAM_RADDR_S) +#define UART_RX_SRAM_RADDR_V 0x000000FFU +#define UART_RX_SRAM_RADDR_S 0 +/** UART_RX_SRAM_WADDR : RO; bitpos: [16:9]; default: 128; + * This register stores the offset write address in Rx-SRAM. + */ +#define UART_RX_SRAM_WADDR 0x000000FFU +#define UART_RX_SRAM_WADDR_M (UART_RX_SRAM_WADDR_V << UART_RX_SRAM_WADDR_S) +#define UART_RX_SRAM_WADDR_V 0x000000FFU +#define UART_RX_SRAM_WADDR_S 9 + +/** UART_FSM_STATUS_REG register + * UART transmit and receive status. + */ +#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x70) +/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0; + * This is the status register of receiver. + */ +#define UART_ST_URX_OUT 0x0000000FU +#define UART_ST_URX_OUT_M (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S) +#define UART_ST_URX_OUT_V 0x0000000FU +#define UART_ST_URX_OUT_S 0 +/** UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0; + * This is the status register of transmitter. + */ +#define UART_ST_UTX_OUT 0x0000000FU +#define UART_ST_UTX_OUT_M (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S) +#define UART_ST_UTX_OUT_V 0x0000000FU +#define UART_ST_UTX_OUT_S 4 + +/** UART_POSPULSE_REG register + * Autobaud high pulse register + */ +#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x74) +/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two positive edges. It + * is used in boudrate-detect process. + */ +#define UART_POSEDGE_MIN_CNT 0x00000FFFU +#define UART_POSEDGE_MIN_CNT_M (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S) +#define UART_POSEDGE_MIN_CNT_V 0x00000FFFU +#define UART_POSEDGE_MIN_CNT_S 0 + +/** UART_NEGPULSE_REG register + * Autobaud low pulse register + */ +#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x78) +/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two negative edges. It + * is used in boudrate-detect process. + */ +#define UART_NEGEDGE_MIN_CNT 0x00000FFFU +#define UART_NEGEDGE_MIN_CNT_M (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S) +#define UART_NEGEDGE_MIN_CNT_V 0x00000FFFU +#define UART_NEGEDGE_MIN_CNT_S 0 + +/** UART_LOWPULSE_REG register + * Autobaud minimum low pulse duration register + */ +#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c) +/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the minimum duration time of the low level pulse. + * It is used in baud rate-detect process. + */ +#define UART_LOWPULSE_MIN_CNT 0x00000FFFU +#define UART_LOWPULSE_MIN_CNT_M (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S) +#define UART_LOWPULSE_MIN_CNT_V 0x00000FFFU +#define UART_LOWPULSE_MIN_CNT_S 0 + +/** UART_HIGHPULSE_REG register + * Autobaud minimum high pulse duration register + */ +#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80) +/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the maxinum duration time for the high level + * pulse. It is used in baud rate-detect process. + */ +#define UART_HIGHPULSE_MIN_CNT 0x00000FFFU +#define UART_HIGHPULSE_MIN_CNT_M (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S) +#define UART_HIGHPULSE_MIN_CNT_V 0x00000FFFU +#define UART_HIGHPULSE_MIN_CNT_S 0 + +/** UART_RXD_CNT_REG register + * Autobaud edge change count register + */ +#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x84) +/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0; + * This register stores the count of rxd edge change. It is used in baud rate-detect + * process. + */ +#define UART_RXD_EDGE_CNT 0x000003FFU +#define UART_RXD_EDGE_CNT_M (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S) +#define UART_RXD_EDGE_CNT_V 0x000003FFU +#define UART_RXD_EDGE_CNT_S 0 + +/** UART_CLK_CONF_REG register + * UART core clock configuration + */ +#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88) +/** UART_SCLK_DIV_B : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor. + */ +#define UART_SCLK_DIV_B 0x0000003FU +#define UART_SCLK_DIV_B_M (UART_SCLK_DIV_B_V << UART_SCLK_DIV_B_S) +#define UART_SCLK_DIV_B_V 0x0000003FU +#define UART_SCLK_DIV_B_S 0 +/** UART_SCLK_DIV_A : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor. + */ +#define UART_SCLK_DIV_A 0x0000003FU +#define UART_SCLK_DIV_A_M (UART_SCLK_DIV_A_V << UART_SCLK_DIV_A_S) +#define UART_SCLK_DIV_A_V 0x0000003FU +#define UART_SCLK_DIV_A_S 6 +/** UART_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1; + * The integral part of the frequency divider factor. + */ +#define UART_SCLK_DIV_NUM 0x000000FFU +#define UART_SCLK_DIV_NUM_M (UART_SCLK_DIV_NUM_V << UART_SCLK_DIV_NUM_S) +#define UART_SCLK_DIV_NUM_V 0x000000FFU +#define UART_SCLK_DIV_NUM_S 12 +/** UART_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; + * UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL. + */ +#define UART_SCLK_SEL 0x00000003U +#define UART_SCLK_SEL_M (UART_SCLK_SEL_V << UART_SCLK_SEL_S) +#define UART_SCLK_SEL_V 0x00000003U +#define UART_SCLK_SEL_S 20 +/** UART_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set this bit to enable UART Tx/Rx clock. + */ +#define UART_SCLK_EN (BIT(22)) +#define UART_SCLK_EN_M (UART_SCLK_EN_V << UART_SCLK_EN_S) +#define UART_SCLK_EN_V 0x00000001U +#define UART_SCLK_EN_S 22 +/** UART_RST_CORE : R/W; bitpos: [23]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx/Rx. + */ +#define UART_RST_CORE (BIT(23)) +#define UART_RST_CORE_M (UART_RST_CORE_V << UART_RST_CORE_S) +#define UART_RST_CORE_V 0x00000001U +#define UART_RST_CORE_S 23 +/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; + * Set this bit to enable UART Tx clock. + */ +#define UART_TX_SCLK_EN (BIT(24)) +#define UART_TX_SCLK_EN_M (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S) +#define UART_TX_SCLK_EN_V 0x00000001U +#define UART_TX_SCLK_EN_S 24 +/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1; + * Set this bit to enable UART Rx clock. + */ +#define UART_RX_SCLK_EN (BIT(25)) +#define UART_RX_SCLK_EN_M (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S) +#define UART_RX_SCLK_EN_V 0x00000001U +#define UART_RX_SCLK_EN_S 25 +/** UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx. + */ +#define UART_TX_RST_CORE (BIT(26)) +#define UART_TX_RST_CORE_M (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S) +#define UART_TX_RST_CORE_V 0x00000001U +#define UART_TX_RST_CORE_S 26 +/** UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0; + * Write 1 then write 0 to this bit to reset UART Rx. + */ +#define UART_RX_RST_CORE (BIT(27)) +#define UART_RX_RST_CORE_M (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S) +#define UART_RX_RST_CORE_V 0x00000001U +#define UART_RX_RST_CORE_S 27 + +/** UART_DATE_REG register + * UART Version register + */ +#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x8c) +/** UART_DATE : R/W; bitpos: [31:0]; default: 35656288; + * This is the version register. + */ +#define UART_DATE 0xFFFFFFFFU +#define UART_DATE_M (UART_DATE_V << UART_DATE_S) +#define UART_DATE_V 0xFFFFFFFFU +#define UART_DATE_S 0 + +/** UART_AFIFO_STATUS_REG register + * UART AFIFO Status + */ +#define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90) +/** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0; + * Full signal of APB TX AFIFO. + */ +#define UART_TX_AFIFO_FULL (BIT(0)) +#define UART_TX_AFIFO_FULL_M (UART_TX_AFIFO_FULL_V << UART_TX_AFIFO_FULL_S) +#define UART_TX_AFIFO_FULL_V 0x00000001U +#define UART_TX_AFIFO_FULL_S 0 +/** UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1; + * Empty signal of APB TX AFIFO. + */ +#define UART_TX_AFIFO_EMPTY (BIT(1)) +#define UART_TX_AFIFO_EMPTY_M (UART_TX_AFIFO_EMPTY_V << UART_TX_AFIFO_EMPTY_S) +#define UART_TX_AFIFO_EMPTY_V 0x00000001U +#define UART_TX_AFIFO_EMPTY_S 1 +/** UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0; + * Full signal of APB RX AFIFO. + */ +#define UART_RX_AFIFO_FULL (BIT(2)) +#define UART_RX_AFIFO_FULL_M (UART_RX_AFIFO_FULL_V << UART_RX_AFIFO_FULL_S) +#define UART_RX_AFIFO_FULL_V 0x00000001U +#define UART_RX_AFIFO_FULL_S 2 +/** UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1; + * Empty signal of APB RX AFIFO. + */ +#define UART_RX_AFIFO_EMPTY (BIT(3)) +#define UART_RX_AFIFO_EMPTY_M (UART_RX_AFIFO_EMPTY_V << UART_RX_AFIFO_EMPTY_S) +#define UART_RX_AFIFO_EMPTY_V 0x00000001U +#define UART_RX_AFIFO_EMPTY_S 3 + +/** UART_REG_UPDATE_REG register + * UART Registers Configuration Update register + */ +#define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98) +/** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0; + * Software write 1 would synchronize registers into UART Core clock domain and would + * be cleared by hardware after synchronization is done. + */ +#define UART_REG_UPDATE (BIT(0)) +#define UART_REG_UPDATE_M (UART_REG_UPDATE_V << UART_REG_UPDATE_S) +#define UART_REG_UPDATE_V 0x00000001U +#define UART_REG_UPDATE_S 0 + +/** UART_ID_REG register + * UART ID register + */ +#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x9c) +/** UART_ID : R/W; bitpos: [31:0]; default: 1280; + * This register is used to configure the uart_id. + */ +#define UART_ID 0xFFFFFFFFU +#define UART_ID_M (UART_ID_V << UART_ID_S) +#define UART_ID_V 0xFFFFFFFFU +#define UART_ID_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/uart_struct.h b/components/soc/esp32c6/include/soc/uart_struct.h new file mode 100644 index 0000000000..487c05b90a --- /dev/null +++ b/components/soc/esp32c6/include/soc/uart_struct.h @@ -0,0 +1,1294 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: FIFO Configuration */ +/** Type of fifo register + * FIFO data register + */ +typedef union { + struct { + /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0; + * UART $n accesses FIFO via this register. + */ + uint32_t rxfifo_rd_byte:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_fifo_reg_t; + +/** Type of mem_conf register + * UART memory power configuration + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** mem_force_pd : R/W; bitpos: [25]; default: 0; + * Set this bit to force power down UART memory. + */ + uint32_t mem_force_pd:1; + /** mem_force_pu : R/W; bitpos: [26]; default: 0; + * Set this bit to force power up UART memory. + */ + uint32_t mem_force_pu:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} uart_mem_conf_reg_t; + +/** Type of tout_conf_sync register + * UART threshold and allocation configuration + */ +typedef union { + struct { + /** rx_tout_en : R/W; bitpos: [0]; default: 0; + * This is the enble bit for uart receiver's timeout function. + */ + uint32_t rx_tout_en:1; + /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control works. + */ + uint32_t rx_tout_flow_dis:1; + /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10; + * This register is used to configure the threshold time that receiver takes to + * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver + * takes more time to receive one byte with rx_tout_en set to 1. + */ + uint32_t rx_tout_thrhd:10; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_tout_conf_sync_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** rxfifo_full : R/WTC/SS; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * what rxfifo_full_thrhd specifies. + */ + uint32_t rxfifo_full:1; + /** txfifo_empty : R/WTC/SS; bitpos: [1]; default: 1; + * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is + * less than what txfifo_empty_thrhd specifies . + */ + uint32_t txfifo_empty:1; + /** parity_err : R/WTC/SS; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error in + * the data. + */ + uint32_t parity_err:1; + /** frm_err : R/WTC/SS; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * . + */ + uint32_t frm_err:1; + /** rxfifo_ovf : R/WTC/SS; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * the FIFO can store. + */ + uint32_t rxfifo_ovf:1; + /** dsr_chg : R/WTC/SS; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * DSRn signal. + */ + uint32_t dsr_chg:1; + /** cts_chg : R/WTC/SS; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * CTSn signal. + */ + uint32_t cts_chg:1; + /** brk_det : R/WTC/SS; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 after the stop + * bit. + */ + uint32_t brk_det:1; + /** rxfifo_tout : R/WTC/SS; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more time than + * rx_tout_thrhd to receive a byte. + */ + uint32_t rxfifo_tout:1; + /** sw_xon : R/WTC/SS; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver recevies Xon char when + * uart_sw_flow_con_en is set to 1. + */ + uint32_t sw_xon:1; + /** sw_xoff : R/WTC/SS; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xoff char when + * uart_sw_flow_con_en is set to 1. + */ + uint32_t sw_xoff:1; + /** glitch_det : R/WTC/SS; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a glitch in the + * middle of a start bit. + */ + uint32_t glitch_det:1; + /** tx_brk_done : R/WTC/SS; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes sending + * NULL characters after all data in Tx-FIFO are sent. + */ + uint32_t tx_brk_done:1; + /** tx_brk_idle_done : R/WTC/SS; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept the shortest + * duration after sending the last data. + */ + uint32_t tx_brk_idle_done:1; + /** tx_done : R/WTC/SS; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has send out all data + * in FIFO. + */ + uint32_t tx_done:1; + /** rs485_parity_err : R/WTC/SS; bitpos: [15]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error + * from the echo of transmitter in rs485 mode. + */ + uint32_t rs485_parity_err:1; + /** rs485_frm_err : R/WTC/SS; bitpos: [16]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * from the echo of transmitter in rs485 mode. + */ + uint32_t rs485_frm_err:1; + /** rs485_clash : R/WTC/SS; bitpos: [17]; default: 0; + * This interrupt raw bit turns to high level when detects a clash between transmitter + * and receiver in rs485 mode. + */ + uint32_t rs485_clash:1; + /** at_cmd_char_det : R/WTC/SS; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the configured + * at_cmd char. + */ + uint32_t at_cmd_char_det:1; + /** wakeup : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes more times + * than what reg_active_threshold specifies in light sleeping mode. + */ + uint32_t wakeup:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** rxfifo_full : RO; bitpos: [0]; default: 0; + * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + */ + uint32_t rxfifo_full:1; + /** txfifo_empty : RO; bitpos: [1]; default: 0; + * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set + * to 1. + */ + uint32_t txfifo_empty:1; + /** parity_err : RO; bitpos: [2]; default: 0; + * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + */ + uint32_t parity_err:1; + /** frm_err : RO; bitpos: [3]; default: 0; + * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + */ + uint32_t frm_err:1; + /** rxfifo_ovf : RO; bitpos: [4]; default: 0; + * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + */ + uint32_t rxfifo_ovf:1; + /** dsr_chg : RO; bitpos: [5]; default: 0; + * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + */ + uint32_t dsr_chg:1; + /** cts_chg : RO; bitpos: [6]; default: 0; + * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + */ + uint32_t cts_chg:1; + /** brk_det : RO; bitpos: [7]; default: 0; + * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + */ + uint32_t brk_det:1; + /** rxfifo_tout : RO; bitpos: [8]; default: 0; + * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + */ + uint32_t rxfifo_tout:1; + /** sw_xon : RO; bitpos: [9]; default: 0; + * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + */ + uint32_t sw_xon:1; + /** sw_xoff : RO; bitpos: [10]; default: 0; + * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + */ + uint32_t sw_xoff:1; + /** glitch_det : RO; bitpos: [11]; default: 0; + * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + */ + uint32_t glitch_det:1; + /** tx_brk_done : RO; bitpos: [12]; default: 0; + * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + */ + uint32_t tx_brk_done:1; + /** tx_brk_idle_done : RO; bitpos: [13]; default: 0; + * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * is set to 1. + */ + uint32_t tx_brk_idle_done:1; + /** tx_done : RO; bitpos: [14]; default: 0; + * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + */ + uint32_t tx_done:1; + /** rs485_parity_err : RO; bitpos: [15]; default: 0; + * This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is + * set to 1. + */ + uint32_t rs485_parity_err:1; + /** rs485_frm_err : RO; bitpos: [16]; default: 0; + * This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set + * to 1. + */ + uint32_t rs485_frm_err:1; + /** rs485_clash : RO; bitpos: [17]; default: 0; + * This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + */ + uint32_t rs485_clash:1; + /** at_cmd_char_det : RO; bitpos: [18]; default: 0; + * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set + * to 1. + */ + uint32_t at_cmd_char_det:1; + /** wakeup : RO; bitpos: [19]; default: 0; + * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + */ + uint32_t wakeup:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** rxfifo_full: R/W; bitpos: [0]; default: 0; + * This is the enable bit for rxfifo_full_int_st register. + */ + uint32_t rxfifo_full:1; + /** txfifo_empty: R/W; bitpos: [1]; default: 0; + * This is the enable bit for txfifo_empty_int_st register. + */ + uint32_t txfifo_empty:1; + /** parity_err: R/W; bitpos: [2]; default: 0; + * This is the enable bit for parity_err_int_st register. + */ + uint32_t parity_err:1; + /** frm_err: R/W; bitpos: [3]; default: 0; + * This is the enable bit for frm_err_int_st register. + */ + uint32_t frm_err:1; + /** rxfifo_ovf: R/W; bitpos: [4]; default: 0; + * This is the enable bit for rxfifo_ovf_int_st register. + */ + uint32_t rxfifo_ovf:1; + /** dsr_chg: R/W; bitpos: [5]; default: 0; + * This is the enable bit for dsr_chg_int_st register. + */ + uint32_t dsr_chg:1; + /** cts_chg: R/W; bitpos: [6]; default: 0; + * This is the enable bit for cts_chg_int_st register. + */ + uint32_t cts_chg:1; + /** brk_det: R/W; bitpos: [7]; default: 0; + * This is the enable bit for brk_det_int_st register. + */ + uint32_t brk_det:1; + /** rxfifo_tout: R/W; bitpos: [8]; default: 0; + * This is the enable bit for rxfifo_tout_int_st register. + */ + uint32_t rxfifo_tout:1; + /** sw_xon: R/W; bitpos: [9]; default: 0; + * This is the enable bit for sw_xon_int_st register. + */ + uint32_t sw_xon:1; + /** sw_xoff: R/W; bitpos: [10]; default: 0; + * This is the enable bit for sw_xoff_int_st register. + */ + uint32_t sw_xoff:1; + /** glitch_det: R/W; bitpos: [11]; default: 0; + * This is the enable bit for glitch_det_int_st register. + */ + uint32_t glitch_det:1; + /** tx_brk_done: R/W; bitpos: [12]; default: 0; + * This is the enable bit for tx_brk_done_int_st register. + */ + uint32_t tx_brk_done:1; + /** tx_brk_idle_done: R/W; bitpos: [13]; default: 0; + * This is the enable bit for tx_brk_idle_done_int_st register. + */ + uint32_t tx_brk_idle_done:1; + /** tx_done: R/W; bitpos: [14]; default: 0; + * This is the enable bit for tx_done_int_st register. + */ + uint32_t tx_done:1; + /** rs485_parity_err: R/W; bitpos: [15]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ + uint32_t rs485_parity_err:1; + /** rs485_frm_err: R/W; bitpos: [16]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ + uint32_t rs485_frm_err:1; + /** rs485_clash: R/W; bitpos: [17]; default: 0; + * This is the enable bit for rs485_clash_int_st register. + */ + uint32_t rs485_clash:1; + /** at_cmd_char_det: R/W; bitpos: [18]; default: 0; + * This is the enable bit for at_cmd_char_det_int_st register. + */ + uint32_t at_cmd_char_det:1; + /** wakeup: R/W; bitpos: [19]; default: 0; + * This is the enable bit for uart_wakeup_int_st register. + */ + uint32_t wakeup:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** rxfifo_full: WT; bitpos: [0]; default: 0; + * Set this bit to clear the rxfifo_full_int_raw interrupt. + */ + uint32_t rxfifo_full:1; + /** txfifo_empty: WT; bitpos: [1]; default: 0; + * Set this bit to clear txfifo_empty_int_raw interrupt. + */ + uint32_t txfifo_empty:1; + /** parity_err: WT; bitpos: [2]; default: 0; + * Set this bit to clear parity_err_int_raw interrupt. + */ + uint32_t parity_err:1; + /** frm_err: WT; bitpos: [3]; default: 0; + * Set this bit to clear frm_err_int_raw interrupt. + */ + uint32_t frm_err:1; + /** rxfifo_ovf: WT; bitpos: [4]; default: 0; + * Set this bit to clear rxfifo_ovf_int_raw interrupt. + */ + uint32_t rxfifo_ovf:1; + /** dsr_chg: WT; bitpos: [5]; default: 0; + * Set this bit to clear the dsr_chg_int_raw interrupt. + */ + uint32_t dsr_chg:1; + /** cts_chg: WT; bitpos: [6]; default: 0; + * Set this bit to clear the cts_chg_int_raw interrupt. + */ + uint32_t cts_chg:1; + /** brk_det: WT; bitpos: [7]; default: 0; + * Set this bit to clear the brk_det_int_raw interrupt. + */ + uint32_t brk_det:1; + /** rxfifo_tout: WT; bitpos: [8]; default: 0; + * Set this bit to clear the rxfifo_tout_int_raw interrupt. + */ + uint32_t rxfifo_tout:1; + /** sw_xon: WT; bitpos: [9]; default: 0; + * Set this bit to clear the sw_xon_int_raw interrupt. + */ + uint32_t sw_xon:1; + /** sw_xoff: WT; bitpos: [10]; default: 0; + * Set this bit to clear the sw_xoff_int_raw interrupt. + */ + uint32_t sw_xoff:1; + /** glitch_det: WT; bitpos: [11]; default: 0; + * Set this bit to clear the glitch_det_int_raw interrupt. + */ + uint32_t glitch_det:1; + /** tx_brk_done: WT; bitpos: [12]; default: 0; + * Set this bit to clear the tx_brk_done_int_raw interrupt.. + */ + uint32_t tx_brk_done:1; + /** tx_brk_idle_done: WT; bitpos: [13]; default: 0; + * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + */ + uint32_t tx_brk_idle_done:1; + /** tx_done: WT; bitpos: [14]; default: 0; + * Set this bit to clear the tx_done_int_raw interrupt. + */ + uint32_t tx_done:1; + /** rs485_parity_err: WT; bitpos: [15]; default: 0; + * Set this bit to clear the rs485_parity_err_int_raw interrupt. + */ + uint32_t rs485_parity_err:1; + /** rs485_frm_err: WT; bitpos: [16]; default: 0; + * Set this bit to clear the rs485_frm_err_int_raw interrupt. + */ + uint32_t rs485_frm_err:1; + /** rs485_clash: WT; bitpos: [17]; default: 0; + * Set this bit to clear the rs485_clash_int_raw interrupt. + */ + uint32_t rs485_clash:1; + /** at_cmd_char_det: WT; bitpos: [18]; default: 0; + * Set this bit to clear the at_cmd_char_det_int_raw interrupt. + */ + uint32_t at_cmd_char_det:1; + /** wakeup: WT; bitpos: [19]; default: 0; + * Set this bit to clear the uart_wakeup_int_raw interrupt. + */ + uint32_t wakeup:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_clr_reg_t; + + +/** Group: Configuration Register */ +/** Type of clkdiv_sync register + * Clock divider configuration + */ +typedef union { + struct { + /** clkdiv_int : R/W; bitpos: [11:0]; default: 694; + * The integral part of the frequency divider factor. + */ + uint32_t clkdiv_int:12; + uint32_t reserved_12:8; + /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0; + * The decimal part of the frequency divider factor. + */ + uint32_t clkdiv_frag:4; + uint32_t reserved_24:8; + }; + uint32_t val; +} uart_clkdiv_sync_reg_t; + +/** Type of rx_filt register + * Rx Filter configuration + */ +typedef union { + struct { + /** glitch_filt : R/W; bitpos: [7:0]; default: 8; + * when input pulse width is lower than this value the pulse is ignored. + */ + uint32_t glitch_filt:8; + /** glitch_filt_en : R/W; bitpos: [8]; default: 0; + * Set this bit to enable Rx signal filter. + */ + uint32_t glitch_filt_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uart_rx_filt_reg_t; + +/** Type of conf0_sync register + * a + */ +typedef union { + struct { + /** parity : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check mode. + */ + uint32_t parity:1; + /** parity_en : R/W; bitpos: [1]; default: 0; + * Set this bit to enable uart parity check. + */ + uint32_t parity_en:1; + /** bit_num : R/W; bitpos: [3:2]; default: 3; + * This register is used to set the length of data. + */ + uint32_t bit_num:2; + /** stop_bit_num : R/W; bitpos: [5:4]; default: 1; + * This register is used to set the length of stop bit. + */ + uint32_t stop_bit_num:2; + /** txd_brk : R/W; bitpos: [6]; default: 0; + * Set this bit to enbale transmitter to send NULL when the process of sending data + * is done. + */ + uint32_t txd_brk:1; + /** irda_dplx : R/W; bitpos: [7]; default: 0; + * Set this bit to enable IrDA loopback mode. + */ + uint32_t irda_dplx:1; + /** irda_tx_en : R/W; bitpos: [8]; default: 0; + * This is the start enable bit for IrDA transmitter. + */ + uint32_t irda_tx_en:1; + /** irda_wctl : R/W; bitpos: [9]; default: 0; + * 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA + * transmitter's 11th bit to 0. + */ + uint32_t irda_wctl:1; + /** irda_tx_inv : R/W; bitpos: [10]; default: 0; + * Set this bit to invert the level of IrDA transmitter. + */ + uint32_t irda_tx_inv:1; + /** irda_rx_inv : R/W; bitpos: [11]; default: 0; + * Set this bit to invert the level of IrDA receiver. + */ + uint32_t irda_rx_inv:1; + /** loopback : R/W; bitpos: [12]; default: 0; + * Set this bit to enable uart loopback test mode. + */ + uint32_t loopback:1; + /** tx_flow_en : R/W; bitpos: [13]; default: 0; + * Set this bit to enable flow control function for transmitter. + */ + uint32_t tx_flow_en:1; + /** irda_en : R/W; bitpos: [14]; default: 0; + * Set this bit to enable IrDA protocol. + */ + uint32_t irda_en:1; + /** rxd_inv : R/W; bitpos: [15]; default: 0; + * Set this bit to inverse the level value of uart rxd signal. + */ + uint32_t rxd_inv:1; + /** txd_inv : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart txd signal. + */ + uint32_t txd_inv:1; + /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0; + * Disable UART Rx data overflow detect. + */ + uint32_t dis_rx_dat_ovf:1; + /** err_wr_mask : R/W; bitpos: [18]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver + * stores the data even if the received data is wrong. + */ + uint32_t err_wr_mask:1; + /** autobaud_en : R/W; bitpos: [19]; default: 0; + * This is the enable bit for detecting baudrate. + */ + uint32_t autobaud_en:1; + /** mem_clk_en : R/W; bitpos: [20]; default: 1; + * UART memory clock gate enable signal. + */ + uint32_t mem_clk_en:1; + /** sw_rts : R/W; bitpos: [21]; default: 0; + * This register is used to configure the software rts signal which is used in + * software flow control. + */ + uint32_t sw_rts:1; + /** rxfifo_rst : R/W; bitpos: [22]; default: 0; + * Set this bit to reset the uart receive-FIFO. + */ + uint32_t rxfifo_rst:1; + /** txfifo_rst : R/W; bitpos: [23]; default: 0; + * Set this bit to reset the uart transmit-FIFO. + */ + uint32_t txfifo_rst:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} uart_conf0_sync_reg_t; + +/** Type of conf1 register + * Configuration register 1 + */ +typedef union { + struct { + /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96; + * It will produce rxfifo_full_int interrupt when receiver receives more data than + * this register value. + */ + uint32_t rxfifo_full_thrhd:8; + /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96; + * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less + * than this register value. + */ + uint32_t txfifo_empty_thrhd:8; + /** cts_inv : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart cts signal. + */ + uint32_t cts_inv:1; + /** dsr_inv : R/W; bitpos: [17]; default: 0; + * Set this bit to inverse the level value of uart dsr signal. + */ + uint32_t dsr_inv:1; + /** rts_inv : R/W; bitpos: [18]; default: 0; + * Set this bit to inverse the level value of uart rts signal. + */ + uint32_t rts_inv:1; + /** dtr_inv : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of uart dtr signal. + */ + uint32_t dtr_inv:1; + /** sw_dtr : R/W; bitpos: [20]; default: 0; + * This register is used to configure the software dtr signal which is used in + * software flow control. + */ + uint32_t sw_dtr:1; + /** clk_en : R/W; bitpos: [21]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} uart_conf1_reg_t; + +/** Type of hwfc_conf_sync register + * Hardware flow-control configuration + */ +typedef union { + struct { + /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0; + * This register is used to configure the maximum amount of data that can be received + * when hardware flow control works. + */ + uint32_t rx_flow_thrhd:8; + /** rx_flow_en : R/W; bitpos: [8]; default: 0; + * This is the flow enable bit for UART receiver. + */ + uint32_t rx_flow_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uart_hwfc_conf_sync_reg_t; + +/** Type of sleep_conf0 register + * UART sleep configure register 0 + */ +typedef union { + struct { + /** wk_char1 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified wake up char1 to wake up + */ + uint32_t wk_char1:8; + /** wk_char2 : R/W; bitpos: [15:8]; default: 0; + * This register restores the specified wake up char2 to wake up + */ + uint32_t wk_char2:8; + /** wk_char3 : R/W; bitpos: [23:16]; default: 0; + * This register restores the specified wake up char3 to wake up + */ + uint32_t wk_char3:8; + /** wk_char4 : R/W; bitpos: [31:24]; default: 0; + * This register restores the specified wake up char4 to wake up + */ + uint32_t wk_char4:8; + }; + uint32_t val; +} uart_sleep_conf0_reg_t; + +/** Type of sleep_conf1 register + * UART sleep configure register 1 + */ +typedef union { + struct { + /** wk_char0 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified char0 to wake up + */ + uint32_t wk_char0:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_sleep_conf1_reg_t; + +/** Type of sleep_conf2 register + * UART sleep configure register 2 + */ +typedef union { + struct { + /** active_threshold : R/W; bitpos: [9:0]; default: 240; + * The uart is activated from light sleeping mode when the input rxd edge changes more + * times than this register value. + */ + uint32_t active_threshold:10; + /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1; + * In wake up mode 1 this field is used to set the received data number threshold to + * wake up chip. + */ + uint32_t rx_wake_up_thrhd:8; + /** wk_char_num : R/W; bitpos: [20:18]; default: 5; + * This register is used to select number of wake up char. + */ + uint32_t wk_char_num:3; + /** wk_char_mask : R/W; bitpos: [25:21]; default: 0; + * This register is used to mask wake up char. + */ + uint32_t wk_char_mask:5; + /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0; + * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: + * received data number larger than + */ + uint32_t wk_mode_sel:2; + uint32_t reserved_28:4; + }; + uint32_t val; +} uart_sleep_conf2_reg_t; + +/** Type of swfc_conf0_sync register + * Software flow-control character configuration + */ +typedef union { + struct { + /** xon_char : R/W; bitpos: [7:0]; default: 17; + * This register stores the Xon flow control char. + */ + uint32_t xon_char:8; + /** xoff_char : R/W; bitpos: [15:8]; default: 19; + * This register stores the Xoff flow control char. + */ + uint32_t xoff_char:8; + /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0; + * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In + * this status, UART Tx can not transmit XOFF even the received data number is larger + * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when + * UART Tx is disabled. + */ + uint32_t xon_xoff_still_send:1; + /** sw_flow_con_en : R/W; bitpos: [17]; default: 0; + * Set this bit to enable software flow control. It is used with register sw_xon or + * sw_xoff. + */ + uint32_t sw_flow_con_en:1; + /** xonoff_del : R/W; bitpos: [18]; default: 0; + * Set this bit to remove flow control char from the received data. + */ + uint32_t xonoff_del:1; + /** force_xon : R/W; bitpos: [19]; default: 0; + * Set this bit to enable the transmitter to go on sending data. + */ + uint32_t force_xon:1; + /** force_xoff : R/W; bitpos: [20]; default: 0; + * Set this bit to stop the transmitter from sending data. + */ + uint32_t force_xoff:1; + /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0; + * Set this bit to send Xon char. It is cleared by hardware automatically. + */ + uint32_t send_xon:1; + /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0; + * Set this bit to send Xoff char. It is cleared by hardware automatically. + */ + uint32_t send_xoff:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} uart_swfc_conf0_sync_reg_t; + +/** Type of swfc_conf1 register + * Software flow-control character configuration + */ +typedef union { + struct { + /** xon_threshold : R/W; bitpos: [7:0]; default: 0; + * When the data amount in Rx-FIFO is less than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xon char. + */ + uint32_t xon_threshold:8; + /** xoff_threshold : R/W; bitpos: [15:8]; default: 224; + * When the data amount in Rx-FIFO is more than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xoff char. + */ + uint32_t xoff_threshold:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_swfc_conf1_reg_t; + +/** Type of txbrk_conf_sync register + * Tx Break character configuration + */ +typedef union { + struct { + /** tx_brk_num : R/W; bitpos: [7:0]; default: 10; + * This register is used to configure the number of 0 to be sent after the process of + * sending data is done. It is active when txd_brk is set to 1. + */ + uint32_t tx_brk_num:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_txbrk_conf_sync_reg_t; + +/** Type of idle_conf_sync register + * Frame-end idle configuration + */ +typedef union { + struct { + /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256; + * It will produce frame end signal when receiver takes more time to receive one byte + * data than this register value. + */ + uint32_t rx_idle_thrhd:10; + /** tx_idle_num : R/W; bitpos: [19:10]; default: 256; + * This register is used to configure the duration time between transfers. + */ + uint32_t tx_idle_num:10; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_idle_conf_sync_reg_t; + +/** Type of rs485_conf_sync register + * RS485 mode configuration + */ +typedef union { + struct { + /** rs485_en : R/W; bitpos: [0]; default: 0; + * Set this bit to choose the rs485 mode. + */ + uint32_t rs485_en:1; + /** dl0_en : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + uint32_t dl0_en:1; + /** dl1_en : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + uint32_t dl1_en:1; + /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0; + * Set this bit to enable receiver could receive data when the transmitter is + * transmitting data in rs485 mode. + */ + uint32_t rs485tx_rx_en:1; + /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0; + * 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + */ + uint32_t rs485rxby_tx_en:1; + /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0; + * This register is used to delay the receiver's internal data signal. + */ + uint32_t rs485_rx_dly_num:1; + /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0; + * This register is used to delay the transmitter's internal data signal. + */ + uint32_t rs485_tx_dly_num:4; + uint32_t reserved_10:22; + }; + uint32_t val; +} uart_rs485_conf_sync_reg_t; + +/** Type of clk_conf register + * UART core clock configuration + */ +typedef union { + struct { + /** sclk_div_b : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor. + */ + uint32_t sclk_div_b:6; + /** sclk_div_a : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor. + */ + uint32_t sclk_div_a:6; + /** sclk_div_num : R/W; bitpos: [19:12]; default: 1; + * The integral part of the frequency divider factor. + */ + uint32_t sclk_div_num:8; + /** sclk_sel : R/W; bitpos: [21:20]; default: 3; + * UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL. + */ + uint32_t sclk_sel:2; + /** sclk_en : R/W; bitpos: [22]; default: 1; + * Set this bit to enable UART Tx/Rx clock. + */ + uint32_t sclk_en:1; + /** rst_core : R/W; bitpos: [23]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx/Rx. + */ + uint32_t rst_core:1; + /** tx_sclk_en : R/W; bitpos: [24]; default: 1; + * Set this bit to enable UART Tx clock. + */ + uint32_t tx_sclk_en:1; + /** rx_sclk_en : R/W; bitpos: [25]; default: 1; + * Set this bit to enable UART Rx clock. + */ + uint32_t rx_sclk_en:1; + /** tx_rst_core : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx. + */ + uint32_t tx_rst_core:1; + /** rx_rst_core : R/W; bitpos: [27]; default: 0; + * Write 1 then write 0 to this bit to reset UART Rx. + */ + uint32_t rx_rst_core:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} uart_clk_conf_reg_t; + + +/** Group: Status Register */ +/** Type of status register + * UART status register + */ +typedef union { + struct { + /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0; + * Stores the byte number of valid data in Rx-FIFO. + */ + uint32_t rxfifo_cnt:8; + uint32_t reserved_8:5; + /** dsrn : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal uart dsr signal. + */ + uint32_t dsrn:1; + /** ctsn : RO; bitpos: [14]; default: 1; + * This register represent the level value of the internal uart cts signal. + */ + uint32_t ctsn:1; + /** rxd : RO; bitpos: [15]; default: 1; + * This register represent the level value of the internal uart rxd signal. + */ + uint32_t rxd:1; + /** txfifo_cnt : RO; bitpos: [23:16]; default: 0; + * Stores the byte number of data in Tx-FIFO. + */ + uint32_t txfifo_cnt:8; + uint32_t reserved_24:5; + /** dtrn : RO; bitpos: [29]; default: 1; + * This bit represents the level of the internal uart dtr signal. + */ + uint32_t dtrn:1; + /** rtsn : RO; bitpos: [30]; default: 1; + * This bit represents the level of the internal uart rts signal. + */ + uint32_t rtsn:1; + /** txd : RO; bitpos: [31]; default: 1; + * This bit represents the level of the internal uart txd signal. + */ + uint32_t txd:1; + }; + uint32_t val; +} uart_status_reg_t; + +/** Type of mem_tx_status register + * Tx-SRAM write and read offset address. + */ +typedef union { + struct { + /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0; + * This register stores the offset write address in Tx-SRAM. + */ + uint32_t tx_sram_waddr:8; + uint32_t reserved_8:1; + /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0; + * This register stores the offset read address in Tx-SRAM. + */ + uint32_t tx_sram_raddr:8; + uint32_t reserved_17:15; + }; + uint32_t val; +} uart_mem_tx_status_reg_t; + +/** Type of mem_rx_status register + * Rx-SRAM write and read offset address. + */ +typedef union { + struct { + /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128; + * This register stores the offset read address in RX-SRAM. + */ + uint32_t rx_sram_raddr:8; + uint32_t reserved_8:1; + /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128; + * This register stores the offset write address in Rx-SRAM. + */ + uint32_t rx_sram_waddr:8; + uint32_t reserved_17:15; + }; + uint32_t val; +} uart_mem_rx_status_reg_t; + +/** Type of fsm_status register + * UART transmit and receive status. + */ +typedef union { + struct { + /** st_urx_out : RO; bitpos: [3:0]; default: 0; + * This is the status register of receiver. + */ + uint32_t st_urx_out:4; + /** st_utx_out : RO; bitpos: [7:4]; default: 0; + * This is the status register of transmitter. + */ + uint32_t st_utx_out:4; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_fsm_status_reg_t; + +/** Type of afifo_status register + * UART AFIFO Status + */ +typedef union { + struct { + /** tx_afifo_full : RO; bitpos: [0]; default: 0; + * Full signal of APB TX AFIFO. + */ + uint32_t tx_afifo_full:1; + /** tx_afifo_empty : RO; bitpos: [1]; default: 1; + * Empty signal of APB TX AFIFO. + */ + uint32_t tx_afifo_empty:1; + /** rx_afifo_full : RO; bitpos: [2]; default: 0; + * Full signal of APB RX AFIFO. + */ + uint32_t rx_afifo_full:1; + /** rx_afifo_empty : RO; bitpos: [3]; default: 1; + * Empty signal of APB RX AFIFO. + */ + uint32_t rx_afifo_empty:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} uart_afifo_status_reg_t; + + +/** Group: AT Escape Sequence Selection Configuration */ +/** Type of at_cmd_precnt_sync register + * Pre-sequence timing configuration + */ +typedef union { + struct { + /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the idle duration time before the first at_cmd + * is received by receiver. + */ + uint32_t pre_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_precnt_sync_reg_t; + +/** Type of at_cmd_postcnt_sync register + * Post-sequence timing configuration + */ +typedef union { + struct { + /** post_idle_num : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the duration time between the last at_cmd and + * the next data. + */ + uint32_t post_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_postcnt_sync_reg_t; + +/** Type of at_cmd_gaptout_sync register + * Timeout configuration + */ +typedef union { + struct { + /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11; + * This register is used to configure the duration time between the at_cmd chars. + */ + uint32_t rx_gap_tout:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_gaptout_sync_reg_t; + +/** Type of at_cmd_char_sync register + * AT escape sequence detection configuration + */ +typedef union { + struct { + /** data : R/W; bitpos: [7:0]; default: 43; + * This register is used to configure the content of at_cmd char. + */ + uint32_t data:8; + /** char_num : R/W; bitpos: [15:8]; default: 3; + * This register is used to configure the num of continuous at_cmd chars received by + * receiver. + */ + uint32_t char_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_char_sync_reg_t; + + +/** Group: Autobaud Register */ +/** Type of pospulse register + * Autobaud high pulse register + */ +typedef union { + struct { + /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two positive edges. It + * is used in boudrate-detect process. + */ + uint32_t posedge_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_pospulse_reg_t; + +/** Type of negpulse register + * Autobaud low pulse register + */ +typedef union { + struct { + /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two negative edges. It + * is used in boudrate-detect process. + */ + uint32_t negedge_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_negpulse_reg_t; + +/** Type of lowpulse register + * Autobaud minimum low pulse duration register + */ +typedef union { + struct { + /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the minimum duration time of the low level pulse. + * It is used in baud rate-detect process. + */ + uint32_t lowpulse_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_lowpulse_reg_t; + +/** Type of highpulse register + * Autobaud minimum high pulse duration register + */ +typedef union { + struct { + /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the maxinum duration time for the high level + * pulse. It is used in baud rate-detect process. + */ + uint32_t highpulse_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_highpulse_reg_t; + +/** Type of rxd_cnt register + * Autobaud edge change count register + */ +typedef union { + struct { + /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0; + * This register stores the count of rxd edge change. It is used in baud rate-detect + * process. + */ + uint32_t rxd_edge_cnt:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} uart_rxd_cnt_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * UART Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35656288; + * This is the version register. + */ + uint32_t date:32; + }; + uint32_t val; +} uart_date_reg_t; + +/** Type of reg_update register + * UART Registers Configuration Update register + */ +typedef union { + struct { + /** reg_update : R/W/SC; bitpos: [0]; default: 0; + * Software write 1 would synchronize registers into UART Core clock domain and would + * be cleared by hardware after synchronization is done. + */ + uint32_t reg_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} uart_reg_update_reg_t; + +/** Type of id register + * UART ID register + */ +typedef union { + struct { + /** id : R/W; bitpos: [31:0]; default: 1280; + * This register is used to configure the uart_id. + */ + uint32_t id:32; + }; + uint32_t val; +} uart_id_reg_t; + + +typedef struct uart_dev_s { + volatile uart_fifo_reg_t fifo; + volatile uart_int_raw_reg_t int_raw; + volatile uart_int_st_reg_t int_st; + volatile uart_int_ena_reg_t int_ena; + volatile uart_int_clr_reg_t int_clr; + volatile uart_clkdiv_sync_reg_t clkdiv_sync; + volatile uart_rx_filt_reg_t rx_filt; + volatile uart_status_reg_t status; + volatile uart_conf0_sync_reg_t conf0_sync; + volatile uart_conf1_reg_t conf1; + uint32_t reserved_028; + volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync; + volatile uart_sleep_conf0_reg_t sleep_conf0; + volatile uart_sleep_conf1_reg_t sleep_conf1; + volatile uart_sleep_conf2_reg_t sleep_conf2; + volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync; + volatile uart_swfc_conf1_reg_t swfc_conf1; + volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync; + volatile uart_idle_conf_sync_reg_t idle_conf_sync; + volatile uart_rs485_conf_sync_reg_t rs485_conf_sync; + volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync; + volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync; + volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync; + volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync; + volatile uart_mem_conf_reg_t mem_conf; + volatile uart_tout_conf_sync_reg_t tout_conf_sync; + volatile uart_mem_tx_status_reg_t mem_tx_status; + volatile uart_mem_rx_status_reg_t mem_rx_status; + volatile uart_fsm_status_reg_t fsm_status; + volatile uart_pospulse_reg_t pospulse; + volatile uart_negpulse_reg_t negpulse; + volatile uart_lowpulse_reg_t lowpulse; + volatile uart_highpulse_reg_t highpulse; + volatile uart_rxd_cnt_reg_t rxd_cnt; + volatile uart_clk_conf_reg_t clk_conf; + volatile uart_date_reg_t date; + volatile uart_afifo_status_reg_t afifo_status; + uint32_t reserved_094; + volatile uart_reg_update_reg_t reg_update; + volatile uart_id_reg_t id; +} uart_dev_t; + +extern uart_dev_t UART0; +extern uart_dev_t UART1; + +#ifndef __cplusplus +_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/uhci_reg.h b/components/soc/esp32c6/include/soc/uhci_reg.h new file mode 100644 index 0000000000..f8c13d973c --- /dev/null +++ b/components/soc/esp32c6/include/soc/uhci_reg.h @@ -0,0 +1,945 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** UHCI_CONF0_REG register + * a + */ +#define UHCI_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x0) +/** UHCI_TX_RST : R/W; bitpos: [0]; default: 0; + * Write 1 then write 0 to this bit to reset decode state machine. + */ +#define UHCI_TX_RST (BIT(0)) +#define UHCI_TX_RST_M (UHCI_TX_RST_V << UHCI_TX_RST_S) +#define UHCI_TX_RST_V 0x00000001U +#define UHCI_TX_RST_S 0 +/** UHCI_RX_RST : R/W; bitpos: [1]; default: 0; + * Write 1 then write 0 to this bit to reset encode state machine. + */ +#define UHCI_RX_RST (BIT(1)) +#define UHCI_RX_RST_M (UHCI_RX_RST_V << UHCI_RX_RST_S) +#define UHCI_RX_RST_V 0x00000001U +#define UHCI_RX_RST_S 1 +/** UHCI_UART0_CE : R/W; bitpos: [2]; default: 0; + * Set this bit to link up HCI and UART0. + */ +#define UHCI_UART0_CE (BIT(2)) +#define UHCI_UART0_CE_M (UHCI_UART0_CE_V << UHCI_UART0_CE_S) +#define UHCI_UART0_CE_V 0x00000001U +#define UHCI_UART0_CE_S 2 +/** UHCI_UART1_CE : R/W; bitpos: [3]; default: 0; + * Set this bit to link up HCI and UART1. + */ +#define UHCI_UART1_CE (BIT(3)) +#define UHCI_UART1_CE_M (UHCI_UART1_CE_V << UHCI_UART1_CE_S) +#define UHCI_UART1_CE_V 0x00000001U +#define UHCI_UART1_CE_S 3 +/** UHCI_SEPER_EN : R/W; bitpos: [5]; default: 1; + * Set this bit to separate the data frame using a special char. + */ +#define UHCI_SEPER_EN (BIT(5)) +#define UHCI_SEPER_EN_M (UHCI_SEPER_EN_V << UHCI_SEPER_EN_S) +#define UHCI_SEPER_EN_V 0x00000001U +#define UHCI_SEPER_EN_S 5 +/** UHCI_HEAD_EN : R/W; bitpos: [6]; default: 1; + * Set this bit to encode the data packet with a formatting header. + */ +#define UHCI_HEAD_EN (BIT(6)) +#define UHCI_HEAD_EN_M (UHCI_HEAD_EN_V << UHCI_HEAD_EN_S) +#define UHCI_HEAD_EN_V 0x00000001U +#define UHCI_HEAD_EN_S 6 +/** UHCI_CRC_REC_EN : R/W; bitpos: [7]; default: 1; + * Set this bit to enable UHCI to receive the 16 bit CRC. + */ +#define UHCI_CRC_REC_EN (BIT(7)) +#define UHCI_CRC_REC_EN_M (UHCI_CRC_REC_EN_V << UHCI_CRC_REC_EN_S) +#define UHCI_CRC_REC_EN_V 0x00000001U +#define UHCI_CRC_REC_EN_S 7 +/** UHCI_UART_IDLE_EOF_EN : R/W; bitpos: [8]; default: 0; + * If this bit is set to 1 UHCI will end the payload receiving process when UART has + * been in idle state. + */ +#define UHCI_UART_IDLE_EOF_EN (BIT(8)) +#define UHCI_UART_IDLE_EOF_EN_M (UHCI_UART_IDLE_EOF_EN_V << UHCI_UART_IDLE_EOF_EN_S) +#define UHCI_UART_IDLE_EOF_EN_V 0x00000001U +#define UHCI_UART_IDLE_EOF_EN_S 8 +/** UHCI_LEN_EOF_EN : R/W; bitpos: [9]; default: 1; + * If this bit is set to 1 UHCI decoder receiving payload data is end when the + * receiving byte count has reached the specified value. The value is payload length + * indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is + * configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder + * receiving payload data is end when 0xc0 is received. + */ +#define UHCI_LEN_EOF_EN (BIT(9)) +#define UHCI_LEN_EOF_EN_M (UHCI_LEN_EOF_EN_V << UHCI_LEN_EOF_EN_S) +#define UHCI_LEN_EOF_EN_V 0x00000001U +#define UHCI_LEN_EOF_EN_S 9 +/** UHCI_ENCODE_CRC_EN : R/W; bitpos: [10]; default: 1; + * Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to + * end of the payload. + */ +#define UHCI_ENCODE_CRC_EN (BIT(10)) +#define UHCI_ENCODE_CRC_EN_M (UHCI_ENCODE_CRC_EN_V << UHCI_ENCODE_CRC_EN_S) +#define UHCI_ENCODE_CRC_EN_V 0x00000001U +#define UHCI_ENCODE_CRC_EN_S 10 +/** UHCI_CLK_EN : R/W; bitpos: [11]; default: 0; + * 1'b1: Force clock on for register. 1'b0: Support clock only when application writes + * registers. + */ +#define UHCI_CLK_EN (BIT(11)) +#define UHCI_CLK_EN_M (UHCI_CLK_EN_V << UHCI_CLK_EN_S) +#define UHCI_CLK_EN_V 0x00000001U +#define UHCI_CLK_EN_S 11 +/** UHCI_UART_RX_BRK_EOF_EN : R/W; bitpos: [12]; default: 0; + * If this bit is set to 1 UHCI will end payload receive process when NULL frame is + * received by UART. + */ +#define UHCI_UART_RX_BRK_EOF_EN (BIT(12)) +#define UHCI_UART_RX_BRK_EOF_EN_M (UHCI_UART_RX_BRK_EOF_EN_V << UHCI_UART_RX_BRK_EOF_EN_S) +#define UHCI_UART_RX_BRK_EOF_EN_V 0x00000001U +#define UHCI_UART_RX_BRK_EOF_EN_S 12 + +/** UHCI_INT_RAW_REG register + * a + */ +#define UHCI_INT_RAW_REG(i) (REG_UHCI_BASE(i) + 0x4) +/** UHCI_RX_START_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * a + */ +#define UHCI_RX_START_INT_RAW (BIT(0)) +#define UHCI_RX_START_INT_RAW_M (UHCI_RX_START_INT_RAW_V << UHCI_RX_START_INT_RAW_S) +#define UHCI_RX_START_INT_RAW_V 0x00000001U +#define UHCI_RX_START_INT_RAW_S 0 +/** UHCI_TX_START_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * a + */ +#define UHCI_TX_START_INT_RAW (BIT(1)) +#define UHCI_TX_START_INT_RAW_M (UHCI_TX_START_INT_RAW_V << UHCI_TX_START_INT_RAW_S) +#define UHCI_TX_START_INT_RAW_V 0x00000001U +#define UHCI_TX_START_INT_RAW_S 1 +/** UHCI_RX_HUNG_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * a + */ +#define UHCI_RX_HUNG_INT_RAW (BIT(2)) +#define UHCI_RX_HUNG_INT_RAW_M (UHCI_RX_HUNG_INT_RAW_V << UHCI_RX_HUNG_INT_RAW_S) +#define UHCI_RX_HUNG_INT_RAW_V 0x00000001U +#define UHCI_RX_HUNG_INT_RAW_S 2 +/** UHCI_TX_HUNG_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * a + */ +#define UHCI_TX_HUNG_INT_RAW (BIT(3)) +#define UHCI_TX_HUNG_INT_RAW_M (UHCI_TX_HUNG_INT_RAW_V << UHCI_TX_HUNG_INT_RAW_S) +#define UHCI_TX_HUNG_INT_RAW_V 0x00000001U +#define UHCI_TX_HUNG_INT_RAW_S 3 +/** UHCI_SEND_S_REG_Q_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * a + */ +#define UHCI_SEND_S_REG_Q_INT_RAW (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_RAW_M (UHCI_SEND_S_REG_Q_INT_RAW_V << UHCI_SEND_S_REG_Q_INT_RAW_S) +#define UHCI_SEND_S_REG_Q_INT_RAW_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_RAW_S 4 +/** UHCI_SEND_A_REG_Q_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * a + */ +#define UHCI_SEND_A_REG_Q_INT_RAW (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_RAW_M (UHCI_SEND_A_REG_Q_INT_RAW_V << UHCI_SEND_A_REG_Q_INT_RAW_S) +#define UHCI_SEND_A_REG_Q_INT_RAW_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_RAW_S 5 +/** UHCI_OUT_EOF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This is the interrupt raw bit. Triggered when there are some errors in EOF in the + */ +#define UHCI_OUT_EOF_INT_RAW (BIT(6)) +#define UHCI_OUT_EOF_INT_RAW_M (UHCI_OUT_EOF_INT_RAW_V << UHCI_OUT_EOF_INT_RAW_S) +#define UHCI_OUT_EOF_INT_RAW_V 0x00000001U +#define UHCI_OUT_EOF_INT_RAW_S 6 +/** UHCI_APP_CTRL0_INT_RAW : R/W; bitpos: [7]; default: 0; + * Soft control int raw bit. + */ +#define UHCI_APP_CTRL0_INT_RAW (BIT(7)) +#define UHCI_APP_CTRL0_INT_RAW_M (UHCI_APP_CTRL0_INT_RAW_V << UHCI_APP_CTRL0_INT_RAW_S) +#define UHCI_APP_CTRL0_INT_RAW_V 0x00000001U +#define UHCI_APP_CTRL0_INT_RAW_S 7 +/** UHCI_APP_CTRL1_INT_RAW : R/W; bitpos: [8]; default: 0; + * Soft control int raw bit. + */ +#define UHCI_APP_CTRL1_INT_RAW (BIT(8)) +#define UHCI_APP_CTRL1_INT_RAW_M (UHCI_APP_CTRL1_INT_RAW_V << UHCI_APP_CTRL1_INT_RAW_S) +#define UHCI_APP_CTRL1_INT_RAW_V 0x00000001U +#define UHCI_APP_CTRL1_INT_RAW_S 8 + +/** UHCI_INT_ST_REG register + * a + */ +#define UHCI_INT_ST_REG(i) (REG_UHCI_BASE(i) + 0x8) +/** UHCI_RX_START_INT_ST : RO; bitpos: [0]; default: 0; + * a + */ +#define UHCI_RX_START_INT_ST (BIT(0)) +#define UHCI_RX_START_INT_ST_M (UHCI_RX_START_INT_ST_V << UHCI_RX_START_INT_ST_S) +#define UHCI_RX_START_INT_ST_V 0x00000001U +#define UHCI_RX_START_INT_ST_S 0 +/** UHCI_TX_START_INT_ST : RO; bitpos: [1]; default: 0; + * a + */ +#define UHCI_TX_START_INT_ST (BIT(1)) +#define UHCI_TX_START_INT_ST_M (UHCI_TX_START_INT_ST_V << UHCI_TX_START_INT_ST_S) +#define UHCI_TX_START_INT_ST_V 0x00000001U +#define UHCI_TX_START_INT_ST_S 1 +/** UHCI_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0; + * a + */ +#define UHCI_RX_HUNG_INT_ST (BIT(2)) +#define UHCI_RX_HUNG_INT_ST_M (UHCI_RX_HUNG_INT_ST_V << UHCI_RX_HUNG_INT_ST_S) +#define UHCI_RX_HUNG_INT_ST_V 0x00000001U +#define UHCI_RX_HUNG_INT_ST_S 2 +/** UHCI_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0; + * a + */ +#define UHCI_TX_HUNG_INT_ST (BIT(3)) +#define UHCI_TX_HUNG_INT_ST_M (UHCI_TX_HUNG_INT_ST_V << UHCI_TX_HUNG_INT_ST_S) +#define UHCI_TX_HUNG_INT_ST_V 0x00000001U +#define UHCI_TX_HUNG_INT_ST_S 3 +/** UHCI_SEND_S_REG_Q_INT_ST : RO; bitpos: [4]; default: 0; + * a + */ +#define UHCI_SEND_S_REG_Q_INT_ST (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_ST_M (UHCI_SEND_S_REG_Q_INT_ST_V << UHCI_SEND_S_REG_Q_INT_ST_S) +#define UHCI_SEND_S_REG_Q_INT_ST_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_ST_S 4 +/** UHCI_SEND_A_REG_Q_INT_ST : RO; bitpos: [5]; default: 0; + * a + */ +#define UHCI_SEND_A_REG_Q_INT_ST (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_ST_M (UHCI_SEND_A_REG_Q_INT_ST_V << UHCI_SEND_A_REG_Q_INT_ST_S) +#define UHCI_SEND_A_REG_Q_INT_ST_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_ST_S 5 +/** UHCI_OUTLINK_EOF_ERR_INT_ST : RO; bitpos: [6]; default: 0; + * a + */ +#define UHCI_OUTLINK_EOF_ERR_INT_ST (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_ST_M (UHCI_OUTLINK_EOF_ERR_INT_ST_V << UHCI_OUTLINK_EOF_ERR_INT_ST_S) +#define UHCI_OUTLINK_EOF_ERR_INT_ST_V 0x00000001U +#define UHCI_OUTLINK_EOF_ERR_INT_ST_S 6 +/** UHCI_APP_CTRL0_INT_ST : RO; bitpos: [7]; default: 0; + * a + */ +#define UHCI_APP_CTRL0_INT_ST (BIT(7)) +#define UHCI_APP_CTRL0_INT_ST_M (UHCI_APP_CTRL0_INT_ST_V << UHCI_APP_CTRL0_INT_ST_S) +#define UHCI_APP_CTRL0_INT_ST_V 0x00000001U +#define UHCI_APP_CTRL0_INT_ST_S 7 +/** UHCI_APP_CTRL1_INT_ST : RO; bitpos: [8]; default: 0; + * a + */ +#define UHCI_APP_CTRL1_INT_ST (BIT(8)) +#define UHCI_APP_CTRL1_INT_ST_M (UHCI_APP_CTRL1_INT_ST_V << UHCI_APP_CTRL1_INT_ST_S) +#define UHCI_APP_CTRL1_INT_ST_V 0x00000001U +#define UHCI_APP_CTRL1_INT_ST_S 8 + +/** UHCI_INT_ENA_REG register + * a + */ +#define UHCI_INT_ENA_REG(i) (REG_UHCI_BASE(i) + 0xc) +/** UHCI_RX_START_INT_ENA : R/W; bitpos: [0]; default: 0; + * a + */ +#define UHCI_RX_START_INT_ENA (BIT(0)) +#define UHCI_RX_START_INT_ENA_M (UHCI_RX_START_INT_ENA_V << UHCI_RX_START_INT_ENA_S) +#define UHCI_RX_START_INT_ENA_V 0x00000001U +#define UHCI_RX_START_INT_ENA_S 0 +/** UHCI_TX_START_INT_ENA : R/W; bitpos: [1]; default: 0; + * a + */ +#define UHCI_TX_START_INT_ENA (BIT(1)) +#define UHCI_TX_START_INT_ENA_M (UHCI_TX_START_INT_ENA_V << UHCI_TX_START_INT_ENA_S) +#define UHCI_TX_START_INT_ENA_V 0x00000001U +#define UHCI_TX_START_INT_ENA_S 1 +/** UHCI_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0; + * a + */ +#define UHCI_RX_HUNG_INT_ENA (BIT(2)) +#define UHCI_RX_HUNG_INT_ENA_M (UHCI_RX_HUNG_INT_ENA_V << UHCI_RX_HUNG_INT_ENA_S) +#define UHCI_RX_HUNG_INT_ENA_V 0x00000001U +#define UHCI_RX_HUNG_INT_ENA_S 2 +/** UHCI_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0; + * a + */ +#define UHCI_TX_HUNG_INT_ENA (BIT(3)) +#define UHCI_TX_HUNG_INT_ENA_M (UHCI_TX_HUNG_INT_ENA_V << UHCI_TX_HUNG_INT_ENA_S) +#define UHCI_TX_HUNG_INT_ENA_V 0x00000001U +#define UHCI_TX_HUNG_INT_ENA_S 3 +/** UHCI_SEND_S_REG_Q_INT_ENA : R/W; bitpos: [4]; default: 0; + * a + */ +#define UHCI_SEND_S_REG_Q_INT_ENA (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_ENA_M (UHCI_SEND_S_REG_Q_INT_ENA_V << UHCI_SEND_S_REG_Q_INT_ENA_S) +#define UHCI_SEND_S_REG_Q_INT_ENA_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_ENA_S 4 +/** UHCI_SEND_A_REG_Q_INT_ENA : R/W; bitpos: [5]; default: 0; + * a + */ +#define UHCI_SEND_A_REG_Q_INT_ENA (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_ENA_M (UHCI_SEND_A_REG_Q_INT_ENA_V << UHCI_SEND_A_REG_Q_INT_ENA_S) +#define UHCI_SEND_A_REG_Q_INT_ENA_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_ENA_S 5 +/** UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; + * a + */ +#define UHCI_OUTLINK_EOF_ERR_INT_ENA (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M (UHCI_OUTLINK_EOF_ERR_INT_ENA_V << UHCI_OUTLINK_EOF_ERR_INT_ENA_S) +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V 0x00000001U +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S 6 +/** UHCI_APP_CTRL0_INT_ENA : R/W; bitpos: [7]; default: 0; + * a + */ +#define UHCI_APP_CTRL0_INT_ENA (BIT(7)) +#define UHCI_APP_CTRL0_INT_ENA_M (UHCI_APP_CTRL0_INT_ENA_V << UHCI_APP_CTRL0_INT_ENA_S) +#define UHCI_APP_CTRL0_INT_ENA_V 0x00000001U +#define UHCI_APP_CTRL0_INT_ENA_S 7 +/** UHCI_APP_CTRL1_INT_ENA : R/W; bitpos: [8]; default: 0; + * a + */ +#define UHCI_APP_CTRL1_INT_ENA (BIT(8)) +#define UHCI_APP_CTRL1_INT_ENA_M (UHCI_APP_CTRL1_INT_ENA_V << UHCI_APP_CTRL1_INT_ENA_S) +#define UHCI_APP_CTRL1_INT_ENA_V 0x00000001U +#define UHCI_APP_CTRL1_INT_ENA_S 8 + +/** UHCI_INT_CLR_REG register + * a + */ +#define UHCI_INT_CLR_REG(i) (REG_UHCI_BASE(i) + 0x10) +/** UHCI_RX_START_INT_CLR : WT; bitpos: [0]; default: 0; + * a + */ +#define UHCI_RX_START_INT_CLR (BIT(0)) +#define UHCI_RX_START_INT_CLR_M (UHCI_RX_START_INT_CLR_V << UHCI_RX_START_INT_CLR_S) +#define UHCI_RX_START_INT_CLR_V 0x00000001U +#define UHCI_RX_START_INT_CLR_S 0 +/** UHCI_TX_START_INT_CLR : WT; bitpos: [1]; default: 0; + * a + */ +#define UHCI_TX_START_INT_CLR (BIT(1)) +#define UHCI_TX_START_INT_CLR_M (UHCI_TX_START_INT_CLR_V << UHCI_TX_START_INT_CLR_S) +#define UHCI_TX_START_INT_CLR_V 0x00000001U +#define UHCI_TX_START_INT_CLR_S 1 +/** UHCI_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0; + * a + */ +#define UHCI_RX_HUNG_INT_CLR (BIT(2)) +#define UHCI_RX_HUNG_INT_CLR_M (UHCI_RX_HUNG_INT_CLR_V << UHCI_RX_HUNG_INT_CLR_S) +#define UHCI_RX_HUNG_INT_CLR_V 0x00000001U +#define UHCI_RX_HUNG_INT_CLR_S 2 +/** UHCI_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0; + * a + */ +#define UHCI_TX_HUNG_INT_CLR (BIT(3)) +#define UHCI_TX_HUNG_INT_CLR_M (UHCI_TX_HUNG_INT_CLR_V << UHCI_TX_HUNG_INT_CLR_S) +#define UHCI_TX_HUNG_INT_CLR_V 0x00000001U +#define UHCI_TX_HUNG_INT_CLR_S 3 +/** UHCI_SEND_S_REG_Q_INT_CLR : WT; bitpos: [4]; default: 0; + * a + */ +#define UHCI_SEND_S_REG_Q_INT_CLR (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_CLR_M (UHCI_SEND_S_REG_Q_INT_CLR_V << UHCI_SEND_S_REG_Q_INT_CLR_S) +#define UHCI_SEND_S_REG_Q_INT_CLR_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_CLR_S 4 +/** UHCI_SEND_A_REG_Q_INT_CLR : WT; bitpos: [5]; default: 0; + * a + */ +#define UHCI_SEND_A_REG_Q_INT_CLR (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_CLR_M (UHCI_SEND_A_REG_Q_INT_CLR_V << UHCI_SEND_A_REG_Q_INT_CLR_S) +#define UHCI_SEND_A_REG_Q_INT_CLR_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_CLR_S 5 +/** UHCI_OUTLINK_EOF_ERR_INT_CLR : WT; bitpos: [6]; default: 0; + * a + */ +#define UHCI_OUTLINK_EOF_ERR_INT_CLR (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M (UHCI_OUTLINK_EOF_ERR_INT_CLR_V << UHCI_OUTLINK_EOF_ERR_INT_CLR_S) +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V 0x00000001U +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S 6 +/** UHCI_APP_CTRL0_INT_CLR : WT; bitpos: [7]; default: 0; + * a + */ +#define UHCI_APP_CTRL0_INT_CLR (BIT(7)) +#define UHCI_APP_CTRL0_INT_CLR_M (UHCI_APP_CTRL0_INT_CLR_V << UHCI_APP_CTRL0_INT_CLR_S) +#define UHCI_APP_CTRL0_INT_CLR_V 0x00000001U +#define UHCI_APP_CTRL0_INT_CLR_S 7 +/** UHCI_APP_CTRL1_INT_CLR : WT; bitpos: [8]; default: 0; + * a + */ +#define UHCI_APP_CTRL1_INT_CLR (BIT(8)) +#define UHCI_APP_CTRL1_INT_CLR_M (UHCI_APP_CTRL1_INT_CLR_V << UHCI_APP_CTRL1_INT_CLR_S) +#define UHCI_APP_CTRL1_INT_CLR_V 0x00000001U +#define UHCI_APP_CTRL1_INT_CLR_S 8 + +/** UHCI_CONF1_REG register + * a + */ +#define UHCI_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x14) +/** UHCI_CHECK_SUM_EN : R/W; bitpos: [0]; default: 1; + * a + */ +#define UHCI_CHECK_SUM_EN (BIT(0)) +#define UHCI_CHECK_SUM_EN_M (UHCI_CHECK_SUM_EN_V << UHCI_CHECK_SUM_EN_S) +#define UHCI_CHECK_SUM_EN_V 0x00000001U +#define UHCI_CHECK_SUM_EN_S 0 +/** UHCI_CHECK_SEQ_EN : R/W; bitpos: [1]; default: 1; + * a + */ +#define UHCI_CHECK_SEQ_EN (BIT(1)) +#define UHCI_CHECK_SEQ_EN_M (UHCI_CHECK_SEQ_EN_V << UHCI_CHECK_SEQ_EN_S) +#define UHCI_CHECK_SEQ_EN_V 0x00000001U +#define UHCI_CHECK_SEQ_EN_S 1 +/** UHCI_CRC_DISABLE : R/W; bitpos: [2]; default: 0; + * a + */ +#define UHCI_CRC_DISABLE (BIT(2)) +#define UHCI_CRC_DISABLE_M (UHCI_CRC_DISABLE_V << UHCI_CRC_DISABLE_S) +#define UHCI_CRC_DISABLE_V 0x00000001U +#define UHCI_CRC_DISABLE_S 2 +/** UHCI_SAVE_HEAD : R/W; bitpos: [3]; default: 0; + * a + */ +#define UHCI_SAVE_HEAD (BIT(3)) +#define UHCI_SAVE_HEAD_M (UHCI_SAVE_HEAD_V << UHCI_SAVE_HEAD_S) +#define UHCI_SAVE_HEAD_V 0x00000001U +#define UHCI_SAVE_HEAD_S 3 +/** UHCI_TX_CHECK_SUM_RE : R/W; bitpos: [4]; default: 1; + * a + */ +#define UHCI_TX_CHECK_SUM_RE (BIT(4)) +#define UHCI_TX_CHECK_SUM_RE_M (UHCI_TX_CHECK_SUM_RE_V << UHCI_TX_CHECK_SUM_RE_S) +#define UHCI_TX_CHECK_SUM_RE_V 0x00000001U +#define UHCI_TX_CHECK_SUM_RE_S 4 +/** UHCI_TX_ACK_NUM_RE : R/W; bitpos: [5]; default: 1; + * a + */ +#define UHCI_TX_ACK_NUM_RE (BIT(5)) +#define UHCI_TX_ACK_NUM_RE_M (UHCI_TX_ACK_NUM_RE_V << UHCI_TX_ACK_NUM_RE_S) +#define UHCI_TX_ACK_NUM_RE_V 0x00000001U +#define UHCI_TX_ACK_NUM_RE_S 5 +/** UHCI_WAIT_SW_START : R/W; bitpos: [7]; default: 0; + * a + */ +#define UHCI_WAIT_SW_START (BIT(7)) +#define UHCI_WAIT_SW_START_M (UHCI_WAIT_SW_START_V << UHCI_WAIT_SW_START_S) +#define UHCI_WAIT_SW_START_V 0x00000001U +#define UHCI_WAIT_SW_START_S 7 +/** UHCI_SW_START : WT; bitpos: [8]; default: 0; + * a + */ +#define UHCI_SW_START (BIT(8)) +#define UHCI_SW_START_M (UHCI_SW_START_V << UHCI_SW_START_S) +#define UHCI_SW_START_V 0x00000001U +#define UHCI_SW_START_S 8 + +/** UHCI_STATE0_REG register + * a + */ +#define UHCI_STATE0_REG(i) (REG_UHCI_BASE(i) + 0x18) +/** UHCI_RX_ERR_CAUSE : RO; bitpos: [2:0]; default: 0; + * a + */ +#define UHCI_RX_ERR_CAUSE 0x00000007U +#define UHCI_RX_ERR_CAUSE_M (UHCI_RX_ERR_CAUSE_V << UHCI_RX_ERR_CAUSE_S) +#define UHCI_RX_ERR_CAUSE_V 0x00000007U +#define UHCI_RX_ERR_CAUSE_S 0 +/** UHCI_DECODE_STATE : RO; bitpos: [5:3]; default: 0; + * a + */ +#define UHCI_DECODE_STATE 0x00000007U +#define UHCI_DECODE_STATE_M (UHCI_DECODE_STATE_V << UHCI_DECODE_STATE_S) +#define UHCI_DECODE_STATE_V 0x00000007U +#define UHCI_DECODE_STATE_S 3 + +/** UHCI_STATE1_REG register + * a + */ +#define UHCI_STATE1_REG(i) (REG_UHCI_BASE(i) + 0x1c) +/** UHCI_ENCODE_STATE : RO; bitpos: [2:0]; default: 0; + * a + */ +#define UHCI_ENCODE_STATE 0x00000007U +#define UHCI_ENCODE_STATE_M (UHCI_ENCODE_STATE_V << UHCI_ENCODE_STATE_S) +#define UHCI_ENCODE_STATE_V 0x00000007U +#define UHCI_ENCODE_STATE_S 0 + +/** UHCI_ESCAPE_CONF_REG register + * a + */ +#define UHCI_ESCAPE_CONF_REG(i) (REG_UHCI_BASE(i) + 0x20) +/** UHCI_TX_C0_ESC_EN : R/W; bitpos: [0]; default: 1; + * a + */ +#define UHCI_TX_C0_ESC_EN (BIT(0)) +#define UHCI_TX_C0_ESC_EN_M (UHCI_TX_C0_ESC_EN_V << UHCI_TX_C0_ESC_EN_S) +#define UHCI_TX_C0_ESC_EN_V 0x00000001U +#define UHCI_TX_C0_ESC_EN_S 0 +/** UHCI_TX_DB_ESC_EN : R/W; bitpos: [1]; default: 1; + * a + */ +#define UHCI_TX_DB_ESC_EN (BIT(1)) +#define UHCI_TX_DB_ESC_EN_M (UHCI_TX_DB_ESC_EN_V << UHCI_TX_DB_ESC_EN_S) +#define UHCI_TX_DB_ESC_EN_V 0x00000001U +#define UHCI_TX_DB_ESC_EN_S 1 +/** UHCI_TX_11_ESC_EN : R/W; bitpos: [2]; default: 0; + * a + */ +#define UHCI_TX_11_ESC_EN (BIT(2)) +#define UHCI_TX_11_ESC_EN_M (UHCI_TX_11_ESC_EN_V << UHCI_TX_11_ESC_EN_S) +#define UHCI_TX_11_ESC_EN_V 0x00000001U +#define UHCI_TX_11_ESC_EN_S 2 +/** UHCI_TX_13_ESC_EN : R/W; bitpos: [3]; default: 0; + * a + */ +#define UHCI_TX_13_ESC_EN (BIT(3)) +#define UHCI_TX_13_ESC_EN_M (UHCI_TX_13_ESC_EN_V << UHCI_TX_13_ESC_EN_S) +#define UHCI_TX_13_ESC_EN_V 0x00000001U +#define UHCI_TX_13_ESC_EN_S 3 +/** UHCI_RX_C0_ESC_EN : R/W; bitpos: [4]; default: 1; + * a + */ +#define UHCI_RX_C0_ESC_EN (BIT(4)) +#define UHCI_RX_C0_ESC_EN_M (UHCI_RX_C0_ESC_EN_V << UHCI_RX_C0_ESC_EN_S) +#define UHCI_RX_C0_ESC_EN_V 0x00000001U +#define UHCI_RX_C0_ESC_EN_S 4 +/** UHCI_RX_DB_ESC_EN : R/W; bitpos: [5]; default: 1; + * a + */ +#define UHCI_RX_DB_ESC_EN (BIT(5)) +#define UHCI_RX_DB_ESC_EN_M (UHCI_RX_DB_ESC_EN_V << UHCI_RX_DB_ESC_EN_S) +#define UHCI_RX_DB_ESC_EN_V 0x00000001U +#define UHCI_RX_DB_ESC_EN_S 5 +/** UHCI_RX_11_ESC_EN : R/W; bitpos: [6]; default: 0; + * a + */ +#define UHCI_RX_11_ESC_EN (BIT(6)) +#define UHCI_RX_11_ESC_EN_M (UHCI_RX_11_ESC_EN_V << UHCI_RX_11_ESC_EN_S) +#define UHCI_RX_11_ESC_EN_V 0x00000001U +#define UHCI_RX_11_ESC_EN_S 6 +/** UHCI_RX_13_ESC_EN : R/W; bitpos: [7]; default: 0; + * a + */ +#define UHCI_RX_13_ESC_EN (BIT(7)) +#define UHCI_RX_13_ESC_EN_M (UHCI_RX_13_ESC_EN_V << UHCI_RX_13_ESC_EN_S) +#define UHCI_RX_13_ESC_EN_V 0x00000001U +#define UHCI_RX_13_ESC_EN_S 7 + +/** UHCI_HUNG_CONF_REG register + * a + */ +#define UHCI_HUNG_CONF_REG(i) (REG_UHCI_BASE(i) + 0x24) +/** UHCI_TXFIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16; + * a + */ +#define UHCI_TXFIFO_TIMEOUT 0x000000FFU +#define UHCI_TXFIFO_TIMEOUT_M (UHCI_TXFIFO_TIMEOUT_V << UHCI_TXFIFO_TIMEOUT_S) +#define UHCI_TXFIFO_TIMEOUT_V 0x000000FFU +#define UHCI_TXFIFO_TIMEOUT_S 0 +/** UHCI_TXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0; + * a + */ +#define UHCI_TXFIFO_TIMEOUT_SHIFT 0x00000007U +#define UHCI_TXFIFO_TIMEOUT_SHIFT_M (UHCI_TXFIFO_TIMEOUT_SHIFT_V << UHCI_TXFIFO_TIMEOUT_SHIFT_S) +#define UHCI_TXFIFO_TIMEOUT_SHIFT_V 0x00000007U +#define UHCI_TXFIFO_TIMEOUT_SHIFT_S 8 +/** UHCI_TXFIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1; + * a + */ +#define UHCI_TXFIFO_TIMEOUT_ENA (BIT(11)) +#define UHCI_TXFIFO_TIMEOUT_ENA_M (UHCI_TXFIFO_TIMEOUT_ENA_V << UHCI_TXFIFO_TIMEOUT_ENA_S) +#define UHCI_TXFIFO_TIMEOUT_ENA_V 0x00000001U +#define UHCI_TXFIFO_TIMEOUT_ENA_S 11 +/** UHCI_RXFIFO_TIMEOUT : R/W; bitpos: [19:12]; default: 16; + * a + */ +#define UHCI_RXFIFO_TIMEOUT 0x000000FFU +#define UHCI_RXFIFO_TIMEOUT_M (UHCI_RXFIFO_TIMEOUT_V << UHCI_RXFIFO_TIMEOUT_S) +#define UHCI_RXFIFO_TIMEOUT_V 0x000000FFU +#define UHCI_RXFIFO_TIMEOUT_S 12 +/** UHCI_RXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [22:20]; default: 0; + * a + */ +#define UHCI_RXFIFO_TIMEOUT_SHIFT 0x00000007U +#define UHCI_RXFIFO_TIMEOUT_SHIFT_M (UHCI_RXFIFO_TIMEOUT_SHIFT_V << UHCI_RXFIFO_TIMEOUT_SHIFT_S) +#define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x00000007U +#define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20 +/** UHCI_RXFIFO_TIMEOUT_ENA : R/W; bitpos: [23]; default: 1; + * a + */ +#define UHCI_RXFIFO_TIMEOUT_ENA (BIT(23)) +#define UHCI_RXFIFO_TIMEOUT_ENA_M (UHCI_RXFIFO_TIMEOUT_ENA_V << UHCI_RXFIFO_TIMEOUT_ENA_S) +#define UHCI_RXFIFO_TIMEOUT_ENA_V 0x00000001U +#define UHCI_RXFIFO_TIMEOUT_ENA_S 23 + +/** UHCI_ACK_NUM_REG register + * a + */ +#define UHCI_ACK_NUM_REG(i) (REG_UHCI_BASE(i) + 0x28) +/** UHCI_ACK_NUM : R/W; bitpos: [2:0]; default: 0; + * a + */ +#define UHCI_ACK_NUM 0x00000007U +#define UHCI_ACK_NUM_M (UHCI_ACK_NUM_V << UHCI_ACK_NUM_S) +#define UHCI_ACK_NUM_V 0x00000007U +#define UHCI_ACK_NUM_S 0 +/** UHCI_ACK_NUM_LOAD : WT; bitpos: [3]; default: 0; + * a + */ +#define UHCI_ACK_NUM_LOAD (BIT(3)) +#define UHCI_ACK_NUM_LOAD_M (UHCI_ACK_NUM_LOAD_V << UHCI_ACK_NUM_LOAD_S) +#define UHCI_ACK_NUM_LOAD_V 0x00000001U +#define UHCI_ACK_NUM_LOAD_S 3 + +/** UHCI_RX_HEAD_REG register + * a + */ +#define UHCI_RX_HEAD_REG(i) (REG_UHCI_BASE(i) + 0x2c) +/** UHCI_RX_HEAD : RO; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_RX_HEAD 0xFFFFFFFFU +#define UHCI_RX_HEAD_M (UHCI_RX_HEAD_V << UHCI_RX_HEAD_S) +#define UHCI_RX_HEAD_V 0xFFFFFFFFU +#define UHCI_RX_HEAD_S 0 + +/** UHCI_QUICK_SENT_REG register + * a + */ +#define UHCI_QUICK_SENT_REG(i) (REG_UHCI_BASE(i) + 0x30) +/** UHCI_SINGLE_SEND_NUM : R/W; bitpos: [2:0]; default: 0; + * a + */ +#define UHCI_SINGLE_SEND_NUM 0x00000007U +#define UHCI_SINGLE_SEND_NUM_M (UHCI_SINGLE_SEND_NUM_V << UHCI_SINGLE_SEND_NUM_S) +#define UHCI_SINGLE_SEND_NUM_V 0x00000007U +#define UHCI_SINGLE_SEND_NUM_S 0 +/** UHCI_SINGLE_SEND_EN : WT; bitpos: [3]; default: 0; + * a + */ +#define UHCI_SINGLE_SEND_EN (BIT(3)) +#define UHCI_SINGLE_SEND_EN_M (UHCI_SINGLE_SEND_EN_V << UHCI_SINGLE_SEND_EN_S) +#define UHCI_SINGLE_SEND_EN_V 0x00000001U +#define UHCI_SINGLE_SEND_EN_S 3 +/** UHCI_ALWAYS_SEND_NUM : R/W; bitpos: [6:4]; default: 0; + * a + */ +#define UHCI_ALWAYS_SEND_NUM 0x00000007U +#define UHCI_ALWAYS_SEND_NUM_M (UHCI_ALWAYS_SEND_NUM_V << UHCI_ALWAYS_SEND_NUM_S) +#define UHCI_ALWAYS_SEND_NUM_V 0x00000007U +#define UHCI_ALWAYS_SEND_NUM_S 4 +/** UHCI_ALWAYS_SEND_EN : R/W; bitpos: [7]; default: 0; + * a + */ +#define UHCI_ALWAYS_SEND_EN (BIT(7)) +#define UHCI_ALWAYS_SEND_EN_M (UHCI_ALWAYS_SEND_EN_V << UHCI_ALWAYS_SEND_EN_S) +#define UHCI_ALWAYS_SEND_EN_V 0x00000001U +#define UHCI_ALWAYS_SEND_EN_S 7 + +/** UHCI_REG_Q0_WORD0_REG register + * a + */ +#define UHCI_REG_Q0_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x34) +/** UHCI_SEND_Q0_WORD0 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q0_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD0_M (UHCI_SEND_Q0_WORD0_V << UHCI_SEND_Q0_WORD0_S) +#define UHCI_SEND_Q0_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD0_S 0 + +/** UHCI_REG_Q0_WORD1_REG register + * a + */ +#define UHCI_REG_Q0_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x38) +/** UHCI_SEND_Q0_WORD1 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q0_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD1_M (UHCI_SEND_Q0_WORD1_V << UHCI_SEND_Q0_WORD1_S) +#define UHCI_SEND_Q0_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD1_S 0 + +/** UHCI_REG_Q1_WORD0_REG register + * a + */ +#define UHCI_REG_Q1_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x3c) +/** UHCI_SEND_Q1_WORD0 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q1_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD0_M (UHCI_SEND_Q1_WORD0_V << UHCI_SEND_Q1_WORD0_S) +#define UHCI_SEND_Q1_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD0_S 0 + +/** UHCI_REG_Q1_WORD1_REG register + * a + */ +#define UHCI_REG_Q1_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x40) +/** UHCI_SEND_Q1_WORD1 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q1_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD1_M (UHCI_SEND_Q1_WORD1_V << UHCI_SEND_Q1_WORD1_S) +#define UHCI_SEND_Q1_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD1_S 0 + +/** UHCI_REG_Q2_WORD0_REG register + * a + */ +#define UHCI_REG_Q2_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x44) +/** UHCI_SEND_Q2_WORD0 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q2_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD0_M (UHCI_SEND_Q2_WORD0_V << UHCI_SEND_Q2_WORD0_S) +#define UHCI_SEND_Q2_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD0_S 0 + +/** UHCI_REG_Q2_WORD1_REG register + * a + */ +#define UHCI_REG_Q2_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x48) +/** UHCI_SEND_Q2_WORD1 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q2_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD1_M (UHCI_SEND_Q2_WORD1_V << UHCI_SEND_Q2_WORD1_S) +#define UHCI_SEND_Q2_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD1_S 0 + +/** UHCI_REG_Q3_WORD0_REG register + * a + */ +#define UHCI_REG_Q3_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x4c) +/** UHCI_SEND_Q3_WORD0 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q3_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD0_M (UHCI_SEND_Q3_WORD0_V << UHCI_SEND_Q3_WORD0_S) +#define UHCI_SEND_Q3_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD0_S 0 + +/** UHCI_REG_Q3_WORD1_REG register + * a + */ +#define UHCI_REG_Q3_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x50) +/** UHCI_SEND_Q3_WORD1 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q3_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD1_M (UHCI_SEND_Q3_WORD1_V << UHCI_SEND_Q3_WORD1_S) +#define UHCI_SEND_Q3_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD1_S 0 + +/** UHCI_REG_Q4_WORD0_REG register + * a + */ +#define UHCI_REG_Q4_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x54) +/** UHCI_SEND_Q4_WORD0 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q4_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD0_M (UHCI_SEND_Q4_WORD0_V << UHCI_SEND_Q4_WORD0_S) +#define UHCI_SEND_Q4_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD0_S 0 + +/** UHCI_REG_Q4_WORD1_REG register + * a + */ +#define UHCI_REG_Q4_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x58) +/** UHCI_SEND_Q4_WORD1 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q4_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD1_M (UHCI_SEND_Q4_WORD1_V << UHCI_SEND_Q4_WORD1_S) +#define UHCI_SEND_Q4_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD1_S 0 + +/** UHCI_REG_Q5_WORD0_REG register + * a + */ +#define UHCI_REG_Q5_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x5c) +/** UHCI_SEND_Q5_WORD0 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q5_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD0_M (UHCI_SEND_Q5_WORD0_V << UHCI_SEND_Q5_WORD0_S) +#define UHCI_SEND_Q5_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD0_S 0 + +/** UHCI_REG_Q5_WORD1_REG register + * a + */ +#define UHCI_REG_Q5_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x60) +/** UHCI_SEND_Q5_WORD1 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q5_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD1_M (UHCI_SEND_Q5_WORD1_V << UHCI_SEND_Q5_WORD1_S) +#define UHCI_SEND_Q5_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD1_S 0 + +/** UHCI_REG_Q6_WORD0_REG register + * a + */ +#define UHCI_REG_Q6_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x64) +/** UHCI_SEND_Q6_WORD0 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q6_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD0_M (UHCI_SEND_Q6_WORD0_V << UHCI_SEND_Q6_WORD0_S) +#define UHCI_SEND_Q6_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD0_S 0 + +/** UHCI_REG_Q6_WORD1_REG register + * a + */ +#define UHCI_REG_Q6_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x68) +/** UHCI_SEND_Q6_WORD1 : R/W; bitpos: [31:0]; default: 0; + * a + */ +#define UHCI_SEND_Q6_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD1_M (UHCI_SEND_Q6_WORD1_V << UHCI_SEND_Q6_WORD1_S) +#define UHCI_SEND_Q6_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD1_S 0 + +/** UHCI_ESC_CONF0_REG register + * a + */ +#define UHCI_ESC_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x6c) +/** UHCI_SEPER_CHAR : R/W; bitpos: [7:0]; default: 192; + * a + */ +#define UHCI_SEPER_CHAR 0x000000FFU +#define UHCI_SEPER_CHAR_M (UHCI_SEPER_CHAR_V << UHCI_SEPER_CHAR_S) +#define UHCI_SEPER_CHAR_V 0x000000FFU +#define UHCI_SEPER_CHAR_S 0 +/** UHCI_SEPER_ESC_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * a + */ +#define UHCI_SEPER_ESC_CHAR0 0x000000FFU +#define UHCI_SEPER_ESC_CHAR0_M (UHCI_SEPER_ESC_CHAR0_V << UHCI_SEPER_ESC_CHAR0_S) +#define UHCI_SEPER_ESC_CHAR0_V 0x000000FFU +#define UHCI_SEPER_ESC_CHAR0_S 8 +/** UHCI_SEPER_ESC_CHAR1 : R/W; bitpos: [23:16]; default: 220; + * a + */ +#define UHCI_SEPER_ESC_CHAR1 0x000000FFU +#define UHCI_SEPER_ESC_CHAR1_M (UHCI_SEPER_ESC_CHAR1_V << UHCI_SEPER_ESC_CHAR1_S) +#define UHCI_SEPER_ESC_CHAR1_V 0x000000FFU +#define UHCI_SEPER_ESC_CHAR1_S 16 + +/** UHCI_ESC_CONF1_REG register + * a + */ +#define UHCI_ESC_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x70) +/** UHCI_ESC_SEQ0 : R/W; bitpos: [7:0]; default: 219; + * a + */ +#define UHCI_ESC_SEQ0 0x000000FFU +#define UHCI_ESC_SEQ0_M (UHCI_ESC_SEQ0_V << UHCI_ESC_SEQ0_S) +#define UHCI_ESC_SEQ0_V 0x000000FFU +#define UHCI_ESC_SEQ0_S 0 +/** UHCI_ESC_SEQ0_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * a + */ +#define UHCI_ESC_SEQ0_CHAR0 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR0_M (UHCI_ESC_SEQ0_CHAR0_V << UHCI_ESC_SEQ0_CHAR0_S) +#define UHCI_ESC_SEQ0_CHAR0_V 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR0_S 8 +/** UHCI_ESC_SEQ0_CHAR1 : R/W; bitpos: [23:16]; default: 221; + * a + */ +#define UHCI_ESC_SEQ0_CHAR1 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR1_M (UHCI_ESC_SEQ0_CHAR1_V << UHCI_ESC_SEQ0_CHAR1_S) +#define UHCI_ESC_SEQ0_CHAR1_V 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR1_S 16 + +/** UHCI_ESC_CONF2_REG register + * a + */ +#define UHCI_ESC_CONF2_REG(i) (REG_UHCI_BASE(i) + 0x74) +/** UHCI_ESC_SEQ1 : R/W; bitpos: [7:0]; default: 17; + * a + */ +#define UHCI_ESC_SEQ1 0x000000FFU +#define UHCI_ESC_SEQ1_M (UHCI_ESC_SEQ1_V << UHCI_ESC_SEQ1_S) +#define UHCI_ESC_SEQ1_V 0x000000FFU +#define UHCI_ESC_SEQ1_S 0 +/** UHCI_ESC_SEQ1_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * a + */ +#define UHCI_ESC_SEQ1_CHAR0 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR0_M (UHCI_ESC_SEQ1_CHAR0_V << UHCI_ESC_SEQ1_CHAR0_S) +#define UHCI_ESC_SEQ1_CHAR0_V 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR0_S 8 +/** UHCI_ESC_SEQ1_CHAR1 : R/W; bitpos: [23:16]; default: 222; + * a + */ +#define UHCI_ESC_SEQ1_CHAR1 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR1_M (UHCI_ESC_SEQ1_CHAR1_V << UHCI_ESC_SEQ1_CHAR1_S) +#define UHCI_ESC_SEQ1_CHAR1_V 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR1_S 16 + +/** UHCI_ESC_CONF3_REG register + * a + */ +#define UHCI_ESC_CONF3_REG(i) (REG_UHCI_BASE(i) + 0x78) +/** UHCI_ESC_SEQ2 : R/W; bitpos: [7:0]; default: 19; + * a + */ +#define UHCI_ESC_SEQ2 0x000000FFU +#define UHCI_ESC_SEQ2_M (UHCI_ESC_SEQ2_V << UHCI_ESC_SEQ2_S) +#define UHCI_ESC_SEQ2_V 0x000000FFU +#define UHCI_ESC_SEQ2_S 0 +/** UHCI_ESC_SEQ2_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * a + */ +#define UHCI_ESC_SEQ2_CHAR0 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR0_M (UHCI_ESC_SEQ2_CHAR0_V << UHCI_ESC_SEQ2_CHAR0_S) +#define UHCI_ESC_SEQ2_CHAR0_V 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR0_S 8 +/** UHCI_ESC_SEQ2_CHAR1 : R/W; bitpos: [23:16]; default: 223; + * a + */ +#define UHCI_ESC_SEQ2_CHAR1 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR1_M (UHCI_ESC_SEQ2_CHAR1_V << UHCI_ESC_SEQ2_CHAR1_S) +#define UHCI_ESC_SEQ2_CHAR1_V 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR1_S 16 + +/** UHCI_PKT_THRES_REG register + * a + */ +#define UHCI_PKT_THRES_REG(i) (REG_UHCI_BASE(i) + 0x7c) +/** UHCI_PKT_THRS : R/W; bitpos: [12:0]; default: 128; + * a + */ +#define UHCI_PKT_THRS 0x00001FFFU +#define UHCI_PKT_THRS_M (UHCI_PKT_THRS_V << UHCI_PKT_THRS_S) +#define UHCI_PKT_THRS_V 0x00001FFFU +#define UHCI_PKT_THRS_S 0 + +/** UHCI_DATE_REG register + * a + */ +#define UHCI_DATE_REG(i) (REG_UHCI_BASE(i) + 0x80) +/** UHCI_DATE : R/W; bitpos: [31:0]; default: 35655936; + * a + */ +#define UHCI_DATE 0xFFFFFFFFU +#define UHCI_DATE_M (UHCI_DATE_V << UHCI_DATE_S) +#define UHCI_DATE_V 0xFFFFFFFFU +#define UHCI_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/uhci_struct.h b/components/soc/esp32c6/include/soc/uhci_struct.h new file mode 100644 index 0000000000..29a488af67 --- /dev/null +++ b/components/soc/esp32c6/include/soc/uhci_struct.h @@ -0,0 +1,655 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of conf0 register + * a + */ +typedef union { + struct { + /** tx_rst : R/W; bitpos: [0]; default: 0; + * Write 1 then write 0 to this bit to reset decode state machine. + */ + uint32_t tx_rst:1; + /** rx_rst : R/W; bitpos: [1]; default: 0; + * Write 1 then write 0 to this bit to reset encode state machine. + */ + uint32_t rx_rst:1; + /** uart0_ce : R/W; bitpos: [2]; default: 0; + * Set this bit to link up HCI and UART0. + */ + uint32_t uart0_ce:1; + /** uart1_ce : R/W; bitpos: [3]; default: 0; + * Set this bit to link up HCI and UART1. + */ + uint32_t uart1_ce:1; + uint32_t reserved_4:1; + /** seper_en : R/W; bitpos: [5]; default: 1; + * Set this bit to separate the data frame using a special char. + */ + uint32_t seper_en:1; + /** head_en : R/W; bitpos: [6]; default: 1; + * Set this bit to encode the data packet with a formatting header. + */ + uint32_t head_en:1; + /** crc_rec_en : R/W; bitpos: [7]; default: 1; + * Set this bit to enable UHCI to receive the 16 bit CRC. + */ + uint32_t crc_rec_en:1; + /** uart_idle_eof_en : R/W; bitpos: [8]; default: 0; + * If this bit is set to 1 UHCI will end the payload receiving process when UART has + * been in idle state. + */ + uint32_t uart_idle_eof_en:1; + /** len_eof_en : R/W; bitpos: [9]; default: 1; + * If this bit is set to 1 UHCI decoder receiving payload data is end when the + * receiving byte count has reached the specified value. The value is payload length + * indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is + * configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder + * receiving payload data is end when 0xc0 is received. + */ + uint32_t len_eof_en:1; + /** encode_crc_en : R/W; bitpos: [10]; default: 1; + * Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to + * end of the payload. + */ + uint32_t encode_crc_en:1; + /** clk_en : R/W; bitpos: [11]; default: 0; + * 1'b1: Force clock on for register. 1'b0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + /** uart_rx_brk_eof_en : R/W; bitpos: [12]; default: 0; + * If this bit is set to 1 UHCI will end payload receive process when NULL frame is + * received by UART. + */ + uint32_t uart_rx_brk_eof_en:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} uhci_conf0_reg_t; + +/** Type of conf1 register + * a + */ +typedef union { + struct { + /** check_sum_en : R/W; bitpos: [0]; default: 1; + * a + */ + uint32_t check_sum_en:1; + /** check_seq_en : R/W; bitpos: [1]; default: 1; + * a + */ + uint32_t check_seq_en:1; + /** crc_disable : R/W; bitpos: [2]; default: 0; + * a + */ + uint32_t crc_disable:1; + /** save_head : R/W; bitpos: [3]; default: 0; + * a + */ + uint32_t save_head:1; + /** tx_check_sum_re : R/W; bitpos: [4]; default: 1; + * a + */ + uint32_t tx_check_sum_re:1; + /** tx_ack_num_re : R/W; bitpos: [5]; default: 1; + * a + */ + uint32_t tx_ack_num_re:1; + uint32_t reserved_6:1; + /** wait_sw_start : R/W; bitpos: [7]; default: 0; + * a + */ + uint32_t wait_sw_start:1; + /** sw_start : WT; bitpos: [8]; default: 0; + * a + */ + uint32_t sw_start:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_conf1_reg_t; + +/** Type of escape_conf register + * a + */ +typedef union { + struct { + /** tx_c0_esc_en : R/W; bitpos: [0]; default: 1; + * a + */ + uint32_t tx_c0_esc_en:1; + /** tx_db_esc_en : R/W; bitpos: [1]; default: 1; + * a + */ + uint32_t tx_db_esc_en:1; + /** tx_11_esc_en : R/W; bitpos: [2]; default: 0; + * a + */ + uint32_t tx_11_esc_en:1; + /** tx_13_esc_en : R/W; bitpos: [3]; default: 0; + * a + */ + uint32_t tx_13_esc_en:1; + /** rx_c0_esc_en : R/W; bitpos: [4]; default: 1; + * a + */ + uint32_t rx_c0_esc_en:1; + /** rx_db_esc_en : R/W; bitpos: [5]; default: 1; + * a + */ + uint32_t rx_db_esc_en:1; + /** rx_11_esc_en : R/W; bitpos: [6]; default: 0; + * a + */ + uint32_t rx_11_esc_en:1; + /** rx_13_esc_en : R/W; bitpos: [7]; default: 0; + * a + */ + uint32_t rx_13_esc_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} uhci_escape_conf_reg_t; + +/** Type of hung_conf register + * a + */ +typedef union { + struct { + /** txfifo_timeout : R/W; bitpos: [7:0]; default: 16; + * a + */ + uint32_t txfifo_timeout:8; + /** txfifo_timeout_shift : R/W; bitpos: [10:8]; default: 0; + * a + */ + uint32_t txfifo_timeout_shift:3; + /** txfifo_timeout_ena : R/W; bitpos: [11]; default: 1; + * a + */ + uint32_t txfifo_timeout_ena:1; + /** rxfifo_timeout : R/W; bitpos: [19:12]; default: 16; + * a + */ + uint32_t rxfifo_timeout:8; + /** rxfifo_timeout_shift : R/W; bitpos: [22:20]; default: 0; + * a + */ + uint32_t rxfifo_timeout_shift:3; + /** rxfifo_timeout_ena : R/W; bitpos: [23]; default: 1; + * a + */ + uint32_t rxfifo_timeout_ena:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_hung_conf_reg_t; + +/** Type of ack_num register + * a + */ +typedef union { + struct { + /** ack_num : R/W; bitpos: [2:0]; default: 0; + * a + */ + uint32_t ack_num:3; + /** ack_num_load : WT; bitpos: [3]; default: 0; + * a + */ + uint32_t ack_num_load:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} uhci_ack_num_reg_t; + +/** Type of quick_sent register + * a + */ +typedef union { + struct { + /** single_send_num : R/W; bitpos: [2:0]; default: 0; + * a + */ + uint32_t single_send_num:3; + /** single_send_en : WT; bitpos: [3]; default: 0; + * a + */ + uint32_t single_send_en:1; + /** always_send_num : R/W; bitpos: [6:4]; default: 0; + * a + */ + uint32_t always_send_num:3; + /** always_send_en : R/W; bitpos: [7]; default: 0; + * a + */ + uint32_t always_send_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} uhci_quick_sent_reg_t; + +/** Type of reg_qn_word0 register + * a + */ +typedef union { + struct { + /** send_word0 : R/W; bitpos: [31:0]; default: 0; + * a + */ + uint32_t send_word0:32; + }; + uint32_t val; +} uhci_reg_qn_word0_reg_t; + +/** Type of reg_qn_word1 register + * a + */ +typedef union { + struct { + /** send_word1 : R/W; bitpos: [31:0]; default: 0; + * a + */ + uint32_t send_word1:32; + }; + uint32_t val; +} uhci_reg_qn_word1_reg_t; + +/** Type of esc_conf0 register + * a + */ +typedef union { + struct { + /** seper_char : R/W; bitpos: [7:0]; default: 192; + * a + */ + uint32_t seper_char:8; + /** seper_esc_char0 : R/W; bitpos: [15:8]; default: 219; + * a + */ + uint32_t seper_esc_char0:8; + /** seper_esc_char1 : R/W; bitpos: [23:16]; default: 220; + * a + */ + uint32_t seper_esc_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf0_reg_t; + +/** Type of esc_conf1 register + * a + */ +typedef union { + struct { + /** esc_seq0 : R/W; bitpos: [7:0]; default: 219; + * a + */ + uint32_t esc_seq0:8; + /** esc_seq0_char0 : R/W; bitpos: [15:8]; default: 219; + * a + */ + uint32_t esc_seq0_char0:8; + /** esc_seq0_char1 : R/W; bitpos: [23:16]; default: 221; + * a + */ + uint32_t esc_seq0_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf1_reg_t; + +/** Type of esc_conf2 register + * a + */ +typedef union { + struct { + /** esc_seq1 : R/W; bitpos: [7:0]; default: 17; + * a + */ + uint32_t esc_seq1:8; + /** esc_seq1_char0 : R/W; bitpos: [15:8]; default: 219; + * a + */ + uint32_t esc_seq1_char0:8; + /** esc_seq1_char1 : R/W; bitpos: [23:16]; default: 222; + * a + */ + uint32_t esc_seq1_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf2_reg_t; + +/** Type of esc_conf3 register + * a + */ +typedef union { + struct { + /** esc_seq2 : R/W; bitpos: [7:0]; default: 19; + * a + */ + uint32_t esc_seq2:8; + /** esc_seq2_char0 : R/W; bitpos: [15:8]; default: 219; + * a + */ + uint32_t esc_seq2_char0:8; + /** esc_seq2_char1 : R/W; bitpos: [23:16]; default: 223; + * a + */ + uint32_t esc_seq2_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf3_reg_t; + +/** Type of pkt_thres register + * a + */ +typedef union { + struct { + /** pkt_thrs : R/W; bitpos: [12:0]; default: 128; + * a + */ + uint32_t pkt_thrs:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} uhci_pkt_thres_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * a + */ +typedef union { + struct { + /** rx_start_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * a + */ + uint32_t rx_start_int_raw:1; + /** tx_start_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * a + */ + uint32_t tx_start_int_raw:1; + /** rx_hung_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * a + */ + uint32_t rx_hung_int_raw:1; + /** tx_hung_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * a + */ + uint32_t tx_hung_int_raw:1; + /** send_s_reg_q_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * a + */ + uint32_t send_s_reg_q_int_raw:1; + /** send_a_reg_q_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * a + */ + uint32_t send_a_reg_q_int_raw:1; + /** out_eof_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * This is the interrupt raw bit. Triggered when there are some errors in EOF in the + */ + uint32_t out_eof_int_raw:1; + /** app_ctrl0_int_raw : R/W; bitpos: [7]; default: 0; + * Soft control int raw bit. + */ + uint32_t app_ctrl0_int_raw:1; + /** app_ctrl1_int_raw : R/W; bitpos: [8]; default: 0; + * Soft control int raw bit. + */ + uint32_t app_ctrl1_int_raw:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_raw_reg_t; + +/** Type of int_st register + * a + */ +typedef union { + struct { + /** rx_start_int_st : RO; bitpos: [0]; default: 0; + * a + */ + uint32_t rx_start_int_st:1; + /** tx_start_int_st : RO; bitpos: [1]; default: 0; + * a + */ + uint32_t tx_start_int_st:1; + /** rx_hung_int_st : RO; bitpos: [2]; default: 0; + * a + */ + uint32_t rx_hung_int_st:1; + /** tx_hung_int_st : RO; bitpos: [3]; default: 0; + * a + */ + uint32_t tx_hung_int_st:1; + /** send_s_reg_q_int_st : RO; bitpos: [4]; default: 0; + * a + */ + uint32_t send_s_reg_q_int_st:1; + /** send_a_reg_q_int_st : RO; bitpos: [5]; default: 0; + * a + */ + uint32_t send_a_reg_q_int_st:1; + /** outlink_eof_err_int_st : RO; bitpos: [6]; default: 0; + * a + */ + uint32_t outlink_eof_err_int_st:1; + /** app_ctrl0_int_st : RO; bitpos: [7]; default: 0; + * a + */ + uint32_t app_ctrl0_int_st:1; + /** app_ctrl1_int_st : RO; bitpos: [8]; default: 0; + * a + */ + uint32_t app_ctrl1_int_st:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_st_reg_t; + +/** Type of int_ena register + * a + */ +typedef union { + struct { + /** rx_start_int_ena : R/W; bitpos: [0]; default: 0; + * a + */ + uint32_t rx_start_int_ena:1; + /** tx_start_int_ena : R/W; bitpos: [1]; default: 0; + * a + */ + uint32_t tx_start_int_ena:1; + /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0; + * a + */ + uint32_t rx_hung_int_ena:1; + /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0; + * a + */ + uint32_t tx_hung_int_ena:1; + /** send_s_reg_q_int_ena : R/W; bitpos: [4]; default: 0; + * a + */ + uint32_t send_s_reg_q_int_ena:1; + /** send_a_reg_q_int_ena : R/W; bitpos: [5]; default: 0; + * a + */ + uint32_t send_a_reg_q_int_ena:1; + /** outlink_eof_err_int_ena : R/W; bitpos: [6]; default: 0; + * a + */ + uint32_t outlink_eof_err_int_ena:1; + /** app_ctrl0_int_ena : R/W; bitpos: [7]; default: 0; + * a + */ + uint32_t app_ctrl0_int_ena:1; + /** app_ctrl1_int_ena : R/W; bitpos: [8]; default: 0; + * a + */ + uint32_t app_ctrl1_int_ena:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_ena_reg_t; + +/** Type of int_clr register + * a + */ +typedef union { + struct { + /** rx_start_int_clr : WT; bitpos: [0]; default: 0; + * a + */ + uint32_t rx_start_int_clr:1; + /** tx_start_int_clr : WT; bitpos: [1]; default: 0; + * a + */ + uint32_t tx_start_int_clr:1; + /** rx_hung_int_clr : WT; bitpos: [2]; default: 0; + * a + */ + uint32_t rx_hung_int_clr:1; + /** tx_hung_int_clr : WT; bitpos: [3]; default: 0; + * a + */ + uint32_t tx_hung_int_clr:1; + /** send_s_reg_q_int_clr : WT; bitpos: [4]; default: 0; + * a + */ + uint32_t send_s_reg_q_int_clr:1; + /** send_a_reg_q_int_clr : WT; bitpos: [5]; default: 0; + * a + */ + uint32_t send_a_reg_q_int_clr:1; + /** outlink_eof_err_int_clr : WT; bitpos: [6]; default: 0; + * a + */ + uint32_t outlink_eof_err_int_clr:1; + /** app_ctrl0_int_clr : WT; bitpos: [7]; default: 0; + * a + */ + uint32_t app_ctrl0_int_clr:1; + /** app_ctrl1_int_clr : WT; bitpos: [8]; default: 0; + * a + */ + uint32_t app_ctrl1_int_clr:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_clr_reg_t; + + +/** Group: UHCI Status Register */ +/** Type of state0 register + * a + */ +typedef union { + struct { + /** rx_err_cause : RO; bitpos: [2:0]; default: 0; + * a + */ + uint32_t rx_err_cause:3; + /** decode_state : RO; bitpos: [5:3]; default: 0; + * a + */ + uint32_t decode_state:3; + uint32_t reserved_6:26; + }; + uint32_t val; +} uhci_state0_reg_t; + +/** Type of state1 register + * a + */ +typedef union { + struct { + /** encode_state : RO; bitpos: [2:0]; default: 0; + * a + */ + uint32_t encode_state:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} uhci_state1_reg_t; + +/** Type of rx_head register + * a + */ +typedef union { + struct { + /** rx_head : RO; bitpos: [31:0]; default: 0; + * a + */ + uint32_t rx_head:32; + }; + uint32_t val; +} uhci_rx_head_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * a + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35655936; + * a + */ + uint32_t date:32; + }; + uint32_t val; +} uhci_date_reg_t; + + +typedef struct uhci_dev_s { + volatile uhci_conf0_reg_t conf0; + volatile uhci_int_raw_reg_t int_raw; + volatile uhci_int_st_reg_t int_st; + volatile uhci_int_ena_reg_t int_ena; + volatile uhci_int_clr_reg_t int_clr; + volatile uhci_conf1_reg_t conf1; + volatile uhci_state0_reg_t state0; + volatile uhci_state1_reg_t state1; + volatile uhci_escape_conf_reg_t escape_conf; + volatile uhci_hung_conf_reg_t hung_conf; + volatile uhci_ack_num_reg_t ack_num; + volatile uhci_rx_head_reg_t rx_head; + volatile uhci_quick_sent_reg_t quick_sent; + volatile struct { + uhci_reg_qn_word0_reg_t word0; + uhci_reg_qn_word1_reg_t word1; + } q_data[7]; + volatile uhci_esc_conf0_reg_t esc_conf0; + volatile uhci_esc_conf1_reg_t esc_conf1; + volatile uhci_esc_conf2_reg_t esc_conf2; + volatile uhci_esc_conf3_reg_t esc_conf3; + volatile uhci_pkt_thres_reg_t pkt_thres; + volatile uhci_date_reg_t date; +} uhci_dev_t; + +extern uhci_dev_t UHCI0; + +#ifndef __cplusplus +_Static_assert(sizeof(uhci_dev_t) == 0x84, "Invalid size of uhci_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32c6/include/soc/usb_serial_jtag_reg.h new file mode 100644 index 0000000000..eb4b8a1e03 --- /dev/null +++ b/components/soc/esp32c6/include/soc/usb_serial_jtag_reg.h @@ -0,0 +1,1188 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** USB_SERIAL_JTAG_EP1_REG register + * FIFO access for the CDC-ACM data IN and OUT endpoints. + */ +#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0) +/** USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [7:0]; default: 0; + * Write and read byte data to/from UART Tx/Rx FIFO through this field. When + * USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 + * bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user + * can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know + * how many data is received, then read data from UART Rx FIFO. + */ +#define USB_SERIAL_JTAG_RDWR_BYTE 0x000000FFU +#define USB_SERIAL_JTAG_RDWR_BYTE_M (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S) +#define USB_SERIAL_JTAG_RDWR_BYTE_V 0x000000FFU +#define USB_SERIAL_JTAG_RDWR_BYTE_S 0 + +/** USB_SERIAL_JTAG_EP1_CONF_REG register + * Configuration and control registers for the CDC-ACM FIFOs. + */ +#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4) +/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0; + * Set this bit to indicate writing byte data to UART Tx FIFO is done. + */ +#define USB_SERIAL_JTAG_WR_DONE (BIT(0)) +#define USB_SERIAL_JTAG_WR_DONE_M (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S) +#define USB_SERIAL_JTAG_WR_DONE_V 0x00000001U +#define USB_SERIAL_JTAG_WR_DONE_S 0 +/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1; + * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing + * USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by + * USB Host. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1)) +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0; + * 1'b1: Indicate there is data in UART Rx FIFO. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2 + +/** USB_SERIAL_JTAG_INT_RAW_REG register + * Interrupt raw status register. + */ +#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when flush cmd is received for IN + * endpoint 2 of JTAG. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0 +/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when SOF frame is received. + */ +#define USB_SERIAL_JTAG_SOF_INT_RAW (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_RAW_M (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S) +#define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_RAW_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when Serial Port OUT Endpoint received + * one packet. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1; + * The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when pid error is detected. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when CRC5 error is detected. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when CRC16 error is detected. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when stuff error is detected. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when IN token for IN endpoint 1 is + * received. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when usb bus reset is detected. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 1 received packet with + * zero palyload. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 2 received packet with + * zero palyload. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit turns to high level when level of RTS from usb serial channel + * is changed. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit turns to high level when level of DTR from usb serial channel + * is changed. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit turns to high level when level of GET LINE CODING request is + * received. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit turns to high level when level of SET LINE CODING request is + * received. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S 15 + +/** USB_SERIAL_JTAG_INT_ST_REG register + * Interrupt status register. + */ +#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0 +/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_ST_M (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S) +#define USB_SERIAL_JTAG_SOF_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_ST_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S 15 + +/** USB_SERIAL_JTAG_INT_ENA_REG register + * Interrupt enable status register. + */ +#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0 +/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_ENA_M (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S) +#define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_ENA_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S 15 + +/** USB_SERIAL_JTAG_INT_CLR_REG register + * Interrupt clear status register. + */ +#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0 +/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_CLR_M (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S) +#define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_CLR_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S 15 + +/** USB_SERIAL_JTAG_CONF0_REG register + * PHY hardware configuration. + */ +#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18) +/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; + * Select internal/external PHY + */ +#define USB_SERIAL_JTAG_PHY_SEL (BIT(0)) +#define USB_SERIAL_JTAG_PHY_SEL_M (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S) +#define USB_SERIAL_JTAG_PHY_SEL_V 0x00000001U +#define USB_SERIAL_JTAG_PHY_SEL_S 0 +/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0; + * Enable software control USB D+ D- exchange + */ +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1)) +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S) +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1 +/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0; + * USB D+ D- exchange + */ +#define USB_SERIAL_JTAG_EXCHG_PINS (BIT(2)) +#define USB_SERIAL_JTAG_EXCHG_PINS_M (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S) +#define USB_SERIAL_JTAG_EXCHG_PINS_V 0x00000001U +#define USB_SERIAL_JTAG_EXCHG_PINS_S 2 +/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0; + * Control single-end input high threshold,1.76V to 2V, step 80mV + */ +#define USB_SERIAL_JTAG_VREFH 0x00000003U +#define USB_SERIAL_JTAG_VREFH_M (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S) +#define USB_SERIAL_JTAG_VREFH_V 0x00000003U +#define USB_SERIAL_JTAG_VREFH_S 3 +/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0; + * Control single-end input low threshold,0.8V to 1.04V, step 80mV + */ +#define USB_SERIAL_JTAG_VREFL 0x00000003U +#define USB_SERIAL_JTAG_VREFL_M (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S) +#define USB_SERIAL_JTAG_VREFL_V 0x00000003U +#define USB_SERIAL_JTAG_VREFL_S 5 +/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0; + * Enable software control input threshold + */ +#define USB_SERIAL_JTAG_VREF_OVERRIDE (BIT(7)) +#define USB_SERIAL_JTAG_VREF_OVERRIDE_M (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S) +#define USB_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_VREF_OVERRIDE_S 7 +/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0; + * Enable software control USB D+ D- pullup pulldown + */ +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8)) +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S) +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8 +/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1; + * Control USB D+ pull up. + */ +#define USB_SERIAL_JTAG_DP_PULLUP (BIT(9)) +#define USB_SERIAL_JTAG_DP_PULLUP_M (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S) +#define USB_SERIAL_JTAG_DP_PULLUP_V 0x00000001U +#define USB_SERIAL_JTAG_DP_PULLUP_S 9 +/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0; + * Control USB D+ pull down. + */ +#define USB_SERIAL_JTAG_DP_PULLDOWN (BIT(10)) +#define USB_SERIAL_JTAG_DP_PULLDOWN_M (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S) +#define USB_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001U +#define USB_SERIAL_JTAG_DP_PULLDOWN_S 10 +/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0; + * Control USB D- pull up. + */ +#define USB_SERIAL_JTAG_DM_PULLUP (BIT(11)) +#define USB_SERIAL_JTAG_DM_PULLUP_M (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S) +#define USB_SERIAL_JTAG_DM_PULLUP_V 0x00000001U +#define USB_SERIAL_JTAG_DM_PULLUP_S 11 +/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0; + * Control USB D- pull down. + */ +#define USB_SERIAL_JTAG_DM_PULLDOWN (BIT(12)) +#define USB_SERIAL_JTAG_DM_PULLDOWN_M (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S) +#define USB_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001U +#define USB_SERIAL_JTAG_DM_PULLDOWN_S 12 +/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0; + * Control pull up value. + */ +#define USB_SERIAL_JTAG_PULLUP_VALUE (BIT(13)) +#define USB_SERIAL_JTAG_PULLUP_VALUE_M (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S) +#define USB_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001U +#define USB_SERIAL_JTAG_PULLUP_VALUE_S 13 +/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1; + * Enable USB pad function. + */ +#define USB_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14)) +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S) +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001U +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14 +/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0; + * Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is + * disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input + * through GPIO Matrix. + */ +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN (BIT(15)) +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S) +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x00000001U +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 15 + +/** USB_SERIAL_JTAG_TEST_REG register + * Registers used for debugging the PHY. + */ +#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c) +/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0; + * Enable test of the USB pad + */ +#define USB_SERIAL_JTAG_TEST_ENABLE (BIT(0)) +#define USB_SERIAL_JTAG_TEST_ENABLE_M (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S) +#define USB_SERIAL_JTAG_TEST_ENABLE_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_ENABLE_S 0 +/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0; + * USB pad oen in test + */ +#define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1)) +#define USB_SERIAL_JTAG_TEST_USB_OE_M (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S) +#define USB_SERIAL_JTAG_TEST_USB_OE_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_USB_OE_S 1 +/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0; + * USB D+ tx value in test + */ +#define USB_SERIAL_JTAG_TEST_TX_DP (BIT(2)) +#define USB_SERIAL_JTAG_TEST_TX_DP_M (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S) +#define USB_SERIAL_JTAG_TEST_TX_DP_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_TX_DP_S 2 +/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0; + * USB D- tx value in test + */ +#define USB_SERIAL_JTAG_TEST_TX_DM (BIT(3)) +#define USB_SERIAL_JTAG_TEST_TX_DM_M (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S) +#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_TX_DM_S 3 +/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1; + * USB RCV value in test + */ +#define USB_SERIAL_JTAG_TEST_RX_RCV (BIT(4)) +#define USB_SERIAL_JTAG_TEST_RX_RCV_M (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S) +#define USB_SERIAL_JTAG_TEST_RX_RCV_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_RCV_S 4 +/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1; + * USB D+ rx value in test + */ +#define USB_SERIAL_JTAG_TEST_RX_DP (BIT(5)) +#define USB_SERIAL_JTAG_TEST_RX_DP_M (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S) +#define USB_SERIAL_JTAG_TEST_RX_DP_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_DP_S 5 +/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0; + * USB D- rx value in test + */ +#define USB_SERIAL_JTAG_TEST_RX_DM (BIT(6)) +#define USB_SERIAL_JTAG_TEST_RX_DM_M (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S) +#define USB_SERIAL_JTAG_TEST_RX_DM_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_DM_S 6 + +/** USB_SERIAL_JTAG_JFIFO_ST_REG register + * JTAG FIFO status and control registers. + */ +#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20) +/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0; + * JTAT in fifo counter. + */ +#define USB_SERIAL_JTAG_IN_FIFO_CNT 0x00000003U +#define USB_SERIAL_JTAG_IN_FIFO_CNT_M (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S) +#define USB_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003U +#define USB_SERIAL_JTAG_IN_FIFO_CNT_S 0 +/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1; + * 1: JTAG in fifo is empty. + */ +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2)) +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S) +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S 2 +/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0; + * 1: JTAG in fifo is full. + */ +#define USB_SERIAL_JTAG_IN_FIFO_FULL (BIT(3)) +#define USB_SERIAL_JTAG_IN_FIFO_FULL_M (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S) +#define USB_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_FULL_S 3 +/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0; + * JTAT out fifo counter. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003U +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S) +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S 4 +/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1; + * 1: JTAG out fifo is empty. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6)) +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S) +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6 +/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0; + * 1: JTAG out fifo is full. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7)) +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S) +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S 7 +/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0; + * Write 1 to reset JTAG in fifo. + */ +#define USB_SERIAL_JTAG_IN_FIFO_RESET (BIT(8)) +#define USB_SERIAL_JTAG_IN_FIFO_RESET_M (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S) +#define USB_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_RESET_S 8 +/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0; + * Write 1 to reset JTAG out fifo. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9)) +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S) +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9 + +/** USB_SERIAL_JTAG_FRAM_NUM_REG register + * Last received SOF frame index register. + */ +#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24) +/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0; + * Frame index of received SOF frame. + */ +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FFU +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S) +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007FFU +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0 + +/** USB_SERIAL_JTAG_IN_EP0_ST_REG register + * Control IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28) +/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP0_STATE_M (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S) +#define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP0_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP1_ST_REG register + * CDC-ACM IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c) +/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP1_STATE_M (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S) +#define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP1_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP2_ST_REG register + * CDC-ACM interrupt IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30) +/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP2_STATE_M (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S) +#define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP2_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP3_ST_REG register + * JTAG IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34) +/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP3_STATE_M (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S) +#define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP3_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register + * Control OUT endpoint status information. + */ +#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38) +/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP0_STATE_M (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register + * CDC-ACM OUT endpoint status information. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c) +/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP1_STATE_M (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0; + * Data count in OUT endpoint 1 when one packet is received. + */ +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S) +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16 + +/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register + * JTAG OUT endpoint status information. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40) +/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP2_STATE_M (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_MISC_CONF_REG register + * Clock enable control + */ +#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44) +/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define USB_SERIAL_JTAG_CLK_EN (BIT(0)) +#define USB_SERIAL_JTAG_CLK_EN_M (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S) +#define USB_SERIAL_JTAG_CLK_EN_V 0x00000001U +#define USB_SERIAL_JTAG_CLK_EN_S 0 + +/** USB_SERIAL_JTAG_MEM_CONF_REG register + * Memory power control + */ +#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48) +/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0; + * 1: power down usb memory. + */ +#define USB_SERIAL_JTAG_USB_MEM_PD (BIT(0)) +#define USB_SERIAL_JTAG_USB_MEM_PD_M (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S) +#define USB_SERIAL_JTAG_USB_MEM_PD_V 0x00000001U +#define USB_SERIAL_JTAG_USB_MEM_PD_S 0 +/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1; + * 1: Force clock on for usb memory. + */ +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1)) +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S) +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001U +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1 + +/** USB_SERIAL_JTAG_CHIP_RST_REG register + * CDC-ACM chip reset control. + */ +#define USB_SERIAL_JTAG_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c) +/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0; + * 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. + */ +#define USB_SERIAL_JTAG_RTS (BIT(0)) +#define USB_SERIAL_JTAG_RTS_M (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S) +#define USB_SERIAL_JTAG_RTS_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_S 0 +/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0; + * 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. + */ +#define USB_SERIAL_JTAG_DTR (BIT(1)) +#define USB_SERIAL_JTAG_DTR_M (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S) +#define USB_SERIAL_JTAG_DTR_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_S 1 +/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0; + * Set this bit to disable chip reset from usb serial channel to reset chip. + */ +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS (BIT(2)) +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S) +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V 0x00000001U +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S 2 + +/** USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register + * W0 of SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50) +/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_DW_DTE_RATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DW_DTE_RATE_M (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S) +#define USB_SERIAL_JTAG_DW_DTE_RATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DW_DTE_RATE_S 0 + +/** USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG register + * W1 of SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54) +/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_BCHAR_FORMAT 0x000000FFU +#define USB_SERIAL_JTAG_BCHAR_FORMAT_M (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S) +#define USB_SERIAL_JTAG_BCHAR_FORMAT_V 0x000000FFU +#define USB_SERIAL_JTAG_BCHAR_FORMAT_S 0 +/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_BPARITY_TYPE 0x000000FFU +#define USB_SERIAL_JTAG_BPARITY_TYPE_M (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S) +#define USB_SERIAL_JTAG_BPARITY_TYPE_V 0x000000FFU +#define USB_SERIAL_JTAG_BPARITY_TYPE_S 8 +/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0; + * The value of bDataBits set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_BDATA_BITS 0x000000FFU +#define USB_SERIAL_JTAG_BDATA_BITS_M (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S) +#define USB_SERIAL_JTAG_BDATA_BITS_V 0x000000FFU +#define USB_SERIAL_JTAG_BDATA_BITS_S 16 + +/** USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register + * W0 of GET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58) +/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S) +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S 0 + +/** USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG register + * W1 of GET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c) +/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_BDATA_BITS 0x000000FFU +#define USB_SERIAL_JTAG_GET_BDATA_BITS_M (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S) +#define USB_SERIAL_JTAG_GET_BDATA_BITS_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BDATA_BITS_S 0 +/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE 0x000000FFU +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S) +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S 8 +/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0; + * The value of bDataBits set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT 0x000000FFU +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S) +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S 16 + +/** USB_SERIAL_JTAG_CONFIG_UPDATE_REG register + * Configuration registers' value update + */ +#define USB_SERIAL_JTAG_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60) +/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0; + * Write 1 to this register would update the value of configure registers from APB + * clock domain to 48MHz clock domain. + */ +#define USB_SERIAL_JTAG_CONFIG_UPDATE (BIT(0)) +#define USB_SERIAL_JTAG_CONFIG_UPDATE_M (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S) +#define USB_SERIAL_JTAG_CONFIG_UPDATE_V 0x00000001U +#define USB_SERIAL_JTAG_CONFIG_UPDATE_S 0 + +/** USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG register + * Serial AFIFO configure register + */ +#define USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64) +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO write clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR (BIT(0)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S 0 +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO read clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD (BIT(1)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S 2 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S 3 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1; + * CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY (BIT(4)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S 4 +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0; + * CDC_ACM OUT IN async FIFO empty signal in write clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL (BIT(5)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S 5 + +/** USB_SERIAL_JTAG_BUS_RESET_ST_REG register + * USB Bus reset status register + */ +#define USB_SERIAL_JTAG_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68) +/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1; + * USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus + * reset is released. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST (BIT(0)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S 0 + +/** USB_SERIAL_JTAG_DATE_REG register + * Date register + */ +#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80) +/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34640416; + * register version. + */ +#define USB_SERIAL_JTAG_DATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DATE_M (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S) +#define USB_SERIAL_JTAG_DATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32c6/include/soc/usb_serial_jtag_struct.h new file mode 100644 index 0000000000..523b58eda2 --- /dev/null +++ b/components/soc/esp32c6/include/soc/usb_serial_jtag_struct.h @@ -0,0 +1,941 @@ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of ep1 register + * FIFO access for the CDC-ACM data IN and OUT endpoints. + */ +typedef union { + struct { + /** rdwr_byte : R/W; bitpos: [7:0]; default: 0; + * Write and read byte data to/from UART Tx/Rx FIFO through this field. When + * USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 + * bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user + * can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know + * how many data is received, then read data from UART Rx FIFO. + */ + uint32_t rdwr_byte:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} usb_serial_jtag_ep1_reg_t; + +/** Type of ep1_conf register + * Configuration and control registers for the CDC-ACM FIFOs. + */ +typedef union { + struct { + /** wr_done : WT; bitpos: [0]; default: 0; + * Set this bit to indicate writing byte data to UART Tx FIFO is done. + */ + uint32_t wr_done:1; + /** serial_in_ep_data_free : RO; bitpos: [1]; default: 1; + * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing + * USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by + * USB Host. + */ + uint32_t serial_in_ep_data_free:1; + /** serial_out_ep_data_avail : RO; bitpos: [2]; default: 0; + * 1'b1: Indicate there is data in UART Rx FIFO. + */ + uint32_t serial_out_ep_data_avail:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} usb_serial_jtag_ep1_conf_reg_t; + +/** Type of conf0 register + * PHY hardware configuration. + */ +typedef union { + struct { + /** phy_sel : R/W; bitpos: [0]; default: 0; + * Select internal/external PHY + */ + uint32_t phy_sel:1; + /** exchg_pins_override : R/W; bitpos: [1]; default: 0; + * Enable software control USB D+ D- exchange + */ + uint32_t exchg_pins_override:1; + /** exchg_pins : R/W; bitpos: [2]; default: 0; + * USB D+ D- exchange + */ + uint32_t exchg_pins:1; + /** vrefh : R/W; bitpos: [4:3]; default: 0; + * Control single-end input high threshold,1.76V to 2V, step 80mV + */ + uint32_t vrefh:2; + /** vrefl : R/W; bitpos: [6:5]; default: 0; + * Control single-end input low threshold,0.8V to 1.04V, step 80mV + */ + uint32_t vrefl:2; + /** vref_override : R/W; bitpos: [7]; default: 0; + * Enable software control input threshold + */ + uint32_t vref_override:1; + /** pad_pull_override : R/W; bitpos: [8]; default: 0; + * Enable software control USB D+ D- pullup pulldown + */ + uint32_t pad_pull_override:1; + /** dp_pullup : R/W; bitpos: [9]; default: 1; + * Control USB D+ pull up. + */ + uint32_t dp_pullup:1; + /** dp_pulldown : R/W; bitpos: [10]; default: 0; + * Control USB D+ pull down. + */ + uint32_t dp_pulldown:1; + /** dm_pullup : R/W; bitpos: [11]; default: 0; + * Control USB D- pull up. + */ + uint32_t dm_pullup:1; + /** dm_pulldown : R/W; bitpos: [12]; default: 0; + * Control USB D- pull down. + */ + uint32_t dm_pulldown:1; + /** pullup_value : R/W; bitpos: [13]; default: 0; + * Control pull up value. + */ + uint32_t pullup_value:1; + /** usb_pad_enable : R/W; bitpos: [14]; default: 1; + * Enable USB pad function. + */ + uint32_t usb_pad_enable:1; + /** usb_jtag_bridge_en : R/W; bitpos: [15]; default: 0; + * Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is + * disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input + * through GPIO Matrix. + */ + uint32_t usb_jtag_bridge_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_conf0_reg_t; + +/** Type of test register + * Registers used for debugging the PHY. + */ +typedef union { + struct { + /** test_enable : R/W; bitpos: [0]; default: 0; + * Enable test of the USB pad + */ + uint32_t test_enable:1; + /** test_usb_oe : R/W; bitpos: [1]; default: 0; + * USB pad oen in test + */ + uint32_t test_usb_oe:1; + /** test_tx_dp : R/W; bitpos: [2]; default: 0; + * USB D+ tx value in test + */ + uint32_t test_tx_dp:1; + /** test_tx_dm : R/W; bitpos: [3]; default: 0; + * USB D- tx value in test + */ + uint32_t test_tx_dm:1; + /** test_rx_rcv : RO; bitpos: [4]; default: 1; + * USB RCV value in test + */ + uint32_t test_rx_rcv:1; + /** test_rx_dp : RO; bitpos: [5]; default: 1; + * USB D+ rx value in test + */ + uint32_t test_rx_dp:1; + /** test_rx_dm : RO; bitpos: [6]; default: 0; + * USB D- rx value in test + */ + uint32_t test_rx_dm:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} usb_serial_jtag_test_reg_t; + +/** Type of misc_conf register + * Clock enable control + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_misc_conf_reg_t; + +/** Type of mem_conf register + * Memory power control + */ +typedef union { + struct { + /** usb_mem_pd : R/W; bitpos: [0]; default: 0; + * 1: power down usb memory. + */ + uint32_t usb_mem_pd:1; + /** usb_mem_clk_en : R/W; bitpos: [1]; default: 1; + * 1: Force clock on for usb memory. + */ + uint32_t usb_mem_clk_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} usb_serial_jtag_mem_conf_reg_t; + +/** Type of chip_rst register + * CDC-ACM chip reset control. + */ +typedef union { + struct { + /** rts : RO; bitpos: [0]; default: 0; + * 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. + */ + uint32_t rts:1; + /** dtr : RO; bitpos: [1]; default: 0; + * 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. + */ + uint32_t dtr:1; + /** usb_uart_chip_rst_dis : R/W; bitpos: [2]; default: 0; + * Set this bit to disable chip reset from usb serial channel to reset chip. + */ + uint32_t usb_uart_chip_rst_dis:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} usb_serial_jtag_chip_rst_reg_t; + +/** Type of get_line_code_w0 register + * W0 of GET_LINE_CODING command. + */ +typedef union { + struct { + /** get_dw_dte_rate : R/W; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_dw_dte_rate:32; + }; + uint32_t val; +} usb_serial_jtag_get_line_code_w0_reg_t; + +/** Type of get_line_code_w1 register + * W1 of GET_LINE_CODING command. + */ +typedef union { + struct { + /** get_bdata_bits : R/W; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_bdata_bits:8; + /** get_bparity_type : R/W; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_bparity_type:8; + /** get_bchar_format : R/W; bitpos: [23:16]; default: 0; + * The value of bDataBits set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_bchar_format:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} usb_serial_jtag_get_line_code_w1_reg_t; + +/** Type of config_update register + * Configuration registers' value update + */ +typedef union { + struct { + /** config_update : WT; bitpos: [0]; default: 0; + * Write 1 to this register would update the value of configure registers from APB + * clock domain to 48MHz clock domain. + */ + uint32_t config_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_config_update_reg_t; + +/** Type of ser_afifo_config register + * Serial AFIFO configure register + */ +typedef union { + struct { + /** serial_in_afifo_reset_wr : R/W; bitpos: [0]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO write clock domain. + */ + uint32_t serial_in_afifo_reset_wr:1; + /** serial_in_afifo_reset_rd : R/W; bitpos: [1]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO read clock domain. + */ + uint32_t serial_in_afifo_reset_rd:1; + /** serial_out_afifo_reset_wr : R/W; bitpos: [2]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + */ + uint32_t serial_out_afifo_reset_wr:1; + /** serial_out_afifo_reset_rd : R/W; bitpos: [3]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + */ + uint32_t serial_out_afifo_reset_rd:1; + /** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1; + * CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + */ + uint32_t serial_out_afifo_rempty:1; + /** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0; + * CDC_ACM OUT IN async FIFO empty signal in write clock domain. + */ + uint32_t serial_in_afifo_wfull:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} usb_serial_jtag_ser_afifo_config_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_raw register + * Interrupt raw status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when flush cmd is received for IN + * endpoint 2 of JTAG. + */ + uint32_t jtag_in_flush_int_raw:1; + /** sof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when SOF frame is received. + */ + uint32_t sof_int_raw:1; + /** serial_out_recv_pkt_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when Serial Port OUT Endpoint received + * one packet. + */ + uint32_t serial_out_recv_pkt_int_raw:1; + /** serial_in_empty_int_raw : R/WTC/SS; bitpos: [3]; default: 1; + * The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + */ + uint32_t serial_in_empty_int_raw:1; + /** pid_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when pid error is detected. + */ + uint32_t pid_err_int_raw:1; + /** crc5_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when CRC5 error is detected. + */ + uint32_t crc5_err_int_raw:1; + /** crc16_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when CRC16 error is detected. + */ + uint32_t crc16_err_int_raw:1; + /** stuff_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when stuff error is detected. + */ + uint32_t stuff_err_int_raw:1; + /** in_token_rec_in_ep1_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when IN token for IN endpoint 1 is + * received. + */ + uint32_t in_token_rec_in_ep1_int_raw:1; + /** usb_bus_reset_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when usb bus reset is detected. + */ + uint32_t usb_bus_reset_int_raw:1; + /** out_ep1_zero_payload_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 1 received packet with + * zero palyload. + */ + uint32_t out_ep1_zero_payload_int_raw:1; + /** out_ep2_zero_payload_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 2 received packet with + * zero palyload. + */ + uint32_t out_ep2_zero_payload_int_raw:1; + /** rts_chg_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit turns to high level when level of RTS from usb serial channel + * is changed. + */ + uint32_t rts_chg_int_raw:1; + /** dtr_chg_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit turns to high level when level of DTR from usb serial channel + * is changed. + */ + uint32_t dtr_chg_int_raw:1; + /** get_line_code_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit turns to high level when level of GET LINE CODING request is + * received. + */ + uint32_t get_line_code_int_raw:1; + /** set_line_code_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit turns to high level when level of SET LINE CODING request is + * received. + */ + uint32_t set_line_code_int_raw:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_raw_reg_t; + +/** Type of int_st register + * Interrupt status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t jtag_in_flush_int_st:1; + /** sof_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ + uint32_t sof_int_st:1; + /** serial_out_recv_pkt_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * interrupt. + */ + uint32_t serial_out_recv_pkt_int_st:1; + /** serial_in_empty_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_in_empty_int_st:1; + /** pid_err_int_st : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ + uint32_t pid_err_int_st:1; + /** crc5_err_int_st : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ + uint32_t crc5_err_int_st:1; + /** crc16_err_int_st : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ + uint32_t crc16_err_int_st:1; + /** stuff_err_int_st : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ + uint32_t stuff_err_int_st:1; + /** in_token_rec_in_ep1_int_st : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT + * interrupt. + */ + uint32_t in_token_rec_in_ep1_int_st:1; + /** usb_bus_reset_int_st : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ + uint32_t usb_bus_reset_int_st:1; + /** out_ep1_zero_payload_int_st : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT + * interrupt. + */ + uint32_t out_ep1_zero_payload_int_st:1; + /** out_ep2_zero_payload_int_st : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT + * interrupt. + */ + uint32_t out_ep2_zero_payload_int_st:1; + /** rts_chg_int_st : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ + uint32_t rts_chg_int_st:1; + /** dtr_chg_int_st : RO; bitpos: [13]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ + uint32_t dtr_chg_int_st:1; + /** get_line_code_int_st : RO; bitpos: [14]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ + uint32_t get_line_code_int_st:1; + /** set_line_code_int_st : RO; bitpos: [15]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ + uint32_t set_line_code_int_st:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t jtag_in_flush_int_ena:1; + /** sof_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ + uint32_t sof_int_ena:1; + /** serial_out_recv_pkt_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ + uint32_t serial_out_recv_pkt_int_ena:1; + /** serial_in_empty_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_in_empty_int_ena:1; + /** pid_err_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ + uint32_t pid_err_int_ena:1; + /** crc5_err_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ + uint32_t crc5_err_int_ena:1; + /** crc16_err_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ + uint32_t crc16_err_int_ena:1; + /** stuff_err_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ + uint32_t stuff_err_int_ena:1; + /** in_token_rec_in_ep1_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt. + */ + uint32_t in_token_rec_in_ep1_int_ena:1; + /** usb_bus_reset_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ + uint32_t usb_bus_reset_int_ena:1; + /** out_ep1_zero_payload_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep1_zero_payload_int_ena:1; + /** out_ep2_zero_payload_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep2_zero_payload_int_ena:1; + /** rts_chg_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ + uint32_t rts_chg_int_ena:1; + /** dtr_chg_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ + uint32_t dtr_chg_int_ena:1; + /** get_line_code_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ + uint32_t get_line_code_int_ena:1; + /** set_line_code_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ + uint32_t set_line_code_int_ena:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t jtag_in_flush_int_clr:1; + /** sof_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt. + */ + uint32_t sof_int_clr:1; + /** serial_out_recv_pkt_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ + uint32_t serial_out_recv_pkt_int_clr:1; + /** serial_in_empty_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_in_empty_int_clr:1; + /** pid_err_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ + uint32_t pid_err_int_clr:1; + /** crc5_err_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ + uint32_t crc5_err_int_clr:1; + /** crc16_err_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ + uint32_t crc16_err_int_clr:1; + /** stuff_err_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ + uint32_t stuff_err_int_clr:1; + /** in_token_rec_in_ep1_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt. + */ + uint32_t in_token_rec_in_ep1_int_clr:1; + /** usb_bus_reset_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ + uint32_t usb_bus_reset_int_clr:1; + /** out_ep1_zero_payload_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep1_zero_payload_int_clr:1; + /** out_ep2_zero_payload_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep2_zero_payload_int_clr:1; + /** rts_chg_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ + uint32_t rts_chg_int_clr:1; + /** dtr_chg_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ + uint32_t dtr_chg_int_clr:1; + /** get_line_code_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ + uint32_t get_line_code_int_clr:1; + /** set_line_code_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ + uint32_t set_line_code_int_clr:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_clr_reg_t; + + +/** Group: Status Registers */ +/** Type of jfifo_st register + * JTAG FIFO status and control registers. + */ +typedef union { + struct { + /** in_fifo_cnt : RO; bitpos: [1:0]; default: 0; + * JTAT in fifo counter. + */ + uint32_t in_fifo_cnt:2; + /** in_fifo_empty : RO; bitpos: [2]; default: 1; + * 1: JTAG in fifo is empty. + */ + uint32_t in_fifo_empty:1; + /** in_fifo_full : RO; bitpos: [3]; default: 0; + * 1: JTAG in fifo is full. + */ + uint32_t in_fifo_full:1; + /** out_fifo_cnt : RO; bitpos: [5:4]; default: 0; + * JTAT out fifo counter. + */ + uint32_t out_fifo_cnt:2; + /** out_fifo_empty : RO; bitpos: [6]; default: 1; + * 1: JTAG out fifo is empty. + */ + uint32_t out_fifo_empty:1; + /** out_fifo_full : RO; bitpos: [7]; default: 0; + * 1: JTAG out fifo is full. + */ + uint32_t out_fifo_full:1; + /** in_fifo_reset : R/W; bitpos: [8]; default: 0; + * Write 1 to reset JTAG in fifo. + */ + uint32_t in_fifo_reset:1; + /** out_fifo_reset : R/W; bitpos: [9]; default: 0; + * Write 1 to reset JTAG out fifo. + */ + uint32_t out_fifo_reset:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} usb_serial_jtag_jfifo_st_reg_t; + +/** Type of fram_num register + * Last received SOF frame index register. + */ +typedef union { + struct { + /** sof_frame_index : RO; bitpos: [10:0]; default: 0; + * Frame index of received SOF frame. + */ + uint32_t sof_frame_index:11; + uint32_t reserved_11:21; + }; + uint32_t val; +} usb_serial_jtag_fram_num_reg_t; + +/** Type of in_ep0_st register + * Control IN endpoint status information. + */ +typedef union { + struct { + /** in_ep0_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 0. + */ + uint32_t in_ep0_state:2; + /** in_ep0_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 0. + */ + uint32_t in_ep0_wr_addr:7; + /** in_ep0_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 0. + */ + uint32_t in_ep0_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep0_st_reg_t; + +/** Type of in_ep1_st register + * CDC-ACM IN endpoint status information. + */ +typedef union { + struct { + /** in_ep1_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 1. + */ + uint32_t in_ep1_state:2; + /** in_ep1_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 1. + */ + uint32_t in_ep1_wr_addr:7; + /** in_ep1_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 1. + */ + uint32_t in_ep1_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep1_st_reg_t; + +/** Type of in_ep2_st register + * CDC-ACM interrupt IN endpoint status information. + */ +typedef union { + struct { + /** in_ep2_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 2. + */ + uint32_t in_ep2_state:2; + /** in_ep2_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 2. + */ + uint32_t in_ep2_wr_addr:7; + /** in_ep2_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 2. + */ + uint32_t in_ep2_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep2_st_reg_t; + +/** Type of in_ep3_st register + * JTAG IN endpoint status information. + */ +typedef union { + struct { + /** in_ep3_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 3. + */ + uint32_t in_ep3_state:2; + /** in_ep3_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 3. + */ + uint32_t in_ep3_wr_addr:7; + /** in_ep3_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 3. + */ + uint32_t in_ep3_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep3_st_reg_t; + +/** Type of out_ep0_st register + * Control OUT endpoint status information. + */ +typedef union { + struct { + /** out_ep0_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 0. + */ + uint32_t out_ep0_state:2; + /** out_ep0_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + */ + uint32_t out_ep0_wr_addr:7; + /** out_ep0_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 0. + */ + uint32_t out_ep0_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_out_ep0_st_reg_t; + +/** Type of out_ep1_st register + * CDC-ACM OUT endpoint status information. + */ +typedef union { + struct { + /** out_ep1_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 1. + */ + uint32_t out_ep1_state:2; + /** out_ep1_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + */ + uint32_t out_ep1_wr_addr:7; + /** out_ep1_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 1. + */ + uint32_t out_ep1_rd_addr:7; + /** out_ep1_rec_data_cnt : RO; bitpos: [22:16]; default: 0; + * Data count in OUT endpoint 1 when one packet is received. + */ + uint32_t out_ep1_rec_data_cnt:7; + uint32_t reserved_23:9; + }; + uint32_t val; +} usb_serial_jtag_out_ep1_st_reg_t; + +/** Type of out_ep2_st register + * JTAG OUT endpoint status information. + */ +typedef union { + struct { + /** out_ep2_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 2. + */ + uint32_t out_ep2_state:2; + /** out_ep2_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + */ + uint32_t out_ep2_wr_addr:7; + /** out_ep2_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 2. + */ + uint32_t out_ep2_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_out_ep2_st_reg_t; + +/** Type of set_line_code_w0 register + * W0 of SET_LINE_CODING command. + */ +typedef union { + struct { + /** dw_dte_rate : RO; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by host through SET_LINE_CODING command. + */ + uint32_t dw_dte_rate:32; + }; + uint32_t val; +} usb_serial_jtag_set_line_code_w0_reg_t; + +/** Type of set_line_code_w1 register + * W1 of SET_LINE_CODING command. + */ +typedef union { + struct { + /** bchar_format : RO; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by host through SET_LINE_CODING command. + */ + uint32_t bchar_format:8; + /** bparity_type : RO; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by host through SET_LINE_CODING command. + */ + uint32_t bparity_type:8; + /** bdata_bits : RO; bitpos: [23:16]; default: 0; + * The value of bDataBits set by host through SET_LINE_CODING command. + */ + uint32_t bdata_bits:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} usb_serial_jtag_set_line_code_w1_reg_t; + +/** Type of bus_reset_st register + * USB Bus reset status register + */ +typedef union { + struct { + /** usb_bus_reset_st : RO; bitpos: [0]; default: 1; + * USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus + * reset is released. + */ + uint32_t usb_bus_reset_st:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_bus_reset_st_reg_t; + + +/** Group: Version Registers */ +/** Type of date register + * Date register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 34640416; + * register version. + */ + uint32_t date:32; + }; + uint32_t val; +} usb_serial_jtag_date_reg_t; + + +typedef struct usb_serial_jtag_dev_s { + volatile usb_serial_jtag_ep1_reg_t ep1; + volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf; + volatile usb_serial_jtag_int_raw_reg_t int_raw; + volatile usb_serial_jtag_int_st_reg_t int_st; + volatile usb_serial_jtag_int_ena_reg_t int_ena; + volatile usb_serial_jtag_int_clr_reg_t int_clr; + volatile usb_serial_jtag_conf0_reg_t conf0; + volatile usb_serial_jtag_test_reg_t test; + volatile usb_serial_jtag_jfifo_st_reg_t jfifo_st; + volatile usb_serial_jtag_fram_num_reg_t fram_num; + volatile usb_serial_jtag_in_ep0_st_reg_t in_ep0_st; + volatile usb_serial_jtag_in_ep1_st_reg_t in_ep1_st; + volatile usb_serial_jtag_in_ep2_st_reg_t in_ep2_st; + volatile usb_serial_jtag_in_ep3_st_reg_t in_ep3_st; + volatile usb_serial_jtag_out_ep0_st_reg_t out_ep0_st; + volatile usb_serial_jtag_out_ep1_st_reg_t out_ep1_st; + volatile usb_serial_jtag_out_ep2_st_reg_t out_ep2_st; + volatile usb_serial_jtag_misc_conf_reg_t misc_conf; + volatile usb_serial_jtag_mem_conf_reg_t mem_conf; + volatile usb_serial_jtag_chip_rst_reg_t chip_rst; + volatile usb_serial_jtag_set_line_code_w0_reg_t set_line_code_w0; + volatile usb_serial_jtag_set_line_code_w1_reg_t set_line_code_w1; + volatile usb_serial_jtag_get_line_code_w0_reg_t get_line_code_w0; + volatile usb_serial_jtag_get_line_code_w1_reg_t get_line_code_w1; + volatile usb_serial_jtag_config_update_reg_t config_update; + volatile usb_serial_jtag_ser_afifo_config_reg_t ser_afifo_config; + volatile usb_serial_jtag_bus_reset_st_reg_t bus_reset_st; + uint32_t reserved_06c[5]; + volatile usb_serial_jtag_date_reg_t date; +} usb_serial_jtag_dev_t; + +extern usb_serial_jtag_dev_t USB_SERIAL_JTAG; + +#ifndef __cplusplus +_Static_assert(sizeof(usb_serial_jtag_dev_t) == 0x84, "Invalid size of usb_serial_jtag_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/wdev_reg.h b/components/soc/esp32c6/include/soc/wdev_reg.h new file mode 100644 index 0000000000..d4207e5c88 --- /dev/null +++ b/components/soc/esp32c6/include/soc/wdev_reg.h @@ -0,0 +1,13 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc.h" +#include "soc/lpperi_reg.h" + +/* Hardware random number generator register */ +#define WDEV_RND_REG LPPERI_RNG_DATA_REG diff --git a/components/soc/esp32c6/interrupts.c b/components/soc/esp32c6/interrupts.c new file mode 100644 index 0000000000..075a674041 --- /dev/null +++ b/components/soc/esp32c6/interrupts.c @@ -0,0 +1,87 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/interrupts.h" + +const char *const esp_isr_names[] = { + [0] = "WIFI_MAC", + [1] = "WIFI_MAC_NMI", + [2] = "WIFI_PWR", + [3] = "WIFI_BB", + [4] = "BT_MAC", + [5] = "BT_BB", + [6] = "BT_BB_NMI", + [7] = "LP_TIMER", + [8] = "COEX", + [9] = "BLE_TIMER", + [10] = "BLE_SEC", + [11] = "I2C_MASTER", + [12] = "ZB_MAC", + [13] = "PMU", + [14] = "EFUSE", + [15] = "LP_RTC_TIMER", + [16] = "LP_UART", + [17] = "LP_I2C", + [18] = "LP_WDT", + [19] = "LP_PERI_TIMEOUT", + [20] = "LP_APM_M0", + [21] = "LP_APM_M1", + [22] = "CPU_FROM_CPU_0", + [23] = "CPU_FROM_CPU_1", + [24] = "CPU_FROM_CPU_2", + [25] = "CPU_FROM_CPU_3", + [26] = "ASSIST_DEBUG", + [27] = "TRACE", + [28] = "CACHE", + [29] = "CPU_PERI_TIMEOUT", + [30] = "GPIO_INTERRUPT_PRO", + [31] = "GPIO_INTERRUPT_PRO_NMI", + [32] = "PAU", + [33] = "HP_PERI_TIMEOUT", + [34] = "MODEM_PERI_TIMEOUT", + [35] = "HP_APM_M0", + [36] = "HP_APM_M1", + [37] = "HP_APM_M2", + [38] = "HP_APM_M3", + [39] = "LP_APM0", + [40] = "MSPI", + [41] = "I2S1", + [42] = "UHCI0", + [43] = "UART0", + [44] = "UART1", + [45] = "LEDC", + [46] = "CAN0", + [47] = "CAN1", + [48] = "USB", + [49] = "RMT", + [50] = "I2C_EXT0", + [51] = "TG0_T0", + [52] = "TG0_T1", + [53] = "TG0_WDT", + [54] = "TG1_T0", + [55] = "TG1_T1", + [56] = "TG1_WDT", + [57] = "SYSTIMER_TARGET0", + [58] = "SYSTIMER_TARGET1", + [59] = "SYSTIMER_TARGET2", + [60] = "APB_ADC", + [61] = "PWM", + [62] = "PCNT", + [63] = "PARL_IO", + [64] = "SLC0", + [65] = "SLC1", + [66] = "DMA_IN_CH0", + [67] = "DMA_IN_CH1", + [68] = "DMA_IN_CH2", + [69] = "DMA_OUT_CH0", + [70] = "DMA_OUT_CH1", + [71] = "DMA_OUT_CH2", + [72] = "GPSPI2", + [73] = "AES", + [74] = "SHA", + [75] = "RSA", + [76] = "ECC", +}; diff --git a/components/soc/esp32c6/ld/esp32c6.peripherals.ld b/components/soc/esp32c6/ld/esp32c6.peripherals.ld new file mode 100644 index 0000000000..55f47792d2 --- /dev/null +++ b/components/soc/esp32c6/ld/esp32c6.peripherals.ld @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +PROVIDE ( UART0 = 0x60000000 ); +PROVIDE ( UART1 = 0x60001000 ); +PROVIDE ( SPIMEM0 = 0x60002000 ); +PROVIDE ( SPIMEM1 = 0x60003000 ); +PROVIDE ( I2C0 = 0x60004000 ); +PROVIDE ( UHCI0 = 0x60005000 ); +PROVIDE ( RMT = 0x60006000 ); +PROVIDE ( RMTMEM = 0x60006400 ); +PROVIDE ( LEDC = 0x60007000 ); +PROVIDE ( TIMERG0 = 0x60008000 ); +PROVIDE ( TIMERG1 = 0x60009000 ); +PROVIDE ( SYSTIMER = 0x6000A000 ); +PROVIDE ( TWAI0 = 0x6000B000 ); +PROVIDE ( I2S0 = 0x6000C000 ); +PROVIDE ( TWAI1 = 0x6000D000 ); +PROVIDE ( APB_SARADC = 0x6000E000 ); +PROVIDE ( USB_SERIAL_JTAG = 0x6000F000 ); + +PROVIDE ( INTMTX = 0x60010000 ); +PROVIDE ( ATOMIC_LOCKER = 0x60011000 ); +PROVIDE ( PCNT = 0x60012000 ); +PROVIDE ( SOC_ETM = 0x60013000 ); +PROVIDE ( MCPWM = 0x60014000 ); +PROVIDE ( PARL_IO = 0x60015000 ); +PROVIDE ( HINF = 0x60016000 ); +PROVIDE ( SLC = 0x60017000 ); +PROVIDE ( HOST = 0x60018000 ); +PROVIDE ( PVT_MONITOR = 0x60019000 ); + +PROVIDE ( GDMA = 0x60080000 ); +PROVIDE ( GPSPI2 = 0x60081000 ); + +PROVIDE ( AES = 0x60088000 ); +PROVIDE ( SHA = 0x60089000 ); +PROVIDE ( RSA = 0x6008A000 ); +PROVIDE ( ECC = 0x6008B000 ); +PROVIDE ( DS = 0x6008C000 ); +PROVIDE ( HMAC = 0x6008D000 ); + +PROVIDE ( IO_MUX = 0x60090000 ); +PROVIDE ( GPIO = 0x60091000 ); +PROVIDE ( GPIO_EXT = 0x60091f00 ); /*ESP32C6-TODO*/ +PROVIDE ( SDM = 0x60091f00 ); +PROVIDE ( GLITCH_FILTER = 0x60091f30 ); +PROVIDE ( GPIO_ETM = 0x60091f60 ); + +PROVIDE ( MEM_MONITOR = 0x60092000 ); +PROVIDE ( PAU = 0x60093000 ); +PROVIDE ( HP_SYSTEM = 0x60095000 ); +PROVIDE ( PCR = 0x60096000 ); +PROVIDE ( TEE = 0x60098000 ); +PROVIDE ( HP_APM = 0x60099000 ); + +PROVIDE ( PMU = 0x600B0000 ); +PROVIDE ( LP_CLKRST = 0x600B0400 ); +PROVIDE ( EFUSE = 0x600B0800 ); +PROVIDE ( LP_TIMER = 0x600B0C00 ); +PROVIDE ( LP_AON = 0x600B1000 ); +PROVIDE ( LP_UART = 0x600B1400 ); +PROVIDE ( LP_I2C = 0x600B1800 ); +PROVIDE ( LP_WDT = 0x600B1C00 ); +PROVIDE ( LP_IO = 0x600B2000 ); +PROVIDE ( LP_I2C_ANA_MST = 0x600B2400 ); +PROVIDE ( LPPERI = 0x600B2800 ); +PROVIDE ( LP_ANA_PERI = 0x600B2C00 ); +PROVIDE ( LP_APM = 0x600B3800 ); +PROVIDE ( OTP_DEBUG = 0x600B3C00 ); diff --git a/components/soc/esp32c6/ledc_periph.c b/components/soc/esp32c6/ledc_periph.c new file mode 100644 index 0000000000..b150f9bc99 --- /dev/null +++ b/components/soc/esp32c6/ledc_periph.c @@ -0,0 +1,17 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/ledc_periph.h" +#include "soc/gpio_sig_map.h" + +/* + Bunch of constants for every LEDC peripheral: GPIO signals +*/ +const ledc_signal_conn_t ledc_periph_signal[1] = { + { + .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX, + } +}; diff --git a/components/soc/esp32c6/pcnt_periph.c b/components/soc/esp32c6/pcnt_periph.c new file mode 100644 index 0000000000..83c3424a0f --- /dev/null +++ b/components/soc/esp32c6/pcnt_periph.c @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/pcnt_periph.h" +#include "soc/gpio_sig_map.h" + +const pcnt_signal_conn_t pcnt_periph_signals = { + .groups = { + [0] = { + .module = PERIPH_PCNT_MODULE, + .irq = ETS_PCNT_INTR_SOURCE, + .units = { + [0] = { + .channels = { + [0] = { + .control_sig = PCNT_CTRL_CH0_IN0_IDX, + .pulse_sig = PCNT_SIG_CH0_IN0_IDX + }, + [1] = { + .control_sig = PCNT_CTRL_CH1_IN0_IDX, + .pulse_sig = PCNT_SIG_CH1_IN0_IDX + } + } + }, + [1] = { + .channels = { + [0] = { + .control_sig = PCNT_CTRL_CH0_IN1_IDX, + .pulse_sig = PCNT_SIG_CH0_IN1_IDX + }, + [1] = { + .control_sig = PCNT_CTRL_CH1_IN1_IDX, + .pulse_sig = PCNT_SIG_CH1_IN1_IDX + } + } + }, + [2] = { + .channels = { + [0] = { + .control_sig = PCNT_CTRL_CH0_IN2_IDX, + .pulse_sig = PCNT_SIG_CH0_IN2_IDX + }, + [1] = { + .control_sig = PCNT_CTRL_CH1_IN2_IDX, + .pulse_sig = PCNT_SIG_CH1_IN2_IDX + } + } + }, + [3] = { + .channels = { + [0] = { + .control_sig = PCNT_CTRL_CH0_IN3_IDX, + .pulse_sig = PCNT_SIG_CH0_IN3_IDX + }, + [1] = { + .control_sig = PCNT_CTRL_CH1_IN3_IDX, + .pulse_sig = PCNT_SIG_CH1_IN3_IDX + } + } + } + } + } + } +}; diff --git a/components/soc/esp32c6/rmt_periph.c b/components/soc/esp32c6/rmt_periph.c new file mode 100644 index 0000000000..0c5a55871e --- /dev/null +++ b/components/soc/esp32c6/rmt_periph.c @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/rmt_periph.h" +#include "soc/gpio_sig_map.h" + +const rmt_signal_conn_t rmt_periph_signals = { + .groups = { + [0] = { + .module = PERIPH_RMT_MODULE, + .irq = ETS_RMT_INTR_SOURCE, + .channels = { + [0] = { + .tx_sig = RMT_SIG_OUT0_IDX, + .rx_sig = -1 + }, + [1] = { + .tx_sig = RMT_SIG_OUT1_IDX, + .rx_sig = -1 + }, + [2] = { + .tx_sig = -1, + .rx_sig = RMT_SIG_IN0_IDX + }, + [3] = { + .tx_sig = -1, + .rx_sig = RMT_SIG_IN1_IDX + }, + } + } + } +}; diff --git a/components/soc/esp32c6/sdm_periph.c b/components/soc/esp32c6/sdm_periph.c new file mode 100644 index 0000000000..6d41dc98f1 --- /dev/null +++ b/components/soc/esp32c6/sdm_periph.c @@ -0,0 +1,25 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/sdm_periph.h" +#include "soc/gpio_sig_map.h" + +const sigma_delta_signal_conn_t sigma_delta_periph_signals = { + .channels = { + [0] = { + GPIO_SD0_OUT_IDX + }, + [1] = { + GPIO_SD1_OUT_IDX + }, + [2] = { + GPIO_SD2_OUT_IDX + }, + [3] = { + GPIO_SD3_OUT_IDX + } + } +}; diff --git a/components/soc/esp32c6/spi_periph.c b/components/soc/esp32c6/spi_periph.c new file mode 100644 index 0000000000..2f292bfdeb --- /dev/null +++ b/components/soc/esp32c6/spi_periph.c @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/spi_periph.h" +#include "stddef.h" + +/* + Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { + { // TODO: IDF-5333 Need check + .spiclk_in = 0,/* SPI clock is not an input signal*/ + .spics_in = 0,/* SPI cs is not an input signal*/ + .spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK, + .spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI, + .spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO, + .spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP, + .spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD, + .spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS, + .irq = ETS_MSPI_INTR_SOURCE, + .irq_dma = -1, + .module = PERIPH_SPI_MODULE, + .hw = (spi_dev_t *) &SPIMEM1, + .func = SPI_FUNC_NUM, + }, { // TODO: IDF-5334 Need check + .spiclk_out = FSPICLK_OUT_IDX, + .spiclk_in = FSPICLK_IN_IDX, + .spid_out = FSPID_OUT_IDX, + .spiq_out = FSPIQ_OUT_IDX, + .spiwp_out = FSPIWP_OUT_IDX, + .spihd_out = FSPIHD_OUT_IDX, + .spid_in = FSPID_IN_IDX, + .spiq_in = FSPIQ_IN_IDX, + .spiwp_in = FSPIWP_IN_IDX, + .spihd_in = FSPIHD_IN_IDX, + .spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX, FSPICS3_OUT_IDX, FSPICS4_OUT_IDX, FSPICS5_OUT_IDX}, + .spics_in = FSPICS0_IN_IDX, + .spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK, + .spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI, + .spiq_iomux_pin = SPI2_IOMUX_PIN_NUM_MISO, + .spiwp_iomux_pin = SPI2_IOMUX_PIN_NUM_WP, + .spihd_iomux_pin = SPI2_IOMUX_PIN_NUM_HD, + .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS, + .irq = ETS_GSPI2_INTR_SOURCE, + .irq_dma = -1, + .module = PERIPH_SPI2_MODULE, + .hw = &GPSPI2, + .func = SPI2_FUNC_NUM, + } +}; diff --git a/components/soc/esp32c6/temperature_sensor_periph.c b/components/soc/esp32c6/temperature_sensor_periph.c new file mode 100644 index 0000000000..f5ad36f5a9 --- /dev/null +++ b/components/soc/esp32c6/temperature_sensor_periph.c @@ -0,0 +1,16 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/temperature_sensor_periph.h" + +const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = { + /*Offset reg_val min max error */ + {-2, 5, 50, 125, 3}, + {-1, 7, 20, 100, 2}, + { 0, 15, -10, 80, 1}, + { 1, 11, -30, 50, 2}, + { 2, 10, -40, 20, 3}, +}; diff --git a/components/soc/esp32c6/timer_periph.c b/components/soc/esp32c6/timer_periph.c new file mode 100644 index 0000000000..089c80958f --- /dev/null +++ b/components/soc/esp32c6/timer_periph.c @@ -0,0 +1,24 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/timer_periph.h" + +const timer_group_signal_conn_t timer_group_periph_signals = { + .groups = { + [0] = { + .module = PERIPH_TIMG0_MODULE, + .timer_irq_id = { + [0] = ETS_TG0_T0_LEVEL_INTR_SOURCE, + } + }, + [1] = { + .module = PERIPH_TIMG1_MODULE, + .timer_irq_id = { + [0] = ETS_TG1_T0_LEVEL_INTR_SOURCE, + } + } + } +}; diff --git a/components/soc/esp32c6/uart_periph.c b/components/soc/esp32c6/uart_periph.c new file mode 100644 index 0000000000..ca2adc3e1f --- /dev/null +++ b/components/soc/esp32c6/uart_periph.c @@ -0,0 +1,80 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/uart_periph.h" + +/* + Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { + { + .pins = { + [SOC_UART_TX_PIN_IDX] = { + .default_gpio = U0TXD_GPIO_NUM, + .iomux_func = U0TXD_MUX_FUNC, + .input = 0, + .signal = U0TXD_OUT_IDX, + }, + + [SOC_UART_RX_PIN_IDX] = { + .default_gpio = U0RXD_GPIO_NUM, + .iomux_func = U0RXD_MUX_FUNC, + .input = 1, + .signal = U0RXD_IN_IDX, + }, + + [SOC_UART_RTS_PIN_IDX] = { + .default_gpio = U0RTS_GPIO_NUM, + .iomux_func = U0RTS_MUX_FUNC, + .input = 0, + .signal = U0RTS_OUT_IDX, + }, + + [SOC_UART_CTS_PIN_IDX] = { + .default_gpio = U0CTS_GPIO_NUM, + .iomux_func = U0CTS_MUX_FUNC, + .input = 1, + .signal = U0CTS_IN_IDX, + } + }, + .irq = ETS_UART0_INTR_SOURCE, + .module = PERIPH_UART0_MODULE, + }, + + { + .pins = { + [SOC_UART_TX_PIN_IDX] = { + .default_gpio = U1TXD_GPIO_NUM, + .iomux_func = U1TXD_MUX_FUNC, + .input = 0, + .signal = U1TXD_OUT_IDX, + }, + + [SOC_UART_RX_PIN_IDX] = { + .default_gpio = U1RXD_GPIO_NUM, + .iomux_func = U1RXD_MUX_FUNC, + .input = 1, + .signal = U1RXD_IN_IDX, + }, + + [SOC_UART_RTS_PIN_IDX] = { + .default_gpio = U1RTS_GPIO_NUM, + .iomux_func = U1RTS_MUX_FUNC, + .input = 0, + .signal = U1RTS_OUT_IDX, + }, + + [SOC_UART_CTS_PIN_IDX] = { + .default_gpio = U1CTS_GPIO_NUM, + .iomux_func = U1CTS_MUX_FUNC, + .input = 1, + .signal = U1CTS_IN_IDX, + }, + }, + .irq = ETS_UART1_INTR_SOURCE, + .module = PERIPH_UART1_MODULE, + }, +}; diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 7c38936113..5fc424d9f5 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -23,10 +23,6 @@ config SOC_BT_SUPPORTED bool default y -config SOC_ESP_NIMBLE_CONTROLLER - bool - default y - config SOC_ASYNC_MEMCPY_SUPPORTED bool default y @@ -67,6 +63,14 @@ config SOC_SDM_SUPPORTED bool default y +config SOC_LEDC_SUPPORTED + bool + default y + +config SOC_I2C_SUPPORTED + bool + default y + config SOC_SYSTIMER_SUPPORTED bool default y @@ -287,6 +291,10 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK int default 0 +config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK + hex + default 0x000001FFFFFFFFC0 + config SOC_GPIO_SUPPORT_SLP_SWITCH bool default y @@ -335,6 +343,10 @@ config SOC_I2S_HW_VERSION_2 bool default y +config SOC_I2S_SUPPORTS_XTAL + bool + default y + config SOC_I2S_SUPPORTS_PCM bool default y @@ -447,10 +459,6 @@ config SOC_RMT_SUPPORT_AHB bool default y -config SOC_RMT_SUPPORT_RC_FAST - bool - default y - config SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH int default 128 @@ -507,6 +515,10 @@ config SOC_SPI_PERIPH_NUM int default 2 +config SOC_SPI_MAX_CS_NUM + int + default 6 + config SOC_SPI_MAXIMUM_BUFFER_SIZE int default 64 @@ -695,6 +707,10 @@ config SOC_UART_SUPPORT_WAKEUP_INT bool default y +config SOC_UART_SUPPORT_AHB_CLK + bool + default y + config SOC_UART_SUPPORT_RTC_CLK bool default y @@ -738,3 +754,15 @@ config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC config SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL bool default y + +config SOC_BLE_SUPPORTED + bool + default y + +config SOC_BLE_MESH_SUPPORTED + bool + default y + +config SOC_ESP_NIMBLE_CONTROLLER + bool + default y diff --git a/components/soc/esp32h2/include/soc/clk_tree_defs.h b/components/soc/esp32h2/include/soc/clk_tree_defs.h index 1b19e0c78f..db53424894 100644 --- a/components/soc/esp32h2/include/soc/clk_tree_defs.h +++ b/components/soc/esp32h2/include/soc/clk_tree_defs.h @@ -158,14 +158,13 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of RMT */ -#define SOC_RMT_CLKS {SOC_MOD_CLK_AHB, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} +#define SOC_RMT_CLKS {SOC_MOD_CLK_AHB, SOC_MOD_CLK_XTAL} /** * @brief Type of RMT clock source */ typedef enum { RMT_CLK_SRC_AHB = SOC_MOD_CLK_AHB, /*!< Select AHB clock as the source clock */ - RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_AHB, /*!< Select AHB as the default choice */ } soc_periph_rmt_clk_src_t; @@ -212,7 +211,7 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of */ -#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL} +#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL, SOC_MOD_CLK_XTAL} /** * @brief I2S clock source enum @@ -220,6 +219,7 @@ typedef enum { typedef enum { I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL, /*!< Select SOC_MOD_CLK_PLL as the default source clock */ I2S_CLK_SRC_PLL_96M = SOC_MOD_CLK_PLL, /*!< Select PLL as the source clock */ + I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ } soc_periph_i2s_clk_src_t; /////////////////////////////////////////////////I2C//////////////////////////////////////////////////////////////////// diff --git a/components/soc/esp32h2/include/soc/hwcrypto_reg.h b/components/soc/esp32h2/include/soc/hwcrypto_reg.h index 474b07faa3..0e4ceb3000 100644 --- a/components/soc/esp32h2/include/soc/hwcrypto_reg.h +++ b/components/soc/esp32h2/include/soc/hwcrypto_reg.h @@ -1,16 +1,9 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. #ifndef __HWCRYPTO_REG_H__ #define __HWCRYPTO_REG_H__ @@ -113,11 +106,6 @@ #define AES_J_BASE ((DR_REG_AES_BASE) + 0x70) #define AES_T_BASE ((DR_REG_AES_BASE) + 0x80) -#define AES_INT_CLR_REG ((DR_REG_AES_BASE) + 0xAC) -#define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0) -#define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4) -#define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8) - /* AES_STATE_REG values */ #define AES_STATE_IDLE 0 #define AES_STATE_BUSY 1 diff --git a/components/soc/esp32h2/include/soc/i2s_struct.h b/components/soc/esp32h2/include/soc/i2s_struct.h index f58a924987..fac2c8af11 100644 --- a/components/soc/esp32h2/include/soc/i2s_struct.h +++ b/components/soc/esp32h2/include/soc/i2s_struct.h @@ -141,7 +141,7 @@ typedef volatile struct i2s_dev_s { uint32_t rx_clkm_div_num: 8; /*Integral I2S clock divider value*/ uint32_t reserved8: 18; /*Reserved*/ uint32_t rx_clk_active: 1; /*I2S Rx module clock enable signal.*/ - uint32_t rx_clk_sel: 2; /*Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/ + uint32_t rx_clk_sel: 2; /*Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/ uint32_t mclk_sel: 1; /*0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT.*/ uint32_t reserved30: 2; /*Reserved*/ }; @@ -152,7 +152,7 @@ typedef volatile struct i2s_dev_s { uint32_t tx_clkm_div_num: 8; /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2 z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2 z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/ uint32_t reserved8: 18; /*Reserved*/ uint32_t tx_clk_active: 1; /*I2S Tx module clock enable signal.*/ - uint32_t tx_clk_sel: 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/ + uint32_t tx_clk_sel: 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/ uint32_t clk_en: 1; /*Set this bit to enable clk gate*/ uint32_t reserved30: 2; /*Reserved*/ }; diff --git a/components/soc/esp32h2/include/soc/rtc.h b/components/soc/esp32h2/include/soc/rtc.h index 4764b3a7f2..5373e0a371 100644 --- a/components/soc/esp32h2/include/soc/rtc.h +++ b/components/soc/esp32h2/include/soc/rtc.h @@ -446,6 +446,11 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles); * 32k XTAL is being calibrated, but the oscillator has not started up (due to * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board). * + * @note When 32k CLK is being calibrated, this function will check the accuracy + * of the clock. Since the xtal 32k or ext osc 32k is generally very stable, if + * the check fails, then consider this an invalid 32k clock and return 0. This + * check can filter some jamming signal. + * * @param cal_clk clock to be measured * @param slow_clk_cycles number of slow clock cycles to average * @return average slow clock period in microseconds, Q13.19 fixed point format, diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h index 8118b8662f..e36b6550db 100644 --- a/components/soc/esp32h2/include/soc/soc.h +++ b/components/soc/esp32h2/include/soc/soc.h @@ -235,3 +235,6 @@ //Interrupt medium level, used for INT WDT for example #define SOC_INTERRUPT_LEVEL_MEDIUM 4 + +// Interrupt number for the Interrupt watchdog +#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM) diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index e990dbf6b1..1c7778c6f7 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -38,7 +38,6 @@ #define SOC_GDMA_SUPPORTED 1 #define SOC_TWAI_SUPPORTED 1 #define SOC_BT_SUPPORTED 1 -#define SOC_ESP_NIMBLE_CONTROLLER 1 #define SOC_ASYNC_MEMCPY_SUPPORTED 1 #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 #define SOC_SUPPORTS_SECURE_DL_MODE 1 @@ -49,6 +48,8 @@ #define SOC_I2S_SUPPORTED 1 #define SOC_RMT_SUPPORTED 1 #define SOC_SDM_SUPPORTED 1 +#define SOC_LEDC_SUPPORTED 1 +#define SOC_I2C_SUPPORTED 1 #define SOC_SYSTIMER_SUPPORTED 1 #define SOC_AES_SUPPORTED 1 #define SOC_MPI_SUPPORTED 1 @@ -155,8 +156,12 @@ #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK #if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1 #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5) +// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_40) +#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000001FFFFFFFFC0ULL #elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2 #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT7 | BIT8 | BIT9 | BIT10 | BIT11 | BIT12) +// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_0~6, GPIO_NUM_13~25) +#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000003FFE07FULL #endif // Support to configure sleep status @@ -183,6 +188,7 @@ /*-------------------------- I2S CAPS ----------------------------------------*/ #define SOC_I2S_NUM (1) #define SOC_I2S_HW_VERSION_2 (1) +#define SOC_I2S_SUPPORTS_XTAL (1) #define SOC_I2S_SUPPORTS_PCM (1) #define SOC_I2S_SUPPORTS_PDM (1) #define SOC_I2S_SUPPORTS_PDM_TX (1) @@ -217,7 +223,6 @@ #define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1 /*!< TX carrier can be modulated to data phase only */ #define SOC_RMT_SUPPORT_XTAL 1 /*!< Support set XTAL clock as the RMT clock source */ #define SOC_RMT_SUPPORT_AHB 1 /*!< Support set AHB clock as the RMT clock source */ -#define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST clock as the RMT clock source */ /*-------------------------- RTC CAPS --------------------------------------*/ #define SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH (128) @@ -262,6 +267,7 @@ /*-------------------------- SPI CAPS ----------------------------------------*/ #define SOC_SPI_PERIPH_NUM 2 #define SOC_SPI_PERIPH_CS_NUM(i) 6 +#define SOC_SPI_MAX_CS_NUM 6 #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 @@ -334,8 +340,9 @@ #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ -#define SOC_UART_SUPPORT_RTC_CLK (1) -#define SOC_UART_SUPPORT_XTAL_CLK (1) +#define SOC_UART_SUPPORT_AHB_CLK (1) /*!< Support AHB as the clock source */ +#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ +#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) @@ -358,3 +365,8 @@ /*-------------------------- Temperature Sensor CAPS -------------------------------------*/ #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1) #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1) + +/*---------------------------------- Bluetooth CAPS ----------------------------------*/ +#define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */ +#define SOC_BLE_MESH_SUPPORTED (1) /*!< Support BLE MESH */ +#define SOC_ESP_NIMBLE_CONTROLLER (1) /*!< Support BLE EMBEDDED controller V1 */ diff --git a/components/soc/esp32h2/spi_periph.c b/components/soc/esp32h2/spi_periph.c index a7c656288b..ce1c5c9af9 100644 --- a/components/soc/esp32h2/spi_periph.c +++ b/components/soc/esp32h2/spi_periph.c @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include "soc/spi_periph.h" #include "stddef.h" @@ -54,7 +46,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .spiq_in = FSPIQ_IN_IDX, .spiwp_in = FSPIWP_IN_IDX, .spihd_in = FSPIHD_IN_IDX, - .spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX}, + .spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX, FSPICS3_OUT_IDX, FSPICS4_OUT_IDX, FSPICS5_OUT_IDX}, .spics_in = FSPICS0_IN_IDX, .spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK, .spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI, diff --git a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in index aa1161a6c4..b1970101cc 100644 --- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in @@ -99,6 +99,14 @@ config SOC_SDM_SUPPORTED bool default y +config SOC_LEDC_SUPPORTED + bool + default y + +config SOC_I2C_SUPPORTED + bool + default y + config SOC_SYSTIMER_SUPPORTED bool default y @@ -235,6 +243,10 @@ config SOC_BROWNOUT_RESET_SUPPORTED bool default y +config SOC_MMU_LINEAR_ADDRESS_REGION_NUM + int + default 6 + config SOC_CP_DMA_MAX_BUFFER_SIZE int default 4095 @@ -287,6 +299,10 @@ config SOC_GPIO_VALID_GPIO_MASK hex default 0x7FFFFFFFFFFF +config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK + hex + default 0x00007FFFFC000000 + config SOC_GPIO_SUPPORT_SLP_SWITCH bool default y @@ -555,6 +571,10 @@ config SOC_SPI_DMA_CHAN_NUM int default 3 +config SOC_SPI_MAX_CS_NUM + int + default 6 + config SOC_SPI_MAXIMUM_BUFFER_SIZE int default 72 @@ -691,6 +711,10 @@ config SOC_UART_SUPPORT_WAKEUP_INT bool default y +config SOC_UART_SUPPORT_APB_CLK + bool + default y + config SOC_UART_SUPPORT_REF_TICK bool default y diff --git a/components/soc/esp32s2/include/soc/ext_mem_defs.h b/components/soc/esp32s2/include/soc/ext_mem_defs.h index de20e102d1..b5554d503c 100644 --- a/components/soc/esp32s2/include/soc/ext_mem_defs.h +++ b/components/soc/esp32s2/include/soc/ext_mem_defs.h @@ -137,6 +137,39 @@ extern "C" { #define CACHE_MEMORY_BANK2_ADDR 0x3FFB4000 #define CACHE_MEMORY_BANK3_ADDR 0x3FFB6000 + +#define SOC_MMU_DBUS_VADDR_BASE 0x3E000000 +#define SOC_MMU_IBUS_VADDR_BASE 0x40000000 + +/*------------------------------------------------------------------------------ + * MMU Linear Address + *----------------------------------------------------------------------------*/ +/** + * - 64KB MMU page size: the last 0xFFFF, which is the offset + * - 384 MMU entries, needs 0x1FF to hold it. + * + * Therefore, 0x1FF,FFFF + */ +#define SOC_MMU_LINEAR_ADDR_MASK 0x1FFFFFF + +#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) +#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) + +#define SOC_MMU_IRAM1_LINEAR_ADDRESS_LOW (IRAM1_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) +#define SOC_MMU_IRAM1_LINEAR_ADDRESS_HIGH (IRAM1_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) + +#define SOC_MMU_DROM0_LINEAR_ADDRESS_LOW (DROM0_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) +#define SOC_MMU_DROM0_LINEAR_ADDRESS_HIGH (DROM0_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) + +#define SOC_MMU_DPORT_LINEAR_ADDRESS_LOW (DPORT_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) +#define SOC_MMU_DPORT_LINEAR_ADDRESS_HIGH (DPORT_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) + +#define SOC_MMU_DRAM1_LINEAR_ADDRESS_LOW (DRAM1_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) +#define SOC_MMU_DRAM1_LINEAR_ADDRESS_HIGH (DRAM1_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) + +#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) +#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s2/include/soc/hwcrypto_reg.h b/components/soc/esp32s2/include/soc/hwcrypto_reg.h index 96a6f98ee4..7206472425 100644 --- a/components/soc/esp32s2/include/soc/hwcrypto_reg.h +++ b/components/soc/esp32s2/include/soc/hwcrypto_reg.h @@ -1,16 +1,9 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. #ifndef __HWCRYPTO_REG_H__ #define __HWCRYPTO_REG_H__ @@ -102,11 +95,6 @@ #define AES_J_BASE ((DR_REG_AES_BASE) + 0x70) #define AES_T_BASE ((DR_REG_AES_BASE) + 0x80) -#define AES_INT_CLR_REG ((DR_REG_AES_BASE) + 0xAC) -#define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0) -#define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4) -#define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8) - /* AES_STATE_REG values */ #define AES_STATE_IDLE 0 #define AES_STATE_BUSY 1 diff --git a/components/soc/esp32s2/include/soc/rtc.h b/components/soc/esp32s2/include/soc/rtc.h index d87ef3951f..35b75e9ecb 100644 --- a/components/soc/esp32s2/include/soc/rtc.h +++ b/components/soc/esp32s2/include/soc/rtc.h @@ -455,6 +455,11 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles, ui * 32k XTAL is being calibrated, but the oscillator has not started up (due to * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board). * + * @note When 32k CLK is being calibrated, this function will check the accuracy + * of the clock. Since the xtal 32k or ext osc 32k is generally very stable, if + * the check fails, then consider this an invalid 32k clock and return 0. This + * check can filter some jamming signal. + * * @param cal_clk clock to be measured * @param slow_clk_cycles number of slow clock cycles to average * @return average slow clock period in microseconds, Q13.19 fixed point format, diff --git a/components/soc/esp32s2/include/soc/rtc_i2c_struct.h b/components/soc/esp32s2/include/soc/rtc_i2c_struct.h index 5831bd5ca2..edec99145e 100644 --- a/components/soc/esp32s2/include/soc/rtc_i2c_struct.h +++ b/components/soc/esp32s2/include/soc/rtc_i2c_struct.h @@ -166,9 +166,13 @@ typedef volatile struct rtc_i2c_dev_s { } fifo_data; union { struct { - uint32_t command0: 14; /*command0*/ + uint32_t byte_num: 8; + uint32_t ack_en: 1; + uint32_t ack_exp: 1; + uint32_t ack_val: 1; + uint32_t op_code: 3; uint32_t reserved14: 17; - uint32_t done: 1; /*command0_done*/ + uint32_t done: 1; }; uint32_t val; } command[16]; diff --git a/components/soc/esp32s2/include/soc/soc.h b/components/soc/esp32s2/include/soc/soc.h index ceebf485e4..560c3ac101 100644 --- a/components/soc/esp32s2/include/soc/soc.h +++ b/components/soc/esp32s2/include/soc/soc.h @@ -265,3 +265,6 @@ //Invalid interrupt for number interrupt matrix #define ETS_INVALID_INUM 6 + +// Interrupt number for the Interrupt watchdog +#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM) diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index 5bdc088149..aefedba59d 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -63,6 +63,8 @@ #define SOC_I2S_SUPPORTED 1 #define SOC_RMT_SUPPORTED 1 #define SOC_SDM_SUPPORTED 1 +#define SOC_LEDC_SUPPORTED 1 +#define SOC_I2C_SUPPORTED 1 #define SOC_SYSTIMER_SUPPORTED 1 #define SOC_SUPPORT_COEXISTENCE 0 #define SOC_AES_SUPPORTED 1 @@ -113,6 +115,9 @@ /*-------------------------- BROWNOUT CAPS -----------------------------------*/ #define SOC_BROWNOUT_RESET_SUPPORTED 1 +/*-------------------------- CACHE/MMU CAPS ----------------------------------*/ +#define SOC_MMU_LINEAR_ADDRESS_REGION_NUM 6 + /*-------------------------- CP-DMA CAPS -------------------------------------*/ #define SOC_CP_DMA_MAX_BUFFER_SIZE (4095) /*!< Maximum size of the buffer that can be attached to descriptor */ @@ -144,6 +149,9 @@ // GPIO 46 is input only #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46)) +// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_26~GPIO_NUM_46) +#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00007FFFFC000000ULL + // Support to configure slept status #define SOC_GPIO_SUPPORT_SLP_SWITCH (1) @@ -248,6 +256,7 @@ #define SOC_SPI_PERIPH_NUM 3 #define SOC_SPI_DMA_CHAN_NUM 3 #define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3)) +#define SOC_SPI_MAX_CS_NUM 6 #define SOC_SPI_MAXIMUM_BUFFER_SIZE 72 #define SOC_SPI_MAX_PRE_DIVIDER 8192 @@ -292,7 +301,7 @@ /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/ #define SOC_TOUCH_VERSION_2 (1) /*! 0) +#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) +#else +#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1) +#endif + +#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) +#if ((DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0) +#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) +#else +#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1) +#endif + +/** + * I/D share the MMU linear address range + */ +_Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same"); + + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s3/include/soc/hwcrypto_reg.h b/components/soc/esp32s3/include/soc/hwcrypto_reg.h index a4b93fb81b..adc5ce5bac 100644 --- a/components/soc/esp32s3/include/soc/hwcrypto_reg.h +++ b/components/soc/esp32s3/include/soc/hwcrypto_reg.h @@ -70,7 +70,7 @@ #define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98) #define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C) #define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8) -#define AES_INT_CLR_REG ((DR_REG_AES_BASE) + 0xAC) +#define AES_INT_CLEAR_REG ((DR_REG_AES_BASE) + 0xAC) #define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0) #define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4) #define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8) diff --git a/components/soc/esp32s3/include/soc/i2s_struct.h b/components/soc/esp32s3/include/soc/i2s_struct.h index 587011c4b6..b048961085 100644 --- a/components/soc/esp32s3/include/soc/i2s_struct.h +++ b/components/soc/esp32s3/include/soc/i2s_struct.h @@ -142,7 +142,7 @@ typedef volatile struct i2s_dev_s { uint32_t rx_clkm_div_num : 8; /*Integral I2S clock divider value*/ uint32_t reserved8 : 18; /* Reserved*/ uint32_t rx_clk_active : 1; /*I2S Rx module clock enable signal.*/ - uint32_t rx_clk_sel : 2; /*Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/ + uint32_t rx_clk_sel : 2; /*Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/ uint32_t mclk_sel : 1; /* 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT. */ uint32_t reserved30 : 2; /* Reserved*/ }; @@ -153,7 +153,7 @@ typedef volatile struct i2s_dev_s { uint32_t tx_clkm_div_num : 8; /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. */ uint32_t reserved8 : 18; /* Reserved*/ uint32_t tx_clk_active : 1; /*I2S Tx module clock enable signal.*/ - uint32_t tx_clk_sel : 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/ + uint32_t tx_clk_sel : 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/ uint32_t clk_en : 1; /*Set this bit to enable clk gate*/ uint32_t reserved30 : 2; /* Reserved*/ }; diff --git a/components/soc/esp32s3/include/soc/interrupt_reg.h b/components/soc/esp32s3/include/soc/interrupt_reg.h index b5cdc9cbc5..df8e7fdb66 100644 --- a/components/soc/esp32s3/include/soc/interrupt_reg.h +++ b/components/soc/esp32s3/include/soc/interrupt_reg.h @@ -1,22 +1,16 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + #ifndef _SOC_INTERRUPT_REG_H_ #define _SOC_INTERRUPT_REG_H_ -#include "interrupt_core0_reg.h" -#include "interrupt_core1_reg.h" +#include "soc/interrupt_core0_reg.h" +#include "soc/interrupt_core1_reg.h" #include "soc.h" + #ifdef __cplusplus extern "C" { #endif diff --git a/components/soc/esp32s3/include/soc/periph_defs.h b/components/soc/esp32s3/include/soc/periph_defs.h index 78510ca83f..0d16f7fda7 100644 --- a/components/soc/esp32s3/include/soc/periph_defs.h +++ b/components/soc/esp32s3/include/soc/periph_defs.h @@ -151,7 +151,7 @@ typedef enum { ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHE_CORE1_ACS_INTR_SOURCE, ETS_USB_SERIAL_JTAG_INTR_SOURCE, - ETS_PREI_BACKUP_INTR_SOURCE, + ETS_PERI_BACKUP_INTR_SOURCE, ETS_DMA_EXTMEM_REJECT_SOURCE, ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */ } periph_interrput_t; diff --git a/components/soc/esp32s3/include/soc/reg_base.h b/components/soc/esp32s3/include/soc/reg_base.h index 9beea9fde3..ad1b7d143a 100644 --- a/components/soc/esp32s3/include/soc/reg_base.h +++ b/components/soc/esp32s3/include/soc/reg_base.h @@ -61,4 +61,4 @@ #define DR_REG_INTERRUPT_BASE 0x600C2000 #define DR_REG_EXTMEM_BASE 0x600C4000 #define DR_REG_ASSIST_DEBUG_BASE 0x600CE000 -#define DR_REG_WORLD_CNTL_BASE 0x600D0000 +#define DR_REG_WCL_BASE 0x600D0000 diff --git a/components/soc/esp32s3/include/soc/rtc.h b/components/soc/esp32s3/include/soc/rtc.h index a67396f1c8..fab75b0439 100644 --- a/components/soc/esp32s3/include/soc/rtc.h +++ b/components/soc/esp32s3/include/soc/rtc.h @@ -126,6 +126,22 @@ set sleep_init default param #define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 0xf +/* +The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value +storing in efuse +*/ +#define K_RTC_MID_MUL10000 198 +#define K_DIG_MID_MUL10000 211 +#define V_RTC_MID_MUL10000 10181 +#define V_DIG_MID_MUL10000 10841 + +/* +set LDO slave during CPU switch +*/ +#define DEFAULT_LDO_SLAVE 0x7 + + + /** * @brief Possible main XTAL frequency values. * @@ -439,6 +455,11 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles); * 32k XTAL is being calibrated, but the oscillator has not started up (due to * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board). * + * @note When 32k CLK is being calibrated, this function will check the accuracy + * of the clock. Since the xtal 32k or ext osc 32k is generally very stable, if + * the check fails, then consider this an invalid 32k clock and return 0. This + * check can filter some jamming signal. + * * @param cal_clk clock to be measured * @param slow_clk_cycles number of slow clock cycles to average * @return average slow clock period in microseconds, Q13.19 fixed point format, diff --git a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h b/components/soc/esp32s3/include/soc/rtc_cntl_reg.h index 19cdfeb234..48927f3d53 100644 --- a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32s3/include/soc/rtc_cntl_reg.h @@ -3683,6 +3683,9 @@ ork.*/ #define RTC_CNTL_DISABLE_RTC_CPU_V 0x1 #define RTC_CNTL_DISABLE_RTC_CPU_S 31 +/* +Due to the LDO slaves, RTC_CNTL_DATE_REG[18:13] can only be used for LDO adjustment. +*/ #define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x1FC) /* RTC_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101271 ; */ /*description: .*/ @@ -3690,7 +3693,12 @@ ork.*/ #define RTC_CNTL_DATE_M ((RTC_CNTL_DATE_V)<<(RTC_CNTL_DATE_S)) #define RTC_CNTL_DATE_V 0xFFFFFFF #define RTC_CNTL_DATE_S 0 - +/*LDO SLAVE : R/W ;bitpos:[18:13] ; default: 6'd0 ;*/ +/*description: .*/ +#define RTC_CNTL_SLAVE_PD 0x0000003F +#define RTC_CNTL_SLAVE_PD_M ((RTC_CNTL_SLAVE_V)<<(RTC_CNTL_SLAVE_S)) +#define RTC_CNTL_SLAVE_PD_V 0x3F +#define RTC_CNTL_SLAVE_PD_S 13 #ifdef __cplusplus } diff --git a/components/soc/esp32s3/include/soc/rtc_i2c_reg.h b/components/soc/esp32s3/include/soc/rtc_i2c_reg.h index 3c065af259..322f28192e 100644 --- a/components/soc/esp32s3/include/soc/rtc_i2c_reg.h +++ b/components/soc/esp32s3/include/soc/rtc_i2c_reg.h @@ -23,7 +23,7 @@ extern "C" { /** RTC_I2C_SCL_LOW_REG register * configure low scl period */ -#define RTC_I2C_SCL_LOW_REG (DR_REG_RTC_BASE + 0x0) +#define RTC_I2C_SCL_LOW_REG (DR_REG_RTC_I2C_BASE + 0x0) /** RTC_I2C_SCL_LOW_PERIOD_REG : R/W; bitpos: [19:0]; default: 256; * time period that scl =0 */ @@ -35,7 +35,7 @@ extern "C" { /** RTC_I2C_CTRL_REG register * configure i2c ctrl */ -#define RTC_I2C_CTRL_REG (DR_REG_RTC_BASE + 0x4) +#define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x4) /** RTC_I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0; * 1=push pull,0=open drain */ @@ -103,7 +103,7 @@ extern "C" { /** RTC_I2C_STATUS_REG register * get i2c status */ -#define RTC_I2C_STATUS_REG (DR_REG_RTC_BASE + 0x8) +#define RTC_I2C_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x8) /** RTC_I2C_ACK_REC : RO; bitpos: [0]; default: 0; * ack response */ @@ -178,7 +178,7 @@ extern "C" { /** RTC_I2C_TO_REG register * configure time out */ -#define RTC_I2C_TO_REG (DR_REG_RTC_BASE + 0xc) +#define RTC_I2C_TO_REG (DR_REG_RTC_I2C_BASE + 0xc) /** RTC_I2C_TIME_OUT_REG : R/W; bitpos: [19:0]; default: 65536; * time out threshold */ @@ -190,7 +190,7 @@ extern "C" { /** RTC_I2C_SLAVE_ADDR_REG register * configure slave id */ -#define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_BASE + 0x10) +#define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x10) /** RTC_I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0; * slave address */ @@ -209,7 +209,7 @@ extern "C" { /** RTC_I2C_SCL_HIGH_REG register * configure high scl period */ -#define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_BASE + 0x14) +#define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_I2C_BASE + 0x14) /** RTC_I2C_SCL_HIGH_PERIOD_REG : R/W; bitpos: [19:0]; default: 256; * time period that scl = 1 */ @@ -221,7 +221,7 @@ extern "C" { /** RTC_I2C_SDA_DUTY_REG register * configure sda duty */ -#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_BASE + 0x18) +#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x18) /** RTC_I2C_SDA_DUTY_NUM : R/W; bitpos: [19:0]; default: 16; * time period for SDA to toggle after SCL goes low */ @@ -233,7 +233,7 @@ extern "C" { /** RTC_I2C_SCL_START_PERIOD_REG register * configure scl start period */ -#define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_BASE + 0x1c) +#define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x1c) /** RTC_I2C_SCL_START_PERIOD : R/W; bitpos: [19:0]; default: 8; * time period for SCL to toggle after I2C start is triggered */ @@ -245,7 +245,7 @@ extern "C" { /** RTC_I2C_SCL_STOP_PERIOD_REG register * configure scl stop period */ -#define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_BASE + 0x20) +#define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x20) /** RTC_I2C_SCL_STOP_PERIOD : R/W; bitpos: [19:0]; default: 8; * time period for SCL to stop after I2C end is triggered */ @@ -257,7 +257,7 @@ extern "C" { /** RTC_I2C_INT_CLR_REG register * interrupt clear register */ -#define RTC_I2C_INT_CLR_REG (DR_REG_RTC_BASE + 0x24) +#define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x24) /** RTC_I2C_SLAVE_TRAN_COMP_INT_CLR : WO; bitpos: [0]; default: 0; * clear slave transit complete interrupt */ @@ -325,7 +325,7 @@ extern "C" { /** RTC_I2C_INT_RAW_REG register * interrupt raw register */ -#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_BASE + 0x28) +#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x28) /** RTC_I2C_SLAVE_TRAN_COMP_INT_RAW : RO; bitpos: [0]; default: 0; * slave transit complete interrupt raw */ @@ -393,7 +393,7 @@ extern "C" { /** RTC_I2C_INT_ST_REG register * interrupt state register */ -#define RTC_I2C_INT_ST_REG (DR_REG_RTC_BASE + 0x2c) +#define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x2c) /** RTC_I2C_SLAVE_TRAN_COMP_INT_ST : RO; bitpos: [0]; default: 0; * slave transit complete interrupt state */ @@ -461,7 +461,7 @@ extern "C" { /** RTC_I2C_INT_ENA_REG register * interrupt enable register */ -#define RTC_I2C_INT_ENA_REG (DR_REG_RTC_BASE + 0x30) +#define RTC_I2C_INT_ENA_REG (DR_REG_RTC_I2C_BASE + 0x30) /** RTC_I2C_SLAVE_TRAN_COMP_INT_ENA : R/W; bitpos: [0]; default: 0; * enable slave transit complete interrupt */ @@ -529,7 +529,7 @@ extern "C" { /** RTC_I2C_DATA_REG register * get i2c data status */ -#define RTC_I2C_DATA_REG (DR_REG_RTC_BASE + 0x34) +#define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x34) /** RTC_I2C_I2C_RDATA : RO; bitpos: [7:0]; default: 0; * data received */ @@ -555,7 +555,7 @@ extern "C" { /** RTC_I2C_CMD0_REG register * i2c commond0 register */ -#define RTC_I2C_CMD0_REG (DR_REG_RTC_BASE + 0x38) +#define RTC_I2C_CMD0_REG (DR_REG_RTC_I2C_BASE + 0x38) /** RTC_I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 2307; * command0 */ @@ -574,7 +574,7 @@ extern "C" { /** RTC_I2C_CMD1_REG register * i2c commond1 register */ -#define RTC_I2C_CMD1_REG (DR_REG_RTC_BASE + 0x3c) +#define RTC_I2C_CMD1_REG (DR_REG_RTC_I2C_BASE + 0x3c) /** RTC_I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 6401; * command1 */ @@ -593,7 +593,7 @@ extern "C" { /** RTC_I2C_CMD2_REG register * i2c commond2 register */ -#define RTC_I2C_CMD2_REG (DR_REG_RTC_BASE + 0x40) +#define RTC_I2C_CMD2_REG (DR_REG_RTC_I2C_BASE + 0x40) /** RTC_I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 2306; * command2 */ @@ -612,7 +612,7 @@ extern "C" { /** RTC_I2C_CMD3_REG register * i2c commond3 register */ -#define RTC_I2C_CMD3_REG (DR_REG_RTC_BASE + 0x44) +#define RTC_I2C_CMD3_REG (DR_REG_RTC_I2C_BASE + 0x44) /** RTC_I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 257; * command3 */ @@ -631,7 +631,7 @@ extern "C" { /** RTC_I2C_CMD4_REG register * i2c commond4 register */ -#define RTC_I2C_CMD4_REG (DR_REG_RTC_BASE + 0x48) +#define RTC_I2C_CMD4_REG (DR_REG_RTC_I2C_BASE + 0x48) /** RTC_I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 2305; * command4 */ @@ -650,7 +650,7 @@ extern "C" { /** RTC_I2C_CMD5_REG register * i2c commond5_register */ -#define RTC_I2C_CMD5_REG (DR_REG_RTC_BASE + 0x4c) +#define RTC_I2C_CMD5_REG (DR_REG_RTC_I2C_BASE + 0x4c) /** RTC_I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 5889; * command5 */ @@ -669,7 +669,7 @@ extern "C" { /** RTC_I2C_CMD6_REG register * i2c commond6 register */ -#define RTC_I2C_CMD6_REG (DR_REG_RTC_BASE + 0x50) +#define RTC_I2C_CMD6_REG (DR_REG_RTC_I2C_BASE + 0x50) /** RTC_I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 6401; * command6 */ @@ -688,7 +688,7 @@ extern "C" { /** RTC_I2C_CMD7_REG register * i2c commond7 register */ -#define RTC_I2C_CMD7_REG (DR_REG_RTC_BASE + 0x54) +#define RTC_I2C_CMD7_REG (DR_REG_RTC_I2C_BASE + 0x54) /** RTC_I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 2308; * command7 */ @@ -707,7 +707,7 @@ extern "C" { /** RTC_I2C_CMD8_REG register * i2c commond8 register */ -#define RTC_I2C_CMD8_REG (DR_REG_RTC_BASE + 0x58) +#define RTC_I2C_CMD8_REG (DR_REG_RTC_I2C_BASE + 0x58) /** RTC_I2C_COMMAND8 : R/W; bitpos: [13:0]; default: 6401; * command8 */ @@ -726,7 +726,7 @@ extern "C" { /** RTC_I2C_CMD9_REG register * i2c commond9 register */ -#define RTC_I2C_CMD9_REG (DR_REG_RTC_BASE + 0x5c) +#define RTC_I2C_CMD9_REG (DR_REG_RTC_I2C_BASE + 0x5c) /** RTC_I2C_COMMAND9 : R/W; bitpos: [13:0]; default: 2307; * command9 */ @@ -745,7 +745,7 @@ extern "C" { /** RTC_I2C_CMD10_REG register * i2c commond10 register */ -#define RTC_I2C_CMD10_REG (DR_REG_RTC_BASE + 0x60) +#define RTC_I2C_CMD10_REG (DR_REG_RTC_I2C_BASE + 0x60) /** RTC_I2C_COMMAND10 : R/W; bitpos: [13:0]; default: 257; * command10 */ @@ -764,7 +764,7 @@ extern "C" { /** RTC_I2C_CMD11_REG register * i2c commond11 register */ -#define RTC_I2C_CMD11_REG (DR_REG_RTC_BASE + 0x64) +#define RTC_I2C_CMD11_REG (DR_REG_RTC_I2C_BASE + 0x64) /** RTC_I2C_COMMAND11 : R/W; bitpos: [13:0]; default: 2305; * command11 */ @@ -783,7 +783,7 @@ extern "C" { /** RTC_I2C_CMD12_REG register * i2c commond12 register */ -#define RTC_I2C_CMD12_REG (DR_REG_RTC_BASE + 0x68) +#define RTC_I2C_CMD12_REG (DR_REG_RTC_I2C_BASE + 0x68) /** RTC_I2C_COMMAND12 : R/W; bitpos: [13:0]; default: 5889; * command12 */ @@ -802,7 +802,7 @@ extern "C" { /** RTC_I2C_CMD13_REG register * i2c commond13 register */ -#define RTC_I2C_CMD13_REG (DR_REG_RTC_BASE + 0x6c) +#define RTC_I2C_CMD13_REG (DR_REG_RTC_I2C_BASE + 0x6c) /** RTC_I2C_COMMAND13 : R/W; bitpos: [13:0]; default: 6401; * command13 */ @@ -821,7 +821,7 @@ extern "C" { /** RTC_I2C_CMD14_REG register * i2c commond14 register */ -#define RTC_I2C_CMD14_REG (DR_REG_RTC_BASE + 0x70) +#define RTC_I2C_CMD14_REG (DR_REG_RTC_I2C_BASE + 0x70) /** RTC_I2C_COMMAND14 : R/W; bitpos: [13:0]; default: 0; * command14 */ @@ -840,7 +840,7 @@ extern "C" { /** RTC_I2C_CMD15_REG register * i2c commond15 register */ -#define RTC_I2C_CMD15_REG (DR_REG_RTC_BASE + 0x74) +#define RTC_I2C_CMD15_REG (DR_REG_RTC_I2C_BASE + 0x74) /** RTC_I2C_COMMAND15 : R/W; bitpos: [13:0]; default: 0; * command15 */ @@ -859,7 +859,7 @@ extern "C" { /** RTC_I2C_DATE_REG register * version register */ -#define RTC_I2C_DATE_REG (DR_REG_RTC_BASE + 0xfc) +#define RTC_I2C_DATE_REG (DR_REG_RTC_I2C_BASE + 0xfc) /** RTC_I2C_I2C_DATE : R/W; bitpos: [27:0]; default: 26235664; * version */ diff --git a/components/soc/esp32s3/include/soc/rtc_i2c_struct.h b/components/soc/esp32s3/include/soc/rtc_i2c_struct.h index 8641683f16..2bac2fa580 100644 --- a/components/soc/esp32s3/include/soc/rtc_i2c_struct.h +++ b/components/soc/esp32s3/include/soc/rtc_i2c_struct.h @@ -190,294 +190,27 @@ typedef union { uint32_t val; } rtc_i2c_data_reg_t; -/** Type of i2c_cmd0 register - * i2c commond0 register +/** Type of i2c_cmd register + * i2c command register */ typedef union { struct { - /** i2c_command0 : R/W; bitpos: [13:0]; default: 2307; - * command0 + /** i2c_command : R/W; bitpos: [13:0]; default: 2307; + * command */ - uint32_t i2c_command0:14; - uint32_t reserved_14:17; - /** i2c_command0_done : RO; bitpos: [31]; default: 0; + uint32_t i2c_byte_num:8; + uint32_t i2c_ack_en:1; + uint32_t i2c_ack_exp:1; + uint32_t i2c_ack_val:1; + uint32_t i2c_op_code:3; + uint32_t reserved14:17; + /** i2c_command_done : RO; bitpos: [31]; default: 0; * command0_done */ - uint32_t i2c_command0_done:1; + uint32_t i2c_command_done:1; }; uint32_t val; -} rtc_i2c_cmd0_reg_t; - -/** Type of i2c_cmd1 register - * i2c commond1 register - */ -typedef union { - struct { - /** i2c_command1 : R/W; bitpos: [13:0]; default: 6401; - * command1 - */ - uint32_t i2c_command1:14; - uint32_t reserved_14:17; - /** i2c_command1_done : RO; bitpos: [31]; default: 0; - * command1_done - */ - uint32_t i2c_command1_done:1; - }; - uint32_t val; -} rtc_i2c_cmd1_reg_t; - -/** Type of i2c_cmd2 register - * i2c commond2 register - */ -typedef union { - struct { - /** i2c_command2 : R/W; bitpos: [13:0]; default: 2306; - * command2 - */ - uint32_t i2c_command2:14; - uint32_t reserved_14:17; - /** i2c_command2_done : RO; bitpos: [31]; default: 0; - * command2_done - */ - uint32_t i2c_command2_done:1; - }; - uint32_t val; -} rtc_i2c_cmd2_reg_t; - -/** Type of i2c_cmd3 register - * i2c commond3 register - */ -typedef union { - struct { - /** i2c_command3 : R/W; bitpos: [13:0]; default: 257; - * command3 - */ - uint32_t i2c_command3:14; - uint32_t reserved_14:17; - /** i2c_command3_done : RO; bitpos: [31]; default: 0; - * command3_done - */ - uint32_t i2c_command3_done:1; - }; - uint32_t val; -} rtc_i2c_cmd3_reg_t; - -/** Type of i2c_cmd4 register - * i2c commond4 register - */ -typedef union { - struct { - /** i2c_command4 : R/W; bitpos: [13:0]; default: 2305; - * command4 - */ - uint32_t i2c_command4:14; - uint32_t reserved_14:17; - /** i2c_command4_done : RO; bitpos: [31]; default: 0; - * command4_done - */ - uint32_t i2c_command4_done:1; - }; - uint32_t val; -} rtc_i2c_cmd4_reg_t; - -/** Type of i2c_cmd5 register - * i2c commond5_register - */ -typedef union { - struct { - /** i2c_command5 : R/W; bitpos: [13:0]; default: 5889; - * command5 - */ - uint32_t i2c_command5:14; - uint32_t reserved_14:17; - /** i2c_command5_done : RO; bitpos: [31]; default: 0; - * command5_done - */ - uint32_t i2c_command5_done:1; - }; - uint32_t val; -} rtc_i2c_cmd5_reg_t; - -/** Type of i2c_cmd6 register - * i2c commond6 register - */ -typedef union { - struct { - /** i2c_command6 : R/W; bitpos: [13:0]; default: 6401; - * command6 - */ - uint32_t i2c_command6:14; - uint32_t reserved_14:17; - /** i2c_command6_done : RO; bitpos: [31]; default: 0; - * command6_done - */ - uint32_t i2c_command6_done:1; - }; - uint32_t val; -} rtc_i2c_cmd6_reg_t; - -/** Type of i2c_cmd7 register - * i2c commond7 register - */ -typedef union { - struct { - /** i2c_command7 : R/W; bitpos: [13:0]; default: 2308; - * command7 - */ - uint32_t i2c_command7:14; - uint32_t reserved_14:17; - /** i2c_command7_done : RO; bitpos: [31]; default: 0; - * command7_done - */ - uint32_t i2c_command7_done:1; - }; - uint32_t val; -} rtc_i2c_cmd7_reg_t; - -/** Type of i2c_cmd8 register - * i2c commond8 register - */ -typedef union { - struct { - /** i2c_command8 : R/W; bitpos: [13:0]; default: 6401; - * command8 - */ - uint32_t i2c_command8:14; - uint32_t reserved_14:17; - /** i2c_command8_done : RO; bitpos: [31]; default: 0; - * command8_done - */ - uint32_t i2c_command8_done:1; - }; - uint32_t val; -} rtc_i2c_cmd8_reg_t; - -/** Type of i2c_cmd9 register - * i2c commond9 register - */ -typedef union { - struct { - /** i2c_command9 : R/W; bitpos: [13:0]; default: 2307; - * command9 - */ - uint32_t i2c_command9:14; - uint32_t reserved_14:17; - /** i2c_command9_done : RO; bitpos: [31]; default: 0; - * command9_done - */ - uint32_t i2c_command9_done:1; - }; - uint32_t val; -} rtc_i2c_cmd9_reg_t; - -/** Type of i2c_cmd10 register - * i2c commond10 register - */ -typedef union { - struct { - /** i2c_command10 : R/W; bitpos: [13:0]; default: 257; - * command10 - */ - uint32_t i2c_command10:14; - uint32_t reserved_14:17; - /** i2c_command10_done : RO; bitpos: [31]; default: 0; - * command10_done - */ - uint32_t i2c_command10_done:1; - }; - uint32_t val; -} rtc_i2c_cmd10_reg_t; - -/** Type of i2c_cmd11 register - * i2c commond11 register - */ -typedef union { - struct { - /** i2c_command11 : R/W; bitpos: [13:0]; default: 2305; - * command11 - */ - uint32_t i2c_command11:14; - uint32_t reserved_14:17; - /** i2c_command11_done : RO; bitpos: [31]; default: 0; - * command11_done - */ - uint32_t i2c_command11_done:1; - }; - uint32_t val; -} rtc_i2c_cmd11_reg_t; - -/** Type of i2c_cmd12 register - * i2c commond12 register - */ -typedef union { - struct { - /** i2c_command12 : R/W; bitpos: [13:0]; default: 5889; - * command12 - */ - uint32_t i2c_command12:14; - uint32_t reserved_14:17; - /** i2c_command12_done : RO; bitpos: [31]; default: 0; - * command12_done - */ - uint32_t i2c_command12_done:1; - }; - uint32_t val; -} rtc_i2c_cmd12_reg_t; - -/** Type of i2c_cmd13 register - * i2c commond13 register - */ -typedef union { - struct { - /** i2c_command13 : R/W; bitpos: [13:0]; default: 6401; - * command13 - */ - uint32_t i2c_command13:14; - uint32_t reserved_14:17; - /** i2c_command13_done : RO; bitpos: [31]; default: 0; - * command13_done - */ - uint32_t i2c_command13_done:1; - }; - uint32_t val; -} rtc_i2c_cmd13_reg_t; - -/** Type of i2c_cmd14 register - * i2c commond14 register - */ -typedef union { - struct { - /** i2c_command14 : R/W; bitpos: [13:0]; default: 0; - * command14 - */ - uint32_t i2c_command14:14; - uint32_t reserved_14:17; - /** i2c_command14_done : RO; bitpos: [31]; default: 0; - * command14_done - */ - uint32_t i2c_command14_done:1; - }; - uint32_t val; -} rtc_i2c_cmd14_reg_t; - -/** Type of i2c_cmd15 register - * i2c commond15 register - */ -typedef union { - struct { - /** i2c_command15 : R/W; bitpos: [13:0]; default: 0; - * command15 - */ - uint32_t i2c_command15:14; - uint32_t reserved_14:17; - /** i2c_command15_done : RO; bitpos: [31]; default: 0; - * command15_done - */ - uint32_t i2c_command15_done:1; - }; - uint32_t val; -} rtc_i2c_cmd15_reg_t; - +} rtc_i2c_cmd_reg_t; /** Group: status register */ /** Type of i2c_status register @@ -750,29 +483,15 @@ typedef struct { volatile rtc_i2c_int_st_reg_t i2c_int_st; volatile rtc_i2c_int_ena_reg_t i2c_int_ena; volatile rtc_i2c_data_reg_t i2c_data; - volatile rtc_i2c_cmd0_reg_t i2c_cmd0; - volatile rtc_i2c_cmd1_reg_t i2c_cmd1; - volatile rtc_i2c_cmd2_reg_t i2c_cmd2; - volatile rtc_i2c_cmd3_reg_t i2c_cmd3; - volatile rtc_i2c_cmd4_reg_t i2c_cmd4; - volatile rtc_i2c_cmd5_reg_t i2c_cmd5; - volatile rtc_i2c_cmd6_reg_t i2c_cmd6; - volatile rtc_i2c_cmd7_reg_t i2c_cmd7; - volatile rtc_i2c_cmd8_reg_t i2c_cmd8; - volatile rtc_i2c_cmd9_reg_t i2c_cmd9; - volatile rtc_i2c_cmd10_reg_t i2c_cmd10; - volatile rtc_i2c_cmd11_reg_t i2c_cmd11; - volatile rtc_i2c_cmd12_reg_t i2c_cmd12; - volatile rtc_i2c_cmd13_reg_t i2c_cmd13; - volatile rtc_i2c_cmd14_reg_t i2c_cmd14; - volatile rtc_i2c_cmd15_reg_t i2c_cmd15; + volatile rtc_i2c_cmd_reg_t i2c_cmd[16]; uint32_t reserved_078[33]; volatile rtc_i2c_date_reg_t i2c_date; -} rtc_dev_t; +} rtc_i2c_dev_t; +extern rtc_i2c_dev_t RTC_I2C; #ifndef __cplusplus -_Static_assert(sizeof(rtc_dev_t) == 0x100, "Invalid size of rtc_dev_t structure"); +_Static_assert(sizeof(rtc_i2c_dev_t) == 0x100, "Invalid size of rtc_i2c_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index 0517b54e81..eeb49ac16e 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -287,3 +287,6 @@ //Invalid interrupt for number interrupt matrix #define ETS_INVALID_INUM 6 + +// Interrupt number for the Interrupt watchdog +#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM) diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index f777535268..e635328a5c 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -52,6 +52,8 @@ #define SOC_I2S_SUPPORTED 1 #define SOC_RMT_SUPPORTED 1 #define SOC_SDM_SUPPORTED 1 +#define SOC_LEDC_SUPPORTED 1 +#define SOC_I2C_SUPPORTED 1 #define SOC_SYSTIMER_SUPPORTED 1 #define SOC_SUPPORT_COEXISTENCE 1 #define SOC_TEMP_SENSOR_SUPPORTED 1 @@ -110,6 +112,9 @@ /*-------------------------- BROWNOUT CAPS -----------------------------------*/ #define SOC_BROWNOUT_RESET_SUPPORTED 1 +/*-------------------------- CACHE/MMU CAPS ----------------------------------*/ +#define SOC_MMU_LINEAR_ADDRESS_REGION_NUM (1U) + /*-------------------------- CPU CAPS ----------------------------------------*/ #define SOC_CPU_CORES_NUM 2 #define SOC_CPU_INTR_NUM 32 @@ -150,6 +155,8 @@ #define SOC_GPIO_VALID_GPIO_MASK (0x1FFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25)) // No GPIO is input only #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK) +// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_26~GPIO_NUM_48) +#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0001FFFFFC000000ULL // Support to configure slept status #define SOC_GPIO_SUPPORT_SLP_SWITCH (1) @@ -177,6 +184,7 @@ /*-------------------------- I2S CAPS ----------------------------------------*/ #define SOC_I2S_NUM (2) #define SOC_I2S_HW_VERSION_2 (1) +#define SOC_I2S_SUPPORTS_XTAL (1) #define SOC_I2S_SUPPORTS_PCM (1) #define SOC_I2S_SUPPORTS_PDM (1) #define SOC_I2S_SUPPORTS_PDM_TX (1) @@ -204,7 +212,7 @@ #include "mpu_caps.h" /*-------------------------- PCNT CAPS ---------------------------------------*/ -#define SOC_PCNT_GROUPS (1) +#define SOC_PCNT_GROUPS (1U) #define SOC_PCNT_UNITS_PER_GROUP (4) #define SOC_PCNT_CHANNELS_PER_UNIT (2) #define SOC_PCNT_THRES_POINT_PER_UNIT (2) @@ -235,6 +243,7 @@ #define SOC_LCD_RGB_PANELS (1U) /*!< Support one RGB LCD panel */ #define SOC_LCD_I80_BUS_WIDTH (16) /*!< Intel 8080 bus width */ #define SOC_LCD_RGB_DATA_WIDTH (16) /*!< Number of LCD data lines */ +#define SOC_LCD_SUPPORT_RGB_YUV_CONV (1) /*!< Support color format conversion between RGB and YUV */ /*-------------------------- RTC CAPS --------------------------------------*/ #define SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH (128) @@ -260,7 +269,8 @@ /*-------------------------- SPI CAPS ----------------------------------------*/ #define SOC_SPI_PERIPH_NUM 3 -#define SOC_SPI_PERIPH_CS_NUM(i) 3 +#define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3)) +#define SOC_SPI_MAX_CS_NUM 6 #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 #define SOC_SPI_SUPPORT_DDRCLK 1 #define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 @@ -322,6 +332,7 @@ // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ +#define SOC_UART_SUPPORT_APB_CLK (1) /*!< Support APB as the clock source */ #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ #define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ #define SOC_UART_REQUIRE_CORE_RESET (1) @@ -442,3 +453,7 @@ #define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */ #define SOC_WIFI_CSI_SUPPORT (1) /*!< Support CSI */ #define SOC_WIFI_MESH_SUPPORT (1) /*!< Support WIFI MESH */ + +/*---------------------------------- Bluetooth CAPS ----------------------------------*/ +#define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */ +#define SOC_BLE_MESH_SUPPORTED (1) /*!< Support BLE MESH */ diff --git a/components/soc/esp32s3/include/soc/usbh_struct.h b/components/soc/esp32s3/include/soc/usb_dwc_struct.h similarity index 71% rename from components/soc/esp32s3/include/soc/usbh_struct.h rename to components/soc/esp32s3/include/soc/usb_dwc_struct.h index 3a52bf9952..e2e86bf94f 100644 --- a/components/soc/esp32s3/include/soc/usbh_struct.h +++ b/components/soc/esp32s3/include/soc/usb_dwc_struct.h @@ -1,20 +1,11 @@ -// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once -#include #ifdef __cplusplus extern "C" { #endif @@ -49,7 +40,7 @@ typedef union { uint32_t reserved10: 10; }; uint32_t val; -} usb_gotgctl_reg_t; +} usb_dwc_gotgctl_reg_t; typedef union { struct { @@ -65,7 +56,7 @@ typedef union { uint32_t reserved12: 12; }; uint32_t val; -} usb_gotgint_reg_t; +} usb_dwc_gotgint_reg_t; typedef union { struct { @@ -84,7 +75,7 @@ typedef union { }; uint32_t val; //Checked -} usb_gahbcfg_reg_t; +} usb_dwc_gahbcfg_reg_t; typedef union { struct { @@ -106,7 +97,7 @@ typedef union { uint32_t corrupttxpkt: 1; }; uint32_t val; -} usb_gusbcfg_reg_t; +} usb_dwc_gusbcfg_reg_t; typedef union { struct { @@ -122,7 +113,7 @@ typedef union { uint32_t ahbidle: 1; }; uint32_t val; -} usb_grstctl_reg_t; +} usb_dwc_grstctl_reg_t; typedef union { struct { @@ -159,7 +150,7 @@ typedef union { uint32_t wkupint: 1; }; uint32_t val; -} usb_gintsts_reg_t; +} usb_dwc_gintsts_reg_t; typedef union { struct { @@ -196,7 +187,7 @@ typedef union { uint32_t wkupintmsk: 1; }; uint32_t val; -} usb_gintmsk_reg_t; +} usb_dwc_gintmsk_reg_t; typedef union { struct { @@ -208,7 +199,7 @@ typedef union { uint32_t reserved7: 7; }; uint32_t val; -} usb_grxstsr_reg_t; +} usb_dwc_grxstsr_reg_t; typedef union { struct { @@ -220,7 +211,7 @@ typedef union { uint32_t reserved7: 7; }; uint32_t val; -} usb_grxstsp_reg_t; +} usb_dwc_grxstsp_reg_t; typedef union { struct { @@ -228,7 +219,7 @@ typedef union { uint32_t reserved16: 16; }; uint32_t val; -} usb_grxfsiz_reg_t; +} usb_dwc_grxfsiz_reg_t; typedef union { struct { @@ -236,7 +227,7 @@ typedef union { uint32_t nptxfdep: 16; }; uint32_t val; -} usb_gnptxfsiz_reg_t; +} usb_dwc_gnptxfsiz_reg_t; typedef union { struct { @@ -247,21 +238,21 @@ typedef union { uint32_t reserved1: 1; }; uint32_t val; -} usb_gnptxsts_reg_t; +} usb_dwc_gnptxsts_reg_t; typedef union { struct { uint32_t synopsysid; }; uint32_t val; -} usb_gsnpsid_reg_t; +} usb_dwc_gsnpsid_reg_t; typedef union { struct { uint32_t epdir; }; uint32_t val; -} usb_ghwcfg1_reg_t; +} usb_dwc_ghwcfg1_reg_t; typedef union { struct { @@ -282,7 +273,7 @@ typedef union { uint32_t reserved1b: 1; }; uint32_t val; -} usb_ghwcfg2_reg_t; +} usb_dwc_ghwcfg2_reg_t; typedef union { struct { @@ -300,7 +291,7 @@ typedef union { uint32_t dfifodepth: 16; }; uint32_t val; -} usb_ghwcfg3_reg_t; +} usb_dwc_ghwcfg3_reg_t; typedef union { struct { @@ -325,7 +316,7 @@ typedef union { uint32_t g_descdma: 1; }; uint32_t val; -} usb_ghwcfg4_reg_t; +} usb_dwc_ghwcfg4_reg_t; typedef union { struct { @@ -334,7 +325,7 @@ typedef union { }; uint32_t val; -} usb_gdfifocfg_reg_t; +} usb_dwc_gdfifocfg_reg_t; typedef union { struct { @@ -342,7 +333,7 @@ typedef union { uint32_t ptxfsize: 16; }; uint32_t val; -} usb_hptxfsiz_reg_t; +} usb_dwc_hptxfsiz_reg_t; typedef union { struct { @@ -350,7 +341,7 @@ typedef union { uint32_t inep1txfdep: 16; }; uint32_t val; -} usb_dieptxfi_reg_t; +} usb_dwc_dieptxfi_reg_t; typedef union { struct { @@ -368,7 +359,7 @@ typedef union { uint32_t modechtimen: 1; }; uint32_t val; -} usb_hcfg_reg_t; +} usb_dwc_hcfg_reg_t; typedef union { struct { @@ -377,7 +368,7 @@ typedef union { uint32_t reserved15: 15; }; uint32_t val; -} usb_hfir_reg_t; +} usb_dwc_hfir_reg_t; typedef union { struct { @@ -386,7 +377,7 @@ typedef union { uint32_t frrem: 16; }; uint32_t val; -} usb_hfnum_reg_t; +} usb_dwc_hfnum_reg_t; typedef union { struct { @@ -396,7 +387,7 @@ typedef union { uint32_t ptxqtop: 8; }; uint32_t val; -} usb_hptxsts_reg_t; +} usb_dwc_hptxsts_reg_t; typedef union { struct { @@ -404,7 +395,7 @@ typedef union { uint32_t reserved24: 24; }; uint32_t val; -} usb_haint_reg_t; +} usb_dwc_haint_reg_t; typedef union { struct { @@ -412,14 +403,14 @@ typedef union { uint32_t reserved24: 24; }; uint32_t val; -} usb_haintmsk_reg_t; +} usb_dwc_haintmsk_reg_t; typedef union { struct { uint32_t hflbaddr; }; uint32_t val; -} usb_hflbaddr_reg_t; +} usb_dwc_hflbaddr_reg_t; typedef union { struct { @@ -440,7 +431,7 @@ typedef union { uint32_t reserved13: 13; }; uint32_t val; -} usb_hprt_reg_t; +} usb_dwc_hprt_reg_t; typedef union { struct { @@ -457,8 +448,7 @@ typedef union { uint32_t chena: 1; }; uint32_t val; - //Checked with changes -} usb_hcchar_reg_t; +} usb_dwc_hcchar_reg_t; typedef union { struct { @@ -479,8 +469,7 @@ typedef union { uint32_t reserved18: 18; }; uint32_t val; - //Checked -} usb_hcint_reg_t; +} usb_dwc_hcint_reg_t; typedef union { struct { @@ -501,8 +490,7 @@ typedef union { uint32_t reserved18: 18; }; uint32_t val; - //Checked -} usb_hcintmsk_reg_t; +} usb_dwc_hcintmsk_reg_t; typedef union { struct { @@ -514,8 +502,7 @@ typedef union { uint32_t dopng: 1; }; uint32_t val; - //Checked -} usb_hctsiz_reg_t; +} usb_dwc_hctsiz_reg_t; typedef union { struct { @@ -528,15 +515,14 @@ typedef union { uint32_t dmaaddr_ctd: 29; } iso; uint32_t val; - //Checked -} usb_hcdma_reg_t; +} usb_dwc_hcdma_reg_t; typedef union { struct { uint32_t hcdmab; }; uint32_t val; -} usb_hcdmab_reg_t; +} usb_dwc_hcdmab_reg_t; typedef union { struct { @@ -555,7 +541,7 @@ typedef union { uint32_t resvalid: 6; }; uint32_t val; -} usb_dcfg_reg_t; +} usb_dwc_dcfg_reg_t; typedef union { struct { @@ -578,7 +564,7 @@ typedef union { uint32_t reserved3: 13; }; uint32_t val; -} usb_dctl_reg_t; +} usb_dwc_dctl_reg_t; typedef union { struct { @@ -591,7 +577,7 @@ typedef union { uint32_t reserved8: 8; }; uint32_t val; -} usb_dsts_reg_t; +} usb_dwc_dsts_reg_t; typedef union { struct { @@ -610,7 +596,7 @@ typedef union { uint32_t reserved18: 18; }; uint32_t val; -} usb_diepmsk_reg_t; +} usb_dwc_diepmsk_reg_t; typedef union { struct { @@ -631,7 +617,7 @@ typedef union { uint32_t reserved17: 17; }; uint32_t val; -} usb_doepmsk_reg_t; +} usb_dwc_doepmsk_reg_t; typedef union { struct { @@ -653,7 +639,7 @@ typedef union { uint32_t reserved9b: 9; }; uint32_t val; -} usb_daint_reg_t; +} usb_dwc_daint_reg_t; typedef union { struct { @@ -675,7 +661,7 @@ typedef union { uint32_t reserved9b: 9; }; uint32_t val; -} usb_daintmsk_reg_t; +} usb_dwc_daintmsk_reg_t; typedef union { struct { @@ -683,7 +669,7 @@ typedef union { uint32_t reserved16: 16; }; uint32_t val; -} usb_dvbusdis_reg_t; +} usb_dwc_dvbusdis_reg_t; typedef union { struct { @@ -691,7 +677,7 @@ typedef union { uint32_t reserved20: 20; }; uint32_t val; -} usb_dvbuspulse_reg_t; +} usb_dwc_dvbuspulse_reg_t; typedef union { struct { @@ -707,7 +693,7 @@ typedef union { uint32_t reserved4: 4; }; uint32_t val; -} usb_dthrctl_reg_t; +} usb_dwc_dthrctl_reg_t; typedef union { struct { @@ -715,7 +701,7 @@ typedef union { uint32_t reserved16: 16; }; uint32_t val; -} usb_diepempmsk_reg_t; +} usb_dwc_diepempmsk_reg_t; typedef union { struct { @@ -736,7 +722,7 @@ typedef union { uint32_t epena0: 1; }; uint32_t val; -} usb_diepctl0_reg_t; +} usb_dwc_diepctl0_reg_t; typedef union { struct { @@ -758,7 +744,7 @@ typedef union { uint32_t reserved17: 17; }; uint32_t val; -} usb_diepint0_reg_t; +} usb_dwc_diepint0_reg_t; typedef union { struct { @@ -768,14 +754,14 @@ typedef union { uint32_t reserved11: 11; }; uint32_t val; -} usb_dieptsiz0_reg_t; +} usb_dwc_dieptsiz0_reg_t; typedef union { struct { uint32_t dmaaddr0; }; uint32_t val; -} usb_diepdma0_reg_t; +} usb_dwc_diepdma0_reg_t; typedef union { struct { @@ -783,14 +769,14 @@ typedef union { uint32_t reserved16: 16; }; uint32_t val; -} usb_dtxfsts0_reg_t; +} usb_dwc_dtxfsts0_reg_t; typedef union { struct { uint32_t dmabufferaddr0; }; uint32_t val; -} usb_diepdmab0_reg_t; +} usb_dwc_diepdmab0_reg_t; typedef union { struct { @@ -812,7 +798,7 @@ typedef union { uint32_t epena: 1; }; uint32_t val; -} usb_diepctl_reg_t; +} usb_dwc_diepctl_reg_t; typedef union { struct { @@ -834,7 +820,7 @@ typedef union { uint32_t reserved15: 17; }; uint32_t val; -} usb_diepint_reg_t; +} usb_dwc_diepint_reg_t; typedef union { struct { @@ -844,14 +830,14 @@ typedef union { uint32_t reserved11: 11; }; uint32_t val; -} usb_dieptsiz_reg_t; +} usb_dwc_dieptsiz_reg_t; typedef union { struct { uint32_t dmaddr1; }; uint32_t val; -} usb_diepdma_reg_t; +} usb_dwc_diepdma_reg_t; typedef union { struct { @@ -859,14 +845,14 @@ typedef union { uint32_t reserved16: 16; }; uint32_t val; -} usb_dtxfsts_reg_t; +} usb_dwc_dtxfsts_reg_t; typedef union { struct { uint32_t dmabufferaddr1; }; uint32_t val; -} usb_diepdmab_reg_t; +} usb_dwc_diepdmab_reg_t; typedef union { struct { @@ -886,7 +872,7 @@ typedef union { uint32_t epena0: 1; }; uint32_t val; -} usb_doepctl0_reg_t; +} usb_dwc_doepctl0_reg_t; typedef union { struct { @@ -909,7 +895,7 @@ typedef union { uint32_t reserved16: 16; }; uint32_t val; -} usb_doepint0_reg_t; +} usb_dwc_doepint0_reg_t; typedef union { struct { @@ -921,21 +907,21 @@ typedef union { uint32_t reserved1: 1; }; uint32_t val; -} usb_doeptsiz0_reg_t; +} usb_dwc_doeptsiz0_reg_t; typedef union { struct { uint32_t dmaaddr0; }; uint32_t val; -} usb_doepdma0_reg_t; +} usb_dwc_doepdma0_reg_t; typedef union { struct { uint32_t dmabufferaddr0; }; uint32_t val; -} usb_doepdmab0_reg_t; +} usb_dwc_doepdmab0_reg_t; typedef union { struct { @@ -956,7 +942,7 @@ typedef union { uint32_t epena: 1; }; uint32_t val; -} usb_doepctl_reg_t; +} usb_dwc_doepctl_reg_t; typedef union { struct { @@ -979,7 +965,7 @@ typedef union { uint32_t reserved16: 16; }; uint32_t val; -} usb_doepint_reg_t; +} usb_dwc_doepint_reg_t; typedef union { struct { @@ -991,21 +977,21 @@ typedef union { uint32_t reserved1: 1; }; uint32_t val; -} usb_doeptsiz_reg_t; +} usb_dwc_doeptsiz_reg_t; typedef union { struct { uint32_t dmaaddr; }; uint32_t val; -} usb_doepdma_reg_t; +} usb_dwc_doepdma_reg_t; typedef union { struct { uint32_t dmabufferaddr; }; uint32_t val; -} usb_doepdmab_reg_t; +} usb_dwc_doepdmab_reg_t; typedef union { struct { @@ -1020,143 +1006,143 @@ typedef union { uint32_t reserved23: 23; }; uint32_t val; -} usb_pcgcctl_reg_t; +} usb_dwc_pcgcctl_reg_t; /* --------------------------- Register Groups ------------------------------ */ typedef struct { - volatile usb_hcchar_reg_t hcchar_reg; //0x00 - uint32_t reserved_0x04_0x08[1]; //0x04 - volatile usb_hcint_reg_t hcint_reg; //0x08 - volatile usb_hcintmsk_reg_t hcintmsk_reg; //0x0c - volatile usb_hctsiz_reg_t hctsiz_reg; //0x10 - volatile usb_hcdma_reg_t hcdma_reg; //0x14 - uint32_t reserved_0x14_0x14[1]; //0x18* - volatile usb_hcdmab_reg_t hcdmab_reg; //0x1c -} usb_host_chan_regs_t; + volatile usb_dwc_hcchar_reg_t hcchar_reg; // 0x00 + uint32_t reserved_0x04_0x08[1]; // 0x04 + volatile usb_dwc_hcint_reg_t hcint_reg; // 0x08 + volatile usb_dwc_hcintmsk_reg_t hcintmsk_reg; // 0x0c + volatile usb_dwc_hctsiz_reg_t hctsiz_reg; // 0x10 + volatile usb_dwc_hcdma_reg_t hcdma_reg; // 0x14 + uint32_t reserved_0x14_0x14[1]; // 0x18 + volatile usb_dwc_hcdmab_reg_t hcdmab_reg; // 0x1c +} usb_dwc_host_chan_regs_t; typedef struct { - volatile usb_diepctl_reg_t diepctl_reg; //0x00 - uint32_t reserved_0x04_0x08[1]; //0x04 - volatile usb_diepint_reg_t diepint_reg; //0x08 - uint32_t reserved_0x0c_0x10[1]; //0x0c - volatile usb_dieptsiz_reg_t dieptsiz_reg; //0x010 - volatile usb_diepdma_reg_t diepdma_reg; //0x14 - volatile usb_dtxfsts_reg_t dtxfsts_reg; //0x18 - volatile usb_diepdmab_reg_t diepdmab_reg; //0x1c -} usb_in_ep_regs_t; + volatile usb_dwc_diepctl_reg_t diepctl_reg; // 0x00 + uint32_t reserved_0x04_0x08[1]; // 0x04 + volatile usb_dwc_diepint_reg_t diepint_reg; // 0x08 + uint32_t reserved_0x0c_0x10[1]; // 0x0c + volatile usb_dwc_dieptsiz_reg_t dieptsiz_reg; // 0x010 + volatile usb_dwc_diepdma_reg_t diepdma_reg; // 0x14 + volatile usb_dwc_dtxfsts_reg_t dtxfsts_reg; // 0x18 + volatile usb_dwc_diepdmab_reg_t diepdmab_reg; // 0x1c +} usb_dwc_in_ep_regs_t; typedef struct { - volatile usb_doepctl_reg_t doepctl_reg; //0x00 - uint32_t reserved_0x04_0x08[1]; //0x04 - volatile usb_doepint_reg_t doepint_reg; //0x08 - uint32_t reserved_0x0c_0x10[1]; //0x0c - volatile usb_doeptsiz_reg_t doeptsiz_reg; //0x10 - volatile usb_doepdma_reg_t doepdma_reg; //0x14 - uint32_t reserved_0x18_0x1c[1]; //0x18 - volatile usb_doepdmab_reg_t doepdmab_reg; //0x1c -} usb_out_ep_regs_t; + volatile usb_dwc_doepctl_reg_t doepctl_reg; // 0x00 + uint32_t reserved_0x04_0x08[1]; // 0x04 + volatile usb_dwc_doepint_reg_t doepint_reg; // 0x08 + uint32_t reserved_0x0c_0x10[1]; // 0x0c + volatile usb_dwc_doeptsiz_reg_t doeptsiz_reg; // 0x10 + volatile usb_dwc_doepdma_reg_t doepdma_reg; // 0x14 + uint32_t reserved_0x18_0x1c[1]; // 0x18 + volatile usb_dwc_doepdmab_reg_t doepdmab_reg; // 0x1c +} usb_dwc_out_ep_regs_t; /* --------------------------- Register Layout ------------------------------ */ typedef struct { //Global Registers - volatile usb_gotgctl_reg_t gotgctl_reg; //0x0000 - volatile usb_gotgint_reg_t gotgint_reg; //0x0004 - volatile usb_gahbcfg_reg_t gahbcfg_reg; //0x0008 - volatile usb_gusbcfg_reg_t gusbcfg_reg; //0x000c - volatile usb_grstctl_reg_t grstctl_reg; //0x0010 - volatile usb_gintsts_reg_t gintsts_reg; //0x0014 - volatile usb_gintmsk_reg_t gintmsk_reg; //0x0018 - volatile usb_grxstsr_reg_t grxstsr_reg; //0x001c - volatile usb_grxstsp_reg_t grxstsp_reg; //0x0020 - volatile usb_grxfsiz_reg_t grxfsiz_reg; //0x0024 - volatile usb_gnptxfsiz_reg_t gnptxfsiz_reg; //0x0028 - volatile usb_gnptxsts_reg_t gnptxsts_reg; //0x002c - uint32_t reserved_0x0030_0x0040[4]; //0x0030 to 0x0040 - volatile usb_gsnpsid_reg_t gsnpsid_reg; //0x0040 - volatile usb_ghwcfg1_reg_t ghwcfg1_reg; //0x0044 - volatile usb_ghwcfg2_reg_t ghwcfg2_reg; //0x0048 - volatile usb_ghwcfg3_reg_t ghwcfg3_reg; //0x004c - volatile usb_ghwcfg4_reg_t ghwcfg4_reg; //0x0050 - uint32_t reserved_0x0054_0x005c[2]; //0x0054 to 0x005c + volatile usb_dwc_gotgctl_reg_t gotgctl_reg; // 0x0000 + volatile usb_dwc_gotgint_reg_t gotgint_reg; // 0x0004 + volatile usb_dwc_gahbcfg_reg_t gahbcfg_reg; // 0x0008 + volatile usb_dwc_gusbcfg_reg_t gusbcfg_reg; // 0x000c + volatile usb_dwc_grstctl_reg_t grstctl_reg; // 0x0010 + volatile usb_dwc_gintsts_reg_t gintsts_reg; // 0x0014 + volatile usb_dwc_gintmsk_reg_t gintmsk_reg; // 0x0018 + volatile usb_dwc_grxstsr_reg_t grxstsr_reg; // 0x001c + volatile usb_dwc_grxstsp_reg_t grxstsp_reg; // 0x0020 + volatile usb_dwc_grxfsiz_reg_t grxfsiz_reg; // 0x0024 + volatile usb_dwc_gnptxfsiz_reg_t gnptxfsiz_reg; // 0x0028 + volatile usb_dwc_gnptxsts_reg_t gnptxsts_reg; // 0x002c + uint32_t reserved_0x0030_0x0040[4]; // 0x0030 to 0x0040 + volatile usb_dwc_gsnpsid_reg_t gsnpsid_reg; // 0x0040 + volatile usb_dwc_ghwcfg1_reg_t ghwcfg1_reg; // 0x0044 + volatile usb_dwc_ghwcfg2_reg_t ghwcfg2_reg; // 0x0048 + volatile usb_dwc_ghwcfg3_reg_t ghwcfg3_reg; // 0x004c + volatile usb_dwc_ghwcfg4_reg_t ghwcfg4_reg; // 0x0050 + uint32_t reserved_0x0054_0x005c[2]; // 0x0054 to 0x005c //FIFO Configurations - volatile usb_gdfifocfg_reg_t gdfifocfg_reg; //0x005c - uint32_t reserved_0x0060_0x0100[40]; //0x0060 to 0x0100 - volatile usb_hptxfsiz_reg_t hptxfsiz_reg; //0x0100 - volatile usb_dieptxfi_reg_t dieptxfi_regs[4]; //0x0104 to 0x0114 - usb_dieptxfi_reg_t reserved_0x0114_0x0140[11]; //0x0114 to 0x0140 - uint32_t reserved_0x140_0x400[176]; //0x0140 to 0x0400 + volatile usb_dwc_gdfifocfg_reg_t gdfifocfg_reg; // 0x005c + uint32_t reserved_0x0060_0x0100[40]; // 0x0060 to 0x0100 + volatile usb_dwc_hptxfsiz_reg_t hptxfsiz_reg; // 0x0100 + volatile usb_dwc_dieptxfi_reg_t dieptxfi_regs[4]; // 0x0104 to 0x0114 + usb_dwc_dieptxfi_reg_t reserved_0x0114_0x0140[11]; // 0x0114 to 0x0140 + uint32_t reserved_0x140_0x400[176]; // 0x0140 to 0x0400 //Host Mode Registers - volatile usb_hcfg_reg_t hcfg_reg; //0x0400 - volatile usb_hfir_reg_t hfir_reg; //0x0404 - volatile usb_hfnum_reg_t hfnum_reg; //0x0408 - uint32_t reserved_0x40c_0x410[1]; //0x040c to 0x0410 - volatile usb_hptxsts_reg_t hptxsts_reg; //0x0410 - volatile usb_haint_reg_t haint_reg; //0x0414 - volatile usb_haintmsk_reg_t haintmsk_reg; //0x0418 - volatile usb_hflbaddr_reg_t hflbaddr_reg; //0x041c - uint32_t reserved_0x420_0x440[8]; //0x0420 to 0x0440 - volatile usb_hprt_reg_t hprt_reg; //0x0440 - uint32_t reserved_0x0444_0x0500[47]; //0x0444 to 0x0500 - usb_host_chan_regs_t host_chans[8]; //0x0500 to 0x0600 - usb_host_chan_regs_t reserved_0x0600_0x0700[8]; //0x0600 to 0x0700 - uint32_t reserved_0x0700_0x0800[64]; //0x0700 to 0x0800 - volatile usb_dcfg_reg_t dcfg_reg; //0x0800 - volatile usb_dctl_reg_t dctl_reg; //0x0804 - volatile usb_dsts_reg_t dsts_reg; //0x0808 - uint32_t reserved_0x080c_0x0810[1]; //0x080c to 0x0810 + volatile usb_dwc_hcfg_reg_t hcfg_reg; // 0x0400 + volatile usb_dwc_hfir_reg_t hfir_reg; // 0x0404 + volatile usb_dwc_hfnum_reg_t hfnum_reg; // 0x0408 + uint32_t reserved_0x40c_0x410[1]; // 0x040c to 0x0410 + volatile usb_dwc_hptxsts_reg_t hptxsts_reg; // 0x0410 + volatile usb_dwc_haint_reg_t haint_reg; // 0x0414 + volatile usb_dwc_haintmsk_reg_t haintmsk_reg; // 0x0418 + volatile usb_dwc_hflbaddr_reg_t hflbaddr_reg; // 0x041c + uint32_t reserved_0x420_0x440[8]; // 0x0420 to 0x0440 + volatile usb_dwc_hprt_reg_t hprt_reg; // 0x0440 + uint32_t reserved_0x0444_0x0500[47]; // 0x0444 to 0x0500 + usb_dwc_host_chan_regs_t host_chans[8]; // 0x0500 to 0x0600 + usb_dwc_host_chan_regs_t reserved_0x0600_0x0700[8]; // 0x0600 to 0x0700 + uint32_t reserved_0x0700_0x0800[64]; // 0x0700 to 0x0800 + volatile usb_dwc_dcfg_reg_t dcfg_reg; // 0x0800 + volatile usb_dwc_dctl_reg_t dctl_reg; // 0x0804 + volatile usb_dwc_dsts_reg_t dsts_reg; // 0x0808 + uint32_t reserved_0x080c_0x0810[1]; // 0x080c to 0x0810 //Device Mode Registers - volatile usb_diepmsk_reg_t diepmsk_reg; //0x810 - volatile usb_doepmsk_reg_t doepmsk_reg; //0x0814 - volatile usb_daint_reg_t daint_reg; //0x0818 - volatile usb_daintmsk_reg_t daintmsk_reg; //0x081c - uint32_t reserved_0x0820_0x0828[2]; //0x0820 to 0x0828 - volatile usb_dvbusdis_reg_t dvbusdis_reg; //0x0828 - volatile usb_dvbuspulse_reg_t dvbuspulse_reg; //0x082c - volatile usb_dthrctl_reg_t dthrctl_reg; //0x0830 - volatile usb_diepempmsk_reg_t diepempmsk_reg; //0x0834 - uint32_t reserved_0x0838_0x0900[50]; //0x0838 to 0x0900 + volatile usb_dwc_diepmsk_reg_t diepmsk_reg; // 0x810 + volatile usb_dwc_doepmsk_reg_t doepmsk_reg; // 0x0814 + volatile usb_dwc_daint_reg_t daint_reg; // 0x0818 + volatile usb_dwc_daintmsk_reg_t daintmsk_reg; // 0x081c + uint32_t reserved_0x0820_0x0828[2]; // 0x0820 to 0x0828 + volatile usb_dwc_dvbusdis_reg_t dvbusdis_reg; // 0x0828 + volatile usb_dwc_dvbuspulse_reg_t dvbuspulse_reg; // 0x082c + volatile usb_dwc_dthrctl_reg_t dthrctl_reg; // 0x0830 + volatile usb_dwc_diepempmsk_reg_t diepempmsk_reg; // 0x0834 + uint32_t reserved_0x0838_0x0900[50]; // 0x0838 to 0x0900 //Deivce: IN EP0 reigsters - volatile usb_diepctl0_reg_t diepctl0_reg; //0x0900 - uint32_t reserved_0x0904_0x0908[1]; //0x0904 to 0x0908 - volatile usb_diepint0_reg_t diepint0_reg; //0x0908 - uint32_t reserved_0x090c_0x0910[1]; //0x090c to 0x0910 - volatile usb_dieptsiz0_reg_t dieptsiz0_reg; //0x0910 - volatile usb_diepdma0_reg_t diepdma0_reg; //0x0914 - volatile usb_dtxfsts0_reg_t dtxfsts0_reg; //0x0918 - volatile usb_diepdmab0_reg_t diepdmab0_reg; //0x091c + volatile usb_dwc_diepctl0_reg_t diepctl0_reg; // 0x0900 + uint32_t reserved_0x0904_0x0908[1]; // 0x0904 to 0x0908 + volatile usb_dwc_diepint0_reg_t diepint0_reg; // 0x0908 + uint32_t reserved_0x090c_0x0910[1]; // 0x090c to 0x0910 + volatile usb_dwc_dieptsiz0_reg_t dieptsiz0_reg; // 0x0910 + volatile usb_dwc_diepdma0_reg_t diepdma0_reg; // 0x0914 + volatile usb_dwc_dtxfsts0_reg_t dtxfsts0_reg; // 0x0918 + volatile usb_dwc_diepdmab0_reg_t diepdmab0_reg; // 0x091c //Deivce: IN EP registers - usb_in_ep_regs_t in_eps[6]; //0x0920 to 0x09e0 - usb_in_ep_regs_t reserved_0x09e0_0x0b00[9]; //0x09e0 to 0x0b00 + usb_dwc_in_ep_regs_t in_eps[6]; // 0x0920 to 0x09e0 + usb_dwc_in_ep_regs_t reserved_0x09e0_0x0b00[9]; // 0x09e0 to 0x0b00 //Device: OUT EP0 reigsters - volatile usb_doepctl0_reg_t doepctl0_reg; //0x0b00 - uint32_t reserved_0x0b04_0x0b08[1]; //0x0b04 to 0x0b08 - volatile usb_doepint0_reg_t doepint0_reg; //0b0b08 - uint32_t reserved_0x0b0c_0x0b10[1]; //0x0b0c to 0x0b10 - volatile usb_doeptsiz0_reg_t doeptsiz0_reg; //0x0b10 - volatile usb_doepdma0_reg_t doepdma0_reg; //0x0b14 - uint32_t reserved_0x0b18_0x0b1c[1]; //0x0b18 to 0x0b1c - volatile usb_doepdmab0_reg_t doepdmab0_reg; //0x0b1c + volatile usb_dwc_doepctl0_reg_t doepctl0_reg; // 0x0b00 + uint32_t reserved_0x0b04_0x0b08[1]; // 0x0b04 to 0x0b08 + volatile usb_dwc_doepint0_reg_t doepint0_reg; // 0b0b08 + uint32_t reserved_0x0b0c_0x0b10[1]; // 0x0b0c to 0x0b10 + volatile usb_dwc_doeptsiz0_reg_t doeptsiz0_reg; // 0x0b10 + volatile usb_dwc_doepdma0_reg_t doepdma0_reg; // 0x0b14 + uint32_t reserved_0x0b18_0x0b1c[1]; // 0x0b18 to 0x0b1c + volatile usb_dwc_doepdmab0_reg_t doepdmab0_reg; // 0x0b1c //Deivce: OUT EP registers - usb_out_ep_regs_t out_eps[6]; //0xb1c - usb_out_ep_regs_t reserved_0x0be0_0x0d00[9]; //0x0be0 to 0x0d00 - uint32_t reserved_0x0d00_0x0e00[64]; //0x0d00 to 0x0e00 - volatile usb_pcgcctl_reg_t pcgcctl_reg; //0x0e00 - uint32_t reserved_0x0e04_0x0e08[1]; //0x0d00 to 0x0e00 -} usbh_dev_t; + usb_dwc_out_ep_regs_t out_eps[6]; // 0xb1c + usb_dwc_out_ep_regs_t reserved_0x0be0_0x0d00[9]; // 0x0be0 to 0x0d00 + uint32_t reserved_0x0d00_0x0e00[64]; // 0x0d00 to 0x0e00 + volatile usb_dwc_pcgcctl_reg_t pcgcctl_reg; // 0x0e00 + uint32_t reserved_0x0e04_0x0e08[1]; // 0x0d00 to 0x0e00 +} usb_dwc_dev_t; -_Static_assert(sizeof(usbh_dev_t) == 0xe08, "USB new struct should be 0xe08 large"); +_Static_assert(sizeof(usb_dwc_dev_t) == 0xe08, "Invalid size of usb_dwc_dev_t structure"); -extern usbh_dev_t USBH; +extern usb_dwc_dev_t USB_DWC; #ifdef __cplusplus diff --git a/components/soc/esp32s3/include/soc/world_controller_reg.h b/components/soc/esp32s3/include/soc/world_controller_reg.h index 610e66089d..1ba5333cf2 100644 --- a/components/soc/esp32s3/include/soc/world_controller_reg.h +++ b/components/soc/esp32s3/include/soc/world_controller_reg.h @@ -1,1084 +1,1504 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_WORLD_CONTROLLER_REG_H_ -#define _SOC_WORLD_CONTROLLER_REG_H_ +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once - -#include "soc.h" +#include +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_1_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x0) -/* WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 1 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_2_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4) -/* WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 2 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_2_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_3_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x8) -/* WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 3 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_3_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_4_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xC) -/* WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 4 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_4_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_5_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x10) -/* WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 5 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_5_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_6_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x14) -/* WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 6 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_6_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_7_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x18) -/* WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 7 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_7_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_8_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x1C) -/* WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 8 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_8_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_9_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x20) -/* WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 9 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_9_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_10_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x24) -/* WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 10 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_10_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_11_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x28) -/* WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 11 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_11_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_12_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x2C) -/* WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 12 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_12_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_13_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x30) -/* WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_0 Entry 13 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR_M ((WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_13_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_CHECK_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x7C) -/* WORLD_CONTROLLER_CORE_0_ENTRY_CHECK : R/W ;bitpos:[13:1] ;default: 1'b1 ; */ -/*description: This filed is used to enable entry address check .*/ -#define WORLD_CONTROLLER_CORE_0_ENTRY_CHECK 0x00001FFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_CHECK_M ((WORLD_CONTROLLER_CORE_0_ENTRY_CHECK_V)<<(WORLD_CONTROLLER_CORE_0_ENTRY_CHECK_S)) -#define WORLD_CONTROLLER_CORE_0_ENTRY_CHECK_V 0x1FFF -#define WORLD_CONTROLLER_CORE_0_ENTRY_CHECK_S 1 - -#define WORLD_CONTROLLER_WCL_CORE_0_MESSAGE_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x100) -/* WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: This field is used to set address that need to write when enter WORLD0.*/ -#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR_M ((WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_MESSAGE_MAX_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x104) -/* WORLD_CONTROLLER_CORE_0_MESSAGE_MAX : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: This filed is used to set the max value of clear write_buffer.*/ -#define WORLD_CONTROLLER_CORE_0_MESSAGE_MAX 0x0000000F -#define WORLD_CONTROLLER_CORE_0_MESSAGE_MAX_M ((WORLD_CONTROLLER_CORE_0_MESSAGE_MAX_V)<<(WORLD_CONTROLLER_CORE_0_MESSAGE_MAX_S)) -#define WORLD_CONTROLLER_CORE_0_MESSAGE_MAX_V 0xF -#define WORLD_CONTROLLER_CORE_0_MESSAGE_MAX_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE1_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x80) -/* WORLD_CONTROLLER_CORE_0_CURRENT_1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 1 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_1 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_1_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_1_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_1_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 1.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_1_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 1 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_1 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_1_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_1_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_1_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE2_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x84) -/* WORLD_CONTROLLER_CORE_0_CURRENT_2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 2 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_2 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_2_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_2_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_2_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 2.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_2_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 2 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_2 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_2_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_2_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_2_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE3_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x88) -/* WORLD_CONTROLLER_CORE_0_CURRENT_3 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 3 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_3 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_3_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_3_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_3_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 3.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_3_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 3 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_3 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_3_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_3_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_3_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE4_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x8C) -/* WORLD_CONTROLLER_CORE_0_CURRENT_4 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 4 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_4 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_4_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_4_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_4_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 4.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_4_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_4 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 4 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_4 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_4_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_4_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_4_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE5_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x90) -/* WORLD_CONTROLLER_CORE_0_CURRENT_5 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 5 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_5 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_5_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_5_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_5_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 5.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_5_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_5 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 5 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_5 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_5_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_5_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_5_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE6_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x94) -/* WORLD_CONTROLLER_CORE_0_CURRENT_6 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 6 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_6 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_6_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_6_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_6_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 6.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_6_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_6 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 6 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_6 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_6_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_6_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_6_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE7_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x98) -/* WORLD_CONTROLLER_CORE_0_CURRENT_7 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 7 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_7 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_7_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_7_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_7_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 7.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_7_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_7 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 7 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_7 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_7_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_7_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_7_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE8_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x9C) -/* WORLD_CONTROLLER_CORE_0_CURRENT_8 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 8 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_8 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_8_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_8_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_8_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 8.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_8_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_8 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 8 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_8 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_8_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_8_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_8_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE9_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xA0) -/* WORLD_CONTROLLER_CORE_0_CURRENT_9 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 9 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_9 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_9_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_9_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_9_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 9.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_9_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_9 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 9 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_9 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_9_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_9_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_9_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE10_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xA4) -/* WORLD_CONTROLLER_CORE_0_CURRENT_10 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 10 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_10 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_10_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_10_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_10_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 10.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_10_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_10 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 10 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_10 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_10_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_10_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_10_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE11_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xA8) -/* WORLD_CONTROLLER_CORE_0_CURRENT_11 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 11 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_11 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_11_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_11_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_11_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 11.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_11_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_11 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 11 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_11 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_11_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_11_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_11_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE12_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xAC) -/* WORLD_CONTROLLER_CORE_0_CURRENT_12 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 12 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_12 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_12_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_12_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_12_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 12.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_12_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_12 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 12 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_12 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_12_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_12_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_12_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE13_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xB0) -/* WORLD_CONTROLLER_CORE_0_CURRENT_13 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 13 .*/ -#define WORLD_CONTROLLER_CORE_0_CURRENT_13 (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_13_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_CURRENT_13_V 0x1 -#define WORLD_CONTROLLER_CORE_0_CURRENT_13_S 5 -/* WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 13.*/ -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13 0x0000000F -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13_M ((WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13_V)<<(WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13_S)) -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13_V 0xF -#define WORLD_CONTROLLER_CORE_0_FROM_ENTRY_13_S 1 -/* WORLD_CONTROLLER_CORE_0_FROM_WORLD_13 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 13 .*/ -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_13 (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_13_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_13_V 0x1 -#define WORLD_CONTROLLER_CORE_0_FROM_WORLD_13_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE_CURRENT_REG (DR_REG_WORLD_CONTROLLER_BASE + 0xFC) -/* WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT : R/W ;bitpos:[13:1] ;default: 13'b0 ; */ -/*description: This field is used to quickly read and rewrite the current field of all STATUSTA -BLE registers.For example.*/ -#define WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT 0x00001FFF -#define WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_M ((WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_V)<<(WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_S)) -#define WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_V 0x1FFF -#define WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_S 1 - -#define WORLD_CONTROLLER_WCL_CORE_0_MESSAGE_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x108) -/* WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: If this bit is 1.*/ -#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE (BIT(6)) -#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE_M (BIT(6)) -#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE_V 0x1 -#define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE_S 6 -/* WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: If this bit is 1.*/ -#define WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE_V 0x1 -#define WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE_S 5 -/* WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT : RO ;bitpos:[4:1] ;default: 4'b0 ; */ -/*description: This field indicates the data to be written next time.*/ -#define WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT 0x0000000F -#define WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT_M ((WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT_V)<<(WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT_S)) -#define WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT_V 0xF -#define WORLD_CONTROLLER_CORE_0_MESSAGE_EXPECT_S 1 -/* WORLD_CONTROLLER_CORE_0_MESSAGE_MATCH : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit indicates whether the check is successful.*/ -#define WORLD_CONTROLLER_CORE_0_MESSAGE_MATCH (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_MESSAGE_MATCH_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_MESSAGE_MATCH_V 0x1 -#define WORLD_CONTROLLER_CORE_0_MESSAGE_MATCH_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_WORLD_TRIGGER_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x140) -/* WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR : RW ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: This field is used to configure the entry address from WORLD0 to WORLD1.*/ -#define WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_M ((WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_WORLD_PREPARE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x144) -/* WORLD_CONTROLLER_CORE_0_WORLD_PREPARE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: This field to used to set world to enter.*/ -#define WORLD_CONTROLLER_CORE_0_WORLD_PREPARE 0x00000003 -#define WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_M ((WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_V)<<(WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_S)) -#define WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_V 0x3 -#define WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_WORLD_UPDATE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x148) -/* WORLD_CONTROLLER_CORE_0_UPDATE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: This field is used to update configuration completed.*/ -#define WORLD_CONTROLLER_CORE_0_UPDATE 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_UPDATE_M ((WORLD_CONTROLLER_CORE_0_UPDATE_V)<<(WORLD_CONTROLLER_CORE_0_UPDATE_S)) -#define WORLD_CONTROLLER_CORE_0_UPDATE_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_UPDATE_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_WORLD_CANCEL_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x14C) -/* WORLD_CONTROLLER_CORE_0_WORLD_CANCEL : WO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: This field is used to cancel switch world configuration.*/ -#define WORLD_CONTROLLER_CORE_0_WORLD_CANCEL 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_M ((WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_V)<<(WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_S)) -#define WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_WORLD_IRAM0_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x150) -/* WORLD_CONTROLLER_CORE_0_WORLD_IRAM0 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: this field is used to read current world of Iram0 bus.*/ -#define WORLD_CONTROLLER_CORE_0_WORLD_IRAM0 0x00000003 -#define WORLD_CONTROLLER_CORE_0_WORLD_IRAM0_M ((WORLD_CONTROLLER_CORE_0_WORLD_IRAM0_V)<<(WORLD_CONTROLLER_CORE_0_WORLD_IRAM0_S)) -#define WORLD_CONTROLLER_CORE_0_WORLD_IRAM0_V 0x3 -#define WORLD_CONTROLLER_CORE_0_WORLD_IRAM0_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_WORLD_DRAM0_PIF_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x154) -/* WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: this field is used to read current world of Dram0 bus and PIF bus.*/ -#define WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF 0x00000003 -#define WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF_M ((WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF_V)<<(WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF_S)) -#define WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF_V 0x3 -#define WORLD_CONTROLLER_CORE_0_WORLD_DRAM0_PIF_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_WORLD_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x158) -/* WORLD_CONTROLLER_CORE_0_WORLD_PHASE : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit indicates whether is preparing to switch to WORLD1.*/ -#define WORLD_CONTROLLER_CORE_0_WORLD_PHASE (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_WORLD_PHASE_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_WORLD_PHASE_V 0x1 -#define WORLD_CONTROLLER_CORE_0_WORLD_PHASE_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_ENABLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x180) -/* WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: this field is used to set NMI mask.*/ -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_M ((WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_V)<<(WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_S)) -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x184) -/* WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: this field to used to set trigger address.*/ -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_M ((WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_S)) -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_DISABLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x188) -/* WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: this field is used to disable NMI mask.*/ -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_M ((WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_V)<<(WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_S)) -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_CANCLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x18C) -/* WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL : WO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: this field is used to cancel NMI mask disable function..*/ -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL_M ((WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL_V)<<(WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL_S)) -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_CANCEL_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x190) -/* WORLD_CONTROLLER_CORE_0_NMI_MASK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: this bit is used to mask NMI interrupt.*/ -#define WORLD_CONTROLLER_CORE_0_NMI_MASK (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_V 0x1 -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x194) -/* WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: this bit is used to indicates whether the NMI interrupt is being masked.*/ -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE_V 0x1 -#define WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_1_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x400) -/* WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 1 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_1_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_2_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x404) -/* WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 2 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_2_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_3_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x408) -/* WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 3 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_3_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_4_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x40C) -/* WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 4 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_4_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_5_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x410) -/* WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 5 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_5_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_6_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x414) -/* WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 6 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_6_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_7_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x418) -/* WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 7 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_7_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_8_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x41C) -/* WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 8 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_8_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_9_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x420) -/* WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 9 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_9_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_10_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x424) -/* WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 10 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_10_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_11_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x428) -/* WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 11 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_11_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_12_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x42C) -/* WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 12 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_12_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_13_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x430) -/* WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */ -/*description: Core_1 Entry 13 address from WORLD1 to WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR_M ((WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_13_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_ENTRY_CHECK_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x47C) -/* WORLD_CONTROLLER_CORE_1_ENTRY_CHECK : R/W ;bitpos:[13:1] ;default: 1'b1 ; */ -/*description: This filed is used to enable entry address check .*/ -#define WORLD_CONTROLLER_CORE_1_ENTRY_CHECK 0x00001FFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_CHECK_M ((WORLD_CONTROLLER_CORE_1_ENTRY_CHECK_V)<<(WORLD_CONTROLLER_CORE_1_ENTRY_CHECK_S)) -#define WORLD_CONTROLLER_CORE_1_ENTRY_CHECK_V 0x1FFF -#define WORLD_CONTROLLER_CORE_1_ENTRY_CHECK_S 1 - -#define WORLD_CONTROLLER_WCL_CORE_1_MESSAGE_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x500) -/* WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: This field is used to set address that need to write when enter WORLD0.*/ -#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR_M ((WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_MESSAGE_MAX_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x504) -/* WORLD_CONTROLLER_CORE_1_MESSAGE_MAX : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: This filed is used to set the max value of clear write_buffer.*/ -#define WORLD_CONTROLLER_CORE_1_MESSAGE_MAX 0x0000000F -#define WORLD_CONTROLLER_CORE_1_MESSAGE_MAX_M ((WORLD_CONTROLLER_CORE_1_MESSAGE_MAX_V)<<(WORLD_CONTROLLER_CORE_1_MESSAGE_MAX_S)) -#define WORLD_CONTROLLER_CORE_1_MESSAGE_MAX_V 0xF -#define WORLD_CONTROLLER_CORE_1_MESSAGE_MAX_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE1_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x480) -/* WORLD_CONTROLLER_CORE_1_CURRENT_1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 1 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_1 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_1_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_1_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_1_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 1.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_1_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 1 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_1 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_1_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_1_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_1_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE2_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x484) -/* WORLD_CONTROLLER_CORE_1_CURRENT_2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 2 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_2 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_2_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_2_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_2_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 2.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_2_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 2 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_2 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_2_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_2_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_2_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE3_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x488) -/* WORLD_CONTROLLER_CORE_1_CURRENT_3 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 3 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_3 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_3_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_3_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_3_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 3.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_3_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 3 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_3 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_3_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_3_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_3_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE4_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x48C) -/* WORLD_CONTROLLER_CORE_1_CURRENT_4 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 4 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_4 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_4_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_4_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_4_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 4.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_4_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_4 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 4 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_4 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_4_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_4_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_4_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE5_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x490) -/* WORLD_CONTROLLER_CORE_1_CURRENT_5 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 5 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_5 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_5_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_5_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_5_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 5.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_5_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_5 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 5 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_5 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_5_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_5_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_5_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE6_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x494) -/* WORLD_CONTROLLER_CORE_1_CURRENT_6 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 6 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_6 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_6_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_6_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_6_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 6.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_6_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_6 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 6 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_6 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_6_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_6_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_6_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE7_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x498) -/* WORLD_CONTROLLER_CORE_1_CURRENT_7 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 7 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_7 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_7_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_7_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_7_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 7.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_7_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_7 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 7 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_7 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_7_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_7_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_7_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE8_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x49C) -/* WORLD_CONTROLLER_CORE_1_CURRENT_8 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 8 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_8 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_8_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_8_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_8_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 8.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_8_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_8 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 8 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_8 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_8_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_8_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_8_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE9_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4A0) -/* WORLD_CONTROLLER_CORE_1_CURRENT_9 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 9 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_9 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_9_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_9_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_9_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 9.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_9_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_9 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 9 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_9 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_9_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_9_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_9_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE10_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4A4) -/* WORLD_CONTROLLER_CORE_1_CURRENT_10 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 10 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_10 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_10_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_10_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_10_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 10.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_10_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_10 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 10 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_10 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_10_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_10_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_10_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE11_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4A8) -/* WORLD_CONTROLLER_CORE_1_CURRENT_11 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 11 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_11 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_11_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_11_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_11_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 11.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_11_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_11 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 11 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_11 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_11_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_11_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_11_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE12_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4AC) -/* WORLD_CONTROLLER_CORE_1_CURRENT_12 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 12 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_12 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_12_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_12_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_12_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 12.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_12_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_12 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 12 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_12 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_12_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_12_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_12_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE13_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4B0) -/* WORLD_CONTROLLER_CORE_1_CURRENT_13 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit is used to confirm whether the current state is in entry 13 .*/ -#define WORLD_CONTROLLER_CORE_1_CURRENT_13 (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_13_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_CURRENT_13_V 0x1 -#define WORLD_CONTROLLER_CORE_1_CURRENT_13_S 5 -/* WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13 : R/W ;bitpos:[4:1] ;default: 4'h0 ; */ -/*description: This filed is used to confirm in which entry before enter entry 13.*/ -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13 0x0000000F -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13_M ((WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13_V)<<(WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13_S)) -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13_V 0xF -#define WORLD_CONTROLLER_CORE_1_FROM_ENTRY_13_S 1 -/* WORLD_CONTROLLER_CORE_1_FROM_WORLD_13 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to confirm world before enter entry 13 .*/ -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_13 (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_13_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_13_V 0x1 -#define WORLD_CONTROLLER_CORE_1_FROM_WORLD_13_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE_CURRENT_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x4FC) -/* WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT : R/W ;bitpos:[13:1] ;default: 13'b0 ; */ -/*description: This field is used to quickly read and rewrite the current field of all STATUSTA -BLE registers.For example.*/ -#define WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT 0x00001FFF -#define WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_M ((WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_V)<<(WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_S)) -#define WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_V 0x1FFF -#define WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_S 1 - -#define WORLD_CONTROLLER_WCL_CORE_1_MESSAGE_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x508) -/* WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: If this bit is 1.*/ -#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE (BIT(6)) -#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE_M (BIT(6)) -#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE_V 0x1 -#define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE_S 6 -/* WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: If this bit is 1.*/ -#define WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE_M (BIT(5)) -#define WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE_V 0x1 -#define WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE_S 5 -/* WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT : RO ;bitpos:[4:1] ;default: 4'b0 ; */ -/*description: This field indicates the data to be written next time.*/ -#define WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT 0x0000000F -#define WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT_M ((WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT_V)<<(WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT_S)) -#define WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT_V 0xF -#define WORLD_CONTROLLER_CORE_1_MESSAGE_EXPECT_S 1 -/* WORLD_CONTROLLER_CORE_1_MESSAGE_MATCH : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit indicates whether the check is successful.*/ -#define WORLD_CONTROLLER_CORE_1_MESSAGE_MATCH (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_MESSAGE_MATCH_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_MESSAGE_MATCH_V 0x1 -#define WORLD_CONTROLLER_CORE_1_MESSAGE_MATCH_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_WORLD_TRIGGER_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x540) -/* WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR : RW ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: This field is used to configure the entry address from WORLD0 to WORLD1.*/ -#define WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_M ((WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_WORLD_PREPARE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x544) -/* WORLD_CONTROLLER_CORE_1_WORLD_PREPARE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: This field to used to set world to enter.*/ -#define WORLD_CONTROLLER_CORE_1_WORLD_PREPARE 0x00000003 -#define WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_M ((WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_V)<<(WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_S)) -#define WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_V 0x3 -#define WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_WORLD_UPDATE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x548) -/* WORLD_CONTROLLER_CORE_1_UPDATE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: This field is used to update configuration completed.*/ -#define WORLD_CONTROLLER_CORE_1_UPDATE 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_UPDATE_M ((WORLD_CONTROLLER_CORE_1_UPDATE_V)<<(WORLD_CONTROLLER_CORE_1_UPDATE_S)) -#define WORLD_CONTROLLER_CORE_1_UPDATE_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_UPDATE_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_WORLD_CANCEL_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x54C) -/* WORLD_CONTROLLER_CORE_1_WORLD_CANCEL : WO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: This field is used to cancel switch world configuration.*/ -#define WORLD_CONTROLLER_CORE_1_WORLD_CANCEL 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_M ((WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_V)<<(WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_S)) -#define WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_WORLD_IRAM0_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x550) -/* WORLD_CONTROLLER_CORE_1_WORLD_IRAM0 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: this field is used to read current world of Iram0 bus.*/ -#define WORLD_CONTROLLER_CORE_1_WORLD_IRAM0 0x00000003 -#define WORLD_CONTROLLER_CORE_1_WORLD_IRAM0_M ((WORLD_CONTROLLER_CORE_1_WORLD_IRAM0_V)<<(WORLD_CONTROLLER_CORE_1_WORLD_IRAM0_S)) -#define WORLD_CONTROLLER_CORE_1_WORLD_IRAM0_V 0x3 -#define WORLD_CONTROLLER_CORE_1_WORLD_IRAM0_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_WORLD_DRAM0_PIF_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x554) -/* WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: this field is used to read current world of Dram0 bus and PIF bus.*/ -#define WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF 0x00000003 -#define WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF_M ((WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF_V)<<(WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF_S)) -#define WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF_V 0x3 -#define WORLD_CONTROLLER_CORE_1_WORLD_DRAM0_PIF_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_WORLD_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x558) -/* WORLD_CONTROLLER_CORE_1_WORLD_PHASE : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit indicates whether is preparing to switch to WORLD1.*/ -#define WORLD_CONTROLLER_CORE_1_WORLD_PHASE (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_WORLD_PHASE_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_WORLD_PHASE_V 0x1 -#define WORLD_CONTROLLER_CORE_1_WORLD_PHASE_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_ENABLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x580) -/* WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: this field is used to set NMI mask.*/ -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_M ((WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_V)<<(WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_S)) -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x584) -/* WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: this field to used to set trigger address.*/ -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_M ((WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_S)) -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_DISABLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x588) -/* WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE : WO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: this field is used to disable NMI mask.*/ -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_M ((WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_V)<<(WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_S)) -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_CANCLE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x58C) -/* WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL : WO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: this field is used to cancel NMI mask disable function..*/ -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL_M ((WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL_V)<<(WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL_S)) -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL_V 0xFFFFFFFF -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_CANCEL_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x590) -/* WORLD_CONTROLLER_CORE_1_NMI_MASK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: this bit is used to mask NMI interrupt.*/ -#define WORLD_CONTROLLER_CORE_1_NMI_MASK (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_V 0x1 -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_S 0 - -#define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_PHASE_REG (DR_REG_WORLD_CONTROLLER_BASE + 0x594) -/* WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: this bit is used to indicates whether the NMI interrupt is being masked.*/ -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE_M (BIT(0)) -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE_V 0x1 -#define WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE_S 0 - +/** WCL_Core_0_ENTRY_1_ADDR_REG register + * Core_0 Entry 1 address configuration Register + */ +#define WCL_CORE_0_ENTRY_1_ADDR_REG (DR_REG_WCL_BASE + 0x0) +/** WCL_CORE_0_ENTRY_1_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 1 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_1_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_1_ADDR_M (WCL_CORE_0_ENTRY_1_ADDR_V << WCL_CORE_0_ENTRY_1_ADDR_S) +#define WCL_CORE_0_ENTRY_1_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_1_ADDR_S 0 + +/** WCL_Core_0_ENTRY_2_ADDR_REG register + * Core_0 Entry 2 address configuration Register + */ +#define WCL_CORE_0_ENTRY_2_ADDR_REG (DR_REG_WCL_BASE + 0x4) +/** WCL_CORE_0_ENTRY_2_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 2 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_2_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_2_ADDR_M (WCL_CORE_0_ENTRY_2_ADDR_V << WCL_CORE_0_ENTRY_2_ADDR_S) +#define WCL_CORE_0_ENTRY_2_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_2_ADDR_S 0 + +/** WCL_Core_0_ENTRY_3_ADDR_REG register + * Core_0 Entry 3 address configuration Register + */ +#define WCL_CORE_0_ENTRY_3_ADDR_REG (DR_REG_WCL_BASE + 0x8) +/** WCL_CORE_0_ENTRY_3_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 3 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_3_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_3_ADDR_M (WCL_CORE_0_ENTRY_3_ADDR_V << WCL_CORE_0_ENTRY_3_ADDR_S) +#define WCL_CORE_0_ENTRY_3_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_3_ADDR_S 0 + +/** WCL_Core_0_ENTRY_4_ADDR_REG register + * Core_0 Entry 4 address configuration Register + */ +#define WCL_CORE_0_ENTRY_4_ADDR_REG (DR_REG_WCL_BASE + 0xc) +/** WCL_CORE_0_ENTRY_4_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 4 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_4_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_4_ADDR_M (WCL_CORE_0_ENTRY_4_ADDR_V << WCL_CORE_0_ENTRY_4_ADDR_S) +#define WCL_CORE_0_ENTRY_4_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_4_ADDR_S 0 + +/** WCL_Core_0_ENTRY_5_ADDR_REG register + * Core_0 Entry 5 address configuration Register + */ +#define WCL_CORE_0_ENTRY_5_ADDR_REG (DR_REG_WCL_BASE + 0x10) +/** WCL_CORE_0_ENTRY_5_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 5 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_5_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_5_ADDR_M (WCL_CORE_0_ENTRY_5_ADDR_V << WCL_CORE_0_ENTRY_5_ADDR_S) +#define WCL_CORE_0_ENTRY_5_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_5_ADDR_S 0 + +/** WCL_Core_0_ENTRY_6_ADDR_REG register + * Core_0 Entry 6 address configuration Register + */ +#define WCL_CORE_0_ENTRY_6_ADDR_REG (DR_REG_WCL_BASE + 0x14) +/** WCL_CORE_0_ENTRY_6_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 6 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_6_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_6_ADDR_M (WCL_CORE_0_ENTRY_6_ADDR_V << WCL_CORE_0_ENTRY_6_ADDR_S) +#define WCL_CORE_0_ENTRY_6_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_6_ADDR_S 0 + +/** WCL_Core_0_ENTRY_7_ADDR_REG register + * Core_0 Entry 7 address configuration Register + */ +#define WCL_CORE_0_ENTRY_7_ADDR_REG (DR_REG_WCL_BASE + 0x18) +/** WCL_CORE_0_ENTRY_7_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 7 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_7_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_7_ADDR_M (WCL_CORE_0_ENTRY_7_ADDR_V << WCL_CORE_0_ENTRY_7_ADDR_S) +#define WCL_CORE_0_ENTRY_7_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_7_ADDR_S 0 + +/** WCL_Core_0_ENTRY_8_ADDR_REG register + * Core_0 Entry 8 address configuration Register + */ +#define WCL_CORE_0_ENTRY_8_ADDR_REG (DR_REG_WCL_BASE + 0x1c) +/** WCL_CORE_0_ENTRY_8_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 8 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_8_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_8_ADDR_M (WCL_CORE_0_ENTRY_8_ADDR_V << WCL_CORE_0_ENTRY_8_ADDR_S) +#define WCL_CORE_0_ENTRY_8_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_8_ADDR_S 0 + +/** WCL_Core_0_ENTRY_9_ADDR_REG register + * Core_0 Entry 9 address configuration Register + */ +#define WCL_CORE_0_ENTRY_9_ADDR_REG (DR_REG_WCL_BASE + 0x20) +/** WCL_CORE_0_ENTRY_9_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 9 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_9_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_9_ADDR_M (WCL_CORE_0_ENTRY_9_ADDR_V << WCL_CORE_0_ENTRY_9_ADDR_S) +#define WCL_CORE_0_ENTRY_9_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_9_ADDR_S 0 + +/** WCL_Core_0_ENTRY_10_ADDR_REG register + * Core_0 Entry 10 address configuration Register + */ +#define WCL_CORE_0_ENTRY_10_ADDR_REG (DR_REG_WCL_BASE + 0x24) +/** WCL_CORE_0_ENTRY_10_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 10 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_10_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_10_ADDR_M (WCL_CORE_0_ENTRY_10_ADDR_V << WCL_CORE_0_ENTRY_10_ADDR_S) +#define WCL_CORE_0_ENTRY_10_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_10_ADDR_S 0 + +/** WCL_Core_0_ENTRY_11_ADDR_REG register + * Core_0 Entry 11 address configuration Register + */ +#define WCL_CORE_0_ENTRY_11_ADDR_REG (DR_REG_WCL_BASE + 0x28) +/** WCL_CORE_0_ENTRY_11_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 11 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_11_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_11_ADDR_M (WCL_CORE_0_ENTRY_11_ADDR_V << WCL_CORE_0_ENTRY_11_ADDR_S) +#define WCL_CORE_0_ENTRY_11_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_11_ADDR_S 0 + +/** WCL_Core_0_ENTRY_12_ADDR_REG register + * Core_0 Entry 12 address configuration Register + */ +#define WCL_CORE_0_ENTRY_12_ADDR_REG (DR_REG_WCL_BASE + 0x2c) +/** WCL_CORE_0_ENTRY_12_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 12 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_12_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_12_ADDR_M (WCL_CORE_0_ENTRY_12_ADDR_V << WCL_CORE_0_ENTRY_12_ADDR_S) +#define WCL_CORE_0_ENTRY_12_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_12_ADDR_S 0 + +/** WCL_Core_0_ENTRY_13_ADDR_REG register + * Core_0 Entry 13 address configuration Register + */ +#define WCL_CORE_0_ENTRY_13_ADDR_REG (DR_REG_WCL_BASE + 0x30) +/** WCL_CORE_0_ENTRY_13_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 13 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_0_ENTRY_13_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_13_ADDR_M (WCL_CORE_0_ENTRY_13_ADDR_V << WCL_CORE_0_ENTRY_13_ADDR_S) +#define WCL_CORE_0_ENTRY_13_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_ENTRY_13_ADDR_S 0 + +/** WCL_Core_0_ENTRY_CHECK_REG register + * Core_0 Entry check configuration Register + */ +#define WCL_CORE_0_ENTRY_CHECK_REG (DR_REG_WCL_BASE + 0x7c) +/** WCL_CORE_0_ENTRY_CHECK : R/W; bitpos: [13:1]; default: 1; + * This filed is used to enable entry address check + */ +#define WCL_CORE_0_ENTRY_CHECK 0x00001FFFU +#define WCL_CORE_0_ENTRY_CHECK_M (WCL_CORE_0_ENTRY_CHECK_V << WCL_CORE_0_ENTRY_CHECK_S) +#define WCL_CORE_0_ENTRY_CHECK_V 0x00001FFFU +#define WCL_CORE_0_ENTRY_CHECK_S 1 + +/** WCL_Core_0_STATUSTABLE1_REG register + * Status register of world switch of entry 1 + */ +#define WCL_CORE_0_STATUSTABLE1_REG (DR_REG_WCL_BASE + 0x80) +/** WCL_CORE_0_FROM_WORLD_1 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 1 + */ +#define WCL_CORE_0_FROM_WORLD_1 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_1_M (WCL_CORE_0_FROM_WORLD_1_V << WCL_CORE_0_FROM_WORLD_1_S) +#define WCL_CORE_0_FROM_WORLD_1_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_1_S 0 +/** WCL_CORE_0_FROM_ENTRY_1 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 1 + */ +#define WCL_CORE_0_FROM_ENTRY_1 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_1_M (WCL_CORE_0_FROM_ENTRY_1_V << WCL_CORE_0_FROM_ENTRY_1_S) +#define WCL_CORE_0_FROM_ENTRY_1_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_1_S 1 +/** WCL_CORE_0_CURRENT_1 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 1 + */ +#define WCL_CORE_0_CURRENT_1 (BIT(5)) +#define WCL_CORE_0_CURRENT_1_M (WCL_CORE_0_CURRENT_1_V << WCL_CORE_0_CURRENT_1_S) +#define WCL_CORE_0_CURRENT_1_V 0x00000001U +#define WCL_CORE_0_CURRENT_1_S 5 + +/** WCL_Core_0_STATUSTABLE2_REG register + * Status register of world switch of entry 2 + */ +#define WCL_CORE_0_STATUSTABLE2_REG (DR_REG_WCL_BASE + 0x84) +/** WCL_CORE_0_FROM_WORLD_2 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 2 + */ +#define WCL_CORE_0_FROM_WORLD_2 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_2_M (WCL_CORE_0_FROM_WORLD_2_V << WCL_CORE_0_FROM_WORLD_2_S) +#define WCL_CORE_0_FROM_WORLD_2_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_2_S 0 +/** WCL_CORE_0_FROM_ENTRY_2 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 2 + */ +#define WCL_CORE_0_FROM_ENTRY_2 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_2_M (WCL_CORE_0_FROM_ENTRY_2_V << WCL_CORE_0_FROM_ENTRY_2_S) +#define WCL_CORE_0_FROM_ENTRY_2_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_2_S 1 +/** WCL_CORE_0_CURRENT_2 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 2 + */ +#define WCL_CORE_0_CURRENT_2 (BIT(5)) +#define WCL_CORE_0_CURRENT_2_M (WCL_CORE_0_CURRENT_2_V << WCL_CORE_0_CURRENT_2_S) +#define WCL_CORE_0_CURRENT_2_V 0x00000001U +#define WCL_CORE_0_CURRENT_2_S 5 + +/** WCL_Core_0_STATUSTABLE3_REG register + * Status register of world switch of entry 3 + */ +#define WCL_CORE_0_STATUSTABLE3_REG (DR_REG_WCL_BASE + 0x88) +/** WCL_CORE_0_FROM_WORLD_3 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 3 + */ +#define WCL_CORE_0_FROM_WORLD_3 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_3_M (WCL_CORE_0_FROM_WORLD_3_V << WCL_CORE_0_FROM_WORLD_3_S) +#define WCL_CORE_0_FROM_WORLD_3_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_3_S 0 +/** WCL_CORE_0_FROM_ENTRY_3 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 3 + */ +#define WCL_CORE_0_FROM_ENTRY_3 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_3_M (WCL_CORE_0_FROM_ENTRY_3_V << WCL_CORE_0_FROM_ENTRY_3_S) +#define WCL_CORE_0_FROM_ENTRY_3_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_3_S 1 +/** WCL_CORE_0_CURRENT_3 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 3 + */ +#define WCL_CORE_0_CURRENT_3 (BIT(5)) +#define WCL_CORE_0_CURRENT_3_M (WCL_CORE_0_CURRENT_3_V << WCL_CORE_0_CURRENT_3_S) +#define WCL_CORE_0_CURRENT_3_V 0x00000001U +#define WCL_CORE_0_CURRENT_3_S 5 + +/** WCL_Core_0_STATUSTABLE4_REG register + * Status register of world switch of entry 4 + */ +#define WCL_CORE_0_STATUSTABLE4_REG (DR_REG_WCL_BASE + 0x8c) +/** WCL_CORE_0_FROM_WORLD_4 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 4 + */ +#define WCL_CORE_0_FROM_WORLD_4 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_4_M (WCL_CORE_0_FROM_WORLD_4_V << WCL_CORE_0_FROM_WORLD_4_S) +#define WCL_CORE_0_FROM_WORLD_4_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_4_S 0 +/** WCL_CORE_0_FROM_ENTRY_4 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 4 + */ +#define WCL_CORE_0_FROM_ENTRY_4 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_4_M (WCL_CORE_0_FROM_ENTRY_4_V << WCL_CORE_0_FROM_ENTRY_4_S) +#define WCL_CORE_0_FROM_ENTRY_4_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_4_S 1 +/** WCL_CORE_0_CURRENT_4 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 4 + */ +#define WCL_CORE_0_CURRENT_4 (BIT(5)) +#define WCL_CORE_0_CURRENT_4_M (WCL_CORE_0_CURRENT_4_V << WCL_CORE_0_CURRENT_4_S) +#define WCL_CORE_0_CURRENT_4_V 0x00000001U +#define WCL_CORE_0_CURRENT_4_S 5 + +/** WCL_Core_0_STATUSTABLE5_REG register + * Status register of world switch of entry 5 + */ +#define WCL_CORE_0_STATUSTABLE5_REG (DR_REG_WCL_BASE + 0x90) +/** WCL_CORE_0_FROM_WORLD_5 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 5 + */ +#define WCL_CORE_0_FROM_WORLD_5 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_5_M (WCL_CORE_0_FROM_WORLD_5_V << WCL_CORE_0_FROM_WORLD_5_S) +#define WCL_CORE_0_FROM_WORLD_5_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_5_S 0 +/** WCL_CORE_0_FROM_ENTRY_5 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 5 + */ +#define WCL_CORE_0_FROM_ENTRY_5 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_5_M (WCL_CORE_0_FROM_ENTRY_5_V << WCL_CORE_0_FROM_ENTRY_5_S) +#define WCL_CORE_0_FROM_ENTRY_5_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_5_S 1 +/** WCL_CORE_0_CURRENT_5 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 5 + */ +#define WCL_CORE_0_CURRENT_5 (BIT(5)) +#define WCL_CORE_0_CURRENT_5_M (WCL_CORE_0_CURRENT_5_V << WCL_CORE_0_CURRENT_5_S) +#define WCL_CORE_0_CURRENT_5_V 0x00000001U +#define WCL_CORE_0_CURRENT_5_S 5 + +/** WCL_Core_0_STATUSTABLE6_REG register + * Status register of world switch of entry 6 + */ +#define WCL_CORE_0_STATUSTABLE6_REG (DR_REG_WCL_BASE + 0x94) +/** WCL_CORE_0_FROM_WORLD_6 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 6 + */ +#define WCL_CORE_0_FROM_WORLD_6 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_6_M (WCL_CORE_0_FROM_WORLD_6_V << WCL_CORE_0_FROM_WORLD_6_S) +#define WCL_CORE_0_FROM_WORLD_6_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_6_S 0 +/** WCL_CORE_0_FROM_ENTRY_6 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 6 + */ +#define WCL_CORE_0_FROM_ENTRY_6 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_6_M (WCL_CORE_0_FROM_ENTRY_6_V << WCL_CORE_0_FROM_ENTRY_6_S) +#define WCL_CORE_0_FROM_ENTRY_6_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_6_S 1 +/** WCL_CORE_0_CURRENT_6 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 6 + */ +#define WCL_CORE_0_CURRENT_6 (BIT(5)) +#define WCL_CORE_0_CURRENT_6_M (WCL_CORE_0_CURRENT_6_V << WCL_CORE_0_CURRENT_6_S) +#define WCL_CORE_0_CURRENT_6_V 0x00000001U +#define WCL_CORE_0_CURRENT_6_S 5 + +/** WCL_Core_0_STATUSTABLE7_REG register + * Status register of world switch of entry 7 + */ +#define WCL_CORE_0_STATUSTABLE7_REG (DR_REG_WCL_BASE + 0x98) +/** WCL_CORE_0_FROM_WORLD_7 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 7 + */ +#define WCL_CORE_0_FROM_WORLD_7 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_7_M (WCL_CORE_0_FROM_WORLD_7_V << WCL_CORE_0_FROM_WORLD_7_S) +#define WCL_CORE_0_FROM_WORLD_7_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_7_S 0 +/** WCL_CORE_0_FROM_ENTRY_7 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 7 + */ +#define WCL_CORE_0_FROM_ENTRY_7 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_7_M (WCL_CORE_0_FROM_ENTRY_7_V << WCL_CORE_0_FROM_ENTRY_7_S) +#define WCL_CORE_0_FROM_ENTRY_7_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_7_S 1 +/** WCL_CORE_0_CURRENT_7 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 7 + */ +#define WCL_CORE_0_CURRENT_7 (BIT(5)) +#define WCL_CORE_0_CURRENT_7_M (WCL_CORE_0_CURRENT_7_V << WCL_CORE_0_CURRENT_7_S) +#define WCL_CORE_0_CURRENT_7_V 0x00000001U +#define WCL_CORE_0_CURRENT_7_S 5 + +/** WCL_Core_0_STATUSTABLE8_REG register + * Status register of world switch of entry 8 + */ +#define WCL_CORE_0_STATUSTABLE8_REG (DR_REG_WCL_BASE + 0x9c) +/** WCL_CORE_0_FROM_WORLD_8 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 8 + */ +#define WCL_CORE_0_FROM_WORLD_8 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_8_M (WCL_CORE_0_FROM_WORLD_8_V << WCL_CORE_0_FROM_WORLD_8_S) +#define WCL_CORE_0_FROM_WORLD_8_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_8_S 0 +/** WCL_CORE_0_FROM_ENTRY_8 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 8 + */ +#define WCL_CORE_0_FROM_ENTRY_8 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_8_M (WCL_CORE_0_FROM_ENTRY_8_V << WCL_CORE_0_FROM_ENTRY_8_S) +#define WCL_CORE_0_FROM_ENTRY_8_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_8_S 1 +/** WCL_CORE_0_CURRENT_8 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 8 + */ +#define WCL_CORE_0_CURRENT_8 (BIT(5)) +#define WCL_CORE_0_CURRENT_8_M (WCL_CORE_0_CURRENT_8_V << WCL_CORE_0_CURRENT_8_S) +#define WCL_CORE_0_CURRENT_8_V 0x00000001U +#define WCL_CORE_0_CURRENT_8_S 5 + +/** WCL_Core_0_STATUSTABLE9_REG register + * Status register of world switch of entry 9 + */ +#define WCL_CORE_0_STATUSTABLE9_REG (DR_REG_WCL_BASE + 0xa0) +/** WCL_CORE_0_FROM_WORLD_9 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 9 + */ +#define WCL_CORE_0_FROM_WORLD_9 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_9_M (WCL_CORE_0_FROM_WORLD_9_V << WCL_CORE_0_FROM_WORLD_9_S) +#define WCL_CORE_0_FROM_WORLD_9_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_9_S 0 +/** WCL_CORE_0_FROM_ENTRY_9 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 9 + */ +#define WCL_CORE_0_FROM_ENTRY_9 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_9_M (WCL_CORE_0_FROM_ENTRY_9_V << WCL_CORE_0_FROM_ENTRY_9_S) +#define WCL_CORE_0_FROM_ENTRY_9_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_9_S 1 +/** WCL_CORE_0_CURRENT_9 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 9 + */ +#define WCL_CORE_0_CURRENT_9 (BIT(5)) +#define WCL_CORE_0_CURRENT_9_M (WCL_CORE_0_CURRENT_9_V << WCL_CORE_0_CURRENT_9_S) +#define WCL_CORE_0_CURRENT_9_V 0x00000001U +#define WCL_CORE_0_CURRENT_9_S 5 + +/** WCL_Core_0_STATUSTABLE10_REG register + * Status register of world switch of entry 10 + */ +#define WCL_CORE_0_STATUSTABLE10_REG (DR_REG_WCL_BASE + 0xa4) +/** WCL_CORE_0_FROM_WORLD_10 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 10 + */ +#define WCL_CORE_0_FROM_WORLD_10 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_10_M (WCL_CORE_0_FROM_WORLD_10_V << WCL_CORE_0_FROM_WORLD_10_S) +#define WCL_CORE_0_FROM_WORLD_10_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_10_S 0 +/** WCL_CORE_0_FROM_ENTRY_10 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 10 + */ +#define WCL_CORE_0_FROM_ENTRY_10 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_10_M (WCL_CORE_0_FROM_ENTRY_10_V << WCL_CORE_0_FROM_ENTRY_10_S) +#define WCL_CORE_0_FROM_ENTRY_10_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_10_S 1 +/** WCL_CORE_0_CURRENT_10 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 10 + */ +#define WCL_CORE_0_CURRENT_10 (BIT(5)) +#define WCL_CORE_0_CURRENT_10_M (WCL_CORE_0_CURRENT_10_V << WCL_CORE_0_CURRENT_10_S) +#define WCL_CORE_0_CURRENT_10_V 0x00000001U +#define WCL_CORE_0_CURRENT_10_S 5 + +/** WCL_Core_0_STATUSTABLE11_REG register + * Status register of world switch of entry 11 + */ +#define WCL_CORE_0_STATUSTABLE11_REG (DR_REG_WCL_BASE + 0xa8) +/** WCL_CORE_0_FROM_WORLD_11 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 11 + */ +#define WCL_CORE_0_FROM_WORLD_11 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_11_M (WCL_CORE_0_FROM_WORLD_11_V << WCL_CORE_0_FROM_WORLD_11_S) +#define WCL_CORE_0_FROM_WORLD_11_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_11_S 0 +/** WCL_CORE_0_FROM_ENTRY_11 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 11 + */ +#define WCL_CORE_0_FROM_ENTRY_11 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_11_M (WCL_CORE_0_FROM_ENTRY_11_V << WCL_CORE_0_FROM_ENTRY_11_S) +#define WCL_CORE_0_FROM_ENTRY_11_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_11_S 1 +/** WCL_CORE_0_CURRENT_11 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 11 + */ +#define WCL_CORE_0_CURRENT_11 (BIT(5)) +#define WCL_CORE_0_CURRENT_11_M (WCL_CORE_0_CURRENT_11_V << WCL_CORE_0_CURRENT_11_S) +#define WCL_CORE_0_CURRENT_11_V 0x00000001U +#define WCL_CORE_0_CURRENT_11_S 5 + +/** WCL_Core_0_STATUSTABLE12_REG register + * Status register of world switch of entry 12 + */ +#define WCL_CORE_0_STATUSTABLE12_REG (DR_REG_WCL_BASE + 0xac) +/** WCL_CORE_0_FROM_WORLD_12 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 12 + */ +#define WCL_CORE_0_FROM_WORLD_12 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_12_M (WCL_CORE_0_FROM_WORLD_12_V << WCL_CORE_0_FROM_WORLD_12_S) +#define WCL_CORE_0_FROM_WORLD_12_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_12_S 0 +/** WCL_CORE_0_FROM_ENTRY_12 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 12 + */ +#define WCL_CORE_0_FROM_ENTRY_12 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_12_M (WCL_CORE_0_FROM_ENTRY_12_V << WCL_CORE_0_FROM_ENTRY_12_S) +#define WCL_CORE_0_FROM_ENTRY_12_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_12_S 1 +/** WCL_CORE_0_CURRENT_12 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 12 + */ +#define WCL_CORE_0_CURRENT_12 (BIT(5)) +#define WCL_CORE_0_CURRENT_12_M (WCL_CORE_0_CURRENT_12_V << WCL_CORE_0_CURRENT_12_S) +#define WCL_CORE_0_CURRENT_12_V 0x00000001U +#define WCL_CORE_0_CURRENT_12_S 5 + +/** WCL_Core_0_STATUSTABLE13_REG register + * Status register of world switch of entry 13 + */ +#define WCL_CORE_0_STATUSTABLE13_REG (DR_REG_WCL_BASE + 0xb0) +/** WCL_CORE_0_FROM_WORLD_13 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 13 + */ +#define WCL_CORE_0_FROM_WORLD_13 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_13_M (WCL_CORE_0_FROM_WORLD_13_V << WCL_CORE_0_FROM_WORLD_13_S) +#define WCL_CORE_0_FROM_WORLD_13_V 0x00000001U +#define WCL_CORE_0_FROM_WORLD_13_S 0 +/** WCL_CORE_0_FROM_ENTRY_13 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 13 + */ +#define WCL_CORE_0_FROM_ENTRY_13 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_13_M (WCL_CORE_0_FROM_ENTRY_13_V << WCL_CORE_0_FROM_ENTRY_13_S) +#define WCL_CORE_0_FROM_ENTRY_13_V 0x0000000FU +#define WCL_CORE_0_FROM_ENTRY_13_S 1 +/** WCL_CORE_0_CURRENT_13 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 13 + */ +#define WCL_CORE_0_CURRENT_13 (BIT(5)) +#define WCL_CORE_0_CURRENT_13_M (WCL_CORE_0_CURRENT_13_V << WCL_CORE_0_CURRENT_13_S) +#define WCL_CORE_0_CURRENT_13_V 0x00000001U +#define WCL_CORE_0_CURRENT_13_S 5 + +/** WCL_Core_0_STATUSTABLE_CURRENT_REG register + * Status register of statustable current + */ +#define WCL_CORE_0_STATUSTABLE_CURRENT_REG (DR_REG_WCL_BASE + 0xfc) +/** WCL_CORE_0_STATUSTABLE_CURRENT : R/W; bitpos: [13:1]; default: 0; + * This field is used to quickly read and rewrite the current field of all STATUSTABLE + * registers,for example,bit 1 represents the current field of STATUSTABLE1,bit2 + * represents the current field of STATUSTABLE2 + */ +#define WCL_CORE_0_STATUSTABLE_CURRENT 0x00001FFFU +#define WCL_CORE_0_STATUSTABLE_CURRENT_M (WCL_CORE_0_STATUSTABLE_CURRENT_V << WCL_CORE_0_STATUSTABLE_CURRENT_S) +#define WCL_CORE_0_STATUSTABLE_CURRENT_V 0x00001FFFU +#define WCL_CORE_0_STATUSTABLE_CURRENT_S 1 + +/** WCL_Core_0_MESSAGE_ADDR_REG register + * Clear writer_buffer write address configuration register + */ +#define WCL_CORE_0_MESSAGE_ADDR_REG (DR_REG_WCL_BASE + 0x100) +/** WCL_CORE_0_MESSAGE_ADDR : R/W; bitpos: [31:0]; default: 0; + * This field is used to set address that need to write when enter WORLD0 + */ +#define WCL_CORE_0_MESSAGE_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_MESSAGE_ADDR_M (WCL_CORE_0_MESSAGE_ADDR_V << WCL_CORE_0_MESSAGE_ADDR_S) +#define WCL_CORE_0_MESSAGE_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_MESSAGE_ADDR_S 0 + +/** WCL_Core_0_MESSAGE_MAX_REG register + * Clear writer_buffer write number configuration register + */ +#define WCL_CORE_0_MESSAGE_MAX_REG (DR_REG_WCL_BASE + 0x104) +/** WCL_CORE_0_MESSAGE_MAX : R/W; bitpos: [3:0]; default: 0; + * This filed is used to set the max value of clear write_buffer + */ +#define WCL_CORE_0_MESSAGE_MAX 0x0000000FU +#define WCL_CORE_0_MESSAGE_MAX_M (WCL_CORE_0_MESSAGE_MAX_V << WCL_CORE_0_MESSAGE_MAX_S) +#define WCL_CORE_0_MESSAGE_MAX_V 0x0000000FU +#define WCL_CORE_0_MESSAGE_MAX_S 0 + +/** WCL_Core_0_MESSAGE_PHASE_REG register + * Clear writer_buffer status register + */ +#define WCL_CORE_0_MESSAGE_PHASE_REG (DR_REG_WCL_BASE + 0x108) +/** WCL_CORE_0_MESSAGE_MATCH : RO; bitpos: [0]; default: 0; + * This bit indicates whether the check is successful + */ +#define WCL_CORE_0_MESSAGE_MATCH (BIT(0)) +#define WCL_CORE_0_MESSAGE_MATCH_M (WCL_CORE_0_MESSAGE_MATCH_V << WCL_CORE_0_MESSAGE_MATCH_S) +#define WCL_CORE_0_MESSAGE_MATCH_V 0x00000001U +#define WCL_CORE_0_MESSAGE_MATCH_S 0 +/** WCL_CORE_0_MESSAGE_EXPECT : RO; bitpos: [4:1]; default: 0; + * This field indicates the data to be written next time + */ +#define WCL_CORE_0_MESSAGE_EXPECT 0x0000000FU +#define WCL_CORE_0_MESSAGE_EXPECT_M (WCL_CORE_0_MESSAGE_EXPECT_V << WCL_CORE_0_MESSAGE_EXPECT_S) +#define WCL_CORE_0_MESSAGE_EXPECT_V 0x0000000FU +#define WCL_CORE_0_MESSAGE_EXPECT_S 1 +/** WCL_CORE_0_MESSAGE_DATAPHASE : RO; bitpos: [5]; default: 0; + * If this bit is 1, it means that is checking clear write_buffer operation,and is + * checking data + */ +#define WCL_CORE_0_MESSAGE_DATAPHASE (BIT(5)) +#define WCL_CORE_0_MESSAGE_DATAPHASE_M (WCL_CORE_0_MESSAGE_DATAPHASE_V << WCL_CORE_0_MESSAGE_DATAPHASE_S) +#define WCL_CORE_0_MESSAGE_DATAPHASE_V 0x00000001U +#define WCL_CORE_0_MESSAGE_DATAPHASE_S 5 +/** WCL_CORE_0_MESSAGE_ADDRESSPHASE : RO; bitpos: [6]; default: 0; + * If this bit is 1, it means that is checking clear write_buffer operation,and is + * checking address. + */ +#define WCL_CORE_0_MESSAGE_ADDRESSPHASE (BIT(6)) +#define WCL_CORE_0_MESSAGE_ADDRESSPHASE_M (WCL_CORE_0_MESSAGE_ADDRESSPHASE_V << WCL_CORE_0_MESSAGE_ADDRESSPHASE_S) +#define WCL_CORE_0_MESSAGE_ADDRESSPHASE_V 0x00000001U +#define WCL_CORE_0_MESSAGE_ADDRESSPHASE_S 6 + +/** WCL_Core_0_World_TRIGGER_ADDR_REG register + * Core_0 trigger address configuration Register + */ +#define WCL_CORE_0_WORLD_TRIGGER_ADDR_REG (DR_REG_WCL_BASE + 0x140) +/** WCL_CORE_0_WORLD_TRIGGER_ADDR : RW; bitpos: [31:0]; default: 0; + * This field is used to configure the entry address from WORLD0 to WORLD1,when the + * CPU executes to this address,switch to WORLD1 + */ +#define WCL_CORE_0_WORLD_TRIGGER_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_WORLD_TRIGGER_ADDR_M (WCL_CORE_0_WORLD_TRIGGER_ADDR_V << WCL_CORE_0_WORLD_TRIGGER_ADDR_S) +#define WCL_CORE_0_WORLD_TRIGGER_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_WORLD_TRIGGER_ADDR_S 0 + +/** WCL_Core_0_World_PREPARE_REG register + * Core_0 prepare world configuration Register + */ +#define WCL_CORE_0_WORLD_PREPARE_REG (DR_REG_WCL_BASE + 0x144) +/** WCL_CORE_0_WORLD_PREPARE : R/W; bitpos: [1:0]; default: 0; + * This field to used to set world to enter, 2'b01 means WORLD0, 2'b10 means WORLD1 + */ +#define WCL_CORE_0_WORLD_PREPARE 0x00000003U +#define WCL_CORE_0_WORLD_PREPARE_M (WCL_CORE_0_WORLD_PREPARE_V << WCL_CORE_0_WORLD_PREPARE_S) +#define WCL_CORE_0_WORLD_PREPARE_V 0x00000003U +#define WCL_CORE_0_WORLD_PREPARE_S 0 + +/** WCL_Core_0_World_UPDATE_REG register + * Core_0 configuration update register + */ +#define WCL_CORE_0_WORLD_UPDATE_REG (DR_REG_WCL_BASE + 0x148) +/** WCL_CORE_0_UPDATE : WO; bitpos: [31:0]; default: 0; + * This field is used to update configuration completed, can write any value,the + * hardware only checks the write operation of this register and does not case about + * its value + */ +#define WCL_CORE_0_UPDATE 0xFFFFFFFFU +#define WCL_CORE_0_UPDATE_M (WCL_CORE_0_UPDATE_V << WCL_CORE_0_UPDATE_S) +#define WCL_CORE_0_UPDATE_V 0xFFFFFFFFU +#define WCL_CORE_0_UPDATE_S 0 + +/** WCL_Core_0_World_Cancel_REG register + * Core_0 configuration cancel register + */ +#define WCL_CORE_0_WORLD_CANCEL_REG (DR_REG_WCL_BASE + 0x14c) +/** WCL_CORE_0_WORLD_CANCEL : WO; bitpos: [31:0]; default: 0; + * This field is used to cancel switch world configuration,if the trigger address and + * update configuration complete,use this register to cancel world switch, jujst need + * write any value,the hardware only checks the write operation of this register and + * does not case about its value + */ +#define WCL_CORE_0_WORLD_CANCEL 0xFFFFFFFFU +#define WCL_CORE_0_WORLD_CANCEL_M (WCL_CORE_0_WORLD_CANCEL_V << WCL_CORE_0_WORLD_CANCEL_S) +#define WCL_CORE_0_WORLD_CANCEL_V 0xFFFFFFFFU +#define WCL_CORE_0_WORLD_CANCEL_S 0 + +/** WCL_Core_0_World_IRam0_REG register + * Core_0 Iram0 world register + */ +#define WCL_CORE_0_WORLD_IRAM0_REG (DR_REG_WCL_BASE + 0x150) +/** WCL_CORE_0_WORLD_IRAM0 : R/W; bitpos: [1:0]; default: 0; + * this field is used to read current world of Iram0 bus + */ +#define WCL_CORE_0_WORLD_IRAM0 0x00000003U +#define WCL_CORE_0_WORLD_IRAM0_M (WCL_CORE_0_WORLD_IRAM0_V << WCL_CORE_0_WORLD_IRAM0_S) +#define WCL_CORE_0_WORLD_IRAM0_V 0x00000003U +#define WCL_CORE_0_WORLD_IRAM0_S 0 + +/** WCL_Core_0_World_DRam0_PIF_REG register + * Core_0 dram0 and PIF world register + */ +#define WCL_CORE_0_WORLD_DRAM0_PIF_REG (DR_REG_WCL_BASE + 0x154) +/** WCL_CORE_0_WORLD_DRAM0_PIF : R/W; bitpos: [1:0]; default: 0; + * this field is used to read current world of Dram0 bus and PIF bus + */ +#define WCL_CORE_0_WORLD_DRAM0_PIF 0x00000003U +#define WCL_CORE_0_WORLD_DRAM0_PIF_M (WCL_CORE_0_WORLD_DRAM0_PIF_V << WCL_CORE_0_WORLD_DRAM0_PIF_S) +#define WCL_CORE_0_WORLD_DRAM0_PIF_V 0x00000003U +#define WCL_CORE_0_WORLD_DRAM0_PIF_S 0 + +/** WCL_Core_0_World_Phase_REG register + * Core_0 world status register + */ +#define WCL_CORE_0_WORLD_PHASE_REG (DR_REG_WCL_BASE + 0x158) +/** WCL_CORE_0_WORLD_PHASE : RO; bitpos: [0]; default: 0; + * This bit indicates whether is preparing to switch to WORLD1, 1 means value. + */ +#define WCL_CORE_0_WORLD_PHASE (BIT(0)) +#define WCL_CORE_0_WORLD_PHASE_M (WCL_CORE_0_WORLD_PHASE_V << WCL_CORE_0_WORLD_PHASE_S) +#define WCL_CORE_0_WORLD_PHASE_V 0x00000001U +#define WCL_CORE_0_WORLD_PHASE_S 0 + +/** WCL_Core_0_NMI_MASK_ENABLE_REG register + * Core_0 NMI mask enable register + */ +#define WCL_CORE_0_NMI_MASK_ENABLE_REG (DR_REG_WCL_BASE + 0x180) +/** WCL_CORE_0_NMI_MASK_ENABLE : WO; bitpos: [31:0]; default: 0; + * this field is used to set NMI mask,it can write any value,when write this + * register,the hardware start masking NMI interrupt + */ +#define WCL_CORE_0_NMI_MASK_ENABLE 0xFFFFFFFFU +#define WCL_CORE_0_NMI_MASK_ENABLE_M (WCL_CORE_0_NMI_MASK_ENABLE_V << WCL_CORE_0_NMI_MASK_ENABLE_S) +#define WCL_CORE_0_NMI_MASK_ENABLE_V 0xFFFFFFFFU +#define WCL_CORE_0_NMI_MASK_ENABLE_S 0 + +/** WCL_Core_0_NMI_MASK_TRIGGER_ADDR_REG register + * Core_0 NMI mask trigger address register + */ +#define WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_REG (DR_REG_WCL_BASE + 0x184) +/** WCL_CORE_0_NMI_MASK_TRIGGER_ADDR : R/W; bitpos: [31:0]; default: 0; + * this field to used to set trigger address, when CPU executes to this address,NMI + * mask automatically fails + */ +#define WCL_CORE_0_NMI_MASK_TRIGGER_ADDR 0xFFFFFFFFU +#define WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_M (WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_V << WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_S) +#define WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_S 0 + +/** WCL_Core_0_NMI_MASK_DISABLE_REG register + * Core_0 NMI mask disable register + */ +#define WCL_CORE_0_NMI_MASK_DISABLE_REG (DR_REG_WCL_BASE + 0x188) +/** WCL_CORE_0_NMI_MASK_DISABLE : WO; bitpos: [31:0]; default: 0; + * this field is used to disable NMI mask,it will not take effect immediately,only + * when the CPU executes to the trigger address will it start to cancel NMI mask + */ +#define WCL_CORE_0_NMI_MASK_DISABLE 0xFFFFFFFFU +#define WCL_CORE_0_NMI_MASK_DISABLE_M (WCL_CORE_0_NMI_MASK_DISABLE_V << WCL_CORE_0_NMI_MASK_DISABLE_S) +#define WCL_CORE_0_NMI_MASK_DISABLE_V 0xFFFFFFFFU +#define WCL_CORE_0_NMI_MASK_DISABLE_S 0 + +/** WCL_Core_0_NMI_MASK_CANCLE_REG register + * Core_0 NMI mask disable register + */ +#define WCL_CORE_0_NMI_MASK_CANCLE_REG (DR_REG_WCL_BASE + 0x18c) +/** WCL_CORE_0_NMI_MASK_CANCEL : WO; bitpos: [31:0]; default: 0; + * this field is used to cancel NMI mask disable function. + */ +#define WCL_CORE_0_NMI_MASK_CANCEL 0xFFFFFFFFU +#define WCL_CORE_0_NMI_MASK_CANCEL_M (WCL_CORE_0_NMI_MASK_CANCEL_V << WCL_CORE_0_NMI_MASK_CANCEL_S) +#define WCL_CORE_0_NMI_MASK_CANCEL_V 0xFFFFFFFFU +#define WCL_CORE_0_NMI_MASK_CANCEL_S 0 + +/** WCL_Core_0_NMI_MASK_REG register + * Core_0 NMI mask register + */ +#define WCL_CORE_0_NMI_MASK_REG (DR_REG_WCL_BASE + 0x190) +/** WCL_CORE_0_NMI_MASK : R/W; bitpos: [0]; default: 0; + * this bit is used to mask NMI interrupt,it can directly mask NMI interrupt + */ +#define WCL_CORE_0_NMI_MASK (BIT(0)) +#define WCL_CORE_0_NMI_MASK_M (WCL_CORE_0_NMI_MASK_V << WCL_CORE_0_NMI_MASK_S) +#define WCL_CORE_0_NMI_MASK_V 0x00000001U +#define WCL_CORE_0_NMI_MASK_S 0 + +/** WCL_Core_0_NMI_MASK_PHASE_REG register + * Core_0 NMI mask phase register + */ +#define WCL_CORE_0_NMI_MASK_PHASE_REG (DR_REG_WCL_BASE + 0x194) +/** WCL_CORE_0_NMI_MASK_PHASE : RO; bitpos: [0]; default: 0; + * this bit is used to indicates whether the NMI interrupt is being masked, 1 means + * NMI interrupt is being masked + */ +#define WCL_CORE_0_NMI_MASK_PHASE (BIT(0)) +#define WCL_CORE_0_NMI_MASK_PHASE_M (WCL_CORE_0_NMI_MASK_PHASE_V << WCL_CORE_0_NMI_MASK_PHASE_S) +#define WCL_CORE_0_NMI_MASK_PHASE_V 0x00000001U +#define WCL_CORE_0_NMI_MASK_PHASE_S 0 + +/** WCL_Core_1_ENTRY_1_ADDR_REG register + * Core_1 Entry 1 address configuration Register + */ +#define WCL_CORE_1_ENTRY_1_ADDR_REG (DR_REG_WCL_BASE + 0x400) +/** WCL_CORE_1_ENTRY_1_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 1 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_1_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_1_ADDR_M (WCL_CORE_1_ENTRY_1_ADDR_V << WCL_CORE_1_ENTRY_1_ADDR_S) +#define WCL_CORE_1_ENTRY_1_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_1_ADDR_S 0 + +/** WCL_Core_1_ENTRY_2_ADDR_REG register + * Core_1 Entry 2 address configuration Register + */ +#define WCL_CORE_1_ENTRY_2_ADDR_REG (DR_REG_WCL_BASE + 0x404) +/** WCL_CORE_1_ENTRY_2_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 2 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_2_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_2_ADDR_M (WCL_CORE_1_ENTRY_2_ADDR_V << WCL_CORE_1_ENTRY_2_ADDR_S) +#define WCL_CORE_1_ENTRY_2_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_2_ADDR_S 0 + +/** WCL_Core_1_ENTRY_3_ADDR_REG register + * Core_1 Entry 3 address configuration Register + */ +#define WCL_CORE_1_ENTRY_3_ADDR_REG (DR_REG_WCL_BASE + 0x408) +/** WCL_CORE_1_ENTRY_3_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 3 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_3_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_3_ADDR_M (WCL_CORE_1_ENTRY_3_ADDR_V << WCL_CORE_1_ENTRY_3_ADDR_S) +#define WCL_CORE_1_ENTRY_3_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_3_ADDR_S 0 + +/** WCL_Core_1_ENTRY_4_ADDR_REG register + * Core_1 Entry 4 address configuration Register + */ +#define WCL_CORE_1_ENTRY_4_ADDR_REG (DR_REG_WCL_BASE + 0x40c) +/** WCL_CORE_1_ENTRY_4_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 4 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_4_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_4_ADDR_M (WCL_CORE_1_ENTRY_4_ADDR_V << WCL_CORE_1_ENTRY_4_ADDR_S) +#define WCL_CORE_1_ENTRY_4_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_4_ADDR_S 0 + +/** WCL_Core_1_ENTRY_5_ADDR_REG register + * Core_1 Entry 5 address configuration Register + */ +#define WCL_CORE_1_ENTRY_5_ADDR_REG (DR_REG_WCL_BASE + 0x410) +/** WCL_CORE_1_ENTRY_5_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 5 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_5_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_5_ADDR_M (WCL_CORE_1_ENTRY_5_ADDR_V << WCL_CORE_1_ENTRY_5_ADDR_S) +#define WCL_CORE_1_ENTRY_5_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_5_ADDR_S 0 + +/** WCL_Core_1_ENTRY_6_ADDR_REG register + * Core_1 Entry 6 address configuration Register + */ +#define WCL_CORE_1_ENTRY_6_ADDR_REG (DR_REG_WCL_BASE + 0x414) +/** WCL_CORE_1_ENTRY_6_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 6 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_6_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_6_ADDR_M (WCL_CORE_1_ENTRY_6_ADDR_V << WCL_CORE_1_ENTRY_6_ADDR_S) +#define WCL_CORE_1_ENTRY_6_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_6_ADDR_S 0 + +/** WCL_Core_1_ENTRY_7_ADDR_REG register + * Core_1 Entry 7 address configuration Register + */ +#define WCL_CORE_1_ENTRY_7_ADDR_REG (DR_REG_WCL_BASE + 0x418) +/** WCL_CORE_1_ENTRY_7_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 7 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_7_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_7_ADDR_M (WCL_CORE_1_ENTRY_7_ADDR_V << WCL_CORE_1_ENTRY_7_ADDR_S) +#define WCL_CORE_1_ENTRY_7_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_7_ADDR_S 0 + +/** WCL_Core_1_ENTRY_8_ADDR_REG register + * Core_1 Entry 8 address configuration Register + */ +#define WCL_CORE_1_ENTRY_8_ADDR_REG (DR_REG_WCL_BASE + 0x41c) +/** WCL_CORE_1_ENTRY_8_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 8 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_8_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_8_ADDR_M (WCL_CORE_1_ENTRY_8_ADDR_V << WCL_CORE_1_ENTRY_8_ADDR_S) +#define WCL_CORE_1_ENTRY_8_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_8_ADDR_S 0 + +/** WCL_Core_1_ENTRY_9_ADDR_REG register + * Core_1 Entry 9 address configuration Register + */ +#define WCL_CORE_1_ENTRY_9_ADDR_REG (DR_REG_WCL_BASE + 0x420) +/** WCL_CORE_1_ENTRY_9_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 9 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_9_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_9_ADDR_M (WCL_CORE_1_ENTRY_9_ADDR_V << WCL_CORE_1_ENTRY_9_ADDR_S) +#define WCL_CORE_1_ENTRY_9_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_9_ADDR_S 0 + +/** WCL_Core_1_ENTRY_10_ADDR_REG register + * Core_1 Entry 10 address configuration Register + */ +#define WCL_CORE_1_ENTRY_10_ADDR_REG (DR_REG_WCL_BASE + 0x424) +/** WCL_CORE_1_ENTRY_10_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 10 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_10_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_10_ADDR_M (WCL_CORE_1_ENTRY_10_ADDR_V << WCL_CORE_1_ENTRY_10_ADDR_S) +#define WCL_CORE_1_ENTRY_10_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_10_ADDR_S 0 + +/** WCL_Core_1_ENTRY_11_ADDR_REG register + * Core_1 Entry 11 address configuration Register + */ +#define WCL_CORE_1_ENTRY_11_ADDR_REG (DR_REG_WCL_BASE + 0x428) +/** WCL_CORE_1_ENTRY_11_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 11 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_11_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_11_ADDR_M (WCL_CORE_1_ENTRY_11_ADDR_V << WCL_CORE_1_ENTRY_11_ADDR_S) +#define WCL_CORE_1_ENTRY_11_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_11_ADDR_S 0 + +/** WCL_Core_1_ENTRY_12_ADDR_REG register + * Core_1 Entry 12 address configuration Register + */ +#define WCL_CORE_1_ENTRY_12_ADDR_REG (DR_REG_WCL_BASE + 0x42c) +/** WCL_CORE_1_ENTRY_12_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 12 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_12_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_12_ADDR_M (WCL_CORE_1_ENTRY_12_ADDR_V << WCL_CORE_1_ENTRY_12_ADDR_S) +#define WCL_CORE_1_ENTRY_12_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_12_ADDR_S 0 + +/** WCL_Core_1_ENTRY_13_ADDR_REG register + * Core_1 Entry 13 address configuration Register + */ +#define WCL_CORE_1_ENTRY_13_ADDR_REG (DR_REG_WCL_BASE + 0x430) +/** WCL_CORE_1_ENTRY_13_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 13 address from WORLD1 to WORLD0 + */ +#define WCL_CORE_1_ENTRY_13_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_13_ADDR_M (WCL_CORE_1_ENTRY_13_ADDR_V << WCL_CORE_1_ENTRY_13_ADDR_S) +#define WCL_CORE_1_ENTRY_13_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_ENTRY_13_ADDR_S 0 + +/** WCL_Core_1_ENTRY_CHECK_REG register + * Core_1 Entry check configuration Register + */ +#define WCL_CORE_1_ENTRY_CHECK_REG (DR_REG_WCL_BASE + 0x47c) +/** WCL_CORE_1_ENTRY_CHECK : R/W; bitpos: [13:1]; default: 1; + * This filed is used to enable entry address check + */ +#define WCL_CORE_1_ENTRY_CHECK 0x00001FFFU +#define WCL_CORE_1_ENTRY_CHECK_M (WCL_CORE_1_ENTRY_CHECK_V << WCL_CORE_1_ENTRY_CHECK_S) +#define WCL_CORE_1_ENTRY_CHECK_V 0x00001FFFU +#define WCL_CORE_1_ENTRY_CHECK_S 1 + +/** WCL_Core_1_STATUSTABLE1_REG register + * Status register of world switch of entry 1 + */ +#define WCL_CORE_1_STATUSTABLE1_REG (DR_REG_WCL_BASE + 0x480) +/** WCL_CORE_1_FROM_WORLD_1 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 1 + */ +#define WCL_CORE_1_FROM_WORLD_1 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_1_M (WCL_CORE_1_FROM_WORLD_1_V << WCL_CORE_1_FROM_WORLD_1_S) +#define WCL_CORE_1_FROM_WORLD_1_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_1_S 0 +/** WCL_CORE_1_FROM_ENTRY_1 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 1 + */ +#define WCL_CORE_1_FROM_ENTRY_1 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_1_M (WCL_CORE_1_FROM_ENTRY_1_V << WCL_CORE_1_FROM_ENTRY_1_S) +#define WCL_CORE_1_FROM_ENTRY_1_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_1_S 1 +/** WCL_CORE_1_CURRENT_1 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 1 + */ +#define WCL_CORE_1_CURRENT_1 (BIT(5)) +#define WCL_CORE_1_CURRENT_1_M (WCL_CORE_1_CURRENT_1_V << WCL_CORE_1_CURRENT_1_S) +#define WCL_CORE_1_CURRENT_1_V 0x00000001U +#define WCL_CORE_1_CURRENT_1_S 5 + +/** WCL_Core_1_STATUSTABLE2_REG register + * Status register of world switch of entry 2 + */ +#define WCL_CORE_1_STATUSTABLE2_REG (DR_REG_WCL_BASE + 0x484) +/** WCL_CORE_1_FROM_WORLD_2 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 2 + */ +#define WCL_CORE_1_FROM_WORLD_2 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_2_M (WCL_CORE_1_FROM_WORLD_2_V << WCL_CORE_1_FROM_WORLD_2_S) +#define WCL_CORE_1_FROM_WORLD_2_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_2_S 0 +/** WCL_CORE_1_FROM_ENTRY_2 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 2 + */ +#define WCL_CORE_1_FROM_ENTRY_2 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_2_M (WCL_CORE_1_FROM_ENTRY_2_V << WCL_CORE_1_FROM_ENTRY_2_S) +#define WCL_CORE_1_FROM_ENTRY_2_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_2_S 1 +/** WCL_CORE_1_CURRENT_2 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 2 + */ +#define WCL_CORE_1_CURRENT_2 (BIT(5)) +#define WCL_CORE_1_CURRENT_2_M (WCL_CORE_1_CURRENT_2_V << WCL_CORE_1_CURRENT_2_S) +#define WCL_CORE_1_CURRENT_2_V 0x00000001U +#define WCL_CORE_1_CURRENT_2_S 5 + +/** WCL_Core_1_STATUSTABLE3_REG register + * Status register of world switch of entry 3 + */ +#define WCL_CORE_1_STATUSTABLE3_REG (DR_REG_WCL_BASE + 0x488) +/** WCL_CORE_1_FROM_WORLD_3 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 3 + */ +#define WCL_CORE_1_FROM_WORLD_3 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_3_M (WCL_CORE_1_FROM_WORLD_3_V << WCL_CORE_1_FROM_WORLD_3_S) +#define WCL_CORE_1_FROM_WORLD_3_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_3_S 0 +/** WCL_CORE_1_FROM_ENTRY_3 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 3 + */ +#define WCL_CORE_1_FROM_ENTRY_3 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_3_M (WCL_CORE_1_FROM_ENTRY_3_V << WCL_CORE_1_FROM_ENTRY_3_S) +#define WCL_CORE_1_FROM_ENTRY_3_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_3_S 1 +/** WCL_CORE_1_CURRENT_3 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 3 + */ +#define WCL_CORE_1_CURRENT_3 (BIT(5)) +#define WCL_CORE_1_CURRENT_3_M (WCL_CORE_1_CURRENT_3_V << WCL_CORE_1_CURRENT_3_S) +#define WCL_CORE_1_CURRENT_3_V 0x00000001U +#define WCL_CORE_1_CURRENT_3_S 5 + +/** WCL_Core_1_STATUSTABLE4_REG register + * Status register of world switch of entry 4 + */ +#define WCL_CORE_1_STATUSTABLE4_REG (DR_REG_WCL_BASE + 0x48c) +/** WCL_CORE_1_FROM_WORLD_4 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 4 + */ +#define WCL_CORE_1_FROM_WORLD_4 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_4_M (WCL_CORE_1_FROM_WORLD_4_V << WCL_CORE_1_FROM_WORLD_4_S) +#define WCL_CORE_1_FROM_WORLD_4_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_4_S 0 +/** WCL_CORE_1_FROM_ENTRY_4 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 4 + */ +#define WCL_CORE_1_FROM_ENTRY_4 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_4_M (WCL_CORE_1_FROM_ENTRY_4_V << WCL_CORE_1_FROM_ENTRY_4_S) +#define WCL_CORE_1_FROM_ENTRY_4_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_4_S 1 +/** WCL_CORE_1_CURRENT_4 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 4 + */ +#define WCL_CORE_1_CURRENT_4 (BIT(5)) +#define WCL_CORE_1_CURRENT_4_M (WCL_CORE_1_CURRENT_4_V << WCL_CORE_1_CURRENT_4_S) +#define WCL_CORE_1_CURRENT_4_V 0x00000001U +#define WCL_CORE_1_CURRENT_4_S 5 + +/** WCL_Core_1_STATUSTABLE5_REG register + * Status register of world switch of entry 5 + */ +#define WCL_CORE_1_STATUSTABLE5_REG (DR_REG_WCL_BASE + 0x490) +/** WCL_CORE_1_FROM_WORLD_5 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 5 + */ +#define WCL_CORE_1_FROM_WORLD_5 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_5_M (WCL_CORE_1_FROM_WORLD_5_V << WCL_CORE_1_FROM_WORLD_5_S) +#define WCL_CORE_1_FROM_WORLD_5_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_5_S 0 +/** WCL_CORE_1_FROM_ENTRY_5 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 5 + */ +#define WCL_CORE_1_FROM_ENTRY_5 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_5_M (WCL_CORE_1_FROM_ENTRY_5_V << WCL_CORE_1_FROM_ENTRY_5_S) +#define WCL_CORE_1_FROM_ENTRY_5_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_5_S 1 +/** WCL_CORE_1_CURRENT_5 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 5 + */ +#define WCL_CORE_1_CURRENT_5 (BIT(5)) +#define WCL_CORE_1_CURRENT_5_M (WCL_CORE_1_CURRENT_5_V << WCL_CORE_1_CURRENT_5_S) +#define WCL_CORE_1_CURRENT_5_V 0x00000001U +#define WCL_CORE_1_CURRENT_5_S 5 + +/** WCL_Core_1_STATUSTABLE6_REG register + * Status register of world switch of entry 6 + */ +#define WCL_CORE_1_STATUSTABLE6_REG (DR_REG_WCL_BASE + 0x494) +/** WCL_CORE_1_FROM_WORLD_6 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 6 + */ +#define WCL_CORE_1_FROM_WORLD_6 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_6_M (WCL_CORE_1_FROM_WORLD_6_V << WCL_CORE_1_FROM_WORLD_6_S) +#define WCL_CORE_1_FROM_WORLD_6_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_6_S 0 +/** WCL_CORE_1_FROM_ENTRY_6 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 6 + */ +#define WCL_CORE_1_FROM_ENTRY_6 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_6_M (WCL_CORE_1_FROM_ENTRY_6_V << WCL_CORE_1_FROM_ENTRY_6_S) +#define WCL_CORE_1_FROM_ENTRY_6_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_6_S 1 +/** WCL_CORE_1_CURRENT_6 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 6 + */ +#define WCL_CORE_1_CURRENT_6 (BIT(5)) +#define WCL_CORE_1_CURRENT_6_M (WCL_CORE_1_CURRENT_6_V << WCL_CORE_1_CURRENT_6_S) +#define WCL_CORE_1_CURRENT_6_V 0x00000001U +#define WCL_CORE_1_CURRENT_6_S 5 + +/** WCL_Core_1_STATUSTABLE7_REG register + * Status register of world switch of entry 7 + */ +#define WCL_CORE_1_STATUSTABLE7_REG (DR_REG_WCL_BASE + 0x498) +/** WCL_CORE_1_FROM_WORLD_7 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 7 + */ +#define WCL_CORE_1_FROM_WORLD_7 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_7_M (WCL_CORE_1_FROM_WORLD_7_V << WCL_CORE_1_FROM_WORLD_7_S) +#define WCL_CORE_1_FROM_WORLD_7_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_7_S 0 +/** WCL_CORE_1_FROM_ENTRY_7 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 7 + */ +#define WCL_CORE_1_FROM_ENTRY_7 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_7_M (WCL_CORE_1_FROM_ENTRY_7_V << WCL_CORE_1_FROM_ENTRY_7_S) +#define WCL_CORE_1_FROM_ENTRY_7_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_7_S 1 +/** WCL_CORE_1_CURRENT_7 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 7 + */ +#define WCL_CORE_1_CURRENT_7 (BIT(5)) +#define WCL_CORE_1_CURRENT_7_M (WCL_CORE_1_CURRENT_7_V << WCL_CORE_1_CURRENT_7_S) +#define WCL_CORE_1_CURRENT_7_V 0x00000001U +#define WCL_CORE_1_CURRENT_7_S 5 + +/** WCL_Core_1_STATUSTABLE8_REG register + * Status register of world switch of entry 8 + */ +#define WCL_CORE_1_STATUSTABLE8_REG (DR_REG_WCL_BASE + 0x49c) +/** WCL_CORE_1_FROM_WORLD_8 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 8 + */ +#define WCL_CORE_1_FROM_WORLD_8 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_8_M (WCL_CORE_1_FROM_WORLD_8_V << WCL_CORE_1_FROM_WORLD_8_S) +#define WCL_CORE_1_FROM_WORLD_8_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_8_S 0 +/** WCL_CORE_1_FROM_ENTRY_8 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 8 + */ +#define WCL_CORE_1_FROM_ENTRY_8 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_8_M (WCL_CORE_1_FROM_ENTRY_8_V << WCL_CORE_1_FROM_ENTRY_8_S) +#define WCL_CORE_1_FROM_ENTRY_8_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_8_S 1 +/** WCL_CORE_1_CURRENT_8 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 8 + */ +#define WCL_CORE_1_CURRENT_8 (BIT(5)) +#define WCL_CORE_1_CURRENT_8_M (WCL_CORE_1_CURRENT_8_V << WCL_CORE_1_CURRENT_8_S) +#define WCL_CORE_1_CURRENT_8_V 0x00000001U +#define WCL_CORE_1_CURRENT_8_S 5 + +/** WCL_Core_1_STATUSTABLE9_REG register + * Status register of world switch of entry 9 + */ +#define WCL_CORE_1_STATUSTABLE9_REG (DR_REG_WCL_BASE + 0x4a0) +/** WCL_CORE_1_FROM_WORLD_9 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 9 + */ +#define WCL_CORE_1_FROM_WORLD_9 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_9_M (WCL_CORE_1_FROM_WORLD_9_V << WCL_CORE_1_FROM_WORLD_9_S) +#define WCL_CORE_1_FROM_WORLD_9_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_9_S 0 +/** WCL_CORE_1_FROM_ENTRY_9 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 9 + */ +#define WCL_CORE_1_FROM_ENTRY_9 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_9_M (WCL_CORE_1_FROM_ENTRY_9_V << WCL_CORE_1_FROM_ENTRY_9_S) +#define WCL_CORE_1_FROM_ENTRY_9_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_9_S 1 +/** WCL_CORE_1_CURRENT_9 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 9 + */ +#define WCL_CORE_1_CURRENT_9 (BIT(5)) +#define WCL_CORE_1_CURRENT_9_M (WCL_CORE_1_CURRENT_9_V << WCL_CORE_1_CURRENT_9_S) +#define WCL_CORE_1_CURRENT_9_V 0x00000001U +#define WCL_CORE_1_CURRENT_9_S 5 + +/** WCL_Core_1_STATUSTABLE10_REG register + * Status register of world switch of entry 10 + */ +#define WCL_CORE_1_STATUSTABLE10_REG (DR_REG_WCL_BASE + 0x4a4) +/** WCL_CORE_1_FROM_WORLD_10 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 10 + */ +#define WCL_CORE_1_FROM_WORLD_10 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_10_M (WCL_CORE_1_FROM_WORLD_10_V << WCL_CORE_1_FROM_WORLD_10_S) +#define WCL_CORE_1_FROM_WORLD_10_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_10_S 0 +/** WCL_CORE_1_FROM_ENTRY_10 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 10 + */ +#define WCL_CORE_1_FROM_ENTRY_10 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_10_M (WCL_CORE_1_FROM_ENTRY_10_V << WCL_CORE_1_FROM_ENTRY_10_S) +#define WCL_CORE_1_FROM_ENTRY_10_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_10_S 1 +/** WCL_CORE_1_CURRENT_10 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 10 + */ +#define WCL_CORE_1_CURRENT_10 (BIT(5)) +#define WCL_CORE_1_CURRENT_10_M (WCL_CORE_1_CURRENT_10_V << WCL_CORE_1_CURRENT_10_S) +#define WCL_CORE_1_CURRENT_10_V 0x00000001U +#define WCL_CORE_1_CURRENT_10_S 5 + +/** WCL_Core_1_STATUSTABLE11_REG register + * Status register of world switch of entry 11 + */ +#define WCL_CORE_1_STATUSTABLE11_REG (DR_REG_WCL_BASE + 0x4a8) +/** WCL_CORE_1_FROM_WORLD_11 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 11 + */ +#define WCL_CORE_1_FROM_WORLD_11 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_11_M (WCL_CORE_1_FROM_WORLD_11_V << WCL_CORE_1_FROM_WORLD_11_S) +#define WCL_CORE_1_FROM_WORLD_11_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_11_S 0 +/** WCL_CORE_1_FROM_ENTRY_11 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 11 + */ +#define WCL_CORE_1_FROM_ENTRY_11 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_11_M (WCL_CORE_1_FROM_ENTRY_11_V << WCL_CORE_1_FROM_ENTRY_11_S) +#define WCL_CORE_1_FROM_ENTRY_11_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_11_S 1 +/** WCL_CORE_1_CURRENT_11 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 11 + */ +#define WCL_CORE_1_CURRENT_11 (BIT(5)) +#define WCL_CORE_1_CURRENT_11_M (WCL_CORE_1_CURRENT_11_V << WCL_CORE_1_CURRENT_11_S) +#define WCL_CORE_1_CURRENT_11_V 0x00000001U +#define WCL_CORE_1_CURRENT_11_S 5 + +/** WCL_Core_1_STATUSTABLE12_REG register + * Status register of world switch of entry 12 + */ +#define WCL_CORE_1_STATUSTABLE12_REG (DR_REG_WCL_BASE + 0x4ac) +/** WCL_CORE_1_FROM_WORLD_12 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 12 + */ +#define WCL_CORE_1_FROM_WORLD_12 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_12_M (WCL_CORE_1_FROM_WORLD_12_V << WCL_CORE_1_FROM_WORLD_12_S) +#define WCL_CORE_1_FROM_WORLD_12_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_12_S 0 +/** WCL_CORE_1_FROM_ENTRY_12 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 12 + */ +#define WCL_CORE_1_FROM_ENTRY_12 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_12_M (WCL_CORE_1_FROM_ENTRY_12_V << WCL_CORE_1_FROM_ENTRY_12_S) +#define WCL_CORE_1_FROM_ENTRY_12_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_12_S 1 +/** WCL_CORE_1_CURRENT_12 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 12 + */ +#define WCL_CORE_1_CURRENT_12 (BIT(5)) +#define WCL_CORE_1_CURRENT_12_M (WCL_CORE_1_CURRENT_12_V << WCL_CORE_1_CURRENT_12_S) +#define WCL_CORE_1_CURRENT_12_V 0x00000001U +#define WCL_CORE_1_CURRENT_12_S 5 + +/** WCL_Core_1_STATUSTABLE13_REG register + * Status register of world switch of entry 13 + */ +#define WCL_CORE_1_STATUSTABLE13_REG (DR_REG_WCL_BASE + 0x4b0) +/** WCL_CORE_1_FROM_WORLD_13 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 13 + */ +#define WCL_CORE_1_FROM_WORLD_13 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_13_M (WCL_CORE_1_FROM_WORLD_13_V << WCL_CORE_1_FROM_WORLD_13_S) +#define WCL_CORE_1_FROM_WORLD_13_V 0x00000001U +#define WCL_CORE_1_FROM_WORLD_13_S 0 +/** WCL_CORE_1_FROM_ENTRY_13 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 13 + */ +#define WCL_CORE_1_FROM_ENTRY_13 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_13_M (WCL_CORE_1_FROM_ENTRY_13_V << WCL_CORE_1_FROM_ENTRY_13_S) +#define WCL_CORE_1_FROM_ENTRY_13_V 0x0000000FU +#define WCL_CORE_1_FROM_ENTRY_13_S 1 +/** WCL_CORE_1_CURRENT_13 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 13 + */ +#define WCL_CORE_1_CURRENT_13 (BIT(5)) +#define WCL_CORE_1_CURRENT_13_M (WCL_CORE_1_CURRENT_13_V << WCL_CORE_1_CURRENT_13_S) +#define WCL_CORE_1_CURRENT_13_V 0x00000001U +#define WCL_CORE_1_CURRENT_13_S 5 + +/** WCL_Core_1_STATUSTABLE_CURRENT_REG register + * Status register of statustable current + */ +#define WCL_CORE_1_STATUSTABLE_CURRENT_REG (DR_REG_WCL_BASE + 0x4fc) +/** WCL_CORE_1_STATUSTABLE_CURRENT : R/W; bitpos: [13:1]; default: 0; + * This field is used to quickly read and rewrite the current field of all STATUSTABLE + * registers,for example,bit 1 represents the current field of STATUSTABLE1 + */ +#define WCL_CORE_1_STATUSTABLE_CURRENT 0x00001FFFU +#define WCL_CORE_1_STATUSTABLE_CURRENT_M (WCL_CORE_1_STATUSTABLE_CURRENT_V << WCL_CORE_1_STATUSTABLE_CURRENT_S) +#define WCL_CORE_1_STATUSTABLE_CURRENT_V 0x00001FFFU +#define WCL_CORE_1_STATUSTABLE_CURRENT_S 1 + +/** WCL_Core_1_MESSAGE_ADDR_REG register + * Clear writer_buffer write address configuration register + */ +#define WCL_CORE_1_MESSAGE_ADDR_REG (DR_REG_WCL_BASE + 0x500) +/** WCL_CORE_1_MESSAGE_ADDR : R/W; bitpos: [31:0]; default: 0; + * This field is used to set address that need to write when enter WORLD0 + */ +#define WCL_CORE_1_MESSAGE_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_MESSAGE_ADDR_M (WCL_CORE_1_MESSAGE_ADDR_V << WCL_CORE_1_MESSAGE_ADDR_S) +#define WCL_CORE_1_MESSAGE_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_MESSAGE_ADDR_S 0 + +/** WCL_Core_1_MESSAGE_MAX_REG register + * Clear writer_buffer write number configuration register + */ +#define WCL_CORE_1_MESSAGE_MAX_REG (DR_REG_WCL_BASE + 0x504) +/** WCL_CORE_1_MESSAGE_MAX : R/W; bitpos: [3:0]; default: 0; + * This filed is used to set the max value of clear write_buffer + */ +#define WCL_CORE_1_MESSAGE_MAX 0x0000000FU +#define WCL_CORE_1_MESSAGE_MAX_M (WCL_CORE_1_MESSAGE_MAX_V << WCL_CORE_1_MESSAGE_MAX_S) +#define WCL_CORE_1_MESSAGE_MAX_V 0x0000000FU +#define WCL_CORE_1_MESSAGE_MAX_S 0 + +/** WCL_Core_1_MESSAGE_PHASE_REG register + * Clear writer_buffer status register + */ +#define WCL_CORE_1_MESSAGE_PHASE_REG (DR_REG_WCL_BASE + 0x508) +/** WCL_CORE_1_MESSAGE_MATCH : RO; bitpos: [0]; default: 0; + * This bit indicates whether the check is successful + */ +#define WCL_CORE_1_MESSAGE_MATCH (BIT(0)) +#define WCL_CORE_1_MESSAGE_MATCH_M (WCL_CORE_1_MESSAGE_MATCH_V << WCL_CORE_1_MESSAGE_MATCH_S) +#define WCL_CORE_1_MESSAGE_MATCH_V 0x00000001U +#define WCL_CORE_1_MESSAGE_MATCH_S 0 +/** WCL_CORE_1_MESSAGE_EXPECT : RO; bitpos: [4:1]; default: 0; + * This field indicates the data to be written next time + */ +#define WCL_CORE_1_MESSAGE_EXPECT 0x0000000FU +#define WCL_CORE_1_MESSAGE_EXPECT_M (WCL_CORE_1_MESSAGE_EXPECT_V << WCL_CORE_1_MESSAGE_EXPECT_S) +#define WCL_CORE_1_MESSAGE_EXPECT_V 0x0000000FU +#define WCL_CORE_1_MESSAGE_EXPECT_S 1 +/** WCL_CORE_1_MESSAGE_DATAPHASE : RO; bitpos: [5]; default: 0; + * If this bit is 1, it means that is checking clear write_buffer operation, and is + * checking data + */ +#define WCL_CORE_1_MESSAGE_DATAPHASE (BIT(5)) +#define WCL_CORE_1_MESSAGE_DATAPHASE_M (WCL_CORE_1_MESSAGE_DATAPHASE_V << WCL_CORE_1_MESSAGE_DATAPHASE_S) +#define WCL_CORE_1_MESSAGE_DATAPHASE_V 0x00000001U +#define WCL_CORE_1_MESSAGE_DATAPHASE_S 5 +/** WCL_CORE_1_MESSAGE_ADDRESSPHASE : RO; bitpos: [6]; default: 0; + * If this bit is 1, it means that is checking clear write_buffer operation, and is + * checking address. + */ +#define WCL_CORE_1_MESSAGE_ADDRESSPHASE (BIT(6)) +#define WCL_CORE_1_MESSAGE_ADDRESSPHASE_M (WCL_CORE_1_MESSAGE_ADDRESSPHASE_V << WCL_CORE_1_MESSAGE_ADDRESSPHASE_S) +#define WCL_CORE_1_MESSAGE_ADDRESSPHASE_V 0x00000001U +#define WCL_CORE_1_MESSAGE_ADDRESSPHASE_S 6 + +/** WCL_Core_1_World_TRIGGER_ADDR_REG register + * Core_1 trigger address configuration Register + */ +#define WCL_CORE_1_WORLD_TRIGGER_ADDR_REG (DR_REG_WCL_BASE + 0x540) +/** WCL_CORE_1_WORLD_TRIGGER_ADDR : RW; bitpos: [31:0]; default: 0; + * This field is used to configure the entry address from WORLD0 to WORLD1,when the + * CPU executes to this address,switch to WORLD1 + */ +#define WCL_CORE_1_WORLD_TRIGGER_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_WORLD_TRIGGER_ADDR_M (WCL_CORE_1_WORLD_TRIGGER_ADDR_V << WCL_CORE_1_WORLD_TRIGGER_ADDR_S) +#define WCL_CORE_1_WORLD_TRIGGER_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_WORLD_TRIGGER_ADDR_S 0 + +/** WCL_Core_1_World_PREPARE_REG register + * Core_1 prepare world configuration Register + */ +#define WCL_CORE_1_WORLD_PREPARE_REG (DR_REG_WCL_BASE + 0x544) +/** WCL_CORE_1_WORLD_PREPARE : R/W; bitpos: [1:0]; default: 0; + * This field to used to set world to enter,2'b01 means WORLD0, 2'b10 means WORLD1 + */ +#define WCL_CORE_1_WORLD_PREPARE 0x00000003U +#define WCL_CORE_1_WORLD_PREPARE_M (WCL_CORE_1_WORLD_PREPARE_V << WCL_CORE_1_WORLD_PREPARE_S) +#define WCL_CORE_1_WORLD_PREPARE_V 0x00000003U +#define WCL_CORE_1_WORLD_PREPARE_S 0 + +/** WCL_Core_1_World_UPDATE_REG register + * Core_1 configuration update register + */ +#define WCL_CORE_1_WORLD_UPDATE_REG (DR_REG_WCL_BASE + 0x548) +/** WCL_CORE_1_UPDATE : WO; bitpos: [31:0]; default: 0; + * This field is used to update configuration completed, can write any value,the + * hardware only checks the write operation of this register and does not case about + * its value + */ +#define WCL_CORE_1_UPDATE 0xFFFFFFFFU +#define WCL_CORE_1_UPDATE_M (WCL_CORE_1_UPDATE_V << WCL_CORE_1_UPDATE_S) +#define WCL_CORE_1_UPDATE_V 0xFFFFFFFFU +#define WCL_CORE_1_UPDATE_S 0 + +/** WCL_Core_1_World_Cancel_REG register + * Core_1 configuration cancel register + */ +#define WCL_CORE_1_WORLD_CANCEL_REG (DR_REG_WCL_BASE + 0x54c) +/** WCL_CORE_1_WORLD_CANCEL : WO; bitpos: [31:0]; default: 0; + * This field is used to cancel switch world configuration,if the trigger address and + * update configuration complete,can use this register to cancel world switch. can + * write any value, the hardware only checks the write operation of this register and + * does not case about its value + */ +#define WCL_CORE_1_WORLD_CANCEL 0xFFFFFFFFU +#define WCL_CORE_1_WORLD_CANCEL_M (WCL_CORE_1_WORLD_CANCEL_V << WCL_CORE_1_WORLD_CANCEL_S) +#define WCL_CORE_1_WORLD_CANCEL_V 0xFFFFFFFFU +#define WCL_CORE_1_WORLD_CANCEL_S 0 + +/** WCL_Core_1_World_IRam0_REG register + * Core_1 Iram0 world register + */ +#define WCL_CORE_1_WORLD_IRAM0_REG (DR_REG_WCL_BASE + 0x550) +/** WCL_CORE_1_WORLD_IRAM0 : R/W; bitpos: [1:0]; default: 0; + * this field is used to read current world of Iram0 bus + */ +#define WCL_CORE_1_WORLD_IRAM0 0x00000003U +#define WCL_CORE_1_WORLD_IRAM0_M (WCL_CORE_1_WORLD_IRAM0_V << WCL_CORE_1_WORLD_IRAM0_S) +#define WCL_CORE_1_WORLD_IRAM0_V 0x00000003U +#define WCL_CORE_1_WORLD_IRAM0_S 0 + +/** WCL_Core_1_World_DRam0_PIF_REG register + * Core_1 dram0 and PIF world register + */ +#define WCL_CORE_1_WORLD_DRAM0_PIF_REG (DR_REG_WCL_BASE + 0x554) +/** WCL_CORE_1_WORLD_DRAM0_PIF : R/W; bitpos: [1:0]; default: 0; + * this field is used to read current world of Dram0 bus and PIF bus + */ +#define WCL_CORE_1_WORLD_DRAM0_PIF 0x00000003U +#define WCL_CORE_1_WORLD_DRAM0_PIF_M (WCL_CORE_1_WORLD_DRAM0_PIF_V << WCL_CORE_1_WORLD_DRAM0_PIF_S) +#define WCL_CORE_1_WORLD_DRAM0_PIF_V 0x00000003U +#define WCL_CORE_1_WORLD_DRAM0_PIF_S 0 + +/** WCL_Core_1_World_Phase_REG register + * Core_0 world status register + */ +#define WCL_CORE_1_WORLD_PHASE_REG (DR_REG_WCL_BASE + 0x558) +/** WCL_CORE_1_WORLD_PHASE : RO; bitpos: [0]; default: 0; + * This bit indicates whether is preparing to switch to WORLD1,1 means value. + */ +#define WCL_CORE_1_WORLD_PHASE (BIT(0)) +#define WCL_CORE_1_WORLD_PHASE_M (WCL_CORE_1_WORLD_PHASE_V << WCL_CORE_1_WORLD_PHASE_S) +#define WCL_CORE_1_WORLD_PHASE_V 0x00000001U +#define WCL_CORE_1_WORLD_PHASE_S 0 + +/** WCL_Core_1_NMI_MASK_ENABLE_REG register + * Core_1 NMI mask enable register + */ +#define WCL_CORE_1_NMI_MASK_ENABLE_REG (DR_REG_WCL_BASE + 0x580) +/** WCL_CORE_1_NMI_MASK_ENABLE : WO; bitpos: [31:0]; default: 0; + * this field is used to set NMI mask, it can write any value, when write this + * register,the hardware start masking NMI interrupt + */ +#define WCL_CORE_1_NMI_MASK_ENABLE 0xFFFFFFFFU +#define WCL_CORE_1_NMI_MASK_ENABLE_M (WCL_CORE_1_NMI_MASK_ENABLE_V << WCL_CORE_1_NMI_MASK_ENABLE_S) +#define WCL_CORE_1_NMI_MASK_ENABLE_V 0xFFFFFFFFU +#define WCL_CORE_1_NMI_MASK_ENABLE_S 0 + +/** WCL_Core_1_NMI_MASK_TRIGGER_ADDR_REG register + * Core_1 NMI mask trigger addr register + */ +#define WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_REG (DR_REG_WCL_BASE + 0x584) +/** WCL_CORE_1_NMI_MASK_TRIGGER_ADDR : R/W; bitpos: [31:0]; default: 0; + * this field to used to set trigger address + */ +#define WCL_CORE_1_NMI_MASK_TRIGGER_ADDR 0xFFFFFFFFU +#define WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_M (WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_V << WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_S) +#define WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_V 0xFFFFFFFFU +#define WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_S 0 + +/** WCL_Core_1_NMI_MASK_DISABLE_REG register + * Core_1 NMI mask disable register + */ +#define WCL_CORE_1_NMI_MASK_DISABLE_REG (DR_REG_WCL_BASE + 0x588) +/** WCL_CORE_1_NMI_MASK_DISABLE : WO; bitpos: [31:0]; default: 0; + * this field is used to disable NMI mask, it will not take effect immediately,only + * when the CPU executes to the trigger address will it start to cancel NMI mask + */ +#define WCL_CORE_1_NMI_MASK_DISABLE 0xFFFFFFFFU +#define WCL_CORE_1_NMI_MASK_DISABLE_M (WCL_CORE_1_NMI_MASK_DISABLE_V << WCL_CORE_1_NMI_MASK_DISABLE_S) +#define WCL_CORE_1_NMI_MASK_DISABLE_V 0xFFFFFFFFU +#define WCL_CORE_1_NMI_MASK_DISABLE_S 0 + +/** WCL_Core_1_NMI_MASK_CANCLE_REG register + * Core_1 NMI mask disable register + */ +#define WCL_CORE_1_NMI_MASK_CANCLE_REG (DR_REG_WCL_BASE + 0x58c) +/** WCL_CORE_1_NMI_MASK_CANCEL : WO; bitpos: [31:0]; default: 0; + * this field is used to cancel NMI mask disable function. + */ +#define WCL_CORE_1_NMI_MASK_CANCEL 0xFFFFFFFFU +#define WCL_CORE_1_NMI_MASK_CANCEL_M (WCL_CORE_1_NMI_MASK_CANCEL_V << WCL_CORE_1_NMI_MASK_CANCEL_S) +#define WCL_CORE_1_NMI_MASK_CANCEL_V 0xFFFFFFFFU +#define WCL_CORE_1_NMI_MASK_CANCEL_S 0 + +/** WCL_Core_1_NMI_MASK_REG register + * Core_1 NMI mask register + */ +#define WCL_CORE_1_NMI_MASK_REG (DR_REG_WCL_BASE + 0x590) +/** WCL_CORE_1_NMI_MASK : R/W; bitpos: [0]; default: 0; + * this bit is used to mask NMI interrupt,it can directly mask NMI interrupt + */ +#define WCL_CORE_1_NMI_MASK (BIT(0)) +#define WCL_CORE_1_NMI_MASK_M (WCL_CORE_1_NMI_MASK_V << WCL_CORE_1_NMI_MASK_S) +#define WCL_CORE_1_NMI_MASK_V 0x00000001U +#define WCL_CORE_1_NMI_MASK_S 0 + +/** WCL_Core_1_NMI_MASK_PHASE_REG register + * Core_1 NMI mask phase register + */ +#define WCL_CORE_1_NMI_MASK_PHASE_REG (DR_REG_WCL_BASE + 0x594) +/** WCL_CORE_1_NMI_MASK_PHASE : RO; bitpos: [0]; default: 0; + * this bit is used to indicates whether the NMI interrupt is being masked, 1 means + * NMI interrupt is being masked + */ +#define WCL_CORE_1_NMI_MASK_PHASE (BIT(0)) +#define WCL_CORE_1_NMI_MASK_PHASE_M (WCL_CORE_1_NMI_MASK_PHASE_V << WCL_CORE_1_NMI_MASK_PHASE_S) +#define WCL_CORE_1_NMI_MASK_PHASE_V 0x00000001U +#define WCL_CORE_1_NMI_MASK_PHASE_S 0 #ifdef __cplusplus } #endif - - - -#endif /*_SOC_WORLD_CONTROLLER_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/world_controller_struct.h b/components/soc/esp32s3/include/soc/world_controller_struct.h index 0791caf4b8..80f6661b35 100644 --- a/components/soc/esp32s3/include/soc/world_controller_struct.h +++ b/components/soc/esp32s3/include/soc/world_controller_struct.h @@ -1,7 +1,7 @@ -/* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -10,773 +10,1572 @@ extern "C" { #endif -typedef volatile struct world_controller_dev_s { - uint32_t wcl_core_0_entry_1_addr; - uint32_t wcl_core_0_entry_2_addr; - uint32_t wcl_core_0_entry_3_addr; - uint32_t wcl_core_0_entry_4_addr; - uint32_t wcl_core_0_entry_5_addr; - uint32_t wcl_core_0_entry_6_addr; - uint32_t wcl_core_0_entry_7_addr; - uint32_t wcl_core_0_entry_8_addr; - uint32_t wcl_core_0_entry_9_addr; - uint32_t wcl_core_0_entry_10_addr; - uint32_t wcl_core_0_entry_11_addr; - uint32_t wcl_core_0_entry_12_addr; - uint32_t wcl_core_0_entry_13_addr; - uint32_t reserved_34; - uint32_t reserved_38; - uint32_t reserved_3c; - uint32_t reserved_40; - uint32_t reserved_44; - uint32_t reserved_48; - uint32_t reserved_4c; - uint32_t reserved_50; - uint32_t reserved_54; - uint32_t reserved_58; - uint32_t reserved_5c; - uint32_t reserved_60; - uint32_t reserved_64; - uint32_t reserved_68; - uint32_t reserved_6c; - uint32_t reserved_70; - uint32_t reserved_74; - uint32_t reserved_78; - union { - struct { - uint32_t reserved0 : 1; - uint32_t reg_core_0_entry_check : 13; /*This filed is used to enable entry address check */ - uint32_t reserved14 : 18; /*reserved*/ - }; - uint32_t val; - } wcl_core_0_entry_check; - uint32_t reserved_80; - uint32_t reserved_84; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - uint32_t reserved_fc; - uint32_t wcl_core_0_message_addr; - union { - struct { - uint32_t reg_core_0_message_max : 4; /*This filed is used to set the max value of clear write_buffer*/ - uint32_t reserved4 : 28; - }; - uint32_t val; - } wcl_core_0_message_max; - union { - struct { - uint32_t reg_core_0_from_world_1 : 1; /*This bit is used to confirm world before enter entry 1 */ - uint32_t reg_core_0_from_entry_1 : 4; /*This filed is used to confirm in which entry before enter entry 1*/ - uint32_t reg_core_0_current_1 : 1; /*This bit is used to confirm whether the current state is in entry 1 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable1; - union { - struct { - uint32_t reg_core_0_from_world_2 : 1; /*This bit is used to confirm world before enter entry 2 */ - uint32_t reg_core_0_from_entry_2 : 4; /*This filed is used to confirm in which entry before enter entry 2*/ - uint32_t reg_core_0_current_2 : 1; /*This bit is used to confirm whether the current state is in entry 2 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable2; - union { - struct { - uint32_t reg_core_0_from_world_3 : 1; /*This bit is used to confirm world before enter entry 3 */ - uint32_t reg_core_0_from_entry_3 : 4; /*This filed is used to confirm in which entry before enter entry 3*/ - uint32_t reg_core_0_current_3 : 1; /*This bit is used to confirm whether the current state is in entry 3 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable3; - union { - struct { - uint32_t reg_core_0_from_world_4 : 1; /*This bit is used to confirm world before enter entry 4 */ - uint32_t reg_core_0_from_entry_4 : 4; /*This filed is used to confirm in which entry before enter entry 4*/ - uint32_t reg_core_0_current_4 : 1; /*This bit is used to confirm whether the current state is in entry 4 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable4; - union { - struct { - uint32_t reg_core_0_from_world_5 : 1; /*This bit is used to confirm world before enter entry 5 */ - uint32_t reg_core_0_from_entry_5 : 4; /*This filed is used to confirm in which entry before enter entry 5*/ - uint32_t reg_core_0_current_5 : 1; /*This bit is used to confirm whether the current state is in entry 5 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable5; - union { - struct { - uint32_t reg_core_0_from_world_6 : 1; /*This bit is used to confirm world before enter entry 6 */ - uint32_t reg_core_0_from_entry_6 : 4; /*This filed is used to confirm in which entry before enter entry 6*/ - uint32_t reg_core_0_current_6 : 1; /*This bit is used to confirm whether the current state is in entry 6 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable6; - union { - struct { - uint32_t reg_core_0_from_world_7 : 1; /*This bit is used to confirm world before enter entry 7 */ - uint32_t reg_core_0_from_entry_7 : 4; /*This filed is used to confirm in which entry before enter entry 7*/ - uint32_t reg_core_0_current_7 : 1; /*This bit is used to confirm whether the current state is in entry 7 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable7; - union { - struct { - uint32_t reg_core_0_from_world_8 : 1; /*This bit is used to confirm world before enter entry 8 */ - uint32_t reg_core_0_from_entry_8 : 4; /*This filed is used to confirm in which entry before enter entry 8*/ - uint32_t reg_core_0_current_8 : 1; /*This bit is used to confirm whether the current state is in entry 8 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable8; - union { - struct { - uint32_t reg_core_0_from_world_9 : 1; /*This bit is used to confirm world before enter entry 9 */ - uint32_t reg_core_0_from_entry_9 : 4; /*This filed is used to confirm in which entry before enter entry 9*/ - uint32_t reg_core_0_current_9 : 1; /*This bit is used to confirm whether the current state is in entry 9 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable9; - union { - struct { - uint32_t reg_core_0_from_world_10 : 1; /*This bit is used to confirm world before enter entry 10 */ - uint32_t reg_core_0_from_entry_10 : 4; /*This filed is used to confirm in which entry before enter entry 10*/ - uint32_t reg_core_0_current_10 : 1; /*This bit is used to confirm whether the current state is in entry 10 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable10; - union { - struct { - uint32_t reg_core_0_from_world_11 : 1; /*This bit is used to confirm world before enter entry 11 */ - uint32_t reg_core_0_from_entry_11 : 4; /*This filed is used to confirm in which entry before enter entry 11*/ - uint32_t reg_core_0_current_11 : 1; /*This bit is used to confirm whether the current state is in entry 11 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable11; - union { - struct { - uint32_t core_0_from_world_12 : 1; /*This bit is used to confirm world before enter entry 12 */ - uint32_t core_0_from_entry_12 : 4; /*This filed is used to confirm in which entry before enter entry 12*/ - uint32_t core_0_current_12 : 1; /*This bit is used to confirm whether the current state is in entry 12 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable12; - union { - struct { - uint32_t reg_core_0_from_world_13 : 1; /*This bit is used to confirm world before enter entry 13 */ - uint32_t reg_core_0_from_entry_13 : 4; /*This filed is used to confirm in which entry before enter entry 13*/ - uint32_t reg_core_0_current_13 : 1; /*This bit is used to confirm whether the current state is in entry 13 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_0_statustable13; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - union { - struct { - uint32_t reserved0 : 1; - uint32_t reg_core_0_statustable_current: 13; /*This field is used to quickly read and rewrite the current field of all STATUSTABLE registers.For example*/ - uint32_t reserved14 : 18; - }; - uint32_t val; - } wcl_core_0_statustable_current; - uint32_t reserved_100; - uint32_t reserved_104; - union { - struct { - uint32_t reg_core_0_message_match : 1; /*This bit indicates whether the check is successful*/ - uint32_t reg_core_0_message_expect : 4; /*This field indicates the data to be written next time*/ - uint32_t reg_core_0_message_dataphase : 1; /*If this bit is 1*/ - uint32_t reg_core_0_message_addressphase: 1; /*If this bit is 1*/ - uint32_t reserved7 : 25; - }; - uint32_t val; - } wcl_core_0_message_phase; - uint32_t reserved_10c; - uint32_t reserved_110; - uint32_t reserved_114; - uint32_t reserved_118; - uint32_t reserved_11c; - uint32_t reserved_120; - uint32_t reserved_124; - uint32_t reserved_128; - uint32_t reserved_12c; - uint32_t reserved_130; - uint32_t reserved_134; - uint32_t reserved_138; - uint32_t reserved_13c; - uint32_t wcl_core_0_world_trigger_addr; - union { - struct { - uint32_t reg_core_0_world_prepare : 2; /*This field to used to set world to enter*/ - uint32_t reserved2 : 30; - }; - uint32_t val; - } wcl_core_0_world_prepare; - uint32_t wcl_core_0_world_update; - uint32_t wcl_core_0_world_cancel; - union { - struct { - uint32_t reg_core_0_world_iram0 : 2; /*this field is used to read current world of Iram0 bus*/ - uint32_t reserved2 : 30; - }; - uint32_t val; - } wcl_core_0_world_iram0; - union { - struct { - uint32_t reg_core_0_world_dram0_pif : 2; /*this field is used to read current world of Dram0 bus and PIF bus*/ - uint32_t reserved2 : 30; - }; - uint32_t val; - } wcl_core_0_world_dram0_pif; - union { - struct { - uint32_t reg_core_0_world_phase : 1; /*This bit indicates whether is preparing to switch to WORLD1*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } wcl_core_0_world_phase; - uint32_t reserved_15c; - uint32_t reserved_160; - uint32_t reserved_164; - uint32_t reserved_168; - uint32_t reserved_16c; - uint32_t reserved_170; - uint32_t reserved_174; - uint32_t reserved_178; - uint32_t reserved_17c; - uint32_t wcl_core_0_nmi_mask_enable; - uint32_t wcl_core_0_nmi_mask_trigger_addr; - uint32_t wcl_core_0_nmi_mask_disable; - uint32_t wcl_core_0_nmi_mask_cancle; - union { - struct { - uint32_t reg_core_0_nmi_mask : 1; /*this bit is used to mask NMI interrupt*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } wcl_core_0_nmi_mask; - union { - struct { - uint32_t reg_core_0_nmi_mask_phase : 1; /*this bit is used to indicates whether the NMI interrupt is being masked*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } wcl_core_0_nmi_mask_phase; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - uint32_t reserved_1c0; - uint32_t reserved_1c4; - uint32_t reserved_1c8; - uint32_t reserved_1cc; - uint32_t reserved_1d0; - uint32_t reserved_1d4; - uint32_t reserved_1d8; - uint32_t reserved_1dc; - uint32_t reserved_1e0; - uint32_t reserved_1e4; - uint32_t reserved_1e8; - uint32_t reserved_1ec; - uint32_t reserved_1f0; - uint32_t reserved_1f4; - uint32_t reserved_1f8; - uint32_t reserved_1fc; - uint32_t reserved_200; - uint32_t reserved_204; - uint32_t reserved_208; - uint32_t reserved_20c; - uint32_t reserved_210; - uint32_t reserved_214; - uint32_t reserved_218; - uint32_t reserved_21c; - uint32_t reserved_220; - uint32_t reserved_224; - uint32_t reserved_228; - uint32_t reserved_22c; - uint32_t reserved_230; - uint32_t reserved_234; - uint32_t reserved_238; - uint32_t reserved_23c; - uint32_t reserved_240; - uint32_t reserved_244; - uint32_t reserved_248; - uint32_t reserved_24c; - uint32_t reserved_250; - uint32_t reserved_254; - uint32_t reserved_258; - uint32_t reserved_25c; - uint32_t reserved_260; - uint32_t reserved_264; - uint32_t reserved_268; - uint32_t reserved_26c; - uint32_t reserved_270; - uint32_t reserved_274; - uint32_t reserved_278; - uint32_t reserved_27c; - uint32_t reserved_280; - uint32_t reserved_284; - uint32_t reserved_288; - uint32_t reserved_28c; - uint32_t reserved_290; - uint32_t reserved_294; - uint32_t reserved_298; - uint32_t reserved_29c; - uint32_t reserved_2a0; - uint32_t reserved_2a4; - uint32_t reserved_2a8; - uint32_t reserved_2ac; - uint32_t reserved_2b0; - uint32_t reserved_2b4; - uint32_t reserved_2b8; - uint32_t reserved_2bc; - uint32_t reserved_2c0; - uint32_t reserved_2c4; - uint32_t reserved_2c8; - uint32_t reserved_2cc; - uint32_t reserved_2d0; - uint32_t reserved_2d4; - uint32_t reserved_2d8; - uint32_t reserved_2dc; - uint32_t reserved_2e0; - uint32_t reserved_2e4; - uint32_t reserved_2e8; - uint32_t reserved_2ec; - uint32_t reserved_2f0; - uint32_t reserved_2f4; - uint32_t reserved_2f8; - uint32_t reserved_2fc; - uint32_t reserved_300; - uint32_t reserved_304; - uint32_t reserved_308; - uint32_t reserved_30c; - uint32_t reserved_310; - uint32_t reserved_314; - uint32_t reserved_318; - uint32_t reserved_31c; - uint32_t reserved_320; - uint32_t reserved_324; - uint32_t reserved_328; - uint32_t reserved_32c; - uint32_t reserved_330; - uint32_t reserved_334; - uint32_t reserved_338; - uint32_t reserved_33c; - uint32_t reserved_340; - uint32_t reserved_344; - uint32_t reserved_348; - uint32_t reserved_34c; - uint32_t reserved_350; - uint32_t reserved_354; - uint32_t reserved_358; - uint32_t reserved_35c; - uint32_t reserved_360; - uint32_t reserved_364; - uint32_t reserved_368; - uint32_t reserved_36c; - uint32_t reserved_370; - uint32_t reserved_374; - uint32_t reserved_378; - uint32_t reserved_37c; - uint32_t reserved_380; - uint32_t reserved_384; - uint32_t reserved_388; - uint32_t reserved_38c; - uint32_t reserved_390; - uint32_t reserved_394; - uint32_t reserved_398; - uint32_t reserved_39c; - uint32_t reserved_3a0; - uint32_t reserved_3a4; - uint32_t reserved_3a8; - uint32_t reserved_3ac; - uint32_t reserved_3b0; - uint32_t reserved_3b4; - uint32_t reserved_3b8; - uint32_t reserved_3bc; - uint32_t reserved_3c0; - uint32_t reserved_3c4; - uint32_t reserved_3c8; - uint32_t reserved_3cc; - uint32_t reserved_3d0; - uint32_t reserved_3d4; - uint32_t reserved_3d8; - uint32_t reserved_3dc; - uint32_t reserved_3e0; - uint32_t reserved_3e4; - uint32_t reserved_3e8; - uint32_t reserved_3ec; - uint32_t reserved_3f0; - uint32_t reserved_3f4; - uint32_t reserved_3f8; - uint32_t reserved_3fc; - uint32_t wcl_core_1_entry_1_addr; - uint32_t wcl_core_1_entry_2_addr; - uint32_t wcl_core_1_entry_3_addr; - uint32_t wcl_core_1_entry_4_addr; - uint32_t wcl_core_1_entry_5_addr; - uint32_t wcl_core_1_entry_6_addr; - uint32_t wcl_core_1_entry_7_addr; - uint32_t wcl_core_1_entry_8_addr; - uint32_t wcl_core_1_entry_9_addr; - uint32_t wcl_core_1_entry_10_addr; - uint32_t wcl_core_1_entry_11_addr; - uint32_t wcl_core_1_entry_12_addr; - uint32_t wcl_core_1_entry_13_addr; - uint32_t reserved_434; - uint32_t reserved_438; - uint32_t reserved_43c; - uint32_t reserved_440; - uint32_t reserved_444; - uint32_t reserved_448; - uint32_t reserved_44c; - uint32_t reserved_450; - uint32_t reserved_454; - uint32_t reserved_458; - uint32_t reserved_45c; - uint32_t reserved_460; - uint32_t reserved_464; - uint32_t reserved_468; - uint32_t reserved_46c; - uint32_t reserved_470; - uint32_t reserved_474; - uint32_t reserved_478; - union { - struct { - uint32_t reserved0 : 1; - uint32_t reg_core_1_entry_check : 13; /*This filed is used to enable entry address check */ - uint32_t reserved14 : 18; /*reserved*/ - }; - uint32_t val; - } wcl_core_1_entry_check; - uint32_t reserved_480; - uint32_t reserved_484; - uint32_t reserved_488; - uint32_t reserved_48c; - uint32_t reserved_490; - uint32_t reserved_494; - uint32_t reserved_498; - uint32_t reserved_49c; - uint32_t reserved_4a0; - uint32_t reserved_4a4; - uint32_t reserved_4a8; - uint32_t reserved_4ac; - uint32_t reserved_4b0; - uint32_t reserved_4b4; - uint32_t reserved_4b8; - uint32_t reserved_4bc; - uint32_t reserved_4c0; - uint32_t reserved_4c4; - uint32_t reserved_4c8; - uint32_t reserved_4cc; - uint32_t reserved_4d0; - uint32_t reserved_4d4; - uint32_t reserved_4d8; - uint32_t reserved_4dc; - uint32_t reserved_4e0; - uint32_t reserved_4e4; - uint32_t reserved_4e8; - uint32_t reserved_4ec; - uint32_t reserved_4f0; - uint32_t reserved_4f4; - uint32_t reserved_4f8; - uint32_t reserved_4fc; - uint32_t wcl_core_1_message_addr; - union { - struct { - uint32_t reg_core_1_message_max : 4; /*This filed is used to set the max value of clear write_buffer*/ - uint32_t reserved4 : 28; - }; - uint32_t val; - } wcl_core_1_message_max; - union { - struct { - uint32_t reg_core_1_from_world_1 : 1; /*This bit is used to confirm world before enter entry 1 */ - uint32_t reg_core_1_from_entry_1 : 4; /*This filed is used to confirm in which entry before enter entry 1*/ - uint32_t reg_core_1_current_1 : 1; /*This bit is used to confirm whether the current state is in entry 1 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable1; - union { - struct { - uint32_t reg_core_1_from_world_2 : 1; /*This bit is used to confirm world before enter entry 2 */ - uint32_t reg_core_1_from_entry_2 : 4; /*This filed is used to confirm in which entry before enter entry 2*/ - uint32_t reg_core_1_current_2 : 1; /*This bit is used to confirm whether the current state is in entry 2 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable2; - union { - struct { - uint32_t reg_core_1_from_world_3 : 1; /*This bit is used to confirm world before enter entry 3 */ - uint32_t reg_core_1_from_entry_3 : 4; /*This filed is used to confirm in which entry before enter entry 3*/ - uint32_t reg_core_1_current_3 : 1; /*This bit is used to confirm whether the current state is in entry 3 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable3; - union { - struct { - uint32_t reg_core_1_from_world_4 : 1; /*This bit is used to confirm world before enter entry 4 */ - uint32_t reg_core_1_from_entry_4 : 4; /*This filed is used to confirm in which entry before enter entry 4*/ - uint32_t reg_core_1_current_4 : 1; /*This bit is used to confirm whether the current state is in entry 4 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable4; - union { - struct { - uint32_t reg_core_1_from_world_5 : 1; /*This bit is used to confirm world before enter entry 5 */ - uint32_t reg_core_1_from_entry_5 : 4; /*This filed is used to confirm in which entry before enter entry 5*/ - uint32_t reg_core_1_current_5 : 1; /*This bit is used to confirm whether the current state is in entry 5 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable5; - union { - struct { - uint32_t reg_core_1_from_world_6 : 1; /*This bit is used to confirm world before enter entry 6 */ - uint32_t reg_core_1_from_entry_6 : 4; /*This filed is used to confirm in which entry before enter entry 6*/ - uint32_t reg_core_1_current_6 : 1; /*This bit is used to confirm whether the current state is in entry 6 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable6; - union { - struct { - uint32_t reg_core_1_from_world_7 : 1; /*This bit is used to confirm world before enter entry 7 */ - uint32_t reg_core_1_from_entry_7 : 4; /*This filed is used to confirm in which entry before enter entry 7*/ - uint32_t reg_core_1_current_7 : 1; /*This bit is used to confirm whether the current state is in entry 7 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable7; - union { - struct { - uint32_t reg_core_1_from_world_8 : 1; /*This bit is used to confirm world before enter entry 8 */ - uint32_t reg_core_1_from_entry_8 : 4; /*This filed is used to confirm in which entry before enter entry 8*/ - uint32_t reg_core_1_current_8 : 1; /*This bit is used to confirm whether the current state is in entry 8 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable8; - union { - struct { - uint32_t reg_core_1_from_world_9 : 1; /*This bit is used to confirm world before enter entry 9 */ - uint32_t reg_core_1_from_entry_9 : 4; /*This filed is used to confirm in which entry before enter entry 9*/ - uint32_t reg_core_1_current_9 : 1; /*This bit is used to confirm whether the current state is in entry 9 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable9; - union { - struct { - uint32_t reg_core_1_from_world_10 : 1; /*This bit is used to confirm world before enter entry 10 */ - uint32_t reg_core_1_from_entry_10 : 4; /*This filed is used to confirm in which entry before enter entry 10*/ - uint32_t reg_core_1_current_10 : 1; /*This bit is used to confirm whether the current state is in entry 10 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable10; - union { - struct { - uint32_t reg_core_1_from_world_11 : 1; /*This bit is used to confirm world before enter entry 11 */ - uint32_t reg_core_1_from_entry_11 : 4; /*This filed is used to confirm in which entry before enter entry 11*/ - uint32_t reg_core_1_current_11 : 1; /*This bit is used to confirm whether the current state is in entry 11 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable11; - union { - struct { - uint32_t core_1_from_world_12 : 1; /*This bit is used to confirm world before enter entry 12 */ - uint32_t core_1_from_entry_12 : 4; /*This filed is used to confirm in which entry before enter entry 12*/ - uint32_t core_1_current_12 : 1; /*This bit is used to confirm whether the current state is in entry 12 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable12; - union { - struct { - uint32_t reg_core_1_from_world_13 : 1; /*This bit is used to confirm world before enter entry 13 */ - uint32_t reg_core_1_from_entry_13 : 4; /*This filed is used to confirm in which entry before enter entry 13*/ - uint32_t reg_core_1_current_13 : 1; /*This bit is used to confirm whether the current state is in entry 13 */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } wcl_core_1_statustable13; - uint32_t reserved_4b4; - uint32_t reserved_4b8; - uint32_t reserved_4bc; - uint32_t reserved_4c0; - uint32_t reserved_4c4; - uint32_t reserved_4c8; - uint32_t reserved_4cc; - uint32_t reserved_4d0; - uint32_t reserved_4d4; - uint32_t reserved_4d8; - uint32_t reserved_4dc; - uint32_t reserved_4e0; - uint32_t reserved_4e4; - uint32_t reserved_4e8; - uint32_t reserved_4ec; - uint32_t reserved_4f0; - uint32_t reserved_4f4; - uint32_t reserved_4f8; - union { - struct { - uint32_t reserved0 : 1; - uint32_t reg_core_1_statustable_current: 13; /*This field is used to quickly read and rewrite the current field of all STATUSTABLE registers.For example*/ - uint32_t reserved14 : 18; - }; - uint32_t val; - } wcl_core_1_statustable_current; - uint32_t reserved_500; - uint32_t reserved_504; - union { - struct { - uint32_t reg_core_1_message_match : 1; /*This bit indicates whether the check is successful*/ - uint32_t reg_core_1_message_expect : 4; /*This field indicates the data to be written next time*/ - uint32_t reg_core_1_message_dataphase : 1; /*If this bit is 1*/ - uint32_t reg_core_1_message_addressphase: 1; /*If this bit is 1*/ - uint32_t reserved7 : 25; - }; - uint32_t val; - } wcl_core_1_message_phase; - uint32_t reserved_50c; - uint32_t reserved_510; - uint32_t reserved_514; - uint32_t reserved_518; - uint32_t reserved_51c; - uint32_t reserved_520; - uint32_t reserved_524; - uint32_t reserved_528; - uint32_t reserved_52c; - uint32_t reserved_530; - uint32_t reserved_534; - uint32_t reserved_538; - uint32_t reserved_53c; - uint32_t wcl_core_1_world_trigger_addr; - union { - struct { - uint32_t reg_core_1_world_prepare : 2; /*This field to used to set world to enter*/ - uint32_t reserved2 : 30; - }; - uint32_t val; - } wcl_core_1_world_prepare; - uint32_t wcl_core_1_world_update; - uint32_t wcl_core_1_world_cancel; - union { - struct { - uint32_t reg_core_1_world_iram0 : 2; /*this field is used to read current world of Iram0 bus*/ - uint32_t reserved2 : 30; - }; - uint32_t val; - } wcl_core_1_world_iram0; - union { - struct { - uint32_t reg_core_1_world_dram0_pif : 2; /*this field is used to read current world of Dram0 bus and PIF bus*/ - uint32_t reserved2 : 30; - }; - uint32_t val; - } wcl_core_1_world_dram0_pif; - union { - struct { - uint32_t reg_core_1_world_phase : 1; /*This bit indicates whether is preparing to switch to WORLD1*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } wcl_core_1_world_phase; - uint32_t reserved_55c; - uint32_t reserved_560; - uint32_t reserved_564; - uint32_t reserved_568; - uint32_t reserved_56c; - uint32_t reserved_570; - uint32_t reserved_574; - uint32_t reserved_578; - uint32_t reserved_57c; - uint32_t wcl_core_1_nmi_mask_enable; - uint32_t wcl_core_1_nmi_mask_trigger_addr; - uint32_t wcl_core_1_nmi_mask_disable; - uint32_t wcl_core_1_nmi_mask_cancle; - union { - struct { - uint32_t reg_core_1_nmi_mask : 1; /*this bit is used to mask NMI interrupt*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } wcl_core_1_nmi_mask; - union { - struct { - uint32_t reg_core_1_nmi_mask_phase : 1; /*this bit is used to indicates whether the NMI interrupt is being masked*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } wcl_core_1_nmi_mask_phase; -} world_controller_dev_t; -extern world_controller_dev_t WORLD_CONTROLLER; +/** Group: WORLD1 to WORLD0 configuration Registers */ +/** Type of core_0_entry_1_addr register + * Core_0 Entry 1 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_1_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 1 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_1_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_1_addr_reg_t; + +/** Type of core_0_entry_2_addr register + * Core_0 Entry 2 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_2_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 2 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_2_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_2_addr_reg_t; + +/** Type of core_0_entry_3_addr register + * Core_0 Entry 3 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_3_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 3 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_3_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_3_addr_reg_t; + +/** Type of core_0_entry_4_addr register + * Core_0 Entry 4 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_4_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 4 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_4_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_4_addr_reg_t; + +/** Type of core_0_entry_5_addr register + * Core_0 Entry 5 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_5_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 5 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_5_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_5_addr_reg_t; + +/** Type of core_0_entry_6_addr register + * Core_0 Entry 6 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_6_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 6 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_6_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_6_addr_reg_t; + +/** Type of core_0_entry_7_addr register + * Core_0 Entry 7 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_7_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 7 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_7_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_7_addr_reg_t; + +/** Type of core_0_entry_8_addr register + * Core_0 Entry 8 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_8_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 8 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_8_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_8_addr_reg_t; + +/** Type of core_0_entry_9_addr register + * Core_0 Entry 9 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_9_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 9 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_9_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_9_addr_reg_t; + +/** Type of core_0_entry_10_addr register + * Core_0 Entry 10 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_10_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 10 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_10_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_10_addr_reg_t; + +/** Type of core_0_entry_11_addr register + * Core_0 Entry 11 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_11_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 11 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_11_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_11_addr_reg_t; + +/** Type of core_0_entry_12_addr register + * Core_0 Entry 12 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_12_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 12 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_12_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_12_addr_reg_t; + +/** Type of core_0_entry_13_addr register + * Core_0 Entry 13 address configuration Register + */ +typedef union { + struct { + /** core_0_entry_13_addr : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 13 address from WORLD1 to WORLD0 + */ + uint32_t core_0_entry_13_addr:32; + }; + uint32_t val; +} wcl_core_0_entry_13_addr_reg_t; + +/** Type of core_0_entry_check register + * Core_0 Entry check configuration Register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** core_0_entry_check : R/W; bitpos: [13:1]; default: 1; + * This filed is used to enable entry address check + */ + uint32_t core_0_entry_check:13; + uint32_t reserved_14:18; + }; + uint32_t val; +} wcl_core_0_entry_check_reg_t; + +/** Type of core_0_message_addr register + * Clear writer_buffer write address configuration register + */ +typedef union { + struct { + /** core_0_message_addr : R/W; bitpos: [31:0]; default: 0; + * This field is used to set address that need to write when enter WORLD0 + */ + uint32_t core_0_message_addr:32; + }; + uint32_t val; +} wcl_core_0_message_addr_reg_t; + +/** Type of core_0_message_max register + * Clear writer_buffer write number configuration register + */ +typedef union { + struct { + /** core_0_message_max : R/W; bitpos: [3:0]; default: 0; + * This filed is used to set the max value of clear write_buffer + */ + uint32_t core_0_message_max:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} wcl_core_0_message_max_reg_t; + +/** Type of core_0_message_phase register + * Clear writer_buffer status register + */ +typedef union { + struct { + /** core_0_message_match : RO; bitpos: [0]; default: 0; + * This bit indicates whether the check is successful + */ + uint32_t core_0_message_match:1; + /** core_0_message_expect : RO; bitpos: [4:1]; default: 0; + * This field indicates the data to be written next time + */ + uint32_t core_0_message_expect:4; + /** core_0_message_dataphase : RO; bitpos: [5]; default: 0; + * If this bit is 1, it means that is checking clear write_buffer operation,and is + * checking data + */ + uint32_t core_0_message_dataphase:1; + /** core_0_message_addressphase : RO; bitpos: [6]; default: 0; + * If this bit is 1, it means that is checking clear write_buffer operation,and is + * checking address. + */ + uint32_t core_0_message_addressphase:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} wcl_core_0_message_phase_reg_t; + +/** Type of core_1_entry_1_addr register + * Core_1 Entry 1 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_1_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 1 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_1_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_1_addr_reg_t; + +/** Type of core_1_entry_2_addr register + * Core_1 Entry 2 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_2_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 2 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_2_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_2_addr_reg_t; + +/** Type of core_1_entry_3_addr register + * Core_1 Entry 3 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_3_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 3 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_3_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_3_addr_reg_t; + +/** Type of core_1_entry_4_addr register + * Core_1 Entry 4 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_4_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 4 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_4_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_4_addr_reg_t; + +/** Type of core_1_entry_5_addr register + * Core_1 Entry 5 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_5_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 5 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_5_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_5_addr_reg_t; + +/** Type of core_1_entry_6_addr register + * Core_1 Entry 6 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_6_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 6 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_6_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_6_addr_reg_t; + +/** Type of core_1_entry_7_addr register + * Core_1 Entry 7 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_7_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 7 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_7_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_7_addr_reg_t; + +/** Type of core_1_entry_8_addr register + * Core_1 Entry 8 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_8_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 8 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_8_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_8_addr_reg_t; + +/** Type of core_1_entry_9_addr register + * Core_1 Entry 9 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_9_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 9 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_9_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_9_addr_reg_t; + +/** Type of core_1_entry_10_addr register + * Core_1 Entry 10 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_10_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 10 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_10_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_10_addr_reg_t; + +/** Type of core_1_entry_11_addr register + * Core_1 Entry 11 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_11_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 11 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_11_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_11_addr_reg_t; + +/** Type of core_1_entry_12_addr register + * Core_1 Entry 12 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_12_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 12 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_12_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_12_addr_reg_t; + +/** Type of core_1_entry_13_addr register + * Core_1 Entry 13 address configuration Register + */ +typedef union { + struct { + /** core_1_entry_13_addr : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 13 address from WORLD1 to WORLD0 + */ + uint32_t core_1_entry_13_addr:32; + }; + uint32_t val; +} wcl_core_1_entry_13_addr_reg_t; + +/** Type of core_1_entry_check register + * Core_1 Entry check configuration Register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** core_1_entry_check : R/W; bitpos: [13:1]; default: 1; + * This filed is used to enable entry address check + */ + uint32_t core_1_entry_check:13; + uint32_t reserved_14:18; + }; + uint32_t val; +} wcl_core_1_entry_check_reg_t; + +/** Type of core_1_message_addr register + * Clear writer_buffer write address configuration register + */ +typedef union { + struct { + /** core_1_message_addr : R/W; bitpos: [31:0]; default: 0; + * This field is used to set address that need to write when enter WORLD0 + */ + uint32_t core_1_message_addr:32; + }; + uint32_t val; +} wcl_core_1_message_addr_reg_t; + +/** Type of core_1_message_max register + * Clear writer_buffer write number configuration register + */ +typedef union { + struct { + /** core_1_message_max : R/W; bitpos: [3:0]; default: 0; + * This filed is used to set the max value of clear write_buffer + */ + uint32_t core_1_message_max:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} wcl_core_1_message_max_reg_t; + +/** Type of core_1_message_phase register + * Clear writer_buffer status register + */ +typedef union { + struct { + /** core_1_message_match : RO; bitpos: [0]; default: 0; + * This bit indicates whether the check is successful + */ + uint32_t core_1_message_match:1; + /** core_1_message_expect : RO; bitpos: [4:1]; default: 0; + * This field indicates the data to be written next time + */ + uint32_t core_1_message_expect:4; + /** core_1_message_dataphase : RO; bitpos: [5]; default: 0; + * If this bit is 1, it means that is checking clear write_buffer operation, and is + * checking data + */ + uint32_t core_1_message_dataphase:1; + /** core_1_message_addressphase : RO; bitpos: [6]; default: 0; + * If this bit is 1, it means that is checking clear write_buffer operation, and is + * checking address. + */ + uint32_t core_1_message_addressphase:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} wcl_core_1_message_phase_reg_t; + + +/** Group: StatusTable Registers */ +/** Type of core_0_statustable1 register + * Status register of world switch of entry 1 + */ +typedef union { + struct { + /** core_0_from_world_1 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 1 + */ + uint32_t core_0_from_world_1:1; + /** core_0_from_entry_1 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 1 + */ + uint32_t core_0_from_entry_1:4; + /** core_0_current_1 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 1 + */ + uint32_t core_0_current_1:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable1_reg_t; + +/** Type of core_0_statustable2 register + * Status register of world switch of entry 2 + */ +typedef union { + struct { + /** core_0_from_world_2 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 2 + */ + uint32_t core_0_from_world_2:1; + /** core_0_from_entry_2 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 2 + */ + uint32_t core_0_from_entry_2:4; + /** core_0_current_2 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 2 + */ + uint32_t core_0_current_2:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable2_reg_t; + +/** Type of core_0_statustable3 register + * Status register of world switch of entry 3 + */ +typedef union { + struct { + /** core_0_from_world_3 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 3 + */ + uint32_t core_0_from_world_3:1; + /** core_0_from_entry_3 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 3 + */ + uint32_t core_0_from_entry_3:4; + /** core_0_current_3 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 3 + */ + uint32_t core_0_current_3:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable3_reg_t; + +/** Type of core_0_statustable4 register + * Status register of world switch of entry 4 + */ +typedef union { + struct { + /** core_0_from_world_4 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 4 + */ + uint32_t core_0_from_world_4:1; + /** core_0_from_entry_4 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 4 + */ + uint32_t core_0_from_entry_4:4; + /** core_0_current_4 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 4 + */ + uint32_t core_0_current_4:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable4_reg_t; + +/** Type of core_0_statustable5 register + * Status register of world switch of entry 5 + */ +typedef union { + struct { + /** core_0_from_world_5 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 5 + */ + uint32_t core_0_from_world_5:1; + /** core_0_from_entry_5 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 5 + */ + uint32_t core_0_from_entry_5:4; + /** core_0_current_5 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 5 + */ + uint32_t core_0_current_5:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable5_reg_t; + +/** Type of core_0_statustable6 register + * Status register of world switch of entry 6 + */ +typedef union { + struct { + /** core_0_from_world_6 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 6 + */ + uint32_t core_0_from_world_6:1; + /** core_0_from_entry_6 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 6 + */ + uint32_t core_0_from_entry_6:4; + /** core_0_current_6 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 6 + */ + uint32_t core_0_current_6:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable6_reg_t; + +/** Type of core_0_statustable7 register + * Status register of world switch of entry 7 + */ +typedef union { + struct { + /** core_0_from_world_7 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 7 + */ + uint32_t core_0_from_world_7:1; + /** core_0_from_entry_7 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 7 + */ + uint32_t core_0_from_entry_7:4; + /** core_0_current_7 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 7 + */ + uint32_t core_0_current_7:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable7_reg_t; + +/** Type of core_0_statustable8 register + * Status register of world switch of entry 8 + */ +typedef union { + struct { + /** core_0_from_world_8 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 8 + */ + uint32_t core_0_from_world_8:1; + /** core_0_from_entry_8 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 8 + */ + uint32_t core_0_from_entry_8:4; + /** core_0_current_8 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 8 + */ + uint32_t core_0_current_8:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable8_reg_t; + +/** Type of core_0_statustable9 register + * Status register of world switch of entry 9 + */ +typedef union { + struct { + /** core_0_from_world_9 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 9 + */ + uint32_t core_0_from_world_9:1; + /** core_0_from_entry_9 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 9 + */ + uint32_t core_0_from_entry_9:4; + /** core_0_current_9 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 9 + */ + uint32_t core_0_current_9:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable9_reg_t; + +/** Type of core_0_statustable10 register + * Status register of world switch of entry 10 + */ +typedef union { + struct { + /** core_0_from_world_10 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 10 + */ + uint32_t core_0_from_world_10:1; + /** core_0_from_entry_10 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 10 + */ + uint32_t core_0_from_entry_10:4; + /** core_0_current_10 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 10 + */ + uint32_t core_0_current_10:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable10_reg_t; + +/** Type of core_0_statustable11 register + * Status register of world switch of entry 11 + */ +typedef union { + struct { + /** core_0_from_world_11 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 11 + */ + uint32_t core_0_from_world_11:1; + /** core_0_from_entry_11 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 11 + */ + uint32_t core_0_from_entry_11:4; + /** core_0_current_11 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 11 + */ + uint32_t core_0_current_11:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable11_reg_t; + +/** Type of core_0_statustable12 register + * Status register of world switch of entry 12 + */ +typedef union { + struct { + /** core_0_from_world_12 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 12 + */ + uint32_t core_0_from_world_12:1; + /** core_0_from_entry_12 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 12 + */ + uint32_t core_0_from_entry_12:4; + /** core_0_current_12 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 12 + */ + uint32_t core_0_current_12:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable12_reg_t; + +/** Type of core_0_statustable13 register + * Status register of world switch of entry 13 + */ +typedef union { + struct { + /** core_0_from_world_13 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 13 + */ + uint32_t core_0_from_world_13:1; + /** core_0_from_entry_13 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 13 + */ + uint32_t core_0_from_entry_13:4; + /** core_0_current_13 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 13 + */ + uint32_t core_0_current_13:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_0_statustable13_reg_t; + +/** Type of core_0_statustable_current register + * Status register of statustable current + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** core_0_statustable_current : R/W; bitpos: [13:1]; default: 0; + * This field is used to quickly read and rewrite the current field of all STATUSTABLE + * registers,for example,bit 1 represents the current field of STATUSTABLE1,bit2 + * represents the current field of STATUSTABLE2 + */ + uint32_t core_0_statustable_current:13; + uint32_t reserved_14:18; + }; + uint32_t val; +} wcl_core_0_statustable_current_reg_t; + +/** Type of core_1_statustable1 register + * Status register of world switch of entry 1 + */ +typedef union { + struct { + /** core_1_from_world_1 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 1 + */ + uint32_t core_1_from_world_1:1; + /** core_1_from_entry_1 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 1 + */ + uint32_t core_1_from_entry_1:4; + /** core_1_current_1 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 1 + */ + uint32_t core_1_current_1:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable1_reg_t; + +/** Type of core_1_statustable2 register + * Status register of world switch of entry 2 + */ +typedef union { + struct { + /** core_1_from_world_2 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 2 + */ + uint32_t core_1_from_world_2:1; + /** core_1_from_entry_2 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 2 + */ + uint32_t core_1_from_entry_2:4; + /** core_1_current_2 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 2 + */ + uint32_t core_1_current_2:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable2_reg_t; + +/** Type of core_1_statustable3 register + * Status register of world switch of entry 3 + */ +typedef union { + struct { + /** core_1_from_world_3 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 3 + */ + uint32_t core_1_from_world_3:1; + /** core_1_from_entry_3 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 3 + */ + uint32_t core_1_from_entry_3:4; + /** core_1_current_3 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 3 + */ + uint32_t core_1_current_3:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable3_reg_t; + +/** Type of core_1_statustable4 register + * Status register of world switch of entry 4 + */ +typedef union { + struct { + /** core_1_from_world_4 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 4 + */ + uint32_t core_1_from_world_4:1; + /** core_1_from_entry_4 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 4 + */ + uint32_t core_1_from_entry_4:4; + /** core_1_current_4 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 4 + */ + uint32_t core_1_current_4:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable4_reg_t; + +/** Type of core_1_statustable5 register + * Status register of world switch of entry 5 + */ +typedef union { + struct { + /** core_1_from_world_5 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 5 + */ + uint32_t core_1_from_world_5:1; + /** core_1_from_entry_5 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 5 + */ + uint32_t core_1_from_entry_5:4; + /** core_1_current_5 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 5 + */ + uint32_t core_1_current_5:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable5_reg_t; + +/** Type of core_1_statustable6 register + * Status register of world switch of entry 6 + */ +typedef union { + struct { + /** core_1_from_world_6 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 6 + */ + uint32_t core_1_from_world_6:1; + /** core_1_from_entry_6 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 6 + */ + uint32_t core_1_from_entry_6:4; + /** core_1_current_6 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 6 + */ + uint32_t core_1_current_6:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable6_reg_t; + +/** Type of core_1_statustable7 register + * Status register of world switch of entry 7 + */ +typedef union { + struct { + /** core_1_from_world_7 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 7 + */ + uint32_t core_1_from_world_7:1; + /** core_1_from_entry_7 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 7 + */ + uint32_t core_1_from_entry_7:4; + /** core_1_current_7 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 7 + */ + uint32_t core_1_current_7:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable7_reg_t; + +/** Type of core_1_statustable8 register + * Status register of world switch of entry 8 + */ +typedef union { + struct { + /** core_1_from_world_8 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 8 + */ + uint32_t core_1_from_world_8:1; + /** core_1_from_entry_8 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 8 + */ + uint32_t core_1_from_entry_8:4; + /** core_1_current_8 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 8 + */ + uint32_t core_1_current_8:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable8_reg_t; + +/** Type of core_1_statustable9 register + * Status register of world switch of entry 9 + */ +typedef union { + struct { + /** core_1_from_world_9 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 9 + */ + uint32_t core_1_from_world_9:1; + /** core_1_from_entry_9 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 9 + */ + uint32_t core_1_from_entry_9:4; + /** core_1_current_9 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 9 + */ + uint32_t core_1_current_9:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable9_reg_t; + +/** Type of core_1_statustable10 register + * Status register of world switch of entry 10 + */ +typedef union { + struct { + /** core_1_from_world_10 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 10 + */ + uint32_t core_1_from_world_10:1; + /** core_1_from_entry_10 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 10 + */ + uint32_t core_1_from_entry_10:4; + /** core_1_current_10 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 10 + */ + uint32_t core_1_current_10:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable10_reg_t; + +/** Type of core_1_statustable11 register + * Status register of world switch of entry 11 + */ +typedef union { + struct { + /** core_1_from_world_11 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 11 + */ + uint32_t core_1_from_world_11:1; + /** core_1_from_entry_11 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 11 + */ + uint32_t core_1_from_entry_11:4; + /** core_1_current_11 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 11 + */ + uint32_t core_1_current_11:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable11_reg_t; + +/** Type of core_1_statustable12 register + * Status register of world switch of entry 12 + */ +typedef union { + struct { + /** core_1_from_world_12 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 12 + */ + uint32_t core_1_from_world_12:1; + /** core_1_from_entry_12 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 12 + */ + uint32_t core_1_from_entry_12:4; + /** core_1_current_12 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 12 + */ + uint32_t core_1_current_12:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable12_reg_t; + +/** Type of core_1_statustable13 register + * Status register of world switch of entry 13 + */ +typedef union { + struct { + /** core_1_from_world_13 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 13 + */ + uint32_t core_1_from_world_13:1; + /** core_1_from_entry_13 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 13 + */ + uint32_t core_1_from_entry_13:4; + /** core_1_current_13 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 13 + */ + uint32_t core_1_current_13:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} wcl_core_1_statustable13_reg_t; + +/** Type of core_1_statustable_current register + * Status register of statustable current + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** core_1_statustable_current : R/W; bitpos: [13:1]; default: 0; + * This field is used to quickly read and rewrite the current field of all STATUSTABLE + * registers,for example,bit 1 represents the current field of STATUSTABLE1 + */ + uint32_t core_1_statustable_current:13; + uint32_t reserved_14:18; + }; + uint32_t val; +} wcl_core_1_statustable_current_reg_t; + + +/** Group: WORLD0 to WORLD1 configuration Registers */ +/** Type of core_0_world_trigger_addr register + * Core_0 trigger address configuration Register + */ +typedef union { + struct { + /** core_0_world_trigger_addr : RW; bitpos: [31:0]; default: 0; + * This field is used to configure the entry address from WORLD0 to WORLD1,when the + * CPU executes to this address,switch to WORLD1 + */ + uint32_t core_0_world_trigger_addr:32; + }; + uint32_t val; +} wcl_core_0_world_trigger_addr_reg_t; + +/** Type of core_0_world_prepare register + * Core_0 prepare world configuration Register + */ +typedef union { + struct { + /** core_0_world_prepare : R/W; bitpos: [1:0]; default: 0; + * This field to used to set world to enter, 2'b01 means WORLD0, 2'b10 means WORLD1 + */ + uint32_t core_0_world_prepare:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} wcl_core_0_world_prepare_reg_t; + +/** Type of core_0_world_update register + * Core_0 configuration update register + */ +typedef union { + struct { + /** core_0_update : WO; bitpos: [31:0]; default: 0; + * This field is used to update configuration completed, can write any value,the + * hardware only checks the write operation of this register and does not case about + * its value + */ + uint32_t core_0_update:32; + }; + uint32_t val; +} wcl_core_0_world_update_reg_t; + +/** Type of core_0_world_cancel register + * Core_0 configuration cancel register + */ +typedef union { + struct { + /** core_0_world_cancel : WO; bitpos: [31:0]; default: 0; + * This field is used to cancel switch world configuration,if the trigger address and + * update configuration complete,use this register to cancel world switch, jujst need + * write any value,the hardware only checks the write operation of this register and + * does not case about its value + */ + uint32_t core_0_world_cancel:32; + }; + uint32_t val; +} wcl_core_0_world_cancel_reg_t; + +/** Type of core_0_world_iram0 register + * Core_0 Iram0 world register + */ +typedef union { + struct { + /** core_0_world_iram0 : R/W; bitpos: [1:0]; default: 0; + * this field is used to read current world of Iram0 bus + */ + uint32_t core_0_world_iram0:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} wcl_core_0_world_iram0_reg_t; + +/** Type of core_0_world_dram0_pif register + * Core_0 dram0 and PIF world register + */ +typedef union { + struct { + /** core_0_world_dram0_pif : R/W; bitpos: [1:0]; default: 0; + * this field is used to read current world of Dram0 bus and PIF bus + */ + uint32_t core_0_world_dram0_pif:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} wcl_core_0_world_dram0_pif_reg_t; + +/** Type of core_0_world_phase register + * Core_0 world status register + */ +typedef union { + struct { + /** core_0_world_phase : RO; bitpos: [0]; default: 0; + * This bit indicates whether is preparing to switch to WORLD1, 1 means value. + */ + uint32_t core_0_world_phase:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} wcl_core_0_world_phase_reg_t; + +/** Type of core_1_world_trigger_addr register + * Core_1 trigger address configuration Register + */ +typedef union { + struct { + /** core_1_world_trigger_addr : RW; bitpos: [31:0]; default: 0; + * This field is used to configure the entry address from WORLD0 to WORLD1,when the + * CPU executes to this address,switch to WORLD1 + */ + uint32_t core_1_world_trigger_addr:32; + }; + uint32_t val; +} wcl_core_1_world_trigger_addr_reg_t; + +/** Type of core_1_world_prepare register + * Core_1 prepare world configuration Register + */ +typedef union { + struct { + /** core_1_world_prepare : R/W; bitpos: [1:0]; default: 0; + * This field to used to set world to enter,2'b01 means WORLD0, 2'b10 means WORLD1 + */ + uint32_t core_1_world_prepare:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} wcl_core_1_world_prepare_reg_t; + +/** Type of core_1_world_update register + * Core_1 configuration update register + */ +typedef union { + struct { + /** core_1_update : WO; bitpos: [31:0]; default: 0; + * This field is used to update configuration completed, can write any value,the + * hardware only checks the write operation of this register and does not case about + * its value + */ + uint32_t core_1_update:32; + }; + uint32_t val; +} wcl_core_1_world_update_reg_t; + +/** Type of core_1_world_cancel register + * Core_1 configuration cancel register + */ +typedef union { + struct { + /** core_1_world_cancel : WO; bitpos: [31:0]; default: 0; + * This field is used to cancel switch world configuration,if the trigger address and + * update configuration complete,can use this register to cancel world switch. can + * write any value, the hardware only checks the write operation of this register and + * does not case about its value + */ + uint32_t core_1_world_cancel:32; + }; + uint32_t val; +} wcl_core_1_world_cancel_reg_t; + +/** Type of core_1_world_iram0 register + * Core_1 Iram0 world register + */ +typedef union { + struct { + /** core_1_world_iram0 : R/W; bitpos: [1:0]; default: 0; + * this field is used to read current world of Iram0 bus + */ + uint32_t core_1_world_iram0:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} wcl_core_1_world_iram0_reg_t; + +/** Type of core_1_world_dram0_pif register + * Core_1 dram0 and PIF world register + */ +typedef union { + struct { + /** core_1_world_dram0_pif : R/W; bitpos: [1:0]; default: 0; + * this field is used to read current world of Dram0 bus and PIF bus + */ + uint32_t core_1_world_dram0_pif:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} wcl_core_1_world_dram0_pif_reg_t; + +/** Type of core_1_world_phase register + * Core_0 world status register + */ +typedef union { + struct { + /** core_1_world_phase : RO; bitpos: [0]; default: 0; + * This bit indicates whether is preparing to switch to WORLD1,1 means value. + */ + uint32_t core_1_world_phase:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} wcl_core_1_world_phase_reg_t; + + +/** Group: NMI mask configuration Registers */ +/** Type of core_0_nmi_mask_enable register + * Core_0 NMI mask enable register + */ +typedef union { + struct { + /** core_0_nmi_mask_enable : WO; bitpos: [31:0]; default: 0; + * this field is used to set NMI mask,it can write any value,when write this + * register,the hardware start masking NMI interrupt + */ + uint32_t core_0_nmi_mask_enable:32; + }; + uint32_t val; +} wcl_core_0_nmi_mask_enable_reg_t; + +/** Type of core_0_nmi_mask_trigger_addr register + * Core_0 NMI mask trigger address register + */ +typedef union { + struct { + /** core_0_nmi_mask_trigger_addr : R/W; bitpos: [31:0]; default: 0; + * this field to used to set trigger address, when CPU executes to this address,NMI + * mask automatically fails + */ + uint32_t core_0_nmi_mask_trigger_addr:32; + }; + uint32_t val; +} wcl_core_0_nmi_mask_trigger_addr_reg_t; + +/** Type of core_0_nmi_mask_disable register + * Core_0 NMI mask disable register + */ +typedef union { + struct { + /** core_0_nmi_mask_disable : WO; bitpos: [31:0]; default: 0; + * this field is used to disable NMI mask,it will not take effect immediately,only + * when the CPU executes to the trigger address will it start to cancel NMI mask + */ + uint32_t core_0_nmi_mask_disable:32; + }; + uint32_t val; +} wcl_core_0_nmi_mask_disable_reg_t; + +/** Type of core_0_nmi_mask_cancle register + * Core_0 NMI mask disable register + */ +typedef union { + struct { + /** core_0_nmi_mask_cancel : WO; bitpos: [31:0]; default: 0; + * this field is used to cancel NMI mask disable function. + */ + uint32_t core_0_nmi_mask_cancel:32; + }; + uint32_t val; +} wcl_core_0_nmi_mask_cancle_reg_t; + +/** Type of core_0_nmi_mask register + * Core_0 NMI mask register + */ +typedef union { + struct { + /** core_0_nmi_mask : R/W; bitpos: [0]; default: 0; + * this bit is used to mask NMI interrupt,it can directly mask NMI interrupt + */ + uint32_t core_0_nmi_mask:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} wcl_core_0_nmi_mask_reg_t; + +/** Type of core_0_nmi_mask_phase register + * Core_0 NMI mask phase register + */ +typedef union { + struct { + /** core_0_nmi_mask_phase : RO; bitpos: [0]; default: 0; + * this bit is used to indicates whether the NMI interrupt is being masked, 1 means + * NMI interrupt is being masked + */ + uint32_t core_0_nmi_mask_phase:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} wcl_core_0_nmi_mask_phase_reg_t; + +/** Type of core_1_nmi_mask_enable register + * Core_1 NMI mask enable register + */ +typedef union { + struct { + /** core_1_nmi_mask_enable : WO; bitpos: [31:0]; default: 0; + * this field is used to set NMI mask, it can write any value, when write this + * register,the hardware start masking NMI interrupt + */ + uint32_t core_1_nmi_mask_enable:32; + }; + uint32_t val; +} wcl_core_1_nmi_mask_enable_reg_t; + +/** Type of core_1_nmi_mask_trigger_addr register + * Core_1 NMI mask trigger addr register + */ +typedef union { + struct { + /** core_1_nmi_mask_trigger_addr : R/W; bitpos: [31:0]; default: 0; + * this field to used to set trigger address + */ + uint32_t core_1_nmi_mask_trigger_addr:32; + }; + uint32_t val; +} wcl_core_1_nmi_mask_trigger_addr_reg_t; + +/** Type of core_1_nmi_mask_disable register + * Core_1 NMI mask disable register + */ +typedef union { + struct { + /** core_1_nmi_mask_disable : WO; bitpos: [31:0]; default: 0; + * this field is used to disable NMI mask, it will not take effect immediately,only + * when the CPU executes to the trigger address will it start to cancel NMI mask + */ + uint32_t core_1_nmi_mask_disable:32; + }; + uint32_t val; +} wcl_core_1_nmi_mask_disable_reg_t; + +/** Type of core_1_nmi_mask_cancle register + * Core_1 NMI mask disable register + */ +typedef union { + struct { + /** core_1_nmi_mask_cancel : WO; bitpos: [31:0]; default: 0; + * this field is used to cancel NMI mask disable function. + */ + uint32_t core_1_nmi_mask_cancel:32; + }; + uint32_t val; +} wcl_core_1_nmi_mask_cancle_reg_t; + +/** Type of core_1_nmi_mask register + * Core_1 NMI mask register + */ +typedef union { + struct { + /** core_1_nmi_mask : R/W; bitpos: [0]; default: 0; + * this bit is used to mask NMI interrupt,it can directly mask NMI interrupt + */ + uint32_t core_1_nmi_mask:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} wcl_core_1_nmi_mask_reg_t; + +/** Type of core_1_nmi_mask_phase register + * Core_1 NMI mask phase register + */ +typedef union { + struct { + /** core_1_nmi_mask_phase : RO; bitpos: [0]; default: 0; + * this bit is used to indicates whether the NMI interrupt is being masked, 1 means + * NMI interrupt is being masked + */ + uint32_t core_1_nmi_mask_phase:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} wcl_core_1_nmi_mask_phase_reg_t; + + +typedef struct { + volatile wcl_core_0_entry_1_addr_reg_t core_0_entry_1_addr; + volatile wcl_core_0_entry_2_addr_reg_t core_0_entry_2_addr; + volatile wcl_core_0_entry_3_addr_reg_t core_0_entry_3_addr; + volatile wcl_core_0_entry_4_addr_reg_t core_0_entry_4_addr; + volatile wcl_core_0_entry_5_addr_reg_t core_0_entry_5_addr; + volatile wcl_core_0_entry_6_addr_reg_t core_0_entry_6_addr; + volatile wcl_core_0_entry_7_addr_reg_t core_0_entry_7_addr; + volatile wcl_core_0_entry_8_addr_reg_t core_0_entry_8_addr; + volatile wcl_core_0_entry_9_addr_reg_t core_0_entry_9_addr; + volatile wcl_core_0_entry_10_addr_reg_t core_0_entry_10_addr; + volatile wcl_core_0_entry_11_addr_reg_t core_0_entry_11_addr; + volatile wcl_core_0_entry_12_addr_reg_t core_0_entry_12_addr; + volatile wcl_core_0_entry_13_addr_reg_t core_0_entry_13_addr; + uint32_t reserved_034[18]; + volatile wcl_core_0_entry_check_reg_t core_0_entry_check; + volatile wcl_core_0_statustable1_reg_t core_0_statustable1; + volatile wcl_core_0_statustable2_reg_t core_0_statustable2; + volatile wcl_core_0_statustable3_reg_t core_0_statustable3; + volatile wcl_core_0_statustable4_reg_t core_0_statustable4; + volatile wcl_core_0_statustable5_reg_t core_0_statustable5; + volatile wcl_core_0_statustable6_reg_t core_0_statustable6; + volatile wcl_core_0_statustable7_reg_t core_0_statustable7; + volatile wcl_core_0_statustable8_reg_t core_0_statustable8; + volatile wcl_core_0_statustable9_reg_t core_0_statustable9; + volatile wcl_core_0_statustable10_reg_t core_0_statustable10; + volatile wcl_core_0_statustable11_reg_t core_0_statustable11; + volatile wcl_core_0_statustable12_reg_t core_0_statustable12; + volatile wcl_core_0_statustable13_reg_t core_0_statustable13; + uint32_t reserved_0b4[18]; + volatile wcl_core_0_statustable_current_reg_t core_0_statustable_current; + volatile wcl_core_0_message_addr_reg_t core_0_message_addr; + volatile wcl_core_0_message_max_reg_t core_0_message_max; + volatile wcl_core_0_message_phase_reg_t core_0_message_phase; + uint32_t reserved_10c[13]; + volatile wcl_core_0_world_trigger_addr_reg_t core_0_world_trigger_addr; + volatile wcl_core_0_world_prepare_reg_t core_0_world_prepare; + volatile wcl_core_0_world_update_reg_t core_0_world_update; + volatile wcl_core_0_world_cancel_reg_t core_0_world_cancel; + volatile wcl_core_0_world_iram0_reg_t core_0_world_iram0; + volatile wcl_core_0_world_dram0_pif_reg_t core_0_world_dram0_pif; + volatile wcl_core_0_world_phase_reg_t core_0_world_phase; + uint32_t reserved_15c[9]; + volatile wcl_core_0_nmi_mask_enable_reg_t core_0_nmi_mask_enable; + volatile wcl_core_0_nmi_mask_trigger_addr_reg_t core_0_nmi_mask_trigger_addr; + volatile wcl_core_0_nmi_mask_disable_reg_t core_0_nmi_mask_disable; + volatile wcl_core_0_nmi_mask_cancle_reg_t core_0_nmi_mask_cancle; + volatile wcl_core_0_nmi_mask_reg_t core_0_nmi_mask; + volatile wcl_core_0_nmi_mask_phase_reg_t core_0_nmi_mask_phase; + uint32_t reserved_198[154]; + volatile wcl_core_1_entry_1_addr_reg_t core_1_entry_1_addr; + volatile wcl_core_1_entry_2_addr_reg_t core_1_entry_2_addr; + volatile wcl_core_1_entry_3_addr_reg_t core_1_entry_3_addr; + volatile wcl_core_1_entry_4_addr_reg_t core_1_entry_4_addr; + volatile wcl_core_1_entry_5_addr_reg_t core_1_entry_5_addr; + volatile wcl_core_1_entry_6_addr_reg_t core_1_entry_6_addr; + volatile wcl_core_1_entry_7_addr_reg_t core_1_entry_7_addr; + volatile wcl_core_1_entry_8_addr_reg_t core_1_entry_8_addr; + volatile wcl_core_1_entry_9_addr_reg_t core_1_entry_9_addr; + volatile wcl_core_1_entry_10_addr_reg_t core_1_entry_10_addr; + volatile wcl_core_1_entry_11_addr_reg_t core_1_entry_11_addr; + volatile wcl_core_1_entry_12_addr_reg_t core_1_entry_12_addr; + volatile wcl_core_1_entry_13_addr_reg_t core_1_entry_13_addr; + uint32_t reserved_434[18]; + volatile wcl_core_1_entry_check_reg_t core_1_entry_check; + volatile wcl_core_1_statustable1_reg_t core_1_statustable1; + volatile wcl_core_1_statustable2_reg_t core_1_statustable2; + volatile wcl_core_1_statustable3_reg_t core_1_statustable3; + volatile wcl_core_1_statustable4_reg_t core_1_statustable4; + volatile wcl_core_1_statustable5_reg_t core_1_statustable5; + volatile wcl_core_1_statustable6_reg_t core_1_statustable6; + volatile wcl_core_1_statustable7_reg_t core_1_statustable7; + volatile wcl_core_1_statustable8_reg_t core_1_statustable8; + volatile wcl_core_1_statustable9_reg_t core_1_statustable9; + volatile wcl_core_1_statustable10_reg_t core_1_statustable10; + volatile wcl_core_1_statustable11_reg_t core_1_statustable11; + volatile wcl_core_1_statustable12_reg_t core_1_statustable12; + volatile wcl_core_1_statustable13_reg_t core_1_statustable13; + uint32_t reserved_4b4[18]; + volatile wcl_core_1_statustable_current_reg_t core_1_statustable_current; + volatile wcl_core_1_message_addr_reg_t core_1_message_addr; + volatile wcl_core_1_message_max_reg_t core_1_message_max; + volatile wcl_core_1_message_phase_reg_t core_1_message_phase; + uint32_t reserved_50c[13]; + volatile wcl_core_1_world_trigger_addr_reg_t core_1_world_trigger_addr; + volatile wcl_core_1_world_prepare_reg_t core_1_world_prepare; + volatile wcl_core_1_world_update_reg_t core_1_world_update; + volatile wcl_core_1_world_cancel_reg_t core_1_world_cancel; + volatile wcl_core_1_world_iram0_reg_t core_1_world_iram0; + volatile wcl_core_1_world_dram0_pif_reg_t core_1_world_dram0_pif; + volatile wcl_core_1_world_phase_reg_t core_1_world_phase; + uint32_t reserved_55c[9]; + volatile wcl_core_1_nmi_mask_enable_reg_t core_1_nmi_mask_enable; + volatile wcl_core_1_nmi_mask_trigger_addr_reg_t core_1_nmi_mask_trigger_addr; + volatile wcl_core_1_nmi_mask_disable_reg_t core_1_nmi_mask_disable; + volatile wcl_core_1_nmi_mask_cancle_reg_t core_1_nmi_mask_cancle; + volatile wcl_core_1_nmi_mask_reg_t core_1_nmi_mask; + volatile wcl_core_1_nmi_mask_phase_reg_t core_1_nmi_mask_phase; +} wcl_dev_t; + +extern wcl_dev_t WORLD_CONTROLLER; + +#ifndef __cplusplus +_Static_assert(sizeof(wcl_dev_t) == 0x598, "Invalid size of wcl_dev_t structure"); +#endif + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s3/interrupts.c b/components/soc/esp32s3/interrupts.c index 1de9d9057b..3f074b00b9 100644 --- a/components/soc/esp32s3/interrupts.c +++ b/components/soc/esp32s3/interrupts.c @@ -1,87 +1,105 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include "soc/interrupts.h" const char *const esp_isr_names[ETS_MAX_INTR_SOURCE] = { [0] = "WIFI_MAC", [1] = "WIFI_NMI", - [2] = "WIFI_BB", - [3] = "BT_MAC", - [4] = "BT_BB", - [5] = "BT_BB_NMI", - [6] = "RWBT", - [7] = "RWBLE", - [8] = "RWBT_NMI", - [9] = "RWBLE_NMI", - [10] = "SLC0", - [11] = "SLC1", - [12] = "UHCI0", - [13] = "UHCI1", - [14] = "TG0_T0_LEVEL", - [15] = "TG0_T1_LEVEL", - [16] = "TG0_WDT_LEVEL", - [17] = "TG0_LACT_LEVEL", - [18] = "TG1_T0_LEVEL", - [19] = "TG1_T1_LEVEL", - [20] = "TG1_WDT_LEVEL", - [21] = "TG1_LACT_LEVEL", - [22] = "GPIO", - [23] = "GPIO_NMI", - [24] = "FROM_CPU0", - [25] = "FROM_CPU1", - [26] = "FROM_CPU2", - [27] = "FROM_CPU3", - [28] = "SPI0", - [29] = "SPI1", - [30] = "SPI2", - [31] = "SPI3", - [32] = "I2S0", - [33] = "I2S1", - [34] = "UART0", - [35] = "UART1", - [36] = "UART2", - [37] = "SDIO_HOST", - [38] = "ETH_MAC", - [39] = "PWM0", - [40] = "PWM1", - [41] = "PWM2", - [42] = "PWM3", - [43] = "LEDC", - [44] = "EFUSE", - [45] = "TWAI", - [46] = "RTC_CORE", - [47] = "RMT", - [48] = "PCNT", - [49] = "I2C_EXT0", - [50] = "I2C_EXT1", - [51] = "RSA", - [52] = "SPI1_DMA", - [53] = "SPI2_DMA", - [54] = "SPI3_DMA", - [55] = "WDT", - [56] = "TIMER1", - [57] = "TIMER2", - [58] = "TG0_T0_EDGE", - [59] = "TG0_T1_EDGE", - [60] = "TG0_WDT_EDGE", - [61] = "TG0_LACT_EDGE", - [62] = "TG1_T0_EDGE", - [63] = "TG1_T1_EDGE", - [64] = "TG1_WDT_EDGE", - [65] = "TG1_LACT_EDGE", - [66] = "MMU_IA", - [67] = "MPU_IA", - [68] = "CACHE_IA", + [2] = "WIFI_PWR", + [3] = "WIFI_BB", + [4] = "BT_MAC", + [5] = "BT_BB", + [6] = "BT_BB_NMI", + [7] = "RWBT", + [8] = "RWBLE", + [9] = "RWBT_NMI", + [10] = "RWBLE_NMI", + [11] = "I2C_MASTER", + [12] = "SLC0", + [13] = "SLC1", + [14] = "UHCI0", + [15] = "UHCI1", + [16] = "GPIO", + [17] = "GPIO_NMI", + [18] = "GPIO_INTR_2", + [19] = "GPIO_NMI_2", + [20] = "SPI1", + [21] = "SPI2", + [22] = "SPI3", + [24] = "LCD_CAM", + [25] = "I2S0", + [26] = "I2S1", + [27] = "UART0", + [28] = "UART1", + [29] = "UART2", + [30] = "SDIO_HOST", + [31] = "PWM0", + [32] = "PWM1", + [35] = "LEDC", + [36] = "EFUSE", + [37] = "TWAI", + [38] = "USB", + [39] = "RTC_CORE", + [40] = "RMT", + [41] = "PCNT", + [42] = "I2C_EXT0", + [43] = "I2C_EXT1", + [44] = "SPI2_DMA", + [45] = "SPI3_DMA", + [47] = "WDT", + [48] = "TIMER1", + [49] = "TIMER2", + [50] = "TG0_T0_LEVEL", + [51] = "TG0_T1_LEVEL", + [52] = "TG0_WDT_LEVEL", + [53] = "TG1_T0_LEVEL", + [54] = "TG1_T1_LEVEL", + [55] = "TG1_WDT_LEVEL", + [56] = "CACHE_IA", + [57] = "SYSTIMER_TARGET0", + [58] = "SYSTIMER_TARGET1", + [59] = "SYSTIMER_TARGET2", + [60] = "SPI_MEM_REJECT_CACHE", + [61] = "DCACHE_PRELOAD0", + [62] = "ICACHE_PRELOAD0", + [63] = "DCACHE_SYNC0", + [64] = "ICACHE_SYNC0", + [65] = "APB_ADC", + [66] = "DMA_IN_CH0", + [67] = "DMA_IN_CH1", + [68] = "DMA_IN_CH2", + [69] = "DMA_IN_CH3", + [70] = "DMA_IN_CH4", + [71] = "DMA_OUT_CH0", + [72] = "DMA_OUT_CH1", + [73] = "DMA_OUT_CH2", + [74] = "DMA_OUT_CH3", + [75] = "DMA_OUT_CH4", + [76] = "RSA", + [77] = "SHA", + [78] = "AES", + [79] = "FROM_CPU_INTR0", + [80] = "FROM_CPU_INTR1", + [81] = "FROM_CPU_INTR2", + [82] = "FROM_CPU_INTR3", + [83] = "ASSIST_DEBUG", + [84] = "DMA_APBPERI_PMS", + [85] = "CORE0_IRAM0_PMS", + [86] = "CORE0_DRAM0_PMS", + [87] = "CORE0_PIF_PMS", + [88] = "CORE0_PIF_PMS_SIZE", + [89] = "CORE1_IRAM0_PMS", + [90] = "CORE1_DRAM0_PMS", + [91] = "CORE1_PIF_PMS", + [92] = "CORE1_PIF_PMS_SIZE", + [93] = "BACKUP_PMS_VIOLATE", + [94] = "CACHE_CORE0_ACS", + [95] = "CACHE_CORE1_ACS", + [96] = "USB_SERIAL_JTAG", + [97] = "PERI_BACKUP", + [98] = "DMA_EXTMEM_REJECT", }; diff --git a/components/soc/esp32s3/ld/esp32s3.peripherals.ld b/components/soc/esp32s3/ld/esp32s3.peripherals.ld index de6ed0abcf..3d69f72f43 100644 --- a/components/soc/esp32s3/ld/esp32s3.peripherals.ld +++ b/components/soc/esp32s3/ld/esp32s3.peripherals.ld @@ -12,6 +12,7 @@ PROVIDE ( EFUSE = 0x60007000 ); PROVIDE ( RTCCNTL = 0x60008000 ); PROVIDE ( RTCIO = 0x60008400 ); PROVIDE ( SENS = 0x60008800 ); +PROVIDE ( RTC_I2C = 0x60008C00 ); PROVIDE ( HINF = 0x6000B000 ); PROVIDE ( I2S0 = 0x6000F000 ); PROVIDE ( I2S1 = 0x6002D000 ); @@ -45,5 +46,6 @@ PROVIDE ( APB_SARADC = 0x60040000 ); PROVIDE ( LCD_CAM = 0x60041000 ); PROVIDE ( USB_SERIAL_JTAG = 0x60038000 ); PROVIDE ( USB0 = 0x60080000 ); -PROVIDE ( USBH = 0x60080000 ); +PROVIDE ( USB_DWC = 0x60080000 ); PROVIDE ( USB_WRAP = 0x60039000 ); +PROVIDE ( WORLD_CONTROLLER = 0x600D0000 ); diff --git a/components/soc/esp32s3/rtc_io_periph.c b/components/soc/esp32s3/rtc_io_periph.c index 6ba215d9c2..029847e116 100644 --- a/components/soc/esp32s3/rtc_io_periph.c +++ b/components/soc/esp32s3/rtc_io_periph.c @@ -1,18 +1,10 @@ -// Copyright 2018-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ -#include "soc/rtc_io_periph.h" +#include "soc/rtc_periph.h" const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = { RTCIO_GPIO0_CHANNEL, //GPIO0 diff --git a/components/soc/esp32s3/spi_periph.c b/components/soc/esp32s3/spi_periph.c index f0c4dcd38e..fb7417ba6d 100644 --- a/components/soc/esp32s3/spi_periph.c +++ b/components/soc/esp32s3/spi_periph.c @@ -1,16 +1,8 @@ -// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include "soc/spi_periph.h" #include "stddef.h" @@ -62,7 +54,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .spid5_in = FSPIIO5_IN_IDX, .spid6_in = FSPIIO6_IN_IDX, .spid7_in = FSPIIO7_IN_IDX, - .spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX}, + .spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX, FSPICS3_OUT_IDX, FSPICS4_OUT_IDX, FSPICS5_OUT_IDX}, .spics_in = FSPICS0_IN_IDX, .spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK, .spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI, diff --git a/components/soc/include/soc/adc_periph.h b/components/soc/include/soc/adc_periph.h index 437d8ad6e6..c45b9e07c4 100644 --- a/components/soc/include/soc/adc_periph.h +++ b/components/soc/include/soc/adc_periph.h @@ -1,22 +1,16 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once #include "soc/soc.h" #include "soc/soc_caps.h" +#if !CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5310 #include "soc/syscon_struct.h" +#endif #if SOC_ADC_RTC_CTRL_SUPPORTED #include "soc/sens_reg.h" @@ -26,7 +20,9 @@ #if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED #include "soc/rtc_io_struct.h" #endif +#if !CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5310 #include "soc/rtc_cntl_struct.h" +#endif #include "soc/adc_channel.h" #include "soc/soc_caps.h" diff --git a/components/soc/include/soc/rtc_cntl_periph.h b/components/soc/include/soc/rtc_cntl_periph.h index 60e3d3216d..e9ed87c7ce 100644 --- a/components/soc/include/soc/rtc_cntl_periph.h +++ b/components/soc/include/soc/rtc_cntl_periph.h @@ -1,18 +1,28 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once +// TODO: IDF-5645 +#if CONFIG_IDF_TARGET_ESP32C6 +#include "soc/lp_aon_reg.h" +#include "soc/lp_analog_peri_reg.h" +#include "soc/lp_clkrst_reg.h" +#include "soc/lp_clkrst_struct.h" +#include "soc/lp_i2c_reg.h" +#include "soc/lp_i2c_struct.h" +#include "soc/lp_io_reg.h" +#include "soc/lp_io_struct.h" +#include "soc/lp_timer_reg.h" +#include "soc/lp_timer_struct.h" +#include "soc/lp_uart_reg.h" +#include "soc/lp_uart_struct.h" +#include "soc/lp_wdt_reg.h" +#include "soc/lp_wdt_struct.h" +#else #include "soc/rtc_cntl_reg.h" #include "soc/rtc_cntl_struct.h" +#endif diff --git a/components/soc/include/soc/rtc_io_periph.h b/components/soc/include/soc/rtc_io_periph.h index 106d879dfb..cb4facbf76 100644 --- a/components/soc/include/soc/rtc_io_periph.h +++ b/components/soc/include/soc/rtc_io_periph.h @@ -17,9 +17,6 @@ #include "soc/rtc_io_struct.h" #endif -#include "soc/rtc_cntl_reg.h" -#include "soc/rtc_cntl_struct.h" - #if SOC_ADC_RTC_CTRL_SUPPORTED #include "soc/sens_struct.h" #endif diff --git a/components/soc/include/soc/rtc_periph.h b/components/soc/include/soc/rtc_periph.h index 433f5cc42e..15dc77846c 100644 --- a/components/soc/include/soc/rtc_periph.h +++ b/components/soc/include/soc/rtc_periph.h @@ -1,21 +1,14 @@ -// Copyright 2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once + #include #include "rtc_io_periph.h" -#include "soc/rtc_cntl_reg.h" +#include "rtc_cntl_periph.h" #include "soc/soc_caps.h" #ifdef __cplusplus diff --git a/components/soc/include/soc/spi_periph.h b/components/soc/include/soc/spi_periph.h index 5f91beb605..f127fa2687 100644 --- a/components/soc/include/soc/spi_periph.h +++ b/components/soc/include/soc/spi_periph.h @@ -60,7 +60,7 @@ typedef struct { const uint8_t spid6_in; const uint8_t spid7_in; #endif // SOC_SPI_SUPPORT_OCT - const uint8_t spics_out[3]; // /CS GPIO output mux signals + const uint8_t spics_out[SOC_SPI_MAX_CS_NUM]; // /CS GPIO output mux signals const uint8_t spics_in; const uint8_t spidqs_out; const uint8_t spicd_out; diff --git a/components/soc/include/soc/syscon_periph.h b/components/soc/include/soc/syscon_periph.h index 0179e867c7..01f12e297f 100644 --- a/components/soc/include/soc/syscon_periph.h +++ b/components/soc/include/soc/syscon_periph.h @@ -1,17 +1,13 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once + +// TODO: IDF-5721 +#if !CONFIG_IDF_TARGET_ESP32C6 #include "soc/syscon_reg.h" #include "soc/syscon_struct.h" +#endif diff --git a/components/spi_flash/CMakeLists.txt b/components/spi_flash/CMakeLists.txt index 260b353b48..7096cb57d0 100644 --- a/components/spi_flash/CMakeLists.txt +++ b/components/spi_flash/CMakeLists.txt @@ -8,7 +8,7 @@ if(${target} STREQUAL "linux") idf_component_register(SRCS "${srcs}" INCLUDE_DIRS include ${hal_dir}/include ${bootloader_support_dir}/include PRIV_INCLUDE_DIRS include/spi_flash - PRIV_REQUIRES linux partition_table) + PRIV_REQUIRES partition_table) return() endif() diff --git a/components/spi_flash/Kconfig b/components/spi_flash/Kconfig index 260c7d146b..209d6e1cd4 100644 --- a/components/spi_flash/Kconfig +++ b/components/spi_flash/Kconfig @@ -53,14 +53,9 @@ menu "SPI Flash driver" to flash on ESP32-D2WD; (2) main SPI flash is connected to non-default pins; (3) main SPI flash chip is manufactured by ISSI. - config SPI_FLASH_HAS_ROM_IMPL - bool - depends on IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 - default y if IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 - config SPI_FLASH_ROM_IMPL bool "Use esp_flash implementation in ROM" - depends on SPI_FLASH_HAS_ROM_IMPL + depends on ESP_ROM_HAS_SPI_FLASH default n help Enable this flag to use new SPI flash driver functions from ROM instead of ESP-IDF. diff --git a/components/spi_flash/cache_utils.c b/components/spi_flash/cache_utils.c index 89bb53e8fc..3b17f5e9d5 100644 --- a/components/spi_flash/cache_utils.c +++ b/components/spi_flash/cache_utils.c @@ -11,6 +11,7 @@ #include #include +#include #include #if CONFIG_IDF_TARGET_ESP32 #include "soc/dport_reg.h" @@ -35,6 +36,10 @@ #include "esp32c2/rom/cache.h" #include "soc/extmem_reg.h" #include "soc/ext_mem_defs.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/cache.h" +#include "soc/extmem_reg.h" +#include "soc/ext_mem_defs.h" #endif #include "esp_rom_spiflash.h" #include @@ -69,6 +74,14 @@ static void spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state); static uint32_t s_flash_op_cache_state[2]; +#if CONFIG_IDF_TARGET_ESP32C6 +/* esp32c6 does not has a register indicating if cache is enabled + * so we use s static data to store to state of cache, every time + * disable/restore api is called, the state will be updated + */ +static volatile DRAM_ATTR bool s_cache_enabled = 1; +#endif + #ifndef CONFIG_FREERTOS_UNICORE static SemaphoreHandle_t s_flash_op_mutex; static volatile bool s_flash_op_can_start = false; @@ -170,8 +183,9 @@ void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu(void) } else { // Temporarily raise current task priority to prevent a deadlock while // waiting for IPC task to start on the other CPU - int old_prio = uxTaskPriorityGet(NULL); - vTaskPrioritySet(NULL, configMAX_PRIORITIES - 1); + prvTaskSavedPriority_t SavedPriority; + prvTaskPriorityRaise(&SavedPriority, configMAX_PRIORITIES - 1); + // Signal to the spi_flash_op_block_task on the other CPU that we need it to // disable cache there and block other tasks from executing. s_flash_op_can_start = false; @@ -189,7 +203,7 @@ void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu(void) vTaskSuspendAll(); #endif // CONFIG_FREERTOS_SMP // Can now set the priority back to the normal one - vTaskPrioritySet(NULL, old_prio); + prvTaskPriorityRestore(&SavedPriority); // This is guaranteed to run on CPU because the other CPU is now // occupied by highest priority task assert(xPortGetCoreID() == cpuid); @@ -370,6 +384,11 @@ static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_st uint32_t icache_state; icache_state = Cache_Suspend_ICache() << 16; *saved_state = icache_state; +#elif CONFIG_IDF_TARGET_ESP32C6 + uint32_t icache_state; + icache_state = Cache_Suspend_ICache(); + *saved_state = icache_state; + s_cache_enabled = 0; #endif } @@ -394,6 +413,9 @@ static void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_sta Cache_Resume_ICache(saved_state >> 16); #elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 Cache_Resume_ICache(saved_state >> 16); +#elif CONFIG_IDF_TARGET_ESP32C6 + Cache_Resume_ICache(saved_state); + s_cache_enabled = 1; #endif } @@ -408,6 +430,8 @@ IRAM_ATTR bool spi_flash_cache_enabled(void) bool result = (REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_ENABLE) != 0); #elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 bool result = (REG_GET_BIT(EXTMEM_ICACHE_CTRL_REG, EXTMEM_ICACHE_ENABLE) != 0); +#elif CONFIG_IDF_TARGET_ESP32C6 + bool result = s_cache_enabled; #endif return result; } @@ -521,7 +545,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable int i; bool flash_spiram_wrap_together, flash_support_wrap = true, spiram_support_wrap = true; uint32_t drom0_in_icache = 1;//always 1 in esp32s2 -#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 +#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 drom0_in_icache = 0; #endif @@ -910,7 +934,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable } #endif -#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 static IRAM_ATTR void esp_enable_cache_flash_wrap(bool icache) { @@ -952,7 +976,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable) } return ESP_OK; } -#endif // CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 +#endif // CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 void IRAM_ATTR spi_flash_enable_cache(uint32_t cpuid) { diff --git a/components/spi_flash/esp32c6/flash_ops_esp32c6.c b/components/spi_flash/esp32c6/flash_ops_esp32c6.c new file mode 100644 index 0000000000..98bca81ae0 --- /dev/null +++ b/components/spi_flash/esp32c6/flash_ops_esp32c6.c @@ -0,0 +1,91 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include "spi_flash_mmap.h" +#include "soc/soc_memory_layout.h" +#include "esp32c6/rom/cache.h" +#include "hal/spi_flash_hal.h" +#include "esp_flash.h" +#include "esp_log.h" +#include "esp_attr.h" +#include "esp_rom_spiflash.h" +#include "esp_private/spi_flash_os.h" + +#define SPICACHE SPIMEM0 +#define SPIFLASH SPIMEM1 + +#define FLASH_WRAP_CMD 0x77 +esp_err_t spi_flash_wrap_set(spi_flash_wrap_mode_t mode) +{ + uint32_t reg_bkp_ctrl = SPIFLASH.ctrl.val; + uint32_t reg_bkp_usr = SPIFLASH.user.val; + SPIFLASH.user.fwrite_dio = 0; + SPIFLASH.user.fwrite_dual = 0; + SPIFLASH.user.fwrite_qio = 1; + SPIFLASH.user.fwrite_quad = 0; + // SPIFLASH.ctrl.fcmd_dual = 0; // TODO: IDF-5333 + SPIFLASH.ctrl.fcmd_quad = 0; + SPIFLASH.user.usr_dummy = 0; + SPIFLASH.user.usr_addr = 1; + SPIFLASH.user.usr_command = 1; + SPIFLASH.user2.usr_command_bitlen = 7; + SPIFLASH.user2.usr_command_value = FLASH_WRAP_CMD; + SPIFLASH.user1.usr_addr_bitlen = 23; + SPIFLASH.addr = 0; + SPIFLASH.user.usr_miso = 0; + SPIFLASH.user.usr_mosi = 1; + SPIFLASH.mosi_dlen.usr_mosi_bit_len = 7; + SPIFLASH.data_buf[0] = (uint32_t) mode << 4;; + SPIFLASH.cmd.usr = 1; + while (SPIFLASH.cmd.usr != 0) + { } + + SPIFLASH.ctrl.val = reg_bkp_ctrl; + SPIFLASH.user.val = reg_bkp_usr; + return ESP_OK; +} + +esp_err_t spi_flash_enable_wrap(uint32_t wrap_size) +{ + CLEAR_PERI_REG_MASK(SPI_MEM_CTRL2_REG(0), SPI_MEM_SPLIT_TRANS_EN_M); // TODO: IDF-5333 Newly added + switch (wrap_size) { + case 8: + return spi_flash_wrap_set(FLASH_WRAP_MODE_8B); + case 16: + return spi_flash_wrap_set(FLASH_WRAP_MODE_16B); + case 32: + return spi_flash_wrap_set(FLASH_WRAP_MODE_32B); + case 64: + return spi_flash_wrap_set(FLASH_WRAP_MODE_64B); + default: + return ESP_FAIL; + } +} + +void spi_flash_disable_wrap(void) +{ + spi_flash_wrap_set(FLASH_WRAP_MODE_DISABLE); +} + +bool spi_flash_support_wrap_size(uint32_t wrap_size) +{ + if (!REG_GET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FREAD_QIO) || !REG_GET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FASTRD_MODE)) { + return ESP_FAIL; + } + switch (wrap_size) { + case 0: + case 8: + case 16: + case 32: + case 64: + return true; + default: + return false; + } +} diff --git a/components/spi_flash/esp_flash_spi_init.c b/components/spi_flash/esp_flash_spi_init.c index 23ec3763fd..4b946737cb 100644 --- a/components/spi_flash/esp_flash_spi_init.c +++ b/components/spi_flash/esp_flash_spi_init.c @@ -104,7 +104,7 @@ esp_flash_t *esp_flash_default_chip = NULL; .input_delay_ns = 0,\ .cs_setup = 1,\ } -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 #if !CONFIG_SPI_FLASH_AUTO_SUSPEND #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \ .host_id = SPI1_HOST,\ @@ -332,7 +332,7 @@ esp_err_t esp_flash_init_default_chip(void) const esp_rom_spiflash_chip_t *legacy_chip = &g_rom_flashchip; memspi_host_config_t cfg = ESP_FLASH_HOST_CONFIG_DEFAULT(); - #if !CONFIG_IDF_TARGET_ESP32 && !CONFIG_IDF_TARGET_ESP32C2 + #if !CONFIG_IDF_TARGET_ESP32 && !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6 // For esp32s2 spi IOs are configured as from IO MUX by default cfg.iomux = esp_rom_efuse_get_flash_gpio_info() == 0 ? true : false; #endif diff --git a/components/spi_flash/flash_mmap.c b/components/spi_flash/flash_mmap.c index fd4a5e17e5..daed070fa8 100644 --- a/components/spi_flash/flash_mmap.c +++ b/components/spi_flash/flash_mmap.c @@ -38,11 +38,13 @@ #include "esp32h2/rom/cache.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/cache.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/cache.h" #endif #if CONFIG_SPIRAM #include "esp_private/esp_psram_extram.h" -#include "esp_private/mmu.h" +#include "esp_private/mmu_psram_flash.h" #endif #ifndef NDEBUG diff --git a/components/spi_flash/flash_ops.c b/components/spi_flash/flash_ops.c index c4a203abed..e17c8b3aab 100644 --- a/components/spi_flash/flash_ops.c +++ b/components/spi_flash/flash_ops.c @@ -40,6 +40,8 @@ #include "esp32h2/rom/cache.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/cache.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/cache.h" #endif #include "esp_rom_spiflash.h" #include "esp_flash_partitions.h" diff --git a/components/spi_flash/host_test/partition_api_test/CMakeLists.txt b/components/spi_flash/host_test/partition_api_test/CMakeLists.txt index 469a614a14..3986bdb314 100644 --- a/components/spi_flash/host_test/partition_api_test/CMakeLists.txt +++ b/components/spi_flash/host_test/partition_api_test/CMakeLists.txt @@ -7,3 +7,5 @@ set(COMPONENTS main) list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/mocks/freertos/") project(partition_api_test) + +add_dependencies(partition_api_test.elf partition-table) diff --git a/components/spi_flash/host_test/partition_api_test/main/CMakeLists.txt b/components/spi_flash/host_test/partition_api_test/main/CMakeLists.txt index 408a6111e1..a43dde98bf 100644 --- a/components/spi_flash/host_test/partition_api_test/main/CMakeLists.txt +++ b/components/spi_flash/host_test/partition_api_test/main/CMakeLists.txt @@ -1,2 +1,2 @@ -idf_component_register(SRCS "partition_api_test.cpp" - REQUIRES spi_flash) +idf_component_register(SRCS "partition_api_test.c" + REQUIRES spi_flash unity) diff --git a/components/spi_flash/host_test/partition_api_test/main/partition_api_test.cpp b/components/spi_flash/host_test/partition_api_test/main/partition_api_test.c similarity index 55% rename from components/spi_flash/host_test/partition_api_test/main/partition_api_test.cpp rename to components/spi_flash/host_test/partition_api_test/main/partition_api_test.c index 4ee8849496..a4d5278c0a 100644 --- a/components/spi_flash/host_test/partition_api_test/main/partition_api_test.cpp +++ b/components/spi_flash/host_test/partition_api_test/main/partition_api_test.c @@ -10,64 +10,74 @@ #include "esp_err.h" #include "esp_partition.h" #include "esp_private/partition_linux.h" +#include "unity.h" +#include "unity_fixture.h" -int main(int argc, char **argv) + +TEST_GROUP(partition_api); + +TEST_SETUP(partition_api) { - printf("Partition API Linux emulation test: "); +} - //////////////////////////////////////// - //PARTITION LOOKUP: +TEST_TEAR_DOWN(partition_api) +{ +} - //1. esp_partition_find (label=STORAGE) +TEST(partition_api, test_partition_find_basic) +{ esp_partition_iterator_t iter = esp_partition_find(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, "storage"); - assert(iter); + TEST_ASSERT_NOT_NULL(iter); - //2. esp_partition_get (label=STORAGE) const esp_partition_t *part = esp_partition_get(iter); - assert(part); + TEST_ASSERT_NOT_NULL(part); - //3. esp_partition_iterator_release (label STORAGE iter): assumed OK esp_partition_iterator_release(iter); +} - //////////////////////////////////////// - //ITERATORS, PARTITION PROPERTIES: - - //4. esp_partition_find_first (type=APP, subtype=ANY) - const esp_partition_t *partition_app = esp_partition_find_first(ESP_PARTITION_TYPE_APP, ESP_PARTITION_SUBTYPE_ANY, NULL); - assert(partition_app); - - //5. enumerate all APP partitions - iter = esp_partition_find(ESP_PARTITION_TYPE_APP, ESP_PARTITION_SUBTYPE_ANY, NULL); - assert(iter); +TEST(partition_api, test_partition_find_app) +{ + esp_partition_iterator_t iter = esp_partition_find(ESP_PARTITION_TYPE_APP, ESP_PARTITION_SUBTYPE_ANY, NULL); + TEST_ASSERT_NOT_NULL(iter); size_t counter = 0; while (iter != NULL) { const esp_partition_t *part_data = esp_partition_get(iter); counter++; - assert(part_data); + TEST_ASSERT_NOT_NULL(part_data); iter = esp_partition_next(iter); } esp_partition_iterator_release(iter); +} - //6. enumerate all DATA partitions and print details for each - iter = esp_partition_find(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, NULL); - assert(iter); - counter = 0; +TEST(partition_api, test_partition_find_data) +{ + esp_partition_iterator_t iter = esp_partition_find(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, NULL); + TEST_ASSERT_NOT_NULL(iter); + size_t counter = 0; while (iter != NULL) { const esp_partition_t *part_data = esp_partition_get(iter); counter++; - assert(part_data); + TEST_ASSERT_NOT_NULL(part_data); iter = esp_partition_next(iter); } esp_partition_iterator_release(iter); +} + +TEST(partition_api, test_partition_find_first) +{ + const esp_partition_t *partition_app = esp_partition_find_first(ESP_PARTITION_TYPE_APP, ESP_PARTITION_SUBTYPE_ANY, NULL); + TEST_ASSERT_NOT_NULL(partition_app); - //7. esp_partition_find_first (type=DATA, label=STORAGE) const esp_partition_t *partition_data = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, "storage"); - assert(partition_data); + TEST_ASSERT_NOT_NULL(partition_data); +} - ///////////////////////////////////// - //OPERATIONS +TEST(partition_api, test_partition_ops) +{ + const esp_partition_t *partition_data = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, "storage"); + TEST_ASSERT_NOT_NULL(partition_data); uint8_t buff[] = "ABCDEFGHIJKLMNOP"; size_t bufsize = sizeof(buff); @@ -75,12 +85,12 @@ int main(int argc, char **argv) //8. esp_partition_write/raw esp_err_t err = esp_partition_write(partition_data, off, (const void *)buff, bufsize); - assert(err == ESP_OK); + TEST_ESP_OK(err); //9. esp_partition_read/raw uint8_t buffout[32] = {0}; err = esp_partition_read(partition_data, off, (void *)buffout, bufsize); - assert(err == ESP_OK); + TEST_ESP_OK(err); //10. esp_partition_erase_range uint8_t buferase[bufsize]; @@ -90,17 +100,30 @@ int main(int argc, char **argv) err = esp_partition_erase_range(partition_data, sector_off, SPI_FLASH_SEC_SIZE); assert(esp_partition_read(partition_data, off, (void *)buffout, bufsize) == ESP_OK); - assert(err == ESP_OK && memcmp(buffout, buferase, bufsize) == 0); + TEST_ESP_OK(err); + TEST_ASSERT_EQUAL(0, memcmp(buffout, buferase, bufsize)); //11. esp_partition_verify (partition_data) const esp_partition_t *verified_partition = esp_partition_verify(partition_data); - assert(verified_partition != NULL); + TEST_ASSERT_NOT_NULL(verified_partition); +} - //12. release SPI FLASH emulation block from memory - err = esp_partition_file_munmap(); - assert(err == ESP_OK); +TEST_GROUP_RUNNER(partition_api) +{ + RUN_TEST_CASE(partition_api, test_partition_find_basic); + RUN_TEST_CASE(partition_api, test_partition_find_app); + RUN_TEST_CASE(partition_api, test_partition_find_data); + RUN_TEST_CASE(partition_api, test_partition_find_first); + RUN_TEST_CASE(partition_api, test_partition_ops); +} - printf("OK\n"); +static void run_all_tests(void) +{ + RUN_TEST_GROUP(partition_api); +} +int main(int argc, char **argv) +{ + UNITY_MAIN_FUNC(run_all_tests); return 0; } diff --git a/components/spi_flash/host_test/partition_api_test/sdkconfig.defaults b/components/spi_flash/host_test/partition_api_test/sdkconfig.defaults index 47666febd9..275e768c6c 100644 --- a/components/spi_flash/host_test/partition_api_test/sdkconfig.defaults +++ b/components/spi_flash/host_test/partition_api_test/sdkconfig.defaults @@ -1,6 +1,7 @@ CONFIG_IDF_TARGET="linux" CONFIG_COMPILER_CXX_EXCEPTIONS=y CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=n +CONFIG_UNITY_ENABLE_FIXTURE=y CONFIG_PARTITION_TABLE_CUSTOM=y CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partition_table.csv" CONFIG_ESPTOOLPY_FLASHSIZE="4MB" diff --git a/components/spi_flash/include/spi_flash_override.h b/components/spi_flash/include/spi_flash_override.h index 5e763c9bca..7f01576dee 100644 --- a/components/spi_flash/include/spi_flash_override.h +++ b/components/spi_flash/include/spi_flash_override.h @@ -29,6 +29,7 @@ typedef struct { typedef enum { SPI_FLASH_HPM_CMD_NEEDED, // Means that in the certain condition, flash needs to enter the high performance mode by command. SPI_FLASH_HPM_DUMMY_NEEDED, // Means that in the certain condition, flash needs to enter the high performance mode by adjusting dummy. + SPI_FLASH_HPM_WRITE_SR_NEEDED, // Means that in the certain condition, flash needs to enter the high performance mode by writing status register. SPI_FLASH_HPM_UNNEEDED, // Means that flash doesn't need to enter the high performance mode. SPI_FLASH_HPM_BEYOND_LIMIT, // Means that flash has no capability to meet that condition. } spi_flash_requirement_t; @@ -41,7 +42,7 @@ typedef spi_flash_requirement_t (*spi_flash_hpm_chip_requirement_check_t)(uint32 typedef struct __attribute__((packed)) { - const char *manufacturer; /* Flash vendor */ + const char *method; /* Flash HPM method */ spi_flash_hpm_probe_fn_t probe; spi_flash_hpm_chip_requirement_check_t chip_hpm_requirement_check; spi_flash_hpm_enable_fn_t flash_hpm_enable; diff --git a/components/spi_flash/partition.c b/components/spi_flash/partition.c index 1ff38261aa..a161c484e5 100644 --- a/components/spi_flash/partition.c +++ b/components/spi_flash/partition.c @@ -30,6 +30,13 @@ #include "esp_private/partition_linux.h" #endif +#ifndef CONFIG_IDF_TARGET_LINUX +#define MMU_PAGE_SIZE CONFIG_MMU_PAGE_SIZE +#else +// No relation to the page size on Linux; assume the same value as on ESP32 +#define MMU_PAGE_SIZE 65536 +#endif // CONFIG_MMU_PAGE_SIZE + #ifndef NDEBUG // Enable built-in checks in queue.h in debug builds #define INVARIANTS @@ -78,7 +85,7 @@ static esp_err_t load_partitions(void) esp_rom_md5_init(&context); #endif - uint32_t partition_align_pg_size = (ESP_PARTITION_TABLE_OFFSET) & ~(CONFIG_MMU_PAGE_SIZE - 1); + uint32_t partition_align_pg_size = (ESP_PARTITION_TABLE_OFFSET) & ~(MMU_PAGE_SIZE - 1); uint32_t partition_pad = ESP_PARTITION_TABLE_OFFSET - partition_align_pg_size; #if CONFIG_IDF_TARGET_LINUX diff --git a/components/spi_flash/sim/Makefile.files b/components/spi_flash/sim/Makefile.files index 8f360aed14..186fce56d3 100644 --- a/components/spi_flash/sim/Makefile.files +++ b/components/spi_flash/sim/Makefile.files @@ -18,6 +18,7 @@ INCLUDE_DIRS := \ app_update/include \ bsd/include \ driver/include \ + esp_app_format/include \ esp_timer/include \ freertos/include \ log/include \ @@ -34,7 +35,7 @@ INCLUDE_DIRS := \ xtensa/include \ xtensa/esp32/include \ soc/esp32/include \ - heap/include \ + heap/include \ soc/include \ esp32/include \ esp_timer/include \ diff --git a/components/spi_flash/sim/stubs/Makefile.files b/components/spi_flash/sim/stubs/Makefile.files index dd6591666d..b2f789c39b 100644 --- a/components/spi_flash/sim/stubs/Makefile.files +++ b/components/spi_flash/sim/stubs/Makefile.files @@ -14,6 +14,7 @@ INCLUDE_DIRS := \ app_update/include \ bsd/include \ driver/include \ + esp_app_format/include \ esp_timer/include \ freertos/include \ log/include \ @@ -26,7 +27,7 @@ INCLUDE_DIRS := \ esp_hw_support/include/soc \ esp_system/include \ soc/esp32/include \ - heap/include \ + heap/include \ soc/include \ xtensa/include \ xtensa/esp32/include \ diff --git a/components/spi_flash/sim/stubs/esp_app_format/include/esp_app_desc.h b/components/spi_flash/sim/stubs/esp_app_format/include/esp_app_desc.h new file mode 100644 index 0000000000..70c698c185 --- /dev/null +++ b/components/spi_flash/sim/stubs/esp_app_format/include/esp_app_desc.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + * + * This is a STUB FILE used when compiling ESP-IDF to run tests on the host system. + * The source file used normally for ESP-IDF has the same name but is located elsewhere. + */ + +#pragma once + +#include +#include +#include +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define ESP_APP_DESC_MAGIC_WORD (0xABCD5432) /*!< The magic word for the esp_app_desc structure that is in DROM. */ + +/** + * @brief Description about application. + */ +typedef struct { + uint32_t magic_word; /*!< Magic word ESP_APP_DESC_MAGIC_WORD */ + uint32_t secure_version; /*!< Secure version */ + uint32_t reserv1[2]; /*!< reserv1 */ + char version[32]; /*!< Application version */ + char project_name[32]; /*!< Project name */ + char time[16]; /*!< Compile time */ + char date[16]; /*!< Compile date*/ + char idf_ver[32]; /*!< Version IDF */ + uint8_t app_elf_sha256[32]; /*!< sha256 of elf file */ + uint32_t reserv2[20]; /*!< reserv2 */ +} esp_app_desc_t; + +/** @cond */ +_Static_assert(sizeof(esp_app_desc_t) == 256, "esp_app_desc_t should be 256 bytes"); +/** @endcond */ + +#ifdef __cplusplus +} +#endif diff --git a/components/spi_flash/spi_flash_hpm_enable.c b/components/spi_flash/spi_flash_hpm_enable.c index 9c808c1cff..81659a2e03 100644 --- a/components/spi_flash/spi_flash_hpm_enable.c +++ b/components/spi_flash/spi_flash_hpm_enable.c @@ -48,6 +48,8 @@ extern uint32_t bootloader_flash_execute_command_common( uint8_t mosi_len, uint32_t mosi_data, uint8_t miso_len); +extern uint32_t IRAM_ATTR bootloader_flash_read_sfdp(uint32_t sfdp_addr, unsigned int miso_byte_num); + //-----------------For flash chips which enter HPM via command-----------------------// /** @@ -61,7 +63,14 @@ static esp_err_t spi_flash_hpm_probe_chip_with_cmd(uint32_t flash_id) /* The flash listed here should enter the HPM with command 0xA3 */ case 0xC84016: case 0xC84017: - break; + // Read BYTE4 in SFDP, 0 means C series, 6 means E series + uint32_t gd_sfdp = bootloader_flash_read_sfdp(0x4, 1); + if (gd_sfdp == 0x0) { + break; + } else { + ret = ESP_ERR_NOT_FOUND; + break; + } default: ret = ESP_ERR_NOT_FOUND; break; @@ -75,18 +84,10 @@ static spi_flash_requirement_t spi_flash_hpm_chip_hpm_requirement_check_with_cmd (void)voltage_mv; (void)temperautre; spi_flash_requirement_t chip_cap = SPI_FLASH_HPM_UNNEEDED; - switch (flash_id) { - /* The flash listed here should enter the HPM with command 0xA3 */ - case 0xC84016: - case 0xC84017: - if (freq_mhz > 80) { - chip_cap = SPI_FLASH_HPM_CMD_NEEDED; - } - break; - default: - chip_cap = SPI_FLASH_HPM_UNNEEDED; - break; + if (freq_mhz > 80) { + chip_cap = SPI_FLASH_HPM_CMD_NEEDED; } + ESP_EARLY_LOGD(HPM_TAG, "HPM with command, status is %d", chip_cap); return chip_cap; } @@ -130,6 +131,17 @@ static esp_err_t spi_flash_hpm_probe_chip_with_dummy(uint32_t flash_id) case 0x204017: case 0x204018: break; + // GD chips. + case 0xC84017: + case 0xC84018: + // Read BYTE4 in SFDP, 0 means C series, 6 means E series + uint32_t gd_sfdp = bootloader_flash_read_sfdp(0x4, 1); + if (gd_sfdp == 0x6) { + break; + } else { + ret = ESP_ERR_NOT_FOUND; + break; + } default: ret = ESP_ERR_NOT_FOUND; break; @@ -143,18 +155,11 @@ static spi_flash_requirement_t spi_flash_hpm_chip_hpm_requirement_check_with_dum (void)voltage_mv; (void)temperautre; spi_flash_requirement_t chip_cap = SPI_FLASH_HPM_UNNEEDED; - switch (flash_id) { - /* The flash listed here should enter the HPM with command 0xA3 */ - case 0x204017: - case 0x204018: - if (freq_mhz >= 104) { - chip_cap = SPI_FLASH_HPM_DUMMY_NEEDED; - } - break; - default: - chip_cap = SPI_FLASH_HPM_UNNEEDED; - break; + + if (freq_mhz >= 104) { + chip_cap = SPI_FLASH_HPM_DUMMY_NEEDED; } + ESP_EARLY_LOGD(HPM_TAG, "HPM with dummy, status is %d", chip_cap); return chip_cap; } @@ -194,6 +199,53 @@ static void spi_flash_hpm_get_dummy_xmc(spi_flash_hpm_dummy_conf_t *dummy_conf) dummy_conf->fastrd_dummy = SPI_FLASH_FASTRD_DUMMY_BITLEN; } +//-----------------For flash chips which enter HPM via write status register-----------------------// + +/** + * @brief Probe the chip whether to write status register to enable HPM mode. Take ZB as an example: + * Write status register bits to enable HPM mode of the flash. If ZB works under 80MHz, the register value + * would be 0, but when works under 120MHz, the register value would be 1. + */ +static esp_err_t spi_flash_hpm_probe_chip_with_write_hpf_bit_5(uint32_t flash_id) +{ + esp_err_t ret = ESP_OK; + switch (flash_id) { + /* The flash listed here should enter the HPM by adjusting dummy cycles */ + // ZB chips. + case 0x5E4016: + break; + default: + ret = ESP_ERR_NOT_FOUND; + break; + } + return ret; +} + +static spi_flash_requirement_t spi_flash_hpm_chip_hpm_requirement_check_with_write_hpf_bit_5(uint32_t flash_id, uint32_t freq_mhz, int voltage_mv, int temperautre) +{ + // voltage and temperature are not been used now, to be completed in the future. + (void)voltage_mv; + (void)temperautre; + spi_flash_requirement_t chip_cap = SPI_FLASH_HPM_UNNEEDED; + + if (freq_mhz >= 104) { + chip_cap = SPI_FLASH_HPM_WRITE_SR_NEEDED; + } + ESP_EARLY_LOGD(HPM_TAG, "HPM with dummy, status is %d", chip_cap); + return chip_cap; +} + +/** + * @brief Write bit 5 in status 3 + */ +static void spi_flash_turn_high_performance_write_hpf_bit_5(void) +{ + uint8_t old_status_3 = bootloader_read_status_8b_rdsr3(); + uint8_t new_status = (old_status_3 | 0x10); + bootloader_execute_flash_command(CMD_WRENVSR, 0, 0, 0); + bootloader_write_status_8b_wrsr3(new_status); + esp_rom_spiflash_wait_idle(&g_rom_flashchip); +} //-----------------------generic functions-------------------------------------// @@ -212,8 +264,9 @@ void __attribute__((weak)) spi_flash_hpm_get_dummy_generic(spi_flash_hpm_dummy_c const spi_flash_hpm_info_t __attribute__((weak)) spi_flash_hpm_enable_list[] = { /* vendor, chip_id, freq_threshold, temperature threshold, operation for setting high performance, reading HPF status, get dummy */ - { "GD", spi_flash_hpm_probe_chip_with_cmd, spi_flash_hpm_chip_hpm_requirement_check_with_cmd, spi_flash_enable_high_performance_send_cmd, spi_flash_high_performance_check_hpf_bit_5, spi_flash_hpm_get_dummy_generic }, - { "XMC", spi_flash_hpm_probe_chip_with_dummy, spi_flash_hpm_chip_hpm_requirement_check_with_dummy, spi_flash_turn_high_performance_reconfig_dummy, spi_flash_high_performance_check_dummy_sr, spi_flash_hpm_get_dummy_xmc}, + { "command", spi_flash_hpm_probe_chip_with_cmd, spi_flash_hpm_chip_hpm_requirement_check_with_cmd, spi_flash_enable_high_performance_send_cmd, spi_flash_high_performance_check_hpf_bit_5, spi_flash_hpm_get_dummy_generic }, + { "dummy", spi_flash_hpm_probe_chip_with_dummy, spi_flash_hpm_chip_hpm_requirement_check_with_dummy, spi_flash_turn_high_performance_reconfig_dummy, spi_flash_high_performance_check_dummy_sr, spi_flash_hpm_get_dummy_xmc}, + { "write sr3-bit5", spi_flash_hpm_probe_chip_with_write_hpf_bit_5, spi_flash_hpm_chip_hpm_requirement_check_with_write_hpf_bit_5, spi_flash_turn_high_performance_write_hpf_bit_5, spi_flash_high_performance_check_hpf_bit_5, spi_flash_hpm_get_dummy_generic}, // default: do nothing, but keep the dummy get function. The first item with NULL as its probe will be the fallback. { "NULL", NULL, NULL, NULL, NULL, spi_flash_hpm_get_dummy_generic}, }; @@ -250,8 +303,8 @@ esp_err_t spi_flash_enable_high_performance_mode(void) } hpm_requirement_check = chip_hpm->chip_hpm_requirement_check(flash_chip_id, flash_freq, voltage, temperature); - if ((hpm_requirement_check == SPI_FLASH_HPM_CMD_NEEDED) || (hpm_requirement_check == SPI_FLASH_HPM_DUMMY_NEEDED)) { - ESP_EARLY_LOGI(HPM_TAG, "Enabling high speed mode for chip %s", chip_hpm->manufacturer); + if ((hpm_requirement_check == SPI_FLASH_HPM_CMD_NEEDED) || (hpm_requirement_check == SPI_FLASH_HPM_DUMMY_NEEDED) || (hpm_requirement_check == SPI_FLASH_HPM_WRITE_SR_NEEDED)) { + ESP_EARLY_LOGI(HPM_TAG, "Enabling flash high speed mode by %s", chip_hpm->method); chip_hpm->flash_hpm_enable(); ESP_EARLY_LOGD(HPM_TAG, "Checking whether HPM has been executed"); diff --git a/components/spi_flash/spi_flash_os_func_app.c b/components/spi_flash/spi_flash_os_func_app.c index 75824da138..f9fc95fdc2 100644 --- a/components/spi_flash/spi_flash_os_func_app.c +++ b/components/spi_flash/spi_flash_os_func_app.c @@ -22,6 +22,7 @@ #include "esp_private/spi_common_internal.h" +#define SPI_FLASH_CACHE_NO_DISABLE (CONFIG_SPI_FLASH_AUTO_SUSPEND || (CONFIG_SPIRAM_FETCH_INSTRUCTIONS && CONFIG_SPIRAM_RODATA)) static const char TAG[] = "spi_flash"; /* @@ -60,14 +61,14 @@ static inline bool on_spi1_check_yield(spi1_app_func_arg_t* ctx); IRAM_ATTR static void cache_enable(void* arg) { -#ifndef CONFIG_SPI_FLASH_AUTO_SUSPEND +#if !SPI_FLASH_CACHE_NO_DISABLE spi_flash_enable_interrupts_caches_and_other_cpu(); #endif } IRAM_ATTR static void cache_disable(void* arg) { -#ifndef CONFIG_SPI_FLASH_AUTO_SUSPEND +#if !SPI_FLASH_CACHE_NO_DISABLE spi_flash_disable_interrupts_caches_and_other_cpu(); #endif } diff --git a/components/spi_flash/spi_flash_os_func_noos.c b/components/spi_flash/spi_flash_os_func_noos.c index f1ce890d3d..c0e15d12e8 100644 --- a/components/spi_flash/spi_flash_os_func_noos.c +++ b/components/spi_flash/spi_flash_os_func_noos.c @@ -26,6 +26,9 @@ #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/ets_sys.h" #include "esp32c2/rom/cache.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/ets_sys.h" +#include "esp32c6/rom/cache.h" #endif #include "esp_attr.h" @@ -37,7 +40,7 @@ typedef struct { } spi_noos_arg_t; static DRAM_ATTR spi_noos_arg_t spi_arg = { 0 }; -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 typedef struct { uint32_t icache_autoload; } spi_noos_arg_t; @@ -54,7 +57,7 @@ static IRAM_ATTR esp_err_t start(void *arg) spi_noos_arg_t *spi_arg = arg; spi_arg->icache_autoload = Cache_Suspend_ICache(); spi_arg->dcache_autoload = Cache_Suspend_DCache(); -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 spi_noos_arg_t *spi_arg = arg; spi_arg->icache_autoload = Cache_Suspend_ICache(); #endif @@ -73,7 +76,7 @@ static IRAM_ATTR esp_err_t end(void *arg) Cache_Invalidate_ICache_All(); Cache_Resume_ICache(spi_arg->icache_autoload); Cache_Resume_DCache(spi_arg->dcache_autoload); -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 spi_noos_arg_t *spi_arg = arg; Cache_Invalidate_ICache_All(); Cache_Resume_ICache(spi_arg->icache_autoload); diff --git a/components/spi_flash/test/test_esp_flash.c b/components/spi_flash/test/test_esp_flash.c index 5e11e1d9dc..52ac167001 100644 --- a/components/spi_flash/test/test_esp_flash.c +++ b/components/spi_flash/test/test_esp_flash.c @@ -12,6 +12,7 @@ #include #include "esp_log.h" + #include #include "unity.h" @@ -38,8 +39,6 @@ #define FUNC_SPI 1 -static uint8_t sector_buf[4096]; - #define MAX_ADDR_24BIT 0x1000000 #define TEST_SPI_SPEED 10 #define TEST_SPI_READ_MODE SPI_FLASH_FASTRD @@ -146,9 +145,6 @@ typedef void (*flash_test_func_t)(const esp_partition_t *part); #if defined(CONFIG_SPIRAM) //SPI1 CS1 occupied by PSRAM #define BYPASS_MULTIPLE_CHIP 1 -#elif TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) -//IDF-5049 -#define BYPASS_MULTIPLE_CHIP 1 #endif #if CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 @@ -167,15 +163,15 @@ typedef void (*flash_test_func_t)(const esp_partition_t *part); #else #if CONFIG_FREERTOS_SMP // IDF-5260 #define TEST_CASE_MULTI_FLASH(STR, FUNC_TO_RUN) \ - TEST_CASE(STR", "TEST_CHIP_NUM_STR" chips", "[esp_flash_3][test_env=UT_T1_ESP_FLASH][timeout=60]") {flash_test_func(FUNC_TO_RUN, TEST_CONFIG_NUM);} + TEST_CASE(STR", "TEST_CHIP_NUM_STR" chips", "[esp_flash_multi][test_env=UT_T1_ESP_FLASH][timeout=60]") {flash_test_func(FUNC_TO_RUN, TEST_CONFIG_NUM);} #else #define TEST_CASE_MULTI_FLASH(STR, FUNC_TO_RUN) \ - TEST_CASE(STR", "TEST_CHIP_NUM_STR" chips", "[esp_flash_3][test_env=UT_T1_ESP_FLASH][timeout=35]") {flash_test_func(FUNC_TO_RUN, TEST_CONFIG_NUM);} + TEST_CASE(STR", "TEST_CHIP_NUM_STR" chips", "[esp_flash_multi][test_env=UT_T1_ESP_FLASH][timeout=35]") {flash_test_func(FUNC_TO_RUN, TEST_CONFIG_NUM);} #endif #endif #define TEST_CASE_MULTI_FLASH_IGNORE(STR, FUNC_TO_RUN) \ - TEST_CASE(STR", "TEST_CHIP_NUM_STR" chips", "[esp_flash_3][test_env=UT_T1_ESP_FLASH][ignore]") {flash_test_func(FUNC_TO_RUN, TEST_CONFIG_NUM);} + TEST_CASE(STR", "TEST_CHIP_NUM_STR" chips", "[esp_flash_multi][test_env=UT_T1_ESP_FLASH][ignore]") {flash_test_func(FUNC_TO_RUN, TEST_CONFIG_NUM);} //currently all the configs are the same with esp_flash_spi_device_config_t, no more information required @@ -467,550 +463,12 @@ static void flash_test_func(flash_test_func_t func, int test_num) ESP_LOGI(TAG, "Completed %d configs", test_num); } -/* ---------- Test code start ------------*/ - -static void test_metadata(const esp_partition_t* part) -{ - esp_flash_t* chip = part->flash_chip; - uint32_t id, size; - TEST_ESP_OK(esp_flash_read_id(chip, &id)); - TEST_ESP_OK(esp_flash_get_size(chip, &size)); - printf("Flash ID %08x detected size %d bytes\n", id, size); -} - -TEST_CASE_FLASH("SPI flash metadata functions", test_metadata); -TEST_CASE_MULTI_FLASH("SPI flash metadata functions", test_metadata); - -static uint32_t erase_test_region(const esp_partition_t *part, int num_sectors) -{ - esp_flash_t* chip = part->flash_chip; - uint32_t offs = part->address; - - /* chip should be initialised */ - TEST_ASSERT(esp_flash_default_chip != NULL - && esp_flash_chip_driver_initialized(esp_flash_default_chip)); - - TEST_ASSERT(num_sectors * 4096 <= part->size); - - bzero(sector_buf, sizeof(sector_buf)); - - printf("Erase @ 0x%x...\n", offs); - TEST_ASSERT_EQUAL_HEX32(ESP_OK, esp_flash_erase_region(chip, offs, num_sectors * 4096) ); - - printf("Verify erased...\n"); - for (int i = 0; i < num_sectors; i++) { - TEST_ASSERT_EQUAL_HEX32(ESP_OK, esp_flash_read(chip, sector_buf, offs + i * 4096, sizeof(sector_buf))); - - printf("Buffer starts 0x%02x 0x%02x 0x%02x 0x%02x\n", sector_buf[0], sector_buf[1], sector_buf[2], sector_buf[3]); - for (int i = 0; i < sizeof(sector_buf); i++) { - TEST_ASSERT_EQUAL_HEX8(0xFF, sector_buf[i]); - } - } - - return offs; -} - -void test_simple_read_write(const esp_partition_t* part) -{ - esp_flash_t* chip = part->flash_chip; - uint32_t offs = erase_test_region(part, 1); - - const int test_seed = 778; - srand(test_seed); - for (int i = 0 ; i < sizeof(sector_buf); i++) { - sector_buf[i] = rand(); - } - - printf("Write %p...\n", (void *)offs); - TEST_ASSERT_EQUAL(ESP_OK, esp_flash_write(chip, sector_buf, offs, sizeof(sector_buf)) ); - - bzero(sector_buf, sizeof(sector_buf)); - - printf("Read back...\n"); - TEST_ASSERT_EQUAL(ESP_OK, esp_flash_read(chip, sector_buf, offs, sizeof(sector_buf)) ); - - printf("Buffer starts 0x%02x 0x%02x 0x%02x 0x%02x\n", sector_buf[0], sector_buf[1], sector_buf[2], sector_buf[3]); - - srand(test_seed); - for (int i = 0; i < sizeof(sector_buf); i++) { - uint8_t data = rand(); - TEST_ASSERT_EQUAL_HEX8(data, sector_buf[i]); - } -} - -TEST_CASE_FLASH("SPI flash simple read/write", test_simple_read_write); -TEST_CASE_MULTI_FLASH("SPI flash simple read/write", test_simple_read_write); - -void test_unaligned_read_write(const esp_partition_t* part) -{ - esp_flash_t* chip = part->flash_chip; - uint32_t offs = erase_test_region(part, 2); - - const char *msg = "i am a message"; - TEST_ASSERT(strlen(msg) + 1 % 4 != 0); - TEST_ASSERT_EQUAL(ESP_OK, esp_flash_write(chip, msg, offs + 1, strlen(msg) + 1) ); - - char buf[strlen(msg) + 1]; - - memset(buf, 0xEE, sizeof(buf)); - - TEST_ASSERT_EQUAL(ESP_OK, esp_flash_read(chip, buf, offs + 1, strlen(msg) + 1) ); - TEST_ASSERT_EQUAL_STRING_LEN(msg, buf, strlen(msg)); - TEST_ASSERT(memcmp(buf, msg, strlen(msg) + 1) == 0); -} - -TEST_CASE_FLASH("SPI flash unaligned read/write", test_unaligned_read_write); -TEST_CASE_MULTI_FLASH("SPI flash unaligned read/write", test_unaligned_read_write); - -void test_single_read_write(const esp_partition_t* part) -{ - esp_flash_t* chip = part->flash_chip; - uint32_t offs = erase_test_region(part, 2); - - const int seed = 699; - srand(seed); - for (unsigned v = 0; v < 512; v++) { - uint32_t data = rand(); - TEST_ASSERT_EQUAL_HEX(ESP_OK, esp_flash_write(chip, &data, offs + v, 1) ); - } - - srand(seed); - for (unsigned v = 0; v < 512; v++) { - uint8_t readback; - uint32_t data = rand(); - TEST_ASSERT_EQUAL_HEX(ESP_OK, esp_flash_read(chip, &readback, offs + v, 1) ); - TEST_ASSERT_EQUAL_HEX8(data, readback); - } -} - -TEST_CASE_FLASH("SPI flash single byte reads/writes", test_single_read_write); -TEST_CASE_MULTI_FLASH("SPI flash single byte reads/writes", test_single_read_write); - - -/* this test is notable because it generates a lot of unaligned reads/writes, - and also reads/writes across both a sector boundary & many page boundaries. -*/ -void test_three_byte_read_write(const esp_partition_t* part) -{ - esp_flash_t* chip = part->flash_chip; - uint32_t offs = erase_test_region(part, 2); - - const int seed = 700; - esp_rom_printf("offs:%X\n", offs); - - srand(seed); - for (uint32_t v = 0; v < 86; v++) { - uint32_t data = rand(); - TEST_ASSERT_EQUAL(ESP_OK, esp_flash_write(chip, &data, offs + 3 * v, 3) ); - } - - srand(seed); - for (uint32_t v = 0; v < 1; v++) { - uint32_t readback; - uint32_t data = rand(); - TEST_ASSERT_EQUAL(ESP_OK, esp_flash_read(chip, &readback, offs + 3 * v, 3) ); - TEST_ASSERT_EQUAL_HEX32(data & 0xFFFFFF, readback & 0xFFFFFF); - } -} - -TEST_CASE_FLASH("SPI flash three byte reads/writes", test_three_byte_read_write); -TEST_CASE_MULTI_FLASH("SPI flash three byte reads/writes", test_three_byte_read_write); - -void test_erase_large_region(const esp_partition_t *part) -{ - esp_flash_t* chip = part->flash_chip; - - /* Write some noise at the start and the end of the region */ - const char *ohai = "OHAI"; - uint32_t readback; - TEST_ASSERT_EQUAL(ESP_OK, esp_flash_write(chip, ohai, part->address, 5)); - TEST_ASSERT_EQUAL(ESP_OK, esp_flash_write(chip, ohai, part->address + part->size - 5, 5)); - - /* sanity check what we just wrote. since the partition may haven't been erased, we only check the part which is written to 0. */ - uint32_t written_data = *((const uint32_t *)ohai); - TEST_ASSERT_EQUAL(ESP_OK, esp_flash_read(chip, &readback, part->address + part->size - 5, 4)); - TEST_ASSERT_EQUAL_HEX32(0, readback & (~written_data)); - TEST_ASSERT_EQUAL(ESP_OK, esp_flash_read(chip, &readback, part->address, 4)); - TEST_ASSERT_EQUAL_HEX32(0, readback & (~written_data)); - - /* Erase zero bytes, check that nothing got erased */ - TEST_ASSERT_EQUAL(ESP_OK, esp_flash_erase_region(chip, part->address, 0)); - TEST_ASSERT_EQUAL(ESP_OK, esp_flash_read(chip, &readback, part->address + part->size - 5, 4)); - TEST_ASSERT_EQUAL_HEX32(0, readback & (~written_data)); - TEST_ASSERT_EQUAL(ESP_OK, esp_flash_read(chip, &readback, part->address, 4)); - TEST_ASSERT_EQUAL_HEX32(0, readback & (~written_data)); - - /* Erase whole region */ - TEST_ASSERT_EQUAL(ESP_OK, esp_flash_erase_region(chip, part->address, part->size)); - - /* ensure both areas we wrote are now all-FFs */ - TEST_ASSERT_EQUAL(ESP_OK, esp_flash_read(chip, &readback, part->address, 4)); - TEST_ASSERT_EQUAL_HEX32(0xFFFFFFFF, readback); - - TEST_ASSERT_EQUAL(ESP_OK, esp_flash_read(chip, &readback, part->address + part->size - 5, 4)); - TEST_ASSERT_EQUAL_HEX32(0xFFFFFFFF, readback); -} - -TEST_CASE_FLASH("SPI flash erase large region", test_erase_large_region); -TEST_CASE_MULTI_FLASH("SPI flash erase large region", test_erase_large_region); - -#if CONFIG_SPI_FLASH_AUTO_SUSPEND -void esp_test_for_suspend(void) -{ - /*clear content in cache*/ -#if !CONFIG_IDF_TARGET_ESP32C3 - Cache_Invalidate_DCache_All(); -#endif - Cache_Invalidate_ICache_All(); - ESP_LOGI(TAG, "suspend test begins:"); - printf("run into test suspend function\n"); - printf("print something when flash is erasing:\n"); - printf("aaaaa bbbbb zzzzz fffff qqqqq ccccc\n"); -} - -static volatile bool task_erase_end, task_suspend_end = false; -void task_erase_large_region(void *arg) -{ - esp_partition_t *part = (esp_partition_t *)arg; - test_erase_large_region(part); - task_erase_end = true; - vTaskDelete(NULL); -} - -void task_request_suspend(void *arg) -{ - vTaskDelay(2); - ESP_LOGI(TAG, "flash go into suspend"); - esp_test_for_suspend(); - task_suspend_end = true; - vTaskDelete(NULL); -} - -static void test_flash_suspend_resume(const esp_partition_t* part) -{ - xTaskCreatePinnedToCore(task_request_suspend, "suspend", 2048, (void *)"test_for_suspend", UNITY_FREERTOS_PRIORITY + 3, NULL, 0); - xTaskCreatePinnedToCore(task_erase_large_region, "test", 2048, (void *)part, UNITY_FREERTOS_PRIORITY + 2, NULL, 0); - while (!task_erase_end || !task_suspend_end) { - } - vTaskDelay(200); -} - -TEST_CASE("SPI flash suspend and resume test", "[esp_flash][test_env=UT_T1_Flash_Suspend]") -{ - flash_test_func(test_flash_suspend_resume, 1 /* first index reserved for main flash */ ); -} - -#endif //CONFIG_SPI_FLASH_AUTO_SUSPEND - -static void test_write_protection(const esp_partition_t* part) -{ - esp_flash_t* chip = part->flash_chip; - - bool wp = true; - esp_err_t ret = ESP_OK; - ret = esp_flash_get_chip_write_protect(chip, &wp); - TEST_ESP_OK(ret); - - for (int i = 0; i < 4; i ++) { - bool wp_write = !wp; - ret = esp_flash_set_chip_write_protect(chip, wp_write); - TEST_ESP_OK(ret); - - bool wp_read; - ret = esp_flash_get_chip_write_protect(chip, &wp_read); - TEST_ESP_OK(ret); - TEST_ASSERT(wp_read == wp_write); - wp = wp_read; - } -} - -TEST_CASE_FLASH("Test esp_flash can enable/disable write protetion", test_write_protection); -TEST_CASE_MULTI_FLASH("Test esp_flash can enable/disable write protetion", test_write_protection); - -static const uint8_t large_const_buffer[16400] = { - 203, // first byte - 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, - 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, - [50 ... 99] = 2, - [1600 ... 2000] = 3, - [8000 ... 9000] = 77, - [15000 ... 16398] = 8, - 43 // last byte -}; - -static void test_write_large_buffer(const esp_partition_t *part, const uint8_t *source, size_t length); -static void write_large_buffer(const esp_partition_t *part, const uint8_t *source, size_t length); -static void read_and_check(const esp_partition_t *part, const uint8_t *source, size_t length); - -// Internal functions for testing, from esp_flash_api.c -#if !CONFIG_ESPTOOLPY_OCT_FLASH -esp_err_t esp_flash_set_io_mode(esp_flash_t* chip, bool qe); -esp_err_t esp_flash_get_io_mode(esp_flash_t* chip, bool* qe); -esp_err_t esp_flash_read_chip_id(esp_flash_t* chip, uint32_t* flash_id); -esp_err_t spi_flash_chip_mxic_probe(esp_flash_t *chip, uint32_t flash_id); - -static bool is_winbond_chip(esp_flash_t* chip) -{ - uint32_t flash_id; - esp_err_t ret = esp_flash_read_chip_id(chip, &flash_id); - TEST_ESP_OK(ret); - if ((flash_id >> 16) == 0xEF) { - return true; - } else { - return false; - } -} - -static bool is_mxic_chip(esp_flash_t* chip) -{ - uint32_t flash_id; - esp_err_t ret = esp_flash_read_chip_id(chip, &flash_id); - TEST_ESP_OK(ret); - return (spi_flash_chip_mxic_probe(chip, flash_id)==ESP_OK); -} - -IRAM_ATTR NOINLINE_ATTR static void test_toggle_qe(const esp_partition_t* part) -{ - esp_flash_t* chip = part->flash_chip; - - bool qe; - if (chip == NULL) { - chip = esp_flash_default_chip; - } - esp_flash_io_mode_t io_mode_before = chip->read_mode; - esp_err_t ret = esp_flash_get_io_mode(chip, &qe); - TEST_ESP_OK(ret); - - bool allow_failure = is_winbond_chip(chip) || is_mxic_chip(chip); - - for (int i = 0; i < 4; i ++) { - esp_rom_printf(DRAM_STR("write qe: %d->%d\n"), qe, !qe); - qe = !qe; - chip->read_mode = qe? SPI_FLASH_QOUT: SPI_FLASH_SLOWRD; - ret = esp_flash_set_io_mode(chip, qe); - if (allow_failure && !qe && ret == ESP_ERR_FLASH_NO_RESPONSE) { - //allows clear qe failure for Winbond chips - ret = ESP_OK; - } - TEST_ESP_OK(ret); - - bool qe_read; - ret = esp_flash_get_io_mode(chip, &qe_read); - TEST_ESP_OK(ret); - ESP_LOGD(TAG, "qe read: %d", qe_read); - if (!qe && qe_read) { - if (allow_failure) { - ESP_LOGW(TAG, "cannot clear QE bit for known permanent QE (Winbond or MXIC) chips."); - } else { - ESP_LOGE(TAG, "cannot clear QE bit, please make sure force clearing QE option is enabled in `spi_flash_common_set_io_mode`, and this chip is not a permanent QE one."); - } - chip->read_mode = io_mode_before; - return; - } - TEST_ASSERT_EQUAL(qe, qe_read); - } - //restore the io_mode after test - chip->read_mode = io_mode_before; -} - -// These tests show whether the QE is permanent or not for the chip tested. -// To test the behaviour of a new SPI flash chip, enable force_check flag in generic driver -// `spi_flash_common_set_io_mode` and then run this test. -TEST_CASE_FLASH_IGNORE("Test esp_flash_write can toggle QE bit", test_toggle_qe); -TEST_CASE_MULTI_FLASH_IGNORE("Test esp_flash_write can toggle QE bit", test_toggle_qe); -#endif //CONFIG_ESPTOOLPY_OCT_FLASH - -// This table could be chip specific in the future. -uint8_t flash_frequency_table[6] = {5, 10, 20, 26, 40, 80}; -#define TEST_FLASH_SPEED_MIN 5 -void test_permutations_part(const flashtest_config_t* config, esp_partition_t* part, void* source_buf, size_t length) -{ - int clock_index = 0; - if (config->host_id != -1) { - while (clock_index < sizeof(flash_frequency_table)/sizeof(uint8_t)) { - uint8_t speed = flash_frequency_table[clock_index]; - //test io_mode in the inner loop to test QE set/clear function, since - //the io mode will switch frequently. - esp_flash_io_mode_t io_mode = SPI_FLASH_READ_MODE_MIN; - while (io_mode != SPI_FLASH_QIO + 1) { - if (io_mode > SPI_FLASH_FASTRD && - !SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(config->host_id)) { - io_mode++; - continue; - } - - esp_flash_t* chip; - flashtest_config_t temp_config = *config; - temp_config.io_mode = io_mode; - temp_config.freq_mhz = flash_frequency_table[clock_index]; - setup_new_chip(&temp_config, &chip); - ESP_LOGI(TAG, "test flash io mode: %d, speed: %d", io_mode, speed); - - part->flash_chip = chip; - read_and_check(part, source_buf, length); - teardown_test_chip(chip); - - io_mode++; - } - clock_index++; - } - } else { - //test main flash - part->flash_chip = NULL; - read_and_check(part, source_buf, length); - } -} - -void test_permutations_chip(const flashtest_config_t* config) -{ - esp_log_level_set("gpio", ESP_LOG_NONE); - esp_flash_t* chip; - flashtest_config_t temp_config = *config; - // Use the lowest speed to read configs, data and write data to make sure success - temp_config.io_mode = SPI_FLASH_READ_MODE_MIN; - temp_config.freq_mhz = TEST_FLASH_SPEED_MIN; - setup_new_chip(&temp_config, &chip); - - //Get size to determine whether to test one extra partition - uint32_t size; - esp_err_t err = esp_flash_get_size(chip, &size); - TEST_ESP_OK(err); - ESP_LOGI(TAG, "Flash size: 0x%08X", size); - bool addr_32bit = (size > MAX_ADDR_24BIT); - - // Get test partition, and locate temporary partitions according to the default one - const esp_partition_t* test_part = get_test_data_partition(); - const int length = sizeof(large_const_buffer); - TEST_ASSERT(test_part->size > length + 2 + SPI_FLASH_SEC_SIZE); - - esp_partition_t part[2] = {}; - part[0] = *test_part; - part[0].flash_chip = chip; - // For flash with size over 16MB, add one extra round of test for the 32-bit address area - if (addr_32bit) { - part[1] = *test_part; - part[1].flash_chip = chip; - part[1].address = 0x1030000; - part[1].size = 0x0010000; - } else { - part[1].size = 0; - } - - // Prepare test data and write to the specified region - uint8_t *source_buf = malloc(length); - TEST_ASSERT_NOT_NULL(source_buf); - srand(778); - for (int i = 0; i < length; i++) { - source_buf[i] = rand(); - } - - for (int i = 0; i < 2; i++) { - if (part[i].size == 0) continue; - write_large_buffer(&part[i], source_buf, length); - } - - teardown_test_chip(chip); - - for (int i = 0; i < 2; i++) { - if (part[i].size == 0) continue; - - part[i].flash_chip = (esp_flash_t*)-1; - ESP_LOGI(TAG, "Testing address 0x%08X...", part[i].address); - test_permutations_part(config, &part[i], source_buf, length); - } - - free(source_buf); -} - -TEST_CASE("SPI flash test reading with all speed/mode permutations", "[esp_flash]") -{ - test_permutations_chip(&config_list[0]); -} - -#ifndef CONFIG_SPIRAM -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) -//IDF-5049 -TEST_CASE("SPI flash test reading with all speed/mode permutations, 3 chips", "[esp_flash_3][test_env=UT_T1_ESP_FLASH]") -{ - for (int i = 0; i < TEST_CONFIG_NUM; i++) { - test_permutations_chip(&config_list[i]); - } -} -#endif -#endif - - -static void test_write_large_const_buffer(const esp_partition_t* part) -{ - test_write_large_buffer(part, large_const_buffer, sizeof(large_const_buffer)); -} - -TEST_CASE_FLASH("Test esp_flash_write large const buffer", test_write_large_const_buffer); -TEST_CASE_MULTI_FLASH("Test esp_flash_write large const buffer", test_write_large_const_buffer); - -static void test_write_large_ram_buffer(const esp_partition_t* part) -{ - // buffer in RAM - uint8_t *source_buf = malloc(sizeof(large_const_buffer)); - TEST_ASSERT_NOT_NULL(source_buf); - memcpy(source_buf, large_const_buffer, sizeof(large_const_buffer)); - test_write_large_buffer(part, source_buf, sizeof(large_const_buffer)); - free(source_buf); -} - -TEST_CASE_FLASH("Test esp_flash_write large RAM buffer", test_write_large_ram_buffer); -TEST_CASE_MULTI_FLASH("Test esp_flash_write large RAM buffer", test_write_large_ram_buffer); - -static void write_large_buffer(const esp_partition_t *part, const uint8_t *source, size_t length) -{ - esp_flash_t* chip = part->flash_chip; - - printf("Writing chip %p %p, %d bytes from source %p\n", chip, (void*)part->address, length, source); - ESP_ERROR_CHECK( esp_flash_erase_region(chip, part->address, (length + SPI_FLASH_SEC_SIZE) & ~(SPI_FLASH_SEC_SIZE - 1)) ); - - // note writing to unaligned address - ESP_ERROR_CHECK( esp_flash_write(chip, source, part->address + 1, length) ); -} - -static void read_and_check(const esp_partition_t *part, const uint8_t *source, size_t length) -{ - esp_flash_t* chip = part->flash_chip; - printf("Checking chip %p 0x%08X, %d bytes\n", chip, part->address, length); - uint8_t *buf = malloc(length); - TEST_ASSERT_NOT_NULL(buf); - ESP_ERROR_CHECK( esp_flash_read(chip, buf, part->address + 1, length) ); - TEST_ASSERT_EQUAL_HEX8_ARRAY(source, buf, length); - free(buf); - - // check nothing was written at beginning or end - uint8_t ends[8]; - - ESP_ERROR_CHECK( esp_flash_read(chip, ends, part->address, sizeof(ends)) ); - TEST_ASSERT_EQUAL_HEX8(0xFF, ends[0]); - TEST_ASSERT_EQUAL_HEX8(source[0], ends[1]); - - ESP_ERROR_CHECK( esp_flash_read(chip, ends, part->address + length, sizeof(ends)) ); - - TEST_ASSERT_EQUAL_HEX8(source[length - 1], ends[0]); - TEST_ASSERT_EQUAL_HEX8(0xFF, ends[1]); - TEST_ASSERT_EQUAL_HEX8(0xFF, ends[2]); - TEST_ASSERT_EQUAL_HEX8(0xFF, ends[3]); -} - -static void test_write_large_buffer(const esp_partition_t* part, const uint8_t *source, size_t length) -{ - TEST_ASSERT(part->size > length + 2 + SPI_FLASH_SEC_SIZE); - - write_large_buffer(part, source, length); - read_and_check(part, source, length); -} typedef struct { uint32_t us_start; size_t len; const char* name; } time_meas_ctx_t; - static void time_measure_start(time_meas_ctx_t* ctx) { ctx->us_start = esp_timer_get_time(); @@ -1181,73 +639,3 @@ TEST_CASE("Test esp_flash read/write performance", "[esp_flash][test_env=UT_T1_E #endif TEST_CASE_MULTI_FLASH("Test esp_flash read/write performance", test_flash_read_write_performance); - -#ifdef CONFIG_SPIRAM_USE_MALLOC - -/* Utility: Read into a small internal RAM buffer using esp_flash_read() and compare what - we read with 'buffer' */ -static void s_test_compare_flash_contents_small_reads(esp_flash_t *chip, const uint8_t *buffer, size_t offs, size_t len) -{ - const size_t INTERNAL_BUF_SZ = 1024; // Should fit in internal RAM - uint8_t *ibuf = heap_caps_malloc(INTERNAL_BUF_SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(ibuf); - - for (int i = 0; i < len; i += INTERNAL_BUF_SZ) { - size_t to_read = MIN(INTERNAL_BUF_SZ, len - i); - ESP_ERROR_CHECK( esp_flash_read(chip, ibuf, offs + i, to_read) ); - TEST_ASSERT_EQUAL_HEX8_ARRAY(buffer + i, ibuf, to_read); - } - - free(ibuf); -} - -static void test_flash_read_large_psram_buffer(const esp_partition_t *part) -{ - esp_flash_t* chip = part->flash_chip; - const size_t BUF_SZ = 256 * 1024; // Too large for internal RAM - const size_t TEST_OFFS = 0x1000; // Can be any offset, really - - uint8_t *buf = heap_caps_malloc(BUF_SZ, MALLOC_CAP_8BIT|MALLOC_CAP_SPIRAM); - TEST_ASSERT_NOT_NULL(buf); - - ESP_ERROR_CHECK( esp_flash_read(chip, buf, TEST_OFFS, BUF_SZ) ); - - // Read back the same into smaller internal memory buffer and check it all matches - s_test_compare_flash_contents_small_reads(chip, buf, TEST_OFFS, BUF_SZ); - - free(buf); -} - -TEST_CASE_FLASH("esp_flash_read large PSRAM buffer", test_flash_read_large_psram_buffer); - - -/* similar to above test, but perform it under memory pressure */ -static void test_flash_read_large_psram_buffer_low_internal_mem(const esp_partition_t *part) -{ - esp_flash_t* chip = part->flash_chip; - const size_t BUF_SZ = 256 * 1024; // Too large for internal RAM - const size_t REMAINING_INTERNAL = 1024; // Exhaust internal memory until maximum free block is less than this - const size_t TEST_OFFS = 0x8000; - - /* Exhaust the available free internal memory */ - test_utils_exhaust_memory_rec erec = test_utils_exhaust_memory(MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT, REMAINING_INTERNAL); - - uint8_t *buf = heap_caps_malloc(BUF_SZ, MALLOC_CAP_8BIT|MALLOC_CAP_SPIRAM); - TEST_ASSERT_NOT_NULL(buf); - - /* Calling esp_flash_read() here will need to allocate a small internal buffer, - so check it works. */ - ESP_ERROR_CHECK( esp_flash_read(chip, buf, TEST_OFFS, BUF_SZ) ); - - test_utils_free_exhausted_memory(erec); - - // Read back the same into smaller internal memory buffer and check it all matches - s_test_compare_flash_contents_small_reads(chip, buf, TEST_OFFS, BUF_SZ); - - free(buf); -} - -TEST_CASE_FLASH("esp_flash_read large PSRAM buffer low memory", test_flash_read_large_psram_buffer_low_internal_mem); - - -#endif diff --git a/components/spi_flash/test_apps/esp_flash/CMakeLists.txt b/components/spi_flash/test_apps/esp_flash/CMakeLists.txt new file mode 100644 index 0000000000..2f29d7008a --- /dev/null +++ b/components/spi_flash/test_apps/esp_flash/CMakeLists.txt @@ -0,0 +1,5 @@ +# This is the project CMakeLists.txt file for the test subproject +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(test_esp_flash_drv) diff --git a/components/spi_flash/test_apps/esp_flash/README.md b/components/spi_flash/test_apps/esp_flash/README.md new file mode 100644 index 0000000000..b5be4985c5 --- /dev/null +++ b/components/spi_flash/test_apps/esp_flash/README.md @@ -0,0 +1,2 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | diff --git a/components/spi_flash/test_apps/esp_flash/main/CMakeLists.txt b/components/spi_flash/test_apps/esp_flash/main/CMakeLists.txt new file mode 100644 index 0000000000..9058d7ac19 --- /dev/null +++ b/components/spi_flash/test_apps/esp_flash/main/CMakeLists.txt @@ -0,0 +1,7 @@ +set(srcs "test_app_main.c" + "test_esp_flash_drv.c") + +# In order for the cases defined by `TEST_CASE` to be linked into the final elf, +# the component can be registered as WHOLE_ARCHIVE +idf_component_register(SRCS ${srcs} + WHOLE_ARCHIVE) diff --git a/components/spi_flash/test_apps/esp_flash/main/test_app_main.c b/components/spi_flash/test_apps/esp_flash/main/test_app_main.c new file mode 100644 index 0000000000..83b782c198 --- /dev/null +++ b/components/spi_flash/test_apps/esp_flash/main/test_app_main.c @@ -0,0 +1,56 @@ +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "unity.h" +#include "unity_test_runner.h" +#include "esp_heap_caps.h" + +// Some resources are lazy allocated in flash encryption, the threadhold is left for that case +#define TEST_MEMORY_LEAK_THRESHOLD (-300) + +static size_t before_free_8bit; +static size_t before_free_32bit; + +static void check_leak(size_t before_free, size_t after_free, const char *type) +{ + ssize_t delta = after_free - before_free; + printf("MALLOC_CAP_%s: Before %u bytes free, After %u bytes free (delta %d)\n", type, before_free, after_free, delta); + TEST_ASSERT_MESSAGE(delta >= TEST_MEMORY_LEAK_THRESHOLD, "memory leak"); +} + +void setUp(void) +{ + before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); +} + +void tearDown(void) +{ + size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); + size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); + check_leak(before_free_8bit, after_free_8bit, "8BIT"); + check_leak(before_free_32bit, after_free_32bit, "32BIT"); +} + +void app_main(void) +{ + + // ,------. ,---. ,------. ,------.,--. ,--. + // | .---'' .-' | .--. ' | .---'| | ,--,--. ,---. | ,---. + // | `--, `. `-. | '--' | | `--, | |' ,-. |( .-' | .-. | + // | `---..-' || | --' | |` | |\ '-' |.-' `)| | | | + // `------'`-----' `--' `--' `--' `--`--'`----' `--' `--' + + + printf(",------. ,---. ,------. ,------.,--. ,--. \n"); + printf("| .---'' .-' | .--. ' | .---'| | ,--,--. ,---. | ,---. \n"); + printf("| `--, `. `-. | '--' | | `--, | |' ,-. |( .-' | .-. | \n"); + printf("| `---..-' || | --' | |` | |\\ '-' |.-' `)| | | | \n"); + printf("`------'`-----' `--' `--' `--' `--`--'`----' `--' `--' \n"); + + + unity_run_menu(); +} diff --git a/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_def.h b/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_def.h new file mode 100644 index 0000000000..b0ac1c8f32 --- /dev/null +++ b/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_def.h @@ -0,0 +1,242 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include "sdkconfig.h" + +#define MAX_ADDR_24BIT 0x1000000 +#define TEST_SPI_SPEED 10 +#define TEST_SPI_READ_MODE SPI_FLASH_FASTRD +// #define FORCE_GPIO_MATRIX + +#if CONFIG_IDF_TARGET_ESP32 +#define EXTRA_SPI1_CLK_IO 17 //the pin which is usually used by the PSRAM clk +#define SPI1_CS_IO 16 //the pin which is usually used by the PSRAM cs + +#define HSPI_PIN_NUM_MOSI HSPI_IOMUX_PIN_NUM_MOSI +#define HSPI_PIN_NUM_MISO HSPI_IOMUX_PIN_NUM_MISO +#define HSPI_PIN_NUM_CLK HSPI_IOMUX_PIN_NUM_CLK +#define HSPI_PIN_NUM_HD HSPI_IOMUX_PIN_NUM_HD +#define HSPI_PIN_NUM_WP HSPI_IOMUX_PIN_NUM_WP +#define HSPI_PIN_NUM_CS HSPI_IOMUX_PIN_NUM_CS + +#define VSPI_PIN_NUM_MOSI VSPI_IOMUX_PIN_NUM_MOSI +#define VSPI_PIN_NUM_MISO VSPI_IOMUX_PIN_NUM_MISO +#define VSPI_PIN_NUM_CLK VSPI_IOMUX_PIN_NUM_CLK +#define VSPI_PIN_NUM_HD VSPI_IOMUX_PIN_NUM_HD +#define VSPI_PIN_NUM_WP VSPI_IOMUX_PIN_NUM_WP +#define VSPI_PIN_NUM_CS VSPI_IOMUX_PIN_NUM_CS + +#elif CONFIG_IDF_TARGET_ESP32S2 +#define SPI1_CS_IO 26 //the pin which is usually used by the PSRAM cs +#define SPI1_HD_IO 27 //the pin which is usually used by the PSRAM hd +#define SPI1_WP_IO 28 //the pin which is usually used by the PSRAM wp + +#define FSPI_PIN_NUM_MOSI 35 +#define FSPI_PIN_NUM_MISO 37 +#define FSPI_PIN_NUM_CLK 36 +#define FSPI_PIN_NUM_HD 33 +#define FSPI_PIN_NUM_WP 38 +#define FSPI_PIN_NUM_CS 34 + +// Just use the same pins for HSPI +#define HSPI_PIN_NUM_MOSI FSPI_PIN_NUM_MOSI +#define HSPI_PIN_NUM_MISO FSPI_PIN_NUM_MISO +#define HSPI_PIN_NUM_CLK FSPI_PIN_NUM_CLK +#define HSPI_PIN_NUM_HD FSPI_PIN_NUM_HD +#define HSPI_PIN_NUM_WP FSPI_PIN_NUM_WP +#define HSPI_PIN_NUM_CS FSPI_PIN_NUM_CS + +#elif CONFIG_IDF_TARGET_ESP32S3 +#define SPI1_CS_IO 26 //the pin which is usually used by the PSRAM cs +#define SPI1_HD_IO 27 //the pin which is usually used by the PSRAM hd +#define SPI1_WP_IO 28 //the pin which is usually used by the PSRAM wp + +#define FSPI_PIN_NUM_MOSI 11 +#define FSPI_PIN_NUM_MISO 13 +#define FSPI_PIN_NUM_CLK 12 +#define FSPI_PIN_NUM_HD 9 +#define FSPI_PIN_NUM_WP 14 +#define FSPI_PIN_NUM_CS 10 + +// Just use the same pins for HSPI +#define HSPI_PIN_NUM_MOSI FSPI_PIN_NUM_MOSI +#define HSPI_PIN_NUM_MISO FSPI_PIN_NUM_MISO +#define HSPI_PIN_NUM_CLK FSPI_PIN_NUM_CLK +#define HSPI_PIN_NUM_HD FSPI_PIN_NUM_HD +#define HSPI_PIN_NUM_WP FSPI_PIN_NUM_WP +#define HSPI_PIN_NUM_CS FSPI_PIN_NUM_CS + +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 +#define SPI1_CS_IO 26 //the pin which is usually used by the PSRAM cs +#define SPI1_HD_IO 27 //the pin which is usually used by the PSRAM hd +#define SPI1_WP_IO 28 //the pin which is usually used by the PSRAM wp + +#define FSPI_PIN_NUM_MOSI 7 +#define FSPI_PIN_NUM_MISO 2 +#define FSPI_PIN_NUM_CLK 6 +#define FSPI_PIN_NUM_HD 4 +#define FSPI_PIN_NUM_WP 5 +#define FSPI_PIN_NUM_CS 10 + +// Just use the same pins for HSPI +#define HSPI_PIN_NUM_MOSI FSPI_PIN_NUM_MOSI +#define HSPI_PIN_NUM_MISO FSPI_PIN_NUM_MISO +#define HSPI_PIN_NUM_CLK FSPI_PIN_NUM_CLK +#define HSPI_PIN_NUM_HD FSPI_PIN_NUM_HD +#define HSPI_PIN_NUM_WP FSPI_PIN_NUM_WP +#define HSPI_PIN_NUM_CS FSPI_PIN_NUM_CS +#endif + +#define TEST_CONFIG_NUM (sizeof(config_list)/sizeof(flashtest_config_t)) + +typedef void (*flash_test_func_t)(const esp_partition_t *part); + +/* Use TEST_CASE_FLASH for SPI flash tests that only use the main SPI flash chip +*/ +#define TEST_CASE_FLASH(STR, FUNC_TO_RUN) \ + TEST_CASE(STR, "[esp_flash]") {flash_test_func(FUNC_TO_RUN, 1 /* first index reserved for main flash */ );} + +#define TEST_CASE_FLASH_IGNORE(STR, FUNC_TO_RUN) \ + TEST_CASE(STR, "[esp_flash][ignore]") {flash_test_func(FUNC_TO_RUN, 1 /* first index reserved for main flash */ );} + +/* Use TEST_CASE_MULTI_FLASH for tests which also run on external flash, which sits in the place of PSRAM + (these tests are incompatible with PSRAM) + + These tests run for all the flash chip configs shown in config_list, below (internal and external). + */ +#define IDF_LOG_PERFORMANCE(item, value_fmt, value, ...) \ + printf("[Performance][%s]: " value_fmt "\n", item, value, ##__VA_ARGS__) + + +#if defined(CONFIG_SPIRAM) +//SPI1 CS1 occupied by PSRAM +#define BYPASS_MULTIPLE_CHIP 1 +#endif + +#if CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 +//chips without PSRAM +#define TEST_CHIP_NUM 2 +#elif CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 +#define TEST_CHIP_NUM 3 +#endif + +#define _STRINGIFY(s) #s +#define STRINGIFY(s) _STRINGIFY(s) +#define TEST_CHIP_NUM_STR STRINGIFY(TEST_CHIP_NUM) + +#if BYPASS_MULTIPLE_CHIP +#define TEST_CASE_MULTI_FLASH TEST_CASE_MULTI_FLASH_IGNORE +#else +#if CONFIG_FREERTOS_SMP // IDF-5260 +#define TEST_CASE_MULTI_FLASH(STR, FUNC_TO_RUN) \ + TEST_CASE(STR", "TEST_CHIP_NUM_STR" chips", "[esp_flash_multi][test_env=UT_T1_ESP_FLASH][timeout=60]") {flash_test_func(FUNC_TO_RUN, TEST_CONFIG_NUM);} +#else +#define TEST_CASE_MULTI_FLASH(STR, FUNC_TO_RUN) \ + TEST_CASE(STR", "TEST_CHIP_NUM_STR" chips", "[esp_flash_multi][test_env=UT_T1_ESP_FLASH][timeout=35]") {flash_test_func(FUNC_TO_RUN, TEST_CONFIG_NUM);} +#endif +#endif + +#define TEST_CASE_MULTI_FLASH_IGNORE(STR, FUNC_TO_RUN) \ + TEST_CASE(STR", "TEST_CHIP_NUM_STR" chips", "[esp_flash_multi][test_env=UT_T1_ESP_FLASH][ignore]") {flash_test_func(FUNC_TO_RUN, TEST_CONFIG_NUM);} + + +//currently all the configs are the same with esp_flash_spi_device_config_t, no more information required +typedef esp_flash_spi_device_config_t flashtest_config_t; + +static const char TAG[] = "test_esp_flash"; + +#define FLASHTEST_CONFIG_COMMON \ + /* 0 always reserved for main flash */ \ + { \ + /* no need to init */ \ + .host_id = -1, \ + } \ + , \ + { \ + .io_mode = TEST_SPI_READ_MODE,\ + .freq_mhz = TEST_SPI_SPEED, \ + .host_id = SPI1_HOST, \ + .cs_id = 1, \ + /* the pin which is usually used by the PSRAM */ \ + .cs_io_num = SPI1_CS_IO, \ + .input_delay_ns = 0, \ + } + +#if CONFIG_IDF_TARGET_ESP32 +flashtest_config_t config_list[] = { + FLASHTEST_CONFIG_COMMON, + /* current runner doesn't have a flash on HSPI */ + // { + // .io_mode = TEST_SPI_READ_MODE, + // .freq_mhz = TEST_SPI_SPEED, + // .host_id = HSPI_HOST, + // .cs_id = 0, + // // uses GPIO matrix on esp32s2 regardless if FORCE_GPIO_MATRIX + // .cs_io_num = HSPI_PIN_NUM_CS, + // .input_delay_ns = 20, + // }, + { + .io_mode = TEST_SPI_READ_MODE, + .freq_mhz = TEST_SPI_SPEED, + .host_id = VSPI_HOST, + .cs_id = 0, + .cs_io_num = VSPI_PIN_NUM_CS, + .input_delay_ns = 0, + }, +}; +#elif CONFIG_IDF_TARGET_ESP32S2 +flashtest_config_t config_list[] = { + FLASHTEST_CONFIG_COMMON, + { + .io_mode = TEST_SPI_READ_MODE, + .freq_mhz = TEST_SPI_SPEED, + .host_id = FSPI_HOST, + .cs_id = 0, + .cs_io_num = FSPI_PIN_NUM_CS, + .input_delay_ns = 0, + }, + { + .io_mode = TEST_SPI_READ_MODE, + .freq_mhz = TEST_SPI_SPEED, + .host_id = HSPI_HOST, + .cs_id = 0, + // uses GPIO matrix on esp32s2 regardless of FORCE_GPIO_MATRIX + .cs_io_num = HSPI_PIN_NUM_CS, + .input_delay_ns = 0, + }, +}; +#elif CONFIG_IDF_TARGET_ESP32S3 +flashtest_config_t config_list[] = { + /* No SPI1 CS1 flash on esp32S3 test */ + { + /* no need to init */ + .host_id = -1, + }, + { + .io_mode = TEST_SPI_READ_MODE, + .freq_mhz = TEST_SPI_SPEED, + .host_id = SPI2_HOST, + .cs_id = 0, + .cs_io_num = FSPI_PIN_NUM_CS, + .input_delay_ns = 0, + }, +}; +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 +flashtest_config_t config_list[] = { + /* No SPI1 CS1 flash on esp32c3 test */ + { + /* no need to init */ + .host_id = -1, + }, + { + .io_mode = TEST_SPI_READ_MODE, + .freq_mhz = TEST_SPI_SPEED, + .host_id = SPI2_HOST, + .cs_id = 0, + .cs_io_num = FSPI_PIN_NUM_CS, + .input_delay_ns = 0, + }, +}; +#endif diff --git a/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c b/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c new file mode 100644 index 0000000000..65516d1dce --- /dev/null +++ b/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c @@ -0,0 +1,850 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include +#include +#include +#include +#include +#include + +#include +#include "esp_flash.h" +#include "esp_private/spi_common_internal.h" +#include "esp_flash_spi_init.h" +#include "memspi_host_driver.h" +#include +#include "esp_log.h" + +#include "unity.h" +#include "driver/gpio.h" +#include "soc/io_mux_reg.h" +#include "sdkconfig.h" + +#include "esp_partition.h" +#include "esp_rom_gpio.h" +#include "esp_rom_sys.h" +#include "esp_timer.h" +#include "test_esp_flash_def.h" + +#if CONFIG_IDF_TARGET_ESP32S2 +#include "esp32s2/rom/cache.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/cache.h" +#elif CONFIG_IDF_TARGET_ESP32C3 +#include "esp32c3/rom/cache.h" +#elif CONFIG_IDF_TARGET_ESP32H2 +#include "esp32h2/rom/cache.h" +#elif CONFIG_IDF_TARGET_ESP32C2 +#include "esp32c2/rom/cache.h" +#endif + +#define FUNC_SPI 1 + +static uint8_t sector_buf[4096]; + +const esp_partition_t *get_test_data_partition(void) +{ + /* This finds "flash_test" partition defined in partition_table_unit_test_app.csv */ + const esp_partition_t *result = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, + ESP_PARTITION_SUBTYPE_ANY, "flash_test"); + TEST_ASSERT_NOT_NULL(result); /* means partition table set wrong */ + return result; +} + +static void get_chip_host(esp_flash_t* chip, spi_host_device_t* out_host_id, int* out_cs_id) +{ + spi_host_device_t host_id; + int cs_id; + if (chip == NULL) { + host_id = SPI1_HOST; + cs_id = 0; + } else { + spi_flash_hal_context_t* host_data = (spi_flash_hal_context_t*)chip->host; + host_id = spi_flash_ll_hw_get_id(host_data->spi); + cs_id = host_data->cs_num; + } + if (out_host_id) { + *out_host_id = host_id; + } + if (out_cs_id) { + *out_cs_id = cs_id; + } +} + +#if CONFIG_IDF_TARGET_ESP32 +static void setup_bus(spi_host_device_t host_id) +{ + if (host_id == SPI1_HOST) { + ESP_LOGI(TAG, "setup flash on SPI1 CS1...\n"); + //no need to initialize the bus, however the CLK may need one more output if it's on the usual place of PSRAM + esp_rom_gpio_connect_out_signal(EXTRA_SPI1_CLK_IO, SPICLK_OUT_IDX, 0, 0); + //currently the SPI bus for main flash chip is initialized through GPIO matrix + } else if (host_id == SPI2_HOST) { + ESP_LOGI(TAG, "setup flash on SPI%u (HSPI) CS0...\n", host_id + 1); + spi_bus_config_t hspi_bus_cfg = { + .mosi_io_num = HSPI_PIN_NUM_MOSI, + .miso_io_num = HSPI_PIN_NUM_MISO, + .sclk_io_num = HSPI_PIN_NUM_CLK, + .quadhd_io_num = HSPI_PIN_NUM_HD, + .quadwp_io_num = HSPI_PIN_NUM_WP, + .max_transfer_sz = 64, + }; + esp_err_t ret = spi_bus_initialize(host_id, &hspi_bus_cfg, 0); + TEST_ESP_OK(ret); + } else if (host_id == SPI3_HOST) { + ESP_LOGI(TAG, "setup flash on SPI%u (VSPI) CS0...\n", host_id + 1); + spi_bus_config_t vspi_bus_cfg = { + .mosi_io_num = VSPI_PIN_NUM_MOSI, + .miso_io_num = VSPI_PIN_NUM_MISO, + .sclk_io_num = VSPI_PIN_NUM_CLK, + .quadhd_io_num = VSPI_PIN_NUM_HD, + .quadwp_io_num = VSPI_PIN_NUM_WP, + .max_transfer_sz = 64, + }; + esp_err_t ret = spi_bus_initialize(host_id, &vspi_bus_cfg, 0); + TEST_ESP_OK(ret); + } else { + ESP_LOGE(TAG, "invalid bus"); + } +} +#else // FOR ESP32-S2, ESP32-S3, ESP32-C3 +static void setup_bus(spi_host_device_t host_id) +{ + if (host_id == SPI1_HOST) { + ESP_LOGI(TAG, "setup flash on SPI1 CS1...\n"); +#if !CONFIG_ESPTOOLPY_FLASHMODE_QIO && !CONFIG_ESPTOOLPY_FLASHMODE_QOUT + //Initialize the WP and HD pins, which are not automatically initialized on ESP32-S2. + int wp_pin = spi_periph_signal[host_id].spiwp_iomux_pin; + int hd_pin = spi_periph_signal[host_id].spihd_iomux_pin; + gpio_iomux_in(wp_pin, spi_periph_signal[host_id].spiwp_in); + gpio_iomux_out(wp_pin, spi_periph_signal[host_id].func, false); + gpio_iomux_in(hd_pin, spi_periph_signal[host_id].spihd_in); + gpio_iomux_out(hd_pin, spi_periph_signal[host_id].func, false); +#endif //CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT + //currently the SPI bus for main flash chip is initialized through GPIO matrix + } else if (host_id == SPI2_HOST) { + ESP_LOGI(TAG, "setup flash on SPI%u (FSPI) CS0...\n", host_id + 1); + spi_bus_config_t fspi_bus_cfg = { + .mosi_io_num = FSPI_PIN_NUM_MOSI, + .miso_io_num = FSPI_PIN_NUM_MISO, + .sclk_io_num = FSPI_PIN_NUM_CLK, + .quadhd_io_num = FSPI_PIN_NUM_HD, + .quadwp_io_num = FSPI_PIN_NUM_WP, + .max_transfer_sz = 64, + }; + esp_err_t ret = spi_bus_initialize(host_id, &fspi_bus_cfg, 0); + TEST_ESP_OK(ret); + } else if (host_id == SPI3_HOST) { + ESP_LOGI(TAG, "setup flash on SPI%u (HSPI) CS0...\n", host_id + 1); + spi_bus_config_t hspi_bus_cfg = { + .mosi_io_num = HSPI_PIN_NUM_MOSI, + .miso_io_num = HSPI_PIN_NUM_MISO, + .sclk_io_num = HSPI_PIN_NUM_CLK, + .quadhd_io_num = HSPI_PIN_NUM_HD, + .quadwp_io_num = HSPI_PIN_NUM_WP, + .max_transfer_sz = 64, + }; + esp_err_t ret = spi_bus_initialize(host_id, &hspi_bus_cfg, 0); + TEST_ESP_OK(ret); + + // HSPI have no multiline mode, use GPIO to pull those pins up + gpio_set_direction(HSPI_PIN_NUM_HD, GPIO_MODE_OUTPUT); + gpio_set_level(HSPI_PIN_NUM_HD, 1); + + gpio_set_direction(HSPI_PIN_NUM_WP, GPIO_MODE_OUTPUT); + gpio_set_level(HSPI_PIN_NUM_WP, 1); + } else { + ESP_LOGE(TAG, "invalid bus"); + } +} +#endif // CONFIG_IDF_TARGET_ESP32 + +static void release_bus(int host_id) +{ + //SPI1 bus can't be deinitialized + if (host_id == SPI2_HOST || host_id == SPI3_HOST) { + spi_bus_free(host_id); + } +} + +static void setup_new_chip(const flashtest_config_t* test_cfg, esp_flash_t** out_chip) +{ + //the bus should be initialized before the flash is attached to the bus + if (test_cfg->host_id == -1) { + *out_chip = NULL; + return; + } + setup_bus(test_cfg->host_id); + + esp_flash_spi_device_config_t dev_cfg = { + .host_id = test_cfg->host_id, + .io_mode = test_cfg->io_mode, + .freq_mhz = test_cfg->freq_mhz, + .cs_id = test_cfg->cs_id, + .cs_io_num = test_cfg->cs_io_num, + .input_delay_ns = test_cfg->input_delay_ns, + }; + esp_flash_t* init_chip; + esp_err_t err = spi_bus_add_flash_device(&init_chip, &dev_cfg); + TEST_ESP_OK(err); + err = esp_flash_init(init_chip); + TEST_ESP_OK(err); + *out_chip = init_chip; +} + +static void teardown_test_chip(esp_flash_t* chip) +{ + spi_host_device_t host_id; + get_chip_host(chip, &host_id, NULL); + //happen to work when chip==NULL + spi_bus_remove_flash_device(chip); + release_bus(host_id); +} + +static void flash_test_core(flash_test_func_t func, const flashtest_config_t* config) +{ + esp_flash_t* chip; + setup_new_chip(config, &chip); + + uint32_t size; + esp_err_t err = esp_flash_get_size(chip, &size); + TEST_ESP_OK(err); + ESP_LOGI(TAG, "Flash size: 0x%08lX", size); + + const esp_partition_t* test_part = get_test_data_partition(); + TEST_ASSERT_NOT_EQUAL(NULL, test_part->flash_chip); + + esp_partition_t part = *test_part; + part.flash_chip = chip; + + ESP_LOGI(TAG, "Testing chip %p, address 0x%08lX...", part.flash_chip, part.address); + (*func)(&part); + + // For flash with size over 16MB, add one extra round of test for the 32-bit address area + if (size > MAX_ADDR_24BIT) { + part.address = 0x1030000; + part.size = 0x0010000; + ESP_LOGI(TAG, "Testing chip %p, address 0x%08lX...", part.flash_chip, part.address); + (*func)(&part); + } + + teardown_test_chip(chip); +} + +static void flash_test_func(flash_test_func_t func, int test_num) +{ + esp_log_level_set("gpio", ESP_LOG_NONE); + for (int i = 0; i < test_num; i++) { + ESP_LOGI(TAG, "Testing config %u/%u", i+1, test_num); + flash_test_core(func, &config_list[i]); + } + ESP_LOGI(TAG, "Completed %u configs", test_num); +} + +/* ---------- Test code start ------------*/ + +static void test_metadata(const esp_partition_t* part) +{ + esp_flash_t* chip = part->flash_chip; + uint32_t id, size; + TEST_ESP_OK(esp_flash_read_id(chip, &id)); + TEST_ESP_OK(esp_flash_get_size(chip, &size)); + printf("Flash ID %08lx detected size %" PRIu32 "bytes\n", id, size); +} + +TEST_CASE_FLASH("SPI flash metadata functions", test_metadata); +TEST_CASE_MULTI_FLASH("SPI flash metadata functions", test_metadata); + +static uint32_t erase_test_region(const esp_partition_t *part, int num_sectors) +{ + esp_flash_t* chip = part->flash_chip; + uint32_t offs = part->address; + + /* chip should be initialised */ + TEST_ASSERT(esp_flash_default_chip != NULL + && esp_flash_chip_driver_initialized(esp_flash_default_chip)); + + TEST_ASSERT(num_sectors * 4096 <= part->size); + + bzero(sector_buf, sizeof(sector_buf)); + + printf("Erase @ 0x%lx...\n", offs); + TEST_ASSERT_EQUAL_HEX32(ESP_OK, esp_flash_erase_region(chip, offs, num_sectors * 4096) ); + + printf("Verify erased...\n"); + for (int i = 0; i < num_sectors; i++) { + TEST_ASSERT_EQUAL_HEX32(ESP_OK, esp_flash_read(chip, sector_buf, offs + i * 4096, sizeof(sector_buf))); + + printf("Buffer starts 0x%02x 0x%02x 0x%02x 0x%02x\n", sector_buf[0], sector_buf[1], sector_buf[2], sector_buf[3]); + for (int i = 0; i < sizeof(sector_buf); i++) { + TEST_ASSERT_EQUAL_HEX8(0xFF, sector_buf[i]); + } + } + + return offs; +} + +void test_simple_read_write(const esp_partition_t* part) +{ + esp_flash_t* chip = part->flash_chip; + uint32_t offs = erase_test_region(part, 1); + + const int test_seed = 778; + srand(test_seed); + for (int i = 0 ; i < sizeof(sector_buf); i++) { + sector_buf[i] = rand(); + } + + printf("Write %p...\n", (void *)offs); + TEST_ASSERT_EQUAL(ESP_OK, esp_flash_write(chip, sector_buf, offs, sizeof(sector_buf)) ); + + bzero(sector_buf, sizeof(sector_buf)); + + printf("Read back...\n"); + TEST_ASSERT_EQUAL(ESP_OK, esp_flash_read(chip, sector_buf, offs, sizeof(sector_buf)) ); + + printf("Buffer starts 0x%02x 0x%02x 0x%02x 0x%02x\n", sector_buf[0], sector_buf[1], sector_buf[2], sector_buf[3]); + + srand(test_seed); + for (int i = 0; i < sizeof(sector_buf); i++) { + uint8_t data = rand(); + TEST_ASSERT_EQUAL_HEX8(data, sector_buf[i]); + } +} + +TEST_CASE_FLASH("SPI flash simple read/write", test_simple_read_write); +TEST_CASE_MULTI_FLASH("SPI flash simple read/write", test_simple_read_write); + +void test_unaligned_read_write(const esp_partition_t* part) +{ + esp_flash_t* chip = part->flash_chip; + uint32_t offs = erase_test_region(part, 2); + + const char *msg = "i am a message"; + TEST_ASSERT(strlen(msg) + 1 % 4 != 0); + TEST_ASSERT_EQUAL(ESP_OK, esp_flash_write(chip, msg, offs + 1, strlen(msg) + 1) ); + + char buf[strlen(msg) + 1]; + + memset(buf, 0xEE, sizeof(buf)); + + TEST_ASSERT_EQUAL(ESP_OK, esp_flash_read(chip, buf, offs + 1, strlen(msg) + 1) ); + TEST_ASSERT_EQUAL_STRING_LEN(msg, buf, strlen(msg)); + TEST_ASSERT(memcmp(buf, msg, strlen(msg) + 1) == 0); +} + +TEST_CASE_FLASH("SPI flash unaligned read/write", test_unaligned_read_write); +TEST_CASE_MULTI_FLASH("SPI flash unaligned read/write", test_unaligned_read_write); + +void test_single_read_write(const esp_partition_t* part) +{ + esp_flash_t* chip = part->flash_chip; + uint32_t offs = erase_test_region(part, 2); + + const int seed = 699; + srand(seed); + for (unsigned v = 0; v < 512; v++) { + uint32_t data = rand(); + TEST_ASSERT_EQUAL_HEX(ESP_OK, esp_flash_write(chip, &data, offs + v, 1) ); + } + + srand(seed); + for (unsigned v = 0; v < 512; v++) { + uint8_t readback; + uint32_t data = rand(); + TEST_ASSERT_EQUAL_HEX(ESP_OK, esp_flash_read(chip, &readback, offs + v, 1) ); + TEST_ASSERT_EQUAL_HEX8(data, readback); + } +} + +TEST_CASE_FLASH("SPI flash single byte reads/writes", test_single_read_write); +TEST_CASE_MULTI_FLASH("SPI flash single byte reads/writes", test_single_read_write); + + +/* this test is notable because it generates a lot of unaligned reads/writes, + and also reads/writes across both a sector boundary & many page boundaries. +*/ +void test_three_byte_read_write(const esp_partition_t* part) +{ + esp_flash_t* chip = part->flash_chip; + uint32_t offs = erase_test_region(part, 2); + + const int seed = 700; + esp_rom_printf("offs:%X\n", offs); + + srand(seed); + for (uint32_t v = 0; v < 86; v++) { + uint32_t data = rand(); + TEST_ASSERT_EQUAL(ESP_OK, esp_flash_write(chip, &data, offs + 3 * v, 3) ); + } + + srand(seed); + for (uint32_t v = 0; v < 1; v++) { + uint32_t readback; + uint32_t data = rand(); + TEST_ASSERT_EQUAL(ESP_OK, esp_flash_read(chip, &readback, offs + 3 * v, 3) ); + TEST_ASSERT_EQUAL_HEX32(data & 0xFFFFFF, readback & 0xFFFFFF); + } +} + +TEST_CASE_FLASH("SPI flash three byte reads/writes", test_three_byte_read_write); +TEST_CASE_MULTI_FLASH("SPI flash three byte reads/writes", test_three_byte_read_write); + +void test_erase_large_region(const esp_partition_t *part) +{ + esp_flash_t* chip = part->flash_chip; + + /* Write some noise at the start and the end of the region */ + const char *ohai = "OHAI"; + uint32_t readback; + TEST_ASSERT_EQUAL(ESP_OK, esp_flash_write(chip, ohai, part->address, 5)); + TEST_ASSERT_EQUAL(ESP_OK, esp_flash_write(chip, ohai, part->address + part->size - 5, 5)); + + /* sanity check what we just wrote. since the partition may haven't been erased, we only check the part which is written to 0. */ + uint32_t written_data = *((const uint32_t *)ohai); + TEST_ASSERT_EQUAL(ESP_OK, esp_flash_read(chip, &readback, part->address + part->size - 5, 4)); + TEST_ASSERT_EQUAL_HEX32(0, readback & (~written_data)); + TEST_ASSERT_EQUAL(ESP_OK, esp_flash_read(chip, &readback, part->address, 4)); + TEST_ASSERT_EQUAL_HEX32(0, readback & (~written_data)); + + /* Erase zero bytes, check that nothing got erased */ + TEST_ASSERT_EQUAL(ESP_OK, esp_flash_erase_region(chip, part->address, 0)); + TEST_ASSERT_EQUAL(ESP_OK, esp_flash_read(chip, &readback, part->address + part->size - 5, 4)); + TEST_ASSERT_EQUAL_HEX32(0, readback & (~written_data)); + TEST_ASSERT_EQUAL(ESP_OK, esp_flash_read(chip, &readback, part->address, 4)); + TEST_ASSERT_EQUAL_HEX32(0, readback & (~written_data)); + + /* Erase whole region */ + TEST_ASSERT_EQUAL(ESP_OK, esp_flash_erase_region(chip, part->address, part->size)); + + /* ensure both areas we wrote are now all-FFs */ + TEST_ASSERT_EQUAL(ESP_OK, esp_flash_read(chip, &readback, part->address, 4)); + TEST_ASSERT_EQUAL_HEX32(0xFFFFFFFF, readback); + + TEST_ASSERT_EQUAL(ESP_OK, esp_flash_read(chip, &readback, part->address + part->size - 5, 4)); + TEST_ASSERT_EQUAL_HEX32(0xFFFFFFFF, readback); +} + +TEST_CASE_FLASH("SPI flash erase large region", test_erase_large_region); +TEST_CASE_MULTI_FLASH("SPI flash erase large region", test_erase_large_region); + +#if CONFIG_SPI_FLASH_AUTO_SUSPEND +void esp_test_for_suspend(void) +{ + /*clear content in cache*/ +#if !CONFIG_IDF_TARGET_ESP32C3 + Cache_Invalidate_DCache_All(); +#endif + Cache_Invalidate_ICache_All(); + ESP_LOGI(TAG, "suspend test begins:"); + printf("run into test suspend function\n"); + printf("print something when flash is erasing:\n"); + printf("aaaaa bbbbb zzzzz fffff qqqqq ccccc\n"); +} + +static volatile bool task_erase_end, task_suspend_end = false; +void task_erase_large_region(void *arg) +{ + esp_partition_t *part = (esp_partition_t *)arg; + test_erase_large_region(part); + task_erase_end = true; + vTaskDelete(NULL); +} + +void task_request_suspend(void *arg) +{ + vTaskDelay(2); + ESP_LOGI(TAG, "flash go into suspend"); + esp_test_for_suspend(); + task_suspend_end = true; + vTaskDelete(NULL); +} + +static void test_flash_suspend_resume(const esp_partition_t* part) +{ + xTaskCreatePinnedToCore(task_request_suspend, "suspend", 2048, (void *)"test_for_suspend", UNITY_FREERTOS_PRIORITY + 3, NULL, 0); + xTaskCreatePinnedToCore(task_erase_large_region, "test", 2048, (void *)part, UNITY_FREERTOS_PRIORITY + 2, NULL, 0); + while (!task_erase_end || !task_suspend_end) { + } + vTaskDelay(200); +} + +TEST_CASE("SPI flash suspend and resume test", "[esp_flash][test_env=UT_T1_Flash_Suspend]") +{ + flash_test_func(test_flash_suspend_resume, 1 /* first index reserved for main flash */ ); +} + +#endif //CONFIG_SPI_FLASH_AUTO_SUSPEND + +static void test_write_protection(const esp_partition_t* part) +{ + esp_flash_t* chip = part->flash_chip; + + bool wp = true; + esp_err_t ret = ESP_OK; + ret = esp_flash_get_chip_write_protect(chip, &wp); + TEST_ESP_OK(ret); + + for (int i = 0; i < 4; i ++) { + bool wp_write = !wp; + ret = esp_flash_set_chip_write_protect(chip, wp_write); + TEST_ESP_OK(ret); + + bool wp_read; + ret = esp_flash_get_chip_write_protect(chip, &wp_read); + TEST_ESP_OK(ret); + TEST_ASSERT(wp_read == wp_write); + wp = wp_read; + } +} + +TEST_CASE_FLASH("Test esp_flash can enable/disable write protetion", test_write_protection); +TEST_CASE_MULTI_FLASH("Test esp_flash can enable/disable write protetion", test_write_protection); + +static const uint8_t large_const_buffer[16400] = { + 203, // first byte + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, + 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, + [50 ... 99] = 2, + [1600 ... 2000] = 3, + [8000 ... 9000] = 77, + [15000 ... 16398] = 8, + 43 // last byte +}; + +static void test_write_large_buffer(const esp_partition_t *part, const uint8_t *source, size_t length); +static void write_large_buffer(const esp_partition_t *part, const uint8_t *source, size_t length); +static void read_and_check(const esp_partition_t *part, const uint8_t *source, size_t length); + +// Internal functions for testing, from esp_flash_api.c +#if !CONFIG_ESPTOOLPY_OCT_FLASH +esp_err_t esp_flash_set_io_mode(esp_flash_t* chip, bool qe); +esp_err_t esp_flash_get_io_mode(esp_flash_t* chip, bool* qe); +esp_err_t esp_flash_read_chip_id(esp_flash_t* chip, uint32_t* flash_id); +esp_err_t spi_flash_chip_mxic_probe(esp_flash_t *chip, uint32_t flash_id); + +static bool is_winbond_chip(esp_flash_t* chip) +{ + uint32_t flash_id; + esp_err_t ret = esp_flash_read_chip_id(chip, &flash_id); + TEST_ESP_OK(ret); + if ((flash_id >> 16) == 0xEF) { + return true; + } else { + return false; + } +} + +static bool is_mxic_chip(esp_flash_t* chip) +{ + uint32_t flash_id; + esp_err_t ret = esp_flash_read_chip_id(chip, &flash_id); + TEST_ESP_OK(ret); + return (spi_flash_chip_mxic_probe(chip, flash_id)==ESP_OK); +} + +IRAM_ATTR NOINLINE_ATTR static void test_toggle_qe(const esp_partition_t* part) +{ + esp_flash_t* chip = part->flash_chip; + + bool qe; + if (chip == NULL) { + chip = esp_flash_default_chip; + } + esp_flash_io_mode_t io_mode_before = chip->read_mode; + esp_err_t ret = esp_flash_get_io_mode(chip, &qe); + TEST_ESP_OK(ret); + + bool allow_failure = is_winbond_chip(chip) || is_mxic_chip(chip); + + for (int i = 0; i < 4; i ++) { + esp_rom_printf(DRAM_STR("write qe: %" PRIu32 "->%" PRIu32 "\n"), qe, !qe); + qe = !qe; + chip->read_mode = qe? SPI_FLASH_QOUT: SPI_FLASH_SLOWRD; + ret = esp_flash_set_io_mode(chip, qe); + if (allow_failure && !qe && ret == ESP_ERR_FLASH_NO_RESPONSE) { + //allows clear qe failure for Winbond chips + ret = ESP_OK; + } + TEST_ESP_OK(ret); + + bool qe_read; + ret = esp_flash_get_io_mode(chip, &qe_read); + TEST_ESP_OK(ret); + ESP_LOGD(TAG, "qe read: %u", qe_read); + if (!qe && qe_read) { + if (allow_failure) { + ESP_LOGW(TAG, "cannot clear QE bit for known permanent QE (Winbond or MXIC) chips."); + } else { + ESP_LOGE(TAG, "cannot clear QE bit, please make sure force clearing QE option is enabled in `spi_flash_common_set_io_mode`, and this chip is not a permanent QE one."); + } + chip->read_mode = io_mode_before; + return; + } + TEST_ASSERT_EQUAL(qe, qe_read); + } + //restore the io_mode after test + chip->read_mode = io_mode_before; +} + +// These tests show whether the QE is permanent or not for the chip tested. +// To test the behaviour of a new SPI flash chip, enable force_check flag in generic driver +// `spi_flash_common_set_io_mode` and then run this test. +TEST_CASE_FLASH_IGNORE("Test esp_flash_write can toggle QE bit", test_toggle_qe); +TEST_CASE_MULTI_FLASH_IGNORE("Test esp_flash_write can toggle QE bit", test_toggle_qe); +#endif //CONFIG_ESPTOOLPY_OCT_FLASH + +// This table could be chip specific in the future. +uint8_t flash_frequency_table[6] = {5, 10, 20, 26, 40, 80}; +#define TEST_FLASH_SPEED_MIN 5 +void test_permutations_part(const flashtest_config_t* config, esp_partition_t* part, void* source_buf, size_t length) +{ + int clock_index = 0; + if (config->host_id != -1) { + while (clock_index < sizeof(flash_frequency_table)/sizeof(uint8_t)) { + uint8_t speed = flash_frequency_table[clock_index]; + //test io_mode in the inner loop to test QE set/clear function, since + //the io mode will switch frequently. + esp_flash_io_mode_t io_mode = SPI_FLASH_READ_MODE_MIN; + while (io_mode != SPI_FLASH_QIO + 1) { + if (io_mode > SPI_FLASH_FASTRD && + !SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(config->host_id)) { + io_mode++; + continue; + } + + esp_flash_t* chip; + flashtest_config_t temp_config = *config; + temp_config.io_mode = io_mode; + temp_config.freq_mhz = flash_frequency_table[clock_index]; + setup_new_chip(&temp_config, &chip); + ESP_LOGI(TAG, "test flash io mode: %u, speed: %u", io_mode, speed); + + part->flash_chip = chip; + read_and_check(part, source_buf, length); + teardown_test_chip(chip); + + io_mode++; + } + clock_index++; + } + } else { + //test main flash + part->flash_chip = NULL; + read_and_check(part, source_buf, length); + } +} + +void test_permutations_chip(const flashtest_config_t* config) +{ + esp_log_level_set("gpio", ESP_LOG_NONE); + esp_flash_t* chip; + flashtest_config_t temp_config = *config; + // Use the lowest speed to read configs, data and write data to make sure success + temp_config.io_mode = SPI_FLASH_READ_MODE_MIN; + temp_config.freq_mhz = TEST_FLASH_SPEED_MIN; + setup_new_chip(&temp_config, &chip); + + //Get size to determine whether to test one extra partition + uint32_t size; + esp_err_t err = esp_flash_get_size(chip, &size); + TEST_ESP_OK(err); + ESP_LOGI(TAG, "Flash size: 0x%08lX", size); + bool addr_32bit = (size > MAX_ADDR_24BIT); + + // Get test partition, and locate temporary partitions according to the default one + const esp_partition_t* test_part = get_test_data_partition(); + const int length = sizeof(large_const_buffer); + TEST_ASSERT(test_part->size > length + 2 + SPI_FLASH_SEC_SIZE); + + esp_partition_t part[2] = {}; + part[0] = *test_part; + part[0].flash_chip = chip; + // For flash with size over 16MB, add one extra round of test for the 32-bit address area + if (addr_32bit) { + part[1] = *test_part; + part[1].flash_chip = chip; + part[1].address = 0x1030000; + part[1].size = 0x0010000; + } else { + part[1].size = 0; + } + + // Prepare test data and write to the specified region + uint8_t *source_buf = malloc(length); + TEST_ASSERT_NOT_NULL(source_buf); + srand(778); + for (int i = 0; i < length; i++) { + source_buf[i] = rand(); + } + + for (int i = 0; i < 2; i++) { + if (part[i].size == 0) continue; + write_large_buffer(&part[i], source_buf, length); + } + + teardown_test_chip(chip); + + for (int i = 0; i < 2; i++) { + if (part[i].size == 0) continue; + + part[i].flash_chip = (esp_flash_t*)-1; + ESP_LOGI(TAG, "Testing address 0x%08lX...", part[i].address); + test_permutations_part(config, &part[i], source_buf, length); + } + + free(source_buf); +} + +TEST_CASE("SPI flash test reading with all speed/mode permutations", "[esp_flash]") +{ + test_permutations_chip(&config_list[0]); +} + +#ifndef CONFIG_SPIRAM +TEST_CASE("SPI flash test reading with all speed/mode permutations, 3 chips", "[esp_flash_multi][test_env=UT_T1_ESP_FLASH]") +{ + for (int i = 0; i < TEST_CONFIG_NUM; i++) { + test_permutations_chip(&config_list[i]); + } +} +#endif + + +static void test_write_large_const_buffer(const esp_partition_t* part) +{ + test_write_large_buffer(part, large_const_buffer, sizeof(large_const_buffer)); +} + +TEST_CASE_FLASH("Test esp_flash_write large const buffer", test_write_large_const_buffer); +TEST_CASE_MULTI_FLASH("Test esp_flash_write large const buffer", test_write_large_const_buffer); + +static void test_write_large_ram_buffer(const esp_partition_t* part) +{ + // buffer in RAM + uint8_t *source_buf = malloc(sizeof(large_const_buffer)); + TEST_ASSERT_NOT_NULL(source_buf); + memcpy(source_buf, large_const_buffer, sizeof(large_const_buffer)); + test_write_large_buffer(part, source_buf, sizeof(large_const_buffer)); + free(source_buf); +} + +TEST_CASE_FLASH("Test esp_flash_write large RAM buffer", test_write_large_ram_buffer); +TEST_CASE_MULTI_FLASH("Test esp_flash_write large RAM buffer", test_write_large_ram_buffer); + +static void write_large_buffer(const esp_partition_t *part, const uint8_t *source, size_t length) +{ + esp_flash_t* chip = part->flash_chip; + + printf("Writing chip %p %p, %u bytes from source %p\n", chip, (void*)part->address, length, source); + ESP_ERROR_CHECK( esp_flash_erase_region(chip, part->address, (length + SPI_FLASH_SEC_SIZE) & ~(SPI_FLASH_SEC_SIZE - 1)) ); + + // note writing to unaligned address + ESP_ERROR_CHECK( esp_flash_write(chip, source, part->address + 1, length) ); +} + +static void read_and_check(const esp_partition_t *part, const uint8_t *source, size_t length) +{ + esp_flash_t* chip = part->flash_chip; + printf("Checking chip %p 0x%08lX, %u bytes\n", chip, part->address, length); + uint8_t *buf = malloc(length); + TEST_ASSERT_NOT_NULL(buf); + ESP_ERROR_CHECK( esp_flash_read(chip, buf, part->address + 1, length) ); + TEST_ASSERT_EQUAL_HEX8_ARRAY(source, buf, length); + free(buf); + + // check nothing was written at beginning or end + uint8_t ends[8]; + + ESP_ERROR_CHECK( esp_flash_read(chip, ends, part->address, sizeof(ends)) ); + TEST_ASSERT_EQUAL_HEX8(0xFF, ends[0]); + TEST_ASSERT_EQUAL_HEX8(source[0], ends[1]); + + ESP_ERROR_CHECK( esp_flash_read(chip, ends, part->address + length, sizeof(ends)) ); + + TEST_ASSERT_EQUAL_HEX8(source[length - 1], ends[0]); + TEST_ASSERT_EQUAL_HEX8(0xFF, ends[1]); + TEST_ASSERT_EQUAL_HEX8(0xFF, ends[2]); + TEST_ASSERT_EQUAL_HEX8(0xFF, ends[3]); +} + +static void test_write_large_buffer(const esp_partition_t* part, const uint8_t *source, size_t length) +{ + TEST_ASSERT(part->size > length + 2 + SPI_FLASH_SEC_SIZE); + + write_large_buffer(part, source, length); + read_and_check(part, source, length); +} + +#ifdef CONFIG_SPIRAM_USE_MALLOC + +/* Utility: Read into a small internal RAM buffer using esp_flash_read() and compare what + we read with 'buffer' */ +static void s_test_compare_flash_contents_small_reads(esp_flash_t *chip, const uint8_t *buffer, size_t offs, size_t len) +{ + const size_t INTERNAL_BUF_SZ = 1024; // Should fit in internal RAM + uint8_t *ibuf = heap_caps_malloc(INTERNAL_BUF_SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + TEST_ASSERT_NOT_NULL(ibuf); + + for (int i = 0; i < len; i += INTERNAL_BUF_SZ) { + size_t to_read = MIN(INTERNAL_BUF_SZ, len - i); + ESP_ERROR_CHECK( esp_flash_read(chip, ibuf, offs + i, to_read) ); + TEST_ASSERT_EQUAL_HEX8_ARRAY(buffer + i, ibuf, to_read); + } + + free(ibuf); +} + +static void test_flash_read_large_psram_buffer(const esp_partition_t *part) +{ + esp_flash_t* chip = part->flash_chip; + const size_t BUF_SZ = 256 * 1024; // Too large for internal RAM + const size_t TEST_OFFS = 0x1000; // Can be any offset, really + + uint8_t *buf = heap_caps_malloc(BUF_SZ, MALLOC_CAP_8BIT|MALLOC_CAP_SPIRAM); + TEST_ASSERT_NOT_NULL(buf); + + ESP_ERROR_CHECK( esp_flash_read(chip, buf, TEST_OFFS, BUF_SZ) ); + + // Read back the same into smaller internal memory buffer and check it all matches + s_test_compare_flash_contents_small_reads(chip, buf, TEST_OFFS, BUF_SZ); + + free(buf); +} + +TEST_CASE_FLASH("esp_flash_read large PSRAM buffer", test_flash_read_large_psram_buffer); + + +/* similar to above test, but perform it under memory pressure */ +static void test_flash_read_large_psram_buffer_low_internal_mem(const esp_partition_t *part) +{ + esp_flash_t* chip = part->flash_chip; + const size_t BUF_SZ = 256 * 1024; // Too large for internal RAM + const size_t REMAINING_INTERNAL = 1024; // Exhaust internal memory until maximum free block is less than this + const size_t TEST_OFFS = 0x8000; + + /* Exhaust the available free internal memory */ + test_utils_exhaust_memory_rec erec = test_utils_exhaust_memory(MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT, REMAINING_INTERNAL); + + uint8_t *buf = heap_caps_malloc(BUF_SZ, MALLOC_CAP_8BIT|MALLOC_CAP_SPIRAM); + TEST_ASSERT_NOT_NULL(buf); + + /* Calling esp_flash_read() here will need to allocate a small internal buffer, + so check it works. */ + ESP_ERROR_CHECK( esp_flash_read(chip, buf, TEST_OFFS, BUF_SZ) ); + + test_utils_free_exhausted_memory(erec); + + // Read back the same into smaller internal memory buffer and check it all matches + s_test_compare_flash_contents_small_reads(chip, buf, TEST_OFFS, BUF_SZ); + + free(buf); +} + +TEST_CASE_FLASH("esp_flash_read large PSRAM buffer low memory", test_flash_read_large_psram_buffer_low_internal_mem); + + +#endif diff --git a/components/spi_flash/test_apps/esp_flash/partitions.csv b/components/spi_flash/test_apps/esp_flash/partitions.csv new file mode 100644 index 0000000000..c941d8f4f1 --- /dev/null +++ b/components/spi_flash/test_apps/esp_flash/partitions.csv @@ -0,0 +1,5 @@ +# Name, Type, SubType, Offset, Size, Flags +# Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap +nvs, data, nvs, 0x9000, 0x6000, +factory, 0, 0, 0x10000, 1M +flash_test, data, fat, , 528K diff --git a/components/spi_flash/test_apps/esp_flash/pytest_esp_flash.py b/components/spi_flash/test_apps/esp_flash/pytest_esp_flash.py new file mode 100644 index 0000000000..1100b61fad --- /dev/null +++ b/components/spi_flash/test_apps/esp_flash/pytest_esp_flash.py @@ -0,0 +1,61 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 + +import pytest +from pytest_embedded import Dut + + +@pytest.mark.esp32 +@pytest.mark.esp32s2 +@pytest.mark.esp32s3 +@pytest.mark.esp32c3 +@pytest.mark.esp32c2 +@pytest.mark.generic +@pytest.mark.parametrize( + 'config', + [ + 'release', + 'flash_qio', + ], + indirect=True, +) +def test_esp_flash(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('[esp_flash]') + dut.expect_unity_test_output() + + +@pytest.mark.esp32s3 +@pytest.mark.esp32c3 +@pytest.mark.esp32c2 +@pytest.mark.generic +@pytest.mark.parametrize( + 'config', + [ + 'rom_impl', + ], + indirect=True, +) +def test_esp_flash_rom(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('[esp_flash]') + dut.expect_unity_test_output() + + +@pytest.mark.esp32 +@pytest.mark.esp32s2 +@pytest.mark.esp32s3 +@pytest.mark.esp32c3 +@pytest.mark.esp32c2 +@pytest.mark.flash_mutli +@pytest.mark.parametrize( + 'config', + [ + 'release', + ], + indirect=True, +) +def test_esp_flash_multi(dut: Dut) -> None: + dut.expect_exact('Press ENTER to see the list of tests') + dut.write('[esp_flash_multi]') + dut.expect_unity_test_output() diff --git a/components/spi_flash/test_apps/esp_flash/sdkconfig.ci.flash_qio b/components/spi_flash/test_apps/esp_flash/sdkconfig.ci.flash_qio new file mode 100644 index 0000000000..45d97b3c1d --- /dev/null +++ b/components/spi_flash/test_apps/esp_flash/sdkconfig.ci.flash_qio @@ -0,0 +1,4 @@ +CONFIG_ESP_TASK_WDT=n +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" +CONFIG_ESPTOOLPY_FLASHMODE_QIO=y diff --git a/components/spi_flash/test_apps/esp_flash/sdkconfig.ci.release b/components/spi_flash/test_apps/esp_flash/sdkconfig.ci.release new file mode 100644 index 0000000000..9a2221effe --- /dev/null +++ b/components/spi_flash/test_apps/esp_flash/sdkconfig.ci.release @@ -0,0 +1,7 @@ +CONFIG_ESP_TASK_WDT=n +CONFIG_FREERTOS_USE_TICKLESS_IDLE=y +CONFIG_COMPILER_OPTIMIZATION_SIZE=y +CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" diff --git a/components/spi_flash/test_apps/esp_flash/sdkconfig.ci.rom_impl b/components/spi_flash/test_apps/esp_flash/sdkconfig.ci.rom_impl new file mode 100644 index 0000000000..1f73cb4152 --- /dev/null +++ b/components/spi_flash/test_apps/esp_flash/sdkconfig.ci.rom_impl @@ -0,0 +1,4 @@ +CONFIG_ESP_TASK_WDT=n +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" +CONFIG_SPI_FLASH_ROM_IMPL=y diff --git a/components/spi_flash/test_apps/esp_flash/sdkconfig.defaults b/components/spi_flash/test_apps/esp_flash/sdkconfig.defaults new file mode 100644 index 0000000000..e58745b57a --- /dev/null +++ b/components/spi_flash/test_apps/esp_flash/sdkconfig.defaults @@ -0,0 +1,3 @@ +CONFIG_ESP_TASK_WDT=n +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" diff --git a/components/spiffs/.build-test-rules.yml b/components/spiffs/.build-test-rules.yml new file mode 100644 index 0000000000..eec002ed8a --- /dev/null +++ b/components/spiffs/.build-test-rules.yml @@ -0,0 +1,4 @@ +components/spiffs/host_test: + enable: + - if: IDF_TARGET == "linux" + reason: only test on linux diff --git a/components/spiffs/CMakeLists.txt b/components/spiffs/CMakeLists.txt index a5e032dc2c..1b8817c244 100644 --- a/components/spiffs/CMakeLists.txt +++ b/components/spiffs/CMakeLists.txt @@ -1,14 +1,22 @@ -idf_component_register(SRCS "esp_spiffs.c" - "spiffs_api.c" - "spiffs/src/spiffs_cache.c" - "spiffs/src/spiffs_check.c" - "spiffs/src/spiffs_gc.c" - "spiffs/src/spiffs_hydrogen.c" - "spiffs/src/spiffs_nucleus.c" - INCLUDE_DIRS "include" - PRIV_INCLUDE_DIRS "." "spiffs/src" - REQUIRES spi_flash - PRIV_REQUIRES bootloader_support esptool_py vfs) +idf_build_get_property(target IDF_TARGET) + +list(APPEND srcs "spiffs_api.c" + "spiffs/src/spiffs_cache.c" + "spiffs/src/spiffs_check.c" + "spiffs/src/spiffs_gc.c" + "spiffs/src/spiffs_hydrogen.c" + "spiffs/src/spiffs_nucleus.c") + +if(NOT ${target} STREQUAL "linux") + list(APPEND pr bootloader_support esptool_py vfs) + list(APPEND srcs "esp_spiffs.c") +endif() + +idf_component_register(SRCS ${srcs} + INCLUDE_DIRS "include" + PRIV_INCLUDE_DIRS "." "spiffs/src" + REQUIRES spi_flash + PRIV_REQUIRES ${pr}) if(CMAKE_C_COMPILER_ID MATCHES "GNU") set_source_files_properties(spiffs/src/spiffs_nucleus.c PROPERTIES COMPILE_FLAGS -Wno-stringop-truncation) diff --git a/components/spiffs/esp_spiffs.c b/components/spiffs/esp_spiffs.c index aecd8f4184..56654786bb 100644 --- a/components/spiffs/esp_spiffs.c +++ b/components/spiffs/esp_spiffs.c @@ -37,6 +37,9 @@ _Static_assert(CONFIG_SPIFFS_META_LENGTH >= sizeof(spiffs_time_t), "SPIFFS_META_LENGTH size should be >= sizeof(spiffs_time_t)"); #endif //CONFIG_SPIFFS_USE_MTIME +_Static_assert(ESP_SPIFFS_PATH_MAX == ESP_VFS_PATH_MAX, + "SPIFFS max path length has to be aligned with the VFS max path length"); + /** * @brief SPIFFS DIR structure */ diff --git a/components/spiffs/host_test/CMakeLists.txt b/components/spiffs/host_test/CMakeLists.txt new file mode 100644 index 0000000000..03f7125aed --- /dev/null +++ b/components/spiffs/host_test/CMakeLists.txt @@ -0,0 +1,25 @@ +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +set(COMPONENTS main) +# Freertos is included via common components, however, currently only the mock component is compatible with linux +# target. +list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/mocks/freertos/") + +project(host_test_spiffs) + +# Custom procedure to build/clean image.bin +add_custom_target(image.bin) + +# Expand image.bin to the same size as "spiffs" partition in partition_table.csv - 2*1024*1024 = 2097152 = 2M +add_custom_command( + TARGET image.bin + POST_BUILD + COMMAND python ../../spiffsgen.py 2097152 ../../spiffs ../image.bin +) + +set_property( + DIRECTORY + APPEND PROPERTY ADDITIONAL_CLEAN_FILES "../image.bin") + +add_dependencies(host_test_spiffs.elf partition-table image.bin) diff --git a/components/spiffs/host_test/README.md b/components/spiffs/host_test/README.md new file mode 100644 index 0000000000..dc6f6df5fd --- /dev/null +++ b/components/spiffs/host_test/README.md @@ -0,0 +1,17 @@ +| Supported Targets | Linux | +| ----------------- | ----- | + +This is a test project for spiffs-related APIs on Linux target (CONFIG_IDF_TARGET_LINUX). + +# Build +Source the IDF environment as usual. + +Once this is done, build the application: +```bash +idf.py build +``` + +# Run +```bash +build/host_test_spiffs.elf +``` diff --git a/components/spiffs/host_test/main/CMakeLists.txt b/components/spiffs/host_test/main/CMakeLists.txt new file mode 100644 index 0000000000..544f56e7fe --- /dev/null +++ b/components/spiffs/host_test/main/CMakeLists.txt @@ -0,0 +1,3 @@ +idf_component_register(SRCS "host_test_spiffs.c" + PRIV_INCLUDE_DIRS "../.." "../../spiffs/src" + REQUIRES spiffs unity) diff --git a/components/spiffs/test_spiffs_host/test_spiffs.cpp b/components/spiffs/host_test/main/host_test_spiffs.c similarity index 63% rename from components/spiffs/test_spiffs_host/test_spiffs.cpp rename to components/spiffs/host_test/main/host_test_spiffs.c index 85961b6059..33845f9fe2 100644 --- a/components/spiffs/test_spiffs_host/test_spiffs.cpp +++ b/components/spiffs/host_test/main/host_test_spiffs.c @@ -14,47 +14,64 @@ #include #include +#include "Mockqueue.h" + #include "esp_partition.h" #include "spiffs.h" #include "spiffs_nucleus.h" #include "spiffs_api.h" -#include "catch.hpp" +#include "unity.h" +#include "unity_fixture.h" -extern "C" void _spi_flash_init(const char* chip_size, size_t block_size, size_t sector_size, size_t page_size, const char* partition_bin); +TEST_GROUP(spiffs); + +TEST_SETUP(spiffs) +{ + // CMock init for spiffs xSemaphore* use + xQueueSemaphoreTake_IgnoreAndReturn(0); + xQueueGenericSend_IgnoreAndReturn(0); +} + +TEST_TEAR_DOWN(spiffs) +{ +} static void init_spiffs(spiffs *fs, uint32_t max_files) { - spiffs_config cfg; + spiffs_config cfg = {}; s32_t spiffs_res; + u32_t flash_sector_size; const esp_partition_t *partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_SPIFFS, "storage"); - REQUIRE(partition); + TEST_ASSERT_NOT_NULL(partition); // Configure objects needed by SPIFFS - esp_spiffs_t *user_data = (esp_spiffs_t*) calloc(1, sizeof(*user_data)); + esp_spiffs_t *user_data = (esp_spiffs_t *) calloc(1, sizeof(*user_data)); user_data->partition = partition; - fs->user_data = (void*)user_data; + fs->user_data = (void *)user_data; + + flash_sector_size = 4096; cfg.hal_erase_f = spiffs_api_erase; cfg.hal_read_f = spiffs_api_read; cfg.hal_write_f = spiffs_api_write; - cfg.log_block_size = CONFIG_WL_SECTOR_SIZE; + cfg.log_block_size = flash_sector_size; cfg.log_page_size = CONFIG_SPIFFS_PAGE_SIZE; cfg.phys_addr = 0; - cfg.phys_erase_block = CONFIG_WL_SECTOR_SIZE; + cfg.phys_erase_block = flash_sector_size; cfg.phys_size = partition->size; uint32_t work_sz = cfg.log_page_size * 2; - uint8_t *work = (uint8_t*) malloc(work_sz); + uint8_t *work = (uint8_t *) malloc(work_sz); uint32_t fds_sz = max_files * sizeof(spiffs_fd); - uint8_t *fds = (uint8_t*) malloc(fds_sz); + uint8_t *fds = (uint8_t *) malloc(fds_sz); #if CONFIG_SPIFFS_CACHE uint32_t cache_sz = sizeof(spiffs_cache) + max_files * (sizeof(spiffs_cache_page) - + cfg.log_page_size); - uint8_t *cache = (uint8_t*) malloc(cache_sz); + + cfg.log_page_size); + uint8_t *cache = (uint8_t *) malloc(cache_sz); #else uint32_t cache_sz = 0; uint8_t cache = NULL; @@ -63,17 +80,17 @@ static void init_spiffs(spiffs *fs, uint32_t max_files) // Special mounting procedure: mount, format, mount as per // https://github.com/pellepl/spiffs/wiki/Using-spiffs spiffs_res = SPIFFS_mount(fs, &cfg, work, fds, fds_sz, - cache, cache_sz, spiffs_api_check); + cache, cache_sz, spiffs_api_check); if (spiffs_res == SPIFFS_ERR_NOT_A_FS) { spiffs_res = SPIFFS_format(fs); - REQUIRE(spiffs_res >= SPIFFS_OK); + TEST_ASSERT_TRUE(spiffs_res >= SPIFFS_OK); spiffs_res = SPIFFS_mount(fs, &cfg, work, fds, fds_sz, - cache, cache_sz, spiffs_api_check); + cache, cache_sz, spiffs_api_check); } - REQUIRE(spiffs_res >= SPIFFS_OK); + TEST_ASSERT_TRUE(spiffs_res >= SPIFFS_OK); } static void deinit_spiffs(spiffs *fs) @@ -89,7 +106,7 @@ static void deinit_spiffs(spiffs *fs) #endif } -static void check_spiffs_files(spiffs *fs, const char *base_path, char* cur_path) +static void check_spiffs_files(spiffs *fs, const char *base_path, char *cur_path) { DIR *dir; struct dirent *entry; @@ -101,7 +118,7 @@ static void check_spiffs_files(spiffs *fs, const char *base_path, char* cur_path } dir = opendir(cur_path); - REQUIRE(dir != 0); + TEST_ASSERT_TRUE(dir != 0); while ((entry = readdir(dir)) != NULL) { char *name = entry->d_name; @@ -117,20 +134,21 @@ static void check_spiffs_files(spiffs *fs, const char *base_path, char* cur_path stat(path, &sb); if (S_ISDIR(sb.st_mode)) { - if (!strcmp(name, ".") || !strcmp(name, "..")) + if (!strcmp(name, ".") || !strcmp(name, "..")) { continue; + } cur_path[len] = '/'; strcpy(cur_path + len + 1, name); check_spiffs_files(fs, base_path, cur_path); cur_path[len] = '\0'; } else { - FILE* f = fopen(path , "r"); - REQUIRE(f); + FILE *f = fopen(path, "r"); + TEST_ASSERT_NOT_NULL(f); fseek(f, 0, SEEK_END); long sz = ftell(f); fseek(f, 0, SEEK_SET); - char *f_contents = (char*) malloc(sz); + char *f_contents = (char *) malloc(sz); fread(f_contents, 1, sz, f); fclose(f); @@ -140,22 +158,22 @@ static void check_spiffs_files(spiffs *fs, const char *base_path, char* cur_path char *spiffs_path = path + strlen(base_path); spiffs_res = SPIFFS_open(fs, spiffs_path, SPIFFS_RDONLY, 0); - REQUIRE(spiffs_res > SPIFFS_OK); + TEST_ASSERT_TRUE(spiffs_res > SPIFFS_OK); spiffs_file fd = spiffs_res; spiffs_stat stat; spiffs_res = SPIFFS_stat(fs, spiffs_path, &stat); - char *spiffs_f_contents = (char*) malloc(stat.size); + char *spiffs_f_contents = (char *) malloc(stat.size); spiffs_res = SPIFFS_read(fs, fd, spiffs_f_contents, stat.size); - REQUIRE(spiffs_res == stat.size); + TEST_ASSERT_TRUE(spiffs_res == stat.size); // Compare the contents - REQUIRE(sz == stat.size); + TEST_ASSERT_TRUE(sz == stat.size); bool same = memcmp(f_contents, spiffs_f_contents, sz) == 0; - REQUIRE(same); + TEST_ASSERT_TRUE(same); free(f_contents); free(spiffs_f_contents); @@ -164,10 +182,8 @@ static void check_spiffs_files(spiffs *fs, const char *base_path, char* cur_path closedir(dir); } -TEST_CASE("format disk, open file, write and read file", "[spiffs]") +TEST(spiffs, format_disk_open_file_write_and_read_file) { - _spi_flash_init(CONFIG_ESPTOOLPY_FLASHSIZE, CONFIG_WL_SECTOR_SIZE * 16, CONFIG_WL_SECTOR_SIZE, CONFIG_WL_SECTOR_SIZE, "partition_table.bin"); - spiffs fs; s32_t spiffs_res; @@ -175,40 +191,39 @@ TEST_CASE("format disk, open file, write and read file", "[spiffs]") // Open test file spiffs_res = SPIFFS_open(&fs, "test.txt", SPIFFS_O_CREAT | SPIFFS_O_RDWR, 0); - REQUIRE(spiffs_res >= SPIFFS_OK); + TEST_ASSERT_TRUE(spiffs_res >= SPIFFS_OK); // Generate data spiffs_file file = spiffs_res; uint32_t data_size = 100000; - char *data = (char*) malloc(data_size); - char *read = (char*) malloc(data_size); + char *data = (char *) malloc(data_size); + char *read = (char *) malloc(data_size); - for(uint32_t i = 0; i < data_size; i += sizeof(i)) - { - *((uint32_t*)(data + i)) = i; + for (uint32_t i = 0; i < data_size; i += sizeof(i)) { + *((uint32_t *)(data + i)) = i; } // Write data to file - spiffs_res = SPIFFS_write(&fs, file, (void*)data, data_size); - REQUIRE(spiffs_res >= SPIFFS_OK); - REQUIRE(spiffs_res == data_size); + spiffs_res = SPIFFS_write(&fs, file, (void *)data, data_size); + TEST_ASSERT_TRUE(spiffs_res >= SPIFFS_OK); + TEST_ASSERT_TRUE(spiffs_res == data_size); // Set the file object pointer to the beginning spiffs_res = SPIFFS_lseek(&fs, file, 0, SPIFFS_SEEK_SET); - REQUIRE(spiffs_res >= SPIFFS_OK); + TEST_ASSERT_TRUE(spiffs_res >= SPIFFS_OK); // Read the file - spiffs_res = SPIFFS_read(&fs, file, (void*)read, data_size); - REQUIRE(spiffs_res >= SPIFFS_OK); - REQUIRE(spiffs_res == data_size); + spiffs_res = SPIFFS_read(&fs, file, (void *)read, data_size); + TEST_ASSERT_TRUE(spiffs_res >= SPIFFS_OK); + TEST_ASSERT_TRUE(spiffs_res == data_size); // Close the test file spiffs_res = SPIFFS_close(&fs, file); - REQUIRE(spiffs_res >= SPIFFS_OK); + TEST_ASSERT_TRUE(spiffs_res >= SPIFFS_OK); - REQUIRE(memcmp(data, read, data_size) == 0); + TEST_ASSERT_TRUE(memcmp(data, read, data_size) == 0); deinit_spiffs(&fs); @@ -216,28 +231,26 @@ TEST_CASE("format disk, open file, write and read file", "[spiffs]") free(data); } -TEST_CASE("can read spiffs image", "[spiffs]") +TEST(spiffs, can_read_spiffs_image) { - _spi_flash_init(CONFIG_ESPTOOLPY_FLASHSIZE, CONFIG_WL_SECTOR_SIZE * 16, CONFIG_WL_SECTOR_SIZE, CONFIG_WL_SECTOR_SIZE, "partition_table.bin"); - spiffs fs; s32_t spiffs_res; const esp_partition_t *partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_SPIFFS, "storage"); // Write the contents of the image file to partition - FILE* img_file = fopen("image.bin", "r"); - REQUIRE(img_file); + FILE *img_file = fopen("image.bin", "r"); + TEST_ASSERT_NOT_NULL(img_file); fseek(img_file, 0, SEEK_END); long img_size = ftell(img_file); fseek(img_file, 0, SEEK_SET); - char *img = (char*) malloc(img_size); + char *img = (char *) malloc(img_size); fread(img, 1, img_size, img_file); fclose(img_file); - REQUIRE(partition->size == img_size); + TEST_ASSERT_TRUE(partition->size == img_size); esp_partition_erase_range(partition, 0, partition->size); esp_partition_write(partition, 0, img, img_size); @@ -250,7 +263,7 @@ TEST_CASE("can read spiffs image", "[spiffs]") // Check spiffs consistency spiffs_res = SPIFFS_check(&fs); - REQUIRE(spiffs_res == SPIFFS_OK); + TEST_ASSERT_TRUE(spiffs_res == SPIFFS_OK); char path_buf[PATH_MAX]; @@ -260,3 +273,20 @@ TEST_CASE("can read spiffs image", "[spiffs]") deinit_spiffs(&fs); } + +TEST_GROUP_RUNNER(spiffs) +{ + RUN_TEST_CASE(spiffs, format_disk_open_file_write_and_read_file); + RUN_TEST_CASE(spiffs, can_read_spiffs_image); +} + +static void run_all_tests(void) +{ + RUN_TEST_GROUP(spiffs); +} + +int main(int argc, char **argv) +{ + UNITY_MAIN_FUNC(run_all_tests); + return 0; +} diff --git a/components/spiffs/test_spiffs_host/partition_table.csv b/components/spiffs/host_test/partition_table.csv similarity index 100% rename from components/spiffs/test_spiffs_host/partition_table.csv rename to components/spiffs/host_test/partition_table.csv diff --git a/components/spiffs/host_test/sdkconfig.defaults b/components/spiffs/host_test/sdkconfig.defaults new file mode 100644 index 0000000000..275e768c6c --- /dev/null +++ b/components/spiffs/host_test/sdkconfig.defaults @@ -0,0 +1,8 @@ +CONFIG_IDF_TARGET="linux" +CONFIG_COMPILER_CXX_EXCEPTIONS=y +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=n +CONFIG_UNITY_ENABLE_FIXTURE=y +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partition_table.csv" +CONFIG_ESPTOOLPY_FLASHSIZE="4MB" +CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y diff --git a/components/spiffs/spiffs_api.c b/components/spiffs/spiffs_api.c index aa7f4ddc63..03e3c4893c 100644 --- a/components/spiffs/spiffs_api.c +++ b/components/spiffs/spiffs_api.c @@ -8,7 +8,6 @@ #include "esp_log.h" #include "esp_partition.h" #include "esp_spiffs.h" -#include "esp_vfs.h" #include "spiffs_api.h" static const char* TAG = "SPIFFS"; diff --git a/components/spiffs/spiffs_api.h b/components/spiffs/spiffs_api.h index 7a9cb8ef5f..512598a7d2 100644 --- a/components/spiffs/spiffs_api.h +++ b/components/spiffs/spiffs_api.h @@ -12,13 +12,14 @@ #include "freertos/task.h" #include "freertos/semphr.h" #include "spiffs.h" -#include "esp_vfs.h" #include "esp_compiler.h" #ifdef __cplusplus extern "C" { #endif +#define ESP_SPIFFS_PATH_MAX 15 + /** * @brief SPIFFS definition structure */ @@ -26,7 +27,7 @@ typedef struct { spiffs *fs; /*!< Handle to the underlying SPIFFS */ SemaphoreHandle_t lock; /*!< FS lock */ const esp_partition_t* partition; /*!< The partition on which SPIFFS is located */ - char base_path[ESP_VFS_PATH_MAX+1]; /*!< Mount point */ + char base_path[ESP_SPIFFS_PATH_MAX+1]; /*!< Mount point */ bool by_label; /*!< Partition was mounted by label */ spiffs_config cfg; /*!< SPIFFS Mount configuration */ uint8_t *work; /*!< Work Buffer */ diff --git a/components/spiffs/spiffsgen.py b/components/spiffs/spiffsgen.py index 9a1dae4ad6..45f84492f8 100755 --- a/components/spiffs/spiffsgen.py +++ b/components/spiffs/spiffsgen.py @@ -167,7 +167,7 @@ class SpiffsObjLuPage(SpiffsPage): img += struct.pack(SpiffsPage._endianness_dict[self.build_config.endianness] + SpiffsPage._len_dict[self.build_config.obj_id_len], obj_id) - assert(len(img) <= self.build_config.page_size) + assert len(img) <= self.build_config.page_size img += b'\xFF' * (self.build_config.page_size - len(img)) @@ -249,7 +249,7 @@ class SpiffsObjIndexPage(SpiffsObjPageWithIdx): img += struct.pack(SpiffsPage._endianness_dict[self.build_config.endianness] + SpiffsPage._len_dict[self.build_config.page_ix_len], page) - assert(len(img) <= self.build_config.page_size) + assert len(img) <= self.build_config.page_size img += b'\xFF' * (self.build_config.page_size - len(img)) @@ -275,7 +275,7 @@ class SpiffsObjDataPage(SpiffsObjPageWithIdx): img += self.contents - assert(len(img) <= self.build_config.page_size) + assert len(img) <= self.build_config.page_size img += b'\xFF' * (self.build_config.page_size - len(img)) @@ -374,7 +374,7 @@ class SpiffsBlock(object): for page in self.pages: img += page.to_binary() - assert(len(img) <= self.build_config.block_size) + assert len(img) <= self.build_config.block_size img += b'\xFF' * (self.build_config.block_size - len(img)) return img diff --git a/components/spiffs/test_spiffs_host/Makefile b/components/spiffs/test_spiffs_host/Makefile deleted file mode 100644 index df5e9b5ed3..0000000000 --- a/components/spiffs/test_spiffs_host/Makefile +++ /dev/null @@ -1,105 +0,0 @@ -ifndef COMPONENT -COMPONENT := spiffs -endif - -COMPONENT_LIB := lib$(COMPONENT).a -TEST_PROGRAM := test_$(COMPONENT) - -STUBS_LIB_DIR := ../../../components/spi_flash/sim/stubs -STUBS_LIB_BUILD_DIR := $(STUBS_LIB_DIR)/build -STUBS_LIB := libstubs.a - -SPI_FLASH_SIM_DIR := ../../../components/spi_flash/sim -SPI_FLASH_SIM_BUILD_DIR := $(SPI_FLASH_SIM_DIR)/build -SPI_FLASH_SIM_LIB := libspi_flash.a - -include Makefile.files - -all: test - -ifndef SDKCONFIG -SDKCONFIG_DIR := $(dir $(realpath sdkconfig/sdkconfig.h)) -SDKCONFIG := $(SDKCONFIG_DIR)sdkconfig.h -else -SDKCONFIG_DIR := $(dir $(realpath $(SDKCONFIG))) -endif - -INCLUDE_FLAGS := $(addprefix -I, $(INCLUDE_DIRS) $(SDKCONFIG_DIR) ../../../tools/catch) - -CPPFLAGS += $(INCLUDE_FLAGS) -g -m32 -CXXFLAGS += $(INCLUDE_FLAGS) -std=c++11 -g -m32 - -# Build libraries that this component is dependent on -$(STUBS_LIB_BUILD_DIR)/$(STUBS_LIB): force - $(MAKE) -C $(STUBS_LIB_DIR) lib SDKCONFIG=$(SDKCONFIG) - -$(SPI_FLASH_SIM_BUILD_DIR)/$(SPI_FLASH_SIM_LIB): force - $(MAKE) -C $(SPI_FLASH_SIM_DIR) lib SDKCONFIG=$(SDKCONFIG) - -# Create target for building this component as a library -CFILES := $(filter %.c, $(SOURCE_FILES)) -CPPFILES := $(filter %.cpp, $(SOURCE_FILES)) - -CTARGET = ${2}/$(patsubst %.c,%.o,$(notdir ${1})) -CPPTARGET = ${2}/$(patsubst %.cpp,%.o,$(notdir ${1})) - -ifndef BUILD_DIR -BUILD_DIR := build -endif - -OBJ_FILES := $(addprefix $(BUILD_DIR)/, $(filter %.o, $(notdir $(SOURCE_FILES:.cpp=.o) $(SOURCE_FILES:.c=.o)))) - -define COMPILE_C -$(call CTARGET, ${1}, $(BUILD_DIR)) : ${1} $(SDKCONFIG) - mkdir -p $(BUILD_DIR) - $(CC) $(CPPFLAGS) $(CFLAGS) -c -o $(call CTARGET, ${1}, $(BUILD_DIR)) ${1} -endef - -define COMPILE_CPP -$(call CPPTARGET, ${1}, $(BUILD_DIR)) : ${1} $(SDKCONFIG) - mkdir -p $(BUILD_DIR) - $(CXX) $(CPPFLAGS) $(CXXFLAGS) -c -o $(call CPPTARGET, ${1}, $(BUILD_DIR)) ${1} -endef - -$(BUILD_DIR)/$(COMPONENT_LIB): $(OBJ_FILES) $(SDKCONFIG) - mkdir -p $(BUILD_DIR) - $(AR) rcs $@ $^ - -clean: - $(MAKE) -C $(STUBS_LIB_DIR) clean - $(MAKE) -C $(SPI_FLASH_SIM_DIR) clean - rm -f $(OBJ_FILES) $(TEST_OBJ_FILES) $(TEST_PROGRAM) $(COMPONENT_LIB) partition_table.bin image.bin - -lib: $(BUILD_DIR)/$(COMPONENT_LIB) - -$(foreach cfile, $(CFILES), $(eval $(call COMPILE_C, $(cfile)))) -$(foreach cxxfile, $(CPPFILES), $(eval $(call COMPILE_CPP, $(cxxfile)))) - -# Create target for building this component as a test -TEST_SOURCE_FILES = \ - test_spiffs.cpp \ - main.cpp \ - -TEST_OBJ_FILES = $(filter %.o, $(TEST_SOURCE_FILES:.cpp=.o) $(TEST_SOURCE_FILES:.c=.o)) - -$(TEST_PROGRAM): lib $(TEST_OBJ_FILES) $(SPI_FLASH_SIM_BUILD_DIR)/$(SPI_FLASH_SIM_LIB) $(STUBS_LIB_BUILD_DIR)/$(STUBS_LIB) partition_table.bin $(SDKCONFIG) - g++ $(LDFLAGS) $(CXXFLAGS) -o $@ $(TEST_OBJ_FILES) -L$(BUILD_DIR) -l:$(COMPONENT_LIB) -L$(SPI_FLASH_SIM_BUILD_DIR) -l:$(SPI_FLASH_SIM_LIB) -L$(STUBS_LIB_BUILD_DIR) -l:$(STUBS_LIB) - -# Use spiffs source directory as the test image -spiffs_image: ../spiffs $(shell find ../spiffs -type d) $(shell find ../spiffs -type -f -name '*') - # Creation of test symlinks unfortunately causes rerun of spiffsgen.py every make invoke - rm -f ../spiffs/include ../spiffs/CMakeLists.txt - ln -s ../include ../spiffs/include - ln -s ../CMakeLists.txt ../spiffs/CMakeLists.txt - ../spiffsgen.py --follow-symlinks 2097152 ../spiffs image.bin - -test: $(TEST_PROGRAM) spiffs_image - ./$(TEST_PROGRAM) - -# Create other necessary targets -partition_table.bin: partition_table.csv - python ../../../components/partition_table/gen_esp32part.py --verify $< $@ - -force: - -.PHONY: all lib test clean force diff --git a/components/spiffs/test_spiffs_host/Makefile.files b/components/spiffs/test_spiffs_host/Makefile.files deleted file mode 100644 index b8269837c5..0000000000 --- a/components/spiffs/test_spiffs_host/Makefile.files +++ /dev/null @@ -1,43 +0,0 @@ -SOURCE_FILES := \ - ../spiffs_api.c \ - $(addprefix ../spiffs/src/, \ - spiffs_cache.c \ - spiffs_check.c \ - spiffs_gc.c \ - spiffs_hydrogen.c \ - spiffs_nucleus.c \ - ) - -INCLUDE_DIRS := \ - . \ - .. \ - ../spiffs/src \ - ../include \ - $(addprefix ../../spi_flash/sim/stubs/, \ - app_update/include \ - driver/include \ - freertos/include \ - newlib/include \ - sdmmc/include \ - vfs/include \ - ) \ - $(addprefix ../../../components/, \ - esp_rom/include \ - esp_common/include \ - esp_hw_support/include \ - esp_hw_support/include/soc \ - esp_system/include \ - log/include \ - xtensa/include \ - xtensa/esp32/include \ - soc/esp32/include \ - heap/include \ - soc/include \ - esp32/include \ - bootloader_support/include \ - bootloader_support/bootloader_flash/include \ - app_update/include \ - spi_flash/include \ - hal/include \ - wear_levelling/include \ - ) diff --git a/components/spiffs/test_spiffs_host/component.mk b/components/spiffs/test_spiffs_host/component.mk deleted file mode 100644 index 928f5343aa..0000000000 --- a/components/spiffs/test_spiffs_host/component.mk +++ /dev/null @@ -1,17 +0,0 @@ -include $(COMPONENT_PATH)/Makefile.files - -COMPONENT_OWNBUILDTARGET := 1 -COMPONENT_OWNCLEANTARGET := 1 - -COMPONENT_ADD_INCLUDEDIRS := $(INCLUDE_DIRS) - -.PHONY: build -build: $(SDKCONFIG_HEADER) - $(MAKE) -C $(COMPONENT_PATH) lib SDKCONFIG=$(SDKCONFIG_HEADER) BUILD_DIR=$(COMPONENT_BUILD_DIR) COMPONENT=$(COMPONENT_NAME) - -CLEAN_FILES := component_project_vars.mk -.PHONY: clean -clean: - $(summary) RM $(CLEAN_FILES) - rm -f $(CLEAN_FILES) - $(MAKE) -C $(COMPONENT_PATH) clean SDKCONFIG=$(SDKCONFIG_HEADER) BUILD_DIR=$(COMPONENT_BUILD_DIR) COMPONENT=$(COMPONENT_NAME) diff --git a/components/spiffs/test_spiffs_host/main.cpp b/components/spiffs/test_spiffs_host/main.cpp deleted file mode 100644 index 42286b7501..0000000000 --- a/components/spiffs/test_spiffs_host/main.cpp +++ /dev/null @@ -1,7 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#define CATCH_CONFIG_MAIN -#include "catch.hpp" diff --git a/components/spiffs/test_spiffs_host/sdkconfig/sdkconfig.h b/components/spiffs/test_spiffs_host/sdkconfig/sdkconfig.h deleted file mode 100644 index 5324b5aee2..0000000000 --- a/components/spiffs/test_spiffs_host/sdkconfig/sdkconfig.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once -#define CONFIG_IDF_TARGET_ESP32 1 -#define CONFIG_SPIFFS_USE_MAGIC_LENGTH 1 -#define CONFIG_SPIFFS_MAX_PARTITIONS 3 -#define CONFIG_SPIFFS_OBJ_NAME_LEN 32 -#define CONFIG_SPIFFS_PAGE_SIZE 256 -#define CONFIG_SPIFFS_GC_MAX_RUNS 10 -#define CONFIG_SPIFFS_CACHE_WR 1 -#define CONFIG_SPIFFS_CACHE 1 -#define CONFIG_SPIFFS_META_LENGTH 4 -#define CONFIG_SPIFFS_USE_MAGIC 1 -#define CONFIG_SPIFFS_PAGE_CHECK 1 -#define CONFIG_SPIFFS_USE_MTIME 1 - -#define CONFIG_WL_SECTOR_SIZE 4096 - -// for log component with linux target -#define CONFIG_LOG_DEFAULT_LEVEL 3 -#define CONFIG_LOG_MAXIMUM_LEVEL 3 -#define CONFIG_LOG_TIMESTAMP_SOURCE_RTOS 1 - -#define CONFIG_PARTITION_TABLE_OFFSET 0x8000 - -#define CONFIG_ESPTOOLPY_FLASHSIZE "8MB" -//currently use the legacy implementation, since the stubs for new HAL are not done yet -#define CONFIG_SPI_FLASH_USE_LEGACY_IMPL 1 -#define CONFIG_MMU_PAGE_SIZE 0X10000 // 64KB - -#undef _Static_assert -#define _Static_assert(cond, message) diff --git a/components/tcp_transport/include/esp_transport_ssl.h b/components/tcp_transport/include/esp_transport_ssl.h index b31e5b4495..30e6db9e65 100644 --- a/components/tcp_transport/include/esp_transport_ssl.h +++ b/components/tcp_transport/include/esp_transport_ssl.h @@ -1,16 +1,8 @@ -// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _ESP_TRANSPORT_SSL_H_ #define _ESP_TRANSPORT_SSL_H_ @@ -142,6 +134,17 @@ void esp_transport_ssl_set_alpn_protocol(esp_transport_handle_t t, const char ** */ void esp_transport_ssl_skip_common_name_check(esp_transport_handle_t t); +/** + * @brief Set the server certificate's common name field + * + * @note + * If non-NULL, server certificate CN must match this name, + * If NULL, server certificate CN must match hostname. + * @param t ssl transport + * common_name A string containing the common name to be set + */ +void esp_transport_ssl_set_common_name(esp_transport_handle_t t, const char *common_name); + /** * @brief Set the ssl context to use secure element (atecc608a) for client(device) private key and certificate * diff --git a/components/tcp_transport/include/esp_transport_tcp.h b/components/tcp_transport/include/esp_transport_tcp.h index 6941820f0e..e5b0a46638 100644 --- a/components/tcp_transport/include/esp_transport_tcp.h +++ b/components/tcp_transport/include/esp_transport_tcp.h @@ -1,22 +1,15 @@ -// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _ESP_TRANSPORT_TCP_H_ #define _ESP_TRANSPORT_TCP_H_ #include "esp_transport.h" #include +#include #ifdef __cplusplus extern "C" { diff --git a/components/tcp_transport/test/test_transport_connect.c b/components/tcp_transport/test/test_transport_connect.c index 8a4bbdb827..681cf6ecaa 100644 --- a/components/tcp_transport/test/test_transport_connect.c +++ b/components/tcp_transport/test/test_transport_connect.c @@ -49,8 +49,6 @@ TEST_CASE("tcp_transport: connect timeout", "[tcp_transport]") esp_transport_list_destroy(transport_list); } -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) -//IDF-5144 TEST_CASE("ssl_transport: connect timeout", "[tcp_transport]") { // Init the transport under test @@ -123,7 +121,6 @@ TEST_CASE("ssl_transport: Keep alive test", "[tcp_transport]") esp_transport_close(ssl); esp_transport_list_destroy(transport_list); } -#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) TEST_CASE("ws_transport: Keep alive test", "[tcp_transport]") { @@ -154,8 +151,6 @@ TEST_CASE("ws_transport: Keep alive test", "[tcp_transport]") esp_transport_list_destroy(transport_list); } -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) -//IDF-5144 // Note: This functionality is tested and kept only for compatibility reasons with IDF <= 4.x // It is strongly encouraged to use transport within lists only TEST_CASE("ssl_transport: Check that parameters (keepalive) are set independently on the list", "[tcp_transport]") @@ -183,4 +178,3 @@ TEST_CASE("ssl_transport: Check that parameters (keepalive) are set independentl esp_transport_close(ssl); esp_transport_destroy(ssl); } -#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) diff --git a/components/tcp_transport/transport.c b/components/tcp_transport/transport.c index b7d504e71e..5ec2195125 100644 --- a/components/tcp_transport/transport.c +++ b/components/tcp_transport/transport.c @@ -15,7 +15,7 @@ #include "esp_transport_internal.h" #include "esp_transport.h" -static const char *TAG = "TRANSPORT"; +static const char *TAG = "transport"; /** * This list will hold all transport available diff --git a/components/tcp_transport/transport_internal.c b/components/tcp_transport/transport_internal.c index 33354686e7..08e8c82648 100644 --- a/components/tcp_transport/transport_internal.c +++ b/components/tcp_transport/transport_internal.c @@ -6,7 +6,7 @@ #include "esp_transport_internal.h" -static const char *TAG = "TRANSPORT"; +static const char *TAG = "transport"; struct timeval* esp_transport_utils_ms_to_timeval(int timeout_ms, struct timeval *tv) { if (timeout_ms == -1) { diff --git a/components/tcp_transport/transport_ssl.c b/components/tcp_transport/transport_ssl.c index bb352461fd..26f7557b59 100644 --- a/components/tcp_transport/transport_ssl.c +++ b/components/tcp_transport/transport_ssl.c @@ -20,7 +20,7 @@ transport_esp_tls_t *ssl = ssl_get_context_data(t); \ if (!ssl) { return; } -static const char *TAG = "TRANSPORT_BASE"; +static const char *TAG = "transport_base"; typedef enum { TRANS_SSL_INIT = 0, @@ -169,7 +169,7 @@ static int base_poll_read(esp_transport_handle_t t, int timeout_ms) ESP_LOGE(TAG, "poll_read select error %d, errno = %s, fd = %d", sock_errno, strerror(sock_errno), ssl->sockfd); ret = -1; } else if (ret == 0) { - ESP_LOGD(TAG, "poll_read: select - Timeout before any socket was ready!"); + ESP_LOGV(TAG, "poll_read: select - Timeout before any socket was ready!"); } return ret; } @@ -408,6 +408,12 @@ void esp_transport_ssl_skip_common_name_check(esp_transport_handle_t t) ssl->cfg.skip_common_name = true; } +void esp_transport_ssl_set_common_name(esp_transport_handle_t t, const char *common_name) +{ + GET_SSL_FROM_TRANSPORT_OR_RETURN(ssl, t); + ssl->cfg.common_name = common_name; +} + #ifdef CONFIG_ESP_TLS_USE_SECURE_ELEMENT void esp_transport_ssl_use_secure_element(esp_transport_handle_t t) { diff --git a/components/tcp_transport/transport_ws.c b/components/tcp_transport/transport_ws.c index 7004660f45..daea861390 100644 --- a/components/tcp_transport/transport_ws.c +++ b/components/tcp_transport/transport_ws.c @@ -17,7 +17,7 @@ #include "errno.h" #include "esp_tls_crypto.h" -static const char *TAG = "TRANSPORT_WS"; +static const char *TAG = "transport_ws"; #define WS_BUFFER_SIZE CONFIG_WS_BUFFER_SIZE #define WS_FIN 0x80 @@ -363,10 +363,8 @@ static int ws_read_payload(esp_transport_handle_t t, char *buffer, int len, int } ws->frame_state.bytes_remaining -= rlen; - if (ws->frame_state.mask_key) { - for (int i = 0; i < bytes_to_read; i++) { - buffer[i] = (buffer[i] ^ ws->frame_state.mask_key[i % 4]); - } + for (int i = 0; i < bytes_to_read; i++) { + buffer[i] = (buffer[i] ^ ws->frame_state.mask_key[i % 4]); } return rlen; } diff --git a/components/tinyusb/additions/include/tusb_cdc_acm.h b/components/tinyusb/additions/include/tusb_cdc_acm.h index da197a67f0..266ca86c82 100644 --- a/components/tinyusb/additions/include/tusb_cdc_acm.h +++ b/components/tinyusb/additions/include/tusb_cdc_acm.h @@ -88,7 +88,7 @@ typedef void(*tusb_cdcacm_callback_t)(int itf, cdcacm_event_t *event); typedef struct { tinyusb_usbdev_t usb_dev; /*!< Usb device to set up */ tinyusb_cdcacm_itf_t cdc_port; /*!< CDC port */ - size_t rx_unread_buf_sz; /*!< Amount of data that can be passed to the AMC at once */ + size_t rx_unread_buf_sz; /*!< Amount of data that can be passed to the ACM at once */ tusb_cdcacm_callback_t callback_rx; /*!< Pointer to the function with the `tusb_cdcacm_callback_t` type that will be handled as a callback */ tusb_cdcacm_callback_t callback_rx_wanted_char; /*!< Pointer to the function with the `tusb_cdcacm_callback_t` type that will be handled as a callback */ tusb_cdcacm_callback_t callback_line_state_changed; /*!< Pointer to the function with the `tusb_cdcacm_callback_t` type that will be handled as a callback */ diff --git a/components/tinyusb/additions/include_private/cdc.h b/components/tinyusb/additions/include_private/cdc.h index e3c85f9570..c6eb923180 100644 --- a/components/tinyusb/additions/include_private/cdc.h +++ b/components/tinyusb/additions/include_private/cdc.h @@ -32,7 +32,7 @@ typedef struct { tinyusb_usbdev_t usb_dev; /*!< USB device to set up */ tusb_class_code_t cdc_class; /*!< CDC device class : Communications or Data device */ union { - cdc_comm_sublcass_type_t comm_subclass; /*!< Communications device subclasses: AMC, ECM, etc. */ + cdc_comm_sublcass_type_t comm_subclass; /*!< Communications device subclasses: ACM, ECM, etc. */ cdc_data_sublcass_type_t data_subclass; /*!< Data device has only one subclass.*/ } cdc_subclass; /*!< CDC device subclass according to Class Definitions for Communications Devices the CDC v.1.20 */ } tinyusb_config_cdc_t; /*!< Main configuration structure of a CDC device */ @@ -41,7 +41,7 @@ typedef struct { tinyusb_usbdev_t usb_dev; /*!< USB device used for the instance */ tusb_class_code_t type; union { - cdc_comm_sublcass_type_t comm_subclass; /*!< Communications device subclasses: AMC, ECM, etc. */ + cdc_comm_sublcass_type_t comm_subclass; /*!< Communications device subclasses: ACM, ECM, etc. */ cdc_data_sublcass_type_t data_subclass; /*!< Data device has only one subclass.*/ } cdc_subclass; /*!< CDC device subclass according to Class Definitions for Communications Devices the CDC v.1.20 */ void *subclass_obj; /*!< Dynamically allocated subclass specific object */ diff --git a/components/tinyusb/additions/src/tusb_cdc_acm.c b/components/tinyusb/additions/src/tusb_cdc_acm.c index b046ce5050..725426ead8 100644 --- a/components/tinyusb/additions/src/tusb_cdc_acm.c +++ b/components/tinyusb/additions/src/tusb_cdc_acm.c @@ -30,7 +30,7 @@ typedef struct { tusb_cdcacm_callback_t callback_rx_wanted_char; tusb_cdcacm_callback_t callback_line_state_changed; tusb_cdcacm_callback_t callback_line_coding_changed; -} esp_tusb_cdcacm_t; /*!< CDC_AMC object */ +} esp_tusb_cdcacm_t; /*!< CDC_ACM object */ static const char *TAG = "tusb_cdc_acm"; diff --git a/components/touch_element/include/touch_element/touch_element.h b/components/touch_element/include/touch_element/touch_element.h index 429fc2503f..902c23e94b 100644 --- a/components/touch_element/include/touch_element/touch_element.h +++ b/components/touch_element/include/touch_element/touch_element.h @@ -94,6 +94,14 @@ typedef struct { touch_pad_t guard_channel; //!< Waterproof Guard-Sensor channel number (index) float guard_sensitivity; //!< Waterproof Guard-Sensor sensitivity } touch_elem_waterproof_config_t; + +/** + * @brief Touch element sleep configuration passed to touch_element_enable_light_sleep or touch_element_enable_deep_sleep +*/ +typedef struct { + uint16_t sample_count; //!< scan times in every measurement, normally equal to the 'sample_count' field in 'touch_elem_hw_config_t'. + uint16_t sleep_cycle; //!< sleep_cycle decide the interval between two measurements， t_sleep = sleep_cycle / (RTC_SLOW_CLK frequency), normally equal to the 'sleep_cycle' field in 'touch_elem_hw_config_t'. +} touch_elem_sleep_config_t; /* ------------------------------------------------------------------------------------------------------------------ */ typedef void *touch_elem_handle_t; //!< Touch element handle type typedef uint32_t touch_elem_event_t; //!< Touch element event type @@ -256,6 +264,75 @@ esp_err_t touch_element_waterproof_add(touch_elem_handle_t element_handle); */ esp_err_t touch_element_waterproof_remove(touch_elem_handle_t element_handle); +/** + * @brief Touch element light sleep initialization + * + * @note It should be called after touch button element installed. + * Any of installed touch element can wake up from the light sleep + * + * @param[in] sleep_config Sleep configurations, set NULL to use default config + * @return + * - ESP_OK: Successfully initialized touch sleep + * - ESP_ERR_INVALID_STATE: Touch element is not installed or touch sleep has been installed + * - ESP_ERR_INVALID_ARG: inputed argument is NULL + * - ESP_ERR_NO_MEM: no memory for touch sleep struct + * - ESP_ERR_NOT_SUPPORTED: inputed wakeup_elem_handle is not touch_button_handle_t type, currently only touch_button_handle_t supported + */ +esp_err_t touch_element_enable_light_sleep(const touch_elem_sleep_config_t *sleep_config); + +/** + * @brief Release the resources that allocated by touch_element_enable_deep_sleep() + * + * This function will also disable the touch sensor to wake up the device + * + * @return + * - ESP_OK: uninstall success + * - ESP_ERR_INVALID_STATE: touch sleep has not been installed + */ +esp_err_t touch_element_disable_light_sleep(void); + +/** + * @brief Touch element deep sleep initialization + * + * This function will enable the device wake-up from deep sleep or light sleep by touch sensor + * + * @note It should be called after touch button element installed. + * Only one touch button can be registered as the deep sleep wake-up button + * + * @param[in] wakeup_elem_handle Touch element instance handle for waking up the device, only support button element + * @param[in] sleep_config Sleep configurations, set NULL to use default config + * + * @return + * - ESP_OK: Successfully initialized touch sleep + * - ESP_ERR_INVALID_STATE: Touch element is not installed or touch sleep has been installed + * - ESP_ERR_INVALID_ARG: inputed argument is NULL + * - ESP_ERR_NO_MEM: no memory for touch sleep struct + * - ESP_ERR_NOT_SUPPORTED: inputed wakeup_elem_handle is not touch_button_handle_t type, currently only touch_button_handle_t supported + */ +esp_err_t touch_element_enable_deep_sleep(touch_elem_handle_t wakeup_elem_handle, const touch_elem_sleep_config_t *sleep_config); + +/** + * @brief Release the resources that allocated by touch_element_enable_deep_sleep() + * + * This function will also disable the touch sensor to wake up the device + * + * @return + * - ESP_OK: uninstall success + * - ESP_ERR_INVALID_STATE: touch sleep has not been installed + */ +esp_err_t touch_element_disable_deep_sleep(void); + +/** + * @brief Touch element wake up calibrations + * + * This function will also disable the touch sensor to wake up the device + * + * @return + * - ESP_OK: uninstall success + * - ESP_ERR_INVALID_STATE: touch sleep has not been installed + */ +esp_err_t touch_element_sleep_enable_wakeup_calibration(touch_elem_handle_t element_handle, bool en); + #ifdef __cplusplus } #endif diff --git a/components/touch_element/include/touch_element/touch_element_private.h b/components/touch_element/include/touch_element/touch_element_private.h index 49971ae2d4..fe09bb31f4 100644 --- a/components/touch_element/include/touch_element/touch_element_private.h +++ b/components/touch_element/include/touch_element/touch_element_private.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,6 +10,8 @@ #include "touch_element/touch_button.h" #include "touch_element/touch_slider.h" #include "touch_element/touch_matrix.h" +#include "esp_pm.h" +#include "sdkconfig.h" #ifdef __cplusplus extern "C" { @@ -54,6 +56,7 @@ typedef struct { touch_pad_t channel; //!< Touch channel number(index) te_dev_type_t type; //!< Touch channel type TODO: need to refactor as te_class_type_t te_dev_state_t state; //!< Touch channel current state + bool is_use_last_threshold; } te_dev_t; typedef enum { @@ -79,6 +82,16 @@ struct te_waterproof_s { bool is_shield_level_set; //Waterproof shield level setting bit }; typedef struct te_waterproof_s* te_waterproof_handle_t; +/* -------------------------------------------- Sleep basic type --------------------------------------------- */ +struct te_sleep_s { + touch_elem_handle_t wakeup_handle; +#ifdef CONFIG_PM_ENABLE + esp_pm_lock_handle_t pm_lock; +#endif + uint32_t *non_volatile_threshold; +}; + +typedef struct te_sleep_s* te_sleep_handle_t; /* -------------------------------------------- Button basic type --------------------------------------------- */ typedef struct { touch_elem_dispatch_t dispatch_method; //Button dispatch method @@ -170,6 +183,16 @@ void te_object_method_register(te_object_methods_t *object_methods, te_class_typ void te_object_method_unregister(te_class_type_t object_type); bool te_object_check_channel(const touch_pad_t *channel_array, uint8_t channel_sum); bool waterproof_check_mask_handle(touch_elem_handle_t te_handle); +bool te_is_touch_dsleep_wakeup(void); +touch_pad_t te_get_sleep_channel(void); + +bool is_button_object_handle(touch_elem_handle_t element_handle); +bool is_slider_object_handle(touch_elem_handle_t element_handle); +bool is_matrix_object_handle(touch_elem_handle_t element_handle); + +void button_enable_wakeup_calibration(te_button_handle_t button_handle, bool en); +void slider_enable_wakeup_calibration(te_slider_handle_t slider_handle, bool en); +void matrix_enable_wakeup_calibration(te_matrix_handle_t matrix_handle, bool en); /* ------------------------------------------------------------------------------------------------------------------ */ #ifdef __cplusplus diff --git a/components/touch_element/touch_button.c b/components/touch_element/touch_button.c index 7a93d03f93..6c0dd3680f 100644 --- a/components/touch_element/touch_button.c +++ b/components/touch_element/touch_button.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -296,6 +296,20 @@ static esp_err_t button_object_remove_instance(te_button_handle_t button_handle) return ret; } +bool is_button_object_handle(touch_elem_handle_t element_handle) +{ + te_button_handle_list_t *item; + xSemaphoreTake(s_te_btn_obj->mutex, portMAX_DELAY); + SLIST_FOREACH(item, &s_te_btn_obj->handle_list, next) { + if (element_handle == item->button_handle) { + xSemaphoreGive(s_te_btn_obj->mutex); + return true; + } + } + xSemaphoreGive(s_te_btn_obj->mutex); + return false; +} + static bool button_channel_check(te_button_handle_t button_handle, touch_pad_t channel_num) { return (channel_num == button_handle->device->channel); @@ -346,6 +360,11 @@ static inline void button_dispatch(te_button_handle_t button_handle, touch_elem_ } } +void button_enable_wakeup_calibration(te_button_handle_t button_handle, bool en) +{ + button_handle->device->is_use_last_threshold = !en; +} + /** * @brief Button process * diff --git a/components/touch_element/touch_element.c b/components/touch_element/touch_element.c index ec465c95b3..d8d656e858 100644 --- a/components/touch_element/touch_element.c +++ b/components/touch_element/touch_element.c @@ -9,11 +9,15 @@ #include "freertos/FreeRTOS.h" #include "freertos/semphr.h" #include "freertos/queue.h" +#include "esp_sleep.h" #include "esp_timer.h" -#include "esp_log.h" +#include "esp_check.h" #include "hal/touch_sensor_hal.h" //TODO: remove hal #include "touch_element/touch_element_private.h" +#include "esp_rom_sys.h" + + #define TE_CLASS_ITEM(cls, cls_type, cls_item) ((&((cls)[cls_type]))->cls_item) #define TE_CLASS_FOREACH(cls_var, cls_start, cls_end) \ @@ -87,6 +91,7 @@ typedef struct { te_object_methods_t object_methods[TE_CLS_TYPE_MAX]; //Class(object) methods touch_elem_global_config_t *global_config; //Global initialization te_waterproof_handle_t waterproof_handle; //Waterproof configuration + te_sleep_handle_t sleep_handle; esp_timer_handle_t proc_timer; //Processing timer handle QueueHandle_t event_msg_queue; //Application event message queue (for user) QueueHandle_t intr_msg_queue; //Interrupt message (for internal) @@ -96,6 +101,7 @@ typedef struct { } te_obj_t; static te_obj_t *s_te_obj = NULL; +RTC_FAST_ATTR uint32_t threshold_shadow[TOUCH_PAD_MAX - 1] = {0}; /** * Internal de-noise channel(Touch channel 0) equivalent capacitance table, depends on hardware design @@ -313,6 +319,36 @@ esp_err_t te_event_give(touch_elem_message_t te_message) return ESP_OK; } +uint32_t te_get_threshold(touch_pad_t channel_num) +{ + uint32_t threshold = 0; + touch_pad_sleep_channel_t sleep_channel_info; + touch_pad_sleep_channel_get_info(&sleep_channel_info); + if (channel_num != sleep_channel_info.touch_num) { + touch_pad_get_thresh(channel_num, &threshold); + } else { + touch_pad_sleep_get_threshold(channel_num, &threshold); + } + return threshold; +} + +bool te_is_touch_dsleep_wakeup(void) +{ + soc_reset_reason_t reset_reason = esp_rom_get_reset_reason(0); + if (reset_reason != RESET_REASON_CORE_DEEP_SLEEP) { + return false; + } + esp_sleep_wakeup_cause_t wakeup_reason = esp_sleep_get_wakeup_cause(); + return wakeup_reason == ESP_SLEEP_WAKEUP_TOUCHPAD; +} + +touch_pad_t te_get_sleep_channel(void) +{ + touch_pad_sleep_channel_t sleep_channel_info; + touch_pad_sleep_channel_get_info(&sleep_channel_info); + return sleep_channel_info.touch_num; +} + /** * @brief Touch sensor interrupt service routine * @@ -323,22 +359,41 @@ static void te_intr_cb(void *arg) { TE_UNUSED(arg); static int scan_done_cnt = 0; + static uint32_t touch_pre_trig_status = 0; int task_awoken = pdFALSE; te_intr_msg_t te_intr_msg; /*< Figure out which touch sensor channel is triggered and the trigger type */ uint32_t intr_mask = touch_pad_read_intr_status_mask(); - te_intr_msg.channel_num = touch_pad_get_current_meas_channel(); if (intr_mask == 0x0) { //For dummy interrupt return; } + bool need_send_queue = true; - if (intr_mask & TOUCH_PAD_INTR_MASK_ACTIVE) { - te_intr_msg.channel_state = TE_STATE_PRESS; - te_intr_msg.intr_type = TE_INTR_PRESS; - } else if (intr_mask & TOUCH_PAD_INTR_MASK_INACTIVE) { - te_intr_msg.channel_state = TE_STATE_RELEASE; - te_intr_msg.intr_type = TE_INTR_RELEASE; - } else if (intr_mask & TOUCH_PAD_INTR_MASK_TIMEOUT) { + uint8_t pad_num = 0; + uint32_t touch_trig_status = touch_pad_get_status(); + uint32_t touch_trig_diff = touch_trig_status ^ touch_pre_trig_status; + while (touch_trig_diff) { + if (touch_trig_diff & 0x1) { + if (touch_trig_status & BIT(pad_num)) { + if (s_te_obj->sleep_handle != NULL) { +#ifdef CONFIG_PM_ENABLE + esp_pm_lock_acquire(s_te_obj->sleep_handle->pm_lock); +#endif + } + te_intr_msg.channel_state = TE_STATE_PRESS; + te_intr_msg.intr_type = TE_INTR_PRESS; + } else { + te_intr_msg.channel_state = TE_STATE_RELEASE; + te_intr_msg.intr_type = TE_INTR_RELEASE; + } + touch_pre_trig_status = touch_trig_status; + te_intr_msg.channel_num = pad_num; + } + pad_num++; + touch_trig_diff >>= 1; + } + + if (intr_mask & TOUCH_PAD_INTR_MASK_TIMEOUT) { te_intr_msg.channel_state = TE_STATE_IDLE; te_intr_msg.intr_type = TE_INTR_TIMEOUT; } else if (intr_mask & TOUCH_PAD_INTR_MASK_SCAN_DONE) { @@ -354,8 +409,6 @@ static void te_intr_cb(void *arg) } /*< De-noise channel signal must be read at the time between SCAN_DONE and next measurement beginning(sleep)!!! */ touch_pad_denoise_read_data(&s_te_obj->denoise_channel_raw); //Update de-noise signal - } else { - te_intr_msg.intr_type = TE_INTR_MAX; // Unknown Exception } if (need_send_queue) { xQueueSendFromISR(s_te_obj->intr_msg_queue, &te_intr_msg, &task_awoken); @@ -385,11 +438,21 @@ static void te_proc_timer_cb(void *arg) if (ret == pdPASS) { if (te_intr_msg.intr_type == TE_INTR_PRESS || te_intr_msg.intr_type == TE_INTR_RELEASE) { te_object_update_state(te_intr_msg); + if ((s_te_obj->sleep_handle != NULL) && (te_intr_msg.intr_type == TE_INTR_RELEASE)) { +#ifdef CONFIG_PM_ENABLE + esp_pm_lock_release(s_te_obj->sleep_handle->pm_lock); +#endif + } } else if (te_intr_msg.intr_type == TE_INTR_SCAN_DONE) { if (s_te_obj->is_set_threshold != true) { s_te_obj->is_set_threshold = true; te_object_set_threshold(); //TODO: add set threshold error processing ESP_LOGD(TE_DEBUG_TAG, "Set threshold"); + if (s_te_obj->sleep_handle != NULL) { +#ifdef CONFIG_PM_ENABLE + esp_pm_lock_release(s_te_obj->sleep_handle->pm_lock); +#endif + } } if (waterproof_check_state()) { te_waterproof_handle_t waterproof_handle = s_te_obj->waterproof_handle; @@ -500,6 +563,7 @@ esp_err_t te_dev_init(te_dev_t **device, uint8_t device_num, te_dev_type_t type, device[idx]->sens = sens[idx] * divider; device[idx]->type = type; device[idx]->state = TE_STATE_IDLE; + device[idx]->is_use_last_threshold = false; esp_err_t ret = touch_pad_config(device[idx]->channel); TE_CHECK(ret == ESP_OK, ret); } @@ -513,10 +577,37 @@ void te_dev_deinit(te_dev_t **device, uint8_t device_num) } } +static esp_err_t te_config_thresh(touch_pad_t channel_num, uint32_t threshold) +{ + esp_err_t ret; + touch_pad_sleep_channel_t sleep_channel_info; + touch_pad_sleep_channel_get_info(&sleep_channel_info); + if (channel_num != sleep_channel_info.touch_num) { + ret = touch_pad_set_thresh(channel_num, threshold); + } else { + ret = touch_pad_sleep_set_threshold(channel_num, threshold); + } + return ret; +} + esp_err_t te_dev_set_threshold(te_dev_t *device) { - uint32_t smo_val = te_read_smooth_signal(device->channel); - esp_err_t ret = touch_pad_set_thresh(device->channel, device->sens * smo_val); + esp_err_t ret = ESP_OK; + uint32_t smo_val = 0; + + if (s_te_obj->sleep_handle && device->is_use_last_threshold) { + if (te_is_touch_dsleep_wakeup()) { //Deep sleep wakeup reset + ret = te_config_thresh(device->channel, s_te_obj->sleep_handle->non_volatile_threshold[device->channel - 1]); + } else { //Other reset + smo_val = te_read_smooth_signal(device->channel); + ret = te_config_thresh(device->channel, device->sens * smo_val); + uint32_t threshold = te_get_threshold(device->channel); + s_te_obj->sleep_handle->non_volatile_threshold[device->channel - 1] = threshold; //Write threshold into RTC Fast Memory + } + } else { + smo_val = te_read_smooth_signal(device->channel); + ret = te_config_thresh(device->channel, device->sens * smo_val); + } ESP_LOGD(TE_DEBUG_TAG, "channel: %"PRIu8", smo_val: %"PRIu32, device->channel, smo_val); return ret; } @@ -648,7 +739,8 @@ static esp_err_t te_sw_init(const touch_elem_sw_config_t *software_init) const esp_timer_create_args_t te_proc_timer_args = { .name = "te_proc_timer_cb", .arg = NULL, - .callback = &te_proc_timer_cb + .callback = &te_proc_timer_cb, + .skip_unhandled_events = true, }; ret = esp_timer_create(&te_proc_timer_args, &s_te_obj->proc_timer); TE_CHECK_GOTO(ret == ESP_OK, cleanup); @@ -879,3 +971,147 @@ static void waterproof_guard_update_state(touch_pad_t current_channel, te_state_ } ESP_LOGD(TE_DEBUG_TAG, "waterproof guard state update %d", guard_device->state); } + +esp_err_t touch_element_enable_light_sleep(const touch_elem_sleep_config_t *sleep_config) +{ + TE_CHECK(s_te_obj != NULL, ESP_ERR_INVALID_STATE); + TE_CHECK(s_te_obj->sleep_handle == NULL, ESP_ERR_INVALID_STATE); + uint16_t sample_count = 500; + uint16_t sleep_cycle = 0x0f; + if (sleep_config) { + sample_count = sleep_config->sample_count; + sleep_cycle = sleep_config->sleep_cycle; + } + + s_te_obj->sleep_handle = calloc(1, sizeof(struct te_sleep_s)); + TE_CHECK(s_te_obj->sleep_handle, ESP_ERR_NO_MEM); + + esp_err_t ret = ESP_OK; + touch_pad_sleep_channel_set_work_time(sleep_cycle, sample_count); + TE_CHECK_GOTO(esp_sleep_enable_touchpad_wakeup() == ESP_OK, cleanup); + + TE_CHECK_GOTO(esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON) == ESP_OK, cleanup); + s_te_obj->sleep_handle->non_volatile_threshold = threshold_shadow; + +#ifdef CONFIG_PM_ENABLE + TE_CHECK_GOTO(esp_pm_lock_create(ESP_PM_NO_LIGHT_SLEEP, 0, "touch_element", &s_te_obj->sleep_handle->pm_lock) == ESP_OK, cleanup); + TE_CHECK_GOTO(esp_pm_lock_acquire(s_te_obj->sleep_handle->pm_lock) == ESP_OK, cleanup); +#endif + + return ESP_OK; + +cleanup: +#ifdef CONFIG_PM_ENABLE + if (s_te_obj->sleep_handle->pm_lock != NULL) { + if (esp_pm_lock_delete(s_te_obj->sleep_handle->pm_lock) != ESP_OK) { + abort(); + } + } +#endif + TE_FREE_AND_NULL(s_te_obj->sleep_handle); + return ret; +} + +esp_err_t touch_element_disable_light_sleep(void) +{ + TE_CHECK(s_te_obj->sleep_handle, ESP_ERR_INVALID_STATE); +#ifdef CONFIG_PM_ENABLE + if (s_te_obj->sleep_handle->pm_lock != NULL) { + /* Sleep channel is going to uninstall, pm lock is not needed anymore, + but we need to make sure that pm lock has been released before delete it. */ + while(esp_pm_lock_release(s_te_obj->sleep_handle->pm_lock) == ESP_OK); + esp_err_t ret = esp_pm_lock_delete(s_te_obj->sleep_handle->pm_lock); + TE_CHECK(ret == ESP_OK, ret); + s_te_obj->sleep_handle->pm_lock = NULL; + } +#endif + esp_sleep_disable_wakeup_source(ESP_SLEEP_WAKEUP_TOUCHPAD); + TE_FREE_AND_NULL(s_te_obj->sleep_handle); + return ESP_OK; +} + +esp_err_t touch_element_enable_deep_sleep(touch_elem_handle_t wakeup_elem_handle, const touch_elem_sleep_config_t *sleep_config) +{ + TE_CHECK(s_te_obj != NULL, ESP_ERR_INVALID_STATE); + TE_CHECK(s_te_obj->sleep_handle == NULL, ESP_ERR_INVALID_STATE); + TE_CHECK(wakeup_elem_handle != NULL, ESP_ERR_INVALID_ARG); + TE_CHECK(sleep_config != NULL, ESP_ERR_INVALID_ARG); + uint16_t sample_count = 500; + uint16_t sleep_cycle = 0x0f; + if (sleep_config) { + sample_count = sleep_config->sample_count; + sleep_cycle = sleep_config->sleep_cycle; + } + + s_te_obj->sleep_handle = calloc(1, sizeof(struct te_sleep_s)); + TE_CHECK(s_te_obj->sleep_handle, ESP_ERR_NO_MEM); + + esp_err_t ret = ESP_OK; + touch_pad_sleep_channel_set_work_time(sleep_cycle, sample_count); + TE_CHECK_GOTO(esp_sleep_enable_touchpad_wakeup() == ESP_OK, cleanup); + + TE_CHECK_GOTO(esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON) == ESP_OK, cleanup); + s_te_obj->sleep_handle->non_volatile_threshold = threshold_shadow; + +#ifdef CONFIG_PM_ENABLE + TE_CHECK_GOTO(esp_pm_lock_create(ESP_PM_NO_LIGHT_SLEEP, 0, "touch_element", &s_te_obj->sleep_handle->pm_lock) == ESP_OK, cleanup); + TE_CHECK_GOTO(esp_pm_lock_acquire(s_te_obj->sleep_handle->pm_lock) == ESP_OK, cleanup); +#endif + //Only support one channel/element as the deep sleep wakeup channel/element + TE_CHECK(is_button_object_handle(wakeup_elem_handle), ESP_ERR_NOT_SUPPORTED); + s_te_obj->sleep_handle->wakeup_handle = wakeup_elem_handle; + te_button_handle_t button_handle = wakeup_elem_handle; + ret = touch_pad_sleep_channel_enable(button_handle->device->channel, true); + TE_CHECK(ret == ESP_OK, ret); + + return ESP_OK; + +cleanup: +#ifdef CONFIG_PM_ENABLE + if (s_te_obj->sleep_handle->pm_lock != NULL) { + if (esp_pm_lock_delete(s_te_obj->sleep_handle->pm_lock) != ESP_OK) { + abort(); + } + } +#endif + TE_FREE_AND_NULL(s_te_obj->sleep_handle); + return ret; +} + +esp_err_t touch_element_disable_deep_sleep(void) +{ + TE_CHECK(s_te_obj->sleep_handle, ESP_ERR_INVALID_STATE); + esp_err_t ret; +#ifdef CONFIG_PM_ENABLE + if (s_te_obj->sleep_handle->pm_lock != NULL) { + /* Sleep channel is going to uninstall, pm lock is not needed anymore, + but we need to make sure that pm lock has been released before delete it. */ + while(esp_pm_lock_release(s_te_obj->sleep_handle->pm_lock) == ESP_OK); + ret = esp_pm_lock_delete(s_te_obj->sleep_handle->pm_lock); + TE_CHECK(ret == ESP_OK, ret); + s_te_obj->sleep_handle->pm_lock = NULL; + } +#endif + te_button_handle_t button_handle = s_te_obj->sleep_handle->wakeup_handle; + ret = touch_pad_sleep_channel_enable(button_handle->device->channel, false); + TE_CHECK(ret == ESP_OK, ret); + esp_sleep_disable_wakeup_source(ESP_SLEEP_WAKEUP_TOUCHPAD); + s_te_obj->sleep_handle->wakeup_handle = NULL; + TE_FREE_AND_NULL(s_te_obj->sleep_handle); + return ESP_OK; +} + +esp_err_t touch_element_sleep_enable_wakeup_calibration(touch_elem_handle_t element_handle, bool en) +{ + TE_CHECK(element_handle != NULL, ESP_ERR_INVALID_ARG); + if (is_button_object_handle(element_handle)) { + button_enable_wakeup_calibration(element_handle, en); + } else if (is_slider_object_handle(element_handle)) { + slider_enable_wakeup_calibration(element_handle, en); + } else if (is_matrix_object_handle(element_handle)) { + matrix_enable_wakeup_calibration(element_handle, en); + } else { + return ESP_ERR_NOT_FOUND; + } + return ESP_OK; +} diff --git a/components/touch_element/touch_matrix.c b/components/touch_element/touch_matrix.c index 8b61b07baf..1bc554834e 100644 --- a/components/touch_element/touch_matrix.c +++ b/components/touch_element/touch_matrix.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -335,6 +335,20 @@ static esp_err_t matrix_object_remove_instance(te_matrix_handle_t matrix_handle) return ret; } +bool is_matrix_object_handle(touch_elem_handle_t element_handle) +{ + te_matrix_handle_list_t *item; + xSemaphoreTake(s_te_mat_obj->mutex, portMAX_DELAY); + SLIST_FOREACH(item, &s_te_mat_obj->handle_list, next) { + if (element_handle == item->matrix_handle) { + xSemaphoreGive(s_te_mat_obj->mutex); + return true; + } + } + xSemaphoreGive(s_te_mat_obj->mutex); + return false; +} + static bool matrix_channel_check(te_matrix_handle_t matrix_handle, touch_pad_t channel_num) { te_dev_t *device; @@ -403,6 +417,13 @@ static inline void matrix_dispatch(te_matrix_handle_t matrix_handle, touch_elem_ } } +void matrix_enable_wakeup_calibration(te_matrix_handle_t matrix_handle, bool en) +{ + for (int idx = 0; idx < matrix_handle->x_channel_num + matrix_handle->y_channel_num; ++idx) { + matrix_handle->device[idx]->is_use_last_threshold = !en; + } +} + /** * @brief Scan the matrix channel * diff --git a/components/touch_element/touch_slider.c b/components/touch_element/touch_slider.c index 15acaa8802..ad506597e0 100644 --- a/components/touch_element/touch_slider.c +++ b/components/touch_element/touch_slider.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -328,6 +328,20 @@ static esp_err_t slider_object_remove_instance(te_slider_handle_t slider_handle) return ret; } +bool is_slider_object_handle(touch_elem_handle_t element_handle) +{ + te_slider_handle_list_t *item; + xSemaphoreTake(s_te_sld_obj->mutex, portMAX_DELAY); + SLIST_FOREACH(item, &s_te_sld_obj->handle_list, next) { + if (element_handle == item->slider_handle) { + xSemaphoreGive(s_te_sld_obj->mutex); + return true; + } + } + xSemaphoreGive(s_te_sld_obj->mutex); + return false; +} + static bool slider_channel_check(te_slider_handle_t slider_handle, touch_pad_t channel_num) { te_dev_t *device; @@ -406,6 +420,13 @@ static inline void slider_dispatch(te_slider_handle_t slider_handle, touch_elem_ } } +void slider_enable_wakeup_calibration(te_slider_handle_t slider_handle, bool en) +{ + for (int idx = 0; idx < slider_handle->channel_sum; ++idx) { + slider_handle->device[idx]->is_use_last_threshold = !en; + } +} + /** * @brief Slider process * diff --git a/components/ulp/.build-test-rules.yml b/components/ulp/.build-test-rules.yml index 919b2e008b..8316bbd3fb 100644 --- a/components/ulp/.build-test-rules.yml +++ b/components/ulp/.build-test-rules.yml @@ -5,5 +5,5 @@ components/ulp/test_apps/ulp_fsm: - if: SOC_ULP_SUPPORTED == 1 components/ulp/test_apps/ulp_riscv: - enable: - - if: SOC_RISCV_COPROC_SUPPORTED == 1 + disable: + - if: SOC_RISCV_COPROC_SUPPORTED != 1 diff --git a/components/ulp/CMakeLists.txt b/components/ulp/CMakeLists.txt index ebbab38890..cdf18b5eb7 100644 --- a/components/ulp/CMakeLists.txt +++ b/components/ulp/CMakeLists.txt @@ -6,7 +6,8 @@ set(includes "") if(CONFIG_SOC_ULP_SUPPORTED OR CONFIG_SOC_RISCV_COPROC_SUPPORTED) list(APPEND srcs - "ulp_common/ulp_common.c") + "ulp_common/ulp_common.c" + "ulp_common/ulp_adc.c") list(APPEND includes ulp_common/include @@ -24,10 +25,12 @@ if(CONFIG_SOC_ULP_SUPPORTED OR CONFIG_SOC_RISCV_COPROC_SUPPORTED) elseif(CONFIG_ULP_COPROC_TYPE_RISCV) list(APPEND srcs "ulp_riscv/ulp_riscv.c" - "ulp_riscv/ulp_riscv_adc.c") + "ulp_riscv/ulp_riscv_lock.c" + "ulp_riscv/ulp_riscv_i2c.c") list(APPEND includes - ulp_riscv/include) + ulp_riscv/include + ulp_riscv/shared/include) endif() endif() diff --git a/components/ulp/cmake/CMakeLists.txt b/components/ulp/cmake/CMakeLists.txt index 028dfdeb98..f1f5b88341 100644 --- a/components/ulp/cmake/CMakeLists.txt +++ b/components/ulp/cmake/CMakeLists.txt @@ -1,44 +1,16 @@ cmake_minimum_required(VERSION 3.16) -include(${IDF_PATH}/tools/cmake/utilities.cmake) +include(${IDF_PATH}/tools/cmake/idf.cmake) project(${ULP_APP_NAME} ASM C) +add_executable(${ULP_APP_NAME}) option(ULP_COCPU_IS_RISCV "Use RISC-V based ULP" OFF) -set(version_pattern "[a-z0-9\.-]+") - -# Check assembler version -execute_process( - COMMAND ${CMAKE_ASM_COMPILER} --version - OUTPUT_VARIABLE as_output - ERROR_QUIET) - -string(REGEX MATCH "\\(GNU Binutils\\) (${version_pattern})" as_version ${as_output}) -set(as_version ${CMAKE_MATCH_1}) - - message(STATUS "Building ULP app ${ULP_APP_NAME}") -if(ULP_COCPU_IS_RISCV) - set(ULP_LD_TEMPLATE ${IDF_PATH}/components/ulp/ld/ulp_riscv.ld) -else() - message(STATUS "ULP assembler version: ${as_version}") - - # Check the supported assembler version - file(STRINGS ${IDF_PATH}/components/ulp/toolchain_ulp_version.mk version_file_contents) - string(REGEX MATCH - "SUPPORTED_ULP_ASSEMBLER_VERSION = (${version_pattern})" - as_supported_version - ${version_file_contents}) - set(as_supported_version ${CMAKE_MATCH_1}) - - if(NOT as_version STREQUAL as_supported_version) - message(WARNING "WARNING: ULP assembler version ${as_version} is not supported. Expected to see version: \ - ${as_supported_version}. Please check ESP-IDF ULP setup instructions and update \ - the toolchain, or proceed at your own risk.") - endif() - - set(ULP_LD_TEMPLATE ${IDF_PATH}/components/ulp/ld/ulp_fsm.ld) +# Check the supported assembler version +if(NOT ULP_COCPU_IS_RISCV) + check_expected_tool_version("esp32ulp-elf" ${CMAKE_ASM_COMPILER}) endif() @@ -53,20 +25,27 @@ list(APPEND ULP_PREPROCESSOR_ARGS ${component_includes}) list(APPEND ULP_PREPROCESSOR_ARGS -I${COMPONENT_DIR}) list(APPEND ULP_PREPROCESSOR_ARGS -I${sdkconfig_dir}) -include_directories(${COMPONENT_INCLUDES}) +target_include_directories(${ULP_APP_NAME} PRIVATE ${COMPONENT_INCLUDES}) list(APPEND ULP_PREPROCESSOR_ARGS -D__ASSEMBLER__) -# Preprocess linker script, pre-linking +# Pre-process the linker script +if(ULP_COCPU_IS_RISCV) + set(ULP_LD_TEMPLATE ${IDF_PATH}/components/ulp/ld/ulp_riscv.ld) +else() + set(ULP_LD_TEMPLATE ${IDF_PATH}/components/ulp/ld/ulp_fsm.ld) +endif() get_filename_component(ULP_LD_SCRIPT ${ULP_LD_TEMPLATE} NAME) add_custom_command(OUTPUT ${ULP_LD_SCRIPT} COMMAND ${CMAKE_C_COMPILER} -E -P -xc -o ${ULP_LD_SCRIPT} ${ULP_PREPROCESSOR_ARGS} ${ULP_LD_TEMPLATE} WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - DEPENDS ${ULP_LD_TEMPLATE} ${SDKCONFIG_HEADER} + MAIN_DEPENDENCY ${ULP_LD_TEMPLATE} + DEPENDS ${SDKCONFIG_HEADER} + COMMENT "Generating ${ULP_LD_SCRIPT} linker script..." VERBATIM) -add_custom_target(${ULP_APP_NAME}_ld_script - DEPENDS ${ULP_LD_SCRIPT} - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}) +add_custom_target(ld_script DEPENDS ${ULP_LD_SCRIPT}) +add_dependencies(${ULP_APP_NAME} ld_script) +target_link_options(${ULP_APP_NAME} PRIVATE SHELL:-T ${CMAKE_CURRENT_BINARY_DIR}/${ULP_LD_SCRIPT}) # To avoid warning "Manually-specified variables were not used by the project" set(bypassWarning "${IDF_TARGET}") @@ -75,33 +54,20 @@ if(ULP_COCPU_IS_RISCV) list(APPEND ULP_S_SOURCES "${IDF_PATH}/components/ulp/ulp_riscv/ulp_core/start.S" "${IDF_PATH}/components/ulp/ulp_riscv/ulp_core/ulp_riscv_adc.c" + "${IDF_PATH}/components/ulp/ulp_riscv/ulp_core/ulp_riscv_lock.c" "${IDF_PATH}/components/ulp/ulp_riscv/ulp_core/ulp_riscv_uart.c" "${IDF_PATH}/components/ulp/ulp_riscv/ulp_core/ulp_riscv_print.c" + "${IDF_PATH}/components/ulp/ulp_riscv/ulp_core/ulp_riscv_i2c.c" "${IDF_PATH}/components/ulp/ulp_riscv/ulp_core/ulp_riscv_utils.c") - #dummy loop to force pre-processed linker file generation: - foreach(ulp_s_source ${ULP_S_SOURCES}) - set(noop ${ulp_s_source}) - - add_custom_command(OUTPUT ${noop} - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - COMMAND cmake -E echo - DEPENDS ${ULP_LD_SCRIPT} - ) - - set_source_files_properties(${noop} PROPERTIES NOOP_PROPERTY ${ULP_LD_SCRIPT}) - endforeach() - - #creates the executable: - add_executable(${ULP_APP_NAME} ${ULP_S_SOURCES}) - set(DUMP_SYMBOL_ARGS -g) - set(MAP_GEN_EXTRA_ARGS --riscv) - set(EXTRA_LINKER_ARGS "-nostartfiles") - list(APPEND EXTRA_LINKER_ARGS "-Wl,--gc-sections") - list(APPEND EXTRA_LINKER_ARGS "-Wl,-Map=\"${CMAKE_CURRENT_BINARY_DIR}/${ULP_APP_NAME}.map\"") + target_link_options(${ULP_APP_NAME} PRIVATE "-nostartfiles") + target_link_options(${ULP_APP_NAME} PRIVATE -Wl,--gc-sections) + target_link_options(${ULP_APP_NAME} PRIVATE -Wl,-Map=${CMAKE_CURRENT_BINARY_DIR}/${ULP_APP_NAME}.map) + target_sources(${ULP_APP_NAME} PRIVATE ${ULP_S_SOURCES}) #Makes the csr utillies for riscv visible: - target_include_directories(${ULP_APP_NAME} PRIVATE "${IDF_PATH}/components/ulp/ulp_riscv/ulp_core/include") - target_link_libraries(${ULP_APP_NAME} "-T \"${IDF_PATH}/components/ulp/ld/${IDF_TARGET}.periperals.ld\"") + target_include_directories(${ULP_APP_NAME} PRIVATE "${IDF_PATH}/components/ulp/ulp_riscv/ulp_core/include" + "${IDF_PATH}/components/ulp/ulp_riscv/shared/include") + target_link_options(${ULP_APP_NAME} PRIVATE SHELL:-T ${IDF_PATH}/components/ulp/ld/${IDF_TARGET}.peripherals.ld) target_compile_definitions(${ULP_APP_NAME} PRIVATE IS_ULP_COCPU) else() @@ -114,7 +80,7 @@ else() WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} COMMAND ${CMAKE_C_COMPILER} -E -P -xc ${ULP_PREPROCESSOR_ARGS} -o ${ulp_ps_output} ${ulp_s_source} - DEPENDS ${ulp_s_source} ${ULP_LD_SCRIPT} + DEPENDS ${ulp_s_source} VERBATIM) # During assembly file compilation, output listing files as well. set_source_files_properties(${ulp_ps_output} @@ -123,17 +89,18 @@ else() list(APPEND ULP_PS_SOURCES ${ulp_ps_output}) endforeach() - # Create an executable - add_executable(${ULP_APP_NAME} ${ULP_PS_SOURCES}) - set(DUMP_SYMBOL_ARGS -g -f posix) - set(MAP_GEN_EXTRA_ARGS .) - set(EXTRA_LINKER_ARGS "-Map=\"${CMAKE_CURRENT_BINARY_DIR}/${ULP_APP_NAME}.map\"") + target_link_options(${ULP_APP_NAME} PRIVATE -Map=${CMAKE_CURRENT_BINARY_DIR}/${ULP_APP_NAME}.map) + target_sources(${ULP_APP_NAME} PRIVATE ${ULP_PS_SOURCES}) endif() +# Currently all the supported targets have the same base address of the ULP memory in the CPU address space. +# Modify this or pull this out of some SoC header file, if that becomes necessary. +set(ULP_BASE_ADDR "0x50000000") + # Dump the list of global symbols in a convenient format add_custom_command(OUTPUT ${ULP_APP_NAME}.sym - COMMAND ${CMAKE_NM} ${DUMP_SYMBOL_ARGS} $ > ${ULP_APP_NAME}.sym + COMMAND ${CMAKE_NM} -f posix -g $ > ${ULP_APP_NAME}.sym DEPENDS ${ULP_APP_NAME} WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}) @@ -144,7 +111,7 @@ add_custom_command(OUTPUT ${ULP_APP_NAME}.bin WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}) add_custom_command(OUTPUT ${ULP_APP_NAME}.ld ${ULP_APP_NAME}.h - COMMAND ${ULP_MAP_GEN} ${MAP_GEN_EXTRA_ARGS} -s ${ULP_APP_NAME}.sym -o ${ULP_APP_NAME} + COMMAND ${ULP_MAP_GEN} -s ${ULP_APP_NAME}.sym -o ${ULP_APP_NAME} --base ${ULP_BASE_ADDR} DEPENDS ${ULP_APP_NAME}.sym WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}) @@ -155,7 +122,3 @@ add_custom_target(build ${CMAKE_CURRENT_BINARY_DIR}/${ULP_APP_NAME}.ld ${CMAKE_CURRENT_BINARY_DIR}/${ULP_APP_NAME}.h WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}) - -target_link_libraries(${ULP_APP_NAME} "-T\"${CMAKE_CURRENT_BINARY_DIR}/${ULP_LD_SCRIPT}\"") -target_link_libraries(${ULP_APP_NAME} ${EXTRA_LINKER_ARGS}) -set_target_properties(${ULP_APP_NAME} PROPERTIES LINK_DEPENDS ${ULP_LD_SCRIPT}) diff --git a/components/ulp/cmake/toolchain-esp32-ulp.cmake b/components/ulp/cmake/toolchain-esp32-ulp.cmake index 56d53c07fb..401de56062 100644 --- a/components/ulp/cmake/toolchain-esp32-ulp.cmake +++ b/components/ulp/cmake/toolchain-esp32-ulp.cmake @@ -1,19 +1,16 @@ # CMake toolchain file for ULP - set(CMAKE_SYSTEM_NAME Generic) # Compiler is only used for preprocessing set(CMAKE_C_COMPILER "xtensa-esp32-elf-gcc") +set(CMAKE_CXX_COMPILER "xtensa-esp32-elf-g++") set(CMAKE_ASM_COMPILER "esp32ulp-elf-as") set(CMAKE_LINKER "esp32ulp-elf-ld") -if(NOT ASM_DIALECT) - set(ASM_DIALECT "") -endif() set(CMAKE_ASM${ASM_DIALECT}_COMPILE_OBJECT "${CMAKE_ASM${ASM_DIALECT}_COMPILER} \ - -o -c ") + --mcpu=esp32 -o -c ") set(CMAKE_EXE_LINKER_FLAGS "-A elf32-esp32ulp -nostdlib" CACHE STRING "ULP Linker Base Flags") set(CMAKE_ASM_LINK_EXECUTABLE "${CMAKE_LINKER} \ -o ") diff --git a/components/ulp/cmake/toolchain-esp32s2-ulp.cmake b/components/ulp/cmake/toolchain-esp32s2-ulp.cmake index 4383d5432a..a2f81eb832 100644 --- a/components/ulp/cmake/toolchain-esp32s2-ulp.cmake +++ b/components/ulp/cmake/toolchain-esp32s2-ulp.cmake @@ -1,15 +1,15 @@ # CMake toolchain file for ULP - set(CMAKE_SYSTEM_NAME Generic) # Compiler is only used for preprocessing set(CMAKE_C_COMPILER "xtensa-esp32s2-elf-gcc") +set(CMAKE_CXX_COMPILER "xtensa-esp32s2-elf-g++") -set(CMAKE_ASM_COMPILER "esp32s2ulp-elf-as") -set(CMAKE_LINKER "esp32s2ulp-elf-ld") +set(CMAKE_ASM_COMPILER "esp32ulp-elf-as") +set(CMAKE_LINKER "esp32ulp-elf-ld") set(CMAKE_ASM${ASM_DIALECT}_COMPILE_OBJECT "${CMAKE_ASM${ASM_DIALECT}_COMPILER} \ - -o -c ") + --mcpu=esp32s2 -o -c ") set(CMAKE_EXE_LINKER_FLAGS "-A elf32-esp32s2ulp -nostdlib" CACHE STRING "ULP Linker Base Flags") set(CMAKE_ASM_LINK_EXECUTABLE "${CMAKE_LINKER} \ -o ") diff --git a/components/ulp/cmake/toolchain-esp32s3-ulp.cmake b/components/ulp/cmake/toolchain-esp32s3-ulp.cmake index 4f1995966a..0e2c218509 100644 --- a/components/ulp/cmake/toolchain-esp32s3-ulp.cmake +++ b/components/ulp/cmake/toolchain-esp32s3-ulp.cmake @@ -1,16 +1,16 @@ # CMake toolchain file for ULP - set(CMAKE_SYSTEM_NAME Generic) # Compiler is only used for preprocessing -#TODO: Update toolchain to be used once esp32s3 support is added to binutils -set(CMAKE_C_COMPILER "xtensa-esp32s2-elf-gcc") +set(CMAKE_C_COMPILER "xtensa-esp32s3-elf-gcc") +set(CMAKE_CXX_COMPILER "xtensa-esp32s3-elf-g++") -set(CMAKE_ASM_COMPILER "esp32s2ulp-elf-as") -set(CMAKE_LINKER "esp32s2ulp-elf-ld") +set(CMAKE_ASM_COMPILER "esp32ulp-elf-as") +set(CMAKE_LINKER "esp32ulp-elf-ld") +# Use ESP32-S2 ULP tools here, because ESP32-S3 uses the same ULP coprocessor type set(CMAKE_ASM${ASM_DIALECT}_COMPILE_OBJECT "${CMAKE_ASM${ASM_DIALECT}_COMPILER} \ - -o -c ") + --mcpu=esp32s2 -o -c ") set(CMAKE_EXE_LINKER_FLAGS "-A elf32-esp32s2ulp -nostdlib" CACHE STRING "ULP Linker Base Flags") set(CMAKE_ASM_LINK_EXECUTABLE "${CMAKE_LINKER} \ -o ") diff --git a/components/ulp/esp32ulp_mapgen.py b/components/ulp/esp32ulp_mapgen.py index bc36737b63..382752269c 100755 --- a/components/ulp/esp32ulp_mapgen.py +++ b/components/ulp/esp32ulp_mapgen.py @@ -2,77 +2,72 @@ # esp32ulp_mapgen utility converts a symbol list provided by nm into an export script # for the linker and a header file. # -# Copyright (c) 2016-2017 Espressif Systems (Shanghai) PTE LTD. -# Distributed under the terms of Apache License v2.0 found in the top-level LICENSE file. +# SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 from __future__ import print_function -from optparse import OptionParser +import argparse +import os +import textwrap +import typing -BASE_ADDR = 0x50000000 +UTIL = os.path.basename(__file__) -def gen_ld_h_from_sym(f_sym, f_ld, f_h): - f_ld.write('/* Variable definitions for ESP32ULP linker\n') - f_ld.write(' * This file is generated automatically by esp32ulp_mapgen.py utility.\n') - f_ld.write(' */\n\n') - f_h.write('// Variable definitions for ESP32ULP\n') - f_h.write('// This file is generated automatically by esp32ulp_mapgen.py utility\n\n') - f_h.write('#pragma once\n\n') +def gen_ld_h_from_sym(f_sym: typing.TextIO, f_ld: typing.TextIO, f_h: typing.TextIO, base_addr: int) -> None: + f_ld.write(textwrap.dedent( + f""" + /* ULP variable definitions for the linker. + * This file is generated automatically by {UTIL} utility. + */ + """ + )) + f_h.write(textwrap.dedent( + f""" + /* ULP variable definitions for the compiler. + * This file is generated automatically by {UTIL} utility. + */ + #pragma once + #ifdef __cplusplus + extern "C" {{ + #endif + """ + )) for line in f_sym: - name, _, addr_str = line.split(' ', 2) - addr = int(addr_str, 16) + BASE_ADDR + # NM "posix" format output has the following structure: + # symbol_name symbol_type addr_hex [size_hex] + parts = line.split() + name = parts[0] + addr = int(parts[2], 16) + base_addr f_h.write('extern uint32_t ulp_{0};\n'.format(name)) f_ld.write('PROVIDE ( ulp_{0} = 0x{1:08x} );\n'.format(name, addr)) - -def gen_ld_h_from_sym_riscv(f_sym, f_ld, f_h): - f_ld.write('/* Variable definitions for ESP32ULP linker\n') - f_ld.write(' * This file is generated automatically by esp32ulp_mapgen.py utility.\n') - f_ld.write(' */\n\n') - f_h.write('// Variable definitions for ESP32ULP\n') - f_h.write('// This file is generated automatically by esp32ulp_mapgen.py utility\n\n') - f_h.write('#pragma once\n\n') - - for line in f_sym: - addr_str, _, name = line.split() - addr = int(addr_str, 16) + BASE_ADDR - f_h.write('extern uint32_t ulp_{0};\n'.format(name)) - f_ld.write('PROVIDE ( ulp_{0} = 0x{1:08x} );\n'.format(name, addr)) + f_h.write(textwrap.dedent( + """ + #ifdef __cplusplus + } + #endif + """ + )) -def main(): +def main() -> None: description = ('This application generates .h and .ld files for symbols defined in input file. ' 'The input symbols file can be generated using nm utility like this: ' - 'esp32-ulp-nm -g -f posix > ') + 'nm -g -f posix > ') - parser = OptionParser(description=description) - parser.add_option('-s', '--symfile', dest='symfile', - help='symbols file name', metavar='SYMFILE') - parser.add_option('-o', '--outputfile', dest='outputfile', - help='destination .h and .ld files name prefix', metavar='OUTFILE') + parser = argparse.ArgumentParser(description=description) + parser.add_argument('-s', '--symfile', required=True, help='symbols file name', metavar='SYMFILE', type=argparse.FileType('r')) + parser.add_argument('-o', '--outputfile', required=True, help='destination .h and .ld files name prefix', metavar='OUTFILE') + parser.add_argument('--base-addr', required=True, help='base address of the ULP memory, to be added to each symbol') - parser.add_option('--riscv', action='store_true', help='use format for ulp riscv .sym file') + args = parser.parse_args() - (options, args) = parser.parse_args() - if options.symfile is None: - parser.print_help() - return 1 - - if options.outputfile is None: - parser.print_help() - return 1 - - if options.riscv: - with open(options.outputfile + '.h', 'w') as f_h, open(options.outputfile + '.ld', 'w') as f_ld, open(options.symfile) as f_sym: - gen_ld_h_from_sym_riscv(f_sym, f_ld, f_h) - return 0 - - with open(options.outputfile + '.h', 'w') as f_h, open(options.outputfile + '.ld', 'w') as f_ld, open(options.symfile) as f_sym: - gen_ld_h_from_sym(f_sym, f_ld, f_h) - return 0 + with open(args.outputfile + '.h', 'w') as f_h, open(args.outputfile + '.ld', 'w') as f_ld: + gen_ld_h_from_sym(args.symfile, f_ld, f_h, int(args.base_addr, 0)) if __name__ == '__main__': - exit(main()) + main() diff --git a/components/ulp/ld/esp32s2.periperals.ld b/components/ulp/ld/esp32s2.peripherals.ld similarity index 87% rename from components/ulp/ld/esp32s2.periperals.ld rename to components/ulp/ld/esp32s2.peripherals.ld index 391b20c1c1..291467eb1a 100644 --- a/components/ulp/ld/esp32s2.periperals.ld +++ b/components/ulp/ld/esp32s2.peripherals.ld @@ -7,3 +7,4 @@ PROVIDE ( RTCCNTL = 0x8000 ); PROVIDE ( RTCIO = 0xA400 ); PROVIDE ( SENS = 0xC800 ); +PROVIDE ( RTC_I2C = 0x8C00 ); diff --git a/components/ulp/ld/esp32s3.periperals.ld b/components/ulp/ld/esp32s3.peripherals.ld similarity index 87% rename from components/ulp/ld/esp32s3.periperals.ld rename to components/ulp/ld/esp32s3.peripherals.ld index 391b20c1c1..5d0753e011 100644 --- a/components/ulp/ld/esp32s3.periperals.ld +++ b/components/ulp/ld/esp32s3.peripherals.ld @@ -7,3 +7,4 @@ PROVIDE ( RTCCNTL = 0x8000 ); PROVIDE ( RTCIO = 0xA400 ); PROVIDE ( SENS = 0xC800 ); +PROVIDE ( RTC_I2C = 0xEC00 ); diff --git a/components/ulp/test_apps/ulp_fsm/main/test_ulp.c b/components/ulp/test_apps/ulp_fsm/main/test_ulp.c index e3386e584f..7f1efad04a 100644 --- a/components/ulp/test_apps/ulp_fsm/main/test_ulp.c +++ b/components/ulp/test_apps/ulp_fsm/main/test_ulp.c @@ -205,7 +205,7 @@ TEST_CASE("ULP FSM light-sleep wakeup test", "[ulp]") TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_ULP); } -TEST_CASE("ULP FSM deep-sleep wakeup test", "[ulp][reset=SW_CPU_RESET][ignore]") +TEST_CASE("ULP FSM deep-sleep wakeup test", "[ulp][ulp_deep_sleep_wakeup]") { assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig"); @@ -389,7 +389,7 @@ TEST_CASE("ULP FSM I_WR_REG instruction test", "[ulp]") } -TEST_CASE("ULP FSM controls RTC_IO", "[ulp][ignore]") +TEST_CASE("ULP FSM controls RTC_IO", "[ulp][ulp_deep_sleep_wakeup]") { assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig"); @@ -455,7 +455,7 @@ TEST_CASE("ULP FSM controls RTC_IO", "[ulp][ignore]") UNITY_TEST_FAIL(__LINE__, "Should not get here!"); } -TEST_CASE("ULP FSM power consumption in deep sleep", "[ulp][ignore]") +TEST_CASE("ULP FSM power consumption in deep sleep", "[ulp][ulp_deep_sleep_wakeup]") { assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 4 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig"); @@ -555,7 +555,7 @@ TEST_CASE("ULP FSM timer setting", "[ulp]") } #if !DISABLED_FOR_TARGETS(ESP32) -TEST_CASE("ULP FSM can use temperature sensor (TSENS) in deep sleep", "[ulp][ignore]") +TEST_CASE("ULP FSM can use temperature sensor (TSENS) in deep sleep", "[ulp][ulp_deep_sleep_wakeup]") { assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig"); @@ -622,7 +622,7 @@ TEST_CASE("ULP FSM can use temperature sensor (TSENS) in deep sleep", "[ulp][ign } #endif //#if !DISABLED_FOR_TARGETS(ESP32) -TEST_CASE("ULP FSM can use ADC in deep sleep", "[ulp][ignore]") +TEST_CASE("ULP FSM can use ADC in deep sleep", "[ulp][ulp_deep_sleep_wakeup]") { assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig"); diff --git a/components/ulp/test_apps/ulp_fsm/pytest_ulp_fsm_app.py b/components/ulp/test_apps/ulp_fsm/pytest_ulp_fsm_app.py index c6f683587a..0377e470e6 100644 --- a/components/ulp/test_apps/ulp_fsm/pytest_ulp_fsm_app.py +++ b/components/ulp/test_apps/ulp_fsm/pytest_ulp_fsm_app.py @@ -11,5 +11,56 @@ from pytest_embedded import Dut @pytest.mark.generic def test_ulp_fsm(dut: Dut) -> None: dut.expect('Press ENTER to see the list of tests') - dut.write('![ignore]') + dut.write('![ulp_deep_sleep_wakeup]') dut.expect_unity_test_output() + + +# Run all deepsleep wakeup tests one after the other instead of running them all with the `ulp_deep_sleep_wakeup` tag. +# This makes sure that all tests are run even after one test causes a system reset. +@pytest.mark.esp32 +@pytest.mark.esp32s2 +@pytest.mark.esp32s3 +@pytest.mark.generic +def test_ulp_fsm_deep_sleep_wakeup(dut: Dut) -> None: + dut.expect('Press ENTER to see the list of tests') + dut.write('"ULP FSM deep-sleep wakeup test"') + dut.expect('rst:0x5') + + +@pytest.mark.esp32 +@pytest.mark.esp32s2 +@pytest.mark.esp32s3 +@pytest.mark.generic +def test_ulp_fsm_rtc_io(dut: Dut) -> None: + dut.expect('Press ENTER to see the list of tests') + dut.write('"ULP FSM controls RTC_IO"') + dut.expect('rst:0x5') + + +@pytest.mark.esp32 +@pytest.mark.esp32s2 +@pytest.mark.esp32s3 +@pytest.mark.generic +def test_ulp_fsm_deep_sleep_power_consumption(dut: Dut) -> None: + dut.expect('Press ENTER to see the list of tests') + dut.write('"ULP FSM power consumption in deep sleep"') + dut.expect('rst:0x5') + + +@pytest.mark.esp32s2 +@pytest.mark.esp32s3 +@pytest.mark.generic +def test_ulp_fsm_tsens(dut: Dut) -> None: + dut.expect('Press ENTER to see the list of tests') + dut.write('"ULP FSM can use temperature sensor (TSENS) in deep sleep"') + dut.expect('rst:0x5') + + +@pytest.mark.esp32 +@pytest.mark.esp32s2 +@pytest.mark.esp32s3 +@pytest.mark.generic +def test_ulp_fsm_adc(dut: Dut) -> None: + dut.expect('Press ENTER to see the list of tests') + dut.write('"ULP FSM can use ADC in deep sleep"') + dut.expect('rst:0x5') diff --git a/components/ulp/test_apps/ulp_riscv/main/CMakeLists.txt b/components/ulp/test_apps/ulp_riscv/main/CMakeLists.txt index 3535f63068..3e153055b5 100644 --- a/components/ulp/test_apps/ulp_riscv/main/CMakeLists.txt +++ b/components/ulp/test_apps/ulp_riscv/main/CMakeLists.txt @@ -2,6 +2,7 @@ set(app_sources "test_app_main.c" "test_ulp_riscv.c") set(ulp_sources "ulp/test_main.c") idf_component_register(SRCS ${app_sources} + INCLUDE_DIRS "ulp" REQUIRES ulp unity WHOLE_ARCHIVE) diff --git a/components/ulp/test_apps/ulp_riscv/main/test_ulp_riscv.c b/components/ulp/test_apps/ulp_riscv/main/test_ulp_riscv.c index 16c0211444..95484f13bb 100644 --- a/components/ulp/test_apps/ulp_riscv/main/test_ulp_riscv.c +++ b/components/ulp/test_apps/ulp_riscv/main/test_ulp_riscv.c @@ -12,27 +12,14 @@ #include "soc/sens_reg.h" #include "soc/rtc_periph.h" #include "ulp_riscv.h" +#include "ulp_riscv_lock.h" #include "ulp_test_app.h" +#include "ulp_test_shared.h" #include "unity.h" #include #include "freertos/FreeRTOS.h" #include "freertos/task.h" -typedef enum{ - RISCV_READ_WRITE_TEST = 1, - RISCV_DEEP_SLEEP_WAKEUP_TEST, - RISCV_LIGHT_SLEEP_WAKEUP_TEST, - RISCV_STOP_TEST, - RISCV_NO_COMMAND, -} riscv_test_commands_t; - -typedef enum { - RISCV_COMMAND_OK = 1, - RISCV_COMMAND_NOK, - RISCV_COMMAND_INVALID, -} riscv_test_command_reply_t; - -#define XOR_MASK 0xDEADBEEF #define ULP_WAKEUP_PERIOD 1000000 // 1 second extern const uint8_t ulp_main_bin_start[] asm("_binary_ulp_test_app_bin_start"); @@ -197,7 +184,7 @@ TEST_CASE("ULP-RISC-V can stop itself and be resumed from the main CPU", "[ulp]" * Keep this test case as the last test case in this suite as a CPU reset occurs. * Add new test cases above in order to ensure they run when all test cases are run together. */ -TEST_CASE("ULP-RISC-V is able to wakeup main CPU from deep sleep", "[ulp][reset=SW_CPU_RESET][ignore]") +TEST_CASE("ULP-RISC-V is able to wakeup main CPU from deep sleep", "[ulp][ulp_deep_sleep_wakeup]") { /* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */ load_and_start_ulp_firmware(); @@ -212,3 +199,31 @@ TEST_CASE("ULP-RISC-V is able to wakeup main CPU from deep sleep", "[ulp][reset= esp_deep_sleep_start(); UNITY_TEST_FAIL(__LINE__, "Should not get here!"); } + +TEST_CASE("ULP-RISC-V mutex", "[ulp]") +{ + /* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */ + load_and_start_ulp_firmware(); + + /* Setup test data */ + ulp_riscv_incrementer = 0; + ulp_main_cpu_reply = RISCV_NO_COMMAND; + ulp_main_cpu_command = RISCV_MUTEX_TEST; + + ulp_riscv_lock_t *lock = (ulp_riscv_lock_t*)&ulp_lock; + + for (int i = 0; i < MUTEX_TEST_ITERATIONS; i++) { + ulp_riscv_lock_acquire(lock); + ulp_riscv_incrementer++; + ulp_riscv_lock_release(lock); + } + + while(ulp_main_cpu_reply != RISCV_COMMAND_OK) { + // Wait for ULP to finish + } + + /* If the variable is protected there should be no race conditions + results should be the sum of increments made by ULP and by main CPU + */ + TEST_ASSERT_EQUAL(2*MUTEX_TEST_ITERATIONS, ulp_riscv_incrementer); +} diff --git a/components/ulp/test_apps/ulp_riscv/main/ulp/test_main.c b/components/ulp/test_apps/ulp_riscv/main/ulp/test_main.c index 16a432571c..1a531cfac2 100644 --- a/components/ulp/test_apps/ulp_riscv/main/ulp/test_main.c +++ b/components/ulp/test_apps/ulp_riscv/main/ulp/test_main.c @@ -9,22 +9,9 @@ #include #include "ulp_riscv_utils.h" #include "ulp_riscv_gpio.h" +#include "ulp_riscv_lock_ulp_core.h" +#include "ulp_test_shared.h" -typedef enum{ - RISCV_READ_WRITE_TEST = 1, - RISCV_DEEP_SLEEP_WAKEUP_TEST, - RISCV_LIGHT_SLEEP_WAKEUP_TEST, - RISCV_STOP_TEST, - RISCV_NO_COMMAND, -} riscv_test_commands_t; - -typedef enum { - RISCV_COMMAND_OK = 1, - RISCV_COMMAND_NOK, - RISCV_COMMAND_INVALID, -} riscv_test_command_reply_t; - -#define XOR_MASK 0xDEADBEEF volatile riscv_test_commands_t main_cpu_command = RISCV_NO_COMMAND; volatile riscv_test_command_reply_t main_cpu_reply = RISCV_COMMAND_INVALID; @@ -33,6 +20,9 @@ volatile uint32_t riscv_test_data_in = 0; volatile uint32_t riscv_test_data_out = 0; volatile uint32_t riscv_counter = 0; +volatile uint32_t riscv_incrementer = 0; +ulp_riscv_lock_t lock; + void handle_commands(riscv_test_commands_t cmd) { riscv_counter++; @@ -87,6 +77,21 @@ void handle_commands(riscv_test_commands_t cmd) break; + case RISCV_MUTEX_TEST: + /* Echo the command ID back to the main CPU */ + command_resp = RISCV_MUTEX_TEST; + + for (int i = 0; i < MUTEX_TEST_ITERATIONS; i++) { + ulp_riscv_lock_acquire(&lock); + riscv_incrementer++; + ulp_riscv_lock_release(&lock); + } + /* Set the command reply status */ + main_cpu_reply = RISCV_COMMAND_OK; + main_cpu_command = RISCV_NO_COMMAND; + + break; + case RISCV_NO_COMMAND: main_cpu_reply = RISCV_COMMAND_OK; break; @@ -99,6 +104,7 @@ void handle_commands(riscv_test_commands_t cmd) int main (void) { + while (1) { handle_commands(main_cpu_command); break; diff --git a/components/ulp/test_apps/ulp_riscv/main/ulp/ulp_test_shared.h b/components/ulp/test_apps/ulp_riscv/main/ulp/ulp_test_shared.h new file mode 100644 index 0000000000..c12f828ad5 --- /dev/null +++ b/components/ulp/test_apps/ulp_riscv/main/ulp/ulp_test_shared.h @@ -0,0 +1,24 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#pragma once + +#define MUTEX_TEST_ITERATIONS 100000 +#define XOR_MASK 0xDEADBEEF + +typedef enum{ + RISCV_READ_WRITE_TEST = 1, + RISCV_DEEP_SLEEP_WAKEUP_TEST, + RISCV_LIGHT_SLEEP_WAKEUP_TEST, + RISCV_STOP_TEST, + RISCV_MUTEX_TEST, + RISCV_NO_COMMAND, +} riscv_test_commands_t; + +typedef enum { + RISCV_COMMAND_OK = 1, + RISCV_COMMAND_NOK, + RISCV_COMMAND_INVALID, +} riscv_test_command_reply_t; diff --git a/components/ulp/test_apps/ulp_riscv/pytest_ulp_riscv.py b/components/ulp/test_apps/ulp_riscv/pytest_ulp_riscv.py index b006e0f341..692c6d55ec 100644 --- a/components/ulp/test_apps/ulp_riscv/pytest_ulp_riscv.py +++ b/components/ulp/test_apps/ulp_riscv/pytest_ulp_riscv.py @@ -10,5 +10,16 @@ from pytest_embedded import Dut @pytest.mark.generic def test_ulp_riscv(dut: Dut) -> None: dut.expect('Press ENTER to see the list of tests') - dut.write('![ignore]') + dut.write('![ulp_deep_sleep_wakeup]') dut.expect_unity_test_output() + + +# Run all deepsleep wakeup tests one after the other instead of running them all with the `ulp_deep_sleep_wakeup` tag. +# This makes sure that all tests are run even after one test causes a system reset. +@pytest.mark.esp32s2 +@pytest.mark.esp32s3 +@pytest.mark.generic +def test_ulp_deep_sleep_wakeup(dut: Dut) -> None: + dut.expect('Press ENTER to see the list of tests') + dut.write('"ULP-RISC-V is able to wakeup main CPU from deep sleep"') + dut.expect('rst:0x5') diff --git a/components/ulp/toolchain_ulp_version.mk b/components/ulp/toolchain_ulp_version.mk deleted file mode 100644 index d835600e43..0000000000 --- a/components/ulp/toolchain_ulp_version.mk +++ /dev/null @@ -1 +0,0 @@ -SUPPORTED_ULP_ASSEMBLER_VERSION = 2.28.51-esp-20191205 diff --git a/components/ulp/ulp_common/include/ulp_adc.h b/components/ulp/ulp_common/include/ulp_adc.h new file mode 100644 index 0000000000..5f1b93967b --- /dev/null +++ b/components/ulp/ulp_common/include/ulp_adc.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "hal/adc_types.h" +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + adc_unit_t adc_n; // ADC Unit + adc_channel_t channel; // ADC channel + adc_atten_t atten; // ADC channel attenuation + adc_bitwidth_t width; // ADC bit width, only used for ADC unit 1 + adc_ulp_mode_t ulp_mode; // ADC ULP Mode +} ulp_adc_cfg_t; // ULP FSM ADC configuration parameters + +/** + * @brief Initialize and calibrate the ADC for use by ULP FSM + * + * @param cfg Configuration parameters + * @return esp_err_t ESP_OK for successful. + */ +esp_err_t ulp_adc_init(const ulp_adc_cfg_t *cfg); + +#ifdef __cplusplus +} +#endif diff --git a/components/ulp/ulp_riscv/ulp_riscv_adc.c b/components/ulp/ulp_common/ulp_adc.c similarity index 72% rename from components/ulp/ulp_riscv/ulp_riscv_adc.c rename to components/ulp/ulp_common/ulp_adc.c index 9241dd9c6a..a46f928eb7 100644 --- a/components/ulp/ulp_riscv/ulp_riscv_adc.c +++ b/components/ulp/ulp_common/ulp_adc.c @@ -4,7 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "ulp_riscv_adc.h" +#include "sdkconfig.h" +#include "ulp_adc.h" #include "esp_err.h" #include "esp_check.h" #include "esp_log.h" @@ -13,9 +14,9 @@ #include "esp_private/esp_sleep_internal.h" #include "esp_private/adc_share_hw_ctrl.h" -static const char *TAG = "ulp_riscv_adc"; +static const char *TAG = "ulp_adc"; -esp_err_t ulp_riscv_adc_init(const ulp_riscv_adc_cfg_t *cfg) +esp_err_t ulp_adc_init(const ulp_adc_cfg_t *cfg) { esp_err_t ret = ESP_OK; @@ -24,10 +25,19 @@ esp_err_t ulp_riscv_adc_init(const ulp_riscv_adc_cfg_t *cfg) //-------------ADC1 Init---------------// adc_oneshot_unit_handle_t adc1_handle; + adc_oneshot_unit_init_cfg_t init_config1 = { .unit_id = cfg->adc_n, - .ulp_mode = ADC_ULP_MODE_RISCV, + .ulp_mode = cfg->ulp_mode, }; + + if (init_config1.ulp_mode == ADC_ULP_MODE_DISABLE) { + /* Default to RISCV for backward compatibility */ + ESP_LOGI(TAG, "No ulp mode specified in cfg struct, default to riscv"); + init_config1.ulp_mode = ADC_ULP_MODE_RISCV; + } + + ESP_ERROR_CHECK(adc_oneshot_new_unit(&init_config1, &adc1_handle)); //-------------ADC1 Config---------------// @@ -38,7 +48,10 @@ esp_err_t ulp_riscv_adc_init(const ulp_riscv_adc_cfg_t *cfg) ESP_ERROR_CHECK(adc_oneshot_config_channel(adc1_handle, cfg->channel, &config)); //Calibrate the ADC +#if SOC_ADC_CALIBRATION_V1_SUPPORTED adc_set_hw_calibration_code(cfg->adc_n, cfg->atten); +#endif + esp_sleep_enable_adc_tsens_monitor(true); err: diff --git a/components/ulp/ulp_common/ulp_common.c b/components/ulp/ulp_common/ulp_common.c index caa48115e8..32307ba729 100644 --- a/components/ulp/ulp_common/ulp_common.c +++ b/components/ulp/ulp_common/ulp_common.c @@ -9,10 +9,10 @@ #include "ulp_common.h" #include "esp_private/esp_clk.h" #include "soc/rtc.h" -#include "soc/rtc_cntl_reg.h" -#include "soc/sens_reg.h" +#include "soc/rtc_cntl_periph.h" #if CONFIG_IDF_TARGET_ESP32 +#include "soc/sens_reg.h" #define ULP_FSM_PREPARE_SLEEP_CYCLES 2 /*!< Cycles spent by FSM preparing ULP for sleep */ #define ULP_FSM_WAKEUP_SLEEP_CYCLES 2 /*!< Cycles spent by FSM waking up ULP from sleep */ #endif diff --git a/components/ulp/ulp_riscv/include/ulp_riscv_adc.h b/components/ulp/ulp_riscv/include/ulp_riscv_adc.h index 05b03264c9..098b7af513 100644 --- a/components/ulp/ulp_riscv/include/ulp_riscv_adc.h +++ b/components/ulp/ulp_riscv/include/ulp_riscv_adc.h @@ -9,24 +9,15 @@ #include "hal/adc_types.h" #include "esp_err.h" +#include "ulp_adc.h" + #ifdef __cplusplus extern "C" { #endif -typedef struct { - adc_unit_t adc_n; // ADC Unit - adc_channel_t channel; // ADC channel - adc_atten_t atten; // ADC channel attenuation - adc_bitwidth_t width; // ADC bit width, only used for ADC unit 1 -} ulp_riscv_adc_cfg_t; // ULP Riscv ADC configuration parameters - -/** - * @brief Initialize and calibrate the ADC for use by ULP RISCV - * - * @param cfg Configuration parameters - * @return esp_err_t ESP_OK for successful. - */ -esp_err_t ulp_riscv_adc_init(const ulp_riscv_adc_cfg_t *cfg); +/* Kept for backwards compatibilty */ +#define ulp_riscv_adc_cfg_t ulp_adc_cfg_t +#define ulp_riscv_adc_init ulp_adc_init #ifdef __cplusplus } diff --git a/components/ulp/ulp_riscv/include/ulp_riscv_i2c.h b/components/ulp/ulp_riscv/include/ulp_riscv_i2c.h new file mode 100644 index 0000000000..d77d2c361b --- /dev/null +++ b/components/ulp/ulp_riscv/include/ulp_riscv_i2c.h @@ -0,0 +1,99 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "hal/gpio_types.h" +#include "esp_err.h" + +typedef struct { + uint32_t sda_io_num; // GPIO pin for SDA signal. Only GPIO#1 or GPIO#3 can be used as the SDA pin. + uint32_t scl_io_num; // GPIO pin for SCL signal. Only GPIO#0 or GPIO#2 can be used as the SCL pin. + bool sda_pullup_en; // SDA line enable internal pullup. Can be configured if external pullup is not used. + bool scl_pullup_en; // SCL line enable internal pullup. Can be configured if external pullup is not used. +} ulp_riscv_i2c_pin_cfg_t; + +typedef struct { + uint32_t scl_low_period; // SCL low period + uint32_t scl_high_period; // SCL high period + uint32_t sda_duty_period; // Period between the SDA switch and the falling edge of SCL + uint32_t scl_start_period; // Waiting time after the START condition + uint32_t scl_stop_period; // Waiting time before the END condition + uint32_t i2c_trans_timeout; // I2C transaction timeout +} ulp_riscv_i2c_timing_cfg_t; + +typedef struct { + ulp_riscv_i2c_pin_cfg_t i2c_pin_cfg; // RTC I2C pin configuration + ulp_riscv_i2c_timing_cfg_t i2c_timing_cfg; // RTC I2C timing configuration +} ulp_riscv_i2c_cfg_t; + +/* Nominal default GPIO settings and timing parametes */ +#define ULP_RISCV_I2C_DEFAULT_CONFIG() \ + { \ + .i2c_pin_cfg.sda_io_num = GPIO_NUM_3, \ + .i2c_pin_cfg.scl_io_num = GPIO_NUM_2, \ + .i2c_pin_cfg.sda_pullup_en = true, \ + .i2c_pin_cfg.scl_pullup_en = true, \ + .i2c_timing_cfg.scl_low_period = 5, \ + .i2c_timing_cfg.scl_high_period = 5, \ + .i2c_timing_cfg.sda_duty_period = 2, \ + .i2c_timing_cfg.scl_start_period = 3, \ + .i2c_timing_cfg.scl_stop_period = 6, \ + .i2c_timing_cfg.i2c_trans_timeout = 20, \ + } + +/** + * @brief Set the I2C slave device address + * + * @param slave_addr I2C slave address (7 bit) + */ +void ulp_riscv_i2c_master_set_slave_addr(uint8_t slave_addr); + +/** + * @brief Set the I2C slave device sub register address + * + * @param slave_reg_addr I2C slave sub register address + */ +void ulp_riscv_i2c_master_set_slave_reg_addr(uint8_t slave_reg_addr); + +/** + * @brief Read from I2C slave device + * + * @note The I2C slave device address must be configured at least once before invoking this API. + * + * @param data_rd Buffer to hold data to be read + * @param size Size of data to be read in bytes + */ +void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size); + +/** + * @brief Write to I2C slave device + * + * @note The I2C slave device address must be configured at least once before invoking this API. + * + * @param data_wr Buffer which holds the data to be written + * @param size Size of data to be written in bytes + */ +void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size); + +/** + * @brief Initialize and configure the RTC I2C for use by ULP RISC-V + * Currently RTC I2C can only be used in master mode + * + * @param cfg Configuration parameters + * @return esp_err_t ESP_OK when successful + */ +esp_err_t ulp_riscv_i2c_master_init(const ulp_riscv_i2c_cfg_t *cfg); + +#ifdef __cplusplus +} +#endif diff --git a/components/ulp/ulp_riscv/include/ulp_riscv_lock.h b/components/ulp/ulp_riscv/include/ulp_riscv_lock.h new file mode 100644 index 0000000000..597e3ed463 --- /dev/null +++ b/components/ulp/ulp_riscv/include/ulp_riscv_lock.h @@ -0,0 +1,38 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ulp_riscv_lock_shared.h" + +/** + * @brief Locks are based on the Peterson's algorithm, https://en.wikipedia.org/wiki/Peterson%27s_algorithm + * + */ + +/** + * @brief Acquire the lock, preventing the ULP from taking until released. Spins until lock is acquired. + * + * @note The lock is only designed for being used by a single thread on the main CPU, + * it is not safe to try to acquire it from multiple threads. + * + * @param lock Pointer to lock struct, shared with ULP + */ +void ulp_riscv_lock_acquire(ulp_riscv_lock_t *lock); + +/** + * @brief Release the lock + * + * @param lock Pointer to lock struct, shared with ULP + */ +void ulp_riscv_lock_release(ulp_riscv_lock_t *lock); + +#ifdef __cplusplus +} +#endif diff --git a/components/ulp/ulp_riscv/shared/include/ulp_riscv_lock_shared.h b/components/ulp/ulp_riscv/shared/include/ulp_riscv_lock_shared.h new file mode 100644 index 0000000000..67c12dac8c --- /dev/null +++ b/components/ulp/ulp_riscv/shared/include/ulp_riscv_lock_shared.h @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enum representing which processor is allowed to enter the critical section + * + */ +typedef enum { + ULP_RISCV_LOCK_TURN_ULP, /*!< ULP's turn to enter the critical section */ + ULP_RISCV_LOCK_TURN_MAIN_CPU, /*!< Main CPU's turn to enter the critical section */ +} ulp_riscv_lock_turn_t; + +/** + * @brief Structure representing a lock shared between ULP and main CPU + * + */ +typedef struct { + volatile bool critical_section_flag_ulp; /*!< ULP wants to enter the critical sections */ + volatile bool critical_section_flag_main_cpu; /*!< Main CPU wants to enter the critical sections */ + volatile ulp_riscv_lock_turn_t turn; /*!< Which CPU is allowed to enter the critical section */ +} ulp_riscv_lock_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_i2c_ulp_core.h b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_i2c_ulp_core.h new file mode 100644 index 0000000000..41383245ea --- /dev/null +++ b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_i2c_ulp_core.h @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/** + * @brief Set the I2C slave device address + * + * @param slave_addr I2C slave address (7 bit) + */ +void ulp_riscv_i2c_master_set_slave_addr(uint8_t slave_addr); + +/** + * @brief Set the I2C slave device sub register address + * + * @param slave_reg_addr I2C slave register address + */ +void ulp_riscv_i2c_master_set_slave_reg_addr(uint8_t slave_reg_addr); + +/** + * @brief Read from I2C slave device + * + * @note The I2C slave device address must be configured at least once before invoking this API. + * + * @param data_rd Buffer to hold data to be read + * @param size Size of data to be read in bytes + */ +void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size); + +/** + * @brief Write to I2C slave device + * + * @note The I2C slave device address must be configured at least once before invoking this API. + * + * @param data_wr Buffer which holds the data to be written + * @param size Size of data to be written in bytes + */ +void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size); + +#ifdef __cplusplus +} +#endif diff --git a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_lock_ulp_core.h b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_lock_ulp_core.h new file mode 100644 index 0000000000..4f403058a1 --- /dev/null +++ b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_lock_ulp_core.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "ulp_riscv_lock_shared.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief Locks are based on the Peterson's algorithm, https://en.wikipedia.org/wiki/Peterson%27s_algorithm + * + */ + +/** + * @brief Acquire the lock, preventing the main CPU from taking until released. Spins until lock is acquired. + * + * @note The lock is only designed for being used by a single thread on the ULP, + * it is not safe to try to acquire it from multiple threads. + * + * @param lock Pointer to lock struct, shared with main CPU + */ +void ulp_riscv_lock_acquire(ulp_riscv_lock_t *lock); + +/** + * @brief Release the lock + * + * @param lock Pointer to lock struct, shared with main CPU + */ +void ulp_riscv_lock_release(ulp_riscv_lock_t *lock); + +#ifdef __cplusplus +} +#endif diff --git a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_i2c.c b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_i2c.c new file mode 100644 index 0000000000..de3f787c57 --- /dev/null +++ b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_i2c.c @@ -0,0 +1,225 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "ulp_riscv_i2c_ulp_core.h" +#include "ulp_riscv_utils.h" +#include "soc/rtc_i2c_reg.h" +#include "soc/rtc_i2c_struct.h" +#include "soc/rtc_io_reg.h" +#include "soc/sens_reg.h" +#include "hal/i2c_ll.h" + +#define I2C_CTRL_SLAVE_ADDR_MASK (0xFF << 0) +#define I2C_CTRL_SLAVE_REG_ADDR_MASK (0xFF << 11) +#define I2C_CTRL_MASTER_TX_DATA_MASK (0xFF << 19) + +#if CONFIG_IDF_TARGET_ESP32S3 +#define ULP_I2C_CMD_RESTART 0 /*! 1) { + /* Read n - 1 bytes */ + ulp_riscv_i2c_format_cmd(cmd_idx++, ULP_I2C_CMD_READ, 0, 0, 1, size - 1); + } + + /* Read last byte + NACK */ + ulp_riscv_i2c_format_cmd(cmd_idx++, ULP_I2C_CMD_READ, 1, 1, 1, 1); + + /* STOP */ + ulp_riscv_i2c_format_cmd(cmd_idx++, ULP_I2C_CMD_STOP, 0, 0, 0, 0); + + /* Configure the RTC I2C controller in read mode */ + SET_PERI_REG_BITS(SENS_SAR_I2C_CTRL_REG, 0x1, 0, 27); + + /* Enable Rx data interrupt */ + SET_PERI_REG_MASK(RTC_I2C_INT_ENA_REG, RTC_I2C_RX_DATA_INT_ENA); + + /* Start RTC I2C transmission */ + SET_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START_FORCE); + SET_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START); + + for (i = 0; i < size; i++) { + /* Poll for RTC I2C Rx Data interrupt bit to be set */ + while (!REG_GET_FIELD(RTC_I2C_INT_ST_REG, RTC_I2C_RX_DATA_INT_ST)) { } + + /* Read the data + * + * Unfortunately, the RTC I2C has no fifo buffer to help us with reading and storing + * multiple bytes of data. Therefore, we need to read one byte at a time and clear the + * Rx interrupt to get ready for the next byte. + */ +#if CONFIG_IDF_TARGET_ESP32S2 + data_rd[i] = REG_GET_FIELD(RTC_I2C_DATA_REG, RTC_I2C_RDATA); +#elif CONFIG_IDF_TARGET_ESP32S3 + data_rd[i] = REG_GET_FIELD(RTC_I2C_DATA_REG, RTC_I2C_I2C_RDATA); +#endif // CONFIG_IDF_TARGET_ESP32S2 + + /* Clear the Rx data interrupt bit */ + SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, RTC_I2C_RX_DATA_INT_CLR); + } + + /* Clear the RTC I2C transmission bits */ + CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START_FORCE); + CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START); +} + +/* + * I2C transactions when master writes one byte of data to the slave device: + * + * |--------|--------|---------|--------|--------|--------|--------|--------|--------| + * | Master | START | SAD + W | | SUB | | DATA | | STOP | + * |--------|--------|---------|--------|--------|--------|--------|--------|--------| + * | Slave | | | ACK | | ACK | | ACK | | + * |--------|--------|---------|--------|--------|--------|--------|--------|--------| + * + * I2C transactions when master writes multiple bytes of data to the slave device: + * + * |--------|--------|---------|--------|--------|--------|--------|--------|--------|--------|--------| + * | Master | START | SAD + W | | SUB | | DATA | | DATA | | STOP | + * |--------|--------|---------|--------|--------|--------|--------|--------|--------|--------|--------| + * | Slave | | | ACK | | ACK | | ACK | | ACK | | + * |--------|--------|---------|--------|--------|--------|--------|--------|--------|--------|--------| + */ +void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size) +{ + uint32_t i = 0; + uint32_t cmd_idx = 0; + + if (size == 0) { + // Quietly return + return; + } + + /* By default, RTC I2C controller is hard wired to use CMD0 and CMD1 registers for write operations */ + cmd_idx = 0; + + /* Write slave addr + reg addr + data */ + ulp_riscv_i2c_format_cmd(cmd_idx++, ULP_I2C_CMD_WRITE, 0, 0, 1, 2 + size); + + /* Stop */ + ulp_riscv_i2c_format_cmd(cmd_idx++, ULP_I2C_CMD_STOP, 0, 0, 0, 0); + + /* Configure the RTC I2C controller in write mode */ + SET_PERI_REG_BITS(SENS_SAR_I2C_CTRL_REG, 0x1, 1, 27); + + /* Enable Tx data interrupt */ + SET_PERI_REG_MASK(RTC_I2C_INT_ENA_REG, RTC_I2C_TX_DATA_INT_ENA); + + for (i = 0; i < size; i++) { + /* Write the data to be transmitted */ + CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, I2C_CTRL_MASTER_TX_DATA_MASK); + SET_PERI_REG_BITS(SENS_SAR_I2C_CTRL_REG, 0xFF, data_wr[i], 19); + + if (i == 0) { + /* Start RTC I2C transmission. (Needn't do it for every byte) */ + SET_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START_FORCE); + SET_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START); + } + + /* Poll for RTC I2C Tx Data interrupt bit to be set */ + while (!REG_GET_FIELD(RTC_I2C_INT_ST_REG, RTC_I2C_TX_DATA_INT_ST)) { } + + /* Clear the Tx data interrupt bit */ + SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, RTC_I2C_TX_DATA_INT_CLR); + } + + /* Clear the RTC I2C transmission bits */ + CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START_FORCE); + CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START); +} diff --git a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_lock.c b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_lock.c new file mode 100644 index 0000000000..d6f3b95dbd --- /dev/null +++ b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_lock.c @@ -0,0 +1,21 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "ulp_riscv_lock.h" +#include "ulp_riscv_lock_shared.h" + +void ulp_riscv_lock_acquire(ulp_riscv_lock_t *lock) +{ + lock->critical_section_flag_ulp = true; + lock->turn = ULP_RISCV_LOCK_TURN_MAIN_CPU; + + while (lock->critical_section_flag_main_cpu && (lock->turn == ULP_RISCV_LOCK_TURN_MAIN_CPU)) { + } +} + +void ulp_riscv_lock_release(ulp_riscv_lock_t *lock) +{ + lock->critical_section_flag_ulp = false; +} diff --git a/components/ulp/ulp_riscv/ulp_riscv_i2c.c b/components/ulp/ulp_riscv/ulp_riscv_i2c.c new file mode 100644 index 0000000000..1f1234ed94 --- /dev/null +++ b/components/ulp/ulp_riscv/ulp_riscv_i2c.c @@ -0,0 +1,441 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "ulp_riscv_i2c.h" +#include "esp_check.h" +#include "soc/rtc_i2c_reg.h" +#include "soc/rtc_i2c_struct.h" +#include "soc/rtc_io_struct.h" +#include "soc/sens_reg.h" +#include "soc/clk_tree_defs.h" +#include "hal/i2c_ll.h" +#include "driver/rtc_io.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + +static const char *RTCI2C_TAG = "ulp_riscv_i2c"; + +#define I2C_CTRL_SLAVE_ADDR_MASK (0xFF << 0) +#define I2C_CTRL_SLAVE_REG_ADDR_MASK (0xFF << 11) +#define I2C_CTRL_MASTER_TX_DATA_MASK (0xFF << 19) + +#if CONFIG_IDF_TARGET_ESP32S3 +#define ULP_I2C_CMD_RESTART 0 /*!i2c_pin_cfg.sda_io_num; + gpio_num_t scl_io_num = cfg->i2c_pin_cfg.scl_io_num; + bool sda_pullup_en = cfg->i2c_pin_cfg.sda_pullup_en; + bool scl_pullup_en = cfg->i2c_pin_cfg.scl_pullup_en; + + /* Verify that the I2C GPIOs are valid */ + ESP_RETURN_ON_ERROR(i2c_gpio_is_cfg_valid(sda_io_num, scl_io_num), RTCI2C_TAG, "RTC I2C GPIO config invalid"); + + /* Initialize SDA Pin */ + ESP_RETURN_ON_ERROR(i2c_configure_io(sda_io_num, sda_pullup_en), RTCI2C_TAG, "RTC I2C SDA pin config failed"); + + /* Initialize SCL Pin */ + ESP_RETURN_ON_ERROR(i2c_configure_io(scl_io_num, scl_pullup_en), RTCI2C_TAG, "RTC I2C SCL pin config failed"); + + /* Route SDA IO signal to the RTC subsystem */ + rtc_io_dev->touch_pad[sda_io_num].mux_sel = 1; + + /* Route SCL IO signal to the RTC subsystem */ + rtc_io_dev->touch_pad[scl_io_num].mux_sel = 1; + + /* Select RTC I2C function for SDA pin */ + rtc_io_dev->touch_pad[sda_io_num].fun_sel = 3; + + /* Select RTC I2C function for SCL pin */ + rtc_io_dev->touch_pad[scl_io_num].fun_sel = 3; + + /* Map the SDA and SCL signals to the RTC I2C controller */ + if (sda_io_num == GPIO_NUM_1) { + rtc_io_dev->sar_i2c_io.sda_sel = 0; + } else { + rtc_io_dev->sar_i2c_io.sda_sel = 1; + } + + if (scl_io_num == GPIO_NUM_0) { + rtc_io_dev->sar_i2c_io.scl_sel = 0; + } else { + rtc_io_dev->sar_i2c_io.scl_sel = 1; + } + + return ESP_OK; +} + +static esp_err_t i2c_set_timing(const ulp_riscv_i2c_cfg_t *cfg) +{ + /* Convert all timing parameters from micro-seconds to period in RTC_FAST_CLK cycles. + * RTC_FAST_CLK = 8.5 MHz for esp32s2 and 17.5 MHz for esp32s3. + * The following calculations approximate the period for each parameter. + */ + uint32_t scl_low_period = MICROSEC_TO_RTC_FAST_CLK(cfg->i2c_timing_cfg.scl_low_period); + uint32_t scl_high_period = MICROSEC_TO_RTC_FAST_CLK(cfg->i2c_timing_cfg.scl_high_period); + uint32_t sda_duty_period = MICROSEC_TO_RTC_FAST_CLK(cfg->i2c_timing_cfg.sda_duty_period); + uint32_t scl_start_period = MICROSEC_TO_RTC_FAST_CLK(cfg->i2c_timing_cfg.scl_start_period); + uint32_t scl_stop_period = MICROSEC_TO_RTC_FAST_CLK(cfg->i2c_timing_cfg.scl_stop_period); + uint32_t i2c_trans_timeout = MICROSEC_TO_RTC_FAST_CLK(cfg->i2c_timing_cfg.i2c_trans_timeout); + uint32_t setup_time_start = (cfg->i2c_timing_cfg.scl_high_period + cfg->i2c_timing_cfg.sda_duty_period); + uint32_t hold_time_start = (cfg->i2c_timing_cfg.scl_start_period - cfg->i2c_timing_cfg.sda_duty_period); + uint32_t setup_time_data = (cfg->i2c_timing_cfg.scl_low_period - cfg->i2c_timing_cfg.sda_duty_period); + + /* Verify timing constraints */ + ESP_RETURN_ON_FALSE((float)cfg->i2c_timing_cfg.scl_low_period > 1.3, ESP_ERR_INVALID_ARG, RTCI2C_TAG, "SCL low period cannot be less than 1.3 micro seconds"); + ESP_RETURN_ON_FALSE((float)cfg->i2c_timing_cfg.scl_high_period > 0.6, ESP_ERR_INVALID_ARG, RTCI2C_TAG, "SCL high period cannot be less than 0.6 micro seconds"); + ESP_RETURN_ON_FALSE((float)setup_time_start > 0.6, ESP_ERR_INVALID_ARG, RTCI2C_TAG, "Setup time cannot be less than 0.6 micro seconds"); + ESP_RETURN_ON_FALSE((float)hold_time_start > 0.6, ESP_ERR_INVALID_ARG, RTCI2C_TAG, "Data hold time cannot be less than 0.6 micro seconds"); + ESP_RETURN_ON_FALSE((float)cfg->i2c_timing_cfg.scl_stop_period > 0.6, ESP_ERR_INVALID_ARG, RTCI2C_TAG, "Setup time cannot be less than 0.6 micro seconds"); + ESP_RETURN_ON_FALSE((float)cfg->i2c_timing_cfg.sda_duty_period < 3.45, ESP_ERR_INVALID_ARG, RTCI2C_TAG, "Data hold time cannot be greater than 3.45 micro seconds"); + ESP_RETURN_ON_FALSE((float)(setup_time_data * 1000) > 250, ESP_ERR_INVALID_ARG, RTCI2C_TAG, "Data setup time cannot be less than 250 nano seconds"); + + /* Verify filtering constrains + * + * I2C may have glitches on the transition edge, so the edge will be filtered in the design, + * which will also affect the value of the timing parameter register. + * Therefore, the following filtering constraints must be followed: + */ + ESP_RETURN_ON_FALSE(scl_stop_period > scl_high_period, ESP_ERR_INVALID_ARG, RTCI2C_TAG, "SCL Stop period cannot be greater than SCL high period"); + ESP_RETURN_ON_FALSE(sda_duty_period < scl_low_period, ESP_ERR_INVALID_ARG, RTCI2C_TAG, "SDA duty period cannot be less than the SCL low period"); + ESP_RETURN_ON_FALSE(scl_start_period > 8, ESP_ERR_INVALID_ARG, RTCI2C_TAG, "SCL start period must be greater than 8 RTC_FAST_CLK cycles"); + ESP_RETURN_ON_FALSE((scl_low_period + scl_high_period - sda_duty_period) > 8, ESP_ERR_INVALID_ARG, RTCI2C_TAG, "SCL low + SCL high - SDA duty must be greater than 8 RTC_FAST_CLK cycles"); + + /* Verify SDA duty num constraints */ + ESP_RETURN_ON_FALSE(sda_duty_period > 14, ESP_ERR_INVALID_ARG, RTCI2C_TAG, "SDA duty period must be greater than 14 RTC_FAST_CLK cycles"); + + /* Set the RTC I2C timing parameters */ +#if CONFIG_IDF_TARGET_ESP32S2 + i2c_dev->scl_low.val = scl_low_period; // SCL low period + i2c_dev->scl_high.val = scl_high_period; // SCL high period + i2c_dev->sda_duty.val = sda_duty_period; // SDA duty cycle + i2c_dev->scl_start_period.val = scl_start_period; // Wait time after START condition + i2c_dev->scl_stop_period.val = scl_stop_period; // Wait time before END condition + i2c_dev->timeout.val = i2c_trans_timeout; // I2C transaction timeout +#elif CONFIG_IDF_TARGET_ESP32S3 + i2c_dev->i2c_scl_low.val = scl_low_period; // SCL low period + i2c_dev->i2c_scl_high.val = scl_high_period; // SCL high period + i2c_dev->i2c_sda_duty.val = sda_duty_period; // SDA duty cycle + i2c_dev->i2c_scl_start_period.val = scl_start_period; // Wait time after START condition + i2c_dev->i2c_scl_stop_period.val = scl_stop_period; // Wait time before END condition + i2c_dev->i2c_to.val = i2c_trans_timeout; // I2C transaction timeout +#endif // CONFIG_IDF_TARGET_ESP32S2 + + return ESP_OK; +} + +/* + * The RTC I2C controller follows the I2C command registers to perform read/write operations. + * The cmd registers have the following format: + * + * 31 30:14 13:11 10 9 8 7:0 + * |----------|----------|---------|---------|----------|------------|---------| + * | CMD_DONE | Reserved | OPCODE |ACK Value|ACK Expect|ACK Check En|Byte Num | + * |----------|----------|---------|---------|----------|------------|---------| + */ +static void ulp_riscv_i2c_format_cmd(uint32_t cmd_idx, uint8_t op_code, uint8_t ack_val, + uint8_t ack_expected, uint8_t ack_check_en, uint8_t byte_num) +{ +#if CONFIG_IDF_TARGET_ESP32S2 + /* Reset cmd register */ + i2c_dev->command[cmd_idx].val = 0; + + /* Write new command to cmd register */ + i2c_dev->command[cmd_idx].done = 0; // CMD Done + i2c_dev->command[cmd_idx].op_code = op_code; // Opcode + i2c_dev->command[cmd_idx].ack_val = ack_val; // ACK bit sent by I2C controller during READ. + // Ignored during RSTART, STOP, END and WRITE cmds. + i2c_dev->command[cmd_idx].ack_exp = ack_expected; // ACK bit expected by I2C controller during WRITE. + // Ignored during RSTART, STOP, END and READ cmds. + i2c_dev->command[cmd_idx].ack_en = ack_check_en; // I2C controller verifies that the ACK bit sent by the + // slave device matches the ACK expected bit during WRITE. + // Ignored during RSTART, STOP, END and READ cmds. + i2c_dev->command[cmd_idx].byte_num = byte_num; // Byte Num +#elif CONFIG_IDF_TARGET_ESP32S3 + /* Reset cmd register */ + i2c_dev->i2c_cmd[cmd_idx].val = 0; + + /* Write new command to cmd register */ + i2c_dev->i2c_cmd[cmd_idx].i2c_command_done = 0; // CMD Done + i2c_dev->i2c_cmd[cmd_idx].i2c_op_code = op_code; // Opcode + i2c_dev->i2c_cmd[cmd_idx].i2c_ack_val = ack_val; // ACK bit sent by I2C controller during READ. + // Ignored during RSTART, STOP, END and WRITE cmds. + i2c_dev->i2c_cmd[cmd_idx].i2c_ack_exp = ack_expected; // ACK bit expected by I2C controller during WRITE. + // Ignored during RSTART, STOP, END and READ cmds. + i2c_dev->i2c_cmd[cmd_idx].i2c_ack_en = ack_check_en; // I2C controller verifies that the ACK bit sent by the + // slave device matches the ACK expected bit during WRITE. + // Ignored during RSTART, STOP, END and READ cmds. + i2c_dev->i2c_cmd[cmd_idx].i2c_byte_num = byte_num; // Byte Num +#endif // CONFIG_IDF_TARGET_ESP32S2 +} + +void ulp_riscv_i2c_master_set_slave_addr(uint8_t slave_addr) +{ + CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, I2C_CTRL_SLAVE_ADDR_MASK); + SET_PERI_REG_BITS(SENS_SAR_I2C_CTRL_REG, 0xFF, slave_addr, 0); +} + +void ulp_riscv_i2c_master_set_slave_reg_addr(uint8_t slave_reg_addr) +{ + CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, I2C_CTRL_SLAVE_REG_ADDR_MASK); + SET_PERI_REG_BITS(SENS_SAR_I2C_CTRL_REG, 0xFF, slave_reg_addr, 11); +} + +/* + * I2C transactions when master reads one byte of data from the slave device: + * + * |--------|--------|---------|--------|--------|--------|--------|---------|--------|--------|--------|--------| + * | Master | START | SAD + W | | SUB | | SR | SAD + R | | | NACK | STOP | + * |--------|--------|---------|--------|--------|--------|--------|---------|--------|--------|--------|--------| + * | Slave | | | ACK | | ACK | | | ACK | DATA | | | + * |--------|--------|---------|--------|--------|--------|--------|---------|--------|--------|--------|--------| + * + * I2C transactions when master reads multiple bytes of data from the slave device: + * + * |--------|--------|---------|--------|--------|--------|--------|---------|--------|--------|--------|--------|--------|--------| + * | Master | START | SAD + W | | SUB | | SR | SAD + R | | | ACK | | NACK | STOP | + * |--------|--------|---------|--------|--------|--------|--------|---------|--------|--------|--------|--------|--------|--------| + * | Slave | | | ACK | | ACK | | | ACK | DATA | | DATA | | | + * |--------|--------|---------|--------|--------|--------|--------|---------|--------|--------|--------|--------|--------|--------| + */ +void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size) +{ + uint32_t i = 0; + uint32_t cmd_idx = 0; + + if (size == 0) { + // Quietly return + return; + } + + /* By default, RTC I2C controller is hard wired to use CMD2 register onwards for read operations */ + cmd_idx = 2; + + /* Write slave addr */ + ulp_riscv_i2c_format_cmd(cmd_idx++, ULP_I2C_CMD_WRITE, 0, 0, 1, 2); + + /* Repeated START */ + ulp_riscv_i2c_format_cmd(cmd_idx++, ULP_I2C_CMD_RESTART, 0, 0, 0, 0); + + /* Write slave register addr */ + ulp_riscv_i2c_format_cmd(cmd_idx++, ULP_I2C_CMD_WRITE, 0, 0, 1, 1); + + if (size > 1) { + /* Read n - 1 bytes */ + ulp_riscv_i2c_format_cmd(cmd_idx++, ULP_I2C_CMD_READ, 0, 0, 1, size - 1); + } + + /* Read last byte + NACK */ + ulp_riscv_i2c_format_cmd(cmd_idx++, ULP_I2C_CMD_READ, 1, 1, 1, 1); + + /* STOP */ + ulp_riscv_i2c_format_cmd(cmd_idx++, ULP_I2C_CMD_STOP, 0, 0, 0, 0); + + /* Configure the RTC I2C controller in read mode */ + SET_PERI_REG_BITS(SENS_SAR_I2C_CTRL_REG, 0x1, 0, 27); + + /* Enable Rx data interrupt */ + SET_PERI_REG_MASK(RTC_I2C_INT_ENA_REG, RTC_I2C_RX_DATA_INT_ENA); + + /* Start RTC I2C transmission */ + SET_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START_FORCE); + SET_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START); + + for (i = 0; i < size; i++) { + /* Poll for RTC I2C Rx Data interrupt bit to be set */ + while (!REG_GET_FIELD(RTC_I2C_INT_ST_REG, RTC_I2C_RX_DATA_INT_ST)) { + /* Minimal delay to avoid hogging the CPU */ + vTaskDelay(1); + } + + /* Read the data + * + * Unfortunately, the RTC I2C has no fifo buffer to help us with reading and storing + * multiple bytes of data. Therefore, we need to read one byte at a time and clear the + * Rx interrupt to get ready for the next byte. + */ +#if CONFIG_IDF_TARGET_ESP32S2 + data_rd[i] = REG_GET_FIELD(RTC_I2C_DATA_REG, RTC_I2C_RDATA); +#elif CONFIG_IDF_TARGET_ESP32S3 + data_rd[i] = REG_GET_FIELD(RTC_I2C_DATA_REG, RTC_I2C_I2C_RDATA); +#endif // CONFIG_IDF_TARGET_ESP32S2 + + /* Clear the Rx data interrupt bit */ + SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, RTC_I2C_RX_DATA_INT_CLR); + } + + /* Clear the RTC I2C transmission bits */ + CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START_FORCE); + CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START); +} + +/* + * I2C transactions when master writes one byte of data to the slave device: + * + * |--------|--------|---------|--------|--------|--------|--------|--------|--------| + * | Master | START | SAD + W | | SUB | | DATA | | STOP | + * |--------|--------|---------|--------|--------|--------|--------|--------|--------| + * | Slave | | | ACK | | ACK | | ACK | | + * |--------|--------|---------|--------|--------|--------|--------|--------|--------| + * + * I2C transactions when master writes multiple bytes of data to the slave device: + * + * |--------|--------|---------|--------|--------|--------|--------|--------|--------|--------|--------| + * | Master | START | SAD + W | | SUB | | DATA | | DATA | | STOP | + * |--------|--------|---------|--------|--------|--------|--------|--------|--------|--------|--------| + * | Slave | | | ACK | | ACK | | ACK | | ACK | | + * |--------|--------|---------|--------|--------|--------|--------|--------|--------|--------|--------| + */ +void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size) +{ + uint32_t i = 0; + uint32_t cmd_idx = 0; + + if (size == 0) { + // Quietly return + return; + } + + /* By default, RTC I2C controller is hard wired to use CMD0 and CMD1 registers for write operations */ + cmd_idx = 0; + + /* Write slave addr + reg addr + data */ + ulp_riscv_i2c_format_cmd(cmd_idx++, ULP_I2C_CMD_WRITE, 0, 0, 1, 2 + size); + + /* Stop */ + ulp_riscv_i2c_format_cmd(cmd_idx++, ULP_I2C_CMD_STOP, 0, 0, 0, 0); + + /* Configure the RTC I2C controller in write mode */ + SET_PERI_REG_BITS(SENS_SAR_I2C_CTRL_REG, 0x1, 1, 27); + + /* Enable Tx data interrupt */ + SET_PERI_REG_MASK(RTC_I2C_INT_ENA_REG, RTC_I2C_TX_DATA_INT_ENA); + + for (i = 0; i < size; i++) { + /* Write the data to be transmitted */ + CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, I2C_CTRL_MASTER_TX_DATA_MASK); + SET_PERI_REG_BITS(SENS_SAR_I2C_CTRL_REG, 0xFF, data_wr[i], 19); + + if (i == 0) { + /* Start RTC I2C transmission. (Needn't do it for every byte) */ + SET_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START_FORCE); + SET_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START); + } + + /* Poll for RTC I2C Tx Data interrupt bit to be set */ + while (!REG_GET_FIELD(RTC_I2C_INT_ST_REG, RTC_I2C_TX_DATA_INT_ST)) { + /* Minimal delay to avoid hogging the CPU */ + vTaskDelay(1); + } + + /* Clear the Tx data interrupt bit */ + SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, RTC_I2C_TX_DATA_INT_CLR); + } + + /* Clear the RTC I2C transmission bits */ + CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START_FORCE); + CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START); +} + +esp_err_t ulp_riscv_i2c_master_init(const ulp_riscv_i2c_cfg_t *cfg) +{ + /* Reset RTC I2C */ +#if CONFIG_IDF_TARGET_ESP32S2 + i2c_dev->ctrl.i2c_reset = 1; + esp_rom_delay_us(20); + i2c_dev->ctrl.i2c_reset = 0; +#elif CONFIG_IDF_TARGET_ESP32S3 + SET_PERI_REG_MASK(SENS_SAR_PERI_RESET_CONF_REG, SENS_RTC_I2C_RESET); + i2c_dev->i2c_ctrl.i2c_i2c_reset = 1; + esp_rom_delay_us(20); + i2c_dev->i2c_ctrl.i2c_i2c_reset = 0; + CLEAR_PERI_REG_MASK(SENS_SAR_PERI_RESET_CONF_REG, SENS_RTC_I2C_RESET); +#endif // CONFIG_IDF_TARGET_ESP32S2 + + /* Verify that the input cfg param is valid */ + ESP_RETURN_ON_FALSE(cfg, ESP_ERR_INVALID_ARG, RTCI2C_TAG, "RTC I2C configuration is NULL"); + + /* Configure RTC I2C GPIOs */ + ESP_RETURN_ON_ERROR(i2c_set_pin(cfg), RTCI2C_TAG, "Failed to configure RTC I2C GPIOs"); + +#if CONFIG_IDF_TARGET_ESP32S2 + /* Configure the RTC I2C controller in master mode */ + i2c_dev->ctrl.ms_mode = 1; + + /* Enable RTC I2C Clock gate */ + i2c_dev->ctrl.i2c_ctrl_clk_gate_en = 1; +#elif CONFIG_IDF_TARGET_ESP32S3 + /* For esp32s3, we need to enable the rtc_i2c clock gate before accessing rtc i2c registers */ + SET_PERI_REG_MASK(SENS_SAR_PERI_CLK_GATE_CONF_REG, SENS_RTC_I2C_CLK_EN); + + /* Configure the RTC I2C controller in master mode */ + i2c_dev->i2c_ctrl.i2c_ms_mode = 1; + + /* Enable RTC I2C Clock gate */ + i2c_dev->i2c_ctrl.i2c_i2c_ctrl_clk_gate_en = 1; +#endif // CONFIG_IDF_TARGET_ESP32S2 + + /* Configure RTC I2C timing paramters */ + ESP_RETURN_ON_ERROR(i2c_set_timing(cfg), RTCI2C_TAG, "Failed to configure RTC I2C timing"); + + return ESP_OK; +} diff --git a/components/ulp/ulp_riscv/ulp_riscv_lock.c b/components/ulp/ulp_riscv/ulp_riscv_lock.c new file mode 100644 index 0000000000..cab59a8d0e --- /dev/null +++ b/components/ulp/ulp_riscv/ulp_riscv_lock.c @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "ulp_riscv_lock.h" +#include "ulp_riscv_lock_shared.h" + +#include + +void ulp_riscv_lock_acquire(ulp_riscv_lock_t *lock) +{ + assert(lock); + + lock->critical_section_flag_main_cpu = true; + lock->turn = ULP_RISCV_LOCK_TURN_ULP; + + while (lock->critical_section_flag_ulp && (lock->turn == ULP_RISCV_LOCK_TURN_ULP)) { + } +} + +void ulp_riscv_lock_release(ulp_riscv_lock_t *lock) +{ + assert(lock); + + lock->critical_section_flag_main_cpu = false; +} diff --git a/components/unity/CMakeLists.txt b/components/unity/CMakeLists.txt index bc8818b32e..ff521fa1d4 100644 --- a/components/unity/CMakeLists.txt +++ b/components/unity/CMakeLists.txt @@ -17,7 +17,7 @@ if(CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER) list(APPEND srcs "unity_runner.c") # Note the following files are not compatible with the Linux target. # On Linux, these are masked because we also don't use the IDF test runner there - list(APPEND srcs "unity_utils_freertos.c") + list(APPEND srcs "unity_utils_freertos.c" "unity_utils_cache.c") list(APPEND requires "freertos") endif() @@ -32,6 +32,7 @@ if(NOT "${target}" STREQUAL "linux") list(APPEND srcs "unity_port_esp32.c") list(APPEND srcs "port/esp/unity_utils_memory_esp.c") else() + list(APPEND srcs "unity_port_linux.c") list(APPEND srcs "port/linux/unity_utils_memory_linux.c") endif() @@ -39,10 +40,12 @@ idf_component_register(SRCS "${srcs}" INCLUDE_DIRS ${includes} REQUIRES ${requires}) -if(NOT "${target}" STREQUAL "linux") - target_compile_definitions(${COMPONENT_LIB} PUBLIC - -DUNITY_INCLUDE_CONFIG_H - ) +if(CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER) + idf_component_optional_requires(PRIVATE spi_flash) endif() +target_compile_definitions(${COMPONENT_LIB} PUBLIC + -DUNITY_INCLUDE_CONFIG_H +) + target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-unused-const-variable) diff --git a/components/unity/include/unity_test_utils.h b/components/unity/include/unity_test_utils.h index c9f38613e7..42afe6bb48 100644 --- a/components/unity/include/unity_test_utils.h +++ b/components/unity/include/unity_test_utils.h @@ -10,6 +10,7 @@ #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "unity_test_utils_memory.h" +#include "unity_test_utils_cache.h" #ifdef __cplusplus extern "C" { diff --git a/components/unity/include/unity_test_utils_cache.h b/components/unity/include/unity_test_utils_cache.h new file mode 100644 index 0000000000..6c33b6dead --- /dev/null +++ b/components/unity/include/unity_test_utils_cache.h @@ -0,0 +1,25 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Disable flash cache and run user stub function and then enable flash cache again + * + * @note You should make sure the passed-in function is in internal RAM. + * + * @param post_cache_disable User function to be invoked after cache is disabled. + * @param user_ctx User context to be passed to user function. + */ +void unity_utils_run_cache_disable_stub(void (*post_cache_disable)(void *), void *user_ctx); + +#ifdef __cplusplus +} +#endif diff --git a/components/unity/unity_port_linux.c b/components/unity/unity_port_linux.c new file mode 100644 index 0000000000..a295879c33 --- /dev/null +++ b/components/unity/unity_port_linux.c @@ -0,0 +1,42 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include +#include +#include "unity.h" +#include "sdkconfig.h" + + +static struct timeval s_test_start, s_test_stop; + +void unity_putc(int c) +{ + putc(c, stdout); +} + +void unity_flush(void) +{ + fflush(stdout); + fsync(fileno(stdout)); +} + +void unity_exec_time_start(void) +{ + gettimeofday(&s_test_start, NULL); +} + +void unity_exec_time_stop(void) +{ + gettimeofday(&s_test_stop, NULL); +} + +uint32_t unity_exec_time_get_ms(void) +{ + return (uint32_t) (((s_test_stop.tv_sec * 1000000ULL + s_test_stop.tv_usec) - + (s_test_start.tv_sec * 1000000ULL + s_test_start.tv_usec)) / 1000); +} diff --git a/components/unity/unity_utils_cache.c b/components/unity/unity_utils_cache.c new file mode 100644 index 0000000000..5d44ec0a0e --- /dev/null +++ b/components/unity/unity_utils_cache.c @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "unity.h" +#include "unity_test_utils_cache.h" +#include "esp_attr.h" +#include "esp_memory_utils.h" +#include "esp_private/spi_flash_os.h" + +IRAM_ATTR void unity_utils_run_cache_disable_stub(void (*post_cache_disable)(void *), void *user_ctx) +{ + // callback function must reside in IRAM + TEST_ASSERT_TRUE(esp_ptr_in_iram(post_cache_disable)); + // disable flash cache + spi_flash_guard_get()->start(); + post_cache_disable(user_ctx); + // enable flash cache + spi_flash_guard_get()->end(); +} diff --git a/components/usb/CMakeLists.txt b/components/usb/CMakeLists.txt index d458fb0130..5ff63af4d7 100644 --- a/components/usb/CMakeLists.txt +++ b/components/usb/CMakeLists.txt @@ -7,7 +7,7 @@ set(priv_include) set(priv_require driver) # usb_phy driver relies on gpio driver API if(CONFIG_USB_OTG_SUPPORTED) - list(APPEND srcs "hcd.c" + list(APPEND srcs "hcd_dwc.c" "hub.c" "usb_helpers.c" "usb_host.c" @@ -23,7 +23,3 @@ idf_component_register(SRCS ${srcs} PRIV_INCLUDE_DIRS ${priv_include} PRIV_REQUIRES ${priv_require} ) - -if(CONFIG_USB_OTG_SUPPORTED) - target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") -endif() diff --git a/components/usb/hcd.c b/components/usb/hcd_dwc.c similarity index 90% rename from components/usb/hcd.c rename to components/usb/hcd_dwc.c index 2ef9b220a8..4af0e84fcd 100644 --- a/components/usb/hcd.c +++ b/components/usb/hcd_dwc.c @@ -14,7 +14,7 @@ #include "esp_intr_alloc.h" #include "esp_err.h" #include "esp_rom_gpio.h" -#include "hal/usbh_hal.h" +#include "hal/usb_dwc_hal.h" #include "hal/usb_types_private.h" #include "soc/gpio_pins.h" #include "soc/gpio_sig_map.h" @@ -52,7 +52,7 @@ typedef struct { * * RXFIFO * - Recommended: ((LPS/4) * 2) + 2 - * - Actual: Whatever leftover size: USBH_HAL_FIFO_TOTAL_USABLE_LINES(200) - 48 - 48 = 104 + * - Actual: Whatever leftover size: USB_DWC_HAL_FIFO_TOTAL_USABLE_LINES(200) - 48 - 48 = 104 * - Worst case can accommodate two packets of 204 bytes, or one packet of 408 * NPTXFIFO * - Recommended: (LPS/4) * 2 @@ -63,7 +63,7 @@ typedef struct { * - Actual: Assume LPS is 64, and 3 packets: (64/4) * 3 = 48 * - Worst case can accommodate three packets of 64 bytes or one packet of 192 */ -const usbh_hal_fifo_config_t fifo_config_default = { +const usb_dwc_hal_fifo_config_t fifo_config_default = { .rx_fifo_lines = 104, .nptx_fifo_lines = 48, .ptx_fifo_lines = 48, @@ -80,7 +80,7 @@ const fifo_mps_limits_t mps_limits_default = { * * RXFIFO * - Recommended: ((LPS/4) * 2) + 2 - * - Actual: Whatever leftover size: USBH_HAL_FIFO_TOTAL_USABLE_LINES(200) - 32 - 16 = 152 + * - Actual: Whatever leftover size: USB_DWC_HAL_FIFO_TOTAL_USABLE_LINES(200) - 32 - 16 = 152 * - Worst case can accommodate two packets of 300 bytes or one packet of 600 bytes * NPTXFIFO * - Recommended: (LPS/4) * 2 @@ -91,7 +91,7 @@ const fifo_mps_limits_t mps_limits_default = { * - Actual: Assume LPS is 64, and 3 packets: (64/4) * 2 = 32 * - Worst case can accommodate two packets of 64 bytes or one packet of 128 */ -const usbh_hal_fifo_config_t fifo_config_bias_rx = { +const usb_dwc_hal_fifo_config_t fifo_config_bias_rx = { .rx_fifo_lines = 152, .nptx_fifo_lines = 16, .ptx_fifo_lines = 32, @@ -116,10 +116,10 @@ const fifo_mps_limits_t mps_limits_bias_rx = { * - Worst case can accommodate one packet of 64 bytes * PTXFIFO * - Recommended: (LPS/4) * 2 - * - Actual: Whatever leftover size: USBH_HAL_FIFO_TOTAL_USABLE_LINES(200) - 34 - 16 = 150 + * - Actual: Whatever leftover size: USB_DWC_HAL_FIFO_TOTAL_USABLE_LINES(200) - 34 - 16 = 150 * - Worst case can accommodate two packets of 300 bytes or one packet of 600 bytes */ -const usbh_hal_fifo_config_t fifo_config_bias_ptx = { +const usb_dwc_hal_fifo_config_t fifo_config_bias_ptx = { .rx_fifo_lines = 34, .nptx_fifo_lines = 16, .ptx_fifo_lines = 150, @@ -248,8 +248,8 @@ struct pipe_obj { uint32_t val; } multi_buffer_control; //HAL related - usbh_hal_chan_t *chan_obj; - usbh_hal_ep_char_t ep_char; + usb_dwc_hal_chan_t *chan_obj; + usb_dwc_hal_ep_char_t ep_char; //Port related port_t *port; //The port to which this pipe is routed through TAILQ_ENTRY(pipe_obj) tailq_entry; //TailQ entry for port's list of pipes @@ -278,7 +278,7 @@ struct pipe_obj { * @brief Object representing a port in the HCD layer */ struct port_obj { - usbh_hal_context_t *hal; + usb_dwc_hal_context_t *hal; void *frame_list; //Pipes routed through this port TAILQ_HEAD(tailhead_pipes_idle, pipe_obj) pipes_idle_tailq; @@ -304,7 +304,7 @@ struct port_obj { } flags; bool initialized; //FIFO biasing related - const usbh_hal_fifo_config_t *fifo_config; + const usb_dwc_hal_fifo_config_t *fifo_config; const fifo_mps_limits_t *fifo_mps_limits; //Port callback and context hcd_port_callback_t callback; @@ -389,7 +389,7 @@ static void _buffer_exec(pipe_t *pipe); /** * @brief Check if a buffer as completed execution * - * This should only be called after receiving a USBH_HAL_CHAN_EVENT_CPLT event to check if a buffer is actually + * This should only be called after receiving a USB_DWC_HAL_CHAN_EVENT_CPLT event to check if a buffer is actually * done. * * @param pipe Pipe object @@ -489,7 +489,7 @@ static bool _buffer_flush_all(pipe_t *pipe, bool canceled); * @param chan_error The HAL channel error * @return hcd_pipe_event_t The corresponding pipe error event */ -static inline hcd_pipe_event_t pipe_decode_error_event(usbh_hal_chan_error_t chan_error); +static inline hcd_pipe_event_t pipe_decode_error_event(usb_dwc_hal_chan_error_t chan_error); /** * @brief Halt a pipe @@ -764,30 +764,30 @@ static bool _internal_pipe_event_notify(pipe_t *pipe, bool from_isr) * @param[out] yield Set to true if a yield is required as a result of handling the interrupt * @return hcd_port_event_t Returns a port event, or HCD_PORT_EVENT_NONE if no port event occurred */ -static hcd_port_event_t _intr_hdlr_hprt(port_t *port, usbh_hal_port_event_t hal_port_event, bool *yield) +static hcd_port_event_t _intr_hdlr_hprt(port_t *port, usb_dwc_hal_port_event_t hal_port_event, bool *yield) { hcd_port_event_t port_event = HCD_PORT_EVENT_NONE; switch (hal_port_event) { - case USBH_HAL_PORT_EVENT_CONN: { + case USB_DWC_HAL_PORT_EVENT_CONN: { //Don't update state immediately, we still need to debounce. port_event = HCD_PORT_EVENT_CONNECTION; break; } - case USBH_HAL_PORT_EVENT_DISCONN: { + case USB_DWC_HAL_PORT_EVENT_DISCONN: { port->state = HCD_PORT_STATE_RECOVERY; port_event = HCD_PORT_EVENT_DISCONNECTION; port->flags.conn_dev_ena = 0; break; } - case USBH_HAL_PORT_EVENT_ENABLED: { - usbh_hal_port_enable(port->hal); //Initialize remaining host port registers - port->speed = (usbh_hal_port_get_conn_speed(port->hal) == USB_PRIV_SPEED_FULL) ? USB_SPEED_FULL : USB_SPEED_LOW; + case USB_DWC_HAL_PORT_EVENT_ENABLED: { + usb_dwc_hal_port_enable(port->hal); //Initialize remaining host port registers + port->speed = (usb_dwc_hal_port_get_conn_speed(port->hal) == USB_PRIV_SPEED_FULL) ? USB_SPEED_FULL : USB_SPEED_LOW; port->state = HCD_PORT_STATE_ENABLED; port->flags.conn_dev_ena = 1; //This was triggered by a command, so no event needs to be propagated. break; } - case USBH_HAL_PORT_EVENT_DISABLED: { + case USB_DWC_HAL_PORT_EVENT_DISABLED: { port->flags.conn_dev_ena = 0; //Disabled could be due to a disable request or reset request, or due to a port error if (port->state != HCD_PORT_STATE_RESETTING) { //Ignore the disable event if it's due to a reset request @@ -804,11 +804,11 @@ static hcd_port_event_t _intr_hdlr_hprt(port_t *port, usbh_hal_port_event_t hal_ } break; } - case USBH_HAL_PORT_EVENT_OVRCUR: - case USBH_HAL_PORT_EVENT_OVRCUR_CLR: { //Could occur if a quick overcurrent then clear happens + case USB_DWC_HAL_PORT_EVENT_OVRCUR: + case USB_DWC_HAL_PORT_EVENT_OVRCUR_CLR: { //Could occur if a quick overcurrent then clear happens if (port->state != HCD_PORT_STATE_NOT_POWERED) { //We need to power OFF the port to protect it - usbh_hal_port_toggle_power(port->hal, false); + usb_dwc_hal_port_toggle_power(port->hal, false); port->state = HCD_PORT_STATE_RECOVERY; port_event = HCD_PORT_EVENT_OVERCURRENT; } @@ -834,13 +834,13 @@ static hcd_port_event_t _intr_hdlr_hprt(port_t *port, usbh_hal_port_event_t hal_ * @param[out] yield Set to true if a yield is required as a result of handling the interrupt * @return hcd_pipe_event_t The pipe event */ -static hcd_pipe_event_t _intr_hdlr_chan(pipe_t *pipe, usbh_hal_chan_t *chan_obj, bool *yield) +static hcd_pipe_event_t _intr_hdlr_chan(pipe_t *pipe, usb_dwc_hal_chan_t *chan_obj, bool *yield) { - usbh_hal_chan_event_t chan_event = usbh_hal_chan_decode_intr(chan_obj); + usb_dwc_hal_chan_event_t chan_event = usb_dwc_hal_chan_decode_intr(chan_obj); hcd_pipe_event_t event = HCD_PIPE_EVENT_NONE; switch (chan_event) { - case USBH_HAL_CHAN_EVENT_CPLT: { + case USB_DWC_HAL_CHAN_EVENT_CPLT: { if (!_buffer_check_done(pipe)) { _buffer_exec_cont(pipe); break; @@ -848,7 +848,7 @@ static hcd_pipe_event_t _intr_hdlr_chan(pipe_t *pipe, usbh_hal_chan_t *chan_obj, pipe->last_event = HCD_PIPE_EVENT_URB_DONE; event = pipe->last_event; //Mark the buffer as done - int stop_idx = usbh_hal_chan_get_qtd_idx(chan_obj); + int stop_idx = usb_dwc_hal_chan_get_qtd_idx(chan_obj); _buffer_done(pipe, stop_idx, pipe->last_event, false); //First check if there is another buffer we can execute. But we only want to execute if there's still a valid device if (_buffer_can_exec(pipe) && pipe->port->flags.conn_dev_ena) { @@ -864,27 +864,27 @@ static hcd_pipe_event_t _intr_hdlr_chan(pipe_t *pipe, usbh_hal_chan_t *chan_obj, } break; } - case USBH_HAL_CHAN_EVENT_ERROR: { + case USB_DWC_HAL_CHAN_EVENT_ERROR: { //Get and store the pipe error event - usbh_hal_chan_error_t chan_error = usbh_hal_chan_get_error(chan_obj); + usb_dwc_hal_chan_error_t chan_error = usb_dwc_hal_chan_get_error(chan_obj); pipe->last_event = pipe_decode_error_event(chan_error); event = pipe->last_event; pipe->state = HCD_PIPE_STATE_HALTED; //Mark the buffer as done with an error - int stop_idx = usbh_hal_chan_get_qtd_idx(chan_obj); + int stop_idx = usb_dwc_hal_chan_get_qtd_idx(chan_obj); _buffer_done(pipe, stop_idx, pipe->last_event, false); //Parse the buffer _buffer_parse(pipe); break; } - case USBH_HAL_CHAN_EVENT_HALT_REQ: { + case USB_DWC_HAL_CHAN_EVENT_HALT_REQ: { assert(pipe->cs_flags.waiting_halt); //We've halted a transfer, so we need to trigger the pipe callback pipe->last_event = HCD_PIPE_EVENT_URB_DONE; event = pipe->last_event; //Halt request event is triggered when packet is successful completed. But just treat all halted transfers as errors pipe->state = HCD_PIPE_STATE_HALTED; - int stop_idx = usbh_hal_chan_get_qtd_idx(chan_obj); + int stop_idx = usb_dwc_hal_chan_get_qtd_idx(chan_obj); _buffer_done(pipe, stop_idx, HCD_PIPE_EVENT_NONE, true); //Parse the buffer _buffer_parse(pipe); @@ -892,7 +892,7 @@ static hcd_pipe_event_t _intr_hdlr_chan(pipe_t *pipe, usbh_hal_chan_t *chan_obj, *yield |= _internal_pipe_event_notify(pipe, true); break; } - case USBH_HAL_CHAN_EVENT_NONE: { + case USB_DWC_HAL_CHAN_EVENT_NONE: { break; //Nothing to do } default: @@ -919,12 +919,12 @@ static void intr_hdlr_main(void *arg) bool yield = false; HCD_ENTER_CRITICAL_ISR(); - usbh_hal_port_event_t hal_port_evt = usbh_hal_decode_intr(port->hal); - if (hal_port_evt == USBH_HAL_PORT_EVENT_CHAN) { + usb_dwc_hal_port_event_t hal_port_evt = usb_dwc_hal_decode_intr(port->hal); + if (hal_port_evt == USB_DWC_HAL_PORT_EVENT_CHAN) { //Channel event. Cycle through each pending channel - usbh_hal_chan_t *chan_obj = usbh_hal_get_chan_pending_intr(port->hal); + usb_dwc_hal_chan_t *chan_obj = usb_dwc_hal_get_chan_pending_intr(port->hal); while (chan_obj != NULL) { - pipe_t *pipe = (pipe_t *)usbh_hal_chan_get_context(chan_obj); + pipe_t *pipe = (pipe_t *)usb_dwc_hal_chan_get_context(chan_obj); hcd_pipe_event_t event = _intr_hdlr_chan(pipe, chan_obj, &yield); //Run callback if a pipe event has occurred and the pipe also has a callback if (event != HCD_PIPE_EVENT_NONE && pipe->callback != NULL) { @@ -933,9 +933,9 @@ static void intr_hdlr_main(void *arg) HCD_ENTER_CRITICAL_ISR(); } //Check for more channels with pending interrupts. Returns NULL if there are no more - chan_obj = usbh_hal_get_chan_pending_intr(port->hal); + chan_obj = usb_dwc_hal_get_chan_pending_intr(port->hal); } - } else if (hal_port_evt != USBH_HAL_PORT_EVENT_NONE) { //Port event + } else if (hal_port_evt != USB_DWC_HAL_PORT_EVENT_NONE) { //Port event hcd_port_event_t port_event = _intr_hdlr_hprt(port, hal_port_evt, &yield); if (port_event != HCD_PORT_EVENT_NONE) { port->last_event = port_event; @@ -959,8 +959,8 @@ static void intr_hdlr_main(void *arg) static port_t *port_obj_alloc(void) { port_t *port = calloc(1, sizeof(port_t)); - usbh_hal_context_t *hal = malloc(sizeof(usbh_hal_context_t)); - void *frame_list = heap_caps_aligned_calloc(USBH_HAL_FRAME_LIST_MEM_ALIGN, FRAME_LIST_LEN,sizeof(uint32_t), MALLOC_CAP_DMA); + usb_dwc_hal_context_t *hal = malloc(sizeof(usb_dwc_hal_context_t)); + void *frame_list = heap_caps_aligned_calloc(USB_DWC_HAL_FRAME_LIST_MEM_ALIGN, FRAME_LIST_LEN,sizeof(uint32_t), MALLOC_CAP_DMA); SemaphoreHandle_t port_mux = xSemaphoreCreateMutex(); if (port == NULL || hal == NULL || frame_list == NULL || port_mux == NULL) { free(port); @@ -1081,7 +1081,7 @@ static bool _port_persist_all_pipes(port_t *port) } TAILQ_FOREACH(pipe, &port->pipes_idle_tailq, tailq_entry) { pipe->cs_flags.reset_lock = 1; - usbh_hal_chan_free(port->hal, pipe->chan_obj); + usb_dwc_hal_chan_free(port->hal, pipe->chan_obj); } return true; } @@ -1092,8 +1092,8 @@ static void _port_recover_all_pipes(port_t *port) TAILQ_FOREACH(pipe, &port->pipes_idle_tailq, tailq_entry) { pipe->cs_flags.persist = 0; pipe->cs_flags.reset_lock = 0; - usbh_hal_chan_alloc(port->hal, pipe->chan_obj, (void *)pipe); - usbh_hal_chan_set_ep_char(port->hal, pipe->chan_obj, &pipe->ep_char); + usb_dwc_hal_chan_alloc(port->hal, pipe->chan_obj, (void *)pipe); + usb_dwc_hal_chan_set_ep_char(port->hal, pipe->chan_obj, &pipe->ep_char); } } @@ -1126,14 +1126,14 @@ static bool _port_debounce(port_t *port) vTaskDelay(pdMS_TO_TICKS(DEBOUNCE_DELAY_MS)); HCD_ENTER_CRITICAL(); //Check the post-debounce state of the bus (i.e., whether it's actually connected/disconnected) - bool is_connected = usbh_hal_port_check_if_connected(port->hal); + bool is_connected = usb_dwc_hal_port_check_if_connected(port->hal); if (is_connected) { port->state = HCD_PORT_STATE_DISABLED; } else { port->state = HCD_PORT_STATE_DISCONNECTED; } //Disable debounce lock - usbh_hal_disable_debounce_lock(port->hal); + usb_dwc_hal_disable_debounce_lock(port->hal); return is_connected; } @@ -1145,8 +1145,8 @@ static esp_err_t _port_cmd_power_on(port_t *port) //Port can only be powered on if it's currently unpowered if (port->state == HCD_PORT_STATE_NOT_POWERED) { port->state = HCD_PORT_STATE_DISCONNECTED; - usbh_hal_port_init(port->hal); - usbh_hal_port_toggle_power(port->hal, true); + usb_dwc_hal_port_init(port->hal); + usb_dwc_hal_port_toggle_power(port->hal, true); ret = ESP_OK; } else { ret = ESP_ERR_INVALID_STATE; @@ -1160,8 +1160,8 @@ static esp_err_t _port_cmd_power_off(port_t *port) //Port can only be unpowered if already powered if (port->state != HCD_PORT_STATE_NOT_POWERED) { port->state = HCD_PORT_STATE_NOT_POWERED; - usbh_hal_port_deinit(port->hal); - usbh_hal_port_toggle_power(port->hal, false); + usb_dwc_hal_port_deinit(port->hal); + usb_dwc_hal_port_toggle_power(port->hal, false); //If a device is currently connected, this should trigger a disconnect event ret = ESP_OK; } else { @@ -1187,7 +1187,7 @@ static esp_err_t _port_cmd_reset(port_t *port) //All pipes (if any_) are guaranteed to be persistent at this point. Proceed to resetting the bus port->state = HCD_PORT_STATE_RESETTING; //Put and hold the bus in the reset state. If the port was previously enabled, a disabled event will occur after this - usbh_hal_port_toggle_reset(port->hal, true); + usb_dwc_hal_port_toggle_reset(port->hal, true); HCD_EXIT_CRITICAL(); vTaskDelay(pdMS_TO_TICKS(RESET_HOLD_MS)); HCD_ENTER_CRITICAL(); @@ -1197,7 +1197,7 @@ static esp_err_t _port_cmd_reset(port_t *port) goto bailout; } //Return the bus to the idle state and hold it for the required reset recovery time. Port enabled event should occur - usbh_hal_port_toggle_reset(port->hal, false); + usb_dwc_hal_port_toggle_reset(port->hal, false); HCD_EXIT_CRITICAL(); vTaskDelay(pdMS_TO_TICKS(RESET_RECOVERY_MS)); HCD_ENTER_CRITICAL(); @@ -1207,10 +1207,10 @@ static esp_err_t _port_cmd_reset(port_t *port) goto bailout; } //Set FIFO sizes based on the selected biasing - usbh_hal_set_fifo_size(port->hal, port->fifo_config); + usb_dwc_hal_set_fifo_size(port->hal, port->fifo_config); //We start periodic scheduling only after a RESET command since SOFs only start after a reset - usbh_hal_port_set_frame_list(port->hal, port->frame_list, FRAME_LIST_LEN); - usbh_hal_port_periodic_enable(port->hal); + usb_dwc_hal_port_set_frame_list(port->hal, port->frame_list, FRAME_LIST_LEN); + usb_dwc_hal_port_periodic_enable(port->hal); ret = ESP_OK; bailout: if (is_runtime_reset) { @@ -1229,7 +1229,7 @@ static esp_err_t _port_cmd_bus_suspend(port_t *port) goto exit; } //All pipes are guaranteed halted at this point. Proceed to suspend the port - usbh_hal_port_suspend(port->hal); + usb_dwc_hal_port_suspend(port->hal); port->state = HCD_PORT_STATE_SUSPENDED; ret = ESP_OK; exit: @@ -1245,13 +1245,13 @@ static esp_err_t _port_cmd_bus_resume(port_t *port) goto exit; } //Put and hold the bus in the K state. - usbh_hal_port_toggle_resume(port->hal, true); + usb_dwc_hal_port_toggle_resume(port->hal, true); port->state = HCD_PORT_STATE_RESUMING; HCD_EXIT_CRITICAL(); vTaskDelay(pdMS_TO_TICKS(RESUME_HOLD_MS)); HCD_ENTER_CRITICAL(); //Return and hold the bus to the J state (as port of the LS EOP) - usbh_hal_port_toggle_resume(port->hal, false); + usb_dwc_hal_port_toggle_resume(port->hal, false); if (port->state != HCD_PORT_STATE_RESUMING || !port->flags.conn_dev_ena) { //Port state unexpectedly changed ret = ESP_ERR_INVALID_RESPONSE; @@ -1285,7 +1285,7 @@ static esp_err_t _port_cmd_disable(port_t *port) } //All pipes are guaranteed to be halted or freed at this point. Proceed to disable the port port->flags.disable_requested = 1; - usbh_hal_port_disable(port->hal); + usb_dwc_hal_port_disable(port->hal); _internal_port_event_wait(port); if (port->state != HCD_PORT_STATE_DISABLED) { //Port state unexpectedly changed @@ -1305,7 +1305,7 @@ esp_err_t hcd_port_init(int port_number, const hcd_port_config_t *port_config, h HCD_CHECK(port_number <= NUM_PORTS, ESP_ERR_NOT_FOUND); //Get a pointer to the correct FIFO bias constant values - const usbh_hal_fifo_config_t *fifo_config; + const usb_dwc_hal_fifo_config_t *fifo_config; const fifo_mps_limits_t *mps_limits; switch (port_config->fifo_bias) { case HCD_PORT_FIFO_BIAS_BALANCED: @@ -1340,7 +1340,7 @@ esp_err_t hcd_port_init(int port_number, const hcd_port_config_t *port_config, h port_obj->callback = port_config->callback; port_obj->callback_arg = port_config->callback_arg; port_obj->context = port_config->context; - usbh_hal_init(port_obj->hal); + usb_dwc_hal_init(port_obj->hal); port_obj->initialized = true; //Clear the frame list. We set the frame list register and enable periodic scheduling after a successful reset memset(port_obj->frame_list, 0, FRAME_LIST_LEN * sizeof(uint32_t)); @@ -1364,7 +1364,7 @@ esp_err_t hcd_port_deinit(hcd_port_handle_t port_hdl) ESP_ERR_INVALID_STATE); port->initialized = false; esp_intr_disable(s_hcd_obj->isr_hdl); - usbh_hal_deinit(port->hal); + usb_dwc_hal_deinit(port->hal); HCD_EXIT_CRITICAL(); return ESP_OK; @@ -1428,7 +1428,7 @@ esp_err_t hcd_port_get_speed(hcd_port_handle_t port_hdl, usb_speed_t *speed) HCD_ENTER_CRITICAL(); //Device speed is only valid if there is device connected to the port that has been reset HCD_CHECK_FROM_CRIT(port->flags.conn_dev_ena, ESP_ERR_INVALID_STATE); - usb_priv_speed_t hal_speed = usbh_hal_port_get_conn_speed(port->hal); + usb_priv_speed_t hal_speed = usb_dwc_hal_port_get_conn_speed(port->hal); if (hal_speed == USB_PRIV_SPEED_FULL) { *speed = USB_SPEED_FULL; } else { @@ -1483,12 +1483,12 @@ esp_err_t hcd_port_recover(hcd_port_handle_t port_hdl) ESP_ERR_INVALID_STATE); //We are about to do a soft reset on the peripheral. Disable the peripheral throughout esp_intr_disable(s_hcd_obj->isr_hdl); - usbh_hal_core_soft_reset(port->hal); + usb_dwc_hal_core_soft_reset(port->hal); port->state = HCD_PORT_STATE_NOT_POWERED; port->last_event = HCD_PORT_EVENT_NONE; port->flags.val = 0; //Soft reset wipes all registers so we need to reinitialize the HAL - usbh_hal_init(port->hal); + usb_dwc_hal_init(port->hal); //Clear the frame list. We set the frame list register and enable periodic scheduling after a successful reset memset(port->frame_list, 0, FRAME_LIST_LEN * sizeof(uint32_t)); esp_intr_enable(s_hcd_obj->isr_hdl); @@ -1510,7 +1510,7 @@ esp_err_t hcd_port_set_fifo_bias(hcd_port_handle_t port_hdl, hcd_port_fifo_bias_ { esp_err_t ret; //Get a pointer to the correct FIFO bias constant values - const usbh_hal_fifo_config_t *fifo_config; + const usb_dwc_hal_fifo_config_t *fifo_config; const fifo_mps_limits_t *mps_limits; switch (bias) { case HCD_PORT_FIFO_BIAS_BALANCED: @@ -1537,7 +1537,7 @@ esp_err_t hcd_port_set_fifo_bias(hcd_port_handle_t port_hdl, hcd_port_fifo_bias_ HCD_ENTER_CRITICAL(); //Check that port is in the correct state to update FIFO sizes if (port->initialized && !port->flags.event_pending && port->num_pipes_idle == 0 && port->num_pipes_queued == 0) { - usbh_hal_set_fifo_size(port->hal, fifo_config); + usb_dwc_hal_set_fifo_size(port->hal, fifo_config); port->fifo_config = fifo_config; port->fifo_mps_limits = mps_limits; ret = ESP_OK; @@ -1553,20 +1553,20 @@ esp_err_t hcd_port_set_fifo_bias(hcd_port_handle_t port_hdl, hcd_port_fifo_bias_ // ----------------------- Private ------------------------- -static inline hcd_pipe_event_t pipe_decode_error_event(usbh_hal_chan_error_t chan_error) +static inline hcd_pipe_event_t pipe_decode_error_event(usb_dwc_hal_chan_error_t chan_error) { hcd_pipe_event_t event = HCD_PIPE_EVENT_NONE; switch (chan_error) { - case USBH_HAL_CHAN_ERROR_XCS_XACT: + case USB_DWC_HAL_CHAN_ERROR_XCS_XACT: event = HCD_PIPE_EVENT_ERROR_XFER; break; - case USBH_HAL_CHAN_ERROR_BNA: + case USB_DWC_HAL_CHAN_ERROR_BNA: event = HCD_PIPE_EVENT_ERROR_URB_NOT_AVAIL; break; - case USBH_HAL_CHAN_ERROR_PKT_BBL: + case USB_DWC_HAL_CHAN_ERROR_PKT_BBL: event = HCD_PIPE_EVENT_ERROR_OVERFLOW; break; - case USBH_HAL_CHAN_ERROR_STALL: + case USB_DWC_HAL_CHAN_ERROR_STALL: event = HCD_PIPE_EVENT_ERROR_STALL; break; } @@ -1591,7 +1591,7 @@ static dma_buffer_block_t *buffer_block_alloc(usb_transfer_type_t type) break; } dma_buffer_block_t *buffer = calloc(1, sizeof(dma_buffer_block_t)); - void *xfer_desc_list = heap_caps_aligned_calloc(USBH_HAL_DMA_MEM_ALIGN, desc_list_len, sizeof(usbh_ll_dma_qtd_t), MALLOC_CAP_DMA); + void *xfer_desc_list = heap_caps_aligned_calloc(USB_DWC_HAL_DMA_MEM_ALIGN, desc_list_len, sizeof(usb_dwc_ll_dma_qtd_t), MALLOC_CAP_DMA); if (buffer == NULL || xfer_desc_list == NULL) { free(buffer); heap_caps_free(xfer_desc_list); @@ -1649,7 +1649,7 @@ static bool pipe_alloc_check_args(const hcd_pipe_config_t *pipe_config, usb_spee return (pipe_config->ep_desc->wMaxPacketSize <= limit); } -static void pipe_set_ep_char(const hcd_pipe_config_t *pipe_config, usb_transfer_type_t type, bool is_default_pipe, int pipe_idx, usb_speed_t port_speed, usbh_hal_ep_char_t *ep_char) +static void pipe_set_ep_char(const hcd_pipe_config_t *pipe_config, usb_transfer_type_t type, bool is_default_pipe, int pipe_idx, usb_speed_t port_speed, usb_dwc_hal_ep_char_t *ep_char) { //Initialize EP characteristics usb_priv_xfer_type_t hal_xfer_type; @@ -1722,7 +1722,7 @@ static esp_err_t _pipe_cmd_halt(pipe_t *pipe) } //If the pipe's port is invalid, we just mark the pipe as halted without needing to halt the underlying channel if (pipe->port->flags.conn_dev_ena //Skip halting the underlying channel if the port is invalid - && !usbh_hal_chan_request_halt(pipe->chan_obj)) { //Check if the channel is already halted + && !usb_dwc_hal_chan_request_halt(pipe->chan_obj)) { //Check if the channel is already halted //Channel is not halted, we need to request and wait for a haltWe need to wait for channel to be halted. pipe->cs_flags.waiting_halt = 1; _internal_pipe_event_wait(pipe); @@ -1730,7 +1730,7 @@ static esp_err_t _pipe_cmd_halt(pipe_t *pipe) assert(pipe->state == HCD_PIPE_STATE_HALTED); } else { //We are already halted, just need to update the state - usbh_hal_chan_mark_halted(pipe->chan_obj); + usb_dwc_hal_chan_mark_halted(pipe->chan_obj); pipe->state = HCD_PIPE_STATE_HALTED; } ret = ESP_OK; @@ -1842,7 +1842,7 @@ esp_err_t hcd_pipe_alloc(hcd_port_handle_t port_hdl, const hcd_pipe_config_t *pi esp_err_t ret; //Allocate the pipe resources pipe_t *pipe = calloc(1, sizeof(pipe_t)); - usbh_hal_chan_t *chan_obj = calloc(1, sizeof(usbh_hal_chan_t)); + usb_dwc_hal_chan_t *chan_obj = calloc(1, sizeof(usb_dwc_hal_chan_t)); dma_buffer_block_t *buffers[NUM_BUFFERS] = {0}; if (pipe == NULL|| chan_obj == NULL) { ret = ESP_ERR_NO_MEM; @@ -1865,9 +1865,9 @@ esp_err_t hcd_pipe_alloc(hcd_port_handle_t port_hdl, const hcd_pipe_config_t *pi pipe->multi_buffer_control.buffer_num_to_fill = NUM_BUFFERS; pipe->port = port; pipe->chan_obj = chan_obj; - usbh_hal_ep_char_t ep_char; + usb_dwc_hal_ep_char_t ep_char; pipe_set_ep_char(pipe_config, type, is_default, pipe_idx, port_speed, &ep_char); - memcpy(&pipe->ep_char, &ep_char, sizeof(usbh_hal_ep_char_t)); + memcpy(&pipe->ep_char, &ep_char, sizeof(usb_dwc_hal_ep_char_t)); pipe->state = HCD_PIPE_STATE_ACTIVE; pipe->callback = pipe_config->callback; pipe->callback_arg = pipe_config->callback_arg; @@ -1880,13 +1880,13 @@ esp_err_t hcd_pipe_alloc(hcd_port_handle_t port_hdl, const hcd_pipe_config_t *pi ret = ESP_ERR_INVALID_STATE; goto err; } - bool chan_allocated = usbh_hal_chan_alloc(port->hal, pipe->chan_obj, (void *) pipe); + bool chan_allocated = usb_dwc_hal_chan_alloc(port->hal, pipe->chan_obj, (void *) pipe); if (!chan_allocated) { HCD_EXIT_CRITICAL(); ret = ESP_ERR_NOT_SUPPORTED; goto err; } - usbh_hal_chan_set_ep_char(port->hal, pipe->chan_obj, &pipe->ep_char); + usb_dwc_hal_chan_set_ep_char(port->hal, pipe->chan_obj, &pipe->ep_char); //Add the pipe to the list of idle pipes in the port object TAILQ_INSERT_TAIL(&port->pipes_idle_tailq, pipe, tailq_entry); port->num_pipes_idle++; @@ -1916,7 +1916,7 @@ esp_err_t hcd_pipe_free(hcd_pipe_handle_t pipe_hdl) //Remove pipe from the list of idle pipes (it must be in the idle list because it should have no queued URBs) TAILQ_REMOVE(&pipe->port->pipes_idle_tailq, pipe, tailq_entry); pipe->port->num_pipes_idle--; - usbh_hal_chan_free(pipe->port->hal, pipe->chan_obj); + usb_dwc_hal_chan_free(pipe->port->hal, pipe->chan_obj); HCD_EXIT_CRITICAL(); //Free pipe resources @@ -1939,7 +1939,7 @@ esp_err_t hcd_pipe_update_mps(hcd_pipe_handle_t pipe_hdl, int mps) ESP_ERR_INVALID_STATE); pipe->ep_char.mps = mps; //Update the underlying channel's registers - usbh_hal_chan_set_ep_char(pipe->port->hal, pipe->chan_obj, &pipe->ep_char); + usb_dwc_hal_chan_set_ep_char(pipe->port->hal, pipe->chan_obj, &pipe->ep_char); HCD_EXIT_CRITICAL(); return ESP_OK; } @@ -1955,7 +1955,7 @@ esp_err_t hcd_pipe_update_dev_addr(hcd_pipe_handle_t pipe_hdl, uint8_t dev_addr) ESP_ERR_INVALID_STATE); pipe->ep_char.dev_addr = dev_addr; //Update the underlying channel's registers - usbh_hal_chan_set_ep_char(pipe->port->hal, pipe->chan_obj, &pipe->ep_char); + usb_dwc_hal_chan_set_ep_char(pipe->port->hal, pipe->chan_obj, &pipe->ep_char); HCD_EXIT_CRITICAL(); return ESP_OK; } @@ -2060,20 +2060,20 @@ static inline void _buffer_fill_ctrl(dma_buffer_block_t *buffer, usb_transfer_t bool data_stg_in = (setup_pkt->bmRequestType & USB_BM_REQUEST_TYPE_DIR_IN); bool data_stg_skip = (setup_pkt->wLength == 0); //Fill setup stage - usbh_hal_xfer_desc_fill(buffer->xfer_desc_list, 0, transfer->data_buffer, sizeof(usb_setup_packet_t), - USBH_HAL_XFER_DESC_FLAG_SETUP | USBH_HAL_XFER_DESC_FLAG_HOC); + usb_dwc_hal_xfer_desc_fill(buffer->xfer_desc_list, 0, transfer->data_buffer, sizeof(usb_setup_packet_t), + USB_DWC_HAL_XFER_DESC_FLAG_SETUP | USB_DWC_HAL_XFER_DESC_FLAG_HOC); //Fill data stage if (data_stg_skip) { //Not data stage. Fill with an empty descriptor - usbh_hal_xfer_desc_clear(buffer->xfer_desc_list, 1); + usb_dwc_hal_xfer_desc_clear(buffer->xfer_desc_list, 1); } else { //Fill data stage. Note that we still fill with transfer->num_bytes instead of setup_pkt->wLength as it's possible to require more bytes than wLength - usbh_hal_xfer_desc_fill(buffer->xfer_desc_list, 1, transfer->data_buffer + sizeof(usb_setup_packet_t), transfer->num_bytes - sizeof(usb_setup_packet_t), - ((data_stg_in) ? USBH_HAL_XFER_DESC_FLAG_IN : 0) | USBH_HAL_XFER_DESC_FLAG_HOC); + usb_dwc_hal_xfer_desc_fill(buffer->xfer_desc_list, 1, transfer->data_buffer + sizeof(usb_setup_packet_t), transfer->num_bytes - sizeof(usb_setup_packet_t), + ((data_stg_in) ? USB_DWC_HAL_XFER_DESC_FLAG_IN : 0) | USB_DWC_HAL_XFER_DESC_FLAG_HOC); } //Fill status stage (i.e., a zero length packet). If data stage is skipped, the status stage is always IN. - usbh_hal_xfer_desc_fill(buffer->xfer_desc_list, 2, NULL, 0, - ((data_stg_in && !data_stg_skip) ? 0 : USBH_HAL_XFER_DESC_FLAG_IN) | USBH_HAL_XFER_DESC_FLAG_HOC); + usb_dwc_hal_xfer_desc_fill(buffer->xfer_desc_list, 2, NULL, 0, + ((data_stg_in && !data_stg_skip) ? 0 : USB_DWC_HAL_XFER_DESC_FLAG_IN) | USB_DWC_HAL_XFER_DESC_FLAG_HOC); //Update buffer flags buffer->flags.ctrl.data_stg_in = data_stg_in; buffer->flags.ctrl.data_stg_skip = data_stg_skip; @@ -2086,16 +2086,16 @@ static inline void _buffer_fill_bulk(dma_buffer_block_t *buffer, usb_transfer_t //Minor optimization: Do the mod operation last bool zero_len_packet = !is_in && (transfer->flags & USB_TRANSFER_FLAG_ZERO_PACK) && (transfer->num_bytes % mps == 0); if (is_in) { - usbh_hal_xfer_desc_fill(buffer->xfer_desc_list, 0, transfer->data_buffer, transfer->num_bytes, - USBH_HAL_XFER_DESC_FLAG_IN | USBH_HAL_XFER_DESC_FLAG_HOC); + usb_dwc_hal_xfer_desc_fill(buffer->xfer_desc_list, 0, transfer->data_buffer, transfer->num_bytes, + USB_DWC_HAL_XFER_DESC_FLAG_IN | USB_DWC_HAL_XFER_DESC_FLAG_HOC); } else { //OUT if (zero_len_packet) { //Adding a zero length packet, so two descriptors are used. - usbh_hal_xfer_desc_fill(buffer->xfer_desc_list, 0, transfer->data_buffer, transfer->num_bytes, 0); - usbh_hal_xfer_desc_fill(buffer->xfer_desc_list, 1, NULL, 0, USBH_HAL_XFER_DESC_FLAG_HOC); + usb_dwc_hal_xfer_desc_fill(buffer->xfer_desc_list, 0, transfer->data_buffer, transfer->num_bytes, 0); + usb_dwc_hal_xfer_desc_fill(buffer->xfer_desc_list, 1, NULL, 0, USB_DWC_HAL_XFER_DESC_FLAG_HOC); } else { //Zero length packet not required. One descriptor is enough - usbh_hal_xfer_desc_fill(buffer->xfer_desc_list, 0, transfer->data_buffer, transfer->num_bytes, USBH_HAL_XFER_DESC_FLAG_HOC); + usb_dwc_hal_xfer_desc_fill(buffer->xfer_desc_list, 0, transfer->data_buffer, transfer->num_bytes, USB_DWC_HAL_XFER_DESC_FLAG_HOC); } } //Update buffer flags @@ -2119,24 +2119,24 @@ static inline void _buffer_fill_intr(dma_buffer_block_t *buffer, usb_transfer_t } assert((zero_len_packet) ? num_qtds + 1 : num_qtds <= XFER_LIST_LEN_INTR); //Check that the number of QTDs doesn't exceed the QTD list's length - uint32_t xfer_desc_flags = (is_in) ? USBH_HAL_XFER_DESC_FLAG_IN : 0; + uint32_t xfer_desc_flags = (is_in) ? USB_DWC_HAL_XFER_DESC_FLAG_IN : 0; int bytes_filled = 0; //Fill all but last QTD for (int i = 0; i < num_qtds - 1; i++) { - usbh_hal_xfer_desc_fill(buffer->xfer_desc_list, i, &transfer->data_buffer[bytes_filled], mps, xfer_desc_flags); + usb_dwc_hal_xfer_desc_fill(buffer->xfer_desc_list, i, &transfer->data_buffer[bytes_filled], mps, xfer_desc_flags); bytes_filled += mps; } //Fill last QTD and zero length packet if (zero_len_packet) { //Fill in last data packet without HOC flag - usbh_hal_xfer_desc_fill(buffer->xfer_desc_list, num_qtds - 1, &transfer->data_buffer[bytes_filled], transfer->num_bytes - bytes_filled, + usb_dwc_hal_xfer_desc_fill(buffer->xfer_desc_list, num_qtds - 1, &transfer->data_buffer[bytes_filled], transfer->num_bytes - bytes_filled, xfer_desc_flags); //HOC flag goes to zero length packet instead - usbh_hal_xfer_desc_fill(buffer->xfer_desc_list, num_qtds, NULL, 0, USBH_HAL_XFER_DESC_FLAG_HOC); + usb_dwc_hal_xfer_desc_fill(buffer->xfer_desc_list, num_qtds, NULL, 0, USB_DWC_HAL_XFER_DESC_FLAG_HOC); } else { //Zero length packet not required. Fill in last QTD with HOC flag - usbh_hal_xfer_desc_fill(buffer->xfer_desc_list, num_qtds - 1, &transfer->data_buffer[bytes_filled], transfer->num_bytes - bytes_filled, - xfer_desc_flags | USBH_HAL_XFER_DESC_FLAG_HOC); + usb_dwc_hal_xfer_desc_fill(buffer->xfer_desc_list, num_qtds - 1, &transfer->data_buffer[bytes_filled], transfer->num_bytes - bytes_filled, + xfer_desc_flags | USB_DWC_HAL_XFER_DESC_FLAG_HOC); } //Update buffer members and flags @@ -2154,19 +2154,19 @@ static inline void _buffer_fill_isoc(dma_buffer_block_t *buffer, usb_transfer_t //For each packet, fill in a descriptor and a interval-1 blank descriptor after it for (int pkt_idx = 0; pkt_idx < transfer->num_isoc_packets; pkt_idx++) { int xfer_len = transfer->isoc_packet_desc[pkt_idx].num_bytes; - uint32_t flags = (is_in) ? USBH_HAL_XFER_DESC_FLAG_IN : 0; + uint32_t flags = (is_in) ? USB_DWC_HAL_XFER_DESC_FLAG_IN : 0; if (pkt_idx == transfer->num_isoc_packets - 1) { //Last packet, set the the HOC flag - flags |= USBH_HAL_XFER_DESC_FLAG_HOC; + flags |= USB_DWC_HAL_XFER_DESC_FLAG_HOC; } - usbh_hal_xfer_desc_fill(buffer->xfer_desc_list, desc_idx, &transfer->data_buffer[bytes_filled], xfer_len, flags); + usb_dwc_hal_xfer_desc_fill(buffer->xfer_desc_list, desc_idx, &transfer->data_buffer[bytes_filled], xfer_len, flags); bytes_filled += xfer_len; if (++desc_idx >= XFER_LIST_LEN_ISOC) { desc_idx = 0; } //Clear descriptors for unscheduled frames for (int i = 0; i < interval - 1; i++) { - usbh_hal_xfer_desc_clear(buffer->xfer_desc_list, desc_idx); + usb_dwc_hal_xfer_desc_clear(buffer->xfer_desc_list, desc_idx); if (++desc_idx >= XFER_LIST_LEN_ISOC) { desc_idx = 0; } @@ -2204,7 +2204,7 @@ static void _buffer_fill(pipe_t *pipe) uint32_t start_idx; if (pipe->multi_buffer_control.buffer_num_to_exec == 0) { //There are no more previously filled buffers to execute. We need to calculate a new start index based on HFNUM and the pipe's schedule - uint32_t cur_frame_num = usbh_hal_port_get_cur_frame_num(pipe->port->hal); + uint32_t cur_frame_num = usb_dwc_hal_port_get_cur_frame_num(pipe->port->hal); uint32_t cur_mod_idx_no_offset = (cur_frame_num - pipe->ep_char.periodic.phase_offset_frames) & (XFER_LIST_LEN_ISOC - 1); //Get the modulated index (i.e., the Nth desc in the descriptor list) //This is the non-offset modulated QTD index of the last scheduled interval uint32_t last_interval_mod_idx_no_offset = (cur_mod_idx_no_offset / pipe->ep_char.periodic.interval) * pipe->ep_char.periodic.interval; //Floor divide and the multiply again @@ -2260,8 +2260,8 @@ static void _buffer_exec(pipe_t *pipe) start_idx = 0; desc_list_len = XFER_LIST_LEN_CTRL; //Set the channel's direction to OUT and PID to 0 respectively for the the setup stage - usbh_hal_chan_set_dir(pipe->chan_obj, false); //Setup stage is always OUT - usbh_hal_chan_set_pid(pipe->chan_obj, 0); //Setup stage always has a PID of DATA0 + usb_dwc_hal_chan_set_dir(pipe->chan_obj, false); //Setup stage is always OUT + usb_dwc_hal_chan_set_pid(pipe->chan_obj, 0); //Setup stage always has a PID of DATA0 break; } case USB_PRIV_XFER_TYPE_ISOCHRONOUS: { @@ -2289,7 +2289,7 @@ static void _buffer_exec(pipe_t *pipe) //Update buffer and multi buffer flags buffer_to_exec->status_flags.executing = 1; pipe->multi_buffer_control.buffer_is_executing = 1; - usbh_hal_chan_activate(pipe->chan_obj, buffer_to_exec->xfer_desc_list, desc_list_len, start_idx); + usb_dwc_hal_chan_activate(pipe->chan_obj, buffer_to_exec->xfer_desc_list, desc_list_len, start_idx); } static void _buffer_exec_cont(pipe_t *pipe) @@ -2318,9 +2318,9 @@ static void _buffer_exec_cont(pipe_t *pipe) buffer_inflight->flags.ctrl.cur_stg = 2; } //Continue the control transfer - usbh_hal_chan_set_dir(pipe->chan_obj, next_dir_is_in); - usbh_hal_chan_set_pid(pipe->chan_obj, next_pid); - usbh_hal_chan_activate(pipe->chan_obj, buffer_inflight->xfer_desc_list, XFER_LIST_LEN_CTRL, buffer_inflight->flags.ctrl.cur_stg); + usb_dwc_hal_chan_set_dir(pipe->chan_obj, next_dir_is_in); + usb_dwc_hal_chan_set_pid(pipe->chan_obj, next_pid); + usb_dwc_hal_chan_activate(pipe->chan_obj, buffer_inflight->xfer_desc_list, XFER_LIST_LEN_CTRL, buffer_inflight->flags.ctrl.cur_stg); } static inline void _buffer_parse_ctrl(dma_buffer_block_t *buffer) @@ -2334,15 +2334,15 @@ static inline void _buffer_parse_ctrl(dma_buffer_block_t *buffer) //Parse the data stage for the remaining length int rem_len; int desc_status; - usbh_hal_xfer_desc_parse(buffer->xfer_desc_list, 1, &rem_len, &desc_status); - assert(desc_status == USBH_HAL_XFER_DESC_STS_SUCCESS); + usb_dwc_hal_xfer_desc_parse(buffer->xfer_desc_list, 1, &rem_len, &desc_status); + assert(desc_status == USB_DWC_HAL_XFER_DESC_STS_SUCCESS); assert(rem_len <= (transfer->num_bytes - sizeof(usb_setup_packet_t))); transfer->actual_num_bytes = transfer->num_bytes - rem_len; } //Update URB status transfer->status = USB_TRANSFER_STATUS_COMPLETED; //Clear the descriptor list - memset(buffer->xfer_desc_list, XFER_LIST_LEN_CTRL, sizeof(usbh_ll_dma_qtd_t)); + memset(buffer->xfer_desc_list, 0, XFER_LIST_LEN_CTRL * sizeof(usb_dwc_ll_dma_qtd_t)); } static inline void _buffer_parse_bulk(dma_buffer_block_t *buffer) @@ -2351,14 +2351,14 @@ static inline void _buffer_parse_bulk(dma_buffer_block_t *buffer) //Update URB's actual number of bytes int rem_len; int desc_status; - usbh_hal_xfer_desc_parse(buffer->xfer_desc_list, 0, &rem_len, &desc_status); - assert(desc_status == USBH_HAL_XFER_DESC_STS_SUCCESS); + usb_dwc_hal_xfer_desc_parse(buffer->xfer_desc_list, 0, &rem_len, &desc_status); + assert(desc_status == USB_DWC_HAL_XFER_DESC_STS_SUCCESS); assert(rem_len <= transfer->num_bytes); transfer->actual_num_bytes = transfer->num_bytes - rem_len; //Update URB's status transfer->status = USB_TRANSFER_STATUS_COMPLETED; //Clear the descriptor list - memset(buffer->xfer_desc_list, XFER_LIST_LEN_BULK, sizeof(usbh_ll_dma_qtd_t)); + memset(buffer->xfer_desc_list, 0, XFER_LIST_LEN_BULK * sizeof(usb_dwc_ll_dma_qtd_t)); } static inline void _buffer_parse_intr(dma_buffer_block_t *buffer, bool is_in, int mps) @@ -2371,12 +2371,12 @@ static inline void _buffer_parse_intr(dma_buffer_block_t *buffer, bool is_in, in int rem_len; int desc_status; for (int i = 0; i < intr_stop_idx - 1; i++) { //Check all packets before the short - usbh_hal_xfer_desc_parse(buffer->xfer_desc_list, i, &rem_len, &desc_status); - assert(rem_len == 0 && desc_status == USBH_HAL_XFER_DESC_STS_SUCCESS); + usb_dwc_hal_xfer_desc_parse(buffer->xfer_desc_list, i, &rem_len, &desc_status); + assert(rem_len == 0 && desc_status == USB_DWC_HAL_XFER_DESC_STS_SUCCESS); } //Check the short packet - usbh_hal_xfer_desc_parse(buffer->xfer_desc_list, intr_stop_idx - 1, &rem_len, &desc_status); - assert(rem_len > 0 && desc_status == USBH_HAL_XFER_DESC_STS_SUCCESS); + usb_dwc_hal_xfer_desc_parse(buffer->xfer_desc_list, intr_stop_idx - 1, &rem_len, &desc_status); + assert(rem_len > 0 && desc_status == USB_DWC_HAL_XFER_DESC_STS_SUCCESS); //Update actual bytes transfer->actual_num_bytes = (mps * intr_stop_idx - 2) + (mps - rem_len); } else { @@ -2384,14 +2384,14 @@ static inline void _buffer_parse_intr(dma_buffer_block_t *buffer, bool is_in, in for (int i = 0; i < buffer->flags.intr.num_qtds - 1; i++) { int rem_len; int desc_status; - usbh_hal_xfer_desc_parse(buffer->xfer_desc_list, i, &rem_len, &desc_status); - assert(rem_len == 0 && desc_status == USBH_HAL_XFER_DESC_STS_SUCCESS); + usb_dwc_hal_xfer_desc_parse(buffer->xfer_desc_list, i, &rem_len, &desc_status); + assert(rem_len == 0 && desc_status == USB_DWC_HAL_XFER_DESC_STS_SUCCESS); } //Check the last packet int last_packet_rem_len; int last_packet_desc_status; - usbh_hal_xfer_desc_parse(buffer->xfer_desc_list, buffer->flags.intr.num_qtds - 1, &last_packet_rem_len, &last_packet_desc_status); - assert(last_packet_desc_status == USBH_HAL_XFER_DESC_STS_SUCCESS); + usb_dwc_hal_xfer_desc_parse(buffer->xfer_desc_list, buffer->flags.intr.num_qtds - 1, &last_packet_rem_len, &last_packet_desc_status); + assert(last_packet_desc_status == USB_DWC_HAL_XFER_DESC_STS_SUCCESS); //All packets except last MUST be MPS. So just deduct the remaining length of the last packet to get actual number of bytes transfer->actual_num_bytes = transfer->num_bytes - last_packet_rem_len; } @@ -2400,15 +2400,15 @@ static inline void _buffer_parse_intr(dma_buffer_block_t *buffer, bool is_in, in for (int i = 0 ; i < buffer->flags.intr.num_qtds; i++) { int rem_len; int desc_status; - usbh_hal_xfer_desc_parse(buffer->xfer_desc_list, i, &rem_len, &desc_status); - assert(rem_len == 0 && desc_status == USBH_HAL_XFER_DESC_STS_SUCCESS); + usb_dwc_hal_xfer_desc_parse(buffer->xfer_desc_list, i, &rem_len, &desc_status); + assert(rem_len == 0 && desc_status == USB_DWC_HAL_XFER_DESC_STS_SUCCESS); } transfer->actual_num_bytes = transfer->num_bytes; } //Update URB's status transfer->status = USB_TRANSFER_STATUS_COMPLETED; //Clear the descriptor list - memset(buffer->xfer_desc_list, XFER_LIST_LEN_INTR, sizeof(usbh_ll_dma_qtd_t)); + memset(buffer->xfer_desc_list, 0, XFER_LIST_LEN_INTR * sizeof(usb_dwc_ll_dma_qtd_t)); } static inline void _buffer_parse_isoc(dma_buffer_block_t *buffer, bool is_in) @@ -2420,15 +2420,15 @@ static inline void _buffer_parse_isoc(dma_buffer_block_t *buffer, bool is_in) //Clear the filled descriptor int rem_len; int desc_status; - usbh_hal_xfer_desc_parse(buffer->xfer_desc_list, desc_idx, &rem_len, &desc_status); - usbh_hal_xfer_desc_clear(buffer->xfer_desc_list, desc_idx); + usb_dwc_hal_xfer_desc_parse(buffer->xfer_desc_list, desc_idx, &rem_len, &desc_status); + usb_dwc_hal_xfer_desc_clear(buffer->xfer_desc_list, desc_idx); assert(rem_len == 0 || is_in); - assert(desc_status == USBH_HAL_XFER_DESC_STS_SUCCESS || USBH_HAL_XFER_DESC_STS_NOT_EXECUTED); + assert(desc_status == USB_DWC_HAL_XFER_DESC_STS_SUCCESS || USB_DWC_HAL_XFER_DESC_STS_NOT_EXECUTED); assert(rem_len <= transfer->isoc_packet_desc[pkt_idx].num_bytes); //Check for DMA errata //Update ISO packet actual length and status transfer->isoc_packet_desc[pkt_idx].actual_num_bytes = transfer->isoc_packet_desc[pkt_idx].num_bytes - rem_len; total_actual_num_bytes += transfer->isoc_packet_desc[pkt_idx].actual_num_bytes; - transfer->isoc_packet_desc[pkt_idx].status = (desc_status == USBH_HAL_XFER_DESC_STS_NOT_EXECUTED) ? USB_TRANSFER_STATUS_SKIPPED : USB_TRANSFER_STATUS_COMPLETED; + transfer->isoc_packet_desc[pkt_idx].status = (desc_status == USB_DWC_HAL_XFER_DESC_STS_NOT_EXECUTED) ? USB_TRANSFER_STATUS_SKIPPED : USB_TRANSFER_STATUS_COMPLETED; //A descriptor is also allocated for unscheduled frames. We need to skip over them desc_idx += buffer->flags.isoc.interval; if (desc_idx >= XFER_LIST_LEN_INTR) { diff --git a/components/usb/test/CMakeLists.txt b/components/usb/test/CMakeLists.txt index 71754ca539..7857c7ee66 100644 --- a/components/usb/test/CMakeLists.txt +++ b/components/usb/test/CMakeLists.txt @@ -10,4 +10,3 @@ idf_component_register( PRIV_INCLUDE_DIRS "../private_include" "common" "hcd" "usb_host" PRIV_REQUIRES cmock usb test_utils ) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/components/usb/test/common/test_usb_mock_classes.c b/components/usb/test/common/test_usb_mock_classes.c index 7a626cfbcd..1a049fd447 100644 --- a/components/usb/test/common/test_usb_mock_classes.c +++ b/components/usb/test/common/test_usb_mock_classes.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include #include #include #include "usb/usb_types_ch9.h" @@ -83,15 +83,15 @@ bool mock_msc_scsi_check_csw(mock_msc_bulk_csw_t *csw, uint32_t tag_expect) bool no_issues = true; if (csw->dCSWSignature != 0x53425355) { no_issues = false; - printf("Warning: csw signature corrupt (0x%X)\n", csw->dCSWSignature); + printf("Warning: csw signature corrupt (0x%"PRIX32")\n", csw->dCSWSignature); } if (csw->dCSWTag != tag_expect) { no_issues = false; - printf("Warning: csw tag unexpected! Expected %d got %d\n", tag_expect, csw->dCSWTag); + printf("Warning: csw tag unexpected! Expected %"PRIu32" got %"PRIu32"\n", tag_expect, csw->dCSWTag); } if (csw->dCSWDataResidue) { no_issues = false; - printf("Warning: csw indicates data residue of %d bytes!\n", csw->dCSWDataResidue); + printf("Warning: csw indicates data residue of %"PRIu32" bytes!\n", csw->dCSWDataResidue); } if (csw->bCSWStatus) { no_issues = false; diff --git a/components/usb/usbh.c b/components/usb/usbh.c index 858ce3d0c9..6426e16c8f 100644 --- a/components/usb/usbh.c +++ b/components/usb/usbh.c @@ -407,7 +407,7 @@ esp_err_t usbh_process(void) Exit critical section to handle device action flags in their listed order --------------------------------------------------------------------- */ USBH_EXIT_CRITICAL(); - ESP_LOGD(USBH_TAG, "Processing actions 0x%x", action_flags); + ESP_LOGD(USBH_TAG, "Processing actions 0x%"PRIx32"", action_flags); //Sanity check. If the device is being freed, there must not be any other action flags set assert(!(action_flags & DEV_FLAG_ACTION_FREE) || action_flags == DEV_FLAG_ACTION_FREE); diff --git a/components/vfs/CMakeLists.txt b/components/vfs/CMakeLists.txt index f21385edce..058d7f3a93 100644 --- a/components/vfs/CMakeLists.txt +++ b/components/vfs/CMakeLists.txt @@ -1,11 +1,16 @@ -idf_component_register(SRCS "vfs.c" - "vfs_eventfd.c" - "vfs_uart.c" - "vfs_semihost.c" - "vfs_console.c" - INCLUDE_DIRS include - PRIV_INCLUDE_DIRS private_include - PRIV_REQUIRES driver esp_timer) +list(APPEND sources "vfs.c" + "vfs_eventfd.c" + "vfs_uart.c" + "vfs_semihost.c" + "vfs_console.c") + +list(APPEND pr driver + esp_timer) + +idf_component_register(SRCS ${sources} + INCLUDE_DIRS include + PRIV_INCLUDE_DIRS private_include + PRIV_REQUIRES ${pr}) if(CONFIG_ESP_CONSOLE_USB_CDC) target_sources(${COMPONENT_LIB} PRIVATE "vfs_cdcacm.c") diff --git a/components/vfs/openocd_semihosting.h b/components/vfs/openocd_semihosting.h index 32dfeb75a9..bcf5c1eca6 100644 --- a/components/vfs/openocd_semihosting.h +++ b/components/vfs/openocd_semihosting.h @@ -31,27 +31,27 @@ extern "C" { * these are not supported in ESP-IDF yet. */ -#define SEMIHOSTING_SYS_CLOCK 0x10 -#define SEMIHOSTING_SYS_CLOSE 0x02 -#define SEMIHOSTING_SYS_ERRNO 0x13 -#define SEMIHOSTING_SYS_EXIT 0x18 -#define SEMIHOSTING_SYS_EXIT_EXTENDED 0x20 -#define SEMIHOSTING_SYS_FLEN 0x0C -#define SEMIHOSTING_SYS_GET_CMDLINE 0x15 -#define SEMIHOSTING_SYS_HEAPINFO 0x16 -#define SEMIHOSTING_SYS_ISERROR 0x08 -#define SEMIHOSTING_SYS_ISTTY 0x09 -#define SEMIHOSTING_SYS_OPEN 0x01 -#define SEMIHOSTING_SYS_READ 0x06 -#define SEMIHOSTING_SYS_READC 0x07 -#define SEMIHOSTING_SYS_REMOVE 0x0E -#define SEMIHOSTING_SYS_RENAME 0x0F -#define SEMIHOSTING_SYS_SEEK 0x0A -#define SEMIHOSTING_SYS_SYSTEM 0x12 -#define SEMIHOSTING_SYS_TIME 0x11 -#define SEMIHOSTING_SYS_WRITE 0x05 -#define SEMIHOSTING_SYS_WRITEC 0x03 -#define SEMIHOSTING_SYS_WRITE0 0x04 +#define SEMIHOSTING_SYS_OPEN 0x01 +#define SEMIHOSTING_SYS_CLOSE 0x02 +#define SEMIHOSTING_SYS_WRITEC 0x03 +#define SEMIHOSTING_SYS_WRITE0 0x04 +#define SEMIHOSTING_SYS_WRITE 0x05 +#define SEMIHOSTING_SYS_READ 0x06 +#define SEMIHOSTING_SYS_READC 0x07 +#define SEMIHOSTING_SYS_ISERROR 0x08 +#define SEMIHOSTING_SYS_ISTTY 0x09 +#define SEMIHOSTING_SYS_SEEK 0x0A +#define SEMIHOSTING_SYS_FLEN 0x0C +#define SEMIHOSTING_SYS_REMOVE 0x0E +#define SEMIHOSTING_SYS_RENAME 0x0F +#define SEMIHOSTING_SYS_CLOCK 0x10 +#define SEMIHOSTING_SYS_TIME 0x11 +#define SEMIHOSTING_SYS_SYSTEM 0x12 +#define SEMIHOSTING_SYS_ERRNO 0x13 +#define SEMIHOSTING_SYS_GET_CMDLINE 0x15 +#define SEMIHOSTING_SYS_HEAPINFO 0x16 +#define SEMIHOSTING_SYS_EXIT 0x18 +#define SEMIHOSTING_SYS_EXIT_EXTENDED 0x20 /* This call is an Espressif OpenOCD extension to send the version * information to the host. This lets the host support different IDF versions, @@ -114,7 +114,7 @@ static inline long semihosting_call(long id, long *data, int *out_errno) long ret = semihosting_call_noerrno(id, data); if (ret < 0) { const int semihosting_sys_errno = SEMIHOSTING_SYS_ERRNO; - *out_errno = (int) semihosting_call_noerrno(semihosting_sys_errno, NULL); + *out_errno = (int)semihosting_call_noerrno(semihosting_sys_errno, NULL); } return ret; } @@ -124,7 +124,7 @@ static inline int semihosting_open(const char *path, int open_mode, int mode) int host_errno = 0; long args[] = {(long) path, open_mode, strlen(path), 0}; (void) mode; // unused in OpenOCD - int result = (int) semihosting_call(SEMIHOSTING_SYS_OPEN, args, &host_errno); + int result = (int)semihosting_call(SEMIHOSTING_SYS_OPEN, args, &host_errno); if (result < 0) { errno = host_errno; } @@ -135,7 +135,7 @@ static inline ssize_t semihosting_write(int fd, const void *data, size_t size) { int host_errno = 0; long args[] = {fd, (long) data, size, 0}; - ssize_t ret = (ssize_t) semihosting_call(SEMIHOSTING_SYS_WRITE, args, &host_errno); + ssize_t ret = (ssize_t)semihosting_call(SEMIHOSTING_SYS_WRITE, args, &host_errno); if (ret < 0) { errno = host_errno; return ret; @@ -150,7 +150,7 @@ static inline ssize_t semihosting_read(int fd, void *data, size_t size) { int host_errno = 0; long args[] = {fd, (long) data, size, 0}; - ssize_t ret = (ssize_t) semihosting_call(SEMIHOSTING_SYS_READ, args, &host_errno); + ssize_t ret = (ssize_t)semihosting_call(SEMIHOSTING_SYS_READ, args, &host_errno); if (ret < 0) { errno = host_errno; return ret; @@ -165,7 +165,7 @@ static inline int semihosting_close(int fd) { int host_errno = 0; long args[] = {fd, 0, 0, 0}; - int ret = (int) semihosting_call(SEMIHOSTING_SYS_CLOSE, args, &host_errno); + int ret = (int)semihosting_call(SEMIHOSTING_SYS_CLOSE, args, &host_errno); if (ret < 0) { errno = host_errno; } @@ -176,7 +176,7 @@ static inline off_t semihosting_seek(int fd, off_t offset, int mode) { int host_errno = 0; long args[] = {fd, offset, mode, 0}; - off_t ret = (off_t) semihosting_call(ESP_SEMIHOSTING_SYS_SEEK, args, &host_errno); + off_t ret = (off_t)semihosting_call(ESP_SEMIHOSTING_SYS_SEEK, args, &host_errno); if (ret == -1) { errno = host_errno; } @@ -190,11 +190,188 @@ static inline int semihosting_ver_info(void) int version; } ver_info = { SEMIHOSTING_DRV_VERSION }; long args[] = {(long) &ver_info, sizeof(ver_info), 0, 0}; - int ret = (int) semihosting_call(ESP_SEMIHOSTING_SYS_DRV_INFO, args, &host_errno); + int ret = (int)semihosting_call(ESP_SEMIHOSTING_SYS_DRV_INFO, args, &host_errno); (void) host_errno; /* errno not set by this call */ return ret; } +static inline int semihosting_fstat(int fd, struct stat *restrict statbuf) +{ + int host_errno = 0; + long args[] = {fd, (int)statbuf, 0, 0}; + int ret = (int)semihosting_call(ESP_SEMIHOSTING_SYS_FSTAT, args, &host_errno); + if (ret < 0) { + errno = host_errno; + } + return ret; +} + +static inline int semihosting_fsync(int fd) +{ + int host_errno = 0; + long args[] = {fd, 0, 0, 0}; + int ret = (int)semihosting_call(ESP_SEMIHOSTING_SYS_FSYNC, args, &host_errno); + if (ret < 0) { + errno = host_errno; + } + return ret; +} + +#ifdef CONFIG_VFS_SUPPORT_DIR +static inline int semihosting_mkdir(const char *host_path, mode_t mode) +{ + int host_errno = 0; + long args[] = {(long)host_path, mode, strlen(host_path), 0}; + int ret = (int)semihosting_call(ESP_SEMIHOSTING_SYS_MKDIR, args, &host_errno); + if (ret < 0) { + errno = host_errno; + } + return ret; +} + +static inline int semihosting_rmdir(const char *host_path) +{ + int host_errno = 0; + long args[] = {(long)host_path, strlen(host_path), 0, 0}; + int ret = (int)semihosting_call(ESP_SEMIHOSTING_SYS_RMDIR, args, &host_errno); + if (ret < 0) { + errno = host_errno; + } + return ret; +} + +static inline int semihosting_access(const char *host_path, int mode) +{ + int host_errno = 0; + long args[] = {(long)host_path, strlen(host_path), mode, 0}; + int ret = (int)semihosting_call(ESP_SEMIHOSTING_SYS_ACCESS, args, &host_errno); + if (ret < 0) { + errno = host_errno; + } + return ret; +} + +static inline int semihosting_truncate(const char *host_path, off_t truncate_length) +{ + int host_errno = 0; + long args[] = {(long)host_path, strlen(host_path), truncate_length, 0}; + int ret = (int)semihosting_call(ESP_SEMIHOSTING_SYS_TRUNCATE, args, &host_errno); + if (ret < 0) { + errno = host_errno; + } + return ret; +} + +static inline int semihosting_utime(const char *host_path, const struct utimbuf *times) +{ + int host_errno = 0; + long args[] = {(long)host_path, strlen(host_path), times->actime, times->modtime}; + int ret = (int)semihosting_call(ESP_SEMIHOSTING_SYS_UTIME, args, &host_errno); + if (ret < 0) { + errno = host_errno; + } + return ret; +} + +static inline int semihosting_stat(const char *host_path, struct stat *restrict statbuf) +{ + int host_errno = 0; + long args[] = {(long)host_path, strlen(host_path), (int)statbuf, 0}; + int ret = (int)semihosting_call(ESP_SEMIHOSTING_SYS_STAT, args, &host_errno); + if (ret < 0) { + errno = host_errno; + } + return ret; +} + +static inline int semihosting_rename(const char *old_path, const char *new_path) +{ + int host_errno = 0; + long args[] = {(long)old_path, strlen(old_path), (long)new_path, strlen(new_path)}; + int ret = (int)semihosting_call(SEMIHOSTING_SYS_RENAME, args, &host_errno); + if (ret < 0) { + errno = host_errno; + } + return ret; +} + +static inline int semihosting_link(const char *path1, const char *path2) +{ + int host_errno = 0; + long args[] = {(long)path1, strlen(path1), (long)path2, strlen(path2)}; + int ret = (int)semihosting_call(ESP_SEMIHOSTING_SYS_LINK, args, &host_errno); + if (ret < 0) { + errno = host_errno; + } + return ret; +} + +static inline int semihosting_unlink(const char *path) +{ + int host_errno = 0; + long args[] = {(long)path, strlen(path), 0, 0}; + int ret = (int)semihosting_call(ESP_SEMIHOSTING_SYS_UNLINK, args, &host_errno); + if (ret < 0) { + errno = host_errno; + } + return ret; +} + +static inline int semihosting_opendir(const char *path, long offset) +{ + int host_errno = 0; + long args[] = {(long)path, strlen(path), offset, 0}; + int ret = (int)semihosting_call(ESP_SEMIHOSTING_SYS_OPENDIR, args, &host_errno); + if (ret < 0) { + errno = host_errno; + } + return ret; +} + +static inline int semihosting_readdir(int struct_dirent_ptr, long offset) +{ + int host_errno = 0; + long args[] = {struct_dirent_ptr, offset, 0, 0}; + int ret = (int)semihosting_call(ESP_SEMIHOSTING_SYS_READDIR, args, &host_errno); + if (ret < 0) { + errno = host_errno; + } + return ret; +} + +static inline int semihosting_closedir(long id) +{ + int host_errno = 0; + long args[] = {id, 0, 0, 0}; + int ret = (int)semihosting_call(ESP_SEMIHOSTING_SYS_CLOSEDIR, args, &host_errno); + if (ret < 0) { + errno = host_errno; + } + return ret; +} + +static inline long semihosting_telldir(long id) +{ + int host_errno = 0; + long args[] = {id, 0, 0, 0}; + long ret = semihosting_call(ESP_SEMIHOSTING_SYS_TELLDIR, args, &host_errno); + if (ret < 0) { + errno = host_errno; + } + return ret; +} +static inline int semihosting_seekdir(long id, long offset) +{ + int host_errno = 0; + long args[] = {id, offset, 0, 0}; + int ret = (int)semihosting_call(ESP_SEMIHOSTING_SYS_SEEKDIR, args, &host_errno); + if (ret < 0) { + errno = host_errno; + } + return ret; +} + +#endif #ifdef __cplusplus } #endif diff --git a/components/vfs/vfs_semihost.c b/components/vfs/vfs_semihost.c index 62d725f66b..b61397ff6e 100644 --- a/components/vfs/vfs_semihost.c +++ b/components/vfs/vfs_semihost.c @@ -19,8 +19,17 @@ #define CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS 1 #endif +#ifndef MIN +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + const static char *TAG = "esp_semihost"; +typedef struct { + char path[256]; /*!< VFS DIR stream path */ + struct dirent e; /*!< Last open dirent */ + long id; /*!< DIR* unique id */ +} vfs_semihost_dir_t; /* Additional open flags */ @@ -98,24 +107,20 @@ static esp_err_t vfs_semihost_drvinfo(vfs_semihost_ctx_t *ctx) static int vfs_semihost_open(void* ctx, const char* path, int flags, int mode) { - int ret_fd = -1; - FAIL_IF_NO_DEBUGGER(); if (path == NULL) { errno = ENOENT; - return ret_fd; + return -1; } ESP_LOGV(TAG, "%s: '%s 0x%x 0x%x'", __func__, path, flags, mode); - int o_mode = get_o_mode(flags); if (o_mode == -1) { /* if wrong flags - error */ errno = EINVAL; - } else { - ret_fd = semihosting_open(path, o_mode, mode); + return -1; } - return ret_fd; + return semihosting_open(path, o_mode, mode); } static ssize_t vfs_semihost_write(void* ctx, int fd, const void * data, size_t size) @@ -159,6 +164,261 @@ static off_t vfs_semihost_lseek(void* ctx, int fd, off_t offset, int mode) return semihosting_seek(fd, offset, mode); } +static int vfs_semihost_fstat(void* ctx, int fd, struct stat *restrict statbuf) +{ + FAIL_IF_NO_DEBUGGER(); + + if (statbuf == NULL) { + errno = ENOENT; + return -1; + } + + ESP_LOGV(TAG, "%s: '0x%x'", __func__, fd); + return semihosting_fstat(fd, statbuf); +} + +static int vfs_semihost_fsync(void* ctx, int fd) +{ + FAIL_IF_NO_DEBUGGER(); + + ESP_LOGV(TAG, "%s: '0x%x'", __func__, fd); + return semihosting_fsync(fd); +} + +#ifdef CONFIG_VFS_SUPPORT_DIR +static int vfs_semihost_mkdir(void* ctx, const char* path, mode_t mode) +{ + FAIL_IF_NO_DEBUGGER(); + + if (path == NULL) { + errno = ENOENT; + return -1; + } + + ESP_LOGV(TAG, "%s: '%s 0x%x'", __func__, path, mode); + return semihosting_mkdir(path, mode); +} + +static int vfs_semihost_rmdir(void* ctx, const char* path) +{ + FAIL_IF_NO_DEBUGGER(); + + if (path == NULL) { + errno = ENOENT; + return -1; + } + + ESP_LOGV(TAG, "%s: '%s'", __func__, path); + return semihosting_rmdir(path); +} + +static int vfs_semihost_access(void* ctx, const char* path, int mode) +{ + FAIL_IF_NO_DEBUGGER(); + + if (path == NULL) { + errno = ENOENT; + return -1; + } + + ESP_LOGV(TAG, "%s: '%s 0x%x'", __func__, path, mode); + return semihosting_access(path, mode); +} + +static int vfs_semihost_truncate(void* ctx, const char* path, off_t length) +{ + FAIL_IF_NO_DEBUGGER(); + + if (length < 0) { + errno = EINVAL; + return -1; + } + + if (path == NULL) { + errno = ENOENT; + return -1; + } + + ESP_LOGV(TAG, "%s: '%s after %ld bytes'", __func__, path, length); + return semihosting_truncate(path, length); +} + +static int vfs_semihost_utime(void* ctx, const char* path, const struct utimbuf *times) +{ + FAIL_IF_NO_DEBUGGER(); + + if (path == NULL || times == NULL) { + errno = ENOENT; + return -1; + } + + ESP_LOGV(TAG, "%s: '%s'", __func__, path); + return semihosting_utime(path, times); +} + +static int vfs_semihost_stat(void* ctx, const char *restrict path, struct stat *restrict statbuf) +{ + FAIL_IF_NO_DEBUGGER(); + + if (statbuf == NULL || path == NULL) { + errno = ENOENT; + return -1; + } + + ESP_LOGV(TAG, "%s: '%s'", __func__, path); + return semihosting_stat(path, statbuf); +} + +static int vfs_semihost_rename(void* ctx, const char *restrict old_name, const char *restrict new_name) +{ + FAIL_IF_NO_DEBUGGER(); + + if (old_name == NULL || new_name == NULL) { + errno = ENOENT; + return -1; + } + + ESP_LOGV(TAG, "%s: '%s -> %s'", __func__, old_name, new_name); + return semihosting_rename(old_name, new_name); +} + +static int vfs_semihost_link(void* ctx, const char *restrict path1, const char *restrict path2) +{ + FAIL_IF_NO_DEBUGGER(); + + if (path1 == NULL || path2 == NULL) { + errno = ENOENT; + return -1; + } + + ESP_LOGV(TAG, "%s: '%s <-> %s'", __func__, path1, path2); + return semihosting_link(path1, path2); +} + +static int vfs_semihost_unlink(void* ctx, const char *restrict path) +{ + FAIL_IF_NO_DEBUGGER(); + + if (path == NULL) { + errno = ENOENT; + return -1; + } + + ESP_LOGV(TAG, "%s: '%s'", __func__, path); + return semihosting_unlink(path); +} + +static DIR* vfs_semihost_opendir(void* ctx, const char *restrict path) +{ + if (!esp_cpu_dbgr_is_attached()) { + return NULL; + } + + if (path == NULL) { + errno = ENOENT; + return NULL; + } + + vfs_semihost_dir_t *semihost_dirp = (vfs_semihost_dir_t*)calloc(1, sizeof(vfs_semihost_dir_t)); + if (semihost_dirp == NULL) { + ESP_LOGE("Error", "Error on vfs_semihost_dir_t creation"); + errno = ENOMEM; + return NULL; + } + + strncpy(semihost_dirp->path, path, MIN(strlen(path), sizeof(semihost_dirp->path) - 1)); + ESP_LOGV(TAG, "%s: '%s'", __func__, path); + int ret_fd = semihosting_opendir(path, (int)&semihost_dirp->id); + if (ret_fd < 0) { + free(semihost_dirp); + return NULL; + } + return (DIR *)semihost_dirp; +} + +static int vfs_semihost_closedir(void* ctx, DIR* dirp) +{ + FAIL_IF_NO_DEBUGGER(); + + vfs_semihost_dir_t *semihost_dirp = (vfs_semihost_dir_t*)dirp; + if (semihost_dirp == NULL) { + errno = ENOENT; + return -1; + } + + ESP_LOGV(TAG, "%s: %s %ld", __func__, semihost_dirp->path, semihost_dirp->id); + int ret_fd = semihosting_closedir(semihost_dirp->id); + free(semihost_dirp); + return ret_fd; +} + +static long vfs_semihost_telldir(void* ctx, DIR* dirp) +{ + FAIL_IF_NO_DEBUGGER(); + + vfs_semihost_dir_t *semihost_dirp = (vfs_semihost_dir_t*)dirp; + if (semihost_dirp == NULL) { + errno = ENOENT; + return -1; + } + + ESP_LOGV(TAG, "%s: %s %ld", __func__, semihost_dirp->path, semihost_dirp->id); + return semihosting_telldir(semihost_dirp->id); +} + +static int vfs_semihost_readdir_r(void* ctx, DIR* dirp, struct dirent* entry, struct dirent** out_dirent) +{ + FAIL_IF_NO_DEBUGGER(); + + vfs_semihost_dir_t *semihost_dirp = (vfs_semihost_dir_t *)dirp; + if (semihost_dirp == NULL || entry == NULL || out_dirent == NULL) { + errno = ENOENT; + return -1; + } + + ESP_LOGV(TAG, "%s: %s %ld", __func__, semihost_dirp->path, semihost_dirp->id); + int ret_fd = semihosting_readdir((int)entry, semihost_dirp->id); + if (ret_fd < 0) { + if (errno == 0) { /* end of directory */ + *out_dirent = NULL; + return 0; + } + return errno; + } + *out_dirent = entry; + return 0; +} + +static struct dirent* vfs_semihost_readdir(void* ctx, DIR* dirp) +{ + if (!esp_cpu_dbgr_is_attached()) { + return NULL; + } + + vfs_semihost_dir_t *semihost_dirp = (vfs_semihost_dir_t *)dirp; + struct dirent *dir_ptr; + ESP_LOGV(TAG, "%s: %s %ld", __func__, semihost_dirp->path, semihost_dirp->id); + int ret = vfs_semihost_readdir_r(ctx, (DIR*)semihost_dirp, &semihost_dirp->e, &dir_ptr); + if (ret != 0) { + errno = ret; + return NULL; + } + return dir_ptr; +} + +static void vfs_semihost_seekdir(void* ctx, DIR* pdir, long offset) +{ + if (!esp_cpu_dbgr_is_attached()) { + return; + } + + vfs_semihost_dir_t *semihost_dirp = (vfs_semihost_dir_t *) pdir; + if (semihost_dirp != NULL) { + ESP_LOGV(TAG, "%s: %s %ld '%ld' bytes", __func__, semihost_dirp->path, semihost_dirp->id, offset); + semihosting_seekdir(semihost_dirp->id, offset); + } +} +#endif esp_err_t esp_vfs_semihost_register(const char* base_path) { assert(base_path); @@ -170,6 +430,25 @@ esp_err_t esp_vfs_semihost_register(const char* base_path) .close_p = &vfs_semihost_close, .read_p = &vfs_semihost_read, .lseek_p = &vfs_semihost_lseek, + .fsync_p = &vfs_semihost_fsync, + .fstat_p = &vfs_semihost_fstat, +#ifdef CONFIG_VFS_SUPPORT_DIR + .mkdir_p = &vfs_semihost_mkdir, + .rmdir_p = &vfs_semihost_rmdir, + .access_p = &vfs_semihost_access, + .truncate_p = &vfs_semihost_truncate, + .utime_p = &vfs_semihost_utime, + .stat_p = &vfs_semihost_stat, + .rename_p = &vfs_semihost_rename, + .link_p = &vfs_semihost_link, + .unlink_p = &vfs_semihost_unlink, + .opendir_p = &vfs_semihost_opendir, + .closedir_p = &vfs_semihost_closedir, + .telldir_p = &vfs_semihost_telldir, + .readdir_p = &vfs_semihost_readdir, + .readdir_r_p = &vfs_semihost_readdir_r, + .seekdir_p = &vfs_semihost_seekdir, +#endif }; ESP_LOGD(TAG, "Register semihosting driver '%s'", base_path); if (!esp_cpu_dbgr_is_attached()) { diff --git a/components/wifi_provisioning/include/wifi_provisioning/manager.h b/components/wifi_provisioning/include/wifi_provisioning/manager.h index e65ef3ea70..7d1f12f352 100644 --- a/components/wifi_provisioning/include/wifi_provisioning/manager.h +++ b/components/wifi_provisioning/include/wifi_provisioning/manager.h @@ -188,11 +188,13 @@ typedef struct { * These are same as the security modes provided by protocomm */ typedef enum wifi_prov_security { +#ifdef CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0 /** * No security (plain-text communication) */ WIFI_PROV_SECURITY_0 = 0, - +#endif +#ifdef CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1 /** * This secure communication mode consists of * X25519 key exchange @@ -200,16 +202,27 @@ typedef enum wifi_prov_security { * + AES-CTR encryption */ WIFI_PROV_SECURITY_1, - +#endif +#ifdef CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2 /** * This secure communication mode consists of * SRP6a based authentication and key exchange * + AES-GCM encryption/decryption */ WIFI_PROV_SECURITY_2 +#endif } wifi_prov_security_t; -typedef protocomm_security1_params_t wifi_prov_security1_params_t; +/** + * @brief Security 1 params structure + * This needs to be passed when using WIFI_PROV_SECURITY_1 + */ +typedef const char wifi_prov_security1_params_t; + +/** + * @brief Security 2 params structure + * This needs to be passed when using WIFI_PROV_SECURITY_2 + */ typedef protocomm_security2_params_t wifi_prov_security2_params_t; /** @@ -266,7 +279,6 @@ void wifi_prov_mgr_deinit(void); * - ESP_OK : Retrieved provision state successfully * - ESP_FAIL : Wi-Fi not initialized * - ESP_ERR_INVALID_ARG : Null argument supplied - * - ESP_ERR_INVALID_STATE : Manager not initialized */ esp_err_t wifi_prov_mgr_is_provisioned(bool *provisioned); @@ -301,6 +313,8 @@ esp_err_t wifi_prov_mgr_is_provisioned(bool *provisioned); * This pointer should hold the struct of type * wifi_prov_security1_params_t for protocomm security 1 * and wifi_prov_security2_params_t for protocomm security 2 respectively. + * This pointer and its contents should be valid till the provisioning service is + * running and has not been stopped or de-inited. * @param[in] service_name Unique name of the service. This translates to: * - Wi-Fi SSID when provisioning mode is softAP * - Device name when provisioning mode is BLE @@ -555,7 +569,8 @@ esp_err_t wifi_prov_mgr_reset_provisioning(void); /** * @brief Reset internal state machine and clear provisioned credentials. * - * This API can be used to restart provisioning in case invalid credentials are entered. + * This API should be used to restart provisioning ONLY in the case + * of provisioning failures without rebooting the device. * * @return * - ESP_OK : Reset provisioning state machine successfully @@ -564,6 +579,23 @@ esp_err_t wifi_prov_mgr_reset_provisioning(void); */ esp_err_t wifi_prov_mgr_reset_sm_state_on_failure(void); +/** + * @brief Reset internal state machine and clear provisioned credentials. + * + * This API can be used to restart provisioning ONLY in case the device is + * to be provisioned again for new credentials after a previous successful + * provisioning without rebooting the device. + * + * @note This API can be used only if provisioning auto-stop has been + * disabled using wifi_prov_mgr_disable_auto_stop() + * + * @return + * - ESP_OK : Reset provisioning state machine successfully + * - ESP_FAIL : Failed to reset provisioning state machine + * - ESP_ERR_INVALID_STATE : Manager not initialized + */ +esp_err_t wifi_prov_mgr_reset_sm_state_for_reprovision(void); + #ifdef __cplusplus } #endif diff --git a/components/wifi_provisioning/src/manager.c b/components/wifi_provisioning/src/manager.c index d75aa60325..27adb38141 100644 --- a/components/wifi_provisioning/src/manager.c +++ b/components/wifi_provisioning/src/manager.c @@ -246,6 +246,7 @@ static cJSON* wifi_prov_get_info_json(void) /* Version field */ cJSON_AddStringToObject(prov_info_json, "ver", prov_ctx->mgr_info.version); + cJSON_AddNumberToObject(prov_info_json, "sec_ver", prov_ctx->security); /* Capabilities field */ cJSON_AddItemToObject(prov_info_json, "cap", prov_capabilities); @@ -600,6 +601,12 @@ static bool wifi_prov_mgr_stop_service(bool blocking) /* Free proof of possession */ if (prov_ctx->protocomm_sec_params) { + if (prov_ctx->security == 1) { + // In case of security 1 we keep an internal copy of "pop". + // Hence free it at this point + uint8_t *pop = (uint8_t *)((protocomm_security1_params_t *) prov_ctx->protocomm_sec_params)->data; + free(pop); + } prov_ctx->protocomm_sec_params = NULL; } @@ -1112,11 +1119,6 @@ esp_err_t wifi_prov_mgr_is_provisioned(bool *provisioned) *provisioned = false; - if (!prov_ctx_lock) { - ESP_LOGE(TAG, "Provisioning manager not initialized"); - return ESP_ERR_INVALID_STATE; - } - /* Get Wi-Fi Station configuration */ wifi_config_t wifi_cfg; if (esp_wifi_get_config(WIFI_IF_STA, &wifi_cfg) != ESP_OK) { @@ -1349,6 +1351,7 @@ void wifi_prov_mgr_deinit(void) ESP_LOGD(TAG, "Manager already de-initialized"); RELEASE_LOCK(prov_ctx_lock); vSemaphoreDelete(prov_ctx_lock); + prov_ctx_lock = NULL; return; } @@ -1401,6 +1404,7 @@ void wifi_prov_mgr_deinit(void) } vSemaphoreDelete(prov_ctx_lock); + prov_ctx_lock = NULL; } esp_err_t wifi_prov_mgr_start_provisioning(wifi_prov_security_t security, const void *wifi_prov_sec_params, @@ -1477,20 +1481,38 @@ esp_err_t wifi_prov_mgr_start_provisioning(wifi_prov_security_t security, const goto err; } +#ifdef CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0 /* Initialize app data */ if (security == WIFI_PROV_SECURITY_0) { prov_ctx->mgr_info.capabilities.no_sec = true; - } else if (security == WIFI_PROV_SECURITY_1) { + } +#endif +#ifdef CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1 + if (security == WIFI_PROV_SECURITY_1) { if (wifi_prov_sec_params) { - prov_ctx->protocomm_sec_params = wifi_prov_sec_params; + static protocomm_security1_params_t sec1_params; + // Generate internal copy of "pop", that shall be freed at the end + char *pop = strdup(wifi_prov_sec_params); + if (pop == NULL) { + ESP_LOGE(TAG, "Failed to allocate memory for pop"); + ret = ESP_ERR_NO_MEM; + goto err; + } + sec1_params.data = (const uint8_t *)pop; + sec1_params.len = strlen(pop); + prov_ctx->protocomm_sec_params = (const void *) &sec1_params; } else { prov_ctx->mgr_info.capabilities.no_pop = true; } - } else if (security == WIFI_PROV_SECURITY_2) { + } +#endif +#ifdef CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2 + if (security == WIFI_PROV_SECURITY_2) { if (wifi_prov_sec_params) { prov_ctx->protocomm_sec_params = wifi_prov_sec_params; } } +#endif prov_ctx->security = security; @@ -1620,3 +1642,52 @@ exit: RELEASE_LOCK(prov_ctx_lock); return err; } + +esp_err_t wifi_prov_mgr_reset_sm_state_for_reprovision(void) +{ + if (!prov_ctx_lock) { + ESP_LOGE(TAG, "Provisioning manager not initialized"); + return ESP_ERR_INVALID_STATE; + } + + ACQUIRE_LOCK(prov_ctx_lock); + + esp_err_t ret = ESP_OK; + wifi_config_t wifi_cfg_empty = {0}; + uint8_t restore_wifi_flag = 0; + + if (!prov_ctx->mgr_info.capabilities.no_auto_stop) { + ESP_LOGE(TAG, "Execute wifi_prov_mgr_disable_auto_stop() before calling this API"); + ret = ESP_ERR_INVALID_STATE; + goto exit; + } + + ret = esp_wifi_set_storage(WIFI_STORAGE_RAM); + if (ret != ESP_OK) { + ESP_LOGE(TAG, "Failed to set Wi-Fi storage to RAM"); + goto exit; + } + restore_wifi_flag |= WIFI_PROV_STORAGE_BIT; + + ret = esp_wifi_set_config(WIFI_IF_STA, &wifi_cfg_empty); + if (ret != ESP_OK) { + ESP_LOGE(TAG, "Failed to set empty Wi-Fi credentials, 0x%x", ret); + goto exit; + } + + ret = esp_wifi_disconnect(); + if (ret != ESP_OK) { + ESP_LOGE(TAG, "Failed to disconnect wifi, 0x%x", ret); + goto exit; + } + + prov_ctx->prov_state = WIFI_PROV_STATE_STARTED; + execute_event_cb(WIFI_PROV_START, NULL, 0); + +exit: + if (restore_wifi_flag & WIFI_PROV_STORAGE_BIT) { + esp_wifi_set_storage(WIFI_STORAGE_FLASH); + } + RELEASE_LOCK(prov_ctx_lock); + return ret; +} diff --git a/components/wpa_supplicant/esp_supplicant/src/crypto/crypto_mbedtls-rsa.c b/components/wpa_supplicant/esp_supplicant/src/crypto/crypto_mbedtls-rsa.c index fd80e5b96a..450f78b8fe 100644 --- a/components/wpa_supplicant/esp_supplicant/src/crypto/crypto_mbedtls-rsa.c +++ b/components/wpa_supplicant/esp_supplicant/src/crypto/crypto_mbedtls-rsa.c @@ -339,8 +339,11 @@ int crypto_public_key_decrypt_pkcs1(struct crypto_public_key *key, size_t len; u8 *pos; mbedtls_pk_context *pkey = (mbedtls_pk_context *)key; + len = mbedtls_pk_rsa(*pkey)->MBEDTLS_PRIVATE(len); + if (len != crypt_len) { + return -1; + } - len = *plain_len; if (mbedtls_rsa_public(mbedtls_pk_rsa(*pkey), crypt, plain) < 0) return -1; diff --git a/components/wpa_supplicant/esp_supplicant/src/crypto/tls_mbedtls.c b/components/wpa_supplicant/esp_supplicant/src/crypto/tls_mbedtls.c index 575a59e458..6c518eec22 100644 --- a/components/wpa_supplicant/esp_supplicant/src/crypto/tls_mbedtls.c +++ b/components/wpa_supplicant/esp_supplicant/src/crypto/tls_mbedtls.c @@ -196,12 +196,18 @@ static int set_ca_cert(tls_context_t *tls, const unsigned char *cacert, size_t c } #ifdef CONFIG_SUITEB192 -static int tls_sig_hashes_for_suiteb[] = { +static uint16_t tls_sig_algs_for_suiteb[] = { #if defined(MBEDTLS_SHA512_C) - MBEDTLS_MD_SHA512, - MBEDTLS_MD_SHA384, +#if defined(MBEDTLS_ECDSA_C) + MBEDTLS_SSL_TLS12_SIG_AND_HASH_ALG( MBEDTLS_SSL_SIG_ECDSA, MBEDTLS_SSL_HASH_SHA512 ), + MBEDTLS_SSL_TLS12_SIG_AND_HASH_ALG( MBEDTLS_SSL_SIG_ECDSA, MBEDTLS_SSL_HASH_SHA384 ), #endif - MBEDTLS_MD_NONE +#if defined(MBEDTLS_RSA_C) + MBEDTLS_SSL_TLS12_SIG_AND_HASH_ALG( MBEDTLS_SSL_SIG_RSA, MBEDTLS_SSL_HASH_SHA512 ), + MBEDTLS_SSL_TLS12_SIG_AND_HASH_ALG( MBEDTLS_SSL_SIG_RSA, MBEDTLS_SSL_HASH_SHA384 ), +#endif +#endif /* MBEDTLS_SHA512_C */ + MBEDTLS_TLS_SIG_NONE }; const mbedtls_x509_crt_profile suiteb_mbedtls_x509_crt_profile = @@ -220,23 +226,40 @@ static void tls_set_suiteb_config(tls_context_t *tls) { const mbedtls_x509_crt_profile *crt_profile = &suiteb_mbedtls_x509_crt_profile; mbedtls_ssl_conf_cert_profile(&tls->conf, crt_profile); - mbedtls_ssl_conf_sig_hashes(&tls->conf, tls_sig_hashes_for_suiteb); + mbedtls_ssl_conf_sig_algs(&tls->conf, tls_sig_algs_for_suiteb); } #endif -static int tls_sig_hashes_for_eap[] = { +static uint16_t tls_sig_algs_for_eap[] = { #if defined(MBEDTLS_SHA512_C) - MBEDTLS_MD_SHA512, - MBEDTLS_MD_SHA384, +#if defined(MBEDTLS_ECDSA_C) + MBEDTLS_SSL_TLS12_SIG_AND_HASH_ALG( MBEDTLS_SSL_SIG_ECDSA, MBEDTLS_SSL_HASH_SHA512 ), + MBEDTLS_SSL_TLS12_SIG_AND_HASH_ALG( MBEDTLS_SSL_SIG_ECDSA, MBEDTLS_SSL_HASH_SHA384 ), #endif +#if defined(MBEDTLS_RSA_C) + MBEDTLS_SSL_TLS12_SIG_AND_HASH_ALG( MBEDTLS_SSL_SIG_RSA, MBEDTLS_SSL_HASH_SHA512 ), + MBEDTLS_SSL_TLS12_SIG_AND_HASH_ALG( MBEDTLS_SSL_SIG_RSA, MBEDTLS_SSL_HASH_SHA384 ), +#endif +#endif /* MBEDTLS_SHA512_C */ #if defined(MBEDTLS_SHA256_C) - MBEDTLS_MD_SHA256, - MBEDTLS_MD_SHA224, +#if defined(MBEDTLS_ECDSA_C) + MBEDTLS_SSL_TLS12_SIG_AND_HASH_ALG( MBEDTLS_SSL_SIG_ECDSA, MBEDTLS_SSL_HASH_SHA256 ), + MBEDTLS_SSL_TLS12_SIG_AND_HASH_ALG( MBEDTLS_SSL_SIG_ECDSA, MBEDTLS_SSL_HASH_SHA224 ), #endif +#if defined(MBEDTLS_RSA_C) + MBEDTLS_SSL_TLS12_SIG_AND_HASH_ALG( MBEDTLS_SSL_SIG_RSA, MBEDTLS_SSL_HASH_SHA256 ), + MBEDTLS_SSL_TLS12_SIG_AND_HASH_ALG( MBEDTLS_SSL_SIG_RSA, MBEDTLS_SSL_HASH_SHA224 ), +#endif +#endif /* MBEDTLS_SHA256_C */ #if defined(MBEDTLS_SHA1_C) - MBEDTLS_MD_SHA1, +#if defined(MBEDTLS_ECDSA_C) + MBEDTLS_SSL_TLS12_SIG_AND_HASH_ALG( MBEDTLS_SSL_SIG_ECDSA, MBEDTLS_SSL_HASH_SHA1 ), #endif - MBEDTLS_MD_NONE +#if defined(MBEDTLS_RSA_C) + MBEDTLS_SSL_TLS12_SIG_AND_HASH_ALG( MBEDTLS_SSL_SIG_RSA, MBEDTLS_SSL_HASH_SHA1 ), +#endif +#endif /* MBEDTLS_SHA1_C */ + MBEDTLS_TLS_SIG_NONE }; const mbedtls_x509_crt_profile eap_mbedtls_x509_crt_profile = @@ -262,7 +285,7 @@ static void tls_enable_sha1_config(tls_context_t *tls) { const mbedtls_x509_crt_profile *crt_profile = &eap_mbedtls_x509_crt_profile; mbedtls_ssl_conf_cert_profile(&tls->conf, crt_profile); - mbedtls_ssl_conf_sig_hashes(&tls->conf, tls_sig_hashes_for_eap); + mbedtls_ssl_conf_sig_algs(&tls->conf, tls_sig_algs_for_eap); } static const int eap_ciphersuite_preference[] = @@ -390,23 +413,6 @@ static const int eap_ciphersuite_preference[] = #if defined(MBEDTLS_CCM_C) MBEDTLS_TLS_PSK_WITH_AES_128_CCM_8, #endif -#endif - -#if defined(MBEDTLS_DES_C) - /* 3DES suites */ - MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA, - MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA, - MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA, - MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA, - MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA, -#endif -#if defined(MBEDTLS_ARC4_C) - /* RC4 suites */ - MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA, - MBEDTLS_TLS_RSA_WITH_RC4_128_SHA, - MBEDTLS_TLS_RSA_WITH_RC4_128_MD5, - MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA, - MBEDTLS_TLS_PSK_WITH_RC4_128_SHA, #endif 0 }; diff --git a/components/wpa_supplicant/esp_supplicant/src/esp_wps.c b/components/wpa_supplicant/esp_supplicant/src/esp_wps.c index d70717ac41..90b1bb2144 100644 --- a/components/wpa_supplicant/esp_supplicant/src/esp_wps.c +++ b/components/wpa_supplicant/esp_supplicant/src/esp_wps.c @@ -29,19 +29,7 @@ #include "eap_common/eap_wsc_common.h" #include "esp_wpas_glue.h" -#if CONFIG_IDF_TARGET_ESP32 -const char *wps_model_number = "ESP32"; -#elif CONFIG_IDF_TARGET_ESP32S2 -const char *wps_model_number = "ESP32S2"; -#elif CONFIG_IDF_TARGET_ESP32S3 -const char *wps_model_number = "ESP32S3"; -#elif CONFIG_IDF_TARGET_ESP32C3 -const char *wps_model_number = "ESP32C3"; -#elif CONFIG_IDF_TARGET_ESP32C2 -const char *wps_model_number = "ESP32C2"; -#elif CONFIG_IDF_TARGET_ESP32H2 -const char *wps_model_number = "ESP32H2"; -#endif +const char *wps_model_number = CONFIG_IDF_TARGET; void *s_wps_api_lock = NULL; /* Used in WPS public API only, never be freed */ void *s_wps_api_sem = NULL; /* Sync semaphore used between WPS publi API caller task and WPS task */ @@ -397,6 +385,7 @@ wps_parse_scan_result(struct wps_scan_ie *scan) for (count = 0; count < WPS_MAX_DIS_AP_NUM; count++) { if (os_memcmp(sm->dis_ap_list[count].bssid, scan->bssid, ETH_ALEN) == 0) { wpa_printf(MSG_INFO, "discard ap bssid "MACSTR, MAC2STR(scan->bssid)); + wpabuf_free(buf); return false; } } @@ -404,6 +393,9 @@ wps_parse_scan_result(struct wps_scan_ie *scan) if (ap_found || sm->ignore_sel_reg) { wpabuf_free(buf); + if (scan->ssid[1] > SSID_MAX_LEN) { + return false; + } esp_wifi_enable_sta_privacy_internal(); os_memset(sm->ssid[0], 0, SSID_MAX_LEN); os_memcpy(sm->ssid[0], (char *)&scan->ssid[2], (int)scan->ssid[1]); @@ -1400,6 +1392,7 @@ wifi_station_wps_init(void) sm = gWpsSm; esp_wifi_get_macaddr_internal(WIFI_IF_STA, sm->ownaddr); + os_memcpy(gWpaSm.own_addr, sm->ownaddr, ETH_ALEN); sm->identity_len = WSC_ID_ENROLLEE_LEN; os_memcpy(sm->identity, WSC_ID_ENROLLEE, sm->identity_len); @@ -1572,6 +1565,7 @@ wifi_wps_scan_done(void *arg, STATUS status) os_memcpy(wifi_config.sta.bssid, sm->bssid, ETH_ALEN); os_memcpy(wifi_config.sta.ssid, (char *)sm->ssid[0], sm->ssid_len[0]); wifi_config.sta.bssid_set = 1; + wifi_config.sta.channel = sm->channel; wpa_printf(MSG_INFO, "WPS: connecting to %s, bssid=" MACSTR, (char *)sm->ssid[0], MAC2STR(wifi_config.sta.bssid)); esp_wifi_set_config(0, &wifi_config); @@ -1910,8 +1904,8 @@ int esp_wifi_wps_disable(void) wpa_printf(MSG_ERROR, "wps disable: failed to disable wps, ret=%d", ret); } - /* Only disconnect in case of WPS pending */ - if (wps_status == WPS_STATUS_PENDING) { + /* Only disconnect in case of WPS pending/done */ + if ((wps_status == WPS_STATUS_PENDING) || (wps_status == WPS_STATUS_SUCCESS)) { esp_wifi_disconnect(); } esp_wifi_set_wps_start_flag_internal(false); diff --git a/components/wpa_supplicant/port/eloop.c b/components/wpa_supplicant/port/eloop.c index 92aaa02fb2..37ce1a5c4a 100644 --- a/components/wpa_supplicant/port/eloop.c +++ b/components/wpa_supplicant/port/eloop.c @@ -366,5 +366,6 @@ void eloop_destroy(void) eloop_data_lock = NULL; } os_timer_disarm(&eloop.eloop_timer); + os_timer_done(&eloop.eloop_timer); os_memset(&eloop, 0, sizeof(eloop)); } diff --git a/components/wpa_supplicant/src/rsn_supp/wpa.c b/components/wpa_supplicant/src/rsn_supp/wpa.c index b30851812a..ffbb8c33df 100644 --- a/components/wpa_supplicant/src/rsn_supp/wpa.c +++ b/components/wpa_supplicant/src/rsn_supp/wpa.c @@ -1625,20 +1625,7 @@ static void wpa_supplicant_process_1_of_2(struct wpa_sm *sm, wpa_sm_set_seq(sm, key, 0); sm->key_info=key_info; - if (wpa_supplicant_send_2_of_2(sm, key, ver, key_info)) - goto failed; - - return; - -failed: - wpa_sm_deauthenticate(sm, WLAN_REASON_UNSPECIFIED); -} - -static int wpa_supplicant_send_2_of_2_txcallback(struct wpa_sm *sm) -{ - u16 key_info=sm->key_info; - u16 rekey= (WPA_SM_STATE(sm) == WPA_COMPLETED); - + /*install gtk before send 2 of 2*/ if((sm->gd).gtk_len) { if (wpa_supplicant_install_gtk(sm, &(sm->gd))) goto failed; @@ -1646,7 +1633,10 @@ static int wpa_supplicant_send_2_of_2_txcallback(struct wpa_sm *sm) goto failed; } - if (rekey) { + if (wpa_supplicant_send_2_of_2(sm, key, ver, key_info)) + goto failed; + + if ((WPA_SM_STATE(sm) == WPA_COMPLETED)) { #ifdef MSG_PRINT wpa_printf(MSG_DEBUG, "WPA: Group rekeying " "completed with " MACSTR " [GTK=%s]", @@ -1654,13 +1644,15 @@ static int wpa_supplicant_send_2_of_2_txcallback(struct wpa_sm *sm) #endif wpa_sm_cancel_auth_timeout(sm); wpa_sm_set_state(WPA_COMPLETED); - } else + } else { wpa_supplicant_key_neg_complete(sm, sm->bssid, - key_info &WPA_KEY_INFO_SECURE); - return 0; + sm->key_info &WPA_KEY_INFO_SECURE); + } + + return; failed: - return WLAN_REASON_UNSPECIFIED; + wpa_sm_deauthenticate(sm, WLAN_REASON_UNSPECIFIED); } static int wpa_supplicant_verify_eapol_key_mic(struct wpa_sm *sm, @@ -2606,7 +2598,6 @@ void eapol_txcb(void *eb) case WPA_GROUP_HANDSHAKE: if (sm->txcb_flags & WPA_GROUP_HANDSHAKE_BIT) { sm->txcb_flags &= ~WPA_GROUP_HANDSHAKE_BIT; - isdeauth = wpa_supplicant_send_2_of_2_txcallback(sm); } else { wpa_printf(MSG_DEBUG, "2/2 txcb, flags=%d\n", sm->txcb_flags); } diff --git a/components/wpa_supplicant/src/utils/includes.h b/components/wpa_supplicant/src/utils/includes.h index 45a2da95ce..f9c4c41599 100644 --- a/components/wpa_supplicant/src/utils/includes.h +++ b/components/wpa_supplicant/src/utils/includes.h @@ -71,6 +71,8 @@ #include "esp32c2/rom/ets_sys.h" #elif CONFIG_IDF_TARGET_ESP32H2 #include "esp32h2/rom/ets_sys.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/ets_sys.h" #endif #endif /* !__ets__ */ diff --git a/docs/_static/ESP32-S3-DevKitC-1_v2-SystemBlock.png b/docs/_static/ESP32-S3-DevKitC-1_v2-SystemBlock.png index 7fcd9c6766..58ab4f25a8 100644 Binary files a/docs/_static/ESP32-S3-DevKitC-1_v2-SystemBlock.png and b/docs/_static/ESP32-S3-DevKitC-1_v2-SystemBlock.png differ diff --git a/docs/_static/ESP32-S3-DevKitC-1_v2-annotated-photo.png b/docs/_static/ESP32-S3-DevKitC-1_v2-annotated-photo.png index da3e27a714..ce2b1ff615 100644 Binary files a/docs/_static/ESP32-S3-DevKitC-1_v2-annotated-photo.png and b/docs/_static/ESP32-S3-DevKitC-1_v2-annotated-photo.png differ diff --git a/docs/_static/ESP32_DevKitM-1_pinlayout.png b/docs/_static/ESP32_DevKitM-1_pinlayout.png new file mode 100644 index 0000000000..359251737f Binary files /dev/null and b/docs/_static/ESP32_DevKitM-1_pinlayout.png differ diff --git a/docs/_static/contribute.png b/docs/_static/contribute.png deleted file mode 100644 index 1984736545..0000000000 Binary files a/docs/_static/contribute.png and /dev/null differ diff --git a/docs/_static/diagrams/i2s/i2s_state_machine.png b/docs/_static/diagrams/i2s/i2s_state_machine.png index 8c56ca9063..620206077f 100644 Binary files a/docs/_static/diagrams/i2s/i2s_state_machine.png and b/docs/_static/diagrams/i2s/i2s_state_machine.png differ diff --git a/docs/_static/esp32-pico-kit-v4-pinout.png b/docs/_static/esp32-pico-kit-v4-pinout.png new file mode 100644 index 0000000000..810c08ea9e Binary files /dev/null and b/docs/_static/esp32-pico-kit-v4-pinout.png differ diff --git a/docs/_static/esp32-s2-devkitc-1-v1-block-diags.png b/docs/_static/esp32-s2-devkitc-1-v1-block-diags.png index 7184d16e6e..a19c87eddc 100644 Binary files a/docs/_static/esp32-s2-devkitc-1-v1-block-diags.png and b/docs/_static/esp32-s2-devkitc-1-v1-block-diags.png differ diff --git a/docs/_static/esp32-s2-devkitc-1-v1-pinout.png b/docs/_static/esp32-s2-devkitc-1-v1-pinout.png index c8ff9231a1..0bece12884 100644 Binary files a/docs/_static/esp32-s2-devkitc-1-v1-pinout.png and b/docs/_static/esp32-s2-devkitc-1-v1-pinout.png differ diff --git a/docs/_static/esp32-s2-devkitm-1-v1-block-diagram.png b/docs/_static/esp32-s2-devkitm-1-v1-block-diagram.png index 8219120531..5cdeade382 100644 Binary files a/docs/_static/esp32-s2-devkitm-1-v1-block-diagram.png and b/docs/_static/esp32-s2-devkitm-1-v1-block-diagram.png differ diff --git a/docs/_static/hw-reference.png b/docs/_static/hw-reference.png deleted file mode 100644 index ec31ab52b9..0000000000 Binary files a/docs/_static/hw-reference.png and /dev/null differ diff --git a/docs/_static/resources.png b/docs/_static/resources.png deleted file mode 100644 index 8989b62987..0000000000 Binary files a/docs/_static/resources.png and /dev/null differ diff --git a/docs/_static/touch_pad-measurement-parameters-version2.png b/docs/_static/touch_pad-measurement-parameters-version2.png new file mode 100644 index 0000000000..b138b0d4b5 Binary files /dev/null and b/docs/_static/touch_pad-measurement-parameters-version2.png differ diff --git a/docs/conf_common.py b/docs/conf_common.py index a752816949..a713c45923 100644 --- a/docs/conf_common.py +++ b/docs/conf_common.py @@ -20,7 +20,6 @@ if os.environ.get('IDF_PATH') is None: raise RuntimeError('IDF_PATH should be set, run export.sh before building docs') BT_DOCS = ['api-guides/blufi.rst', - 'api-guides/esp-ble-mesh/**', 'api-reference/bluetooth/bt_le.rst', 'api-reference/bluetooth/esp_bt_defs.rst', 'api-reference/bluetooth/esp_bt_device.rst', @@ -32,9 +31,16 @@ BT_DOCS = ['api-guides/blufi.rst', 'api-reference/bluetooth/esp_gatts.rst', 'api-reference/bluetooth/esp_gattc.rst', 'api-reference/bluetooth/esp_blufi.rst', - 'api-reference/bluetooth/esp-ble-mesh.rst', 'api-reference/bluetooth/index.rst', - 'api-reference/bluetooth/nimble/index.rst'] + 'api-reference/bluetooth/nimble/index.rst', + 'migration-guides/release-5.x/bluetooth-low-energy.rst'] + +BLE_MESH_DOCS = ['api-guides/esp-ble-mesh/ble-mesh-index.rst', + 'api-guides/esp-ble-mesh/ble-mesh-feature-list.rst', + 'api-guides/esp-ble-mesh/ble-mesh-terminology.rst', + 'api-guides/esp-ble-mesh/ble-mesh-architecture.rst', + 'api-guides/esp-ble-mesh/ble-mesh-faq.rst', + 'api-reference/bluetooth/esp-ble-mesh.rst'] CLASSIC_BT_DOCS = ['api-reference/bluetooth/classic_bt.rst', 'api-reference/bluetooth/esp_a2dp.rst', @@ -143,8 +149,9 @@ ESP32C3_DOCS = ['hw-reference/esp32c3/**', # format: {tag needed to include: documents to included}, tags are parsed from sdkconfig and peripheral_caps.h headers conditional_include_dict = {'SOC_BT_SUPPORTED':BT_DOCS, + 'SOC_BLE_MESH_SUPPORTED':BLE_MESH_DOCS, 'SOC_WIFI_SUPPORTED':WIFI_DOCS, - 'SOC_CLASSIC_BT_SUPPORTED':CLASSIC_BT_DOCS, + 'SOC_BT_CLASSIC_SUPPORTED':CLASSIC_BT_DOCS, 'SOC_SUPPORT_COEXISTENCE':COEXISTENCE_DOCS, 'SOC_SDMMC_HOST_SUPPORTED':SDMMC_DOCS, 'SOC_SDIO_SLAVE_SUPPORTED':SDIO_SLAVE_DOCS, @@ -183,7 +190,6 @@ extensions += ['sphinx_copybutton', # connected to another extension 'esp_docs.idf_extensions.build_system', 'esp_docs.idf_extensions.esp_err_definitions', - 'esp_docs.idf_extensions.gen_toolchain_links', 'esp_docs.idf_extensions.gen_defines', 'esp_docs.idf_extensions.gen_version_specific_includes', 'esp_docs.idf_extensions.kconfig_reference', @@ -221,9 +227,7 @@ linkcheck_exclude_documents = ['index', # several false positives due to the wa linkcheck_ignore = ['https://webhome.phy.duke.edu/~rgb/General/dieharder.php', # Certificate error - 'https://dl.espressif.com/dl/esp32s3_rom.elf', # Not published 'https://docs.espressif.com/projects/esptool/en/latest/esp32c2/espefuse/index.html', # Not published - 'https://www.espressif.com/sites/default/files/documentation/esp32-c2_datasheet_en.pdf', # Not published ] diff --git a/docs/docs_not_updated/esp32c2.txt b/docs/docs_not_updated/esp32c2.txt index 3df61368f7..e69de29bb2 100644 --- a/docs/docs_not_updated/esp32c2.txt +++ b/docs/docs_not_updated/esp32c2.txt @@ -1,45 +0,0 @@ -api-guides/blufi -api-guides/esp-ble-mesh/ble-mesh-index -api-guides/esp-ble-mesh/ble-mesh-feature-list -api-guides/esp-ble-mesh/ble-mesh-terminology -api-guides/esp-ble-mesh/ble-mesh-architecture -api-guides/esp-ble-mesh/ble-mesh-faq -api-reference/storage/vfs -api-reference/storage/spiffs -api-reference/storage/wear-levelling -api-reference/storage/fatfs -api-reference/storage/nvs_partition_gen -api-reference/storage/spi_flash_concurrency -api-reference/storage/spi_flash -api-reference/storage/spi_flash_override_driver -api-reference/storage/nvs_flash -api-reference/storage/sdmmc -api-reference/storage/mass_mfg -api-reference/storage/index -api-reference/system/sleep_modes -api-reference/system/power_management -api-reference/system/wdts -api-reference/system/inc/power_management_esp32s2_and_later -api-reference/bluetooth/esp_spp -api-reference/bluetooth/esp_avrc -api-reference/bluetooth/controller_vhci -api-reference/bluetooth/esp_bt_defs -api-reference/bluetooth/esp_hf_ag -api-reference/bluetooth/esp_bt_main -api-reference/bluetooth/esp_bt_device -api-reference/bluetooth/esp_gatts -api-reference/bluetooth/esp_gattc -api-reference/bluetooth/bt_common -api-reference/bluetooth/nimble/index -api-reference/bluetooth/esp_hf_client -api-reference/bluetooth/esp_a2dp -api-reference/bluetooth/esp_blufi -api-reference/bluetooth/bt_le -api-reference/bluetooth/esp_hf_defs -api-reference/bluetooth/esp_hidd -api-reference/bluetooth/esp_gap_bt -api-reference/bluetooth/esp_gatt_defs -api-reference/bluetooth/esp-ble-mesh -api-reference/bluetooth/index -api-reference/bluetooth/esp_gap_ble -api-reference/bluetooth/classic_bt diff --git a/docs/doxygen/Doxyfile b/docs/doxygen/Doxyfile index 56d0cb7f7e..d8ebc4ab5e 100644 --- a/docs/doxygen/Doxyfile +++ b/docs/doxygen/Doxyfile @@ -80,12 +80,16 @@ INPUT = \ $(PROJECT_PATH)/components/driver/include/driver/touch_sensor_common.h \ $(PROJECT_PATH)/components/driver/include/driver/twai.h \ $(PROJECT_PATH)/components/driver/include/driver/uart.h \ + $(PROJECT_PATH)/components/driver/test/esp_serial_slave_link/include/esp_serial_slave_link/essl.h \ + $(PROJECT_PATH)/components/driver/test/esp_serial_slave_link/include/esp_serial_slave_link/essl_sdio.h \ + $(PROJECT_PATH)/components/driver/test/esp_serial_slave_link/include/esp_serial_slave_link/essl_spi.h \ $(PROJECT_PATH)/components/efuse/$(IDF_TARGET)/include/esp_efuse_chip.h \ $(PROJECT_PATH)/components/efuse/include/esp_efuse.h \ $(PROJECT_PATH)/components/esp_adc/include/esp_adc/adc_cali_scheme.h \ $(PROJECT_PATH)/components/esp_adc/include/esp_adc/adc_cali.h \ $(PROJECT_PATH)/components/esp_adc/include/esp_adc/adc_continuous.h \ $(PROJECT_PATH)/components/esp_adc/include/esp_adc/adc_oneshot.h \ + $(PROJECT_PATH)/components/esp_app_format/include/esp_app_desc.h \ $(PROJECT_PATH)/components/esp_common/include/esp_check.h \ $(PROJECT_PATH)/components/esp_common/include/esp_err.h \ $(PROJECT_PATH)/components/esp_common/include/esp_idf_version.h \ @@ -126,9 +130,6 @@ INPUT = \ $(PROJECT_PATH)/components/esp_pm/include/esp_pm.h \ $(PROJECT_PATH)/components/esp_ringbuf/include/freertos/ringbuf.h \ $(PROJECT_PATH)/components/esp_rom/include/esp_rom_sys.h \ - $(PROJECT_PATH)/components/esp_serial_slave_link/include/esp_serial_slave_link/essl.h \ - $(PROJECT_PATH)/components/esp_serial_slave_link/include/esp_serial_slave_link/essl_sdio.h \ - $(PROJECT_PATH)/components/esp_serial_slave_link/include/esp_serial_slave_link/essl_spi.h \ $(PROJECT_PATH)/components/esp_system/include/esp_expression_with_stack.h \ $(PROJECT_PATH)/components/esp_system/include/esp_freertos_hooks.h \ $(PROJECT_PATH)/components/esp_system/include/esp_system.h \ diff --git a/docs/doxygen/Doxyfile_esp32s2 b/docs/doxygen/Doxyfile_esp32s2 index f74884ca20..0aa2a6e963 100644 --- a/docs/doxygen/Doxyfile_esp32s2 +++ b/docs/doxygen/Doxyfile_esp32s2 @@ -25,6 +25,8 @@ INPUT += \ $(PROJECT_PATH)/components/touch_element/include/touch_element/touch_slider.h \ $(PROJECT_PATH)/components/ulp/ulp_common/include/$(IDF_TARGET)/ulp_common_defs.h \ $(PROJECT_PATH)/components/ulp/ulp_fsm/include/$(IDF_TARGET)/ulp.h \ + $(PROJECT_PATH)/components/ulp/ulp_riscv/include/ulp_riscv_lock.h \ + $(PROJECT_PATH)/components/ulp/ulp_riscv/shared/include/ulp_riscv_lock_shared.h \ $(PROJECT_PATH)/components/usb/include/usb/usb_helpers.h \ $(PROJECT_PATH)/components/usb/include/usb/usb_host.h \ $(PROJECT_PATH)/components/usb/include/usb/usb_types_ch9.h \ diff --git a/docs/doxygen/Doxyfile_esp32s3 b/docs/doxygen/Doxyfile_esp32s3 index 4c247aaffa..1f6738be6d 100644 --- a/docs/doxygen/Doxyfile_esp32s3 +++ b/docs/doxygen/Doxyfile_esp32s3 @@ -31,6 +31,8 @@ INPUT += \ $(PROJECT_PATH)/components/soc/$(IDF_TARGET)/include/soc/touch_sensor_channel.h \ $(PROJECT_PATH)/components/ulp/ulp_common/include/$(IDF_TARGET)/ulp_common_defs.h \ $(PROJECT_PATH)/components/ulp/ulp_fsm/include/$(IDF_TARGET)/ulp.h \ + $(PROJECT_PATH)/components/ulp/ulp_riscv/include/ulp_riscv_lock.h \ + $(PROJECT_PATH)/components/ulp/ulp_riscv/shared/include/ulp_riscv_lock_shared.h \ $(PROJECT_PATH)/components/usb/include/usb/usb_helpers.h \ $(PROJECT_PATH)/components/usb/include/usb/usb_host.h \ $(PROJECT_PATH)/components/usb/include/usb/usb_types_ch9.h \ diff --git a/docs/en/COPYRIGHT.rst b/docs/en/COPYRIGHT.rst index 1ce90ddd22..329d295bbc 100644 --- a/docs/en/COPYRIGHT.rst +++ b/docs/en/COPYRIGHT.rst @@ -55,18 +55,12 @@ These third party libraries can be included into the application (firmware) prod * `mynewt-nimble`_ Apache Mynewt NimBLE, Copyright 2015-2018, The Apache Software Foundation, is licensed under Apache License 2.0 as described in :component_file:`LICENSE file`. -* `cryptoauthlib`_ Microchip CryptoAuthentication Library - Copyright (c) 2015 - 2018 Microchip Technology Inc, is licensed under common Microchip software License as described in :example_file:`LICENSE file ` - * `TLSF allocator ` Two Level Segregated Fit memory allocator, Copyright (c) 2006-2016, Matthew Conte, and licensed under the BSD 3-clause license. -* `qrcode`_ QR Code generator library Copyright (c) Project Nayuki, is licensed under MIT license. - * :component:`openthread`, Copyright (c) The OpenThread Authors, is licensed under BSD License as described in :component_file:`LICENSE file`. * :component_file:`UBSAN runtime ` — Copyright (c) 2016, Linaro Limited and JiÅ™Ă­ ZĂ¡revĂºcky, licensed under the BSD 2-clause license. -* `freemodbus`_ Copyright (c) 2006-2013 Christian Walter, Armink and licensed under the BSD license. - * :component:`HTTP Parser ` Based on src/http/ngx_http_parse.c from NGINX copyright Igor Sysoev. Additional changes are licensed under the same terms as NGINX and Joyent, Inc. and other Node contributors. For details please check :component_file:`LICENSE file`. * `SEGGER SystemView`_ target-side library, Copyright (c) 2015-2017 SEGGER Microcontroller GmbH & Co. KG, is licensed under BSD 3-clause license. @@ -167,7 +161,4 @@ Copyright (C) 2011, ChaN, all right reserved. .. _ESP-IDF Programming Guide: https://docs.espressif.com/projects/esp-idf/en/latest/ .. _sphinx_idf_theme: https://github.com/espressif/sphinx_idf_theme .. _sphinx_rtd_theme: https://github.com/readthedocs/sphinx_rtd_theme -.. _cryptoauthlib: https://github.com/MicrochipTech/cryptoauthlib -.. _qrcode: https://github.com/nayuki/QR-Code-generator -.. _freemodbus: https://github.com/armink/FreeModbus_Slave-Master-RTT-STM32 .. _SEGGER SystemView: https://www.segger.com/downloads/systemview/ diff --git a/docs/en/api-guides/bootloader.rst b/docs/en/api-guides/bootloader.rst index ede6b483ed..2715e5d6d7 100644 --- a/docs/en/api-guides/bootloader.rst +++ b/docs/en/api-guides/bootloader.rst @@ -14,7 +14,7 @@ The ESP-IDF Software Bootloader performs the following functions: Bootloader is located at the address {IDF_TARGET_BOOTLOADER_OFFSET} in the flash. -For a full description of the startup process including the the ESP-IDF bootloader, see :doc:`startup`. +For a full description of the startup process including the ESP-IDF bootloader, see :doc:`startup`. .. _bootloader-compatibility: diff --git a/docs/en/api-guides/build-system.rst b/docs/en/api-guides/build-system.rst index 1a83795142..c7d83fd760 100644 --- a/docs/en/api-guides/build-system.rst +++ b/docs/en/api-guides/build-system.rst @@ -80,7 +80,7 @@ If using CMake with ``ninja`` or ``make``, there are also targets for more of th .. _flash-with-ninja-or-make: -Flashing with ninja or make +Flashing with Ninja or Make ^^^^^^^^^^^^^^^^^^^^^^^^^^^ It's possible to build and flash directly from ninja or make by running a target like:: @@ -129,7 +129,7 @@ If using an IDE with CMake, setting the ``PYTHON`` value as a CMake cache overri To manage the Python version more generally via the command line, check out the tools pyenv_ or virtualenv_. These let you change the default Python version. -Possible issues +Possible Issues ^^^^^^^^^^^^^^^^^^^^^ The user of ``idf.py`` may sometimes experience ``ImportError`` described below. @@ -178,9 +178,9 @@ This example "myProject" contains the following elements: - "sdkconfig" project configuration file. This file is created/updated when ``idf.py menuconfig`` runs, and holds configuration for all of the components in the project (including ESP-IDF itself). The "sdkconfig" file may or may not be added to the source control system of the project. -- Optional "components" directory contains components that are part of the project. A project does not have to contain custom components of this kind, but it can be useful for structuring reusable code or including third party components that aren't part of ESP-IDF. Alternatively, ``EXTRA_COMPONENT_DIRS`` can be set in the top-level CMakeLists.txt to look for components in other places. See the :ref:`renaming main ` section for more info. If you have a lot of source files in your project, we recommend grouping most into components instead of putting them all in "main". +- Optional "components" directory contains components that are part of the project. A project does not have to contain custom components of this kind, but it can be useful for structuring reusable code or including third party components that aren't part of ESP-IDF. Alternatively, ``EXTRA_COMPONENT_DIRS`` can be set in the top-level CMakeLists.txt to look for components in other places. -- "main" directory is a special component that contains source code for the project itself. "main" is a default name, the CMake variable ``COMPONENT_DIRS`` includes this component but you can modify this variable. +- "main" directory is a special component that contains source code for the project itself. "main" is a default name, the CMake variable ``COMPONENT_DIRS`` includes this component but you can modify this variable. See the :ref:`renaming main ` section for more info. If you have a lot of source files in your project, we recommend grouping most into components instead of putting them all in "main". - "build" directory is where build output is created. This directory is created by ``idf.py`` if it doesn't already exist. CMake configures the project and generates interim build files in this directory. Then, after the main build process is run, this directory will also contain interim object files and libraries as well as final binary output files. This directory is usually not added to source control or distributed with the project source code. @@ -234,7 +234,7 @@ To set these variables, use the `cmake set command `_ ie ``set(VARIA .. _rename-main: -Renaming ``main`` component +Renaming ``main`` Component ---------------------------- The build system provides special treatment to the ``main`` component. It is a component that gets automatically added to the build provided that it is in the expected location, PROJECT_DIR/main. All other components in the build are also added as its dependencies, saving the user from hunting down dependencies and providing a build that works right out of the box. Renaming the ``main`` component causes the loss of these behind-the-scenes heavy lifting, requiring the user to specify the location of the newly renamed component and manually specifying its dependencies. Specifically, the steps to renaming ``main`` are as follows: @@ -244,7 +244,7 @@ The build system provides special treatment to the ``main`` component. It is a c 3. Specify the dependencies in the renamed component's CMakeLists.txt file via REQUIRES or PRIV_REQUIRES arguments :ref:`on component registration`. -Overriding default build specifications +Overriding Default Build Specifications --------------------------------------- The build sets some global build specifications (compile flags, definitions, etc.) that gets used in compiling all sources from all components. @@ -281,7 +281,7 @@ When CMake runs to configure the project, it logs the components included in the .. _cmake-components-same-name: -Multiple components with the same name +Multiple Components with the Same Name -------------------------------------- When ESP-IDF is collecting all the components to compile, it will do this in the order specified by ``COMPONENT_DIRS``; by default, this means ESP-IDF's internal components first (``IDF_PATH/components``), then any components in directories specified in ``EXTRA_COMPONENT_DIRS``, and finally the project's components (``PROJECT_DIR/components``). If two or more of these directories contain component sub-directories with the same name, the component in the last place searched is used. This allows, for example, overriding ESP-IDF components with a modified version by copying that component from the ESP-IDF components directory to the project components directory and then modifying it there. If used in this way, the ESP-IDF directory itself can remain untouched. @@ -333,8 +333,7 @@ The following variables are set at the project level, but available for use in c Build/Project Variables ------------------------ -The following are some project/build variables that are available as build properties and whose values can be queried using ``idf_build_get_property`` -from the component CMakeLists.txt: +The following are some project/build variables that are available as build properties and whose values can be queried using ``idf_build_get_property`` from the component CMakeLists.txt: - ``PROJECT_NAME``: Name of the project, as set in project CMakeLists.txt file. - ``PROJECT_DIR``: Absolute path of the project directory containing the project CMakeLists. Same as the ``CMAKE_SOURCE_DIR`` variable. @@ -343,13 +342,13 @@ from the component CMakeLists.txt: - ``IDF_VERSION_MAJOR``, ``IDF_VERSION_MINOR``, ``IDF_VERSION_PATCH``: Components of ESP-IDF version, to be used in conditional expressions. Note that this information is less precise than that provided by ``IDF_VER`` variable. ``v4.0-dev-*``, ``v4.0-beta1``, ``v4.0-rc1`` and ``v4.0`` will all have the same values of ``IDF_VERSION_*`` variables, but different ``IDF_VER`` values. - ``IDF_TARGET``: Name of the target for which the project is being built. - ``PROJECT_VER``: Project version. -- ``EXTRA_PARTITION_SUBTYPES``: CMake list of extra partition subtypes. Each subtype description is a comma separated string with ``type_name, subtype_name, numeric_value`` format. Components may add new subtypes by appending them to this list. * If :ref:`CONFIG_APP_PROJECT_VER_FROM_CONFIG` option is set, the value of :ref:`CONFIG_APP_PROJECT_VER` will be used. * Else, if ``PROJECT_VER`` variable is set in project CMakeLists.txt file, its value will be used. * Else, if the ``PROJECT_DIR/version.txt`` exists, its contents will be used as ``PROJECT_VER``. * Else, if the project is located inside a Git repository, the output of git describe will be used. * Otherwise, ``PROJECT_VER`` will be "1". +- ``EXTRA_PARTITION_SUBTYPES``: CMake list of extra partition subtypes. Each subtype description is a comma separated string with ``type_name, subtype_name, numeric_value`` format. Components may add new subtypes by appending them to this list. Other build properties are listed :ref:`here`. @@ -403,7 +402,7 @@ Component Requirements When compiling each component, the ESP-IDF build system recursively evaluates its dependencies. This means each component needs to declare the components that it depends on ("requires"). -When writing a component +When Writing a Component ------------------------ .. code-block:: cmake @@ -426,7 +425,7 @@ If a components only supports some target chips (values of ``IDF_TARGET``) then .. _example component requirements: -Example of component requirements +Example of Component Requirements --------------------------------- Imagine there is a ``car`` component, which uses the ``engine`` component, which uses the ``spark_plug`` component: @@ -445,7 +444,7 @@ Imagine there is a ``car`` component, which uses the ``engine`` component, which - spark_plug.c - spark_plug.h -Car component +Car Component ^^^^^^^^^^^^^ .. highlight:: c @@ -476,7 +475,7 @@ This means the ``car/CMakeLists.txt`` file needs to declare that ``car`` require - ``INCLUDE_DIRS`` gives the list of public include directories for this component. Because the public interface is ``car.h``, the directory containing ``car.h`` is listed here. - ``REQUIRES`` gives the list of components required by the public interface of this component. Because ``car.h`` is a public header and includes a header from ``engine``, we include ``engine`` here. This makes sure that any other component which includes ``car.h`` will be able to recursively include the required ``engine.h`` also. -Engine component +Engine Component ^^^^^^^^^^^^^^^^ .. highlight:: c @@ -537,21 +536,21 @@ Each component's source file is compiled with these include path directories, as - The ``INCLUDE_DIRS`` belonging to all other components listed in the ``REQUIRES`` and ``PRIV_REQUIRES`` parameters (ie all the current component's public and private dependencies). - Recursively, all of the ``INCLUDE_DIRS`` of those components ``REQUIRES`` lists (ie all public dependencies of this component's dependencies, recursively expanded). -Main component requirements +Main Component Requirements --------------------------- The component named ``main`` is special because it automatically requires all other components in the build. So it's not necessary to pass ``REQUIRES`` or ``PRIV_REQUIRES`` to this component. See :ref:`renaming main ` for a description of what needs to be changed if no longer using the ``main`` component. .. _component-common-requirements: -Common component requirements +Common Component Requirements ----------------------------- To avoid duplication, every component automatically requires some "common" IDF components even if they are not mentioned explicitly. Headers from these components can always be included. The list of common components is: cxx, newlib, freertos, esp_hw_support, heap, log, soc, hal, esp_rom, esp_common, esp_system, xtensa/riscv. -Including components in the build +Including Components in the Build ---------------------------------- - By default, every component is included in the build. @@ -607,7 +606,7 @@ See the `target_link_libraries`_ documentation for more information about this C .. _component-requirements-implementation: -Requirements in the build system implementation +Requirements in the Build System Implementation ----------------------------------------------- - Very early in the CMake configuration process, the script ``expand_requirements.cmake`` is run. This script does a partial evaluation of all component CMakeLists.txt files and builds a graph of component requirements (this :ref:`graph may have cycles `). The graph is used to generate a file ``component_depends.cmake`` in the build directory. @@ -655,6 +654,21 @@ Take care when adding configuration values in this file, as they will be include ``project_include.cmake`` files are used inside ESP-IDF, for defining project-wide build features such as ``esptool.py`` command line arguments and the ``bootloader`` "special app". +Wrappers to Redefine or Extend Existing Functions +------------------------------------------------- + +Thanks to the linker's wrap feature, it is possible to redefine or extend the behavior of an existing ESP-IDF function. To do so, you will need to provide the following CMake declaration in your project's ``CMakeLists.txt`` file: + +.. code-block:: cmake + + target_link_libraries(${COMPONENT_LIB} INTERFACE "-Wl,--wrap=function_to_redefine") + +Where ``function_to_redefine`` is the name of the function to redefine or extend. This option will let the linker replace all the calls to ``function_to_redefine`` functions in the binary libraries with calls to ``__wrap_function_to_redefine`` function. Thus, you must define this new symbol in your application. + +The linker will provide a new symbol named ``__real_function_to_redefine`` which points to the former implementation of the function to redefine. It can be called from the new implementation, making it an extension of the former one. + +This mechanism is shown in the example :example:`build_system/wrappers`. Check :idf_file:`examples/build_system/wrappers/README.md` for more details. + .. _config_only_component: Configuration-Only Components @@ -699,7 +713,7 @@ Here are some more advanced examples of component CMakeLists files. .. _add_conditional_config: -Adding conditional configuration +Adding Conditional Configuration -------------------------------- The configuration system can be used to conditionally compile some files depending on the options selected in the project configuration. @@ -765,7 +779,7 @@ This can also be used to select or stub out an implementation, as such: idf_component_register(SRCS "${srcs}" ...) -Conditions which depend on the target +Conditions Which Depend on the Target ------------------------------------- The current target is available to CMake files via ``IDF_TARGET`` variable. @@ -861,7 +875,7 @@ ESP-IDF has a feature called linker script generation that enables components to .. _component-build-full-override: -Fully Overriding The Component Build Process +Fully Overriding the Component Build Process -------------------------------------------- .. highlight:: cmake @@ -908,8 +922,8 @@ Obviously, there are cases where all these recipes are insufficient for a certai .. _ADDITIONAL_MAKE_CLEAN_FILES_note: -ExternalProject dependencies, clean builds -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +ExternalProject Dependencies and Clean Builds +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ CMake has some unusual behaviour around external project builds: @@ -924,7 +938,7 @@ The best of these approaches for building an external project will depend on the .. _custom-sdkconfig-defaults: -Custom sdkconfig defaults +Custom Sdkconfig Defaults ========================= For example projects or other projects where you don't want to specify a full sdkconfig configuration, but you do want to override some key values from the ESP-IDF defaults, it is possible to create a file ``sdkconfig.defaults`` in the project directory. This file will be used when creating a new config from scratch, or when any new config value hasn't yet been set in the ``sdkconfig`` file. @@ -935,7 +949,7 @@ When specifying multiple files, use a semicolon as the list separator. Files lis Some of the IDF examples include a ``sdkconfig.ci`` file. This is part of the continuous integration (CI) test framework and is ignored by the normal build process. -Target-dependent sdkconfig defaults +Target-dependent Sdkconfig Defaults ----------------------------------- In addition to ``sdkconfig.defaults`` file, build system will also load defaults from ``sdkconfig.defaults.TARGET_NAME`` file, where ``TARGET_NAME`` is the value of ``IDF_TARGET``. For example, for ``esp32`` target, default settings will be taken from ``sdkconfig.defaults`` first, and then from ``sdkconfig.defaults.esp32``. @@ -946,7 +960,7 @@ For example, if ``SDKCONFIG_DEFAULTS="sdkconfig.defaults;sdkconfig_devkit1"``, a .. _flash_parameters: -Flash arguments +Flash Arguments =============== There are some scenarios that we want to flash the target board without IDF. For this case we want to save the built binaries, esptool.py and esptool write_flash arguments. It's simple to write a script to save binaries and esptool.py. @@ -1025,7 +1039,7 @@ It is also possible to wrap a third-party library to be used as a component in t The CMake variable ``ESP_PLATFORM`` is set to 1 whenever the ESP-IDF build system is being used. Tests such as ``if (ESP_PLATFORM)`` can be used in generic CMake code if special IDF-specific logic is required. -Using ESP-IDF components from external libraries +Using ESP-IDF Components from External Libraries ------------------------------------------------ The above example assumes that the external library ``foo`` (or ``tinyxml`` in the case of the ``import_lib`` example) doesn't need to use any ESP-IDF APIs apart from common APIs such as libc, libstdc++, etc. If the external library needs to use APIs provided by other ESP-IDF components, this needs to be specified in the external CMakeLists.txt file by adding a dependency on the library target ``idf::``. @@ -1480,7 +1494,7 @@ No Longer Necessary - In the legacy Make-based build system, it is required to also set ``COMPONENT_SRCDIRS`` if ``COMPONENT_SRCS`` is set. In CMake, the equivalent is not necessary i.e. specifying ``SRC_DIRS`` to ``idf_component_register`` if ``SRCS`` is also specified (in fact, ``SRCS`` is ignored if ``SRC_DIRS`` is specified). -Flashing from make +Flashing from Make ------------------ ``make flash`` and similar targets still work to build and flash. However, project ``sdkconfig`` no longer specifies serial port and baud rate. Environment variables can be used to override these. See :ref:`flash-with-ninja-or-make` for more details. diff --git a/docs/en/api-guides/core_dump.rst b/docs/en/api-guides/core_dump.rst index d4787261fd..e4b47d39a4 100644 --- a/docs/en/api-guides/core_dump.rst +++ b/docs/en/api-guides/core_dump.rst @@ -1,8 +1,6 @@ Core Dump ========= -{IDF_TARGET_ROM_ELF:default="(File for this target is not published yet)", esp32="https://dl.espressif.com/dl/esp32_rom.elf", esp32s2="https://dl.espressif.com/dl/esp32s2_rom.elf", esp32s3="https://dl.espressif.com/dl/esp32s3_rom.elf", esp32c3="https://dl.espressif.com/dl/esp32c3_rev3_rom.elf"} - Overview -------- @@ -67,12 +65,10 @@ There are a number of core dump related configuration options which user can cho * Decode and show summary (info_corefile) * Don't decode -.. only:: esp32c3 +**Reserved stack size (Components -> Core dump -> Reserved stack size)** - **Reserved stack size (Components -> Core dump -> Reserved stack size)** - - Size of the memory to be reserved for core dump stack. If 0 core dump process will run on the stack of crashed task/ISR, otherwise special stack will be allocated. - To ensure that core dump itself will not overflow task/ISR stack set this to the value above 800. + Size of the memory to be reserved for core dump stack. If 0 core dump process will run on the stack of crashed task/ISR, otherwise special stack will be allocated. + To ensure that core dump itself will not overflow task/ISR stack set this to the value above 800. Save core dump to flash ----------------------- @@ -134,7 +130,7 @@ ROM Functions in Backtraces It is possible situation that at the moment of crash some tasks or/and crashed task itself have one or more ROM functions in their callstacks. Since ROM is not part of the program ELF it will be impossible for GDB to parse such callstacks, because it tries to analyse functions' prologues to accomplish that. In that case callstack printing will be broken with error message at the first ROM function. -To overcome this issue you can use ROM ELF provided by Espressif ({IDF_TARGET_ROM_ELF}) and pass it to ``espcoredump.py``. +To overcome this issue, you can use the `ROM ELF `_ provided by Espressif. You can find the {IDF_TARGET_PATH_NAME}'s corresponding ROM ELF file from the list of released archives. The ROM ELF file can then be passed to ``espcoredump.py``. More details about ROM ELFs can be found `here `_. Dumping variables on demand --------------------------- diff --git a/docs/en/api-guides/esp-ble-mesh/ble-mesh-feature-list.rst b/docs/en/api-guides/esp-ble-mesh/ble-mesh-feature-list.rst index 63e92d12c0..017af20fa4 100644 --- a/docs/en/api-guides/esp-ble-mesh/ble-mesh-feature-list.rst +++ b/docs/en/api-guides/esp-ble-mesh/ble-mesh-feature-list.rst @@ -123,11 +123,11 @@ Mesh Applications * :example_file:`Fast Provisioning Client Model Tutorial ` * :example_file:`Fast Provisioning Server Model Tutorial ` * :example:`Example ` - * `Demo Video `__ + * `Demo Video `__ * ESP-BLE-MESH and Wi-Fi Coexistence * :example_file:`Tutorial ` * :example:`Example ` - * `Demo Video `__ + * `Demo Video `__ * ESP-BLE-MESH Console Commands * :example:`Example ` diff --git a/docs/en/api-guides/esp-wifi-mesh.rst b/docs/en/api-guides/esp-wifi-mesh.rst index 81e7599c1a..03284305a8 100644 --- a/docs/en/api-guides/esp-wifi-mesh.rst +++ b/docs/en/api-guides/esp-wifi-mesh.rst @@ -570,7 +570,7 @@ An ESP-WIFI-MESH network channel switch can be triggered by either the router or Root Node Triggered """"""""""""""""""" -**A root node triggered channel switch can only occur when the ESP-WIFI-MESH network is not connected to a router**. By calling :cpp:func:`esp_mesh_switch_channel`, the root node will set an initial Channel Switch Count value and begin including a CSA element in its beacon frames. Each CSA element is then received by second layer nodes, and forwarded downstream in the their own beacon frames. +**A root node triggered channel switch can only occur when the ESP-WIFI-MESH network is not connected to a router**. By calling :cpp:func:`esp_mesh_switch_channel`, the root node will set an initial Channel Switch Count value and begin including a CSA element in its beacon frames. Each CSA element is then received by second layer nodes, and forwarded downstream in their own beacon frames. Router Triggered """""""""""""""" diff --git a/docs/en/api-guides/fatal-errors.rst b/docs/en/api-guides/fatal-errors.rst index 851a44469b..2342325b58 100644 --- a/docs/en/api-guides/fatal-errors.rst +++ b/docs/en/api-guides/fatal-errors.rst @@ -284,7 +284,7 @@ The GDB prompt can be used to inspect CPU registers, local and static variables, RTC Watchdog Timeout -------------------- -The RTC watchdog is used in the startup code to keep track of execution time and also helps to prevent a lock up caused by an unstable power source, it is enabled by default, see :ref:`CONFIG_BOOTLOADER_WDT_ENABLE`. If the execution time is exceeded, the RTC watchdog will restart the system. In this case, the ROM bootloader will print a message with the ``RTC Watchdog Timeout`` reason for the reboot. +The RTC watchdog is used in the startup code to keep track of execution time and it also helps to prevent a lock-up caused by an unstable power source. It is enabled by default (see :ref:`CONFIG_BOOTLOADER_WDT_ENABLE`). If the execution time is exceeded, the RTC watchdog will restart the system. In this case, the ROM bootloader will print a message with the ``RTC Watchdog Timeout`` reason for the reboot. .. only:: esp32 @@ -298,7 +298,7 @@ The RTC watchdog is used in the startup code to keep track of execution time and rst:0x10 (RTCWDT_RTC_RST) -The RTC watchdog covers the execution time from the first stage bootloader (ROM bootloader) to application startup. It is initially set in the ROM bootloader, then configured in the bootloader with the :ref:`CONFIG_BOOTLOADER_WDT_TIME_MS` option (9000ms by default). During the application initialization stage, it is reconfigured again because the source of the slow clock may have changed, and finally disabled right before the ``app_main()`` call. There is an option :ref:`CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE` which allows the RTC watchdog to not be disabled before ``app_main`` and instead the RTC watchdog remains active and must be explicitly reset in your application. +The RTC watchdog covers the execution time from the first stage bootloader (ROM bootloader) to application startup. It is initially set in the ROM bootloader, then configured in the bootloader with the :ref:`CONFIG_BOOTLOADER_WDT_TIME_MS` option (9000 ms by default). During the application initialization stage, it is reconfigured because the source of the slow clock may have changed, and finally disabled right before the ``app_main()`` call. There is an option :ref:`CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE` which prevents the RTC watchdog from being disabled before ``app_main``. Instead, the RTC watchdog remains active and must be fed periodically in your application's code. .. _Guru-Meditation-Errors: diff --git a/docs/en/api-guides/index.rst b/docs/en/api-guides/index.rst index 5024b3fcb6..ef0891f243 100644 --- a/docs/en/api-guides/index.rst +++ b/docs/en/api-guides/index.rst @@ -14,7 +14,7 @@ API Guides :SOC_RTC_MEM_SUPPORTED: deep-sleep-stub :SOC_USB_OTG_SUPPORTED: dfu error-handling - :SOC_BT_SUPPORTED: esp-ble-mesh/ble-mesh-index + :SOC_BLE_MESH_SUPPORTED: esp-ble-mesh/ble-mesh-index freertos-smp :SOC_WIFI_MESH_SUPPORT: esp-wifi-mesh event-handling diff --git a/docs/en/api-guides/jtag-debugging/building-openocd-macos.rst b/docs/en/api-guides/jtag-debugging/building-openocd-macos.rst index 52b6c985c5..9b7b724d11 100644 --- a/docs/en/api-guides/jtag-debugging/building-openocd-macos.rst +++ b/docs/en/api-guides/jtag-debugging/building-openocd-macos.rst @@ -41,6 +41,11 @@ Optionally you can add ``sudo make install`` step at the end. Skip it, if you ha .. note:: * Should an error occur, resolve it and try again until the command ``make`` works. + * Error ``Unknown command 'raggedright'`` may indicate that the required version of ``texinfo`` was not installed on your computer or installed but was not linked to your PATH. To resolve this issue make sure ``texinfo`` is installed and PATH is adjusted prior to the ``./bootstrap`` by running:: + + brew install texinfo + export PATH=/usr/local/opt/texinfo/bin:$PATH + * If there is a submodule problem from OpenOCD, please ``cd`` to the ``openocd-esp32`` directory and input ``git submodule update --init``. * If the ``./configure`` is successfully run, information of enabled JTAG will be printed under ``OpenOCD configuration summary``. * If the information of your device is not shown in the log, use ``./configure`` to enable it as described in ``../openocd-esp32/doc/INSTALL.txt``. diff --git a/docs/en/api-guides/jtag-debugging/configure-other-jtag.rst b/docs/en/api-guides/jtag-debugging/configure-other-jtag.rst index 1f0da8312c..13c66c0d8a 100644 --- a/docs/en/api-guides/jtag-debugging/configure-other-jtag.rst +++ b/docs/en/api-guides/jtag-debugging/configure-other-jtag.rst @@ -1,23 +1,35 @@ -Configure Other JTAG Interface -============================== +Configure Other JTAG Interfaces +=============================== :link_to_translation:`zh_CN:[中文]` -For guidance about which JTAG interface to select to enable operation with OpenOCD and {IDF_TARGET_NAME}, refer to section :ref:`jtag-debugging-selecting-jtag-adapter`. Then follow the three configuration steps below to get it working. +For guidance about which JTAG interface to select when using OpenOCD with {IDF_TARGET_NAME}, refer to the section :ref:`jtag-debugging-selecting-jtag-adapter`. Then follow the configuration steps below to get it working. -.. only:: SOC_USB_SERIAL_JTAG_SUPPORTED +.. only:: SOC_USB_SERIAL_JTAG_SUPPORTED and not esp32c3 - Configure eFuses - ^^^^^^^^^^^^^^^^ + Configure eFuses + ^^^^^^^^^^^^^^^^ - By default, {IDF_TARGET_NAME} JTAG interface is connected to the :doc:`built-in USB_SERIAL_JTAG peripheral `. To use an external JTAG adapter instead, you need to switch the JTAG interface to the GPIO pins. This can be done by burning eFuses using ``espefuse.py`` tool. + By default, {IDF_TARGET_NAME} JTAG interface is connected to the :doc:`built-in USB_SERIAL_JTAG peripheral `. To use an external JTAG adapter instead, you need to switch the JTAG interface to the GPIO pins. This can be done by burning eFuses using ``espefuse.py`` tool. - Burning eFuses is an irreversible operation, so consider both options below before starting the process. + - Burning ``DIS_USB_JTAG`` eFuse will permanently disable the connection between USB_SERIAL_JTAG and the JTAG port of the CPU. JTAG interface can then be connected to |jtag-gpio-list|. Note that USB CDC functionality of USB_SERIAL_JTAG will still be usable, i.e., flashing and monitoring over USB CDC will still work. + - Burning ``STRAP_JTAG_SEL`` eFuse will enable selection of JTAG interface by a strapping pin, |jtag-sel-gpio|. If the strapping pin is low when {IDF_TARGET_NAME} is reset, JTAG interface will use |jtag-gpio-list|. If the strapping pin is high, USB_SERIAL_JTAG will be used as the JTAG interface. - - Burning ``DIS_USB_JTAG`` eFuse will permanently disable the connection between USB_SERIAL_JTAG and the JTAG port of the CPU. JTAG interface can then be connected to |jtag-gpio-list|. Note that USB CDC functionality of USB_SERIAL_JTAG will still be usable, i.e. flashing and monitoring over USB CDC will still work. + .. warning:: + Burning eFuses is an irreversible operation, so please consider the above options before starting the process. - - Burning ``JTAG_SEL_ENABLE`` eFuse will enable selection of JTAG interface by a strapping pin, |jtag-sel-gpio|. If the strapping pin is low when {IDF_TARGET_NAME} is reset, JTAG interface will use |jtag-gpio-list|. If the strapping pin is high, USB_SERIAL_JTAG will be used as the JTAG interface. +.. only:: esp32c3 + + Configure eFuses + ^^^^^^^^^^^^^^^^ + + By default, {IDF_TARGET_NAME} JTAG interface is connected to the :doc:`built-in USB_SERIAL_JTAG peripheral `. To use an external JTAG adapter instead, you need to switch the JTAG interface to the GPIO pins. This can be done by burning eFuses using ``espefuse.py`` tool. + + Burning ``DIS_USB_JTAG`` eFuse will permanently disable the connection between USB_SERIAL_JTAG and the JTAG port of the CPU. JTAG interface can then be connected to |jtag-gpio-list|. Note that USB CDC functionality of USB_SERIAL_JTAG will still be usable, i.e., flashing and monitoring over USB CDC will still work. + + .. warning:: + Burning eFuses is an irreversible operation, so please consider the above option before starting the process. Configure Hardware ^^^^^^^^^^^^^^^^^^ diff --git a/docs/en/api-guides/jtag-debugging/debugging-examples.rst b/docs/en/api-guides/jtag-debugging/debugging-examples.rst index 73f7e1e2d7..3390b20a6f 100644 --- a/docs/en/api-guides/jtag-debugging/debugging-examples.rst +++ b/docs/en/api-guides/jtag-debugging/debugging-examples.rst @@ -245,6 +245,7 @@ Examples in this section 5. :ref:`jtag-debugging-examples-command-line-05` 6. :ref:`jtag-debugging-examples-command-line-06` 7. :ref:`jtag-debugging-examples-command-line-07` +8. :ref:`jtag-debugging-examples-command-line-08` .. _jtag-debugging-examples-command-line-01: @@ -445,10 +446,6 @@ To check it delete all breakpoints and enter ``c`` to resume application. Then e In particular case above, the application has been halted in line 52 of code in file ``freertos_hooks.c``. Now you can resume it again by enter ``c`` or do some debugging as discussed below. -.. note:: - - In MSYS2 shell Ctrl+C does not halt the target but exists debugger. To resolve this issue consider debugging with :ref:`jtag-debugging-examples-eclipse` or check a workaround under http://www.mingw.org/wiki/Workaround_for_GDB_Ctrl_C_Interrupt. - .. _jtag-debugging-examples-command-line-04: @@ -627,6 +624,34 @@ If current value of ``i`` is less than ``2`` and program is resumed, it will bli (gdb) +.. _jtag-debugging-examples-command-line-08: + +Debugging FreeRTOS Objects +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +This part might be interesting when you are debugging FreeRTOS tasks interactions. +Users that need to use the FreeRTOS task interactions can use the GDB ``freertos`` command. The ``freertos`` command is not native to GDB and comes from the `freertos-gdb `_ Python extension module. The ``freertos`` command contains a series of sub-commands as demonstrated in the code snippet:: + + (gdb) freertos + "freertos" must be followed by the name of a subcommand. + List of freertos subcommands: + + freertos queue -- Generate a print out of the current queues info. + freertos semaphore -- Generate a print out of the current semaphores info. + freertos task -- Generate a print out of the current tasks and their states. + freertos timer -- Generate a print out of the current timers info. + +For a more detailed description of this extension, please refer to https://pypi.org/project/freertos-gdb. + +.. note:: + + The freertos-gdb Python module is included as a Python package requirement by ESP-IDF, thus should be automatically installed (see :ref:`get-started-set-up-tools` for more details). + + The FreeRTOS extension automatically loads in case GDB is executed with command via ``idf.py gdb``. Otherwise, the module could be enabled via the ``python import freertos_gdb`` command inside GDB. + + Users only need to have Python 3.6 (or above) that contains a Python shared library. + + Obtaining help on commands ^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/en/api-guides/jtag-debugging/index.rst b/docs/en/api-guides/jtag-debugging/index.rst index 48a6dc01a8..a2187d7dfb 100644 --- a/docs/en/api-guides/jtag-debugging/index.rst +++ b/docs/en/api-guides/jtag-debugging/index.rst @@ -249,6 +249,11 @@ This section is intended for users not familiar with GDB. It presents example de Similar debugging actions are provided using GDB from :ref:`jtag-debugging-examples-command-line`. +.. note:: + + :ref:`jtag-debugging-examples-command-line-08` is currently only available for command line debugging. + + Before proceeding to examples, set up your {IDF_TARGET_NAME} target and load it with :example:`get-started/blink`. diff --git a/docs/en/api-guides/jtag-debugging/tips-and-quirks.rst b/docs/en/api-guides/jtag-debugging/tips-and-quirks.rst index f881965fb5..edffe00a88 100644 --- a/docs/en/api-guides/jtag-debugging/tips-and-quirks.rst +++ b/docs/en/api-guides/jtag-debugging/tips-and-quirks.rst @@ -71,6 +71,8 @@ FreeRTOS support OpenOCD has explicit support for the ESP-IDF FreeRTOS. GDB can see FreeRTOS tasks as threads. Viewing them all can be done using the GDB ``i threads`` command, changing to a certain task is done with ``thread n``, with ``n`` being the number of the thread. FreeRTOS detection can be disabled in target's configuration. For more details see :ref:`jtag-debugging-tip-openocd-configure-target`. +GDB has a Python extension for FreeRTOS support. ESP-IDF automatically loads this module into GDB with the ``idf.py gdb`` command when the system requirements are met. See more details in :ref:`jtag-debugging-examples-command-line-08`. + .. only:: esp32 .. _jtag-debugging-tip-code-flash-voltage: diff --git a/docs/en/api-guides/linker-script-generation.rst b/docs/en/api-guides/linker-script-generation.rst index 53f24e6f5e..2770ada499 100644 --- a/docs/en/api-guides/linker-script-generation.rst +++ b/docs/en/api-guides/linker-script-generation.rst @@ -13,7 +13,7 @@ For example, it may be necessary to place: * critical code in RAM for performance reasons. * executable code in IRAM so that it can be ran while cache is disabled. - :SOC_RTC_MEM_SUPPORTED: * code in RTC memory for use in a wake stub or the ULP coprocessor. + :SOC_RTC_MEM_SUPPORTED: * code in RTC memory for use in a wake stub. :SOC_ULP_SUPPORTED: * code in RTC memory for use by the ULP coprocessor. With the linker script generation mechanism, it is possible to specify these placements at the component level within ESP-IDF. The component presents information on how it would like to place its symbols, objects or the entire archive. During build, the information presented by the components are collected, parsed and processed; and the placement rules generated is used to link the app. diff --git a/docs/en/api-guides/linux-host-testing.rst b/docs/en/api-guides/linux-host-testing.rst index 57ae25382d..ba9dad1381 100644 --- a/docs/en/api-guides/linux-host-testing.rst +++ b/docs/en/api-guides/linux-host-testing.rst @@ -36,10 +36,11 @@ The current focus of the Linux host tests is on creating isolated unit tests of A complete implementation of IDF to run on Linux does not exist currently. -There are currently two examples for running IDF-built code on Linux host: +Examples for running IDF-built code on Linux host include (non-exhaustive list): -- An example :example_file:`hello-world application ` -- A :component_file:`unit test for NVS `. +- :component_file:`unit test for the NVS Page class `. +- :component_file:`unit test for esp_event `. +- :component_file:`unit test for mqtt `. Inside the component which should be tested, there is a separate directory ``host_test``, besides the "traditional" ``test`` directory or the ``test_apps`` directory. It has one or more subdirectories:: diff --git a/docs/en/api-guides/memory-types.rst b/docs/en/api-guides/memory-types.rst index 1fa849bbd8..8cc3bddb8e 100644 --- a/docs/en/api-guides/memory-types.rst +++ b/docs/en/api-guides/memory-types.rst @@ -127,6 +127,7 @@ If a function is not explicitly placed into :ref:`iram` or RTC memory, it is pla During :doc:`startup`, the bootloader (which runs from IRAM) configures the MMU flash cache to map the app's instruction code region to the instruction space. Flash accessed via the MMU is cached using some internal SRAM and accessing cached flash data is as fast as accessing other types of internal memory. + .. _drom: DROM (data stored in flash) diff --git a/docs/en/api-guides/partition-tables.rst b/docs/en/api-guides/partition-tables.rst index c168f498be..0fb17fbeb9 100644 --- a/docs/en/api-guides/partition-tables.rst +++ b/docs/en/api-guides/partition-tables.rst @@ -66,12 +66,12 @@ The CSV format is the same format as printed in the summaries shown above. Howev * Each non-comment line in the CSV file is a partition definition. * The "Offset" field for each partition is empty. The gen_esp32part.py tool fills in each blank offset, starting after the partition table and making sure each partition is aligned correctly. -Name field +Name Field ~~~~~~~~~~ -Name field can be any meaningful name. It is not significant to the {IDF_TARGET_NAME}. Names longer than 16 characters will be truncated. +Name field can be any meaningful name. It is not significant to the {IDF_TARGET_NAME}. The maximum length of names is 16 bytes, including one null terminator. Names longer than the maximum length will be truncated. -Type field +Type Field ~~~~~~~~~~ Partition type field can be specified as ``app`` (0x00) or ``data`` (0x01). Or it can be a number 0-254 (or as hex 0x00-0xFE). Types 0x00-0x3F are reserved for ESP-IDF core functions. @@ -90,11 +90,11 @@ SubType ~~~~~~~ {IDF_TARGET_ESP_PHY_REF:default = ":ref:`CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION`", esp32c2 = "(not updated yet)"} -The 8-bit subtype field is specific to a given partition type. ESP-IDF currently only specifies the meaning of the subtype field for ``app`` and ``data`` partition types. +The 8-bit SubType field is specific to a given partition type. ESP-IDF currently only specifies the meaning of the subtype field for ``app`` and ``data`` partition types. See enum :cpp:type:`esp_partition_subtype_t` for the full list of subtypes defined by ESP-IDF, including the following: -* When type is ``app``, the subtype field can be specified as ``factory`` (0x00), ``ota_0`` (0x10) ... ``ota_15`` (0x1F) or ``test`` (0x20). +* When type is ``app``, the SubType field can be specified as ``factory`` (0x00), ``ota_0`` (0x10) ... ``ota_15`` (0x1F) or ``test`` (0x20). - ``factory`` (0x00) is the default app partition. The bootloader will execute the factory app unless there it sees a partition of type data/ota, in which case it reads this partition to determine which OTA image to boot. @@ -134,7 +134,7 @@ See enum :cpp:type:`esp_partition_subtype_t` for the full list of subtypes defin Extra Partition SubTypes ~~~~~~~~~~~~~~~~~~~~~~~~ -A component can define a new partition subtype by setting the ``EXTRA_PARTITION_SUBTYPES`` property. This property is a CMake list, each entry of which is a comma separated string with ``, , `` format. The build system uses this property to add extra subtypes and creates fields named ``ESP_PARTITION_SUBTYPE__`` in :cpp:type:`esp_partition_type_t`. The project can use this subtype to define partitions in the partitions table CSV file and use the new fields in :cpp:type:`esp_partition_type_t`. +A component can define a new partition subtype by setting the ``EXTRA_PARTITION_SUBTYPES`` property. This property is a CMake list, each entry of which is a comma separated string with ``, , `` format. The build system uses this property to add extra subtypes and creates fields named ``ESP_PARTITION_SUBTYPE__`` in :cpp:type:`esp_partition_subtype_t`. The project can use this subtype to define partitions in the partitions table CSV file and use the new fields in :cpp:type:`esp_partition_subtype_t`. Offset & Size ~~~~~~~~~~~~~ @@ -189,7 +189,7 @@ Currently these checks are performed for the following binaries: Although the build process will fail if the size check returns an error, the binary files are still generated and can be flashed (although they may not work if they are too large for the available space.) -MD5 checksum +MD5 Checksum ~~~~~~~~~~~~ The binary format of the partition table contains an MD5 checksum computed based on the partition table. This checksum is used for checking the integrity of the partition table during the boot. @@ -203,7 +203,7 @@ The binary format of the partition table contains an MD5 checksum computed based The MD5 checksum generation can be disabled by the ``--disable-md5sum`` option of ``gen_esp32part.py`` or by the :ref:`CONFIG_PARTITION_TABLE_MD5` option. -Flashing the partition table +Flashing the Partition Table ---------------------------- * ``idf.py partition-table-flash``: will flash the partition table with esptool.py. diff --git a/docs/en/api-guides/performance/size.rst b/docs/en/api-guides/performance/size.rst index 3d98cecf3b..19b36e9de9 100644 --- a/docs/en/api-guides/performance/size.rst +++ b/docs/en/api-guides/performance/size.rst @@ -16,6 +16,9 @@ To optimize both firmware binary size and memory usage it's necessary to measure Using the :ref:`idf.py` sub-commands ``size``, ``size-components`` and ``size-files`` provides a summary of memory used by the project: +.. note:: + It is possible to add ``-DOUTPUT_FORMAT=csv`` or ``-DOUTPUT_FORMAT=json`` to get the output in CSV or JSON format. + Size Summary (idf.py size) ^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -188,9 +191,9 @@ Comparing Two Binaries If making some changes that affect binary size, it's possible to use an ESP-IDF tool to break down the exact differences in size. -This operation isn't part of ``idf.py``, it's necessary to run the ``idf-size.py`` Python tool directly. +This operation isn't part of ``idf.py``, it's necessary to run the ``idf_size.py`` Python tool directly. -To do so, first locate the linker map file in the build directory. It will have the name ``PROJECTNAME.map``. The ``idf-size.py`` tool performs its analysis based on the output of the linker map file. +To do so, first locate the linker map file in the build directory. It will have the name ``PROJECTNAME.map``. The ``idf_size.py`` tool performs its analysis based on the output of the linker map file. To compare with another binary, you will also need its corresponding ``.map`` file saved from the build directory. @@ -215,6 +218,9 @@ We can see from the "Difference" column that changing this one setting caused th It's also possible to use the "diff" mode to output a table of component-level (static library archive) differences: +.. note:: + To get the output in JSON or CSV format using ``idf_size.py`` it is possible to use the ``--format`` option. + .. code-block:: bash $IDF_PATH/tools/idf_size.py --archives --diff build_Og/https_request.map build_Oshttps_request.map @@ -298,7 +304,7 @@ The following configuration options will reduce the final binary size of almost - Disabling :ref:`CONFIG_ESP_ERR_TO_NAME_LOOKUP` will remove the lookup table to translate user-friendly names for error values (see :doc:`/api-guides/error-handling`) in error logs, etc. This saves some binary size, but error values will be printed as integers only. - Setting :ref:`CONFIG_ESP_SYSTEM_PANIC` to "Silent reboot" will save a small amount of binary size, however this is *only* recommended if no one will use UART output to debug the device. :CONFIG_IDF_TARGET_ARCH_RISCV: - Set :ref:`CONFIG_COMPILER_SAVE_RESTORE_LIBCALLS` to reduce binary size by replacing inlined prologues/epilogues with library calls. - + - If the application binary uses only one of the security versions of the protocomm component, then the support for others can be disabled to save some code size. The support can be disabled through :ref:`CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0`, :ref:`CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1` or :ref:`CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2` respectively. .. note:: In addition to the many configuration items shown here, there are a number of configuration options where changing the option from the default will increase binary size. These are not noted here. Where the increase is significant, this is usually noted in the configuration item help text. diff --git a/docs/en/api-guides/performance/speed.rst b/docs/en/api-guides/performance/speed.rst index f9b2f4bdb8..860f6a385c 100644 --- a/docs/en/api-guides/performance/speed.rst +++ b/docs/en/api-guides/performance/speed.rst @@ -126,7 +126,7 @@ In addition to the overall performance improvements shown above, the following o .. list:: - Minimizing the :ref:`CONFIG_LOG_DEFAULT_LEVEL` and :ref:`CONFIG_BOOTLOADER_LOG_LEVEL` has a large impact on startup time. To enable more logging after the app starts up, set the :ref:`CONFIG_LOG_MAXIMUM_LEVEL` as well and then call :cpp:func:`esp_log_level_set` to restore higher level logs. The :example:`system/startup_time` main function shows how to do this. - - If using deep sleep, setting :ref:`CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP` allows a faster wake from sleep. Note that if using Secure Boot this represents a security compromise, as Secure Boot validation will not be performed on wake. + :SOC_RTC_FAST_MEM_SUPPORTED: - If using deep sleep, setting :ref:`CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP` allows a faster wake from sleep. Note that if using Secure Boot this represents a security compromise, as Secure Boot validation will not be performed on wake. - Setting :ref:`CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON` will skip verifying the binary on every boot from power-on reset. How much time this saves depends on the binary size and the flash settings. Note that this setting carries some risk if the flash becomes corrupt unexpectedly. Read the help text of the :ref:`config item ` for an explanation and recommendations if using this option. - It's possible to save a small amount of time during boot by disabling RTC slow clock calibration. To do so, set :ref:`CONFIG_RTC_CLK_CAL_CYCLES` to 0. Any part of the firmware that uses RTC slow clock as a timing source will be less accurate as a result. diff --git a/docs/en/api-guides/tools/idf-py.rst b/docs/en/api-guides/tools/idf-py.rst index 2dbad4c627..fd02b2eeec 100644 --- a/docs/en/api-guides/tools/idf-py.rst +++ b/docs/en/api-guides/tools/idf-py.rst @@ -146,7 +146,7 @@ or partition table as applicable. Hints on how to resolve errors ============================== -``idf.py`` will try to suggest hints on how to resolve errors. It works with a database of hints stored in :idf_file:`tools/idf_py_actions/hints.yml` and the hints will be printed if a match is found for the given error. ``idf.py menuconfig`` is not supported by automatic hints on resolving errors. +``idf.py`` will try to suggest hints on how to resolve errors. It works with a database of hints stored in :idf_file:`tools/idf_py_actions/hints.yml` and the hints will be printed if a match is found for the given error. The monitor, menuconfig, gdb and openocd targets are not supported at the moment by automatic hints on resolving errors. The ``--no-hints`` argument of ``idf.py`` can be used to turn the hints off in case they are not desired. @@ -191,7 +191,7 @@ Will print app size information including occupied RAM and FLASH and section siz .. code-block:: bash - idf.py size + idf.py size-components Similarly, this will print the same information for each component used in the project. @@ -201,7 +201,11 @@ Similarly, this will print the same information for each component used in the p Will print size information per source file in the project. -If you define variable ``-DOUTPUT_JSON=1`` when running CMake (or ``idf.py``), the output will be formatted as JSON not as human readable text. See ``idf.py-size`` for more information. +Options +^^^^^^^ + +- ``--format`` specifies the output format with available options: ``text``, ``csv``, ``json``, default being ``text``. +- ``--output-file`` optionally specifies the name of the file to print the command output to instead of the standard output. Reconfigure the project: reconfigure ------------------------------------ diff --git a/docs/en/api-guides/tools/idf-tools-notes.inc b/docs/en/api-guides/tools/idf-tools-notes.inc index 99ed36d383..4aee6e2d39 100644 --- a/docs/en/api-guides/tools/idf-tools-notes.inc +++ b/docs/en/api-guides/tools/idf-tools-notes.inc @@ -35,11 +35,6 @@ .. tool-esp32ulp-elf-notes ---- - -.. tool-esp32s2ulp-elf-notes - - --- .. tool-openocd-esp32-notes @@ -77,6 +72,11 @@ On Linux and macOS, it is recommended to install ninja using the OS-specific pac .. tool-dfu-util-notes +--- + +.. tool-esp-rom-elfs-notes + + --- .. tool-idf-python-notes diff --git a/docs/en/api-guides/tools/idf-tools.rst b/docs/en/api-guides/tools/idf-tools.rst index 5847423bec..291314ce34 100644 --- a/docs/en/api-guides/tools/idf-tools.rst +++ b/docs/en/api-guides/tools/idf-tools.rst @@ -111,7 +111,7 @@ Any mirror server can be used provided the URL matches the ``github.com`` downlo * ``install-python-env``: Create a Python virtual environment in the ``${IDF_TOOLS_PATH}/python_env`` directory and install there the required Python packages. An optional ``--features`` argument allows one to specify a comma-separated list of features to be added or removed. Feature that begins with ``-`` will be removed and features with ``+`` or without any sign will be added. Example syntax for removing feature ``XY`` is ``--features=-XY`` and for adding ``--features=+XY`` or ``--features=XY``. If both removing and adding options are provided with the same feature, no operation is performed. For each feature a requirements file must exist. For example, feature ``XY`` is a valid feature if ``${IDF_PATH}/tools/requirements/requirements.XY.txt`` is an existing file with a list of Python packages to be installed. There is one mandatory ``core`` feature ensuring core functionality of ESP-IDF (build, flash, monitor, debug in console). There can be an arbitrary number of optional features. The selected list of features is stored in ``idf-env.json``. The requirement files contain a list of the desired Python packages to be installed and ``espidf.constraints.*.txt`` downloaded from https://dl.espressif.com and stored in ``${IDF_TOOLS_PATH}`` the package version requirements for a given ESP-IDF version. Althought it is not recommended, the download and use of constraint files can be disabled with the ``--no-constraints`` argument or setting the ``IDF_PYTHON_CHECK_CONSTRAINTS`` environment variable to ``no``. -* ``check-python-dependencies``: Checks if all required Python packages are installed. Packages from ``${IDF_PATH}/tools/requirements/requirements.*.txt`` files selected by the feature list of ``idf-env.json`` are checked with the package versions specified in the ``espidf.constraints.*.txt`` file. The constraint file will be downloaded from https://dl.espressif.com if this step hasn't been done already in the last day. The use of constraints files can be disabled similarly to the ``install-python-env`` command. +* ``check-python-dependencies``: Checks if all required Python packages are installed. Packages from ``${IDF_PATH}/tools/requirements/requirements.*.txt`` files selected by the feature list of ``idf-env.json`` are checked with the package versions specified in the ``espidf.constraints.*.txt`` file. The constraint file is downloaded with ``install-python-env`` command. The use of constraints files can be disabled similarly to the ``install-python-env`` command. * ``uninstall``: Print and remove tools, that are currently not used by active ESP-IDF version. diff --git a/docs/en/api-guides/usb-serial-jtag-console.rst b/docs/en/api-guides/usb-serial-jtag-console.rst index 650c56fa1a..6d64aa4547 100644 --- a/docs/en/api-guides/usb-serial-jtag-console.rst +++ b/docs/en/api-guides/usb-serial-jtag-console.rst @@ -63,4 +63,16 @@ There are several limitations to the USB console feature. These may or may not b 3. The behavior between an actual USB-to-serial bridge chip and the USB Serial/JTAG Controller is slightly different if the ESP-IDF application does not listen for incoming bytes. An USB-to-serial bridge chip will just send the bytes to a (not listening) chip, while the USB Serial/JTAG Controller will block until the application reads the bytes. This can lead to a non-responsive looking terminal program. -4. If the application enters light-sleep (including automatic light-sleep) or software reset, etc. The USB CDC device will still work on the system. But be aware that this might increase the power consumption, if you don't need USB CDC in sleep and want to keep low power consumption, please disable the menuconfig ``CONFIG_RTC_CLOCK_BBPLL_POWER_ON_WITH_USB``. Moreover, the power consumption will only increase when your USB CDC port is really in use (like data transaction), therefore, if your USB CDC just connects with power bank or battery, rather than something like computer, you don't need to care about the increasing power consumption mentioned above. +4. The USB CDC device won't work in sleep modes as normal due to the lack of APB clock in sleep modes. This includes deep-sleep, light-sleep (automataic light-sleep as well). + +5. The power consumption in sleep modes will be higher if the USB CDC device is in use. + + This is because we want to keep the USB CDC device alive during software reset by default. + + However there is an issue that this might also increase the power consumption in sleep modes. This is because the software keeps a clock source on during the reset to keep the USB CDC device alive. As a side-effect, the clock is also kept on during sleep modes. There is one exception: the clock will only be kept on when your USB CDC port is really in use (like data transaction), therefore, if your USB CDC is connected to power bank or battery, etc., instead of a valid USB host (for example, a PC), the power consumption will not increase. + + If you still want to keep low power consumption in sleep modes: + + 1. If you are not using the USB CDC port, you don't need to do anything. Software will detect if the CDC device is connected to a valid host before going to sleep, and keep the clocks only when the host is connected. Otherwise the clocks will be turned off as normal. + + 2. If you are using the USB CDC port, please disable the menuconfig option ``CONFIG_RTC_CLOCK_BBPLL_POWER_ON_WITH_USB``. The clock will be switched off as normal during software reset and in sleep modes. In these cases, the USB CDC device may be unplugged from the host. diff --git a/docs/en/api-guides/wifi.rst b/docs/en/api-guides/wifi.rst index b94d5239d7..861a9b9e52 100644 --- a/docs/en/api-guides/wifi.rst +++ b/docs/en/api-guides/wifi.rst @@ -508,7 +508,7 @@ The scan type and other per-scan attributes are configured by :cpp:func:`esp_wif - min=0, max>0: scan dwells on each channel for ``max`` ms. - min>0, max>0: the minimum time the scan dwells on each channel is ``min`` ms. If no AP is found during this time frame, the scan switches to the next channel. Otherwise, the scan dwells on the channel for ``max`` ms. - If you want to improve the performance of the the scan, you can try to modify these two parameters. + If you want to improve the performance of the scan, you can try to modify these two parameters. There are also some global scan attributes which are configured by API :cpp:func:`esp_wifi_set_config()`, refer to `Station Basic Configuration`_ @@ -1365,13 +1365,7 @@ The following table depicts which country info is used in different Wi-Fi modes For scan: - - If schan+nchan-1 >11 : - - Use active scan from schan to 11 and use passive scan from 12 to 14. - - - If schan+nchan-1 <= 11 : - - Use active scan from schan to schan+nchan-1 and use passive scan from schan+nchan to 14. + Use active scan from 1 to 11 and use passive scan from 12 to 14. Always keep in mind that if an AP with hidden SSID and station is set to a passive scan channel, the passive scan will not find it. In other words, if the application hopes to find the AP with hidden SSID in every channel, the policy of country info should be configured to WIFI_COUNTRY_POLICY_MANUAL. @@ -1381,24 +1375,25 @@ The following table depicts which country info is used in different Wi-Fi modes For scan: - - If schan+nchan-1 >11 : - - Use active scan from schan to 11 and use passive scan from 12 to schan+nchan-1. - - - If schan+nchan-1 <= 11 : - Use active scan from schan to schan+nchan-1. + * - AP - WIFI_COUNTRY_POLICY_AUTO - Always use the configured country info. + * - AP - WIFI_COUNTRY_POLICY_MANUAL - Always use the configured country info. + * - Station/AP-coexistence - WIFI_COUNTRY_POLICY_AUTO - - If the station does not connect to any external AP, the AP uses the configured country info. If the station connects to an external AP, the AP has the same country info as the station. + - Station: Same as station mode with policy WIFI_COUNTRY_POLICY_AUTO. + AP: If the station does not connect to any external AP, the AP uses the configured country info. If the station connects to an external AP, the AP has the same country info as the station. - Same as station mode with policy WIFI_COUNTRY_POLICY_AUTO. + * - Station/AP-coexistence + - WIFI_COUNTRY_POLICY_MANUAL + - Station: Same as station mode with policy WIFI_COUNTRY_POLICY_MANUAL. + AP: Same as AP mode with policy WIFI_COUNTRY_POLICY_MANUAL. Home Channel @@ -2479,7 +2474,6 @@ The parameters not mentioned in the following table should be set to the default - 31.5 - 27.7 - .. only:: esp32s3 .. list-table:: @@ -2577,14 +2571,12 @@ The parameters not mentioned in the following table should be set to the default The test was performed with a single stream in a shielded box using an ASUS RT-N66U router. {IDF_TARGET_NAME}'s CPU is single core with 160 MHz. {IDF_TARGET_NAME}'s flash is in QIO mode with 80 MHz. - .. only:: esp32c2 .. note:: The test was performed with a single stream in a shielded box using an Redmi RM2100 router. {IDF_TARGET_NAME}'s CPU is single core with 120 MHz. {IDF_TARGET_NAME}'s flash is in QIO mode with 60 MHz. - .. only:: esp32 **Ranks:** diff --git a/docs/en/api-reference/bluetooth/index.rst b/docs/en/api-reference/bluetooth/index.rst index 52326945c6..3ce38bac69 100644 --- a/docs/en/api-reference/bluetooth/index.rst +++ b/docs/en/api-reference/bluetooth/index.rst @@ -8,9 +8,9 @@ Bluetooth API bt_common bt_le - :SOC_CLASSIC_BT_SUPPORTED: classic_bt + :SOC_BT_CLASSIC_SUPPORTED: classic_bt controller_vhci - esp-ble-mesh + :SOC_BLE_MESH_SUPPORTED: esp-ble-mesh nimble/index ESP-IDF currently supports two host stacks. The Bluedroid based stack (default) supports classic Bluetooth as well as BLE. On the other hand, Apache NimBLE based stack is BLE only. For users to make a choice: diff --git a/docs/en/api-reference/bluetooth/nimble/index.rst b/docs/en/api-reference/bluetooth/nimble/index.rst index 04b0a14e58..fb68debdd8 100644 --- a/docs/en/api-reference/bluetooth/nimble/index.rst +++ b/docs/en/api-reference/bluetooth/nimble/index.rst @@ -30,8 +30,7 @@ To begin with, make sure that the NimBLE stack is enabled from menuconfig :ref:` Typical programming sequence with NimBLE stack consists of the following steps: * Initialize NVS flash using :cpp:func:`nvs_flash_init` API. This is because ESP controller uses NVS during initialization. - * Call :cpp:func:`esp_nimble_hci_and_controller_init` to initialize ESP controller as well as transport layer. This will also link the host and controller modules together. Alternatively, if ESP controller is already initialized, then :cpp:func:`esp_nimble_hci_init` can be called for the remaining initialization. - * Initialize the host stack using ``nimble_port_init``. + * Initialize the host and controller stack using ``nimble_port_init``. * Initialize the required NimBLE host configuration parameters and callbacks * Perform application specific tasks/initialization * Run the thread for host stack using ``nimble_port_freertos_init`` diff --git a/docs/en/api-reference/network/esp_netif_driver.rst b/docs/en/api-reference/network/esp_netif_driver.rst index 000d5eb37d..6ea1b5104b 100644 --- a/docs/en/api-reference/network/esp_netif_driver.rst +++ b/docs/en/api-reference/network/esp_netif_driver.rst @@ -91,7 +91,12 @@ Network stack connection ------------------------ The packet data path functions for transmitting and freeing the rx buffer (defined in the I/O driver) are called from -the esp-netif, specifically from its TCP/IP stack connecting layer. The following API reference outlines these network stack -interaction with the esp-netif. +the esp-netif, specifically from its TCP/IP stack connecting layer. + +Note, that IDF provides several network stack configurations for the most common network interfaces, such as for the WiFi station or Ethernet. +These configurations are defined in :component_file:`esp_netif/include/esp_netif_defaults.h` and should be sufficient for most network drivers. +(In rare cases, expert users might want to define custom lwIP based interface layers; it is possible, but an explicit dependency to lwIP needs to be set) + +The following API reference outlines these network stack interaction with the esp-netif: .. include-build-file:: inc/esp_netif_net_stack.inc diff --git a/docs/en/api-reference/network/esp_wifi.rst b/docs/en/api-reference/network/esp_wifi.rst index f00dccc238..87e2c59c1f 100644 --- a/docs/en/api-reference/network/esp_wifi.rst +++ b/docs/en/api-reference/network/esp_wifi.rst @@ -20,11 +20,7 @@ The Wi-Fi libraries provide support for configuring and monitoring the {IDF_TARG Application Examples -------------------- -The :example:`wifi` directory of ESP-IDF examples contains the following applications: - -* Code examples for Wi-Fi. - -* A simple `esp-idf-template `_ application to demonstrate a minimal IDF project structure. +Several application examples demonstrating the functionality of Wi-Fi library are provided in :example:`wifi` directory of ESP-IDF repository. Please check the :example_file:`README ` for more details. API Reference diff --git a/docs/en/api-reference/peripherals/adc_continuous.rst b/docs/en/api-reference/peripherals/adc_continuous.rst index 6f30edafbe..f6f313b821 100644 --- a/docs/en/api-reference/peripherals/adc_continuous.rst +++ b/docs/en/api-reference/peripherals/adc_continuous.rst @@ -18,6 +18,7 @@ Driver Concepts ^^^^^^^^^^^^^^^ ADC continuous mode conversion is made up with multiple Conversion Frames. + - Conversion Frame: One Conversion Frame contains multiple Conversion Results. Conversion Frame size is configured in :cpp:func:`adc_continuous_new_handle`, in bytes. - Conversion Result: One Conversion Result contains multiple bytes (see :c:macro:`SOC_ADC_DIGI_RESULT_BYTES`). Its structure is :cpp:type:`adc_digi_output_data_t`, including ADC unit, ADC channel and raw data. @@ -199,6 +200,7 @@ Dmax Maximum of the output ADC raw digital reading result, which is 2^bitwidt To do further calbration to convert the ADC raw result to voltage in mV, please refer to calibration doc :doc:`adc_calibration`. +.. _hardware_limitations_adc_continuous: Hardware Limitations ^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/en/api-reference/peripherals/adc_oneshot.rst b/docs/en/api-reference/peripherals/adc_oneshot.rst index 506d922e88..f8cd4c5336 100644 --- a/docs/en/api-reference/peripherals/adc_oneshot.rst +++ b/docs/en/api-reference/peripherals/adc_oneshot.rst @@ -41,7 +41,7 @@ The ADC oneshot mode driver is implemented based on {IDF_TARGET_NAME} SAR ADC mo To install an ADC instance, set up the required initial configuration structure :cpp:type:`adc_oneshot_unit_init_cfg_t`: - :cpp:member:`adc_oneshot_unit_init_cfg_t::unit_id` selects the ADC. Please refer to the `datasheet <{IDF_TARGET_TRM_EN_URL}>`__ to know dedicated analog IOs for this ADC. -- :cpp:member:`adc_oneshot_unit_init_cfg_t::ulp_mode` sets if the ADC will be working under super low power mode. +- :cpp:member:`adc_oneshot_unit_init_cfg_t::ulp_mode` sets if the ADC will be working under ULP mode. .. todo:: @@ -62,7 +62,7 @@ Create an ADC Unit Handle under Normal Oneshot Mode adc_oneshot_unit_handle_t adc1_handle; adc_oneshot_unit_init_cfg_t init_config1 = { .unit_id = ADC_UNIT_1, - .ulp_mode = false, + .ulp_mode = ADC_ULP_MODE_DISABLE, }; ESP_ERROR_CHECK(adc_oneshot_new_unit(&init_config1, &adc1_handle)); @@ -78,10 +78,9 @@ Recycle the ADC Unit Unit Configuration ^^^^^^^^^^^^^^^^^^ -After an ADC instance is created, set up the :cpp:type:`adc_oneshot_chan_cfg_t` to configure ADC IO to measure analog signal: +After an ADC instance is created, set up the :cpp:type:`adc_oneshot_chan_cfg_t` to configure ADC IOs to measure analog signal: - :cpp:member:`adc_oneshot_chan_cfg_t::atten`, ADC attenuation. Refer to the On-Chip Sensor chapter in `TRM <{IDF_TARGET_TRM_EN_URL}>`__. -- :cpp:member:`adc_oneshot_chan_cfg_t::channel`, the IO corresponding ADC channel number. See below note. - :cpp:member:`adc_oneshot_chan_cfg_t::bitwidth`, the bitwidth of the raw conversion result. .. note:: @@ -89,7 +88,8 @@ After an ADC instance is created, set up the :cpp:type:`adc_oneshot_chan_cfg_t` For the IO corresponding ADC channel number. Check `datasheet <{IDF_TARGET_TRM_EN_URL}>`__ to know the ADC IOs. On the other hand, :cpp:func:`adc_continuous_io_to_channel` and :cpp:func:`adc_continuous_channel_to_io` can be used to know the ADC channels and ADC IOs. -To make these settings take effect, call :cpp:func:`adc_oneshot_config_channel` with above configuration structure. Especially, this :cpp:func:`adc_oneshot_config_channel` can be called multiple times to configure different ADC channels. Drvier will save these per channel configurations internally. +To make these settings take effect, call :cpp:func:`adc_oneshot_config_channel` with above configuration structure. You should specify an ADC channel to be configured as well. +Especially, this :cpp:func:`adc_oneshot_config_channel` can be called multiple times to configure different ADC channels. Drvier will save these per channel configurations internally. Configure Two ADC Channels @@ -98,14 +98,11 @@ Configure Two ADC Channels .. code:: c adc_oneshot_chan_cfg_t config = { - .channel = EXAMPLE_ADC1_CHAN0, .bitwidth = ADC_BITWIDTH_DEFAULT, .atten = ADC_ATTEN_DB_11, }; - ESP_ERROR_CHECK(adc_oneshot_config_channel(adc1_handle, &config)); - - config.channel = EXAMPLE_ADC1_CHAN1; - ESP_ERROR_CHECK(adc_oneshot_config_channel(adc1_handle, &config)); + ESP_ERROR_CHECK(adc_oneshot_config_channel(adc1_handle, EXAMPLE_ADC1_CHAN0, &config)); + ESP_ERROR_CHECK(adc_oneshot_config_channel(adc1_handle, EXAMPLE_ADC1_CHAN1, &config)); Read Conversion Result @@ -146,6 +143,7 @@ Read Raw Result ESP_ERROR_CHECK(adc_oneshot_read(adc1_handle, EXAMPLE_ADC1_CHAN1, &adc_raw[0][1])); ESP_LOGI(TAG, "ADC%d Channel[%d] Raw Data: %d", ADC_UNIT_1 + 1, EXAMPLE_ADC1_CHAN1, adc_raw[0][1]); +.. _hardware_limitations_adc_oneshot: Hardware Limitations ^^^^^^^^^^^^^^^^^^^^ @@ -188,7 +186,7 @@ Thread Safety Above functions are guaranteed to be thread safe. Therefore, you can call them from different RTOS tasks without protection by extra locks. -- :cpp:func:`adc_oneshot_del_unit` is not thread safe. Besides, concurrently calling this function may result in thread-safe APIs fail. +- :cpp:func:`adc_oneshot_del_unit` is not thread safe. Besides, concurrently calling this function may result in failures of above thread-safe APIs. Kconfig Options diff --git a/docs/en/api-reference/peripherals/ds.rst b/docs/en/api-reference/peripherals/ds.rst index 78308185e1..09b98070e4 100644 --- a/docs/en/api-reference/peripherals/ds.rst +++ b/docs/en/api-reference/peripherals/ds.rst @@ -63,13 +63,9 @@ The configuration involves the following steps - For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *Digital Signature (DS)* [`PDF <{IDF_TARGET_TRM_EN_URL}#digsig>`__]. -To configure the DS peripheral for development purposes, you can use the python script :example_file:`configure_ds.py`. -More details about the `configure_ds.py` script can be found at :example_file:`mqtt example README `. +To configure the DS peripheral for development purposes, you can use the `esp-secure-cert-tool `_. -The encrypted private key parameters obtained after the DS peripheral configuration are then to be kept in flash. Furthermore, they are to be passed to the DS peripheral which makes use of those parameters for the Digital Signature operation. -:doc:`Non Volatile Storage<../storage/nvs_flash>` can be used to store the encrypted private key parameters in flash. -The script :example_file:`configure_ds.py` creates an NVS partition for the encrypted private key parameters. Then the script flashes this partition onto the {IDF_TARGET_NAME}. -The application then needs to read the DS data from NVS, which can be done with the function ``esp_read_ds_data_from_nvs()`` in file :example_file:`ssl_ds/main/app_main.c ` +The encrypted private key parameters obtained after the DS peripheral configuration are then to be kept in flash. Furthermore, they are to be passed to the DS peripheral which makes use of those parameters for the Digital Signature operation. The application then needs to read the ds data from the flash which has been done through the API's provided by the `esp_secure_cert_mgr `_ component. Please refer the `component/README. `_ for more details. The process of initializing the DS peripheral and then performing the Digital Signature operation is done internally with help of `ESP-TLS`. Please refer to `Digital Signature with ESP-TLS` in :doc:`ESP-TLS <../protocols/esp_tls>` for more details. As mentioned in the `ESP-TLS` documentation, the application only needs to provide the encrypted private key parameters to the esp_tls context (as `ds_data`), which internally performs diff --git a/docs/en/api-reference/peripherals/gpio.rst b/docs/en/api-reference/peripherals/gpio.rst index 19ff5f0184..531d8f40ae 100644 --- a/docs/en/api-reference/peripherals/gpio.rst +++ b/docs/en/api-reference/peripherals/gpio.rst @@ -198,7 +198,8 @@ Overview - JTAG: GPIO12-15 are usually used for inline debug. - GPI: GPIO34-39 can only be set as input mode and do not have software-enabled pullup or pulldown functions. - TXD & RXD are usually used for flashing and debugging. - - ADC2: ADC2 pins cannot be used when Wi-Fi is used. So, if you are having trouble getting the value from an ADC2 GPIO while using Wi-Fi, you may consider using an ADC1 GPIO instead, which should solve your problem. For more details, please refer to `ADC limitations `_. + - ADC2: ADC2 pins cannot be used when Wi-Fi is used. So, if you are having trouble getting the value from an ADC2 GPIO while using Wi-Fi, you may consider using an ADC1 GPIO instead, which should solve your problem. For more details, please refer to :ref:`Hardware Limitations of ADC Continuous Mode ` and :ref:`Hardware Limitations of ADC Oneshot Mode `. + - Please do not use the interrupt of GPIO36 and GPIO39 when using ADC or Wi-Fi and Bluetooth with sleep mode enabled. Please refer to `ESP32 ECO and Workarounds for Bugs `_ > Section 3.11 for the detailed description of the issue. .. only:: esp32s2 diff --git a/docs/en/api-reference/peripherals/gptimer.rst b/docs/en/api-reference/peripherals/gptimer.rst index a663d5b425..c06e0ffbfc 100644 --- a/docs/en/api-reference/peripherals/gptimer.rst +++ b/docs/en/api-reference/peripherals/gptimer.rst @@ -17,18 +17,18 @@ Functional Overview The following sections of this document cover the typical steps to install and operate a timer: -- :ref:`resource-allocation` - covers which parameters should be set up to get a timer handle and how to recycle the resources when GPTimer finishes working. +- :ref:`gptimer-resource-allocation` - covers which parameters should be set up to get a timer handle and how to recycle the resources when GPTimer finishes working. - :ref:`set-and-get-count-value` - covers how to force the timer counting from a start point and how to get the count value at anytime. - :ref:`set-up-alarm-action` - covers the parameters that should be set up to enable the alarm event. -- :ref:`register-event-callbacks` - covers how to hook user specific code to the alarm event callback function. +- :ref:`gptimer-register-event-callbacks` - covers how to hook user specific code to the alarm event callback function. - :ref:`enable-and-disable-timer` - covers how to enable and disable the timer. - :ref:`start-and-stop-timer` - shows some typical use cases that start the timer with different alarm behavior. -- :ref:`power-management` - describes how different source clock selections can affect power consumption. -- :ref:`iram-safe` - describes tips on how to make the timer interrupt and IO control functions work better along with a disabled cache. -- :ref:`thread-safety` - lists which APIs are guaranteed to be thread safe by the driver. -- :ref:`kconfig-options` - lists the supported Kconfig options that can be used to make a different effect on driver behavior. +- :ref:`gptimer-power-management` - describes how different source clock selections can affect power consumption. +- :ref:`gptimer-iram-safe` - describes tips on how to make the timer interrupt and IO control functions work better along with a disabled cache. +- :ref:`gptimer-thread-safety` - lists which APIs are guaranteed to be thread safe by the driver. +- :ref:`gptimer-kconfig-options` - lists the supported Kconfig options that can be used to make a different effect on driver behavior. -.. _resource-allocation: +.. _gptimer-resource-allocation: Resource Allocation ^^^^^^^^^^^^^^^^^^^ @@ -39,7 +39,7 @@ A GPTimer instance is represented by :cpp:type:`gptimer_handle_t`. The driver be To install a timer instance, there is a configuration structure that needs to be given in advance: :cpp:type:`gptimer_config_t`: -- :cpp:member:`gptimer_config_t::clk_src` selects the source clock for the timer. The available clocks are listed in :cpp:type:`gptimer_clock_source_t`, you can only pick one of them. For the effect on power consumption of different clock source, please refer to Section :ref:`power-management`. +- :cpp:member:`gptimer_config_t::clk_src` selects the source clock for the timer. The available clocks are listed in :cpp:type:`gptimer_clock_source_t`, you can only pick one of them. For the effect on power consumption of different clock source, please refer to Section :ref:`gptimer-power-management`. - :cpp:member:`gptimer_config_t::direction` sets the counting direction of the timer, supported directions are listed in :cpp:type:`gptimer_count_direction_t`, you can only pick one of them. @@ -94,7 +94,7 @@ To make the alarm configurations take effect, you should call :cpp:func:`gptimer If an alarm value is set and the timer has already exceeded this value, the alarm will be triggered immediately. -.. _register-event-callbacks: +.. _gptimer-register-event-callbacks: Register Event Callbacks ^^^^^^^^^^^^^^^^^^^^^^^^ @@ -116,7 +116,7 @@ Before doing IO control to the timer, you needs to enable the timer first, by ca * Switch the timer driver state from **init** to **enable**. * Enable the interrupt service if it has been lazy installed by :cpp:func:`gptimer_register_event_callbacks`. -* Acquire a proper power management lock if a specific clock source (e.g. APB clock) is selected. See Section :ref:`power-management` for more information. +* Acquire a proper power management lock if a specific clock source (e.g. APB clock) is selected. See Section :ref:`gptimer-power-management` for more information. Calling :cpp:func:`gptimer_disable` will do the opposite, that is, put the timer driver back to the **init** state, disable the interrupts service and release the power management lock. @@ -256,7 +256,7 @@ Alarm value can be updated dynamically inside the ISR handler callback, by chang ESP_ERROR_CHECK(gptimer_enable(gptimer)); ESP_ERROR_CHECK(gptimer_start(gptimer, &alarm_config)); -.. _power-management: +.. _gptimer-power-management: Power Management ^^^^^^^^^^^^^^^^ @@ -267,7 +267,7 @@ However, the driver can prevent the system from changing APB frequency by acquir If other gptimer clock sources are selected such as :cpp:enumerator:`GPTIMER_CLK_SRC_XTAL`, then the driver will not install power management lock. The XTAL clock source is more suitable for a low power application as long as the source clock can still provide sufficient resolution. -.. _iram-safe: +.. _gptimer-iram-safe: IRAM Safe ^^^^^^^^^ @@ -290,7 +290,7 @@ There is another Kconfig option :ref:`CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM` that can - :cpp:func:`gptimer_set_raw_count` - :cpp:func:`gptimer_set_alarm_action` -.. _thread-safety: +.. _gptimer-thread-safety: Thread Safety ^^^^^^^^^^^^^ @@ -307,13 +307,13 @@ The following functions are allowed to run under ISR context, as the driver uses Other functions that take :cpp:type:`gptimer_handle_t` as the first positional parameter, are not treated as thread safe, which means you should avoid calling them from multiple tasks. -.. _kconfig-options: +.. _gptimer-kconfig-options: Kconfig Options ^^^^^^^^^^^^^^^ -- :ref:`CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM` controls where to place the GPTimer control functions (IRAM or flash), see Section :ref:`iram-safe` for more information. -- :ref:`CONFIG_GPTIMER_ISR_IRAM_SAFE` controls whether the default ISR handler can work when the cache is disabled, see Section :ref:`iram-safe` for more information. +- :ref:`CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM` controls where to place the GPTimer control functions (IRAM or flash), see Section :ref:`gptimer-iram-safe` for more information. +- :ref:`CONFIG_GPTIMER_ISR_IRAM_SAFE` controls whether the default ISR handler can work when the cache is disabled, see Section :ref:`gptimer-iram-safe` for more information. - :ref:`CONFIG_GPTIMER_ENABLE_DEBUG_LOG` is used to enabled the debug log output. Enable this option will increase the firmware binary size. Application Examples diff --git a/docs/en/api-reference/peripherals/i2s.rst b/docs/en/api-reference/peripherals/i2s.rst index 54abfe0645..2c5cb35aa5 100644 --- a/docs/en/api-reference/peripherals/i2s.rst +++ b/docs/en/api-reference/peripherals/i2s.rst @@ -108,7 +108,7 @@ Overview of All Modes ========= ======== ======== ======== ======== ======== ========== ESP32 I2S 0/1 I2S 0 I2S 0 none I2S 0 I2S 0 ESP32S2 I2S 0 none none none none I2S 0 -ESP32C3 I2S 0 I2S 0 none I2S0 none none +ESP32C3 I2S 0 I2S 0 none I2S 0 none none ESP32S3 I2S 0/1 I2S 0 I2S 0 I2S 0/1 none none ========= ======== ======== ======== ======== ======== ========== @@ -723,6 +723,12 @@ Here is the table of the data that received in the buffer with different :cpp:me Please refer to :ref:`i2s-api-reference-i2s_tdm` for TDM API information. And for more details, please refer to :component_file:`driver/include/driver/i2s_tdm.h`. + .. note:: + + When setting the clock configuration for a slave role, please be aware that :cpp:member:`i2s_tdm_clk_config_t::bclk_div` should not be smaller than 8 (hardware limitation), increase this field can reduce the data lagging that sent from the slave. In the high sample rate case, the data might lag behind more than one ``bclk`` which will lead data malposition, you can try to increase :cpp:member:`i2s_tdm_clk_config_t::bclk_div` gradually to correct it. + + As :cpp:member:`i2s_tdm_clk_config_t::bclk_div` is the division of ``mclk`` to ``bclk``, increase it will also increase the ``mclk`` frequency, therefore, the clock calculation might failed if the ``mclk`` is too high to divide from the source clock, which means :cpp:member:`i2s_tdm_clk_config_t::bclk_div` is not the bigger the better. + TDM TX Mode ~~~~~~~~~~~ diff --git a/docs/en/api-reference/peripherals/lcd.rst b/docs/en/api-reference/peripherals/lcd.rst index 58d761c60a..57947b2431 100644 --- a/docs/en/api-reference/peripherals/lcd.rst +++ b/docs/en/api-reference/peripherals/lcd.rst @@ -218,7 +218,7 @@ After we get the LCD handle, the remaining LCD operations are the same for diffe .. note:: It should never happen in a well-designed embedded application, but it can in theory be possible that the DMA cannot deliver data as fast as the LCD consumes it. In the {IDF_TARGET_NAME} hardware, this leads to the LCD simply outputting dummy bytes while DMA waits for data. If we were to run DMA in a stream fashion, this would mean a de-sync between the LCD address the DMA reads the data for and the LCD address the LCD peripheral thinks it outputs data for, leading to a **permanently** shifted image. - In order to stop this from happening, you can enable the :ref:`CONFIG_LCD_RGB_RESTART_IN_VSYNC` option, so the driver will restart the DMA in the VBlank interrupt; this way we always know where it starts. + In order to stop this from happening, you can either enable the :ref:`CONFIG_LCD_RGB_RESTART_IN_VSYNC` option, so the driver can restart the DMA in the VBlank interrupt automatically or call :cpp:func:`esp_lcd_rgb_panel_restart` to restart the DMA manually. Note :cpp:func:`esp_lcd_rgb_panel_restart` doesn't restart the DMA immediately, the DMA will still be restarted in the next VSYNC event. Application Example ------------------- @@ -231,6 +231,11 @@ LCD examples are located under: :example:`peripherals/lcd`: * RGB panel example with scatter chart UI - :example:`peripherals/lcd/rgb_panel` * I2C interfaced OLED display scrolling text - :example:`peripherals/lcd/i2c_oled` +Other LCD drivers +----------------- + +Drivers for some LCD and touch controllers are available in `IDF Component Registry `_. The list of available and planned drivers with links is in this `table `__. + API Reference ------------- diff --git a/docs/en/api-reference/peripherals/mcpwm.rst b/docs/en/api-reference/peripherals/mcpwm.rst index 6166899582..017d934ac1 100644 --- a/docs/en/api-reference/peripherals/mcpwm.rst +++ b/docs/en/api-reference/peripherals/mcpwm.rst @@ -33,7 +33,7 @@ Description of the MCPWM functionality is divided into the following sections: - `Resource Allocation and Initialization <#resource-allocation-and-initialization>`__ - covers how to allocate various MCPWM objects, like timers, operators, comparators, generators and so on. These objects are the basis of the following IO setting and control functions. - `Timer Operations and Events <#timer-operations-and-events>`__ - describes control functions and event callbacks that supported by the MCPWM timer. -- `Comparator Operations and Events `__ - describes control functions and event callbacks that supported by the MCPWM comparator. +- `Comparator Operations and Events <#comparator-operations-and-events>`__ - describes control functions and event callbacks that supported by the MCPWM comparator. - `Generator Actions on Events <#generator-actions-on-events>`__ - describes how to set actions for MCPWM generators on particular events that generated by the MCPWM timer and comparators. - `Classical PWM Waveforms and Generator Configurations <#classical-pwm-waveforms-and-generator-configurations>`__ - demonstrates some classical PWM waveforms that can be achieved by configuring generator actions. - `Dead Time <#dead-time>`__ - describes how to set dead time for MCPWM generators. @@ -797,7 +797,7 @@ The basic functionality of MCPWM capture is to record the time when any pulse ed MCPWM BLDC with Hall Sensor -The capture timer is usually connected with several capture channels, please refer to ``__ for resource allocation. +The capture timer is usually connected with several capture channels, please refer to `MCPWM Capture Timer and Channels <#mcpwm-capture-timer-and-channels>`__ for resource allocation. Register Event Callbacks ~~~~~~~~~~~~~~~~~~~~~~~~ @@ -806,7 +806,7 @@ The MCPWM capture channel can inform the user when there's a valid edge detected - :cpp:member:`mcpwm_capture_event_callbacks_t::on_cap` sets callback function for the capture channel when a valid edge is detected. -The callback function will provide event specific data of type :cpp:type:`mcpwm_capture_event_data_t`, so that you can get the the edge of the capture signal in :cpp:member:`mcpwm_capture_event_data_t::cap_edge` and the count value of that moment in :cpp:member:`mcpwm_capture_event_data_t::cap_value`. +The callback function will provide event specific data of type :cpp:type:`mcpwm_capture_event_data_t`, so that you can get the edge of the capture signal in :cpp:member:`mcpwm_capture_event_data_t::cap_edge` and the count value of that moment in :cpp:member:`mcpwm_capture_event_data_t::cap_value`. The callback function is called within the ISR context, so is should **not** attempt to block (e.g., make sure that only FreeRTOS APIs with ``ISR`` suffix is called within the function). @@ -814,6 +814,11 @@ The parameter ``user_data`` of :cpp:func:`mcpwm_capture_channel_register_event_c This function will lazy install interrupt service for the MCPWM capture channel, whereas the service can only be removed in :cpp:type:`mcpwm_del_capture_channel`. +Enable and Disable Capture Channel +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The capture channel is not enabled after allocation by :cpp:func:`mcpwm_new_capture_channel`. You should call :cpp:func:`mcpwm_capture_channel_enable` and :cpp:func:`mcpwm_capture_channel_disable` accordingly to enable or disable the channel. If the interrupt service is lazy installed during registering event callbacks for the channel in :cpp:func:`mcpwm_capture_channel_register_event_callbacks`, :cpp:func:`mcpwm_capture_channel_enable` will enable the interrupt service as well. + Enable and Disable Capture Timer ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -856,19 +861,26 @@ There's a Kconfig option :ref:`CONFIG_MCPWM_ISR_IRAM_SAFE` that will: This will allow the interrupt to run while the cache is disabled but will come at the cost of increased IRAM consumption. +There is another Kconfig option :ref:`CONFIG_MCPWM_CTRL_FUNC_IN_IRAM` that can put commonly used IO control functions into IRAM as well. So, these functions can also be executable when the cache is disabled. These IO control functions are as follows: + +- :cpp:func:`mcpwm_comparator_set_compare_value` + Thread Safety ^^^^^^^^^^^^^ The factory functions like :cpp:func:`mcpwm_new_timer` are guaranteed to be thread safe by the driver, which means, you can call it from different RTOS tasks without protection by extra locks. -No functions are allowed to run within ISR environment. +The following functions are allowed to run under ISR context, as the driver uses a critical section to prevent them being called concurrently in the task and ISR. -Functions that are not related to `Resource Allocation <#resource-allocation-and-initialization>`__, are not thread safe. Thus, you should avoid calling them in different tasks without mutex protection. +- :cpp:func:`mcpwm_comparator_set_compare_value` + +Other functions that are not related to `Resource Allocation <#resource-allocation-and-initialization>`__, are not thread safe. Thus, you should avoid calling them in different tasks without mutex protection. Kconfig Options ^^^^^^^^^^^^^^^ - :ref:`CONFIG_MCPWM_ISR_IRAM_SAFE` controls whether the default ISR handler can work when cache is disabled, see `IRAM Safe <#iram-safe>`__ for more information. +- :ref:`CONFIG_MCPWM_CTRL_FUNC_IN_IRAM` controls where to place the MCPWM control functions (IRAM or flash), see `IRAM Safe <#iram-safe>`__ for more information. - :ref:`CONFIG_MCPWM_ENABLE_DEBUG_LOG` is used to enabled the debug log output. Enable this option will increase the firmware binary size. Application Examples diff --git a/docs/en/api-reference/peripherals/pcnt.rst b/docs/en/api-reference/peripherals/pcnt.rst index accee48fb6..1892b5ed61 100644 --- a/docs/en/api-reference/peripherals/pcnt.rst +++ b/docs/en/api-reference/peripherals/pcnt.rst @@ -173,7 +173,7 @@ The PCNT unit features filters to ignore possible short glitches in the signals. You can enable the glitch filter for PCNT unit by calling :cpp:func:`pcnt_unit_set_glitch_filter` with the filter configuration provided above. Particularly, you can disable the glitch filter later by calling :cpp:func:`pcnt_unit_set_glitch_filter` with a `NULL` filter configuration. -This function should be called when the the unit is in the init state. Otherwise, it will return :c:macro:`ESP_ERR_INVALID_STATE` error. +This function should be called when the unit is in the init state. Otherwise, it will return :c:macro:`ESP_ERR_INVALID_STATE` error. .. note:: diff --git a/docs/en/api-reference/peripherals/sdmmc_host.rst b/docs/en/api-reference/peripherals/sdmmc_host.rst index 15b4955cdc..1469e86f1f 100644 --- a/docs/en/api-reference/peripherals/sdmmc_host.rst +++ b/docs/en/api-reference/peripherals/sdmmc_host.rst @@ -94,6 +94,9 @@ In the designs where communication at 40 MHz frequency can be achieved, it is po sdmmc_host_t host = SDMMC_HOST_DEFAULT(); host.max_freq_khz = SDMMC_FREQ_HIGHSPEED; +If you need a specific frequency other than standard speeds, you are free to use any value from within appropriate range of the SD interface given (SDMMC or SDSPI). However, the real clock frequency shall be calculated by the underlying driver and the value can be different from the one required. +For the SDMMC, ``max_freq_khz`` works as the upper limit so the final frequency value shall be always lower or equal. For the SDSPI, the nearest fitting frequency is supplied and thus the value can be greater than / equal to / lower than ``max_freq_khz``. + To configure the bus width, set the ``width`` field of :cpp:class:`sdmmc_slot_config_t`. For example, to set 1-line mode:: sdmmc_slot_config_t slot = SDMMC_SLOT_CONFIG_DEFAULT(); diff --git a/docs/en/api-reference/peripherals/sdspi_host.rst b/docs/en/api-reference/peripherals/sdspi_host.rst index 11013ffacd..51fd18a2ea 100644 --- a/docs/en/api-reference/peripherals/sdspi_host.rst +++ b/docs/en/api-reference/peripherals/sdspi_host.rst @@ -19,7 +19,7 @@ The SD SPI driver uses software-controlled CS signal. How to Use ---------- -Firstly, use the macro :c:macro:`SDSPI_DEVICE_CONFIG_DEFAULT` to initialize a structure :cpp:type:`sdmmc_slot_config_t`, which is used to initialize an SD SPI device. This macro will also fill in the default pin mappings, which is same as the pin mappings of SDMMC host driver. Modify the host and pins of the structure to desired value. Then call `sdspi_host_init_device` to initialize the SD SPI device and attach to its bus. +Firstly, use the macro :c:macro:`SDSPI_DEVICE_CONFIG_DEFAULT` to initialize a structure :cpp:type:`sdspi_device_config_t`, which is used to initialize an SD SPI device. This macro will also fill in the default pin mappings, which is same as the pin mappings of SDMMC host driver. Modify the host and pins of the structure to desired value. Then call `sdspi_host_init_device` to initialize the SD SPI device and attach to its bus. Then use :c:macro:`SDSPI_HOST_DEFAULT` macro to initialize a :cpp:type:`sdmmc_host_t` structure, which is used to store the state and configurations of upper layer (SD/SDIO/MMC driver). Modify the `slot` parameter of the structure to the SD SPI device spi_handle just returned from `sdspi_host_init_device`. Call `sdmmc_card_init` with the :cpp:type:`sdmmc_host_t` to probe and initialize the SD card. diff --git a/docs/en/api-reference/peripherals/spi_master.rst b/docs/en/api-reference/peripherals/spi_master.rst index 68639eb7f6..7f032066bc 100644 --- a/docs/en/api-reference/peripherals/spi_master.rst +++ b/docs/en/api-reference/peripherals/spi_master.rst @@ -98,8 +98,8 @@ Phase Description ============== ========================================================================================================= **Command** In this phase, a command (0-16 bit) is written to the bus by the Host. **Address** In this phase, an address (0-{IDF_TARGET_ADDR_LEN} bit) is transmitted over the bus by the Host. -**Write** Host sends data to a Device. This data follows the optional command and address phases and is indistinguishable from them at the electrical level. **Dummy** This phase is configurable and is used to meet the timing requirements. +**Write** Host sends data to a Device. This data follows the optional command and address phases and is indistinguishable from them at the electrical level. **Read** Device sends data to its Host. ============== ========================================================================================================= @@ -461,8 +461,37 @@ Typical transaction duration for one byte of data are given below. SPI Clock Frequency ^^^^^^^^^^^^^^^^^^^ +The driver support setting an SPI peripheral to different clock frequencies. Actual clock frequency may not be exactly equal to the number you set, it will be re-calculated by the driver to the nearest hardware compatible number, you can call :cpp:func:`spi_device_get_actual_freq` to get the actual frequency computed by driver. -Transferring each byte takes eight times the clock period *8/fspi*. +Theoretical maximum transfer speed of Write or Read phase can be calculated according to the table below: + +.. only:: not SOC_SPI_SUPPORT_OCT + + +--------------------------------+------------------------+ + | Line Width of Write/Read phase | Speed (Bps) | + +================================+========================+ + | 1-Line | *SPI Frequency / 8* | + +--------------------------------+------------------------+ + | 2-Line | *SPI Frequency / 4* | + +--------------------------------+------------------------+ + | 4-Line | *SPI Frequency / 2* | + +--------------------------------+------------------------+ + +.. only:: SOC_SPI_SUPPORT_OCT + + +--------------------------------+------------------------+ + | Line Width of Write/Read phase | Speed (Bps) | + +================================+========================+ + | 1-Line | *SPI Frequency / 8* | + +--------------------------------+------------------------+ + | 2-Line | *SPI Frequency / 4* | + +--------------------------------+------------------------+ + | 4-Line | *SPI Frequency / 2* | + +--------------------------------+------------------------+ + | 8-Line | *SPI Frequency* | + +--------------------------------+------------------------+ + +The transfer speed calculation of other phases(command, address, dummy) are similar. .. only:: esp32 diff --git a/docs/en/api-reference/peripherals/touch_element.rst b/docs/en/api-reference/peripherals/touch_element.rst index 869f950c0d..86797227c0 100644 --- a/docs/en/api-reference/peripherals/touch_element.rst +++ b/docs/en/api-reference/peripherals/touch_element.rst @@ -355,6 +355,34 @@ In code, the waterproof configuration may look like as follows: ... } +Wakeup from Light/Deep Sleep +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Only Touch Button can be configured as wake up source. + +Light or deep sleep are both supported to be waken up by touch sensor. For the light sleep, any installed touch button can wake it up. But only the sleep button can wake up from deep sleep, and the touch sensor will do a calibration immediately, the reference value will be calibrated to a wrong value if our finger doesn't remove timely. Though the wrong reference value will recover after the finger remove away and have no affect to the driver logic, if you don't want to see a wrong reference value while waking up from deep sleep, you can call :cpp:func:`touch_element_sleep_enable_wakeup_calibration` to disable the wakeup calibration. + +The Touch Element Wakeup example is available in `example/system/light_sleep` directory. + +.. code-block:: c + + void app_main() + { + ... + touch_element_install(); + touch_button_install(); //Initialize the touch button + touch_button_create(&element_handle); //Create a new Touch element + + ... + + // ESP_ERROR_CHECK(touch_element_enable_light_sleep(&sleep_config)); + ESP_ERROR_CHECK(touch_element_enable_deep_sleep(button_handle[0], &sleep_config)); + // ESP_ERROR_CHECK(touch_element_sleep_enable_wakeup_calibration(button_handle[0], false)); // (optional) Disable wakeup calibration to prevent updating the base line to a wrong value + + touch_element_start(); + + ... + } Application Example ------------------- diff --git a/docs/en/api-reference/peripherals/touch_pad.rst b/docs/en/api-reference/peripherals/touch_pad.rst index 2f89be7042..6223b0784a 100644 --- a/docs/en/api-reference/peripherals/touch_pad.rst +++ b/docs/en/api-reference/peripherals/touch_pad.rst @@ -131,16 +131,29 @@ The following list summarizes available measurement parameters and corresponding * Charge and discharge times of one measurement: :cpp:func:`touch_pad_set_charge_discharge_times` -Relationship between the voltage range (high / low reference voltages), speed (slope), and measurement time is shown in the figure below. +Relationship between the voltage range (high/low reference voltages), speed (slope), and measurement time is shown in the figure below. -.. figure:: ../../../_static/touch_pad-measurement-parameters.jpg - :align: center - :alt: Touch Pad - relationship between measurement parameters - :figclass: align-center +.. only:: SOC_TOUCH_VERSION_1 - Touch pad - relationship between measurement parameters + .. figure:: ../../../_static/touch_pad-measurement-parameters.jpg + :align: center + :alt: Touch Pad - relationship between measurement parameters + :figclass: align-center -The last chart *Output* represents the touch sensor reading, i.e., the count of pulses collected within the measurement time. + Touch pad - relationship between measurement parameters + + The last chart *Output* represents the touch sensor reading, i.e., the count of pulses collected within the measurement time. + +.. only:: SOC_TOUCH_VERSION_2 + + .. figure:: ../../../_static/touch_pad-measurement-parameters-version2.png + :align: center + :alt: Touch Pad - relationship between measurement parameters + :figclass: align-center + + Touch pad - relationship between measurement parameters + + The last chart *Output* represents the touch sensor reading, i.e., the time taken to accumulate the fixed number of cycles. All functions are provided in pairs to *set* a specific parameter and to *get* the current parameter's value, e.g., :cpp:func:`touch_pad_set_voltage` and :cpp:func:`touch_pad_get_voltage`. diff --git a/docs/en/api-reference/peripherals/twai.rst b/docs/en/api-reference/peripherals/twai.rst index 2667b27058..3988210c06 100644 --- a/docs/en/api-reference/peripherals/twai.rst +++ b/docs/en/api-reference/peripherals/twai.rst @@ -329,7 +329,7 @@ Message Fields and Flags The TWAI driver distinguishes different types of messages by using the various bit field members of the :cpp:type:`twai_message_t` structure. These bit field members determine whether a message is in standard or extended format, a remote frame, and the type of transmission to use when transmitting such a message. -These bit field members can also be toggled using the the `flags` member of :cpp:type:`twai_message_t` and the following message flags: +These bit field members can also be toggled using the `flags` member of :cpp:type:`twai_message_t` and the following message flags: .. list-table:: :widths: 30 70 diff --git a/docs/en/api-reference/peripherals/usb_device.rst b/docs/en/api-reference/peripherals/usb_device.rst index fed107be45..79c4934552 100644 --- a/docs/en/api-reference/peripherals/usb_device.rst +++ b/docs/en/api-reference/peripherals/usb_device.rst @@ -11,7 +11,7 @@ USB Device Driver Overview -------- -The driver allows users to use {IDF_TARGET_NAME} chips to develop USB devices on a top of the TinyUSB stack. TinyUSB is integrated with ESP-IDF to provide USB features of the framework. Using this driver the chip works as a composite device supporting several USB devices simultaneously. Currently, only the Communications Device Class (CDC) type of the device with the Abstract Control Model (ACM) subclass and the Musical Instrument Digital Interface (MIDI) are supported. +The driver allows you to use {IDF_TARGET_NAME} chips to develop USB devices on a top of TinyUSB stack. TinyUSB is integrated with ESP-IDF to provide USB features of the framework. Using this driver the chip works as simple or composite device supporting several USB devices simultaneously. Our USB-OTG implementation is limited to {IDF_TARGET_USB_EP_NUM} number of USB endpoints ({IDF_TARGET_USB_EP_NUM_INOUT} IN/OUT endpoints and {IDF_TARGET_USB_EP_NUM_IN} IN endpoint) - find more information in `technical reference manual <{IDF_TARGET_TRM_EN_URL}>`_. @@ -20,8 +20,8 @@ Features - Configuration of device and string USB descriptors - USB Serial Device (CDC-ACM) -- Input and output through USB Serial Device -- USB MIDI Device +- Input and output streams through USB Serial Device +- Other USB classes (MIDI, MSC, HID...) support directly via TinyUSB Hardware USB Connection @@ -67,9 +67,9 @@ Via Menuconfig options you can specify: Descriptors Configuration ^^^^^^^^^^^^^^^^^^^^^^^^^ -The driver's descriptors are provided by the :cpp:type:`tinyusb_config_t` structure's :cpp:member:`descriptor` and :cpp:member:`string_descriptor` members. Therefore, users should initialize :cpp:type:`tinyusb_config_t` to their desired descriptor before calling :cpp:func:`tinyusb_driver_install` to install driver. +The driver's descriptors are provided by :cpp:type:`tinyusb_config_t` structure's :cpp:member:`device_descriptor`, :cpp:member:`configuration_descriptor` and :cpp:member:`string_descriptor` members. Therefore, you should initialize :cpp:type:`tinyusb_config_t` with your desired descriptors before calling :cpp:func:`tinyusb_driver_install` to install the driver. -However, the driver also provides a default descriptor. The driver can be installed with the default descriptor by setting the :cpp:member:`descriptor` and :cpp:member:`string_descriptor` members of :cpp:type:`tinyusb_config_t` to `NULL` before calling :cpp:func:`tinyusb_driver_install`. The driver's default descriptor is specified using Menuconfig, where the following fields should be configured: +However, the driver also provides default descriptors. You can install the driver with default device and string descriptors by setting the :cpp:member:`device_descriptor` and :cpp:member:`string_descriptor` members of :cpp:type:`tinyusb_config_t` to `NULL` before calling :cpp:func:`tinyusb_driver_install`. To lower your development effort we also provide default configuration descriptor for CDC and MSC class, as these classes rarely require custom configuration. The driver's default device descriptor is specified using Menuconfig, where the following fields should be configured: - PID - VID @@ -79,31 +79,32 @@ However, the driver also provides a default descriptor. The driver can be instal - Name of CDC device if it is On - Serial number -If you want to use own descriptors with extended modification, you can define them during the driver installation process +If you want to use your own descriptors with extended modification, you can define them during the driver installation process. Install Driver -------------- To initialize the driver, users should call :cpp:func:`tinyusb_driver_install`. The driver's configuration is specified in a :cpp:type:`tinyusb_config_t` structure that is passed as an argument to :cpp:func:`tinyusb_driver_install`. - Note that the :cpp:type:`tinyusb_config_t` structure can be zero initialized (e.g. ``tinyusb_config_t tusb_cfg = { 0 }``) or partially (as shown below). For any member that is initialized to `0` or `NULL`, the driver will use its default configuration values for that member (see example below) + Note that the :cpp:type:`tinyusb_config_t` structure can be zero initialized (e.g. ``const tinyusb_config_t tusb_cfg = { 0 };``) or partially (as shown below). For any member that is initialized to `0` or `NULL`, the driver will use its default configuration values for that member (see example below) .. code-block:: c - tinyusb_config_t partial_init = { - .descriptor = NULL; //Uses default descriptor specified in Menuconfig - .string_descriptor = NULL; //Uses default string specified in Menuconfig - .external_phy = false; - } + const tinyusb_config_t partial_init = { + .device_descriptor = NULL, // Use default device descriptor specified in Menuconfig + .string_descriptor = NULL, // Use default string descriptors specified in Menuconfig + .external_phy = false, // Use internal USB PHY + .configuration_descriptor = NULL, // Use default configuration descriptor according to settings in Menuconfig + }; USB Serial Device (CDC-ACM) --------------------------- -If the CDC option is enabled in Menuconfig, the USB Serial Device could be initialized with :cpp:func:`tusb_cdc_acm_init` according to the settings from :cpp:type:`tinyusb_config_cdcacm_t` (see example below). +If the CDC option is enabled in Menuconfig, the USB Serial Device can be initialized with :cpp:func:`tusb_cdc_acm_init` according to the settings from :cpp:type:`tinyusb_config_cdcacm_t` (see example below). .. code-block:: c - tinyusb_config_cdcacm_t acm_cfg = { + const tinyusb_config_cdcacm_t acm_cfg = { .usb_dev = TINYUSB_USBDEV_0, .cdc_port = TINYUSB_CDC_ACM_0, .rx_unread_buf_sz = 64, @@ -119,7 +120,7 @@ To specify callbacks you can either set the pointer to your :cpp:type:`tusb_cdca USB Serial Console ^^^^^^^^^^^^^^^^^^ -The driver allows to redirect all standard application strings (stdin/out/err) to the USB Serial Device and return them to UART using :cpp:func:`esp_tusb_init_console`/:cpp:func:`esp_tusb_deinit_console` functions. +The driver allows to redirect all standard application streams (stdinm stdout, stderr) to the USB Serial Device and return them to UART using :cpp:func:`esp_tusb_init_console`/:cpp:func:`esp_tusb_deinit_console` functions. Application Examples @@ -135,12 +136,12 @@ The table below describes the code examples available in the directory :example: - Description * - :example:`peripherals/usb/device/tusb_console` - How to set up {IDF_TARGET_NAME} chip to get log output via Serial Device connection - * - :example:`peripherals/usb/device/tusb_sample_descriptor` - - How to set up {IDF_TARGET_NAME} chip to work as a Generic USB Device with a user-defined descriptor * - :example:`peripherals/usb/device/tusb_serial_device` - How to set up {IDF_TARGET_NAME} chip to work as a USB Serial Device * - :example:`peripherals/usb/device/tusb_midi` - How to set up {IDF_TARGET_NAME} chip to work as a USB MIDI Device + * - :example:`peripherals/usb/device/tusb_hid` + - How to set up {IDF_TARGET_NAME} chip to work as a USB Human Interface Device API Reference diff --git a/docs/en/api-reference/peripherals/usb_host.rst b/docs/en/api-reference/peripherals/usb_host.rst index 169328c57a..4a819ffa66 100644 --- a/docs/en/api-reference/peripherals/usb_host.rst +++ b/docs/en/api-reference/peripherals/usb_host.rst @@ -1,9 +1,6 @@ USB Host ======== -.. warning:: - The USB Host Library API is a beta version thus is subject to change. - The document provides information regarding the USB Host Library. This document is split into the following sections: .. contents:: Sections @@ -365,14 +362,15 @@ The USB Host Stack provides a number examples that implement host class drivers CDC-ACM """"""" -* A host class driver for the Communication Device Class (Abstract Control Model) is currently implemented as an example component (found via :example:`peripherals/usb/host/cdc/common/cdc_acm_host`). +* A host class driver for the Communication Device Class (Abstract Control Model) is deployed to `IDF component registry `__. * The :example:`peripherals/usb/host/cdc/cdc_acm_host` example uses the CDC-ACM host driver component to communicate with CDC-ACM devices * The :example:`peripherals/usb/host/cdc/cdc_acm_bg96` example uses the CDC-ACM host driver component to communicate with non-compliant CDC-ACM devices (i.e., vendor-specific classes that support a subset of CDC-ACM features) such as the Quectel BG96 modem. +* The :example:`peripherals/usb/host/cdc/cdc_acm_vcp` example shows how can you extend the CDC-ACM host driver to interface Virtual COM Port devices. MSC """ -* A host class driver for the Mass Storage Class (Bulk-Only Transport) is current implemented as an example found via :example:`peripherals/usb/host/msc`. +* A host class driver for the Mass Storage Class (Bulk-Only Transport) is deployed to `IDF component registry `__. You can find its example in :example:`peripherals/usb/host/msc`. .. -------------------------------------------------- API Reference ---------------------------------------------------- diff --git a/docs/en/api-reference/protocols/esp_http_client.rst b/docs/en/api-reference/protocols/esp_http_client.rst index fee18b21a9..54ba136c21 100644 --- a/docs/en/api-reference/protocols/esp_http_client.rst +++ b/docs/en/api-reference/protocols/esp_http_client.rst @@ -6,7 +6,7 @@ Overview ``esp_http_client`` provides an API for making HTTP/S requests from ESP-IDF applications. The steps to use this API are as follows: - * :cpp:func:`esp_http_client_init`: Creates an :cpp:type:`esp_http_client_config_t` instance i.e. a HTTP client handle based on the given :cpp:type:`esp_http_client_config_t` configuration. This function must be the first to be called; default values will be assumed for the configuration values that are not explicitly defined by the user. + * :cpp:func:`esp_http_client_init`: Creates an :cpp:type:`esp_http_client_handle_t` instance i.e. a HTTP client handle based on the given :cpp:type:`esp_http_client_config_t` configuration. This function must be the first to be called; default values will be assumed for the configuration values that are not explicitly defined by the user. * :cpp:func:`esp_http_client_perform`: Performs all operations of the esp_http_client - opening the connection, exchanging data and closing the connection (as required), while blocking the current task until its completion. All related events will be invoked through the event handler (as specified in :cpp:type:`esp_http_client_config_t`). * :cpp:func:`esp_http_client_cleanup`: Closes the connection (if any) and frees up all the memory allocated to the HTTP client instance. This must be the last function to be called after the completion of operations. diff --git a/docs/en/api-reference/provisioning/provisioning.rst b/docs/en/api-reference/provisioning/provisioning.rst index 29d136992a..d4f373f943 100644 --- a/docs/en/api-reference/provisioning/provisioning.rst +++ b/docs/en/api-reference/provisioning/provisioning.rst @@ -146,7 +146,6 @@ Security1 scheme details are shown in the below sequence diagram - CLIENT -> CLIENT [label = "Verify Device", rightnote = "check (cli_pubkey == aes_ctr_dec(dev_verify...)"]; } -.. note:: We shall soon migrate to ``Security2 scheme`` as the default scheme in our examples as it provides enhanced security. This change shall be done once we have our phone apps (Android/iOS) upgraded to handle ``Security2 scheme``. Security2 Scheme >>>>>>>>>>>>>>>> diff --git a/docs/en/api-reference/storage/fatfs.rst b/docs/en/api-reference/storage/fatfs.rst index b00691ad76..f9abc95813 100644 --- a/docs/en/api-reference/storage/fatfs.rst +++ b/docs/en/api-reference/storage/fatfs.rst @@ -144,4 +144,4 @@ It is a reverse tool of (:component_file:`fatfsgen.py`), i.e. Usage:: - ./fatfsparse.py [-h] [--long-name-support] [--wear-leveling] fatfs_image.img + ./fatfsparse.py [-h] [--wl-layer {detect,enabled,disabled}] fatfs_image.img diff --git a/docs/en/api-reference/storage/index.rst b/docs/en/api-reference/storage/index.rst index ead81fc6a1..d02dfecb71 100644 --- a/docs/en/api-reference/storage/index.rst +++ b/docs/en/api-reference/storage/index.rst @@ -10,6 +10,7 @@ Storage API mass_mfg.rst nvs_flash nvs_partition_gen.rst + nvs_partition_parse.rst sdmmc spi_flash spiffs diff --git a/docs/en/api-reference/storage/nvs_flash.rst b/docs/en/api-reference/storage/nvs_flash.rst index cdf2004eb5..b5798ec922 100644 --- a/docs/en/api-reference/storage/nvs_flash.rst +++ b/docs/en/api-reference/storage/nvs_flash.rst @@ -46,7 +46,7 @@ Data type check is also performed when reading a value. An error is returned if Namespaces ^^^^^^^^^^ -To mitigate potential conflicts in key names between different components, NVS assigns each key-value pair to one of namespaces. Namespace names follow the same rules as key names, i.e., the maximum length is 15 characters. Namespace name is specified in the :cpp:func:`nvs_open` or :cpp:type:`nvs_open_from_partition` call. This call returns an opaque handle, which is used in subsequent calls to the ``nvs_get_*``, ``nvs_set_*``, and :cpp:func:`nvs_commit` functions. This way, a handle is associated with a namespace, and key names will not collide with same names in other namespaces. Please note that the namespaces with the same name in different NVS partitions are considered as separate namespaces. +To mitigate potential conflicts in key names between different components, NVS assigns each key-value pair to one of namespaces. Namespace names follow the same rules as key names, i.e., the maximum length is 15 characters. Furthermore, there can be no more than 254 different namespaces in one NVS partition. Namespace name is specified in the :cpp:func:`nvs_open` or :cpp:type:`nvs_open_from_partition` call. This call returns an opaque handle, which is used in subsequent calls to the ``nvs_get_*``, ``nvs_set_*``, and :cpp:func:`nvs_commit` functions. This way, a handle is associated with a namespace, and key names will not collide with same names in other namespaces. Please note that the namespaces with the same name in different NVS partitions are considered as separate namespaces. NVS Iterators ^^^^^^^^^^^^^ @@ -82,14 +82,14 @@ Data stored in NVS partitions can be encrypted using AES-XTS in the manner simil The NVS Encryption is enabled by default when :doc:`Flash Encryption <../../security/flash-encryption>` is enabled. This is done because Wi-Fi driver stores credentials (like SSID and passphrase) in the default NVS partition. It is important to encrypt them as default choice if platform level encryption is already enabled. -For using NVS encryption, the partition table must contain the :ref:`nvs_key_partition`. Two partition tables containing the :ref:`nvs_key_partition` are provided for NVS encryption under the partition table option (menuconfig->Partition Table). They can be selected with the project configuration menu (``idf.py menuconfig``). Please refer to the example :example:`security/flash_encryption` for how to configure and use NVS encryption feature. +For using NVS encryption, the partition table must contain the :ref:`nvs_key_partition`. Two partition tables containing the :ref:`nvs_key_partition` are provided for NVS encryption under the partition table option (``menuconfig`` > ``Partition Table``). They can be selected with the project configuration menu (``idf.py menuconfig``). Please refer to the example :example:`security/flash_encryption` for how to configure and use NVS encryption feature. .. _nvs_key_partition: NVS Key Partition ^^^^^^^^^^^^^^^^^ - An application requiring NVS encryption support needs to be compiled with a key-partition of the type `data` and subtype `key`. This partition should be marked as `encrypted` and its size should be the minimum partition size (4KB). Refer to :doc:`Partition Tables <../../api-guides/partition-tables>` for more details. Two additional partition tables which contain the :ref:`nvs_key_partition` are provided under the partition table option (menuconfig->Partition Table). They can be directly used for :ref:`nvs_encryption`. The structure of these partitions is depicted below. +An application requiring NVS encryption support needs to be compiled with a key-partition of the type `data` and subtype `key`. This partition should be marked as `encrypted` and its size should be the minimum partition size (4KB). Refer to :doc:`Partition Tables <../../api-guides/partition-tables>` for more details. Two additional partition tables which contain the :ref:`nvs_key_partition` are provided under the partition table option (``menuconfig`` > ``Partition Table``). They can be directly used for :ref:`nvs_encryption`. The structure of these partitions is depicted below. .. highlight:: none @@ -111,6 +111,11 @@ The XTS encryption keys in the :ref:`nvs_key_partition` can be generated in one The API functions :cpp:func:`nvs_flash_secure_init` and :cpp:func:`nvs_flash_secure_init_partition` do not generate the keys internally. When these API functions are used for initializing encrypted NVS partitions, the keys can be generated after startup using the :cpp:func:`nvs_flash_generate_keys` API function provided by ``nvs_flash.h``. The API function will then write those keys onto the key-partition in encrypted form. + .. note:: Please note that `nvs_keys` partition must be completely erased before starting the application in this approach. Otherwise the application may generate :c:macro:`ESP_ERR_NVS_CORRUPT_KEY_PART` error code assuming that `nvs_keys` partition was not empty and contains malformatted data. You can use the following command for this: + :: + + parttool.py --port PORT --partition-table-file=PARTITION_TABLE_FILE --partition-table-offset PARTITION_TABLE_OFFSET erase_partition --partition-type=data --partition-subtype=nvs_keys + 2. Use pre-generated key partition: This option will be required by the user when keys in the :ref:`nvs_key_partition` are not generated by the application. The :ref:`nvs_key_partition` containing the XTS encryption keys can be generated with the help of :doc:`NVS Partition Generator Utility`. Then the user can store the pre generated key partition on the flash with help of the following two commands: diff --git a/docs/en/api-reference/storage/nvs_partition_parse.rst b/docs/en/api-reference/storage/nvs_partition_parse.rst new file mode 100644 index 0000000000..01a481fc9b --- /dev/null +++ b/docs/en/api-reference/storage/nvs_partition_parse.rst @@ -0,0 +1 @@ +.. include:: /../../components/nvs_flash/nvs_partition_parser/README.rst diff --git a/docs/en/api-reference/storage/spi_flash.rst b/docs/en/api-reference/storage/spi_flash.rst index 6b5de93aea..b55e58e2a9 100644 --- a/docs/en/api-reference/storage/spi_flash.rst +++ b/docs/en/api-reference/storage/spi_flash.rst @@ -153,7 +153,7 @@ Refer to the :doc:`Flash Encryption documentation ` Memory Mapping API ------------------ -{IDF_TARGET_CACHE_SIZE:default="64 KB"} +{IDF_TARGET_CACHE_SIZE:default="64 KB",esp32c2=16~64 KB} {IDF_TARGET_NAME} features memory hardware which allows regions of flash memory to be mapped into instruction and data address spaces. This mapping works only for read operations. It is not possible to modify contents of flash memory by writing to a mapped memory region. @@ -286,4 +286,5 @@ API Reference - Partition Table API Reference - Flash Encrypt ----------------------------- -.. include-build-file:: inc/esp_flash_encrypt.inc \ No newline at end of file +.. include-build-file:: inc/esp_flash_encrypt.inc + \ No newline at end of file diff --git a/docs/en/api-reference/storage/spi_flash_override_driver.rst b/docs/en/api-reference/storage/spi_flash_override_driver.rst index 8f3e7a84b2..c1da0dbc23 100644 --- a/docs/en/api-reference/storage/spi_flash_override_driver.rst +++ b/docs/en/api-reference/storage/spi_flash_override_driver.rst @@ -32,7 +32,7 @@ Steps For Creating Custom Chip Drivers and Overriding the IDF Default Driver Lis 1. Please check whether your flash chip have the capabilities listed in `spi_flash_caps_t` by checking the flash datasheet. 2. Write a function named `spi_flash_chip_***(vendor)_get_caps`. Take the example below as a reference. (if the flash support `suspend` and `read unique id`). - 3. Points the the pointer `get_chip_caps` (in `spi_flash_chip_t`) to the function mentioned above. + 3. Points the pointer `get_chip_caps` (in `spi_flash_chip_t`) to the function mentioned above. .. code-block:: c diff --git a/docs/en/api-reference/storage/spiffs.rst b/docs/en/api-reference/storage/spiffs.rst index 28edf80759..7c040e54a4 100644 --- a/docs/en/api-reference/storage/spiffs.rst +++ b/docs/en/api-reference/storage/spiffs.rst @@ -17,7 +17,7 @@ Notes - SPIFFS is able to reliably utilize only around 75% of assigned partition space. - When the filesystem is running out of space, the garbage collector is trying to find free space by scanning the filesystem multiple times, which can take up to several seconds per write function call, depending on required space. This is caused by the SPIFFS design and the issue has been reported multiple times (e.g. `here `_) and in the official `SPIFFS github repository `_. The issue can be partially mitigated by the `SPIFFS configuration `_. - Deleting a file does not always remove the whole file, which leaves unusable sections throughout the filesystem. - - When ESP32 experiences a power loss during a file system operation it could result in SPIFFS corruption. However the file system still might be recovered via ``esp_spiffs_check`` function. More details in the official SPIFFS `FAQ `. + - When the chip experiences a power loss during a file system operation it could result in SPIFFS corruption. However the file system still might be recovered via ``esp_spiffs_check`` function. More details in the official SPIFFS `FAQ `. Tools ----- diff --git a/docs/en/api-reference/system/app_image_format.rst b/docs/en/api-reference/system/app_image_format.rst index bda9375036..e779759607 100644 --- a/docs/en/api-reference/system/app_image_format.rst +++ b/docs/en/api-reference/system/app_image_format.rst @@ -68,17 +68,19 @@ You can also see the information on segments in the ESP-IDF logs while your appl 3. The image has a single checksum byte after the last segment. This byte is written on a sixteen byte padded boundary, so the application image might need padding. 4. If the ``hash_appended`` field from :cpp:type:`esp_image_header_t` is set then a SHA256 checksum will be appended. The value of SHA256 is calculated on the range from the first byte and up to this field. The length of this field is 32 bytes. -5. If the options :ref:`CONFIG_SECURE_SIGNED_APPS_SCHEME` is set to ECDSA then the application image will have additional 68 bytes for an ECDSA signature, which includes: +5. If the option :ref:`CONFIG_SECURE_SIGNED_APPS_SCHEME` is set to ECDSA then the application image will have an additional 68 bytes for an ECDSA signature, which includes: * version word (4 bytes), * signature data (64 bytes). +6. If the option :ref:`CONFIG_SECURE_SIGNED_APPS_SCHEME` is set to RSA or ECDSA (V2) then the application image will have an additional signature sector of 4K size. For more details on the format of this signature sector, please refer to :ref:`signature-block-format`. + .. _app_image_format_application_description: Application Description ----------------------- -The ``DROM`` segment starts with the :cpp:type:`esp_app_desc_t` structure which carries specific fields describing the application: +The ``DROM`` segment of the application binary starts with the :cpp:type:`esp_app_desc_t` structure which carries specific fields describing the application: * ``magic_word`` - the magic word for the esp_app_desc structure. * ``secure_version`` - see :doc:`Anti-rollback`. @@ -86,12 +88,17 @@ The ``DROM`` segment starts with the :cpp:type:`esp_app_desc_t` structure which * ``project_name`` is filled from ``PROJECT_NAME``. ``*`` * ``time`` and ``date`` - compile time and date. * ``idf_ver`` - version of ESP-IDF. ``*`` - * ``app_elf_sha256`` - contains sha256 for the elf application file. + * ``app_elf_sha256`` - contains sha256 for the application ELF file. -``*`` - The maximum length is 32 characters, including null-termination character. For example, if the length of ``PROJECT_NAME`` exceeds 32 characters, the excess characters will be disregarded. +``*`` - The maximum length is 32 characters, including null-termination character. For example, if the length of ``PROJECT_NAME`` exceeds 31 characters, the excess characters will be disregarded. This structure is useful for identification of images uploaded OTA because it has a fixed offset = sizeof(:cpp:type:`esp_image_header_t`) + sizeof(:cpp:type:`esp_image_segment_header_t`). As soon as a device receives the first fragment containing this structure, it has all the information to determine whether the update should be continued or not. +To obtain the :cpp:type:`esp_app_desc_t` structure for the currently running application, use :cpp:func:`esp_app_get_description`. + +To obtain the :cpp:type:`esp_app_desc_t` structure for another OTA partition, use :cpp:func:`esp_ota_get_partition_description`. + + Adding a Custom Structure to an Application ------------------------------------------- diff --git a/docs/en/api-reference/system/async_memcpy.rst b/docs/en/api-reference/system/async_memcpy.rst index c04592db6e..d5a4813571 100644 --- a/docs/en/api-reference/system/async_memcpy.rst +++ b/docs/en/api-reference/system/async_memcpy.rst @@ -44,29 +44,30 @@ Send memory copy request :cpp:func:`esp_async_memcpy` is the API to send memory copy request to DMA engine. It must be called after driver is installed successfully. This API is thread safe, so it can be called from different tasks. -Different from the libc version of `memcpy`, user should also pass a callback to :cpp:func:`esp_async_memcpy`, if it's necessary to be notified when the memory copy is done. The callback is executed in the ISR context, make sure you won't violate the the restriction applied to ISR handler. +Different from the libc version of ``memcpy``, user should also pass a callback to :cpp:func:`esp_async_memcpy`, if it's necessary to be notified when the memory copy is done. The callback is executed in the ISR context, make sure you won't violate the restriction applied to ISR handler. -Besides that, the callback function should reside in IRAM space by applying `IRAM_ATTR` attribute. The prototype of the callback function is :cpp:type:`async_memcpy_isr_cb_t`, please note that, the callback function should return true if it wakes up a high priority task by some API like :cpp:func:`xSemaphoreGiveFromISR`. +Besides that, the callback function should reside in IRAM space by applying ``IRAM_ATTR`` attribute. The prototype of the callback function is :cpp:type:`async_memcpy_isr_cb_t`, please note that, the callback function should return true if it wakes up a high priority task by some API like :cpp:func:`xSemaphoreGiveFromISR`. .. highlight:: c :: - Semphr_Handle_t semphr; //already initialized in somewhere - // Callback implementation, running in ISR context static IRAM_ATTR bool my_async_memcpy_cb(async_memcpy_t mcp_hdl, async_memcpy_event_t *event, void *cb_args) { SemaphoreHandle_t sem = (SemaphoreHandle_t)cb_args; BaseType_t high_task_wakeup = pdFALSE; - SemphrGiveInISR(semphr, &high_task_wakeup); // high_task_wakeup set to pdTRUE if some high priority task unblocked + xSemaphoreGiveFromISR(semphr, &high_task_wakeup); // high_task_wakeup set to pdTRUE if some high priority task unblocked return high_task_wakeup == pdTRUE; } + // Create a semaphore used to report the completion of async memcpy + SemaphoreHandle_t semphr = xSemaphoreCreateBinary(); + // Called from user's context ESP_ERROR_CHECK(esp_async_memcpy(driver_handle, to, from, copy_len, my_async_memcpy_cb, my_semaphore)); - //Do something else here - SemphrTake(my_semaphore, ...); //wait until the buffer copy is done + // Do something else here + xSemaphoreTake(my_semaphore, portMAX_DELAY); // Wait until the buffer copy is done Uninstall driver (optional) --------------------------- diff --git a/docs/en/api-reference/system/inc/power_management_esp32.rst b/docs/en/api-reference/system/inc/power_management_esp32.rst index d4f3512363..6a91d2026f 100644 --- a/docs/en/api-reference/system/inc/power_management_esp32.rst +++ b/docs/en/api-reference/system/inc/power_management_esp32.rst @@ -1,5 +1,5 @@ +---------------+---------------------------------------+-------------------------------------+ -| Max CPU | Lock Acquisition | CPU and APB Frequncies | +| Max CPU | Lock Acquisition | CPU and APB Frequencies | | Frequency Set | | | +---------------+---------------------------------------+-------------------------------------+ | 240 | | Any of ``ESP_PM_CPU_FREQ_MAX`` | | diff --git a/docs/en/api-reference/system/inc/power_management_esp32s2_and_later.rst b/docs/en/api-reference/system/inc/power_management_esp32s2_and_later.rst index b9e846342a..cbb78544d5 100644 --- a/docs/en/api-reference/system/inc/power_management_esp32s2_and_later.rst +++ b/docs/en/api-reference/system/inc/power_management_esp32s2_and_later.rst @@ -1,27 +1,29 @@ +{IDF_TARGET_APB_FREQ: default="80 Mhz", esp32c2="40 MHz"} + +---------------+---------------------------------------+-------------------------------------+ -| Max CPU | Lock Acquisition | CPU and APB Frequncies | +| Max CPU | Lock Acquisition | CPU and APB Frequencies | | Frequency Set | | | +---------------+---------------------------------------+-------------------------------------+ | 240 | ``ESP_PM_CPU_FREQ_MAX`` acquired | | CPU: 240 MHz | -| | | | APB: 80 MHz | +| | | | APB: {IDF_TARGET_APB_FREQ} | + +---------------------------------------+-------------------------------------+ | | ``ESP_PM_APB_FREQ_MAX`` acquired, | | CPU: 80 MHz | -| | ``ESP_PM_CPU_FREQ_MAX`` not acquired | | APB: 80 MHz | +| | ``ESP_PM_CPU_FREQ_MAX`` not acquired | | APB: {IDF_TARGET_APB_FREQ} | + +---------------------------------------+-------------------------------------+ | | None | Min values for both frequencies set | | | | with :cpp:func:`esp_pm_configure` | +---------------+---------------------------------------+-------------------------------------+ | 160 | ``ESP_PM_CPU_FREQ_MAX`` acquired | | CPU: 160 MHz | -| | | | APB: 80 MHz | +| | | | APB: {IDF_TARGET_APB_FREQ} | + +---------------------------------------+-------------------------------------+ | | ``ESP_PM_APB_FREQ_MAX`` acquired, | | CPU: 80 MHz | -| | ``ESP_PM_CPU_FREQ_MAX`` not acquired | | APB: 80 MHz | +| | ``ESP_PM_CPU_FREQ_MAX`` not acquired | | APB: {IDF_TARGET_APB_FREQ} | + +---------------------------------------+-------------------------------------+ | | None | Min values for both frequencies set | | | | with :cpp:func:`esp_pm_configure` | +---------------+---------------------------------------+-------------------------------------+ | 80 | | Any of ``ESP_PM_CPU_FREQ_MAX`` | | CPU: 80 MHz | -| | | or ``ESP_PM_APB_FREQ_MAX`` acquired | | APB: 80 MHz | +| | | or ``ESP_PM_APB_FREQ_MAX`` acquired | | APB: {IDF_TARGET_APB_FREQ} | + +---------------------------------------+-------------------------------------+ | | None | Min values for both frequencies set | | | | with :cpp:func:`esp_pm_configure` | diff --git a/docs/en/api-reference/system/mem_alloc.rst b/docs/en/api-reference/system/mem_alloc.rst index d757273ede..86d2c3267b 100644 --- a/docs/en/api-reference/system/mem_alloc.rst +++ b/docs/en/api-reference/system/mem_alloc.rst @@ -30,7 +30,9 @@ For more details on these internal memory types, see :ref:`memory-layout`. It's also possible to connect external SPI RAM to the {IDF_TARGET_NAME} - :doc:`external RAM ` can be integrated into the {IDF_TARGET_NAME}'s memory map using the flash cache, and accessed similarly to DRAM. -DRAM uses capability ``MALLOC_CAP_8BIT`` (accessible in single byte reads and writes). When calling ``malloc()``, the ESP-IDF ``malloc()`` implementation internally calls ``heap_caps_malloc(size, MALLOC_CAP_8BIT)`` in order to allocate DRAM that is byte-addressable. To test the free DRAM heap size at runtime, call cpp:func:`heap_caps_get_free_size(MALLOC_CAP_8BIT)`. +DRAM uses capability ``MALLOC_CAP_8BIT`` (accessible in single byte reads and writes). To test the free DRAM heap size at runtime, call cpp:func:`heap_caps_get_free_size(MALLOC_CAP_8BIT)`. + +When calling ``malloc()``, the ESP-IDF ``malloc()`` implementation internally calls cpp:func:`heap_caps_malloc_default(size)`. This will allocate memory with capability ``MALLOC_CAP_DEFAULT``, which is byte-addressable. Because malloc uses the capabilities-based allocation system, memory allocated using :cpp:func:`heap_caps_malloc` can be freed by calling the standard ``free()`` function. @@ -119,14 +121,8 @@ generate a fatal LoadStoreError exception. To use the region above the 4MiB limit, you can use the :doc:`himem API`. - -API Reference - Heap Allocation -------------------------------- - -.. include-build-file:: inc/esp_heap_caps.inc - Thread Safety -^^^^^^^^^^^^^ +------------- Heap functions are thread safe, meaning they can be called from different tasks simultaneously without any limitations. @@ -141,11 +137,6 @@ The following features are documented on the :doc:`Heap Memory Debugging ` - :ref:`Heap Tracing ` (memory leak detection, monitoring, etc.) -API Reference - Initialisation ------------------------------- - -.. include-build-file:: inc/esp_heap_caps_init.inc - Implementation Notes -------------------- @@ -157,6 +148,18 @@ The heap capabilities allocator uses knowledge of the memory regions to initiali Calling ``free()`` involves finding the particular heap corresponding to the freed address, and then calling :cpp:func:`multi_heap_free` on that particular multi_heap instance. + +API Reference - Heap Allocation +------------------------------- + +.. include-build-file:: inc/esp_heap_caps.inc + + +API Reference - Initialisation +------------------------------ + +.. include-build-file:: inc/esp_heap_caps_init.inc + .. _multi-heap: API Reference - Multi Heap API diff --git a/docs/en/api-reference/system/misc_system_api.rst b/docs/en/api-reference/system/misc_system_api.rst index 25c5cd78c4..9a53942c0e 100644 --- a/docs/en/api-reference/system/misc_system_api.rst +++ b/docs/en/api-reference/system/misc_system_api.rst @@ -211,7 +211,7 @@ The application version is stored in :cpp:class:`esp_app_desc_t` structure. It i To set the version in your project manually, you need to set the ``PROJECT_VER`` variable in the ``CMakeLists.txt`` of your project. In application ``CMakeLists.txt``, put ``set(PROJECT_VER "0.1.0.1")`` before including ``project.cmake``. -If the :ref:`CONFIG_APP_PROJECT_VER_FROM_CONFIG` option is set, the value of :ref:`CONFIG_APP_PROJECT_VER` will be used. Otherwise, if the ``PROJECT_VER`` variable is not set in the project, it will be retrieved either from the ``$(PROJECT_PATH)/version.txt`` file (if present) or using git command ``git describe``. If neither is available, ``PROJECT_VER`` will be set to "1". Application can make use of this by calling :cpp:func:`esp_ota_get_app_description` or :cpp:func:`esp_ota_get_partition_description` functions. +If the :ref:`CONFIG_APP_PROJECT_VER_FROM_CONFIG` option is set, the value of :ref:`CONFIG_APP_PROJECT_VER` will be used. Otherwise, if the ``PROJECT_VER`` variable is not set in the project, it will be retrieved either from the ``$(PROJECT_PATH)/version.txt`` file (if present) or using git command ``git describe``. If neither is available, ``PROJECT_VER`` will be set to "1". Application can make use of this by calling :cpp:func:`esp_app_get_description` or :cpp:func:`esp_ota_get_partition_description` functions. API Reference ------------- @@ -221,3 +221,4 @@ API Reference .. include-build-file:: inc/esp_mac.inc .. include-build-file:: inc/esp_chip_info.inc .. include-build-file:: inc/esp_cpu.inc +.. include-build-file:: inc/esp_app_desc.inc diff --git a/docs/en/api-reference/system/sleep_modes.rst b/docs/en/api-reference/system/sleep_modes.rst index ace78939b7..792038c1ee 100644 --- a/docs/en/api-reference/system/sleep_modes.rst +++ b/docs/en/api-reference/system/sleep_modes.rst @@ -16,9 +16,8 @@ In Deep-sleep mode, the CPUs, most of the RAM, and all digital peripherals that .. list:: - RTC controller - - RTC peripherals :SOC_ULP_SUPPORTED: - ULP coprocessor - - RTC fast memory + :SOC_RTC_FAST_MEM_SUPPORTED: - RTC fast memory :SOC_RTC_SLOW_MEM_SUPPORTED: - RTC slow memory There are several wakeup sources in Deep-sleep and Light-sleep modes. These sources can also be combined so that the chip will wake up when any of the sources are triggered. Wakeup sources can be enabled using ``esp_sleep_enable_X_wakeup`` APIs and can be disabled using :cpp:func:`esp_sleep_disable_wakeup_source` API. Next section describes these APIs in detail. Wakeup sources can be configured at any moment before entering Light-sleep or Deep-sleep mode. @@ -164,7 +163,7 @@ By default, :cpp:func:`esp_deep_sleep_start` and :cpp:func:`esp_light_sleep_star If some variables in the program are placed into RTC slow memory (for example, using ``RTC_DATA_ATTR`` attribute), RTC slow memory will be kept powered on by default. This can be overridden using :cpp:func:`esp_sleep_pd_config` function, if desired. -.. only:: not SOC_RTC_SLOW_MEM_SUPPORTED +.. only:: not SOC_RTC_SLOW_MEM_SUPPORTED and SOC_RTC_FAST_MEM_SUPPORTED In {IDF_TARGET_NAME}, there is only RTC fast memory, so if some variables in the program are marked by ``RTC_DATA_ATTR``, ``RTC_SLOW_ATTR`` or ``RTC_FAST_ATTR`` attributes, all of them go to RTC fast memory. It will be kept powered on by default. This can be overridden using :cpp:func:`esp_sleep_pd_config` function, if desired. @@ -213,7 +212,7 @@ Configuring IOs Some {IDF_TARGET_NAME} IOs have internal pullups or pulldowns, which are enabled by default. If an external circuit drives this pin in Deep-sleep mode, current consumption may increase due to current flowing through these pullups and pulldowns. -.. only:: not esp32c3 +.. only:: SOC_RTCIO_HOLD_SUPPORTED To isolate a pin to prevent extra current draw, call :cpp:func:`rtc_gpio_isolate` function. @@ -223,7 +222,7 @@ Some {IDF_TARGET_NAME} IOs have internal pullups or pulldowns, which are enabled rtc_gpio_isolate(GPIO_NUM_12); -.. only:: esp32c3 +.. only:: esp32c2 or esp32c3 In Deep-sleep mode: - digital GPIOs (GPIO6 ~ 21) are in a high impedance state. @@ -267,7 +266,7 @@ Application Example - :example:`system/deep_sleep`: the usage of various Deep-sleep wakeup triggers and ULP coprocessor programming. -.. only:: esp32c3 +.. only:: esp32c3 or esp32c2 - :example:`system/deep_sleep`: the usage of Deep-sleep wakeup triggered by timer. diff --git a/docs/en/api-reference/system/ulp-risc-v.rst b/docs/en/api-reference/system/ulp-risc-v.rst index a3088a0954..124e530e0e 100644 --- a/docs/en/api-reference/system/ulp-risc-v.rst +++ b/docs/en/api-reference/system/ulp-risc-v.rst @@ -35,7 +35,7 @@ To compile the ULP RISC-V code as part of the component, the following steps mus The first argument to ``ulp_embed_binary`` specifies the ULP binary name. The name specified here will also be used by other generated artifacts such as the ELF file, map file, header file and linker export file. The second argument specifies the ULP source files. Finally, the third argument specifies the list of component source files which include the header file to be generated. This list is needed to build the dependencies correctly and ensure that the generated header file will be created before any of these files are compiled. See the section below for the concept of generated header files for ULP applications. -3. Build the application as usual (e.g. `idf.py app`). +3. Build the application as usual (e.g., `idf.py app`). Inside, the build system will take the following steps to build ULP program: @@ -98,6 +98,18 @@ To access the ULP RISC-V program variables from the main program, the generated ulp_measurement_count = 64; } +Mutual Exclusion +^^^^^^^^^^^^^^^^ + +If mutual exclusion is needed when accessing a variable shared between the main program and ULP, then this can be achieved by using the ULP RISC-V lock API: + + * :cpp:func:`ulp_riscv_lock_acquire` + * :cpp:func:`ulp_riscv_lock_release` + +The ULP does not have any hardware instructions to facilitate mutual exclusion, so the lock API achieves this through a software algorithm (`Peterson's algorithm `_). + +The locks are intended to only be called from a single thread in the main program, and will not provide mutual exclusion if used simultaneously from multiple threads. + Starting the ULP RISC-V Program ------------------------------- @@ -142,24 +154,26 @@ To disable the timer (effectively preventing the ULP program from running again) Debugging Your ULP RISC-V Program ---------------------------------- -When programming the ULP RISC-V it can sometimes be challenging to figure out why the program is not behaving as expected. Due to the simplicity of the core many of the standard methods of debugging, e.g. JTAG or ``printf``, are simply not available. +When programming the ULP RISC-V, it can sometimes be challenging to figure out why the program is not behaving as expected. Due to the simplicity of the core, many of the standard methods of debugging, e.g., JTAG or ``printf``, are simply not available. Keeping this in mind, here are some ways that may help you debug you ULP RISC-V program: * Share program state through shared variables: as described in :ref:`ulp-riscv-access-variables`, both the main CPU and the ULP core can easily access global variables in RTC memory. Writing state information to such a variable from the ULP and reading it from the main CPU can help you discern what is happening on the ULP core. The downside of this approach is that it requires the main CPU to be awake, which will not always be the case. Keeping the main CPU awake might even, in some cases, mask problems, as some issues may only occur when certain power domains are powered down. - * Printing using the bit-banged UART driver: the ULP RISC-V component comes with a low-speed bit-banged UART TX driver that can be used for printing information independently of the main CPU state. See :example:`system/ulp_riscv/uart_print` for an example of how to use this driver. - * Trap signal: the ULP RISC-V has a hardware trap that will trigger under certain conditions, e.g. illegal instruction. This will cause the main CPU to be woken up with the wake-up cause :cpp:enumerator:`ESP_SLEEP_WAKEUP_COCPU_TRAP_TRIG`. + * Use the bit-banged UART driver to print: the ULP RISC-V component comes with a low-speed bit-banged UART TX driver that can be used for printing information independently of the main CPU state. See :example:`system/ulp_riscv/uart_print` for an example of how to use this driver. + * Trap signal: the ULP RISC-V has a hardware trap that will trigger under certain conditions, e.g., illegal instruction. This will cause the main CPU to be woken up with the wake-up cause :cpp:enumerator:`ESP_SLEEP_WAKEUP_COCPU_TRAP_TRIG`. Application Examples -------------------- * ULP RISC-V Coprocessor polls GPIO while main CPU is in deep sleep: :example:`system/ulp_riscv/gpio`. -* ULP RISC-V Coprocessor uses bit-banged UART tx to print: :example:`system/ulp_riscv/uart_print`. +* ULP RISC-V Coprocessor uses bit-banged UART driver to print: :example:`system/ulp_riscv/uart_print`. * ULP RISC-V Coprocessor reads external temperature sensor while main CPU is in deep sleep: :example:`system/ulp_riscv/ds18b20_onewire`. API Reference ------------- .. include-build-file:: inc/ulp_riscv.inc +.. include-build-file:: inc/ulp_riscv_lock_shared.inc +.. include-build-file:: inc/ulp_riscv_lock.inc diff --git a/docs/en/api-reference/system/ulp.rst b/docs/en/api-reference/system/ulp.rst index 6349bf2e42..665b5176a0 100644 --- a/docs/en/api-reference/system/ulp.rst +++ b/docs/en/api-reference/system/ulp.rst @@ -184,4 +184,4 @@ API Reference .. include-build-file:: inc/ulp_common.inc .. include-build-file:: inc/ulp_common_defs.inc -.. _binutils-esp32ulp toolchain: https://github.com/espressif/binutils-esp32ulp +.. _binutils-esp32ulp toolchain: https://github.com/espressif/binutils-gdb diff --git a/docs/en/api-reference/system/ulp_instruction_set.rst b/docs/en/api-reference/system/ulp_instruction_set.rst index a064bbfc88..abe268a9f3 100644 --- a/docs/en/api-reference/system/ulp_instruction_set.rst +++ b/docs/en/api-reference/system/ulp_instruction_set.rst @@ -281,6 +281,9 @@ The detailed description of all instructions is presented below: **Description** The instruction does a logical shift to left of the source register by the number of bits from another source register or a 16-bit signed value and stores the result to the destination register. +.. note:: + Shift operations which are greater than 15 bits will have an undefined result. + **Examples**:: 1: LSH R1, R2, R3 // R1 = R2 << R3 @@ -316,6 +319,9 @@ The detailed description of all instructions is presented below: **Description** The instruction does a logical shift to right of a source register by the number of bits from another source register or a 16-bit signed value and stores the result to the destination register. +.. note:: + Shift operations which are greater than 15 bits will have an undefined result. + **Examples**:: 1: RSH R1, R2, R3 // R1 = R2 >> R3 @@ -979,7 +985,8 @@ The detailed description of all instructions is presented below: - If the SoC is not in deep sleep mode, and ULP interrupt bit (RTC_CNTL_ULP_CP_INT_ENA) is set in RTC_CNTL_INT_ENA_REG register, RTC interrupt will be triggered. - Note that before using WAKE instruction, ULP program may needs to wait until RTC controller is ready to wake up the main CPU. This is indicated using RTC_CNTL_RDY_FOR_WAKEUP bit of RTC_CNTL_LOW_POWER_ST_REG register. If WAKE instruction is executed while RTC_CNTL_RDY_FOR_WAKEUP is zero, it has no effect (wake up does not occur). +.. note:: + Note that before using WAKE instruction, ULP program may need to wait until RTC controller is ready to wake up the main CPU. This is indicated using RTC_CNTL_RDY_FOR_WAKEUP bit of RTC_CNTL_LOW_POWER_ST_REG register. If WAKE instruction is executed while RTC_CNTL_RDY_FOR_WAKEUP is zero, it has no effect (wake up does not occur). If the WAKE instruction is intended to be used while the main CPU is not in sleep mode then the RTC_CNTL_MAIN_STATE_IN_IDLE (bit 27) of RTC_CNTL_LOW_POWER_ST_REG can be used to check whether main CPU is in normal mode or sleep mode. **Examples**:: @@ -993,6 +1000,15 @@ The detailed description of all instructions is presented below: // After these instructions, SoC will wake up, // and ULP will not run again until started by the main program. + 1: check_wakeup: // Read RTC_CNTL_RDY_FOR_WAKEUP and RTC_CNTL_MAIN_STATE_IN_IDLE bit + READ_RTC_REG(RTC_CNTL_LOW_POWER_ST_REG, 27, 0) + MOVE r1, r0 // Copy result in to r1 + READ_RTC_FIELD(RTC_CNTL_LOW_POWER_ST_REG, RTC_CNTL_RDY_FOR_WAKEUP) + OR r0, r0, r1 + JUMP check_wakeup, eq // Retry until either of the bit are set + WAKE // Trigger wake up + HALT // Stop the ULP program + .. only:: esp32 @@ -1209,7 +1225,7 @@ The detailed description of all instructions is presented below: .. only:: esp32s2 or esp32s3 - This instruction can access registers in RTC_CNTL, RTC_IO, SENS, and RTC_I2C peripherals. Address of the the register, as seen from the ULP, can be calculated from the address of the same register on the PeriBUS1 as follows:: + This instruction can access registers in RTC_CNTL, RTC_IO, SENS, and RTC_I2C peripherals. Address of the register, as seen from the ULP, can be calculated from the address of the same register on the PeriBUS1 as follows:: addr_ulp = (addr_peribus1 - DR_REG_RTCCNTL_BASE) / 4 diff --git a/docs/en/api-reference/system/ulp_macros.rst b/docs/en/api-reference/system/ulp_macros.rst index 22a5b5eb2b..150f2a2921 100644 --- a/docs/en/api-reference/system/ulp_macros.rst +++ b/docs/en/api-reference/system/ulp_macros.rst @@ -28,7 +28,7 @@ The ``program`` array is an array of ``ulp_insn_t``, i.e. ULP coprocessor instru To generate branch instructions, special ``M_`` preprocessor defines are used. ``M_LABEL`` define can be used to define a branch target. Label identifier is a 16-bit integer. ``M_Bxxx`` defines can be used to generate branch instructions with target set to a particular label. -Implementation note: these ``M_`` preprocessor defines will be translated into two ulp_insn_t values: one is a token value which contains label number, and the other is the actual instruction. ``ulp_process_macros_and_load`` function resolves the label number to the address, modifies the branch instruction to use the correct address, and removes the the extra ``ulp_insn_t`` token which contains the label numer. +Implementation note: these ``M_`` preprocessor defines will be translated into two ulp_insn_t values: one is a token value which contains label number, and the other is the actual instruction. ``ulp_process_macros_and_load`` function resolves the label number to the address, modifies the branch instruction to use the correct address, and removes the extra ``ulp_insn_t`` token which contains the label numer. Here is an example of using labels and branches:: diff --git a/docs/en/api-reference/system/wdts.rst b/docs/en/api-reference/system/wdts.rst index f8e536cc0c..40c42cf8a2 100644 --- a/docs/en/api-reference/system/wdts.rst +++ b/docs/en/api-reference/system/wdts.rst @@ -19,13 +19,15 @@ The various watchdog timers can be enabled using the :ref:`project-configuration Interrupt Watchdog Timer (IWDT) ------------------------------- +{IDF_IWDT_TIMER_GROUP:default="Timer Group 1", esp32c2="Timer Group 0"} + The purpose of the IWDT is to ensure that interrupt service routines (ISRs) are not blocked from running for a prolonged period of time (i.e., the IWDT timeout period). Blocking ISRs from running in a timely manner is undesirable as it can increases ISR latency, and also prevents task switching (as task switching is executed form an ISR). The things that can block ISRs from running include: - Disabling interrupts - Critical Sections (also disables interrupts) - Other same/higher priority ISRs (will block same/lower priority ISRs from running it completes execution) -The IWDT utilizes the watchdog timer in Timer Group 1 as its underlying hardware timer and leverages the FreeRTOS tick interrupt on each CPU to feed the watchdog timer. If the tick interrupt on a particular CPU is not run at within the IWDT timeout period, it is indicative that something is blocking ISRs from being run on that CPU (see the list of reasons above). +The IWDT utilizes the watchdog timer in {IDF_IWDT_TIMER_GROUP} as its underlying hardware timer and leverages the FreeRTOS tick interrupt on each CPU to feed the watchdog timer. If the tick interrupt on a particular CPU is not run at within the IWDT timeout period, it is indicative that something is blocking ISRs from being run on that CPU (see the list of reasons above). When the IWDT times out, the default action is to invoke the panic handler and display the panic reason as ``Interrupt wdt timeout on CPU0`` or ``Interrupt wdt timeout on CPU1`` (as applicable). Depending on the panic handler's configured behavior (see :ref:`CONFIG_ESP_SYSTEM_PANIC`), users can then debug the source of the IWDT timeout (via the backtrace, OpenOCD, gdbstub etc) or simply reset the chip (which may be preferred in a production environment). @@ -59,7 +61,13 @@ Task Watchdog Timer (TWDT) The Task Watchdog Timer (TWDT) is used to monitor particular tasks, ensuring that they are able to execute within a given timeout period. The TWDT primarily watches the {IDF_TARGET_IDLE_TASKS}, however any task can subscribe to be watched by the TWDT. By watching the {IDF_TARGET_IDLE_TASKS}, the TWDT can detect instances of tasks running for a prolonged period of time wihtout yielding. This can be an indicator of poorly written code that spinloops on a peripheral, or a task that is stuck in an infinite loop. -The TWDT is built around the Hardware Watchdog Timer in Timer Group 0. When a timeout occurs, an interrupt is triggered. Users can redefine the function `esp_task_wdt_isr_user_handler` in the user code, in order to receive the timeout event and handle it differently. +.. only:: not esp32c2 + + The TWDT is built around the Hardware Watchdog Timer in Timer Group 0. When a timeout occurs, an interrupt is triggered. Users can define the function `esp_task_wdt_isr_user_handler` in the user code, in order to receive the timeout event and extend the default behavior. + +.. only:: esp32c2 + + The {IDF_TARGET_NAME} has only a single Timer Group, used by Interrupt Watchdog (IWDT). Thus, the Task Watchdog is built around the `esp_timer` component in order to implement a software timer. When a timeout occurs, an interrupt is triggered, notifying the `esp_timer`'s main task. The later will then execute the TWDT callback previously registered. Users can define the function `esp_task_wdt_isr_user_handler` in the user code, in order to receive the timeout event and extend the default behavior. Usage ^^^^^ @@ -93,13 +101,14 @@ The default timeout period for the TWDT is set using config item :ref:`CONFIG_ES For more information, you can refer to :doc:`SPI Flash <../storage/spi_flash>`. -The following config options control TWDT configuration at startup. They are all enabled by default: +The following config options control TWDT configuration. They are all enabled by default: {IDF_TARGET_IDLE_TASK:default="Idle task", esp32="CPU0 Idle task", esp32s3="CPU0 Idle task"} .. list:: - - :ref:`CONFIG_ESP_TASK_WDT` - the TWDT is initialized automatically during startup. If this option is disabled, it is still possible to initialize the Task WDT at runtime by calling :cpp:func:`esp_task_wdt_init`. + - :ref:`CONFIG_ESP_TASK_WDT_EN` - enables TWDT feature. If this option is disabled, TWDT cannot be used, even if initialized at runtime. + - :ref:`CONFIG_ESP_TASK_WDT_INIT` - the TWDT is initialized automatically during startup. If this option is disabled, it is still possible to initialize the Task WDT at runtime by calling :cpp:func:`esp_task_wdt_init`. - :ref:`CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0` - {IDF_TARGET_IDLE_TASK} is subscribed to the TWDT during startup. If this option is disabled, it is still possible to subscribe the idle task by calling :cpp:func:`esp_task_wdt_init` again. :not CONFIG_FREERTOS_UNICORE: - :ref:`CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1` - CPU1 Idle task is subscribed to the TWDT during startup. diff --git a/docs/en/api-reference/template.rst b/docs/en/api-reference/template.rst index d4929f0af9..7eb70fac43 100644 --- a/docs/en/api-reference/template.rst +++ b/docs/en/api-reference/template.rst @@ -61,9 +61,9 @@ API Reference 1. This repository provides for automatic update of API reference documentation using :doc:`code markup retrieved by Doxygen from header files <../contribute/documenting-code>`. - 1. Update is done on each documentation build by invoking Sphinx extension :`esp_extensions/run_doxygen.py` for all header files listed in the ``INPUT`` statement of :idf_file:`docs/doxygen/Doxyfile`. + 2. Update is done on each documentation build by invoking Sphinx extension :`esp_extensions/run_doxygen.py` for all header files listed in the ``INPUT`` statement of :idf_file:`docs/doxygen/Doxyfile`. - 1. Each line of the ``INPUT`` statement (other than a comment that begins with ``##``) contains a path to header file ``*.h`` that will be used to generate corresponding ``*.inc`` files:: + 3. Each line of the ``INPUT`` statement (other than a comment that begins with ``##``) contains a path to header file ``*.h`` that will be used to generate corresponding ``*.inc`` files:: ## ## Wi-Fi - API Reference @@ -71,17 +71,17 @@ API Reference ../components/esp32/include/esp_wifi.h \ ../components/esp32/include/esp_smartconfig.h \ - 1. When the headers are expanded, any macros defined by default in ``sdkconfig.h`` as well as any macros defined in SOC-specific ``include/soc/*_caps.h`` headers will be expanded. This allows the headers to include/exclude material based on the ``IDF_TARGET`` value. + 4. When the headers are expanded, any macros defined by default in ``sdkconfig.h`` as well as any macros defined in SOC-specific ``include/soc/*_caps.h`` headers will be expanded. This allows the headers to include/exclude material based on the ``IDF_TARGET`` value. - 1. The ``*.inc`` files contain formatted reference of API members generated automatically on each documentation build. All ``*.inc`` files are placed in Sphinx ``_build`` directory. To see directives generated for e.g. ``esp_wifi.h``, run ``python gen-dxd.py esp32/include/esp_wifi.h``. + 5. The ``*.inc`` files contain formatted reference of API members generated automatically on each documentation build. All ``*.inc`` files are placed in Sphinx ``_build`` directory. To see directives generated for e.g. ``esp_wifi.h``, run ``python gen-dxd.py esp32/include/esp_wifi.h``. - 1. To show contents of ``*.inc`` file in documentation, include it as follows:: + 6. To show contents of ``*.inc`` file in documentation, include it as follows:: .. include-build-file:: inc/esp_wifi.inc For example see :idf_file:`docs/en/api-reference/network/esp_wifi.rst` - 1. Optionally, rather that using ``*.inc`` files, you may want to describe API in you own way. See :idf_file:`docs/en/api-reference/storage/fatfs.rst` for example. + 7. Optionally, rather that using ``*.inc`` files, you may want to describe API in you own way. See :idf_file:`docs/en/api-reference/storage/fatfs.rst` for example. Below is the list of common ``.. doxygen...::`` directives: @@ -98,6 +98,6 @@ API Reference * :component_file:`path_to/header_file.h` - 1. In any case, to generate API reference, the file :idf_file:`docs/doxygen/Doxyfile` should be updated with paths to ``*.h`` headers that are being documented. + 8. In any case, to generate API reference, the file :idf_file:`docs/doxygen/Doxyfile` should be updated with paths to ``*.h`` headers that are being documented. - 1. When changes are committed and documentation is build, check how this section has been rendered. :doc:`Correct annotations <../contribute/documenting-code>` in respective header files, if required. + 9. When changes are committed and documentation is build, check how this section has been rendered. :doc:`Correct annotations <../contribute/documenting-code>` in respective header files, if required. diff --git a/docs/en/contribute/esp-idf-tests-with-pytest.rst b/docs/en/contribute/esp-idf-tests-with-pytest.rst index d7cbc69f81..7f5eab1e5c 100644 --- a/docs/en/contribute/esp-idf-tests-with-pytest.rst +++ b/docs/en/contribute/esp-idf-tests-with-pytest.rst @@ -270,8 +270,6 @@ Advanced Examples Multi Dut Tests with the Same App """"""""""""""""""""""""""""""""" -This code example is taken from :idf_file:`pytest_usb_host.py `. - .. code:: python @pytest.mark.esp32s2 diff --git a/docs/en/get-started/establish-serial-connection.rst b/docs/en/get-started/establish-serial-connection.rst index 3e76eaf508..918f8e799d 100644 --- a/docs/en/get-started/establish-serial-connection.rst +++ b/docs/en/get-started/establish-serial-connection.rst @@ -83,7 +83,7 @@ For boards with an installed USB-to-UART bridge, the connection between the pers shape = line; style = dotted; color = "#FF0000"; - label = "Developmment Board\n\n\n"; + label = "Development Board\n\n\n"; BRIDGE; CHIP; } } @@ -121,7 +121,7 @@ Sometimes the USB-to-UART bridge is external. This is often used in small develo shape = line; style = dotted; color = "#FF0000"; - label = "Programmmer Board\n\n\n"; + label = "Programmer Board\n\n\n"; BRIDGE } group { @@ -243,12 +243,20 @@ Verify serial connection Now verify that the serial connection is operational. You can do this using a serial terminal program by checking if you get any output on the terminal after resetting {IDF_TARGET_NAME}. +.. only:: esp32c2 + + The default console baud rate on ESP32-C2 is 115200 when a 40 MHz XTAL is used, or 74880 when a 26 MHz XTAL is used. + +.. only:: not esp32c2 + + The default console baud rate on {IDF_TARGET_NAME} is 115200. + Windows and Linux ^^^^^^^^^^^^^^^^^ In this example we will use `PuTTY SSH Client `_ that is available for both Windows and Linux. You can use other serial programs and set communication parameters like below. -Run terminal, set identified serial port, baud rate = 115200, data bits = 8, stop bits = 1, and parity = N. Below are example screen shots of setting the port and such transmission parameters (in short described as 115200-8-1-N) on Windows and Linux. Remember to select exactly the same serial port you have identified in steps above. +Run terminal and set identified serial port. Baud rate = 115200 (if needed, change this to the default baud rate of the chip in use), data bits = 8, stop bits = 1, and parity = N. Below are example screenshots of setting the port and such transmission parameters (in short described as 115200-8-1-N) on Windows and Linux. Remember to select exactly the same serial port you have identified in steps above. .. figure:: ../../_static/putty-settings-windows.png :align: center @@ -283,7 +291,7 @@ To spare you the trouble of installing a serial terminal program, macOS offers t /dev/cu.Bluetooth-Incoming-Port /dev/cu.SLAB_USBtoUART /dev/cu.SLAB_USBtoUART7 -- The output will vary depending on the type and the number of boards connected to your PC. Then pick the device name of your board and run:: +- The output will vary depending on the type and the number of boards connected to your PC. Then pick the device name of your board and run (if needed, change "115200" to the default baud rate of the chip in use):: screen /dev/cu.device_name 115200 @@ -322,7 +330,7 @@ An example log is shown below. Reset the board if you do not see anything. I (45) boot: compile time 18:48:10 ... -If you can see readable log output, it means serial connection is working and you are ready to proceed with installation and finally upload of application to {IDF_TARGET_NAME}. +If you can see readable log output, it means serial connection is working and you are ready to proceed with installation and finally upload an application to {IDF_TARGET_NAME}. .. note:: diff --git a/docs/en/get-started/index.rst b/docs/en/get-started/index.rst index 950af44d9a..90ba95231b 100644 --- a/docs/en/get-started/index.rst +++ b/docs/en/get-started/index.rst @@ -97,7 +97,7 @@ If you have one of {IDF_TARGET_NAME} official development boards listed below, y :maxdepth: 1 ESP32-S2-Saola-1 <../hw-reference/esp32s2/user-guide-saola-1-v1.2> - ESP32-S2-DevKitM-1(U) <../hw-reference/esp32s2/user-guide-devkitm-1-v1> + ESP32-S2-DevKitM-1 <../hw-reference/esp32s2/user-guide-devkitm-1-v1> ESP32-S2-DevKitC-1 <../hw-reference/esp32s2/user-guide-s2-devkitc-1> ESP32-S2-Kaluga-Kit <../hw-reference/esp32s2/user-guide-esp32-s2-kaluga-1-kit> diff --git a/docs/en/get-started/start-project.rst b/docs/en/get-started/start-project.rst index 2cfa540f9b..3d84cecc60 100644 --- a/docs/en/get-started/start-project.rst +++ b/docs/en/get-started/start-project.rst @@ -381,31 +381,31 @@ ESP-IDF supports Python 3.7 or newer. It is recommended to upgrade your operatin A BSP typically supports all of the hardware components provided on development board. Apart from the pinout definition and initialization functions, a BSP ships with drivers for the external components such as sensors, displays, audio codecs etc. - The BSPs are distributed via `IDF Component Manager <../api-guides/tools/idf-component-manager>`_, so they can be found in `IDF Component Registry `_. + The BSPs are distributed via :doc:`IDF Component Manager `, so they can be found in `IDF Component Registry `_. .. only:: esp32 **Here's an example of how to add ESP-WROVER-KIT BSP to your project:** - + .. code-block:: bash - - idf.py add-dependency esp_wrover_kit + + idf.py add-dependency esp_wrover_kit .. only:: esp32s2 **Here's an example of how to add ESP32-S2-Kaluga-Kit BSP to your project:** - + .. code-block:: bash - + idf.py add-dependency esp32_s2_kaluga_kit .. only:: esp32s3 **Here's an example of how to add ESP-BOX BSP to your project:** - + .. code-block:: bash - - idf.py add-dependency esp-box + + idf.py add-dependency esp-box More examples of BSP usage can be found in `BSP examples folder `_. diff --git a/docs/en/hw-reference/chip-series-comparison.rst b/docs/en/hw-reference/chip-series-comparison.rst deleted file mode 100644 index 19c0a0463e..0000000000 --- a/docs/en/hw-reference/chip-series-comparison.rst +++ /dev/null @@ -1,302 +0,0 @@ -*********************** -Chip Series Comparison -*********************** - -:link_to_translation:`zh_CN:[中文]` - -The comparison below covers key features of chips supported by ESP-IDF. For the full list of features please refer to respective datasheets in Section `Related Documents`_. - -.. list-table:: Chip Series Comparison - :widths: 20 40 40 40 40 - :header-rows: 1 - - * - Feature - - ESP32 Series - - ESP32-S2 Series - - ESP32-C3 Series - - ESP32-S3 Series - * - Launch year - - 2016 - - 2020 - - 2020 - - 2020 - * - Variants - - See `ESP32 Datasheet (PDF) `_ - - See `ESP32-S2 Datasheet (PDF) `_ - - See `ESP32-C3 Datasheet (PDF) `_ - - See `ESP32-S3 Datasheet (PDF) `_ - * - Core - - Xtensa® dual-/single core 32-bit LX6 - - Xtensa® single-core 32-bit LX7 - - 32-bit single-core RISC-V - - Xtensa® dual-core 32-bit LX7 - * - Wi-Fi protocols - - 802.11 b/g/n, 2.4 GHz - - 802.11 b/g/n, 2.4 GHz - - 802.11 b/g/n, 2.4 GHz - - 802.11 b/g/n, 2.4 GHz - * - Bluetooth® - - Bluetooth v4.2 BR/EDR and Bluetooth Low Energy - - âœ–ï¸ - - Bluetooth 5.0 - - Bluetooth 5.0 - * - Typical frequency - - 240 MHz (160 MHz for ESP32-S0WD) - - 240 MHz - - 160 MHz - - 240 MHz - * - SRAM - - 520 KB - - 320 KB - - 400 KB - - 512 KB - * - ROM - - 448 KB for booting and core functions - - 128 KB for booting and core functions - - 384 KB for booting and core functions - - 384 KB for booting and core functions - * - Embedded flash - - 2 MB, 4 MB, or none, depending on variants - - 2 MB, 4 MB, or none, depending on variants - - 4 MB or none, depending on variants - - 8 MB or none, depending on variants - * - External flash - - Up to 16 MB device, address 11 MB + 248 KB each time - - Up to 1 GB device, address 11.5 MB each time - - Up to 16 MB device, address 8 MB each time - - Up to 1 GB device, address 32 MB each time - * - External RAM - - Up to 8 MB device, address 4 MB each time - - Up to 1 GB device, address 11.5 MB each time - - âœ–ï¸ - - Up to 1 GB device, address 32 MB each time - * - Cache - - âœ”ï¸ Two-way set associative - - âœ”ï¸ Four-way set associative, independent instruction cache and data cache - - âœ”ï¸ Eight-way set associative, 32-bit data/instruction bus width - - âœ”ï¸ Four-way or eight-way set associative for instruction cache; four-way set associative for data cache, 32-bit data/instruction bus width - * - **Peripherals** - - - - - - - - - * - ADC - - Two 12-bit, 18 channels - - Two 12-bit, 20 channels - - Two 12-bit SAR ADCs, at most 6 channels - - Two 12-bit SAR ADCs, 20 channels - * - DAC - - Two 8-bit channels - - Two 8-bit channels - - âœ–ï¸ - - âœ–ï¸ - * - Timers - - Four 64-bit general-purpose timers, and three watchdog timers - - Four 64-bit general-purpose timers, and three watchdog timers - - Two 54-bit general-purpose timers, and three watchdog timers - - Four 54-bit general-purpose timers, and three watchdog timers - * - Temperature sensor - - âœ–ï¸ - - 1 - - 1 - - 1 - * - Touch sensor - - 10 - - 14 - - âœ–ï¸ - - 14 - * - Hall sensor - - 1 - - âœ–ï¸ - - âœ–ï¸ - - âœ–ï¸ - * - GPIO - - 34 - - 43 - - 22 - - 45 - * - SPI - - 4 - - 4 - - 3 - - 4 - * - LCD interface - - 1 - - 1 - - âœ–ï¸ - - 1 - * - UART - - 3 - - 2 :sup:`1` - - 2 :sup:`1` - - 3 - * - I2C - - 2 - - 2 - - 1 - - 2 - * - I2S - - 2, can be configured to operate with 8/16/32/40/48-bit resolution as an input or output channel. - - 1, can be configured to operate with 8/16/24/32/48/64-bit resolution as an input or output channel. - - 1, can be configured to operate with 8/16/24/32-bit resolution as an input or output channel. - - 2, can be configured to operate with 8/16/24/32-bit resolution as an input or output channel. - * - Camera interface - - 1 - - 1 - - âœ–ï¸ - - 1 - * - DMA - - Dedicated DMA to UART, SPI, I2S, SDIO slave, SD/MMC host, EMAC, BT, and Wi-Fi - - Dedicated DMA to UART, SPI, AES, SHA, I2S, and ADC Controller - - General-purpose, 3 TX channels, 3 RX channels - - General-purpose, 5 TX channels, 5 RX channels - * - RMT - - 8 channels - - 4 channels :sup:`1`, can be configured to TX/RX channels - - 4 channels :sup:`2`, 2 TX channels, 2 RX channels - - 8 channels :sup:`2`, 4 TX channels, 4 RX channels - * - Pulse counter - - 8 channels - - 4 channels :sup:`1` - - âœ–ï¸ - - 4 channels :sup:`1` - * - LED PWM - - 16 channels - - 8 channels :sup:`1` - - 6 channels :sup:`2` - - 8 channels :sup:`1` - * - MCPWM - - 2, six PWM outputs - - âœ–ï¸ - - âœ–ï¸ - - 2, six PWM outputs - * - USB OTG - - âœ–ï¸ - - 1 - - âœ–ï¸ - - 1 - * - TWAI® controller (compatible with ISO 11898-1) - - 1 - - 1 - - 1 - - 1 - * - SD/SDIO/MMC host controller - - 1 - - âœ–ï¸ - - âœ–ï¸ - - 1 - * - SDIO slave controller - - 1 - - âœ–ï¸ - - âœ–ï¸ - - âœ–ï¸ - * - Ethernet MAC - - 1 - - âœ–ï¸ - - âœ–ï¸ - - âœ–ï¸ - * - ULP - - ULP FSM - - PicoRV32 core with 8 KB SRAM, ULP FSM - - âœ–ï¸ - - PicoRV32 core with 8 KB SRAM, ULP FSM - * - Debug Assist - - âœ–ï¸ - - âœ–ï¸ - - 1 - - âœ–ï¸ - * - **Security** - - - - - - - - - * - Secure boot - - âœ”ï¸ - - âœ”ï¸ Faster and safer, compared with ESP32 - - âœ”ï¸ Faster and safer, compared with ESP32 - - âœ”ï¸ Faster and safer, compared with ESP32 - * - Flash encryption - - âœ”ï¸ - - âœ”ï¸ Support for PSRAM encryption. Safer, compared with ESP32 - - âœ”ï¸ Safer, compared with ESP32 - - âœ”ï¸ Support for PSRAM encryption. Safer, compared with ESP32 - * - OTP - - 1024-bit - - 4096-bit - - 4096-bit - - 4096-bit - * - AES - - âœ”ï¸ AES-128, AES-192, AES-256 (FIPS PUB 197) - - âœ”ï¸ AES-128, AES-192, AES-256 (FIPS PUB 197); DMA support - - âœ”ï¸ AES-128, AES-256 (FIPS PUB 197); DMA support - - âœ”ï¸ AES-128, AES-256 (FIPS PUB 197); DMA support - * - HASH - - SHA-1, SHA-256, SHA-384, SHA-512 (FIPS PUB 180-4) - - SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224, SHA-512/256, SHA-512/t (FIPS PUB 180-4); DMA support - - SHA-1, SHA-224, SHA-256 (FIPS PUB 180-4); DMA support - - SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224, SHA-512/256, SHA-512/t (FIPS PUB 180-4); DMA support - * - RSA - - Up to 4096 bits - - Up to 4096 bits - - Up to 3072 bits - - Up to 4096 bits - * - RNG - - âœ”ï¸ - - âœ”ï¸ - - âœ”ï¸ - - âœ”ï¸ - * - HMAC - - âœ–ï¸ - - âœ”ï¸ - - âœ”ï¸ - - âœ”ï¸ - * - Digital signature - - âœ–ï¸ - - âœ”ï¸ - - âœ”ï¸ - - âœ”ï¸ - * - XTS - - âœ–ï¸ - - âœ”ï¸ XTS-AES-128, XTS-AES-256 - - âœ”ï¸ XTS-AES-128 - - âœ”ï¸ XTS-AES-128, XTS-AES-256 - * - **Other** - - - - - - - - - * - Deep-sleep (ULP sensor-monitored pattern) - - 100 μA (when ADC work with a duty cycle of 1%) - - 22 μA (when touch sensors work with a duty cycle of 1%) - - No such pattern - - TBD - * - Size - - QFN48 5*5, 6*6, depending on variants - - QFN56 7*7 - - QFN32 5*5 - - QFN56 7*7 - - -- **Note** 1: Reduced chip area compared with ESP32 -- **Note** 2: Reduced chip area compared with ESP32 and ESP32-S2 -- **Note** 3: Die size: ESP32-C3 < ESP32-S2 < ESP32-S3 < ESP32 - - - - - - -Related Documents -================= - -- `ESP32 Datasheet (PDF) `_ -- ESP32-PICO Datasheets (PDF) - - - `ESP32-PICO-D4 `_ - - `ESP32-PICO-V3 `_ - - `ESP32-PICO-V3-02 `_ - -- `ESP32-S2 Datasheet (PDF) `_ -- `ESP32-C3 Datasheet (PDF) `_ -- `ESP32-S3 Datasheet (PDF) `_ -- `ESP Product Selector `_ \ No newline at end of file diff --git a/docs/en/hw-reference/esp32/get-started-pico-kit.rst b/docs/en/hw-reference/esp32/get-started-pico-kit.rst index a98531ebde..1f044e8b96 100644 --- a/docs/en/hw-reference/esp32/get-started-pico-kit.rst +++ b/docs/en/hw-reference/esp32/get-started-pico-kit.rst @@ -188,6 +188,14 @@ No. Name Type Function 3. This pin is connected to the pin of the USB bridge chip on the board. 4. The operating voltage of ESP32-PICO-KIT’s embedded SPI flash is 3.3 V. Therefore, the strapping pin MTDI should hold bit zero during the module power-on reset. If connected, please make sure that this pin is not held up on reset. +Pin Layout +^^^^^^^^^^^ +.. figure:: ../../../_static/esp32-pico-kit-v4-pinout.png + :align: center + :scale: 43% + :alt: ESP32-PICO-KIT (click to enlarge) + + ESP32-PICO-KIT Pin Layout (click to enlarge) Start Application Development ----------------------------- diff --git a/docs/en/hw-reference/esp32/user-guide-devkitm-1.rst b/docs/en/hw-reference/esp32/user-guide-devkitm-1.rst index ccefa7b274..16f62cc634 100644 --- a/docs/en/hw-reference/esp32/user-guide-devkitm-1.rst +++ b/docs/en/hw-reference/esp32/user-guide-devkitm-1.rst @@ -168,7 +168,7 @@ The table below provides the Name and Function of pins on both sides of the boar * - No. - Name - - Type + - Type [1]_ - Function * - 1 - GND @@ -237,7 +237,7 @@ The table below provides the Name and Function of pins on both sides of the boar * - 17 - IO12 - I/O - - GPIO12, ADC2_CH5, TOUCH5, RTC_GPIO15, MTDI, HSPIQ, HS2_DATA2, SD_DATA2, EMAC_TXD3 + - GPIO12, ADC2_CH5, TOUCH5, RTC_GPIO15, MTDI [2]_, HSPIQ, HS2_DATA2, SD_DATA2, EMAC_TXD3 * - 18 - IO13 - I/O @@ -245,15 +245,15 @@ The table below provides the Name and Function of pins on both sides of the boar * - 19 - IO15 - I/O - - GPIO15, ADC2_CH3, TOUCH3, RTC_GPIO13, MTDO, HSPICS0, HS2_CMD, SD_CMD, EMAC_RXD3 + - GPIO15, ADC2_CH3, TOUCH3, RTC_GPIO13, MTDO [2]_, HSPICS0, HS2_CMD, SD_CMD, EMAC_RXD3 * - 20 - IO2 - I/O - - GPIO2, ADC2_CH2, TOUCH2, RTC_GPIO12, HSPIWP, HS2_DATA0, SD_DATA0 + - GPIO2 [2]_, ADC2_CH2, TOUCH2, RTC_GPIO12, HSPIWP, HS2_DATA0, SD_DATA0 * - 21 - IO0 - I/O - - GPIO0, ADC2_CH1, TOUCH1, RTC_GPIO11, CLK_OUT1, EMAC_TX_CLK + - GPIO0 [2]_, ADC2_CH1, TOUCH1, RTC_GPIO11, CLK_OUT1, EMAC_TX_CLK * - 22 - IO4 - I/O @@ -269,7 +269,7 @@ The table below provides the Name and Function of pins on both sides of the boar * - 25 - IO5 - I/O - - GPIO5, HS1_DATA6, VSPICS0, EMAC_RX_CLK + - GPIO5 [2]_, HS1_DATA6, VSPICS0, EMAC_RX_CLK * - 26 - IO18 - I/O @@ -299,6 +299,19 @@ The table below provides the Name and Function of pins on both sides of the boar - I/O - GPIO3, U0RXD, CLK_OUT2 +.. [1] P: Power supply; I: Input; O: Output. +.. [2] MTDI, GPIO0, GPIO2, MTDO, and GPIO5 are strapping pins. These pins are used to control several chip functions depending on binary voltage values applied to the pins during chip power-up or system reset. For description and application of the strapping pins, please refer to `ESP32 Datasheet`_ > Section *Strapping Pins*. + +Pin Layout +^^^^^^^^^^^ + +.. figure:: ../../../_static/ESP32_DevKitM-1_pinlayout.png + :align: center + :scale: 43% + :alt: ESP32-DevKitM-1 (click to enlarge) + :figclass: align-center + + ESP32-DevKitM-1 (click to enlarge) Hardware Revision Details ============================ @@ -316,4 +329,4 @@ Related Documents * `ESP32 Datasheet `_ (PDF) * `ESP Product Selector `_ -For other design documentation for the board, please contact us at sales@espressif.com. \ No newline at end of file +For other design documentation for the board, please contact us at sales@espressif.com. diff --git a/docs/en/hw-reference/esp32s2/user-guide-devkitm-1-v1.rst b/docs/en/hw-reference/esp32s2/user-guide-devkitm-1-v1.rst index f135f0babd..a4b04ccef5 100644 --- a/docs/en/hw-reference/esp32s2/user-guide-devkitm-1-v1.rst +++ b/docs/en/hw-reference/esp32s2/user-guide-devkitm-1-v1.rst @@ -1,14 +1,12 @@ -===================== -ESP32-S2-DevKitM-1(U) -===================== +================== +ESP32-S2-DevKitM-1 +================== :link_to_translation:`zh_CN:[中文]` -This user guide provides information on Espressif's small-sized development board ESP32-S2-DevKitM-1(U). +This user guide provides information on Espressif's small-sized development board ESP32-S2-DevKitM-1. -ESP32-S2-DevKitM-1(U) is a general-purpose development board based on `ESP32-S2FH4 `__ chip, which falls into ESP32-S2 chip series. With a rich peripheral set and optimized pinout, this board allows rapid prototyping. - -ESP32-S2-DevKitM-1 is embedded with `ESP32-S2-MINI-1 `__ module (on-board PCB antenna), while ESP32-S2-DevKitM-1U with `ESP32-S2-MINI-1U `__ module (external antenna connector). +ESP32-S2-DevKitM-1 is entry-level development board. Most of the I/O pins on the module are broken out to the pin headers on both sides for easy interfacing. Developers can either connect peripherals with jumper wires or mount ESP32-S2-DevKitM-1 on a breadboard. +----------------------+-----------------------+ | |ESP32-S2-DevKitM-1| | |ESP32-S2-DevKitM-1U| | @@ -22,32 +20,80 @@ ESP32-S2-DevKitM-1 is embedded with `ESP32-S2-MINI-1 `_. + - On **ESP32-S2-MINI-2U** and **ESP32-S2-MINI-1U** module only. For connector dimensions, please refer to Section External Antenna Connector Dimensions in module datasheet. Start Application Development ----------------------------- -Before powering up your ESP32-S2-DevKitM-1(U), please make sure that it is in good condition with no obvious signs of damage. +Before powering up your ESP32-S2-DevKitM-1, please make sure that it is in good condition with no obvious signs of damage. Required Hardware ^^^^^^^^^^^^^^^^^ -- ESP32-S2-DevKitM-1(U) - - + For ESP32-S2-DevKitM-1U, an antenna is also required. - +- ESP32-S2-DevKitM-1 - USB 2.0 cable (Standard-A to Micro-B) - Computer running Windows, Linux, or macOS @@ -125,7 +168,7 @@ Required Hardware Software Setup ^^^^^^^^^^^^^^ -Please proceed to :doc:`../../get-started/index`, where Section :ref:`get-started-step-by-step` will quickly help you set up the development environment and then flash an application example into your ESP32-S2-DevKitM-1(U). +Please proceed to :doc:`../../get-started/index`, where Section :ref:`get-started-step-by-step` will quickly help you set up the development environment and then flash an application example into your ESP32-S2-DevKitM-1. .. note:: @@ -142,10 +185,10 @@ A block diagram below shows the components of ESP32-S2-DevKitM-1 and their inter .. figure:: ../../../_static/esp32-s2-devkitm-1-v1-block-diagram.png :align: center :scale: 70% - :alt: ESP32-S2-DevKitM-1(U) (click to enlarge) + :alt: ESP32-S2-DevKitM-1 (click to enlarge) :figclass: align-center - ESP32-S2-DevKitM-1(U) (click to enlarge) + ESP32-S2-DevKitM-1 (click to enlarge) Power Supply Options ^^^^^^^^^^^^^^^^^^^^ @@ -163,7 +206,7 @@ It is recommended to use the first option: Micro-USB Port. Header Block ------------ -The two tables below provide the **Name** and **Function** of the pin headers on both sides of the board (J1 and J3). The pin header names are shown in :ref:`user-guide-devkitm-1-v1-board-front`. The numbering is the same as in the `ESP32-S2-DevKitM-1(U) Schematics `_ (PDF). +The two tables below provide the **Name** and **Function** of the pin headers on both sides of the board (J1 and J3). The pin header names are shown in :ref:`user-guide-devkitm-1-v1-board-front`. The numbering is the same as in the `ESP32-S2-DevKitM-1 Schematics `_ (PDF). J1 ^^^ @@ -228,10 +271,10 @@ Pin Layout .. figure:: ../../../_static/esp32-s2-devkitm-1-v1-pin-layout.png :align: center :scale: 15% - :alt: ESP32-S2-DevKitM-1(U) (click to enlarge) + :alt: ESP32-S2-DevKitM-1 (click to enlarge) :figclass: align-center - ESP32-S2-DevKitM-1(U) Pin Layout (click to enlarge) + ESP32-S2-DevKitM-1 Pin Layout (click to enlarge) Hardware Revision Details ========================= @@ -240,11 +283,18 @@ This is the first revision of this board released. Related Documents ================= -* `ESP32-S2-DevKitM-1(U) Schematics `_ (PDF) -* `ESP32-S2-DevKitM-1(U) PCB Layout `_ (PDF) -* `ESP32-S2-DevKitM-1(U) Dimensions `_ (PDF) -* `ESP32-S2 Series Datasheet `_ (PDF) -* `ESP32-S2-MINI-1 & ESP32-S2-MINI-1U Datasheet `_ (PDF) +* `ESP32-S2 Series Chip Revision v1.0 Datasheet`_ (PDF) +* `ESP32-S2 Series Chip Revision v0.0 Datasheet `_ (PDF) +* `ESP32-S2 Series SoC Errata`_ (PDF) +* `ESP32-S2-MINI-2 & ESP32-S2-MINI-2U Module Datasheet `_ (PDF) +* `ESP32-S2-MINI-1 & ESP32-S2-MINI-1U Module Datasheet `_ (PDF) +* `ESP32-S2-DevKitM-1 Schematics `_ (PDF) +* `ESP32-S2-DevKitM-1 PCB Layout `_ (PDF) +* `ESP32-S2-DevKitM-1 Dimensions `_ (PDF) * `ESP Product Selector `_ For other design documentation for the board, please contact us at `sales@espressif.com `_. + +.. _NRND: https://www.espressif.com/en/products/longevity-commitment?id=nrnd +.. _ESP32-S2 Series Chip Revision v1.0 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s2-v1.0_datasheet_en.pdf +.. _ESP32-S2 Series SoC Errata: https://espressif.com/sites/default/files/documentation/esp32-s2_errata_en.pdf diff --git a/docs/en/hw-reference/esp32s2/user-guide-s2-devkitc-1.rst b/docs/en/hw-reference/esp32s2/user-guide-s2-devkitc-1.rst index 229978a062..78d2e478e4 100644 --- a/docs/en/hw-reference/esp32s2/user-guide-s2-devkitc-1.rst +++ b/docs/en/hw-reference/esp32s2/user-guide-s2-devkitc-1.rst @@ -6,9 +6,7 @@ ESP32-S2-DevKitC-1 This user guide will help you get started with ESP32-S2-DevKitC-1 and will also provide more in-depth information. -ESP32-S2-DevKitC-1 is an entry-level development board based on ESP32-S2-SOLO (on-board PCB antenna) or ESP32-S2-SOLO-U (external antenna connector), which are two general-purpose modules with a 4 MB SPI flash. This board integrates complete Wi-Fi functions. - -Most of the I/O pins are broken out to the pin headers on both sides for easy interfacing. Developers can either connect peripherals with jumper wires or mount ESP32-S2-DevKitC-1 on a breadboard. +ESP32-S2-DevKitC-1 is an entry-level development board. This board integrates complete Wi-Fi functions. Most of the I/O pins are broken out to the pin headers on both sides for easy interfacing. Developers can either connect peripherals with jumper wires or mount ESP32-S2-DevKitC-1 on a breadboard. .. figure:: ../../../_static/esp32-s2-devkitc-1-v1-isometric.png :align: center @@ -49,8 +47,8 @@ The key components of the board are described in a clockwise direction. * - Key Component - Description - * - ESP32-S2-SOLO or ESP32-S2-SOLO-U - - ESP32-S2-SOLO and ESP32-S2-SOLO-U are two general-purpose Wi-Fi modules. ESP32-S2-SOLO comes with an on-board PCB antenna and ESP32-S2-SOLO-U comes with a connector for an external antenna. ESP32-S2-SOLO or ESP32-S2-SOLO-U on the board may come either with a 4 MB flash, or a 4 MB flash plus a 2 MB PSRAM embedded in the chip. + * - On-board module (ESP32-S2-SOLO or ESP32-S2-SOLO-U in the above figure) + - ESP32-S2-SOLO series modules with an on-board PCB antenna or a connector for an external antenna. This series of modules have multiple options for flash and PSRAM size. For more information, please refer to :ref:`user-guide-s2-devkitc-1-v1-ordering-info`. * - 3.3 V Power On LED - Turns on when the USB power is connected to the board. * - USB-to-UART Bridge @@ -100,6 +98,59 @@ Please proceed to `ESP-IDF Get Started `_ (PDF). +The two tables below provide the **Name** and **Function** of the pin headers on both sides of the board (J1 and J3). The pin header names are shown in :ref:`user-guide-s2-devkitc-1-v1-board-front`. The numbering is the same as in the `ESP32-S2-DevKitC-1 Schematic`_ (PDF). J1 ^^^ -=== ==== ========== ========================================================================== -No. Name Type [#]_ Function -=== ==== ========== ========================================================================== -1 3V3 P 3.3 V power supply -2 3V3 P 3.3 V power supply -3 RST I CHIP_PU -4 4 I/O/T RTC_GPIO4, GPIO4, TOUCH4, ADC1_CH3 -5 5 I/O/T RTC_GPIO5, GPIO5, TOUCH5, ADC1_CH4 -6 6 I/O/T RTC_GPIO6, GPIO6, TOUCH6, ADC1_CH5 -7 7 I/O/T RTC_GPIO7, GPIO7, TOUCH7, ADC1_CH6 -8 15 I/O/T RTC_GPIO15, GPIO15, U0RTS, ADC2_CH4, XTAL_32K_P -9 16 I/O/T RTC_GPIO16, GPIO16, U0CTS, ADC2_CH5, XTAL_32K_N -10 17 I/O/T RTC_GPIO17, GPIO17, U1TXD, ADC2_CH6, DAC_1 -11 18 I/O/T RTC_GPIO18, GPIO18, U1RXD, ADC2_CH7, DAC_2, CLK_OUT3, RGB LED -12 8 I/O/T RTC_GPIO8, GPIO8, TOUCH8, ADC1_CH7 -13 3 I/O/T RTC_GPIO3, GPIO3, TOUCH3, ADC1_CH2 -14 46 I GPIO46 -15 9 I/O/T RTC_GPIO9, GPIO9, TOUCH9, ADC1_CH8, FSPIHD -16 10 I/O/T RTC_GPIO10, GPIO10, TOUCH10, ADC1_CH9, FSPICS0, FSPIIO4 -17 11 I/O/T RTC_GPIO11, GPIO11, TOUCH11, ADC2_CH0, FSPID, FSPIIO5 -18 12 I/O/T RTC_GPIO12, GPIO12, TOUCH12, ADC2_CH1, FSPICLK, FSPIIO6 -19 13 I/O/T RTC_GPIO13, GPIO13, TOUCH13, ADC2_CH2, FSPIQ, FSPIIO7 -20 14 I/O/T RTC_GPIO14, GPIO14, TOUCH14, ADC2_CH3, FSPIWP, FSPIDQS -21 5V P 5 V power supply -22 G G Ground -=== ==== ========== ========================================================================== +=== ========= ========== ========================================================================== +No. Name Type [#]_ Function +=== ========= ========== ========================================================================== +1 3V3 P 3.3 V power supply +2 3V3 P 3.3 V power supply +3 RST I CHIP_PU +4 4 I/O/T RTC_GPIO4, GPIO4, TOUCH4, ADC1_CH3 +5 5 I/O/T RTC_GPIO5, GPIO5, TOUCH5, ADC1_CH4 +6 6 I/O/T RTC_GPIO6, GPIO6, TOUCH6, ADC1_CH5 +7 7 I/O/T RTC_GPIO7, GPIO7, TOUCH7, ADC1_CH6 +8 15 I/O/T RTC_GPIO15, GPIO15, U0RTS, ADC2_CH4, XTAL_32K_P +9 16 I/O/T RTC_GPIO16, GPIO16, U0CTS, ADC2_CH5, XTAL_32K_N +10 17 I/O/T RTC_GPIO17, GPIO17, U1TXD, ADC2_CH6, DAC_1 +11 18 [#]_ I/O/T RTC_GPIO18, GPIO18, U1RXD, ADC2_CH7, DAC_2, CLK_OUT3, RGB LED +12 8 I/O/T RTC_GPIO8, GPIO8, TOUCH8, ADC1_CH7 +13 3 I/O/T RTC_GPIO3, GPIO3, TOUCH3, ADC1_CH2 +14 46 I GPIO46 +15 9 I/O/T RTC_GPIO9, GPIO9, TOUCH9, ADC1_CH8, FSPIHD +16 10 I/O/T RTC_GPIO10, GPIO10, TOUCH10, ADC1_CH9, FSPICS0, FSPIIO4 +17 11 I/O/T RTC_GPIO11, GPIO11, TOUCH11, ADC2_CH0, FSPID, FSPIIO5 +18 12 I/O/T RTC_GPIO12, GPIO12, TOUCH12, ADC2_CH1, FSPICLK, FSPIIO6 +19 13 I/O/T RTC_GPIO13, GPIO13, TOUCH13, ADC2_CH2, FSPIQ, FSPIIO7 +20 14 I/O/T RTC_GPIO14, GPIO14, TOUCH14, ADC2_CH3, FSPIWP, FSPIDQS +21 5V P 5 V power supply +22 G G Ground +=== ========= ========== ========================================================================== J3 @@ -206,12 +257,13 @@ No. Name Type Function === ==== ===== ============================================================ .. [#] P: Power supply; I: Input; O: Output; T: High impedance. +.. [#] GPIO18 is not pulled up on boards with an ESP32-S2-SOLO-2 or ESP32-S2-SOLO-2U module. Pin Layout ^^^^^^^^^^^ .. figure:: ../../../_static/esp32-s2-devkitc-1-v1-pinout.png :align: center - :scale: 15% + :scale: 45% :alt: ESP32-S2-DevKitC-1 (click to enlarge) :figclass: align-center @@ -224,11 +276,20 @@ This is the first revision of this board released. Related Documents ================= -* `ESP32-S2 Series Chip Datasheet `_ (PDF) + +* `ESP32-S2 Series Chip Revision v1.0 Datasheet`_ (PDF) +* `ESP32-S2 Series Chip Revision v0.0 Datasheet `_ (PDF) +* `ESP32-S2 Series SoC Errata`_ (PDF) +* `ESP32-S2-SOLO-2 & ESP32-S2-SOLO-2U Module Datasheet `_ (PDF) * `ESP32-S2-SOLO & ESP32-S2-SOLO-U Module Datasheet `_ (PDF) -* `ESP32-S2-DevKitC-1 Schematic `_ (PDF) +* `ESP32-S2-DevKitC-1 Schematic`_ (PDF) * `ESP32-S2-DevKitC-1 PCB Layout `_ (PDF) * `ESP32-S2-DevKitC-1 Dimensions `_ (PDF) * `ESP32-S2-DevKitC-1 Dimensions source file `_ (DXF) - You can view it with `Autodesk Viewer `_ online For further design documentation for the board, please contact us at `sales@espressif.com `_. + +.. _NRND: https://www.espressif.com/en/products/longevity-commitment?id=nrnd +.. _ESP32-S2 Series Chip Revision v1.0 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s2-v1.0_datasheet_en.pdf +.. _ESP32-S2 Series SoC Errata: https://espressif.com/sites/default/files/documentation/esp32-s2_errata_en.pdf +.. _ESP32-S2-DevKitC-1 Schematic: https://dl.espressif.com/dl/schematics/esp-idf/SCH_ESP32-S2-DEVKITC-1_V1_20220817.pdf diff --git a/docs/en/hw-reference/esp32s3/user-guide-devkitc-1.rst b/docs/en/hw-reference/esp32s3/user-guide-devkitc-1.rst index c37dc30d8a..3db423e260 100644 --- a/docs/en/hw-reference/esp32s3/user-guide-devkitc-1.rst +++ b/docs/en/hw-reference/esp32s3/user-guide-devkitc-1.rst @@ -38,7 +38,7 @@ Description of Components .. _user-guide-s3-devkitc-1-v1.1-board-front: -.. figure:: ../../../_static/ESP32-S3-DevKitC-1_v1.1-annotated-photo.png +.. figure:: ../../../_static/ESP32-S3-DevKitC-1_v2-annotated-photo.png :align: center :alt: ESP32-S3-DevKitC-1 - front @@ -64,7 +64,7 @@ The key components of the board are described in a counter-clockwise direction. - Download button. Holding down **Boot** and then pressing **Reset** initiates Firmware Download mode for downloading firmware through the serial port. * - Reset Button - Press this button to restart the system. - * - ESP32-S3 USB Port + * - USB Port - ESP32-S3 full-speed USB OTG interface, compliant with the USB 1.1 specification. The interface is used for power supply to the board, for flashing applications to the chip, for communication with the chip using USB 1.1 protocols, as well as for JTAG debugging. * - USB-to-UART Bridge - Single USB-to-UART bridge chip provides transfer rates up to 3 Mbps. diff --git a/docs/en/hw-reference/index.rst b/docs/en/hw-reference/index.rst index 8a11e49059..6291efe12d 100644 --- a/docs/en/hw-reference/index.rst +++ b/docs/en/hw-reference/index.rst @@ -22,5 +22,5 @@ Hardware Reference Espressif KiCad Library ESP Product Selector Regulatory Certificates - Chip Series Comparison + Chip Series Comparison User Forum (Hardware) diff --git a/docs/en/index.rst b/docs/en/index.rst index cc036883cf..79845b00ca 100644 --- a/docs/en/index.rst +++ b/docs/en/index.rst @@ -19,13 +19,9 @@ This is the documentation for Espressif IoT Development Framework (`esp-idf `_ +* `Porting to GCC 10 `_ +* `Porting to GCC 11 `_ -* https://gcc.gnu.org/gcc-9/porting_to.html +Warnings +======== -* https://gcc.gnu.org/gcc-10/porting_to.html +The upgrade to GCC 11.2.0 has resulted in the addition of new warnings, or enhancements to existing warnings. The full details of all GCC warnings can be found in `GCC Warning Options `_. Users are advised to double-check their code, then fix the warnings if possible. Unfortunately, depending on the warning and the complexity of the user's code, some warnings will be false positives that require non-trivial fixes. In such cases, users can choose to suppress the warning in multiple ways. This section outlines some common warnings that users are likely to encounter, and ways to suppress them. -* https://gcc.gnu.org/gcc-11/porting_to.html +.. warning:: + Users are advised to check that a warning is indeed a false positive before attempting to suppress them it. -Espressif Toolchain changes -=========================== +``-Wstringop-overflow``, ``-Wstringop-overread``, ``-Wstringop-truncation``, and ``-Warray-bounds`` +-------------------------------------------------------------------------------------------------------- - -``int32_t`` and ``uint32_t`` for Xtensa compiler ------------------------------------------------- - -The types ``int32_t`` and ``uint32_t`` have been changed from ``int`` and ``unsigned int`` to ``long`` and ``unsigned long``. Upstream GCC uses ``long`` integers for int32_t/uint32_t on Xtensa, RISC-V and other architectures. - -+---------+--------------------------+-----------------+ -| | 2021r2 and older, GCC 8 | 2022r1, GCC 11 | -+=========+==========================+=================+ -| xtensa | (unsigned) int | (unsigned) long | -+---------+--------------------------+-----------------+ -| riscv32 | (unsigned) long | (unsigned) long | -+---------+--------------------------+-----------------+ - - -The most cases in code are related to the formatting. Using ``%i``, ``%x``, etc., should be replaced to ``PRIi32``, ``PRIxx``, and others from ````. - -In other cases it should be noted that enums have ``int`` type. - -In common, ``int32_t`` and ``int`` are different types, as well as ``uint32_t`` and ``unsigned int``. - - -Removing of ``CONFIG_COMPILER_DISABLE_GCC8_WARNINGS`` build option ------------------------------------------------------------------- - -``CONFIG_COMPILER_DISABLE_GCC8_WARNINGS`` option was introduced to help transition from rigid GCC 5 toolchain to new ones with helping build ancient code. Enough time has passed to fix the warnings. - -For now in GCC 11, the suggestion is to review your own code to comply compiler warnings. - - -Common cases in code -==================== - - -``-Wstringop-overflow``, ``-Wstringop-overread``, ``-Wstringop-truncation``, and ``-Warray-bounds`` warnings ------------------------------------------------------------------------------------------------------------- - -Warning details: https://gcc.gnu.org/onlinedocs/gcc-11.2.0/gcc/Warning-Options.html - -Double check your code then fix please. Unfortunately, not all seemingly simple ways to satisfy the compiler will work. -You can supress such warnings if the compiler worried for nothing. +Users that use memory/string copy/compare functions will run into one of the ``-Wstringop`` warnings if the compiler cannot properly determine the size of the memory/string. The examples below demonstrate code that triggers these warnings and how to suppress them. .. code-block:: c @@ -80,15 +48,10 @@ You can supress such warnings if the compiler worried for nothing. #pragma GCC diagnostic pop +``-Waddress-of-packed-member`` +-------------------------------- -``-Waddress-of-packed-member`` warning --------------------------------------- - -Warning details: https://gcc.gnu.org/onlinedocs/gcc-11.2.0/gcc/Warning-Options.html - -Double check your code then fix please. - -Unaligned pointer value for data doesn't have penalty for xtensa and riscv32 Espressif chips so we can ignore it in most cases. +GCC will issue this warning when accessing an unaligned member of a packed ``struct`` due to the incurred penalty of unaligned memory access. However, all ESP chips (on both Xtensa and RISC-V architectures) allow for unaligned memory access and incur no extra penalty. Thus, this warning can be ignored in most cases. .. code-block:: none @@ -98,7 +61,7 @@ Unaligned pointer value for data doesn't have penalty for xtensa and riscv32 Esp | ^~~~~~~~~~~~~ -on CMake level for tons of cases: +If the warning occurs in multiple places across multiple source files, users can suppress the warning at the CMake level as demonstrated below. .. code-block:: cmake @@ -109,7 +72,7 @@ on CMake level for tons of cases: "host/bluedroid/btc/profile/std/gatt/btc_gatts.c" PROPERTIES COMPILE_FLAGS -Wno-address-of-packed-member) -or on code level: +However, if there are only one or two instances, users can suppress the warning directly in the source code itself as demonstrated below. .. code-block:: c @@ -121,8 +84,56 @@ or on code level: #pragma GCC diagnostic pop - -``llabs()`` for 64-bit integers +``llabs()`` for 64-bit Integers ------------------------------- -The function ``abs()`` from stdlib.h takes ``int`` argument. Please use ``llabs()`` for types that intended to be 64-bit. In particular it's important for ``time_t``. +The function ``abs()`` from stdlib.h takes ``int`` argument. Please use ``llabs()`` for types that are intended to be 64-bit. It is particularly important for ``time_t``. + + +Espressif Toolchain Changes +=========================== + +``int32_t`` and ``uint32_t`` for Xtensa Compiler +------------------------------------------------ + +The types ``int32_t`` and ``uint32_t`` have been changed from the previous ``int`` and ``unsigned int`` to ``long`` and ``unsigned long`` respectively for the Xtensa compiler. This change now matches upstream GCC which ``long`` integers for ``int32_t`` and ``uint32_t`` on Xtensa, RISC-V, and other architectures. + + +.. list-table:: + :widths: 20 45 35 + :header-rows: 1 + + * - + - 2021r2 and older, GCC 8 + - 2022r1, GCC 11 + * - Xtensa + - (unsigned) int + - (unsigned) long + * - riscv32 + - (unsigned) long + - (unsigned) long + + +The change mostly affects code that formats strings using types provided by ````. Users will need to replace placeholders such as ``%i`` and ``%x`` with ``PRIi32`` and ``PRIxx`` respectively. + +In other cases, it should be noted that enums have the ``int`` type. + +In common, ``int32_t`` and ``int``, as well as ``uint32_t`` and ``unsigned int``, are different types. + +If users do not make the aforementioned updates to format strings in their applications, the following error will be reported during compilation: + +.. code-block:: none + + /Users/name/esp/esp-rainmaker/components/esp-insights/components/esp_diagnostics/include/esp_diagnostics.h:238:29: error: format '%u' expects argument of type 'unsigned int', but argument 3 has type 'uint32_t' {aka 'long unsigned int'} [-Werror=format=] + 238 | esp_diag_log_event(tag, "EV (%u) %s: " format, esp_log_timestamp(), tag, ##__VA_ARGS__); \ + | ^~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~ + | | + | uint32_t {aka long unsigned int} + uint32_t {aka long unsigned int} + +Removing ``CONFIG_COMPILER_DISABLE_GCC8_WARNINGS`` Build Option +------------------------------------------------------------------ + +``CONFIG_COMPILER_DISABLE_GCC8_WARNINGS`` option was introduced to allow building of legacy code dating from the rigid GCC 5 toolchain. However, enough time has passed to allow for the warnings to be fixed, thus this option has been removed. + +For now in GCC 11, users are advised to review their code and fix the compiler warnings where possible. diff --git a/docs/en/migration-guides/release-5.x/index.rst b/docs/en/migration-guides/release-5.x/index.rst index c9cc97d89e..44ccc789be 100644 --- a/docs/en/migration-guides/release-5.x/index.rst +++ b/docs/en/migration-guides/release-5.x/index.rst @@ -6,7 +6,8 @@ Migration from 4.4 to 5.0 .. toctree:: :maxdepth: 1 - :SOC_CLASSIC_BT_SUPPORTED: bluetooth-classic + :SOC_BT_CLASSIC_SUPPORTED: bluetooth-classic + :SOC_BLE_SUPPORTED: bluetooth-low-energy build-system gcc networking diff --git a/docs/en/migration-guides/release-5.x/networking.rst b/docs/en/migration-guides/release-5.x/networking.rst index 3be7715068..8e8d3381e5 100644 --- a/docs/en/migration-guides/release-5.x/networking.rst +++ b/docs/en/migration-guides/release-5.x/networking.rst @@ -4,98 +4,105 @@ Networking :link_to_translation:`zh_CN:[中文]` Ethernet -********** +******** esp_eth_ioctl() API ------------------- -:cpp:func:`esp_eth_ioctl` third argument could take `int` (`bool`) number as an input in some cases. However, it was not properly documented and, in addition, the number had to be "unnaturally" type casted to `void *` datatype to prevent compiler warnings as shown in below example: -.. highlight:: c +Previously, the :cpp:func:`esp_eth_ioctl` API had the following issues: -:: + - The third parameter (which is of type ``void *``) would accept an ``int``/``bool`` type arguments (i.e., not pointers) as input in some cases. However, these cases were not documented properly. + - To pass ``int``/``bool`` type argument as the third parameter, the argument had to be "unnaturally" casted to a ``void *`` type, to prevent a compiler warning as demonstrated in the code snippet below. This casting could lead to misuse of the :cpp:func:`esp_eth_ioctl` function. + +.. code-block:: c esp_eth_ioctl(eth_handle, ETH_CMD_S_FLOW_CTRL, (void *)true); - -This could lead to misuse of the :cpp:func:`esp_eth_ioctl`. Therefore, ESP-IDF 5.0 unified usage of :cpp:func:`esp_eth_ioctl`. Its third argument now always acts as pointer to a memory location of specific type from/to where the configuration option is read/stored. +Therefore, the usage of :cpp:func:`esp_eth_ioctl` is now unified. Arguments to the third parameter must be passed as pointers to a specific data type to/from where data will be stored/read by :cpp:func:`esp_eth_ioctl`. The code snippets below demonstrate the usage of :cpp:func:`esp_eth_ioctl`. Usage example to set Ethernet configuration: -.. highlight:: c - -:: +.. code-block:: c eth_duplex_t new_duplex_mode = ETH_DUPLEX_HALF; esp_eth_ioctl(eth_handle, ETH_CMD_S_DUPLEX_MODE, &new_duplex_mode); Usage example to get Ethernet configuration: -.. highlight:: c - -:: - +.. code-block:: c + eth_duplex_t duplex_mode; esp_eth_ioctl(eth_handle, ETH_CMD_G_DUPLEX_MODE, &duplex_mode); - KSZ8041/81 and LAN8720 Driver Update ------------------------------------ -KSZ8041/81 and LAN8720 Drivers were updated to support more devices (generations) from associated product family. The drivers are able to recognize particular chip number and its potential support by the driver. -As a result, the specific "chip number" functions calls were replaced by generic ones as follows: +The KSZ8041/81 and LAN8720 drivers are updated to support more devices (i.e., generations) from their associated product families. The drivers can recognize particular chip numbers and their potential support by the driver. -* `esp_eth_phy_new_ksz8041` and `esp_eth_phy_new_ksz8081` were removed, use :cpp:func:`esp_eth_phy_new_ksz80xx` instead -* `esp_eth_phy_new_lan8720` was removed, use :cpp:func:`esp_eth_phy_new_lan87xx` instead +As a result, the specific "chip number" functions calls are replaced by generic ones as follows: + +* Removed ``esp_eth_phy_new_ksz8041()`` and ``esp_eth_phy_new_ksz8081()``, and use :cpp:func:`esp_eth_phy_new_ksz80xx` instead +* Removed ``esp_eth_phy_new_lan8720()``, and use :cpp:func:`esp_eth_phy_new_lan87xx` instead ESP NETIF Glue Event Handlers ----------------------------- -``esp_eth_set_default_handlers()`` and ``esp_eth_clear_default_handlers()`` functions were removed. Registration of the default IP layer handlers for Ethernet is now handled automatically. If users have already followed the recommendation to fully initialize the Ethernet driver and network interface prior to registering their Ethernet/IP event handlers, then no action is required (except for deleting the affected functions). Otherwise, users should ensure that they register the user event handlers as the last thing prior to starting the Ethernet driver. + +``esp_eth_set_default_handlers()`` and ``esp_eth_clear_default_handlers()`` functions are removed. Registration of the default IP layer handlers for Ethernet is now handled automatically. If you have already followed the suggestion to fully initialize the Ethernet driver and network interface before registering their Ethernet/IP event handlers, then no action is required (except for deleting the affected functions). Otherwise, you may start the Ethernet driver right after they register the user event handler. PHY Address Auto-detect ----------------------- -Ethernet PHY address auto-detect function ``esp_eth_detect_phy_addr`` was renamed to :cpp:func:`esp_eth_phy_802_3_detect_phy_addr` and its header declaration was moved to :component_file:`esp_eth/include/esp_eth_phy_802_3.h`. + +The Ethernet PHY address auto-detect function ``esp_eth_detect_phy_addr()`` is renamed to :cpp:func:`esp_eth_phy_802_3_detect_phy_addr` and its header declaration is moved to :component_file:`esp_eth/include/esp_eth_phy_802_3.h`. + + +SPI-Ethernet Module Initialization +----------------------------------- + +The SPI-Ethernet Module initialization is now simplified. Previously, you had to manually allocate an SPI device using :cpp:func:`spi_bus_add_device` before instantiating the SPI-Ethernet MAC. + +Now, you no longer need to call :cpp:func:`spi_bus_add_device` as SPI devices are allocated internally. As a result, the :cpp:class:`eth_dm9051_config_t`, :cpp:class:`eth_w5500_config_t`, and :cpp:class:`eth_ksz8851snl_config_t` configuration structures are updated to include members for SPI device configuration (e.g., to allow fine tuning of SPI timing which may be dependent on PCB design). Likewise, the ``ETH_DM9051_DEFAULT_CONFIG``, ``ETH_W5500_DEFAULT_CONFIG``, and ``ETH_KSZ8851SNL_DEFAULT_CONFIG`` configuration initialization macros are updated to accept new input parameters. Refer to :doc:`Ethernet API Reference Guide<../../api-reference/network/esp_eth>` for an example of SPI-Ethernet Module initialization. + .. _tcpip-adapter: TCP/IP Adapter ***************** -TCP/IP Adapter was a network interface abstraction component used in ESP-IDF prior to v4.1. This page outlines migration from tcpip_adapter API to its successor :doc:`/api-reference/network/esp_netif`. +The TCP/IP Adapter was a network interface abstraction component used in ESP-IDF prior to v4.1. This section outlines migration from tcpip_adapter API to its successor :doc:`/api-reference/network/esp_netif`. -Updating network connection code +Updating Network Connection Code -------------------------------- -Network stack initialization +Network Stack Initialization ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Simply replace ``tcpip_adapter_init()`` with ``esp_netif_init()``. Please note that the :doc:`/api-reference/network/esp_netif` initialization API returns standard error code and the ``esp_netif_deinit()`` for un-initialization is available. - -Also replace ``#include "tcpip_adapter.h"`` with ``#include "esp_netif.h"``. +- You may simply replace ``tcpip_adapter_init()`` with ``esp_netif_init()``. However, please should note that the ``esp_netif_init()`` function now returns standard error codes. See :doc:`/api-reference/network/esp_netif` for more details. +- The ``esp_netif_deinit()`` function is provided to de-initialize the network stack. +- You should also replace ``#include "tcpip_adapter.h"`` with ``#include "esp_netif.h"``. -Network interface creation +Network Interface Creation ^^^^^^^^^^^^^^^^^^^^^^^^^^ -TCP/IP Adapter defined these three interfaces statically: +Previously, the TCP/IP Adapter defined the following network interfaces statically: - WiFi Station - WiFi Access Point - Ethernet -Network interface instance shall be explicitly constructed for the :doc:`/api-reference/network/esp_netif` to enable its connection to the TCP/IP stack. -For example initialization code for WiFi has to explicitly call ``esp_netif_create_default_wifi_sta();`` or ``esp_netif_create_default_wifi_ap();`` after the TCP/IP stack and the event loop have been initialized. -Please consult an example initialization code for these three interfaces: +This now changes. Network interface instance should be explicitly constructed, so that the :doc:`/api-reference/network/esp_netif` can connect to the TCP/IP stack. For example, after the TCP/IP stack and the event loop are initialized, the initialization code for WiFi must explicitly call ``esp_netif_create_default_wifi_sta();`` or ``esp_netif_create_default_wifi_ap();``. + +Please refer to the example initialization code for these three interfaces: - WiFi Station: :example_file:`wifi/getting_started/station/main/station_example_main.c` - WiFi Access Point: :example_file:`wifi/getting_started/softAP/main/softap_example_main.c` - Ethernet: :example_file:`ethernet/basic/main/ethernet_example_main.c` - -Replacing other tcpip_adapter API -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Other tcpip_adapter API Replacement +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ All the tcpip_adapter functions have their esp-netif counter-part. Please refer to the esp_netif.h grouped into these sections: @@ -104,13 +111,13 @@ All the tcpip_adapter functions have their esp-netif counter-part. Please refer * :component_file:`DNS ` * :component_file:`IP address ` - -Default event handlers +Default Event Handlers ^^^^^^^^^^^^^^^^^^^^^^ -Event handlers are moved from tcpip_adapter to appropriate driver code. There is no change from application code perspective, all events shall be handled in the same way. -Please note that within IP related event handlers, application code usually receives IP addresses in a form of esp-netif specific struct (not the LwIP structs, but binary compatible). -This is the preferred way of printing the address: +Event handlers are moved from tcpip_adapter to appropriate driver code. There is no change from application code perspective, as all events should be handled in the same way. Please note that for IP-related event handlers, application code usually receives IP addresses in the form of an esp-netif specific struct instead of the LwIP structs. However, both structs are binary compatible. + + +This is the preferred way to print the address: .. code-block:: c @@ -122,19 +129,18 @@ Instead of ESP_LOGI(TAG, "got ip:%s\n", ip4addr_ntoa(&event->ip_info.ip)); -Since ``ip4addr_ntoa()`` is a LwIP API, the esp-netif provides ``esp_ip4addr_ntoa()`` as a replacement, but the above method is generally preferred. +Since ``ip4addr_ntoa()`` is a LwIP API, the esp-netif provides ``esp_ip4addr_ntoa()`` as a replacement. However, the above method using ``IP2STR()`` is generally preferred. - -IP addresses +IP Addresses ^^^^^^^^^^^^ -It is preferred to use esp-netif defined IP structures. Please note that the LwIP structs will still work when default compatibility enabled. +You are advised to use esp-netif defined IP structures. Please note that with default compatibility enabled, the LwIP structs will still work. + * :component_file:`esp-netif IP address definitions ` - -Next steps +Next Steps ^^^^^^^^^^ -Additional step in porting an application to fully benefit from the :doc:`/api-reference/network/esp_netif` is to disable the tcpip_adapter compatibility layer in the component configuration: -``ESP NETIF Adapter`` -> ``Enable backward compatible tcpip_adapter interface`` and check if the project compiles. -TCP/IP adapter brings many include dependencies and this step might help in decoupling the application from using specific TCP/IP stack API directly. +To port an application which may fully benefit from the :doc:`/api-reference/network/esp_netif`, you also need to disable the tcpip_adapter compatibility layer in the component configuration option. Please go to ``ESP NETIF Adapter`` > ``Enable backward compatible tcpip_adapter interface``. After that, check if your project compiles. + +The TCP/IP adapter includes many dependencies. Thus, disabling its compatibility might help separate the application from using specific TCP/IP stack API directly. diff --git a/docs/en/migration-guides/release-5.x/peripherals.rst b/docs/en/migration-guides/release-5.x/peripherals.rst index 15c4a742fd..f421466359 100644 --- a/docs/en/migration-guides/release-5.x/peripherals.rst +++ b/docs/en/migration-guides/release-5.x/peripherals.rst @@ -1,6 +1,8 @@ Peripherals =========== +:link_to_translation:`zh_CN:[中文]` + Peripheral Clock Gating ----------------------- @@ -16,108 +18,190 @@ RTC control APIs have been moved from ``driver/rtc_cntl.h`` to ``esp_private/rtc ADC --- -- ADC oneshot mode driver has been redesigned. New driver is in ``esp_adc`` component and the include path is ``esp_adc/adc_oneshot.h``. Legacy driver is still available in the previous include path ``driver/adc.h``. However, by default, including ``driver/adc.h`` will bring a build warning like `legacy adc driver is deprecated, please migrate to use esp_adc/adc_oneshot.h and esp_adc/adc_continuous.h for oneshot mode and continuous mode drivers respectively`. The warning can be suppressed by the Kconfig option :ref:`CONFIG_ADC_SUPPRESS_DEPRECATE_WARN`. -- ADC continuous mode driver has been moved from ``driver`` component to ``esp_adc`` component. Include path has been changed from ``driver/adc.h`` to ``esp_adc/adc_continuous.h``. Legacy driver is still available in the previous include path ``driver/adc.h``. Similarly, including it will bring a build warning, and it can be suppressed by the Kconfig option :ref:`CONFIG_ADC_SUPPRESS_DEPRECATE_WARN`. -- ADC calibration driver has been redesigned. New driver is in ``esp_adc`` component and the include path is ``esp_adc/adc_cali.h`` and ``esp_adc/adc_cali_scheme.h``. Legacy driver is still available by including ``esp_adc_cal.h``. However, by default, including ``esp_adc_cal.h`` will bring a build warning like `legacy adc calibration driver is deprecated, please migrate to use esp_adc/adc_cali.h and esp_adc/adc_cali_scheme.h`. The warning can be suppressed by the Kconfig option :ref:`CONFIG_ADC_CALI_SUPPRESS_DEPRECATE_WARN`. -- API ``adc_power_acquire`` and ``adc_power_release`` have been deprecated. These two are used by other drivers to maintain ADC power due to hardware limitation. After this change, ADC power will still be handled by the drivers. However, for users who are interested in this, the include path has been changed from ``driver/adc.h`` to ``esp_private/adc_share_hw_ctrl.h``. -- Previous ``driver/adc2_wifi_private.h`` has been moved to ``esp_private/adc_share_hw_ctrl.h``. -- Enums ``ADC_UNIT_BOTH``, ``ADC_UNIT_ALTER`` and ``ADC_UNIT_MAX`` in ``adc_unit_t`` have been removed. -- Enum ``ADC_CHANNEL_MAX`` in ``adc_channel_t`` has been removed. Some channels are not supported on some chips, driver will give a dynamic error if an unsupported channels are used. -- Enum ``ADC_ATTEN_MAX`` has been removed. Some attenuations are not supported on some chips, driver will give a dynamic error if an unsupported attenuation is used. -- Enum ``ADC_CONV_UNIT_MAX`` has been removed. Some convert mode are not supported on some chips, driver will give a dynamic error if an unsupported convert mode is used. -- API ``hall_sensor_read`` on ESP32 has been removed. Hall sensor is no more supported on ESP32. +ADC Oneshot & Continuous Mode drivers +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The ADC oneshot mode driver has been redesigned. + +- The new driver is in ``esp_adc`` component and the include path is ``esp_adc/adc_oneshot.h``. +- The legacy driver is still available in the previous include path ``driver/adc.h``. + +The ADC continuous mode driver has been moved from ``driver`` component to ``esp_adc`` component. + +- The include path has been changed from ``driver/adc.h`` to ``esp_adc/adc_continuous.h``. + +Attempting to use the legacy include path ``driver/adc.h`` of either driver will trigger the build warning below by default. However, the warning can be suppressed by enabling the :ref:`CONFIG_ADC_SUPPRESS_DEPRECATE_WARN` Kconfig option. + +.. code-block:: text + + legacy adc driver is deprecated, please migrate to use esp_adc/adc_oneshot.h and esp_adc/adc_continuous.h for oneshot mode and continuous mode drivers respectively + +ADC Calibration Driver +^^^^^^^^^^^^^^^^^^^^^^ + +The ADC calibration driver has been redesigned. + +- The new driver is in ``esp_adc`` component and the include path is ``esp_adc/adc_cali.h`` and ``esp_adc/adc_cali_scheme.h``. + +Legacy driver is still available by including ``esp_adc_cal.h``. However, if users still would like to use the include path of the legacy driver, users should add ``esp_adc`` component to the list of component requirements in CMakeLists.txt. + +Attempting to use the legacy include path ``esp_adc_cal.h`` will trigger the build warning below by default. However, the warning can be suppressed by enabling the :ref:`CONFIG_ADC_CALI_SUPPRESS_DEPRECATE_WARN` Kconfig option. + +.. code-block:: text + + legacy adc calibration driver is deprecated, please migrate to use esp_adc/adc_cali.h and esp_adc/adc_cali_scheme.h + +API Changes +^^^^^^^^^^^ + +- The ADC power management APIs ``adc_power_acquire`` and ``adc_power_release`` have made private and moved to ``esp_private/adc_share_hw_ctrl.h``. + + - The two APIs were previously made public due to a HW errata workaround. + - Now, ADC power management is completely handled internally by drivers. + - Users who still require this API can include ``esp_private/adc_share_hw_ctrl.h`` to continue using these functions. + +- ``driver/adc2_wifi_private.h`` has been moved to ``esp_private/adc_share_hw_ctrl.h``. +- Enums ``ADC_UNIT_BOTH``, ``ADC_UNIT_ALTER``, and ``ADC_UNIT_MAX`` in ``adc_unit_t`` have been removed. +- The following enumerations have been removed as some of their enumeration values are not supported on all chips. This would lead to the driver triggering a runtime error if an unsupported value is used. + + - Enum ``ADC_CHANNEL_MAX`` + - Enum ``ADC_ATTEN_MAX`` + - Enum ``ADC_CONV_UNIT_MAX`` + +- API ``hall_sensor_read`` on ESP32 has been removed. Hall sensor is no longer supported on ESP32. - API ``adc_set_i2s_data_source`` and ``adc_i2s_mode_init`` have been deprecated. Related enum ``adc_i2s_source_t`` has been deprecated. Please migrate to use ``esp_adc/adc_continuous.h``. GPIO ---- -The previous Kconfig option `RTCIO_SUPPORT_RTC_GPIO_DESC` has been removed, thus the ``rtc_gpio_desc`` array is unavailable. Please use ``rtc_io_desc`` array instead. +- The previous Kconfig option `RTCIO_SUPPORT_RTC_GPIO_DESC` has been removed, thus the ``rtc_gpio_desc`` array is unavailable. Please use ``rtc_io_desc`` array instead. + +- The user callback of a GPIO interrupt should no longer read the GPIO interrupt status register to get the GPIO's pin number of triggering the interrupt. You should use the callback argument to determine the GPIO's pin number instead. + + - Previously, when a GPIO interrupt occurs, the GPIO's interrupt status register is cleared after calling the user callbacks. Thus, it was possible for users to read the GPIO's interrupt status register inside the callback to determine which GPIO was used to trigger the interrupt. + - However, clearing the interrupt status register after calling the user callbacks can potentially cause edge-triggered interrupts to be lost. For example, if an edge-triggered interrupt (re)is triggered while the user callbacks are being called, that interrupt will be cleared without its registered user callback being handled. + - Now, the GPIO's interrupt status register is cleared **before** invoking the user callbacks. Thus, users can no longer read the GPIO interrupt status register to determine which pin has triggered the interrupt. Instead, users should use the callback argument to pass the pin number. .. only:: SOC_SDM_SUPPORTED Sigma-Delta Modulator --------------------- - The Sigma-Delta Modulator driver has been redesigned into :doc:`SDM <../../api-reference/peripherals/sdm>`. The new driver implements a factory pattern, where the SDM channels are managed in a pool internally, thus you don't have to fix a SDM channel to a GPIO manually. All SDM channels can be allocated dynamically. Although it's recommended to use the new driver APIs, the legacy driver is still available in the previous include path ``driver/sigmadelta.h``. However, by default, including ``driver/sigmadelta.h`` will bring a build warning like ``The legacy sigma-delta driver is deprecated, please use driver/sdm.h``. The warning can be suppressed by Kconfig option :ref:`CONFIG_SDM_SUPPRESS_DEPRECATE_WARN`. + The Sigma-Delta Modulator driver has been redesigned into :doc:`SDM <../../api-reference/peripherals/sdm>`. + + - The new driver implements a factory pattern, where the SDM channels are managed in a pool internally, thus users don't have to fix a SDM channel to a GPIO manually. + - All SDM channels can be allocated dynamically. + + Although it's recommended to use the new driver APIs, the legacy driver is still available in the previous include path ``driver/sigmadelta.h``. However, by default, including ``driver/sigmadelta.h`` will trigger the build warning below. The warning can be suppressed by Kconfig option :ref:`CONFIG_SDM_SUPPRESS_DEPRECATE_WARN`. + + .. code-block:: text + + The legacy sigma-delta driver is deprecated, please use driver/sdm.h The major breaking changes in concept and usage are listed as follows: Breaking Changes in Concepts - ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - SDM channel representation has changed from ``sigmadelta_channel_t`` to :cpp:type:`sdm_channel_handle_t`, which is an opaque pointer. - SDM channel configurations are stored in :cpp:type:`sdm_config_t` now, instead the previous ``sigmadelta_config_t``. - - In the legacy driver, you don't have to set the clock source for SDM channel. But in the new driver, you need to set a proper one in the :cpp:member:`sdm_config_t::clk_src`. The available clock sources are listed in the :cpp:type:`soc_periph_sdm_clk_src_t`. - - In the legacy driver, you need to set a ``prescale`` for the channel, which will reflected into the frequency the modulator output a pulse. In the new driver, you should use :cpp:member:`sdm_config_t::sample_rate_hz`. + - In the legacy driver, users don't have to set the clock source for SDM channel. But in the new driver, users need to set a proper one in the :cpp:member:`sdm_config_t::clk_src`. The available clock sources are listed in the :cpp:type:`soc_periph_sdm_clk_src_t`. + - In the legacy driver, users need to set a ``prescale`` for the channel, which reflects the frequency in which the modulator outputs a pulse. In the new driver, users should use :cpp:member:`sdm_config_t::sample_rate_hz`. Breaking Changes in Usage - ~~~~~~~~~~~~~~~~~~~~~~~~~ + ^^^^^^^^^^^^^^^^^^^^^^^^^ - Channel configuration was done by channel allocation, in :cpp:func:`sdm_new_channel`. In the new driver, only the ``duty`` can be changed at runtime, by :cpp:func:`sdm_channel_set_duty`. Other parameters like ``gpio number`` and ``prescale`` are only allowed to set during channel allocation. - - Before further channel operations, you should **enable** the channel in advance, by calling :cpp:func:`sdm_channel_enable`. This function will help to manage some system level services, like **Power Management**. + - Before further channel operations, users should **enable** the channel in advance, by calling :cpp:func:`sdm_channel_enable`. This function will help to manage some system level services, like **Power Management**. Timer Group Driver ------------------ -Timer Group driver has been redesigned into :doc:`GPTimer <../../api-reference/peripherals/gptimer>`, which aims to unify and simplify the usage of general purpose timer. Although it's recommended to use the the new driver APIs, the legacy driver is still available in the previous include path ``driver/timer.h``. However, by default, including ``driver/timer.h`` will bring a build warning like ``legacy timer group driver is deprecated, please migrate to driver/gptimer.h``. The warning can be suppressed by the Kconfig option :ref:`CONFIG_GPTIMER_SUPPRESS_DEPRECATE_WARN`. +Timer Group driver has been redesigned into :doc:`GPTimer <../../api-reference/peripherals/gptimer>`, which aims to unify and simplify the usage of general purpose timer. + +Although it's recommended to use the new driver APIs, the legacy driver is still available in the previous include path ``driver/timer.h``. However, by default, including ``driver/timer.h`` will trigger the build warning below. The warning can be suppressed by the Kconfig option :ref:`CONFIG_GPTIMER_SUPPRESS_DEPRECATE_WARN`. + +.. code-block:: text + + legacy timer group driver is deprecated, please migrate to driver/gptimer.h The major breaking changes in concept and usage are listed as follows: Breaking Changes in Concepts -~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - ``timer_group_t`` and ``timer_idx_t`` which used to identify the hardware timer are removed from user's code. In the new driver, a timer is represented by :cpp:type:`gptimer_handle_t`. -- Definition of timer source clock is moved to :cpp:type:`gptimer_clock_source_t`, the previous ``timer_src_clk_t`` is not used. +- Definition of timer clock source is moved to :cpp:type:`gptimer_clock_source_t`, the previous ``timer_src_clk_t`` is not used. - Definition of timer count direction is moved to :cpp:type:`gptimer_count_direction_t`, the previous ``timer_count_dir_t`` is not used. - Only level interrupt is supported, ``timer_intr_t`` and ``timer_intr_mode_t`` are not used. - Auto-reload is enabled by set the :cpp:member:`gptimer_alarm_config_t::auto_reload_on_alarm` flag. ``timer_autoreload_t`` is not used. Breaking Changes in Usage -~~~~~~~~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^^^^^^^^ -- Timer initialization is done by creating a timer instance from :cpp:func:`gptimer_new_timer`. Basic configurations like clock source, resolution and direction should be set in :cpp:type:`gptimer_config_t`. Note that, alarm event specific configurations are not needed during the driver install stage. +- Timer initialization is done by creating a timer instance from :cpp:func:`gptimer_new_timer`. Basic configurations like clock source, resolution and direction should be set in :cpp:type:`gptimer_config_t`. Note that, specific configurations of alarm events are not needed during the installation stage of the driver. - Alarm event is configured by :cpp:func:`gptimer_set_alarm_action`, with parameters set in the :cpp:type:`gptimer_alarm_config_t`. -- Setting and getting count value are done by :cpp:func:`gptimer_get_raw_count` and :cpp:func:`gptimer_set_raw_count`. The driver doesn't help convert the raw value into UTC time-stamp. Instead, the conversion should be done form user's side as the timer resolution is also known to the user. -- The driver will install the interrupt service as well if :cpp:member:`gptimer_event_callbacks_t::on_alarm` is set to a valid callback function. In the callback, user doesn't have to deal with the low level registers (like "clear interrupt status", "re-enable alarm event" and so on). So functions like ``timer_group_get_intr_status_in_isr`` and ``timer_group_get_auto_reload_in_isr`` are not used anymore. +- Setting and getting count value are done by :cpp:func:`gptimer_get_raw_count` and :cpp:func:`gptimer_set_raw_count`. The driver doesn't help convert the raw value into UTC time-stamp. Instead, the conversion should be done from user's side as the timer resolution is also known to the user. +- The driver will install the interrupt service as well if :cpp:member:`gptimer_event_callbacks_t::on_alarm` is set to a valid callback function. In the callback, users do not have to deal with the low level registers (like "clear interrupt status", "re-enable alarm event" and so on). So functions like ``timer_group_get_intr_status_in_isr`` and ``timer_group_get_auto_reload_in_isr`` are not used anymore. - To update the alarm configurations when alarm event happens, one can call :cpp:func:`gptimer_set_alarm_action` in the interrupt callback, then the alarm will be re-enabled again. - Alarm will always be re-enabled by the driver if :cpp:member:`gptimer_alarm_config_t::auto_reload_on_alarm` is set to true. UART ---- -+-----------------------------------------------+-----------------------------------------------+----------------------------------------------------------+ -| Removed/Deprecated items | Replacement | Remarks | -+===============================================+===============================================+==========================================================+ -| ``uart_isr_register()`` | None | UART interrupt handling is implemented by driver itself. | -+-----------------------------------------------+-----------------------------------------------+----------------------------------------------------------+ -| ``uart_isr_free()`` | None | UART interrupt handling is implemented by driver itself. | -+-----------------------------------------------+-----------------------------------------------+----------------------------------------------------------+ -| ``use_ref_tick`` in :cpp:type:`uart_config_t` | :cpp:member:`uart_config_t::source_clk` | Select the clock source. | -+-----------------------------------------------+-----------------------------------------------+----------------------------------------------------------+ -| ``uart_enable_pattern_det_intr()`` | :cpp:func:`uart_enable_pattern_det_baud_intr` | Enable pattern detection interrupt. | -+-----------------------------------------------+-----------------------------------------------+----------------------------------------------------------+ +.. list-table:: + :width: 700 px + :header-rows: 1 + + * - Removed/Deprecated items + - Replacement + - Remarks + * - ``uart_isr_register()`` + - None + - UART interrupt handling is implemented by driver itself. + * - ``uart_isr_free()`` + - None + - UART interrupt handling is implemented by driver itself. + * - ``use_ref_tick`` in :cpp:type:`uart_config_t` + - :cpp:member:`uart_config_t::source_clk` + - Select the clock source. + * - ``uart_enable_pattern_det_intr()`` + - :cpp:func:`uart_enable_pattern_det_baud_intr` + - Enable pattern detection interrupt. I2C --- -+--------------------------+-------------+---------------------------------------------------------+ -| Removed/Deprecated items | Replacement | Remarks | -+==========================+=============+=========================================================+ -| ``i2c_isr_register()`` | None | I2C interrupt handling is implemented by driver itself. | -+--------------------------+-------------+---------------------------------------------------------+ -| ``i2c_isr_register()`` | None | I2C interrupt handling is implemented by driver itself. | -+--------------------------+-------------+---------------------------------------------------------+ -| ``i2c_opmode_t`` | None | It's not used anywhere in esp-idf. | -+--------------------------+-------------+---------------------------------------------------------+ +.. list-table:: + :width: 700 px + :header-rows: 1 + + * - Removed/Deprecated items + - Replacement + - Remarks + * - ``i2c_isr_register()`` + - None + - I2C interrupt handling is implemented by driver itself. + * - ``i2c_isr_register()`` + - None + - I2C interrupt handling is implemented by driver itself. + * - ``i2c_opmode_t`` + - None + - It's not used anywhere in esp-idf. SPI --- -+--------------------------+----------------------------------+---------------------------------+ -| Removed/Deprecated items | Replacement | Remarks | -+==========================+==================================+=================================+ -| ``spi_cal_clock()`` | :cpp:func:`spi_get_actual_clock` | Get SPI real working frequency. | -+--------------------------+----------------------------------+---------------------------------+ +.. list-table:: + :width: 700 px + :header-rows: 1 + + * - Removed/Deprecated items + - Replacement + - Remarks + * - ``spi_cal_clock()`` + - :cpp:func:`spi_get_actual_clock` + - Get SPI real working frequency. - The internal header file ``spi_common_internal.h`` has been moved to ``esp_private/spi_common_internal.h``. @@ -126,42 +210,61 @@ SPI SDMMC ----- - +----------------------------+----------------------------------------------+--------------------------+ - | Removed/Deprecated items | Replacement | Remarks | - +============================+==============================================+==========================+ - | ``sdmmc_host_pullup_en()`` | set ``SDMMC_SLOT_FLAG_INTERNAL_PULLUP`` flag | Enable internal pull up. | - | | in :cpp:member:`sdmmc_slot_config_t::flags` | | - +----------------------------+----------------------------------------------+--------------------------+ + .. list-table:: + :width: 700 px + :header-rows: 1 + + * - Removed/Deprecated items + - Replacement + - Remarks + * - ``sdmmc_host_pullup_en()`` + - set ``SDMMC_SLOT_FLAG_INTERNAL_PULLUP`` flag in :cpp:member:`sdmmc_slot_config_t::flags` + - Enable internal pull up. LEDC ----- -+------------------------------------------------+----------------------------------------------------+-----------------------------------+ -| Removed/Deprecated items | Replacement | Remarks | -+================================================+====================================================+===================================+ -| ``bit_num`` in :cpp:type:`ledc_timer_config_t` | :cpp:member:`ledc_timer_config_t::duty_resolution` | Set resolution of the duty cycle. | -+------------------------------------------------+----------------------------------------------------+-----------------------------------+ +.. list-table:: + :width: 700 px + :header-rows: 1 + + * - Removed/Deprecated items + - Replacement + - Remarks + * - ``bit_num`` in :cpp:type:`ledc_timer_config_t` + - :cpp:member:`ledc_timer_config_t::duty_resolution` + - Set resolution of the duty cycle. .. only:: SOC_PCNT_SUPPORTED Pulse Counter Driver -------------------- - Pulse counter driver has been redesigned (see :doc:`PCNT <../../api-reference/peripherals/pcnt>`), which aims to unify and simplify the usage of PCNT peripheral. Although it's recommended to use the new driver APIs, the legacy driver is still available in the previous include path ``driver/pcnt.h``. However, by default, including ``driver/pcnt.h`` will bring a build warning like `legacy pcnt driver is deprecated, please migrate to use driver/pulse_cnt.h`. The warning can be suppressed by the Kconfig option :ref:`CONFIG_PCNT_SUPPRESS_DEPRECATE_WARN`. + Pulse counter driver has been redesigned (see :doc:`PCNT <../../api-reference/peripherals/pcnt>`), which aims to unify and simplify the usage of PCNT peripheral. + + Although it's recommended to use the new driver APIs, the legacy driver is still available in the previous include path ``driver/pcnt.h``. However, including ``driver/pcnt.h`` will trigger the build warning below by default. The warning can be suppressed by the Kconfig option :ref:`CONFIG_PCNT_SUPPRESS_DEPRECATE_WARN`. + + .. code-block:: text + + legacy pcnt driver is deprecated, please migrate to use driver/pulse_cnt.h The major breaking changes in concept and usage are listed as follows: Breaking Changes in Concepts - ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - ``pcnt_port_t``, ``pcnt_unit_t`` and ``pcnt_channel_t`` which used to identify the hardware unit and channel are removed from user's code. In the new driver, PCNT unit is represented by :cpp:type:`pcnt_unit_handle_t`, likewise, PCNT channel is represented by :cpp:type:`pcnt_channel_handle_t`. Both of them are opaque pointers. - ``pcnt_evt_type_t`` is not used any more, they have been replaced by a universal **Watch Point Event**. In the event callback :cpp:type:`pcnt_watch_cb_t`, it's still possible to distinguish different watch points from :cpp:type:`pcnt_watch_event_data_t`. - ``pcnt_count_mode_t`` is replaced by :cpp:type:`pcnt_channel_edge_action_t`, and ``pcnt_ctrl_mode_t`` is replaced by :cpp:type:`pcnt_channel_level_action_t`. Breaking Changes in Usage - ~~~~~~~~~~~~~~~~~~~~~~~~~ + ^^^^^^^^^^^^^^^^^^^^^^^^^ + + - Previously, the PCNT unit configuration and channel configuration were combined into a single function: ``pcnt_unit_config``. They are now split into the two factory APIs: :cpp:func:`pcnt_new_unit` and :cpp:func:`pcnt_new_channel` respectively. + + - Only the count range is necessary for initializing a PCNT unit. GPIO number assignment has been moved to :cpp:func:`pcnt_new_channel`. + - High/Low control mode and positive/negative edge count mode are set by stand-alone functions: :cpp:func:`pcnt_channel_set_edge_action` and :cpp:func:`pcnt_channel_set_level_action`. - - In the legacy driver, the PCNT unit configuration and channel configuration were combined into a single function: ``pcnt_unit_config``. Now this is split into two factory APIs: :cpp:func:`pcnt_new_unit` and :cpp:func:`pcnt_new_channel`. Only the count range is necessary for initializing a PCNT unit. GPIO number assignment has been moved to :cpp:func:`pcnt_new_channel`. High/Low control mode and positive/negative edge count mode are set by stand-alone functions: :cpp:func:`pcnt_channel_set_edge_action` and :cpp:func:`pcnt_channel_set_level_action`. - ``pcnt_get_counter_value`` is replaced by :cpp:func:`pcnt_unit_get_count`. - ``pcnt_counter_pause`` is replaced by :cpp:func:`pcnt_unit_stop`. - ``pcnt_counter_resume`` is replaced by :cpp:func:`pcnt_unit_start`. @@ -170,9 +273,9 @@ LEDC - ``pcnt_event_enable`` and ``pcnt_event_disable`` are removed. In the new driver, the PCNT events are enabled/disabled by adding/removing watch points :cpp:func:`pcnt_unit_add_watch_point`, :cpp:func:`pcnt_unit_remove_watch_point`. - ``pcnt_set_event_value`` is removed. In the new driver, event value is also set when adding watch point by :cpp:func:`pcnt_unit_add_watch_point`. - ``pcnt_get_event_value`` and ``pcnt_get_event_status`` are removed. In the new driver, these information are provided by event callback :cpp:type:`pcnt_watch_cb_t` in the :cpp:type:`pcnt_watch_event_data_t`. - - ``pcnt_isr_register`` and ``pcnt_isr_unregister`` are removed. Register of the ISR handler from user code is no longer permitted. Users should register event callbacks instead by calling :cpp:func:`pcnt_unit_register_event_callbacks`. - - ``pcnt_set_pin`` is removed and the new driver no longer allows the switching of the GPIO at runtime. If you want to change to other GPIOs, please delete the existing PCNT channel by :cpp:func:`pcnt_del_channel` and reinstall with the new GPIO number by :cpp:func:`pcnt_new_channel`. - - ``pcnt_filter_enable``, ``pcnt_filter_disable``, and ``pcnt_set_filter_value`` are replaced by :cpp:func:`pcnt_unit_set_glitch_filter`. Meanwhile, ``pcnt_get_filter_value`` has been removed. + - ``pcnt_isr_register`` and ``pcnt_isr_unregister`` are removed. Register of the ISR handler from user's code is no longer permitted. Users should register event callbacks instead by calling :cpp:func:`pcnt_unit_register_event_callbacks`. + - ``pcnt_set_pin`` is removed and the new driver no longer allows the switching of the GPIO at runtime. If users want to change to other GPIOs, please delete the existing PCNT channel by :cpp:func:`pcnt_del_channel` and reinstall with the new GPIO number by :cpp:func:`pcnt_new_channel`. + - ``pcnt_filter_enable``, ``pcnt_filter_disable`` and ``pcnt_set_filter_value`` are replaced by :cpp:func:`pcnt_unit_set_glitch_filter`. Meanwhile, ``pcnt_get_filter_value`` has been removed. - ``pcnt_set_mode`` is replaced by :cpp:func:`pcnt_channel_set_edge_action` and :cpp:func:`pcnt_channel_set_level_action`. - ``pcnt_isr_service_install``, ``pcnt_isr_service_uninstall``, ``pcnt_isr_handler_add`` and ``pcnt_isr_handler_remove`` are replaced by :cpp:func:`pcnt_unit_register_event_callbacks`. The default ISR handler is lazy installed in the new driver. @@ -181,38 +284,50 @@ LEDC Temperature Sensor Driver ------------------------- - - Old API header ``temp_sensor.h`` has been redesigned as ``temperature_sensor.h``, it is recommended to use the new driver and the old driver is not allowed to be used at the same time. - - Although it's recommended to use the new driver APIs, the legacy driver is still available in the previous include path ``driver/temp_sensor.h``. However, by default, including ``driver/temp_sensor.h`` will bring a build warning like "legacy temperature sensor driver is deprecated, please migrate to driver/temperature_sensor.h". The warning can be suppressed by enabling the menuconfig option :ref:`CONFIG_TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN`. - - Configuration contents has been changed. In old version, user need to configure the ``clk_div`` and ``dac_offset``. While in new version, user only need to choose ``tsens_range`` - - The process of using temperature sensor has been changed. In old version, user can use ``config->start->read_celsius`` to get value. In the new version, user must install the temperature sensor driver firstly, by ``temperature_sensor_install`` and uninstall it when finished. For more information, you can refer to :doc:`Temperature Sensor <../../api-reference/peripherals/temp_sensor>` . + The temperature sensor driver has been redesigned and it is recommended to use the new driver. However, the old driver is still available but cannot be used with the new driver simultaneously. + + The new driver can be included via ``driver/temperature_sensor.h``. The old driver is still available in the previous include path ``driver/temp_sensor.h``. However, including ``driver/temp_sensor.h`` will trigger the build warning below by default. The warning can be suppressed by enabling the menuconfig option :ref:`CONFIG_TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN`. + + .. code-block:: text + + legacy temperature sensor driver is deprecated, please migrate to driver/temperature_sensor.h + + Configuration contents has been changed. In the old version, users need to configure ``clk_div`` and ``dac_offset``. While in the new version, users only need to choose ``tsens_range``. + + The process of using temperature sensor has been changed. In the old version, users can use ``config->start->read_celsius`` to get value. In the new version, users should install the temperature sensor driver firstly, by ``temperature_sensor_install`` and uninstall it when finished. For more information, please refer to :doc:`Temperature Sensor <../../api-reference/peripherals/temp_sensor>` . .. only:: SOC_RMT_SUPPORTED RMT Driver ---------- - RMT driver has been redesigned (see :doc:`RMT transceiver <../../api-reference/peripherals/rmt>`), which aims to unify and extend the usage of RMT peripheral. Although it's recommended to use the new driver APIs, the legacy driver is still available in the previous include path ``driver/rmt.h``. However, by default, including ``driver/rmt.h`` will bring a build warning like `The legacy RMT driver is deprecated, please use driver/rmt_tx.h and/or driver/rmt_rx.h`. The warning can be suppressed by the Kconfig option :ref:`CONFIG_RMT_SUPPRESS_DEPRECATE_WARN`. + RMT driver has been redesigned (see :doc:`RMT transceiver <../../api-reference/peripherals/rmt>`), which aims to unify and extend the usage of RMT peripheral. + + Although it's recommended to use the new driver APIs, the legacy driver is still available in the previous include path ``driver/rmt.h``. However, including ``driver/rmt.h`` will trigger the build warning below by default. The warning can be suppressed by the Kconfig option :ref:`CONFIG_RMT_SUPPRESS_DEPRECATE_WARN`. + + .. code-block:: text + + The legacy RMT driver is deprecated, please use driver/rmt_tx.h and/or driver/rmt_rx.h The major breaking changes in concept and usage are listed as follows: Breaking Changes in Concepts - ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - ``rmt_channel_t`` which used to identify the hardware channel are removed from user space. In the new driver, RMT channel is represented by :cpp:type:`rmt_channel_handle_t`. The channel is dynamic allocated by the driver, instead of designated by user. + - ``rmt_channel_t`` which used to identify the hardware channel are removed from user space. In the new driver, RMT channel is represented by :cpp:type:`rmt_channel_handle_t`. The channel is dynamically allocated by the driver, instead of designated by user. - ``rmt_item32_t`` is replaced by :cpp:type:`rmt_symbol_word_t`, which avoids a nested union inside a struct. - ``rmt_mem_t`` is removed, as we don't allow users to access RMT memory block (a.k.an RMTMEM) directly. Direct access to RMTMEM doesn't make sense but make mistakes, especially when the RMT channel also connected with a DMA channel. - - ``rmt_mem_owner_t`` is removed, as the ownership is controller by driver, not by user anymore. - - ``rmt_source_clk_t`` is replaced by :cpp:type:`rmt_clock_source_t`, note they're not binary compatible. + - ``rmt_mem_owner_t`` is removed, as the ownership is controlled by driver, not by user anymore. + - ``rmt_source_clk_t`` is replaced by :cpp:type:`rmt_clock_source_t`, and note they're not binary compatible. - ``rmt_data_mode_t`` is removed, the RMT memory access mode is configured to always use Non-FIFO and DMA mode. - ``rmt_mode_t`` is removed, as the driver has stand alone install functions for TX and RX channels. - ``rmt_idle_level_t`` is removed, setting IDLE level for TX channel is available in :cpp:member:`rmt_transmit_config_t::eot_level`. - ``rmt_carrier_level_t`` is removed, setting carrier polarity is available in :cpp:member:`rmt_carrier_config_t::polarity_active_low`. - ``rmt_channel_status_t`` and ``rmt_channel_status_result_t`` are removed, they're not used anywhere. - - transmitting by RMT channel doesn't expect user to prepare the RMT symbols, instead, user needs to provide an RMT Encoder to tell the driver how to convert user data into RMT symbols. - + - Transmitting by RMT channel doesn't expect user to prepare the RMT symbols, instead, user needs to provide an RMT Encoder to tell the driver how to convert user data into RMT symbols. Breaking Changes in Usage - ~~~~~~~~~~~~~~~~~~~~~~~~~ + ^^^^^^^^^^^^^^^^^^^^^^^^^ - Channel installation has been separated for TX and RX channels into :cpp:func:`rmt_new_tx_channel` and :cpp:func:`rmt_new_rx_channel`. - ``rmt_set_clk_div`` and ``rmt_get_clk_div`` are removed. Channel clock configuration can only be done during channel installation. @@ -248,30 +363,39 @@ LEDC LCD --- -- The LCD panel initialization flow is slightly changed. Now the :cpp:func:`esp_lcd_panel_init` won't turn on the display automatically. User needs to call :cpp:func:`esp_lcd_panel_disp_on_off` to manually turn on the display. Note, this is different from turning on backlight. With this breaking change, user can flush a predefined pattern to the screen before turning on the screen. This can help avoid random noise on the screen after a power on reset. +- The LCD panel initialization flow is slightly changed. Now the :cpp:func:`esp_lcd_panel_init` won't turn on the display automatically. User needs to call :cpp:func:`esp_lcd_panel_disp_on_off` to manually turn on the display. Note, this is different from turning on backlight. With this breaking change, user can flash a predefined pattern to the screen before turning on the screen. This can help avoid random noise on the screen after a power on reset. - :cpp:func:`esp_lcd_panel_disp_off` is deprecated, please use :cpp:func:`esp_lcd_panel_disp_on_off` instead. -- ``dc_as_cmd_phase`` is removed. The SPI LCD driver currently doesn't support a 9bit SPI LCD. Please always use a dedicated GPIO to control the LCD D/C line. +- ``dc_as_cmd_phase`` is removed. The SPI LCD driver currently doesn't support a 9-bit SPI LCD. Please always use a dedicated GPIO to control the LCD D/C line. - The way to register RGB panel event callbacks has been moved from the :cpp:type:`esp_lcd_rgb_panel_config_t` into a separate API :cpp:func:`esp_lcd_rgb_panel_register_event_callbacks`. However, the event callback signature is not changed. - Previous ``relax_on_idle`` flag in :cpp:type:`esp_lcd_rgb_panel_config_t` has been renamed into :cpp:member:`esp_lcd_rgb_panel_config_t::refresh_on_demand`, which expresses the same meaning but with a clear name. -- If the RGB LCD is created with the ``refresh_on_demand`` flag enabled, the driver won't start a refresh in the :cpp:func:`esp_lcd_panel_draw_bitmap`. Now you have to call :cpp:func:`esp_lcd_rgb_panel_refresh` to refresh the screen by yourself. +- If the RGB LCD is created with the ``refresh_on_demand`` flag enabled, the driver won't start a refresh in the :cpp:func:`esp_lcd_panel_draw_bitmap`. Now users have to call :cpp:func:`esp_lcd_rgb_panel_refresh` to refresh the screen by themselves. +- :cpp:type:`esp_lcd_color_space_t` is deprecated, please use :cpp:type:`lcd_color_space_t` to describe the color space, and use :cpp:type:`lcd_color_rgb_endian_t` to describe the data order of RGB color. .. only:: SOC_MCPWM_SUPPORTED MCPWM ----- - MCPWM driver was redesigned (see :doc:`MCPWM <../../api-reference/peripherals/mcpwm>`), meanwhile, the legacy driver is deprecated. The new driver's aim is to make each MCPWM submodule independent to each other, and give the freedom of resource connection back to users. Although it's recommended to use the new driver APIs, the legacy driver is still available in the previous include path ``driver/mcpwm.h``. However, by default, using legacy driver will bring compile warnings like ``legacy MCPWM driver is deprecated, please migrate to the new driver (include driver/mcpwm_prelude.h)``. This warning can be suppressed by the Kconfig option :ref:`CONFIG_MCPWM_SUPPRESS_DEPRECATE_WARN`. + MCPWM driver was redesigned (see :doc:`MCPWM <../../api-reference/peripherals/mcpwm>`), meanwhile, the legacy driver is deprecated. + + The new driver's aim is to make each MCPWM submodule independent to each other, and give the freedom of resource connection back to users. + + Although it's recommended to use the new driver APIs, the legacy driver is still available in the previous include path ``driver/mcpwm.h``. However, using legacy driver will rigger the build warning below by default. This warning can be suppressed by the Kconfig option :ref:`CONFIG_MCPWM_SUPPRESS_DEPRECATE_WARN`. + + .. code-block:: text + + legacy MCPWM driver is deprecated, please migrate to the new driver (include driver/mcpwm_prelude.h) The major breaking changes in concept and usage are listed as follows: Breaking Changes in Concepts - ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ The new MCPWM driver is object-oriented, where most of the MCPWM submodule has a driver object associated with it. The driver object is created by factory function like :cpp:func:`mcpwm_new_timer`. IO control function always needs an object handle, in the first place. The legacy driver has an inappropriate assumption, that is the MCPWM operator should be connected to different MCPWM timer. In fact, the hardware doesn't have such limitation. In the new driver, a MCPWM timer can be connected to multiple operators, so that the operators can achieve the best synchronization performance. - The legacy driver preset the way to generate a PWM waveform into a so called ``mcpwm_duty_type_t``, however, the duty cycle modes listed there are far from sufficient. Likewise, legacy driver has several preset ``mcpwm_deadtime_type_t``, which also doesn't cover all the use cases. What's more, user usually gets confused by the name of the duty cycle mode and dead-time mode. In the new driver, there're no such limitation, but user has to construct the generator behavior from scratch. + The legacy driver presets the way to generate a PWM waveform into a so called ``mcpwm_duty_type_t``. However, the duty cycle modes listed there are far from sufficient. Likewise, legacy driver has several preset ``mcpwm_deadtime_type_t``, which also doesn't cover all the use cases. What's more, user usually gets confused by the name of the duty cycle mode and dead-time mode. In the new driver, there're no such limitation, but user has to construct the generator behavior from scratch. In the legacy driver, the ways to synchronize the MCPWM timer by GPIO, software and other timer module are not unified. It increased learning costs for users. In the new driver, the synchronization APIs are unified. @@ -285,18 +409,18 @@ LCD - ``mcpwm_capture_signal_t`` is not used. A capture channel is represented by :cpp:type:`mcpwm_cap_channel_handle_t`. Breaking Changes in Usage - ~~~~~~~~~~~~~~~~~~~~~~~~~ + ^^^^^^^^^^^^^^^^^^^^^^^^^ - ``mcpwm_gpio_init`` and ``mcpwm_set_pin``: GPIO configurations are moved to submodule's own configuration. e.g. set the PWM GPIO in :cpp:member:`mcpwm_generator_config_t::gen_gpio_num`. - - ``mcpwm_init``: To get an expected PWM waveform, you need to allocated at least one MCPWM timer and MCPWM operator, then connect them by calling :cpp:func:`mcpwm_operator_connect_timer`. After that, you should set the generator's actions on various events by calling e.g. :cpp:func:`mcpwm_generator_set_actions_on_timer_event`, :cpp:func:`mcpwm_generator_set_actions_on_compare_event`. + - ``mcpwm_init``: To get an expected PWM waveform, users need to allocated at least one MCPWM timer and MCPWM operator, then connect them by calling :cpp:func:`mcpwm_operator_connect_timer`. After that, users should set the generator's actions on various events by calling e.g. :cpp:func:`mcpwm_generator_set_actions_on_timer_event`, :cpp:func:`mcpwm_generator_set_actions_on_compare_event`. - ``mcpwm_group_set_resolution``: in the new driver, the group resolution is fixed to the maximum, usually it's 80MHz. - ``mcpwm_timer_set_resolution``: MCPWM Timer resolution is set in :cpp:member:`mcpwm_timer_config_t::resolution_hz`. - ``mcpwm_set_frequency``: PWM frequency is determined by :cpp:member:`mcpwm_timer_config_t::resolution_hz`, :cpp:member:`mcpwm_timer_config_t::count_mode` and :cpp:member:`mcpwm_timer_config_t::period_ticks`. - - ``mcpwm_set_duty``: To set the PWM duty cycle, you should call :cpp:func:`mcpwm_comparator_set_compare_value` to change comparator's threshold. - - ``mcpwm_set_duty_type``: There won't be any preset duty types, the duty type is configured by setting different generator actions. e.g. :cpp:func:`mcpwm_generator_set_actions_on_timer_event`. + - ``mcpwm_set_duty``: To set the PWM duty cycle, users should call :cpp:func:`mcpwm_comparator_set_compare_value` to change comparator's threshold. + - ``mcpwm_set_duty_type``: There won't be any preset duty cycle types, the duty cycle type is configured by setting different generator actions. e.g. :cpp:func:`mcpwm_generator_set_actions_on_timer_event`. - ``mcpwm_set_signal_high`` and ``mcpwm_set_signal_low`` are replaced by :cpp:func:`mcpwm_generator_set_force_level`. In the new driver, it's implemented by setting force action for the generator, instead of changing the duty cycle to 0% or 100% at the background. - ``mcpwm_start`` and ``mcpwm_stop`` are replaced by :cpp:func:`mcpwm_timer_start_stop`. You have more modes to start and stop the MCPWM timer, see :cpp:type:`mcpwm_timer_start_stop_cmd_t`. - - ``mcpwm_carrier_init``: It's replaced by :cpp:func:`mcpwm_operator_apply_carrier`. + - ``mcpwm_carrier_init`` is replaced by :cpp:func:`mcpwm_operator_apply_carrier`. - ``mcpwm_carrier_enable`` and ``mcpwm_carrier_disable``: Enabling and disabling carrier submodule is done automatically by checking whether the carrier configuration structure :cpp:type:`mcpwm_carrier_config_t` is NULL. - ``mcpwm_carrier_set_period`` is replaced by :cpp:member:`mcpwm_carrier_config_t::frequency_hz`. - ``mcpwm_carrier_set_duty_cycle`` is replaced by :cpp:member:`mcpwm_carrier_config_t::duty_cycle`. @@ -308,7 +432,7 @@ LCD - ``mcpwm_fault_set_oneshot_mode``, ``mcpwm_fault_set_cyc_mode`` are replaced by :cpp:func:`mcpwm_operator_set_brake_on_fault` and :cpp:func:`mcpwm_generator_set_actions_on_brake_event`. - ``mcpwm_capture_enable`` is removed. It's duplicated to :cpp:func:`mcpwm_capture_enable_channel`. - ``mcpwm_capture_disable`` is removed. It's duplicated to :cpp:func:`mcpwm_capture_capture_disable_channel`. - - ``mcpwm_capture_enable_channel`` and ``mcpwm_capture_disable_channel`` are replaced by :cpp:func:`mcpwm_new_capture_channel` and :cpp:func:`mcpwm_del_capture_channel`. + - ``mcpwm_capture_enable_channel`` and ``mcpwm_capture_disable_channel`` are replaced by :cpp:func:`mcpwm_capture_channel_enable` and :cpp:func:`mcpwm_capture_channel_disable`. - ``mcpwm_capture_signal_get_value`` and ``mcpwm_capture_signal_get_edge``: Capture timer count value and capture edge are provided in the capture event callback, via :cpp:type:`mcpwm_capture_event_data_t`. Capture data are only valuable when capture event happens. Providing single API to fetch capture data is meaningless. - ``mcpwm_sync_enable`` is removed. It's duplicated to :cpp:func:`mcpwm_sync_configure`. - ``mcpwm_sync_configure`` is replaced by :cpp:func:`mcpwm_timer_set_phase_on_sync`. @@ -316,85 +440,94 @@ LCD - ``mcpwm_set_timer_sync_output`` is replaced by :cpp:func:`mcpwm_new_timer_sync_src`. - ``mcpwm_timer_trigger_soft_sync`` is replaced by :cpp:func:`mcpwm_soft_sync_activate`. - ``mcpwm_sync_invert_gpio_synchro`` is equivalent to setting :cpp:member:`mcpwm_gpio_sync_src_config_t::active_neg`. - - ``mcpwm_isr_register`` is removed. You can register various event callbacks instead. For example, to register capture event callback, you can use :cpp:func:`mcpwm_capture_channel_register_event_callbacks`. + - ``mcpwm_isr_register`` is removed. You can register various event callbacks instead. For example, to register capture event callback, users can use :cpp:func:`mcpwm_capture_channel_register_event_callbacks`. .. only:: SOC_DEDICATED_GPIO_SUPPORTED Dedicated GPIO Driver --------------------- - - All of the dedicated GPIO related LL functionsn in ``cpu_ll.h`` have been moved to ``dedic_gpio_cpu_ll.h`` and renamed. + - All of the dedicated GPIO related Low Level (LL) functions in ``cpu_ll.h`` have been moved to ``dedic_gpio_cpu_ll.h`` and renamed. .. only:: SOC_I2S_SUPPORTED I2S driver ---------- - Shortcomings are exposed when supporting all the new features of ESP32-C3 & ESP32-S3 by the old I2S driver, so it is re-designed to make it more compatible and flexible to all the communication modes. New APIs are available by including corresponding mode header files :component_file:`driver/include/driver/i2s_std.h`, :component_file:`driver/include/driver/i2s_pdm.h` or :component_file:`driver/include/driver/i2s_tdm.h`. Meanwhile, the old APIs in :component_file:`driver/deprecated/driver/i2s.h` are still supported for backward compatibility. But there will be warnings if you keep using the old APIs in your project, these warnings can be suppressed by the Kconfig option :ref:`CONFIG_I2S_SUPPRESS_DEPRECATE_WARN`. Here is the general overview of the current I2S files: + The I2S driver has been redesigned (see :doc:`I2S Driver <../../api-reference/peripherals/i2s>`), which aims to rectify the shortcomings of the driver that were exposed when supporting all the new features of ESP32-C3 & ESP32-S3. The new driver's APIs are available by including corresponding I2S mode's header files :component_file:`driver/include/driver/i2s_std.h`, :component_file:`driver/include/driver/i2s_pdm.h`, or :component_file:`driver/include/driver/i2s_tdm.h`. + + Meanwhile, the old driver's APIs in :component_file:`driver/deprecated/driver/i2s.h` are still supported for backward compatibility. But there will be warnings if users keep using the old APIs in their projects, these warnings can be suppressed by the Kconfig option :ref:`CONFIG_I2S_SUPPRESS_DEPRECATE_WARN`. + + Here is the general overview of the current I2S files: .. figure:: ../../../_static/diagrams/i2s/i2s_file_structure.png :align: center :alt: I2S File Structure Breaking changes in Concepts - ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - The minimum control unit in new I2S driver will be tx/rx channel instead of a whole I2S controller. + Independent TX/RX channels + """""""""""""""""""""""""" - 1. The tx/rx channel in a same I2S controller can be controlled separately, that means they will be initialized, started or stopped separately. Especially for ESP32-C3 and ESP32-S3, tx and rx channels in one controller can be configured to different clocks or modes now, they are able to work in a totally separate way which can help to save the resources of I2S controller. But for ESP32 and ESP32-S2, though their tx/rx can be controlled separately, some hardware resources are still shared by tx and rx, they might affect each other if they are configured to different configurations; - 2. The channels can be registered to an available I2S controller automatically by setting :cpp:enumerator:`i2s_port_t::I2S_NUM_AUTO` as I2S port id. The driver will help you to search for the available tx/rx channel. Of cause, driver can still support to be installed by a specific port; - 3. :c:type:`i2s_chan_handle_t` is the handle that used for identifying the I2S channels. All the APIs will require the channel handle, users need to maintain the channel handles by themselves; - 4. In order to distinguish tx/rx channel and sound channel, now the word 'channel' is only stand for the tx/rx channel in new driver, meanwhile the sound channel will be called 'slot'. + The minimum control unit in new I2S driver are now individual TX/RX channels instead of an entire I2S controller (that consistes of multiple channels). - - I2S communication modes are extracted into three modes. + - The TX and RX channels of the same I2S controller can be controlled separately, meaning that they are configured such that they can be started or stopped separately. + - The c:type:`i2s_chan_handle_t` handle type is used to uniquely identify I2S channels. All the APIs will require the channel handle and users need to maintain the channel handles by themselves. + - On the ESP32-C3 and ESP32-S3, TX and RX channels in the same controller can be configured to different clocks or modes. + - However, on the ESP32 and ESP32-S2, the TX and RX channels of the same controller still share some hardware resources. Thus, configurations may cause one channel to affect another channel in the same controller. + - The channels can be registered to an available I2S controller automatically by setting :cpp:enumerator:`i2s_port_t::I2S_NUM_AUTO` as I2S port ID which will cause the driver to search for the available TX/RX channels. However, the driver also supports registering channels to a specific port. + - In order to distinguish between TX/RX channels and sound channels, the term 'channel' in the context of the I2S driver will only refer to TX/RX channels. Meanwhile, sound channels will be referred to as "slots". - 1. **Standard mode**: Standard mode always has two slots, it can support Philip, MSB and PCM(short sync) format, please refer to :component_file:`driver/include/driver/i2s_std.h` for details; - 2. **PDM mode**: PDM mode only support two slots with 16 bits data width, but the configurations of PDM TX and PDM RX are little bit different. For PDM TX, the sample rate can be set by :cpp:member:`i2s_pdm_tx_clk_config_t::sample_rate`, and its clock frequency is depended on the up-sampling configuration. For PDM RX, the sample rate can be set by :cpp:member:`i2s_pdm_rx_clk_config_t::sample_rate`, and its clock frequency is depended on the down-sampling configuration. Please refer to :component_file:`driver/include/driver/i2s_pdm.h` for details; - 3. **TDM mode**: TDM mode can support upto 16 slots. It can work in Philip, MSB, PCM(short sync) and PCM(long sync) format, please refer to :component_file:`driver/include/driver/i2s_tdm.h` for details; - 4. When allocating a new channel in a specific mode, must initialize this channel by corresponding function. It is strongly recommended to use the helper macros to generate the default configurations, in case the default values will be changed one day. + I2S Mode Categorization + """""""""""""""""""""""" + + I2S communication modes are categorized into the following three modes. Note that: + + - **Standard mode**: Standard mode always has two slots, it can support Philips, MSB, and PCM (short frame sync) formats. Please refer to :component_file:`driver/include/driver/i2s_std.h` for more details. + - **PDM mode**: PDM mode only supports two slots with 16-bit data width, but the configurations of PDM TX and PDM RX are slightly different. For PDM TX, the sample rate can be set by :cpp:member:`i2s_pdm_tx_clk_config_t::sample_rate`, and its clock frequency depends on the up-sampling configuration. For PDM RX, the sample rate can be set by :cpp:member:`i2s_pdm_rx_clk_config_t::sample_rate`, and its clock frequency depends on the down-sampling configuration. Please refer to :component_file:`driver/include/driver/i2s_pdm.h` for details. + - **TDM mode**: TDM mode can support up to 16 slots. It can work in Philips, MSB, PCM (short frame sync), and PCM (long frame sync) formats. Please refer to :component_file:`driver/include/driver/i2s_tdm.h` for details. + + When allocating a new channel in a specific mode, users should initialize that channel by its corresponding function. It is strongly recommended to use the helper macros to generate the default configurations in case the default values are changed in the future. + + Independent Slot and Clock Configuration + """""""""""""""""""""""""""""""""""""""" + + The slot configurations and clock configurations can be configured separately. + + - Call :cpp:func:`i2s_channel_init_std_mode`, :cpp:func:`i2s_channel_init_pdm_rx_mode`, :cpp:func:`i2s_channel_init_pdm_tx_mode`, or :cpp:func:`i2s_channel_init_tdm_mode` to initialize the slot/clock/gpio_pin configurations. + - Calling :cpp:func:`i2s_channel_reconfig_std_slot`, :cpp:func:`i2s_channel_reconfig_pdm_rx_slot`, :cpp:func:`i2s_channel_reconfig_pdm_tx_slot`, or :cpp:func:`i2s_channel_reconfig_tdm_slot` can change the slot configurations after initialization. + - Calling :cpp:func:`i2s_channel_reconfig_std_clock`, :cpp:func:`i2s_channel_reconfig_pdm_rx_clock`, :cpp:func:`i2s_channel_reconfig_pdm_tx_clock`, or :cpp:func:`i2s_channel_reconfig_tdm_clock` can change the clock configurations after initialization. + - Calling :cpp:func:`i2s_channel_reconfig_std_gpio`, :cpp:func:`i2s_channel_reconfig_pdm_rx_gpio`, :cpp:func:`i2s_channel_reconfig_pdm_tx_gpio`, or :cpp:func:`i2s_channel_reconfig_tdm_gpio` can change the GPIO configurations after initialization. + + Misc + """" - States and state-machine are adopted in the new I2S driver to avoid APIs called in wrong state. - - - The slot configurations and clock configurations can be configured separately. - - 1. Calling :cpp:func:`i2s_channel_init_std_mode`, :cpp:func:`i2s_channel_init_pdm_rx_mode`, :cpp:func:`i2s_channel_init_pdm_tx_mode` or :cpp:func:`i2s_channel_init_tdm_mode` to initialize the slot/clock/gpio_pin configurations; - 2. Calling :cpp:func:`i2s_channel_reconfig_std_slot`, :cpp:func:`i2s_channel_reconfig_pdm_rx_slot`, :cpp:func:`i2s_channel_reconfig_pdm_tx_slot` or :cpp:func:`i2s_channel_reconfig_tdm_slot` can change the slot configurations after initialization; - 3. Calling :cpp:func:`i2s_channel_reconfig_std_clock`, :cpp:func:`i2s_channel_reconfig_pdm_rx_clock`, :cpp:func:`i2s_channel_reconfig_pdm_tx_clock` or :cpp:func:`i2s_channel_reconfig_tdm_clock` can change the clock configurations after initialization; - 4. Calling :cpp:func:`i2s_channel_reconfig_std_gpio`, :cpp:func:`i2s_channel_reconfig_pdm_rx_gpio`, :cpp:func:`i2s_channel_reconfig_pdm_tx_gpio` or :cpp:func:`i2s_channel_reconfig_tdm_gpio` can change the gpio configurations after initialization. - - - ADC and DAC modes are removed. They will only be supported in their own driver and legacy I2S driver. - - - :cpp:func:`i2s_channel_write` and :cpp:func:`i2s_channel_read` can be aborted by :cpp:func:`i2s_channel_abort_reading_writing` now. + - ADC and DAC modes are removed. They will only be supported in their own drivers and the legacy I2S driver. Breaking Changes in Usage - ~~~~~~~~~~~~~~~~~~~~~~~~~ + ^^^^^^^^^^^^^^^^^^^^^^^^^ To use the new I2S driver, please follow these steps: - 1. Calling :cpp:func:`i2s_new_channel` to aquire the channel handles. We should specify the work role and I2S port in this step. Besides, the tx or rx channel handles will be generated by the driver. Inputting both two tx and rx handles is not necessary but at least one handle is needed. In the case of inputting both two handles, the driver will work at duplex mode, both tx and rx channel will be avaliable on a same port, and they will share the MCLK, BCLK and WS signal. But if only one of the tx or rx handle is inputted, this channel will only work in simplex mode. + 1. Call :cpp:func:`i2s_new_channel` to acquire channel handles. We should specify the work role and I2S port in this step. Besides, the TX or RX channel handle will be generated by the driver. Inputting both two TX and RX channel handles is not necessary but at least one handle is needed. In the case of inputting both two handles, the driver will work at the duplex mode. Both TX and RX channels will be avaliable on a same port, and they will share the MCLK, BCLK and WS signal. But if only one of the TX or RX channel handle is inputted, this channel will only work in the simplex mode. + 2. Call :func:`i2s_channel_init_std_mode`, :func:`i2s_channel_init_pdm_rx_mode`, :func:`i2s_channel_init_pdm_tx_mode` or :func:`i2s_channel_init_tdm_mode` to initialize the channel to the specified mode. Corresponding slot, clock and GPIO configurations are needed in this step. + 3. (Optional) Call :cpp:func:`i2s_channel_register_event_callback` to register the ISR event callback functions. I2S events now can be received by the callback function synchronously, instead of from the event queue asynchronously. + 4. Call :cpp:func:`i2s_channel_enable` to start the hardware of I2S channel. In the new driver, I2S won't start automatically after installed, and users are supposed to know clearly whether the channel has started or not. + 5. Read or write data by :cpp:func:`i2s_channel_read` or :cpp:func:`i2s_channel_write`. Certainly, only the RX channel handle is suppoesd to be inputted in :cpp:func:`i2s_channel_read` and the TX channel handle in :cpp:func:`i2s_channel_write`. + 6. (Optional) The slot, clock and GPIO configurations can be changed by corresponding 'reconfig' functions, but :cpp:func:`i2s_channel_disable` must be called before updating the configurations. + 7. Call :cpp:func:`i2s_channel_disable` to stop the hardware of I2S channel. + 8. Call :cpp:func:`i2s_del_channel` to delete and release the resources of the channel if it is not needed any more, but the channel must be disabled before deleting it. - 2. Calling :func:`i2s_channel_init_std_mode`, :func:`i2s_channel_init_pdm_rx_mode`, :func:`i2s_channel_init_pdm_tx_mode` or :func:`i2s_channel_init_tdm_mode` to initialize the channel to the specified mode. Corresponding slot, clock and gpio configurations are needed in this step. - - 3. (Optional) Calling :cpp:func:`i2s_channel_register_event_callback` to register the ISR event callback functions. I2S events now can be received by the callback function synchronously, instead of from event queue asynchronously. - - 4. Calling :cpp:func:`i2s_channel_enable` to start the hardware of I2S channel. In the new driver, I2S won't start automatically after installed anymore, users are supposed to know clearly whether the channel has started or not. - - 5. Reading or writing data by :cpp:func:`i2s_channel_read` or :cpp:func:`i2s_channel_write`. Certainly, only rx channel handle is suppoesd to be inputted in :cpp:func:`i2s_channel_read` and tx channel handle in :cpp:func:`i2s_channel_write`. - - 6. (Optional) The slot, clock and gpio configurations can be changed by corresponding 'reconfig' functions, but :cpp:func:`i2s_channel_disable` must be called before updating the configurations. - - 7. Calling :cpp:func:`i2s_channel_disable` to stop the hardware of I2S channel. - - 8. Calling :cpp:func:`i2s_del_channel` to delete and release the resources of the channel if it is not needed any more, but the channel must be disabled before deleting it. - -Register access macros +Register Access Macros ---------------------- Previously, all register access macros could be used as expressions, so the following was allowed:: uint32_t val = REG_SET_BITS(reg, mask); -In IDF v5.0, register access macros which write or read-modify-write the register can no longer be used as expressions, and can only be used as statements. This applies to the following macros: ``REG_WRITE``, ``REG_SET_BIT``, ``REG_CLR_BIT``, ``REG_SET_BITS``, ``REG_SET_FIELD``, ``WRITE_PERI_REG``, ``CLEAR_PERI_REG_MASK``, ``SET_PERI_REG_MASK``, ``SET_PERI_REG_BITS``. +In ESP-IDF v5.0, register access macros which write or read-modify-write the register can no longer be used as expressions, and can only be used as statements. This applies to the following macros: ``REG_WRITE``, ``REG_SET_BIT``, ``REG_CLR_BIT``, ``REG_SET_BITS``, ``REG_SET_FIELD``, ``WRITE_PERI_REG``, ``CLEAR_PERI_REG_MASK``, ``SET_PERI_REG_MASK``, ``SET_PERI_REG_BITS``. To store the value which would have been written into the register, split the operation as follows:: @@ -404,4 +537,4 @@ To store the value which would have been written into the register, split the op To get the value of the register after modification (which may be different from the value written), add an explicit read:: REG_SET_BITS(reg, mask); - uint32_t new_val = REG_READ(reg); + uint32_t new_val = REG_READ(reg); \ No newline at end of file diff --git a/docs/en/migration-guides/release-5.x/protocols.rst b/docs/en/migration-guides/release-5.x/protocols.rst index 5e58514beb..842ee4e8b6 100644 --- a/docs/en/migration-guides/release-5.x/protocols.rst +++ b/docs/en/migration-guides/release-5.x/protocols.rst @@ -1,6 +1,8 @@ Protocols ========= +:link_to_translation:`zh_CN:[中文]` + .. _migration_guide_mbedtls: Mbed TLS @@ -8,7 +10,7 @@ Mbed TLS For ESP-IDF v5.0, `Mbed TLS `_ has been updated from v2.x to v3.1.0. -The official guide for Mbed TLS to migrate from version 2.x to version 3.0 or greater can be found `here `__. +For more details about Mbed TLS's migration from version 2.x to version 3.0 or greater, please refer to the `official guide `__. Breaking Changes (Summary) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -18,19 +20,19 @@ Most structure fields are now private - Direct access to fields of structures (``struct`` types) declared in public headers is no longer supported. - Appropriate accessor functions (getter/setter) must be used for the same. A temporary workaround would be to use ``MBEDTLS_PRIVATE`` macro (**not recommended**). -- For more details, refer to the official guide `here `__. +- For more details, refer to the `official guide `__. SSL ^^^ -- Removed support for TLS 1.0, 1.1 and DTLS 1.0 +- Removed support for TLS 1.0, 1.1, and DTLS 1.0 - Removed support for SSL 3.0 -Deprecated functions were removed from cryptography modules +Deprecated Functions Were Removed from Cryptography Modules ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - The functions ``mbedtls_*_ret()`` (related to MD, SHA, RIPEMD, RNG, HMAC modules) was renamed to replace the corresponding functions without ``_ret`` appended and updated return value. -- For more details, refer to the official guide `here `__. +- For more details, refer to the `official guide `__. Deprecated Config Options @@ -44,13 +46,13 @@ Following are some of the important config options deprecated by this update. Th - ``MBEDTLS_DES_C`` : Support for 3DES ciphersuites - ``MBEDTLS_RC4_MODE`` : Support for RC4-based ciphersuites -.. note:: This list includes only major options configurable through ``idf.py menuconfig``. For more details on deprecated options, refer to the official migration guide. +.. note:: This list includes only major options configurable through ``idf.py menuconfig``. For more details on deprecated options, refer to the `official guide `__. Miscellaneous ------------- -Disabled Diffie-Hellman Key Exchange modes +Disabled Diffie-Hellman Key Exchange Modes ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The Diffie-Hellman Key Exchange modes have now been disabled by default due to security risks (see warning text `here `__). Related configs are given below: @@ -61,17 +63,17 @@ The Diffie-Hellman Key Exchange modes have now been disabled by default due to s .. note:: During the initial step of the handshake (i.e. ``client_hello``), the server selects a cipher from the list that the client publishes. As the DHE_PSK/DHE_RSA ciphers have now been disabled by the above change, the server would fall back to an alternative cipher; if in a rare case, it does not support any other cipher, the handshake would fail. To retrieve the list of ciphers supported by the server, one must attempt to connect with the server with a specific cipher from the client-side. Few utilities can help do this, e.g. ``sslscan``. -Remove ``certs`` module from X509 library +Remove ``certs`` Module from X509 Library ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- The ``mbedtls/certs.h`` header is no longer available in mbedtls 3.1, most applications can safely remove it from the list of includes. +- The ``mbedtls/certs.h`` header is no longer available in mbedtls 3.1. Most applications can safely remove it from the list of includes. -Breaking change for ``esp_crt_bundle_set`` API +Breaking Change for ``esp_crt_bundle_set`` API ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - The :cpp:func:`esp_crt_bundle_set()` API now requires one additional argument named ``bundle_size``. The return type of the API has also been changed to :cpp:type:`esp_err_t` from ``void``. -Breaking change for ``esp_ds_rsa_sign`` API +Breaking Change for ``esp_ds_rsa_sign`` API ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - The :cpp:func:`esp_ds_rsa_sign()` API now requires one less argument. The argument ``mode`` is no longer required. @@ -85,10 +87,10 @@ Breaking Changes (Summary) Names of variables holding different certs in :cpp:type:`httpd_ssl_config_t` structure have been updated. .. list:: - * :cpp:member:`httpd_ssl_config::servercert` variable inherits role of `cacert_pem` variable. - * :cpp:member:`httpd_ssl_config::servercert_len` variable inherits role of `cacert_len` variable - * :cpp:member:`httpd_ssl_config::cacert_pem` variable inherits role of `client_verify_cert_pem` variable - * :cpp:member:`httpd_ssl_config::cacert_len` variable inherits role of `client_verify_cert_len` variable + * :cpp:member:`httpd_ssl_config::servercert` variable inherits role of ``cacert_pem`` variable. + * :cpp:member:`httpd_ssl_config::servercert_len` variable inherits role of ``cacert_len`` variable + * :cpp:member:`httpd_ssl_config::cacert_pem` variable inherits role of ``client_verify_cert_pem`` variable + * :cpp:member:`httpd_ssl_config::cacert_len` variable inherits role of ``client_verify_cert_len`` variable The return type of the :cpp:func:`httpd_ssl_stop` API has been changed to :cpp:type:`esp_err_t` from ``void``. @@ -107,30 +109,33 @@ ESP-TLS Breaking Changes (Summary) ~~~~~~~~~~~~~~~~~~~~~~~~~~ -``esp_tls_t`` structure is now private +``esp_tls_t`` Structure is Now Private ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The :cpp:type:`esp_tls_t` has now been made completely private. You cannot access its internal structures directly. Any necessary data that needs to be obtained from the esp-tls handle can be done through respective getter/setter functions. If there is a requirement of a specific getter/setter function please raise an issue on ESP-IDF. +The :cpp:type:`esp_tls_t` has now been made completely private. You cannot access its internal structures directly. Any necessary data that needs to be obtained from the ESP-TLS handle can be done through respective getter/setter functions. If there is a requirement of a specific getter/setter function, please raise an `issue `__ on ESP-IDF. The list of newly added getter/setter function is as as follows: .. list:: - * :cpp:func:`esp_tls_get_ssl_context` - Obtain the ssl context of the underlying ssl stack from the esp-tls handle. + * :cpp:func:`esp_tls_get_ssl_context` - Obtain the ssl context of the underlying ssl stack from the ESP-TLS handle. -Function deprecations and recommended alternatives +Function Deprecations And Recommended Alternatives ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Following table summarizes the deprecated functions removed and their alternatives to be used from ESP-IDF v5.0 onwards. -+-----------------------------------+----------------------------------------+ -| Function | Alternative | -+===================================+========================================+ -| :cpp:func:`esp_tls_conn_new` | :cpp:func:`esp_tls_conn_new_sync` | -+-----------------------------------+----------------------------------------+ -| :cpp:func:`esp_tls_conn_delete` | :cpp:func:`esp_tls_conn_destroy` | -+-----------------------------------+----------------------------------------+ +.. list-table:: + :widths: 50 50 + :header-rows: 1 -- The function :cpp:func:`esp_tls_conn_http_new` has now been termed as deprecated. Please use the alternative function :cpp:func:`esp_tls_conn_http_new_sync` (or its asynchronous :cpp:func:`esp_tls_conn_http_new_async`). Note that the alternatives need an additional parameter :cpp:type:`esp_tls_t` which has to be initialized using the :cpp:func:`esp_tls_init` function. + * - Deprecated Function + - Alternative + * - ``esp_tls_conn_new()`` + - :cpp:func:`esp_tls_conn_new_sync` + * - ``esp_tls_conn_delete()`` + - :cpp:func:`esp_tls_conn_destroy` + +- The function :cpp:func:`esp_tls_conn_http_new` has now been termed as deprecated. Please use the alternative function :cpp:func:`esp_tls_conn_http_new_sync` (or its asynchronous :cpp:func:`esp_tls_conn_http_new_async`). Note that the alternatives need an additional parameter :cpp:type:`esp_tls_t`, which has to be initialized using the :cpp:func:`esp_tls_init` function. HTTP Server ----------- @@ -170,4 +175,31 @@ Most common configurations are listed below: - Broker address now is set in :cpp:member:`esp_mqtt_client_config_t::broker::address::uri` - Security related to broker verification in :cpp:member:`esp_mqtt_client_config_t::broker::verification` -- Client username is set in :cpp:member:`esp_mqtt_client_config_t::credentials::username` +- Client username is set in :cpp:member:`esp_mqtt_client_config_t::credentials::username` + + +ESP-Modbus +---------- + +Breaking Changes (Summary) +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The ESP-IDF component ``freemodbus`` has been removed from ESP-IDF and is supported as a separate component. Additional information for the ``ESP-Modbus`` component can be found in the separate repository: + +* `ESP-Modbus component on GitHub `__ + +The ``main`` component folder of the new application shall include the component manager manifest file ``idf_component.yml`` as in the example below: + +.. code-block:: text + + dependencies: + espressif/esp-modbus: + version: "^1.0" + +The ``esp-modbus`` component can be found in `component manager registry `__. Refer to `component manager documentation `__ for more information on how to set up the component manager. + +For applications targeting v4.x releases of ESP-IDF that need to use new ``esp-modbus`` component, adding the component manager manifest file ``idf_component.yml`` will be sufficient to pull in the new component. However, users should also exclude the legacy ``freemodbus`` component from the build. This can be achieved using the statement below in the project's ``CMakeLists.txt``: + +.. code-block:: cmake + + set(EXCLUDE_COMPONENTS freemodbus) diff --git a/docs/en/migration-guides/release-5.x/provisioning.rst b/docs/en/migration-guides/release-5.x/provisioning.rst index 3fdc7d1e60..f9950203ce 100644 --- a/docs/en/migration-guides/release-5.x/provisioning.rst +++ b/docs/en/migration-guides/release-5.x/provisioning.rst @@ -1,25 +1,25 @@ Provisioning ============ +:link_to_translation:`zh_CN:[中文]` + Protocomm --------- -The :cpp:func:`protocomm_set_security` API now takes a parameter ``sec_params`` as input instead of ``pop`` (deprecated). -This parameter should contain the structure (containing the security parameters) as required by the protocol version used. +The ``pop`` field in the :cpp:func:`protocomm_set_security` API is now deprecated. Please use the ``sec_params`` field instead of ``pop``. This parameter should contain the structure (including the security parameters) as required by the protocol version used. -For example when using security version 2, the ``sec_params`` parameter should contain the pointer to the structure of type :cpp:type:`protocomm_security2_params_t`. +For example, when using security version 2, the ``sec_params`` parameter should contain the pointer to the structure of type :cpp:type:`protocomm_security2_params_t`. Wi-Fi Provisioning ------------------ -The :cpp:func:`wifi_prov_mgr_start_provisioning` API now takes a parameter ``wifi_prov_sec_params`` as input instead of ``pop``. -This parameter should contain the structure (containing the security parameters) as required by the protocol version used. - -For example when using security version 2, the ``wifi_prov_sec_params`` parameter should contain the pointer to the structure of type :cpp:type:`wifi_prov_security2_params_t`. +.. list:: + * The ``pop`` field in the :cpp:func:`wifi_prov_mgr_start_provisioning` API is now deprecated. For backward compatibility, ``pop`` can be still passed as a string for security1. However for Security2 the ``wifi_prov_sec_params`` argument needs to be passed instead of ``pop``. This parameter should contain the structure (containing the security parameters) as required by the protocol version used. For example, when using security version 2, the ``wifi_prov_sec_params`` parameter should contain the pointer to the structure of type :cpp:type:`wifi_prov_security2_params_t`. For security 1 the behaviour and the usage of the API remains same. + * The API :cpp:func:`wifi_prov_mgr_is_provisioned` does not return :c:macro:`ESP_ERR_INVALID_STATE` error any more. This API now works without any dependency on provisioning manager initialization state. ESP Local Control ----------------- -The `pop` field in :cpp:type:`esp_local_ctrl_proto_sec_cfg_t` is now deprecated, use ``sec_params`` field instead of ``pop``. -This field should contain the structure (containing the security parameters) as required by the protocol version used. -For example when using security version 2, the ``sec_params`` field should contain pointer to the structure of type :cpp:type:`esp_local_ctrl_security2_params_t`. +The ``pop`` field in the :cpp:type:`esp_local_ctrl_proto_sec_cfg_t` API is now deprecated. Please use the ``sec_params`` field instead of ``pop``. This field should contain the structure (containing the security parameters) as required by the protocol version used. + +For example, when using security version 2, the ``sec_params`` field should contain pointer to the structure of type :cpp:type:`esp_local_ctrl_security2_params_t`. diff --git a/docs/en/migration-guides/release-5.x/removed-components.rst b/docs/en/migration-guides/release-5.x/removed-components.rst index 9a3289dcb2..20af737f8a 100644 --- a/docs/en/migration-guides/release-5.x/removed-components.rst +++ b/docs/en/migration-guides/release-5.x/removed-components.rst @@ -1,6 +1,8 @@ Removed or Deprecated Components ================================ +:link_to_translation:`zh_CN:[中文]` + Components Moved to IDF Component Registry ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -18,6 +20,10 @@ Following components are removed from ESP-IDF and moved to `IDF Component Regist * `sh2lib `_ * `expat `_ * `coap `_ +* `esp-cryptoauthlib `_ +* `qrcode `_ +* `tjpgd `_ +* `esp_serial_slave_link `_ .. note:: Please note that http parser functionality which was previously part of ``nghttp`` component is now part of :component:`http_parser ` component. @@ -40,6 +46,9 @@ The following components are removed since they were deprecated in IDF v4.x: .. note:: OpenSSL-API component is no longer supported. It is not available in the IDF Component Registry, either. Please use :doc:`ESP-TLS ` or :component:`mbedtls` API directly. +.. note:: + ``esp_adc_cal`` component is no longer supported. New adc calibration driver is in ``esp_adc`` component. Legacy adc calibration driver has been moved into ``esp_adc`` component. To use legacy ``esp_adc_cal`` driver APIs, you should add ``esp_adc`` component to the list of component requirements in CMakeLists.txt. Also check :doc:`Peripherals Migration Guide ` for more details. + The targets components are no longer necessary after refactoring and have been removed: * ``esp32`` diff --git a/docs/en/migration-guides/release-5.x/storage.rst b/docs/en/migration-guides/release-5.x/storage.rst index 6af864b457..54454fe79f 100644 --- a/docs/en/migration-guides/release-5.x/storage.rst +++ b/docs/en/migration-guides/release-5.x/storage.rst @@ -1,90 +1,98 @@ Storage ======= -Breaking changes: -~~~~~~~~~~~~~~~~~ +SDMMC/SDSPI +----------- -f_mkfs() signature change in FATFS v0.14 ----------------------------------------- +SD card frequency on SDMMC/SDSPI interface can be now configured through ``sdmmc_host_t.max_freq_khz`` to a specific value, not only ``SDMMC_FREQ_PROBING`` (400 kHz), ``SDMMC_FREQ_DEFAULT`` (20 MHz), or ``SDMMC_FREQ_HIGHSPEED`` (40 MHz). Previously, in case you have specified a custom frequency other than any of the above-mentioned values, the closest lower-or-equal one was selected anyway. -New signature is ``FRESULT f_mkfs (const TCHAR* path, const MKFS_PARM* opt, void* work, UINT len);`` which now uses ``MKFS_PARM`` struct as a second argument. +Now, the underlaying drivers calculate the nearest fitting value, given by available frequency dividers instead of an enumeration item selection. This could cause troubles in communication with your SD card without a change of the existing application code.If you encounter such an issue, please, keep trying different frequencies around your desired value unless you find the one working well. To check the frequency value calculated and actually applied, use ``void sdmmc_card_print_info(FILE* stream, const sdmmc_card_t* card)`` function. -Partition table generation no longer supports misaligned partitions -------------------------------------------------------------------- +FatFs +----- -When generating a partiton table, ``esp-idf`` will no longer accept partitions which offset does not align to 4kB. This change only affects generating new partition tables, reading and writing to already existing partitions remains unchanged. +FatFs is now updated to v0.14. As a result, the function signature of ``f_mkfs()`` has changed. The new signature is ``FRESULT f_mkfs (const TCHAR* path, const MKFS_PARM* opt, void* work, UINT len);`` which uses ``MKFS_PARM`` struct as a second argument. -esp_vfs_semihost_register() signature change --------------------------------------------- +Partition Table +--------------- -New signature is ``esp_err_t esp_vfs_semihost_register(const char* base_path);`` Absolute path as a second parameter will no longer in use. Instead, the OpenOCD command ``ESP_SEMIHOST_BASEDIR`` should be used to set the full path on the host. +The partition table generator no longer supports misaligned partitions. When generating a partition table, ``ESP-IDF`` only accepts partitions with offsets that align to 4 KB. This change only affects generating new partition tables. Reading and writing to already existing partitions remains unchanged. -NVS + +VFS --- -``nvs_entry_find()``, ``nvs_entry_next()`` and ``nvs_entry_info()`` always return ``esp_err_t`` now instead of ``void`` or ``nvs_iterator_t``. This provides better error reporting when parameters are invalid or something goes wrong internally than returning ``nullptr`` instead of a valid iterator or checking parameters with ``assert``. ``nvs_entry_find()`` and ``nvs_entry_next()`` modify iterators via parameters now instead of returning an iterator. +The ``esp_vfs_semihost_register()`` function signature is changed as follows: + +- The new signature is ``esp_err_t esp_vfs_semihost_register(const char* base_path);`` +- The ``host_path`` parameter of the old signature no longer exists. Instead, the OpenOCD command ``ESP_SEMIHOST_BASEDIR`` should be used to set the full path on the host. + +Function Signature Changes +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following functions now return ``esp_err_t`` instead of ``void`` or ``nvs_iterator_t``. Previously, when parameters were invalid or when something goes wrong internally, these functions would ``assert()`` or return a ``nullptr``. With an ``esp_err_t`` returned, you can get better error reporting. + +- :cpp:func:`nvs_entry_find` +- :cpp:func:`nvs_entry_next` +- :cpp:func:`nvs_entry_info` + +Because the ``esp_err_t`` return type changes, the usage patterns of ``nvs_entry_find()`` and ``nvs_entry_next()`` become different. Both functions now modify iterators via parameters instead of returning an iterator. The old programming pattern to iterate over an NVS partition was as follows: -.. highlight:: c - -:: +.. code-block:: c nvs_iterator_t it = nvs_entry_find(, , NVS_TYPE_ANY); while (it != NULL) { nvs_entry_info_t info; nvs_entry_info(it, &info); it = nvs_entry_next(it); - printf("key '%s', type '%d' \n", info.key, info.type); + printf("key '%s', type '%d'", info.key, info.type); }; The new programming pattern to iterate over an NVS partition is now: -.. highlight:: c - -:: +.. code-block:: c nvs_iterator_t it = nullptr; esp_err_t res = nvs_entry_find(, , NVS_TYPE_ANY, &it); while(res == ESP_OK) { nvs_entry_info_t info; nvs_entry_info(it, &info); // Can omit error check if parameters are guaranteed to be non-NULL - printf("key '%s', type '%d' \n", info.key, info.type); + printf("key '%s', type '%d'", info.key, info.type); res = nvs_entry_next(&it); } nvs_release_iterator(it); -Signature Changes -^^^^^^^^^^^^^^^^^ - -``nvs_iterator_t nvs_entry_find(const char *part_name, const char *namespace_name, nvs_type_t type)`` changes to ``esp_err_t nvs_entry_find(const char *part_name, const char *namespace_name, nvs_type_t type, nvs_iterator_t *output_iterator)``. The iterator is returned via the parameter ``output_iterator`` instead of a return value. This allows reporting additional errors, like e.g. memory errors, via the new return value. - -``nvs_iterator_t nvs_entry_next(nvs_iterator_t iterator)`` changes to ``esp_err_t nvs_entry_next(nvs_iterator_t *it)``. This allows reporting parameter errors and internal errors, like e.g. flash errors. - -``void nvs_entry_info(nvs_iterator_t iterator, nvs_entry_info_t *out_info)`` changes to ``esp_err_t nvs_entry_info(const nvs_iterator_t iterator, nvs_entry_info_t *out_info)`` to allow reporting parameter errors. - Iterator Validity ^^^^^^^^^^^^^^^^^ -Note that due to the new signatures, it is possible to have an invalid iterator from ``nvs_entry_find()``, if there is a parameter errors. Hence, it is important to initialize the iterator with ``NULL`` before using ``nvs_entry_find()`` to avoid complex error checking before calling ``nvs_release_iterator()``. A good example is the programming pattern above. +Note that because the function signature changes, if there is a parameter error, you may get an invalid iterator from ``nvs_entry_find()``. Hence, it is important to initialize the iterator to ``NULL`` before using ``nvs_entry_find()``, so that you can avoid complex error checking before calling ``nvs_release_iterator()``. A good example is the programming pattern above. -Removed SDSPI deprecated API + +Removed SDSPI Deprecated API ---------------------------- -Removed structure ``sdspi_slot_config_t`` and fuction ``sdspi_host_init_slot``. These were replaced by a structure ``sdspi_device_config_t`` and a fuction ``sdspi_host_init_device`` respectively. +Structure ``sdspi_slot_config_t`` and function ``sdspi_host_init_slot()`` are removed, and replaced by structure ``sdspi_device_config_t`` and function ``sdspi_host_init_device()`` respectively. -SPI Flash Interface -------------------- +ROM SPI Flash +^^^^^^^^^^^^^ -Version before v5.0, spi flash functions in rom can be included by ``esp32**/rom/spi_flash.h``. However, your code written for different chips may be filled with ROM headers of different versions. At the meantime not all the APIs can be used on all chips. +In versions before v5.0, ROM SPI flash functions were included via ``esp32**/rom/spi_flash.h``. Thus, code written to support different ESP chips might be filled with ROM headers of different targets. Furthermore, not all of the APIs could be used on all ESP chips. -Therefore, the common APIs are extracted to ``esp_rom_spiflash.h``. Although it's not a breaking change, it is strongly recommended to only use the functions with prefix ``esp_rom_spiflash`` included by ``esp_rom_spiflash.h`` for better cross-compatibility. +Now, the common APIs are extracted to ``esp_rom_spiflash.h``. Although it is not a breaking change, you are strongly recommended to only use the functions from this header (i.e., prefixed with ``esp_rom_spiflash`` and included by ``esp_rom_spiflash.h``) for better cross-compatibility between ESP chips. -To make the API clearer, we renamed the function ``esp_rom_spiflash_lock`` to ``esp_rom_spiflash_set_bp``. We renamed ``esp_rom_spiflash_unlock`` to ``esp_rom_spiflash_clear_bp``. +To make ROM SPI flash APIs clearer, the following functions are also renamed: -ENUM type ``esp_flash_speed_t`` has been deprecated. From now on, you can directly parse the real clock frequency value to the flash initialization structure. For example, if you want the flash frequency is 80M, you can write the code like: +- ``esp_rom_spiflash_lock()`` to ``esp_rom_spiflash_set_bp()`` +- ``esp_rom_spiflash_unlock()`` to ``esp_rom_spiflash_clear_bp()`` -.. code:: c +SPI Flash Driver +^^^^^^^^^^^^^^^^ + +The ``esp_flash_speed_t`` ``enum`` type is now deprecated. Instead, you may now directly pass the real clock frequency value to the flash configuration structure. The following example demonstrates how to configure a flash frequency of 80MHz: + +.. code-block:: c esp_flash_spi_device_config_t dev_cfg = { // Other members @@ -92,29 +100,32 @@ ENUM type ``esp_flash_speed_t`` has been deprecated. From now on, you can direct // Other members }; -Breaking changes in legacy APIs -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Legacy SPI Flash Driver +^^^^^^^^^^^^^^^^^^^^^^^ -In order to make spi_flash driver more stable, legacy spi_flash driver is removed on v5.0. Legacy spi_flash driver refers to default spi_flash driver since v3.0 and spi_flash driver with configuration option ``CONFIG_SPI_FLASH_USE_LEGACY_IMPL`` switched on on v4.0 series. The major breaking change is legacy spi_flash driver is not supported on new version anymore. Therefore, the configuration option ``CONFIG_SPI_FLASH_USE_LEGACY_IMPL`` is removed. After that, following functions will no longer exist. But meanwhile, you can use our new APIs instead. +To make SPI flash drivers more stable, the legacy SPI flash driver is removed from v5.0. The legacy SPI flash driver refers to default spi_flash driver since v3.0, and the SPI flash driver with configuration option ``CONFIG_SPI_FLASH_USE_LEGACY_IMPL`` enabled since v4.0. The major breaking change here is that the legacy spi_flash driver is no longer supported from v5.0. Therefore, the legacy driver APIs and the ``CONFIG_SPI_FLASH_USE_LEGACY_IMPL`` configuration option are both removed. Please use the new spi_flash driver's APIs instead. -+---------------------------------+-------------------------------+ -| Removed items | Replacement | -+=================================+===============================+ -| ``spi_flash_erase_sector()`` | ``esp_flash_erase_region`` | -+---------------------------------+-------------------------------+ -| ``spi_flash_erase_range()`` | ``esp_flash_erase_region`` | -+---------------------------------+-------------------------------+ -| ``spi_flash_write`` | ``esp_flash_write`` | -+---------------------------------+-------------------------------+ -| ``spi_flash_read()`` | ``esp_flash_read`` | -+---------------------------------+-------------------------------+ -| ``spi_flash_write_encrypted()`` | ``esp_flash_write_encrypted`` | -+---------------------------------+-------------------------------+ -| ``spi_flash_read_encrypted`` | ``esp_flash_read_encrypted`` | -+---------------------------------+-------------------------------+ +.. list-table:: + :widths: 50 50 + :header-rows: 1 + + * - Removed items + - Replacement + * - ``spi_flash_erase_sector()`` + - ``esp_flash_erase_region()`` + * - ``spi_flash_erase_range()`` + - ``esp_flash_erase_region()`` + * - ``spi_flash_write()`` + - ``esp_flash_write()`` + * - ``spi_flash_read()`` + - ``esp_flash_read()`` + * - ``spi_flash_write_encrypted()`` + - ``esp_flash_write_encrypted()`` + * - ``spi_flash_read_encrypted()`` + - ``esp_flash_read_encrypted()`` .. note:: - New functions with prefix ``esp_flash`` accept an additional ``esp_flash_t*`` parameter. You can simply set it to NULL means that the function will operate the main flash(``esp_flash_default_chip``) + New functions with prefix ``esp_flash`` accept an additional ``esp_flash_t*`` parameter. You can simply set it to NULL. This will make the function to run the main flash (``esp_flash_default_chip``). -Header ``esp_spi_flash.h`` has been deprecated, system functions are no longer public. To make use of flash memory mapping APIs, you should include ``spi_flash_mmap.h`` instead. +The ``esp_spi_flash.h`` header is deprecated as system functions are no longer public. To use flash memory mapping APIs, you may include ``spi_flash_mmap.h`` instead. diff --git a/docs/en/migration-guides/release-5.x/system.rst b/docs/en/migration-guides/release-5.x/system.rst index 00d39e5662..bde5a39d9c 100644 --- a/docs/en/migration-guides/release-5.x/system.rst +++ b/docs/en/migration-guides/release-5.x/system.rst @@ -115,6 +115,8 @@ Task Watchdog Timers - Configuration is now passed as a configuration structure. - The function will now handle subscribing of the idle tasks if configured to do so. +- The former ``CONFIG_ESP_TASK_WDT`` configuration option has been renamed to :ref:`CONFIG_ESP_TASK_WDT_INIT` and a new :ref:`CONFIG_ESP_TASK_WDT_EN` option has been introduced. + FreeRTOS -------- @@ -149,3 +151,15 @@ The file ``portmacro_deprecated.h`` which was added to maintain backward compati - ``vPortCPUAcquireMutex()`` is removed. Users should use the ``spinlock_acquire()`` function instead. - ``vPortCPUAcquireMutexTimeout()`` is removed. Users should use the ``spinlock_acquire()`` function instead. - ``vPortCPUReleaseMutex()`` is removed. Users should use the ``spinlock_release()`` function instead. + +App Update +---------- + +- The functions :cpp:func:`esp_ota_get_app_description` and :cpp:func:`esp_ota_get_app_elf_sha256` have been termed as deprecated. Please use the alternative functions :cpp:func:`esp_app_get_description` and :cpp:func:`esp_app_get_elf_sha256` respectively. These functions have now been moved to a new component :component:`esp_app_format`. Please refer to the header file :component_file:`esp_app_desc.h `. + +Bootloader Support +------------------ + +- The :cpp:type:`esp_app_desc_t` structure, which used to be declared in :component_file:`esp_app_format.h `, is now declared in :component_file:`esp_app_desc.h `. + +- The function :cpp:func:`bootloader_common_get_partition_description` has now been made private. Please use the alternative function :cpp:func:`esp_ota_get_partition_description`. Note that this function takes :cpp:type:`esp_partition_t` as its first argument instead of :cpp:type:`esp_partition_pos_t`. diff --git a/docs/en/security/secure-boot-v2.rst b/docs/en/security/secure-boot-v2.rst index 89fde7abcd..ef890c9cec 100644 --- a/docs/en/security/secure-boot-v2.rst +++ b/docs/en/security/secure-boot-v2.rst @@ -150,7 +150,7 @@ The content of each signature block is shown in the following table: - Pre-calculated M’, derived from ‘n’ * - 812 - 384 - - RSA-PSS Signature result (section 8.1.1 of RFC8017) of image content, computed using following PSS parameters: SHA256 hash, MFG1 function, salt length 32 bytes, default trailer field (0xBC). + - RSA-PSS Signature result (section 8.1.1 of RFC8017) of image content, computed using following PSS parameters: SHA256 hash, MGF1 function, salt length 32 bytes, default trailer field (0xBC). * - 1196 - 4 - CRC32 of the preceding 1196 bytes. diff --git a/docs/page_redirects.txt b/docs/page_redirects.txt index e0298de25a..de7ec0d23e 100644 --- a/docs/page_redirects.txt +++ b/docs/page_redirects.txt @@ -83,6 +83,8 @@ hw-reference/get-started-pico-kit-v3 hw-reference/esp32/get-started-p hw-reference/get-started-ethernet-kit-v1.0 hw-reference/esp32/get-started-ethernet-kit-v1.0 hw-reference/get-started-ethernet-kit hw-reference/esp32/get-started-ethernet-kit hw-reference/esp32s2/usermacos-setup_mesh api-reference/network/esp-wifi-mesh +# The 'chip series comparison' is merged into 'esp product selector' +hw-reference/chip-series-comparison "https://products.espressif.com/#/product-comparison" # Getting Started get-started/macos-setup get-started/linux-macos-setup diff --git a/docs/zh_CN/api-guides/bootloader.rst b/docs/zh_CN/api-guides/bootloader.rst index 8094562644..903ca26d3c 100644 --- a/docs/zh_CN/api-guides/bootloader.rst +++ b/docs/zh_CN/api-guides/bootloader.rst @@ -150,7 +150,6 @@ ROM ä¸­ç„ :ref:`first-stage-bootloader` ä» flash ä¸­è¯»å– :ref:`second-stage- 引导å è½½ç¨‹åºæœ‰ :ref:`CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP` 选项，å¯ä»¥å‡å°‘ä»æ·±åº¦ç¡çœ ä¸­å”¤é†’ç„时间（有利äºé™ä½åŸè€—ï¼‰ă€‚å½“ :ref:`CONFIG_SECURE_BOOT` 选项ç¦ç”¨æ—¶ï¼Œè¯¥é€‰é¡¹å¯ç”¨ă€‚ç”±äºæ— éœ€é•œåƒæ ¡éªŒï¼Œå”¤é†’时间å‡å°‘ă€‚åœ¨ç¬¬ä¸€æ¬¡å¯å¨æ—¶ï¼Œå¼•å¯¼å è½½ç¨‹åºå°†å¯å¨ç„应用程åºç„地å€å­˜å‚¨åœ¨ RTC FAST å­˜å‚¨å™¨ä¸­ă€‚è€Œåœ¨å”¤é†’è¿‡ç¨‹ä¸­ï¼Œè¿™ä¸ªåœ°å€ç”¨äºå¯å¨è€Œæ— éœ€ä»»ä½•æ£€æŸ¥ï¼Œä»è€Œå®ç°äº†å¿«é€Ÿå è½½ă€‚ - 自å®ä¹‰å¼•å¯¼å è½½ç¨‹åº ---------------------- diff --git a/docs/zh_CN/api-guides/build-system.rst b/docs/zh_CN/api-guides/build-system.rst index e760b8746d..88805f721e 100644 --- a/docs/zh_CN/api-guides/build-system.rst +++ b/docs/zh_CN/api-guides/build-system.rst @@ -178,9 +178,9 @@ ESP-IDF é€‚ç”¨äº Python 3.7 以ä¸ç‰ˆæœ¬ă€‚ - "sdkconfig" 项目é…置文件，执行 ``idf.py menuconfig`` æ—¶ä¼åˆ›å»ºæˆ–更新此文件，文件中ä¿å­˜äº†é¡¹ç›®ä¸­æ‰€æœ‰ç»„件（包括 ESP-IDF 本身）ç„é…置信æ¯ă€‚ ``sdkconfig`` 文件å¯èƒ½ä¼ä¹Ÿå¯èƒ½ä¸ä¼è¢«æ·»å åˆ°é¡¹ç›®ç„æºç ç®¡ç†ç³»ç»Ÿä¸­ă€‚ -- å¯é€‰ç„ "components" 目录中包å«äº†é¡¹ç›®ç„部分自å®ä¹‰ç»„件，并ä¸æ˜¯æ¯ä¸ªé¡¹ç›®éƒ½éœ€è¦è¿™ç§è‡ªå®ä¹‰ç»„件，但它有å©äºæ„建å¯å¤ç”¨ç„代ç æˆ–者导入第三方（ä¸å±äº ESP-IDF）ç„ç»„ä»¶ă€‚æˆ–è€…ï¼Œæ‚¨ä¹Ÿå¯ä»¥åœ¨é¡¶å±‚ CMakeLists.txt 中设置 ``EXTRA_COMPONENT_DIRS`` å˜é‡ä»¥æŸ¥æ‰¾å…¶ä»–指å®ä½ç½®å¤„ç„ç»„ä»¶ă€‚æœ‰å…³è¯¦ç»†ä¿¡æ¯ï¼Œè¯·å‚阅 :ref:`é‡å‘½å main 组件 `ă€‚å¦‚æœé¡¹ç›®ä¸­æºæ–‡ä»¶è¾ƒå¤ï¼Œå»ºè®®å°†å…¶å½’äºç»„件中，而ä¸æ˜¯å…¨éƒ¨æ”¾åœ¨ "main" 中。 +- å¯é€‰ç„ "components" 目录中包å«äº†é¡¹ç›®ç„部分自å®ä¹‰ç»„件，并ä¸æ˜¯æ¯ä¸ªé¡¹ç›®éƒ½éœ€è¦è¿™ç§è‡ªå®ä¹‰ç»„件，但它有å©äºæ„建å¯å¤ç”¨ç„代ç æˆ–者导入第三方（ä¸å±äº ESP-IDF）ç„ç»„ä»¶ă€‚æˆ–è€…ï¼Œæ‚¨ä¹Ÿå¯ä»¥åœ¨é¡¶å±‚ CMakeLists.txt 中设置 ``EXTRA_COMPONENT_DIRS`` å˜é‡ä»¥æŸ¥æ‰¾å…¶ä»–指å®ä½ç½®å¤„ç„组件。 -- "main" 目录是一个特æ®ç„组件，它包å«é¡¹ç›®æœ¬èº«ç„æºä»£ç ă€‚"main" 是默认å称，CMake å˜é‡ ``COMPONENT_DIRS`` 默认包å«æ­¤ç»„件，但您å¯ä»¥ä¿®æ”¹æ­¤å˜é‡ă€‚ +- "main" 目录是一个特æ®ç„组件，它包å«é¡¹ç›®æœ¬èº«ç„æºä»£ç ă€‚"main" 是默认å称，CMake å˜é‡ ``COMPONENT_DIRS`` 默认包å«æ­¤ç»„件，但您å¯ä»¥ä¿®æ”¹æ­¤å˜é‡ă€‚有关详细信æ¯ï¼Œè¯·å‚阅 :ref:`é‡å‘½å main 组件 `ă€‚å¦‚æœé¡¹ç›®ä¸­æºæ–‡ä»¶è¾ƒå¤ï¼Œå»ºè®®å°†å…¶å½’äºç»„件中，而ä¸æ˜¯å…¨éƒ¨æ”¾åœ¨ "main" 中。 - "build" 目录是存放æ„建输出ç„地方，如æœæ²¡æœ‰æ­¤ç›®å½•ï¼Œ``idf.py`` ä¼è‡ªå¨åˆ›å»ºă€‚CMake ä¼é…置项目，并在此目录下生æˆä¸´æ—¶ç„æ„å»ºæ–‡ä»¶ă€‚éå，在主æ„建进程ç„è¿è¡ŒæœŸé—´ï¼Œè¯¥ç›®å½•è¿˜ä¼ä¿å­˜ä¸´æ—¶ç›®æ ‡æ–‡ä»¶ă€åº“文件以å最终输出ç„äºŒè¿›åˆ¶æ–‡ä»¶ă€‚æ­¤ç›®å½•é€å¸¸ä¸ä¼æ·»å åˆ°é¡¹ç›®ç„æºç ç®¡ç†ç³»ç»Ÿä¸­ï¼Œä¹Ÿä¸ä¼é项目æºç ä¸€åŒå‘å¸ƒă€‚ @@ -335,7 +335,6 @@ ESP-IDF 在æœç´¢æ‰€æœ‰å¾…æ„建ç„组件时，ä¼æŒ‰ç…§ ``COMPONENT_DIRS`` 指 以下是å¯ä½œä¸ºæ„建å±æ€§ç„æ„建/项目å˜é‡ï¼Œå¯é€è¿‡ç»„件 CMakeLists.txt ä¸­ç„ ``idf_build_get_property`` 查询其å˜é‡å€¼ă€‚ - - ``PROJECT_NAME``ï¼é¡¹ç›®å，在项目 CMakeLists.txt æ–‡ä»¶ä¸­è®¾ç½®ă€‚ - ``PROJECT_DIR``ï¼é¡¹ç›®ç›®å½•ï¼ˆåŒ…å«é¡¹ç›® CMakeLists 文件）ç„ç»å¯¹è·¯å¾„ï¼Œä¸ ``CMAKE_SOURCE_DIR`` å˜é‡ç›¸åŒă€‚ - ``COMPONENTS``ï¼æ­¤æ¬¡æ„建中包å«ç„所有组件ç„å称，具体格å¼ä¸ºç”¨åˆ†å·é”å¼€ç„ CMake åˆ—è¡¨ă€‚ @@ -349,6 +348,7 @@ ESP-IDF 在æœç´¢æ‰€æœ‰å¾…æ„建ç„组件时，ä¼æŒ‰ç…§ ``COMPONENT_DIRS`` 指 * æˆ–è€…ï¼Œå¦‚æœ ``PROJECT_DIR/version.txt`` 文件存在，其内容ä¼ç”¨ä½œ ``PROJECT_VER`` ç„å€¼ă€‚ * 或者，如æœé¡¹ç›®ä½äºæŸä¸ª Git 仓库中，则使用 ``git describe`` 命令ç„输出作为 ``PROJECT_VER`` ç„å€¼ă€‚ * å¦åˆ™ï¼Œ``PROJECT_VER`` ç„值为 1。 +- ``EXTRA_PARTITION_SUBTYPES``ï¼CMake 列表，用äºåˆ›å»ºé¢å¤–ç„分区å­ç±»å‹ă€‚å­ç±»å‹ç„æ述由字符串组æˆï¼Œä»¥é€—å·ä¸ºåˆ†é”，格å¼ä¸º ``type_name, subtype_name, numeric_value``。组件å¯é€è¿‡æ­¤åˆ—表，添å æ–°ç„å­ç±»å‹ă€‚ 其它ä¸æ„建å±æ€§æœ‰å…³ç„ä¿¡æ¯è¯·å‚考 :ref:`这里`。 @@ -626,12 +626,12 @@ CMake é€å¸¸ä¼åœ¨é“¾æ¥å™¨å‘½ä»¤è¡Œä¸é‡å¤ä¸¤æ¬¡ç»„件库å称æ¥è‡ªå¨å¤„ .. _override_project_config: 覆盖项目ç„部分设置 ------------------- +===================== .. _project_include.cmake: project_include.cmake -^^^^^^^^^^^^^^^^^^^^^ +--------------------- 如æœç»„件ç„æŸäº›æ„建行为需è¦åœ¨ç»„件 CMakeLists 文件之å‰è¢«æ‰§è¡Œï¼Œæ‚¨å¯ä»¥åœ¨ç»„件目录下创建å为 ``project_include.cmake`` ç„文件，``project.cmake`` 在è¿è¡Œè¿‡ç¨‹ä¸­ä¼å¯¼å…¥æ­¤ CMake æ–‡ä»¶ă€‚ @@ -646,7 +646,7 @@ project_include.cmake 在 ``project_include.cmake`` 文件中设置å˜é‡æˆ–目标时è¦æ ¼å¤–å°å¿ƒï¼Œè¿™äº›å€¼è¢«åŒ…å«åœ¨é¡¹ç›®ç„顶层 CMake 文件中，因此他们ä¼å½±å“或破å所有组件ç„åŸèƒ½ă€‚ KConfig.projbuild -^^^^^^^^^^^^^^^^^ +----------------- ä¸ ``project_include.cmake`` 类似，也å¯ä»¥ä¸ºç»„件å®ä¹‰ä¸€ä¸ª KConfig 文件以å®ç°å…¨å±€ç„ :ref:`component-configuration`ă€‚å¦‚æœè¦åœ¨ menuconfig ç„顶层添å é…置选项，而ä¸æ˜¯åœ¨ “Component Configuration†å­èœå•ä¸­ï¼Œåˆ™å¯ä»¥åœ¨ ``CMakeLists.txt`` æ–‡ä»¶æ‰€åœ¨ç›®å½•ç„ KConfig.projbuild 文件中å®ä¹‰è¿™äº›é€‰é¡¹ă€‚ @@ -654,15 +654,30 @@ KConfig.projbuild ``project_include.cmake`` 文件在 ESP-IDF 内部使用，以å®ä¹‰é¡¹ç›®èŒƒå›´å†…ç„æ„建åŸèƒ½ï¼Œæ¯”如 ``esptool.py`` ç„命令行å‚æ•°å’Œ ``bootloader`` 这个特æ®ç„应用程åºă€‚ +é€è¿‡å°è£…对ç°æœ‰å‡½æ•°è¿›è¡Œé‡æ–°å®ä¹‰æˆ–扩展 +------------------------------------- + +链æ¥å™¨å…·æœ‰å°è£…åŸèƒ½ï¼Œå¯ä»¥é‡æ–°å®ä¹‰æˆ–扩展ç°æœ‰ ESP-IDF 函数ç„è¡Œä¸ºă€‚å¦‚éœ€å°è£…函数，您需è¦åœ¨é¡¹ç›®ç„ ``CMakeLists.txt`` 文件中æ供以下 CMake 声æ˜ï¼ + +.. code-block:: cmake + + target_link_libraries(${COMPONENT_LIB} INTERFACE "-Wl,--wrap=function_to_redefine") + +其中，``function_to_redefine`` 为需è¦è¢«é‡æ–°å®ä¹‰æˆ–扩展ç„函数å称。å¯ç”¨æ­¤é€‰é¡¹å，链æ¥å™¨å°†æ二进制库中所有对 ``function_to_redefine`` 函数ç„调用改为对 ``__wrap_function_to_redefine`` 函数ç„è°ƒç”¨ă€‚å› æ­¤ï¼Œæ‚¨å¿…é¡»åœ¨åº”ç”¨ç¨‹åºä¸­å®ä¹‰è¿™ä¸€ç¬¦å·ă€‚ + +链æ¥å™¨ä¼æ供一个å为 ``__real_function_to_redefine`` ç„新符å·ï¼ŒæŒ‡å‘将被é‡æ–°å®ä¹‰ç„函数ç„åŸæœ‰å®ç°ă€‚由此，å¯ä»¥ä»æ–°ç„å®ç°ä¸­è°ƒç”¨è¯¥å‡½æ•°ï¼Œä»è€Œå¯¹åŸæœ‰å®ç°è¿›è¡Œæ‰©å±•ă€‚ + +请å‚考 :example:`build_system/wrappers` 示例，了解其详细åŸç†ă€‚æ›´å¤ç»†è‚请å‚阅 :idf_file:`examples/build_system/wrappers/README.md`。 + .. _config_only_component: ä»…é…置组件 -^^^^^^^^^^ +=========== ä»…é…置组件是一类ä¸åŒ…å«æºæ–‡ä»¶ç„特æ®ç»„ä»¶ï¼Œä»…åŒ…å« ``Kconfig.projbuild``ă€``KConfig`` å’Œ ``CMakeLists.txt`` 文件，该 ``CMakeLists.txt`` 文件仅有一行代ç ï¼Œè°ƒç”¨äº† ``idf_component_register()`` å‡½æ•°ă€‚æ­¤å‡½æ•°ä¼å°†ç»„件导入到项目æ„建中，但ä¸ä¼æ„建任何库，也ä¸ä¼å°†å¤´æ–‡ä»¶æ·»å åˆ°ä»»ä½• include æœç´¢è·¯å¾„中。 CMake 调试 ----------- +=========== 请查看 `CMake v3.16 官方文档`_ è·å–æ›´å¤å…³äº CMake_ å’Œ CMake 命令ç„ä¿¡æ¯ă€‚ @@ -679,7 +694,7 @@ CMake 调试 .. _warn-undefined-variables: è­¦å‘未å®ä¹‰ç„å˜é‡ -^^^^^^^^^^^^^^^^ +------------------ 默认情况下，``idf.py`` 在调用 CMake_ æ—¶ä¼ç»™å®ƒä¼ é€’ ``--warn-uninitialized`` 标志，如æœåœ¨æ„建ç„过程中引用了未å®ä¹‰ç„å˜é‡ï¼ŒCMake_ ä¼æ‰“å°è­¦å‘ă€‚è¿™å¯¹æŸ¥æ‰¾æœ‰é”™è¯¯ç„ CMake 文件éå¸¸æœ‰ç”¨ă€‚ @@ -1100,7 +1115,7 @@ ESP-IDF æä¾›äº†ä¸€ä¸ªæ¨¡æ¿ CMake 项目，å¯ä»¥åŸºäºæ­¤è½»æ¾åˆ›å»ºåº”用 ESP-IDF CMake æ„建系统 API ============================== -idf æ„建命令 +ESP-IDF æ„建命令 ------------------ .. code-block:: none @@ -1163,7 +1178,7 @@ idf æ„建命令 .. _cmake-build-properties: -idf æ„建å±æ€§ +ESP-IDF æ„建å±æ€§ -------------------- å¯ä»¥é€è¿‡ä½¿ç”¨æ„建命令 ``idf_build_get_property`` æ¥è·å–æ„建å±æ€§ç„å€¼ă€‚ä¾‹å¦‚ï¼Œä»¥ä¸‹å‘½ä»¤å¯ä»¥è·å–æ„å»ºè¿‡ç¨‹ä¸­ä½¿ç”¨ç„ Python 解é‡å™¨ç„相关信æ¯ă€‚ @@ -1201,7 +1216,7 @@ idf æ„建å±æ€§ - SDKCONFIG_JSON - 包å«ç»„件é…ç½®ç„ JSON 文件ç„完整路径；由 ``idf_build_process`` è®¾ç½®ă€‚ - SDKCONFIG_JSON_MENUS - 包å«é…ç½®èœå•ç„ JSON 文件ç„完整路径；由 ``idf_build_process`` è®¾ç½®ă€‚ -idf 组件命令 +ESP-IDF 组件命令 ---------------------- .. code-block:: none @@ -1262,7 +1277,7 @@ idf 组件命令 .. _cmake-component-properties: -idf 组件å±æ€§ +ESP-IDF 组件å±æ€§ ------------------------ 组件ç„å±æ€§å€¼å¯ä»¥é€è¿‡ä½¿ç”¨æ„建命令 ``idf_component_get_property`` æ¥è·å–ă€‚ä¾‹å¦‚ï¼Œä»¥ä¸‹å‘½ä»¤å¯ä»¥è·å– ``freertos`` 组件ç„ç›®å½•ă€‚ diff --git a/docs/zh_CN/api-guides/esp-ble-mesh/ble-mesh-index.rst b/docs/zh_CN/api-guides/esp-ble-mesh/ble-mesh-index.rst index bbe638b231..34ed2ccf3f 100644 --- a/docs/zh_CN/api-guides/esp-ble-mesh/ble-mesh-index.rst +++ b/docs/zh_CN/api-guides/esp-ble-mesh/ble-mesh-index.rst @@ -4,9 +4,6 @@ ESP-BLE-MESH :link_to_translation:`en:[English]` -概述 -===== - è“牙 mesh 网络å®ç°äº†æ— çº¿è®¾å¤‡ç„“å¤å¯¹å¤â€é€è®¯ï¼Œå…¶å¯ç”¨äºå»ºç«‹åŒ…å«å¤§é‡è®¾å¤‡ç„ç½‘ç»œă€‚ 设备能将数æ®ä¸­ç»§è‡³ä¸åœ¨åˆå§‹è®¾å¤‡æ— çº¿ç”µè¦†ç›–范围内ç„å…¶ä»–è®¾å¤‡ă€‚è¿™æ ·ï¼Œmesh 网络就能够覆盖é常大ç„物ç†åŒºåŸŸï¼Œå¹¶ä¸”å›æ‹¬å¤§é‡è®¾å¤‡ă€‚Mesh 网络é常适用äºæ¥¼å®‡è‡ªå¨åŒ–ă€ä¼ æ„Ÿå™¨ç½‘络和其他物è”网解决方案，这些情景下数以å计ă€ç™¾è®¡ă€åƒè®¡ç„设备需è¦ä¸å…¶ä»–设备进行安全å¯é ç„é€ä¿¡ă€‚ @@ -37,6 +34,7 @@ ESP-BLE-MESH 快速入门 如æœæ‚¨æ˜¯ç¬¬ä¸€æ¬¡æ¥è§¦ ESP-IDF，请å‚è§ esp-idf :doc:`../../get-started/index` æ¥è®¾ç½®å¼€å‘ç¯å¢ƒï¼Œç¼–译ă€çƒ§å†™å’Œè¿è¡Œç¤ºä¾‹åº”用程åºă€‚ + 硬件å软件准备 -------------- @@ -232,9 +230,8 @@ ESP-BLE-MESH 示例 ESP-BLE-MESH 演示视频 ====================== -* `Provisioning of ESP-BLE-MESH nodes using Smartphone App `_ -* `Espressif Fast Provisioning using ESP-BLE-MESH App `_ -* `Espressif ESP-BLE-MESH and Wi-Fi Coexistence `_ +* `Espressif Fast Provisioning using ESP-BLE-MESH App `_ +* `Espressif ESP-BLE-MESH and Wi-Fi Coexistence `_ ESP-BLE-MESH 常è§é—®é¢˜æ‰‹å†Œ diff --git a/docs/zh_CN/api-guides/fatal-errors.rst b/docs/zh_CN/api-guides/fatal-errors.rst index 76410711e2..53d4eea467 100644 --- a/docs/zh_CN/api-guides/fatal-errors.rst +++ b/docs/zh_CN/api-guides/fatal-errors.rst @@ -279,6 +279,27 @@ GDB Stub 在 GDB ä¼è¯ä¸­ï¼Œæˆ‘们å¯ä»¥æ£€æŸ¥ CPU 寄存器，本地和é™æ€å˜é‡ä»¥å内存中任æ„ä½ç½®ç„å€¼ă€‚ä½†æ˜¯ä¸æ”¯æŒè®¾ç½®æ–­ç‚¹ï¼Œæ”¹å˜ PC 值或者æ¢å¤ç¨‹åºç„è¿è¡Œă€‚è‹¥è¦å¤ä½ç¨‹åºï¼Œè¯·é€€å‡º GDB ä¼è¯ï¼Œåœ¨ IDF 监视器 中è¿ç»­è¾“å…¥ Ctrl-T Ctrl-R，或者按下开å‘æ¿ä¸ç„å¤ä½æŒ‰é”®ä¹Ÿå¯ä»¥é‡æ–°è¿è¡Œç¨‹åºă€‚ +.. _RTC-Watchdog-Timeout: + +RTC 看门狗超时 +---------------- + +RTC 看门狗在å¯å¨ä»£ç ä¸­ç”¨äºè·Ÿè¸ªæ‰§è¡Œæ—¶é—´ï¼Œä¹Ÿæœ‰å©äºé˜²æ­¢ç”±äºç”µæºä¸ç¨³å®å¼•èµ·ç„é”å®ă€‚RTC 看门狗默认å¯ç”¨ï¼Œå‚è§ :ref:`CONFIG_BOOTLOADER_WDT_ENABLE`ă€‚å¦‚æœæ‰§è¡Œæ—¶é—´è¶…时，RTC 看门狗将自å¨é‡å¯ç³»ç»Ÿă€‚此时，ROM 引导å è½½ç¨‹åºå°†æ‰“å°æ¶ˆæ¯ ``RTC Watchdog Timeout`` 说æ˜é‡å¯åŸå› ă€‚ + +.. only:: esp32 + + :: + + rst:0x10 (RTCWDT_RTC_RESET) + +.. only:: not esp32 + + :: + + rst:0x10 (RTCWDT_RTC_RST) + +RTC 看门狗涵盖了ä»ä¸€çº§å¼•å¯¼ç¨‹åºï¼ˆROM 引导程åºï¼‰åˆ°åº”用程åºå¯å¨ç„执行时间，最åˆåœ¨ ROM 引导程åºä¸­è®¾ç½®ï¼Œè€Œå在引导程åºä¸­ä½¿ç”¨ :ref:`CONFIG_BOOTLOADER_WDT_TIME_MS` 选项进行é…置（默认 9000 msï¼‰ă€‚åœ¨åº”ç”¨åˆå§‹åŒ–阶段，由äºæ…¢é€Ÿæ—¶é’Ÿæºå¯èƒ½å·²æ›´æ”¹ï¼ŒRTC 看门狗将被é‡æ–°é…置，最å在调用 ``app_main()`` 之å‰è¢«ç¦ç”¨ă€‚å¯ä»¥ä½¿ç”¨é€‰é¡¹ :ref:`CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE` 以ä¿è¯ RTC 看门狗在调用 ``app_main`` 之å‰ä¸è¢«ç¦ç”¨ï¼Œè€Œæ˜¯ä¿æŒè¿è¡Œç¶æ€ï¼Œç”¨æˆ·éœ€è¦åœ¨åº”用代ç ä¸­å®æœŸâ€œå–‚ç‹—â€ă€‚ + .. _Guru-Meditation-Errors: Guru Meditation 错误 diff --git a/docs/zh_CN/api-guides/index.rst b/docs/zh_CN/api-guides/index.rst index e7d7d175eb..31c1530961 100644 --- a/docs/zh_CN/api-guides/index.rst +++ b/docs/zh_CN/api-guides/index.rst @@ -14,7 +14,7 @@ API æŒ‡å— :SOC_RTC_MEM_SUPPORTED: deep-sleep-stub :SOC_USB_OTG_SUPPORTED: dfu error-handling - :SOC_BT_SUPPORTED: esp-ble-mesh/ble-mesh-index + :SOC_BLE_MESH_SUPPORTED: esp-ble-mesh/ble-mesh-index freertos-smp :SOC_WIFI_MESH_SUPPORT: esp-wifi-mesh event-handling diff --git a/docs/zh_CN/api-guides/jtag-debugging/building-openocd-macos.rst b/docs/zh_CN/api-guides/jtag-debugging/building-openocd-macos.rst index e6060607f5..96f0868be1 100644 --- a/docs/zh_CN/api-guides/jtag-debugging/building-openocd-macos.rst +++ b/docs/zh_CN/api-guides/jtag-debugging/building-openocd-macos.rst @@ -41,6 +41,11 @@ MacOS ç¯å¢ƒä¸‹ä»æºç ç¼–译 OpenOCD .. note:: * 如æœå‘生错误，请解决åå†æ¬¡å°è¯•ç¼–译，直到 ``make`` æˆåŸä¸ºæ­¢ă€‚ + * å‘生 ``Unknown command 'raggedright'`` 错误å¯èƒ½æ˜¯å› ä¸ºå®‰è£…ç„ ``texinfo`` 版本ä¸å¯¹ï¼Œæˆ–是由äºæ²¡æœ‰å°†å…¶æ·»å åˆ° PATH è·¯å¾„ă€‚ä¸ºäº†è§£å†³è¯¥é—®é¢˜ï¼Œåœ¨è¿è¡Œ ``./bootstrap`` å‰ï¼Œè¯·å…ˆè¿è¡Œå¦‚下命令确ä¿å®‰è£…åˆé€‚ç‰ˆæœ¬ç„ ``texinfo`` 并将其添å åˆ° PATH 路径:: + + brew install texinfo + export PATH=/usr/local/opt/texinfo/bin:$PATH + * å¦‚æœ OpenOCD 存在å­æ¨¡å—问题，请 ``cd`` 到 ``openocd-esp32`` 目录，并输入 ``git submodule update --init`` å‘½ä»¤ă€‚ * å¦‚æœ ``./configure`` æˆåŸè¿è¡Œï¼ŒJTAG 被使能ç„ä¿¡æ¯ä¼è¢«æ‰“å°åœ¨ ``OpenOCD configuration summary`` 下é¢ă€‚ * 如æœæ‚¨ç„设备信æ¯æœªæ˜¾ç¤ºåœ¨æ—¥å¿—ä¸­ï¼Œè¯·æ ¹æ® ``../openocd-esp32/doc/INSTALL.txt`` 文中ç„æ述使用 ``./configure`` å¯ç”¨å®ƒă€‚ diff --git a/docs/zh_CN/api-guides/jtag-debugging/configure-other-jtag.rst b/docs/zh_CN/api-guides/jtag-debugging/configure-other-jtag.rst index ab011392ea..2f9d1654db 100644 --- a/docs/zh_CN/api-guides/jtag-debugging/configure-other-jtag.rst +++ b/docs/zh_CN/api-guides/jtag-debugging/configure-other-jtag.rst @@ -1,24 +1,36 @@ -é…置其它 JTAG æ¥å£ +é…置其他 JTAG æ¥å£ ================== :link_to_translation:`en:[English]` å…³äºé€‚é… OpenOCD å’Œ {IDF_TARGET_NAME} ç„ JTAG æ¥å£é€‰æ‹©é—®é¢˜ï¼Œè¯·å‚考 :ref:`jtag-debugging-selecting-jtag-adapter` ç« è‚ï¼Œç¡®ä¿ JTAG 适é…å™¨èƒ½å¤Ÿä¸ OpenOCD å’Œ {IDF_TARGET_NAME} 一åŒå·¥ä½œă€‚然åæŒ‰ç…§ä»¥ä¸‹ä¸‰ä¸ªæ­¥éª¤è¿›è¡Œè®¾ç½®ï¼Œä½¿å…¶æ­£å¸¸å·¥ä½œă€‚ -.. only:: SOC_USB_SERIAL_JTAG_SUPPORTED +.. only:: SOC_USB_SERIAL_JTAG_SUPPORTED and not esp32c3 - é…ç½® eFuses - ^^^^^^^^^^^^^^^^ + é…ç½® eFuse + ^^^^^^^^^^^^^^^^ - {IDF_TARGET_NAME} JTAG æ¥å£é»˜è®¤è¿æ¥è‡³ :doc:`内置 USB_SERIAL_JTAG 外设 `。è¦ä½¿ç”¨å¤–部 JTAG 适é…器，需将 JTAG æ¥å£åˆ‡æ¢è‡³ GPIO 管è„ă€‚æ‚¨å¯ä»¥ä½¿ç”¨ `espefuse.py` 工具æ¥çƒ§å½• eFuse，以完æˆæ¥å£è½¬æ¢ă€‚ + {IDF_TARGET_NAME} JTAG æ¥å£é»˜è®¤è¿æ¥è‡³ :doc:`内置 USB_SERIAL_JTAG 外设 `。è¦ä½¿ç”¨å¤–部 JTAG 适é…器，需将 JTAG æ¥å£åˆ‡æ¢è‡³ GPIO 管è„ă€‚æ‚¨å¯ä»¥ä½¿ç”¨ ``espefuse.py`` 工具æ¥çƒ§å½• eFuse，以完æˆæ¥å£è½¬æ¢ă€‚ - 烧录 eFuse 是一项ä¸å¯é€†ç„æ“作，所以在开始之å‰ï¼Œè¯·è€ƒè™‘ä»¥ä¸‹ä¸¤ç‚¹ï¼ + - 烧录 ``DIS_USB_JTAG`` eFuse å，USB_SERIAL_JTAG å’Œ CPU ç„ JTAG æ¥å£ä¹‹é—´ç„è¿æ¥å°†è¢«æ°¸ä¹…ç¦ç”¨ï¼Œæ­¤å您å¯ä»¥å°† JTAG æ¥å£è¿æ¥åˆ° |jtag-gpio-list|ă€‚æ³¨æ„，烧录å，USB_SERIAL_JTAG ç„ USB CDC åŸèƒ½ä»ç„¶å¯ç”¨ï¼Œå³ä»ç„¶å¯ä»¥é€è¿‡ USB CDC è¿›è¡Œçƒ§å½•å’ŒæŸ¥çœ‹æ—¥å¿—ă€‚ + - 烧录 ``STRAP_JTAG_SEL`` eFuse å，JTAG æ¥å£ç„选择将由 strapping ç®¡è„ |jtag-sel-gpio| æ¥å†³å®ă€‚{IDF_TARGET_NAME} å¤ä½æ—¶ï¼Œå¦‚æœè¯¥ strapping 管è„为ä½ç”µå¹³ï¼ŒJTAG æ¥å£å°†ä½¿ç”¨ |jtag-gpio-list|，如æœä¸ºé«˜ç”µå¹³ï¼ŒUSB_SERIAL_JTAG 将被用作 JTAG æ¥å£ă€‚ - - 烧录 `DIS_USB_JTAG` eFuse å，USB_SERIAL_JTAG å’Œ CPU ç„ JTAG æ¥å£ä¹‹é—´ç„è¿æ¥å°†è¢«æ°¸ä¹…ç¦ç”¨ï¼Œæ­¤å您å¯ä»¥å°† JTAG æ¥å£è¿æ¥åˆ° |jtag-gpio-list|ă€‚æ³¨æ„，烧录å，USB_SERIAL_JTAG ç„ USB CDC åŸèƒ½ä»ç„¶å¯ç”¨ï¼Œå³ä»ç„¶å¯ä»¥é€è¿‡ USB CDC 进行烧录和 log æŸ¥çœ‹ă€‚ - - - 烧录 ``JTAG_SEL_ENABLE`` eFuse å，JTAG æ¥å£ç„选择将由 strapping ç®¡è„ |jtag-sel-gpio| æ¥å†³å®ă€‚{IDF_TARGET_NAME} å¤ä½æ—¶ï¼Œå¦‚æœè¯¥ strapping 管è„为ä½ç”µå¹³ï¼ŒJTAG æ¥å£å°†ä½¿ç”¨ |jtag-gpio-list|，如æœä¸ºé«˜ç”µå¹³ï¼ŒUSB_SERIAL_JTAG 将被用作 JTAG æ¥å£ă€‚ + .. warning:: + 请注æ„，烧录 eFuse 是一项ä¸å¯é€†ç„æ“作，请在开始å‰è°¨æ…考虑以ä¸é€‰é¡¹ă€‚ +.. only:: esp32c3 + + é…ç½® eFuse + ^^^^^^^^^^^^^^^^ + + {IDF_TARGET_NAME} JTAG æ¥å£é»˜è®¤è¿æ¥è‡³ :doc:`内置 USB_SERIAL_JTAG 外设 `。è¦ä½¿ç”¨å¤–部 JTAG 适é…器，需将 JTAG æ¥å£åˆ‡æ¢è‡³ GPIO 管è„ă€‚æ‚¨å¯ä»¥ä½¿ç”¨ ``espefuse.py`` 工具æ¥çƒ§å½• eFuse，以完æˆæ¥å£è½¬æ¢ă€‚ + + 烧录 ``DIS_USB_JTAG`` eFuse å，USB_SERIAL_JTAG å’Œ CPU ç„ JTAG æ¥å£ä¹‹é—´ç„è¿æ¥å°†è¢«æ°¸ä¹…ç¦ç”¨ï¼Œæ­¤å您å¯ä»¥å°† JTAG æ¥å£è¿æ¥åˆ° |jtag-gpio-list|ă€‚æ³¨æ„，烧录å，USB_SERIAL_JTAG ç„ USB CDC åŸèƒ½ä»ç„¶å¯ç”¨ï¼Œå³ä»ç„¶å¯ä»¥é€è¿‡ USB CDC è¿›è¡Œçƒ§å½•å’ŒæŸ¥çœ‹æ—¥å¿—ă€‚ + + .. warning:: + 请注æ„，烧录 eFuse 是一项ä¸å¯é€†ç„æ“作，请在开始å‰è°¨æ…考虑以ä¸é€‰é¡¹ă€‚ + é…置硬件 ^^^^^^^^ @@ -45,4 +57,4 @@ å°† JTAG æ¥å£è¿æ¥åˆ°è®¡ç®—机，打开 {IDF_TARGET_NAME} å’Œ JTAG æ¥å£æ¿ä¸ç„电æºï¼Œç„¶å检查计算机是å¦å¯ä»¥è¯†åˆ«åˆ° JTAG æ¥å£ă€‚ -è¦ç»§ç»­è®¾ç½®è°ƒè¯•ç¯å¢ƒï¼Œè¯·å‰å¾€ :ref:`jtag-debugging-run-openocd` ç« è‚。 +如需继续设置调试ç¯å¢ƒï¼Œè¯·å‰å¾€ :ref:`jtag-debugging-run-openocd` ç« è‚。 diff --git a/docs/zh_CN/api-guides/jtag-debugging/debugging-examples.rst b/docs/zh_CN/api-guides/jtag-debugging/debugging-examples.rst index 5dd9c6b3b6..3a6fb757a7 100644 --- a/docs/zh_CN/api-guides/jtag-debugging/debugging-examples.rst +++ b/docs/zh_CN/api-guides/jtag-debugging/debugging-examples.rst @@ -245,6 +245,7 @@ 5. :ref:`jtag-debugging-examples-command-line-05` 6. :ref:`jtag-debugging-examples-command-line-06` 7. :ref:`jtag-debugging-examples-command-line-07` +8. :ref:`jtag-debugging-examples-command-line-08` .. _jtag-debugging-examples-command-line-01: @@ -445,10 +446,6 @@ 在ä¸å›¾æ‰€ç¤ºç„情况下，应用程åºå·²ç»åœ¨ ``freertos_hooks.c`` 文件ç„第 52 è¡Œæ‚åœè¿è¡Œï¼Œç°åœ¨æ‚¨å¯ä»¥é€è¿‡è¾“å…¥ ``c`` å†æ¬¡å°†å…¶æ¢å¤è¿è¡Œæˆ–者进行如下所述ç„ä¸€äº›è°ƒè¯•å·¥ä½œă€‚ -.. note:: - - 在 MSYS2 ç„ shell 中输入 Ctrl+C 并ä¸ä¼æ‚åœç›®æ ‡ç„è¿è¡Œï¼Œè€Œæ˜¯ä¼é€€å‡ºè°ƒè¯•å™¨ă€‚解决这个问题ç„方法å¯ä»¥é€è¿‡ :ref:`使用 Eclipse æ¥è°ƒè¯• ` 或者å‚考 http://www.mingw.org/wiki/Workaround_for_GDB_Ctrl_C_Interrupt 里ç„è§£å†³æ–¹æ¡ˆă€‚ - .. _jtag-debugging-examples-command-line-04: @@ -627,6 +624,34 @@ (gdb) +.. _jtag-debugging-examples-command-line-08: + +调试 FreeRTOS 对象 +^^^^^^^^^^^^^^^^^^ + +该部分内容或许å¯ä»¥å¸®å©æ‚¨è°ƒè¯• FreeRTOS ä»»å¡äº¤äº’。 +需è¦è°ƒè¯• FreeRTOS ä»»å¡äº¤äº’ç„用户å¯ä½¿ç”¨ GDB 命令 ``freertos``ă€‚è¯¥å‘½ä»¤å¹¶é GDB åŸç”Ÿå‘½ä»¤ï¼Œè€Œæ˜¯æ¥è‡ªäº Python æ‰©å±•æ¨¡å— `freertos-gdb `_，其包å«ä¸€ç³»åˆ—å­å‘½ä»¤:: + + (gdb) freertos + "freertos" åé¢å¿…须紧éå­å‘½ä»¤ç„å称 + freertos å­å‘½ä»¤å¦‚ä¸‹ï¼ + + freertos queue -- 打å°å½“å‰é˜Ÿåˆ—ä¿¡æ¯ + freertos semaphore -- 打å°å½“å‰ä¿¡å·é‡ä¿¡æ¯ + freertos task -- 打å°å½“å‰ä»»å¡åå…¶ç¶æ€ + freertos timer -- 打å°å½“å‰å®æ—¶å™¨ä¿¡æ¯ + +点击 https://pypi.org/project/freertos-gdb 链æ¥äº†è§£æ­¤æ‰©å±•æ¨¡å—ç„详细信æ¯ă€‚ + +.. note:: + + ESP-IDF 在安装 Pyhton 包时ä¼è‡ªå¨å®‰è£… freertos-gdb Python 模å—，详情请å‚考 :ref:`get-started-set-up-tools`。 + + 如æœä½¿ç”¨ ``idf.py gdb`` 命令è¿è¡Œ GDB，FreeRTOS 扩展ä¼è‡ªå¨å è½½ă€‚也å¯ä»¥ä½¿ç”¨ GDB 内部命令 ``python import freertos_gdb`` 使能该模å—。 + + 请ä¿è¯ä½¿ç”¨ Python 3.6 å以ä¸ç‰ˆæœ¬ï¼Œè¯¥ç‰ˆæœ¬å…·æœ‰ Python å…±äº«åº“ă€‚ + + è·å¾—命令ç„帮å©ä¿¡æ¯ ^^^^^^^^^^^^^^^^^^ diff --git a/docs/zh_CN/api-guides/jtag-debugging/index.rst b/docs/zh_CN/api-guides/jtag-debugging/index.rst index 63ad61fa74..f353c3b206 100644 --- a/docs/zh_CN/api-guides/jtag-debugging/index.rst +++ b/docs/zh_CN/api-guides/jtag-debugging/index.rst @@ -249,6 +249,11 @@ OpenOCD 安装完æˆåå°±å¯ä»¥é…ç½® {IDF_TARGET_NAME} 目标（å³å¸¦ JTAG 此外还ä¼æ供在 :ref:`在命令行终端进行调试 ` 下使用 GDB 调试ç„æ¡ˆä¾‹ă€‚ +.. note:: + + :ref:`jtag-debugging-examples-command-line-08` ç›®å‰ä»…适用äºå‘½ä»¤è¡Œè°ƒè¯•ă€‚ + + 在演示之å‰ï¼Œè¯·å®Œæˆ {IDF_TARGET_NAME} 目标æ¿è®¾ç½®å¹¶å è½½ :example:`get-started/blink` 至 {IDF_TARGET_NAME} 中。 diff --git a/docs/zh_CN/api-guides/jtag-debugging/tips-and-quirks.rst b/docs/zh_CN/api-guides/jtag-debugging/tips-and-quirks.rst index d4fdff2907..23e7c600e2 100644 --- a/docs/zh_CN/api-guides/jtag-debugging/tips-and-quirks.rst +++ b/docs/zh_CN/api-guides/jtag-debugging/tips-and-quirks.rst @@ -69,7 +69,9 @@ ESP-IDF 有一些针对 OpenOCD 调试åŸèƒ½ç„选项å¯ä»¥åœ¨ç¼–译时进行设 æ”¯æŒ FreeRTOS ^^^^^^^^^^^^^^^^ -OpenOCD å®Œå…¨æ”¯æŒ ESP-IDF è‡ªå¸¦ç„ FreeRTOS æ“作系统，GDB ä¼å°† FreeRTOS 中ç„ä»»å¡å½“åçº¿ç¨‹ă€‚ä½¿ç”¨ GDB 命令 ``i threads`` å¯ä»¥æŸ¥çœ‹æ‰€æœ‰ç„线程，使用命令 ``thread n`` å¯ä»¥åˆ‡æ¢åˆ°æŸä¸ªå…·ä½“ä»»å¡ç„堆栈，其中 ``n`` 是线程ç„ç¼–å·ă€‚检测 FreeRTOS ç„åŸèƒ½å¯ä»¥åœ¨é…置目标时被ç¦ç”¨ă€‚æ›´å¤è¯¦ç»†ä¿¡æ¯ï¼Œè¯·å‚阅 :ref:`jtag-debugging-tip-openocd-configure-target`. +OpenOCD å®Œå…¨æ”¯æŒ ESP-IDF è‡ªå¸¦ç„ FreeRTOS æ“作系统，GDB ä¼å°† FreeRTOS 中ç„ä»»å¡å½“åçº¿ç¨‹ă€‚ä½¿ç”¨ GDB 命令 ``i threads`` å¯ä»¥æŸ¥çœ‹æ‰€æœ‰ç„线程，使用命令 ``thread n`` å¯ä»¥åˆ‡æ¢åˆ°æŸä¸ªå…·ä½“ä»»å¡ç„堆栈，其中 ``n`` 是线程ç„ç¼–å·ă€‚检测 FreeRTOS ç„åŸèƒ½å¯ä»¥åœ¨é…置目标时被ç¦ç”¨ă€‚æ›´å¤è¯¦ç»†ä¿¡æ¯ï¼Œè¯·å‚阅 :ref:`jtag-debugging-tip-openocd-configure-target`。 + +GDB 具有 FreeRTOS 支æŒç„ Python 扩展模å—ă€‚åœ¨ç³»ç»Ÿè¦æ±‚满足ç„情况下，é€è¿‡ ``idf.py gdb`` 命令，ESP-IDF ä¼å°†è¯¥æ¨¡å—自å¨å è½½åˆ° GDB ä¸­ă€‚è¯¦ç»†ä¿¡æ¯è¯·å‚考 :ref:`jtag-debugging-examples-command-line-08`。 .. only:: esp32 @@ -78,7 +80,7 @@ OpenOCD å®Œå…¨æ”¯æŒ ESP-IDF è‡ªå¸¦ç„ FreeRTOS æ“作系统，GDB ä¼å°† FreeRT 在 OpenOCD ç„é…置文件中设置 SPI 闪存ç„å·¥ä½œç”µå‹ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - ESP32 ç„ MTDI 引è„æ˜¯ç”¨äº JTAG é€ä¿¡ç„四个引è„之一，åŒæ—¶ä¹Ÿæ˜¯ ESP32 ç„ bootstrapping 引è„。ä¸ç”µæ—¶ï¼ŒESP32 ä¼åœ¨ MTDI 引è„ä¸é‡‡æ ·äºŒè¿›åˆ¶ç”µå¹³ï¼Œæ®æ­¤æ¥è®¾ç½®å†…部ç„稳å‹å™¨ï¼Œç”¨äºç»™å¤–éƒ¨ç„ SPI 闪存è¯ç‰‡ä¾›ç”µă€‚如æœä¸ç”µæ—¶ MTDI 引è„ä¸ç„二进制电平为ä½ç”µå¹³ï¼Œåˆ™ç¨³å‹å™¨ä¼è¢«è®¾ç½®ä¸º 3.3 Vï¼›å¦‚æœ MTDI 引è„为高电平，则稳å‹å™¨ä¼è¢«è®¾ç½®ä¸º 1.8 V。MTDI 引è„é€å¸¸éœ€è¦ä¸€ä¸ªä¸æ‹‰ç”µé˜»æˆ–者直æ¥ä½¿èƒ½å†…部ç„å¼±ä¸‹æ‹‰ç”µé˜»ï¼ˆè¯¦è§ `ESP32 系列è¯ç‰‡æ€æœ¯è§„格书 `_ ），具体å–决äºæ‰€ä½¿ç”¨ç„ SPI è¯ç‰‡ç„ç±»å‹ă€‚但是一旦è¿æ¥ä¸ JTAG å，åŸæ¥ç”¨äºå®ç° bootstrapping åŸèƒ½ç„ä¸æ‹‰æˆ–者下拉电阻都ä¼è¢«è¦†ç›–æ‰ă€‚ + ESP32 ç„ MTDI 管è„æ˜¯ç”¨äº JTAG é€ä¿¡ç„四个管è„之一，åŒæ—¶ä¹Ÿæ˜¯ ESP32 ç„ bootstrapping 管è„。ä¸ç”µæ—¶ï¼ŒESP32 ä¼åœ¨ MTDI 管è„ä¸é‡‡æ ·äºŒè¿›åˆ¶ç”µå¹³ï¼Œæ®æ­¤æ¥è®¾ç½®å†…部ç„稳å‹å™¨ï¼Œç”¨äºç»™å¤–éƒ¨ç„ SPI 闪存è¯ç‰‡ä¾›ç”µă€‚如æœä¸ç”µæ—¶ MTDI 管è„ä¸ç„二进制电平为ä½ç”µå¹³ï¼Œåˆ™ç¨³å‹å™¨ä¼è¢«è®¾ç½®ä¸º 3.3 Vï¼›å¦‚æœ MTDI 管è„为高电平，则稳å‹å™¨ä¼è¢«è®¾ç½®ä¸º 1.8 V。MTDI 管è„é€å¸¸éœ€è¦ä¸€ä¸ªä¸æ‹‰ç”µé˜»æˆ–者直æ¥ä½¿èƒ½å†…部ç„å¼±ä¸‹æ‹‰ç”µé˜»ï¼ˆè¯¦è§ `ESP32 系列è¯ç‰‡æ€æœ¯è§„格书 `_ ），具体å–决äºæ‰€ä½¿ç”¨ç„ SPI è¯ç‰‡ç„ç±»å‹ă€‚但是一旦è¿æ¥ä¸ JTAG å，åŸæ¥ç”¨äºå®ç° bootstrapping åŸèƒ½ç„ä¸æ‹‰æˆ–者下拉电阻都ä¼è¢«è¦†ç›–æ‰ă€‚ 为了解决这个问题，OpenOCD ç„æ¿çº§é…置文件（例如 ESP-WROVER-KIT å¼€å‘æ¿ç„ ``board\esp32-wrover-kit-3.3v.cfg``）æ供了 ``ESP32_FLASH_VOLTAGE`` å‚æ•°æ¥è®¾ç½® ``TDO`` ä¿¡å·çº¿åœ¨ç©ºé—²ç¶æ€ä¸‹ç„二进制电平，这样就å¯ä»¥å‡å°‘ç”±äºé—ªå­˜ç”µå‹ä¸æ­£ç¡®è€Œå¯¼è‡´ç„应用程åºå¯å¨ä¸è‰¯ç„几ç‡ă€‚ @@ -172,7 +174,7 @@ TCL 语言中为å˜é‡èµ‹å€¼ç„语法是: * - ``ESP_RTOS`` - è®¾ç½®æˆ ``none`` å¯ä»¥å…³é—­ OpenOCD 对 RTOS ç„支æŒï¼Œè¿™æ ·ç„è¯ï¼Œä½ å°†æ— æ³•åœ¨ GDB ä¸­æŸ¥çœ‹åˆ°çº¿ç¨‹åˆ—è¡¨ă€‚è¿™ä¸ªåŸèƒ½åœ¨è°ƒè¯• FreeRTOS 本身ç„时候ä¼å¾ˆæœ‰ç”¨ï¼Œå¯ä»¥å•æ­¥è°ƒè¯•è°ƒåº¦å™¨ç„代ç ă€‚ * - ``ESP_FLASH_SIZE`` - - è®¾ç½®æˆ ``0`` å¯ä»¥å…³é—­å¯¹ Flash 断点ç„支æŒă€‚ + - è®¾ç½®æˆ ``0`` å¯ä»¥å…³é—­å¯¹ flash 断点ç„支æŒă€‚ * - ``ESP_SEMIHOST_BASEDIR`` - 设置 semihosting 在主机端ç„é»˜è®¤ç›®å½•ă€‚ @@ -190,16 +192,16 @@ TCL 语言中为å˜é‡èµ‹å€¼ç„语法是: .. _jtag-debugging-tip-jtag-pins-reconfigured: -ä¸è¦å°† JTAG 引è„用äºå…¶ä»–åŸèƒ½ +ä¸è¦å°† JTAG 管è„用äºå…¶ä»–åŸèƒ½ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -如æœé™¤äº† {IDF_TARGET_NAME} 模组和 JTAG 适é…器之外ç„其他硬件也è¿æ¥åˆ°äº† JTAG 引è„，那么 JTAG ç„æ“作å¯èƒ½ä¼å—åˆ°å¹²æ‰°ă€‚{IDF_TARGET_NAME} JTAG 使用以下引è„ï¼ +如æœé™¤äº† {IDF_TARGET_NAME} 模组和 JTAG 适é…器之外ç„其他硬件也è¿æ¥åˆ°äº† JTAG 管è„，那么 JTAG ç„æ“作å¯èƒ½ä¼å—åˆ°å¹²æ‰°ă€‚{IDF_TARGET_NAME} JTAG 使用以下管è„ï¼ .. include:: {IDF_TARGET_PATH_NAME}.inc :start-after: jtag-pins :end-before: --- -如æœç”¨æˆ·åº”用程åºæ›´æ”¹äº† JTAG 引è„ç„é…置，JTAG é€ä¿¡å¯èƒ½ä¼å¤±è´¥ă€‚å¦‚æœ OpenOCD 正确åˆå§‹åŒ–（检测到两个 Tensilica 内核），但在程åºè¿è¡ŒæœŸé—´å¤±å»äº†åŒæ­¥å¹¶æ¥å‡ºå¤§é‡ DTR/DIR 错误，则应用程åºå¯èƒ½å°† JTAG 引è„é‡æ–°é…置为其他åŸèƒ½æˆ–者用户忘记将 Vtar è¿æ¥åˆ° JTAG 适é…å™¨ă€‚ +如æœç”¨æˆ·åº”用程åºæ›´æ”¹äº† JTAG 管è„ç„é…置，JTAG é€ä¿¡å¯èƒ½ä¼å¤±è´¥ă€‚å¦‚æœ OpenOCD 正确åˆå§‹åŒ–（检测到两个 Tensilica 内核），但在程åºè¿è¡ŒæœŸé—´å¤±å»äº†åŒæ­¥å¹¶æ¥å‡ºå¤§é‡ DTR/DIR 错误，则应用程åºå¯èƒ½å°† JTAG 管è„é‡æ–°é…置为其他åŸèƒ½æˆ–者用户忘记将 Vtar è¿æ¥åˆ° JTAG 适é…å™¨ă€‚ .. highlight:: none @@ -221,16 +223,16 @@ JTAG ä¸é—ªå­˜å å¯†å’Œå®‰å…¨å¼•å¯¼ Kconfig é…置项 :ref:`CONFIG_SECURE_BOOT_ALLOW_JTAG` å¯ä»¥æ”¹å˜è¿™ä¸ªé»˜è®¤è¡Œä¸ºï¼Œä½¿å¾—用户å³ä½¿å¼€å¯äº†å®‰å…¨å¼•å¯¼æˆ–者闪存å å¯†ï¼Œä»ä¼ä¿ç•™ JTAG ç„åŸèƒ½ă€‚ -然而，因为设置 :ref:`软件断点 ` ç„需è¦ï¼ŒOpenOCD ä¼å°è¯•è‡ªå¨è¯»å†™ Flash 中ç„内容，这ä¼å¸¦æ¥ä¸¤ä¸ªé—®é¢˜ï¼ +然而，因为设置 :ref:`软件断点 ` ç„需è¦ï¼ŒOpenOCD ä¼å°è¯•è‡ªå¨è¯»å†™ flash 中ç„内容，这ä¼å¸¦æ¥ä¸¤ä¸ªé—®é¢˜ï¼ -- 软件断点和闪存å å¯†æ˜¯ä¸å…¼å®¹ç„ï¼Œç›®å‰ OpenOCD å°ä¸æ”¯æŒå¯¹ Flash 中ç„内容进行å å¯†å’Œè§£å¯†ă€‚ +- 软件断点和闪存å å¯†æ˜¯ä¸å…¼å®¹ç„ï¼Œç›®å‰ OpenOCD å°ä¸æ”¯æŒå¯¹ flash 中ç„内容进行å å¯†å’Œè§£å¯†ă€‚ - 如æœå¼€å¯äº†å®‰å…¨å¼•å¯¼åŸèƒ½ï¼Œè®¾ç½®è½¯ä»¶æ–­ç‚¹ä¼æ”¹å˜è¢«ç­¾åç„程åºç„摘è¦ï¼Œä»è€Œä½¿å¾—ç­¾åå¤±æ•ˆă€‚è¿™ä¹Ÿæ„味ç€ï¼Œå¦‚æœè®¾ç½®äº†è½¯ä»¶æ–­ç‚¹ï¼Œç³»ç»Ÿä¼åœ¨ä¸‹æ¬¡é‡å¯æ—¶ç„ç­¾å验è¯é˜¶æ®µå¤±è´¥ï¼Œå¯¼è‡´æ— æ³•å¯å¨ă€‚ 关闭 JTAG ç„软件断点åŸèƒ½ï¼Œå¯ä»¥åœ¨å¯å¨ OpenOCD 时在命令行é¢å¤–å ä¸€é¡¹é…ç½®å‚æ•° ``-c 'set ESP_FLASH_SIZE 0'``，请å‚考 :ref:`jtag-debugging-tip-openocd-config-vars`。 .. note:: - åŒæ ·åœ°ï¼Œå½“å¯ç”¨è¯¥é€‰é¡¹ï¼Œå¹¶ä¸”调试过程中打了软件断点，之å引导程åºå°†æ— æ³•æ ¡éªŒé€è¿‡åº”用程åºç„ç­¾å。 + åŒæ ·åœ°ï¼Œå½“å¯ç”¨è¯¥é€‰é¡¹ï¼Œå¹¶ä¸”在调试过程中设置了软件断点，引导程åºå°†æ— æ³•æ ¡éªŒé€è¿‡åº”用程åºç„ç­¾å。 .. only:: esp32 @@ -255,7 +257,7 @@ Kconfig é…置项 :ref:`CONFIG_SECURE_BOOT_ALLOW_JTAG` å¯ä»¥æ”¹å˜è¿™ä¸ªé»˜è®¤ c. 用äºè°ƒè¯•ç„æ“作系统ç„详细信æ¯ă€‚ d. æ“作系统是在本地计算机è¿è¡Œè¿˜æ˜¯åœ¨è™æ‹Ÿæœºä¸è¿è¡Œï¼Ÿ -2. 创建一个能够演示问题ç„简å•ç¤ºä¾‹å·¥ç¨‹ï¼Œæè¿°å¤ç°è¯¥é—®é¢˜ç„æ­¥éª¤ă€‚ä¸”è¿™ä¸ªè°ƒè¯•ç¤ºä¾‹ä¸èƒ½å—到 Wi-Fi å议栈引入ç„éç¡®å®æ€§è¡Œä¸ºç„å½±å“，因而å†æ¬¡é‡åˆ°åŒæ ·é—®é¢˜æ—¶ï¼Œæ›´å®¹æ˜“å¤ç°ă€‚ +2. 创建一个能够演示问题ç„简å•ç¤ºä¾‹å·¥ç¨‹ï¼Œæè¿°å¤ç°è¯¥é—®é¢˜ç„æ­¥éª¤ă€‚ä¸”è¿™ä¸ªè°ƒè¯•ç¤ºä¾‹ä¸èƒ½å—到 Wi-Fi å议栈引入ç„éç¡®å®æ€§è¡Œä¸ºç„å½±å“，这样å†æ¬¡é‡åˆ°åŒæ ·é—®é¢˜æ—¶ï¼Œæ›´å®¹æ˜“å¤ç°ă€‚ .. highlight:: bash diff --git a/docs/zh_CN/api-guides/linker-script-generation.rst b/docs/zh_CN/api-guides/linker-script-generation.rst index fac18dc0e4..a86d19f092 100644 --- a/docs/zh_CN/api-guides/linker-script-generation.rst +++ b/docs/zh_CN/api-guides/linker-script-generation.rst @@ -7,13 +7,14 @@ {IDF_TARGET_NAME} 中有å¤ä¸ªç”¨äºå­˜æ”¾ä»£ç å’Œæ•°æ®ç„ :ref:`内存区域` ă€‚ä»£ç å’Œåªè¯»æ•°æ®é»˜è®¤å­˜æ”¾åœ¨ flash 中，å¯å†™æ•°æ®å­˜æ”¾åœ¨ RAM 中。ä¸è¿‡æœ‰æ—¶ï¼Œç”¨æˆ·å¿…é¡»æ›´æ”¹é»˜è®¤å­˜æ”¾åŒºåŸŸă€‚ -.. only:: SOC_ULP_SUPPORTED +ä¾‹å¦‚ï¼ - 例如为了æ高性能，将关键代ç å­˜æ”¾åˆ° RAM 中，或者将代ç å­˜æ”¾åˆ° RTC 存储器中以便在 wake up stub å’Œ ULP å处ç†å™¨ä¸­ä½¿ç”¨ă€‚ +.. list:: -.. only:: not SOC_ULP_SUPPORTED - - 例如为了æ高性能，将关键代ç å­˜æ”¾åˆ° RAM 中，或者将代ç å­˜æ”¾åˆ° RTC 存储器中以便在wake up stub ä¸­ä½¿ç”¨ă€‚ + * 将关键代ç å­˜æ”¾åˆ° RAM 中以æ高性能； + * å°†å¯æ‰§è¡Œä»£ç å­˜æ”¾åˆ° IRAM 中，以便在缓存被ç¦ç”¨æ—¶è¿è¡Œè¿™äº›ä»£ç ï¼› + :SOC_RTC_MEM_SUPPORTED: * 将代ç å­˜æ”¾åˆ° RTC 存储器中，以便在 wake stub 中使用； + :SOC_ULP_SUPPORTED: * 将代ç å­˜æ”¾åˆ° RTC 内存中，以便 ULP å处ç†å™¨ä½¿ç”¨ă€‚ 链æ¥å™¨è„本生æˆæœºåˆ¶å¯ä»¥è®©ç”¨æˆ·æŒ‡å®ä»£ç å’Œæ•°æ®åœ¨ ESP-IDF 组件中ç„å­˜æ”¾åŒºåŸŸă€‚ç»„ä»¶åŒ…å«å¦‚何存放符å·ă€ç›®æ ‡æˆ–完整库ç„ä¿¡æ¯ă€‚在æ„建应用程åºæ—¶ï¼Œç»„件中ç„这些信æ¯ä¼è¢«æ”¶é›†ă€è§£æ并处ç†ï¼›ç”Ÿæˆç„存放规则用äºé“¾æ¥åº”用程åºă€‚ diff --git a/docs/zh_CN/api-guides/partition-tables.rst b/docs/zh_CN/api-guides/partition-tables.rst index 982c052e89..ee5db60474 100644 --- a/docs/zh_CN/api-guides/partition-tables.rst +++ b/docs/zh_CN/api-guides/partition-tables.rst @@ -69,7 +69,7 @@ CSV 文件ç„æ ¼å¼ä¸ä¸é¢æ‘˜è¦ä¸­æ‰“å°ç„æ ¼å¼ç›¸åŒï¼Œä½†æ˜¯åœ¨ CSV æ–‡ Name 字段 ~~~~~~~~~ -Name 字段å¯ä»¥æ˜¯ä»»ä½•æœ‰æ„义ç„å称，但ä¸èƒ½è¶…过 16 个字符（之åç„å†…å®¹å°†è¢«æˆªæ–­ï¼‰ă€‚è¯¥å­—æ®µå¯¹ {IDF_TARGET_NAME} 并ä¸æ˜¯ç‰¹åˆ«é‡è¦ă€‚ +Name 字段å¯ä»¥æ˜¯ä»»ä½•æœ‰æ„义ç„å称，但ä¸èƒ½è¶…过 16 个字è‚，其中包括一个空字è‚（之åç„å†…å®¹å°†è¢«æˆªæ–­ï¼‰ă€‚è¯¥å­—æ®µå¯¹ {IDF_TARGET_NAME} 并ä¸æ˜¯ç‰¹åˆ«é‡è¦ă€‚ Type 字段 ~~~~~~~~~ @@ -131,6 +131,11 @@ SubType 字段长度为 8 bit，内容ä¸å…·ä½“分区 Type æœ‰å…³ă€‚ç›®å‰ï¼Œesp 请注æ„如æœç”¨ C++ 编写，应用程åºå®ä¹‰ç„å­ç±»å‹å€¼éœ€è¦è½¬æ¢ä¸º :cpp:type:`esp_partition_type_t`，ä»è€Œä¸ :ref:`分区 API` ä¸€èµ·ä½¿ç”¨ă€‚ +é¢å¤–分区 SubType 字段 +~~~~~~~~~~~~~~~~~~~~~~~~ + +组件å¯ä»¥é€è¿‡è®¾ç½® ``EXTRA_PARTITION_SUBTYPES`` å±æ€§æ¥å®ä¹‰é¢å¤–ç„分区å­ç±»å‹ă€‚ ``EXTRA_PARTITION_SUBTYPES`` 是一个 CMake 列表，其中ç„æ¯ä¸ªæ¡ç›®ç”±å­—符串组æˆï¼Œä»¥é€—å·ä¸ºåˆ†é”，格å¼ä¸º ``, , ``。æ„建系统é€è¿‡è¯¥å±æ€§ä¼è‡ªå¨æ·»å é¢å¤–ç„å­ç±»å‹ï¼Œå¹¶åœ¨ :cpp:type:`esp_partition_subtype_t` 中æ’å…¥å为 ``ESP_PARTITION_SUBTYPE__`` ç„å­—æ®µă€‚é¡¹ç›®å¯ä»¥ä½¿ç”¨è¿™ä¸ªå­ç±»å‹æ¥å®ä¹‰åˆ†åŒºè¡¨ CSV 文件中ç„分区，并使用 :cpp:type:`esp_partition_subtype_t` 中ç„æ–°å­—æ®µă€‚ + Offset å’Œ Size 字段 ~~~~~~~~~~~~~~~~~~~ diff --git a/docs/zh_CN/api-guides/tools/idf-tools-notes.inc b/docs/zh_CN/api-guides/tools/idf-tools-notes.inc index 5af2e9a693..ec7bb478c0 100644 --- a/docs/zh_CN/api-guides/tools/idf-tools-notes.inc +++ b/docs/zh_CN/api-guides/tools/idf-tools-notes.inc @@ -37,11 +37,6 @@ .. tool-esp32ulp-elf-notes ---- - -.. tool-esp32s2ulp-elf-notes - - --- .. tool-openocd-esp32-notes @@ -79,6 +74,11 @@ On Linux and macOS, it is recommended to install ninja using the OS package mana .. tool-dfu-util-notes +--- + +.. tool-esp-rom-elfs-notes + + --- .. tool-idf-python-notes diff --git a/docs/zh_CN/api-guides/wifi.rst b/docs/zh_CN/api-guides/wifi.rst index 1b03912d14..d2388e03e5 100644 --- a/docs/zh_CN/api-guides/wifi.rst +++ b/docs/zh_CN/api-guides/wifi.rst @@ -5,9 +5,11 @@ {IDF_TARGET_NAME} Wi-Fi åŸèƒ½åˆ—表 ------------------------------------ +{IDF_TARGET_NAME} 支æŒä»¥ä¸‹ Wi-Fi åŸèƒ½ï¼ + .. only:: esp32 or esp32s2 or esp32c3 or esp32s3 - - æ”¯æŒ 4 个è™æ‹Ÿæ¥å£ï¼Œå³STAă€APă€Sniffer å’Œ reserved。 + - æ”¯æŒ 4 个è™æ‹Ÿæ¥å£ï¼Œå³ STAă€APă€Sniffer å’Œ reserved。 - 支æŒä»… station 模å¼ă€ä»… AP 模å¼ă€station/AP å…±å­˜æ¨¡å¼ - 支æŒä½¿ç”¨ IEEE 802.11bă€IEEE 802.11gă€IEEE 802.11n å’Œ API é…ç½®åè®®æ¨¡å¼ - æ”¯æŒ WPA/WPA2/WPA3/WPA2-ä¼ä¸ç‰ˆ/WPA3-ä¼ä¸ç‰ˆ/WAPI/WPS å’Œ DPP @@ -1167,7 +1169,6 @@ API esp_wifi_set_config() å¯ç”¨äºé…ç½® APă€‚ä¸‹è¡¨è¯¦ç»†ä»‹ç»äº†å„个字段 - beacon é—´é”ă€‚å€¼ä¸º 100 ~ 60000 ms，默认值为 100 msă€‚å¦‚æœè¯¥å€¼ä¸åœ¨ä¸è¿°èŒƒå›´ï¼ŒAP é»˜è®¤å– 100 ms。 - Wi-Fi åè®®æ¨¡å¼ +++++++++++++++++++++++++ @@ -1364,13 +1365,7 @@ Wi-Fi 国家/åœ°åŒºä»£ç  æ‰«ææ—¶ï¼ - - å¦‚æœ schan+nchan-1>11ï¼ - - 主å¨æ‰«æ起始信é“è‡³ä¿¡é“ 11，被å¨æ‰«æä¿¡é“ 12 至 ä¿¡é“ 14。 - - - å¦‚æœ schan+nchan-1<=11ï¼ - - 主å¨æ‰«æ起始信é“è‡³ä¿¡é“ schan+nchan-1，被å¨æ‰«æä¿¡é“ schan+nchan 至 ä¿¡é“ 14。 + 主å¨æ‰«æä¿¡é“ 1 è‡³ä¿¡é“ 11，被å¨æ‰«æä¿¡é“ 12 至 ä¿¡é“ 14。 请记ä½ï¼Œå¦‚æœå¸¦æœ‰éè— SSID ç„ AP å’Œ station 被设置在被å¨æ‰«æä¿¡é“ä¸ï¼Œè¢«å¨æ‰«æ将无法找到该 APă€‚ä¹Ÿå°±æ˜¯è¯´ï¼Œå¦‚æœåº”用程åºå¸Œæœ›åœ¨æ¯ä¸ªä¿¡é“中找到带有éè— SSID ç„ AP，国家/地区信æ¯åº”该é…置为 WIFI_COUNTRY_POLICY_MANUAL。 @@ -1380,24 +1375,25 @@ Wi-Fi 国家/åœ°åŒºä»£ç  æ‰«ææ—¶ï¼ - - å¦‚æœ schan+nchan-1>11ï¼ + 主å¨æ‰«æä¿¡é“ schan è‡³ä¿¡é“ schan+nchan-1。 - 主å¨æ‰«æ起始信é“è‡³ä¿¡é“ 11，被å¨æ‰«æä¿¡é“ 12 至 ä¿¡é“ schan+nchan-1。 - - - å¦‚æœ schan+nchan-1<=11ï¼ - - 主å¨æ‰«æ起始信é“è‡³ä¿¡é“ schan+nchan-1。 * - AP æ¨¡å¼ - WIFI_COUNTRY_POLICY_AUTO - 总是使用é…ç½®ç„国家/地区信æ¯ă€‚ + * - AP æ¨¡å¼ - WIFI_COUNTRY_POLICY_MANUAL - 总是使用é…ç½®ç„国家/地区信æ¯ă€‚ + * - station/AP å…±å­˜æ¨¡å¼ - WIFI_COUNTRY_POLICY_AUTO - - å¦‚æœ station ä¸è¿æ¥ä»»ä½•å¤–部 AP，AP 使用é…ç½®ç„国家/地区信æ¯ă€‚å¦‚æœ station è¿æ¥ä¸€ä¸ªå¤–部 AP，该 AP ç„国家/地区信æ¯ä¸è¯¥ station 相åŒă€‚ + - 该 station ä¸ station 模å¼ă€WIFI_COUNTRY_POLICY_AUTO 策略下使用ç„国家/地区信æ¯ç›¸åŒă€‚ + å¦‚æœ station ä¸è¿æ¥ä»»ä½•å¤–部 AP，AP 使用é…ç½®ç„国家/地区信æ¯ă€‚å¦‚æœ station è¿æ¥ä¸€ä¸ªå¤–部 AP，该 AP ç„国家/地区信æ¯ä¸è¯¥ station 相åŒă€‚ - ä¸ station 模å¼ă€WIFI_COUNTRY_POLICY_AUTO 策略下使用ç„国家/地区信æ¯ç›¸åŒă€‚ + * - station/AP å…±å­˜æ¨¡å¼ + - WIFI_COUNTRY_POLICY_MANUAL + - 该 station ä¸ station 模å¼ă€WIFI_COUNTRY_POLICY_MANUAL 策略下使用ç„国家/地区信æ¯ç›¸åŒă€‚ + 该 AP ä¸ AP 模å¼ă€WIFI_COUNTRY_POLICY_MANUAL 策略下使用ç„国家/地区信æ¯ç›¸åŒă€‚ ä¸»ä¿¡é“ @@ -1547,7 +1543,7 @@ AP ç¡çœ  - iperf example - 15575346 - 使用 iperf example 测试ååé‡æ—¶ï¼Œsdkconfig 是 :idf_file:` 示例/wifi/iperf/sdkconfig.defaults.esp32`。 + 使用 iperf example 测试ååé‡æ—¶ï¼Œsdkconfig 是 :idf_file:`examples/wifi/iperf/sdkconfig.defaults.esp32`。 .. only:: esp32s2 @@ -1591,7 +1587,7 @@ AP ç¡çœ  - iperf example - 15575346 - 使用 iperf example 测试ååé‡æ—¶ï¼Œsdkconfig 是 :idf_file:` 示例/wifi/iperf/sdkconfig.defaults.esp32s2`。 + 使用 iperf example 测试ååé‡æ—¶ï¼Œsdkconfig 是 :idf_file:`examples/wifi/iperf/sdkconfig.defaults.esp32s2`。 .. only:: esp32c3 @@ -1635,7 +1631,7 @@ AP ç¡çœ  - iperf example - 15575346 - 使用 iperf example 测试ååé‡æ—¶ï¼Œsdkconfig 是 :idf_file:` 示例/wifi/iperf/sdkconfig.defaults.esp32c3`。 + 使用 iperf example 测试ååé‡æ—¶ï¼Œsdkconfig 是 :idf_file:`examples/wifi/iperf/sdkconfig.defaults.esp32c3`。 .. only:: esp32s3 @@ -1679,7 +1675,7 @@ AP ç¡çœ  - iperf example - 15575346 - 使用 iperf example 测试ååé‡æ—¶ï¼Œsdkconfig 是 :idf_file:` 示例/wifi/iperf/sdkconfig.defaults.esp32s3`。 + 使用 iperf example 测试ååé‡æ—¶ï¼Œsdkconfig 是 :idf_file:`examples/wifi/iperf/sdkconfig.defaults.esp32s3`。 Wi-Fi 80211 æ•°æ®åŒ…å‘é€ --------------------------- diff --git a/docs/zh_CN/api-reference/bluetooth/index.rst b/docs/zh_CN/api-reference/bluetooth/index.rst index b1a3f3e0de..46f147f751 100644 --- a/docs/zh_CN/api-reference/bluetooth/index.rst +++ b/docs/zh_CN/api-reference/bluetooth/index.rst @@ -8,9 +8,9 @@ bt_common bt_le - :SOC_CLASSIC_BT_SUPPORTED: classic_bt + :SOC_BT_CLASSIC_SUPPORTED: classic_bt controller_vhci - esp-ble-mesh + :SOC_BLE_MESH_SUPPORTED: esp-ble-mesh nimble/index ESP-IDF ç›®å‰æ”¯æŒä¸¤ä¸ªä¸»æœºå †æ ˆă€‚åŸºäº Bluedroid ç„堆栈（默认）支æŒä¼ ç»Ÿè“牙和 BLEï¼Œè€ŒåŸºäº Apache NimBLE ç„å †æ ˆä»…æ”¯æŒ BLEă€‚ç”¨æˆ·å¯å‚考如下信æ¯è¿›è¡Œé€‰æ‹©ï¼ diff --git a/docs/zh_CN/api-reference/network/esp_wifi.rst b/docs/zh_CN/api-reference/network/esp_wifi.rst index 929c423250..6baee6755a 100644 --- a/docs/zh_CN/api-reference/network/esp_wifi.rst +++ b/docs/zh_CN/api-reference/network/esp_wifi.rst @@ -20,11 +20,7 @@ Wi-Fi 库支æŒé…ç½®åç›‘æ§ {IDF_TARGET_NAME} Wi-Fi è¿ç½‘åŸèƒ½ă€‚支æŒé… 应用示例 ---------- -ESP-IDF ç¤ºä¾‹é¡¹ç›®ç„ :example:`wifi` 目录下包å«ä»¥ä¸‹åº”用程åºï¼ - -* Wi-Fi 示例代ç ï¼› - -* 一个简å•ç„åº”ç”¨ç¨‹åº `esp-idf-template `_ï¼Œå±•ç¤ºäº†æœ€åŸºç¡€ç„ IDF 项目结æ„。 +ESP-IDF ä»“åº“ç„ :example:`wifi` 目录下æ供了演示 Wi-Fi 库åŸèƒ½ç„几个应用示例，请查看 :example_file:`README ` 了解更å¤è¯¦ç»†ä¿¡æ¯ă€‚ API å‚考 diff --git a/docs/zh_CN/api-reference/peripherals/gpio.rst b/docs/zh_CN/api-reference/peripherals/gpio.rst index f7b34b9bf4..59b943fb71 100644 --- a/docs/zh_CN/api-reference/peripherals/gpio.rst +++ b/docs/zh_CN/api-reference/peripherals/gpio.rst @@ -198,7 +198,8 @@ GPIO & RTC GPIO - JTAGï¼GPIO12-15 é€å¸¸ç”¨äºåœ¨çº¿è°ƒè¯•ă€‚ - GPIï¼GPIO34-39 åªèƒ½è®¾ç½®ä¸ºè¾“入模å¼ï¼Œä¸å…·å¤‡è½¯ä»¶ä½¿èƒ½ç„ä¸æ‹‰æˆ–下拉åŸèƒ½ă€‚ - TXD & RXD é€å¸¸ç”¨äºçƒ§å½•å’Œè°ƒè¯•ă€‚ - - ADC2ï¼ä½¿ç”¨ Wi-Fi æ—¶ä¸èƒ½ä½¿ç”¨ ADC2 管è„ă€‚å› æ­¤ï¼Œå¦‚æœæ‚¨åœ¨ä½¿ç”¨ Wi-Fi æ—¶æ— æ³•ä» ADC2 GPIO è·å–值，å¯ä»¥è€ƒè™‘使用 ADC1 GPIO æ¥è§£å†³è¯¥é—®é¢˜ă€‚æ›´å¤è¯¦æƒ…请å‚考 `ADC é™åˆ¶ `_。 + - ADC2ï¼ä½¿ç”¨ Wi-Fi æ—¶ä¸èƒ½ä½¿ç”¨ ADC2 管è„ă€‚å› æ­¤ï¼Œå¦‚æœæ‚¨åœ¨ä½¿ç”¨ Wi-Fi æ—¶æ— æ³•ä» ADC2 GPIO è·å–值，å¯ä»¥è€ƒè™‘使用 ADC1 GPIO æ¥è§£å†³è¯¥é—®é¢˜ă€‚æ›´å¤è¯¦æƒ…请å‚考 :ref:`ADC è¿ç»­è½¬æ¢æ¨¡å¼ä¸‹ç„硬件é™åˆ¶ ` 以å :ref:`ADC å•æ¬¡è½¬æ¢æ¨¡å¼ä¸‹ç„硬件é™åˆ¶`。 + - 使用 ADC 或ç¡çœ æ¨¡å¼ä¸‹ä½¿ç”¨ Wi-Fi å’Œè“牙时，请ä¸è¦ä½¿ç”¨ GPIO36 å’Œ GPIO39 ç„ä¸­æ–­ă€‚æœ‰å…³é—®é¢˜ç„详细æ述，请å‚考 `ESP32 ECO å’Œ Bug 解决方法 `_ > 中ç„第 3.11 è‚。 .. only:: esp32s2 diff --git a/docs/zh_CN/api-reference/peripherals/gptimer.rst b/docs/zh_CN/api-reference/peripherals/gptimer.rst index 18d0702ea5..6d144568e0 100644 --- a/docs/zh_CN/api-reference/peripherals/gptimer.rst +++ b/docs/zh_CN/api-reference/peripherals/gptimer.rst @@ -17,18 +17,18 @@ 下文介ç»äº†é…置和æ“作å®æ—¶å™¨ç„å¸¸è§„æ­¥éª¤ï¼ -- :ref:`resource-allocation` - è·å–å®æ—¶å™¨å¥æŸ„应设置ç„å‚数，以å如何在é€ç”¨å®æ—¶å™¨å®Œæˆå·¥ä½œæ—¶å›æ”¶èµ„æºă€‚ +- :ref:`gptimer-resource-allocation` - è·å–å®æ—¶å™¨å¥æŸ„应设置ç„å‚数，以å如何在é€ç”¨å®æ—¶å™¨å®Œæˆå·¥ä½œæ—¶å›æ”¶èµ„æºă€‚ - :ref:`set-and-get-count-value` - 如何强制å®æ—¶å™¨ä»èµ·ç‚¹å¼€å§‹è®¡æ•°ï¼Œä»¥å如何éæ—¶è·å–è®¡æ•°å€¼ă€‚ - :ref:`set-up-alarm-action` - å¯å¨è­¦æ¥äº‹ä»¶åº”设置ç„å‚æ•°ă€‚ -- :ref:`register-event-callbacks` - 如何将用户ç„特å®ä»£ç æŒ‚载到警æ¥äº‹ä»¶å›è°ƒå‡½æ•°ă€‚ +- :ref:`gptimer-register-event-callbacks` - 如何将用户ç„特å®ä»£ç æŒ‚载到警æ¥äº‹ä»¶å›è°ƒå‡½æ•°ă€‚ - :ref:`enable-and-disable-timer` - 如何使能和ç¦ç”¨å®æ—¶å™¨ă€‚ - :ref:`start-and-stop-timer` - é€è¿‡ä¸åŒæ¥è­¦è¡Œä¸ºå¯å¨å®æ—¶å™¨ç„å…¸å‹ä½¿ç”¨åœºæ™¯ă€‚ -- :ref:`power-management` - 选择ä¸åŒç„时钟æºå°†ä¼å¦‚何影å“åŸè€—。 -- :ref:`iram-safe` - 在 cache ç¦ç”¨ç„情况下，如何更好地让å®æ—¶å™¨å¤„ç†ä¸­æ–­äº‹å¡ä»¥åå®ç° IO æ§åˆ¶åŸèƒ½ă€‚ -- :ref:`thread-safety` - 驱å¨ç¨‹åºä¿è¯å“ªäº› API çº¿ç¨‹å®‰å…¨ă€‚ -- :ref:`kconfig-options` - 支æŒç„ Kconfig 选项，这些选项ä¼å¯¹é©±å¨ç¨‹åºè¡Œä¸ºäº§ç”Ÿä¸åŒå½±å“。 +- :ref:`gptimer-power-management` - 选择ä¸åŒç„时钟æºå°†ä¼å¦‚何影å“åŸè€—。 +- :ref:`gptimer-iram-safe` - 在 cache ç¦ç”¨ç„情况下，如何更好地让å®æ—¶å™¨å¤„ç†ä¸­æ–­äº‹å¡ä»¥åå®ç° IO æ§åˆ¶åŸèƒ½ă€‚ +- :ref:`gptimer-thread-safety` - 驱å¨ç¨‹åºä¿è¯å“ªäº› API çº¿ç¨‹å®‰å…¨ă€‚ +- :ref:`gptimer-kconfig-options` - 支æŒç„ Kconfig 选项，这些选项ä¼å¯¹é©±å¨ç¨‹åºè¡Œä¸ºäº§ç”Ÿä¸åŒå½±å“。 -.. _resource-allocation: +.. _gptimer-resource-allocation: 资æºåˆ†é… ^^^^^^^^^^^^^^^^^^ @@ -39,7 +39,7 @@ è¦å®‰è£…一个å®æ—¶å™¨å®ä¾‹ï¼Œéœ€è¦æå‰æä¾›é…置结æ„体 :cpp:type:`gptimer_config_t`ï¼ -- :cpp:member:`gptimer_config_t::clk_src` 选择å®æ—¶å™¨ç„时钟æºă€‚:cpp:type:`gptimer_clock_source_t` 中列出å¤ä¸ªå¯ç”¨æ—¶é’Ÿï¼Œä»…å¯é€‰æ‹©å…¶ä¸­ä¸€ä¸ªæ—¶é’Ÿă€‚了解ä¸åŒæ—¶é’Ÿæºå¯¹åŸè€—ç„å½±å“ï¼Œè¯·æŸ¥çœ‹ç« è‚ :ref:`power-management`。 +- :cpp:member:`gptimer_config_t::clk_src` 选择å®æ—¶å™¨ç„时钟æºă€‚:cpp:type:`gptimer_clock_source_t` 中列出å¤ä¸ªå¯ç”¨æ—¶é’Ÿï¼Œä»…å¯é€‰æ‹©å…¶ä¸­ä¸€ä¸ªæ—¶é’Ÿă€‚了解ä¸åŒæ—¶é’Ÿæºå¯¹åŸè€—ç„å½±å“ï¼Œè¯·æŸ¥çœ‹ç« è‚ :ref:`gptimer-power-management`。 - :cpp:member:`gptimer_config_t::direction` 设置å®æ—¶å™¨ç„计数方å‘，:cpp:type:`gptimer_count_direction_t` 中列出å¤ä¸ªæ”¯æŒç„æ–¹å‘，仅å¯é€‰æ‹©å…¶ä¸­ä¸€ä¸ªæ–¹å‘。 @@ -94,7 +94,7 @@ 如æœè­¦æ¥å€¼å·²è®¾ç½®ä¸”å®æ—¶å™¨è¶…过该值，则ä¼ç«‹å³è§¦å‘è­¦æ¥ă€‚ -.. _register-event-callbacks: +.. _gptimer-register-event-callbacks: 注册事件å›è°ƒå‡½æ•° ^^^^^^^^^^^^^^^^^^^^^^^^ @@ -116,7 +116,7 @@ * 此函数将æå®æ—¶å™¨é©±å¨ç¨‹åºç„ç¶æ€ä» **init** 切æ¢ä¸º **enable**。 * å¦‚æœ :cpp:func:`gptimer_register_event_callbacks` å·²ç»å»¶è¿Ÿå®‰è£…中断æœå¡ï¼Œæ­¤å‡½æ•°å°†ä½¿èƒ½ä¸­æ–­æœå¡ă€‚ -* 如æœé€‰æ‹©äº†ç‰¹å®ç„时钟æºï¼ˆä¾‹å¦‚ APB 时钟），此函数将è·å–适当ç„电æºç®¡ç†é”ă€‚äº†è§£æ›´å¤ä¿¡æ¯ï¼Œè¯·æŸ¥çœ‹ç« è‚ :ref:`power-management`。 +* 如æœé€‰æ‹©äº†ç‰¹å®ç„时钟æºï¼ˆä¾‹å¦‚ APB 时钟），此函数将è·å–适当ç„电æºç®¡ç†é”ă€‚äº†è§£æ›´å¤ä¿¡æ¯ï¼Œè¯·æŸ¥çœ‹ç« è‚ :ref:`gptimer-power-management`。 调用 :cpp:func:`gptimer_disable` ä¼è¿›è¡Œç›¸åç„æ“作，å³å°†å®æ—¶å™¨é©±å¨ç¨‹åºæ¢å¤åˆ° **init** ç¶æ€ï¼Œç¦ç”¨ä¸­æ–­æœå¡å¹¶é‡æ”¾ç”µæºç®¡ç†é”。 @@ -256,7 +256,7 @@ ESP_ERROR_CHECK(gptimer_enable(gptimer)); ESP_ERROR_CHECK(gptimer_start(gptimer, &alarm_config)); -.. _power-management: +.. _gptimer-power-management: 电æºç®¡ç† ^^^^^^^^^^^^^^^^^ @@ -267,7 +267,7 @@ 如æœé€‰æ‹© :cpp:enumerator:`GPTIMER_CLK_SRC_XTAL` 等其他时钟æºï¼Œé‚£ä¹ˆé©±å¨ç¨‹åºä¸ä¼å®‰è£…电æºç®¡ç†é”。åªè¦æ—¶é’Ÿæºä»å¯æ供足够ç„分辨ç‡ï¼ŒXTAL 时钟æºå°±æ›´é€‚åˆä½åŸè€—åº”ç”¨ă€‚ -.. _iram-safe: +.. _gptimer-iram-safe: IRAM 安全 ^^^^^^^^^^^^^^^^^^ @@ -290,7 +290,7 @@ IRAM 安全 - :cpp:func:`gptimer_set_raw_count` - :cpp:func:`gptimer_set_alarm_action` -.. _thread-safety: +.. _gptimer-thread-safety: 线程安全 ^^^^^^^^^^^^^^^^^^ @@ -307,13 +307,13 @@ IRAM 安全 å°† :cpp:type:`gptimer_handle_t` 作为第一个ä½ç½®å‚æ•°ç„其他函数ä¸è¢«è§†ä½œçº¿ç¨‹å®‰å…¨ï¼Œä¹Ÿå°±æ˜¯è¯´åº”该é¿å…ä»å¤ä¸ªä»»å¡ä¸­è°ƒç”¨è¿™äº›å‡½æ•°ă€‚ -.. _kconfig-options: +.. _gptimer-kconfig-options: Kconfig 选项 ^^^^^^^^^^^^^^^^^^^^^^ -- :ref:`CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM` æ§åˆ¶æ”¾ç½®é€ç”¨å®æ—¶å™¨æ§åˆ¶å‡½æ•°ï¼ˆIRAM 或 flash）ç„ä½ç½®ă€‚了解更å¤ä¿¡æ¯ï¼Œè¯·å‚è€ƒç« è‚ :ref:`iram-safe`。 -- :ref:`CONFIG_GPTIMER_ISR_IRAM_SAFE` æ§åˆ¶é»˜è®¤ ISR 程åºåœ¨ cache ç¦ç”¨æ—¶æ˜¯å¦å¯ä»¥è¿è¡Œă€‚了解更å¤ä¿¡æ¯ï¼Œè¯·å‚è€ƒç« è‚ :ref:`iram-safe`。 +- :ref:`CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM` æ§åˆ¶æ”¾ç½®é€ç”¨å®æ—¶å™¨æ§åˆ¶å‡½æ•°ï¼ˆIRAM 或 flash）ç„ä½ç½®ă€‚了解更å¤ä¿¡æ¯ï¼Œè¯·å‚è€ƒç« è‚ :ref:`gptimer-iram-safe`。 +- :ref:`CONFIG_GPTIMER_ISR_IRAM_SAFE` æ§åˆ¶é»˜è®¤ ISR 程åºåœ¨ cache ç¦ç”¨æ—¶æ˜¯å¦å¯ä»¥è¿è¡Œă€‚了解更å¤ä¿¡æ¯ï¼Œè¯·å‚è€ƒç« è‚ :ref:`gptimer-iram-safe`。 - :ref:`CONFIG_GPTIMER_ENABLE_DEBUG_LOG` 用äºå¯ç”¨è°ƒè¯•æ—¥å¿—è¾“å‡ºă€‚å¯ç”¨è¿™ä¸€é€‰é¡¹å°†å¢å å›ºä»¶äºŒè¿›åˆ¶æ–‡ä»¶å¤§å°ă€‚ 应用示例 diff --git a/docs/zh_CN/api-reference/peripherals/i2c.rst b/docs/zh_CN/api-reference/peripherals/i2c.rst index b1bb004acf..4e148f7079 100644 --- a/docs/zh_CN/api-reference/peripherals/i2c.rst +++ b/docs/zh_CN/api-reference/peripherals/i2c.rst @@ -105,6 +105,7 @@ I2C 驱å¨ç¨‹åºç®¡ç†åœ¨ I2C 总线ä¸è®¾å¤‡ç„é€ä¿¡ï¼Œè¯¥é©±å¨ç¨‹åºå…·å¤‡ .mode = I2C_MODE_SLAVE, .slave.addr_10bit_en = 0, .slave.slave_addr = ESP_SLAVE_ADDR, // address of your project + .clk_flags = 0, }; 在此阶段，:cpp:func:`i2c_param_config` 还将其他 I2C é…ç½®å‚数设置为 I2C 总线å议规范中å®ä¹‰ç„é»˜è®¤å€¼ă€‚æœ‰å…³é»˜è®¤å€¼å修改默认值ç„详细信æ¯ï¼Œè¯·å‚考 :ref:`i2c-api-customized-configuration`。 diff --git a/docs/zh_CN/api-reference/peripherals/touch_pad.rst b/docs/zh_CN/api-reference/peripherals/touch_pad.rst index 42b161e2f3..cfc9413a17 100644 --- a/docs/zh_CN/api-reference/peripherals/touch_pad.rst +++ b/docs/zh_CN/api-reference/peripherals/touch_pad.rst @@ -133,14 +133,27 @@ 电å‹é—¨é™ï¼ˆå‚考ä½å€¼/å‚考高值）ă€é€Ÿç‡ï¼ˆæ–œç‡ï¼‰ä¸æµ‹é‡æ—¶é—´ç„å…³ç³»å¦‚ä¸‹å›¾æ‰€ç¤ºï¼ -.. figure:: ../../../_static/touch_pad-measurement-parameters.jpg - :align: center - :alt: Touch Pad - relationship between measurement parameters - :figclass: align-center +.. only:: SOC_TOUCH_VERSION_1 - 触摸传感器 - 测é‡å‚数之间ç„关系 + .. figure:: ../../../_static/touch_pad-measurement-parameters.jpg + :align: center + :alt: Touch Pad - relationship between measurement parameters + :figclass: align-center -ä¸å›¾ä¸­ç„ *Output* 代表触摸传感器读值，å³ä¸€ä¸ªæµ‹é‡å‘¨æœŸå†…测得ç„è„‰å†²è®¡æ•°å€¼ă€‚ + 触摸传感器 - 测é‡å‚数之间ç„关系 + + ä¸å›¾ä¸­ç„ *Output* 代表触摸传感器读值，å³ä¸€ä¸ªæµ‹é‡å‘¨æœŸå†…测得ç„è„‰å†²è®¡æ•°å€¼ă€‚ + +.. only:: SOC_TOUCH_VERSION_2 + + .. figure:: ../../../_static/touch_pad-measurement-parameters-version2.png + :align: center + :alt: Touch Pad - relationship between measurement parameters + :figclass: align-center + + 触摸传感器 - 测é‡å‚数之间ç„关系 + + ä¸å›¾ä¸­ç„ *Output* 代表触摸传感器读值，å³å›ºå®å……放电次数所需ç„æ—¶é—´ă€‚ 所有函数å‡æˆå¯¹å‡ºç°ï¼Œç”¨äºè®¾å®æŸä¸€ç‰¹å®å‚数，并è·å–当å‰å‚æ•°å€¼ă€‚ä¾‹å¦‚ï¼:cpp:func:`touch_pad_set_voltage` å’Œ :cpp:func:`touch_pad_get_voltage`。 diff --git a/docs/zh_CN/api-reference/storage/fatfs.rst b/docs/zh_CN/api-reference/storage/fatfs.rst index c3aa464dc3..9f84ef9b1b 100644 --- a/docs/zh_CN/api-reference/storage/fatfs.rst +++ b/docs/zh_CN/api-reference/storage/fatfs.rst @@ -121,7 +121,10 @@ FatFs 分区生æˆå™¨ 2. base_dir - 目录å称，该目录ä¼è¢«ç¼–ç ä¸º FatFs 分区，也å¯ä»¥é€‰æ‹©å°†å…¶è¢«çƒ§å½•è¿›è®¾å¤‡ă€‚但注æ„必须在分区表中指å®åˆé€‚ç„分区大å°ă€‚ -3. ``FLASH_IN_PROJECT`` 标志 - 用户å¯ä»¥é€è¿‡æŒ‡å® ``FLASH_IN_PROJECT``，选择在执行 ``idf.py flash -p `` 时让分区镜åƒè‡ªå¨ä¸åº”用程åºäºŒè¿›åˆ¶æ–‡ä»¶ă€åˆ†åŒºè¡¨ç­‰ä¸€åŒçƒ§å½•è¿›è®¾å¤‡ă€‚ +3. ``FLASH_IN_PROJECT`` 标志 - å¯é€‰å‚数，用户å¯ä»¥é€è¿‡æŒ‡å® ``FLASH_IN_PROJECT``，选择在执行 ``idf.py flash -p `` 时让分区镜åƒè‡ªå¨ä¸åº”用程åºäºŒè¿›åˆ¶æ–‡ä»¶ă€åˆ†åŒºè¡¨ç­‰ä¸€åŒçƒ§å½•è¿›è®¾å¤‡ă€‚ + +4. ``PRESERVE_TIME`` 标志 - å¯é€‰å‚数，用户å¯å¼ºåˆ¶è®©ç›®æ ‡é•œåƒä¿ç•™æºæ–‡ä»¶å¤¹ç„æ—¶é—´æˆ³ă€‚å¦‚æœä¸ä¿ç•™ï¼Œæ¯ä¸ªç›®æ ‡é•œåƒç„时间戳都将设置为 FATFS 默认åˆå§‹æ—¶é—´ï¼ˆ1980 å¹´ 1 月 1 æ—¥ï¼‰ă€‚ + 例如:: @@ -141,4 +144,4 @@ FatFs 分区分æ器 您å¯ä»¥ä½¿ç”¨:: - ./fatfsparse.py [-h] [--long-name-support] [--wear-leveling] fatfs_image.img + ./fatfsparse.py [-h] [--wl-layer {detect,enabled,disabled}] fatfs_image.img diff --git a/docs/zh_CN/api-reference/storage/index.rst b/docs/zh_CN/api-reference/storage/index.rst index 5dfbfae2d5..26f2309b03 100644 --- a/docs/zh_CN/api-reference/storage/index.rst +++ b/docs/zh_CN/api-reference/storage/index.rst @@ -10,6 +10,7 @@ mass_mfg.rst nvs_flash nvs_partition_gen.rst + nvs_partition_parse.rst sdmmc spi_flash spiffs diff --git a/docs/zh_CN/api-reference/storage/nvs_flash.rst b/docs/zh_CN/api-reference/storage/nvs_flash.rst index 2e2756897c..25f19a1c2b 100644 --- a/docs/zh_CN/api-reference/storage/nvs_flash.rst +++ b/docs/zh_CN/api-reference/storage/nvs_flash.rst @@ -46,7 +46,7 @@ NVS ç„æ“作对象为键值对，其中键是 ASCII 字符串，当å‰æ”¯æŒç„ 命å空间 ^^^^^^^^^^ -为了å‡å°‘ä¸åŒç»„件之间键åç„潜在冲çªï¼ŒNVS å°†æ¯ä¸ªé”®å€¼å¯¹åˆ†é…给一个命åç©ºé—´ă€‚å‘½å空间ç„命å规则éµå¾ªé”®åç„命å规则，例如，最å¤å¯å  15 ä¸ªå­—ç¬¦ă€‚å‘½å空间ç„å称在调用 :cpp:func:`nvs_open` 或 :cpp:type:`nvs_open_from_partition` 中指å®ï¼Œè°ƒç”¨å将返å›ä¸€ä¸ªä¸é€æ˜å¥æŸ„，用äºå续调用 ``nvs_get_*``ă€``nvs_set_*`` å’Œ ``nvs_commit`` å‡½æ•°ă€‚è¿™æ ·ï¼Œä¸€ä¸ªå¥æŸ„å…³è”一个命å空间，键å便ä¸ä¼ä¸å…¶ä»–命å空间中相åŒé”®å冲çªă€‚请注æ„，ä¸åŒ NVS 分区中具有相åŒå称ç„命å空间将被视为ä¸åŒç„命åç©ºé—´ă€‚ +为了å‡å°‘ä¸åŒç»„件之间键åç„潜在冲çªï¼ŒNVS å°†æ¯ä¸ªé”®å€¼å¯¹åˆ†é…给一个命åç©ºé—´ă€‚å‘½å空间ç„命å规则éµå¾ªé”®åç„命å规则，例如，最å¤å¯å  15 ä¸ªå­—ç¬¦ă€‚æ­¤å¤–ï¼Œå•ä¸ª NVS 分区最å¤åªèƒ½å®¹çº³ 254 个ä¸åŒç„命åç©ºé—´ă€‚å‘½å空间ç„å称在调用 :cpp:func:`nvs_open` 或 :cpp:type:`nvs_open_from_partition` 中指å®ï¼Œè°ƒç”¨å将返å›ä¸€ä¸ªä¸é€æ˜å¥æŸ„，用äºå续调用 ``nvs_get_*``ă€``nvs_set_*`` å’Œ ``nvs_commit`` å‡½æ•°ă€‚è¿™æ ·ï¼Œä¸€ä¸ªå¥æŸ„å…³è”一个命å空间，键å便ä¸ä¼ä¸å…¶ä»–命å空间中相åŒé”®å冲çªă€‚请注æ„，ä¸åŒ NVS 分区中具有相åŒå称ç„命å空间将被视为ä¸åŒç„命åç©ºé—´ă€‚ NVS 迭代器 ^^^^^^^^^^^^^ @@ -82,14 +82,14 @@ NVS 分区内存储ç„æ•°æ®å¯ä½¿ç”¨ AES-XTS 进行å å¯†ï¼Œç±»ä¼¼äº IEEE P161 å¯ç”¨ :doc:`Flash å å¯† <../../security/flash-encryption>` 时，默认å¯ç”¨ NVS å å¯†ă€‚这是因为 Wi-Fi 驱å¨åœ¨é»˜è®¤ç„ NVS 分区中存储了凭è¯ï¼ˆå¦‚ SSID 和密ç ï¼‰ă€‚如已å¯ç”¨å¹³å°çº§å å¯†ï¼Œé‚£ä¹ˆåŒæ—¶é»˜è®¤å¯ç”¨ NVS å å¯†æœ‰å…¶å¿…è¦æ€§ă€‚ -使用 NVS å å¯†ï¼Œåˆ†åŒºè¡¨å¿…é¡»åŒ…å« :ref:`nvs_key_partition`ă€‚åœ¨åˆ†åŒºè¡¨é€‰é¡¹ (menuconfig->Partition Table) 下，为 NVS å å¯†æä¾›äº†ä¸¤ä¸ªåŒ…å« :ref:`nvs_key_partition` ç„分区表，您å¯ä»¥é€è¿‡å·¥ç¨‹é…ç½®èœå• (``idf.py menuconfig``) è¿›è¡Œé€‰æ‹©ă€‚è¯·å‚考 :example:`security/flash_encryption` 中ç„例å­ï¼Œäº†è§£å¦‚何é…置和使用 NVS å å¯†åŸèƒ½ă€‚ +使用 NVS å å¯†ï¼Œåˆ†åŒºè¡¨å¿…é¡»åŒ…å« :ref:`nvs_key_partition`ă€‚åœ¨åˆ†åŒºè¡¨é€‰é¡¹ (``menuconfig`` > ``Partition Table``) 下，为 NVS å å¯†æä¾›äº†ä¸¤ä¸ªåŒ…å« :ref:`nvs_key_partition` ç„分区表，您å¯ä»¥é€è¿‡å·¥ç¨‹é…ç½®èœå• (``idf.py menuconfig``) è¿›è¡Œé€‰æ‹©ă€‚è¯·å‚考 :example:`security/flash_encryption` 中ç„例å­ï¼Œäº†è§£å¦‚何é…置和使用 NVS å å¯†åŸèƒ½ă€‚ .. _nvs_key_partition: NVS 密钥分区 ^^^^^^^^^^^^^^^^^ - 应用程åºå¦‚æœæƒ³ä½¿ç”¨ NVS å å¯†ï¼Œåˆ™éœ€è¦ç¼–译进一个类å‹ä¸º `data`，å­ç±»å‹ä¸º `key` ç„å¯†é’¥åˆ†åŒºă€‚è¯¥åˆ†åŒºåº”æ ‡è®°ä¸º `å·²å å¯†` 且最å°ä¸º 4096 å­—è‚ă€‚å¦‚éœ€äº†è§£æ›´å¤è¯¦ç»†ä¿¡æ¯ï¼Œè¯·å‚考 :doc:`分区表 <../../api-guides/partition-tables>`ă€‚åœ¨åˆ†åŒºè¡¨é€‰é¡¹ (menuconfig->Partition Table) 下æä¾›äº†ä¸¤ä¸ªåŒ…å« :ref:`nvs_key_partition` ç„é¢å¤–分区表，å¯ä»¥ç›´æ¥ç”¨äº :ref:`nvs_encryption`ă€‚è¿™äº›åˆ†åŒºç„具体结æ„è§ä¸‹è¡¨ï¼ +应用程åºå¦‚æœæƒ³ä½¿ç”¨ NVS å å¯†ï¼Œåˆ™éœ€è¦ç¼–译进一个类å‹ä¸º `data`，å­ç±»å‹ä¸º `key` ç„å¯†é’¥åˆ†åŒºă€‚è¯¥åˆ†åŒºåº”æ ‡è®°ä¸º `å·²å å¯†` 且最å°ä¸º 4096 å­—è‚ă€‚å¦‚éœ€äº†è§£æ›´å¤è¯¦ç»†ä¿¡æ¯ï¼Œè¯·å‚考 :doc:`分区表 <../../api-guides/partition-tables>`ă€‚åœ¨åˆ†åŒºè¡¨é€‰é¡¹ (``menuconfig`` > ``Partition Table``) 下æä¾›äº†ä¸¤ä¸ªåŒ…å« :ref:`nvs_key_partition` ç„é¢å¤–分区表，å¯ä»¥ç›´æ¥ç”¨äº :ref:`nvs_encryption`ă€‚è¿™äº›åˆ†åŒºç„具体结æ„è§ä¸‹è¡¨ï¼ .. highlight:: none diff --git a/docs/zh_CN/api-reference/storage/nvs_partition_parse.rst b/docs/zh_CN/api-reference/storage/nvs_partition_parse.rst new file mode 100644 index 0000000000..fb4477b66a --- /dev/null +++ b/docs/zh_CN/api-reference/storage/nvs_partition_parse.rst @@ -0,0 +1 @@ +.. include:: /../../components/nvs_flash/nvs_partition_parser/README_CN.rst diff --git a/docs/zh_CN/api-reference/storage/spi_flash.rst b/docs/zh_CN/api-reference/storage/spi_flash.rst index 02baed68dd..f3ef3d5e4e 100644 --- a/docs/zh_CN/api-reference/storage/spi_flash.rst +++ b/docs/zh_CN/api-reference/storage/spi_flash.rst @@ -153,7 +153,7 @@ SPI Flash å å¯† 内存映射 API ------------------ -{IDF_TARGET_CACHE_SIZE:default="64 KB"} +{IDF_TARGET_CACHE_SIZE:default="64 KB",esp32c2=16~64 KB} {IDF_TARGET_NAME} ç„内存硬件å¯ä»¥å°† flash 部分区域映射到指令地å€ç©ºé—´å’Œæ•°æ®åœ°å€ç©ºé—´ă€‚此映射仅用äºè¯»æ“作，ä¸èƒ½é€è¿‡å†™å…¥ flash 映射ç„存储区域æ¥æ”¹å˜ flash 中ç„å†…å®¹ă€‚ @@ -286,4 +286,4 @@ SPI Flash API å‚考 Flash å å¯† API å‚考 ----------------------------- -.. include-build-file:: inc/esp_flash_encrypt.inc \ No newline at end of file +.. include-build-file:: inc/esp_flash_encrypt.inc diff --git a/docs/zh_CN/api-reference/storage/spiffs.rst b/docs/zh_CN/api-reference/storage/spiffs.rst index 913891eb43..5d863b7dcc 100644 --- a/docs/zh_CN/api-reference/storage/spiffs.rst +++ b/docs/zh_CN/api-reference/storage/spiffs.rst @@ -17,7 +17,7 @@ SPIFFS æ˜¯ä¸€ä¸ªç”¨äº SPI NOR flash 设备ç„嵌入å¼æ–‡ä»¶ç³»ç»Ÿï¼Œæ”¯æŒç£¨ - SPIFFS åªèƒ½ç¨³å®åœ°ä½¿ç”¨çº¦ 75% ç„指å®åˆ†åŒºå®¹é‡ă€‚ - 当文件系统空间ä¸è¶³æ—¶ï¼Œåƒåœ¾æ”¶é›†å™¨ä¼å°è¯•å¤æ¬¡æ‰«æ文件系统æ¥å¯»æ‰¾å¯ç”¨ç©ºé—´ă€‚æ ¹æ®æ‰€éœ€ç©ºé—´ç„ä¸åŒï¼Œå†™æ“作ä¼è¢«è°ƒç”¨å¤æ¬¡ï¼Œæ¯æ¬¡å‡½æ•°è°ƒç”¨å°†è±è´¹å‡ ç§’。åŒä¸€æ“作å¯èƒ½ä¼è±è´¹ä¸åŒæ—¶é•¿ç„é—®é¢˜ç¼˜äº SPIFFS ç„è®¾è®¡ï¼Œä¸”å·²åœ¨å®˜æ–¹ç„ `SPIFFS github 仓库 `_ 或是 `_ 中被å¤æ¬¡æ¥å‘ă€‚è¿™ä¸ªé—®é¢˜å¯ä»¥é€è¿‡ `SPIFFS é…ç½® `_ éƒ¨åˆ†ç¼“è§£ă€‚ - 被删除文件é€å¸¸ä¸ä¼è¢«å®Œå…¨æ¸…除，ä¼åœ¨æ–‡ä»¶ç³»ç»Ÿä¸­é—留下无法使用ç„éƒ¨åˆ†ă€‚ - - å¦‚æœ ESP32 在文件系统æ“作期间断电，å¯èƒ½ä¼å¯¼è‡´ SPIFFS æŸåă€‚ä½†æ˜¯ä»å¯é€è¿‡ ``esp_spiffs_check`` 函数æ¢å¤æ–‡ä»¶ç³»ç»Ÿă€‚详情请å‚阅官方 SPIFFS `FAQ `。 + - å¦‚æœ {IDF_TARGET_NAME} 在文件系统æ“作期间断电，å¯èƒ½ä¼å¯¼è‡´ SPIFFS æŸåă€‚ä½†æ˜¯ä»å¯é€è¿‡ ``esp_spiffs_check`` 函数æ¢å¤æ–‡ä»¶ç³»ç»Ÿă€‚详情请å‚阅官方 SPIFFS `FAQ `。 工具 ----- diff --git a/docs/zh_CN/api-reference/system/inc/power_management_esp32s2_and_later.rst b/docs/zh_CN/api-reference/system/inc/power_management_esp32s2_and_later.rst index 4054209783..7d77823835 100644 --- a/docs/zh_CN/api-reference/system/inc/power_management_esp32s2_and_later.rst +++ b/docs/zh_CN/api-reference/system/inc/power_management_esp32s2_and_later.rst @@ -1,27 +1,29 @@ +{IDF_TARGET_APB_FREQ: default="80 Mhz", esp32c2="40 MHz"} + +---------------+---------------------------------------+-------------------------------------+ | CPU æœ€é«˜é¢‘ç‡ | 电æºç®¡ç†é”è·å–情况 | APB 频ç‡å’Œ CPU é¢‘ç‡ | | | | | +---------------+---------------------------------------+-------------------------------------+ | 240 | è·å– ``ESP_PM_CPU_FREQ_MAX`` | | CPU: 240 MHz | -| | | | APB: 80 MHz | +| | | | APB: {IDF_TARGET_APB_FREQ} | + +---------------------------------------+-------------------------------------+ | | | è·å– ``ESP_PM_APB_FREQ_MAX``, | | CPU: 80 MHz | -| | | 未è·å¾— ``ESP_PM_CPU_FREQ_MAX`` | | APB: 80 MHz | +| | | 未è·å¾— ``ESP_PM_CPU_FREQ_MAX`` | | APB: {IDF_TARGET_APB_FREQ} | + +---------------------------------------+-------------------------------------+ | | æ—  | 使用 :cpp:func:`esp_pm_configure` | | | | 为二者设置最å°å€¼ | +---------------+---------------------------------------+-------------------------------------+ | 160 | è·å– ``ESP_PM_CPU_FREQ_MAX`` | | CPU: 160 MHz | -| | | | APB: 80 MHz | +| | | | APB: {IDF_TARGET_APB_FREQ} | + +---------------------------------------+-------------------------------------+ | | | è·å– ``ESP_PM_APB_FREQ_MAX``, | | CPU: 80 MHz | -| | | 未è·å¾— ``ESP_PM_CPU_FREQ_MAX`` | | APB: 80 MHz | +| | | 未è·å¾— ``ESP_PM_CPU_FREQ_MAX`` | | APB: {IDF_TARGET_APB_FREQ} | + +---------------------------------------+-------------------------------------+ | | æ—  | 使用 :cpp:func:`esp_pm_configure` | | | | 为二者设置最å°å€¼ | +---------------+---------------------------------------+-------------------------------------+ | 80 | | è·å– ``ESP_PM_CPU_FREQ_MAX`` | | CPU: 80 MHz | -| | | 或 ``ESP_PM_APB_FREQ_MAX`` | | APB: 80 MHz | +| | | 或 ``ESP_PM_APB_FREQ_MAX`` | | APB: {IDF_TARGET_APB_FREQ} | + +---------------------------------------+-------------------------------------+ | | æ—  | 使用 :cpp:func:`esp_pm_configure` | | | | 为二者设置最å°å€¼ | diff --git a/docs/zh_CN/api-reference/system/misc_system_api.rst b/docs/zh_CN/api-reference/system/misc_system_api.rst index 736025bab3..223f29e32b 100644 --- a/docs/zh_CN/api-reference/system/misc_system_api.rst +++ b/docs/zh_CN/api-reference/system/misc_system_api.rst @@ -211,7 +211,7 @@ SDK 版本 若需手å¨è®¾ç½®ç‰ˆæœ¬ï¼Œéœ€è¦åœ¨é¡¹ç›®ç„ ``CMakeLists.txt`` 文件中设置 ``PROJECT_VER`` å˜é‡ï¼Œå³åœ¨ ``CMakeLists.txt`` æ–‡ä»¶ä¸­ï¼Œåœ¨åŒ…å« ``project.cmake`` 之å‰æ·»å  ``set(PROJECT_VER "0.1.0.1")``。 -如æœè®¾ç½®äº† :ref:`CONFIG_APP_PROJECT_VER_FROM_CONFIG` 选项，则将使用 :ref:`CONFIG_APP_PROJECT_VER` ç„å€¼ă€‚å¦åˆ™ï¼Œå¦‚æœåœ¨é¡¹ç›®ä¸­æœªè®¾ç½® ``PROJECT_VER`` å˜é‡ï¼Œåˆ™è¯¥å˜é‡å°†ä» ``$(PROJECT_PATH)/version.txt`` 文件（若有）中检索，或使用 git 命令 ``git describe`` æ£€ç´¢ă€‚å¦‚æœä¸¤è€…都ä¸å¯ç”¨ï¼Œåˆ™ ``PROJECT_VER`` 将被设置为 “1â€ă€‚应用程åºå¯é€è¿‡è°ƒç”¨ :cpp:func:`esp_ota_get_app_description` 或 :cpp:func:`esp_ota_get_partition_description` 函数æ¥è·å–应用程åºç„版本信æ¯ă€‚ +如æœè®¾ç½®äº† :ref:`CONFIG_APP_PROJECT_VER_FROM_CONFIG` 选项，则将使用 :ref:`CONFIG_APP_PROJECT_VER` ç„å€¼ă€‚å¦åˆ™ï¼Œå¦‚æœåœ¨é¡¹ç›®ä¸­æœªè®¾ç½® ``PROJECT_VER`` å˜é‡ï¼Œåˆ™è¯¥å˜é‡å°†ä» ``$(PROJECT_PATH)/version.txt`` 文件（若有）中检索，或使用 git 命令 ``git describe`` æ£€ç´¢ă€‚å¦‚æœä¸¤è€…都ä¸å¯ç”¨ï¼Œåˆ™ ``PROJECT_VER`` 将被设置为 “1â€ă€‚应用程åºå¯é€è¿‡è°ƒç”¨ :cpp:func:`esp_app_get_description` 或 :cpp:func:`esp_ota_get_partition_description` 函数æ¥è·å–应用程åºç„版本信æ¯ă€‚ API å‚考 ------------- @@ -221,3 +221,4 @@ API å‚考 .. include-build-file:: inc/esp_mac.inc .. include-build-file:: inc/esp_chip_info.inc .. include-build-file:: inc/esp_cpu.inc +.. include-build-file:: inc/esp_app_desc.inc diff --git a/docs/zh_CN/api-reference/system/sleep_modes.rst b/docs/zh_CN/api-reference/system/sleep_modes.rst index f8b679a543..f25f316517 100644 --- a/docs/zh_CN/api-reference/system/sleep_modes.rst +++ b/docs/zh_CN/api-reference/system/sleep_modes.rst @@ -16,9 +16,8 @@ .. list:: - RTC æ§åˆ¶å™¨ - - RTC 外设 :SOC_ULP_SUPPORTED: - ULP å处ç†å™¨ - - RTC 高速内存 + :SOC_RTC_FAST_MEM_SUPPORTED: - RTC 高速内存 :SOC_RTC_SLOW_MEM_SUPPORTED: - RTC ä½é€Ÿå†…å­˜ Light-sleep å’Œ Deep-sleep 模å¼æœ‰å¤ç§å”¤é†’æºă€‚这些唤醒æºä¹Ÿå¯ä»¥ç»„åˆåœ¨ä¸€èµ·ï¼Œæ­¤æ—¶ä»»ä½•ä¸€ä¸ªå”¤é†’æºéƒ½å¯ä»¥è§¦å‘å”¤é†’ă€‚é€è¿‡ API ``esp_sleep_enable_X_wakeup`` å¯å¯ç”¨å”¤é†’æºï¼Œé€è¿‡ API :cpp:func:`esp_sleep_disable_wakeup_source` å¯ç¦ç”¨å”¤é†’æºï¼Œè¯¦è§ä¸‹ä¸€å°è‚ă€‚åœ¨ç³»ç»Ÿè¿›å…¥ Light-sleep 或 Deep-sleep 模å¼å‰ï¼Œå¯ä»¥åœ¨ä»»æ„时刻é…置唤醒æºă€‚ @@ -164,14 +163,16 @@ RTC 外设和内存断电 如æœç¨‹åºä¸­ç„æŸäº›å€¼è¢«æ”¾å…¥ RTC ä½é€Ÿå†…存中（例如使用 ``RTC_DATA_ATTR`` å±æ€§ï¼‰ï¼ŒRTC ä½é€Ÿå†…存将默认ä¿æŒä¾›ç”µă€‚如æœæœ‰éœ€è¦ï¼Œä¹Ÿå¯ä»¥ä½¿ç”¨å‡½æ•° :cpp:func:`esp_sleep_pd_config` å¯¹å…¶è¿›è¡Œä¿®æ”¹ă€‚ -.. only:: not SOC_RTC_SLOW_MEM_SUPPORTED +.. only:: not SOC_RTC_SLOW_MEM_SUPPORTED and SOC_RTC_FAST_MEM_SUPPORTED {IDF_TARGET_NAME} 中åªæœ‰ RTC 高速内存，因此，如æœç¨‹åºä¸­ç„æŸäº›å€¼è¢«æ ‡è®°ä¸º ``RTC_DATA_ATTR``ă€``RTC_SLOW_ATTR`` 或 ``RTC_FAST_ATTR`` å±æ€§ï¼Œé‚£ä¹ˆæ‰€æœ‰è¿™äº›å€¼éƒ½å°†è¢«å­˜å…¥ RTC 高速内存，默认情况下ä¿æŒä¾›ç”µă€‚如æœæœ‰éœ€è¦ï¼Œæ‚¨ä¹Ÿå¯ä»¥ä½¿ç”¨å‡½æ•° :cpp:func:`esp_sleep_pd_config` å¯¹å…¶è¿›è¡Œä¿®æ”¹ă€‚ Flash 断电 ---------- -默认情况下，调用函数 :cpp:func:`esp_light_sleep_start` å， **ä¸ä¼** 断电 flashă€‚åœ¨ sleep 过程中断电 flash 存在é£é™©ă€‚因为 flash 断电需è¦æ—¶é—´ï¼Œä½†æ˜¯åœ¨æ­¤æœŸé—´ï¼Œç³»ç»Ÿæœ‰å¯èƒ½è¢«å”¤é†’ă€‚æ­¤æ—¶ flash é‡æ–°è¢«ä¸ç”µï¼Œæ–­ç”µå°æœªå®Œæˆåˆé‡æ–°ä¸ç”µç„硬件行为有概ç‡å¯¼è‡´ flash ä¸èƒ½æ­£å¸¸å·¥ä½œă€‚如æœç”¨æˆ·ä¸º flash 供电电路添å äº†æ»¤æ³¢ç”µå®¹ï¼Œæ–­ç”µæ‰€éœ€æ—¶é—´å¯èƒ½ä¼æ›´é•¿ă€‚此外，å³ä½¿å¯ä»¥é¢„知 flash 彻底断电所需ç„时间，有时也ä¸èƒ½é€è¿‡è®¾ç½®è¶³å¤Ÿé•¿ç„ç¡çœ æ—¶é—´æ¥ç¡®ä¿ flash 断电ç„安全（比如，çªå‘ç„异步唤醒æºä¼ä½¿å¾—å®é™…ç„ç¡çœ æ—¶é—´ä¸å¯æ§ï¼‰ă€‚ +默认情况下，调用函数 :cpp:func:`esp_light_sleep_start` å， flash **ä¸ä¼** 断电，因为在 sleep 过程中断电 flash 存在é£é™©ă€‚具体而言，flash 断电需è¦æ—¶é—´ï¼Œä½†æ˜¯åœ¨æ­¤æœŸé—´ï¼Œç³»ç»Ÿæœ‰å¯èƒ½è¢«å”¤é†’，导致 flash é‡æ–°è¢«ä¸ç”µă€‚此时，断电å°æœªå®Œæˆåˆé‡æ–°ä¸ç”µç„硬件行为有å¯èƒ½å¯¼è‡´ flash æ— æ³•æ­£å¸¸å·¥ä½œă€‚ + +ç†è®ºä¸è®²ï¼Œåœ¨ flash 完全断电åå¯ä»¥ä»…唤醒系统，然而ç°å®æƒ…况是 flash 断电所需ç„时间很é¾é¢„æµ‹ă€‚å¦‚æœç”¨æˆ·ä¸º flash 供电电路添å äº†æ»¤æ³¢ç”µå®¹ï¼Œæ–­ç”µæ‰€éœ€æ—¶é—´å¯èƒ½ä¼æ›´é•¿ă€‚此外，å³ä½¿å¯ä»¥é¢„知 flash 彻底断电所需ç„时间，有时也ä¸èƒ½é€è¿‡è®¾ç½®è¶³å¤Ÿé•¿ç„ç¡çœ æ—¶é—´æ¥ç¡®ä¿ flash 断电ç„安全（比如，çªå‘ç„异步唤醒æºä¼ä½¿å¾—å®é™…ç„ç¡çœ æ—¶é—´ä¸å¯æ§ï¼‰ă€‚ .. warning:: 如æœåœ¨ flash ç„供电电路ä¸æ·»å äº†æ»¤æ³¢ç”µå®¹ï¼Œé‚£ä¹ˆåº”当尽一切å¯èƒ½é¿å… flash æ–­ç”µă€‚ @@ -193,7 +194,7 @@ Flash 断电 .. list:: - - Light sleep 时，ESP-IDF 并未æä¾›ä¿è¯ flash 一å®ä¼è¢«æ–­ç”µç„æœºåˆ¶ă€‚ + - Light sleep 时，ESP-IDF 没有æä¾›ä¿è¯ flash 一å®ä¼è¢«æ–­ç”µç„æœºåˆ¶ă€‚ - ä¸ç®¡ç”¨æˆ·ç„é…置如何，函数 :cpp:func:`esp_deep_sleep_start` 都ä¼å¼ºåˆ¶æ–­ç”µ flash。 进入 Light-sleep æ¨¡å¼ @@ -211,7 +212,7 @@ Flash 断电 一些 {IDF_TARGET_NAME} IO 在默认情况下å¯ç”¨å†…部ä¸æ‹‰æˆ–ä¸‹æ‹‰ç”µé˜»ă€‚å¦‚æœè¿™äº›ç®¡è„在 Deep-sleep 模å¼ä¸‹ä¸­å—外部电路驱å¨ï¼Œç”µæµæµç»è¿™äº›ä¸ä¸‹æ‹‰ç”µé˜»æ—¶ï¼Œå¯èƒ½ä¼å¢å ç”µæµæ¶ˆè€—。 -.. only:: not esp32c3 +.. only:: SOC_RTCIO_HOLD_SUPPORTED 想è¦é”离这些管è„以é¿å…é¢å¤–ç„电æµæ¶ˆè€—，请调用 :cpp:func:`rtc_gpio_isolate` å‡½æ•°ă€‚ @@ -221,7 +222,7 @@ Flash 断电 rtc_gpio_isolate(GPIO_NUM_12); -.. only:: esp32c3 +.. only:: esp32c2 or esp32c3 在 Deep-sleep 模å¼ä¸­ï¼ - æ•°å­— GPIO (GPIO6 ~ 21) 处äºé«˜é˜»æ€ă€‚ @@ -265,7 +266,7 @@ UART è¾“å‡ºå¤„ç† - :example:`system/deep_sleep`ï¼å¦‚何使用 Deep-sleep 唤醒触å‘器和 ULP å处ç†å™¨ç¼–程。 -.. only:: esp32c3 +.. only:: esp32c3 or esp32c2 - :example:`system/deep_sleep`ï¼å¦‚何é€è¿‡å®æ—¶å™¨è§¦å‘ Deep-sleep å”¤é†’ă€‚ diff --git a/docs/zh_CN/api-reference/system/ulp-risc-v.rst b/docs/zh_CN/api-reference/system/ulp-risc-v.rst index f3c2d2c09b..da720f2b84 100644 --- a/docs/zh_CN/api-reference/system/ulp-risc-v.rst +++ b/docs/zh_CN/api-reference/system/ulp-risc-v.rst @@ -11,7 +11,7 @@ ULP RISC-V å处ç†å™¨ä»£ç ä»¥ C 语言（或汇编语言）编写，使用基 如æœæ‚¨å·²ä¾ç…§ :doc:`å¿«é€Ÿå…¥é—¨æŒ‡å— <../../../get-started/index>` 中ç„介ç»å®‰è£…好了 ESP-IDF åå…¶ CMake æ„建系统，那么 ULP RISC-V 工具链已ç»è¢«é»˜è®¤å®‰è£…到了您ç„å¼€å‘ç¯å¢ƒä¸­ă€‚ -.. note: 在早期版本ç„ESP-IDF中，RISC-V工具链具有ä¸åŒç„å称ï¼`riscv-none-embed-gcc`。 +.. note: åœ¨æ—©æœŸç‰ˆæœ¬ç„ ESP-IDF 中，RISC-V 工具链具有ä¸åŒç„å称ï¼`riscv-none-embed-gcc`。 编译 ULP RISC-V ä»£ç  ----------------------------- @@ -51,18 +51,20 @@ ULP RISC-V å处ç†å™¨ä»£ç ä»¥ C 语言（或汇编语言）编写，使用基 6. **创建 LD 导出è„本和头文件** （``ulp_app_name.ld`` å’Œ ``ulp_app_name.h``），包å«æ¥è‡ª ``ulp_app_name.sym`` ç„符å·ă€‚此步骤å¯å€Ÿå© ``esp32ulp_mapgen.py`` 工具æ¥å®Œæˆă€‚ - 7. **将生æˆç„二进制文件添å åˆ°è¦åµŒå…¥åº”用程åºç„äºŒè¿›åˆ¶æ–‡ä»¶åˆ—è¡¨ä¸­ă€‚** + 7. **将生æˆç„二进制文件添å åˆ°è¦åµŒå…¥åº”用程åºç„äºŒè¿›åˆ¶æ–‡ä»¶åˆ—è¡¨ä¸­ă€‚** + +.. _ulp-riscv-access-variables: 访问 ULP RISC-V 程åºå˜é‡ ---------------------------- -在 ULP RISC-V 程åºä¸­å®ä¹‰ç„全局符å·ä¹Ÿå¯ä»¥åœ¨ä¸»ç¨‹åºä¸­ä½¿ç”¨ă€‚ +在 ULP RISC-V 程åºä¸­å®ä¹‰ç„全局符å·ä¹Ÿå¯ä»¥åœ¨ä¸»ç¨‹åºä¸­ä½¿ç”¨ă€‚ 例如，ULP RISC-V 程åºå¯ä»¥å®ä¹‰ ``measurement_count`` å˜é‡ï¼Œæ­¤å˜é‡å¯ä»¥å®ä¹‰ç¨‹åºä»æ·±åº¦ç¡çœ ä¸­å”¤é†’è¯ç‰‡ä¹‹å‰éœ€è¦è¿›è¡Œç„ ADC 测é‡ç„æ¬¡æ•°ă€‚ .. code-block:: c - volatile int measurement_count; + volatile int measurement_count; int some_function() { @@ -96,6 +98,18 @@ ULP RISC-V å处ç†å™¨ä»£ç ä»¥ C 语言（或汇编语言）编写，使用基 ulp_measurement_count = 64; } +互斥 +^^^^^^^ + +如æœæƒ³è¦äº’斥地访问被主程åºå’Œ ULP 程åºå…±äº«ç„å˜é‡ï¼Œåˆ™å¯ä»¥é€è¿‡ ULP RISC-V Lock API æ¥å®ç°ï¼ + + * :cpp:func:`ulp_riscv_lock_acquire` + * :cpp:func:`ulp_riscv_lock_release` + +ULP 中ç„所有硬件指令都ä¸æ”¯æŒäº’斥，所以 Lock API 需é€è¿‡ä¸€ç§è½¯ä»¶ç®—法（`Peterson 算法 `_ ）æ¥å®ç°äº’æ–¥ă€‚ + +注æ„，åªèƒ½ä»ä¸»ç¨‹åºç„å•ä¸ªçº¿ç¨‹ä¸­è°ƒç”¨è¿™äº›é”，如æœå¤ä¸ªçº¿ç¨‹åŒæ—¶è°ƒç”¨ï¼Œå°†æ— æ³•å¯ç”¨äº’æ–¥åŸèƒ½ă€‚ + å¯å¨ ULP RISC-V ç¨‹åº ------------------------------- @@ -136,13 +150,30 @@ ULP RISC-V å处ç†å™¨ç”±å®æ—¶å™¨å¯å¨ï¼Œè°ƒç”¨ :cpp:func:`ulp_riscv_run` å³ å¦‚éœ€ç¦ç”¨å®æ—¶å™¨ï¼ˆæœ‰æ•ˆé˜²æ­¢ ULP 程åºå†æ¬¡è¿è¡Œï¼‰ï¼Œè¯·æ¸…除 ``RTC_CNTL_STATE0_REG`` å¯„å­˜å™¨ä¸­ç„ ``RTC_CNTL_ULP_CP_SLP_TIMER_EN`` ä½ï¼Œæ­¤é¡¹æ“作å¯åœ¨ ULP 代ç æˆ–主程åºä¸­è¿›è¡Œă€‚ + +调试 ULP RISC-V ç¨‹åº +---------------------------------- + +在对 ULP RISC-V 进行编程时，若程åºæœªæŒ‰é¢„期è¿è¡Œï¼Œæœ‰æ—¶å¾ˆé¾æ‰¾å‡ºç„åŸå› ă€‚因为其内核ç„简å•æ€§ï¼Œè®¸å¤æ ‡å‡†ç„调试方法如 JTAG 或 ``printf`` æ— æ³•ä½¿ç”¨ă€‚ + +以下方法å¯ä»¥å¸®å©æ‚¨è°ƒè¯• ULP RISC-V 程åºï¼ + + * é€è¿‡å…±äº«å˜é‡æŸ¥çœ‹ç¨‹åºç¶æ€ï¼å¦‚ :ref:`ulp-riscv-access-variables` 中所述，主 CPU 以å ULP 内核都å¯ä»¥è½»æ¾è®¿é—® RTC 内存中ç„全局å˜é‡ă€‚é€è¿‡ ULP å‘该å˜é‡ä¸­å†™å…¥ç¶æ€ä¿¡æ¯ï¼Œç„¶åé€è¿‡ä¸» CPU 读å–ç¶æ€ä¿¡æ¯ï¼Œå¯å¸®å©æ‚¨äº†è§£ ULP 内核ç„ç¶æ€ă€‚该方法ç„缺点在äºå®ƒè¦æ±‚主 CPU 一直处äºå”¤é†’ç¶æ€ï¼Œä½†ç°å®æƒ…况å¯èƒ½å¹¶éå¦‚æ­¤ă€‚æœ‰æ—¶ï¼Œä¿æŒä¸» CPU 处äºå”¤é†’ç¶æ€è¿˜å¯èƒ½ä¼æ©ç›–一些问题，因为æŸäº›é—®é¢˜å¯èƒ½ä»…在特å®ç”µæºåŸŸæ–­ç”µæ—¶æ‰ä¼å‡ºç°ă€‚ + + * 使用 bit-banged UART 驱å¨ç¨‹åºæ‰“å°ï¼ULP RISC-V 组件中有一个ä½é€Ÿ bit-banged UART TX 驱å¨ç¨‹åºï¼Œå¯ç”¨äºæ‰“å°ç‹¬ç«‹äºä¸» CPU ç¶æ€ç„ä¿¡æ¯ă€‚有关如何使用此驱å¨ç¨‹åºç„示例，请å‚阅 :example:`system/ulp_riscv/uart_print`。 + + * 陷阱信å·ï¼ULP RISC-V 有一个硬件陷阱，将在特å®æ¡ä»¶ä¸‹è§¦å‘，例如éæ³•æŒ‡ä»¤ă€‚è¿™å°†å¯¼è‡´ä¸» CPU 被 :cpp:enumerator:`ESP_SLEEP_WAKEUP_COCPU_TRAP_TRIG` å”¤é†’ă€‚ + 应用示例 -------------------- * 主处ç†å™¨å¤„äº Deep-sleep ç¶æ€æ—¶ï¼ŒULP RISC-V å处ç†å™¨è½®è¯¢ GPIOï¼:example:`system/ulp_riscv/gpio`。 +* ULP RISC-V å处ç†å™¨ä½¿ç”¨ bit-banged UART 驱å¨ç¨‹åºæ‰“å°: :example:`system/ulp_riscv/uart_print`. * 主处ç†å™¨å¤„äº Deep-sleep ç¶æ€æ—¶ï¼ŒULP RISC-V å处ç†å™¨è¯»å–外部温度传感器ï¼:example:`system/ulp_riscv/ds18b20_onewire`。 API å‚考 ------------- .. include-build-file:: inc/ulp_riscv.inc +.. include-build-file:: inc/ulp_riscv_lock_shared.inc +.. include-build-file:: inc/ulp_riscv_lock.inc diff --git a/docs/zh_CN/api-reference/system/ulp.rst b/docs/zh_CN/api-reference/system/ulp.rst index 36ef43741f..66f6ce7a0d 100644 --- a/docs/zh_CN/api-reference/system/ulp.rst +++ b/docs/zh_CN/api-reference/system/ulp.rst @@ -184,4 +184,4 @@ API å‚考 .. include-build-file:: inc/ulp_common.inc .. include-build-file:: inc/ulp_common_defs.inc -.. _binutils-esp32ulp 工具链: https://github.com/espressif/binutils-esp32ulp +.. _binutils-esp32ulp 工具链: https://github.com/espressif/binutils-gdb diff --git a/docs/zh_CN/get-started/establish-serial-connection.rst b/docs/zh_CN/get-started/establish-serial-connection.rst index 57e1f9a93b..8095ba205d 100644 --- a/docs/zh_CN/get-started/establish-serial-connection.rst +++ b/docs/zh_CN/get-started/establish-serial-connection.rst @@ -243,12 +243,20 @@ macOS:: ç°åœ¨ï¼Œè¯·ä½¿ç”¨ä¸²å£ç»ˆç«¯ç¨‹åºï¼ŒæŸ¥çœ‹é‡ç½® {IDF_TARGET_NAME} å终端ä¸æ˜¯å¦æœ‰è¾“出，ä»è€ŒéªŒè¯ä¸²å£è¿æ¥æ˜¯å¦å¯ç”¨ă€‚ +.. only:: esp32c2 + + 使用 40 MHz ç„ XTAL 时，ESP32-C2 ç„æ§åˆ¶å°æ³¢ç‰¹ç‡é»˜è®¤ä¸º 115200；使用 26 MHz ç„ XTAL 时，其波特ç‡é»˜è®¤ä¸º 74880。 + +.. only:: not esp32c2 + + {IDF_TARGET_NAME} ç„æ§åˆ¶å°æ³¢ç‰¹ç‡é»˜è®¤ä¸º 115200。 + Windows å’Œ Linux æ“作系统 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -在本示例中，我们将使用 `PuTTY SSH Client `_， `PuTTY SSH Client `_ æ—¢å¯ç”¨äº Windows 也å¯ç”¨äº Linuxă€‚ä½ ä¹Ÿå¯ä»¥ä½¿ç”¨å…¶ä»–串å£ç¨‹åºå¹¶è®¾ç½®å¦‚下ç„é€ä¿¡å‚æ•°ă€‚ +在本示例中，我们将使用 `PuTTY SSH Client `_， `PuTTY SSH Client `_ æ—¢å¯ç”¨äº Windows 也å¯ç”¨äº Linuxă€‚æ‚¨ä¹Ÿå¯ä»¥ä½¿ç”¨å…¶ä»–串å£ç¨‹åºå¹¶è®¾ç½®å¦‚下ç„é€ä¿¡å‚æ•°ă€‚ -è¿è¡Œç»ˆç«¯ï¼Œé…置在ä¸è¿°æ­¥éª¤ä¸­ç¡®è®¤ç„串å£ï¼æ³¢ç‰¹ç‡ = 115200，数æ®ä½ = 8，åœæ­¢ä½ = 1，奇å¶æ ¡éªŒ = Nă€‚ä»¥ä¸‹æˆªå±åˆ†åˆ«å±•ç¤ºäº†å¦‚何在 Windows å’Œ Linux 中é…置串å£å’Œä¸è¿°é€ä¿¡å‚数（如 115200-8-1-Nï¼‰ă€‚æ³¨æ„，这里一å®è¦é€‰æ‹©åœ¨ä¸è¿°æ­¥éª¤ä¸­ç¡®è®¤ç„串å£è¿›è¡Œé…ç½®ă€‚ +è¿è¡Œç»ˆç«¯ï¼Œé…置在ä¸è¿°æ­¥éª¤ä¸­ç¡®è®¤ç„串å£ï¼æ³¢ç‰¹ç‡ = 115200（如有需è¦ï¼Œè¯·æ›´æ”¹ä¸ºä½¿ç”¨è¯ç‰‡ç„默认波特ç‡ï¼‰ï¼Œæ•°æ®ä½ = 8，åœæ­¢ä½ = 1，奇å¶æ ¡éªŒ = Nă€‚ä»¥ä¸‹æˆªå±åˆ†åˆ«å±•ç¤ºäº†å¦‚何在 Windows å’Œ Linux 中é…置串å£å’Œä¸è¿°é€ä¿¡å‚数（如 115200-8-1-Nï¼‰ă€‚æ³¨æ„，这里一å®è¦é€‰æ‹©åœ¨ä¸è¿°æ­¥éª¤ä¸­ç¡®è®¤ç„串å£è¿›è¡Œé…ç½®ă€‚ .. figure:: ../../_static/putty-settings-windows.png :align: center @@ -283,7 +291,7 @@ macOS æ供了 **å±å¹•** 命令，因此您ä¸ç”¨å®‰è£…串å£ç»ˆç«¯ç¨‹åºă€‚ /dev/cu.Bluetooth-Incoming-Port /dev/cu.SLAB_USBtoUART /dev/cu.SLAB_USBtoUART7 -- æ ¹æ®æ‚¨è¿æ¥åˆ°ç”µè„‘ä¸ç„å¼€å‘æ¿ç±»å‹å’Œæ•°é‡ï¼Œè¾“出结æœä¼æœ‰æ‰€ä¸åŒă€‚请选择开å‘æ¿ç„设备å称，并è¿è¡Œä»¥ä¸‹å‘½ä»¤:: +- æ ¹æ®æ‚¨è¿æ¥åˆ°ç”µè„‘ä¸ç„å¼€å‘æ¿ç±»å‹å’Œæ•°é‡ï¼Œè¾“出结æœä¼æœ‰æ‰€ä¸åŒă€‚请选择开å‘æ¿ç„设备å称，并è¿è¡Œä»¥ä¸‹å‘½ä»¤ï¼ˆå¦‚有需è¦ï¼Œè¯·å°†â€œ115200â€æ›´æ”¹ä¸ºä½¿ç”¨è¯ç‰‡ç„默认波特ç‡ï¼‰:: screen /dev/cu.device_name 115200 diff --git a/docs/zh_CN/get-started/index.rst b/docs/zh_CN/get-started/index.rst index 9fc5370ad3..e58adb2fd1 100644 --- a/docs/zh_CN/get-started/index.rst +++ b/docs/zh_CN/get-started/index.rst @@ -97,7 +97,7 @@ :maxdepth: 1 ESP32-S2-Saola-1 <../hw-reference/esp32s2/user-guide-saola-1-v1.2> - ESP32-S2-DevKitM-1(U) <../hw-reference/esp32s2/user-guide-devkitm-1-v1> + ESP32-S2-DevKitM-1 <../hw-reference/esp32s2/user-guide-devkitm-1-v1> ESP32-S2-DevKitC-1 <../hw-reference/esp32s2/user-guide-s2-devkitc-1> ESP32-S2-Kaluga-Kit <../hw-reference/esp32s2/user-guide-esp32-s2-kaluga-1-kit> diff --git a/docs/zh_CN/get-started/linux-macos-setup.rst b/docs/zh_CN/get-started/linux-macos-setup.rst index f5f73b92d7..f724de92df 100644 --- a/docs/zh_CN/get-started/linux-macos-setup.rst +++ b/docs/zh_CN/get-started/linux-macos-setup.rst @@ -154,7 +154,7 @@ ESP-IDF 将下载至 ``~/esp/esp-idf``。 cd ~/esp/esp-idf ./install.fish {IDF_TARGET_PATH_NAME} -ä¸è¿°å‘½ä»¤ä»…仅为 {IDF_TARGET_NAME} å®‰è£…æ‰€éœ€å·¥å…·ă€‚å¦‚æœéœ€è¦ä¸ºå¤ä¸ªç›®æ ‡è¯ç‰‡å¼€å‘项目，则å¯ä»¥ä¸€æ¬¡æ€§æŒ‡å®å¤ä¸ªç›®æ ‡ï¼Œå¦‚下所示:: +ä¸è¿°å‘½ä»¤ä»…仅为 {IDF_TARGET_NAME} å®‰è£…æ‰€éœ€å·¥å…·ă€‚å¦‚æœéœ€è¦ä¸ºå¤ä¸ªç›®æ ‡è¯ç‰‡å¼€å‘项目，则å¯ä»¥ä¸€æ¬¡æ€§æŒ‡å®å¤ä¸ªç›®æ ‡ï¼Œå¦‚ä¸‹æ‰€ç¤ºï¼ .. code-block:: bash @@ -189,7 +189,6 @@ ESP-IDF 将下载至 ``~/esp/esp-idf``。 å¯è¿è¡Œæ‚¨ç”µè„‘ Python æ–‡ä»¶å¤¹ä¸­ç„ ``Install Certificates.command`` 安装è¯ä¹¦ă€‚了解更å¤ä¿¡æ¯ï¼Œè¯·å‚考 `安装 ESP-IDF 工具时出ç°ç„下载错误 `_。 - 下载工具备选方案 ~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/zh_CN/get-started/start-project.rst b/docs/zh_CN/get-started/start-project.rst index 751cba1078..9e5800b277 100644 --- a/docs/zh_CN/get-started/start-project.rst +++ b/docs/zh_CN/get-started/start-project.rst @@ -381,31 +381,31 @@ ESP-IDF æ”¯æŒ Python 3.7 å以ä¸ç‰ˆæœ¬ï¼Œå»ºè®®å‡çº§æ“作系统到最新版 一般æ¥è¯´ï¼ŒBSP 支æŒå¼€å‘æ¿ä¸æ‰€æœ‰ç¡¬ä»¶ç»„ä»¶ă€‚é™¤äº†ç®¡è„å®ä¹‰å’Œåˆå§‹åŒ–åŸèƒ½å¤–，BSP 还附带如传感器ă€æ˜¾ç¤ºå™¨ă€éŸ³é¢‘编解ç å™¨ç­‰å¤–部元件ç„驱å¨ç¨‹åºă€‚ - BSP é€è¿‡ `IDF 组件管ç†å™¨ <../api-guides/tools/idf-component-manager>`_ å‘布，您å¯ä»¥å‰å¾€ `IDF 组件注册器 `_ è¿›è¡Œä¸‹è½½ă€‚ + BSP é€è¿‡ :doc:`IDF 组件管ç†å™¨ ` å‘布，您å¯ä»¥å‰å¾€ `IDF 组件注册器 `_ è¿›è¡Œä¸‹è½½ă€‚ .. only:: esp32 **以下示例演示了如何将 ESP-WROVER-KIT BSP æ·»å åˆ°é¡¹ç›®ä¸­ï¼** - + .. code-block:: bash - - idf.py add-dependency esp_wrover_kit + + idf.py add-dependency esp_wrover_kit .. only:: esp32s2 **以下示例演示了如何将 ESP32-S2-Kaluga-Kit BSP æ·»å åˆ°é¡¹ç›®ä¸­ï¼** - + .. code-block:: bash - + idf.py add-dependency esp32_s2_kaluga_kit .. only:: esp32s3 **以下示例演示了如何将 ESP-BOX BSP æ·»å åˆ°é¡¹ç›®ä¸­ï¼** - + .. code-block:: bash - - idf.py add-dependency esp-box + + idf.py add-dependency esp-box æ›´å¤æœ‰å…³ä½¿ç”¨ BSP ç„示例，请å‰å¾€ `BSP 示例文件夹 `_。 diff --git a/docs/zh_CN/hw-reference/chip-series-comparison.rst b/docs/zh_CN/hw-reference/chip-series-comparison.rst deleted file mode 100644 index baaa9012dd..0000000000 --- a/docs/zh_CN/hw-reference/chip-series-comparison.rst +++ /dev/null @@ -1,302 +0,0 @@ -*********************** -è¯ç‰‡ç³»åˆ—对比 -*********************** - -:link_to_translation:`en: [English]` - -下表对比了 ESP-IDF å„系列è¯ç‰‡ç„主è¦ç‰¹æ€§ï¼Œå¦‚需了解更å¤ä¿¡æ¯ï¼Œè¯·å‚考 `相关文档`_ 中å„系列è¯ç‰‡ç„æ€æœ¯è§„æ ¼ä¹¦ă€‚ - -.. list-table:: è¯ç‰‡ç³»åˆ—对比 - :widths: 20 40 40 40 40 - :header-rows: 1 - - * - 特性 - - ESP32 系列 - - ESP32-S2 系列 - - ESP32-C3 系列 - - ESP32-S3 系列 - * - å‘布时间 - - 2016 - - 2020 - - 2020 - - 2020 - * - 产å“å‹å· - - 请å‚考 `ESP32 æ€æœ¯è§„格书 (PDF) `_ - - 请å‚考 `ESP32-S2 æ€æœ¯è§„格书 (PDF) `_ - - 请å‚考 `ESP32-C3 æ€æœ¯è§„格书 (PDF) `_ - - 请å‚考 `ESP32-S3 æ€æœ¯è§„格书 (PDF) `_ - * - 内核 - - æ­è½½ä½åŸè€— Xtensa® LX6 32 ä½åŒæ ¸/å•æ ¸å¤„ç†å™¨ - - æ­è½½ä½åŸè€— Xtensa® LX7 32 ä½å•æ ¸å¤„ç†å™¨ - - æ­è½½ RISC-V 32 ä½å•æ ¸å¤„ç†å™¨ - - æ­è½½ä½åŸè€— Xtensa® LX7 32 ä½åŒæ ¸å¤„ç†å™¨ - * - Wi-Fi åè®® - - 802.11 b/g/nă€2.4 GHz - - 802.11 b/g/nă€2.4 GHz - - 802.11 b/g/nă€2.4 GHz - - 802.11 b/g/nă€2.4 GHz - * - Bluetooth® - - Bluetooth v4.2 BR/EDR å’Œ Bluetooth Low Energy - - âœ–ï¸ - - Bluetooth 5.0 - - Bluetooth 5.0 - * - 主频 - - 240 MHz（ESP32-S0WD 为 160 MHz） - - 240 MHz - - 160 MHz - - 240 MHz - * - SRAM - - 520 KB - - 320 KB - - 400 KB - - 512 KB - * - ROM - - 448 KB 用äºç¨‹åºå¯å¨å’Œå†…æ ¸åŸèƒ½è°ƒç”¨ - - 128 KB 用äºç¨‹åºå¯å¨å’Œå†…æ ¸åŸèƒ½è°ƒç”¨ - - 384 KB 用äºç¨‹åºå¯å¨å’Œå†…æ ¸åŸèƒ½è°ƒç”¨ - - 384 KB 用äºç¨‹åºå¯å¨å’Œå†…æ ¸åŸèƒ½è°ƒç”¨ - * - åµŒå…¥å¼ flash - - 2 MBă€4 MB æˆ–æ— åµŒå…¥å¼ flash，ä¸åŒå‹å·æœ‰å·®å¼‚ - - 2 MBă€4 MB æˆ–æ— åµŒå…¥å¼ flash，ä¸åŒå‹å·æœ‰å·®å¼‚ - - 4 MB æˆ–æ— åµŒå…¥å¼ flash，ä¸åŒå‹å·æœ‰å·®å¼‚ - - 8 MB æˆ–æ— åµŒå…¥å¼ flash，ä¸åŒå‹å·æœ‰å·®å¼‚ - * - 外部 flash - - æœ€å¤§æ”¯æŒ 16 MB，一次最å¤å¯æ˜ å°„ 11 MB + 248 KB - - æœ€å¤§æ”¯æŒ 1 GB，一次最å¤å¯æ˜ å°„ 11.5 MB - - æœ€å¤§æ”¯æŒ 16 MB，一次最å¤å¯æ˜ å°„ 8 MB - - æœ€å¤§æ”¯æŒ 1 GB，一次最å¤å¯æ˜ å°„ 32 MB - * - 片外 RAM - - æœ€å¤§æ”¯æŒ 8 MB，一次最å¤å¯æ˜ å°„ 4 MB - - æœ€å¤§æ”¯æŒ 1 GB，一次最å¤å¯æ˜ å°„ 11.5 MB - - âœ–ï¸ - - æœ€å¤§æ”¯æŒ 1 GB，一次最å¤å¯æ˜ å°„ 32 MB - * - Cache - - âœ”ï¸ 2 è·¯ç»„ç›¸è” - - âœ”ï¸ 4 路组相è”，独立ç„æŒ‡ä»¤å’Œæ•°æ® cache - - âœ”ï¸ 8 路组相è¿ï¼Œ32 ä½æ•°æ®/指令总线宽度 - - âœ”ï¸ æŒ‡ä»¤ cache å¯é…置为 4 路组相è¿æˆ– 8 路组相è¿ï¼Œæ•°æ® cache 固å®ä¸º 4 路组相è¿ï¼Œ32 ä½æ•°æ®/指令总线宽度 - * - **外设** - - - - - - - - - * - 模/数转æ¢å™¨ (ADC) - - 两个 12 ä½ SAR ADC，å¤è¾¾ 18 个é€é“ - - 两个 12 ä½ SAR ADC，å¤è¾¾ 20 个é€é“ - - 两个 12 ä½ SAR ADC，最å¤æ”¯æŒ 6 个é€é“ - - 两个 12 ä½ SAR ADC，å¤è¾¾ 20 个é€é“ - * - æ•°/模转æ¢å™¨ (DAC) - - 两个 8 ä½é€é“ - - 两个 8 ä½é€é“ - - âœ–ï¸ - - âœ–ï¸ - * - å®æ—¶å™¨ - - 4 个 64 ä½é€ç”¨å®æ—¶å™¨ï¼Œ3 个看门狗å®æ—¶å™¨ - - 4 个 64 ä½é€ç”¨å®æ—¶å™¨ï¼Œ3 个看门狗å®æ—¶å™¨ - - 2 个 54 ä½é€ç”¨å®æ—¶å™¨ï¼Œ3 个看门狗å®æ—¶å™¨ - - 4 个 54 ä½é€ç”¨å®æ—¶å™¨ï¼Œ3 个看门狗å®æ—¶å™¨ - * - 温度传感器 - - âœ–ï¸ - - 1 - - 1 - - 1 - * - 触摸传感器 - - 10 - - 14 - - âœ–ï¸ - - 14 - * - éœå°”传感器 - - 1 - - âœ–ï¸ - - âœ–ï¸ - - âœ–ï¸ - * - é€ç”¨è¾“å…¥/输出æ¥å£ (GPIO) - - 34 - - 43 - - 22 - - 45 - * - 串行外设æ¥å£ (SPI) - - 4 - - 4 - - 3 - - 4 - * - LCD æ¥å£ - - 1 - - 1 - - âœ–ï¸ - - 1 - * - é€ç”¨å¼‚步收å‘器 (UART) - - 3 - - 2 [#one]_ - - 2 [#one]_ - - 3 - * - I2C æ¥å£ - - 2 - - 2 - - 1 - - 2 - * - I2S æ¥å£ - - 2 个，å¯é…置为 8/16/32/40/48 ä½ç„输入输出é€é“ - - 1 个，å¯é…置为 8/16/24/32/48/64 ä½ç„输入输出é€é“ - - 1 个，å¯é…置为 8/16/24/32 ä½ç„输入输出é€é“ - - 2 个，å¯é…置为 8/16/24/32 ä½ç„输入输出é€é“ - * - Camera æ¥å£ - - 1 - - 1 - - âœ–ï¸ - - 1 - * - DMA - - UARTă€SPIă€I2Să€SDIO ä»æœºă€SD/MMC 主机ă€EMACă€BT å’Œ Wi-Fi éƒ½æœ‰ä¸“ç”¨ç„ DMA æ§åˆ¶å™¨ - - UARTă€SPIă€AESă€SHAă€I2S å’Œ ADC æ§åˆ¶å™¨éƒ½æœ‰ä¸“ç”¨ç„ DMA æ§åˆ¶å™¨ - - é€ç”¨ DMA æ§åˆ¶å™¨ï¼Œ3 个æ¥æ”¶é€é“å’Œ 3 个å‘é€é€é“ - - é€ç”¨ DMA æ§åˆ¶å™¨ï¼Œ5 个æ¥æ”¶é€é“å’Œ 5 个å‘é€é€é“ - * - 红外é¥æ§å™¨ (RMT) - - æ”¯æŒ 8 é€é“ - - æ”¯æŒ 4 é€é“ [#one]_，å¯é…置为红外å‘å°„å’Œæ¥æ”¶ - - æ”¯æŒ 4 é€é“ [#two]_，åŒé€é“ç„红外å‘å°„å’ŒåŒé€é“ç„红外æ¥æ”¶ - - æ”¯æŒ 8 é€é“ [#one]_，å¯é…置为红外å‘å°„å’Œæ¥æ”¶ - * - 脉冲计数器 - - 8 é€é“ - - 4 é€é“ [#one]_ - - âœ–ï¸ - - 4 é€é“ [#one]_ - * - LED PWM - - 16 é€é“ - - 8 é€é“ [#one]_ - - 6 é€é“ [#two]_ - - 8 é€é“ [#one]_ - * - MCPWM - - 2，æ供六个 PWM 输出 - - âœ–ï¸ - - âœ–ï¸ - - 2，æ供六个 PWM 输出 - * - USB OTG - - âœ–ï¸ - - 1 - - âœ–ï¸ - - 1 - * - TWAI® æ§åˆ¶å™¨ï¼ˆå…¼å®¹ ISO 11898-1 å议） - - 1 - - 1 - - 1 - - 1 - * - SD/SDIO/MMC 主机æ§åˆ¶å™¨ - - 1 - - âœ–ï¸ - - âœ–ï¸ - - 1 - * - SDIO ä»æœºæ§åˆ¶å™¨ - - 1 - - âœ–ï¸ - - âœ–ï¸ - - âœ–ï¸ - * - 以太网 MAC æ¥å£ - - 1 - - âœ–ï¸ - - âœ–ï¸ - - âœ–ï¸ - * - 超ä½åŸè€—å处ç†å™¨ (ULP) - - ULP FSM - - PicoRV32 内核，8 KB SRAM，ULP FSM - - âœ–ï¸ - - PicoRV32 内核，8 KB SRAM，ULP FSM - * - è¾…å©è°ƒè¯• - - âœ–ï¸ - - âœ–ï¸ - - 1 - - âœ–ï¸ - * - **安全机制** - - - - - - - - - * - 安全å¯å¨ - - âœ”ï¸ - - âœ”ï¸ æ¯” ESP32 更快更安全 - - âœ”ï¸ æ¯” ESP32 更快更安全 - - âœ”ï¸ æ¯” ESP32 更快更安全 - * - Flash å å¯† - - âœ”ï¸ - - âœ”ï¸ æ”¯æŒ PSRAM å å¯†ï¼Œæ¯” ESP32 更安全 - - âœ”ï¸ æ¯” ESP32 更安全 - - âœ”ï¸ æ”¯æŒ PSRAM å å¯†ï¼Œæ¯” ESP32 更安全 - * - OTP - - 1024 ä½ - - 4096 ä½ - - 4096 ä½ - - 4096 ä½ - * - AES - - âœ”ï¸ AES-128, AES-192, AES-256 (FIPS PUB 197) - - âœ”ï¸ AES-128, AES-192, AES-256 (FIPS PUB 197); æ”¯æŒ DMA - - âœ”ï¸ AES-128, AES-256 (FIPS PUB 197); æ”¯æŒ DMA - - âœ”ï¸ AES-128, AES-256 (FIPS PUB 197); æ”¯æŒ DMA - * - HASH - - SHA-1, SHA-256, SHA-384, SHA-512 (FIPS PUB 180-4) - - SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224, SHA-512/256, SHA-512/t (FIPS PUB 180-4); æ”¯æŒ DMA - - SHA-1, SHA-224, SHA-256 (FIPS PUB 180-4); æ”¯æŒ DMA - - SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224, SHA-512/256, SHA-512/t (FIPS PUB 180-4); æ”¯æŒ DMA - * - RSA - - 高达 4096 ä½ - - 高达 4096 ä½ - - 高达 3072 ä½ - - 高达 4096 ä½ - * - é机数生æˆå™¨ (RNG) - - âœ”ï¸ - - âœ”ï¸ - - âœ”ï¸ - - âœ”ï¸ - * - HMAC - - âœ–ï¸ - - âœ”ï¸ - - âœ”ï¸ - - âœ”ï¸ - * - æ•°å­—ç­¾å - - âœ–ï¸ - - âœ”ï¸ - - âœ”ï¸ - - âœ”ï¸ - * - XTS - - âœ–ï¸ - - âœ”ï¸ XTS-AES-128, XTS-AES-256 - - âœ”ï¸ XTS-AES-128 - - âœ”ï¸ XTS-AES-128, XTS-AES-256 - * - **其它** - - - - - - - - - * - Deep-sleep åŸè€—（超ä½åŸè€—传感器监测方å¼ï¼‰ - - 100 μA（ADC 以 1% å ç©ºæ¯”工作时） - - 22 μA（触摸传感器以 1% å ç©ºæ¯”工作时） - - æ— æ­¤æ¨¡å¼ - - TBD - * - å°è£…尺寸 - - QFN48 5*5ă€6*6，ä¸åŒå‹å·æœ‰å·®å¼‚ - - QFN56 7*7 - - QFN32 5*5 - - QFN56 7*7 - -.. note:: - - .. [#one] ä¸ ESP32 相比，å‡å°äº†è¯ç‰‡é¢ç§¯ - - .. [#two] ä¸ ESP32 å’Œ ESP32-S2 相比，å‡å°äº†è¯ç‰‡é¢ç§¯ - -.. note:: - - è¯ç‰‡å¤§å° (die size)ï¼ESP32-C3 < ESP32-S2 < ESP32-S3 < ESP32 - -相关文档 -================= - -- `ESP32 æ€æœ¯è§„格书 (PDF) `_ -- ESP32-PICO æ€æœ¯è§„格书 (PDF) - - - `ESP32-PICO-D4 `_ - - `ESP32-PICO-V3 `_ - - `ESP32-PICO-V3-02 `_ - -- `ESP32-S2 æ€æœ¯è§„格书 (PDF) `_ -- `ESP32-C3 æ€æœ¯è§„格书 (PDF) `_ -- `ESP32-S3 æ€æœ¯è§„格书 (PDF) `_ -- `ESP 产å“é€‰å‹ `_ \ No newline at end of file diff --git a/docs/zh_CN/hw-reference/esp32/get-started-pico-kit.rst b/docs/zh_CN/hw-reference/esp32/get-started-pico-kit.rst index aa1b53ffd8..36cae993c1 100644 --- a/docs/zh_CN/hw-reference/esp32/get-started-pico-kit.rst +++ b/docs/zh_CN/hw-reference/esp32/get-started-pico-kit.rst @@ -188,6 +188,14 @@ No. Name Type Function 3. 该管è„å·²è¿æ¥è‡³å¼€å‘æ¿ç„ USB æ¡¥æ¥å™¨è¯ç‰‡ă€‚ 4. ESP32-PICO-KIT 内置 SPI flash ç„工作电å‹ä¸º 3.3 Vă€‚å› æ­¤ï¼Œstrapping ç®¡è„ MTDI 在模组ä¸ç”µå¤ä½è¿‡ç¨‹ä¸­åº”ä¿æŒä½ç”µå¹³ă€‚如è¿æ¥è¯¥ç®¡è„，请确ä¿è¯¥ç®¡è„在å¤ä½ä¸­ä¸è¦ä¿æŒé«˜ç”µå¹³ă€‚ +管è„布局 +^^^^^^^^^^^ +.. figure:: ../../../_static/esp32-pico-kit-v4-pinout.png + :align: center + :scale: 43% + :alt: ESP32-PICO-KIT 管è„布局（点击放大） + + ESP32-PICO-KIT 管è„布局（点击放大） 应用程åºå¼€å‘ ------------ diff --git a/docs/zh_CN/hw-reference/esp32/user-guide-devkitm-1.rst b/docs/zh_CN/hw-reference/esp32/user-guide-devkitm-1.rst index b27ed0bd91..3fcf02d0ca 100644 --- a/docs/zh_CN/hw-reference/esp32/user-guide-devkitm-1.rst +++ b/docs/zh_CN/hw-reference/esp32/user-guide-devkitm-1.rst @@ -10,9 +10,9 @@ ESP32-DevKitM-1 是ä¹é‘«æ¨å‡ºç„ä¸€æ¬¾åŸºäº ESP32-MINI-1(1U) 模组ç„入门 +------------------------+-------------------------+ -| |ESP32-DevKitM-1-æ­£é¢| | |ESP32-DevKitM-1-侧é¢| | +| |ESP32-DevKitM-1-æ­£é¢| | |ESP32-DevKitM-1-侧é¢| | +------------------------+-------------------------+ -| ESP32-DevKitM-1-æ­£é¢ | ESP32-DevKitM-1-ä¾§é¢ | +| ESP32-DevKitM-1-æ­£é¢ | ESP32-DevKitM-1-ä¾§é¢ | +------------------------+-------------------------+ .. |ESP32-DevKitM-1-æ­£é¢| image:: ../../../_static/esp32-DevKitM-1-front.png @@ -63,7 +63,7 @@ ESP32-DevKitM-1 å¼€å‘æ¿æ˜¯ä¸€æ¬¾å°å·§å®ç”¨ç„å¼€å‘æ¿ï¼Œå…·å¤‡ä»¥ä¸‹ç‰¹è‰² 批é‡è®¢å•è¯·å‰å¾€ https://www.espressif.com/zh-hans/contact-us/sales-questions。 -ç»„ä»¶ä»‹ç» +ç»„ä»¶ä»‹ç» ----------- ESP32-DevKitM-1 å¼€å‘æ¿ç„主è¦ç»„件ă€æ¥å£åæ§åˆ¶æ–¹å¼è§ä¸‹å›¾ă€‚下文以æ¿è½½ ESP32-MINI-1 ç„å¼€å‘æ¿ä¸ºä¾‹è¿›è¡Œè¯´æ˜ă€‚ @@ -135,10 +135,10 @@ ESP32-DevKitM-1 ç„主è¦ç»„件和è¿æ¥æ–¹å¼å¦‚ä¸‹å›¾æ‰€ç¤ºă€‚ .. figure:: ../../../_static/esp32-DevKitM-1_v1_SystemBlock.png :align: center - :alt: ESP32-DevKitM-1 + :alt: ESP32-DevKitM-1 :figclass: align-center - ESP32-DevKitM-1 + ESP32-DevKitM-1 电æºé€‰é¡¹ @@ -161,144 +161,157 @@ ESP32-DevKitM-1 ç„主è¦ç»„件和è¿æ¥æ–¹å¼å¦‚ä¸‹å›¾æ‰€ç¤ºă€‚ å¼€å‘æ¿ä¸¤ä¾§ I/O 管è„，其具体å称和åŸèƒ½è§ä¸‹è¡¨ă€‚外设管è„分é…请å‚考 `ă€ESP32 æ€æœ¯è§„æ ¼ä¹¦ă€‹`_。 -.. list-table:: - :header-rows: 1 - :widths: 10 12 12 66 - - +.. list-table:: + :header-rows: 1 + :widths: 10 12 12 66 + + * - ç¼–å· - - å称 - - ç±»å‹ - - åŸèƒ½ + - å称 + - ç±»å‹ [1]_ + - åŸèƒ½ * - 1 - - GND - - P - - æ¥åœ° + - GND + - P + - æ¥åœ° * - 2 - - 3V3 - - P - - 3.3 V ç”µæº + - 3V3 + - P + - 3.3 V ç”µæº * - 3 - - I36 - - I - - GPIO36, ADC1_CH0, RTC_GPIO0 + - I36 + - I + - GPIO36, ADC1_CH0, RTC_GPIO0 * - 4 - - I37 - - I - - GPIO37, ADC1_CH1, RTC_GPIO1 + - I37 + - I + - GPIO37, ADC1_CH1, RTC_GPIO1 * - 5 - - I38 - - I - - GPIO38, ADC1_CH2, RTC_GPIO2 + - I38 + - I + - GPIO38, ADC1_CH2, RTC_GPIO2 * - 6 - - I39 - - I - - GPIO39, ADC1_CH3, RTC_GPIO3 + - I39 + - I + - GPIO39, ADC1_CH3, RTC_GPIO3 * - 7 - RST - I - - å¤ä½ï¼›é«˜ç”µå¹³ï¼ä½¿èƒ½ï¼›ä½ç”µå¹³ï¼å…³é—­ + - å¤ä½ï¼›é«˜ç”µå¹³ï¼ä½¿èƒ½ï¼›ä½ç”µå¹³ï¼å…³é—­ * - 8 - - I34 - - I - - GPIO34, ADC1_CH6, RTC_GPIO4 + - I34 + - I + - GPIO34, ADC1_CH6, RTC_GPIO4 * - 9 - - I35 - - I - - GPIO35, ADC1_CH7, RTC_GPIO5 + - I35 + - I + - GPIO35, ADC1_CH7, RTC_GPIO5 * - 10 - - IO32 - - I/O - - GPIO32, XTAL_32K_P (32.768 kHz crystal oscillator input), ADC1_CH4, TOUCH9, RTC_GPIO9 + - IO32 + - I/O + - GPIO32, XTAL_32K_P (32.768 kHz crystal oscillator input), ADC1_CH4, TOUCH9, RTC_GPIO9 * - 11 - - IO33 - - I/O - - GPIO33, XTAL_32K_N (32.768 kHz crystal oscillator output), ADC1_CH5, TOUCH8, RTC_GPIO8 + - IO33 + - I/O + - GPIO33, XTAL_32K_N (32.768 kHz crystal oscillator output), ADC1_CH5, TOUCH8, RTC_GPIO8 * - 12 - - IO25 - - I/O - - GPIO25, DAC_1, ADC2_CH8, RTC_GPIO6, EMAC_RXD0 + - IO25 + - I/O + - GPIO25, DAC_1, ADC2_CH8, RTC_GPIO6, EMAC_RXD0 * - 13 - - IO26 - - I/O - - GPIO26, DAC_2, ADC2_CH9, RTC_GPIO7, EMAC_RXD1 + - IO26 + - I/O + - GPIO26, DAC_2, ADC2_CH9, RTC_GPIO7, EMAC_RXD1 * - 14 - - IO27 - - I/O - - GPIO27, ADC2_CH7, TOUCH7, RTC_GPIO17, EMAC_RX_DV + - IO27 + - I/O + - GPIO27, ADC2_CH7, TOUCH7, RTC_GPIO17, EMAC_RX_DV * - 15 - - IO14 - - I/O - - GPIO14, ADC2_CH6, TOUCH6, RTC_GPIO16, MTMS, HSPICLK, HS2_CLK, SD_CLK, EMAC_TXD2 + - IO14 + - I/O + - GPIO14, ADC2_CH6, TOUCH6, RTC_GPIO16, MTMS, HSPICLK, HS2_CLK, SD_CLK, EMAC_TXD2 * - 16 - 5V - - P - - 5 V ç”µæº + - P + - 5 V ç”µæº * - 17 - - IO12 - - I/O - - GPIO12, ADC2_CH5, TOUCH5, RTC_GPIO15, MTDI, HSPIQ, HS2_DATA2, SD_DATA2, EMAC_TXD3 + - IO12 + - I/O + - GPIO12, ADC2_CH5, TOUCH5, RTC_GPIO15, MTDI [2]_, HSPIQ, HS2_DATA2, SD_DATA2, EMAC_TXD3 * - 18 - - IO13 - - I/O - - GPIO13, ADC2_CH4, TOUCH4, RTC_GPIO14, MTCK, HSPID, HS2_DATA3, SD_DATA3, EMAC_RX_ER + - IO13 + - I/O + - GPIO13, ADC2_CH4, TOUCH4, RTC_GPIO14, MTCK, HSPID, HS2_DATA3, SD_DATA3, EMAC_RX_ER * - 19 - - IO15 - - I/O - - GPIO15, ADC2_CH3, TOUCH3, RTC_GPIO13, MTDO, HSPICS0, HS2_CMD, SD_CMD, EMAC_RXD3 + - IO15 + - I/O + - GPIO15, ADC2_CH3, TOUCH3, RTC_GPIO13, MTDO [2]_, HSPICS0, HS2_CMD, SD_CMD, EMAC_RXD3 * - 20 - - IO2 - - I/O - - GPIO2, ADC2_CH2, TOUCH2, RTC_GPIO12, HSPIWP, HS2_DATA0, SD_DATA0 + - IO2 + - I/O + - GPIO2 [2]_, ADC2_CH2, TOUCH2, RTC_GPIO12, HSPIWP, HS2_DATA0, SD_DATA0 * - 21 - - IO0 - - I/O - - GPIO0, ADC2_CH1, TOUCH1, RTC_GPIO11, CLK_OUT1, EMAC_TX_CLK + - IO0 + - I/O + - GPIO0 [2]_, ADC2_CH1, TOUCH1, RTC_GPIO11, CLK_OUT1, EMAC_TX_CLK * - 22 - - IO4 - - I/O - - GPIO4, ADC2_CH0, TOUCH0, RTC_GPIO10, HSPIHD, HS2_DATA1, SD_DATA1, EMAC_TX_ER + - IO4 + - I/O + - GPIO4, ADC2_CH0, TOUCH0, RTC_GPIO10, HSPIHD, HS2_DATA1, SD_DATA1, EMAC_TX_ER * - 23 - - IO9 - - I/O - - GPIO9, HS1_DATA2, U1RXD, SD_DATA2 + - IO9 + - I/O + - GPIO9, HS1_DATA2, U1RXD, SD_DATA2 * - 24 - - IO10 - - I/O - - GPIO10, HS1_DATA3, U1TXD, SD_DATA3 + - IO10 + - I/O + - GPIO10, HS1_DATA3, U1TXD, SD_DATA3 * - 25 - - IO5 - - I/O - - GPIO5, HS1_DATA6, VSPICS0, EMAC_RX_CLK + - IO5 + - I/O + - GPIO5 [2]_, HS1_DATA6, VSPICS0, EMAC_RX_CLK * - 26 - - IO18 - - I/O - - GPIO18, HS1_DATA7, VSPICLK + - IO18 + - I/O + - GPIO18, HS1_DATA7, VSPICLK * - 27 - - IO23 - - I/O - - GPIO23, HS1_STROBE, VSPID + - IO23 + - I/O + - GPIO23, HS1_STROBE, VSPID * - 28 - - IO19 - - I/O - - GPIO19, VSPIQ, U0CTS, EMAC_TXD0 + - IO19 + - I/O + - GPIO19, VSPIQ, U0CTS, EMAC_TXD0 * - 29 - - IO22 - - I/O - - GPIO22, VSPIWP, U0RTS, EMAC_TXD1 + - IO22 + - I/O + - GPIO22, VSPIWP, U0RTS, EMAC_TXD1 * - 30 - - IO21 - - I/O - - GPIO21, VSPIHD, EMAC_TX_EN + - IO21 + - I/O + - GPIO21, VSPIHD, EMAC_TX_EN * - 31 - - TXD0 - - I/O - - GPIO1, U0TXD, CLK_OUT3, EMAC_RXD2 + - TXD0 + - I/O + - GPIO1, U0TXD, CLK_OUT3, EMAC_RXD2 * - 32 - - RXD0 - - I/O - - GPIO3, U0RXD, CLK_OUT2 + - RXD0 + - I/O + - GPIO3, U0RXD, CLK_OUT2 +.. [1] Pï¼ç”µæºï¼›Iï¼è¾“入；Oï¼è¾“å‡ºă€‚ +.. [2] MTDIă€GPIO0ă€GPIO2ă€MTDO å’Œ GPIO5 为 Strapping 管è„ă€‚åœ¨è¯ç‰‡ä¸ç”µå’Œç³»ç»Ÿå¤ä½è¿‡ç¨‹ä¸­ï¼ŒStrapping 管è„æ ¹æ®ç®¡è„ç„二进制电å‹å€¼æ§åˆ¶è¯ç‰‡åŸèƒ½ă€‚Strapping 管è„ç„具体æ述和应用，请å‚考 `ă€ESP32 æ€æœ¯è§„æ ¼ä¹¦ă€‹`_ > ç« è‚ Strapping 管è„。 + +管è„布局 +^^^^^^^^ + +.. figure:: ../../../_static/ESP32_DevKitM-1_pinlayout.png + :align: center + :scale: 43% + :alt: ESP32-DevKitM-1 （点击放大） + :figclass: align-center + + ESP32-DevKitM-1 （点击放大） 硬件修订å†å² =============== @@ -316,4 +329,4 @@ ESP32-DevKitM-1 ç„主è¦ç»„件和è¿æ¥æ–¹å¼å¦‚ä¸‹å›¾æ‰€ç¤ºă€‚ * `ä¹é‘«äº§å“选å‹å·¥å…· `_ * `ă€ESP32 æ€æœ¯è§„æ ¼ä¹¦ă€‹ `_ (PDF) -有关本开å‘æ¿ç„æ›´å¤è®¾è®¡æ–‡æ¡£ï¼Œè¯·è”系我们ç„商å¡éƒ¨é—¨ sales@espressif.com。 \ No newline at end of file +有关本开å‘æ¿ç„æ›´å¤è®¾è®¡æ–‡æ¡£ï¼Œè¯·è”系我们ç„商å¡éƒ¨é—¨ sales@espressif.com。 diff --git a/docs/zh_CN/hw-reference/esp32s2/user-guide-devkitm-1-v1.rst b/docs/zh_CN/hw-reference/esp32s2/user-guide-devkitm-1-v1.rst index f4e1670afb..962706ce0a 100644 --- a/docs/zh_CN/hw-reference/esp32s2/user-guide-devkitm-1-v1.rst +++ b/docs/zh_CN/hw-reference/esp32s2/user-guide-devkitm-1-v1.rst @@ -1,14 +1,12 @@ -===================== -ESP32-S2-DevKitM-1(U) -===================== +================== +ESP32-S2-DevKitM-1 +================== :link_to_translation:`en: [English]` -本指å—介ç»äº†ä¹é‘«ç„å°å‹å¼€å‘æ¿ ESP32-S2-DevKitM-1(U)。 +本指å—介ç»äº†ä¹é‘«ç„å°å‹å¼€å‘æ¿ ESP32-S2-DevKitM-1。 -ESP32-S2-DevKitM-1(U) æ˜¯ä¸€æ¬¾åŸºäº `ESP32-S2FH4 `__ è¯ç‰‡ï¼ˆESP32-S2 系列）ç„é€ç”¨å‹å¼€å‘æ¿ă€‚该款开å‘æ¿å…·æœ‰ä¸°å¯Œç„外设和优化ç„引è„布局，令产å“å¼€å‘æ›´å¿«æ·ă€‚ - -ESP32-S2-DevKitM-1 æ­è½½ç„是 `ESP32-S2-MINI-1 `__ 模组 （PCB æ¿è½½å¤©çº¿ï¼‰ï¼ŒESP32-S2-DevKitM-1U æ­è½½ç„是 `ESP32-S2-MINI-1U `__ 模组 （外部天线è¿æ¥å™¨ï¼‰ă€‚ +ESP32-S2-DevKitM-1 是ä¹é‘«ä¸€æ¬¾å…¥é—¨çº§å¼€å‘æ¿ă€‚æ¿ä¸æ¨¡ç»„大部分管è„å‡å·²å¼•å‡ºè‡³ä¸¤ä¾§æ’针，开å‘人员å¯æ ¹æ®å®é™…需求，轻æ¾é€è¿‡è·³çº¿è¿æ¥å¤ç§å¤–围设备，åŒæ—¶ä¹Ÿå¯å°†å¼€å‘æ¿æ’在é¢åŒ…æ¿ä¸ä½¿ç”¨ă€‚ +----------------------+-----------------------+ | |ESP32-S2-DevKitM-1| | |ESP32-S2-DevKitM-1U| | @@ -22,36 +20,84 @@ ESP32-S2-DevKitM-1 æ­è½½ç„是 `ESP32-S2-MINI-1 `_ ç„外部天线è¿æ¥å™¨å°ºå¯¸ç« è‚。 + - ä»… **ESP32-S2-MINI-2U** å’Œ **ESP32-S2-MINI-1U** 模组带有外部天线è¿æ¥å™¨ă€‚è¿æ¥å™¨å°ºå¯¸ï¼Œè¯·å‚è€ƒæ¨¡ç»„è§„æ ¼ä¹¦ç„ å¤–éƒ¨å¤©çº¿è¿æ¥å™¨å°ºå¯¸ç« è‚。 开始开å‘应用 ------------ -é€ç”µå‰ï¼Œè¯·ç¡®ä¿ ESP32-S2-DevKitM-1(U) 完好无æŸă€‚ +é€ç”µå‰ï¼Œè¯·ç¡®ä¿ ESP32-S2-DevKitM-1 完好无æŸă€‚ 必备硬件 ^^^^^^^^ -- ESP32-S2-DevKitM-1(U) - - + 如使用 ESP32-S2-DevKitM-1U，还需准备天线 - +- ESP32-S2-DevKitM-1 - USB 2.0 æ•°æ®çº¿ï¼ˆæ ‡å‡† A å‹è½¬ Micro-B å‹ï¼‰ - 电脑 （Windowsă€Linux 或 macOS） @@ -125,7 +168,7 @@ ESP32-S2-DevKitM-1(U) 是ä¹é‘«ä¸€æ¬¾æ­è½½ ESP32-S2-MINI-1 或 ESP32-S2-MINI-1U 软件设置 ^^^^^^^^ -请å‰å¾€ :doc:`../../get-started/index`，在 :ref:`get-started-step-by-step` 一è‚查看如何快速设置开å‘ç¯å¢ƒï¼Œå°†åº”用程åºçƒ§å½•è‡³ ESP32-S2-DevKitM-1(U)。 +请å‰å¾€ :doc:`../../get-started/index`，在 :ref:`get-started-step-by-step` 一è‚查看如何快速设置开å‘ç¯å¢ƒï¼Œå°†åº”用程åºçƒ§å½•è‡³ ESP32-S2-DevKitM-1。 .. 注解:: @@ -137,20 +180,20 @@ ESP32-S2-DevKitM-1(U) 是ä¹é‘«ä¸€æ¬¾æ­è½½ ESP32-S2-MINI-1 或 ESP32-S2-MINI-1U åŸèƒ½æ¡†å›¾ -------- -ESP32-S2-DevKitM-1(U) ç„主è¦ç»„件和è¿æ¥æ–¹å¼å¦‚ä¸‹å›¾æ‰€ç¤ºă€‚ +ESP32-S2-DevKitM-1 ç„主è¦ç»„件和è¿æ¥æ–¹å¼å¦‚ä¸‹å›¾æ‰€ç¤ºă€‚ .. figure:: ../../../_static/esp32-s2-devkitm-1-v1-block-diagram.png :align: center :scale: 70% - :alt: ESP32-S2-DevKitM-1(U) （点击放大） + :alt: ESP32-S2-DevKitM-1 （点击放大） :figclass: align-center - ESP32-S2-DevKitM-1(U) （点击放大） + ESP32-S2-DevKitM-1 （点击放大） 电æºé€‰é¡¹ ^^^^^^^^ -您å¯ä»ä»¥ä¸‹ä¸‰ç§ä¾›ç”µæ–¹å¼ä¸­ä»»é€‰å…¶ä¸€ç»™ ESP32-S2-DevKitM-1(U) ä¾›ç”µï¼ +您å¯ä»ä»¥ä¸‹ä¸‰ç§ä¾›ç”µæ–¹å¼ä¸­ä»»é€‰å…¶ä¸€ç»™ ESP32-S2-DevKitM-1 ä¾›ç”µï¼ - Micro-USB æ¥å£ä¾›ç”µï¼ˆé»˜è®¤ï¼‰ - 5V å’Œ GND æ’针供电 @@ -163,7 +206,7 @@ ESP32-S2-DevKitM-1(U) ç„主è¦ç»„件和è¿æ¥æ–¹å¼å¦‚ä¸‹å›¾æ‰€ç¤ºă€‚ æ’é’ˆ ---- -下表列出了开å‘æ¿ä¸¤ä¾§æ’针（J1 å’Œ J3ï¼‰ç„ **å称** å’Œ **åŸèƒ½**，æ’é’ˆç„å称如图 :ref:`user-guide-devkitm-1-v1-board-front` 所示，æ’é’ˆç„åºå·ä¸ `ESP32-S2-DevKitM-1(U) åŸç†å›¾ `_ (PDF)ä¸€è‡´ă€‚ +下表列出了开å‘æ¿ä¸¤ä¾§æ’针（J1 å’Œ J3ï¼‰ç„ **å称** å’Œ **åŸèƒ½**，æ’é’ˆç„å称如图 :ref:`user-guide-devkitm-1-v1-board-front` 所示，æ’é’ˆç„åºå·ä¸ `ESP32-S2-DevKitM-1 åŸç†å›¾ `_ (PDF)ä¸€è‡´ă€‚ J1 ^^^ @@ -228,10 +271,10 @@ J3 .. figure:: ../../../_static/esp32-s2-devkitm-1-v1-pin-layout.png :align: center :scale: 15% - :alt: ESP32-S2-DevKitM-1(U) 管è„布局（点击放大） + :alt: ESP32-S2-DevKitM-1 管è„布局（点击放大） :figclass: align-center - ESP32-S2-DevKitM-1(U) 管è„布局（点击放大） + ESP32-S2-DevKitM-1 管è„布局（点击放大） 硬件版本 ========== @@ -240,11 +283,18 @@ J3 相关文档 ======== -* `ESP32-S2-DevKitM-1(U) åŸç†å›¾ `_ (PDF) -* `ESP32-S2-DevKitM-1(U) PCB 布局 `_ (PDF) -* `ESP32-S2-DevKitM-1(U) 尺寸图 `_ (PDF) -* `ESP32-S2 系列æ€æœ¯è§„格书 `_ (PDF) -* `ESP32-S2-MINI-1 & ESP32-S2-MINI-1U æ€æœ¯è§„格书 `_ (PDF) +* `ESP32-S2 系列è¯ç‰‡ v1.0 版本æ€æœ¯è§„格书`_ (PDF) +* `ESP32-S2 系列è¯ç‰‡ v0.0 版本æ€æœ¯è§„格书 `_ (PDF) +* `ă€ESP32-S2 系列è¯ç‰‡å‹˜è¯¯è¡¨ă€‹`_ (PDF) +* `ă€ESP32-S2-MINI-2 & ESP32-S2-MINI-2U æ€æœ¯è§„æ ¼ä¹¦ă€‹ `_ (PDF) +* `ă€ESP32-S2-MINI-1 & ESP32-S2-MINI-1U æ€æœ¯è§„æ ¼ä¹¦ă€‹ `_ (PDF) +* `ESP32-S2-DevKitM-1 åŸç†å›¾ `_ (PDF) +* `ESP32-S2-DevKitM-1 PCB 布局 `_ (PDF) +* `ESP32-S2-DevKitM-1 尺寸图 `_ (PDF) * `ä¹é‘«äº§å“选å‹å·¥å…· `__ 有关本开å‘æ¿ç„æ›´å¤è®¾è®¡æ–‡æ¡£ï¼Œè¯·è”系我们ç„商å¡éƒ¨é—¨ `sales@espressif.com `_。 + +.. _ä¸æ¨è用äºæ–°è®¾è®¡: https://www.espressif.com/zh-hans/products/longevity-commitment +.. _ESP32-S2 系列è¯ç‰‡ v1.0 版本æ€æœ¯è§„格书: https://www.espressif.com/sites/default/files/documentation/esp32-s2-v1.0_datasheet_cn.pdf +.. _ă€ESP32-S2 系列è¯ç‰‡å‹˜è¯¯è¡¨ă€‹: https://espressif.com/sites/default/files/documentation/esp32-s2_errata_cn.pdf diff --git a/docs/zh_CN/hw-reference/esp32s2/user-guide-s2-devkitc-1.rst b/docs/zh_CN/hw-reference/esp32s2/user-guide-s2-devkitc-1.rst index 2306ad219c..774abbb8d1 100644 --- a/docs/zh_CN/hw-reference/esp32s2/user-guide-s2-devkitc-1.rst +++ b/docs/zh_CN/hw-reference/esp32s2/user-guide-s2-devkitc-1.rst @@ -1,14 +1,12 @@ -=================== +================== ESP32-S2-DevKitC-1 -=================== +================== :link_to_translation:`en: [English]` 本指å—将帮å©æ‚¨å¿«é€Ÿä¸æ‰‹ ESP32-S2-DevKitC-1，并æ供该款开å‘æ¿ç„详细信æ¯ă€‚ -ESP32-S2-DevKitC-1 是一款入门级开å‘æ¿ï¼Œä½¿ç”¨å¸¦æœ‰ 4 MB SPI flash ç„ ESP32-S2-SOLO（æ¿è½½ PCB 天线）或 ESP32-S2-SOLO-U（外部天线è¿æ¥å™¨ï¼‰æ¨¡ç»„ă€‚è¯¥æ¬¾å¼€å‘æ¿å…·å¤‡å®Œæ•´ç„ Wi-Fi åŸèƒ½ă€‚ - -æ¿ä¸æ¨¡ç»„大部分管è„å‡å·²å¼•å‡ºè‡³ä¸¤ä¾§æ’针，开å‘人员å¯æ ¹æ®å®é™…需求，轻æ¾é€è¿‡è·³çº¿è¿æ¥å¤ç§å¤–围设备，åŒæ—¶ä¹Ÿå¯å°†å¼€å‘æ¿æ’在é¢åŒ…æ¿ä¸ä½¿ç”¨ă€‚ +ESP32-S2-DevKitC-1 是一款入门级开å‘æ¿ï¼Œå…·å¤‡å®Œæ•´ç„ Wi-Fi åŸèƒ½ă€‚æ¿ä¸æ¨¡ç»„大部分管è„å‡å·²å¼•å‡ºè‡³ä¸¤ä¾§æ’针，开å‘人员å¯æ ¹æ®å®é™…需求，轻æ¾é€è¿‡è·³çº¿è¿æ¥å¤ç§å¤–围设备，åŒæ—¶ä¹Ÿå¯å°†å¼€å‘æ¿æ’在é¢åŒ…æ¿ä¸ä½¿ç”¨ă€‚ .. figure:: ../../../_static/esp32-s2-devkitc-1-v1-isometric.png :align: center @@ -49,8 +47,8 @@ ESP32-S2-DevKitC-1 是一款入门级开å‘æ¿ï¼Œä½¿ç”¨å¸¦æœ‰ 4 MB SPI flash ç„ * - 主è¦ç»„件 - ä»‹ç» - * - ESP32-S2-SOLO 或 ESP32-S2-SOLO-U - - ESP32-S2-SOLO å’Œ ESP32-S2-SOLO-U 是两款é€ç”¨å‹ Wi-Fi æ¨¡ç»„ă€‚ESP32-S2-SOLO 采用 PCB æ¿è½½å¤©çº¿ï¼ŒESP32-S2-SOLO-U 采用è¿æ¥å™¨è¿æ¥å¤–éƒ¨å¤©çº¿ă€‚å¼€å‘æ¿ä¸ç„ ESP32-S2-SOLO 或 ESP32-S2-SOLO-U 模组å¯é…ç½® 4 MB flash，也å¯é…ç½® 4 MB flash å  2 MB PSRAM（è¯ç‰‡å†…ç½®ï¼‰ă€‚ + * - æ¿è½½æ¨¡ç»„（ä¸å›¾ä¸­ä¸º ESP32-S2-SOLO 或 ESP32-S2-SOLO-U） + - ESP32-S2-SOLO 系列模组，å¯æ­è½½ PCB æ¿è½½å¤©çº¿æˆ–外部天线è¿æ¥å™¨ï¼Œæ”¯æŒå¤ç§ flash å’Œ PSRAM 大å°ă€‚æ›´å¤ä¿¡æ¯ï¼Œè¯¦è§ :ref:`user-guide-s2-devkitc-1-v1-ordering-info`。 * - 3.3 V Power On LED（3.3 V 电æºæŒ‡ç¤ºç¯ï¼‰ - å¼€å‘æ¿è¿æ¥ USB 电æºå，该指示ç¯äº®èµ·ă€‚ * - USB-to-UART Bridge（USB 转 UART æ¡¥æ¥å™¨ï¼‰ @@ -100,6 +98,59 @@ ESP32-S2-DevKitC-1 是一款入门级开å‘æ¿ï¼Œä½¿ç”¨å¸¦æœ‰ 4 MB SPI flash ç„ å†…å«ç»„件和包装 -------------- +.. _user-guide-s2-devkitc-1-v1-ordering-info: + +è®¢è´­ä¿¡æ¯ +^^^^^^^^ + +该开å‘æ¿æœ‰å¤ç§å‹å·å¯ä¾›é€‰æ‹©ï¼Œè¯¦è§ä¸‹è¡¨ă€‚ + +.. list-table:: + :header-rows: 1 + :widths: 35 25 10 10 20 + + * - è®¢è´­ä»£ç  + - æ­è½½æ¨¡ç»„ [#]_ + - Flash + - PSRAM + - 天线 + * - ESP32-S2-DevKitC-1-N8R2 + - ESP32-S2-SOLO-2 + + （æ¨è） + - 8 MB + - 2 MB + - PCB æ¿è½½å¤©çº¿ + * - ESP32-S2-DevKitC-1U-N8R2 + - ESP32-S2-SOLO-2U + + （æ¨è） + - 8 MB + - 2 MB + - 外部天线è¿æ¥å™¨ + * - ESP32-S2-DevKitC-1 + - ESP32-S2-SOLO + - 4 MB + - --- + - PCB æ¿è½½å¤©çº¿ + * - ESP32-S2-DevKitC-1U + - ESP32-S2-SOLO-U + - 4 MB + - --- + - 外部天线è¿æ¥å™¨ + * - ESP32-S2-DevKitC-1R + - ESP32-S2-SOLO + - 4 MB + - 2 MB + - PCB æ¿è½½å¤©çº¿ + * - ESP32-S2-DevKitC-1RU + - ESP32-S2-SOLO-U + - 4 MB + - 2 MB + - 外部天线è¿æ¥å™¨ + +.. [#] ESP32-S2-SOLO-2 å’Œ ESP32-S2-SOLO-2U 模组使用 v1.0 版本è¯ç‰‡ï¼Œå…¶ä½™æ¨¡ç»„使用 v0.0 版本è¯ç‰‡ă€‚æ›´å¤å…³äºè¯ç‰‡ç‰ˆæœ¬ç„ä¿¡æ¯ï¼Œè¯·å‚考 `ă€ESP32-S2 系列è¯ç‰‡å‹˜è¯¯è¡¨ă€‹`_。 + é›¶å”®è®¢å• ^^^^^^^^ @@ -144,36 +195,36 @@ ESP32-S2-DevKitC-1 ç„主è¦ç»„件和è¿æ¥æ–¹å¼å¦‚ä¸‹å›¾æ‰€ç¤ºă€‚ æ’é’ˆ ---- -下表列出了开å‘æ¿ä¸¤ä¾§æ’针（J1 å’Œ J3ï¼‰ç„ **å称** å’Œ **åŸèƒ½**，æ’é’ˆç„å称如图 :ref:`user-guide-s2-devkitc-1-v1-board-front` 所示，æ’é’ˆç„åºå·ä¸ `ESP32-S2-DevKitC-1 åŸç†å›¾ `_ (PDF) ä¸€è‡´ă€‚ +下表列出了开å‘æ¿ä¸¤ä¾§æ’针（J1 å’Œ J3ï¼‰ç„ **å称** å’Œ **åŸèƒ½**，æ’é’ˆç„å称如图 :ref:`user-guide-s2-devkitc-1-v1-board-front` 所示，æ’é’ˆç„åºå·ä¸ `ESP32-S2-DevKitC-1 åŸç†å›¾`_ (PDF) ä¸€è‡´ă€‚ J1 ^^^ -==== ==== ========= ========================================================================= -åºå· å称 ç±»å‹ [#]_ åŸèƒ½ -==== ==== ========= ========================================================================= -1 3V3 P 3.3 V ç”µæº -2 3V3 P 3.3 V ç”µæº -3 RST I CHIP_PU -4 4 I/O/T RTC_GPIO4, GPIO4, TOUCH4, ADC1_CH3 -5 5 I/O/T RTC_GPIO5, GPIO5, TOUCH5, ADC1_CH4 -6 6 I/O/T RTC_GPIO6, GPIO6, TOUCH6, ADC1_CH5 -7 7 I/O/T RTC_GPIO7, GPIO7, TOUCH7, ADC1_CH6 -8 15 I/O/T RTC_GPIO15, GPIO15, U0RTS, ADC2_CH4, XTAL_32K_P -9 16 I/O/T RTC_GPIO16, GPIO16, U0CTS, ADC2_CH5, XTAL_32K_N -10 17 I/O/T RTC_GPIO17, GPIO17, U1TXD, ADC2_CH6, DAC_1 -11 18 I/O/T RTC_GPIO18, GPIO18, U1RXD, ADC2_CH7, DAC_2, CLK_OUT3, RGB LED -12 8 I/O/T RTC_GPIO8, GPIO8, TOUCH8, ADC1_CH7 -13 3 I/O/T RTC_GPIO3, GPIO3, TOUCH3, ADC1_CH2 -14 46 I GPIO46 -15 9 I/O/T RTC_GPIO9, GPIO9, TOUCH9, ADC1_CH8, FSPIHD -16 10 I/O/T RTC_GPIO10, GPIO10, TOUCH10, ADC1_CH9, FSPICS0, FSPIIO4 -17 11 I/O/T RTC_GPIO11, GPIO11, TOUCH11, ADC2_CH0, FSPID, FSPIIO5 -18 12 I/O/T RTC_GPIO12, GPIO12, TOUCH12, ADC2_CH1, FSPICLK, FSPIIO6 -19 13 I/O/T RTC_GPIO13, GPIO13, TOUCH13, ADC2_CH2, FSPIQ, FSPIIO7 -20 14 I/O/T RTC_GPIO14, GPIO14, TOUCH14, ADC2_CH3, FSPIWP, FSPIDQS -21 5V P 5 V ç”µæº -22 G G æ¥åœ° -==== ==== ========= ========================================================================= +==== ========= ========= ========================================================================= +åºå· å称 ç±»å‹ [#]_ åŸèƒ½ +==== ========= ========= ========================================================================= +1 3V3 P 3.3 V ç”µæº +2 3V3 P 3.3 V ç”µæº +3 RST I CHIP_PU +4 4 I/O/T RTC_GPIO4, GPIO4, TOUCH4, ADC1_CH3 +5 5 I/O/T RTC_GPIO5, GPIO5, TOUCH5, ADC1_CH4 +6 6 I/O/T RTC_GPIO6, GPIO6, TOUCH6, ADC1_CH5 +7 7 I/O/T RTC_GPIO7, GPIO7, TOUCH7, ADC1_CH6 +8 15 I/O/T RTC_GPIO15, GPIO15, U0RTS, ADC2_CH4, XTAL_32K_P +9 16 I/O/T RTC_GPIO16, GPIO16, U0CTS, ADC2_CH5, XTAL_32K_N +10 17 I/O/T RTC_GPIO17, GPIO17, U1TXD, ADC2_CH6, DAC_1 +11 18 [#]_ I/O/T RTC_GPIO18, GPIO18[#]_, U1RXD, ADC2_CH7, DAC_2, CLK_OUT3, RGB LED +12 8 I/O/T RTC_GPIO8, GPIO8, TOUCH8, ADC1_CH7 +13 3 I/O/T RTC_GPIO3, GPIO3, TOUCH3, ADC1_CH2 +14 46 I GPIO46 +15 9 I/O/T RTC_GPIO9, GPIO9, TOUCH9, ADC1_CH8, FSPIHD +16 10 I/O/T RTC_GPIO10, GPIO10, TOUCH10, ADC1_CH9, FSPICS0, FSPIIO4 +17 11 I/O/T RTC_GPIO11, GPIO11, TOUCH11, ADC2_CH0, FSPID, FSPIIO5 +18 12 I/O/T RTC_GPIO12, GPIO12, TOUCH12, ADC2_CH1, FSPICLK, FSPIIO6 +19 13 I/O/T RTC_GPIO13, GPIO13, TOUCH13, ADC2_CH2, FSPIQ, FSPIIO7 +20 14 I/O/T RTC_GPIO14, GPIO14, TOUCH14, ADC2_CH3, FSPIWP, FSPIDQS +21 5V P 5 V ç”µæº +22 G G æ¥åœ° +==== ========= ========= ========================================================================= J3 ^^^ @@ -205,13 +256,14 @@ J3 22 G G æ¥åœ° ==== ==== ===== ================================================================ -.. [#] Pï¼ç”µæºï¼›Iï¼è¾“入；Oï¼è¾“出；Tï¼å¯è®¾ç½®ä¸ºé«˜é˜»ă€‚ +.. [#] Pï¼ç”µæºï¼›Iï¼è¾“入；Oï¼è¾“出；Tï¼å¯è®¾ç½®ä¸ºé«˜é˜»ă€‚ +.. [#] æ­è½½ ESP32-S2-SOLO-2 或 ESP32-S2-SOLO-2U ç„å¼€å‘æ¿æœªä¸æ‹‰ GPIO18。 管è„布局 ^^^^^^^^ .. figure:: ../../../_static/esp32-s2-devkitc-1-v1-pinout.png :align: center - :scale: 15% + :scale: 45% :alt: ESP32-S2-DevKitC-1 管è„布局（点击放大） :figclass: align-center @@ -224,11 +276,20 @@ J3 相关文档 ======== -* `ESP32-S2 系列è¯ç‰‡è§„格书 `_ (PDF) -* `ESP32-S2-SOLO & ESP32-S2-SOLO-U 模组æ€æœ¯è§„格书 `_ (PDF) -* `ESP32-S2-DevKitC-1 åŸç†å›¾ `_ (PDF) + +* `ESP32-S2 系列è¯ç‰‡ v1.0 版本æ€æœ¯è§„格书`_ (PDF) +* `ESP32-S2 系列è¯ç‰‡ v0.0 版本æ€æœ¯è§„格书 `_ (PDF) +* `ă€ESP32-S2 系列è¯ç‰‡å‹˜è¯¯è¡¨ă€‹`_ (PDF) +* `ă€ESP32-S2-SOLO-2 & ESP32-S2-SOLO-2U 模组æ€æœ¯è§„æ ¼ä¹¦ă€‹ `_ (PDF) +* `ă€ESP32-S2-SOLO & ESP32-S2-SOLO-U 模组æ€æœ¯è§„æ ¼ä¹¦ă€‹ `_ (PDF) +* `ESP32-S2-DevKitC-1 åŸç†å›¾`_ (PDF) * `ESP32-S2-DevKitC-1 PCB 布局图 `_ (PDF) * `ESP32-S2-DevKitC-1 尺寸图 `_ (PDF) * `ESP32-S2-DevKitC-1 尺寸图æºæ–‡ä»¶ `_ (DXF) - å¯ä½¿ç”¨ `Autodesk Viewer `_ 查看 有关本开å‘æ¿ç„æ›´å¤è®¾è®¡æ–‡æ¡£ï¼Œè¯·è”系我们ç„商å¡éƒ¨é—¨ `sales@espressif.com `_。 + +.. _ä¸æ¨è用äºæ–°è®¾è®¡: https://www.espressif.com/zh-hans/products/longevity-commitment +.. _ESP32-S2 系列è¯ç‰‡ v1.0 版本æ€æœ¯è§„格书: https://www.espressif.com/sites/default/files/documentation/esp32-s2-v1.0_datasheet_cn.pdf +.. _ă€ESP32-S2 系列è¯ç‰‡å‹˜è¯¯è¡¨ă€‹: https://espressif.com/sites/default/files/documentation/esp32-s2_errata_cn.pdf +.. _ESP32-S2-DevKitC-1 åŸç†å›¾: https://dl.espressif.com/dl/schematics/esp-idf/SCH_ESP32-S2-DEVKITC-1_V1_20220817.pdf diff --git a/docs/zh_CN/hw-reference/esp32s3/user-guide-devkitc-1.rst b/docs/zh_CN/hw-reference/esp32s3/user-guide-devkitc-1.rst index 5fd9b14221..332f8adb85 100644 --- a/docs/zh_CN/hw-reference/esp32s3/user-guide-devkitc-1.rst +++ b/docs/zh_CN/hw-reference/esp32s3/user-guide-devkitc-1.rst @@ -38,7 +38,7 @@ ESP32-S3-DevKitC-1 是一款入门级开å‘æ¿ï¼Œæ­è½½ Wi-Fi + Bluetooth® LE .. _user-guide-s3-devkitc-1-v1.1-board-front: -.. figure:: ../../../_static/ESP32-S3-DevKitC-1_v1.1-annotated-photo.png +.. figure:: ../../../_static/ESP32-S3-DevKitC-1_v2-annotated-photo.png :align: center :alt: ESP32-S3-DevKitC-1 - æ­£é¢ @@ -64,7 +64,7 @@ ESP32-S3-DevKitC-1 是一款入门级开å‘æ¿ï¼Œæ­è½½ Wi-Fi + Bluetooth® LE - ä¸‹è½½æŒ‰é”®ă€‚æŒ‰ä½ **Boot** é”®ç„åŒæ—¶æŒ‰ä¸€ä¸‹ **Reset** 键进入“固件下载â€æ¨¡å¼ï¼Œé€è¿‡ä¸²å£ä¸‹è½½å›ºä»¶ă€‚ * - Reset Button（Reset 键） - å¤ä½æŒ‰é”®ă€‚ - * - ESP32-S3 USB Port（ESP32-S3 USB æ¥å£ï¼‰ + * - USB Port（USB æ¥å£ï¼‰ - ESP32-S3 USB OTG æ¥å£ï¼Œæ”¯æŒå…¨é€Ÿ USB 1.1 æ ‡å‡†ă€‚ESP32-S3 USB æ¥å£å¯ç”¨ä½œå¼€å‘æ¿ç„供电æ¥å£ï¼Œå¯çƒ§å½•å›ºä»¶è‡³è¯ç‰‡ï¼Œå¯é€è¿‡ USB åè®®ä¸è¯ç‰‡é€ä¿¡ï¼Œä¹Ÿå¯ç”¨äºÂ JTAG è°ƒè¯•ă€‚ * - USB-to-UART Bridge（USB 转 UART æ¡¥æ¥å™¨ï¼‰ - å•è¯ç‰‡ USB 至 UART æ¡¥æ¥å™¨ï¼Œå¯æ供高达 3 Mbps ç„传输速ç‡ă€‚ diff --git a/docs/zh_CN/hw-reference/index.rst b/docs/zh_CN/hw-reference/index.rst index 564ebdd577..94a8195bbf 100644 --- a/docs/zh_CN/hw-reference/index.rst +++ b/docs/zh_CN/hw-reference/index.rst @@ -22,5 +22,5 @@ H/W 硬件å‚考 ä¹é‘« KiCad 库 ä¹é‘«äº§å“选å‹å·¥å…· ä¹é‘«äº§å“è¯ä¹¦ - è¯ç‰‡ç³»åˆ—对比 + è¯ç‰‡ç³»åˆ—对比 官方论å›ç¡¬ä»¶ç‰ˆå— diff --git a/docs/zh_CN/index.rst b/docs/zh_CN/index.rst index d6d4bf945e..b8563a09d0 100644 --- a/docs/zh_CN/index.rst +++ b/docs/zh_CN/index.rst @@ -19,13 +19,9 @@ ESP-IDF ç¼–ç¨‹æŒ‡å— æœ¬æ–‡æ¡£ä»…åŒ…å«é’ˆå¯¹ {IDF_TARGET_NAME} è¯ç‰‡ç„ ESP-IDF ä½¿ç”¨ă€‚ ================== ================== ================== -|快速入门|_ |API å‚考|_ |H/W å‚考|_ +|快速入门|_ |API å‚考|_ |API 指å—|_ ------------------ ------------------ ------------------ -`快速入门`_ `API å‚考`_ `H/W å‚考`_ ------------------- ------------------ ------------------ -|API 指å—|_ |贡献代ç |_ |相关资æº|_ ------------------- ------------------ ------------------ -`API 指å—`_ `贡献代ç `_ `相关资æº`_ +`快速入门`_ `API å‚考`_ `API 指å—`_ ================== ================== ================== .. |快速入门| image:: ../_static/get-started.png @@ -34,20 +30,11 @@ ESP-IDF ç¼–ç¨‹æŒ‡å— .. |API å‚考| image:: ../_static/api-reference.png .. _API å‚考: api-reference/index.html -.. |H/W å‚考| image:: ../_static/hw-reference.png -.. _H/W å‚考: hw-reference/index.html - .. |API 指å—| image:: ../_static/api-guides.png .. _API 指å—: api-guides/index.html .. _Libraries and Frameworks: libraries-and-frameworks/index.html -.. |贡献代ç | image:: ../_static/contribute.png -.. _贡献代ç : contribute/index.html - -.. |相关资æº| image:: ../_static/resources.png -.. _相关资æº: resources.html - .. toctree:: :hidden: @@ -64,5 +51,3 @@ ESP-IDF ç¼–ç¨‹æŒ‡å— COPYRIGHT about languages - -* :ref:`genindex` diff --git a/docs/zh_CN/migration-guides/release-5.x/bluetooth-classic.rst b/docs/zh_CN/migration-guides/release-5.x/bluetooth-classic.rst index 01cd8f5820..cb607f0502 100644 --- a/docs/zh_CN/migration-guides/release-5.x/bluetooth-classic.rst +++ b/docs/zh_CN/migration-guides/release-5.x/bluetooth-classic.rst @@ -1 +1,64 @@ -.. include:: ../../../en/migration-guides/release-5.x/bluetooth-classic.rst +ç»å…¸è“牙 +================= + +:link_to_translation:`en:[English]` + +Bluedroid +--------- + + - :component_file:`bt/host/bluedroid/api/include/api/esp_hf_defs.h` + + - 在 :cpp:enum:`esp_hf_cme_err_t` 中 + + - ``ESP_HF_CME_MEMEORY_FULL`` 改å为 ``ESP_HF_CME_MEMORY_FULL`` + - ``ESP_HF_CME_MEMEORY_FAILURE`` 改å为 ``ESP_HF_CME_MEMORY_FAILURE`` + + - :component_file:`bt/host/bluedroid/api/include/api/esp_hf_ag_api.h` + + - ``esp_bt_hf_init(esp_bd_addr_t remote_addr)`` 改为 ``esp_hf_ag_init(void)`` + + - ``esp_bt_hf_deinit(esp_bd_addr_t remote_addr)`` 改为 ``esp_hf_ag_deinit(void)`` + + 除此之外，`bt_bdaddr_t init` å’Œ `bt_bdaddr_t deinit` å·²ç»ä» `union btc_arg_t` 中移除。 + + - ``esp_bt_hf_register_callback`` 改为 ``esp_hf_ag_register_callback`` + + - ``esp_bt_hf_connect`` 改为 ``esp_hf_ag_slc_connect`` + + - ``esp_bt_hf_disconnect`` 改为 ``esp_hf_ag_slc_disconnect`` + + - ``esp_bt_hf_connect_audio`` 改为 ``esp_hf_ag_audio_connect`` + + - ``esp_bt_hf_disconnect_audio`` 改为 ``esp_hf_ag_audio_disconnect`` + + - ``esp_bt_hf_vra`` 改为 ``esp_hf_ag_vra_control`` + + - ``esp_bt_hf_volume_control`` 改为 ``esp_hf_ag_volume_control`` + + - ``esp_hf_unat_response`` 改为 ``esp_hf_ag_unknown_at_send`` + + - ``esp_bt_hf_cmee_response`` 改为 ``esp_hf_ag_cmee_send`` + + - ``esp_bt_hf_indchange_notification`` 改为 ``esp_hf_ag_devices_status_indchange`` + + - ``esp_bt_hf_cind_response`` 改为 ``esp_hf_ag_cind_response`` + + - ``esp_bt_hf_cops_response`` 改为 ``esp_hf_ag_cops_response`` + + - ``esp_bt_hf_clcc_response`` 改为 ``esp_hf_ag_clcc_response`` + + - ``esp_bt_hf_cnum_response`` 改为 ``esp_hf_ag_cnum_response`` + + - ``esp_bt_hf_bsir`` 改为 ``esp_hf_ag_bsir`` + + - ``esp_bt_hf_answer_call`` 改为 ``esp_hf_ag_answer_call`` + + - ``esp_bt_hf_reject_call`` 改为 ``esp_hf_ag_reject_call`` + + - ``esp_bt_hf_out_call`` 改为 ``esp_hf_ag_out_call`` + + - ``esp_bt_hf_end_call`` 改为 ``esp_hf_ag_end_call`` + + - ``esp_bt_hf_register_data_callback`` 改为 ``esp_hf_ag_register_data_callback`` + + - ``esp_hf_outgoing_data_ready`` 改为 ``esp_hf_ag_outgoing_data_ready`` diff --git a/docs/zh_CN/migration-guides/release-5.x/bluetooth-low-energy.rst b/docs/zh_CN/migration-guides/release-5.x/bluetooth-low-energy.rst new file mode 100644 index 0000000000..99affc7912 --- /dev/null +++ b/docs/zh_CN/migration-guides/release-5.x/bluetooth-low-energy.rst @@ -0,0 +1,45 @@ +ä½åŸè€—è“牙 +==================== + +:link_to_translation:`en:[English]` + +Bluedroid +--------- + + 以下 Bluedroid å®ă€ç±»å‹å’Œå‡½æ•°å·²è¢«é‡å‘½åï¼ + + - :component_file:`bt/host/bluedroid/api/include/api/esp_gap_ble_api.h` + + - :cpp:enum:`esp_gap_ble_cb_event_t` ä¸­ï¼ + + - ``ESP_GAP_BLE_SET_PREFERED_DEFAULT_PHY_COMPLETE_EVT`` 改å为 ``ESP_GAP_BLE_SET_PREFERRED_DEFAULT_PHY_COMPLETE_EVT`` + - ``ESP_GAP_BLE_SET_PREFERED_PHY_COMPLETE_EVT`` 改å为 ``ESP_GAP_BLE_SET_PREFERRED_PHY_COMPLETE_EVT`` + - ``ESP_GAP_BLE_CHANNEL_SELETE_ALGORITHM_EVT`` 改å为 ``ESP_GAP_BLE_CHANNEL_SELECT_ALGORITHM_EVT`` + + - ``esp_ble_wl_opration_t`` 改å为 :cpp:enum:`esp_ble_wl_operation_t` + - ``esp_ble_gap_cb_param_t.pkt_data_lenth_cmpl`` 改å为 ``pkt_data_length_cmpl`` + - ``esp_ble_gap_cb_param_t.update_whitelist_cmpl.wl_opration`` 改å为 ``wl_operation`` + - ``esp_ble_gap_set_prefered_default_phy`` 改å为 :cpp:func:`esp_ble_gap_set_preferred_default_phy` + - ``esp_ble_gap_set_prefered_phy`` 改å为 :cpp:func:`esp_ble_gap_set_preferred_phy` + + - :component_file:`bt/host/bluedroid/api/include/api/esp_gatt_defs.h` + + - :cpp:enum:`esp_gatt_status_t` ä¸­ï¼ + + - ``ESP_GATT_ENCRYPED_MITM`` 改å为 ``ESP_GATT_ENCRYPTED_MITM`` + - ``ESP_GATT_ENCRYPED_NO_MITM`` 改å为 ``ESP_GATT_ENCRYPTED_NO_MITM`` + +Nimble +-------- + + 以下 Nimble API å·²è¢«ç§»é™¤ï¼ + + - :component_file:`bt/host/nimble/esp-hci/include/esp_nimble_hci.h` + + - 移除 ``esp_err_t esp_nimble_hci_and_controller_init(void)`` + + - æ§åˆ¶å™¨åˆå§‹åŒ–ă€ä½¿èƒ½ä»¥å HCI åˆå§‹åŒ–ç„调用已ç»è¢«ç§»åˆ° `nimble_port_init` 中。å¯ç›´æ¥åˆ é™¤è¯¥å‡½æ•°ă€‚ + + - 移除 ``esp_err_t esp_nimble_hci_and_controller_deinit(void)`` + + - æ§åˆ¶å™¨å»åˆå§‹åŒ–ă€ç¦ç”¨ä»¥å HCI å»åˆå§‹åŒ–ç„调用已ç»è¢«ç§»åˆ° `nimble_port_deinit` 中。å¯ç›´æ¥åˆ é™¤è¯¥å‡½æ•°ă€‚ diff --git a/docs/zh_CN/migration-guides/release-5.x/gcc.rst b/docs/zh_CN/migration-guides/release-5.x/gcc.rst index 532a3c0e03..c8e712d918 100644 --- a/docs/zh_CN/migration-guides/release-5.x/gcc.rst +++ b/docs/zh_CN/migration-guides/release-5.x/gcc.rst @@ -1 +1,139 @@ -.. include:: ../../../en/migration-guides/release-5.x/gcc.rst +GCC +*** + +:link_to_translation:`en:[English]` + + +GCC 版本 +======== + +ESP-IDF 之å‰ä½¿ç”¨ç„ GCC 版本为 8.4.0，ç°å·²é’ˆå¯¹æ‰€æœ‰è¯ç‰‡ç›®æ ‡å‡çº§è‡³ GCC 11.2.0ă€‚è‹¥éœ€è¦å°†æ‚¨ç„代ç ä» GCC 8.4.0 è¿ç§»åˆ° GCC 11.2.0，请å‚考以下官方 GCC è¿ç§»æŒ‡å—。 + +* `è¿ç§»è‡³ GCC 9 `_ +* `è¿ç§»è‡³ GCC 10 `_ +* `è¿ç§»è‡³ GCC 11 `_ + + +è­¦å‘ +==== + +å‡çº§è‡³ GCC 11.2.0 åä¼è§¦å‘æ–°è­¦å‘，或是导致åŸæœ‰è­¦å‘内容å‘生å˜åŒ–ă€‚æ‰€æœ‰ GCC è­¦å‘ç„详细内容，请å‚考 `GCC è­¦å‘选项 `_ă€‚å»ºè®®ç”¨æˆ·ä»”ç»†æ£€æŸ¥ä»£ç ï¼Œå¹¶è®¾æ³•è§£å†³è¿™äº›è­¦å‘ă€‚ä½†ç”±äºæŸäº›è­¦å‘ç„特æ®æ€§å用户代ç ç„å¤æ‚性，有些警å‘å¯èƒ½ä¸ºè¯¯æ¥ï¼Œéœ€è¦è¿›è¡Œå…³é”®ä¿®å¤ă€‚在这ç§æƒ…况下，用户å¯ä»¥é‡‡å–å¤ç§æ–¹å¼æ¥æ‘制这些警å‘ă€‚æœ¬è‚介ç»äº†ç”¨æˆ·å¯èƒ½é‡åˆ°ç„常è§è­¦å‘å如何æ‘制这些警å‘。 + +.. 注æ„:: + 建议用户在æ‘制警å‘之å‰ä»”细确认该警å‘是å¦ç¡®å®ä¸ºè¯¯æ¥ă€‚ + + +``-Wstringop-overflow``〠``-Wstringop-overread``〠``-Wstringop-truncation`` å’Œ ``-Warray-bounds`` +------------------------------------------------------------------------------------------------------------------ + +如æœç¼–译器ä¸èƒ½å‡†ç¡®åˆ¤æ–­å†…存或字符串ç„大å°ï¼Œä½¿ç”¨ memory/string copy/compare 函数ç„用户ä¼é‡åˆ°æŸç§ ``-Wstringop`` è­¦å‘ă€‚ä¸‹æ–‡å±•ç¤ºäº†è§¦å‘这些警å‘ç„代ç ï¼Œå¹¶ä»‹ç»äº†å¦‚何æ‘制这些警å‘。 + +.. code-block:: c + + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wstringop-overflow" + #pragma GCC diagnostic ignored "-Warray-bounds" + memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM); // <<-- 此行触å‘äº†è­¦å‘ + #pragma GCC diagnostic pop + + +.. code-block:: c + + #pragma GCC diagnostic push + #if __GNUC__ >= 11 + #pragma GCC diagnostic ignored "-Wstringop-overread" // <<-- æ­¤é”®ä» GCC 11 开始引入 + #endif + #pragma GCC diagnostic ignored "-Warray-bounds"（-Warray-boundsï¼‰ă€‚ + memcpy(backup_write_data, (void *)EFUSE_PGM_DATA0_REG, sizeof(backup_write_data)); // <<-- 此行触å‘äº†è­¦å‘ + #pragma GCC diagnostic pop + + +``-Waddress-of-packed-member`` +--------------------------------- + +当访问打包 ``struct`` 中ç„æŸä¸ªæœªå¯¹é½æˆå‘˜æ—¶ï¼Œç”±äºé对é½å†…存访问ä¼å¯¹æ€§èƒ½äº§ç”Ÿå½±å“，GCC ä¼è§¦å‘ ``-Waddress-of-packed-member`` è­¦å‘ă€‚ç„¶è€Œï¼Œæ‰€æœ‰åŸºäº Xtensa 或 RISC-V æ¶æ„ç„ ESP è¯ç‰‡éƒ½å…许é对é½å†…存访问，并且ä¸ä¼äº§ç”Ÿé¢å¤–ç„性能影å“ă€‚å› æ­¤ï¼Œåœ¨å¤§å¤æ•°æƒ…况下，å¯ä»¥å¿½ç•¥æ­¤é—®é¢˜ă€‚ + +.. code-block:: none + + components/bt/host/bluedroid/btc/profile/std/gatt/btc_gatt_util.c: In function 'btc_to_bta_gatt_id': + components/bt/host/bluedroid/btc/profile/std/gatt/btc_gatt_util.c:105:21: warning: taking address of packed member of 'struct ' may result in an unaligned pointer value [-Waddress-of-packed-member] + 105 | btc_to_bta_uuid(&p_dest->uuid, &p_src->uuid); + | ^~~~~~~~~~~~~ + + +如æœè¯¥è­¦å‘在å¤ä¸ªæºæ–‡ä»¶ä¸­å¤æ¬¡å‡ºç°ï¼Œå¯ä»¥åœ¨ CMake 级别æ‘制该警å‘ï¼Œå¦‚ä¸‹æ‰€ç¤ºă€‚ + +.. code-block:: cmake + + set_source_files_properties( + "host/bluedroid/bta/gatt/bta_gattc_act.c" + "host/bluedroid/bta/gatt/bta_gattc_cache.c" + "host/bluedroid/btc/profile/std/gatt/btc_gatt_util.c" + "host/bluedroid/btc/profile/std/gatt/btc_gatts.c" + PROPERTIES COMPILE_FLAGS -Wno-address-of-packed-member) + +但如æœåªæœ‰ä¸€æˆ–两处警å‘，å¯ä»¥ç›´æ¥åœ¨æºä»£ç ä¸­è¿›è¡Œæ‘åˆ¶ï¼Œå¦‚ä¸‹æ‰€ç¤ºă€‚ + +.. code-block:: c + + #pragma GCC diagnostic push + #if __GNUC__ >= 9 + #pragma GCC diagnostic ignored "-Waddress-of-packed-member" <<-- æ­¤é”®ä» GCC 11 开始引入 + #endif + uint32_t* reg_ptr = (uint32_t*)src; + #pragma GCC diagnostic pop + + +``llabs()`` ç”¨äº 64 ä½æ•´æ•° +------------------------------- + +stdlib.h 中ç„函数 ``abs()`` 需è¦ä½¿ç”¨ ``int`` å‚æ•°ă€‚è¯·åœ¨è®¡åˆ’ä¸º 64 ä½ç„ç±»å‹ä¸­ä½¿ç”¨ ``llabs()``，尤其是 ``time_t``。 + + +ä¹é‘«å·¥å…·é“¾æ›´æ–° +================= + +Xtensa ç¼–è¯‘å™¨ä¸­ç„ ``int32_t`` å’Œ ``uint32_t`` +--------------------------------------------------- + +在 Xtensa 编译器中，``int32_t`` å’Œ ``uint32_t`` ç±»å‹å·²åˆ†åˆ«ä» ``int`` å’Œ ``unsigned int`` 更新为 ``long`` å’Œ ``unsigned long``ă€‚æ­¤æ›´æ–°ç°ä¸ä¸æ¸¸ GCC 相匹é…，ä¸æ¸¸ GCC 在 Xtensaă€RISC-V 和其他æ¶æ„ä¸ä½¿ç”¨ ``long`` æ•´æ•°æ¥è¡¨ç¤º ``int32_t`` å’Œ ``uint32_t``。 + + +.. list-table:: + :widths: 20 45 35 + :header-rows: 1 + + * - + - 2021r2 å以ä¸ç‰ˆæœ¬ï¼ŒGCC 8 + - 2022r1，GCC 11 + * - Xtensa + - (unsigned) int + - (unsigned) long + * - riscv32 + - (unsigned) long + - (unsigned) long + + +ä¸è¿°å˜åŒ–主è¦å½±å“到使用 ```` æä¾›ç„ç±»å‹æ¥æ ¼å¼åŒ–字符串ç„代ç ă€‚请使用 ``PRIi32``ă€``PRIxx`` ç­‰å ä½ç¬¦æ¥åˆ†åˆ«æ›¿æ¢ ``%i``ă€``%x`` 等。 + +在其他情况下，请注æ„æä¸¾æ”¯æŒ ``int`` ç±»å‹ă€‚ + +é€å¸¸ï¼Œ``int32_t`` å’Œ ``int`` 为ä¸åŒç„ç±»å‹ă€‚åŒæ ·ï¼Œ``uint32_t`` å’Œ ``unsigned int`` 也为ä¸åŒç„ç±»å‹ă€‚ + +如æœç”¨æˆ·åœ¨å…¶åº”用中没有对格å¼åŒ–字符串进行ä¸è¿°æ›´æ–°ï¼Œç¨‹åºä¼æ¥é”™ï¼Œå¦‚ä¸‹æ‰€ç¤ºï¼ + +.. code-block:: none + + /Users/name/esp/esp-rainmaker/components/esp-insights/components/esp_diagnostics/include/esp_diagnostics.h:238:29: error: format '%u' expects argument of type 'unsigned int', but argument 3 has type 'uint32_t' {aka 'long unsigned int'} [-Werror=format=] + 238 | esp_diag_log_event(tag, "EV (%u) %s: " format, esp_log_timestamp(), tag, ##__VA_ARGS__); \ + | ^~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~ + | | + | uint32_t {aka long unsigned int} + uint32_t {aka long unsigned int} + +移除æ„建选项 ``CONFIG_COMPILER_DISABLE_GCC8_WARNINGS`` +---------------------------------------------------------- + +åŸæœ‰ç„ ``CONFIG_COMPILER_DISABLE_GCC8_WARNINGS`` 选项用äºæ„建使用ç°å·²åƒµåŒ–ç„ GCC 5 工具链编写ç„陈旧代ç ă€‚但由äºå·²ç»è¿‡å»è¾ƒé•¿æ—¶é—´ï¼Œç°åœ¨å¯ä»¥å¯¹è­¦å‘进行修å¤ï¼Œå› æ­¤è¯¥é€‰é¡¹å·²è¢«ç§»é™¤ă€‚ + +ç›®å‰ï¼Œåœ¨ GCC 11 中，建议用户仔细检查代ç ï¼Œå°½é‡è§£å†³ç¼–译器警å‘。 diff --git a/docs/zh_CN/migration-guides/release-5.x/index.rst b/docs/zh_CN/migration-guides/release-5.x/index.rst index 3c4a3b45e2..4b476cfa3f 100644 --- a/docs/zh_CN/migration-guides/release-5.x/index.rst +++ b/docs/zh_CN/migration-guides/release-5.x/index.rst @@ -6,7 +6,8 @@ .. toctree:: :maxdepth: 1 - :SOC_CLASSIC_BT_SUPPORTED: bluetooth-classic + :SOC_BT_CLASSIC_SUPPORTED: bluetooth-classic + :SOC_BLE_SUPPORTED: bluetooth-low-energy build-system gcc networking diff --git a/docs/zh_CN/migration-guides/release-5.x/networking.rst b/docs/zh_CN/migration-guides/release-5.x/networking.rst index c14e0d2622..712f529ab0 100644 --- a/docs/zh_CN/migration-guides/release-5.x/networking.rst +++ b/docs/zh_CN/migration-guides/release-5.x/networking.rst @@ -1,67 +1,75 @@ -Networking +网络 =========== :link_to_translation:`en:[English]` -Ethernet -********** +以太网 +************** esp_eth_ioctl() API ------------------- -:cpp:func:`esp_eth_ioctl` third argument could take `int` (`bool`) number as an input in some cases. However, it was not properly documented and, in addition, the number had to be "unnaturally" type casted to `void *` datatype to prevent compiler warnings as shown in below example: -.. highlight:: c +æ­¤å‰ï¼Œ:cpp:func:`esp_eth_ioctl` API å­˜åœ¨ä»¥ä¸‹é—®é¢˜ï¼ -:: + - 在æŸäº›æƒ…况下，第三个å‚数（数æ®ç±»å‹ä¸º ``void /*``）å¯ä»¥æ¥å— ``int``/``bool`` ç±»å‹å®å‚（而éæŒ‡é’ˆï¼‰ä½œä¸ºè¾“å…¥ă€‚ç„¶è€Œï¼Œæ–‡æ¡£ä¸­æœªæè¿°è¿™äº›æƒ…å†µă€‚ + - 为了将 ``int``/``bool`` ç±»å‹å®å‚作为第三个å‚数传递，å®å‚将被强制转æ¢ä¸º ``void *`` ç±»å‹ï¼Œä»¥é˜²å‡ºç°å¦‚下所示ç„编译器警å‘ă€‚æ­¤ç­‰è½¬æ¢å¯èƒ½å¼•èµ· :cpp:func:`esp_eth_ioctl` 函数ç„æ»¥ç”¨ă€‚ + +.. code-block:: c esp_eth_ioctl(eth_handle, ETH_CMD_S_FLOW_CTRL, (void *)true); +因此，我们统一了 :cpp:func:`esp_eth_ioctl` ç„ç”¨æ³•ă€‚ç°åœ¨ï¼Œè¯¥ç»“æ„体ç„第三个å‚数在传递时必须作为指å‘特å®æ•°æ®ç±»å‹ç„指针，表示 :cpp:func:`esp_eth_ioctl` 读å–/存储数æ®ç„ä½ç½®ă€‚:cpp:func:`esp_eth_ioctl` ç„用法如下列代ç æ‰€ç¤ºă€‚ -This could lead to misuse of the :cpp:func:`esp_eth_ioctl`. Therefore, ESP-IDF 5.0 unified usage of :cpp:func:`esp_eth_ioctl`. Its third argument now always acts as pointer to a memory location of specific type from/to where the configuration option is read/stored. +设置以太网é…ç½®ç„ç”¨ä¾‹å¦‚ä¸‹ï¼ -Usage example to set Ethernet configuration: - -.. highlight:: c - -:: +.. code-block:: c eth_duplex_t new_duplex_mode = ETH_DUPLEX_HALF; esp_eth_ioctl(eth_handle, ETH_CMD_S_DUPLEX_MODE, &new_duplex_mode); -Usage example to get Ethernet configuration: - -.. highlight:: c - -:: +è·å–以太网é…ç½®ç„ç”¨ä¾‹å¦‚ä¸‹ï¼ +.. code-block:: c + eth_duplex_t duplex_mode; esp_eth_ioctl(eth_handle, ETH_CMD_G_DUPLEX_MODE, &duplex_mode); +KSZ8041/81 å’Œ LAN8720 驱å¨æ›´æ–° +-------------------------------------------- -KSZ8041/81 and LAN8720 Driver Update ------------------------------------- -KSZ8041/81 and LAN8720 Drivers were updated to support more devices (generations) from associated product family. The drivers are able to recognize particular chip number and its potential support by the driver. +KSZ8041/81 å’Œ LAN8720 驱å¨ç°å·²æ›´æ–°ï¼Œä»¥æ”¯æŒç›¸å…³äº§å“系列中ç„æ›´å¤è®¾å¤‡ï¼ˆå¦‚æ–°ä¸€ä»£è®¾å¤‡ï¼‰ă€‚ä¸è¿°é©±å¨èƒ½å¤Ÿè¯†åˆ«ç‰¹å®è¯ç‰‡ç¼–å·å驱å¨æä¾›ç„潜在支æŒă€‚ -As a result, the specific "chip number" functions calls were replaced by generic ones as follows: +更新之å，é€ç”¨å‡½æ•°å°†æ›¿ä»£ç‰¹å®â€œè¯ç‰‡ç¼–å·â€å‡½æ•°å¾—ä»¥è°ƒç”¨ï¼ -* `esp_eth_phy_new_ksz8041` and `esp_eth_phy_new_ksz8081` were removed, use :cpp:func:`esp_eth_phy_new_ksz80xx` instead -* `esp_eth_phy_new_lan8720` was removed, use :cpp:func:`esp_eth_phy_new_lan87xx` instead +* 删除 ``esp_eth_phy_new_ksz8041()`` 以å ``esp_eth_phy_new_ksz8081()``，转而使用 :cpp:func:`esp_eth_phy_new_ksz80xx` +* 删除 ``esp_eth_phy_new_lan8720()``，转而使用 :cpp:func:`esp_eth_phy_new_lan87xx` -ESP NETIF Glue Event Handlers ------------------------------ -``esp_eth_set_default_handlers()`` and ``esp_eth_clear_default_handlers()`` functions were removed. Registration of the default IP layer handlers for Ethernet is now handled automatically. If users have already followed the recommendation to fully initialize the Ethernet driver and network interface prior to registering their Ethernet/IP event handlers, then no action is required (except for deleting the affected functions). Otherwise, users should ensure that they register the user event handlers as the last thing prior to starting the Ethernet driver. +ESP NETIF Glue 时间处ç†ç¨‹åº +----------------------------------- + +``esp_eth_set_default_handlers()`` å’Œ ``esp_eth_clear_default_handlers()`` 函数ç°å·²åˆ é™¤ă€‚ç°åœ¨å¯ä»¥è‡ªå¨å¤„ç†ä»¥å¤ªç½‘默认 IP 层处ç†ç¨‹åºç„æ³¨å†Œă€‚å¦‚æ‚¨åœ¨æ³¨å†Œä»¥å¤ªç½‘/IP 事件处ç†ç¨‹åºä¹‹å‰å·²ç»æŒ‰ç…§å»ºè®®å®Œå…¨åˆå§‹åŒ–以太网驱å¨å’Œç½‘络æ¥å£ï¼Œåˆ™æ— éœ€æ‰§è¡Œä»»ä½•æ“作（除了删除å—å½±å“ç„å‡½æ•°ï¼‰ă€‚å¦åˆ™ï¼Œåœ¨æ³¨å†Œç”¨æˆ·äº‹ä»¶å¤„ç†ç¨‹åºå，应éå³å¯å¨ä»¥å¤ªç½‘驱å¨ă€‚ + +PHY 地å€è‡ªå¨æ£€æµ‹ +--------------------------- + +以太网 PHY 地å€è‡ªå¨æ£€æµ‹å‡½æ•° ``esp_eth_detect_phy_addr()`` å·²é‡å‘½å为 :cpp:func:`esp_eth_phy_802_3_detect_phy_addr`，其声æ˜ç§»è‡³ :component_file:`esp_eth/include/esp_eth_phy_802_3.h`。 + + +SPI 以太网模å—åˆå§‹åŒ– +-------------------------------------- + +SPI 以太网模å—ç„åˆå§‹åŒ–过程已ç»ç®€åŒ–ă€‚æ­¤å‰ï¼Œæ‚¨éœ€è¦åœ¨å®ä¾‹åŒ– SPI 以太网 MAC 之å‰ï¼Œä½¿ç”¨ :cpp:func:`spi_bus_add_device` 手å¨åˆ†é… SPI è®¾å¤‡ă€‚ + +ç°åœ¨ï¼Œç”±äº SPI 设备已在内部分é…，您无需å†è°ƒç”¨ :cpp:func:`spi_bus_add_device`。:cpp:class:`eth_dm9051_config_t`ă€:cpp:class:`eth_w5500_config_t` å’Œ :cpp:class:`eth_ksz8851snl_config_t` é…置结æ„体ç°å·²åŒ…å« SPI 设备é…ç½®æˆå‘˜ï¼ˆä¾‹å¦‚，å¯ä»¥å¾®è°ƒå¯èƒ½ä¾èµ– PCB è®¾è®¡ç„ SPI æ—¶åºï¼‰ă€‚``ETH_DM9051_DEFAULT_CONFIG``ă€``ETH_W5500_DEFAULT_CONFIG`` å’Œ ``ETH_KSZ8851SNL_DEFAULT_CONFIG`` é…ç½®åˆå§‹åŒ–å®ä¹Ÿå·²æ¥å—æ–°ç„å‚æ•°è¾“å…¥ă€‚äº†è§£ SPI 以太网模å—åˆå§‹åŒ–示例，请查看 :doc:`以太网 API å‚考指å—<../../api-reference/network/esp_eth>`。 -PHY Address Auto-detect ------------------------ -Ethernet PHY address auto-detect function ``esp_eth_detect_phy_addr`` was renamed to :cpp:func:`esp_eth_phy_802_3_detect_phy_addr` and its header declaration was moved to :component_file:`esp_eth/include/esp_eth_phy_802_3.h`. .. _tcpip-adapter: TCP/IP 适é…器 -************* +**************** -TCP/IP 适é…器是在 ESP-IDF v4.1 之å‰ä½¿ç”¨ç„网络æ¥å£æ½è±¡ç»„ä»¶ă€‚æœ¬æ–‡æ¡£æ¦‚è¿°äº†ä» tcpip_adapter 移出至其å继者 :doc:`/api-reference/network/esp_netif` ç„è¿‡ç¨‹ă€‚ +TCP/IP 适é…器是在 ESP-IDF v4.1 之å‰ä½¿ç”¨ç„网络æ¥å£æ½è±¡ç»„ä»¶ă€‚æœ¬æ–‡æ¡£æ¦‚è¿°äº†ä» tcpip_adapter API è¿ç§»è‡³ :doc:`/api-reference/network/esp_netif` ç„è¿‡ç¨‹ă€‚ 更新网络è¿æ¥ä»£ç  @@ -71,45 +79,44 @@ TCP/IP 适é…器是在 ESP-IDF v4.1 之å‰ä½¿ç”¨ç„网络æ¥å£æ½è±¡ç»„件。 网络软件栈åˆå§‹åŒ– ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -åªéœ€å°† ``tcpip_adapter_init()`` 替æ¢ä¸º ``esp_netif_init()``ă€‚è¯·æ³¨æ„，:doc:`/api-reference/network/esp_netif` åˆå§‹åŒ– API å¯è¿”å›æ ‡å‡†é”™è¯¯ä»£ç ï¼Œè¿˜å¯ä»¥ä½¿ç”¨ ``esp_netif_deinit()`` 进行å»åˆå§‹åŒ–。 - -此外，还需将 ``#include "tcpip_adapter.h"`` 替æ¢ä¸º ``#include "esp_netif.h"``。 +- 您åªéœ€ç”¨ ``esp_netif_init()`` æ›¿æ¢ ``tcpip_adapter_init()``ï¼Œæ³¨æ„ ``esp_netif_init()`` 函数ç°å°†è¿”å›æ ‡å‡†é”™è¯¯ä»£ç ă€‚了解详细信æ¯ï¼Œè¯·å‚考 :doc:`/api-reference/network/esp_netif`。 +- ``esp_netif_deinit()`` 函数用äºååˆå§‹åŒ–ç½‘ç»œè½¯ä»¶æ ˆă€‚ +- 您还需用 ``#include "esp_netif.h"`` æ›¿æ¢ ``#include "tcpip_adapter.h"``。 创建网络æ¥å£ ^^^^^^^^^^^^^^^^^^^^^^^^^^ -TCP/IP 适é…器é™æ€å®ä¹‰äº†ä¸‰ä¸ªæ¥å£ï¼ +更新之å‰ï¼ŒTCP/IP 适é…器é™æ€å®ä¹‰äº†ä»¥ä¸‹ä¸‰ä¸ªæ¥å£ï¼ - Wi-Fi Station - Wi-Fi AP - 以太网 -网络æ¥å£ç„设计应严格å‚考 :doc:`/api-reference/network/esp_netif`，以使其能够è¿æ¥åˆ° TCP/IP è½¯ä»¶æ ˆă€‚ -例如，在 TCP/IP 软件栈和事件循ç¯åˆå§‹åŒ–完æˆå，Wi-Fi ç„åˆå§‹åŒ–代ç å¿…须显示调用 ``esp_netif_create_default_wifi_sta();`` 或 ``esp_netif_create_default_wifi_ap();``。 -请å‚阅这三个æ¥å£ç„åˆå§‹åŒ–代ç ç¤ºä¾‹ï¼ +æ¥å£å®ä¹‰ç°å·²æ›´æ–°ă€‚网络æ¥å£ç„设计应严格å‚考 :doc:`/api-reference/network/esp_netif`，使其能够è¿æ¥è‡³ TCP/IP è½¯ä»¶æ ˆă€‚ä¾‹å¦‚ï¼Œåœ¨ TCP/IP 软件栈和事件循ç¯åˆå§‹åŒ–完æˆå，Wi-Fi ç„åˆå§‹åŒ–代ç å¿…须显示调用 ``esp_netif_create_default_wifi_sta();`` 或 ``esp_netif_create_default_wifi_ap();``。 -- Wi-Fi Station: :example_file:`wifi/getting_started/station/main/station_example_main.c` -- Wi-Fi AP: :example_file:`wifi/getting_started/softAP/main/softap_example_main.c` -- 以太网: :example_file:`ethernet/basic/main/ethernet_example_main.c` +请å‚考ä¸è¿°ä¸‰ä¸ªæ¥å£ç„åˆå§‹åŒ–代ç ç¤ºä¾‹ï¼ +- Wi-Fi Stationï¼:example_file:`wifi/getting_started/station/main/station_example_main.c` +- Wi-Fi APï¼:example_file:`wifi/getting_started/softAP/main/softap_example_main.c` +- 以太网ï¼:example_file:`ethernet/basic/main/ethernet_example_main.c` -æ›´æ¢ tcpip_adapter API +其他 tcpip_adapter API æ›´æ¢ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -所有 tcpip_adapter å‡½æ•°éƒ½æœ‰å¯¹åº”ç„ esp-netifă€‚è¯·å‚阅 esp_netif.h 查看更å¤ä¿¡æ¯ï¼ +所有 tcpip_adapter å‡½æ•°éƒ½æœ‰å¯¹åº”ç„ esp-netifă€‚è¯·å‚考以下章è‚ä¸­ç„ esp_netif.h 部分，了解更å¤ä¿¡æ¯ï¼ * :component_file:`Setters/Getters ` * :component_file:`DHCP ` * :component_file:`DNS ` * :component_file:`IP address ` - 默认事件处ç†ç¨‹åº ^^^^^^^^^^^^^^^^^^^^^^ -事件处ç†ç¨‹åºå·²ç»ä» tcpip_adapter 移å¨åˆ°ç›¸åº”ç„驱å¨ç¨‹åºä»£ç ă€‚ä»åº”用程åºç„角度æ¥çœ‹ï¼Œè¿™ä¸ä¼å¸¦æ¥ä»»ä½•å½±å“，所有事件ä»ä»¥ç›¸åŒç„æ–¹å¼å¤„ç†ă€‚ -请注æ„ï¼Œåœ¨ä¸ IP 相关ç„事件处ç†ç¨‹åºä¸­ï¼Œåº”用程åºä»£ç é€å¸¸ä»¥ esp-netif 结æ„体ç„å½¢å¼æ¥æ”¶ IP 地å€ï¼Œè¯¥ç»“æ„体并é LwIP 结æ„，但兼容二进制格å¼ă€‚ +事件处ç†ç¨‹åºå·²ä» tcpip_adapter 移至相应驱å¨ç¨‹åºä»£ç ă€‚ä»åº”用程åºç„角度æ¥çœ‹ï¼Œè¿™ä¸€å˜æ›´ä¸ä¼äº§ç”Ÿä»»ä½•å½±å“，所有事件ä»å°†ä»¥ç›¸åŒç„æ–¹å¼å¤„ç†ă€‚请注æ„ï¼Œåœ¨ä¸ IP 相关ç„事件处ç†ç¨‹åºä¸­ï¼Œåº”用程åºä»£ç é€å¸¸ä»¥ esp-netif 结æ„体而é LwIP 结æ„体ç„å½¢å¼æ¥æ”¶ IP 地å€ă€‚两ç§ç»“æ„体å‡å…¼å®¹äºŒè¿›åˆ¶æ ¼å¼ă€‚ + + 打å°åœ°å€ç„首选方å¼å¦‚ä¸‹æ‰€ç¤ºï¼ .. code-block:: c @@ -122,19 +129,18 @@ TCP/IP 适é…器é™æ€å®ä¹‰äº†ä¸‰ä¸ªæ¥å£ï¼ ESP_LOGI(TAG, "got ip:%s\n", ip4addr_ntoa(&event->ip_info.ip)); -ç”±äº ``ip4addr_ntoa()`` 为 LwIP API，因此 esp-netif 还æ供了替代函数 ``esp_ip4addr_ntoa()``，但整体而言，ä»æ¨è使用第一ç§æ–¹æ³•ă€‚ - +``ip4addr_ntoa()`` 为 LwIP API，因此 esp-netif 还æ供了替代函数 ``esp_ip4addr_ntoa()``，然而总得æ¥è¯´ä»æ¨è使用 ``IP2STR()`` è¿™ä¸€æ–¹æ³•ă€‚ IP åœ°å€ ^^^^^^^^^^^^ æ¨è使用 esp-netif å®ä¹‰ç„ IP 结æ„ă€‚è¯·æ³¨æ„，在å¯ç”¨é»˜è®¤å…¼å®¹æ€§æ—¶ï¼ŒLwIP 结æ„体ä»ç„¶å¯ä»¥å·¥ä½œă€‚ + * :component_file:`esp-netif IP address definitions ` +å续步骤 +^^^^^^^^^^^^^^ -下一步 -^^^^^^^^^^ +为了令移æ¤åº”用程åºå¯ä»¥ä½¿ç”¨ :doc:`/api-reference/network/esp_netif`，还需在组件é…置中ç¦ç”¨ tcpip_adapter å…¼å®¹å±‚ă€‚è¯·å‰å¾€ ``ESP NETIF Adapter`` > ``Enable backward compatible tcpip_adapter interface`` 进行设置，并检查项目是å¦ç¼–译æˆåŸă€‚ -为了令移æ¤åº”用程åºå¯ä»¥ä½¿ç”¨ :doc:`/api-reference/network/esp_netif`，还需在组件é…置中ç¦ç”¨ tcpip_adapter å…¼å®¹å±‚ă€‚ -方法为ï¼``ESP NETIF Adapter`` -> ``Enable backward compatible tcpip_adapter interface``，并检查工程是å¦ç¼–译æˆåŸă€‚ -TCP/IP 适é…器涉å大é‡ä¾èµ–项，这一步å¯èƒ½æœ‰å©äºå°†åº”用程åºä¸ä½¿ç”¨ç‰¹å® TCP/IP è½¯ä»¶æ ˆç„ API 分离开æ¥ă€‚ +TCP/IP 适é…器涉å大é‡ä¾èµ–项，ç¦ç”¨å…¼å®¹å±‚å¯èƒ½æœ‰å©äºå°†åº”用程åºä¸ä½¿ç”¨ç‰¹å® TCP/IP è½¯ä»¶æ ˆç„ API 分离开æ¥ă€‚ diff --git a/docs/zh_CN/migration-guides/release-5.x/peripherals.rst b/docs/zh_CN/migration-guides/release-5.x/peripherals.rst index 0f56c38001..180bc75d5b 100644 --- a/docs/zh_CN/migration-guides/release-5.x/peripherals.rst +++ b/docs/zh_CN/migration-guides/release-5.x/peripherals.rst @@ -1 +1,540 @@ -.. include:: ../../../en/migration-guides/release-5.x/peripherals.rst +外设 +============ + +:link_to_translation:`en:[English]` + +å¤–è®¾æ—¶é’Ÿé—¨æ§ +------------------------------ + +ä¸æ›´æ–°ä¹‹å‰ç›¸åŒï¼Œå¤–设ç„时钟ä»ç”±é©±å¨å¤„ç†ï¼Œç”¨æˆ·æ— éœ€å¯¹å¤–设模å—ç„时钟门æ§è¿›è¡Œè®¾ç½®ă€‚ + +但是，如æœç”¨æˆ·æƒ³åŸºäºç»„件 ``hal`` å’Œ ``soc`` å¼€å‘自己ç„驱å¨ï¼Œè¯·æ³¨æ„时钟门æ§ç„头文件引用路径已由 ``driver/periph_ctrl.h`` 更新为 ``esp_private/periph_ctrl.h``。 + +RTC å­ç³»ç»Ÿæ§åˆ¶ +---------------------------------- + +RTC æ§åˆ¶ API å·²ç»ä» ``driver/rtc_cntl.h`` 移å¨åˆ°äº† ``esp_private/rtc_ctrl.h``。 + +ADC +----------------- + +ADC å•æ¬¡æ¨¡å¼åè¿ç»­æ¨¡å¼é©±å¨ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +ADC å•æ¬¡æ¨¡å¼ç„驱å¨å·²æ›´æ–°ă€‚ + +- æ–°ç„驱å¨ä½äºç»„件 ``esp_adc`` 中，头文件引用路径为 ``esp_adc/adc_oneshot.h``。 +- 旧版驱å¨ä»ç„¶å¯ç”¨ï¼Œå…¶å¤´æ–‡ä»¶å¼•ç”¨è·¯å¾„为 ``driver/adc.h``。 + +å¯¹äº ADC è¿ç»­æ¨¡å¼é©±å¨ï¼Œå…¶ä½ç½®å·²ç”±ç»„件 ``driver`` 更新为 ``esp_adc``。 + +- 头文件引用路径由 ``driver/adc.h`` 更新为 ``esp_adc/adc_continuous.h``。 + +但是，引用两ç§æ¨¡å¼ç„旧版路径 ``driver/adc.h`` ä¼é»˜è®¤è§¦å‘如下编译警å‘，å¯é€è¿‡é…ç½® Kconfig 选项 :ref:`CONFIG_ADC_SUPPRESS_DEPRECATE_WARN` 关闭该警å‘。 + +.. code-block:: text + + legacy adc driver is deprecated, please migrate to use esp_adc/adc_oneshot.h and esp_adc/adc_continuous.h for oneshot mode and continuous mode drivers respectively + +ADC æ ¡å‡†é©±å¨ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +ADC 校准驱å¨å·²æ›´æ–°ă€‚ + +- æ–°ç„驱å¨ä½äºç»„件 ``esp_adc`` 中，头文件引用路径为 ``esp_adc/adc_cali.h`` å’Œ ``esp_adc/adc_cali_scheme.h``。 + +旧版驱å¨ä»ç„¶å¯ç”¨ï¼Œå…¶å¤´æ–‡ä»¶å¼•ç”¨è·¯å¾„为 ``esp_adc_cal.h``ă€‚å¦‚æœç”¨æˆ·è¦ä½¿ç”¨æ—§ç‰ˆè·¯å¾„，需è¦å°†ç»„件 ``esp_adc`` æ·»å åˆ°æ–‡ä»¶ CMakeLists.txt ç„ç»„ä»¶éœ€æ±‚è¡¨ä¸­ă€‚ + +默认情况下，引用路径 ``esp_adc_cal.h`` ä¼é»˜è®¤è§¦å‘如下编译警å‘，å¯é€è¿‡é…ç½® Kconfig 选项 :ref:`CONFIG_ADC_CALI_SUPPRESS_DEPRECATE_WARN` 关闭该警å‘。 + +.. code-block:: text + + legacy adc calibration driver is deprecated, please migrate to use esp_adc/adc_cali.h and esp_adc/adc_cali_scheme.h + +API æ›´æ–° +^^^^^^^^^^^^^^^^^^^^^ + +- ADC 电æºç®¡ç† API ``adc_power_acquire`` å’Œ ``adc_power_release`` 已被移至 ``esp_private/adc_share_hw_ctrl.h``，用äºå†…部åŸèƒ½ă€‚ + + - æ›´æ–°å‰ï¼Œç”±äºç¡¬ä»¶å‹˜è¯¯è¡¨ç„工作åŸç†ï¼Œè¿™ä¸¤ä¸ª API å¯ä»¥è¢«ç”¨æˆ·è°ƒç”¨ă€‚ + - æ›´æ–°å，ADC 电æºç®¡ç†å®Œå…¨ç”±é©±å¨åœ¨å†…部å®ç°ă€‚ + - 如æœç”¨æˆ·ä»éœ€è°ƒç”¨è¿™ä¸ª API，å¯ä»¥é€è¿‡å¼•ç”¨è·¯å¾„ ``esp_private/adc_share_hw_ctrl.h`` æ¥è°ƒç”¨å®ƒă€‚ + +- æ›´æ–°å， ``driver/adc2_wifi_private.h`` 已被移至 ``esp_private/adc_share_hw_ctrl.h``。 +- ``adc_unit_t`` 中ç„æ举 ``ADC_UNIT_BOTH``， ``ADC_UNIT_ALTER`` å ``ADC_UNIT_MAX`` å·²è¢«åˆ é™¤ă€‚ +- ç”±äºåªæœ‰éƒ¨åˆ†è¯ç‰‡æ”¯æŒä¸‹åˆ—æ举ç„æŸäº›å–值，因此将下列æä¸¾åˆ é™¤ă€‚å¦‚æœç”¨æˆ·ä½¿ç”¨äº†ä¸æ”¯æŒç„å–值，ä¼é€ æˆé©±å¨è¿è¡Œé”™è¯¯ă€‚ + + - æ举 ``ADC_CHANNEL_MAX`` + - æ举 ``ADC_ATTEN_MAX`` + - æ举 ``ADC_CONV_UNIT_MAX`` + +- ESP32 ä¸­ç„ API ``hall_sensor_read`` 已被删除，因此 ESP32 ä¸å†æ”¯æŒéœå°”ä¼ æ„Ÿå™¨ă€‚ +- API ``adc_set_i2s_data_source`` å’Œ ``adc_i2s_mode_init`` 已被弃用，相关ç„æ举 ``adc_i2s_source_t`` 也已被弃用，请使用 ``esp_adc/adc_continuous.h`` 进行è¿ç§»ă€‚ + +GPIO +---------- + +- 之å‰ç„ Kconfig 选项 `RTCIO_SUPPORT_RTC_GPIO_DESC` 已被删除，因此数组 ``rtc_gpio_desc`` å·²ä¸å¯ç”¨ï¼Œè¯·ä½¿ç”¨æ›¿ä»£æ•°ç»„ ``rtc_io_desc``。 + +- æ›´æ–°å，用户å›è°ƒå‡½æ•°æ— æ³•å†é€è¿‡è¯»å– GPIO 中断ç„ç¶æ€å¯„存器æ¥è·å–用äºè§¦å‘ä¸­æ–­ç„ GPIO 管è„ç„ç¼–å·ă€‚但是，用户å¯ä»¥é€è¿‡ä½¿ç”¨å›è°ƒå‡½æ•°å˜é‡æ¥ç¡®å®è¯¥ç®¡è„ç¼–å·ă€‚ + + - æ›´æ–°å‰ï¼ŒGPIO 中断å‘生时，GPIO 中断ç¶æ€å¯„存器调用用户å›è°ƒå‡½æ•°ä¹‹å，ä¼è¢«æ¸…ç©ºă€‚å› æ­¤ï¼Œç”¨æˆ·å¯ä»¥åœ¨å›è°ƒå‡½æ•°ä¸­è¯»å– GPIO 中断ç¶æ€å¯„存器，以便确å®è§¦å‘ä¸­æ–­ç„ GPIO 管è„。 + - 但是，在调用å›è°ƒå‡½æ•°å清空中断ç¶æ€å¯„存器å¯èƒ½ä¼å¯¼è‡´è¾¹æ²¿è§¦å‘ç„ä¸­æ–­ä¸¢å¤±ă€‚ä¾‹å¦‚ï¼Œåœ¨è°ƒç”¨ç”¨æˆ·å›è°ƒå‡½æ•°æ—¶ï¼Œå¦‚æœæŸä¸ªè¾¹æ²¿è§¦å‘ç„中断 (re) 被触å‘，该中断ä¼è¢«æ¸…除，并且其注册ç„用户å›è°ƒå‡½æ•°è¿˜æœªè¢«å¤„ç†ă€‚ + - æ›´æ–°å，GPIO ç„中断ç¶æ€å¯„存器在调用用户å›è°ƒå‡½æ•° **之å‰** è¢«æ¸…ç©ºă€‚å› æ­¤ï¼Œç”¨æˆ·æ— æ³•è¯»å– GPIO 中断ç¶æ€å¯„存器æ¥ç¡®å®å“ªä¸ªç®¡è„触å‘äº†ä¸­æ–­ă€‚ä½†æ˜¯ï¼Œç”¨æˆ·å¯ä»¥é€è¿‡å›è°ƒå‡½æ•°å˜é‡æ¥ä¼ é€’被触å‘ç„管è„ç¼–å·ă€‚ + +.. only:: SOC_SDM_SUPPORTED + + Sigma-Delta 调制器 + --------------------------------- + + Sigma-Delta 调制器ç„驱å¨ç°å·²æ›´æ–°ä¸º :doc:`SDM <../../api-reference/peripherals/sdm>`。 + + - 新驱å¨ä¸­å®ç°äº†å·¥å‚模å¼ï¼ŒSDM é€é“都ä½äºå†…部é€é“池中，因此用户无需手å¨å°† SDM é€é“é…置到 GPIO 管è„。 + - SDM é€é“ä¼è¢«è‡ªå¨åˆ†é…。 + + 尽管我们æ¨è用户使用新ç„é©±å¨ API，旧版驱å¨ä»ç„¶å¯ç”¨ï¼Œä½äºå¤´æ–‡ä»¶å¼•ç”¨è·¯å¾„ ``driver/sigmadelta.h`` ä¸­ă€‚ä½†æ˜¯ï¼Œå¼•ç”¨ ``driver/sigmadelta.h`` ä¼é»˜è®¤è§¦å‘如下编译警å‘，å¯é€è¿‡é…ç½® Kconfig 选项 :ref:`CONFIG_SDM_SUPPRESS_DEPRECATE_WARN` 关闭该警å‘。 + + .. code-block:: text + + The legacy sigma-delta driver is deprecated, please use driver/sdm.h + + 概念ä¸ä½¿ç”¨æ–¹æ³•ä¸ç„主è¦æ›´æ–°å¦‚ä¸‹æ‰€ç¤ºï¼ + + 主è¦æ¦‚念更新 + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + - SDM é€é“å称已由 ``sigmadelta_channel_t`` 更新为 :cpp:type:`sdm_channel_handle_t`，å者为一个ä¸é€æ˜æŒ‡é’ˆă€‚ + - SDM é€é“é…ç½®åŸæ¥å­˜æ”¾äº ``sigmadelta_config_t``，ç°å­˜æ”¾äº :cpp:type:`sdm_config_t`。 + - 旧版驱å¨ä¸­ï¼Œç”¨æˆ·æ— éœ€ä¸º SDM é€é“设置时钟æºă€‚但是在新驱å¨ä¸­ï¼Œç”¨æˆ·éœ€è¦åœ¨ :cpp:member:`sdm_config_t::clk_src` 为 SDM é€é“设置åˆé€‚ç„时钟æºï¼Œ:cpp:type:`soc_periph_sdm_clk_src_t` 中列出了å¯ç”¨ç„时钟æºă€‚ + - 旧版驱å¨ä¸­ï¼Œç”¨æˆ·éœ€è¦ä¸ºé€é“设置 ``prescale``，该å‚æ•°ä¼å½±å“调制器输出脉冲ç„频ç‡ă€‚在新ç„驱å¨ä¸­ï¼Œç”¨æˆ·éœ€è¦ä½¿ç”¨ :cpp:member:`sdm_config_t::sample_rate_hz` å®ç°è¯¥åŸèƒ½ă€‚ + + 主è¦ä½¿ç”¨æ–¹æ³•æ›´æ–° + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + - æ›´æ–°å‰ï¼Œé€é“é…置由é€é“分é…在 :cpp:func:`sdm_new_channel` 完æˆă€‚在新驱å¨ä¸­ï¼Œåªæœ‰ ``duty`` å¯åœ¨è¿è¡Œæ—¶ç”± :cpp:func:`sdm_channel_set_duty` æ›´æ–°ă€‚å…¶ä»–å‚数如 ``gpio number``〠``prescale`` åªèƒ½åœ¨é€é“分é…æ—¶è¿›è¡Œè®¾ç½®ă€‚ + - 在进行下一步é€é“æ“作å‰ï¼Œç”¨æˆ·åº”é€è¿‡è°ƒç”¨ :cpp:func:`sdm_channel_enable` æå‰ **使能** 该é€é“ă€‚è¯¥å‡½æ•°æœ‰å©äºç®¡ç†ä¸€äº›ç³»ç»Ÿçº§æœå¡ï¼Œå¦‚ **电æºç®¡ç†**。 + +å®æ—¶å™¨ç»„é©±å¨ +----------------------------------------- + +为统一和简化é€ç”¨å®æ—¶å™¨ç„使用，å®æ—¶å™¨ç»„驱å¨å·²æ›´æ–°ä¸º :doc:`GPTimer <../../api-reference/peripherals/gptimer>`。 + +尽管我们æ¨è使用新ç„é©±å¨ API， 旧版驱å¨ä»ç„¶å¯ç”¨ï¼Œå…¶å¤´æ–‡ä»¶å¼•ç”¨è·¯å¾„为 ``driver/timer.h``ă€‚ä½†æ˜¯ï¼Œå¼•ç”¨ ``driver/timer.h`` ä¼é»˜è®¤è§¦å‘如下编译警å‘，å¯é€è¿‡é…ç½® Kconfig 选项 :ref:`CONFIG_GPTIMER_SUPPRESS_DEPRECATE_WARN` 关闭该警å‘。 + +.. code-block:: text + + legacy timer group driver is deprecated, please migrate to driver/gptimer.h + +概念和使用方法ä¸ç„主è¦æ›´æ–°å¦‚ä¸‹æ‰€ç¤ºï¼ + +主è¦æ¦‚念更新 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- 用äºè¯†åˆ«å®æ—¶å™¨ç„ ``timer_group_t`` å’Œ ``timer_idx_t`` å·²è¢«åˆ é™¤ă€‚åœ¨æ–°é©±å¨ä¸­ï¼Œå®æ—¶å™¨ç”¨å‚æ•° :cpp:type:`gptimer_handle_t` è¡¨ç¤ºă€‚ +- æ›´æ–°å，å®æ—¶å™¨ç„时钟æºç”± :cpp:type:`gptimer_clock_source_t` å®ä¹‰ï¼Œä¹‹å‰ç„时钟æºå‚æ•° ``timer_src_clk_t`` ä¸å†ä½¿ç”¨ă€‚ +- æ›´æ–°å，å®æ—¶å™¨è®¡æ•°æ–¹å‘ç”± :cpp:type:`gptimer_count_direction_t` å®ä¹‰ï¼Œä¹‹å‰ç„计数方å‘å‚æ•° ``timer_count_dir_t`` ä¸å†ä½¿ç”¨ă€‚ +- æ›´æ–°å，仅支æŒç”µå¹³è§¦å‘ç„中断， ``timer_intr_t`` å’Œ ``timer_intr_mode_t`` ä¸å†ä½¿ç”¨ă€‚ +- æ›´æ–°å，é€è¿‡è®¾ç½®æ ‡å¿—ä½ :cpp:member:`gptimer_alarm_config_t::auto_reload_on_alarm`， å¯ä»¥ä½¿èƒ½è‡ªå¨å è½½ă€‚ ``timer_autoreload_t`` ä¸å†ä½¿ç”¨ă€‚ + +主è¦ä½¿ç”¨æ–¹æ³•æ›´æ–° +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- æ›´æ–°å，é€è¿‡ä» :cpp:func:`gptimer_new_timer` 创建å®æ—¶å™¨ç¤ºä¾‹å¯ä»¥åˆå§‹åŒ–å®æ—¶å™¨ă€‚用户å¯ä»¥åœ¨ :cpp:type:`gptimer_config_t` 进行一些基本设置，如时钟æºï¼Œåˆ†è¾¨ç‡å’Œè®¡æ•°æ–¹å‘ă€‚è¯·æ³¨æ„，无需在驱å¨å®‰è£…阶段进行æ¥è­¦äº‹ä»¶ç„特æ®è®¾ç½®ă€‚ +- æ›´æ–°å，æ¥è­¦äº‹ä»¶åœ¨ :cpp:func:`gptimer_set_alarm_action` 中进行设置，å‚数在 :cpp:type:`gptimer_alarm_config_t` ä¸­è¿›è¡Œè®¾ç½®ă€‚ +- æ›´æ–°å，é€è¿‡ :cpp:func:`gptimer_get_raw_count` 设置计数数值，é€è¿‡ :cpp:func:`gptimer_set_raw_count` è·å–è®¡æ•°æ•°å€¼ă€‚é©±å¨ä¸ä¼è‡ªå¨å°†åŸå§‹æ•°æ®åŒæ­¥åˆ° UTC æ—¶é—´æˆ³ă€‚ç”±äºå®æ—¶å™¨ç„分辨ç‡å·²çŸ¥ï¼Œç”¨æˆ·å¯ä»¥è‡ªè¡Œè½¬æ¢æ•°æ®ă€‚ +- æ›´æ–°åï¼Œå¦‚æœ :cpp:member:`gptimer_event_callbacks_t::on_alarm` 被设置为有效ç„å›è°ƒå‡½æ•°ï¼Œé©±å¨ç¨‹åºä¹Ÿä¼å®‰è£…中断æœå¡ă€‚在å›è°ƒå‡½æ•°ä¸­ï¼Œç”¨æˆ·æ— éœ€é…置底层寄存器，如用äºâ€œæ¸…除中断ç¶æ€â€ï¼Œâ€œé‡æ–°ä½¿èƒ½äº‹ä»¶â€ç„å¯„å­˜å™¨ç­‰ă€‚å› æ­¤ï¼Œ ``timer_group_get_intr_status_in_isr`` ä¸ ``timer_group_get_auto_reload_in_isr`` 这些函数ä¸å†ä½¿ç”¨ă€‚ +- æ›´æ–°å，当æ¥è­¦äº‹ä»¶å‘生时，为更新æ¥è­¦é…置，用户å¯ä»¥åœ¨ä¸­æ–­å›è°ƒä¸­è°ƒç”¨ :cpp:func:`gptimer_set_alarm_action`，这样æ¥è­¦äº‹ä»¶ä¼è¢«é‡æ–°ä½¿èƒ½ă€‚ +- æ›´æ–°å，如æœç”¨æˆ·å°† :cpp:member:`gptimer_alarm_config_t::auto_reload_on_alarm` 设置为 true，æ¥è­¦äº‹ä»¶å°†ä¼ä¸€ç›´è¢«é©±å¨ç¨‹åºä½¿èƒ½ă€‚ + +UART +------------ + +.. list-table:: + :width: 700 px + :header-rows: 1 + + * - 删除/弃用项目 + - 替代 + - 备注 + * - ``uart_isr_register()`` + - æ—  + - æ›´æ–°å，UART 中断由驱å¨å¤„ç†ă€‚ + * - ``uart_isr_free()`` + - æ—  + - æ›´æ–°å，UART 中断由驱å¨å¤„ç†ă€‚ + * - :cpp:type:`uart_config_t` ä¸­ç„ ``use_ref_tick`` + - :cpp:member:`uart_config_t::source_clk` + - 选择时钟æºă€‚ + * - ``uart_enable_pattern_det_intr()`` + - :cpp:func:`uart_enable_pattern_det_baud_intr` + - 使能模å¼æ£€æµ‹ä¸­æ–­ă€‚ + +I2C +------- + +.. list-table:: + :width: 700 px + :header-rows: 1 + + * - 删除/弃用项目 + - 替代 + - 备注 + * - ``i2c_isr_register()`` + - æ—  + - æ›´æ–°å，I2C 中断由驱å¨å¤„ç†ă€‚ + * - ``i2c_isr_register()`` + - æ—  + - æ›´æ–°å，I2C 中断由驱å¨å¤„ç†ă€‚ + * - ``i2c_opmode_t`` + - æ—  + - æ›´æ–°å，该项ä¸å†åœ¨ esp-idf ä¸­ä½¿ç”¨ă€‚ + +SPI +--- + +.. list-table:: + :width: 700 px + :header-rows: 1 + + * - 删除/弃用项目 + - 替代 + - 备注 + * - ``spi_cal_clock()`` + - :cpp:func:`spi_get_actual_clock` + - è·å– SPI 真å®ç„工作频ç‡ă€‚ + +- 内部头文件 ``spi_common_internal.h`` 已被移至 ``esp_private/spi_common_internal.h``。 + +.. only:: SOC_SDMMC_HOST_SUPPORTED + + SDMMC + ----- + + .. list-table:: + :width: 700 px + :header-rows: 1 + + * - 删除/弃用项目 + - 替代 + - 备注 + * - ``sdmmc_host_pullup_en()`` + - 在 :cpp:member:`sdmmc_slot_config_t::flags` è®¾ç½®æ ‡å¿—ä½ ``SDMMC_SLOT_FLAG_INTERNAL_PULLUP`` + - 使能内部ä¸æ‹‰ă€‚ + +LEDC +----- + +.. list-table:: + :width: 700 px + :header-rows: 1 + + * - 删除/弃用项目 + - 替代 + - 备注 + * - :cpp:type:`ledc_timer_config_t` ä¸­ç„ ``bit_num`` + - :cpp:member:`ledc_timer_config_t::duty_resolution` + - 设置å ç©ºæ¯”分辨ç‡ă€‚ + +.. only:: SOC_PCNT_SUPPORTED + + 脉冲计数器 (PCNT) é©±å¨ + ---------------------------------- + + 为统一和简化 PCNT 外设，PCNT 驱å¨å·²æ›´æ–°ï¼Œè¯¦è§ :doc:`PCNT <../../api-reference/peripherals/pcnt>`。 + + 尽管我们æ¨è使用新ç„é©±å¨ API，旧版驱å¨ä»ç„¶å¯ç”¨ï¼Œä¿ç•™åœ¨å¤´æ–‡ä»¶å¼•ç”¨è·¯å¾„ ``driver/pcnt.h`` ä¸­ă€‚ä½†æ˜¯ï¼Œå¼•ç”¨è·¯å¾„ ``driver/pcnt.h`` ä¼é»˜è®¤è§¦å‘如下编译警å‘，å¯é€è¿‡é…ç½® Kconfig 选项 :ref:`CONFIG_PCNT_SUPPRESS_DEPRECATE_WARN` æ¥å…³é—­è¯¥è­¦å‘。 + + .. code-block:: text + + legacy pcnt driver is deprecated, please migrate to use driver/pulse_cnt.h + + 主è¦æ¦‚念和使用方法ä¸ç„æ›´æ–°å¦‚ä¸‹æ‰€ç¤ºï¼ + + 主è¦æ¦‚念更新 + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + - æ›´æ–°å， ``pcnt_port_t``〠``pcnt_unit_t`` å’Œ ``pcnt_channel_t`` 这些用äºè¯†åˆ« PCNT å•å…ƒå’Œé€é“ç„å‚æ•°å·²è¢«åˆ é™¤ă€‚åœ¨æ–°ç„驱å¨ä¸­ï¼ŒPCNT å•å…ƒç”±å‚æ•° :cpp:type:`pcnt_unit_handle_t` 表示，PCNT é€é“ç”±å‚æ•° :cpp:type:`pcnt_channel_handle_t` 表示，这两个å‚数都是ä¸é€æ˜æŒ‡é’ˆă€‚ + - æ›´æ–°å，ä¸å†ä½¿ç”¨ ``pcnt_evt_type_t``ï¼Œå®ƒä»¬ç”±ç»Ÿä¸€ç„ **观察点事件** è¡¨ç¤ºă€‚åœ¨äº‹ä»¶å›è°ƒå‡½æ•° :cpp:type:`pcnt_watch_cb_t` 中，é€è¿‡ :cpp:type:`pcnt_watch_event_data_t` å¯ä»¥åˆ†è¾¨ä¸åŒè§‚å¯Ÿç‚¹ă€‚ + - ``pcnt_count_mode_t`` 更新为:cpp:type:`pcnt_channel_edge_action_t`， ``pcnt_ctrl_mode_t`` 更新为 :cpp:type:`pcnt_channel_level_action_t`。 + + 主è¦ä½¿ç”¨æ–¹æ³•æ›´æ–° + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + - æ›´æ–°å‰ï¼ŒPCNT ç„å•å…ƒé…置和é€é“é…置都é€è¿‡å‡½æ•° ``pcnt_unit_config`` å®ç°ă€‚æ›´æ–°å，PCNT ç„å•å…ƒé…ç½®é€è¿‡å·¥å‚ API :cpp:func:`pcnt_new_unit` 完æˆï¼Œé€é“é…ç½®é€è¿‡å·¥å‚ API :cpp:func:`pcnt_new_channel` 完æˆă€‚ + + - åªéœ€é…置计数范围å³å¯åˆå§‹åŒ–一个 PCNT å•å…ƒă€‚æ›´æ–°å，GPIO 管è„分é…é€è¿‡ :cpp:func:`pcnt_new_channel` 完æˆă€‚ + - 高/ä½ç”µå¹³æ§åˆ¶æ¨¡å¼å’Œä¸å‡æ²¿/下é™æ²¿è®¡æ•°æ¨¡å¼åˆ†åˆ«é€è¿‡å‡½æ•° :cpp:func:`pcnt_channel_set_edge_action` å’Œ :cpp:func:`pcnt_channel_set_level_action` è¿›è¡Œè®¾ç½®ă€‚ + + - ``pcnt_get_counter_value`` 更新为 :cpp:func:`pcnt_unit_get_count`。 + - ``pcnt_counter_pause`` 更新为 :cpp:func:`pcnt_unit_stop`。 + - ``pcnt_counter_resume`` 更新为 :cpp:func:`pcnt_unit_start`。 + - ``pcnt_counter_clear`` 更新为 :cpp:func:`pcnt_unit_clear_count`。 + - æ›´æ–°å， ``pcnt_intr_enable`` ä¸ ``pcnt_intr_disable`` å·²è¢«åˆ é™¤ă€‚æ–°ç„驱å¨ä¸­ï¼Œé€è¿‡æ³¨å†Œæ—¶é—´å›è°ƒå‡½æ•° :cpp:func:`pcnt_unit_register_event_callbacks` æ¥ä½¿èƒ½ä¸­æ–­ă€‚ + - æ›´æ–°å， ``pcnt_event_enable`` ä¸ ``pcnt_event_disable`` å·²è¢«åˆ é™¤ă€‚æ–°ç„驱å¨ä¸­ï¼Œå¯é€è¿‡ :cpp:func:`pcnt_unit_add_watch_point` å’Œ :cpp:func:`pcnt_unit_remove_watch_point` æ¥å¢å /删除观察点，以使能/åœç”¨ PCNT äº‹ä»¶ă€‚ + - æ›´æ–°å， ``pcnt_set_event_value`` å·²è¢«åˆ é™¤ă€‚æ–°ç„驱å¨ä¸­ï¼Œé€è¿‡ :cpp:func:`pcnt_unit_add_watch_point` å¢å è§‚察点时，也åŒæ—¶è®¾ç½®äº†äº‹ä»¶ç„æ•°å€¼ă€‚ + - æ›´æ–°å， ``pcnt_get_event_value`` ä¸ ``pcnt_get_event_status`` å·²è¢«åˆ é™¤ă€‚åœ¨æ–°ç„驱å¨ä¸­ï¼Œè¿™äº›ä¿¡æ¯å­˜å‚¨åœ¨ :cpp:type:`pcnt_watch_event_data_t` ç„å›è°ƒå‡½æ•° :cpp:type:`pcnt_watch_cb_t` 中。 + - æ›´æ–°å， ``pcnt_isr_register`` ä¸ ``pcnt_isr_unregister`` 已被删除，ä¸å…许注册 ISR å¥æŸ„。 用户å¯ä»¥é€è¿‡è°ƒç”¨:cpp:func:`pcnt_unit_register_event_callbacks` æ¥æ³¨å†Œäº‹ä»¶å›è°ƒå‡½æ•°ă€‚ + - æ›´æ–°å， ``pcnt_set_pin`` 已被删除，新ç„驱å¨ä¸å†å…许在è¿è¡Œæ—¶åˆ‡æ¢ GPIO 管è„ă€‚å¦‚æœç”¨æˆ·æƒ³åˆ‡æ¢ä¸ºå…¶ä»– GPIO 管è„，å¯é€è¿‡:cpp:func:`pcnt_del_channel` 删除当å‰ç„ PCNT é€é“，然åé€è¿‡:cpp:func:`pcnt_new_channel` å®‰è£…æ–°ç„ GPIO 管è„。 + - ``pcnt_filter_enable``， ``pcnt_filter_disable`` ä¸ ``pcnt_set_filter_value`` 更新为 :cpp:func:`pcnt_unit_set_glitch_filter`。åŒæ—¶ï¼Œ ``pcnt_get_filter_value`` å·²è¢«åˆ é™¤ă€‚ + - ``pcnt_set_mode`` 更新为 :cpp:func:`pcnt_channel_set_edge_action` ä¸ :cpp:func:`pcnt_channel_set_level_action`。 + - ``pcnt_isr_service_install``， ``pcnt_isr_service_uninstall``， ``pcnt_isr_handler_add`` ä¸ ``pcnt_isr_handler_remove`` 更新为 :cpp:func:`pcnt_unit_register_event_callbacks`ă€‚é»˜è®¤ç„ ISR å¥æŸ„已安装在新ç„驱å¨ä¸­ă€‚ + +.. only:: SOC_TEMP_SENSOR_SUPPORTED + + æ¸©åº¦ä¼ æ„Ÿå™¨é©±å¨ + ------------------------------------------------------------ + + 温度传感器ç„驱å¨å·²æ›´æ–°ï¼Œæ¨è用户使用新驱å¨ă€‚旧版驱å¨ä»ç„¶å¯ç”¨ï¼Œä½†æ˜¯æ— æ³•ä¸æ–°é©±å¨åŒæ—¶ä½¿ç”¨ă€‚ + + 新驱å¨ç„头文件引用路径为 ``driver/temperature_sensor.h``ă€‚æ—§ç‰ˆé©±å¨ä»ç„¶å¯ç”¨ï¼Œä¿ç•™åœ¨å¼•ç”¨è·¯å¾„ ``driver/temp_sensor.h`` ä¸­ă€‚ä½†æ˜¯ï¼Œå¼•ç”¨è·¯å¾„ ``driver/temp_sensor.h`` ä¼é»˜è®¤è§¦å‘如下编译警å‘，å¯é€è¿‡è®¾ç½® Kconfig 选项 :ref:`CONFIG_TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN` æ¥å…³é—­è¯¥è­¦å‘。 + + .. code-block:: text + + legacy temperature sensor driver is deprecated, please migrate to driver/temperature_sensor.h + + é…ç½®å†…å®¹å·²æ›´æ–°ă€‚æ›´æ–°å‰ï¼Œç”¨æˆ·éœ€è¦è®¾ç½® ``clk_div`` ä¸ ``dac_offset``ă€‚æ›´æ–°å，用户仅需设置 ``tsens_range``。 + + 温度传感器ç„ä½¿ç”¨è¿‡ç¨‹ä¹Ÿå·²æ›´æ–°ă€‚æ›´æ–°å‰ï¼Œç”¨æˆ·å¯é€è¿‡ ``config->start->read_celsius`` è·å–æ•°æ®ă€‚æ›´æ–°å，用户需è¦é€è¿‡ ``temperature_sensor_install`` 先安装温度传感器ç„驱å¨ï¼Œæµ‹é‡å®Œæˆå需å¸è½½é©±å¨ï¼Œè¯¦æƒ…请å‚考 :doc:`Temperature Sensor <../../api-reference/peripherals/temp_sensor>`。 + +.. only:: SOC_RMT_SUPPORTED + + RMT é©±å¨ + ---------------------- + + 为统一和扩展 RMT 外设ç„使用，RMT 驱å¨å·²æ›´æ–°ï¼Œè¯¦è§ :doc:`RMT transceiver <../../api-reference/peripherals/rmt>`。 + + 尽管我们建议使用新ç„é©±å¨ API，旧版驱å¨ä»ç„¶å¯ç”¨ï¼Œä¿ç•™åœ¨å¤´æ–‡ä»¶å¼•ç”¨è·¯å¾„ ``driver/rmt.h``ä¸­ă€‚ä½†æ˜¯ï¼Œå¼•ç”¨è·¯å¾„ ``driver/rmt.h`` ä¼é»˜è®¤è§¦å‘如下编译警å‘，å¯é€è¿‡é…ç½® Kconfig 选项 :ref:`CONFIG_RMT_SUPPRESS_DEPRECATE_WARN` æ¥å…³é—­è¯¥è­¦å‘。 + + .. code-block:: text + + The legacy RMT driver is deprecated, please use driver/rmt_tx.h and/or driver/rmt_rx.h + + 主è¦æ¦‚å¿µå’Œä½¿ç”¨æ–¹æ³•æ›´æ–°å¦‚ä¸‹æ‰€ç¤ºï¼ + + 主è¦æ¦‚念更新 + ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + - æ›´æ–°å，用äºè¯†åˆ«ç¡¬ä»¶é€é“ç„ ``rmt_channel_t`` å·²åˆ é™¤ă€‚åœ¨æ–°ç„驱å¨ä¸­ï¼ŒRMT é€é“用å‚æ•° :cpp:type:`rmt_channel_handle_t` 表示，该é€é“由驱å¨ç¨‹åºå¨æ€åˆ†é…，而ä¸æ˜¯ç”±ç”¨æˆ·æŒ‡å®ă€‚ + - ``rmt_item32_t`` 更新为 :cpp:type:`rmt_symbol_word_t`，以é¿å…在结æ„体中出ç°åµŒå¥—ç„å…±ç”¨ä½“ă€‚ + - æ›´æ–°å， ``rmt_mem_t`` 已被删除，因为我们ä¸å…许用户直æ¥è®¿é—® RMT 内存å—ï¼ˆå³ RMTMEMï¼‰ă€‚ç›´æ¥è®¿é—® RMTMEM 没有æ„义，å而ä¼å¼•å‘错误，特别是当 RMT é€é“ä¸ DMA é€é“相è¿æ—¶ă€‚ + - æ›´æ–°åï¼Œç”±äº ``rmt_mem_owner_t`` 由驱å¨æ§åˆ¶ï¼Œè€Œä¸æ˜¯ç”¨æˆ·ï¼Œå› æ­¤ ``rmt_mem_owner_t`` å·²è¢«åˆ é™¤ă€‚ + - ``rmt_source_clk_t`` 更新为 :cpp:type:`rmt_clock_source_t`，å者ä¸æ”¯æŒäºŒè¿›åˆ¶å…¼å®¹ă€‚ + - æ›´æ–°å， ``rmt_data_mode_t`` 已被删除，RMT 内存访问模å¼é…置为始终使用 Non-FIFO å’Œ DMA 模å¼ă€‚ + - æ›´æ–°å，由äºé©±å¨æœ‰ç‹¬ç«‹ç„å‘é€å’Œæ¥æ”¶é€é“安装函数，因此 ``rmt_mode_t`` å·²è¢«åˆ é™¤ă€‚ + - æ›´æ–°å， ``rmt_idle_level_t`` 已被删除，在 :cpp:member:`rmt_transmit_config_t::eot_level` 中å¯ä¸ºå‘é€é€é“设置空闲ç¶æ€ç”µå¹³ă€‚ + - æ›´æ–°å， ``rmt_carrier_level_t`` 已被删除，å¯åœ¨ :cpp:member:`rmt_carrier_config_t::polarity_active_low` 设置载æµå­ææ€§ă€‚ + - æ›´æ–°å， ``rmt_channel_status_t`` ä¸ ``rmt_channel_status_result_t`` 已被删除，ä¸å†ä½¿ç”¨ă€‚ + - é€è¿‡ RMT é€é“å‘é€å¹¶ä¸éœ€è¦ç”¨æˆ·æä¾› RMT 符å·ï¼Œä½†æ˜¯ç”¨æˆ·éœ€è¦æ供一个 RMT ç¼–ç å™¨ç”¨æ¥å‘诉驱å¨å¦‚何将用户数æ®è½¬æ¢æˆ RMT 符å·ă€‚ + + 主è¦ä½¿ç”¨æ–¹æ³•æ›´æ–° + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + - æ›´æ–°å，分别é€è¿‡ :cpp:func:`rmt_new_tx_channel` å’Œ :cpp:func:`rmt_new_rx_channel` 安装å‘é€é€é“å’Œæ¥æ”¶é€é“。 + - æ›´æ–°å， ``rmt_set_clk_div`` å’Œ ``rmt_get_clk_div`` å·²è¢«åˆ é™¤ă€‚é€é“时钟é…ç½®åªèƒ½åœ¨é€é“安装时完æˆă€‚ + - æ›´æ–°å， ``rmt_set_rx_idle_thresh`` å’Œ ``rmt_get_rx_idle_thresh`` å·²è¢«åˆ é™¤ă€‚æ–°é©±å¨ä¸­ï¼Œæ¥æ”¶é€é“ç„空闲ç¶æ€é˜ˆå€¼å®ä¹‰ä¸º :cpp:member:`rmt_receive_config_t::signal_range_max_ns`。 + - æ›´æ–°å， ``rmt_set_mem_block_num`` å’Œ ``rmt_get_mem_block_num`` å·²è¢«åˆ é™¤ă€‚æ–°é©±å¨ä¸­ï¼Œå†…å­˜å—ç„æ•°é‡ç”± :cpp:member:`rmt_tx_channel_config_t::mem_block_symbols` ä¸ :cpp:member:`rmt_rx_channel_config_t::mem_block_symbols` 决å®ă€‚ + - æ›´æ–°å， ``rmt_set_tx_carrier`` å·²è¢«åˆ é™¤ă€‚æ–°é©±å¨ä½¿ç”¨ :cpp:func:`rmt_apply_carrier` æ¥è®¾ç½®è½½æ³¢å¨ä½œă€‚ + - æ›´æ–°å， ``rmt_set_mem_pd`` å’Œ ``rmt_get_mem_pd`` 已被删除，驱å¨ç¨‹åºè‡ªå¨è°ƒæ•´å†…å­˜ç„åŸç‡ă€‚ + - æ›´æ–°å， ``rmt_memory_rw_rst``， ``rmt_tx_memory_reset`` å’Œ ``rmt_rx_memory_reset`` 已被删除，驱å¨ç¨‹åºè‡ªå¨è¿›è¡Œå†…å­˜é‡ç½®ă€‚ + - æ›´æ–°å， ``rmt_tx_start`` å’Œ ``rmt_rx_start`` 被åˆå¹¶ä¸ºå‡½æ•° :cpp:func:`rmt_enable`，该函数åŒæ—¶é€‚用äºå‘å°„é€é“å’Œæ¥æ”¶é€é“。 + - æ›´æ–°å， ``rmt_tx_stop`` å’Œ ``rmt_rx_stop`` 被åˆå¹¶ä¸ºå‡½æ•° :cpp:func:`rmt_disable`，该函数åŒæ—¶é€‚用äºå‘å°„é€é“å’Œæ¥æ”¶é€é“。 + - æ›´æ–°å， ``rmt_set_memory_owner`` å’Œ ``rmt_get_memory_owner`` 已被删除，驱å¨ç¨‹åºè‡ªå¨æ·»å  RMT 内存ä¿æ¤ă€‚ + - æ›´æ–°å， ``rmt_set_tx_loop_mode`` å’Œ ``rmt_get_tx_loop_mode`` å·²è¢«åˆ é™¤ă€‚æ–°é©±å¨ä¸­ï¼Œåœ¨ :cpp:member:`rmt_transmit_config_t::loop_count` 中设置循ç¯æ¨¡å¼ă€‚ + - æ›´æ–°å， ``rmt_set_source_clk`` å’Œ ``rmt_get_source_clk`` å·²è¢«åˆ é™¤ă€‚ä»…èƒ½åœ¨é€é“安装时é€è¿‡ :cpp:member:`rmt_tx_channel_config_t::clk_src` å’Œ :cpp:member:`rmt_rx_channel_config_t::clk_src` 设置时钟æºă€‚ + - æ›´æ–°å， ``rmt_set_rx_filter`` å·²è¢«åˆ é™¤ă€‚æ–°é©±å¨ä¸­ï¼Œè¿‡æ»¤é˜ˆå€¼å®ä¹‰ä¸º :cpp:member:`rmt_receive_config_t::signal_range_min_ns`。 + - æ›´æ–°å， ``rmt_set_idle_level`` å’Œ ``rmt_get_idle_level`` 已被删除，å¯åœ¨ :cpp:member:`rmt_transmit_config_t::eot_level` 中设置å‘å°„é€é“ç„空闲ç¶æ€ç”µå¹³ă€‚ + - æ›´æ–°å， ``rmt_set_rx_intr_en``， ``rmt_set_err_intr_en``， ``rmt_set_tx_intr_en``， ``rmt_set_tx_thr_intr_en`` å’Œ ``rmt_set_rx_thr_intr_en`` å·²è¢«åˆ é™¤ă€‚æ–°é©±å¨ä¸å…许用户在用户端开å¯/关闭中断，而是æ供了å›è°ƒå‡½æ•°ă€‚ + - æ›´æ–°å， ``rmt_set_gpio`` å’Œ ``rmt_set_pin`` å·²è¢«åˆ é™¤ă€‚æ–°é©±å¨ä¸æ”¯æŒè¿è¡Œæ—¶å¨æ€åˆ‡æ¢ GPIO 管è„。 + - æ›´æ–°å， ``rmt_config`` å·²è¢«åˆ é™¤ă€‚æ–°é©±å¨ä¸­ï¼ŒåŸºç¡€é…置在é€é“安装阶段完æˆă€‚ + - æ›´æ–°å， ``rmt_isr_register`` å’Œ ``rmt_isr_deregister`` 已被删除，驱å¨ç¨‹åºè´Ÿè´£åˆ†é…ä¸­æ–­ă€‚ + - ``rmt_driver_install`` 更新为 :cpp:func:`rmt_new_tx_channel` ä¸ :cpp:func:`rmt_new_rx_channel`。 + - ``rmt_driver_uninstall`` 更新为 :cpp:func:`rmt_del_channel`。 + - æ›´æ–°å， ``rmt_fill_tx_items``， ``rmt_write_items`` å’Œ ``rmt_write_sample`` å·²è¢«åˆ é™¤ă€‚æ–°é©±å¨ä¸­ï¼Œç”¨æˆ·éœ€è¦æ供一个编ç å™¨ç”¨æ¥å°†ç”¨æˆ·æ•°æ®â€œç¿»è¯‘â€ä¸º RMT 符å·ă€‚ + - æ›´æ–°å，由äºç”¨æˆ·å¯ä»¥é€è¿‡ :cpp:member:`rmt_tx_channel_config_t::resolution_hz` é…ç½®é€é“ç„时钟分辨ç‡ï¼Œ ``rmt_get_counter_clock`` å·²è¢«åˆ é™¤ă€‚ + - ``rmt_wait_tx_done`` 更新为 :cpp:func:`rmt_tx_wait_all_done`。 + - æ›´æ–°å， ``rmt_translator_init``， ``rmt_translator_set_context`` å’Œ ``rmt_translator_get_context`` å·²è¢«åˆ é™¤ă€‚æ–°é©±å¨ä¸­ï¼Œç¿»è¯‘器更新为 RMT 译ç å™¨ă€‚ + - æ›´æ–°å， ``rmt_get_ringbuf_handle`` å·²è¢«åˆ é™¤ă€‚æ–°é©±å¨ç¨‹åºä¸å†ä½¿ç”¨ Ringbuffer æ¥ä¿å­˜ RMT 符å·ă€‚输入数æ®ä¼ç›´æ¥ä¿å­˜åˆ°ç”¨æˆ·æä¾›ç„缓冲区中，这些缓冲区ç”至å¯ä»¥ç›´æ¥è¢«æŒ‚载到 DMA 链æ¥å†…éƒ¨ă€‚ + - ``rmt_register_tx_end_callback`` 更新为 :cpp:func:`rmt_tx_register_event_callbacks`，用户å¯ä»¥åœ¨è¿™ä¸ªå‚数里é¢æ³¨å†Œäº‹ä»¶å›è°ƒå‡½æ•° :cpp:member:`rmt_tx_event_callbacks_t::on_trans_done`。 + - æ›´æ–°å， ``rmt_set_intr_enable_mask`` å’Œ ``rmt_clr_intr_enable_mask`` å·²è¢«åˆ é™¤ă€‚ç”±äºé©±å¨ç¨‹åºè´Ÿè´£å¤„ç†ä¸­æ–­ï¼Œå› æ­¤ç”¨æˆ·æ— éœ€è¿›è¡Œå¤„ç†ă€‚ + - ``rmt_add_channel_to_group`` å’Œ ``rmt_remove_channel_from_group`` 更新为 RMT åŒæ­¥ç®¡ç†å™¨ï¼Œè¯¦è§ :cpp:func:`rmt_new_sync_manager`。 + - æ›´æ–°å， ``rmt_set_tx_loop_count`` å·²è¢«åˆ é™¤ă€‚æ–°é©±å¨ä¸­ï¼Œå¾ªç¯è®¡æ•°åœ¨ :cpp:member:`rmt_transmit_config_t::loop_count` 进行é…ç½®ă€‚ + - æ›´æ–°å， ``rmt_enable_tx_loop_autostop`` å·²è¢«åˆ é™¤ă€‚æ–°é©±å¨ä¸­ï¼Œå‘射循ç¯è‡ªå¨ç»ˆæ­¢ä¸€ç›´ä½¿èƒ½ï¼Œç”¨æˆ·æ— æ³•è¿›è¡Œé…ç½®ă€‚ + +LCD +----- + +- LCD é¢æ¿ç„åˆå§‹åŒ–æµç¨‹ä¹Ÿæœ‰ä¸€äº›æ›´æ–°ă€‚æ›´æ–°å，:cpp:func:`esp_lcd_panel_init` ä¸å†ä¼è‡ªå¨æ‰“å¼€æ˜¾ç¤ºå™¨ă€‚ç”¨æˆ·éœ€è¦è°ƒç”¨ :cpp:func:`esp_lcd_panel_disp_on_off` æ¥æ‰‹å¨æ‰“å¼€æ˜¾ç¤ºå™¨ă€‚è¯·æ³¨æ„，打开显示器ä¸æ‰“开背光是ä¸åŒç„ă€‚æ›´æ–°å，打开å±å¹•å‰ï¼Œç”¨æˆ·å¯ä»¥çƒ§å½•ä¸€ä¸ªé¢„å®ä¹‰ç„图案，这å¯ä»¥é¿å…开机å¤ä½åå±å¹•ä¸ç„éæœºå™ªéŸ³ă€‚ +- æ›´æ–°å， :cpp:func:`esp_lcd_panel_disp_off` 已被弃用，请使用 :cpp:func:`esp_lcd_panel_disp_on_off` ä½œä¸ºæ›¿ä»£ă€‚ +- æ›´æ–°å， ``dc_as_cmd_phase`` 已被删除，SPI LCD 驱å¨ä¸å†æ”¯æŒ 9-bit ç„ SPI LCDă€‚è¯·ä½¿ç”¨ä¸“ç”¨ç„ GPIO 管è„æ¥æ§åˆ¶ LCD D/C çº¿ă€‚ +- æ›´æ–°å，用äºæ³¨å†Œ RGB é¢æ¿ç„事件å›è°ƒå‡½æ•°å·²ä» :cpp:type:`esp_lcd_rgb_panel_config_t` 更新为å•ç‹¬ç„ API :cpp:func:`esp_lcd_rgb_panel_register_event_callbacks`ă€‚ä½†æ˜¯ï¼Œäº‹ä»¶å›è°ƒç­¾åä»ä¿æŒä¸å˜ă€‚ +- æ›´æ–°å， :cpp:type:`esp_lcd_rgb_panel_config_t` 中ç„æ ‡å¿—ä½ ``relax_on_idle`` 被é‡å‘½å为 :cpp:member:`esp_lcd_rgb_panel_config_t::refresh_on_demand`，å者虽表达了åŒæ ·ç„å«ä¹‰ï¼Œä½†æ˜¯å…¶å‘½å更有æ„ä¹‰ă€‚ +- æ›´æ–°å，如æœåˆ›å»º RGB LCD æ—¶ï¼Œæ ‡å¿—ä½ ``refresh_on_demand`` 使能，驱å¨ä¸ä¼åœ¨ :cpp:func:`esp_lcd_panel_draw_bitmap` 中进行刷新，用户需è¦è°ƒç”¨ :cpp:func:`esp_lcd_rgb_panel_refresh` æ¥åˆ·æ–°å±å¹•ă€‚ +- æ›´æ–°å，:cpp:type:`esp_lcd_color_space_t` 已被弃用，请使用 :cpp:type:`lcd_color_space_t` æ¥æ述色彩空间，使用 :cpp:type:`lcd_color_rgb_endian_t` æ¥æè¿° RGB 颜色ç„æ’列顺åºă€‚ + +.. only:: SOC_MCPWM_SUPPORTED + + MCPWM + ----- + + MCPWM 驱å¨å·²æ›´æ–°ï¼ˆè¯¦è§ :doc:`MCPWM <../../api-reference/peripherals/mcpwm>`ï¼‰ă€‚åŒæ—¶ï¼Œæ—§ç‰ˆé©±å¨å·²è¢«å¼ƒç”¨ă€‚ + + 新驱å¨ä¸­ï¼Œæ¯ä¸ª MCPWM å­æ¨¡å—相互独立，用户å¯ä»¥è‡ªç”±è¿›è¡Œèµ„æºè¿æ¥ă€‚ + + 尽管我们æ¨è使用新ç„é©±å¨ API，旧版驱å¨ä»ç„¶å¯ç”¨ï¼Œå…¶å¼•ç”¨è·¯å¾„为 ``driver/mcpwm.h``ă€‚ä½†æ˜¯ï¼Œä½¿ç”¨æ—§ç‰ˆé©±å¨ä¼é»˜è®¤è§¦å‘如下编译警å‘，å¯ä»¥é€è¿‡é…ç½® Kconfig 选项 :ref:`CONFIG_MCPWM_SUPPRESS_DEPRECATE_WARN` æ¥å…³é—­è¯¥è­¦å‘。 + + .. code-block:: text + + legacy MCPWM driver is deprecated, please migrate to the new driver (include driver/mcpwm_prelude.h) + + 主è¦æ¦‚念和使用方法ä¸ç„æ›´æ–°å¦‚ä¸‹æ‰€ç¤ºï¼ + + 主è¦æ¦‚念更新 + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + æ›´æ–°å，MCPWM 驱å¨æ˜¯é¢å‘对象ç„，大å¤æ•° MCPWM å­æ¨¡å—都有一个ä¸ä¹‹ç›¸å…³ç„驱å¨å¯¹è±¡ă€‚驱å¨å¯¹è±¡æ˜¯ç”±å·¥å‚函数创建ç„，如 :cpp:func:`mcpwm_new_timer`。IO æ§åˆ¶å‡½æ•°æ€»æ˜¯éœ€è¦å¯¹è±¡å¥æŸ„。 + + 旧版驱å¨æœ‰ä¸€ä¸ªä¸æ°å½“ç„å‡è®¾ï¼Œå³ MCPWM è¿ç®—器应è¿æ¥åˆ°ä¸åŒç„ MCPWM å®æ—¶å™¨ä¸ă€‚但是，硬件ä¸å¹¶æ²¡æœ‰è¿™æ ·ç„é™åˆ¶ă€‚新驱å¨ä¸­ï¼ŒåŒä¸€ä¸ª MCPWM å®æ—¶å™¨å¯ä»¥è¿æ¥å¤ä¸ªè¿ç®—器，这样è¿ç®—器å¯ä»¥è·å¾—最佳ç„åŒæ­¥æ€§èƒ½ă€‚ + + æ›´æ–°å‰ï¼Œé©±å¨å°†ç”Ÿæˆ PWM 波形ç„æ–¹æ³•é¢„è®¾ä¸ºæ‰€è°“ç„ ``mcpwm_duty_type_t``，但是，列出ç„å ç©ºæ¯”模å¼è¿œè¿œä¸å¤Ÿă€‚类似ç„，旧版驱å¨æœ‰ä¸€äº›é¢„è®¾ç„ ``mcpwm_deadtime_type_t`` 也没有包å«æ‰€æœ‰ç„ä½¿ç”¨åœºæ™¯ă€‚æ›´é‡è¦ç„是，用户é€å¸¸ä¼è¢«å ç©ºæ¯”模å¼å’Œæ­»åŒºæ—¶é—´æ¨¡å¼ç„åç§°æ‰€è¿·æƒ‘ă€‚æ›´æ–°å，驱å¨æ²¡æœ‰è¿™äº›é™åˆ¶ï¼Œä½†æ˜¯ç”¨æˆ·å¿…é¡»ä»å¤´å¼€å§‹æ„建å‘生器ç„è¡Œä¸ºă€‚ + + 在旧版驱å¨ä¸­ï¼Œé€è¿‡ GPIO 管è„，软件和其他å®æ—¶å™¨æ¨¡å—åŒæ­¥ MCPWM å®æ—¶å™¨ç„方法并ä¸ç»Ÿä¸€ă€‚è¿™å¢å äº†ç”¨æˆ·ç„学习æˆæœ¬ï¼Œå› æ­¤æ–°é©±å¨ç»Ÿä¸€äº†åŒæ­¥ API。 + + 旧版驱å¨æ··æ·†äº†â€œæ•…éœæ£€æµ‹å™¨â€å’Œâ€œæ•…éœå¤„ç†å™¨â€ç„æ¦‚å¿µă€‚è¿™è®©ç”¨æˆ·å¯¹ API 感到éå¸¸å›°æƒ‘ă€‚æ–°é©±å¨ä¸­ï¼Œæ•…éœå¯¹è±¡åªä»£è¡¨ä¸€ä¸ªæ•…éœæºï¼Œè€Œä¸”我们引入了一个新概念， **制å¨å™¨**，æ¥è¡¨ç¤ºæ•…éœå¤„ç†å™¨ă€‚而且，新驱å¨æ”¯æŒè½¯ä»¶æ•…éœă€‚ + + 旧版驱å¨åªä¸ºè·å–å­æ¨¡å—æ供了å›è°ƒå‡½æ•°ï¼Œè€Œæ–°é©±å¨ä¸º MCPWM å­æ¨¡å—æä¾›å¤ç§å›è°ƒå‡½æ•°ï¼Œå¦‚åœæ­¢å®æ—¶å™¨ï¼Œæ¯”较匹é…，故éœè¿›å…¥ï¼Œç´§æ€¥åœæ­¢ç­‰ă€‚ + + - æ›´æ–°å，ä¸å†ä½¿ç”¨ ``mcpwm_io_signals_t`` å’Œ ``mcpwm_pin_config_t``， GPIO 管è„é…置被移至å­æ¨¡å—ç„é…置结æ„中。 + - æ›´æ–°å，ä¸å†ä½¿ç”¨ ``mcpwm_timer_t`` å’Œ ``mcpwm_generator_t``，å®æ—¶å™¨å’Œå‘生器分别用 :cpp:type:`mcpwm_timer_handle_t` å’Œ:cpp:type:`mcpwm_gen_handle_t` è¡¨ç¤ºă€‚ + - æ›´æ–°å，ä¸å†ä½¿ç”¨ ``mcpwm_fault_signal_t`` å’Œ ``mcpwm_sync_signal_t``，故éœå’ŒåŒæ­¥æºåˆ†åˆ«ç”¨ :cpp:type:`mcpwm_fault_handle_t` å’Œ:cpp:type:`mcpwm_sync_handle_t` è¡¨ç¤ºă€‚ + - æ›´æ–°å，ä¸å†ä½¿ç”¨ ``mcpwm_capture_signal_t``，è·å–é€é“用 :cpp:type:`mcpwm_cap_channel_handle_t` è¡¨ç¤ºă€‚ + + 主è¦ä½¿ç”¨æ–¹æ³•æ›´æ–° + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + - ``mcpwm_gpio_init`` å’Œ ``mcpwm_set_pin``ï¼GPIO 管è„é…置在å­æ¨¡å—é…置中完æˆï¼Œä¾‹å¦‚在 :cpp:member:`mcpwm_generator_config_t::gen_gpio_num` 中设置 PWM GPIO 管è„。 + - ``mcpwm_init``ï¼ä¸ºå¾—åˆ°é¢„æœŸç„ PWM 波形，用户需è¦è‡³å°‘分é…一个 MCPWM å®æ—¶å™¨å’Œ MCPWM è¿ç®—器，然åé€è¿‡è°ƒç”¨ :cpp:func:`mcpwm_operator_connect_timer` 将二者è¿æ¥èµ·æ¥ă€‚然å，用户需è¦è°ƒç”¨å¦‚:cpp:func:`mcpwm_generator_set_actions_on_timer_event`， :cpp:func:`mcpwm_generator_set_actions_on_compare_event` æ¥è®¾ç½®å‘生器对ä¸åŒäº‹ä»¶ç„å¨ä½œă€‚ + - ``mcpwm_group_set_resolution``ï¼æ–°é©±å¨ä¸­ï¼Œç¾¤ç»„分辨ç‡å›ºå®ä¸ºæœ€å¤§å€¼ï¼Œé€å¸¸ä¸º 80 MHz。 + - ``mcpwm_timer_set_resolution``ï¼MCPWM å®æ—¶å™¨ç„分辨ç‡åœ¨ :cpp:member:`mcpwm_timer_config_t::resolution_hz` ä¸­è¿›è¡Œè®¾ç½®ă€‚ + - ``mcpwm_set_frequency``ï¼PWM 频ç‡ç”± :cpp:member:`mcpwm_timer_config_t::resolution_hz` ，:cpp:member:`mcpwm_timer_config_t::count_mode` å’Œ:cpp:member:`mcpwm_timer_config_t::period_ticks` 决å®ă€‚ + - ``mcpwm_set_duty``ï¼ä¸ºè®¾ç½® PWM å ç©ºæ¯”，用户应调用 :cpp:func:`mcpwm_comparator_set_compare_value` æ¥æ”¹å˜æ¯”较器ç„é˜ˆå€¼ă€‚ + - ``mcpwm_set_duty_type``ï¼æ–°é©±å¨ä¸­æ²¡æœ‰é¢„设ç„å ç©ºæ¯”模å¼ï¼Œé€è¿‡è®¾ç½®ä¸åŒç„å‘生器行为，如 :cpp:func:`mcpwm_generator_set_actions_on_timer_event`，æ¥é…ç½®å ç©ºæ¯”模å¼ă€‚ + - ``mcpwm_set_signal_high`` å’Œ ``mcpwm_set_signal_low`` 更新为 :cpp:func:`mcpwm_generator_set_force_level`ă€‚æ–°é©±å¨ä¸­ï¼Œè¿™æ˜¯é€è¿‡ä¸ºå‘生器设置å›ä½œç”¨æ¥å®ç°ç„，而ä¸æ˜¯åœ¨åå°å°†å ç©ºæ¯”改为 0% 或 100%。 + - ``mcpwm_start`` å’Œ ``mcpwm_stop`` 更新为 :cpp:func:`mcpwm_timer_start_stop`ă€‚ç”¨æˆ·å¯ä»¥ç”¨æ›´å¤ç„模å¼æ¥å¯å¨å’Œåœæ­¢ MCPWM å®æ—¶å™¨ï¼Œè¯¦è§ :cpp:type:`mcpwm_timer_start_stop_cmd_t`。 + - ``mcpwm_carrier_init`` 更新为 :cpp:func:`mcpwm_operator_apply_carrier`。 + - ``mcpwm_carrier_enable`` ä¸ ``mcpwm_carrier_disable``ï¼é€è¿‡æ£€æŸ¥è½½æ³¢è®¾ç½®ç»“æ„ :cpp:type:`mcpwm_carrier_config_t` 是å¦ä¸ºç©ºé›†æ¥è‡ªå¨ä½¿èƒ½å’Œåœç”¨è½½æ³¢å­æ¨¡å—。 + - ``mcpwm_carrier_set_period`` 更新为 :cpp:member:`mcpwm_carrier_config_t::frequency_hz`。 + - ``mcpwm_carrier_set_duty_cycle`` 更新为 :cpp:member:`mcpwm_carrier_config_t::duty_cycle`。 + - ``mcpwm_carrier_oneshot_mode_enable`` 更新为 :cpp:member:`mcpwm_carrier_config_t::first_pulse_duration_us`。 + - æ›´æ–°å， ``mcpwm_carrier_oneshot_mode_disable`` è¢«åˆ é™¤ă€‚ç¡¬ä»¶ä¸æ”¯æŒåœç”¨ç¬¬ä¸€ä¸ªè½½æ³¢è„‰å†²ï¼ˆå³ä¸€æ¬¡æ€§è„‰å†²ï¼‰ă€‚ + - ``mcpwm_carrier_output_invert`` 更新为 :cpp:member:`mcpwm_carrier_config_t::invert_before_modulate` å’Œ :cpp:member:`mcpwm_carrier_config_t::invert_after_modulate`。 + - ``mcpwm_deadtime_enable`` ä¸ ``mcpwm_deadtime_disable`` 更新为 :cpp:func:`mcpwm_generator_set_dead_time`。 + - ``mcpwm_fault_init`` 更新为 :cpp:func:`mcpwm_new_gpio_fault`。 + - ``mcpwm_fault_set_oneshot_mode`` ä¸ ``mcpwm_fault_set_cyc_mode`` 更新为 :cpp:func:`mcpwm_operator_set_brake_on_fault` ä¸ :cpp:func:`mcpwm_generator_set_actions_on_brake_event`。 + - ç”±äº ``mcpwm_capture_enable`` ä¸ :cpp:func:`mcpwm_capture_enable_channel` é‡å¤ï¼Œå› æ­¤åœ¨æ›´æ–°åè¢«åˆ é™¤ă€‚ + - ç”±äº ``mcpwm_capture_disable`` ä¸ :cpp:func:`mcpwm_capture_capture_disable_channel` é‡å¤ï¼Œå› æ­¤åœ¨æ›´æ–°åè¢«åˆ é™¤ă€‚ + - ``mcpwm_capture_enable_channel`` ä¸ ``mcpwm_capture_disable_channel`` 更新为 :cpp:func:`mcpwm_capture_channel_enable` ä¸ :cpp:func:`mcpwm_capture_channel_disable`。 + - ``mcpwm_capture_signal_get_value`` ä¸ ``mcpwm_capture_signal_get_edge``ï¼é€è¿‡ :cpp:type:`mcpwm_capture_event_data_t`，è·å–事件å›è°ƒå‡½æ•°ä¸­æ供了计时器ç„æ•°å€¼å’Œè¾¹ç¼˜ç”µå¹³ă€‚åªæœ‰è·å–事件å‘生时，è·å–æ•°æ®æ‰æœ‰æ„义，æä¾›å•ä¸€ç„ API æ¥è·å–æ•è·æ•°æ®æ˜¯æ²¡æœ‰æ„义ç„。 + - ç”±äº ``mcpwm_sync_enable`` ä¸ :cpp:func:`mcpwm_sync_configure` é‡å¤ï¼Œå› æ­¤æ›´æ–°åè¢«åˆ é™¤ă€‚ + - ``mcpwm_sync_configure`` 更新为 :cpp:func:`mcpwm_timer_set_phase_on_sync`。 + - ``mcpwm_sync_disable`` 相当äºå°† :cpp:member:`mcpwm_timer_sync_phase_config_t::sync_src` 设置为 ``NULL``。 + - ``mcpwm_set_timer_sync_output`` 更新为 :cpp:func:`mcpwm_new_timer_sync_src`。 + - ``mcpwm_timer_trigger_soft_sync`` 更新为 :cpp:func:`mcpwm_soft_sync_activate`。 + - ``mcpwm_sync_invert_gpio_synchro`` ä¸è®¾ç½® :cpp:member:`mcpwm_gpio_sync_src_config_t::active_neg` åŸèƒ½ç›¸åŒă€‚ + - æ›´æ–°å， ``mcpwm_isr_register`` å·²è¢«åˆ é™¤ă€‚ç”¨æˆ·å¯ä»¥æ³¨å†Œä¸åŒç„事件å›è°ƒå‡½æ•°æ¥æ›¿ä»£å…¶åŸèƒ½ï¼Œä¾‹å¦‚，å¯ä»¥ä½¿ç”¨ :cpp:func:`mcpwm_capture_channel_register_event_callbacks` 注册è·å–äº‹ä»¶æ³¨å†Œå‡½æ•°ă€‚ + +.. only:: SOC_DEDICATED_GPIO_SUPPORTED + + ä¸“ç”¨ç„ GPIO é©±å¨ + ------------------------------------- + + - æ›´æ–°å，所有ä¸ä¸“用 GPIO 管è„相关ç„底层 (LL) å‡½æ•°ä» ``cpu_ll.h`` 中被移至 ``dedic_gpio_cpu_ll.h``，并é‡æ–°å‘½å。 + +.. only:: SOC_I2S_SUPPORTED + + I2S é©±å¨ + ----------------------- + + 旧版 I2S 驱å¨åœ¨æ”¯æŒ ESP32-C3 å’Œ ESP32-S3 æ–°åŸèƒ½æ—¶æ´éœ²äº†å¾ˆå¤ç¼ºç‚¹ï¼Œä¸ºè§£å†³è¿™äº›ç¼ºç‚¹ï¼ŒI2S 驱å¨å·²æ›´æ–°ï¼ˆè¯·å‚考:doc:`I2S Driver <../../api-reference/peripherals/i2s>`ï¼‰ă€‚ç”¨æˆ·å¯ä»¥é€è¿‡å¼•ç”¨ä¸åŒ I2S 模å¼å¯¹åº”ç„头文件æ¥ä½¿ç”¨æ–°ç‰ˆé©±å¨ç„ API，如 :component_file:`driver/include/driver/i2s_std.h`， :component_file:`driver/include/driver/i2s_pdm.h` 以å :component_file:`driver/include/driver/i2s_tdm.h`。 + + 为ä¿è¯å‰å‘兼容，旧版驱å¨ç„ API ä»ç„¶åœ¨ :component_file:`driver/deprecated/driver/i2s.h` 中å¯ç”¨ă€‚但使用旧版 API ä¼è§¦å‘编译警å‘，该警å‘å¯é€è¿‡é…ç½® Kconfig 选项 :ref:`CONFIG_I2S_SUPPRESS_DEPRECATE_WARN` æ¥å…³é—­ă€‚ + + 以下是更新åç„ I2S æ–‡ä»¶æ¦‚å†µă€‚ + + .. figure:: ../../../_static/diagrams/i2s/i2s_file_structure.png + :align: center + :alt: I2S File Structure + + 主è¦æ¦‚念更新 + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + 独立ç„å‘é€é€é“å’Œæ¥æ”¶é€é“ + """""""""""""""""""""""""""""""""""""""""""""""""""""""" + + æ›´æ–°å，I2S 驱å¨ç„最å°æ§åˆ¶å•å…ƒæ˜¯å‘é€/æ¥æ”¶é€é“，而ä¸æ˜¯æ•´ä¸ª I2S æ§åˆ¶å™¨ï¼ˆæ§åˆ¶å™¨åŒ…括å¤ä¸ªé€é“ï¼‰ă€‚ + + - 用户å¯ä»¥åˆ†åˆ«æ§åˆ¶åŒä¸€ä¸ª I2S æ§åˆ¶å™¨ç„å‘é€é€é“å’Œæ¥æ”¶é€é“，å³å¯ä»¥é€è¿‡é…ç½®å®ç°åˆ†åˆ«å¼€å¯å’Œå…³é—­å‘é€é€é“å’Œæ¥æ”¶é€é“。 + - :c:type:`i2s_chan_handle_t` å¥æŸ„ç±»å‹ç”¨äºå”¯ä¸€åœ°è¯†åˆ« I2S é€é“ă€‚æ‰€æœ‰ç„ API 都需è¦è¯¥é€é“å¥æŸ„，用户需è¦å¯¹è¿™äº›é€é“å¥æŸ„进行维æ¤ă€‚ + - å¯¹äº ESP32-C3 å’Œ ESP32-S3，åŒä¸€ä¸ªæ§åˆ¶å™¨ä¸­ç„å‘é€é€é“å’Œæ¥æ”¶é€é“å¯ä»¥é…置为ä¸åŒç„时钟或ä¸åŒç„模å¼ă€‚ + - ä½†æ˜¯å¯¹äº ESP32 å’Œ ESP32-S2， åŒä¸€ä¸ªæ§åˆ¶å™¨ä¸­ç„å‘é€é€é“å’Œæ¥æ”¶é€é“共享æŸäº›ç¡¬ä»¶èµ„æºă€‚因此，é…ç½®å¯èƒ½ä¼é€ æˆä¸€ä¸ªé€é“å½±å“åŒä¸€ä¸ªæ§åˆ¶å™¨ä¸­ç„å¦ä¸€ä¸ªé€é“。 + - é€è¿‡å°† :cpp:enumerator:`i2s_port_t::I2S_NUM_AUTO` 设置为 I2S ç«¯å£ ID，驱å¨ä¼æœç´¢å¯ç”¨ç„å‘é€/æ¥æ”¶é€é“，之åé€é“ä¼è¢«è‡ªå¨æ³¨å†Œåˆ°å¯ç”¨ç„ I2S æ§åˆ¶å™¨ä¸ă€‚但是，驱å¨ä»ç„¶æ”¯æŒå°†é€é“注册到一个特å®ç„端å£ä¸ă€‚ + - 为区分å‘é€/æ¥æ”¶é€é“和声音é€é“，在更新åç„驱å¨ä¸­ï¼Œâ€œé€é“ (channel)â€ä¸€è¯ä»…代表å‘é€/æ¥æ”¶é€é“ï¼Œç”¨â€œå£°é“ (slot)â€æ¥è¡¨ç¤ºå£°éŸ³é€é“。 + + I2S 模å¼åˆ†ç±» + """""""""""""""""""""""""""""""" + + I2S é€ä¿¡æ¨¡å¼åŒ…括以下三ç§æ¨¡å¼ï¼Œè¯·æ³¨æ„ï¼ + + - **标准模å¼**ï¼æ ‡å‡†æ¨¡å¼é€å¸¸åŒ…括两个声é“ï¼Œæ”¯æŒ Philip，MSB å’Œ PCM（短帧åŒæ­¥ï¼‰æ ¼å¼ï¼Œè¯¦è§ :component_file:`driver/include/driver/i2s_std.h`。 + - **PDM模å¼**ï¼PDM 模å¼ä»…支æŒä¸¤ä¸ªå£°é“，16 bit æ•°æ®ä½å®½ï¼Œä½†æ˜¯ PDM TX å’Œ PDM RX ç„é…置略有ä¸åŒă€‚å¯¹äº PDM TX，采样ç‡å¯é€è¿‡ :cpp:member:`i2s_pdm_tx_clk_config_t::sample_rate` 进行设置，其时钟频ç‡å–决äºä¸é‡‡æ ·ç„é…ç½®ă€‚å¯¹äº PDM RX，采样ç‡å¯é€è¿‡ :cpp:member:`i2s_pdm_rx_clk_config_t::sample_rate` 进行设置，其时钟频ç‡å–决äºä¸‹é‡‡æ ·ç„é…ç½®ï¼Œè¯¦è§ :component_file:`driver/include/driver/i2s_pdm.h`。 + - **TDM 模å¼**ï¼TDM 模å¼å¯æ”¯æŒé«˜è¾¾ 16 声é“，该模å¼å¯å·¥ä½œåœ¨ Philip，MSB，PCM（短帧åŒæ­¥ï¼‰å’ŒPCM（长帧åŒæ­¥ï¼‰æ ¼å¼ä¸‹ï¼Œè¯¦è§ :component_file:`driver/include/driver/i2s_tdm.h`。 + + 在æŸä¸ªæ¨¡å¼ä¸‹åˆ†é…æ–°é€é“时，必须é€è¿‡ç›¸åº”ç„函数åˆå§‹åŒ–这个é€é“ă€‚æˆ‘ä»¬å¼ºçƒˆå»ºè®®ä½¿ç”¨è¾…å©å®æ¥ç”Ÿæˆé»˜è®¤é…置，以é¿å…默认值被改å¨ă€‚ + + 独立ç„声é“é…置和时钟é…ç½® + """""""""""""""""""""""""""""""""""""""""""""""""""" + + å¯ä»¥å•ç‹¬è¿›è¡Œå£°é“é…置和时钟é…ç½®ă€‚ + + - é€è¿‡è°ƒç”¨ :cpp:func:`i2s_channel_init_std_mode`， :cpp:func:`i2s_channel_init_pdm_rx_mode`， :cpp:func:`i2s_channel_init_pdm_tx_mode` 或:cpp:func:`i2s_channel_init_tdm_mode` åˆå§‹åŒ–声é“/时钟/GPIO 管è„é…ç½®ă€‚ + - é€è¿‡è°ƒç”¨ :cpp:func:`i2s_channel_reconfig_std_slot`， :cpp:func:`i2s_channel_reconfig_pdm_rx_slot`， :cpp:func:`i2s_channel_reconfig_pdm_tx_slot` 或 :cpp:func:`i2s_channel_reconfig_tdm_slot` å¯ä»¥åœ¨åˆå§‹åŒ–之å改å˜å£°é“é…ç½®ă€‚ + - é€è¿‡è°ƒç”¨ :cpp:func:`i2s_channel_reconfig_std_clock`， :cpp:func:`i2s_channel_reconfig_pdm_rx_clock`， :cpp:func:`i2s_channel_reconfig_pdm_tx_clock` 或 :cpp:func:`i2s_channel_reconfig_tdm_clock` å¯ä»¥åœ¨åˆå§‹åŒ–之å改å˜æ—¶é’Ÿé…ç½®ă€‚ + - é€è¿‡è°ƒç”¨ :cpp:func:`i2s_channel_reconfig_std_gpio`， :cpp:func:`i2s_channel_reconfig_pdm_rx_gpio`， :cpp:func:`i2s_channel_reconfig_pdm_tx_gpio` 或 :cpp:func:`i2s_channel_reconfig_tdm_gpio` å¯ä»¥åœ¨åˆå§‹åŒ–之åæ”¹å˜ GPIO 管è„é…ç½®ă€‚ + + Misc + """" + + - æ›´æ–°å，I2S 驱å¨åˆ©ç”¨ç¶æ€å’Œç¶æ€æœºé¿å…在错误ç¶æ€ä¸‹è°ƒç”¨ API。 + - æ›´æ–°å，ADC å’Œ DAC 模å¼å·²è¢«åˆ é™¤ï¼Œåªæœ‰å®ƒä»¬å„自专用ç„驱å¨å I2S 旧版驱å¨è¿˜æ”¯æŒè¿™ä¸¤ç§æ¨¡å¼ă€‚ + + 主è¦ä½¿ç”¨æ–¹æ³•æ›´æ–° + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + 请å‚考以下步骤使用更新åç„ I2S 驱å¨ï¼ + + 1. é€è¿‡è°ƒç”¨ :cpp:func:`i2s_new_channel` æ¥è·å–é€é“å¥æŸ„ă€‚æˆ‘ä»¬åº”è¯¥åœ¨æ­¤æ­¥éª¤ä¸­æŒ‡å®å¤–设为主机还是ä»æœºä»¥å I2S 端å£ă€‚此外，驱å¨è´Ÿè´£ç”Ÿæˆå‘é€é€é“或æ¥æ”¶é€é“ç„å¥æŸ„。ä¸éœ€è¦åŒæ—¶è¾“å…¥å‘é€é€é“å’Œæ¥æ”¶é€é“å¥æŸ„，但需è¦è¾“入至少一个å¥æŸ„ă€‚è¾“å…¥ä¸¤ä¸ªå¥æŸ„时，驱å¨ä¼å·¥ä½œåœ¨åŒå·¥æ¨¡å¼ă€‚在åŒä¸€ç«¯å£ä¸ï¼Œå‘é€é€é“å’Œæ¥æ”¶é€é“åŒæ—¶å¯ç”¨ï¼Œå¹¶ä¸”共享 MCLK，BCLK å’Œ WS ä¿¡å·ă€‚如æœåªè¾“入了å‘é€é€é“å¥æŸ„或æ¥æ”¶é€é“å¥æŸ„，该é€é“åªèƒ½å·¥ä½œåœ¨å•å·¥æ¨¡å¼ă€‚ + 2. é€è¿‡è°ƒç”¨ :func:`i2s_channel_init_std_mode`， :func:`i2s_channel_init_pdm_rx_mode`， :func:`i2s_channel_init_pdm_tx_mode` 或 :func:`i2s_channel_init_tdm_mode` å°†é€é“åˆå§‹åŒ–为指å®æ¨¡å¼ă€‚进行相应ç„声é“ă€æ—¶é’Ÿå’Œ GPIO 管è„é…ç½®ă€‚ + 3. （å¯é€‰ï¼‰é€è¿‡è°ƒç”¨ :cpp:func:`i2s_channel_register_event_callback` 注册 ISR 事件å›è°ƒå‡½æ•°ă€‚I2S 事件由å›è°ƒå‡½æ•°åŒæ­¥æ¥æ”¶ï¼Œè€Œä¸æ˜¯ä»äº‹ä»¶é˜Ÿåˆ—中异步æ¥æ”¶ă€‚ + 4. é€è¿‡è°ƒç”¨ :cpp:func:`i2s_channel_enable` æ¥å¼€å¯ I2S é€é“ç„硬件资æºă€‚在更新åç„驱å¨ä¸­ï¼ŒI2S 在安装åä¸ä¼å†è‡ªå¨å¼€å¯ï¼Œç”¨æˆ·éœ€è¦ç¡®å®é€é“是å¦å·²ç»å¼€å¯ă€‚ + 5. 分别é€è¿‡ :cpp:func:`i2s_channel_read` å’Œ :cpp:func:`i2s_channel_write` æ¥è¯»å–和写入数æ®ă€‚当然，在 :cpp:func:`i2s_channel_read` 中åªèƒ½è¾“å…¥æ¥æ”¶é€é“å¥æŸ„，在 :cpp:func:`i2s_channel_write` 中åªèƒ½è¾“å…¥å‘é€é€é“å¥æŸ„。 + 6. （å¯é€‰ï¼‰é€è¿‡ç›¸åº”ç„ 'reconfig' 函数å¯ä»¥æ›´æ”¹å£°é“ă€æ—¶é’Ÿå’Œ GPIO 管è„é…置，但是更改é…ç½®å‰å¿…须调用 :cpp:func:`i2s_channel_disable`。 + 7. é€è¿‡è°ƒç”¨ :cpp:func:`i2s_channel_disable` å¯ä»¥åœæ­¢ä½¿ç”¨ I2S é€é“ç„硬件资æºă€‚ + 8. ä¸å†ä½¿ç”¨æŸé€é“时，é€è¿‡è°ƒç”¨ :cpp:func:`i2s_del_channel` å¯ä»¥åˆ é™¤å’Œé‡æ”¾è¯¥é€é“资æºï¼Œä½†æ˜¯åˆ é™¤ä¹‹å‰å¿…须先åœç”¨è¯¥é€é“。 + +用äºè®¿é—®å¯„存器ç„å® +--------------------------------------------- + +æ›´æ–°å‰ï¼Œæ‰€æœ‰ç”¨äºè®¿é—®å¯„存器ç„å®éƒ½å¯ä»¥ä½œä¸ºè¡¨è¾¾å¼æ¥ä½¿ç”¨ï¼Œæ‰€ä»¥ä»¥ä¸‹å‘½ä»¤æ˜¯å…许ç„:: + + uint32_t val = REG_SET_BITS(reg, mask); + +在 ESP-IDF v5.0 中，用äºå†™å…¥æˆ–读å–-修改-写入寄存器ç„å®ä¸èƒ½å†ä½œä¸ºè¡¨è¾¾å¼ä½¿ç”¨ï¼Œè€Œåªèƒ½ä½œä¸ºè¯­å¥ä½¿ç”¨ï¼Œè¿™é€‚用äºä»¥ä¸‹å®ï¼ ``REG_WRITE``， ``REG_SET_BIT``， ``REG_CLR_BIT``， ``REG_SET_BITS``， ``REG_SET_FIELD``， ``WRITE_PERI_REG``， ``CLEAR_PERI_REG_MASK``， ``SET_PERI_REG_MASK``， ``SET_PERI_REG_BITS``。 + +为存储è¦å†™å…¥å¯„存器ç„值，请按以下步骤完æˆæ“作:: + + uint32_t new_val = REG_READ(reg) | mask; + REG_WRITE(reg, new_val); + +è¦è·å¾—修改åç„寄存器ç„值（该值å¯èƒ½ä¸å†™å…¥ç„值ä¸åŒï¼‰ï¼Œè¦å¢å ä¸€ä¸ªæ˜¾ç¤ºç„读å–命令:: + + REG_SET_BITS(reg, mask); + uint32_t new_val = REG_READ(reg); \ No newline at end of file diff --git a/docs/zh_CN/migration-guides/release-5.x/protocols.rst b/docs/zh_CN/migration-guides/release-5.x/protocols.rst index 47b0509019..87bcec3621 100644 --- a/docs/zh_CN/migration-guides/release-5.x/protocols.rst +++ b/docs/zh_CN/migration-guides/release-5.x/protocols.rst @@ -1 +1,205 @@ -.. include:: ../../../en/migration-guides/release-5.x/protocols.rst +åè®® +========= + +:link_to_translation:`en:[English]` + +.. _migration_guide_mbedtls: + +Mbed TLS +-------- + +在 ESP-IDF v5.0 版本中，`Mbed TLS `_ å·²ä» v2.x 版本更新到 v3.1.0 ç‰ˆæœ¬ă€‚ + +æ›´å¤æœ‰å…³ Mbed TLS ä» v2.x 版本è¿ç§»åˆ° v3.0 或更高版本ç„详细信æ¯ï¼Œè¯·å‚考 `å®˜æ–¹æŒ‡å— `__。 + +é‡å¤§æ›´æ–°ï¼ˆæ¦‚述） +~~~~~~~~~~~~~~~~~~~~ + +å¢å ç§æœ‰ç»“æ„ä½“å­—æ®µæ•°é‡ +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- ä¸å†æ”¯æŒç›´æ¥è®¿é—®å…¬å…±å¤´æ–‡ä»¶ä¸­å£°æ˜ç„结æ„体（ ``struct`` ç±»å‹ï¼‰å­—æ®µă€‚ +- 当å‰ç‰ˆæœ¬ä¸‹ï¼Œè®¿é—®å…¬å…±å¤´æ–‡ä»¶ä¸­å£°æ˜ç„结æ„体字段需è¦ä½¿ç”¨ç‰¹å®ç„访问函数 (getter/setter)。å¦å¤–，也å¯ä»¥ç”¨ ``MBEDTLS_PRIVATE`` å®æ‚时代替，但ä¸å»ºè®®ä½¿ç”¨æ­¤ç§æ–¹æ³•ă€‚ +- æ›´å¤è¯¦ç»†ä¿¡æ¯ï¼Œè¯·å‚考 `å®˜æ–¹æŒ‡å— `__。 + + +SSL +^^^ +- ä¸å†æ”¯æŒ TLS 1.0ă€TLS 1.1 å’Œ DTLS 1.0 +- ä¸å†æ”¯æŒ SSL 3.0 + +移除密ç æ¨¡å—中ç„废弃函数 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- æ›´æ–°äº†ä¸ MDă€SHAă€RIPEMDă€RNGă€HMAC 模å—相关ç„函数 ``mbedtls_*_ret()`` ç„è¿”å›å€¼ï¼Œå¹¶å°†å…¶é‡æ–°å‘½å，以å–ä»£æœªé™„å  ``_ret`` ç„ç›¸åº”å‡½æ•°ă€‚ +- æ›´å¤è¯¦ç»†ä¿¡æ¯ï¼Œè¯·å‚考 `å®˜æ–¹æŒ‡å— `__。 + + +废弃é…置选项 +^^^^^^^^^^^^^^^^^^^^^^^^^ +下列为在此次更新中废弃ç„é‡è¦é…ç½®é€‰é¡¹ă€‚ä¸ä»¥ä¸‹é…置有关或是ä¾èµ–äºä¸‹åˆ—é…ç½®ç„相关é…ç½®ä¹Ÿå·²ç›¸åº”åºŸå¼ƒă€‚ + +- ``MBEDTLS_SSL_PROTO_SSL3``ï¼åŸç”¨äºæ”¯æŒ SSL 3.0 +- ``MBEDTLS_SSL_PROTO_TLS1``ï¼åŸç”¨äºæ”¯æŒ TLS 1.0 +- ``MBEDTLS_SSL_PROTO_TLS1_1``ï¼åŸç”¨äºæ”¯æŒ TLS 1.1 +- ``MBEDTLS_SSL_PROTO_DTLS``ï¼åŸç”¨äºæ”¯æŒ DTLS 1.1（当å‰ç‰ˆæœ¬ä»…æ”¯æŒ DTLS 1.2） +- ``MBEDTLS_DES_C``ï¼åŸç”¨äºæ”¯æŒ 3DES 密ç å¥—件 +- ``MBEDTLS_RC4_MODE``ï¼åŸç”¨äºæ”¯æŒåŸºäº RC4 ç„密ç å¥—件 + +.. note:: ä¸è¿°ä»…列出了å¯é€è¿‡ ``idf.py menuconfig`` é…ç½®ç„主è¦é€‰é¡¹ă€‚æ›´å¤æœ‰å…³åºŸå¼ƒé€‰é¡¹ç„ä¿¡æ¯ï¼Œè¯·å‚考 `å®˜æ–¹æŒ‡å— `__。 + + +其他更新 +------------- + +ç¦ç”¨ Diffie-Hellman 密ç äº¤æ¢æ¨¡å¼ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +为é¿å… `安全é£é™© `__，当å‰ç‰ˆæœ¬å·²é»˜è®¤ç¦ç”¨ Diffie-Hellman 密ç äº¤æ¢æ¨¡å¼ă€‚以下为相应ç„ç¦ç”¨é…ç½®é¡¹ï¼ + +- ``MBEDTLS_DHM_C``ï¼åŸç”¨äºæ”¯æŒ Diffie-Hellman-Merkle æ¨¡å— +- ``MBEDTLS_KEY_EXCHANGE_DHE_PSK``ï¼åŸç”¨äºæ”¯æŒ Diffie-Hellman 预共享密钥 (PSK) TLS 认è¯æ¨¡å¼ +- ``MBEDTLS_KEY_EXCHANGE_DHE_RSA``ï¼åŸç”¨äºæ”¯æŒå¸¦æœ‰å‰ç¼€ç„密ç å¥—件 ``TLS-DHE-RSA-WITH-`` + +.. note:: 在信å·äº¤æ¢ç„åˆå§‹æ­¥éª¤ï¼ˆå³ ``client_hello``）中，æœå¡å™¨ä¼åœ¨å®¢æˆ·ç«¯æä¾›ç„列表中选择一个密ç ă€‚ç”±äº DHE_PSK/DHE_RSA 密ç å·²åœ¨æœ¬æ¬¡æ›´æ–°ä¸­ç¦ç”¨ï¼Œæœå¡å™¨å°†é€€å›åˆ°ä¸€ä¸ªæ›¿ä»£å¯†ç ă€‚在æ个别情况中，æœå¡å™¨ä¸æ”¯æŒä»»ä½•å…¶ä»–ç„代ç ï¼Œæ­¤æ—¶ï¼Œåˆå§‹æ­¥éª¤å°†å¤±è´¥ă€‚è‹¥è¦æ£€ç´¢æœå¡å™¨æ‰€æ”¯æŒç„密ç åˆ—表，需è¦é¦–先在客户端使用特å®ç„密ç è¿æ¥æœå¡å™¨ï¼Œå¯ä»¥ä½¿ç”¨ ``sslscan`` 等工具完æˆè¿æ¥ă€‚ + +ä» X509 库中移除 ``certs`` æ¨¡å— +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- mbedtls 3.1 ä¸å†æ”¯æŒ ``mbedtls/certs.h`` å¤´æ–‡ä»¶ă€‚å¤§å¤æ•°åº”用程åºæ”¯æŒä»åŒ…å«åˆ—è¡¨ä¸­å®‰å…¨åˆ é™¤è¯¥å¤´æ–‡ä»¶ă€‚ + +对 ``esp_crt_bundle_set`` API ç„é‡å¤§æ›´æ–° +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- æ›´æ–°å，调用 :cpp:func:`esp_crt_bundle_set()` API 需è¦ä¸€ä¸ªé¢å¤–ç„å‚æ•° ``bundle_size``ă€‚è¯¥ API ç„è¿”å›ç±»å‹ä¹Ÿä» ``void`` å˜ä¸ºäº† :cpp:type:`esp_err_t`。 + +对 ``esp_ds_rsa_sign`` API ç„é‡å¤§æ›´æ–° +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- æ›´æ–°å，调用 :cpp:func:`esp_ds_rsa_sign()` API 无需å†ä½¿ç”¨å‚æ•° ``mode``。 + +HTTPS æœå¡å™¨ +------------ + +é‡å¤§æ›´æ–°ï¼ˆæ¦‚述） +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +æ›´æ–° :cpp:type:`httpd_ssl_config_t` 结æ„体中æŒæœ‰ä¸åŒè¯ä¹¦ç„å˜é‡å。 + +.. list:: + * :cpp:member:`httpd_ssl_config::servercert`ï¼åŸ ``cacert_pem`` + * :cpp:member:`httpd_ssl_config::servercert_len`ï¼åŸ ``cacert_len`` + * :cpp:member:`httpd_ssl_config::cacert_pem`ï¼åŸ ``client_verify_cert_pem`` + * :cpp:member:`httpd_ssl_config::cacert_len`ï¼åŸ ``client_verify_cert_len`` + +:cpp:func:`httpd_ssl_stop` API ç„è¿”å›ç±»å‹ä» ``void`` å˜ä¸ºäº† :cpp:type:`esp_err_t`。 + +ESP HTTPS OTA +-------------- + +é‡å¤§æ›´æ–°ï¼ˆæ¦‚述） +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- 函数 :cpp:func:`esp_https_ota` ç°éœ€ä»¥æŒ‡å‘ :cpp:type:`esp_https_ota_config_t` ç„指针作为å‚数，而é之å‰ç„æŒ‡å‘ :cpp:type:`esp_http_client_config_t` ç„æŒ‡é’ˆă€‚ + + +ESP-TLS +-------------- + +é‡å¤§æ›´æ–°ï¼ˆæ¦‚述） +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +ç§æœ‰åŒ– ``esp_tls_t`` 结æ„体 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +æ›´æ–°å，:cpp:type:`esp_tls_t` 已完全ç§æœ‰åŒ–，用户无法直æ¥è®¿é—®å…¶å†…部结æ„ă€‚ä¹‹å‰éœ€è¦é€è¿‡ ESP-TLS å¥æŸ„è·å¾—ç„å¿…è¦æ•°æ®ï¼Œç°åœ¨å¯ç”±å¯¹åº”ç„ getter/setter 函数è·å–ă€‚å¦‚éœ€ç‰¹å®åŸèƒ½ç„ getter/setter 函数，请在 ESP-IDF ç„ `Issue æ¿å— `__ æå‡ºă€‚ + + +下列为新å¢ç„ getter/setter å‡½æ•°ï¼ + +.. list:: + * :cpp:func:`esp_tls_get_ssl_context`ï¼ä» ESP-TLS å¥æŸ„è·å–底层 ssl æ ˆç„ ssl ä¸ä¸‹æ–‡ă€‚ + +废弃函数åæ¨èç„替代函数 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +下表总结了在 ESP-IDF v5.0 中废弃ç„函数以å相应ç„æ›¿ä»£å‡½æ•°ă€‚ + +.. list-table:: + :widths: 50 50 + :header-rows: 1 + + * - 废弃函数 + - 替代函数 + * - ``esp_tls_conn_new()`` + - :cpp:func:`esp_tls_conn_new_sync` + * - ``esp_tls_conn_delete()`` + - :cpp:func:`esp_tls_conn_destroy` + +- 函数 :cpp:func:`esp_tls_conn_http_new` ç°å·²åºŸå¼ƒă€‚请使用替代函数 :cpp:func:`esp_tls_conn_http_new_sync` （或其异步函数 :cpp:func:`esp_tls_conn_http_new_async` ï¼‰ă€‚è¯·æ³¨æ„，使用替代函数时，需è¦é¢å¤–ç„å‚æ•° :cpp:type:`esp_tls_t`，此å‚数必须首先é€è¿‡ :cpp:func:`esp_tls_init` 函数进行åˆå§‹åŒ–。 + +HTTP æœå¡å™¨ +----------- + +é‡å¤§æ›´æ–°ï¼ˆæ¦‚述） +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- ``esp_http_server`` ç°ä¸å†æ”¯æŒ ``http_server.h`` å¤´æ–‡ä»¶ă€‚è¯·ä½¿ç”¨ ``esp_http_server.h``。 + +ESP HTTP 客户端 +--------------- + +é‡å¤§æ›´æ–°ï¼ˆæ¦‚述） +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- 函数 :cpp:func:`esp_http_client_read` å’Œ :cpp:func:`esp_http_client_fetch_headers` ç°åœ¨ä¼è¿”å›é¢å¤–ç„è¿”å›å€¼ ``-ESP_ERR_HTTP_EAGAIN`` 用äºå¤„ç†è¶…时错误，å³æ•°æ®å‡†å¤‡å¥½å‰å°±å·²è°ƒç”¨è¶…æ—¶ç„æƒ…å†µă€‚ + + +TCP 传输 +------------- + +é‡å¤§æ›´æ–°ï¼ˆæ¦‚述） +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- æ›´æ–°å，出ç°è¿æ¥è¶…æ—¶ç„情况时，函数 :cpp:func:`esp_transport_read` å°†è¿”å› ``0``ï¼Œå¯¹å…¶ä»–é”™è¯¯åˆ™è¿”å› ``< 0``ă€‚è¯·å‚考 :cpp:enum:`esp_tcp_transport_err_t`，查看所有å¯èƒ½ç„è¿”å›å€¼ă€‚ + + +MQTT 客户端 +----------- + +é‡å¤§æ›´æ–°ï¼ˆæ¦‚述） +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :cpp:type:`esp_mqtt_client_config_t` ç„所有字段都分组存放在å­ç»“æ„ä½“ä¸­ă€‚ + +以下为较为常用ç„é…ç½®é€‰é¡¹ï¼ + +- é€è¿‡ :cpp:member:`esp_mqtt_client_config_t::broker::address::uri` é…ç½® MQTT Broker +- é€è¿‡ :cpp:member:`esp_mqtt_client_config_t::broker::verification` é…ç½® MQTT Broker 身份验è¯ç„相关安全问题 +- é€è¿‡ :cpp:member:`esp_mqtt_client_config_t::credentials::username` é…置客户端用户å + + +ESP-Modbus +---------- + +é‡å¤§æ›´æ–°ï¼ˆæ¦‚述） +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +æœ¬æ¬¡æ›´æ–°ä» ESP-IDF 中移除了组件 ``freemodbus``，该组件已作为一个独立组件å—到支æŒă€‚å¯å‰å¾€å¦‚下ç„独立仓库，查看更å¤æœ‰å…³ ``ESP-Modbus`` ç„ä¿¡æ¯ï¼ + +* `GitHub ä¸­ç„ ESP-Modbus 组件 `__ + +在新版应用程åºä¸­ï¼Œ ``main`` 组件文件夹应包括组件管ç†å™¨æ¸…å•æ–‡ä»¶ ``idf_component.yml``ï¼Œå¦‚ä¸‹æ‰€ç¤ºï¼ + +.. code-block:: text + + dependencies: + espressif/esp-modbus: + version: "^1.0" + +å¯ä»¥å‰å¾€ `组件管ç†å™¨æ³¨å†Œè¡¨ `__ 找到 ``ESP-Modbus`` ç»„ä»¶ă€‚æ›´å¤æœ‰å…³å¦‚何设置组件管ç†å™¨ç„ä¿¡æ¯ï¼Œè¯·å‚考 `组件管ç†å™¨æ–‡æ¡£ `__。 + +对äºä½¿ç”¨ ESP-IDF v4.x å以å版本ç„应用程åºï¼Œéœ€è¦é€è¿‡æ·»å ç»„件管ç†å™¨æ¸…å•æ–‡ä»¶ ``idf_component.yml`` 拉å–新版 ``ESP-Modbus`` 组件。åŒæ—¶ï¼Œåœ¨ç¼–译时，应å»æ‰å·²è¿‡æ—¶ç„ ``freemodbus`` ç»„ä»¶ă€‚æ­¤é¡¹æ“作å¯é€è¿‡é¡¹ç›® ``CMakeLists.txt`` 中ç„以下语å¥å®ç°ï¼ + +.. code-block:: cmake + + set(EXCLUDE_COMPONENTS freemodbus) diff --git a/docs/zh_CN/migration-guides/release-5.x/provisioning.rst b/docs/zh_CN/migration-guides/release-5.x/provisioning.rst index 2664b06a35..91ff8e5ccc 100644 --- a/docs/zh_CN/migration-guides/release-5.x/provisioning.rst +++ b/docs/zh_CN/migration-guides/release-5.x/provisioning.rst @@ -1 +1,26 @@ -.. include:: ../../../en/migration-guides/release-5.x/provisioning.rst +é…ç½® +====== + +:link_to_translation:`en:[English]` + +Protocomm +--------- + +:cpp:func:`protocomm_set_security` API ä¸­ç„ ``pop`` 字段ç°å·²å¼ƒç”¨ă€‚请使用 ``sec_params`` 字段æ¥ä»£æ›¿ ``pop``ă€‚æ­¤å‚数应包å«æ‰€ä½¿ç”¨ç„å议版本所è¦æ±‚ç„结æ„（包括安全å‚æ•°ï¼‰ă€‚ + +例如，当使用安全版本 2 时，``sec_params`` å‚数应包å«æŒ‡å‘ :cpp:type:`protocomm_security2_params_t` ç±»å‹ç»“æ„ç„æŒ‡é’ˆă€‚ + +Wi-Fi é…ç½® +------------- + +.. list:: + * :cpp:func:`wifi_prov_mgr_start_provisioning` API ä¸­ç„ ``pop`` 字段ç°å·²å¼ƒç”¨ă€‚请使用 ``wifi_prov_sec_params`` 字段æ¥ä»£æ›¿ ``pop``ă€‚æ­¤å‚数应包å«æ‰€ä½¿ç”¨ç„å议版本所è¦æ±‚ç„结æ„（包括安全å‚æ•°ï¼‰ă€‚ä¾‹å¦‚ï¼Œå½“ä½¿ç”¨å®‰å…¨ç‰ˆæœ¬ 2 时，``wifi_prov_sec_params`` å‚数应包å«æŒ‡å‘ :cpp:type:`wifi_prov_security2_params_t` 结æ„体类å‹ç„æŒ‡é’ˆă€‚ + + * :cpp:func:`wifi_prov_mgr_is_provisioned` API ä¸å†è¿”å› :c:macro:`ESP_ERR_INVALID_STATE` é”™è¯¯ă€‚æ­¤ API ç°åœ¨å¯ä»¥åœ¨ä¸ä¾èµ–é…置管ç†å™¨åˆå§‹åŒ–ç¶æ€ç„æƒ…å†µä¸‹å·¥ä½œă€‚ + +ESP 本地æ§åˆ¶ +----------------- + +:cpp:type:`esp_local_ctrl_proto_sec_cfg_t` API ä¸­ç„ ``pop`` 字段ç°å·²å¼ƒç”¨ă€‚请使用 ``sec_params`` 字段æ¥ä»£æ›¿ ``pop``ă€‚æ­¤å‚数应包å«æ‰€ä½¿ç”¨ç„å议版本所è¦æ±‚ç„结æ„（包括安全å‚æ•°ï¼‰ă€‚ + +例如，当使用安全版本 2 时，``sec_params`` 字段应包å«æŒ‡å‘ :cpp:type:`esp_local_ctrl_security2_params_t` ç±»å‹ç»“æ„ç„æŒ‡é’ˆă€‚ diff --git a/docs/zh_CN/migration-guides/release-5.x/removed-components.rst b/docs/zh_CN/migration-guides/release-5.x/removed-components.rst index fe05889c6c..d713c1bacd 100644 --- a/docs/zh_CN/migration-guides/release-5.x/removed-components.rst +++ b/docs/zh_CN/migration-guides/release-5.x/removed-components.rst @@ -1,6 +1,8 @@ ä» ESP-IDF 中移出或弃用ç„组件 ================================ +:link_to_translation:`en:[English]` + 移至 IDF Component Registry ç„组件 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -18,6 +20,9 @@ * `sh2lib `_ * `expat `_ * `coap `_ +* `esp-cryptoauthlib `_ +* `qrcode `_ +* `tjpgd `_ .. note:: 请注æ„，http 解æåŸèƒ½ä»¥å‰å±äº ``nghttp`` 组件一部分，但ç°åœ¨å±äº :component:`http_parser ` 组件。 @@ -40,6 +45,9 @@ IDF v4.x 版本中已ä¸å†ä½¿ç”¨ä»¥ä¸‹ç»„ä»¶ï¼Œè¿™äº›ç»„ä»¶å·²å¼ƒç”¨ï¼ .. note:: ä¸å†æ”¯æŒ OpenSSL-API 组件。IDF Component Registry ä¸­ä¹Ÿæ²¡æœ‰è¯¥ç»„ä»¶ă€‚è¯·ç›´æ¥ä½¿ç”¨ :doc:`ESP-TLS ` 或 :component:`mbedtls` API。 +.. note:: + ä¸å†æ”¯æŒ esp_adc_cal 组件。 æ–°ç„ adc 校准驱å¨åœ¨ esp_adc ç»„ä»¶ä¸­ă€‚æ—§ç‰ˆ adc 校准驱å¨å·²è¢«è¿ç§»è¿› esp_adc 组件中。 è¦ä½¿ç”¨æ—§ç‰ˆ esp_adc_cal 驱å¨æ¥å£ï¼Œä½ åº”该在 CMakeLists.txt 文件ç„组件ä¾èµ–列表中å¢å  esp_adc ă€‚æ›´å¤ç»†è‚请查看 :doc:`Peripherals Migration Guide `。 + 版本更新å无需目标组件，因此以下目标组件也已ç»ä» ESP-IDF ä¸­åˆ é™¤ï¼ * ``esp32`` diff --git a/docs/zh_CN/migration-guides/release-5.x/storage.rst b/docs/zh_CN/migration-guides/release-5.x/storage.rst index 5022a34040..7e759515ab 100644 --- a/docs/zh_CN/migration-guides/release-5.x/storage.rst +++ b/docs/zh_CN/migration-guides/release-5.x/storage.rst @@ -1 +1,131 @@ -.. include:: ../../../en/migration-guides/release-5.x/storage.rst \ No newline at end of file +存储 +======= + +SDMMC/SDSPI +----------- + +用户ç°å¯é€è¿‡ ``sdmmc_host_t.max_freq_khz`` å°† SDMMC/SDSPI æ¥å£ä¸ç„ SD å¡é¢‘ç‡é…置为特å®å€¼ï¼Œä¸å†å±€é™äºä¹‹å‰ç„ ``SDMMC_FREQ_PROBING`` (400 kHz)〠``SDMMC_FREQ_DEFAULT`` (20 MHz) 或是 ``SDMMC_FREQ_HIGHSPEED`` (40 MHz)ă€‚æ­¤å‰ï¼Œå¦‚æœç”¨æˆ·é…置了ä¸è¿°ä¸‰ä¸ªç»™å®é¢‘ç‡ä¹‹å¤–ç„值，用户所选频ç‡å°†è‡ªå¨è°ƒæ•´ä¸ºä¸å…¶æœ€ä¸ºæ¥è¿‘ç„ç»™å®å€¼ă€‚ + +æ›´æ–°å，底层驱å¨å°†è®¡ç®—ä¸ç”¨æˆ·é…ç½®ç„特å®å€¼æœ€ä¸ºæ¥è¿‘ç„åˆé€‚频ç‡ă€‚相对äºæ举项选择，该频ç‡ç°ç”±å¯ç”¨ç„分频器æä¾›ă€‚ä¸è¿‡ï¼Œå¦‚æœå°æœªæ›´æ–°ç°æœ‰ç„应用代ç ï¼Œå¯èƒ½ä¼å¯¼è‡´ä¸ SD å¡ç„é€ä¿¡è¿‡ç¨‹å‡ºç°é—®é¢˜ă€‚如å‘ç°ä¸è¿°é—®é¢˜ï¼Œè¯·ç»§ç»­å°è¯•é…ç½®ä¸æœŸæœ›å€¼æ¥è¿‘ç„ä¸åŒé¢‘ç‡ï¼Œç›´åˆ°æ‰¾åˆ°åˆé€‚ç„频ç‡ă€‚如需查看底层驱å¨ç„计算结æœä»¥åå®é™…应用ç„频ç‡ï¼Œè¯·ä½¿ç”¨ ``void sdmmc_card_print_info(FILE* stream, const sdmmc_card_t* card)`` å‡½æ•°ă€‚ + +FatFs +----- + +FatFs 已更新至 v0.14， ``f_mkfs()`` 函数签å也已å˜æ›´ă€‚æ–°ç­¾å为 ``FRESULT f_mkfs (const TCHAR* path, const MKFS_PARM* opt, void* work, UINT len);``，使用 ``MKFS_PARM`` 结æ„体作为第二个å®å‚。 + +分区表 +--------------- + +分区表生æˆå™¨ä¸å†æ”¯æŒæœªå¯¹é½ç„åˆ†åŒºă€‚ç”Ÿæˆåˆ†åŒºè¡¨æ—¶ï¼Œ ``ESP-IDF`` å°†åªæ¥å—å移é‡ä¸ 4 KB 对é½ç„åˆ†åŒºă€‚æ­¤å˜æ›´ä»…å½±å“新生æˆç„分区表，ä¸å½±å“读写ç°æœ‰åˆ†åŒºă€‚ + + +VFS +--- + +``esp_vfs_semihost_register()`` 函数签åæœ‰æ‰€æ›´æ”¹ï¼ + +- æ–°ç­¾å为 ``esp_err_t esp_vfs_semihost_register(const char* base_path);`` +- 旧签åç„ ``host_path`` å‚æ•°ä¸å†å­˜åœ¨ï¼Œè¯·ä½¿ç”¨ OpenOCD 命令 ``ESP_SEMIHOST_BASEDIR`` 设置主机ä¸ç„å®Œæ•´è·¯å¾„ă€‚ + +函数签å更改 +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +以下函数ç°å°†è¿”å› ``esp_err_t``，而é ``void`` 或 ``nvs_iterator_t``ă€‚æ­¤å‰ï¼Œå½“å‚数无效或内部出ç°é—®é¢˜æ—¶ï¼Œè¿™äº›å‡½æ•°å°† ``assert()`` æˆ–è¿”å› ``nullptr``。é€è¿‡è¿”å› ``esp_err_t``，您将è·å¾—æ›´å å®ç”¨ç„错误æ¥å‘。 + +- :cpp:func:`nvs_entry_find` +- :cpp:func:`nvs_entry_next` +- :cpp:func:`nvs_entry_info` + +ç”±äº ``esp_err_t`` è¿”å›ç±»å‹ç„更改， ``nvs_entry_find()`` å’Œ ``nvs_entry_next()`` ç„使用模å¼ä¹Ÿå‘生了å˜åŒ–。ä¸è¿°å‡½æ•°ç°å‡é€è¿‡å‚数修改迭代器，而éè¿”å›ä¸€ä¸ªè¿­ä»£å™¨ă€‚ + +迭代 NVS 分区ç„旧编程模å¼å¦‚ä¸‹æ‰€ç¤ºï¼ + +.. code-block:: c + + nvs_iterator_t it = nvs_entry_find(, , NVS_TYPE_ANY); + while (it != NULL) { + nvs_entry_info_t info; + nvs_entry_info(it, &info); + it = nvs_entry_next(it); + printf("key '%s', type '%d'", info.key, info.type); + }; + +ç°åœ¨ï¼Œè¿­ä»£ NVS 分区ç„编程模å¼å·²æ›´æ–°ä¸ºï¼ + +.. code-block:: c + + nvs_iterator_t it = nullptr; + esp_err_t res = nvs_entry_find(, , NVS_TYPE_ANY, &it); + while(res == ESP_OK) { + nvs_entry_info_t info; + nvs_entry_info(it, &info); // Can omit error check if parameters are guaranteed to be non-NULL + printf("key '%s', type '%d'", info.key, info.type); + res = nvs_entry_next(&it); + } + nvs_release_iterator(it); + +迭代器有效性 +^^^^^^^^^^^^^^^^^ + +请注æ„，由äºå‡½æ•°ç­¾åç„改å¨ï¼Œå¦‚æœå­˜åœ¨å‚数错误，则å¯èƒ½ä» ``nvs_entry_find()`` è·å¾—æ— æ•ˆè¿­ä»£å™¨ă€‚å› æ­¤ï¼Œè¯·å¡å¿…在使用 ``nvs_entry_find()`` 之å‰å°†è¿­ä»£å™¨åˆå§‹åŒ–为 ``NULL``，以å…在调用 ``nvs_release_iterator()`` 之å‰è¿›è¡Œå¤æ‚ç„é”™è¯¯æ£€æŸ¥ă€‚ä¸è¿°ç¼–程模å¼ä¾¿æ˜¯ä¸€ä¸ªå¾ˆå¥½ç„例å­ă€‚ + + +删除 SDSPI å¼ƒç”¨ç„ API +------------------------------------- + +结æ„体 ``sdspi_slot_config_t`` 和函数 ``sdspi_host_init_slot()`` ç°å·²åˆ é™¤ï¼Œå¹¶ç”±ç»“æ„体 ``sdspi_device_config_t`` 和函数 ``sdspi_host_init_device()`` æ›¿ä»£ă€‚ + +ROM SPI flash +^^^^^^^^^^^^^ + +在 v5.0 之å‰ç„版本中，ROM SPI flash 函数一般é€è¿‡ ``esp32**/rom/spi_flash.h`` 得以体ç°ă€‚因此，为支æŒä¸åŒ ESP è¯ç‰‡è€Œç¼–写ç„代ç å¯èƒ½ä¼å¡«å……ä¸åŒç›®æ ‡ç„ ROM å¤´æ–‡ä»¶ă€‚æ­¤å¤–ï¼Œå¹¶é所有 API 都å¯ä»¥åœ¨å…¨éƒ¨ç„ ESP è¯ç‰‡ä¸ä½¿ç”¨ă€‚ + +ç°åœ¨ï¼Œå¸¸ç”¨ API 被æå–至 ``esp_rom_spiflash.h``ă€‚å°½ç®¡è¿™ä¸èƒ½ç®—作é‡å¤§å˜æ›´ï¼Œæˆ‘们强烈建议您仅使用此头文件中ç„函数（å³ä»¥ ``esp_rom_spiflash`` 为å‰ç¼€å¹¶åŒ…å«åœ¨ ``esp_rom_spiflash.h`` 中），以è·å¾—ä¸åŒ ESP è¯ç‰‡ä¹‹é—´æ›´ä½³ç„交å‰å…¼å®¹æ€§ă€‚ + +为了æ高 ROM SPI flash API ç„å¯è¯»æ€§ï¼Œä»¥ä¸‹å‡½æ•°ä¹Ÿè¢«é‡å‘½åï¼ + +- ``esp_rom_spiflash_lock()`` æ›´å为 ``esp_rom_spiflash_set_bp()`` +- ``esp_rom_spiflash_unlock()`` æ›´å为 ``esp_rom_spiflash_clear_bp()`` + +SPI flash é©±å¨ +^^^^^^^^^^^^^^^^^^^^^^ + +``esp_flash_speed_t`` ``enum`` ç±»å‹ç°å·²å¼ƒç”¨ă€‚ç°åœ¨ï¼Œæ‚¨å¯ä»¥ç›´æ¥å°†å®é™…时钟频ç‡å€¼ä¼ é€’ç»™ flash é…置结æ„ă€‚ä¸‹ä¸ºé…ç½® 80MHz flash 频ç‡ç„ç¤ºä¾‹ï¼ + +.. code-block:: c + + esp_flash_spi_device_config_t dev_cfg = { + // Other members + .freq_mhz = 80, + // Other members + }; + +旧版 SPI flash é©±å¨ +^^^^^^^^^^^^^^^^^^^^^^^ + +为了使 SPI flash 驱å¨æ›´ä¸ºç¨³å®ï¼Œv5.0 å·²ç»åˆ é™¤æ—§ç‰ˆ SPI flash 驱å¨ă€‚旧版 SPI flash 驱å¨ç¨‹åºæ˜¯æŒ‡è‡ª v3.0 以æ¥ç„默认 SPI flash 驱å¨ç¨‹åºï¼Œä»¥å自 v4.0 以æ¥å¯ç”¨é…置选项 ``CONFIG_SPI_FLASH_USE_LEGACY_IMPL`` ç„ SPI flash 驱å¨ă€‚ä» v5.0 开始，我们将ä¸å†æ”¯æŒæ—§ç‰ˆ SPI flash 驱å¨ç¨‹åºă€‚å› æ­¤ï¼Œæ—§ç‰ˆé©±å¨ API å’Œ ``CONFIG_SPI_FLASH_USE_LEGACY_IMPL`` é…置选项å‡è¢«åˆ é™¤ï¼Œè¯·æ”¹ç”¨æ–° SPI flash 驱å¨ç„ API。 + +.. list-table:: + :widths: 50 50 + :header-rows: 1 + + * - 删除项目 + - 替代项目 + * - ``spi_flash_erase_sector()`` + - ``esp_flash_erase_region()`` + * - ``spi_flash_erase_range()`` + - ``esp_flash_erase_region()`` + * - ``spi_flash_write()`` + - ``esp_flash_write()`` + * - ``spi_flash_read()`` + - ``esp_flash_read()`` + * - ``spi_flash_write_encrypted()`` + - ``esp_flash_write_encrypted()`` + * - ``spi_flash_read_encrypted()`` + - ``esp_flash_read_encrypted()`` + +.. note:: + + 带有å‰ç¼€ ``esp_flash`` ç„新函数æ¥å—é¢å¤–ç„ ``esp_flash_t*`` å‚æ•°ă€‚æ‚¨å¯ä»¥ç›´æ¥å°†å…¶è®¾ç½®ä¸º NULL，ä»è€Œä½¿å‡½æ•°è¿è¡Œä¸» flash (``esp_flash_default_chip``)。 + +ç”±äºç³»ç»Ÿå‡½æ•°ä¸å†æ˜¯å…¬å…±å‡½æ•°ï¼Œ ``esp_spi_flash.h`` 头文件已åœæ­¢ä½¿ç”¨ă€‚è‹¥è¦ä½¿ç”¨ flash 映射 API，请使用 ``spi_flash_mmap.h``。 diff --git a/docs/zh_CN/migration-guides/release-5.x/system.rst b/docs/zh_CN/migration-guides/release-5.x/system.rst index 5c6ca2cc14..d5e76bb59d 100644 --- a/docs/zh_CN/migration-guides/release-5.x/system.rst +++ b/docs/zh_CN/migration-guides/release-5.x/system.rst @@ -54,7 +54,7 @@ esp_hw_support - ``esp_cpu_get_ccount()``ă€``esp_cpu_set_ccount()`` å’Œ ``esp_cpu_in_ocd_debug_mode()`` å·²ä» ``esp_cpu.h`` ä¸­ç§»é™¤ă€‚è¯·åˆ†åˆ«ä½¿ç”¨ ``esp_cpu_get_cycle_count()``ă€``esp_cpu_set_cycle_count()`` å’Œ ``esp_cpu_dbgr_is_attached()`` ä»£æ›¿ă€‚ - 头文件 ``esp_intr.h`` å·²è¢«ç§»é™¤ă€‚è¯·åŒ…å« ``esp_intr_alloc.h`` 以分é…å’Œæ“ä½œä¸­æ–­ă€‚ - Panic API（å³ä»¥ ``esp_panic`` 为å‰ç¼€ç„函数ă€ç±»å‹æˆ–å®ï¼‰å·²è¢«æ›´æ–°ä¸ºç§æœ‰ APIă€‚å› æ­¤ï¼ŒåŸå…ˆç„包å«è·¯å¾„ ``#include "esp_panic.h"`` å·²è¢«ç§»é™¤ă€‚å¦‚ä»éœ€ä½¿ç”¨ Panic API（并ä¸æ¨è），请使用 ``#include "esp_private/panic_reason.h"`` æ¥åŒ…å«ă€‚æ­¤å¤–ï¼Œè¯·åŒ…å« ``esp_debug_helpers.h`` 以使用ä¸è°ƒè¯•æœ‰å…³ç„ä»»æ„è¾…å©å‡½æ•°ï¼Œå¦‚打å°å›æº¯ă€‚ -- 头文件 ``soc_log.h`` ç°æ›´å为 ``esp_hw_log.h``，所有日志å®ä¹Ÿä» ``SOC_LOGx`` 更新为 ``ESP_HW_LOGx``ă€‚è¯·ä½¿ç”¨æ›´æ–°åç„æ ¼å¼ă€‚ +- 头文件 ``soc_log.h`` ç°æ›´å为 ``esp_hw_log.h``，并已更新为ç§æœ‰ă€‚建议用户使用 ``esp_log.h`` 头文件下ç„日志 API。 - 包å«å¤´æ–‡ä»¶ ``spinlock.h``ă€``clk_ctrl_os.h`` å’Œ ``rtc_wdt.h`` æ—¶ä¸åº”当使用 ``soc`` å‰ç¼€ï¼Œå¦‚ ``#include "spinlock.h"``。 - ``esp_chip_info()`` 命令返å›è¯ç‰‡ç‰ˆæœ¬ï¼Œæ ¼å¼ä¸º = 100 * ``ä¸»è¦ eFuse 版本`` + ``æ¬¡è¦ eFuse 版本``ă€‚å› æ­¤ï¼Œä¸ºé€‚åº”æ–°æ ¼å¼ï¼Œ ``esp_chip_info_t`` 结æ„ä½“ä¸­ç„ ``revision`` 被扩展为 uint16_t。 @@ -115,6 +115,8 @@ ESP é•œåƒä¸­å…³äº SPI 速度ç„æ举æˆå‘˜å·²é‡æ–°æ›´åï¼ - 以结æ„体ç„å½¢å¼ä¼ é€’é…ç½®ă€‚ - å¯å°†è¯¥å‡½æ•°é…置为订阅空闲任å¡ă€‚ +- åŸå…ˆç„é…置选项 ``CONFIG_ESP_TASK_WDT`` 被é‡æ–°å‘½å为 :ref:`CONFIG_ESP_TASK_WDT_INIT` 并引入了一个新选项 :ref:`CONFIG_ESP_TASK_WDT_EN`。 + FreeRTOS -------- @@ -149,3 +151,15 @@ FreeRTOS 移æ¤ç›¸å…³ç„å® - ``vPortCPUAcquireMutex()`` 已被移除，请使用 ``spinlock_acquire()`` å‡½æ•°ă€‚ - ``vPortCPUAcquireMutexTimeout()`` 已被移除，请使用 ``spinlock_acquire()`` å‡½æ•°ă€‚ - ``vPortCPUReleaseMutex()`` 已被移除，请使用 ``spinlock_release()`` å‡½æ•°ă€‚ + +应用程åºæ›´æ–° +------------ + +- 函数 :cpp:func:`esp_ota_get_app_description` å’Œ :cpp:func:`esp_ota_get_app_elf_sha256` 已被弃用，请分别使用 :cpp:func:`esp_app_get_description` å’Œ :cpp:func:`esp_app_get_elf_sha256` 函数æ¥ä»£æ›¿ă€‚这些函数已被移至新组件 :component:`esp_app_format`ă€‚è¯·å‚考头文件 :component_file:`esp_app_desc.h `。 + +引导å è½½ç¨‹åºæ”¯æŒ +---------------- + +- :cpp:type:`esp_app_desc_t` 结æ„体此å‰åœ¨ :component_file:`esp_app_format.h ` 中声æ˜ï¼Œç°åœ¨åœ¨ :component_file:`esp_app_desc.h ` 中声æ˜ă€‚ + +- 函数 :cpp:func:`bootloader_common_get_partition_description` 已更新为ç§æœ‰å‡½æ•°ï¼Œè¯·ä½¿ç”¨ä»£æ›¿å‡½æ•° :cpp:func:`esp_ota_get_partition_description`ă€‚æ³¨æ„，此函数ç„第一个å‚数为 :cpp:type:`esp_partition_t`，而é :cpp:type:`esp_partition_pos_t`。 diff --git a/examples/bluetooth/.build-test-rules.yml b/examples/bluetooth/.build-test-rules.yml index ab53dcd219..e3e0f2458e 100644 --- a/examples/bluetooth/.build-test-rules.yml +++ b/examples/bluetooth/.build-test-rules.yml @@ -99,6 +99,24 @@ examples/bluetooth/nimble/ble_l2cap_coc: temporary: true reason: the other targets are not tested yet +examples/bluetooth/nimble/ble_periodic_adv: + enable: + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3"] + temporary: true + reason: the other targets are not tested yet + +examples/bluetooth/nimble/ble_periodic_sync: + enable: + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3"] + temporary: true + reason: the other targets are not tested yet + +examples/bluetooth/nimble/ble_phy: + enable: + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3"] + temporary: true + reason: the other targets are not tested yet + examples/bluetooth/nimble/ble_spp: enable: - if: IDF_TARGET in ["esp32", "esp32c3", "esp32s3"] diff --git a/examples/bluetooth/bluedroid/ble_50/ble50_security_server/main/ble50_sec_gatts_demo.c b/examples/bluetooth/bluedroid/ble_50/ble50_security_server/main/ble50_sec_gatts_demo.c index b7503e7c18..b3ac9f7160 100644 --- a/examples/bluetooth/bluedroid/ble_50/ble50_security_server/main/ble50_sec_gatts_demo.c +++ b/examples/bluetooth/bluedroid/ble_50/ble50_security_server/main/ble50_sec_gatts_demo.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -55,6 +55,7 @@ esp_ble_gap_ext_adv_params_t ext_adv_params_2M = { .sid = 0, .scan_req_notif = false, .own_addr_type = BLE_ADDR_TYPE_PUBLIC, + .tx_power = EXT_ADV_TX_PWR_NO_PREFERENCE, }; struct gatts_profile_inst { diff --git a/examples/bluetooth/bluedroid/ble_50/multi-adv/main/multi_adv_demo.c b/examples/bluetooth/bluedroid/ble_50/multi-adv/main/multi_adv_demo.c index 8cb211a098..42e75b09cb 100644 --- a/examples/bluetooth/bluedroid/ble_50/multi-adv/main/multi_adv_demo.c +++ b/examples/bluetooth/bluedroid/ble_50/multi-adv/main/multi_adv_demo.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -64,6 +64,7 @@ esp_ble_gap_ext_adv_params_t ext_adv_params_1M = { .sid = 0, .scan_req_notif = false, .own_addr_type = BLE_ADDR_TYPE_RANDOM, + .tx_power = EXT_ADV_TX_PWR_NO_PREFERENCE, }; esp_ble_gap_ext_adv_params_t ext_adv_params_2M = { @@ -78,6 +79,7 @@ esp_ble_gap_ext_adv_params_t ext_adv_params_2M = { .sid = 1, .scan_req_notif = false, .own_addr_type = BLE_ADDR_TYPE_RANDOM, + .tx_power = EXT_ADV_TX_PWR_NO_PREFERENCE, }; esp_ble_gap_ext_adv_params_t legacy_adv_params = { @@ -92,6 +94,7 @@ esp_ble_gap_ext_adv_params_t legacy_adv_params = { .sid = 2, .scan_req_notif = false, .own_addr_type = BLE_ADDR_TYPE_RANDOM, + .tx_power = EXT_ADV_TX_PWR_NO_PREFERENCE, }; esp_ble_gap_ext_adv_params_t ext_adv_params_coded = { @@ -106,6 +109,7 @@ esp_ble_gap_ext_adv_params_t ext_adv_params_coded = { .sid = 3, .scan_req_notif = false, .own_addr_type = BLE_ADDR_TYPE_RANDOM, + .tx_power = EXT_ADV_TX_PWR_NO_PREFERENCE, }; static uint8_t raw_adv_data_1m[] = { diff --git a/examples/bluetooth/bluedroid/ble_50/peroidic_adv/main/periodic_adv_demo.c b/examples/bluetooth/bluedroid/ble_50/peroidic_adv/main/periodic_adv_demo.c index 7adb5fa67e..60f497e719 100644 --- a/examples/bluetooth/bluedroid/ble_50/peroidic_adv/main/periodic_adv_demo.c +++ b/examples/bluetooth/bluedroid/ble_50/peroidic_adv/main/periodic_adv_demo.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -65,6 +65,7 @@ esp_ble_gap_ext_adv_params_t ext_adv_params_2M = { .sid = 0, .scan_req_notif = false, .own_addr_type = BLE_ADDR_TYPE_RANDOM, + .tx_power = EXT_ADV_TX_PWR_NO_PREFERENCE, }; static esp_ble_gap_periodic_adv_params_t periodic_adv_params = { diff --git a/examples/bluetooth/bluedroid/classic_bt/a2dp_sink/main/bt_app_av.c b/examples/bluetooth/bluedroid/classic_bt/a2dp_sink/main/bt_app_av.c index 3238cc3f27..8495fbb67b 100644 --- a/examples/bluetooth/bluedroid/classic_bt/a2dp_sink/main/bt_app_av.c +++ b/examples/bluetooth/bluedroid/classic_bt/a2dp_sink/main/bt_app_av.c @@ -302,6 +302,7 @@ static void bt_av_hdl_a2d_evt(uint16_t event, void *p_param) /* for now only SBC stream is supported */ if (a2d->audio_cfg.mcc.type == ESP_A2D_MCT_SBC) { int sample_rate = 16000; + int ch_count = 2; char oct0 = a2d->audio_cfg.mcc.cie.sbc[0]; if (oct0 & (0x01 << 6)) { sample_rate = 32000; @@ -310,11 +311,19 @@ static void bt_av_hdl_a2d_evt(uint16_t event, void *p_param) } else if (oct0 & (0x01 << 4)) { sample_rate = 48000; } + + if (oct0 & (0x01 << 3)) { + ch_count = 1; + } #ifdef CONFIG_EXAMPLE_A2DP_SINK_OUTPUT_INTERNAL_DAC - i2s_set_clk(0, sample_rate, 16, 2); + i2s_set_clk(0, sample_rate, 16, ch_count); #else + i2s_channel_disable(tx_chan); i2s_std_clk_config_t clk_cfg = I2S_STD_CLK_DEFAULT_CONFIG(sample_rate); + i2s_std_slot_config_t slot_cfg = I2S_STD_MSB_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_16BIT, ch_count); i2s_channel_reconfig_std_clock(tx_chan, &clk_cfg); + i2s_channel_reconfig_std_slot(tx_chan, &slot_cfg); + i2s_channel_enable(tx_chan); #endif ESP_LOGI(BT_AV_TAG, "Configure audio player: %x-%x-%x-%x", a2d->audio_cfg.mcc.cie.sbc[0], diff --git a/examples/bluetooth/bluedroid/classic_bt/bt_spp_initiator/main/console_uart.c b/examples/bluetooth/bluedroid/classic_bt/bt_spp_initiator/main/console_uart.c index ed5b6b1de4..bde63273b7 100644 --- a/examples/bluetooth/bluedroid/classic_bt/bt_spp_initiator/main/console_uart.c +++ b/examples/bluetooth/bluedroid/classic_bt/bt_spp_initiator/main/console_uart.c @@ -25,6 +25,7 @@ static const uart_config_t uart_cfg = { .stop_bits = UART_STOP_BITS_1, .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, .rx_flow_ctrl_thresh = 127, + .source_clk = UART_SCLK_DEFAULT, }; extern void spp_msg_args_parser(char *buf, int len); diff --git a/examples/bluetooth/bluedroid/classic_bt/hfp_ag/sdkconfig.defaults b/examples/bluetooth/bluedroid/classic_bt/hfp_ag/sdkconfig.defaults index c7f714a012..d79e6d40d8 100644 --- a/examples/bluetooth/bluedroid/classic_bt/hfp_ag/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/classic_bt/hfp_ag/sdkconfig.defaults @@ -3,6 +3,7 @@ CONFIG_BT_ENABLED=y CONFIG_BT_BLE_ENABLED=n CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=y +CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN=1 CONFIG_BT_BLUEDROID_ENABLED=y CONFIG_BT_CLASSIC_ENABLED=y CONFIG_BT_HFP_ENABLE=y diff --git a/examples/bluetooth/bluedroid/classic_bt/hfp_hf/sdkconfig.defaults b/examples/bluetooth/bluedroid/classic_bt/hfp_hf/sdkconfig.defaults index e9b56e3807..4775673416 100644 --- a/examples/bluetooth/bluedroid/classic_bt/hfp_hf/sdkconfig.defaults +++ b/examples/bluetooth/bluedroid/classic_bt/hfp_hf/sdkconfig.defaults @@ -3,6 +3,7 @@ CONFIG_BT_ENABLED=y CONFIG_BT_BLE_ENABLED=n CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=y +CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN=1 CONFIG_BT_BLUEDROID_ENABLED=y CONFIG_BT_CLASSIC_ENABLED=y CONFIG_BT_HFP_ENABLE=y diff --git a/examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/main/bt_app_av.c b/examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/main/bt_app_av.c index f8ee8f811b..151ff86f86 100644 --- a/examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/main/bt_app_av.c +++ b/examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/main/bt_app_av.c @@ -173,8 +173,10 @@ static void bt_av_hdl_a2d_evt(uint16_t event, void *p_param) #ifdef CONFIG_EXAMPLE_A2DP_SINK_OUTPUT_INTERNAL_DAC i2s_set_clk(0, sample_rate, 16, 2); #else + i2s_channel_disable(tx_chan); i2s_std_clk_config_t clk_cfg = I2S_STD_CLK_DEFAULT_CONFIG(sample_rate); i2s_channel_reconfig_std_clock(tx_chan, &clk_cfg); + i2s_channel_enable(tx_chan); #endif ESP_LOGI(BT_AV_TAG, "Configure audio player %x-%x-%x-%x", diff --git a/examples/bluetooth/blufi/main/blufi_example.h b/examples/bluetooth/blufi/main/blufi_example.h index 207543fdc5..595f293beb 100644 --- a/examples/bluetooth/blufi/main/blufi_example.h +++ b/examples/bluetooth/blufi/main/blufi_example.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -21,3 +21,4 @@ void blufi_security_deinit(void); int esp_blufi_gap_register_callback(void); esp_err_t esp_blufi_host_init(void); esp_err_t esp_blufi_host_and_cb_init(esp_blufi_callbacks_t *callbacks); +esp_err_t esp_blufi_host_deinit(void); diff --git a/examples/bluetooth/blufi/main/blufi_init.c b/examples/bluetooth/blufi/main/blufi_init.c index 46b3af3d85..da10642608 100644 --- a/examples/bluetooth/blufi/main/blufi_init.c +++ b/examples/bluetooth/blufi/main/blufi_init.c @@ -47,6 +47,37 @@ esp_err_t esp_blufi_host_init(void) } +esp_err_t esp_blufi_host_deinit(void) +{ + int ret; + ret = esp_blufi_profile_deinit(); + if(ret != ESP_OK) { + return ret; + } + + ret = esp_bluedroid_disable(); + if (ret) { + BLUFI_ERROR("%s deinit bluedroid failed: %s\n", __func__, esp_err_to_name(ret)); + return ESP_FAIL; + } + + ret = esp_bluedroid_deinit(); + if (ret) { + BLUFI_ERROR("%s deinit bluedroid failed: %s\n", __func__, esp_err_to_name(ret)); + return ESP_FAIL; + } + + ESP_ERROR_CHECK(esp_bt_controller_disable()); + ret = esp_bt_controller_deinit(); + if (ret) { + BLUFI_ERROR("%s deinit bluedroid failed: %s\n", __func__, esp_err_to_name(ret)); + return ESP_FAIL; + } + + return ESP_OK; + +} + esp_err_t esp_blufi_gap_register_callback(void) { int rc; @@ -161,6 +192,25 @@ esp_err_t esp_blufi_host_init(void) return ESP_OK; } +esp_err_t esp_blufi_host_deinit(void) +{ + esp_err_t ret = ESP_OK; + + ret = esp_blufi_profile_deinit(); + if(ret != ESP_OK) { + return ret; + } + + esp_blufi_btc_deinit(); + + ret = nimble_port_stop(); + if (ret == 0) { + nimble_port_deinit(); + } + + return ret; +} + esp_err_t esp_blufi_gap_register_callback(void) { return ESP_OK; diff --git a/examples/bluetooth/blufi/main/blufi_security.c b/examples/bluetooth/blufi/main/blufi_security.c index bfec66c845..5dd304b034 100644 --- a/examples/bluetooth/blufi/main/blufi_security.c +++ b/examples/bluetooth/blufi/main/blufi_security.c @@ -104,18 +104,25 @@ void blufi_dh_negotiate_data_handler(uint8_t *data, int len, uint8_t **output_da } free(blufi_sec->dh_param); blufi_sec->dh_param = NULL; - ret = mbedtls_dhm_make_public(&blufi_sec->dhm, (int) mbedtls_mpi_size( &blufi_sec->dhm.MBEDTLS_PRIVATE(P) ), blufi_sec->self_public_key, mbedtls_mpi_size( &blufi_sec->dhm.MBEDTLS_PRIVATE(P) ), myrand, NULL); + + const int dhm_len = mbedtls_dhm_get_len(&blufi_sec->dhm); + ret = mbedtls_dhm_make_public(&blufi_sec->dhm, dhm_len, blufi_sec->self_public_key, dhm_len, myrand, NULL); if (ret) { BLUFI_ERROR("%s make public failed %d\n", __func__, ret); btc_blufi_report_error(ESP_BLUFI_MAKE_PUBLIC_ERROR); return; } - mbedtls_dhm_calc_secret( &blufi_sec->dhm, + ret = mbedtls_dhm_calc_secret( &blufi_sec->dhm, blufi_sec->share_key, SHARE_KEY_BIT_LEN, &blufi_sec->share_len, - NULL, NULL); + myrand, NULL); + if (ret) { + BLUFI_ERROR("%s mbedtls_dhm_calc_secret failed %d\n", __func__, ret); + btc_blufi_report_error(ESP_BLUFI_DH_PARAM_ERROR); + return; + } ret = mbedtls_md5(blufi_sec->share_key, blufi_sec->share_len, blufi_sec->psk); @@ -129,7 +136,7 @@ void blufi_dh_negotiate_data_handler(uint8_t *data, int len, uint8_t **output_da /* alloc output data */ *output_data = &blufi_sec->self_public_key[0]; - *output_len = mbedtls_mpi_size( &blufi_sec->dhm.MBEDTLS_PRIVATE(P) ); + *output_len = dhm_len; *need_free = false; } diff --git a/examples/bluetooth/blufi/sdkconfig.defaults.esp32c2 b/examples/bluetooth/blufi/sdkconfig.defaults.esp32c2 index b00342ef4e..aa4d6be851 100644 --- a/examples/bluetooth/blufi/sdkconfig.defaults.esp32c2 +++ b/examples/bluetooth/blufi/sdkconfig.defaults.esp32c2 @@ -3,9 +3,10 @@ # CONFIG_PARTITION_TABLE_SINGLE_APP_LARGE=y CONFIG_BT_ENABLED=y -CONFIG_BT_BLE_BLUFI_ENABLE=y +CONFIG_BT_NIMBLE_BLUFI_ENABLE=y # CONFIG_BT_GATTC_ENABLE is not set # CONFIG_BT_BLE_SMP_ENABLE is not set # CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y CONFIG_MBEDTLS_DHM_C=y +CONFIG_BT_NIMBLE_ENABLED=y diff --git a/examples/bluetooth/esp_ble_mesh/ble_mesh_console/sdkconfig.ci.bluedroid b/examples/bluetooth/esp_ble_mesh/ble_mesh_console/sdkconfig.ci.bluedroid new file mode 100644 index 0000000000..3517a675b4 --- /dev/null +++ b/examples/bluetooth/esp_ble_mesh/ble_mesh_console/sdkconfig.ci.bluedroid @@ -0,0 +1,32 @@ +# Override some defaults so BT stack is enabled +CONFIG_BT_ENABLED=y +CONFIG_BTDM_CTRL_MODE_BLE_ONLY=y +CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=n +CONFIG_BTDM_CTRL_MODE_BTDM=n +CONFIG_CTRL_BTDM_MODEM_SLEEP=n +CONFIG_BTDM_SCAN_DUPL_TYPE_DATA_DEVICE=y +CONFIG_BTDM_BLE_MESH_SCAN_DUPL_EN=y +CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MANUAL=y +CONFIG_BT_BTU_TASK_STACK_SIZE=4512 + +# Override some defaults of ESP BLE Mesh +CONFIG_BLE_MESH=y +CONFIG_BLE_MESH_NODE=y +CONFIG_BLE_MESH_PB_GATT=y +CONFIG_BLE_MESH_TX_SEG_MSG_COUNT=3 +CONFIG_BLE_MESH_RX_SEG_MSG_COUNT=3 +CONFIG_BLE_MESH_CFG_CLI=y +CONFIG_BLE_MESH_GENERIC_ONOFF_CLI=y +CONFIG_BLE_MESH_PROVISIONER=y +CONFIG_BLE_MESH_PROVISIONER_RECV_HB=y +CONFIG_BLE_MESH_PROVISIONER_RECV_HB_FILTER_SIZE=3 +CONFIG_BLE_MESH_SELF_TEST=y +CONFIG_BLE_MESH_TEST_AUTO_ENTER_NETWORK=y +CONFIG_BLE_MESH_WAIT_FOR_PROV_MAX_DEV_NUM=80 +CONFIG_BLE_MESH_MAX_PROV_NODES=80 + +# partitions +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_FILENAME="partitions.csv" +CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y +CONFIG_ESPTOOLPY_FLASHSIZE="4MB" diff --git a/examples/bluetooth/esp_ble_mesh/ble_mesh_console/sdkconfig.ci.nimble b/examples/bluetooth/esp_ble_mesh/ble_mesh_console/sdkconfig.ci.nimble new file mode 100644 index 0000000000..f5777657cc --- /dev/null +++ b/examples/bluetooth/esp_ble_mesh/ble_mesh_console/sdkconfig.ci.nimble @@ -0,0 +1,31 @@ +# Override some defaults so nimble is enabled +CONFIG_BT_ENABLED=y +CONFIG_BTDM_CTRL_MODE_BLE_ONLY=y +CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=n +CONFIG_BTDM_CTRL_MODE_BTDM=n +CONFIG_CTRL_BTDM_MODEM_SLEEP=n +CONFIG_BTDM_SCAN_DUPL_TYPE_DATA_DEVICE=y +CONFIG_BTDM_BLE_MESH_SCAN_DUPL_EN=y +CONFIG_BT_NIMBLE_ENABLED=y + +# Override some defaults of ESP BLE Mesh +CONFIG_BLE_MESH=y +CONFIG_BLE_MESH_NODE=y +CONFIG_BLE_MESH_PB_GATT=y +CONFIG_BLE_MESH_TX_SEG_MSG_COUNT=3 +CONFIG_BLE_MESH_RX_SEG_MSG_COUNT=3 +CONFIG_BLE_MESH_CFG_CLI=y +CONFIG_BLE_MESH_GENERIC_ONOFF_CLI=y +CONFIG_BLE_MESH_PROVISIONER=y +CONFIG_BLE_MESH_PROVISIONER_RECV_HB=y +CONFIG_BLE_MESH_PROVISIONER_RECV_HB_FILTER_SIZE=3 +CONFIG_BLE_MESH_SELF_TEST=y +CONFIG_BLE_MESH_TEST_AUTO_ENTER_NETWORK=y +CONFIG_BLE_MESH_WAIT_FOR_PROV_MAX_DEV_NUM=80 +CONFIG_BLE_MESH_MAX_PROV_NODES=80 + +# partitions +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_FILENAME="partitions.csv" +CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y +CONFIG_ESPTOOLPY_FLASHSIZE="4MB" diff --git a/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/CMakeLists.txt b/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/CMakeLists.txt index 6265291dec..905d2f8b8d 100644 --- a/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/CMakeLists.txt +++ b/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/CMakeLists.txt @@ -2,5 +2,7 @@ # CMakeLists in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.5) +set(EXTRA_COMPONENT_DIRS ${CMAKE_CURRENT_LIST_DIR}/../../common/nimble_central_utils) + include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(coc_blecent) diff --git a/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/main/CMakeLists.txt b/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/main/CMakeLists.txt index 7eff1870a2..18d510d988 100644 --- a/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/main/CMakeLists.txt +++ b/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/main/CMakeLists.txt @@ -1,2 +1,4 @@ -idf_component_register(SRCS "main.c" "misc.c" "peer.c" - INCLUDE_DIRS ".") +set(srcs "main.c") + +idf_component_register(SRCS "${srcs}" + INCLUDE_DIRS ".") diff --git a/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/main/coc_blecent.h b/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/main/coc_blecent.h index 5111ad3dd9..0a29abb156 100644 --- a/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/main/coc_blecent.h +++ b/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/main/coc_blecent.h @@ -8,6 +8,7 @@ #define H_COC_BLECENT_ #include "modlog/modlog.h" +#include "esp_central.h" #ifdef __cplusplus extern "C" { #endif @@ -18,76 +19,6 @@ struct ble_hs_cfg; union ble_store_value; union ble_store_key; -/** Misc. */ -void print_bytes(const uint8_t *bytes, int len); -void print_mbuf(const struct os_mbuf *om); -char *addr_str(const void *addr); -void print_uuid(const ble_uuid_t *uuid); -void print_conn_desc(const struct ble_gap_conn_desc *desc); -void print_adv_fields(const struct ble_hs_adv_fields *fields); -void ext_print_adv_report(const void *param); -void print_mbuf_data(const struct os_mbuf *om); - -/** Peer. */ -struct peer_dsc { - SLIST_ENTRY(peer_dsc) next; - struct ble_gatt_dsc dsc; -}; -SLIST_HEAD(peer_dsc_list, peer_dsc); - -struct peer_chr { - SLIST_ENTRY(peer_chr) next; - struct ble_gatt_chr chr; - - struct peer_dsc_list dscs; -}; -SLIST_HEAD(peer_chr_list, peer_chr); - -struct peer_svc { - SLIST_ENTRY(peer_svc) next; - struct ble_gatt_svc svc; - - struct peer_chr_list chrs; -}; -SLIST_HEAD(peer_svc_list, peer_svc); - -struct peer; -typedef void peer_disc_fn(const struct peer *peer, int status, void *arg); - -struct peer { - SLIST_ENTRY(peer) next; - - uint16_t conn_handle; - - /** List of discovered GATT services. */ - struct peer_svc_list svcs; - - /** Keeps track of where we are in the service discovery process. */ - uint16_t disc_prev_chr_val; - struct peer_svc *cur_svc; - - /** Callback that gets executed when service discovery completes. */ - peer_disc_fn *disc_cb; - void *disc_cb_arg; -}; - -int peer_disc_all(uint16_t conn_handle, peer_disc_fn *disc_cb, - void *disc_cb_arg); -const struct peer_dsc * -peer_dsc_find_uuid(const struct peer *peer, const ble_uuid_t *svc_uuid, - const ble_uuid_t *chr_uuid, const ble_uuid_t *dsc_uuid); -const struct peer_chr * -peer_chr_find_uuid(const struct peer *peer, const ble_uuid_t *svc_uuid, - const ble_uuid_t *chr_uuid); -const struct peer_svc * -peer_svc_find_uuid(const struct peer *peer, const ble_uuid_t *uuid); -int peer_delete(uint16_t conn_handle); -int peer_add(uint16_t conn_handle); -int peer_init(int max_peers, int max_svcs, int max_chrs, int max_dscs); -struct peer * -peer_find(uint16_t conn_handle); - - #ifdef __cplusplus } #endif diff --git a/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/CMakeLists.txt b/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/CMakeLists.txt index 74e6734037..1979f5db49 100644 --- a/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/CMakeLists.txt +++ b/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/CMakeLists.txt @@ -2,5 +2,7 @@ # CMakeLists in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.5) +set(EXTRA_COMPONENT_DIRS ${CMAKE_CURRENT_LIST_DIR}/../../common/nimble_peripheral_utils) + include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(coc_bleprph) diff --git a/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/main/CMakeLists.txt b/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/main/CMakeLists.txt index 04e467e105..18d510d988 100644 --- a/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/main/CMakeLists.txt +++ b/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/main/CMakeLists.txt @@ -1,6 +1,4 @@ -set(srcs "main.c" - "misc.c" - "scli.c") +set(srcs "main.c") idf_component_register(SRCS "${srcs}" - INCLUDE_DIRS ".") + INCLUDE_DIRS ".") diff --git a/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/main/coc_bleprph.h b/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/main/coc_bleprph.h index 4503e9a1b3..bf4ffe6e28 100644 --- a/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/main/coc_bleprph.h +++ b/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/main/coc_bleprph.h @@ -10,6 +10,7 @@ #include #include "nimble/ble.h" #include "modlog/modlog.h" +#include "esp_peripheral.h" #ifdef __cplusplus extern "C" { #endif @@ -23,14 +24,6 @@ struct ble_gatt_register_ctxt; void gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *arg); int gatt_svr_init(void); -/* Console */ -int scli_init(void); -int scli_receive_key(int *key); - -/** Misc. */ -void print_bytes(const uint8_t *bytes, int len); -void print_addr(const void *addr); - #ifdef __cplusplus } #endif diff --git a/examples/bluetooth/nimble/ble_periodic_adv/CMakeLists.txt b/examples/bluetooth/nimble/ble_periodic_adv/CMakeLists.txt new file mode 100644 index 0000000000..a143c9dd24 --- /dev/null +++ b/examples/bluetooth/nimble/ble_periodic_adv/CMakeLists.txt @@ -0,0 +1,7 @@ +# The following lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) +set(EXTRA_COMPONENT_DIRS ${CMAKE_CURRENT_LIST_DIR}/../common/nimble_peripheral_utils) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(ble_periodic_adv) diff --git a/examples/bluetooth/nimble/ble_periodic_adv/README.md b/examples/bluetooth/nimble/ble_periodic_adv/README.md new file mode 100644 index 0000000000..58d6b24d7e --- /dev/null +++ b/examples/bluetooth/nimble/ble_periodic_adv/README.md @@ -0,0 +1,75 @@ +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | + +# BLE Periodic Advertiser Example + +(See the README.md file in the upper level 'examples' directory for more information about examples.) + +This example starts periodic advertising with non resolvable private address. + +It uses Bluetooth controller and NimBLE stack based BLE host. + +This example aims at understanding periodic advertisement and related NimBLE APIs. + + +To test this demo, any BLE Periodic Sync app can be used. + + +Note : + +* Make sure to run `python -m pip install --user -r $IDF_PATH/requirements.txt -r $IDF_PATH/tools/ble/requirements.txt` to install the dependency packages needed. +* Currently this Python utility is only supported on Linux (BLE communication is via BLuez + DBus). + +## How to Use Example + +Before project configuration and build, be sure to set the correct chip target using: + +```bash +idf.py set-target +``` + +### Configure the project + +Open the project configuration menu: + +```bash +idf.py menuconfig +``` + +In the `Example Configuration` menu: + +* Select I/O capabilities of device from `Example Configuration --> I/O Capability`, default is `Just_works`. + +### Build and Flash + +Run `idf.py -p PORT flash monitor` to build, flash and monitor the project. + +(To exit the serial monitor, type ``Ctrl-]``.) + +See the [Getting Started Guide](https://idf.espressif.com/) for full steps to configure and use ESP-IDF to build projects. + +## Example Output + +There is this console output when periodic_adv is started: + +``` +I (313) BTDM_INIT: BT controller compile version [2ee0168] +I (313) phy_init: phy_version 912,d001756,Jun 2 2022,16:28:07 +I (353) system_api: Base MAC address is not set +I (353) system_api: read default base MAC address from EFUSE +I (353) BTDM_INIT: Bluetooth MAC: 84:f7:03:08:14:8e + +I (363) NimBLE_BLE_PERIODIC_ADV: BLE Host Task Started +I (373) NimBLE: Device Address: +I (373) NimBLE: d0:42:3a:95:84:05 +I (373) NimBLE: + +I (383) NimBLE: instance 1 started (periodic) +``` + +## Note +* Periodic sync transfer is not implemented for now. + +## Troubleshooting + +For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon. diff --git a/examples/bluetooth/nimble/ble_periodic_adv/main/CMakeLists.txt b/examples/bluetooth/nimble/ble_periodic_adv/main/CMakeLists.txt new file mode 100644 index 0000000000..023dd5e462 --- /dev/null +++ b/examples/bluetooth/nimble/ble_periodic_adv/main/CMakeLists.txt @@ -0,0 +1,4 @@ +set(srcs "main.c") + +idf_component_register(SRCS "${srcs}" + INCLUDE_DIRS ".") diff --git a/examples/bluetooth/nimble/ble_periodic_adv/main/Kconfig.projbuild b/examples/bluetooth/nimble/ble_periodic_adv/main/Kconfig.projbuild new file mode 100644 index 0000000000..3dca6ecbf7 --- /dev/null +++ b/examples/bluetooth/nimble/ble_periodic_adv/main/Kconfig.projbuild @@ -0,0 +1,15 @@ +menu "Example Configuration" + + config EXAMPLE_EXTENDED_ADV + bool + default y if SOC_ESP_NIMBLE_CONTROLLER + prompt "Enable Extended Adv" + help + Use this option to enable extended advertising in the example + + config EXAMPLE_RANDOM_ADDR + bool + prompt "Advertise RANDOM Address" + help + Use this option to advertise a random address instead of public address +endmenu diff --git a/examples/bluetooth/nimble/ble_periodic_adv/main/main.c b/examples/bluetooth/nimble/ble_periodic_adv/main/main.c new file mode 100644 index 0000000000..3b2be3b720 --- /dev/null +++ b/examples/bluetooth/nimble/ble_periodic_adv/main/main.c @@ -0,0 +1,221 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#include "esp_log.h" +#include "nvs_flash.h" +/* BLE */ +#include "nimble/nimble_port.h" +#include "nimble/nimble_port_freertos.h" +#include "host/ble_hs.h" +#include "host/util/util.h" +#include "console/console.h" +#include "services/gap/ble_svc_gap.h" +#include "periodic_adv.h" +#include "host/ble_gap.h" +#include "host/ble_hs_adv.h" +#include "patterns.h" + +#if CONFIG_EXAMPLE_EXTENDED_ADV +static uint8_t periodic_adv_raw_data[] = {'E', 'S', 'P', '_', 'P', 'E', 'R', 'I', 'O', 'D', 'I', 'C', '_', 'A', 'D', 'V'}; +static uint8_t id_addr_type; +#endif + +static const char *tag = "NimBLE_BLE_PERIODIC_ADV"; +#if CONFIG_EXAMPLE_RANDOM_ADDR +static uint8_t own_addr_type = BLE_OWN_ADDR_RANDOM; +#else +static uint8_t own_addr_type; +#endif + +void ble_store_config_init(void); + +#if CONFIG_EXAMPLE_EXTENDED_ADV +/** + * Enables advertising with the following parameters: + * o General discoverable mode. + * o Undirected connectable mode. + */ +static void +start_periodic_adv(void) +{ + int rc = ble_hs_util_ensure_addr(0); + assert(rc == 0); + /* configure global address */ + rc = ble_hs_id_infer_auto(0, &id_addr_type); + assert(rc == 0); + + struct ble_gap_periodic_adv_params pparams; + struct ble_gap_ext_adv_params params; + struct ble_hs_adv_fields adv_fields; + struct os_mbuf *data; + uint8_t instance = 1; + ble_addr_t addr; + + /* For periodic we use instance with non-connectable advertising */ + memset (¶ms, 0, sizeof(params)); + + /* advertise using random addr */ + params.own_addr_type = BLE_OWN_ADDR_RANDOM; + params.primary_phy = BLE_HCI_LE_PHY_1M; + params.secondary_phy = BLE_HCI_LE_PHY_2M; + params.sid = 2; + + /* configure instance 1 */ + rc = ble_gap_ext_adv_configure(instance, ¶ms, NULL, NULL, NULL); + assert (rc == 0); + + /* set random (NRPA) address for instance */ + rc = ble_hs_id_gen_rnd(1, &addr); + assert (rc == 0); + + rc = ble_gap_ext_adv_set_addr(instance, &addr ); + assert (rc == 0); + + memset(&adv_fields, 0, sizeof(adv_fields)); + adv_fields.name = (const uint8_t *)"Periodic ADV"; + adv_fields.name_len = strlen((char *)adv_fields.name); + + /* Default to legacy PDUs size, mbuf chain will be increased if needed + */ + data = os_msys_get_pkthdr(BLE_HCI_MAX_ADV_DATA_LEN, 0); + assert(data); + + rc = ble_hs_adv_set_fields_mbuf(&adv_fields, data); + assert(rc == 0); + + rc = ble_gap_ext_adv_set_data(instance, data); + assert(rc == 0); + + /* configure periodic advertising */ + memset(&pparams, 0, sizeof(pparams)); + pparams.include_tx_power = 0; + pparams.itvl_min = 160; + pparams.itvl_max = 240; + + rc = ble_gap_periodic_adv_configure(instance, &pparams); + assert(rc == 0); + + /* get mbuf for periodic data */ + data = os_msys_get_pkthdr(sizeof(ext_adv_pattern_1), 0); + assert(data); + + /* fill mbuf with periodic data */ + + rc = os_mbuf_append(data, ext_adv_pattern_1, sizeof(ext_adv_pattern_1)); + assert(rc == 0); + + data = os_msys_get_pkthdr(sizeof(periodic_adv_raw_data), 0); + assert(data); + + rc = os_mbuf_append(data, periodic_adv_raw_data, sizeof(periodic_adv_raw_data)); + assert(rc == 0); + rc = ble_gap_periodic_adv_set_data(instance, data); + assert (rc == 0); + + /* start periodic advertising */ + rc = ble_gap_periodic_adv_start(instance); + assert (rc == 0); + + /* start advertising */ + rc = ble_gap_ext_adv_start(instance, 0, 0); + assert (rc == 0); + + MODLOG_DFLT(INFO, "instance %u started (periodic)\n", instance); +} +#endif +static void +periodic_adv_on_reset(int reason) +{ + MODLOG_DFLT(ERROR, "Resetting state; reason=%d\n", reason); +} + +#if CONFIG_EXAMPLE_RANDOM_ADDR +static void +periodic_adv_set_addr(void) +{ + ble_addr_t addr; + int rc; + + /* generate new non-resolvable private address */ + rc = ble_hs_id_gen_rnd(0, &addr); + assert(rc == 0); + + /* set generated address */ + rc = ble_hs_id_set_rnd(addr.val); + + assert(rc == 0); +} +#endif + +static void +periodic_adv_on_sync(void) +{ + int rc; + +#if CONFIG_EXAMPLE_RANDOM_ADDR + /* Generate a non-resolvable private address. */ + periodic_adv_set_addr(); + /* Make sure we have proper identity address set (public preferred) */ + rc = ble_hs_util_ensure_addr(1); +#else + rc = ble_hs_util_ensure_addr(0); +#endif + assert(rc == 0); + + /* Figure out address to use while advertising (no privacy for now) */ + rc = ble_hs_id_infer_auto(0, &own_addr_type); + if (rc != 0) { + MODLOG_DFLT(ERROR, "error determining address type; rc=%d\n", rc); + return; + } + + /* Printing ADDR */ + uint8_t addr_val[6] = {0}; + rc = ble_hs_id_copy_addr(own_addr_type, addr_val, NULL); + + MODLOG_DFLT(INFO, "Device Address: "); + print_addr(addr_val); + MODLOG_DFLT(INFO, "\n"); + /* Begin advertising. */ +#if CONFIG_EXAMPLE_EXTENDED_ADV + start_periodic_adv(); +#endif +} + +void periodic_adv_host_task(void *param) +{ + ESP_LOGI(tag, "BLE Host Task Started"); + /* This function will return only when nimble_port_stop() is executed */ + nimble_port_run(); + + nimble_port_freertos_deinit(); +} + +void +app_main(void) +{ + int rc; + /* Initialize NVS — it is used to store PHY calibration data */ + esp_err_t ret = nvs_flash_init(); + if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { + ESP_ERROR_CHECK(nvs_flash_erase()); + ret = nvs_flash_init(); + } + ESP_ERROR_CHECK(ret); + nimble_port_init(); + /* Initialize the NimBLE host configuration. */ + ble_hs_cfg.reset_cb = periodic_adv_on_reset; + ble_hs_cfg.sync_cb = periodic_adv_on_sync; + ble_hs_cfg.store_status_cb = ble_store_util_status_rr; + /* Set the default device name. */ + rc = ble_svc_gap_device_name_set("nimble_periodic_adv"); + assert(rc == 0); + + /* XXX Need to have template for store */ + ble_store_config_init(); + + nimble_port_freertos_init(periodic_adv_host_task); +} diff --git a/examples/bluetooth/nimble/ble_periodic_adv/main/patterns.h b/examples/bluetooth/nimble/ble_periodic_adv/main/patterns.h new file mode 100644 index 0000000000..94b85f72c6 --- /dev/null +++ b/examples/bluetooth/nimble/ble_periodic_adv/main/patterns.h @@ -0,0 +1,173 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +static const uint8_t ext_adv_pattern_1[] = { + 0x00, 0x02, 0x00, 0x04, 0x00, 0x06, 0x00, 0x08, 0x00, 0x0a, + 0x00, 0x0c, 0x00, 0x0e, 0x00, 0x10, 0x00, 0x12, 0x00, 0x14, + 0x00, 0x16, 0x00, 0x18, 0x00, 0x1a, 0x00, 0x1c, 0x00, 0x1e, + 0x00, 0x20, 0x00, 0x22, 0x00, 0x24, 0x00, 0x26, 0x00, 0x28, + 0x00, 0x2a, 0x00, 0x2c, 0x00, 0x2e, 0x00, 0x30, 0x00, 0x32, + 0x00, 0x34, 0x00, 0x36, 0x00, 0x38, 0x00, 0x3a, 0x00, 0x3c, + 0x00, 0x3e, 0x00, 0x40, 0x00, 0x42, 0x00, 0x44, 0x00, 0x46, + 0x00, 0x48, 0x00, 0x4a, 0x00, 0x4c, 0x00, 0x4e, 0x00, 0x50, + 0x00, 0x52, 0x00, 0x54, 0x00, 0x56, 0x00, 0x58, 0x00, 0x5a, + 0x00, 0x5c, 0x00, 0x5e, 0x00, 0x60, 0x00, 0x62, 0x00, 0x64, + 0x00, 0x66, 0x00, 0x68, 0x00, 0x6a, 0x00, 0x6c, 0x00, 0x6e, + 0x00, 0x70, 0x00, 0x72, 0x00, 0x74, 0x00, 0x76, 0x00, 0x78, + 0x00, 0x7a, 0x00, 0x7c, 0x00, 0x7e, 0x00, 0x80, 0x00, 0x82, + 0x00, 0x84, 0x00, 0x86, 0x00, 0x88, 0x00, 0x8a, 0x00, 0x8c, + 0x00, 0x8e, 0x00, 0x90, 0x00, 0x92, 0x00, 0x94, 0x00, 0x96, + 0x00, 0x98, 0x00, 0x9a, 0x00, 0x9c, 0x00, 0x9e, 0x00, 0xa0, + 0x00, 0xa2, 0x00, 0xa4, 0x00, 0xa6, 0x00, 0xa8, 0x00, 0xaa, + 0x00, 0xac, 0x00, 0xae, 0x00, 0xb0, 0x00, 0xb2, 0x00, 0xb4, + 0x00, 0xb6, 0x00, 0xb8, 0x00, 0xba, 0x00, 0xbc, 0x00, 0xbe, + 0x00, 0xc0, 0x00, 0xc2, 0x00, 0xc4, 0x00, 0xc6, 0x00, 0xc8, + 0x00, 0xca, 0x00, 0xcc, 0x00, 0xce, 0x00, 0xd0, 0x00, 0xd2, + 0x00, 0xd4, 0x00, 0xd6, 0x00, 0xd8, 0x00, 0xda, 0x00, 0xdc, + 0x00, 0xde, 0x00, 0xe0, 0x00, 0xe2, 0x00, 0xe4, 0x00, 0xe6, + 0x00, 0xe8, 0x00, 0xea, 0x00, 0xec, 0x00, 0xee, 0x00, 0xf0, + 0x00, 0xf2, 0x00, 0xf4, 0x00, 0xf6, 0x00, 0xf8, 0x00, 0xfa, + 0x00, 0xfc, 0x00, 0xfe, 0x01, 0x01, 0x01, 0x03, 0x01, 0x05, + 0x01, 0x07, 0x01, 0x09, 0x01, 0x0b, 0x01, 0x0d, 0x01, 0x0f, + 0x01, 0x11, 0x01, 0x13, 0x01, 0x15, 0x01, 0x17, 0x01, 0x19, + 0x01, 0x1b, 0x01, 0x1d, 0x01, 0x1f, 0x01, 0x21, 0x01, 0x23, + 0x01, 0x25, 0x01, 0x27, 0x01, 0x29, 0x01, 0x2b, 0x01, 0x2d, + 0x01, 0x2f, 0x01, 0x31, 0x01, 0x33, 0x01, 0x35, 0x01, 0x37, + 0x01, 0x39, 0x01, 0x3b, 0x01, 0x3d, 0x01, 0x3f, 0x01, 0x41, + 0x01, 0x43, 0x01, 0x45, 0x01, 0x47, 0x01, 0x49, 0x01, 0x4b, + 0x01, 0x4d, 0x01, 0x4f, 0x01, 0x51, 0x01, 0x53, 0x01, 0x55, + 0x01, 0x57, 0x01, 0x59, 0x01, 0x5b, 0x01, 0x5d, 0x01, 0x5f, + 0x01, 0x61, 0x01, 0x63, 0x01, 0x65, 0x01, 0x67, 0x01, 0x69, + 0x01, 0x6b, 0x01, 0x6d, 0x01, 0x6f, 0x01, 0x71, 0x01, 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a/examples/bluetooth/nimble/ble_periodic_adv/main/periodic_adv.h b/examples/bluetooth/nimble/ble_periodic_adv/main/periodic_adv.h new file mode 100644 index 0000000000..bb1bdad298 --- /dev/null +++ b/examples/bluetooth/nimble/ble_periodic_adv/main/periodic_adv.h @@ -0,0 +1,25 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#ifndef H_BLE_PERIODIC_ADV_ +#define H_BLE_PERIODIC_ADV_ + +#include +#include "nimble/ble.h" +#include "modlog/modlog.h" +#include "esp_peripheral.h" +#ifdef __cplusplus +extern "C" { +#endif + +struct ble_hs_cfg; +struct ble_gatt_register_ctxt; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/examples/bluetooth/nimble/ble_periodic_adv/sdkconfig.defaults b/examples/bluetooth/nimble/ble_periodic_adv/sdkconfig.defaults new file mode 100644 index 0000000000..60f9e68480 --- /dev/null +++ b/examples/bluetooth/nimble/ble_periodic_adv/sdkconfig.defaults @@ -0,0 +1,15 @@ +# Override some defaults so BT stack is enabled +# in this example + +# +# BT config +# +CONFIG_BT_ENABLED=y +CONFIG_BTDM_CTRL_MODE_BLE_ONLY=y +CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=n +CONFIG_BTDM_CTRL_MODE_BTDM=n +CONFIG_BT_BLUEDROID_ENABLED=n +CONFIG_BT_NIMBLE_ENABLED=y +CONFIG_EXAMPLE_EXTENDED_ADV=y +CONFIG_BT_NIMBLE_EXT_ADV=y +CONFIG_BT_NIMBLE_MAX_PERIODIC_SYNCS=1 diff --git a/examples/bluetooth/nimble/ble_periodic_sync/CMakeLists.txt b/examples/bluetooth/nimble/ble_periodic_sync/CMakeLists.txt new file mode 100644 index 0000000000..12971ca736 --- /dev/null +++ b/examples/bluetooth/nimble/ble_periodic_sync/CMakeLists.txt @@ -0,0 +1,6 @@ +# The following lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) +set(EXTRA_COMPONENT_DIRS ${CMAKE_CURRENT_LIST_DIR}/../common/nimble_central_utils) +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(ble_periodic_sync) diff --git a/examples/bluetooth/nimble/ble_periodic_sync/README.md b/examples/bluetooth/nimble/ble_periodic_sync/README.md new file mode 100644 index 0000000000..11923e7ef9 --- /dev/null +++ b/examples/bluetooth/nimble/ble_periodic_sync/README.md @@ -0,0 +1,84 @@ +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | + +# BLE Periodic Sync Example + +(See the README.md file in the upper level 'examples' directory for more information about examples.) + +This example performs passive scan for non-connectable non-scannable extended advertisement, it then establishes the periodic sync with the advertiser and then listens to the periodic advertisements. + + +It uses ESP32C3's Bluetooth controller and NimBLE stack based BLE host. + +This example aims at understanding BLE periodic sync establishment and periodic advertisement reports. + +To test this demo, use any periodic advertiser with uses extended adv data as "ESP_PERIODIC_ADV". + + +Note : + +* Make sure to run `python -m pip install --user -r $IDF_PATH/requirements.txt -r $IDF_PATH/tools/ble/requirements.txt` to install the dependency packages needed. +* Currently this Python utility is only supported on Linux (BLE communication is via BLuez + DBus). + +## How to Use Example + +Before project configuration and build, be sure to set the correct chip target using: + +```bash +idf.py set-target +``` + +### Hardware Required + +* A development board with ESP32/ESP32-C3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A USB cable for Power supply and programming + +See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. + +### Configure the Project + +Open the project configuration menu: + +```bash +idf.py menuconfig +``` + +In the `Example Configuration` menu: + +* Change the `Peer Address` option if needed. + +### Build and Flash + +Run `idf.py -p PORT flash monitor` to build, flash and monitor the project. + +(To exit the serial monitor, type ``Ctrl-]``.) + +See the [Getting Started Guide](https://idf.espressif.com/) for full steps to configure and use ESP-IDF to build projects. + +## Example Output + +This is the console output on successful periodic sync: + +``` +I (311) BTDM_INIT: BT controller compile version [3a49744] +I (311) phy_init: phy_version 912,d001756,Jun 2 2022,16:28:07 +I (351) system_api: Base MAC address is not set +I (351) system_api: read default base MAC address from EFUSE +I (351) BTDM_INIT: Bluetooth MAC: 84:f7:03:08:14:8e + +I (361) NimBLE_BLE_PERIODIC_SYNC: BLE Host Task Started +I (941) NimBLE: Periodic sync event : + +I (941) NimBLE: Periodic adv report event: + +I (4241) NimBLE: Periodic adv report event: + +I (7541) NimBLE: Periodic adv report event: + +I (10841) NimBLE: Periodic adv report event: +``` + + +## Troubleshooting + +For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon. diff --git a/examples/bluetooth/nimble/ble_periodic_sync/main/CMakeLists.txt b/examples/bluetooth/nimble/ble_periodic_sync/main/CMakeLists.txt new file mode 100644 index 0000000000..cf2c455cb5 --- /dev/null +++ b/examples/bluetooth/nimble/ble_periodic_sync/main/CMakeLists.txt @@ -0,0 +1,2 @@ +idf_component_register(SRCS "main.c" + INCLUDE_DIRS ".") diff --git a/examples/bluetooth/nimble/ble_periodic_sync/main/Kconfig.projbuild b/examples/bluetooth/nimble/ble_periodic_sync/main/Kconfig.projbuild new file mode 100644 index 0000000000..86199b5d91 --- /dev/null +++ b/examples/bluetooth/nimble/ble_periodic_sync/main/Kconfig.projbuild @@ -0,0 +1,8 @@ +menu "Example Configuration" + config EXAMPLE_EXTENDED_ADV + bool + default y if SOC_ESP_NIMBLE_CONTROLLER + prompt "Enable Extended Adv" + help + Use this option to enable extended advertising in the example +endmenu diff --git a/examples/bluetooth/nimble/ble_periodic_sync/main/main.c b/examples/bluetooth/nimble/ble_periodic_sync/main/main.c new file mode 100644 index 0000000000..8d7cb55531 --- /dev/null +++ b/examples/bluetooth/nimble/ble_periodic_sync/main/main.c @@ -0,0 +1,204 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#include "esp_log.h" +#include "nvs_flash.h" +/* BLE */ +#include "nimble/nimble_port.h" +#include "nimble/nimble_port_freertos.h" +#include "host/ble_hs.h" +#include "host/util/util.h" +#include "console/console.h" +#include "services/gap/ble_svc_gap.h" +#include "periodic_sync.h" +#include "host/ble_gap.h" + +static const char *tag = "NimBLE_BLE_PERIODIC_SYNC"; +static int synced = 0; +static int periodic_sync_gap_event(struct ble_gap_event *event, void *arg); + +void ble_store_config_init(void); + +static void +periodic_sync_scan(void) +{ + uint8_t own_addr_type; + struct ble_gap_disc_params disc_params; + int rc; + + /* Figure out address to use while advertising (no privacy for now) */ + rc = ble_hs_id_infer_auto(0, &own_addr_type); + if (rc != 0) { + MODLOG_DFLT(ERROR, "error determining address type; rc=%d\n", rc); + return; + } + + /* Tell the controller to filter duplicates; we don't want to process + * repeated advertisements from the same device. + */ + disc_params.filter_duplicates = 0; + + /** + * Perform a passive scan. I.e., don't send follow-up scan requests to + * each advertiser. + */ + disc_params.passive = 1; + + /* Use defaults for the rest of the parameters. */ + disc_params.itvl = 0; + disc_params.window = 0; + disc_params.filter_policy = 0; + disc_params.limited = 0; + + rc = ble_gap_disc(own_addr_type, BLE_HS_FOREVER, &disc_params, + periodic_sync_gap_event, NULL); + if (rc != 0) { + MODLOG_DFLT(ERROR, "Error initiating GAP discovery procedure; rc=%d\n", + rc); + } +} + +void print_periodic_sync_data(struct ble_gap_event *event) +{ + MODLOG_DFLT(DEBUG, "status : %d\nperiodic_sync_handle : %d\nsid : %d\n", event->periodic_sync.status, event->periodic_sync.sync_handle, event->periodic_sync.sid); + MODLOG_DFLT(DEBUG, "adv addr : "); + for (int i = 0; i < 6; i++) { + MODLOG_DFLT(DEBUG, "%d ", event->periodic_sync.adv_addr.val[i]); + } + MODLOG_DFLT(DEBUG, "\nadv_phy : %s\n", event->periodic_sync.adv_phy == 1 ? "1m" : (event->periodic_sync.adv_phy == 2 ? "2m" : "coded")); + MODLOG_DFLT(DEBUG, "per_adv_ival : %d\n", event->periodic_sync.per_adv_ival); + MODLOG_DFLT(DEBUG, "adv_clk_accuracy : %d\n", event->periodic_sync.adv_clk_accuracy); +} +void print_periodic_adv_data(struct ble_gap_event *event) +{ + MODLOG_DFLT(DEBUG, "sync_handle : %d\n", event->periodic_report.sync_handle); + MODLOG_DFLT(DEBUG, "tx_power : %d\n", event->periodic_report.tx_power); + MODLOG_DFLT(DEBUG, "rssi : %d\n", event->periodic_report.rssi); + MODLOG_DFLT(DEBUG, "data_status : %d\n", event->periodic_report.data_status); + MODLOG_DFLT(DEBUG, "data_length : %d\n", event->periodic_report.data_length); + MODLOG_DFLT(DEBUG, "data : "); + for (int i = 0; i < event->periodic_report.data_length; i++) { + MODLOG_DFLT(DEBUG, "%c", ((char *)event->periodic_report.data)[i]); + } + MODLOG_DFLT(DEBUG, "\n"); +} +void print_periodic_sync_lost_data(struct ble_gap_event *event) +{ + MODLOG_DFLT(DEBUG, "sync_handle : %d\n", event->periodic_sync_lost.sync_handle); + MODLOG_DFLT(DEBUG, "reason : %s\n", event->periodic_sync_lost.reason == 13 ? "timeout" : (event->periodic_sync_lost.reason == 14 ? "terminated locally" : "Unknown reason")); +} +/** + * The nimble host executes this callback when a GAP event occurs. The + * application associates a GAP event callback with each connection that is + * established. periodic_sync uses the same callback for all connections. + * + * @param event The event being signalled. + * @param arg Application-specified argument; unused by + * periodic_sync. + * + * @return 0 if the application successfully handled the + * event; nonzero on failure. The semantics + * of the return code is specific to the + * particular GAP event being signalled. + */ +static int +periodic_sync_gap_event(struct ble_gap_event *event, void *arg) +{ + switch (event->type) { +#if CONFIG_EXAMPLE_EXTENDED_ADV + case BLE_GAP_EVENT_EXT_DISC: + /* An advertisment report was received during GAP discovery. */ + struct ble_gap_ext_disc_desc *disc = ((struct ble_gap_ext_disc_desc *)(&event->disc)); + if (disc->sid == 2 && synced == 0) { + synced++; + const ble_addr_t addr; + uint8_t adv_sid; + struct ble_gap_periodic_sync_params params; + int rc; + memcpy((void *)&addr, (void *)&disc->addr, sizeof(disc->addr)); + memcpy(&adv_sid, &disc->sid, sizeof(disc->sid)); + params.skip = 10; + params.sync_timeout = 1000; + rc = ble_gap_periodic_adv_sync_create(&addr, adv_sid, ¶ms, periodic_sync_gap_event, NULL); + assert(rc == 0); + } + return 0; + case BLE_GAP_EVENT_PERIODIC_REPORT: + MODLOG_DFLT(INFO, "Periodic adv report event: \n"); + print_periodic_adv_data(event); + return 0; + case BLE_GAP_EVENT_PERIODIC_SYNC_LOST: + MODLOG_DFLT(INFO, "Periodic sync lost\n"); + print_periodic_sync_lost_data(event); + synced = 0; + return 0; + case BLE_GAP_EVENT_PERIODIC_SYNC: + MODLOG_DFLT(INFO, "Periodic sync event : \n"); + print_periodic_sync_data(event); + return 0; +#endif + default: + return 0; + } +} + +static void +periodic_sync_on_reset(int reason) +{ + MODLOG_DFLT(ERROR, "Resetting state; reason=%d\n", reason); +} + +static void +periodic_sync_on_sync(void) +{ + int rc; + /* Make sure we have proper identity address set (public preferred) */ + rc = ble_hs_util_ensure_addr(0); + assert(rc == 0); + + /* Begin scanning for a peripheral to connect to. */ + periodic_sync_scan(); +} + +void periodic_sync_host_task(void *param) +{ + ESP_LOGI(tag, "BLE Host Task Started"); + /* This function will return only when nimble_port_stop() is executed */ + nimble_port_run(); + + nimble_port_freertos_deinit(); +} + +void +app_main(void) +{ + int rc; + /* Initialize NVS — it is used to store PHY calibration data */ + esp_err_t ret = nvs_flash_init(); + if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { + ESP_ERROR_CHECK(nvs_flash_erase()); + ret = nvs_flash_init(); + } + ESP_ERROR_CHECK(ret); + + nimble_port_init(); + /* Configure the host. */ + ble_hs_cfg.reset_cb = periodic_sync_on_reset; + ble_hs_cfg.sync_cb = periodic_sync_on_sync; + ble_hs_cfg.store_status_cb = ble_store_util_status_rr; + + /* Initialize data structures to track connected peers. */ + rc = peer_init(MYNEWT_VAL(BLE_MAX_CONNECTIONS), 64, 64, 64); + assert(rc == 0); + + /* Set the default device name. */ + rc = ble_svc_gap_device_name_set("nimble_periodic_sync"); + assert(rc == 0); + + /* XXX Need to have template for store */ + ble_store_config_init(); + nimble_port_freertos_init(periodic_sync_host_task); +} diff --git a/examples/bluetooth/nimble/ble_periodic_sync/main/periodic_sync.h b/examples/bluetooth/nimble/ble_periodic_sync/main/periodic_sync.h new file mode 100644 index 0000000000..5da9f33399 --- /dev/null +++ b/examples/bluetooth/nimble/ble_periodic_sync/main/periodic_sync.h @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#ifndef H_BLE_PERIODIC_SYNC_ +#define H_BLE_PERIODIC_SYNC_ + +#include "modlog/modlog.h" +#include "esp_central.h" +#ifdef __cplusplus +extern "C" { +#endif + +struct ble_hs_adv_fields; +struct ble_gap_conn_desc; +struct ble_hs_cfg; +union ble_store_value; +union ble_store_key; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/examples/bluetooth/nimble/ble_periodic_sync/sdkconfig.defaults b/examples/bluetooth/nimble/ble_periodic_sync/sdkconfig.defaults new file mode 100644 index 0000000000..60f9e68480 --- /dev/null +++ b/examples/bluetooth/nimble/ble_periodic_sync/sdkconfig.defaults @@ -0,0 +1,15 @@ +# Override some defaults so BT stack is enabled +# in this example + +# +# BT config +# +CONFIG_BT_ENABLED=y +CONFIG_BTDM_CTRL_MODE_BLE_ONLY=y +CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=n +CONFIG_BTDM_CTRL_MODE_BTDM=n +CONFIG_BT_BLUEDROID_ENABLED=n +CONFIG_BT_NIMBLE_ENABLED=y +CONFIG_EXAMPLE_EXTENDED_ADV=y +CONFIG_BT_NIMBLE_EXT_ADV=y +CONFIG_BT_NIMBLE_MAX_PERIODIC_SYNCS=1 diff --git a/examples/bluetooth/nimble/ble_phy/phy_cent/CMakeLists.txt b/examples/bluetooth/nimble/ble_phy/phy_cent/CMakeLists.txt new file mode 100644 index 0000000000..06b2dba673 --- /dev/null +++ b/examples/bluetooth/nimble/ble_phy/phy_cent/CMakeLists.txt @@ -0,0 +1,8 @@ +# The following lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +set(EXTRA_COMPONENT_DIRS $ {CMAKE_CURRENT_LIST_DIR} / .. / .. / common / nimble_central_utils) + +include($ENV{IDF_PATH} / tools / cmake / project.cmake) +project(phy_cent) diff --git a/examples/bluetooth/nimble/ble_phy/phy_cent/README.md b/examples/bluetooth/nimble/ble_phy/phy_cent/README.md new file mode 100644 index 0000000000..e82e7cc550 --- /dev/null +++ b/examples/bluetooth/nimble/ble_phy/phy_cent/README.md @@ -0,0 +1,169 @@ +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | + +# BLE Central PHY Example + +(See the README.md file in the upper level 'examples' directory for more information about examples.) + +This example performs below functionalities: + +* Establishes a connection on LE 1M PHY and switch to LE 2M PHY once connection is established. Then perform GATT read operation against the specified peer. Disconnect the link once this is completed. + +* Change the default LE PHY to 2M/Coded and establish a connection on that PHY. Then perform GATT read operation against the specified peer. Disconnect the link once this is completed. + +This example aims at understanding how to establish connections on preferred PHY and changing LE PHY once the connection is established. + +To test this demo, use any BLE GATT server app that advertises support for the LE PHY service (0xABF2) and includes it in the GATT database. Also make sure device supports extended advertising. + +Note : + +* Make sure to run `python -m pip install --user -r $IDF_PATH/requirements.txt -r $IDF_PATH/tools/ble/requirements.txt` to install the dependency packages needed. +* Currently this Python utility is only supported on Linux (BLE communication is via BLuez + DBus). + +## How to Use Example + +Before project configuration and build, be sure to set the correct chip target using: + +```bash +idf.py set-target +``` + +### Hardware Required + +* A development board with ESP32-C3 SoC (e.g., ESP-WROVER-KIT, etc.) +* A USB cable for Power supply and programming + +See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. + +### Configure the Project + +Open the project configuration menu: + +```bash +idf.py menuconfig +``` + +### Build and Flash + +Run `idf.py -p PORT flash monitor` to build, flash and monitor the project. + +(To exit the serial monitor, type ``Ctrl-]``.) + +See the [Getting Started Guide](https://idf.espressif.com/) for full steps to configure and use ESP-IDF to build projects. + +## Example Output + +This is the console output on successful connection: + +``` +I (315) BTDM_INIT: BT controller compile version [05195c9] +I (315) phy_init: phy_version 912,d001756,Jun 2 2022,16:28:07 +I (355) system_api: Base MAC address is not set +I (355) system_api: read default base MAC address from EFUSE +I (355) BTDM_INIT: Bluetooth MAC: 84:f7:03:08:4d:8e + +I (355) NimBLE_BLE_PHY_CENT: BLE Host Task Started +I (465) NimBLE: Connection established +I (465) NimBLE: + +I (465) NimBLE: Prefered LE PHY set to LE_PHY_2M successfully +I (465) NimBLE: GATT procedure initiated: discover all services + +I (565) NimBLE: GATT procedure initiated: discover all characteristics; +I (565) NimBLE: start_handle=1 end_handle=5 + +I (765) NimBLE: GATT procedure initiated: discover all characteristics; +I (765) NimBLE: start_handle=6 end_handle=9 + +I (965) NimBLE: GATT procedure initiated: discover all characteristics; +I (965) NimBLE: start_handle=10 end_handle=65535 + +I (1015) NimBLE: LE PHY Update completed; status=0 conn_handle=1 tx_phy=2 rx_phy = 2 + +I (1165) NimBLE: GATT procedure initiated: discover all descriptors; +I (1165) NimBLE: chr_val_handle=8 end_handle=9 + +I (1265) NimBLE: GATT procedure initiated: discover all descriptors; +I (1265) NimBLE: chr_val_handle=12 end_handle=65535 + +I (1365) NimBLE: Service discovery complete; status=0 conn_handle=1 + +I (1365) NimBLE: GATT procedure initiated: read; +I (1365) NimBLE: att_handle=12 + +I (1375) NimBLE: GAP procedure initiated: terminate connection; conn_handle=1 hci_reason=19 + +I (1415) NimBLE: disconnect; reason=534 +I (1415) NimBLE: + +I (1415) NimBLE: Default LE PHY set successfully; tx_phy = 2, rx_phy = 2 +I (1505) NimBLE: Connection established +I (1505) NimBLE: + +I (1505) NimBLE: GATT procedure initiated: discover all services + +I (1615) NimBLE: GATT procedure initiated: discover all characteristics; +I (1615) NimBLE: start_handle=1 end_handle=5 + +I (1815) NimBLE: GATT procedure initiated: discover all characteristics; +I (1815) NimBLE: start_handle=6 end_handle=9 + +I (2015) NimBLE: LE PHY Update completed; status=0 conn_handle=1 tx_phy=2 rx_phy = 2 + +I (2015) NimBLE: GATT procedure initiated: discover all characteristics; +I (2025) NimBLE: start_handle=10 end_handle=65535 + +I (2215) NimBLE: GATT procedure initiated: discover all descriptors; +I (2215) NimBLE: chr_val_handle=8 end_handle=9 + +I (2315) NimBLE: GATT procedure initiated: discover all descriptors; +I (2315) NimBLE: chr_val_handle=12 end_handle=65535 + +I (2415) NimBLE: Service discovery complete; status=0 conn_handle=1 + +I (2415) NimBLE: GATT procedure initiated: read; +I (2415) NimBLE: att_handle=12 + +I (2425) NimBLE: GAP procedure initiated: terminate connection; conn_handle=1 hci_reason=19 + +I (2465) NimBLE: disconnect; reason=534 +I (2465) NimBLE: + +I (2465) NimBLE: Default LE PHY set successfully; tx_phy = 4, rx_phy = 4 +I (2555) NimBLE: Connection established +I (2555) NimBLE: + +I (2555) NimBLE: GATT procedure initiated: discover all services + +I (2665) NimBLE: GATT procedure initiated: discover all characteristics; +I (2665) NimBLE: start_handle=1 end_handle=5 + +I (2865) NimBLE: GATT procedure initiated: discover all characteristics; +I (2865) NimBLE: start_handle=6 end_handle=9 + +I (3065) NimBLE: LE PHY Update completed; status=0 conn_handle=1 tx_phy=3 rx_phy = 3 + +I (3065) NimBLE: GATT procedure initiated: discover all characteristics; +I (3075) NimBLE: start_handle=10 end_handle=65535 + +I (3265) NimBLE: GATT procedure initiated: discover all descriptors; +I (3265) NimBLE: chr_val_handle=8 end_handle=9 + +I (3365) NimBLE: GATT procedure initiated: discover all descriptors; +I (3365) NimBLE: chr_val_handle=12 end_handle=65535 + +I (3465) NimBLE: Service discovery complete; status=0 conn_handle=1 + +I (3465) NimBLE: GATT procedure initiated: read; +I (3465) NimBLE: att_handle=12 + +I (3475) NimBLE: GAP procedure initiated: terminate connection; conn_handle=1 hci_reason=19 + +I (3515) NimBLE: disconnect; reason=534 +I (3515) NimBLE: + +``` + +## Troubleshooting + +For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon. diff --git a/examples/bluetooth/nimble/ble_phy/phy_cent/main/CMakeLists.txt b/examples/bluetooth/nimble/ble_phy/phy_cent/main/CMakeLists.txt new file mode 100644 index 0000000000..18d510d988 --- /dev/null +++ b/examples/bluetooth/nimble/ble_phy/phy_cent/main/CMakeLists.txt @@ -0,0 +1,4 @@ +set(srcs "main.c") + +idf_component_register(SRCS "${srcs}" + INCLUDE_DIRS ".") diff --git a/examples/bluetooth/nimble/ble_phy/phy_cent/main/Kconfig.projbuild b/examples/bluetooth/nimble/ble_phy/phy_cent/main/Kconfig.projbuild new file mode 100644 index 0000000000..3f37c35634 --- /dev/null +++ b/examples/bluetooth/nimble/ble_phy/phy_cent/main/Kconfig.projbuild @@ -0,0 +1,16 @@ +menu "Example Configuration" + + config EXAMPLE_PEER_ADDR + string "Peer Address" + default "ADDR_ANY" + help + Enter the peer address in aa:bb:cc:dd:ee:ff form to connect to a specific peripheral + + config EXAMPLE_EXTENDED_ADV + bool + default y + prompt "Enable Extended Adv" + help + Use this option to enable extended advertising in the example + +endmenu diff --git a/examples/bluetooth/nimble/ble_phy/phy_cent/main/main.c b/examples/bluetooth/nimble/ble_phy/phy_cent/main/main.c new file mode 100644 index 0000000000..95d7184f5c --- /dev/null +++ b/examples/bluetooth/nimble/ble_phy/phy_cent/main/main.c @@ -0,0 +1,499 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#include "esp_log.h" +#include "nvs_flash.h" +/* BLE */ +#include "nimble/nimble_port.h" +#include "nimble/nimble_port_freertos.h" +#include "host/ble_hs.h" +#include "host/util/util.h" +#include "console/console.h" +#include "services/gap/ble_svc_gap.h" +#include "phy_cent.h" + +static const char *tag = "NimBLE_BLE_PHY_CENT"; +static int blecent_gap_event(struct ble_gap_event *event, void *arg); +static uint8_t peer_addr[6]; +static void blecent_scan(void); + +static uint8_t s_current_phy; +void ble_store_config_init(void); + +/** + * Performs GATT operation against the specified peer: + * 1. Reads the Supported LE PHY characteristic. + * + * If the peer does not support a required service, characteristic, or + * descriptor, then the peer lied when it claimed support for the alert + * notification service! When this happens, or if a GATT procedure fails, + * this function immediately terminates the connection. + */ +static void +blecent_read(const struct peer *peer) +{ + const struct peer_chr *chr; + int rc; + + /* Read the supported-new-alert-category characteristic. */ + chr = peer_chr_find_uuid(peer, + BLE_UUID16_DECLARE(LE_PHY_UUID16), + BLE_UUID16_DECLARE(LE_PHY_CHR_UUID16)); + if (chr == NULL) { + MODLOG_DFLT(ERROR, "Error: Peer doesn't support the Supported " + "LE PHY characteristic\n"); + goto err; + } + + rc = ble_gattc_read(peer->conn_handle, chr->chr.val_handle, + NULL, NULL); + if (rc != 0) { + MODLOG_DFLT(ERROR, "Error: Failed to read characteristic; rc=%d\n", + rc); + goto err; + } + + return; +err: + /* Terminate the connection. */ + ble_gap_terminate(peer->conn_handle, BLE_ERR_REM_USER_CONN_TERM); +} + +/** + * Called when service discovery of the specified peer has completed. + */ +static void +blecent_on_disc_complete(const struct peer *peer, int status, void *arg) +{ + + if (status != 0) { + /* Service discovery failed. Terminate the connection. */ + MODLOG_DFLT(ERROR, "Error: Service discovery failed; status=%d " + "conn_handle=%d\n", status, peer->conn_handle); + ble_gap_terminate(peer->conn_handle, BLE_ERR_REM_USER_CONN_TERM); + return; + } + + /* Service discovery has completed successfully. Now we have a complete + * list of services, characteristics, and descriptors that the peer + * supports. + */ + MODLOG_DFLT(INFO, "Service discovery complete; status=%d " + "conn_handle=%d\n", status, peer->conn_handle); + + /* Now perform GATT procedure against the peer: read + */ + blecent_read(peer); + + /* Terminate the connection once GATT procedure is completed */ + ble_gap_terminate(peer->conn_handle, BLE_ERR_REM_USER_CONN_TERM); +} + +/* Set preferred LE PHY after connection is established */ +void set_prefered_le_phy_after_conn(uint16_t conn_handle) +{ + uint8_t tx_phys_mask = 0, rx_phys_mask = 0; + + tx_phys_mask = BLE_HCI_LE_PHY_2M_PREF_MASK; + + rx_phys_mask = BLE_HCI_LE_PHY_2M_PREF_MASK; + + int rc = ble_gap_set_prefered_le_phy(conn_handle, tx_phys_mask, rx_phys_mask, 0); + if (rc == 0) { + MODLOG_DFLT(INFO, "Prefered LE PHY set to LE_PHY_2M successfully"); + } else { + MODLOG_DFLT(ERROR, "Failed to set prefered LE_PHY_2M"); + } +} + +/* Set default LE PHY before establishing connection */ +void set_default_le_phy_before_conn(uint8_t tx_phys_mask, uint8_t rx_phys_mask) +{ + int rc = ble_gap_set_prefered_default_le_phy(tx_phys_mask, rx_phys_mask); + if (rc == 0) { + MODLOG_DFLT(INFO, "Default LE PHY set successfully; tx_phy = %d, rx_phy = %d", + tx_phys_mask, rx_phys_mask); + } else { + MODLOG_DFLT(ERROR, "Failed to set default LE PHY"); + } +} + +/** + * Initiates the GAP general discovery procedure. + */ +static void +blecent_scan(void) +{ + uint8_t own_addr_type; + struct ble_gap_disc_params disc_params; + int rc; + + /* Figure out address to use while advertising (no privacy for now) */ + rc = ble_hs_id_infer_auto(0, &own_addr_type); + if (rc != 0) { + MODLOG_DFLT(ERROR, "error determining address type; rc=%d\n", rc); + return; + } + + /* Tell the controller to filter duplicates; we don't want to process + * repeated advertisements from the same device. + */ + disc_params.filter_duplicates = 1; + + /** + * Perform a passive scan. I.e., don't send follow-up scan requests to + * each advertiser. + */ + disc_params.passive = 1; + + /* Use defaults for the rest of the parameters. */ + disc_params.itvl = 0; + disc_params.window = 0; + disc_params.filter_policy = 0; + disc_params.limited = 0; + + rc = ble_gap_disc(own_addr_type, BLE_HS_FOREVER, &disc_params, + blecent_gap_event, NULL); + if (rc != 0) { + MODLOG_DFLT(ERROR, "Error initiating GAP discovery procedure; rc=%d\n", + rc); + } +} + +/** + * Indicates whether we should try to connect to the sender of the specified + * advertisement. The function returns a positive result if the device + * advertises connectability and support for the LE PHY service. + */ +#if CONFIG_EXAMPLE_EXTENDED_ADV +static int +ext_blecent_should_connect(const struct ble_gap_ext_disc_desc *disc) +{ + int offset = 0; + int ad_struct_len = 0; + + if (disc->legacy_event_type != BLE_HCI_ADV_RPT_EVTYPE_ADV_IND && + disc->legacy_event_type != BLE_HCI_ADV_RPT_EVTYPE_DIR_IND) { + return 0; + } + if (strlen(CONFIG_EXAMPLE_PEER_ADDR) && (strncmp(CONFIG_EXAMPLE_PEER_ADDR, "ADDR_ANY", strlen ("ADDR_ANY")) != 0)) { + ESP_LOGI(tag, "Peer address from menuconfig: %s", CONFIG_EXAMPLE_PEER_ADDR); + /* Convert string to address */ + sscanf(CONFIG_EXAMPLE_PEER_ADDR, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", + &peer_addr[5], &peer_addr[4], &peer_addr[3], + &peer_addr[2], &peer_addr[1], &peer_addr[0]); + if (memcmp(peer_addr, disc->addr.val, sizeof(disc->addr.val)) != 0) { + return 0; + } + } + + /* The device has to advertise support LE PHY UUID (0xABF2). + */ + do { + ad_struct_len = disc->data[offset]; + + if (!ad_struct_len) { + break; + } + + /* Search if LE PHY UUID is advertised */ + if (disc->data[offset] == 0x03 && disc->data[offset + 1] == 0x03) { + if ( disc->data[offset + 2] == 0xAB && disc->data[offset + 3] == 0xF2 ) { + return 1; + } + } + + offset += ad_struct_len + 1; + + } while ( offset < disc->length_data ); + return 0; +} +#else +static int +blecent_should_connect(const struct ble_gap_disc_desc *disc) +{ + struct ble_hs_adv_fields fields; + int rc; + int i; + + /* The device has to be advertising connectability. */ + if (disc->event_type != BLE_HCI_ADV_RPT_EVTYPE_ADV_IND && + disc->event_type != BLE_HCI_ADV_RPT_EVTYPE_DIR_IND) { + return 0; + } + + rc = ble_hs_adv_parse_fields(&fields, disc->data, disc->length_data); + if (rc != 0) { + return rc; + } + + if (strlen(CONFIG_EXAMPLE_PEER_ADDR) && (strncmp(CONFIG_EXAMPLE_PEER_ADDR, "ADDR_ANY", strlen("ADDR_ANY")) != 0)) { + ESP_LOGI(tag, "Peer address from menuconfig: %s", CONFIG_EXAMPLE_PEER_ADDR); + /* Convert string to address */ + sscanf(CONFIG_EXAMPLE_PEER_ADDR, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", + &peer_addr[5], &peer_addr[4], &peer_addr[3], + &peer_addr[2], &peer_addr[1], &peer_addr[0]); + if (memcmp(peer_addr, disc->addr.val, sizeof(disc->addr.val)) != 0) { + return 0; + } + } + + /* The device has to advertise support for LE PHY UUID (0xABF2) + */ + for (i = 0; i < fields.num_uuids16; i++) { + if (ble_uuid_u16(&fields.uuids16[i].u) == LE_PHY_UUID16) { + return 1; + } + } + + return 0; +} +#endif + +/** + * Connects to the sender of the specified advertisement of it looks + * interesting. A device is "interesting" if it advertises connectability and + * support for the LE PHY service. + */ +static void +blecent_connect_if_interesting(void *disc) +{ + uint8_t own_addr_type; + int rc; + ble_addr_t *addr; + + /* Don't do anything if we don't care about this advertiser. */ +#if CONFIG_EXAMPLE_EXTENDED_ADV + if (!ext_blecent_should_connect((struct ble_gap_ext_disc_desc *)disc)) { + return; + } +#else + if (!blecent_should_connect((struct ble_gap_disc_desc *)disc)) { + return; + } +#endif + + /* Scanning must be stopped before a connection can be initiated. */ + rc = ble_gap_disc_cancel(); + if (rc != 0) { + MODLOG_DFLT(DEBUG, "Failed to cancel scan; rc=%d\n", rc); + return; + } + + /* Figure out address to use for connect (no privacy for now) */ + rc = ble_hs_id_infer_auto(0, &own_addr_type); + if (rc != 0) { + MODLOG_DFLT(ERROR, "error determining address type; rc=%d\n", rc); + return; + } + + /* Try to connect the the advertiser. Allow 30 seconds (30000 ms) for + * timeout. + */ +#if CONFIG_EXAMPLE_EXTENDED_ADV + addr = &((struct ble_gap_ext_disc_desc *)disc)->addr; +#else + addr = &((struct ble_gap_disc_desc *)disc)->addr; +#endif + + rc = ble_gap_connect(own_addr_type, addr, 30000, NULL, + blecent_gap_event, NULL); + if (rc != 0) { + MODLOG_DFLT(ERROR, "Error: Failed to connect to device; addr_type=%d " + "addr=%s; rc=%d\n", + addr->type, addr_str(addr->val), rc); + return; + } +} + +/** + * The nimble host executes this callback when a GAP event occurs. The + * application associates a GAP event callback with each connection that is + * established. blecent uses the same callback for all connections. + * + * @param event The event being signalled. + * @param arg Application-specified argument; unused by + * blecent. + * + * @return 0 if the application successfully handled the + * event; nonzero on failure. The semantics + * of the return code is specific to the + * particular GAP event being signalled. + */ +static int +blecent_gap_event(struct ble_gap_event *event, void *arg) +{ + struct ble_gap_conn_desc desc; + struct ble_hs_adv_fields fields; + int rc; + + switch (event->type) { + case BLE_GAP_EVENT_DISC: + rc = ble_hs_adv_parse_fields(&fields, event->disc.data, + event->disc.length_data); + if (rc != 0) { + return 0; + } + + /* An advertisment report was received during GAP discovery. */ + print_adv_fields(&fields); + + /* Try to connect to the advertiser if it looks interesting. */ + blecent_connect_if_interesting(&event->disc); + return 0; + + case BLE_GAP_EVENT_CONNECT: + /* A new connection was established or a connection attempt failed. */ + if (event->connect.status == 0) { + /* Connection successfully established. */ + MODLOG_DFLT(INFO, "Connection established "); + + rc = ble_gap_conn_find(event->connect.conn_handle, &desc); + assert(rc == 0); + print_conn_desc(&desc); + MODLOG_DFLT(INFO, "\n"); + + /* Remember peer. */ + rc = peer_add(event->connect.conn_handle); + if (rc != 0) { + MODLOG_DFLT(ERROR, "Failed to add peer; rc=%d\n", rc); + return 0; + } + + if (s_current_phy == BLE_HCI_LE_PHY_1M_PREF_MASK) { + /* Update LE PHY from 1M to 2M */ + set_prefered_le_phy_after_conn(event->connect.conn_handle); + } + /* Perform service discovery. */ + rc = peer_disc_all(event->connect.conn_handle, + blecent_on_disc_complete, NULL); + if (rc != 0) { + MODLOG_DFLT(ERROR, "Failed to discover services; rc=%d\n", rc); + return 0; + } + } else { + /* Connection attempt failed; resume scanning. */ + MODLOG_DFLT(ERROR, "Error: Connection failed; status=%d\n", + event->connect.status); + blecent_scan(); + } + + return 0; + + case BLE_GAP_EVENT_DISCONNECT: + /* Connection terminated. */ + MODLOG_DFLT(INFO, "disconnect; reason=%d ", event->disconnect.reason); + print_conn_desc(&event->disconnect.conn); + MODLOG_DFLT(INFO, "\n"); + + /* Forget about peer. */ + peer_delete(event->disconnect.conn.conn_handle); + + switch (s_current_phy) { + case BLE_HCI_LE_PHY_1M_PREF_MASK: + /* Setting current phy to create connection on 2M PHY */ + s_current_phy = BLE_HCI_LE_PHY_2M_PREF_MASK; + break; + + case BLE_HCI_LE_PHY_2M_PREF_MASK: + /* Setting current phy to create connection on CODED PHY */ + s_current_phy = BLE_HCI_LE_PHY_CODED_PREF_MASK; + break; + + case BLE_HCI_LE_PHY_CODED_PREF_MASK: + return 0; + } + set_default_le_phy_before_conn(s_current_phy, s_current_phy); + blecent_scan(); + return 0; + + case BLE_GAP_EVENT_DISC_COMPLETE: + MODLOG_DFLT(INFO, "discovery complete; reason=%d\n", + event->disc_complete.reason); + return 0; + +#if CONFIG_EXAMPLE_EXTENDED_ADV + case BLE_GAP_EVENT_EXT_DISC: + /* An advertisment report was received during GAP discovery. */ + ext_print_adv_report(&event->disc); + + blecent_connect_if_interesting(&event->disc); + return 0; +#endif + + case BLE_GAP_EVENT_PHY_UPDATE_COMPLETE: + MODLOG_DFLT(INFO, "LE PHY Update completed; status=%d conn_handle=%d tx_phy=%d " + "rx_phy = %d\n", event->phy_updated.status, + event->phy_updated.conn_handle, event->phy_updated.tx_phy, + event->phy_updated.rx_phy); + return 0; + + default: + return 0; + } +} + +static void +blecent_on_reset(int reason) +{ + MODLOG_DFLT(ERROR, "Resetting state; reason=%d\n", reason); +} + +static void +blecent_on_sync(void) +{ + int rc; + + /* Make sure we have proper identity address set (public preferred) */ + rc = ble_hs_util_ensure_addr(0); + assert(rc == 0); + + s_current_phy = BLE_HCI_LE_PHY_1M_PREF_MASK; + /* Begin scanning for a peripheral to connect to. */ + blecent_scan(); +} + +void blecent_host_task(void *param) +{ + ESP_LOGI(tag, "BLE Host Task Started"); + /* This function will return only when nimble_port_stop() is executed */ + nimble_port_run(); + + nimble_port_freertos_deinit(); +} + +void +app_main(void) +{ + int rc; + /* Initialize NVS — it is used to store PHY calibration data */ + esp_err_t ret = nvs_flash_init(); + if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { + ESP_ERROR_CHECK(nvs_flash_erase()); + ret = nvs_flash_init(); + } + ESP_ERROR_CHECK(ret); + + nimble_port_init(); + /* Configure the host. */ + ble_hs_cfg.reset_cb = blecent_on_reset; + ble_hs_cfg.sync_cb = blecent_on_sync; + ble_hs_cfg.store_status_cb = ble_store_util_status_rr; + + /* Initialize data structures to track connected peers. */ + rc = peer_init(MYNEWT_VAL(BLE_MAX_CONNECTIONS), 64, 64, 64); + assert(rc == 0); + + /* Set the default device name. */ + rc = ble_svc_gap_device_name_set("blecent-phy"); + assert(rc == 0); + + /* XXX Need to have template for store */ + ble_store_config_init(); + + nimble_port_freertos_init(blecent_host_task); + +} diff --git a/examples/bluetooth/nimble/ble_phy/phy_cent/main/phy_cent.h b/examples/bluetooth/nimble/ble_phy/phy_cent/main/phy_cent.h new file mode 100644 index 0000000000..1db6bfccc8 --- /dev/null +++ b/examples/bluetooth/nimble/ble_phy/phy_cent/main/phy_cent.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#ifndef H_PHY_CENT_ +#define H_PHY_CENT_ + +#include "modlog/modlog.h" +#include "esp_central.h" +#ifdef __cplusplus +extern "C" { +#endif + +struct ble_hs_adv_fields; +struct ble_gap_conn_desc; +struct ble_hs_cfg; +union ble_store_value; +union ble_store_key; + +#define LE_PHY_UUID16 0xABF2 +#define LE_PHY_CHR_UUID16 0xABF3 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/examples/bluetooth/nimble/ble_phy/phy_cent/sdkconfig.defaults b/examples/bluetooth/nimble/ble_phy/phy_cent/sdkconfig.defaults new file mode 100644 index 0000000000..81960c1079 --- /dev/null +++ b/examples/bluetooth/nimble/ble_phy/phy_cent/sdkconfig.defaults @@ -0,0 +1,13 @@ +# Override some defaults so BT stack is enabled +# in this example + +# +# BT config +# +CONFIG_BT_ENABLED=y +CONFIG_BTDM_CTRL_MODE_BLE_ONLY=y +CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=n +CONFIG_BTDM_CTRL_MODE_BTDM=n +CONFIG_BT_BLUEDROID_ENABLED=n +CONFIG_BT_NIMBLE_ENABLED=y +CONFIG_BT_NIMBLE_EXT_ADV=y diff --git a/examples/bluetooth/nimble/ble_phy/phy_prph/CMakeLists.txt b/examples/bluetooth/nimble/ble_phy/phy_prph/CMakeLists.txt new file mode 100644 index 0000000000..550d0a0827 --- /dev/null +++ b/examples/bluetooth/nimble/ble_phy/phy_prph/CMakeLists.txt @@ -0,0 +1,8 @@ +# The following lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +set(EXTRA_COMPONENT_DIRS $ {CMAKE_CURRENT_LIST_DIR} / .. / .. / common / nimble_peripheral_utils) + +include($ENV{IDF_PATH} / tools / cmake / project.cmake) +project(phy_prph) diff --git a/examples/bluetooth/nimble/ble_phy/phy_prph/README.md b/examples/bluetooth/nimble/ble_phy/phy_prph/README.md new file mode 100644 index 0000000000..562f185257 --- /dev/null +++ b/examples/bluetooth/nimble/ble_phy/phy_prph/README.md @@ -0,0 +1,171 @@ +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | + +# BLE Peripheral PHY Example + +(See the README.md file in the upper level 'examples' directory for more information about examples.) + +This example performs below functionalities: + +* Establishes a connection on LE 1M PHY and switch to LE 2M PHY once connection is established. Then perform GATT read operation against the specified peer. Disconnect the link once this is completed. + +* Change the default LE PHY to 2M/Coded and establish a connection on that PHY. Then perform GATT read operation against the specified peer. Disconnect the link once this is completed. + +This example aims at understanding how to establish connections on preferred PHY and changing LE PHY once the connection is established. + +To test this demo, use any BLE GATT client app that supports extended advertising. + +Note : + +* Make sure to run `python -m pip install --user -r $IDF_PATH/requirements.txt -r $IDF_PATH/tools/ble/requirements.txt` to install the dependency packages needed. +* Currently this Python utility is only supported on Linux (BLE communication is via BLuez + DBus). + +## How to Use Example + +Before project configuration and build, be sure to set the correct chip target using: + +```bash +idf.py set-target +``` + +### Hardware Required + +* A development board with ESP32-C3 SoC (e.g., ESP-WROVER-KIT, etc.) +* A USB cable for Power supply and programming + +See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. + +### Configure the Project + +Open the project configuration menu: + +```bash +idf.py menuconfig +``` + +### Build and Flash + +Run `idf.py -p PORT flash monitor` to build, flash and monitor the project. + +(To exit the serial monitor, type ``Ctrl-]``.) + +See the [Getting Started Guide](https://idf.espressif.com/) for full steps to configure and use ESP-IDF to build projects. + +## Example Output + +This is the console output on successful connection: + +``` +I (322) BTDM_INIT: BT controller compile version [05195c9] +I (322) phy_init: phy_version 912,d001756,Jun 2 2022,16:28:07 +I (362) system_api: Base MAC address is not set +I (362) system_api: read default base MAC address from EFUSE +I (362) BTDM_INIT: Bluetooth MAC: 84:f7:03:05:a5:f6 + +I (362) NimBLE_BLE_PHY_PRPH: BLE Host Task Started +I (372) NimBLE: Device Address: +I (372) NimBLE: 84:f7:03:05:a5:f6 +I (382) NimBLE: + +I (382) uart: queue free spaces: 8 +I (4782) NimBLE: connection established; status=0 +I (4782) NimBLE: handle=1 our_ota_addr_type=0 our_ota_addr= +I (4782) NimBLE: 84:f7:03:05:a5:f6 +I (4782) NimBLE: our_id_addr_type=0 our_id_addr= +I (4792) NimBLE: 84:f7:03:05:a5:f6 +I (4792) NimBLE: peer_ota_addr_type=0 peer_ota_addr= +I (4802) NimBLE: 84:f7:03:08:4d:8e +I (4802) NimBLE: peer_id_addr_type=0 peer_id_addr= +I (4812) NimBLE: 84:f7:03:08:4d:8e +I (4812) NimBLE: conn_itvl=40 conn_latency=0 supervision_timeout=256 encrypted=0 authenticated=0 bonded=0 + +I (4822) NimBLE: + +I (4822) NimBLE: advertise complete; reason=0 +I (4832) NimBLE: LE PHY Update completed; status=0 conn_handle=1 tx_phy=1 rx_phy = 0 + +I (5322) NimBLE: LE PHY Update completed; status=0 conn_handle=1 tx_phy=2 rx_phy = 2 + +I (5732) NimBLE: disconnect; reason=531 +I (5732) NimBLE: handle=1 our_ota_addr_type=0 our_ota_addr= +I (5732) NimBLE: 84:f7:03:05:a5:f6 +I (5732) NimBLE: our_id_addr_type=0 our_id_addr= +I (5742) NimBLE: 84:f7:03:05:a5:f6 +I (5742) NimBLE: peer_ota_addr_type=0 peer_ota_addr= +I (5752) NimBLE: 84:f7:03:08:4d:8e +I (5752) NimBLE: peer_id_addr_type=0 peer_id_addr= +I (5762) NimBLE: 84:f7:03:08:4d:8e +I (5762) NimBLE: conn_itvl=40 conn_latency=0 supervision_timeout=256 encrypted=0 authenticated=0 bonded=0 + +I (5772) NimBLE: + +I (5772) NimBLE: Default LE PHY set successfully +I (5822) NimBLE: connection established; status=0 +I (5822) NimBLE: handle=1 our_ota_addr_type=0 our_ota_addr= +I (5822) NimBLE: 84:f7:03:05:a5:f6 +I (5822) NimBLE: our_id_addr_type=0 our_id_addr= +I (5832) NimBLE: 84:f7:03:05:a5:f6 +I (5832) NimBLE: peer_ota_addr_type=0 peer_ota_addr= +I (5842) NimBLE: 84:f7:03:08:4d:8e +I (5842) NimBLE: peer_id_addr_type=0 peer_id_addr= +I (5852) NimBLE: 84:f7:03:08:4d:8e +I (5852) NimBLE: conn_itvl=40 conn_latency=0 supervision_timeout=256 encrypted=0 authenticated=0 bonded=0 + +I (5862) NimBLE: + +I (5862) NimBLE: advertise complete; reason=0 +I (5872) NimBLE: LE PHY Update completed; status=0 conn_handle=1 tx_phy=1 rx_phy = 0 + +I (6322) NimBLE: LE PHY Update completed; status=0 conn_handle=1 tx_phy=2 rx_phy = 2 + +I (6782) NimBLE: disconnect; reason=531 +I (6782) NimBLE: handle=1 our_ota_addr_type=0 our_ota_addr= +I (6782) NimBLE: 84:f7:03:05:a5:f6 +I (6782) NimBLE: our_id_addr_type=0 our_id_addr= +I (6792) NimBLE: 84:f7:03:05:a5:f6 +I (6792) NimBLE: peer_ota_addr_type=0 peer_ota_addr= +I (6802) NimBLE: 84:f7:03:08:4d:8e +I (6802) NimBLE: peer_id_addr_type=0 peer_id_addr= +I (6812) NimBLE: 84:f7:03:08:4d:8e +I (6812) NimBLE: conn_itvl=40 conn_latency=0 supervision_timeout=256 encrypted=0 authenticated=0 bonded=0 + +I (6822) NimBLE: + +I (6822) NimBLE: Default LE PHY set successfully +I (6872) NimBLE: connection established; status=0 +I (6872) NimBLE: handle=1 our_ota_addr_type=0 our_ota_addr= +I (6872) NimBLE: 84:f7:03:05:a5:f6 +I (6872) NimBLE: our_id_addr_type=0 our_id_addr= +I (6882) NimBLE: 84:f7:03:05:a5:f6 +I (6882) NimBLE: peer_ota_addr_type=0 peer_ota_addr= +I (6892) NimBLE: 84:f7:03:08:4d:8e +I (6892) NimBLE: peer_id_addr_type=0 peer_id_addr= +I (6902) NimBLE: 84:f7:03:08:4d:8e +I (6902) NimBLE: conn_itvl=40 conn_latency=0 supervision_timeout=256 encrypted=0 authenticated=0 bonded=0 + +I (6912) NimBLE: + +I (6912) NimBLE: advertise complete; reason=0 +I (6922) NimBLE: LE PHY Update completed; status=0 conn_handle=1 tx_phy=1 rx_phy = 0 + +I (7372) NimBLE: LE PHY Update completed; status=0 conn_handle=1 tx_phy=3 rx_phy = 3 + +I (7832) NimBLE: disconnect; reason=531 +I (7832) NimBLE: handle=1 our_ota_addr_type=0 our_ota_addr= +I (7832) NimBLE: 84:f7:03:05:a5:f6 +I (7832) NimBLE: our_id_addr_type=0 our_id_addr= +I (7842) NimBLE: 84:f7:03:05:a5:f6 +I (7842) NimBLE: peer_ota_addr_type=0 peer_ota_addr= +I (7852) NimBLE: 84:f7:03:08:4d:8e +I (7852) NimBLE: peer_id_addr_type=0 peer_id_addr= +I (7862) NimBLE: 84:f7:03:08:4d:8e +I (7862) NimBLE: conn_itvl=40 conn_latency=0 supervision_timeout=256 encrypted=0 authenticated=0 bonded=0 + +I (7872) NimBLE: + + +``` + +## Troubleshooting + +For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon. diff --git a/examples/bluetooth/nimble/ble_phy/phy_prph/main/CMakeLists.txt b/examples/bluetooth/nimble/ble_phy/phy_prph/main/CMakeLists.txt new file mode 100644 index 0000000000..0d03be369b --- /dev/null +++ b/examples/bluetooth/nimble/ble_phy/phy_prph/main/CMakeLists.txt @@ -0,0 +1,5 @@ +set(srcs "main.c" + "gatt_svr.c") + +idf_component_register(SRCS "${srcs}" + INCLUDE_DIRS ".") diff --git a/examples/bluetooth/nimble/ble_phy/phy_prph/main/Kconfig.projbuild b/examples/bluetooth/nimble/ble_phy/phy_prph/main/Kconfig.projbuild new file mode 100644 index 0000000000..de90ea8627 --- /dev/null +++ b/examples/bluetooth/nimble/ble_phy/phy_prph/main/Kconfig.projbuild @@ -0,0 +1,55 @@ +menu "Example Configuration" + + choice EXAMPLE_USE_IO_TYPE + prompt "I/O Capability" + default BLE_SM_IO_CAP_NO_IO + help + I/O capability of device. + + config BLE_SM_IO_CAP_DISP_ONLY + bool "DISPLAY ONLY" + config BLE_SM_IO_CAP_DISP_YES_NO + bool "DISPLAY YESNO" + config BLE_SM_IO_CAP_KEYBOARD_ONLY + bool "KEYBOARD ONLY" + config BLE_SM_IO_CAP_NO_IO + bool "Just works" + config BLE_SM_IO_CAP_KEYBOARD_DISP + bool "Both KEYBOARD & DISPLAY" + endchoice + + config EXAMPLE_IO_TYPE + int + default 0 if BLE_SM_IO_CAP_DISP_ONLY + default 1 if BLE_SM_IO_CAP_DISP_YES_NO + default 2 if BLE_SM_IO_CAP_KEYBOARD_ONLY + default 3 if BLE_SM_IO_CAP_NO_IO + default 4 if BLE_SM_IO_CAP_KEYBOARD_DISP + + config EXAMPLE_BONDING + bool + prompt "Use Bonding" + help + Use this option to enable/disable bonding. + + config EXAMPLE_MITM + bool + prompt "MITM security" + help + Use this option to enable/disable MITM security. + + config EXAMPLE_USE_SC + bool + depends on BT_NIMBLE_SM_SC + prompt "Use Secure Connection feature" + help + Use this option to enable/disable Security Manager Secure Connection 4.2 feature. + + config EXAMPLE_EXTENDED_ADV + bool + default y + prompt "Enable Extended Adv" + help + Use this option to enable extended advertising in the example + +endmenu diff --git a/examples/bluetooth/nimble/ble_phy/phy_prph/main/gatt_svr.c b/examples/bluetooth/nimble/ble_phy/phy_prph/main/gatt_svr.c new file mode 100644 index 0000000000..ce3db2a024 --- /dev/null +++ b/examples/bluetooth/nimble/ble_phy/phy_prph/main/gatt_svr.c @@ -0,0 +1,125 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#include +#include +#include +#include "host/ble_hs.h" +#include "host/ble_uuid.h" +#include "services/gap/ble_svc_gap.h" +#include "services/gatt/ble_svc_gatt.h" +#include "phy_prph.h" + +static int +gatt_svr_chr_access_le_phy(uint16_t conn_handle, uint16_t attr_handle, + struct ble_gatt_access_ctxt *ctxt, + void *arg); + +static const struct ble_gatt_svc_def gatt_svr_svcs_le_phy[] = { + { + /*** Service: LE PHY. */ + .type = BLE_GATT_SVC_TYPE_PRIMARY, + .uuid = BLE_UUID16_DECLARE(LE_PHY_UUID16), + .characteristics = (struct ble_gatt_chr_def[]) + { { + /*** Characteristic */ + .uuid = BLE_UUID16_DECLARE(LE_PHY_CHR_UUID16), + .access_cb = gatt_svr_chr_access_le_phy, + .flags = BLE_GATT_CHR_F_READ | BLE_GATT_CHR_F_READ_ENC, + }, { + 0, /* No more characteristics in this service. */ + } + }, + }, + + { + 0, /* No more services. */ + }, +}; + +static int +gatt_svr_chr_access_le_phy(uint16_t conn_handle, uint16_t attr_handle, + struct ble_gatt_access_ctxt *ctxt, + void *arg) +{ + const ble_uuid_t *uuid; + int rand_num; + int rc; + + uuid = ctxt->chr->uuid; + + /* Determine which characteristic is being accessed by examining its + * 128-bit UUID. + */ + + if (ble_uuid_cmp(uuid, BLE_UUID16_DECLARE(LE_PHY_CHR_UUID16)) == 0) { + assert(ctxt->op == BLE_GATT_ACCESS_OP_READ_CHR); + + /* Respond with a 32-bit random number. */ + rand_num = rand(); + rc = os_mbuf_append(ctxt->om, &rand_num, sizeof rand_num); + return rc == 0 ? 0 : BLE_ATT_ERR_INSUFFICIENT_RES; + } + + /* Unknown characteristic; the nimble stack should not have called this + * function. + */ + assert(0); + return BLE_ATT_ERR_UNLIKELY; +} + +void +gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *arg) +{ + char buf[BLE_UUID_STR_LEN]; + + switch (ctxt->op) { + case BLE_GATT_REGISTER_OP_SVC: + MODLOG_DFLT(DEBUG, "registered service %s with handle=%d\n", + ble_uuid_to_str(ctxt->svc.svc_def->uuid, buf), + ctxt->svc.handle); + break; + + case BLE_GATT_REGISTER_OP_CHR: + MODLOG_DFLT(DEBUG, "registering characteristic %s with " + "def_handle=%d val_handle=%d\n", + ble_uuid_to_str(ctxt->chr.chr_def->uuid, buf), + ctxt->chr.def_handle, + ctxt->chr.val_handle); + break; + + case BLE_GATT_REGISTER_OP_DSC: + MODLOG_DFLT(DEBUG, "registering descriptor %s with handle=%d\n", + ble_uuid_to_str(ctxt->dsc.dsc_def->uuid, buf), + ctxt->dsc.handle); + break; + + default: + assert(0); + break; + } +} + +int +gatt_svr_init_le_phy(void) +{ + int rc; + + ble_svc_gap_init(); + ble_svc_gatt_init(); + + rc = ble_gatts_count_cfg(gatt_svr_svcs_le_phy); + if (rc != 0) { + return rc; + } + + rc = ble_gatts_add_svcs(gatt_svr_svcs_le_phy); + if (rc != 0) { + return rc; + } + + return 0; +} diff --git a/examples/bluetooth/nimble/ble_phy/phy_prph/main/main.c b/examples/bluetooth/nimble/ble_phy/phy_prph/main/main.c new file mode 100644 index 0000000000..2b34bdd16e --- /dev/null +++ b/examples/bluetooth/nimble/ble_phy/phy_prph/main/main.c @@ -0,0 +1,440 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#include "esp_log.h" +#include "nvs_flash.h" +/* BLE */ +#include "nimble/nimble_port.h" +#include "nimble/nimble_port_freertos.h" +#include "host/ble_hs.h" +#include "host/util/util.h" +#include "console/console.h" +#include "services/gap/ble_svc_gap.h" +#include "phy_prph.h" + +#if CONFIG_EXAMPLE_EXTENDED_ADV +static uint8_t ext_adv_pattern_1M[] = { + 0x02, 0x01, 0x06, + 0x03, 0x03, 0xab, 0xcd, + 0x03, 0x03, 0xAB, 0xF2, + 0x0e, 0X09, 'b', 'l', 'e', 'p', 'r', 'p', 'h', '-', 'p', 'h', 'y', '-', '1', 'M', +}; + +static uint8_t ext_adv_pattern_2M[] = { + 0x02, 0x01, 0x06, + 0x03, 0x03, 0xab, 0xcd, + 0x03, 0x03, 0xAB, 0xF2, + 0x0e, 0X09, 'b', 'l', 'e', 'p', 'r', 'p', 'h', '-', 'p', 'h', 'y', '-', '2', 'M', +}; + +static uint8_t ext_adv_pattern_coded[] = { + 0x02, 0x01, 0x06, + 0x03, 0x03, 0xab, 0xcd, + 0x03, 0x03, 0xAB, 0xF2, + 0x11, 0X09, 'b', 'l', 'e', 'p', 'r', 'p', 'h', '-', 'p', 'h', 'y', '-', 'c', 'o', 'd', 'e', + 'd', +}; +#endif + +static const char *tag = "NimBLE_BLE_PHY_PRPH"; +static int bleprph_gap_event(struct ble_gap_event *event, void *arg); +static uint8_t own_addr_type; + +static uint8_t s_current_phy; +void ble_store_config_init(void); + +/* Set default LE PHY before establishing connection */ +void set_default_le_phy_before_conn(uint8_t tx_phys_mask, uint8_t rx_phys_mask) +{ + int rc = ble_gap_set_prefered_default_le_phy(tx_phys_mask, rx_phys_mask); + if (rc == 0) { + MODLOG_DFLT(INFO, "Default LE PHY set successfully"); + } else { + MODLOG_DFLT(ERROR, "Failed to set default LE PHY"); + } +} + +/** + * Logs information about a connection to the console. + */ +static void +bleprph_print_conn_desc(struct ble_gap_conn_desc *desc) +{ + MODLOG_DFLT(INFO, "handle=%d our_ota_addr_type=%d our_ota_addr=", + desc->conn_handle, desc->our_ota_addr.type); + print_addr(desc->our_ota_addr.val); + MODLOG_DFLT(INFO, " our_id_addr_type=%d our_id_addr=", + desc->our_id_addr.type); + print_addr(desc->our_id_addr.val); + MODLOG_DFLT(INFO, " peer_ota_addr_type=%d peer_ota_addr=", + desc->peer_ota_addr.type); + print_addr(desc->peer_ota_addr.val); + MODLOG_DFLT(INFO, " peer_id_addr_type=%d peer_id_addr=", + desc->peer_id_addr.type); + print_addr(desc->peer_id_addr.val); + MODLOG_DFLT(INFO, " conn_itvl=%d conn_latency=%d supervision_timeout=%d " + "encrypted=%d authenticated=%d bonded=%d\n", + desc->conn_itvl, desc->conn_latency, + desc->supervision_timeout, + desc->sec_state.encrypted, + desc->sec_state.authenticated, + desc->sec_state.bonded); +} + +#if CONFIG_EXAMPLE_EXTENDED_ADV +static struct os_mbuf * +ext_get_data(uint8_t ext_adv_pattern[], int size) +{ + struct os_mbuf *data; + int rc; + data = os_msys_get_pkthdr(size, 0); + assert(data); + rc = os_mbuf_append(data, ext_adv_pattern, size); + assert(rc == 0); + return data; +} + +/** + * Enables advertising with the following parameters: + * o General discoverable mode. + * o Undirected connectable mode. + */ +static void +ext_bleprph_advertise(void) +{ + struct ble_gap_ext_adv_params params; + struct os_mbuf *data = NULL; + uint8_t instance = 1; + int rc; + + /* use defaults for non-set params */ + memset (¶ms, 0, sizeof(params)); + + /* enable connectable advertising */ + params.connectable = 1; + params.scannable = 1; + params.legacy_pdu = 1; + + /* advertise using random addr */ + params.own_addr_type = BLE_OWN_ADDR_PUBLIC; + + /* Set current phy; get mbuf for scan rsp data; fill mbuf with scan rsp data */ + switch (s_current_phy) { + case BLE_HCI_LE_PHY_1M_PREF_MASK: + params.primary_phy = BLE_HCI_LE_PHY_1M; + params.secondary_phy = BLE_HCI_LE_PHY_1M; + data = ext_get_data(ext_adv_pattern_1M, sizeof(ext_adv_pattern_1M)); + break; + + case BLE_HCI_LE_PHY_2M_PREF_MASK: + params.primary_phy = BLE_HCI_LE_PHY_1M; + params.secondary_phy = BLE_HCI_LE_PHY_2M; + data = ext_get_data(ext_adv_pattern_2M, sizeof(ext_adv_pattern_2M)); + break; + + case BLE_HCI_LE_PHY_CODED_PREF_MASK: + params.primary_phy = BLE_HCI_LE_PHY_CODED; + params.secondary_phy = BLE_HCI_LE_PHY_CODED; + data = ext_get_data(ext_adv_pattern_coded, sizeof(ext_adv_pattern_coded)); + break; + } + + //params.tx_power = 127; + params.sid = 1; + + params.itvl_min = BLE_GAP_ADV_FAST_INTERVAL1_MIN; + params.itvl_max = BLE_GAP_ADV_FAST_INTERVAL1_MIN; + + /* configure instance 0 */ + rc = ble_gap_ext_adv_configure(instance, ¶ms, NULL, + bleprph_gap_event, NULL); + assert (rc == 0); + + rc = ble_gap_ext_adv_set_data(instance, data); + assert (rc == 0); + + /* start advertising */ + rc = ble_gap_ext_adv_start(instance, 0, 0); + assert (rc == 0); +} +#else +/** + * Enables advertising with the following parameters: + * o General discoverable mode. + * o Undirected connectable mode. + */ +static void +bleprph_advertise(void) +{ + struct ble_gap_adv_params adv_params; + struct ble_hs_adv_fields fields; + const char *name; + int rc; + + /** + * Set the advertisement data included in our advertisements: + * o Flags (indicates advertisement type and other general info). + * o Advertising tx power. + * o Device name. + * o 16-bit service UUIDs (alert notifications). + */ + + memset(&fields, 0, sizeof fields); + + /* Advertise two flags: + * o Discoverability in forthcoming advertisement (general) + * o BLE-only (BR/EDR unsupported). + */ + fields.flags = BLE_HS_ADV_F_DISC_GEN | + BLE_HS_ADV_F_BREDR_UNSUP; + + /* Indicate that the TX power level field should be included; have the + * stack fill this value automatically. This is done by assigning the + * special value BLE_HS_ADV_TX_PWR_LVL_AUTO. + */ + fields.tx_pwr_lvl_is_present = 1; + fields.tx_pwr_lvl = BLE_HS_ADV_TX_PWR_LVL_AUTO; + + name = ble_svc_gap_device_name(); + fields.name = (uint8_t *)name; + fields.name_len = strlen(name); + fields.name_is_complete = 1; + + fields.uuids16 = (ble_uuid16_t[]) { + BLE_UUID16_INIT(LE_PHY_UUID16) + }; + fields.num_uuids16 = 1; + fields.uuids16_is_complete = 1; + + rc = ble_gap_adv_set_fields(&fields); + if (rc != 0) { + MODLOG_DFLT(ERROR, "error setting advertisement data; rc=%d\n", rc); + return; + } + + /* Begin advertising. */ + memset(&adv_params, 0, sizeof adv_params); + adv_params.conn_mode = BLE_GAP_CONN_MODE_UND; + adv_params.disc_mode = BLE_GAP_DISC_MODE_GEN; + rc = ble_gap_adv_start(own_addr_type, NULL, BLE_HS_FOREVER, + &adv_params, bleprph_gap_event, NULL); + if (rc != 0) { + MODLOG_DFLT(ERROR, "error enabling advertisement; rc=%d\n", rc); + return; + } +} +#endif +/** + * The nimble host executes this callback when a GAP event occurs. The + * application associates a GAP event callback with each connection that forms. + * bleprph uses the same callback for all connections. + * + * @param event The type of event being signalled. + * @param ctxt Various information pertaining to the event. + * @param arg Application-specified argument; unused by + * bleprph. + * + * @return 0 if the application successfully handled the + * event; nonzero on failure. The semantics + * of the return code is specific to the + * particular GAP event being signalled. + */ +static int +bleprph_gap_event(struct ble_gap_event *event, void *arg) +{ + struct ble_gap_conn_desc desc; + int rc; + + switch (event->type) { + case BLE_GAP_EVENT_CONNECT: + /* A new connection was established or a connection attempt failed. */ + MODLOG_DFLT(INFO, "connection %s; status=%d ", + event->connect.status == 0 ? "established" : "failed", + event->connect.status); + if (event->connect.status == 0) { + rc = ble_gap_conn_find(event->connect.conn_handle, &desc); + assert(rc == 0); + bleprph_print_conn_desc(&desc); + } + MODLOG_DFLT(INFO, "\n"); + + if (event->connect.status != 0) { + /* Connection failed; resume advertising. */ +#if CONFIG_EXAMPLE_EXTENDED_ADV + ext_bleprph_advertise(); +#else + bleprph_advertise(); +#endif + } + return 0; + + case BLE_GAP_EVENT_DISCONNECT: + MODLOG_DFLT(INFO, "disconnect; reason=%d ", event->disconnect.reason); + bleprph_print_conn_desc(&event->disconnect.conn); + MODLOG_DFLT(INFO, "\n"); + + /* Connection terminated; resume advertising. */ + +#if CONFIG_EXAMPLE_EXTENDED_ADV + switch (s_current_phy) { + case BLE_HCI_LE_PHY_1M_PREF_MASK: + /* Setting current phy to create connection on 2M PHY */ + s_current_phy = BLE_HCI_LE_PHY_2M_PREF_MASK; + break; + + case BLE_HCI_LE_PHY_2M_PREF_MASK: + /* Setting current phy to create connection on CODED PHY */ + s_current_phy = BLE_HCI_LE_PHY_CODED_PREF_MASK; + break; + + case BLE_HCI_LE_PHY_CODED_PREF_MASK: + return 0; + + default: + return 0; + } + set_default_le_phy_before_conn(s_current_phy, s_current_phy); + ext_bleprph_advertise(); +#else + bleprph_advertise(); +#endif + return 0; + + case BLE_GAP_EVENT_CONN_UPDATE: + /* The central has updated the connection parameters. */ + MODLOG_DFLT(INFO, "connection updated; status=%d ", + event->conn_update.status); + rc = ble_gap_conn_find(event->conn_update.conn_handle, &desc); + assert(rc == 0); + bleprph_print_conn_desc(&desc); + MODLOG_DFLT(INFO, "\n"); + return 0; + + case BLE_GAP_EVENT_ADV_COMPLETE: + MODLOG_DFLT(INFO, "advertise complete; reason=%d", + event->adv_complete.reason); +#if !CONFIG_EXAMPLE_EXTENDED_ADV + bleprph_advertise(); +#endif + return 0; + + case BLE_GAP_EVENT_PHY_UPDATE_COMPLETE: + MODLOG_DFLT(INFO, "LE PHY Update completed; status=%d conn_handle=%d tx_phy=%d " + "rx_phy = %d\n", event->phy_updated.status, + event->phy_updated.conn_handle, event->phy_updated.tx_phy, + event->phy_updated.rx_phy); + return 0; + } + + return 0; +} + +static void +bleprph_on_reset(int reason) +{ + MODLOG_DFLT(ERROR, "Resetting state; reason=%d\n", reason); +} + +static void +bleprph_on_sync(void) +{ + int rc; + + /* Make sure we have proper identity address set (public preferred) */ + rc = ble_hs_util_ensure_addr(0); + assert(rc == 0); + + /* Figure out address to use while advertising (no privacy for now) */ + rc = ble_hs_id_infer_auto(0, &own_addr_type); + if (rc != 0) { + MODLOG_DFLT(ERROR, "error determining address type; rc=%d\n", rc); + return; + } + + /* Printing ADDR */ + uint8_t addr_val[6] = {0}; + rc = ble_hs_id_copy_addr(own_addr_type, addr_val, NULL); + + MODLOG_DFLT(INFO, "Device Address: "); + print_addr(addr_val); + MODLOG_DFLT(INFO, "\n"); + + s_current_phy = BLE_HCI_LE_PHY_1M_PREF_MASK; + + /* Begin advertising. */ +#if CONFIG_EXAMPLE_EXTENDED_ADV + ext_bleprph_advertise(); +#else + bleprph_advertise(); +#endif +} + +void bleprph_host_task(void *param) +{ + ESP_LOGI(tag, "BLE Host Task Started"); + /* This function will return only when nimble_port_stop() is executed */ + nimble_port_run(); + + nimble_port_freertos_deinit(); +} + +void +app_main(void) +{ + int rc; + + /* Initialize NVS — it is used to store PHY calibration data */ + esp_err_t ret = nvs_flash_init(); + if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { + ESP_ERROR_CHECK(nvs_flash_erase()); + ret = nvs_flash_init(); + } + ESP_ERROR_CHECK(ret); + + //ESP_ERROR_CHECK(esp_nimble_hci_and_controller_init()); + + nimble_port_init(); + /* Initialize the NimBLE host configuration. */ + ble_hs_cfg.reset_cb = bleprph_on_reset; + ble_hs_cfg.sync_cb = bleprph_on_sync; + ble_hs_cfg.gatts_register_cb = gatt_svr_register_cb; + ble_hs_cfg.store_status_cb = ble_store_util_status_rr; + + ble_hs_cfg.sm_io_cap = CONFIG_EXAMPLE_IO_TYPE; +#ifdef CONFIG_EXAMPLE_BONDING + ble_hs_cfg.sm_bonding = 1; +#endif +#ifdef CONFIG_EXAMPLE_MITM + ble_hs_cfg.sm_mitm = 1; +#endif +#ifdef CONFIG_EXAMPLE_USE_SC + ble_hs_cfg.sm_sc = 1; +#else + ble_hs_cfg.sm_sc = 0; +#endif +#ifdef CONFIG_EXAMPLE_BONDING + ble_hs_cfg.sm_our_key_dist = 1; + ble_hs_cfg.sm_their_key_dist = 1; +#endif + + rc = gatt_svr_init_le_phy(); + assert(rc == 0); + + /* Set the default device name. */ + rc = ble_svc_gap_device_name_set("bleprph-phy"); + assert(rc == 0); + + /* XXX Need to have template for store */ + ble_store_config_init(); + + nimble_port_freertos_init(bleprph_host_task); + + /* Initialize command line interface to accept input from user */ + rc = scli_init(); + if (rc != ESP_OK) { + ESP_LOGE(tag, "scli_init() failed"); + } +} diff --git a/examples/bluetooth/nimble/ble_phy/phy_prph/main/phy_prph.h b/examples/bluetooth/nimble/ble_phy/phy_prph/main/phy_prph.h new file mode 100644 index 0000000000..b9f8a667e0 --- /dev/null +++ b/examples/bluetooth/nimble/ble_phy/phy_prph/main/phy_prph.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#ifndef H_PHY_PRPH_ +#define H_PHY_PRPH_ + +#include +#include "nimble/ble.h" +#include "modlog/modlog.h" +#include "esp_peripheral.h" +#ifdef __cplusplus +extern "C" { +#endif + +struct ble_hs_cfg; +struct ble_gatt_register_ctxt; + +/** Making sure client connects to server having LE PHY UUID */ +#define LE_PHY_UUID16 0xABF2 +#define LE_PHY_CHR_UUID16 0xABF3 + +void gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *arg); +int gatt_svr_init_le_phy(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/examples/bluetooth/nimble/ble_phy/phy_prph/sdkconfig.defaults b/examples/bluetooth/nimble/ble_phy/phy_prph/sdkconfig.defaults new file mode 100644 index 0000000000..81960c1079 --- /dev/null +++ b/examples/bluetooth/nimble/ble_phy/phy_prph/sdkconfig.defaults @@ -0,0 +1,13 @@ +# Override some defaults so BT stack is enabled +# in this example + +# +# BT config +# +CONFIG_BT_ENABLED=y +CONFIG_BTDM_CTRL_MODE_BLE_ONLY=y +CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=n +CONFIG_BTDM_CTRL_MODE_BTDM=n +CONFIG_BT_BLUEDROID_ENABLED=n +CONFIG_BT_NIMBLE_ENABLED=y +CONFIG_BT_NIMBLE_EXT_ADV=y diff --git a/examples/bluetooth/nimble/ble_spp/spp_client/CMakeLists.txt b/examples/bluetooth/nimble/ble_spp/spp_client/CMakeLists.txt index 615f271b6c..b0bdddddf7 100644 --- a/examples/bluetooth/nimble/ble_spp/spp_client/CMakeLists.txt +++ b/examples/bluetooth/nimble/ble_spp/spp_client/CMakeLists.txt @@ -2,5 +2,7 @@ # CMakeLists in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.16) +set(EXTRA_COMPONENT_DIRS ${CMAKE_CURRENT_LIST_DIR}/../../common/nimble_central_utils) + include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(spp_client) diff --git a/examples/bluetooth/nimble/ble_spp/spp_client/main/CMakeLists.txt b/examples/bluetooth/nimble/ble_spp/spp_client/main/CMakeLists.txt index 7eff1870a2..18d510d988 100644 --- a/examples/bluetooth/nimble/ble_spp/spp_client/main/CMakeLists.txt +++ b/examples/bluetooth/nimble/ble_spp/spp_client/main/CMakeLists.txt @@ -1,2 +1,4 @@ -idf_component_register(SRCS "main.c" "misc.c" "peer.c" - INCLUDE_DIRS ".") +set(srcs "main.c") + +idf_component_register(SRCS "${srcs}" + INCLUDE_DIRS ".") diff --git a/examples/bluetooth/nimble/ble_spp/spp_client/main/ble_spp_client.h b/examples/bluetooth/nimble/ble_spp/spp_client/main/ble_spp_client.h index da0f9d8f8d..c94f900558 100644 --- a/examples/bluetooth/nimble/ble_spp/spp_client/main/ble_spp_client.h +++ b/examples/bluetooth/nimble/ble_spp/spp_client/main/ble_spp_client.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -8,6 +8,7 @@ #define H_BLESPPCLIENT_ #include "modlog/modlog.h" +#include "esp_central.h" #ifdef __cplusplus extern "C" { #endif @@ -25,74 +26,6 @@ union ble_store_key; #define GATT_SVR_CHR_UNR_ALERT_STAT_UUID 0x2A45 #define GATT_SVR_CHR_ALERT_NOT_CTRL_PT 0x2A44 -/** Misc. */ -void print_bytes(const uint8_t *bytes, int len); -void print_mbuf(const struct os_mbuf *om); -char *addr_str(const void *addr); -void print_uuid(const ble_uuid_t *uuid); -void print_conn_desc(const struct ble_gap_conn_desc *desc); -void print_adv_fields(const struct ble_hs_adv_fields *fields); - -/** Peer. */ -struct peer_dsc { - SLIST_ENTRY(peer_dsc) next; - struct ble_gatt_dsc dsc; -}; -SLIST_HEAD(peer_dsc_list, peer_dsc); - -struct peer_chr { - SLIST_ENTRY(peer_chr) next; - struct ble_gatt_chr chr; - - struct peer_dsc_list dscs; -}; -SLIST_HEAD(peer_chr_list, peer_chr); - -struct peer_svc { - SLIST_ENTRY(peer_svc) next; - struct ble_gatt_svc svc; - - struct peer_chr_list chrs; -}; -SLIST_HEAD(peer_svc_list, peer_svc); - -struct peer; -typedef void peer_disc_fn(const struct peer *peer, int status, void *arg); - -struct peer { - SLIST_ENTRY(peer) next; - - uint16_t conn_handle; - - /** List of discovered GATT services. */ - struct peer_svc_list svcs; - - /** Keeps track of where we are in the service discovery process. */ - uint16_t disc_prev_chr_val; - struct peer_svc *cur_svc; - - /** Callback that gets executed when service discovery completes. */ - peer_disc_fn *disc_cb; - void *disc_cb_arg; -}; - -int peer_disc_all(uint16_t conn_handle, peer_disc_fn *disc_cb, - void *disc_cb_arg); -const struct peer_dsc * -peer_dsc_find_uuid(const struct peer *peer, const ble_uuid_t *svc_uuid, - const ble_uuid_t *chr_uuid, const ble_uuid_t *dsc_uuid); -const struct peer_chr * -peer_chr_find_uuid(const struct peer *peer, const ble_uuid_t *svc_uuid, - const ble_uuid_t *chr_uuid); -const struct peer_svc * -peer_svc_find_uuid(const struct peer *peer, const ble_uuid_t *uuid); -int peer_delete(uint16_t conn_handle); -int peer_add(uint16_t conn_handle); -int peer_init(int max_peers, int max_svcs, int max_chrs, int max_dscs); -struct peer * -peer_find(uint16_t conn_handle); - - #ifdef __cplusplus } #endif diff --git a/examples/bluetooth/nimble/ble_spp/spp_client/main/misc.c b/examples/bluetooth/nimble/ble_spp/spp_client/main/misc.c deleted file mode 100644 index d94c15b55f..0000000000 --- a/examples/bluetooth/nimble/ble_spp/spp_client/main/misc.c +++ /dev/null @@ -1,198 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Unlicense OR CC0-1.0 - */ - -#include -#include -#include -#include "host/ble_hs.h" -#include "host/ble_uuid.h" -#include "ble_spp_client.h" - -/** - * Utility function to log an array of bytes. - */ -void -print_bytes(const uint8_t *bytes, int len) -{ - int i; - - for (i = 0; i < len; i++) { - MODLOG_DFLT(DEBUG, "%s0x%02x", i != 0 ? ":" : "", bytes[i]); - } -} - -void -print_mbuf(const struct os_mbuf *om) -{ - int colon, i; - - colon = 0; - while (om != NULL) { - if (colon) { - MODLOG_DFLT(INFO, ":"); - } else { - colon = 1; - } - for (i = 0; i < om->om_len; i++) { - MODLOG_DFLT(INFO, "%s0x%02x", i != 0 ? ":" : "", om->om_data[i]); - } - om = SLIST_NEXT(om, om_next); - } -} - -char * -addr_str(const void *addr) -{ - static char buf[6 * 2 + 5 + 1]; - const uint8_t *u8p; - - u8p = addr; - sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x", - u8p[5], u8p[4], u8p[3], u8p[2], u8p[1], u8p[0]); - - return buf; -} - -void -print_uuid(const ble_uuid_t *uuid) -{ - char buf[BLE_UUID_STR_LEN]; - - MODLOG_DFLT(DEBUG, "%s", ble_uuid_to_str(uuid, buf)); -} - -/** - * Logs information about a connection to the console. - */ -void -print_conn_desc(const struct ble_gap_conn_desc *desc) -{ - MODLOG_DFLT(DEBUG, "handle=%d our_ota_addr_type=%d our_ota_addr=%s ", - desc->conn_handle, desc->our_ota_addr.type, - addr_str(desc->our_ota_addr.val)); - MODLOG_DFLT(DEBUG, "our_id_addr_type=%d our_id_addr=%s ", - desc->our_id_addr.type, addr_str(desc->our_id_addr.val)); - MODLOG_DFLT(DEBUG, "peer_ota_addr_type=%d peer_ota_addr=%s ", - desc->peer_ota_addr.type, addr_str(desc->peer_ota_addr.val)); - MODLOG_DFLT(DEBUG, "peer_id_addr_type=%d peer_id_addr=%s ", - desc->peer_id_addr.type, addr_str(desc->peer_id_addr.val)); - MODLOG_DFLT(DEBUG, "conn_itvl=%d conn_latency=%d supervision_timeout=%d " - "encrypted=%d authenticated=%d bonded=%d", - desc->conn_itvl, desc->conn_latency, - desc->supervision_timeout, - desc->sec_state.encrypted, - desc->sec_state.authenticated, - desc->sec_state.bonded); -} - - -void -print_adv_fields(const struct ble_hs_adv_fields *fields) -{ - char s[BLE_HS_ADV_MAX_SZ]; - const uint8_t *u8p; - int i; - - if (fields->flags != 0) { - MODLOG_DFLT(DEBUG, " flags=0x%02x\n", fields->flags); - } - - if (fields->uuids16 != NULL) { - MODLOG_DFLT(DEBUG, " uuids16(%scomplete)=", - fields->uuids16_is_complete ? "" : "in"); - for (i = 0; i < fields->num_uuids16; i++) { - print_uuid(&fields->uuids16[i].u); - MODLOG_DFLT(DEBUG, " "); - } - MODLOG_DFLT(DEBUG, "\n"); - } - - if (fields->uuids32 != NULL) { - MODLOG_DFLT(DEBUG, " uuids32(%scomplete)=", - fields->uuids32_is_complete ? "" : "in"); - for (i = 0; i < fields->num_uuids32; i++) { - print_uuid(&fields->uuids32[i].u); - MODLOG_DFLT(DEBUG, " "); - } - MODLOG_DFLT(DEBUG, "\n"); - } - - if (fields->uuids128 != NULL) { - MODLOG_DFLT(DEBUG, " uuids128(%scomplete)=", - fields->uuids128_is_complete ? "" : "in"); - for (i = 0; i < fields->num_uuids128; i++) { - print_uuid(&fields->uuids128[i].u); - MODLOG_DFLT(DEBUG, " "); - } - MODLOG_DFLT(DEBUG, "\n"); - } - - if (fields->name != NULL) { - assert(fields->name_len < sizeof s - 1); - memcpy(s, fields->name, fields->name_len); - s[fields->name_len] = '\0'; - MODLOG_DFLT(DEBUG, " name(%scomplete)=%s\n", - fields->name_is_complete ? "" : "in", s); - } - - if (fields->tx_pwr_lvl_is_present) { - MODLOG_DFLT(DEBUG, " tx_pwr_lvl=%d\n", fields->tx_pwr_lvl); - } - - if (fields->slave_itvl_range != NULL) { - MODLOG_DFLT(DEBUG, " slave_itvl_range="); - print_bytes(fields->slave_itvl_range, BLE_HS_ADV_SLAVE_ITVL_RANGE_LEN); - MODLOG_DFLT(DEBUG, "\n"); - } - - if (fields->svc_data_uuid16 != NULL) { - MODLOG_DFLT(DEBUG, " svc_data_uuid16="); - print_bytes(fields->svc_data_uuid16, fields->svc_data_uuid16_len); - MODLOG_DFLT(DEBUG, "\n"); - } - - if (fields->public_tgt_addr != NULL) { - MODLOG_DFLT(DEBUG, " public_tgt_addr="); - u8p = fields->public_tgt_addr; - for (i = 0; i < fields->num_public_tgt_addrs; i++) { - MODLOG_DFLT(DEBUG, "public_tgt_addr=%s ", addr_str(u8p)); - u8p += BLE_HS_ADV_PUBLIC_TGT_ADDR_ENTRY_LEN; - } - MODLOG_DFLT(DEBUG, "\n"); - } - - if (fields->appearance_is_present) { - MODLOG_DFLT(DEBUG, " appearance=0x%04x\n", fields->appearance); - } - - if (fields->adv_itvl_is_present) { - MODLOG_DFLT(DEBUG, " adv_itvl=0x%04x\n", fields->adv_itvl); - } - - if (fields->svc_data_uuid32 != NULL) { - MODLOG_DFLT(DEBUG, " svc_data_uuid32="); - print_bytes(fields->svc_data_uuid32, fields->svc_data_uuid32_len); - MODLOG_DFLT(DEBUG, "\n"); - } - - if (fields->svc_data_uuid128 != NULL) { - MODLOG_DFLT(DEBUG, " svc_data_uuid128="); - print_bytes(fields->svc_data_uuid128, fields->svc_data_uuid128_len); - MODLOG_DFLT(DEBUG, "\n"); - } - - if (fields->uri != NULL) { - MODLOG_DFLT(DEBUG, " uri="); - print_bytes(fields->uri, fields->uri_len); - MODLOG_DFLT(DEBUG, "\n"); - } - - if (fields->mfg_data != NULL) { - MODLOG_DFLT(DEBUG, " mfg_data="); - print_bytes(fields->mfg_data, fields->mfg_data_len); - MODLOG_DFLT(DEBUG, "\n"); - } -} diff --git a/examples/bluetooth/nimble/ble_spp/spp_client/main/peer.c b/examples/bluetooth/nimble/ble_spp/spp_client/main/peer.c deleted file mode 100644 index 93ab5a483c..0000000000 --- a/examples/bluetooth/nimble/ble_spp/spp_client/main/peer.c +++ /dev/null @@ -1,794 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Unlicense OR CC0-1.0 - */ - -#include -#include -#include "host/ble_hs.h" -#include "ble_spp_client.h" - -static void *peer_svc_mem; -static struct os_mempool peer_svc_pool; - -static void *peer_chr_mem; -static struct os_mempool peer_chr_pool; - -static void *peer_dsc_mem; -static struct os_mempool peer_dsc_pool; - -static void *peer_mem; -static struct os_mempool peer_pool; -static SLIST_HEAD(, peer) peers; - -static struct peer_svc * -peer_svc_find_range(struct peer *peer, uint16_t attr_handle); -static struct peer_svc * -peer_svc_find(struct peer *peer, uint16_t svc_start_handle, - struct peer_svc **out_prev); -int -peer_svc_is_empty(const struct peer_svc *svc); - -uint16_t -chr_end_handle(const struct peer_svc *svc, const struct peer_chr *chr); -int -chr_is_empty(const struct peer_svc *svc, const struct peer_chr *chr); -static struct peer_chr * -peer_chr_find(const struct peer_svc *svc, uint16_t chr_def_handle, - struct peer_chr **out_prev); -static void -peer_disc_chrs(struct peer *peer); - -static int -peer_dsc_disced(uint16_t conn_handle, const struct ble_gatt_error *error, - uint16_t chr_val_handle, const struct ble_gatt_dsc *dsc, - void *arg); - -struct peer * -peer_find(uint16_t conn_handle) -{ - struct peer *peer; - - SLIST_FOREACH(peer, &peers, next) { - if (peer->conn_handle == conn_handle) { - return peer; - } - } - - return NULL; -} - -static void -peer_disc_complete(struct peer *peer, int rc) -{ - peer->disc_prev_chr_val = 0; - - /* Notify caller that discovery has completed. */ - if (peer->disc_cb != NULL) { - peer->disc_cb(peer, rc, peer->disc_cb_arg); - } -} - -static struct peer_dsc * -peer_dsc_find_prev(const struct peer_chr *chr, uint16_t dsc_handle) -{ - struct peer_dsc *prev; - struct peer_dsc *dsc; - - prev = NULL; - SLIST_FOREACH(dsc, &chr->dscs, next) { - if (dsc->dsc.handle >= dsc_handle) { - break; - } - - prev = dsc; - } - - return prev; -} - -static struct peer_dsc * -peer_dsc_find(const struct peer_chr *chr, uint16_t dsc_handle, - struct peer_dsc **out_prev) -{ - struct peer_dsc *prev; - struct peer_dsc *dsc; - - prev = peer_dsc_find_prev(chr, dsc_handle); - if (prev == NULL) { - dsc = SLIST_FIRST(&chr->dscs); - } else { - dsc = SLIST_NEXT(prev, next); - } - - if (dsc != NULL && dsc->dsc.handle != dsc_handle) { - dsc = NULL; - } - - if (out_prev != NULL) { - *out_prev = prev; - } - return dsc; -} - -static int -peer_dsc_add(struct peer *peer, uint16_t chr_val_handle, - const struct ble_gatt_dsc *gatt_dsc) -{ - struct peer_dsc *prev; - struct peer_dsc *dsc; - struct peer_svc *svc; - struct peer_chr *chr; - - svc = peer_svc_find_range(peer, chr_val_handle); - if (svc == NULL) { - /* Can't find service for discovered descriptor; this shouldn't - * happen. - */ - assert(0); - return BLE_HS_EUNKNOWN; - } - - chr = peer_chr_find(svc, chr_val_handle, NULL); - if (chr == NULL) { - /* Can't find characteristic for discovered descriptor; this shouldn't - * happen. - */ - assert(0); - return BLE_HS_EUNKNOWN; - } - - dsc = peer_dsc_find(chr, gatt_dsc->handle, &prev); - if (dsc != NULL) { - /* Descriptor already discovered. */ - return 0; - } - - dsc = os_memblock_get(&peer_dsc_pool); - if (dsc == NULL) { - /* Out of memory. */ - return BLE_HS_ENOMEM; - } - memset(dsc, 0, sizeof * dsc); - - dsc->dsc = *gatt_dsc; - - if (prev == NULL) { - SLIST_INSERT_HEAD(&chr->dscs, dsc, next); - } else { - SLIST_NEXT(prev, next) = dsc; - } - - return 0; -} - -static void -peer_disc_dscs(struct peer *peer) -{ - struct peer_chr *chr; - struct peer_svc *svc; - int rc; - - /* Search through the list of discovered characteristics for the first - * characteristic that contains undiscovered descriptors. Then, discover - * all descriptors belonging to that characteristic. - */ - SLIST_FOREACH(svc, &peer->svcs, next) { - SLIST_FOREACH(chr, &svc->chrs, next) { - if (!chr_is_empty(svc, chr) && - SLIST_EMPTY(&chr->dscs) && - peer->disc_prev_chr_val <= chr->chr.def_handle) { - - rc = ble_gattc_disc_all_dscs(peer->conn_handle, - chr->chr.val_handle, - chr_end_handle(svc, chr), - peer_dsc_disced, peer); - if (rc != 0) { - peer_disc_complete(peer, rc); - } - - peer->disc_prev_chr_val = chr->chr.val_handle; - return; - } - } - } - - /* All descriptors discovered. */ - peer_disc_complete(peer, 0); -} - -static int -peer_dsc_disced(uint16_t conn_handle, const struct ble_gatt_error *error, - uint16_t chr_val_handle, const struct ble_gatt_dsc *dsc, - void *arg) -{ - struct peer *peer; - int rc; - - peer = arg; - assert(peer->conn_handle == conn_handle); - - switch (error->status) { - case 0: - rc = peer_dsc_add(peer, chr_val_handle, dsc); - break; - - case BLE_HS_EDONE: - /* All descriptors in this characteristic discovered; start discovering - * descriptors in the next characteristic. - */ - if (peer->disc_prev_chr_val > 0) { - peer_disc_dscs(peer); - } - rc = 0; - break; - - default: - /* Error; abort discovery. */ - rc = error->status; - break; - } - - if (rc != 0) { - /* Error; abort discovery. */ - peer_disc_complete(peer, rc); - } - - return rc; -} - -uint16_t -chr_end_handle(const struct peer_svc *svc, const struct peer_chr *chr) -{ - const struct peer_chr *next_chr; - - next_chr = SLIST_NEXT(chr, next); - if (next_chr != NULL) { - return next_chr->chr.def_handle - 1; - } else { - return svc->svc.end_handle; - } -} - -int -chr_is_empty(const struct peer_svc *svc, const struct peer_chr *chr) -{ - return chr_end_handle(svc, chr) <= chr->chr.val_handle; -} - -static struct peer_chr * -peer_chr_find_prev(const struct peer_svc *svc, uint16_t chr_val_handle) -{ - struct peer_chr *prev; - struct peer_chr *chr; - - prev = NULL; - SLIST_FOREACH(chr, &svc->chrs, next) { - if (chr->chr.val_handle >= chr_val_handle) { - break; - } - - prev = chr; - } - - return prev; -} - -static struct peer_chr * -peer_chr_find(const struct peer_svc *svc, uint16_t chr_val_handle, - struct peer_chr **out_prev) -{ - struct peer_chr *prev; - struct peer_chr *chr; - - prev = peer_chr_find_prev(svc, chr_val_handle); - if (prev == NULL) { - chr = SLIST_FIRST(&svc->chrs); - } else { - chr = SLIST_NEXT(prev, next); - } - - if (chr != NULL && chr->chr.val_handle != chr_val_handle) { - chr = NULL; - } - - if (out_prev != NULL) { - *out_prev = prev; - } - return chr; -} - -static void -peer_chr_delete(struct peer_chr *chr) -{ - struct peer_dsc *dsc; - - while ((dsc = SLIST_FIRST(&chr->dscs)) != NULL) { - SLIST_REMOVE_HEAD(&chr->dscs, next); - os_memblock_put(&peer_dsc_pool, dsc); - } - - os_memblock_put(&peer_chr_pool, chr); -} - -static int -peer_chr_add(struct peer *peer, uint16_t svc_start_handle, - const struct ble_gatt_chr *gatt_chr) -{ - struct peer_chr *prev; - struct peer_chr *chr; - struct peer_svc *svc; - - svc = peer_svc_find(peer, svc_start_handle, NULL); - if (svc == NULL) { - /* Can't find service for discovered characteristic; this shouldn't - * happen. - */ - assert(0); - return BLE_HS_EUNKNOWN; - } - - chr = peer_chr_find(svc, gatt_chr->def_handle, &prev); - if (chr != NULL) { - /* Characteristic already discovered. */ - return 0; - } - - chr = os_memblock_get(&peer_chr_pool); - if (chr == NULL) { - /* Out of memory. */ - return BLE_HS_ENOMEM; - } - memset(chr, 0, sizeof * chr); - - chr->chr = *gatt_chr; - - if (prev == NULL) { - SLIST_INSERT_HEAD(&svc->chrs, chr, next); - } else { - SLIST_NEXT(prev, next) = chr; - } - - return 0; -} - -static int -peer_chr_disced(uint16_t conn_handle, const struct ble_gatt_error *error, - const struct ble_gatt_chr *chr, void *arg) -{ - struct peer *peer; - int rc; - - peer = arg; - assert(peer->conn_handle == conn_handle); - - switch (error->status) { - case 0: - rc = peer_chr_add(peer, peer->cur_svc->svc.start_handle, chr); - break; - - case BLE_HS_EDONE: - /* All characteristics in this service discovered; start discovering - * characteristics in the next service. - */ - if (peer->disc_prev_chr_val > 0) { - peer_disc_chrs(peer); - } - rc = 0; - break; - - default: - rc = error->status; - break; - } - - if (rc != 0) { - /* Error; abort discovery. */ - peer_disc_complete(peer, rc); - } - - return rc; -} - -static void -peer_disc_chrs(struct peer *peer) -{ - struct peer_svc *svc; - int rc; - - /* Search through the list of discovered service for the first service that - * contains undiscovered characteristics. Then, discover all - * characteristics belonging to that service. - */ - SLIST_FOREACH(svc, &peer->svcs, next) { - if (!peer_svc_is_empty(svc) && SLIST_EMPTY(&svc->chrs)) { - peer->cur_svc = svc; - rc = ble_gattc_disc_all_chrs(peer->conn_handle, - svc->svc.start_handle, - svc->svc.end_handle, - peer_chr_disced, peer); - if (rc != 0) { - peer_disc_complete(peer, rc); - } - return; - } - } - - /* All characteristics discovered. */ - peer_disc_dscs(peer); -} - -int -peer_svc_is_empty(const struct peer_svc *svc) -{ - return svc->svc.end_handle <= svc->svc.start_handle; -} - -static struct peer_svc * -peer_svc_find_prev(struct peer *peer, uint16_t svc_start_handle) -{ - struct peer_svc *prev; - struct peer_svc *svc; - - prev = NULL; - SLIST_FOREACH(svc, &peer->svcs, next) { - if (svc->svc.start_handle >= svc_start_handle) { - break; - } - - prev = svc; - } - - return prev; -} - -static struct peer_svc * -peer_svc_find(struct peer *peer, uint16_t svc_start_handle, - struct peer_svc **out_prev) -{ - struct peer_svc *prev; - struct peer_svc *svc; - - prev = peer_svc_find_prev(peer, svc_start_handle); - if (prev == NULL) { - svc = SLIST_FIRST(&peer->svcs); - } else { - svc = SLIST_NEXT(prev, next); - } - - if (svc != NULL && svc->svc.start_handle != svc_start_handle) { - svc = NULL; - } - - if (out_prev != NULL) { - *out_prev = prev; - } - return svc; -} - -static struct peer_svc * -peer_svc_find_range(struct peer *peer, uint16_t attr_handle) -{ - struct peer_svc *svc; - - SLIST_FOREACH(svc, &peer->svcs, next) { - if (svc->svc.start_handle <= attr_handle && - svc->svc.end_handle >= attr_handle) { - - return svc; - } - } - - return NULL; -} - -const struct peer_svc * -peer_svc_find_uuid(const struct peer *peer, const ble_uuid_t *uuid) -{ - const struct peer_svc *svc; - - SLIST_FOREACH(svc, &peer->svcs, next) { - if (ble_uuid_cmp(&svc->svc.uuid.u, uuid) == 0) { - return svc; - } - } - - return NULL; -} - -const struct peer_chr * -peer_chr_find_uuid(const struct peer *peer, const ble_uuid_t *svc_uuid, - const ble_uuid_t *chr_uuid) -{ - const struct peer_svc *svc; - const struct peer_chr *chr; - - svc = peer_svc_find_uuid(peer, svc_uuid); - if (svc == NULL) { - return NULL; - } - - SLIST_FOREACH(chr, &svc->chrs, next) { - if (ble_uuid_cmp(&chr->chr.uuid.u, chr_uuid) == 0) { - return chr; - } - } - - return NULL; -} - -const struct peer_dsc * -peer_dsc_find_uuid(const struct peer *peer, const ble_uuid_t *svc_uuid, - const ble_uuid_t *chr_uuid, const ble_uuid_t *dsc_uuid) -{ - const struct peer_chr *chr; - const struct peer_dsc *dsc; - - chr = peer_chr_find_uuid(peer, svc_uuid, chr_uuid); - if (chr == NULL) { - return NULL; - } - - SLIST_FOREACH(dsc, &chr->dscs, next) { - if (ble_uuid_cmp(&dsc->dsc.uuid.u, dsc_uuid) == 0) { - return dsc; - } - } - - return NULL; -} - -static int -peer_svc_add(struct peer *peer, const struct ble_gatt_svc *gatt_svc) -{ - struct peer_svc *prev; - struct peer_svc *svc; - - svc = peer_svc_find(peer, gatt_svc->start_handle, &prev); - if (svc != NULL) { - /* Service already discovered. */ - return 0; - } - - svc = os_memblock_get(&peer_svc_pool); - if (svc == NULL) { - /* Out of memory. */ - return BLE_HS_ENOMEM; - } - memset(svc, 0, sizeof * svc); - - svc->svc = *gatt_svc; - SLIST_INIT(&svc->chrs); - - if (prev == NULL) { - SLIST_INSERT_HEAD(&peer->svcs, svc, next); - } else { - SLIST_INSERT_AFTER(prev, svc, next); - } - - return 0; -} - -static void -peer_svc_delete(struct peer_svc *svc) -{ - struct peer_chr *chr; - - while ((chr = SLIST_FIRST(&svc->chrs)) != NULL) { - SLIST_REMOVE_HEAD(&svc->chrs, next); - peer_chr_delete(chr); - } - - os_memblock_put(&peer_svc_pool, svc); -} - -static int -peer_svc_disced(uint16_t conn_handle, const struct ble_gatt_error *error, - const struct ble_gatt_svc *service, void *arg) -{ - struct peer *peer; - int rc; - - peer = arg; - assert(peer->conn_handle == conn_handle); - - switch (error->status) { - case 0: - rc = peer_svc_add(peer, service); - break; - - case BLE_HS_EDONE: - /* All services discovered; start discovering characteristics. */ - if (peer->disc_prev_chr_val > 0) { - peer_disc_chrs(peer); - } - rc = 0; - break; - - default: - rc = error->status; - break; - } - - if (rc != 0) { - /* Error; abort discovery. */ - peer_disc_complete(peer, rc); - } - - return rc; -} - - -int -peer_disc_all(uint16_t conn_handle, peer_disc_fn *disc_cb, void *disc_cb_arg) -{ - struct peer_svc *svc; - struct peer *peer; - int rc; - - peer = peer_find(conn_handle); - if (peer == NULL) { - return BLE_HS_ENOTCONN; - } - - /* Undiscover everything first. */ - while ((svc = SLIST_FIRST(&peer->svcs)) != NULL) { - SLIST_REMOVE_HEAD(&peer->svcs, next); - peer_svc_delete(svc); - } - - peer->disc_prev_chr_val = 1; - peer->disc_cb = disc_cb; - peer->disc_cb_arg = disc_cb_arg; - - rc = ble_gattc_disc_all_svcs(conn_handle, peer_svc_disced, peer); - if (rc != 0) { - return rc; - } - - return 0; -} - -int -peer_delete(uint16_t conn_handle) -{ - struct peer_svc *svc; - struct peer *peer; - int rc; - - peer = peer_find(conn_handle); - if (peer == NULL) { - return BLE_HS_ENOTCONN; - } - - SLIST_REMOVE(&peers, peer, peer, next); - - while ((svc = SLIST_FIRST(&peer->svcs)) != NULL) { - SLIST_REMOVE_HEAD(&peer->svcs, next); - peer_svc_delete(svc); - } - - rc = os_memblock_put(&peer_pool, peer); - if (rc != 0) { - return BLE_HS_EOS; - } - - return 0; -} - -int -peer_add(uint16_t conn_handle) -{ - struct peer *peer; - - /* Make sure the connection handle is unique. */ - peer = peer_find(conn_handle); - if (peer != NULL) { - return BLE_HS_EALREADY; - } - - peer = os_memblock_get(&peer_pool); - if (peer == NULL) { - /* Out of memory. */ - return BLE_HS_ENOMEM; - } - - memset(peer, 0, sizeof * peer); - peer->conn_handle = conn_handle; - - SLIST_INSERT_HEAD(&peers, peer, next); - - return 0; -} - -static void -peer_free_mem(void) -{ - free(peer_mem); - peer_mem = NULL; - - free(peer_svc_mem); - peer_svc_mem = NULL; - - free(peer_chr_mem); - peer_chr_mem = NULL; - - free(peer_dsc_mem); - peer_dsc_mem = NULL; -} - -int -peer_init(int max_peers, int max_svcs, int max_chrs, int max_dscs) -{ - int rc; - - /* Free memory first in case this function gets called more than once. */ - peer_free_mem(); - - peer_mem = malloc( - OS_MEMPOOL_BYTES(max_peers, sizeof (struct peer))); - if (peer_mem == NULL) { - rc = BLE_HS_ENOMEM; - goto err; - } - - rc = os_mempool_init(&peer_pool, max_peers, - sizeof (struct peer), peer_mem, - "peer_pool"); - if (rc != 0) { - rc = BLE_HS_EOS; - goto err; - } - - peer_svc_mem = malloc( - OS_MEMPOOL_BYTES(max_svcs, sizeof (struct peer_svc))); - if (peer_svc_mem == NULL) { - rc = BLE_HS_ENOMEM; - goto err; - } - - rc = os_mempool_init(&peer_svc_pool, max_svcs, - sizeof (struct peer_svc), peer_svc_mem, - "peer_svc_pool"); - if (rc != 0) { - rc = BLE_HS_EOS; - goto err; - } - - peer_chr_mem = malloc( - OS_MEMPOOL_BYTES(max_chrs, sizeof (struct peer_chr))); - if (peer_chr_mem == NULL) { - rc = BLE_HS_ENOMEM; - goto err; - } - - rc = os_mempool_init(&peer_chr_pool, max_chrs, - sizeof (struct peer_chr), peer_chr_mem, - "peer_chr_pool"); - if (rc != 0) { - rc = BLE_HS_EOS; - goto err; - } - - peer_dsc_mem = malloc( - OS_MEMPOOL_BYTES(max_dscs, sizeof (struct peer_dsc))); - if (peer_dsc_mem == NULL) { - rc = BLE_HS_ENOMEM; - goto err; - } - - rc = os_mempool_init(&peer_dsc_pool, max_dscs, - sizeof (struct peer_dsc), peer_dsc_mem, - "peer_dsc_pool"); - if (rc != 0) { - rc = BLE_HS_EOS; - goto err; - } - - return 0; - -err: - peer_free_mem(); - return rc; -} diff --git a/examples/bluetooth/nimble/ble_spp/spp_server/CMakeLists.txt b/examples/bluetooth/nimble/ble_spp/spp_server/CMakeLists.txt index 99cadaff23..87c71ac07d 100644 --- a/examples/bluetooth/nimble/ble_spp/spp_server/CMakeLists.txt +++ b/examples/bluetooth/nimble/ble_spp/spp_server/CMakeLists.txt @@ -2,5 +2,7 @@ # CMakeLists in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.16) +set(EXTRA_COMPONENT_DIRS ${CMAKE_CURRENT_LIST_DIR}/../../common/nimble_peripheral_utils) + include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(spp_server) diff --git a/examples/bluetooth/nimble/ble_spp/spp_server/main/CMakeLists.txt b/examples/bluetooth/nimble/ble_spp/spp_server/main/CMakeLists.txt index 1d440d5d68..eee6ef2d0a 100644 --- a/examples/bluetooth/nimble/ble_spp/spp_server/main/CMakeLists.txt +++ b/examples/bluetooth/nimble/ble_spp/spp_server/main/CMakeLists.txt @@ -1,6 +1,5 @@ set(srcs "main.c" - "gatt_svr.c" - "misc.c") + "gatt_svr.c") idf_component_register(SRCS "${srcs}" - INCLUDE_DIRS ".") + INCLUDE_DIRS ".") diff --git a/examples/bluetooth/nimble/ble_spp/spp_server/main/ble_spp_server.h b/examples/bluetooth/nimble/ble_spp/spp_server/main/ble_spp_server.h index 2b6d12e394..880ca9efca 100644 --- a/examples/bluetooth/nimble/ble_spp/spp_server/main/ble_spp_server.h +++ b/examples/bluetooth/nimble/ble_spp/spp_server/main/ble_spp_server.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -10,6 +10,7 @@ #include #include "nimble/ble.h" #include "modlog/modlog.h" +#include "esp_peripheral.h" #ifdef __cplusplus extern "C" { #endif @@ -28,14 +29,6 @@ struct ble_gatt_register_ctxt; void gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *arg); int new_gatt_svr_init(void); -/* Console */ -int scli_init(void); -int scli_receive_key(int *key); - -/** Misc. */ -void print_bytes(const uint8_t *bytes, int len); -void print_addr(const void *addr); - #ifdef __cplusplus } #endif diff --git a/examples/bluetooth/nimble/ble_spp/spp_server/main/misc.c b/examples/bluetooth/nimble/ble_spp/spp_server/main/misc.c deleted file mode 100644 index 988ffebd1e..0000000000 --- a/examples/bluetooth/nimble/ble_spp/spp_server/main/misc.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Unlicense OR CC0-1.0 - */ - -#include "ble_spp_server.h" - -/** - * Utility function to log an array of bytes. - */ -void -print_bytes(const uint8_t *bytes, int len) -{ - int i; - - for (i = 0; i < len; i++) { - MODLOG_DFLT(INFO, "%s0x%02x", i != 0 ? ":" : "", bytes[i]); - } -} - -void -print_addr(const void *addr) -{ - const uint8_t *u8p; - - u8p = addr; - MODLOG_DFLT(INFO, "%02x:%02x:%02x:%02x:%02x:%02x", - u8p[5], u8p[4], u8p[3], u8p[2], u8p[1], u8p[0]); -} diff --git a/examples/bluetooth/nimble/blecent/CMakeLists.txt b/examples/bluetooth/nimble/blecent/CMakeLists.txt index f443dbefda..6b337e7c82 100644 --- a/examples/bluetooth/nimble/blecent/CMakeLists.txt +++ b/examples/bluetooth/nimble/blecent/CMakeLists.txt @@ -2,5 +2,7 @@ # CMakeLists in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.16) +set(EXTRA_COMPONENT_DIRS ${CMAKE_CURRENT_LIST_DIR}/../common/nimble_central_utils) + include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(blecent) diff --git a/examples/bluetooth/nimble/blecent/main/CMakeLists.txt b/examples/bluetooth/nimble/blecent/main/CMakeLists.txt index 7eff1870a2..18d510d988 100644 --- a/examples/bluetooth/nimble/blecent/main/CMakeLists.txt +++ b/examples/bluetooth/nimble/blecent/main/CMakeLists.txt @@ -1,2 +1,4 @@ -idf_component_register(SRCS "main.c" "misc.c" "peer.c" - INCLUDE_DIRS ".") +set(srcs "main.c") + +idf_component_register(SRCS "${srcs}" + INCLUDE_DIRS ".") diff --git a/examples/bluetooth/nimble/blecent/main/blecent.h b/examples/bluetooth/nimble/blecent/main/blecent.h index d540908d45..b070af1164 100644 --- a/examples/bluetooth/nimble/blecent/main/blecent.h +++ b/examples/bluetooth/nimble/blecent/main/blecent.h @@ -21,6 +21,7 @@ #define H_BLECENT_ #include "modlog/modlog.h" +#include "esp_central.h" #ifdef __cplusplus extern "C" { #endif @@ -38,75 +39,6 @@ union ble_store_key; #define BLECENT_CHR_UNR_ALERT_STAT_UUID 0x2A45 #define BLECENT_CHR_ALERT_NOT_CTRL_PT 0x2A44 -/** Misc. */ -void print_bytes(const uint8_t *bytes, int len); -void print_mbuf(const struct os_mbuf *om); -char *addr_str(const void *addr); -void print_uuid(const ble_uuid_t *uuid); -void print_conn_desc(const struct ble_gap_conn_desc *desc); -void print_adv_fields(const struct ble_hs_adv_fields *fields); -void ext_print_adv_report(const void *param); - -/** Peer. */ -struct peer_dsc { - SLIST_ENTRY(peer_dsc) next; - struct ble_gatt_dsc dsc; -}; -SLIST_HEAD(peer_dsc_list, peer_dsc); - -struct peer_chr { - SLIST_ENTRY(peer_chr) next; - struct ble_gatt_chr chr; - - struct peer_dsc_list dscs; -}; -SLIST_HEAD(peer_chr_list, peer_chr); - -struct peer_svc { - SLIST_ENTRY(peer_svc) next; - struct ble_gatt_svc svc; - - struct peer_chr_list chrs; -}; -SLIST_HEAD(peer_svc_list, peer_svc); - -struct peer; -typedef void peer_disc_fn(const struct peer *peer, int status, void *arg); - -struct peer { - SLIST_ENTRY(peer) next; - - uint16_t conn_handle; - - /** List of discovered GATT services. */ - struct peer_svc_list svcs; - - /** Keeps track of where we are in the service discovery process. */ - uint16_t disc_prev_chr_val; - struct peer_svc *cur_svc; - - /** Callback that gets executed when service discovery completes. */ - peer_disc_fn *disc_cb; - void *disc_cb_arg; -}; - -int peer_disc_all(uint16_t conn_handle, peer_disc_fn *disc_cb, - void *disc_cb_arg); -const struct peer_dsc * -peer_dsc_find_uuid(const struct peer *peer, const ble_uuid_t *svc_uuid, - const ble_uuid_t *chr_uuid, const ble_uuid_t *dsc_uuid); -const struct peer_chr * -peer_chr_find_uuid(const struct peer *peer, const ble_uuid_t *svc_uuid, - const ble_uuid_t *chr_uuid); -const struct peer_svc * -peer_svc_find_uuid(const struct peer *peer, const ble_uuid_t *uuid); -int peer_delete(uint16_t conn_handle); -int peer_add(uint16_t conn_handle); -int peer_init(int max_peers, int max_svcs, int max_chrs, int max_dscs); -struct peer * -peer_find(uint16_t conn_handle); - - #ifdef __cplusplus } #endif diff --git a/examples/bluetooth/nimble/blecent/main/misc.c b/examples/bluetooth/nimble/blecent/main/misc.c deleted file mode 100644 index 5437fe692f..0000000000 --- a/examples/bluetooth/nimble/blecent/main/misc.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Licensed to the Apache Software Foundation (ASF) under one - * or more contributor license agreements. See the NOTICE file - * distributed with this work for additional information - * regarding copyright ownership. The ASF licenses this file - * to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance - * with the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, - * software distributed under the License is distributed on an - * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - * KIND, either express or implied. See the License for the - * specific language governing permissions and limitations - * under the License. - */ - -#include -#include -#include -#include "host/ble_hs.h" -#include "host/ble_uuid.h" -#include "blecent.h" - -/** - * Utility function to log an array of bytes. - */ -void -print_bytes(const uint8_t *bytes, int len) -{ - int i; - - for (i = 0; i < len; i++) { - MODLOG_DFLT(DEBUG, "%s0x%02x", i != 0 ? ":" : "", bytes[i]); - } -} - -void -print_mbuf(const struct os_mbuf *om) -{ - int colon, i; - - colon = 0; - while (om != NULL) { - if (colon) { - MODLOG_DFLT(INFO, ":"); - } else { - colon = 1; - } - for (i = 0; i < om->om_len; i++) { - MODLOG_DFLT(INFO, "%s0x%02x", i != 0 ? ":" : "", om->om_data[i]); - } - om = SLIST_NEXT(om, om_next); - } -} - -char * -addr_str(const void *addr) -{ - static char buf[6 * 2 + 5 + 1]; - const uint8_t *u8p; - - u8p = addr; - sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x", - u8p[5], u8p[4], u8p[3], u8p[2], u8p[1], u8p[0]); - - return buf; -} - -void -print_uuid(const ble_uuid_t *uuid) -{ - char buf[BLE_UUID_STR_LEN]; - - MODLOG_DFLT(DEBUG, "%s", ble_uuid_to_str(uuid, buf)); -} - -/** - * Logs information about a connection to the console. - */ -void -print_conn_desc(const struct ble_gap_conn_desc *desc) -{ - MODLOG_DFLT(DEBUG, "handle=%d our_ota_addr_type=%d our_ota_addr=%s ", - desc->conn_handle, desc->our_ota_addr.type, - addr_str(desc->our_ota_addr.val)); - MODLOG_DFLT(DEBUG, "our_id_addr_type=%d our_id_addr=%s ", - desc->our_id_addr.type, addr_str(desc->our_id_addr.val)); - MODLOG_DFLT(DEBUG, "peer_ota_addr_type=%d peer_ota_addr=%s ", - desc->peer_ota_addr.type, addr_str(desc->peer_ota_addr.val)); - MODLOG_DFLT(DEBUG, "peer_id_addr_type=%d peer_id_addr=%s ", - desc->peer_id_addr.type, addr_str(desc->peer_id_addr.val)); - MODLOG_DFLT(DEBUG, "conn_itvl=%d conn_latency=%d supervision_timeout=%d " - "encrypted=%d authenticated=%d bonded=%d", - desc->conn_itvl, desc->conn_latency, - desc->supervision_timeout, - desc->sec_state.encrypted, - desc->sec_state.authenticated, - desc->sec_state.bonded); -} - -#if CONFIG_EXAMPLE_EXTENDED_ADV -void -print_addr(const void *addr, const char *name) -{ - const uint8_t *u8p; - u8p = addr; - MODLOG_DFLT(DEBUG, "%s = %02x:%02x:%02x:%02x:%02x:%02x", - name, u8p[5], u8p[4], u8p[3], u8p[2], u8p[1], u8p[0]); -} -void -ext_print_adv_report(const void *param) -{ - const struct ble_gap_ext_disc_desc *disc = (struct ble_gap_ext_disc_desc *)param; - MODLOG_DFLT(DEBUG, "props=%d data_status=%d legacy_event_type=%d", disc->props, disc->data_status, disc->legacy_event_type); - print_addr(disc->addr.val, "address"); - MODLOG_DFLT(DEBUG, "rssi=%d tx_power=%d", disc->rssi, disc->tx_power); - MODLOG_DFLT(DEBUG, "sid=%d prim_phy=%d sec_phy=%d", disc->sid, disc->prim_phy, disc->sec_phy); - MODLOG_DFLT(DEBUG, "periodic_adv_itvl=%d length_data=%d", disc->periodic_adv_itvl, disc->length_data); - print_addr(disc->direct_addr.val, "direct address"); -} -#endif - -void -print_adv_fields(const struct ble_hs_adv_fields *fields) -{ - char s[BLE_HS_ADV_MAX_SZ]; - const uint8_t *u8p; - int i; - - if (fields->flags != 0) { - MODLOG_DFLT(DEBUG, " flags=0x%02x\n", fields->flags); - } - - if (fields->uuids16 != NULL) { - MODLOG_DFLT(DEBUG, " uuids16(%scomplete)=", - fields->uuids16_is_complete ? "" : "in"); - for (i = 0; i < fields->num_uuids16; i++) { - print_uuid(&fields->uuids16[i].u); - MODLOG_DFLT(DEBUG, " "); - } - MODLOG_DFLT(DEBUG, "\n"); - } - - if (fields->uuids32 != NULL) { - MODLOG_DFLT(DEBUG, " uuids32(%scomplete)=", - fields->uuids32_is_complete ? "" : "in"); - for (i = 0; i < fields->num_uuids32; i++) { - print_uuid(&fields->uuids32[i].u); - MODLOG_DFLT(DEBUG, " "); - } - MODLOG_DFLT(DEBUG, "\n"); - } - - if (fields->uuids128 != NULL) { - MODLOG_DFLT(DEBUG, " uuids128(%scomplete)=", - fields->uuids128_is_complete ? "" : "in"); - for (i = 0; i < fields->num_uuids128; i++) { - print_uuid(&fields->uuids128[i].u); - MODLOG_DFLT(DEBUG, " "); - } - MODLOG_DFLT(DEBUG, "\n"); - } - - if (fields->name != NULL) { - assert(fields->name_len < sizeof s - 1); - memcpy(s, fields->name, fields->name_len); - s[fields->name_len] = '\0'; - MODLOG_DFLT(DEBUG, " name(%scomplete)=%s\n", - fields->name_is_complete ? "" : "in", s); - } - - if (fields->tx_pwr_lvl_is_present) { - MODLOG_DFLT(DEBUG, " tx_pwr_lvl=%d\n", fields->tx_pwr_lvl); - } - - if (fields->slave_itvl_range != NULL) { - MODLOG_DFLT(DEBUG, " slave_itvl_range="); - print_bytes(fields->slave_itvl_range, BLE_HS_ADV_SLAVE_ITVL_RANGE_LEN); - MODLOG_DFLT(DEBUG, "\n"); - } - - if (fields->svc_data_uuid16 != NULL) { - MODLOG_DFLT(DEBUG, " svc_data_uuid16="); - print_bytes(fields->svc_data_uuid16, fields->svc_data_uuid16_len); - MODLOG_DFLT(DEBUG, "\n"); - } - - if (fields->public_tgt_addr != NULL) { - MODLOG_DFLT(DEBUG, " public_tgt_addr="); - u8p = fields->public_tgt_addr; - for (i = 0; i < fields->num_public_tgt_addrs; i++) { - MODLOG_DFLT(DEBUG, "public_tgt_addr=%s ", addr_str(u8p)); - u8p += BLE_HS_ADV_PUBLIC_TGT_ADDR_ENTRY_LEN; - } - MODLOG_DFLT(DEBUG, "\n"); - } - - if (fields->appearance_is_present) { - MODLOG_DFLT(DEBUG, " appearance=0x%04x\n", fields->appearance); - } - - if (fields->adv_itvl_is_present) { - MODLOG_DFLT(DEBUG, " adv_itvl=0x%04x\n", fields->adv_itvl); - } - - if (fields->svc_data_uuid32 != NULL) { - MODLOG_DFLT(DEBUG, " svc_data_uuid32="); - print_bytes(fields->svc_data_uuid32, fields->svc_data_uuid32_len); - MODLOG_DFLT(DEBUG, "\n"); - } - - if (fields->svc_data_uuid128 != NULL) { - MODLOG_DFLT(DEBUG, " svc_data_uuid128="); - print_bytes(fields->svc_data_uuid128, fields->svc_data_uuid128_len); - MODLOG_DFLT(DEBUG, "\n"); - } - - if (fields->uri != NULL) { - MODLOG_DFLT(DEBUG, " uri="); - print_bytes(fields->uri, fields->uri_len); - MODLOG_DFLT(DEBUG, "\n"); - } - - if (fields->mfg_data != NULL) { - MODLOG_DFLT(DEBUG, " mfg_data="); - print_bytes(fields->mfg_data, fields->mfg_data_len); - MODLOG_DFLT(DEBUG, "\n"); - } -} diff --git a/examples/bluetooth/nimble/blecent/main/peer.c b/examples/bluetooth/nimble/blecent/main/peer.c deleted file mode 100644 index a01ae061e3..0000000000 --- a/examples/bluetooth/nimble/blecent/main/peer.c +++ /dev/null @@ -1,807 +0,0 @@ -/* - * Licensed to the Apache Software Foundation (ASF) under one - * or more contributor license agreements. See the NOTICE file - * distributed with this work for additional information - * regarding copyright ownership. The ASF licenses this file - * to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance - * with the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, - * software distributed under the License is distributed on an - * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - * KIND, either express or implied. See the License for the - * specific language governing permissions and limitations - * under the License. - */ - -#include -#include -#include "host/ble_hs.h" -#include "blecent.h" - -static void *peer_svc_mem; -static struct os_mempool peer_svc_pool; - -static void *peer_chr_mem; -static struct os_mempool peer_chr_pool; - -static void *peer_dsc_mem; -static struct os_mempool peer_dsc_pool; - -static void *peer_mem; -static struct os_mempool peer_pool; -static SLIST_HEAD(, peer) peers; - -static struct peer_svc * -peer_svc_find_range(struct peer *peer, uint16_t attr_handle); -static struct peer_svc * -peer_svc_find(struct peer *peer, uint16_t svc_start_handle, - struct peer_svc **out_prev); -int -peer_svc_is_empty(const struct peer_svc *svc); - -uint16_t -chr_end_handle(const struct peer_svc *svc, const struct peer_chr *chr); -int -chr_is_empty(const struct peer_svc *svc, const struct peer_chr *chr); -static struct peer_chr * -peer_chr_find(const struct peer_svc *svc, uint16_t chr_def_handle, - struct peer_chr **out_prev); -static void -peer_disc_chrs(struct peer *peer); - -static int -peer_dsc_disced(uint16_t conn_handle, const struct ble_gatt_error *error, - uint16_t chr_val_handle, const struct ble_gatt_dsc *dsc, - void *arg); - -struct peer * -peer_find(uint16_t conn_handle) -{ - struct peer *peer; - - SLIST_FOREACH(peer, &peers, next) { - if (peer->conn_handle == conn_handle) { - return peer; - } - } - - return NULL; -} - -static void -peer_disc_complete(struct peer *peer, int rc) -{ - peer->disc_prev_chr_val = 0; - - /* Notify caller that discovery has completed. */ - if (peer->disc_cb != NULL) { - peer->disc_cb(peer, rc, peer->disc_cb_arg); - } -} - -static struct peer_dsc * -peer_dsc_find_prev(const struct peer_chr *chr, uint16_t dsc_handle) -{ - struct peer_dsc *prev; - struct peer_dsc *dsc; - - prev = NULL; - SLIST_FOREACH(dsc, &chr->dscs, next) { - if (dsc->dsc.handle >= dsc_handle) { - break; - } - - prev = dsc; - } - - return prev; -} - -static struct peer_dsc * -peer_dsc_find(const struct peer_chr *chr, uint16_t dsc_handle, - struct peer_dsc **out_prev) -{ - struct peer_dsc *prev; - struct peer_dsc *dsc; - - prev = peer_dsc_find_prev(chr, dsc_handle); - if (prev == NULL) { - dsc = SLIST_FIRST(&chr->dscs); - } else { - dsc = SLIST_NEXT(prev, next); - } - - if (dsc != NULL && dsc->dsc.handle != dsc_handle) { - dsc = NULL; - } - - if (out_prev != NULL) { - *out_prev = prev; - } - return dsc; -} - -static int -peer_dsc_add(struct peer *peer, uint16_t chr_val_handle, - const struct ble_gatt_dsc *gatt_dsc) -{ - struct peer_dsc *prev; - struct peer_dsc *dsc; - struct peer_svc *svc; - struct peer_chr *chr; - - svc = peer_svc_find_range(peer, chr_val_handle); - if (svc == NULL) { - /* Can't find service for discovered descriptor; this shouldn't - * happen. - */ - assert(0); - return BLE_HS_EUNKNOWN; - } - - chr = peer_chr_find(svc, chr_val_handle, NULL); - if (chr == NULL) { - /* Can't find characteristic for discovered descriptor; this shouldn't - * happen. - */ - assert(0); - return BLE_HS_EUNKNOWN; - } - - dsc = peer_dsc_find(chr, gatt_dsc->handle, &prev); - if (dsc != NULL) { - /* Descriptor already discovered. */ - return 0; - } - - dsc = os_memblock_get(&peer_dsc_pool); - if (dsc == NULL) { - /* Out of memory. */ - return BLE_HS_ENOMEM; - } - memset(dsc, 0, sizeof * dsc); - - dsc->dsc = *gatt_dsc; - - if (prev == NULL) { - SLIST_INSERT_HEAD(&chr->dscs, dsc, next); - } else { - SLIST_NEXT(prev, next) = dsc; - } - - return 0; -} - -static void -peer_disc_dscs(struct peer *peer) -{ - struct peer_chr *chr; - struct peer_svc *svc; - int rc; - - /* Search through the list of discovered characteristics for the first - * characteristic that contains undiscovered descriptors. Then, discover - * all descriptors belonging to that characteristic. - */ - SLIST_FOREACH(svc, &peer->svcs, next) { - SLIST_FOREACH(chr, &svc->chrs, next) { - if (!chr_is_empty(svc, chr) && - SLIST_EMPTY(&chr->dscs) && - peer->disc_prev_chr_val <= chr->chr.def_handle) { - - rc = ble_gattc_disc_all_dscs(peer->conn_handle, - chr->chr.val_handle, - chr_end_handle(svc, chr), - peer_dsc_disced, peer); - if (rc != 0) { - peer_disc_complete(peer, rc); - } - - peer->disc_prev_chr_val = chr->chr.val_handle; - return; - } - } - } - - /* All descriptors discovered. */ - peer_disc_complete(peer, 0); -} - -static int -peer_dsc_disced(uint16_t conn_handle, const struct ble_gatt_error *error, - uint16_t chr_val_handle, const struct ble_gatt_dsc *dsc, - void *arg) -{ - struct peer *peer; - int rc; - - peer = arg; - assert(peer->conn_handle == conn_handle); - - switch (error->status) { - case 0: - rc = peer_dsc_add(peer, chr_val_handle, dsc); - break; - - case BLE_HS_EDONE: - /* All descriptors in this characteristic discovered; start discovering - * descriptors in the next characteristic. - */ - if (peer->disc_prev_chr_val > 0) { - peer_disc_dscs(peer); - } - rc = 0; - break; - - default: - /* Error; abort discovery. */ - rc = error->status; - break; - } - - if (rc != 0) { - /* Error; abort discovery. */ - peer_disc_complete(peer, rc); - } - - return rc; -} - -uint16_t -chr_end_handle(const struct peer_svc *svc, const struct peer_chr *chr) -{ - const struct peer_chr *next_chr; - - next_chr = SLIST_NEXT(chr, next); - if (next_chr != NULL) { - return next_chr->chr.def_handle - 1; - } else { - return svc->svc.end_handle; - } -} - -int -chr_is_empty(const struct peer_svc *svc, const struct peer_chr *chr) -{ - return chr_end_handle(svc, chr) <= chr->chr.val_handle; -} - -static struct peer_chr * -peer_chr_find_prev(const struct peer_svc *svc, uint16_t chr_val_handle) -{ - struct peer_chr *prev; - struct peer_chr *chr; - - prev = NULL; - SLIST_FOREACH(chr, &svc->chrs, next) { - if (chr->chr.val_handle >= chr_val_handle) { - break; - } - - prev = chr; - } - - return prev; -} - -static struct peer_chr * -peer_chr_find(const struct peer_svc *svc, uint16_t chr_val_handle, - struct peer_chr **out_prev) -{ - struct peer_chr *prev; - struct peer_chr *chr; - - prev = peer_chr_find_prev(svc, chr_val_handle); - if (prev == NULL) { - chr = SLIST_FIRST(&svc->chrs); - } else { - chr = SLIST_NEXT(prev, next); - } - - if (chr != NULL && chr->chr.val_handle != chr_val_handle) { - chr = NULL; - } - - if (out_prev != NULL) { - *out_prev = prev; - } - return chr; -} - -static void -peer_chr_delete(struct peer_chr *chr) -{ - struct peer_dsc *dsc; - - while ((dsc = SLIST_FIRST(&chr->dscs)) != NULL) { - SLIST_REMOVE_HEAD(&chr->dscs, next); - os_memblock_put(&peer_dsc_pool, dsc); - } - - os_memblock_put(&peer_chr_pool, chr); -} - -static int -peer_chr_add(struct peer *peer, uint16_t svc_start_handle, - const struct ble_gatt_chr *gatt_chr) -{ - struct peer_chr *prev; - struct peer_chr *chr; - struct peer_svc *svc; - - svc = peer_svc_find(peer, svc_start_handle, NULL); - if (svc == NULL) { - /* Can't find service for discovered characteristic; this shouldn't - * happen. - */ - assert(0); - return BLE_HS_EUNKNOWN; - } - - chr = peer_chr_find(svc, gatt_chr->def_handle, &prev); - if (chr != NULL) { - /* Characteristic already discovered. */ - return 0; - } - - chr = os_memblock_get(&peer_chr_pool); - if (chr == NULL) { - /* Out of memory. */ - return BLE_HS_ENOMEM; - } - memset(chr, 0, sizeof * chr); - - chr->chr = *gatt_chr; - - if (prev == NULL) { - SLIST_INSERT_HEAD(&svc->chrs, chr, next); - } else { - SLIST_NEXT(prev, next) = chr; - } - - return 0; -} - -static int -peer_chr_disced(uint16_t conn_handle, const struct ble_gatt_error *error, - const struct ble_gatt_chr *chr, void *arg) -{ - struct peer *peer; - int rc; - - peer = arg; - assert(peer->conn_handle == conn_handle); - - switch (error->status) { - case 0: - rc = peer_chr_add(peer, peer->cur_svc->svc.start_handle, chr); - break; - - case BLE_HS_EDONE: - /* All characteristics in this service discovered; start discovering - * characteristics in the next service. - */ - if (peer->disc_prev_chr_val > 0) { - peer_disc_chrs(peer); - } - rc = 0; - break; - - default: - rc = error->status; - break; - } - - if (rc != 0) { - /* Error; abort discovery. */ - peer_disc_complete(peer, rc); - } - - return rc; -} - -static void -peer_disc_chrs(struct peer *peer) -{ - struct peer_svc *svc; - int rc; - - /* Search through the list of discovered service for the first service that - * contains undiscovered characteristics. Then, discover all - * characteristics belonging to that service. - */ - SLIST_FOREACH(svc, &peer->svcs, next) { - if (!peer_svc_is_empty(svc) && SLIST_EMPTY(&svc->chrs)) { - peer->cur_svc = svc; - rc = ble_gattc_disc_all_chrs(peer->conn_handle, - svc->svc.start_handle, - svc->svc.end_handle, - peer_chr_disced, peer); - if (rc != 0) { - peer_disc_complete(peer, rc); - } - return; - } - } - - /* All characteristics discovered. */ - peer_disc_dscs(peer); -} - -int -peer_svc_is_empty(const struct peer_svc *svc) -{ - return svc->svc.end_handle <= svc->svc.start_handle; -} - -static struct peer_svc * -peer_svc_find_prev(struct peer *peer, uint16_t svc_start_handle) -{ - struct peer_svc *prev; - struct peer_svc *svc; - - prev = NULL; - SLIST_FOREACH(svc, &peer->svcs, next) { - if (svc->svc.start_handle >= svc_start_handle) { - break; - } - - prev = svc; - } - - return prev; -} - -static struct peer_svc * -peer_svc_find(struct peer *peer, uint16_t svc_start_handle, - struct peer_svc **out_prev) -{ - struct peer_svc *prev; - struct peer_svc *svc; - - prev = peer_svc_find_prev(peer, svc_start_handle); - if (prev == NULL) { - svc = SLIST_FIRST(&peer->svcs); - } else { - svc = SLIST_NEXT(prev, next); - } - - if (svc != NULL && svc->svc.start_handle != svc_start_handle) { - svc = NULL; - } - - if (out_prev != NULL) { - *out_prev = prev; - } - return svc; -} - -static struct peer_svc * -peer_svc_find_range(struct peer *peer, uint16_t attr_handle) -{ - struct peer_svc *svc; - - SLIST_FOREACH(svc, &peer->svcs, next) { - if (svc->svc.start_handle <= attr_handle && - svc->svc.end_handle >= attr_handle) { - - return svc; - } - } - - return NULL; -} - -const struct peer_svc * -peer_svc_find_uuid(const struct peer *peer, const ble_uuid_t *uuid) -{ - const struct peer_svc *svc; - - SLIST_FOREACH(svc, &peer->svcs, next) { - if (ble_uuid_cmp(&svc->svc.uuid.u, uuid) == 0) { - return svc; - } - } - - return NULL; -} - -const struct peer_chr * -peer_chr_find_uuid(const struct peer *peer, const ble_uuid_t *svc_uuid, - const ble_uuid_t *chr_uuid) -{ - const struct peer_svc *svc; - const struct peer_chr *chr; - - svc = peer_svc_find_uuid(peer, svc_uuid); - if (svc == NULL) { - return NULL; - } - - SLIST_FOREACH(chr, &svc->chrs, next) { - if (ble_uuid_cmp(&chr->chr.uuid.u, chr_uuid) == 0) { - return chr; - } - } - - return NULL; -} - -const struct peer_dsc * -peer_dsc_find_uuid(const struct peer *peer, const ble_uuid_t *svc_uuid, - const ble_uuid_t *chr_uuid, const ble_uuid_t *dsc_uuid) -{ - const struct peer_chr *chr; - const struct peer_dsc *dsc; - - chr = peer_chr_find_uuid(peer, svc_uuid, chr_uuid); - if (chr == NULL) { - return NULL; - } - - SLIST_FOREACH(dsc, &chr->dscs, next) { - if (ble_uuid_cmp(&dsc->dsc.uuid.u, dsc_uuid) == 0) { - return dsc; - } - } - - return NULL; -} - -static int -peer_svc_add(struct peer *peer, const struct ble_gatt_svc *gatt_svc) -{ - struct peer_svc *prev; - struct peer_svc *svc; - - svc = peer_svc_find(peer, gatt_svc->start_handle, &prev); - if (svc != NULL) { - /* Service already discovered. */ - return 0; - } - - svc = os_memblock_get(&peer_svc_pool); - if (svc == NULL) { - /* Out of memory. */ - return BLE_HS_ENOMEM; - } - memset(svc, 0, sizeof * svc); - - svc->svc = *gatt_svc; - SLIST_INIT(&svc->chrs); - - if (prev == NULL) { - SLIST_INSERT_HEAD(&peer->svcs, svc, next); - } else { - SLIST_INSERT_AFTER(prev, svc, next); - } - - return 0; -} - -static void -peer_svc_delete(struct peer_svc *svc) -{ - struct peer_chr *chr; - - while ((chr = SLIST_FIRST(&svc->chrs)) != NULL) { - SLIST_REMOVE_HEAD(&svc->chrs, next); - peer_chr_delete(chr); - } - - os_memblock_put(&peer_svc_pool, svc); -} - -static int -peer_svc_disced(uint16_t conn_handle, const struct ble_gatt_error *error, - const struct ble_gatt_svc *service, void *arg) -{ - struct peer *peer; - int rc; - - peer = arg; - assert(peer->conn_handle == conn_handle); - - switch (error->status) { - case 0: - rc = peer_svc_add(peer, service); - break; - - case BLE_HS_EDONE: - /* All services discovered; start discovering characteristics. */ - if (peer->disc_prev_chr_val > 0) { - peer_disc_chrs(peer); - } - rc = 0; - break; - - default: - rc = error->status; - break; - } - - if (rc != 0) { - /* Error; abort discovery. */ - peer_disc_complete(peer, rc); - } - - return rc; -} - - -int -peer_disc_all(uint16_t conn_handle, peer_disc_fn *disc_cb, void *disc_cb_arg) -{ - struct peer_svc *svc; - struct peer *peer; - int rc; - - peer = peer_find(conn_handle); - if (peer == NULL) { - return BLE_HS_ENOTCONN; - } - - /* Undiscover everything first. */ - while ((svc = SLIST_FIRST(&peer->svcs)) != NULL) { - SLIST_REMOVE_HEAD(&peer->svcs, next); - peer_svc_delete(svc); - } - - peer->disc_prev_chr_val = 1; - peer->disc_cb = disc_cb; - peer->disc_cb_arg = disc_cb_arg; - - rc = ble_gattc_disc_all_svcs(conn_handle, peer_svc_disced, peer); - if (rc != 0) { - return rc; - } - - return 0; -} - -int -peer_delete(uint16_t conn_handle) -{ - struct peer_svc *svc; - struct peer *peer; - int rc; - - peer = peer_find(conn_handle); - if (peer == NULL) { - return BLE_HS_ENOTCONN; - } - - SLIST_REMOVE(&peers, peer, peer, next); - - while ((svc = SLIST_FIRST(&peer->svcs)) != NULL) { - SLIST_REMOVE_HEAD(&peer->svcs, next); - peer_svc_delete(svc); - } - - rc = os_memblock_put(&peer_pool, peer); - if (rc != 0) { - return BLE_HS_EOS; - } - - return 0; -} - -int -peer_add(uint16_t conn_handle) -{ - struct peer *peer; - - /* Make sure the connection handle is unique. */ - peer = peer_find(conn_handle); - if (peer != NULL) { - return BLE_HS_EALREADY; - } - - peer = os_memblock_get(&peer_pool); - if (peer == NULL) { - /* Out of memory. */ - return BLE_HS_ENOMEM; - } - - memset(peer, 0, sizeof * peer); - peer->conn_handle = conn_handle; - - SLIST_INSERT_HEAD(&peers, peer, next); - - return 0; -} - -static void -peer_free_mem(void) -{ - free(peer_mem); - peer_mem = NULL; - - free(peer_svc_mem); - peer_svc_mem = NULL; - - free(peer_chr_mem); - peer_chr_mem = NULL; - - free(peer_dsc_mem); - peer_dsc_mem = NULL; -} - -int -peer_init(int max_peers, int max_svcs, int max_chrs, int max_dscs) -{ - int rc; - - /* Free memory first in case this function gets called more than once. */ - peer_free_mem(); - - peer_mem = malloc( - OS_MEMPOOL_BYTES(max_peers, sizeof (struct peer))); - if (peer_mem == NULL) { - rc = BLE_HS_ENOMEM; - goto err; - } - - rc = os_mempool_init(&peer_pool, max_peers, - sizeof (struct peer), peer_mem, - "peer_pool"); - if (rc != 0) { - rc = BLE_HS_EOS; - goto err; - } - - peer_svc_mem = malloc( - OS_MEMPOOL_BYTES(max_svcs, sizeof (struct peer_svc))); - if (peer_svc_mem == NULL) { - rc = BLE_HS_ENOMEM; - goto err; - } - - rc = os_mempool_init(&peer_svc_pool, max_svcs, - sizeof (struct peer_svc), peer_svc_mem, - "peer_svc_pool"); - if (rc != 0) { - rc = BLE_HS_EOS; - goto err; - } - - peer_chr_mem = malloc( - OS_MEMPOOL_BYTES(max_chrs, sizeof (struct peer_chr))); - if (peer_chr_mem == NULL) { - rc = BLE_HS_ENOMEM; - goto err; - } - - rc = os_mempool_init(&peer_chr_pool, max_chrs, - sizeof (struct peer_chr), peer_chr_mem, - "peer_chr_pool"); - if (rc != 0) { - rc = BLE_HS_EOS; - goto err; - } - - peer_dsc_mem = malloc( - OS_MEMPOOL_BYTES(max_dscs, sizeof (struct peer_dsc))); - if (peer_dsc_mem == NULL) { - rc = BLE_HS_ENOMEM; - goto err; - } - - rc = os_mempool_init(&peer_dsc_pool, max_dscs, - sizeof (struct peer_dsc), peer_dsc_mem, - "peer_dsc_pool"); - if (rc != 0) { - rc = BLE_HS_EOS; - goto err; - } - - return 0; - -err: - peer_free_mem(); - return rc; -} diff --git a/examples/bluetooth/nimble/bleprph/CMakeLists.txt b/examples/bluetooth/nimble/bleprph/CMakeLists.txt index 0e8a4553f9..1156a75370 100644 --- a/examples/bluetooth/nimble/bleprph/CMakeLists.txt +++ b/examples/bluetooth/nimble/bleprph/CMakeLists.txt @@ -2,5 +2,7 @@ # CMakeLists in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.16) +set(EXTRA_COMPONENT_DIRS ${CMAKE_CURRENT_LIST_DIR}/../common/nimble_peripheral_utils) + include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(bleprph) diff --git a/examples/bluetooth/nimble/bleprph/main/CMakeLists.txt b/examples/bluetooth/nimble/bleprph/main/CMakeLists.txt index 621b69cbd3..4195d94b04 100644 --- a/examples/bluetooth/nimble/bleprph/main/CMakeLists.txt +++ b/examples/bluetooth/nimble/bleprph/main/CMakeLists.txt @@ -1,8 +1,6 @@ set(srcs "main.c" - "gatt_svr.c" - "misc.c" - "scli.c") + "gatt_svr.c") idf_component_register(SRCS "${srcs}" - INCLUDE_DIRS ".") + INCLUDE_DIRS ".") target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/bluetooth/nimble/bleprph/main/bleprph.h b/examples/bluetooth/nimble/bleprph/main/bleprph.h index cf90b9fb6a..f6b89a618f 100644 --- a/examples/bluetooth/nimble/bleprph/main/bleprph.h +++ b/examples/bluetooth/nimble/bleprph/main/bleprph.h @@ -23,6 +23,7 @@ #include #include "nimble/ble.h" #include "modlog/modlog.h" +#include "esp_peripheral.h" #ifdef __cplusplus extern "C" { #endif @@ -41,14 +42,6 @@ struct ble_gatt_register_ctxt; void gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *arg); int gatt_svr_init(void); -/* Console */ -int scli_init(void); -int scli_receive_key(int *key); - -/** Misc. */ -void print_bytes(const uint8_t *bytes, int len); -void print_addr(const void *addr); - #ifdef __cplusplus } #endif diff --git a/examples/bluetooth/nimble/bleprph/main/misc.c b/examples/bluetooth/nimble/bleprph/main/misc.c deleted file mode 100644 index 640b7ff8b6..0000000000 --- a/examples/bluetooth/nimble/bleprph/main/misc.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Licensed to the Apache Software Foundation (ASF) under one - * or more contributor license agreements. See the NOTICE file - * distributed with this work for additional information - * regarding copyright ownership. The ASF licenses this file - * to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance - * with the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, - * software distributed under the License is distributed on an - * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - * KIND, either express or implied. See the License for the - * specific language governing permissions and limitations - * under the License. - */ - -#include "bleprph.h" - -/** - * Utility function to log an array of bytes. - */ -void -print_bytes(const uint8_t *bytes, int len) -{ - int i; - - for (i = 0; i < len; i++) { - MODLOG_DFLT(INFO, "%s0x%02x", i != 0 ? ":" : "", bytes[i]); - } -} - -void -print_addr(const void *addr) -{ - const uint8_t *u8p; - - u8p = addr; - MODLOG_DFLT(INFO, "%02x:%02x:%02x:%02x:%02x:%02x", - u8p[5], u8p[4], u8p[3], u8p[2], u8p[1], u8p[0]); -} diff --git a/examples/bluetooth/nimble/bleprph/main/scli.c b/examples/bluetooth/nimble/bleprph/main/scli.c deleted file mode 100644 index 173e0a9166..0000000000 --- a/examples/bluetooth/nimble/bleprph/main/scli.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Licensed to the Apache Software Foundation (ASF) under one - * or more contributor license agreements. See the NOTICE file - * distributed with this work for additional information - * regarding copyright ownership. The ASF licenses this file - * to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance - * with the License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, - * software distributed under the License is distributed on an - * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - * KIND, either express or implied. See the License for the - * specific language governing permissions and limitations - * under the License. - */ - -#include -#include -#include "esp_log.h" -#include -#include -#include -#include -#include -#include -#include -#include "bleprph.h" - -#define BLE_RX_TIMEOUT (30000 / portTICK_PERIOD_MS) - -static TaskHandle_t cli_task; -static QueueHandle_t cli_handle; -static int stop; - -static int enter_passkey_handler(int argc, char *argv[]) -{ - int key; - char pkey[8]; - int num; - - if (argc != 2) { - return -1; - } - - sscanf(argv[1], "%s", pkey); - ESP_LOGI("You entered", "%s %s", argv[0], argv[1]); - num = pkey[0]; - - if (isalpha(num)) { - if ((strcasecmp(pkey, "Y") == 0) || (strcasecmp(pkey, "Yes") == 0)) { - key = 1; - xQueueSend(cli_handle, &key, 0); - } else { - key = 0; - xQueueSend(cli_handle, &key, 0); - } - } else { - sscanf(pkey, "%d", &key); - xQueueSend(cli_handle, &key, 0); - } - - return 0; -} - -int scli_receive_key(int *console_key) -{ - return xQueueReceive(cli_handle, console_key, BLE_RX_TIMEOUT); -} - -static esp_console_cmd_t cmds[] = { - { - .command = "key", - .help = "", - .func = enter_passkey_handler, - }, -}; - -static int ble_register_cli(void) -{ - int cmds_num = sizeof(cmds) / sizeof(esp_console_cmd_t); - int i; - for (i = 0; i < cmds_num; i++) { - esp_console_cmd_register(&cmds[i]); - } - return 0; -} - -static void scli_task(void *arg) -{ - int uart_num = (int) arg; - uint8_t linebuf[256]; - int i, cmd_ret; - esp_err_t ret; - QueueHandle_t uart_queue; - uart_event_t event; - - uart_driver_install(uart_num, 256, 0, 8, &uart_queue, 0); - /* Initialize the console */ - esp_console_config_t console_config = { - .max_cmdline_args = 8, - .max_cmdline_length = 256, - }; - - esp_console_init(&console_config); - - while (!stop) { - i = 0; - memset(linebuf, 0, sizeof(linebuf)); - do { - ret = xQueueReceive(uart_queue, (void * )&event, (TickType_t)portMAX_DELAY); - if (ret != pdPASS) { - if (stop == 1) { - break; - } else { - continue; - } - } - if (event.type == UART_DATA) { - while (uart_read_bytes(uart_num, (uint8_t *) &linebuf[i], 1, 0)) { - if (linebuf[i] == '\r') { - uart_write_bytes(uart_num, "\r\n", 2); - } else { - uart_write_bytes(uart_num, (char *) &linebuf[i], 1); - } - i++; - } - } - } while ((i < 255) && linebuf[i - 1] != '\r'); - if (stop) { - break; - } - /* Remove the truncating \r\n */ - linebuf[strlen((char *)linebuf) - 1] = '\0'; - ret = esp_console_run((char *) linebuf, &cmd_ret); - if (ret < 0) { - break; - } - } - vTaskDelete(NULL); -} - -int scli_init(void) -{ - /* Register CLI "key " to accept input from user during pairing */ - ble_register_cli(); - - xTaskCreate(scli_task, "scli_cli", 4096, (void *) 0, 3, &cli_task); - if (cli_task == NULL) { - return ESP_FAIL; - } - cli_handle = xQueueCreate( 1, sizeof(int) ); - if (cli_handle == NULL) { - return ESP_FAIL; - } - return ESP_OK; -} diff --git a/examples/bluetooth/nimble/common/nimble_central_utils/CMakeLists.txt b/examples/bluetooth/nimble/common/nimble_central_utils/CMakeLists.txt new file mode 100644 index 0000000000..f6ec8bde8d --- /dev/null +++ b/examples/bluetooth/nimble/common/nimble_central_utils/CMakeLists.txt @@ -0,0 +1,3 @@ +idf_component_register(SRCS "misc.c" "peer.c" + INCLUDE_DIRS "." + PRIV_REQUIRES bt) diff --git a/examples/bluetooth/nimble/common/nimble_central_utils/esp_central.h b/examples/bluetooth/nimble/common/nimble_central_utils/esp_central.h new file mode 100644 index 0000000000..740275d426 --- /dev/null +++ b/examples/bluetooth/nimble/common/nimble_central_utils/esp_central.h @@ -0,0 +1,89 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#ifndef H_ESP_CENTRAL_ +#define H_ESP_CENTRAL_ + +#include "modlog/modlog.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** Misc. */ +void print_bytes(const uint8_t *bytes, int len); +void print_mbuf(const struct os_mbuf *om); +void print_mbuf_data(const struct os_mbuf *om); +char *addr_str(const void *addr); +void print_uuid(const ble_uuid_t *uuid); +void print_conn_desc(const struct ble_gap_conn_desc *desc); +void print_adv_fields(const struct ble_hs_adv_fields *fields); +void ext_print_adv_report(const void *param); + +/** Peer. */ +struct peer_dsc { + SLIST_ENTRY(peer_dsc) next; + struct ble_gatt_dsc dsc; +}; +SLIST_HEAD(peer_dsc_list, peer_dsc); + +struct peer_chr { + SLIST_ENTRY(peer_chr) next; + struct ble_gatt_chr chr; + + struct peer_dsc_list dscs; +}; +SLIST_HEAD(peer_chr_list, peer_chr); + +struct peer_svc { + SLIST_ENTRY(peer_svc) next; + struct ble_gatt_svc svc; + + struct peer_chr_list chrs; +}; +SLIST_HEAD(peer_svc_list, peer_svc); + +struct peer; +typedef void peer_disc_fn(const struct peer *peer, int status, void *arg); + +struct peer { + SLIST_ENTRY(peer) next; + + uint16_t conn_handle; + + /** List of discovered GATT services. */ + struct peer_svc_list svcs; + + /** Keeps track of where we are in the service discovery process. */ + uint16_t disc_prev_chr_val; + struct peer_svc *cur_svc; + + /** Callback that gets executed when service discovery completes. */ + peer_disc_fn *disc_cb; + void *disc_cb_arg; +}; + +int peer_disc_all(uint16_t conn_handle, peer_disc_fn *disc_cb, + void *disc_cb_arg); +const struct peer_dsc * +peer_dsc_find_uuid(const struct peer *peer, const ble_uuid_t *svc_uuid, + const ble_uuid_t *chr_uuid, const ble_uuid_t *dsc_uuid); +const struct peer_chr * +peer_chr_find_uuid(const struct peer *peer, const ble_uuid_t *svc_uuid, + const ble_uuid_t *chr_uuid); +const struct peer_svc * +peer_svc_find_uuid(const struct peer *peer, const ble_uuid_t *uuid); +int peer_delete(uint16_t conn_handle); +int peer_add(uint16_t conn_handle); +int peer_init(int max_peers, int max_svcs, int max_chrs, int max_dscs); +struct peer * +peer_find(uint16_t conn_handle); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/main/misc.c b/examples/bluetooth/nimble/common/nimble_central_utils/misc.c similarity index 99% rename from examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/main/misc.c rename to examples/bluetooth/nimble/common/nimble_central_utils/misc.c index 5a57815e77..41f3dfff46 100644 --- a/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/main/misc.c +++ b/examples/bluetooth/nimble/common/nimble_central_utils/misc.c @@ -9,7 +9,7 @@ #include #include "host/ble_hs.h" #include "host/ble_uuid.h" -#include "coc_blecent.h" +#include "esp_central.h" /** * Utility function to log an array of bytes. diff --git a/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/main/peer.c b/examples/bluetooth/nimble/common/nimble_central_utils/peer.c similarity index 99% rename from examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/main/peer.c rename to examples/bluetooth/nimble/common/nimble_central_utils/peer.c index 5f0112766b..30cb1338af 100644 --- a/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/main/peer.c +++ b/examples/bluetooth/nimble/common/nimble_central_utils/peer.c @@ -7,7 +7,7 @@ #include #include #include "host/ble_hs.h" -#include "coc_blecent.h" +#include "esp_central.h" static void *peer_svc_mem; static struct os_mempool peer_svc_pool; diff --git a/examples/bluetooth/nimble/common/nimble_peripheral_utils/CMakeLists.txt b/examples/bluetooth/nimble/common/nimble_peripheral_utils/CMakeLists.txt new file mode 100644 index 0000000000..963f158e7f --- /dev/null +++ b/examples/bluetooth/nimble/common/nimble_peripheral_utils/CMakeLists.txt @@ -0,0 +1,3 @@ +idf_component_register(SRCS "misc.c" "scli.c" + INCLUDE_DIRS "." + PRIV_REQUIRES bt console driver) diff --git a/examples/bluetooth/nimble/common/nimble_peripheral_utils/esp_peripheral.h b/examples/bluetooth/nimble/common/nimble_peripheral_utils/esp_peripheral.h new file mode 100644 index 0000000000..9a68ee7166 --- /dev/null +++ b/examples/bluetooth/nimble/common/nimble_peripheral_utils/esp_peripheral.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#ifndef H_ESP_PERIPHERAL_ +#define H_ESP_PERIPHERAL_ + +#include +#include "nimble/ble.h" +#include "modlog/modlog.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* Console */ +int scli_init(void); +int scli_receive_key(int *key); + +/** Misc. */ +void print_bytes(const uint8_t *bytes, int len); +void print_addr(const void *addr); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/main/misc.c b/examples/bluetooth/nimble/common/nimble_peripheral_utils/misc.c similarity index 95% rename from examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/main/misc.c rename to examples/bluetooth/nimble/common/nimble_peripheral_utils/misc.c index 836e7b0864..543bfe7f6c 100644 --- a/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/main/misc.c +++ b/examples/bluetooth/nimble/common/nimble_peripheral_utils/misc.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ -#include "coc_bleprph.h" +#include "esp_peripheral.h" /** * Utility function to log an array of bytes. diff --git a/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/main/scli.c b/examples/bluetooth/nimble/common/nimble_peripheral_utils/scli.c similarity index 99% rename from examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/main/scli.c rename to examples/bluetooth/nimble/common/nimble_peripheral_utils/scli.c index f20aceaa00..0a5b4565ce 100644 --- a/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/main/scli.c +++ b/examples/bluetooth/nimble/common/nimble_peripheral_utils/scli.c @@ -14,7 +14,7 @@ #include #include #include -#include "coc_bleprph.h" +#include "esp_peripheral.h" #define BLE_RX_TIMEOUT (30000 / portTICK_PERIOD_MS) diff --git a/examples/build_system/.build-test-rules.yml b/examples/build_system/.build-test-rules.yml index 67ee6592c2..6388351100 100644 --- a/examples/build_system/.build-test-rules.yml +++ b/examples/build_system/.build-test-rules.yml @@ -6,11 +6,6 @@ examples/build_system/cmake/import_lib: temporary: true reason: lack of runners -examples/build_system/cmake/linux_host_app: - enable: - - if: IDF_TARGET == "linux" - reason: only test on linux - examples/build_system/cmake/plugins: disable_test: - if: IDF_TARGET not in ["esp32", "esp32c3"] diff --git a/examples/build_system/cmake/linux_host_app/CMakeLists.txt b/examples/build_system/cmake/linux_host_app/CMakeLists.txt deleted file mode 100644 index 060c9e4250..0000000000 --- a/examples/build_system/cmake/linux_host_app/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -cmake_minimum_required(VERSION 3.16) - -include($ENV{IDF_PATH}/tools/cmake/project.cmake) -set(COMPONENTS main) - -# Freertos is included via common components, however, currently only the mock component is compatible with linux -# target. -list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/mocks/freertos/") - -project(linux_host_app) diff --git a/examples/build_system/cmake/linux_host_app/README.md b/examples/build_system/cmake/linux_host_app/README.md deleted file mode 100644 index 02fbd5b5bd..0000000000 --- a/examples/build_system/cmake/linux_host_app/README.md +++ /dev/null @@ -1,38 +0,0 @@ -| Supported Targets | Linux | -| ----------------- | ----- | - -This hello-world example builds a simple hello-world application for Linux. -The compiler used is the Linux-gcc. - -There are two major differences to an IDF application built for an ESP chip compared to an application build for Linux: - -1. The entry-point on Linux is `int main(int argc, char **argv)`, instead of `void app_main(void)` on an ESP chip. - In this example for Linux, the `void app_main(void)` function is still included to make the connection to the IDF entry point clearer. - However, it is simply called by `int main(int argc, char **argv)`. - Refer to the source file [linux_host_app.cpp](main/linux_host_app.cpp) to see how it is used. - -2. The project-level [CMakeLists.txt](CMakeLists.txt) for Linux is different from that of a normal IDF application for an ESP chip. - On Linux, there is an additional line `set(COMPONENTS main)`, which clears the common requirements (default dependencies usually included in all IDF applications). - This is currently necessary as the Linux-host feature is still under development. - Otherwise, a lot of hardware-dependent code would be pulled in. - -# Requirements -Currently, Ruby is required for the mock override of FreeRTOS. - -# Build -Source the IDF environment as usual, then set the Linux target: -```bash -idf.py --preview set-target linux -``` -sdkconfig.defaults sets the Linux target by default, so this not strictly necessary. - -Once this is done, build the application: -```bash -idf.py build -``` -Since this application runs on host, the flashing step is unnecessary. - -# Run -```bash -`build/linux_host_app.elf` -``` diff --git a/examples/build_system/cmake/linux_host_app/main/CMakeLists.txt b/examples/build_system/cmake/linux_host_app/main/CMakeLists.txt deleted file mode 100644 index 25db9e0ab7..0000000000 --- a/examples/build_system/cmake/linux_host_app/main/CMakeLists.txt +++ /dev/null @@ -1 +0,0 @@ -idf_component_register(SRCS "linux_host_app.cpp") diff --git a/examples/build_system/cmake/linux_host_app/main/linux_host_app.cpp b/examples/build_system/cmake/linux_host_app/main/linux_host_app.cpp deleted file mode 100644 index 7c646d1743..0000000000 --- a/examples/build_system/cmake/linux_host_app/main/linux_host_app.cpp +++ /dev/null @@ -1,30 +0,0 @@ -/* Hello World Example - - This example code is in the Public Domain (or CC0 licensed, at your option.) - - Unless required by applicable law or agreed to in writing, this - software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR - CONDITIONS OF ANY KIND, either express or implied. -*/ - -#include "stdio.h" -#include - -void app_main() { - while(1) { - printf("Hello, Host!\n"); - - for (int i = 10; i >= 0; i--) { - printf("Restarting in %d seconds...\n", i); - sleep(1); - } - } -} - -int main(int argc, char **argv) -{ - setbuf(stdout, NULL); - app_main(); - - return 0; -} diff --git a/examples/build_system/cmake/linux_host_app/sdkconfig.defaults b/examples/build_system/cmake/linux_host_app/sdkconfig.defaults deleted file mode 100644 index f14d0b8caa..0000000000 --- a/examples/build_system/cmake/linux_host_app/sdkconfig.defaults +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=n -CONFIG_IDF_TARGET="linux" -CONFIG_COMPILER_CXX_EXCEPTIONS=y diff --git a/examples/build_system/wrappers/CMakeLists.txt b/examples/build_system/wrappers/CMakeLists.txt new file mode 100644 index 0000000000..1457f6eb9b --- /dev/null +++ b/examples/build_system/wrappers/CMakeLists.txt @@ -0,0 +1,6 @@ +# The following lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(wrappers) diff --git a/examples/build_system/wrappers/README.md b/examples/build_system/wrappers/README.md new file mode 100644 index 0000000000..05d28f1ac9 --- /dev/null +++ b/examples/build_system/wrappers/README.md @@ -0,0 +1,57 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | + +# Using wrapper to redefine IDF functions + +This examples shows a linker feature that will let anyone redefine or override any public function included in both ESP-IDF and the bootloader. + +Thanks to this, it is possible to modify the default behavior of a function or extend it. + +## Building this example + +To build this example, set the target first: +``` +# Build for ESP32-C3 for example +idf.py set-target esp32c3 +``` + +Launch the build: +``` +idf.py build +``` + +Finally, flash it and check the monitor: +``` +idf.py flash monitor +``` + +## Expected output + +This example will redefine the bootloader's `bootloader_print_banner` function and IDF's `esp_restart` function. + +Thus in the monitor, the following messages should appear: +``` +I (30) boot-wrapper: message from a bootloader wrapper +[...] +Restarting in 5 seconds... +Restarting is progress... +[...] +``` + +This shows that functions have been redefined successfully. + +## How does it work? + +When redefining a function, the option `-Wl,--wrap=a_common_idf_function` will tell the linker to replace all the occurrences of `a_common_idf_function` function calls in the code and precompiled libraries to `__wrap_a_common_idf_function`. Thus, the application should now provide such symbol. + +Moreover, the linker will also provide a new symbol, `__real_a_common_idf_function`, which points to the former function implementation. This is very handy if the new redefinition needs to call the former implementation at some point. + +## Limitations + +Because the wrapping system happens at link time, the function to redefine must be global. Indeed, functions marked as `static` won't be visible by the linker and thus, cannot be replaced. + +Moreover, even though it is not recommended, it is also possible to wrap IDF internal functions that are not marked as `static`. However, keep in mind that such function may be renamed or removed from one IDF version to another. Therefore, after upgrading IDF, make sure the functions you redefine have not been renamed or removed. + +Finally, wrapping certain functions may lead to bugs or undefined behavior, for example, redefining a function in IRAM by a function in flash may lead to exceptions at runtime. + +Overall, this wrapping method should be used at your own risk. diff --git a/examples/build_system/wrappers/bootloader_components/my_boot_message/CMakeLists.txt b/examples/build_system/wrappers/bootloader_components/my_boot_message/CMakeLists.txt new file mode 100644 index 0000000000..c8683aa677 --- /dev/null +++ b/examples/build_system/wrappers/bootloader_components/my_boot_message/CMakeLists.txt @@ -0,0 +1,13 @@ +# Since the IDF bootloader is part of a project different from the application one, we cannot put bootloader wrappers +# inside the application. Thus, we need to create this bootloader component, which will be included inside the +# final bootloader binary, to store our wrappers. +idf_component_register(SRCS "wrapper.c" + # Since our source file doesn't contain any symbol strictly required by the linker, the latter + # may completely omit it and discard out wrapper. Thus, the following option will force it to + # include our object file inside the final binary. + WHOLE_ARCHIVE) + +# Tell the linker that we want to redefine the function named `bootloader_print_banner`. +# We must now define a function named __wrap_bootloader_print_banner, which has the same +# signature as the former implementation. +target_link_libraries(${COMPONENT_LIB} INTERFACE "-Wl,--wrap=bootloader_print_banner") diff --git a/examples/build_system/wrappers/bootloader_components/my_boot_message/wrapper.c b/examples/build_system/wrappers/bootloader_components/my_boot_message/wrapper.c new file mode 100644 index 0000000000..b972017fdf --- /dev/null +++ b/examples/build_system/wrappers/bootloader_components/my_boot_message/wrapper.c @@ -0,0 +1,24 @@ +/* + * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: CC0-1.0 + */ +#include "esp_log.h" + +static const char *TAG = "boot-wrapper"; + +/** + * Declare the following symbol in order to have access to the original function implementation + */ +extern void __real_bootloader_print_banner(void); + +/** + * Extend the bootloader's print banner function. + */ +void __wrap_bootloader_print_banner(void) +{ + /* Let's first let the original code run */ + __real_bootloader_print_banner(); + /* and then extend it by printing another message */ + ESP_LOGI(TAG, "message from a bootloader wrapper"); +} diff --git a/examples/build_system/wrappers/main/CMakeLists.txt b/examples/build_system/wrappers/main/CMakeLists.txt new file mode 100644 index 0000000000..438e36444a --- /dev/null +++ b/examples/build_system/wrappers/main/CMakeLists.txt @@ -0,0 +1,9 @@ +# For this component, contraty to the bootloader's one, we don't need the WHOLE_ARCHIVE option. +# This is due to the fact that this source file, app_wrapper.c, contains a strong symbol that is required by the linker +# in order to generate the final binary: `app_main`. Thus, the whole app_wrapper object file, including the wrapper +# it contains, will be included inside the application binary. +idf_component_register(SRCS "app_wrapper.c") + +# Tell the linker that we want to redefine the function named `esp_restart`. +# We must now define a function named __wrap_esp_restart, which has the same signature as the former implementation. +target_link_libraries(${COMPONENT_LIB} INTERFACE "-Wl,--wrap=esp_restart") diff --git a/examples/build_system/wrappers/main/app_wrapper.c b/examples/build_system/wrappers/main/app_wrapper.c new file mode 100644 index 0000000000..64a210bdeb --- /dev/null +++ b/examples/build_system/wrappers/main/app_wrapper.c @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: CC0-1.0 + */ + +#include +#include "sdkconfig.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + +/** + * Declare the symbol pointing to the former implementation of esp_restart function + */ +extern void __real_esp_restart(void); + + +/** + * Redefine esp_restart function to print a message before actually restarting + */ +void __wrap_esp_restart(void) +{ + printf("Restarting in progress...\n"); + /* Call the former implementation to actually restart the board */ + __real_esp_restart(); +} + +void app_main(void) +{ + printf("Restarting in 5 seconds...\n"); + vTaskDelay(5000 / portTICK_PERIOD_MS); + esp_restart(); +} diff --git a/examples/common_components/env_caps/esp32c6/Kconfig.env_caps b/examples/common_components/env_caps/esp32c6/Kconfig.env_caps new file mode 100644 index 0000000000..39167df4f9 --- /dev/null +++ b/examples/common_components/env_caps/esp32c6/Kconfig.env_caps @@ -0,0 +1,16 @@ +config ENV_GPIO_RANGE_MIN + int + default 0 + +config ENV_GPIO_RANGE_MAX + int + default 30 + # GPIOs 16/17 are always used by UART in examples + +config ENV_GPIO_IN_RANGE_MAX + int + default ENV_GPIO_RANGE_MAX + +config ENV_GPIO_OUT_RANGE_MAX + int + default ENV_GPIO_RANGE_MAX diff --git a/examples/common_components/led_strip/CMakeLists.txt b/examples/common_components/led_strip/CMakeLists.txt deleted file mode 100644 index bdf92d10fc..0000000000 --- a/examples/common_components/led_strip/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -set(srcs "src/led_strip_api.c") - -if(CONFIG_SOC_RMT_SUPPORTED) - list(APPEND srcs "src/led_strip_rmt_dev.c" "src/led_strip_rmt_encoder.c") -endif() - -idf_component_register(SRCS ${srcs} - INCLUDE_DIRS "include" "interface" - PRIV_REQUIRES "driver") diff --git a/examples/common_components/led_strip/README.md b/examples/common_components/led_strip/README.md deleted file mode 100644 index 8f3dae326e..0000000000 --- a/examples/common_components/led_strip/README.md +++ /dev/null @@ -1,15 +0,0 @@ -# LED Strip Component - -This directory contains an implementation for addressable LEDs by different peripherals. Currently only RMT is supported as the led strip backend. - -It's compatible with: - -* [WS2812](http://www.world-semi.com/Certifications/WS2812B.html) -* SK68XX - -This component is used as part of the following ESP-IDF examples: -- [Blink Example](../../get-started/blink). - -To learn more about how to use this component, please check API Documentation from header file [led_strip.h](./include/led_strip.h). - -Please note that this component is not considered to be a part of ESP-IDF stable API. It may change and it may be removed in the future releases. diff --git a/examples/common_components/led_strip/include/led_strip.h b/examples/common_components/led_strip/include/led_strip.h deleted file mode 100644 index d49a530ca4..0000000000 --- a/examples/common_components/led_strip/include/led_strip.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "esp_err.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief LED strip handle - */ -typedef struct led_strip_t *led_strip_handle_t; - -/** - * @brief Set RGB for a specific pixel - * - * @param strip: LED strip - * @param index: index of pixel to set - * @param red: red part of color - * @param green: green part of color - * @param blue: blue part of color - * - * @return - * - ESP_OK: Set RGB for a specific pixel successfully - * - ESP_ERR_INVALID_ARG: Set RGB for a specific pixel failed because of invalid parameters - * - ESP_FAIL: Set RGB for a specific pixel failed because other error occurred - */ -esp_err_t led_strip_set_pixel(led_strip_handle_t strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue); - -/** - * @brief Refresh memory colors to LEDs - * - * @param strip: LED strip - * - * @return - * - ESP_OK: Refresh successfully - * - ESP_FAIL: Refresh failed because some other error occurred - * - * @note: - * After updating the LED colors in the memory, a following invocation of this API is needed to flush colors to strip. - */ -esp_err_t led_strip_refresh(led_strip_handle_t strip); - -/** - * @brief Clear LED strip (turn off all LEDs) - * - * @param strip: LED strip - * - * @return - * - ESP_OK: Clear LEDs successfully - * - ESP_FAIL: Clear LEDs failed because some other error occurred - */ -esp_err_t led_strip_clear(led_strip_handle_t strip); - -/** - * @brief Free LED strip resources - * - * @param strip: LED strip - * - * @return - * - ESP_OK: Free resources successfully - * - ESP_FAIL: Free resources failed because error occurred - */ -esp_err_t led_strip_del(led_strip_handle_t strip); - -/** - * @brief LED Strip Configuration - */ -typedef struct { - uint32_t strip_gpio_num; /*!< GPIO number that used by LED strip */ - uint32_t max_leds; /*!< Maximum LEDs in a single strip */ -} led_strip_config_t; - -/** - * @brief Create LED strip based on RMT TX channel - * - * @param config LED strip specific configuration - * @param ret_strip Returned LED strip handle - * @return - * - ESP_OK: create LED strip handle successfully - * - ESP_ERR_INVALID_ARG: create LED strip handle failed because of invalid argument - * - ESP_ERR_NO_MEM: create LED strip handle failed because of out of memory - * - ESP_FAIL: create LED strip handle failed because some other error - */ -esp_err_t led_strip_new_rmt_device(const led_strip_config_t *config, led_strip_handle_t *ret_strip); - -#ifdef __cplusplus -} -#endif diff --git a/examples/common_components/led_strip/interface/led_strip_interface.h b/examples/common_components/led_strip/interface/led_strip_interface.h deleted file mode 100644 index 3ba15df2ba..0000000000 --- a/examples/common_components/led_strip/interface/led_strip_interface.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "esp_err.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct led_strip_t led_strip_t; /*!< Type of LED strip */ - -/** - * @brief LED strip interface definition - */ -struct led_strip_t { - /** - * @brief Set RGB for a specific pixel - * - * @param strip: LED strip - * @param index: index of pixel to set - * @param red: red part of color - * @param green: green part of color - * @param blue: blue part of color - * - * @return - * - ESP_OK: Set RGB for a specific pixel successfully - * - ESP_ERR_INVALID_ARG: Set RGB for a specific pixel failed because of invalid parameters - * - ESP_FAIL: Set RGB for a specific pixel failed because other error occurred - */ - esp_err_t (*set_pixel)(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue); - - /** - * @brief Refresh memory colors to LEDs - * - * @param strip: LED strip - * @param timeout_ms: timeout value for refreshing task - * - * @return - * - ESP_OK: Refresh successfully - * - ESP_FAIL: Refresh failed because some other error occurred - * - * @note: - * After updating the LED colors in the memory, a following invocation of this API is needed to flush colors to strip. - */ - esp_err_t (*refresh)(led_strip_t *strip); - - /** - * @brief Clear LED strip (turn off all LEDs) - * - * @param strip: LED strip - * @param timeout_ms: timeout value for clearing task - * - * @return - * - ESP_OK: Clear LEDs successfully - * - ESP_FAIL: Clear LEDs failed because some other error occurred - */ - esp_err_t (*clear)(led_strip_t *strip); - - /** - * @brief Free LED strip resources - * - * @param strip: LED strip - * - * @return - * - ESP_OK: Free resources successfully - * - ESP_FAIL: Free resources failed because error occurred - */ - esp_err_t (*del)(led_strip_t *strip); -}; - -#ifdef __cplusplus -} -#endif diff --git a/examples/common_components/led_strip/src/led_strip_api.c b/examples/common_components/led_strip/src/led_strip_api.c deleted file mode 100644 index b2fbf8f175..0000000000 --- a/examples/common_components/led_strip/src/led_strip_api.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "esp_log.h" -#include "esp_check.h" -#include "led_strip.h" -#include "led_strip_interface.h" - -static const char *TAG = "led_strip"; - -esp_err_t led_strip_set_pixel(led_strip_handle_t strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue) -{ - ESP_RETURN_ON_FALSE(strip, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - return strip->set_pixel(strip, index, red, green, blue); -} - -esp_err_t led_strip_refresh(led_strip_handle_t strip) -{ - ESP_RETURN_ON_FALSE(strip, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - return strip->refresh(strip); -} - -esp_err_t led_strip_clear(led_strip_handle_t strip) -{ - ESP_RETURN_ON_FALSE(strip, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - return strip->clear(strip); -} - -esp_err_t led_strip_del(led_strip_handle_t strip) -{ - ESP_RETURN_ON_FALSE(strip, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - return strip->del(strip); -} diff --git a/examples/common_components/led_strip/src/led_strip_rmt_dev.c b/examples/common_components/led_strip/src/led_strip_rmt_dev.c deleted file mode 100644 index 7658df8c93..0000000000 --- a/examples/common_components/led_strip/src/led_strip_rmt_dev.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include -#include -#include -#include "esp_log.h" -#include "esp_check.h" -#include "driver/rmt_tx.h" -#include "led_strip.h" -#include "led_strip_interface.h" -#include "led_strip_rmt_encoder.h" - -#define LED_SRIP_RMT_RESOLUTION 10000000 // 10MHz resolution - -static const char *TAG = "led_strip_rmt"; - -typedef struct { - led_strip_t base; - rmt_channel_handle_t rmt_chan; - rmt_encoder_handle_t strip_encoder; - uint32_t strip_len; - uint8_t pixel_buf[]; -} led_strip_rmt_obj; - -static esp_err_t led_strip_rmt_set_pixel(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue) -{ - led_strip_rmt_obj *rmt_strip = __containerof(strip, led_strip_rmt_obj, base); - ESP_RETURN_ON_FALSE(index < rmt_strip->strip_len, ESP_ERR_INVALID_ARG, TAG, "index out of maximum number of LEDs"); - uint32_t start = index * 3; - // In thr order of GRB, as LED strip like WS2812 sends out pixels in this order - rmt_strip->pixel_buf[start + 0] = green & 0xFF; - rmt_strip->pixel_buf[start + 1] = red & 0xFF; - rmt_strip->pixel_buf[start + 2] = blue & 0xFF; - return ESP_OK; -} - -static esp_err_t led_strip_rmt_refresh(led_strip_t *strip) -{ - led_strip_rmt_obj *rmt_strip = __containerof(strip, led_strip_rmt_obj, base); - rmt_transmit_config_t tx_conf = { - .loop_count = 0, - }; - ESP_RETURN_ON_ERROR(rmt_transmit(rmt_strip->rmt_chan, rmt_strip->strip_encoder, rmt_strip->pixel_buf, - rmt_strip->strip_len * 3, &tx_conf), TAG, "transmit pixels by RMT failed"); - ESP_RETURN_ON_ERROR(rmt_tx_wait_all_done(rmt_strip->rmt_chan, -1), TAG, "flush RMT channel failed"); - return ESP_OK; -} - -static esp_err_t led_strip_rmt_clear(led_strip_t *strip) -{ - led_strip_rmt_obj *rmt_strip = __containerof(strip, led_strip_rmt_obj, base); - // Write zero to turn off all leds - memset(rmt_strip->pixel_buf, 0, rmt_strip->strip_len * 3); - return led_strip_rmt_refresh(strip); -} - -static esp_err_t led_strip_rmt_del(led_strip_t *strip) -{ - led_strip_rmt_obj *rmt_strip = __containerof(strip, led_strip_rmt_obj, base); - ESP_RETURN_ON_ERROR(rmt_disable(rmt_strip->rmt_chan), TAG, "disable RMT channel failed"); - ESP_RETURN_ON_ERROR(rmt_del_channel(rmt_strip->rmt_chan), TAG, "delete RMT channel failed"); - ESP_RETURN_ON_ERROR(rmt_del_encoder(rmt_strip->strip_encoder), TAG, "delete strip encoder failed"); - free(rmt_strip); - return ESP_OK; -} - -esp_err_t led_strip_new_rmt_device(const led_strip_config_t *config, led_strip_handle_t *ret_strip) -{ - led_strip_rmt_obj *rmt_strip = NULL; - esp_err_t ret = ESP_OK; - ESP_GOTO_ON_FALSE(config && ret_strip, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument"); - rmt_strip = calloc(1, sizeof(led_strip_rmt_obj) + config->max_leds * 3); - ESP_GOTO_ON_FALSE(rmt_strip, ESP_ERR_NO_MEM, err, TAG, "no mem for rmt strip"); - rmt_tx_channel_config_t rmt_chan_config = { - .clk_src = RMT_CLK_SRC_DEFAULT, - .gpio_num = config->strip_gpio_num, - .mem_block_symbols = 64, - .resolution_hz = LED_SRIP_RMT_RESOLUTION, - .trans_queue_depth = 4, - }; - ESP_GOTO_ON_ERROR(rmt_new_tx_channel(&rmt_chan_config, &rmt_strip->rmt_chan), err, TAG, "create RMT TX channel failed"); - - led_strip_encoder_config_t strip_encoder_conf = { - .resolution = LED_SRIP_RMT_RESOLUTION, - }; - ESP_GOTO_ON_ERROR(rmt_new_led_strip_encoder(&strip_encoder_conf, &rmt_strip->strip_encoder), err, TAG, "create LED strip encoder failed"); - - ESP_GOTO_ON_ERROR(rmt_enable(rmt_strip->rmt_chan), err, TAG, "enable RMT channel failed"); - - rmt_strip->strip_len = config->max_leds; - rmt_strip->base.set_pixel = led_strip_rmt_set_pixel; - rmt_strip->base.refresh = led_strip_rmt_refresh; - rmt_strip->base.clear = led_strip_rmt_clear; - rmt_strip->base.del = led_strip_rmt_del; - - *ret_strip = &rmt_strip->base; - return ESP_OK; -err: - if (rmt_strip) { - if (rmt_strip->rmt_chan) { - rmt_del_channel(rmt_strip->rmt_chan); - } - if (rmt_strip->strip_encoder) { - rmt_del_encoder(rmt_strip->strip_encoder); - } - free(rmt_strip); - } - return ret; -} diff --git a/examples/common_components/led_strip/src/led_strip_rmt_encoder.c b/examples/common_components/led_strip/src/led_strip_rmt_encoder.c deleted file mode 100644 index aa05fd3daf..0000000000 --- a/examples/common_components/led_strip/src/led_strip_rmt_encoder.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "esp_check.h" -#include "led_strip_rmt_encoder.h" - -static const char *TAG = "led_encoder"; - -typedef struct { - rmt_encoder_t base; - rmt_encoder_t *bytes_encoder; - rmt_encoder_t *copy_encoder; - int state; - rmt_symbol_word_t reset_code; -} rmt_led_strip_encoder_t; - -static size_t rmt_encode_led_strip(rmt_encoder_t *encoder, rmt_channel_handle_t channel, const void *primary_data, size_t data_size, rmt_encode_state_t *ret_state) -{ - rmt_led_strip_encoder_t *led_encoder = __containerof(encoder, rmt_led_strip_encoder_t, base); - rmt_encoder_handle_t bytes_encoder = led_encoder->bytes_encoder; - rmt_encoder_handle_t copy_encoder = led_encoder->copy_encoder; - rmt_encode_state_t session_state = 0; - rmt_encode_state_t state = 0; - size_t encoded_symbols = 0; - switch (led_encoder->state) { - case 0: // send RGB data - encoded_symbols += bytes_encoder->encode(bytes_encoder, channel, primary_data, data_size, &session_state); - if (session_state & RMT_ENCODING_COMPLETE) { - led_encoder->state = 1; // switch to next state when current encoding session finished - } - if (session_state & RMT_ENCODING_MEM_FULL) { - state |= RMT_ENCODING_MEM_FULL; - goto out; // yield if there's no free space for encoding artifacts - } - // fall-through - case 1: // send reset code - encoded_symbols += copy_encoder->encode(copy_encoder, channel, &led_encoder->reset_code, - sizeof(led_encoder->reset_code), &session_state); - if (session_state & RMT_ENCODING_COMPLETE) { - led_encoder->state = 0; // back to the initial encoding session - state |= RMT_ENCODING_COMPLETE; - } - if (session_state & RMT_ENCODING_MEM_FULL) { - state |= RMT_ENCODING_MEM_FULL; - goto out; // yield if there's no free space for encoding artifacts - } - } -out: - *ret_state = state; - return encoded_symbols; -} - -static esp_err_t rmt_del_led_strip_encoder(rmt_encoder_t *encoder) -{ - rmt_led_strip_encoder_t *led_encoder = __containerof(encoder, rmt_led_strip_encoder_t, base); - rmt_del_encoder(led_encoder->bytes_encoder); - rmt_del_encoder(led_encoder->copy_encoder); - free(led_encoder); - return ESP_OK; -} - -static esp_err_t rmt_led_strip_encoder_reset(rmt_encoder_t *encoder) -{ - rmt_led_strip_encoder_t *led_encoder = __containerof(encoder, rmt_led_strip_encoder_t, base); - rmt_encoder_reset(led_encoder->bytes_encoder); - rmt_encoder_reset(led_encoder->copy_encoder); - led_encoder->state = 0; - return ESP_OK; -} - -esp_err_t rmt_new_led_strip_encoder(const led_strip_encoder_config_t *config, rmt_encoder_handle_t *ret_encoder) -{ - esp_err_t ret = ESP_OK; - rmt_led_strip_encoder_t *led_encoder = NULL; - ESP_GOTO_ON_FALSE(config && ret_encoder, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument"); - led_encoder = calloc(1, sizeof(rmt_led_strip_encoder_t)); - ESP_GOTO_ON_FALSE(led_encoder, ESP_ERR_NO_MEM, err, TAG, "no mem for led strip encoder"); - led_encoder->base.encode = rmt_encode_led_strip; - led_encoder->base.del = rmt_del_led_strip_encoder; - led_encoder->base.reset = rmt_led_strip_encoder_reset; - // different led strip might have its own timing requirements, following parameter is for WS2812 - rmt_bytes_encoder_config_t bytes_encoder_config = { - .bit0 = { - .level0 = 1, - .duration0 = 0.3 * config->resolution / 1000000, // T0H=0.3us - .level1 = 0, - .duration1 = 0.9 * config->resolution / 1000000, // T0L=0.9us - }, - .bit1 = { - .level0 = 1, - .duration0 = 0.9 * config->resolution / 1000000, // T1H=0.9us - .level1 = 0, - .duration1 = 0.3 * config->resolution / 1000000, // T1L=0.3us - }, - .flags.msb_first = 1 // WS2812 transfer bit order: G7...G0R7...R0B7...B0 - }; - ESP_GOTO_ON_ERROR(rmt_new_bytes_encoder(&bytes_encoder_config, &led_encoder->bytes_encoder), err, TAG, "create bytes encoder failed"); - rmt_copy_encoder_config_t copy_encoder_config = {}; - ESP_GOTO_ON_ERROR(rmt_new_copy_encoder(©_encoder_config, &led_encoder->copy_encoder), err, TAG, "create copy encoder failed"); - - uint32_t reset_ticks = config->resolution / 1000000 * 50 / 2; // reset code duration defaults to 50us - led_encoder->reset_code = (rmt_symbol_word_t) { - .level0 = 0, - .duration0 = reset_ticks, - .level1 = 0, - .duration1 = reset_ticks, - }; - *ret_encoder = &led_encoder->base; - return ESP_OK; -err: - if (led_encoder) { - if (led_encoder->bytes_encoder) { - rmt_del_encoder(led_encoder->bytes_encoder); - } - if (led_encoder->copy_encoder) { - rmt_del_encoder(led_encoder->copy_encoder); - } - free(led_encoder); - } - return ret; -} diff --git a/examples/common_components/led_strip/src/led_strip_rmt_encoder.h b/examples/common_components/led_strip/src/led_strip_rmt_encoder.h deleted file mode 100644 index db5ef076b3..0000000000 --- a/examples/common_components/led_strip/src/led_strip_rmt_encoder.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "driver/rmt_encoder.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Type of led strip encoder configuration - */ -typedef struct { - uint32_t resolution; /*!< Encoder resolution, in Hz */ -} led_strip_encoder_config_t; - -/** - * @brief Create RMT encoder for encoding LED strip pixels into RMT symbols - * - * @param[in] config Encoder configuration - * @param[out] ret_encoder Returned encoder handle - * @return - * - ESP_ERR_INVALID_ARG for any invalid arguments - * - ESP_ERR_NO_MEM out of memory when creating led strip encoder - * - ESP_OK if creating encoder successfully - */ -esp_err_t rmt_new_led_strip_encoder(const led_strip_encoder_config_t *config, rmt_encoder_handle_t *ret_encoder); - -#ifdef __cplusplus -} -#endif diff --git a/examples/common_components/protocol_examples_common/eth_connect.c b/examples/common_components/protocol_examples_common/eth_connect.c index 71f06e2910..0b7d8f4b1a 100644 --- a/examples/common_components/protocol_examples_common/eth_connect.c +++ b/examples/common_components/protocol_examples_common/eth_connect.c @@ -21,6 +21,9 @@ static const char *TAG = "ethernet_connect"; static SemaphoreHandle_t s_semph_get_ip_addrs = NULL; +#if CONFIG_EXAMPLE_CONNECT_IPV6 +static SemaphoreHandle_t s_semph_get_ip6_addrs = NULL; +#endif static esp_netif_t *eth_start(void); static void eth_stop(void); @@ -36,9 +39,7 @@ static void eth_on_got_ip(void *arg, esp_event_base_t event_base, return; } ESP_LOGI(TAG, "Got IPv4 event: Interface \"%s\" address: " IPSTR, esp_netif_get_desc(event->esp_netif), IP2STR(&event->ip_info.ip)); - if (s_semph_get_ip_addrs) { - xSemaphoreGive(s_semph_get_ip_addrs); - } + xSemaphoreGive(s_semph_get_ip_addrs); } #if CONFIG_EXAMPLE_CONNECT_IPV6 @@ -54,7 +55,7 @@ static void eth_on_got_ipv6(void *arg, esp_event_base_t event_base, ESP_LOGI(TAG, "Got IPv6 event: Interface \"%s\" address: " IPV6STR ", type: %s", esp_netif_get_desc(event->esp_netif), IPV62STR(event->ip6_info.ip), example_ipv6_addr_types_to_str[ipv6_type]); if (ipv6_type == EXAMPLE_CONNECT_PREFERRED_IPV6_TYPE) { - xSemaphoreGive(s_semph_get_ip_addrs); + xSemaphoreGive(s_semph_get_ip6_addrs); } } @@ -204,16 +205,31 @@ void example_ethernet_shutdown(void) } vSemaphoreDelete(s_semph_get_ip_addrs); s_semph_get_ip_addrs = NULL; +#if CONFIG_EXAMPLE_CONNECT_IPV6 + vSemaphoreDelete(s_semph_get_ip6_addrs); + s_semph_get_ip6_addrs = NULL; +#endif eth_stop(); } esp_err_t example_ethernet_connect(void) { - s_semph_get_ip_addrs = xSemaphoreCreateCounting(NR_OF_IP_ADDRESSES_TO_WAIT_FOR, 0); + s_semph_get_ip_addrs = xSemaphoreCreateBinary(); + if (s_semph_get_ip_addrs == NULL) { + return ESP_ERR_NO_MEM; + } +#if CONFIG_EXAMPLE_CONNECT_IPV6 + s_semph_get_ip6_addrs = xSemaphoreCreateBinary(); + if (s_semph_get_ip6_addrs == NULL) { + vSemaphoreDelete(s_semph_get_ip_addrs); + return ESP_ERR_NO_MEM; + } +#endif eth_start(); ESP_LOGI(TAG, "Waiting for IP(s)."); - for (int i = 0; i < NR_OF_IP_ADDRESSES_TO_WAIT_FOR; ++i) { - xSemaphoreTake(s_semph_get_ip_addrs, portMAX_DELAY); - } + xSemaphoreTake(s_semph_get_ip_addrs, portMAX_DELAY); +#if CONFIG_EXAMPLE_CONNECT_IPV6 + xSemaphoreTake(s_semph_get_ip6_addrs, portMAX_DELAY); +#endif return ESP_OK; } diff --git a/examples/common_components/protocol_examples_common/include/example_common_private.h b/examples/common_components/protocol_examples_common/include/example_common_private.h index 03518bfbac..4921e477ea 100644 --- a/examples/common_components/protocol_examples_common/include/example_common_private.h +++ b/examples/common_components/protocol_examples_common/include/example_common_private.h @@ -15,13 +15,6 @@ extern "C" { #endif -#if CONFIG_EXAMPLE_CONNECT_IPV6 -#define NR_OF_IP_ADDRESSES_TO_WAIT_FOR (2) -#else -#define NR_OF_IP_ADDRESSES_TO_WAIT_FOR (1) -#endif - - #if CONFIG_EXAMPLE_CONNECT_IPV6 #define MAX_IP6_ADDRS_PER_NETIF (5) diff --git a/examples/common_components/protocol_examples_common/wifi_connect.c b/examples/common_components/protocol_examples_common/wifi_connect.c index 682367fffc..3e10407d93 100644 --- a/examples/common_components/protocol_examples_common/wifi_connect.c +++ b/examples/common_components/protocol_examples_common/wifi_connect.c @@ -22,6 +22,9 @@ static const char *TAG = "example_connect"; static esp_netif_t *s_example_sta_netif = NULL; static SemaphoreHandle_t s_semph_get_ip_addrs = NULL; +#if CONFIG_EXAMPLE_CONNECT_IPV6 +static SemaphoreHandle_t s_semph_get_ip6_addrs = NULL; +#endif #if CONFIG_EXAMPLE_WIFI_SCAN_METHOD_FAST #define EXAMPLE_WIFI_SCAN_METHOD WIFI_FAST_SCAN @@ -63,13 +66,15 @@ static void example_handler_on_wifi_disconnect(void *arg, esp_event_base_t event s_retry_num++; if (s_retry_num > CONFIG_EXAMPLE_WIFI_CONN_MAX_RETRY) { ESP_LOGI(TAG, "WiFi Connect failed %d times, stop reconnect.", s_retry_num); + /* let example_wifi_sta_do_connect() return */ if (s_semph_get_ip_addrs) { - /* let example_wifi_sta_do_connect() return */ xSemaphoreGive(s_semph_get_ip_addrs); -#if CONFIG_EXAMPLE_CONNECT_IPV6 - xSemaphoreGive(s_semph_get_ip_addrs); -#endif } +#if CONFIG_EXAMPLE_CONNECT_IPV6 + if (s_semph_get_ip6_addrs) { + xSemaphoreGive(s_semph_get_ip6_addrs); + } +#endif return; } ESP_LOGI(TAG, "Wi-Fi disconnected, trying to reconnect..."); @@ -117,8 +122,8 @@ static void example_handler_on_sta_got_ipv6(void *arg, esp_event_base_t event_ba IPV62STR(event->ip6_info.ip), example_ipv6_addr_types_to_str[ipv6_type]); if (ipv6_type == EXAMPLE_CONNECT_PREFERRED_IPV6_TYPE) { - if (s_semph_get_ip_addrs) { - xSemaphoreGive(s_semph_get_ip_addrs); + if (s_semph_get_ip6_addrs) { + xSemaphoreGive(s_semph_get_ip6_addrs); } else { ESP_LOGI(TAG, "- IPv6 address: " IPV6STR ", type: %s", IPV62STR(event->ip6_info.ip), example_ipv6_addr_types_to_str[ipv6_type]); } @@ -162,7 +167,17 @@ void example_wifi_stop(void) esp_err_t example_wifi_sta_do_connect(wifi_config_t wifi_config, bool wait) { if (wait) { - s_semph_get_ip_addrs = xSemaphoreCreateCounting(NR_OF_IP_ADDRESSES_TO_WAIT_FOR, 0); + s_semph_get_ip_addrs = xSemaphoreCreateBinary(); + if (s_semph_get_ip_addrs == NULL) { + return ESP_ERR_NO_MEM; + } +#if CONFIG_EXAMPLE_CONNECT_IPV6 + s_semph_get_ip6_addrs = xSemaphoreCreateBinary(); + if (s_semph_get_ip6_addrs == NULL) { + vSemaphoreDelete(s_semph_get_ip_addrs); + return ESP_ERR_NO_MEM; + } +#endif } s_retry_num = 0; ESP_ERROR_CHECK(esp_event_handler_register(WIFI_EVENT, WIFI_EVENT_STA_DISCONNECTED, &example_handler_on_wifi_disconnect, NULL)); @@ -181,9 +196,10 @@ esp_err_t example_wifi_sta_do_connect(wifi_config_t wifi_config, bool wait) } if (wait) { ESP_LOGI(TAG, "Waiting for IP(s)"); - for (int i = 0; i < NR_OF_IP_ADDRESSES_TO_WAIT_FOR; ++i) { - xSemaphoreTake(s_semph_get_ip_addrs, portMAX_DELAY); - } + xSemaphoreTake(s_semph_get_ip_addrs, portMAX_DELAY); +#if CONFIG_EXAMPLE_CONNECT_IPV6 + xSemaphoreTake(s_semph_get_ip6_addrs, portMAX_DELAY); +#endif if (s_retry_num > CONFIG_EXAMPLE_WIFI_CONN_MAX_RETRY) { return ESP_FAIL; } @@ -202,6 +218,11 @@ esp_err_t example_wifi_sta_do_disconnect(void) if (s_semph_get_ip_addrs) { vSemaphoreDelete(s_semph_get_ip_addrs); } +#if CONFIG_EXAMPLE_CONNECT_IPV6 + if (s_semph_get_ip6_addrs) { + vSemaphoreDelete(s_semph_get_ip6_addrs); + } +#endif return esp_wifi_disconnect(); } diff --git a/examples/cxx/experimental/experimental_cpp_component/host_test/fixtures/test_fixtures.hpp b/examples/cxx/experimental/experimental_cpp_component/host_test/fixtures/test_fixtures.hpp index 484762c249..1de85ab65f 100644 --- a/examples/cxx/experimental/experimental_cpp_component/host_test/fixtures/test_fixtures.hpp +++ b/examples/cxx/experimental/experimental_cpp_component/host_test/fixtures/test_fixtures.hpp @@ -300,7 +300,7 @@ struct SPITransactionDescriptorFix { }; struct I2CMasterFix { - I2CMasterFix(i2c_port_t port_arg = 0) : i2c_conf(), port(port_arg) + I2CMasterFix(i2c_port_t port_arg = I2C_NUM_0) : i2c_conf(), port(port_arg) { i2c_conf.mode = i2c_mode_t::I2C_MODE_MASTER; i2c_conf.sda_io_num = 2; @@ -320,7 +320,7 @@ struct I2CMasterFix { #if CONFIG_SOC_I2C_SUPPORT_SLAVE struct I2CSlaveFix { - I2CSlaveFix(CreateAnd flags, i2c_port_t port_arg = 0, size_t buffer_size = 64) : i2c_conf(), port(port_arg) + I2CSlaveFix(CreateAnd flags, i2c_port_t port_arg = I2C_NUM_0, size_t buffer_size = 64) : i2c_conf(), port(port_arg) { if (flags == CreateAnd::SUCCEED) { i2c_conf.mode = i2c_mode_t::I2C_MODE_SLAVE; diff --git a/examples/cxx/experimental/experimental_cpp_component/host_test/gpio/CMakeLists.txt b/examples/cxx/experimental/experimental_cpp_component/host_test/gpio/CMakeLists.txt index c640f7dfed..37c11659fa 100644 --- a/examples/cxx/experimental/experimental_cpp_component/host_test/gpio/CMakeLists.txt +++ b/examples/cxx/experimental/experimental_cpp_component/host_test/gpio/CMakeLists.txt @@ -3,8 +3,6 @@ cmake_minimum_required(VERSION 3.16) include($ENV{IDF_PATH}/tools/cmake/project.cmake) set(COMPONENTS main) -idf_build_set_property(COMPILE_DEFINITIONS "-DNO_DEBUG_STORAGE" APPEND) - # Overriding components which should be mocked list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/mocks/driver/") list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/mocks/freertos/") diff --git a/examples/cxx/experimental/experimental_cpp_component/host_test/i2c/CMakeLists.txt b/examples/cxx/experimental/experimental_cpp_component/host_test/i2c/CMakeLists.txt index 625bcfd457..948f0697f5 100644 --- a/examples/cxx/experimental/experimental_cpp_component/host_test/i2c/CMakeLists.txt +++ b/examples/cxx/experimental/experimental_cpp_component/host_test/i2c/CMakeLists.txt @@ -3,8 +3,6 @@ cmake_minimum_required(VERSION 3.16) include($ENV{IDF_PATH}/tools/cmake/project.cmake) set(COMPONENTS main) -idf_build_set_property(COMPILE_DEFINITIONS "-DNO_DEBUG_STORAGE" APPEND) - # Overriding components which should be mocked list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/mocks/driver/") list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/mocks/freertos/") diff --git a/examples/cxx/experimental/experimental_cpp_component/host_test/i2c/main/i2c_cxx_test.cpp b/examples/cxx/experimental/experimental_cpp_component/host_test/i2c/main/i2c_cxx_test.cpp index a3d2bcc085..60e274087b 100644 --- a/examples/cxx/experimental/experimental_cpp_component/host_test/i2c/main/i2c_cxx_test.cpp +++ b/examples/cxx/experimental/experimental_cpp_component/host_test/i2c/main/i2c_cxx_test.cpp @@ -183,7 +183,7 @@ TEST_CASE("I2CWrite calls driver correctly") // will actually write the data but for the tests it is enough for now i2c_master_write_ExpectWithArrayAndReturn(&cmd_fix.dummy_handle, expected_write, WRITE_SIZE, EXPECTED_DATA_LEN, true, ESP_OK); i2c_master_stop_ExpectAndReturn(&cmd_fix.dummy_handle, ESP_OK); - i2c_master_cmd_begin_ExpectAndReturn(0, &cmd_fix.dummy_handle, 1000 / portTICK_PERIOD_MS, ESP_OK); + i2c_master_cmd_begin_ExpectAndReturn(I2C_NUM_0, &cmd_fix.dummy_handle, 1000 / portTICK_PERIOD_MS, ESP_OK); std::vector WRITE_BYTES = {0xAB, 0xBA}; I2CWrite write(WRITE_BYTES); @@ -218,7 +218,7 @@ TEST_CASE("I2CRead calls driver correctly") // will actually read the data but for the tests it is enough for now i2c_master_read_ReturnArrayThruPtr_data(READ_DATA, READ_SIZE); i2c_master_stop_ExpectAndReturn(&cmd_fix.dummy_handle, ESP_OK); - i2c_master_cmd_begin_ExpectAndReturn(0, &cmd_fix.dummy_handle, 1000 / portTICK_PERIOD_MS, ESP_OK); + i2c_master_cmd_begin_ExpectAndReturn(I2C_NUM_0, &cmd_fix.dummy_handle, 1000 / portTICK_PERIOD_MS, ESP_OK); I2CRead reader(READ_SIZE); std::vector result = reader.do_transfer(I2CNumber::I2C0(), I2CAddress(0x47)); @@ -261,7 +261,7 @@ TEST_CASE("I2CComposed calls driver correctly") // will actually read the data but for the tests it is enough for now i2c_master_read_ReturnArrayThruPtr_data(READ_DATA, READ_SIZE); i2c_master_stop_ExpectAndReturn(&cmd_fix.dummy_handle, ESP_OK); - i2c_master_cmd_begin_ExpectAndReturn(0, &cmd_fix.dummy_handle, 1000 / portTICK_PERIOD_MS, ESP_OK); + i2c_master_cmd_begin_ExpectAndReturn(I2C_NUM_0, &cmd_fix.dummy_handle, 1000 / portTICK_PERIOD_MS, ESP_OK); I2CComposed composed_transfer; composed_transfer.add_write({0x47, 0x48, 0x49}); @@ -289,7 +289,7 @@ TEST_CASE("I2CWrite transfer calls driver correctly") // will actually write the data but for the tests it is enough for now i2c_master_write_ExpectWithArrayAndReturn(&cmd_fix.dummy_handle, expected_write, WRITE_SIZE, EXPECTED_DATA_LEN, true, ESP_OK); i2c_master_stop_ExpectAndReturn(&cmd_fix.dummy_handle, ESP_OK); - i2c_master_cmd_begin_ExpectAndReturn(0, &cmd_fix.dummy_handle, 1000 / portTICK_PERIOD_MS, ESP_OK); + i2c_master_cmd_begin_ExpectAndReturn(I2C_NUM_0, &cmd_fix.dummy_handle, 1000 / portTICK_PERIOD_MS, ESP_OK); I2CMaster master(I2CNumber::I2C0(), SCL_GPIO(1), SDA_GPIO(2), Frequency(400000)); std::vector WRITE_BYTES = {0xAB, 0xBA}; @@ -310,7 +310,7 @@ TEST_CASE("I2CMaster synchronous write") // will actually write the data but for the tests it is enough for now i2c_master_write_ExpectWithArrayAndReturn(&cmd_fix.dummy_handle, expected_write, WRITE_SIZE, EXPECTED_DATA_LEN, true, ESP_OK); i2c_master_stop_ExpectAndReturn(&cmd_fix.dummy_handle, ESP_OK); - i2c_master_cmd_begin_ExpectAndReturn(0, &cmd_fix.dummy_handle, 1000 / portTICK_PERIOD_MS, ESP_OK); + i2c_master_cmd_begin_ExpectAndReturn(I2C_NUM_0, &cmd_fix.dummy_handle, 1000 / portTICK_PERIOD_MS, ESP_OK); I2CMaster master(I2CNumber::I2C0(), SCL_GPIO(1), SDA_GPIO(2), Frequency(400000)); std::vector WRITE_BYTES = {0xAB, 0xBA}; @@ -332,7 +332,7 @@ TEST_CASE("I2CMaster synchronous read") // will actually read the data but for the tests it is enough for now i2c_master_read_ReturnArrayThruPtr_data(READ_DATA, READ_SIZE); i2c_master_stop_ExpectAndReturn(&cmd_fix.dummy_handle, ESP_OK); - i2c_master_cmd_begin_ExpectAndReturn(0, &cmd_fix.dummy_handle, 1000 / portTICK_PERIOD_MS, ESP_OK); + i2c_master_cmd_begin_ExpectAndReturn(I2C_NUM_0, &cmd_fix.dummy_handle, 1000 / portTICK_PERIOD_MS, ESP_OK); I2CMaster master(I2CNumber::I2C0(), SCL_GPIO(1), SDA_GPIO(2), Frequency(400000)); std::vector result = master.sync_read(I2CAddress(0x47), READ_SIZE); @@ -365,7 +365,7 @@ TEST_CASE("I2CMaster syncronous transfer (read and write)") // will actually read the data but for the tests it is enough for now i2c_master_read_ReturnArrayThruPtr_data(READ_DATA, READ_SIZE); i2c_master_stop_ExpectAndReturn(&cmd_fix.dummy_handle, ESP_OK); - i2c_master_cmd_begin_ExpectAndReturn(0, &cmd_fix.dummy_handle, 1000 / portTICK_PERIOD_MS, ESP_OK); + i2c_master_cmd_begin_ExpectAndReturn(I2C_NUM_0, &cmd_fix.dummy_handle, 1000 / portTICK_PERIOD_MS, ESP_OK); I2CMaster master(I2CNumber::I2C0(), SCL_GPIO(1), SDA_GPIO(2), Frequency(400000)); vector read_result = master.sync_transfer(I2CAddress(0x47), {0x47, 0x48, 0x49}, READ_SIZE); diff --git a/examples/cxx/experimental/experimental_cpp_component/host_test/spi/CMakeLists.txt b/examples/cxx/experimental/experimental_cpp_component/host_test/spi/CMakeLists.txt index e330769f08..b0d4046a8d 100644 --- a/examples/cxx/experimental/experimental_cpp_component/host_test/spi/CMakeLists.txt +++ b/examples/cxx/experimental/experimental_cpp_component/host_test/spi/CMakeLists.txt @@ -3,8 +3,6 @@ cmake_minimum_required(VERSION 3.16) include($ENV{IDF_PATH}/tools/cmake/project.cmake) set(COMPONENTS main) -idf_build_set_property(COMPILE_DEFINITIONS "-DNO_DEBUG_STORAGE" APPEND) - # Overriding components which should be mocked list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/mocks/driver/") list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/mocks/freertos/") diff --git a/examples/cxx/experimental/experimental_cpp_component/i2c_cxx.cpp b/examples/cxx/experimental/experimental_cpp_component/i2c_cxx.cpp index e549aef15a..fab4ed85b4 100644 --- a/examples/cxx/experimental/experimental_cpp_component/i2c_cxx.cpp +++ b/examples/cxx/experimental/experimental_cpp_component/i2c_cxx.cpp @@ -15,6 +15,20 @@ namespace idf { #define I2C_CHECK_THROW(err) CHECK_THROW_SPECIFIC((err), I2CException) +/** + * I2C bus are defined in the header files, let's check that the values are correct + */ +#if SOC_I2C_NUM >= 2 +static_assert(I2C_NUM_1 == 1, "I2C_NUM_1 must be equal to 1"); +#endif // SOC_I2C_NUM >= 2 +static_assert(I2C_NUM_MAX == SOC_I2C_NUM, "I2C_NUM_MAX must be equal to SOC_I2C_NUM"); + +namespace { +i2c_port_t i2c_num_to_driver_type(I2CNumber num) { + return static_cast(num.get_num()); +} +} + esp_err_t check_i2c_num(uint32_t i2c_num) noexcept { if (i2c_num >= I2C_NUM_MAX) { @@ -96,7 +110,7 @@ void I2CCommandLink::stop() void I2CCommandLink::execute_transfer(I2CNumber i2c_num, chrono::milliseconds driver_timeout) { - esp_err_t err = i2c_master_cmd_begin(i2c_num.get_num(), handle, driver_timeout.count() / portTICK_PERIOD_MS); + esp_err_t err = i2c_master_cmd_begin(i2c_num_to_driver_type(i2c_num), handle, driver_timeout.count() / portTICK_PERIOD_MS); if (err != ESP_OK) { throw I2CTransferException(err); } @@ -121,13 +135,13 @@ I2CMaster::I2CMaster(I2CNumber i2c_number, conf.sda_io_num = sda_gpio.get_num(); conf.sda_pullup_en = sda_pullup; conf.master.clk_speed = clock_speed.get_value(); - I2C_CHECK_THROW(i2c_param_config(i2c_num.get_value(), &conf)); - I2C_CHECK_THROW(i2c_driver_install(i2c_num.get_value(), conf.mode, 0, 0, 0)); + I2C_CHECK_THROW(i2c_param_config(i2c_num_to_driver_type(i2c_num), &conf)); + I2C_CHECK_THROW(i2c_driver_install(i2c_num_to_driver_type(i2c_num), conf.mode, 0, 0, 0)); } I2CMaster::~I2CMaster() { - i2c_driver_delete(i2c_num.get_value()); + i2c_driver_delete(i2c_num_to_driver_type(i2c_num)); } void I2CMaster::sync_write(I2CAddress i2c_addr, const vector &data) @@ -174,23 +188,23 @@ I2CSlave::I2CSlave(I2CNumber i2c_number, conf.sda_pullup_en = sda_pullup; conf.slave.addr_10bit_en = 0; conf.slave.slave_addr = slave_addr.get_addr(); - I2C_CHECK_THROW(i2c_param_config(i2c_num.get_value(), &conf)); - I2C_CHECK_THROW(i2c_driver_install(i2c_num.get_value(), conf.mode, rx_buf_len, tx_buf_len, 0)); + I2C_CHECK_THROW(i2c_param_config(i2c_num_to_driver_type(i2c_num), &conf)); + I2C_CHECK_THROW(i2c_driver_install(i2c_num_to_driver_type(i2c_num), conf.mode, rx_buf_len, tx_buf_len, 0)); } I2CSlave::~I2CSlave() { - i2c_driver_delete(i2c_num.get_value()); + i2c_driver_delete(i2c_num_to_driver_type(i2c_num)); } int I2CSlave::write_raw(const uint8_t *data, size_t data_len, chrono::milliseconds timeout) { - return i2c_slave_write_buffer(i2c_num.get_value(), data, data_len, (TickType_t) timeout.count() / portTICK_PERIOD_MS); + return i2c_slave_write_buffer(i2c_num_to_driver_type(i2c_num), data, data_len, (TickType_t) timeout.count() / portTICK_PERIOD_MS); } int I2CSlave::read_raw(uint8_t *buffer, size_t buffer_len, chrono::milliseconds timeout) { - return i2c_slave_read_buffer(i2c_num.get_value(), buffer, buffer_len, (TickType_t) timeout.count() / portTICK_PERIOD_MS); + return i2c_slave_read_buffer(i2c_num_to_driver_type(i2c_num), buffer, buffer_len, (TickType_t) timeout.count() / portTICK_PERIOD_MS); } #endif // CONFIG_SOC_I2C_SUPPORT_SLAVE diff --git a/examples/ethernet/.build-test-rules.yml b/examples/ethernet/.build-test-rules.yml index 8125667558..71c591c339 100644 --- a/examples/ethernet/.build-test-rules.yml +++ b/examples/ethernet/.build-test-rules.yml @@ -1,17 +1,7 @@ # Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps -examples/ethernet: - disable: - - if: IDF_TARGET == "esp32c2" - temporary: true - reason: target esp32c2 is not supported yet - examples/ethernet/iperf: - disable: - - if: IDF_TARGET == "esp32c2" - temporary: true - reason: target esp32c2 is not supported yet disable_test: - - if: IDF_TARGET in ["esp32c3", "esp32s2", "esp32s3"] + - if: IDF_TARGET in ["esp32c3", "esp32c2", "esp32s2", "esp32s3"] temporary: true reason: lack of runners diff --git a/examples/ethernet/README.md b/examples/ethernet/README.md index a36b1f255b..46aa134729 100644 --- a/examples/ethernet/README.md +++ b/examples/ethernet/README.md @@ -56,7 +56,7 @@ Please consult Espressif Technical reference manual along with datasheet for spe ## Common Configurations -1. In the `Example Configuration` menu: +1. In the `Example Ethernet Configuration` menu: * Choose the kind of Ethernet. * If `Internal EMAC` is selected: * Choose PHY device under `Ethernet PHY Device`, by default, the **ESP32-Ethernet-Kit** has an `IP101` on board. diff --git a/examples/ethernet/basic/README.md b/examples/ethernet/basic/README.md index b59744f434..ab7070419d 100644 --- a/examples/ethernet/basic/README.md +++ b/examples/ethernet/basic/README.md @@ -1,16 +1,17 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | # Ethernet Example (See the README.md file in the upper level 'examples' directory for more information about examples.) ## Overview -This example demonstrates basic usage of `Ethernet driver` together with `esp_netif`. The work flow of the example could be as follows: +This example demonstrates basic usage of `Ethernet driver` together with `esp_netif`. Initialization of the `Ethernet driver` is wrapped in separate [sub-component](./components/ethernet_init/ethernet_init.c) of this project to clearly distinguish between the driver's and `esp_netif` initializations. The work flow of the example could be as follows: 1. Install Ethernet driver -2. Send DHCP requests and wait for a DHCP lease -3. If get IP address successfully, then you will be able to ping the device +2. Attach the driver to `esp_netif` +3. Send DHCP requests and wait for a DHCP lease +4. If get IP address successfully, then you will be able to ping the device If you have a new Ethernet application to go (for example, connect to IoT cloud via Ethernet), try this as a basic template, then add your own code. diff --git a/examples/ethernet/basic/components/ethernet_init/CMakeLists.txt b/examples/ethernet/basic/components/ethernet_init/CMakeLists.txt new file mode 100644 index 0000000000..382893ed87 --- /dev/null +++ b/examples/ethernet/basic/components/ethernet_init/CMakeLists.txt @@ -0,0 +1,3 @@ +idf_component_register(SRCS "ethernet_init.c" + PRIV_REQUIRES driver esp_eth + INCLUDE_DIRS ".") diff --git a/examples/network/bridge/main/Kconfig.projbuild b/examples/ethernet/basic/components/ethernet_init/Kconfig.projbuild similarity index 98% rename from examples/network/bridge/main/Kconfig.projbuild rename to examples/ethernet/basic/components/ethernet_init/Kconfig.projbuild index 2f584ba5d3..ce79cb4e23 100644 --- a/examples/network/bridge/main/Kconfig.projbuild +++ b/examples/ethernet/basic/components/ethernet_init/Kconfig.projbuild @@ -1,10 +1,11 @@ -menu "Example Configuration" +menu "Example Ethernet Configuration" orsource "$IDF_PATH/examples/common_components/env_caps/$IDF_TARGET/Kconfig.env_caps" config EXAMPLE_USE_INTERNAL_ETHERNET - depends on IDF_TARGET_ESP32 + depends on SOC_EMAC_SUPPORTED select ETH_USE_ESP32_EMAC + default y bool "Internal EMAC" help Use internal Ethernet MAC controller. @@ -89,7 +90,7 @@ menu "Example Configuration" config EXAMPLE_USE_SPI_ETHERNET bool "SPI Ethernet" - default y + default n select ETH_USE_SPI_ETHERNET help Use external SPI-Ethernet module(s). @@ -192,7 +193,7 @@ menu "Example Configuration" config EXAMPLE_ETH_SPI_INT0_GPIO int "Interrupt GPIO number SPI Ethernet module #1" range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX - default 4 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C3 + default 4 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 default 4 if IDF_TARGET_ESP32C2 help Set the GPIO number used by the first SPI Ethernet module interrupt line. diff --git a/examples/ethernet/basic/components/ethernet_init/ethernet_init.c b/examples/ethernet/basic/components/ethernet_init/ethernet_init.c new file mode 100644 index 0000000000..238fa1acdc --- /dev/null +++ b/examples/ethernet/basic/components/ethernet_init/ethernet_init.c @@ -0,0 +1,289 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include "ethernet_init.h" +#include "esp_log.h" +#include "esp_check.h" +#include "esp_mac.h" +#include "driver/gpio.h" +#include "sdkconfig.h" +#if CONFIG_ETH_USE_SPI_ETHERNET +#include "driver/spi_master.h" +#endif // CONFIG_ETH_USE_SPI_ETHERNET + +static const char *TAG = "example_eth_init"; + +#if CONFIG_EXAMPLE_SPI_ETHERNETS_NUM +#define SPI_ETHERNETS_NUM CONFIG_EXAMPLE_SPI_ETHERNETS_NUM +#else +#define SPI_ETHERNETS_NUM 0 +#endif + +#if CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET +#define INTERNAL_ETHERNETS_NUM 1 +#else +#define INTERNAL_ETHERNETS_NUM 0 +#endif + +#define INIT_SPI_ETH_MODULE_CONFIG(eth_module_config, num) \ + do { \ + eth_module_config[num].spi_cs_gpio = CONFIG_EXAMPLE_ETH_SPI_CS ##num## _GPIO; \ + eth_module_config[num].int_gpio = CONFIG_EXAMPLE_ETH_SPI_INT ##num## _GPIO; \ + eth_module_config[num].phy_reset_gpio = CONFIG_EXAMPLE_ETH_SPI_PHY_RST ##num## _GPIO; \ + eth_module_config[num].phy_addr = CONFIG_EXAMPLE_ETH_SPI_PHY_ADDR ##num; \ + } while(0) + +typedef struct { + uint8_t spi_cs_gpio; + uint8_t int_gpio; + int8_t phy_reset_gpio; + uint8_t phy_addr; + uint8_t *mac_addr; +}spi_eth_module_config_t; + +#if CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET +/** + * @brief Internal ESP32 Ethernet initialization + * + * @param[out] mac_out optionally returns Ethernet MAC object + * @param[out] phy_out optionally returns Ethernet PHY object + * @return + * - esp_eth_handle_t if init succeeded + * - NULL if init failed + */ +static esp_eth_handle_t eth_init_internal(esp_eth_mac_t **mac_out, esp_eth_phy_t **phy_out) +{ + esp_eth_handle_t ret = NULL; + + // Init common MAC and PHY configs to default + eth_mac_config_t mac_config = ETH_MAC_DEFAULT_CONFIG(); + eth_phy_config_t phy_config = ETH_PHY_DEFAULT_CONFIG(); + + // Update PHY config based on board specific configuration + phy_config.phy_addr = CONFIG_EXAMPLE_ETH_PHY_ADDR; + phy_config.reset_gpio_num = CONFIG_EXAMPLE_ETH_PHY_RST_GPIO; + // Init vendor specific MAC config to default + eth_esp32_emac_config_t esp32_emac_config = ETH_ESP32_EMAC_DEFAULT_CONFIG(); + // Update vendor specific MAC config based on board configuration + esp32_emac_config.smi_mdc_gpio_num = CONFIG_EXAMPLE_ETH_MDC_GPIO; + esp32_emac_config.smi_mdio_gpio_num = CONFIG_EXAMPLE_ETH_MDIO_GPIO; + // Create new ESP32 Ethernet MAC instance + esp_eth_mac_t *mac = esp_eth_mac_new_esp32(&esp32_emac_config, &mac_config); + // Create new PHY instance based on board configuration +#if CONFIG_EXAMPLE_ETH_PHY_IP101 + esp_eth_phy_t *phy = esp_eth_phy_new_ip101(&phy_config); +#elif CONFIG_EXAMPLE_ETH_PHY_RTL8201 + esp_eth_phy_t *phy = esp_eth_phy_new_rtl8201(&phy_config); +#elif CONFIG_EXAMPLE_ETH_PHY_LAN87XX + esp_eth_phy_t *phy = esp_eth_phy_new_lan87xx(&phy_config); +#elif CONFIG_EXAMPLE_ETH_PHY_DP83848 + esp_eth_phy_t *phy = esp_eth_phy_new_dp83848(&phy_config); +#elif CONFIG_EXAMPLE_ETH_PHY_KSZ80XX + esp_eth_phy_t *phy = esp_eth_phy_new_ksz80xx(&phy_config); +#endif + // Init Ethernet driver to default and install it + esp_eth_handle_t eth_handle = NULL; + esp_eth_config_t config = ETH_DEFAULT_CONFIG(mac, phy); + ESP_GOTO_ON_FALSE(esp_eth_driver_install(&config, ð_handle) == ESP_OK, NULL, + err, TAG, "Ethernet driver install failed"); + + if (mac_out != NULL) { + *mac_out = mac; + } + if (phy_out != NULL) { + *phy_out = phy; + } + return eth_handle; +err: + if (eth_handle != NULL) { + esp_eth_driver_uninstall(eth_handle); + } + if (mac != NULL) { + mac->del(mac); + } + if (phy != NULL) { + phy->del(phy); + } + return ret; +} +#endif // CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET + +#if CONFIG_EXAMPLE_USE_SPI_ETHERNET +/** + * @brief SPI bus initialization (to be used by Ethernet SPI modules) + * + * @return + * - ESP_OK on success + */ +static esp_err_t spi_bus_init(void) +{ + esp_err_t ret = ESP_OK; + + // Install GPIO ISR handler to be able to service SPI Eth modules interrupts + ret = gpio_install_isr_service(0); + if (ret != ESP_OK) { + if (ret == ESP_ERR_INVALID_STATE) { + ESP_LOGW(TAG, "GPIO ISR handler has been already installed"); + ret = ESP_OK; // ISR handler has been already installed so no issues + } else { + ESP_LOGE(TAG, "GPIO ISR handler install failed"); + goto err; + } + } + + // Init SPI bus + spi_bus_config_t buscfg = { + .miso_io_num = CONFIG_EXAMPLE_ETH_SPI_MISO_GPIO, + .mosi_io_num = CONFIG_EXAMPLE_ETH_SPI_MOSI_GPIO, + .sclk_io_num = CONFIG_EXAMPLE_ETH_SPI_SCLK_GPIO, + .quadwp_io_num = -1, + .quadhd_io_num = -1, + }; + ESP_GOTO_ON_ERROR(spi_bus_initialize(CONFIG_EXAMPLE_ETH_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO), + err, TAG, "SPI host #%d init failed", CONFIG_EXAMPLE_ETH_SPI_HOST); + +err: + return ret; +} + +/** + * @brief Ethernet SPI modules initialization + * + * @param[in] spi_eth_module_config specific SPI Ethernet module configuration + * @param[out] mac_out optionally returns Ethernet MAC object + * @param[out] phy_out optionally returns Ethernet PHY object + * @return + * - esp_eth_handle_t if init succeeded + * - NULL if init failed + */ +static esp_eth_handle_t eth_init_spi(spi_eth_module_config_t *spi_eth_module_config, esp_eth_mac_t **mac_out, esp_eth_phy_t **phy_out) +{ + esp_eth_handle_t ret = NULL; + + // Init common MAC and PHY configs to default + eth_mac_config_t mac_config = ETH_MAC_DEFAULT_CONFIG(); + eth_phy_config_t phy_config = ETH_PHY_DEFAULT_CONFIG(); + + // Update PHY config based on board specific configuration + phy_config.phy_addr = spi_eth_module_config->phy_addr; + phy_config.reset_gpio_num = spi_eth_module_config->phy_reset_gpio; + + // Configure SPI interface for specific SPI module + spi_device_interface_config_t spi_devcfg = { + .mode = 0, + .clock_speed_hz = CONFIG_EXAMPLE_ETH_SPI_CLOCK_MHZ * 1000 * 1000, + .queue_size = 20, + .spics_io_num = spi_eth_module_config->spi_cs_gpio + }; + // Init vendor specific MAC config to default, and create new SPI Ethernet MAC instance + // and new PHY instance based on board configuration +#if CONFIG_EXAMPLE_USE_KSZ8851SNL + eth_ksz8851snl_config_t ksz8851snl_config = ETH_KSZ8851SNL_DEFAULT_CONFIG(CONFIG_EXAMPLE_ETH_SPI_HOST, &spi_devcfg); + ksz8851snl_config.int_gpio_num = spi_eth_module_config->int_gpio; + esp_eth_mac_t *mac = esp_eth_mac_new_ksz8851snl(&ksz8851snl_config, &mac_config); + esp_eth_phy_t *phy = esp_eth_phy_new_ksz8851snl(&phy_config); +#elif CONFIG_EXAMPLE_USE_DM9051 + eth_dm9051_config_t dm9051_config = ETH_DM9051_DEFAULT_CONFIG(CONFIG_EXAMPLE_ETH_SPI_HOST, &spi_devcfg); + dm9051_config.int_gpio_num = spi_eth_module_config->int_gpio; + esp_eth_mac_t *mac = esp_eth_mac_new_dm9051(&dm9051_config, &mac_config); + esp_eth_phy_t *phy = esp_eth_phy_new_dm9051(&phy_config); +#elif CONFIG_EXAMPLE_USE_W5500 + eth_w5500_config_t w5500_config = ETH_W5500_DEFAULT_CONFIG(CONFIG_EXAMPLE_ETH_SPI_HOST, &spi_devcfg); + w5500_config.int_gpio_num = spi_eth_module_config->int_gpio; + esp_eth_mac_t *mac = esp_eth_mac_new_w5500(&w5500_config, &mac_config); + esp_eth_phy_t *phy = esp_eth_phy_new_w5500(&phy_config); +#endif //CONFIG_EXAMPLE_USE_W5500 + // Init Ethernet driver to default and install it + esp_eth_handle_t eth_handle = NULL; + esp_eth_config_t eth_config_spi = ETH_DEFAULT_CONFIG(mac, phy); + ESP_GOTO_ON_FALSE(esp_eth_driver_install(ð_config_spi, ð_handle) == ESP_OK, NULL, err, TAG, "SPI Ethernet driver install failed"); + + // The SPI Ethernet module might not have a burned factory MAC address, we can set it manually. + if (spi_eth_module_config->mac_addr != NULL) { + ESP_GOTO_ON_FALSE(esp_eth_ioctl(eth_handle, ETH_CMD_S_MAC_ADDR, spi_eth_module_config->mac_addr) == ESP_OK, + NULL, err, TAG, "SPI Ethernet MAC address config failed"); + } + + if (mac_out != NULL) { + *mac_out = mac; + } + if (phy_out != NULL) { + *phy_out = phy; + } + return eth_handle; +err: + if (eth_handle != NULL) { + esp_eth_driver_uninstall(eth_handle); + } + if (mac != NULL) { + mac->del(mac); + } + if (phy != NULL) { + phy->del(phy); + } + return ret; +} +#endif // CONFIG_EXAMPLE_USE_SPI_ETHERNET + +esp_err_t example_eth_init(esp_eth_handle_t *eth_handles_out[], uint8_t *eth_cnt_out) +{ + esp_err_t ret = ESP_OK; + esp_eth_handle_t *eth_handles = NULL; + uint8_t eth_cnt = 0; + +#if CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET || CONFIG_EXAMPLE_USE_SPI_ETHERNET + ESP_GOTO_ON_FALSE(eth_handles_out != NULL && eth_cnt_out != NULL, ESP_ERR_INVALID_ARG, + err, TAG, "invalid arguments: initialized handles array or number of interfaces"); + eth_handles = calloc(SPI_ETHERNETS_NUM + INTERNAL_ETHERNETS_NUM, sizeof(esp_eth_handle_t)); + ESP_GOTO_ON_FALSE(eth_handles != NULL, ESP_ERR_NO_MEM, err, TAG, "no memory"); + +#if CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET + eth_handles[eth_cnt] = eth_init_internal(NULL, NULL); + ESP_GOTO_ON_FALSE(eth_handles[eth_cnt], ESP_FAIL, err, TAG, "internal Ethernet init failed"); + eth_cnt++; +#endif //CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET + +#if CONFIG_EXAMPLE_USE_SPI_ETHERNET + ESP_GOTO_ON_ERROR(spi_bus_init(), err, TAG, "SPI bus init failed"); + // Init specific SPI Ethernet module configuration from Kconfig (CS GPIO, Interrupt GPIO, etc.) + spi_eth_module_config_t spi_eth_module_config[CONFIG_EXAMPLE_SPI_ETHERNETS_NUM] = { 0 }; + INIT_SPI_ETH_MODULE_CONFIG(spi_eth_module_config, 0); + // The SPI Ethernet module(s) might not have a burned factory MAC address, hence use manually configured address(es). + // In this example, Locally Administered MAC address derived from ESP32x base MAC address is used. + // Note that Locally Administered OUI range should be used only when testing on a LAN under your control! + uint8_t base_mac_addr[ETH_ADDR_LEN]; + ESP_GOTO_ON_ERROR(esp_efuse_mac_get_default(base_mac_addr), err, TAG, "get EFUSE MAC failed"); + u_int8_t local_mac_1[ETH_ADDR_LEN]; + esp_derive_local_mac(local_mac_1, base_mac_addr); + spi_eth_module_config[0].mac_addr = local_mac_1; +#if CONFIG_EXAMPLE_SPI_ETHERNETS_NUM > 1 + INIT_SPI_ETH_MODULE_CONFIG(spi_eth_module_config, 1); + u_int8_t local_mac_2[ETH_ADDR_LEN]; + base_mac_addr[ETH_ADDR_LEN - 1] += 1; + esp_derive_local_mac(local_mac_2, base_mac_addr); + spi_eth_module_config[1].mac_addr = local_mac_2; +#endif +#if CONFIG_EXAMPLE_SPI_ETHERNETS_NUM > 2 +#error Maximum number of supported SPI Ethernet devices is currently limited to 2 by this example. +#endif + for (int i = 0; i < CONFIG_EXAMPLE_SPI_ETHERNETS_NUM; i++) { + eth_handles[eth_cnt] = eth_init_spi(&spi_eth_module_config[i], NULL, NULL); + ESP_GOTO_ON_FALSE(eth_handles[eth_cnt], ESP_FAIL, err, TAG, "SPI Ethernet init failed"); + eth_cnt++; + } +#endif // CONFIG_ETH_USE_SPI_ETHERNET +#else + ESP_LOGD(TAG, "no Ethernet device selected to init"); +#endif // CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET || CONFIG_EXAMPLE_USE_SPI_ETHERNET + *eth_handles_out = eth_handles; + *eth_cnt_out = eth_cnt; + + return ret; +#if CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET || CONFIG_EXAMPLE_USE_SPI_ETHERNET +err: + free(eth_handles); + return ret; +#endif +} diff --git a/examples/ethernet/basic/components/ethernet_init/ethernet_init.h b/examples/ethernet/basic/components/ethernet_init/ethernet_init.h new file mode 100644 index 0000000000..8fa5df6106 --- /dev/null +++ b/examples/ethernet/basic/components/ethernet_init/ethernet_init.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#pragma once + +#include "esp_eth_driver.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Initialize Ethernet driver based on Espressif IoT Development Framework Configuration + * + * @param[out] eth_handles_out array of initialized Ethernet driver handles + * @param[out] eth_cnt_out number of initialized Ethernets + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG when passed invalid pointers + * - ESP_ERR_NO_MEM when there is no memory to allocate for Ethernet driver handles array + * - ESP_FAIL on any other failure + */ +esp_err_t example_eth_init(esp_eth_handle_t *eth_handles_out[], uint8_t *eth_cnt_out); + +#ifdef __cplusplus +} +#endif diff --git a/examples/ethernet/basic/main/Kconfig.projbuild b/examples/ethernet/basic/main/Kconfig.projbuild deleted file mode 100644 index b0c5d1af08..0000000000 --- a/examples/ethernet/basic/main/Kconfig.projbuild +++ /dev/null @@ -1,239 +0,0 @@ -menu "Example Configuration" - - orsource "$IDF_PATH/examples/common_components/env_caps/$IDF_TARGET/Kconfig.env_caps" - - config EXAMPLE_USE_INTERNAL_ETHERNET - depends on IDF_TARGET_ESP32 - select ETH_USE_ESP32_EMAC - bool "Internal EMAC" - help - Use internal Ethernet MAC controller. - - if EXAMPLE_USE_INTERNAL_ETHERNET - choice EXAMPLE_ETH_PHY_MODEL - prompt "Ethernet PHY Device" - default EXAMPLE_ETH_PHY_IP101 - help - Select the Ethernet PHY device to use in the example. - - config EXAMPLE_ETH_PHY_IP101 - bool "IP101" - help - IP101 is a single port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver. - Goto http://www.icplus.com.tw/pp-IP101G.html for more information about it. - - config EXAMPLE_ETH_PHY_RTL8201 - bool "RTL8201/SR8201" - help - RTL8201F/SR8201F is a single port 10/100Mb Ethernet Transceiver with auto MDIX. - Goto http://www.corechip-sz.com/productsview.asp?id=22 for more information about it. - - config EXAMPLE_ETH_PHY_LAN87XX - bool "LAN87xx" - help - Below chips are supported: - LAN8710A is a small footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and - flexPWR® Technology. - LAN8720A is a small footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support. - LAN8740A/LAN8741A is a small footprint MII/RMII 10/100 Energy Efficient Ethernet Transceiver - with HP Auto-MDIX and flexPWR® Technology. - LAN8742A is a small footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and - flexPWR® Technology. - Goto https://www.microchip.com for more information about them. - - config EXAMPLE_ETH_PHY_DP83848 - bool "DP83848" - help - DP83848 is a single port 10/100Mb/s Ethernet Physical Layer Transceiver. - Goto http://www.ti.com/product/DP83848J for more information about it. - - config EXAMPLE_ETH_PHY_KSZ80XX - bool "KSZ80xx" - help - With the KSZ80xx series, Microchip offers single-chip 10BASE-T/100BASE-TX - Ethernet Physical Layer Tranceivers (PHY). - The following chips are supported: KSZ8001, KSZ8021, KSZ8031, KSZ8041, - KSZ8051, KSZ8061, KSZ8081, KSZ8091 - Goto https://www.microchip.com for more information about them. - endchoice # EXAMPLE_ETH_PHY_MODEL - - config EXAMPLE_ETH_MDC_GPIO - int "SMI MDC GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 23 - help - Set the GPIO number used by SMI MDC. - - config EXAMPLE_ETH_MDIO_GPIO - int "SMI MDIO GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 18 - help - Set the GPIO number used by SMI MDIO. - - config EXAMPLE_ETH_PHY_RST_GPIO - int "PHY Reset GPIO number" - range -1 ENV_GPIO_OUT_RANGE_MAX - default 5 - help - Set the GPIO number used to reset PHY chip. - Set to -1 to disable PHY chip hardware reset. - - config EXAMPLE_ETH_PHY_ADDR - int "PHY Address" - range 0 31 - default 1 - help - Set PHY address according your board schematic. - endif # EXAMPLE_USE_INTERNAL_ETHERNET - - config EXAMPLE_USE_SPI_ETHERNET - bool "SPI Ethernet" - default y - select ETH_USE_SPI_ETHERNET - help - Use external SPI-Ethernet module(s). - - if EXAMPLE_USE_SPI_ETHERNET - config EXAMPLE_SPI_ETHERNETS_NUM - int "Number of SPI Ethernet modules to use at a time" - range 1 2 - default 1 - help - Set the number of SPI Ethernet modules you want to use at a time. Multiple SPI modules can be connected - to one SPI interface and can be separately accessed based on state of associated Chip Select (CS). - - choice EXAMPLE_ETHERNET_TYPE_SPI - prompt "Ethernet SPI" - default EXAMPLE_USE_W5500 - help - Select which kind of Ethernet will be used in the example. - - config EXAMPLE_USE_DM9051 - bool "DM9051 Module" - select ETH_SPI_ETHERNET_DM9051 - help - Select external SPI-Ethernet module (DM9051). - - config EXAMPLE_USE_KSZ8851SNL - bool "KSZ8851SNL Module" - select ETH_SPI_ETHERNET_KSZ8851SNL - help - Select external SPI-Ethernet module (KSZ8851SNL). - - config EXAMPLE_USE_W5500 - bool "W5500 Module" - select ETH_SPI_ETHERNET_W5500 - help - Select external SPI-Ethernet module (W5500). - endchoice - - config EXAMPLE_ETH_SPI_HOST - int "SPI Host Number" - range 0 2 - default 1 - help - Set the SPI host used to communicate with the SPI Ethernet Controller. - - config EXAMPLE_ETH_SPI_SCLK_GPIO - int "SPI SCLK GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 14 if IDF_TARGET_ESP32 - default 12 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 - default 6 if IDF_TARGET_ESP32C3 - help - Set the GPIO number used by SPI SCLK. - - config EXAMPLE_ETH_SPI_MOSI_GPIO - int "SPI MOSI GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 13 if IDF_TARGET_ESP32 - default 11 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 - default 7 if IDF_TARGET_ESP32C3 - help - Set the GPIO number used by SPI MOSI. - - config EXAMPLE_ETH_SPI_MISO_GPIO - int "SPI MISO GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX - default 12 if IDF_TARGET_ESP32 - default 13 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 - default 2 if IDF_TARGET_ESP32C3 - help - Set the GPIO number used by SPI MISO. - - config EXAMPLE_ETH_SPI_CLOCK_MHZ - int "SPI clock speed (MHz)" - range 5 80 - default 12 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32C3 - default 36 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 - help - Set the clock speed (MHz) of SPI interface. - - config EXAMPLE_ETH_SPI_CS0_GPIO - int "SPI CS0 GPIO number for SPI Ethernet module #1" - range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 15 if IDF_TARGET_ESP32 - default 10 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 - help - Set the GPIO number used by SPI CS0, i.e. Chip Select associated with the first SPI Eth module). - - config EXAMPLE_ETH_SPI_CS1_GPIO - depends on EXAMPLE_SPI_ETHERNETS_NUM > 1 - int "SPI CS1 GPIO number for SPI Ethernet module #2" - range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 32 if IDF_TARGET_ESP32 - default 7 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 - default 8 if IDF_TARGET_ESP32C3 - help - Set the GPIO number used by SPI CS1, i.e. Chip Select associated with the second SPI Eth module. - - config EXAMPLE_ETH_SPI_INT0_GPIO - int "Interrupt GPIO number SPI Ethernet module #1" - range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX - default 4 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 - help - Set the GPIO number used by the first SPI Ethernet module interrupt line. - - config EXAMPLE_ETH_SPI_INT1_GPIO - depends on EXAMPLE_SPI_ETHERNETS_NUM > 1 - int "Interrupt GPIO number SPI Ethernet module #2" - range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX - default 33 if IDF_TARGET_ESP32 - default 5 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 - help - Set the GPIO number used by the second SPI Ethernet module interrupt line. - - config EXAMPLE_ETH_SPI_PHY_RST0_GPIO - int "PHY Reset GPIO number of SPI Ethernet Module #1" - range -1 ENV_GPIO_OUT_RANGE_MAX - default -1 - help - Set the GPIO number used to reset PHY chip on the first SPI Ethernet module. - Set to -1 to disable PHY chip hardware reset. - - config EXAMPLE_ETH_SPI_PHY_RST1_GPIO - depends on EXAMPLE_SPI_ETHERNETS_NUM > 1 - int "PHY Reset GPIO number of SPI Ethernet Module #2" - range -1 ENV_GPIO_OUT_RANGE_MAX - default -1 - help - Set the GPIO number used to reset PHY chip on the second SPI Ethernet module. - Set to -1 to disable PHY chip hardware reset. - - config EXAMPLE_ETH_SPI_PHY_ADDR0 - int "PHY Address of SPI Ethernet Module #1" - range 0 31 - default 1 - help - Set the first SPI Ethernet module PHY address according your board schematic. - - config EXAMPLE_ETH_SPI_PHY_ADDR1 - depends on EXAMPLE_SPI_ETHERNETS_NUM > 1 - int "PHY Address of SPI Ethernet Module #2" - range 0 31 - default 1 - help - Set the second SPI Ethernet module PHY address according your board schematic. - endif # EXAMPLE_USE_SPI_ETHERNET -endmenu diff --git a/examples/ethernet/basic/main/ethernet_example_main.c b/examples/ethernet/basic/main/ethernet_example_main.c index 1a21b98b2e..b3033e3329 100644 --- a/examples/ethernet/basic/main/ethernet_example_main.c +++ b/examples/ethernet/basic/main/ethernet_example_main.c @@ -14,31 +14,11 @@ #include "esp_eth.h" #include "esp_event.h" #include "esp_log.h" -#include "driver/gpio.h" +#include "ethernet_init.h" #include "sdkconfig.h" -#if CONFIG_ETH_USE_SPI_ETHERNET -#include "driver/spi_master.h" -#endif // CONFIG_ETH_USE_SPI_ETHERNET static const char *TAG = "eth_example"; -#if CONFIG_EXAMPLE_USE_SPI_ETHERNET -#define INIT_SPI_ETH_MODULE_CONFIG(eth_module_config, num) \ - do { \ - eth_module_config[num].spi_cs_gpio = CONFIG_EXAMPLE_ETH_SPI_CS ##num## _GPIO; \ - eth_module_config[num].int_gpio = CONFIG_EXAMPLE_ETH_SPI_INT ##num## _GPIO; \ - eth_module_config[num].phy_reset_gpio = CONFIG_EXAMPLE_ETH_SPI_PHY_RST ##num## _GPIO; \ - eth_module_config[num].phy_addr = CONFIG_EXAMPLE_ETH_SPI_PHY_ADDR ##num; \ - } while(0) - -typedef struct { - uint8_t spi_cs_gpio; - uint8_t int_gpio; - int8_t phy_reset_gpio; - uint8_t phy_addr; -}spi_eth_module_config_t; -#endif - /** Event handler for Ethernet events */ static void eth_event_handler(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) @@ -85,146 +65,55 @@ static void got_ip_event_handler(void *arg, esp_event_base_t event_base, void app_main(void) { - // Initialize TCP/IP network interface (should be called only once in application) + // Initialize Ethernet driver + uint8_t eth_port_cnt = 0; + esp_eth_handle_t *eth_handles; + ESP_ERROR_CHECK(example_eth_init(ð_handles, ð_port_cnt)); + + // Initialize TCP/IP network interface aka the esp-netif (should be called only once in application) ESP_ERROR_CHECK(esp_netif_init()); // Create default event loop that running in background ESP_ERROR_CHECK(esp_event_loop_create_default()); -#if CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET - // Create new default instance of esp-netif for Ethernet - esp_netif_config_t cfg = ESP_NETIF_DEFAULT_ETH(); - esp_netif_t *eth_netif = esp_netif_new(&cfg); + // Create instance(s) of esp-netif for Ethernet(s) + if (eth_port_cnt == 1) { + // Use ESP_NETIF_DEFAULT_ETH when just one Ethernet interface is used and you don't need to modify + // default esp-netif configuration parameters. + esp_netif_config_t cfg = ESP_NETIF_DEFAULT_ETH(); + esp_netif_t *eth_netif = esp_netif_new(&cfg); + // Attach Ethernet driver to TCP/IP stack + ESP_ERROR_CHECK(esp_netif_attach(eth_netif, esp_eth_new_netif_glue(eth_handles[0]))); + } else { + // Use ESP_NETIF_INHERENT_DEFAULT_ETH when multiple Ethernet interfaces are used and so you need to modify + // esp-netif configuration parameters for each interface (name, priority, etc.). + esp_netif_inherent_config_t esp_netif_config = ESP_NETIF_INHERENT_DEFAULT_ETH(); + esp_netif_config_t cfg_spi = { + .base = &esp_netif_config, + .stack = ESP_NETIF_NETSTACK_DEFAULT_ETH + }; + char if_key_str[10]; + char if_desc_str[10]; + char num_str[3]; + for (int i = 0; i < eth_port_cnt; i++) { + itoa(i, num_str, 10); + strcat(strcpy(if_key_str, "ETH_"), num_str); + strcat(strcpy(if_desc_str, "eth"), num_str); + esp_netif_config.if_key = if_key_str; + esp_netif_config.if_desc = if_desc_str; + esp_netif_config.route_prio -= i*5; + esp_netif_t *eth_netif = esp_netif_new(&cfg_spi); - // Init MAC and PHY configs to default - eth_mac_config_t mac_config = ETH_MAC_DEFAULT_CONFIG(); - eth_phy_config_t phy_config = ETH_PHY_DEFAULT_CONFIG(); - - phy_config.phy_addr = CONFIG_EXAMPLE_ETH_PHY_ADDR; - phy_config.reset_gpio_num = CONFIG_EXAMPLE_ETH_PHY_RST_GPIO; - eth_esp32_emac_config_t esp32_emac_config = ETH_ESP32_EMAC_DEFAULT_CONFIG(); - esp32_emac_config.smi_mdc_gpio_num = CONFIG_EXAMPLE_ETH_MDC_GPIO; - esp32_emac_config.smi_mdio_gpio_num = CONFIG_EXAMPLE_ETH_MDIO_GPIO; - esp_eth_mac_t *mac = esp_eth_mac_new_esp32(&esp32_emac_config, &mac_config); -#if CONFIG_EXAMPLE_ETH_PHY_IP101 - esp_eth_phy_t *phy = esp_eth_phy_new_ip101(&phy_config); -#elif CONFIG_EXAMPLE_ETH_PHY_RTL8201 - esp_eth_phy_t *phy = esp_eth_phy_new_rtl8201(&phy_config); -#elif CONFIG_EXAMPLE_ETH_PHY_LAN87XX - esp_eth_phy_t *phy = esp_eth_phy_new_lan87xx(&phy_config); -#elif CONFIG_EXAMPLE_ETH_PHY_DP83848 - esp_eth_phy_t *phy = esp_eth_phy_new_dp83848(&phy_config); -#elif CONFIG_EXAMPLE_ETH_PHY_KSZ80XX - esp_eth_phy_t *phy = esp_eth_phy_new_ksz80xx(&phy_config); -#endif - esp_eth_config_t config = ETH_DEFAULT_CONFIG(mac, phy); - esp_eth_handle_t eth_handle = NULL; - ESP_ERROR_CHECK(esp_eth_driver_install(&config, ð_handle)); - /* attach Ethernet driver to TCP/IP stack */ - ESP_ERROR_CHECK(esp_netif_attach(eth_netif, esp_eth_new_netif_glue(eth_handle))); -#endif //CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET - -#if CONFIG_EXAMPLE_USE_SPI_ETHERNET - // Create instance(s) of esp-netif for SPI Ethernet(s) - esp_netif_inherent_config_t esp_netif_config = ESP_NETIF_INHERENT_DEFAULT_ETH(); - esp_netif_config_t cfg_spi = { - .base = &esp_netif_config, - .stack = ESP_NETIF_NETSTACK_DEFAULT_ETH - }; - esp_netif_t *eth_netif_spi[CONFIG_EXAMPLE_SPI_ETHERNETS_NUM] = { NULL }; - char if_key_str[10]; - char if_desc_str[10]; - char num_str[3]; - for (int i = 0; i < CONFIG_EXAMPLE_SPI_ETHERNETS_NUM; i++) { - itoa(i, num_str, 10); - strcat(strcpy(if_key_str, "ETH_SPI_"), num_str); - strcat(strcpy(if_desc_str, "eth"), num_str); - esp_netif_config.if_key = if_key_str; - esp_netif_config.if_desc = if_desc_str; - esp_netif_config.route_prio = 30 - i; - eth_netif_spi[i] = esp_netif_new(&cfg_spi); + // Attach Ethernet driver to TCP/IP stack + ESP_ERROR_CHECK(esp_netif_attach(eth_netif, esp_eth_new_netif_glue(eth_handles[i]))); + } } - // Init MAC and PHY configs to default - eth_mac_config_t mac_config_spi = ETH_MAC_DEFAULT_CONFIG(); - eth_phy_config_t phy_config_spi = ETH_PHY_DEFAULT_CONFIG(); - - // Install GPIO ISR handler to be able to service SPI Eth modlues interrupts - gpio_install_isr_service(0); - - // Init SPI bus - spi_bus_config_t buscfg = { - .miso_io_num = CONFIG_EXAMPLE_ETH_SPI_MISO_GPIO, - .mosi_io_num = CONFIG_EXAMPLE_ETH_SPI_MOSI_GPIO, - .sclk_io_num = CONFIG_EXAMPLE_ETH_SPI_SCLK_GPIO, - .quadwp_io_num = -1, - .quadhd_io_num = -1, - }; - ESP_ERROR_CHECK(spi_bus_initialize(CONFIG_EXAMPLE_ETH_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO)); - - // Init specific SPI Ethernet module configuration from Kconfig (CS GPIO, Interrupt GPIO, etc.) - spi_eth_module_config_t spi_eth_module_config[CONFIG_EXAMPLE_SPI_ETHERNETS_NUM]; - INIT_SPI_ETH_MODULE_CONFIG(spi_eth_module_config, 0); -#if CONFIG_EXAMPLE_SPI_ETHERNETS_NUM > 1 - INIT_SPI_ETH_MODULE_CONFIG(spi_eth_module_config, 1); -#endif - - // Configure SPI interface and Ethernet driver for specific SPI module - esp_eth_mac_t *mac_spi[CONFIG_EXAMPLE_SPI_ETHERNETS_NUM]; - esp_eth_phy_t *phy_spi[CONFIG_EXAMPLE_SPI_ETHERNETS_NUM]; - esp_eth_handle_t eth_handle_spi[CONFIG_EXAMPLE_SPI_ETHERNETS_NUM] = { NULL }; - spi_device_interface_config_t spi_devcfg = { - .mode = 0, - .clock_speed_hz = CONFIG_EXAMPLE_ETH_SPI_CLOCK_MHZ * 1000 * 1000, - .queue_size = 20 - }; - for (int i = 0; i < CONFIG_EXAMPLE_SPI_ETHERNETS_NUM; i++) { - // Set SPI module Chip Select GPIO - spi_devcfg.spics_io_num = spi_eth_module_config[i].spi_cs_gpio; - // Set remaining GPIO numbers and configuration used by the SPI module - phy_config_spi.phy_addr = spi_eth_module_config[i].phy_addr; - phy_config_spi.reset_gpio_num = spi_eth_module_config[i].phy_reset_gpio; -#if CONFIG_EXAMPLE_USE_KSZ8851SNL - eth_ksz8851snl_config_t ksz8851snl_config = ETH_KSZ8851SNL_DEFAULT_CONFIG(CONFIG_EXAMPLE_ETH_SPI_HOST, &spi_devcfg); - ksz8851snl_config.int_gpio_num = spi_eth_module_config[i].int_gpio; - mac_spi[i] = esp_eth_mac_new_ksz8851snl(&ksz8851snl_config, &mac_config_spi); - phy_spi[i] = esp_eth_phy_new_ksz8851snl(&phy_config_spi); -#elif CONFIG_EXAMPLE_USE_DM9051 - eth_dm9051_config_t dm9051_config = ETH_DM9051_DEFAULT_CONFIG(CONFIG_EXAMPLE_ETH_SPI_HOST, &spi_devcfg); - dm9051_config.int_gpio_num = spi_eth_module_config[i].int_gpio; - mac_spi[i] = esp_eth_mac_new_dm9051(&dm9051_config, &mac_config_spi); - phy_spi[i] = esp_eth_phy_new_dm9051(&phy_config_spi); -#elif CONFIG_EXAMPLE_USE_W5500 - eth_w5500_config_t w5500_config = ETH_W5500_DEFAULT_CONFIG(CONFIG_EXAMPLE_ETH_SPI_HOST, &spi_devcfg); - w5500_config.int_gpio_num = spi_eth_module_config[i].int_gpio; - mac_spi[i] = esp_eth_mac_new_w5500(&w5500_config, &mac_config_spi); - phy_spi[i] = esp_eth_phy_new_w5500(&phy_config_spi); -#endif - esp_eth_config_t eth_config_spi = ETH_DEFAULT_CONFIG(mac_spi[i], phy_spi[i]); - ESP_ERROR_CHECK(esp_eth_driver_install(ð_config_spi, ð_handle_spi[i])); - - /* The SPI Ethernet module might not have a burned factory MAC address, we cat to set it manually. - 02:00:00 is a Locally Administered OUI range so should not be used except when testing on a LAN under your control. - */ - ESP_ERROR_CHECK(esp_eth_ioctl(eth_handle_spi[i], ETH_CMD_S_MAC_ADDR, (uint8_t[]) { - 0x02, 0x00, 0x00, 0x12, 0x34, 0x56 + i - })); - - // attach Ethernet driver to TCP/IP stack - ESP_ERROR_CHECK(esp_netif_attach(eth_netif_spi[i], esp_eth_new_netif_glue(eth_handle_spi[i]))); - } -#endif // CONFIG_ETH_USE_SPI_ETHERNET - // Register user defined event handers ESP_ERROR_CHECK(esp_event_handler_register(ETH_EVENT, ESP_EVENT_ANY_ID, ð_event_handler, NULL)); ESP_ERROR_CHECK(esp_event_handler_register(IP_EVENT, IP_EVENT_ETH_GOT_IP, &got_ip_event_handler, NULL)); - /* start Ethernet driver state machine */ -#if CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET - ESP_ERROR_CHECK(esp_eth_start(eth_handle)); -#endif // CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET -#if CONFIG_EXAMPLE_USE_SPI_ETHERNET - for (int i = 0; i < CONFIG_EXAMPLE_SPI_ETHERNETS_NUM; i++) { - ESP_ERROR_CHECK(esp_eth_start(eth_handle_spi[i])); + // Start Ethernet driver state machine + for (int i = 0; i < eth_port_cnt; i++) { + ESP_ERROR_CHECK(esp_eth_start(eth_handles[i])); } -#endif // CONFIG_EXAMPLE_USE_SPI_ETHERNET } diff --git a/examples/ethernet/enc28j60/README.md b/examples/ethernet/enc28j60/README.md index e1c4682220..5d57b0156b 100644 --- a/examples/ethernet/enc28j60/README.md +++ b/examples/ethernet/enc28j60/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | # ENC28J60 Example (See the README.md file in the upper level 'examples' directory for more information about examples.) @@ -17,7 +17,7 @@ If you have a more complicated application to go (for example, connect to some I ### Hardware Required To run this example, you need to prepare following hardwares: -* [ESP32 dev board](https://www.espressif.com/en/products/devkits?id=ESP32) (e.g. ESP32-PICO, ESP32 DevKitC, etc) +* [ESP32 dev board](https://www.espressif.com/en/products/devkits) (e.g. ESP32-PICO, ESP32 DevKitC, etc) * ENC28J60 Ethernet module (the latest revision should be 6) * **!! IMPORTANT !!** Proper input power source since ENC28J60 is quite power consuming device (it consumes more than 200 mA in peaks when transmitting). If improper power source is used, input voltage may drop and ENC28J60 may either provide nonsense response to host controller via SPI (fail to read registers properly) or it may enter to some strange state in the worst case. There are several options how to resolve it: * Power ESP32 dev board from `USB 3.0`, if the dev board is used as source of power to the ENC28J60 module. diff --git a/examples/ethernet/enc28j60/main/Kconfig.projbuild b/examples/ethernet/enc28j60/main/Kconfig.projbuild index 37bc799661..60001d4ed1 100644 --- a/examples/ethernet/enc28j60/main/Kconfig.projbuild +++ b/examples/ethernet/enc28j60/main/Kconfig.projbuild @@ -14,7 +14,7 @@ menu "Example Configuration" range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX default 14 if IDF_TARGET_ESP32 default 12 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 - default 6 if IDF_TARGET_ESP32C3 + default 6 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 help Set the GPIO number used by SPI SCLK. @@ -23,7 +23,7 @@ menu "Example Configuration" range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX default 13 if IDF_TARGET_ESP32 default 11 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 - default 7 if IDF_TARGET_ESP32C3 + default 7 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 help Set the GPIO number used by SPI MOSI. @@ -32,7 +32,7 @@ menu "Example Configuration" range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX default 12 if IDF_TARGET_ESP32 default 13 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 - default 2 if IDF_TARGET_ESP32C3 + default 2 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 help Set the GPIO number used by SPI MISO. @@ -40,7 +40,7 @@ menu "Example Configuration" int "SPI CS GPIO number" range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX default 15 if IDF_TARGET_ESP32 - default 10 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 + default 10 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C2 help Set the GPIO number used by SPI CS. @@ -55,6 +55,7 @@ menu "Example Configuration" int "Interrupt GPIO number" range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX default 4 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 + default 4 if IDF_TARGET_ESP32C2 help Set the GPIO number used by ENC28J60 interrupt. diff --git a/examples/ethernet/eth2ap/CMakeLists.txt b/examples/ethernet/eth2ap/CMakeLists.txt index ec2b0f57d9..daf2d1f318 100644 --- a/examples/ethernet/eth2ap/CMakeLists.txt +++ b/examples/ethernet/eth2ap/CMakeLists.txt @@ -1,4 +1,6 @@ cmake_minimum_required(VERSION 3.16) +set(EXTRA_COMPONENT_DIRS $ENV{IDF_PATH}/examples/ethernet/basic/components/ethernet_init) + include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(eth2ap) diff --git a/examples/ethernet/eth2ap/README.md b/examples/ethernet/eth2ap/README.md index 36a87603c4..f6e53ff3f5 100644 --- a/examples/ethernet/eth2ap/README.md +++ b/examples/ethernet/eth2ap/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | # eth2ap Example (See the README.md file in the upper level 'examples' directory for more information about examples. To try a more complex application about Ethernet to WiFi data forwarding, please go to [iot-solution](https://github.com/espressif/esp-iot-solution/tree/release/v1.0/examples/eth2wifi).) diff --git a/examples/ethernet/eth2ap/main/Kconfig.projbuild b/examples/ethernet/eth2ap/main/Kconfig.projbuild index 56c4779e24..885ccf6dbb 100644 --- a/examples/ethernet/eth2ap/main/Kconfig.projbuild +++ b/examples/ethernet/eth2ap/main/Kconfig.projbuild @@ -1,186 +1,5 @@ menu "Example Configuration" - orsource "$IDF_PATH/examples/common_components/env_caps/$IDF_TARGET/Kconfig.env_caps" - - config EXAMPLE_USE_SPI_ETHERNET - bool - - choice EXAMPLE_ETHERNET_TYPE - prompt "Ethernet Type" - default EXAMPLE_USE_INTERNAL_ETHERNET if IDF_TARGET_ESP32 - default EXAMPLE_USE_W5500 - help - Select which kind of Ethernet will be used in the example. - - config EXAMPLE_USE_INTERNAL_ETHERNET - depends on IDF_TARGET_ESP32 - select ETH_USE_ESP32_EMAC - bool "Internal EMAC" - help - Select internal Ethernet MAC controller. - - config EXAMPLE_USE_DM9051 - bool "DM9051 Module" - select EXAMPLE_USE_SPI_ETHERNET - select ETH_USE_SPI_ETHERNET - select ETH_SPI_ETHERNET_DM9051 - help - Select external SPI-Ethernet module (DM9051). - - config EXAMPLE_USE_W5500 - bool "W5500 Module" - select EXAMPLE_USE_SPI_ETHERNET - select ETH_USE_SPI_ETHERNET - select ETH_SPI_ETHERNET_W5500 - help - Select external SPI-Ethernet module (W5500). - - config EXAMPLE_USE_KSZ8851SNL - bool "KSZ8851SNL Module" - select EXAMPLE_USE_SPI_ETHERNET - select ETH_USE_SPI_ETHERNET - select ETH_SPI_ETHERNET_KSZ8851SNL - help - Select external SPI-Ethernet module (KSZ8851SNL). - endchoice # EXAMPLE_ETHERNET_TYPE - - if EXAMPLE_USE_INTERNAL_ETHERNET - choice EXAMPLE_ETH_PHY_MODEL - prompt "Ethernet PHY Device" - default EXAMPLE_ETH_PHY_IP101 - help - Select the Ethernet PHY device to use in the example. - - config EXAMPLE_ETH_PHY_IP101 - bool "IP101" - help - IP101 is a single port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver. - Goto http://www.icplus.com.tw/pp-IP101G.html for more information about it. - - config EXAMPLE_ETH_PHY_RTL8201 - bool "RTL8201/SR8201" - help - RTL8201F/SR8201F is a single port 10/100Mb Ethernet Transceiver with auto MDIX. - Goto http://www.corechip-sz.com/productsview.asp?id=22 for more information about it. - - config EXAMPLE_ETH_PHY_LAN87XX - bool "LAN87xx" - help - Below chips are supported: - LAN8710A is a small footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and - flexPWR® Technology. - LAN8720A is a small footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support. - LAN8740A/LAN8741A is a small footprint MII/RMII 10/100 Energy Efficient Ethernet Transceiver - with HP Auto-MDIX and flexPWR® Technology. - LAN8742A is a small footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and - flexPWR® Technology. - Goto https://www.microchip.com for more information about them. - - config EXAMPLE_ETH_PHY_DP83848 - bool "DP83848" - help - DP83848 is a single port 10/100Mb/s Ethernet Physical Layer Transceiver. - Goto http://www.ti.com/product/DP83848J for more information about it. - - config EXAMPLE_ETH_PHY_KSZ80XX - bool "KSZ80xx" - help - With the KSZ80xx series, Microchip offers single-chip 10BASE-T/100BASE-TX - Ethernet Physical Layer Tranceivers (PHY). - The following chips are supported: KSZ8001, KSZ8021, KSZ8031, KSZ8041, - KSZ8051, KSZ8061, KSZ8081, KSZ8091 - Goto https://www.microchip.com for more information about them. - endchoice # EXAMPLE_ETH_PHY_MODEL - - config EXAMPLE_ETH_MDC_GPIO - int "SMI MDC GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 23 - help - Set the GPIO number used by SMI MDC. - - config EXAMPLE_ETH_MDIO_GPIO - int "SMI MDIO GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 18 - help - Set the GPIO number used by SMI MDIO. - endif # EXAMPLE_USE_INTERNAL_ETHERNET - - if EXAMPLE_USE_SPI_ETHERNET - config EXAMPLE_ETH_SPI_HOST - int "SPI Host Number" - range 0 2 - default 1 - help - Set the SPI host used to communicate with the SPI Ethernet Controller. - - config EXAMPLE_ETH_SPI_SCLK_GPIO - int "SPI SCLK GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 14 if IDF_TARGET_ESP32 - default 12 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 - default 6 if IDF_TARGET_ESP32C3 - help - Set the GPIO number used by SPI SCLK. - - config EXAMPLE_ETH_SPI_MOSI_GPIO - int "SPI MOSI GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 13 if IDF_TARGET_ESP32 - default 11 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 - default 7 if IDF_TARGET_ESP32C3 - help - Set the GPIO number used by SPI MOSI. - - config EXAMPLE_ETH_SPI_MISO_GPIO - int "SPI MISO GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX - default 12 if IDF_TARGET_ESP32 - default 13 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 - default 2 if IDF_TARGET_ESP32C3 - help - Set the GPIO number used by SPI MISO. - - config EXAMPLE_ETH_SPI_CS_GPIO - int "SPI CS GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 15 if IDF_TARGET_ESP32 - default 10 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 - help - Set the GPIO number used by SPI CS. - - config EXAMPLE_ETH_SPI_CLOCK_MHZ - int "SPI clock speed (MHz)" - range 5 80 - default 12 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32C3 - default 36 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 - help - Set the clock speed (MHz) of SPI interface. - - config EXAMPLE_ETH_SPI_INT_GPIO - int "Interrupt GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX - default 4 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 - help - Set the GPIO number used by the SPI Ethernet module interrupt line. - endif # EXAMPLE_USE_SPI_ETHERNET - - config EXAMPLE_ETH_PHY_RST_GPIO - int "PHY Reset GPIO number" - range -1 ENV_GPIO_OUT_RANGE_MAX - default 5 - help - Set the GPIO number used to reset PHY chip. - Set to -1 to disable PHY chip hardware reset. - - config EXAMPLE_ETH_PHY_ADDR - int "PHY Address" - range 0 31 - default 1 - help - Set PHY address according your board schematic. - config EXAMPLE_WIFI_SSID string "Wi-Fi SSID" default "eth2ap" diff --git a/examples/ethernet/eth2ap/main/ethernet_example_main.c b/examples/ethernet/eth2ap/main/ethernet_example_main.c index b98e49c18b..afccd20451 100644 --- a/examples/ethernet/eth2ap/main/ethernet_example_main.c +++ b/examples/ethernet/eth2ap/main/ethernet_example_main.c @@ -18,12 +18,9 @@ #include "esp_wifi.h" #include "nvs_flash.h" #include "esp_private/wifi.h" -#include "driver/gpio.h" -#if CONFIG_ETH_USE_SPI_ETHERNET -#include "driver/spi_master.h" -#endif +#include "ethernet_init.h" -static const char *TAG = "eth_example"; +static const char *TAG = "eth2ap_example"; static esp_eth_handle_t s_eth_handle = NULL; static QueueHandle_t flow_control_queue = NULL; static bool s_sta_is_connected = false; @@ -152,75 +149,19 @@ static void wifi_event_handler(void *arg, esp_event_base_t event_base, static void initialize_ethernet(void) { - ESP_ERROR_CHECK(esp_event_handler_register(ETH_EVENT, ESP_EVENT_ANY_ID, eth_event_handler, NULL)); - eth_mac_config_t mac_config = ETH_MAC_DEFAULT_CONFIG(); - eth_phy_config_t phy_config = ETH_PHY_DEFAULT_CONFIG(); - phy_config.phy_addr = CONFIG_EXAMPLE_ETH_PHY_ADDR; - phy_config.reset_gpio_num = CONFIG_EXAMPLE_ETH_PHY_RST_GPIO; -#if CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET - eth_esp32_emac_config_t esp32_emac_config = ETH_ESP32_EMAC_DEFAULT_CONFIG(); - esp32_emac_config.smi_mdc_gpio_num = CONFIG_EXAMPLE_ETH_MDC_GPIO; - esp32_emac_config.smi_mdio_gpio_num = CONFIG_EXAMPLE_ETH_MDIO_GPIO; - esp_eth_mac_t *mac = esp_eth_mac_new_esp32(&esp32_emac_config, &mac_config); -#if CONFIG_EXAMPLE_ETH_PHY_IP101 - esp_eth_phy_t *phy = esp_eth_phy_new_ip101(&phy_config); -#elif CONFIG_EXAMPLE_ETH_PHY_RTL8201 - esp_eth_phy_t *phy = esp_eth_phy_new_rtl8201(&phy_config); -#elif CONFIG_EXAMPLE_ETH_PHY_LAN87XX - esp_eth_phy_t *phy = esp_eth_phy_new_lan87xx(&phy_config); -#elif CONFIG_EXAMPLE_ETH_PHY_DP83848 - esp_eth_phy_t *phy = esp_eth_phy_new_dp83848(&phy_config); -#elif CONFIG_EXAMPLE_ETH_PHY_KSZ80XX - esp_eth_phy_t *phy = esp_eth_phy_new_ksz80xx(&phy_config); -#endif -#elif CONFIG_ETH_USE_SPI_ETHERNET - gpio_install_isr_service(0); - spi_bus_config_t buscfg = { - .miso_io_num = CONFIG_EXAMPLE_ETH_SPI_MISO_GPIO, - .mosi_io_num = CONFIG_EXAMPLE_ETH_SPI_MOSI_GPIO, - .sclk_io_num = CONFIG_EXAMPLE_ETH_SPI_SCLK_GPIO, - .quadwp_io_num = -1, - .quadhd_io_num = -1, - }; - ESP_ERROR_CHECK(spi_bus_initialize(CONFIG_EXAMPLE_ETH_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO)); - - spi_device_interface_config_t spi_devcfg = { - .mode = 0, - .clock_speed_hz = CONFIG_EXAMPLE_ETH_SPI_CLOCK_MHZ * 1000 * 1000, - .spics_io_num = CONFIG_EXAMPLE_ETH_SPI_CS_GPIO, - .queue_size = 20 - }; -#if CONFIG_EXAMPLE_USE_KSZ8851SNL - eth_ksz8851snl_config_t ksz8851snl_config = ETH_KSZ8851SNL_DEFAULT_CONFIG(CONFIG_EXAMPLE_ETH_SPI_HOST, &spi_devcfg); - ksz8851snl_config.int_gpio_num = CONFIG_EXAMPLE_ETH_SPI_INT_GPIO; - esp_eth_mac_t *mac = esp_eth_mac_new_ksz8851snl(&ksz8851snl_config, &mac_config); - esp_eth_phy_t *phy = esp_eth_phy_new_ksz8851snl(&phy_config); -#elif CONFIG_EXAMPLE_USE_DM9051 - eth_dm9051_config_t dm9051_config = ETH_DM9051_DEFAULT_CONFIG(CONFIG_EXAMPLE_ETH_SPI_HOST, &spi_devcfg); - dm9051_config.int_gpio_num = CONFIG_EXAMPLE_ETH_SPI_INT_GPIO; - esp_eth_mac_t *mac = esp_eth_mac_new_dm9051(&dm9051_config, &mac_config); - esp_eth_phy_t *phy = esp_eth_phy_new_dm9051(&phy_config); -#elif CONFIG_EXAMPLE_USE_W5500 - eth_w5500_config_t w5500_config = ETH_W5500_DEFAULT_CONFIG(CONFIG_EXAMPLE_ETH_SPI_HOST, &spi_devcfg); - w5500_config.int_gpio_num = CONFIG_EXAMPLE_ETH_SPI_INT_GPIO; - esp_eth_mac_t *mac = esp_eth_mac_new_w5500(&w5500_config, &mac_config); - esp_eth_phy_t *phy = esp_eth_phy_new_w5500(&phy_config); -#endif -#endif // CONFIG_ETH_USE_SPI_ETHERNET - esp_eth_config_t config = ETH_DEFAULT_CONFIG(mac, phy); - config.stack_input = pkt_eth2wifi; - ESP_ERROR_CHECK(esp_eth_driver_install(&config, &s_eth_handle)); -#if !CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET - /* The SPI Ethernet module might doesn't have a burned factory MAC address, we cat to set it manually. - 02:00:00 is a Locally Administered OUI range so should not be used except when testing on a LAN under your control. - */ - ESP_ERROR_CHECK(esp_eth_ioctl(s_eth_handle, ETH_CMD_S_MAC_ADDR, (uint8_t[]) { - 0x02, 0x00, 0x00, 0x12, 0x34, 0x56 - })); -#endif + uint8_t eth_port_cnt = 0; + esp_eth_handle_t *eth_handles; + ESP_ERROR_CHECK(example_eth_init(ð_handles, ð_port_cnt)); + if (eth_port_cnt > 1) { + ESP_LOGW(TAG, "multiple Ethernet devices detected, the first initialized is to be used!"); + } + s_eth_handle = eth_handles[0]; + free(eth_handles); + ESP_ERROR_CHECK(esp_eth_update_input_path(s_eth_handle, pkt_eth2wifi, NULL)); bool eth_promiscuous = true; - esp_eth_ioctl(s_eth_handle, ETH_CMD_S_PROMISCUOUS, ð_promiscuous); - esp_eth_start(s_eth_handle); + ESP_ERROR_CHECK(esp_eth_ioctl(s_eth_handle, ETH_CMD_S_PROMISCUOUS, ð_promiscuous)); + ESP_ERROR_CHECK(esp_event_handler_register(ETH_EVENT, ESP_EVENT_ANY_ID, eth_event_handler, NULL)); + ESP_ERROR_CHECK(esp_eth_start(s_eth_handle)); } static void initialize_wifi(void) diff --git a/examples/ethernet/iperf/CMakeLists.txt b/examples/ethernet/iperf/CMakeLists.txt index b1e914439a..ff4d488339 100644 --- a/examples/ethernet/iperf/CMakeLists.txt +++ b/examples/ethernet/iperf/CMakeLists.txt @@ -4,7 +4,7 @@ cmake_minimum_required(VERSION 3.16) set(EXTRA_COMPONENT_DIRS $ENV{IDF_PATH}/examples/system/console/advanced/components $ENV{IDF_PATH}/examples/common_components/iperf - $ENV{IDF_PATH}/examples/ethernet/enc28j60/components/eth_enc28j60) + $ENV{IDF_PATH}/examples/ethernet/basic/components/ethernet_init) include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(ethernet_iperf) diff --git a/examples/ethernet/iperf/README.md b/examples/ethernet/iperf/README.md index e211bf4d36..573e751551 100644 --- a/examples/ethernet/iperf/README.md +++ b/examples/ethernet/iperf/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | # Ethernet iperf Example diff --git a/examples/ethernet/iperf/iperf_test.py b/examples/ethernet/iperf/iperf_test.py index 9fe3f9f2be..1233369257 100644 --- a/examples/ethernet/iperf/iperf_test.py +++ b/examples/ethernet/iperf/iperf_test.py @@ -26,7 +26,7 @@ except ImportError: # Only used for type annotations pass -NO_BANDWIDTH_LIMIT = -1 # iperf send bandwith is not limited +NO_BANDWIDTH_LIMIT = -1 # iperf send bandwidth is not limited class IperfTestUtilityEth(IperfUtility.IperfTestUtility): @@ -50,7 +50,7 @@ class IperfTestUtilityEth(IperfUtility.IperfTestUtility): self.dut.write('ethernet start') time.sleep(10) self.dut.write('ethernet info') - dut_ip = self.dut.expect(re.compile(r'ETHIP: (\d+[.]\d+[.]\d+[.]\d+)'))[0] + dut_ip = self.dut.expect(re.compile(r'ETHIP: (\d+[.]\d+[.]\d+[.]\d+)\r'))[0] rssi = 0 return dut_ip, rssi diff --git a/examples/ethernet/iperf/main/Kconfig.projbuild b/examples/ethernet/iperf/main/Kconfig.projbuild index 10c453b32b..83d85cef65 100644 --- a/examples/ethernet/iperf/main/Kconfig.projbuild +++ b/examples/ethernet/iperf/main/Kconfig.projbuild @@ -1,7 +1,5 @@ menu "Example Configuration" - orsource "$IDF_PATH/examples/common_components/env_caps/$IDF_TARGET/Kconfig.env_caps" - config EXAMPLE_STORE_HISTORY bool "Store command history in flash" default y @@ -9,212 +7,4 @@ menu "Example Configuration" Linenoise line editing library provides functions to save and load command history. If this option is enabled, initalizes a FAT filesystem and uses it to store command history. - - config EXAMPLE_USE_SPI_ETHERNET - bool - - choice EXAMPLE_ETHERNET_TYPE - prompt "Ethernet Type" - default EXAMPLE_USE_INTERNAL_ETHERNET if IDF_TARGET_ESP32 - default EXAMPLE_USE_W5500 - help - Select which kind of Ethernet will be used in the example. - - config EXAMPLE_USE_INTERNAL_ETHERNET - depends on IDF_TARGET_ESP32 - select ETH_USE_ESP32_EMAC - bool "Internal EMAC" - help - Select internal Ethernet MAC controller. - - config EXAMPLE_USE_DM9051 - bool "DM9051 Module" - select EXAMPLE_USE_SPI_ETHERNET - select ETH_USE_SPI_ETHERNET - select ETH_SPI_ETHERNET_DM9051 - help - Select external SPI-Ethernet module (DM9051). - - config EXAMPLE_USE_W5500 - bool "W5500 Module" - select EXAMPLE_USE_SPI_ETHERNET - select ETH_USE_SPI_ETHERNET - select ETH_SPI_ETHERNET_W5500 - help - Select external SPI-Ethernet module (W5500). - - config EXAMPLE_USE_KSZ8851SNL - bool "KSZ8851SNL Module" - select EXAMPLE_USE_SPI_ETHERNET - select ETH_USE_SPI_ETHERNET - select ETH_SPI_ETHERNET_KSZ8851SNL - help - Select external SPI-Ethernet module (KSZ8851SNL). - - config EXAMPLE_USE_ENC28J60 - bool "ENC28J60 Module" - select EXAMPLE_USE_SPI_ETHERNET - select ETH_USE_SPI_ETHERNET - select ETH_SPI_ETHERNET_ENC28J60 - help - Select external SPI-Ethernet module (ENC28J60). - endchoice # EXAMPLE_ETHERNET_TYPE - - if EXAMPLE_USE_INTERNAL_ETHERNET - choice EXAMPLE_ETH_PHY_MODEL - prompt "Ethernet PHY Device" - default EXAMPLE_ETH_PHY_IP101 - help - Select the Ethernet PHY device to use in the example. - - config EXAMPLE_ETH_PHY_IP101 - bool "IP101" - help - IP101 is a single port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver. - Goto http://www.icplus.com.tw/pp-IP101G.html for more information about it. - - config EXAMPLE_ETH_PHY_RTL8201 - bool "RTL8201/SR8201" - help - RTL8201F/SR8201F is a single port 10/100Mb Ethernet Transceiver with auto MDIX. - Goto http://www.corechip-sz.com/productsview.asp?id=22 for more information about it. - - config EXAMPLE_ETH_PHY_LAN87XX - bool "LAN87xx" - help - Below chips are supported: - LAN8710A is a small footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and - flexPWR® Technology. - LAN8720A is a small footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support. - LAN8740A/LAN8741A is a small footprint MII/RMII 10/100 Energy Efficient Ethernet Transceiver - with HP Auto-MDIX and flexPWR® Technology. - LAN8742A is a small footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and - flexPWR® Technology. - Goto https://www.microchip.com for more information about them. - - config EXAMPLE_ETH_PHY_DP83848 - bool "DP83848" - help - DP83848 is a single port 10/100Mb/s Ethernet Physical Layer Transceiver. - Goto http://www.ti.com/product/DP83848J for more information about it. - - config EXAMPLE_ETH_PHY_KSZ80XX - bool "KSZ80xx" - help - With the KSZ80xx series, Microchip offers single-chip 10BASE-T/100BASE-TX - Ethernet Physical Layer Tranceivers (PHY). - The following chips are supported: KSZ8001, KSZ8021, KSZ8031, KSZ8041, - KSZ8051, KSZ8061, KSZ8081, KSZ8091 - Goto https://www.microchip.com for more information about them. - endchoice # EXAMPLE_ETH_PHY_MODEL - - config EXAMPLE_ETH_MDC_GPIO - int "SMI MDC GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 23 - help - Set the GPIO number used by SMI MDC. - - config EXAMPLE_ETH_MDIO_GPIO - int "SMI MDIO GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 18 - help - Set the GPIO number used by SMI MDIO. - endif # EXAMPLE_USE_INTERNAL_ETHERNET - - if EXAMPLE_USE_SPI_ETHERNET - config EXAMPLE_ETH_SPI_HOST - int "SPI Host Number" - range 0 2 - default 1 - help - Set the SPI host used to communicate with the SPI Ethernet Controller. - - config EXAMPLE_ETH_SPI_SCLK_GPIO - int "SPI SCLK GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 14 if IDF_TARGET_ESP32 - default 12 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 - default 6 if IDF_TARGET_ESP32C3 - help - Set the GPIO number used by SPI SCLK. - - config EXAMPLE_ETH_SPI_MOSI_GPIO - int "SPI MOSI GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 13 if IDF_TARGET_ESP32 - default 11 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 - default 7 if IDF_TARGET_ESP32C3 - help - Set the GPIO number used by SPI MOSI. - - config EXAMPLE_ETH_SPI_MISO_GPIO - int "SPI MISO GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX - default 12 if IDF_TARGET_ESP32 - default 13 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 - default 2 if IDF_TARGET_ESP32C3 - help - Set the GPIO number used by SPI MISO. - - config EXAMPLE_ETH_SPI_CS_GPIO - int "SPI CS GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 15 if IDF_TARGET_ESP32 - default 10 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 - help - Set the GPIO number used by SPI CS. - - config EXAMPLE_ETH_SPI_CLOCK_MHZ - int "SPI clock speed (MHz)" - range 5 80 - default 8 if EXAMPLE_USE_ENC28J60 - default 12 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32C3 - default 36 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 - help - Set the clock speed (MHz) of SPI interface. - - config EXAMPLE_ETH_SPI_INT_GPIO - int "Interrupt GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX - default 4 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 - help - Set the GPIO number used by the SPI Ethernet module interrupt line. - endif # EXAMPLE_USE_SPI_ETHERNET - - config EXAMPLE_ETH_PHY_RST_GPIO - int "PHY Reset GPIO number" - range -1 ENV_GPIO_OUT_RANGE_MAX - default 5 - help - Set the GPIO number used to reset PHY chip. - Set to -1 to disable PHY chip hardware reset. - - config EXAMPLE_ETH_PHY_ADDR - int "PHY Address" - range 0 31 - default 1 - help - Set PHY address according your board schematic. - - if EXAMPLE_USE_ENC28J60 - choice EXAMPLE_ENC28J60_DUPLEX_MODE - prompt "Duplex Mode" - default EXAMPLE_ENC28J60_DUPLEX_HALF - help - Select ENC28J60 Duplex operation mode. - - config EXAMPLE_ENC28J60_DUPLEX_FULL - bool "Full Duplex" - help - Set ENC28J60 to Full Duplex mode. Do not forget to manually set the remote node (switch, router - or Ethernet controller) to full-duplex operation mode too. - - config EXAMPLE_ENC28J60_DUPLEX_HALF - bool "Half Duplex" - help - Set ENC28J60 to Half Duplex mode. - endchoice # EXAMPLE_ENC28J60_DUPLEX_MODE - endif # ETH_SPI_ETHERNET_ENC28J60 endmenu diff --git a/examples/ethernet/iperf/main/cmd_ethernet.c b/examples/ethernet/iperf/main/cmd_ethernet.c index 6200955743..0a7754feea 100644 --- a/examples/ethernet/iperf/main/cmd_ethernet.c +++ b/examples/ethernet/iperf/main/cmd_ethernet.c @@ -10,29 +10,25 @@ #include #include "freertos/FreeRTOS.h" #include "freertos/event_groups.h" +#include "sys/socket.h" // for INADDR_ANY #include "esp_netif.h" #include "esp_log.h" #include "esp_console.h" #include "esp_event.h" #include "esp_eth.h" #include "esp_mac.h" -#include "driver/gpio.h" +#include "esp_bit_defs.h" #include "argtable3/argtable3.h" +#include "ethernet_init.h" #include "iperf.h" #include "sdkconfig.h" -#if CONFIG_ETH_USE_SPI_ETHERNET -#include "driver/spi_master.h" -#if CONFIG_EXAMPLE_USE_ENC28J60 -#include "esp_eth_enc28j60.h" -#endif //CONFIG_EXAMPLE_USE_ENC28J60 -#endif // CONFIG_ETH_USE_SPI_ETHERNET -static esp_netif_ip_info_t ip; static bool started = false; static EventGroupHandle_t eth_event_group; static const int GOTIP_BIT = BIT0; -static esp_eth_handle_t eth_handle = NULL; -static esp_netif_t *eth_netif = NULL; +static esp_eth_handle_t *s_eth_handles = NULL; +static uint8_t s_eth_port_cnt = 0; +static esp_netif_t **s_eth_netifs = NULL; /* "ethernet" command */ static struct { @@ -50,12 +46,16 @@ static int eth_cmd_control(int argc, char **argv) if (!strncmp(eth_control_args.control->sval[0], "info", 4)) { uint8_t mac_addr[6]; - esp_eth_ioctl(eth_handle, ETH_CMD_G_MAC_ADDR, mac_addr); - printf("HW ADDR: " MACSTR "\r\n", MAC2STR(mac_addr)); - esp_netif_get_ip_info(eth_netif, &ip); - printf("ETHIP: " IPSTR "\r\n", IP2STR(&ip.ip)); - printf("ETHMASK: " IPSTR "\r\n", IP2STR(&ip.netmask)); - printf("ETHGW: " IPSTR "\r\n", IP2STR(&ip.gw)); + esp_netif_ip_info_t ip; + for(uint32_t i = 0; i < s_eth_port_cnt; i++) { + printf("%s:\r\n", esp_netif_get_desc(s_eth_netifs[i])); + esp_eth_ioctl(s_eth_handles[i], ETH_CMD_G_MAC_ADDR, mac_addr); + printf(" HW ADDR: " MACSTR "\r\n", MAC2STR(mac_addr)); + esp_netif_get_ip_info(s_eth_netifs[i], &ip); + printf(" ETHIP: " IPSTR "\r\n", IP2STR(&ip.ip)); + printf(" ETHMASK: " IPSTR "\r\n", IP2STR(&ip.netmask)); + printf(" ETHGW: " IPSTR "\r\n", IP2STR(&ip.gw)); + } } return 0; } @@ -119,14 +119,10 @@ static int eth_cmd_iperf(int argc, char **argv) cfg.len_send_buf = iperf_args.length->ival[0]; } - - /* acquiring for ip, could blocked here */ + /* wait for ip, could blocked here */ xEventGroupWaitBits(eth_event_group, GOTIP_BIT, pdFALSE, pdTRUE, portMAX_DELAY); - cfg.source_ip4 = ip.ip.addr; - if (cfg.source_ip4 == 0) { - return 0; - } + cfg.source_ip4 = INADDR_ANY; /* iperf -u */ if (iperf_args.udp->count == 0) { @@ -201,8 +197,6 @@ static void event_handler(void *arg, esp_event_base_t event_base, xEventGroupClearBits(eth_event_group, GOTIP_BIT); started = false; } else if (event_base == IP_EVENT && event_id == IP_EVENT_ETH_GOT_IP) { - ip_event_got_ip_t *event = (ip_event_got_ip_t *) event_data; - memcpy(&ip, &event->ip_info, sizeof(ip)); xEventGroupSetBits(eth_event_group, GOTIP_BIT); } } @@ -210,91 +204,38 @@ static void event_handler(void *arg, esp_event_base_t event_base, void register_ethernet(void) { eth_event_group = xEventGroupCreate(); - ESP_ERROR_CHECK(esp_netif_init()); ESP_ERROR_CHECK(esp_event_loop_create_default()); - esp_netif_config_t cfg = ESP_NETIF_DEFAULT_ETH(); - eth_netif = esp_netif_new(&cfg); - eth_mac_config_t mac_config = ETH_MAC_DEFAULT_CONFIG(); - eth_phy_config_t phy_config = ETH_PHY_DEFAULT_CONFIG(); - phy_config.phy_addr = CONFIG_EXAMPLE_ETH_PHY_ADDR; - phy_config.reset_gpio_num = CONFIG_EXAMPLE_ETH_PHY_RST_GPIO; -#if CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET - eth_esp32_emac_config_t esp32_emac_config = ETH_ESP32_EMAC_DEFAULT_CONFIG(); - esp32_emac_config.smi_mdc_gpio_num = CONFIG_EXAMPLE_ETH_MDC_GPIO; - esp32_emac_config.smi_mdio_gpio_num = CONFIG_EXAMPLE_ETH_MDIO_GPIO; - esp_eth_mac_t *mac = esp_eth_mac_new_esp32(&esp32_emac_config, &mac_config); -#if CONFIG_EXAMPLE_ETH_PHY_IP101 - esp_eth_phy_t *phy = esp_eth_phy_new_ip101(&phy_config); -#elif CONFIG_EXAMPLE_ETH_PHY_RTL8201 - esp_eth_phy_t *phy = esp_eth_phy_new_rtl8201(&phy_config); -#elif CONFIG_EXAMPLE_ETH_PHY_LAN87XX - esp_eth_phy_t *phy = esp_eth_phy_new_lan87xx(&phy_config); -#elif CONFIG_EXAMPLE_ETH_PHY_DP83848 - esp_eth_phy_t *phy = esp_eth_phy_new_dp83848(&phy_config); -#elif CONFIG_EXAMPLE_ETH_PHY_KSZ80XX - esp_eth_phy_t *phy = esp_eth_phy_new_ksz80xx(&phy_config); -#endif -#elif CONFIG_ETH_USE_SPI_ETHERNET - gpio_install_isr_service(0); - spi_bus_config_t buscfg = { - .miso_io_num = CONFIG_EXAMPLE_ETH_SPI_MISO_GPIO, - .mosi_io_num = CONFIG_EXAMPLE_ETH_SPI_MOSI_GPIO, - .sclk_io_num = CONFIG_EXAMPLE_ETH_SPI_SCLK_GPIO, - .quadwp_io_num = -1, - .quadhd_io_num = -1, - }; - ESP_ERROR_CHECK(spi_bus_initialize(CONFIG_EXAMPLE_ETH_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO)); + ESP_ERROR_CHECK(example_eth_init(&s_eth_handles, &s_eth_port_cnt)); - spi_device_interface_config_t spi_devcfg = { - .mode = 0, - .clock_speed_hz = CONFIG_EXAMPLE_ETH_SPI_CLOCK_MHZ * 1000 * 1000, - .spics_io_num = CONFIG_EXAMPLE_ETH_SPI_CS_GPIO, - .queue_size = 20 + ESP_ERROR_CHECK(esp_netif_init()); + s_eth_netifs = calloc(s_eth_port_cnt, sizeof(esp_netif_t *)); + esp_netif_inherent_config_t esp_netif_config = ESP_NETIF_INHERENT_DEFAULT_ETH(); + esp_netif_config_t cfg_spi = { + .base = &esp_netif_config, + .stack = ESP_NETIF_NETSTACK_DEFAULT_ETH }; -#if CONFIG_EXAMPLE_USE_KSZ8851SNL - eth_ksz8851snl_config_t ksz8851snl_config = ETH_KSZ8851SNL_DEFAULT_CONFIG(CONFIG_EXAMPLE_ETH_SPI_HOST, &spi_devcfg); - ksz8851snl_config.int_gpio_num = CONFIG_EXAMPLE_ETH_SPI_INT_GPIO; - esp_eth_mac_t *mac = esp_eth_mac_new_ksz8851snl(&ksz8851snl_config, &mac_config); - esp_eth_phy_t *phy = esp_eth_phy_new_ksz8851snl(&phy_config); -#elif CONFIG_EXAMPLE_USE_DM9051 - eth_dm9051_config_t dm9051_config = ETH_DM9051_DEFAULT_CONFIG(CONFIG_EXAMPLE_ETH_SPI_HOST, &spi_devcfg); - dm9051_config.int_gpio_num = CONFIG_EXAMPLE_ETH_SPI_INT_GPIO; - esp_eth_mac_t *mac = esp_eth_mac_new_dm9051(&dm9051_config, &mac_config); - esp_eth_phy_t *phy = esp_eth_phy_new_dm9051(&phy_config); -#elif CONFIG_EXAMPLE_USE_W5500 - eth_w5500_config_t w5500_config = ETH_W5500_DEFAULT_CONFIG(CONFIG_EXAMPLE_ETH_SPI_HOST, &spi_devcfg); - w5500_config.int_gpio_num = CONFIG_EXAMPLE_ETH_SPI_INT_GPIO; - esp_eth_mac_t *mac = esp_eth_mac_new_w5500(&w5500_config, &mac_config); - esp_eth_phy_t *phy = esp_eth_phy_new_w5500(&phy_config); -#elif CONFIG_EXAMPLE_USE_ENC28J60 - spi_devcfg.cs_ena_posttrans = enc28j60_cal_spi_cs_hold_time(CONFIG_EXAMPLE_ETH_SPI_CLOCK_MHZ); - eth_enc28j60_config_t enc28j60_config = ETH_ENC28J60_DEFAULT_CONFIG(CONFIG_EXAMPLE_ETH_SPI_HOST, &spi_devcfg); - enc28j60_config.int_gpio_num = CONFIG_EXAMPLE_ETH_SPI_INT_GPIO; - esp_eth_mac_t *mac = esp_eth_mac_new_enc28j60(&enc28j60_config, &mac_config); - phy_config.autonego_timeout_ms = 0; // ENC28J60 doesn't support auto-negotiation - phy_config.reset_gpio_num = -1; // ENC28J60 doesn't have a pin to reset internal PHY - esp_eth_phy_t *phy = esp_eth_phy_new_enc28j60(&phy_config); -#endif -#endif // CONFIG_ETH_USE_SPI_ETHERNET - esp_eth_config_t config = ETH_DEFAULT_CONFIG(mac, phy); - ESP_ERROR_CHECK(esp_eth_driver_install(&config, ð_handle)); -#if !CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET - /* The SPI Ethernet module might doesn't have a burned factory MAC address, we cat to set it manually. - 02:00:00 is a Locally Administered OUI range so should not be used except when testing on a LAN under your control. - */ - ESP_ERROR_CHECK(esp_eth_ioctl(eth_handle, ETH_CMD_S_MAC_ADDR, (uint8_t[]) { - 0x02, 0x00, 0x00, 0x12, 0x34, 0x56 - })); -#endif -#if CONFIG_EXAMPLE_USE_ENC28J60 && CONFIG_EXAMPLE_ENC28J60_DUPLEX_FULL - eth_duplex_t duplex = ETH_DUPLEX_FULL; - ESP_ERROR_CHECK(esp_eth_ioctl(eth_handle, ETH_CMD_S_DUPLEX_MODE, &duplex)); -#endif - ESP_ERROR_CHECK(esp_netif_attach(eth_netif, esp_eth_new_netif_glue(eth_handle))); + char if_key_str[10]; + char if_desc_str[10]; + char num_str[3]; + for (int i = 0; i < s_eth_port_cnt; i++) { + itoa(i, num_str, 10); + strcat(strcpy(if_key_str, "ETH_"), num_str); + strcat(strcpy(if_desc_str, "eth"), num_str); + esp_netif_config.if_key = if_key_str; + esp_netif_config.if_desc = if_desc_str; + esp_netif_config.route_prio -= i*5; + s_eth_netifs[i] = esp_netif_new(&cfg_spi); + + // attach Ethernet driver to TCP/IP stack + ESP_ERROR_CHECK(esp_netif_attach(s_eth_netifs[i], esp_eth_new_netif_glue(s_eth_handles[i]))); + } + ESP_ERROR_CHECK(esp_event_handler_register(ETH_EVENT, ESP_EVENT_ANY_ID, &event_handler, NULL)); ESP_ERROR_CHECK(esp_event_handler_register(IP_EVENT, IP_EVENT_ETH_GOT_IP, &event_handler, NULL)); - ESP_ERROR_CHECK(esp_eth_start(eth_handle)); + for (int i = 0; i < s_eth_port_cnt; i++) { + ESP_ERROR_CHECK(esp_eth_start(s_eth_handles[i])); + } eth_control_args.control = arg_str1(NULL, NULL, "", "Get info of Ethernet"); eth_control_args.end = arg_end(1); diff --git a/examples/get-started/blink/CMakeLists.txt b/examples/get-started/blink/CMakeLists.txt index c7b0832ffc..489742ae56 100644 --- a/examples/get-started/blink/CMakeLists.txt +++ b/examples/get-started/blink/CMakeLists.txt @@ -2,7 +2,5 @@ # CMakeLists in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.16) -set(EXTRA_COMPONENT_DIRS $ENV{IDF_PATH}/examples/common_components/led_strip) - include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(blink) diff --git a/examples/get-started/blink/README.md b/examples/get-started/blink/README.md index 3c9864fc27..b44a692fcc 100644 --- a/examples/get-started/blink/README.md +++ b/examples/get-started/blink/README.md @@ -5,9 +5,9 @@ (See the README.md file in the upper level 'examples' directory for more information about examples.) -This example demonstrates how to blink a LED using GPIO or RMT for the addressable LED, i.e. [WS2812](http://www.world-semi.com/Certifications/WS2812B.html). +This example demonstrates how to blink a LED using GPIO or using the [led_strip](https://components.espressif.com/component/espressif/led_strip) component for the addressable LED, i.e. [WS2812](http://www.world-semi.com/Certifications/WS2812B.html). -See the RMT examples in the [RMT Peripheral](../../peripherals/rmt) for more information about how to use it. +The `led_strip` is installed via [component manager](main/idf_component.yml). ## How to Use Example @@ -37,7 +37,7 @@ Open the project configuration menu (`idf.py menuconfig`). In the `Example Configuration` menu: * Select the LED type in the `Blink LED type` option. - * Use `GPIO` for regular LED blink. + * Use `GPIO` for regular LED blink. * Set the GPIO number used for the signal in the `Blink GPIO number` option. * Set the blinking period in the `Blink period in ms` option. @@ -53,7 +53,7 @@ See the [Getting Started Guide](https://docs.espressif.com/projects/esp-idf/en/l As you run the example, you will see the LED blinking, according to the previously defined period. For the addressable LED, you can also change the LED color by setting the `led_strip_set_pixel(led_strip, 0, 16, 16, 16);` (LED Strip, Pixel Number, Red, Green, Blue) with values from 0 to 255 in the [source file](main/blink_example_main.c). -``` +```text I (315) example: Example configured to blink addressable LED! I (325) example: Turning the LED OFF! I (1325) example: Turning the LED ON! diff --git a/examples/get-started/blink/main/blink_example_main.c b/examples/get-started/blink/main/blink_example_main.c index 3320ead77a..8a7c4ed50b 100644 --- a/examples/get-started/blink/main/blink_example_main.c +++ b/examples/get-started/blink/main/blink_example_main.c @@ -49,7 +49,10 @@ static void configure_led(void) .strip_gpio_num = BLINK_GPIO, .max_leds = 1, // at least one LED on board }; - ESP_ERROR_CHECK(led_strip_new_rmt_device(&strip_config, &led_strip)); + led_strip_rmt_config_t rmt_config = { + .resolution_hz = 10 * 1000 * 1000, // 10MHz + }; + ESP_ERROR_CHECK(led_strip_new_rmt_device(&strip_config, &rmt_config, &led_strip)); /* Set all LED off to clear all pixels */ led_strip_clear(led_strip); } diff --git a/examples/get-started/blink/main/idf_component.yml b/examples/get-started/blink/main/idf_component.yml new file mode 100644 index 0000000000..234f9781ac --- /dev/null +++ b/examples/get-started/blink/main/idf_component.yml @@ -0,0 +1,2 @@ +dependencies: + espressif/led_strip: "^2.0.0" diff --git a/examples/get-started/blink/pytest_blink.py b/examples/get-started/blink/pytest_blink.py index 47d3aaccbd..b7ea802c3b 100644 --- a/examples/get-started/blink/pytest_blink.py +++ b/examples/get-started/blink/pytest_blink.py @@ -1,7 +1,6 @@ # SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: CC0-1.0 -import hashlib import logging import os @@ -9,21 +8,6 @@ import pytest from pytest_embedded_idf.dut import IdfDut -def verify_elf_sha256_embedding(bin_path: str, sha256_reported: str) -> None: - elf_file = os.path.join(bin_path, 'blink.elf') - sha256 = hashlib.sha256() - with open(elf_file, 'rb') as f: - sha256.update(f.read()) - sha256_expected = sha256.hexdigest() - - logging.info(f'ELF file SHA256: {sha256_expected}') - logging.info(f'ELF file SHA256 (reported by the app): {sha256_reported}') - - # the app reports only the first several hex characters of the SHA256, check that they match - if not sha256_expected.startswith(sha256_reported): - raise ValueError('ELF file SHA256 mismatch') - - @pytest.mark.supported_targets @pytest.mark.generic def test_blink(dut: IdfDut) -> None: @@ -31,7 +15,3 @@ def test_blink(dut: IdfDut) -> None: binary_file = os.path.join(dut.app.binary_path, 'blink.bin') bin_size = os.path.getsize(binary_file) logging.info('blink_bin_size : {}KB'.format(bin_size // 1024)) - - sha256_reported = dut.expect(r'ELF file SHA256:\s+([a-f0-9]+)').group(1).decode('utf-8') - - verify_elf_sha256_embedding(dut.app.binary_path, sha256_reported) diff --git a/examples/get-started/hello_world/pytest_hello_world.py b/examples/get-started/hello_world/pytest_hello_world.py index 3cb161c774..7a55984ab1 100644 --- a/examples/get-started/hello_world/pytest_hello_world.py +++ b/examples/get-started/hello_world/pytest_hello_world.py @@ -1,22 +1,46 @@ # SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: CC0-1.0 +import hashlib +import logging from typing import Callable import pytest from pytest_embedded_idf.dut import IdfDut +from pytest_embedded_qemu.app import QemuApp from pytest_embedded_qemu.dut import QemuDut @pytest.mark.supported_targets @pytest.mark.generic -def test_hello_world(dut: IdfDut, log_minimum_free_heap_size: Callable[..., None]) -> None: +def test_hello_world( + dut: IdfDut, log_minimum_free_heap_size: Callable[..., None] +) -> None: dut.expect('Hello world!') log_minimum_free_heap_size() +def verify_elf_sha256_embedding(app: QemuApp, sha256_reported: str) -> None: + sha256 = hashlib.sha256() + with open(app.elf_file, 'rb') as f: + sha256.update(f.read()) + sha256_expected = sha256.hexdigest() + + logging.info(f'ELF file SHA256: {sha256_expected}') + logging.info(f'ELF file SHA256 (reported by the app): {sha256_reported}') + + # the app reports only the first several hex characters of the SHA256, check that they match + if not sha256_expected.startswith(sha256_reported): + raise ValueError('ELF file SHA256 mismatch') + + @pytest.mark.esp32 # we only support qemu on esp32 for now @pytest.mark.host_test @pytest.mark.qemu -def test_hello_world_host(dut: QemuDut) -> None: +def test_hello_world_host(app: QemuApp, dut: QemuDut) -> None: + sha256_reported = ( + dut.expect(r'ELF file SHA256:\s+([a-f0-9]+)').group(1).decode('utf-8') + ) + verify_elf_sha256_embedding(app, sha256_reported) + dut.expect('Hello world!') diff --git a/examples/network/.build-test-rules.yml b/examples/network/.build-test-rules.yml index 799c35c911..43f8ee13f0 100644 --- a/examples/network/.build-test-rules.yml +++ b/examples/network/.build-test-rules.yml @@ -7,11 +7,7 @@ examples/network/network_tests: reason: target esp32c2 is not supported yet examples/network/simple_sniffer: - disable: - - if: IDF_TARGET == "esp32c2" - temporary: true - reason: target esp32c2 is not supported yet disable_test: - - if: IDF_TARGET in ["esp32c3", "esp32s2", "esp32s3"] + - if: IDF_TARGET in ["esp32c3", "esp32c2", "esp32s2", "esp32s3"] temporary: true reason: not tested diff --git a/examples/network/bridge/CMakeLists.txt b/examples/network/bridge/CMakeLists.txt index 774bc527d7..3161df5b0d 100644 --- a/examples/network/bridge/CMakeLists.txt +++ b/examples/network/bridge/CMakeLists.txt @@ -2,5 +2,7 @@ # in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.16) +set(EXTRA_COMPONENT_DIRS $ENV{IDF_PATH}/examples/ethernet/basic/components/ethernet_init) + include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(bridge) diff --git a/examples/network/bridge/main/bridge_example_main.c b/examples/network/bridge/main/bridge_example_main.c index f4f9d02bdc..e0cd3f60c5 100644 --- a/examples/network/bridge/main/bridge_example_main.c +++ b/examples/network/bridge/main/bridge_example_main.c @@ -13,43 +13,12 @@ #include "esp_eth.h" #include "esp_event.h" #include "esp_log.h" -#include "driver/gpio.h" +#include "esp_mac.h" +#include "ethernet_init.h" #include "sdkconfig.h" -#if CONFIG_ETH_USE_SPI_ETHERNET -#include "driver/spi_master.h" -#endif // CONFIG_ETH_USE_SPI_ETHERNET static const char *TAG = "eth_bridge_example"; -#if CONFIG_EXAMPLE_SPI_ETHERNETS_NUM -#define SPI_ETHERNETS_NUM CONFIG_EXAMPLE_SPI_ETHERNETS_NUM -#else -#define SPI_ETHERNETS_NUM 0 -#endif - -#if CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET -#define INTERNAL_ETHERNETS_NUM 1 -#else -#define INTERNAL_ETHERNETS_NUM 0 -#endif - -#if CONFIG_EXAMPLE_USE_SPI_ETHERNET -#define INIT_SPI_ETH_MODULE_CONFIG(eth_module_config, num) \ - do { \ - eth_module_config[num].spi_cs_gpio = CONFIG_EXAMPLE_ETH_SPI_CS ##num## _GPIO; \ - eth_module_config[num].int_gpio = CONFIG_EXAMPLE_ETH_SPI_INT ##num## _GPIO; \ - eth_module_config[num].phy_reset_gpio = CONFIG_EXAMPLE_ETH_SPI_PHY_RST ##num## _GPIO; \ - eth_module_config[num].phy_addr = CONFIG_EXAMPLE_ETH_SPI_PHY_ADDR ##num; \ - } while(0) - -typedef struct { - uint8_t spi_cs_gpio; - uint8_t int_gpio; - int8_t phy_reset_gpio; - uint8_t phy_addr; -}spi_eth_module_config_t; -#endif - /** Event handler for Ethernet events */ static void eth_event_handler(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) @@ -94,144 +63,29 @@ static void got_ip_event_handler(void *arg, esp_event_base_t event_base, ESP_LOGI(TAG, "~~~~~~~~~~~"); } -#if CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET -/** Internal EMAC initialization */ -esp_eth_handle_t eth_init_internal(void) -{ - esp_eth_handle_t eth_handle; - - // Init MAC and PHY configs to default - eth_mac_config_t mac_config = ETH_MAC_DEFAULT_CONFIG(); - eth_phy_config_t phy_config = ETH_PHY_DEFAULT_CONFIG(); - - phy_config.phy_addr = CONFIG_EXAMPLE_ETH_PHY_ADDR; - phy_config.reset_gpio_num = CONFIG_EXAMPLE_ETH_PHY_RST_GPIO; - eth_esp32_emac_config_t esp32_emac_config = ETH_ESP32_EMAC_DEFAULT_CONFIG(); - esp32_emac_config.smi_mdc_gpio_num = CONFIG_EXAMPLE_ETH_MDC_GPIO; - esp32_emac_config.smi_mdio_gpio_num = CONFIG_EXAMPLE_ETH_MDIO_GPIO; - esp_eth_mac_t *mac = esp_eth_mac_new_esp32(&esp32_emac_config, &mac_config); -#if CONFIG_EXAMPLE_ETH_PHY_IP101 - esp_eth_phy_t *phy = esp_eth_phy_new_ip101(&phy_config); -#elif CONFIG_EXAMPLE_ETH_PHY_RTL8201 - esp_eth_phy_t *phy = esp_eth_phy_new_rtl8201(&phy_config); -#elif CONFIG_EXAMPLE_ETH_PHY_LAN87XX - esp_eth_phy_t *phy = esp_eth_phy_new_lan87xx(&phy_config); -#elif CONFIG_EXAMPLE_ETH_PHY_DP83848 - esp_eth_phy_t *phy = esp_eth_phy_new_dp83848(&phy_config); -#elif CONFIG_EXAMPLE_ETH_PHY_KSZ80XX - esp_eth_phy_t *phy = esp_eth_phy_new_ksz80xx(&phy_config); -#endif - esp_eth_config_t config = ETH_DEFAULT_CONFIG(mac, phy); - ESP_ERROR_CHECK(esp_eth_driver_install(&config, ð_handle)); - - return eth_handle; -} -#endif // CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET - -#if CONFIG_EXAMPLE_USE_SPI_ETHERNET -/** Ethernet SPI modules initialization */ -esp_eth_handle_t eth_init_spi(spi_eth_module_config_t *spi_eth_module_config, uint8_t *mac_addr) -{ - esp_eth_handle_t eth_handle; - - // Init MAC and PHY configs to default - eth_mac_config_t mac_config = ETH_MAC_DEFAULT_CONFIG(); - eth_phy_config_t phy_config = ETH_PHY_DEFAULT_CONFIG(); - - // Set module specific PHY config - phy_config.phy_addr = spi_eth_module_config->phy_addr; - phy_config.reset_gpio_num = spi_eth_module_config->phy_reset_gpio; - - // Configure SPI interface and Ethernet driver for specific SPI module - esp_eth_mac_t *mac; - esp_eth_phy_t *phy; - - spi_device_interface_config_t spi_devcfg = { - .mode = 0, - .clock_speed_hz = CONFIG_EXAMPLE_ETH_SPI_CLOCK_MHZ * 1000 * 1000, - .queue_size = 20, - .spics_io_num = spi_eth_module_config->spi_cs_gpio - }; -#if CONFIG_EXAMPLE_USE_KSZ8851SNL - eth_ksz8851snl_config_t ksz8851snl_config = ETH_KSZ8851SNL_DEFAULT_CONFIG(CONFIG_EXAMPLE_ETH_SPI_HOST, &spi_devcfg); - ksz8851snl_config.int_gpio_num = spi_eth_module_config->int_gpio; - - mac = esp_eth_mac_new_ksz8851snl(&ksz8851snl_config, &mac_config); - phy = esp_eth_phy_new_ksz8851snl(&phy_config); -#elif CONFIG_EXAMPLE_USE_DM9051 - eth_dm9051_config_t dm9051_config = ETH_DM9051_DEFAULT_CONFIG(CONFIG_EXAMPLE_ETH_SPI_HOST, &spi_devcfg); - dm9051_config.int_gpio_num = spi_eth_module_config->int_gpio; - - mac = esp_eth_mac_new_dm9051(&dm9051_config, &mac_config); - phy = esp_eth_phy_new_dm9051(&phy_config); -#elif CONFIG_EXAMPLE_USE_W5500 - eth_w5500_config_t w5500_config = ETH_W5500_DEFAULT_CONFIG(CONFIG_EXAMPLE_ETH_SPI_HOST, &spi_devcfg); - w5500_config.int_gpio_num = spi_eth_module_config->int_gpio; - - mac = esp_eth_mac_new_w5500(&w5500_config, &mac_config); - phy = esp_eth_phy_new_w5500(&phy_config); - -#endif //CONFIG_EXAMPLE_USE_W5500 - esp_eth_config_t eth_config_spi = ETH_DEFAULT_CONFIG(mac, phy); - ESP_ERROR_CHECK(esp_eth_driver_install(ð_config_spi, ð_handle)); - - // The SPI Ethernet module might not have a burned factory MAC address, we cat to set it manually. - ESP_ERROR_CHECK(esp_eth_ioctl(eth_handle, ETH_CMD_S_MAC_ADDR, mac_addr)); - - return eth_handle; -} -#endif // CONFIG_EXAMPLE_USE_SPI_ETHERNET - void app_main(void) { - // number of Ethernet ports to be used in the bridge - uint8_t port_cnt = 0; - // the same MAC address will be used for all Ethernet ports since the bridge acts as one device + // Initialize Ethernet driver + uint8_t eth_port_cnt = 0; + esp_eth_handle_t *eth_handles; + ESP_ERROR_CHECK(example_eth_init(ð_handles, ð_port_cnt)); + + // The same MAC address will be used for all Ethernet ports since the bridge acts as one device uint8_t common_mac_addr[ETH_ADDR_LEN]; + // If internal Ethernet is not supported by ESP32x SoC, Locally Administered OUI address might be returned. + // Note that Locally Administered OUI range should be used only when testing on a LAN under your control! + ESP_ERROR_CHECK(esp_read_mac(common_mac_addr, ESP_MAC_ETH)); + for (int i = 0; i < eth_port_cnt; i++) { + ESP_ERROR_CHECK(esp_eth_ioctl(eth_handles[i], ETH_CMD_S_MAC_ADDR, common_mac_addr)); + } - esp_eth_handle_t eth_handles[SPI_ETHERNETS_NUM + INTERNAL_ETHERNETS_NUM] = { NULL }; - esp_netif_t *eth_netifs[SPI_ETHERNETS_NUM + INTERNAL_ETHERNETS_NUM] = { NULL }; - - // Initialize TCP/IP network interface (should be called only once in application) + // Initialize TCP/IP network interface ESP_ERROR_CHECK(esp_netif_init()); // Create default event loop that running in background ESP_ERROR_CHECK(esp_event_loop_create_default()); -#if CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET - eth_handles[port_cnt++] = eth_init_internal(); - // use burned ESP32 MAC address as commom address for all Ethernet interfaces - ESP_ERROR_CHECK(esp_eth_ioctl(eth_handles[0], ETH_CMD_G_MAC_ADDR, common_mac_addr)); -#elif CONFIG_EXAMPLE_USE_SPI_ETHERNET - // if ESP32 internal Ethernet is not used, use manually configured MAC address - // 02:00:00 is a Locally Administered OUI range so should not be used except when testing on a LAN under your control. - memcpy(common_mac_addr, (uint8_t[]) {0x02, 0x00, 0x00, 0x12, 0x34, 0x56}, ETH_ADDR_LEN); -#endif //CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET - -#if CONFIG_EXAMPLE_USE_SPI_ETHERNET - // Install GPIO ISR handler to be able to service SPI Eth modlues interrupts - gpio_install_isr_service(0); - - // Init SPI bus - spi_bus_config_t buscfg = { - .miso_io_num = CONFIG_EXAMPLE_ETH_SPI_MISO_GPIO, - .mosi_io_num = CONFIG_EXAMPLE_ETH_SPI_MOSI_GPIO, - .sclk_io_num = CONFIG_EXAMPLE_ETH_SPI_SCLK_GPIO, - .quadwp_io_num = -1, - .quadhd_io_num = -1, - }; - ESP_ERROR_CHECK(spi_bus_initialize(CONFIG_EXAMPLE_ETH_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO)); - - // Init specific SPI Ethernet module configuration from Kconfig (CS GPIO, Interrupt GPIO, etc.) - spi_eth_module_config_t spi_eth_module_config[CONFIG_EXAMPLE_SPI_ETHERNETS_NUM]; - INIT_SPI_ETH_MODULE_CONFIG(spi_eth_module_config, 0); -#if CONFIG_EXAMPLE_SPI_ETHERNETS_NUM > 1 - INIT_SPI_ETH_MODULE_CONFIG(spi_eth_module_config, 1); -#endif - for (int i = 0; i < CONFIG_EXAMPLE_SPI_ETHERNETS_NUM; i++) { - eth_handles[port_cnt++] = eth_init_spi(&spi_eth_module_config[i], common_mac_addr); - } -#endif // CONFIG_ETH_USE_SPI_ETHERNET // Create instances of esp-netif for Ethernet ports + esp_netif_t **eth_netifs = calloc(eth_port_cnt, sizeof(esp_netif_t *)); esp_netif_inherent_config_t esp_netif_config = ESP_NETIF_INHERENT_DEFAULT_ETH(); esp_netif_config_t netif_cfg = { .base = &esp_netif_config, @@ -240,18 +94,18 @@ void app_main(void) char if_key_str[10]; char if_desc_str[10]; char num_str[3]; - for (int i = 0; i < port_cnt; i++) { + for (int i = 0; i < eth_port_cnt; i++) { itoa(i, num_str, 10); strcat(strcpy(if_key_str, "ETH_"), num_str); strcat(strcpy(if_desc_str, "eth"), num_str); esp_netif_config.if_key = if_key_str; esp_netif_config.if_desc = if_desc_str; esp_netif_config.route_prio = 50 - i; - esp_netif_config.flags = 0; // ESP-NETIF flags need to be zero when port's to be bridged + esp_netif_config.flags = 0; // esp-netif flags need to be zero when port's to be bridged eth_netifs[i] = esp_netif_new(&netif_cfg); - // attach Ethernet driver to TCP/IP stack + // Attach Ethernet driver to TCP/IP stack ESP_ERROR_CHECK(esp_netif_attach(eth_netifs[i], esp_eth_new_netif_glue(eth_handles[i]))); } @@ -265,7 +119,7 @@ void app_main(void) bridgeif_config_t bridgeif_config = { .max_fdb_dyn_entries = 10, // maximum number of address entries in dynamic forwarding database .max_fdb_sta_entries = 2, // maximum number of address entries in static forwarding database - .max_ports = port_cnt // maximum number of ports the bridge can consist of + .max_ports = eth_port_cnt // maximum number of ports the bridge can consist of }; esp_netif_br_config.bridge_info = &bridgeif_config; // Set MAC address of bridge interface the same as the Ethernet interface @@ -275,7 +129,7 @@ void app_main(void) // Create new esp netif bridge glue instance esp_netif_br_glue_handle_t netif_br_glue = esp_netif_br_glue_new(); // Add Ethernet port interfaces to that esp netif bridge glue instance - for (int i = 0; i < port_cnt; i++) { + for (int i = 0; i < eth_port_cnt; i++) { ESP_ERROR_CHECK(esp_netif_br_glue_add_port(netif_br_glue, eth_netifs[i])); } // Attach esp netif bridge glue instance with added ports to bridge netif @@ -285,7 +139,7 @@ void app_main(void) ESP_ERROR_CHECK(esp_event_handler_register(ETH_EVENT, ESP_EVENT_ANY_ID, ð_event_handler, NULL)); ESP_ERROR_CHECK(esp_event_handler_register(IP_EVENT, IP_EVENT_ETH_GOT_IP, &got_ip_event_handler, NULL)); - for (int i = 0; i < port_cnt; i++) { + for (int i = 0; i < eth_port_cnt; i++) { // Since the MAC forwarding is performed in lwIP bridge, we need to pass all addresses through the Ethernet MACs bool promiscuous = true; esp_eth_ioctl(eth_handles[i], ETH_CMD_S_PROMISCUOUS, &promiscuous); diff --git a/examples/network/simple_sniffer/CMakeLists.txt b/examples/network/simple_sniffer/CMakeLists.txt index 5097b1500a..a314a64c39 100644 --- a/examples/network/simple_sniffer/CMakeLists.txt +++ b/examples/network/simple_sniffer/CMakeLists.txt @@ -2,5 +2,7 @@ # in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.16) +set(EXTRA_COMPONENT_DIRS $ENV{IDF_PATH}/examples/ethernet/basic/components/ethernet_init) + include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(simple_sniffer) diff --git a/examples/network/simple_sniffer/README.md b/examples/network/simple_sniffer/README.md index afd98514af..addfc1950a 100644 --- a/examples/network/simple_sniffer/README.md +++ b/examples/network/simple_sniffer/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | # Simple Sniffer Example @@ -26,7 +26,7 @@ See common pin assignments for Ethernet from [ethernet examples folder](../../et ### Configure the project -Open the project configuration menu (`idf.py menuconfig`). Then go into `Example Configuration` menu. +Open the project configuration menu (`idf.py menuconfig`). Then go into `Example Configuration` in top menu. - Check `Store command history in flash` if you want to save command history into flash (recommend). - Select where to save the pcap file in `Select destination to store pcap file` menu item. @@ -38,10 +38,8 @@ Open the project configuration menu (`idf.py menuconfig`). Then go into `Example - Set the length of sniffer work queue in `Length of sniffer work queue` menu item. - Set the stack size of the sniffer task in `Stack size of sniffer task` menu item. - Set the priority of the sniffer task in `Length of sniffer work queue` menu item. -- Select Ethernet Type - - `No Ethernet` means your board does not have Ethernet. - - `Internal EMAC` means ESP32 EMAC is used in conjunction with with selected PHY. - - `DM9051 Module`, `W5500 Module` or `KSZ8851SNL Module` means that SPI-Ethernet module is used with its own EMAC and PHY. + +To configure Ethernet device(s), go to `Example Ethernet Configuration` in top menu. - For more information related to Ethernet configurations see common configuration of Ethernet from [ethernet examples folder](../../ethernet/README.md#common-configurations). ### Build and Flash diff --git a/examples/network/simple_sniffer/main/Kconfig.projbuild b/examples/network/simple_sniffer/main/Kconfig.projbuild index 92f1630b9b..2677b15366 100644 --- a/examples/network/simple_sniffer/main/Kconfig.projbuild +++ b/examples/network/simple_sniffer/main/Kconfig.projbuild @@ -87,188 +87,4 @@ menu "Example Configuration" help Priority of sniffer task. - config SNIFFER_USE_SPI_ETHERNET - bool - - choice SNIFFER_ETHERNET_TYPE - prompt "Ethernet Type" - default SNIFFER_NO_ETHERNET - help - Select which kind of Ethernet will be used in the example. - - config SNIFFER_NO_ETHERNET - bool "No Ethernet" - help - No Ethernet. - - config SNIFFER_USE_INTERNAL_ETHERNET - depends on IDF_TARGET_ESP32 - select ETH_USE_ESP32_EMAC - bool "Internal EMAC" - help - Select internal Ethernet MAC controller. - - config SNIFFER_USE_DM9051 - bool "DM9051 Module" - select SNIFFER_USE_SPI_ETHERNET - select ETH_USE_SPI_ETHERNET - select ETH_SPI_ETHERNET_DM9051 - help - Select external SPI-Ethernet module (DM9051). - - config SNIFFER_USE_W5500 - bool "W5500 Module" - select SNIFFER_USE_SPI_ETHERNET - select ETH_USE_SPI_ETHERNET - select ETH_SPI_ETHERNET_W5500 - help - Select external SPI-Ethernet module (W5500). - - config SNIFFER_USE_KSZ8851SNL - bool "KSZ8851SNL Module" - select SNIFFER_USE_SPI_ETHERNET - select ETH_USE_SPI_ETHERNET - select ETH_SPI_ETHERNET_KSZ8851SNL - help - Select external SPI-Ethernet module (KSZ8851SNL). - endchoice # SNIFFER_ETHERNET_TYPE - - if SNIFFER_USE_INTERNAL_ETHERNET - choice SNIFFER_ETH_PHY_MODEL - prompt "Ethernet PHY Device" - default SNIFFER_ETH_PHY_IP101 - help - Select the Ethernet PHY device to use in the example. - - config SNIFFER_ETH_PHY_IP101 - bool "IP101" - help - IP101 is a single port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver. - Goto http://www.icplus.com.tw/pp-IP101G.html for more information about it. - - config SNIFFER_ETH_PHY_RTL8201 - bool "RTL8201/SR8201" - help - RTL8201F/SR8201F is a single port 10/100Mb Ethernet Transceiver with auto MDIX. - Goto http://www.corechip-sz.com/productsview.asp?id=22 for more information about it. - - config SNIFFER_ETH_PHY_LAN87XX - bool "LAN87xx" - help - Below chips are supported: - LAN8710A is a small footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and - flexPWR® Technology. - LAN8720A is a small footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support. - LAN8740A/LAN8741A is a small footprint MII/RMII 10/100 Energy Efficient Ethernet Transceiver - with HP Auto-MDIX and flexPWR® Technology. - LAN8742A is a small footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and - flexPWR® Technology. - Goto https://www.microchip.com for more information about them. - - config SNIFFER_ETH_PHY_DP83848 - bool "DP83848" - help - DP83848 is a single port 10/100Mb/s Ethernet Physical Layer Transceiver. - Goto http://www.ti.com/product/DP83848J for more information about it. - - config SNIFFER_ETH_PHY_KSZ80XX - bool "KSZ80xx" - help - With the KSZ80xx series, Microchip offers single-chip 10BASE-T/100BASE-TX - Ethernet Physical Layer Tranceivers (PHY). - The following chips are supported: KSZ8001, KSZ8021, KSZ8031, KSZ8041, - KSZ8051, KSZ8061, KSZ8081, KSZ8091 - Goto https://www.microchip.com for more information about them. - endchoice # SNIFFER_ETH_PHY_MODEL - - config SNIFFER_ETH_MDC_GPIO - int "SMI MDC GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 23 - help - Set the GPIO number used by SMI MDC. - - config SNIFFER_ETH_MDIO_GPIO - int "SMI MDIO GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 18 - help - Set the GPIO number used by SMI MDIO. - endif # SNIFFER_USE_INTERNAL_ETHERNET - - if SNIFFER_USE_SPI_ETHERNET - config SNIFFER_ETH_SPI_HOST - int "SPI Host Number" - range 0 2 - default 1 - help - Set the SPI host used to communicate with the SPI Ethernet Controller. - - config SNIFFER_ETH_SPI_SCLK_GPIO - int "SPI SCLK GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 14 if IDF_TARGET_ESP32 - default 12 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 - default 6 if IDF_TARGET_ESP32C3 - help - Set the GPIO number used by SPI SCLK. - - config SNIFFER_ETH_SPI_MOSI_GPIO - int "SPI MOSI GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 13 if IDF_TARGET_ESP32 - default 11 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 - default 7 if IDF_TARGET_ESP32C3 - help - Set the GPIO number used by SPI MOSI. - - config SNIFFER_ETH_SPI_MISO_GPIO - int "SPI MISO GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX - default 12 if IDF_TARGET_ESP32 - default 13 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 - default 2 if IDF_TARGET_ESP32C3 - help - Set the GPIO number used by SPI MISO. - - config SNIFFER_ETH_SPI_CS_GPIO - int "SPI CS GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 15 if IDF_TARGET_ESP32 - default 10 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 - help - Set the GPIO number used by SPI CS. - - config SNIFFER_ETH_SPI_CLOCK_MHZ - int "SPI clock speed (MHz)" - range 5 80 - default 12 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32C3 - default 36 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 - help - Set the clock speed (MHz) of SPI interface. - - config SNIFFER_ETH_SPI_INT_GPIO - int "Interrupt GPIO number" - range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX - default 4 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 - help - Set the GPIO number used by the SPI Ethernet module interrupt line. - endif # SNIFFER_USE_SPI_ETHERNET - - if !SNIFFER_NO_ETHERNET - config SNIFFER_ETH_PHY_RST_GPIO - int "PHY Reset GPIO number" - range -1 ENV_GPIO_OUT_RANGE_MAX - default 5 - help - Set the GPIO number used to reset PHY chip. - Set to -1 to disable PHY chip hardware reset. - - config SNIFFER_ETH_PHY_ADDR - int "PHY Address" - range 0 31 - default 1 - help - Set PHY address according your board schematic. - endif # !SNIFFER_NO_ETHERNET endmenu diff --git a/examples/network/simple_sniffer/main/cmd_sniffer.c b/examples/network/simple_sniffer/main/cmd_sniffer.c index 01f6ec1e82..31b1aad800 100644 --- a/examples/network/simple_sniffer/main/cmd_sniffer.c +++ b/examples/network/simple_sniffer/main/cmd_sniffer.c @@ -373,11 +373,11 @@ static int do_sniffer_cmd(int argc, char **argv) snf_rt.interf = SNIFFER_INTF_ETH; snf_rt.interf_num = eth_intf_num; } else { - ESP_LOGE(SNIFFER_TAG, "unsupported interface %s", sniffer_args.interface->sval[0]); + ESP_LOGE(SNIFFER_TAG, "interface %s not found", sniffer_args.interface->sval[0]); return 1; } } else { - ESP_LOGE(SNIFFER_TAG, "unsupported interface %s", sniffer_args.interface->sval[0]); + ESP_LOGE(SNIFFER_TAG, "interface %s not found", sniffer_args.interface->sval[0]); return 1; } } else { diff --git a/examples/network/simple_sniffer/main/simple_sniffer_example_main.c b/examples/network/simple_sniffer/main/simple_sniffer_example_main.c index ee0c6efa18..ce4cdd8741 100644 --- a/examples/network/simple_sniffer/main/simple_sniffer_example_main.c +++ b/examples/network/simple_sniffer/main/simple_sniffer_example_main.c @@ -16,6 +16,7 @@ #include "esp_event.h" #include "esp_vfs_fat.h" #include "esp_wifi.h" +#include "ethernet_init.h" #include "esp_err.h" #include "esp_log.h" #if CONFIG_SNIFFER_PCAP_DESTINATION_SD @@ -27,9 +28,6 @@ #include "sdmmc_cmd.h" #include "cmd_sniffer.h" #include "cmd_pcap.h" -#if CONFIG_ETH_USE_SPI_ETHERNET -#include "driver/spi_master.h" -#endif // CONFIG_ETH_USE_SPI_ETHERNET #if CONFIG_SNIFFER_STORE_HISTORY #define HISTORY_MOUNT_POINT "/data" @@ -91,7 +89,6 @@ static void initialize_wifi(void) ESP_ERROR_CHECK(esp_wifi_set_mode(WIFI_MODE_NULL)); } -#ifndef CONFIG_SNIFFER_NO_ETHERNET /** Event handler for Ethernet events */ static void eth_event_handler(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) @@ -127,80 +124,23 @@ static void eth_event_handler(void *arg, esp_event_base_t event_base, static void initialize_eth(void) { - // Register user defined event handers - ESP_ERROR_CHECK(esp_event_handler_register(ETH_EVENT, ESP_EVENT_ANY_ID, ð_event_handler, NULL)); + // Initialize Ethernet driver + uint8_t eth_port_cnt = 0; + esp_eth_handle_t *eth_handles; + ESP_ERROR_CHECK(example_eth_init(ð_handles, ð_port_cnt)); - eth_mac_config_t mac_config = ETH_MAC_DEFAULT_CONFIG(); - eth_phy_config_t phy_config = ETH_PHY_DEFAULT_CONFIG(); - phy_config.phy_addr = CONFIG_SNIFFER_ETH_PHY_ADDR; - phy_config.reset_gpio_num = CONFIG_SNIFFER_ETH_PHY_RST_GPIO; -#if CONFIG_SNIFFER_USE_INTERNAL_ETHERNET - eth_esp32_emac_config_t esp32_emac_config = ETH_ESP32_EMAC_DEFAULT_CONFIG(); - esp32_emac_config.smi_mdc_gpio_num = CONFIG_SNIFFER_ETH_MDC_GPIO; - esp32_emac_config.smi_mdio_gpio_num = CONFIG_SNIFFER_ETH_MDIO_GPIO; - esp_eth_mac_t *mac = esp_eth_mac_new_esp32(&esp32_emac_config, &mac_config); -#if CONFIG_SNIFFER_ETH_PHY_IP101 - esp_eth_phy_t *phy = esp_eth_phy_new_ip101(&phy_config); -#elif CONFIG_SNIFFER_ETH_PHY_RTL8201 - esp_eth_phy_t *phy = esp_eth_phy_new_rtl8201(&phy_config); -#elif CONFIG_SNIFFER_ETH_PHY_LAN87XX - esp_eth_phy_t *phy = esp_eth_phy_new_lan87xx(&phy_config); -#elif CONFIG_SNIFFER_ETH_PHY_DP83848 - esp_eth_phy_t *phy = esp_eth_phy_new_dp83848(&phy_config); -#elif CONFIG_SNIFFER_ETH_PHY_KSZ80XX - esp_eth_phy_t *phy = esp_eth_phy_new_ksz80xx(&phy_config); -#endif -#elif CONFIG_ETH_USE_SPI_ETHERNET - gpio_install_isr_service(0); - spi_bus_config_t buscfg = { - .miso_io_num = CONFIG_SNIFFER_ETH_SPI_MISO_GPIO, - .mosi_io_num = CONFIG_SNIFFER_ETH_SPI_MOSI_GPIO, - .sclk_io_num = CONFIG_SNIFFER_ETH_SPI_SCLK_GPIO, - .quadwp_io_num = -1, - .quadhd_io_num = -1, - }; - ESP_ERROR_CHECK(spi_bus_initialize(CONFIG_SNIFFER_ETH_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO)); - spi_device_interface_config_t spi_devcfg = { - .mode = 0, - .clock_speed_hz = CONFIG_SNIFFER_ETH_SPI_CLOCK_MHZ * 1000 * 1000, - .spics_io_num = CONFIG_SNIFFER_ETH_SPI_CS_GPIO, - .queue_size = 20 - }; -#if CONFIG_SNIFFER_USE_KSZ8851SNL - eth_ksz8851snl_config_t ksz8851snl_config = ETH_KSZ8851SNL_DEFAULT_CONFIG(CONFIG_SNIFFER_ETH_SPI_HOST, &spi_devcfg); - ksz8851snl_config.int_gpio_num = CONFIG_SNIFFER_ETH_SPI_INT_GPIO; - esp_eth_mac_t *mac = esp_eth_mac_new_ksz8851snl(&ksz8851snl_config, &mac_config); - esp_eth_phy_t *phy = esp_eth_phy_new_ksz8851snl(&phy_config); -#elif CONFIG_SNIFFER_USE_DM9051 - eth_dm9051_config_t dm9051_config = ETH_DM9051_DEFAULT_CONFIG(CONFIG_SNIFFER_ETH_SPI_HOST, &spi_devcfg); - dm9051_config.int_gpio_num = CONFIG_SNIFFER_ETH_SPI_INT_GPIO; - esp_eth_mac_t *mac = esp_eth_mac_new_dm9051(&dm9051_config, &mac_config); - esp_eth_phy_t *phy = esp_eth_phy_new_dm9051(&phy_config); -#elif CONFIG_SNIFFER_USE_W5500 - eth_w5500_config_t w5500_config = ETH_W5500_DEFAULT_CONFIG(CONFIG_SNIFFER_ETH_SPI_HOST, &spi_devcfg); - w5500_config.int_gpio_num = CONFIG_SNIFFER_ETH_SPI_INT_GPIO; - esp_eth_mac_t *mac = esp_eth_mac_new_w5500(&w5500_config, &mac_config); - esp_eth_phy_t *phy = esp_eth_phy_new_w5500(&phy_config); -#endif -#endif // CONFIG_ETH_USE_SPI_ETHERNET - esp_eth_config_t config = ETH_DEFAULT_CONFIG(mac, phy); - esp_eth_handle_t eth_handle = NULL; - ESP_ERROR_CHECK(esp_eth_driver_install(&config, ð_handle)); -#if !CONFIG_SNIFFER_USE_INTERNAL_ETHERNET - /* The SPI Ethernet module might doesn't have a burned factory MAC address, we cat to set it manually. - 02:00:00 is a Locally Administered OUI range so should not be used except when testing on a LAN under your control. - */ - ESP_ERROR_CHECK(esp_eth_ioctl(eth_handle, ETH_CMD_S_MAC_ADDR, (uint8_t[]) { - 0x02, 0x00, 0x00, 0x12, 0x34, 0x56 - })); -#endif - /* start Ethernet driver state machine */ - ESP_ERROR_CHECK(esp_eth_start(eth_handle)); + if (eth_port_cnt > 0) { + // Register user defined event handers + ESP_ERROR_CHECK(esp_event_handler_register(ETH_EVENT, ESP_EVENT_ANY_ID, ð_event_handler, NULL)); - /* Register Ethernet interface to could be used by sniffer */ - ESP_ERROR_CHECK(sniffer_reg_eth_intf(eth_handle)); + for (uint32_t i = 0; i < eth_port_cnt; i++) { + /* start Ethernet driver state machine */ + ESP_ERROR_CHECK(esp_eth_start(eth_handles[i])); + /* Register Ethernet interface to could be used by sniffer */ + ESP_ERROR_CHECK(sniffer_reg_eth_intf(eth_handles[i])); + } + } } -#endif // CONFIG_SNIFFER_NO_ETHERNET #if CONFIG_SNIFFER_PCAP_DESTINATION_SD static struct { @@ -341,10 +281,8 @@ void app_main(void) ESP_ERROR_CHECK(esp_event_loop_create_default()); /* Initialize WiFi */ initialize_wifi(); -#ifndef CONFIG_SNIFFER_NO_ETHERNET /* Initialize Ethernet */ initialize_eth(); -#endif /*--- Initialize Console ---*/ esp_console_repl_t *repl = NULL; diff --git a/examples/network/simple_sniffer/sdkconfig.defaults b/examples/network/simple_sniffer/sdkconfig.defaults index ee62d2d43d..a190affdc5 100644 --- a/examples/network/simple_sniffer/sdkconfig.defaults +++ b/examples/network/simple_sniffer/sdkconfig.defaults @@ -19,3 +19,7 @@ CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y # FatFS CONFIG_FATFS_LFN_HEAP=y CONFIG_FATFS_MAX_LFN=31 + +# Network Interfaces +CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET=n +CONFIG_EXAMPLE_USE_SPI_ETHERNET=n diff --git a/examples/network/vlan_support/CMakeLists.txt b/examples/network/vlan_support/CMakeLists.txt new file mode 100644 index 0000000000..4ed01ae191 --- /dev/null +++ b/examples/network/vlan_support/CMakeLists.txt @@ -0,0 +1,20 @@ +# For more information about build system see +# https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/build-system.html +# The following five lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +set(EXTRA_COMPONENT_DIRS $ENV{IDF_PATH}/examples/ethernet/basic/components/ethernet_init) +include($ENV{IDF_PATH}/tools/cmake/project.cmake) + +project(vlan_support) + + +# Enabling Vlan by injecting vlan hooks into lwip. +idf_component_get_property(lwip lwip COMPONENT_LIB) +target_compile_options(${lwip} PRIVATE "-I${PROJECT_DIR}/main") + +target_compile_definitions(${lwip} PRIVATE "-DESP_IDF_LWIP_HOOK_FILENAME=\"vlan_hooks.h\"" + "-DETHARP_SUPPORT_VLAN=1" + "-DLWIP_HOOK_VLAN_CHECK=lwip_vlan_check" + "-DLWIP_HOOK_VLAN_SET=lwip_vlan_set") diff --git a/examples/network/vlan_support/README.md b/examples/network/vlan_support/README.md new file mode 100644 index 0000000000..6177d7b935 --- /dev/null +++ b/examples/network/vlan_support/README.md @@ -0,0 +1,114 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | + +# Ethernet VLAN Support Example + +See the [README.md](../../ethernet/README.md) file in the upper level [examples](../../ethernet) directory for more information about examples. + +## Overview + +This example demonstrates the creation of one virtual network interface over Ethernet, an additional VLAN interface(disabled by default), and an interface without vlan tag. The work flow of the example could be as follows: + +1. Install Ethernet driver for standard interface and both the virtual network interface. +2. Setup static IP address to both the virtual network interface. +3. Send DHCP requests and wait for a DHCP lease on the standard interface +4. If get IP address successfully, then you will be able to ping the standard interface of the device. +5. The virtual interfaces can be pinged over the configured static IP address. + +Note: The code in vlan_support_main.c can be modified to add more vlan interfaces. The maximum number of interfaces that can be added is specified by the macro `MAX_ETH_NETIF_COUNT`. +## How to use example + +### Hardware Required + +To run this example, it's recommended that you have an official ESP32 Ethernet development board - [ESP32-Ethernet-Kit](https://docs.espressif.com/projects/esp-idf/en/latest/hw-reference/get-started-ethernet-kit.html). This example should also work for 3rd party ESP32 board as long as it's integrated with a supported Ethernet PHY chip. + +### Configure the project + +``` +idf.py menuconfig +``` +See common configurations for Ethernet examples from [upper level](../../ethernet/README.md#common-configurations). + +The Virtual network interface is enabled by default. +An additional virtual network interface can also be enabled. +The VLAN tag, Static IP address, network mask and default gateway of these interfaces are also configurable. + +To configure the virtual network interfaces select: +``` +Example Configuration ---> +``` + +### Build, Flash, and Run + +Build the project and flash it to the board, then run monitor tool to view serial output: + +``` +idf.py -p PORT build flash monitor +``` + +(Replace PORT with the name of the serial port to use.) + +(To exit the serial monitor, type ``Ctrl-]``.) + +See the [Getting Started Guide](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/index.html) for full steps to configure and use ESP-IDF to build projects. + +## Example Output + +``` +I (0) cpu_start: Starting scheduler on APP CPU. +I (423) system_api: Base MAC address is not set +I (423) system_api: read default base MAC address from EFUSE +I (443) esp_eth.netif.netif_glue: 24:d7:eb:bb:f2:1b +I (443) esp_eth.netif.netif_glue: ethernet attached to netif +I (443) esp_eth.netif.netif_glue: 24:d7:eb:bb:f2:1b +I (443) esp_eth.netif.netif_glue: ethernet attached to netif +I (453) esp_eth.netif.netif_glue: 24:d7:eb:bb:f2:1b +I (463) esp_eth.netif.netif_glue: ethernet attached to netif +I (3563) eth_vlan_example: Ethernet Started +I (3563) eth_vlan_example: Ethernet Link Up +I (3563) eth_vlan_example: Ethernet HW Addr 24:d7:eb:bb:f2:1b +I (3563) eth_vlan_example: Ethernet interface(24:d7:eb:bb:f2:1b): ETH_VLAN20, Got IP Address +I (3573) eth_vlan_example: ~~~~~~~~~~~ +I (3573) eth_vlan_example: ETHIP:192.168.20.10 +I (3583) eth_vlan_example: ETHMASK:192.168.20.1 +I (3583) eth_vlan_example: ETHGW:255.255.255.0 +I (3593) eth_vlan_example: ~~~~~~~~~~~ +I (3593) esp_netif_handlers: eth ip: 192.168.20.10, mask: 192.168.20.1, gw: 255.255.255.0 +I (3603) eth_vlan_example: Ethernet interface(24:d7:eb:bb:f2:1b): ETH_VLAN30, Got IP Address +I (3613) eth_vlan_example: ~~~~~~~~~~~ +I (3623) eth_vlan_example: ETHIP:192.168.30.10 +I (3623) eth_vlan_example: ETHMASK:192.168.30.1 +I (3633) eth_vlan_example: ETHGW:255.255.255.0 +I (3633) eth_vlan_example: ~~~~~~~~~~~ +I (3643) esp_netif_handlers: eth ip: 192.168.30.10, mask: 192.168.30.1, gw: 255.255.255.0 +I (7943) eth_vlan_example: Ethernet interface(24:d7:eb:bb:f2:1b): ETH_DEF, Got IP Address +I (7943) eth_vlan_example: ~~~~~~~~~~~ +I (7943) eth_vlan_example: ETHIP:192.168.10.100 +I (7943) eth_vlan_example: ETHMASK:255.255.255.0 +I (7953) eth_vlan_example: ETHGW:192.168.10.1 +I (7953) eth_vlan_example: ~~~~~~~~~~~ +I (7963) esp_netif_handlers: eth ip: 192.168.10.100, mask: 255.255.255.0, gw: 192.168.10.1 +``` + +Now you can ping your ESP32 in the terminal. +You can ping the ESP32 VLAN interface from the VLAN interface of your system with default VLAN tag 20. + +## Troubleshooting +### Setup VLAN on Linux +``` +vconfig add eth0 20 +ip addr add 192.168.20.30/24 dev eth0.20 +ip link set eth0.20 up +``` +Replace interface eth0 with your system ethernet interface. +### Setup VLAN on Mac +``` +sudo ifconfig vlan20 create +sudo ifconfig vlan20 vlan 20 vlandev en5 +sudo ifconfig vlan20 inet 192.168.20.30 netmask 255.255.255.0 +``` +Replace interface en5 with your system ethernet interface. + +See common troubleshooting for Ethernet examples from [upper level](../../ethernet/README.md#common-troubleshooting). + +(For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you as soon as possible.) diff --git a/examples/network/vlan_support/main/CMakeLists.txt b/examples/network/vlan_support/main/CMakeLists.txt new file mode 100644 index 0000000000..ab2281f9d9 --- /dev/null +++ b/examples/network/vlan_support/main/CMakeLists.txt @@ -0,0 +1,2 @@ +idf_component_register(SRCS "vlan_support_main.c" "eth_vlan_utils.c" + INCLUDE_DIRS ".") diff --git a/examples/network/vlan_support/main/Kconfig.projbuild b/examples/network/vlan_support/main/Kconfig.projbuild new file mode 100644 index 0000000000..aa2ad4903f --- /dev/null +++ b/examples/network/vlan_support/main/Kconfig.projbuild @@ -0,0 +1,60 @@ +menu "Example Configuration" + + comment "Virtual Ethernet Interface Configuration" + + config EXAMPLE_ETHERNET_VLAN_ID + int "VLAN identifier" + range 1 4094 + default 20 + help + Set the VLAN Id to the virtual interface + + config EXAMPLE_VLAN_STATIC_IPV4_ADDR + string "IPV4 Address" + default "192.168.20.10" + help + The example will set this IPV4 address to this interface. + + config EXAMPLE_VLAN_STATIC_ADDR_MASK + string "Subnet Mask" + default "255.255.255.0" + + config EXAMPLE_VLAN_STATIC_ADDR_DEF_GW + string "IPV4 Default Gateway" + default "192.168.20.1" + + config EXAMPLE_EXTRA_VLAN_INTERFACE + bool "Additional Vlan Interface" + default n + help + Enables an additional VLAN interface + + if EXAMPLE_EXTRA_VLAN_INTERFACE + config EXAMPLE_EXTRA_ETHERNET_VLAN_ID + int "VLAN identifier" + range 1 4094 + default 30 + depends on EXAMPLE_EXTRA_VLAN_INTERFACE + help + Set the VLAN Id to the additional virtual interface + + config EXAMPLE_EXTRA_VLAN_STATIC_IPV4_ADDR + string "IPV4 Address" + default "192.168.30.10" + depends on EXAMPLE_EXTRA_VLAN_INTERFACE + help + The example will set this IPV4 address to this interface. + + config EXAMPLE_EXTRA_VLAN_STATIC_ADDR_MASK + string "Subnet Mask" + default "255.255.255.0" + depends on EXAMPLE_EXTRA_VLAN_INTERFACE + + config EXAMPLE_EXTRA_VLAN_STATIC_ADDR_DEF_GW + string "IPV4 Default Gateway" + default "192.168.30.1" + depends on EXAMPLE_EXTRA_VLAN_INTERFACE + + endif #EXAMPLE_EXTRA_VLAN_INTERFACE + +endmenu diff --git a/examples/network/vlan_support/main/eth_vlan_utils.c b/examples/network/vlan_support/main/eth_vlan_utils.c new file mode 100644 index 0000000000..49ad7cb38e --- /dev/null +++ b/examples/network/vlan_support/main/eth_vlan_utils.c @@ -0,0 +1,113 @@ +/* + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "esp_netif.h" +#include "esp_eth_netif_glue.h" +#include "esp_netif_net_stack.h" +#include "esp_event.h" +#include "esp_log.h" +#include "esp_check.h" +#include "lwip/esp_netif_net_stack.h" +#include "sdkconfig.h" +#include "lwip/prot/ethernet.h" +#include "lwip/prot/ieee.h" +#include "eth_vlan_utils.h" +#if CONFIG_ESP_NETIF_L2_TAP +#include "esp_vfs_l2tap.h" +#endif + + +/** + * @brief This function gets invoked when Ethernet receive a new packets. + * + * @note This function is to be registered as a callback function which get invoked when Ethernet receive a new packets. + * + * @param eth_handle handle of Ethernet driver + * @param buffer buffer of the received packet + * @param length length of the received packet + * @param priv private pointer + * + * @return + * - ESP_OK: input frame buffer to upper stack successfully + * - ESP_FAIL: error occurred when inputting buffer to upper stack + */ +esp_err_t eth_input_to_netif(esp_eth_handle_t eth_handle, uint8_t *buffer, uint32_t length, void *priv) +{ + struct netif *lwip_netif; + u16_t netif_vlan_id; + struct eth_hdr *ethhdr = (struct eth_hdr *)buffer; + struct eth_vlan_hdr *vlan; + esp_vlan_netifs *vlan_netifs = (esp_vlan_netifs *)priv; + + if (PP_HTONS(ETHTYPE_VLAN) != ethhdr->type) { + // L2 tap after VLAN is not supported. +#if CONFIG_ESP_NETIF_L2_TAP + esp_err_t ret = ESP_OK; + ret = esp_vfs_l2tap_eth_filter(eth_handle, buffer, (size_t *)&length); + if (length == 0) { + return ret; + } +#endif + return esp_netif_receive(vlan_netifs->esp_netif[0], buffer, length, NULL); + } else { + for (int i = 1; i < vlan_netifs->netif_count; i++) { + lwip_netif = esp_netif_get_netif_impl(vlan_netifs->esp_netif[i]); + netif_vlan_id = *((uint16_t *)netif_get_client_data(lwip_netif, LWIP_NETIF_CLIENT_DATA_INDEX_MAX + 1)); + + vlan = (struct eth_vlan_hdr *)(((char *)ethhdr) + SIZEOF_ETH_HDR); + + if (VLAN_ID(vlan) == netif_vlan_id) { + return esp_netif_receive(vlan_netifs->esp_netif[i], buffer, length, NULL); + } + } + + // If the vlan id of the incoming frame doesn't match with any of the interface send it to the default interface. + return esp_netif_receive(vlan_netifs->esp_netif[0], buffer, length, NULL); + } +} + + +/** + * @brief This function creates configuration for esp-netif Ethernet + * + * @param vlan_id handle of Ethernet driver, used to name the interface key. + * @param vlan_eth_cfg_o output parameter returning the esp-netif ethernet configuration. + * + * @return ESP_OK or ESP_FAIL + */ +esp_err_t get_vlan_netif_config(uint16_t vlan_id, esp_netif_config_t *vlan_eth_cfg_o) +{ + // Create new default instance of VLAN esp-netif for Ethernet + char *if_key; + if (asprintf(&if_key, "ETH_VLAN%d", vlan_id) == -1) { + return ESP_FAIL; + } + + esp_netif_inherent_config_t *esp_eth_vlan_base_config = malloc(sizeof(esp_netif_inherent_config_t)); + if (NULL == esp_eth_vlan_base_config) { + return ESP_FAIL; + } + *esp_eth_vlan_base_config = (esp_netif_inherent_config_t)ESP_NETIF_INHERENT_DEFAULT_ETH(); + esp_eth_vlan_base_config->if_key = if_key; + + vlan_eth_cfg_o->base = esp_eth_vlan_base_config; + vlan_eth_cfg_o->driver = NULL; + vlan_eth_cfg_o->stack = ESP_NETIF_NETSTACK_DEFAULT_ETH; + + return ESP_OK; +} + +/** + * @brief This function frees the memory allocated for configuration for esp-netif Ethernet + * + * @param vlan_eth_cfg configuration for esp-netif Ethernet + */ +void free_vlan_config(esp_netif_config_t *vlan_eth_cfg) +{ + if ((NULL != vlan_eth_cfg) && (NULL != vlan_eth_cfg->base)) { + free((void *)(vlan_eth_cfg->base->if_key)); + free((void *)(vlan_eth_cfg->base)); + } +} diff --git a/examples/network/vlan_support/main/eth_vlan_utils.h b/examples/network/vlan_support/main/eth_vlan_utils.h new file mode 100644 index 0000000000..43ebbedb08 --- /dev/null +++ b/examples/network/vlan_support/main/eth_vlan_utils.h @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + + +// Maximum number of interface that can be added +#define MAX_ETH_NETIF_COUNT (10) + +typedef struct { + esp_netif_t *esp_netif[MAX_ETH_NETIF_COUNT]; + uint8_t netif_count; +} esp_vlan_netifs; + + +/** + * @brief This function gets invoked when Ethernet receive a new packets. + * + * @note This function is to be registered as a callback function which get invoked when Ethernet receive a new packets. + * + * @param eth_handle handle of Ethernet driver + * @param buffer buffer of the received packet + * @param length length of the received packet + * @param priv private pointer + * + * @return + * - ESP_OK: input frame buffer to upper stack successfully + * - ESP_FAIL: error occurred when inputting buffer to upper stack + */ +esp_err_t eth_input_to_netif(esp_eth_handle_t eth_handle, uint8_t *buffer, uint32_t length, void *priv); + + +/** + * @brief This function creates configuration for esp-netif Ethernet + * + * @param vlan_id handle of Ethernet driver, used to name the interface key. + * @param vlan_eth_cfg_o output parameter returning the esp-netif ethernet configuration. + * + * @return ESP_OK or ESP_FAIL + */ +esp_err_t get_vlan_netif_config(uint16_t vlan_id, esp_netif_config_t *vlan_eth_cfg_o); + + +/** + * @brief This function frees the memory allocated for configuration for esp-netif Ethernet + * + * @param vlan_eth_cfg configuration for esp-netif Ethernet + */ +void free_vlan_config(esp_netif_config_t *vlan_eth_cfg); diff --git a/examples/network/vlan_support/main/vlan_hooks.h b/examples/network/vlan_support/main/vlan_hooks.h new file mode 100644 index 0000000000..eb97125c6a --- /dev/null +++ b/examples/network/vlan_support/main/vlan_hooks.h @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#include "lwip/netif.h" +#include "lwip/pbuf.h" +#include "lwip/prot/ethernet.h" + +/** + * @brief Returns the custom data stored in the supplied `netif` struct representing its vlan tag + * + * @param netif The lwIP network interface on which to send the packet + * @param p The packet to send. pbuf layer must be @ref PBUF_LINK. + * @param src The source MAC address to be copied into the ethernet header + * @param dst The destination MAC address to be copied into the ethernet header + * @param eth_type Ethernet type (@ref lwip_ieee_eth_type) + * + * @return Returns the vlan tag of the interface or -1. + */ +static inline int lwip_vlan_set(struct netif *netif, struct pbuf *p, + const struct eth_addr *src, const struct eth_addr *dst, + u16_t eth_type) +{ + u16_t vlan_id = *((uint16_t *)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_MAX + 1)); + + if (0xFFF == vlan_id) { + return -1; + } else { + return vlan_id; + } +} + +/** + * @brief Checks if the vlan tag in the frame matches the vlan tag of the interface. + * + * @param netif: struct netif on which the packet has been received + * @param eth_hdr: struct eth_hdr of the packet + * @param vlan_hdr: struct eth_vlan_hdr of the packet + * + * @return Returns true if the vlan tag in the frame matches the vlan tag of the interface, else returns false. + */ +static inline bool lwip_vlan_check(struct netif *netif, struct eth_hdr *eth_hdr, struct eth_vlan_hdr *vlan_hdr) +{ + u16_t vlan_id = *((uint16_t *)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_MAX + 1)); + + if (vlan_id == VLAN_ID(vlan_hdr)) { + return true; + } + + return false; +} diff --git a/examples/network/vlan_support/main/vlan_support_main.c b/examples/network/vlan_support/main/vlan_support_main.c new file mode 100644 index 0000000000..bae06eeec8 --- /dev/null +++ b/examples/network/vlan_support/main/vlan_support_main.c @@ -0,0 +1,196 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +/* Ethernet Basic Example with an additional VLAN interface. */ +#include +#include +#include +#include "esp_netif.h" +#include "esp_eth.h" +#include "ethernet_init.h" +#include "esp_event.h" +#include "esp_log.h" +#include "eth_vlan_utils.h" +#include "sdkconfig.h" +#include "lwip/prot/ethernet.h" +#include "lwip/prot/ieee.h" +#include "esp_netif_net_stack.h" + + +static const char *TAG = "eth_vlan_example"; + +/** + * @brief Event handler for Ethernet events + * + * @note This function is not required for core functionality. + * + * @param arg + * @param event_base the base ID of the event to register the handler for + * @param event_id the ID of the event with which to unregister the handler + * @param event_data the data, specific to the event occurrence, that gets passed to the handler + */ +void eth_event_handler(void *arg, esp_event_base_t event_base, + int32_t event_id, void *event_data) +{ + uint8_t mac_addr[6] = {0}; + /* we can get the ethernet driver handle from event data */ + esp_eth_handle_t eth_handle = *(esp_eth_handle_t *)event_data; + + switch (event_id) { + case ETHERNET_EVENT_CONNECTED: + esp_eth_ioctl(eth_handle, ETH_CMD_G_MAC_ADDR, mac_addr); + ESP_LOGI(TAG, "Ethernet Link Up"); + ESP_LOGI(TAG, "Ethernet HW Addr %02x:%02x:%02x:%02x:%02x:%02x", + mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]); + break; + case ETHERNET_EVENT_DISCONNECTED: + ESP_LOGI(TAG, "Ethernet Link Down"); + break; + case ETHERNET_EVENT_START: + ESP_LOGI(TAG, "Ethernet Started"); + break; + case ETHERNET_EVENT_STOP: + ESP_LOGI(TAG, "Ethernet Stopped"); + break; + default: + ESP_LOGI(TAG, "Default Event"); + break; + } +} + + +/** + * @brief Event handler for IP_EVENT_ETH_GOT_IP + * + * @note This function is not required for core functionality. + * + * @param arg + * @param event_base the base ID of the event to register the handler for + * @param event_id the ID of the event with which to unregister the handler + * @param event_data the data, specific to the event occurrence, that gets passed to the handler + */ +void got_ip_event_handler(void *arg, esp_event_base_t event_base, + int32_t event_id, void *event_data) +{ + ip_event_got_ip_t *event = (ip_event_got_ip_t *) event_data; + const esp_netif_ip_info_t *ip_info = &event->ip_info; + u8_t hwaddr[NETIF_MAX_HWADDR_LEN]; + + esp_netif_get_mac(event->esp_netif, hwaddr); + ESP_LOGI(TAG, "Ethernet interface(%"X8_F":%"X8_F":%"X8_F":%"X8_F":%"X8_F":%"X8_F"): %s, Got IP Address", + hwaddr[0], hwaddr[1], hwaddr[2], hwaddr[3], hwaddr[4], hwaddr[5], esp_netif_get_ifkey(event->esp_netif)); + ESP_LOGI(TAG, "~~~~~~~~~~~"); + ESP_LOGI(TAG, "ETHIP:" IPSTR, IP2STR(&ip_info->ip)); + ESP_LOGI(TAG, "ETHMASK:" IPSTR, IP2STR(&ip_info->netmask)); + ESP_LOGI(TAG, "ETHGW:" IPSTR, IP2STR(&ip_info->gw)); + ESP_LOGI(TAG, "~~~~~~~~~~~"); +} + + +void app_main(void) +{ + static esp_vlan_netifs vlan_netif_list; + + // Initialize Ethernet driver + uint8_t eth_port_cnt = 0; + esp_eth_handle_t *eth_handle; + ESP_ERROR_CHECK(example_eth_init(ð_handle, ð_port_cnt)); + + // Check or multiple ethernet interface + if (1 < eth_port_cnt) { + ESP_LOGW(TAG, "Multiple Ethernet Interface detected: Only the first initialized interface is going to be used."); + } + + // Initialize TCP/IP network interface (should be called only once in application) + ESP_ERROR_CHECK(esp_netif_init()); + + // Create default event loop that running in background + ESP_ERROR_CHECK(esp_event_loop_create_default()); + + // Register user defined event handers + ESP_ERROR_CHECK(esp_event_handler_register(ETH_EVENT, ESP_EVENT_ANY_ID, ð_event_handler, NULL)); + ESP_ERROR_CHECK(esp_event_handler_register(IP_EVENT, IP_EVENT_ETH_GOT_IP, &got_ip_event_handler, NULL)); + + static uint16_t vlan_id[MAX_ETH_NETIF_COUNT]; + vlan_netif_list.netif_count = 0; + + // Create new default instance of default esp-netif for Ethernet. + // vlan_netif_list.esp_netif[0] must be used as default esp-netif for Ethernet, + // and all untagged and unsupported tagged frames will go to this interface. + esp_netif_config_t eth_cfg = ESP_NETIF_DEFAULT_ETH(); + vlan_netif_list.esp_netif[vlan_netif_list.netif_count] = esp_netif_new(ð_cfg); + + // Attach Ethernet drivers to TCP/IP stack + esp_eth_netif_glue_handle_t eth_glue = esp_eth_new_netif_glue(eth_handle[0]); + ESP_ERROR_CHECK(esp_netif_attach(vlan_netif_list.esp_netif[vlan_netif_list.netif_count], eth_glue)); + + // Set VLAN tag in data of lwip netif. + // VLAN tag 0xFFF can be used to indicate a wildcard match in management operations or filtering database entries. + vlan_id[vlan_netif_list.netif_count] = 0xFFF; + struct netif *lwip_netif = esp_netif_get_netif_impl(vlan_netif_list.esp_netif[vlan_netif_list.netif_count]); + netif_set_client_data(lwip_netif, LWIP_NETIF_CLIENT_DATA_INDEX_MAX + 1, (void *)&vlan_id[vlan_netif_list.netif_count]); + vlan_netif_list.netif_count++; + + + // Create new instance of esp-netif for Ethernet vlan interface + esp_netif_config_t vlan_eth_cfg; + ESP_ERROR_CHECK(get_vlan_netif_config(CONFIG_EXAMPLE_ETHERNET_VLAN_ID, &vlan_eth_cfg)); + vlan_netif_list.esp_netif[vlan_netif_list.netif_count] = esp_netif_new(&vlan_eth_cfg); + free_vlan_config(&vlan_eth_cfg); + + // Attach vlan Ethernet drivers to TCP/IP stack + esp_eth_netif_glue_handle_t vlan_glue = esp_eth_new_netif_glue(eth_handle[0]); + ESP_ERROR_CHECK(esp_netif_attach(vlan_netif_list.esp_netif[vlan_netif_list.netif_count], vlan_glue)); + + // Set VLAN tag in data of lwip netif + vlan_id[vlan_netif_list.netif_count] = CONFIG_EXAMPLE_ETHERNET_VLAN_ID; + lwip_netif = esp_netif_get_netif_impl(vlan_netif_list.esp_netif[vlan_netif_list.netif_count]); + netif_set_client_data(lwip_netif, LWIP_NETIF_CLIENT_DATA_INDEX_MAX + 1, (void *)&vlan_id[vlan_netif_list.netif_count]); + + // Set static IP to the ETH_VLAN interface + esp_netif_dhcpc_stop(vlan_netif_list.esp_netif[vlan_netif_list.netif_count]); + + esp_netif_ip_info_t info_t; + memset(&info_t, 0, sizeof(esp_netif_ip_info_t)); + inet_aton(CONFIG_EXAMPLE_VLAN_STATIC_IPV4_ADDR, &info_t.ip.addr); + inet_aton(CONFIG_EXAMPLE_VLAN_STATIC_ADDR_MASK, &info_t.gw.addr); + inet_aton(CONFIG_EXAMPLE_VLAN_STATIC_ADDR_DEF_GW, &info_t.netmask.addr); + esp_netif_set_ip_info(vlan_netif_list.esp_netif[vlan_netif_list.netif_count], &info_t); + vlan_netif_list.netif_count++; + + + +#if defined(CONFIG_EXAMPLE_EXTRA_VLAN_INTERFACE) + // Create an additional instance of esp-netif for Ethernet vlan interface + ESP_ERROR_CHECK(get_vlan_netif_config(CONFIG_EXAMPLE_EXTRA_ETHERNET_VLAN_ID, &vlan_eth_cfg)); + vlan_netif_list.esp_netif[vlan_netif_list.netif_count] = esp_netif_new(&vlan_eth_cfg); + free_vlan_config(&vlan_eth_cfg); + + // Attach vlan Ethernet drivers to TCP/IP stack + vlan_glue = esp_eth_new_netif_glue(eth_handle[0]); + ESP_ERROR_CHECK(esp_netif_attach(vlan_netif_list.esp_netif[vlan_netif_list.netif_count], vlan_glue)); + + // Set VLAN tag in data of lwip netif + vlan_id[vlan_netif_list.netif_count] = CONFIG_EXAMPLE_EXTRA_ETHERNET_VLAN_ID; + lwip_netif = esp_netif_get_netif_impl(vlan_netif_list.esp_netif[vlan_netif_list.netif_count]); + netif_set_client_data(lwip_netif, LWIP_NETIF_CLIENT_DATA_INDEX_MAX + 1, (void *)&vlan_id[vlan_netif_list.netif_count]); + + // Set static IP to the ETH_VLAN interface + esp_netif_dhcpc_stop(vlan_netif_list.esp_netif[vlan_netif_list.netif_count]); + + memset(&info_t, 0, sizeof(esp_netif_ip_info_t)); + inet_aton(CONFIG_EXAMPLE_EXTRA_VLAN_STATIC_IPV4_ADDR, &info_t.ip.addr); + inet_aton(CONFIG_EXAMPLE_EXTRA_VLAN_STATIC_ADDR_MASK, &info_t.gw.addr); + inet_aton(CONFIG_EXAMPLE_EXTRA_VLAN_STATIC_ADDR_DEF_GW, &info_t.netmask.addr); + esp_netif_set_ip_info(vlan_netif_list.esp_netif[vlan_netif_list.netif_count], &info_t); + vlan_netif_list.netif_count++; +#endif //CONFIG_EXAMPLE_EXTRA_VLAN_INTERFACE + + // Update input path of the ethernet driver + esp_eth_update_input_path(eth_handle[0], eth_input_to_netif, &vlan_netif_list); + + // start Ethernet driver state machine + ESP_ERROR_CHECK(esp_eth_start(eth_handle[0])); +} diff --git a/examples/network/vlan_support/sdkconfig.defaults b/examples/network/vlan_support/sdkconfig.defaults new file mode 100644 index 0000000000..19f33526c0 --- /dev/null +++ b/examples/network/vlan_support/sdkconfig.defaults @@ -0,0 +1,4 @@ +# This file was generated using idf.py save-defconfig. It can be edited manually. +# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration +# +CONFIG_LWIP_NUM_NETIF_CLIENT_DATA=1 diff --git a/examples/openthread/.build-test-rules.yml b/examples/openthread/.build-test-rules.yml index 374b79845a..c357600b06 100644 --- a/examples/openthread/.build-test-rules.yml +++ b/examples/openthread/.build-test-rules.yml @@ -5,6 +5,10 @@ examples/openthread/ot_br: - if: IDF_TARGET == "esp32c2" temporary: true reason: target esp32c2 is not supported yet + disable_test: + - if: IDF_TARGET in ["esp32", "esp32c3", "esp32s2"] + temporary: true + reason: only test on esp32s3 examples/openthread/ot_cli: enable: diff --git a/examples/openthread/ot_br/README.md b/examples/openthread/ot_br/README.md index afc66c8e71..60b9e25605 100644 --- a/examples/openthread/ot_br/README.md +++ b/examples/openthread/ot_br/README.md @@ -10,11 +10,11 @@ This example demonstrates an [OpenThread border router](https://openthread.io/gu ## How to use example ### Hardware Required - +#### **Wi-Fi based Thread Border Router** The following SoCs are required to run this example: * An ESP32 series Wi-Fi SoC (ESP32, ESP32-C, ESP32-S, etc) loaded with this ot_br example. * An ESP32-H2 802.15.4 SoC loaded with [ot_rcp](../ot_rcp) example. -* Another ESP32-H2 SoC loaded with [ot_cli](../ot_cli) example. Enable `OPENTHREAD_JOINER` option in menuconfig before compiling the example. +* Another ESP32-H2 SoC loaded with [ot_cli](../ot_cli) example. Connect the two SoCs via UART, below is an example setup with ESP32 DevKitC and ESP32-H2 DevKitC: ![thread_br](image/thread-border-router-esp32-esp32h2.jpg) @@ -25,6 +25,9 @@ ESP32 pin | ESP32-H2 pin GPIO4 | TX GPIO5 | RX +#### **Ethernet based Thread Border Router** +Similar to the previous Wi-Fi based Thread Border Route setup, but a device with Ethernet interface is required, such as [ESP32-Ethernet-Kit](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/esp32/get-started-ethernet-kit.html) + ### Configure the project ``` @@ -39,6 +42,8 @@ The device will connect to Wi-Fi and form a Thread network automatically after b - Manual mode Disable `OPENTHREAD_BR_AUTO_START` and enable `OPENTHREAD_CLI_ESP_EXTENSION`. `wifi` command will be added for connecting the device to the Wi-Fi network. +If the `CONFIG_EXAMPLE_CONNECT_ETHERNET` option is enabled, the device will connect to `Ethernet`, form a Thread network and act as a Ethernet based Thread Border Router. + ### Build, Flash, and Run Build the project and flash it to the board, then run monitor tool to view serial output: @@ -117,105 +122,6 @@ I(8139) OPENTHREAD:[NOTE]-MLE-----: Allocate router id 50 I(8139) OPENTHREAD:[NOTE]-MLE-----: RLOC16 fffe -> c800 I(8159) OPENTHREAD:[NOTE]-MLE-----: Role Detached -> Leader ``` -## Using the border agent feature - -You need to build ot-commissioner on the host machine and another Thread end device running OpenThread cli. - -You can find the guide to build and run ot-commissioner [here](https://openthread.io/guides/commissioner/build). - -Make sure to configure the same PSKc as the one in sdkconfig in ot-commisioner's config file `non-ccm-config.json` - -### Connect the commissioner to the border router - -Note that the target address `192.168.1.100` shall match the actual Wi-Fi IP address of the device. `49154` is a port number used by the OT commissioner. - -``` bash -$ commissioner-cli /usr/local/etc/commissioner/non-ccm-config.json -> start 192.168.1.100 49154 -[done] -> active -true -[done] -``` - -You can also verify the commissioner connection from the border router's log: - -``` -I(59709) OPENTHREAD:[INFO]-MESH-CP-: DTLS started -I(65469) OPENTHREAD:[INFO]-MESH-CP-: Commissioner connected -I(65479) OPENTHREAD:[INFO]-MESH-CP-: Forwarded request to leader on c/lp -I(65489) OPENTHREAD:[INFO]-MESH-CP-: received petition -I(65489) OPENTHREAD:[INFO]-MESH-CP-: sent petition response -I(65489) OPENTHREAD:[INFO]-MESH-CP-: commissioner accepted: session ID=3077, ALOC=fd04:b642:9ba9:fcdc:0:ff:fe00:fc35 -I(65499) OPENTHREAD:[INFO]-MESH-CP-: Sent to commissioner -I(65509) OPENTHREAD:[INFO]-CORE----: Notifier: StateChanged (0x00000201) [Ip6+ NetData] -I(65529) OPENTHREAD:[INFO]-BBR-----: PBBR state: None -I(65539) OPENTHREAD:[INFO]-BBR-----: Domain Prefix: ::/0, state: None -I(65559) OPENTHREAD:[INFO]-MESH-CP-: Forwarded request to leader on c/ag -W(65559) OPENTHREAD:[WARN]-MESH-CP-: Failed to notify commissioner on ProxyRx (c/ur): DestinationAddressFiltered -I(65579) OPENTHREAD:[INFO]-MESH-CP-: sent active dataset get response to fd04:b642:9ba9:fcdc:0:ff:fe00:c800 -W(65579) OPENTHREAD:[WARN]-MESH-CP-: Failed to notify commissioner on ProxyRx (c/ur): DestinationAddressFiltered -I(65589) OPENTHREAD:[INFO]-MESH-CP-: Sent to commissioner -I(65629) OPENTHREAD:[INFO]-MESH-CP-: Forwarded request to leader on c/ag -W(65629) OPENTHREAD:[WARN]-MESH-CP-: Failed to notify commissioner on ProxyRx (c/ur): DestinationAddressFiltered -I(65649) OPENTHREAD:[INFO]-MESH-CP-: sent active dataset get response to fd04:b642:9ba9:fcdc:0:ff:fe00:c800 -W(65649) OPENTHREAD:[WARN]-MESH-CP-: Failed to notify commissioner on ProxyRx (c/ur): DestinationAddressFiltered -I(65659) OPENTHREAD:[INFO]-MESH-CP-: Sent to commissioner -I(65689) OPENTHREAD:[INFO]-MESH-CP-: Proxy transmit sent to fd04:b642:9ba9:fcdc:0:ff:fe00:fc00 -W(65689) OPENTHREAD:[WARN]-MESH-CP-: Failed to notify commissioner on ProxyRx (c/ur): DestinationAddressFiltered -I(65699) OPENTHREAD:[INFO]-MESH-CP-: sent pending dataset get response to fd04:b642:9ba9:fcdc:0:ff:fe00:fc35 -I(65709) OPENTHREAD:[INFO]-MESH-CP-: Sent to commissioner on c/ur -I(65749) OPENTHREAD:[INFO]-MESH-CP-: Proxy transmit sent to fd04:b642:9ba9:fcdc:0:ff:fe00:fc00 -W(65749) OPENTHREAD:[WARN]-MESH-CP-: Failed to notify commissioner on ProxyRx (c/ur): DestinationAddressFiltered -I(65759) OPENTHREAD:[INFO]-MESH-CP-: sent commissioning dataset set response -I(65769) OPENTHREAD:[INFO]-MESH-CP-: Sent to commissioner on c/ur -I(65769) OPENTHREAD:[INFO]-CORE----: Notifier: StateChanged (0x00000200) [NetData] -I(65789) OPENTHREAD:[INFO]-BBR-----: PBBR state: None - -``` - -### Commission the joiner - -In the OT commissioner cli, run: -``` bash -> joiner enableall meshcop J01NU5 -[done] -> -``` - -In the joining device's cli, run: - -```bash -> ifconfig up -Done -> joiner start J01NU5 -Done -> Join success! -> thread start -Done -``` - -You can also find these log lines in the border router: - -``` -I(531219) OPENTHREAD:[INFO]-MESH-CP-: Received relay transmit -I(531229) OPENTHREAD:[INFO]-MESH-CP-: Received kek -I(531279) OPENTHREAD:[INFO]-MAC-----: Sent IPv6 UDP msg, len:85, chksum:14a0, to:92335c4b320830fb, sec:no, prio:net -I(531279) OPENTHREAD:[INFO]-MAC-----: src:[fe80:0:0:0:ac2f:720a:6fe4:c837]:1000 -I(531289) OPENTHREAD:[INFO]-MAC-----: dst:[fe80:0:0:0:9033:5c4b:3208:30fb]:1000 -I(531299) OPENTHREAD:[INFO]-MESH-CP-: Sending JOIN_ENT.ntf -I(531299) OPENTHREAD:[INFO]-MESH-CP-: Sent joiner entrust length = 161 - -...... - -I(552699) OPENTHREAD:[INFO]-MLE-----: Receive Child ID Request (fe80:0:0:0:8434:c5ec:fe9f:c088) -I(552729) OPENTHREAD:[INFO]-CORE----: [settings] Added ChildInfo {rloc:0xc801, extaddr:8634c5ecfe9fc088, timeout:240, mode:0x0f, version:3} -I(552729) OPENTHREAD:[INFO]-MLE-----: Send Child ID Response (fe80:0:0:0:8434:c5ec:fe9f:c088,0xc801) -I(552739) OPENTHREAD:[INFO]-CORE----: Notifier: StateChanged (0x00000400) [Child+] -I(552749) OPENTHREAD:[INFO]-UTIL----: Starting Child Supervision -``` - -The device has now joined the same Thread network based on the key set by the commissioner. ## Bidirectional IPv6 connectivity @@ -236,7 +142,7 @@ For mobile devices, the route table rules will be automatically configured after ### Testing IPv6 connectivity -Now in the joining device, check the IP addresses: +Now in the Thread end device, check the IP addresses: ``` > ipaddr @@ -262,6 +168,7 @@ PING fde6:75ff:def4:3bc3:9e9e:3ef:4245:28b5(fde6:75ff:def4:3bc3:9e9e:3ef:4245:28 The newly introduced service registration protocol([SRP](https://datatracker.ietf.org/doc/html/draft-ietf-dnssd-srp-10)) allows devices in the Thread network to register a service. The border router will forward the service to the Wi-Fi network via mDNS. +### Publish the service using SRP Now we'll publish the service `my-service._test._udp` with hostname `test0` and port 12345 ``` @@ -293,3 +200,57 @@ $ avahi-browse -r _test._udp -t port = [12345] txt = [] ``` + +### Discovery delegate + +First, the service `testhost._test._udp` need to be published using `avahi-publish-service` on the Wi-Fi network(for example Host). + +```bash +$ avahi-publish-service testhost _test._udp 12345 test=1 dn="aabbbb" +``` + +Then get the border router's OMR prefix global unicast address(or ML-EID), and configure it on the Thread end device. + +On the border router: +``` +> ipaddr +fdde:ad00:beef:0:0:ff:fe00:fc10 +fd9b:347f:93f7:1:1003:8f00:bcc1:3038 +fdde:ad00:beef:0:0:ff:fe00:fc00 +fdde:ad00:beef:0:0:ff:fe00:b800 +fdde:ad00:beef:0:f891:287:866:776 +fe80:0:0:0:77:bca6:6079:785b +Done +``` + +On the Thread end device: +``` +> dns config fd9b:347f:93f7:1:1003:8f00:bcc1:3038 +(or +> dns config fdde:ad00:beef:0:f891:287:866:776) +Done +``` + +Now the service published on the Host can be discovered on the Thread end device. +``` +> dns resolve FA001208.default.service.arpa. +DNS response for FA001208.default.service.arpa. - fdde:ad00:beef:cafe:b939:26be:7516:b87e TTL:120 +Done + +> dns browse _test._udp.default.service.arpa. +DNS browse response for _test._udp.default.service.arpa. +testhost + Port:5683, Priority:0, Weight:0, TTL:120 + Host:FA001208.default.service.arpa. + HostAddress:fdde:ad00:beef:cafe:b939:26be:7516:b87e TTL:120 + TXT:[test=31, dn=616162626262] TTL:120 +Done + +> dns service testhost _test._udp.default.service.arpa. +DNS service resolution response for testhost for service _test._udp.default.service.arpa. +Port:5683, Priority:0, Weight:0, TTL:120 +Host:FA001208.default.service.arpa. +HostAddress:fdde:ad00:beef:cafe:b939:26be:7516:b87e TTL:120 +TXT:[test=31, dn=616162626262] TTL:120 +Done +``` diff --git a/examples/openthread/ot_br/main/esp_ot_br.c b/examples/openthread/ot_br/main/esp_ot_br.c index 348c0510d0..8bbb44ed86 100644 --- a/examples/openthread/ot_br/main/esp_ot_br.c +++ b/examples/openthread/ot_br/main/esp_ot_br.c @@ -213,6 +213,7 @@ void app_main(void) ESP_ERROR_CHECK(esp_netif_init()); ESP_ERROR_CHECK(esp_event_loop_create_default()); +#if CONFIG_EXAMPLE_CONNECT_WIFI #if CONFIG_OPENTHREAD_BR_AUTO_START ESP_ERROR_CHECK(example_connect()); ESP_ERROR_CHECK(esp_wifi_set_ps(WIFI_PS_NONE)); @@ -221,6 +222,13 @@ void app_main(void) esp_ot_wifi_netif_init(); esp_openthread_set_backbone_netif(esp_netif_get_handle_from_ifkey("WIFI_STA_DEF")); #endif // CONFIG_OPENTHREAD_BR_AUTO_START +#elif CONFIG_EXAMPLE_CONNECT_ETHERNET + ESP_ERROR_CHECK(example_connect()); + esp_openthread_set_backbone_netif(get_example_netif()); +#else + ESP_LOGE(TAG, "ESP-Openthread has not set backbone netif"); +#endif // CONFIG_EXAMPLE_CONNECT_WIFI + ESP_ERROR_CHECK(mdns_init()); ESP_ERROR_CHECK(mdns_hostname_set("esp-ot-br")); xTaskCreate(ot_task_worker, "ot_br_main", 20480, xTaskGetCurrentTaskHandle(), 5, NULL); diff --git a/examples/openthread/ot_br/main/idf_component.yml b/examples/openthread/ot_br/main/idf_component.yml index 6bcf90f97a..2f9c0f6440 100644 --- a/examples/openthread/ot_br/main/idf_component.yml +++ b/examples/openthread/ot_br/main/idf_component.yml @@ -1,6 +1,6 @@ ## IDF Component Manager Manifest File dependencies: - espressif/esp_ot_cli_extension: "*" + espressif/esp_ot_cli_extension: "~0.1.0" espressif/mdns: "^1.0.3" ## Required IDF version idf: diff --git a/examples/openthread/ot_br/sdkconfig.ci.br b/examples/openthread/ot_br/sdkconfig.ci.br new file mode 100644 index 0000000000..e69de29bb2 diff --git a/examples/openthread/ot_br/sdkconfig.defaults b/examples/openthread/ot_br/sdkconfig.defaults index e8dddfb481..369bdb00f6 100644 --- a/examples/openthread/ot_br/sdkconfig.defaults +++ b/examples/openthread/ot_br/sdkconfig.defaults @@ -17,7 +17,6 @@ CONFIG_PARTITION_TABLE_MD5=y # # mbedTLS # - CONFIG_MBEDTLS_CMAC_C=y CONFIG_MBEDTLS_SSL_PROTO_DTLS=y CONFIG_MBEDTLS_KEY_EXCHANGE_ECJPAKE=y diff --git a/examples/openthread/ot_ci_function.py b/examples/openthread/ot_ci_function.py new file mode 100644 index 0000000000..b71e7f19e7 --- /dev/null +++ b/examples/openthread/ot_ci_function.py @@ -0,0 +1,222 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Unlicense OR CC0-1.0 +# !/usr/bin/env python3 +# this file defines some functions for testing cli and br under pytest framework + +import re +import subprocess +import time +from typing import Tuple, Union + +import netifaces +import pexpect +from pytest_embedded_idf.dut import IdfDut + + +def reset_thread(dut:IdfDut) -> None: + time.sleep(1) + dut.write('factoryreset') + time.sleep(3) + dut.expect('OpenThread attached to netif', timeout=10) + dut.write(' ') + dut.write('state') + + +# config thread +def config_thread(dut:IdfDut, model:str, dataset:str='0') -> Union[str, None]: + if model == 'random': + dut.write('dataset init new') + dut.expect('Done', timeout=2) + dut.write('dataset commit active') + dut.expect('Done', timeout=2) + dut.write('ifconfig up') + dut.expect('Done', timeout=2) + dut.write('dataset active -x') # get dataset + dut_data = dut.expect(r'\n(\w{212})\r', timeout=5)[1].decode() + return str(dut_data) + if model == 'appointed': + tmp = 'dataset set active ' + str(dataset) + dut.write(tmp) + dut.expect('Done', timeout=2) + dut.write('ifconfig up') + dut.expect('Done', timeout=2) + return None + return None + + +# get the mleid address of the thread +def get_mleid_addr(dut:IdfDut) -> str: + dut_adress = '' + clean_buffer(dut) + dut.write('ipaddr mleid') + dut_adress = dut.expect(r'\n((?:\w+:){7}\w+)\r', timeout=5)[1].decode() + return dut_adress + + +# get the rloc address of the thread +def get_rloc_addr(dut:IdfDut) -> str: + dut_adress = '' + clean_buffer(dut) + dut.write('ipaddr rloc') + dut_adress = dut.expect(r'\n((?:\w+:){7}\w+)\r', timeout=5)[1].decode() + return dut_adress + + +# get the linklocal address of the thread +def get_linklocal_addr(dut:IdfDut) -> str: + dut_adress = '' + clean_buffer(dut) + dut.write('ipaddr linklocal') + dut_adress = dut.expect(r'\n((?:\w+:){7}\w+)\r', timeout=5)[1].decode() + return dut_adress + + +# get the global unicast address of the thread: +def get_global_unicast_addr(dut:IdfDut, br:IdfDut) -> str: + dut_adress = '' + clean_buffer(br) + br.write('br omrprefix') + omrprefix = br.expect(r'\n((?:\w+:){4}):/\d+\r', timeout=5)[1].decode() + clean_buffer(dut) + dut.write('ipaddr') + dut_adress = dut.expect(r'(%s(?:\w+:){3}\w+)\r' % str(omrprefix), timeout=5)[1].decode() + return dut_adress + + +# start thread +def start_thread(dut:IdfDut) -> str: + role = '' + dut.write('thread start') + tmp = dut.expect(r'Role detached -> (\w+)\W', timeout=20)[0] + role = re.findall(r'Role detached -> (\w+)\W', str(tmp))[0] + return role + + +# config br and cli manually +def form_network_using_manual_configuration(leader:IdfDut, child:IdfDut, leader_name:str, thread_dataset_model:str, + thread_dataset:str, wifi:IdfDut, wifi_ssid:str, wifi_psk:str) -> str: + time.sleep(3) + leader.expect('OpenThread attached to netif', timeout=10) + leader.write(' ') + leader.write('state') + child.expect('OpenThread attached to netif', timeout=10) + child.write(' ') + child.write('state') + reset_thread(leader) + reset_thread(child) + leader.write('channel 12') + leader.expect('Done', timeout=2) + child.write('channel 12') + child.expect('Done', timeout=2) + res = '0000' + if wifi_psk != '0000': + res = connect_wifi(wifi, wifi_ssid, wifi_psk, 10)[0] + leader_data = '' + if thread_dataset_model == 'random': + leader_data = str(config_thread(leader, 'random')) + else: + config_thread(leader, 'appointed', thread_dataset) + if leader_name == 'br': + leader.write('bbr enable') + leader.expect('Done', timeout=2) + role = start_thread(leader) + assert role == 'leader' + if thread_dataset_model == 'random': + config_thread(child, 'appointed', leader_data) + else: + config_thread(child, 'appointed', thread_dataset) + if leader_name != 'br': + child.write('bbr enable') + child.expect('Done', timeout=2) + role = start_thread(child) + assert role == 'child' + return res + + +# ping of thread +def ot_ping(dut:IdfDut, target:str, times:int) -> Tuple[int, int]: + command = 'ping ' + str(target) + ' 0 ' + str(times) + dut.write(command) + transmitted = dut.expect(r'(\d+) packets transmitted', timeout=30)[1].decode() + tx_count = int(transmitted) + received = dut.expect(r'(\d+) packets received', timeout=30)[1].decode() + rx_count = int(received) + return tx_count, rx_count + + +# connect Wi-Fi +def connect_wifi(dut:IdfDut, ssid:str, psk:str, nums:int) -> Tuple[str, int]: + clean_buffer(dut) + ip_address = '' + information = '' + for order in range(1, nums): + dut.write('wifi connect -s ' + str(ssid) + ' -p ' + str(psk)) + tmp = dut.expect(pexpect.TIMEOUT, timeout=5) + ip_address = re.findall(r'sta ip: (\w+.\w+.\w+.\w+),', str(tmp))[0] + information = dut.expect(r'wifi sta (\w+ \w+ \w+)\W', timeout=5)[1].decode() + if information == 'is connected successfully': + break + assert information == 'is connected successfully' + return ip_address, order + + +def reset_host_interface() -> None: + interface_name = get_host_interface_name() + flag = False + try: + command = 'ifconfig ' + interface_name + ' down' + subprocess.call(command, shell=True, timeout=5) + time.sleep(10) + command = 'ifconfig ' + interface_name + ' up' + subprocess.call(command, shell=True, timeout=10) + time.sleep(20) + flag = True + finally: + time.sleep(10) + assert flag + + +def set_interface_sysctl_options() -> None: + interface_name = get_host_interface_name() + flag = False + try: + command = 'sysctl -w net/ipv6/conf/' + interface_name + '/accept_ra=2' + subprocess.call(command, shell=True, timeout=5) + time.sleep(1) + command = 'sysctl -w net/ipv6/conf/' + interface_name + '/accept_ra_rt_info_max_plen=128' + subprocess.call(command, shell=True, timeout=5) + time.sleep(5) + flag = True + finally: + time.sleep(5) + assert flag + + +def init_interface_ipv6_address() -> None: + interface_name = get_host_interface_name() + flag = False + try: + command = 'ip -6 route | grep ' + interface_name + " | grep ra | awk {'print $1'} | xargs -I {} ip -6 route del {}" + subprocess.call(command, shell=True, timeout=5) + time.sleep(0.5) + subprocess.call(command, shell=True, timeout=5) + time.sleep(1) + command = 'ip -6 address show dev ' + interface_name + \ + " scope global | grep 'inet6' | awk {'print $2'} | xargs -I {} ip -6 addr del {} dev " + interface_name + subprocess.call(command, shell=True, timeout=5) + time.sleep(1) + flag = True + finally: + time.sleep(5) + assert flag + + +def get_host_interface_name() -> str: + interfaces = netifaces.interfaces() + interface_name = [s for s in interfaces if 'wl' in s][0] + return str(interface_name) + + +def clean_buffer(dut:IdfDut) -> None: + str_length = str(len(dut.expect(pexpect.TIMEOUT, timeout=0.1))) + dut.expect(r'[\s\S]{%s}' % str(str_length), timeout=10) diff --git a/examples/openthread/ot_cli/main/esp_ot_cli.c b/examples/openthread/ot_cli/main/esp_ot_cli.c index 863664a585..0d4e3ad379 100644 --- a/examples/openthread/ot_cli/main/esp_ot_cli.c +++ b/examples/openthread/ot_cli/main/esp_ot_cli.c @@ -43,7 +43,6 @@ #define TAG "ot_esp_cli" -#if CONFIG_OPENTHREAD_CLI_ESP_EXTENSION static esp_netif_t *init_openthread_netif(const esp_openthread_platform_config_t *config) { esp_netif_config_t cfg = ESP_NETIF_DEFAULT_OPENTHREAD(); @@ -53,7 +52,6 @@ static esp_netif_t *init_openthread_netif(const esp_openthread_platform_config_t return netif; } -#endif // CONFIG_OPENTHREAD_CLI_ESP_EXTENSION static void ot_task_worker(void *aContext) { @@ -66,16 +64,18 @@ static void ot_task_worker(void *aContext) // Initialize the OpenThread stack ESP_ERROR_CHECK(esp_openthread_init(&config)); +#if CONFIG_OPENTHREAD_LOG_LEVEL_DYNAMIC // The OpenThread log level directly matches ESP log level (void)otLoggingSetLevel(CONFIG_LOG_DEFAULT_LEVEL); +#endif // Initialize the OpenThread cli esp_openthread_cli_init(); -#if CONFIG_OPENTHREAD_CLI_ESP_EXTENSION esp_netif_t *openthread_netif; // Initialize the esp_netif bindings openthread_netif = init_openthread_netif(&config); +#if CONFIG_OPENTHREAD_CLI_ESP_EXTENSION esp_cli_custom_command_init(); #endif // CONFIG_OPENTHREAD_CLI_ESP_EXTENSION @@ -84,10 +84,8 @@ static void ot_task_worker(void *aContext) esp_openthread_launch_mainloop(); // Clean up -#if CONFIG_OPENTHREAD_CLI_ESP_EXTENSION esp_netif_destroy(openthread_netif); esp_openthread_netif_glue_deinit(); -#endif // CONFIG_OPENTHREAD_CLI_ESP_EXTENSION esp_vfs_eventfd_unregister(); vTaskDelete(NULL); @@ -104,9 +102,7 @@ void app_main(void) }; ESP_ERROR_CHECK(esp_event_loop_create_default()); -#if CONFIG_OPENTHREAD_CLI_ESP_EXTENSION ESP_ERROR_CHECK(esp_netif_init()); -#endif // CONFIG_OPENTHREAD_CLI_ESP_EXTENSION ESP_ERROR_CHECK(esp_vfs_eventfd_register(&eventfd_config)); xTaskCreate(ot_task_worker, "ot_cli_main", 10240, xTaskGetCurrentTaskHandle(), 5, NULL); } diff --git a/examples/openthread/ot_cli/main/idf_component.yml b/examples/openthread/ot_cli/main/idf_component.yml index 1d7d5f4a23..2246fc9a0e 100644 --- a/examples/openthread/ot_cli/main/idf_component.yml +++ b/examples/openthread/ot_cli/main/idf_component.yml @@ -1,5 +1,5 @@ ## IDF Component Manager Manifest File dependencies: - espressif/esp_ot_cli_extension: "*" + espressif/esp_ot_cli_extension: "~0.1.0" idf: version: ">=4.1.0" diff --git a/examples/openthread/ot_cli/sdkconfig.ci.cli b/examples/openthread/ot_cli/sdkconfig.ci.cli new file mode 100644 index 0000000000..3151ae4eaf --- /dev/null +++ b/examples/openthread/ot_cli/sdkconfig.ci.cli @@ -0,0 +1,3 @@ +CONFIG_IDF_TARGET="esp32h2" +CONFIG_IDF_TARGET_ESP32H2=y +CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2=y diff --git a/examples/openthread/ot_rcp/main/Kconfig.projbuild b/examples/openthread/ot_rcp/main/Kconfig.projbuild new file mode 100644 index 0000000000..3bff9f0920 --- /dev/null +++ b/examples/openthread/ot_rcp/main/Kconfig.projbuild @@ -0,0 +1,21 @@ +menu "OpenThread RCP Example" + + config OPENTHREAD_UART_PIN_MANUAL + bool "Configure RCP UART pin manually" + default n + help + Select this to choose UART pin manually + + config OPENTHREAD_UART_RX_PIN + int "The number of RX pin" + depends on OPENTHREAD_UART_PIN_MANUAL + default 4 + range 0 25 + + config OPENTHREAD_UART_TX_PIN + int "The number of TX pin" + depends on OPENTHREAD_UART_PIN_MANUAL + default 5 + range 0 25 + +endmenu diff --git a/examples/openthread/ot_rcp/main/esp_ot_config.h b/examples/openthread/ot_rcp/main/esp_ot_config.h index 3006f4aa40..a54e23c0cf 100644 --- a/examples/openthread/ot_rcp/main/esp_ot_config.h +++ b/examples/openthread/ot_rcp/main/esp_ot_config.h @@ -20,6 +20,14 @@ .radio_mode = RADIO_MODE_NATIVE, \ } +#if CONFIG_OPENTHREAD_UART_PIN_MANUAL +#define OPENTHREAD_RCP_UART_RX_PIN CONFIG_OPENTHREAD_UART_RX_PIN +#define OPENTHREAD_RCP_UART_TX_PIN CONFIG_OPENTHREAD_UART_TX_PIN +#else +#define OPENTHREAD_RCP_UART_RX_PIN UART_PIN_NO_CHANGE +#define OPENTHREAD_RCP_UART_TX_PIN UART_PIN_NO_CHANGE +#endif + #define ESP_OPENTHREAD_DEFAULT_HOST_CONFIG() \ { \ .host_connection_mode = HOST_CONNECTION_MODE_RCP_UART, \ @@ -35,8 +43,8 @@ .rx_flow_ctrl_thresh = 0, \ .source_clk = UART_SCLK_DEFAULT, \ }, \ - .rx_pin = UART_PIN_NO_CHANGE, \ - .tx_pin = UART_PIN_NO_CHANGE, \ + .rx_pin = OPENTHREAD_RCP_UART_RX_PIN, \ + .tx_pin = OPENTHREAD_RCP_UART_TX_PIN, \ }, \ } diff --git a/examples/openthread/ot_rcp/sdkconfig.ci.rcp b/examples/openthread/ot_rcp/sdkconfig.ci.rcp new file mode 100644 index 0000000000..98376e6808 --- /dev/null +++ b/examples/openthread/ot_rcp/sdkconfig.ci.rcp @@ -0,0 +1,3 @@ +CONFIG_OPENTHREAD_UART_PIN_MANUAL=y +CONFIG_OPENTHREAD_UART_RX_PIN=4 +CONFIG_OPENTHREAD_UART_TX_PIN=5 diff --git a/examples/openthread/pytest_otbr.py b/examples/openthread/pytest_otbr.py new file mode 100644 index 0000000000..2130183641 --- /dev/null +++ b/examples/openthread/pytest_otbr.py @@ -0,0 +1,223 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Unlicense OR CC0-1.0 +# !/usr/bin/env python3 + + +import os.path +import re +import socket +import struct +import subprocess +import time +from typing import Tuple + +import ot_ci_function as ocf +import pytest +from pytest_embedded_idf.dut import IdfDut + +# This file contains the test scripts for Thread: + +# Case 1: Thread network formation and attaching +# A Thread Border Router forms a Thread network, a Thread device attaches to it, then test ping connection between them. + +# Case 2: Bidirectional IPv6 connectivity +# Test IPv6 ping connection between Thread device and Linux Host (via Thread Border Router). + +# Case 3: Multicast forwarding from Wi-Fi to Thread network +# Thread device joins the multicast group, then test group communication from Wi-Fi to Thread network. + +# Case 4: Multicast forwarding from Thread to Wi-Fi network +# Linux Host joins the multicast group, test group communication from Thread to Wi-Fi network. + + +@pytest.fixture(name='Init_interface') +def fixture_Init_interface() -> bool: + ocf.init_interface_ipv6_address() + ocf.reset_host_interface() + ocf.set_interface_sysctl_options() + return True + + +# Case 1: Thread network formation and attaching +@pytest.mark.esp32s3 +@pytest.mark.esp32h2 +@pytest.mark.i154_multi_dut +@pytest.mark.flaky(reruns=2, reruns_delay=10) +@pytest.mark.parametrize( + 'port, config, count, app_path, beta_target, target', [ + ('/dev/USB_BR|/dev/USB_CLI|/dev/USB_RCP', 'br|cli|rcp', 3, + f'{os.path.join(os.path.dirname(__file__), "ot_br")}' + f'|{os.path.join(os.path.dirname(__file__), "ot_cli")}' + f'|{os.path.join(os.path.dirname(__file__), "ot_rcp")}', + 'esp32s3|esp32h2beta2|esp32h2beta2', 'esp32s3|esp32h2|esp32h2'), + ], + indirect=True, +) +def test_thread_connect(dut:Tuple[IdfDut, IdfDut]) -> None: + br = dut[0] + cli = dut[1] + + dataset = '-1' + ocf.form_network_using_manual_configuration(br, cli, 'br', 'random', dataset, br, 'OTCITE', '0000') + time.sleep(1) + flag = False + try: + cli_mleid_addr = ocf.get_mleid_addr(cli) + br_mleid_addr = ocf.get_mleid_addr(br) + rx_nums = ocf.ot_ping(cli, br_mleid_addr, 5)[1] + assert rx_nums != 0 + rx_nums = ocf.ot_ping(br, cli_mleid_addr, 5)[1] + assert rx_nums != 0 + flag = True + finally: + br.write('factoryreset') + cli.write('factoryreset') + time.sleep(3) + assert flag + + +# Case 2: Bidirectional IPv6 connectivity +@pytest.mark.esp32s3 +@pytest.mark.esp32h2 +@pytest.mark.i154_multi_dut +@pytest.mark.flaky(reruns=5, reruns_delay=10) +@pytest.mark.parametrize( + 'port, config, count, app_path, beta_target, target', [ + ('/dev/USB_BR|/dev/USB_CLI|/dev/USB_RCP', 'br|cli|rcp', 3, + f'{os.path.join(os.path.dirname(__file__), "ot_br")}' + f'|{os.path.join(os.path.dirname(__file__), "ot_cli")}' + f'|{os.path.join(os.path.dirname(__file__), "ot_rcp")}', + 'esp32s3|esp32h2beta2|esp32h2beta2', 'esp32s3|esp32h2|esp32h2'), + ], + indirect=True, +) +def test_Bidirectional_IPv6_connectivity(Init_interface:bool, dut: Tuple[IdfDut, IdfDut]) -> None: + br = dut[0] + cli = dut[1] + assert Init_interface + + dataset = '-1' + ocf.form_network_using_manual_configuration(br, cli, 'br', 'random', dataset, br, 'OTCITE', 'otcitest888') + time.sleep(5) + cli_global_unicast_addr = ocf.get_global_unicast_addr(cli, br) + flag = False + try: + command = 'ping ' + str(cli_global_unicast_addr) + ' -c 10' + out_bytes = subprocess.check_output(command, shell=True, timeout=60) + out_str = out_bytes.decode('utf-8') + role = re.findall(r' (\d+)%', str(out_str))[0] + assert role != '100' + interface_name = ocf.get_host_interface_name() + command = 'ifconfig ' + interface_name + out_bytes = subprocess.check_output(command, shell=True, timeout=5) + out_str = out_bytes.decode('utf-8') + host_global_unicast_addr = re.findall(r'inet6 ((?:\w+:){7}\w+) prefixlen 64 scopeid 0x0', str(out_str)) + rx_nums = 0 + for ip_addr in host_global_unicast_addr: + txrx_nums = ocf.ot_ping(cli, str(ip_addr), 5) + rx_nums = rx_nums + int(txrx_nums[1]) + assert rx_nums != 0 + flag = True + finally: + br.write('factoryreset') + cli.write('factoryreset') + time.sleep(3) + assert flag + + +# Case 3: Multicast forwarding from Wi-Fi to Thread network +@pytest.mark.esp32s3 +@pytest.mark.esp32h2 +@pytest.mark.i154_multi_dut +@pytest.mark.flaky(reruns=5, reruns_delay=10) +@pytest.mark.parametrize( + 'port, config, count, app_path, beta_target, target', [ + ('/dev/USB_BR|/dev/USB_CLI|/dev/USB_RCP', 'br|cli|rcp', 3, + f'{os.path.join(os.path.dirname(__file__), "ot_br")}' + f'|{os.path.join(os.path.dirname(__file__), "ot_cli")}' + f'|{os.path.join(os.path.dirname(__file__), "ot_rcp")}', + 'esp32s3|esp32h2beta2|esp32h2beta2', 'esp32s3|esp32h2|esp32h2'), + ], + indirect=True, +) +def test_multicast_forwarding_A(Init_interface:bool, dut: Tuple[IdfDut, IdfDut]) -> None: + br = dut[0] + cli = dut[1] + assert Init_interface + + dataset = '-1' + ocf.form_network_using_manual_configuration(br, cli, 'br', 'random', dataset, br, 'OTCITE', 'otcitest888') + time.sleep(5) + flag = False + try: + br.write('bbr') + br.expect('server16', timeout=2) + cli.write('mcast join ff04::125') + cli.expect('Done', timeout=2) + time.sleep(1) + interface_name = ocf.get_host_interface_name() + command = 'ping -I ' + str(interface_name) + ' -t 64 ff04::125 -c 10' + out_bytes = subprocess.check_output(command, shell=True, timeout=60) + out_str = out_bytes.decode('utf-8') + role = re.findall(r' (\d+)%', str(out_str))[0] + assert role != '100' + flag = True + finally: + br.write('factoryreset') + cli.write('factoryreset') + time.sleep(3) + assert flag + + +# Case 4: Multicast forwarding from Thread to Wi-Fi network +@pytest.mark.esp32s3 +@pytest.mark.esp32h2 +@pytest.mark.i154_multi_dut +@pytest.mark.flaky(reruns=5, reruns_delay=5) +@pytest.mark.parametrize( + 'port, config, count, app_path, beta_target, target', [ + ('/dev/USB_BR|/dev/USB_CLI|/dev/USB_RCP', 'br|cli|rcp', 3, + f'{os.path.join(os.path.dirname(__file__), "ot_br")}' + f'|{os.path.join(os.path.dirname(__file__), "ot_cli")}' + f'|{os.path.join(os.path.dirname(__file__), "ot_rcp")}', + 'esp32s3|esp32h2beta2|esp32h2beta2', 'esp32s3|esp32h2|esp32h2'), + ], + indirect=True, +) +def test_multicast_forwarding_B(Init_interface:bool, dut: Tuple[IdfDut, IdfDut]) -> None: + br = dut[0] + cli = dut[1] + assert Init_interface + + dataset = '-1' + ocf.form_network_using_manual_configuration(br, cli, 'br', 'random', dataset, br, 'OTCITE', 'otcitest888') + time.sleep(5) + br.write('bbr') + br.expect('server16', timeout=2) + interface_name = ocf.get_host_interface_name() + if_index = socket.if_nametoindex(interface_name) + sock = socket.socket(socket.AF_INET6, socket.SOCK_DGRAM) + sock.bind(('::', 5090)) + sock.setsockopt( + socket.IPPROTO_IPV6, socket.IPV6_JOIN_GROUP, + struct.pack('16si', socket.inet_pton(socket.AF_INET6, 'ff04::125'), + if_index)) + time.sleep(1) + cli.write('udp open') + cli.expect('Done', timeout=2) + cli.write('udp send ff04::125 5090 hello') + cli.expect('Done', timeout=2) + data = b'' + try: + print('The host start to receive message!') + sock.settimeout(5) + data = (sock.recvfrom(1024))[0] + print('The host has received message!') + except socket.error: + print('The host did not received message!') + finally: + sock.close() + br.write('factoryreset') + cli.write('factoryreset') + time.sleep(3) + assert data == b'hello' diff --git a/examples/peripherals/.build-test-rules.yml b/examples/peripherals/.build-test-rules.yml index 5412877979..bed4e447d7 100644 --- a/examples/peripherals/.build-test-rules.yml +++ b/examples/peripherals/.build-test-rules.yml @@ -50,6 +50,10 @@ examples/peripherals/i2s/i2s_basic/i2s_tdm: disable: - if: SOC_I2S_SUPPORTS_TDM != 1 +examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm: + disable: + - if: SOC_I2S_SUPPORTS_TDM != 1 + examples/peripherals/i2s/i2s_codec/i2s_es8311: disable: - if: SOC_I2S_SUPPORTED != 1 @@ -103,16 +107,16 @@ examples/peripherals/rmt/ir_nec_transceiver: reason: lack of runners examples/peripherals/rmt/musical_buzzer: - enable: - - if: SOC_RMT_SUPPORT_TX_LOOP_COUNT == 1 + disable: + - if: SOC_RMT_SUPPORT_TX_LOOP_COUNT != 1 examples/peripherals/rmt/onewire_ds18b20: disable: - if: SOC_RMT_SUPPORTED != 1 examples/peripherals/rmt/stepper_motor: - enable: - - if: SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP == 1 + disable: + - if: SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP != 1 examples/peripherals/sdio: disable: diff --git a/examples/peripherals/adc/continuous_read/main/CMakeLists.txt b/examples/peripherals/adc/continuous_read/main/CMakeLists.txt index c9dd1dd9cd..902872a063 100644 --- a/examples/peripherals/adc/continuous_read/main/CMakeLists.txt +++ b/examples/peripherals/adc/continuous_read/main/CMakeLists.txt @@ -1,3 +1,2 @@ idf_component_register(SRCS "continuous_read_main.c" INCLUDE_DIRS ".") -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/adc/continuous_read/main/continuous_read_main.c b/examples/peripherals/adc/continuous_read/main/continuous_read_main.c index 47f51edb61..bdfbf8965d 100644 --- a/examples/peripherals/adc/continuous_read/main/continuous_read_main.c +++ b/examples/peripherals/adc/continuous_read/main/continuous_read_main.c @@ -133,7 +133,7 @@ void app_main(void) while (1) { ret = adc_continuous_read(handle, result, EXAMPLE_READ_LEN, &ret_num, 0); if (ret == ESP_OK) { - ESP_LOGI("TASK", "ret is %x, ret_num is %d", ret, ret_num); + ESP_LOGI("TASK", "ret is %x, ret_num is %"PRIu32, ret, ret_num); for (int i = 0; i < ret_num; i += SOC_ADC_DIGI_RESULT_BYTES) { adc_digi_output_data_t *p = (void*)&result[i]; #if CONFIG_IDF_TARGET_ESP32 diff --git a/examples/peripherals/adc/oneshot_read/main/oneshot_read_main.c b/examples/peripherals/adc/oneshot_read/main/oneshot_read_main.c index a7ac30a7b6..c71c50259b 100644 --- a/examples/peripherals/adc/oneshot_read/main/oneshot_read_main.c +++ b/examples/peripherals/adc/oneshot_read/main/oneshot_read_main.c @@ -70,7 +70,7 @@ void app_main(void) adc_oneshot_unit_handle_t adc2_handle; adc_oneshot_unit_init_cfg_t init_config2 = { .unit_id = ADC_UNIT_2, - .ulp_mode = false, + .ulp_mode = ADC_ULP_MODE_DISABLE, }; ESP_ERROR_CHECK(adc_oneshot_new_unit(&init_config2, &adc2_handle)); diff --git a/examples/peripherals/gpio/generic_gpio/main/CMakeLists.txt b/examples/peripherals/gpio/generic_gpio/main/CMakeLists.txt index 8adcdef66d..81e99f92f9 100644 --- a/examples/peripherals/gpio/generic_gpio/main/CMakeLists.txt +++ b/examples/peripherals/gpio/generic_gpio/main/CMakeLists.txt @@ -1,3 +1,2 @@ idf_component_register(SRCS "gpio_example_main.c" INCLUDE_DIRS ".") -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c b/examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c index e0ec63efd1..baa4bcef27 100644 --- a/examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c +++ b/examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c @@ -9,6 +9,7 @@ #include #include #include +#include #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/queue.h" @@ -55,7 +56,7 @@ static void gpio_task_example(void* arg) uint32_t io_num; for(;;) { if(xQueueReceive(gpio_evt_queue, &io_num, portMAX_DELAY)) { - printf("GPIO[%d] intr, val: %d\n", io_num, gpio_get_level(io_num)); + printf("GPIO[%"PRIu32"] intr, val: %d\n", io_num, gpio_get_level(io_num)); } } } @@ -107,7 +108,7 @@ void app_main(void) //hook isr handler for specific gpio pin again gpio_isr_handler_add(GPIO_INPUT_IO_0, gpio_isr_handler, (void*) GPIO_INPUT_IO_0); - printf("Minimum free heap size: %d bytes\n", esp_get_minimum_free_heap_size()); + printf("Minimum free heap size: %"PRIu32" bytes\n", esp_get_minimum_free_heap_size()); int cnt = 0; while(1) { diff --git a/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/CMakeLists.txt b/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/CMakeLists.txt index 98f9bcab35..167e6b2d80 100644 --- a/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/CMakeLists.txt +++ b/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/CMakeLists.txt @@ -5,4 +5,3 @@ idf_component_register(SRCS "${component_srcs}" PRIV_INCLUDE_DIRS "" PRIV_REQUIRES "driver" REQUIRES "") -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/src/matrix_keyboard.c b/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/src/matrix_keyboard.c index e801b02846..b19d4eea71 100644 --- a/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/src/matrix_keyboard.c +++ b/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/src/matrix_keyboard.c @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include #include "freertos/FreeRTOS.h" #include "freertos/task.h" @@ -67,7 +59,7 @@ static void matrix_kbd_debounce_timer_callback(TimerHandle_t xTimer) uint32_t row_out = dedic_gpio_bundle_read_out(mkbd->row_bundle); uint32_t col_in = dedic_gpio_bundle_read_in(mkbd->col_bundle); row_out = (~row_out) & ((1 << mkbd->nr_row_gpios) - 1); - ESP_LOGD(TAG, "row_out=%x, col_in=%x", row_out, col_in); + ESP_LOGD(TAG, "row_out=%"PRIx32", col_in=%"PRIx32, row_out, col_in); int row = -1; int col = -1; uint32_t key_code = 0; diff --git a/examples/peripherals/gpio/matrix_keyboard/main/CMakeLists.txt b/examples/peripherals/gpio/matrix_keyboard/main/CMakeLists.txt index ad6b382f26..ce42fe41d6 100644 --- a/examples/peripherals/gpio/matrix_keyboard/main/CMakeLists.txt +++ b/examples/peripherals/gpio/matrix_keyboard/main/CMakeLists.txt @@ -1,3 +1,2 @@ idf_component_register(SRCS "matrix_keyboard_example_main.c" INCLUDE_DIRS "") -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/gpio/matrix_keyboard/main/matrix_keyboard_example_main.c b/examples/peripherals/gpio/matrix_keyboard/main/matrix_keyboard_example_main.c index af121e0815..fd1008e90b 100644 --- a/examples/peripherals/gpio/matrix_keyboard/main/matrix_keyboard_example_main.c +++ b/examples/peripherals/gpio/matrix_keyboard/main/matrix_keyboard_example_main.c @@ -21,10 +21,10 @@ esp_err_t example_matrix_kbd_event_handler(matrix_kbd_handle_t mkbd_handle, matr uint32_t key_code = (uint32_t)event_data; switch (event) { case MATRIX_KBD_EVENT_DOWN: - ESP_LOGI(TAG, "press event, key code = %04x", key_code); + ESP_LOGI(TAG, "press event, key code = %04"PRIx32, key_code); break; case MATRIX_KBD_EVENT_UP: - ESP_LOGI(TAG, "release event, key code = %04x", key_code); + ESP_LOGI(TAG, "release event, key code = %04"PRIx32, key_code); break; } return ESP_OK; diff --git a/examples/peripherals/i2c/i2c_self_test/main/CMakeLists.txt b/examples/peripherals/i2c/i2c_self_test/main/CMakeLists.txt index a1ac988361..3603c38d49 100644 --- a/examples/peripherals/i2c/i2c_self_test/main/CMakeLists.txt +++ b/examples/peripherals/i2c/i2c_self_test/main/CMakeLists.txt @@ -1,3 +1,2 @@ idf_component_register(SRCS "i2c_example_main.c" - INCLUDE_DIRS ".") -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") + INCLUDE_DIRS ".") diff --git a/examples/peripherals/i2c/i2c_self_test/main/i2c_example_main.c b/examples/peripherals/i2c/i2c_self_test/main/i2c_example_main.c index 184ccfcc35..26b6db52b7 100644 --- a/examples/peripherals/i2c/i2c_self_test/main/i2c_example_main.c +++ b/examples/peripherals/i2c/i2c_self_test/main/i2c_example_main.c @@ -213,7 +213,7 @@ static void disp_buf(uint8_t *buf, int len) static void i2c_test_task(void *arg) { int ret; - uint32_t task_idx = (uint32_t)arg; + int task_idx = (int)arg; #if SOC_I2C_NUM > 1 int i = 0; uint8_t *data = (uint8_t *)malloc(DATA_LENGTH); diff --git a/examples/peripherals/i2c/i2c_tools/main/CMakeLists.txt b/examples/peripherals/i2c/i2c_tools/main/CMakeLists.txt index d61b866297..60f09894c4 100644 --- a/examples/peripherals/i2c/i2c_tools/main/CMakeLists.txt +++ b/examples/peripherals/i2c/i2c_tools/main/CMakeLists.txt @@ -1,4 +1,3 @@ idf_component_register(SRCS "i2ctools_example_main.c" "cmd_i2ctools.c" - INCLUDE_DIRS ".") -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") + INCLUDE_DIRS ".") diff --git a/examples/peripherals/i2c/i2c_tools/main/cmd_i2ctools.c b/examples/peripherals/i2c/i2c_tools/main/cmd_i2ctools.c index 28b97b2180..8d30ede7b8 100644 --- a/examples/peripherals/i2c/i2c_tools/main/cmd_i2ctools.c +++ b/examples/peripherals/i2c/i2c_tools/main/cmd_i2ctools.c @@ -148,7 +148,7 @@ static int do_i2cdetect_cmd(int argc, char **argv) return 0; } -static void register_i2cdectect(void) +static void register_i2cdetect(void) { const esp_console_cmd_t i2cdetect_cmd = { .command = "i2cdetect", @@ -380,7 +380,7 @@ static int do_i2cdump_cmd(int argc, char **argv) } else if ((block[k] & 0xff) < 32 || (block[k] & 0xff) >= 127) { printf("?"); } else { - printf("%c", block[k] & 0xff); + printf("%c", (char)(block[k] & 0xff)); } } printf("\r\n"); @@ -407,7 +407,7 @@ static void register_i2cdump(void) void register_i2ctools(void) { register_i2cconfig(); - register_i2cdectect(); + register_i2cdetect(); register_i2cget(); register_i2cset(); register_i2cdump(); diff --git a/examples/peripherals/i2s/common/format_wav.h b/examples/peripherals/i2s/common/format_wav.h new file mode 100644 index 0000000000..b84345eabc --- /dev/null +++ b/examples/peripherals/i2s/common/format_wav.h @@ -0,0 +1,73 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Header structure for WAV file with only one data chunk + * + * @note See this for reference: http://soundfile.sapp.org/doc/WaveFormat/ + * + * @note Assignment to variables in this struct directely is only possible for little endian architectures + * (including Xtensa & RISC-V) + */ +typedef struct { + struct { + char chunk_id[4]; /*!< Contains the letters "RIFF" in ASCII form */ + uint32_t chunk_size; /*!< This is the size of the rest of the chunk following this number */ + char chunk_format[4]; /*!< Contains the letters "WAVE" */ + } descriptor_chunk; /*!< Canonical WAVE format starts with the RIFF header */ + struct { + char subchunk_id[4]; /*!< Contains the letters "fmt " */ + uint32_t subchunk_size; /*!< This is the size of the rest of the Subchunk which follows this number */ + uint16_t audio_format; /*!< PCM = 1, values other than 1 indicate some form of compression */ + uint16_t num_of_channels; /*!< Mono = 1, Stereo = 2, etc. */ + uint32_t sample_rate; /*!< 8000, 44100, etc. */ + uint32_t byte_rate; /*!< ==SampleRate * NumChannels * BitsPerSample s/ 8 */ + uint16_t block_align; /*!< ==NumChannels * BitsPerSample / 8 */ + uint16_t bits_per_sample; /*!< 8 bits = 8, 16 bits = 16, etc. */ + } fmt_chunk; /*!< The "fmt " subchunk describes the sound data's format */ + struct { + char subchunk_id[4]; /*!< Contains the letters "data" */ + uint32_t subchunk_size; /*!< ==NumSamples * NumChannels * BitsPerSample / 8 */ + int16_t data[0]; /*!< Holds raw audio data */ + } data_chunk; /*!< The "data" subchunk contains the size of the data and the actual sound */ +} wav_header_t; + +/** + * @brief Default header for PCM format WAV files + * + */ +#define WAV_HEADER_PCM_DEFAULT(wav_sample_size, wav_sample_bits, wav_sample_rate, wav_channel_num) { \ + .descriptor_chunk = { \ + .chunk_id = {'R', 'I', 'F', 'F'}, \ + .chunk_size = (wav_sample_size) + sizeof(wav_header_t) - 8, \ + .chunk_format = {'W', 'A', 'V', 'E'} \ + }, \ + .fmt_chunk = { \ + .subchunk_id = {'f', 'm', 't', ' '}, \ + .subchunk_size = 16, /* 16 for PCM */ \ + .audio_format = 1, /* 1 for PCM */ \ + .num_of_channels = (wav_channel_num), \ + .sample_rate = (wav_sample_rate), \ + .byte_rate = (wav_sample_bits) * (wav_sample_rate) * (wav_channel_num) / 8, \ + .block_align = (wav_sample_bits) * (wav_channel_num) / 8, \ + .bits_per_sample = (wav_sample_bits)\ + }, \ + .data_chunk = { \ + .subchunk_id = {'d', 'a', 't', 'a'}, \ + .subchunk_size = (wav_sample_size) \ + } \ +} + +#ifdef __cplusplus +} +#endif diff --git a/examples/peripherals/i2s/i2s_adc_dac/main/CMakeLists.txt b/examples/peripherals/i2s/i2s_adc_dac/main/CMakeLists.txt index c31750a8f7..61fac40e63 100644 --- a/examples/peripherals/i2s/i2s_adc_dac/main/CMakeLists.txt +++ b/examples/peripherals/i2s/i2s_adc_dac/main/CMakeLists.txt @@ -1,3 +1,2 @@ idf_component_register(SRCS "app_main.c" INCLUDE_DIRS ".") -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/i2s/i2s_adc_dac/main/app_main.c b/examples/peripherals/i2s/i2s_adc_dac/main/app_main.c index 645c975503..7fa073b51e 100644 --- a/examples/peripherals/i2s/i2s_adc_dac/main/app_main.c +++ b/examples/peripherals/i2s/i2s_adc_dac/main/app_main.c @@ -78,8 +78,8 @@ void example_i2s_init(void) .communication_format = I2S_COMM_FORMAT_STAND_MSB, .channel_format = EXAMPLE_I2S_FORMAT, .intr_alloc_flags = 0, - .dma_desc_num = 2, - .dma_frame_num = 1024, + .dma_buf_count = 6, + .dma_buf_len = 256, .use_apll = 1, }; //install and start i2s driver @@ -101,7 +101,7 @@ void example_erase_flash(void) data_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_FAT, PARTITION_NAME); if (data_partition != NULL) { - printf("partiton addr: 0x%08x; size: %d; label: %s\n", data_partition->address, data_partition->size, data_partition->label); + printf("partiton addr: 0x%08"PRIx32"; size: %"PRIu32"; label: %s\n", data_partition->address, data_partition->size, data_partition->label); } printf("Erase size: %d Bytes\n", FLASH_ERASE_SIZE); ESP_ERROR_CHECK(esp_partition_erase_range(data_partition, 0, FLASH_ERASE_SIZE)); @@ -209,7 +209,7 @@ void example_i2s_adc_dac(void*arg) data_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_FAT, PARTITION_NAME); if (data_partition != NULL) { - printf("partiton addr: 0x%08x; size: %d; label: %s\n", data_partition->address, data_partition->size, data_partition->label); + printf("partiton addr: 0x%08"PRIx32"; size: %"PRIu32"; label: %s\n", data_partition->address, data_partition->size, data_partition->label); } else { ESP_LOGE(TAG, "Partition error: can't find partition name: %s\n", PARTITION_NAME); vTaskDelete(NULL); @@ -288,7 +288,7 @@ void adc_read_task(void* arg) uint32_t voltage; vTaskDelay(200 / portTICK_PERIOD_MS); esp_adc_cal_get_voltage(ADC1_TEST_CHANNEL, &characteristics, &voltage); - ESP_LOGI(TAG, "%d mV", voltage); + ESP_LOGI(TAG, "%"PRIu32" mV", voltage); } } diff --git a/examples/peripherals/i2s/i2s_adc_dac/tools/generate_audio_file.py b/examples/peripherals/i2s/i2s_adc_dac/tools/generate_audio_file.py index edc4ae3ea0..2d1a20fcac 100644 --- a/examples/peripherals/i2s/i2s_adc_dac/tools/generate_audio_file.py +++ b/examples/peripherals/i2s/i2s_adc_dac/tools/generate_audio_file.py @@ -1,11 +1,8 @@ # SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Unlicense OR CC0-1.0 -from __future__ import print_function - import os import struct import wave -from builtins import range try: from typing import List diff --git a/examples/peripherals/i2s/i2s_basic/i2s_pdm/main/i2s_pdm_rx.c b/examples/peripherals/i2s/i2s_basic/i2s_pdm/main/i2s_pdm_rx.c index 6b758b347f..dc44a3807d 100644 --- a/examples/peripherals/i2s/i2s_basic/i2s_pdm/main/i2s_pdm_rx.c +++ b/examples/peripherals/i2s/i2s_basic/i2s_pdm/main/i2s_pdm_rx.c @@ -60,6 +60,9 @@ void i2s_example_pdm_rx_task(void *args) i2s_chan_handle_t rx_chan = i2s_example_init_pdm_rx(); size_t r_bytes = 0; + /* ATTENTION: The print and delay in the read task only for monitoring the data by human, + * Normally there shouldn't be any delays to ensure a short polling time, + * Otherwise the dma buffer will overflow and lead to the data lost */ while (1) { /* Read i2s data */ if (i2s_channel_read(rx_chan, r_buf, EXAMPLE_BUFF_SIZE, &r_bytes, 1000) == ESP_OK) { diff --git a/examples/peripherals/i2s/i2s_basic/i2s_std/main/i2s_std_example_main.c b/examples/peripherals/i2s/i2s_basic/i2s_std/main/i2s_std_example_main.c index b46b41fff9..84a20b5d01 100644 --- a/examples/peripherals/i2s/i2s_basic/i2s_std/main/i2s_std_example_main.c +++ b/examples/peripherals/i2s/i2s_basic/i2s_std/main/i2s_std_example_main.c @@ -53,6 +53,9 @@ static void i2s_example_read_task(void *args) uint8_t *r_buf = (uint8_t *)calloc(1, EXAMPLE_BUFF_SIZE); assert(r_buf); // Check if r_buf allocation success size_t r_bytes = 0; + /* ATTENTION: The print and delay in the read task only for monitoring the data by human, + * Normally there shouldn't be any delays to ensure a short polling time, + * Otherwise the dma buffer will overflow and lead to the data lost */ while (1) { /* Read i2s data */ if (i2s_channel_read(rx_chan, r_buf, EXAMPLE_BUFF_SIZE, &r_bytes, 1000) == ESP_OK) { diff --git a/examples/peripherals/i2s/i2s_basic/i2s_tdm/main/i2s_tdm_example_main.c b/examples/peripherals/i2s/i2s_basic/i2s_tdm/main/i2s_tdm_example_main.c index c0c3536609..0fc04f713c 100644 --- a/examples/peripherals/i2s/i2s_basic/i2s_tdm/main/i2s_tdm_example_main.c +++ b/examples/peripherals/i2s/i2s_basic/i2s_tdm/main/i2s_tdm_example_main.c @@ -38,6 +38,9 @@ static void i2s_example_read_task(void *args) uint8_t *r_buf = (uint8_t *)calloc(1, EXAMPLE_BUFF_SIZE); assert(r_buf); // Check if r_buf allocation success size_t r_bytes = 0; + /* ATTENTION: The print and delay in the read task only for monitoring the data by human, + * Normally there shouldn't be any delays to ensure a short polling time, + * Otherwise the dma buffer will overflow and lead to the data lost */ while (1) { /* Read i2s data */ if (i2s_channel_read(rx_chan, r_buf, EXAMPLE_BUFF_SIZE, &r_bytes, 1000) == ESP_OK) { diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/CMakeLists.txt b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/CMakeLists.txt new file mode 100644 index 0000000000..28f0ad3ad3 --- /dev/null +++ b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/CMakeLists.txt @@ -0,0 +1,6 @@ +# The following lines of boilerplate have to be in your project's CMakeLists +# in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(es7210_tdm_record_example) diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/README.md b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/README.md new file mode 100644 index 0000000000..b4a4e857b5 --- /dev/null +++ b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/README.md @@ -0,0 +1,85 @@ +| Supported Targets | ESP32-C3 | ESP32-S3 | +| ----------------- | -------- | -------- | + +# I2S TDM Example -- ES7210 4-Ch ADC Codec + +(See the README.md file in the upper level 'examples' directory for more information about examples.) + +I2S on `ESP32S3` and `ESP32C3` supports [TDM mode](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-reference/peripherals/i2s.html#tdm-mode), in which multiple slots can be transmitted by standard I2S connection. + +This example demonstrates how to use I2S TDM mode to record 4 MICs connected to [ES7210](http://www.everest-semi.com/pdf/ES7210%20PB.pdf) codec. ES7210 has 4 TDM modes, which are `ES7210_I2S_FMT_I2S` `ES7210_I2S_FMT_LJ` `ES7210_I2S_FMT_DSP_A` and `ES7210_I2S_FMT_DSP_B`, and they are all supported by I2S TDM driver. Relation between ES7210 TDM modes and I2S Driver TDM modes is shown in the following table. + +| Mode of ES7210 TDM | Mode of I2S Driver TDM | +| :------------------: | :--------------------: | +| ES7210_I2S_FMT_I2S | Philip format | +| ES7210_I2S_FMT_LJ | MSB format | +| ES7210_I2S_FMT_DSP_A | PCM short format | +| ES7210_I2S_FMT_DSP_B | PCM long format | + +Recorded voice will be saved to SD card in `wav` format, and can be played or processed on PC. + +## How to Use Example + +### Hardware Required + +* A development board with any supported Espressif SOC chip (see `Supported Targets` table above) +* An ES7210 module with 4 MICs connected +* A SPI SD card module +* A SD card reader and a PC (if you want to play recorded voice) + +All the GPIO used in this example can be changed according to your board, by macros `EXAMPLE_xxx_IO` defined at the beginning of [i2s_es7210_record_example.c](main/i2s_es7210_record_example.c). + +### Configure the project + +* Set the target of the build by following command, where TARGET can be `esp32s3` or `esp32c3`. +``` +idf.py set-target TARGET +``` +* Change value of `EXAMPLE_I2S_FORMAT` to check I2S driver's functionality on different I2S formats. +* Change `EXAMPLE_ES7210_MIC_GAIN` and `EXAMPLE_ES7210_MIC_BIAS` accoirding your MIC's specs if needed. +* Change `EXAMPLE_ES7210_ADC_VOLUME` if recorded voice is too loud or too quite. + +Note: it's better to adjust `EXAMPLE_ES7210_MIC_GAIN` first. If adjusting MIC gain doesn't meet your demand, you can then adjust `EXAMPLE_ES7210_ADC_VOLUME`. That is to say, it's better to adjust analog gain than digital gain. + +### Build and Flash + +Run `idf.py -p PORT flash monitor` to build, flash and monitor the project. + +(To exit the serial monitor, type ``Ctrl-]``.) + +See the [Getting Started Guide](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/index.html) for full steps to configure and use ESP-IDF to build projects. + +## Console Output + +``` +I (277) cpu_start: Starting scheduler. +I (281) example: Create I2S receive channel +I (281) example: Configure I2S receive channel to TDM mode +I (291) example: Init I2C used to configure ES7210 +I (291) example: Configure ES7210 codec parameters +I (301) ES7210: format: standard i2s, bit width: 16, tdm mode enabled +I (311) ES7210: sample rate: 48000Hz, mclk frequency: 12288000Hz +I (311) example: Initializing SPI bus for SD card +I (321) example: Mounting SD card +I (321) gpio: GPIO[4]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0 +I (371) sdspi_transaction: cmd=5, R1 response: command not supported +I (381) example: Card size: 14772MB, speed: 20MHz +I (381) example: Opening file /RECORD.WAV +I (391) example: Recording: 1/10s +I (1401) example: Recording: 2/10s +I (2411) example: Recording: 3/10s +I (3401) example: Recording: 4/10s +I (4411) example: Recording: 5/10s +I (5411) example: Recording: 6/10s +I (6421) example: Recording: 7/10s +I (7411) example: Recording: 8/10s +I (8411) example: Recording: 9/10s +I (9401) example: Recording: 10/10s +I (10401) example: Recording done! Flushing file buffer +I (10431) gpio: GPIO[4]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0 +I (10431) example: You can now safely remove the card, recorded file is /RECORD.WAV +``` + +## Troubleshooting + +For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon. diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/components/es7210/CMakeLists.txt b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/components/es7210/CMakeLists.txt new file mode 100644 index 0000000000..026081fca6 --- /dev/null +++ b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/components/es7210/CMakeLists.txt @@ -0,0 +1,4 @@ +idf_component_register(SRCS "es7210.c" + INCLUDE_DIRS "." + PRIV_REQUIRES driver +) diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/components/es7210/es7210.c b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/components/es7210/es7210.c new file mode 100644 index 0000000000..479e67a4a5 --- /dev/null +++ b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/components/es7210/es7210.c @@ -0,0 +1,341 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "es7210.h" +#include "esp_log.h" +#include "esp_check.h" + +const static char *TAG = "ES7210"; + +#define IS_ES7210_I2S_FMT(val) (((val)==ES7210_I2S_FMT_I2S) || ((val)==ES7210_I2S_FMT_LJ) || \ + ((val)==ES7210_I2S_FMT_DSP_A) || ((val)==ES7210_I2S_FMT_DSP_B)) + +#define IS_ES7210_I2S_BITS(val) (((val)==ES7210_I2S_BITS_24B) || ((val)==ES7210_I2S_BITS_20B) || \ + ((val)==ES7210_I2S_BITS_18B) || ((val)==ES7210_I2S_BITS_16B) || ((val)==ES7210_I2S_BITS_32B)) + +#define IS_ES7210_MIC_GAIN(val) (((val) >= ES7210_MIC_GAIN_0DB) && ((val) <= ES7210_MIC_GAIN_37_5DB)) + +#define IS_ES7210_MIC_BIAS(val) (((val)==ES7210_MIC_BIAS_2V18) || ((val)==ES7210_MIC_BIAS_2V26) || \ + ((val)==ES7210_MIC_BIAS_2V36) || ((val)==ES7210_MIC_BIAS_2V45) || ((val)==ES7210_MIC_BIAS_2V55) || \ + ((val)==ES7210_MIC_BIAS_2V66) || ((val)==ES7210_MIC_BIAS_2V78) || ((val)==ES7210_MIC_BIAS_2V87)) + +#define ES7210_WRITE_REG(reg_addr, reg_value) do { \ + ESP_RETURN_ON_ERROR(es7210_write_reg(handle, (reg_addr), (reg_value)), \ + TAG, "i2c communication error while writing "#reg_addr); \ +} while(0) + +struct es7210_dev_t { + i2c_port_t i2c_port; // TODO: update to i2c handle in future driver-NG + uint8_t i2c_addr; +}; + +/** + * @brief Clock coefficient structure + * + */ +typedef struct { + uint32_t mclk; /*!< mclk frequency */ + uint32_t lrck; /*!< lrck */ + uint8_t ss_ds; /*!< not used */ + uint8_t adc_div; /*!< adcclk divider */ + uint8_t dll; /*!< dll_bypass */ + uint8_t doubler; /*!< doubler enable */ + uint8_t osr; /*!< adc osr */ + uint8_t mclk_src; /*!< select mclk source */ + uint32_t lrck_h; /*!< The high 4 bits of lrck */ + uint32_t lrck_l; /*!< The low 8 bits of lrck */ +} coeff_div_t; + +/** + * @brief ES7210 clock coefficient lookup table + * + */ +static const coeff_div_t es7210_coeff_div[] = { +// mclk lrck ss_ds adc_div dll doubler osr mclk_src lrckh lrckl + /* 8k */ + {12288000, 8000 , 0x00, 0x03, 0x01, 0x00, 0x20, 0x00, 0x06, 0x00}, + {16384000, 8000 , 0x00, 0x04, 0x01, 0x00, 0x20, 0x00, 0x08, 0x00}, + {19200000, 8000 , 0x00, 0x1e, 0x00, 0x01, 0x28, 0x00, 0x09, 0x60}, + {4096000, 8000 , 0x00, 0x01, 0x01, 0x00, 0x20, 0x00, 0x02, 0x00}, + + /* 11.025k */ + {11289600, 11025, 0x00, 0x02, 0x01, 0x00, 0x20, 0x00, 0x01, 0x00}, + + /* 12k */ + {12288000, 12000, 0x00, 0x02, 0x01, 0x00, 0x20, 0x00, 0x04, 0x00}, + {19200000, 12000, 0x00, 0x14, 0x00, 0x01, 0x28, 0x00, 0x06, 0x40}, + + /* 16k */ + {4096000, 16000, 0x00, 0x01, 0x01, 0x01, 0x20, 0x00, 0x01, 0x00}, + {19200000, 16000, 0x00, 0x0a, 0x00, 0x00, 0x1e, 0x00, 0x04, 0x80}, + {16384000, 16000, 0x00, 0x02, 0x01, 0x00, 0x20, 0x00, 0x04, 0x00}, + {12288000, 16000, 0x00, 0x03, 0x01, 0x01, 0x20, 0x00, 0x03, 0x00}, + + /* 22.05k */ + {11289600, 22050, 0x00, 0x01, 0x01, 0x00, 0x20, 0x00, 0x02, 0x00}, + + /* 24k */ + {12288000, 24000, 0x00, 0x01, 0x01, 0x00, 0x20, 0x00, 0x02, 0x00}, + {19200000, 24000, 0x00, 0x0a, 0x00, 0x01, 0x28, 0x00, 0x03, 0x20}, + + /* 32k */ + {12288000, 32000, 0x00, 0x03, 0x00, 0x00, 0x20, 0x00, 0x01, 0x80}, + {16384000, 32000, 0x00, 0x01, 0x01, 0x00, 0x20, 0x00, 0x02, 0x00}, + {19200000, 32000, 0x00, 0x05, 0x00, 0x00, 0x1e, 0x00, 0x02, 0x58}, + + /* 44.1k */ + {11289600, 44100, 0x00, 0x01, 0x01, 0x01, 0x20, 0x00, 0x01, 0x00}, + + /* 48k */ + {12288000, 48000, 0x00, 0x01, 0x01, 0x01, 0x20, 0x00, 0x01, 0x00}, + {19200000, 48000, 0x00, 0x05, 0x00, 0x01, 0x28, 0x00, 0x01, 0x90}, + + /* 64k */ + {16384000, 64000, 0x01, 0x01, 0x01, 0x00, 0x20, 0x00, 0x01, 0x00}, + {19200000, 64000, 0x00, 0x05, 0x00, 0x01, 0x1e, 0x00, 0x01, 0x2c}, + + /* 88.2k */ + {11289600, 88200, 0x01, 0x01, 0x01, 0x01, 0x20, 0x00, 0x00, 0x80}, + + /* 96k */ + {12288000, 96000, 0x01, 0x01, 0x01, 0x01, 0x20, 0x00, 0x00, 0x80}, + {19200000, 96000, 0x01, 0x05, 0x00, 0x01, 0x28, 0x00, 0x00, 0xc8}, +}; + +/** + * @brief Get coefficient from coefficient table + * + * @param mclk Desired MCLK value + * @param lrck Desired LRCK vaule + * @return Coefficient struct, NULL if desired value cannot be achieved + */ +static const coeff_div_t *es7210_get_coeff(uint32_t mclk, uint32_t lrck) +{ + for (int i = 0; i < sizeof(es7210_coeff_div) / sizeof(coeff_div_t); i++) { + if (es7210_coeff_div[i].lrck == lrck && es7210_coeff_div[i].mclk == mclk) + return &es7210_coeff_div[i]; + } + return NULL; +} + +static esp_err_t es7210_write_reg(es7210_dev_handle_t handle, uint8_t reg_addr, uint8_t reg_val) +{ + ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_ARG, TAG, "invalid device handle"); + esp_err_t ret = ESP_OK; + + i2c_cmd_handle_t cmd = i2c_cmd_link_create(); + ESP_GOTO_ON_FALSE(cmd, ESP_ERR_NO_MEM, err, TAG, "memory allocation for i2c cmd handle failed"); + + ESP_GOTO_ON_ERROR(i2c_master_start(cmd), err, TAG, "error while appending i2c command"); + ESP_GOTO_ON_ERROR(i2c_master_write_byte(cmd, handle->i2c_addr<<1 | I2C_MASTER_WRITE, true), + err, TAG, "error while appending i2c command"); + ESP_GOTO_ON_ERROR(i2c_master_write_byte(cmd, reg_addr, true), err, + TAG, "error while appending i2c command"); + ESP_GOTO_ON_ERROR(i2c_master_write_byte(cmd, reg_val, true), err, + TAG, "error while appending i2c command"); + ESP_GOTO_ON_ERROR(i2c_master_stop(cmd), err, TAG, "error while appending i2c command"); + + ESP_GOTO_ON_ERROR(i2c_master_cmd_begin(handle->i2c_port, cmd, pdMS_TO_TICKS(1000)), + err, TAG, "error while writing register"); +err: + if(cmd) { + i2c_cmd_link_delete(cmd); + } + return ret; +} + +static esp_err_t es7210_set_i2s_format(es7210_dev_handle_t handle, es7210_i2s_fmt_t i2s_format, + es7210_i2s_bits_t bit_width, bool tdm_enable) +{ + ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_ARG, TAG, "invalid device handle pointer"); + ESP_RETURN_ON_FALSE(IS_ES7210_I2S_FMT(i2s_format), ESP_ERR_INVALID_ARG, TAG, "invalid i2s format argument"); + ESP_RETURN_ON_FALSE(IS_ES7210_I2S_BITS(bit_width), ESP_ERR_INVALID_ARG, TAG, "invalid i2s bit width argument"); + + uint8_t reg_val = 0; + + switch (bit_width) { + case ES7210_I2S_BITS_16B: + reg_val = 0x60; + break; + case ES7210_I2S_BITS_18B: + reg_val = 0x40; + break; + case ES7210_I2S_BITS_20B: + reg_val = 0x20; + break; + case ES7210_I2S_BITS_24B: + reg_val = 0x00; + break; + case ES7210_I2S_BITS_32B: + reg_val = 0x80; + break; + default: + abort(); + } + ES7210_WRITE_REG(ES7210_SDP_INTERFACE1_REG11, i2s_format | reg_val); + + const char *mode_str = NULL; + switch (i2s_format) { + case ES7210_I2S_FMT_I2S: + reg_val = 0x02; + mode_str = "standard i2s"; + break; + case ES7210_I2S_FMT_LJ: + reg_val = 0x02; + mode_str = "left justify"; + break; + case ES7210_I2S_FMT_DSP_A: + reg_val = 0x01; + mode_str = "DSP-A"; + break; + case ES7210_I2S_FMT_DSP_B: + reg_val = 0x01; + mode_str = "DSP-B"; + break; + default: + abort(); + } + + if (tdm_enable) { // enable 1xFS TDM + ES7210_WRITE_REG(ES7210_SDP_INTERFACE2_REG12, reg_val); + } else { + ES7210_WRITE_REG(ES7210_SDP_INTERFACE2_REG12, 0x00); + } + + ESP_LOGI(TAG, "format: %s, bit width: %d, tdm mode %s", mode_str, bit_width, tdm_enable ? "enabled" : "disabled"); + return ESP_OK; +} + +static esp_err_t es7210_set_i2s_sample_rate(es7210_dev_handle_t handle, uint32_t sample_rate_hz, uint32_t mclk_ratio) +{ + ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_ARG, TAG, "invalid device handle pointer"); + + uint32_t mclk_freq_hz = sample_rate_hz * mclk_ratio; + const coeff_div_t *coeff_div = es7210_get_coeff(mclk_freq_hz, sample_rate_hz); + ESP_RETURN_ON_FALSE(coeff_div, ESP_ERR_NOT_SUPPORTED, TAG, + "unable to set %"PRIu32"Hz sample rate with %"PRIu32"Hz MCLK", sample_rate_hz, mclk_freq_hz); + /* Set osr */ + ES7210_WRITE_REG(ES7210_OSR_REG07, coeff_div->osr); + /* Set adc_div & doubler & dll */ + ES7210_WRITE_REG(ES7210_MAINCLK_REG02, (coeff_div->adc_div) | (coeff_div->doubler << 6) | (coeff_div->dll << 7)); + /* Set lrck */ + ES7210_WRITE_REG(ES7210_LRCK_DIVH_REG04, coeff_div->lrck_h); + ES7210_WRITE_REG(ES7210_LRCK_DIVL_REG05, coeff_div->lrck_l); + + ESP_LOGI(TAG, "sample rate: %"PRIu32"Hz, mclk frequency: %"PRIu32"Hz", sample_rate_hz, mclk_freq_hz); + return ESP_OK; +} + +static esp_err_t es7210_set_mic_gain(es7210_dev_handle_t handle, es7210_mic_gain_t mic_gain) +{ + ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_ARG, TAG, "invalid device handle pointer"); + ESP_RETURN_ON_FALSE(IS_ES7210_MIC_GAIN(mic_gain), ESP_ERR_INVALID_ARG, TAG, "invalid mic gain value"); + + ES7210_WRITE_REG(ES7210_MIC1_GAIN_REG43, mic_gain | 0x10); + ES7210_WRITE_REG(ES7210_MIC2_GAIN_REG44, mic_gain | 0x10); + ES7210_WRITE_REG(ES7210_MIC3_GAIN_REG45, mic_gain | 0x10); + ES7210_WRITE_REG(ES7210_MIC4_GAIN_REG46, mic_gain | 0x10); + + return ESP_OK; +} + +static esp_err_t es7210_set_mic_bias(es7210_dev_handle_t handle, es7210_mic_bias_t mic_bias) +{ + ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_ARG, TAG, "invalid device handle pointer"); + ESP_RETURN_ON_FALSE(IS_ES7210_MIC_BIAS(mic_bias), ESP_ERR_INVALID_ARG, TAG, "invalid mic bias value"); + + ES7210_WRITE_REG(ES7210_MIC12_BIAS_REG41, mic_bias); + ES7210_WRITE_REG(ES7210_MIC34_BIAS_REG42, mic_bias); + + return ESP_OK; +} + +esp_err_t es7210_new_codec(const es7210_i2c_config_t *i2c_conf, es7210_dev_handle_t *handle_out) +{ + ESP_RETURN_ON_FALSE(i2c_conf, ESP_ERR_INVALID_ARG, TAG, "invalid device config pointer"); + ESP_RETURN_ON_FALSE(handle_out, ESP_ERR_INVALID_ARG, TAG, "invalid device handle pointer"); + + struct es7210_dev_t *handle = calloc(1, sizeof(struct es7210_dev_t)); + ESP_RETURN_ON_FALSE(handle, ESP_ERR_NO_MEM, TAG, "memory allocation for device handler failed"); + + handle->i2c_port = i2c_conf->i2c_port; // TODO: check i2c handle in future driver-NG + handle->i2c_addr = i2c_conf->i2c_addr; + + *handle_out = handle; + return ESP_OK; +} + +esp_err_t es7210_del_codec(es7210_dev_handle_t handle) +{ + ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_ARG, TAG, "invalid device handle pointer"); + + free(handle); + + return ESP_OK; +} + +esp_err_t es7210_config_codec(es7210_dev_handle_t handle, const es7210_codec_config_t *codec_conf) +{ + ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_ARG, TAG, "invalid device handle pointer"); + ESP_RETURN_ON_FALSE(codec_conf, ESP_ERR_INVALID_ARG, TAG, "invalid codec config pointer"); + + /* Perform software reset */ + ES7210_WRITE_REG(ES7210_RESET_REG00, 0xFF); + ES7210_WRITE_REG(ES7210_RESET_REG00, 0x32); + /* Set the initialization time when device powers up */ + ES7210_WRITE_REG(ES7210_TIME_CONTROL0_REG09, 0x30); + ES7210_WRITE_REG(ES7210_TIME_CONTROL1_REG0A, 0x30); + /* Configure HPF for ADC1-4 */ + ES7210_WRITE_REG(ES7210_ADC12_HPF1_REG23, 0x2A); + ES7210_WRITE_REG(ES7210_ADC12_HPF2_REG22, 0x0A); + ES7210_WRITE_REG(ES7210_ADC34_HPF1_REG21, 0x2A); + ES7210_WRITE_REG(ES7210_ADC34_HPF2_REG20, 0x0A); + /* Set bits per sample to 16, data protocal to I2S, enable 1xFS TDM */ + ESP_RETURN_ON_ERROR(es7210_set_i2s_format(handle, codec_conf->i2s_format, codec_conf->bit_width, + codec_conf->flags.tdm_enable), TAG, "error while setting i2s format"); + /* Configure analog power and VMID voltage */ + ES7210_WRITE_REG(ES7210_ANALOG_REG40, 0xC3); + /* Set MIC14 bias to 2.87V */ + ESP_RETURN_ON_ERROR(es7210_set_mic_bias(handle, codec_conf->mic_bias), TAG, "error while setting mic bias"); + /* Set MIC1-4 gain to 30dB */ + ESP_RETURN_ON_ERROR(es7210_set_mic_gain(handle, codec_conf->mic_gain), TAG, "error while setting mic gain"); + /* Power on MIC1-4 */ + ES7210_WRITE_REG(ES7210_MIC1_POWER_REG47, 0x08); + ES7210_WRITE_REG(ES7210_MIC2_POWER_REG48, 0x08); + ES7210_WRITE_REG(ES7210_MIC3_POWER_REG49, 0x08); + ES7210_WRITE_REG(ES7210_MIC4_POWER_REG4A, 0x08); + /* Set ADC sample rate to 48kHz */ + ESP_RETURN_ON_ERROR(es7210_set_i2s_sample_rate(handle, codec_conf->sample_rate_hz, codec_conf->mclk_ratio), + TAG, "error while setting sample rate"); + /* Power down DLL */ + ES7210_WRITE_REG(ES7210_POWER_DOWN_REG06, 0x04); + /* Power on MIC1-4 bias & ADC1-4 & PGA1-4 Power */ + ES7210_WRITE_REG(ES7210_MIC12_POWER_REG4B, 0x0F); + ES7210_WRITE_REG(ES7210_MIC34_POWER_REG4C, 0x0F); + /* Enable device */ + ES7210_WRITE_REG(ES7210_RESET_REG00, 0x71); + ES7210_WRITE_REG(ES7210_RESET_REG00, 0x41); + + return ESP_OK; +} + +esp_err_t es7210_config_volume(es7210_dev_handle_t handle, int8_t volume_db) +{ + ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_ARG, TAG, "invalid device handle pointer"); + ESP_RETURN_ON_FALSE(volume_db >= -95 && volume_db <= 32, ESP_ERR_INVALID_ARG, TAG, "invalid volume range"); + + /* + * reg_val: 0x00 represents -95.5dB, 0xBF represents 0dB (default after reset), + * and 0xFF represents +32dB, with a 0.5dB step + */ + uint8_t reg_val = 191 + volume_db * 2; + + ES7210_WRITE_REG(ES7210_ADC1_DIRECT_DB_REG1B, reg_val); + ES7210_WRITE_REG(ES7210_ADC2_DIRECT_DB_REG1C, reg_val); + ES7210_WRITE_REG(ES7210_ADC3_DIRECT_DB_REG1D, reg_val); + ES7210_WRITE_REG(ES7210_ADC4_DIRECT_DB_REG1E, reg_val); + + return ESP_OK; +} diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/components/es7210/es7210.h b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/components/es7210/es7210.h new file mode 100644 index 0000000000..3051e96f3d --- /dev/null +++ b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/components/es7210/es7210.h @@ -0,0 +1,203 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "esp_err.h" +#include "driver/i2c.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* ES7210 register addresses */ +#define ES7210_RESET_REG00 0x00 /* Reset control */ +#define ES7210_CLOCK_OFF_REG01 0x01 /* Used to turn off the ADC clock */ +#define ES7210_MAINCLK_REG02 0x02 /* Set ADC clock frequency division */ +#define ES7210_MASTER_CLK_REG03 0x03 /* MCLK source $ SCLK division */ +#define ES7210_LRCK_DIVH_REG04 0x04 /* lrck_divh */ +#define ES7210_LRCK_DIVL_REG05 0x05 /* lrck_divl */ +#define ES7210_POWER_DOWN_REG06 0x06 /* power down */ +#define ES7210_OSR_REG07 0x07 +#define ES7210_MODE_CONFIG_REG08 0x08 /* Set master/slave & channels */ +#define ES7210_TIME_CONTROL0_REG09 0x09 /* Set Chip intial state period*/ +#define ES7210_TIME_CONTROL1_REG0A 0x0A /* Set Power up state period */ +#define ES7210_SDP_INTERFACE1_REG11 0x11 /* Set sample & fmt */ +#define ES7210_SDP_INTERFACE2_REG12 0x12 /* Pins state */ +#define ES7210_ADC_AUTOMUTE_REG13 0x13 /* Set mute */ +#define ES7210_ADC34_MUTERANGE_REG14 0x14 /* Set mute range */ +#define ES7210_ALC_SEL_REG16 0x16 /* Set ALC mode */ +#define ES7210_ADC1_DIRECT_DB_REG1B 0x1B +#define ES7210_ADC2_DIRECT_DB_REG1C 0x1C +#define ES7210_ADC3_DIRECT_DB_REG1D 0x1D +#define ES7210_ADC4_DIRECT_DB_REG1E 0x1E /* ADC direct dB when ALC close, ALC max gain when ALC open */ +#define ES7210_ADC34_HPF2_REG20 0x20 /* HPF */ +#define ES7210_ADC34_HPF1_REG21 0x21 +#define ES7210_ADC12_HPF2_REG22 0x22 +#define ES7210_ADC12_HPF1_REG23 0x23 +#define ES7210_ANALOG_REG40 0x40 /* ANALOG Power */ +#define ES7210_MIC12_BIAS_REG41 0x41 +#define ES7210_MIC34_BIAS_REG42 0x42 +#define ES7210_MIC1_GAIN_REG43 0x43 +#define ES7210_MIC2_GAIN_REG44 0x44 +#define ES7210_MIC3_GAIN_REG45 0x45 +#define ES7210_MIC4_GAIN_REG46 0x46 +#define ES7210_MIC1_POWER_REG47 0x47 +#define ES7210_MIC2_POWER_REG48 0x48 +#define ES7210_MIC3_POWER_REG49 0x49 +#define ES7210_MIC4_POWER_REG4A 0x4A +#define ES7210_MIC12_POWER_REG4B 0x4B /* MICBias & ADC & PGA Power */ +#define ES7210_MIC34_POWER_REG4C 0x4C + +/** + * @brief Select I2S interface format for ES7210 + */ +typedef enum { + ES7210_I2S_FMT_I2S = 0x00, /*!< normal I2S format */ + ES7210_I2S_FMT_LJ = 0x01, /*!< left justify format */ + ES7210_I2S_FMT_DSP_A = 0x03, /*!< DSP-A format, MSB is available on 2nd SCLK rising edge after LRCK rising edge */ + ES7210_I2S_FMT_DSP_B = 0x13 /*!< DSP-B format, MSB is available on 1st SCLK rising edge after LRCK rising edge */ +} es7210_i2s_fmt_t; + +/** + * @brief Select I2S bit width for ES7210 + * + */ +typedef enum { + ES7210_I2S_BITS_16B = 16, /*!< 16-bit I2S mode */ + ES7210_I2S_BITS_18B = 18, /*!< 18-bit I2S mode */ + ES7210_I2S_BITS_20B = 20, /*!< 20-bit I2S mode */ + ES7210_I2S_BITS_24B = 24, /*!< 24-bit I2S mode */ + ES7210_I2S_BITS_32B = 32 /*!< 32-bit I2S mode */ +} es7210_i2s_bits_t; + +/** + * @brief Select MIC gain for ES7210 + * + */ +typedef enum { + ES7210_MIC_GAIN_0DB = 0, /*!< 0dB MIC gain */ + ES7210_MIC_GAIN_3DB = 1, /*!< 3dB MIC gain */ + ES7210_MIC_GAIN_6DB = 2, /*!< 6dB MIC gain */ + ES7210_MIC_GAIN_9DB = 3, /*!< 9dB MIC gain */ + ES7210_MIC_GAIN_12DB = 4, /*!< 12dB MIC gain */ + ES7210_MIC_GAIN_15DB = 5, /*!< 15dB MIC gain */ + ES7210_MIC_GAIN_18DB = 6, /*!< 18dB MIC gain */ + ES7210_MIC_GAIN_21DB = 7, /*!< 21dB MIC gain */ + ES7210_MIC_GAIN_24DB = 8, /*!< 24dB MIC gain */ + ES7210_MIC_GAIN_27DB = 9, /*!< 27dB MIC gain */ + ES7210_MIC_GAIN_30DB = 10, /*!< 30dB MIC gain */ + ES7210_MIC_GAIN_33DB = 11, /*!< 33dB MIC gain */ + ES7210_MIC_GAIN_34_5DB = 12, /*!< 34.5dB MIC gain */ + ES7210_MIC_GAIN_36DB = 13, /*!< 36dB MIC gain */ + ES7210_MIC_GAIN_37_5DB = 14 /*!< 37.5dB MIC gain */ +} es7210_mic_gain_t; + +/** + * @brief Select MIC bias for ES7210 + * + */ +typedef enum { + ES7210_MIC_BIAS_2V18 = 0x00, /*!< 2.18V MIC bias */ + ES7210_MIC_BIAS_2V26 = 0x10, /*!< 2.26V MIC bias */ + ES7210_MIC_BIAS_2V36 = 0x20, /*!< 2.36V MIC bias */ + ES7210_MIC_BIAS_2V45 = 0x30, /*!< 2.45V MIC bias */ + ES7210_MIC_BIAS_2V55 = 0x40, /*!< 2.55V MIC bias */ + ES7210_MIC_BIAS_2V66 = 0x50, /*!< 2.66V MIC bias */ + ES7210_MIC_BIAS_2V78 = 0x60, /*!< 2.78V MIC bias */ + ES7210_MIC_BIAS_2V87 = 0x70 /*!< 2.87V MIC bias */ +} es7210_mic_bias_t; + +/** + * @brief Type of es7210 device handle + * + */ +typedef struct es7210_dev_t* es7210_dev_handle_t; + +/** + * @brief ES7210 I2C config struct + * + */ +typedef struct { + i2c_port_t i2c_port; /*!< I2C port used to connecte ES7210 device */ + uint8_t i2c_addr; /*!< I2C address of ES7210 device, can be 0x40 0x41 0x42 or 0x43 according to A0 and A1 pin */ +} es7210_i2c_config_t; + +/** + * @brief ES7210 codec config struct + * + */ +typedef struct { + uint32_t sample_rate_hz; /*!< Sample rate in Hz, common values are supported */ + uint32_t mclk_ratio; /*!< MCLK-to-Sample-rate clock ratio, typically 256 */ + es7210_i2s_fmt_t i2s_format; /*!< I2S format of ES7210's output, can be any value in es7210_i2s_fmt_t */ + es7210_i2s_bits_t bit_width; /*!< I2S bit width of ES7210's output, can be any value in es7210_i2s_bits_t */ + es7210_mic_bias_t mic_bias; /*!< Bias volatge of analog MIC, please refer to your MIC's datasheet */ + es7210_mic_gain_t mic_gain; /*!< Gain of analog MIC, please adjust according to your MIC's sensitivity */ + struct { + uint32_t tdm_enable:1; /*!< Choose whether to enable TDM mode */ + } flags; +} es7210_codec_config_t; + +/** + * @brief Create new ES7210 device handle. + * + * @param[in] i2c_conf Config for I2C used by ES7210 + * @param[out] handle_out New ES7210 device handle + * @return + * - ESP_OK Device handle creation success. + * - ESP_ERR_INVALID_ARG Invalid device handle or argument. + * - ESP_ERR_NO_MEM Memory allocation failed. + * + */ +esp_err_t es7210_new_codec(const es7210_i2c_config_t *i2c_conf, es7210_dev_handle_t *handle_out); + +/** + * @brief Delete ES7210 device handle. + * + * @param[in] handle ES7210 device handle + * @return + * - ESP_OK Device handle deletion success. + * - ESP_ERR_INVALID_ARG Invalid device handle or argument. + * + */ +esp_err_t es7210_del_codec(es7210_dev_handle_t handle); + +/** + * @brief Configure codec-related parameters of ES7210. + * + * @param[in] handle ES7210 device handle + * @param codec_conf codec-related parameters of ES7210 + * @return + * - ESP_OK Codec config success. + * - ESP_ERR_INVALID_ARG Invalid device handle or argument. + * - ESP_ERR_NO_MEM Memory allocation failed. + * - ESP_FAIL Sending command error, slave hasn't ACK the transfer. + * - ESP_ERR_INVALID_STATE I2C driver not installed or not in master mode. + * - ESP_ERR_TIMEOUT Operation timeout because the bus is busy. + * + */ +esp_err_t es7210_config_codec(es7210_dev_handle_t handle, const es7210_codec_config_t *codec_conf); + +/** + * @brief Configure volume of ES7210. + * + * @param[in] handle ES7210 device handle + * @param volume_db Volume to be set, in dB, with a range from -95dB to +32dB. + * @return + * - ESP_OK Volume config success. + * - ESP_ERR_INVALID_ARG Invalid device handle or argument. + * - ESP_ERR_NO_MEM Memory allocation failed. + * - ESP_FAIL Sending command error, slave hasn't ACK the transfer. + * - ESP_ERR_INVALID_STATE I2C driver not installed or not in master mode. + * - ESP_ERR_TIMEOUT Operation timeout because the bus is busy. + * + */ +esp_err_t es7210_config_volume(es7210_dev_handle_t handle, int8_t volume_db); + +#ifdef __cplusplus +} +#endif diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/CMakeLists.txt b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/CMakeLists.txt new file mode 100644 index 0000000000..223b8f8931 --- /dev/null +++ b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/CMakeLists.txt @@ -0,0 +1,3 @@ +idf_component_register(SRCS "i2s_es7210_record_example.c" + INCLUDE_DIRS "../../../common" +) diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/i2s_es7210_record_example.c b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/i2s_es7210_record_example.c new file mode 100644 index 0000000000..15c855f916 --- /dev/null +++ b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/i2s_es7210_record_example.c @@ -0,0 +1,259 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include +#include "sdkconfig.h" +#include "esp_check.h" +#include "esp_vfs_fat.h" +#include "driver/i2s_tdm.h" +#include "driver/i2c.h" +#include "es7210.h" +#include "format_wav.h" + +#if CONFIG_IDF_TARGET_ESP32S3 // ESP32-S3-Korvo-1 pinout +/* I2C port and GPIOs */ +#define EXAMPLE_I2C_NUM (0) +#define EXAMPLE_I2C_SDA_IO (1) +#define EXAMPLE_I2C_SCL_IO (2) + +/* I2S port and GPIOs */ +#define EXAMPLE_I2S_NUM (0) +#define EXAMPLE_I2S_MCK_IO (20) +#define EXAMPLE_I2S_BCK_IO (10) +#define EXAMPLE_I2S_WS_IO (9) +#define EXAMPLE_I2S_DI_IO (11) + +/* SD card SPI GPIOs */ +#define EXAMPLE_SD_SPI_CLK_IO (18) +#define EXAMPLE_SD_SPI_MOSI_IO (17) +#define EXAMPLE_SD_SPI_MISO_IO (16) +#define EXAMPLE_SD_SPI_CS_IO (15) +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 +#define EXAMPLE_I2C_NUM (0) +#define EXAMPLE_I2C_SDA_IO (3) +#define EXAMPLE_I2C_SCL_IO (2) + +/* I2S port and GPIOs */ +#define EXAMPLE_I2S_NUM (0) +#define EXAMPLE_I2S_MCK_IO (0) +#define EXAMPLE_I2S_BCK_IO (1) +#define EXAMPLE_I2S_WS_IO (10) +#define EXAMPLE_I2S_DI_IO (8) + +/* SD card SPI GPIOs */ +#define EXAMPLE_SD_SPI_CLK_IO (5) +#define EXAMPLE_SD_SPI_MOSI_IO (7) +#define EXAMPLE_SD_SPI_MISO_IO (6) +#define EXAMPLE_SD_SPI_CS_IO (4) +#endif + +/* I2S configurations */ +#define EXAMPLE_I2S_TDM_FORMAT (ES7210_I2S_FMT_I2S) +#define EXAMPLE_I2S_CHAN_NUM (4) +#define EXAMPLE_I2S_SAMPLE_RATE (48000) +#define EXAMPLE_I2S_MCLK_MULTIPLE (I2S_MCLK_MULTIPLE_256) +#define EXAMPLE_I2S_SAMPLE_BITS (I2S_DATA_BIT_WIDTH_16BIT) +#define EXAMPLE_I2S_TDM_SLOT_MASK (I2S_TDM_SLOT0 | I2S_TDM_SLOT1 | I2S_TDM_SLOT2 | I2S_TDM_SLOT3) + +/* ES7210 configurations */ +#define EXAMPLE_ES7210_I2C_ADDR (0x40) +#define EXAMPLE_ES7210_I2C_CLK (100000) +#define EXAMPLE_ES7210_MIC_GAIN (ES7210_MIC_GAIN_30DB) +#define EXAMPLE_ES7210_MIC_BIAS (ES7210_MIC_BIAS_2V87) +#define EXAMPLE_ES7210_ADC_VOLUME (0) + +/* SD card & recording configurations */ +#define EXAMPLE_RECORD_TIME_SEC (10) +#define EXAMPLE_SD_MOUNT_POINT "/sdcard" +#define EXAMPLE_RECORD_FILE_PATH "/RECORD.WAV" + +static const char *TAG = "example"; + + +static i2s_chan_handle_t es7210_i2s_init(void) +{ + i2s_chan_handle_t i2s_rx_chan = NULL; + ESP_LOGI(TAG, "Create I2S receive channel"); + i2s_chan_config_t i2s_rx_conf = I2S_CHANNEL_DEFAULT_CONFIG(I2S_NUM_AUTO, I2S_ROLE_MASTER); + ESP_ERROR_CHECK(i2s_new_channel(&i2s_rx_conf, NULL, &i2s_rx_chan)); + + ESP_LOGI(TAG, "Configure I2S receive channel to TDM mode"); + i2s_tdm_config_t i2s_tdm_rx_conf = { +#if EXAMPLE_I2S_FORMAT == ES7210_I2S_FMT_I2S + .slot_cfg = I2S_TDM_PHILIP_SLOT_DEFAULT_CONFIG(EXAMPLE_I2S_SAMPLE_BITS, I2S_SLOT_MODE_STEREO, EXAMPLE_I2S_TDM_SLOT_MASK), +#elif EXAMPLE_I2S_FORMAT == ES7210_I2S_FMT_LJ + .slot_cfg = I2S_TDM_MSB_SLOT_DEFAULT_CONFIG(EXAMPLE_I2S_SAMPLE_BITS, I2S_SLOT_MODE_STEREO, EXAMPLE_I2S_TDM_SLOT_MASK), +#elif EXAMPLE_I2S_FORMAT == ES7210_I2S_FMT_DSP_A + .slot_cfg = I2S_TDM_PCM_SHORT_SLOT_DEFAULT_CONFIG(EXAMPLE_I2S_SAMPLE_BITS, I2S_SLOT_MODE_STEREO, EXAMPLE_I2S_TDM_SLOT_MASK), +#elif EXAMPLE_I2S_FORMAT == ES7210_I2S_FMT_DSP_B + .slot_cfg = I2S_TDM_PCM_LONG_SLOT_DEFAULT_CONFIG(EXAMPLE_I2S_SAMPLE_BITS, I2S_SLOT_MODE_STEREO, EXAMPLE_I2S_TDM_SLOT_MASK), +#endif + .clk_cfg = { + .clk_src = I2S_CLK_SRC_DEFAULT, + .sample_rate_hz = EXAMPLE_I2S_SAMPLE_RATE, + .mclk_multiple = EXAMPLE_I2S_MCLK_MULTIPLE + }, + .gpio_cfg = { + .mclk = EXAMPLE_I2S_MCK_IO, + .bclk = EXAMPLE_I2S_BCK_IO, + .ws = EXAMPLE_I2S_WS_IO, + .dout = -1, // ES7210 only has ADC capability + .din = EXAMPLE_I2S_DI_IO + }, + }; + + ESP_ERROR_CHECK(i2s_channel_init_tdm_mode(i2s_rx_chan, &i2s_tdm_rx_conf)); + + return i2s_rx_chan; +} + +sdmmc_card_t * mount_sdcard(void) +{ + sdmmc_host_t sdmmc_host = SDSPI_HOST_DEFAULT(); + sdmmc_card_t *sdmmc_card = NULL; + + ESP_LOGI(TAG, "Initializing SPI bus for SD card"); + spi_bus_config_t bus_cfg = { + .mosi_io_num = EXAMPLE_SD_SPI_MOSI_IO, + .miso_io_num = EXAMPLE_SD_SPI_MISO_IO, + .sclk_io_num = EXAMPLE_SD_SPI_CLK_IO, + .quadwp_io_num = -1, + .quadhd_io_num = -1, + .max_transfer_sz = 4000, + }; + ESP_ERROR_CHECK(spi_bus_initialize(sdmmc_host.slot, &bus_cfg, SPI_DMA_CH_AUTO)); + + sdspi_device_config_t slot_config = SDSPI_DEVICE_CONFIG_DEFAULT(); + slot_config.gpio_cs = EXAMPLE_SD_SPI_CS_IO; + slot_config.host_id = sdmmc_host.slot; + + ESP_LOGI(TAG, "Mounting SD card"); + esp_vfs_fat_sdmmc_mount_config_t mount_config = { + .format_if_mount_failed = true, + .max_files = 2, + .allocation_unit_size = 8 * 1024 + }; + + esp_err_t ret; + while (1) { + ret = esp_vfs_fat_sdspi_mount(EXAMPLE_SD_MOUNT_POINT, &sdmmc_host, &slot_config, &mount_config, &sdmmc_card); + if (ret == ESP_OK) { + break; + } else if (ret == ESP_FAIL) { + ESP_LOGE(TAG, "Failed to mount filesystem."); + } else { + ESP_LOGE(TAG, "Failed to initialize the card (%s). " + "Make sure SD card lines have pull-up resistors in place.", esp_err_to_name(ret)); + } + vTaskDelay(pdMS_TO_TICKS(1000)); + } + + ESP_LOGI(TAG, "Card size: %lluMB, speed: %dMHz", + (((uint64_t)sdmmc_card->csd.capacity) * sdmmc_card->csd.sector_size) >> 20, + sdmmc_card->max_freq_khz / 1000); + + return sdmmc_card; +} + +static void es7210_codec_init(void) +{ + ESP_LOGI(TAG, "Init I2C used to configure ES7210"); + i2c_config_t i2c_conf = { + .sda_io_num = EXAMPLE_I2C_SDA_IO, + .scl_io_num = EXAMPLE_I2C_SCL_IO, + .mode = I2C_MODE_MASTER, + .sda_pullup_en = GPIO_PULLUP_ENABLE, + .scl_pullup_en = GPIO_PULLUP_ENABLE, + .master.clk_speed = EXAMPLE_ES7210_I2C_CLK, + }; + ESP_ERROR_CHECK(i2c_param_config(EXAMPLE_I2C_NUM, &i2c_conf)); + ESP_ERROR_CHECK(i2c_driver_install(EXAMPLE_I2C_NUM, i2c_conf.mode, 0, 0, 0)); + + /* Create ES7210 device handle */ + es7210_dev_handle_t es7210_handle = NULL; + es7210_i2c_config_t es7210_i2c_conf = { + .i2c_port = EXAMPLE_I2C_NUM, + .i2c_addr = EXAMPLE_ES7210_I2C_ADDR + }; + ESP_ERROR_CHECK(es7210_new_codec(&es7210_i2c_conf, &es7210_handle)); + + ESP_LOGI(TAG, "Configure ES7210 codec parameters"); + es7210_codec_config_t codec_conf = { + .i2s_format = EXAMPLE_I2S_TDM_FORMAT, + .mclk_ratio = EXAMPLE_I2S_MCLK_MULTIPLE, + .sample_rate_hz = EXAMPLE_I2S_SAMPLE_RATE, + .bit_width = (es7210_i2s_bits_t)EXAMPLE_I2S_SAMPLE_BITS, + .mic_bias = EXAMPLE_ES7210_MIC_BIAS, + .mic_gain = EXAMPLE_ES7210_MIC_GAIN, + .flags.tdm_enable = true + }; + ESP_ERROR_CHECK(es7210_config_codec(es7210_handle, &codec_conf)); + ESP_ERROR_CHECK(es7210_config_volume(es7210_handle, EXAMPLE_ES7210_ADC_VOLUME)); +} + +static esp_err_t record_wav(i2s_chan_handle_t i2s_rx_chan) +{ + ESP_RETURN_ON_FALSE(i2s_rx_chan, ESP_FAIL, TAG, "invalid i2s channel handle pointer"); + esp_err_t ret = ESP_OK; + + uint32_t byte_rate = EXAMPLE_I2S_SAMPLE_RATE * EXAMPLE_I2S_CHAN_NUM * EXAMPLE_I2S_SAMPLE_BITS / 8; + uint32_t wav_size = byte_rate * EXAMPLE_RECORD_TIME_SEC; + + const wav_header_t wav_header = + WAV_HEADER_PCM_DEFAULT(wav_size, EXAMPLE_I2S_SAMPLE_BITS, EXAMPLE_I2S_SAMPLE_RATE, EXAMPLE_I2S_CHAN_NUM); + + ESP_LOGI(TAG, "Opening file %s", EXAMPLE_RECORD_FILE_PATH); + FILE *f = fopen(EXAMPLE_SD_MOUNT_POINT EXAMPLE_RECORD_FILE_PATH, "w"); + ESP_RETURN_ON_FALSE(f, ESP_FAIL, TAG, "error while opening wav file"); + + /* Write wav header */ + ESP_GOTO_ON_FALSE(fwrite(&wav_header, sizeof(wav_header_t), 1, f), ESP_FAIL, err, + TAG, "error while writting wav header"); + + /* Start recording */ + size_t wav_written = 0; + static int16_t i2s_readraw_buff[4096]; + ESP_GOTO_ON_ERROR(i2s_channel_enable(i2s_rx_chan), err, TAG, "error while starting i2s rx channel"); + while (wav_written < wav_size) { + if(wav_written % byte_rate < sizeof(i2s_readraw_buff)) { + ESP_LOGI(TAG, "Recording: %"PRIu32"/%ds", wav_written/byte_rate + 1, EXAMPLE_RECORD_TIME_SEC); + } + size_t bytes_read = 0; + /* Read RAW samples from ES7210 */ + ESP_GOTO_ON_ERROR(i2s_channel_read(i2s_rx_chan, i2s_readraw_buff, sizeof(i2s_readraw_buff), &bytes_read, + pdMS_TO_TICKS(1000)), err, TAG, "error while reading samples from i2s"); + /* Write the samples to the WAV file */ + ESP_GOTO_ON_FALSE(fwrite(i2s_readraw_buff, bytes_read, 1, f), ESP_FAIL, err, + TAG, "error while writing samples to wav file"); + wav_written += bytes_read; + } + +err: + i2s_channel_disable(i2s_rx_chan); + ESP_LOGI(TAG, "Recording done! Flushing file buffer"); + fclose(f); + + return ret; +} + +void app_main(void) +{ + /* Init I2C bus to configure ES7210 and I2S bus to receive audio data from ES7210 */ + i2s_chan_handle_t i2s_rx_chan = es7210_i2s_init(); + /* Create ES7210 device handle and configure codec parameters */ + es7210_codec_init(); + /* Mount SD card, the recorded audio file will be saved into it */ + sdmmc_card_t *sdmmc_card = mount_sdcard(); + /* Start to record wav audio */ + esp_err_t err = record_wav(i2s_rx_chan); + /* Unmount SD card */ + esp_vfs_fat_sdcard_unmount(EXAMPLE_SD_MOUNT_POINT, sdmmc_card); + if(err == ESP_OK) { + ESP_LOGI(TAG, "Audio was successfully recorded into "EXAMPLE_RECORD_FILE_PATH + ". You can now remove the SD card safely"); + } else { + ESP_LOGE(TAG, "Record failed, "EXAMPLE_RECORD_FILE_PATH" on SD card may not be playable."); + } +} diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/pytest_i2s_es7210_tdm.py b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/pytest_i2s_es7210_tdm.py new file mode 100644 index 0000000000..c6ca369f64 --- /dev/null +++ b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/pytest_i2s_es7210_tdm.py @@ -0,0 +1,14 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Unlicense OR CC0-1.0 +import pytest +from pytest_embedded import Dut + + +@pytest.mark.esp32s3 +@pytest.mark.esp32c3 +@pytest.mark.generic +def test_i2s_es7210_tdm_example(dut: Dut) -> None: + dut.expect_exact('example: Create I2S receive channel') + dut.expect_exact('example: Configure I2S receive channel to TDM mode') + dut.expect_exact('example: Init I2C used to configure ES7210') + dut.expect_exact('example: Configure ES7210 codec parameters') diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md b/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md index f10fbe7154..9caaf6a1ec 100644 --- a/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md +++ b/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md @@ -65,7 +65,7 @@ The component can be installed by esp component manager. Since this example alre idf.py add-dependency espressif/es8311==0.0.2-alpha ``` -If the dependency is added, you can check `idf_component.yml` for more detail. When building this example or other project with managed component in it, the component manager will search the component online and download it under the `managed_componets` folder. +If the dependency is added, you can check `idf_component.yml` for more detail. When building this example or other projects with managed components, the component manager will search for the required components online and download them into the `managed_componets` folder. ### Configure the Project diff --git a/examples/peripherals/i2s/i2s_recorder/main/CMakeLists.txt b/examples/peripherals/i2s/i2s_recorder/main/CMakeLists.txt index 5ffc0c8df5..44a620a03e 100644 --- a/examples/peripherals/i2s/i2s_recorder/main/CMakeLists.txt +++ b/examples/peripherals/i2s/i2s_recorder/main/CMakeLists.txt @@ -1,2 +1,2 @@ idf_component_register(SRCS "i2s_recorder_main.c" - INCLUDE_DIRS ".") + INCLUDE_DIRS "../../common") diff --git a/examples/peripherals/i2s/i2s_recorder/main/i2s_recorder_main.c b/examples/peripherals/i2s/i2s_recorder/main/i2s_recorder_main.c index dbb17482f5..cf881e10b0 100644 --- a/examples/peripherals/i2s/i2s_recorder/main/i2s_recorder_main.c +++ b/examples/peripherals/i2s/i2s_recorder/main/i2s_recorder_main.c @@ -10,6 +10,7 @@ #include #include #include +#include "sdkconfig.h" #include "esp_log.h" #include "esp_err.h" #include "esp_system.h" @@ -20,7 +21,7 @@ #include "driver/gpio.h" #include "driver/spi_common.h" #include "sdmmc_cmd.h" -#include "sdkconfig.h" +#include "format_wav.h" static const char *TAG = "pdm_rec_example"; @@ -90,40 +91,15 @@ void mount_sdcard(void) sdmmc_card_print_info(stdout, card); } -void generate_wav_header(char *wav_header, uint32_t wav_size, uint32_t sample_rate) -{ - // See this for reference: http://soundfile.sapp.org/doc/WaveFormat/ - uint32_t file_size = wav_size + WAVE_HEADER_SIZE - 8; - uint32_t byte_rate = BYTE_RATE; - - const char set_wav_header[] = { - 'R', 'I', 'F', 'F', // ChunkID - file_size, file_size >> 8, file_size >> 16, file_size >> 24, // ChunkSize - 'W', 'A', 'V', 'E', // Format - 'f', 'm', 't', ' ', // Subchunk1ID - 0x10, 0x00, 0x00, 0x00, // Subchunk1Size (16 for PCM) - 0x01, 0x00, // AudioFormat (1 for PCM) - 0x01, 0x00, // NumChannels (1 channel) - sample_rate, sample_rate >> 8, sample_rate >> 16, sample_rate >> 24, // SampleRate - byte_rate, byte_rate >> 8, byte_rate >> 16, byte_rate >> 24, // ByteRate - 0x02, 0x00, // BlockAlign - 0x10, 0x00, // BitsPerSample (16 bits) - 'd', 'a', 't', 'a', // Subchunk2ID - wav_size, wav_size >> 8, wav_size >> 16, wav_size >> 24, // Subchunk2Size - }; - - memcpy(wav_header, set_wav_header, sizeof(set_wav_header)); -} - void record_wav(uint32_t rec_time) { // Use POSIX and C standard library functions to work with files. int flash_wr_size = 0; ESP_LOGI(TAG, "Opening file"); - char wav_header_fmt[WAVE_HEADER_SIZE]; uint32_t flash_rec_time = BYTE_RATE * rec_time; - generate_wav_header(wav_header_fmt, flash_rec_time, CONFIG_EXAMPLE_SAMPLE_RATE); + const wav_header_t wav_header = + WAV_HEADER_PCM_DEFAULT(flash_rec_time, 16, CONFIG_EXAMPLE_SAMPLE_RATE, 1); // First check if file exists before creating a new file. struct stat st; @@ -140,7 +116,7 @@ void record_wav(uint32_t rec_time) } // Write the header to the WAV file - fwrite(wav_header_fmt, 1, WAVE_HEADER_SIZE, f); + fwrite(&wav_header, sizeof(wav_header), 1, f); // Start recording while (flash_wr_size < flash_rec_time) { @@ -148,7 +124,7 @@ void record_wav(uint32_t rec_time) if (i2s_channel_read(rx_handle, (char *)i2s_readraw_buff, SAMPLE_SIZE, &bytes_read, 1000) == ESP_OK) { printf("[0] %d [1] %d [2] %d [3]%d ...\n", i2s_readraw_buff[0], i2s_readraw_buff[1], i2s_readraw_buff[2], i2s_readraw_buff[3]); // Write the samples to the WAV file - fwrite(i2s_readraw_buff, 1, bytes_read, f); + fwrite(i2s_readraw_buff, bytes_read, 1, f); flash_wr_size += bytes_read; } else { printf("Read Failed!\n"); diff --git a/examples/peripherals/lcd/i2c_oled/main/i2c_oled_example_main.c b/examples/peripherals/lcd/i2c_oled/main/i2c_oled_example_main.c index 638652e51c..f21f5654c6 100644 --- a/examples/peripherals/lcd/i2c_oled/main/i2c_oled_example_main.c +++ b/examples/peripherals/lcd/i2c_oled/main/i2c_oled_example_main.c @@ -117,7 +117,6 @@ void app_main(void) esp_lcd_panel_handle_t panel_handle = NULL; esp_lcd_panel_dev_config_t panel_config = { .bits_per_pixel = 1, - .color_space = ESP_LCD_COLOR_SPACE_MONOCHROME, .reset_gpio_num = EXAMPLE_PIN_NUM_RST, }; ESP_ERROR_CHECK(esp_lcd_new_panel_ssd1306(io_handle, &panel_config, &panel_handle)); diff --git a/examples/peripherals/lcd/i2c_oled/main/lvgl_demo_ui.c b/examples/peripherals/lcd/i2c_oled/main/lvgl_demo_ui.c index 28d9801515..fe165fde7d 100644 --- a/examples/peripherals/lcd/i2c_oled/main/lvgl_demo_ui.c +++ b/examples/peripherals/lcd/i2c_oled/main/lvgl_demo_ui.c @@ -12,6 +12,6 @@ void example_lvgl_demo_ui(lv_disp_t *disp) lv_obj_t *label = lv_label_create(scr); lv_label_set_long_mode(label, LV_LABEL_LONG_SCROLL_CIRCULAR); /* Circular scroll */ lv_label_set_text(label, "Hello Espressif, Hello LVGL."); - lv_obj_set_width(label, 150); + lv_obj_set_width(label, 128); lv_obj_align(label, LV_ALIGN_TOP_MID, 0, 0); } diff --git a/examples/peripherals/lcd/i80_controller/main/i80_controller_example_main.c b/examples/peripherals/lcd/i80_controller/main/i80_controller_example_main.c index d71f186e36..8c2090f4a9 100644 --- a/examples/peripherals/lcd/i80_controller/main/i80_controller_example_main.c +++ b/examples/peripherals/lcd/i80_controller/main/i80_controller_example_main.c @@ -211,7 +211,7 @@ void app_main(void) ESP_LOGI(TAG, "Install LCD driver of st7789"); esp_lcd_panel_dev_config_t panel_config = { .reset_gpio_num = EXAMPLE_PIN_NUM_RST, - .color_space = ESP_LCD_COLOR_SPACE_RGB, + .rgb_endian = LCD_RGB_ENDIAN_RGB, .bits_per_pixel = 16, }; ESP_ERROR_CHECK(esp_lcd_new_panel_st7789(io_handle, &panel_config, &panel_handle)); @@ -226,7 +226,7 @@ void app_main(void) ESP_LOGI(TAG, "Install LCD driver of nt35510"); esp_lcd_panel_dev_config_t panel_config = { .reset_gpio_num = EXAMPLE_PIN_NUM_RST, - .color_space = ESP_LCD_COLOR_SPACE_BGR, + .rgb_endian = LCD_RGB_ENDIAN_BGR, .bits_per_pixel = 16, }; ESP_ERROR_CHECK(esp_lcd_new_panel_nt35510(io_handle, &panel_config, &panel_handle)); @@ -244,7 +244,7 @@ void app_main(void) ESP_LOGI(TAG, "Install LCD driver of ili9341 (st7789 compatible)"); esp_lcd_panel_dev_config_t panel_config = { .reset_gpio_num = EXAMPLE_PIN_NUM_RST, - .color_space = ESP_LCD_COLOR_SPACE_BGR, + .rgb_endian = LCD_RGB_ENDIAN_BGR, .bits_per_pixel = 16, }; ESP_ERROR_CHECK(esp_lcd_new_panel_st7789(io_handle, &panel_config, &panel_handle)); diff --git a/examples/peripherals/lcd/rgb_panel/main/CMakeLists.txt b/examples/peripherals/lcd/rgb_panel/main/CMakeLists.txt index 30da0c0318..4e9a3d43e5 100644 --- a/examples/peripherals/lcd/rgb_panel/main/CMakeLists.txt +++ b/examples/peripherals/lcd/rgb_panel/main/CMakeLists.txt @@ -1,4 +1,2 @@ idf_component_register(SRCS "rgb_lcd_example_main.c" "lvgl_demo_ui.c" INCLUDE_DIRS ".") - -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/lcd/spi_lcd_touch/main/spi_lcd_touch_example_main.c b/examples/peripherals/lcd/spi_lcd_touch/main/spi_lcd_touch_example_main.c index 4b3e51939d..3808948879 100644 --- a/examples/peripherals/lcd/spi_lcd_touch/main/spi_lcd_touch_example_main.c +++ b/examples/peripherals/lcd/spi_lcd_touch/main/spi_lcd_touch_example_main.c @@ -208,9 +208,9 @@ void app_main(void) esp_lcd_panel_dev_config_t panel_config = { .reset_gpio_num = EXAMPLE_PIN_NUM_LCD_RST, #if CONFIG_EXAMPLE_LCD_CONTROLLER_ILI9341 - .color_space = ESP_LCD_COLOR_SPACE_RGB, + .rgb_endian = LCD_RGB_ENDIAN_RGB, #elif CONFIG_EXAMPLE_LCD_CONTROLLER_GC9A01 - .color_space = ESP_LCD_COLOR_SPACE_BGR, + .rgb_endian = LCD_RGB_ENDIAN_BGR, #endif .bits_per_pixel = 16, }; diff --git a/examples/peripherals/lcd/tjpgd/main/decode_image.c b/examples/peripherals/lcd/tjpgd/main/decode_image.c index f7182a32cb..3a02a04862 100644 --- a/examples/peripherals/lcd/tjpgd/main/decode_image.c +++ b/examples/peripherals/lcd/tjpgd/main/decode_image.c @@ -15,132 +15,54 @@ format if you want to use a different image file. */ #include "decode_image.h" -#include "esp_rom_tjpgd.h" +#include "jpeg_decoder.h" #include "esp_log.h" +#include "esp_check.h" #include +#include "freertos/FreeRTOS.h" //Reference the binary-included jpeg file extern const uint8_t image_jpg_start[] asm("_binary_image_jpg_start"); extern const uint8_t image_jpg_end[] asm("_binary_image_jpg_end"); //Define the height and width of the jpeg file. Make sure this matches the actual jpeg //dimensions. -#define IMAGE_W 336 -#define IMAGE_H 256 const char *TAG = "ImageDec"; -//Data that is passed from the decoder function to the infunc/outfunc functions. -typedef struct { - const unsigned char *inData; //Pointer to jpeg data - uint16_t inPos; //Current position in jpeg data - uint16_t **outData; //Array of IMAGE_H pointers to arrays of IMAGE_W 16-bit pixel values - int outW; //Width of the resulting file - int outH; //Height of the resulting file -} JpegDev; - -//Input function for jpeg decoder. Just returns bytes from the inData field of the JpegDev structure. -static uint32_t infunc(esp_rom_tjpgd_dec_t *decoder, uint8_t *buf, uint32_t len) -{ - //Read bytes from input file - JpegDev *jd = (JpegDev *)decoder->device; - if (buf != NULL) { - memcpy(buf, jd->inData + jd->inPos, len); - } - jd->inPos += len; - return len; -} - -//Output function. Re-encodes the RGB888 data from the decoder as big-endian RGB565 and -//stores it in the outData array of the JpegDev structure. -static uint32_t outfunc(esp_rom_tjpgd_dec_t *decoder, void *bitmap, esp_rom_tjpgd_rect_t *rect) -{ - JpegDev *jd = (JpegDev *)decoder->device; - uint8_t *in = (uint8_t *)bitmap; - for (int y = rect->top; y <= rect->bottom; y++) { - for (int x = rect->left; x <= rect->right; x++) { - //We need to convert the 3 bytes in `in` to a rgb565 value. - uint16_t v = 0; - v |= ((in[0] >> 3) << 11); - v |= ((in[1] >> 2) << 5); - v |= ((in[2] >> 3) << 0); - //The LCD wants the 16-bit value in big-endian, so swap bytes - v = (v >> 8) | (v << 8); - jd->outData[y][x] = v; - in += 3; - } - } - return 1; -} - -//Size of the work space for the jpeg decoder. -#define WORKSZ 3100 - //Decode the embedded image into pixel lines that can be used with the rest of the logic. -esp_err_t decode_image(uint16_t ***pixels) +esp_err_t decode_image(uint16_t **pixels) { - char *work = NULL; - int r; - esp_rom_tjpgd_dec_t decoder; - JpegDev jd; *pixels = NULL; esp_err_t ret = ESP_OK; //Alocate pixel memory. Each line is an array of IMAGE_W 16-bit pixels; the `*pixels` array itself contains pointers to these lines. - *pixels = calloc(IMAGE_H, sizeof(uint16_t *)); - if (*pixels == NULL) { - ESP_LOGE(TAG, "Error allocating memory for lines"); - ret = ESP_ERR_NO_MEM; - goto err; - } - for (int i = 0; i < IMAGE_H; i++) { - (*pixels)[i] = malloc(IMAGE_W * sizeof(uint16_t)); - if ((*pixels)[i] == NULL) { - ESP_LOGE(TAG, "Error allocating memory for line %d", i); - ret = ESP_ERR_NO_MEM; - goto err; + *pixels = calloc(IMAGE_H * IMAGE_W, sizeof(uint16_t)); + ESP_GOTO_ON_FALSE((*pixels), ESP_ERR_NO_MEM, err, TAG, "Error allocating memory for lines"); + + //JPEG decode config + esp_jpeg_image_cfg_t jpeg_cfg = { + .indata = (uint8_t *)image_jpg_start, + .indata_size = image_jpg_end - image_jpg_start, + .outbuf = (uint8_t*)(*pixels), + .outbuf_size = IMAGE_W * IMAGE_H * sizeof(uint16_t), + .out_format = JPEG_IMAGE_FORMAT_RGB565, + .out_scale = JPEG_IMAGE_SCALE_0, + .flags = { + .swap_color_bytes = 1, } - } + }; - //Allocate the work space for the jpeg decoder. - work = calloc(WORKSZ, 1); - if (work == NULL) { - ESP_LOGE(TAG, "Cannot allocate workspace"); - ret = ESP_ERR_NO_MEM; - goto err; - } + //JPEG decode + esp_jpeg_image_output_t outimg; + esp_jpeg_decode(&jpeg_cfg, &outimg); - //Populate fields of the JpegDev struct. - jd.inData = image_jpg_start; - jd.inPos = 0; - jd.outData = *pixels; - jd.outW = IMAGE_W; - jd.outH = IMAGE_H; + ESP_LOGI(TAG, "JPEG image decoded! Size of the decoded image is: %dpx x %dpx", outimg.width, outimg.height); - //Prepare and decode the jpeg. - r = esp_rom_tjpgd_prepare(&decoder, infunc, work, WORKSZ, (void *)&jd); - if (r != JDR_OK) { - ESP_LOGE(TAG, "Image decoder: jd_prepare failed (%d)", r); - ret = ESP_ERR_NOT_SUPPORTED; - goto err; - } - r = esp_rom_tjpgd_decomp(&decoder, outfunc, 0); - if (r != JDR_OK && r != JDR_FMT1) { - ESP_LOGE(TAG, "Image decoder: jd_decode failed (%d)", r); - ret = ESP_ERR_NOT_SUPPORTED; - goto err; - } - - //All done! Free the work area (as we don't need it anymore) and return victoriously. - free(work); return ret; err: //Something went wrong! Exit cleanly, de-allocating everything we allocated. if (*pixels != NULL) { - for (int i = 0; i < IMAGE_H; i++) { - free((*pixels)[i]); - } free(*pixels); } - free(work); return ret; } diff --git a/examples/peripherals/lcd/tjpgd/main/decode_image.h b/examples/peripherals/lcd/tjpgd/main/decode_image.h index 8fa1155005..44800b17ba 100644 --- a/examples/peripherals/lcd/tjpgd/main/decode_image.h +++ b/examples/peripherals/lcd/tjpgd/main/decode_image.h @@ -8,6 +8,9 @@ #include #include "esp_err.h" +#define IMAGE_W 320 +#define IMAGE_H 240 + /** * @brief Decode the jpeg ``image.jpg`` embedded into the program file into pixel data. * @@ -17,4 +20,4 @@ * - ESP_ERR_NO_MEM if out of memory * - ESP_OK on succesful decode */ -esp_err_t decode_image(uint16_t ***pixels); +esp_err_t decode_image(uint16_t **pixels); diff --git a/examples/peripherals/lcd/tjpgd/main/idf_component.yml b/examples/peripherals/lcd/tjpgd/main/idf_component.yml new file mode 100644 index 0000000000..a2167bf4c2 --- /dev/null +++ b/examples/peripherals/lcd/tjpgd/main/idf_component.yml @@ -0,0 +1,3 @@ +dependencies: + idf: ">=4.4" + esp_jpeg: ">=1.0.2" diff --git a/examples/peripherals/lcd/tjpgd/main/image.jpg b/examples/peripherals/lcd/tjpgd/main/image.jpg index 803ca2cdca..cacad09050 100644 Binary files a/examples/peripherals/lcd/tjpgd/main/image.jpg and b/examples/peripherals/lcd/tjpgd/main/image.jpg differ diff --git a/examples/peripherals/lcd/tjpgd/main/lcd_tjpgd_example_main.c b/examples/peripherals/lcd/tjpgd/main/lcd_tjpgd_example_main.c index 9fb00d9a66..6a27dce742 100644 --- a/examples/peripherals/lcd/tjpgd/main/lcd_tjpgd_example_main.c +++ b/examples/peripherals/lcd/tjpgd/main/lcd_tjpgd_example_main.c @@ -28,7 +28,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// //////////////////// Please update the following configuration according to your LCD spec ////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -#define EXAMPLE_LCD_PIXEL_CLOCK_HZ (10 * 1000 * 1000) +#define EXAMPLE_LCD_PIXEL_CLOCK_HZ (20 * 1000 * 1000) #define EXAMPLE_LCD_BK_LIGHT_ON_LEVEL 0 #define EXAMPLE_LCD_BK_LIGHT_OFF_LEVEL !EXAMPLE_LCD_BK_LIGHT_ON_LEVEL #define EXAMPLE_PIN_NUM_DATA0 23 /*!< for 1-line SPI, this also refered as MOSI */ @@ -130,7 +130,7 @@ void app_main(void) esp_lcd_panel_handle_t panel_handle = NULL; esp_lcd_panel_dev_config_t panel_config = { .reset_gpio_num = EXAMPLE_PIN_NUM_RST, - .color_space = ESP_LCD_COLOR_SPACE_BGR, + .rgb_endian = LCD_RGB_ENDIAN_BGR, .bits_per_pixel = 16, }; // Initialize the LCD configuration diff --git a/examples/peripherals/lcd/tjpgd/main/pretty_effect.c b/examples/peripherals/lcd/tjpgd/main/pretty_effect.c index 3aa8ac03c9..b7e557f990 100644 --- a/examples/peripherals/lcd/tjpgd/main/pretty_effect.c +++ b/examples/peripherals/lcd/tjpgd/main/pretty_effect.c @@ -9,15 +9,13 @@ #include "sdkconfig.h" #include "decode_image.h" -uint16_t **pixels; +uint16_t *pixels; //Grab a rgb16 pixel from the esp32_tiles image static inline uint16_t get_bgnd_pixel(int x, int y) { - //Image has an 8x8 pixel margin, so we can also resolve e.g. [-3, 243] - x+=8; - y+=8; - return pixels[y][x]; + //Get color of the pixel on x,y coords + return (uint16_t) *(pixels + (y * IMAGE_W) + x); } //This variable is used to detect the next frame. diff --git a/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/README.md b/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/README.md index 09ab448a55..6693150462 100644 --- a/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/README.md +++ b/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/README.md @@ -4,11 +4,11 @@ (See the README.md file in the upper level 'examples' directory for more information about examples.) -This example mainly illustrates how to drive a brushed DC motor by generating two specific PWM signals. However the PWM signals from ESP chip can't drive motors directly as the motor usually consumes high current. So an H-bridge like [DRV8848](https://www.ti.com/product/DRV8848) should be used to provide the needed voltage and current for brushed DC motor. To simplify the DC motor control of MCPWM peripheral driver, there's a component called [bdc_motor](components/bdc_motor/README.md) which abstracts the common operations into a generic interface. The most useful operations are: `forward`, `reverse`, `coast` and `brake`. +This example mainly illustrates how to drive a brushed DC motor by generating two specific PWM signals. However the PWM signals from ESP chip can't drive motors directly as the motor usually consumes high current. So an H-bridge like [DRV8848](https://www.ti.com/product/DRV8848) should be used to provide the needed voltage and current for brushed DC motor. To simplify the DC motor control of MCPWM peripheral driver, there's a component called [bdc_motor](https://components.espressif.com/component/espressif/bdc_motor) which abstracts the common operations into a generic interface. The most useful operations are: `forward`, `reverse`, `coast` and `brake`. To measure the speed of motor, a photoelectric encoder is used to generate the "speed feedback" signals (e.g. a pair of quadrature signal). In the example, we use the PCNT peripheral to decode that quadrature signals. For more information, please refer to [rotary encoder example](../../pcnt/rotary_encoder/README.md) as well. -The example uses a simple PID algorithm to keep the motor spin in a stable speed. The PID component is fetched from the [IDF Component Registry](https://components.espressif.com/component/espressif/pid_ctrl). +The example uses a simple PID algorithm to keep the motor spin in a stable speed. Like the [bdc_motor](https://components.espressif.com/component/espressif/bdc_motor), the [PID component](https://components.espressif.com/component/espressif/pid_ctrl) is also managed by the component manager. These components' dependencies are listed in the [manifest file](main/idf_component.yml). ## How to Use Example diff --git a/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/components/bdc_motor/CMakeLists.txt b/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/components/bdc_motor/CMakeLists.txt deleted file mode 100644 index e8f680b259..0000000000 --- a/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/components/bdc_motor/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -set(srcs "src/bdc_motor.c") - -if(CONFIG_SOC_MCPWM_SUPPORTED) - list(APPEND srcs "src/bdc_motor_mcpwm_impl.c") -endif() - -idf_component_register(SRCS ${srcs} - INCLUDE_DIRS "include" "interface" - PRIV_REQUIRES "driver") diff --git a/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/components/bdc_motor/README.md b/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/components/bdc_motor/README.md deleted file mode 100644 index 8918067552..0000000000 --- a/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/components/bdc_motor/README.md +++ /dev/null @@ -1,7 +0,0 @@ -# Brushed DC Motor Component - -This directory contains an implementation for Brushed DC Motor by different peripherals. Currently only MCPWM is supported as the BDC motor backend. - -To learn more about how to use this component, please check API Documentation from header file [bdc_motor.h](./include/bdc_motor.h). - -Please note that this component is not considered to be a part of ESP-IDF stable API. It may change and it may be removed in the future releases. diff --git a/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/components/bdc_motor/include/bdc_motor.h b/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/components/bdc_motor/include/bdc_motor.h deleted file mode 100644 index 1b102d91f6..0000000000 --- a/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/components/bdc_motor/include/bdc_motor.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "esp_err.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Brushed DC Motor handle - */ -typedef struct bdc_motor_t *bdc_motor_handle_t; - -/** - * @brief Enable BDC motor - * - * @param motor: BDC Motor handle - * - * @return - * - ESP_OK: Enable motor successfully - * - ESP_ERR_INVALID_ARG: Enable motor failed because of invalid parameters - * - ESP_FAIL: Enable motor failed because other error occurred - */ -esp_err_t bdc_motor_enable(bdc_motor_handle_t motor); - -/** - * @brief Disable BDC motor - * - * @param motor: BDC Motor handle - * - * @return - * - ESP_OK: Disable motor successfully - * - ESP_ERR_INVALID_ARG: Disable motor failed because of invalid parameters - * - ESP_FAIL: Disable motor failed because other error occurred - */ -esp_err_t bdc_motor_disable(bdc_motor_handle_t motor); - -/** - * @brief Set speed for bdc motor - * - * @param motor: BDC Motor handle - * @param speed: BDC speed - * - * @return - * - ESP_OK: Set motor speed successfully - * - ESP_ERR_INVALID_ARG: Set motor speed failed because of invalid parameters - * - ESP_FAIL: Set motor speed failed because other error occurred - */ -esp_err_t bdc_motor_set_speed(bdc_motor_handle_t motor, uint32_t speed); - -/** - * @brief Forward BDC motor - * - * @param motor: BDC Motor handle - * - * @return - * - ESP_OK: Forward motor successfully - * - ESP_FAIL: Forward motor failed because some other error occurred - */ -esp_err_t bdc_motor_forward(bdc_motor_handle_t motor); - -/** - * @brief Reverse BDC Motor - * - * @param strip: BDC Motor handle - * - * @return - * - ESP_OK: Reverse motor successfully - * - ESP_FAIL: Reverse motor failed because some other error occurred - */ -esp_err_t bdc_motor_reverse(bdc_motor_handle_t motor); - -/** - * @brief Stop motor in a coast way (a.k.a Fast Decay) - * - * @param motor: BDC Motor handle - * - * @return - * - ESP_OK: Stop motor successfully - * - ESP_FAIL: Stop motor failed because some other error occurred - */ -esp_err_t bdc_motor_coast(bdc_motor_handle_t motor); - -/** - * @brief Stop motor in a brake way (a.k.a Slow Decay) - * - * @param motor: BDC Motor handle - * - * @return - * - ESP_OK: Stop motor successfully - * - ESP_FAIL: Stop motor failed because some other error occurred - */ -esp_err_t bdc_motor_brake(bdc_motor_handle_t motor); - -/** - * @brief Free BDC Motor resources - * - * @param strip: BDC Motor handle - * - * @return - * - ESP_OK: Free resources successfully - * - ESP_FAIL: Free resources failed because error occurred - */ -esp_err_t bdc_motor_del(bdc_motor_handle_t motor); - -/** - * @brief BDC Motor Configuration - */ -typedef struct { - uint32_t pwma_gpio_num; /*!< BDC Motor PWM A gpio number */ - uint32_t pwmb_gpio_num; /*!< BDC Motor PWM B gpio number */ - uint32_t pwm_freq_hz; /*!< PWM frequency, in Hz */ -} bdc_motor_config_t; - -/** - * @brief BDC Motor MCPWM specific configuration - */ -typedef struct { - int group_id; /*!< MCPWM group number */ - uint32_t resolution_hz; /*!< MCPWM timer resolution */ -} bdc_motor_mcpwm_config_t; - -/** - * @brief Create BDC Motor based on MCPWM peripheral - * - * @param motor_config: BDC Motor configuration - * @param mcpwm_config: MCPWM specific configuration - * @param ret_motor Returned BDC Motor handle - * @return - * - ESP_OK: Create BDC Motor handle successfully - * - ESP_ERR_INVALID_ARG: Create BDC Motor handle failed because of invalid argument - * - ESP_ERR_NO_MEM: Create BDC Motor handle failed because of out of memory - * - ESP_FAIL: Create BDC Motor handle failed because some other error - */ -esp_err_t bdc_motor_new_mcpwm_device(const bdc_motor_config_t *motor_config, const bdc_motor_mcpwm_config_t *mcpwm_config, bdc_motor_handle_t *ret_motor); - -#ifdef __cplusplus -} -#endif diff --git a/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/components/bdc_motor/interface/bdc_motor_interface.h b/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/components/bdc_motor/interface/bdc_motor_interface.h deleted file mode 100644 index 35e9697ac2..0000000000 --- a/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/components/bdc_motor/interface/bdc_motor_interface.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "esp_err.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct bdc_motor_t bdc_motor_t; /*!< Type of BDC motor */ - -/** - * @brief BDC motor interface definition - */ -struct bdc_motor_t { - /** - * @brief Enable BDC motor - * - * @param motor: BDC Motor handle - * - * @return - * - ESP_OK: Enable motor successfully - * - ESP_ERR_INVALID_ARG: Enable motor failed because of invalid parameters - * - ESP_FAIL: Enable motor failed because other error occurred - */ - esp_err_t (*enable)(bdc_motor_t *motor); - - /** - * @brief Disable BDC motor - * - * @param motor: BDC Motor handle - * - * @return - * - ESP_OK: Disable motor successfully - * - ESP_ERR_INVALID_ARG: Disable motor failed because of invalid parameters - * - ESP_FAIL: Disable motor failed because other error occurred - */ - esp_err_t (*disable)(bdc_motor_t *motor); - - /** - * @brief Set speed for bdc motor - * - * @param motor: BDC Motor handle - * @param speed: BDC speed - * - * @return - * - ESP_OK: Set motor speed successfully - * - ESP_ERR_INVALID_ARG: Set motor speed failed because of invalid parameters - * - ESP_FAIL: Set motor speed failed because other error occurred - */ - esp_err_t (*set_speed)(bdc_motor_t *motor, uint32_t speed); - - /** - * @brief Forward BDC motor - * - * @param motor: BDC Motor handle - * - * @return - * - ESP_OK: Forward motor successfully - * - ESP_FAIL: Forward motor failed because some other error occurred - */ - esp_err_t (*forward)(bdc_motor_t *motor); - - /** - * @brief Reverse BDC Motor - * - * @param motor: BDC Motor handle - * - * @return - * - ESP_OK: Reverse motor successfully - * - ESP_FAIL: Reverse motor failed because some other error occurred - */ - esp_err_t (*reverse)(bdc_motor_t *motor); - - /** - * @brief Stop motor in a coast way (a.k.a Fast Decay) - * - * @param motor: BDC Motor handle - * - * @return - * - ESP_OK: Stop motor successfully - * - ESP_FAIL: Stop motor failed because some other error occurred - */ - esp_err_t (*coast)(bdc_motor_t *motor); - - /** - * @brief Stop motor in a brake way (a.k.a Slow Decay) - * - * @param motor: BDC Motor handle - * - * @return - * - ESP_OK: Stop motor successfully - * - ESP_FAIL: Stop motor failed because some other error occurred - */ - esp_err_t (*brake)(bdc_motor_t *motor); - - /** - * @brief Free BDC Motor handle resources - * - * @param motor: BDC Motor handle - * - * @return - * - ESP_OK: Free resources successfully - * - ESP_FAIL: Free resources failed because error occurred - */ - esp_err_t (*del)(bdc_motor_t *motor); -}; - -#ifdef __cplusplus -} -#endif diff --git a/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/components/bdc_motor/src/bdc_motor.c b/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/components/bdc_motor/src/bdc_motor.c deleted file mode 100644 index fbbc440312..0000000000 --- a/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/components/bdc_motor/src/bdc_motor.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include -#include -#include -#include "esp_log.h" -#include "esp_check.h" -#include "bdc_motor.h" -#include "bdc_motor_interface.h" - -static const char *TAG = "bdc_motor"; - -esp_err_t bdc_motor_enable(bdc_motor_handle_t motor) -{ - ESP_RETURN_ON_FALSE(motor, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - return motor->enable(motor); -} - -esp_err_t bdc_motor_disable(bdc_motor_handle_t motor) -{ - ESP_RETURN_ON_FALSE(motor, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - return motor->disable(motor); -} - -esp_err_t bdc_motor_set_speed(bdc_motor_handle_t motor, uint32_t speed) -{ - ESP_RETURN_ON_FALSE(motor, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - return motor->set_speed(motor, speed); -} - -esp_err_t bdc_motor_forward(bdc_motor_handle_t motor) -{ - ESP_RETURN_ON_FALSE(motor, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - return motor->forward(motor); -} - -esp_err_t bdc_motor_reverse(bdc_motor_handle_t motor) -{ - ESP_RETURN_ON_FALSE(motor, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - return motor->reverse(motor); -} - -esp_err_t bdc_motor_coast(bdc_motor_handle_t motor) -{ - ESP_RETURN_ON_FALSE(motor, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - return motor->coast(motor); -} - -esp_err_t bdc_motor_brake(bdc_motor_handle_t motor) -{ - ESP_RETURN_ON_FALSE(motor, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - return motor->brake(motor); -} - -esp_err_t bdc_motor_del(bdc_motor_handle_t motor) -{ - ESP_RETURN_ON_FALSE(motor, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); - return motor->del(motor); -} diff --git a/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/components/bdc_motor/src/bdc_motor_mcpwm_impl.c b/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/components/bdc_motor/src/bdc_motor_mcpwm_impl.c deleted file mode 100644 index 2b502a6a44..0000000000 --- a/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/components/bdc_motor/src/bdc_motor_mcpwm_impl.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include -#include -#include -#include "esp_log.h" -#include "esp_check.h" -#include "driver/mcpwm_prelude.h" -#include "bdc_motor.h" -#include "bdc_motor_interface.h" - -static const char *TAG = "bdc_motor_mcpwm"; - -typedef struct { - bdc_motor_t base; - mcpwm_timer_handle_t timer; - mcpwm_oper_handle_t operator; - mcpwm_cmpr_handle_t cmpa; - mcpwm_cmpr_handle_t cmpb; - mcpwm_gen_handle_t gena; - mcpwm_gen_handle_t genb; -} bdc_motor_mcpwm_obj; - -static esp_err_t bdc_motor_mcpwm_set_speed(bdc_motor_t *motor, uint32_t speed) -{ - bdc_motor_mcpwm_obj *mcpwm_motor = __containerof(motor, bdc_motor_mcpwm_obj, base); - ESP_RETURN_ON_ERROR(mcpwm_comparator_set_compare_value(mcpwm_motor->cmpa, speed), TAG, "set compare value failed"); - ESP_RETURN_ON_ERROR(mcpwm_comparator_set_compare_value(mcpwm_motor->cmpb, speed), TAG, "set compare value failed"); - return ESP_OK; -} - -static esp_err_t bdc_motor_mcpwm_enable(bdc_motor_t *motor) -{ - bdc_motor_mcpwm_obj *mcpwm_motor = __containerof(motor, bdc_motor_mcpwm_obj, base); - ESP_RETURN_ON_ERROR(mcpwm_timer_enable(mcpwm_motor->timer), TAG, "enable timer failed"); - ESP_RETURN_ON_ERROR(mcpwm_timer_start_stop(mcpwm_motor->timer, MCPWM_TIMER_START_NO_STOP), TAG, "start timer failed"); - return ESP_OK; -} - -static esp_err_t bdc_motor_mcpwm_disable(bdc_motor_t *motor) -{ - bdc_motor_mcpwm_obj *mcpwm_motor = __containerof(motor, bdc_motor_mcpwm_obj, base); - ESP_RETURN_ON_ERROR(mcpwm_timer_start_stop(mcpwm_motor->timer, MCPWM_TIMER_STOP_EMPTY), TAG, "stop timer failed"); - ESP_RETURN_ON_ERROR(mcpwm_timer_disable(mcpwm_motor->timer), TAG, "disable timer failed"); - return ESP_OK; -} - -static esp_err_t bdc_motor_mcpwm_forward(bdc_motor_t *motor) -{ - bdc_motor_mcpwm_obj *mcpwm_motor = __containerof(motor, bdc_motor_mcpwm_obj, base); - ESP_RETURN_ON_ERROR(mcpwm_generator_set_force_level(mcpwm_motor->gena, -1, true), TAG, "disable force level for gena failed"); - ESP_RETURN_ON_ERROR(mcpwm_generator_set_force_level(mcpwm_motor->genb, 0, true), TAG, "set force level for genb failed"); - return ESP_OK; -} - -static esp_err_t bdc_motor_mcpwm_reverse(bdc_motor_t *motor) -{ - bdc_motor_mcpwm_obj *mcpwm_motor = __containerof(motor, bdc_motor_mcpwm_obj, base); - ESP_RETURN_ON_ERROR(mcpwm_generator_set_force_level(mcpwm_motor->genb, -1, true), TAG, "disable force level for genb failed"); - ESP_RETURN_ON_ERROR(mcpwm_generator_set_force_level(mcpwm_motor->gena, 0, true), TAG, "set force level for gena failed"); - return ESP_OK; -} - -static esp_err_t bdc_motor_mcpwm_coast(bdc_motor_t *motor) -{ - bdc_motor_mcpwm_obj *mcpwm_motor = __containerof(motor, bdc_motor_mcpwm_obj, base); - ESP_RETURN_ON_ERROR(mcpwm_generator_set_force_level(mcpwm_motor->gena, 0, true), TAG, "set force level for gena failed"); - ESP_RETURN_ON_ERROR(mcpwm_generator_set_force_level(mcpwm_motor->genb, 0, true), TAG, "set force level for genb failed"); - return ESP_OK; -} - -static esp_err_t bdc_motor_mcpwm_brake(bdc_motor_t *motor) -{ - bdc_motor_mcpwm_obj *mcpwm_motor = __containerof(motor, bdc_motor_mcpwm_obj, base); - ESP_RETURN_ON_ERROR(mcpwm_generator_set_force_level(mcpwm_motor->gena, 1, true), TAG, "set force level for gena failed"); - ESP_RETURN_ON_ERROR(mcpwm_generator_set_force_level(mcpwm_motor->genb, 1, true), TAG, "set force level for genb failed"); - return ESP_OK; -} - -static esp_err_t bdc_motor_mcpwm_del(bdc_motor_t *motor) -{ - bdc_motor_mcpwm_obj *mcpwm_motor = __containerof(motor, bdc_motor_mcpwm_obj, base); - mcpwm_del_generator(mcpwm_motor->gena); - mcpwm_del_generator(mcpwm_motor->genb); - mcpwm_del_comparator(mcpwm_motor->cmpa); - mcpwm_del_comparator(mcpwm_motor->cmpb); - mcpwm_del_operator(mcpwm_motor->operator); - mcpwm_del_timer(mcpwm_motor->timer); - free(mcpwm_motor); - return ESP_OK; -} - -esp_err_t bdc_motor_new_mcpwm_device(const bdc_motor_config_t *motor_config, const bdc_motor_mcpwm_config_t *mcpwm_config, bdc_motor_handle_t *ret_motor) -{ - bdc_motor_mcpwm_obj *mcpwm_motor = NULL; - esp_err_t ret = ESP_OK; - ESP_GOTO_ON_FALSE(motor_config && mcpwm_config && ret_motor, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument"); - mcpwm_motor = calloc(1, sizeof(bdc_motor_mcpwm_obj)); - ESP_GOTO_ON_FALSE(mcpwm_motor, ESP_ERR_NO_MEM, err, TAG, "no mem for rmt motor"); - - // mcpwm timer - mcpwm_timer_config_t timer_config = { - .group_id = mcpwm_config->group_id, - .clk_src = MCPWM_TIMER_CLK_SRC_DEFAULT, - .resolution_hz = mcpwm_config->resolution_hz, - .period_ticks = mcpwm_config->resolution_hz / motor_config->pwm_freq_hz, - .count_mode = MCPWM_TIMER_COUNT_MODE_UP, - }; - ESP_GOTO_ON_ERROR(mcpwm_new_timer(&timer_config, &mcpwm_motor->timer), err, TAG, "create MCPWM timer failed"); - - mcpwm_operator_config_t operator_config = { - .group_id = mcpwm_config->group_id, - }; - ESP_GOTO_ON_ERROR(mcpwm_new_operator(&operator_config, &mcpwm_motor->operator), err, TAG, "create MCPWM operator failed"); - - ESP_GOTO_ON_ERROR(mcpwm_operator_connect_timer(mcpwm_motor->operator, mcpwm_motor->timer), err, TAG, "connect timer and operator failed"); - - mcpwm_comparator_config_t comparator_config = { - .flags.update_cmp_on_tez = true, - }; - ESP_GOTO_ON_ERROR(mcpwm_new_comparator(mcpwm_motor->operator, &comparator_config, &mcpwm_motor->cmpa), err, TAG, "create comparator failed"); - ESP_GOTO_ON_ERROR(mcpwm_new_comparator(mcpwm_motor->operator, &comparator_config, &mcpwm_motor->cmpb), err, TAG, "create comparator failed"); - - // set the initial compare value for both comparators - mcpwm_comparator_set_compare_value(mcpwm_motor->cmpa, 0); - mcpwm_comparator_set_compare_value(mcpwm_motor->cmpb, 0); - - mcpwm_generator_config_t generator_config = { - .gen_gpio_num = motor_config->pwma_gpio_num, - }; - ESP_GOTO_ON_ERROR(mcpwm_new_generator(mcpwm_motor->operator, &generator_config, &mcpwm_motor->gena), err, TAG, "create generator failed"); - generator_config.gen_gpio_num = motor_config->pwmb_gpio_num; - ESP_GOTO_ON_ERROR(mcpwm_new_generator(mcpwm_motor->operator, &generator_config, &mcpwm_motor->genb), err, TAG, "create generator failed"); - - mcpwm_generator_set_actions_on_timer_event(mcpwm_motor->gena, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH), - MCPWM_GEN_TIMER_EVENT_ACTION_END()); - mcpwm_generator_set_actions_on_compare_event(mcpwm_motor->gena, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, mcpwm_motor->cmpa, MCPWM_GEN_ACTION_LOW), - MCPWM_GEN_COMPARE_EVENT_ACTION_END()); - mcpwm_generator_set_actions_on_timer_event(mcpwm_motor->genb, - MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH), - MCPWM_GEN_TIMER_EVENT_ACTION_END()); - mcpwm_generator_set_actions_on_compare_event(mcpwm_motor->genb, - MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, mcpwm_motor->cmpb, MCPWM_GEN_ACTION_LOW), - MCPWM_GEN_COMPARE_EVENT_ACTION_END()); - - mcpwm_motor->base.enable = bdc_motor_mcpwm_enable; - mcpwm_motor->base.disable = bdc_motor_mcpwm_disable; - mcpwm_motor->base.forward = bdc_motor_mcpwm_forward; - mcpwm_motor->base.reverse = bdc_motor_mcpwm_reverse; - mcpwm_motor->base.coast = bdc_motor_mcpwm_coast; - mcpwm_motor->base.brake = bdc_motor_mcpwm_brake; - mcpwm_motor->base.set_speed = bdc_motor_mcpwm_set_speed; - mcpwm_motor->base.del = bdc_motor_mcpwm_del; - *ret_motor = &mcpwm_motor->base; - return ESP_OK; - -err: - if (mcpwm_motor) { - if (mcpwm_motor->gena) { - mcpwm_del_generator(mcpwm_motor->gena); - } - if (mcpwm_motor->genb) { - mcpwm_del_generator(mcpwm_motor->genb); - } - if (mcpwm_motor->cmpa) { - mcpwm_del_comparator(mcpwm_motor->cmpa); - } - if (mcpwm_motor->cmpb) { - mcpwm_del_comparator(mcpwm_motor->cmpb); - } - if (mcpwm_motor->operator) { - mcpwm_del_operator(mcpwm_motor->operator); - } - if (mcpwm_motor->timer) { - mcpwm_del_timer(mcpwm_motor->timer); - } - free(mcpwm_motor); - } - return ret; -} diff --git a/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/main/idf_component.yml b/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/main/idf_component.yml index 7d51337b61..4beea621a6 100644 --- a/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/main/idf_component.yml +++ b/examples/peripherals/mcpwm/mcpwm_bdc_speed_control/main/idf_component.yml @@ -1,2 +1,3 @@ dependencies: pid_ctrl: "^0.1.1" + bdc_motor: "^0.1.0" diff --git a/examples/peripherals/mcpwm/mcpwm_bldc_hall_control/main/CMakeLists.txt b/examples/peripherals/mcpwm/mcpwm_bldc_hall_control/main/CMakeLists.txt index 2ecff3751d..1d97d04dc0 100644 --- a/examples/peripherals/mcpwm/mcpwm_bldc_hall_control/main/CMakeLists.txt +++ b/examples/peripherals/mcpwm/mcpwm_bldc_hall_control/main/CMakeLists.txt @@ -1,3 +1,2 @@ idf_component_register(SRCS "mcpwm_bldc_hall_control_example_main.c" INCLUDE_DIRS ".") -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/mcpwm/mcpwm_bldc_hall_control/main/mcpwm_bldc_hall_control_example_main.c b/examples/peripherals/mcpwm/mcpwm_bldc_hall_control/main/mcpwm_bldc_hall_control_example_main.c index 3fcb12d21e..f6e4d86bd1 100644 --- a/examples/peripherals/mcpwm/mcpwm_bldc_hall_control/main/mcpwm_bldc_hall_control_example_main.c +++ b/examples/peripherals/mcpwm/mcpwm_bldc_hall_control/main/mcpwm_bldc_hall_control_example_main.c @@ -321,6 +321,15 @@ void app_main(void) ESP_ERROR_CHECK(mcpwm_capture_channel_register_event_callbacks(cap_channels[i], &cbs, task_to_notify)); } + ESP_LOGI(TAG, "Enable capture channels"); + for (int i = 0; i < 3; i++) { + ESP_ERROR_CHECK(mcpwm_capture_channel_enable(cap_channels[i])); + } + + ESP_LOGI(TAG, "Enable and start capture timer"); + ESP_ERROR_CHECK(mcpwm_capture_timer_enable(cap_timer)); + ESP_ERROR_CHECK(mcpwm_capture_timer_start(cap_timer)); + ESP_LOGI(TAG, "Start a timer to adjust motor speed periodically"); esp_timer_handle_t periodic_timer = NULL; const esp_timer_create_args_t periodic_timer_args = { @@ -344,7 +353,7 @@ void app_main(void) if (hall_sensor_value >= 1 && hall_sensor_value <= 6) { s_hall_actions[hall_sensor_value](generators); } else { - ESP_LOGE(TAG, "invalid bldc phase, wrong hall sensor value:%d", hall_sensor_value); + ESP_LOGE(TAG, "invalid bldc phase, wrong hall sensor value:%"PRIu32, hall_sensor_value); } ulTaskNotifyTake(pdTRUE, portMAX_DELAY); } diff --git a/examples/peripherals/mcpwm/mcpwm_capture_hc_sr04/main/CMakeLists.txt b/examples/peripherals/mcpwm/mcpwm_capture_hc_sr04/main/CMakeLists.txt index bd120826dd..450a211ce5 100644 --- a/examples/peripherals/mcpwm/mcpwm_capture_hc_sr04/main/CMakeLists.txt +++ b/examples/peripherals/mcpwm/mcpwm_capture_hc_sr04/main/CMakeLists.txt @@ -1,3 +1,2 @@ idf_component_register(SRCS "mcpwm_capture_hc_sr04.c" INCLUDE_DIRS ".") -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/mcpwm/mcpwm_capture_hc_sr04/main/mcpwm_capture_hc_sr04.c b/examples/peripherals/mcpwm/mcpwm_capture_hc_sr04/main/mcpwm_capture_hc_sr04.c index b18fbfe81e..10e8a55eef 100644 --- a/examples/peripherals/mcpwm/mcpwm_capture_hc_sr04/main/mcpwm_capture_hc_sr04.c +++ b/examples/peripherals/mcpwm/mcpwm_capture_hc_sr04/main/mcpwm_capture_hc_sr04.c @@ -83,6 +83,9 @@ void app_main(void) }; ESP_ERROR_CHECK(mcpwm_capture_channel_register_event_callbacks(cap_chan, &cbs, cur_task)); + ESP_LOGI(TAG, "Enable capture channel"); + ESP_ERROR_CHECK(mcpwm_capture_channel_enable(cap_chan)); + ESP_LOGI(TAG, "Configure Trig pin"); gpio_config_t io_conf = { .mode = GPIO_MODE_OUTPUT, diff --git a/examples/peripherals/mcpwm/mcpwm_capture_hc_sr04/pytest_hc_sr04.py b/examples/peripherals/mcpwm/mcpwm_capture_hc_sr04/pytest_hc_sr04.py index 6e519dff82..70ca04bc69 100644 --- a/examples/peripherals/mcpwm/mcpwm_capture_hc_sr04/pytest_hc_sr04.py +++ b/examples/peripherals/mcpwm/mcpwm_capture_hc_sr04/pytest_hc_sr04.py @@ -12,5 +12,6 @@ def test_hc_sr04_example(dut: Dut) -> None: dut.expect_exact('example: Install capture timer') dut.expect_exact('example: Install capture channel') dut.expect_exact('example: Register capture callback') + dut.expect_exact('example: Enable capture channel') dut.expect_exact('example: Configure Trig pin') dut.expect_exact('example: Enable and start capture timer') diff --git a/examples/peripherals/mcpwm/mcpwm_servo_control/main/mcpwm_servo_control_example_main.c b/examples/peripherals/mcpwm/mcpwm_servo_control/main/mcpwm_servo_control_example_main.c index c905eeafc8..1d79651a12 100644 --- a/examples/peripherals/mcpwm/mcpwm_servo_control/main/mcpwm_servo_control_example_main.c +++ b/examples/peripherals/mcpwm/mcpwm_servo_control/main/mcpwm_servo_control_example_main.c @@ -39,27 +39,27 @@ void app_main(void) }; ESP_ERROR_CHECK(mcpwm_new_timer(&timer_config, &timer)); - mcpwm_oper_handle_t operator = NULL; + mcpwm_oper_handle_t oper = NULL; mcpwm_operator_config_t operator_config = { .group_id = 0, // operator must be in the same group to the timer }; - ESP_ERROR_CHECK(mcpwm_new_operator(&operator_config, &operator)); + ESP_ERROR_CHECK(mcpwm_new_operator(&operator_config, &oper)); ESP_LOGI(TAG, "Connect timer and operator"); - ESP_ERROR_CHECK(mcpwm_operator_connect_timer(operator, timer)); + ESP_ERROR_CHECK(mcpwm_operator_connect_timer(oper, timer)); ESP_LOGI(TAG, "Create comparator and generator from the operator"); mcpwm_cmpr_handle_t comparator = NULL; mcpwm_comparator_config_t comparator_config = { .flags.update_cmp_on_tez = true, }; - ESP_ERROR_CHECK(mcpwm_new_comparator(operator, &comparator_config, &comparator)); + ESP_ERROR_CHECK(mcpwm_new_comparator(oper, &comparator_config, &comparator)); mcpwm_gen_handle_t generator = NULL; mcpwm_generator_config_t generator_config = { .gen_gpio_num = SERVO_PULSE_GPIO, }; - ESP_ERROR_CHECK(mcpwm_new_generator(operator, &generator_config, &generator)); + ESP_ERROR_CHECK(mcpwm_new_generator(oper, &generator_config, &generator)); // set the initial compare value, so that the servo will spin to the center position ESP_ERROR_CHECK(mcpwm_comparator_set_compare_value(comparator, example_angle_to_compare(0))); diff --git a/examples/peripherals/rmt/musical_buzzer/README.md b/examples/peripherals/rmt/musical_buzzer/README.md index 1db9f79d10..0d6d0ad43e 100644 --- a/examples/peripherals/rmt/musical_buzzer/README.md +++ b/examples/peripherals/rmt/musical_buzzer/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C3 | ESP32-H2 | ESP32-S2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | # RMT Transmit Loop Count Example -- Musical Buzzer diff --git a/examples/peripherals/rmt/musical_buzzer/pytest_musical_buzzer.py b/examples/peripherals/rmt/musical_buzzer/pytest_musical_buzzer.py index 84d7fd3f83..0e03953bc3 100644 --- a/examples/peripherals/rmt/musical_buzzer/pytest_musical_buzzer.py +++ b/examples/peripherals/rmt/musical_buzzer/pytest_musical_buzzer.py @@ -8,7 +8,7 @@ from pytest_embedded import Dut @pytest.mark.esp32s2 @pytest.mark.esp32s3 @pytest.mark.esp32c3 -@pytest.mark.esp32h2 +# @pytest.mark.esp32h2 TODO: uncomment this when remove --preview for h2 @pytest.mark.generic def test_musical_buzzer_example(dut: Dut) -> None: dut.expect_exact('example: Create RMT TX channel') diff --git a/examples/peripherals/sdio/README.md b/examples/peripherals/sdio/README.md index 162c6963e4..845dd9a1bd 100644 --- a/examples/peripherals/sdio/README.md +++ b/examples/peripherals/sdio/README.md @@ -104,8 +104,14 @@ and ``api_reference/peripherals/sd_pullup_requirements`` to see more descriptions about pullups and MTDI requirements and solutions of official modules and devkits. -## About `esp_serial_slave_link` component used in this example +## About `esp_serial_slave_link` component used in the host example -`esp_serial_slave_link` component in the IDF is used to communicate to a ESP slave device. -When the `esp_serial_slave_link` device is initialized with an `essl_sdio_config_t` structure, -the `esp_serial_slave_link` can be used to communicate with an ESP32 SDIO slave. +The host example is based on [esp_serial_slave_link component](https://components.espressif.com/components/espressif/esp_serial_slave_link), which is used to communicate to a ESP slave device. + +The component can be installed by esp component manager. Since this example already installed it, no need to re-installed it again, but if you want to install this component in your own project, you can input the following command: + +``` +idf.py add-dependency espressif/esp_serial_slave_link +``` + +If the dependency is added, you can check `idf_component.yml` for more detail. When building this example or other projects with managed components, the component manager will search for the required components online and download them into the `managed_componets` folder. diff --git a/examples/peripherals/sdio/host/main/CMakeLists.txt b/examples/peripherals/sdio/host/main/CMakeLists.txt index c31750a8f7..61fac40e63 100644 --- a/examples/peripherals/sdio/host/main/CMakeLists.txt +++ b/examples/peripherals/sdio/host/main/CMakeLists.txt @@ -1,3 +1,2 @@ idf_component_register(SRCS "app_main.c" INCLUDE_DIRS ".") -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/sdio/host/main/app_main.c b/examples/peripherals/sdio/host/main/app_main.c index 2dfa2165d4..055b52e4fe 100644 --- a/examples/peripherals/sdio/host/main/app_main.c +++ b/examples/peripherals/sdio/host/main/app_main.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "freertos/FreeRTOS.h" #include "freertos/task.h" @@ -24,6 +25,8 @@ #include "sdkconfig.h" #include "driver/sdmmc_host.h" #include "driver/sdspi_host.h" +#include "sdmmc_cmd.h" + #define TIMEOUT_MAX UINT32_MAX @@ -307,7 +310,7 @@ static esp_err_t get_intr(essl_handle_t handle, uint32_t* out_raw, uint32_t* out if (ret != ESP_OK) return ret; ret = essl_clear_intr(handle, *out_raw, TIMEOUT_MAX); if (ret != ESP_OK) return ret; - ESP_LOGD(TAG, "intr: %08X", *out_raw); + ESP_LOGD(TAG, "intr: %08"PRIX32, *out_raw); return ESP_OK; } @@ -411,8 +414,8 @@ void job_fifo(essl_handle_t handle) const int wait_ms = 50; int length = packet_len[i]; ret = essl_send_packet(handle, send_buffer + pointer, length, wait_ms); - if (ret == ESP_ERR_TIMEOUT) { - ESP_LOGD(TAG, "several packets are expected to timeout."); + if (ret == ESP_ERR_TIMEOUT || ret == ESP_ERR_NOT_FOUND) { + ESP_LOGD(TAG, "slave not ready to receive packet %d", i); // And there are several packets expected to timeout. } else { ESP_ERROR_CHECK(ret); ESP_LOGI(TAG, "send packet length: %d", length); diff --git a/examples/peripherals/sdio/host/main/idf_component.yml b/examples/peripherals/sdio/host/main/idf_component.yml new file mode 100644 index 0000000000..d693bfe039 --- /dev/null +++ b/examples/peripherals/sdio/host/main/idf_component.yml @@ -0,0 +1,2 @@ +dependencies: + espressif/esp_serial_slave_link: "^1.0.0" diff --git a/examples/peripherals/secure_element/atecc608_ecdsa/components/esp-cryptoauthlib b/examples/peripherals/secure_element/atecc608_ecdsa/components/esp-cryptoauthlib deleted file mode 160000 index 985ea960f8..0000000000 --- a/examples/peripherals/secure_element/atecc608_ecdsa/components/esp-cryptoauthlib +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 985ea960f83f67f66881e2dae57097e2a07b92a0 diff --git a/examples/peripherals/secure_element/atecc608_ecdsa/main/idf_component.yml b/examples/peripherals/secure_element/atecc608_ecdsa/main/idf_component.yml new file mode 100644 index 0000000000..6eb177a228 --- /dev/null +++ b/examples/peripherals/secure_element/atecc608_ecdsa/main/idf_component.yml @@ -0,0 +1,3 @@ +## IDF Component Manager Manifest File +dependencies: + espressif/esp-cryptoauthlib: "^3.3.1" diff --git a/examples/peripherals/spi_master/lcd/main/CMakeLists.txt b/examples/peripherals/spi_master/lcd/main/CMakeLists.txt index a59f4a0ae5..0d34bee60e 100644 --- a/examples/peripherals/spi_master/lcd/main/CMakeLists.txt +++ b/examples/peripherals/spi_master/lcd/main/CMakeLists.txt @@ -6,5 +6,3 @@ set(srcs "pretty_effect.c" idf_component_register(SRCS ${srcs} INCLUDE_DIRS "." EMBED_FILES image.jpg) - -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/spi_master/lcd/main/decode_image.c b/examples/peripherals/spi_master/lcd/main/decode_image.c index a9a460bc39..bedaf4334d 100644 --- a/examples/peripherals/spi_master/lcd/main/decode_image.c +++ b/examples/peripherals/spi_master/lcd/main/decode_image.c @@ -18,132 +18,54 @@ format if you want to use a different image file. */ #include "decode_image.h" -#include "esp_rom_tjpgd.h" +#include "jpeg_decoder.h" #include "esp_log.h" +#include "esp_check.h" #include +#include "freertos/FreeRTOS.h" //Reference the binary-included jpeg file extern const uint8_t image_jpg_start[] asm("_binary_image_jpg_start"); extern const uint8_t image_jpg_end[] asm("_binary_image_jpg_end"); //Define the height and width of the jpeg file. Make sure this matches the actual jpeg //dimensions. -#define IMAGE_W 336 -#define IMAGE_H 256 const char *TAG = "ImageDec"; -//Data that is passed from the decoder function to the infunc/outfunc functions. -typedef struct { - const unsigned char *inData; //Pointer to jpeg data - uint16_t inPos; //Current position in jpeg data - uint16_t **outData; //Array of IMAGE_H pointers to arrays of IMAGE_W 16-bit pixel values - int outW; //Width of the resulting file - int outH; //Height of the resulting file -} JpegDev; - -//Input function for jpeg decoder. Just returns bytes from the inData field of the JpegDev structure. -static uint32_t infunc(esp_rom_tjpgd_dec_t *decoder, uint8_t *buf, uint32_t len) -{ - //Read bytes from input file - JpegDev *jd = (JpegDev *)decoder->device; - if (buf != NULL) { - memcpy(buf, jd->inData + jd->inPos, len); - } - jd->inPos += len; - return len; -} - -//Output function. Re-encodes the RGB888 data from the decoder as big-endian RGB565 and -//stores it in the outData array of the JpegDev structure. -static uint32_t outfunc(esp_rom_tjpgd_dec_t *decoder, void *bitmap, esp_rom_tjpgd_rect_t *rect) -{ - JpegDev *jd = (JpegDev *)decoder->device; - uint8_t *in = (uint8_t *)bitmap; - for (int y = rect->top; y <= rect->bottom; y++) { - for (int x = rect->left; x <= rect->right; x++) { - //We need to convert the 3 bytes in `in` to a rgb565 value. - uint16_t v = 0; - v |= ((in[0] >> 3) << 11); - v |= ((in[1] >> 2) << 5); - v |= ((in[2] >> 3) << 0); - //The LCD wants the 16-bit value in big-endian, so swap bytes - v = (v >> 8) | (v << 8); - jd->outData[y][x] = v; - in += 3; - } - } - return 1; -} - -//Size of the work space for the jpeg decoder. -#define WORKSZ 3100 - //Decode the embedded image into pixel lines that can be used with the rest of the logic. -esp_err_t decode_image(uint16_t ***pixels) +esp_err_t decode_image(uint16_t **pixels) { - char *work = NULL; - int r; - esp_rom_tjpgd_dec_t decoder; - JpegDev jd; *pixels = NULL; esp_err_t ret = ESP_OK; //Alocate pixel memory. Each line is an array of IMAGE_W 16-bit pixels; the `*pixels` array itself contains pointers to these lines. - *pixels = calloc(IMAGE_H, sizeof(uint16_t *)); - if (*pixels == NULL) { - ESP_LOGE(TAG, "Error allocating memory for lines"); - ret = ESP_ERR_NO_MEM; - goto err; - } - for (int i = 0; i < IMAGE_H; i++) { - (*pixels)[i] = malloc(IMAGE_W * sizeof(uint16_t)); - if ((*pixels)[i] == NULL) { - ESP_LOGE(TAG, "Error allocating memory for line %d", i); - ret = ESP_ERR_NO_MEM; - goto err; + *pixels = calloc(IMAGE_H * IMAGE_W, sizeof(uint16_t)); + ESP_GOTO_ON_FALSE((*pixels), ESP_ERR_NO_MEM, err, TAG, "Error allocating memory for lines"); + + //JPEG decode config + esp_jpeg_image_cfg_t jpeg_cfg = { + .indata = (uint8_t *)image_jpg_start, + .indata_size = image_jpg_end - image_jpg_start, + .outbuf = (uint8_t*)(*pixels), + .outbuf_size = IMAGE_W * IMAGE_H * sizeof(uint16_t), + .out_format = JPEG_IMAGE_FORMAT_RGB565, + .out_scale = JPEG_IMAGE_SCALE_0, + .flags = { + .swap_color_bytes = 1, } - } + }; - //Allocate the work space for the jpeg decoder. - work = calloc(WORKSZ, 1); - if (work == NULL) { - ESP_LOGE(TAG, "Cannot allocate workspace"); - ret = ESP_ERR_NO_MEM; - goto err; - } + //JPEG decode + esp_jpeg_image_output_t outimg; + esp_jpeg_decode(&jpeg_cfg, &outimg); - //Populate fields of the JpegDev struct. - jd.inData = image_jpg_start; - jd.inPos = 0; - jd.outData = *pixels; - jd.outW = IMAGE_W; - jd.outH = IMAGE_H; + ESP_LOGI(TAG, "JPEG image decoded! Size of the decoded image is: %dpx x %dpx", outimg.width, outimg.height); - //Prepare and decode the jpeg. - r = esp_rom_tjpgd_prepare(&decoder, infunc, work, WORKSZ, (void *)&jd); - if (r != JDR_OK) { - ESP_LOGE(TAG, "Image decoder: jd_prepare failed (%d)", r); - ret = ESP_ERR_NOT_SUPPORTED; - goto err; - } - r = esp_rom_tjpgd_decomp(&decoder, outfunc, 0); - if (r != JDR_OK && r != JDR_FMT1) { - ESP_LOGE(TAG, "Image decoder: jd_decode failed (%d)", r); - ret = ESP_ERR_NOT_SUPPORTED; - goto err; - } - - //All done! Free the work area (as we don't need it anymore) and return victoriously. - free(work); return ret; err: //Something went wrong! Exit cleanly, de-allocating everything we allocated. if (*pixels != NULL) { - for (int i = 0; i < IMAGE_H; i++) { - free((*pixels)[i]); - } free(*pixels); } - free(work); return ret; } diff --git a/examples/peripherals/spi_master/lcd/main/decode_image.h b/examples/peripherals/spi_master/lcd/main/decode_image.h index 1e31e3d1cd..c9aaf0cd02 100644 --- a/examples/peripherals/spi_master/lcd/main/decode_image.h +++ b/examples/peripherals/spi_master/lcd/main/decode_image.h @@ -10,6 +10,9 @@ #include #include "esp_err.h" +#define IMAGE_W 320 +#define IMAGE_H 240 + #ifdef __cplusplus extern "C" { #endif @@ -23,7 +26,7 @@ extern "C" { * - ESP_ERR_NO_MEM if out of memory * - ESP_OK on succesful decode */ -esp_err_t decode_image(uint16_t ***pixels); +esp_err_t decode_image(uint16_t **pixels); #ifdef __cplusplus } diff --git a/examples/peripherals/spi_master/lcd/main/idf_component.yml b/examples/peripherals/spi_master/lcd/main/idf_component.yml new file mode 100644 index 0000000000..a2167bf4c2 --- /dev/null +++ b/examples/peripherals/spi_master/lcd/main/idf_component.yml @@ -0,0 +1,3 @@ +dependencies: + idf: ">=4.4" + esp_jpeg: ">=1.0.2" diff --git a/examples/peripherals/spi_master/lcd/main/image.jpg b/examples/peripherals/spi_master/lcd/main/image.jpg index 803ca2cdca..cacad09050 100644 Binary files a/examples/peripherals/spi_master/lcd/main/image.jpg and b/examples/peripherals/spi_master/lcd/main/image.jpg differ diff --git a/examples/peripherals/spi_master/lcd/main/pretty_effect.c b/examples/peripherals/spi_master/lcd/main/pretty_effect.c index 2923b7cf6f..9c6887977e 100644 --- a/examples/peripherals/spi_master/lcd/main/pretty_effect.c +++ b/examples/peripherals/spi_master/lcd/main/pretty_effect.c @@ -14,16 +14,15 @@ #include "sdkconfig.h" #include "decode_image.h" -uint16_t **pixels; +uint16_t *pixels; //Grab a rgb16 pixel from the esp32_tiles image static inline uint16_t get_bgnd_pixel(int x, int y) { - //Image has an 8x8 pixel margin, so we can also resolve e.g. [-3, 243] - x+=8; - y+=8; - return pixels[y][x]; + //Get color of the pixel on x,y coords + return (uint16_t) *(pixels + (y * IMAGE_W) + x); } + //This variable is used to detect the next frame. static int prev_frame=-1; diff --git a/examples/peripherals/spi_master/lcd/main/spi_master_example_main.c b/examples/peripherals/spi_master/lcd/main/spi_master_example_main.c index f46e4b0a28..fba231f517 100644 --- a/examples/peripherals/spi_master/lcd/main/spi_master_example_main.c +++ b/examples/peripherals/spi_master/lcd/main/spi_master_example_main.c @@ -9,6 +9,7 @@ #include #include #include +#include #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "esp_system.h" @@ -272,7 +273,7 @@ void lcd_init(spi_device_handle_t spi) int lcd_detected_type = 0; int lcd_type; - printf("LCD ID: %08X\n", lcd_id); + printf("LCD ID: %08"PRIx32"\n", lcd_id); if ( lcd_id == 0 ) { //zero, ili lcd_detected_type = LCD_TYPE_ILI; diff --git a/examples/peripherals/spi_slave_hd/append_mode/README.md b/examples/peripherals/spi_slave_hd/append_mode/README.md index 8580aeca86..d28b9f27aa 100644 --- a/examples/peripherals/spi_slave_hd/append_mode/README.md +++ b/examples/peripherals/spi_slave_hd/append_mode/README.md @@ -31,6 +31,17 @@ This example requires 2 targets. Here we use 2 ESP32S2 DevKits to act as the SPI Feel free to modify the pin setting defined on the top of the ``app_main.c``. +### Dependency + +The master example is based on [esp_serial_slave_link component](https://components.espressif.com/components/espressif/esp_serial_slave_link), which is used to communicate to a ESP slave device. + +The component can be installed by esp component manager. Since this example already installed it, no need to re-installed it again, but if you want to install this component in your own project, you can input the following command: +``` +idf.py add-dependency espressif/esp_serial_slave_link +``` + +If the dependency is added, you can check `idf_component.yml` for more detail. When building this example or other projects with managed components, the component manager will search for the required components online and download them into the `managed_componets` folder. + ### Configure the project * Set the target of the build (where `{IDF_TARGET}` stands for the target chip such as `esp32s2`). diff --git a/examples/peripherals/spi_slave_hd/append_mode/master/main/app_main.c b/examples/peripherals/spi_slave_hd/append_mode/master/main/app_main.c index 58c0b6ccec..855d7cc9fd 100644 --- a/examples/peripherals/spi_slave_hd/append_mode/master/main/app_main.c +++ b/examples/peripherals/spi_slave_hd/append_mode/master/main/app_main.c @@ -8,6 +8,8 @@ */ #include "esp_log.h" #include "esp_err.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" #include "driver/spi_common.h" #include "driver/spi_master.h" #include "esp_serial_slave_link/essl.h" diff --git a/examples/peripherals/spi_slave_hd/append_mode/master/main/idf_component.yml b/examples/peripherals/spi_slave_hd/append_mode/master/main/idf_component.yml new file mode 100644 index 0000000000..d693bfe039 --- /dev/null +++ b/examples/peripherals/spi_slave_hd/append_mode/master/main/idf_component.yml @@ -0,0 +1,2 @@ +dependencies: + espressif/esp_serial_slave_link: "^1.0.0" diff --git a/examples/peripherals/spi_slave_hd/append_mode/slave/main/CMakeLists.txt b/examples/peripherals/spi_slave_hd/append_mode/slave/main/CMakeLists.txt index c31750a8f7..61fac40e63 100644 --- a/examples/peripherals/spi_slave_hd/append_mode/slave/main/CMakeLists.txt +++ b/examples/peripherals/spi_slave_hd/append_mode/slave/main/CMakeLists.txt @@ -1,3 +1,2 @@ idf_component_register(SRCS "app_main.c" INCLUDE_DIRS ".") -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/spi_slave_hd/append_mode/slave/main/app_main.c b/examples/peripherals/spi_slave_hd/append_mode/slave/main/app_main.c index 672fd283f6..9e6d1ef578 100644 --- a/examples/peripherals/spi_slave_hd/append_mode/slave/main/app_main.c +++ b/examples/peripherals/spi_slave_hd/append_mode/slave/main/app_main.c @@ -14,7 +14,6 @@ #include "freertos/task.h" #include "freertos/semphr.h" #include "driver/spi_slave_hd.h" -#include "esp_serial_slave_link/essl_spi.h" #define GPIO_MOSI 11 #define GPIO_MISO 13 diff --git a/examples/peripherals/spi_slave_hd/segment_mode/seg_master/main/CMakeLists.txt b/examples/peripherals/spi_slave_hd/segment_mode/seg_master/main/CMakeLists.txt index c31750a8f7..61fac40e63 100644 --- a/examples/peripherals/spi_slave_hd/segment_mode/seg_master/main/CMakeLists.txt +++ b/examples/peripherals/spi_slave_hd/segment_mode/seg_master/main/CMakeLists.txt @@ -1,3 +1,2 @@ idf_component_register(SRCS "app_main.c" INCLUDE_DIRS ".") -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/spi_slave_hd/segment_mode/seg_master/main/app_main.c b/examples/peripherals/spi_slave_hd/segment_mode/seg_master/main/app_main.c index 59022bb485..667342090a 100644 --- a/examples/peripherals/spi_slave_hd/segment_mode/seg_master/main/app_main.c +++ b/examples/peripherals/spi_slave_hd/segment_mode/seg_master/main/app_main.c @@ -207,8 +207,8 @@ void app_main(void) ESP_ERROR_CHECK(get_slave_max_buf_size(spi, &slave_max_tx_buf_size, &slave_max_rx_buf_size)); uint32_t rx_buf_size = slave_max_tx_buf_size; printf("\n\n---------SLAVE INFO---------\n\n"); - printf("Slave MAX Send Buffer Size: %d\n", slave_max_tx_buf_size); - printf("Slave MAX Receive Buffer Size: %d\n", slave_max_rx_buf_size); + printf("Slave MAX Send Buffer Size: %"PRIu32"\n", slave_max_tx_buf_size); + printf("Slave MAX Receive Buffer Size: %"PRIu32"\n", slave_max_rx_buf_size); uint8_t *recv_buf = heap_caps_calloc(1, rx_buf_size, MALLOC_CAP_DMA); if (!recv_buf) { @@ -245,7 +245,7 @@ void app_main(void) uint32_t size_can_be_read = get_slave_tx_buf_size(spi) - size_has_read; if (size_can_be_read > rx_buf_size) { - ESP_LOGW(TAG, "Slave is going to send buffer(%d Bytes) larger than pre-negotiated MAX size", size_can_be_read); + ESP_LOGW(TAG, "Slave is going to send buffer(%"PRIu32" Bytes) larger than pre-negotiated MAX size", size_can_be_read); /** * NOTE: * In this condition, Master should still increase its counter (``size_has_read``) by the size that Slave has loaded, @@ -277,7 +277,7 @@ void app_main(void) //Prepare your TX transaction in your own way. Here is an example. //You can set any size to send (shorter, longer or equal to the Slave Max RX buf size), Slave can get the actual length by ``trans_len`` member of ``spi_slave_hd_data_t`` uint32_t actual_tx_size = (rand() % (slave_max_rx_buf_size - TX_SIZE_MIN + 1)) + TX_SIZE_MIN; - snprintf((char *)send_buf, slave_max_rx_buf_size, "this is master's transaction %d", tx_trans_id); + snprintf((char *)send_buf, slave_max_rx_buf_size, "this is master's transaction %"PRIu32, tx_trans_id); for (int i = 0; i < num_to_send; i++) { ESP_ERROR_CHECK(essl_spi_wrdma(spi, send_buf, actual_tx_size, -1, 0)); diff --git a/examples/peripherals/spi_slave_hd/segment_mode/seg_master/main/idf_component.yml b/examples/peripherals/spi_slave_hd/segment_mode/seg_master/main/idf_component.yml new file mode 100644 index 0000000000..d693bfe039 --- /dev/null +++ b/examples/peripherals/spi_slave_hd/segment_mode/seg_master/main/idf_component.yml @@ -0,0 +1,2 @@ +dependencies: + espressif/esp_serial_slave_link: "^1.0.0" diff --git a/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/main/CMakeLists.txt b/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/main/CMakeLists.txt index c31750a8f7..61fac40e63 100644 --- a/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/main/CMakeLists.txt +++ b/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/main/CMakeLists.txt @@ -1,3 +1,2 @@ idf_component_register(SRCS "app_main.c" INCLUDE_DIRS ".") -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/main/app_main.c b/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/main/app_main.c index 0801e8a975..1945f2fed9 100644 --- a/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/main/app_main.c +++ b/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/main/app_main.c @@ -156,7 +156,7 @@ static bool get_tx_data(uint8_t *data, uint32_t max_len, uint32_t *out_len) return false; } - snprintf((char *)data, *out_len, "Transaction No.%d from slave, length: %d", s_tx_data_id, *out_len); + snprintf((char *)data, *out_len, "Transaction No.%"PRIu32" from slave, length: %"PRIu32, s_tx_data_id, *out_len); s_tx_data_id++; return true; } diff --git a/examples/peripherals/temp_sensor/main/CMakeLists.txt b/examples/peripherals/temp_sensor/main/CMakeLists.txt index 84c61f9473..8e713a2504 100644 --- a/examples/peripherals/temp_sensor/main/CMakeLists.txt +++ b/examples/peripherals/temp_sensor/main/CMakeLists.txt @@ -1,3 +1,2 @@ idf_component_register(SRCS "temp_sensor_main.c" - INCLUDE_DIRS ".") -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") + INCLUDE_DIRS ".") diff --git a/examples/peripherals/timer_group/gptimer/pytest_gptimer_example.py b/examples/peripherals/timer_group/gptimer/pytest_gptimer_example.py index 0aa647f6aa..309beee822 100644 --- a/examples/peripherals/timer_group/gptimer/pytest_gptimer_example.py +++ b/examples/peripherals/timer_group/gptimer/pytest_gptimer_example.py @@ -12,7 +12,7 @@ def test_gptimer_example(dut: Dut) -> None: dut.expect_exact('Start timer, stop it at alarm event', timeout=5) res = dut.expect(r'Timer stopped, count=(\d+)', timeout=30) stopped_count = res.group(1).decode('utf8') - assert (1000000 - 10) < int(stopped_count) < (1000000 + 10) + assert (1000000 - 20) < int(stopped_count) < (1000000 + 20) dut.expect_exact('Set count value') dut.expect_exact('Get count value') diff --git a/examples/peripherals/touch_sensor/touch_element/touch_button/main/CMakeLists.txt b/examples/peripherals/touch_sensor/touch_element/touch_button/main/CMakeLists.txt index 01c1423b22..64e4f4dd82 100644 --- a/examples/peripherals/touch_sensor/touch_element/touch_button/main/CMakeLists.txt +++ b/examples/peripherals/touch_sensor/touch_element/touch_button/main/CMakeLists.txt @@ -1,4 +1,3 @@ idf_component_register(SRCS "touch_button_example_main.c" INCLUDE_DIRS "." PRIV_REQUIRES touch_element) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/touch_sensor/touch_element/touch_button/main/touch_button_example_main.c b/examples/peripherals/touch_sensor/touch_element/touch_button/main/touch_button_example_main.c index 031106ab25..1456c08571 100644 --- a/examples/peripherals/touch_sensor/touch_element/touch_button/main/touch_button_example_main.c +++ b/examples/peripherals/touch_sensor/touch_element/touch_button/main/touch_button_example_main.c @@ -66,11 +66,11 @@ static void button_handler_task(void *arg) /* Decode message */ const touch_button_message_t *button_message = touch_button_get_message(&element_message); if (button_message->event == TOUCH_BUTTON_EVT_ON_PRESS) { - ESP_LOGI(TAG, "Button[%d] Press", (uint32_t)element_message.arg); + ESP_LOGI(TAG, "Button[%d] Press", (int)element_message.arg); } else if (button_message->event == TOUCH_BUTTON_EVT_ON_RELEASE) { - ESP_LOGI(TAG, "Button[%d] Release", (uint32_t)element_message.arg); + ESP_LOGI(TAG, "Button[%d] Release", (int)element_message.arg); } else if (button_message->event == TOUCH_BUTTON_EVT_ON_LONGPRESS) { - ESP_LOGI(TAG, "Button[%d] LongPress", (uint32_t)element_message.arg); + ESP_LOGI(TAG, "Button[%d] LongPress", (int)element_message.arg); } } } @@ -80,11 +80,11 @@ static void button_handler(touch_button_handle_t out_handle, touch_button_messag { (void) out_handle; //Unused if (out_message->event == TOUCH_BUTTON_EVT_ON_PRESS) { - ESP_LOGI(TAG, "Button[%d] Press", (uint32_t)arg); + ESP_LOGI(TAG, "Button[%d] Press", (int)arg); } else if (out_message->event == TOUCH_BUTTON_EVT_ON_RELEASE) { - ESP_LOGI(TAG, "Button[%d] Release", (uint32_t)arg); + ESP_LOGI(TAG, "Button[%d] Release", (int)arg); } else if (out_message->event == TOUCH_BUTTON_EVT_ON_LONGPRESS) { - ESP_LOGI(TAG, "Button[%d] LongPress", (uint32_t)arg); + ESP_LOGI(TAG, "Button[%d] LongPress", (int)arg); } } #endif @@ -107,8 +107,9 @@ void app_main(void) /* Create Touch buttons */ ESP_ERROR_CHECK(touch_button_create(&button_config, &button_handle[i])); /* Subscribe touch button events (On Press, On Release, On LongPress) */ - ESP_ERROR_CHECK(touch_button_subscribe_event(button_handle[i], TOUCH_ELEM_EVENT_ON_PRESS | TOUCH_ELEM_EVENT_ON_RELEASE | TOUCH_ELEM_EVENT_ON_LONGPRESS, - (void *)channel_array[i])); + ESP_ERROR_CHECK(touch_button_subscribe_event(button_handle[i], + TOUCH_ELEM_EVENT_ON_PRESS | TOUCH_ELEM_EVENT_ON_RELEASE | TOUCH_ELEM_EVENT_ON_LONGPRESS, + (void *)channel_array[i])); #ifdef CONFIG_TOUCH_ELEM_EVENT /* Set EVENT as the dispatch method */ ESP_ERROR_CHECK(touch_button_set_dispatch_method(button_handle[i], TOUCH_ELEM_DISP_EVENT)); diff --git a/examples/peripherals/touch_sensor/touch_element/touch_element_waterproof/main/CMakeLists.txt b/examples/peripherals/touch_sensor/touch_element/touch_element_waterproof/main/CMakeLists.txt index 80a1673df5..df1acc5837 100644 --- a/examples/peripherals/touch_sensor/touch_element/touch_element_waterproof/main/CMakeLists.txt +++ b/examples/peripherals/touch_sensor/touch_element/touch_element_waterproof/main/CMakeLists.txt @@ -1,4 +1,3 @@ idf_component_register(SRCS "waterproof_example_main.c" INCLUDE_DIRS "." PRIV_REQUIRES touch_element) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/touch_sensor/touch_element/touch_element_waterproof/main/waterproof_example_main.c b/examples/peripherals/touch_sensor/touch_element/touch_element_waterproof/main/waterproof_example_main.c index 427d63cbbb..631670de8d 100644 --- a/examples/peripherals/touch_sensor/touch_element/touch_element_waterproof/main/waterproof_example_main.c +++ b/examples/peripherals/touch_sensor/touch_element/touch_element_waterproof/main/waterproof_example_main.c @@ -36,11 +36,11 @@ static void button_handler_task(void *arg) touch_element_message_receive(&element_message, portMAX_DELAY); //Block take const touch_button_message_t *button_message = touch_button_get_message(&element_message); if (button_message->event == TOUCH_BUTTON_EVT_ON_PRESS) { - ESP_LOGI(TAG, "Button[%d] Press", (uint32_t)element_message.arg); + ESP_LOGI(TAG, "Button[%d] Press", (int)element_message.arg); } else if (button_message->event == TOUCH_BUTTON_EVT_ON_RELEASE) { - ESP_LOGI(TAG, "Button[%d] Release", (uint32_t)element_message.arg); + ESP_LOGI(TAG, "Button[%d] Release", (int)element_message.arg); } else if (button_message->event == TOUCH_BUTTON_EVT_ON_LONGPRESS) { - ESP_LOGI(TAG, "Button[%d] LongPress", (uint32_t)element_message.arg); + ESP_LOGI(TAG, "Button[%d] LongPress", (int)element_message.arg); } } } @@ -74,8 +74,9 @@ void app_main(void) /* Create touch button */ ESP_ERROR_CHECK(touch_button_create(&button_config, &button_handle[i])); /* Subscribe touch button event(Press, Release, LongPress) */ - ESP_ERROR_CHECK(touch_button_subscribe_event(button_handle[i], TOUCH_ELEM_EVENT_ON_PRESS | TOUCH_ELEM_EVENT_ON_RELEASE | TOUCH_ELEM_EVENT_ON_LONGPRESS, - (void *)channel_array[i])); + ESP_ERROR_CHECK(touch_button_subscribe_event(button_handle[i], + TOUCH_ELEM_EVENT_ON_PRESS | TOUCH_ELEM_EVENT_ON_RELEASE | TOUCH_ELEM_EVENT_ON_LONGPRESS, + (void *)channel_array[i])); /* Button set dispatch method */ ESP_ERROR_CHECK(touch_button_set_dispatch_method(button_handle[i], TOUCH_ELEM_DISP_EVENT)); #ifdef CONFIG_TOUCH_WATERPROOF_GUARD_ENABLE diff --git a/examples/peripherals/touch_sensor/touch_element/touch_elements_combination/main/CMakeLists.txt b/examples/peripherals/touch_sensor/touch_element/touch_elements_combination/main/CMakeLists.txt index 4cfd621f1e..a768337bd2 100644 --- a/examples/peripherals/touch_sensor/touch_element/touch_elements_combination/main/CMakeLists.txt +++ b/examples/peripherals/touch_sensor/touch_element/touch_elements_combination/main/CMakeLists.txt @@ -1,4 +1,3 @@ idf_component_register(SRCS "touch_elements_example_main.c" INCLUDE_DIRS "." PRIV_REQUIRES touch_element) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/touch_sensor/touch_element/touch_elements_combination/main/touch_elements_example_main.c b/examples/peripherals/touch_sensor/touch_element/touch_elements_combination/main/touch_elements_example_main.c index 4e529a1a63..7b8396527b 100644 --- a/examples/peripherals/touch_sensor/touch_element/touch_elements_combination/main/touch_elements_example_main.c +++ b/examples/peripherals/touch_sensor/touch_element/touch_elements_combination/main/touch_elements_example_main.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: CC0-1.0 */ +#include #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "touch_element/touch_button.h" @@ -53,11 +54,11 @@ static void button_handler(touch_elem_message_t element_message) { const touch_button_message_t *button_message = touch_button_get_message(&element_message); if (button_message->event == TOUCH_BUTTON_EVT_ON_PRESS) { - ESP_LOGI(TAG, "Button[%d] Press", (uint32_t)element_message.arg); + ESP_LOGI(TAG, "Button[%d] Press", (int)element_message.arg); } else if (button_message->event == TOUCH_BUTTON_EVT_ON_RELEASE) { - ESP_LOGI(TAG, "Button[%d] Release", (uint32_t)element_message.arg); + ESP_LOGI(TAG, "Button[%d] Release", (int)element_message.arg); } else if (button_message->event == TOUCH_BUTTON_EVT_ON_LONGPRESS) { - ESP_LOGI(TAG, "Button[%d] LongPress", (uint32_t)element_message.arg); + ESP_LOGI(TAG, "Button[%d] LongPress", (int)element_message.arg); } } @@ -65,11 +66,11 @@ static void slider_handler(touch_elem_message_t element_message) { const touch_slider_message_t *slider_message = touch_slider_get_message(&element_message); if (slider_message->event == TOUCH_SLIDER_EVT_ON_PRESS) { - ESP_LOGI(TAG, "Slider Press, position: %d", slider_message->position); + ESP_LOGI(TAG, "Slider Press, position: %"PRIu32, slider_message->position); } else if (slider_message->event == TOUCH_SLIDER_EVT_ON_RELEASE) { - ESP_LOGI(TAG, "Slider Release, position: %d", slider_message->position); + ESP_LOGI(TAG, "Slider Release, position: %"PRIu32, slider_message->position); } else if (slider_message->event == TOUCH_SLIDER_EVT_ON_CALCULATION) { - ESP_LOGI(TAG, "Slider Calculate, position: %d", slider_message->position); + ESP_LOGI(TAG, "Slider Calculate, position: %"PRIu32, slider_message->position); } } @@ -107,7 +108,8 @@ void button_example_init(void) /* Create Touch buttons */ ESP_ERROR_CHECK(touch_button_create(&button_config, &button_handle[i])); /* Subscribe touch button events (On Press, On Release, On LongPress) */ - ESP_ERROR_CHECK(touch_button_subscribe_event(button_handle[i], TOUCH_ELEM_EVENT_ON_PRESS | TOUCH_ELEM_EVENT_ON_RELEASE | TOUCH_ELEM_EVENT_ON_LONGPRESS, + ESP_ERROR_CHECK(touch_button_subscribe_event(button_handle[i], + TOUCH_ELEM_EVENT_ON_PRESS | TOUCH_ELEM_EVENT_ON_RELEASE | TOUCH_ELEM_EVENT_ON_LONGPRESS, (void *)button_channel_array[i])); /* Set EVENT as the dispatch method */ ESP_ERROR_CHECK(touch_button_set_dispatch_method(button_handle[i], TOUCH_ELEM_DISP_EVENT)); @@ -131,7 +133,8 @@ void slider_example_init(void) }; ESP_ERROR_CHECK(touch_slider_create(&slider_config, &slider_handle)); /* Subscribe touch slider events (On Press, On Release, On Calculation) */ - ESP_ERROR_CHECK(touch_slider_subscribe_event(slider_handle, TOUCH_ELEM_EVENT_ON_PRESS | TOUCH_ELEM_EVENT_ON_RELEASE | TOUCH_ELEM_EVENT_ON_CALCULATION, NULL)); + ESP_ERROR_CHECK(touch_slider_subscribe_event(slider_handle, + TOUCH_ELEM_EVENT_ON_PRESS | TOUCH_ELEM_EVENT_ON_RELEASE | TOUCH_ELEM_EVENT_ON_CALCULATION, NULL)); /* Set EVENT as the dispatch method */ ESP_ERROR_CHECK(touch_slider_set_dispatch_method(slider_handle, TOUCH_ELEM_DISP_EVENT)); ESP_LOGI(TAG, "Touch slider created"); diff --git a/examples/peripherals/touch_sensor/touch_element/touch_matrix/main/CMakeLists.txt b/examples/peripherals/touch_sensor/touch_element/touch_matrix/main/CMakeLists.txt index 69b1052aeb..ca3814e9f0 100644 --- a/examples/peripherals/touch_sensor/touch_element/touch_matrix/main/CMakeLists.txt +++ b/examples/peripherals/touch_sensor/touch_element/touch_matrix/main/CMakeLists.txt @@ -1,4 +1,3 @@ idf_component_register(SRCS "touch_matrix_example_main.c" INCLUDE_DIRS "." PRIV_REQUIRES touch_element) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/touch_sensor/touch_element/touch_matrix/main/touch_matrix_example_main.c b/examples/peripherals/touch_sensor/touch_element/touch_matrix/main/touch_matrix_example_main.c index 0ba483dc5a..de6c092160 100644 --- a/examples/peripherals/touch_sensor/touch_element/touch_matrix/main/touch_matrix_example_main.c +++ b/examples/peripherals/touch_sensor/touch_element/touch_matrix/main/touch_matrix_example_main.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: CC0-1.0 */ +#include #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "touch_element/touch_matrix.h" @@ -58,11 +59,14 @@ static void matrix_handler_task(void *arg) /* Decode message */ const touch_matrix_message_t *matrix_message = touch_matrix_get_message(&element_message); if (matrix_message->event == TOUCH_MATRIX_EVT_ON_PRESS) { - ESP_LOGI(TAG, "Matrix Press, axis: (%d, %d) index: %d", matrix_message->position.x_axis, matrix_message->position.y_axis, matrix_message->position.index); + ESP_LOGI(TAG, "Matrix Press, axis: (%"PRIu8", %"PRIu8") index: %"PRIu8, matrix_message->position.x_axis, + matrix_message->position.y_axis, matrix_message->position.index); } else if (matrix_message->event == TOUCH_MATRIX_EVT_ON_RELEASE) { - ESP_LOGI(TAG, "Matrix Release, axis: (%d, %d) index: %d", matrix_message->position.x_axis, matrix_message->position.y_axis, matrix_message->position.index); + ESP_LOGI(TAG, "Matrix Release, axis: (%"PRIu8", %"PRIu8") index: %"PRIu8, matrix_message->position.x_axis, + matrix_message->position.y_axis, matrix_message->position.index); } else if (matrix_message->event == TOUCH_MATRIX_EVT_ON_LONGPRESS) { - ESP_LOGI(TAG, "Matrix LongPress, axis: (%d, %d) index: %d", matrix_message->position.x_axis, matrix_message->position.y_axis, matrix_message->position.index); + ESP_LOGI(TAG, "Matrix LongPress, axis: (%"PRIu8", %"PRIu8") index: %"PRIu8, matrix_message->position.x_axis, + matrix_message->position.y_axis, matrix_message->position.index); } } } @@ -75,11 +79,14 @@ void matrix_handler(touch_matrix_handle_t out_handle, touch_matrix_message_t *ou return; } if (out_message->event == TOUCH_MATRIX_EVT_ON_PRESS) { - ESP_LOGI(TAG, "Matrix Press, axis: (%d, %d) index: %d", out_message->position.x_axis, out_message->position.y_axis, out_message->position.index); + ESP_LOGI(TAG, "Matrix Press, axis: (%"PRIu8", %"PRIu8") index: %"PRIu8, out_message->position.x_axis, + out_message->position.y_axis, out_message->position.index); } else if (out_message->event == TOUCH_MATRIX_EVT_ON_RELEASE) { - ESP_LOGI(TAG, "Matrix Release, axis: (%d, %d) index: %d", out_message->position.x_axis, out_message->position.y_axis, out_message->position.index); + ESP_LOGI(TAG, "Matrix Release, axis: (%"PRIu8", %"PRIu8") index: %"PRIu8, out_message->position.x_axis, + out_message->position.y_axis, out_message->position.index); } else if (out_message->event == TOUCH_MATRIX_EVT_ON_LONGPRESS) { - ESP_LOGI(TAG, "Matrix LongPress, axis: (%d, %d) index: %d", out_message->position.x_axis, out_message->position.y_axis, out_message->position.index); + ESP_LOGI(TAG, "Matrix LongPress, axis: (%"PRIu8", %"PRIu8") index: %"PRIu8, out_message->position.x_axis, + out_message->position.y_axis, out_message->position.index); } } #endif @@ -105,7 +112,8 @@ void app_main(void) }; ESP_ERROR_CHECK(touch_matrix_create(&matrix_config, &matrix_handle)); /* Subscribe touch matrix events (On Press, On Release, On LongPress) */ - ESP_ERROR_CHECK(touch_matrix_subscribe_event(matrix_handle, TOUCH_ELEM_EVENT_ON_PRESS | TOUCH_ELEM_EVENT_ON_RELEASE | TOUCH_ELEM_EVENT_ON_LONGPRESS, NULL)); + ESP_ERROR_CHECK(touch_matrix_subscribe_event(matrix_handle, + TOUCH_ELEM_EVENT_ON_PRESS | TOUCH_ELEM_EVENT_ON_RELEASE | TOUCH_ELEM_EVENT_ON_LONGPRESS, NULL)); #ifdef CONFIG_TOUCH_ELEM_EVENT /* Set EVENT as the dispatch method */ ESP_ERROR_CHECK(touch_matrix_set_dispatch_method(matrix_handle, TOUCH_ELEM_DISP_EVENT)); diff --git a/examples/peripherals/touch_sensor/touch_element/touch_slider/main/CMakeLists.txt b/examples/peripherals/touch_sensor/touch_element/touch_slider/main/CMakeLists.txt index 3a69d86adf..8742ecf28c 100644 --- a/examples/peripherals/touch_sensor/touch_element/touch_slider/main/CMakeLists.txt +++ b/examples/peripherals/touch_sensor/touch_element/touch_slider/main/CMakeLists.txt @@ -1,4 +1,3 @@ idf_component_register(SRCS "touch_slider_example_main.c" INCLUDE_DIRS "." PRIV_REQUIRES touch_element) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/touch_sensor/touch_element/touch_slider/main/touch_slider_example_main.c b/examples/peripherals/touch_sensor/touch_element/touch_slider/main/touch_slider_example_main.c index 3ae4eb7f93..4df27f2882 100644 --- a/examples/peripherals/touch_sensor/touch_element/touch_slider/main/touch_slider_example_main.c +++ b/examples/peripherals/touch_sensor/touch_element/touch_slider/main/touch_slider_example_main.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: CC0-1.0 */ +#include #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "touch_element/touch_slider.h" @@ -51,11 +52,11 @@ static void slider_handler_task(void *arg) /* Decode message */ const touch_slider_message_t *slider_message = touch_slider_get_message(&element_message); if (slider_message->event == TOUCH_SLIDER_EVT_ON_PRESS) { - ESP_LOGI(TAG, "Slider Press, position: %d", slider_message->position); + ESP_LOGI(TAG, "Slider Press, position: %"PRIu32, slider_message->position); } else if (slider_message->event == TOUCH_SLIDER_EVT_ON_RELEASE) { - ESP_LOGI(TAG, "Slider Release, position: %d", slider_message->position); + ESP_LOGI(TAG, "Slider Release, position: %"PRIu32, slider_message->position); } else if (slider_message->event == TOUCH_SLIDER_EVT_ON_CALCULATION) { - ESP_LOGI(TAG, "Slider Calculate, position: %d", slider_message->position); + ESP_LOGI(TAG, "Slider Calculate, position: %"PRIu32, slider_message->position); } } } @@ -69,11 +70,11 @@ void slider_handler(touch_slider_handle_t out_handle, touch_slider_message_t *ou return; } if (out_message->event == TOUCH_SLIDER_EVT_ON_PRESS) { - ESP_LOGI(TAG, "Slider Press, position: %d", out_message->position); + ESP_LOGI(TAG, "Slider Press, position: %"PRIu32, out_message->position); } else if (out_message->event == TOUCH_SLIDER_EVT_ON_RELEASE) { - ESP_LOGI(TAG, "Slider Release, position: %d", out_message->position); + ESP_LOGI(TAG, "Slider Release, position: %"PRIu32, out_message->position); } else if (out_message->event == TOUCH_SLIDER_EVT_ON_CALCULATION) { - ESP_LOGI(TAG, "Slider Calculate, position: %d", out_message->position); + ESP_LOGI(TAG, "Slider Calculate, position: %"PRIu32, out_message->position); } } #endif @@ -97,7 +98,8 @@ void app_main(void) }; ESP_ERROR_CHECK(touch_slider_create(&slider_config, &slider_handle)); /* Subscribe touch slider events (On Press, On Release, On Calculation) */ - ESP_ERROR_CHECK(touch_slider_subscribe_event(slider_handle, TOUCH_ELEM_EVENT_ON_PRESS | TOUCH_ELEM_EVENT_ON_RELEASE | TOUCH_ELEM_EVENT_ON_CALCULATION, NULL)); + ESP_ERROR_CHECK(touch_slider_subscribe_event(slider_handle, + TOUCH_ELEM_EVENT_ON_PRESS | TOUCH_ELEM_EVENT_ON_RELEASE | TOUCH_ELEM_EVENT_ON_CALCULATION, NULL)); #ifdef CONFIG_TOUCH_ELEM_EVENT /* Set EVENT as the dispatch method */ ESP_ERROR_CHECK(touch_slider_set_dispatch_method(slider_handle, TOUCH_ELEM_DISP_EVENT)); diff --git a/examples/peripherals/touch_sensor/touch_sensor_v1/touch_pad_interrupt/main/CMakeLists.txt b/examples/peripherals/touch_sensor/touch_sensor_v1/touch_pad_interrupt/main/CMakeLists.txt index 43bd93bcf4..94fac9872e 100644 --- a/examples/peripherals/touch_sensor/touch_sensor_v1/touch_pad_interrupt/main/CMakeLists.txt +++ b/examples/peripherals/touch_sensor/touch_sensor_v1/touch_pad_interrupt/main/CMakeLists.txt @@ -1,3 +1,2 @@ idf_component_register(SRCS "tp_interrupt_main.c" INCLUDE_DIRS ".") -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/touch_sensor/touch_sensor_v1/touch_pad_interrupt/main/tp_interrupt_main.c b/examples/peripherals/touch_sensor/touch_sensor_v1/touch_pad_interrupt/main/tp_interrupt_main.c index 22fb8f4515..58e3da4f9d 100644 --- a/examples/peripherals/touch_sensor/touch_sensor_v1/touch_pad_interrupt/main/tp_interrupt_main.c +++ b/examples/peripherals/touch_sensor/touch_sensor_v1/touch_pad_interrupt/main/tp_interrupt_main.c @@ -5,6 +5,7 @@ */ #include +#include #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/queue.h" @@ -93,7 +94,7 @@ static void tp_example_read_task(void *pvParameter) touch_pad_read_filtered(i, &value); if (value < s_pad_init_val[i] * TOUCH_THRESH_PERCENT / 100) { ESP_LOGI(TAG, "T%d activated!", i); - ESP_LOGI(TAG, "value: %d; init val: %d", value, s_pad_init_val[i]); + ESP_LOGI(TAG, "value: %"PRIu16"; init val: %"PRIu32, value, s_pad_init_val[i]); vTaskDelay(200 / portTICK_PERIOD_MS); // Reset the counter to stop changing mode. change_mode = 1; diff --git a/examples/peripherals/touch_sensor/touch_sensor_v1/touch_pad_read/main/CMakeLists.txt b/examples/peripherals/touch_sensor/touch_sensor_v1/touch_pad_read/main/CMakeLists.txt index 9454ca3650..2b9a209ec4 100644 --- a/examples/peripherals/touch_sensor/touch_sensor_v1/touch_pad_read/main/CMakeLists.txt +++ b/examples/peripherals/touch_sensor/touch_sensor_v1/touch_pad_read/main/CMakeLists.txt @@ -1,3 +1,2 @@ idf_component_register(SRCS "tp_read_main.c" INCLUDE_DIRS ".") -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/touch_sensor/touch_sensor_v1/touch_pad_read/main/tp_read_main.c b/examples/peripherals/touch_sensor/touch_sensor_v1/touch_pad_read/main/tp_read_main.c index b605621072..59ba5955e3 100644 --- a/examples/peripherals/touch_sensor/touch_sensor_v1/touch_pad_read/main/tp_read_main.c +++ b/examples/peripherals/touch_sensor/touch_sensor_v1/touch_pad_read/main/tp_read_main.c @@ -5,6 +5,7 @@ */ #include +#include #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "driver/touch_pad.h" @@ -33,10 +34,10 @@ static void tp_example_read_task(void *pvParameter) // If open the filter mode, please use this API to get the touch pad count. touch_pad_read_raw_data(i, &touch_value); touch_pad_read_filtered(i, &touch_filter_value); - printf("T%d:[%4d,%4d] ", i, touch_value, touch_filter_value); + printf("T%d:[%4"PRIu16",%4"PRIu16"] ", i, touch_value, touch_filter_value); #else touch_pad_read(i, &touch_value); - printf("T%d:[%4d] ", i, touch_value); + printf("T%d:[%4"PRIu16"] ", i, touch_value); #endif } printf("\n"); diff --git a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/main/CMakeLists.txt b/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/main/CMakeLists.txt index 43bd93bcf4..94fac9872e 100644 --- a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/main/CMakeLists.txt +++ b/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/main/CMakeLists.txt @@ -1,3 +1,2 @@ idf_component_register(SRCS "tp_interrupt_main.c" INCLUDE_DIRS ".") -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/main/tp_interrupt_main.c b/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/main/tp_interrupt_main.c index 1285558143..a852a069e0 100644 --- a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/main/tp_interrupt_main.c +++ b/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/main/tp_interrupt_main.c @@ -5,6 +5,7 @@ */ #include +#include #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/queue.h" @@ -76,7 +77,7 @@ static void tp_example_set_thresholds(void) touch_pad_read_benchmark(button[i], &touch_value); //set interrupt threshold. touch_pad_set_thresh(button[i], touch_value * button_threshold[i]); - ESP_LOGI(TAG, "touch pad [%d] base %d, thresh %d", \ + ESP_LOGI(TAG, "touch pad [%d] base %"PRIu32", thresh %"PRIu32, \ button[i], touch_value, (uint32_t)(touch_value * button_threshold[i])); } } @@ -113,10 +114,10 @@ static void tp_example_read_task(void *pvParameter) /* if guard pad be touched, other pads no response. */ if (evt.pad_num == button[3]) { guard_mode_flag = 1; - ESP_LOGW(TAG, "TouchSensor [%d] be activated, enter guard mode", evt.pad_num); + ESP_LOGW(TAG, "TouchSensor [%"PRIu32"] be activated, enter guard mode", evt.pad_num); } else { if (guard_mode_flag == 0) { - ESP_LOGI(TAG, "TouchSensor [%d] be activated, status mask 0x%x", evt.pad_num, evt.pad_status); + ESP_LOGI(TAG, "TouchSensor [%"PRIu32"] be activated, status mask 0x%"PRIu32"", evt.pad_num, evt.pad_status); } else { ESP_LOGW(TAG, "In guard mode. No response"); } @@ -126,19 +127,19 @@ static void tp_example_read_task(void *pvParameter) /* if guard pad be touched, other pads no response. */ if (evt.pad_num == button[3]) { guard_mode_flag = 0; - ESP_LOGW(TAG, "TouchSensor [%d] be inactivated, exit guard mode", evt.pad_num); + ESP_LOGW(TAG, "TouchSensor [%"PRIu32"] be inactivated, exit guard mode", evt.pad_num); } else { if (guard_mode_flag == 0) { - ESP_LOGI(TAG, "TouchSensor [%d] be inactivated, status mask 0x%x", evt.pad_num, evt.pad_status); + ESP_LOGI(TAG, "TouchSensor [%"PRIu32"] be inactivated, status mask 0x%"PRIu32, evt.pad_num, evt.pad_status); } } } if (evt.intr_mask & TOUCH_PAD_INTR_MASK_SCAN_DONE) { - ESP_LOGI(TAG, "The touch sensor group measurement is done [%d].", evt.pad_num); + ESP_LOGI(TAG, "The touch sensor group measurement is done [%"PRIu32"].", evt.pad_num); } if (evt.intr_mask & TOUCH_PAD_INTR_MASK_TIMEOUT) { /* Add your exception handling in here. */ - ESP_LOGI(TAG, "Touch sensor channel %d measure timeout. Skip this exception channel!!", evt.pad_num); + ESP_LOGI(TAG, "Touch sensor channel %"PRIu32" measure timeout. Skip this exception channel!!", evt.pad_num); touch_pad_timeout_resume(); // Point on the next channel to measure. } } diff --git a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_read/main/CMakeLists.txt b/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_read/main/CMakeLists.txt index 9454ca3650..2b9a209ec4 100644 --- a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_read/main/CMakeLists.txt +++ b/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_read/main/CMakeLists.txt @@ -1,3 +1,2 @@ idf_component_register(SRCS "tp_read_main.c" INCLUDE_DIRS ".") -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_read/main/tp_read_main.c b/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_read/main/tp_read_main.c index 83d5eee05e..c082d9e6b3 100644 --- a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_read/main/tp_read_main.c +++ b/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_read/main/tp_read_main.c @@ -5,6 +5,7 @@ */ #include +#include #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "driver/touch_pad.h" @@ -46,7 +47,7 @@ static void tp_example_read_task(void *pvParameter) while (1) { for (int i = 0; i < TOUCH_BUTTON_NUM; i++) { touch_pad_read_raw_data(button[i], &touch_value); // read raw data. - printf("T%d: [%4d] ", button[i], touch_value); + printf("T%d: [%4"PRIu32"] ", button[i], touch_value); } printf("\n"); vTaskDelay(200 / portTICK_PERIOD_MS); diff --git a/examples/peripherals/twai/twai_network/twai_network_listen_only/main/CMakeLists.txt b/examples/peripherals/twai/twai_network/twai_network_listen_only/main/CMakeLists.txt index 0075b952ca..e26450a577 100644 --- a/examples/peripherals/twai/twai_network/twai_network_listen_only/main/CMakeLists.txt +++ b/examples/peripherals/twai/twai_network/twai_network_listen_only/main/CMakeLists.txt @@ -1,3 +1,2 @@ idf_component_register(SRCS "twai_network_example_listen_only_main.c" INCLUDE_DIRS ".") -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/twai/twai_network/twai_network_listen_only/main/twai_network_example_listen_only_main.c b/examples/peripherals/twai/twai_network/twai_network_listen_only/main/twai_network_example_listen_only_main.c index 53474c14d6..0f6b3b7bab 100644 --- a/examples/peripherals/twai/twai_network/twai_network_listen_only/main/twai_network_example_listen_only_main.c +++ b/examples/peripherals/twai/twai_network/twai_network_listen_only/main/twai_network_example_listen_only_main.c @@ -78,7 +78,7 @@ static void twai_receive_task(void *arg) for (int i = 0; i < rx_msg.data_length_code; i++) { data |= (rx_msg.data[i] << (i * 8)); } - ESP_LOGI(EXAMPLE_TAG, "Received data value %d", data); + ESP_LOGI(EXAMPLE_TAG, "Received data value %"PRIu32, data); } else if (rx_msg.identifier == ID_MASTER_STOP_CMD) { ESP_LOGI(EXAMPLE_TAG, "Received master stop command"); } else if (rx_msg.identifier == ID_SLAVE_STOP_RESP) { diff --git a/examples/peripherals/twai/twai_network/twai_network_master/main/CMakeLists.txt b/examples/peripherals/twai/twai_network/twai_network_master/main/CMakeLists.txt index 06a6d3828a..112b3ca1b4 100644 --- a/examples/peripherals/twai/twai_network/twai_network_master/main/CMakeLists.txt +++ b/examples/peripherals/twai/twai_network/twai_network_master/main/CMakeLists.txt @@ -1,3 +1,2 @@ idf_component_register(SRCS "twai_network_example_master_main.c" INCLUDE_DIRS ".") -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/twai/twai_network/twai_network_master/main/twai_network_example_master_main.c b/examples/peripherals/twai/twai_network/twai_network_master/main/twai_network_example_master_main.c index 6392480630..e1a7007435 100644 --- a/examples/peripherals/twai/twai_network/twai_network_master/main/twai_network_example_master_main.c +++ b/examples/peripherals/twai/twai_network/twai_network_master/main/twai_network_example_master_main.c @@ -109,7 +109,7 @@ static void twai_receive_task(void *arg) for (int i = 0; i < rx_msg.data_length_code; i++) { data |= (rx_msg.data[i] << (i * 8)); } - ESP_LOGI(EXAMPLE_TAG, "Received data value %d", data); + ESP_LOGI(EXAMPLE_TAG, "Received data value %"PRIu32, data); data_msgs_rec ++; } } diff --git a/examples/peripherals/twai/twai_network/twai_network_slave/main/CMakeLists.txt b/examples/peripherals/twai/twai_network/twai_network_slave/main/CMakeLists.txt index 7e8c1cd4ec..84241dd1d3 100644 --- a/examples/peripherals/twai/twai_network/twai_network_slave/main/CMakeLists.txt +++ b/examples/peripherals/twai/twai_network/twai_network_slave/main/CMakeLists.txt @@ -1,3 +1,2 @@ idf_component_register(SRCS "twai_network_example_slave_main.c" INCLUDE_DIRS ".") -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/peripherals/twai/twai_network/twai_network_slave/main/twai_network_example_slave_main.c b/examples/peripherals/twai/twai_network/twai_network_slave/main/twai_network_example_slave_main.c index 1a5785cdaa..836ee61291 100644 --- a/examples/peripherals/twai/twai_network/twai_network_slave/main/twai_network_example_slave_main.c +++ b/examples/peripherals/twai/twai_network/twai_network_slave/main/twai_network_example_slave_main.c @@ -146,7 +146,7 @@ static void twai_transmit_task(void *arg) data_message.data[i] = (sensor_data >> (i * 8)) & 0xFF; } twai_transmit(&data_message, portMAX_DELAY); - ESP_LOGI(EXAMPLE_TAG, "Transmitted data value %d", sensor_data); + ESP_LOGI(EXAMPLE_TAG, "Transmitted data value %"PRIu32, sensor_data); vTaskDelay(pdMS_TO_TICKS(DATA_PERIOD_MS)); if (xSemaphoreTake(stop_data_sem, 0) == pdTRUE) { break; diff --git a/examples/peripherals/uart/uart_echo_rs485/README.md b/examples/peripherals/uart/uart_echo_rs485/README.md index 887ca2ede4..a2203062c7 100644 --- a/examples/peripherals/uart/uart_echo_rs485/README.md +++ b/examples/peripherals/uart/uart_echo_rs485/README.md @@ -13,7 +13,7 @@ The approach demonstrated in this example can be used in user application to tra ### Hardware Required PC + USB Serial adapter connected to USB port + RS485 line drivers + Espressif development board. -The MAX485 line driver is used for example below but other similar chips can be used as well. +The MAX483 line driver is used for example below but other similar chips can be used as well. #### RS485 example connection circuit schematic: ``` @@ -22,7 +22,7 @@ The MAX485 line driver is used for example below but other similar chips can be +-------x-------+ +-------x-------+ RXD <------| RO | | RO|-----> RXD | B|---------------|B | - TXD ------>| DI MAX485 | \ / | MAX485 DI|<----- TXD + TXD ------>| DI MAX483 | \ / | MAX483 DI|<----- TXD ESP32 BOARD | | RS-485 side | | SERIAL ADAPTER SIDE RTS --+--->| DE | / \ | DE|---+ | | A|---------------|A | | diff --git a/examples/peripherals/uart/uart_events/main/uart_events_example_main.c b/examples/peripherals/uart/uart_events/main/uart_events_example_main.c index c4f12db2fa..dcf2614b14 100644 --- a/examples/peripherals/uart/uart_events/main/uart_events_example_main.c +++ b/examples/peripherals/uart/uart_events/main/uart_events_example_main.c @@ -69,7 +69,7 @@ static void uart_event_task(void *pvParameters) //Event of UART ring buffer full case UART_BUFFER_FULL: ESP_LOGI(TAG, "ring buffer full"); - // If buffer full happened, you should consider encreasing your buffer size + // If buffer full happened, you should consider increasing your buffer size // As an example, we directly flush the rx buffer here in order to read more data. uart_flush_input(EX_UART_NUM); xQueueReset(uart0_queue); diff --git a/examples/peripherals/usb/device/.build-test-rules.yml b/examples/peripherals/usb/device/.build-test-rules.yml new file mode 100644 index 0000000000..2e88c76571 --- /dev/null +++ b/examples/peripherals/usb/device/.build-test-rules.yml @@ -0,0 +1,9 @@ +# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps + +examples/peripherals/usb/device: + enable: + - if: SOC_USB_OTG_SUPPORTED == 1 + disable_test: + - if: IDF_TARGET == "esp32s3" + temporary: true + reason: lack of runners diff --git a/examples/peripherals/usb/device/tusb_console/pytest_usb_device_console.py b/examples/peripherals/usb/device/tusb_console/pytest_usb_device_console.py new file mode 100644 index 0000000000..0cd523dad9 --- /dev/null +++ b/examples/peripherals/usb/device/tusb_console/pytest_usb_device_console.py @@ -0,0 +1,35 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 +from time import sleep + +import pytest +from pytest_embedded import Dut +from serial import Serial +from serial.tools.list_ports import comports + + +@pytest.mark.esp32s2 +@pytest.mark.usb_device +def test_usb_device_console_example(dut: Dut) -> None: + dut.expect_exact('USB initialization DONE') + dut.expect_exact('example: log -> UART') + dut.expect_exact('example: print -> stdout') + dut.expect_exact('example: print -> stderr') + + # Find device with Espressif TinyUSB VID/PID + sleep(2) # Some time for the OS to enumerate our USB device + ports = comports() + for port, _, hwid in ports: + if '303A:4001' in hwid: + with Serial(port) as s: + # Assert TinyUSB output: Read 3 lines and check their content + serial_output = list() + serial_output.append(s.readline()) + serial_output.append(s.readline()) + serial_output.append(s.readline()) + assert any(b'example: log -> USB' in out for out in serial_output) + assert any(b'example: print -> stdout' in out for out in serial_output) + assert any(b'example: print -> stderr' in out for out in serial_output) + return + + raise Exception('TinyUSB COM port not found') diff --git a/examples/peripherals/usb/device/tusb_hid/pytest_usb_device_hid.py b/examples/peripherals/usb/device/tusb_hid/pytest_usb_device_hid.py new file mode 100644 index 0000000000..f38b3a7415 --- /dev/null +++ b/examples/peripherals/usb/device/tusb_hid/pytest_usb_device_hid.py @@ -0,0 +1,12 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 +import pytest +from pytest_embedded import Dut + + +@pytest.mark.esp32s2 +@pytest.mark.usb_device +def test_usb_device_hid_example(dut: Dut) -> None: + dut.expect_exact('USB initialization DONE') + dut.expect_exact('Sending Keyboard report') + dut.expect_exact('Sending Mouse report') diff --git a/examples/peripherals/usb/device/tusb_midi/main/tusb_midi_main.c b/examples/peripherals/usb/device/tusb_midi/main/tusb_midi_main.c index 231393e5ef..c6dccf8392 100644 --- a/examples/peripherals/usb/device/tusb_midi/main/tusb_midi_main.c +++ b/examples/peripherals/usb/device/tusb_midi/main/tusb_midi_main.c @@ -57,6 +57,7 @@ static void periodic_midi_write_example_cb(void *arg) } // Send Note On for current position at full velocity (127) on channel 1. + ESP_LOGI(TAG, "Writing MIDI data %d", note_sequence[note_pos]); uint8_t note_on[3] = {0x90 | channel, note_sequence[note_pos], 127}; tud_midi_stream_write(cable_num, note_on, 3); diff --git a/examples/peripherals/usb/device/tusb_midi/pytest_usb_device_midi.py b/examples/peripherals/usb/device/tusb_midi/pytest_usb_device_midi.py new file mode 100644 index 0000000000..b0b55a1f28 --- /dev/null +++ b/examples/peripherals/usb/device/tusb_midi/pytest_usb_device_midi.py @@ -0,0 +1,13 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 +import pytest +from pytest_embedded import Dut + + +@pytest.mark.esp32s2 +@pytest.mark.usb_device +def test_usb_device_midi_example(dut: Dut) -> None: + dut.expect_exact('USB initialization DONE') + dut.expect_exact('MIDI write task init') + dut.expect_exact('MIDI read task init') + dut.expect_exact('Writing MIDI data 74') diff --git a/examples/peripherals/usb/device/tusb_sample_descriptor/README.md b/examples/peripherals/usb/device/tusb_sample_descriptor/README.md deleted file mode 100644 index 2f0f8cb6aa..0000000000 --- a/examples/peripherals/usb/device/tusb_sample_descriptor/README.md +++ /dev/null @@ -1,123 +0,0 @@ -| Supported Targets | ESP32-S2 | ESP32-S3 | -| ----------------- | -------- | -------- | - -# TinyUSB Sample Descriptor - -(See the README.md file in the upper level 'examples' directory for more information about examples.) - -This example is demonstrating how to set up ESP chip to work as a Generic USB Device with a user-defined descriptor. You can specify a manufacturer, device's name, ID and other USB-devices parameters responsible for identification by host. - -As a USB stack, a TinyUSB component is used. - -## How to use example - -### Hardware Required - -Any ESP boards that have USB-OTG supported. - -#### Pin Assignment - -See common pin assignments for USB Device examples from [upper level](../../README.md#common-pin-assignments). - -### Configure the project - -There are two ways to set up a descriptor - using Menuconfig tool and in-code - -#### In-code setting up - -For the manual descriptor configuration use the default example's settings and modify `my_descriptor` in [source code](main/tusb_sample_descriptor_main.c) according to your needs - -#### Menuconfig - -If you want to set up the descriptor using Menuconfig UI: - -1. Execute in the terminal from the example's directory: `idf.py menuconfig` - -2. Turn off `Set up a USB descriptor manually in code` parameter at `Example Configuration` - -3. Follow `Component config -> TinyUSB -> Descriptor configuration` for all available configurations. - -### Build and Flash - -Build the project and flash it to the board, then run monitor tool to view serial output: - -```bash -idf.py -p PORT flash monitor -``` - -(Replace PORT with the name of the serial port to use.) - -(To exit the serial monitor, type ``Ctrl-]``.) - -See the Getting Started Guide for full steps to configure and use ESP-IDF to build projects. - -## Example Output - -After the flashing you should see the output: - -``` -I (287) example: USB initialization -I (287) tusb_desc: -┌─────────────────────────────────┠-│ USB Device Descriptor Summary │ -├───────────────────┬─────────────┤ -│bDeviceClass │ 0 │ -├───────────────────┼─────────────┤ -│bDeviceSubClass │ 0 │ -├───────────────────┼─────────────┤ -│bDeviceProtocol │ 0 │ -├───────────────────┼─────────────┤ -│bMaxPacketSize0 │ 64 │ -├───────────────────┼─────────────┤ -│idVendor │ 0x303a │ -├───────────────────┼─────────────┤ -│idProduct │ 0x3000 │ -├───────────────────┼─────────────┤ -│bcdDevice │ 0x101 │ -├───────────────────┼─────────────┤ -│iManufacturer │ 0x1 │ -├───────────────────┼─────────────┤ -│iProduct │ 0x2 │ -├───────────────────┼─────────────┤ -│iSerialNumber │ 0x3 │ -├───────────────────┼─────────────┤ -│bNumConfigurations │ 0x1 │ -└───────────────────┴─────────────┘ -I (457) TinyUSB: TinyUSB Driver installed -I (467) example: USB initialization DONE -``` - -From PC, running `lsusb -v`, you should find the device's descriptor like: -``` -Bus 001 Device 007: ID 303a:3000 I My Custom Device -Device Descriptor: - bLength 18 - bDescriptorType 1 - bcdUSB 2.00 - bDeviceClass 0 - bDeviceSubClass 0 - bDeviceProtocol 0 - bMaxPacketSize0 64 - idVendor 0x303a - idProduct 0x3000 - bcdDevice 1.01 - iManufacturer 1 I - iProduct 2 My Custom Device - iSerial 3 012-345 - bNumConfigurations 1 - Configuration Descriptor: - bLength 9 - bDescriptorType 2 - wTotalLength 0x0009 - bNumInterfaces 0 - bConfigurationValue 1 - iConfiguration 0 - bmAttributes 0xa0 - (Bus Powered) - Remote Wakeup - MaxPower 100mA -can't get device qualifier: Resource temporarily unavailable -can't get debug descriptor: Resource temporarily unavailable -Device Status: 0x0000 - (Bus Powered) -``` diff --git a/examples/peripherals/usb/device/tusb_sample_descriptor/main/CMakeLists.txt b/examples/peripherals/usb/device/tusb_sample_descriptor/main/CMakeLists.txt deleted file mode 100644 index 6581258cb9..0000000000 --- a/examples/peripherals/usb/device/tusb_sample_descriptor/main/CMakeLists.txt +++ /dev/null @@ -1,2 +0,0 @@ -idf_component_register(SRCS "tusb_sample_descriptor_main.c" - INCLUDE_DIRS .) diff --git a/examples/peripherals/usb/device/tusb_sample_descriptor/main/Kconfig.projbuild b/examples/peripherals/usb/device/tusb_sample_descriptor/main/Kconfig.projbuild deleted file mode 100644 index 49a79fe590..0000000000 --- a/examples/peripherals/usb/device/tusb_sample_descriptor/main/Kconfig.projbuild +++ /dev/null @@ -1,10 +0,0 @@ -menu "Example Configuration" - - config EXAMPLE_MANUAL_DESC - bool "Set up a USB descriptor manually in code" - default y - help - You can set up a descriptor using Menuconfig or independently of - your project configuration - manually in code - -endmenu diff --git a/examples/peripherals/usb/device/tusb_sample_descriptor/main/tusb_sample_descriptor_main.c b/examples/peripherals/usb/device/tusb_sample_descriptor/main/tusb_sample_descriptor_main.c deleted file mode 100644 index 9bae30a4ff..0000000000 --- a/examples/peripherals/usb/device/tusb_sample_descriptor/main/tusb_sample_descriptor_main.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Unlicense OR CC0-1.0 - */ - -#include -#include "esp_log.h" -#include "driver/gpio.h" -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "tinyusb.h" -#include "sdkconfig.h" - -static const char *TAG = "example"; - -void app_main(void) -{ - ESP_LOGI(TAG, "USB initialization"); - -#if CONFIG_EXAMPLE_MANUAL_DESC - // Setting of descriptor. You can use descriptor_tinyusb and - // descriptor_str_tinyusb as a reference - tusb_desc_device_t my_descriptor = { - .bLength = sizeof(my_descriptor), - .bDescriptorType = TUSB_DESC_DEVICE, - .bcdUSB = 0x0200, // USB version. 0x0200 means version 2.0 - .bDeviceClass = TUSB_CLASS_UNSPECIFIED, - .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, - - .idVendor = 0x303A, - .idProduct = 0x3000, - .bcdDevice = 0x0101, // Device FW version - - .iManufacturer = 0x01, // see string_descriptor[1] bellow - .iProduct = 0x02, // see string_descriptor[2] bellow - .iSerialNumber = 0x03, // see string_descriptor[3] bellow - - .bNumConfigurations = 0x01 - }; - - tusb_desc_strarray_device_t my_string_descriptor = { - // array of pointer to string descriptors - (char[]){0x09, 0x04}, // 0: is supported language is English (0x0409) - "I", // 1: Manufacturer - "My Custom Device", // 2: Product - "012-345", // 3: Serials, should use chip ID - }; - - const tinyusb_config_t tusb_cfg = { - .descriptor = &my_descriptor, - .string_descriptor = my_string_descriptor, - .external_phy = false, - .configuration_descriptor = NULL, - }; - -#else - - const tinyusb_config_t tusb_cfg = { - .device_descriptor = NULL, - .string_descriptor = NULL, - .external_phy = false, - .configuration_descriptor = NULL, - }; - -#endif - - ESP_ERROR_CHECK(tinyusb_driver_install(&tusb_cfg)); - ESP_LOGI(TAG, "USB initialization DONE"); -} diff --git a/examples/peripherals/usb/device/tusb_sample_descriptor/sdkconfig.defaults b/examples/peripherals/usb/device/tusb_sample_descriptor/sdkconfig.defaults deleted file mode 100644 index 9e66e7cc08..0000000000 --- a/examples/peripherals/usb/device/tusb_sample_descriptor/sdkconfig.defaults +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_TINYUSB=y -CONFIG_TINYUSB_DESC_USE_ESPRESSIF_VID=n -CONFIG_TINYUSB_DESC_CUSTOM_VID=0x303A -CONFIG_TINYUSB_DESC_USE_DEFAULT_PID=n -CONFIG_TINYUSB_DESC_CUSTOM_PID=0x3000 diff --git a/examples/peripherals/usb/device/tusb_serial_device/pytest_usb_device_serial.py b/examples/peripherals/usb/device/tusb_serial_device/pytest_usb_device_serial.py new file mode 100644 index 0000000000..bcf6c90203 --- /dev/null +++ b/examples/peripherals/usb/device/tusb_serial_device/pytest_usb_device_serial.py @@ -0,0 +1,29 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 +from time import sleep + +import pytest +from pytest_embedded import Dut +from serial import Serial +from serial.tools.list_ports import comports + + +@pytest.mark.esp32s2 +@pytest.mark.usb_device +def test_usb_device_serial_example(dut: Dut) -> None: + dut.expect_exact('USB initialization DONE') + sleep(2) # Some time for the OS to enumerate our USB device + + # Find device with Espressif TinyUSB VID/PID + ports = comports() + for port, _, hwid in ports: + if '303A:4001' in hwid: + with Serial(port) as s: + s.write('text\r\n'.encode()) # Write dummy text to COM port + dut.expect_exact('Data from channel 0:') # Check ESP log + dut.expect_exact('|text..|') + res = s.readline() # Check COM echo + assert b'text\r\n' in res + return + + raise Exception('TinyUSB COM port not found') diff --git a/examples/peripherals/usb/device/tusb_serial_device/sdkconfig.ci b/examples/peripherals/usb/device/tusb_serial_device/sdkconfig.ci new file mode 100644 index 0000000000..e69de29bb2 diff --git a/examples/peripherals/usb/host/cdc/cdc_acm_bg96/CMakeLists.txt b/examples/peripherals/usb/host/cdc/cdc_acm_bg96/CMakeLists.txt index 0955a50e2a..726b664235 100644 --- a/examples/peripherals/usb/host/cdc/cdc_acm_bg96/CMakeLists.txt +++ b/examples/peripherals/usb/host/cdc/cdc_acm_bg96/CMakeLists.txt @@ -4,6 +4,5 @@ # CMakeLists in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.16) -set(EXTRA_COMPONENT_DIRS $ENV{IDF_PATH}/examples/peripherals/usb/host/cdc/common) include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(cdc_acm_host_bg96) diff --git a/examples/peripherals/usb/host/cdc/cdc_acm_bg96/main/idf_component.yml b/examples/peripherals/usb/host/cdc/cdc_acm_bg96/main/idf_component.yml index 7f91e1ab78..0455cf6acb 100644 --- a/examples/peripherals/usb/host/cdc/cdc_acm_bg96/main/idf_component.yml +++ b/examples/peripherals/usb/host/cdc/cdc_acm_bg96/main/idf_component.yml @@ -1,3 +1,5 @@ +## IDF Component Manager Manifest File dependencies: idf: ">=4.4" igrr/libnmea: "^0.1.1" + usb_host_cdc_acm: "1.*" diff --git a/examples/peripherals/usb/host/cdc/cdc_acm_host/CMakeLists.txt b/examples/peripherals/usb/host/cdc/cdc_acm_host/CMakeLists.txt index eeca393d0c..067259a1fb 100644 --- a/examples/peripherals/usb/host/cdc/cdc_acm_host/CMakeLists.txt +++ b/examples/peripherals/usb/host/cdc/cdc_acm_host/CMakeLists.txt @@ -4,6 +4,5 @@ # CMakeLists in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.16) -set(EXTRA_COMPONENT_DIRS $ENV{IDF_PATH}/examples/peripherals/usb/host/cdc/common) include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(cdc_acm_host) diff --git a/examples/peripherals/usb/host/cdc/cdc_acm_host/main/idf_component.yml b/examples/peripherals/usb/host/cdc/cdc_acm_host/main/idf_component.yml new file mode 100644 index 0000000000..96533b1fbc --- /dev/null +++ b/examples/peripherals/usb/host/cdc/cdc_acm_host/main/idf_component.yml @@ -0,0 +1,4 @@ +## IDF Component Manager Manifest File +dependencies: + usb_host_cdc_acm: "1.*" + idf: ">=4.4" diff --git a/examples/peripherals/usb/host/cdc/cdc_acm_vcp/CMakeLists.txt b/examples/peripherals/usb/host/cdc/cdc_acm_vcp/CMakeLists.txt index 18a0d1a6dd..daa5b7c53c 100644 --- a/examples/peripherals/usb/host/cdc/cdc_acm_vcp/CMakeLists.txt +++ b/examples/peripherals/usb/host/cdc/cdc_acm_vcp/CMakeLists.txt @@ -4,6 +4,5 @@ # CMakeLists in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.16) -set(EXTRA_COMPONENT_DIRS $ENV{IDF_PATH}/examples/peripherals/usb/host/cdc/common) include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(cdc_acm_vcp) diff --git a/examples/peripherals/usb/host/cdc/cdc_acm_vcp/main/idf_component.yml b/examples/peripherals/usb/host/cdc/cdc_acm_vcp/main/idf_component.yml new file mode 100644 index 0000000000..96533b1fbc --- /dev/null +++ b/examples/peripherals/usb/host/cdc/cdc_acm_vcp/main/idf_component.yml @@ -0,0 +1,4 @@ +## IDF Component Manager Manifest File +dependencies: + usb_host_cdc_acm: "1.*" + idf: ">=4.4" diff --git a/examples/peripherals/usb/host/cdc/common/cdc_acm_host/CMakeLists.txt b/examples/peripherals/usb/host/cdc/common/cdc_acm_host/CMakeLists.txt deleted file mode 100644 index 17093480c9..0000000000 --- a/examples/peripherals/usb/host/cdc/common/cdc_acm_host/CMakeLists.txt +++ /dev/null @@ -1,18 +0,0 @@ -set(srcs) -set(include) -# As CONFIG_USB_OTG_SUPPORTED comes from Kconfig, it is not evaluated yet -# when components are being registered. -set(require usb) - -if(CONFIG_USB_OTG_SUPPORTED) - list(APPEND srcs "cdc_acm_host.c") - list(APPEND include "include") -endif() - -idf_component_register(SRCS ${srcs} - INCLUDE_DIRS ${include} - REQUIRES ${require} - ) -if(CONFIG_USB_OTG_SUPPORTED) - target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") -endif() diff --git a/examples/peripherals/usb/host/cdc/common/cdc_acm_host/README.md b/examples/peripherals/usb/host/cdc/common/cdc_acm_host/README.md deleted file mode 100644 index aeb28b107f..0000000000 --- a/examples/peripherals/usb/host/cdc/common/cdc_acm_host/README.md +++ /dev/null @@ -1,46 +0,0 @@ -# USB Host CDC-ACM Class Driver - -This directory contains an implementation of a USB CDC-ACM Host Class Driver that is implemented on top of the [USB Host Library](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-reference/peripherals/usb_host.html). - -## Supported Devices - -The CDC-ACM Host driver supports the following types of CDC devices: - -1. CDC-ACM devices -2. CDC-like vendor specific devices (usually found on USB to UART bridge devices) - -### CDC-ACM Devices - -The CDC-ACM Class driver supports CDC-ACM devices that meet the following requirements: -- The device class code must be set to the CDC class `0x02` or implement Interface Association Descriptor (IAD) -- The CDC-ACM must contain the following interfaces: - - A Communication Class Interface containing a management element (EP0) and may also contain a notification element (an interrupt endpoint). The driver will check this interface for CDC Functional Descriptors. - - A Data Class Interface with two BULK endpoints (IN and OUT). Other transfer types are not supported by the driver - -### CDC-Like Vendor Specific Devices - -The CDC-ACM Class driver supports CDC-like devices that meet the following requirements: -- The device class code must be set to the vendor specific class code `0xFF` -- The device needs to provide and interface containing the following endpoints: - - (Mandatory) Two Bulk endpoints (IN and OUT) for data - - (Optional) An interrupt endpoint (IN) for the notification element - -For CDC-like devices, users are responsible for ensuring that they only call APIs (e.g., `cdc_acm_host_send_break()`) that are supported by the target device. - - -## Usage - -The following steps outline the typical API call pattern of the CDC-ACM Class Driver - -1. Install the USB Host Library via `usb_host_install()` -2. Install the CDC-ACM driver via `cdc_acm_host_install()` -3. Call `cdc_acm_host_open()`/`cdc_acm_host_open_vendor_specific()` to open a target CDC-ACM/CDC-like device. These functions will block until the target device is connected -4. To transmit data, call `cdc_acm_host_data_tx_blocking()` -5. When data is received, the driver will automatically run the receive data callback -6. An opened device can be closed via `cdc_acm_host_close()` -7. The CDC-ACM driver can be uninstalled via `cdc_acm_host_uninstall()` - -## Examples - -- For an example with a CDC-ACM device, refer to [cdc_acm_host](../../cdc_acm_host) -- For an example with a CDC-like device, refer to [cdc_acm_host_bg96](../../cdc_acm_bg96) diff --git a/examples/peripherals/usb/host/cdc/common/cdc_acm_host/cdc_acm_host.c b/examples/peripherals/usb/host/cdc/common/cdc_acm_host/cdc_acm_host.c deleted file mode 100644 index 4d8cfd3f9e..0000000000 --- a/examples/peripherals/usb/host/cdc/common/cdc_acm_host/cdc_acm_host.c +++ /dev/null @@ -1,1223 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "esp_log.h" -#include -#include -#include -#include "usb/usb_host.h" -#include "usb/cdc_acm_host.h" -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "freertos/semphr.h" -#include "freertos/event_groups.h" -#include "esp_check.h" -#include "esp_system.h" - -#define TAG "cdc_acm" - -// CDC devices often implement Interface Association Descriptor (IAD). Parse IAD only when -// bDeviceClass = 0xEF (Miscellaneous Device Class), bDeviceSubClass = 0x02 (Common Class), bDeviceProtocol = 0x01 (Interface Association Descriptor) -// @see USB Interface Association Descriptor: Device Class Code and Use Model rev 1.0, Table 1-1 -#define USB_SUBCLASS_COMMON 0x02 -#define USB_DEVICE_PROTOCOL_IAD 0x01 - -// CDC-ACM spinlock -static portMUX_TYPE cdc_acm_lock = portMUX_INITIALIZER_UNLOCKED; -#define CDC_ACM_ENTER_CRITICAL() portENTER_CRITICAL(&cdc_acm_lock) -#define CDC_ACM_EXIT_CRITICAL() portEXIT_CRITICAL(&cdc_acm_lock) - -// CDC-ACM events -#define CDC_ACM_TEARDOWN BIT0 -#define CDC_ACM_TEARDOWN_COMPLETE BIT1 - -// CDC-ACM check macros -#define CDC_ACM_CHECK(cond, ret_val) ({ \ - if (!(cond)) { \ - return (ret_val); \ - } \ -}) - -#define CDC_ACM_CHECK_FROM_CRIT(cond, ret_val) ({ \ - if (!(cond)) { \ - CDC_ACM_EXIT_CRITICAL(); \ - return ret_val; \ - } \ -}) - -// CDC-ACM driver object -typedef struct { - usb_host_client_handle_t cdc_acm_client_hdl; /*!< USB Host handle reused for all CDC-ACM devices in the system */ - SemaphoreHandle_t open_close_mutex; - EventGroupHandle_t event_group; - cdc_acm_new_dev_callback_t new_dev_cb; - SLIST_HEAD(list_dev, cdc_dev_s) cdc_devices_list; /*!< List of open pseudo devices */ -} cdc_acm_obj_t; - -static cdc_acm_obj_t *p_cdc_acm_obj = NULL; - -/** - * @brief Default CDC-ACM driver configuration - * - * This configuration is used when user passes NULL to config pointer during device open. - */ -static const cdc_acm_host_driver_config_t cdc_acm_driver_config_default = { - .driver_task_stack_size = 4096, - .driver_task_priority = 10, - .xCoreID = 0, - .new_dev_cb = NULL, -}; - -/** - * @brief USB CDC PSTN Call Descriptor - * - * @see Table 3, USB CDC-PSTN specification rev. 1.2 - */ -typedef struct { - uint8_t bFunctionLength; - const uint8_t bDescriptorType; - const cdc_desc_subtype_t bDescriptorSubtype; - union { - struct { - uint8_t call_management: 1; // Device handles call management itself - uint8_t call_over_data_if: 1; // Device sends/receives call management information over Data Class interface - uint8_t reserved: 6; - }; - uint8_t val; - } bmCapabilities; - uint8_t bDataInterface; // Interface number of Data Class interface optionally used for call management -} __attribute__((packed)) cdc_acm_call_desc_t; - -/** - * @brief USB CDC PSTN Abstract Control Model Descriptor - * - * @see Table 4, USB CDC-PSTN specification rev. 1.2 - */ -typedef struct { - uint8_t bFunctionLength; - const uint8_t bDescriptorType; - const cdc_desc_subtype_t bDescriptorSubtype; - union { - struct { - uint8_t feature: 1; // Device supports Set/Clear/Get_Comm_Feature requests - uint8_t serial: 1; // Device supports Set/Get_Line_Coding, Set_Control_Line_State and Serial_State request and notifications - uint8_t send_break: 1; // Device supports Send_Break request - uint8_t network: 1; // Device supports Network_Connection notification - uint8_t reserved: 4; - }; - uint8_t val; - } bmCapabilities; -} __attribute__((packed)) cdc_acm_acm_desc_t; - -typedef struct cdc_dev_s cdc_dev_t; -struct cdc_dev_s{ - usb_device_handle_t dev_hdl; // USB device handle - void *cb_arg; // Common argument for user's callbacks (data IN and Notification) - struct { - usb_transfer_t *out_xfer; // OUT data transfer - usb_transfer_t *in_xfer; // IN data transfer - cdc_acm_data_callback_t in_cb; // User's callback for async (non-blocking) data IN - const usb_intf_desc_t *intf_desc; // Pointer to data interface descriptor - SemaphoreHandle_t out_mux; // OUT mutex - } data; - - struct { - usb_transfer_t *xfer; // IN notification transfer - const usb_intf_desc_t *intf_desc; // Pointer to notification interface descriptor, can be NULL if there is no notification channel in the device - cdc_acm_host_dev_callback_t cb; // User's callback for device events - } notif; // Structure with Notif pipe data - - usb_transfer_t *ctrl_transfer; // CTRL (endpoint 0) transfer - SemaphoreHandle_t ctrl_mux; // CTRL mutex - cdc_acm_uart_state_t serial_state; // Serial State - cdc_comm_protocol_t comm_protocol; - cdc_data_protocol_t data_protocol; - int num_cdc_intf_desc; // Number of CDC Interface descriptors in following array - const usb_standard_desc_t **cdc_intf_desc; // CDC Interface descriptors - SLIST_ENTRY(cdc_dev_s) list_entry; -}; - -/** - * @brief Notification received callback - * - * Notification (interrupt) IN transfer is submitted at the end of this function to ensure periodic poll of IN endpoint. - * - * @param[in] transfer Transfer that triggered the callback - */ -static void notif_xfer_cb(usb_transfer_t *transfer); - -/** - * @brief Data received callback - * - * Data (bulk) IN transfer is submitted at the end of this function to ensure continuous poll of IN endpoint. - * - * @param[in] transfer Transfer that triggered the callback - */ -static void in_xfer_cb(usb_transfer_t *transfer); - -/** - * @brief Data send callback - * - * Reused for bulk OUT and CTRL transfers - * - * @param[in] transfer Transfer that triggered the callback - */ -static void out_xfer_cb(usb_transfer_t *transfer); - -/** - * @brief USB Host Client event callback - * - * Handling of USB device connection/disconnection to/from root HUB. - * - * @param[in] event_msg Event message type - * @param[in] arg Caller's argument (not used in this driver) - */ -static void usb_event_cb(const usb_host_client_event_msg_t *event_msg, void *arg); - -/** - * @brief Send CDC specific request - * - * Helper function that will send CDC specific request to default endpoint. - * Both IN and OUT requests are sent through this API, depending on the in_transfer parameter. - * - * @see Chapter 6.2, USB CDC specification rev. 1.2 - * @note CDC specific requests are only supported by devices that have dedicated management element. - * - * @param[in] cdc_dev Pointer to CDC device - * @param[in] in_transfer Direction of data phase. true: IN, false: OUT - * @param[in] request CDC request code - * @param[inout] data Pointer to data buffer. Input for OUT transfers, output for IN transfers. - * @param[in] data_len Length of data buffer - * @param[in] value Value to be set in bValue of Setup packet - * @return esp_err_t - */ -static esp_err_t send_cdc_request(cdc_dev_t *cdc_dev, bool in_transfer, cdc_request_code_t request, uint8_t *data, uint16_t data_len, uint16_t value); - -/** - * @brief CDC-ACM driver handling task - * - * USB host client registration and deregistration is handled here. - * - * @param[in] arg User's argument. Handle of a task that started this task. - */ -static void cdc_acm_client_task(void *arg) -{ - vTaskSuspend(NULL); // Task will be resumed from cdc_acm_host_install() - cdc_acm_obj_t *cdc_acm_obj = p_cdc_acm_obj; // Make local copy of the driver's handle - assert(cdc_acm_obj->cdc_acm_client_hdl); - - // Start handling client's events - while (1) { - usb_host_client_handle_events(cdc_acm_obj->cdc_acm_client_hdl, portMAX_DELAY); - EventBits_t events = xEventGroupGetBits(cdc_acm_obj->event_group); - if (events & CDC_ACM_TEARDOWN) { - break; - } - } - - ESP_LOGD(TAG, "Deregistering client"); - ESP_ERROR_CHECK(usb_host_client_deregister(cdc_acm_obj->cdc_acm_client_hdl)); - xEventGroupSetBits(cdc_acm_obj->event_group, CDC_ACM_TEARDOWN_COMPLETE); - vTaskDelete(NULL); -} - -/** - * @brief Cancel transfer and reset endpoint - * - * This function will cancel ongoing transfer a reset its endpoint to ready state. - * - * @param[in] dev_hdl USB device handle - * @param[in] transfer Transfer to be cancelled - * @return esp_err_t - */ -static esp_err_t cdc_acm_reset_transfer_endpoint(usb_device_handle_t dev_hdl, usb_transfer_t *transfer) -{ - assert(dev_hdl); - assert(transfer); - - ESP_RETURN_ON_ERROR(usb_host_endpoint_halt(dev_hdl, transfer->bEndpointAddress), TAG,); - ESP_RETURN_ON_ERROR(usb_host_endpoint_flush(dev_hdl, transfer->bEndpointAddress), TAG,); - usb_host_endpoint_clear(dev_hdl, transfer->bEndpointAddress); - return ESP_OK; -} - -/** - * @brief Start CDC device - * - * After this call, USB host peripheral will continuously poll IN endpoints. - * - * @param cdc_dev - * @param[in] event_cb Device event callback - * @param[in] in_cb Data received callback - * @param[in] user_arg Optional user's argument, that will be passed to the callbacks - * @return esp_err_t - */ -static esp_err_t cdc_acm_start(cdc_dev_t *cdc_dev, cdc_acm_host_dev_callback_t event_cb, cdc_acm_data_callback_t in_cb, void *user_arg) -{ - esp_err_t ret = ESP_OK; - assert(cdc_dev); - - CDC_ACM_ENTER_CRITICAL(); - cdc_dev->notif.cb = event_cb; - cdc_dev->data.in_cb = in_cb; - cdc_dev->cb_arg = user_arg; - CDC_ACM_EXIT_CRITICAL(); - - // Claim data interface and start polling its IN endpoint - ESP_GOTO_ON_ERROR(usb_host_interface_claim(p_cdc_acm_obj->cdc_acm_client_hdl, cdc_dev->dev_hdl, cdc_dev->data.intf_desc->bInterfaceNumber, 0), err, TAG,); - ESP_LOGD("CDC_ACM", "Submitting poll for BULK IN transfer"); - ESP_ERROR_CHECK(usb_host_transfer_submit(cdc_dev->data.in_xfer)); - - // If notification are supported, claim its interface and start polling its IN endpoint - if (cdc_dev->notif.intf_desc != NULL) { - if (cdc_dev->notif.intf_desc != cdc_dev->data.intf_desc) { - ESP_GOTO_ON_ERROR(usb_host_interface_claim(p_cdc_acm_obj->cdc_acm_client_hdl, cdc_dev->dev_hdl, - cdc_dev->notif.intf_desc->bInterfaceNumber, 0), err, TAG,); - } - ESP_LOGD("CDC_ACM", "Submitting poll for INTR IN transfer"); - ESP_ERROR_CHECK(usb_host_transfer_submit(cdc_dev->notif.xfer)); - } - - // Everything OK, add the device into list and return - CDC_ACM_ENTER_CRITICAL(); - SLIST_INSERT_HEAD(&p_cdc_acm_obj->cdc_devices_list, cdc_dev, list_entry); - CDC_ACM_EXIT_CRITICAL(); - return ret; - -err: - usb_host_interface_release(p_cdc_acm_obj->cdc_acm_client_hdl, cdc_dev->dev_hdl, cdc_dev->data.intf_desc->bInterfaceNumber); - if (cdc_dev->notif.intf_desc != NULL) { - usb_host_interface_release(p_cdc_acm_obj->cdc_acm_client_hdl, cdc_dev->dev_hdl, cdc_dev->notif.intf_desc->bInterfaceNumber); - } - return ret; -} - -static void cdc_acm_transfers_free(cdc_dev_t *cdc_dev); -/** - * @brief Helper function that releases resources claimed by CDC device - * - * Close underlying USB device, free device driver memory - * - * @note All interfaces claimed by this device must be release before calling this function - * @param cdc_dev CDC device handle to be removed - */ -static void cdc_acm_device_remove(cdc_dev_t *cdc_dev) -{ - assert(cdc_dev); - cdc_acm_transfers_free(cdc_dev); - free(cdc_dev->cdc_intf_desc); - // We don't check the error code of usb_host_device_close, as the close might fail, if someone else is still using the device (not all interfaces are released) - usb_host_device_close(p_cdc_acm_obj->cdc_acm_client_hdl, cdc_dev->dev_hdl); // Gracefully continue on error - free(cdc_dev); -} - -/** - * @brief Open USB device with requested VID/PID - * - * This function has two regular return paths: - * 1. USB device with matching VID/PID is already opened by this driver: allocate new CDC device on top of the already opened USB device. - * 2. USB device with matching VID/PID is NOT opened by this driver yet: poll USB connected devices until it is found. - * - * @note This function will block for timeout_ms, if the device is not enumerated at the moment of calling this function. - * @param[in] vid Vendor ID - * @param[in] pid Product ID - * @param[in] timeout_ms Connection timeout [ms] - * @param[out] dev CDC-ACM device - * @return esp_err_t - */ -static esp_err_t cdc_acm_find_and_open_usb_device(uint16_t vid, uint16_t pid, int timeout_ms, cdc_dev_t **dev) -{ - assert(p_cdc_acm_obj); - assert(dev); - - *dev = calloc(1, sizeof(cdc_dev_t)); - if (*dev == NULL) { - return ESP_ERR_NO_MEM; - } - - // First, check list of already opened CDC devices - ESP_LOGD(TAG, "Checking list of opened USB devices"); - cdc_dev_t *cdc_dev; - SLIST_FOREACH(cdc_dev, &p_cdc_acm_obj->cdc_devices_list, list_entry) { - const usb_device_desc_t *device_desc; - ESP_ERROR_CHECK(usb_host_get_device_descriptor(cdc_dev->dev_hdl, &device_desc)); - if (device_desc->idVendor == vid && device_desc->idProduct == pid) { - // Return path 1: - (*dev)->dev_hdl = cdc_dev->dev_hdl; - return ESP_OK; - } - } - - // Second, poll connected devices until new device is connected or timeout - TickType_t timeout_ticks = (timeout_ms == 0) ? portMAX_DELAY : pdMS_TO_TICKS(timeout_ms); - TimeOut_t connection_timeout; - vTaskSetTimeOutState(&connection_timeout); - - while (true) { - ESP_LOGD(TAG, "Checking list of connected USB devices"); - uint8_t dev_addr_list[10]; - int num_of_devices; - ESP_ERROR_CHECK(usb_host_device_addr_list_fill(sizeof(dev_addr_list), dev_addr_list, &num_of_devices)); - - // Go through device address list and find the one we are looking for - for (int i = 0; i < num_of_devices; i++) { - usb_device_handle_t current_device; - // Open USB device - if (usb_host_device_open(p_cdc_acm_obj->cdc_acm_client_hdl, dev_addr_list[i], ¤t_device) != ESP_OK) { - continue; // In case we failed to open this device, continue with next one in the list - } - assert(current_device); - const usb_device_desc_t *device_desc; - ESP_ERROR_CHECK(usb_host_get_device_descriptor(current_device, &device_desc)); - if (device_desc->idVendor == vid && device_desc->idProduct == pid) { - // Return path 2: - (*dev)->dev_hdl = current_device; - return ESP_OK; - } - usb_host_device_close(p_cdc_acm_obj->cdc_acm_client_hdl, current_device); - } - - if (xTaskCheckForTimeOut(&connection_timeout, &timeout_ticks) != pdFALSE) { - break; // Timeout elapsed and the device is not connected - } - vTaskDelay(pdMS_TO_TICKS(50)); - } - - // Timeout was reached, clean-up - free(*dev); - *dev = NULL; - return ESP_ERR_NOT_FOUND; -} - -esp_err_t cdc_acm_host_install(const cdc_acm_host_driver_config_t *driver_config) -{ - CDC_ACM_CHECK(!p_cdc_acm_obj, ESP_ERR_INVALID_STATE); - - // Check driver configuration, use default if NULL is passed - if (driver_config == NULL) { - driver_config = &cdc_acm_driver_config_default; - } - - // Allocate all we need for this driver - esp_err_t ret; - cdc_acm_obj_t *cdc_acm_obj = heap_caps_calloc(1, sizeof(cdc_acm_obj_t), MALLOC_CAP_DEFAULT); - EventGroupHandle_t event_group = xEventGroupCreate(); - SemaphoreHandle_t mutex = xSemaphoreCreateMutex(); - TaskHandle_t driver_task_h = NULL; - xTaskCreatePinnedToCore( - cdc_acm_client_task, "USB-CDC", driver_config->driver_task_stack_size, NULL, - driver_config->driver_task_priority, &driver_task_h, driver_config->xCoreID); - - if (cdc_acm_obj == NULL || driver_task_h == NULL || event_group == NULL || mutex == NULL) { - ret = ESP_ERR_NO_MEM; - goto err; - } - - // Register USB Host client - usb_host_client_handle_t usb_client = NULL; - const usb_host_client_config_t client_config = { - .is_synchronous = false, - .max_num_event_msg = 3, - .async.client_event_callback = usb_event_cb, - .async.callback_arg = NULL - }; - ESP_GOTO_ON_ERROR(usb_host_client_register(&client_config, &usb_client), err, TAG, "Failed to register USB host client"); - - // Initialize CDC-ACM driver structure - SLIST_INIT(&(cdc_acm_obj->cdc_devices_list)); - cdc_acm_obj->event_group = event_group; - cdc_acm_obj->open_close_mutex = mutex; - cdc_acm_obj->cdc_acm_client_hdl = usb_client; - cdc_acm_obj->new_dev_cb = driver_config->new_dev_cb; - - // Between 1st call of this function and following section, another task might try to install this driver: - // Make sure that there is only one instance of this driver in the system - CDC_ACM_ENTER_CRITICAL(); - if (p_cdc_acm_obj) { - // Already created - ret = ESP_ERR_INVALID_STATE; - CDC_ACM_EXIT_CRITICAL(); - goto client_err; - } else { - p_cdc_acm_obj = cdc_acm_obj; - } - CDC_ACM_EXIT_CRITICAL(); - - // Everything OK: Start CDC-Driver task and return - vTaskResume(driver_task_h); - return ESP_OK; - -client_err: - usb_host_client_deregister(usb_client); -err: // Clean-up - free(cdc_acm_obj); - if (event_group) { - vEventGroupDelete(event_group); - } - if (driver_task_h) { - vTaskDelete(driver_task_h); - } - if (mutex) { - vSemaphoreDelete(mutex); - } - return ret; -} - -esp_err_t cdc_acm_host_uninstall() -{ - esp_err_t ret; - - CDC_ACM_ENTER_CRITICAL(); - CDC_ACM_CHECK_FROM_CRIT(p_cdc_acm_obj, ESP_ERR_INVALID_STATE); - cdc_acm_obj_t *cdc_acm_obj = p_cdc_acm_obj; // Save Driver's handle to temporary handle - CDC_ACM_EXIT_CRITICAL(); - - xSemaphoreTake(p_cdc_acm_obj->open_close_mutex, portMAX_DELAY); // Wait for all open/close calls to finish - - CDC_ACM_ENTER_CRITICAL(); - if (SLIST_EMPTY(&p_cdc_acm_obj->cdc_devices_list)) { // Check that device list is empty (all devices closed) - p_cdc_acm_obj = NULL; // NULL static driver pointer: No open/close calls form this point - } else { - ret = ESP_ERR_INVALID_STATE; - CDC_ACM_EXIT_CRITICAL(); - goto unblock; - } - CDC_ACM_EXIT_CRITICAL(); - - // Signal to CDC task to stop, unblock it and wait for its deletion - xEventGroupSetBits(cdc_acm_obj->event_group, CDC_ACM_TEARDOWN); - usb_host_client_unblock(cdc_acm_obj->cdc_acm_client_hdl); - ESP_GOTO_ON_FALSE( - xEventGroupWaitBits(cdc_acm_obj->event_group, CDC_ACM_TEARDOWN_COMPLETE, pdFALSE, pdFALSE, pdMS_TO_TICKS(100)), - ESP_ERR_NOT_FINISHED, unblock, TAG,); - - // Free remaining resources and return - vEventGroupDelete(cdc_acm_obj->event_group); - xSemaphoreGive(cdc_acm_obj->open_close_mutex); - vSemaphoreDelete(cdc_acm_obj->open_close_mutex); - free(cdc_acm_obj); - return ESP_OK; - -unblock: - xSemaphoreGive(cdc_acm_obj->open_close_mutex); - return ret; -} - -/** - * @brief Free USB transfers used by this device - * - * @note There can be no transfers in flight, at the moment of calling this function. - * @param[in] cdc_dev Pointer to CDC device - */ -static void cdc_acm_transfers_free(cdc_dev_t *cdc_dev) -{ - assert(cdc_dev); - usb_host_transfer_free(cdc_dev->notif.xfer); - usb_host_transfer_free(cdc_dev->data.in_xfer); - if (cdc_dev->data.out_xfer != NULL) { - if (cdc_dev->data.out_xfer->context != NULL) { - vSemaphoreDelete((SemaphoreHandle_t)cdc_dev->data.out_xfer->context); - } - if (cdc_dev->data.out_mux != NULL) { - vSemaphoreDelete(cdc_dev->data.out_mux); - } - usb_host_transfer_free(cdc_dev->data.out_xfer); - } - if (cdc_dev->ctrl_transfer != NULL) { - if (cdc_dev->ctrl_transfer->context != NULL) { - vSemaphoreDelete((SemaphoreHandle_t)cdc_dev->ctrl_transfer->context); - } - if (cdc_dev->ctrl_mux != NULL) { - vSemaphoreDelete(cdc_dev->ctrl_mux); - } - usb_host_transfer_free(cdc_dev->ctrl_transfer); - } -} - -/** - * @brief Allocate CDC transfers - * - * @param[in] cdc_dev Pointer to CDC device - * @param[in] notif_ep_desc Pointer to notification EP descriptor - * @param[in] in_ep_desc- Pointer to data IN EP descriptor - * @param[in] out_ep_desc Pointer to data OUT EP descriptor - * @param[in] out_buf_len Length of data OUT buffer - * @return esp_err_t - */ -static esp_err_t cdc_acm_transfers_allocate(cdc_dev_t *cdc_dev, const usb_ep_desc_t *notif_ep_desc, const usb_ep_desc_t *in_ep_desc, const usb_ep_desc_t *out_ep_desc, size_t out_buf_len) -{ - esp_err_t ret; - - // 1. Setup notification transfer if it is supported - if (notif_ep_desc) { - ESP_GOTO_ON_ERROR( - usb_host_transfer_alloc(USB_EP_DESC_GET_MPS(notif_ep_desc), 0, &cdc_dev->notif.xfer), - err, TAG,); - cdc_dev->notif.xfer->device_handle = cdc_dev->dev_hdl; - cdc_dev->notif.xfer->bEndpointAddress = notif_ep_desc->bEndpointAddress; - cdc_dev->notif.xfer->callback = notif_xfer_cb; - cdc_dev->notif.xfer->context = cdc_dev; - cdc_dev->notif.xfer->num_bytes = USB_EP_DESC_GET_MPS(notif_ep_desc); - } - - // 2. Setup control transfer - usb_device_info_t dev_info; - ESP_ERROR_CHECK(usb_host_device_info(cdc_dev->dev_hdl, &dev_info)); - ESP_GOTO_ON_ERROR( - usb_host_transfer_alloc(dev_info.bMaxPacketSize0, 0, &cdc_dev->ctrl_transfer), - err, TAG,); - cdc_dev->ctrl_transfer->timeout_ms = 1000; - cdc_dev->ctrl_transfer->bEndpointAddress = 0; - cdc_dev->ctrl_transfer->device_handle = cdc_dev->dev_hdl; - cdc_dev->ctrl_transfer->context = cdc_dev; - cdc_dev->ctrl_transfer->callback = out_xfer_cb; - cdc_dev->ctrl_transfer->context = xSemaphoreCreateBinary(); - ESP_GOTO_ON_FALSE(cdc_dev->ctrl_transfer->context, ESP_ERR_NO_MEM, err, TAG,); - cdc_dev->ctrl_mux = xSemaphoreCreateMutex(); - ESP_GOTO_ON_FALSE(cdc_dev->ctrl_mux, ESP_ERR_NO_MEM, err, TAG,); - - // 3. Setup IN data transfer - ESP_GOTO_ON_ERROR( - usb_host_transfer_alloc(USB_EP_DESC_GET_MPS(in_ep_desc), 0, &cdc_dev->data.in_xfer), - err, TAG, - ); - assert(cdc_dev->data.in_xfer); - cdc_dev->data.in_xfer->callback = in_xfer_cb; - cdc_dev->data.in_xfer->num_bytes = USB_EP_DESC_GET_MPS(in_ep_desc); - cdc_dev->data.in_xfer->bEndpointAddress = in_ep_desc->bEndpointAddress; - cdc_dev->data.in_xfer->device_handle = cdc_dev->dev_hdl; - cdc_dev->data.in_xfer->context = cdc_dev; - - // 4. Setup OUT bulk transfer (if it is required (out_buf_len > 0)) - if (out_buf_len != 0) { - ESP_GOTO_ON_ERROR( - usb_host_transfer_alloc(out_buf_len, 0, &cdc_dev->data.out_xfer), - err, TAG, - ); - assert(cdc_dev->data.out_xfer); - cdc_dev->data.out_xfer->device_handle = cdc_dev->dev_hdl; - cdc_dev->data.out_xfer->context = xSemaphoreCreateBinary(); - ESP_GOTO_ON_FALSE(cdc_dev->data.out_xfer->context, ESP_ERR_NO_MEM, err, TAG,); - cdc_dev->data.out_mux = xSemaphoreCreateMutex(); - ESP_GOTO_ON_FALSE(cdc_dev->data.out_mux, ESP_ERR_NO_MEM, err, TAG,); - cdc_dev->data.out_xfer->bEndpointAddress = out_ep_desc->bEndpointAddress; - cdc_dev->data.out_xfer->callback = out_xfer_cb; - } - return ESP_OK; - -err: - cdc_acm_transfers_free(cdc_dev); - return ret; -} - -/** - * @brief Find CDC interface descriptor and its endpoint descriptors - * - * @note This function is called in open procedure of CDC compliant devices only. - * @param[in] cdc_dev Pointer to CDC device - * @param[in] intf_idx Index of CDC interface that should be used for this device - * @param[out] notif_ep Pointer to notification EP descriptor - * @param[out] in_ep Pointer to data IN EP descriptor - * @param[out] out_ep Pointer to data OUT EP descriptor - * @return esp_err_t - */ -static esp_err_t cdc_acm_find_intf_and_ep_desc(cdc_dev_t *cdc_dev, uint8_t intf_idx, const usb_ep_desc_t **notif_ep, const usb_ep_desc_t **in_ep, const usb_ep_desc_t **out_ep) -{ - bool interface_found = false; - const usb_config_desc_t *config_desc; - const usb_device_desc_t *device_desc; - int data_intf_idx, notif_intf_idx; - int desc_offset = 0; - - // Get required descriptors - ESP_ERROR_CHECK(usb_host_get_device_descriptor(cdc_dev->dev_hdl, &device_desc)); - ESP_ERROR_CHECK(usb_host_get_active_config_descriptor(cdc_dev->dev_hdl, &config_desc)); - - if ((device_desc->bDeviceClass == USB_CLASS_MISC) && (device_desc->bDeviceSubClass == USB_SUBCLASS_COMMON) && - (device_desc->bDeviceProtocol == USB_DEVICE_PROTOCOL_IAD)) { - // This is a composite device, that uses Interface Association Descriptor - const usb_standard_desc_t *this_desc = (const usb_standard_desc_t *)config_desc; - do { - this_desc = usb_parse_next_descriptor_of_type( - this_desc, config_desc->wTotalLength, USB_B_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, &desc_offset); - - if (this_desc == NULL) - break; // Reached end of configuration descriptor - - const usb_iad_desc_t *iad_desc = (const usb_iad_desc_t *)this_desc; - if (iad_desc->bFirstInterface == intf_idx) { - // IAD with correct interface number was found: Check Class/Subclass codes, save Interface indexes - assert(iad_desc->bInterfaceCount == 2); - assert(iad_desc->bFunctionClass == USB_CLASS_COMM); - assert(iad_desc->bFunctionSubClass == USB_CDC_SUBCLASS_ACM); - notif_intf_idx = iad_desc->bFirstInterface; - data_intf_idx = iad_desc->bFirstInterface + 1; - interface_found = true; - } - } while (!interface_found); - } else if ((device_desc->bDeviceClass == USB_CLASS_COMM) && (intf_idx == 0)) { - // This is a Communication Device Class - notif_intf_idx = 0; - data_intf_idx = 1; - interface_found = true; - } - - // Save found interfaces descriptors: - if (interface_found) { - // Notification IF and EP - cdc_dev->notif.intf_desc = usb_parse_interface_descriptor(config_desc, notif_intf_idx, 0, &desc_offset); - assert(cdc_dev->notif.intf_desc); - - // CDC specific descriptors should be right after CDC-Communication interface descriptor - // Note: That's why we use usb_parse_next_descriptor instead of usb_parse_next_descriptor_of_type. - // The latter could return CDC specific descriptors that don't belong to this interface - const usb_standard_desc_t *cdc_desc = (usb_standard_desc_t *)cdc_dev->notif.intf_desc; - do { - cdc_desc = usb_parse_next_descriptor(cdc_desc, config_desc->wTotalLength, &desc_offset); - if ((cdc_desc == NULL) || (cdc_desc->bDescriptorType != ((USB_CLASS_COMM << 4) | USB_B_DESCRIPTOR_TYPE_INTERFACE ))) - break; // We found all CDC specific descriptors - cdc_dev->num_cdc_intf_desc++; - cdc_dev->cdc_intf_desc = - realloc(cdc_dev->cdc_intf_desc, cdc_dev->num_cdc_intf_desc * (sizeof(usb_standard_desc_t *))); - assert(cdc_dev->cdc_intf_desc); - cdc_dev->cdc_intf_desc[cdc_dev->num_cdc_intf_desc - 1] = cdc_desc; - } while (1); - *notif_ep = usb_parse_endpoint_descriptor_by_index(cdc_dev->notif.intf_desc, 0, config_desc->wTotalLength, &desc_offset); - assert(notif_ep); - - // Data IF and EP - cdc_dev->data.intf_desc = usb_parse_interface_descriptor(config_desc, data_intf_idx, 0, &desc_offset); - assert(cdc_dev->data.intf_desc); - int temp_offset = desc_offset; - for (int i = 0; i < 2; i++) { - const usb_ep_desc_t *this_ep = usb_parse_endpoint_descriptor_by_index(cdc_dev->data.intf_desc, i, config_desc->wTotalLength, &desc_offset); - assert(this_ep); - if (USB_EP_DESC_GET_EP_DIR(this_ep)) { - *in_ep = this_ep; - } else { - *out_ep = this_ep; - } - desc_offset = temp_offset; - } - return ESP_OK; - } - return ESP_ERR_NOT_FOUND; -} - -esp_err_t cdc_acm_host_open(uint16_t vid, uint16_t pid, uint8_t interface_idx, const cdc_acm_host_device_config_t *dev_config, cdc_acm_dev_hdl_t *cdc_hdl_ret) -{ - esp_err_t ret; - CDC_ACM_CHECK(p_cdc_acm_obj, ESP_ERR_INVALID_STATE); - CDC_ACM_CHECK(dev_config, ESP_ERR_INVALID_ARG); - CDC_ACM_CHECK(cdc_hdl_ret, ESP_ERR_INVALID_ARG); - - xSemaphoreTake(p_cdc_acm_obj->open_close_mutex, portMAX_DELAY); - // Find underlying USB device - cdc_dev_t *cdc_dev; - ESP_GOTO_ON_ERROR( - cdc_acm_find_and_open_usb_device(vid, pid, dev_config->connection_timeout_ms, &cdc_dev), - exit, TAG, "USB device with VID: 0x%04X, PID: 0x%04X not found", vid, pid); - - // Find and save relevant interface and endpoint descriptors - const usb_ep_desc_t *notif_ep = NULL; - const usb_ep_desc_t *in_ep = NULL; - const usb_ep_desc_t *out_ep = NULL; - ESP_GOTO_ON_ERROR( - cdc_acm_find_intf_and_ep_desc(cdc_dev, interface_idx, ¬if_ep, &in_ep, &out_ep), - err, TAG, "Could not find required interface"); - - // Check whether found Interfaces are really CDC-ACM - assert(cdc_dev->notif.intf_desc->bInterfaceClass == USB_CLASS_COMM); - assert(cdc_dev->notif.intf_desc->bInterfaceSubClass == USB_CDC_SUBCLASS_ACM); - assert(cdc_dev->notif.intf_desc->bNumEndpoints == 1); - assert(cdc_dev->data.intf_desc->bInterfaceClass == USB_CLASS_CDC_DATA); - assert(cdc_dev->data.intf_desc->bNumEndpoints == 2); - - // Save Communication and Data protocols - cdc_dev->comm_protocol = (cdc_comm_protocol_t)cdc_dev->notif.intf_desc->bInterfaceProtocol; - cdc_dev->data_protocol = (cdc_data_protocol_t)cdc_dev->data.intf_desc->bInterfaceProtocol; - - // Allocate USB transfers, claim CDC interfaces and return CDC-ACM handle - ESP_GOTO_ON_ERROR(cdc_acm_transfers_allocate(cdc_dev, notif_ep, in_ep, out_ep, dev_config->out_buffer_size), err, TAG,); - ESP_GOTO_ON_ERROR(cdc_acm_start(cdc_dev, dev_config->event_cb, dev_config->data_cb, dev_config->user_arg), err, TAG,); - *cdc_hdl_ret = (cdc_acm_dev_hdl_t)cdc_dev; - xSemaphoreGive(p_cdc_acm_obj->open_close_mutex); - return ESP_OK; - -err: - cdc_acm_device_remove(cdc_dev); -exit: - xSemaphoreGive(p_cdc_acm_obj->open_close_mutex); - *cdc_hdl_ret = NULL; - return ret; -} - -esp_err_t cdc_acm_host_open_vendor_specific(uint16_t vid, uint16_t pid, uint8_t interface_num, const cdc_acm_host_device_config_t *dev_config, cdc_acm_dev_hdl_t *cdc_hdl_ret) -{ - esp_err_t ret; - CDC_ACM_CHECK(p_cdc_acm_obj, ESP_ERR_INVALID_STATE); - CDC_ACM_CHECK(dev_config, ESP_ERR_INVALID_ARG); - CDC_ACM_CHECK(cdc_hdl_ret, ESP_ERR_INVALID_ARG); - - xSemaphoreTake(p_cdc_acm_obj->open_close_mutex, portMAX_DELAY); - - // Find underlying USB device - cdc_dev_t *cdc_dev; - ESP_GOTO_ON_ERROR( - cdc_acm_find_and_open_usb_device(vid, pid, dev_config->connection_timeout_ms, &cdc_dev), - exit, TAG, "USB device with VID: 0x%04X, PID: 0x%04X not found", vid, pid); - - // Open procedure for CDC-ACM non-compliant devices: - const usb_config_desc_t *config_desc; - int desc_offset; - ESP_ERROR_CHECK(usb_host_get_active_config_descriptor(cdc_dev->dev_hdl, &config_desc)); - cdc_dev->data.intf_desc = usb_parse_interface_descriptor(config_desc, interface_num, 0, &desc_offset); - ESP_GOTO_ON_FALSE( - cdc_dev->data.intf_desc, - ESP_ERR_NOT_FOUND, err, TAG, "Required interfece no %d was not found.", interface_num); - const int temp_offset = desc_offset; // Save this offset for later - - // The interface can have 2-3 endpoints. 2 for data and 1 optional for notifications - const usb_ep_desc_t *in_ep = NULL; - const usb_ep_desc_t *out_ep = NULL; - const usb_ep_desc_t *notif_ep = NULL; - int ep_idx = 0; - if (cdc_dev->data.intf_desc->bNumEndpoints == 3) { - // Notification channel does not have its dedicated interface (data and notif interface is the same) - // First endpoint of this interface is used as notification channel - cdc_dev->notif.intf_desc = cdc_dev->data.intf_desc; - notif_ep = usb_parse_endpoint_descriptor_by_index(cdc_dev->data.intf_desc, 0, config_desc->wTotalLength, &desc_offset); - desc_offset = temp_offset; - ep_idx++; - } - - for (int i = ep_idx; i < ep_idx + 2; i++) { - const usb_ep_desc_t *this_ep = usb_parse_endpoint_descriptor_by_index(cdc_dev->data.intf_desc, i, config_desc->wTotalLength, &desc_offset); - assert(this_ep); - if (USB_EP_DESC_GET_EP_DIR(this_ep)) { - in_ep = this_ep; - } else { - out_ep = this_ep; - } - desc_offset = temp_offset; - } - - // Allocate USB transfers, claim CDC interfaces and return CDC-ACM handle - ESP_GOTO_ON_ERROR(cdc_acm_transfers_allocate(cdc_dev, notif_ep, in_ep, out_ep, dev_config->out_buffer_size), err, TAG, ); - ESP_GOTO_ON_ERROR(cdc_acm_start(cdc_dev, dev_config->event_cb, dev_config->data_cb, dev_config->user_arg), err, TAG,); - *cdc_hdl_ret = (cdc_acm_dev_hdl_t)cdc_dev; - xSemaphoreGive(p_cdc_acm_obj->open_close_mutex); - return ESP_OK; -err: - cdc_acm_device_remove(cdc_dev); -exit: - xSemaphoreGive(p_cdc_acm_obj->open_close_mutex); - return ret; -} - -esp_err_t cdc_acm_host_close(cdc_acm_dev_hdl_t cdc_hdl) -{ - CDC_ACM_CHECK(p_cdc_acm_obj, ESP_ERR_INVALID_STATE); - CDC_ACM_CHECK(cdc_hdl, ESP_ERR_INVALID_ARG); - - xSemaphoreTake(p_cdc_acm_obj->open_close_mutex, portMAX_DELAY); - - cdc_dev_t *cdc_dev = (cdc_dev_t *)cdc_hdl; - - // Cancel polling of BULK IN and INTERRUPT IN endpoints - cdc_dev->notif.cb = NULL; - cdc_dev->data.in_cb = NULL; - ESP_ERROR_CHECK(cdc_acm_reset_transfer_endpoint(cdc_dev->dev_hdl, cdc_dev->data.in_xfer)); - if (cdc_dev->notif.intf_desc != NULL) { - ESP_ERROR_CHECK(cdc_acm_reset_transfer_endpoint(cdc_dev->dev_hdl, cdc_dev->notif.xfer)); - } - - // Release all interfaces - ESP_ERROR_CHECK(usb_host_interface_release(p_cdc_acm_obj->cdc_acm_client_hdl, cdc_dev->dev_hdl, cdc_dev->data.intf_desc->bInterfaceNumber)); - if ((cdc_dev->notif.intf_desc != NULL) && (cdc_dev->notif.intf_desc != cdc_dev->data.intf_desc)) { - ESP_ERROR_CHECK(usb_host_interface_release(p_cdc_acm_obj->cdc_acm_client_hdl, cdc_dev->dev_hdl, cdc_dev->notif.intf_desc->bInterfaceNumber)); - } - - CDC_ACM_ENTER_CRITICAL(); - SLIST_REMOVE(&p_cdc_acm_obj->cdc_devices_list, cdc_dev, cdc_dev_s, list_entry); - CDC_ACM_EXIT_CRITICAL(); - - cdc_acm_device_remove(cdc_dev); - xSemaphoreGive(p_cdc_acm_obj->open_close_mutex); - return ESP_OK; -} - -/** - * @brief Print CDC specific descriptor in human readable form - * - * This is a callback function that is called from USB Host library, - * when it wants to print full configuration descriptor to stdout. - * - * @param[in] _desc CDC specific descriptor - */ -static void cdc_acm_print_desc(const usb_standard_desc_t *_desc) -{ - if (_desc->bDescriptorType != ((USB_CLASS_COMM << 4) | USB_B_DESCRIPTOR_TYPE_INTERFACE )) - { - // Quietly return in case that this descriptor is not CDC interface descriptor - return; - } - - switch (((cdc_header_desc_t *)_desc)->bDescriptorSubtype) { - case USB_CDC_DESC_SUBTYPE_HEADER: { - cdc_header_desc_t *desc = (cdc_header_desc_t *)_desc; - printf("\t*** CDC Header Descriptor ***\n"); - printf("\tbcdCDC: %d.%d0\n", ((desc->bcdCDC >> 8) & 0xF), ((desc->bcdCDC >> 4) & 0xF)); - break; - } - case USB_CDC_DESC_SUBTYPE_CALL: { - cdc_acm_call_desc_t *desc = (cdc_acm_call_desc_t *)_desc; - printf("\t*** CDC Call Descriptor ***\n"); - printf("\tbmCapabilities: 0x%02X\n", desc->bmCapabilities.val); - printf("\tbDataInterface: %d\n", desc->bDataInterface); - break; - } - case USB_CDC_DESC_SUBTYPE_ACM: { - cdc_acm_acm_desc_t *desc = (cdc_acm_acm_desc_t *)_desc; - printf("\t*** CDC ACM Descriptor ***\n"); - printf("\tbmCapabilities: 0x%02X\n", desc->bmCapabilities.val); - break; - } - case USB_CDC_DESC_SUBTYPE_UNION: { - cdc_union_desc_t *desc = (cdc_union_desc_t *)_desc; - printf("\t*** CDC Union Descriptor ***\n"); - printf("\tbControlInterface: %d\n", desc->bControlInterface); - printf("\tbSubordinateInterface[0]: %d\n", desc->bSubordinateInterface[0]); - break; - } - default: - ESP_LOGW(TAG, "Unsupported CDC specific descriptor"); - break; - } -} - -void cdc_acm_host_desc_print(cdc_acm_dev_hdl_t cdc_hdl) -{ - assert(cdc_hdl); - cdc_dev_t *cdc_dev = (cdc_dev_t *)cdc_hdl; - - const usb_device_desc_t *device_desc; - const usb_config_desc_t *config_desc; - ESP_ERROR_CHECK_WITHOUT_ABORT(usb_host_get_device_descriptor(cdc_dev->dev_hdl, &device_desc)); - ESP_ERROR_CHECK_WITHOUT_ABORT(usb_host_get_active_config_descriptor(cdc_dev->dev_hdl, &config_desc)); - usb_print_device_descriptor(device_desc); - usb_print_config_descriptor(config_desc, cdc_acm_print_desc); -} - -/** - * @brief Check finished transfer status - * - * Return to on transfer completed OK. - * Cancel the transfer and issue user's callback in case of an error. - * - * @param[in] transfer Transfer to be checked - * @return true Transfer completed - * @return false Transfer NOT completed - */ -static bool cdc_acm_is_transfer_completed(usb_transfer_t *transfer) -{ - cdc_dev_t *cdc_dev = (cdc_dev_t *)transfer->context; - bool completed = false; - - switch (transfer->status) { - case USB_TRANSFER_STATUS_COMPLETED: - completed = true; - break; - case USB_TRANSFER_STATUS_NO_DEVICE: // User is notified about device disconnection from usb_event_cb - case USB_TRANSFER_STATUS_CANCELED: - break; - case USB_TRANSFER_STATUS_ERROR: - case USB_TRANSFER_STATUS_TIMED_OUT: - case USB_TRANSFER_STATUS_STALL: - case USB_TRANSFER_STATUS_OVERFLOW: - case USB_TRANSFER_STATUS_SKIPPED: - default: - // Transfer was not completed or cancelled by user. Inform user about this - if (cdc_dev->notif.cb) { - const cdc_acm_host_dev_event_data_t error_event = { - .type = CDC_ACM_HOST_ERROR, - .data.error = (int) transfer->status - }; - cdc_dev->notif.cb(&error_event, cdc_dev->cb_arg); - } - } - return completed; -} - -static void in_xfer_cb(usb_transfer_t *transfer) -{ - ESP_LOGD("CDC_ACM", "in xfer cb"); - cdc_dev_t *cdc_dev = (cdc_dev_t *)transfer->context; - - if (cdc_acm_is_transfer_completed(transfer)) { - if (cdc_dev->data.in_cb) { - cdc_dev->data.in_cb(transfer->data_buffer, transfer->actual_num_bytes, cdc_dev->cb_arg); - } - - ESP_LOGD("CDC_ACM", "Submitting poll for BULK IN transfer"); - usb_host_transfer_submit(cdc_dev->data.in_xfer); - } -} - -static void notif_xfer_cb(usb_transfer_t *transfer) -{ - ESP_LOGD("CDC_ACM", "notif xfer cb"); - cdc_dev_t *cdc_dev = (cdc_dev_t *)transfer->context; - - if (cdc_acm_is_transfer_completed(transfer)) { - cdc_notification_t *notif = (cdc_notification_t *)transfer->data_buffer; - switch (notif->bNotificationCode) { - case USB_CDC_NOTIF_NETWORK_CONNECTION: { - if (cdc_dev->notif.cb) { - const cdc_acm_host_dev_event_data_t net_conn_event = { - .type = CDC_ACM_HOST_NETWORK_CONNECTION, - .data.network_connected = (bool) notif->wValue - }; - cdc_dev->notif.cb(&net_conn_event, cdc_dev->cb_arg); - } - break; - } - case USB_CDC_NOTIF_SERIAL_STATE: { - cdc_dev->serial_state.val = *((uint16_t *)notif->Data); - if (cdc_dev->notif.cb) { - const cdc_acm_host_dev_event_data_t serial_state_event = { - .type = CDC_ACM_HOST_SERIAL_STATE, - .data.serial_state = cdc_dev->serial_state - }; - cdc_dev->notif.cb(&serial_state_event, cdc_dev->cb_arg); - } - break; - } - case USB_CDC_NOTIF_RESPONSE_AVAILABLE: // Encapsulated commands not implemented - fallthrough - default: - ESP_LOGW("CDC_ACM", "Unsupported notification type 0x%02X", notif->bNotificationCode); - ESP_LOG_BUFFER_HEX("CDC_ACM", transfer->data_buffer, transfer->actual_num_bytes); - break; - } - - // Start polling for new data again - ESP_LOGD("CDC_ACM", "Submitting poll for INTR IN transfer"); - usb_host_transfer_submit(cdc_dev->notif.xfer); - } -} - -static void out_xfer_cb(usb_transfer_t *transfer) -{ - ESP_LOGD("CDC_ACM", "out/ctrl xfer cb"); - assert(transfer->context); - xSemaphoreGive((SemaphoreHandle_t)transfer->context); -} - -static void usb_event_cb(const usb_host_client_event_msg_t *event_msg, void *arg) -{ - switch (event_msg->event) { - case USB_HOST_CLIENT_EVENT_NEW_DEV: - ESP_LOGD(TAG, "New device connected"); - if (p_cdc_acm_obj->new_dev_cb) { - usb_device_handle_t new_dev; - if (usb_host_device_open(p_cdc_acm_obj->cdc_acm_client_hdl, event_msg->new_dev.address, &new_dev) != ESP_OK) { - ESP_LOGW(TAG, "Couldn't open the new device"); - break; - } - assert(new_dev); - p_cdc_acm_obj->new_dev_cb(new_dev); - usb_host_device_close(p_cdc_acm_obj->cdc_acm_client_hdl, new_dev); - } - break; - case USB_HOST_CLIENT_EVENT_DEV_GONE: { - ESP_LOGD(TAG, "Device suddenly disconnected"); - // Find CDC pseudo-devices associated with this USB device and close them - cdc_dev_t *cdc_dev; - cdc_dev_t *tcdc_dev; - // We are using 'SAFE' version of 'SLIST_FOREACH' which enables user to close the disconnected device in the callback - SLIST_FOREACH_SAFE(cdc_dev, &p_cdc_acm_obj->cdc_devices_list, list_entry, tcdc_dev) { - if (cdc_dev->dev_hdl == event_msg->dev_gone.dev_hdl && cdc_dev->notif.cb) { - // The suddenly disconnected device was opened by this driver: inform user about this - const cdc_acm_host_dev_event_data_t disconn_event = { - .type = CDC_ACM_HOST_DEVICE_DISCONNECTED, - .data.cdc_hdl = (cdc_acm_dev_hdl_t) cdc_dev, - }; - cdc_dev->notif.cb(&disconn_event, cdc_dev->cb_arg); - } - } - break; - } - default: - assert(false); - break; - } -} - -esp_err_t cdc_acm_host_data_tx_blocking(cdc_acm_dev_hdl_t cdc_hdl, const uint8_t *data, size_t data_len, uint32_t timeout_ms) -{ - esp_err_t ret; - CDC_ACM_CHECK(cdc_hdl, ESP_ERR_INVALID_ARG); - cdc_dev_t *cdc_dev = (cdc_dev_t *)cdc_hdl; - CDC_ACM_CHECK(data && (data_len > 0), ESP_ERR_INVALID_ARG); - CDC_ACM_CHECK(cdc_dev->data.out_xfer, ESP_ERR_NOT_SUPPORTED); // Device was opened as read-only. - CDC_ACM_CHECK(data_len <= cdc_dev->data.out_xfer->data_buffer_size, ESP_ERR_INVALID_SIZE); - - // Take OUT mutex and fill the OUT transfer - BaseType_t taken = xSemaphoreTake(cdc_dev->data.out_mux, pdMS_TO_TICKS(timeout_ms)); - if (taken != pdTRUE) { - return ESP_ERR_TIMEOUT; - } - - ESP_LOGD("CDC_ACM", "Submitting BULK OUT transfer"); - memcpy(cdc_dev->data.out_xfer->data_buffer, data, data_len); - cdc_dev->data.out_xfer->num_bytes = data_len; - cdc_dev->data.out_xfer->timeout_ms = timeout_ms; - ESP_GOTO_ON_ERROR(usb_host_transfer_submit(cdc_dev->data.out_xfer), unblock, TAG,); - - // Wait for OUT transfer completion - taken = xSemaphoreTake((SemaphoreHandle_t)cdc_dev->data.out_xfer->context, pdMS_TO_TICKS(timeout_ms)); - if (!taken) { - // Reset the endpoint - cdc_acm_reset_transfer_endpoint(cdc_dev->dev_hdl, cdc_dev->data.out_xfer); - ret = ESP_ERR_TIMEOUT; - goto unblock; - } - - ESP_GOTO_ON_FALSE(cdc_dev->data.out_xfer->status == USB_TRANSFER_STATUS_COMPLETED, ESP_ERR_INVALID_RESPONSE, unblock, TAG, "Bulk OUT transfer error"); - ESP_GOTO_ON_FALSE(cdc_dev->data.out_xfer->actual_num_bytes == data_len, ESP_ERR_INVALID_RESPONSE, unblock, TAG, "Incorrect number of bytes transferred"); - ret = ESP_OK; - -unblock: - xSemaphoreGive(cdc_dev->data.out_mux); - return ret; -} - -esp_err_t cdc_acm_host_line_coding_get(cdc_acm_dev_hdl_t cdc_hdl, cdc_acm_line_coding_t *line_coding) -{ - CDC_ACM_CHECK(line_coding, ESP_ERR_INVALID_ARG); - - ESP_RETURN_ON_ERROR( - send_cdc_request((cdc_dev_t *)cdc_hdl, true, USB_CDC_REQ_GET_LINE_CODING, (uint8_t *)line_coding, sizeof(cdc_acm_line_coding_t), 0), - TAG,); - ESP_LOGD(TAG, "Line Get: Rate: %d, Stop bits: %d, Parity: %d, Databits: %d", line_coding->dwDTERate, - line_coding->bCharFormat, line_coding->bParityType, line_coding->bDataBits); - return ESP_OK; -} - -esp_err_t cdc_acm_host_line_coding_set(cdc_acm_dev_hdl_t cdc_hdl, const cdc_acm_line_coding_t *line_coding) -{ - CDC_ACM_CHECK(line_coding, ESP_ERR_INVALID_ARG); - - ESP_RETURN_ON_ERROR( - send_cdc_request((cdc_dev_t *)cdc_hdl, false, USB_CDC_REQ_SET_LINE_CODING, (uint8_t *)line_coding, sizeof(cdc_acm_line_coding_t), 0), - TAG,); - ESP_LOGD(TAG, "Line Set: Rate: %d, Stop bits: %d, Parity: %d, Databits: %d", line_coding->dwDTERate, - line_coding->bCharFormat, line_coding->bParityType, line_coding->bDataBits); - return ESP_OK; -} - -esp_err_t cdc_acm_host_set_control_line_state(cdc_acm_dev_hdl_t cdc_hdl, bool dtr, bool rts) -{ - const uint16_t ctrl_bitmap = (uint16_t)dtr | ((uint16_t)rts << 1); - - ESP_RETURN_ON_ERROR( - send_cdc_request((cdc_dev_t *)cdc_hdl, false, USB_CDC_REQ_SET_CONTROL_LINE_STATE, NULL, 0, ctrl_bitmap), - TAG,); - ESP_LOGD(TAG, "Control Line Set: DTR: %d, RTS: %d", dtr, rts); - return ESP_OK; -} - -esp_err_t cdc_acm_host_send_break(cdc_acm_dev_hdl_t cdc_hdl, uint16_t duration_ms) -{ - ESP_RETURN_ON_ERROR( - send_cdc_request((cdc_dev_t *)cdc_hdl, false, USB_CDC_REQ_SEND_BREAK, NULL, 0, duration_ms), - TAG,); - - // Block until break is deasserted - vTaskDelay(pdMS_TO_TICKS(duration_ms + 1)); - return ESP_OK; -} - -esp_err_t cdc_acm_host_send_custom_request(cdc_acm_dev_hdl_t cdc_hdl, uint8_t bmRequestType, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, uint16_t wLength, uint8_t *data) -{ - CDC_ACM_CHECK(cdc_hdl, ESP_ERR_INVALID_ARG); - cdc_dev_t *cdc_dev = (cdc_dev_t *)cdc_hdl; - if (wLength > 0) { - CDC_ACM_CHECK(data, ESP_ERR_INVALID_ARG); - } - CDC_ACM_CHECK(cdc_dev->ctrl_transfer->data_buffer_size >= wLength, ESP_ERR_INVALID_SIZE); - - esp_err_t ret; - - // Take Mutex and fill the CTRL request - BaseType_t taken = xSemaphoreTake(cdc_dev->ctrl_mux, pdMS_TO_TICKS(5000)); - if (!taken) { - return ESP_ERR_TIMEOUT; - } - usb_setup_packet_t *req = (usb_setup_packet_t *)(cdc_dev->ctrl_transfer->data_buffer); - uint8_t *start_of_data = (uint8_t *)req + sizeof(usb_setup_packet_t); - req->bmRequestType = bmRequestType; - req->bRequest = bRequest; - req->wValue = wValue; - req->wIndex = wIndex; - req->wLength = wLength; - - // For IN transfers we must transfer data ownership to CDC driver - const bool in_transfer = bmRequestType & USB_BM_REQUEST_TYPE_DIR_IN; - if (!in_transfer) { - memcpy(start_of_data, data, wLength); - } - - cdc_dev->ctrl_transfer->num_bytes = wLength + sizeof(usb_setup_packet_t); - ESP_GOTO_ON_ERROR( - usb_host_transfer_submit_control(p_cdc_acm_obj->cdc_acm_client_hdl, cdc_dev->ctrl_transfer), - unblock, TAG, "CTRL transfer failed"); - - taken = xSemaphoreTake((SemaphoreHandle_t)cdc_dev->ctrl_transfer->context, pdMS_TO_TICKS(5000)); // This is a fixed timeout. Every CDC device should be able to respond to CTRL transfer in 5 seconds - if (!taken) { - // Transfer was not finished, error in USB LIB. Reset the endpoint - cdc_acm_reset_transfer_endpoint(cdc_dev->dev_hdl, cdc_dev->ctrl_transfer); - ret = ESP_ERR_TIMEOUT; - goto unblock; - } - - ESP_GOTO_ON_FALSE(cdc_dev->ctrl_transfer->status == USB_TRANSFER_STATUS_COMPLETED, ESP_ERR_INVALID_RESPONSE, unblock, TAG, "Control transfer error"); - ESP_GOTO_ON_FALSE(cdc_dev->ctrl_transfer->actual_num_bytes == cdc_dev->ctrl_transfer->num_bytes, ESP_ERR_INVALID_RESPONSE, unblock, TAG, "Incorrect number of bytes transferred"); - - // For OUT transfers, we must transfer data ownership to user - if (in_transfer) { - memcpy(data, start_of_data, wLength); - } - ret = ESP_OK; - -unblock: - xSemaphoreGive(cdc_dev->ctrl_mux); - return ret; -} - -static esp_err_t send_cdc_request(cdc_dev_t *cdc_dev, bool in_transfer, cdc_request_code_t request, uint8_t *data, uint16_t data_len, uint16_t value) -{ - CDC_ACM_CHECK(cdc_dev, ESP_ERR_INVALID_ARG); - CDC_ACM_CHECK(cdc_dev->notif.intf_desc, ESP_ERR_NOT_SUPPORTED); - - uint8_t req_type = USB_BM_REQUEST_TYPE_TYPE_CLASS | USB_BM_REQUEST_TYPE_RECIP_INTERFACE; - if (in_transfer) { - req_type |= USB_BM_REQUEST_TYPE_DIR_IN; - } else { - req_type |= USB_BM_REQUEST_TYPE_DIR_OUT; - } - return cdc_acm_host_send_custom_request((cdc_acm_dev_hdl_t) cdc_dev, req_type, request, value, cdc_dev->notif.intf_desc->bInterfaceNumber, data_len, data); -} - -esp_err_t cdc_acm_host_protocols_get(cdc_acm_dev_hdl_t cdc_hdl, cdc_comm_protocol_t *comm, cdc_data_protocol_t *data) -{ - CDC_ACM_CHECK(cdc_hdl, ESP_ERR_INVALID_ARG); - cdc_dev_t *cdc_dev = (cdc_dev_t *)cdc_hdl; - - if (comm != NULL) *comm = cdc_dev->comm_protocol; - if (data != NULL) *data = cdc_dev->data_protocol; - return ESP_OK; -} diff --git a/examples/peripherals/usb/host/cdc/common/cdc_acm_host/include/usb/cdc_acm_host.h b/examples/peripherals/usb/host/cdc/common/cdc_acm_host/include/usb/cdc_acm_host.h deleted file mode 100644 index 952ecb85cb..0000000000 --- a/examples/peripherals/usb/host/cdc/common/cdc_acm_host/include/usb/cdc_acm_host.h +++ /dev/null @@ -1,343 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include -#include "usb/usb_host.h" -#include "usb_types_cdc.h" -#include "esp_err.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct cdc_dev_s *cdc_acm_dev_hdl_t; - -/** - * @brief Line Coding structure - * @see Table 17, USB CDC-PSTN specification rev. 1.2 - */ -typedef struct { - uint32_t dwDTERate; // in bits per second - uint8_t bCharFormat; // 0: 1 stopbit, 1: 1.5 stopbits, 2: 2 stopbits - uint8_t bParityType; // 0: None, 1: Odd, 2: Even, 3: Mark, 4: Space - uint8_t bDataBits; // 5, 6, 7, 8 or 16 -} __attribute__((packed)) cdc_acm_line_coding_t; - -/** - * @brief UART State Bitmap - * @see Table 31, USB CDC-PSTN specification rev. 1.2 - */ -typedef union { - struct { - uint16_t bRxCarrier : 1; // State of receiver carrier detection mechanism of device. This signal corresponds to V.24 signal 109 and RS-232 signal DCD. - uint16_t bTxCarrier : 1; // State of transmission carrier. This signal corresponds to V.24 signal 106 and RS-232 signal DSR. - uint16_t bBreak : 1; // State of break detection mechanism of the device. - uint16_t bRingSignal : 1; // State of ring signal detection of the device. - uint16_t bFraming : 1; // A framing error has occurred. - uint16_t bParity : 1; // A parity error has occurred. - uint16_t bOverRun : 1; // Received data has been discarded due to overrun in the device. - uint16_t reserved : 9; - }; - uint16_t val; -} cdc_acm_uart_state_t; - -/** - * @brief CDC-ACM Device Event types to upper layer - * - */ -typedef enum { - CDC_ACM_HOST_ERROR, - CDC_ACM_HOST_SERIAL_STATE, - CDC_ACM_HOST_NETWORK_CONNECTION, - CDC_ACM_HOST_DEVICE_DISCONNECTED -} cdc_acm_host_dev_event_t; - -/** - * @brief CDC-ACM Device Event data structure - * - */ -typedef struct { - cdc_acm_host_dev_event_t type; - union { - int error; //!< Error code from USB Host - cdc_acm_uart_state_t serial_state; //!< Serial (UART) state - bool network_connected; //!< Network connection event - cdc_acm_dev_hdl_t cdc_hdl; //!< Disconnection event - } data; -} cdc_acm_host_dev_event_data_t; - -/** - * @brief New USB device callback - * - * Provides already opened usb_dev, that will be closed after this callback returns. - * This is useful for peeking device's descriptors, e.g. peeking VID/PID and loading proper driver. - * - * @attention This callback is called from USB Host context, so the CDC device can't be opened here. - */ -typedef void (*cdc_acm_new_dev_callback_t)(usb_device_handle_t usb_dev); - -/** - * @brief Data receive callback type - */ -typedef void (*cdc_acm_data_callback_t)(uint8_t* data, size_t data_len, void *user_arg); - -/** - * @brief Device event callback type - * @see cdc_acm_host_dev_event_data_t - */ -typedef void (*cdc_acm_host_dev_callback_t)(const cdc_acm_host_dev_event_data_t *event, void *user_ctx); - -/** - * @brief Configuration structure of USB Host CDC-ACM driver - * - */ -typedef struct { - size_t driver_task_stack_size; /**< Stack size of the driver's task */ - unsigned driver_task_priority; /**< Priority of the driver's task */ - int xCoreID; /**< Core affinity of the driver's task */ - cdc_acm_new_dev_callback_t new_dev_cb; /**< New USB device connected callback. Can be NULL. */ -} cdc_acm_host_driver_config_t; - -/** - * @brief Configuration structure of CDC-ACM device - * - */ -typedef struct { - uint32_t connection_timeout_ms; /**< Timeout for USB device connection in [ms] */ - size_t out_buffer_size; /**< Maximum size of USB bulk out transfer, set to 0 for read-only devices */ - cdc_acm_host_dev_callback_t event_cb; /**< Device's event callback function. Can be NULL */ - cdc_acm_data_callback_t data_cb; /**< Device's data RX callback function. Can be NULL for write-only devices */ - void *user_arg; /**< User's argument that will be passed to the callbacks */ -} cdc_acm_host_device_config_t; - -/** - * @brief Install CDC-ACM driver - * - * - USB Host Library must already be installed before calling this function (via usb_host_install()) - * - This function should be called before calling any other CDC driver functions - * - * @param[in] driver_config Driver configuration structure. If set to NULL, a default configuration will be used. - * @return esp_err_t - */ -esp_err_t cdc_acm_host_install(const cdc_acm_host_driver_config_t *driver_config); - -/** - * @brief Uninstall CDC-ACM driver - * - * - Users must ensure that all CDC devices must be closed via cdc_acm_host_close() before calling this function - * - * @return esp_err_t - */ -esp_err_t cdc_acm_host_uninstall(void); - -/** - * @brief Open CDC-ACM compliant device - * - * CDC-ACM compliant device must contain either an Interface Association Descriptor or CDC-Union descriptor, - * which are used for the driver's configuration. - * - * @param[in] vid Device's Vendor ID - * @param[in] pid Device's Product ID - * @param[in] interface_idx Index of device's interface used for CDC-ACM communication - * @param[in] dev_config Configuration structure of the device - * @param[out] cdc_hdl_ret CDC device handle - * @return esp_err_t - */ -esp_err_t cdc_acm_host_open(uint16_t vid, uint16_t pid, uint8_t interface_idx, const cdc_acm_host_device_config_t *dev_config, cdc_acm_dev_hdl_t *cdc_hdl_ret); - -/** - * @brief Open CDC-ACM non-compliant device - * - * CDC-ACM non-compliant device acts as CDC-ACM device but doesn't support all its features. - * User must provide the interface index that will be used (zero for non-composite devices). - * - * @param[in] vid Device's Vendor ID - * @param[in] pid Device's Product ID - * @param[in] interface_idx Index of device's interface used for CDC-ACM like communication - * @param[in] dev_config Configuration structure of the device - * @param[out] cdc_hdl_ret CDC device handle - * @return esp_err_t - */ -esp_err_t cdc_acm_host_open_vendor_specific(uint16_t vid, uint16_t pid, uint8_t interface_num, const cdc_acm_host_device_config_t *dev_config, cdc_acm_dev_hdl_t *cdc_hdl_ret); - -/** - * @brief Close CDC device and release its resources - * - * @note All in-flight transfers will be prematurely canceled. - * @param cdc_hdl CDC handle obtained from cdc_acm_host_open() - * @return esp_err_t - */ -esp_err_t cdc_acm_host_close(cdc_acm_dev_hdl_t cdc_hdl); - -/** - * @brief Transmit data - blocking mode - * - * @param cdc_hdl CDC handle obtained from cdc_acm_host_open() - * @param[in] data Data to be sent - * @param[in] data_len Data length - * @param[in] timeout_ms Timeout in [ms] - * @return esp_err_t - */ -esp_err_t cdc_acm_host_data_tx_blocking(cdc_acm_dev_hdl_t cdc_hdl, const uint8_t *data, size_t data_len, uint32_t timeout_ms); - -/** - * @brief SetLineCoding function - * - * @see Chapter 6.3.10, USB CDC-PSTN specification rev. 1.2 - * - * @param cdc_hdl CDC handle obtained from cdc_acm_host_open() - * @param[in] line_coding Line Coding structure - * @return esp_err_t - */ -esp_err_t cdc_acm_host_line_coding_set(cdc_acm_dev_hdl_t cdc_hdl, const cdc_acm_line_coding_t *line_coding); - -/** - * @brief GetLineCoding function - * - * @see Chapter 6.3.11, USB CDC-PSTN specification rev. 1.2 - * - * @param cdc_hdl CDC handle obtained from cdc_acm_host_open() - * @param[out] line_coding Line Coding structure to be filled - * @return esp_err_t - */ -esp_err_t cdc_acm_host_line_coding_get(cdc_acm_dev_hdl_t cdc_hdl, cdc_acm_line_coding_t *line_coding); - -/** - * @brief SetControlLineState function - * - * @see Chapter 6.3.12, USB CDC-PSTN specification rev. 1.2 - * - * @param cdc_hdl CDC handle obtained from cdc_acm_host_open() - * @param[in] dtr Indicates to DCE if DTE is present or not. This signal corresponds to V.24 signal 108/2 and RS-232 signal Data Terminal Ready. - * @param[in] rts Carrier control for half duplex modems. This signal corresponds to V.24 signal 105 and RS-232 signal Request To Send. - * @return esp_err_t - */ -esp_err_t cdc_acm_host_set_control_line_state(cdc_acm_dev_hdl_t cdc_hdl, bool dtr, bool rts); - -/** - * @brief SendBreak function - * - * This function will block until the duration_ms has passed. - * - * @see Chapter 6.3.13, USB CDC-PSTN specification rev. 1.2 - * - * @param cdc_hdl CDC handle obtained from cdc_acm_host_open() - * @param[in] duration_ms Duration of the Break signal in [ms] - * @return esp_err_t - */ -esp_err_t cdc_acm_host_send_break(cdc_acm_dev_hdl_t cdc_hdl, uint16_t duration_ms); - -/** - * @brief Print device's descriptors - * - * Device and full Configuration descriptors are printed in human readable format to stdout. - * - * @param cdc_hdl CDC handle obtained from cdc_acm_host_open() - */ -void cdc_acm_host_desc_print(cdc_acm_dev_hdl_t cdc_hdl); - -/** - * @brief Get protocols defined in USB-CDC interface descriptors - * - * @param cdc_hdl CDC handle obtained from cdc_acm_host_open() - * @param[out] comm Communication protocol - * @param[out] data Data protocol - * @return esp_err_t - */ -esp_err_t cdc_acm_host_protocols_get(cdc_acm_dev_hdl_t cdc_hdl, cdc_comm_protocol_t *comm, cdc_data_protocol_t *data); - -/** - * @brief Send command to CTRL endpoint - * - * Sends Control transfer as described in USB specification chapter 9. - * This function can be used by device drivers that use custom/vendor specific commands. - * These commands can either extend or replace commands defined in USB CDC-PSTN specification rev. 1.2. - * - * @param cdc_hdl CDC handle obtained from cdc_acm_host_open() - * @param[in] bmRequestType Field of USB control request - * @param[in] bRequest Field of USB control request - * @param[in] wValue Field of USB control request - * @param[in] wIndex Field of USB control request - * @param[in] wLength Field of USB control request - * @param[inout] data Field of USB control request - * @return esp_err_t - */ -esp_err_t cdc_acm_host_send_custom_request(cdc_acm_dev_hdl_t cdc_hdl, uint8_t bmRequestType, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, uint16_t wLength, uint8_t *data); - -#ifdef __cplusplus -} -class CdcAcmDevice -{ -public: - // Operators - CdcAcmDevice() : cdc_hdl(NULL){}; - ~CdcAcmDevice() - { - // Close CDC-ACM device, if it wasn't explicitly closed - if (this->cdc_hdl != NULL) { - this->close(); - } - } - - inline esp_err_t tx_blocking(uint8_t *data, size_t len, uint32_t timeout_ms = 100) - { - return cdc_acm_host_data_tx_blocking(this->cdc_hdl, data, len, timeout_ms); - } - - inline esp_err_t open(uint16_t vid, uint16_t pid, uint8_t interface_idx, const cdc_acm_host_device_config_t* dev_config) - { - return cdc_acm_host_open(vid, pid, interface_idx, dev_config, &this->cdc_hdl); - } - - inline esp_err_t open_vendor_specific(uint16_t vid, uint16_t pid, uint8_t interface_idx, const cdc_acm_host_device_config_t* dev_config) - { - return cdc_acm_host_open_vendor_specific(vid, pid, interface_idx, dev_config, &this->cdc_hdl); - } - - inline esp_err_t close() - { - esp_err_t err = cdc_acm_host_close(this->cdc_hdl); - if (err == ESP_OK) { - this->cdc_hdl = NULL; - } - return err; - } - - inline esp_err_t line_coding_get(cdc_acm_line_coding_t *line_coding) - { - return cdc_acm_host_line_coding_get(this->cdc_hdl, line_coding); - } - - inline esp_err_t line_coding_set(cdc_acm_line_coding_t *line_coding) - { - return cdc_acm_host_line_coding_set(this->cdc_hdl, line_coding); - } - - inline esp_err_t set_control_line_state(bool dtr, bool rts) - { - return cdc_acm_host_set_control_line_state(this->cdc_hdl, dtr, rts); - } - - inline esp_err_t send_break(uint16_t duration_ms) - { - return cdc_acm_host_send_break(this->cdc_hdl, duration_ms); - } - - inline esp_err_t send_custom_request(uint8_t bmRequestType, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, uint16_t wLength, uint8_t *data) - { - return cdc_acm_host_send_custom_request(this->cdc_hdl, bmRequestType, bRequest, wValue, wIndex, wLength, data); - } - -private: - CdcAcmDevice(const CdcAcmDevice &Copy); - CdcAcmDevice &operator= (const CdcAcmDevice &Copy); - bool operator== (const CdcAcmDevice ¶m) const; - bool operator!= (const CdcAcmDevice ¶m) const; - cdc_acm_dev_hdl_t cdc_hdl; -}; -#endif diff --git a/examples/peripherals/usb/host/cdc/common/cdc_acm_host/include/usb/usb_types_cdc.h b/examples/peripherals/usb/host/cdc/common/cdc_acm_host/include/usb/usb_types_cdc.h deleted file mode 100644 index bd8b1d07f7..0000000000 --- a/examples/peripherals/usb/host/cdc/common/cdc_acm_host/include/usb/usb_types_cdc.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once -#include - -/** - * @brief USB CDC Descriptor Subtypes - * - * @see Table 13, USB CDC specification rev. 1.2 - */ -typedef enum { - USB_CDC_DESC_SUBTYPE_HEADER = 0x00, // Header Functional Descriptor - USB_CDC_DESC_SUBTYPE_CALL = 0x01, // Call Management Functional Descriptor - USB_CDC_DESC_SUBTYPE_ACM = 0x02, // Abstract Control Management Functional Descriptor - USB_CDC_DESC_SUBTYPE_DLM = 0x03, // Direct Line Management Functional Descriptor - USB_CDC_DESC_SUBTYPE_TEL_RINGER = 0x04, // Telephone Ringer Functional Descriptor - USB_CDC_DESC_SUBTYPE_TEL_CLSR = 0x05, // Telephone Call and Line State Reporting Capabilities Functional Descriptor - USB_CDC_DESC_SUBTYPE_UNION = 0x06, // Union Functional Descriptor - USB_CDC_DESC_SUBTYPE_COUNTRY = 0x07, // Country Selection Functional Descriptor - USB_CDC_DESC_SUBTYPE_TEL_MODE = 0x08, // Telephone Operational Modes Functional Descriptor - USB_CDC_DESC_SUBTYPE_TERMINAL = 0x09, // USB Terminal - USB_CDC_DESC_SUBTYPE_NCHT = 0x0A, // Network Channel Terminal - USB_CDC_DESC_SUBTYPE_PROTOCOL = 0x08, // Protocol Unit - USB_CDC_DESC_SUBTYPE_EXTENSION = 0x0C, // Extension Unit - USB_CDC_DESC_SUBTYPE_MULTI_CHAN = 0x0D, // Multi-Channel Management Functional Descriptor - USB_CDC_DESC_SUBTYPE_CAPI = 0x0E, // CAPI Control - USB_CDC_DESC_SUBTYPE_ETH = 0x0F, // Ethernet Networking - USB_CDC_DESC_SUBTYPE_ATM = 0x10, // ATM Networking - USB_CDC_DESC_SUBTYPE_WHANDSET = 0x11, // Wireless Handset Control Model Functional Descriptor - USB_CDC_DESC_SUBTYPE_MDLM = 0x12, // Mobile Direct Line Model - USB_CDC_DESC_SUBTYPE_MDLM_DETAIL = 0x13, // MDLM Detail - USB_CDC_DESC_SUBTYPE_DMM = 0x14, // Device Management Model - USB_CDC_DESC_SUBTYPE_OBEX = 0x15, // OBEX Functional - USB_CDC_DESC_SUBTYPE_COMMAND_SET = 0x16, // Command Set - USB_CDC_DESC_SUBTYPE_COMMAND_SET_DETAIL = 0x17, // Command Set Detail Functional Descriptor - USB_CDC_DESC_SUBTYPE_TEL_CM = 0x18, // Telephone Control Model Functional Descriptor - USB_CDC_DESC_SUBTYPE_OBEX_SERVICE = 0x19, // OBEX Service Identifier Functional Descriptor - USB_CDC_DESC_SUBTYPE_NCM = 0x1A // NCM Functional Descriptor -} __attribute__((packed)) cdc_desc_subtype_t; - -/** - * @brief USB CDC Subclass codes - * - * @see Table 4, USB CDC specification rev. 1.2 - */ -typedef enum { - USB_CDC_SUBCLASS_DLCM = 0x01, // Direct Line Control Model - USB_CDC_SUBCLASS_ACM = 0x02, // Abstract Control Model - USB_CDC_SUBCLASS_TCM = 0x03, // Telephone Control Model - USB_CDC_SUBCLASS_MCHCM = 0x04, // Multi-Channel Control Model - USB_CDC_SUBCLASS_CAPI = 0x05, // CAPI Control Model - USB_CDC_SUBCLASS_ECM = 0x06, // Ethernet Networking Control Model - USB_CDC_SUBCLASS_ATM = 0x07, // ATM Networking Model - USB_CDC_SUBCLASS_HANDSET = 0x08, // Wireless Handset Control Model - USB_CDC_SUBCLASS_DEV_MAN = 0x09, // Device Management - USB_CDC_SUBCLASS_MOBILE = 0x0A, // Mobile Direct Line Model - USB_CDC_SUBCLASS_OBEX = 0x0B, // OBEX - USB_CDC_SUBCLASS_EEM = 0x0C, // Ethernet Emulation Model - USB_CDC_SUBCLASS_NCM = 0x0D // Network Control Model -} __attribute__((packed)) cdc_subclass_t; - -/** - * @brief USB CDC Communications Protocol Codes - * - * @see Table 5, USB CDC specification rev. 1.2 - */ -typedef enum { - USB_CDC_COMM_PROTOCOL_NONE = 0x00, // No class specific protocol required - USB_CDC_COMM_PROTOCOL_V250 = 0x01, // AT Commands: V.250 etc - USB_CDC_COMM_PROTOCOL_PCAA = 0x02, // AT Commands defined by PCCA-101 - USB_CDC_COMM_PROTOCOL_PCAA_A = 0x03, // AT Commands defined by PCAA-101 & Annex O - USB_CDC_COMM_PROTOCOL_GSM = 0x04, // AT Commands defined by GSM 07.07 - USB_CDC_COMM_PROTOCOL_3GPP = 0x05, // AT Commands defined by 3GPP 27.007 - USB_CDC_COMM_PROTOCOL_TIA = 0x06, // AT Commands defined by TIA for CDMA - USB_CDC_COMM_PROTOCOL_EEM = 0x07, // Ethernet Emulation Model - USB_CDC_COMM_PROTOCOL_EXT = 0xFE, // External Protocol: Commands defined by Command Set Functional Descriptor - USB_CDC_COMM_PROTOCOL_VENDOR = 0xFF // Vendor-specific -} __attribute__((packed)) cdc_comm_protocol_t; - -/** - * @brief USB CDC Data Protocol Codes - * - * @see Table 7, USB CDC specification rev. 1.2 - */ -typedef enum { - USB_CDC_DATA_PROTOCOL_NONE = 0x00, // No class specific protocol required - USB_CDC_DATA_PROTOCOL_NCM = 0x01, // Network Transfer Block - USB_CDC_DATA_PROTOCOL_I430 = 0x30, // Physical interface protocol for ISDN BRI - USB_CDC_DATA_PROTOCOL_HDLC = 0x31, // HDLC - USB_CDC_DATA_PROTOCOL_Q921M = 0x50, // Management protocol for Q.921 data link protocol - USB_CDC_DATA_PROTOCOL_Q921 = 0x51, // Data link protocol for Q.931 - USB_CDC_DATA_PROTOCOL_Q921TM = 0x52, // TEI-multiplexor for Q.921 data link protocol - USB_CDC_DATA_PROTOCOL_V42BIS = 0x90, // Data compression procedures - USB_CDC_DATA_PROTOCOL_Q931 = 0x91, // Euro-ISDN protocol control - USB_CDC_DATA_PROTOCOL_V120 = 0x92, // V.24 rate adaptation to ISDN - USB_CDC_DATA_PROTOCOL_CAPI = 0x93, // CAPI Commands - USB_CDC_DATA_PROTOCOL_VENDOR = 0xFF // Vendor-specific -} __attribute__((packed)) cdc_data_protocol_t; - -/** - * @brief USB CDC Request Codes - * - * @see Table 19, USB CDC specification rev. 1.2 - */ -typedef enum { - USB_CDC_REQ_SEND_ENCAPSULATED_COMMAND = 0x00, - USB_CDC_REQ_GET_ENCAPSULATED_RESPONSE = 0x01, - USB_CDC_REQ_SET_COMM_FEATURE = 0x02, - USB_CDC_REQ_GET_COMM_FEATURE = 0x03, - USB_CDC_REQ_CLEAR_COMM_FEATURE = 0x04, - USB_CDC_REQ_SET_AUX_LINE_STATE = 0x10, - USB_CDC_REQ_SET_HOOK_STATE = 0x11, - USB_CDC_REQ_PULSE_SETUP = 0x12, - USB_CDC_REQ_SEND_PULSE = 0x13, - USB_CDC_REQ_SET_PULSE_TIME = 0x14, - USB_CDC_REQ_RING_AUX_JACK = 0x15, - USB_CDC_REQ_SET_LINE_CODING = 0x20, - USB_CDC_REQ_GET_LINE_CODING = 0x21, - USB_CDC_REQ_SET_CONTROL_LINE_STATE = 0x22, - USB_CDC_REQ_SEND_BREAK = 0x23, - USB_CDC_REQ_SET_RINGER_PARMS = 0x30, - USB_CDC_REQ_GET_RINGER_PARMS = 0x31, - USB_CDC_REQ_SET_OPERATION_PARMS = 0x32, - USB_CDC_REQ_GET_OPERATION_PARMS = 0x33, - USB_CDC_REQ_SET_LINE_PARMS = 0x34, - USB_CDC_REQ_GET_LINE_PARMS = 0x35, - USB_CDC_REQ_DIAL_DIGITS = 0x36, - USB_CDC_REQ_SET_UNIT_PARAMETER = 0x37, - USB_CDC_REQ_GET_UNIT_PARAMETER = 0x38, - USB_CDC_REQ_CLEAR_UNIT_PARAMETER = 0x39, - USB_CDC_REQ_GET_PROFILE = 0x3A, - USB_CDC_REQ_SET_ETHERNET_MULTICAST_FILTERS = 0x40, - USB_CDC_REQ_SET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER = 0x41, - USB_CDC_REQ_GET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER = 0x42, - USB_CDC_REQ_SET_ETHERNET_PACKET_FILTER = 0x43, - USB_CDC_REQ_GET_ETHERNET_STATISTIC = 0x44, - USB_CDC_REQ_SET_ATM_DATA_FORMAT = 0x50, - USB_CDC_REQ_GET_ATM_DEVICE_STATISTICS = 0x51, - USB_CDC_REQ_SET_ATM_DEFAULT_VC = 0x52, - USB_CDC_REQ_GET_ATM_VC_STATISTICS = 0x53, - USB_CDC_REQ_GET_NTB_PARAMETERS = 0x80, - USB_CDC_REQ_GET_NET_ADDRESS = 0x81, - USB_CDC_REQ_SET_NET_ADDRESS = 0x82, - USB_CDC_REQ_GET_NTB_FORMAT = 0x83, - USB_CDC_REQ_SET_NTB_FORMAT = 0x84, - USB_CDC_REQ_GET_NTB_INPUT_SIZE = 0x85, - USB_CDC_REQ_SET_NTB_INPUT_SIZE = 0x86, - USB_CDC_REQ_GET_MAX_DATAGRAM_SIZE = 0x87, - USB_CDC_REQ_SET_MAX_DATAGRAM_SIZE = 0x88, - USB_CDC_REQ_GET_CRC_MODE = 0x89, - USB_CDC_REQ_SET_CRC_MODE = 0x8A -} __attribute__((packed)) cdc_request_code_t; - -/** - * @brief USB CDC Notification Codes - * - * @see Table 20, USB CDC specification rev. 1.2 - */ -typedef enum { - USB_CDC_NOTIF_NETWORK_CONNECTION = 0x00, - USB_CDC_NOTIF_RESPONSE_AVAILABLE = 0x01, - USB_CDC_NOTIF_AUX_JACK_HOOK_STATE = 0x08, - USB_CDC_NOTIF_RING_DETECT = 0x09, - USB_CDC_NOTIF_SERIAL_STATE = 0x20, - USB_CDC_NOTIF_CALL_STATE_CHANGE = 0x28, - USB_CDC_NOTIF_LINE_STATE_CHANGE = 0x29, - USB_CDC_NOTIF_CONNECTION_SPEED_CHANGE = 0x2A -} __attribute__((packed)) cdc_notification_code_t; - -typedef struct { - uint8_t bmRequestType; - cdc_notification_code_t bNotificationCode; - uint16_t wValue; - uint16_t wIndex; - uint16_t wLength; - uint8_t Data[]; -} __attribute__((packed)) cdc_notification_t; - -/** - * @brief USB CDC Header Functional Descriptor - * - * @see Table 15, USB CDC specification rev. 1.2 - */ -typedef struct { - uint8_t bFunctionLength; - const uint8_t bDescriptorType; // Upper nibble: CDC code 0x02, Lower nibble: intf/ep descriptor type 0x04/0x05 - const cdc_desc_subtype_t bDescriptorSubtype; - uint16_t bcdCDC; // CDC version as binary-coded decimal. This driver is written for version 1.2 -} __attribute__((packed)) cdc_header_desc_t; - -/** - * @brief USB CDC Union Functional Descriptor - * - * @see Table 16, USB CDC specification rev. 1.2 - */ -typedef struct { - uint8_t bFunctionLength; - const uint8_t bDescriptorType; // Upper nibble: CDC code 0x02, Lower nibble: intf/ep descriptor type 0x04/0x05 - const cdc_desc_subtype_t bDescriptorSubtype; - const uint8_t bControlInterface; // Master/controlling interface - uint8_t bSubordinateInterface[]; // Slave/subordinate interfaces -} __attribute__((packed)) cdc_union_desc_t; diff --git a/examples/peripherals/usb/host/cdc/common/cdc_acm_host/test/CMakeLists.txt b/examples/peripherals/usb/host/cdc/common/cdc_acm_host/test/CMakeLists.txt deleted file mode 100644 index 0345c55e76..0000000000 --- a/examples/peripherals/usb/host/cdc/common/cdc_acm_host/test/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -idf_component_register(SRCS "test_cdc_acm_host.c" "usb_device.c" - INCLUDE_DIRS "." - REQUIRES cdc_acm_host tinyusb unity) diff --git a/examples/peripherals/usb/host/cdc/common/cdc_acm_host/test/test_cdc_acm_host.c b/examples/peripherals/usb/host/cdc/common/cdc_acm_host/test/test_cdc_acm_host.c deleted file mode 100644 index 1ba2bcf231..0000000000 --- a/examples/peripherals/usb/host/cdc/common/cdc_acm_host/test/test_cdc_acm_host.c +++ /dev/null @@ -1,447 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: CC0-1.0 - */ - -#include "soc/soc_caps.h" -#if SOC_USB_OTG_SUPPORTED - -#include -#include "esp_system.h" -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "esp_log.h" -#include "esp_err.h" - -#include "esp_private/usb_phy.h" -#include "usb/usb_host.h" -#include "usb/cdc_acm_host.h" -#include - -#include "esp_intr_alloc.h" - -#include "unity.h" -#include "soc/usb_wrap_struct.h" - -static uint8_t tx_buf[] = "HELLO"; -static uint8_t tx_buf2[] = "WORLD"; -static int nb_of_responses; -static int nb_of_responses2; -static usb_phy_handle_t phy_hdl = NULL; - -static void force_conn_state(bool connected, TickType_t delay_ticks) -{ - TEST_ASSERT_NOT_EQUAL(NULL, phy_hdl); - if (delay_ticks > 0) { - //Delay of 0 ticks causes a yield. So skip if delay_ticks is 0. - vTaskDelay(delay_ticks); - } - ESP_ERROR_CHECK(usb_phy_action(phy_hdl, (connected) ? USB_PHY_ACTION_HOST_ALLOW_CONN : USB_PHY_ACTION_HOST_FORCE_DISCONN)); -} - -void usb_lib_task(void *arg) -{ - // Initialize the internal USB PHY to connect to the USB OTG peripheral. We manually install the USB PHY for testing - usb_phy_config_t phy_config = { - .controller = USB_PHY_CTRL_OTG, - .target = USB_PHY_TARGET_INT, - .otg_mode = USB_OTG_MODE_HOST, - .otg_speed = USB_PHY_SPEED_UNDEFINED, //In Host mode, the speed is determined by the connected device - .gpio_conf = NULL, - }; - TEST_ASSERT_EQUAL(ESP_OK, usb_new_phy(&phy_config, &phy_hdl)); - // Install USB Host driver. Should only be called once in entire application - const usb_host_config_t host_config = { - .skip_phy_setup = true, - .intr_flags = ESP_INTR_FLAG_LEVEL1, - }; - TEST_ASSERT_EQUAL(ESP_OK, usb_host_install(&host_config)); - printf("USB Host installed\n"); - xTaskNotifyGive(arg); - - bool all_clients_gone = false; - bool all_dev_free = false; - while (!all_clients_gone || !all_dev_free) { - // Start handling system events - uint32_t event_flags; - usb_host_lib_handle_events(portMAX_DELAY, &event_flags); - if (event_flags & USB_HOST_LIB_EVENT_FLAGS_NO_CLIENTS) { - printf("No more clients\n"); - usb_host_device_free_all(); - all_clients_gone = true; - } - if (event_flags & USB_HOST_LIB_EVENT_FLAGS_ALL_FREE) { - printf("All devices freed\n"); - all_dev_free = true; - } - } - - // Clean up USB Host - vTaskDelay(10); // Short delay to allow clients clean-up - TEST_ASSERT_EQUAL(ESP_OK, usb_host_uninstall()); - TEST_ASSERT_EQUAL(ESP_OK, usb_del_phy(phy_hdl)); //Tear down USB PHY - phy_hdl = NULL; - vTaskDelete(NULL); -} - -void test_install_cdc_driver(void) -{ - // Create a task that will handle USB library events - TEST_ASSERT_EQUAL(pdTRUE, xTaskCreatePinnedToCore(usb_lib_task, "usb_lib", 4*4096, xTaskGetCurrentTaskHandle(), 10, NULL, 0)); - ulTaskNotifyTake(false, 1000); - - printf("Installing CDC-ACM driver\n"); - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_install(NULL)); -} - -/* ------------------------------- Callbacks -------------------------------- */ -static void handle_rx(uint8_t *data, size_t data_len, void *arg) -{ - printf("Data received\n"); - nb_of_responses++; - TEST_ASSERT_EQUAL_STRING_LEN(data, arg, data_len); -} - -static void handle_rx2(uint8_t *data, size_t data_len, void *arg) -{ - printf("Data received 2\n"); - nb_of_responses2++; - TEST_ASSERT_EQUAL_STRING_LEN(data, arg, data_len); -} - -static void notif_cb(const cdc_acm_host_dev_event_data_t *event, void *user_ctx) -{ - switch (event->type) { - case CDC_ACM_HOST_ERROR: - printf("Error event %d\n", event->data.error); - break; - case CDC_ACM_HOST_SERIAL_STATE: - break; - case CDC_ACM_HOST_NETWORK_CONNECTION: - break; - case CDC_ACM_HOST_DEVICE_DISCONNECTED: - printf("Disconnection event\n"); - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_close(event->data.cdc_hdl)); - xTaskNotifyGive(user_ctx); - break; - default: - assert(false); - } -} - -static bool new_dev_cb_called = false; -static void new_dev_cb(usb_device_handle_t usb_dev) { - new_dev_cb_called = true; - const usb_config_desc_t *config_desc; - const usb_device_desc_t *device_desc; - - // Get descriptors - TEST_ASSERT_EQUAL(ESP_OK, usb_host_get_device_descriptor(usb_dev, &device_desc)); - TEST_ASSERT_EQUAL(ESP_OK, usb_host_get_active_config_descriptor(usb_dev, &config_desc)); - - printf("New device connected. VID = 0x%04X PID = %04X\n", device_desc->idVendor, device_desc->idProduct); -} - -/* Basic test to check CDC communication: - * open/read/write/close device - * CDC-ACM specific commands: set/get_line_coding, set_control_line_state */ -TEST_CASE("read_write", "[cdc_acm]") -{ - nb_of_responses = 0; - cdc_acm_dev_hdl_t cdc_dev = NULL; - - test_install_cdc_driver(); - - const cdc_acm_host_device_config_t dev_config = { - .connection_timeout_ms = 500, - .out_buffer_size = 64, - .event_cb = notif_cb, - .data_cb = handle_rx, - .user_arg = tx_buf, - }; - - printf("Opening CDC-ACM device\n"); - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_open(0x303A, 0x4002, 0, &dev_config, &cdc_dev)); // 0x303A:0x4002 (TinyUSB Dual CDC device) - TEST_ASSERT_NOT_NULL(cdc_dev); - cdc_acm_host_desc_print(cdc_dev); - vTaskDelay(100); - - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_data_tx_blocking(cdc_dev, tx_buf, sizeof(tx_buf), 1000)); - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_data_tx_blocking(cdc_dev, tx_buf, sizeof(tx_buf), 1000)); - vTaskDelay(100); // Wait until responses are processed - - // We sent two messages, should get two responses - TEST_ASSERT_EQUAL(2, nb_of_responses); - - cdc_acm_line_coding_t line_coding_get; - const cdc_acm_line_coding_t line_coding_set = { - .dwDTERate = 9600, - .bDataBits = 7, - .bParityType = 1, - .bCharFormat = 1, - }; - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_line_coding_set(cdc_dev, &line_coding_set)); - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_line_coding_get(cdc_dev, &line_coding_get)); - TEST_ASSERT_EQUAL_MEMORY(&line_coding_set, &line_coding_get, sizeof(cdc_acm_line_coding_t)); - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_set_control_line_state(cdc_dev, true, false)); - - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_close(cdc_dev)); - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_uninstall()); - - vTaskDelay(20); //Short delay to allow task to be cleaned up -} - -/* Test communication with multiple CDC-ACM devices from one thread */ -TEST_CASE("multiple_devices", "[cdc_acm]") -{ - nb_of_responses = 0; - nb_of_responses2 = 0; - - test_install_cdc_driver(); - - printf("Opening 2 CDC-ACM devices\n"); - cdc_acm_dev_hdl_t cdc_dev1, cdc_dev2; - cdc_acm_host_device_config_t dev_config = { - .connection_timeout_ms = 1000, - .out_buffer_size = 64, - .event_cb = notif_cb, - .data_cb = handle_rx, - .user_arg = tx_buf, - }; - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_open(0x303A, 0x4002, 0, &dev_config, &cdc_dev1)); // 0x303A:0x4002 (TinyUSB Dual CDC device) - dev_config.data_cb = handle_rx2; - dev_config.user_arg = tx_buf2; - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_open(0x303A, 0x4002, 2, &dev_config, &cdc_dev2)); // 0x303A:0x4002 (TinyUSB Dual CDC device) - TEST_ASSERT_NOT_NULL(cdc_dev1); - TEST_ASSERT_NOT_NULL(cdc_dev2); - - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_data_tx_blocking(cdc_dev1, tx_buf, sizeof(tx_buf), 1000)); - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_data_tx_blocking(cdc_dev2, tx_buf2, sizeof(tx_buf2), 1000)); - - vTaskDelay(100); // Wait for RX callbacks - - // We sent two messages, should get two responses - TEST_ASSERT_EQUAL(1, nb_of_responses); - TEST_ASSERT_EQUAL(1, nb_of_responses2); - - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_close(cdc_dev1)); - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_close(cdc_dev2)); - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_uninstall()); - - //Short delay to allow task to be cleaned up - vTaskDelay(20); -} - -#define MULTIPLE_THREADS_TRANSFERS_NUM 5 -#define MULTIPLE_THREADS_TASKS_NUM 4 -void tx_task(void *arg) -{ - cdc_acm_dev_hdl_t cdc_dev = (cdc_acm_dev_hdl_t) arg; - // Send multiple transfers to make sure that some of them will run at the same time - for (int i = 0; i < MULTIPLE_THREADS_TRANSFERS_NUM; i++) { - // BULK endpoints - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_data_tx_blocking(cdc_dev, tx_buf, sizeof(tx_buf), 1000)); - - // CTRL endpoints - cdc_acm_line_coding_t line_coding_get; - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_line_coding_get(cdc_dev, &line_coding_get)); - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_set_control_line_state(cdc_dev, true, false)); - } - vTaskDelete(NULL); -} - -/** - * @brief Multiple threads test - * - * In this test, one CDC device is accessed from multiple threads. - * It has to be opened/closed just once, though. - */ -TEST_CASE("multiple_threads", "[cdc_acm]") -{ - nb_of_responses = 0; - cdc_acm_dev_hdl_t cdc_dev; - test_install_cdc_driver(); - - const cdc_acm_host_device_config_t dev_config = { - .connection_timeout_ms = 5000, - .out_buffer_size = 64, - .event_cb = notif_cb, - .data_cb = handle_rx, - .user_arg = tx_buf, - }; - - printf("Opening CDC-ACM device\n"); - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_open(0x303A, 0x4002, 0, &dev_config, &cdc_dev)); // 0x303A:0x4002 (TinyUSB Dual CDC device) - TEST_ASSERT_NOT_NULL(cdc_dev); - - // Create two tasks that will try to access cdc_dev - for (int i = 0; i < MULTIPLE_THREADS_TASKS_NUM; i++) { - TEST_ASSERT_EQUAL(pdTRUE, xTaskCreate(tx_task, "CDC TX", 4096, cdc_dev, i + 3, NULL)); - } - - // Wait until all tasks finish - vTaskDelay(pdMS_TO_TICKS(500)); - TEST_ASSERT_EQUAL(MULTIPLE_THREADS_TASKS_NUM * MULTIPLE_THREADS_TRANSFERS_NUM, nb_of_responses); - - // Clean-up - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_close(cdc_dev)); - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_uninstall()); - vTaskDelay(20); -} - -/* Test CDC driver reaction to USB device sudden disconnection */ -TEST_CASE("sudden_disconnection", "[cdc_acm]") -{ - test_install_cdc_driver(); - - cdc_acm_dev_hdl_t cdc_dev; - cdc_acm_host_device_config_t dev_config = { - .connection_timeout_ms = 1000, - .out_buffer_size = 64, - .event_cb = notif_cb, - .data_cb = handle_rx - }; - dev_config.user_arg = xTaskGetCurrentTaskHandle(); - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_open(0x303A, 0x4002, 0, &dev_config, &cdc_dev)); - TEST_ASSERT_NOT_NULL(cdc_dev); - - force_conn_state(false, pdMS_TO_TICKS(10)); // Simulate device disconnection - TEST_ASSERT_EQUAL(1, ulTaskNotifyTake(false, pdMS_TO_TICKS(100))); // Notify will succeed only if CDC_ACM_HOST_DEVICE_DISCONNECTED notification was generated - - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_uninstall()); - vTaskDelay(20); //Short delay to allow task to be cleaned up -} - -/** - * @brief CDC-ACM error handling test - * - * There are multiple erroneous scenarios checked in this test: - * - * -# Install CDC-ACM driver without USB Host - * -# Open device without installed driver - * -# Uninstall driver before installing it - * -# Open non-existent device - * -# Open the same device twice - * -# Uninstall driver with open devices - * -# Send data that is too large - * -# Send unsupported CDC request - * -# Write to read-only device - */ -TEST_CASE("error_handling", "[cdc_acm]") -{ - cdc_acm_dev_hdl_t cdc_dev; - cdc_acm_host_device_config_t dev_config = { - .connection_timeout_ms = 500, - .out_buffer_size = 64, - .event_cb = notif_cb, - .data_cb = handle_rx - }; - - // Install CDC-ACM driver without USB Host - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_STATE, cdc_acm_host_install(NULL)); - - // Open device without installed driver - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_STATE, cdc_acm_host_open(0x303A, 0x4002, 0, &dev_config, &cdc_dev)); - - // Uninstall driver before installing it - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_STATE, cdc_acm_host_uninstall()); - - // Properly install USB and CDC drivers - test_install_cdc_driver(); - - // Open non-existent device - TEST_ASSERT_EQUAL(ESP_ERR_NOT_FOUND, cdc_acm_host_open(0x303A, 0x1234, 0, &dev_config, &cdc_dev)); // 0x303A:0x1234 this device is not connected to USB Host - TEST_ASSERT_NULL(cdc_dev); - - // Open regular device - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_open(0x303A, 0x4002, 0, &dev_config, &cdc_dev)); - TEST_ASSERT_NOT_NULL(cdc_dev); - - // Open one CDC-ACM device twice - cdc_acm_dev_hdl_t cdc_dev_test; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_STATE, cdc_acm_host_open(0x303A, 0x4002, 0, &dev_config, &cdc_dev_test)); - TEST_ASSERT_NULL(cdc_dev_test); - - // Uninstall driver with open devices - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_STATE, cdc_acm_host_uninstall()); - - // Send data that is too large and NULL data - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_SIZE, cdc_acm_host_data_tx_blocking(cdc_dev, tx_buf, 1024, 1000)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, cdc_acm_host_data_tx_blocking(cdc_dev, NULL, 10, 1000)); - - // Change mode to read-only and try to write to it - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_close(cdc_dev)); - dev_config.out_buffer_size = 0; // Read-only device - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_open(0x303A, 0x4002, 0, &dev_config, &cdc_dev)); - TEST_ASSERT_NOT_NULL(cdc_dev); - TEST_ASSERT_EQUAL(ESP_ERR_NOT_SUPPORTED, cdc_acm_host_data_tx_blocking(cdc_dev, tx_buf, sizeof(tx_buf), 1000)); - - // Send unsupported CDC request (TinyUSB accepts SendBreak command, eventhough it doesn't support it) - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_send_break(cdc_dev, 100)); - - // Clean-up - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_close(cdc_dev)); - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_uninstall()); - vTaskDelay(20); -} - -TEST_CASE("custom_command", "[cdc_acm]") -{ - test_install_cdc_driver(); - - // Open device with only CTRL endpoint (endpoint no 0) - cdc_acm_dev_hdl_t cdc_dev; - const cdc_acm_host_device_config_t dev_config = { - .connection_timeout_ms = 500, - .out_buffer_size = 0, - .event_cb = notif_cb, - .data_cb = NULL - }; - - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_open(0x303A, 0x4002, 0, &dev_config, &cdc_dev)); - TEST_ASSERT_NOT_NULL(cdc_dev); - - // Corresponds to command: Set Control Line State, DTR on, RTS off - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_send_custom_request(cdc_dev, 0x21, 34, 1, 0, 0, NULL)); - - // Clean-up - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_close(cdc_dev)); - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_uninstall()); - vTaskDelay(20); -} - -TEST_CASE("new_device_connection", "[cdc_acm]") -{ - // Create a task that will handle USB library events - TEST_ASSERT_EQUAL(pdTRUE, xTaskCreatePinnedToCore(usb_lib_task, "usb_lib", 4*4096, xTaskGetCurrentTaskHandle(), 10, NULL, 0)); - ulTaskNotifyTake(false, 1000); - - printf("Installing CDC-ACM driver\n"); - const cdc_acm_host_driver_config_t driver_config = { - .driver_task_priority = 11, - .driver_task_stack_size = 2048, - .xCoreID = 0, - .new_dev_cb = new_dev_cb, - }; - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_install(&driver_config)); - - vTaskDelay(80); - TEST_ASSERT_TRUE_MESSAGE(new_dev_cb_called, "New device callback was not called\n"); - - // Clean-up - TEST_ASSERT_EQUAL(ESP_OK, cdc_acm_host_uninstall()); - vTaskDelay(20); -} - -/* Following test case implements dual CDC-ACM USB device that can be used as mock device for CDC-ACM Host tests */ -void run_usb_dual_cdc_device(void); -TEST_CASE("mock_device_app", "[cdc_acm_device][ignore]") -{ - run_usb_dual_cdc_device(); - while (1) { - vTaskDelay(10); - } -} - -#endif diff --git a/examples/peripherals/usb/host/cdc/common/cdc_acm_host/test/usb_device.c b/examples/peripherals/usb/host/cdc/common/cdc_acm_host/test/usb_device.c deleted file mode 100644 index 86c645e2c7..0000000000 --- a/examples/peripherals/usb/host/cdc/common/cdc_acm_host/test/usb_device.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: CC0-1.0 - */ - -#include -#include "sdkconfig.h" -#include "tinyusb.h" -#include "tusb_cdc_acm.h" - -static uint8_t buf[CONFIG_TINYUSB_CDC_RX_BUFSIZE + 1]; -void tinyusb_cdc_rx_callback(int itf, cdcacm_event_t *event) -{ - size_t rx_size = 0; - /* read and write back */ - ESP_ERROR_CHECK(tinyusb_cdcacm_read(itf, buf, CONFIG_TINYUSB_CDC_RX_BUFSIZE, &rx_size)); - tinyusb_cdcacm_write_queue(itf, buf, rx_size); - tinyusb_cdcacm_write_flush(itf, 0); -} - -static const tusb_desc_device_t cdc_device_descriptor = { - .bLength = sizeof(cdc_device_descriptor), - .bDescriptorType = TUSB_DESC_DEVICE, - .bcdUSB = 0x0200, - .bDeviceClass = TUSB_CLASS_MISC, - .bDeviceSubClass = MISC_SUBCLASS_COMMON, - .bDeviceProtocol = MISC_PROTOCOL_IAD, - .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, - .idVendor = USB_ESPRESSIF_VID, - .idProduct = 0x4002, - .bcdDevice = 0x0100, - .iManufacturer = 0x01, - .iProduct = 0x02, - .iSerialNumber = 0x03, - .bNumConfigurations = 0x01 -}; - -const uint16_t cdc_desc_config_len = TUD_CONFIG_DESC_LEN + 2 * TUD_CDC_DESC_LEN; -static const uint8_t cdc_desc_configuration[] = { - TUD_CONFIG_DESCRIPTOR(1, 4, 0, cdc_desc_config_len, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), - TUD_CDC_DESCRIPTOR(0, 4, 0x81, 8, 0x02, 0x82, 64), - TUD_CDC_DESCRIPTOR(2, 4, 0x83, 8, 0x04, 0x84, 64), -}; - -void run_usb_dual_cdc_device(void) -{ - const tinyusb_config_t tusb_cfg = { - .device_descriptor = &cdc_device_descriptor, - .configuration_descriptor = cdc_desc_configuration - }; - ESP_ERROR_CHECK(tinyusb_driver_install(&tusb_cfg)); - - tinyusb_config_cdcacm_t acm_cfg = { - .usb_dev = TINYUSB_USBDEV_0, - .cdc_port = TINYUSB_CDC_ACM_0, - .rx_unread_buf_sz = 64, - .callback_rx = &tinyusb_cdc_rx_callback, - .callback_rx_wanted_char = NULL, - .callback_line_state_changed = NULL, - .callback_line_coding_changed = NULL - }; - - ESP_ERROR_CHECK(tusb_cdc_acm_init(&acm_cfg)); -#if (CONFIG_TINYUSB_CDC_COUNT > 1) - acm_cfg.cdc_port = TINYUSB_CDC_ACM_1; - ESP_ERROR_CHECK(tusb_cdc_acm_init(&acm_cfg)); -#endif - - printf("USB initialization DONE\n"); -} diff --git a/examples/peripherals/usb/host/msc/components/msc/CMakeLists.txt b/examples/peripherals/usb/host/msc/components/msc/CMakeLists.txt deleted file mode 100644 index 4543217199..0000000000 --- a/examples/peripherals/usb/host/msc/components/msc/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -set(sources src/msc_scsi_bot.c - src/diskio_usb.c - src/msc_host.c - src/msc_host_vfs.c) - -idf_component_register( SRCS ${sources} - INCLUDE_DIRS include - PRIV_INCLUDE_DIRS private_include - REQUIRES usb fatfs vfs ) diff --git a/examples/peripherals/usb/host/msc/components/msc/README.md b/examples/peripherals/usb/host/msc/components/msc/README.md deleted file mode 100644 index 4f722d1fcd..0000000000 --- a/examples/peripherals/usb/host/msc/components/msc/README.md +++ /dev/null @@ -1,32 +0,0 @@ -# USB Host MSC (Mass Storage Class) Driver - -This directory contains an implementation of a USB Mass Storage Class Driver implemented on top of the [USB Host Library](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-reference/peripherals/usb_host.html). - -MSC driver allows access to USB flash drivers using the BOT “Bulk-Only Transport†protocol and the Transparent SCSI command set. - -## Usage - -- First, usb host library has to be initialized by calling `usb_host_install` -- USB Host Library events have to be handled by invoking `usb_host_lib_handle_events` periodically. - In general, an application should spawn a dedicated task handle USB Host Library events. - However, in order to save RAM, an already existing task can also be used to call `usb_host_lib_handle_events`. -- Mass Storage Class driver is installed by calling `usb_msc_install` function along side with configuration. -- Supplied configuration contains user provided callback function invoked whenever MSC device is connected/disconnected - and optional parameters for creating background task handling MSC related events. - Alternatively, user can call `usb_msc_handle_events` function from already existing task. -- After receiving `MSC_DEVICE_CONNECTED` event, user has to install device with `usb_msc_install_device` function, - obtaining MSC device handle. -- USB descriptors can be printed out with `usb_msc_print_descriptors` and general information about MSC device retrieved - with `from usb_msc_get_device_info` function. -- Obtained device handle is then used in helper function `usb_msc_vfs_register` mounting USB Disk to Virtual filesystem. -- At this point, standard C functions for accessing storage (`fopen`, `fwrite`, `fread`, `mkdir` etc.) can be carried out. -- In order to uninstall the whole USB stack, deinitializing counterparts to functions above has to be called in reverse order. - -## Known issues - -- Driver only supports USB 2.0 flash drives using the BOT “Bulk-Only Transport†protocol and the Transparent SCSI command set -- Composite USB devices are not supported - -## Troubleshooting - -After connecting composite USB device, driver prints `COMPOSITE DEVICES UNSUPPORTED` diff --git a/examples/peripherals/usb/host/msc/components/msc/include/msc_host.h b/examples/peripherals/usb/host/msc/components/msc/include/msc_host.h deleted file mode 100644 index 058037649d..0000000000 --- a/examples/peripherals/usb/host/msc/components/msc/include/msc_host.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include -#include -#include "esp_err.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#define ESP_ERR_MSC_HOST_BASE 0x1700 /*!< MSC host error code base */ -#define ESP_ERR_MSC_MOUNT_FAILED (ESP_ERR_MSC_HOST_BASE + 1) /*!< Failed to mount storage */ -#define ESP_ERR_MSC_FORMAT_FAILED (ESP_ERR_MSC_HOST_BASE + 2) /*!< Failed to format storage */ -#define ESP_ERR_MSC_INTERNAL (ESP_ERR_MSC_HOST_BASE + 3) /*!< MSC host internal error */ - -#define MSC_STR_DESC_SIZE 32 - -typedef struct msc_host_device *msc_host_device_handle_t; /**< Handle to a Mass Storage Device */ - -/** - * @brief USB Mass Storage event containing event type and associated device handle. -*/ -typedef struct { - enum { - MSC_DEVICE_CONNECTED, /**< MSC device has been connected to the system.*/ - MSC_DEVICE_DISCONNECTED, /**< MSC device has been disconnected from the system.*/ - } event; - union { - uint8_t address; /**< Address of connected MSC device.*/ - msc_host_device_handle_t handle; /**< MSC device handle to disconnected device.*/ - } device; -} msc_host_event_t; - -/** - * @brief USB Mass Storage event callback. - * - * @param[in] event mass storage event -*/ -typedef void (*msc_host_event_cb_t)(const msc_host_event_t *event, void *arg); - -/** - * @brief MSC configuration structure. -*/ -typedef struct { - bool create_backround_task; /**< When set to true, background task handling usb events is created. - Otherwise user has to periodically call msc_host_handle_events function */ - size_t task_priority; /**< Task priority of crated background task */ - size_t stack_size; /**< Stack size of crated background task */ - BaseType_t core_id; /**< Select core on which background task will run or tskNO_AFFINITY */ - msc_host_event_cb_t callback; /**< Callback invoked when MSC event occurs. Must not be NULL. */ - void *callback_arg; /**< User provided argument passed to callback */ -} msc_host_driver_config_t; - -/** - * @brief MSC device info. -*/ -typedef struct { - uint32_t sector_count; - uint32_t sector_size; - uint16_t idProduct; - uint16_t idVendor; - wchar_t iManufacturer[MSC_STR_DESC_SIZE]; - wchar_t iProduct[MSC_STR_DESC_SIZE]; - wchar_t iSerialNumber[MSC_STR_DESC_SIZE]; -} msc_host_device_info_t; - -/** - * @brief Install USB Host Mass Storage Class driver - * - * @param[in] config configuration structure MSC to create - * @return esp_err_r - */ -esp_err_t msc_host_install(const msc_host_driver_config_t *config); - -/** - * @brief Uninstall Mass Storage Class driver - * @return esp_err_t - */ -esp_err_t msc_host_uninstall(void); - -/** - * @brief Initialization of MSC device. - * - * @param[in] device_address Device address obtained from MSC callback provided upon connection and enumeration - * @param[out] device Mass storage device handle to be used for subsequent calls. - * @return esp_err_t - */ -esp_err_t msc_host_install_device(uint8_t device_address, msc_host_device_handle_t *device); - -/** - * @brief Deinitialization of MSC device. - * - * @param[in] device Device handle obtained from msc_host_install_device function - * @return esp_err_t - */ -esp_err_t msc_host_uninstall_device(msc_host_device_handle_t device); - -/** - * @brief Helper function for reading sector from mass storage device. - * - * @warning This call is not thread safe and should not be combined - * with accesses to storage through file system. - * - * @note Provided sector and size cannot exceed - * sector_count and sector_size obtained from msc_host_device_info_t - * - * @param[in] device Device handle - * @param[in] sector Number of sector to be read - * @param[out] data Buffer into which data will be written - * @param[in] size Number of bytes to be read - * @return esp_err_t - */ -esp_err_t msc_host_read_sector(msc_host_device_handle_t device, size_t sector, void *data, size_t size); - -/** - * @brief Helper function for writing sector to mass storage device. - * - * @warning This call is not thread safe and should not be combined - * with accesses to storare through file system. - * - * @note Provided sector and size cannot exceed - * sector_count and sector_size obtained from msc_host_device_info_t - * - * @param[in] device Device handle - * @param[in] sector Number of sector to be read - * @param[in] data Data to be written to the sector - * @param[in] size Number of bytes to be written - * @return esp_err_t - */ -esp_err_t msc_host_write_sector(msc_host_device_handle_t device, size_t sector, const void *data, size_t size); - -/** - * @brief Handle MSC HOST events. - * - * @param[in] timeout_ms Timeout in miliseconds - * @return esp_err_t - */ -esp_err_t msc_host_handle_events(uint32_t timeout_ms); - -/** - * @brief Gets devices information. - * - * @warning This call is not thread safe and should not be combined - * with accesses to storare through file system. - * - * @param[in] device Handle to device - * @param[out] info Structure to be populated with device info - * @return esp_err_t - */ -esp_err_t msc_host_get_device_info(msc_host_device_handle_t device, msc_host_device_info_t *info); - -/** - * @brief Print configuration descriptor. - * - * @param[in] device Handle of MSC device - * @return esp_err_t - */ -esp_err_t msc_host_print_descriptors(msc_host_device_handle_t device); - -#ifdef __cplusplus -} -#endif //__cplusplus diff --git a/examples/peripherals/usb/host/msc/components/msc/include/msc_host_vfs.h b/examples/peripherals/usb/host/msc/components/msc/include/msc_host_vfs.h deleted file mode 100644 index af9137f9d9..0000000000 --- a/examples/peripherals/usb/host/msc/components/msc/include/msc_host_vfs.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include "esp_vfs_fat.h" -#include "msc_host.h" -#include "esp_err.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct msc_host_vfs *msc_host_vfs_handle_t; /**< VFS handle to attached Mass Storage device */ - -/** - * @brief Register MSC device to Virtual filesystem. - * - * @param[in] device Device handle obtained from MSC callback provided upon initialization - * @param[in] base_path Base VFS path to be used to access file storage - * @param[in] mount_config Mount configuration. - * @param[out] vfs_handle Handle to MSC device associated with registered VFS - * @return esp_err_t - */ -esp_err_t msc_host_vfs_register(msc_host_device_handle_t device, - const char *base_path, - const esp_vfs_fat_mount_config_t *mount_config, - msc_host_vfs_handle_t *vfs_handle); - - -/** - * @brief Unregister MSC device from Virtual filesystem. - * - * @param[in] vfs_handle VFS handle obtained from MSC callback provided upon initialization - * @return esp_err_t - */ -esp_err_t msc_host_vfs_unregister(msc_host_vfs_handle_t vfs_handle); - -#ifdef __cplusplus -} -#endif diff --git a/examples/peripherals/usb/host/msc/components/msc/private_include/diskio_usb.h b/examples/peripherals/usb/host/msc/components/msc/private_include/diskio_usb.h deleted file mode 100644 index 6327d6eee5..0000000000 --- a/examples/peripherals/usb/host/msc/components/msc/private_include/diskio_usb.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Mass storage disk initialization structure - */ -typedef struct { - uint32_t block_size; /**< Block size */ - uint32_t block_count; /**< Block count */ -} usb_disk_t; - -/** - * @brief Register mass storage disk to fat file system - * - * @param[in] pdrv Number of free drive obtained from ff_diskio_get_drive() function - * @param[in] disk usb_disk_t structure - */ -void ff_diskio_register_msc(uint8_t pdrv, usb_disk_t *disk); - -/** - * @brief Obtains number of drive assigned to usb disk upon calling ff_diskio_register_msc() - * - * @param[in] disk usb_disk_t structure - * @return Drive number - */ -uint8_t ff_diskio_get_pdrv_disk(const usb_disk_t *disk); - -#ifdef __cplusplus -} -#endif //__cplusplus diff --git a/examples/peripherals/usb/host/msc/components/msc/private_include/msc_common.h b/examples/peripherals/usb/host/msc/components/msc/private_include/msc_common.h deleted file mode 100644 index a5bed31e1d..0000000000 --- a/examples/peripherals/usb/host/msc/components/msc/private_include/msc_common.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include -#include -#include "esp_err.h" -#include "esp_check.h" -#include "diskio_usb.h" -#include "usb/usb_host.h" -#include "usb/usb_types_stack.h" -#include "freertos/semphr.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -typedef enum { - MSC_EP_OUT, - MSC_EP_IN -} msc_endpoint_t; - -typedef struct { - uint16_t bulk_in_mps; - uint8_t bulk_in_ep; - uint8_t bulk_out_ep; - uint8_t iface_num; -} msc_config_t; - -typedef struct msc_host_device { - STAILQ_ENTRY(msc_host_device) tailq_entry; - usb_transfer_status_t transfer_status; - SemaphoreHandle_t transfer_done; - usb_device_handle_t handle; - usb_transfer_t *xfer; - msc_config_t config; - usb_disk_t disk; -} msc_device_t; - -esp_err_t msc_bulk_transfer(msc_device_t *device_handle, uint8_t *data, size_t size, msc_endpoint_t ep); - -esp_err_t msc_control_transfer(msc_device_t *device_handle, usb_transfer_t *xfer, size_t len); - -#define MSC_GOTO_ON_ERROR(exp) ESP_GOTO_ON_ERROR(exp, fail, TAG, "") - -#define MSC_GOTO_ON_FALSE(exp, err) ESP_GOTO_ON_FALSE( (exp), err, fail, TAG, "" ) - -#define MSC_RETURN_ON_ERROR(exp) ESP_RETURN_ON_ERROR((exp), TAG, "") - -#define MSC_RETURN_ON_FALSE(exp, err) ESP_RETURN_ON_FALSE( (exp), (err), TAG, "") - -#define MSC_RETURN_ON_INVALID_ARG(exp) ESP_RETURN_ON_FALSE((exp) != NULL, ESP_ERR_INVALID_ARG, TAG, "") - -#ifdef __cplusplus -} -#endif diff --git a/examples/peripherals/usb/host/msc/components/msc/private_include/msc_scsi_bot.h b/examples/peripherals/usb/host/msc/components/msc/private_include/msc_scsi_bot.h deleted file mode 100644 index d4ee210347..0000000000 --- a/examples/peripherals/usb/host/msc/components/msc/private_include/msc_scsi_bot.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include -#include "esp_err.h" -#include "msc_common.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -typedef struct { - uint8_t key; - uint8_t code; - uint8_t code_q; -} scsi_sense_data_t; - -esp_err_t scsi_cmd_read10(msc_device_t *device, - uint8_t *data, - uint32_t sector_address, - uint32_t num_sectors, - uint32_t sector_size); - -esp_err_t scsi_cmd_write10(msc_device_t *device, - const uint8_t *data, - uint32_t sector_address, - uint32_t num_sectors, - uint32_t sector_size); - -esp_err_t scsi_cmd_read_capacity(msc_device_t *device, - uint32_t *block_size, - uint32_t *block_count); - -esp_err_t scsi_cmd_sense(msc_device_t *device, scsi_sense_data_t *sense); - -esp_err_t scsi_cmd_unit_ready(msc_device_t *device); - -esp_err_t scsi_cmd_inquiry(msc_device_t *device); - -esp_err_t scsi_cmd_prevent_removal(msc_device_t *device, bool prevent); - -esp_err_t scsi_cmd_mode_sense(msc_device_t *device); - -esp_err_t msc_mass_reset(msc_device_t *device); - -esp_err_t msc_get_max_lun(msc_device_t *device, uint8_t *lun); - -#ifdef __cplusplus -} -#endif diff --git a/examples/peripherals/usb/host/msc/components/msc/src/diskio_usb.c b/examples/peripherals/usb/host/msc/components/msc/src/diskio_usb.c deleted file mode 100644 index 0191f289c9..0000000000 --- a/examples/peripherals/usb/host/msc/components/msc/src/diskio_usb.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "diskio_impl.h" -#include "ffconf.h" -#include "ff.h" -#include "esp_log.h" -#include "diskio_usb.h" -#include "msc_scsi_bot.h" -#include "msc_common.h" -#include "usb/usb_types_stack.h" - -static usb_disk_t *s_disks[FF_VOLUMES] = { NULL }; - -static const char *TAG = "diskio_usb"; - -static DSTATUS usb_disk_initialize (BYTE pdrv) -{ - return RES_OK; -} - -static DSTATUS usb_disk_status (BYTE pdrv) -{ - return RES_OK; -} - -static DRESULT usb_disk_read (BYTE pdrv, BYTE *buff, DWORD sector, UINT count) -{ - assert(pdrv < FF_VOLUMES); - assert(s_disks[pdrv]); - - esp_err_t err; - usb_disk_t *disk = s_disks[pdrv]; - size_t sector_size = disk->block_size; - msc_device_t *dev = __containerof(disk, msc_device_t, disk); - - for (int i = 0; i < count; i++) { - err = scsi_cmd_read10(dev, &buff[i * sector_size], sector + i, 1, sector_size); - if (err != ESP_OK) { - ESP_LOGE(TAG, "scsi_cmd_read10 failed (%d)", err); - return RES_ERROR; - } - - } - - return RES_OK; -} - -static DRESULT usb_disk_write (BYTE pdrv, const BYTE *buff, DWORD sector, UINT count) -{ - assert(pdrv < FF_VOLUMES); - assert(s_disks[pdrv]); - - esp_err_t err; - usb_disk_t *disk = s_disks[pdrv]; - size_t sector_size = disk->block_size; - msc_device_t *dev = __containerof(disk, msc_device_t, disk); - - for (int i = 0; i < count; i++) { - err = scsi_cmd_write10(dev, &buff[i * sector_size], sector + i, 1, sector_size); - if (err != ESP_OK) { - ESP_LOGE(TAG, "scsi_cmd_write10 failed (%d)", err); - return RES_ERROR; - } - - } - return RES_OK; -} - -static DRESULT usb_disk_ioctl (BYTE pdrv, BYTE cmd, void *buff) -{ - assert(pdrv < FF_VOLUMES); - assert(s_disks[pdrv]); - - usb_disk_t *disk = s_disks[pdrv]; - - switch (cmd) { - case CTRL_SYNC: - return RES_OK; - case GET_SECTOR_COUNT: - *((DWORD *) buff) = disk->block_count; - return RES_OK; - case GET_SECTOR_SIZE: - *((WORD *) buff) = disk->block_size; - return RES_OK; - case GET_BLOCK_SIZE: - return RES_ERROR; - } - return RES_ERROR; -} - -void ff_diskio_register_msc(BYTE pdrv, usb_disk_t *disk) -{ - assert(pdrv < FF_VOLUMES); - - static const ff_diskio_impl_t usb_disk_impl = { - .init = &usb_disk_initialize, - .status = &usb_disk_status, - .read = &usb_disk_read, - .write = &usb_disk_write, - .ioctl = &usb_disk_ioctl - }; - s_disks[pdrv] = disk; - ff_diskio_register(pdrv, &usb_disk_impl); -} - -BYTE ff_diskio_get_pdrv_disk(const usb_disk_t *disk) -{ - for (int i = 0; i < FF_VOLUMES; i++) { - if (disk == s_disks[i]) { - return i; - } - } - return 0xff; -} diff --git a/examples/peripherals/usb/host/msc/components/msc/src/msc_host.c b/examples/peripherals/usb/host/msc/components/msc/src/msc_host.c deleted file mode 100644 index 402b4fcf09..0000000000 --- a/examples/peripherals/usb/host/msc/components/msc/src/msc_host.c +++ /dev/null @@ -1,553 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include -#include -#include "esp_log.h" -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "freertos/semphr.h" -#include "usb/usb_host.h" -#include "diskio_usb.h" -#include "msc_common.h" -#include "msc_host.h" -#include "msc_scsi_bot.h" -#include "usb/usb_types_ch9.h" -#include "usb/usb_helpers.h" - -static portMUX_TYPE msc_lock = portMUX_INITIALIZER_UNLOCKED; - -#define MSC_ENTER_CRITICAL() portENTER_CRITICAL(&msc_lock) -#define MSC_EXIT_CRITICAL() portEXIT_CRITICAL(&msc_lock) - -#define MSC_GOTO_ON_FALSE_CRITICAL(exp, err) \ - do { \ - if(!(exp)) { \ - MSC_EXIT_CRITICAL(); \ - ret = err; \ - goto fail; \ - } \ - } while(0) - -#define MSC_RETURN_ON_FALSE_CRITICAL(exp, err) \ - do { \ - if(!(exp)) { \ - MSC_EXIT_CRITICAL(); \ - return err; \ - } \ - } while(0) - -#define WAIT_FOR_READY_TIMEOUT_MS 3000 -#define TAG "USB_MSC" - -#define SCSI_COMMAND_SET 0x06 -#define BULK_ONLY_TRANSFER 0x50 -#define MSC_NO_SENSE 0x00 -#define MSC_NOT_READY 0x02 -#define MSC_UNIT_ATTENTION 0x06 - -typedef struct { - usb_host_client_handle_t client_handle; - msc_host_event_cb_t user_cb; - void *user_arg; - SemaphoreHandle_t all_events_handled; - volatile bool end_client_event_handling; -} msc_driver_t; - -static msc_driver_t *s_msc_driver; - -STAILQ_HEAD(devices, msc_host_device) devices_tailq; - -static const usb_standard_desc_t *next_interface_desc(const usb_standard_desc_t *desc, size_t len, size_t *offset) -{ - return usb_parse_next_descriptor_of_type(desc, len, USB_W_VALUE_DT_INTERFACE, (int *)offset); -} - -static const usb_standard_desc_t *next_endpoint_desc(const usb_standard_desc_t *desc, size_t len, size_t *offset) -{ - return usb_parse_next_descriptor_of_type(desc, len, USB_B_DESCRIPTOR_TYPE_ENDPOINT, (int *)offset); -} - -static const usb_intf_desc_t *find_msc_interface(const usb_config_desc_t *config_desc, size_t *offset) -{ - size_t total_length = config_desc->wTotalLength; - const usb_standard_desc_t *next_desc = (const usb_standard_desc_t *)config_desc; - - next_desc = next_interface_desc(next_desc, total_length, offset); - - while ( next_desc ) { - - const usb_intf_desc_t *ifc_desc = (const usb_intf_desc_t *)next_desc; - - if ( ifc_desc->bInterfaceClass == USB_CLASS_MASS_STORAGE && - ifc_desc->bInterfaceSubClass == SCSI_COMMAND_SET && - ifc_desc->bInterfaceProtocol == BULK_ONLY_TRANSFER ) { - return ifc_desc; - } - - next_desc = next_interface_desc(next_desc, total_length, offset); - }; - return NULL; -} - -/** - * @brief Extracts configuration from configuration descriptor. - * - * @note Passes interface and endpoint descriptors to obtain: - - * - interface number, IN endpoint, OUT endpoint, max. packet size - * - * @param[in] cfg_desc Configuration descriptor - * @param[out] cfg Obtained configuration - * @return esp_err_t - */ -static esp_err_t extract_config_from_descriptor(const usb_config_desc_t *cfg_desc, msc_config_t *cfg) -{ - size_t offset = 0; - size_t total_len = cfg_desc->wTotalLength; - const usb_intf_desc_t *ifc_desc = find_msc_interface(cfg_desc, &offset); - assert(ifc_desc); - const usb_standard_desc_t *next_desc = (const usb_standard_desc_t *)ifc_desc; - const usb_ep_desc_t *ep_desc = NULL; - - cfg->iface_num = ifc_desc->bInterfaceNumber; - - next_desc = next_endpoint_desc(next_desc, total_len, &offset); - MSC_RETURN_ON_FALSE(next_desc, ESP_ERR_NOT_SUPPORTED); - ep_desc = (const usb_ep_desc_t *)next_desc; - - if (ep_desc->bEndpointAddress & 0x80) { - cfg->bulk_in_ep = ep_desc->bEndpointAddress; - cfg->bulk_in_mps = ep_desc->wMaxPacketSize; - } else { - cfg->bulk_out_ep = ep_desc->bEndpointAddress; - } - - next_desc = next_endpoint_desc(next_desc, total_len, &offset); - MSC_RETURN_ON_FALSE(next_desc, ESP_ERR_NOT_SUPPORTED); - ep_desc = (const usb_ep_desc_t *)next_desc; - - if (ep_desc->bEndpointAddress & 0x80) { - cfg->bulk_in_ep = ep_desc->bEndpointAddress; - cfg->bulk_in_mps = ep_desc->wMaxPacketSize; - } else { - cfg->bulk_out_ep = ep_desc->bEndpointAddress; - } - - return ESP_OK; -} - -static esp_err_t msc_deinit_device(msc_device_t *dev, bool install_failed) -{ - MSC_ENTER_CRITICAL(); - MSC_RETURN_ON_FALSE_CRITICAL( dev, ESP_ERR_INVALID_STATE ); - STAILQ_REMOVE(&devices_tailq, dev, msc_host_device, tailq_entry); - MSC_EXIT_CRITICAL(); - - if (dev->transfer_done) { - vSemaphoreDelete(dev->transfer_done); - } - if (install_failed) { - // Error code is unchecked, as it's unknown at what point installation failed. - usb_host_interface_release(s_msc_driver->client_handle, dev->handle, dev->config.iface_num); - usb_host_device_close(s_msc_driver->client_handle, dev->handle); - usb_host_transfer_free(dev->xfer); - } else { - MSC_RETURN_ON_ERROR( usb_host_interface_release(s_msc_driver->client_handle, dev->handle, dev->config.iface_num) ); - MSC_RETURN_ON_ERROR( usb_host_device_close(s_msc_driver->client_handle, dev->handle) ); - MSC_RETURN_ON_ERROR( usb_host_transfer_free(dev->xfer) ); - } - - free(dev); - return ESP_OK; -} - -// Some MSC devices requires to change its internal state from non-ready to ready -static esp_err_t msc_wait_for_ready_state(msc_device_t *dev, size_t timeout_ms) -{ - esp_err_t err; - scsi_sense_data_t sense; - uint32_t trials = MAX(1, timeout_ms / 100); - - do { - err = scsi_cmd_unit_ready(dev); - if (err != ESP_OK) { - MSC_RETURN_ON_ERROR( scsi_cmd_sense(dev, &sense) ); - if (sense.key != MSC_NOT_READY && - sense.key != MSC_UNIT_ATTENTION && - sense.key != MSC_NO_SENSE) { - return ESP_ERR_MSC_INTERNAL; - } - } - vTaskDelay( pdMS_TO_TICKS(100) ); - } while (trials-- && err); - - return err; -} - -static bool is_mass_storage_device(uint8_t dev_addr) -{ - size_t dummy = 0; - bool is_msc_device = false; - usb_device_handle_t device; - const usb_config_desc_t *config_desc; - - if ( usb_host_device_open(s_msc_driver->client_handle, dev_addr, &device) == ESP_OK) { - if ( usb_host_get_active_config_descriptor(device, &config_desc) == ESP_OK ) { - if ( find_msc_interface(config_desc, &dummy) ) { - is_msc_device = true; - } else { - ESP_LOGD(TAG, "Connected USB device is not MSC"); - } - } - usb_host_device_close(s_msc_driver->client_handle, device); - } - - return is_msc_device; -} - -static void event_handler_task(void *arg) -{ - while (1) { - usb_host_client_handle_events(s_msc_driver->client_handle, pdMS_TO_TICKS(50)); - - if (s_msc_driver->end_client_event_handling) { - break; - } - } - usb_host_client_unblock(s_msc_driver->client_handle); - ESP_ERROR_CHECK( usb_host_client_deregister(s_msc_driver->client_handle) ); - xSemaphoreGive(s_msc_driver->all_events_handled); - vTaskDelete(NULL); -} - -static msc_device_t *find_msc_device(usb_device_handle_t device_handle) -{ - msc_host_device_handle_t device; - - STAILQ_FOREACH(device, &devices_tailq, tailq_entry) { - if (device_handle == device->handle) { - return device; - } - } - - return NULL; -} - -static void client_event_cb(const usb_host_client_event_msg_t *event, void *arg) -{ - if (event->event == USB_HOST_CLIENT_EVENT_NEW_DEV) { - if (is_mass_storage_device(event->new_dev.address)) { - const msc_host_event_t msc_event = { - .event = MSC_DEVICE_CONNECTED, - .device.address = event->new_dev.address, - }; - s_msc_driver->user_cb(&msc_event, s_msc_driver->user_arg); - } - } else if (event->event == USB_HOST_CLIENT_EVENT_DEV_GONE) { - msc_device_t *msc_device = find_msc_device(event->dev_gone.dev_hdl); - if (msc_device) { - const msc_host_event_t msc_event = { - .event = MSC_DEVICE_DISCONNECTED, - .device.handle = msc_device, - }; - s_msc_driver->user_cb(&msc_event, s_msc_driver->user_arg); - } - } -} - -esp_err_t msc_host_install(const msc_host_driver_config_t *config) -{ - esp_err_t ret; - - MSC_RETURN_ON_INVALID_ARG(config); - MSC_RETURN_ON_INVALID_ARG(config->callback); - if ( config->create_backround_task ) { - MSC_RETURN_ON_FALSE(config->stack_size != 0, ESP_ERR_INVALID_ARG); - MSC_RETURN_ON_FALSE(config->task_priority != 0, ESP_ERR_INVALID_ARG); - } - MSC_RETURN_ON_FALSE(!s_msc_driver, ESP_ERR_INVALID_STATE); - - msc_driver_t *driver = calloc(1, sizeof(msc_driver_t)); - MSC_RETURN_ON_FALSE(driver, ESP_ERR_NO_MEM); - driver->user_cb = config->callback; - driver->user_arg = config->callback_arg; - - usb_host_client_config_t client_config = { - .async.client_event_callback = client_event_cb, - .async.callback_arg = NULL, - .max_num_event_msg = 10, - }; - - driver->end_client_event_handling = false; - driver->all_events_handled = xSemaphoreCreateBinary(); - MSC_GOTO_ON_FALSE(driver->all_events_handled, ESP_ERR_NO_MEM); - - MSC_GOTO_ON_ERROR( usb_host_client_register(&client_config, &driver->client_handle) ); - - MSC_ENTER_CRITICAL(); - MSC_GOTO_ON_FALSE_CRITICAL(!s_msc_driver, ESP_ERR_INVALID_STATE); - s_msc_driver = driver; - STAILQ_INIT(&devices_tailq); - MSC_EXIT_CRITICAL(); - - if (config->create_backround_task) { - BaseType_t task_created = xTaskCreatePinnedToCore( - event_handler_task, "USB MSC", config->stack_size, - NULL, config->task_priority, NULL, config->core_id); - MSC_GOTO_ON_FALSE(task_created, ESP_ERR_NO_MEM); - } - - return ESP_OK; - -fail: - s_msc_driver = NULL; - usb_host_client_deregister(driver->client_handle); - if (driver->all_events_handled) { - vSemaphoreDelete(driver->all_events_handled); - } - free(driver); - return ret; -} - -esp_err_t msc_host_uninstall(void) -{ - // Make sure msc driver is installed, - // not being uninstalled from other task - // and no msc device is registered - MSC_ENTER_CRITICAL(); - MSC_RETURN_ON_FALSE_CRITICAL( s_msc_driver != NULL, ESP_ERR_INVALID_STATE ); - MSC_RETURN_ON_FALSE_CRITICAL( !s_msc_driver->end_client_event_handling, ESP_ERR_INVALID_STATE ); - MSC_RETURN_ON_FALSE_CRITICAL( STAILQ_EMPTY(&devices_tailq), ESP_ERR_INVALID_STATE ); - s_msc_driver->end_client_event_handling = true; - MSC_EXIT_CRITICAL(); - - xSemaphoreTake(s_msc_driver->all_events_handled, portMAX_DELAY); - vSemaphoreDelete(s_msc_driver->all_events_handled); - free(s_msc_driver); - s_msc_driver = NULL; - return ESP_OK; -} - -esp_err_t msc_host_install_device(uint8_t device_address, msc_host_device_handle_t *msc_device_handle) -{ - esp_err_t ret; - uint32_t block_size, block_count; - const usb_config_desc_t *config_desc; - msc_device_t *msc_device; - uint8_t lun; - size_t transfer_size = 512; // Normally the smallest block size - - MSC_GOTO_ON_FALSE( msc_device = calloc(1, sizeof(msc_device_t)), ESP_ERR_NO_MEM ); - - MSC_ENTER_CRITICAL(); - MSC_GOTO_ON_FALSE_CRITICAL( s_msc_driver, ESP_ERR_INVALID_STATE ); - MSC_GOTO_ON_FALSE_CRITICAL( s_msc_driver->client_handle, ESP_ERR_INVALID_STATE ); - STAILQ_INSERT_TAIL(&devices_tailq, msc_device, tailq_entry); - MSC_EXIT_CRITICAL(); - - MSC_GOTO_ON_FALSE( msc_device->transfer_done = xSemaphoreCreateBinary(), ESP_ERR_NO_MEM); - MSC_GOTO_ON_ERROR( usb_host_device_open(s_msc_driver->client_handle, device_address, &msc_device->handle) ); - MSC_GOTO_ON_ERROR( usb_host_get_active_config_descriptor(msc_device->handle, &config_desc) ); - MSC_GOTO_ON_ERROR( extract_config_from_descriptor(config_desc, &msc_device->config) ); - MSC_GOTO_ON_ERROR( usb_host_transfer_alloc(transfer_size, 0, &msc_device->xfer) ); - MSC_GOTO_ON_ERROR( usb_host_interface_claim(s_msc_driver->client_handle, - msc_device->handle, - msc_device->config.iface_num, 0) ); - - MSC_GOTO_ON_ERROR( msc_get_max_lun(msc_device, &lun) ); - MSC_GOTO_ON_ERROR( scsi_cmd_inquiry(msc_device) ); - MSC_GOTO_ON_ERROR( msc_wait_for_ready_state(msc_device, WAIT_FOR_READY_TIMEOUT_MS) ); - MSC_GOTO_ON_ERROR( scsi_cmd_read_capacity(msc_device, &block_size, &block_count) ); - - // Configuration descriptor size of simple MSC device is 32 bytes. - if (config_desc->wTotalLength != 32) { - ESP_LOGE(TAG, "COMPOSITE DEVICES UNSUPPORTED"); - } - - msc_device->disk.block_size = block_size; - msc_device->disk.block_count = block_count; - - if (block_size > transfer_size) { - usb_transfer_t *larger_xfer; - MSC_GOTO_ON_ERROR( usb_host_transfer_alloc(block_size, 0, &larger_xfer) ); - usb_host_transfer_free(msc_device->xfer); - msc_device->xfer = larger_xfer; - } - - *msc_device_handle = msc_device; - - return ESP_OK; - -fail: - msc_deinit_device(msc_device, true); - return ret; -} - -esp_err_t msc_host_uninstall_device(msc_host_device_handle_t device) -{ - MSC_RETURN_ON_INVALID_ARG(device); - return msc_deinit_device((msc_device_t *)device, false); -} - - -esp_err_t msc_host_read_sector(msc_host_device_handle_t device, size_t sector, void *data, size_t size) -{ - MSC_RETURN_ON_INVALID_ARG(device); - msc_device_t *dev = (msc_device_t *)device; - - return scsi_cmd_read10(dev, data, sector, 1, dev->disk.block_size); -} - -esp_err_t msc_host_write_sector(msc_host_device_handle_t device, size_t sector, const void *data, size_t size) -{ - MSC_RETURN_ON_INVALID_ARG(device); - msc_device_t *dev = (msc_device_t *)device; - - return scsi_cmd_write10(dev, data, sector, 1, dev->disk.block_size); -} - -esp_err_t msc_host_handle_events(uint32_t timeout_ms) -{ - MSC_RETURN_ON_FALSE(s_msc_driver != NULL, ESP_ERR_INVALID_STATE); - - return usb_host_client_handle_events(s_msc_driver->client_handle, timeout_ms); -} - -static esp_err_t msc_read_string_desc(msc_device_t *dev, uint8_t index, wchar_t *str) -{ - if (index == 0) { - // String descriptor not available - str[0] = 0; - return ESP_OK; - } - - usb_transfer_t *xfer = dev->xfer; - USB_SETUP_PACKET_INIT_GET_STR_DESC((usb_setup_packet_t *)xfer->data_buffer, index, 0x409, 64); - MSC_RETURN_ON_ERROR( msc_control_transfer(dev, xfer, USB_SETUP_PACKET_SIZE + 64) ); - - usb_standard_desc_t *desc = (usb_standard_desc_t *)(xfer->data_buffer + USB_SETUP_PACKET_SIZE); - wchar_t *data = (wchar_t *)(xfer->data_buffer + USB_SETUP_PACKET_SIZE + 2); - size_t len = MIN((desc->bLength - USB_STANDARD_DESC_SIZE) / 2, MSC_STR_DESC_SIZE - 1); - - wcsncpy(str, data, len); - str[len] = 0; - - return ESP_OK; -} - -esp_err_t msc_host_get_device_info(msc_host_device_handle_t device, msc_host_device_info_t *info) -{ - MSC_RETURN_ON_INVALID_ARG(device); - MSC_RETURN_ON_INVALID_ARG(info); - - msc_device_t *dev = (msc_device_t *)device; - const usb_device_desc_t *desc; - - MSC_RETURN_ON_ERROR( usb_host_get_device_descriptor(dev->handle, &desc) ); - - info->idProduct = desc->idProduct; - info->idVendor = desc->idVendor; - info->sector_size = dev->disk.block_size; - info->sector_count = dev->disk.block_count; - - MSC_RETURN_ON_ERROR( msc_read_string_desc(dev, desc->iManufacturer, info->iManufacturer) ); - MSC_RETURN_ON_ERROR( msc_read_string_desc(dev, desc->iProduct, info->iProduct) ); - MSC_RETURN_ON_ERROR( msc_read_string_desc(dev, desc->iSerialNumber, info->iSerialNumber) ); - - return ESP_OK; -} - -esp_err_t msc_host_print_descriptors(msc_host_device_handle_t device) -{ - msc_device_t *dev = (msc_device_t *)device; - const usb_device_desc_t *device_desc; - const usb_config_desc_t *config_desc; - MSC_RETURN_ON_ERROR( usb_host_get_device_descriptor(dev->handle, &device_desc) ); - MSC_RETURN_ON_ERROR( usb_host_get_active_config_descriptor(dev->handle, &config_desc) ); - usb_print_device_descriptor(device_desc); - usb_print_config_descriptor(config_desc, NULL); - return ESP_OK; -} - -static void transfer_callback(usb_transfer_t *transfer) -{ - msc_device_t *device = (msc_device_t *)transfer->context; - - if (transfer->status != USB_TRANSFER_STATUS_COMPLETED) { - ESP_LOGE("Transfer failed", "Status %d", transfer->status); - } - - device->transfer_status = transfer->status; - xSemaphoreGive(device->transfer_done); -} - -static esp_err_t wait_for_transfer_done(usb_transfer_t *xfer) -{ - msc_device_t *device = (msc_device_t *)xfer->context; - BaseType_t received = xSemaphoreTake(device->transfer_done, pdMS_TO_TICKS(xfer->timeout_ms)); - - if (received != pdTRUE) { - usb_host_endpoint_halt(xfer->device_handle, xfer->bEndpointAddress); - usb_host_endpoint_flush(xfer->device_handle, xfer->bEndpointAddress); - xSemaphoreTake(device->transfer_done, portMAX_DELAY); - return ESP_ERR_TIMEOUT; - } - - return (device->transfer_status == USB_TRANSFER_STATUS_COMPLETED) ? ESP_OK : ESP_FAIL; -} - -static inline bool is_in_endpoint(uint8_t endpoint) -{ - return endpoint & USB_B_ENDPOINT_ADDRESS_EP_DIR_MASK ? true : false; -} - -esp_err_t msc_bulk_transfer(msc_device_t *device, uint8_t *data, size_t size, msc_endpoint_t ep) -{ - usb_transfer_t *xfer = device->xfer; - MSC_RETURN_ON_FALSE(size <= xfer->data_buffer_size, ESP_ERR_INVALID_SIZE); - uint8_t endpoint = (ep == MSC_EP_IN) ? device->config.bulk_in_ep : device->config.bulk_out_ep; - - if (is_in_endpoint(endpoint)) { - xfer->num_bytes = usb_round_up_to_mps(size, device->config.bulk_in_mps); - } else { - memcpy(xfer->data_buffer, data, size); - xfer->num_bytes = size; - } - - xfer->device_handle = device->handle; - xfer->bEndpointAddress = endpoint; - xfer->callback = transfer_callback; - xfer->timeout_ms = 1000; - xfer->context = device; - - MSC_RETURN_ON_ERROR( usb_host_transfer_submit(xfer) ); - MSC_RETURN_ON_ERROR( wait_for_transfer_done(xfer) ); - - if (is_in_endpoint(endpoint)) { - memcpy(data, xfer->data_buffer, size); - } - - return ESP_OK; -} - -esp_err_t msc_control_transfer(msc_device_t *device, usb_transfer_t *xfer, size_t len) -{ - xfer->device_handle = device->handle; - xfer->bEndpointAddress = 0; - xfer->callback = transfer_callback; - xfer->timeout_ms = 1000; - xfer->num_bytes = len; - xfer->context = device; - - MSC_RETURN_ON_ERROR( usb_host_transfer_submit_control(s_msc_driver->client_handle, xfer)); - return wait_for_transfer_done(xfer); -} diff --git a/examples/peripherals/usb/host/msc/components/msc/src/msc_host_vfs.c b/examples/peripherals/usb/host/msc/components/msc/src/msc_host_vfs.c deleted file mode 100644 index bb45742bd1..0000000000 --- a/examples/peripherals/usb/host/msc/components/msc/src/msc_host_vfs.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include "msc_common.h" -#include "msc_host_vfs.h" -#include "diskio_impl.h" -#include "ffconf.h" -#include "ff.h" - -#define DRIVE_STR_LEN 3 - -typedef struct msc_host_vfs { - char drive[DRIVE_STR_LEN]; - char *base_path; - uint8_t pdrv; -} msc_host_vfs_t; - -static const char *TAG = "MSC VFS"; - -static esp_err_t msc_format_storage(size_t block_size, size_t allocation_size, const char *drv) -{ - void *workbuf = NULL; - const size_t workbuf_size = 4096; - - MSC_RETURN_ON_FALSE( workbuf = ff_memalloc(workbuf_size), ESP_ERR_NO_MEM ); - - // Valid value of cluster size is between sector_size and 128 * sector_size. - size_t cluster_size = MIN(MAX(allocation_size, block_size), 128 * block_size); - const MKFS_PARM opt = {(BYTE)(FM_ANY | FM_SFD), 0, 0, 0, cluster_size}; - FRESULT err = f_mkfs(drv, &opt, workbuf, workbuf_size); - if (err) { - ESP_LOGE(TAG, "Formatting failed with error: %d", err); - free(workbuf); - return ESP_ERR_MSC_FORMAT_FAILED; - } - - free(workbuf); - return ESP_OK; -} - -static void dealloc_msc_vfs(msc_host_vfs_t *vfs) -{ - free(vfs->base_path); - free(vfs); -} - -esp_err_t msc_host_vfs_register(msc_host_device_handle_t device, - const char *base_path, - const esp_vfs_fat_mount_config_t *mount_config, - msc_host_vfs_handle_t *vfs_handle) -{ - MSC_RETURN_ON_INVALID_ARG(device); - MSC_RETURN_ON_INVALID_ARG(base_path); - MSC_RETURN_ON_INVALID_ARG(mount_config); - MSC_RETURN_ON_INVALID_ARG(vfs_handle); - - FATFS *fs = NULL; - BYTE pdrv; - bool diskio_registered = false; - esp_err_t ret = ESP_ERR_MSC_MOUNT_FAILED; - msc_device_t *dev = (msc_device_t *)device; - size_t block_size = dev->disk.block_size; - size_t alloc_size = mount_config->allocation_unit_size; - - msc_host_vfs_t *vfs = calloc(1, sizeof(msc_host_vfs_t)); - MSC_RETURN_ON_FALSE(vfs != NULL, ESP_ERR_NO_MEM); - - MSC_GOTO_ON_ERROR( ff_diskio_get_drive(&pdrv) ); - - ff_diskio_register_msc(pdrv, &dev->disk); - char drive[DRIVE_STR_LEN] = {(char)('0' + pdrv), ':', 0}; - diskio_registered = true; - - strncpy(vfs->drive, drive, DRIVE_STR_LEN); - MSC_GOTO_ON_FALSE( vfs->base_path = strdup(base_path), ESP_ERR_NO_MEM ); - vfs->pdrv = pdrv; - - MSC_GOTO_ON_ERROR( esp_vfs_fat_register(base_path, drive, mount_config->max_files, &fs) ); - - FRESULT fresult = f_mount(fs, drive, 1); - - if ( fresult != FR_OK) { - if (mount_config->format_if_mount_failed && - (fresult == FR_NO_FILESYSTEM || fresult == FR_INT_ERR)) { - MSC_GOTO_ON_ERROR( msc_format_storage(block_size, alloc_size, drive) ); - MSC_GOTO_ON_FALSE( f_mount(fs, drive, 0) == FR_OK, ESP_ERR_MSC_MOUNT_FAILED ); - } else { - goto fail; - } - } - - *vfs_handle = vfs; - return ESP_OK; - -fail: - if (diskio_registered) { - ff_diskio_unregister(pdrv); - } - esp_vfs_fat_unregister_path(base_path); - if(fs) { - f_mount(NULL, drive, 0); - } - dealloc_msc_vfs(vfs); - return ret; -} - -esp_err_t msc_host_vfs_unregister(msc_host_vfs_handle_t vfs_handle) -{ - MSC_RETURN_ON_INVALID_ARG(vfs_handle); - msc_host_vfs_t *vfs = (msc_host_vfs_t *)vfs_handle; - - f_mount(NULL, vfs->drive, 0); - ff_diskio_unregister(vfs->pdrv); - esp_vfs_fat_unregister_path(vfs->base_path); - dealloc_msc_vfs(vfs); - return ESP_OK; -} diff --git a/examples/peripherals/usb/host/msc/components/msc/src/msc_scsi_bot.c b/examples/peripherals/usb/host/msc/components/msc/src/msc_scsi_bot.c deleted file mode 100644 index 2e548f0b9e..0000000000 --- a/examples/peripherals/usb/host/msc/components/msc/src/msc_scsi_bot.c +++ /dev/null @@ -1,434 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include "esp_log.h" -#include -#include -#include -#include -#include "esp_check.h" -#include "esp_log.h" -#include "msc_common.h" -#include "msc_scsi_bot.h" - -#define TAG "USB_MSC_SCSI" - -/* --------------------------- SCSI Definitions ----------------------------- */ -#define CMD_SENSE_VALID_BIT (1 << 7) -#define SCSI_FLAG_DPO (1<<4) -#define SCSI_FLAG_FUA (1<<3) - -#define SCSI_CMD_FORMAT_UNIT 0x04 -#define SCSI_CMD_INQUIRY 0x12 -#define SCSI_CMD_MODE_SELECT 0x55 -#define SCSI_CMD_MODE_SENSE 0x5A -#define SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E -#define SCSI_CMD_READ10 0x28 -#define SCSI_CMD_READ12 0xA8 -#define SCSI_CMD_READ_CAPACITY 0x25 -#define SCSI_CMD_READ_FORMAT_CAPACITIES 0x23 -#define SCSI_CMD_REQUEST_SENSE 0x03 -#define SCSI_CMD_REZERO 0x01 -#define SCSI_CMD_SEEK10 0x2B -#define SCSI_CMD_SEND_DIAGNOSTIC 0x1D -#define SCSI_CMD_START_STOP Unit 0x1B -#define SCSI_CMD_TEST_UNIT_READY 0x00 -#define SCSI_CMD_VERIFY 0x2F -#define SCSI_CMD_WRITE10 0x2A -#define SCSI_CMD_WRITE12 0xAA -#define SCSI_CMD_WRITE_AND_VERIFY 0x2E - -#define IN_DIR CWB_FLAG_DIRECTION_IN -#define OUT_DIR 0 - -#define INQUIRY_VID_SIZE 8 -#define INQUIRY_PID_SIZE 16 -#define INQUIRY_REV_SIZE 4 - -#define CBW_CMD_SIZE(cmd) (sizeof(cmd) - sizeof(msc_cbw_t)) - -#define CBW_BASE_INIT(dir, cbw_len, data_len) \ - .base = { \ - .signature = 0x43425355, \ - .tag = ++cbw_tag, \ - .flags = dir, \ - .lun = 0, \ - .data_length = data_len, \ - .cbw_length = cbw_len, \ - } - -#define FEATURE_SELECTOR_ENDPOINT 0 -#define CSW_SIGNATURE 0x53425355 -#define CBW_SIZE 31 - -#define USB_MASS_REQ_INIT_RESET(ctrl_req_ptr, intf_num) ({ \ - (ctrl_req_ptr)->bmRequestType = USB_BM_REQUEST_TYPE_DIR_OUT | \ - USB_BM_REQUEST_TYPE_TYPE_CLASS | \ - USB_BM_REQUEST_TYPE_RECIP_INTERFACE; \ - (ctrl_req_ptr)->bRequest = 0xFF; \ - (ctrl_req_ptr)->wValue = 0; \ - (ctrl_req_ptr)->wIndex = (intf_num); \ - (ctrl_req_ptr)->wLength = 0; \ -}) - -#define USB_MASS_REQ_INIT_GET_MAX_LUN(ctrl_req_ptr, intf_num) ({ \ - (ctrl_req_ptr)->bmRequestType = USB_BM_REQUEST_TYPE_DIR_IN | \ - USB_BM_REQUEST_TYPE_TYPE_CLASS | \ - USB_BM_REQUEST_TYPE_RECIP_INTERFACE; \ - (ctrl_req_ptr)->bRequest = 0xFE; \ - (ctrl_req_ptr)->wValue = 0; \ - (ctrl_req_ptr)->wIndex = (intf_num); \ - (ctrl_req_ptr)->wLength = 1; \ -}) - -#define USB_SETUP_PACKET_INIT_CLEAR_FEATURE_EP(ctrl_req_ptr, ep_num) ({ \ - (ctrl_req_ptr)->bmRequestType = USB_BM_REQUEST_TYPE_DIR_OUT | \ - USB_BM_REQUEST_TYPE_TYPE_STANDARD | \ - USB_BM_REQUEST_TYPE_RECIP_ENDPOINT; \ - (ctrl_req_ptr)->bRequest = USB_B_REQUEST_CLEAR_FEATURE; \ - (ctrl_req_ptr)->wValue = FEATURE_SELECTOR_ENDPOINT; \ - (ctrl_req_ptr)->wIndex = (ep_num); \ - (ctrl_req_ptr)->wLength = 0; \ -}) - -#define CWB_FLAG_DIRECTION_IN (1<<7) // device -> host - -/** - * @brief Command Block Wrapper structure - */ -typedef struct __attribute__((packed)) -{ - uint32_t signature; - uint32_t tag; - uint32_t data_length; - uint8_t flags; - uint8_t lun; - uint8_t cbw_length; -} msc_cbw_t; - -/** - * @brief Command Status Wrapper structure - */ -typedef struct __attribute__((packed)) -{ - uint32_t signature; - uint32_t tag; - uint32_t dataResidue; - uint8_t status; -} msc_csw_t; - -typedef struct __attribute__((packed)) -{ - msc_cbw_t base; - uint8_t opcode; - uint8_t flags; - uint32_t address; - uint8_t reserved1; - uint16_t length; - uint8_t reserved2[3]; -} cbw_read10_t; - -typedef struct __attribute__((packed)) -{ - msc_cbw_t base; - uint8_t opcode; - uint8_t flags; - uint32_t address; - uint8_t reserved1; - uint16_t length; - uint8_t reserved2[1]; -} cbw_write10_t; - -typedef struct __attribute__((packed)) -{ - msc_cbw_t base; - uint8_t opcode; - uint8_t flags; - uint32_t address; - uint8_t reserved[6]; -} cbw_read_capacity_t; - -typedef struct __attribute__((packed)) -{ - uint32_t block_count; - uint32_t block_size; -} cbw_read_capacity_response_t; - -typedef struct __attribute__((packed)) -{ - msc_cbw_t base; - uint8_t opcode; - uint8_t flags; - uint8_t reserved[10]; -} cbw_unit_ready_t; - -typedef struct __attribute__((packed)) -{ - msc_cbw_t base; - uint8_t opcode; - uint8_t flags; - uint8_t reserved_0[2]; - uint8_t allocation_length; - uint8_t reserved_1[7]; -} cbw_sense_t; - -typedef struct __attribute__((packed)) -{ - uint8_t error_code; - uint8_t reserved_0; - uint8_t sense_key; - uint32_t info; - uint8_t sense_len; - uint32_t reserved_1; - uint8_t sense_code; - uint8_t sense_code_qualifier; - uint32_t reserved_2; -} cbw_sense_response_t; - -typedef struct __attribute__((packed)) -{ - msc_cbw_t base; - uint8_t opcode; - uint8_t flags; - uint8_t page_code; - uint8_t reserved_0; - uint8_t allocation_length; - uint8_t reserved_1[7]; -} cbw_inquiry_t; - -typedef struct __attribute__((packed)) -{ - msc_cbw_t base; - uint8_t opcode; - uint8_t flags; - uint8_t pc_page_code; - uint8_t reserved_1[4]; - uint16_t parameter_list_length; - uint8_t reserved_2[3]; -} mode_sense_t; - -typedef struct __attribute__((packed)) -{ - uint8_t data[8]; -} mode_sense_response_t; - -typedef struct __attribute__((packed)) -{ - msc_cbw_t base; - uint8_t opcode; - uint8_t flags; - uint8_t reserved_1[2]; - uint8_t prevent; - uint8_t reserved_2[7]; -} prevent_allow_medium_removal_t; - -typedef struct __attribute__((packed)) -{ - uint8_t data[36]; -} cbw_inquiry_response_t; - -// Unique number based on which MSC protocol pairs request and response -static uint32_t cbw_tag; - -static esp_err_t check_csw(msc_csw_t *csw, uint32_t tag) -{ - bool csw_ok = csw->signature == CSW_SIGNATURE && csw->tag == tag && - csw->dataResidue == 0 && csw->status == 0; - - if (!csw_ok) { - ESP_LOGD(TAG, "CSW failed: status %d", csw->status); - } - - return csw_ok ? ESP_OK : ESP_FAIL; -} - -static esp_err_t clear_feature(msc_device_t *device, uint8_t endpoint) -{ - usb_device_handle_t dev = device->handle; - usb_transfer_t *xfer = device->xfer; - - MSC_RETURN_ON_ERROR( usb_host_endpoint_clear(dev, endpoint) ); - USB_SETUP_PACKET_INIT_CLEAR_FEATURE_EP((usb_setup_packet_t *)xfer->data_buffer, endpoint); - MSC_RETURN_ON_ERROR( msc_control_transfer(device, xfer, USB_SETUP_PACKET_SIZE) ); - - return ESP_OK; -} - -esp_err_t msc_mass_reset(msc_device_t *device) -{ - usb_transfer_t *xfer = device->xfer; - - USB_MASS_REQ_INIT_RESET((usb_setup_packet_t *)xfer->data_buffer, 0); - MSC_RETURN_ON_ERROR( msc_control_transfer(device, xfer, USB_SETUP_PACKET_SIZE) ); - - return ESP_OK; -} - -esp_err_t msc_get_max_lun(msc_device_t *device, uint8_t *lun) -{ - usb_transfer_t *xfer = device->xfer; - - USB_MASS_REQ_INIT_GET_MAX_LUN((usb_setup_packet_t *)xfer->data_buffer, 0); - MSC_RETURN_ON_ERROR( msc_control_transfer(device, xfer, USB_SETUP_PACKET_SIZE + 1) ); - - *lun = xfer->data_buffer[USB_SETUP_PACKET_SIZE]; - - return ESP_OK; -} - -static esp_err_t bot_execute_command(msc_device_t *device, msc_cbw_t *cbw, void *data, size_t size) -{ - msc_csw_t csw; - msc_endpoint_t ep = (cbw->flags & CWB_FLAG_DIRECTION_IN) ? MSC_EP_IN : MSC_EP_OUT; - - MSC_RETURN_ON_ERROR( msc_bulk_transfer(device, (uint8_t *)cbw, CBW_SIZE, MSC_EP_OUT) ); - - if (data) { - MSC_RETURN_ON_ERROR( msc_bulk_transfer(device, (uint8_t *)data, size, ep) ); - } - - esp_err_t err = msc_bulk_transfer(device, (uint8_t *)&csw, sizeof(msc_csw_t), MSC_EP_IN); - - if (err == ESP_FAIL && device->transfer_status == USB_TRANSFER_STATUS_STALL) { - ESP_RETURN_ON_ERROR( clear_feature(device, MSC_EP_IN), TAG, "Clear feature failed" ); - // Try to read csw again after clearing feature - err = msc_bulk_transfer(device, (uint8_t *)&csw, sizeof(msc_csw_t), MSC_EP_IN); - if (err) { - ESP_RETURN_ON_ERROR( clear_feature(device, MSC_EP_IN), TAG, "Clear feature failed" ); - ESP_RETURN_ON_ERROR( msc_mass_reset(device), TAG, "Mass reset failed" ); - return ESP_FAIL; - } - } - - MSC_RETURN_ON_ERROR(err); - - return check_csw(&csw, cbw->tag); -} - - -esp_err_t scsi_cmd_read10(msc_device_t *device, - uint8_t *data, - uint32_t sector_address, - uint32_t num_sectors, - uint32_t sector_size) -{ - cbw_read10_t cbw = { - CBW_BASE_INIT(IN_DIR, CBW_CMD_SIZE(cbw_read10_t), num_sectors * sector_size), - .opcode = SCSI_CMD_READ10, - .flags = 0, // lun - .address = __builtin_bswap32(sector_address), - .length = __builtin_bswap16(num_sectors), - }; - - return bot_execute_command(device, &cbw.base, data, num_sectors * sector_size); -} - -esp_err_t scsi_cmd_write10(msc_device_t *device, - const uint8_t *data, - uint32_t sector_address, - uint32_t num_sectors, - uint32_t sector_size) -{ - cbw_write10_t cbw = { - CBW_BASE_INIT(OUT_DIR, CBW_CMD_SIZE(cbw_write10_t), num_sectors * sector_size), - .opcode = SCSI_CMD_WRITE10, - .address = __builtin_bswap32(sector_address), - .length = __builtin_bswap16(num_sectors), - }; - - return bot_execute_command(device, &cbw.base, (void *)data, num_sectors * sector_size); -} - -esp_err_t scsi_cmd_read_capacity(msc_device_t *device, uint32_t *block_size, uint32_t *block_count) -{ - cbw_read_capacity_response_t response; - - cbw_read_capacity_t cbw = { - CBW_BASE_INIT(IN_DIR, CBW_CMD_SIZE(cbw_read_capacity_t), sizeof(response)), - .opcode = SCSI_CMD_READ_CAPACITY, - }; - - MSC_RETURN_ON_ERROR( bot_execute_command(device, &cbw.base, &response, sizeof(response)) ); - - *block_count = __builtin_bswap32(response.block_count); - *block_size = __builtin_bswap32(response.block_size); - - return ESP_OK; -} - -esp_err_t scsi_cmd_unit_ready(msc_device_t *device) -{ - cbw_unit_ready_t cbw = { - CBW_BASE_INIT(IN_DIR, CBW_CMD_SIZE(cbw_unit_ready_t), 0), - .opcode = SCSI_CMD_TEST_UNIT_READY, - }; - - return bot_execute_command(device, &cbw.base, NULL, 0); -} - -esp_err_t scsi_cmd_sense(msc_device_t *device, scsi_sense_data_t *sense) -{ - cbw_sense_response_t response; - - cbw_sense_t cbw = { - CBW_BASE_INIT(IN_DIR, CBW_CMD_SIZE(cbw_sense_t), sizeof(response)), - .opcode = SCSI_CMD_REQUEST_SENSE, - .allocation_length = sizeof(response), - }; - - MSC_RETURN_ON_ERROR( bot_execute_command(device, &cbw.base, &response, sizeof(response)) ); - - if (sense->key) { - ESP_LOGD(TAG, "sense_key: 0x%02X, code: 0x%02X, qualifier: 0x%02X", - response.sense_key, response.sense_code, response.sense_code_qualifier); - } - - sense->key = response.sense_key; - sense->code = response.sense_code; - sense->code_q = response.sense_code_qualifier; - - return ESP_OK; -} - -esp_err_t scsi_cmd_inquiry(msc_device_t *device) -{ - cbw_inquiry_response_t response = { 0 }; - - cbw_inquiry_t cbw = { - CBW_BASE_INIT(IN_DIR, CBW_CMD_SIZE(cbw_inquiry_t), sizeof(response)), - .opcode = SCSI_CMD_INQUIRY, - .allocation_length = sizeof(response), - }; - - return bot_execute_command(device, &cbw.base, &response, sizeof(response) ); -} - -esp_err_t scsi_cmd_mode_sense(msc_device_t *device) -{ - mode_sense_response_t response = { 0 }; - - mode_sense_t cbw = { - CBW_BASE_INIT(IN_DIR, CBW_CMD_SIZE(mode_sense_t), sizeof(response)), - .opcode = SCSI_CMD_MODE_SENSE, - .pc_page_code = 0x3F, - .parameter_list_length = sizeof(response), - }; - - return bot_execute_command(device, &cbw.base, &response, sizeof(response) ); -} - -esp_err_t scsi_cmd_prevent_removal(msc_device_t *device, bool prevent) -{ - prevent_allow_medium_removal_t cbw = { - CBW_BASE_INIT(OUT_DIR, CBW_CMD_SIZE(prevent_allow_medium_removal_t), 0), - .opcode = SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL, - .prevent = 1, - }; - - return bot_execute_command(device, &cbw.base, NULL, 0); -} diff --git a/examples/peripherals/usb/host/msc/components/msc/test/CMakeLists.txt b/examples/peripherals/usb/host/msc/components/msc/test/CMakeLists.txt deleted file mode 100644 index 829f046e33..0000000000 --- a/examples/peripherals/usb/host/msc/components/msc/test/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -idf_component_register(SRC_DIRS . - INCLUDE_DIRS . - REQUIRES unity usb msc tinyusb) diff --git a/examples/peripherals/usb/host/msc/components/msc/test/msc_device.c b/examples/peripherals/usb/host/msc/components/msc/test/msc_device.c deleted file mode 100644 index 03dd21020d..0000000000 --- a/examples/peripherals/usb/host/msc/components/msc/test/msc_device.c +++ /dev/null @@ -1,302 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2019 Ha Thach (tinyusb.org) - * - * SPDX-License-Identifier: MIT - * - * SPDX-FileContributor: 2019-2021 Espressif Systems (Shanghai) CO LTD - * - */ - -/* - * The MIT License (MIT) - * - * Copyright (c) 2019 Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - */ - -#include -#include "esp_log.h" -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "tinyusb.h" -#include "test_common.h" -#include "soc/soc_caps.h" - -#if SOC_USB_OTG_SUPPORTED - -#define MASS_STORAGE_CLASS 0x08 -#define SCSI_COMMAND_SET 0x06 -#define BULK_ONLY_TRANSFER 0x50 - -static const char *TAG = "msc_example"; - - -/**** Kconfig driven Descriptor ****/ -static const tusb_desc_device_t device_descriptor = { - .bLength = sizeof(device_descriptor), - .bDescriptorType = TUSB_DESC_DEVICE, - .bcdUSB = 0x0200, - .bDeviceClass = MASS_STORAGE_CLASS, - .bDeviceSubClass = SCSI_COMMAND_SET, - .bDeviceProtocol = BULK_ONLY_TRANSFER, - .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, - .idVendor = USB_ESPRESSIF_VID, - .idProduct = 0x1234, - .bcdDevice = 0x0100, - .iManufacturer = 0x01, - .iProduct = 0x02, - .iSerialNumber = 0x03, - .bNumConfigurations = 0x01 -}; - -const uint16_t msc_desc_config_len = TUD_CONFIG_DESC_LEN + CFG_TUD_MSC * TUD_MSC_DESC_LEN; -static const uint8_t msc_desc_configuration[] = { - TUD_CONFIG_DESCRIPTOR(1, 4, 0, msc_desc_config_len, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), - TUD_MSC_DESCRIPTOR(0, 5, 1, 0x80 | 1, 64), -}; - - -void device_app(void) -{ - ESP_LOGI(TAG, "USB initialization"); - - tinyusb_config_t tusb_cfg = { - .device_descriptor = &device_descriptor, - .configuration_descriptor = msc_desc_configuration - }; - - ESP_ERROR_CHECK(tinyusb_driver_install(&tusb_cfg)); - ESP_LOGI(TAG, "USB initialization DONE"); - - while (1) { - vTaskDelay(100); - } -} - -// whether host does safe-eject -static bool ejected = false; - -// Some MCU doesn't have enough 8KB SRAM to store the whole disk -// We will use Flash as read-only disk with board that has -// CFG_EXAMPLE_MSC_READONLY defined - -uint8_t msc_disk[DISK_BLOCK_NUM][DISK_BLOCK_SIZE] = { - //------------- Block0: Boot Sector -------------// - // byte_per_sector = DISK_BLOCK_SIZE; fat12_sector_num_16 = DISK_BLOCK_NUM; - // sector_per_cluster = 1; reserved_sectors = 1; - // fat_num = 1; fat12_root_entry_num = 16; - // sector_per_fat = 1; sector_per_track = 1; head_num = 1; hidden_sectors = 0; - // drive_number = 0x80; media_type = 0xf8; extended_boot_signature = 0x29; - // filesystem_type = "FAT12 "; volume_serial_number = 0x1234; volume_label = "TinyUSB MSC"; - // FAT magic code at offset 510-511 - { - 0xEB, 0x3C, 0x90, 0x4D, 0x53, 0x44, 0x4F, 0x53, 0x35, 0x2E, 0x30, 0x00, 0x02, 0x01, 0x01, 0x00, - 0x01, 0x10, 0x00, 0x10, 0x00, 0xF8, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x29, 0x34, 0x12, 0x00, 0x00, 'T', 'i', 'n', 'y', 'U', - 'S', 'B', ' ', 'M', 'S', 'C', 0x46, 0x41, 0x54, 0x31, 0x32, 0x20, 0x20, 0x20, 0x00, 0x00, - - // Zero up to 2 last bytes of FAT magic code - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 'F', 'A', 'T', '3', '2', ' ', ' ', ' ', 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0xAA - }, - - //------------- Block1: FAT12 Table -------------// - { - 0xF8, 0xFF, 0xFF, 0xFF, 0x0F // // first 2 entries must be F8FF, third entry is cluster end of readme file - }, - - //------------- Block2: Root Directory -------------// - { - // first entry is volume label - 'T', 'i', 'n', 'y', 'U', 'S', 'B', ' ', 'M', 'S', 'C', 0x08, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4F, 0x6D, 0x65, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - // second entry is readme file - 'R', 'E', 'A', 'D', 'M', 'E', ' ', ' ', 'T', 'X', 'T', 0x20, 0x00, 0xC6, 0x52, 0x6D, - 0x65, 0x43, 0x65, 0x43, 0x00, 0x00, 0x88, 0x6D, 0x65, 0x43, 0x02, 0x00, - sizeof(README_CONTENTS) - 1, 0x00, 0x00, 0x00 // readme's files size (4 Bytes) - }, - - //------------- Block3: Readme Content -------------// - README_CONTENTS -}; - -// Invoked when received SCSI_CMD_INQUIRY -// Application fill vendor id, product id and revision with string up to 8, 16, 4 characters respectively -void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16], uint8_t product_rev[4]) -{ - (void) lun; - - const char vid[] = "TinyUSB"; - const char pid[] = "Mass Storage"; - const char rev[] = "1.0"; - - memcpy(vendor_id, vid, strlen(vid)); - memcpy(product_id, pid, strlen(pid)); - memcpy(product_rev, rev, strlen(rev)); -} - -// Invoked when received Test Unit Ready command. -// return true allowing host to read/write this LUN e.g SD card inserted -bool tud_msc_test_unit_ready_cb(uint8_t lun) -{ - (void) lun; - - // RAM disk is ready until ejected - if (ejected) { - tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x3a, 0x00); - return false; - } - - return true; -} - -// Invoked when received SCSI_CMD_READ_CAPACITY_10 and SCSI_CMD_READ_FORMAT_CAPACITY to determine the disk size -// Application update block count and block size -void tud_msc_capacity_cb(uint8_t lun, uint32_t *block_count, uint16_t *block_size) -{ - (void) lun; - - *block_count = DISK_BLOCK_NUM; - *block_size = DISK_BLOCK_SIZE; -} - -// Invoked when received Start Stop Unit command -// - Start = 0 : stopped power mode, if load_eject = 1 : unload disk storage -// - Start = 1 : active mode, if load_eject = 1 : load disk storage -bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start, bool load_eject) -{ - (void) lun; - (void) power_condition; - - if ( load_eject ) { - if (start) { - // load disk storage - } else { - // unload disk storage - ejected = true; - } - } - - return true; -} - -// Callback invoked when received READ10 command. -// Copy disk's data to buffer (up to bufsize) and return number of copied bytes. -int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void *buffer, uint32_t bufsize) -{ - (void) lun; - - uint8_t const *addr = msc_disk[lba] + offset; - memcpy(buffer, addr, bufsize); - - return bufsize; -} - -// Callback invoked when received WRITE10 command. -// Process data in buffer to disk's storage and return number of written bytes -int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t *buffer, uint32_t bufsize) -{ - (void) lun; - -#ifndef CFG_EXAMPLE_MSC_READONLY - uint8_t *addr = msc_disk[lba] + offset; - memcpy(addr, buffer, bufsize); -#else - (void) lba; (void) offset; (void) buffer; -#endif - - return bufsize; -} - -// Callback invoked when received an SCSI command not in built-in list below -// - READ_CAPACITY10, READ_FORMAT_CAPACITY, INQUIRY, MODE_SENSE6, REQUEST_SENSE -// - READ10 and WRITE10 has their own callbacks -int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void *buffer, uint16_t bufsize) -{ - // read10 & write10 has their own callback and MUST not be handled here - - void const *response = NULL; - uint16_t resplen = 0; - - // most scsi handled is input - bool in_xfer = true; - - switch (scsi_cmd[0]) { - case SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL: - // Host is about to read/write etc ... better not to disconnect disk - resplen = 0; - break; - - default: - // Set Sense = Invalid Command Operation - tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); - - // negative means error -> tinyusb could stall and/or response with failed status - resplen = -1; - break; - } - - // return resplen must not larger than bufsize - if ( resplen > bufsize ) { - resplen = bufsize; - } - - if ( response && (resplen > 0) ) { - if (in_xfer) { - memcpy(buffer, response, resplen); - } else { - // SCSI output - } - } - - return resplen; -} - -#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/examples/peripherals/usb/host/msc/components/msc/test/test_common.h b/examples/peripherals/usb/host/msc/components/msc/test/test_common.h deleted file mode 100644 index 63eb63df34..0000000000 --- a/examples/peripherals/usb/host/msc/components/msc/test/test_common.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: CC0-1.0 - */ -#pragma once - -enum { - // FatFS only allows to format disks with number of blocks greater than 128 - DISK_BLOCK_NUM = 128 + 1, - DISK_BLOCK_SIZE = 512 -}; - -#define README_CONTENTS \ -"This is tinyusb's MassStorage Class demo.\r\n\r\n\ -If you find any bugs or get any questions, feel free to file an\r\n\ -issue at github.com/hathach/tinyusb" - -void device_app(void); diff --git a/examples/peripherals/usb/host/msc/components/msc/test/test_msc.c b/examples/peripherals/usb/host/msc/components/msc/test/test_msc.c deleted file mode 100644 index 1c595b8176..0000000000 --- a/examples/peripherals/usb/host/msc/components/msc/test/test_msc.c +++ /dev/null @@ -1,325 +0,0 @@ - -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: CC0-1.0 - */ - -#include "unity.h" -#include -#include -#include -#include -#include -#include -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "freertos/queue.h" -#include "freertos/semphr.h" -#include "esp_err.h" -#include "esp_log.h" -#include "esp_private/usb_phy.h" -#include "usb/usb_host.h" -#include "msc_host.h" -#include "msc_host_vfs.h" -#include "ffconf.h" -#include "ff.h" -#include "esp_vfs.h" -#include "test_common.h" -#include "soc/usb_wrap_struct.h" -#include "soc/soc_caps.h" - -#if SOC_USB_OTG_SUPPORTED - -static const char *TAG = "APP"; - -#define ESP_OK_ASSERT(exp) TEST_ASSERT_EQUAL(ESP_OK, exp) - -static esp_vfs_fat_mount_config_t mount_config = { - .format_if_mount_failed = false, - .max_files = 3, - .allocation_unit_size = 1024, -}; - -static QueueHandle_t app_queue; -static SemaphoreHandle_t ready_to_deinit_usb; -static msc_host_device_handle_t device; -static msc_host_vfs_handle_t vfs_handle; -static volatile bool waiting_for_sudden_disconnect; -static usb_phy_handle_t phy_hdl = NULL; - -static void force_conn_state(bool connected, TickType_t delay_ticks) -{ - TEST_ASSERT(phy_hdl); - if (delay_ticks > 0) { - //Delay of 0 ticks causes a yield. So skip if delay_ticks is 0. - vTaskDelay(delay_ticks); - } - ESP_ERROR_CHECK(usb_phy_action(phy_hdl, (connected) ? USB_PHY_ACTION_HOST_ALLOW_CONN : USB_PHY_ACTION_HOST_FORCE_DISCONN)); -} - -static void msc_event_cb(const msc_host_event_t *event, void *arg) -{ - if (waiting_for_sudden_disconnect) { - waiting_for_sudden_disconnect = false; - TEST_ASSERT_EQUAL(MSC_DEVICE_DISCONNECTED, event->event); - } - - if (event->event == MSC_DEVICE_CONNECTED) { - printf("MSC_DEVICE_CONNECTED\n"); - } else { - printf("MSC_DEVICE_DISCONNECTED\n"); - } - - xQueueSend(app_queue, event, 10); -} - -static const char *TEST_STRING = "Hello World!"; -static const char *FILE_NAME = "/usb/ESP32.txt"; - -static void write_read_file(const char *file_path) -{ - char line[64]; - - ESP_LOGI(TAG, "Writing file"); - FILE *f = fopen(file_path, "w"); - TEST_ASSERT(f); - fprintf(f, TEST_STRING); - fclose(f); - - ESP_LOGI(TAG, "Reading file"); - TEST_ASSERT(fopen(file_path, "r")); - fgets(line, sizeof(line), f); - fclose(f); - // strip newline - char *pos = strchr(line, '\n'); - if (pos) { - *pos = '\0'; - } - TEST_ASSERT_EQUAL_STRING(line, TEST_STRING); - ESP_LOGI(TAG, "Done"); -} - -static bool file_exists(const char *file_path) -{ - return ( access(file_path, F_OK) == 0 ); -} - -// Handles common USB host library events -static void handle_usb_events(void *args) -{ - uint32_t end_flags = 0; - - while (1) { - uint32_t event_flags; - usb_host_lib_handle_events(portMAX_DELAY, &event_flags); - // Release devices once all clients has deregistered - if (event_flags & USB_HOST_LIB_EVENT_FLAGS_NO_CLIENTS) { - printf("USB_HOST_LIB_EVENT_FLAGS_NO_CLIENTS\n"); - usb_host_device_free_all(); - end_flags |= 1; - } - // Give ready_to_deinit_usb semaphore to indicate that USB Host library - // can be deinitialized, and terminate this task. - if (event_flags & USB_HOST_LIB_EVENT_FLAGS_ALL_FREE) { - printf("USB_HOST_LIB_EVENT_FLAGS_ALL_FREE\n"); - end_flags |= 2; - } - - if (end_flags == 3) { - xSemaphoreGive(ready_to_deinit_usb); - break; - } - } - vTaskDelete(NULL); -} - -static void check_file_content(const char *file_path, const char *expected) -{ - ESP_LOGI(TAG, "Reading %s:", file_path); - FILE *file = fopen(file_path, "r"); - TEST_ASSERT(file) - - char content[200]; - fread(content, 1, sizeof(content), file); - TEST_ASSERT_EQUAL_STRING(content, expected); - fclose(file); -} - -static void check_sudden_disconnect(void) -{ - uint8_t data[512]; - const size_t DATA_SIZE = sizeof(data); - - ESP_LOGI(TAG, "Creating test.tx"); - FILE *file = fopen("/usb/test.txt", "w"); - TEST_ASSERT(file); - - ESP_LOGI(TAG, "Write data"); - TEST_ASSERT_EQUAL(DATA_SIZE, fwrite(data, 1, DATA_SIZE, file)); - TEST_ASSERT_EQUAL(DATA_SIZE, fwrite(data, 1, DATA_SIZE, file)); - TEST_ASSERT_EQUAL(0, fflush(file)); - - ESP_LOGI(TAG, "Trigger a disconnect"); - //Trigger a disconnect - waiting_for_sudden_disconnect = true; - force_conn_state(false, 0); - - // Make sure flag was leared in callback - vTaskDelay( pdMS_TO_TICKS(100) ); - TEST_ASSERT_FALSE(waiting_for_sudden_disconnect); - - ESP_LOGI(TAG, "Write data after disconnect"); - TEST_ASSERT_NOT_EQUAL( DATA_SIZE, fwrite(data, 1, DATA_SIZE, file)); - - fclose(file); -} - -static void msc_setup(void) -{ - BaseType_t task_created; - - ready_to_deinit_usb = xSemaphoreCreateBinary(); - - TEST_ASSERT( app_queue = xQueueCreate(5, sizeof(msc_host_event_t)) ); - - //Initialize the internal USB PHY to connect to the USB OTG peripheral. We manually install the USB PHY for testing - usb_phy_config_t phy_config = { - .controller = USB_PHY_CTRL_OTG, - .target = USB_PHY_TARGET_INT, - .otg_mode = USB_OTG_MODE_HOST, - .otg_speed = USB_PHY_SPEED_UNDEFINED, //In Host mode, the speed is determined by the connected device - .gpio_conf = NULL, - }; - ESP_OK_ASSERT(usb_new_phy(&phy_config, &phy_hdl)); - const usb_host_config_t host_config = { - .skip_phy_setup = true, - .intr_flags = ESP_INTR_FLAG_LEVEL1, - }; - ESP_OK_ASSERT( usb_host_install(&host_config) ); - - task_created = xTaskCreatePinnedToCore(handle_usb_events, "usb_events", 2048, NULL, 2, NULL, 0); - TEST_ASSERT(task_created); - - const msc_host_driver_config_t msc_config = { - .create_backround_task = true, - .callback = msc_event_cb, - .stack_size = 4096, - .task_priority = 5, - }; - ESP_OK_ASSERT( msc_host_install(&msc_config) ); - - ESP_LOGI(TAG, "Waiting for USB stick to be connected"); - msc_host_event_t app_event; - xQueueReceive(app_queue, &app_event, portMAX_DELAY); - TEST_ASSERT_EQUAL(MSC_DEVICE_CONNECTED, app_event.event); - uint8_t device_addr = app_event.device.address; - - ESP_OK_ASSERT( msc_host_install_device(device_addr, &device) ); - ESP_OK_ASSERT( msc_host_vfs_register(device, "/usb", &mount_config, &vfs_handle) ); -} - -static void msc_teardown(void) -{ - // Wait to finish any ongoing USB operations - vTaskDelay(100); - - ESP_OK_ASSERT( msc_host_vfs_unregister(vfs_handle) ); - ESP_OK_ASSERT( msc_host_uninstall_device(device) ); - ESP_OK_ASSERT( msc_host_uninstall() ); - - xSemaphoreTake(ready_to_deinit_usb, portMAX_DELAY); - vSemaphoreDelete(ready_to_deinit_usb); - ESP_OK_ASSERT( usb_host_uninstall() ); - //Tear down USB PHY - ESP_OK_ASSERT(usb_del_phy(phy_hdl)); - phy_hdl = NULL; - - vQueueDelete(app_queue); -} - -static void write_read_sectors(void) -{ - uint8_t write_data[DISK_BLOCK_SIZE]; - uint8_t read_data[DISK_BLOCK_SIZE]; - - memset(write_data, 0x55, DISK_BLOCK_SIZE); - memset(read_data, 0, DISK_BLOCK_SIZE); - - msc_host_write_sector(device, 10, write_data, DISK_BLOCK_SIZE); - msc_host_read_sector(device, 10, read_data, DISK_BLOCK_SIZE); - - TEST_ASSERT_EQUAL_MEMORY(write_data, read_data, DISK_BLOCK_SIZE); -} - -static void erase_storage(void) -{ - uint8_t data[DISK_BLOCK_SIZE]; - memset(data, 0xFF, DISK_BLOCK_SIZE); - - for (int block = 0; block < DISK_BLOCK_NUM; block++) { - msc_host_write_sector(device, block, data, DISK_BLOCK_SIZE); - } -} - -TEST_CASE("write_and_read_file", "[usb_msc]") -{ - msc_setup(); - write_read_file(FILE_NAME); - msc_teardown(); -} - -TEST_CASE("sudden_disconnect", "[usb_msc]") -{ - msc_setup(); - check_sudden_disconnect(); - msc_teardown(); -} - -TEST_CASE("sectors_can_be_written_and_read", "[usb_msc]") -{ - msc_setup(); - write_read_sectors(); - msc_teardown(); -} - -TEST_CASE("check_README_content", "[usb_msc]") -{ - msc_setup(); - check_file_content("/usb/README.TXT", README_CONTENTS); - msc_teardown(); -} - -/** - * @brief USB MSC format testcase - * @attention This testcase deletes all content on the USB MSC device. - * The device must be reset in order to contain the FILE_NAME again. - */ -TEST_CASE("can_be_formated", "[usb_msc]") -{ - printf("Create file\n"); - msc_setup(); - write_read_file(FILE_NAME); - msc_teardown(); - - printf("File exists after mounting again\n"); - msc_setup(); - TEST_ASSERT(file_exists(FILE_NAME)); - printf("Erase storage device\n"); - erase_storage(); - msc_teardown(); - - printf("Check file does not exist after formatting\n"); - mount_config.format_if_mount_failed = true; - msc_setup(); - TEST_ASSERT_FALSE(file_exists(FILE_NAME)); - msc_teardown(); - mount_config.format_if_mount_failed = false; -} - -TEST_CASE("mock_device_app", "[usb_msc_device][ignore]") -{ - device_app(); -} - -#endif diff --git a/examples/peripherals/usb/host/msc/main/CMakeLists.txt b/examples/peripherals/usb/host/msc/main/CMakeLists.txt index 94b145cd8f..e4e3bca4b3 100644 --- a/examples/peripherals/usb/host/msc/main/CMakeLists.txt +++ b/examples/peripherals/usb/host/msc/main/CMakeLists.txt @@ -1,4 +1,3 @@ idf_component_register(SRCS "msc_example_main.c" INCLUDE_DIRS "" - REQUIRES usb msc fatfs vfs) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") + REQUIRES usb vfs) diff --git a/examples/peripherals/usb/host/msc/main/idf_component.yml b/examples/peripherals/usb/host/msc/main/idf_component.yml new file mode 100644 index 0000000000..57f225551e --- /dev/null +++ b/examples/peripherals/usb/host/msc/main/idf_component.yml @@ -0,0 +1,4 @@ +## IDF Component Manager Manifest File +dependencies: + idf: ">=4.4" + usb_host_msc: "^1.0.0" diff --git a/examples/peripherals/usb/host/msc/main/msc_example_main.c b/examples/peripherals/usb/host/msc/main/msc_example_main.c index f7e4abc875..c37107a39d 100644 --- a/examples/peripherals/usb/host/msc/main/msc_example_main.c +++ b/examples/peripherals/usb/host/msc/main/msc_example_main.c @@ -16,7 +16,6 @@ #include "msc_host.h" #include "msc_host_vfs.h" #include "ffconf.h" -#include "ff.h" #include "esp_vfs.h" #include "errno.h" #include "hal/usb_hal.h" @@ -57,8 +56,8 @@ static void print_device_info(msc_host_device_info_t *info) printf("Device info:\n"); printf("\t Capacity: %llu MB\n", capacity); - printf("\t Sector size: %u\n", info->sector_size); - printf("\t Sector count: %u\n", info->sector_count); + printf("\t Sector size: %"PRIu32"\n", info->sector_size); + printf("\t Sector count: %"PRIu32"\n", info->sector_count); printf("\t PID: 0x%4X \n", info->idProduct); printf("\t VID: 0x%4X \n", info->idVendor); wprintf(L"\t iProduct: %S \n", info->iProduct); @@ -161,7 +160,7 @@ void app_main(void) BaseType_t task_created; const gpio_config_t input_pin = { - .pin_bit_mask = (1 << USB_DISCONNECT_PIN), + .pin_bit_mask = BIT64(USB_DISCONNECT_PIN), .mode = GPIO_MODE_INPUT, .pull_up_en = GPIO_PULLUP_ENABLE, }; diff --git a/examples/peripherals/usb/host/uvc/CMakeLists.txt b/examples/peripherals/usb/host/uvc/CMakeLists.txt new file mode 100644 index 0000000000..e85e1a8712 --- /dev/null +++ b/examples/peripherals/usb/host/uvc/CMakeLists.txt @@ -0,0 +1,8 @@ +# The following lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +set(EXTRA_COMPONENT_DIRS $ENV{IDF_PATH}/examples/common_components/protocol_examples_common) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(usb-uvc) diff --git a/examples/peripherals/usb/host/uvc/README.md b/examples/peripherals/usb/host/uvc/README.md new file mode 100644 index 0000000000..3fd8e0cfaa --- /dev/null +++ b/examples/peripherals/usb/host/uvc/README.md @@ -0,0 +1,199 @@ +| Supported Targets | ESP32-S2 | ESP32-S3 | +| ----------------- | -------- | -------- | + +# USB Camera Example + +## Overview + +This example demonstrates how to: + +- Capture video from a USB camera using the `libuvc` library. +- Stream the video over WiFi by hosting a TCP server. + +The example enumerates connected camera, negotiates selected resolution together with `FPS` and starts capturing video. +`frame_callback` function is then invoked after receiving each frame. User can process received frame according to his needs. + +Optionally, captured video can be visualized on computer with help of `player.py` script located in this example. +After setting `Enable streaming` menuconfig option, example will create TCP server upon start, and wait until `player.py` connects to server. +Once connection is established, example streams each received frame to computer for visualization. + +**Notice** that `libuvc` selects highest possible `dwMaxPayloadTransferSize` by default, so example has to manually overwrite this value to 512 bytes (maximum transfer size supported by ESP32-S2/S3). + +(See the README.md file in the upper level 'examples' directory for more information about examples.) + +## How to Use Example + +### Hardware Required + +This example requires any ESP32-S2 or ESP32-S3 with external PSRAM and exposed USB connector attached to USB camera. +*ESP module without external PSRAM will fail to initialize* + +### Configure the project + +Following configuration is needed for streaming video: + +Open the project configuration menu (`idf.py menuconfig`). + +In the `Example Connection Configuration` menu: + +* Set the Wi-Fi configuration. + * Set `WiFi SSID`. + * Set `WiFi Password`. + +In the `Example Configuration` menu: + +* Set the Example configuration + * `Enable streaming` + +Optional: If you need, change the other options according to your requirements. + +Additionally, `player.py` python script makes use of `opencv-python` and `numpy` packages, +not included in `idf-env` environment. Run following commands to install: +* `pip install opencv-python` +* `pip install numpy` + +### Build and Flash + +Build the project and flash it to the board, then run the monitor tool to view the serial output: + +Run `idf.py set-target esp32s2` to set target chip. + +Run `idf.py -p PORT flash monitor` to build, flash and monitor the project. + +(To exit the serial monitor, type ``Ctrl-]``.) + +See the Getting Started Guide for all the steps to configure and use the ESP-IDF to build projects. + +## Known limitations + +Having only Full Speed USB peripheral and hardware limited MPS (maximum packet size) to 512 bytes, ESP32-S2/S3 is capable of reading about 0.5 MB of data per second. When connected to Full Speed USB host, cameras normally provide resolution no larger than 640x480 pixels. +Following two supported formats are the most common (both encoded in MJPEG): + * 320x240 30 FPS + * 640x480 15 FPS + +## Tested cameras + * Logitech C980 + * CANYON CNE-CWC2 + +## Example Output + +``` +... +Waiting for device +Device found +DEVICE CONFIGURATION (0c45:6340/ S) --- +Status: idle +VideoControl: + bcdUVC: 0x0100 +VideoStreaming(1): + bEndpointAddress: 129 + Formats: + MJPEGFormat(1) + bits per pixel: 0 + GUID: 4d4a5047000000000000000000000000 (MJPG) + default frame: 1 + aspect ratio: 0x0 + interlace flags: 00 + copy protect: 00 + FrameDescriptor(1) + capabilities: 00 + size: 640x480 + bit rate: 24576000-147456000 + max frame size: 614400 + default interval: 1/30 + interval[0]: 1/30 + interval[1]: 1/25 + interval[2]: 1/20 + interval[3]: 1/15 + interval[4]: 1/10 + interval[5]: 1/5 + FrameDescriptor(2) + capabilities: 00 + size: 352x288 + bit rate: 8110080-48660480 + max frame size: 202752 + default interval: 1/30 + interval[0]: 1/30 + interval[1]: 1/25 + interval[2]: 1/20 + interval[3]: 1/15 + interval[4]: 1/10 + interval[5]: 1/5 + FrameDescriptor(3) + capabilities: 00 + size: 320x240 + bit rate: 6144000-36864000 + max frame size: 153600 + default interval: 1/30 + interval[0]: 1/30 + interval[1]: 1/25 + interval[2]: 1/20 + interval[3]: 1/15 + interval[4]: 1/10 + interval[5]: 1/5 + FrameDescriptor(4) + capabilities: 00 + size: 176x144 + bit rate: 2027520-12165120 + max frame size: 50688 + default interval: 1/30 + interval[0]: 1/30 + interval[1]: 1/25 + interval[2]: 1/20 + interval[3]: 1/15 + interval[4]: 1/10 + interval[5]: 1/5 + FrameDescriptor(5) + capabilities: 00 + size: 160x120 + bit rate: 1536000-9216000 + max frame size: 38400 + default interval: 1/30 + interval[0]: 1/30 + interval[1]: 1/25 + interval[2]: 1/20 + interval[3]: 1/15 + interval[4]: 1/10 + interval[5]: 1/5 + StillFrameDescriptor + bEndPointAddress: 00 + wWidth(1) = 640 + wHeight(1) = 480 + wWidth(2) = 352 + wHeight(2) = 288 + wWidth(3) = 320 + wHeight(3) = 240 + wWidth(4) = 176 + wHeight(4) = 144 + wWidth(5) = 160 + wHeight(5) = 120 +END DEVICE CONFIGURATION +bmHint: 0001 +bFormatIndex: 1 +bFrameIndex: 3 +dwFrameInterval: 333333 +wKeyFrameRate: 0 +wPFrameRate: 0 +wCompQuality: 0 +wCompWindowSize: 0 +wDelay: 20905 +dwMaxVideoFrameSize: 153600 +dwMaxPayloadTransferSize: 512 +bInterfaceNumber: 1 +Streaming... +I (4801) example: fps: 35, bytes per second: 170480 +I (5821) example: fps: 34, bytes per second: 172448 +I (6841) example: fps: 34, bytes per second: 172448 +I (7871) example: fps: 34, bytes per second: 172448 +I (8891) example: fps: 34, bytes per second: 172448 +I (9921) example: fps: 35, bytes per second: 177520 +I (10941) example: fps: 34, bytes per second: 172448 +I (11961) example: fps: 34, bytes per second: 172448 +I (12991) example: fps: 34, bytes per second: 172448 +I (14011) example: fps: 34, bytes per second: 172448 +I (15041) example: fps: 34, bytes per second: 172448 +I (16061) example: fps: 34, bytes per second: 172448 +I (17081) example: fps: 34, bytes per second: 172448 +Done streaming. +UVC exited +``` diff --git a/examples/peripherals/usb/host/uvc/main/CMakeLists.txt b/examples/peripherals/usb/host/uvc/main/CMakeLists.txt new file mode 100644 index 0000000000..1ab9ce5ce5 --- /dev/null +++ b/examples/peripherals/usb/host/uvc/main/CMakeLists.txt @@ -0,0 +1,3 @@ +idf_component_register(SRCS "main.c" "tcp_server.c" + INCLUDE_DIRS "" + REQUIRES protocol_examples_common nvs_flash usb mdns esp_ringbuf esp_timer esp_wifi driver) diff --git a/examples/peripherals/usb/host/uvc/main/Kconfig.projbuild b/examples/peripherals/usb/host/uvc/main/Kconfig.projbuild new file mode 100644 index 0000000000..2dac27bf66 --- /dev/null +++ b/examples/peripherals/usb/host/uvc/main/Kconfig.projbuild @@ -0,0 +1,7 @@ +menu "Example Configuration" + config EXAMPLE_ENABLE_STREAMING + bool "Enable streaming" + default n + help + Enables streaming of captured video +endmenu diff --git a/examples/peripherals/usb/host/uvc/main/idf_component.yml b/examples/peripherals/usb/host/uvc/main/idf_component.yml new file mode 100644 index 0000000000..8b906ef6cf --- /dev/null +++ b/examples/peripherals/usb/host/uvc/main/idf_component.yml @@ -0,0 +1,7 @@ +## IDF Component Manager Manifest File +dependencies: + idf: ">=4.4" + usb_host_uvc: "1.0.0" + mdns: + rules: + - if: "idf_version >= 5.0" diff --git a/examples/peripherals/usb/host/uvc/main/main.c b/examples/peripherals/usb/host/uvc/main/main.c new file mode 100644 index 0000000000..7cf4f476b6 --- /dev/null +++ b/examples/peripherals/usb/host/uvc/main/main.c @@ -0,0 +1,236 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include "esp_log.h" +#include "tcp_server.h" +#include "libuvc/libuvc.h" +#include "libuvc_helper.h" +#include "libuvc_adapter.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/semphr.h" +#include "freertos/event_groups.h" +#include "driver/gpio.h" +#include "usb/usb_host.h" +#include "esp_err.h" +#include "esp_log.h" +#include "esp_timer.h" + +static const char *TAG = "example"; + +#define USB_DISCONNECT_PIN GPIO_NUM_0 + +#define FPS 30 +#define WIDTH 320 +#define HEIGHT 240 +#define FORMAT UVC_COLOR_FORMAT_MJPEG // UVC_COLOR_FORMAT_YUYV + +// Attached camera can be filtered out based on (non-zero value of) PID, VID, SERIAL_NUMBER +#define PID 0 +#define VID 0 +#define SERIAL_NUMBER NULL + +#define UVC_CHECK(exp) do { \ + uvc_error_t _err_ = (exp); \ + if(_err_ < 0) { \ + ESP_LOGE(TAG, "UVC error: %s", \ + uvc_error_string(_err_)); \ + assert(0); \ + } \ +} while(0) + +static SemaphoreHandle_t ready_to_uninstall_usb; +static EventGroupHandle_t app_flags; + +// Handles common USB host library events +static void usb_lib_handler_task(void *args) +{ + while (1) { + uint32_t event_flags; + usb_host_lib_handle_events(portMAX_DELAY, &event_flags); + // Release devices once all clients has deregistered + if (event_flags & USB_HOST_LIB_EVENT_FLAGS_NO_CLIENTS) { + usb_host_device_free_all(); + } + // Give ready_to_uninstall_usb semaphore to indicate that USB Host library + // can be deinitialized, and terminate this task. + if (event_flags & USB_HOST_LIB_EVENT_FLAGS_ALL_FREE) { + xSemaphoreGive(ready_to_uninstall_usb); + } + } + + vTaskDelete(NULL); +} + +static esp_err_t initialize_usb_host_lib(void) +{ + TaskHandle_t task_handle = NULL; + + const usb_host_config_t host_config = { + .intr_flags = ESP_INTR_FLAG_LEVEL1 + }; + + esp_err_t err = usb_host_install(&host_config); + if (err != ESP_OK) { + return err; + } + + ready_to_uninstall_usb = xSemaphoreCreateBinary(); + if (ready_to_uninstall_usb == NULL) { + usb_host_uninstall(); + return ESP_ERR_NO_MEM; + } + + if (xTaskCreate(usb_lib_handler_task, "usb_events", 4096, NULL, 2, &task_handle) != pdPASS) { + vSemaphoreDelete(ready_to_uninstall_usb); + usb_host_uninstall(); + return ESP_ERR_NO_MEM; + } + + return ESP_OK; +} + +static void uninitialize_usb_host_lib(void) +{ + xSemaphoreTake(ready_to_uninstall_usb, portMAX_DELAY); + vSemaphoreDelete(ready_to_uninstall_usb); + + if ( usb_host_uninstall() != ESP_OK) { + ESP_LOGE(TAG, "Failed to uninstall usb_host"); + } +} + +/* This callback function runs once per frame. Use it to perform any + * quick processing you need, or have it put the frame into your application's + * input queue. If this function takes too long, you'll start losing frames. */ +void frame_callback(uvc_frame_t *frame, void *ptr) +{ + static size_t fps; + static size_t bytes_per_second; + static int64_t start_time; + + int64_t current_time = esp_timer_get_time(); + bytes_per_second += frame->data_bytes; + fps++; + + if (!start_time) { + start_time = current_time; + } + + if (current_time > start_time + 1000000) { + ESP_LOGI(TAG, "fps: %u, bytes per second: %u", fps, bytes_per_second); + start_time = current_time; + bytes_per_second = 0; + fps = 0; + } + + // Stream received frame to client, if enabled + tcp_server_send(frame->data, frame->data_bytes); +} + +void button_callback(int button, int state, void *user_ptr) +{ + printf("button %d state %d\n", button, state); +} + +static void libuvc_adapter_cb(libuvc_adapter_event_t event) +{ + xEventGroupSetBits(app_flags, event); +} + +static EventBits_t wait_for_event(EventBits_t event) +{ + return xEventGroupWaitBits(app_flags, event, pdTRUE, pdFALSE, portMAX_DELAY) & event; +} + +int app_main(int argc, char **argv) +{ + uvc_context_t *ctx; + uvc_device_t *dev; + uvc_device_handle_t *devh; + uvc_stream_ctrl_t ctrl; + uvc_error_t res; + + app_flags = xEventGroupCreate(); + assert(app_flags); + + const gpio_config_t input_pin = { + .pin_bit_mask = BIT64(USB_DISCONNECT_PIN), + .mode = GPIO_MODE_INPUT, + .pull_up_en = GPIO_PULLUP_ENABLE, + }; + ESP_ERROR_CHECK( gpio_config(&input_pin) ); + + ESP_ERROR_CHECK( initialize_usb_host_lib() ); + + libuvc_adapter_config_t config = { + .create_background_task = true, + .task_priority = 5, + .stack_size = 4096, + .callback = libuvc_adapter_cb + }; + + libuvc_adapter_set_config(&config); + + UVC_CHECK( uvc_init(&ctx, NULL) ); + + // Streaming takes place only when enabled in menuconfig + ESP_ERROR_CHECK( tcp_server_wait_for_connection() ); + + do { + + printf("Waiting for device\n"); + wait_for_event(UVC_DEVICE_CONNECTED); + + UVC_CHECK( uvc_find_device(ctx, &dev, PID, VID, SERIAL_NUMBER) ); + puts("Device found"); + + UVC_CHECK( uvc_open(dev, &devh) ); + + // Uncomment to print configuration descriptor + // libuvc_adapter_print_descriptors(devh); + + uvc_set_button_callback(devh, button_callback, NULL); + + // Print known device information + uvc_print_diag(devh, stderr); + + // Negotiate stream profile + res = uvc_get_stream_ctrl_format_size(devh, &ctrl, FORMAT, WIDTH, HEIGHT, FPS ); + while (res != UVC_SUCCESS) { + printf("Negotiating streaming format failed, trying again...\n"); + res = uvc_get_stream_ctrl_format_size(devh, &ctrl, FORMAT, WIDTH, HEIGHT, FPS ); + sleep(1); + } + + // dwMaxPayloadTransferSize has to be overwritten to MPS (maximum packet size) + // supported by ESP32-S2(S3), as libuvc selects the highest possible MPS by default. + ctrl.dwMaxPayloadTransferSize = 512; + + uvc_print_stream_ctrl(&ctrl, stderr); + + UVC_CHECK( uvc_start_streaming(devh, &ctrl, frame_callback, NULL, 0) ); + puts("Streaming..."); + + wait_for_event(UVC_DEVICE_DISCONNECTED); + + uvc_stop_streaming(devh); + puts("Done streaming."); + + uvc_close(devh); + + } while (gpio_get_level(USB_DISCONNECT_PIN) != 0); + + tcp_server_close_when_done(); + + uvc_exit(ctx); + puts("UVC exited"); + + uninitialize_usb_host_lib(); + + return 0; +} diff --git a/examples/peripherals/usb/host/uvc/main/tcp_server.c b/examples/peripherals/usb/host/uvc/main/tcp_server.c new file mode 100644 index 0000000000..d11c8b3a4e --- /dev/null +++ b/examples/peripherals/usb/host/uvc/main/tcp_server.c @@ -0,0 +1,227 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include +#include +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/ringbuf.h" +#include "freertos/event_groups.h" +#include "esp_system.h" +#include "esp_wifi.h" +#include "esp_event.h" +#include "esp_log.h" +#include "nvs_flash.h" +#include "esp_netif.h" +#include "protocol_examples_common.h" +#include "addr_from_stdin.h" +#include "lwip/err.h" +#include "lwip/sockets.h" +#include "tcp_server.h" +#include "mdns.h" + +#define TAG "tcp_server" +#define PORT 2222 + +typedef struct { + int sock; + int listen_sock; + RingbufHandle_t buffer; + volatile bool close_request; + bool is_active; +} tcp_server_t; + +#ifdef CONFIG_EXAMPLE_ENABLE_STREAMING + +static tcp_server_t *s_server; + +void socket_close(tcp_server_t *server) +{ + ESP_LOGI(TAG, "Closing socket"); + shutdown(server->sock, 0); + close(server->sock); + close(server->listen_sock); +} + +static void sender_task(void *arg) +{ + tcp_server_t *server = (tcp_server_t *)arg; + server->is_active = true; + + while (1) { + size_t bytes_received = 0; + char *payload = (char *)xRingbufferReceiveUpTo( + server->buffer, &bytes_received, pdMS_TO_TICKS(2500), 20000); + + if (payload != NULL && server->is_active) { + int sent = send(server->sock, payload, bytes_received, 0); + if (sent < 0) { + ESP_LOGE(TAG, "Error occurred during sending: errno %d, \ + Shutting down tcp server...", errno); + server->is_active = false; + } + vRingbufferReturnItem(server->buffer, (void *)payload); + } + + if (server->close_request) { + socket_close(server); + vRingbufferDelete(server->buffer); + vTaskDelete(NULL); + s_server = NULL; + free(server); + return; + } + } +} + +esp_err_t tcp_server_send(uint8_t *payload, size_t size) +{ + if (!s_server || !s_server->is_active) { + return ESP_OK; + } + + if ( xRingbufferSend(s_server->buffer, payload, size, pdMS_TO_TICKS(1)) != pdTRUE ) { + ESP_LOGW(TAG, "Failed to send frame to ring buffer."); + return ESP_FAIL; + } + + return ESP_OK; +} + +static esp_err_t start_mdns_service(void) +{ + esp_err_t err = mdns_init(); + if (err) { + printf("MDNS Init failed: %d\n", err); + return ESP_FAIL; + } + + mdns_hostname_set("esp-cam"); + + return ESP_OK; +} + +static esp_err_t create_server(tcp_server_t *server) +{ + char addr_str[128]; + int ip_protocol = 0; + int addr_family = AF_INET; + struct sockaddr_storage dest_addr; + + struct sockaddr_in *dest_addr_ip4 = (struct sockaddr_in *)&dest_addr; + dest_addr_ip4->sin_addr.s_addr = htonl(INADDR_ANY); + dest_addr_ip4->sin_family = addr_family; + dest_addr_ip4->sin_port = htons(PORT); + ip_protocol = IPPROTO_IP; + + server->listen_sock = socket(addr_family, SOCK_STREAM, ip_protocol); + if (server->listen_sock < 0) { + ESP_LOGE(TAG, "Unable to create socket: errno %d", errno); + return ESP_FAIL; + } + int opt = 1; + setsockopt(server->listen_sock, SOL_SOCKET, SO_REUSEADDR, &opt, sizeof(opt)); + + ESP_LOGI(TAG, "Socket created"); + + int err = bind(server->listen_sock, (struct sockaddr *)&dest_addr, sizeof(dest_addr)); + if (err != 0) { + ESP_LOGE(TAG, "Socket unable to bind: errno %d", errno); + ESP_LOGE(TAG, "IPPROTO: %d", addr_family); + close(server->listen_sock); + return ESP_FAIL; + } + ESP_LOGI(TAG, "Socket bound, port %d", PORT); + + err = listen(server->listen_sock, 1); + if (err != 0) { + ESP_LOGE(TAG, "Error occurred during listen: errno %d", errno); + close(server->listen_sock); + return ESP_FAIL; + } + + ESP_LOGI(TAG, "Socket listening..."); + ESP_LOGI(TAG, "Execute player.py script"); + + struct sockaddr_storage source_addr; + socklen_t addr_len = sizeof(source_addr); + server->sock = accept(server->listen_sock, (struct sockaddr *)&source_addr, &addr_len); + if (server->sock < 0) { + ESP_LOGE(TAG, "Unable to accept connection: errno %d", errno); + close(server->listen_sock); + return ESP_FAIL; + } + + // Convert ip address to string + if (source_addr.ss_family == PF_INET) { + inet_ntoa_r(((struct sockaddr_in *)&source_addr)->sin_addr, addr_str, sizeof(addr_str) - 1); + } + ESP_LOGI(TAG, "Socket accepted ip address: %s", addr_str); + + return ESP_OK; +} + +esp_err_t tcp_server_wait_for_connection(void) +{ + TaskHandle_t task_handle = NULL; + + ESP_ERROR_CHECK(nvs_flash_init()); + ESP_ERROR_CHECK(esp_netif_init()); + ESP_ERROR_CHECK(esp_event_loop_create_default()); + ESP_ERROR_CHECK(start_mdns_service()); + ESP_ERROR_CHECK(example_connect()); + + tcp_server_t *server = calloc(1, sizeof(tcp_server_t)); + if (server == NULL) { + return ESP_ERR_NO_MEM; + } + + server->buffer = xRingbufferCreate(100000, RINGBUF_TYPE_BYTEBUF); + if ( server->buffer == NULL) { + free(server); + return ESP_ERR_NO_MEM;; + } + + if ( create_server(server) != ESP_OK) { + vRingbufferDelete(server->buffer); + free(server); + return ESP_FAIL; + } + + + BaseType_t task_created = xTaskCreate(sender_task, "sender_task", 4096, server, 10, &task_handle); + if (!task_created) { + socket_close(server); + vRingbufferDelete(server->buffer); + free(server); + return ESP_ERR_NO_MEM; + } + + s_server = server; + return ESP_OK; +} + +void tcp_server_close_when_done(void) +{ + if (s_server) { + s_server->close_request = true; + } +} + +#else + +esp_err_t tcp_server_wait_for_connection(void) +{ + return ESP_OK; +} + +esp_err_t tcp_server_send(uint8_t *payload, size_t size) +{ + return ESP_OK; +} + +void tcp_server_close_when_done(void) { } + +#endif diff --git a/examples/peripherals/usb/host/uvc/main/tcp_server.h b/examples/peripherals/usb/host/uvc/main/tcp_server.h new file mode 100644 index 0000000000..b4562a3fb7 --- /dev/null +++ b/examples/peripherals/usb/host/uvc/main/tcp_server.h @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#pragma once + +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +esp_err_t tcp_server_wait_for_connection(void); + +esp_err_t tcp_server_send(uint8_t *payload, size_t size); + +void tcp_server_close_when_done(void); + +#ifdef __cplusplus +} +#endif diff --git a/examples/peripherals/usb/host/uvc/player.py b/examples/peripherals/usb/host/uvc/player.py new file mode 100644 index 0000000000..1340ce36f4 --- /dev/null +++ b/examples/peripherals/usb/host/uvc/player.py @@ -0,0 +1,37 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Unlicense OR CC0-1.0 +import socket + +import cv2 +import numpy as np + +frame_count = 0 +stream = bytearray() + +print('Connecting to server...') + +with socket.socket(socket.AF_INET, socket.SOCK_STREAM) as sock: + sock.connect(('esp-cam.local', 2222)) + + print('Receiving data ') + while True: + data = sock.recv(4096) + if not data: + break + stream += data + print('.', end='', flush=True) + + a = stream.find(b'\xff\xd8') + b = stream.find(b'\xff\xd9', a) + + if a != -1 and b != -1: + jpg = stream[a:b + 2] + stream = stream[b + 2:] + buffer = np.frombuffer(jpg, dtype=np.uint8) + image = cv2.imdecode(buffer, cv2.IMREAD_COLOR) + cv2.imshow('Stream', image) + if cv2.waitKey(10) == 27: + exit(0) + frame_count += 1 + +print('\nFrames received ', frame_count) diff --git a/examples/peripherals/usb/host/uvc/sdkconfig.defaults b/examples/peripherals/usb/host/uvc/sdkconfig.defaults new file mode 100644 index 0000000000..cb7325efc7 --- /dev/null +++ b/examples/peripherals/usb/host/uvc/sdkconfig.defaults @@ -0,0 +1,26 @@ +# +# SPIRAM +# +CONFIG_SPIRAM=y +CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL=150000 +CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP=y + +# +# USB +# +CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE=1024 +CONFIG_USB_HOST_HW_BUFFER_BIAS_IN=y + +# +# WIFI +# +CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=8 +CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=8 +CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=8 +CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM=16 +CONFIG_ESP32_WIFI_RX_BA_WIN=8 + +# +# LWIP +# +CONFIG_LWIP_TCP_SND_BUF_DEFAULT=15000 diff --git a/examples/protocols/.build-test-rules.yml b/examples/protocols/.build-test-rules.yml index dd07fc0a53..07ec3ae0aa 100644 --- a/examples/protocols/.build-test-rules.yml +++ b/examples/protocols/.build-test-rules.yml @@ -53,10 +53,9 @@ examples/protocols/asio/udp_echo_server: reason: lack of runners examples/protocols/coap_client: - disable: - - if: IDF_TARGET == "esp32c2" - temporary: true - reason: target esp32c2 is not supported yet + disable_test: + - if: IDF_TARGET != "esp32" + reason: running this test on single platform is sufficient for coverage examples/protocols/coap_server: disable: @@ -239,6 +238,8 @@ examples/protocols/sockets/tcp_client: - if: IDF_TARGET != "esp32" temporary: true reason: lack of runners + enable: + - if: INCLUDE_DEFAULT == 1 or IDF_TARGET == "linux" examples/protocols/sockets/tcp_client_multi_net: disable: diff --git a/examples/protocols/coap_client/README.md b/examples/protocols/coap_client/README.md index 6a3ea197d5..a9b39c55cd 100644 --- a/examples/protocols/coap_client/README.md +++ b/examples/protocols/coap_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | # CoAP client example diff --git a/examples/protocols/coap_client/pytest_coap_client_example.py b/examples/protocols/coap_client/pytest_coap_client_example.py new file mode 100644 index 0000000000..6e70feb74c --- /dev/null +++ b/examples/protocols/coap_client/pytest_coap_client_example.py @@ -0,0 +1,21 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Unlicense OR CC0-1.0 +import pexpect +import pytest +from pytest_embedded import Dut + + +@pytest.mark.esp32 +@pytest.mark.ethernet +def test_coap_example(dut: Dut) -> None: + dut.expect('Loaded app from partition at offset', timeout=30) + try: + dut.expect(r'IPv4 address: (\d+\.\d+\.\d+\.\d+)[^\d]', timeout=30) + except pexpect.exceptions.TIMEOUT: + raise ValueError('ENV_TEST_FAILURE: Cannot connect to AP/Ethernet') + + dut.expect('DNS lookup succeeded', timeout=30) + dut.expect('Received', timeout=30) + dut.expect(r'This server is using the Eclipse Californium \(Cf\) CoAP framework', timeout=30) + dut.expect(r'published under EPL\+EDL: http://www\.eclipse\.org/californium/', timeout=30) + dut.expect('Starting again!', timeout=30) diff --git a/examples/protocols/coap_client/sdkconfig.ci b/examples/protocols/coap_client/sdkconfig.ci new file mode 100644 index 0000000000..f958eb22e9 --- /dev/null +++ b/examples/protocols/coap_client/sdkconfig.ci @@ -0,0 +1,8 @@ +CONFIG_EXAMPLE_CONNECT_ETHERNET=y +CONFIG_EXAMPLE_CONNECT_WIFI=n +CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET=y +CONFIG_EXAMPLE_ETH_PHY_IP101=y +CONFIG_EXAMPLE_ETH_MDC_GPIO=23 +CONFIG_EXAMPLE_ETH_MDIO_GPIO=18 +CONFIG_EXAMPLE_ETH_PHY_RST_GPIO=5 +CONFIG_EXAMPLE_ETH_PHY_ADDR=1 diff --git a/examples/protocols/http_server/advanced_tests/scripts/test.py b/examples/protocols/http_server/advanced_tests/scripts/test.py index dc43fdd197..e3e11b0d15 100644 --- a/examples/protocols/http_server/advanced_tests/scripts/test.py +++ b/examples/protocols/http_server/advanced_tests/scripts/test.py @@ -1,18 +1,7 @@ #!/usr/bin/env python # -# Copyright 2018 Espressif Systems (Shanghai) PTE LTD -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. +# SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 # Utility for testing the web server. Test cases: # Assume the device supports 'n' simultaneous open sockets @@ -139,7 +128,6 @@ import string import sys import threading import time -from builtins import object, range, str try: import Utility diff --git a/examples/protocols/http_server/persistent_sockets/pytest_http_server_persistence.py b/examples/protocols/http_server/persistent_sockets/pytest_http_server_persistence.py index ac8b3febc3..c0514e54e2 100644 --- a/examples/protocols/http_server/persistent_sockets/pytest_http_server_persistence.py +++ b/examples/protocols/http_server/persistent_sockets/pytest_http_server_persistence.py @@ -2,14 +2,10 @@ # # SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 - -from __future__ import division, print_function, unicode_literals - import logging import os import random import sys -from builtins import range, str import pytest diff --git a/examples/protocols/http_server/simple/pytest_http_server_simple.py b/examples/protocols/http_server/simple/pytest_http_server_simple.py index fc1b3d9b58..eb5d8a95b4 100644 --- a/examples/protocols/http_server/simple/pytest_http_server_simple.py +++ b/examples/protocols/http_server/simple/pytest_http_server_simple.py @@ -2,9 +2,6 @@ # # SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 - -from __future__ import division, print_function, unicode_literals - import logging import os import random @@ -13,7 +10,6 @@ import string import sys import threading import time -from builtins import range import pytest diff --git a/examples/protocols/https_request/main/https_request_example_main.c b/examples/protocols/https_request/main/https_request_example_main.c index 86ab25ded8..70e7f9b398 100644 --- a/examples/protocols/https_request/main/https_request_example_main.c +++ b/examples/protocols/https_request/main/https_request_example_main.c @@ -280,7 +280,7 @@ void app_main(void) } const esp_timer_create_args_t nvs_update_timer_args = { - .callback = &fetch_and_store_time_in_nvs, + .callback = (void *)&fetch_and_store_time_in_nvs, }; esp_timer_handle_t nvs_update_timer; diff --git a/examples/protocols/https_request/main/include/time_sync.h b/examples/protocols/https_request/main/include/time_sync.h index 38f8d6089f..1052eee969 100644 --- a/examples/protocols/https_request/main/include/time_sync.h +++ b/examples/protocols/https_request/main/include/time_sync.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -20,7 +20,7 @@ esp_err_t update_time_from_nvs(void); * @brief Fetch the current time from SNTP and stores it in NVS. * */ -void fetch_and_store_time_in_nvs(void*); +esp_err_t fetch_and_store_time_in_nvs(void*); #ifdef __cplusplus } diff --git a/examples/protocols/https_request/main/time_sync.c b/examples/protocols/https_request/main/time_sync.c index 653889617d..faeca0d484 100644 --- a/examples/protocols/https_request/main/time_sync.c +++ b/examples/protocols/https_request/main/time_sync.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -34,14 +34,15 @@ void initialize_sntp(void) { ESP_LOGI(TAG, "Initializing SNTP"); sntp_setoperatingmode(SNTP_OPMODE_POLL); - sntp_setservername(0, "pool.ntp.org"); + sntp_setservername(0, "time.windows.com"); + sntp_setservername(1, "pool.ntp.org"); #ifdef CONFIG_SNTP_TIME_SYNC_METHOD_SMOOTH sntp_set_sync_mode(SNTP_SYNC_MODE_SMOOTH); #endif sntp_init(); } -static void obtain_time(void) +static esp_err_t obtain_time(void) { /** * NTP server address could be aquired via DHCP, @@ -58,12 +59,18 @@ static void obtain_time(void) ESP_LOGI(TAG, "Waiting for system time to be set... (%d/%d)", retry, retry_count); vTaskDelay(2000 / portTICK_PERIOD_MS); } + if (retry == retry_count) { + return ESP_FAIL; + } + return ESP_OK; } -void fetch_and_store_time_in_nvs(void *args) +esp_err_t fetch_and_store_time_in_nvs(void *args) { initialize_sntp(); - obtain_time(); + if (obtain_time() != ESP_OK) { + return ESP_FAIL; + } nvs_handle_t my_handle; esp_err_t err; @@ -97,6 +104,7 @@ exit: } else { ESP_LOGI(TAG, "Updated time in NVS"); } + return err; } esp_err_t update_time_from_nvs(void) @@ -114,8 +122,12 @@ esp_err_t update_time_from_nvs(void) err = nvs_get_i64(my_handle, "timestamp", ×tamp); if (err == ESP_ERR_NVS_NOT_FOUND) { - fetch_and_store_time_in_nvs(NULL); - err = ESP_OK; + ESP_LOGI(TAG, "Time not found in NVS. Syncing time from SNTP server."); + if (fetch_and_store_time_in_nvs(NULL) != ESP_OK) { + err = ESP_FAIL; + } else { + err = ESP_OK; + } } else if (err == ESP_OK) { struct timeval get_nvs_time; get_nvs_time.tv_sec = timestamp; diff --git a/examples/protocols/https_request/pytest_https_request.py b/examples/protocols/https_request/pytest_https_request.py index a672edc2fc..176ea0de2b 100644 --- a/examples/protocols/https_request/pytest_https_request.py +++ b/examples/protocols/https_request/pytest_https_request.py @@ -61,6 +61,7 @@ def start_https_server(server_file: str, key_file: str, server_ip: str, server_p @pytest.mark.esp32s3 @pytest.mark.ethernet @pytest.mark.parametrize('config', ['cli_ses_tkt',], indirect=True) +@pytest.mark.parametrize('erase_nvs', ['y'], indirect=True) def test_examples_protocol_https_request_cli_session_tickets(dut: Dut) -> None: logging.info("Testing for \"esp_tls client session tickets\"") @@ -123,6 +124,7 @@ def test_examples_protocol_https_request_cli_session_tickets(dut: Dut) -> None: @pytest.mark.esp32s3 @pytest.mark.ethernet @pytest.mark.parametrize('config', ['ssldyn',], indirect=True) +@pytest.mark.parametrize('erase_nvs', ['y'], indirect=True) def test_examples_protocol_https_request_dynamic_buffers(dut: Dut) -> None: # Check for connection using crt bundle with mbedtls dynamic resource enabled # check and log bin size @@ -153,6 +155,7 @@ def test_examples_protocol_https_request_dynamic_buffers(dut: Dut) -> None: @pytest.mark.supported_targets @pytest.mark.ethernet +@pytest.mark.parametrize('erase_nvs', ['y'], indirect=True) def test_examples_protocol_https_request(dut: Dut) -> None: """ diff --git a/examples/protocols/https_request/sdkconfig.defaults b/examples/protocols/https_request/sdkconfig.defaults index eab29d35fa..4fe81b2f33 100644 --- a/examples/protocols/https_request/sdkconfig.defaults +++ b/examples/protocols/https_request/sdkconfig.defaults @@ -1 +1,2 @@ CONFIG_MBEDTLS_HAVE_TIME_DATE=y +CONFIG_LWIP_SNTP_MAX_SERVERS=2 diff --git a/examples/protocols/mqtt/ssl/mqtt_ssl_example_test.py b/examples/protocols/mqtt/ssl/mqtt_ssl_example_test.py index 3309ca4d2a..51ac4e9754 100644 --- a/examples/protocols/mqtt/ssl/mqtt_ssl_example_test.py +++ b/examples/protocols/mqtt/ssl/mqtt_ssl_example_test.py @@ -1,10 +1,7 @@ -from __future__ import print_function, unicode_literals - import os import re import ssl import sys -from builtins import str from threading import Event, Thread import paho.mqtt.client as mqtt diff --git a/examples/protocols/mqtt/ssl_ds/CMakeLists.txt b/examples/protocols/mqtt/ssl_ds/CMakeLists.txt index c45c2a0c8d..144cf8b4db 100644 --- a/examples/protocols/mqtt/ssl_ds/CMakeLists.txt +++ b/examples/protocols/mqtt/ssl_ds/CMakeLists.txt @@ -9,12 +9,11 @@ set(EXTRA_COMPONENT_DIRS $ENV{IDF_PATH}/examples/common_components/protocol_exam include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(mqtt_ssl_ds) -# Flash the custom partition named `pre_prov`. -set(partition pre_prov) +# Flash the custom partition named `esp_secure_cert`. +set(partition esp_secure_cert) idf_build_get_property(project_dir PROJECT_DIR) -set(image_file ${project_dir}/esp_ds_data/${partition}.bin) +set(image_file ${project_dir}/esp_secure_cert_data/${partition}.bin) partition_table_get_partition_info(offset "--partition-name ${partition}" "offset") esptool_py_flash_target_image(flash "${partition}" "${offset}" "${image_file}") -target_add_binary_data(${CMAKE_PROJECT_NAME}.elf "main/client.crt" TEXT) target_add_binary_data(${CMAKE_PROJECT_NAME}.elf "main/mosquitto.org.crt" TEXT) diff --git a/examples/protocols/mqtt/ssl_ds/README.md b/examples/protocols/mqtt/ssl_ds/README.md index 065bcfca2b..6a321bd483 100644 --- a/examples/protocols/mqtt/ssl_ds/README.md +++ b/examples/protocols/mqtt/ssl_ds/README.md @@ -40,22 +40,27 @@ openssl genrsa -out client.key openssl req -out client.csr -key client.key -new ``` -Paste the generated CSR in the [Mosquitto test certificate signer](https://test.mosquitto.org/ssl/index.php), click Submit and copy the downloaded `client.crt` in the `main` directory. - -Please note, that the supplied file `client.crt` in the `main` directory is only a placeholder for your client certificate (i.e. the example "as is" would compile but would not connect to the broker) +Paste the generated CSR in the [Mosquitto test certificate signer](https://test.mosquitto.org/ssl/index.php), click Submit and downloaded the `client.crt`. This `client.crt` file shall be used as the device certificate. #### 3) Configure the DS peripheral -* The DS peripheral can be configured with the python script [configure_ds.py](README.md#configure_ds-py) by executing the following command +* i) Install the [esp_secure_cert configuration utility](https://github.com/espressif/esp_secure_cert_mgr/tree/main/tools#esp_secure_cert-configuration-tool) with following command: +``` +pip install esp-secure-cert-tool +``` +* ii) The DS peripheral can be configured by executing the following command: ``` - python configure_ds.py --port /* USB COM port */ --private-key /* RSA priv key */ +configure_esp_secure_cert.py -p /* Serial port */ --device-cert /* Device cert */ --private-key /* RSA priv key */ --target_chip /* target chip */ --configure_ds --skip_flash ``` +This command shall generate a partition named `esp_secure_cert.bin` in the `esp_secure_cert_data` directory. This partition would be aumatically detected by the build system and flashed at appropriate offset when `idf.py flash` command is used. For this process, the command must be executed in the current folder only. In the command USB COM port is nothing but the serial port to which the ESP chip is connected. see [check serial port](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/get-started/establish-serial-connection.html#check-port-on-windows) for more details. RSA private key is nothing but the client private key ( RSA ) generated in Step 2. +> Note: More details about the `esp-secure-cert-tool` utility can be found [here](https://github.com/espressif/esp_secure_cert_mgr/tree/main/tools). + #### 4) Connection cofiguration * Open the project configuration menu (`idf.py menuconfig`) * Configure Wi-Fi or Ethernet under "Example Connection Configuration" menu. See "Establishing Wi-Fi or Ethernet Connection" section in [examples/protocols/README.md](../../README.md) for more details. @@ -97,49 +102,3 @@ I (5194) MQTTS_EXAMPLE: MQTT_EVENT_DATA TOPIC=/topic/qos0 DATA=data ``` - - -### configure_ds.py -The script [configure_ds.py](./configure_ds.py) is used for configuring the DS peripheral on the ESP32-S2/ESP32-S3/ESP32-C3 SoC. The steps in the script are based on technical details of certain operations in the Digital Signature calculation, which can be found at Digital Signature Section of [ESP32-S2 TRM](https://www.espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf) - -The configuration script performs the following steps - - -1. Take the client private key ( RSA key ) as input. - (*required parameter for the script) -can be provided with -``` - python configure_ds.py --private-key /* path to client (rsa) prv key */ -``` - -2. Randomly Calculate the `HMAC_KEY` and the `initialization vector`(IV). Then calculate the encrypted private key parameters from client private key (step i) and newly generated parameters. These encrypted private key parameters are required for the DS peripheral to perform the Digital Signature operation. - -3. Store the `HMAC_KEY` in one of the efuse key blocks (in the hardware). - The ID of the efuse key block ( should be in range 1-5) can be provided with the following option. (default value of 1 is used if not provided), -``` - python configure_ds.py --efuse_key_id /* key id in range 1-5 */ -``` - -Currently for development purposes, the `HMAC_KEY` is stored in the efuse key block without read protection so that read operation can be performed on the same key block. -> You can burn (write) a key on an efuse key block only once. Please use a different key block ID if you want to use a different `HMAC_KEY` for the DS operation. - -4. Create an NVS partition of the name `pre_prov.csv` (in `esp_ds_data` folder) which contains the required encrypted private key parameters. A bin file of the nvs partition (`pre_prov.bin`) is also created. As we have added a custom partition, the example is set to use the custom partition table by adding the required option in `sdkconfig.defaults`. - -5. (optional) The script can be made to print the summary of the efuse on the chip by providing the following option. When this option is enabled, no other operations in the script are performed. -``` - python configure_ds.py --summary -``` - -6. (optional) If the user wants to keep the encrypted private key data and the randomly generated `HMAC_KEY` on the host machine for testing purpose. The following option may be used. -``` - python configure_ds.py --keep_ds_data_on_host -``` - The respective files will be stored in the `esp_ds_data` folder which is generated by the script in the same directory. The contents of the `esp_ds_data` folder may be overwritten when the `configure_ds.py` script is executed again. - -7. (optional) If the user wants to use the script for production usecase then this option can be used. -Currently for development purpose, the script disables the read protection on the efuse key block by default. -In case of a production usecase it is recommeneded to enable the read protection for the efuse key block. It can be done by providing following option along with other required options: -``` - python configure_ds.py --production -``` - -> A list of all the supported options in the script can be obtained by executing `python configure_ds.py --help`. diff --git a/examples/protocols/mqtt/ssl_ds/configure_ds.py b/examples/protocols/mqtt/ssl_ds/configure_ds.py deleted file mode 100644 index d847db23a6..0000000000 --- a/examples/protocols/mqtt/ssl_ds/configure_ds.py +++ /dev/null @@ -1,393 +0,0 @@ -#!/usr/bin/env python -# SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD -# SPDX-License-Identifier: Apache-2.0 -import argparse -import hashlib -import hmac -import json -import os -import struct -import subprocess -import sys - -from cryptography.hazmat.backends import default_backend -from cryptography.hazmat.primitives import serialization -from cryptography.hazmat.primitives.asymmetric import rsa -from cryptography.hazmat.primitives.ciphers import Cipher, algorithms, modes -from cryptography.utils import int_to_bytes - -try: - import nvs_partition_gen as nvs_gen -except ImportError: - idf_path = os.getenv('IDF_PATH') - if not idf_path or not os.path.exists(idf_path): - raise Exception('IDF_PATH not found') - sys.path.insert(0, os.path.join(idf_path, 'components', 'nvs_flash', 'nvs_partition_generator')) - import nvs_partition_gen as nvs_gen - -# Check python version is proper or not to avoid script failure -assert sys.version_info >= (3, 6, 0), 'Python version too low.' - -esp_ds_data_dir = 'esp_ds_data' -# hmac_key_file is generated when HMAC_KEY is calculated, it is used when burning HMAC_KEY to efuse -hmac_key_file = esp_ds_data_dir + '/hmac_key.bin' -# csv and bin filenames are default filenames for nvs partition files created with this script -csv_filename = esp_ds_data_dir + '/pre_prov.csv' -bin_filename = esp_ds_data_dir + '/pre_prov.bin' -expected_json_path = os.path.join('build', 'config', 'sdkconfig.json') -# Targets supported by the script -supported_targets = {'esp32s2', 'esp32c3', 'esp32s3'} -supported_key_size = {'esp32s2':[1024, 2048, 3072, 4096], 'esp32c3':[1024, 2048, 3072], 'esp32s3':[1024, 2048, 3072, 4096]} - - -# @return -# on success idf_target - value of the IDF_TARGET read from build/config/sdkconfig.json -# on failure None -def get_idf_target(): - if os.path.exists(expected_json_path): - sdkconfig = json.load(open(expected_json_path)) - idf_target_read = sdkconfig['IDF_TARGET'] - return idf_target_read - else: - print('ERROR: IDF_TARGET has not been set for the supported targets,' - "\nplase execute command \"idf.py set-target {TARGET}\" in the example directory") - return None - - -def load_privatekey(key_file_path, password=None): - key_file = open(key_file_path, 'rb') - key = key_file.read() - key_file.close() - return serialization.load_pem_private_key(key, password=password, backend=default_backend()) - - -def number_as_bytes(number, pad_bits=None): - """ - Given a number, format as a little endian array of bytes - """ - result = int_to_bytes(number)[::-1] - while pad_bits is not None and len(result) < (pad_bits // 8): - result += b'\x00' - return result - - -# @return -# c : ciphertext_c -# iv : initialization vector -# key_size : key size of the RSA private key in bytes. -# @input -# privkey : path to the RSA private key -# priv_key_pass : path to the RSA privaete key password -# hmac_key : HMAC key value ( to calculate DS params) -# idf_target : The target chip for the script (e.g. esp32s2, esp32c3, esp32s3) -# @info -# The function calculates the encrypted private key parameters. -# Consult the DS documentation (available for the ESP32-S2) in the esp-idf programming guide for more details about the variables and calculations. -def calculate_ds_parameters(privkey, priv_key_pass, hmac_key, idf_target): - private_key = load_privatekey(privkey, priv_key_pass) - if not isinstance(private_key, rsa.RSAPrivateKey): - print('ERROR: Only RSA private keys are supported') - sys.exit(-1) - if hmac_key is None: - print('ERROR: hmac_key cannot be None') - sys.exit(-2) - - priv_numbers = private_key.private_numbers() - pub_numbers = private_key.public_key().public_numbers() - Y = priv_numbers.d - M = pub_numbers.n - key_size = private_key.key_size - if key_size not in supported_key_size[idf_target]: - print('ERROR: Private key size {0} not supported for the target {1},\nthe supported key sizes are {2}' - .format(key_size, idf_target, str(supported_key_size[idf_target]))) - sys.exit(-1) - - iv = os.urandom(16) - - rr = 1 << (key_size * 2) - rinv = rr % pub_numbers.n - mprime = - rsa._modinv(M, 1 << 32) - mprime &= 0xFFFFFFFF - length = key_size // 32 - 1 - - # get max supported key size for the respective target - max_len = max(supported_key_size[idf_target]) - aes_key = hmac.HMAC(hmac_key, b'\xFF' * 32, hashlib.sha256).digest() - - md_in = number_as_bytes(Y, max_len) + \ - number_as_bytes(M, max_len) + \ - number_as_bytes(rinv, max_len) + \ - struct.pack('esp_ds_data = (esp_ds_data_t *)calloc(1, sizeof(esp_ds_data_t)); - if (ds_data_ctx->esp_ds_data == NULL) { - ESP_LOGE(TAG, "Could not allocate memory for DS data handle "); - goto exit; - } - - nvs_handle_t esp_ds_nvs_handle; - esp_err_t esp_ret; - esp_ret = nvs_flash_init_partition(NVS_PARTITION_NAME); - if (esp_ret != ESP_OK) { - ESP_LOGE(TAG, "Error in esp_ds_nvs partition init,\nreturned %02x (%s)", esp_ret, esp_err_to_name(esp_ret)); - goto exit; - } - - esp_ret = nvs_open_from_partition(NVS_PARTITION_NAME, NVS_NAMESPACE, - NVS_READONLY, &esp_ds_nvs_handle); - if (esp_ret != ESP_OK) { - ESP_LOGE(TAG, "Error in esp_ds_nvs partition open,\nreturned %02x (%s)", esp_ret, esp_err_to_name(esp_ret)); - goto exit; - } - - esp_ret = nvs_get_u8(esp_ds_nvs_handle, NVS_EFUSE_KEY_ID, &ds_data_ctx->efuse_key_id); - if (esp_ret != ESP_OK) { - ESP_LOGE(TAG, "Error in efuse_key_id value from nvs,\nreturned %02x (%s)", esp_ret, esp_err_to_name(esp_ret)); - goto exit; - } - - esp_ret = nvs_get_u16(esp_ds_nvs_handle, NVS_RSA_LEN, &ds_data_ctx->rsa_length_bits); - if (esp_ret != ESP_OK) { - ESP_LOGE(TAG, "Error in reading rsa key length value from nvs,\nreturned %02x (%s)", esp_ret, esp_err_to_name(esp_ret)); - goto exit; - } - - size_t blob_length = ESP_DS_C_LEN; - esp_ret = nvs_get_blob(esp_ds_nvs_handle, NVS_CIPHER_C, (void *)(ds_data_ctx->esp_ds_data->c), &blob_length); - if ((esp_ret != ESP_OK) || (blob_length != ESP_DS_C_LEN)) { - ESP_LOGE(TAG, "Error in reading ciphertext_c value from nvs,bytes_read = %d,\nreturned %02x (%s)", blob_length, esp_ret, esp_err_to_name(esp_ret)); - goto exit; - } - - blob_length = ESP_DS_IV_LEN; - esp_ret = nvs_get_blob(esp_ds_nvs_handle, NVS_IV, (void *)(ds_data_ctx->esp_ds_data->iv), &blob_length); - if ((esp_ret != ESP_OK) || (blob_length != ESP_DS_IV_LEN)) { - ESP_LOGE(TAG, "Error in reading initialization vector value from nvs,bytes_read = %d,\nreturned %02x (%s)", blob_length, esp_ret, esp_err_to_name(esp_ret)); - goto exit; - } - - return (void *)ds_data_ctx; -exit: - if (ds_data_ctx != NULL) { - free(ds_data_ctx->esp_ds_data); - } - free(ds_data_ctx); - return NULL; -} - static void mqtt_app_start(void) { - /* The context is used by the DS peripheral, should not be freed */ - void *ds_data = esp_read_ds_data_from_nvs(); + esp_ds_data_ctx_t *ds_data = esp_secure_cert_get_ds_ctx(); if (ds_data == NULL) { ESP_LOGE(TAG, "Error in reading DS data from NVS"); vTaskDelete(NULL); } + char *device_cert = NULL; + esp_err_t ret; + uint32_t len; + ret = esp_secure_cert_get_device_cert(&device_cert, &len); + if (ret != ESP_OK) { + ESP_LOGE(TAG, "Failed to obtain the device certificate"); + vTaskDelete(NULL); + } + const esp_mqtt_client_config_t mqtt_cfg = { .broker = { .address.uri = "mqtts://test.mosquitto.org:8884", @@ -190,9 +118,9 @@ static void mqtt_app_start(void) }, .credentials = { .authentication = { - .certificate = (const char *)client_cert_pem_start, + .certificate = (const char *)device_cert, .key = NULL, - .ds_data = ds_data + .ds_data = (void *)ds_data }, }, }; diff --git a/examples/protocols/mqtt/ssl_ds/main/client.crt b/examples/protocols/mqtt/ssl_ds/main/client.crt deleted file mode 100644 index 7a3074b907..0000000000 --- a/examples/protocols/mqtt/ssl_ds/main/client.crt +++ /dev/null @@ -1 +0,0 @@ -Please paste your client certificate here (follow instructions in README.md) diff --git a/examples/protocols/mqtt/ssl_ds/main/idf_component.yml b/examples/protocols/mqtt/ssl_ds/main/idf_component.yml new file mode 100644 index 0000000000..80c7c822a8 --- /dev/null +++ b/examples/protocols/mqtt/ssl_ds/main/idf_component.yml @@ -0,0 +1,3 @@ +## IDF Component Manager Manifest File +dependencies: + espressif/esp_secure_cert_mgr: "^2.0.0" diff --git a/examples/protocols/mqtt/ssl_ds/partitions.csv b/examples/protocols/mqtt/ssl_ds/partitions.csv index 2e1b23d522..0c4ad775c5 100644 --- a/examples/protocols/mqtt/ssl_ds/partitions.csv +++ b/examples/protocols/mqtt/ssl_ds/partitions.csv @@ -1,6 +1,6 @@ # ESP-IDF Partition Table # Name, Type, SubType, Offset, Size, Flags -nvs,data,nvs,0x9000,24K, -phy_init,data,phy,0xf000,4K, -pre_prov,data,nvs,0x10000,0x3000, +esp_secure_cert,0x3F,,,0x2000, +nvs,data,nvs,,24K, +phy_init,data,phy,,4K, factory,app,factory,0x20000,1M, diff --git a/examples/protocols/mqtt/ssl_ds/sdkconfig.defaults b/examples/protocols/mqtt/ssl_ds/sdkconfig.defaults index 4b0421e1ab..94e282f1d6 100644 --- a/examples/protocols/mqtt/ssl_ds/sdkconfig.defaults +++ b/examples/protocols/mqtt/ssl_ds/sdkconfig.defaults @@ -1 +1,7 @@ CONFIG_PARTITION_TABLE_CUSTOM=y +# Setting partition table offset to 0xC000 would make the address of +# `esp_secure_cert` partition as 0xD000 (comes next in the sequence). +# Modules that are programmed with Espressif Secure Pre Provisioining service +# uses this offset for `esp_secure_cert` and hence this change aligns this example +# to work on those modules. +CONFIG_PARTITION_TABLE_OFFSET=0xC000 diff --git a/examples/protocols/mqtt/ws/mqtt_ws_example_test.py b/examples/protocols/mqtt/ws/mqtt_ws_example_test.py index 72d4fa71e7..c24cfec336 100644 --- a/examples/protocols/mqtt/ws/mqtt_ws_example_test.py +++ b/examples/protocols/mqtt/ws/mqtt_ws_example_test.py @@ -1,9 +1,6 @@ -from __future__ import print_function, unicode_literals - import os import re import sys -from builtins import str from threading import Event, Thread import paho.mqtt.client as mqtt diff --git a/examples/protocols/mqtt/wss/mqtt_wss_example_test.py b/examples/protocols/mqtt/wss/mqtt_wss_example_test.py index 9f8ab12692..c0a1454dc5 100644 --- a/examples/protocols/mqtt/wss/mqtt_wss_example_test.py +++ b/examples/protocols/mqtt/wss/mqtt_wss_example_test.py @@ -1,10 +1,7 @@ -from __future__ import unicode_literals - import os import re import ssl import sys -from builtins import str from threading import Event, Thread import paho.mqtt.client as mqtt diff --git a/examples/protocols/mqtt5/sdkconfig.ci b/examples/protocols/mqtt5/sdkconfig.ci index 0673297b05..f4a0a7e403 100644 --- a/examples/protocols/mqtt5/sdkconfig.ci +++ b/examples/protocols/mqtt5/sdkconfig.ci @@ -7,3 +7,4 @@ CONFIG_EXAMPLE_ETH_MDIO_GPIO=18 CONFIG_EXAMPLE_ETH_PHY_RST_GPIO=5 CONFIG_EXAMPLE_ETH_PHY_ADDR=1 CONFIG_MQTT_PROTOCOL_5=y +CONFIG_BROKER_URL="mqtt://${EXAMPLE_MQTTV5_BROKER_TCP}" diff --git a/examples/protocols/slip/slip_udp/README.md b/examples/protocols/slip/slip_udp/README.md deleted file mode 100644 index e83944da84..0000000000 --- a/examples/protocols/slip/slip_udp/README.md +++ /dev/null @@ -1,86 +0,0 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | - -# SLIP device client - -(See the README.md file in the upper level 'examples' directory for more information about examples.) - -## Overview - -This provides SLIP support for connection to Contiki gateway devices, allowing the ESP platform board to be used to bridge between low-power networks and IP (Wifi / Ethernet). - -## How to use example - -### Hardware Required - -To run this example, you need an ESP32 dev board (e.g. ESP32-WROVER Kit) or ESP32 core board (e.g. ESP32-DevKitC). -For test purpose, you also need a SLIP capable gateway device, such as anything running [Contiki](https://github.com/contiki-os/contiki) gateway firmware. -You can also try other modules as long as they implement the SLIP protocol (e.g. linux device with slip module loaded) - -#### Setup a test SLIP device - -It is possible to configure any device with linux and a serial interface -(e.g. raspberry PI or a PC with USB to serial bridge) to enable SLIP interface. - -To test this example with such device, please follow these steps: - -- Configure IPv4 mode in the example configuration menu - -- Setup SLIP interface -``` -slattach -v -L -s 115200 -p slip /dev/ttyAMA0 -``` -where the `/dev/ttyAMA0` is the device's serial port - -- Configure IP addresses -``` -ifconfig sl0 10.0.0.1 dstaddr 10.0.0.2 -``` -where the `10.0.0.2` is IPv4 address of the ESP platform board - -- Send and receive back UDP packets, as the example implements UDP echo server -``` -nc -u 10.0.0.2 5678 -``` - -#### Pin Assignment - -**Note:** The following pin assignments are used by default which can be changed in menuconfig. - -| ESP32 | Gateway | -| ------ | -------------- | -| GPIO4 | RX | -| GPIO36 | TX | -| GND | GND | -| 3v3 | VCC | - -### Configure the project - -Open the project configuration menu (`idf.py menuconfig`). Then go into `Example Configuration` menu. - -- Choose the RX and TX pins -- Choose port number and IP protocol for socket udp server -For use in external projects `SLIP support` must be enabled under the `components/lwip` menu. - - -### Build and Flash - -Run `idf.py -p PORT flash monitor` to build and flash the project.. - -(To exit the serial monitor, type ``Ctrl-]``.) - -See the [Getting Started Guide](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/index.html) for full steps to configure and use ESP-IDF to build projects. - - - -## Troubleshooting - -1. Invalid slip packets - -Many slip devices use additional messages for things like ipv6 prefix configuration (or sending log messages over the SLIP serial port). This is supported in the driver through the use of an `rx_filter` function that is called on receipt of all packets and can be used to filter packets prior to passing them to the stack. - -2. No packets received - -The first layer to check is the serial port, you can enable debugging of the SLIP component by setting the global log level to `DEBUG`, or changing the slip component log levbel with `esp_log_level_set("esp-netif_lwip-slip", ESP_LOG_DEBUG);` - -(For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you as soon as possible.) diff --git a/examples/protocols/slip/slip_udp/components/slip_modem/CMakeLists.txt b/examples/protocols/slip/slip_udp/components/slip_modem/CMakeLists.txt deleted file mode 100644 index 838d5a975a..0000000000 --- a/examples/protocols/slip/slip_udp/components/slip_modem/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SLIP Modem Component - -idf_component_register( - SRCS "library/slip_modem.c" - INCLUDE_DIRS "include" - REQUIRES esp_netif driver -) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/protocols/slip/slip_udp/components/slip_modem/include/slip_modem.h b/examples/protocols/slip/slip_udp/components/slip_modem/include/slip_modem.h deleted file mode 100644 index 2cbd4be519..0000000000 --- a/examples/protocols/slip/slip_udp/components/slip_modem/include/slip_modem.h +++ /dev/null @@ -1,68 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#include -#include - -#include "esp_netif.h" -#include "esp_netif_slip.h" - -#include "driver/uart.h" - -// Forward declare modem object -typedef struct esp_slip_modem esp_slip_modem_t; - -// Filter callbacks for handling application specific slip messages -typedef bool slip_rx_filter_cb_t(void *ctx, uint8_t *data, uint32_t len); - - -/** @brief Configuration structure for SLIP modem interface - * - */ -typedef struct { - uart_port_t uart_dev; /* UART device for reading and writing SLIP information, this must be initialised externally */ - - int uart_tx_pin; /* UART TX pin number */ - int uart_rx_pin; /* UART TX pin number */ - - uint32_t uart_baud; /* UART baud rate */ - - uint32_t rx_buffer_len; /* Length of buffer for RX messages */ - - slip_rx_filter_cb_t *rx_filter; /* Filter for parsing out non-SLIP messages from incoming SLIP stream */ - void *rx_filter_ctx; /* Context to be passed to SLIP filter function */ - -} esp_slip_modem_config_t; - - -/** @brief Create a slip modem - * - * @param[in] slip configured esp netif - * @param[in] configuration for the slip modem - * - * @returns - * - slip modem driver glue object - */ -void *esp_slip_modem_create(esp_netif_t *slip_netif, esp_slip_modem_config_t *modem_config); - -/** @brief Destroy a slip modem - * - * @param[in] slip modem object for destruction - * - * @return - * - ESP_OK on success - */ -esp_err_t esp_slip_modem_destroy(esp_slip_modem_t *slip_modem); diff --git a/examples/protocols/slip/slip_udp/components/slip_modem/library/slip_modem.c b/examples/protocols/slip/slip_udp/components/slip_modem/library/slip_modem.c deleted file mode 100644 index 816ffdded9..0000000000 --- a/examples/protocols/slip/slip_udp/components/slip_modem/library/slip_modem.c +++ /dev/null @@ -1,227 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "slip_modem.h" - -#include "esp_netif.h" -#include "esp_netif_slip.h" -#include "esp_event.h" -#include "esp_log.h" - -#define SLIP_RX_TASK_PRIORITY 10 -#define SLIP_RX_TASK_STACK_SIZE (4 * 1024) - -static const char *TAG = "esp-slip_modem"; - - -// UART container object -typedef struct { - // UART device number for SIO use - uart_port_t uart_dev; - - // UART baud rate for configuration - uint32_t uart_baud; - - // UART TX pin for configuration - int uart_tx_pin; - - // UART RX pin for configuration - int uart_rx_pin; - - // QueueHandle for uart driver - QueueHandle_t uart_queue; - - // TaskHandle for receive task - TaskHandle_t uart_rx_task; -} esp_slip_uart_t; - - -// Modem object, implements glue logic for slip_driver and esp_netif -struct esp_slip_modem { - // ESP base netif driver - esp_netif_driver_base_t base; - - // Uart for use with slip - esp_slip_uart_t uart; - - // Buffer for incoming messages - uint8_t *buffer; - uint32_t buffer_len; - - // Filter callbacks for application-specific slip message handling - slip_rx_filter_cb_t *rx_filter; - void *rx_filter_ctx; - - // Running flag - bool running; -}; - - -// Forward function declaration -static void esp_slip_modem_uart_rx_task(void *arg); -static esp_err_t esp_slip_modem_post_attach(esp_netif_t *esp_netif, void *args); - -// Create a new slip netif -void *esp_slip_modem_create(esp_netif_t *slip_netif, esp_slip_modem_config_t *modem_config) -{ - ESP_LOGI(TAG, "%s: Creating slip modem (netif: %p)", __func__, slip_netif); - - ESP_LOGD(TAG, "%s (netif: %p)", __func__, slip_netif); - - esp_slip_modem_t *slip_modem = calloc(1, sizeof(esp_slip_modem_t)); - if (!slip_modem) { - ESP_LOGE(TAG, "create netif glue failed"); - return NULL; - } - - // Attach driver and post_attach callbacks - slip_modem->base.post_attach = esp_slip_modem_post_attach; - - // Attach config - slip_modem->buffer_len = modem_config->rx_buffer_len; - - slip_modem->rx_filter = modem_config->rx_filter; - slip_modem->rx_filter_ctx = modem_config->rx_filter_ctx; - - slip_modem->uart.uart_dev = modem_config->uart_dev; - slip_modem->uart.uart_baud = modem_config->uart_baud; - slip_modem->uart.uart_rx_pin = modem_config->uart_rx_pin; - slip_modem->uart.uart_tx_pin = modem_config->uart_tx_pin; - - // Return new modem, with a cast to the first item - return &slip_modem->base; -} - -// Internal handler called on driver start -static esp_err_t esp_slip_driver_start(esp_slip_modem_t *slip_modem) -{ - ESP_LOGD(TAG, "%s: Starting SLIP modem (modem %p)", __func__, slip_modem); - - // Allocate RX buffer if one does not exist - if (slip_modem->buffer == NULL) { - slip_modem->buffer = malloc(slip_modem->buffer_len); - } - if (slip_modem->buffer == NULL) { - ESP_LOGE(TAG, "error allocating rx buffer"); - return ESP_ERR_NO_MEM; - } - - // Build configuration - uart_config_t uart_config = { - .baud_rate = slip_modem->uart.uart_baud, - .data_bits = UART_DATA_8_BITS, - .parity = UART_PARITY_DISABLE, - .stop_bits = UART_STOP_BITS_1, - .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, - }; - - // Initialise uart - ESP_ERROR_CHECK(uart_param_config(slip_modem->uart.uart_dev, &uart_config)); - - // Set UART pins - ESP_ERROR_CHECK(uart_set_pin(slip_modem->uart.uart_dev, slip_modem->uart.uart_tx_pin, slip_modem->uart.uart_rx_pin, 0, 0)); - - // Install UART driver - ESP_ERROR_CHECK(uart_driver_install(slip_modem->uart.uart_dev, slip_modem->buffer_len, slip_modem->buffer_len, 10, &slip_modem->uart.uart_queue, 0)); - - // Start slip RX task - slip_modem->running = true; - xTaskCreate(esp_slip_modem_uart_rx_task, "slip_modem_uart_rx_task", SLIP_RX_TASK_STACK_SIZE, slip_modem, SLIP_RX_TASK_PRIORITY, &slip_modem->uart.uart_rx_task); - - // Finally, initialise slip network interface - esp_netif_action_start(slip_modem->base.netif, 0, 0, 0); - - return ESP_OK; -} - - -esp_err_t esp_slip_modem_destroy(esp_slip_modem_t *slip_modem) -{ - // Stop slip driver - esp_netif_action_stop(slip_modem->base.netif, 0, 0, 0); - - // Stop uart rx task - vTaskDelete(slip_modem->uart.uart_rx_task); - - // Delete driver - uart_driver_delete(slip_modem->uart.uart_dev); - - // Free slip interface - free(slip_modem); - - return ESP_OK; -} - -// Modem transmit for glue logic -static esp_err_t esp_slip_modem_transmit(void *slip_driver, void *buffer, size_t len) -{ - ESP_LOGD(TAG, "%s", __func__); - ESP_LOG_BUFFER_HEXDUMP(TAG, buffer, len, ESP_LOG_DEBUG); - esp_slip_modem_t *slip_modem = (esp_slip_modem_t *) slip_driver; - - int32_t res = uart_write_bytes(slip_modem->uart.uart_dev, (char *)buffer, len); - if (res < 0) { - // Handle errors - ESP_LOGE(TAG, "%s: uart_write_bytes error %i", __func__, res); - return ESP_FAIL; - } - return ESP_OK; -} - -// Post-attach handler for netif -static esp_err_t esp_slip_modem_post_attach(esp_netif_t *esp_netif, void *args) -{ - esp_slip_modem_t *slip_modem = (esp_slip_modem_t *) args; - - ESP_LOGD(TAG, "%s (netif: %p args: %p)", __func__, esp_netif, args); - - const esp_netif_driver_ifconfig_t driver_ifconfig = { - .driver_free_rx_buffer = NULL, - .transmit = esp_slip_modem_transmit, - .handle = slip_modem, - }; - - slip_modem->base.netif = esp_netif; - ESP_ERROR_CHECK(esp_netif_set_driver_config(esp_netif, &driver_ifconfig)); - - esp_slip_driver_start(slip_modem); - - return ESP_OK; -} - -static void esp_slip_modem_uart_rx_task(void *arg) -{ - esp_slip_modem_t *slip_modem = (esp_slip_modem_t *) arg; - - ESP_LOGD(TAG, "Start SLIP modem RX task (slip_modem %p filter: %p)", slip_modem, slip_modem->rx_filter); - ESP_LOGD(TAG, "Uart: %d, buffer: %p (%d bytes)", slip_modem->uart.uart_dev, slip_modem->buffer, slip_modem->buffer_len); - - while (slip_modem->running == true) { - // Read data from the UART - int len = uart_read_bytes(slip_modem->uart.uart_dev, slip_modem->buffer, slip_modem->buffer_len, 1 / portTICK_PERIOD_MS); - - if (len > 0) { - - // Log slip RX data - ESP_LOGD(TAG, "rx %d bytes", len); - ESP_LOG_BUFFER_HEX_LEVEL(TAG, slip_modem->buffer, len, ESP_LOG_DEBUG); - - // Ensure null termination - slip_modem->buffer[len] = '\0'; - - // Filter if provided - if ((slip_modem->rx_filter != NULL) && slip_modem->rx_filter(slip_modem->rx_filter_ctx, slip_modem->buffer, len)) { - continue; - } - - // Pass received bytes in to slip interface - esp_netif_receive(slip_modem->base.netif, slip_modem->buffer, len, NULL); - } - - // Yeild to allow other tasks to progress - vTaskDelay(1 * portTICK_PERIOD_MS); - } -} diff --git a/examples/protocols/slip/slip_udp/main/CMakeLists.txt b/examples/protocols/slip/slip_udp/main/CMakeLists.txt deleted file mode 100644 index eace917e55..0000000000 --- a/examples/protocols/slip/slip_udp/main/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Slip client example - -idf_component_register( - SRCS "slip_client_main.c" - INCLUDE_DIRS "." - REQUIRES esp_netif slip_modem driver -) -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/examples/protocols/slip/slip_udp/main/Kconfig.projbuild b/examples/protocols/slip/slip_udp/main/Kconfig.projbuild deleted file mode 100644 index e23abfa081..0000000000 --- a/examples/protocols/slip/slip_udp/main/Kconfig.projbuild +++ /dev/null @@ -1,38 +0,0 @@ -menu "Example Configuration" - - menu "UART Configuration" - config EXAMPLE_UART_TX_PIN - int "TXD Pin Number" - default 4 - range 0 36 - help - Pin number of UART TX. - - config EXAMPLE_UART_RX_PIN - int "RXD Pin Number" - default 36 - range 0 36 - help - Pin number of UART RX. - - config EXAMPLE_UART_BAUD - int "UART baud rate" - default 115200 - help - Baud rate for UART communication - - endmenu - - config EXAMPLE_UDP_PORT - int "Port for UDP echo server" - default 5678 - help - Port for UDP echo server in example - - config EXAMPLE_IPV4 - bool "Test with IPv4 address" - default n - help - Test interface using IPv4 - -endmenu diff --git a/examples/protocols/slip/slip_udp/main/slip_client_main.c b/examples/protocols/slip/slip_udp/main/slip_client_main.c deleted file mode 100644 index 8bb131f986..0000000000 --- a/examples/protocols/slip/slip_udp/main/slip_client_main.c +++ /dev/null @@ -1,247 +0,0 @@ -/* SLIP Client Example - - This example code is in the Public Domain (or CC0 licensed, at your option.) - - Unless required by applicable law or agreed to in writing, this - software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR - CONDITIONS OF ANY KIND, either express or implied. -*/ -#include -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" - -#include "esp_system.h" -#include "esp_log.h" -#include "esp_event.h" -#include "esp_netif.h" -#include "esp_netif_slip.h" - -#include "lwip/sockets.h" - -#include "slip_modem.h" - -static const char *TAG = "SLIP_EXAMPLE"; - -#define STACK_SIZE (10 * 1024) -#define PRIORITY 10 - -static void udp_rx_tx_task(void *arg) -{ - char addr_str[128]; - uint8_t rx_buff[1024]; - - int sock = (int)arg; - - struct sockaddr_storage source_addr; - socklen_t socklen = sizeof(source_addr); - - - ESP_LOGI(TAG, "Starting node manager UDP task"); - - while (1) { - // Receive data - int len = recvfrom(sock, rx_buff, sizeof(rx_buff) - 1, 0, (struct sockaddr *)&source_addr, &socklen); - if (len < 0) { - ESP_LOGE(TAG, "recvfrom failed: errno %d", errno); - break; - } - - // Parse out address to string - if (source_addr.ss_family == PF_INET) { - inet_ntoa_r(((struct sockaddr_in *)&source_addr)->sin_addr.s_addr, addr_str, sizeof(addr_str) - 1); - } else if (source_addr.ss_family == PF_INET6) { - inet6_ntoa_r(((struct sockaddr_in6 *)&source_addr)->sin6_addr, addr_str, sizeof(addr_str) - 1); - } - - // Force null termination of received data and print - rx_buff[len] = 0; - ESP_LOGI(TAG, "Received '%s' from '%s'", rx_buff, addr_str); - - // Send data back - int err = sendto(sock, rx_buff, len, 0, (struct sockaddr *)&source_addr, socklen); - if (err < 0) { - ESP_LOGE(TAG, "sendto failed: errno %d", errno); - break; - } - } - - vTaskDelete(NULL); -} - -esp_err_t udp_rx_tx_init(void) -{ - // Setup bind address - struct sockaddr_in6 dest_addr; -#if CONFIG_EXAMPLE_IPV4 - sa_family_t family = AF_INET; - int ip_protocol = IPPROTO_IP; - struct sockaddr_in *dest_addr_ip4 = (struct sockaddr_in *)&dest_addr; - dest_addr_ip4->sin_addr.s_addr = htonl(INADDR_ANY); - dest_addr_ip4->sin_family = AF_INET; - dest_addr_ip4->sin_port = htons(CONFIG_EXAMPLE_UDP_PORT); - ip_protocol = IPPROTO_IP; -#else - sa_family_t family = AF_INET6; - int ip_protocol = IPPROTO_IPV6; - bzero(&dest_addr.sin6_addr.un, sizeof(dest_addr.sin6_addr.un)); - dest_addr.sin6_family = family; - dest_addr.sin6_port = htons(CONFIG_EXAMPLE_UDP_PORT); -#endif - - // Create socket - int sock = socket(family, SOCK_DGRAM, ip_protocol); - if (sock < 0) { - ESP_LOGE(TAG, "Unable to create socket: errno %d", errno); - return ESP_FAIL; - } - - // Disable IPv4 and reuse address - int opt = 1; - setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, &opt, sizeof(opt)); -#if !CONFIG_EXAMPLE_IPV4 - setsockopt(sock, IPPROTO_IPV6, IPV6_V6ONLY, &opt, sizeof(opt)); -#endif - - // Bind socket - int err = bind(sock, (struct sockaddr *)&dest_addr, sizeof(dest_addr)); - if (err < 0) { - ESP_LOGE(TAG, "Socket unable to bind: errno %d", errno); - return ESP_FAIL; - } - ESP_LOGI(TAG, "Socket bound, port %d", CONFIG_EXAMPLE_UDP_PORT); - - - // Start UDP rx thread - xTaskCreate(udp_rx_tx_task, "udp_rx_tx", STACK_SIZE, (void *)sock, PRIORITY, NULL); - - return ESP_OK; -} - -// Write a prefix to the contiki slip device -static void slip_set_prefix(esp_netif_t *slip_netif) -{ - uint8_t buff[10] = {0}; - - // Fetch the slip interface IP - const esp_ip6_addr_t *addr = esp_slip_get_ip6(slip_netif); - - ESP_LOGI(TAG, "%s: prefix set (%08x:%08x)", __func__, - lwip_ntohl(addr->addr[0]), lwip_ntohl(addr->addr[1])); - - // Build slip set message - buff[0] = '!'; - buff[1] = 'P'; - for (int i = 0; i < 2; i++) { - for (int j = 0; j < 4; j++) { - buff[2 + i * 4 + j] = addr->addr[i] >> (j * 8); - } - } - - // Write raw data out the slip interface - esp_netif_lwip_slip_raw_output(slip_netif, buff, 2 + 8); -} - -// slip_rx_filter filters incoming commands from the slip interface -// this implementation is designed for use with contiki slip devices -bool slip_rx_filter(void *ctx, uint8_t *data, uint32_t len) -{ - - esp_netif_t *slip_netif = (esp_netif_t *)ctx; - - if (data[1] == '?') { - switch (data[2]) { - case 'P': - ESP_LOGI(TAG, "Prefix request"); - slip_set_prefix(slip_netif); - - return true; - - default: - ESP_LOGI(TAG, "Unhandled request '%c'", data[2]); - break; - } - - return true; - - } else if (data[1] == '!') { - switch (data[2]) { - default: - ESP_LOGI(TAG, "Unhandled command '%c'", data[2]); - break; - } - } - - return false; -} - -#if CONFIG_EXAMPLE_IPV4 -static const esp_netif_ip_info_t s_slip_ip4 = { - .ip = { .addr = ESP_IP4TOADDR( 10, 0, 0, 2) }, -}; -#endif - -// Initialise the SLIP interface -esp_netif_t *slip_if_init(void) -{ - ESP_LOGI(TAG, "Initialising SLIP interface"); - - esp_netif_inherent_config_t base_cfg = ESP_NETIF_INHERENT_DEFAULT_SLIP() -#if CONFIG_EXAMPLE_IPV4 - base_cfg.ip_info = &s_slip_ip4; -#endif - esp_netif_config_t cfg = { .base = &base_cfg, - .driver = NULL, - .stack = ESP_NETIF_NETSTACK_DEFAULT_SLIP }; - - esp_netif_t *slip_netif = esp_netif_new(&cfg); - - esp_netif_slip_config_t slip_config; - - IP6_ADDR(&slip_config.ip6_addr, - lwip_htonl(0xfd0000), - lwip_htonl(0x00000000), - lwip_htonl(0x00000000), - lwip_htonl(0x00000001) - ); - - esp_netif_slip_set_params(slip_netif, &slip_config); - - ESP_LOGI(TAG, "Initialising SLIP modem"); - - esp_slip_modem_config_t modem_cfg = { - .uart_dev = UART_NUM_1, - - .uart_tx_pin = CONFIG_EXAMPLE_UART_TX_PIN, - .uart_rx_pin = CONFIG_EXAMPLE_UART_RX_PIN, - .uart_baud = CONFIG_EXAMPLE_UART_BAUD, - - .rx_buffer_len = 1024, - - .rx_filter = slip_rx_filter, - .rx_filter_ctx = slip_netif, - }; - - void *slip_modem = esp_slip_modem_create(slip_netif, &modem_cfg); - ESP_ERROR_CHECK(esp_netif_attach(slip_netif, slip_modem)); - - ESP_LOGI(TAG, "SLIP init complete"); - - return slip_netif; -} - -void app_main(void) -{ - // Setup networking - esp_netif_init(); - - esp_log_level_set("*", ESP_LOG_DEBUG); - - // Create event loop - ESP_ERROR_CHECK(esp_event_loop_create_default()); - - // Setup slip interface - slip_if_init(); - - // Setup UDP loopback service - udp_rx_tx_init(); -} diff --git a/examples/protocols/slip/slip_udp/sdkconfig.defaults b/examples/protocols/slip/slip_udp/sdkconfig.defaults deleted file mode 100644 index a0f094bcdd..0000000000 --- a/examples/protocols/slip/slip_udp/sdkconfig.defaults +++ /dev/null @@ -1,2 +0,0 @@ -# Override some defaults to enable SLIP -CONFIG_LWIP_SLIP_SUPPORT=y diff --git a/examples/protocols/sockets/tcp_client/CMakeLists.txt b/examples/protocols/sockets/tcp_client/CMakeLists.txt index 7015df7e4b..0d19ff5631 100644 --- a/examples/protocols/sockets/tcp_client/CMakeLists.txt +++ b/examples/protocols/sockets/tcp_client/CMakeLists.txt @@ -1,10 +1,14 @@ -# The following five lines of boilerplate have to be in your project's +# The following lines of boilerplate have to be in your project's # CMakeLists in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.16) -# (Not part of the boilerplate) -# This example uses an extra component for common functions such as Wi-Fi and Ethernet connection. -set(EXTRA_COMPONENT_DIRS $ENV{IDF_PATH}/examples/common_components/protocol_examples_common) +if(${IDF_TARGET} STREQUAL "linux") + list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/mocks/freertos/") + set(COMPONENTS main) + include($ENV{IDF_PATH}/tools/cmake/project.cmake) +else() + set(EXTRA_COMPONENT_DIRS $ENV{IDF_PATH}/examples/common_components/protocol_examples_common) + include($ENV{IDF_PATH}/tools/cmake/project.cmake) +endif() -include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(tcp_client) diff --git a/examples/protocols/sockets/tcp_client/README.md b/examples/protocols/sockets/tcp_client/README.md index 0ac216d4a1..0d90afe16c 100644 --- a/examples/protocols/sockets/tcp_client/README.md +++ b/examples/protocols/sockets/tcp_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | Linux | +| ----------------- | ----- | -------- | -------- | -------- | -------- | ----- | # TCP Client example @@ -8,13 +8,38 @@ The application creates a TCP socket and tries to connect to the server with predefined IP address and port number. When a connection is successfully established, the application sends message and waits for the answer. After the server's reply, application prints received reply as ASCII text, waits for 2 seconds and sends another message. -## How to use example +## Configure the project +This example can be configured to run on ESP32 and Linux target to communicate over IPv4 and IPv6. + +``` +idf.py menuconfig +``` + +Set following parameters under ```Example Configuration``` Options: + +* Set `IP version` of example to be IPV4 or IPV6. + +* Set `IPV4 Address` in case your chose IP version IPV4 above. + +* Set `IPV6 Address` in case your chose IP version IPV6 above. + * For IPv6 there's an additional option for ```Interface selection```. + * Enter the name of the interface to explicitely establish communication over a specific interface. + * On selecting ```Auto``` the example will find the first interface with an IPv6 address and use it. + +* Set `Port` number that represents remote port the example will connect to. + +Configure Wi-Fi or Ethernet under "Example Connection Configuration" menu. See "Establishing Wi-Fi or Ethernet Connection" section in [examples/protocols/README.md](../../README.md) for more details. + + +Note: please replace `192.168.0.167 3333` with desired IPV4/IPV6 address (displayed in monitor console) and port number in the following command. + + +## How to use example: In order to create TCP server that communicates with TCP Client example, choose one of the following options. There are many host-side tools which can be used to interact with the UDP/TCP server/client. One command line tool is [netcat](http://netcat.sourceforge.net) which can send and receive many kinds of packets. -Note: please replace `192.168.0.167 3333` with desired IPV4/IPV6 address (displayed in monitor console) and port number in the following command. In addition to those tools, simple Python scripts can be found under sockets/scripts directory. Every script is designed to interact with one of the examples. @@ -24,35 +49,24 @@ nc -l 192.168.0.167 3333 ``` ### Python scripts -Script example_test.py could be used as a counter part to the tcp-client project, ip protocol name (IPv4 or IPv6) shall be stated as argument. Example: +Script example_test.py could be used as a counter part to the tcp-client project, ip protocol name (IPv4 or IPv6) shall be stated as argument. +Note that this script is used in automated tests, as well, so the IDF test framework packages need to be imported. +Please run the following commands to configure the terminal to execute the script. +``` +export PYTHONPATH="$IDF_PATH/tools:$IDF_PATH/tools/ci/python_packages" +python -m pip install -r $IDF_PATH/tools/ci/python_packages/ttfw_idf/requirements.txt +``` + +Example: ``` python example_test.py IPv4 ``` -Note that this script is used in automated tests, as well, so the IDF test framework packages need to be imported; -please add `$IDF_PATH/tools/ci/python_packages` to `PYTHONPATH`. - ## Hardware Required This example can be run on any commonly available ESP32 development board. +This example can also run on any Linux environment. -## Configure the project - -``` -idf.py menuconfig -``` - -Set following parameters under Example Configuration Options: - -* Set `IP version` of example to be IPV4 or IPV6. - -* Set `IPV4 Address` in case your chose IP version IPV4 above. - -* Set `IPV6 Address` in case your chose IP version IPV6 above. - -* Set `Port` number that represents remote port the example will connect to. - -Configure Wi-Fi or Ethernet under "Example Connection Configuration" menu. See "Establishing Wi-Fi or Ethernet Connection" section in [examples/protocols/README.md](../../README.md) for more details. ## Build and Flash diff --git a/examples/protocols/sockets/tcp_client/components/esp_stubs/CMakeLists.txt b/examples/protocols/sockets/tcp_client/components/esp_stubs/CMakeLists.txt new file mode 100644 index 0000000000..74f75ec2a8 --- /dev/null +++ b/examples/protocols/sockets/tcp_client/components/esp_stubs/CMakeLists.txt @@ -0,0 +1,6 @@ +if(${IDF_TARGET} STREQUAL "linux") + idf_component_register(SRCS + esp_stubs/esp_stubs.c + INCLUDE_DIRS . include/stubs + REQUIRES main) +endif() diff --git a/examples/protocols/sockets/tcp_client/components/esp_stubs/esp_stubs/esp_stubs.c b/examples/protocols/sockets/tcp_client/components/esp_stubs/esp_stubs/esp_stubs.c new file mode 100644 index 0000000000..51141e0bc5 --- /dev/null +++ b/examples/protocols/sockets/tcp_client/components/esp_stubs/esp_stubs/esp_stubs.c @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include +#include "esp_err.h" +#include "esp_log.h" + +extern void app_main(void); + +esp_err_t esp_event_loop_create_default(void) +{ + return ESP_OK; +} + +esp_err_t esp_netif_init(void) +{ + return ESP_OK; +} + +esp_err_t example_connect(void) +{ + return ESP_OK; +} + +esp_err_t nvs_flash_init(void) +{ + return ESP_OK; +} + +int main() +{ + app_main(); + + return 0; +} diff --git a/examples/protocols/sockets/tcp_client/components/esp_stubs/include/stubs/esp_event.h b/examples/protocols/sockets/tcp_client/components/esp_stubs/include/stubs/esp_event.h new file mode 100644 index 0000000000..79887049cf --- /dev/null +++ b/examples/protocols/sockets/tcp_client/components/esp_stubs/include/stubs/esp_event.h @@ -0,0 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include "esp_err.h" + +esp_err_t esp_event_loop_create_default(void); diff --git a/examples/protocols/sockets/tcp_client/components/esp_stubs/include/stubs/esp_netif.h b/examples/protocols/sockets/tcp_client/components/esp_stubs/include/stubs/esp_netif.h new file mode 100644 index 0000000000..860d7a620b --- /dev/null +++ b/examples/protocols/sockets/tcp_client/components/esp_stubs/include/stubs/esp_netif.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include +#include +#include +#include "esp_err.h" + +esp_err_t esp_netif_init(void); diff --git a/examples/protocols/sockets/tcp_client/components/esp_stubs/include/stubs/nvs_flash.h b/examples/protocols/sockets/tcp_client/components/esp_stubs/include/stubs/nvs_flash.h new file mode 100644 index 0000000000..9d138a838a --- /dev/null +++ b/examples/protocols/sockets/tcp_client/components/esp_stubs/include/stubs/nvs_flash.h @@ -0,0 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include "esp_err.h" + +esp_err_t nvs_flash_init(void); diff --git a/examples/protocols/sockets/tcp_client/components/esp_stubs/include/stubs/protocol_examples_common.h b/examples/protocols/sockets/tcp_client/components/esp_stubs/include/stubs/protocol_examples_common.h new file mode 100644 index 0000000000..6f8bf0706f --- /dev/null +++ b/examples/protocols/sockets/tcp_client/components/esp_stubs/include/stubs/protocol_examples_common.h @@ -0,0 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include "esp_err.h" + +esp_err_t example_connect(void); diff --git a/examples/protocols/sockets/tcp_client/example_test.py b/examples/protocols/sockets/tcp_client/example_test.py index 3427296b5b..6ab409fda5 100644 --- a/examples/protocols/sockets/tcp_client/example_test.py +++ b/examples/protocols/sockets/tcp_client/example_test.py @@ -5,14 +5,10 @@ # CONDITIONS OF ANY KIND, either express or implied. # -*- coding: utf-8 -*- - -from __future__ import print_function, unicode_literals - import os import re import socket import sys -from builtins import input from threading import Event, Thread import netifaces diff --git a/examples/protocols/sockets/tcp_client/main/CMakeLists.txt b/examples/protocols/sockets/tcp_client/main/CMakeLists.txt index 9ff632b1e0..acea8ee344 100644 --- a/examples/protocols/sockets/tcp_client/main/CMakeLists.txt +++ b/examples/protocols/sockets/tcp_client/main/CMakeLists.txt @@ -1,2 +1,13 @@ -idf_component_register(SRCS "tcp_client.c" - INCLUDE_DIRS ".") +if(${IDF_TARGET} STREQUAL "linux") + set(requires esp_stubs) +endif() + +if("${CONFIG_EXAMPLE_IPV4}" STREQUAL y) + set(tcp_client_ip tcp_client_v4.c) +else() + set(tcp_client_ip tcp_client_v6.c) +endif() + +idf_component_register(SRCS "tcp_client_main.c" "${tcp_client_ip}" + INCLUDE_DIRS "." + REQUIRES ${requires}) diff --git a/examples/protocols/sockets/tcp_client/main/Kconfig.projbuild b/examples/protocols/sockets/tcp_client/main/Kconfig.projbuild index a1f5cea4a3..ca0de49c39 100644 --- a/examples/protocols/sockets/tcp_client/main/Kconfig.projbuild +++ b/examples/protocols/sockets/tcp_client/main/Kconfig.projbuild @@ -35,6 +35,26 @@ menu "Example Configuration" help The remote port to which the client example will connect to. + choice EXAMPLE_INTERFACE + prompt "Interface selection" + depends on EXAMPLE_IPV6 + help + Example can use either "Auto" or "User specified". + + config EXAMPLE_IFACE_AUTO + bool "Auto" + + config EXAMPLE_USER_SPECIFIED_IFACE + bool "User specified interface" + endchoice + + config EXAMPLE_USER_SPECIFIED_IFACE_NAME + string "User specified interface name" + default "st1" + depends on EXAMPLE_USER_SPECIFIED_IFACE + help + This interface will be used for communication. + choice EXAMPLE_SOCKET_IP_INPUT prompt "Socket example source" default EXAMPLE_SOCKET_IP_INPUT_STRING diff --git a/examples/protocols/sockets/tcp_client/main/tcp_client_main.c b/examples/protocols/sockets/tcp_client/main/tcp_client_main.c new file mode 100644 index 0000000000..2b2a27d420 --- /dev/null +++ b/examples/protocols/sockets/tcp_client/main/tcp_client_main.c @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include "nvs_flash.h" +#include "esp_netif.h" +#include "protocol_examples_common.h" +#include "esp_event.h" + + +extern void tcp_client(void); + +void app_main(void) +{ + ESP_ERROR_CHECK(nvs_flash_init()); + ESP_ERROR_CHECK(esp_netif_init()); + ESP_ERROR_CHECK(esp_event_loop_create_default()); + + /* This helper function configures Wi-Fi or Ethernet, as selected in menuconfig. + * Read "Establishing Wi-Fi or Ethernet Connection" section in + * examples/protocols/README.md for more information about this function. + */ + ESP_ERROR_CHECK(example_connect()); + + tcp_client(); +} diff --git a/examples/protocols/sockets/tcp_client/main/tcp_client.c b/examples/protocols/sockets/tcp_client/main/tcp_client_v4.c similarity index 56% rename from examples/protocols/sockets/tcp_client/main/tcp_client.c rename to examples/protocols/sockets/tcp_client/main/tcp_client_v4.c index a1977c49d6..e50e974895 100644 --- a/examples/protocols/sockets/tcp_client/main/tcp_client.c +++ b/examples/protocols/sockets/tcp_client/main/tcp_client_v4.c @@ -1,33 +1,24 @@ -/* BSD Socket API Example - - This example code is in the Public Domain (or CC0 licensed, at your option.) - - Unless required by applicable law or agreed to in writing, this - software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR - CONDITIONS OF ANY KIND, either express or implied. -*/ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include "sdkconfig.h" #include -#include -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "freertos/event_groups.h" -#include "esp_system.h" -#include "esp_wifi.h" -#include "esp_event.h" -#include "esp_log.h" -#include "nvs_flash.h" +#include +#include +#include +#include // struct addrinfo +#include #include "esp_netif.h" -#include "protocol_examples_common.h" +#include "esp_log.h" +#if defined(CONFIG_EXAMPLE_SOCKET_IP_INPUT_STDIN) #include "addr_from_stdin.h" -#include "lwip/err.h" -#include "lwip/sockets.h" - +#endif #if defined(CONFIG_EXAMPLE_IPV4) #define HOST_IP_ADDR CONFIG_EXAMPLE_IPV4_ADDR -#elif defined(CONFIG_EXAMPLE_IPV6) -#define HOST_IP_ADDR CONFIG_EXAMPLE_IPV6_ADDR -#else +#elif defined(CONFIG_EXAMPLE_SOCKET_IP_INPUT_STDIN) #define HOST_IP_ADDR "" #endif @@ -36,7 +27,8 @@ static const char *TAG = "example"; static const char *payload = "Message from ESP32 "; -static void tcp_client_task(void *pvParameters) + +void tcp_client(void) { char rx_buffer[128]; char host_ip[] = HOST_IP_ADDR; @@ -46,23 +38,16 @@ static void tcp_client_task(void *pvParameters) while (1) { #if defined(CONFIG_EXAMPLE_IPV4) struct sockaddr_in dest_addr; - dest_addr.sin_addr.s_addr = inet_addr(host_ip); + inet_pton(AF_INET, host_ip, &dest_addr.sin_addr); dest_addr.sin_family = AF_INET; dest_addr.sin_port = htons(PORT); addr_family = AF_INET; ip_protocol = IPPROTO_IP; -#elif defined(CONFIG_EXAMPLE_IPV6) - struct sockaddr_in6 dest_addr = { 0 }; - inet6_aton(host_ip, &dest_addr.sin6_addr); - dest_addr.sin6_family = AF_INET6; - dest_addr.sin6_port = htons(PORT); - dest_addr.sin6_scope_id = esp_netif_get_netif_impl_index(EXAMPLE_INTERFACE); - addr_family = AF_INET6; - ip_protocol = IPPROTO_IPV6; #elif defined(CONFIG_EXAMPLE_SOCKET_IP_INPUT_STDIN) struct sockaddr_storage dest_addr = { 0 }; ESP_ERROR_CHECK(get_addr_from_stdin(PORT, SOCK_STREAM, &ip_protocol, &addr_family, &dest_addr)); #endif + int sock = socket(addr_family, SOCK_STREAM, ip_protocol); if (sock < 0) { ESP_LOGE(TAG, "Unable to create socket: errno %d", errno); @@ -70,7 +55,7 @@ static void tcp_client_task(void *pvParameters) } ESP_LOGI(TAG, "Socket created, connecting to %s:%d", host_ip, PORT); - int err = connect(sock, (struct sockaddr *)&dest_addr, sizeof(struct sockaddr_in6)); + int err = connect(sock, (struct sockaddr *)&dest_addr, sizeof(dest_addr)); if (err != 0) { ESP_LOGE(TAG, "Socket unable to connect: errno %d", errno); break; @@ -96,8 +81,6 @@ static void tcp_client_task(void *pvParameters) ESP_LOGI(TAG, "Received %d bytes from %s:", len, host_ip); ESP_LOGI(TAG, "%s", rx_buffer); } - - vTaskDelay(2000 / portTICK_PERIOD_MS); } if (sock != -1) { @@ -106,20 +89,4 @@ static void tcp_client_task(void *pvParameters) close(sock); } } - vTaskDelete(NULL); -} - -void app_main(void) -{ - ESP_ERROR_CHECK(nvs_flash_init()); - ESP_ERROR_CHECK(esp_netif_init()); - ESP_ERROR_CHECK(esp_event_loop_create_default()); - - /* This helper function configures Wi-Fi or Ethernet, as selected in menuconfig. - * Read "Establishing Wi-Fi or Ethernet Connection" section in - * examples/protocols/README.md for more information about this function. - */ - ESP_ERROR_CHECK(example_connect()); - - xTaskCreate(tcp_client_task, "tcp_client", 4096, NULL, 5, NULL); } diff --git a/examples/protocols/sockets/tcp_client/main/tcp_client_v6.c b/examples/protocols/sockets/tcp_client/main/tcp_client_v6.c new file mode 100644 index 0000000000..73acd117e2 --- /dev/null +++ b/examples/protocols/sockets/tcp_client/main/tcp_client_v6.c @@ -0,0 +1,255 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include "sdkconfig.h" +#include +#include +#include +#include +#include // struct addrinfo +#include +#include "esp_netif.h" +#include "esp_log.h" +#if defined(CONFIG_EXAMPLE_SOCKET_IP_INPUT_STDIN) +#include "addr_from_stdin.h" +#endif + +#if defined(CONFIG_EXAMPLE_IPV6_ADDR) +#define HOST_IP_ADDR CONFIG_EXAMPLE_IPV6_ADDR +#else +#define HOST_IP_ADDR "" +#endif + +#define PORT CONFIG_EXAMPLE_PORT + +static const char *TAG = "example"; +static const char *payload = "Message from ESP32 "; + +#if defined(CONFIG_IDF_TARGET_LINUX) +// Checks for Global address, Unique Unicast(RFC4193) and link-local address. +#define ip6_addr_isglobal(ip6addr) ((((ip6addr)->sin6_addr.s6_addr[0] & htonl(0xe0000000UL)) & htonl(0x20000000UL)) || \ + (((ip6addr)->sin6_addr.s6_addr[0] & htonl(0xff000000UL)) & htonl(0xfc000000UL)) || \ + (((ip6addr)->sin6_addr.s6_addr[0] & htonl(0xff000000UL)) & htonl(0xfe800000UL))) + + +/** + * @brief In case of Auto mode returns the interface name with a valid IPv6 address or + * In case the user has specified interface, validates and returns the interface name. + * + * @param[out] interface Name of the interface in as a string. + * + * @return 0 incase of success. + */ +static int get_src_iface(char *interface) +{ + struct ifaddrs *ifap, *ifa; + char src_addr_str[INET6_ADDRSTRLEN]; + + if (getifaddrs(&ifap) == -1) { + ESP_LOGE(TAG, "getifaddrs failed"); + return -1; + } + + for (ifa = ifap; ifa; ifa = ifa->ifa_next) { + if (ifa->ifa_addr && ifa->ifa_addr->sa_family == AF_INET6) { +#if defined(CONFIG_EXAMPLE_USER_SPECIFIED_IFACE) + if (0 == strcmp(CONFIG_EXAMPLE_USER_SPECIFIED_IFACE_NAME, ifa->ifa_name)) { + strcpy(interface, ifa->ifa_name); + freeifaddrs(ifap); + ESP_LOGI(TAG, "Interface: %s", interface); + return 0; + } +#else + strcpy(interface, ifa->ifa_name); + getnameinfo(ifa->ifa_addr, sizeof(struct sockaddr_in6), src_addr_str, + sizeof(src_addr_str), NULL, 0, NI_NUMERICHOST); + + struct sockaddr_in6 *src_addr = (struct sockaddr_in6 *) ifa->ifa_addr; + inet_ntop(AF_INET6, &(src_addr->sin6_addr), src_addr_str, INET6_ADDRSTRLEN); + + if (ip6_addr_isglobal(src_addr)) { + //Return as we have the source address + freeifaddrs(ifap); + ESP_LOGI(TAG, "Interface: %s", interface); + return 0; + } +#endif // #if defined(CONFIG_EXAMPLE_USER_SPECIFIED_IFACE) + } + } + + freeifaddrs(ifap); + return -1; +} +#else + +static esp_netif_t *get_esp_netif_from_iface(char *interface_i) +{ + esp_netif_t *netif = NULL; + esp_err_t ret = ESP_FAIL; + char iface[10]; + + // Get interface details and own global ipv6 address + for (int i = 0; i < esp_netif_get_nr_of_ifs(); ++i) { + netif = esp_netif_next(netif); + ret = esp_netif_get_netif_impl_name(netif, iface); + if ((ESP_FAIL == ret) || (NULL == netif)) { + ESP_LOGE(TAG, "No interface available"); + return NULL; + } + + if (0 == strcmp(interface_i, iface)) { + return netif; + } + } + + return NULL; +} + + +/** + * @brief In case of Auto mode returns the interface name with a valid IPv6 address or + * In case the user has specified interface, validates and returns the interface name. + * + * @param[out] interface Name of the interface in as a string. + * + * @return 0 incase of success. + */ +static int get_src_iface(char *interface) +{ + esp_netif_t *netif = NULL; + esp_err_t ret = ESP_FAIL; + int ip6_addrs_count = 0; + esp_ip6_addr_t ip6[LWIP_IPV6_NUM_ADDRESSES]; + + // Get interface details and own global ipv6 address + for (int i = 0; i < esp_netif_get_nr_of_ifs(); ++i) { + netif = esp_netif_next(netif); + ret = esp_netif_get_netif_impl_name(netif, interface); + + if ((ESP_FAIL == ret) || (NULL == netif)) { + ESP_LOGE(TAG, "No interface available"); + return -1; + } + +#if defined(CONFIG_EXAMPLE_USER_SPECIFIED_IFACE) + if (!strcmp(CONFIG_EXAMPLE_USER_SPECIFIED_IFACE_NAME, interface)) { + ESP_LOGI(TAG, "Interface: %s", interface); + return 0; + } +#else + ip6_addrs_count = esp_netif_get_all_ip6(netif, ip6); + for (int j = 0; j < ip6_addrs_count; ++j) { + esp_ip6_addr_type_t ipv6_type = esp_netif_ip6_get_addr_type(&(ip6[j])); + + if ((ESP_IP6_ADDR_IS_GLOBAL == ipv6_type) || + (ESP_IP6_ADDR_IS_UNIQUE_LOCAL == ipv6_type) || + (ESP_IP6_ADDR_IS_LINK_LOCAL == ipv6_type)) { + // Break as we have the source address + ESP_LOGI(TAG, "Interface: %s", interface); + return 0; + } + } +#endif // #if defined(CONFIG_EXAMPLE_USER_SPECIFIED_IFACE) + } + + return -1; +} +#endif // #if defined(CONFIG_IDF_TARGET_LINUX) + + +void tcp_client(void) +{ + char rx_buffer[128]; + char host_ip[] = HOST_IP_ADDR; + int addr_family = 0; + int ip_protocol = 0; + char interface[10]; +#if defined(CONFIG_IDF_TARGET_LINUX) + struct ifreq ifr; +#else + esp_netif_t *netif = NULL; +#endif + + while (1) { +#if defined(CONFIG_EXAMPLE_IPV6) + struct sockaddr_in6 dest_addr = { 0 }; + inet_pton(AF_INET6, host_ip, &dest_addr.sin6_addr); + dest_addr.sin6_family = AF_INET6; + dest_addr.sin6_port = htons(PORT); + addr_family = AF_INET6; + ip_protocol = IPPROTO_TCP; +#elif defined(CONFIG_EXAMPLE_SOCKET_IP_INPUT_STDIN) + struct sockaddr_storage dest_addr = { 0 }; + ESP_ERROR_CHECK(get_addr_from_stdin(PORT, SOCK_STREAM, &ip_protocol, &addr_family, &dest_addr)); +#endif + int sock = socket(addr_family, SOCK_STREAM, ip_protocol); + if (sock < 0) { + ESP_LOGE(TAG, "Unable to create socket: errno %d", errno); + break; + } + ESP_LOGI(TAG, "Socket created, connecting to %s:%d", host_ip, PORT); + + if (0 != get_src_iface(interface)) { + ESP_LOGE(TAG, "Interface: Unavailable\n"); + break; + } + +#if defined(CONFIG_IDF_TARGET_LINUX) + memset (&ifr, 0, sizeof(ifr)); + snprintf (ifr.ifr_name, sizeof (ifr.ifr_name), "%s", interface); + if (ioctl (sock, SIOCGIFINDEX, &ifr) < 0) { + ESP_LOGE(TAG, "ioctl() failed to find interface "); + break; + } +#if defined(CONFIG_EXAMPLE_IPV6) + dest_addr.sin6_scope_id = ifr.ifr_ifindex; + ESP_LOGI(TAG, "Interface index: %d\n", dest_addr.sin6_scope_id); +#endif +#else + if (NULL == (netif = get_esp_netif_from_iface(interface))) { + ESP_LOGE(TAG, "Failed to find interface "); + break; + } +#if defined(CONFIG_EXAMPLE_IPV6) + dest_addr.sin6_scope_id = esp_netif_get_netif_impl_index(netif); + ESP_LOGI(TAG, "Interface index: %d\n", dest_addr.sin6_scope_id); +#endif +#endif + + int err = connect(sock, (struct sockaddr *)&dest_addr, sizeof(dest_addr)); + if (err != 0) { + ESP_LOGE(TAG, "Socket unable to connect: errno %d", errno); + break; + } + ESP_LOGI(TAG, "Successfully connected"); + + while (1) { + int err = send(sock, payload, strlen(payload), 0); + if (err < 0) { + ESP_LOGE(TAG, "Error occurred during sending: errno %d", errno); + break; + } + + int len = recv(sock, rx_buffer, sizeof(rx_buffer) - 1, 0); + // Error occurred during receiving + if (len < 0) { + ESP_LOGE(TAG, "recv failed: errno %d", errno); + break; + } + // Data received + else { + rx_buffer[len] = 0; // Null-terminate whatever we received and treat like a string + ESP_LOGI(TAG, "Received %d bytes from %s:", len, host_ip); + ESP_LOGI(TAG, "%s", rx_buffer); + } + } + + if (sock != -1) { + ESP_LOGE(TAG, "Shutting down socket and restarting..."); + shutdown(sock, 0); + close(sock); + } + } +} diff --git a/examples/protocols/sockets/tcp_client/sdkconfig.defaults b/examples/protocols/sockets/tcp_client/sdkconfig.defaults new file mode 100644 index 0000000000..d4a9198544 --- /dev/null +++ b/examples/protocols/sockets/tcp_client/sdkconfig.defaults @@ -0,0 +1,4 @@ +# This file was generated using idf.py save-defconfig. It can be edited manually. +# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration +# +# CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER is not set diff --git a/examples/protocols/sockets/tcp_server/main/tcp_server.c b/examples/protocols/sockets/tcp_server/main/tcp_server.c index 6f73e85901..157a19784e 100644 --- a/examples/protocols/sockets/tcp_server/main/tcp_server.c +++ b/examples/protocols/sockets/tcp_server/main/tcp_server.c @@ -53,6 +53,8 @@ static void do_retransmit(const int sock) int written = send(sock, rx_buffer + (len - to_write), to_write, 0); if (written < 0) { ESP_LOGE(TAG, "Error occurred during sending: errno %d", errno); + // Failed to retransmit, giving up + return; } to_write -= written; } diff --git a/examples/protocols/sockets/tcp_transport_client/CMakeLists.txt b/examples/protocols/sockets/tcp_transport_client/CMakeLists.txt new file mode 100644 index 0000000000..888ca62b16 --- /dev/null +++ b/examples/protocols/sockets/tcp_transport_client/CMakeLists.txt @@ -0,0 +1,10 @@ +# The following five lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.5) + +# (Not part of the boilerplate) +# This example uses an extra component for common functions such as Wi-Fi and Ethernet connection. +set(EXTRA_COMPONENT_DIRS $ENV{IDF_PATH}/examples/common_components/protocol_examples_common) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(tcp_transport_client) diff --git a/examples/protocols/sockets/tcp_transport_client/README.md b/examples/protocols/sockets/tcp_transport_client/README.md new file mode 100644 index 0000000000..6f3649b29d --- /dev/null +++ b/examples/protocols/sockets/tcp_transport_client/README.md @@ -0,0 +1,59 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | + + +# TCP TRANSPORT Client example + +(See the README.md file in the upper level 'examples' directory for more information about examples.) + +The application creates a TCP transport connection and tries to connect to the server with predefined IP address and port number. When a connection is successfully established, the application sends message and waits for the answer. After the server's reply, application prints received reply as ASCII text, waits for 2 seconds and sends another message. + +## How to use example + +In order to create TCP server that communicates with TCP TRANSPORT Client example, choose one of the following options. + +There are many host-side tools which can be used to interact with the UDP/TCP server/client. +One command line tool is [netcat](http://netcat.sourceforge.net) which can send and receive many kinds of packets. +Note: please replace `192.168.0.167 3333` with desired IPV4/IPV6 address (displayed in monitor console) and port number in the following command. + +In addition to those tools, simple Python scripts can be found under sockets/scripts directory. Every script is designed to interact with one of the examples. + +### TCP server using netcat +``` +nc -l 192.168.0.167 3333 +``` + +## Hardware Required + +This example can be run on any commonly available ESP32 development board. + +## Configure the project + +``` +idf.py menuconfig +``` + +Set following parameters under Example Configuration Options: + +* Set `IPV4 Address` that represents remote host the example will connect to. + +* Set `Port` number that represents remote port the example will connect to. + +Configure Wi-Fi or Ethernet under "Example Connection Configuration" menu. See "Establishing Wi-Fi or Ethernet Connection" section in [examples/protocols/README.md](../../README.md) for more details. + +## Build and Flash + +Build the project and flash it to the board, then run monitor tool to view serial output: + +``` +idf.py -p PORT flash monitor +``` + +(To exit the serial monitor, type ``Ctrl-]``.) + +See the Getting Started Guide for full steps to configure and use ESP-IDF to build projects. + + +## Troubleshooting + +Start server first, to receive data sent from the client (application). diff --git a/examples/protocols/sockets/tcp_transport_client/main/CMakeLists.txt b/examples/protocols/sockets/tcp_transport_client/main/CMakeLists.txt new file mode 100644 index 0000000000..1365c27b1e --- /dev/null +++ b/examples/protocols/sockets/tcp_transport_client/main/CMakeLists.txt @@ -0,0 +1,2 @@ +idf_component_register(SRCS "tcp_transport_client.c" + ) diff --git a/examples/protocols/sockets/tcp_transport_client/main/Kconfig.projbuild b/examples/protocols/sockets/tcp_transport_client/main/Kconfig.projbuild new file mode 100644 index 0000000000..3bee48e876 --- /dev/null +++ b/examples/protocols/sockets/tcp_transport_client/main/Kconfig.projbuild @@ -0,0 +1,16 @@ +menu "Example Configuration" + + config EXAMPLE_IPV4_ADDR + string "IPV4 Address" + default "192.168.0.165" + help + The example will connect to this IPV4 address. + + config EXAMPLE_PORT + int "Port" + range 0 65535 + default 3333 + help + The remote port to which the client example will connect to. + +endmenu diff --git a/examples/protocols/sockets/tcp_transport_client/main/tcp_transport_client.c b/examples/protocols/sockets/tcp_transport_client/main/tcp_transport_client.c new file mode 100644 index 0000000000..c6b10e0b13 --- /dev/null +++ b/examples/protocols/sockets/tcp_transport_client/main/tcp_transport_client.c @@ -0,0 +1,85 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include +#include +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "esp_system.h" +#include "esp_wifi.h" +#include "esp_event.h" +#include "esp_log.h" +#include "nvs_flash.h" +#include "esp_netif.h" +#include "protocol_examples_common.h" +#include "esp_transport.h" +#include "esp_transport_tcp.h" + + +#define HOST_IP_ADDR CONFIG_EXAMPLE_IPV4_ADDR + +#define PORT CONFIG_EXAMPLE_PORT + +static const char *TAG = "tcp_transport_client"; +static const char *payload = "Message from ESP32"; + +static void tcp_transport_client_task(void *pvParameters) +{ + char rx_buffer[128]; + char host_ip[] = HOST_IP_ADDR; + esp_transport_handle_t tcp = esp_transport_tcp_init(); + while (1) { + if (tcp == NULL) { + ESP_LOGE(TAG, "Error occurred during esp_transport_tcp_init()"); + break; + } + int err = esp_transport_connect(tcp, HOST_IP_ADDR, PORT, -1); + if (err != 0) { + ESP_LOGE(TAG, "Client unable to connect: errno %d", errno); + break; + } + ESP_LOGI(TAG, "Successfully connected"); + + while (1) { + int bytes_written = esp_transport_write(tcp, payload, strlen(payload), 0); + if (bytes_written < 0) { + ESP_LOGE(TAG, "Error occurred during sending: esp_transport_write() returned %d, errno %d", bytes_written, errno); + break; + } + int len = esp_transport_read(tcp, rx_buffer, sizeof(rx_buffer) - 1, 0); + // Error occurred during receiving + if (len < 0) { + ESP_LOGE(TAG, "recv failed: esp_transport_read() returned %d, errno %d", len, errno); + break; + } + // Data received + rx_buffer[len] = 0; // Null-terminate whatever we received and treat like a string + ESP_LOGI(TAG, "Received %d bytes from %s:", len, host_ip); + ESP_LOGI(TAG, "%s", rx_buffer); + + vTaskDelay(2000 / portTICK_PERIOD_MS); + } + + ESP_LOGE(TAG, "Shutting down TCP and restarting..."); + esp_transport_close(tcp); + } + esp_transport_destroy(tcp); + vTaskDelete(NULL); +} + +void app_main(void) +{ + ESP_ERROR_CHECK(nvs_flash_init()); + ESP_ERROR_CHECK(esp_netif_init()); + ESP_ERROR_CHECK(esp_event_loop_create_default()); + + /* This helper function configures Wi-Fi or Ethernet, as selected in menuconfig. + * Read "Establishing Wi-Fi or Ethernet Connection" section in + * examples/protocols/README.md for more information about this function. + */ + ESP_ERROR_CHECK(example_connect()); + + xTaskCreate(tcp_transport_client_task, "tcp_transport_client", 4096, NULL, 5, NULL); +} diff --git a/examples/protocols/sockets/udp_client/example_test.py b/examples/protocols/sockets/udp_client/example_test.py index a5425b8614..5b4593fc15 100644 --- a/examples/protocols/sockets/udp_client/example_test.py +++ b/examples/protocols/sockets/udp_client/example_test.py @@ -5,14 +5,10 @@ # CONDITIONS OF ANY KIND, either express or implied. # -*- coding: utf-8 -*- - -from __future__ import print_function, unicode_literals - import os import re import socket import sys -from builtins import input from threading import Event, Thread import netifaces diff --git a/examples/provisioning/wifi_prov_mgr/README.md b/examples/provisioning/wifi_prov_mgr/README.md index b0410bf7b1..3f7d33ef15 100644 --- a/examples/provisioning/wifi_prov_mgr/README.md +++ b/examples/provisioning/wifi_prov_mgr/README.md @@ -86,7 +86,7 @@ python esp_prov.py --transport ble --service_name PROV_261FCC --sec_ver 1 --pop For security version 2, the following command can be used: ``` -python esp_prov.py --transport ble --service_name PROV_261FCC --sec_ver 2 --sec2_username testuser --sec2_pwd testpassword --ssid myssid --passphrase mypassword +python esp_prov.py --transport ble --service_name PROV_261FCC --sec_ver 2 --sec2_username wifiprov --sec2_pwd abcd1234 --ssid myssid --passphrase mypassword ``` Above command will perform the provisioning steps, and the monitor log should display something like this : @@ -123,17 +123,19 @@ I (55355) app: Hello World! The config option `CONFIG_EXAMPLE_PROV_SEC2_DEV_MODE` should be enabled for the example and in `main/app_main.c`, the macro `EXAMPLE_PROV_SEC2_USERNAME` should be set to the same username used in the salt-verifier generation. ```log -$ python esp_prov.py --transport softap --sec_ver 2 --sec2_gen_cred --sec2_username testuser --sec2_pwd testpassword +$ python esp_prov.py --transport softap --sec_ver 2 --sec2_gen_cred --sec2_username wifiprov --sec2_pwd abcd1234 ==== Salt-verifier for security scheme 2 (SRP6a) ==== static const char sec2_salt[] = { - 0x14, 0xdf, 0x42, 0x50, 0x3d, 0xec, 0x54, 0xc3, 0xe5, 0x0e, 0x0c, 0x9d, 0xb4, 0x84, 0xd7, 0xe4 + 0x03, 0x6e, 0xe0, 0xc7, 0xbc, 0xb9, 0xed, 0xa8, 0x4c, 0x9e, 0xac, 0x97, 0xd9, 0x3d, 0xec, 0xf4 }; static const char sec2_verifier[] = { - 0xd7, 0xc2, 0xdb, 0x68, 0x3b, 0x98, 0xf0, 0xbf, 0x4f, 0x02, 0x21, 0xf6, 0x07, 0xe6, 0xfc, 0x0d, - ... - ... - 0x86, 0xf2, 0x78, 0xba, 0x1e, 0x12, 0xa9, 0x62, 0x9a, 0x47, 0x1b, 0x69, 0x42, 0xba, 0x37, 0xe2 + 0x7c, 0x7c, 0x85, 0x47, 0x65, 0x08, 0x94, 0x6d, 0xd6, 0x36, 0xaf, 0x37, 0xd7, 0xe8, 0x91, 0x43, + 0x78, 0xcf, 0xfd, 0x61, 0x6c, 0x59, 0xd2, 0xf8, 0x39, 0x08, 0x12, 0x72, 0x38, 0xde, 0x9e, 0x24, + . + . + . + 0xe6, 0xf6, 0x53, 0xc8, 0x31, 0xa8, 0x78, 0xde, 0x50, 0x40, 0xf7, 0x62, 0xde, 0x36, 0xb2, 0xba }; ``` diff --git a/examples/provisioning/wifi_prov_mgr/main/Kconfig.projbuild b/examples/provisioning/wifi_prov_mgr/main/Kconfig.projbuild index 269ad1866c..d103d6f774 100644 --- a/examples/provisioning/wifi_prov_mgr/main/Kconfig.projbuild +++ b/examples/provisioning/wifi_prov_mgr/main/Kconfig.projbuild @@ -17,7 +17,7 @@ menu "Example Configuration" choice EXAMPLE_PROV_SECURITY_VERSION bool "Protocomm security version" - default EXAMPLE_PROV_SECURITY_VERSION_1 + default EXAMPLE_PROV_SECURITY_VERSION_2 help Wi-Fi provisioning component offers 3 security versions. The example offers a choice between security version 1 and 2. @@ -96,4 +96,11 @@ menu "Example Configuration" default y help This enables BLE 4.2 features for Bluedroid. + + config EXAMPLE_REPROVISIONING + bool "Re-provisioning" + help + Enable re-provisioning - allow the device to provision for new credentials + after previous successful provisioning. + endmenu diff --git a/examples/provisioning/wifi_prov_mgr/main/app_main.c b/examples/provisioning/wifi_prov_mgr/main/app_main.c index e786a7f01e..8e1055efd8 100644 --- a/examples/provisioning/wifi_prov_mgr/main/app_main.c +++ b/examples/provisioning/wifi_prov_mgr/main/app_main.c @@ -34,41 +34,41 @@ static const char *TAG = "app"; #if CONFIG_EXAMPLE_PROV_SECURITY_VERSION_2 #if CONFIG_EXAMPLE_PROV_SEC2_DEV_MODE -#define EXAMPLE_PROV_SEC2_USERNAME "testuser" -#define EXAMPLE_PROV_SEC2_PWD "testpassword" +#define EXAMPLE_PROV_SEC2_USERNAME "wifiprov" +#define EXAMPLE_PROV_SEC2_PWD "abcd1234" -/* This salt,verifier has been generated for username = "testuser" and password = "testpassword" +/* This salt,verifier has been generated for username = "wifiprov" and password = "abcd1234" * IMPORTANT NOTE: For production cases, this must be unique to every device * and should come from device manufacturing partition.*/ static const char sec2_salt[] = { - 0x2f, 0x3d, 0x3c, 0xf8, 0x0d, 0xbd, 0x0c, 0xa9, 0x6f, 0x30, 0xb4, 0x4d, 0x89, 0xd5, 0x2f, 0x0e + 0x03, 0x6e, 0xe0, 0xc7, 0xbc, 0xb9, 0xed, 0xa8, 0x4c, 0x9e, 0xac, 0x97, 0xd9, 0x3d, 0xec, 0xf4 }; static const char sec2_verifier[] = { - 0xf2, 0x9f, 0xc1, 0xf5, 0x28, 0x4a, 0x11, 0x74, 0xb4, 0x24, 0x09, 0x23, 0xd8, 0x27, 0xb7, 0x5a, - 0x95, 0x3a, 0x99, 0xed, 0xf4, 0x6e, 0xe9, 0x8c, 0x4f, 0x07, 0xf2, 0xf5, 0x43, 0x3d, 0x7f, 0x9a, - 0x11, 0x60, 0x66, 0xaf, 0xcd, 0xa5, 0xf6, 0xfa, 0xcb, 0x06, 0xe9, 0xc5, 0x3f, 0x4d, 0x77, 0x16, - 0x4c, 0x68, 0x6d, 0x7f, 0x7c, 0xd7, 0xc7, 0x5a, 0x83, 0xc0, 0xfb, 0x94, 0x2d, 0xa9, 0x60, 0xf0, - 0x09, 0x11, 0xa0, 0xe1, 0x95, 0x33, 0xd1, 0x30, 0x7f, 0x82, 0x1b, 0x1b, 0x0f, 0x6d, 0xf1, 0xdc, - 0x93, 0x1c, 0x20, 0xa7, 0xc0, 0x8d, 0x48, 0x38, 0xff, 0x46, 0xb9, 0xaf, 0xf7, 0x93, 0x78, 0xae, - 0xff, 0xb8, 0x3b, 0xdf, 0x99, 0x7b, 0x64, 0x47, 0x02, 0xba, 0x01, 0x39, 0x0f, 0x5c, 0xd8, 0x4e, - 0x6f, 0xc8, 0xd0, 0x82, 0x7f, 0x2d, 0x33, 0x1a, 0x09, 0x65, 0x77, 0x85, 0xbc, 0x8a, 0x84, 0xe0, - 0x46, 0x7e, 0x3b, 0x0e, 0x6e, 0x3b, 0xdf, 0x70, 0x17, 0x70, 0x0a, 0xbc, 0x84, 0x67, 0xfa, 0xf9, - 0x84, 0x53, 0xda, 0xb4, 0xca, 0x38, 0x71, 0xe4, 0x06, 0xf6, 0x7d, 0xc8, 0x32, 0xbb, 0x91, 0x0c, - 0xe7, 0xd3, 0x59, 0xb6, 0x03, 0xed, 0x8e, 0x0d, 0x91, 0x9c, 0x09, 0xd7, 0x6f, 0xd5, 0xca, 0x55, - 0xc5, 0x58, 0x0f, 0x95, 0xb5, 0x83, 0x65, 0x6f, 0x2d, 0xbc, 0x94, 0x0f, 0xbb, 0x0f, 0xd3, 0x42, - 0xa5, 0xfe, 0x15, 0x7f, 0xf9, 0xa8, 0x16, 0xe6, 0x58, 0x9b, 0x4c, 0x0f, 0xd3, 0x83, 0x2c, 0xac, - 0xe4, 0xbf, 0xa3, 0x96, 0x1e, 0xb6, 0x6f, 0x59, 0xe6, 0xd1, 0x0e, 0xd4, 0x27, 0xb6, 0x05, 0x34, - 0xec, 0x8c, 0xf8, 0x72, 0xbb, 0x04, 0x7b, 0xa4, 0x49, 0x3d, 0x6d, 0xa9, 0x99, 0xfc, 0x0a, 0x2b, - 0xd8, 0x46, 0xa8, 0xd1, 0x46, 0x61, 0x5c, 0x96, 0xd2, 0x43, 0xcd, 0xea, 0x7f, 0x6a, 0x50, 0x59, - 0x0d, 0x0e, 0xa1, 0xb3, 0x94, 0x5a, 0x34, 0xe0, 0x1e, 0x95, 0x56, 0x68, 0xb4, 0xbc, 0xf1, 0x08, - 0x54, 0xcb, 0x42, 0x41, 0xc6, 0x78, 0xad, 0x71, 0x84, 0x1c, 0x29, 0xb8, 0x33, 0x79, 0x1c, 0x10, - 0xdd, 0x07, 0xc8, 0x91, 0x21, 0x85, 0x89, 0x76, 0xd7, 0x37, 0xdf, 0x5b, 0x19, 0x33, 0x4e, 0x17, - 0x67, 0x02, 0x0f, 0x1b, 0xb9, 0x2f, 0xa4, 0xdc, 0xdd, 0x75, 0x32, 0x96, 0x87, 0xdd, 0x66, 0xc3, - 0x33, 0xc1, 0xfc, 0x4c, 0x27, 0x63, 0xb9, 0x14, 0x72, 0x76, 0x65, 0xb8, 0x90, 0x2b, 0xeb, 0x7a, - 0xde, 0x71, 0x97, 0xf3, 0x6b, 0xc9, 0x8e, 0xdf, 0xfc, 0x6e, 0x13, 0xcc, 0x1b, 0x2b, 0x54, 0x1a, - 0x6e, 0x3d, 0xe6, 0x1c, 0xec, 0x5d, 0xa1, 0xf1, 0xd4, 0x86, 0x9d, 0xcd, 0xb9, 0xe8, 0x98, 0xf1, - 0xe5, 0x16, 0xa5, 0x48, 0xe5, 0xec, 0x12, 0xe8, 0x17, 0xe2, 0x55, 0xb5, 0xb3, 0x7c, 0xce, 0xfd + 0x7c, 0x7c, 0x85, 0x47, 0x65, 0x08, 0x94, 0x6d, 0xd6, 0x36, 0xaf, 0x37, 0xd7, 0xe8, 0x91, 0x43, + 0x78, 0xcf, 0xfd, 0x61, 0x6c, 0x59, 0xd2, 0xf8, 0x39, 0x08, 0x12, 0x72, 0x38, 0xde, 0x9e, 0x24, + 0xa4, 0x70, 0x26, 0x1c, 0xdf, 0xa9, 0x03, 0xc2, 0xb2, 0x70, 0xe7, 0xb1, 0x32, 0x24, 0xda, 0x11, + 0x1d, 0x97, 0x18, 0xdc, 0x60, 0x72, 0x08, 0xcc, 0x9a, 0xc9, 0x0c, 0x48, 0x27, 0xe2, 0xae, 0x89, + 0xaa, 0x16, 0x25, 0xb8, 0x04, 0xd2, 0x1a, 0x9b, 0x3a, 0x8f, 0x37, 0xf6, 0xe4, 0x3a, 0x71, 0x2e, + 0xe1, 0x27, 0x86, 0x6e, 0xad, 0xce, 0x28, 0xff, 0x54, 0x46, 0x60, 0x1f, 0xb9, 0x96, 0x87, 0xdc, + 0x57, 0x40, 0xa7, 0xd4, 0x6c, 0xc9, 0x77, 0x54, 0xdc, 0x16, 0x82, 0xf0, 0xed, 0x35, 0x6a, 0xc4, + 0x70, 0xad, 0x3d, 0x90, 0xb5, 0x81, 0x94, 0x70, 0xd7, 0xbc, 0x65, 0xb2, 0xd5, 0x18, 0xe0, 0x2e, + 0xc3, 0xa5, 0xf9, 0x68, 0xdd, 0x64, 0x7b, 0xb8, 0xb7, 0x3c, 0x9c, 0xfc, 0x00, 0xd8, 0x71, 0x7e, + 0xb7, 0x9a, 0x7c, 0xb1, 0xb7, 0xc2, 0xc3, 0x18, 0x34, 0x29, 0x32, 0x43, 0x3e, 0x00, 0x99, 0xe9, + 0x82, 0x94, 0xe3, 0xd8, 0x2a, 0xb0, 0x96, 0x29, 0xb7, 0xdf, 0x0e, 0x5f, 0x08, 0x33, 0x40, 0x76, + 0x52, 0x91, 0x32, 0x00, 0x9f, 0x97, 0x2c, 0x89, 0x6c, 0x39, 0x1e, 0xc8, 0x28, 0x05, 0x44, 0x17, + 0x3f, 0x68, 0x02, 0x8a, 0x9f, 0x44, 0x61, 0xd1, 0xf5, 0xa1, 0x7e, 0x5a, 0x70, 0xd2, 0xc7, 0x23, + 0x81, 0xcb, 0x38, 0x68, 0xe4, 0x2c, 0x20, 0xbc, 0x40, 0x57, 0x76, 0x17, 0xbd, 0x08, 0xb8, 0x96, + 0xbc, 0x26, 0xeb, 0x32, 0x46, 0x69, 0x35, 0x05, 0x8c, 0x15, 0x70, 0xd9, 0x1b, 0xe9, 0xbe, 0xcc, + 0xa9, 0x38, 0xa6, 0x67, 0xf0, 0xad, 0x50, 0x13, 0x19, 0x72, 0x64, 0xbf, 0x52, 0xc2, 0x34, 0xe2, + 0x1b, 0x11, 0x79, 0x74, 0x72, 0xbd, 0x34, 0x5b, 0xb1, 0xe2, 0xfd, 0x66, 0x73, 0xfe, 0x71, 0x64, + 0x74, 0xd0, 0x4e, 0xbc, 0x51, 0x24, 0x19, 0x40, 0x87, 0x0e, 0x92, 0x40, 0xe6, 0x21, 0xe7, 0x2d, + 0x4e, 0x37, 0x76, 0x2f, 0x2e, 0xe2, 0x68, 0xc7, 0x89, 0xe8, 0x32, 0x13, 0x42, 0x06, 0x84, 0x84, + 0x53, 0x4a, 0xb3, 0x0c, 0x1b, 0x4c, 0x8d, 0x1c, 0x51, 0x97, 0x19, 0xab, 0xae, 0x77, 0xff, 0xdb, + 0xec, 0xf0, 0x10, 0x95, 0x34, 0x33, 0x6b, 0xcb, 0x3e, 0x84, 0x0f, 0xb9, 0xd8, 0x5f, 0xb8, 0xa0, + 0xb8, 0x55, 0x53, 0x3e, 0x70, 0xf7, 0x18, 0xf5, 0xce, 0x7b, 0x4e, 0xbf, 0x27, 0xce, 0xce, 0xa8, + 0xb3, 0xbe, 0x40, 0xc5, 0xc5, 0x32, 0x29, 0x3e, 0x71, 0x64, 0x9e, 0xde, 0x8c, 0xf6, 0x75, 0xa1, + 0xe6, 0xf6, 0x53, 0xc8, 0x31, 0xa8, 0x78, 0xde, 0x50, 0x40, 0xf7, 0x62, 0xde, 0x36, 0xb2, 0xba }; #endif @@ -336,15 +336,12 @@ void app_main(void) * - NULL if not used */ const char *pop = "abcd1234"; + /* This is the structure for passing security parameters * for the protocomm security 1. - * This does not need not be static i.e. could be dynamically allocated */ - wifi_prov_security1_params_t sec1_params = { - .data = (const uint8_t *)pop, - .len = strlen(pop), - }; - wifi_prov_security1_params_t *sec_params = &sec1_params; + wifi_prov_security1_params_t *sec_params = pop; + const char *username = NULL; #elif CONFIG_EXAMPLE_PROV_SECURITY_VERSION_2 @@ -366,7 +363,8 @@ void app_main(void) #endif /* This is the structure for passing security parameters * for the protocomm security 2. - * This does not need not be static i.e. could be dynamically allocated + * If dynamically allocated, sec2_params pointer and its content + * must be valid till WIFI_PROV_END event is triggered. */ wifi_prov_security2_params_t sec2_params = {}; @@ -412,8 +410,13 @@ void app_main(void) * This call must be made before starting the provisioning. */ wifi_prov_mgr_endpoint_create("custom-data"); - /* Start provisioning service */ + /* Do not stop and de-init provisioning even after success, + * so that we can restart it later. */ +#ifdef CONFIG_EXAMPLE_REPROVISIONING + wifi_prov_mgr_disable_auto_stop(1000); +#endif + /* Start provisioning service */ ESP_ERROR_CHECK(wifi_prov_mgr_start_provisioning(security, (const void *) sec_params, service_name, service_key)); /* The handler for the optional endpoint created above. @@ -445,11 +448,27 @@ void app_main(void) } /* Wait for Wi-Fi connection */ - xEventGroupWaitBits(wifi_event_group, WIFI_CONNECTED_EVENT, false, true, portMAX_DELAY); + xEventGroupWaitBits(wifi_event_group, WIFI_CONNECTED_EVENT, true, true, portMAX_DELAY); /* Start main application now */ +#if CONFIG_EXAMPLE_REPROVISIONING while (1) { - ESP_LOGI(TAG, "Hello World!"); - vTaskDelay(1000 / portTICK_PERIOD_MS); + for (int i = 0; i < 10; i++) { + ESP_LOGI(TAG, "Hello World!"); + vTaskDelay(1000 / portTICK_PERIOD_MS); + } + + /* Resetting provisioning state machine to enable re-provisioning */ + wifi_prov_mgr_reset_sm_state_for_reprovision(); + + /* Wait for Wi-Fi connection */ + xEventGroupWaitBits(wifi_event_group, WIFI_CONNECTED_EVENT, true, true, portMAX_DELAY); } +#else + while (1) { + ESP_LOGI(TAG, "Hello World!"); + vTaskDelay(1000 / portTICK_PERIOD_MS); + } +#endif + } diff --git a/examples/provisioning/wifi_prov_mgr/pytest_wifi_prov_mgr.py b/examples/provisioning/wifi_prov_mgr/pytest_wifi_prov_mgr.py index cea11131c2..45704df07f 100644 --- a/examples/provisioning/wifi_prov_mgr/pytest_wifi_prov_mgr.py +++ b/examples/provisioning/wifi_prov_mgr/pytest_wifi_prov_mgr.py @@ -25,11 +25,7 @@ logging.basicConfig(level=logging.INFO) esp_prov.config_throw_except = True -@pytest.mark.esp32 -@pytest.mark.generic -@pytest.mark.xfail(reason='Runner unable to connect to target over Bluetooth', run=False) -def test_examples_wifi_prov_mgr(dut: Dut) -> None: - +def test_wifi_prov_mgr(dut: Dut, sec_ver: int) -> None: # Check if BT memory is released before provisioning starts dut.expect('wifi_prov_scheme_ble: BT memory released', timeout=60) @@ -40,14 +36,22 @@ def test_examples_wifi_prov_mgr(dut: Dut) -> None: logging.info('Starting Provisioning') verbose = False protover = 'v1.1' - secver = 1 - pop = 'abcd1234' provmode = 'ble' ap_ssid = 'myssid' ap_password = 'mypassword' logging.info('Getting security') - security = esp_prov.get_security(secver, pop, verbose) + if (sec_ver == 1): + pop = 'abcd1234' + sec2_username = None + sec2_password = None + security = esp_prov.get_security(sec_ver, sec2_username, sec2_password, pop, verbose) + elif (sec_ver == 2): + pop = None + sec2_username = 'wifiprov' + sec2_password = 'abcd1234' + security = esp_prov.get_security(sec_ver, sec2_username, sec2_password, pop, verbose) + if security is None: raise RuntimeError('Failed to get security') @@ -85,3 +89,20 @@ def test_examples_wifi_prov_mgr(dut: Dut) -> None: # Check if BTDM memory is released after provisioning finishes dut.expect('wifi_prov_scheme_ble: BTDM memory released', timeout=30) + + +@pytest.mark.esp32 +@pytest.mark.generic +@pytest.mark.parametrize('config', ['security1',], indirect=True) +@pytest.mark.xfail(reason='Runner unable to connect to target over Bluetooth', run=False) +def test_examples_wifi_prov_mgr_sec1(dut: Dut) -> None: + + test_wifi_prov_mgr(dut, 1) + + +@pytest.mark.esp32 +@pytest.mark.generic +@pytest.mark.xfail(reason='Runner unable to connect to target over Bluetooth', run=False) +def test_examples_wifi_prov_mgr_sec2(dut: Dut) -> None: + + test_wifi_prov_mgr(dut, 2) diff --git a/examples/provisioning/wifi_prov_mgr/sdkconfig.ci.security1 b/examples/provisioning/wifi_prov_mgr/sdkconfig.ci.security1 new file mode 100644 index 0000000000..760cddbe95 --- /dev/null +++ b/examples/provisioning/wifi_prov_mgr/sdkconfig.ci.security1 @@ -0,0 +1 @@ +CONFIG_EXAMPLE_PROV_SECURITY_VERSION_1=y diff --git a/examples/security/flash_encryption/README.md b/examples/security/flash_encryption/README.md index 22daca8157..7c1182cfae 100644 --- a/examples/security/flash_encryption/README.md +++ b/examples/security/flash_encryption/README.md @@ -32,7 +32,9 @@ The configuration for NVS encryption involves generating the XTS encryption keys When NVS encryption is enabled the `nvs_flash_init` API function can internally generate the XTS encryption keys on the ESP chip. The API function finds the first [NVS key partition](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/storage/nvs_flash.html#nvs-key-partition) i.e. a partition of type `data` and subtype `nvs_keys`. Then the API function automatically generates and stores the - nvs keys in that partition. New keys are generated and stored only when the respective key partiton is empty. (Consult the [`nvs_flash_init`](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/storage/nvs_flash.html#_CPPv414nvs_flash_initv) API documentation in the ESP-IDF programming guide for more details) + nvs keys in that partition. New keys are generated and stored only when the respective key partiton is empty. (Consult the [`nvs_flash_init`](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/storage/nvs_flash.html#_CPPv414nvs_flash_initv) API documentation in the ESP-IDF programming guide for more details). + + **Please note that `nvs_keys` partition must be completely erased before starting the application. Otherwise the application may generate `ESP_ERR_NVS_CORRUPT_KEY_PART` error code assuming that `nvs_keys` partition was not empty and contains malformatted data.** 2. Use pre-generated XTS encryption keys: This method will be required by the user when the `XTS encryption keys` in [NVS key partition](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/storage/nvs_flash.html#nvs-key-partition) are not generated by the application. diff --git a/examples/storage/parttool/partitions_example.csv b/examples/storage/parttool/partitions_example.csv index d39fab4bb2..6c09529c47 100644 --- a/examples/storage/parttool/partitions_example.csv +++ b/examples/storage/parttool/partitions_example.csv @@ -3,4 +3,5 @@ nvs, data, nvs, 0x9000, 0x6000, phy_init, data, phy, 0xf000, 0x1000, factory, app, factory, 0x10000, 1M, +custom, data, nvs, , 0x1000, storage, data, spiffs, , 0x10000, diff --git a/examples/storage/parttool/pytest_parttool_example.py b/examples/storage/parttool/pytest_parttool_example.py index a53ba47103..9f984cfc1a 100644 --- a/examples/storage/parttool/pytest_parttool_example.py +++ b/examples/storage/parttool/pytest_parttool_example.py @@ -26,3 +26,22 @@ def test_examples_parttool(dut: Dut) -> None: script_path = os.path.join(idf_path, 'examples', 'storage', 'parttool', 'parttool_example.py') binary_path = os.path.join(dut.app.binary_path, 'parttool.bin') subprocess.check_call([sys.executable, script_path, '--binary', binary_path, '--port', dut.serial.port]) + + # following tests check the external interface (parsing) of the parttool commands + with open('custom.bin', 'wb') as f: + f.write(b'0' * 1024 * 4) + + PARTTOOL = os.path.join(idf_path, 'components', 'partition_table', 'parttool.py') + BASE_CMD = [sys.executable, PARTTOOL, '--port', dut.serial.port] + + cmds = ['read_partition --partition-type=data --partition-subtype=nvs --output custom1.bin', + 'erase_partition --partition-name=custom', + 'write_partition --partition-name=custom --input custom.bin', + 'get_partition_info --partition-boot-default --info size'] + + for cmd in cmds: + subprocess.check_call(BASE_CMD + cmd.split()) + + clean_files = ['custom.bin', 'custom1.bin'] + for clean_file in clean_files: + os.unlink(clean_file) diff --git a/examples/storage/sd_card/sdmmc/main/sd_card_example_main.c b/examples/storage/sd_card/sdmmc/main/sd_card_example_main.c index 9f7ef71c76..153fd4c52b 100644 --- a/examples/storage/sd_card/sdmmc/main/sd_card_example_main.c +++ b/examples/storage/sd_card/sdmmc/main/sd_card_example_main.c @@ -46,6 +46,10 @@ void app_main(void) // production applications. ESP_LOGI(TAG, "Using SDMMC peripheral"); + + // By default, SD card frequency is initialized to SDMMC_FREQ_DEFAULT (20MHz) + // For setting a specific frequency, use host.max_freq_khz (range 400kHz - 40MHz for SDMMC) + // Example: for fixed frequency of 10MHz, use host.max_freq_khz = 10000; sdmmc_host_t host = SDMMC_HOST_DEFAULT(); // This initializes the slot without card detect (CD) and write protect (WP) signals. diff --git a/examples/storage/sd_card/sdspi/main/sd_card_example_main.c b/examples/storage/sd_card/sdspi/main/sd_card_example_main.c index f18094cd2d..341855dfb8 100644 --- a/examples/storage/sd_card/sdspi/main/sd_card_example_main.c +++ b/examples/storage/sd_card/sdspi/main/sd_card_example_main.c @@ -52,7 +52,11 @@ void app_main(void) // production applications. ESP_LOGI(TAG, "Using SPI peripheral"); + // By default, SD card frequency is initialized to SDMMC_FREQ_DEFAULT (20MHz) + // For setting a specific frequency, use host.max_freq_khz (range 400kHz - 20MHz for SDSPI) + // Example: for fixed frequency of 10MHz, use host.max_freq_khz = 10000; sdmmc_host_t host = SDSPI_HOST_DEFAULT(); + spi_bus_config_t bus_cfg = { .mosi_io_num = PIN_NUM_MOSI, .miso_io_num = PIN_NUM_MISO, diff --git a/examples/system/.build-test-rules.yml b/examples/system/.build-test-rules.yml index 7cfcddac8d..e635728186 100644 --- a/examples/system/.build-test-rules.yml +++ b/examples/system/.build-test-rules.yml @@ -43,10 +43,6 @@ examples/system/deep_sleep: reason: target esp32c2 is not supported yet examples/system/efuse: - disable: - - if: IDF_TARGET == "esp32c2" - temporary: true - reason: target esp32c2 is not supported yet disable_test: - if: IDF_TARGET == "esp32s3" temporary: true @@ -140,29 +136,15 @@ examples/system/select: temporary: true reason: lack of runners -examples/system/startup_time: - disable_test: - - if: IDF_TARGET == "esp32s3" or IDF_TARGET == "esp32c2" - temporary: true - reason: lack of runners - examples/system/sysview_tracing: - enable: - - if: IDF_TARGET in ["esp32", "esp32c3", "esp32s2"] - temporary: true - reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET == "esp32s2" or IDF_TARGET == "esp32c3" + - if: IDF_TARGET != "esp32" temporary: true reason: lack of runners examples/system/sysview_tracing_heap_log: - enable: - - if: IDF_TARGET in ["esp32", "esp32c3", "esp32s2"] - temporary: true - reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET == "esp32s2" or IDF_TARGET == "esp32c3" + - if: IDF_TARGET != "esp32" temporary: true reason: lack of runners @@ -178,7 +160,7 @@ examples/system/ulp_fsm/ulp: examples/system/ulp_fsm/ulp_adc: enable: - - if: IDF_TARGET == "esp32" + - if: IDF_TARGET in ["esp32", "esp32s3"] temporary: true reason: the other targets are not tested yet @@ -206,6 +188,17 @@ examples/system/ulp_riscv/gpio_interrupt: temporary: true reason: the other targets are not tested yet +examples/system/ulp_riscv/i2c: + enable: + - if: SOC_RISCV_COPROC_SUPPORTED == 1 + examples/system/ulp_riscv/uart_print: enable: - if: SOC_RISCV_COPROC_SUPPORTED == 1 +examples/system/xip_from_psram: + enable: + - if: SOC_SPIRAM_SUPPORTED == 1 + reason: this feature is supported on chips that have PSRAM + disable: + - if: IDF_TARGET == "esp32" + reason: target esp32 doesn't support this feature. diff --git a/examples/system/base_mac_address/pytest_base_mac_address.py b/examples/system/base_mac_address/pytest_base_mac_address.py index ee3dcb7381..a5ec6f03c4 100644 --- a/examples/system/base_mac_address/pytest_base_mac_address.py +++ b/examples/system/base_mac_address/pytest_base_mac_address.py @@ -12,16 +12,30 @@ def test_base_mac_address(dut: Dut) -> None: hex_r = r', '.join((r'0x([0-9a-f]{1,2})',) * 6) mac_m = dut.expect(r'BASE_MAC: Using "' + hex_r + r'" as base MAC address', timeout=5).groups() - def get_expected_mac_string(increment: int) -> str: + def get_expected_mac_string(increment: int, target: str) -> str: ''' Return the string representation of the MAC address mac_m with the last octet incremented. mac_m is an array of strings in hexa-decimal format without the '0x' prefix. ''' + # as a result of some esp32s2 chips burned with one MAC address by mistake, + # there are some MAC address are reserved for this bug fix. + # related mistake MAC address is 0x7cdfa1003000~0x7cdfa1005fff, + # reserved MAC address is 0x7cdfa1020000~0x7cdfa1022fff (MAC address + 0x1d000). + if target == 'esp32s2' and increment == 1: + hex_string = ''.join([m.decode('utf8').rjust(2, '0') for m in mac_m]) + mac_bytes = int(hex_string, 16) + + if mac_bytes >= int('7cdfa1003000', 16) and mac_bytes <= int('7cdfa1005fff', 16): + mac_bytes += int('1d000', 16) + hex_string = f'{mac_bytes:x}' + # Format the new string to match the expected output from the app (includes stripping leading zeroes) + return ', '.join('0x{}'.format(hex_string[i:i + 2].lstrip('0')) for i in range(0, len(hex_string), 2)) + return ', '.join(['0x{}'.format(m.decode('utf8')) for m in mac_m[:-1]] + [hex(int(mac_m[-1], 16) + increment)]) - dut.expect_exact('WIFI_STA MAC: ' + get_expected_mac_string(0), timeout=2) - dut.expect_exact('SoftAP MAC: ' + get_expected_mac_string(1)) + dut.expect_exact('WIFI_STA MAC: ' + get_expected_mac_string(0, dut.target), timeout=2) + dut.expect_exact('SoftAP MAC: ' + get_expected_mac_string(1, dut.target)) if dut.target != 'esp32s2': - dut.expect_exact('BT MAC: ' + get_expected_mac_string(2)) - dut.expect_exact('Ethernet MAC: ' + get_expected_mac_string(3)) + dut.expect_exact('BT MAC: ' + get_expected_mac_string(2, dut.target)) + dut.expect_exact('Ethernet MAC: ' + get_expected_mac_string(3, dut.target)) diff --git a/examples/system/efuse/README.md b/examples/system/efuse/README.md index 14e9e36e3d..23a722c6d7 100644 --- a/examples/system/efuse/README.md +++ b/examples/system/efuse/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | # eFuse Example diff --git a/examples/system/efuse/example_test.py b/examples/system/efuse/example_test.py index 868b2266f2..af5afa9e62 100644 --- a/examples/system/efuse/example_test.py +++ b/examples/system/efuse/example_test.py @@ -27,7 +27,7 @@ def erase_field_on_emul_efuse(dut, pos_of_bits): # type: (ttfw_idf.TinyFW.Env, dut.write_flash(flash_files) -@ttfw_idf.idf_example_test(env_tag='Example_GENERIC', target=['esp32', 'esp32c3']) +@ttfw_idf.idf_example_test(env_tag='Example_GENERIC', target=['esp32', 'esp32c3', 'esp32c2']) def test_examples_efuse(env, _): # type: (ttfw_idf.TinyFW.Env, None) -> None dut = env.get_dut('efuse', 'examples/system/efuse') dut.start_app() @@ -54,7 +54,7 @@ def test_examples_efuse(env, _): # type: (ttfw_idf.TinyFW.Env, None) -> None timeout=30) -@ttfw_idf.idf_example_test(env_tag='Example_GENERIC', target=['esp32', 'esp32s2', 'esp32c3']) +@ttfw_idf.idf_example_test(env_tag='Example_GENERIC', target=['esp32', 'esp32s2', 'esp32c3', 'esp32c2']) def test_examples_efuse_with_virt_flash_enc(env, _): # type: (ttfw_idf.TinyFW.Env, None) -> None dut = env.get_dut('efuse', 'examples/system/efuse', app_config_name='virt_flash_enc') # check and log bin size @@ -79,7 +79,10 @@ def test_examples_efuse_with_virt_flash_enc(env, _): # type: (ttfw_idf.TinyFW.E dut.expect('Disable JTAG...') dut.expect('Disable ROM BASIC interpreter fallback...') else: - dut.expect('Writing EFUSE_BLK_KEY0 with purpose 4') + if dut.TARGET == 'esp32c2': + dut.expect('Writing EFUSE_BLK_KEY0 with purpose 1') + else: + dut.expect('Writing EFUSE_BLK_KEY0 with purpose 4') dut.expect('Not disabling UART bootloader encryption') dut.expect('Disable UART bootloader cache...') dut.expect('Disable JTAG...') @@ -138,7 +141,7 @@ def test_examples_efuse_with_virt_flash_enc_aes_256(env, _): # type: (ttfw_idf. dut.expect('example: Done') -@ttfw_idf.idf_example_test(env_tag='Example_GENERIC', target=['esp32', 'esp32s2', 'esp32c3']) +@ttfw_idf.idf_example_test(env_tag='Example_GENERIC', target=['esp32', 'esp32s2', 'esp32c3', 'esp32c2']) def test_examples_efuse_with_virt_flash_enc_pre_loaded(env, _): # type: (ttfw_idf.TinyFW.Env, None) -> None dut = env.get_dut('efuse', 'examples/system/efuse', app_config_name='virt_flash_enc') @@ -161,6 +164,9 @@ def test_examples_efuse_with_virt_flash_enc_pre_loaded(env, _): # type: (ttfw_i FLASH_CRYPT_CNT = 20 # Resets eFuse, which enables Flash encryption feature erase_field_on_emul_efuse(dut, [FLASH_CRYPT_CNT]) + elif dut.TARGET == 'esp32c2': + FLASH_CRYPT_CNT = 39 + erase_field_on_emul_efuse(dut, [FLASH_CRYPT_CNT]) else: # offset of this eFuse is taken from components/efuse/{target}/esp_efuse_table.csv print(' - Flash emul_efuse with pre-loaded efuses (SPI_BOOT_CRYPT_CNT 1 -> 0)') @@ -201,7 +207,7 @@ def test_examples_efuse_with_virt_flash_enc_pre_loaded(env, _): # type: (ttfw_i dut.expect('example: Done') -@ttfw_idf.idf_example_test(env_tag='Example_GENERIC', target=['esp32', 'esp32s2', 'esp32c3']) +@ttfw_idf.idf_example_test(env_tag='Example_GENERIC', target=['esp32', 'esp32s2', 'esp32c3', 'esp32c2']) def test_examples_efuse_with_virt_flash_enc_release(env, _): # type: (ttfw_idf.TinyFW.Env, None) -> None dut = env.get_dut('efuse', 'examples/system/efuse', app_config_name='virt_flash_enc_release') # check and log bin size @@ -226,7 +232,10 @@ def test_examples_efuse_with_virt_flash_enc_release(env, _): # type: (ttfw_idf. dut.expect('Disable JTAG...') dut.expect('Disable ROM BASIC interpreter fallback...') else: - dut.expect('Writing EFUSE_BLK_KEY0 with purpose 4') + if dut.TARGET == 'esp32c2': + dut.expect('Writing EFUSE_BLK_KEY0 with purpose 1') + else: + dut.expect('Writing EFUSE_BLK_KEY0 with purpose 4') dut.expect('Disable UART bootloader encryption') dut.expect('Disable UART bootloader cache...') dut.expect('Disable JTAG...') @@ -347,7 +356,7 @@ def test_examples_efuse_with_virt_secure_boot_v1_pre_loaded(env, _): # type: (t @ttfw_idf.idf_example_test(env_tag='Example_EthKitV12', target=['esp32']) def test_examples_efuse_with_virt_secure_boot_v2(env, _): # type: (ttfw_idf.TinyFW.Env, None) -> None # only for ESP32 ECO3 - dut = env.get_dut('efuse', 'examples/system/efuse', app_config_name='virt_secure_boot_v2') + dut = env.get_dut('efuse', 'examples/system/efuse', app_config_name='virt_secure_boot_v2.' + env.default_dut_cls.TARGET) # check and log bin size binary_file = os.path.join(dut.app.binary_path, 'bootloader', 'bootloader.bin') bin_size = os.path.getsize(binary_file) @@ -408,7 +417,7 @@ def test_examples_efuse_with_virt_secure_boot_v2(env, _): # type: (ttfw_idf.Tin @ttfw_idf.idf_example_test(env_tag='Example_EthKitV12', target=['esp32']) def test_examples_efuse_with_virt_secure_boot_v2_pre_loaded(env, _): # type: (ttfw_idf.TinyFW.Env, None) -> None # only for ESP32 ECO3 - dut = env.get_dut('efuse', 'examples/system/efuse', app_config_name='virt_secure_boot_v2') + dut = env.get_dut('efuse', 'examples/system/efuse', app_config_name='virt_secure_boot_v2.' + env.default_dut_cls.TARGET) print(' - Erase flash') dut.erase_flash() @@ -469,9 +478,9 @@ def test_examples_efuse_with_virt_secure_boot_v2_pre_loaded(env, _): # type: (t dut.expect('example: Done') -@ttfw_idf.idf_example_test(env_tag='Example_GENERIC', target=['esp32s2', 'esp32c3']) +@ttfw_idf.idf_example_test(env_tag='Example_GENERIC', target=['esp32s2', 'esp32c3', 'esp32c2']) def test_examples_efuse_with_virt_secure_boot_v2_esp32xx(env, _): # type: (ttfw_idf.TinyFW.Env, None) -> None - dut = env.get_dut('efuse', 'examples/system/efuse', app_config_name='virt_secure_boot_v2') + dut = env.get_dut('efuse', 'examples/system/efuse', app_config_name='virt_secure_boot_v2.' + env.default_dut_cls.TARGET) # check and log bin size binary_file = os.path.join(dut.app.binary_path, 'bootloader', 'bootloader.bin') bin_size = os.path.getsize(binary_file) @@ -489,24 +498,29 @@ def test_examples_efuse_with_virt_secure_boot_v2_esp32xx(env, _): # type: (ttfw dut.expect('Verifying image signature...') dut.expect('secure_boot_v2: Secure boot V2 is not enabled yet and eFuse digest keys are not set') - dut.expect('secure_boot_v2: Verifying with RSA-PSS...') + signed_scheme = 'ECDSA' if dut.TARGET == 'esp32c2' else 'RSA-PSS' + dut.expect('secure_boot_v2: Verifying with %s...' % signed_scheme) dut.expect('secure_boot_v2: Signature verified successfully!') dut.expect('secure_boot_v2: enabling secure boot v2...') dut.expect('Verifying image signature...') dut.expect('secure_boot_v2: Secure boot V2 is not enabled yet and eFuse digest keys are not set') - dut.expect('secure_boot_v2: Verifying with RSA-PSS...') + dut.expect('secure_boot_v2: Verifying with %s...' % signed_scheme) dut.expect('secure_boot_v2: Signature verified successfully!') dut.expect('secure_boot_v2: Secure boot digests absent, generating..') dut.expect('secure_boot_v2: Digests successfully calculated, 1 valid signatures') dut.expect('secure_boot_v2: 1 signature block(s) found appended to the bootloader') - dut.expect('Writing EFUSE_BLK_KEY0 with purpose 9') + if dut.TARGET == 'esp32c2': + dut.expect('Writing EFUSE_BLK_KEY0 with purpose 3') + else: + dut.expect('Writing EFUSE_BLK_KEY0 with purpose 9') dut.expect('secure_boot_v2: Digests successfully calculated, 1 valid signatures') dut.expect('secure_boot_v2: 1 signature block(s) found appended to the app') dut.expect('secure_boot_v2: Application key(0) matches with bootloader key(0)') - dut.expect('secure_boot_v2: Revoking empty key digest slot (1)...') - dut.expect('secure_boot_v2: Revoking empty key digest slot (2)...') + if dut.TARGET != 'esp32c2': + dut.expect('secure_boot_v2: Revoking empty key digest slot (1)...') + dut.expect('secure_boot_v2: Revoking empty key digest slot (2)...') dut.expect('secure_boot_v2: blowing secure boot efuse...') dut.expect('UART ROM Download mode kept enabled - SECURITY COMPROMISED') dut.expect('Disable hardware & software JTAG...') @@ -520,7 +534,7 @@ def test_examples_efuse_with_virt_secure_boot_v2_esp32xx(env, _): # type: (ttfw dut.reset() dut.expect('Loading virtual efuse blocks from flash') dut.expect('Verifying image signature...') - dut.expect('secure_boot_v2: Verifying with RSA-PSS...') + dut.expect('secure_boot_v2: Verifying with %s...' % signed_scheme) dut.expect('secure_boot_v2: Signature verified successfully!') dut.expect('secure_boot_v2: enabling secure boot v2...') dut.expect('secure_boot_v2: secure boot v2 is already enabled, continuing..') @@ -528,9 +542,9 @@ def test_examples_efuse_with_virt_secure_boot_v2_esp32xx(env, _): # type: (ttfw dut.expect('example: Done') -@ttfw_idf.idf_example_test(env_tag='Example_GENERIC', target=['esp32s2', 'esp32c3']) +@ttfw_idf.idf_example_test(env_tag='Example_GENERIC', target=['esp32s2', 'esp32c3', 'esp32c2']) def test_examples_efuse_with_virt_secure_boot_v2_esp32xx_pre_loaded(env, _): # type: (ttfw_idf.TinyFW.Env, None) -> None - dut = env.get_dut('efuse', 'examples/system/efuse', app_config_name='virt_secure_boot_v2') + dut = env.get_dut('efuse', 'examples/system/efuse', app_config_name='virt_secure_boot_v2.' + env.default_dut_cls.TARGET) print(' - Erase flash') dut.erase_flash() @@ -546,28 +560,34 @@ def test_examples_efuse_with_virt_secure_boot_v2_esp32xx_pre_loaded(env, _): # print(' - Flash emul_efuse with pre-loaded efuses (SECURE_BOOT_EN 1 -> 0, SECURE_BOOT_KEY_REVOKE[0..2] -> 0)') # offsets of eFuses are taken from components/efuse/{target}/esp_efuse_table.csv - SECURE_BOOT_EN = 116 - SECURE_BOOT_KEY_REVOKE0 = 85 - SECURE_BOOT_KEY_REVOKE1 = 86 - SECURE_BOOT_KEY_REVOKE2 = 87 - # Resets eFuse, which enables Secure boot feature - # Resets eFuses, which control digest slots - erase_field_on_emul_efuse(dut, [SECURE_BOOT_EN, SECURE_BOOT_KEY_REVOKE0, SECURE_BOOT_KEY_REVOKE1, SECURE_BOOT_KEY_REVOKE2]) + if dut.TARGET == 'esp32c2': + SECURE_BOOT_EN = 53 + erase_field_on_emul_efuse(dut, [SECURE_BOOT_EN]) + else: + SECURE_BOOT_EN = 116 + SECURE_BOOT_KEY_REVOKE0 = 85 + SECURE_BOOT_KEY_REVOKE1 = 86 + SECURE_BOOT_KEY_REVOKE2 = 87 + # Resets eFuse, which enables Secure boot feature + # Resets eFuses, which control digest slots + erase_field_on_emul_efuse(dut, [SECURE_BOOT_EN, SECURE_BOOT_KEY_REVOKE0, SECURE_BOOT_KEY_REVOKE1, SECURE_BOOT_KEY_REVOKE2]) print(' - Start app (flash partition_table and app)') dut.start_app() dut.expect('Loading virtual efuse blocks from flash') dut.expect('Verifying image signature...') - dut.expect('secure_boot_v2: Verifying with RSA-PSS...') + signed_scheme = 'ECDSA' if dut.TARGET == 'esp32c2' else 'RSA-PSS' + dut.expect('secure_boot_v2: Verifying with %s...' % signed_scheme) dut.expect('secure_boot_v2: Signature verified successfully!') dut.expect('secure_boot_v2: Secure boot digests already present') dut.expect('secure_boot_v2: Using pre-loaded public key digest in eFuse') dut.expect('secure_boot_v2: Digests successfully calculated, 1 valid signatures') dut.expect('secure_boot_v2: 1 signature block(s) found appended to the app') dut.expect('secure_boot_v2: Application key(0) matches with bootloader key(0)') - dut.expect('secure_boot_v2: Revoking empty key digest slot (1)...') - dut.expect('secure_boot_v2: Revoking empty key digest slot (2)...') + if dut.TARGET != 'esp32c2': + dut.expect('secure_boot_v2: Revoking empty key digest slot (1)...') + dut.expect('secure_boot_v2: Revoking empty key digest slot (2)...') dut.expect('secure_boot_v2: blowing secure boot efuse...') dut.expect('UART ROM Download mode kept enabled - SECURITY COMPROMISED') @@ -582,7 +602,7 @@ def test_examples_efuse_with_virt_secure_boot_v2_esp32xx_pre_loaded(env, _): # dut.reset() dut.expect('Loading virtual efuse blocks from flash') dut.expect('Verifying image signature...') - dut.expect('secure_boot_v2: Verifying with RSA-PSS...') + dut.expect('secure_boot_v2: Verifying with %s...' % signed_scheme) dut.expect('secure_boot_v2: Signature verified successfully!') dut.expect('secure_boot_v2: enabling secure boot v2...') dut.expect('secure_boot_v2: secure boot v2 is already enabled, continuing..') @@ -654,7 +674,7 @@ def test_examples_efuse_with_virt_sb_v1_and_fe(env, _): # type: (ttfw_idf.TinyF @ttfw_idf.idf_example_test(env_tag='Example_EthKitV12', target=['esp32']) def test_examples_efuse_with_virt_sb_v2_and_fe(env, _): # type: (ttfw_idf.TinyFW.Env, None) -> None # only for ESP32 ECO3 - dut = env.get_dut('efuse', 'examples/system/efuse', app_config_name='virt_sb_v2_and_fe') + dut = env.get_dut('efuse', 'examples/system/efuse', app_config_name='virt_sb_v2_and_fe.' + env.default_dut_cls.TARGET) # check and log bin size binary_file = os.path.join(dut.app.binary_path, 'bootloader', 'bootloader.bin') bin_size = os.path.getsize(binary_file) @@ -730,9 +750,9 @@ def test_examples_efuse_with_virt_sb_v2_and_fe(env, _): # type: (ttfw_idf.TinyF dut.expect('example: Done') -@ttfw_idf.idf_example_test(env_tag='Example_GENERIC', target=['esp32s2', 'esp32c3']) +@ttfw_idf.idf_example_test(env_tag='Example_GENERIC', target=['esp32s2', 'esp32c3', 'esp32c2']) def test_examples_efuse_with_virt_sb_v2_and_fe_esp32xx(env, _): # type: (ttfw_idf.TinyFW.Env, None) -> None - dut = env.get_dut('efuse', 'examples/system/efuse', app_config_name='virt_sb_v2_and_fe') + dut = env.get_dut('efuse', 'examples/system/efuse', app_config_name='virt_sb_v2_and_fe.' + env.default_dut_cls.TARGET) # check and log bin size binary_file = os.path.join(dut.app.binary_path, 'bootloader', 'bootloader.bin') bin_size = os.path.getsize(binary_file) @@ -750,51 +770,65 @@ def test_examples_efuse_with_virt_sb_v2_and_fe_esp32xx(env, _): # type: (ttfw_i dut.expect('Verifying image signature...') dut.expect('secure_boot_v2: Secure boot V2 is not enabled yet and eFuse digest keys are not set') - dut.expect('secure_boot_v2: Verifying with RSA-PSS...') + signed_scheme = 'ECDSA' if dut.TARGET == 'esp32c2' else 'RSA-PSS' + dut.expect('secure_boot_v2: Verifying with %s...' % signed_scheme) dut.expect('secure_boot_v2: Signature verified successfully!') dut.expect('secure_boot_v2: enabling secure boot v2...') dut.expect('Verifying image signature...') dut.expect('secure_boot_v2: Secure boot V2 is not enabled yet and eFuse digest keys are not set') - dut.expect('secure_boot_v2: Verifying with RSA-PSS...') + dut.expect('secure_boot_v2: Verifying with %s...' % signed_scheme) dut.expect('secure_boot_v2: Signature verified successfully!') dut.expect('secure_boot_v2: Secure boot digests absent, generating..') dut.expect('secure_boot_v2: Digests successfully calculated, 1 valid signatures') dut.expect('secure_boot_v2: 1 signature block(s) found appended to the bootloader') - dut.expect('Writing EFUSE_BLK_KEY0 with purpose 9') + if dut.TARGET == 'esp32c2': + dut.expect('Writing EFUSE_BLK_KEY0 with purpose 3') + else: + dut.expect('Writing EFUSE_BLK_KEY0 with purpose 9') dut.expect('secure_boot_v2: Digests successfully calculated, 1 valid signatures') dut.expect('secure_boot_v2: 1 signature block(s) found appended to the app') dut.expect('secure_boot_v2: Application key(0) matches with bootloader key(0)') - dut.expect('secure_boot_v2: Revoking empty key digest slot (1)...') - dut.expect('secure_boot_v2: Revoking empty key digest slot (2)...') + if dut.TARGET != 'esp32c2': + dut.expect('secure_boot_v2: Revoking empty key digest slot (1)...') + dut.expect('secure_boot_v2: Revoking empty key digest slot (2)...') dut.expect('secure_boot_v2: blowing secure boot efuse...') dut.expect('UART ROM Download mode kept enabled - SECURITY COMPROMISED') dut.expect('Disable hardware & software JTAG...') - dut.expect('secure_boot_v2: Secure boot permanently enabled') + + if dut.TARGET != 'esp32c2': + dut.expect('secure_boot_v2: Secure boot permanently enabled') dut.expect('Checking flash encryption...') dut.expect('flash_encrypt: Generating new flash encryption key...') - dut.expect('Writing EFUSE_BLK_KEY1 with purpose 4') + if dut.TARGET == 'esp32c2': + dut.expect('Writing EFUSE_BLK_KEY0 with purpose 2') + else: + dut.expect('Writing EFUSE_BLK_KEY1 with purpose 4') + dut.expect('Not disabling UART bootloader encryption') dut.expect('Disable UART bootloader cache...') dut.expect('Disable JTAG...') + if dut.TARGET == 'esp32c2': + dut.expect('boot: Secure boot permanently enabled') + dut.expect('Verifying image signature...') - dut.expect('secure_boot_v2: Verifying with RSA-PSS...') + dut.expect('secure_boot_v2: Verifying with %s...' % signed_scheme) dut.expect('secure_boot_v2: Signature verified successfully!') dut.expect('flash_encrypt: bootloader encrypted successfully') dut.expect('flash_encrypt: partition table encrypted and loaded successfully') dut.expect('Verifying image signature...') - dut.expect('secure_boot_v2: Verifying with RSA-PSS...') + dut.expect('secure_boot_v2: Verifying with %s...' % signed_scheme) dut.expect('secure_boot_v2: Signature verified successfully!') dut.expect('flash_encrypt: Flash encryption completed', timeout=90) dut.expect('Resetting with flash encryption enabled...') dut.expect('Loading virtual efuse blocks from flash') dut.expect('Verifying image signature...') - dut.expect('secure_boot_v2: Verifying with RSA-PSS...') + dut.expect('secure_boot_v2: Verifying with %s...' % signed_scheme) dut.expect('secure_boot_v2: Signature verified successfully!') dut.expect('secure_boot_v2: enabling secure boot v2...') dut.expect('secure_boot_v2: secure boot v2 is already enabled, continuing..') diff --git a/examples/system/efuse/main/efuse_main.c b/examples/system/efuse/main/efuse_main.c index 1a5c290f07..8c24a407d9 100644 --- a/examples/system/efuse/main/efuse_main.c +++ b/examples/system/efuse/main/efuse_main.c @@ -15,6 +15,10 @@ #include "esp_efuse.h" #include "esp_efuse_table.h" #include "esp_efuse_custom_table.h" +#if CONFIG_IDF_TARGET_ESP32C2 +#include "esp_secure_boot.h" +#include "esp_flash_encrypt.h" +#endif #include "sdkconfig.h" static const char* TAG = "example"; @@ -138,6 +142,16 @@ void app_main(void) read_efuse_fields(&device_desc); ESP_LOGW(TAG, "This example does not burn any efuse in reality only virtually"); + +#if CONFIG_IDF_TARGET_ESP32C2 + if (esp_secure_boot_enabled() || esp_flash_encryption_enabled()) { + ESP_LOGW(TAG, "BLOCK3 is used for secure boot or/and flash encryption"); + ESP_LOGW(TAG, "eFuses from the custom eFuse table can not be used as they are placed in BLOCK3"); + ESP_LOGI(TAG, "Done"); + return; + } +#endif + #ifdef CONFIG_EFUSE_VIRTUAL ESP_LOGW(TAG, "Write operations in efuse fields are performed virtually"); if (device_desc.device_role == 0) { diff --git a/examples/system/efuse/sdkconfig.ci.virt_sb_v2_and_fe.esp32 b/examples/system/efuse/sdkconfig.ci.virt_sb_v2_and_fe.esp32 new file mode 100644 index 0000000000..4abf5fcc95 --- /dev/null +++ b/examples/system/efuse/sdkconfig.ci.virt_sb_v2_and_fe.esp32 @@ -0,0 +1,21 @@ +# FLASH_ENCRYPTION & SECURE_BOOT_V2 with EFUSE_VIRTUAL_KEEP_IN_FLASH + +CONFIG_IDF_TARGET="esp32" + +# ESP32 supports SECURE_BOOT_V2 only in ECO3 +CONFIG_ESP32_REV_MIN_3=y +CONFIG_ESP32_REV_MIN=3 + +CONFIG_PARTITION_TABLE_OFFSET=0xD000 +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="test/partitions_efuse_emul.csv" + +CONFIG_SECURE_BOOT=y +CONFIG_SECURE_BOOT_V2_ENABLED=y +CONFIG_SECURE_BOOT_SIGNING_KEY="test/secure_boot_signing_key.pem" + +CONFIG_SECURE_FLASH_ENC_ENABLED=y + +# IMPORTANT: ONLY VIRTUAL eFuse MODE! +CONFIG_EFUSE_VIRTUAL=y +CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH=y diff --git a/examples/system/efuse/sdkconfig.ci.virt_sb_v2_and_fe.esp32c2 b/examples/system/efuse/sdkconfig.ci.virt_sb_v2_and_fe.esp32c2 new file mode 100644 index 0000000000..2be2ad7ea4 --- /dev/null +++ b/examples/system/efuse/sdkconfig.ci.virt_sb_v2_and_fe.esp32c2 @@ -0,0 +1,17 @@ +# FLASH_ENCRYPTION & SECURE_BOOT_V2 with EFUSE_VIRTUAL_KEEP_IN_FLASH + +CONFIG_IDF_TARGET="esp32c2" + +CONFIG_PARTITION_TABLE_OFFSET=0xD000 +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="test/partitions_efuse_emul.csv" + +CONFIG_SECURE_BOOT=y +CONFIG_SECURE_BOOT_V2_ENABLED=y +CONFIG_SECURE_BOOT_SIGNING_KEY="test/secure_boot_signing_key_ecdsa_nistp256.pem" + +CONFIG_SECURE_FLASH_ENC_ENABLED=y + +# IMPORTANT: ONLY VIRTUAL eFuse MODE! +CONFIG_EFUSE_VIRTUAL=y +CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH=y diff --git a/examples/system/efuse/sdkconfig.ci.virt_sb_v2_and_fe b/examples/system/efuse/sdkconfig.ci.virt_sb_v2_and_fe.esp32c3 similarity index 85% rename from examples/system/efuse/sdkconfig.ci.virt_sb_v2_and_fe rename to examples/system/efuse/sdkconfig.ci.virt_sb_v2_and_fe.esp32c3 index 1f7b03c551..04c2764dfd 100644 --- a/examples/system/efuse/sdkconfig.ci.virt_sb_v2_and_fe +++ b/examples/system/efuse/sdkconfig.ci.virt_sb_v2_and_fe.esp32c3 @@ -1,8 +1,7 @@ # FLASH_ENCRYPTION & SECURE_BOOT_V2 with EFUSE_VIRTUAL_KEEP_IN_FLASH -# ESP32 supports SECURE_BOOT_V2 only in ECO3 -CONFIG_ESP32_REV_MIN_3=y -CONFIG_ESP32_REV_MIN=3 +CONFIG_IDF_TARGET="esp32c3" + # ESP32C3 supports SECURE_BOOT_V2 only in ECO3 CONFIG_ESP32C3_REV_MIN_3=y CONFIG_ESP32C3_REV_MIN=3 diff --git a/examples/system/efuse/sdkconfig.ci.virt_sb_v2_and_fe.esp32s2 b/examples/system/efuse/sdkconfig.ci.virt_sb_v2_and_fe.esp32s2 new file mode 100644 index 0000000000..1ba66bfa5a --- /dev/null +++ b/examples/system/efuse/sdkconfig.ci.virt_sb_v2_and_fe.esp32s2 @@ -0,0 +1,17 @@ +# FLASH_ENCRYPTION & SECURE_BOOT_V2 with EFUSE_VIRTUAL_KEEP_IN_FLASH + +CONFIG_IDF_TARGET="esp32s2" + +CONFIG_PARTITION_TABLE_OFFSET=0xD000 +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="test/partitions_efuse_emul.csv" + +CONFIG_SECURE_BOOT=y +CONFIG_SECURE_BOOT_V2_ENABLED=y +CONFIG_SECURE_BOOT_SIGNING_KEY="test/secure_boot_signing_key.pem" + +CONFIG_SECURE_FLASH_ENC_ENABLED=y + +# IMPORTANT: ONLY VIRTUAL eFuse MODE! +CONFIG_EFUSE_VIRTUAL=y +CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH=y diff --git a/examples/system/efuse/sdkconfig.ci.virt_secure_boot_v2.esp32 b/examples/system/efuse/sdkconfig.ci.virt_secure_boot_v2.esp32 new file mode 100644 index 0000000000..da26487548 --- /dev/null +++ b/examples/system/efuse/sdkconfig.ci.virt_secure_boot_v2.esp32 @@ -0,0 +1,20 @@ +# SECURE_BOOT_V2 with EFUSE_VIRTUAL_KEEP_IN_FLASH + +CONFIG_IDF_TARGET="esp32" + +# ESP32 supports SECURE_BOOT_V2 only in ECO3 +CONFIG_ESP32_REV_MIN_3=y +CONFIG_ESP32_REV_MIN=3 + +CONFIG_PARTITION_TABLE_OFFSET=0xC000 +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="test/partitions_efuse_emul.csv" + +CONFIG_SECURE_BOOT=y +CONFIG_SECURE_BOOT_V2_ENABLED=y +CONFIG_SECURE_BOOT_SIGNING_KEY="test/secure_boot_signing_key.pem" +CONFIG_SECURE_INSECURE_ALLOW_DL_MODE=y + +# IMPORTANT: ONLY VIRTUAL eFuse MODE! +CONFIG_EFUSE_VIRTUAL=y +CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH=y diff --git a/examples/system/efuse/sdkconfig.ci.virt_secure_boot_v2.esp32c2 b/examples/system/efuse/sdkconfig.ci.virt_secure_boot_v2.esp32c2 new file mode 100644 index 0000000000..6d8478ce4c --- /dev/null +++ b/examples/system/efuse/sdkconfig.ci.virt_secure_boot_v2.esp32c2 @@ -0,0 +1,16 @@ +# SECURE_BOOT_V2 with EFUSE_VIRTUAL_KEEP_IN_FLASH + +CONFIG_IDF_TARGET="esp32c2" + +CONFIG_PARTITION_TABLE_OFFSET=0xC000 +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="test/partitions_efuse_emul.csv" + +CONFIG_SECURE_BOOT=y +CONFIG_SECURE_BOOT_V2_ENABLED=y +CONFIG_SECURE_BOOT_SIGNING_KEY="test/secure_boot_signing_key_ecdsa_nistp256.pem" +CONFIG_SECURE_INSECURE_ALLOW_DL_MODE=y + +# IMPORTANT: ONLY VIRTUAL eFuse MODE! +CONFIG_EFUSE_VIRTUAL=y +CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH=y diff --git a/examples/system/efuse/sdkconfig.ci.virt_secure_boot_v2 b/examples/system/efuse/sdkconfig.ci.virt_secure_boot_v2.esp32c3 similarity index 85% rename from examples/system/efuse/sdkconfig.ci.virt_secure_boot_v2 rename to examples/system/efuse/sdkconfig.ci.virt_secure_boot_v2.esp32c3 index 1f31177a3b..35dc608a61 100644 --- a/examples/system/efuse/sdkconfig.ci.virt_secure_boot_v2 +++ b/examples/system/efuse/sdkconfig.ci.virt_secure_boot_v2.esp32c3 @@ -1,8 +1,7 @@ # SECURE_BOOT_V2 with EFUSE_VIRTUAL_KEEP_IN_FLASH -# ESP32 supports SECURE_BOOT_V2 only in ECO3 -CONFIG_ESP32_REV_MIN_3=y -CONFIG_ESP32_REV_MIN=3 +CONFIG_IDF_TARGET="esp32c3" + # ESP32C3 supports SECURE_BOOT_V2 only in ECO3 CONFIG_ESP32C3_REV_MIN_3=y CONFIG_ESP32C3_REV_MIN=3 diff --git a/examples/system/efuse/sdkconfig.ci.virt_secure_boot_v2.esp32s2 b/examples/system/efuse/sdkconfig.ci.virt_secure_boot_v2.esp32s2 new file mode 100644 index 0000000000..53b1cbcdd6 --- /dev/null +++ b/examples/system/efuse/sdkconfig.ci.virt_secure_boot_v2.esp32s2 @@ -0,0 +1,16 @@ +# SECURE_BOOT_V2 with EFUSE_VIRTUAL_KEEP_IN_FLASH + +CONFIG_IDF_TARGET="esp32s2" + +CONFIG_PARTITION_TABLE_OFFSET=0xC000 +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="test/partitions_efuse_emul.csv" + +CONFIG_SECURE_BOOT=y +CONFIG_SECURE_BOOT_V2_ENABLED=y +CONFIG_SECURE_BOOT_SIGNING_KEY="test/secure_boot_signing_key.pem" +CONFIG_SECURE_INSECURE_ALLOW_DL_MODE=y + +# IMPORTANT: ONLY VIRTUAL eFuse MODE! +CONFIG_EFUSE_VIRTUAL=y +CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH=y diff --git a/examples/system/efuse/test/secure_boot_signing_key_ecdsa_nistp256.pem b/examples/system/efuse/test/secure_boot_signing_key_ecdsa_nistp256.pem new file mode 100644 index 0000000000..b885d6c6bc --- /dev/null +++ b/examples/system/efuse/test/secure_boot_signing_key_ecdsa_nistp256.pem @@ -0,0 +1,5 @@ +-----BEGIN EC PRIVATE KEY----- +MHcCAQEEIKbc9BxtbY3xeDA9J5PCCsPIk7pcTDylSQEzH2qXYcNCoAoGCCqGSM49 +AwEHoUQDQgAEU9yRNPfLJd3+ZsvdjWMqQgGmmccAnwBtb+IJz8KkbbXys38S7D+z +5MLc+VY2AwGXNUyd0myLInojX2SKUOsOfw== +-----END EC PRIVATE KEY----- diff --git a/examples/system/esp_event/user_event_loops/main/main.c b/examples/system/esp_event/user_event_loops/main/main.c index fe83df2d12..f99d2d1def 100644 --- a/examples/system/esp_event/user_event_loops/main/main.c +++ b/examples/system/esp_event/user_event_loops/main/main.c @@ -23,6 +23,9 @@ esp_event_loop_handle_t loop_without_task; static void application_task(void* args) { + // Wait to be started by the main task + ulTaskNotifyTake(pdTRUE, portMAX_DELAY); + while(1) { ESP_LOGI(TAG, "application_task: running application task"); esp_event_loop_run(loop_without_task, 100); @@ -58,6 +61,9 @@ static void task_iteration_handler(void* handler_args, esp_event_base_t base, in static void task_event_source(void* args) { + // Wait to be started by the main task + ulTaskNotifyTake(pdTRUE, portMAX_DELAY); + for(int iteration = 1; iteration <= TASK_ITERATIONS_COUNT; iteration++) { esp_event_loop_handle_t loop_to_post_to; @@ -112,12 +118,19 @@ void app_main(void) ESP_ERROR_CHECK(esp_event_handler_instance_register_with(loop_with_task, TASK_EVENTS, TASK_ITERATION_EVENT, task_iteration_handler, loop_with_task, NULL)); ESP_ERROR_CHECK(esp_event_handler_instance_register_with(loop_without_task, TASK_EVENTS, TASK_ITERATION_EVENT, task_iteration_handler, loop_without_task, NULL)); + // Create the event source task + TaskHandle_t task_event_source_hdl; ESP_LOGI(TAG, "starting event source"); + xTaskCreate(task_event_source, "task_event_source", 3072, NULL, uxTaskPriorityGet(NULL) + 1, &task_event_source_hdl); - // Create the event source task with the same priority as the current task - xTaskCreate(task_event_source, "task_event_source", 3072, NULL, uxTaskPriorityGet(NULL), NULL); - + // Create the application task + TaskHandle_t application_task_hdl; ESP_LOGI(TAG, "starting application task"); - // Create the application task with the same priority as the current task - xTaskCreate(application_task, "application_task", 3072, NULL, uxTaskPriorityGet(NULL), NULL); + xTaskCreate(application_task, "application_task", 3072, NULL, uxTaskPriorityGet(NULL) + 1, &application_task_hdl); + + // Start the event source task first to post an event + xTaskNotifyGive(task_event_source_hdl); + + // Start the application task to run the event handlers + xTaskNotifyGive(application_task_hdl); } diff --git a/examples/system/esp_timer/pytest_esp_timer.py b/examples/system/esp_timer/pytest_esp_timer.py index 229a95afb8..4a7924282f 100644 --- a/examples/system/esp_timer/pytest_esp_timer.py +++ b/examples/system/esp_timer/pytest_esp_timer.py @@ -48,22 +48,22 @@ def test_esp_timer(dut: Dut) -> None: logging.info('Start time: {} us'.format(start_time)) match = dut.expect(TIMER_DUMP_LINE_REGEX, timeout=2) - assert(match.group(1).decode('utf8') == 'periodic' and int(match.group(2)) == INITIAL_TIMER_PERIOD) + assert match.group(1).decode('utf8') == 'periodic' and int(match.group(2)) == INITIAL_TIMER_PERIOD match = dut.expect(TIMER_DUMP_LINE_REGEX, timeout=2) - assert(match.group(1).decode('utf8') == 'one-shot' and int(match.group(2)) == 0) + assert match.group(1).decode('utf8') == 'one-shot' and int(match.group(2)) == 0 for i in range(0, 5): match = dut.expect(PERIODIC_TIMER_REGEX, timeout=2) cur_time = int(match.group(1)) diff = start_time + (i + 1) * INITIAL_TIMER_PERIOD - cur_time logging.info('Callback #{}, time: {} us, diff: {} us'.format(i, cur_time, diff)) - assert(abs(diff) < 100) + assert abs(diff) < 100 match = dut.expect(ONE_SHOT_REGEX, timeout=3) one_shot_timer_time = int(match.group(1)) diff = start_time + ONE_SHOT_TIMER_PERIOD - one_shot_timer_time logging.info('One-shot timer, time: {} us, diff: {}'.format(one_shot_timer_time, diff)) - assert(abs(diff) < 350) + assert abs(diff) < 350 match = dut.expect(RESTART_REGEX, timeout=3) start_time = int(match.group(1)) @@ -74,7 +74,7 @@ def test_esp_timer(dut: Dut) -> None: cur_time = int(match.group(1)) diff = start_time + (i + 1) * FINAL_TIMER_PERIOD - cur_time logging.info('Callback #{}, time: {} us, diff: {} us'.format(i, cur_time, diff)) - assert(abs(diff) < 100) + assert abs(diff) < 100 match = dut.expect(LIGHT_SLEEP_ENTER_REGEX, timeout=2) sleep_enter_time = int(match.group(1)) @@ -85,13 +85,13 @@ def test_esp_timer(dut: Dut) -> None: logging.info('Enter sleep: {}, exit sleep: {}, slept: {}'.format( sleep_enter_time, sleep_exit_time, sleep_time)) - assert(abs(sleep_time - LIGHT_SLEEP_TIME) < 1000) + assert abs(sleep_time - LIGHT_SLEEP_TIME) < 1000 for i in range(5, 7): match = dut.expect(PERIODIC_TIMER_REGEX, timeout=2) cur_time = int(match.group(1)) diff = abs(start_time + (i + 1) * FINAL_TIMER_PERIOD - cur_time) logging.info('Callback #{}, time: {} us, diff: {} us'.format(i, cur_time, diff)) - assert(diff < 100) + assert diff < 100 dut.expect(STOP_REGEX, timeout=2) diff --git a/examples/system/flash_suspend/pytest_flash_suspend.py b/examples/system/flash_suspend/pytest_flash_suspend.py index 0929a6b6ad..603233dc52 100644 --- a/examples/system/flash_suspend/pytest_flash_suspend.py +++ b/examples/system/flash_suspend/pytest_flash_suspend.py @@ -14,7 +14,7 @@ def test_flash_suspend_example(dut: Dut) -> None: dut.expect_exact('found partition') res = dut.expect(r'During Erase, ISR callback function\(in flash\) response time:\s+(\d+(\.\d{1,2})) us') response_time = res.group(1).decode('utf8') - assert 0 <= float(response_time) < 40 + assert 0 <= float(response_time) < 120 res = dut.expect(r'During Erase, ISR callback function\(in iram\) response time:\s+(\d+(\.\d{1,2})) us') response_time = res.group(1).decode('utf8') diff --git a/examples/system/light_sleep/README.md b/examples/system/light_sleep/README.md index 1a24c4ebce..70ada8ab88 100644 --- a/examples/system/light_sleep/README.md +++ b/examples/system/light_sleep/README.md @@ -61,6 +61,14 @@ Note #2: only UART0 and UART1 (if has) are supported to be configured as wake up Note #3: due to limitation of the HW, the bytes that received during light sleep is only used for waking up, and it will not be received by UART peripheral or passed to the driver. +### Wake-up by Touch Pad + +For this example, pressing any registered touch buttons can wake up the chip. + +Note #1: For light sleep, all registered touch buttons can wake up the chip. But only the channel which is configured as wake up channel can wake up the chip from deep sleep. + +Note #2: Waking-up by touch pad relies on 'touch_element' driver, which can only support ESP32-S2 and ESP32-S3 currently. + ``` Entering light sleep Returned from light sleep, reason: timer, t=2713 ms, slept for 1999 ms @@ -83,6 +91,11 @@ Entering light sleep Returned from light sleep, reason: pin, t=12564 ms, slept for 1 ms Waiting for GPIO9 to go high... Entering light sleep +... +I (361) touch_wakeup: Button[1] Press +Returned from light sleep, reason: touch, t=14471 ms, slept for 467 ms +Entering light sleep + ... ``` diff --git a/examples/system/light_sleep/main/CMakeLists.txt b/examples/system/light_sleep/main/CMakeLists.txt index d5b05c298c..25d2112b95 100644 --- a/examples/system/light_sleep/main/CMakeLists.txt +++ b/examples/system/light_sleep/main/CMakeLists.txt @@ -3,5 +3,11 @@ set(srcs "light_sleep_example_main.c" "timer_wakeup.c" "uart_wakeup.c") +set(TOUCH_ELEMENT_COMPATIBLE_TARGETS "esp32s2" "esp32s3") + +if(IDF_TARGET IN_LIST TOUCH_ELEMENT_COMPATIBLE_TARGETS) + list(APPEND srcs "touch_wakeup.c") +endif() + idf_component_register(SRCS ${srcs} INCLUDE_DIRS ".") diff --git a/examples/system/light_sleep/main/light_sleep_example.h b/examples/system/light_sleep/main/light_sleep_example.h index b3faf43f57..c3401c4aed 100644 --- a/examples/system/light_sleep/main/light_sleep_example.h +++ b/examples/system/light_sleep/main/light_sleep_example.h @@ -18,6 +18,10 @@ esp_err_t example_register_timer_wakeup(void); esp_err_t example_register_uart_wakeup(void); +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 +void example_register_touch_wakeup(void); +#endif + #ifdef __cplusplus } #endif diff --git a/examples/system/light_sleep/main/light_sleep_example_main.c b/examples/system/light_sleep/main/light_sleep_example_main.c index fccb36883f..4beb322e20 100644 --- a/examples/system/light_sleep/main/light_sleep_example_main.c +++ b/examples/system/light_sleep/main/light_sleep_example_main.c @@ -50,6 +50,11 @@ static void light_sleep_task(void *args) * Otherwise the chip may fall sleep again before running uart task */ vTaskDelay(1); break; +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + case ESP_SLEEP_WAKEUP_TOUCHPAD: + wakeup_reason = "touch"; + break; +#endif default: wakeup_reason = "other"; break; @@ -72,6 +77,10 @@ void app_main(void) example_register_timer_wakeup(); /* Enable wakeup from light sleep by uart */ example_register_uart_wakeup(); +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + /* Enable wakeup from light sleep by touch element */ + example_register_touch_wakeup(); +#endif xTaskCreate(light_sleep_task, "light_sleep_task", 4096, NULL, 6, NULL); } diff --git a/examples/system/light_sleep/main/touch_wakeup.c b/examples/system/light_sleep/main/touch_wakeup.c new file mode 100644 index 0000000000..92d0668c10 --- /dev/null +++ b/examples/system/light_sleep/main/touch_wakeup.c @@ -0,0 +1,101 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "esp_log.h" +#include "esp_sleep.h" +#include "touch_element/touch_button.h" + +static const char *TAG = "touch_wakeup"; + +#define TOUCH_BUTTON_NUM 5 + +/* Touch buttons handle */ +static touch_button_handle_t button_handle[TOUCH_BUTTON_NUM]; + + +/* Touch buttons channel array */ +static const touch_pad_t channel_array[TOUCH_BUTTON_NUM] = { + TOUCH_PAD_NUM1, + TOUCH_PAD_NUM2, + TOUCH_PAD_NUM3, + TOUCH_PAD_NUM4, + TOUCH_PAD_NUM5, +}; + +/* Touch buttons channel sensitivity array */ +static const float channel_sens_array[TOUCH_BUTTON_NUM] = { + 0.03F, + 0.03F, + 0.03F, + 0.03F, + 0.03F, +}; + +/* Button event handler task */ +static void button_handler_task(void *arg) +{ + (void) arg; //Unused + touch_elem_message_t element_message; + while (1) { + /* Waiting for touch element messages */ + touch_element_message_receive(&element_message, portMAX_DELAY); + if (element_message.element_type != TOUCH_ELEM_TYPE_BUTTON) { + continue; + } + /* Decode message */ + const touch_button_message_t *button_message = touch_button_get_message(&element_message); + if (button_message->event == TOUCH_BUTTON_EVT_ON_PRESS) { + ESP_LOGI(TAG, "Button[%"PRIu32"] Press", (uint32_t)element_message.arg); + } else if (button_message->event == TOUCH_BUTTON_EVT_ON_RELEASE) { + ESP_LOGI(TAG, "Button[%"PRIu32"] Release", (uint32_t)element_message.arg); + } else if (button_message->event == TOUCH_BUTTON_EVT_ON_LONGPRESS) { + ESP_LOGI(TAG, "Button[%"PRIu32"] LongPress", (uint32_t)element_message.arg); + } + } + vTaskDelete(NULL); +} + +esp_err_t example_register_touch_wakeup(void) +{ + /* Initialize Touch Element library */ + touch_elem_global_config_t global_config = TOUCH_ELEM_GLOBAL_DEFAULT_CONFIG(); + ESP_ERROR_CHECK(touch_element_install(&global_config)); + ESP_LOGI(TAG, "Touch element library installed"); + + touch_button_global_config_t button_global_config = TOUCH_BUTTON_GLOBAL_DEFAULT_CONFIG(); + ESP_ERROR_CHECK(touch_button_install(&button_global_config)); + ESP_LOGI(TAG, "Touch button installed"); + for (int i = 0; i < TOUCH_BUTTON_NUM; i++) { + touch_button_config_t button_config = { + .channel_num = channel_array[i], + .channel_sens = channel_sens_array[i] + }; + /* Create Touch buttons */ + ESP_ERROR_CHECK(touch_button_create(&button_config, &button_handle[i])); + /* Set EVENT as the dispatch method */ + ESP_ERROR_CHECK(touch_button_set_dispatch_method(button_handle[i], TOUCH_ELEM_DISP_EVENT)); + /* Subscribe touch button events (On Press, On Release, On LongPress) */ + ESP_ERROR_CHECK(touch_button_subscribe_event(button_handle[i], + TOUCH_ELEM_EVENT_ON_PRESS | + TOUCH_ELEM_EVENT_ON_RELEASE | + TOUCH_ELEM_EVENT_ON_LONGPRESS, + (void *)channel_array[i])); + } + ESP_LOGI(TAG, "Touch buttons created"); + + touch_elem_sleep_config_t sleep_config = { + .sample_count = global_config.hardware.sample_count, + .sleep_cycle = global_config.hardware.sleep_cycle, + }; + /* Enable one of registered touch button as light/deep sleep wake-up source */ + ESP_ERROR_CHECK(touch_element_enable_light_sleep(&sleep_config)); + + touch_element_start(); + xTaskCreate(&button_handler_task, "button_handler_task", 4 * 1024, NULL, 6, NULL); + ESP_LOGI(TAG, "touch wakeup source is ready"); + return ESP_OK; +} diff --git a/examples/system/light_sleep/pytest_light_sleep.py b/examples/system/light_sleep/pytest_light_sleep.py index 4f9025aa59..4b0fc8c9a7 100644 --- a/examples/system/light_sleep/pytest_light_sleep.py +++ b/examples/system/light_sleep/pytest_light_sleep.py @@ -39,7 +39,7 @@ def test_light_sleep(dut: Dut) -> None: match = dut.expect(EXIT_SLEEP_REGEX) logging.info('Got second sleep period, wakeup from {}, slept for {}'.format(match.group(1), match.group(3))) # sleep time error should be less than 1ms - assert(match.group(1).decode('utf8') == 'timer' and int(match.group(3)) >= WAKEUP_INTERVAL_MS - 1 and int(match.group(3)) <= WAKEUP_INTERVAL_MS + 1) + assert match.group(1).decode('utf8') == 'timer' and int(match.group(3)) >= WAKEUP_INTERVAL_MS - 1 and int(match.group(3)) <= WAKEUP_INTERVAL_MS + 1 # this time we'll test gpio wakeup dut.expect_exact(ENTERING_SLEEP_STR) @@ -48,7 +48,7 @@ def test_light_sleep(dut: Dut) -> None: time.sleep(1) match = dut.expect(EXIT_SLEEP_PIN_REGEX) logging.info('Got third sleep period, wakeup from {}, slept for {}'.format(match.group(1), match.group(3))) - assert(int(match.group(3)) < WAKEUP_INTERVAL_MS) + assert int(match.group(3)) < WAKEUP_INTERVAL_MS dut.expect(WAITING_FOR_GPIO_STR) logging.info('Is waiting for GPIO...') @@ -62,9 +62,9 @@ def test_light_sleep(dut: Dut) -> None: time.sleep(1) match = dut.expect(EXIT_SLEEP_UART_REGEX) logging.info('Got third sleep period, wakeup from {}, slept for {}'.format(match.group(1), match.group(3))) - assert(int(match.group(3)) < WAKEUP_INTERVAL_MS) + assert int(match.group(3)) < WAKEUP_INTERVAL_MS logging.info('Went to sleep again') match = dut.expect(EXIT_SLEEP_REGEX) - assert(match.group(1).decode('utf8') == 'timer' and int(match.group(3)) >= WAKEUP_INTERVAL_MS - 1 and int(match.group(3)) <= WAKEUP_INTERVAL_MS + 1) + assert match.group(1).decode('utf8') == 'timer' and int(match.group(3)) >= WAKEUP_INTERVAL_MS - 1 and int(match.group(3)) <= WAKEUP_INTERVAL_MS + 1 logging.info('Woke up from timer again') diff --git a/examples/system/ota/advanced_https_ota/pytest_advanced_ota.py b/examples/system/ota/advanced_https_ota/pytest_advanced_ota.py index aa68a1bc03..a0970c2449 100644 --- a/examples/system/ota/advanced_https_ota/pytest_advanced_ota.py +++ b/examples/system/ota/advanced_https_ota/pytest_advanced_ota.py @@ -129,7 +129,7 @@ def test_examples_protocol_advanced_https_ota_example(dut: Dut) -> None: print('writing to device: {}'.format('https://' + host_ip + ':' + str(server_port) + '/' + bin_name)) dut.write('https://' + host_ip + ':' + str(server_port) + '/' + bin_name) - dut.expect('upgrade successful. Rebooting ...', timeout=60) + dut.expect('upgrade successful. Rebooting ...', timeout=150) finally: thread1.terminate() @@ -383,7 +383,7 @@ def test_examples_protocol_advanced_https_ota_example_chunked(dut: Dut) -> None: dut.expect('Starting Advanced OTA example', timeout=30) print('writing to device: {}'.format('https://' + host_ip + ':8070/' + bin_name)) dut.write('https://' + host_ip + ':8070/' + bin_name) - dut.expect('upgrade successful. Rebooting ...', timeout=60) + dut.expect('upgrade successful. Rebooting ...', timeout=150) # after reboot dut.expect('Loaded app from partition at offset', timeout=30) dut.expect('OTA example app_main start', timeout=10) @@ -437,7 +437,7 @@ def test_examples_protocol_advanced_https_ota_example_redirect_url(dut: Dut) -> try: print('writing to device: {}'.format('https://' + host_ip + ':' + str(redirection_server_port) + '/' + bin_name)) dut.write('https://' + host_ip + ':' + str(redirection_server_port) + '/' + bin_name) - dut.expect('upgrade successful. Rebooting ...', timeout=60) + dut.expect('upgrade successful. Rebooting ...', timeout=150) # after reboot dut.expect('Loaded app from partition at offset', timeout=30) dut.expect('OTA example app_main start', timeout=10) @@ -612,7 +612,7 @@ def test_examples_protocol_advanced_https_ota_example_nimble_gatts(dut: Dut) -> print('Started GAP advertising.') dut.write('https://' + host_ip + ':' + str(server_port) + '/' + bin_name) - dut.expect('upgrade successful. Rebooting ...', timeout=60) + dut.expect('upgrade successful. Rebooting ...', timeout=150) # after reboot dut.expect('Loaded app from partition at offset', timeout=30) dut.expect('OTA example app_main start', timeout=10) @@ -665,7 +665,7 @@ def test_examples_protocol_advanced_https_ota_example_bluedroid_gatts(dut: Dut) print('Started GAP advertising.') dut.write('https://' + host_ip + ':' + str(server_port) + '/' + bin_name) - dut.expect('upgrade successful. Rebooting ...', timeout=60) + dut.expect('upgrade successful. Rebooting ...', timeout=150) # after reboot dut.expect('Loaded app from partition at offset', timeout=30) dut.expect('OTA example app_main start', timeout=10) @@ -716,7 +716,7 @@ def test_examples_protocol_advanced_https_ota_example_openssl_aligned_bin(dut: D dut.expect('Starting Advanced OTA example', timeout=30) print('writing to device: {}'.format('https://' + host_ip + ':8070/' + aligned_bin_name)) dut.write('https://' + host_ip + ':8070/' + aligned_bin_name) - dut.expect('upgrade successful. Rebooting ...', timeout=60) + dut.expect('upgrade successful. Rebooting ...', timeout=150) # after reboot dut.expect('Loaded app from partition at offset', timeout=30) dut.expect('OTA example app_main start', timeout=10) diff --git a/examples/system/ota/native_ota_example/main/native_ota_example.c b/examples/system/ota/native_ota_example/main/native_ota_example.c index ebebbabd99..287405436f 100644 --- a/examples/system/ota/native_ota_example/main/native_ota_example.c +++ b/examples/system/ota/native_ota_example/main/native_ota_example.c @@ -13,6 +13,7 @@ #include "esp_event.h" #include "esp_log.h" #include "esp_ota_ops.h" +#include "esp_app_format.h" #include "esp_http_client.h" #include "esp_flash_partitions.h" #include "esp_partition.h" diff --git a/examples/system/ota/pre_encrypted_ota/pytest_pre_encrypted_ota.py b/examples/system/ota/pre_encrypted_ota/pytest_pre_encrypted_ota.py index b9f2f056c4..58286eefbf 100644 --- a/examples/system/ota/pre_encrypted_ota/pytest_pre_encrypted_ota.py +++ b/examples/system/ota/pre_encrypted_ota/pytest_pre_encrypted_ota.py @@ -77,7 +77,7 @@ def test_examples_protocol_pre_encrypted_ota_example(dut: Dut) -> None: dut.write('https://' + host_ip + ':' + str(server_port) + '/' + enc_bin_name) dut.expect('Magic Verified', timeout=30) dut.expect('Reading RSA private key', timeout=30) - dut.expect('upgrade successful. Rebooting', timeout=30) + dut.expect('upgrade successful. Rebooting', timeout=60) # after reboot dut.expect('Loaded app from partition at offset', timeout=30) finally: diff --git a/examples/system/startup_time/example_test.py b/examples/system/startup_time/example_test.py deleted file mode 100644 index 68fbe79918..0000000000 --- a/examples/system/startup_time/example_test.py +++ /dev/null @@ -1,22 +0,0 @@ -from __future__ import print_function - -import re - -import ttfw_idf -from tiny_test_fw import TinyFW - - -@ttfw_idf.idf_example_test(env_tag='Example_GENERIC', target=['esp32', 'esp32s2', 'esp32c3']) -def test_startup_time_example(env, _): - key = 'startup_time' - dut = env.get_dut(key, 'examples/system/startup_time') - dut.start_app() - - res = dut.expect(re.compile(r'\((\d+)\) [^:]+: App started!')) - time = int(res[0]) - - TinyFW.JunitReport.update_performance([(key, time)]) - - -if __name__ == '__main__': - test_startup_time_example() diff --git a/examples/system/startup_time/pytest_startup_time.py b/examples/system/startup_time/pytest_startup_time.py new file mode 100644 index 0000000000..a2eff33822 --- /dev/null +++ b/examples/system/startup_time/pytest_startup_time.py @@ -0,0 +1,20 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 +import logging + +import pytest +from pytest_embedded import Dut + + +@pytest.mark.supported_targets +@pytest.mark.generic +@pytest.mark.parametrize('config', [ + 'defaults', + 'always_skip', +], indirect=True) +def test_startup_time_example(dut: Dut) -> None: + + res = dut.expect(r'\((\d+)\) [^:]+: App started!') + time = int(res[1]) + + logging.info(f'[Performance][startup_time]: {time}') diff --git a/examples/system/startup_time/sdkconfig.ci.always_skip b/examples/system/startup_time/sdkconfig.ci.always_skip new file mode 100644 index 0000000000..951b84e129 --- /dev/null +++ b/examples/system/startup_time/sdkconfig.ci.always_skip @@ -0,0 +1 @@ +CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS=y diff --git a/examples/system/startup_time/sdkconfig.ci.defaults b/examples/system/startup_time/sdkconfig.ci.defaults new file mode 100644 index 0000000000..e69de29bb2 diff --git a/examples/system/sysview_tracing/README.md b/examples/system/sysview_tracing/README.md index fff1141ebc..04dd0f3288 100644 --- a/examples/system/sysview_tracing/README.md +++ b/examples/system/sysview_tracing/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-S2 | -| ----------------- | ----- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | # Example: Application Level Tracing - SystemView Tracing (sysview_tracing) This test code shows how to perform system-wide behavioral analysis of the program using [SEGGER SystemView tool](https://www.segger.com/products/development-tools/systemview/). @@ -127,7 +127,7 @@ NOTE: In order to run this example you need OpenOCD version `v0.10.0-esp32-20181 xtensa-esp32-elf-gdb -x gdbinit build/sysview_tracing.elf ``` - **Note:** Replace `xtensa-esp32-elf-gdb` with `xtensa-esp32s2-elf-gdb` if running the example on ESP32-S2. + **Note:** Replace `xtensa-esp32-elf-gdb` with the related gdb tool (e.g. `xtensa-esp32s2-elf-gdb`, `xtensa-esp32s3-elf-gdb` or `riscv32-esp-elf-gdb`) if running the example on different chip. 7. When program prints the last message, interrupt its execution (e.g. by pressing `CTRL+C`) and type the following command in GDB console to stop tracing: diff --git a/examples/system/sysview_tracing_heap_log/README.md b/examples/system/sysview_tracing_heap_log/README.md index 63b8cb17c5..590e3b56cc 100644 --- a/examples/system/sysview_tracing_heap_log/README.md +++ b/examples/system/sysview_tracing_heap_log/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-S2 | -| ----------------- | ----- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | # SystemView Heap and Log Tracing Example diff --git a/examples/system/task_watchdog/README.md b/examples/system/task_watchdog/README.md index 7c4a9d631e..e04259d6fc 100644 --- a/examples/system/task_watchdog/README.md +++ b/examples/system/task_watchdog/README.md @@ -21,7 +21,7 @@ Before project configuration and build, be sure to set the correct chip target u ### Configure the project -Program should run correctly without needing any special configuration. However, users can disable `CONFIG_ESP_TASK_WDT` which will prevent the TWDT from being automatically initialized on startup. If disabled, the example will manually initialize the TWDT. +Program should run correctly without needing any special configuration. However, users can disable `CONFIG_ESP_TASK_WDT_INIT` which will prevent the TWDT from being automatically initialized on startup. If disabled, the example will manually initialize the TWDT. ### Build and Flash diff --git a/examples/system/task_watchdog/main/task_watchdog_example_main.c b/examples/system/task_watchdog/main/task_watchdog_example_main.c index 2ff643b2cb..2a3a8bb588 100644 --- a/examples/system/task_watchdog/main/task_watchdog_example_main.c +++ b/examples/system/task_watchdog/main/task_watchdog_example_main.c @@ -71,7 +71,7 @@ void task_func(void *arg) void app_main(void) { -#if !CONFIG_ESP_TASK_WDT +#if !CONFIG_ESP_TASK_WDT_INIT // If the TWDT was not initialized automatically on startup, manually intialize it now esp_task_wdt_config_t twdt_config = { .timeout_ms = TWDT_TIMEOUT_MS, @@ -80,7 +80,7 @@ void app_main(void) }; ESP_ERROR_CHECK(esp_task_wdt_init(&twdt_config)); printf("TWDT initialized\n"); -#endif // CONFIG_ESP_TASK_WDT +#endif // CONFIG_ESP_TASK_WDT_INIT // Create a task run_loop = true; @@ -94,10 +94,10 @@ void app_main(void) run_loop = false; ulTaskNotifyTake(pdTRUE, portMAX_DELAY); -#if !CONFIG_ESP_TASK_WDT +#if !CONFIG_ESP_TASK_WDT_INIT // If we manually initialized the TWDT, deintialize it now ESP_ERROR_CHECK(esp_task_wdt_deinit()); printf("TWDT deinitialized\n"); -#endif // CONFIG_ESP_TASK_WDT +#endif // CONFIG_ESP_TASK_WDT_INIT printf("Example complete\n"); } diff --git a/examples/system/ulp_fsm/ulp/main/ulp/wake_up.S b/examples/system/ulp_fsm/ulp/main/ulp/wake_up.S index 34b80b4118..1ccc94a9f4 100644 --- a/examples/system/ulp_fsm/ulp/main/ulp/wake_up.S +++ b/examples/system/ulp_fsm/ulp/main/ulp/wake_up.S @@ -1,14 +1,28 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ /* ULP assembly files are passed through C preprocessor first, so include directives and C macros may be used in these files */ #include "soc/rtc_cntl_reg.h" #include "soc/soc_ulp.h" +#include "sdkconfig.h" .global wake_up wake_up: + /* Check if the system is in sleep mode */ +#if CONFIG_IDF_TARGET_ESP32 + READ_RTC_REG(RTC_CNTL_LOW_POWER_ST_REG, 27, 0) +#else + READ_RTC_FIELD(RTC_CNTL_LOW_POWER_ST_REG, RTC_CNTL_MAIN_STATE_IN_IDLE) +#endif + move r1, r0 /* Check if the system can be woken up */ READ_RTC_FIELD(RTC_CNTL_LOW_POWER_ST_REG, RTC_CNTL_RDY_FOR_WAKEUP) - and r0, r0, 1 + /* If the system is in normal mode or if the system is in sleep mode with ready for wakeup set, we can signal the main CPU to wakeup */ + or r0, r0, r1 jump wake_up, eq /* Wake up the SoC, end program */ diff --git a/examples/system/ulp_fsm/ulp_adc/README.md b/examples/system/ulp_fsm/ulp_adc/README.md index b27ef2772d..21dc77038f 100644 --- a/examples/system/ulp_fsm/ulp_adc/README.md +++ b/examples/system/ulp_fsm/ulp_adc/README.md @@ -1,11 +1,11 @@ -| Supported Targets | ESP32 | -| ----------------- | ----- | +| Supported Targets | ESP32 | ESP32-S3 | +| ----------------- | ----- | -------- | # ULP ADC Example This example demonstrates how to use the ULP coprocessor to poll ADC in deep sleep. -ULP program periodically measures the input voltage on GPIO34. The voltage is compared to two thresholds. If the voltage is less than the low threshold, or higher than the high threshold, ULP wakes up the system. +ULP program periodically measures the input voltage on ADC_CHANNEL_6 (GPIO34 on ESP32, GPIO7 on ESP32-S3). The voltage is compared to two thresholds. If the voltage is less than the low threshold, or higher than the high threshold, ULP wakes up the system. By default, thresholds are set to 1.35V and 1.75V, approximately. diff --git a/examples/system/ulp_fsm/ulp_adc/main/ulp/adc.S b/examples/system/ulp_fsm/ulp_adc/main/ulp/adc.S index 1b59ccee73..b96f51c3b0 100644 --- a/examples/system/ulp_fsm/ulp_adc/main/ulp/adc.S +++ b/examples/system/ulp_fsm/ulp_adc/main/ulp/adc.S @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ /* ULP Example: using ADC in deep sleep This example code is in the Public Domain (or CC0 licensed, at your option.) @@ -22,9 +27,9 @@ */ #include "soc/rtc_cntl_reg.h" #include "soc/soc_ulp.h" +#include "example_config.h" - /* ADC1 channel 6, GPIO34 */ - .set adc_channel, 6 + .set adc_channel, EXAMPLE_ADC_CHANNEL /* Configure the number of ADC samples to average on each measurement. For convenience, make it a power of 2. */ diff --git a/examples/system/ulp_fsm/ulp_adc/main/ulp/example_config.h b/examples/system/ulp_fsm/ulp_adc/main/ulp/example_config.h new file mode 100644 index 0000000000..baa86dd842 --- /dev/null +++ b/examples/system/ulp_fsm/ulp_adc/main/ulp/example_config.h @@ -0,0 +1,16 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#pragma once + +/* Ints are used here to be able to include the file in assembly as well */ +#define EXAMPLE_ADC_CHANNEL 6 // ADC_CHANNEL_6, GPIO34 on ESP32, GPIO7 on ESP32-S3 +#define EXAMPLE_ADC_UNIT 0 // ADC_UNIT_1 +#define EXAMPLE_ADC_ATTEN 3 // ADC_ATTEN_DB_11 +#define EXAMPLE_ADC_WIDTH 0 // ADC_BITWIDTH_DEFAULT + +/* Set low and high thresholds, approx. 1.35V - 1.75V*/ +#define EXAMPLE_ADC_LOW_TRESHOLD 1500 +#define EXAMPLE_ADC_HIGH_TRESHOLD 2000 diff --git a/examples/system/ulp_fsm/ulp_adc/main/ulp_adc_example_main.c b/examples/system/ulp_fsm/ulp_adc/main/ulp_adc_example_main.c index 6b3ff56485..a8d431c755 100644 --- a/examples/system/ulp_fsm/ulp_adc/main/ulp_adc_example_main.c +++ b/examples/system/ulp_fsm/ulp_adc/main/ulp_adc_example_main.c @@ -10,16 +10,18 @@ #include #include #include "esp_sleep.h" -#include "nvs.h" -#include "nvs_flash.h" #include "soc/rtc_cntl_reg.h" #include "soc/sens_reg.h" #include "driver/gpio.h" #include "driver/rtc_io.h" -#include "driver/dac.h" -#include "esp32/ulp.h" +#include "ulp.h" #include "ulp_main.h" #include "esp_adc/adc_oneshot.h" +#include "ulp/example_config.h" +#include "ulp_adc.h" + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" extern const uint8_t ulp_main_bin_start[] asm("_binary_ulp_main_bin_start"); extern const uint8_t ulp_main_bin_end[] asm("_binary_ulp_main_bin_end"); @@ -51,6 +53,12 @@ void app_main(void) printf("Entering deep sleep\n\n"); start_ulp_program(); ESP_ERROR_CHECK( esp_sleep_enable_ulp_wakeup() ); + +#if !CONFIG_IDF_TARGET_ESP32 + /* RTC peripheral power domain needs to be kept on to keep SAR ADC related configs during sleep */ + esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON); +#endif + esp_deep_sleep_start(); } @@ -60,35 +68,31 @@ static void init_ulp_program(void) (ulp_main_bin_end - ulp_main_bin_start) / sizeof(uint32_t)); ESP_ERROR_CHECK(err); - //-------------ADC1 Init---------------// - adc_oneshot_unit_handle_t adc1_handle; - adc_oneshot_unit_init_cfg_t init_config1 = { - .unit_id = ADC_UNIT_1, + ulp_adc_cfg_t cfg = { + .adc_n = EXAMPLE_ADC_UNIT, + .channel = EXAMPLE_ADC_CHANNEL, + .width = EXAMPLE_ADC_WIDTH, + .atten = EXAMPLE_ADC_ATTEN, .ulp_mode = ADC_ULP_MODE_FSM, }; - ESP_ERROR_CHECK(adc_oneshot_new_unit(&init_config1, &adc1_handle)); - //-------------ADC1 Channel Config---------------// - // Note: when changing channel here, also change 'adc_channel' constant in adc.S - adc_oneshot_chan_cfg_t config = { - .bitwidth = ADC_BITWIDTH_DEFAULT, - .atten = ADC_ATTEN_DB_11, - }; - ESP_ERROR_CHECK(adc_oneshot_config_channel(adc1_handle, ADC_CHANNEL_6, &config)); + ESP_ERROR_CHECK(ulp_adc_init(&cfg)); - /* Set low and high thresholds, approx. 1.35V - 1.75V*/ - ulp_low_thr = 1500; - ulp_high_thr = 2000; + ulp_low_thr = EXAMPLE_ADC_LOW_TRESHOLD; + ulp_high_thr = EXAMPLE_ADC_HIGH_TRESHOLD; /* Set ULP wake up period to 20ms */ ulp_set_wakeup_period(0, 20000); +#if CONFIG_IDF_TARGET_ESP32 /* Disconnect GPIO12 and GPIO15 to remove current drain through - * pullup/pulldown resistors. + * pullup/pulldown resistors on modules which have these (e.g. ESP32-WROVER) * GPIO12 may be pulled high to select flash voltage. */ rtc_gpio_isolate(GPIO_NUM_12); rtc_gpio_isolate(GPIO_NUM_15); +#endif // CONFIG_IDF_TARGET_ESP32 + esp_deep_sleep_disable_rom_logging(); // suppress boot messages } diff --git a/examples/system/ulp_fsm/ulp_adc/pytest_ulp_fsm_adc.py b/examples/system/ulp_fsm/ulp_adc/pytest_ulp_fsm_adc.py index 0908d8c931..b5c9d9974c 100644 --- a/examples/system/ulp_fsm/ulp_adc/pytest_ulp_fsm_adc.py +++ b/examples/system/ulp_fsm/ulp_adc/pytest_ulp_fsm_adc.py @@ -8,6 +8,7 @@ from pytest_embedded import Dut @pytest.mark.esp32 +@pytest.mark.esp32s3 @pytest.mark.generic def test_ulp_fsm_adc(dut: Dut) -> None: diff --git a/examples/system/ulp_riscv/adc/main/ulp_riscv_adc_example_main.c b/examples/system/ulp_riscv/adc/main/ulp_riscv_adc_example_main.c index b18951b6d4..c1806f6d02 100644 --- a/examples/system/ulp_riscv/adc/main/ulp_riscv_adc_example_main.c +++ b/examples/system/ulp_riscv/adc/main/ulp_riscv_adc_example_main.c @@ -15,7 +15,7 @@ #include #include "esp_sleep.h" #include "ulp_riscv.h" -#include "ulp_riscv_adc.h" +#include "ulp_adc.h" #include "ulp_main.h" #include "ulp/example_config.h" @@ -56,14 +56,15 @@ void app_main(void) static void init_ulp_program(void) { - ulp_riscv_adc_cfg_t cfg = { - .adc_n = EXAMPLE_ADC_UNIT, - .channel = EXAMPLE_ADC_CHANNEL, - .width = EXAMPLE_ADC_WIDTH, - .atten = EXAMPLE_ADC_ATTEN, + ulp_adc_cfg_t cfg = { + .adc_n = EXAMPLE_ADC_UNIT, + .channel = EXAMPLE_ADC_CHANNEL, + .width = EXAMPLE_ADC_WIDTH, + .atten = EXAMPLE_ADC_ATTEN, + .ulp_mode = ADC_ULP_MODE_RISCV, }; - ESP_ERROR_CHECK(ulp_riscv_adc_init(&cfg)); + ESP_ERROR_CHECK(ulp_adc_init(&cfg)); esp_err_t err = ulp_riscv_load_binary(ulp_main_bin_start, (ulp_main_bin_end - ulp_main_bin_start)); ESP_ERROR_CHECK(err); diff --git a/examples/system/ulp_riscv/i2c/CMakeLists.txt b/examples/system/ulp_riscv/i2c/CMakeLists.txt new file mode 100644 index 0000000000..d186d07abc --- /dev/null +++ b/examples/system/ulp_riscv/i2c/CMakeLists.txt @@ -0,0 +1,6 @@ +# The following lines of boilerplate have to be in your project's CMakeLists +# in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(ulp-riscv-rtc-i2c-example) diff --git a/examples/system/ulp_riscv/i2c/README.md b/examples/system/ulp_riscv/i2c/README.md new file mode 100644 index 0000000000..11ba448c06 --- /dev/null +++ b/examples/system/ulp_riscv/i2c/README.md @@ -0,0 +1,76 @@ +| Supported Targets | ESP32-S2 | ESP32-S3 | +| ----------------- | -------- | -------- | + +# ULP RISC-V I2C Example + +This example demonstrates how to use the RTC I2C peripheral from the ULP RISC-V coprocessor in deep sleep. + +The ULP program is based on the BMP180 Temperature and Pressure sensor (https://cz.mouser.com/datasheet/2/783/BST-BMP180-DS000-1509579.pdf) which has an I2C interface. The main CPU initializes the RTC I2C peripheral, the BMP180 sensor and loads the ULP program. It then goes into deep sleep. + +The ULP program periodically measures the temperature and pressure values from the BMP180 sensor and wakesup the main CPU when the values are above a certain thershold. +### Hardware Required + +* A development board with a SOC which has a RISC-V ULP coprocessor (e.g., ESP32-S2 Saola) +* A BMP180 sensor module +* A USB cable for power supply and programming + +## Example output + +Below is the output from this example. + +``` +Not a ULP-RISC V wakeup (cause = 0) +Initializing RTC I2C ... +RTC_I2C_STATUS_REG = 0x00000000 +Reading calibration data from BMP180 ... +ac1 = 7819 +ac2 = -1152 +ac3 = -14317 +ac4 = 34252 +ac5 = 25122 +ac6 = 14289 +b1 = 6515 +b2 = 44 +mb = -32768 +mc = -11786 +md = 2746 + +Reading initial uncompensated temperature and pressure data ... +Uncompensated Temperature = 22865 +Uncompensated Pressure = 41768 + +Real Temperature = 24.900000 deg celcius +Real Pressure = 990.640000 hPa + +Entering in deep sleep + +ESP-ROM:esp32s2-rc4-20191025 +Build:Oct 25 2019 +rst:0x5 (DSLEEP),boot:0x9 (SPI_FAST_FLASH_BOOT) +SPIWP:0xee +mode:DIO, clock div:1 +load:0x3ffe6108,len:0x1298 +load:0x4004c000,len:0x92c +load:0x40050000,len:0x2f04 +entry 0x4004c154 +W (76) spi_flash: Detected size(4096k) larger than the size in the binary image header(2048k). Using the size in the binary image header. +ULP RISC-V woke up the main CPU +Uncompensated Temperature = 22865 +Uncompensated Pressure = 41765 +Reading calibration data from BMP180 ... +ac1 = 7819 +ac2 = -1152 +ac3 = -14317 +ac4 = 34252 +ac5 = 25122 +ac6 = 14289 +b1 = 6515 +b2 = 44 +mb = -32768 +mc = -11786 +md = 2746 + +New Real Temperature = 24.900000 deg celcius +New Real Pressure = 990.550000 hPa +Entering in deep sleep +``` diff --git a/examples/system/ulp_riscv/i2c/main/CMakeLists.txt b/examples/system/ulp_riscv/i2c/main/CMakeLists.txt new file mode 100644 index 0000000000..1f929ff573 --- /dev/null +++ b/examples/system/ulp_riscv/i2c/main/CMakeLists.txt @@ -0,0 +1,25 @@ +idf_component_register(SRCS "ulp_riscv_rtc_i2c_example_main.c" + INCLUDE_DIRS "" + REQUIRES soc ulp) +target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") + +# +# ULP support additions to component CMakeLists.txt. +# +# 1. The ULP app name must be unique (if multiple components use ULP). +set(ulp_app_name ulp_${COMPONENT_NAME}) +# +# 2. Specify all C and Assembly source files. +# Files should be placed into a separate directory (in this case, ulp/), +# which should not be added to COMPONENT_SRCS. +set(ulp_riscv_sources "ulp/main.c") + +# +# 3. List all the component source files which include automatically +# generated ULP export file, ${ulp_app_name}.h: +set(ulp_exp_dep_srcs "ulp_riscv_rtc_i2c_example_main.c") + +# +# 4. Call function to build ULP binary and embed in project using the argument +# values above. +ulp_embed_binary(${ulp_app_name} "${ulp_riscv_sources}" "${ulp_exp_dep_srcs}") diff --git a/examples/system/ulp_riscv/i2c/main/bmp180_defs.h b/examples/system/ulp_riscv/i2c/main/bmp180_defs.h new file mode 100644 index 0000000000..d8ae173e92 --- /dev/null +++ b/examples/system/ulp_riscv/i2c/main/bmp180_defs.h @@ -0,0 +1,110 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#pragma once + +/*************************************************** + * BMP180 Register Addresses + ***************************************************/ +#define BMP180_SENSOR_I2C_ADDR 0x77 +#define BMP180_SENSOR_REG_ADDR_WHO_AM_I 0xD0 +#define BMP180_SENSOR_REG_ADDR_SOFT_RESET 0xE0 +#define BMP180_SENSOR_REG_ADDR_AC1_MSB 0xAA +#define BMP180_SENSOR_REG_ADDR_AC1_LSB 0xAB +#define BMP180_SENSOR_REG_ADDR_AC2_MSB 0xAC +#define BMP180_SENSOR_REG_ADDR_AC2_LSB 0xAD +#define BMP180_SENSOR_REG_ADDR_AC3_MSB 0xAE +#define BMP180_SENSOR_REG_ADDR_AC3_LSB 0xAF +#define BMP180_SENSOR_REG_ADDR_AC4_MSB 0xB0 +#define BMP180_SENSOR_REG_ADDR_AC4_LSB 0xB1 +#define BMP180_SENSOR_REG_ADDR_AC5_MSB 0xB2 +#define BMP180_SENSOR_REG_ADDR_AC5_LSB 0xB3 +#define BMP180_SENSOR_REG_ADDR_AC6_MSB 0xB4 +#define BMP180_SENSOR_REG_ADDR_AC6_LSB 0xB5 +#define BMP180_SENSOR_REG_ADDR_B1_MSB 0xB6 +#define BMP180_SENSOR_REG_ADDR_B1_LSB 0xB7 +#define BMP180_SENSOR_REG_ADDR_B2_MSB 0xB8 +#define BMP180_SENSOR_REG_ADDR_B2_LSB 0xB9 +#define BMP180_SENSOR_REG_ADDR_MB_MSB 0xBA +#define BMP180_SENSOR_REG_ADDR_MB_LSB 0xBB +#define BMP180_SENSOR_REG_ADDR_MC_MSB 0xBC +#define BMP180_SENSOR_REG_ADDR_MC_LSB 0xBD +#define BMP180_SENSOR_REG_ADDR_MD_MSB 0xBE +#define BMP180_SENSOR_REG_ADDR_MD_LSB 0xBF +#define BMP180_SENSOR_REG_ADDR_CTRL_REG 0xF4 +#define BMP180_SENSOR_REG_ADDR_SENSOR_DATA_MSB 0xF6 +#define BMP180_SENSOR_REG_ADDR_SENSOR_DATA_LSB 0xF7 +#define BMP180_SENSOR_REG_ADDR_SENSOR_DATA_XLSB 0xF8 + +/*************************************************** + * BMP180 Control Commands + ***************************************************/ +#define BMP180_SENSOR_CMD_READ_TEMPERATURE 0x2E +#define BMP180_SENSOR_CMD_READ_PRESSURE_OSS_0 0x34 +#define BMP180_SENSOR_CMD_READ_PRESSURE_OSS_1 0x74 +#define BMP180_SENSOR_CMD_READ_PRESSURE_OSS_2 0xB4 +#define BMP180_SENSOR_CMD_READ_PRESSURE_OSS_3 0xF4 +#define BMP180_SENSOR_CMD_SOFT_RESET 0xB6 + +/*************************************************** + * BMP180 Chip ID + ***************************************************/ +#define BMP180_SENSOR_CHIP_ID 0x55 + +/*************************************************** + * BMP180 Calibration Data + ***************************************************/ +typedef struct { + int16_t ac1; + int16_t ac2; + int16_t ac3; + uint16_t ac4; + uint16_t ac5; + uint16_t ac6; + int16_t b1; + int16_t b2; + int16_t mb; + int16_t mc; + int16_t md; +} bmp180_cal_data_t; + +bmp180_cal_data_t bmp180_cal_data; + +/*************************************************** + * BMP180 Oversampling setting to measure pressure + ***************************************************/ +typedef enum { + OSS_0 = 0, // Ultra low power + OSS_1 = 1, // Standard + OSS_2 = 2, // High resolution + OSS_3 = 3 // Ultra high resolution +} oss_mode_t; + +/*************************************************** + * BMP180 Interaction APIs + ***************************************************/ +static void bmp180_read_cal_data(void); // Read cal data +static void bmp180_read_ut_data(int16_t *ut_data); // Read uncompensated temperature +static void bmp180_read_up_data(int32_t *up_data, oss_mode_t oss_mode); // Read uncompensated pressure + +/************************************************ + * BMP180 Utility APIs + ************************************************/ +static void bmp180_read16(uint16_t *data_out, uint32_t reg_msb, uint32_t reg_lsb); +static int32_t bmp180_calculate_real_temp(int32_t ut_data); +static int32_t bmp180_calculate_real_pressure(int32_t up_data, int32_t ut_data, oss_mode_t oss_mode); + +/************************************************ + * Pressure measurement mode + ************************************************/ +#define EXAMPLE_OSS_MODE OSS_0 + +/************************************************ + * Temperature and Pressure thresholds (uncompensated) to wake up Main CPU + * The threshold values have been selected for demp purposes and may not + * represent real world use case. + ************************************************/ +#define EXAMPLE_UT_THRESHOLD 20000 +#define EXAMPLE_UP_THRESHOLD 40000 diff --git a/examples/system/ulp_riscv/i2c/main/ulp/main.c b/examples/system/ulp_riscv/i2c/main/ulp/main.c new file mode 100644 index 0000000000..ba545ac6ea --- /dev/null +++ b/examples/system/ulp_riscv/i2c/main/ulp/main.c @@ -0,0 +1,126 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +/* ULP RISC-V RTC I2C example + + This example code is in the Public Domain (or CC0 licensed, at your option.) + + Unless required by applicable law or agreed to in writing, this + software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + CONDITIONS OF ANY KIND, either express or implied. + + This code runs on ULP RISC-V coprocessor +*/ + +#include +#include "ulp_riscv.h" +#include "ulp_riscv_utils.h" +#include "ulp_riscv_i2c_ulp_core.h" +#include "../bmp180_defs.h" + +/************************************************ + * Shared data between main CPU and ULP + ************************************************/ +int16_t ut_data = 0; +int32_t up_data = 0; +int32_t ut_threshold = EXAMPLE_UT_THRESHOLD; +int32_t up_threshold = EXAMPLE_UP_THRESHOLD; +oss_mode_t oss_mode = EXAMPLE_OSS_MODE; + +int main (void) +{ + /* Read uncompensated temperature */ + bmp180_read_ut_data(&ut_data); + + /* Read uncompensated pressure */ + bmp180_read_up_data(&up_data, oss_mode); + + /* Wakeup the main CPU if either the uncompensated temperature or uncompensated pressure values + * are more than their respective threshold values. + */ + if ((ut_data > ut_threshold) || (up_data > up_threshold)) { + ulp_riscv_wakeup_main_processor(); + } + + return 0; +} + +static void bmp180_read16(uint16_t *data_out, uint32_t reg_msb, uint32_t reg_lsb) +{ + uint8_t data_rd = 0; + *data_out = 0; + + ulp_riscv_i2c_master_set_slave_reg_addr(reg_msb); + ulp_riscv_i2c_master_read_from_device(&data_rd, 1); + *data_out |= (uint16_t)(data_rd << 8); + ulp_riscv_i2c_master_set_slave_reg_addr(reg_lsb); + data_rd = 0; + ulp_riscv_i2c_master_read_from_device(&data_rd, 1); + *data_out |= (uint16_t)(data_rd); +} + +static void bmp180_read_ut_data(int16_t *ut_data) +{ + /* Set slave register address to the control register */ + ulp_riscv_i2c_master_set_slave_reg_addr(BMP180_SENSOR_REG_ADDR_CTRL_REG); + + /* Setup control register to read temperature */ + uint8_t cmd = BMP180_SENSOR_CMD_READ_TEMPERATURE; + ulp_riscv_i2c_master_write_to_device(&cmd, 1); + + /* Wait at least 4.5 milliseconds for the sensor to complete the reading */ + ulp_riscv_delay_cycles(5 * ULP_RISCV_CYCLES_PER_US * 1000); + + /* Read uncompensated temperature data */ + bmp180_read16((uint16_t *)ut_data, BMP180_SENSOR_REG_ADDR_SENSOR_DATA_MSB, BMP180_SENSOR_REG_ADDR_SENSOR_DATA_LSB); +} + +static void bmp180_read_up_data(int32_t *up_data, oss_mode_t oss_mode) +{ + uint16_t press_high; + uint8_t press_low; + + /* Set slave register address to the control register */ + ulp_riscv_i2c_master_set_slave_reg_addr(BMP180_SENSOR_REG_ADDR_CTRL_REG); + + /* Setup control register to read pressure */ + uint8_t cmd = 0; + uint8_t wait = 0; + switch(oss_mode) + { + case OSS_0: + cmd = BMP180_SENSOR_CMD_READ_PRESSURE_OSS_0; + wait = 5; // Wait atleast 4.5 msec + break; + case OSS_1: + cmd = BMP180_SENSOR_CMD_READ_PRESSURE_OSS_1; + wait = 8; // Wait atleast 7.5 msec + break; + case OSS_2: + cmd = BMP180_SENSOR_CMD_READ_PRESSURE_OSS_2; + wait = 14; // Wait atleast 13.5 msec + break; + case OSS_3: + cmd = BMP180_SENSOR_CMD_READ_PRESSURE_OSS_3; + wait = 26; // Wait atleast 25.5 msec + break; + } + + ulp_riscv_i2c_master_write_to_device(&cmd, 1); + + /* Wait for the required amount of time for the sensor to complete the reading */ + ulp_riscv_delay_cycles(wait * ULP_RISCV_CYCLES_PER_US * 1000); + + /* Read uncompensated temperature data */ + + /* Read MSB + LSB */ + bmp180_read16(&press_high, BMP180_SENSOR_REG_ADDR_SENSOR_DATA_MSB, BMP180_SENSOR_REG_ADDR_SENSOR_DATA_LSB); + + /* Read XLSB */ + ulp_riscv_i2c_master_set_slave_reg_addr(BMP180_SENSOR_REG_ADDR_SENSOR_DATA_XLSB); + ulp_riscv_i2c_master_read_from_device(&press_low, 1); + + *up_data = (((uint32_t)press_high << 8) + (uint32_t)press_low) >> (8 - oss_mode); +} diff --git a/examples/system/ulp_riscv/i2c/main/ulp_riscv_rtc_i2c_example_main.c b/examples/system/ulp_riscv/i2c/main/ulp_riscv_rtc_i2c_example_main.c new file mode 100644 index 0000000000..3cb3ff2307 --- /dev/null +++ b/examples/system/ulp_riscv/i2c/main/ulp_riscv_rtc_i2c_example_main.c @@ -0,0 +1,351 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +/* ULP RISC-V RTC I2C example + + This example code is in the Public Domain (or CC0 licensed, at your option.) + + Unless required by applicable law or agreed to in writing, this + software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + CONDITIONS OF ANY KIND, either express or implied. +*/ + +#include +#include +#include "esp_sleep.h" +#include "ulp_riscv.h" +#include "ulp_riscv_i2c.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "ulp_main.h" +#include "bmp180_defs.h" + +extern const uint8_t ulp_main_bin_start[] asm("_binary_ulp_main_bin_start"); +extern const uint8_t ulp_main_bin_end[] asm("_binary_ulp_main_bin_end"); + +/************************************************ + * ULP utility APIs + ************************************************/ +static void init_ulp_program(void); + +/************************************************ + * RTC I2C utility APIs + ************************************************/ +static void init_i2c(void); + +void app_main(void) +{ + uint8_t data_rd = 0; + int16_t ut_data = 0; + int32_t up_data = 0; + int32_t temperature = 0; + int32_t pressure = 0; + oss_mode_t oss_mode; + + esp_sleep_wakeup_cause_t cause = esp_sleep_get_wakeup_cause(); + + /* Not a wakeup from ULP + * Initialize RTC I2C + * Setup BMP180 sensor + * Store current temperature and pressure values + * Load the ULP firmware + * Go to deep sleep + */ + if (cause != ESP_SLEEP_WAKEUP_ULP) { + printf("Not a ULP-RISC V wakeup (cause = %d)\n", cause); + + /* Initialize RTC I2C */ + init_i2c(); + + /* Configure I2C slave address */ + ulp_riscv_i2c_master_set_slave_addr(BMP180_SENSOR_I2C_ADDR); + + /* Reset the BMP180 sensor*/ + ulp_riscv_i2c_master_set_slave_reg_addr(BMP180_SENSOR_REG_ADDR_SOFT_RESET); + uint8_t data_wr = BMP180_SENSOR_CMD_SOFT_RESET; + ulp_riscv_i2c_master_write_to_device(&data_wr, 1); + + /* Confirm that the sensor is alive + * The BMP180 returns the chip id 0x55 on quering reg addr 0xD0 + */ + ulp_riscv_i2c_master_set_slave_reg_addr(BMP180_SENSOR_REG_ADDR_WHO_AM_I); + ulp_riscv_i2c_master_read_from_device(&data_rd, 1); + if (data_rd != BMP180_SENSOR_CHIP_ID) { + printf("ERROR: Cannot communicate with I2C sensor\n"); + abort(); + } + + /* Read the calibration data */ + printf("Reading calibration data from BMP180 ...\n"); + bmp180_read_cal_data(); + printf("\n"); + + /* Read uncompensated temperature and pressure */ + printf("Reading initial uncompensated temperature and pressure data ...\n"); + ut_data = 0; + up_data = 0; + oss_mode = EXAMPLE_OSS_MODE; + bmp180_read_ut_data(&ut_data); + bmp180_read_up_data(&up_data, oss_mode); + printf("Uncompensated Temperature = %d\n", ut_data); + printf("Uncompensated Pressure = %d\n", up_data); + printf("\n"); + + /* Calculate real temperature value */ + temperature = bmp180_calculate_real_temp((int32_t)ut_data); + printf("Real Temperature = %f deg celcius\n", (float)(temperature/10.0)); + + /* Calculate real pressure value */ + pressure = bmp180_calculate_real_pressure(up_data, (int32_t)ut_data, oss_mode); + printf("Real Pressure = %f hPa\n", pressure / 100.0); + printf("\n"); + + /* Load ULP firmware + * + * The ULP is responsible of monitoring the temperature and pressure values + * periodically. It will wakeup the main CPU if the temperature and pressure + * values are above a certain threshold. + */ + init_ulp_program(); + } + + /* ULP RISC-V read and detected a temperature or pressure above the limit */ + if (cause == ESP_SLEEP_WAKEUP_ULP) { + printf("ULP RISC-V woke up the main CPU\n"); + + /* Pause ULP while we are using the RTC I2C from the main CPU */ + ulp_timer_stop(); + ulp_riscv_halt(); + + printf("Uncompensated Temperature = %d\n", ulp_ut_data); + printf("Uncompensated Pressure = %d\n", ulp_up_data); + + /* Read the calibration data again */ + printf("Reading calibration data from BMP180 ...\n"); + bmp180_read_cal_data(); + printf("\n"); + + /* Calculate real temperature and pressure again */ + temperature = 0; + temperature = bmp180_calculate_real_temp((int32_t)ulp_ut_data); + printf("New Real Temperature = %f deg celcius\n", (float)(temperature/10.0)); + + /* Calculate real pressure value */ + pressure = 0; + pressure = bmp180_calculate_real_pressure(ulp_up_data, (int32_t)ulp_ut_data, oss_mode); + printf("New Real Pressure = %f hPa\n", pressure / 100.0); + + /* Resume ULP and go to deep sleep again */ + ulp_timer_resume(); + } + + + /* Add a delay for everything to the printed before heading in to light sleep */ + vTaskDelay(100); + + /* Go back to sleep, only the ULP RISC-V will run */ + printf("Entering deep sleep\n\n"); + + /* RTC peripheral power domain needs to be kept on to keep RTC I2C related configs during sleep */ + esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON); + + ESP_ERROR_CHECK(esp_sleep_enable_ulp_wakeup()); + + esp_deep_sleep_start(); +} + +static void init_i2c(void) +{ + /* Configure RTC I2C */ + printf("Initializing RTC I2C ...\n"); + ulp_riscv_i2c_cfg_t i2c_cfg = ULP_RISCV_I2C_DEFAULT_CONFIG(); + ulp_riscv_i2c_master_init(&i2c_cfg); +} + +static void bmp180_read16(uint16_t *data_out, uint32_t reg_msb, uint32_t reg_lsb) +{ + uint8_t data_rd = 0; + *data_out = 0; + + ulp_riscv_i2c_master_set_slave_reg_addr(reg_msb); + ulp_riscv_i2c_master_read_from_device(&data_rd, 1); + *data_out |= (uint16_t)(data_rd << 8); + ulp_riscv_i2c_master_set_slave_reg_addr(reg_lsb); + data_rd = 0; + ulp_riscv_i2c_master_read_from_device(&data_rd, 1); + *data_out |= (uint16_t)(data_rd); +} + +static void bmp180_read_cal_data(void) +{ + /* AC1 */ + bmp180_read16((uint16_t *)&bmp180_cal_data.ac1, BMP180_SENSOR_REG_ADDR_AC1_MSB, BMP180_SENSOR_REG_ADDR_AC1_LSB); + printf("ac1 = %d\n", bmp180_cal_data.ac1); + + /* AC2 */ + bmp180_read16((uint16_t *)&bmp180_cal_data.ac2, BMP180_SENSOR_REG_ADDR_AC2_MSB, BMP180_SENSOR_REG_ADDR_AC2_LSB); + printf("ac2 = %d\n", bmp180_cal_data.ac2); + + /* AC3 */ + bmp180_read16((uint16_t *)&bmp180_cal_data.ac3, BMP180_SENSOR_REG_ADDR_AC3_MSB, BMP180_SENSOR_REG_ADDR_AC3_LSB); + printf("ac3 = %d\n", bmp180_cal_data.ac3); + + /* AC4 */ + bmp180_read16(&bmp180_cal_data.ac4, BMP180_SENSOR_REG_ADDR_AC4_MSB, BMP180_SENSOR_REG_ADDR_AC4_LSB); + printf("ac4 = %u\n", bmp180_cal_data.ac4); + + /* AC5 */ + bmp180_read16(&bmp180_cal_data.ac5, BMP180_SENSOR_REG_ADDR_AC5_MSB, BMP180_SENSOR_REG_ADDR_AC5_LSB); + printf("ac5 = %u\n", bmp180_cal_data.ac5); + + /* AC6 */ + bmp180_read16(&bmp180_cal_data.ac6, BMP180_SENSOR_REG_ADDR_AC6_MSB, BMP180_SENSOR_REG_ADDR_AC6_LSB); + printf("ac6 = %u\n", bmp180_cal_data.ac6); + + /* B1 */ + bmp180_read16((uint16_t *)&bmp180_cal_data.b1, BMP180_SENSOR_REG_ADDR_B1_MSB, BMP180_SENSOR_REG_ADDR_B1_LSB); + printf("b1 = %d\n", bmp180_cal_data.b1); + + /* B2 */ + bmp180_read16((uint16_t *)&bmp180_cal_data.b2, BMP180_SENSOR_REG_ADDR_B2_MSB, BMP180_SENSOR_REG_ADDR_B2_LSB); + printf("b2 = %d\n", bmp180_cal_data.b2); + + /* MB */ + bmp180_read16((uint16_t *)&bmp180_cal_data.mb, BMP180_SENSOR_REG_ADDR_MB_MSB, BMP180_SENSOR_REG_ADDR_MB_LSB); + printf("mb = %d\n", bmp180_cal_data.mb); + + /* MC */ + bmp180_read16((uint16_t *)&bmp180_cal_data.mc, BMP180_SENSOR_REG_ADDR_MC_MSB, BMP180_SENSOR_REG_ADDR_MC_LSB); + printf("mc = %d\n", bmp180_cal_data.mc); + + /* MD */ + bmp180_read16((uint16_t *)&bmp180_cal_data.md, BMP180_SENSOR_REG_ADDR_MD_MSB, BMP180_SENSOR_REG_ADDR_MD_LSB); + printf("md = %d\n", bmp180_cal_data.md); +} + +static void bmp180_read_ut_data(int16_t *ut_data) +{ + /* Set slave register address to the control register */ + ulp_riscv_i2c_master_set_slave_reg_addr(BMP180_SENSOR_REG_ADDR_CTRL_REG); + + /* Setup control register to read temperature */ + uint8_t cmd = BMP180_SENSOR_CMD_READ_TEMPERATURE; + ulp_riscv_i2c_master_write_to_device(&cmd, 1); + + /* Wait at least 4.5 milliseconds for the sensor to complete the reading */ + vTaskDelay(pdMS_TO_TICKS(5)); + + /* Read uncompensated temperature data */ + bmp180_read16((uint16_t *)ut_data, BMP180_SENSOR_REG_ADDR_SENSOR_DATA_MSB, BMP180_SENSOR_REG_ADDR_SENSOR_DATA_LSB); +} + +static int32_t computeb5(int32_t ut_data) +{ + int32_t x1 = (ut_data - (int32_t)bmp180_cal_data.ac6) * ((int32_t)bmp180_cal_data.ac5) >> 15; + int32_t x2 = ((int32_t)bmp180_cal_data.mc << 11) / (x1 + (int32_t)bmp180_cal_data.md); + return x1 + x2; +} + +static int32_t bmp180_calculate_real_temp(int32_t ut_data) +{ + int32_t b5 = computeb5(ut_data); + int32_t t = (b5 + 8) >> 4; + + return t; +} + +static void bmp180_read_up_data(int32_t *up_data, oss_mode_t oss_mode) +{ + uint16_t press_high; + uint8_t press_low; + + /* Set slave register address to the control register */ + ulp_riscv_i2c_master_set_slave_reg_addr(BMP180_SENSOR_REG_ADDR_CTRL_REG); + + /* Setup control register to read pressure */ + uint8_t cmd = 0; + uint8_t wait = 0; + switch(oss_mode) + { + case OSS_0: + cmd = BMP180_SENSOR_CMD_READ_PRESSURE_OSS_0; + wait = 5; // Wait atleast 4.5 msec + break; + case OSS_1: + cmd = BMP180_SENSOR_CMD_READ_PRESSURE_OSS_1; + wait = 8; // Wait atleast 7.5 msec + break; + case OSS_2: + cmd = BMP180_SENSOR_CMD_READ_PRESSURE_OSS_2; + wait = 14; // Wait atleast 13.5 msec + break; + case OSS_3: + cmd = BMP180_SENSOR_CMD_READ_PRESSURE_OSS_3; + wait = 26; // Wait atleast 25.5 msec + break; + } + + ulp_riscv_i2c_master_write_to_device(&cmd, 1); + + /* Wait for the required amount of time for the sensor to complete the reading */ + vTaskDelay(pdMS_TO_TICKS(wait)); + + /* Read uncompensated temperature data */ + + /* Read MSB + LSB */ + bmp180_read16(&press_high, BMP180_SENSOR_REG_ADDR_SENSOR_DATA_MSB, BMP180_SENSOR_REG_ADDR_SENSOR_DATA_LSB); + + /* Read XLSB */ + ulp_riscv_i2c_master_set_slave_reg_addr(BMP180_SENSOR_REG_ADDR_SENSOR_DATA_XLSB); + ulp_riscv_i2c_master_read_from_device(&press_low, 1); + + *up_data = (((uint32_t)press_high << 8) + (uint32_t)press_low) >> (8 - oss_mode); +} + +static int32_t bmp180_calculate_real_pressure(int32_t up_data, int32_t ut_data, oss_mode_t oss_mode) +{ + int32_t p, x1, x2, x3, b3, b5, b6; + uint32_t b4, b7; + + b5 = computeb5(ut_data); + b6 = b5 - 4000; + x1 = (bmp180_cal_data.b2 * ((b6 * b6) >> 12)) >> 11; + x2 = (bmp180_cal_data.ac2 * b6) >> 11; + x3 = x1 + x2; + b3 = (((((int32_t) bmp180_cal_data.ac1) * 4 + x3) << oss_mode) + 2) >> 2; + x1 = (bmp180_cal_data.ac3 * b6) >> 13; + x2 = (bmp180_cal_data.b1 * ((b6 * b6) >> 12)) >> 16; + x3 = ((x1 + x2) + 2) >> 2; + b4 = (bmp180_cal_data.ac4 * (uint32_t) (x3 + 32768)) >> 15; + b7 = ((uint32_t) (up_data - b3) * (50000 >> oss_mode)); + + if (b7 < 0x80000000) { + p = (b7 << 1) / b4; + } else { + p = (b7 / b4) << 1; + } + + x1 = (p >> 8) * (p >> 8); + x1 = (x1 * 3038) >> 16; + x2 = (-7357 * p) >> 16; + p = p + ((x1 + x2 + 3791) >> 4); + + return p; +} + +static void init_ulp_program(void) +{ + esp_err_t err = ulp_riscv_load_binary(ulp_main_bin_start, (ulp_main_bin_end - ulp_main_bin_start)); + ESP_ERROR_CHECK(err); + + /* The first argument is the period index, which is not used by the ULP-RISC-V timer + * The second argument is the period in microseconds, which gives a wakeup time period of: 20ms + */ + ulp_set_wakeup_period(0, 20000); + + /* Start the program */ + err = ulp_riscv_run(); + ESP_ERROR_CHECK(err); +} diff --git a/examples/system/ulp_riscv/i2c/sdkconfig.defaults b/examples/system/ulp_riscv/i2c/sdkconfig.defaults new file mode 100644 index 0000000000..a28f71162e --- /dev/null +++ b/examples/system/ulp_riscv/i2c/sdkconfig.defaults @@ -0,0 +1,9 @@ +# Enable ULP +CONFIG_ULP_COPROC_ENABLED=y +CONFIG_ULP_COPROC_RISCV=y +CONFIG_ULP_COPROC_RESERVE_MEM=4096 +# Set log level to Warning to produce clean output +CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y +CONFIG_BOOTLOADER_LOG_LEVEL=2 +CONFIG_LOG_DEFAULT_LEVEL_WARN=y +CONFIG_LOG_DEFAULT_LEVEL=2 diff --git a/examples/system/xip_from_psram/CMakeLists.txt b/examples/system/xip_from_psram/CMakeLists.txt new file mode 100644 index 0000000000..2fab110f0a --- /dev/null +++ b/examples/system/xip_from_psram/CMakeLists.txt @@ -0,0 +1,8 @@ +# For more information about build system see +# https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/build-system.html +# The following five lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(xip_from_psram) diff --git a/examples/system/xip_from_psram/README.md b/examples/system/xip_from_psram/README.md new file mode 100644 index 0000000000..5afc68ebd2 --- /dev/null +++ b/examples/system/xip_from_psram/README.md @@ -0,0 +1,112 @@ +| Supported Targets | ESP32-S2 | ESP32-S3 | +| ----------------- | -------- | -------- | + +# XIP (Execute-In-Place) From PSRAM Example + +This example illustrates a typical usage of XIP (Execute-In-Place) From PSRAM. With this feature: +- You can optimize internal RAM usage +- System can avoid disabling the Cache during an SPI1 Flash operation. + +## Overview + +Here we define two sets of operations related to external memory: +SET1: Operations where CPU fetches data and instructions from external memory. +SET2: `ESP Flash` driver operations and other operations from drivers based on `ESP Flash` (NVS, Partition drivers, etc.). + +By default, during `SET2` operations, concurrent access requests to the Flash and PSRAM (`SET1` operations) will be disabled otherwise both the `SET1` and `SET2` operations are not guaranteed to be safe (this is an undefined behaviour). + +Only ISRs in internal RAM will get executed during `SET2` operations. Besides, if any functions or data are accessed in these ISRs (usually this happens in ISR callbacks), they need to be placed into internal RAM as well. For interrupt handlers which need to execute when the cache is disabled (e.g., for low latency operations), you need to set the ESP_INTR_FLAG_IRAM flag when the interrupt handler is registered. + +When **CONFIG_SPIRAM_FETCH_INSTRUCTIONS** and **CONFIG_SPIRAM_RODATA** are both enabled, the `flash.text` sections (for instructions) and the `.rodata` section (read only data) will be moved to PSRAM. Corresponding virtual memory range will be re-mapped to PSRAM. Under this condition, ESP-IDF won't disable concurrent accesses to external memory (`SET1` operations) anymore. + +By using this feature, during `SET2` operations, placement of ISRs, ISR callbacks, and related data are no longer limited to internal RAM. + +## Example Process + +To show this feature, in this example we go through the following steps: + +`General Steps`: +1. Create a partition for Flash Erase Operation +2. Create an esp_timer in one-shot mode + +`PSRAM Steps`: +3. Do a Flash erase operation, and start the timer +4. ESP-Timer callback is dispatched and it calls a function in PSRAM during the flash erase operation +5. The Flash erase operation finishes +6. Show the result about the callback(in PSRAM) response and execute time + +`IRAM Steps`: +7. Do a Flash erase operation, and start the timer +8. ESP-Timer callback is dispatched and it calls a function in IRAM during the flash erase operation +9. The flash erase operation finishes +10. Show the result about the callback(in IRAM) response and execute time + +### Timeline + +Initialization and config -> Flash erase start -> ESP-Timer callback(in PSRAM) appear -> Flash erase finish -> Flash erase start -> ESP-Timer callback(in IRAM) appear -> Flash erase finish + + ISR CPU + | | + | | + | | + | * <----flash operation starts + | * + callback starts * --------> * + (in PSRAM) * * + callback finishes * <-------- * + | * + | * + | * <----flash operation finishes + | | + | | + | | + | | + | | + | | + | * <----flash operation starts + | * + callback starts * --------> * + (in IRAM) * * + callback finishes * <-------- * + | * + | * + | * <----flash operation finishes + | | + | | + +## Example Result + +The ISR which call a function in IRAM happening during Flash erase operations. CPU fetches instructions and data from internal RAM. +The ISR which call a function in PSRAM happening during Flash erase operations and its response time is longer than calling a function in IRAM. That's because fetching instructions from PSRAM takes more time than fetching from IRAM. + +## Configure the project + +Open the project configuration menu (`idf.py menuconfig`). + +1. Set the `Partition Table -> Custom partition table CSV` to `y`. +2. Set the `Component config -> High resolution timer -> Support ISR dispatch method` to `y`. +3. Set the `Component config -> ESP PSRAM -> SPI RAM config` to `y` then set `Cache fetch instructions from SPI RAM` and `Cache load read only data from SPI RAM` to `y`. + + +## Build and Flash + +Run `idf.py -p PORT flash monitor` to build and flash the project.. + +(To exit the serial monitor, type ``Ctrl-]``.) + +See the [Getting Started Guide](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/index.html) for full steps to configure and use ESP-IDF to build projects. + +## Example Output + +``` +I (742) esp_psram: Reserving pool of 32K of internal memory for DMA/internal allocations +I (742) example: found partition 'storage1' at offset 0x110000 with size 0x10000 + +I (1152) example: callback(in PSRAM) response time: 7 us +I (1362) example: callback(in IRAM) response time: 5 us + +``` + +## Troubleshooting + +For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon. diff --git a/examples/system/xip_from_psram/main/CMakeLists.txt b/examples/system/xip_from_psram/main/CMakeLists.txt new file mode 100644 index 0000000000..298ffae6d6 --- /dev/null +++ b/examples/system/xip_from_psram/main/CMakeLists.txt @@ -0,0 +1,2 @@ +idf_component_register(SRCS "xip_from_psram_example_main.c" + INCLUDE_DIRS ".") diff --git a/examples/system/xip_from_psram/main/xip_from_psram_example_main.c b/examples/system/xip_from_psram/main/xip_from_psram_example_main.c new file mode 100644 index 0000000000..a9c9639c42 --- /dev/null +++ b/examples/system/xip_from_psram/main/xip_from_psram_example_main.c @@ -0,0 +1,95 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include +#include +#include +#include "sdkconfig.h" +#include "esp_log.h" +#include "esp_cpu.h" +#include "esp_err.h" +#include "esp_partition.h" +#include "esp_flash.h" +#include "esp_timer.h" + +static void oneshot_timer_callback(void* arg); +static void cb_in_psram(void); +static void cb_in_iram(void); +static const esp_partition_t *s_get_partition(void); + +static int time_cb_start; //Time when ISR callback start +static int time_cb_end; //Time when ISR callback end + +const static char *TAG = "example"; + +void app_main(void) +{ + bool instructions_in_psram = true; //Flags to indicate where the instructions in + + esp_timer_handle_t oneshot_timer; + const esp_timer_create_args_t oneshot_timer_args = { + .callback = &oneshot_timer_callback, + .arg = &instructions_in_psram, + .dispatch_method = ESP_TIMER_ISR, + .name = "one-shot" + }; + ESP_ERROR_CHECK(esp_timer_create(&oneshot_timer_args, &oneshot_timer)); + + const esp_partition_t *part = s_get_partition(); + ESP_LOGI(TAG, "found partition '%s' at offset 0x%"PRIx32" with size 0x%"PRIx32, part->label, part->address, part->size); + ESP_ERROR_CHECK(esp_flash_erase_region(part->flash_chip, part->address, part->size)); + + ESP_ERROR_CHECK(esp_timer_start_once(oneshot_timer, 1 * 10 * 1000)); + ESP_ERROR_CHECK(esp_flash_erase_region(part->flash_chip, part->address, part->size)); + + ESP_LOGI(TAG, "callback(in PSRAM) response time: %d us", time_cb_end - time_cb_start); + + instructions_in_psram = false; + + ESP_ERROR_CHECK(esp_timer_start_once(oneshot_timer, 1 * 10 * 1000)); + ESP_ERROR_CHECK(esp_flash_erase_region(part->flash_chip, part->address, part->size)); + + ESP_LOGI(TAG, "callback(in IRAM) response time: %d us", time_cb_end - time_cb_start); + + ESP_ERROR_CHECK(esp_timer_delete(oneshot_timer)); +} + +static IRAM_ATTR void NOINLINE_ATTR oneshot_timer_callback(void* arg) +{ + bool in_psram = (bool*) arg; + time_cb_start = esp_timer_get_time(); + if (in_psram == true) { + cb_in_psram(); + } else { + cb_in_iram(); + } +} + +static IRAM_ATTR NOINLINE_ATTR void cb_in_iram(void) +{ + for (int i = 0; i < 100; i++) { + asm volatile("nop"); + } + time_cb_end = esp_timer_get_time(); +} + +static NOINLINE_ATTR void cb_in_psram(void) +{ + for (int i = 0; i < 100; i++) { + asm volatile("nop"); + } + time_cb_end = esp_timer_get_time(); +} + +static const esp_partition_t *s_get_partition(void) +{ + //Find the "storage1" partition defined in `partitions.csv` + const esp_partition_t *result = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, "storage1"); + if (!result) { + ESP_LOGE(TAG, "Can't find the partition, please define it correctly in `partitions.csv`"); + abort(); + } + return result; +} diff --git a/examples/system/xip_from_psram/partitions.csv b/examples/system/xip_from_psram/partitions.csv new file mode 100644 index 0000000000..34c6c64f04 --- /dev/null +++ b/examples/system/xip_from_psram/partitions.csv @@ -0,0 +1,6 @@ +# Name, Type, SubType, Offset, Size, Flags +# Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap +nvs, data, nvs, 0x9000, 0x6000, +phy_init, data, phy, 0xf000, 0x1000, +factory, app, factory, 0x10000, 1M, +storage1, data, fat, , 64K, diff --git a/examples/system/xip_from_psram/pytest_xip_from_psram.py b/examples/system/xip_from_psram/pytest_xip_from_psram.py new file mode 100644 index 0000000000..9af84289d6 --- /dev/null +++ b/examples/system/xip_from_psram/pytest_xip_from_psram.py @@ -0,0 +1,49 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +import pytest +from pytest_embedded.dut import Dut + + +@pytest.mark.esp32s2 +@pytest.mark.esp32s3 +@pytest.mark.generic +# in order to build the default sdkconfig(the CI won't build the sdkconfig.defaults if there is a sdkconfig.ci.xx) +@pytest.mark.parametrize( + 'config', + [ + 'generic', + ], + indirect=True, +) +def test_xip_from_psram_example_generic(dut: Dut) -> None: + dut.expect_exact('found partition') + + res = dut.expect(r'callback\(in PSRAM\) response time: (\d{1,3}) us') + response_time = res.group(1).decode('utf8') + assert float(response_time) <= 12 + + res = dut.expect(r'callback\(in IRAM\) response time: (\d{1,3}) us') + response_time = res.group(1).decode('utf8') + assert float(response_time) <= 12 + + +@pytest.mark.esp32s3 +@pytest.mark.MSPI_F4R8 +@pytest.mark.parametrize( + 'config', + [ + 'esp32s3_f4r8', + ], + indirect=True, +) +def test_xip_from_psram_example_f4r8(dut: Dut) -> None: + dut.expect_exact('found partition') + + res = dut.expect(r'callback\(in PSRAM\) response time: (\d{1,3}) us') + response_time = res.group(1).decode('utf8') + assert float(response_time) <= 12 + + res = dut.expect(r'callback\(in IRAM\) response time: (\d{1,3}) us') + response_time = res.group(1).decode('utf8') + assert float(response_time) <= 12 diff --git a/examples/system/xip_from_psram/sdkconfig.ci.esp32s3_f4r8 b/examples/system/xip_from_psram/sdkconfig.ci.esp32s3_f4r8 new file mode 100644 index 0000000000..f1e352e8e0 --- /dev/null +++ b/examples/system/xip_from_psram/sdkconfig.ci.esp32s3_f4r8 @@ -0,0 +1 @@ +CONFIG_SPIRAM_MODE_OCT=y diff --git a/examples/system/xip_from_psram/sdkconfig.ci.generic b/examples/system/xip_from_psram/sdkconfig.ci.generic new file mode 100644 index 0000000000..e69de29bb2 diff --git a/examples/system/xip_from_psram/sdkconfig.defaults b/examples/system/xip_from_psram/sdkconfig.defaults new file mode 100644 index 0000000000..1fd37b3537 --- /dev/null +++ b/examples/system/xip_from_psram/sdkconfig.defaults @@ -0,0 +1,7 @@ +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions.csv" +CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD=y +CONFIG_SPIRAM=y +CONFIG_SPIRAM_FETCH_INSTRUCTIONS=y +CONFIG_SPIRAM_RODATA=y diff --git a/examples/wifi/README.md b/examples/wifi/README.md index f40ecfa8b2..5ebd696853 100644 --- a/examples/wifi/README.md +++ b/examples/wifi/README.md @@ -7,7 +7,7 @@ This directory contains a range of examples ESP-IDF projects. These are intended The examples are grouped into sub-directories by category. Each category directory contains one or more example projects: * `espnow` is the connectionless Wi-Fi communication protocol. -* `fast_scan` shows how to use fast scan while connecting to an AP.. +* `fast_scan` shows how to use fast scan while connecting to an AP. * `ftm` is a how to use FTM (Fine Timing Measurement) feature to calculate distance between devices. * `getting_started` contains the basic examples for using Wi-Fi in STA and AP mode. * `iperf` shows the common performance measurements for two ESP running this example. @@ -15,8 +15,9 @@ The examples are grouped into sub-directories by category. Each category directo * `roaming` contains a example using 802.11k and 802.11v APIs. * `scan` shows how to scan for all the available APs. * `smart_config` shows how ESP connects to a target AP with ESPTOUCH. +* `wifi_eap_fast` shows how ESP connects to AP with Wi-Fi enterprise encryption using the EAP-FAST method. * `wifi_easy_connect` shows how to configure an ESP device as an enrollee using Device Provisioning Protocol (DPP). -* `wpa2_enterprise` connects to AP with WPA2 enterprise encryption. +* `wpa2_enterprise` shows how ESP connects to AP with WPA2 enterprise encryption. * `wps` contains a how to use the Wi-Fi Protected Setup protocol. # More diff --git a/examples/wifi/espnow/main/espnow_example_main.c b/examples/wifi/espnow/main/espnow_example_main.c index 8975e4d76a..7031a35021 100644 --- a/examples/wifi/espnow/main/espnow_example_main.c +++ b/examples/wifi/espnow/main/espnow_example_main.c @@ -51,6 +51,7 @@ static void example_wifi_init(void) ESP_ERROR_CHECK( esp_wifi_set_storage(WIFI_STORAGE_RAM) ); ESP_ERROR_CHECK( esp_wifi_set_mode(ESPNOW_WIFI_MODE) ); ESP_ERROR_CHECK( esp_wifi_start()); + ESP_ERROR_CHECK( esp_wifi_set_channel(CONFIG_ESPNOW_CHANNEL, WIFI_SECOND_CHAN_NONE)); #if CONFIG_ESPNOW_ENABLE_LONG_RANGE ESP_ERROR_CHECK( esp_wifi_set_protocol(ESPNOW_WIFI_IF, WIFI_PROTOCOL_11B|WIFI_PROTOCOL_11G|WIFI_PROTOCOL_11N|WIFI_PROTOCOL_LR) ); diff --git a/examples/wifi/iperf/iperf_test.py b/examples/wifi/iperf/iperf_test.py index f95716bfde..a2a83899b0 100644 --- a/examples/wifi/iperf/iperf_test.py +++ b/examples/wifi/iperf/iperf_test.py @@ -19,13 +19,10 @@ The test env Example_ShieldBox do need the following config:: apc_ip: "192.168.1.88" pc_nic: "eth0" """ -from __future__ import division, unicode_literals - import os import re import subprocess import time -from builtins import range, str import ttfw_idf from idf_iperf_test_util import Attenuator, IperfUtility, PowerControl, TestReport diff --git a/examples/zigbee/light_sample/light_bulb/CMakeLists.txt b/examples/zigbee/light_sample/light_bulb/CMakeLists.txt index 1302519c20..3c60c93069 100644 --- a/examples/zigbee/light_sample/light_bulb/CMakeLists.txt +++ b/examples/zigbee/light_sample/light_bulb/CMakeLists.txt @@ -1,8 +1,6 @@ # The following lines of boilerplate have to be in your project's CMakeLists # in this exact order for cmake to work correctly cmake_minimum_required(VERSION 3.16) -set(EXTRA_COMPONENT_DIRS - $ENV{IDF_PATH}/examples/common_components/led_strip - ) + include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(light_bulb) diff --git a/examples/zigbee/light_sample/light_bulb/main/idf_component.yml b/examples/zigbee/light_sample/light_bulb/main/idf_component.yml index b13132f298..92103ca698 100644 --- a/examples/zigbee/light_sample/light_bulb/main/idf_component.yml +++ b/examples/zigbee/light_sample/light_bulb/main/idf_component.yml @@ -1,6 +1,7 @@ ## IDF Component Manager Manifest File dependencies: espressif/esp-zboss-lib: "~0.0.4" + espressif/led_strip: "~2.0.0" ## Required IDF version idf: version: ">=5.0.0" diff --git a/examples/zigbee/light_sample/light_bulb/main/light_driver.c b/examples/zigbee/light_sample/light_bulb/main/light_driver.c index 9d6413eaea..aea5651c61 100644 --- a/examples/zigbee/light_sample/light_bulb/main/light_driver.c +++ b/examples/zigbee/light_sample/light_bulb/main/light_driver.c @@ -53,6 +53,9 @@ void light_driver_init(bool power) .max_leds = CONFIG_EXAMPLE_STRIP_LED_NUMBER, .strip_gpio_num = CONFIG_EXAMPLE_STRIP_LED_GPIO, }; - ESP_ERROR_CHECK(led_strip_new_rmt_device(&led_strip_conf, &s_led_strip)); + led_strip_rmt_config_t rmt_conf = { + .resolution_hz = 10 * 1000 * 1000, // 10MHz + }; + ESP_ERROR_CHECK(led_strip_new_rmt_device(&led_strip_conf, &rmt_conf, &s_led_strip)); light_driver_set_power(power); } diff --git a/export.fish b/export.fish index b112b61e07..905d3a4cd8 100644 --- a/export.fish +++ b/export.fish @@ -1,20 +1,17 @@ # This script should be sourced, not executed. -# `idf_tools.py export --unset` create statement, with keyword unset, but fish shell support only `set --erase variable` +# `idf_tools.py export --deactivate` create statement, with keyword unset, but fish shell support only `set --erase variable` function unset set --erase $argv end function __main + set script_dir (dirname (realpath (status -f))) if not set -q IDF_PATH - set -gx IDF_PATH (cd (dirname (status -f)); and pwd) + set -gx IDF_PATH $script_dir echo "Setting IDF_PATH to '$IDF_PATH'" end - set script_dir (cd (dirname (status -f)); and pwd) - if test "$script_dir" = "." - set script_dir $pwd - end if test "$IDF_PATH" != "$script_dir" # Change IDF_PATH is important when there are 2 ESP-IDF versions in different directories. # Sourcing this script without change, would cause sourcing wrong export script. @@ -31,8 +28,8 @@ function __main "$ESP_PYTHON" "$IDF_PATH"/tools/python_version_checker.py echo "Checking other ESP-IDF version." - set idf_unset ("$ESP_PYTHON" "$IDF_PATH"/tools/idf_tools.py export --unset) || return 1 - eval "$idf_unset" + set idf_deactivate ("$ESP_PYTHON" "$IDF_PATH"/tools/idf_tools.py export --deactivate) || return 1 + eval "$idf_deactivate" echo "Adding ESP-IDF tools to PATH..." # Call idf_tools.py to export tool paths @@ -50,7 +47,7 @@ function __main set -x PATH "$IDF_ADD_PATHS_EXTRAS":"$PATH" echo "Checking if Python packages are up to date..." - python "$IDF_PATH"/tools/idf_tools.py check-python-dependencies || return 1 + "$ESP_PYTHON" "$IDF_PATH"/tools/idf_tools.py check-python-dependencies || return 1 set added_path_variables for entry in $PATH; @@ -88,7 +85,7 @@ function __main set -e ESP_PYTHON set -e uninstall set -e script_dir - set -e idf_unset + set -e idf_deactivate # Not unsetting IDF_PYTHON_ENV_PATH, it can be used by IDF build system diff --git a/export.ps1 b/export.ps1 index 1843c81376..3ddbe32a0f 100644 --- a/export.ps1 +++ b/export.ps1 @@ -1,18 +1,18 @@ #!/usr/bin/env pwsh $S = [IO.Path]::PathSeparator # path separator. WIN:';', UNIX:":" -$IDF_PATH = $PSScriptRoot +$IDF_PATH = "$PSScriptRoot" Write-Output "Setting IDF_PATH: $IDF_PATH" -$env:IDF_PATH = $IDF_PATH +$env:IDF_PATH = "$IDF_PATH" Write-Output "Checking Python compatibility" -python $IDF_PATH/tools/python_version_checker.py +python "$IDF_PATH/tools/python_version_checker.py" Write-Output "Adding ESP-IDF tools to PATH..." $OLD_PATH = $env:PATH.split($S) | Select-Object -Unique # array without duplicates # using idf_tools.py to get $envars_array to set -$envars_raw = python $IDF_PATH/tools/idf_tools.py export --format key-value +$envars_raw = python "$IDF_PATH/tools/idf_tools.py" export --format key-value if ($LASTEXITCODE -ne 0) { exit $LASTEXITCODE } # if error $envars_array = @() # will be filled like: @@ -75,7 +75,7 @@ Write-Output "Checking if Python packages are up to date..." Start-Process -Wait -NoNewWindow -FilePath "python" -Args "`"$IDF_PATH/tools/idf_tools.py`" check-python-dependencies" if ($LASTEXITCODE -ne 0) { exit $LASTEXITCODE } # if error -$uninstall = python $IDF_PATH/tools/idf_tools.py uninstall --dry-run +$uninstall = python "$IDF_PATH/tools/idf_tools.py" uninstall --dry-run if (![string]::IsNullOrEmpty($uninstall)){ Write-Output "" diff --git a/export.sh b/export.sh index 9eefa41549..2db9f123e4 100644 --- a/export.sh +++ b/export.sh @@ -116,8 +116,8 @@ __main() { "$ESP_PYTHON" "${IDF_PATH}/tools/python_version_checker.py" __verbose "Checking other ESP-IDF version." - idf_unset=$("$ESP_PYTHON" "${IDF_PATH}/tools/idf_tools.py" export --unset) || return 1 - eval "${idf_unset}" + idf_deactivate=$("$ESP_PYTHON" "${IDF_PATH}/tools/idf_tools.py" export --deactivate) || return 1 + eval "${idf_deactivate}" __verbose "Adding ESP-IDF tools to PATH..." # Call idf_tools.py to export tool paths @@ -134,9 +134,8 @@ __main() { eval "${idf_exports}" export PATH="${IDF_ADD_PATHS_EXTRAS}:${PATH}" - __verbose "Using Python interpreter in $(which python)" __verbose "Checking if Python packages are up to date..." - python "${IDF_PATH}/tools/idf_tools.py" check-python-dependencies || return 1 + "$ESP_PYTHON" "${IDF_PATH}/tools/idf_tools.py" check-python-dependencies || return 1 if [ -n "$BASH" ] then @@ -184,7 +183,7 @@ __cleanup() { unset path_entry unset IDF_ADD_PATHS_EXTRAS unset idf_exports - unset idf_unset + unset idf_deactivate unset ESP_PYTHON unset SOURCE_ZSH unset SOURCE_BASH diff --git a/install.ps1 b/install.ps1 index 8460c26d61..7f9c3c63b9 100644 --- a/install.ps1 +++ b/install.ps1 @@ -4,14 +4,14 @@ $IDF_PATH = $PSScriptRoot $TARGETS = (python "$IDF_PATH/tools/install_util.py" extract targets "$args") Write-Output "Installing ESP-IDF tools" -$proces_tools = Start-Process -Wait -PassThru -NoNewWindow -FilePath "python" -Args "$IDF_PATH/tools/idf_tools.py install --targets=${TARGETS}" +$proces_tools = Start-Process -Wait -PassThru -NoNewWindow -FilePath "python" -Args "`"$IDF_PATH/tools/idf_tools.py`" install --targets=${TARGETS}" $exit_code_tools = $proces_tools.ExitCode if ($exit_code_tools -ne 0) { exit $exit_code_tools } # if error $FEATURES = (python "$IDF_PATH/tools/install_util.py" extract features "$args") Write-Output "Setting up Python environment" -$proces_py_env = Start-Process -Wait -PassThru -NoNewWindow -FilePath "python" -Args "$IDF_PATH/tools/idf_tools.py install-python-env --features=${FEATURES}" +$proces_py_env = Start-Process -Wait -PassThru -NoNewWindow -FilePath "python" -Args "`"$IDF_PATH/tools/idf_tools.py`" install-python-env --features=${FEATURES}" $exit_code_py_env = $proces_py_env.ExitCode if ($exit_code_py_env -ne 0) { exit $exit_code_py_env } # if error diff --git a/pytest.ini b/pytest.ini index 2433ce2571..587da2f348 100644 --- a/pytest.ini +++ b/pytest.ini @@ -37,10 +37,12 @@ markers = quad_psram: runners with quad psram octal_psram: runners with octal psram usb_host: usb host runners + usb_device: usb device runners ethernet_ota: ethernet OTA runners flash_encryption: Flash Encryption runners flash_encryption_f4r8: Flash Encryption runners with 4-line flash and 8-line psram flash_encryption_f8r8: Flash Encryption runners with 8-line flash and 8-line psram + flash_mutli: Multiple flash chips tests psram: Chip has 4-line psram ir_transceiver: runners with a pair of IR transmitter and receiver flash_encryption_wifi_high_traffic: Flash Encryption runners with wifi high traffic support @@ -59,9 +61,13 @@ markers = MSPI_F8R8: runner with Octal Flash and Octal PSRAM MSPI_F4R8: runner with Quad Flash and Octal PSRAM MSPI_F4R4: runner with Quad Flash and Quad PSRAM + test_jtag_arm: runner where the chip is accessible through JTAG as well + adc: ADC related tests should run on adc runners # multi-dut markers + i154_multi_dut: tests should be used for i154, such as openthread. multi_dut_generic: tests should be run on generic runners, at least have two duts connected. + generic_multi_device: generic multiple devices whose corresponding gpio pins are connected to each other. # host_test markers host_test: tests which shouldn not be built at the build stage, and instead built in host_test stage. diff --git a/tools/ci/build_template_app.sh b/tools/ci/build_template_app.sh index b79d94fa28..274c87675e 100755 --- a/tools/ci/build_template_app.sh +++ b/tools/ci/build_template_app.sh @@ -62,7 +62,7 @@ build_stage2() { --build-log ${BUILD_LOG_CMAKE} \ --size-file size.json \ --collect-size-info size_info.txt \ - --default-build-targets esp32,esp32s2,esp32s3,esp32c2,esp32c3 # add esp32h2 back after IDF-5541 + --default-build-targets esp32,esp32s2,esp32s3,esp32c2,esp32c3,esp32c6 # add esp32h2 back after IDF-5541 } build_stage1() { @@ -76,7 +76,7 @@ build_stage1() { --build-log ${BUILD_LOG_CMAKE} \ --size-file size.json \ --collect-size-info size_info.txt \ - --default-build-targets esp32,esp32s2,esp32s3,esp32c2,esp32c3,esp32h2 + --default-build-targets esp32,esp32s2,esp32s3,esp32c2,esp32c3,esp32h2,esp32c6 } # Default arguments diff --git a/tools/ci/check_build_test_rules.py b/tools/ci/check_build_test_rules.py index 2a9c242aa7..0d5fd02a81 100755 --- a/tools/ci/check_build_test_rules.py +++ b/tools/ci/check_build_test_rules.py @@ -12,6 +12,7 @@ from io import StringIO from pathlib import Path from typing import Dict, List, Optional, Tuple +import yaml from idf_ci_utils import IDF_PATH, get_pytest_cases, get_ttfw_cases YES = u'\u2713' @@ -30,6 +31,7 @@ USUAL_TO_FORMAL = { 'esp32c3': 'ESP32-C3', 'esp32h2': 'ESP32-H2', 'esp32c2': 'ESP32-C2', + 'esp32c6': 'ESP32-C6', 'linux': 'Linux', } @@ -40,6 +42,7 @@ FORMAL_TO_USUAL = { 'ESP32-C3': 'esp32c3', 'ESP32-H2': 'esp32h2', 'ESP32-C2': 'esp32c2', + 'ESP32-C6': 'esp32c6', 'Linux': 'linux', } @@ -51,7 +54,11 @@ def doublequote(s: str) -> str: return f'"{s}"' -def check_readme(paths: List[str]) -> None: +def check_readme( + paths: List[str], + exclude_dirs: Optional[List[str]] = None, + extra_default_build_targets: Optional[List[str]] = None, +) -> None: from idf_build_apps import App, find_apps from idf_build_apps.constants import SUPPORTED_TARGETS @@ -136,9 +143,11 @@ def check_readme(paths: List[str]) -> None: paths, 'all', recursive=True, + exclude_list=exclude_dirs or [], manifest_files=[ str(p) for p in Path(IDF_PATH).glob('**/.build-test-rules.yml') ], + default_build_targets=SUPPORTED_TARGETS + extra_default_build_targets, ) ) exit_code = 0 @@ -196,7 +205,11 @@ def check_readme(paths: List[str]) -> None: sys.exit(exit_code) -def check_test_scripts(paths: List[str]) -> None: +def check_test_scripts( + paths: List[str], + exclude_dirs: Optional[List[str]] = None, + bypass_check_test_targets: Optional[List[str]] = None, +) -> None: from idf_build_apps import App, find_apps # takes long time, run only in CI @@ -242,7 +255,7 @@ def check_test_scripts(paths: List[str]) -> None: actual_extra_tested_targets = set(actual_verified_targets) - set( _app.verified_targets ) - if actual_extra_tested_targets: + if actual_extra_tested_targets - set(bypass_check_test_targets or []): print( inspect.cleandoc( f''' @@ -303,6 +316,7 @@ def check_test_scripts(paths: List[str]) -> None: paths, 'all', recursive=True, + exclude_list=exclude_dirs or [], manifest_files=[ str(p) for p in Path(IDF_PATH).glob('**/.build-test-rules.yml') ], @@ -397,9 +411,21 @@ if __name__ == '__main__': _check_readme = action.add_parser('check-readmes') _check_readme.add_argument('paths', nargs='+', help='check under paths') + _check_readme.add_argument( + '-c', + '--config', + default=os.path.join(IDF_PATH, '.gitlab', 'ci', 'default-build-test-rules.yml'), + help='default build test rules config file', + ) _check_test_scripts = action.add_parser('check-test-scripts') _check_test_scripts.add_argument('paths', nargs='+', help='check under paths') + _check_test_scripts.add_argument( + '-c', + '--config', + default=os.path.join(IDF_PATH, '.gitlab', 'ci', 'default-build-test-rules.yml'), + help='default build test rules config file', + ) _sort_yaml = action.add_parser('sort-yaml') _sort_yaml.add_argument('files', nargs='+', help='all specified yaml files') @@ -407,19 +433,60 @@ if __name__ == '__main__': arg = parser.parse_args() # Since this script is executed from the pre-commit hook environment, make sure IDF_PATH is set - os.environ['IDF_PATH'] = os.path.realpath(os.path.join(os.path.dirname(__file__), '..', '..')) + os.environ['IDF_PATH'] = os.path.realpath( + os.path.join(os.path.dirname(__file__), '..', '..') + ) if arg.action == 'sort-yaml': sort_yaml(arg.files) else: check_dirs = set() - for path in arg.paths: - if os.path.isfile(path): - check_dirs.add(os.path.dirname(path)) + + # check if *_caps.h files changed + check_all = False + soc_caps_header_files = list( + (Path(IDF_PATH) / 'components' / 'soc').glob('**/*_caps.h') + ) + for p in arg.paths: + if Path(p).resolve() in soc_caps_header_files: + check_all = True + break + + if os.path.isfile(p): + check_dirs.add(os.path.dirname(p)) else: - check_dirs.add(path) + check_dirs.add(p) + + if check_all: + check_dirs = {IDF_PATH} + _exclude_dirs = [os.path.join(IDF_PATH, 'tools', 'unit-test-app'), + os.path.join(IDF_PATH, 'tools', 'test_build_system', 'build_test_app')] + else: + _exclude_dirs = [] + + extra_default_build_targets: List[str] = [] + bypass_check_test_targets: List[str] = [] + if arg.config: + with open(arg.config) as fr: + configs = yaml.safe_load(fr) + + if configs: + extra_default_build_targets = ( + configs.get('extra_default_build_targets') or [] + ) + bypass_check_test_targets = ( + configs.get('bypass_check_test_targets') or [] + ) if arg.action == 'check-readmes': - check_readme(list(check_dirs)) + check_readme( + list(check_dirs), + exclude_dirs=_exclude_dirs, + extra_default_build_targets=extra_default_build_targets, + ) elif arg.action == 'check-test-scripts': - check_test_scripts(list(check_dirs)) + check_test_scripts( + list(check_dirs), + exclude_dirs=_exclude_dirs, + bypass_check_test_targets=bypass_check_test_targets, + ) diff --git a/tools/ci/check_build_warnings.py b/tools/ci/check_build_warnings.py deleted file mode 100755 index 7e6eafd3fa..0000000000 --- a/tools/ci/check_build_warnings.py +++ /dev/null @@ -1,110 +0,0 @@ -#!/usr/bin/env python -# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD -# SPDX-License-Identifier: Apache-2.0 -# coding=utf-8 -# -# CI script to check build logs for warnings. -# Reads the list of builds, in the format produced by find_apps.py or build_apps.py, and finds warnings in the -# log files for every build. -# Exits with a non-zero exit code if any warning is found. - -import argparse -import logging -import os -import re -import sys - -try: - from find_build_apps import BuildItem, setup_logging -except ImportError: - sys.path.insert(0, os.path.join(os.path.dirname(__file__), '..')) - from find_build_apps import BuildItem, setup_logging - -WARNING_REGEX = re.compile(r'(?:error|warning)[^\w]', re.MULTILINE | re.IGNORECASE) - -IGNORE_WARNS = [ - re.compile(r_str) for r_str in [ - r'library/error\.o', - r'/.*error\S*\.o', - r'.*error.*\.c\.obj', - r'.*error.*\.c', - r'.*error.*\.cpp\.obj', - r'.*error.*\.cxx\.obj', - r'.*error.*\.cc\.obj', - r'-Werror', - r'error\.d', - r'/.*error\S*.d', - r'reassigning to symbol', - r'changes choice state', - r'crosstool_version_check\.cmake', - r'CryptographyDeprecationWarning', - r'Warning: \d+/\d+ app partitions are too small for binary', - ] -] - - -def line_has_warnings(line): # type: (str) -> bool - if not WARNING_REGEX.search(line): - return False - - has_warnings = True - for ignored in IGNORE_WARNS: - if re.search(ignored, line): - has_warnings = False - break - - return has_warnings - - -def main(): # type: () -> None - parser = argparse.ArgumentParser(description='ESP-IDF app builder') - parser.add_argument( - '-v', - '--verbose', - action='count', - help='Increase the logging level of the script. Can be specified multiple times.', - ) - parser.add_argument( - '--log-file', - type=argparse.FileType('w'), - help='Write the script log to the specified file, instead of stderr', - ) - parser.add_argument( - 'build_list', - type=argparse.FileType('r'), - nargs='?', - default=sys.stdin, - help='Name of the file to read the list of builds from. If not specified, read from stdin.', - ) - args = parser.parse_args() - setup_logging(args) - - build_items = [BuildItem.from_json(line) for line in args.build_list] - if not build_items: - logging.warning('Empty build list') - SystemExit(0) - - found_warnings = 0 - for build_item in build_items: - if not build_item.build_log_path: - logging.debug('No log file for {}'.format(build_item.work_dir)) - continue - with open(build_item.build_log_path, 'r') as log_file: - for line_no, line in enumerate(log_file): - if line_has_warnings(line): - logging.error('Issue in app {}, config {}:'.format(build_item.app_dir, build_item.config_name)) - logging.error(line.rstrip('\n')) - logging.error('See {}:{} for details'.format(os.path.basename(build_item.build_log_path), - line_no + 1)) - found_warnings += 1 - break - - if found_warnings: - logging.error('Checked {} builds, found {} warnings'.format(len(build_items), found_warnings)) - raise SystemExit(1) - - logging.info('No warnings found') - - -if __name__ == '__main__': - main() diff --git a/tools/ci/check_copyright_config.yaml b/tools/ci/check_copyright_config.yaml index bb99c7d0b6..df7774885b 100644 --- a/tools/ci/check_copyright_config.yaml +++ b/tools/ci/check_copyright_config.yaml @@ -132,6 +132,13 @@ argtable3: - BSD-3-Clause - Apache-2.0 +md5_hash: + include: + - 'components/esp_rom/include/**/rom/md5_hash.h' + allowed_licenses: + - BSD-3-Clause + - Apache-2.0 + xtensa: include: - 'components/xtensa/**' @@ -143,7 +150,9 @@ tinyusb: - 'examples/peripherals/usb/device/tusb_midi/' allowed_licenses: - Apache-2.0 - - MIT + - MIT # Example derived from TinyUSB code by HaThach + - Unlicense + - CC0-1.0 # files matching this section do not perform the check # file patterns starting with ! are negated, meaning files matching them won't match the section. diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index bdaaa3d546..6417146d57 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -398,25 +398,6 @@ components/bt/host/bluedroid/stack/smp/smp_main.c components/bt/host/bluedroid/stack/smp/smp_utils.c components/console/linenoise/linenoise.c components/console/linenoise/linenoise.h -components/esp32/include/rom/aes.h -components/esp32/include/rom/bigint.h -components/esp32/include/rom/cache.h -components/esp32/include/rom/crc.h -components/esp32/include/rom/efuse.h -components/esp32/include/rom/ets_sys.h -components/esp32/include/rom/gpio.h -components/esp32/include/rom/libc_stubs.h -components/esp32/include/rom/lldesc.h -components/esp32/include/rom/md5_hash.h -components/esp32/include/rom/miniz.h -components/esp32/include/rom/queue.h -components/esp32/include/rom/rtc.h -components/esp32/include/rom/secure_boot.h -components/esp32/include/rom/sha.h -components/esp32/include/rom/spi_flash.h -components/esp32/include/rom/tbconsole.h -components/esp32/include/rom/tjpgd.h -components/esp32/include/rom/uart.h components/esp_eth/src/dm9051.h components/esp_eth/src/ksz8851.h components/esp_eth/src/openeth.h @@ -460,8 +441,6 @@ components/esp_local_ctrl/src/esp_local_ctrl_handler.c components/esp_local_ctrl/src/esp_local_ctrl_priv.h components/esp_local_ctrl/src/esp_local_ctrl_transport_ble.c components/esp_netif/include/esp_netif_ppp.h -components/esp_netif/include/esp_netif_slip.h -components/esp_netif/lwip/esp_netif_lwip_slip.h components/esp_netif/private_include/esp_netif_private.h components/esp_netif/test/test_esp_netif.c components/esp_netif/test_apps/component_ut_test.py @@ -473,7 +452,6 @@ components/esp_pm/include/esp_private/pm_impl.h components/esp_pm/include/esp_private/pm_trace.h components/esp_pm/pm_locks.c components/esp_pm/test/test_pm.c -components/esp_rom/esp32/esp_rom_caps.h components/esp_rom/esp32/ld/esp32.rom.api.ld components/esp_rom/esp32/ld/esp32.rom.eco3.ld components/esp_rom/esp32/ld/esp32.rom.ld @@ -499,7 +477,6 @@ components/esp_rom/esp32h2/ld/esp32h2.rom.libgcc.ld components/esp_rom/esp32h2/ld/esp32h2.rom.newlib-nano.ld components/esp_rom/esp32h2/ld/esp32h2.rom.newlib.ld components/esp_rom/esp32h2/ld/esp32h2.rom.version.ld -components/esp_rom/esp32s2/esp_rom_caps.h components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld components/esp_rom/esp32s2/ld/esp32s2.rom.ld components/esp_rom/esp32s2/ld/esp32s2.rom.libgcc.ld @@ -519,13 +496,11 @@ components/esp_rom/include/esp32/rom/bigint.h components/esp_rom/include/esp32/rom/crc.h components/esp_rom/include/esp32/rom/efuse.h components/esp_rom/include/esp32/rom/libc_stubs.h -components/esp_rom/include/esp32/rom/md5_hash.h components/esp_rom/include/esp32/rom/miniz.h components/esp_rom/include/esp32/rom/rsa_pss.h components/esp_rom/include/esp32/rom/sha.h components/esp_rom/include/esp32/rom/tbconsole.h components/esp_rom/include/esp32/rom/tjpgd.h -components/esp_rom/include/esp32c2/rom/md5_hash.h components/esp_rom/include/esp32c3/rom/aes.h components/esp_rom/include/esp32c3/rom/bigint.h components/esp_rom/include/esp32c3/rom/cache.h @@ -536,7 +511,6 @@ components/esp_rom/include/esp32c3/rom/ets_sys.h components/esp_rom/include/esp32c3/rom/gpio.h components/esp_rom/include/esp32c3/rom/hmac.h components/esp_rom/include/esp32c3/rom/libc_stubs.h -components/esp_rom/include/esp32c3/rom/md5_hash.h components/esp_rom/include/esp32c3/rom/miniz.h components/esp_rom/include/esp32c3/rom/rom_layout.h components/esp_rom/include/esp32c3/rom/rsa_pss.h @@ -554,7 +528,6 @@ components/esp_rom/include/esp32h2/rom/esp_flash.h components/esp_rom/include/esp32h2/rom/ets_sys.h components/esp_rom/include/esp32h2/rom/hmac.h components/esp_rom/include/esp32h2/rom/libc_stubs.h -components/esp_rom/include/esp32h2/rom/md5_hash.h components/esp_rom/include/esp32h2/rom/miniz.h components/esp_rom/include/esp32h2/rom/rsa_pss.h components/esp_rom/include/esp32h2/rom/sha.h @@ -569,7 +542,6 @@ components/esp_rom/include/esp32s2/rom/ets_sys.h components/esp_rom/include/esp32s2/rom/gpio.h components/esp_rom/include/esp32s2/rom/hmac.h components/esp_rom/include/esp32s2/rom/libc_stubs.h -components/esp_rom/include/esp32s2/rom/md5_hash.h components/esp_rom/include/esp32s2/rom/miniz.h components/esp_rom/include/esp32s2/rom/opi_flash.h components/esp_rom/include/esp32s2/rom/rsa_pss.h @@ -595,7 +567,6 @@ components/esp_rom/include/esp32s3/rom/ets_sys.h components/esp_rom/include/esp32s3/rom/gpio.h components/esp_rom/include/esp32s3/rom/hmac.h components/esp_rom/include/esp32s3/rom/libc_stubs.h -components/esp_rom/include/esp32s3/rom/md5_hash.h components/esp_rom/include/esp32s3/rom/miniz.h components/esp_rom/include/esp32s3/rom/opi_flash.h components/esp_rom/include/esp32s3/rom/rom_layout.h @@ -641,7 +612,6 @@ components/esp_system/include/esp_freertos_hooks.h components/esp_system/include/esp_int_wdt.h components/esp_system/include/esp_private/dbg_stubs.h components/esp_system/include/esp_private/panic_internal.h -components/esp_system/include/esp_private/system_internal.h components/esp_system/include/esp_task.h components/esp_system/port/arch/riscv/expression_with_stack.c components/esp_system/port/arch/xtensa/expression_with_stack.c @@ -679,7 +649,6 @@ components/esp_wifi/src/smartconfig.c components/esp_wifi/test/test_wifi_init.c components/fatfs/diskio/diskio.c components/fatfs/diskio/diskio_impl.h -components/fatfs/diskio/diskio_rawflash.c components/fatfs/diskio/diskio_rawflash.h components/fatfs/diskio/diskio_wl.h components/fatfs/port/freertos/ffsystem.c @@ -727,47 +696,38 @@ components/hal/esp32/include/hal/aes_ll.h components/hal/esp32/include/hal/can_hal.h components/hal/esp32/include/hal/can_types.h components/hal/esp32/include/hal/mpu_ll.h -components/hal/esp32/include/hal/rtc_io_ll.h components/hal/esp32/include/hal/rwdt_ll.h components/hal/esp32/include/hal/spi_flash_encrypted_ll.h components/hal/esp32/include/hal/touch_sensor_hal.h components/hal/esp32/include/hal/trace_ll.h -components/hal/esp32/include/hal/uart_ll.h components/hal/esp32c3/hmac_hal.c -components/hal/esp32c3/include/hal/aes_ll.h components/hal/esp32c3/include/hal/ds_ll.h components/hal/esp32c3/include/hal/hmac_hal.h components/hal/esp32c3/include/hal/hmac_ll.h components/hal/esp32c3/include/hal/mpu_ll.h -components/hal/esp32c3/include/hal/rtc_cntl_ll.h components/hal/esp32c3/include/hal/sha_ll.h components/hal/esp32c3/include/hal/spi_flash_encrypted_ll.h components/hal/esp32c3/include/hal/uhci_ll.h components/hal/esp32c3/include/hal/usb_serial_jtag_ll.h components/hal/esp32c3/rtc_cntl_hal.c components/hal/esp32h2/hmac_hal.c -components/hal/esp32h2/include/hal/aes_ll.h components/hal/esp32h2/include/hal/ds_ll.h components/hal/esp32h2/include/hal/hmac_hal.h components/hal/esp32h2/include/hal/hmac_ll.h components/hal/esp32h2/include/hal/mpu_ll.h -components/hal/esp32h2/include/hal/rtc_cntl_ll.h components/hal/esp32h2/include/hal/sha_ll.h components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h components/hal/esp32h2/include/hal/uhci_ll.h components/hal/esp32h2/include/hal/uhci_types.h components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h -components/hal/esp32s2/include/hal/aes_ll.h components/hal/esp32s2/include/hal/crypto_dma_ll.h components/hal/esp32s2/include/hal/dac_hal.h components/hal/esp32s2/include/hal/dedic_gpio_ll.h components/hal/esp32s2/include/hal/mpu_ll.h -components/hal/esp32s2/include/hal/rtc_io_ll.h components/hal/esp32s2/include/hal/sha_ll.h components/hal/esp32s2/include/hal/spi_flash_encrypted_ll.h components/hal/esp32s2/include/hal/trace_ll.h components/hal/esp32s2/include/hal/usb_ll.h -components/hal/esp32s3/include/hal/aes_ll.h components/hal/esp32s3/include/hal/mpu_ll.h components/hal/esp32s3/include/hal/rwdt_ll.h components/hal/esp32s3/include/hal/sha_ll.h @@ -784,7 +744,6 @@ components/hal/include/hal/esp_flash_err.h components/hal/include/hal/mpu_hal.h components/hal/include/hal/mpu_types.h components/hal/include/hal/rtc_io_types.h -components/hal/include/hal/sdio_slave_hal.h components/hal/include/hal/sdio_slave_ll.h components/hal/include/hal/sha_hal.h components/hal/include/hal/spi_flash_encrypt_hal.h @@ -794,7 +753,6 @@ components/hal/include/hal/twai_types.h components/hal/include/hal/uhci_types.h components/hal/include/hal/usb_hal.h components/hal/include/hal/usb_types_private.h -components/hal/include/hal/wdt_hal.h components/hal/include/hal/wdt_types.h components/hal/ledc_hal_iram.c components/hal/mpu_hal.c @@ -963,7 +921,6 @@ components/pthread/test/test_pthread_local_storage.c components/riscv/include/riscv/csr.h components/riscv/include/riscv/encoding.h components/riscv/include/riscv/instruction_decode.h -components/riscv/include/riscv/riscv_interrupts.h components/riscv/include/riscv/rvruntime-frames.h components/riscv/instruction_decode.c components/sdmmc/sdmmc_common.c @@ -1032,7 +989,6 @@ components/soc/esp32/include/soc/uart_struct.h components/soc/esp32/include/soc/uhci_reg.h components/soc/esp32/include/soc/uhci_struct.h components/soc/esp32/include/soc/wdev_reg.h -components/soc/esp32/interrupts.c components/soc/esp32/ledc_periph.c components/soc/esp32/sdio_slave_periph.c components/soc/esp32/sdmmc_periph.c @@ -1051,7 +1007,6 @@ components/soc/esp32c3/include/soc/fe_reg.h components/soc/esp32c3/include/soc/gpio_pins.h components/soc/esp32c3/include/soc/gpio_reg.h components/soc/esp32c3/include/soc/gpio_struct.h -components/soc/esp32c3/include/soc/hwcrypto_reg.h components/soc/esp32c3/include/soc/i2c_reg.h components/soc/esp32c3/include/soc/i2c_struct.h components/soc/esp32c3/include/soc/interrupt_core0_reg.h @@ -1079,7 +1034,6 @@ components/soc/esp32c3/include/soc/usb_serial_jtag_struct.h components/soc/esp32c3/include/soc/wdev_reg.h components/soc/esp32c3/interrupts.c components/soc/esp32c3/ledc_periph.c -components/soc/esp32c3/spi_periph.c components/soc/esp32c3/uart_periph.c components/soc/esp32h2/i2c_periph.c components/soc/esp32h2/include/soc/apb_ctrl_reg.h @@ -1094,7 +1048,6 @@ components/soc/esp32h2/include/soc/efuse_reg.h components/soc/esp32h2/include/soc/efuse_struct.h components/soc/esp32h2/include/soc/extmem_reg.h components/soc/esp32h2/include/soc/fe_reg.h -components/soc/esp32h2/include/soc/hwcrypto_reg.h components/soc/esp32h2/include/soc/interrupt_reg.h components/soc/esp32h2/include/soc/ledc_reg.h components/soc/esp32h2/include/soc/nrx_reg.h @@ -1118,7 +1071,6 @@ components/soc/esp32h2/include/soc/usb_serial_jtag_reg.h components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h components/soc/esp32h2/include/soc/wdev_reg.h components/soc/esp32h2/ledc_periph.c -components/soc/esp32h2/spi_periph.c components/soc/esp32h2/uart_periph.c components/soc/esp32s2/adc_periph.c components/soc/esp32s2/dac_periph.c @@ -1139,7 +1091,6 @@ components/soc/esp32s2/include/soc/fe_reg.h components/soc/esp32s2/include/soc/gpio_pins.h components/soc/esp32s2/include/soc/gpio_reg.h components/soc/esp32s2/include/soc/gpio_sig_map.h -components/soc/esp32s2/include/soc/hwcrypto_reg.h components/soc/esp32s2/include/soc/i2c_reg.h components/soc/esp32s2/include/soc/interrupt_reg.h components/soc/esp32s2/include/soc/ledc_reg.h @@ -1174,9 +1125,7 @@ components/soc/esp32s2/include/soc/usb_wrap_reg.h components/soc/esp32s2/include/soc/usb_wrap_struct.h components/soc/esp32s2/include/soc/usbh_struct.h components/soc/esp32s2/include/soc/wdev_reg.h -components/soc/esp32s2/interrupts.c components/soc/esp32s2/ledc_periph.c -components/soc/esp32s2/spi_periph.c components/soc/esp32s2/uart_periph.c components/soc/esp32s2/usb_periph.c components/soc/esp32s3/dedic_gpio_periph.c @@ -1207,7 +1156,6 @@ components/soc/esp32s3/include/soc/interrupt_core0_reg.h components/soc/esp32s3/include/soc/interrupt_core0_struct.h components/soc/esp32s3/include/soc/interrupt_core1_reg.h components/soc/esp32s3/include/soc/interrupt_core1_struct.h -components/soc/esp32s3/include/soc/interrupt_reg.h components/soc/esp32s3/include/soc/interrupt_struct.h components/soc/esp32s3/include/soc/ledc_reg.h components/soc/esp32s3/include/soc/ledc_struct.h @@ -1258,16 +1206,11 @@ components/soc/esp32s3/include/soc/usb_wrap_reg.h components/soc/esp32s3/include/soc/usb_wrap_struct.h components/soc/esp32s3/include/soc/usbh_struct.h components/soc/esp32s3/include/soc/wdev_reg.h -components/soc/esp32s3/include/soc/world_controller_reg.h -components/soc/esp32s3/interrupts.c components/soc/esp32s3/ledc_periph.c -components/soc/esp32s3/rtc_io_periph.c components/soc/esp32s3/sdio_slave_periph.c components/soc/esp32s3/sdmmc_periph.c -components/soc/esp32s3/spi_periph.c components/soc/esp32s3/uart_periph.c components/soc/esp32s3/usb_periph.c -components/soc/include/soc/adc_periph.h components/soc/include/soc/dac_periph.h components/soc/include/soc/dedic_gpio_periph.h components/soc/include/soc/emac_periph.h @@ -1275,12 +1218,9 @@ components/soc/include/soc/gpio_periph.h components/soc/include/soc/i2c_periph.h components/soc/include/soc/interrupts.h components/soc/include/soc/ledc_periph.h -components/soc/include/soc/rtc_cntl_periph.h -components/soc/include/soc/rtc_periph.h components/soc/include/soc/sdio_slave_periph.h components/soc/include/soc/sdmmc_periph.h components/soc/include/soc/sens_periph.h -components/soc/include/soc/syscon_periph.h components/soc/include/soc/twai_periph.h components/soc/include/soc/uart_periph.h components/soc/include/soc/uhci_periph.h @@ -1312,8 +1252,6 @@ components/spi_flash/test/test_mmap.c components/spi_flash/test/test_out_of_bounds_write.c components/spi_flash/test/test_partition_ext.c components/spi_flash/test/test_spi_flash.c -components/tcp_transport/include/esp_transport_ssl.h -components/tcp_transport/include/esp_transport_tcp.h components/tcp_transport/include/esp_transport_ws.h components/tcp_transport/test/tcp_transport_fixtures.h components/tcp_transport/test/test_transport_basic.c @@ -1321,7 +1259,6 @@ components/tcp_transport/test/test_transport_connect.c components/tcp_transport/test/test_transport_fixtures.c components/tcp_transport/transport_utils.c components/tinyusb/additions/include/tusb_config.h -components/ulp/esp32ulp_mapgen.py components/ulp/test/esp32/test_ulp_as.c components/unity/include/priv/setjmp.h components/unity/include/unity_config.h @@ -1643,7 +1580,6 @@ examples/build_system/cmake/import_prebuilt/main/main.c examples/build_system/cmake/import_prebuilt/prebuilt/components/prebuilt/prebuilt.c examples/build_system/cmake/import_prebuilt/prebuilt/components/prebuilt/prebuilt.h examples/build_system/cmake/import_prebuilt/prebuilt/main/main.c -examples/build_system/cmake/linux_host_app/main/linux_host_app.cpp examples/build_system/cmake/multi_config/main/func.h examples/build_system/cmake/multi_config/main/func_dev.c examples/build_system/cmake/multi_config/main/func_prod.c @@ -1719,7 +1655,6 @@ examples/peripherals/adc/single_read/adc2/main/adc2_example_main.c examples/peripherals/gpio/generic_gpio/example_test.py examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/include/matrix_keyboard.h -examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/src/matrix_keyboard.c examples/peripherals/gpio/matrix_keyboard/main/matrix_keyboard_example_main.c examples/peripherals/i2c/i2c_simple/main/i2c_simple_main.c examples/peripherals/i2c/i2c_tools/example_test.py @@ -1774,7 +1709,6 @@ examples/protocols/http_server/advanced_tests/http_server_advanced_test.py examples/protocols/http_server/advanced_tests/main/include/tests.h examples/protocols/http_server/advanced_tests/main/main.c examples/protocols/http_server/advanced_tests/main/tests.c -examples/protocols/http_server/advanced_tests/scripts/test.py examples/protocols/http_server/captive_portal/example_test.py examples/protocols/http_server/captive_portal/main/dns_server.c examples/protocols/http_server/captive_portal/main/include/dns_server.h @@ -1806,7 +1740,6 @@ examples/protocols/mqtt/ws/main/app_main.c examples/protocols/mqtt/ws/mqtt_ws_example_test.py examples/protocols/mqtt/wss/main/app_main.c examples/protocols/mqtt/wss/mqtt_wss_example_test.py -examples/protocols/slip/slip_udp/components/slip_modem/include/slip_modem.h examples/protocols/slip/slip_udp/main/slip_client_main.c examples/protocols/sntp/example_test.py examples/protocols/sntp/main/sntp_example_main.c diff --git a/tools/ci/check_public_headers_exceptions.txt b/tools/ci/check_public_headers_exceptions.txt index 71b5cd3f5d..a76a5c9368 100644 --- a/tools/ci/check_public_headers_exceptions.txt +++ b/tools/ci/check_public_headers_exceptions.txt @@ -24,9 +24,6 @@ components/esp_rom/include/esp32s2/rom/rsa_pss.h components/esp_common/include/esp_private/ -components/esp32/include/esp32/brownout.h -components/esp32/include/esp32/cache_err_int.h - # LWIP: sockets.h uses #include_next<>, which doesn't work correctly with the checker # memp_std.h is supposed to be included multiple times with different settings components/lwip/lwip/src/include/lwip/priv/memp_std.h @@ -102,22 +99,21 @@ components/esp_hw_support/include/esp_private/esp_memprot_internal.h components/esp_wifi/include/esp_private/wifi_os_adapter.h ### To be fixed: headers that rely on implicit inclusion # +components/esp_rom/include/esp32/rom/rtc.h +components/esp_rom/include/esp32c3/rom/rtc.h +components/esp_rom/include/esp32s2/rom/rtc.h +components/esp_rom/include/esp32s3/rom/rtc.h +components/esp_rom/include/esp32h2/rom/rtc.h +components/esp_rom/include/esp32c2/rom/rtc.h +components/esp_rom/include/esp32c6/rom/rtc.h components/esp_rom/include/esp32/rom/sha.h components/esp_rom/include/esp32/rom/secure_boot.h components/esp_rom/include/esp32c3/rom/spi_flash.h -components/esp_rom/include/esp32c3/rom/rtc.h components/esp_rom/include/esp32s2/rom/spi_flash.h components/esp_rom/include/esp32s2/rom/cache.h components/esp_rom/include/esp32s2/rom/secure_boot.h components/esp_rom/include/esp32s2/rom/opi_flash.h -components/esp_rom/include/esp32s2/rom/rtc.h components/esp_rom/include/esp32s2/rom/efuse.h -components/esp_rom/include/esp32s3/rom/rtc.h -components/esp_rom/include/esp32h2/rom/rtc.h -components/esp_rom/include/esp32c2/rom/rtc.h -components/esp32/include/esp32/dport_access.h -components/esp32/include/rom/sha.h -components/esp32/include/rom/secure_boot.h components/esp_ringbuf/include/freertos/ringbuf.h components/esp_wifi/include/esp_wifi_crypto_types.h components/esp_wifi/include/esp_coexist_internal.h @@ -130,7 +126,6 @@ components/esp_netif/include/esp_netif_sta_list.h components/esp_netif/include/esp_netif_defaults.h components/esp_netif/include/esp_netif_net_stack.h components/esp_netif/include/esp_netif_ppp.h -components/console/linenoise/linenoise.h components/protocomm/include/transports/protocomm_httpd.h components/fatfs/src/diskio.h components/fatfs/diskio/diskio_sdmmc.h @@ -146,14 +141,11 @@ components/usb/include/usb/usb_types_stack.h components/esp_psram/include/esp32/himem.h components/esp_rom/include/esp32/rom/ets_sys.h -components/esp_rom/include/esp32/rom/rtc.h components/esp_rom/include/esp32/rom/uart.h ### To be fixed: files which don't compile for esp32s3 target: -components/soc/esp32s3/include/soc/world_controller_struct.h - ### To be fixed: files which don't compile for esp32c3 target: @@ -162,8 +154,3 @@ components/espcoredump/include/port/xtensa/esp_core_dump_summary_port.h components/riscv/include/esp_private/panic_reason.h components/riscv/include/riscv/interrupt.h components/riscv/include/riscv/rvruntime-frames.h - - -### To be fixed: files which don't compile for esp32c2 target: - -components/efuse/esp32c2/include/esp_efuse_table.h diff --git a/tools/ci/check_readme_links.py b/tools/ci/check_readme_links.py index 80ed216d54..bf33b4a06f 100755 --- a/tools/ci/check_readme_links.py +++ b/tools/ci/check_readme_links.py @@ -18,8 +18,6 @@ from collections import defaultdict, namedtuple from pathlib import Path from typing import List -EXCLUDE_DOCS_LIST = ['examples/peripherals/secure_element/atecc608_ecdsa/components/esp-cryptoauthlib/cryptoauthlib/**'] - # The apple apps links are not accessible from the company network for some reason EXCLUDE_URL_LIST = ['https://apps.apple.com/in/app/esp-ble-provisioning/id1473590141', 'https://apps.apple.com/in/app/esp-softap-provisioning/id1474040630'] @@ -98,10 +96,6 @@ def get_md_links(folder: str) -> List: links = [] for path in (idf_path / folder).rglob('*.md'): - if any([path.relative_to(idf_path).match(exclude_doc) for exclude_doc in EXCLUDE_DOCS_LIST]): - print('{} - excluded'.format(path)) - continue - with path.open(encoding='utf8') as f: content = f.read() diff --git a/tools/ci/check_rules_yml.py b/tools/ci/check_rules_yml.py index 36ebf4e03c..5a55132456 100755 --- a/tools/ci/check_rules_yml.py +++ b/tools/ci/check_rules_yml.py @@ -76,6 +76,10 @@ class YMLConfig: YML_CONFIG = YMLConfig(ROOT_YML_FP) +def get_needed_rules() -> Set[str]: + return deepcopy(YML_CONFIG.all_extends) + + def validate_needed_rules(rules_yml: 'os.PathLike[str]') -> int: res = 0 needed_rules = deepcopy(YML_CONFIG.all_extends) diff --git a/tools/ci/checkout_project_ref.py b/tools/ci/checkout_project_ref.py index 10af27c760..4a987c2eee 100755 --- a/tools/ci/checkout_project_ref.py +++ b/tools/ci/checkout_project_ref.py @@ -10,10 +10,25 @@ import json import os import re import subprocess -from typing import List +from typing import List, Tuple IDF_GIT_DESCRIBE_PATTERN = re.compile(r'^v(\d)\.(\d)') -RETRY_COUNT = 3 + + +def _idf_version_from_cmake() -> Tuple[int, int]: + version_path = os.path.join(os.environ['IDF_PATH'], 'tools/cmake/version.cmake') + regex = re.compile(r'^\s*set\s*\(\s*IDF_VERSION_([A-Z]{5})\s+(\d+)') + try: + ver = {} + with open(version_path) as f: + for line in f: + m = regex.match(line) + if m: + ver[m.group(1)] = m.group(2) + return (int(ver['MAJOR']), int(ver['MINOR'])) + except (KeyError, OSError): + print('WARNING: Cannot find ESP-IDF version in version.cmake') + return (0, 0) def get_customized_project_revision(proj_name: str) -> str: @@ -47,20 +62,12 @@ def target_branch_candidates(proj_name: str) -> List: candidates.insert(0, customized_candidate) # branch name read from IDF - try: - git_describe = subprocess.check_output(['git', 'describe', 'HEAD']) - match = IDF_GIT_DESCRIBE_PATTERN.search(git_describe.decode()) - if match: - major_revision = match.group(1) - minor_revision = match.group(2) - # release branch - candidates.append('release/v{}.{}'.format(major_revision, minor_revision)) - # branch to match all major branches, like v3.x or v3 - candidates.append('release/v{}.x'.format(major_revision)) - candidates.append('release/v{}'.format(major_revision)) - except subprocess.CalledProcessError: - # this should not happen as IDF should have describe message - pass + major_revision, minor_revision = _idf_version_from_cmake() + # release branch + candidates.append('release/v{}.{}'.format(major_revision, minor_revision)) + # branch to match all major branches, like v3.x or v3 + candidates.append('release/v{}.x'.format(major_revision)) + candidates.append('release/v{}'.format(major_revision)) return [c for c in candidates if c] # filter out null value @@ -103,16 +110,10 @@ if __name__ == '__main__': continue if ref_to_use: - for _ in range(RETRY_COUNT): - # Add retry for projects with git-lfs - try: - subprocess.check_call(['git', 'checkout', '-f', ref_to_use], stdout=subprocess.PIPE) # not print the stdout - print('CI using ref {} for project {}'.format(ref_to_use, args.project)) - break - except subprocess.CalledProcessError: - pass - else: - print('Failed to use ref {} for project {}'.format(ref_to_use, args.project)) - exit(1) + try: + subprocess.check_call(['git', 'checkout', '-f', ref_to_use], stdout=subprocess.PIPE) # not print the stdout + print('CI using ref {} for project {}'.format(ref_to_use, args.project)) + except subprocess.CalledProcessError: + pass else: print('using default branch') diff --git a/tools/ci/ci_build_apps.py b/tools/ci/ci_build_apps.py index 8d9a8192f1..e06d8edf18 100644 --- a/tools/ci/ci_build_apps.py +++ b/tools/ci/ci_build_apps.py @@ -10,10 +10,12 @@ import os import sys from collections import defaultdict from pathlib import Path -from typing import List, Set +from typing import List, Optional, Set +import yaml from idf_build_apps import LOGGER, App, build_apps, find_apps, setup_logging -from idf_ci_utils import IDF_PATH, get_pytest_app_paths, get_pytest_cases, get_ttfw_app_paths +from idf_build_apps.constants import SUPPORTED_TARGETS +from idf_ci_utils import IDF_PATH, PytestApp, get_pytest_cases, get_ttfw_app_paths def get_pytest_apps( @@ -22,6 +24,7 @@ def get_pytest_apps( config_rules_str: List[str], marker_expr: str, preserve_all: bool = False, + extra_default_build_targets: Optional[List[str]] = None, ) -> List[App]: pytest_cases = get_pytest_cases(paths, target, marker_expr) @@ -55,9 +58,8 @@ def get_pytest_apps( build_log_path='build_log.txt', size_json_path='size.json', check_warnings=True, - manifest_files=[ - str(p) for p in Path(IDF_PATH).glob('**/.build-test-rules.yml') - ], + manifest_files=[str(p) for p in Path(IDF_PATH).glob('**/.build-test-rules.yml')], + default_build_targets=SUPPORTED_TARGETS + extra_default_build_targets, ) for app in apps: @@ -73,6 +75,7 @@ def get_cmake_apps( target: str, config_rules_str: List[str], preserve_all: bool = False, + extra_default_build_targets: Optional[List[str]] = None, ) -> List[App]: ttfw_app_dirs = get_ttfw_app_paths(paths, target) apps = find_apps( @@ -85,18 +88,17 @@ def get_cmake_apps( size_json_path='size.json', check_warnings=True, preserve=False, - manifest_files=[ - str(p) for p in Path(IDF_PATH).glob('**/.build-test-rules.yml') - ], + manifest_files=[str(p) for p in Path(IDF_PATH).glob('**/.build-test-rules.yml')], + default_build_targets=SUPPORTED_TARGETS + extra_default_build_targets, ) apps_for_build = [] - pytest_app_dirs = get_pytest_app_paths(paths, target) + pytest_cases_apps = [app for case in get_pytest_cases(paths, target) for app in case.apps] for app in apps: if preserve_all or app.app_dir in ttfw_app_dirs: # relpath app.preserve = True - if os.path.realpath(app.app_dir) in pytest_app_dirs: + if PytestApp(os.path.realpath(app.app_dir), app.target, app.config_name) in pytest_cases_apps: LOGGER.debug('Skipping build app with pytest scripts: %s', app) continue @@ -109,14 +111,33 @@ APPS_BUILD_PER_JOB = 30 def main(args: argparse.Namespace) -> None: + extra_default_build_targets: List[str] = [] + if args.default_build_test_rules: + with open(args.default_build_test_rules) as fr: + configs = yaml.safe_load(fr) + + if configs: + extra_default_build_targets = configs.get('extra_default_build_targets') or [] + if args.pytest_apps: LOGGER.info('Only build apps with pytest scripts') apps = get_pytest_apps( - args.paths, args.target, args.config, args.marker_expr, args.preserve_all + args.paths, + args.target, + args.config, + args.marker_expr, + args.preserve_all, + extra_default_build_targets, ) else: LOGGER.info('build apps. will skip pytest apps with pytest scripts') - apps = get_cmake_apps(args.paths, args.target, args.config, args.preserve_all) + apps = get_cmake_apps( + args.paths, + args.target, + args.config, + args.preserve_all, + extra_default_build_targets, + ) LOGGER.info('Found %d apps after filtering', len(apps)) LOGGER.info( @@ -131,10 +152,7 @@ def main(args: argparse.Namespace) -> None: for extra_preserve_dir in args.extra_preserve_dirs: abs_extra_preserve_dir = Path(extra_preserve_dir).resolve() abs_app_dir = Path(app.app_dir).resolve() - if ( - abs_extra_preserve_dir == abs_app_dir - or abs_extra_preserve_dir in abs_app_dir.parents - ): + if abs_extra_preserve_dir == abs_app_dir or abs_extra_preserve_dir in abs_app_dir.parents: app.preserve = True ret_code = build_apps( @@ -193,9 +211,7 @@ if __name__ == '__main__': action='store_true', help='Preserve the binaries for all apps when specified.', ) - parser.add_argument( - '--parallel-count', default=1, type=int, help='Number of parallel build jobs.' - ) + parser.add_argument('--parallel-count', default=1, type=int, help='Number of parallel build jobs.') parser.add_argument( '--parallel-index', default=1, @@ -247,6 +263,11 @@ if __name__ == '__main__': help='only build tests matching given mark expression. For example: -m "host_test and generic". Works only' 'for pytest', ) + parser.add_argument( + '--default-build-test-rules', + default=os.path.join(IDF_PATH, '.gitlab', 'ci', 'default-build-test-rules.yml'), + help='default build test rules config file', + ) arguments = parser.parse_args() diff --git a/tools/ci/configure_ci_environment.sh b/tools/ci/configure_ci_environment.sh index 512f26e526..417663742f 100644 --- a/tools/ci/configure_ci_environment.sh +++ b/tools/ci/configure_ci_environment.sh @@ -44,3 +44,5 @@ if [ "${CI_CCACHE_DISABLE_SECONDARY}" != "1" ] && [ -n "${REDIS_CACHE}" ]; then export CCACHE_SECONDARY_STORAGE="redis://${REDIS_CACHE}" echo "INFO: Using CCACHE_SECONDARY_STORAGE=${CCACHE_SECONDARY_STORAGE}" fi + +export LDGEN_CHECK_MAPPING="1" diff --git a/tools/ci/exclude_check_tools_files.txt b/tools/ci/exclude_check_tools_files.txt index 168a8ee00d..028b79b88c 100644 --- a/tools/ci/exclude_check_tools_files.txt +++ b/tools/ci/exclude_check_tools_files.txt @@ -15,6 +15,7 @@ tools/ci/checkout_project_ref.py tools/ci/ci_fetch_submodule.py tools/ci/ci_get_mr_info.py tools/ci/configure_ci_environment.sh +tools/ci/generate_rules.py tools/ci/deploy_docs.py tools/ci/envsubst.py tools/ci/*exclude*.txt @@ -29,7 +30,6 @@ tools/ci/mypy_ignore_list.txt tools/ci/normalize_clangtidy_path.py tools/ci/push_to_github.sh tools/ci/python_packages/wifi_tools.py -tools/ci/setup_python.sh tools/ci/utils.sh tools/eclipse-code-style.xml tools/format-minimal.sh @@ -40,4 +40,3 @@ tools/set-submodules-to-github.sh tools/templates/sample_component/CMakeLists.txt tools/templates/sample_component/include/main.h tools/templates/sample_component/main.c -tools/toolchain_versions.mk diff --git a/tools/ci/executable-list.txt b/tools/ci/executable-list.txt index 4c51965632..af68794867 100644 --- a/tools/ci/executable-list.txt +++ b/tools/ci/executable-list.txt @@ -1,4 +1,3 @@ -.gitlab/ci/dependencies/generate_rules.py components/app_update/otatool.py components/efuse/efuse_table_gen.py components/efuse/test_efuse_host/efuse_tests.py @@ -71,6 +70,7 @@ tools/ci/checkout_project_ref.py tools/ci/deploy_docs.py tools/ci/envsubst.py tools/ci/fix_empty_prototypes.sh +tools/ci/generate_rules.py tools/ci/get-full-sources.sh tools/ci/get_supported_examples.sh tools/ci/mirror-submodule-update.sh @@ -113,6 +113,7 @@ tools/python_version_checker.py tools/set-submodules-to-github.sh tools/test_apps/system/no_embedded_paths/check_for_file_paths.py tools/test_idf_monitor/run_test_idf_monitor.py +tools/test_idf_py/test_hints.py tools/test_idf_py/test_idf_py.py tools/test_idf_size/test.sh tools/test_idf_tools/test_idf_tools.py diff --git a/.gitlab/ci/dependencies/generate_rules.py b/tools/ci/generate_rules.py similarity index 97% rename from .gitlab/ci/dependencies/generate_rules.py rename to tools/ci/generate_rules.py index 2d8ef88018..1d37ac69c6 100755 --- a/.gitlab/ci/dependencies/generate_rules.py +++ b/tools/ci/generate_rules.py @@ -11,6 +11,8 @@ from collections import defaultdict from itertools import product import yaml +from check_rules_yml import get_needed_rules +from idf_ci_utils import IDF_PATH try: import pygraphviz as pgv @@ -22,8 +24,6 @@ try: except ImportError: # used for type hint pass -IDF_PATH = os.path.abspath(os.getenv('IDF_PATH', os.path.join(os.path.dirname(__file__), '..', '..', '..'))) - def _list(str_or_list): # type: (Union[str, list]) -> list if isinstance(str_or_list, str): @@ -201,6 +201,9 @@ class RulesWriter: def new_rules_str(self): # type: () -> str res = [] for k, v in sorted(self.rules.items()): + if '.rules:' + k not in get_needed_rules(): + print(f'WARNING: unused rule: {k}, skipping...') + continue res.append(self.RULES_TEMPLATE.format(k, self._format_rule(k, v))) return '\n\n'.join(res) diff --git a/tools/ci/idf_ci_utils.py b/tools/ci/idf_ci_utils.py index 77cec5ccb1..050371b935 100644 --- a/tools/ci/idf_ci_utils.py +++ b/tools/ci/idf_ci_utils.py @@ -274,14 +274,6 @@ def get_pytest_cases( return cases -def get_pytest_app_paths( - paths: Union[str, List[str]], target: str, marker_expr: Optional[str] = None -) -> Set[str]: - cases = get_pytest_cases(paths, target, marker_expr) - - return set({app.path for case in cases for app in case.apps}) - - ################## # TTFW Utilities # ################## diff --git a/tools/ci/ignore_build_warnings.txt b/tools/ci/ignore_build_warnings.txt index fe3f6c1623..0f2daf214b 100644 --- a/tools/ci/ignore_build_warnings.txt +++ b/tools/ci/ignore_build_warnings.txt @@ -10,7 +10,8 @@ error\.d /.*error\S*.d reassigning to symbol changes choice state -crosstool_version_check\.cmake +tool_version_check\.cmake CryptographyDeprecationWarning Warning: \d+/\d+ app partitions are too small for binary CMake Deprecation Warning at main/lib/tinyxml2/CMakeLists\.txt:11 \(cmake_policy\) +The smallest .+ partition is nearly full \(\d+% free space left\)! diff --git a/tools/ci/integration_test/prepare_test_bins.py b/tools/ci/integration_test/prepare_test_bins.py index 8e6598a37e..48d847c7c8 100644 --- a/tools/ci/integration_test/prepare_test_bins.py +++ b/tools/ci/integration_test/prepare_test_bins.py @@ -7,7 +7,14 @@ import argparse import os import gitlab -import gitlab_api + +try: + import gitlab_api +except ImportError: + import sys + sys.path.append(os.path.join(os.path.dirname(__file__), '..', 'python_packages')) + import gitlab_api + from AutoTestScript.RunnerConfigs.Config import Config SSC_BUILD_JOB_MAP = { diff --git a/tools/ci/mypy_ignore_list.txt b/tools/ci/mypy_ignore_list.txt index b0e37ec659..a50adee500 100644 --- a/tools/ci/mypy_ignore_list.txt +++ b/tools/ci/mypy_ignore_list.txt @@ -18,7 +18,6 @@ components/protocomm/python/constants_pb2.py components/protocomm/python/sec0_pb2.py components/protocomm/python/sec1_pb2.py components/protocomm/python/session_pb2.py -components/ulp/esp32ulp_mapgen.py components/wifi_provisioning/python/wifi_config_pb2.py components/wifi_provisioning/python/wifi_constants_pb2.py components/wifi_provisioning/python/wifi_scan_pb2.py @@ -78,7 +77,6 @@ examples/protocols/icmp_echo/example_test.py examples/protocols/modbus/serial/example_test.py examples/protocols/modbus/tcp/example_test.py examples/protocols/mqtt/ssl/mqtt_ssl_example_test.py -examples/protocols/mqtt/ssl_ds/configure_ds.py examples/protocols/mqtt/tcp/mqtt_tcp_example_test.py examples/protocols/mqtt/ws/mqtt_ws_example_test.py examples/protocols/mqtt/wss/mqtt_wss_example_test.py diff --git a/tools/ci/python_packages/idf_http_server_test/adder.py b/tools/ci/python_packages/idf_http_server_test/adder.py index d11a8a2c4c..85ff255fa5 100644 --- a/tools/ci/python_packages/idf_http_server_test/adder.py +++ b/tools/ci/python_packages/idf_http_server_test/adder.py @@ -3,12 +3,9 @@ # SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 -from __future__ import print_function, unicode_literals - import argparse import http.client import logging -from builtins import range, str def start_session(ip, port): diff --git a/tools/ci/python_packages/idf_http_server_test/client.py b/tools/ci/python_packages/idf_http_server_test/client.py index 9215fe017e..a8dd67e1bf 100644 --- a/tools/ci/python_packages/idf_http_server_test/client.py +++ b/tools/ci/python_packages/idf_http_server_test/client.py @@ -3,13 +3,10 @@ # SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 -from __future__ import print_function, unicode_literals - import argparse import errno import http.client import logging -from builtins import str def verbose_print(verbosity, *args): diff --git a/tools/ci/python_packages/idf_http_server_test/test.py b/tools/ci/python_packages/idf_http_server_test/test.py index dac5e29d8b..0f0db77b03 100644 --- a/tools/ci/python_packages/idf_http_server_test/test.py +++ b/tools/ci/python_packages/idf_http_server_test/test.py @@ -118,8 +118,6 @@ # - Simple GET on /hello/restart_results (returns the leak results) -from __future__ import division, print_function - import argparse import http.client import logging @@ -129,7 +127,6 @@ import string import sys import threading import time -from builtins import object, range, str _verbose_ = False diff --git a/tools/ci/python_packages/idf_iperf_test_util/IperfUtility.py b/tools/ci/python_packages/idf_iperf_test_util/IperfUtility.py index 4d928da777..e350c9c57c 100644 --- a/tools/ci/python_packages/idf_iperf_test_util/IperfUtility.py +++ b/tools/ci/python_packages/idf_iperf_test_util/IperfUtility.py @@ -4,7 +4,6 @@ import os import re import subprocess import time -from builtins import object, range, str from idf_iperf_test_util import LineChart from tiny_test_fw import DUT, Utility @@ -336,7 +335,7 @@ class IperfTestUtility(object): self.dut.write('iperf -s -i 1 -t {}'.format(TEST_TIME)) # wait until DUT TCP server created try: - self.dut.expect('iperf tcp server create successfully', timeout=1) + self.dut.expect('iperf: Socket created', timeout=5) except DUT.ExpectTimeout: # compatible with old iperf example binary Utility.console_log('create iperf tcp server fail') @@ -356,7 +355,7 @@ class IperfTestUtility(object): self.dut.write('iperf -s -u -i 1 -t {}'.format(TEST_TIME)) # wait until DUT TCP server created try: - self.dut.expect('iperf udp server create successfully', timeout=1) + self.dut.expect('iperf: Socket bound', timeout=5) except DUT.ExpectTimeout: # compatible with old iperf example binary Utility.console_log('create iperf udp server fail') diff --git a/tools/ci/python_packages/ttfw_idf/IDFDUT.py b/tools/ci/python_packages/ttfw_idf/IDFDUT.py index f3d69becc1..aa4e106abb 100644 --- a/tools/ci/python_packages/ttfw_idf/IDFDUT.py +++ b/tools/ci/python_packages/ttfw_idf/IDFDUT.py @@ -216,7 +216,7 @@ class IDFDUT(DUT.SerialDUT): if expected_rom_class and type(inst) != expected_rom_class: raise RuntimeError('Target not expected') return inst.read_mac() is not None, get_target_by_rom_class(type(inst)) - except(FatalError, RuntimeError): + except (FatalError, RuntimeError): return False, None finally: if inst is not None: diff --git a/tools/ci/setup_python.sh b/tools/ci/setup_python.sh deleted file mode 100644 index c85924e087..0000000000 --- a/tools/ci/setup_python.sh +++ /dev/null @@ -1,50 +0,0 @@ -#!/usr/bin/env bash - -if [ -z ${PYTHON_VER+x} ]; then - # Use this version of the Python interpreter if it was not defined before. - # 3.6.13 is the default python3 interpreter in esp32-ci-env - # Jobs which doesn't support this version should define PYTHON_VER themselves - PYTHON_VER=3.7.10 -fi - -if [ -f /opt/pyenv/activate ]; -then - source /opt/pyenv/activate - pyenv global $PYTHON_VER || { - echo 'Python' $PYTHON_VER 'is not installed.' - INSTALLED_PY_VERS=$(pyenv versions --bare) - - while [ ${#PYTHON_VER} -gt 0 ] - do - echo 'Tring to locate a match for' $PYTHON_VER - - for ver in ${INSTALLED_PY_VERS[@]} - do - if [[ $ver == $PYTHON_VER* ]]; - then - pyenv global $ver - break 2 - fi - done - - # Removing last character and trying to find some match. - # For example, if 3.4.8 was selected but isn't installed then it will try to - # find some other installed 3.4.X version, and then some 3.X.X version. - PYTHON_VER=${PYTHON_VER: : -1} - done - } - python --version || { - echo 'No matching Python interpreter is found!' - exit 1 - } -elif command -v python -V 1>/dev/null 2>&1; -then - python --version - echo 'No /opt/pyenv/activate exists and Python from path is used.' -else - echo 'No /opt/pyenv/activate exists and no Python interpreter is found!' - exit 1 -fi - -# add esp-idf local package path to PYTHONPATH so it can be imported directly -export PYTHONPATH="$IDF_PATH/tools:$IDF_PATH/components/partition_table:$IDF_PATH/tools/ci/python_packages:$PYTHONPATH" diff --git a/tools/ci/static-analysis-rules.yml b/tools/ci/static-analysis-rules.yml index f729329f02..d67022c636 100644 --- a/tools/ci/static-analysis-rules.yml +++ b/tools/ci/static-analysis-rules.yml @@ -30,7 +30,6 @@ skip: - "components/tinyusb/tinyusb" - "components/unity/unity" - "components/heap/tlsf" - - "examples/peripherals/secure_element/atecc608_ecdsa/components/esp-cryptoauthlib" # disabled temporarily to pass the CI - "components/bt/common/btc/core/btc_task.c" diff --git a/tools/ci/test_build_system_cmake.sh b/tools/ci/test_build_system_cmake.sh index 247d3e1e05..f75a3e710b 100755 --- a/tools/ci/test_build_system_cmake.sh +++ b/tools/ci/test_build_system_cmake.sh @@ -936,6 +936,14 @@ endmenu\n" >> ${IDF_PATH}/Kconfig mv CMakeLists.bak CMakeLists.txt # revert previous modifications rm -rf extra_dir components + print_status "Components in EXCLUDE_COMPONENTS not passed to idf_component_manager" + clean_build_dir + idf.py create-component -C components/ to_be_excluded || failure "Failed to create a component" + echo "invalid syntax..." > components/to_be_excluded/idf_component.yml + ! idf.py reconfigure || failure "Build should have failed due to invalid syntax in idf_component.yml" + idf.py -DEXCLUDE_COMPONENTS=to_be_excluded reconfigure || failure "Build should have succeeded when the component is excluded" + rm -rf components/to_be_excluded + print_status "Create project using idf.py and build it" echo "Trying to create project." (idf.py -C projects create-project temp_test_project) || failure "Failed to create the project." diff --git a/tools/cmake/build.cmake b/tools/cmake/build.cmake index 0a274e89eb..7045bea6a1 100644 --- a/tools/cmake/build.cmake +++ b/tools/cmake/build.cmake @@ -30,6 +30,9 @@ endfunction() function(idf_build_set_property property value) cmake_parse_arguments(_ "APPEND" "" "" ${ARGN}) + # Fixup property value, e.g. for compatibility. (Overwrites variable 'value'.) + __build_fixup_property("${property}" "${value}" value) + if(__APPEND) set_property(TARGET __idf_build_target APPEND PROPERTY ${property} ${value}) else() @@ -73,7 +76,7 @@ function(__build_get_idf_git_revision) endif() # cut IDF_VER to required 32 characters. string(SUBSTRING "${idf_ver_t}" 0 31 idf_ver) - idf_build_set_property(COMPILE_DEFINITIONS "-DIDF_VER=\"${idf_ver}\"" APPEND) + idf_build_set_property(COMPILE_DEFINITIONS "IDF_VER=\"${idf_ver}\"" APPEND) git_submodule_check("${idf_path}") idf_build_set_property(IDF_VER ${idf_ver}) endfunction() @@ -90,7 +93,7 @@ function(__build_set_default_build_specifications) unset(c_compile_options) unset(cxx_compile_options) - list(APPEND compile_definitions "-D_GNU_SOURCE") + list(APPEND compile_definitions "_GNU_SOURCE") list(APPEND compile_options "-ffunction-sections" "-fdata-sections" @@ -164,6 +167,21 @@ function(__build_set_lang_version) idf_build_set_property(CXX_COMPILE_OPTIONS "-std=${cxx_std}" APPEND) endfunction() +# +# Perform any fixes or adjustments to the values stored in IDF build properties. +# This function only gets called from 'idf_build_set_property' and doesn't affect +# the properties set directly via 'set_property'. +# +function(__build_fixup_property property value out_var) + + # Fixup COMPILE_DEFINITIONS property to support -D prefix, which had to be used in IDF v4.x projects. + if(property STREQUAL "COMPILE_DEFINITIONS" AND NOT "${value}" STREQUAL "") + string(REGEX REPLACE "^-D" "" stripped_value "${value}") + set("${out_var}" "${stripped_value}" PARENT_SCOPE) + endif() + +endfunction() + # # Initialize the build. This gets called upon inclusion of idf.cmake to set internal # properties used for the processing phase of the build. @@ -206,7 +224,7 @@ function(__build_init idf_path) endforeach() if("${target}" STREQUAL "linux") - set(requires_common freertos log esp_rom esp_common) + set(requires_common freertos log esp_rom esp_common linux) idf_build_set_property(__COMPONENT_REQUIRES_COMMON "${requires_common}") else() # Set components required by all other components in the build @@ -494,10 +512,8 @@ macro(idf_build_process target) set(local_components_list_file ${build_dir}/local_components_list.temp.yml) set(__contents "components:\n") - idf_build_get_property(__component_targets __COMPONENT_TARGETS) - foreach(__component_target ${__component_targets}) - __component_get_property(__component_name ${__component_target} COMPONENT_NAME) - __component_get_property(__component_dir ${__component_target} COMPONENT_DIR) + foreach(__component_name ${components}) + idf_component_get_property(__component_dir ${__component_name} COMPONENT_DIR) set(__contents "${__contents} - name: \"${__component_name}\"\n path: \"${__component_dir}\"\n") endforeach() @@ -594,7 +610,7 @@ macro(idf_build_process target) # All targets built under this scope is with the ESP-IDF build system set(ESP_PLATFORM 1) - idf_build_set_property(COMPILE_DEFINITIONS "-DESP_PLATFORM" APPEND) + idf_build_set_property(COMPILE_DEFINITIONS "ESP_PLATFORM" APPEND) # Perform component processing (inclusion of project_include.cmake, adding component # subdirectories, creating library targets, linking libraries, etc.) @@ -614,8 +630,7 @@ endmacro() function(idf_build_executable elf) # Set additional link flags for the executable idf_build_get_property(link_options LINK_OPTIONS) - # Using LINK_LIBRARIES here instead of LINK_OPTIONS, as the latter is not in CMake 3.5. - set_property(TARGET ${elf} APPEND PROPERTY LINK_LIBRARIES "${link_options}") + set_property(TARGET ${elf} APPEND PROPERTY LINK_OPTIONS "${link_options}") # Propagate link dependencies from component library targets to the executable idf_build_get_property(link_depends __LINK_DEPENDS) diff --git a/tools/cmake/component.cmake b/tools/cmake/component.cmake index cea0084bf7..218d1b4d0e 100644 --- a/tools/cmake/component.cmake +++ b/tools/cmake/component.cmake @@ -453,6 +453,7 @@ function(idf_component_register) # idf_build_process idf_build_get_property(include_directories INCLUDE_DIRECTORIES GENERATOR_EXPRESSION) idf_build_get_property(compile_options COMPILE_OPTIONS GENERATOR_EXPRESSION) + idf_build_get_property(compile_definitions COMPILE_DEFINITIONS GENERATOR_EXPRESSION) idf_build_get_property(c_compile_options C_COMPILE_OPTIONS GENERATOR_EXPRESSION) idf_build_get_property(cxx_compile_options CXX_COMPILE_OPTIONS GENERATOR_EXPRESSION) idf_build_get_property(asm_compile_options ASM_COMPILE_OPTIONS GENERATOR_EXPRESSION) @@ -460,18 +461,11 @@ function(idf_component_register) include_directories("${include_directories}") add_compile_options("${compile_options}") + add_compile_definitions("${compile_definitions}") add_c_compile_options("${c_compile_options}") add_cxx_compile_options("${cxx_compile_options}") add_asm_compile_options("${asm_compile_options}") - # Unfortunately add_definitions() does not support generator expressions. A new command - # add_compile_definition() does but is only available on CMake 3.12 or newer. This uses - # add_compile_options(), which can add any option as the workaround. - # - # TODO: Use add_compile_definitions() once minimum supported version is 3.12 or newer. - idf_build_get_property(compile_definitions COMPILE_DEFINITIONS GENERATOR_EXPRESSION) - add_compile_options("${compile_definitions}") - if(common_reqs) # check whether common_reqs exists, this may be the case in minimalistic host unit test builds list(REMOVE_ITEM common_reqs ${component_lib}) endif() @@ -564,6 +558,8 @@ function(idf_component_mock) INCLUDE_DIRS ${__INCLUDE_DIRS} REQUIRES ${__REQUIRES}) + + set(COMPONENT_LIB ${COMPONENT_LIB} PARENT_SCOPE) add_custom_command( OUTPUT ruby_found SYMBOLIC COMMAND "ruby" "-v" diff --git a/tools/cmake/crosstool_version_check.cmake b/tools/cmake/crosstool_version_check.cmake deleted file mode 100644 index 5f8aeaa116..0000000000 --- a/tools/cmake/crosstool_version_check.cmake +++ /dev/null @@ -1,59 +0,0 @@ -# Function to check the toolchain used the expected version -# of crosstool, and warn otherwise - -set(ctng_version_warning "Check Getting Started documentation or proceed at own risk.\n") - -function(gcc_version_check expected_gcc_version) - if(NOT "${CMAKE_C_COMPILER_VERSION}" STREQUAL "${expected_gcc_version}") - message(WARNING "Toolchain ${CMAKE_C_COMPILER} version ${CMAKE_C_COMPILER_VERSION} " - "is not the supported version ${expected_gcc_version}. ${ctng_version_warning}") - endif() -endfunction() - -function(crosstool_version_check expected_ctng_version) - execute_process( - COMMAND ${CMAKE_C_COMPILER} --version - OUTPUT_VARIABLE toolchain_version - ERROR_QUIET) - - string(REGEX REPLACE ".*(crosstool-NG ([^\)]+)).*\n" "\\2" ctng_version "${toolchain_version}") - # We use FIND to match version instead of STREQUAL because some toolchains are built - # with longer git hash strings than others. This will match any version which starts with - # the expected version string. - string(FIND "${ctng_version}" "${expected_ctng_version}" found_expected_version) - if(NOT ctng_version) - message(WARNING "Toolchain ${CMAKE_C_COMPILER} does not appear to be built with crosstool-ng. " - "${ctng_version_warning}") - elseif(found_expected_version EQUAL -1) - set(wrong_compiler_msg "\nToolchain: ${CMAKE_C_COMPILER}, " - "crosstool-ng version ${ctng_version} doesn't match supported version ${expected_ctng_version}" - "\nPlease try to run 'idf.py fullclean' to solve it quickly.\n") - set(IDF_MAINTAINER $ENV{IDF_MAINTAINER}) - if(IDF_MAINTAINER) - message(WARNING ${wrong_compiler_msg} ${ctng_version_warning}) - else() - set(ctng_version_error "Check Getting Started documentation if the error continues." - "\nYou can override this error and proceed with build by defining the IDF_MAINTAINER environment variable.\n") - message(FATAL_ERROR ${wrong_compiler_msg} ${ctng_version_error}) - endif() - endif() -endfunction() - -function(get_expected_ctng_version _toolchain_ver _gcc_ver) - idf_build_get_property(idf_path IDF_PATH) - file(STRINGS ${idf_path}/tools/toolchain_versions.mk config_contents) - foreach(name_and_value ${config_contents}) - # Strip spaces - string(REPLACE " " "" name_and_value ${name_and_value}) - # Find variable name - string(REGEX MATCH "^[^=]+" name ${name_and_value}) - # Find the value - string(REPLACE "${name}=" "" value ${name_and_value}) - # Getting values - if("${name}" STREQUAL "SUPPORTED_TOOLCHAIN_COMMIT_DESC") - set("${_toolchain_ver}" "${value}" PARENT_SCOPE) - elseif("${name}" STREQUAL "SUPPORTED_TOOLCHAIN_GCC_VERSIONS") - set(${_gcc_ver} "${value}" PARENT_SCOPE) - endif() - endforeach() -endfunction() diff --git a/tools/cmake/dfu.cmake b/tools/cmake/dfu.cmake index c6c5172dc7..8db0a6199e 100644 --- a/tools/cmake/dfu.cmake +++ b/tools/cmake/dfu.cmake @@ -15,6 +15,8 @@ function(__add_dfu_targets) return() elseif("${target}" STREQUAL "esp32c2") return() + elseif("${target}" STREQUAL "esp32c6") + return() elseif("${target}" STREQUAL "linux") return() else() diff --git a/tools/cmake/idf.cmake b/tools/cmake/idf.cmake index aad4475af5..71cf857369 100644 --- a/tools/cmake/idf.cmake +++ b/tools/cmake/idf.cmake @@ -39,7 +39,7 @@ if(NOT __idf_env_set) include(CheckCCompilerFlag) include(CheckCXXCompilerFlag) include(git_submodules) - include(crosstool_version_check) + include(tool_version_check) include(kconfig) include(component) include(utilities) diff --git a/tools/cmake/project.cmake b/tools/cmake/project.cmake index a051cb6629..1604b9840d 100644 --- a/tools/cmake/project.cmake +++ b/tools/cmake/project.cmake @@ -344,6 +344,12 @@ macro(project project_name) # Generate compile_commands.json (needs to come after project call). set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + # If CMAKE_COLOR_DIAGNOSTICS not set in project CMakeLists.txt or in the environment, + # enable it by default. + if(NOT DEFINED CMAKE_COLOR_DIAGNOSTICS AND NOT DEFINED ENV{CMAKE_COLOR_DIAGNOSTICS}) + set(CMAKE_COLOR_DIAGNOSTICS ON) + endif() + # Since components can import third-party libraries, the original definition of project() should be restored # before the call to add components to the build. function(project) @@ -518,8 +524,12 @@ macro(project project_name) set(mapfile "${CMAKE_BINARY_DIR}/${CMAKE_PROJECT_NAME}.map") set(idf_target "${IDF_TARGET}") string(TOUPPER ${idf_target} idf_target) - target_link_libraries(${project_elf} PRIVATE "-Wl,--cref" "-Wl,--defsym=IDF_TARGET_${idf_target}=0" - "-Wl,--Map=\"${mapfile}\"") + # Add cross-reference table to the map file + target_link_options(${project_elf} PRIVATE "-Wl,--cref") + # Add this symbol as a hint for idf_size.py to guess the target name + target_link_options(${project_elf} PRIVATE "-Wl,--defsym=IDF_TARGET_${idf_target}=0") + # Enable map file output + target_link_options(${project_elf} PRIVATE "-Wl,--Map=${mapfile}") unset(idf_target) endif() @@ -531,23 +541,44 @@ macro(project project_name) idf_build_get_property(python PYTHON) set(idf_size ${python} ${idf_path}/tools/idf_size.py) - if(DEFINED OUTPUT_JSON AND OUTPUT_JSON) - list(APPEND idf_size "--json") - endif() # Add size targets, depend on map file, run idf_size.py + # OUTPUT_JSON is passed for compatibility reasons, SIZE_OUTPUT_FORMAT + # environment variable is recommended and has higher priority add_custom_target(size + COMMAND ${CMAKE_COMMAND} + -D "IDF_SIZE_TOOL=${idf_size}" + -D "MAP_FILE=${mapfile}" + -D "OUTPUT_JSON=${OUTPUT_JSON}" + -P "${idf_path}/tools/cmake/run_size_tool.cmake" DEPENDS ${mapfile} - COMMAND ${idf_size} ${mapfile} - ) + USES_TERMINAL + VERBATIM + ) + add_custom_target(size-files + COMMAND ${CMAKE_COMMAND} + -D "IDF_SIZE_TOOL=${idf_size}" + -D "IDF_SIZE_MODE=--files" + -D "MAP_FILE=${mapfile}" + -D "OUTPUT_JSON=${OUTPUT_JSON}" + -P "${idf_path}/tools/cmake/run_size_tool.cmake" DEPENDS ${mapfile} - COMMAND ${idf_size} --files ${mapfile} - ) + USES_TERMINAL + VERBATIM + ) + add_custom_target(size-components + COMMAND ${CMAKE_COMMAND} + -D "IDF_SIZE_TOOL=${idf_size}" + -D "IDF_SIZE_MODE=--archives" + -D "MAP_FILE=${mapfile}" + -D "OUTPUT_JSON=${OUTPUT_JSON}" + -P "${idf_path}/tools/cmake/run_size_tool.cmake" DEPENDS ${mapfile} - COMMAND ${idf_size} --archives ${mapfile} - ) + USES_TERMINAL + VERBATIM + ) unset(idf_size) diff --git a/tools/cmake/project_description.json.in b/tools/cmake/project_description.json.in index 2145d0fa5f..8ed6c197ce 100644 --- a/tools/cmake/project_description.json.in +++ b/tools/cmake/project_description.json.in @@ -4,6 +4,7 @@ "build_dir": "${BUILD_DIR}", "config_file": "${SDKCONFIG}", "config_defaults": "${SDKCONFIG_DEFAULTS}", + "bootloader_elf": "${BOOTLOADER_ELF_FILE}", "app_elf": "${PROJECT_EXECUTABLE}", "app_bin": "${PROJECT_BIN}", "git_revision": "${IDF_VER}", diff --git a/tools/cmake/run_size_tool.cmake b/tools/cmake/run_size_tool.cmake new file mode 100644 index 0000000000..27be3977e7 --- /dev/null +++ b/tools/cmake/run_size_tool.cmake @@ -0,0 +1,43 @@ +# A CMake script to run size tool commands supporting SIZE_OUTPUT_FORMAT and +# OUTPUT_JSON environment variables from within ninja or make or another +# cmake-based build runner. +# +# It is recommended to NOT USE this CMake script if you have the option of +# running the tool directly. This script exists only for use inside CMake builds. +cmake_minimum_required(VERSION 3.16) + +# Main purpose of this script: we can't expand these environment variables in the main IDF CMake build, +# because we want to expand them at CMake target build time not at CMake configuration time +# (so they can change without needing a CMake re-run) + +set(IDF_SIZE_CMD ${IDF_SIZE_TOOL}) + +if(NOT DEFINED ENV{SIZE_OUTPUT_FORMAT} OR "$ENV{SIZE_OUTPUT_FORMAT}" STREQUAL "default") + # Format not passed to "idf.py size" explicitly, or this target was invoked + # from make/ninja directly (without idf.py) + if(DEFINED OUTPUT_JSON AND OUTPUT_JSON) + # honor the legacy OUTPUT_JSON variable, if set + list(APPEND IDF_SIZE_CMD "--format=json") + endif() +elseif(DEFINED ENV{SIZE_OUTPUT_FORMAT}) + # specific format was requested + list(APPEND IDF_SIZE_CMD "--format=$ENV{SIZE_OUTPUT_FORMAT}") +endif() + +if(DEFINED ENV{SIZE_OUTPUT_FILE}) + list(APPEND IDF_SIZE_CMD "--output-file=$ENV{SIZE_OUTPUT_FILE}") +endif() + +if(DEFINED IDF_SIZE_MODE) + list(APPEND IDF_SIZE_CMD ${IDF_SIZE_MODE}) +endif() + +list(APPEND IDF_SIZE_CMD ${MAP_FILE}) + +execute_process(COMMAND ${IDF_SIZE_CMD} + RESULT_VARIABLE result + ) + +if(${result}) + message(FATAL_ERROR "${IDF_SIZE_TOOL} failed") +endif() diff --git a/tools/cmake/tool_version_check.cmake b/tools/cmake/tool_version_check.cmake new file mode 100644 index 0000000000..df68f59b9b --- /dev/null +++ b/tools/cmake/tool_version_check.cmake @@ -0,0 +1,44 @@ +function(check_expected_tool_version tool_name tool_path) + # Function to check the tool used the expected version and warn otherwise + set(tool_version_warning "Check Getting Started documentation or proceed at own risk.\n") + set(tool_version_error "Check Getting Started documentation if the error continues.\n" + "You can override this error and proceed with build by defining the IDF_MAINTAINER environment variable.\n") + set(fixing_hint "Please try to run 'idf.py fullclean' to solve it.\n") + + idf_build_get_property(python PYTHON) + idf_build_get_property(idf_path IDF_PATH) + + set(ENV{IDF_TOOLS_VERSION_HELPER} "1") + # Use idf_tools.py to check if tool version is supported + execute_process( + COMMAND ${python} "${idf_path}/tools/idf_tools.py" + "check-tool-supported" "--tool-name" "${tool_name}" + "--exec-path" "${tool_path}" + OUTPUT_VARIABLE is_version_supported + OUTPUT_STRIP_TRAILING_WHITESPACE + ERROR_QUIET) + + if(is_version_supported STREQUAL "False") + # Version is not supported. Need to get supported versions list to print them to user + execute_process( + COMMAND ${python} "${idf_path}/tools/idf_tools.py" + "get-tool-supported-versions" "--tool-name" "${tool_name}" + OUTPUT_VARIABLE tool_supported_versions + OUTPUT_STRIP_TRAILING_WHITESPACE + ERROR_QUIET) + # IDF maintainers can build projects with not supported versions with just a warning + if($ENV{IDF_MAINTAINER}) + set(message_mode "WARNING") + else() + set(message_mode "FATAL_ERROR") + endif() + + message(${message_mode} "\n" + "Tool doesn't match supported version from list " + "${tool_supported_versions}: ${tool_path}\n" + ${fixing_hint}) + elseif(NOT is_version_supported STREQUAL "True") + message(WARNING "Can not get version for tool: ${tool_path}\n" ${tool_version_warning}) + endif() + unset(ENV{IDF_TOOLS_VERSION_HELPER}) +endfunction() diff --git a/tools/cmake/toolchain-esp32c6.cmake b/tools/cmake/toolchain-esp32c6.cmake new file mode 100644 index 0000000000..ff3ba0b65f --- /dev/null +++ b/tools/cmake/toolchain-esp32c6.cmake @@ -0,0 +1,18 @@ +include($ENV{IDF_PATH}/tools/cmake/utilities.cmake) + +set(CMAKE_SYSTEM_NAME Generic) + +set(CMAKE_C_COMPILER riscv32-esp-elf-gcc) +set(CMAKE_CXX_COMPILER riscv32-esp-elf-g++) +set(CMAKE_ASM_COMPILER riscv32-esp-elf-gcc) +set(_CMAKE_TOOLCHAIN_PREFIX riscv32-esp-elf-) + +remove_duplicated_flags("-march=rv32imac ${CMAKE_C_FLAGS}" UNIQ_CMAKE_C_FLAGS) +set(CMAKE_C_FLAGS "${UNIQ_CMAKE_C_FLAGS}" CACHE STRING "C Compiler Base Flags" FORCE) +remove_duplicated_flags("-march=rv32imac ${CMAKE_CXX_FLAGS}" UNIQ_CMAKE_CXX_FLAGS) +set(CMAKE_CXX_FLAGS "${UNIQ_CMAKE_CXX_FLAGS}" CACHE STRING "C++ Compiler Base Flags" FORCE) + +remove_duplicated_flags("-nostartfiles -march=rv32imac --specs=nosys.specs \ + ${CMAKE_EXE_LINKER_FLAGS}" + UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS) +set(CMAKE_EXE_LINKER_FLAGS "${UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS}" CACHE STRING "Linker Base Flags" FORCE) diff --git a/tools/cmake/uf2.cmake b/tools/cmake/uf2.cmake index 525a128eda..4e80d8decf 100644 --- a/tools/cmake/uf2.cmake +++ b/tools/cmake/uf2.cmake @@ -14,6 +14,8 @@ function(__add_uf2_targets) set(uf2_family_id "0x332726f6") elseif("${target}" STREQUAL "esp32c2") set(uf2_family_id "0x2b88d29c") + elseif("${target}" STREQUAL "esp32c6") # TODO: IDF-5626 + set(uf2_family_id "0x2b88d29c") elseif("${target}" STREQUAL "linux") return() else() diff --git a/tools/cmake/utilities.cmake b/tools/cmake/utilities.cmake index b035f278c7..9d1a301b9f 100644 --- a/tools/cmake/utilities.cmake +++ b/tools/cmake/utilities.cmake @@ -152,24 +152,18 @@ function(target_linker_script target deptype scriptfiles) get_filename_component(search_dir "${abs_script}" DIRECTORY) get_filename_component(scriptname "${abs_script}" NAME) - if(deptype STREQUAL INTERFACE OR deptype STREQUAL PUBLIC) - get_target_property(link_libraries "${target}" INTERFACE_LINK_LIBRARIES) - else() - get_target_property(link_libraries "${target}" LINK_LIBRARIES) - endif() - - list(FIND "${link_libraries}" "-L \"${search_dir}\"" found_search_dir) - if(found_search_dir EQUAL "-1") # not already added as a search path - target_link_libraries("${target}" "${deptype}" "-L \"${search_dir}\"") - endif() - - target_link_libraries("${target}" "${deptype}" "-T ${scriptname}") + target_link_directories("${target}" "${deptype}" ${search_dir}) + # Regarding the usage of SHELL, see + # https://cmake.org/cmake/help/latest/command/target_link_options.html#option-de-duplication + target_link_options("${target}" "${deptype}" "SHELL:-T ${scriptname}") # Note: In ESP-IDF, most targets are libraries and libary LINK_DEPENDS don't propagate to - # executable(s) the library is linked to. Attach manually to executable once it is known. - # - # Property INTERFACE_LINK_DEPENDS is available in CMake 3.13 which should propagate link - # dependencies. + # executable(s) the library is linked to. Since CMake 3.13, INTERFACE_LINK_DEPENDS is + # available to solve this. However, when GNU Make generator is used, this property also + # propagates INTERFACE_LINK_DEPENDS dependencies to other static libraries. + # TODO: see if this is an expected behavior and possibly report this as a bug to CMake. + # For the time being, record all linker scripts in __LINK_DEPENDS and attach manually to + # the executable target once it is known. if(NOT __PROCESS) idf_build_set_property(__LINK_DEPENDS ${abs_script} APPEND) endif() diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile index ab0d018cd8..447cb76f84 100644 --- a/tools/docker/Dockerfile +++ b/tools/docker/Dockerfile @@ -2,7 +2,6 @@ FROM ubuntu:20.04 ARG DEBIAN_FRONTEND=noninteractive -# We need libpython2.7 due to GDB tools RUN : \ && apt-get update \ && apt-get install -y \ @@ -14,12 +13,12 @@ RUN : \ curl \ flex \ git \ + git-lfs \ gperf \ lcov \ libbsd-dev \ libffi-dev \ libncurses-dev \ - libpython2.7 \ libusb-1.0-0-dev \ make \ ninja-build \ diff --git a/tools/gdb_panic_server.py b/tools/gdb_panic_server.py index cd66a20b11..eeef4321aa 100644 --- a/tools/gdb_panic_server.py +++ b/tools/gdb_panic_server.py @@ -25,7 +25,6 @@ import binascii import logging import struct import sys -from builtins import bytes from collections import namedtuple # Used for type annotations only. Silence linter warnings. @@ -60,7 +59,8 @@ GDB_REGS_INFO_RISCV_ILP32 = [ GDB_REGS_INFO = { 'esp32c3': GDB_REGS_INFO_RISCV_ILP32, 'esp32c2': GDB_REGS_INFO_RISCV_ILP32, - 'esp32h2': GDB_REGS_INFO_RISCV_ILP32 + 'esp32h2': GDB_REGS_INFO_RISCV_ILP32, + 'esp32c6': GDB_REGS_INFO_RISCV_ILP32 } PanicInfo = namedtuple('PanicInfo', 'core_id regs stack_base_addr stack_data') @@ -154,7 +154,8 @@ def parse_idf_riscv_panic_output(panic_text): # type: (str) -> PanicInfo PANIC_OUTPUT_PARSERS = { 'esp32c3': parse_idf_riscv_panic_output, 'esp32c2': parse_idf_riscv_panic_output, - 'esp32h2': parse_idf_riscv_panic_output + 'esp32h2': parse_idf_riscv_panic_output, + 'esp32c6': parse_idf_riscv_panic_output } diff --git a/tools/gen_esp_err_to_name.py b/tools/gen_esp_err_to_name.py index b4957d967c..17f76b886e 100755 --- a/tools/gen_esp_err_to_name.py +++ b/tools/gen_esp_err_to_name.py @@ -3,22 +3,6 @@ # SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 -from __future__ import print_function, unicode_literals - -import sys -from typing import Any, List, Optional, TextIO - -try: - from builtins import object, range, str -except ImportError: - # This should not happen because the Python packages are checked before invoking this script. However, here is - # some output which should help if we missed something. - print('Import has failed probably because of the missing "future" package. Please install all the packages for ' - 'interpreter {} from the requirements.txt file.'.format(sys.executable)) - # The path to requirements.txt is not provided because this script could be invoked from an IDF project (then the - # requirements.txt from the IDF_PATH should be used) or from the documentation project (then the requirements.txt - # for the documentation directory should be used). - sys.exit(1) import argparse import collections import fnmatch @@ -27,6 +11,7 @@ import os import re import textwrap from io import open +from typing import Any, List, Optional, TextIO # list files here which should not be parsed ignore_files: list = list() @@ -83,9 +68,9 @@ class ErrItem(object): base = '_BASE' if self.file == other.file: - if self.name.endswith(base) and not(other.name.endswith(base)): + if self.name.endswith(base) and not other.name.endswith(base): return 1 - elif not(self.name.endswith(base)) and other.name.endswith(base): + elif not self.name.endswith(base) and other.name.endswith(base): return -1 self_key = self.file + self.name diff --git a/tools/idf.py b/tools/idf.py index 2a705e556d..1d05593aed 100755 --- a/tools/idf.py +++ b/tools/idf.py @@ -27,7 +27,7 @@ from collections import Counter, OrderedDict, _OrderedDictKeysView from importlib import import_module from pkgutil import iter_modules from types import FrameType -from typing import Any, Callable, Dict, List, Optional, TextIO, Union +from typing import Any, Callable, Dict, List, Optional, Union # pyc files remain in the filesystem when switching between branches which might raise errors for incompatible # idf.py extensions. Therefore, pyc file generation is turned off: @@ -37,8 +37,10 @@ import python_version_checker # noqa: E402 try: from idf_py_actions.errors import FatalError # noqa: E402 - from idf_py_actions.tools import (PropertyDict, executable_exists, get_target, idf_version, # noqa: E402 - merge_action_lists, realpath) + from idf_py_actions.tools import (PROG, SHELL_COMPLETE_RUN, SHELL_COMPLETE_VAR, PropertyDict, # noqa: E402 + debug_print_idf_version, get_target, merge_action_lists, print_warning, realpath) + if os.getenv('IDF_COMPONENT_MANAGER') != '0': + from idf_component_manager import idf_extensions except ImportError: # For example, importing click could cause this. print('Please use idf.py only in an ESP-IDF shell environment.', file=sys.stderr) @@ -51,23 +53,6 @@ PYTHON = sys.executable # you have to pass env=os.environ explicitly anywhere that we create a process os.environ['PYTHON'] = sys.executable -# Name of the program, normally 'idf.py'. -# Can be overridden from idf.bat using IDF_PY_PROGRAM_NAME -PROG = os.getenv('IDF_PY_PROGRAM_NAME', 'idf.py') - -# environment variable used during click shell completion run -SHELL_COMPLETE_VAR = '_IDF.PY_COMPLETE' - -# was shell completion invoked? -SHELL_COMPLETE_RUN = SHELL_COMPLETE_VAR in os.environ - - -# function prints warning when autocompletion is not being performed -# set argument stream to sys.stderr for errors and exceptions -def print_warning(message: str, stream: TextIO=None) -> None: - if not SHELL_COMPLETE_RUN: - print(message, file=stream or sys.stderr) - def check_environment() -> List: """ @@ -77,10 +62,6 @@ def check_environment() -> List: """ checks_output = [] - if not executable_exists(['cmake', '--version']): - debug_print_idf_version() - raise FatalError("'cmake' must be available on the PATH to use %s" % PROG) - # verify that IDF_PATH env variable is set # find the directory idf.py is in, then the parent directory of this, and assume this is IDF_PATH detected_idf_path = realpath(os.path.join(os.path.dirname(__file__), '..')) @@ -135,14 +116,6 @@ def _safe_relpath(path: str, start: Optional[str]=None) -> str: return os.path.abspath(path) -def debug_print_idf_version() -> None: - version = idf_version() - if version: - print_warning('ESP-IDF %s' % version) - else: - print_warning('ESP-IDF version unknown') - - def init_cli(verbose_output: List=None) -> Any: # Click is imported here to run it after check_environment() import click @@ -672,7 +645,6 @@ def init_cli(verbose_output: List=None) -> Any: # Load component manager idf.py extensions if not explicitly disabled if os.getenv('IDF_COMPONENT_MANAGER') != '0': - from idf_component_manager import idf_extensions extensions.append(('component_manager_ext', idf_extensions)) # Optional load `pyclang` for additional clang-tidy related functionalities diff --git a/tools/idf_monitor.py b/tools/idf_monitor.py index b990ba3be5..8e4e372909 100755 --- a/tools/idf_monitor.py +++ b/tools/idf_monitor.py @@ -29,7 +29,6 @@ import subprocess import sys import threading import time -from builtins import bytes from typing import Any, List, Optional, Type, Union import serial diff --git a/tools/idf_py_actions/constants.py b/tools/idf_py_actions/constants.py index bd0f1f291a..5311d8c7d5 100644 --- a/tools/idf_py_actions/constants.py +++ b/tools/idf_py_actions/constants.py @@ -12,7 +12,6 @@ GENERATORS: Dict[str, Union[str, Dict, list]] = collections.OrderedDict([ # - dry_run: command to run in dry run mode # - verbose_flag: verbose flag # - force_progression: one liner status of the progress - # - envvar: environment variables ('Ninja', { 'command': ['ninja'], 'version': ['ninja', '--version'], @@ -20,7 +19,6 @@ GENERATORS: Dict[str, Union[str, Dict, list]] = collections.OrderedDict([ 'verbose_flag': '-v', # as opposed to printing the status updates each in a in new line 'force_progression': True, - 'envvar': {} }), ]) @@ -30,11 +28,17 @@ if os.name != 'nt': 'version': [MAKE_CMD, '--version'], 'dry_run': [MAKE_CMD, '-n'], 'verbose_flag': 'VERBOSE=1', - 'force_progression': False, - # CLICOLOR_FORCE if set forcing make to print ANSI escape sequence - 'envvar': {'CLICOLOR_FORCE': '1'}} + 'force_progression': False} URL_TO_DOC = 'https://docs.espressif.com/projects/esp-idf' SUPPORTED_TARGETS = ['esp32', 'esp32s2', 'esp32c3', 'esp32s3', 'esp32c2'] -PREVIEW_TARGETS = ['linux', 'esp32h2'] +PREVIEW_TARGETS = ['linux', 'esp32h2', 'esp32c6'] + +OPENOCD_TAGET_CONFIG_DEFAULT = '-f interface/ftdi/esp32_devkitj_v1.cfg -f target/{target}.cfg' +OPENOCD_TAGET_CONFIG: Dict[str, str] = { + 'esp32': '-f board/esp32-wrover-kit-3.3v.cfg', + 'esp32s2': '-f board/esp32s2-kaluga-1.cfg', + 'esp32c3': '-f board/esp32c3-builtin.cfg', + 'esp32s3': '-f board/esp32s3-builtin.cfg', +} diff --git a/tools/idf_py_actions/core_ext.py b/tools/idf_py_actions/core_ext.py index 074c41316f..aa085c74a5 100644 --- a/tools/idf_py_actions/core_ext.py +++ b/tools/idf_py_actions/core_ext.py @@ -18,8 +18,8 @@ from click.core import Context from idf_py_actions.constants import GENERATORS, PREVIEW_TARGETS, SUPPORTED_TARGETS, URL_TO_DOC from idf_py_actions.errors import FatalError from idf_py_actions.global_options import global_options -from idf_py_actions.tools import (PropertyDict, TargetChoice, ensure_build_directory, get_target, idf_version, - merge_action_lists, print_hints, realpath, run_target) +from idf_py_actions.tools import (PropertyDict, TargetChoice, ensure_build_directory, generate_hints, get_target, + idf_version, merge_action_lists, realpath, run_target, yellow_print) def action_extensions(base_actions: Dict, project_path: str) -> Any: @@ -30,25 +30,27 @@ def action_extensions(base_actions: Dict, project_path: str) -> Any: Calls ensure_build_directory() which will run cmake to generate a build directory (with the specified generator) as needed. """ - hints = not args.no_hints ensure_build_directory(args, ctx.info_name) - run_target(target_name, args, force_progression=GENERATORS[args.generator].get('force_progression', False), hints=hints) + run_target(target_name, args, force_progression=GENERATORS[args.generator].get('force_progression', False)) - def size_target(target_name: str, ctx: Context, args: PropertyDict) -> None: + def size_target(target_name: str, ctx: Context, args: PropertyDict, output_format: str, output_file: str) -> None: """ Builds the app and then executes a size-related target passed in 'target_name'. `tool_error_handler` handler is used to suppress errors during the build, so size action can run even in case of overflow. - """ def tool_error_handler(e: int, stdout: str, stderr: str) -> None: - print_hints(stdout, stderr) + for hint in generate_hints(stdout, stderr): + yellow_print(hint) + + os.environ['SIZE_OUTPUT_FORMAT'] = output_format + if output_file: + os.environ['SIZE_OUTPUT_FILE'] = os.path.abspath(output_file) - hints = not args.no_hints ensure_build_directory(args, ctx.info_name) run_target('all', args, force_progression=GENERATORS[args.generator].get('force_progression', False), - custom_error_handler=tool_error_handler, hints=hints) + custom_error_handler=tool_error_handler) run_target(target_name, args) def list_build_system_targets(target_name: str, ctx: Context, args: PropertyDict) -> None: @@ -338,6 +340,16 @@ def action_extensions(base_actions: Dict, project_path: str) -> Any: 'global_action_callbacks': [validate_root_options], } + # 'default' is introduced instead of simply setting 'text' as the default so that we know + # if the user explicitly specified the format or not. If the format is not specified, then + # the legacy OUTPUT_JSON CMake variable will be taken into account. + size_options = [{'names': ['--format', 'output_format'], + 'type': click.Choice(['default', 'text', 'csv', 'json']), + 'help': 'Specify output format: text (same as "default"), csv or json.', + 'default': 'default'}, + {'names': ['--output-file', 'output_file'], + 'help': 'Print output to the specified file instead of to the standard output'}] + build_actions = { 'actions': { 'all': { @@ -390,17 +402,17 @@ def action_extensions(base_actions: Dict, project_path: str) -> Any: 'size': { 'callback': size_target, 'help': 'Print basic size information about the app.', - 'options': global_options, + 'options': global_options + size_options, }, 'size-components': { 'callback': size_target, 'help': 'Print per-component size information.', - 'options': global_options, + 'options': global_options + size_options, }, 'size-files': { 'callback': size_target, 'help': 'Print per-source-file size information.', - 'options': global_options, + 'options': global_options + size_options, }, 'bootloader': { 'callback': build_target, diff --git a/tools/idf_py_actions/debug_ext.py b/tools/idf_py_actions/debug_ext.py index 53bdfb3d36..395cd61564 100644 --- a/tools/idf_py_actions/debug_ext.py +++ b/tools/idf_py_actions/debug_ext.py @@ -4,18 +4,65 @@ import json import os import re import shlex +import shutil import subprocess import sys import threading import time +from textwrap import indent from threading import Thread from typing import Any, Dict, List, Optional from click.core import Context +from idf_py_actions.constants import OPENOCD_TAGET_CONFIG, OPENOCD_TAGET_CONFIG_DEFAULT from idf_py_actions.errors import FatalError from idf_py_actions.tools import PropertyDict, ensure_build_directory PYTHON = sys.executable +ESP_ROM_INFO_FILE = 'roms.json' +GDBINIT_PYTHON_TEMPLATE = ''' +# Add Python GDB extensions +python +import sys +sys.path = {sys_path} +import freertos_gdb +end +''' +GDBINIT_PYTHON_NOT_SUPPORTED = ''' +# Python scripting is not supported in this copy of GDB. +# Please make sure that your Python distribution contains Python shared library. +''' +GDBINIT_BOOTLOADER_ADD_SYMBOLS = ''' +# Load bootloader symbols +set confirm off + add-symbol-file {boot_elf} +set confirm on +''' +GDBINIT_BOOTLOADER_NOT_FOUND = ''' +# Bootloader elf was not found +''' +GDBINIT_APP_ADD_SYMBOLS = ''' +# Load application file +file {app_elf} +''' +GDBINIT_CONNECT = ''' +# Connect to the default openocd-esp port and break on app_main() +target remote :3333 +monitor reset halt +flushregs +thbreak app_main +continue +''' +GDBINIT_MAIN = ''' +source {py_extensions} +source {symbols} +source {connect} +''' + + +def get_openocd_arguments(target: str) -> str: + default_args = OPENOCD_TAGET_CONFIG_DEFAULT.format(target=target) + return str(OPENOCD_TAGET_CONFIG.get(target, default_args)) def action_extensions(base_actions: Dict, project_path: str) -> Dict: @@ -78,10 +125,8 @@ def action_extensions(base_actions: Dict, project_path: str) -> Dict: time.sleep(0.1) else: p.kill() - if target + '_outfile_name' in processes: - if target == 'openocd': - print(_check_for_common_openocd_issues(processes[target + '_outfile_name'], print_all=False)) - os.unlink(processes[target + '_outfile_name']) + if target + '_outfile_name' in processes and target == 'openocd': + print(_check_for_common_openocd_issues(processes[target + '_outfile_name'], print_all=False)) except Exception as e: print(e) print('Failed to close/kill {}'.format(target)) @@ -91,22 +136,111 @@ def action_extensions(base_actions: Dict, project_path: str) -> Dict: # execute simple python command to check is it supported return subprocess.run([gdb, '--batch-silent', '--ex', 'python import os'], stderr=subprocess.DEVNULL).returncode == 0 - def create_local_gdbinit(gdb: str, gdbinit: str, elf_file: str) -> None: - with open(gdbinit, 'w') as f: + def get_normalized_path(path: str) -> str: + if os.name == 'nt': + return os.path.normpath(path).replace('\\','\\\\') + return path + + def get_rom_if_condition_str(date_addr: int, date_str: str) -> str: + r = [] + for i in range(0, len(date_str), 4): + value = hex(int.from_bytes(bytes(date_str[i:i + 4], 'utf-8'), 'little')) + r.append(f'(*(int*) {hex(date_addr + i)}) == {value}') + return 'if ' + ' && '.join(r) + + def generate_gdbinit_rom_add_symbols(target: str) -> str: + base_ident = ' ' + rom_elfs_dir = os.getenv('ESP_ROM_ELF_DIR') + if not rom_elfs_dir: + raise FatalError('ESP_ROM_ELF_DIR environment variable is not defined. Please try to run IDF "install" and "export" scripts.') + with open(os.path.join(os.path.dirname(os.path.realpath(__file__)), ESP_ROM_INFO_FILE), 'r') as f: + roms = json.load(f) + if target not in roms: + msg_body = f'Target "{target}" was not found in "{ESP_ROM_INFO_FILE}". Please check IDF integrity.' + if os.getenv('ESP_IDF_GDB_TESTING'): + raise FatalError(msg_body) + print(f'Warning: {msg_body}') + return f'# {msg_body}' + r = ['', f'# Load {target} ROM ELF symbols'] + is_one_revision = len(roms[target]) == 1 + if not is_one_revision: + r.append('define target hookpost-remote') + r.append('set confirm off') + # Workaround for reading ROM data on xtensa chips + # This should be deleted after the new openocd-esp release (newer than v0.11.0-esp32-20220706) + xtensa_chips = ['esp32', 'esp32s2', 'esp32s3'] + if target in xtensa_chips: + r.append('monitor xtensa set_permissive 1') + # Since GDB does not have 'else if' statement than we use nested 'if..else' instead. + for i, k in enumerate(roms[target], 1): + indent_str = base_ident * i + rom_file = get_normalized_path(os.path.join(rom_elfs_dir, f'{target}_rev{k["rev"]}_rom.elf')) + build_date_addr = int(k['build_date_str_addr'], base=16) + r.append(indent(f'# if $_streq((char *) {hex(build_date_addr)}, "{k["build_date_str"]}")', indent_str)) + r.append(indent(get_rom_if_condition_str(build_date_addr, k['build_date_str']), indent_str)) + r.append(indent(f'add-symbol-file {rom_file}', indent_str + base_ident)) + r.append(indent('else', indent_str)) + if i == len(roms[target]): + # In case no one known ROM ELF fits - print error and exit with error code 1 + indent_str += base_ident + msg_body = f'unknown {target} ROM revision.' + if os.getenv('ESP_IDF_GDB_TESTING'): + r.append(indent(f'echo Error: {msg_body}\\n', indent_str)) + r.append(indent('quit 1', indent_str)) + else: + r.append(indent(f'echo Warning: {msg_body}\\n', indent_str)) + # Close 'else' operators + for i in range(len(roms[target]), 0, -1): + r.append(indent('end', base_ident * i)) + if target in xtensa_chips: + r.append('monitor xtensa set_permissive 0') + r.append('set confirm on') + if not is_one_revision: + r.append('end') + r.append('') + return os.linesep.join(r) + raise FatalError(f'{ESP_ROM_INFO_FILE} file not found. Please check IDF integrity.') + + def generate_gdbinit_files(gdb: str, gdbinit: Optional[str], project_desc: Dict[str, Any]) -> None: + app_elf = get_normalized_path(os.path.join(project_desc['build_dir'], project_desc['app_elf'])) + if not os.path.exists(app_elf): + raise FatalError('ELF file not found. You need to build & flash the project before running debug targets') + + # Recreate empty 'gdbinit' directory + gdbinit_dir = os.path.join(project_desc['build_dir'], 'gdbinit') + if os.path.isfile(gdbinit_dir): + os.remove(gdbinit_dir) + elif os.path.isdir(gdbinit_dir): + shutil.rmtree(gdbinit_dir) + os.mkdir(gdbinit_dir) + + # Prepare gdbinit for Python GDB extensions import + py_extensions = os.path.join(gdbinit_dir, 'py_extensions') + with open(py_extensions, 'w') as f: if is_gdb_with_python(gdb): - f.write('python\n') - f.write('import sys\n') - f.write(f'sys.path = {sys.path}\n') - f.write('import freertos_gdb\n') - f.write('end\n') - if os.name == 'nt': - elf_file = elf_file.replace('\\','\\\\') - f.write('file {}\n'.format(elf_file)) - f.write('target remote :3333\n') - f.write('mon reset halt\n') - f.write('flushregs\n') - f.write('thb app_main\n') - f.write('c\n') + f.write(GDBINIT_PYTHON_TEMPLATE.format(sys_path=sys.path)) + else: + f.write(GDBINIT_PYTHON_NOT_SUPPORTED) + + # Prepare gdbinit for related ELFs symbols load + symbols = os.path.join(gdbinit_dir, 'symbols') + with open(symbols, 'w') as f: + boot_elf = get_normalized_path(project_desc['bootloader_elf']) if 'bootloader_elf' in project_desc else None + if boot_elf and os.path.exists(boot_elf): + f.write(GDBINIT_BOOTLOADER_ADD_SYMBOLS.format(boot_elf=boot_elf)) + else: + f.write(GDBINIT_BOOTLOADER_NOT_FOUND) + f.write(generate_gdbinit_rom_add_symbols(project_desc['target'])) + f.write(GDBINIT_APP_ADD_SYMBOLS.format(app_elf=app_elf)) + + # Generate the gdbinit for target connect if no custom gdbinit is present + if not gdbinit: + gdbinit = os.path.join(gdbinit_dir, 'connect') + with open(gdbinit, 'w') as f: + f.write(GDBINIT_CONNECT) + + with open(os.path.join(gdbinit_dir, 'gdbinit'), 'w') as f: + f.write(GDBINIT_MAIN.format(py_extensions=py_extensions, symbols=symbols, connect=gdbinit)) def debug_cleanup() -> None: print('cleaning up debug targets') @@ -156,12 +290,6 @@ def action_extensions(base_actions: Dict, project_path: str) -> Dict: """ Execute openocd as external tool """ - OPENOCD_TAGET_CONFIG = { - 'esp32': '-f board/esp32-wrover-kit-3.3v.cfg', - 'esp32s2': '-f board/esp32s2-kaluga-1.cfg', - 'esp32c3': '-f board/esp32c3-builtin.cfg', - 'esp32s3': '-f board/esp32s3-builtin.cfg', - } if os.getenv('OPENOCD_SCRIPTS') is None: raise FatalError('OPENOCD_SCRIPTS not found in the environment: Please run export.sh/export.bat', ctx) openocd_arguments = os.getenv('OPENOCD_COMMANDS') if openocd_commands is None else openocd_commands @@ -169,8 +297,7 @@ def action_extensions(base_actions: Dict, project_path: str) -> Dict: if openocd_arguments is None: # use default value if commands not defined in the environment nor command line target = project_desc['target'] - default_args = '-f interface/ftdi/esp32_devkitj_v1.cfg -f target/{}.cfg'.format(target) - openocd_arguments = OPENOCD_TAGET_CONFIG.get(target, default_args) + openocd_arguments = get_openocd_arguments(target) print('Note: OpenOCD cfg not found (via env variable OPENOCD_COMMANDS nor as a --openocd-commands argument)\n' 'OpenOCD arguments default to: "{}"'.format(openocd_arguments)) # script directory is taken from the environment by OpenOCD, update only if command line arguments to override @@ -179,7 +306,7 @@ def action_extensions(base_actions: Dict, project_path: str) -> Dict: local_dir = project_desc['build_dir'] args = ['openocd'] + shlex.split(openocd_arguments) openocd_out_name = os.path.join(local_dir, OPENOCD_OUT_FILE) - openocd_out = open(openocd_out_name, 'a+') + openocd_out = open(openocd_out_name, 'w') try: process = subprocess.Popen(args, stdout=openocd_out, stderr=subprocess.STDOUT, bufsize=1) except Exception as e: @@ -191,7 +318,8 @@ def action_extensions(base_actions: Dict, project_path: str) -> Dict: processes['openocd_outfile_name'] = openocd_out_name print('OpenOCD started as a background task {}'.format(process.pid)) - def get_gdb_args(gdbinit: str, project_desc: Dict[str, Any]) -> List: + def get_gdb_args(project_desc: Dict[str, Any]) -> List: + gdbinit = os.path.join(project_desc['build_dir'], 'gdbinit', 'gdbinit') args = ['-x={}'.format(gdbinit)] debug_prefix_gdbinit = project_desc.get('debug_prefix_map_gdbinit') if debug_prefix_gdbinit: @@ -205,16 +333,14 @@ def action_extensions(base_actions: Dict, project_path: str) -> Dict: project_desc = get_project_desc(args, ctx) local_dir = project_desc['build_dir'] gdb = project_desc['monitor_toolprefix'] + 'gdb' - if gdbinit is None: - gdbinit = os.path.join(local_dir, 'gdbinit') - create_local_gdbinit(gdb, gdbinit, os.path.join(args.build_dir, project_desc['app_elf'])) + generate_gdbinit_files(gdb, gdbinit, project_desc) # this is a workaround for gdbgui # gdbgui is using shlex.split for the --gdb-args option. When the input is: # - '"-x=foo -x=bar"', would return ['foo bar'] # - '-x=foo', would return ['-x', 'foo'] and mess up the former option '--gdb-args' # so for one item, use extra double quotes. for more items, use no extra double quotes. - gdb_args_list = get_gdb_args(gdbinit, project_desc) + gdb_args_list = get_gdb_args(project_desc) gdb_args = '"{}"'.format(' '.join(gdb_args_list)) if len(gdb_args_list) == 1 else ' '.join(gdb_args_list) args = ['gdbgui', '-g', gdb, '--gdb-args', gdb_args] print(args) @@ -222,7 +348,7 @@ def action_extensions(base_actions: Dict, project_path: str) -> Dict: if gdbgui_port is not None: args += ['--port', gdbgui_port] gdbgui_out_name = os.path.join(local_dir, GDBGUI_OUT_FILE) - gdbgui_out = open(gdbgui_out_name, 'a+') + gdbgui_out = open(gdbgui_out_name, 'w') env = os.environ.copy() # The only known solution for https://github.com/cs01/gdbgui/issues/359 is to set the following environment # variable. The greenlet package cannot be downgraded for compatibility with other requirements (gdbgui, @@ -276,9 +402,9 @@ def action_extensions(base_actions: Dict, project_path: str) -> Dict: """ Synchronous GDB target with text ui mode """ - gdb(action, ctx, args, 1, gdbinit, require_openocd) + gdb(action, ctx, args, False, 1, gdbinit, require_openocd) - def gdb(action: str, ctx: Context, args: PropertyDict, gdb_tui: Optional[int], gdbinit: Optional[str], require_openocd: bool) -> None: + def gdb(action: str, ctx: Context, args: PropertyDict, batch: bool, gdb_tui: Optional[int], gdbinit: Optional[str], require_openocd: bool) -> None: """ Synchronous GDB target """ @@ -286,18 +412,13 @@ def action_extensions(base_actions: Dict, project_path: str) -> Dict: watch_openocd.start() processes['threads_to_join'].append(watch_openocd) project_desc = get_project_desc(args, ctx) - - elf_file = os.path.join(args.build_dir, project_desc['app_elf']) - if not os.path.exists(elf_file): - raise FatalError('ELF file not found. You need to build & flash the project before running debug targets', ctx) gdb = project_desc['monitor_toolprefix'] + 'gdb' - local_dir = project_desc['build_dir'] - if gdbinit is None: - gdbinit = os.path.join(local_dir, 'gdbinit') - create_local_gdbinit(gdb, gdbinit, elf_file) - args = [gdb, *get_gdb_args(gdbinit, project_desc)] + generate_gdbinit_files(gdb, gdbinit, project_desc) + args = [gdb, *get_gdb_args(project_desc)] if gdb_tui is not None: args += ['-tui'] + if batch: + args += ['--batch'] t = Thread(target=run_gdb, args=(args,)) t.start() while True: @@ -354,12 +475,17 @@ def action_extensions(base_actions: Dict, project_path: str) -> Dict: 'callback': gdb, 'help': 'Run the GDB.', 'options': [ + { + 'names': ['--batch'], + 'help': ('exit after processing gdbinit.\n'), + 'hidden': True, + 'is_flag': True, + 'default': False, + }, { 'names': ['--gdb-tui', '--gdb_tui'], - 'help': - ('run gdb in TUI mode\n'), - 'default': - None, + 'help': ('run gdb in TUI mode\n'), + 'default': None, }, gdbinit, fail_if_openocd_failed ], 'order_dependencies': ['all', 'flash'], diff --git a/tools/idf_py_actions/hints.yml b/tools/idf_py_actions/hints.yml index d46b191efe..482b5c66e7 100644 --- a/tools/idf_py_actions/hints.yml +++ b/tools/idf_py_actions/hints.yml @@ -1,44 +1,116 @@ # - # re: Regular expression of error to search -# hint: Message of the hint. Optionally, it is possible to use '{}' at the place where the matched group from 're' should be inserted. This requires 'match_to_output: True'. +# hint: The message of the hint. Optionally, it is possible to use '{}' at the place where the matched group from 're' should be inserted. This requires 'match_to_output: True'. You can use variables with hint messages. For this, you need to add variables and "{}" in a place where you want to put your hint variable, but you can't use 'match_to_output' with variables. # match_to_output: (False by default) see the description of 'hint'. - - +# variables: +# - +# re_variables: [set variable for regular expression] +# hint_variables: [set variable for hint] # Rules to write regex for hints on how to resolve errors # - Do not use more than one whitespace in a row. The script automatically merges several whitespaces into one when capturing output # - Do not use \n in your regex. They are all automatically deletes by the script when capturing output +# +# example of using hints: +# - +# re: "Error: header {} is missing" (you can use '{1} ... {1}' placeholders in 'hint' and 're', so that you don't have to repeat the same variables, you can use 'hint: 'The {0} (functions/types/macros prefixed with '{1}') has been made into a private API. If users still require usage of the {0} (though this is not recommended), it can be included via #include "esp_private/{2}.h".' in this file as an example) +# hint: "header {} is missing, you need to add dependency on component {}" +# variables: +# - +# re_variables: [Q] +# hint_variables: [A, B] +# - +# re_variables: [W] +# hint_variables: [C, D] +# - +# re_variables: [R] +# hint_variables: [E, F] +# +# that example will replace this : +# - +# re: "Error: header Q is missing" +# hint: "header A is missing, you need to add dependency on component B" +# - +# re: Error: header W is missing" +# hint: "header C is missing, you need to add dependency on component D" +# - +# re: Error: header R is missing" +# hint: "header E is missing, you need to add dependency on component F" - - re: "error: implicit declaration of function 'bootloader_common_get_reset_reason'" - hint: "'bootloader_common_get_reset_reason()' has been removed. Please use the function 'esp_rom_get_reset_reason()' in the ROM component." + re: "warning: passing argument 1 of 'esp_secure_boot_read_key_digests' from incompatible pointer type" + hint: "The parameter type of the function esp_secure_boot_read_key_digests() has been changed from ets_secure_boot_key_digests_t* to esp_secure_boot_key_digests_t*." + +- + re: "error: implicit declaration of function '{}'" + hint: "Function '{}' has been removed. Please use the function {}." + variables: + - + re_variables: ['bootloader_common_get_reset_reason'] + hint_variables: ['bootloader_common_get_reset_reason()', "'esp_rom_get_reset_reason()' in the ROM component"] + - + re_variables: ['esp_efuse_get_chip_ver'] + hint_variables: ['esp_efuse_get_chip_ver()', 'efuse_hal_get_major_chip_version()', 'efuse_hal_get_minor_chip_version() or efuse_hal_chip_revision() instead'] + - + re_variables: ['(esp_spiram_get_chip_size|esp_spiram_get_size)'] + hint_variables: ['esp_spiram_get_chip_size and esp_spiram_get_size', 'esp_psram_get_size()'] - re: "error: implicit declaration of function 'esp_secure_boot_verify_sbv2_signature_block|esp_secure_boot_verify_rsa_signature_block'" - hint: "'esp_secure_boot_verify_sbv2_signature_block()' and 'esp_secure_boot_verify_rsa_signature_block()' and has been made private and are no longer available." + hint: "'esp_secure_boot_verify_sbv2_signature_block()' and 'esp_secure_boot_verify_rsa_signature_block()' and have been made private and are no longer available." - - re: "error: implicit declaration of function 'esp_cpu_ccount_t'" - hint: "Use esp_cpu_cycle_count_t defined in esp_cpu.h instead of esp_cpu_ccount_t." + re: "error: implicit declaration of function '{}'" + hint: '{0}.h header file is not included by esp_system.h anymore. It shall then be manually included with #include "{0}.h"' + variables: + - + re_variables: ['(esp_random|esp_fill_random)'] + hint_variables: ['esp_random'] + - + re_variables: ['(esp_base_mac_addr_(s|g)et|esp_efuse_mac_get_(custom|default)|esp_read_mac|esp_derive_local_mac)'] + hint_variables: ['esp_mac'] + - + re_variables: ['esp_chip_info'] + hint_variables: ['esp_chip_info'] - - re: "error: implicit declaration of function 'esp_cpu_(g|s)et_ccount'" - hint: "Use esp_cpu_{}et_cycle_count() defined in esp_cpu.h instead." + re: "fatal error: (spiram.h|esp_spiram.h): No such file or directory" + hint: "{} was removed. Include esp_psram.h instead. Make sure to also add esp_psram as a dependency in your CMakeLists.txt file." match_to_output: True - - re: "fatal error: (soc/cpu.h|compare_set.h): No such file or directory" - hint: "{} was removed. Include and use the API function provided by esp_cpu.h instead." - match_to_output: True + re: "error: implicit declaration of function '{}'" + hint: "Use {} defined in esp_cpu.h instead of {}." + variables: + - + re_variables: ['esp_cpu_ccount_t'] + hint_variables: ['esp_cpu_cycle_count_t', 'esp_cpu_ccount_t'] + - + re_variables: ['esp_cpu_get_ccount'] + hint_variables: ['esp_cpu_get_cycle_count()', 'esp_cpu_get_ccount'] + - + re_variables: ['esp_cpu_set_ccount'] + hint_variables: ['esp_cpu_set_cycle_count()', 'esp_cpu_set_ccount'] - - re: "fatal error: (esp_intr.h): No such file or directory" - hint: "{} was removed. Include esp_intr_alloc.h instead." - match_to_output: True + re: "fatal error: {}: No such file or directory" + hint: "{} was removed. Include {} instead." + variables: + - + re_variables: ['esp_intr.h'] + hint_variables: ['esp_intr.h', 'esp_intr_alloc.h'] + - + re_variables: ['soc/cpu.h'] + hint_variables: ['soc/cpu.h', 'and use the API function provided by esp_cpu.h'] + - + re_variables: ['compare_set.h'] + hint_variables: ['compare_set.h', 'and use the API function provided by esp_cpu.h'] + - + re_variables: ['esp_panic.h'] + hint_variables: ['esp_panic.h', 'use functionalities provided in esp_debug_helpers.h'] - - re: "fatal error: (esp_panic.h): No such file or directory" - hint: "{} was made private. Use functionalities provided in esp_debug_helpers.h instead." - match_to_output: True + re: "error: implicit declaration of function 'esp_int_wdt_\\w+'" + hint: 'The Interrupt Watchdog API has been made private, it shall not be used anymore. You can still force its inclusion with #include "esp_private/esp_int_wdt.h" (not recommended)' - re: "fatal error: soc/(spinlock.h|clk_ctrl_os.h|rtc_wdt.h): No such file or directory" @@ -51,27 +123,57 @@ match_to_output: True - - re: "error: implicit declaration of function '(\\w+)'" - hint: "Maybe you forgot to import {} library(s) in header file or add the necessary REQURIES component. Try to add missing libraries to your project header file or check idf_component_register(REQUIRES ...) section in your component CmakeList.txt file. For more information run 'idf.py docs -sp api-guides/build-system.html'." + re: "error: unknown type name '(portTickType|xTaskHandle|xQueueHandle|xSemaphoreHandle|xQueueSetHandle|xQueueSetMemberHandle|xTimeOutType|xMemoryRegion|xTaskParameters|xTaskStatusType|xTimerHandle|xCoRoutineHandle|pdTASK_HOOK_CODE|tmrTIMER_CALLBACK|pdTASK_CODE|xListItem|xList)'" + hint: "You are maybe using pre FreeRTOS V8.0.0 data types. The backward compatibility of such data types is no longer enabled by default. Please turn on CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY explicitly to use such data types." match_to_output: True - - re: "fatal error: esp32\\w*\\/clk.h: No such file or directory" - hint: "The ESP Clock API (functions/types/macros prefixed with 'esp_clk') has been made into a private API. If users still require usage of the ESP Clock API (though this is not recommended), it can be included via '#include \"esp_private/esp_clk.h\"'." + re: "error: 'portTICK_RATE_MS' undeclared" + hint: "You are maybe using pre FreeRTOS V8.0.0 APIs. The backward compatibility of such APIs is no longer enabled by default. Please turn on CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY explicitly to use such APIs." + match_to_output: True - - re: "fatal error: esp32\\w*\\/cache_err_int.h: No such file or directory" - hint: "The Cache Error Interrupt API (functions/types/macros prefixed with 'esp_cache_err') has been made into a private API. If users still require usage of the Cache Error Interrupt API (though this is not recommended), it can be included via '#include \"esp_private/cache_err_int.h\"'" + re: "error: implicit declaration of function '(eTaskStateGet|pcTaskGetTaskName|pcTimerGetTimerName|pcQueueGetQueueName|vTaskGetTaskInfo|xTaskGetIdleRunTimeCounter)'" + hint: "You are maybe using pre FreeRTOS V8.0.0 APIs. The backward compatibility of such APIs is no longer enabled by default. Please turn on CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY explicitly to use such APIs." + match_to_output: True +- + re: "error: unknown type name 'TaskSnapshot_t'" + hint: "The header file task_snapshot.h is no longer included as part of freertos/task.h. Users need to include freertos/task_snapshot.h explicitly." + match_to_output: True +- + re: "error: implicit declaration of function '(pxTaskGetNext|vTaskGetSnapshot|uxTaskGetSnapshotAll)'" + hint: "The header file task_snapshot.h is no longer included as part of freertos/task.h. Users need to include freertos/task_snapshot.h explicitly." + match_to_output: True +- + re: "error: implicit declaration of function '(portENTER_CRITICAL_NESTED|portEXIT_CRITICAL_NESTED|vPortCPUInitializeMutex|vPortCPUAcquireMutex|vPortCPUAcquireMutexTimeout|vPortCPUReleaseMutex)'" + hint: "The header file portmacro_deprecated.h has been removed. Users should refer the migration guide for alternative functions." + match_to_output: True - - re: "fatal error: brownout.h: No such file or directory" - hint: "The Brownout API (functions/types/macros prefixed with 'esp_brownout') has been made into a private API. If users still require usage of the Brownout API (though this is not recommended), it can be included via '#include \"esp_private/brownout.h\"'." + re: "fatal error: {}.h: No such file or directory" + hint: 'The {0} (functions/types/macros prefixed with "{1}") has been made into a private API. If users still require usage of the {0} (though this is not recommended), it can be included via #include "esp_private/{2}.h".' + variables: + - + re_variables: ['esp32\\w*\\/clk'] + hint_variables: ['ESP Clock API', 'esp_clk', 'esp_clk'] + - + re_variables: ['esp32\\w*\\/cache_err_int'] + hint_variables: ['Cache Error Interrupt API', 'esp_cache_err', 'cache_err_int'] + - + re_variables: ['brownout'] + hint_variables: ['Brownout API', 'esp_brownout', 'brownout'] + - + re_variables: ['trax'] + hint_variables: ['Trax API', 'trax_', 'trax'] + - + re_variables: ['eh_frame_parser'] + hint_variables: ['Backtrace Parser API', 'eh_frame_parser', 'eh_frame_parser'] - - re: "fatal error: trax.h: No such file or directory" - hint: "The Trax API (functions/types/macros prefixed with 'trax_') has been made into a private API. If users still require usage of the Trax API (though this is not recommended), it can be included via '#include \"esp_private/trax.h\"'." + re: "fatal error: esp_adc_cal.h: No such file or directory" + hint: "``esp_adc_cal`` component is no longer supported. New adc calibration driver is in ``esp_adc``. Legacy adc calibration driver has been moved into ``esp_adc`` component. To use legacy ``esp_adc_cal`` driver APIs, you should add ``esp_adc`` component to the list of component requirements in CMakeLists.txt. For more information run 'idf.py docs -sp migration-guides/release-5.x/peripherals.html'." - - re: "fatal error: [\\w/]+\\.h: No such file or directory" - hint: "Please check if you've specified all component dependencies with 'idf_component_register(REQUIRES ...)'. If the component is not present then it should be added by the IDF Component Manager. For more information run 'idf.py docs -sp api-guides/build-system.html'." + re: "fatal error: .*atca_mbedtls_wrap\\.h: No such file or directory" + hint: "To use CONFIG_ESP_TLS_USE_SECURE_ELEMENT option, please install `esp-cryptoauthlib` using 'idf.py add-dependency espressif/esp-cryptoauthlib'" - re: "The CMAKE_[A-Z]+_COMPILER: [\\w+-]+ is not a full path and was not found in the PATH\\." @@ -85,6 +187,10 @@ re: "CMake Error at .* \\(message\\): Could not create symbolic link for: error\\.c --> Cannot create a file when that file already exists\\." hint: "Run 'idf.py fullclean' and try the build again." +- + re: "CMake Error at .* \\(message\\): Directory specified in EXTRA_COMPONENT_DIRS doesn't exist: \\/?.*\\/examples\\/common_components\\/.*" + hint: "The component with path specified in the EXTRA_COMPONENT_DIRS variable has been moved to IDF component manager (or has been removed).\nPlease look out for component in 'https://components.espressif.com' and add using 'idf.py add-dependency' command.\nRefer to the migration guide for more details." + - re: "ImportError: bad magic number in 'kconfiglib':" hint: "Run 'idf.py python-clean', and try again" @@ -98,9 +204,27 @@ hint: "Projects using target_link_libraries with project_elf explicitly and custom CMake projects must specify PRIVATE, PUBLIC or INTERFACE arguments." - - re: "format '([^']+)' expects argument of type '((unsigned )?int|long)', but argument (\\w+) has type '([u]?int32_t)'( {aka '([^']+)'})?" + re: "format '([^']+)' expects argument of type '((unsigned )?int|long)', but argument (\\w+) has type '([u]?int32_t)'( \\{aka '([^']+)'\\})?" hint: "The issue is better to resolve by replacing format specifiers to 'PRI'-family macros (include header file)." - re: "Failed to resolve component 'esp_ipc'" hint: "IPC component has been moved to esp_system. Any `REQUIRES esp_ipc` can simply be deleted as esp_system is REQUIRED by default." + +- + re: "error: invalid use of incomplete typedef 'esp_tls_t'" + hint: "The struct 'esp_tls_t' has now been made private - its elements can be only be accessed/modified through respective getter/setter functions. Please refer to the migration guide for more information." + +- + re: "error: enumeration value 'HTTP_EVENT_REDIRECT' not handled in switch" + hint: "The event handler, specified in the 'event_handler' element, of the 'esp_http_client_config_t' struct now needs to handle the new 'HTTP_EVENT_REDIRECT' event case." + +- + re: "Failed to resolve component '(?!esp_ipc)(\\w+)'" + hint: "The component {} has been moved to the IDF component manager or has been removed and refactored into some other component.\nPlease look out for component in 'https://components.espressif.com' and add using 'idf.py add-dependency' command.\nRefer to the migration guide for more details." + match_to_output: True + +- + re: "fatal error: (esp_rom_tjpgd.h): No such file or directory" + hint: "{} was removed. Please use esp_jpeg component from IDF component manager instead.\nPlease look out for component in 'https://components.espressif.com' and add using 'idf.py add-dependency' command.\nRefer to the migration guide for more details." + match_to_output: True diff --git a/tools/idf_py_actions/roms.json b/tools/idf_py_actions/roms.json new file mode 100644 index 0000000000..16df8b7c18 --- /dev/null +++ b/tools/idf_py_actions/roms.json @@ -0,0 +1,47 @@ +{ + "esp32": [ + { + "rev": 0, + "build_date_str_addr": "0x3ff9ea80", + "build_date_str": "Jun 8 2016" + }, + { + "rev": 3, + "build_date_str_addr": "0x3ff9e986", + "build_date_str": "Jul 29 2019" + } + ], + "esp32s2": [ + { + "rev": 0, + "build_date_str_addr": "0x3ffaf34b", + "build_date_str": "Oct 25 2019" + } + ], + "esp32s3": [ + { + "rev": 0, + "build_date_str_addr": "0x3ff194ad", + "build_date_str": "Mar 1 2021" + } + ], + "esp32c2": [ + { + "rev": 0, + "build_date_str_addr": "0x3ff47874", + "build_date_str": "Jan 27 2022" + } + ], + "esp32c3": [ + { + "rev": 0, + "build_date_str_addr": "0x3ff1b878", + "build_date_str": "Sep 18 2020" + }, + { + "rev": 3, + "build_date_str_addr": "0x3ff1a374", + "build_date_str": "Feb 7 2021" + } + ] +} diff --git a/tools/idf_py_actions/roms_schema.json b/tools/idf_py_actions/roms_schema.json new file mode 100644 index 0000000000..b4ab4c5f47 --- /dev/null +++ b/tools/idf_py_actions/roms_schema.json @@ -0,0 +1,29 @@ +{ + "$schema": "http://json-schema.org/draft-07/schema#", + "type": "object", + "patternProperties": { + "^esp32.*$": { + "anyOf": [ + { + "type": "array", + "items": { + "type": "object", + "properties": { + "rev": { + "type": "integer", + "minimum": 0, + "description": "Chip revision/ROM revision number" + }, + "build_date_str_addr": { + "type": "string", + "description": "The ROM build date string address to compare between ROM elf file and chip ROM memory", + "pattern": "^0x[0-9a-fA-F]{8}$" + } + }, + "required": ["rev", "build_date_str_addr"] + } + } + ] + } + } +} diff --git a/tools/idf_py_actions/serial_ext.py b/tools/idf_py_actions/serial_ext.py index d44c2f5f60..51dd9f6ca6 100644 --- a/tools/idf_py_actions/serial_ext.py +++ b/tools/idf_py_actions/serial_ext.py @@ -154,7 +154,7 @@ def action_extensions(base_actions: Dict, project_path: str) -> Dict: idf_py = [PYTHON] + _get_commandline_options(ctx) # commands to re-run idf.py monitor_args += ['-m', ' '.join("'%s'" % a for a in idf_py)] - hints = not args.no_hints + hints = False # Temporarily disabled because of https://github.com/espressif/esp-idf/issues/9610 RunTool('idf_monitor', monitor_args, args.project_dir, build_dir=args.build_dir, hints=hints, interactive=True)() @@ -175,7 +175,7 @@ def action_extensions(base_actions: Dict, project_path: str) -> Dict: ensure_build_directory(args, ctx.info_name) esptool_args = _get_esptool_args(args) esptool_args += ['erase_flash'] - RunTool('esptool.py', esptool_args, args.build_dir)() + RunTool('esptool.py', esptool_args, args.build_dir, hints=not args.no_hints)() def global_callback(ctx: click.core.Context, global_args: Dict, tasks: PropertyDict) -> None: encryption = any([task.name in ('encrypted-flash', 'encrypted-app-flash') for task in tasks]) diff --git a/tools/idf_py_actions/tools.py b/tools/idf_py_actions/tools.py index 0020818758..8d0cdc2489 100644 --- a/tools/idf_py_actions/tools.py +++ b/tools/idf_py_actions/tools.py @@ -8,15 +8,24 @@ import sys from asyncio.subprocess import Process from io import open from types import FunctionType -from typing import Any, Dict, List, Optional, TextIO, Tuple, Union +from typing import Any, Dict, Generator, List, Match, Optional, TextIO, Tuple, Union import click import yaml -from idf_monitor_base.output_helpers import yellow_print from .constants import GENERATORS from .errors import FatalError +# Name of the program, normally 'idf.py'. +# Can be overridden from idf.bat using IDF_PY_PROGRAM_NAME +PROG = os.getenv('IDF_PY_PROGRAM_NAME', 'idf.py') + +# environment variable used during click shell completion run +SHELL_COMPLETE_VAR = '_IDF.PY_COMPLETE' + +# was shell completion invoked? +SHELL_COMPLETE_RUN = SHELL_COMPLETE_VAR in os.environ + def executable_exists(args: List) -> bool: try: @@ -79,7 +88,35 @@ def idf_version() -> Optional[str]: return version -def print_hints(*filenames: str) -> None: +# function prints warning when autocompletion is not being performed +# set argument stream to sys.stderr for errors and exceptions +def print_warning(message: str, stream: TextIO=None) -> None: + if not SHELL_COMPLETE_RUN: + print(message, file=stream or sys.stderr) + + +def color_print(message: str, color: str, newline: Optional[str]='\n') -> None: + """ Print a message to stderr with colored highlighting """ + ansi_normal = '\033[0m' + sys.stderr.write('%s%s%s%s' % (color, message, ansi_normal, newline)) + sys.stderr.flush() + + +def yellow_print(message: str, newline: Optional[str]='\n') -> None: + ansi_yellow = '\033[0;33m' + color_print(message, ansi_yellow, newline) + + +def red_print(message: str, newline: Optional[str]='\n') -> None: + ansi_red = '\033[1;31m' + color_print(message, ansi_red, newline) + + +def debug_print_idf_version() -> None: + print_warning(f'ESP-IDF {idf_version() or "version unknown"}') + + +def generate_hints(*filenames: str) -> Generator: """Getting output files and printing hints on how to resolve errors based on the output.""" with open(os.path.join(os.path.dirname(__file__), 'hints.yml'), 'r') as file: hints = yaml.safe_load(file) @@ -87,16 +124,36 @@ def print_hints(*filenames: str) -> None: with open(file_name, 'r') as file: output = ' '.join(line.strip() for line in file if line.strip()) for hint in hints: + variables_list = hint.get('variables') + hint_list, hint_vars, re_vars = [], [], [] + match: Optional[Match[str]] = None try: - match = re.compile(hint['re']).findall(output) - except KeyError: - raise KeyError("Argument 're' missing in {}. Check hints.yml file.".format(hint)) + if variables_list: + for variables in variables_list: + hint_vars = variables['hint_variables'] + re_vars = variables['re_variables'] + regex = hint['re'].format(*re_vars) + if re.compile(regex).search(output): + try: + hint_list.append(hint['hint'].format(*hint_vars)) + except KeyError as e: + red_print('Argument {} missing in {}. Check hints.yml file.'.format(e, hint)) + sys.exit(1) + else: + match = re.compile(hint['re']).search(output) + except KeyError as e: + red_print('Argument {} missing in {}. Check hints.yml file.'.format(e, hint)) + sys.exit(1) except re.error as e: - raise re.error('{} from hints.yml have {} problem. Check hints.yml file.'.format(hint['re'], e)) - if match: - extra_info = ', '.join(match) if hint.get('match_to_output', '') else '' + red_print('{} from hints.yml have {} problem. Check hints.yml file.'.format(hint['re'], e)) + sys.exit(1) + if hint_list: + for message in hint_list: + yield ' '.join(['HINT:', message]) + elif match: + extra_info = ', '.join(match.groups()) if hint.get('match_to_output', '') else '' try: - yellow_print(' '.join(['HINT:', hint['hint'].format(extra_info)])) + yield ' '.join(['HINT:', hint['hint'].format(extra_info)]) except KeyError: raise KeyError("Argument 'hint' missing in {}. Check hints.yml file.".format(hint)) @@ -117,7 +174,7 @@ def fit_text_in_terminal(out: str) -> str: class RunTool: def __init__(self, tool_name: str, args: List, cwd: str, env: Dict=None, custom_error_handler: FunctionType=None, build_dir: str=None, - hints: bool=False, force_progression: bool=False, interactive: bool=False) -> None: + hints: bool=True, force_progression: bool=False, interactive: bool=False) -> None: self.tool_name = tool_name self.args = args self.cwd = cwd @@ -158,7 +215,8 @@ class RunTool: return if stderr_output_file and stdout_output_file: - print_hints(stderr_output_file, stdout_output_file) + for hint in generate_hints(stderr_output_file, stdout_output_file): + yellow_print(hint) raise FatalError('{} failed with exit code {}, output of the command is in the {} and {}'.format(self.tool_name, process.returncode, stderr_output_file, stdout_output_file)) @@ -185,45 +243,68 @@ class RunTool: if p.stderr and p.stdout: # it only to avoid None type in p.std await asyncio.gather( self.read_and_write_stream(p.stderr, stderr_output_file, sys.stderr), - self.read_and_write_stream(p.stdout, stdout_output_file)) + self.read_and_write_stream(p.stdout, stdout_output_file, sys.stdout)) await p.wait() # added for avoiding None returncode return p, stderr_output_file, stdout_output_file async def read_and_write_stream(self, input_stream: asyncio.StreamReader, output_filename: str, - output_stream: TextIO=sys.stdout) -> None: + output_stream: TextIO) -> None: """read the output of the `input_stream` and then write it into `output_filename` and `output_stream`""" def delete_ansi_escape(text: str) -> str: ansi_escape = re.compile(r'\x1B(?:[@-Z\\-_]|\[[0-?]*[ -/]*[@-~])') return ansi_escape.sub('', text) - def prepare_for_print(out: bytes) -> str: - # errors='ignore' is here because some chips produce some garbage bytes - result = out.decode(errors='ignore') - if not output_stream.isatty(): - # delete escape sequence if we printing in environments where ANSI coloring is disabled - return delete_ansi_escape(result) - return result - def print_progression(output: str) -> None: # Print a new line on top of the previous line sys.stdout.write('\x1b[K') print('\r', end='') print(fit_text_in_terminal(output.strip('\n\r')), end='', file=output_stream) + async def read_stream() -> Optional[str]: + try: + output_b = await input_stream.readline() + return output_b.decode(errors='ignore') + except (asyncio.LimitOverrunError, asyncio.IncompleteReadError) as e: + print(e, file=sys.stderr) + return None + except AttributeError: + return None + + async def read_interactive_stream() -> Optional[str]: + buffer = b'' + while True: + output_b = await input_stream.read(1) + if not output_b: + return None + try: + return (buffer + output_b).decode() + except UnicodeDecodeError: + buffer += output_b + if len(buffer) > 4: + # Multi-byte character contain up to 4 bytes and if buffer have more then 4 bytes + # and still can not decode it we can just ignore some bytes + return buffer.decode(errors='ignore') + try: - with open(output_filename, 'w') as output_file: + with open(output_filename, 'w', encoding='utf8') as output_file: while True: if self.interactive: - out = await input_stream.read(1) + output = await read_interactive_stream() else: - out = await input_stream.readline() - if not out: + output = await read_stream() + if not output: break - output = prepare_for_print(out) - output_file.write(output) + output_noescape = delete_ansi_escape(output) + # Always remove escape sequences when writing the build log. + output_file.write(output_noescape) + # If idf.py output is redirected and the output stream is not a TTY, + # strip the escape sequences as well. + # (There shouldn't be any, but just in case.) + if not output_stream.isatty(): + output = output_noescape - # print output in progression way but only the progression related (that started with '[') and if verbose flag is not set if self.force_progression and output[0] == '[' and '-v' not in self.args and output_stream.isatty(): + # print output in progression way but only the progression related (that started with '[') and if verbose flag is not set print_progression(output) else: output_stream.write(output) @@ -234,23 +315,29 @@ class RunTool: def run_tool(*args: Any, **kwargs: Any) -> None: - # Added in case some one use run_tool externally in a idf.py extensions + # Added in case someone uses run_tool externally in idf.py extensions return RunTool(*args, **kwargs)() def run_target(target_name: str, args: 'PropertyDict', env: Optional[Dict]=None, - custom_error_handler: FunctionType=None, force_progression: bool=False, hints: bool=False, interactive: bool=False) -> None: + custom_error_handler: FunctionType=None, force_progression: bool=False, interactive: bool=False) -> None: """Run target in build directory.""" if env is None: env = {} generator_cmd = GENERATORS[args.generator]['command'] - env.update(GENERATORS[args.generator]['envvar']) if args.verbose: generator_cmd += [GENERATORS[args.generator]['verbose_flag']] - RunTool(generator_cmd[0], generator_cmd + [target_name], args.build_dir, env, custom_error_handler, hints=hints, + # By default, GNU Make and Ninja strip away color escape sequences when they see that their stdout is redirected. + # If idf.py's stdout is not redirected, the final output is a TTY, so we can tell Make/Ninja to disable stripping + # of color escape sequences. (Requires Ninja v1.9.0 or later.) + if sys.stdout.isatty(): + if 'CLICOLOR_FORCE' not in env: + env['CLICOLOR_FORCE'] = '1' + + RunTool(generator_cmd[0], generator_cmd + [target_name], args.build_dir, env, custom_error_handler, hints=not args.no_hints, force_progression=force_progression, interactive=interactive)() @@ -317,6 +404,11 @@ def ensure_build_directory(args: 'PropertyDict', prog_name: str, always_run_cmak the build directory, an error is raised. If the parameter is None, this function will set it to an auto-detected default generator or to the value already configured in the build directory. """ + + if not executable_exists(['cmake', '--version']): + debug_print_idf_version() + raise FatalError(f'"cmake" must be available on the PATH to use {PROG}') + project_dir = args.project_dir # Verify the project directory if not os.path.isdir(project_dir): diff --git a/tools/idf_size.py b/tools/idf_size.py index bfac433f80..787fef3859 100755 --- a/tools/idf_size.py +++ b/tools/idf_size.py @@ -9,8 +9,6 @@ # SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 # -from __future__ import division, print_function, unicode_literals - import argparse import collections import json @@ -20,9 +18,16 @@ import sys from typing import Any, Callable, Collection, Dict, Iterable, List, Optional, TextIO, Tuple, Union import yaml -from future.utils import iteritems -Section = Dict[str, Union[str, int]] + +class Section(Dict): + # define for python type hints + size: int + address: int + name: str + sources: List[Dict] + + SectionDict = Dict[str, Section] @@ -445,15 +450,21 @@ def check_target(target: str, map_file: TextIO) -> None: def main() -> None: parser = argparse.ArgumentParser(description='idf_size - a tool to print size information from an IDF MAP file') - parser.add_argument( - '--json', - help='Output results as JSON', - action='store_true') - parser.add_argument( 'map_file', help='MAP file produced by linker', type=argparse.FileType('r')) + format_group = parser.add_mutually_exclusive_group() + + format_group.add_argument( + '--format', + help='Specify output format: text, csv or json', + choices=['text','csv', 'json'], + default='text') + + format_group.add_argument( + '--json', help=argparse.SUPPRESS, action='store_true') + parser.add_argument( '--archives', help='Print per-archive sizes', action='store_true') @@ -481,6 +492,9 @@ def main() -> None: args = parser.parse_args() + if args.json: + print('WARNING: --json argument is deprecated in favour of the --format argument') + detected_target, segments, sections = load_map_data(args.map_file) args.map_file.close() check_target(detected_target, args.map_file) @@ -504,32 +518,31 @@ def main() -> None: output = '' - if not args.json or not (args.archives or args.files or args.archive_details): + if not args.format == 'json' or not (args.archives or args.files or args.archive_details): output += get_summary(args.map_file.name, segments, sections, detected_target, - args.json, - args.another_map_file, segments_diff, sections_diff, detected_target_diff, not (args.archives or args.files)) + args.format, args.another_map_file, segments_diff, + sections_diff, detected_target_diff, not (args.archives or args.files)) if args.archives: - output += get_detailed_sizes(sections, 'archive', 'Archive File', args.json, sections_diff) + output += get_detailed_sizes(sections, 'archive', 'Archive File', args.format, sections_diff) if args.files: - output += get_detailed_sizes(sections, 'file', 'Object File', args.json, sections_diff) - + output += get_detailed_sizes(sections, 'file', 'Object File', args.format, sections_diff) if args.archive_details: - output += get_archive_symbols(sections, args.archive_details, args.json, sections_diff) + output += get_archive_symbols(sections, args.archive_details, args.format, sections_diff) args.output_file.write(output) args.output_file.close() class StructureForSummary(object): - used_dram_data, used_dram_bss, used_dram_rodata, used_dram_other, used_dram, dram_total, dram_remain = (0, ) * 7 + dram_data, dram_bss, dram_rodata, dram_other, used_dram, dram_total, dram_remain = (0, ) * 7 used_dram_ratio = 0. - used_iram_vectors, used_iram_text, used_iram_other, used_iram, iram_total, iram_remain = (0, ) * 6 + iram_vectors, iram_text, iram_other, used_iram, iram_total, iram_remain = (0, ) * 6 used_iram_ratio = 0. - used_diram_data, used_diram_bss, used_diram_text, used_diram_vectors, used_diram_rodata, used_diram_other, diram_total, used_diram, diram_remain = (0, ) * 9 + diram_data, diram_bss, diram_text, diram_vectors, diram_rodata, diram_other, diram_total, used_diram, diram_remain = (0, ) * 9 used_diram_ratio = 0. - used_flash_text, used_flash_rodata, used_flash_other, used_flash, total_size = (0, ) * 5 + flash_code, flash_rodata, flash_other, used_flash_non_ram, total_size = (0, ) * 5 def __sub__(self, rhs: 'StructureForSummary') -> 'StructureForSummary': assert isinstance(rhs, StructureForSummary) @@ -606,84 +619,84 @@ class StructureForSummary(object): flash_rodata_list = filter_in_section(flash_sections, 'rodata') flash_other_list = [x for x in flash_sections if x not in flash_text_list + flash_rodata_list] - r.used_dram_data = get_size(dram_data_list) - r.used_dram_bss = get_size(dram_bss_list) - r.used_dram_rodata = get_size(dram_rodata_list) - r.used_dram_other = get_size(dram_other_list) - r.used_dram = r.used_dram_data + r.used_dram_bss + r.used_dram_other + r.used_dram_rodata + r.dram_data = get_size(dram_data_list) + r.dram_bss = get_size(dram_bss_list) + r.dram_rodata = get_size(dram_rodata_list) + r.dram_other = get_size(dram_other_list) + r.used_dram = r.dram_data + r.dram_bss + r.dram_other + r.dram_rodata try: r.used_dram_ratio = r.used_dram / r.dram_total except ZeroDivisionError: r.used_dram_ratio = float('nan') if r.used_dram != 0 else 0 r.dram_remain = r.dram_total - r.used_dram - r.used_iram_vectors = get_size((iram_vectors_list)) - r.used_iram_text = get_size((iram_text_list)) - r.used_iram_other = get_size((iram_other_list)) - r.used_iram = r.used_iram_vectors + r.used_iram_text + r.used_iram_other + r.iram_vectors = get_size((iram_vectors_list)) + r.iram_text = get_size((iram_text_list)) + r.iram_other = get_size((iram_other_list)) + r.used_iram = r.iram_vectors + r.iram_text + r.iram_other try: r.used_iram_ratio = r.used_iram / r.iram_total except ZeroDivisionError: r.used_iram_ratio = float('nan') if r.used_iram != 0 else 0 r.iram_remain = r.iram_total - r.used_iram - r.used_diram_data = get_size(diram_data_list) - r.used_diram_bss = get_size(diram_bss_list) - r.used_diram_text = get_size(diram_text_list) - r.used_diram_vectors = get_size(diram_vectors_list) - r.used_diram_rodata = get_size(diram_rodata_list) - r.used_diram_other = get_size(diram_other_list) - r.used_diram = r.used_diram_data + r.used_diram_bss + r.used_diram_text + r.used_diram_vectors + r.used_diram_other + r.used_diram_rodata + r.diram_data = get_size(diram_data_list) + r.diram_bss = get_size(diram_bss_list) + r.diram_text = get_size(diram_text_list) + r.diram_vectors = get_size(diram_vectors_list) + r.diram_rodata = get_size(diram_rodata_list) + r.diram_other = get_size(diram_other_list) + r.used_diram = r.diram_data + r.diram_bss + r.diram_text + r.diram_vectors + r.diram_other + r.diram_rodata try: r.used_diram_ratio = r.used_diram / r.diram_total except ZeroDivisionError: r.used_diram_ratio = float('nan') if r.used_diram != 0 else 0 r.diram_remain = r.diram_total - r.used_diram - r.used_flash_text = get_size(flash_text_list) - r.used_flash_rodata = get_size(flash_rodata_list) + r.flash_code = get_size(flash_text_list) + r.flash_rodata = get_size(flash_rodata_list) - r.used_flash_other = get_size(flash_other_list) - r.used_flash = r.used_flash_text + r.used_flash_rodata + r.used_flash_other + r.flash_other = get_size(flash_other_list) + r.used_flash_non_ram = r.flash_code + r.flash_rodata + r.flash_other # The used DRAM BSS is counted into the "Used static DRAM" but not into the "Total image size" - r.total_size = r.used_dram - r.used_dram_bss + r.used_iram + r.used_diram - r.used_diram_bss + r.used_flash + r.total_size = r.used_dram - r.dram_bss + r.used_iram + r.used_diram - r.diram_bss + r.used_flash_non_ram return r - def get_json_dic(self) -> collections.OrderedDict: + def get_dict(self) -> collections.OrderedDict: ret = collections.OrderedDict([ - ('dram_data', self.used_dram_data), - ('dram_bss', self.used_dram_bss), - ('dram_rodata', self.used_dram_rodata), - ('dram_other', self.used_dram_other), + ('dram_data', self.dram_data), + ('dram_bss', self.dram_bss), + ('dram_rodata', self.dram_rodata), + ('dram_other', self.dram_other), ('used_dram', self.used_dram), ('dram_total', self.dram_total), ('used_dram_ratio', self.used_dram_ratio if self.used_dram_ratio is not float('nan') else 0), ('dram_remain', self.dram_remain), - ('iram_vectors', self.used_iram_vectors), - ('iram_text', self.used_iram_text), - ('iram_other', self.used_iram_other), + ('iram_vectors', self.iram_vectors), + ('iram_text', self.iram_text), + ('iram_other', self.iram_other), ('used_iram', self.used_iram), ('iram_total', self.iram_total), ('used_iram_ratio', self.used_iram_ratio), ('iram_remain', self.iram_remain), - ('diram_data', self.used_diram_data), - ('diram_bss', self.used_diram_bss), - ('diram_text', self.used_diram_text), - ('diram_vectors', self.used_diram_vectors), - ('diram_rodata', self.used_diram_rodata), - ('diram_other', self.used_diram_other), + ('diram_data', self.diram_data), + ('diram_bss', self.diram_bss), + ('diram_text', self.diram_text), + ('diram_vectors', self.diram_vectors), + ('diram_rodata', self.diram_rodata), + ('diram_other', self.diram_other), ('diram_total', self.diram_total), ('used_diram', self.used_diram), ('used_diram_ratio', self.used_diram_ratio), ('diram_remain', self.diram_remain), - ('flash_code', self.used_flash_text), - ('flash_rodata', self.used_flash_rodata), - ('flash_other', self.used_flash_other), - ('used_flash_non_ram', self.used_flash), # text/data in D/I RAM not included + ('flash_code', self.flash_code), + ('flash_rodata', self.flash_rodata), + ('flash_other', self.flash_other), + ('used_flash_non_ram', self.used_flash_non_ram), # text/data in D/I RAM not included ('total_size', self.total_size) # bss not included ]) @@ -702,8 +715,7 @@ def get_structure_for_target(segments: Dict, sections: Dict, target: str) -> Str return current -def get_summary(path: str, segments: Dict, sections: Dict, target: str, - as_json: bool=False, +def get_summary(path: str, segments: Dict, sections: Dict, target: str, output_format: str='', path_diff: str='', segments_diff: Optional[Dict]=None, sections_diff: Optional[Dict]=None, target_diff: str='', print_suggestions: bool=True) -> str: segments_diff = segments_diff or {} @@ -721,12 +733,12 @@ def get_summary(path: str, segments: Dict, sections: Dict, target: str, diff_en = False reference = StructureForSummary() - if as_json: - current_json_dic = current.get_json_dic() + if output_format == 'json': + current_json_dic = current.get_dict() if diff_en: - reference_json_dic = reference.get_json_dic() + reference_json_dic = reference.get_dict() diff_json_dic = collections.OrderedDict([ - (k, v - reference_json_dic[k]) for k, v in iteritems(current_json_dic)]) + (k, v - reference_json_dic[k]) for k, v in current_json_dic.items()]) output = format_json(collections.OrderedDict([('current', current_json_dic), ('reference', reference_json_dic), ('diff', diff_json_dic), @@ -735,24 +747,24 @@ def get_summary(path: str, segments: Dict, sections: Dict, target: str, output = format_json(current_json_dic) else: class LineDef(object): - title = '' - name = '' def __init__(self, title: str, name: str) -> None: self.title = title self.name = name def format_line(self) -> Tuple[str, str, str, str]: - return (self.title + ': {%s:>7} bytes' % self.name, + return ('%16s: {%s:>7} bytes' % (self.title, self.name), '{%s:>7}' % self.name, '{%s:+}' % self.name, '') + def format_line_csv(self) -> Tuple[str, str, str, str]: + return ('%s,{%s} bytes' % (self.title, self.name), + '{%s}' % self.name, + '{%s:+}' % self.name, + '') + class HeadLineDef(LineDef): - remain = '' - ratio = '' - total = '' - warning_message = '' def __init__(self, title: str, name: str, remain: str, ratio: str, total: str, warning_message: str) -> None: super(HeadLineDef, self).__init__(title, name) @@ -762,87 +774,108 @@ def get_summary(path: str, segments: Dict, sections: Dict, target: str, self.warning_message = warning_message def format_line(self) -> Tuple[str, str, str, str]: - return ('%s: {%s:>7} bytes ({%s:>7} remain, {%s:.1%%} used)%s' % (self.title, self.name, self.remain, self.ratio, self.warning_message), + return ('%-1s: {%s:>7} bytes ({%s:>7} remain, {%s:.1%%} used)%s' % (self.title, self.name, self.remain, self.ratio, self.warning_message), '{%s:>7}' % self.name, '{%s:+}' % self.name, '({%s:>+7} remain, {%s:>+7} total)' % (self.remain, self.total)) + def format_line_csv(self) -> Tuple[str, str, str, str]: + return ('%s,{%s} bytes ({%s} remain {%s:.1%%} used)%s' % (self.title, self.name, self.remain, self.ratio, self.warning_message), + '{%s}' % self.name, + '{%s:+}' % self.name, + '{%s} remain,{%s} total' % (self.remain, self.total)) + class TotalLineDef(LineDef): def format_line(self) -> Tuple[str, str, str, str]: - return (self.title + ': {%s:>7} bytes (.bin may be padded larger)' % self.name, + return ('%16s: {%s:>7} bytes (.bin may be padded larger)' % (self.title, self.name), '{%s:>7}' % self.name, '{%s:+}' % self.name, '') + def format_line_csv(self) -> Tuple[str, str, str, str]: + return ('%s,{%s} bytes (.bin may be padded larger)' % (self.title, self.name), + '{%s}' % self.name, + '{%s:+}' % self.name, + '') + warning_message = ' Overflow detected!' + (' You can run idf.py size-files for more information.' if print_suggestions else '') format_list = [ HeadLineDef('Used static DRAM', 'used_dram', remain='dram_remain', ratio='used_dram_ratio', total='dram_total', warning_message=warning_message if current.get_dram_overflowed() else ''), - LineDef(' .data size', 'used_dram_data'), - LineDef(' .bss size', 'used_dram_bss'), - LineDef(' .rodata size', 'used_dram_rodata'), - LineDef(' DRAM other size', 'used_dram_other'), + LineDef('.data size', 'dram_data'), + LineDef('.bss size', 'dram_bss'), + LineDef('.rodata size', 'dram_rodata'), + LineDef('DRAM other size', 'dram_other'), HeadLineDef('Used static IRAM', 'used_iram', remain='iram_remain', ratio='used_iram_ratio', total='iram_total', warning_message=warning_message if current.get_iram_overflowed() else ''), - LineDef(' .text size', 'used_iram_text'), - LineDef(' .vectors size', 'used_iram_vectors'), + LineDef('.text size', 'iram_text'), + LineDef('.vectors size', 'iram_vectors'), HeadLineDef('Used stat D/IRAM', 'used_diram', remain='diram_remain', ratio='used_diram_ratio', total='diram_total', warning_message=warning_message if current.get_diram_overflowed() else ''), - LineDef(' .data size', 'used_diram_data'), - LineDef(' .bss size', 'used_diram_bss'), - LineDef(' .text size', 'used_diram_text'), - LineDef(' .vectors size', 'used_diram_vectors'), - LineDef(' .rodata size', 'used_diram_rodata'), - LineDef(' other ', 'used_diram_other'), + LineDef('.data size', 'diram_data'), + LineDef('.bss size', 'diram_bss'), + LineDef('.text size', 'diram_text'), + LineDef('.vectors size', 'diram_vectors'), + LineDef('.rodata size', 'diram_rodata'), + LineDef('other', 'diram_other'), - LineDef('Used Flash size ', 'used_flash'), - LineDef(' .text ', 'used_flash_text'), - LineDef(' .rodata ', 'used_flash_rodata'), + LineDef('Used Flash size ', 'used_flash_non_ram'), + LineDef('.text', 'flash_code'), + LineDef('.rodata', 'flash_rodata'), TotalLineDef('Total image size', 'total_size') ] - def convert_to_fmt_dict(summary: StructureForSummary, suffix: str='') -> Dict: - required_items = StructureForSummary.get_required_items() - return dict([(key + suffix, getattr(summary, key)) for key in required_items]) - - f_dic1 = convert_to_fmt_dict(current) + current_dict = current.get_dict() if diff_en: - f_dic2 = convert_to_fmt_dict(reference) - f_dic_diff = convert_to_fmt_dict(current - reference) + reference_dict = reference.get_dict() + diff_dict = (current - reference).get_dict() - lf = '{:60}{:>15}{:>15} {}' # Width for a, b, c, d columns + if output_format == 'csv': + line_format = '{},{},{},{}' + else: + line_format = '{:60}{:>15}{:>15} {}' # Width for a, b, c, d columns def print_in_columns(a: str, b: Optional[str]='', c: Optional[str]='', d: Optional[str]='') -> str: - return lf.format(a, b, c, d).rstrip() + os.linesep + return line_format.format(a, b, c, d).rstrip() + os.linesep output = '' if diff_en: - output += print_in_columns(' MAP file: ' + path) - output += print_in_columns(' MAP file: ' + path_diff) - output += print_in_columns('Difference is counted as - , ', - 'i.e. a positive number means that is larger.') - output += print_in_columns('Total sizes of :', '', 'Difference', '') + if output_format == 'csv': + output += print_in_columns('',':', '', 'Difference') + output += print_in_columns('File', path, path_diff, ' - ') + else: + output += print_in_columns(' MAP file: ' + path) + output += print_in_columns(' MAP file: ' + path_diff) + output += print_in_columns('Difference is counted as - , ', + 'i.e. a positive number means that is larger.') + output += print_in_columns('Total sizes of :', '', 'Difference') for line in format_list: if getattr(current, line.name) > 0 or getattr(reference, line.name) > 0 or line.name == 'total_size': - main_string_format, reference_format, sign_format, main_diff_format = line.format_line() + if output_format == 'csv': + main_string_format, reference_format, sign_format, main_diff_format = line.format_line_csv() + else: + main_string_format, reference_format, sign_format, main_diff_format = line.format_line() output += print_in_columns( - main_string_format.format(**f_dic1), - reference_format.format(**f_dic2), - sign_format.format(**f_dic_diff) if not sign_format.format(**f_dic_diff).startswith('+0') else '', - main_diff_format.format(**f_dic_diff)) + main_string_format.format(**current_dict), + reference_format.format(**reference_dict), + sign_format.format(**diff_dict) if not sign_format.format(**diff_dict).startswith('+0') else '', + main_diff_format.format(**diff_dict)) else: output += print_in_columns('Total sizes:') for line in format_list: if getattr(current, line.name) > 0 or line.name == 'total_size': - main_string_format, reference_format, sign_format, main_diff_format = line.format_line() - output += print_in_columns(main_string_format.format(**f_dic1)) + if output_format == 'csv': + main_string_format, _, _, _ = line.format_line_csv() + else: + main_string_format, _, _, _ = line.format_line() + output += print_in_columns(main_string_format.format(**current_dict)) return output @@ -878,7 +911,7 @@ class StructureForDetailedSizes(object): Key can be either "archive" (for per-archive data) or "file" (for per-file data) in the result. """ result = {} # type: Dict[str, Dict[str, int]] - for _, section in iteritems(sections): + for _, section in sections.items(): for s in section['sources']: if not s[key] in result: result[s[key]] = {} @@ -919,7 +952,7 @@ class StructureForDetailedSizes(object): return collections.OrderedDict(s) -def get_detailed_sizes(sections: Dict, key: str, header: str, as_json: bool=False, sections_diff: Dict=None) -> str: +def get_detailed_sizes(sections: Dict, key: str, header: str, output_format: str, sections_diff: Dict=None) -> str: key_name_set = set() current = StructureForDetailedSizes.get(sections, key) @@ -936,7 +969,8 @@ def get_detailed_sizes(sections: Dict, key: str, header: str, as_json: bool=Fals key_name_list = list(key_name_set) ordered_key_list, display_name_list = LinkingSections.get_display_name_order(key_name_list) - if as_json: + + if output_format == 'json': if diff_en: diff_json_dic = collections.OrderedDict() for name in sorted(list(frozenset(current.keys()) | frozenset(reference.keys()))): @@ -953,16 +987,19 @@ def get_detailed_sizes(sections: Dict, key: str, header: str, as_json: bool=Fals else: output = format_json(current) else: - def _get_header_format(disp_list: List=display_name_list) -> str: + def _get_header_format(disp_list: List=display_name_list, output_format: str='') -> str: + if output_format == 'csv': + return '{},' * (len(disp_list) - 1) + '{}' + os.linesep len_list = [len(x) for x in disp_list] len_list.insert(0, 24) return ' '.join(['{:>%d}' % x for x in len_list]) + os.linesep - def _get_output(data: Dict[str, Dict[str, int]], selection: Collection, key_list: List=ordered_key_list, disp_list: List=display_name_list) -> str: - header_format = _get_header_format(disp_list) + def _get_output(data: Dict[str, Dict[str, int]], selection: Collection, output_format: str, + key_list: List=ordered_key_list, disp_list: List=display_name_list) -> str: + header_format = _get_header_format(disp_list, output_format) output = header_format.format(header, *disp_list) - for key, data_info in iteritems(data): + for key, data_info in data.items(): if key not in selection: continue @@ -980,30 +1017,32 @@ def get_detailed_sizes(sections: Dict, key: str, header: str, as_json: bool=Fals output += header_format.format(key[:24], *(section_size_list)) return output - def _get_header_format_diff(disp_list: List=display_name_list, columns: bool=False) -> str: + def _get_header_format_diff(disp_list: List=display_name_list, columns: bool=False, output_format: str='') -> str: + if output_format == 'csv': + return '{},' * len(disp_list) + '{}' + os.linesep if columns: len_list = (24, ) + (7, ) * 3 * len(disp_list) return '|'.join(['{:>%d}' % x for x in len_list]) + os.linesep - len_list = (24, ) + (23, ) * len(disp_list) return ' '.join(['{:>%d}' % x for x in len_list]) + os.linesep - def _get_output_diff(curr: Dict, ref: Dict, key_list: List=ordered_key_list, disp_list: List=display_name_list) -> str: + def _get_output_diff(curr: Dict, ref: Dict, output_format: str, key_list: List=ordered_key_list, disp_list: List=display_name_list) -> str: # First header without Current/Ref/Diff columns - header_format = _get_header_format_diff(columns=False) + header_format = _get_header_format_diff(columns=False, output_format=output_format) output = header_format.format(header, *disp_list) f_print = ('-' * 23, '') * len(key_list) f_print = f_print[0:len(key_list)] header_line = header_format.format('', *f_print) - header_format = _get_header_format_diff(columns=True) + header_format = _get_header_format_diff(columns=True, output_format=output_format) f_print = ('', '', '-') * len(key_list) output += header_format.format('', *f_print) - output += header_line + if output_format != 'csv': + output += header_line - for key, data_info in iteritems(curr): + for key, data_info in curr.items(): try: v2 = ref[key] except KeyError: @@ -1034,7 +1073,7 @@ def get_detailed_sizes(sections: Dict, key: str, header: str, as_json: bool=Fals output = 'Per-{} contributions to ELF file:{}'.format(key, os.linesep) if diff_en: - output += _get_output_diff(current, reference) + output += _get_output_diff(current, reference, output_format) in_current = frozenset(current.keys()) in_reference = frozenset(reference.keys()) @@ -1043,13 +1082,13 @@ def get_detailed_sizes(sections: Dict, key: str, header: str, as_json: bool=Fals if len(only_in_current) > 0: output += 'The following entries are present in only:{}'.format(os.linesep) - output += _get_output(current, only_in_current) + output += _get_output(current, only_in_current, output_format) if len(only_in_reference) > 0: output += 'The following entries are present in only:{}'.format(os.linesep) - output += _get_output(reference, only_in_reference) + output += _get_output(reference, only_in_reference, output_format) else: - output += _get_output(current, current) + output += _get_output(current, current, output_format) return output @@ -1060,7 +1099,7 @@ class StructureForArchiveSymbols(object): interested_sections = LinkingSections.filter_sections(sections) result = dict([(t, {}) for t in interested_sections]) # type: Dict[str, Dict[str, int]] - for _, section in iteritems(sections): + for _, section in sections.items(): section_name = section['name'] if section_name not in interested_sections: continue @@ -1081,12 +1120,12 @@ class StructureForArchiveSymbols(object): return section_symbols -def get_archive_symbols(sections: Dict, archive: str, as_json: bool=False, sections_diff: Dict=None) -> str: +def get_archive_symbols(sections: Dict, archive: str, output_format: str, sections_diff: Dict=None) -> str: diff_en = bool(sections_diff) current = StructureForArchiveSymbols.get(archive, sections) reference = StructureForArchiveSymbols.get(archive, sections_diff) if sections_diff else {} - if as_json: + if output_format == 'json': if diff_en: diff_json_dic = collections.OrderedDict() for name in sorted(list(frozenset(current.keys()) | frozenset(reference.keys()))): @@ -1104,41 +1143,51 @@ def get_archive_symbols(sections: Dict, archive: str, as_json: bool=False, secti output = format_json(current) else: def _get_item_pairs(name: str, section: collections.OrderedDict) -> collections.OrderedDict: - return collections.OrderedDict([(key.replace(name + '.', ''), val) for key, val in iteritems(section)]) + return collections.OrderedDict([(key.replace(name + '.', ''), val) for key, val in section.items()]) def _get_max_len(symbols_dict: Dict) -> Tuple[int, int]: # the lists have 0 in them because max() doesn't work with empty lists names_max_len = 0 numbers_max_len = 0 - for t, s in iteritems(symbols_dict): - numbers_max_len = max([numbers_max_len, *[len(str(x)) for _, x in iteritems(s)]]) + for t, s in symbols_dict.items(): + numbers_max_len = max([numbers_max_len, *[len(str(x)) for _, x in s.items()]]) names_max_len = max([names_max_len, *[len(x) for x in _get_item_pairs(t, s)]]) return names_max_len, numbers_max_len def _get_output(section_symbols: Dict) -> str: output = '' + names_max_len, numbers_max_len = _get_max_len(section_symbols) - for t, s in iteritems(section_symbols): + if output_format == 'csv': + line_format = '{},{}' + os.linesep + else: + line_format = ' {:<%d} : {:>%d}' % (names_max_len,numbers_max_len) + os.linesep + + for t, s in section_symbols.items(): output += '{}Symbols from section: {}{}'.format(os.linesep, t, os.linesep) item_pairs = _get_item_pairs(t, s) - for key, val in iteritems(item_pairs): - output += ' '.join([('\t{:<%d} : {:>%d}\n' % (names_max_len,numbers_max_len)).format(key, val)]) - section_total = sum([val for _, val in iteritems(item_pairs)]) + for key, val in item_pairs.items(): + output += line_format.format(key, val) + section_total = sum([val for _, val in item_pairs.items()]) output += 'Section total: {}{}'.format(section_total, os.linesep) return output output = '{}Symbols within the archive: {} (Not all symbols may be reported){}'.format(os.linesep, archive, os.linesep) if diff_en: - def _generate_line_tuple(curr: collections.OrderedDict, ref: collections.OrderedDict, name: str) -> Tuple[str, int, int, str]: + def _generate_line_tuple(curr: collections.OrderedDict, ref: collections.OrderedDict, name: str, indent: str) -> Tuple[str, int, int, str]: cur_val = curr.get(name, 0) ref_val = ref.get(name, 0) diff_val = cur_val - ref_val # string slicing is used just to make sure it will fit into the first column of line_format - return ((' ' * 4 + name)[:40], cur_val, ref_val, '' if diff_val == 0 else '{:+}'.format(diff_val)) + return ((indent + name)[:40], cur_val, ref_val, '' if diff_val == 0 else '{:+}'.format(diff_val)) + + if output_format == 'csv': + line_format = '{},{},{},{}' + else: + line_format = '{:40} {:>12} {:>12} {:>25}' - line_format = '{:40} {:>12} {:>12} {:>25}' all_section_names = sorted(list(frozenset(current.keys()) | frozenset(reference.keys()))) for section_name in all_section_names: current_item_pairs = _get_item_pairs(section_name, current.get(section_name, {})) @@ -1147,15 +1196,17 @@ def get_archive_symbols(sections: Dict, archive: str, as_json: bool=False, secti '', '', ' - ') + os.linesep - current_section_total = sum([val for _, val in iteritems(current_item_pairs)]) - reference_section_total = sum([val for _, val in iteritems(reference_item_pairs)]) + current_section_total = sum([val for _, val in current_item_pairs.items()]) + reference_section_total = sum([val for _, val in reference_item_pairs.items()]) diff_section_total = current_section_total - reference_section_total all_item_names = sorted(list(frozenset(current_item_pairs.keys()) | frozenset(reference_item_pairs.keys()))) - output += os.linesep.join([line_format.format(*_generate_line_tuple(current_item_pairs, - reference_item_pairs, - n) - ).rstrip() for n in all_item_names]) + indent = 4 * ' ' if output_format != 'csv' else '' + output += os.linesep.join(line_format.format(*_generate_line_tuple(current_item_pairs, + reference_item_pairs, + n, + indent) + ).rstrip() for n in all_item_names) output += os.linesep if current_section_total > 0 or reference_section_total > 0 else '' output += line_format.format('Section total:', current_section_total, diff --git a/tools/idf_size_yaml/esp32c6_data_info.yaml b/tools/idf_size_yaml/esp32c6_data_info.yaml new file mode 100644 index 0000000000..a4fbecf547 --- /dev/null +++ b/tools/idf_size_yaml/esp32c6_data_info.yaml @@ -0,0 +1,20 @@ +# Data_type: +# primary_address: value +# length: value or equation +# secondary_address: value if exist +DRAM: + primary_address: 0x40800000 + length: 0x80000 + secondary_address: 0x40800000 +IRAM: + primary_address: 0x40800000 + length: 0x80000 +CACHE_I: + primary_address: 0x42000000 + length: 0x800000 +CACHE_D: + primary_address: 0x42000000 + length: 0x800000 +RTC_SLOW_D: # TODO: IDF-5667 Better to rename to LP_RAM + primary_address: 0x50000000 + length: 0x4000 diff --git a/tools/idf_tools.py b/tools/idf_tools.py index 13073e3e48..fee794be12 100755 --- a/tools/idf_tools.py +++ b/tools/idf_tools.py @@ -44,6 +44,7 @@ import ssl import subprocess import sys import tarfile +import tempfile import time from collections import OrderedDict, namedtuple from json import JSONEncoder @@ -128,8 +129,11 @@ class Platforms: 'osx': PLATFORM_MACOS, 'darwin': PLATFORM_MACOS, 'Darwin-x86_64': PLATFORM_MACOS, + 'x86_64-apple-darwin': PLATFORM_MACOS, PLATFORM_MACOS_ARM64: PLATFORM_MACOS_ARM64, 'Darwin-arm64': PLATFORM_MACOS_ARM64, + 'aarch64-apple-darwin': PLATFORM_MACOS_ARM64, + 'arm64-apple-darwin': PLATFORM_MACOS_ARM64, # Linux PLATFORM_LINUX64: PLATFORM_LINUX64, 'linux64': PLATFORM_LINUX64, @@ -159,6 +163,9 @@ class Platforms: if platform_alias is None: return None + if platform_alias == 'any' and CURRENT_PLATFORM: + platform_alias = CURRENT_PLATFORM + platform_name = Platforms.PLATFORM_FROM_NAME.get(platform_alias, None) # ARM platform may run on armhf hardware but having armel installed packages. @@ -190,37 +197,29 @@ CURRENT_PLATFORM = Platforms.get(PYTHON_PLATFORM) EXPORT_SHELL = 'shell' EXPORT_KEY_VALUE = 'key-value' -ISRG_X1_ROOT_CERT = u""" +# "DigiCert Global Root CA" +DIGICERT_ROOT_CERT = u""" -----BEGIN CERTIFICATE----- -MIIFazCCA1OgAwIBAgIRAIIQz7DSQONZRGPgu2OCiwAwDQYJKoZIhvcNAQELBQAw -TzELMAkGA1UEBhMCVVMxKTAnBgNVBAoTIEludGVybmV0IFNlY3VyaXR5IFJlc2Vh -cmNoIEdyb3VwMRUwEwYDVQQDEwxJU1JHIFJvb3QgWDEwHhcNMTUwNjA0MTEwNDM4 -WhcNMzUwNjA0MTEwNDM4WjBPMQswCQYDVQQGEwJVUzEpMCcGA1UEChMgSW50ZXJu -ZXQgU2VjdXJpdHkgUmVzZWFyY2ggR3JvdXAxFTATBgNVBAMTDElTUkcgUm9vdCBY -MTCCAiIwDQYJKoZIhvcNAQEBBQADggIPADCCAgoCggIBAK3oJHP0FDfzm54rVygc -h77ct984kIxuPOZXoHj3dcKi/vVqbvYATyjb3miGbESTtrFj/RQSa78f0uoxmyF+ -0TM8ukj13Xnfs7j/EvEhmkvBioZxaUpmZmyPfjxwv60pIgbz5MDmgK7iS4+3mX6U -A5/TR5d8mUgjU+g4rk8Kb4Mu0UlXjIB0ttov0DiNewNwIRt18jA8+o+u3dpjq+sW -T8KOEUt+zwvo/7V3LvSye0rgTBIlDHCNAymg4VMk7BPZ7hm/ELNKjD+Jo2FR3qyH -B5T0Y3HsLuJvW5iB4YlcNHlsdu87kGJ55tukmi8mxdAQ4Q7e2RCOFvu396j3x+UC -B5iPNgiV5+I3lg02dZ77DnKxHZu8A/lJBdiB3QW0KtZB6awBdpUKD9jf1b0SHzUv -KBds0pjBqAlkd25HN7rOrFleaJ1/ctaJxQZBKT5ZPt0m9STJEadao0xAH0ahmbWn -OlFuhjuefXKnEgV4We0+UXgVCwOPjdAvBbI+e0ocS3MFEvzG6uBQE3xDk3SzynTn -jh8BCNAw1FtxNrQHusEwMFxIt4I7mKZ9YIqioymCzLq9gwQbooMDQaHWBfEbwrbw -qHyGO0aoSCqI3Haadr8faqU9GY/rOPNk3sgrDQoo//fb4hVC1CLQJ13hef4Y53CI -rU7m2Ys6xt0nUW7/vGT1M0NPAgMBAAGjQjBAMA4GA1UdDwEB/wQEAwIBBjAPBgNV -HRMBAf8EBTADAQH/MB0GA1UdDgQWBBR5tFnme7bl5AFzgAiIyBpY9umbbjANBgkq -hkiG9w0BAQsFAAOCAgEAVR9YqbyyqFDQDLHYGmkgJykIrGF1XIpu+ILlaS/V9lZL -ubhzEFnTIZd+50xx+7LSYK05qAvqFyFWhfFQDlnrzuBZ6brJFe+GnY+EgPbk6ZGQ -3BebYhtF8GaV0nxvwuo77x/Py9auJ/GpsMiu/X1+mvoiBOv/2X/qkSsisRcOj/KK -NFtY2PwByVS5uCbMiogziUwthDyC3+6WVwW6LLv3xLfHTjuCvjHIInNzktHCgKQ5 -ORAzI4JMPJ+GslWYHb4phowim57iaztXOoJwTdwJx4nLCgdNbOhdjsnvzqvHu7Ur -TkXWStAmzOVyyghqpZXjFaH3pO3JLF+l+/+sKAIuvtd7u+Nxe5AW0wdeRlN8NwdC -jNPElpzVmbUq4JUagEiuTDkHzsxHpFKVK7q4+63SM1N95R1NbdWhscdCb+ZAJzVc -oyi3B43njTOQ5yOf+1CceWxG1bQVs5ZufpsMljq4Ui0/1lvh+wjChP4kqKOJ2qxq -4RgqsahDYVvTH9w7jXbyLeiNdd8XM2w9U/t7y0Ff/9yi0GE44Za4rF2LN9d11TPA -mRGunUHBcnWEvgJBQl9nJEiU0Zsnvgc/ubhPgXRR4Xq37Z0j4r7g1SgEEzwxA57d -emyPxgcYxn/eR44/KJ4EBs+lVDR3veyJm+kXQ99b21/+jh5Xos1AnX5iItreGCc= +MIIDrzCCApegAwIBAgIQCDvgVpBCRrGhdWrJWZHHSjANBgkqhkiG9w0BAQUFADBh +MQswCQYDVQQGEwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3 +d3cuZGlnaWNlcnQuY29tMSAwHgYDVQQDExdEaWdpQ2VydCBHbG9iYWwgUm9vdCBD +QTAeFw0wNjExMTAwMDAwMDBaFw0zMTExMTAwMDAwMDBaMGExCzAJBgNVBAYTAlVT +MRUwEwYDVQQKEwxEaWdpQ2VydCBJbmMxGTAXBgNVBAsTEHd3dy5kaWdpY2VydC5j +b20xIDAeBgNVBAMTF0RpZ2lDZXJ0IEdsb2JhbCBSb290IENBMIIBIjANBgkqhkiG +9w0BAQEFAAOCAQ8AMIIBCgKCAQEA4jvhEXLeqKTTo1eqUKKPC3eQyaKl7hLOllsB +CSDMAZOnTjC3U/dDxGkAV53ijSLdhwZAAIEJzs4bg7/fzTtxRuLWZscFs3YnFo97 +nh6Vfe63SKMI2tavegw5BmV/Sl0fvBf4q77uKNd0f3p4mVmFaG5cIzJLv07A6Fpt +43C/dxC//AH2hdmoRBBYMql1GNXRor5H4idq9Joz+EkIYIvUX7Q6hL+hqkpMfT7P +T19sdl6gSzeRntwi5m3OFBqOasv+zbMUZBfHWymeMr/y7vrTC0LUq7dBMtoM1O/4 +gdW7jVg/tRvoSSiicNoxBN33shbyTApOB6jtSj1etX+jkMOvJwIDAQABo2MwYTAO +BgNVHQ8BAf8EBAMCAYYwDwYDVR0TAQH/BAUwAwEB/zAdBgNVHQ4EFgQUA95QNVbR +TLtm8KPiGxvDl7I90VUwHwYDVR0jBBgwFoAUA95QNVbRTLtm8KPiGxvDl7I90VUw +DQYJKoZIhvcNAQEFBQADggEBAMucN6pIExIK+t1EnE9SsPTfrgT1eXkIoyQY/Esr +hMAtudXH/vTBH1jLuG2cenTnmCmrEbXjcKChzUyImZOMkXDiqw8cvpOp/2PV5Adg +06O/nVsJ8dWO41P0jmP6P6fbtGbfYmbW0W5BjfIttep3Sp+dWOIrWcBAI+0tKIJF +PnlUkiaY4IBIqDfv8NZ5YBberOgOzW6sRBc4L0na4UU+Krk2U886UAb3LujEV0ls +YSEY1QSteDwsOoBrp+uvFRTp2InBuThs4pFsiv9kuXclVzDAGySj4dzp30d8tbQk +CAUw7C29C79Fv1C5qfPrmAESrciIxpg0X40KPMbp1ZWVbd4= -----END CERTIFICATE----- """ @@ -249,6 +248,25 @@ def info(text, f=None, *args): # type: (str, Optional[IO[str]], str) -> None f.write(text + '\n', *args) +def print_hints_on_download_error(err): # type: (str) -> None + info('Please make sure you have a working Internet connection.') + + if 'CERTIFICATE' in err: + info('Certificate issues are usually caused by an outdated certificate database on your computer.') + info('Please check the documentation of your operating system for how to upgrade it.') + + if sys.platform == 'darwin': + info('Running "./Install\\ Certificates.command" might be able to fix this issue.') + + info('Running "{} -m pip install --upgrade certifi" can also resolve this issue in some cases.'.format(sys.executable)) + + # Certificate issue on Windows can be hidden under different errors which might be even translated, + # e.g. "[WinError -2146881269] ASN1 valor de tag invĂ¡lido encontrado" + if sys.platform == 'win32': + info('By downloading and using the offline installer from https://dl.espressif.com/dl/esp-idf ' + 'you might be able to work around this issue.') + + def run_cmd_check_output(cmd, input_text=None, extra_paths=None): # type: (List[str], Optional[str], Optional[List[str]]) -> bytes # If extra_paths is given, locate the executable in one of these directories. @@ -405,17 +423,17 @@ def urlretrieve_ctx(url, filename, reporthook=None, data=None, context=None): return result -def download(url, destination): # type: (str, str) -> None +def download(url, destination): # type: (str, str) -> Optional[Exception] info(f'Downloading {url}') info(f'Destination: {destination}') try: ctx = None - # For dl.espressif.com, add the ISRG x1 root certificate. + # For dl.espressif.com and github.com, add the DigiCert root certificate. # This works around the issue with outdated certificate stores in some installations. - if 'dl.espressif.com' in url: + if 'dl.espressif.com' in url or 'github.com' in url: try: ctx = ssl.create_default_context() - ctx.load_verify_locations(cadata=ISRG_X1_ROOT_CERT) + ctx.load_verify_locations(cadata=DIGICERT_ROOT_CERT) except AttributeError: # no ssl.create_default_context or load_verify_locations cadata argument # in Python <=2.7.8 @@ -423,10 +441,10 @@ def download(url, destination): # type: (str, str) -> None urlretrieve_ctx(url, destination, report_progress if not global_non_interactive else None, context=ctx) sys.stdout.write('\rDone\n') + return None except Exception as e: # urlretrieve could throw different exceptions, e.g. IOError when the server is down - # Errors are ignored because the downloaded file is checked a couple of lines later. - warn('Download failure {}'.format(e)) + return e finally: sys.stdout.flush() @@ -452,7 +470,7 @@ def rename_with_retry(path_from, path_to): # type: (str, str) -> None time.sleep(0.5) -def strip_container_dirs(path, levels): # type: (str, int) -> None +def do_strip_container_dirs(path, levels): # type: (str, int) -> None assert levels > 0 # move the original directory out of the way (add a .tmp suffix) tmp_path = path + '.tmp' @@ -486,10 +504,6 @@ class ToolExecError(RuntimeError): pass -class DownloadError(RuntimeError): - pass - - class IDFToolDownload(object): def __init__(self, platform_name, url, size, sha256): # type: (str, str, int, str) -> None self.platform_name = platform_name @@ -549,6 +563,7 @@ IDFToolOptions = namedtuple('IDFToolOptions', [ 'version_cmd', 'version_regex', 'version_regex_replace', + 'is_executable', 'export_paths', 'export_vars', 'install', @@ -565,8 +580,8 @@ class IDFTool(object): INSTALL_NEVER = 'never' def __init__(self, name, description, install, info_url, license, version_cmd, version_regex, supported_targets, version_regex_replace=None, - strip_container_dirs=0): - # type: (str, str, str, str, str, List[str], str, List[str], Optional[str], int) -> None + strip_container_dirs=0, is_executable=True): + # type: (str, str, str, str, str, List[str], str, List[str], Optional[str], int, bool) -> None self.name = name self.description = description self.drop_versions() @@ -574,11 +589,12 @@ class IDFTool(object): self.versions_installed = [] # type: List[str] if version_regex_replace is None: version_regex_replace = VERSION_REGEX_REPLACE_DEFAULT - self.options = IDFToolOptions(version_cmd, version_regex, version_regex_replace, + self.options = IDFToolOptions(version_cmd, version_regex, version_regex_replace, is_executable, [], OrderedDict(), install, info_url, license, strip_container_dirs, supported_targets) # type: ignore self.platform_overrides = [] # type: List[Dict[str, str]] self._platform = CURRENT_PLATFORM self._update_current_options() + self.is_executable = is_executable def copy_for_platform(self, platform): # type: (str) -> IDFTool result = copy.deepcopy(self) @@ -599,14 +615,14 @@ class IDFTool(object): self.versions = OrderedDict() # type: Dict[str, IDFToolVersion] def add_version(self, version): # type: (IDFToolVersion) -> None - assert(type(version) is IDFToolVersion) + assert type(version) is IDFToolVersion self.versions[version.version] = version def get_path(self): # type: () -> str return os.path.join(global_idf_tools_path or '', 'tools', self.name) def get_path_for_version(self, version): # type: (str) -> str - assert(version in self.versions) + assert version in self.versions return os.path.join(self.get_path(), version) def get_export_paths(self, version): # type: (str) -> List[str] @@ -625,10 +641,12 @@ class IDFTool(object): v_repl = re.sub(SUBST_TOOL_PATH_REGEX, replace_path, v) if v_repl != v: v_repl = to_shell_specific_paths([v_repl])[0] - result[k] = v_repl + old_v = os.environ.get(k) + if old_v is None or old_v != v_repl: + result[k] = v_repl return result - def check_version(self, extra_paths=None): # type: (Optional[List[str]]) -> str + def get_version(self, extra_paths=None, executable_path=None): # type: (Optional[List[str]], Optional[str]) -> str """ Execute the tool, optionally prepending extra_paths to PATH, extract the version string and return it as a result. @@ -640,6 +658,8 @@ class IDFTool(object): # this function can not be called for a different platform assert self._platform == CURRENT_PLATFORM cmd = self._current_options.version_cmd # type: ignore + if executable_path: + cmd[0] = executable_path try: version_cmd_result = run_cmd_check_output(cmd, None, extra_paths) except OSError: @@ -655,6 +675,10 @@ class IDFTool(object): return UNKNOWN_VERSION return re.sub(self._current_options.version_regex, self._current_options.version_regex_replace, match.group(0)) # type: ignore + def check_version(self, executable_path): # type: (Optional[str]) -> bool + version = self.get_version(executable_path=executable_path) + return version in self.versions + def get_install_type(self): # type: () -> Callable[[str], None] return self._current_options.install # type: ignore @@ -697,7 +721,7 @@ class IDFTool(object): assert self._platform == CURRENT_PLATFORM # First check if the tool is in system PATH try: - ver_str = self.check_version() + ver_str = self.get_version() except ToolNotFound: # not in PATH pass @@ -716,8 +740,11 @@ class IDFTool(object): if not os.path.exists(tool_path): # version not installed continue + if not self.is_executable: + self.versions_installed.append(version) + continue try: - ver_str = self.check_version(self.get_export_paths(version)) + ver_str = self.get_version(self.get_export_paths(version)) except ToolNotFound: warn('directory for tool {} version {} is present, but tool was not found'.format( self.name, version)) @@ -732,11 +759,11 @@ class IDFTool(object): self.versions_installed.append(version) def download(self, version): # type: (str) -> None - assert(version in self.versions) + assert version in self.versions download_obj = self.versions[version].get_download_for_platform(self._platform) if not download_obj: fatal('No packages for tool {} platform {}!'.format(self.name, self._platform)) - raise DownloadError() + raise SystemExit(1) url = download_obj.url archive_name = os.path.basename(url) @@ -754,8 +781,9 @@ class IDFTool(object): downloaded = False local_temp_path = local_path + '.tmp' for retry in range(DOWNLOAD_RETRY_COUNT): - download(url, local_temp_path) + err = download(url, local_temp_path) if not os.path.isfile(local_temp_path) or not self.check_download_file(download_obj, local_temp_path): + warn('Download failure: {}'.format(err)) warn('Failed to download {} to {}'.format(url, local_temp_path)) continue rename_with_retry(local_temp_path, local_path) @@ -763,17 +791,18 @@ class IDFTool(object): break if not downloaded: fatal('Failed to download, and retry count has expired') - raise DownloadError() + print_hints_on_download_error(str(err)) + raise SystemExit(1) def install(self, version): # type: (str) -> None # Currently this is called after calling 'download' method, so here are a few asserts # for the conditions which should be true once that method is done. - assert (version in self.versions) + assert version in self.versions download_obj = self.versions[version].get_download_for_platform(self._platform) - assert (download_obj is not None) + assert download_obj is not None archive_name = os.path.basename(download_obj.url) archive_path = os.path.join(global_idf_tools_path or '', 'dist', archive_name) - assert (os.path.isfile(archive_path)) + assert os.path.isfile(archive_path) dest_dir = self.get_path_for_version(version) if os.path.exists(dest_dir): warn('destination path already exists, removing') @@ -781,7 +810,7 @@ class IDFTool(object): mkdir_p(dest_dir) unpack(archive_path, dest_dir) if self._current_options.strip_container_dirs: # type: ignore - strip_container_dirs(dest_dir, self._current_options.strip_container_dirs) # type: ignore + do_strip_container_dirs(dest_dir, self._current_options.strip_container_dirs) # type: ignore @staticmethod def check_download_file(download_obj, local_path): # type: (IDFToolDownload, str) -> bool @@ -798,28 +827,29 @@ class IDFTool(object): @classmethod def from_json(cls, tool_dict): # type: (Dict[str, Union[str, List[str], Dict[str, str]]]) -> IDFTool - # json.load will return 'str' types in Python 3 and 'unicode' in Python 2 - expected_str_type = type(u'') - # Validate json fields tool_name = tool_dict.get('name') # type: ignore - if type(tool_name) is not expected_str_type: + if not isinstance(tool_name, str): raise RuntimeError('tool_name is not a string') description = tool_dict.get('description') # type: ignore - if type(description) is not expected_str_type: + if not isinstance(description, str): raise RuntimeError('description is not a string') + is_executable = tool_dict.get('is_executable', True) # type: ignore + if not isinstance(is_executable, bool): + raise RuntimeError('is_executable for tool %s is not a bool' % tool_name) + version_cmd = tool_dict.get('version_cmd') if type(version_cmd) is not list: raise RuntimeError('version_cmd for tool %s is not a list of strings' % tool_name) version_regex = tool_dict.get('version_regex') - if type(version_regex) is not expected_str_type or not version_regex: + if not isinstance(version_regex, str) or (not version_regex and is_executable): raise RuntimeError('version_regex for tool %s is not a non-empty string' % tool_name) version_regex_replace = tool_dict.get('version_regex_replace') - if version_regex_replace and type(version_regex_replace) is not expected_str_type: + if version_regex_replace and not isinstance(version_regex_replace, str): raise RuntimeError('version_regex_replace for tool %s is not a string' % tool_name) export_paths = tool_dict.get('export_paths') @@ -835,15 +865,15 @@ class IDFTool(object): raise RuntimeError('versions for tool %s is not an array' % tool_name) install = tool_dict.get('install', False) # type: ignore - if type(install) is not expected_str_type: + if not isinstance(install, str): raise RuntimeError('install for tool %s is not a string' % tool_name) info_url = tool_dict.get('info_url', False) # type: ignore - if type(info_url) is not expected_str_type: + if not isinstance(info_url, str): raise RuntimeError('info_url for tool %s is not a string' % tool_name) license = tool_dict.get('license', False) # type: ignore - if type(license) is not expected_str_type: + if not isinstance(license, str): raise RuntimeError('license for tool %s is not a string' % tool_name) strip_container_dirs = tool_dict.get('strip_container_dirs', 0) @@ -861,7 +891,7 @@ class IDFTool(object): # Create the object tool_obj = cls(tool_name, description, install, info_url, license, # type: ignore version_cmd, version_regex, supported_targets, version_regex_replace, # type: ignore - strip_container_dirs) # type: ignore + strip_container_dirs, is_executable) # type: ignore for path in export_paths: # type: ignore tool_obj.options.export_paths.append(path) # type: ignore @@ -875,7 +905,7 @@ class IDFTool(object): raise RuntimeError('platforms for override %d of tool %s is not a list' % (index, tool_name)) install = override.get('install') # type: ignore - if install is not None and type(install) is not expected_str_type: + if install is not None and not isinstance(install, str): raise RuntimeError('install for override %d of tool %s is not a string' % (index, tool_name)) version_cmd = override.get('version_cmd') # type: ignore @@ -884,12 +914,12 @@ class IDFTool(object): (index, tool_name)) version_regex = override.get('version_regex') # type: ignore - if version_regex is not None and (type(version_regex) is not expected_str_type or not version_regex): + if version_regex is not None and (not isinstance(version_regex, str) or not version_regex): raise RuntimeError('version_regex for override %d of tool %s is not a non-empty string' % (index, tool_name)) version_regex_replace = override.get('version_regex_replace') # type: ignore - if version_regex_replace is not None and type(version_regex_replace) is not expected_str_type: + if version_regex_replace is not None and not isinstance(version_regex_replace, str): raise RuntimeError('version_regex_replace for override %d of tool %s is not a string' % (index, tool_name)) @@ -905,11 +935,11 @@ class IDFTool(object): recommended_versions = {} # type: dict[str, list[str]] for version_dict in versions: # type: ignore version = version_dict.get('name') # type: ignore - if type(version) is not expected_str_type: + if not isinstance(version, str): raise RuntimeError('version name for tool {} is not a string'.format(tool_name)) version_status = version_dict.get('status') # type: ignore - if type(version_status) is not expected_str_type and version_status not in IDFToolVersion.STATUS_VALUES: + if not isinstance(version_status, str) and version_status not in IDFToolVersion.STATUS_VALUES: raise RuntimeError('tool {} version {} status is not one of {}', tool_name, version, IDFToolVersion.STATUS_VALUES) @@ -976,6 +1006,8 @@ class IDFTool(object): tool_json['platform_overrides'] = overrides_array if self.options.strip_container_dirs: tool_json['strip_container_dirs'] = self.options.strip_container_dirs + if self.options.is_executable is False: + tool_json['is_executable'] = self.options.is_executable return tool_json @@ -1018,6 +1050,16 @@ class IDFRecord: def __repr__(self) -> str: return self.__str__() + def __eq__(self, other: object) -> bool: + if not isinstance(other, IDFRecord): + return False + return all(getattr(self, x) == getattr(other, x) for x in ('version', 'path', 'features', 'targets')) + + def __ne__(self, other: object) -> bool: + if not isinstance(other, IDFRecord): + return False + return not self.__eq__(other) + @property def features(self) -> List[str]: return self._features @@ -1065,74 +1107,24 @@ class IDFRecord: idf_record_obj.update_features(record_dict.get('features', [])) idf_record_obj.extend_targets(record_dict.get('targets', [])) - unset = record_dict.get('unset') - # Records with unset are type SelectedIDFRecord - if unset: - return SelectedIDFRecord(idf_record_obj, unset) - - return idf_record_obj - - -class SelectedIDFRecord(IDFRecord): - """ - SelectedIDFRecord extends IDFRecord by unset attribute - * unset - global variables that need to be removed from env when the active esp-idf environment is beiing deactivated - """ - - # No constructor from parent IDFRecord class is called because that conctructor create instance with default values, - # meanwhile SelectedIDFRecord constructor is called only to expand existing IDFRecord instance. - def __init__(self, idf_record_obj: IDFRecord, unset: Dict[str, Any]): - self.version = idf_record_obj.version - self.path = idf_record_obj.path - self._targets = idf_record_obj.targets - self._features = idf_record_obj.features - self.unset = unset - - def __iter__(self): # type: ignore - yield from { - 'version': self.version, - 'path': self.path, - 'features': self._features, - 'targets': self._targets, - 'unset': self.unset - }.items() - - def __str__(self) -> str: - return json.dumps(dict(self), ensure_ascii=False, indent=4) # type: ignore - - def __repr__(self) -> str: - return self.__str__() - - # When there is no need to store unset attr with IDF record, cast it back SelectedIDFRecord -> IDFRecord - def cast_to_idf_record(self) -> IDFRecord: - idf_record_obj = IDFRecord() - idf_record_obj.version = self.version - idf_record_obj.path = self.path - idf_record_obj._targets = self._targets - idf_record_obj._features = self._features return idf_record_obj class IDFEnv: """ - IDFEnv represents ESP-IDF Environments installed on system. All information are saved and loaded from IDF_ENV_FILE + IDFEnv represents ESP-IDF Environments installed on system and is responsible for loading and saving structured data + All information is saved and loaded from IDF_ENV_FILE Contains: - * idf_selected_id - ID of selected ESP-IDF from idf_installed. ID is combination of ESP-IDF absolute path and version * idf_installed - all installed environments of ESP-IDF on system - * idf_previous_id - ID of ESP-IDF which was active before switching to idf_selected_id """ def __init__(self) -> None: active_idf_id = active_repo_id() - self.idf_selected_id = active_idf_id # type: str self.idf_installed = {active_idf_id: IDFRecord.get_active_idf_record()} # type: Dict[str, IDFRecord] - self.idf_previous_id = '' # type: str def __iter__(self): # type: ignore yield from { - 'idfSelectedId': self.idf_selected_id, 'idfInstalled': self.idf_installed, - 'idfPreviousId': self.idf_previous_id }.items() def __str__(self) -> str: @@ -1142,30 +1134,27 @@ class IDFEnv: return self.__str__() def save(self) -> None: - try: - if global_idf_tools_path: # mypy fix for Optional[str] in the next call - # the directory doesn't exist if this is run on a clean system the first time - mkdir_p(global_idf_tools_path) - with open(os.path.join(global_idf_tools_path or '', IDF_ENV_FILE), 'w') as w: - json.dump(dict(self), w, cls=IDFEnvEncoder, ensure_ascii=False, indent=4) # type: ignore - except (IOError, OSError): - fatal('File {} is not accessible to write. '.format(os.path.join(global_idf_tools_path or '', IDF_ENV_FILE))) - raise SystemExit(1) + """ + Diff current class instance with instance loaded from IDF_ENV_FILE and save only if are different + """ + # It is enough to compare just active records because others can't be touched by the running script + if self.get_active_idf_record() != self.get_idf_env().get_active_idf_record(): + idf_env_file_path = os.path.join(global_idf_tools_path or '', IDF_ENV_FILE) + try: + if global_idf_tools_path: # mypy fix for Optional[str] in the next call + # the directory doesn't exist if this is run on a clean system the first time + mkdir_p(global_idf_tools_path) + with open(idf_env_file_path, 'w') as w: + info('Updating {}'.format(idf_env_file_path)) + json.dump(dict(self), w, cls=IDFEnvEncoder, ensure_ascii=False, indent=4) # type: ignore + except (IOError, OSError): + if not os.access(global_idf_tools_path or '', os.W_OK): + raise OSError('IDF_TOOLS_PATH {} is not accessible to write. Required changes have not been saved'.format(global_idf_tools_path or '')) + raise OSError('File {} is not accessible to write or corrupted. Required changes have not been saved'.format(idf_env_file_path)) def get_active_idf_record(self) -> IDFRecord: return self.idf_installed[active_repo_id()] - def get_selected_idf_record(self) -> IDFRecord: - return self.idf_installed[self.idf_selected_id] - - def get_previous_idf_record(self) -> Union[IDFRecord, str]: - if self.idf_previous_id != '': - return self.idf_installed[self.idf_previous_id] - return '' - - def idf_installed_update(self, idf_name: str, idf_value: IDFRecord) -> None: - self.idf_installed[idf_name] = idf_value - @classmethod def get_idf_env(cls): # type: () -> IDFEnv # IDFEnv class is used to process IDF_ENV_FILE file. The constructor is therefore called only in this method that loads the file and checks its contents @@ -1193,12 +1182,6 @@ class IDFEnv: # If the active record is already in idf_installed, it is not overwritten idf_env_obj.idf_installed = dict(idf_env_obj.idf_installed, **idf_installed_verified) - for file_var_name, class_var_name in [('idfSelectedId', 'idf_selected_id'), ('idfPreviousId', 'idf_previous_id')]: - idf_env_value = idf_env_json.get(file_var_name) - # Update the variable only if it meets the given conditions, otherwise keep default value from constructor - if idf_env_value in idf_env_obj.idf_installed and idf_env_value != 'sha': - idf_env_obj.__setattr__(class_var_name, idf_env_value) - except (IOError, OSError, ValueError): # If no, empty or not-accessible to read IDF_ENV_FILE found, use default values from constructor pass @@ -1206,6 +1189,50 @@ class IDFEnv: return idf_env_obj +class ENVState: + """ + ENVState is used to handle IDF global variables that are set in environment and need to be removed when switching between ESP-IDF versions in opened shell + Every opened shell/terminal has it's own temporary file to store these variables + The temporary file's name is generated automatically with suffix 'idf_ + opened shell ID'. Path to this tmp file is stored as env global variable (env_key) + The shell ID is crucial, since in one terminal can be opened more shells + * env_key - global variable name/key + * deactivate_file_path - global variable value (generated tmp file name) + * idf_variables - loaded IDF variables from file + """ + env_key = 'IDF_DEACTIVATE_FILE_PATH' + deactivate_file_path = os.environ.get(env_key, '') + + def __init__(self) -> None: + self.idf_variables = {} # type: Dict[str, Any] + + @classmethod + def get_env_state(cls): # type: () -> ENVState + env_state_obj = cls() + + if cls.deactivate_file_path: + try: + with open(cls.deactivate_file_path, 'r') as fp: + env_state_obj.idf_variables = json.load(fp) + except (IOError, OSError, ValueError): + pass + return env_state_obj + + def save(self) -> str: + try: + if self.deactivate_file_path and os.path.basename(self.deactivate_file_path).endswith('idf_' + str(os.getppid())): + # If exported file path/name exists and belongs to actual opened shell + with open(self.deactivate_file_path, 'w') as w: + json.dump(self.idf_variables, w, ensure_ascii=False, indent=4) # type: ignore + else: + with tempfile.NamedTemporaryFile(delete=False, suffix='idf_' + str(os.getppid())) as fp: + self.deactivate_file_path = fp.name + fp.write(json.dumps(self.idf_variables, ensure_ascii=False, indent=4).encode('utf-8')) + except (IOError, OSError): + warn('File storing IDF env variables {} is not accessible to write. ' + 'Potentional switching ESP-IDF versions may cause problems'.format(self.deactivate_file_path)) + return self.deactivate_file_path + + def load_tools_info(): # type: () -> dict[str, IDFTool] """ Load tools metadata from tools.json, return a dictionary: tool name - tool info @@ -1378,58 +1405,45 @@ def filter_tools_info(idf_env_obj, tools_info): # type: (IDFEnv, OrderedDict[st return OrderedDict(filtered_tools_spec) -def add_unset(idf_env_obj, new_unset_vars, args): # type: (IDFEnv, dict[str, Any], list[str]) -> None +def add_variables_to_deactivate_file(args, new_idf_vars): # type: (list[str], dict[str, Any]) -> str """ - Add global variables that need to be removed when the active esp-idf environment is deactivated. + Add IDF global variables that need to be removed when the active esp-idf environment is deactivated. """ - if 'PATH' in new_unset_vars: - new_unset_vars['PATH'] = new_unset_vars['PATH'].split(':')[:-1] # PATH is stored as list of sub-paths without '$PATH' + if 'PATH' in new_idf_vars: + new_idf_vars['PATH'] = new_idf_vars['PATH'].split(':')[:-1] # PATH is stored as list of sub-paths without '$PATH' - new_unset_vars['PATH'] = new_unset_vars.get('PATH', []) + new_idf_vars['PATH'] = new_idf_vars.get('PATH', []) args_add_paths_extras = vars(args).get('add_paths_extras') # remove mypy error with args - new_unset_vars['PATH'] = new_unset_vars['PATH'] + args_add_paths_extras.split(':') if args_add_paths_extras else new_unset_vars['PATH'] + new_idf_vars['PATH'] = new_idf_vars['PATH'] + args_add_paths_extras.split(':') if args_add_paths_extras else new_idf_vars['PATH'] - selected_idf = idf_env_obj.get_selected_idf_record() - # Detection if new variables are being added to the active ESP-IDF environment, or new terminal without active ESP-IDF environment is exporting. - if 'IDF_PYTHON_ENV_PATH' in os.environ: - # Adding new variables to SelectedIDFRecord (ESP-IDF env already activated) + env_state_obj = ENVState.get_env_state() - if not isinstance(selected_idf, SelectedIDFRecord): - # Versions without feature Switching between ESP-IDF versions (version <= 4.4) don't have SelectedIDFRecord -> set new one - idf_env_obj.idf_installed_update(idf_env_obj.idf_selected_id, SelectedIDFRecord(selected_idf, new_unset_vars)) - else: - # SelectedIDFRecord detected -> update - exported_unset_vars = selected_idf.unset - new_unset_vars['PATH'] = list(set(new_unset_vars['PATH'] + exported_unset_vars.get('PATH', []))) # remove duplicates - selected_idf.unset = dict(exported_unset_vars, **new_unset_vars) # merge two dicts - idf_env_obj.idf_installed_update(idf_env_obj.idf_selected_id, selected_idf) + if env_state_obj.idf_variables: + exported_idf_vars = env_state_obj.idf_variables + new_idf_vars['PATH'] = list(set(new_idf_vars['PATH'] + exported_idf_vars.get('PATH', []))) # remove duplicates + env_state_obj.idf_variables = dict(exported_idf_vars, **new_idf_vars) # merge two dicts else: - # Resetting new SelectedIDFRecord (new ESP-IDF env is being activated) - idf_env_obj.idf_installed_update(idf_env_obj.idf_selected_id, SelectedIDFRecord(selected_idf, new_unset_vars)) + env_state_obj.idf_variables = new_idf_vars + deactivate_file_path = env_state_obj.save() - previous_idf = idf_env_obj.get_previous_idf_record() - # If new ESP-IDF environment was activated, the previous one can't be SelectedIDFRecord anymore - if isinstance(previous_idf, SelectedIDFRecord): - idf_env_obj.idf_installed_update(idf_env_obj.idf_previous_id, previous_idf.cast_to_idf_record()) - - return + return deactivate_file_path -def deactivate_statement(idf_env_obj, args): # type: (IDFEnv, list[str]) -> None +def deactivate_statement(args): # type: (list[str]) -> None """ - Deactivate statement is sequence of commands, that remove some global variables from enviroment, + Deactivate statement is sequence of commands, that remove IDF global variables from enviroment, so the environment gets to the state it was before calling export.{sh/fish} script. """ - selected_idf = idf_env_obj.get_selected_idf_record() - if not isinstance(selected_idf, SelectedIDFRecord): - warn('No IDF variables to unset found. Deactivation of previous esp-idf version was unsuccessful.') + env_state_obj = ENVState.get_env_state() + if not env_state_obj.idf_variables: + warn('No IDF variables to remove from environment found. Deactivation of previous esp-idf version was not successful.') return - unset = selected_idf.unset + unset_vars = env_state_obj.idf_variables env_path = os.getenv('PATH') # type: Optional[str] if env_path: - cleared_env_path = ':'.join([k for k in env_path.split(':') if k not in unset['PATH']]) + cleared_env_path = ':'.join([k for k in env_path.split(':') if k not in unset_vars['PATH']]) - unset_list = [k for k in unset.keys() if k != 'PATH'] + unset_list = [k for k in unset_vars.keys() if k != 'PATH'] unset_format, sep = get_unset_format_and_separator(args) unset_statement = sep.join([unset_format.format(k) for k in unset_list]) @@ -1439,6 +1453,9 @@ def deactivate_statement(idf_env_obj, args): # type: (IDFEnv, list[str]) -> Non deactivate_statement_str = sep.join([unset_statement, export_statement]) print(deactivate_statement_str) + # After deactivation clear old variables + env_state_obj.idf_variables.clear() + env_state_obj.save() return @@ -1524,22 +1541,31 @@ def action_check(args): # type: ignore def action_export(args): # type: ignore - idf_env_obj = IDFEnv.get_idf_env() - if args.unset: - if different_idf_detected(): - deactivate_statement(idf_env_obj, args) - idf_env_obj.save() + if args.deactivate and different_idf_detected(): + deactivate_statement(args) return tools_info = load_tools_info() - tools_info = filter_tools_info(idf_env_obj, tools_info) + tools_info = filter_tools_info(IDFEnv.get_idf_env(), tools_info) all_tools_found = True export_vars = {} paths_to_export = [] + + self_restart_cmd = f'{sys.executable} {__file__}{(" --tools-json " + args.tools_json) if args.tools_json else ""}' + self_restart_cmd = to_shell_specific_paths([self_restart_cmd])[0] + prefer_system_hint = '' if IDF_TOOLS_EXPORT_CMD else f' To use it, run \'{self_restart_cmd} export --prefer-system\'' + install_cmd = to_shell_specific_paths([IDF_TOOLS_INSTALL_CMD])[0] if IDF_TOOLS_INSTALL_CMD else self_restart_cmd + ' install' + for name, tool in tools_info.items(): if tool.get_install_type() == IDFTool.INSTALL_NEVER: continue tool.find_installed_versions() + version_to_use = tool.get_preferred_installed_version() + + if not tool.is_executable and version_to_use: + tool_export_vars = tool.get_export_vars(version_to_use) + export_vars = {**export_vars, **tool_export_vars} + continue if tool.version_in_path: if tool.version_in_path not in tool.versions: @@ -1563,20 +1589,6 @@ def action_export(args): # type: ignore warn('using a deprecated version of tool {} found in PATH: {}'.format(name, tool.version_in_path)) continue - self_restart_cmd = '{} {}{}'.format(sys.executable, __file__, - (' --tools-json ' + args.tools_json) if args.tools_json else '') - self_restart_cmd = to_shell_specific_paths([self_restart_cmd])[0] - - if IDF_TOOLS_EXPORT_CMD: - prefer_system_hint = '' - else: - prefer_system_hint = ' To use it, run \'{} export --prefer-system\''.format(self_restart_cmd) - - if IDF_TOOLS_INSTALL_CMD: - install_cmd = to_shell_specific_paths([IDF_TOOLS_INSTALL_CMD])[0] - else: - install_cmd = self_restart_cmd + ' install' - if not tool.versions_installed: if tool.get_install_type() == IDFTool.INSTALL_ALWAYS: all_tools_found = False @@ -1595,15 +1607,11 @@ def action_export(args): # type: ignore info('Not using an unsupported version of tool {} found in PATH: {}.'.format( tool.name, tool.version_in_path) + prefer_system_hint, f=sys.stderr) - version_to_use = tool.get_preferred_installed_version() export_paths = tool.get_export_paths(version_to_use) if export_paths: paths_to_export += export_paths tool_export_vars = tool.get_export_vars(version_to_use) - for k, v in tool_export_vars.items(): - old_v = os.environ.get(k) - if old_v is None or old_v != v: - export_vars[k] = v + export_vars = {**export_vars, **tool_export_vars} current_path = os.getenv('PATH') idf_python_env_path, idf_python_export_path, virtualenv_python, _ = get_python_env_path() @@ -1635,18 +1643,12 @@ def action_export(args): # type: ignore if paths_to_export: export_vars['PATH'] = path_sep.join(to_shell_specific_paths(paths_to_export) + [old_path]) - export_statements = export_sep.join([export_format.format(k, v) for k, v in export_vars.items()]) - - active_idf_id = active_repo_id() - if idf_env_obj.idf_selected_id != active_idf_id: - idf_env_obj.idf_previous_id = idf_env_obj.idf_selected_id - idf_env_obj.idf_selected_id = active_idf_id - - if export_statements: + if export_vars: + # if not copy of export_vars is given to function, it brekas the formatting string for 'export_statements' + deactivate_file_path = add_variables_to_deactivate_file(args, export_vars.copy()) + export_vars[ENVState.env_key] = deactivate_file_path + export_statements = export_sep.join([export_format.format(k, v) for k, v in export_vars.items()]) print(export_statements) - add_unset(idf_env_obj, export_vars, args) - - idf_env_obj.save() if not all_tools_found: raise SystemExit(1) @@ -1756,7 +1758,12 @@ def action_download(args): # type: ignore if 'required' in tools_spec: idf_env_obj = IDFEnv.get_idf_env() targets = add_and_check_targets(idf_env_obj, args.targets) - idf_env_obj.save() + try: + idf_env_obj.save() + except OSError as err: + if args.targets in targets: + targets.remove(args.targets) + warn('Downloading tools for targets was not successful with error: {}'.format(err)) tools_spec, tools_info_for_platform = get_tools_spec_and_platform_info(args.platform, targets, args.tools) @@ -1795,7 +1802,12 @@ def action_install(args): # type: ignore if 'required' in tools_spec or 'all' in tools_spec: idf_env_obj = IDFEnv.get_idf_env() targets = add_and_check_targets(idf_env_obj, args.targets) - idf_env_obj.save() + try: + idf_env_obj.save() + except OSError as err: + if args.targets in targets: + targets.remove(args.targets) + warn('Installing targets was not successful with error: {}'.format(err)) info('Selected targets are: {}'.format(', '.join(targets))) # Installing tools for defined ESP_targets @@ -1864,16 +1876,29 @@ def get_wheels_dir(): # type: () -> Optional[str] def get_requirements(new_features): # type: (str) -> list[str] idf_env_obj = IDFEnv.get_idf_env() features = process_and_check_features(idf_env_obj, new_features) - idf_env_obj.save() + try: + idf_env_obj.save() + except OSError as err: + if new_features in features: + features.remove(new_features) + warn('Updating features was not successful with error: {}'.format(err)) return [feature_to_requirements_path(feature) for feature in features] -def get_constraints(idf_version): # type: (str) -> str +def get_constraints(idf_version, online=True): # type: (str, bool) -> str constraint_file = 'espidf.constraints.v{}.txt'.format(idf_version) constraint_path = os.path.join(global_idf_tools_path or '', constraint_file) constraint_url = '/'.join([IDF_DL_URL, constraint_file]) temp_path = constraint_path + '.tmp' + if not online: + if os.path.isfile(constraint_path): + return constraint_path + else: + fatal(f'{constraint_path} doesn\'t exist. Perhaps you\'ve forgotten to run the install scripts. ' + f'Please check the installation guide for more information.') + raise SystemExit(1) + mkdir_p(os.path.dirname(temp_path)) try: @@ -1886,8 +1911,9 @@ def get_constraints(idf_version): # type: (str) -> str pass for _ in range(DOWNLOAD_RETRY_COUNT): - download(constraint_url, temp_path) + err = download(constraint_url, temp_path) if not os.path.isfile(temp_path): + warn('Download failure: {}'.format(err)) warn('Failed to download {} to {}'.format(constraint_url, temp_path)) continue if os.path.isfile(constraint_path): @@ -1901,8 +1927,9 @@ def get_constraints(idf_version): # type: (str) -> str return constraint_path else: fatal('Failed to download, and retry count has expired') + print_hints_on_download_error(str(err)) info('See the help on how to disable constraints in order to work around this issue.') - raise DownloadError() + raise SystemExit(1) def install_legacy_python_virtualenv(path): # type: (str) -> None @@ -1977,6 +2004,8 @@ def action_install_python_env(args): # type: ignore warn('Removing the existing Python environment in {}'.format(idf_python_env_path)) shutil.rmtree(idf_python_env_path) + venv_can_upgrade = False + if not os.path.exists(virtualenv_python): try: import venv # noqa: F401 @@ -1986,6 +2015,7 @@ def action_install_python_env(args): # type: ignore if sys.version_info[:2] >= (3, 9): # upgrade pip & setuptools virtualenv_options += ['--upgrade-deps'] + venv_can_upgrade = True info('Creating a new Python environment in {}'.format(idf_python_env_path)) subprocess.check_call([sys.executable, '-m', 'venv', @@ -2000,6 +2030,12 @@ def action_install_python_env(args): # type: ignore if env_copy.get('PIP_USER') == 'yes': warn('Found PIP_USER="yes" in the environment. Disabling PIP_USER in this shell to install packages into a virtual environment.') env_copy['PIP_USER'] = 'no' + + if not venv_can_upgrade: + info('Upgrading pip and setuptools...') + subprocess.check_call([virtualenv_python, '-m', 'pip', 'install', '--upgrade', 'pip', 'setuptools'], + stdout=sys.stdout, stderr=sys.stderr, env=env_copy) + run_args = [virtualenv_python, '-m', 'pip', 'install', '--no-warn-script-location'] requirements_file_list = get_requirements(args.features) for requirement_file in requirements_file_list: @@ -2038,7 +2074,7 @@ def action_check_python_dependencies(args): # type: ignore raise SystemExit(1) if use_constraints: - constr_path = get_constraints(idf_version) + constr_path = get_constraints(idf_version, online=False) # keep offline for checking info('Constraint file: {}'.format(constr_path)) info('Requirement files:') @@ -2358,6 +2394,40 @@ More info: {info_url} print_out('') +def action_check_tool_supported(args): # type: (Any) -> None + """ + Print "True"/"False" to stdout as a result that tool is supported in IDF + Print erorr message to stderr otherwise and set exit code to 1 + """ + try: + tools_info = load_tools_info() + for _, v in tools_info.items(): + if v.name == args.tool_name: + print(v.check_version(args.exec_path)) + break + except (RuntimeError, ToolNotFound, ToolExecError) as err: + fatal(f'Failed to check tool support: (name: {args.tool_name}, exec: {args.exec_path})') + fatal(f'{err}') + raise SystemExit(1) + + +def action_get_tool_supported_versions(args): # type: (Any) -> None + """ + Print supported versions of a tool to stdout + Print erorr message to stderr otherwise and set exit code to 1 + """ + try: + tools_info = load_tools_info() + for _, v in tools_info.items(): + if v.name == args.tool_name: + print(list(v.versions.keys())) + break + except RuntimeError as err: + fatal(f'Failed to get tool supported versions. (tool: {args.tool_name})') + fatal(f'{err}') + raise SystemExit(1) + + def main(argv): # type: (list[str]) -> None parser = argparse.ArgumentParser() @@ -2377,8 +2447,9 @@ def main(argv): # type: (list[str]) -> None 'but has an unsupported version, a version from the tools directory ' + 'will be used instead. If this flag is given, the version in PATH ' + 'will be used.', action='store_true') - export.add_argument('--unset', help='Output command for unsetting tool paths, previously set with export', action='store_true') - export.add_argument('--add_paths_extras', help='Add idf-related path extras for unset option') + export.add_argument('--deactivate', help='Output command for deactivate different ESP-IDF version, previously set with export', action='store_true') + export.add_argument('--unset', help=argparse.SUPPRESS, action='store_true') + export.add_argument('--add_paths_extras', help='Add idf-related path extras for deactivate option') install = subparsers.add_parser('install', help='Download and install tools into the tools directory') install.add_argument('tools', metavar='TOOL', nargs='*', default=['required'], help='Tools to install. ' + @@ -2454,6 +2525,15 @@ def main(argv): # type: (list[str]) -> None 'to manage package versions by yourself. It can be set with the IDF_PYTHON_CHECK_CONSTRAINTS ' 'environment variable.') + if os.environ.get('IDF_TOOLS_VERSION_HELPER'): + check_tool_supported = subparsers.add_parser('check-tool-supported', + help='Check that selected tool is compatible with IDF. Writes "True"/"False" to stdout in success.') + check_tool_supported.add_argument('--tool-name', required=True, help='Tool name (from tools.json)') + check_tool_supported.add_argument('--exec-path', required=True, help='Full path to executable under the test') + + get_tool_supported_versions = subparsers.add_parser('get-tool-supported-versions', help='Prints a list of tool\'s supported versions') + get_tool_supported_versions.add_argument('--tool-name', required=True, help='Tool name (from tools.json)') + args = parser.parse_args(argv) if args.action is None: @@ -2468,6 +2548,9 @@ def main(argv): # type: (list[str]) -> None global global_non_interactive global_non_interactive = True + if 'unset' in args and args.unset: + args.deactivate = True + global global_idf_path global_idf_path = os.environ.get('IDF_PATH') if args.idf_path: diff --git a/tools/kconfig_new/confgen.py b/tools/kconfig_new/confgen.py index 6b2d3fd33a..173b4e6098 100755 --- a/tools/kconfig_new/confgen.py +++ b/tools/kconfig_new/confgen.py @@ -22,7 +22,6 @@ from collections import defaultdict import gen_kconfig_doc import kconfiglib -from future.utils import iteritems __version__ = '0.1' @@ -39,8 +38,10 @@ class DeprecatedOptions(object): # r_dic maps deprecated options to new options; rev_r_dic maps in the opposite direction self.r_dic, self.rev_r_dic = self._parse_replacements(path_rename_files) - # note the '=' at the end of regex for not getting partial match of configs - self._RE_CONFIG = re.compile(r'{}(\w+)='.format(self.config_prefix)) + # note the '=' at the end of regex for not getting partial match of configs. + # Also match if the config option is followed by a whitespace, this is the case + # in sdkconfig.defaults files contaning "# CONFIG_MMM_NNN is not set". + self._RE_CONFIG = re.compile(r'{}(\w+)(=|\s+)'.format(self.config_prefix)) def _parse_replacements(self, repl_paths): rep_dic = {} @@ -175,21 +176,6 @@ class DeprecatedOptions(object): f_o.write('#define {}{} {}{}\n'.format(self.config_prefix, dep_opt, self.config_prefix, new_opt)) -def dict_enc_for_env(dic, encoding=sys.getfilesystemencoding() or 'utf-8'): - """ - This function can be deleted after dropping support for Python 2. - There is no rule for it that environment variables cannot be Unicode but usually people try to avoid it. - The upstream kconfiglib cannot detect strings properly if the environment variables are "unicode". This is problem - only in Python 2. - """ - if sys.version_info[0] >= 3: - return dic - ret = dict() - for (key, value) in iteritems(dic): - ret[key.encode(encoding)] = value.encode(encoding) - return ret - - def main(): parser = argparse.ArgumentParser(description='confgen.py v%s - Config Generation Tool' % __version__, prog=os.path.basename(sys.argv[0])) @@ -251,7 +237,7 @@ def main(): if args.env_file is not None: env = json.load(args.env_file) - os.environ.update(dict_enc_for_env(env)) + os.environ.update(env) config = kconfiglib.Kconfig(args.kconfig) config.warn_assign_redun = False diff --git a/tools/kconfig_new/confserver.py b/tools/kconfig_new/confserver.py index b0aed9aa35..f54dabcf8a 100755 --- a/tools/kconfig_new/confserver.py +++ b/tools/kconfig_new/confserver.py @@ -3,8 +3,6 @@ # Long-running server process uses stdin & stdout to communicate JSON # with a caller # -from __future__ import print_function - import argparse import json import os @@ -66,7 +64,7 @@ def main(): if args.env_file is not None: env = json.load(args.env_file) - os.environ.update(confgen.dict_enc_for_env(env)) + os.environ.update(env) run_server(args.kconfig, args.config, args.sdkconfig_rename) diff --git a/tools/kconfig_new/gen_kconfig_doc.py b/tools/kconfig_new/gen_kconfig_doc.py index 9cacb27d01..67479921e6 100644 --- a/tools/kconfig_new/gen_kconfig_doc.py +++ b/tools/kconfig_new/gen_kconfig_doc.py @@ -170,7 +170,7 @@ def get_link_anchor(node): try: return 'CONFIG_%s' % node.item.name except AttributeError: - assert(node_is_menu(node)) # only menus should have no item.name + assert node_is_menu(node) # only menus should have no item.name # for menus, build a link anchor out of the parents result = [] diff --git a/tools/kconfig_new/test/confgen/test_confgen.py b/tools/kconfig_new/test/confgen/test_confgen.py index 00a57c315a..903743184c 100755 --- a/tools/kconfig_new/test/confgen/test_confgen.py +++ b/tools/kconfig_new/test/confgen/test_confgen.py @@ -8,8 +8,6 @@ import tempfile import textwrap import unittest -from future.utils import iteritems - class ConfgenBaseTestCase(unittest.TestCase): @classmethod @@ -36,7 +34,7 @@ class ConfgenBaseTestCase(unittest.TestCase): def invoke_confgen(self, args): call_args = [sys.executable, '../../confgen.py'] - for (k, v) in iteritems(args): + for (k, v) in args.items(): if k != 'output': if isinstance(v, type('')): # easy Python 2/3 compatible str/unicode call_args += ['--{}'.format(k), v] @@ -170,6 +168,55 @@ class ConfigTestCase(ConfgenBaseTestCase): self.invoke_and_test(self.input, 'CONFIG_UNKNOWN', 'not in') +class RenameConfigTestCase(ConfgenBaseTestCase): + @classmethod + def setUpClass(self): + super(RenameConfigTestCase, self).setUpClass() + # `args` attribute is a dictionary containing the parameters to pass to `confgen.py`. + # Specify the name of the output file, this will generate the argument `--output config`. + self.args.update({'output': 'config'}) + # Setup the KConfig file content in the `input` attribute. + # Let's define an option that is enabled by default, this is very important. + # Indeed, as we explicitly disables it by its former name below, rename will be considered as functional + # if the new name, `(CONFIG_)RENAMED_OPTION` is also disabled in the final configuration file. + self.input = """ + config RENAMED_OPTION + bool "Renamed option" + default y + """ + + def setUp(self): + super(RenameConfigTestCase, self).setUp() + # Setup the actual test. What we want to do is to have a configuration file containing which + # option should be enabled or not, this is the equivalent of the `sdkconfig` that we can find + # in the examples. + with tempfile.NamedTemporaryFile(mode='w+', prefix='test_confgen_', delete=False) as f: + self.addCleanup(os.remove, f.name) + # The current file name will be given to `confgen.py` after `--config` argument. + self.args.update({'config': f.name}) + # Specify the content of that configuration file, in our case, we want to explicitely + # have an option, which needs to be renamed, disabled/not set. + f.write(textwrap.dedent(""" + # CONFIG_NAMED_OPTION is not set + """)) + # The configuration file is ready, we need to prepare a `rename` configuration file which will + # provide the new name for `CONFIG_NAMED_OPTION` we defined above + with tempfile.NamedTemporaryFile(mode='w+', prefix='test_confgen_', delete=False) as f: + self.addCleanup(os.remove, f.name) + # Same as above, the following entry will result in the generation of `--sdkconfig-rename` + # parameter followed by the current temporary file name. + self.args.update({'sdkconfig-rename': f.name}) + # The content of our `rename` file is simple: replace `CONFIG_NAMED_OPTION` by `CONFIG_RENAMED_OPTION` + f.write(textwrap.dedent(""" + CONFIG_NAMED_OPTION CONFIG_RENAMED_OPTION + """)) + + def testRenamedOptionDisabled(self): + # Invoke the unit test, specify that the final `sdkconfig` generated must contain the string: + # "# CONFIG_RENAMED_OPTION is not set" + self.invoke_and_test(self.input, '# CONFIG_RENAMED_OPTION is not set') + + class HeaderTestCase(ConfgenBaseTestCase): @classmethod def setUpClass(self): diff --git a/tools/ldgen/ldgen.py b/tools/ldgen/ldgen.py index 767b34bbc7..5f19b7b553 100755 --- a/tools/ldgen/ldgen.py +++ b/tools/ldgen/ldgen.py @@ -21,14 +21,6 @@ from ldgen.linker_script import LinkerScript from ldgen.sdkconfig import SDKConfig from pyparsing import ParseException, ParseFatalException -try: - import confgen -except Exception: - parent_dir_name = os.path.dirname(os.path.dirname(os.path.realpath(__file__))) - kconfig_new_dir = os.path.abspath(parent_dir_name + '/kconfig_new') - sys.path.insert(0, kconfig_new_dir) - import confgen - def _update_environment(args): env = [(name, value) for (name,value) in (e.split('=',1) for e in args.env)] @@ -38,7 +30,7 @@ def _update_environment(args): if args.env_file is not None: env = json.load(args.env_file) - os.environ.update(confgen.dict_enc_for_env(env)) + os.environ.update(env) def main(): diff --git a/tools/ldgen/ldgen/generation.py b/tools/ldgen/ldgen/generation.py index f4e87d849e..2b67dec896 100644 --- a/tools/ldgen/ldgen/generation.py +++ b/tools/ldgen/ldgen/generation.py @@ -134,9 +134,9 @@ class EntityNode: def add_child(self, entity): child_specificity = self.entity.specificity.value + 1 - assert (child_specificity <= Entity.Specificity.SYMBOL.value) + assert child_specificity <= Entity.Specificity.SYMBOL.value name = entity[Entity.Specificity(child_specificity)] - assert (name and name != Entity.ALL) + assert name and name != Entity.ALL child = [c for c in self.children if c.name == name] assert (len(child) <= 1) @@ -174,7 +174,7 @@ class EntityNode: for sections in self.get_output_sections(): placement = self.placements[sections] if placement.is_significant(): - assert (placement.node == self) + assert placement.node == self keep = False sort = None diff --git a/tools/ldgen/ldgen/output_commands.py b/tools/ldgen/ldgen/output_commands.py index 7df4a85210..ae8e2b7027 100644 --- a/tools/ldgen/ldgen/output_commands.py +++ b/tools/ldgen/ldgen/output_commands.py @@ -65,7 +65,7 @@ class InputSectionDesc: """ def __init__(self, entity, sections, exclusions=None, keep=False, sort=None): - assert (entity.specificity != Entity.Specificity.SYMBOL) + assert entity.specificity != Entity.Specificity.SYMBOL self.entity = entity self.sections = set(sections) @@ -73,8 +73,8 @@ class InputSectionDesc: self.exclusions = set() if exclusions: - assert (not [e for e in exclusions if e.specificity == Entity.Specificity.SYMBOL or - e.specificity == Entity.Specificity.NONE]) + assert not [e for e in exclusions if e.specificity == Entity.Specificity.SYMBOL or + e.specificity == Entity.Specificity.NONE] self.exclusions = set(exclusions) else: self.exclusions = set() diff --git a/tools/mass_mfg/mfg_gen.py b/tools/mass_mfg/mfg_gen.py index 0d4dce1605..600b2d7371 100644 --- a/tools/mass_mfg/mfg_gen.py +++ b/tools/mass_mfg/mfg_gen.py @@ -4,15 +4,12 @@ # SPDX-License-Identifier: Apache-2.0 # -from __future__ import print_function - import argparse import csv import distutils.dir_util import os import sys - -from future.moves.itertools import zip_longest +from itertools import zip_longest try: idf_path = os.environ['IDF_PATH'] diff --git a/tools/mkdfu.py b/tools/mkdfu.py index 4cd2dacbe5..5c994e71ec 100755 --- a/tools/mkdfu.py +++ b/tools/mkdfu.py @@ -21,8 +21,6 @@ import zlib from collections import namedtuple from functools import partial -from future.utils import iteritems - try: import typing except ImportError: @@ -312,9 +310,9 @@ def main(): # type: () -> None with open(args.json) as f: files += [(int(addr, 0), - process_json_file(f_name)) for addr, f_name in iteritems(json.load(f)['flash_files'])] + process_json_file(f_name)) for addr, f_name in json.load(f)['flash_files'].items()] - files = sorted([(addr, f_name.decode('utf-8') if isinstance(f_name, type(b'')) else f_name) for addr, f_name in iteritems(dict(files))], + files = sorted([(addr, f_name) for addr, f_name in dict(files).items()], key=lambda x: x[0]) # remove possible duplicates and sort based on the address cmd_args = {'output_file': args.output_file, diff --git a/tools/mkuf2.py b/tools/mkuf2.py index e76bae895f..a81c086358 100755 --- a/tools/mkuf2.py +++ b/tools/mkuf2.py @@ -13,8 +13,6 @@ import struct from functools import partial from typing import Dict, List -from future.utils import iteritems - def round_up_int_div(n: int, d: int) -> int: # equivalent to math.ceil(n / d) @@ -66,7 +64,7 @@ class UF2Writer(object): md5_part = self._to_uint32(addr) md5_part += self._to_uint32(len_chunk) md5_part += hashlib.md5(chunk).digest() - assert(len(md5_part) == self.UF2_MD5_PART_SIZE) + assert len(md5_part) == self.UF2_MD5_PART_SIZE block += md5_part block += b'\x00' * (self.UF2_DATA_SIZE - self.UF2_MD5_PART_SIZE - len_chunk) @@ -172,15 +170,15 @@ def main() -> None: flash_dic = dict((x['offset'], x['file']) for x in bin_selection) except KeyError: print('Invalid binary was selected.') - valid = [k if all(x in v for x in ('offset', 'file')) else None for k, v in iteritems(json_content)] + valid = [k if all(x in v for x in ('offset', 'file')) else None for k, v in json_content.items()] print('Valid ones:', ' '.join(x for x in valid if x)) exit(1) else: flash_dic = json_content['flash_files'] - files += [(parse_addr(addr), process_json_file(f_name)) for addr, f_name in iteritems(flash_dic)] + files += [(parse_addr(addr), process_json_file(f_name)) for addr, f_name in flash_dic.items()] - files = sorted([(addr, f_name) for addr, f_name in iteritems(dict(files))], + files = sorted([(addr, f_name) for addr, f_name in dict(files).items()], key=lambda x: x[0]) # remove possible duplicates and sort based on the address cmd_args = {'output_file': args.output_file, diff --git a/tools/mocks/driver/CMakeLists.txt b/tools/mocks/driver/CMakeLists.txt index cb68badac0..218f7deb18 100644 --- a/tools/mocks/driver/CMakeLists.txt +++ b/tools/mocks/driver/CMakeLists.txt @@ -20,5 +20,3 @@ idf_component_mock(INCLUDE_DIRS ${include_dirs} ${original_driver_dir}/include/driver/spi_common.h ${original_driver_dir}/include/driver/i2c.h ${original_driver_dir}/include/driver/gpio.h) - -idf_build_set_property(COMPILE_DEFINITIONS "-DSPI_MOCK" APPEND) diff --git a/tools/mocks/esp-tls/CMakeLists.txt b/tools/mocks/esp-tls/CMakeLists.txt new file mode 100644 index 0000000000..ffe9866874 --- /dev/null +++ b/tools/mocks/esp-tls/CMakeLists.txt @@ -0,0 +1,12 @@ +# NOTE: This kind of mocking currently works on Linux targets only. +# On Espressif chips, too many dependencies are missing at the moment. +message(STATUS "building ESP-TLS MOCKS") + +idf_component_get_property(original_esp_tls_dir esp-tls COMPONENT_OVERRIDEN_DIR) + +idf_component_mock(INCLUDE_DIRS "${original_esp_tls_dir}" + "${original_esp_tls_dir}/esp-tls-crypto" + MOCK_HEADER_FILES ${original_esp_tls_dir}/esp_tls.h + ${original_esp_tls_dir}/esp-tls-crypto/esp_tls_crypto.h + ) +target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-array-parameter) diff --git a/tools/mocks/esp-tls/mock/mock_config.yaml b/tools/mocks/esp-tls/mock/mock_config.yaml new file mode 100644 index 0000000000..60a445dc0c --- /dev/null +++ b/tools/mocks/esp-tls/mock/mock_config.yaml @@ -0,0 +1,16 @@ + +:cmock: + :plugins: + - expect + - expect_any_args + - return_thru_ptr + - ignore + - ignore_arg + :when_ptr: :compare_ptr + :strippables: + - '(?:esp_tls_cfg_server_session_tickets_init\s*\(+.*?\)+)' + - '(?:esp_tls_cfg_server_session_tickets_free\s*\(+.*?\)+)' + - '(?:esp_tls_server_session_create\s*\(+.*?\)+)' + - '(?:esp_tls_get_global_ca_store\s*\(+.*?\)+)' + - '(?:esp_tls_get_client_session\s*\(+.*?\)+)' + - '(?:esp_tls_free_client_session\s*\(+.*?\)+)' diff --git a/tools/mocks/esp_event/CMakeLists.txt b/tools/mocks/esp_event/CMakeLists.txt new file mode 100644 index 0000000000..24629a6ef6 --- /dev/null +++ b/tools/mocks/esp_event/CMakeLists.txt @@ -0,0 +1,10 @@ +# NOTE: This kind of mocking currently works on Linux targets only. +# On Espressif chips, too many dependencies are missing at the moment. +message(STATUS "building ESP EVENT MOCKS") + +idf_component_get_property(original_esp_event_dir esp_event COMPONENT_OVERRIDEN_DIR) + +idf_component_mock(INCLUDE_DIRS "${original_esp_event_dir}/include" + MOCK_HEADER_FILES ${original_esp_event_dir}/include/esp_event.h + ${original_esp_event_dir}/include/esp_event_base.h + ) diff --git a/tools/mocks/esp_event/mock/mock_config.yaml b/tools/mocks/esp_event/mock/mock_config.yaml new file mode 100644 index 0000000000..596255b0ce --- /dev/null +++ b/tools/mocks/esp_event/mock/mock_config.yaml @@ -0,0 +1,9 @@ + :cmock: + :plugins: + - expect + - expect_any_args + - return_thru_ptr + - array + - ignore + - ignore_arg + - callback diff --git a/tools/mocks/esp_hw_support/CMakeLists.txt b/tools/mocks/esp_hw_support/CMakeLists.txt new file mode 100644 index 0000000000..724c3b42a4 --- /dev/null +++ b/tools/mocks/esp_hw_support/CMakeLists.txt @@ -0,0 +1,10 @@ +# NOTE: This kind of mocking currently works on Linux targets only. +# On Espressif chips, too many dependencies are missing at the moment. +message(STATUS "building ESP HW SUPPORT MOCKS") + +idf_component_get_property(original_esp_hw_support_dir esp_hw_support COMPONENT_OVERRIDEN_DIR) + +idf_component_mock(INCLUDE_DIRS "${original_esp_hw_support_dir}/include" + MOCK_HEADER_FILES ${original_esp_hw_support_dir}/include/esp_mac.h + ${original_esp_hw_support_dir}/include/esp_random.h + ) diff --git a/tools/mocks/esp_hw_support/mock/mock_config.yaml b/tools/mocks/esp_hw_support/mock/mock_config.yaml new file mode 100644 index 0000000000..e250ea354d --- /dev/null +++ b/tools/mocks/esp_hw_support/mock/mock_config.yaml @@ -0,0 +1,7 @@ + :cmock: + :plugins: + - expect + - expect_any_args + - ignore + - ignore_arg + - return_thru_ptr diff --git a/tools/mocks/freertos/CMakeLists.txt b/tools/mocks/freertos/CMakeLists.txt index 4409be36f3..a72dee3577 100644 --- a/tools/mocks/freertos/CMakeLists.txt +++ b/tools/mocks/freertos/CMakeLists.txt @@ -1,18 +1,25 @@ # NOTE: This kind of mocking currently works on Linux targets only. # On Espressif chips, too many dependencies are missing at the moment. -message(STATUS "building FREERTOS MOCKS (only task and queue)") +message(STATUS "building FREERTOS MOCKS (only task, event-groups and queue)") idf_component_get_property(original_freertos_dir freertos COMPONENT_OVERRIDEN_DIR) +set(kernel_dir "${original_freertos_dir}/FreeRTOS-Kernel") + set(include_dirs - "${original_freertos_dir}/FreeRTOS-Kernel/include" + "${kernel_dir}/include" "${original_freertos_dir}/esp_additions/include" "${original_freertos_dir}/esp_additions/include/freertos" - "${original_freertos_dir}/FreeRTOS-Kernel/include/freertos" # this is due to the way includes are generated in CMock - "${original_freertos_dir}/FreeRTOS-Kernel/portable/linux/include") + "${kernel_dir}/portable/linux/include" # For FreeRTOSConfig_arch.h + "${kernel_dir}/include/freertos" # this is due to the way includes are generated in CMock (without freertos prefix) +) idf_component_mock(INCLUDE_DIRS ${include_dirs} REQUIRES esp_common MOCK_HEADER_FILES ${original_freertos_dir}/FreeRTOS-Kernel/include/freertos/task.h + ${original_freertos_dir}/FreeRTOS-Kernel/include/freertos/event_groups.h ${original_freertos_dir}/FreeRTOS-Kernel/include/freertos/queue.h) + +idf_component_get_property(freertos_lib freertos COMPONENT_LIB) +target_compile_definitions(${freertos_lib} PUBLIC "projCOVERAGE_TEST=0") diff --git a/tools/mocks/freertos/Kconfig b/tools/mocks/freertos/Kconfig index ddb265003a..3a2d4786a7 100644 --- a/tools/mocks/freertos/Kconfig +++ b/tools/mocks/freertos/Kconfig @@ -1,13 +1,22 @@ menu "FreeRTOS" - config FREERTOS_MAX_TASK_NAME_LEN - int "Maximum task name length" - range 1 256 - default 16 - help - Changes the maximum task name length. Each task allocated will - include this many bytes for a task name. Using a shorter value - saves a small amount of RAM, a longer value allows more complex - names. - For most uses, the default of 16 is OK. + menu "Kernel" + config FREERTOS_HZ + int "configTICK_RATE_HZ" + range 1 1000 + default 1000 + help + Sets the FreeRTOS tick interrupt frequency in Hz (see configTICK_RATE_HZ documentation for more + details). + + config FREERTOS_MAX_TASK_NAME_LEN + int "configMAX_TASK_NAME_LEN" + range 1 256 + default 16 + help + Sets the maximum number of characters for task names (see configMAX_TASK_NAME_LEN documentation for + more details). + + Note: For most uses, the default of 16 characters is sufficient. + endmenu endmenu diff --git a/tools/mocks/freertos/mock/mock_config.yaml b/tools/mocks/freertos/mock/mock_config.yaml index dad1a6e2a4..9b7eab92eb 100644 --- a/tools/mocks/freertos/mock/mock_config.yaml +++ b/tools/mocks/freertos/mock/mock_config.yaml @@ -1,21 +1,22 @@ - :cmock: - :includes_h_pre_orig_header: - - FreeRTOS.h - :plugins: - - expect - - expect_any_args - - return_thru_ptr - - array - - ignore - - ignore_arg - - callback - :strippables: - - '(?:__attribute__\s*\(+.*?\)+)' - # following functions are disabled by configQUEUE_REGISTRY_SIZE - - '(?:vQueueAddToRegistry\s*\([\s\w\*_,]*\))' - - '(?:vQueueUnregisterQueue\s*\([\s\w\*_,]*\))' - - '(?:pcQueueGetName\s*\([\s\w\*_,]*\))' - # following function is disabled by configTHREAD_LOCAL_STORAGE_DELETE_CALLBACKS - - '(?:vTaskSetThreadLocalStoragePointerAndDelCallback\s*\([\s\w\*_,]*\))' - - PRIVILEGED_FUNCTION - - portDONT_DISCARD +:cmock: + :includes_h_pre_orig_header: + - FreeRTOSConfig.h + - FreeRTOS.h + :plugins: + - expect + - expect_any_args + - return_thru_ptr + - array + - ignore + - ignore_arg + - callback + :strippables: + - '(?:__attribute__\s*\(+.*?\)+)' + # following functions are disabled by configQUEUE_REGISTRY_SIZE + - '(?:vQueueAddToRegistry\s*\([\s\w\*_,]*\))' + - '(?:vQueueUnregisterQueue\s*\([\s\w\*_,]*\))' + - '(?:pcQueueGetName\s*\([\s\w\*_,]*\))' + # following function is disabled by configTHREAD_LOCAL_STORAGE_DELETE_CALLBACKS + - '(?:vTaskSetThreadLocalStoragePointerAndDelCallback\s*\([\s\w\*_,]*\))' + - PRIVILEGED_FUNCTION + - portDONT_DISCARD diff --git a/tools/mocks/hal/include/hal/gpio_types.h b/tools/mocks/hal/include/hal/gpio_types.h index 29797e0dea..9311b611f4 100644 --- a/tools/mocks/hal/include/hal/gpio_types.h +++ b/tools/mocks/hal/include/hal/gpio_types.h @@ -95,17 +95,6 @@ typedef enum { GPIO_PULLDOWN_ENABLE = 0x1, /*!< Enable GPIO pull-down resistor */ } gpio_pulldown_t; -/** - * @brief Configuration parameters of GPIO pad for gpio_config function - */ -typedef struct { - uint64_t pin_bit_mask; /*!< GPIO pin: set with bit mask, each bit maps to a GPIO */ - gpio_mode_t mode; /*!< GPIO mode: set input/output mode */ - gpio_pullup_t pull_up_en; /*!< GPIO pull-up */ - gpio_pulldown_t pull_down_en; /*!< GPIO pull-down */ - gpio_int_type_t intr_type; /*!< GPIO interrupt type */ -} gpio_config_t; - typedef enum { GPIO_PULLUP_ONLY, /*!< Pad pull up */ GPIO_PULLDOWN_ONLY, /*!< Pad pull down */ @@ -122,8 +111,6 @@ typedef enum { GPIO_DRIVE_CAP_MAX, } gpio_drive_cap_t; -typedef void (*gpio_isr_t)(void *); - #ifdef __cplusplus } #endif diff --git a/tools/mocks/hal/include/hal/i2c_types.h b/tools/mocks/hal/include/hal/i2c_types.h index 1eaf5216ab..ad76ed43e7 100644 --- a/tools/mocks/hal/include/hal/i2c_types.h +++ b/tools/mocks/hal/include/hal/i2c_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,7 +17,16 @@ extern "C" { #endif -typedef int i2c_port_t; +/** + * @brief I2C port number, can be I2C_NUM_0 ~ (I2C_NUM_MAX-1). + */ +typedef enum { + I2C_NUM_0 = 0, /*!< I2C port 0 */ +#if SOC_I2C_NUM >= 2 + I2C_NUM_1, /*!< I2C port 1 */ +#endif + I2C_NUM_MAX, /*!< I2C port max */ +} i2c_port_t; typedef enum{ I2C_MODE_SLAVE = 0, /*!< I2C slave mode */ diff --git a/tools/mocks/http_parser/CMakeLists.txt b/tools/mocks/http_parser/CMakeLists.txt new file mode 100644 index 0000000000..7050914da3 --- /dev/null +++ b/tools/mocks/http_parser/CMakeLists.txt @@ -0,0 +1,8 @@ +# NOTE: This kind of mocking currently works on Linux targets only. +# On Espressif chips, too many dependencies are missing at the moment. +message(STATUS "building HTTP PARSER MOCKS") + +idf_component_get_property(original_http_parser_dir http_parser COMPONENT_OVERRIDEN_DIR) + +idf_component_mock(INCLUDE_DIRS "${original_http_parser_dir}" + MOCK_HEADER_FILES ${original_http_parser_dir}/http_parser.h) diff --git a/tools/mocks/http_parser/mock/mock_config.yaml b/tools/mocks/http_parser/mock/mock_config.yaml new file mode 100644 index 0000000000..1923353c61 --- /dev/null +++ b/tools/mocks/http_parser/mock/mock_config.yaml @@ -0,0 +1,9 @@ +:cmock: + :plugins: + - expect + - expect_any_args + - return_thru_ptr + - array + - ignore + - ignore_arg + - callback diff --git a/tools/mocks/lwip/CMakeLists.txt b/tools/mocks/lwip/CMakeLists.txt new file mode 100644 index 0000000000..ea9f075886 --- /dev/null +++ b/tools/mocks/lwip/CMakeLists.txt @@ -0,0 +1,10 @@ +# NOTE: This kind of mocking currently works on Linux targets only. +# On Espressif chips, too many dependencies are missing at the moment. +message(STATUS "building LWIP MOCKS (only netdb)") + +idf_component_get_property(original_lwip_dir lwip COMPONENT_OVERRIDEN_DIR) + +idf_component_mock(INCLUDE_DIRS "${original_lwip_dir}/port" + "${original_lwip_dir}/include/lwip" + "${original_lwip_dir}/lwip/src/include" + MOCK_HEADER_FILES ${original_lwip_dir}/lwip/src/include/lwip/netdb.h ) diff --git a/tools/mocks/lwip/mock/mock_config.yaml b/tools/mocks/lwip/mock/mock_config.yaml new file mode 100644 index 0000000000..596255b0ce --- /dev/null +++ b/tools/mocks/lwip/mock/mock_config.yaml @@ -0,0 +1,9 @@ + :cmock: + :plugins: + - expect + - expect_any_args + - return_thru_ptr + - array + - ignore + - ignore_arg + - callback diff --git a/tools/mocks/tcp_transport/CMakeLists.txt b/tools/mocks/tcp_transport/CMakeLists.txt new file mode 100644 index 0000000000..9ff6b93510 --- /dev/null +++ b/tools/mocks/tcp_transport/CMakeLists.txt @@ -0,0 +1,13 @@ +# NOTE: This kind of mocking currently works on Linux targets only. +# On Espressif chips, too many dependencies are missing at the moment. +message(STATUS "building TCP TRANSPORT MOCKS") + +idf_component_get_property(original_tcp_transport_dir tcp_transport COMPONENT_OVERRIDEN_DIR) + +idf_component_mock(INCLUDE_DIRS "${original_tcp_transport_dir}/include" + MOCK_HEADER_FILES ${original_tcp_transport_dir}/include/esp_transport.h + ${original_tcp_transport_dir}/include/esp_transport_tcp.h + ${original_tcp_transport_dir}/include/esp_transport_ssl.h + ${original_tcp_transport_dir}/include/esp_transport_ws.h + REQUIRES esp-tls + ) diff --git a/tools/mocks/tcp_transport/mock/mock_config.yaml b/tools/mocks/tcp_transport/mock/mock_config.yaml new file mode 100644 index 0000000000..fcf2722bc1 --- /dev/null +++ b/tools/mocks/tcp_transport/mock/mock_config.yaml @@ -0,0 +1,9 @@ +:cmock: + :plugins: + - expect + - expect_any_args + - return_thru_ptr + - ignore + - ignore_arg + - callback + :when_ptr: :compare_ptr diff --git a/tools/requirements/requirements.ci.txt b/tools/requirements/requirements.ci.txt index b183644fec..f40bb9e205 100644 --- a/tools/requirements/requirements.ci.txt +++ b/tools/requirements/requirements.ci.txt @@ -4,6 +4,8 @@ # ci coverage idf-build-apps +jsonschema junit_xml python-gitlab pyyaml +SimpleWebSocketServer diff --git a/tools/requirements/requirements.core.txt b/tools/requirements/requirements.core.txt index fc3cb0b48a..d433d99b86 100644 --- a/tools/requirements/requirements.core.txt +++ b/tools/requirements/requirements.core.txt @@ -3,7 +3,6 @@ setuptools click pyserial -future cryptography pyparsing pyelftools diff --git a/tools/requirements/requirements.pytest.txt b/tools/requirements/requirements.pytest.txt index fb84dc624f..5e7e2cd746 100644 --- a/tools/requirements/requirements.pytest.txt +++ b/tools/requirements/requirements.pytest.txt @@ -14,5 +14,5 @@ scapy websocket-client netifaces rangehttpserver -dbus-python; sys_platform != 'win32' +dbus-python; sys_platform == 'linux' protobuf diff --git a/tools/requirements/requirements.ttfw.txt b/tools/requirements/requirements.ttfw.txt index ed7cb2187f..6203f1dfc2 100644 --- a/tools/requirements/requirements.ttfw.txt +++ b/tools/requirements/requirements.ttfw.txt @@ -17,7 +17,7 @@ pygdbmi # ble future -dbus-python; sys_platform != 'win32' +dbus-python; sys_platform == 'linux' pygobject; sys_platform != 'win32' # iperf_test_util @@ -33,3 +33,7 @@ SimpleWebSocketServer # py_debug_backend debug_backend + +# examples/protocols/mqtt +# tools/test_apps/protocols/mqtt +paho-mqtt diff --git a/tools/test_apps/.build-test-rules.yml b/tools/test_apps/.build-test-rules.yml index 8bc316fe55..73e5a262bc 100644 --- a/tools/test_apps/.build-test-rules.yml +++ b/tools/test_apps/.build-test-rules.yml @@ -11,6 +11,14 @@ tools/test_apps/build_system/ldgen_test: temporary: true reason: target esp32c2 is not supported yet +tools/test_apps/linux_compatible/hello_world_linux_compatible: + enable: + - if: INCLUDE_DEFAULT == 1 or IDF_TARGET == "linux" + disable_test: + - if: IDF_TARGET not in ["esp32", "esp32c3"] + temporary: true + reason: pytest doesn't support linux target yet, hence, it's tested independenly in the host_tests stage + tools/test_apps/peripherals/usb: enable: - if: IDF_TARGET in ["esp32s2", "esp32s3"] @@ -95,7 +103,7 @@ tools/test_apps/system/flash_psram: tools/test_apps/system/g0_components: enable: - - if: INCLUDE_DEFAULT == 1 or IDF_TARGET == "esp32h2" + - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["esp32h2", "esp32c6"] # preview targets tools/test_apps/system/g1_components: disable: diff --git a/tools/test_apps/linux_compatible/hello_world_linux_compatible/CMakeLists.txt b/tools/test_apps/linux_compatible/hello_world_linux_compatible/CMakeLists.txt new file mode 100644 index 0000000000..827441ca4c --- /dev/null +++ b/tools/test_apps/linux_compatible/hello_world_linux_compatible/CMakeLists.txt @@ -0,0 +1,7 @@ +# The following lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +set(COMPONENTS main) +project(hello_world) diff --git a/tools/test_apps/linux_compatible/hello_world_linux_compatible/README.md b/tools/test_apps/linux_compatible/hello_world_linux_compatible/README.md new file mode 100644 index 0000000000..2a5c7d4293 --- /dev/null +++ b/tools/test_apps/linux_compatible/hello_world_linux_compatible/README.md @@ -0,0 +1,45 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | Linux | +| ----------------- | ----- | -------- | -------- | -------- | -------- | ----- | + +# Hello World Example Compatible with POSIX-port + +This is a version of the "Hello World" example compatible with the linux target. Just by using `idf.py (--preview) set-target `, it can be compiled for chip targets as well as for the [FreeRTOS POSIX/Linux simulator](https://www.freertos.org/FreeRTOS-simulator-for-Linux.html), i.e., for running it on Linux. The applications can then be run on the chosen target. + +## Requirements + +If you want to use this example on Linux, you need a Linux machine as host. The remaining requirements are the same requirements as for [Unit Testing on Linux (using cmock)](https://docs.espressif.com/projects/esp-idf/en/stable/esp32/api-guides/linux-host-testing.html#requirements), except you do not need Ruby. + +## How to use example + +### Configure the project + +No special configuration is required, we also do not recommend changing configuration when compiled for the POSIX/Linux simulator as this is still in preview. If you have to configure something, use the usual IDF menuconfig: +``` +idf.py menuconfig +``` + +### Build and Flash + +You can compile this example for chip targets, e.g. ESP32 and then run it by using: +``` +idf.py set-target esp32 +idf.py build +idf.py -p flash monitor +``` + +If you want to build this example for the linux target and run it, use the same commands except setting the linux target and omitting the flash command: +``` +idf.py --preview set-target linux +idf.by build +idf.py monitor +``` +The linux target is still in preview, hence the necessary `--preview` argument. Flashing can be omitted on Linux. + + +## Example folder contents + +The files in this project have the same structure as the files in the [original Hello World application](../../../../examples/get-started/hello_world/). + +## Example Output + +The output is similar to the output of the [original Hello World application](../../../../examples/get-started/hello_world/), except that no chip information is printed and there won't be any bootloader output on the linux target. diff --git a/tools/test_apps/linux_compatible/hello_world_linux_compatible/main/CMakeLists.txt b/tools/test_apps/linux_compatible/hello_world_linux_compatible/main/CMakeLists.txt new file mode 100644 index 0000000000..392c049cbf --- /dev/null +++ b/tools/test_apps/linux_compatible/hello_world_linux_compatible/main/CMakeLists.txt @@ -0,0 +1,4 @@ +idf_component_register(SRCS "hello_world_main.c" + INCLUDE_DIRS "") + +target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/tools/test_apps/linux_compatible/hello_world_linux_compatible/main/hello_world_main.c b/tools/test_apps/linux_compatible/hello_world_linux_compatible/main/hello_world_main.c new file mode 100644 index 0000000000..988ea320fc --- /dev/null +++ b/tools/test_apps/linux_compatible/hello_world_linux_compatible/main/hello_world_main.c @@ -0,0 +1,24 @@ +/* + * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: CC0-1.0 + */ + +#include +#include +#include "sdkconfig.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + +void app_main(void) +{ + printf("Hello world!\n"); + + for (int i = 10; i >= 0; i--) { + printf("Restarting in %d seconds...\n", i); + vTaskDelay(1000 / portTICK_PERIOD_MS); + } + printf("Restarting now.\n"); + fflush(stdout); + exit(0); +} diff --git a/tools/test_apps/linux_compatible/hello_world_linux_compatible/pytest_hello_world_linux_compatible.py b/tools/test_apps/linux_compatible/hello_world_linux_compatible/pytest_hello_world_linux_compatible.py new file mode 100644 index 0000000000..08e67cea7a --- /dev/null +++ b/tools/test_apps/linux_compatible/hello_world_linux_compatible/pytest_hello_world_linux_compatible.py @@ -0,0 +1,15 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +import pytest +from pytest_embedded_idf.dut import IdfDut + +# Note that support for Linux target console applications hasn't been implemented for pytest-embedded yet +# (https://github.com/espressif/pytest-embedded/issues/106) + + +@pytest.mark.esp32 +@pytest.mark.esp32c3 +@pytest.mark.generic +def test_hello_world_linux_compatible(dut: IdfDut) -> None: + dut.expect('Hello world!') diff --git a/tools/test_apps/peripherals/usb/CMakeLists.txt b/tools/test_apps/peripherals/usb/CMakeLists.txt deleted file mode 100644 index 8451ba1d94..0000000000 --- a/tools/test_apps/peripherals/usb/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -# The following lines of boilerplate have to be in your project's -# CMakeLists in this exact order for cmake to work correctly -cmake_minimum_required(VERSION 3.16) - -set(EXTRA_COMPONENT_DIRS $ENV{IDF_PATH}/examples/peripherals/usb/host/cdc/common - $ENV{IDF_PATH}/examples/peripherals/usb/host/msc/components/) - -# Set the components to include the tests for. -set(TEST_COMPONENTS "cdc_acm_host" "msc" CACHE STRING "List of components to test") -include($ENV{IDF_PATH}/tools/cmake/project.cmake) -project(usb_test_app) diff --git a/tools/test_apps/peripherals/usb/README.md b/tools/test_apps/peripherals/usb/README.md deleted file mode 100644 index 245f71285a..0000000000 --- a/tools/test_apps/peripherals/usb/README.md +++ /dev/null @@ -1,26 +0,0 @@ -| Supported Targets | ESP32-S2 | ESP32-S3 | -| ----------------- | -------- | -------- | - -# USB Host Class driver test project -Main purpose of this application is to test the USB Host Class drivers. - -## CDC-ACM driver - -It tests basic functionality of the driver like open/close/read/write operations, -advanced features like CDC control request, multi-threaded or multi-device access, -as well as reaction to sudden disconnection and other error states. - -### Hardware Required - -This test expects that TinyUSB dual CDC device with VID = 0x303A and PID = 0x4002 -is connected to the USB host. - -## MSC driver - -Basic functionality such as MSC device install/uninstall, file operatons, -raw access to MSC device and sudden disconnect is tested. - -### Hardware Required - -This test requires two ESP32-S2/S3 boards with a interconnected USB perpherals, -one acting as host running MSC host driver and another MSC device driver (tinyusb). diff --git a/tools/test_apps/peripherals/usb/main/CMakeLists.txt b/tools/test_apps/peripherals/usb/main/CMakeLists.txt deleted file mode 100644 index b25d15fabb..0000000000 --- a/tools/test_apps/peripherals/usb/main/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -idf_component_register(SRCS "usb_test_main.c" - INCLUDE_DIRS "" - REQUIRES unity driver usb) diff --git a/tools/test_apps/peripherals/usb/pytest_usb_host.py b/tools/test_apps/peripherals/usb/pytest_usb_host.py deleted file mode 100644 index d05b736625..0000000000 --- a/tools/test_apps/peripherals/usb/pytest_usb_host.py +++ /dev/null @@ -1,40 +0,0 @@ -# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD -# SPDX-License-Identifier: CC0-1.0 - -from typing import Tuple - -import pytest -from pytest_embedded_idf.dut import IdfDut - - -@pytest.mark.esp32s2 -@pytest.mark.esp32s3 -@pytest.mark.usb_host -@pytest.mark.parametrize('count', [ - 2, -], indirect=True) -def test_usb_host(dut: Tuple[IdfDut, IdfDut]) -> None: - device = dut[0] - host = dut[1] - - # 1.1 Prepare USB device for CDC test - device.expect_exact('Press ENTER to see the list of tests.') - device.write('[cdc_acm_device]') - device.expect_exact('USB initialization DONE') - - # 1.2 Run CDC test - host.expect_exact('Press ENTER to see the list of tests.') - host.write('[cdc_acm]') - host.expect_unity_test_output() - host.expect_exact("Enter next test, or 'enter' to see menu") - - # 2.1 Prepare USB device for MSC test - device.serial.hard_reset() - device.expect_exact('Press ENTER to see the list of tests.') - device.write('[usb_msc_device]') - device.expect_exact('USB initialization DONE') - - # 2.2 Run MSC test - host.write('[usb_msc]') - host.expect_unity_test_output() - host.expect_exact("Enter next test, or 'enter' to see menu") diff --git a/tools/test_apps/peripherals/usb/sdkconfig.defaults b/tools/test_apps/peripherals/usb/sdkconfig.defaults deleted file mode 100644 index bab404d696..0000000000 --- a/tools/test_apps/peripherals/usb/sdkconfig.defaults +++ /dev/null @@ -1,16 +0,0 @@ -# Configure TinyUSB, it will be used to mock USB devices -CONFIG_TINYUSB=y -CONFIG_TINYUSB_MSC_ENABLED=y -CONFIG_TINYUSB_CDC_ENABLED=y -CONFIG_TINYUSB_CDC_COUNT=2 - -# Disable watchdogs, they'd get triggered during unity interactive menu -CONFIG_ESP_INT_WDT=n -CONFIG_ESP_TASK_WDT=n - -# Run-time checks of Heap and Stack -CONFIG_HEAP_POISONING_COMPREHENSIVE=y -CONFIG_COMPILER_STACK_CHECK_MODE_STRONG=y -CONFIG_COMPILER_STACK_CHECK=y - -CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL=y diff --git a/tools/test_apps/protocols/mqtt/publish_connect_test/app_test.py b/tools/test_apps/protocols/mqtt/publish_connect_test/app_test.py index c4f28d27b9..f87c376357 100644 --- a/tools/test_apps/protocols/mqtt/publish_connect_test/app_test.py +++ b/tools/test_apps/protocols/mqtt/publish_connect_test/app_test.py @@ -31,7 +31,7 @@ def set_server_cert_cn(ip): '-CAkey', _path('ca.key'), '-CAcreateserial', '-out', _path('srv.crt'), '-days', '360']] for args in arg_list: if subprocess.check_call(args) != 0: - raise('openssl command {} failed'.format(args)) + raise RuntimeError('openssl command {} failed'.format(args)) # Publisher class creating a python client to send/receive published data from esp-mqtt client @@ -264,7 +264,7 @@ def connection_tests(dut, cases, dut_ip): dut.expect('MQTT_EVENT_ERROR: Test={}'.format(test_nr), timeout=30) dut.expect('ESP-TLS ERROR: ESP_ERR_MBEDTLS_SSL_HANDSHAKE_FAILED') # expect ... handshake error (PEER_DID_NOT_RETURN_A_CERTIFICATE) if 'PEER_DID_NOT_RETURN_A_CERTIFICATE' not in s.get_last_ssl_error(): - raise('Unexpected ssl error from the server {}'.format(s.get_last_ssl_error())) + raise RuntimeError('Unexpected ssl error from the server {}'.format(s.get_last_ssl_error())) for case in ['CONFIG_EXAMPLE_CONNECT_CASE_MUTUAL_AUTH', 'CONFIG_EXAMPLE_CONNECT_CASE_MUTUAL_AUTH_KEY_PWD']: # These cases connect to server with both server and client verification (client key might be password protected) diff --git a/tools/test_apps/system/bootloader_sections/sdkconfig.ci.rtc_retain b/tools/test_apps/system/bootloader_sections/sdkconfig.ci.rtc_retain index 3ba7ab36b7..5476981755 100644 --- a/tools/test_apps/system/bootloader_sections/sdkconfig.ci.rtc_retain +++ b/tools/test_apps/system/bootloader_sections/sdkconfig.ci.rtc_retain @@ -1 +1,2 @@ CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP=y +CONFIG_COMPILER_OPTIMIZATION_PERF=y diff --git a/tools/test_apps/system/build_test/sdkconfig.ci.rvfplib b/tools/test_apps/system/build_test/sdkconfig.ci.esp32c2_without_rvfplib similarity index 100% rename from tools/test_apps/system/build_test/sdkconfig.ci.rvfplib rename to tools/test_apps/system/build_test/sdkconfig.ci.esp32c2_without_rvfplib diff --git a/tools/test_apps/system/build_test/sdkconfig.ci.esp32c6_with_rom_impl_components b/tools/test_apps/system/build_test/sdkconfig.ci.esp32c6_with_rom_impl_components new file mode 100644 index 0000000000..cb561f4977 --- /dev/null +++ b/tools/test_apps/system/build_test/sdkconfig.ci.esp32c6_with_rom_impl_components @@ -0,0 +1,5 @@ +CONFIG_IDF_TARGET="esp32c6" +CONFIG_HAL_WDT_USE_ROM_IMPL=y +CONFIG_HAL_SYSTIMER_USE_ROM_IMPL=y +CONFIG_HEAP_TLSF_USE_ROM_IMPL=y +CONFIG_SPI_FLASH_ROM_IMPL=y diff --git a/tools/test_apps/system/build_test/sdkconfig.ci.esp32c6_without_rom_impl_components b/tools/test_apps/system/build_test/sdkconfig.ci.esp32c6_without_rom_impl_components new file mode 100644 index 0000000000..ee55ffa744 --- /dev/null +++ b/tools/test_apps/system/build_test/sdkconfig.ci.esp32c6_without_rom_impl_components @@ -0,0 +1,5 @@ +CONFIG_IDF_TARGET="esp32c6" +CONFIG_HAL_WDT_USE_ROM_IMPL=n +CONFIG_HAL_SYSTIMER_USE_ROM_IMPL=n +CONFIG_HEAP_TLSF_USE_ROM_IMPL=n +CONFIG_SPI_FLASH_ROM_IMPL=n diff --git a/tools/test_apps/system/build_test/sdkconfig.ci.esp32c6_without_rvfplib b/tools/test_apps/system/build_test/sdkconfig.ci.esp32c6_without_rvfplib new file mode 100644 index 0000000000..e82ca0e1f0 --- /dev/null +++ b/tools/test_apps/system/build_test/sdkconfig.ci.esp32c6_without_rvfplib @@ -0,0 +1,2 @@ +CONFIG_IDF_TARGET="esp32c6" +CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB=y diff --git a/tools/test_apps/system/build_test/sdkconfig.ci.o2_no_asserts b/tools/test_apps/system/build_test/sdkconfig.ci.o2_no_asserts new file mode 100644 index 0000000000..e267df30e6 --- /dev/null +++ b/tools/test_apps/system/build_test/sdkconfig.ci.o2_no_asserts @@ -0,0 +1,2 @@ +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE=y +CONFIG_COMPILER_OPTIMIZATION_PERF=y diff --git a/tools/test_apps/system/cxx_build_test/main/CMakeLists.txt b/tools/test_apps/system/cxx_build_test/main/CMakeLists.txt index ece9736565..df82785cfb 100644 --- a/tools/test_apps/system/cxx_build_test/main/CMakeLists.txt +++ b/tools/test_apps/system/cxx_build_test/main/CMakeLists.txt @@ -1,4 +1,5 @@ idf_component_register(SRCS cxx_build_test_main.cpp test_soc_reg_macros.cpp INCLUDE_DIRS "." + PRIV_REQUIRES driver REQUIRES soc) diff --git a/tools/test_apps/system/cxx_build_test/main/cxx_build_test_main.cpp b/tools/test_apps/system/cxx_build_test/main/cxx_build_test_main.cpp index 3196de6e05..94b9f3787f 100644 --- a/tools/test_apps/system/cxx_build_test/main/cxx_build_test_main.cpp +++ b/tools/test_apps/system/cxx_build_test/main/cxx_build_test_main.cpp @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ #include +#include "driver/mcpwm_prelude.h" extern "C" void app_main(void) { diff --git a/tools/test_apps/system/flash_psram/pytest_flash_psram.py b/tools/test_apps/system/flash_psram/pytest_flash_psram.py index 1cadd1a736..e52c14653e 100644 --- a/tools/test_apps/system/flash_psram/pytest_flash_psram.py +++ b/tools/test_apps/system/flash_psram/pytest_flash_psram.py @@ -36,4 +36,4 @@ MSPI_F4R4_configs = [p.name.replace('sdkconfig.ci.', '') for p in pathlib.Path(o @pytest.mark.MSPI_F4R4 @pytest.mark.parametrize('config', MSPI_F4R4_configs, indirect=True) def test_flash4_psram4(dut: Dut) -> None: - dut.expect_exact('flash psram test success') + dut.expect_exact('flash psram test success', timeout=40) diff --git a/tools/test_apps/system/g0_components/CMakeLists.txt b/tools/test_apps/system/g0_components/CMakeLists.txt index f5fd24076a..d6433b7fce 100644 --- a/tools/test_apps/system/g0_components/CMakeLists.txt +++ b/tools/test_apps/system/g0_components/CMakeLists.txt @@ -28,7 +28,7 @@ project(g0_components) # As a workaround for ESP32-C2, we need to define the MMU page size here, until MMU hal-driver # is refactored -if(CONFIG_IDF_TARGET_ESP32C2) +if(CONFIG_IDF_TARGET_ESP32C2 OR CONFIG_IDF_TARGET_ESP32C6) idf_build_set_property(C_COMPILE_OPTIONS "-DCONFIG_MMU_PAGE_SIZE=64" APPEND) endif() diff --git a/tools/test_apps/system/g0_components/README.md b/tools/test_apps/system/g0_components/README.md index 420e59a67a..bea7ca0e46 100644 --- a/tools/test_apps/system/g0_components/README.md +++ b/tools/test_apps/system/g0_components/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-H2 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # "G0"-components-only app diff --git a/tools/test_apps/system/g1_components/CMakeLists.txt b/tools/test_apps/system/g1_components/CMakeLists.txt index 7c69876019..0380cdd395 100644 --- a/tools/test_apps/system/g1_components/CMakeLists.txt +++ b/tools/test_apps/system/g1_components/CMakeLists.txt @@ -21,8 +21,8 @@ set(extra_allowed_components # These components are currently included into "G1" build, but shouldn't. # After removing the extra dependencies, remove the components from this list as well. set(extra_components_which_shouldnt_be_included - # app_update gets added because of bootloader_support, spi_flash, espcoredump. - # bootloader_support, spi_flash, espcoredump should be removed from dependencies; + # app_update gets added because of spi_flash. + # spi_flash should be removed from dependencies; app_update # of G1 components, bootloader is only included from spi_flash # [refactor-todo]: see if this dependency from spi_flash can be made weak @@ -36,6 +36,8 @@ set(extra_components_which_shouldnt_be_included # [refactor-todo]: driver is a dependency of esp_pm, esp_timer, spi_flash, vfs, esp_wifi, ${IDF_TARGET} # all of these should be removed from G1 except for spi_flash. driver + # esp_app_format is dependency of bootloader_support, app_update + esp_app_format # [refactor-todo]: efuse is a dependency of esp_hw_support, esp_system. # Figure out if these components can exist without a dependency on efuse. # If not, see if esp_hw_support can provide minimal efuse component replacement in G1 build. diff --git a/tools/test_apps/system/gdb/CMakeLists.txt b/tools/test_apps/system/gdb/CMakeLists.txt new file mode 100644 index 0000000000..1c0bd70903 --- /dev/null +++ b/tools/test_apps/system/gdb/CMakeLists.txt @@ -0,0 +1,6 @@ +# The following lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(gdb) diff --git a/tools/test_apps/system/gdb/README.md b/tools/test_apps/system/gdb/README.md new file mode 100644 index 0000000000..0b4b22e8c3 --- /dev/null +++ b/tools/test_apps/system/gdb/README.md @@ -0,0 +1,6 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | + +# IDF GDB test application + +This project tests if `idf.py gdb` works correct diff --git a/tools/test_apps/system/gdb/main/CMakeLists.txt b/tools/test_apps/system/gdb/main/CMakeLists.txt new file mode 100644 index 0000000000..69def7bc1d --- /dev/null +++ b/tools/test_apps/system/gdb/main/CMakeLists.txt @@ -0,0 +1,3 @@ +idf_component_register(SRCS "hello_world_main.c" + INCLUDE_DIRS "") +target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/tools/test_apps/system/gdb/main/hello_world_main.c b/tools/test_apps/system/gdb/main/hello_world_main.c new file mode 100644 index 0000000000..915866a4c2 --- /dev/null +++ b/tools/test_apps/system/gdb/main/hello_world_main.c @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: CC0-1.0 + */ + +#include +#include "sdkconfig.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "esp_chip_info.h" +#include "esp_flash.h" + +void app_main(void) +{ + printf("Hello world!\n"); + + /* Print chip information */ + esp_chip_info_t chip_info; + uint32_t flash_size; + esp_chip_info(&chip_info); + printf("This is %s chip with %d CPU core(s), WiFi%s%s, ", + CONFIG_IDF_TARGET, + chip_info.cores, + (chip_info.features & CHIP_FEATURE_BT) ? "/BT" : "", + (chip_info.features & CHIP_FEATURE_BLE) ? "/BLE" : ""); + + printf("silicon revision %d, ", chip_info.revision); + if(esp_flash_get_size(NULL, &flash_size) != ESP_OK) { + printf("Get flash size failed"); + return; + } + + printf("%uMB %s flash\n", flash_size / (1024 * 1024), + (chip_info.features & CHIP_FEATURE_EMB_FLASH) ? "embedded" : "external"); + + printf("Minimum free heap size: %d bytes\n", esp_get_minimum_free_heap_size()); + + for (int i = 10; i >= 0; i--) { + printf("Restarting in %d seconds...\n", i); + vTaskDelay(1000 / portTICK_PERIOD_MS); + } + printf("Restarting now.\n"); + fflush(stdout); + esp_restart(); +} diff --git a/tools/test_apps/system/gdb/pytest_gdb.py b/tools/test_apps/system/gdb/pytest_gdb.py new file mode 100644 index 0000000000..0bb16d8e81 --- /dev/null +++ b/tools/test_apps/system/gdb/pytest_gdb.py @@ -0,0 +1,53 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Unlicense OR CC0-1.0 +import os +import re +import signal +import subprocess +import sys + +import pexpect +import pytest +from pytest_embedded import Dut + +try: + from idf_py_actions.debug_ext import get_openocd_arguments +except ModuleNotFoundError: + sys.path.append(os.path.join(os.path.dirname(__file__), '..', '..', '..')) + from idf_py_actions.debug_ext import get_openocd_arguments + + +@pytest.mark.supported_targets +@pytest.mark.test_jtag_arm +def test_idf_gdb(dut: Dut) -> None: + # Need to wait a moment to connect via OpenOCD after the hard reset happened. + # Along with this check that app runs ok + dut.expect('Hello world!') + + # Don't need to have output from UART any more + dut.serial.stop_redirect_thread() + + with open(os.path.join(dut.logdir, 'ocd.log'), 'w') as ocd_log: + ocd = subprocess.Popen(f'openocd {get_openocd_arguments(dut.target)}', stdout=ocd_log, stderr=ocd_log, shell=True) + + try: + gdb_env = os.environ.copy() + gdb_env['ESP_IDF_GDB_TESTING'] = '1' + + with open(os.path.join(dut.logdir, 'gdb.log'), 'w') as gdb_log, \ + pexpect.spawn(f'idf.py -B {dut.app.binary_path} gdb --batch', + env=gdb_env, + timeout=60, + logfile=gdb_log, + encoding='utf-8', + codec_errors='ignore') as p: + p.expect(re.compile(r'add symbol table from file.*bootloader.elf')) + p.expect(re.compile(r'add symbol table from file.*rom.elf')) + p.expect_exact('hit Temporary breakpoint 1, app_main ()') + finally: + try: + ocd.send_signal(signal.SIGINT) + ocd.communicate(timeout=15) + except subprocess.TimeoutExpired: + ocd.kill() + ocd.communicate() diff --git a/tools/test_apps/system/monitor_ide_integration/app_test.py b/tools/test_apps/system/monitor_ide_integration/app_test.py deleted file mode 100644 index 4aceecd041..0000000000 --- a/tools/test_apps/system/monitor_ide_integration/app_test.py +++ /dev/null @@ -1,93 +0,0 @@ -from __future__ import unicode_literals - -import glob -import json -import os -import re -import threading - -import ttfw_idf -from SimpleWebSocketServer import SimpleWebSocketServer, WebSocket -from tiny_test_fw import Utility - - -class IDEWSProtocol(WebSocket): - - def handleMessage(self): - try: - j = json.loads(self.data) - except Exception as e: - Utility.console_log('Server ignores error: {}'.format(e), 'orange') - return - event = j.get('event') - if event and 'prog' in j and ((event == 'gdb_stub' and 'port' in j) or - (event == 'coredump' and 'file' in j)): - payload = {'event': 'debug_finished'} - self.sendMessage(json.dumps(payload)) - Utility.console_log('Server sent: {}'.format(payload)) - else: - Utility.console_log('Server received: {}'.format(j), 'orange') - - def handleConnected(self): - Utility.console_log('{} connected to server'.format(self.address)) - - def handleClose(self): - Utility.console_log('{} closed the connection'.format(self.address)) - - -class WebSocketServer(object): - HOST = '127.0.0.1' - PORT = 1123 - - def run(self): - server = SimpleWebSocketServer(self.HOST, self.PORT, IDEWSProtocol) - while not self.exit_event.is_set(): - server.serveonce() - - def __init__(self): - self.exit_event = threading.Event() - self.thread = threading.Thread(target=self.run) - self.thread.start() - - def __enter__(self): - return self - - def __exit__(self, exc_type, exc_value, traceback): - self.exit_event.set() - self.thread.join(10) - if self.thread.is_alive(): - Utility.console_log('Thread cannot be joined', 'orange') - - -@ttfw_idf.idf_custom_test(env_tag='test_jtag_arm', group='test-apps') -def test_monitor_ide_integration(env, extra_data): - config_files = glob.glob(os.path.join(os.path.dirname(__file__), 'sdkconfig.ci.*')) - config_names = [os.path.basename(s).replace('sdkconfig.ci.', '') for s in config_files] - rel_proj_path = 'tools/test_apps/system/monitor_ide_integration' - for name in config_names: - Utility.console_log('Checking config "{}"... '.format(name), 'green', end='') - dut = env.get_dut('panic', rel_proj_path, app_config_name=name) - monitor_path = os.path.join(dut.app.idf_path, 'tools/idf_monitor.py') - elf_path = os.path.join(dut.app.binary_path, 'panic.elf') - dut.start_app() - # Closing the DUT because we will reconnect with IDF Monitor - env.close_dut(dut.name) - - with WebSocketServer(), ttfw_idf.CustomProcess(' '.join([monitor_path, - elf_path, - '--port', str(dut.port), - '--ws', 'ws://{}:{}'.format(WebSocketServer.HOST, - WebSocketServer.PORT)]), - logfile='monitor_{}.log'.format(name)) as p: - p.pexpect_proc.expect(re.compile(r'Guru Meditation Error'), timeout=10) - p.pexpect_proc.expect_exact('Communicating through WebSocket', timeout=5) - # "u?" is for Python 2 only in the following regular expressions. - # The elements of dictionary can be printed in different order depending on the Python version. - p.pexpect_proc.expect(re.compile(r"WebSocket sent: \{u?.*'event': u?'" + name + "'"), timeout=5) - p.pexpect_proc.expect_exact('Waiting for debug finished event', timeout=5) - p.pexpect_proc.expect(re.compile(r"WebSocket received: \{u?'event': u?'debug_finished'\}"), timeout=5) - p.pexpect_proc.expect_exact('Communications through WebSocket is finished', timeout=5) - - -if __name__ == '__main__': - test_monitor_ide_integration() diff --git a/tools/test_apps/system/monitor_ide_integration/main/main.c b/tools/test_apps/system/monitor_ide_integration/main/main.c index 13c5f7dfba..5229715e7b 100644 --- a/tools/test_apps/system/monitor_ide_integration/main/main.c +++ b/tools/test_apps/system/monitor_ide_integration/main/main.c @@ -13,6 +13,6 @@ void app_main(void) { int *p = (int *)4; - vTaskDelay(1000 / portTICK_PERIOD_MS); + vTaskDelay(2000 / portTICK_PERIOD_MS); *p = 0; } diff --git a/tools/test_apps/system/monitor_ide_integration/pytest_monitor_ide_integration.py b/tools/test_apps/system/monitor_ide_integration/pytest_monitor_ide_integration.py new file mode 100644 index 0000000000..7c893e5207 --- /dev/null +++ b/tools/test_apps/system/monitor_ide_integration/pytest_monitor_ide_integration.py @@ -0,0 +1,93 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Unlicense OR CC0-1.0 +import json +import logging +import multiprocessing +import os +import re +import sys +from types import TracebackType +from typing import Optional, Type, TypeVar + +import pexpect +import pytest +from pytest_embedded import Dut +from SimpleWebSocketServer import SimpleWebSocketServer, WebSocket + +WebSocketServerType = TypeVar('WebSocketServerType') + + +class IDEWSProtocol(WebSocket): + + def handleMessage(self) -> None: + try: + j = json.loads(self.data) + except Exception as e: + logging.info(f'Server ignores error: {e}') + return + event = j.get('event') + if event and 'prog' in j and ((event == 'gdb_stub' and 'port' in j) or + (event == 'coredump' and 'file' in j)): + payload = {'event': 'debug_finished'} + self.sendMessage(json.dumps(payload)) + logging.info(f'Server sent: {payload}') + else: + logging.info(f'Server received: {j}') + + def handleConnected(self) -> None: + logging.info(f'{self.address} connected to server') + + def handleClose(self) -> None: + logging.info(f'{self.address} closed the connection') + + +class WebSocketServer(object): + HOST = '127.0.0.1' + PORT = 1123 + + def run(self) -> None: + server = SimpleWebSocketServer(self.HOST, self.PORT, IDEWSProtocol) + while not self.exit_event.is_set(): + server.serveonce() + + def __init__(self) -> None: + self.exit_event = multiprocessing.Event() + self.proc = multiprocessing.Process(target=self.run) + self.proc.start() + + def __enter__(self: WebSocketServerType) -> WebSocketServerType: + return self + + def __exit__(self, exc_type: Optional[Type[BaseException]], exc_value: Optional[BaseException], traceback: + Optional[TracebackType]) -> None: + self.exit_event.set() + self.proc.join(10) + if self.proc.is_alive(): + logging.info('Process cannot be joined') + + +@pytest.mark.esp32 +@pytest.mark.generic +@pytest.mark.parametrize('config', ['gdb_stub', 'coredump'], indirect=True) +def test_monitor_ide_integration(config: str, dut: Dut) -> None: + # The port needs to be closed because idf_monitor.py will connect to it + dut.serial.stop_redirect_thread() + + monitor_py = os.path.join(os.environ['IDF_PATH'], 'tools', 'idf_monitor.py') + monitor_cmd = ' '.join([sys.executable, monitor_py, os.path.join(dut.app.binary_path, 'panic.elf'), + '--port', str(dut.serial.port), + '--ws', f'ws://{WebSocketServer.HOST}:{WebSocketServer.PORT}']) + monitor_log_path = os.path.join(dut.logdir, 'monitor.log') + + with open(monitor_log_path, 'w') as log, WebSocketServer(), pexpect.spawn(monitor_cmd, + logfile=log, + timeout=5, + encoding='utf-8', + codec_errors='ignore') as p: + p.expect(re.compile(r'Guru Meditation Error'), timeout=10) + p.expect_exact('Communicating through WebSocket') + # The elements of dictionary can be printed in different order depending on the Python version. + p.expect(re.compile(r"WebSocket sent: \{.*'event': '" + config + "'")) + p.expect_exact('Waiting for debug finished event') + p.expect(re.compile(r"WebSocket received: \{'event': 'debug_finished'\}")) + p.expect_exact('Communications through WebSocket is finished') diff --git a/tools/test_apps/system/panic/conftest.py b/tools/test_apps/system/panic/conftest.py index e688deb9c7..dc43e48c82 100644 --- a/tools/test_apps/system/panic/conftest.py +++ b/tools/test_apps/system/panic/conftest.py @@ -3,279 +3,10 @@ # pylint: disable=W0621 # redefined-outer-name -import logging -import os -import subprocess -import sys -from typing import Any, Dict, List, TextIO - -import pexpect import pytest from _pytest.fixtures import FixtureRequest from _pytest.monkeypatch import MonkeyPatch -from panic_utils import NoGdbProcessError, attach_logger, quote_string, sha256, verify_valid_gdb_subprocess -from pygdbmi.gdbcontroller import GdbController -from pytest_embedded_idf.app import IdfApp -from pytest_embedded_idf.dut import IdfDut -from pytest_embedded_idf.serial import IdfSerial - - -class PanicTestDut(IdfDut): - BOOT_CMD_ADDR = 0x9000 - BOOT_CMD_SIZE = 0x1000 - DEFAULT_EXPECT_TIMEOUT = 10 - COREDUMP_UART_START = '================= CORE DUMP START =================' - COREDUMP_UART_END = '================= CORE DUMP END =================' - - app: IdfApp - serial: IdfSerial - - def __init__(self, *args, **kwargs) -> None: # type: ignore - super().__init__(*args, **kwargs) - - self.gdb: GdbController = None # type: ignore - # record this since pygdbmi is using logging.debug to generate some single character mess - self.log_level = logging.getLogger().level - # pygdbmi is using logging.debug to generate some single character mess - if self.log_level <= logging.DEBUG: - logging.getLogger().setLevel(logging.INFO) - - self.coredump_output: TextIO = None # type: ignore - - def close(self) -> None: - if self.gdb: - self.gdb.exit() - - super().close() - - def revert_log_level(self) -> None: - logging.getLogger().setLevel(self.log_level) - - def expect_test_func_name(self, test_func_name: str) -> None: - self.expect_exact('Enter test name:') - self.write(test_func_name) - self.expect_exact('Got test name: ' + test_func_name) - - def expect_none(self, pattern, **kwargs) -> None: # type: ignore - """like dut.expect_all, but with an inverse logic""" - if 'timeout' not in kwargs: - kwargs['timeout'] = 1 - - try: - res = self.expect(pattern, **kwargs) - raise AssertionError(f'Unexpected: {res.group().decode("utf8")}') - except pexpect.TIMEOUT: - pass - - def expect_backtrace(self) -> None: - self.expect_exact('Backtrace:') - self.expect_none('CORRUPTED') - - def expect_gme(self, reason: str) -> None: - """Expect method for Guru Meditation Errors""" - self.expect_exact(f"Guru Meditation Error: Core 0 panic'ed ({reason})") - - def expect_reg_dump(self, core: int = 0) -> None: - """Expect method for the register dump""" - self.expect(r'Core\s+%d register dump:' % core) - - def expect_elf_sha256(self) -> None: - """Expect method for ELF SHA256 line""" - elf_sha256 = sha256(self.app.elf_file) - elf_sha256_len = int( - self.app.sdkconfig.get('CONFIG_APP_RETRIEVE_LEN_ELF_SHA', '16') - ) - self.expect_exact('ELF file SHA256: ' + elf_sha256[0:elf_sha256_len]) - - def _call_espcoredump( - self, extra_args: List[str], coredump_file_name: str, output_file_name: str - ) -> None: - # no "with" here, since we need the file to be open for later inspection by the test case - if not self.coredump_output: - self.coredump_output = open(output_file_name, 'w') - - espcoredump_script = os.path.join( - os.environ['IDF_PATH'], 'components', 'espcoredump', 'espcoredump.py' - ) - espcoredump_args = [ - sys.executable, - espcoredump_script, - 'info_corefile', - '--core', - coredump_file_name, - ] - espcoredump_args += extra_args - espcoredump_args.append(self.app.elf_file) - logging.info('Running %s', ' '.join(espcoredump_args)) - logging.info('espcoredump output is written to %s', self.coredump_output.name) - - subprocess.check_call(espcoredump_args, stdout=self.coredump_output) - self.coredump_output.flush() - self.coredump_output.seek(0) - - def process_coredump_uart(self) -> None: - """Extract the core dump from UART output of the test, run espcoredump on it""" - self.expect(self.COREDUMP_UART_START) - res = self.expect('(.+)' + self.COREDUMP_UART_END) - coredump_base64 = res.group(1).decode('utf8') - with open(os.path.join(self.logdir, 'coredump_data.b64'), 'w') as coredump_file: - logging.info('Writing UART base64 core dump to %s', coredump_file.name) - coredump_file.write(coredump_base64) - - output_file_name = os.path.join(self.logdir, 'coredump_uart_result.txt') - self._call_espcoredump( - ['--core-format', 'b64'], coredump_file.name, output_file_name - ) - - def process_coredump_flash(self) -> None: - """Extract the core dump from flash, run espcoredump on it""" - coredump_file_name = os.path.join(self.logdir, 'coredump_data.bin') - logging.info('Writing flash binary core dump to %s', coredump_file_name) - self.serial.dump_flash(partition='coredump', output=coredump_file_name) - - output_file_name = os.path.join(self.logdir, 'coredump_flash_result.txt') - self._call_espcoredump( - ['--core-format', 'raw'], coredump_file_name, output_file_name - ) - - def gdb_write(self, command: str) -> Any: - """ - Wrapper to write to gdb with a longer timeout, as test runner - host can be slow sometimes - """ - return self.gdb.write(command, timeout_sec=10) - - def start_gdb(self) -> None: - """ - Runs GDB and connects it to the "serial" port of the DUT. - After this, the DUT expect methods can no longer be used to capture output. - """ - gdb_path = self.toolchain_prefix + 'gdb' - try: - from pygdbmi.constants import GdbTimeoutError - default_gdb_args = ['--nx', '--quiet', '--interpreter=mi2'] - gdb_command = [gdb_path] + default_gdb_args - self.gdb = GdbController(command=gdb_command) - pygdbmi_logger = attach_logger() - except ImportError: - # fallback for pygdbmi<0.10.0.0. - from pygdbmi.gdbcontroller import GdbTimeoutError - self.gdb = GdbController(gdb_path=gdb_path) - pygdbmi_logger = self.gdb.logger - - # pygdbmi logs to console by default, make it log to a file instead - pygdbmi_log_file_name = os.path.join(self.logdir, 'pygdbmi_log.txt') - pygdbmi_logger.setLevel(logging.DEBUG) - while pygdbmi_logger.hasHandlers(): - pygdbmi_logger.removeHandler(pygdbmi_logger.handlers[0]) - log_handler = logging.FileHandler(pygdbmi_log_file_name) - log_handler.setFormatter( - logging.Formatter('%(asctime)s %(levelname)s: %(message)s') - ) - pygdbmi_logger.addHandler(log_handler) - try: - gdb_command = self.gdb.command - except AttributeError: - # fallback for pygdbmi < 0.10 - gdb_command = self.gdb.cmd - - logging.info(f'Running command: "{" ".join(quote_string(c) for c in gdb_command)}"') - for _ in range(10): - try: - # GdbController creates a process with subprocess.Popen(). Is it really running? It is probable that - # an RPI under high load will get non-responsive during creating a lot of processes. - if not hasattr(self.gdb, 'verify_valid_gdb_subprocess'): - # for pygdbmi >= 0.10.0.0 - verify_valid_gdb_subprocess(self.gdb.gdb_process) - resp = self.gdb.get_gdb_response( - timeout_sec=10 - ) # calls verify_valid_gdb_subprocess() internally for pygdbmi < 0.10.0.0 - # it will be interesting to look up this response if the next GDB command fails (times out) - logging.info('GDB response: %s', resp) - break # success - except GdbTimeoutError: - logging.warning( - 'GDB internal error: cannot get response from the subprocess' - ) - except NoGdbProcessError: - logging.error('GDB internal error: process is not running') - break # failure - TODO: create another GdbController - except ValueError: - logging.error( - 'GDB internal error: select() returned an unexpected file number' - ) - - # Set up logging for GDB remote protocol - gdb_remotelog_file_name = os.path.join(self.logdir, 'gdb_remote_log.txt') - self.gdb_write('-gdb-set remotelogfile ' + gdb_remotelog_file_name) - - # Load the ELF file - self.gdb_write('-file-exec-and-symbols {}'.format(self.app.elf_file)) - - # Connect GDB to UART - self.serial.proc.close() - logging.info('Connecting to GDB Stub...') - self.gdb_write('-gdb-set serial baud 115200') - responses = self.gdb_write('-target-select remote ' + self.serial.port) - - # Make sure we get the 'stopped' notification - stop_response = self.find_gdb_response('stopped', 'notify', responses) - if not stop_response: - responses = self.gdb_write('-exec-interrupt') - stop_response = self.find_gdb_response('stopped', 'notify', responses) - assert stop_response - frame = stop_response['payload']['frame'] - if 'file' not in frame: - frame['file'] = '?' - if 'line' not in frame: - frame['line'] = '?' - logging.info('Stopped in {func} at {addr} ({file}:{line})'.format(**frame)) - - # Drain remaining responses - self.gdb.get_gdb_response(raise_error_on_timeout=False) - - def gdb_backtrace(self) -> Any: - """ - Returns the list of stack frames for the current thread. - Each frame is a dictionary, refer to pygdbmi docs for the format. - """ - assert self.gdb - - responses = self.gdb_write('-stack-list-frames') - return self.find_gdb_response('done', 'result', responses)['payload']['stack'] - - @staticmethod - def match_backtrace( - gdb_backtrace: List[Any], expected_functions_list: List[Any] - ) -> bool: - """ - Returns True if the function names listed in expected_functions_list match the backtrace - given by gdb_backtrace argument. The latter is in the same format as returned by gdb_backtrace() - function. - """ - return all( - [ - frame['func'] == expected_functions_list[i] - for i, frame in enumerate(gdb_backtrace) - ] - ) - - @staticmethod - def find_gdb_response( - message: str, response_type: str, responses: List[Any] - ) -> Any: - """ - Helper function which extracts one response from an array of GDB responses, filtering - by message and type. Returned message is a dictionary, refer to pygdbmi docs for the format. - """ - - def match_response(response: Dict[str, Any]) -> bool: - return response['message'] == message and response['type'] == response_type # type: ignore - - filtered_responses = [r for r in responses if match_response(r)] - if not filtered_responses: - return None - return filtered_responses[0] +from test_panic_util import PanicTestDut @pytest.fixture(scope='module') diff --git a/tools/test_apps/system/panic/pytest_panic.py b/tools/test_apps/system/panic/pytest_panic.py index fe11577e6a..f60f384eaf 100644 --- a/tools/test_apps/system/panic/pytest_panic.py +++ b/tools/test_apps/system/panic/pytest_panic.py @@ -6,8 +6,7 @@ from pprint import pformat from typing import List, Optional import pytest - -from conftest import PanicTestDut +from test_panic_util import PanicTestDut CONFIGS = [ pytest.param('coredump_flash_bin_crc', marks=[pytest.mark.esp32, pytest.mark.esp32s2]), @@ -272,10 +271,10 @@ def test_abort(dut: PanicTestDut, config: str, test_func_name: str) -> None: dut, config, expected_backtrace=[ - # Backtrace interrupted when abort is called, IDF-842 'panic_abort', 'esp_system_abort', - ], + 'abort' + ] + get_default_backtrace(test_func_name), ) else: common_test(dut, config) @@ -295,10 +294,11 @@ def test_ub(dut: PanicTestDut, config: str, test_func_name: str) -> None: dut, config, expected_backtrace=[ - # Backtrace interrupted when abort is called, IDF-842 'panic_abort', 'esp_system_abort', - ], + '__ubsan_default_handler', + '__ubsan_handle_out_of_bounds' + ] + get_default_backtrace(test_func_name), ) else: common_test(dut, config) diff --git a/tools/test_apps/system/panic/test_panic_util/__init__.py b/tools/test_apps/system/panic/test_panic_util/__init__.py new file mode 100644 index 0000000000..8079526734 --- /dev/null +++ b/tools/test_apps/system/panic/test_panic_util/__init__.py @@ -0,0 +1,5 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Unlicense OR CC0-1.0 +from .panic_dut import PanicTestDut + +__all__ = ['PanicTestDut'] diff --git a/tools/test_apps/system/panic/test_panic_util/panic_dut.py b/tools/test_apps/system/panic/test_panic_util/panic_dut.py new file mode 100644 index 0000000000..e956e0ec5f --- /dev/null +++ b/tools/test_apps/system/panic/test_panic_util/panic_dut.py @@ -0,0 +1,272 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Unlicense OR CC0-1.0 +import logging +import os +import subprocess +import sys +from typing import Any, Dict, List, TextIO + +import pexpect +from panic_utils import NoGdbProcessError, attach_logger, quote_string, sha256, verify_valid_gdb_subprocess +from pygdbmi.gdbcontroller import GdbController +from pytest_embedded_idf.app import IdfApp +from pytest_embedded_idf.dut import IdfDut +from pytest_embedded_idf.serial import IdfSerial + + +class PanicTestDut(IdfDut): + BOOT_CMD_ADDR = 0x9000 + BOOT_CMD_SIZE = 0x1000 + DEFAULT_EXPECT_TIMEOUT = 10 + COREDUMP_UART_START = '================= CORE DUMP START =================' + COREDUMP_UART_END = '================= CORE DUMP END =================' + + app: IdfApp + serial: IdfSerial + + def __init__(self, *args, **kwargs) -> None: # type: ignore + super().__init__(*args, **kwargs) + + self.gdb: GdbController = None # type: ignore + # record this since pygdbmi is using logging.debug to generate some single character mess + self.log_level = logging.getLogger().level + # pygdbmi is using logging.debug to generate some single character mess + if self.log_level <= logging.DEBUG: + logging.getLogger().setLevel(logging.INFO) + + self.coredump_output: TextIO = None # type: ignore + + def close(self) -> None: + if self.gdb: + self.gdb.exit() + + super().close() + + def revert_log_level(self) -> None: + logging.getLogger().setLevel(self.log_level) + + def expect_test_func_name(self, test_func_name: str) -> None: + self.expect_exact('Enter test name:') + self.write(test_func_name) + self.expect_exact('Got test name: ' + test_func_name) + + def expect_none(self, pattern, **kwargs) -> None: # type: ignore + """like dut.expect_all, but with an inverse logic""" + if 'timeout' not in kwargs: + kwargs['timeout'] = 1 + + try: + res = self.expect(pattern, **kwargs) + raise AssertionError(f'Unexpected: {res.group().decode("utf8")}') + except pexpect.TIMEOUT: + pass + + def expect_backtrace(self) -> None: + self.expect_exact('Backtrace:') + self.expect_none('CORRUPTED') + + def expect_gme(self, reason: str) -> None: + """Expect method for Guru Meditation Errors""" + self.expect_exact(f"Guru Meditation Error: Core 0 panic'ed ({reason})") + + def expect_reg_dump(self, core: int = 0) -> None: + """Expect method for the register dump""" + self.expect(r'Core\s+%d register dump:' % core) + + def expect_elf_sha256(self) -> None: + """Expect method for ELF SHA256 line""" + elf_sha256 = sha256(self.app.elf_file) + elf_sha256_len = int( + self.app.sdkconfig.get('CONFIG_APP_RETRIEVE_LEN_ELF_SHA', '16') + ) + self.expect_exact('ELF file SHA256: ' + elf_sha256[0:elf_sha256_len]) + + def _call_espcoredump( + self, extra_args: List[str], coredump_file_name: str, output_file_name: str + ) -> None: + # no "with" here, since we need the file to be open for later inspection by the test case + if not self.coredump_output: + self.coredump_output = open(output_file_name, 'w') + + espcoredump_script = os.path.join( + os.environ['IDF_PATH'], 'components', 'espcoredump', 'espcoredump.py' + ) + espcoredump_args = [ + sys.executable, + espcoredump_script, + 'info_corefile', + '--core', + coredump_file_name, + ] + espcoredump_args += extra_args + espcoredump_args.append(self.app.elf_file) + logging.info('Running %s', ' '.join(espcoredump_args)) + logging.info('espcoredump output is written to %s', self.coredump_output.name) + + subprocess.check_call(espcoredump_args, stdout=self.coredump_output) + self.coredump_output.flush() + self.coredump_output.seek(0) + + def process_coredump_uart(self) -> None: + """Extract the core dump from UART output of the test, run espcoredump on it""" + self.expect(self.COREDUMP_UART_START) + res = self.expect('(.+)' + self.COREDUMP_UART_END) + coredump_base64 = res.group(1).decode('utf8') + with open(os.path.join(self.logdir, 'coredump_data.b64'), 'w') as coredump_file: + logging.info('Writing UART base64 core dump to %s', coredump_file.name) + coredump_file.write(coredump_base64) + + output_file_name = os.path.join(self.logdir, 'coredump_uart_result.txt') + self._call_espcoredump( + ['--core-format', 'b64'], coredump_file.name, output_file_name + ) + + def process_coredump_flash(self) -> None: + """Extract the core dump from flash, run espcoredump on it""" + coredump_file_name = os.path.join(self.logdir, 'coredump_data.bin') + logging.info('Writing flash binary core dump to %s', coredump_file_name) + self.serial.dump_flash(partition='coredump', output=coredump_file_name) + + output_file_name = os.path.join(self.logdir, 'coredump_flash_result.txt') + self._call_espcoredump( + ['--core-format', 'raw'], coredump_file_name, output_file_name + ) + + def gdb_write(self, command: str) -> Any: + """ + Wrapper to write to gdb with a longer timeout, as test runner + host can be slow sometimes + """ + return self.gdb.write(command, timeout_sec=10) + + def start_gdb(self) -> None: + """ + Runs GDB and connects it to the "serial" port of the DUT. + After this, the DUT expect methods can no longer be used to capture output. + """ + gdb_path = self.toolchain_prefix + 'gdb' + try: + from pygdbmi.constants import GdbTimeoutError + default_gdb_args = ['--nx', '--quiet', '--interpreter=mi2'] + gdb_command = [gdb_path] + default_gdb_args + self.gdb = GdbController(command=gdb_command) + pygdbmi_logger = attach_logger() + except ImportError: + # fallback for pygdbmi<0.10.0.0. + from pygdbmi.gdbcontroller import GdbTimeoutError + self.gdb = GdbController(gdb_path=gdb_path) + pygdbmi_logger = self.gdb.logger + + # pygdbmi logs to console by default, make it log to a file instead + pygdbmi_log_file_name = os.path.join(self.logdir, 'pygdbmi_log.txt') + pygdbmi_logger.setLevel(logging.DEBUG) + while pygdbmi_logger.hasHandlers(): + pygdbmi_logger.removeHandler(pygdbmi_logger.handlers[0]) + log_handler = logging.FileHandler(pygdbmi_log_file_name) + log_handler.setFormatter( + logging.Formatter('%(asctime)s %(levelname)s: %(message)s') + ) + pygdbmi_logger.addHandler(log_handler) + try: + gdb_command = self.gdb.command + except AttributeError: + # fallback for pygdbmi < 0.10 + gdb_command = self.gdb.cmd + + logging.info(f'Running command: "{" ".join(quote_string(c) for c in gdb_command)}"') + for _ in range(10): + try: + # GdbController creates a process with subprocess.Popen(). Is it really running? It is probable that + # an RPI under high load will get non-responsive during creating a lot of processes. + if not hasattr(self.gdb, 'verify_valid_gdb_subprocess'): + # for pygdbmi >= 0.10.0.0 + verify_valid_gdb_subprocess(self.gdb.gdb_process) + resp = self.gdb.get_gdb_response( + timeout_sec=10 + ) # calls verify_valid_gdb_subprocess() internally for pygdbmi < 0.10.0.0 + # it will be interesting to look up this response if the next GDB command fails (times out) + logging.info('GDB response: %s', resp) + break # success + except GdbTimeoutError: + logging.warning( + 'GDB internal error: cannot get response from the subprocess' + ) + except NoGdbProcessError: + logging.error('GDB internal error: process is not running') + break # failure - TODO: create another GdbController + except ValueError: + logging.error( + 'GDB internal error: select() returned an unexpected file number' + ) + + # Set up logging for GDB remote protocol + gdb_remotelog_file_name = os.path.join(self.logdir, 'gdb_remote_log.txt') + self.gdb_write('-gdb-set remotelogfile ' + gdb_remotelog_file_name) + + # Load the ELF file + self.gdb_write('-file-exec-and-symbols {}'.format(self.app.elf_file)) + + # Connect GDB to UART + self.serial.proc.close() + logging.info('Connecting to GDB Stub...') + self.gdb_write('-gdb-set serial baud 115200') + responses = self.gdb_write('-target-select remote ' + self.serial.port) + + # Make sure we get the 'stopped' notification + stop_response = self.find_gdb_response('stopped', 'notify', responses) + if not stop_response: + responses = self.gdb_write('-exec-interrupt') + stop_response = self.find_gdb_response('stopped', 'notify', responses) + assert stop_response + frame = stop_response['payload']['frame'] + if 'file' not in frame: + frame['file'] = '?' + if 'line' not in frame: + frame['line'] = '?' + logging.info('Stopped in {func} at {addr} ({file}:{line})'.format(**frame)) + + # Drain remaining responses + self.gdb.get_gdb_response(raise_error_on_timeout=False) + + def gdb_backtrace(self) -> Any: + """ + Returns the list of stack frames for the current thread. + Each frame is a dictionary, refer to pygdbmi docs for the format. + """ + assert self.gdb + + responses = self.gdb_write('-stack-list-frames') + return self.find_gdb_response('done', 'result', responses)['payload']['stack'] + + @staticmethod + def match_backtrace( + gdb_backtrace: List[Any], expected_functions_list: List[Any] + ) -> bool: + """ + Returns True if the function names listed in expected_functions_list match the backtrace + given by gdb_backtrace argument. The latter is in the same format as returned by gdb_backtrace() + function. + """ + return all( + [ + frame['func'] == expected_functions_list[i] + for i, frame in enumerate(gdb_backtrace) + ] + ) + + @staticmethod + def find_gdb_response( + message: str, response_type: str, responses: List[Any] + ) -> Any: + """ + Helper function which extracts one response from an array of GDB responses, filtering + by message and type. Returned message is a dictionary, refer to pygdbmi docs for the format. + """ + + def match_response(response: Dict[str, Any]) -> bool: + return response['message'] == message and response['type'] == response_type # type: ignore + + filtered_responses = [r for r in responses if match_response(r)] + if not filtered_responses: + return None + return filtered_responses[0] diff --git a/tools/test_build_system/MIGRATION.md b/tools/test_build_system/MIGRATION.md new file mode 100644 index 0000000000..57827ad396 --- /dev/null +++ b/tools/test_build_system/MIGRATION.md @@ -0,0 +1,107 @@ +# Migration from test_build_system_cmake.sh to pytest + +This table tracks migration of tests from [test_build_system_cmake.sh](../ci/test_build_system_cmake.sh) and [test_build_system_spaces.py](../ci/test_build_system_spaces.py) to pytest. + +When all tests are migrated to pytest, remove the original tests, corresponding CI jobs, and this file. + +Legacy test name | New test name | Comments +-----------------|---------------|--------- +Initial clean build | test_rebuild::test_rebuild_no_changes | +Updating component source file rebuilds component | test_rebuild::test_rebuild_source_files | +Bootloader source file rebuilds bootloader | test_rebuild::test_rebuild_source_files | +Partition CSV file rebuilds partitions | test_rebuild::test_rebuild_source_files | +Partial build doesn't compile anything by default | test_rebuild::test_rebuild_no_changes | +Rebuild when app version was changed | | +Change app version | | +Re-building does not change app.bin | | +Get the version of app from git describe. Project is not inside IDF and do not have a tag only a hash commit. | | +Get the version of app from Kconfig option | | +Use IDF version variables in component CMakeLists.txt file | | +Project is in ESP-IDF which has a custom tag | | +Moving BUILD_DIR_BASE out of tree | | +BUILD_DIR_BASE inside default build directory | | +Can still clean build if all text files are CRLFs | | +Updating rom ld file should re-link app and bootloader | test_rebuild::test_rebuild_linker | +Updating app-only ld file should only re-link app | test_rebuild::test_rebuild_linker | +Updating ld file should only re-link app | test_rebuild::test_rebuild_linker | +Updating fragment file should only re-link app | test_rebuild::test_rebuild_linker | +sdkconfig update triggers full recompile | test_rebuild::test_rebuild_source_files | +Updating project CMakeLists.txt triggers full recompile | test_rebuild::test_rebuild_source_files | +Can build with Ninja (no idf.py) | | +Can build with GNU Make (no idf.py) | | +idf.py can build with Ninja | | +idf.py can build with Unix Makefiles | | +Can build with IDF_PATH set via cmake cache not environment | | +Can build with IDF_PATH unset and inferred by build system | | +Can build with IDF_PATH unset and inferred by cmake when Kconfig needs it to be set | | +can build with phy_init_data | | +can build with ethernet component disabled | | +Compiler flags on build command line are taken into account | | +Compiler flags cannot be overwritten | | +Can override IDF_TARGET from environment | | +Can set target using idf.py -D | | +Can set target using -D as subcommand parameter for idf.py | | +Can set target using idf.py set-target | | +idf.py understands alternative target names | | +Can guess target from sdkconfig, if CMakeCache does not exist | | +Can set the default target using sdkconfig.defaults | | +IDF_TARGET takes precedence over the value of CONFIG_IDF_TARGET in sdkconfig.defaults | | +idf.py fails if IDF_TARGET settings don't match in sdkconfig, CMakeCache.txt, and the environment | | +Setting EXTRA_COMPONENT_DIRS works | | +Non-existent paths in EXTRA_COMPONENT_DIRS are not allowed | | +Component names may contain spaces | | +sdkconfig should have contents of all files: sdkconfig, sdkconfig.defaults, sdkconfig.defaults.IDF_TARGET | | +Test if it can build the example to run on host | | +Test build ESP-IDF as a library to a custom CMake projects for all targets | | +Building a project with CMake library imported and PSRAM workaround, all files compile with workaround | | +Test for external libraries in custom CMake projects with ESP-IDF components linked | | +Test for external libraries in custom CMake projects with PSRAM strategy $strat | | +Cleaning Python bytecode | | +Displays partition table when executing target partition_table | | +Make sure a full build never runs '/usr/bin/env python' or similar | | +Handling deprecated Kconfig options | | +Handling deprecated Kconfig options in sdkconfig.defaults | | +Confserver can be invoked by idf.py | | +Check ccache is used to build | | +Custom bootloader overrides original | | +Empty directory not treated as a component | | +If a component directory is added to COMPONENT_DIRS, its subdirectories are not added | | +If a component directory is added to COMPONENT_DIRS, its sibling directories are not added | | +toolchain prefix is set in project description file | | +Can set options to subcommands: print_filter for monitor | | +Fail on build time works | | +Component properties are set | | +should be able to specify multiple sdkconfig default files | | +Supports git worktree | | +idf.py fallback to build system target | | +Build fails if partitions don't fit in flash | | +Warning is given if smallest partition is nearly full | | +Flash size is correctly set in the bootloader image header | | +DFU build works | | +UF2 build works | | +Loadable ELF build works | | +Defaults set properly for unspecified idf_build_process args | | +Getting component overriden dir | | +Overriding Kconfig | | +Project components prioritized over EXTRA_COMPONENT_DIRS | | +Components in EXCLUDE_COMPONENTS not passed to idf_component_manager | | +Create project using idf.py and build it | | +Create component using idf.py, create project using idf.py. | | +Add the component to the created project and build the project. | | +Check that command for creating new project will fail if the target folder is not empty. | | +Check that command for creating new project will fail if the target path is file. | | +Check docs command | | +Deprecation warning check | | +Save-defconfig checks | | +test_build | | +test_build_ulp_fsm | | +test_build_ulp_riscv | | +test_spiffsgen | | +test_flash_encryption | | +test_secure_boot_v1 | | +test_secure_boot_v2 | | +test_app_signing | | +test_secure_boot_release_mode | | +test_x509_cert_bundle | | +test_dfu | | +test_uf2 | | diff --git a/tools/test_build_system/README.md b/tools/test_build_system/README.md new file mode 100644 index 0000000000..0563d75ffa --- /dev/null +++ b/tools/test_build_system/README.md @@ -0,0 +1,166 @@ +# Tools & Build System Tests + +This directory contains tests for the build system and build-related tools. These tests are meant to be used both by developers and in CI. Please check the sections below for details on: + +- Running the tests locally +- Debugging test failures +- Adding new tests +- Fixtures and helper functions + +## Running the tests locally + +1. Install pytest using `install.{sh,bat,ps1,fish} --enable-pytest`. +1. Activate the IDF shell environment using `export.{sh,bat,ps1,fish}`. +1. To run all the tests, go to `$IDF_PATH/tools/test_build_system` directory, then run: + ``` + pytest + ``` +1. To run one specific test, use `-k` flag of pytest, for example + ``` + pytest -k test_compile_commands_json_updated_by_reconfigure + ``` +1. To speed up the builds you can install Ccache and set the following environment variables: + ``` + export IDF_CCACHE_ENABLE=1 + export CCACHE_NOHASHDIR=1 + ``` + +## Debugging test failures + +If you are working on a bug fix or a feature and one of the tests starts to fail, you should try to reproduce the failure locally. + +1. Find the name of the failing test in the CI job log +1. Follow the steps in the section above to run that one test +1. By default, the fixtures which create temporary directories will remove them after the test. To prevent the directories from being removed, run `pytest` with `--work-dir /some/path` flag. The temporary directories will be created under `/some/path`, and you will be able to inspect them once the test fails. +1. You can increase the logging level to see the commands being executed by the test by running `pytest` with `--log-cli-level DEBUG` argument. + +## Adding new tests + +1. When adding a new test, think of the developer who might have to run this test locally. + - Avoid adding tests which take a long time to run. Running the entire test suite should be possible! + - Remember that developers run these tests in their IDF work directories. Be careful with destructive actions, especially removing directories recursively. Developers might have untracked files in the directory you are removing! Prefer using the `idf_copy` fixture to make a copy of the IDF directory, when doing some modifications to IDF source. If this is too expensive, do the modification in place but make sure to clean up the changes you perform using a try/finally block. This especially applies to the newly created files. +1. Read through the test cases and try to find a test which does something similar to what you need to test. This will usually be a good starting point. Also read through the section below, which explains fixtures and utility functions. +1. The tests need to run on Windows, Linux and macOS. Avoid calling OS-specific programs such as `sed` or `awk` in tests. If you need to perform some complex file modification in the test case, consider writing a Python helper function for that. + +## Fixtures and helper functions + +If you aren't yet familiar with Pytest fixtures, please take a few moments and read a Pytest tutorial or watch the training, before moving on to the next section. + +### `test_app_copy` fixture + +This fixture selects the app (inside IDF) to be used by the test and copies this app to a temporary directory, recursively. The working directory is set to the root of the copied app. The directory is removed once the test is finished. + +```python +def test_something(test_app_copy): + assert test_app_copy == os.getcwd() + # the current working directory now contains the copy of the test app +``` + +If the test case doesn't use the `test_app_copy` argument, pylint will typically warn about an unused argument, even if the fixture is actually used. To avoid the warning, use the following pattern: +```python +@pytest.mark.usefixtures('test_app_copy') +def test_something(idf_py): + idf_py('build') +``` + +By default, the source app is `tools/test_build_system/build_test_app` and the destination directory name is derived from the test case name. (See more about this test app [here](#application-under-test).) This can be overridden using a `@pytest.mark.test_app_copy` decorator, as shown below. The first argument is the path of the source app. The second argument is the name of the temporary directory to create. The second argument is optional, it is mostly useful to test handling of special characters (such as spaces) in the path. + +```python +@pytest.mark.test_app_copy('examples/get-started/blink', 'custom dir name') +@pytest.mark.usefixtures('test_app_copy') +def test_something(): + pass +``` + +### `idf_py` fixture + +This fixture runs `idf.py` with IDF environment set up. + +```python +@pytest.mark.usefixtures('test_app_copy') +def test_something(idf_py) + # 1. 'test_app_copy' fixture has copied the test app into a temporary directory and + # set the working directory there. + # 2. 'idf_py' fixture is a function which calls idf.py: + idf_py('fullclean') + + # 3. It accepts multiple arguments and returns a subprocess.CompletedProcess + # instance. It can be used to check the process output. + output = idf_py('-DIDF_TARGET=esp32c3', 'reconfigure') + assert 'CONFIG_IDF_TARGET="esp32c3"' in Path('sdkconfig').read_text() + assert 'Building ESP-IDF components for target esp32c3' in output.stdout + + # 4. Raises subprocess.CalledProcessError on failure + with(pytest.raises(subprocess.CalledProcessError)) as exc_info: + idf_py('unknown_command') + assert 'command "unknown_command" is not known to idf.py' in exc_info.value.stderr +``` + +### `default_idf_env` fixture + +Returns a dictionary of environment variables required for the IDF build environment. It is similar to the output of `env` command after running the `export` script. + +```python +@pytest.mark.usefixtures('test_app_copy') +def test_cmake(default_idf_env): + with tempfile.TemporaryDirectory() as build_dir: + # default_idf_env can be passed to subprocess APIs to run other tools + subprocess.run(['cmake', '-B', build_dir, '.'], env=default_idf_env, check=True) +``` + +Note, `default_idf_env` sets up the environment based on the `IDF_PATH` environment variable set before launching `pytest`. + +### `idf_copy` fixture + +Copies IDF from `IDF_PATH` into a new temporary directory. `@pytest.mark.idf_copy('name prefix')` can be used to specify the name prefix of the temporary directory. + +For the duration of the test, `IDF_PATH` environment variable is set to the newly created copy. + +```python +@pytest.mark.usefixtures('test_app_copy') +def test_idf_copy(idf_copy): + # idf_copy is the temporary IDF copy. + # For example, we can check if idf.py build can work without the .git directory: + shutil.rmtree(os.path.join(idf_copy, '.git'), ignore_errors=True) + # Note that we can't use idf_py fixture, since it uses the default IDF path. + # We can use 'get_idf_build_env' with 'run_idf_py', instead: + env = get_idf_build_env(idf_copy) + run_idf_py('build', env=env) +``` + +### Build snapshots + +`get_snapshot(list_of_globs)` function takes a list of glob expressions, finds the files matching these expressions, and returns a `Snapshot` instance. `Snapshot` instances record file names and their modification timestamps. Two `Snapshot` instances can be compared using `assert_same` and `assert_different` methods: + +```python +@pytest.mark.usefixtures('test_app_copy') +def test_build_jsons_updated_by_reconfigure(idf_py): + globs = ['build/*.json'] + + idf_py('reconfigure') + snapshot_1 = get_snapshot(globs) + snapshot_2 = get_snapshot(globs) + snapshot_2.assert_same(snapshot_1) + + idf_py('reconfigure') + snapshot_3 = get_snapshot(globs) + snapshot_3.assert_different(snapshot_2) +``` + +### Helper functions for file modifications + +A few extra functions are provided to make simple file modifications: + +* `append_to_file(filename: typing.Union[str, Path], what: str) -> None` — appends the given string to a file. +* `replace_in_file(filename: typing.Union[str, Path], search: str, replace: str) -> None` — searches the file for occurrences of the string `search` and replaces all of them with `replace`, then writes the result back to the file. + +### Application under test + +Most build system tests should use the included [`build_test_app`](build_test_app/), if possible. + +Using other test apps and examples for the purpose of testing the build system is okay as long as you keep the following in mind: + +* Don't use the build system tests to compile examples or test apps under a particular combination of sdkconfig options. Use the `sdkconfig.ci.*` files for that, instead. +* Examples or test apps may be changed, renamed or removed. If you add a dependency on another example or a test app, your test case might need to be rewritten if someone has to modify or remove the example or a test app your test case depends on. + +For convenience, the `build_test_app` app included here provides several placeholders which can be modified using the `replace_in_file` function. You can find the placeholders by running `grep -r placeholder_ build_test_app`. diff --git a/tools/test_build_system/build_test_app/CMakeLists.txt b/tools/test_build_system/build_test_app/CMakeLists.txt new file mode 100644 index 0000000000..d73b116405 --- /dev/null +++ b/tools/test_build_system/build_test_app/CMakeLists.txt @@ -0,0 +1,9 @@ +cmake_minimum_required(VERSION 3.16) + +# placeholder_before_include_project_cmake + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) + +# placeholder_after_include_project_cmake + +project(build_test_app) diff --git a/tools/test_build_system/build_test_app/README.md b/tools/test_build_system/build_test_app/README.md new file mode 100644 index 0000000000..faf3c22837 --- /dev/null +++ b/tools/test_build_system/build_test_app/README.md @@ -0,0 +1 @@ +Information about this test app can be found [here](../README.md#application-under-test). diff --git a/tools/test_build_system/build_test_app/main/CMakeLists.txt b/tools/test_build_system/build_test_app/main/CMakeLists.txt new file mode 100644 index 0000000000..a72bec5a39 --- /dev/null +++ b/tools/test_build_system/build_test_app/main/CMakeLists.txt @@ -0,0 +1,5 @@ +# placeholder_before_idf_component_register + +idf_component_register(SRCS "build_test_app.c" + # placeholder_inside_idf_component_register +) diff --git a/tools/test_build_system/build_test_app/main/build_test_app.c b/tools/test_build_system/build_test_app/main/build_test_app.c new file mode 100644 index 0000000000..89169f848a --- /dev/null +++ b/tools/test_build_system/build_test_app/main/build_test_app.c @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +// placeholder_before_main + +void app_main(void) +{ + // placeholder_inside_main +} diff --git a/tools/test_build_system/conftest.py b/tools/test_build_system/conftest.py new file mode 100644 index 0000000000..a575cf5696 --- /dev/null +++ b/tools/test_build_system/conftest.py @@ -0,0 +1,142 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +import datetime +import logging +import os +import shutil +import subprocess +import typing +from pathlib import Path +from tempfile import mkdtemp + +import pytest +from _pytest.fixtures import FixtureRequest +from test_build_system_helpers import EXT_IDF_PATH, EnvDict, IdfPyFunc, get_idf_build_env, run_idf_py + + +# Pytest hook used to check if the test has passed or failed, from a fixture. +# Based on https://docs.pytest.org/en/latest/example/simple.html#making-test-result-information-available-in-fixtures +@pytest.hookimpl(tryfirst=True, hookwrapper=True) +def pytest_runtest_makereport(item: typing.Any, call: typing.Any) -> typing.Generator[None, pytest.TestReport, None]: # pylint: disable=unused-argument + outcome = yield # Execute all other hooks to obtain the report object + report = outcome.get_result() + if report.when == 'call' and report.passed: + # set an attribute which can be checked using 'should_clean_test_dir' function below + setattr(item, 'passed', True) + + +def should_clean_test_dir(request: FixtureRequest) -> bool: + # Only remove the test directory if the test has passed + return getattr(request.node, 'passed', False) + + +def pytest_addoption(parser: pytest.Parser) -> None: + parser.addoption( + '--work-dir', action='store', default=None, + help='Directory for temporary files. If not specified, an OS-specific ' + 'temporary directory will be used.' + ) + + +@pytest.fixture(name='session_work_dir', scope='session', autouse=True) +def fixture_session_work_dir(request: FixtureRequest) -> typing.Generator[Path, None, None]: + work_dir = request.config.getoption('--work-dir') + if work_dir: + work_dir = os.path.join(work_dir, datetime.datetime.utcnow().strftime('%Y-%m-%d_%H-%M-%S')) + logging.debug(f'using work directory: {work_dir}') + os.makedirs(work_dir, exist_ok=True) + clean_dir = None + else: + work_dir = mkdtemp() + logging.debug(f'created temporary work directory: {work_dir}') + clean_dir = work_dir + + yield Path(work_dir) + + if clean_dir: + logging.debug(f'cleaning up {clean_dir}') + shutil.rmtree(clean_dir, ignore_errors=True) + + +@pytest.fixture +def test_app_copy(session_work_dir: Path, request: FixtureRequest) -> typing.Generator[Path, None, None]: + # by default, use hello_world app and copy it to a temporary directory with + # the name resembling that of the test + copy_from = 'tools/test_build_system/build_test_app' + copy_to = request.node.name + '_app' + + # allow overriding source and destination via pytest.mark.test_app_copy() + mark = request.node.get_closest_marker('test_app_copy') + if mark: + copy_from = mark.args[0] + if len(mark.args) > 1: + copy_to = mark.args[1] + + path_from = Path(os.environ['IDF_PATH']) / copy_from + path_to = session_work_dir / copy_to + + # if the new directory inside the original directory, + # make sure not to go into recursion. + ignore = shutil.ignore_patterns( + path_to.name, + # also ignore files which may be present in the work directory + 'build', 'sdkconfig') + + logging.debug(f'copying {path_from} to {path_to}') + shutil.copytree(path_from, path_to, ignore=ignore, symlinks=True) + + old_cwd = Path.cwd() + os.chdir(path_to) + + yield Path(path_to) + + os.chdir(old_cwd) + + if should_clean_test_dir(request): + logging.debug('cleaning up work directory after a successful test: {}'.format(path_to)) + shutil.rmtree(path_to, ignore_errors=True) + + +@pytest.fixture +def idf_copy(session_work_dir: Path, request: FixtureRequest) -> typing.Generator[Path, None, None]: + copy_to = request.node.name + '_idf' + + # allow overriding the destination via pytest.mark.idf_copy() + mark = request.node.get_closest_marker('idf_copy') + if mark: + copy_to = mark.args[0] + + path_from = EXT_IDF_PATH + path_to = session_work_dir / copy_to + + # if the new directory inside the original directory, + # make sure not to go into recursion. + ignore = shutil.ignore_patterns( + path_to.name, + # also ignore the build directories which may be quite large + '**/build') + + logging.debug(f'copying {path_from} to {path_to}') + shutil.copytree(path_from, path_to, ignore=ignore, symlinks=True) + + orig_idf_path = os.environ['IDF_PATH'] + + yield Path(path_to) + + os.environ['IDF_PATH'] = orig_idf_path + + if should_clean_test_dir(request): + logging.debug('cleaning up work directory after a successful test: {}'.format(path_to)) + shutil.rmtree(path_to, ignore_errors=True) + + +@pytest.fixture(name='default_idf_env') +def fixture_default_idf_env() -> EnvDict: + return get_idf_build_env(os.environ['IDF_PATH']) # type: ignore + + +@pytest.fixture +def idf_py(default_idf_env: EnvDict) -> IdfPyFunc: + def result(*args: str) -> subprocess.CompletedProcess: + return run_idf_py(*args, env=default_idf_env, workdir=os.getcwd()) # type: ignore + return result diff --git a/tools/test_build_system/pytest.ini b/tools/test_build_system/pytest.ini new file mode 100644 index 0000000000..4ceee1e0a8 --- /dev/null +++ b/tools/test_build_system/pytest.ini @@ -0,0 +1,19 @@ +[pytest] +addopts = -s -p no:pytest-embedded + +# log related +log_cli = True +log_cli_level = INFO +log_cli_format = %(asctime)s %(levelname)s %(message)s +log_cli_date_format = %Y-%m-%d %H:%M:%S + +# junit related +junit_family = xunit1 + +## log all to `system-out` when case fail +junit_logging = stdout +junit_log_passing_tests = False + +markers = + test_app_copy: specify relative path of the app to copy, and the prefix of the destination directory name + idf_copy: specify the prefix of the destination directory where IDF should be copied diff --git a/tools/test_build_system/test_build_system_helpers/__init__.py b/tools/test_build_system/test_build_system_helpers/__init__.py new file mode 100644 index 0000000000..90d69c3dc6 --- /dev/null +++ b/tools/test_build_system/test_build_system_helpers/__init__.py @@ -0,0 +1,11 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +from .editing import append_to_file, replace_in_file +from .idf_utils import EXT_IDF_PATH, EnvDict, IdfPyFunc, get_idf_build_env, run_idf_py +from .snapshot import Snapshot, get_snapshot + +__all__ = [ + 'append_to_file', 'replace_in_file', + 'get_idf_build_env', 'run_idf_py', 'EXT_IDF_PATH', 'EnvDict', 'IdfPyFunc', + 'Snapshot', 'get_snapshot' +] diff --git a/tools/test_build_system/test_build_system_helpers/editing.py b/tools/test_build_system/test_build_system_helpers/editing.py new file mode 100644 index 0000000000..7f21d52822 --- /dev/null +++ b/tools/test_build_system/test_build_system_helpers/editing.py @@ -0,0 +1,17 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +import typing +from pathlib import Path + + +def append_to_file(filename: typing.Union[str, Path], what: str) -> None: + with open(filename, 'a', encoding='utf-8') as f: + f.write(what) + + +def replace_in_file(filename: typing.Union[str, Path], search: str, replace: str) -> None: + with open(filename, 'r', encoding='utf-8') as f: + data = f.read() + result = data.replace(search, replace) + with open(filename, 'w', encoding='utf-8') as f: + f.write(result) diff --git a/tools/test_build_system/test_build_system_helpers/idf_utils.py b/tools/test_build_system/test_build_system_helpers/idf_utils.py new file mode 100644 index 0000000000..96cc33db9a --- /dev/null +++ b/tools/test_build_system/test_build_system_helpers/idf_utils.py @@ -0,0 +1,87 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +import logging +import os +import shutil +import subprocess +import sys +import typing +from pathlib import Path + +try: + EXT_IDF_PATH = os.environ['IDF_PATH'] # type: str +except KeyError: + print('IDF_PATH must be set before running this test', file=sys.stderr) + exit(1) + + +EnvDict = typing.Dict[str, str] +IdfPyFunc = typing.Callable[..., subprocess.CompletedProcess] + + +def find_python(path_var: str) -> str: + """ + Find python interpreter in the paths specified in the given PATH variable. + Returns the full path to the interpreter. + """ + res = shutil.which('python', path=path_var) + if res is None: + raise ValueError('python not found') + return res + + +def get_idf_build_env(idf_path: str) -> EnvDict: + """ + Get environment variables (as set by export.sh) for the specific IDF copy + :param idf_path: path of the IDF copy to use + :return: dictionary of environment variables and their values + """ + cmd = [ + sys.executable, + os.path.join(idf_path, 'tools', 'idf_tools.py'), + 'export', + '--format=key-value' + ] + keys_values = subprocess.check_output(cmd, stderr=subprocess.PIPE).decode() + env_vars = {key: os.path.expandvars(value) for key, value in + [line.split('=') for line in keys_values.splitlines()]} + # not set by idf_tools.py, normally set by export.sh + env_vars['IDF_PATH'] = idf_path + + return env_vars + + +def run_idf_py(*args: str, + env: typing.Optional[EnvDict] = None, + idf_path: typing.Optional[typing.Union[str,Path]] = None, + workdir: typing.Optional[str] = None) -> subprocess.CompletedProcess: + """ + Run idf.py command with given arguments, raise an exception on failure + :param args: arguments to pass to idf.py + :param env: environment variables to run the build with; if not set, the default environment is used + :param idf_path: path to the IDF copy to use; if not set, IDF_PATH from the 'env' argument is used + :param workdir: directory where to run the build; if not set, the current directory is used + """ + env_dict = dict(**os.environ) + if env is not None: + env_dict.update(env) + if not workdir: + workdir = os.getcwd() + # order: function argument -> value in env dictionary -> system environment + if idf_path is None: + idf_path = env_dict.get('IDF_PATH') + if not idf_path: + raise ValueError('IDF_PATH must be set in the env array if idf_path argument is not set') + + python = find_python(env_dict['PATH']) + + cmd = [ + python, + os.path.join(idf_path, 'tools', 'idf.py') + ] + cmd += args # type: ignore + logging.debug('running {} in {}'.format(' '.join(cmd), workdir)) + return subprocess.run( + cmd, env=env_dict, cwd=workdir, + check=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE, + text=True, encoding='utf-8', errors='backslashreplace') diff --git a/tools/test_build_system/test_build_system_helpers/snapshot.py b/tools/test_build_system/test_build_system_helpers/snapshot.py new file mode 100644 index 0000000000..79ee0ffa70 --- /dev/null +++ b/tools/test_build_system/test_build_system_helpers/snapshot.py @@ -0,0 +1,61 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +import fnmatch +import glob +import os +from typing import List, Optional, Tuple, Union + + +class Snapshot: + """ + Helper class for working with build snapshots. + A snapshot is a set of files along with their modification timestamps. + """ + def __init__(self, files: List[str]) -> None: + """Create a snapshot of the given list of files, recording their mtimes""" + self.info: List[Tuple[str, int]] = [] + for file in sorted(files): + st = os.stat(file) + self.info.append((file, st.st_mtime_ns)) + + def assert_same(self, other: 'Snapshot') -> None: + """Assert that this snapshot has the same files and mtimes as the other snapshot""" + for my_info, other_info in zip(self.info, other.info): + assert my_info[0] == other_info[0], f'Snapshots mismatch, expected file {my_info[0]}, found {other_info[0]}' + assert my_info[1] == other_info[1], f'File {my_info[0]} timestamp has changed! diff={(other_info[1]-my_info[1])/10**9}' + + def assert_different(self, other: 'Snapshot') -> None: + """Assert that this snapshot has the same files as the other snapshot, but all mtimes are different""" + for my_info, other_info in zip(self.info, other.info): + assert my_info[0] == other_info[0], f'Snapshots mismatch, expected file {my_info[0]}, found {other_info[0]}' + assert my_info[1] != other_info[1], f'File {my_info[0]} timestamp has not changed! ({my_info[1]})' + + +def get_snapshot(glob_patterns: Union[str, List[str]], + exclude_patterns: Optional[Union[str, List[str]]] = None) -> Snapshot: + """Return a snapshot including the files matched by glob_patterns, and excluding those matched by exclude_patterns""" + if isinstance(glob_patterns, str): + glob_patterns = [glob_patterns] + + if isinstance(exclude_patterns, str): + exclude_patterns_list = [exclude_patterns] + elif exclude_patterns is None: + exclude_patterns_list = [] + elif isinstance(exclude_patterns, list): + exclude_patterns_list = exclude_patterns + else: + raise ValueError(f'Unexpcted type of exclude_patterns: ({type(exclude_patterns)}') + + # whether the path found by glob.glob should be excluded? + def should_exclude(filename: str) -> bool: + return os.path.isdir(filename) or \ + any((fnmatch.fnmatch(filename, pattern) for pattern in exclude_patterns_list)) + + files_to_snapshot: List[str] = [] + for pattern in glob_patterns: + found = filter(lambda f: not should_exclude(f), + glob.glob(pattern, recursive=True)) + if not found: + raise RuntimeError(f'failed to match any files with pattern {pattern}') + files_to_snapshot.extend(found) + return Snapshot(files_to_snapshot) diff --git a/tools/test_build_system/test_common.py b/tools/test_build_system/test_common.py new file mode 100644 index 0000000000..bd50aeb8f1 --- /dev/null +++ b/tools/test_build_system/test_common.py @@ -0,0 +1,57 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +import shutil +import subprocess +from pathlib import Path + +import pytest +from test_build_system_helpers import EnvDict, IdfPyFunc, get_snapshot, replace_in_file + + +@pytest.mark.usefixtures('test_app_copy') +@pytest.mark.test_app_copy('examples/get-started/blink') +def test_compile_commands_json_updated_by_reconfigure(idf_py: IdfPyFunc) -> None: + output = idf_py('reconfigure') + assert 'Building ESP-IDF components for target esp32' in output.stdout + snapshot_1 = get_snapshot(['build/compile_commands.json']) + snapshot_2 = get_snapshot(['build/compile_commands.json']) + snapshot_2.assert_same(snapshot_1) + idf_py('reconfigure') + snapshot_3 = get_snapshot(['build/compile_commands.json']) + snapshot_3.assert_different(snapshot_2) + + +@pytest.mark.usefixtures('test_app_copy') +def test_of_test_app_copy(idf_py: IdfPyFunc) -> None: + p = Path('main/idf_component.yml') + p.write_text('syntax_error\n') + try: + with (pytest.raises(subprocess.CalledProcessError)) as exc_info: + idf_py('reconfigure') + assert 'ERROR: Unknown format of the manifest file:' in exc_info.value.stderr + finally: + p.unlink() + + +@pytest.mark.usefixtures('test_app_copy') +def test_hints_no_color_output_when_noninteractive(idf_py: EnvDict) -> None: + """Check that idf.py hints don't include color escape codes in non-interactive builds""" + + # make the build fail in such a way that idf.py shows a hint + replace_in_file('main/build_test_app.c', '// placeholder_inside_main', + 'esp_chip_info_t chip_info; esp_chip_info(&chip_info);') + + with (pytest.raises(subprocess.CalledProcessError)) as exc_info: + idf_py('build') + + # Should not actually include a color escape sequence! + # Change the assert to the correct value once the bug is fixed. + assert '\x1b[0;33mHINT: esp_chip_info.h' in exc_info.value.stderr + + +@pytest.mark.usefixtures('test_app_copy') +def test_idf_copy(idf_copy: Path, idf_py: IdfPyFunc) -> None: + # idf_copy is the temporary IDF copy. + # For example, we can check if idf.py build can work without the .git directory: + shutil.rmtree(idf_copy / '.git', ignore_errors=True) + idf_py('build') diff --git a/tools/test_build_system/test_rebuild.py b/tools/test_build_system/test_rebuild.py new file mode 100644 index 0000000000..c3ddd95890 --- /dev/null +++ b/tools/test_build_system/test_rebuild.py @@ -0,0 +1,139 @@ +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +# These tests check whether the build system rebuilds some files or not +# depending on the changes to the project. +import logging +import os +from pathlib import Path +from typing import List, Union + +import pytest +from test_build_system_helpers import IdfPyFunc, get_snapshot, replace_in_file + +BOOTLOADER_BINS = ['build/bootloader/bootloader.elf', 'build/bootloader/bootloader.bin'] +APP_BINS = ['build/build_test_app.elf', 'build/build_test_app.bin'] +PARTITION_BIN = ['build/partition_table/partition-table.bin'] +JSON_METADATA = ['build/project_description.json', 'build/flasher_args.json', 'build/config/kconfig_menus.json', 'build/config/sdkconfig.json'] +ALL_ARTIFACTS = [ + *BOOTLOADER_BINS, + *APP_BINS, + *PARTITION_BIN, + *JSON_METADATA +] + + +@pytest.mark.usefixtures('test_app_copy') +def test_rebuild_no_changes(idf_py: IdfPyFunc) -> None: + logging.info('initial build') + idf_py('build') + logging.info('get the first snapshot') + # excluding the 'log' subdirectory here since it changes after every build + all_build_files = get_snapshot('build/**/*', exclude_patterns='build/log/*') + + logging.info('check that all build artifacts were generated') + for artifact in ALL_ARTIFACTS: + assert Path(artifact).exists() + + logging.info('build again with no changes') + idf_py('build') + # if there are no changes, nothing gets rebuilt + all_build_files_after_rebuild = get_snapshot('build/**/*', exclude_patterns='build/log/*') + all_build_files_after_rebuild.assert_same(all_build_files) + + +def rebuild_and_check(idf_py: IdfPyFunc, + should_be_rebuilt: Union[str, List[str]], + should_not_be_rebuilt: Union[str, List[str]]) -> None: + """ + Helper function for the test cases below. + Asserts that the files matching 'should_be_rebuilt' patterns are rebuilt + and files matching 'should_not_be_rebuilt' patterns aren't, after + touching (updating the mtime) of the given 'file_to_touch' and rebuilding. + """ + snapshot_should_be_rebuilt = get_snapshot(should_be_rebuilt) + snapshot_should_not_be_rebuilt = get_snapshot(should_not_be_rebuilt) + idf_py('build') + snapshot_should_be_rebuilt.assert_different(get_snapshot(should_be_rebuilt)) + snapshot_should_not_be_rebuilt.assert_same(get_snapshot(should_not_be_rebuilt)) + + +# For this and the following test function, there are actually multiple logical +# tests in one test function. It would be better to have every check in a separate +# test case, but that would mean doing a full clean build each time. Having a few +# related checks per test function looks like a reasonable compromise. +# If the test function grows too big, try splitting it into two or more functions. +@pytest.mark.usefixtures('test_app_copy') +def test_rebuild_source_files(idf_py: IdfPyFunc) -> None: + idf_path = Path(os.environ['IDF_PATH']) + logging.info('initial build') + idf_py('build') + + logging.info('updating a component source file rebuilds only that component') + component_files_patterns = [ + 'build/esp-idf/esp_system/libesp_system.a', + 'build/esp-idf/esp_system/CMakeFiles/__idf_esp_system.dir/port/cpu_start.c.obj'] + other_files_patterns = [ + 'build/esp-idf/lwip/liblwip.a', + 'build/esp-idf/freertos/libfreertos.a', + *BOOTLOADER_BINS, + *PARTITION_BIN] + (idf_path / 'components/esp_system/port/cpu_start.c').touch() + rebuild_and_check(idf_py, + component_files_patterns, other_files_patterns) + + logging.info('changing a bootloader source file rebuilds the bootloader') + (idf_path / 'components/bootloader/subproject/main/bootloader_start.c').touch() + rebuild_and_check(idf_py, + BOOTLOADER_BINS, APP_BINS + PARTITION_BIN) + + logging.info('changing the partitions CSV file rebuilds only the partition table') + (idf_path / 'components/partition_table/partitions_singleapp.csv').touch() + rebuild_and_check(idf_py, + PARTITION_BIN, APP_BINS + BOOTLOADER_BINS) + + logging.info('sdkconfig update triggers full recompile') + # pick on .c, .cpp, .S file which includes sdkconfig.h: + obj_files = [ + 'build/esp-idf/newlib/CMakeFiles/__idf_newlib.dir/newlib_init.c.obj', + 'build/esp-idf/nvs_flash/CMakeFiles/__idf_nvs_flash.dir/src/nvs_api.cpp.obj' + 'build/esp-idf/esp_system/CMakeFiles/__idf_esp_system.dir/port/arch/xtensa/panic_handler_asm.S.obj' + ] + sdkconfig_files = [ + 'build/config/sdkconfig.h', + 'build/config/sdkconfig.json' + ] + replace_in_file('sdkconfig', '# CONFIG_FREERTOS_UNICORE is not set', 'CONFIG_FREERTOS_UNICORE=y') + rebuild_and_check(idf_py, APP_BINS + BOOTLOADER_BINS + obj_files + sdkconfig_files, PARTITION_BIN) + + logging.info('Updating project CMakeLists.txt triggers app recompile') + replace_in_file('CMakeLists.txt', + '# placeholder_after_include_project_cmake', + 'add_compile_options("-DUSELESS_MACRO_DOES_NOTHING=1")') + rebuild_and_check(idf_py, APP_BINS + obj_files, PARTITION_BIN + BOOTLOADER_BINS + sdkconfig_files) + + +@pytest.mark.usefixtures('test_app_copy') +def test_rebuild_linker(idf_py: IdfPyFunc) -> None: + idf_path = Path(os.environ['IDF_PATH']) + logging.info('initial build') + idf_py('build') + + logging.info('Updating rom ld file should re-link app and bootloader') + (idf_path / 'components/esp_rom/esp32/ld/esp32.rom.ld').touch() + rebuild_and_check(idf_py, + APP_BINS + BOOTLOADER_BINS, PARTITION_BIN) + + logging.info('Updating app-only sections ld file should only re-link the app') + (idf_path / 'components/esp_system/ld/esp32/sections.ld.in').touch() + rebuild_and_check(idf_py, + APP_BINS, BOOTLOADER_BINS + PARTITION_BIN) + + logging.info('Updating app-only memory ld file should only re-link the app') + (idf_path / 'components/esp_system/ld/esp32/memory.ld.in').touch() + rebuild_and_check(idf_py, + APP_BINS, BOOTLOADER_BINS + PARTITION_BIN) + + logging.info('Updating fragment file should only re-link the app') + (idf_path / 'components/esp_common/common.lf').touch() + rebuild_and_check(idf_py, + APP_BINS, BOOTLOADER_BINS + PARTITION_BIN) diff --git a/tools/test_idf_monitor/run_test_idf_monitor.py b/tools/test_idf_monitor/run_test_idf_monitor.py index dc151a16e7..ed4523a098 100755 --- a/tools/test_idf_monitor/run_test_idf_monitor.py +++ b/tools/test_idf_monitor/run_test_idf_monitor.py @@ -3,8 +3,6 @@ # SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 -from __future__ import print_function, unicode_literals - import errno import filecmp import os @@ -16,7 +14,6 @@ import sys import tempfile import threading import time -from builtins import object from io import open XTENSA_ARGS = '--toolchain-prefix xtensa-esp32-elf-' diff --git a/tools/test_idf_py/error_output.yml b/tools/test_idf_py/error_output.yml new file mode 100644 index 0000000000..0bc84a2a2b --- /dev/null +++ b/tools/test_idf_py/error_output.yml @@ -0,0 +1,113 @@ +'ccache error: Failed to create temporary file\n': + "HINT: On Windows, you should enable long path support in the installer, or disable ccache temporarily. See 'idf.py --help' or the documentation how to achieve this." + +"CMake Error at C:/Users/esp-idf/esp-idf/ (message): Directory specified in EXTRA_COMPONENT_DIRS doesn't exist: C:/Users/esp-idf/esp-idf/examples/common_components/component\n": + "HINT: The component with path specified in the EXTRA_COMPONENT_DIRS variable has been moved to IDF component manager (or has been removed).\nPlease look out for component in 'https://components.espressif.com' and add using 'idf.py add-dependency' command.\nRefer to the migration guide for more details." + +'CMake Error: The current CMakeCache.txt directory C:/Users/esp-idf/examples/get-started/hello_world/build is different than the directory /mnt/c/Users/esp-idf/examples/get-started/hello_world/build where CMakeCache.txt was created.\n': + "HINT: Run 'idf.py fullclean' and try the build again." + +"error: 'portTICK_RATE_MS' undeclared\n": + 'HINT: You are maybe using pre FreeRTOS V8.0.0 APIs. The backward compatibility of such APIs is no longer enabled by default. Please turn on CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY explicitly to use such APIs.' + +"error: enumeration value 'HTTP_EVENT_REDIRECT' not handled in switch\n": + "HINT: The event handler, specified in the 'event_handler' element, of the 'esp_http_client_config_t' struct now needs to handle the new 'HTTP_EVENT_REDIRECT' event case." + +"error: implicit declaration of function 'portENTER_CRITICAL_NESTED'\n": + 'HINT: The header file portmacro_deprecated.h has been removed. Users should refer the migration guide for alternative functions.' + +"error: implicit declaration of function 'bootloader_common_get_reset_reason'\n": + "HINT: Function 'bootloader_common_get_reset_reason()' has been removed. Please use the function 'esp_rom_get_reset_reason()' in the ROM component." + +"error: implicit declaration of function 'esp_base_mac_addr_get'\n": + 'HINT: esp_mac.h header file is not included by esp_system.h anymore. It shall then be manually included with #include "esp_mac.h"' + +"error: implicit declaration of function 'esp_chip_info'\n": + 'HINT: esp_chip_info.h header file is not included by esp_system.h anymore. It shall then be manually included with #include "esp_chip_info.h"' + +"error: implicit declaration of function 'esp_cpu_ccount_t'\n": + 'HINT: Use esp_cpu_cycle_count_t defined in esp_cpu.h instead of esp_cpu_ccount_t.' + +"error: implicit declaration of function 'esp_cpu_get_ccount'\n": + 'HINT: Use esp_cpu_get_cycle_count() defined in esp_cpu.h instead of esp_cpu_get_ccount.' + +"error: implicit declaration of function 'esp_cpu_set_ccount'\n": + 'HINT: Use esp_cpu_set_cycle_count() defined in esp_cpu.h instead of esp_cpu_set_ccount.' + +"error: implicit declaration of function 'esp_efuse_get_chip_ver'\n": + "HINT: Function 'esp_efuse_get_chip_ver()' has been removed. Please use the function efuse_hal_get_major_chip_version()." + +"error: implicit declaration of function 'esp_fill_random'\n": + 'HINT: esp_random.h header file is not included by esp_system.h anymore. It shall then be manually included with #include "esp_random.h"' + +"error: implicit declaration of function 'esp_spiram_get_chip_size'\n": + "HINT: Function 'esp_spiram_get_chip_size and esp_spiram_get_size' has been removed. Please use the function esp_psram_get_size()." + +"error: invalid use of incomplete typedef 'esp_tls_t'\n": + "HINT: The struct 'esp_tls_t' has now been made private - its elements can be only be accessed/modified through respective getter/setter functions. Please refer to the migration guide for more information." + +"error: unknown type name 'TaskSnapshot_t'\n": + 'HINT: The header file task_snapshot.h is no longer included as part of freertos/task.h. Users need to include freertos/task_snapshot.h explicitly.' + +"Failed to resolve component 'component'\n": + "HINT: The component component has been moved to the IDF component manager or has been removed and refactored into some other component.\nPlease look out for component in 'https://components.espressif.com' and add using 'idf.py add-dependency' command.\nRefer to the migration guide for more details." + +'fatal error: tmp/atca_mbedtls_wrap.h: No such file or directory\n': + "HINT: To use CONFIG_ESP_TLS_USE_SECURE_ELEMENT option, please install `esp-cryptoauthlib` using 'idf.py add-dependency espressif/esp-cryptoauthlib'" + +'fatal error: brownout.h: No such file or directory\n': + 'HINT: The Brownout API (functions/types/macros prefixed with "esp_brownout") has been made into a private API. If users still require usage of the Brownout API (though this is not recommended), it can be included via #include "esp_private/brownout.h".' + +'fatal error: compare_set.h: No such file or directory\n': + 'HINT: compare_set.h was removed. Include and use the API function provided by esp_cpu.h instead.' + +'fatal error: eh_frame_parser.h: No such file or directory\n': + 'HINT: The Backtrace Parser API (functions/types/macros prefixed with "eh_frame_parser") has been made into a private API. If users still require usage of the Backtrace Parser API (though this is not recommended), it can be included via #include "esp_private/eh_frame_parser.h".' + +'fatal error: esp32/cache_err_int.h: No such file or directory\n': + 'HINT: The Cache Error Interrupt API (functions/types/macros prefixed with "esp_cache_err") has been made into a private API. If users still require usage of the Cache Error Interrupt API (though this is not recommended), it can be included via #include "esp_private/cache_err_int.h".' + +'fatal error: esp32/clk.h: No such file or directory\n': + 'HINT: The ESP Clock API (functions/types/macros prefixed with "esp_clk") has been made into a private API. If users still require usage of the ESP Clock API (though this is not recommended), it can be included via #include "esp_private/esp_clk.h".' + +'fatal error: esp_adc_cal.h: No such file or directory\n': + "HINT: ``esp_adc_cal`` component is no longer supported. New adc calibration driver is in ``esp_adc``. Legacy adc calibration driver has been moved into ``esp_adc`` component. To use legacy ``esp_adc_cal`` driver APIs, you should add ``esp_adc`` component to the list of component requirements in CMakeLists.txt. For more information run 'idf.py docs -sp migration-guides/release-5.x/peripherals.html'." + +'fatal error: esp_intr.h: No such file or directory\n': + 'HINT: esp_intr.h was removed. Include esp_intr_alloc.h instead.' + +'fatal error: esp_panic.h: No such file or directory\n': + 'HINT: esp_panic.h was removed. Include use functionalities provided in esp_debug_helpers.h instead.' + +'fatal error: esp_rom_tjpgd.h: No such file or directory\n': + "HINT: esp_rom_tjpgd.h was removed. Please use esp_jpeg component from IDF component manager instead.\nPlease look out for component in 'https://components.espressif.com' and add using 'idf.py add-dependency' command.\nRefer to the migration guide for more details." + +'fatal error: soc/cpu.h: No such file or directory\n': + 'HINT: soc/cpu.h was removed. Include and use the API function provided by esp_cpu.h instead.' + +'fatal error: soc/spinlock.h: No such file or directory\n': + "HINT: spinlock.h must be included without the 'soc' part." + +'fatal error: soc_log.h: No such file or directory\n': + 'HINT: soc_log.h was renamed and made private. Consider using the logging APIs provided under esp_log.h instead.' + +'fatal error: spiram.h: No such file or directory\n': + 'HINT: spiram.h was removed. Include esp_psram.h instead. Make sure to also add esp_psram as a dependency in your CMakeLists.txt file.' + +'fatal error: trax.h: No such file or directory\n': + 'HINT: The Trax API (functions/types/macros prefixed with "trax_") has been made into a private API. If users still require usage of the Trax API (though this is not recommended), it can be included via #include "esp_private/trax.h".' + +"format 'format' expects argument of type 'unsigned int', but argument arg has type 'uint32_t' {aka 'int'}\n": + "HINT: The issue is better to resolve by replacing format specifiers to 'PRI'-family macros (include header file)." + +"ImportError: bad magic number in 'kconfiglib':\n": + "HINT: Run 'idf.py python-clean', and try again" + +'The CMAKE_CXX_COMPILER: xtensa-esp32s3-elf-g++ is not a full path and was not found in the PATH.\n': + "HINT: Try to reinstall the toolchain for the chip that you trying to use. \nFor more information run 'idf.py docs -sp get-started/#installation' and follow the instructions for your system" + +'The keyword signature for target_link_libraries has already been used\n': + 'HINT: Projects using target_link_libraries with project_elf explicitly and custom CMake projects must specify PRIVATE, PUBLIC or INTERFACE arguments.' + +"warning: passing argument 1 of 'esp_secure_boot_read_key_digests' from incompatible pointer type\n": + 'HINT: The parameter type of the function esp_secure_boot_read_key_digests() has been changed from ets_secure_boot_key_digests_t* to esp_secure_boot_key_digests_t*.' diff --git a/tools/test_idf_py/test_hints.py b/tools/test_idf_py/test_hints.py new file mode 100755 index 0000000000..31699801a0 --- /dev/null +++ b/tools/test_idf_py/test_hints.py @@ -0,0 +1,35 @@ +#!/usr/bin/env python +# +# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +import os +import sys +import tempfile +import unittest + +import yaml + +CWD = os.path.join(os.path.dirname(__file__)) +ERR_OUT_YML = os.path.join(CWD, 'error_output.yml') + +try: + from idf_py_actions.tools import generate_hints +except ImportError: + sys.path.append(os.path.join(CWD, '..')) + from idf_py_actions.tools import generate_hints + + +class TestHintsMassages(unittest.TestCase): + def test_output(self) -> None: + with open(ERR_OUT_YML) as f: + error_output = yaml.safe_load(f) + for error, hint in error_output.items(): + with tempfile.NamedTemporaryFile(mode='w') as f: + f.write(error) + f.flush() + for generated_hint in generate_hints(f.name): + self.assertEqual(generated_hint, hint) + + +if __name__ == '__main__': + unittest.main() diff --git a/tools/test_idf_py/test_idf_py.py b/tools/test_idf_py/test_idf_py.py index 4a14faa687..edc63bfec7 100755 --- a/tools/test_idf_py/test_idf_py.py +++ b/tools/test_idf_py/test_idf_py.py @@ -9,7 +9,9 @@ import subprocess import sys from unittest import TestCase, main, mock +import elftools.common.utils as ecu import jsonschema +from elftools.elf.elffile import ELFFile try: from StringIO import StringIO @@ -25,7 +27,8 @@ except ImportError: current_dir = os.path.dirname(os.path.realpath(__file__)) idf_py_path = os.path.join(current_dir, '..', 'idf.py') extension_path = os.path.join(current_dir, 'test_idf_extensions', 'test_ext') -link_path = os.path.join(current_dir, '..', 'idf_py_actions', 'test_ext') +py_actions_path = os.path.join(current_dir, '..', 'idf_py_actions') +link_path = os.path.join(py_actions_path, 'test_ext') class TestWithoutExtensions(TestCase): @@ -246,5 +249,47 @@ class TestHelpOutput(TestWithoutExtensions): action_test(['idf.py', 'help', '--json', '--add-options'], schema_json) +class TestROMs(TestWithoutExtensions): + def get_string_from_elf_by_addr(self, filename: str, address: int) -> str: + result = '' + with open(filename, 'rb') as stream: + elf_file = ELFFile(stream) + ro = elf_file.get_section_by_name('.rodata') + ro_addr_delta = ro['sh_addr'] - ro['sh_offset'] + cstring = ecu.parse_cstring_from_stream(ro.stream, address - ro_addr_delta) + if cstring: + result = str(cstring.decode('utf-8')) + return result + + def test_roms_validate_json(self): + with open(os.path.join(py_actions_path, 'roms.json'), 'r') as f: + roms_json = json.load(f) + + with open(os.path.join(py_actions_path, 'roms_schema.json'), 'r') as f: + schema_json = json.load(f) + jsonschema.validate(roms_json, schema_json) + + def test_roms_check_supported_chips(self): + from idf_py_actions.constants import SUPPORTED_TARGETS + with open(os.path.join(py_actions_path, 'roms.json'), 'r') as f: + roms_json = json.load(f) + for chip in SUPPORTED_TARGETS: + self.assertTrue(chip in roms_json, msg=f'Have no ROM data for chip {chip}') + + def test_roms_validate_build_date(self): + sys.path.append(py_actions_path) + + rom_elfs_dir = os.getenv('ESP_ROM_ELF_DIR') + with open(os.path.join(py_actions_path, 'roms.json'), 'r') as f: + roms_json = json.load(f) + + for chip in roms_json: + for k in roms_json[chip]: + rom_file = os.path.join(rom_elfs_dir, f'{chip}_rev{k["rev"]}_rom.elf') + build_date_str = self.get_string_from_elf_by_addr(rom_file, int(k['build_date_str_addr'], base=16)) + self.assertTrue(len(build_date_str) == 11) + self.assertTrue(build_date_str == k['build_date_str']) + + if __name__ == '__main__': main() diff --git a/tools/test_idf_size/expected_output b/tools/test_idf_size/expected_output index 7d0b68ea9c..3c721c910b 100644 --- a/tools/test_idf_size/expected_output +++ b/tools/test_idf_size/expected_output @@ -37,8 +37,8 @@ Used static IRAM: 38932 bytes ( 92140 remain, 29.7% used) .text size: 37908 bytes .vectors size: 1024 bytes Used Flash size : 186524 bytes - .text : 146944 bytes - .rodata : 39580 bytes + .text: 146944 bytes + .rodata: 39580 bytes Total image size: 234780 bytes (.bin may be padded larger) *** @@ -62,8 +62,8 @@ Used static IRAM: 181518 bytes ( -50446 remain, 138.5% used) Overflow detected! .text size: 180491 bytes .vectors size: 1027 bytes Used Flash size : 531135 bytes - .text : 432171 bytes - .rodata : 98708 bytes + .text: 432171 bytes + .rodata: 98708 bytes Total image size: 730117 bytes (.bin may be padded larger) *** @@ -76,8 +76,8 @@ Used static IRAM: 38932 bytes ( 92140 remain, 29.7% used) .text size: 37908 bytes .vectors size: 1024 bytes Used Flash size : 186524 bytes - .text : 146944 bytes - .rodata : 39580 bytes + .text: 146944 bytes + .rodata: 39580 bytes Total image size: 234780 bytes (.bin may be padded larger) Per-archive contributions to ELF file: Archive File DRAM .data & 0.bss IRAM0 .text & 0.vectors ram_st_total Flash .text & .rodata flash_total @@ -130,8 +130,8 @@ Used static IRAM: 38932 bytes ( 92140 remain, 29.7% used) .text size: 37908 bytes .vectors size: 1024 bytes Used Flash size : 186524 bytes - .text : 146944 bytes - .rodata : 39580 bytes + .text: 146944 bytes + .rodata: 39580 bytes Total image size: 234780 bytes (.bin may be padded larger) Per-file contributions to ELF file: Object File DRAM .data & 0.bss IRAM0 .text & 0.vectors ram_st_total Flash .text & .rodata flash_total @@ -427,47 +427,47 @@ Used static IRAM: 38932 bytes ( 92140 remain, 29.7% used) .text size: 37908 bytes .vectors size: 1024 bytes Used Flash size : 186524 bytes - .text : 146944 bytes - .rodata : 39580 bytes + .text: 146944 bytes + .rodata: 39580 bytes Total image size: 234780 bytes (.bin may be padded larger) Symbols within the archive: libdriver.a (Not all symbols may be reported) Symbols from section: .dram0.bss - p_uart_obj : 12 - s_rtc_isr_handle : 4 - s_rtc_isr_handler_list : 4 + p_uart_obj : 12 + s_rtc_isr_handle : 4 + s_rtc_isr_handler_list : 4 Section total: 20 Symbols from section: .dram0.data - timer_spinlock : 16 - periph_spinlock : 8 - s_rtc_isr_handler_list_lock : 8 - uart_selectlock : 8 + timer_spinlock : 16 + periph_spinlock : 8 + s_rtc_isr_handler_list_lock : 8 + uart_selectlock : 8 Section total: 40 Symbols from section: .flash.rodata - str1.4 : 249 - get_clk_en_mask : 128 - get_rst_en_mask : 128 - __FUNCTION__$5441 : 24 - TG : 8 + str1.4 : 249 + get_clk_en_mask : 128 + get_rst_en_mask : 128 + __FUNCTION__$5441 : 24 + TG : 8 Section total: 537 Symbols from section: .flash.text - get_clk_en_mask : 211 - get_rst_en_mask : 157 - timer_group_intr_enable : 112 - rtc_isr : 86 - periph_module_enable : 78 - rtc_isr_ensure_installed : 75 - rtc_gpio_force_hold_dis_all : 65 - rtc_isr_register : 65 - is_wifi_clk_peripheral : 28 - uart_set_select_notif_callback : 26 - get_rst_en_reg : 25 - get_clk_en_reg : 21 - uart_get_selectlock : 12 + get_clk_en_mask : 211 + get_rst_en_mask : 157 + timer_group_intr_enable : 112 + rtc_isr : 86 + periph_module_enable : 78 + rtc_isr_ensure_installed : 75 + rtc_gpio_force_hold_dis_all : 65 + rtc_isr_register : 65 + is_wifi_clk_peripheral : 28 + uart_set_select_notif_callback : 26 + get_rst_en_reg : 25 + get_clk_en_reg : 21 + uart_get_selectlock : 12 Section total: 961 Symbols from section: .iram0.text @@ -505,8 +505,8 @@ Used static IRAM: 38932 bytes ( 92140 remain, 29.7% used) 18796 .text size: 37908 bytes 18796 +19112 .vectors size: 1024 bytes 0 +1024 Used Flash size : 186524 bytes 0 +186524 - .text : 146944 bytes 0 +146944 - .rodata : 39580 bytes 0 +39580 + .text: 146944 bytes 0 +146944 + .rodata: 39580 bytes 0 +39580 Total image size: 234780 bytes (.bin may be padded larger) 25960 +208820 *** @@ -522,8 +522,8 @@ Used static IRAM: 38932 bytes ( 92140 remain, 29.7% used) 38932 .text size: 37908 bytes 37908 .vectors size: 1024 bytes 1024 Used Flash size : 186524 bytes 186524 - .text : 146944 bytes 146944 - .rodata : 39580 bytes 39580 + .text: 146944 bytes 146944 + .rodata: 39580 bytes 39580 Total image size: 234780 bytes (.bin may be padded larger) 234780 *** @@ -539,8 +539,8 @@ Used static IRAM: 38932 bytes ( 92140 remain, 29.7% used) 38956 .text size: 37908 bytes 37929 -21 .vectors size: 1024 bytes 1027 -3 Used Flash size : 186524 bytes 99551 +86973 - .text : 146944 bytes 77191 +69753 - .rodata : 39580 bytes 22360 +17220 + .text: 146944 bytes 77191 +69753 + .rodata: 39580 bytes 22360 +17220 Total image size: 234780 bytes (.bin may be padded larger) 147087 +87693 *** @@ -556,8 +556,8 @@ Used static IRAM: 38956 bytes ( 92116 remain, 29.7% used) 38932 .text size: 37929 bytes 37908 +21 .vectors size: 1027 bytes 1024 +3 Used Flash size : 99551 bytes 186524 -86973 - .text : 77191 bytes 146944 -69753 - .rodata : 22360 bytes 39580 -17220 + .text: 77191 bytes 146944 -69753 + .rodata: 22360 bytes 39580 -17220 Total image size: 147087 bytes (.bin may be padded larger) 234780 -87693 *** @@ -574,8 +574,8 @@ Used static IRAM: 38932 bytes ( 92140 remain, 29.7% used) 18796 .text size: 37908 bytes 18796 +19112 .vectors size: 1024 bytes 0 +1024 Used Flash size : 186524 bytes 0 +186524 - .text : 146944 bytes 0 +146944 - .rodata : 39580 bytes 0 +39580 + .text: 146944 bytes 0 +146944 + .rodata: 39580 bytes 0 +39580 Total image size: 234780 bytes (.bin may be padded larger) 25960 +208820 Per-archive contributions to ELF file: Archive File DRAM .data & 0.bss & 0.rodata IRAM .text & 0.text & 0.vectors & _loader.text ram_st_total Flash .text & .rodata flash_total @@ -639,8 +639,8 @@ Used static IRAM: 38932 bytes ( 92140 remain, 29.7% used) 38932 .text size: 37908 bytes 37908 .vectors size: 1024 bytes 1024 Used Flash size : 186524 bytes 186524 - .text : 146944 bytes 146944 - .rodata : 39580 bytes 39580 + .text: 146944 bytes 146944 + .rodata: 39580 bytes 39580 Total image size: 234780 bytes (.bin may be padded larger) 234780 Per-archive contributions to ELF file: Archive File DRAM .data & 0.bss IRAM0 .text & 0.vectors ram_st_total Flash .text & .rodata flash_total @@ -698,8 +698,8 @@ Used static IRAM: 38932 bytes ( 92140 remain, 29.7% used) 38956 .text size: 37908 bytes 37929 -21 .vectors size: 1024 bytes 1027 -3 Used Flash size : 186524 bytes 99551 +86973 - .text : 146944 bytes 77191 +69753 - .rodata : 39580 bytes 22360 +17220 + .text: 146944 bytes 77191 +69753 + .rodata: 39580 bytes 22360 +17220 Total image size: 234780 bytes (.bin may be padded larger) 147087 +87693 Per-archive contributions to ELF file: Archive File DRAM .data & 0.bss IRAM0 .text & 0.vectors ram_st_total Flash .text & .rodata flash_total @@ -769,8 +769,8 @@ Used static IRAM: 38956 bytes ( 92116 remain, 29.7% used) 38932 .text size: 37929 bytes 37908 +21 .vectors size: 1027 bytes 1024 +3 Used Flash size : 99551 bytes 186524 -86973 - .text : 77191 bytes 146944 -69753 - .rodata : 22360 bytes 39580 -17220 + .text: 77191 bytes 146944 -69753 + .rodata: 22360 bytes 39580 -17220 Total image size: 147087 bytes (.bin may be padded larger) 234780 -87693 Per-archive contributions to ELF file: Archive File DRAM .data & 0.bss IRAM0 .text & 0.vectors ram_st_total Flash .text & .rodata flash_total @@ -841,8 +841,8 @@ Used static IRAM: 38932 bytes ( 92140 remain, 29.7% used) 18796 .text size: 37908 bytes 18796 +19112 .vectors size: 1024 bytes 0 +1024 Used Flash size : 186524 bytes 0 +186524 - .text : 146944 bytes 0 +146944 - .rodata : 39580 bytes 0 +39580 + .text: 146944 bytes 0 +146944 + .rodata: 39580 bytes 0 +39580 Total image size: 234780 bytes (.bin may be padded larger) 25960 +208820 Per-file contributions to ELF file: Object File DRAM .data & 0.bss & 0.rodata IRAM .text & 0.text & 0.vectors & _loader.text ram_st_total Flash .text & .rodata flash_total @@ -1185,8 +1185,8 @@ Used static IRAM: 38932 bytes ( 92140 remain, 29.7% used) 38932 .text size: 37908 bytes 37908 .vectors size: 1024 bytes 1024 Used Flash size : 186524 bytes 186524 - .text : 146944 bytes 146944 - .rodata : 39580 bytes 39580 + .text: 146944 bytes 146944 + .rodata: 39580 bytes 39580 Total image size: 234780 bytes (.bin may be padded larger) 234780 Per-file contributions to ELF file: Object File DRAM .data & 0.bss IRAM0 .text & 0.vectors ram_st_total Flash .text & .rodata flash_total @@ -1487,8 +1487,8 @@ Used static IRAM: 38932 bytes ( 92140 remain, 29.7% used) 38956 .text size: 37908 bytes 37929 -21 .vectors size: 1024 bytes 1027 -3 Used Flash size : 186524 bytes 99551 +86973 - .text : 146944 bytes 77191 +69753 - .rodata : 39580 bytes 22360 +17220 + .text: 146944 bytes 77191 +69753 + .rodata: 39580 bytes 22360 +17220 Total image size: 234780 bytes (.bin may be padded larger) 147087 +87693 Per-file contributions to ELF file: Object File DRAM .data & 0.bss IRAM0 .text & 0.vectors ram_st_total Flash .text & .rodata flash_total @@ -1976,8 +1976,8 @@ Used static IRAM: 38956 bytes ( 92116 remain, 29.7% used) 38932 .text size: 37929 bytes 37908 +21 .vectors size: 1027 bytes 1024 +3 Used Flash size : 99551 bytes 186524 -86973 - .text : 77191 bytes 146944 -69753 - .rodata : 22360 bytes 39580 -17220 + .text: 77191 bytes 146944 -69753 + .rodata: 22360 bytes 39580 -17220 Total image size: 147087 bytes (.bin may be padded larger) 234780 -87693 Per-file contributions to ELF file: Object File DRAM .data & 0.bss IRAM0 .text & 0.vectors ram_st_total Flash .text & .rodata flash_total @@ -2466,8 +2466,8 @@ Used static IRAM: 38932 bytes ( 92140 remain, 29.7% used) 18796 .text size: 37908 bytes 18796 +19112 .vectors size: 1024 bytes 0 +1024 Used Flash size : 186524 bytes 0 +186524 - .text : 146944 bytes 0 +146944 - .rodata : 39580 bytes 0 +39580 + .text: 146944 bytes 0 +146944 + .rodata: 39580 bytes 0 +39580 Total image size: 234780 bytes (.bin may be padded larger) 25960 +208820 Symbols within the archive: libdriver.a (Not all symbols may be reported) @@ -2553,8 +2553,8 @@ Used static IRAM: 38932 bytes ( 92140 remain, 29.7% used) 18796 .text size: 37908 bytes 18796 +19112 .vectors size: 1024 bytes 0 +1024 Used Flash size : 186524 bytes 0 +186524 - .text : 146944 bytes 0 +146944 - .rodata : 39580 bytes 0 +39580 + .text: 146944 bytes 0 +146944 + .rodata: 39580 bytes 0 +39580 Total image size: 234780 bytes (.bin may be padded larger) 25960 +208820 Symbols within the archive: libc.a (Not all symbols may be reported) @@ -2618,8 +2618,8 @@ Used static IRAM: 38932 bytes ( 92140 remain, 29.7% used) 38932 .text size: 37908 bytes 37908 .vectors size: 1024 bytes 1024 Used Flash size : 186524 bytes 186524 - .text : 146944 bytes 146944 - .rodata : 39580 bytes 39580 + .text: 146944 bytes 146944 + .rodata: 39580 bytes 39580 Total image size: 234780 bytes (.bin may be padded larger) 234780 Symbols within the archive: libdriver.a (Not all symbols may be reported) @@ -2695,8 +2695,8 @@ Used static IRAM: 38932 bytes ( 92140 remain, 29.7% used) 38956 .text size: 37908 bytes 37929 -21 .vectors size: 1024 bytes 1027 -3 Used Flash size : 186524 bytes 99551 +86973 - .text : 146944 bytes 77191 +69753 - .rodata : 39580 bytes 22360 +17220 + .text: 146944 bytes 77191 +69753 + .rodata: 39580 bytes 22360 +17220 Total image size: 234780 bytes (.bin may be padded larger) 147087 +87693 Symbols within the archive: libdriver.a (Not all symbols may be reported) @@ -2837,8 +2837,8 @@ Used static IRAM: 38956 bytes ( 92116 remain, 29.7% used) 38932 .text size: 37929 bytes 37908 +21 .vectors size: 1027 bytes 1024 +3 Used Flash size : 99551 bytes 186524 -86973 - .text : 77191 bytes 146944 -69753 - .rodata : 22360 bytes 39580 -17220 + .text: 77191 bytes 146944 -69753 + .rodata: 22360 bytes 39580 -17220 Total image size: 147087 bytes (.bin may be padded larger) 234780 -87693 Symbols within the archive: libdriver.a (Not all symbols may be reported) @@ -2979,8 +2979,8 @@ Used static IRAM: 38932 bytes ( 92140 remain, 29.7% used) 38956 .text size: 37908 bytes 37929 -21 .vectors size: 1024 bytes 1027 -3 Used Flash size : 186524 bytes 99551 +86973 - .text : 146944 bytes 77191 +69753 - .rodata : 39580 bytes 22360 +17220 + .text: 146944 bytes 77191 +69753 + .rodata: 39580 bytes 22360 +17220 Total image size: 234780 bytes (.bin may be padded larger) 147087 +87693 Symbols within the archive: libfreertos.a (Not all symbols may be reported) @@ -3276,8 +3276,8 @@ Used stat D/IRAM: 43020 bytes ( 153588 remain, 21.9% used) .text size: 32905 bytes .vectors size: 1027 bytes Used Flash size : 93019 bytes - .text : 74439 bytes - .rodata : 18580 bytes + .text: 74439 bytes + .rodata: 18580 bytes Total image size: 134103 bytes (.bin may be padded larger) *** @@ -3289,8 +3289,8 @@ Used stat D/IRAM: 207299 bytes ( -18883 remain, 110.0% used) Overflow detected! .text size: 171884 bytes .vectors size: 1027 bytes Used Flash size : 519371 bytes - .text : 420899 bytes - .rodata : 98216 bytes + .text: 420899 bytes + .rodata: 98216 bytes Total image size: 708078 bytes (.bin may be padded larger) *** @@ -3302,8 +3302,8 @@ Used stat D/IRAM: 43020 bytes ( 153588 remain, 21.9% used) .text size: 32905 bytes .vectors size: 1027 bytes Used Flash size : 93019 bytes - .text : 74439 bytes - .rodata : 18580 bytes + .text: 74439 bytes + .rodata: 18580 bytes Total image size: 134103 bytes (.bin may be padded larger) *** @@ -3335,8 +3335,8 @@ Used stat D/IRAM: 43020 bytes ( 153588 remain, 21.9% used) .text size: 32905 bytes .vectors size: 1027 bytes Used Flash size : 93019 bytes - .text : 74439 bytes - .rodata : 18580 bytes + .text: 74439 bytes + .rodata: 18580 bytes Total image size: 134103 bytes (.bin may be padded larger) Per-archive contributions to ELF file: Archive File DRAM .data & 0.bss IRAM0 .text & 0.vectors ram_st_total Flash .text & .rodata flash_total @@ -3375,8 +3375,8 @@ Used stat D/IRAM: 43020 bytes ( 153588 remain, 21.9% used) .text size: 32905 bytes .vectors size: 1027 bytes Used Flash size : 93019 bytes - .text : 74439 bytes - .rodata : 18580 bytes + .text: 74439 bytes + .rodata: 18580 bytes Total image size: 134103 bytes (.bin may be padded larger) Per-file contributions to ELF file: Object File DRAM .data & 0.bss IRAM0 .text & 0.vectors ram_st_total Flash .text & .rodata flash_total @@ -3603,84 +3603,84 @@ Used stat D/IRAM: 43020 bytes ( 153588 remain, 21.9% used) .text size: 32905 bytes .vectors size: 1027 bytes Used Flash size : 93019 bytes - .text : 74439 bytes - .rodata : 18580 bytes + .text: 74439 bytes + .rodata: 18580 bytes Total image size: 134103 bytes (.bin may be padded larger) Symbols within the archive: libdriver.a (Not all symbols may be reported) Symbols from section: .dram0.bss - p_timer_obj : 16 - p_uart_obj : 8 - s_rtc_isr_handle : 4 - s_rtc_isr_handler_list : 4 + p_timer_obj : 16 + p_uart_obj : 8 + s_rtc_isr_handle : 4 + s_rtc_isr_handler_list : 4 Section total: 32 Symbols from section: .dram0.data - uart_context : 32 - timer_spinlock : 16 - periph_spinlock : 8 - rtc_spinlock : 8 - s_rtc_isr_handler_list_lock : 8 - uart_selectlock : 8 + uart_context : 32 + timer_spinlock : 16 + periph_spinlock : 8 + rtc_spinlock : 8 + s_rtc_isr_handler_list_lock : 8 + uart_selectlock : 8 Section total: 80 Symbols from section: .flash.rodata - timer_get_counter_value.str1.4 : 146 - get_clk_en_mask : 136 - get_rst_en_mask : 136 - uart_pattern_enqueue.str1.4 : 88 - uart_flush_input.str1.4 : 45 - uart_set_word_length.str1.4 : 31 - __FUNCTION__$7196 : 27 - __FUNCTION__$5699 : 24 - __FUNCTION__$6971 : 23 - __FUNCTION__$6966 : 22 - __FUNCTION__$6896 : 21 - __FUNCTION__$6901 : 21 - __FUNCTION__$6906 : 19 - __FUNCTION__$6911 : 19 - __FUNCTION__$6926 : 18 - __FUNCTION__$6932 : 18 - __FUNCTION__$7131 : 18 - uart_pattern_pop_pos.str1.4 : 18 - __FUNCTION__$7202 : 17 - __FUNCTION__$6916 : 16 - __FUNCTION__$6921 : 16 - uart_set_stop_bits.str1.4 : 15 + timer_get_counter_value.str1.4 : 146 + get_clk_en_mask : 136 + get_rst_en_mask : 136 + uart_pattern_enqueue.str1.4 : 88 + uart_flush_input.str1.4 : 45 + uart_set_word_length.str1.4 : 31 + __FUNCTION__$7196 : 27 + __FUNCTION__$5699 : 24 + __FUNCTION__$6971 : 23 + __FUNCTION__$6966 : 22 + __FUNCTION__$6896 : 21 + __FUNCTION__$6901 : 21 + __FUNCTION__$6906 : 19 + __FUNCTION__$6911 : 19 + __FUNCTION__$6926 : 18 + __FUNCTION__$6932 : 18 + __FUNCTION__$7131 : 18 + uart_pattern_pop_pos.str1.4 : 18 + __FUNCTION__$7202 : 17 + __FUNCTION__$6916 : 16 + __FUNCTION__$6921 : 16 + uart_set_stop_bits.str1.4 : 15 Section total: 894 Symbols from section: .flash.text - uart_flush_input : 453 - uart_wait_tx_done : 417 - get_clk_en_mask : 267 - get_rst_en_mask : 198 - timer_group_intr_enable : 184 - uart_set_word_length : 144 - uart_set_stop_bits : 128 - periph_module_enable : 112 - uart_get_bufferedlen : 109 - uart_enable_intr_mask : 98 - uart_disable_intr_mask : 96 - uart_set_baudrate : 96 - rtc_isr : 90 - uart_get_baudrate : 82 - uart_set_parity : 82 - rtc_isr_ensure_installed : 79 - uart_pattern_queue_update : 74 - uart_get_parity : 69 - uart_get_stop_bits : 69 - uart_get_word_length : 69 - rtc_isr_register : 62 - rtc_gpio_force_hold_dis_all : 53 - is_wifi_clk_peripheral : 38 - uart_is_driver_installed : 30 - get_rst_en_reg : 25 - uart_set_select_notif_callback : 23 - get_clk_en_reg : 21 - uart_disable_rx_intr : 18 - uart_enable_rx_intr : 18 - uart_get_selectlock : 12 + uart_flush_input : 453 + uart_wait_tx_done : 417 + get_clk_en_mask : 267 + get_rst_en_mask : 198 + timer_group_intr_enable : 184 + uart_set_word_length : 144 + uart_set_stop_bits : 128 + periph_module_enable : 112 + uart_get_bufferedlen : 109 + uart_enable_intr_mask : 98 + uart_disable_intr_mask : 96 + uart_set_baudrate : 96 + rtc_isr : 90 + uart_get_baudrate : 82 + uart_set_parity : 82 + rtc_isr_ensure_installed : 79 + uart_pattern_queue_update : 74 + uart_get_parity : 69 + uart_get_stop_bits : 69 + uart_get_word_length : 69 + rtc_isr_register : 62 + rtc_gpio_force_hold_dis_all : 53 + is_wifi_clk_peripheral : 38 + uart_is_driver_installed : 30 + get_rst_en_reg : 25 + uart_set_select_notif_callback : 23 + get_clk_en_reg : 21 + uart_disable_rx_intr : 18 + uart_enable_rx_intr : 18 + uart_get_selectlock : 12 Section total: 3216 Symbols from section: .iram0.text @@ -3723,8 +3723,8 @@ Used stat D/IRAM: 0 bytes ( 0 remain, 0.0% used) 43020 .text size: 0 bytes 32905 -32905 .vectors size: 0 bytes 1027 -1027 Used Flash size : 186524 bytes 93019 +93505 - .text : 146944 bytes 74439 +72505 - .rodata : 39580 bytes 18580 +21000 + .text: 146944 bytes 74439 +72505 + .rodata: 39580 bytes 18580 +21000 Total image size: 234780 bytes (.bin may be padded larger) 134103 +100677 *** @@ -3735,8 +3735,8 @@ Used stat D/IRAM: 45656 bytes ( 282024 remain, 13.9% used) .bss size: 3664 bytes .text size: 37128 bytes Used Flash size : 110492 bytes - .text : 85252 bytes - .rodata : 24984 bytes + .text: 85252 bytes + .rodata: 24984 bytes Total image size: 152484 bytes (.bin may be padded larger) *** @@ -3747,8 +3747,8 @@ Used stat D/IRAM: 45656 bytes ( 282024 remain, 13.9% used) .bss size: 3664 bytes .text size: 37128 bytes Used Flash size : 110492 bytes - .text : 85252 bytes - .rodata : 24984 bytes + .text: 85252 bytes + .rodata: 24984 bytes Total image size: 152484 bytes (.bin may be padded larger) *** @@ -3759,8 +3759,8 @@ Used stat D/IRAM: 45656 bytes ( 282024 remain, 13.9% used) .bss size: 3664 bytes .text size: 37128 bytes Used Flash size : 110492 bytes - .text : 85252 bytes - .rodata : 24984 bytes + .text: 85252 bytes + .rodata: 24984 bytes Total image size: 152484 bytes (.bin may be padded larger) Per-archive contributions to ELF file: Archive File DRAM .data .rtc.data DRAM .bss IRAM0 .text ram_st_total Flash .text & .rodata & .appdesc flash_total @@ -3796,8 +3796,8 @@ Used stat D/IRAM: 45656 bytes ( 282024 remain, 13.9% used) .bss size: 3664 bytes .text size: 37128 bytes Used Flash size : 110492 bytes - .text : 85252 bytes - .rodata : 24984 bytes + .text: 85252 bytes + .rodata: 24984 bytes Total image size: 152484 bytes (.bin may be padded larger) Per-file contributions to ELF file: Object File DRAM .data .rtc.data DRAM .bss IRAM0 .text ram_st_total Flash .text & .rodata & .appdesc flash_total @@ -3955,70 +3955,70 @@ Used stat D/IRAM: 45656 bytes ( 282024 remain, 13.9% used) .bss size: 3664 bytes .text size: 37128 bytes Used Flash size : 110492 bytes - .text : 85252 bytes - .rodata : 24984 bytes + .text: 85252 bytes + .rodata: 24984 bytes Total image size: 152484 bytes (.bin may be padded larger) Symbols within the archive: libdriver.a (Not all symbols may be reported) Symbols from section: .dram0.bss - ref_counts : 27 - .p_uart_obj : 8 + ref_counts : 27 + .p_uart_obj : 8 Section total: 35 Symbols from section: .dram0.data - uart_context : 32 - .uart_selectlock : 8 - ..g_spi_lock_main_flash_dev : 4 + uart_context : 32 + .uart_selectlock : 8 + ..g_spi_lock_main_flash_dev : 4 Section total: 44 Symbols from section: .flash.appdesc Section total: 0 Symbols from section: .flash.rodata - periph_module_enable.str1.4 : 64 - uart_disable_intr_mask_and_return_prev.str1.4 : 54 - uart_pattern_pop_pos.str1.4 : 49 - uart_set_stop_bits.str1.4 : 46 - uart_set_word_length.str1.4 : 46 - uart_flush_input.str1.4 : 45 - __FUNCTION__.7485 : 39 - __FUNCTION__.7477 : 27 - __FUNCTION__.7240 : 22 - __FUNCTION__.7171 : 21 - __FUNCTION__.7176 : 21 - __func__.4215 : 21 - __FUNCTION__.7181 : 19 - __FUNCTION__.7186 : 19 - __FUNCTION__.7201 : 18 - __FUNCTION__.7206 : 18 - __FUNCTION__.7412 : 18 - __FUNCTION__.7489 : 17 - __FUNCTION__.7191 : 16 - __FUNCTION__.7196 : 16 + periph_module_enable.str1.4 : 64 + uart_disable_intr_mask_and_return_prev.str1.4 : 54 + uart_pattern_pop_pos.str1.4 : 49 + uart_set_stop_bits.str1.4 : 46 + uart_set_word_length.str1.4 : 46 + uart_flush_input.str1.4 : 45 + __FUNCTION__.7485 : 39 + __FUNCTION__.7477 : 27 + __FUNCTION__.7240 : 22 + __FUNCTION__.7171 : 21 + __FUNCTION__.7176 : 21 + __func__.4215 : 21 + __FUNCTION__.7181 : 19 + __FUNCTION__.7186 : 19 + __FUNCTION__.7201 : 18 + __FUNCTION__.7206 : 18 + __FUNCTION__.7412 : 18 + __FUNCTION__.7489 : 17 + __FUNCTION__.7191 : 16 + __FUNCTION__.7196 : 16 Section total: 596 Symbols from section: .flash.text - periph_module_enable : 682 - uart_flush_input : 580 - uart_wait_tx_done : 484 - uart_set_stop_bits : 178 - uart_set_word_length : 178 - uart_get_bufferedlen : 152 - uart_disable_intr_mask_and_return_prev : 138 - uart_enable_intr_mask : 122 - uart_get_baudrate : 116 - uart_set_baudrate : 116 - uart_set_parity : 116 - uart_get_parity : 86 - uart_get_stop_bits : 86 - uart_get_word_length : 86 - uart_pattern_queue_update : 80 - uart_is_driver_installed : 34 - uart_set_select_notif_callback : 30 - periph_ll_get_clk_en_reg : 28 - periph_ll_get_rst_en_reg : 28 - uart_get_selectlock : 6 + periph_module_enable : 682 + uart_flush_input : 580 + uart_wait_tx_done : 484 + uart_set_stop_bits : 178 + uart_set_word_length : 178 + uart_get_bufferedlen : 152 + uart_disable_intr_mask_and_return_prev : 138 + uart_enable_intr_mask : 122 + uart_get_baudrate : 116 + uart_set_baudrate : 116 + uart_set_parity : 116 + uart_get_parity : 86 + uart_get_stop_bits : 86 + uart_get_word_length : 86 + uart_pattern_queue_update : 80 + uart_is_driver_installed : 34 + uart_set_select_notif_callback : 30 + periph_ll_get_clk_en_reg : 28 + periph_ll_get_rst_en_reg : 28 + uart_get_selectlock : 6 Section total: 3326 Symbols from section: .iram0.bss @@ -4053,8 +4053,8 @@ Used stat D/IRAM: 48466 bytes ( 279214 remain, 14.8% used) .bss size: 3664 bytes .text size: 39754 bytes Used Flash size : 117008 bytes - .text : 90400 bytes - .rodata : 26352 bytes + .text: 90400 bytes + .rodata: 26352 bytes Total image size: 161810 bytes (.bin may be padded larger) *** @@ -4067,8 +4067,8 @@ Total sizes: Used stat D/IRAM: 551174 bytes (-223494 remain, 168.2% used) Overflow detected! You can run idf.py size-files for more information. .text size: 551174 bytes Used Flash size : 494592 bytes - .text : 410978 bytes - .rodata : 83358 bytes + .text: 410978 bytes + .rodata: 83358 bytes Total image size: 1045766 bytes (.bin may be padded larger) *** @@ -4079,8 +4079,8 @@ Used stat D/IRAM: 48466 bytes ( 279214 remain, 14.8% used) .bss size: 3664 bytes .text size: 39754 bytes Used Flash size : 117008 bytes - .text : 90400 bytes - .rodata : 26352 bytes + .text: 90400 bytes + .rodata: 26352 bytes Total image size: 161810 bytes (.bin may be padded larger) *** @@ -4091,8 +4091,8 @@ Used stat D/IRAM: 48466 bytes ( 279214 remain, 14.8% used) .bss size: 3664 bytes .text size: 39754 bytes Used Flash size : 117008 bytes - .text : 90400 bytes - .rodata : 26352 bytes + .text: 90400 bytes + .rodata: 26352 bytes Total image size: 161810 bytes (.bin may be padded larger) Per-archive contributions to ELF file: Archive File DRAM .data .rtc.data DRAM .bss IRAM0 .text ram_st_total Flash .text & .rodata & .appdesc flash_total @@ -4130,8 +4130,8 @@ Used stat D/IRAM: 48466 bytes ( 279214 remain, 14.8% used) .bss size: 3664 bytes .text size: 39754 bytes Used Flash size : 117008 bytes - .text : 90400 bytes - .rodata : 26352 bytes + .text: 90400 bytes + .rodata: 26352 bytes Total image size: 161810 bytes (.bin may be padded larger) Per-file contributions to ELF file: Object File DRAM .data .rtc.data DRAM .bss IRAM0 .text ram_st_total Flash .text & .rodata & .appdesc flash_total @@ -4295,100 +4295,100 @@ Used stat D/IRAM: 48466 bytes ( 279214 remain, 14.8% used) .bss size: 3664 bytes .text size: 39754 bytes Used Flash size : 117008 bytes - .text : 90400 bytes - .rodata : 26352 bytes + .text: 90400 bytes + .rodata: 26352 bytes Total image size: 161810 bytes (.bin may be padded larger) Symbols within the archive: libdriver.a (Not all symbols may be reported) Symbols from section: .dram0.bss - ref_counts : 27 - .p_uart_obj : 8 + ref_counts : 27 + .p_uart_obj : 8 Section total: 35 Symbols from section: .dram0.data - uart_context : 32 - .uart_selectlock : 8 - ..g_spi_lock_main_flash_dev : 4 + uart_context : 32 + .uart_selectlock : 8 + ..g_spi_lock_main_flash_dev : 4 Section total: 44 Symbols from section: .flash.appdesc Section total: 0 Symbols from section: .flash.rodata - gpio_set_pull_mode.str1.4 : 93 - periph_module_enable.str1.4 : 64 - gpio_input_enable.str1.4 : 62 - uart_disable_intr_mask_and_return_prev.str1.4 : 54 - uart_pattern_pop_pos.str1.4 : 49 - uart_set_stop_bits.str1.4 : 46 - uart_set_word_length.str1.4 : 46 - uart_flush_input.str1.4 : 45 - __FUNCTION__.7467 : 39 - __FUNCTION__.7459 : 27 - gpio_sleep_output_enable.str1.4 : 27 - __FUNCTION__.6231 : 26 - __FUNCTION__.6223 : 25 - __FUNCTION__.6235 : 25 - __FUNCTION__.6240 : 25 - __FUNCTION__.6246 : 25 - __FUNCTION__.6219 : 24 - __FUNCTION__.6227 : 24 - __FUNCTION__.6215 : 23 - __FUNCTION__.6211 : 22 - __FUNCTION__.7222 : 22 - __FUNCTION__.6207 : 21 - __FUNCTION__.7153 : 21 - __FUNCTION__.7158 : 21 - __func__.4238 : 21 - __FUNCTION__.6261 : 19 - __FUNCTION__.7163 : 19 - __FUNCTION__.7168 : 19 - __FUNCTION__.6257 : 18 - __FUNCTION__.7183 : 18 - __FUNCTION__.7188 : 18 - __FUNCTION__.7394 : 18 - __FUNCTION__.7471 : 17 - __FUNCTION__.7173 : 16 - __FUNCTION__.7178 : 16 + gpio_set_pull_mode.str1.4 : 93 + periph_module_enable.str1.4 : 64 + gpio_input_enable.str1.4 : 62 + uart_disable_intr_mask_and_return_prev.str1.4 : 54 + uart_pattern_pop_pos.str1.4 : 49 + uart_set_stop_bits.str1.4 : 46 + uart_set_word_length.str1.4 : 46 + uart_flush_input.str1.4 : 45 + __FUNCTION__.7467 : 39 + __FUNCTION__.7459 : 27 + gpio_sleep_output_enable.str1.4 : 27 + __FUNCTION__.6231 : 26 + __FUNCTION__.6223 : 25 + __FUNCTION__.6235 : 25 + __FUNCTION__.6240 : 25 + __FUNCTION__.6246 : 25 + __FUNCTION__.6219 : 24 + __FUNCTION__.6227 : 24 + __FUNCTION__.6215 : 23 + __FUNCTION__.6211 : 22 + __FUNCTION__.7222 : 22 + __FUNCTION__.6207 : 21 + __FUNCTION__.7153 : 21 + __FUNCTION__.7158 : 21 + __func__.4238 : 21 + __FUNCTION__.6261 : 19 + __FUNCTION__.7163 : 19 + __FUNCTION__.7168 : 19 + __FUNCTION__.6257 : 18 + __FUNCTION__.7183 : 18 + __FUNCTION__.7188 : 18 + __FUNCTION__.7394 : 18 + __FUNCTION__.7471 : 17 + __FUNCTION__.7173 : 16 + __FUNCTION__.7178 : 16 Section total: 1055 Symbols from section: .flash.rodata_noload Section total: 0 Symbols from section: .flash.text - periph_module_enable : 736 - uart_flush_input : 580 - uart_wait_tx_done : 484 - gpio_sleep_set_pull_mode : 318 - uart_set_stop_bits : 178 - uart_set_word_length : 178 - gpio_sleep_set_direction : 156 - uart_get_bufferedlen : 152 - gpio_sleep_pulldown_en : 148 - gpio_sleep_pullup_en : 148 - gpio_sleep_sel_en : 148 - gpio_sleep_pulldown_dis : 146 - gpio_sleep_pullup_dis : 146 - gpio_sleep_sel_dis : 146 - uart_disable_intr_mask_and_return_prev : 138 - gpio_sleep_input_enable : 126 - gpio_sleep_output_enable : 126 - gpio_sleep_input_disable : 124 - gpio_sleep_output_disable : 124 - uart_enable_intr_mask : 122 - uart_get_baudrate : 116 - uart_set_baudrate : 116 - uart_set_parity : 116 - uart_get_parity : 86 - uart_get_stop_bits : 86 - uart_get_word_length : 86 - uart_pattern_queue_update : 80 - periph_ll_get_clk_en_reg : 50 - periph_ll_get_rst_en_reg : 50 - uart_is_driver_installed : 34 - uart_set_select_notif_callback : 30 - uart_get_selectlock : 6 + periph_module_enable : 736 + uart_flush_input : 580 + uart_wait_tx_done : 484 + gpio_sleep_set_pull_mode : 318 + uart_set_stop_bits : 178 + uart_set_word_length : 178 + gpio_sleep_set_direction : 156 + uart_get_bufferedlen : 152 + gpio_sleep_pulldown_en : 148 + gpio_sleep_pullup_en : 148 + gpio_sleep_sel_en : 148 + gpio_sleep_pulldown_dis : 146 + gpio_sleep_pullup_dis : 146 + gpio_sleep_sel_dis : 146 + uart_disable_intr_mask_and_return_prev : 138 + gpio_sleep_input_enable : 126 + gpio_sleep_output_enable : 126 + gpio_sleep_input_disable : 124 + gpio_sleep_output_disable : 124 + uart_enable_intr_mask : 122 + uart_get_baudrate : 116 + uart_set_baudrate : 116 + uart_set_parity : 116 + uart_get_parity : 86 + uart_get_stop_bits : 86 + uart_get_word_length : 86 + uart_pattern_queue_update : 80 + periph_ll_get_clk_en_reg : 50 + periph_ll_get_rst_en_reg : 50 + uart_is_driver_installed : 34 + uart_set_select_notif_callback : 30 + uart_get_selectlock : 6 Section total: 5280 Symbols from section: .iram0.bss @@ -4425,8 +4425,8 @@ Used stat D/IRAM: 11772 bytes ( 123396 remain, 8.7% used) .data size: 9252 bytes .bss size: 2520 bytes Used Flash size : 114851 bytes - .text : 87463 bytes - .rodata : 27132 bytes + .text: 87463 bytes + .rodata: 27132 bytes Total image size: 170889 bytes (.bin may be padded larger) *** @@ -4439,8 +4439,8 @@ Used stat D/IRAM: 94049 bytes ( 41119 remain, 69.6% used) .data size: 68929 bytes .bss size: 25120 bytes Used Flash size : 461714 bytes - .text : 366715 bytes - .rodata : 94743 bytes + .text: 366715 bytes + .rodata: 94743 bytes Total image size: 868549 bytes (.bin may be padded larger) *** @@ -4453,8 +4453,8 @@ Used stat D/IRAM: 11772 bytes ( 123396 remain, 8.7% used) .data size: 9252 bytes .bss size: 2520 bytes Used Flash size : 114851 bytes - .text : 87463 bytes - .rodata : 27132 bytes + .text: 87463 bytes + .rodata: 27132 bytes Total image size: 170889 bytes (.bin may be padded larger) *** @@ -4467,8 +4467,8 @@ Used stat D/IRAM: 11772 bytes ( 123396 remain, 8.7% used) .data size: 9252 bytes .bss size: 2520 bytes Used Flash size : 114851 bytes - .text : 87463 bytes - .rodata : 27132 bytes + .text: 87463 bytes + .rodata: 27132 bytes Total image size: 170889 bytes (.bin may be padded larger) Per-archive contributions to ELF file: Archive File DRAM .data .rtc.data DRAM .bss IRAM0 .text & 0.vectors ram_st_total Flash .text & .rodata & .appdesc flash_total @@ -4511,8 +4511,8 @@ Used stat D/IRAM: 11772 bytes ( 123396 remain, 8.7% used) .data size: 9252 bytes .bss size: 2520 bytes Used Flash size : 114851 bytes - .text : 87463 bytes - .rodata : 27132 bytes + .text: 87463 bytes + .rodata: 27132 bytes Total image size: 170889 bytes (.bin may be padded larger) Per-file contributions to ELF file: Object File DRAM .data .rtc.data DRAM .bss IRAM0 .text & 0.vectors ram_st_total Flash .text & .rodata & .appdesc flash_total @@ -4777,74 +4777,74 @@ Used stat D/IRAM: 11772 bytes ( 123396 remain, 8.7% used) .data size: 9252 bytes .bss size: 2520 bytes Used Flash size : 114851 bytes - .text : 87463 bytes - .rodata : 27132 bytes + .text: 87463 bytes + .rodata: 27132 bytes Total image size: 170889 bytes (.bin may be padded larger) Symbols within the archive: libdriver.a (Not all symbols may be reported) Symbols from section: .dram0.bss - ref_counts : 37 - p_uart_obj : 12 + ref_counts : 37 + p_uart_obj : 12 Section total: 49 Symbols from section: .dram0.data - uart_context : 48 - periph_spinlock : 8 - uart_selectlock : 8 + uart_context : 48 + periph_spinlock : 8 + uart_selectlock : 8 Section total: 64 Symbols from section: .flash.appdesc Section total: 0 Symbols from section: .flash.rodata - periph_module_enable.str1.4 : 64 - uart_disable_intr_mask_and_return_prev.str1.4 : 54 - uart_pattern_pop_pos.str1.4 : 49 - uart_set_stop_bits.str1.4 : 46 - uart_set_word_length.str1.4 : 46 - uart_flush_input.str1.4 : 45 - __FUNCTION__$8051 : 39 - __FUNCTION__$8043 : 27 - __FUNCTION__$7806 : 22 - __FUNCTION__$7737 : 21 - __FUNCTION__$7742 : 21 - __func__$4997 : 21 - __FUNCTION__$7747 : 19 - __FUNCTION__$7752 : 19 - __FUNCTION__$7767 : 18 - __FUNCTION__$7772 : 18 - __FUNCTION__$7978 : 18 - __FUNCTION__$8055 : 17 - __FUNCTION__$7757 : 16 - __FUNCTION__$7762 : 16 - g_spi_lock_main_flash_dev : 4 + periph_module_enable.str1.4 : 64 + uart_disable_intr_mask_and_return_prev.str1.4 : 54 + uart_pattern_pop_pos.str1.4 : 49 + uart_set_stop_bits.str1.4 : 46 + uart_set_word_length.str1.4 : 46 + uart_flush_input.str1.4 : 45 + __FUNCTION__$8051 : 39 + __FUNCTION__$8043 : 27 + __FUNCTION__$7806 : 22 + __FUNCTION__$7737 : 21 + __FUNCTION__$7742 : 21 + __func__$4997 : 21 + __FUNCTION__$7747 : 19 + __FUNCTION__$7752 : 19 + __FUNCTION__$7767 : 18 + __FUNCTION__$7772 : 18 + __FUNCTION__$7978 : 18 + __FUNCTION__$8055 : 17 + __FUNCTION__$7757 : 16 + __FUNCTION__$7762 : 16 + g_spi_lock_main_flash_dev : 4 Section total: 600 Symbols from section: .flash.rodata_noload Section total: 0 Symbols from section: .flash.text - periph_module_enable : 1131 - uart_flush_input : 509 - uart_wait_tx_done : 393 - uart_set_stop_bits : 130 - uart_set_word_length : 130 - periph_ll_get_rst_en_reg : 125 - uart_disable_intr_mask_and_return_prev : 122 - periph_ll_get_clk_en_reg : 121 - uart_get_bufferedlen : 108 - uart_enable_intr_mask : 100 - uart_get_baudrate : 88 - uart_set_parity : 88 - uart_set_baudrate : 84 - uart_pattern_queue_update : 74 - uart_get_parity : 68 - uart_get_stop_bits : 68 - uart_get_word_length : 64 - uart_is_driver_installed : 30 - uart_set_select_notif_callback : 23 - uart_get_selectlock : 12 + periph_module_enable : 1131 + uart_flush_input : 509 + uart_wait_tx_done : 393 + uart_set_stop_bits : 130 + uart_set_word_length : 130 + periph_ll_get_rst_en_reg : 125 + uart_disable_intr_mask_and_return_prev : 122 + periph_ll_get_clk_en_reg : 121 + uart_get_bufferedlen : 108 + uart_enable_intr_mask : 100 + uart_get_baudrate : 88 + uart_set_parity : 88 + uart_set_baudrate : 84 + uart_pattern_queue_update : 74 + uart_get_parity : 68 + uart_get_stop_bits : 68 + uart_get_word_length : 64 + uart_is_driver_installed : 30 + uart_set_select_notif_callback : 23 + uart_get_selectlock : 12 Section total: 3468 Symbols from section: .iram0.bss @@ -18187,12 +18187,2578 @@ Producing JSON output for esp32s3... ".rtc_noinit": {} } +*** +Producing CSV output... +Total sizes:,,, +Used static DRAM,17620 bytes (163116 remain 9.7% used),,, +.data size,9324 bytes,,, +.bss size,8296 bytes,,, +Used static IRAM,38932 bytes (92140 remain 29.7% used),,, +.text size,37908 bytes,,, +.vectors size,1024 bytes,,, +Used Flash size ,186524 bytes,,, +.text,146944 bytes,,, +.rodata,39580 bytes,,, +Total image size,234780 bytes (.bin may be padded larger),,, +Total sizes:,,, +Used static DRAM,17620 bytes (163116 remain 9.7% used),,, +.data size,9324 bytes,,, +.bss size,8296 bytes,,, +Used static IRAM,38932 bytes (92140 remain 29.7% used),,, +.text size,37908 bytes,,, +.vectors size,1024 bytes,,, +Used Flash size ,186524 bytes,,, +.text,146944 bytes,,, +.rodata,39580 bytes,,, +Total image size,234780 bytes (.bin may be padded larger),,, +Per-archive contributions to ELF file: +Archive File,DRAM .data,& 0.bss,IRAM0 .text,& 0.vectors,ram_st_total,Flash .text,& .rodata +liblwip.a,14,3751,0,0,3765,66978,13936 +libc.a,0,0,0,0,0,55583,3709 +libesp32.a,2635,2375,7758,0,12768,4814,8133 +libfreertos.a,4156,832,12428,425,17841,0,1545 +libspi_flash.a,36,359,7004,0,7399,886,1624 +libsoc.a,660,8,3887,0,4555,0,3456 +libheap.a,1331,4,4376,0,5711,1218,980 +libgcc.a,4,20,104,0,128,5488,888 +libvfs.a,232,103,0,0,335,3770,403 +libunity.a,0,121,0,0,121,2316,830 +libstdc++.a,8,16,0,0,24,1827,1062 +libnewlib.a,152,272,853,0,1277,803,86 +libpthread.a,16,12,174,0,202,774,638 +libdriver.a,40,20,0,0,60,961,537 +liblog.a,8,268,456,0,732,396,166 +libapp_update.a,0,0,0,0,0,123,717 +libhal.a,0,0,515,0,515,0,32 +libtcpip_adapter.a,0,81,0,0,81,180,359 +libm.a,0,0,92,0,92,0,0 +libmain.a,0,0,0,0,0,53,10 +libcxx.a,0,0,0,0,0,11,0 +libxtensa-debug-module.a,0,0,8,0,8,0,0 +libbootloader_support.a,0,0,0,0,0,0,0 +libcoexist.a,0,0,0,0,0,0,0 +libcore.a,0,0,0,0,0,0,0 +libethernet.a,0,0,0,0,0,0,0 +libmbedtls.a,0,0,0,0,0,0,0 +libmesh.a,0,0,0,0,0,0,0 +libnet80211.a,0,0,0,0,0,0,0 +libnvs_flash.a,0,0,0,0,0,0,0 +libphy.a,0,0,0,0,0,0,0 +libpp.a,0,0,0,0,0,0,0 +librtc.a,0,0,0,0,0,0,0 +libsmartconfig_ack.a,0,0,0,0,0,0,0 +libwpa.a,0,0,0,0,0,0,0 +libwpa2.a,0,0,0,0,0,0,0 +libwpa_supplicant.a,0,0,0,0,0,0,0 +libwps.a,0,0,0,0,0,0,0 +Total sizes:,,, +Used static DRAM,17620 bytes (163116 remain 9.7% used),,, +.data size,9324 bytes,,, +.bss size,8296 bytes,,, +Used static IRAM,38932 bytes (92140 remain 29.7% used),,, +.text size,37908 bytes,,, +.vectors size,1024 bytes,,, +Used Flash size ,186524 bytes,,, +.text,146944 bytes,,, +.rodata,39580 bytes,,, +Total image size,234780 bytes (.bin may be padded larger),,, +Per-file contributions to ELF file: +Object File,DRAM .data,& 0.bss,IRAM0 .text,& 0.vectors,ram_st_total,Flash .text,& .rodata +lib_a-vfprintf.o,0,0,0,0,0,14193,704 +lib_a-svfprintf.o,0,0,0,0,0,13834,756 +lib_a-svfiprintf.o,0,0,0,0,0,9642,1176 +lib_a-vfiprintf.o,0,0,0,0,0,9933,704 +tcp_in.o,0,54,0,0,54,8127,916 +nd6.o,8,1027,0,0,1035,8427,136 +tasks.o,20,700,5667,0,6387,0,503 +tcp_out.o,0,0,0,0,0,5060,1124 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+ieee80211_rfid.o,0,0,0,0,0,0,0 +ieee80211_scan.o,0,0,0,0,0,0,0 +ieee80211_sta.o,0,0,0,0,0,0,0 +ieee80211_timer.o,0,0,0,0,0,0,0 +wl_chm.o,0,0,0,0,0,0,0 +wl_cnx.o,0,0,0,0,0,0,0 +nvs_api.o,0,0,0,0,0,0,0 +nvs_item_hash_list.o,0,0,0,0,0,0,0 +nvs_page.o,0,0,0,0,0,0,0 +nvs_pagemanager.o,0,0,0,0,0,0,0 +nvs_storage.o,0,0,0,0,0,0,0 +nvs_types.o,0,0,0,0,0,0,0 +phy.o,0,0,0,0,0,0,0 +phy_chip_v7.o,0,0,0,0,0,0,0 +phy_chip_v7_ana.o,0,0,0,0,0,0,0 +phy_chip_v7_cal.o,0,0,0,0,0,0,0 +esf_buf.o,0,0,0,0,0,0,0 +if_hwctrl.o,0,0,0,0,0,0,0 +lmac.o,0,0,0,0,0,0,0 +pm.o,0,0,0,0,0,0,0 +pm_for_bcn_only_mode.o,0,0,0,0,0,0,0 +pp.o,0,0,0,0,0,0,0 +pp_debug.o,0,0,0,0,0,0,0 +pp_timer.o,0,0,0,0,0,0,0 +rate_control.o,0,0,0,0,0,0,0 +trc.o,0,0,0,0,0,0,0 +wdev.o,0,0,0,0,0,0,0 +bt_bb.o,0,0,0,0,0,0,0 +pm.o,0,0,0,0,0,0,0 +rtc.o,0,0,0,0,0,0,0 +rtc_analog.o,0,0,0,0,0,0,0 +smartconfig_ack.o,0,0,0,0,0,0,0 +gpio_periph.o,0,0,0,0,0,0,0 +rtc_sleep.o,0,0,0,0,0,0,0 +bad_alloc.o,0,0,0,0,0,0,0 +del_op.o,0,0,0,0,0,0,0 +del_opv.o,0,0,0,0,0,0,0 +eh_exception.o,0,0,0,0,0,0,0 +new_handler.o,0,0,0,0,0,0,0 +pure.o,0,0,0,0,0,0,0 +tinfo.o,0,0,0,0,0,0,0 +ap_config.o,0,0,0,0,0,0,0 +common.o,0,0,0,0,0,0,0 +wpa.o,0,0,0,0,0,0,0 +wpa_auth.o,0,0,0,0,0,0,0 +wpa_auth_ie.o,0,0,0,0,0,0,0 +wpa_common.o,0,0,0,0,0,0,0 +wpa_debug.o,0,0,0,0,0,0,0 +wpa_ie.o,0,0,0,0,0,0,0 +wpa_main.o,0,0,0,0,0,0,0 +wpabuf.o,0,0,0,0,0,0,0 +wpas_glue.o,0,0,0,0,0,0,0 +wpa2_internal.o,0,0,0,0,0,0,0 +os_xtensa.o,0,0,0,0,0,0,0 +wps_internal.o,0,0,0,0,0,0,0 +Total sizes:,,, +Used static DRAM,17620 bytes (163116 remain 9.7% used),,, +.data size,9324 bytes,,, +.bss size,8296 bytes,,, +Used static IRAM,38932 bytes (92140 remain 29.7% used),,, +.text size,37908 bytes,,, +.vectors size,1024 bytes,,, +Used Flash size ,186524 bytes,,, +.text,146944 bytes,,, +.rodata,39580 bytes,,, +Total image size,234780 bytes (.bin may be padded larger),,, + +Symbols within the archive: libdriver.a (Not all symbols may be reported) + +Symbols from section: .dram0.bss +p_uart_obj,12 +s_rtc_isr_handle,4 +s_rtc_isr_handler_list,4 +Section total: 20 + +Symbols from section: .dram0.data +timer_spinlock,16 +periph_spinlock,8 +s_rtc_isr_handler_list_lock,8 +uart_selectlock,8 +Section total: 40 + +Symbols from section: .flash.rodata +str1.4,249 +get_clk_en_mask,128 +get_rst_en_mask,128 +__FUNCTION__$5441,24 +TG,8 +Section total: 537 + +Symbols from section: .flash.text +get_clk_en_mask,211 +get_rst_en_mask,157 +timer_group_intr_enable,112 +rtc_isr,86 +periph_module_enable,78 +rtc_isr_ensure_installed,75 +rtc_gpio_force_hold_dis_all,65 +rtc_isr_register,65 +is_wifi_clk_peripheral,28 +uart_set_select_notif_callback,26 +get_rst_en_reg,25 +get_clk_en_reg,21 +uart_get_selectlock,12 +Section total: 961 + +Symbols from section: .iram0.text +Section total: 0 + +Symbols from section: .iram0.vectors +Section total: 0 + +Symbols from section: .noinit +Section total: 0 + +Symbols from section: .rtc.bss +Section total: 0 + +Symbols from section: .rtc.data +Section total: 0 + +Symbols from section: .rtc.text +Section total: 0 + +Symbols from section: .rtc_noinit +Section total: 0 +,:,,Difference +File,app.map,app2.map, - +Used static DRAM,17620 bytes (163116 remain 9.7% used),10604,+7016,-7016 remain,0 total +.data size,9324 bytes,8580,+744, +.bss size,8296 bytes,2024,+6272, +Used static IRAM,38932 bytes (92140 remain 29.7% used),38956,-24,24 remain,0 total +.text size,37908 bytes,37929,-21, +.vectors size,1024 bytes,1027,-3, +Used Flash size ,186524 bytes,99551,+86973, +.text,146944 bytes,77191,+69753, +.rodata,39580 bytes,22360,+17220, +Total image size,234780 bytes (.bin may be padded larger),147087,+87693, +,:,,Difference +File,app.map,app2.map, - +Used static DRAM,17620 bytes (163116 remain 9.7% used),10604,+7016,-7016 remain,0 total +.data size,9324 bytes,8580,+744, +.bss size,8296 bytes,2024,+6272, +Used static IRAM,38932 bytes (92140 remain 29.7% used),38956,-24,24 remain,0 total +.text size,37908 bytes,37929,-21, +.vectors size,1024 bytes,1027,-3, +Used Flash size ,186524 bytes,99551,+86973, +.text,146944 bytes,77191,+69753, +.rodata,39580 bytes,22360,+17220, +Total image size,234780 bytes (.bin may be padded larger),147087,+87693, +Per-archive contributions to ELF file: +Archive File,DRAM .data,& 0.bss,IRAM0 .text,& 0.vectors,ram_st_total,Flash .text,& .rodata,flash_total +,,,-,,,-,, +libc.a,,364,-364,,,,, +libesp32.a,2635,2118,+517,2375,81,+2294,7758,5462 +libfreertos.a,4156,4140,+16,832,792,+40,12428,12459 +libspi_flash.a,36,779,-743,359,294,+65,7004,4896 +libsoc.a,660,208,+452,8,4,+4,3887,6790 +libheap.a,1331,304,+1027,4,4,,4376,3129 +libgcc.a,4,,+4,20,,+20,104, +libvfs.a,232,308,-76,103,48,+55,, +libnewlib.a,152,152,,272,272,,853,820 +libpthread.a,16,8,+8,12,12,,174, +libdriver.a,40,112,-72,20,20,,, +liblog.a,8,8,,268,272,-4,456,222 +libapp_update.a,,,,,4,-4,,109 +libhal.a,,,,,,,515,447 +libmain.a,,,,,,,, +libcxx.a,,,,,,,, +libbootloader_support.a,,,,,,,,1028 +libwpa_supplicant.a,,,,,,,, +The following entries are present in only: +Archive File,DRAM .data,& 0.bss,IRAM0 .text,& 0.vectors,ram_st_total,Flash .text,& .rodata +liblwip.a,14,3751,0,0,3765,66978,13936 +libunity.a,0,121,0,0,121,2316,830 +libstdc++.a,8,16,0,0,24,1827,1062 +libtcpip_adapter.a,0,81,0,0,81,180,359 +libm.a,0,0,92,0,92,0,0 +libxtensa-debug-module.a,0,0,8,0,8,0,0 +libcoexist.a,0,0,0,0,0,0,0 +libcore.a,0,0,0,0,0,0,0 +libethernet.a,0,0,0,0,0,0,0 +libmbedtls.a,0,0,0,0,0,0,0 +libmesh.a,0,0,0,0,0,0,0 +libnet80211.a,0,0,0,0,0,0,0 +libnvs_flash.a,0,0,0,0,0,0,0 +libphy.a,0,0,0,0,0,0,0 +libpp.a,0,0,0,0,0,0,0 +librtc.a,0,0,0,0,0,0,0 +libsmartconfig_ack.a,0,0,0,0,0,0,0 +libwpa.a,0,0,0,0,0,0,0 +libwpa2.a,0,0,0,0,0,0,0 +libwps.a,0,0,0,0,0,0,0 +The following entries are present in only: +Archive File,DRAM .data,& 0.bss,IRAM0 .text,& 0.vectors,ram_st_total,Flash .text,& .rodata +libesp_common.a,8,184,239,0,431,783,5421 +libesp_timer.a,16,20,794,0,830,723,493 +libesp_ringbuf.a,0,0,858,0,858,0,150 +libxtensa.a,0,0,217,0,217,0,0 +libsoc_esp32.a,0,0,0,0,0,0,160 +(exe),0,0,0,3,3,3,12 +libefuse.a,0,0,0,0,0,0,0 +libmbedcrypto.a,0,0,0,0,0,0,0 +,:,,Difference +File,app.map,app2.map, - +Used static DRAM,17620 bytes (163116 remain 9.7% used),10604,+7016,-7016 remain,0 total +.data size,9324 bytes,8580,+744, +.bss size,8296 bytes,2024,+6272, +Used static IRAM,38932 bytes (92140 remain 29.7% used),38956,-24,24 remain,0 total +.text size,37908 bytes,37929,-21, +.vectors size,1024 bytes,1027,-3, +Used Flash size ,186524 bytes,99551,+86973, +.text,146944 bytes,77191,+69753, +.rodata,39580 bytes,22360,+17220, +Total image size,234780 bytes (.bin may be padded larger),147087,+87693, +Per-file contributions to ELF file: +Object File,DRAM .data,& 0.bss,IRAM0 .text,& 0.vectors,ram_st_total,Flash .text,& .rodata,flash_total +,,,-,,,-,, +lib_a-vfprintf.o,,,,,,,, +lib_a-svfprintf.o,,,,,,,, +lib_a-svfiprintf.o,,,,,,,, +lib_a-vfiprintf.o,,,,,,,, +lib_a-dtoa.o,,,,,,,, +lib_a-mprec.o,,,,,,,, +lib_a-fseeko.o,,,,,,,, +windowspill_asm.o,,,,,,,311,315 +lib_a-reent.o,,,,,,,, +lib_a-fopen.o,,,,,,,, +lib_a-puts.o,,,,,,,, +lib_a-assert.o,,,,,,,, +lib_a-flags.o,,,,,,,, +lib_a-printf.o,,,,,,,, +lib_a-s_frexp.o,,,,,,,, +lib_a-vprintf.o,,,,,,,, +lib_a-fiprintf.o,,,,,,,, +state_asm--restore_extra,,,,,,,62,62 +state_asm--save_extra_nw,,,,,,,62,62 +lib_a-fseek.o,,,,,,,, +_divdi3.o,,,,,,,, +_moddi3.o,,,,,,,, +_udivdi3.o,,,,,,,, +_umoddi3.o,,,,,,,, +interrupts--intlevel.o,,,,,,,, +lib_a-errno.o,,,,,,,, +int_asm--set_intclear.o,,,,,,,8,8 +lib_a-fputs.o,,,,,,,, +lib_a-snprintf.o,,,,,,,, +lib_a-strerror.o,,,,,,,, +lib_a-sysgettod.o,,,,,,,, +lib_a-u_strerr.o,,,,,,,, +_addsubdf3.o,,,,,,,, +_cmpdf2.o,,,,,,,, +_divdf3.o,,,,,,,, +_fixdfsi.o,,,,,,,, +_floatsidf.o,,,,,,,, +_muldf3.o,,,,,,,, +_popcountsi2.o,,,,,,,, +The following entries are present in only: +Object File,DRAM .data,& 0.bss,IRAM0 .text,& 0.vectors,ram_st_total,Flash .text,& .rodata +tcp_in.o,0,54,0,0,54,8127,916 +nd6.o,8,1027,0,0,1035,8427,136 +tasks.o,20,700,5667,0,6387,0,503 +tcp_out.o,0,0,0,0,0,5060,1124 +tcp.o,4,23,0,0,27,4290,1384 +sockets.o,0,728,0,0,728,4627,824 +api_msg.o,0,0,0,0,0,3763,1366 +dhcp.o,0,8,0,0,8,3456,1401 +panic.o,2579,5,2145,0,4729,0,0 +esp_err_to_name.o,0,0,0,0,0,50,4091 +unwind-dw2-fde.o,4,20,0,0,24,3316,404 +pbuf.o,0,1,0,0,1,2453,1161 +portasm.o,3084,0,480,0,3564,0,0 +ip6.o,0,0,0,0,0,3212,124 +spi_flash_rom_patch.o,0,0,2518,0,2518,0,766 +etharp.o,0,241,0,0,241,2618,658 +udp.o,2,4,0,0,6,3020,216 +intr_alloc.o,8,22,726,0,756,1749,710 +multi_heap.o,857,0,2217,0,3074,0,0 +queue.o,8,56,2569,0,2633,0,369 +unwind-dw2-xtensa.o,0,0,0,0,0,2172,324 +flash_ops.o,32,41,2352,0,2425,99,0 +rtc_clk.o,660,8,1794,0,2462,0,0 +ip6_frag.o,0,6,0,0,6,1905,442 +api_lib.o,0,0,0,0,0,1425,919 +vfs.o,192,40,0,0,232,1995,132 +igmp.o,0,12,0,0,12,1604,707 +unity_platform.o,0,13,0,0,13,1511,600 +vfs_uart.o,40,63,0,0,103,1775,271 +esp_timer_esp32.o,8,26,1295,0,1329,254,526 +rtc_periph.o,0,0,0,0,0,0,2080 +dns.o,0,1292,0,0,1292,1809,206 +heap_caps.o,4,0,1195,0,1199,188,593 +eh_personality.o,0,0,0,0,0,1561,384 +ip4.o,0,6,0,0,6,1664,139 +flash_mmap.o,0,296,1298,0,1594,124,327 +xtensa_vectors.o,8,0,1272,425,1705,0,36 +cpu_start.o,0,1,806,0,807,277,486 +clk.o,0,0,67,0,67,581,893 +netif.o,0,241,0,0,241,1239,287 +sys_arch.o,0,8,0,0,8,1216,222 +multi_heap_poisoning.o,470,0,964,0,1434,0,0 +heap_caps_init.o,0,4,0,0,4,1030,387 +timers.o,8,56,1149,0,1213,0,233 +mld6.o,0,4,0,0,4,1334,0 +cache_utils.o,4,14,836,0,854,81,390 +raw.o,0,4,0,0,4,1087,223 +esp_timer.o,8,20,702,0,730,429,142 +system_api.o,0,8,589,0,597,0,662 +soc_memory_layout.o,0,0,0,0,0,0,1239 +icmp.o,0,0,0,0,0,769,371 +xtensa_intr_asm.o,1024,0,51,0,1075,0,0 +log.o,8,268,456,0,732,396,166 +pthread.o,8,8,174,0,190,298,512 +icmp6.o,0,0,0,0,0,863,127 +port.o,0,16,617,0,633,0,369 +rtc_init.o,0,0,980,0,980,0,0 +rtc_time.o,0,0,803,0,803,0,137 +dport_access.o,8,40,539,0,587,189,129 +unity.o,0,108,0,0,108,767,90 +esp_ota_ops.o,0,0,0,0,0,123,717 +tcpip.o,0,16,0,0,16,644,191 +time.o,0,32,139,0,171,691,0 +periph_ctrl.o,8,0,0,0,8,520,256 +timers.o,0,12,0,0,12,638,131 +partition.o,0,8,0,0,8,582,141 +locks.o,8,0,552,0,560,0,84 +pthread_local_storage.o,8,4,0,0,12,476,126 +ipc.o,0,36,159,0,195,329,104 +inet_chksum.o,0,0,0,0,0,580,0 +tcpip_adapter_lwip.o,0,81,0,0,81,180,359 +crosscore_int.o,8,8,204,0,220,126,148 +netbuf.o,0,0,0,0,0,154,326 +vfs_lwip.o,0,0,0,0,0,307,155 +timer.o,16,0,0,0,16,112,281 +int_wdt.o,0,1,87,0,88,301,0 +eh_globals.o,0,16,0,0,16,149,193 +brownout.o,0,0,0,0,0,145,191 +cpu_util.o,0,0,310,0,310,0,0 +rtc_module.o,8,8,0,0,16,291,0 +xtensa_context.o,0,0,299,0,299,0,0 +eh_terminate.o,0,0,0,0,0,117,141 +ethernet.o,0,0,0,0,0,244,12 +dport_panic_highint_hdl.,8,0,234,0,242,0,0 +syscall_table.o,144,240,0,0,384,67,0 +dhcpserver.o,0,4,0,0,4,203,0 +freertos_hooks.o,8,128,43,0,179,137,0 +test_utils.o,0,0,0,0,0,38,140 +lib_a-sprintf.o,0,0,0,0,0,167,0 +cache_err_int.o,0,0,56,0,56,98,0 +list.o,0,0,142,0,142,0,0 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+lib_a-gmtime_r.o,0,0,0,0,0,0,0 +lib_a-impure.o,0,0,0,0,0,0,0 +lib_a-iswspace.o,0,0,0,0,0,0,0 +lib_a-lcltime_r.o,0,0,0,0,0,0,0 +lib_a-makebuf.o,0,0,0,0,0,0,0 +lib_a-mbrtowc.o,0,0,0,0,0,0,0 +lib_a-memchr.o,0,0,0,0,0,0,0 +lib_a-memcmp.o,0,0,0,0,0,0,0 +lib_a-memcpy.o,0,0,0,0,0,0,0 +lib_a-memmove.o,0,0,0,0,0,0,0 +lib_a-memset.o,0,0,0,0,0,0,0 +lib_a-month_lengths.o,0,0,0,0,0,0,0 +lib_a-putc.o,0,0,0,0,0,0,0 +lib_a-putchar.o,0,0,0,0,0,0,0 +lib_a-qsort.o,0,0,0,0,0,0,0 +lib_a-refill.o,0,0,0,0,0,0,0 +lib_a-sccl.o,0,0,0,0,0,0,0 +lib_a-siscanf.o,0,0,0,0,0,0,0 +lib_a-stdio.o,0,0,0,0,0,0,0 +lib_a-strcmp.o,0,0,0,0,0,0,0 +lib_a-strcpy.o,0,0,0,0,0,0,0 +lib_a-strcspn.o,0,0,0,0,0,0,0 +lib_a-strerror_r.o,0,0,0,0,0,0,0 +lib_a-strlcpy.o,0,0,0,0,0,0,0 +lib_a-strlen.o,0,0,0,0,0,0,0 +lib_a-strncmp.o,0,0,0,0,0,0,0 +lib_a-strncpy.o,0,0,0,0,0,0,0 +lib_a-strstr.o,0,0,0,0,0,0,0 +lib_a-strtol.o,0,0,0,0,0,0,0 +lib_a-strtoll.o,0,0,0,0,0,0,0 +lib_a-strtoul.o,0,0,0,0,0,0,0 +lib_a-strtoull.o,0,0,0,0,0,0,0 +lib_a-svfiscanf.o,0,0,0,0,0,0,0 +lib_a-tzcalc_limits.o,0,0,0,0,0,0,0 +lib_a-tzlock.o,0,0,0,0,0,0,0 +lib_a-tzset.o,0,0,0,0,0,0,0 +lib_a-tzset_r.o,0,0,0,0,0,0,0 +lib_a-tzvars.o,0,0,0,0,0,0,0 +lib_a-ungetc.o,0,0,0,0,0,0,0 +lib_a-wbuf.o,0,0,0,0,0,0,0 +lib_a-wcrtomb.o,0,0,0,0,0,0,0 +lib_a-wctomb_r.o,0,0,0,0,0,0,0 +lib_a-wsetup.o,0,0,0,0,0,0,0 +spi_common.c.obj,0,0,0,0,0,0,0 +esp_efuse_api.c.obj,0,0,0,0,0,0,0 +esp_efuse_fields.c.obj,0,0,0,0,0,0,0 +esp_efuse_table.c.obj,0,0,0,0,0,0,0 +esp_efuse_utility.c.obj,0,0,0,0,0,0,0 +hw_random.c.obj,0,0,0,0,0,0,0 +pm_locks.c.obj,0,0,0,0,0,0,0 +system_api.c.obj,0,0,0,0,0,0,0 +_bswapsi2.o,0,0,0,0,0,0,0 +esp_sha256.c.obj,0,0,0,0,0,0,0 +sha.c.obj,0,0,0,0,0,0,0 +gpio_hal.c.obj,0,0,0,0,0,0,0 +rtc_io_hal.c.obj,0,0,0,0,0,0,0 +rtc_io_periph.c.obj,0,0,0,0,0,0,0 +spi_periph.c.obj,0,0,0,0,0,0,0 +uart_periph.c.obj,0,0,0,0,0,0,0 +spi_flash_rom_patch.c.ob,0,0,0,0,0,0,0 +md5-internal.c.obj,0,0,0,0,0,0,0 +debug_helpers_asm.S.obj,0,0,0,0,0,0,0 +,:,,Difference +File,app.map,app2.map, - +Used static DRAM,17620 bytes (163116 remain 9.7% used),10604,+7016,-7016 remain,0 total +.data size,9324 bytes,8580,+744, +.bss size,8296 bytes,2024,+6272, +Used static IRAM,38932 bytes (92140 remain 29.7% used),38956,-24,24 remain,0 total +.text size,37908 bytes,37929,-21, +.vectors size,1024 bytes,1027,-3, +Used Flash size ,186524 bytes,99551,+86973, +.text,146944 bytes,77191,+69753, +.rodata,39580 bytes,22360,+17220, +Total image size,234780 bytes (.bin may be padded larger),147087,+87693, + +Symbols within the archive: libdriver.a (Not all symbols may be reported) + +.dram0.bss,,, - +p_uart_obj,12,12, +s_rtc_isr_handle,4,4, +s_rtc_isr_handler_list,4,4, +Section total:,20,20, + +.dram0.data,,, - +_gpio_hal,0,8,-8 +gpio_context,0,24,-24 +periph_spinlock,8,8, +rtc_spinlock,0,8,-8 +s_rtc_isr_handler_list_lock,8,8, +timer_spinlock,16,0,+16 +uart_context,0,48,-48 +uart_selectlock,8,8, +Section total:,40,112,-72 + +.flash.rodata,,, - +TG,8,0,+8 +__FUNCTION__$5441,24,0,+24 +__FUNCTION__$6237,0,19,-19 +__FUNCTION__$6241,0,18,-18 +__FUNCTION__$6245,0,20,-20 +__FUNCTION__$6249,0,19,-19 +__FUNCTION__$6253,0,16,-16 +__FUNCTION__$6257,0,15,-15 +__FUNCTION__$6262,0,15,-15 +__FUNCTION__$6282,0,19,-19 +__FUNCTION__$6912,0,21,-21 +__FUNCTION__$6917,0,21,-21 +__FUNCTION__$6922,0,19,-19 +__FUNCTION__$6927,0,19,-19 +__FUNCTION__$6932,0,16,-16 +__FUNCTION__$6937,0,16,-16 +__FUNCTION__$6942,0,18,-18 +__FUNCTION__$6948,0,18,-18 +__FUNCTION__$6982,0,22,-22 +__FUNCTION__$6987,0,23,-23 +__FUNCTION__$7173,0,18,-18 +__FUNCTION__$7238,0,27,-27 +__FUNCTION__$7244,0,17,-17 +__func__$6052,0,22,-22 +__func__$6060,0,21,-21 +__func__$6068,0,23,-23 +get_clk_en_mask,128,0,+128 +get_rst_en_mask,128,0,+128 +gpio_input_disable.str1.4,0,188,-188 +gpio_input_enable.str1.4,0,243,-243 +gpio_od_enable.str1.4,0,62,-62 +gpio_output_disable.str1.4,0,192,-192 +gpio_output_enable.str1.4,0,27,-27 +gpio_set_direction.str1.4,0,51,-51 +periph_module_enable,0,488,-488 +str1.4,249,0,+249 +uart_flush_input.str1.4,0,45,-45 +uart_pattern_enqueue.str1.4,0,88,-88 +uart_pattern_pop_pos.str1.4,0,18,-18 +uart_set_stop_bits.str1.4,0,15,-15 +uart_set_word_length.str1.4,0,31,-31 +Section total:,537,1910,-1373 + +.flash.text,,, - +get_clk_en_mask,211,0,+211 +get_clk_en_reg,21,0,+21 +get_rst_en_mask,157,0,+157 +get_rst_en_reg,25,0,+25 +gpio_input_disable,0,132,-132 +gpio_input_enable,0,140,-140 +gpio_od_disable,0,98,-98 +gpio_od_enable,0,118,-118 +gpio_output_disable,0,184,-184 +gpio_output_enable,0,153,-153 +gpio_set_direction,0,172,-172 +gpio_set_level,0,196,-196 +is_wifi_clk_peripheral,28,0,+28 +periph_module_enable,78,696,-618 +rtc_gpio_force_hold_dis_all,65,53,+12 +rtc_isr,86,90,-4 +rtc_isr_ensure_installed,75,79,-4 +rtc_isr_register,65,62,+3 +timer_group_intr_enable,112,0,+112 +uart_disable_intr_mask,0,96,-96 +uart_disable_rx_intr,0,18,-18 +uart_enable_intr_mask,0,98,-98 +uart_enable_rx_intr,0,18,-18 +uart_flush_input,0,457,-457 +uart_get_baudrate,0,82,-82 +uart_get_bufferedlen,0,109,-109 +uart_get_parity,0,69,-69 +uart_get_selectlock,12,12, +uart_get_stop_bits,0,69,-69 +uart_get_word_length,0,69,-69 +uart_is_driver_installed,0,30,-30 +uart_pattern_queue_update,0,74,-74 +uart_set_baudrate,0,96,-96 +uart_set_parity,0,82,-82 +uart_set_select_notif_callback,26,23,+3 +uart_set_stop_bits,0,128,-128 +uart_set_word_length,0,144,-144 +uart_wait_tx_done,0,425,-425 +Section total:,961,4272,-3311 + +.iram0.text,,, - +Section total:,0,0, + +.iram0.vectors,,, - +Section total:,0,0, + +.noinit,,, - +Section total:,0,0, + +.rtc.bss,,, - +Section total:,0,0, + +.rtc.data,,, - +Section total:,0,0, + +.rtc.text,,, - +Section total:,0,0, + +.rtc_noinit,,, - +Section total:,0,0, + +*** +Producing CSV output for esp32s2... +Total sizes:,,, +Used stat D/IRAM,43020 bytes (153588 remain 21.9% used),,, +.data size,7152 bytes,,, +.bss size,1936 bytes,,, +.text size,32905 bytes,,, +.vectors size,1027 bytes,,, +Used Flash size ,93019 bytes,,, +.text,74439 bytes,,, +.rodata,18580 bytes,,, +Total image size,134103 bytes (.bin may be padded larger),,, +Total sizes:,,, +Used stat D/IRAM,43020 bytes (153588 remain 21.9% used),,, +.data size,7152 bytes,,, +.bss size,1936 bytes,,, +.text size,32905 bytes,,, +.vectors size,1027 bytes,,, +Used Flash size ,93019 bytes,,, +.text,74439 bytes,,, +.rodata,18580 bytes,,, +Total image size,134103 bytes (.bin may be padded larger),,, +Per-archive contributions to ELF file: +Archive File,DRAM .data,& 0.bss,IRAM0 .text,& 0.vectors,ram_st_total,Flash .text,& .rodata +libc.a,364,4,0,0,368,54964,3645 +libfreertos.a,2080,736,10555,425,13796,0,1175 +libesp32s2.a,2621,22,4210,0,6853,4169,2209 +libsoc.a,405,8,7075,0,7488,1574,878 +libspi_flash.a,775,416,4114,0,5305,1109,1130 +libvfs.a,272,48,0,0,320,5581,555 +libesp_common.a,8,72,87,0,167,416,5304 +libheap.a,304,4,3171,0,3479,888,741 +libdriver.a,80,32,0,0,112,3216,894 +libnewlib.a,152,272,812,0,1236,856,84 +libesp_timer.a,16,20,668,0,704,657,546 +libesp_ringbuf.a,0,0,858,0,858,0,150 +liblog.a,8,272,594,0,874,94,147 +libapp_update.a,0,4,0,0,4,151,470 +libmain.a,0,0,0,0,0,192,196 +libhal.a,0,0,337,0,337,0,32 +libpthread.a,8,12,0,0,20,264,0 +libgcc.a,0,0,0,0,0,0,160 +(exe),0,0,0,3,3,3,12 +libcxx.a,0,0,0,0,0,11,0 +libbootloader_support.a,0,0,0,0,0,0,0 +libmbedcrypto.a,0,0,0,0,0,0,0 +libsoc_esp32s2.a,0,0,0,0,0,0,0 +libwpa_supplicant.a,0,0,0,0,0,0,0 +libxtensa.a,0,0,0,0,0,0,0 +Total sizes:,,, +Used stat D/IRAM,43020 bytes (153588 remain 21.9% used),,, +.data size,7152 bytes,,, +.bss size,1936 bytes,,, +.text size,32905 bytes,,, +.vectors size,1027 bytes,,, +Used Flash size ,93019 bytes,,, +.text,74439 bytes,,, +.rodata,18580 bytes,,, +Total image size,134103 bytes (.bin may be padded larger),,, +Per-file contributions to ELF file: +Object File,DRAM .data,& 0.bss,IRAM0 .text,& 0.vectors,ram_st_total,Flash .text,& .rodata +lib_a-vfprintf.o,0,0,0,0,0,13681,700 +lib_a-svfprintf.o,0,0,0,0,0,13294,752 +lib_a-svfiprintf.o,0,0,0,0,0,9623,1172 +lib_a-vfiprintf.o,0,0,0,0,0,9933,700 +tasks.c.obj,12,660,4954,0,5626,0,406 +esp_err_to_name.c.obj,0,0,0,0,0,53,5101 +panic.c.obj,2552,1,2321,0,4874,0,0 +vfs_uart.c.obj,80,8,0,0,88,3689,423 +lib_a-dtoa.o,0,0,0,0,0,3524,13 +intr_alloc.c.obj,8,13,660,0,681,1682,706 +queue.c.obj,0,0,2397,0,2397,0,424 +uart.c.obj,40,8,0,0,48,2087,452 +multi_heap.c.obj,300,0,2273,0,2573,0,0 +lib_a-mprec.o,0,0,0,0,0,2144,296 +rtc_clk.c.obj,381,8,1867,0,2256,0,0 +vfs.c.obj,192,40,0,0,232,1892,132 +portasm.S.obj,1544,0,365,0,1909,0,0 +spi_flash_hal_iram.c.obj,24,0,1804,0,1828,0,0 +spi_flash_chip_generic.c,340,0,1417,0,1757,0,0 +task_wdt.c.obj,53,4,0,0,57,1190,496 +flash_mmap.c.obj,0,392,1200,0,1592,124,252 +heap_caps.c.obj,4,0,898,0,902,50,362 +xtensa_vectors.S.obj,0,0,864,425,1289,0,0 +rtc_init.c.obj,0,0,1255,0,1255,0,8 +timers.c.obj,8,56,987,0,1051,0,223 +heap_caps_init.c.obj,0,4,0,0,4,838,379 +cpu_start.c.obj,0,0,536,0,536,152,489 +esp_timer_impl_systimer.,8,8,388,0,404,252,442 +ringbuf.c.obj,0,0,858,0,858,0,150 +periph_ctrl.c.obj,8,0,0,0,8,661,272 +clk.c.obj,0,0,34,0,34,626,281 +lib_a-fseeko.o,0,0,0,0,0,910,0 +partition.c.obj,0,8,0,0,8,679,181 +esp_flash_api.c.obj,0,0,600,0,600,16,240 +time.c.obj,0,32,115,0,147,719,0 +memory_layout_utils.c.ob,0,0,0,0,0,509,295 +rtc_wdt.c.obj,0,0,800,0,800,0,0 +esp_timer.c.obj,8,12,280,0,300,405,104 +log.c.obj,8,264,406,0,678,94,147 +rtc_time.c.obj,0,0,626,0,626,0,0 +esp_flash_spi_init.c.obj,120,4,0,0,124,215,281 +locks.c.obj,8,0,487,0,495,5,84 +xtensa_intr_asm.S.obj,512,0,51,0,563,0,0 +port.c.obj,0,16,408,0,424,0,87 +crosscore_int.c.obj,8,4,154,0,166,86,237 +soc_memory_layout.c.obj,0,0,0,0,0,0,479 +rtc_sleep.c.obj,0,0,414,0,414,0,0 +uart_hal.c.obj,0,0,0,0,0,409,0 +spi_flash_hal.c.obj,0,0,0,0,0,309,96 +cache_utils.c.obj,0,8,197,0,205,21,176 +hello_world_main.c.obj,0,0,0,0,0,192,196 +lib_a-locale.o,364,0,0,0,364,0,10 +timer.c.obj,16,16,0,0,32,184,170 +lib_a-refill.o,0,0,0,0,0,368,0 +esp_ota_ops.c.obj,0,4,0,0,4,151,214 +int_wdt.c.obj,0,0,59,0,59,302,0 +system_api_esp32s2.c.obj,0,0,323,0,323,27,0 +brownout.c.obj,0,0,0,0,0,120,203 +windowspill_asm.o,0,0,315,0,315,0,0 +cpu_util.c.obj,0,0,309,0,309,0,0 +brownout_hal.c.obj,0,0,0,0,0,304,0 +freertos_hooks.c.obj,8,64,47,0,119,243,0 +spi_flash_chip_gd.c.obj,95,0,181,0,276,0,0 +esp_app_desc.c.obj,0,0,0,0,0,0,256 +memspi_host_driver.c.obj,43,0,206,0,249,0,0 +rtc_module.c.obj,16,8,0,0,24,231,0 +lib_a-fopen.o,0,0,0,0,0,244,0 +lib_a-puts.o,0,0,0,0,0,234,2 +lib_a-reent.o,0,0,0,0,0,236,0 +lib_a-snprintf.o,0,0,0,0,0,217,0 +syscall_table.c.obj,144,240,0,0,384,70,0 +xtensa_context.S.obj,0,0,201,0,201,0,0 +spi_flash_chip_issi.c.ob,97,0,101,0,198,0,0 +pthread_local_storage.c.,8,4,0,0,12,183,0 +log_freertos.c.obj,0,8,188,0,196,0,0 +heap.c.obj,0,0,151,0,151,0,0 +xtensa_intr.c.obj,0,0,112,0,112,0,35 +spi_flash_os_func_app.c.,24,0,95,0,119,25,0 +list.c.obj,0,0,138,0,138,0,0 +lib_a-flags.o,0,0,0,0,0,128,0 +dport_panic_highint_hdl.,0,0,123,0,123,0,0 +lib_a-printf.o,0,0,0,0,0,116,0 +spi_flash_os_func_noos.c,16,0,89,0,105,0,0 +lib_a-s_frexp.o,0,0,0,0,0,100,0 +cache_err_int.c.obj,0,0,0,0,0,96,0 +lib_a-vprintf.o,0,0,0,0,0,94,0 +pthread.c.obj,0,8,0,0,8,81,0 +flash_ops.c.obj,20,4,28,0,52,29,0 +lib_a-localeconv.o,0,0,0,0,0,63,0 +reent_init.c.obj,0,0,59,0,59,0,0 +rtc_io.c.obj,0,0,0,0,0,53,0 +syscalls.c.obj,0,0,0,0,0,50,0 +xtensa_vector_defaults.S,0,0,46,0,46,0,0 +lib_a-fseek.o,0,0,0,0,0,45,0 +uart_hal_iram.c.obj,0,0,0,0,0,43,0 +system_api.c.obj,0,8,40,0,48,0,0 +_divdi3.o,0,0,0,0,0,0,40 +_moddi3.o,0,0,0,0,0,0,40 +_udivdi3.o,0,0,0,0,0,0,40 +_umoddi3.o,0,0,0,0,0,0,40 +xtensa_init.c.obj,0,4,32,0,36,0,0 +interrupts--intlevel.o,0,0,0,0,0,0,32 +spi_flash_chip_drivers.c,20,0,0,0,20,0,0 +pthread.c.obj,0,0,0,0,0,12,0 +lib_a-errno.o,0,0,0,0,0,10,0 +crtend.o,0,0,0,0,0,0,8 +pm_esp32s2.c.obj,0,0,0,0,0,8,0 +int_asm--set_intclear.o,0,0,8,0,8,0,0 +state_asm--restore_extra,0,0,7,0,7,0,0 +state_asm--save_extra_nw,0,0,7,0,7,0,0 +crti.o,0,0,0,3,3,3,0 +cxx_exception_stubs.cpp.,0,0,0,0,0,6,0 +cxx_guards.cpp.obj,0,0,0,0,0,5,0 +crtbegin.o,0,0,0,0,0,0,4 +FreeRTOS-openocd.c.obj,4,0,0,0,4,0,0 +crt0.o,0,0,0,0,0,0,0 +crtn.o,0,0,0,0,0,0,0 +project_elf_src.c.obj,0,0,0,0,0,0,0 +bootloader_common.c.obj,0,0,0,0,0,0,0 +bootloader_efuse_esp32s2,0,0,0,0,0,0,0 +bootloader_flash.c.obj,0,0,0,0,0,0,0 +bootloader_random.c.obj,0,0,0,0,0,0,0 +bootloader_sha.c.obj,0,0,0,0,0,0,0 +bootloader_utility.c.obj,0,0,0,0,0,0,0 +esp_image_format.c.obj,0,0,0,0,0,0,0 +flash_partitions.c.obj,0,0,0,0,0,0,0 +isatty.o,0,0,0,0,0,0,0 +lib_a-assert.o,0,0,0,0,0,0,0 +lib_a-bzero.o,0,0,0,0,0,0,0 +lib_a-ctype_.o,0,0,0,0,0,0,0 +lib_a-environ.o,0,4,0,0,4,0,0 +lib_a-envlock.o,0,0,0,0,0,0,0 +lib_a-fclose.o,0,0,0,0,0,0,0 +lib_a-fflush.o,0,0,0,0,0,0,0 +lib_a-findfp.o,0,0,0,0,0,0,0 +lib_a-fiprintf.o,0,0,0,0,0,0,0 +lib_a-fputs.o,0,0,0,0,0,0,0 +lib_a-fputwc.o,0,0,0,0,0,0,0 +lib_a-fvwrite.o,0,0,0,0,0,0,0 +lib_a-fwalk.o,0,0,0,0,0,0,0 +lib_a-getenv_r.o,0,0,0,0,0,0,0 +lib_a-gettzinfo.o,0,0,0,0,0,0,0 +lib_a-gmtime_r.o,0,0,0,0,0,0,0 +lib_a-impure.o,0,0,0,0,0,0,0 +lib_a-iswspace.o,0,0,0,0,0,0,0 +lib_a-lcltime_r.o,0,0,0,0,0,0,0 +lib_a-makebuf.o,0,0,0,0,0,0,0 +lib_a-mbrtowc.o,0,0,0,0,0,0,0 +lib_a-mbtowc_r.o,0,0,0,0,0,0,0 +lib_a-memchr.o,0,0,0,0,0,0,0 +lib_a-memcmp.o,0,0,0,0,0,0,0 +lib_a-memcpy.o,0,0,0,0,0,0,0 +lib_a-memmove.o,0,0,0,0,0,0,0 +lib_a-memset.o,0,0,0,0,0,0,0 +lib_a-month_lengths.o,0,0,0,0,0,0,0 +lib_a-putc.o,0,0,0,0,0,0,0 +lib_a-putchar.o,0,0,0,0,0,0,0 +lib_a-qsort.o,0,0,0,0,0,0,0 +lib_a-sccl.o,0,0,0,0,0,0,0 +lib_a-siscanf.o,0,0,0,0,0,0,0 +lib_a-stdio.o,0,0,0,0,0,0,0 +lib_a-strcmp.o,0,0,0,0,0,0,0 +lib_a-strcpy.o,0,0,0,0,0,0,0 +lib_a-strcspn.o,0,0,0,0,0,0,0 +lib_a-strerror.o,0,0,0,0,0,0,0 +lib_a-strerror_r.o,0,0,0,0,0,0,0 +lib_a-strlcpy.o,0,0,0,0,0,0,0 +lib_a-strlen.o,0,0,0,0,0,0,0 +lib_a-strncmp.o,0,0,0,0,0,0,0 +lib_a-strncpy.o,0,0,0,0,0,0,0 +lib_a-strstr.o,0,0,0,0,0,0,0 +lib_a-strtol.o,0,0,0,0,0,0,0 +lib_a-strtoll.o,0,0,0,0,0,0,0 +lib_a-strtoul.o,0,0,0,0,0,0,0 +lib_a-strtoull.o,0,0,0,0,0,0,0 +lib_a-svfiscanf.o,0,0,0,0,0,0,0 +lib_a-sysgettod.o,0,0,0,0,0,0,0 +lib_a-tzcalc_limits.o,0,0,0,0,0,0,0 +lib_a-tzlock.o,0,0,0,0,0,0,0 +lib_a-tzset.o,0,0,0,0,0,0,0 +lib_a-tzset_r.o,0,0,0,0,0,0,0 +lib_a-tzvars.o,0,0,0,0,0,0,0 +lib_a-u_strerr.o,0,0,0,0,0,0,0 +lib_a-ungetc.o,0,0,0,0,0,0,0 +lib_a-wbuf.o,0,0,0,0,0,0,0 +lib_a-wcrtomb.o,0,0,0,0,0,0,0 +lib_a-wctomb_r.o,0,0,0,0,0,0,0 +lib_a-wsetup.o,0,0,0,0,0,0,0 +gpio.c.obj,0,0,0,0,0,0,0 +spi_common.c.obj,0,0,0,0,0,0,0 +hw_random.c.obj,0,0,0,0,0,0,0 +pm_locks.c.obj,0,0,0,0,0,0,0 +_addsubdf3.o,0,0,0,0,0,0,0 +_cmpdf2.o,0,0,0,0,0,0,0 +_divdf3.o,0,0,0,0,0,0,0 +_fixdfsi.o,0,0,0,0,0,0,0 +_floatdidf.o,0,0,0,0,0,0,0 +_floatsidf.o,0,0,0,0,0,0,0 +_muldf3.o,0,0,0,0,0,0,0 +esp_mem.c.obj,0,0,0,0,0,0,0 +platform.c.obj,0,0,0,0,0,0,0 +platform_util.c.obj,0,0,0,0,0,0,0 +sha256.c.obj,0,0,0,0,0,0,0 +gpio_hal.c.obj,0,0,0,0,0,0,0 +rtc_io_hal.c.obj,0,0,0,0,0,0,0 +spi_flash_hal_gpspi.c.ob,0,0,0,0,0,0,0 +timer_hal.c.obj,0,0,0,0,0,0,0 +gpio_periph.c.obj,0,0,0,0,0,0,0 +rtc_io_periph.c.obj,0,0,0,0,0,0,0 +spi_periph.c.obj,0,0,0,0,0,0,0 +uart_periph.c.obj,0,0,0,0,0,0,0 +md5-internal.c.obj,0,0,0,0,0,0,0 +stdatomic.c.obj,0,0,0,0,0,0,0 +Total sizes:,,, +Used stat D/IRAM,43020 bytes (153588 remain 21.9% used),,, +.data size,7152 bytes,,, +.bss size,1936 bytes,,, +.text size,32905 bytes,,, +.vectors size,1027 bytes,,, +Used Flash size ,93019 bytes,,, +.text,74439 bytes,,, +.rodata,18580 bytes,,, +Total image size,134103 bytes (.bin may be padded larger),,, + +Symbols within the archive: libdriver.a (Not all symbols may be reported) + +Symbols from section: .dram0.bss +p_timer_obj,16 +p_uart_obj,8 +s_rtc_isr_handle,4 +s_rtc_isr_handler_list,4 +Section total: 32 + +Symbols from section: .dram0.data +uart_context,32 +timer_spinlock,16 +periph_spinlock,8 +rtc_spinlock,8 +s_rtc_isr_handler_list_lock,8 +uart_selectlock,8 +Section total: 80 + +Symbols from section: .flash.rodata +timer_get_counter_value.str1.4,146 +get_clk_en_mask,136 +get_rst_en_mask,136 +uart_pattern_enqueue.str1.4,88 +uart_flush_input.str1.4,45 +uart_set_word_length.str1.4,31 +__FUNCTION__$7196,27 +__FUNCTION__$5699,24 +__FUNCTION__$6971,23 +__FUNCTION__$6966,22 +__FUNCTION__$6896,21 +__FUNCTION__$6901,21 +__FUNCTION__$6906,19 +__FUNCTION__$6911,19 +__FUNCTION__$6926,18 +__FUNCTION__$6932,18 +__FUNCTION__$7131,18 +uart_pattern_pop_pos.str1.4,18 +__FUNCTION__$7202,17 +__FUNCTION__$6916,16 +__FUNCTION__$6921,16 +uart_set_stop_bits.str1.4,15 +Section total: 894 + +Symbols from section: .flash.text +uart_flush_input,453 +uart_wait_tx_done,417 +get_clk_en_mask,267 +get_rst_en_mask,198 +timer_group_intr_enable,184 +uart_set_word_length,144 +uart_set_stop_bits,128 +periph_module_enable,112 +uart_get_bufferedlen,109 +uart_enable_intr_mask,98 +uart_disable_intr_mask,96 +uart_set_baudrate,96 +rtc_isr,90 +uart_get_baudrate,82 +uart_set_parity,82 +rtc_isr_ensure_installed,79 +uart_pattern_queue_update,74 +uart_get_parity,69 +uart_get_stop_bits,69 +uart_get_word_length,69 +rtc_isr_register,62 +rtc_gpio_force_hold_dis_all,53 +is_wifi_clk_peripheral,38 +uart_is_driver_installed,30 +get_rst_en_reg,25 +uart_set_select_notif_callback,23 +get_clk_en_reg,21 +uart_disable_rx_intr,18 +uart_enable_rx_intr,18 +uart_get_selectlock,12 +Section total: 3216 + +Symbols from section: .iram0.text +Section total: 0 + +Symbols from section: .iram0.vectors +Section total: 0 + +Symbols from section: .noinit +Section total: 0 + +Symbols from section: .rtc.bss +Section total: 0 + +Symbols from section: .rtc.data +Section total: 0 + +Symbols from section: .rtc.text +Section total: 0 + +Symbols from section: .rtc_noinit +Section total: 0 + +*** +Producing CSV output for esp32c3... +Total sizes:,,, +Used stat D/IRAM,48466 bytes (279214 remain 14.8% used),,, +.data size,5048 bytes,,, +.bss size,3664 bytes,,, +.text size,39754 bytes,,, +Used Flash size ,117008 bytes,,, +.text,90400 bytes,,, +.rodata,26352 bytes,,, +Total image size,161810 bytes (.bin may be padded larger),,, +Total sizes:,,, +Used stat D/IRAM,48466 bytes (279214 remain 14.8% used),,, +.data size,5048 bytes,,, +.bss size,3664 bytes,,, +.text size,39754 bytes,,, +Used Flash size ,117008 bytes,,, +.text,90400 bytes,,, +.rodata,26352 bytes,,, +Total image size,161810 bytes (.bin may be padded larger),,, +Per-archive contributions to ELF file: +Archive File,DRAM .data,.rtc.data,DRAM .bss,IRAM0 .text,ram_st_total,Flash .text,& .rodata,& .appdesc +ilp32\libc.a,4,0,4,0,8,53504,4098,0 +libesp_hw_support.a,171,16,21,4356,4564,7722,1669,0 +libfreertos.a,16,0,2228,10094,12338,194,3143,0 +libspi_flash.a,1949,0,160,7674,9783,1716,1626,0 +libesp_system.a,185,0,125,1480,1790,6314,3302,0 +libheap.a,1961,0,8,5836,7805,1988,1207,0 +libvfs.a,272,0,48,0,320,6762,378,0 +libesp_common.a,6,0,0,0,6,56,7065,0 +libhal.a,85,0,0,5788,5873,1036,96,0 +libdriver.a,44,0,35,0,79,5280,1055,0 +libnewlib.a,194,0,440,1498,2132,1252,344,0 +libesp_timer.a,16,0,28,544,588,952,277,0 +libefuse.a,96,0,4,0,100,1188,475,0 +libesp_ringbuf.a,0,0,0,1004,1004,0,512,0 +liblog.a,8,0,272,264,544,562,122,0 +libriscv.a,0,0,256,652,908,74,137,0 +ilp32\libgcc.a,0,0,0,0,0,848,0,0 +libapp_update.a,1,0,12,198,211,218,125,256 +libmain.a,0,0,0,0,0,248,232,0 +libbootloader_support.a,0,0,0,340,340,98,0,0 +libpthread.a,0,0,12,0,12,342,0,0 +libsoc.a,0,0,0,0,0,0,88,0 +libesp_pm.a,0,0,0,0,0,28,0,0 +libesp_rom.a,0,0,0,24,24,0,0,0 +libcxx.a,0,0,0,0,0,2,0,0 +Total sizes:,,, +Used stat D/IRAM,48466 bytes (279214 remain 14.8% used),,, +.data size,5048 bytes,,, +.bss size,3664 bytes,,, +.text size,39754 bytes,,, +Used Flash size ,117008 bytes,,, +.text,90400 bytes,,, +.rodata,26352 bytes,,, +Total image size,161810 bytes (.bin may be padded larger),,, +Per-file contributions to ELF file: +Object File,DRAM .data,.rtc.data,DRAM .bss,IRAM0 .text,ram_st_total,Flash .text,& .rodata,& .appdesc +lib_a-vfprintf.o,0,0,0,0,0,14720,748,0 +lib_a-svfiprintf.o,0,0,0,0,0,9544,1172,0 +lib_a-vfiprintf.o,0,0,0,0,0,9756,737,0 +esp_err_to_name.c.obj,6,0,0,0,6,56,7065,0 +tasks.c.obj,8,0,664,5552,6224,0,1080,0 +heap_tlsf.c.obj,1796,0,0,4036,5832,0,0,0 +lib_a-dtoa.o,0,0,0,0,0,5312,233,0 +vfs_uart.c.obj,80,0,8,0,88,4402,270,0 +queue.c.obj,0,0,0,3192,3192,0,1495,0 +lib_a-mprec.o,0,0,0,0,0,4252,406,0 +memprot.c.obj,0,0,0,772,772,2762,800,0 +spi_flash_chip_generic.c,554,0,0,2684,3238,0,0,0 +uart.c.obj,40,0,8,0,48,2588,511,0 +intr_alloc.c.obj,0,0,13,688,701,2128,198,0 +panic_arch.c.obj,0,0,0,0,0,1060,1693,0 +vfs.c.obj,192,0,40,0,232,2360,108,0 +rtc_init.c.obj,0,0,0,0,0,2068,500,0 +gpio.c.obj,0,0,0,0,0,1856,459,0 +spi_flash_hal_iram.c.obj,0,0,0,2220,2220,0,0,0 +task_wdt.c.obj,45,0,12,0,57,1438,478,0 +flash_mmap.c.obj,0,0,136,1530,1666,182,240,0 +rtc_clk.c.obj,171,0,4,1738,1913,0,0,0 +esp_flash_api.c.obj,20,0,0,968,988,82,762,0 +heap_caps.c.obj,4,0,4,1122,1130,286,355,0 +ringbuf.c.obj,0,0,0,1004,1004,0,512,0 +spi_flash_hal_gpspi.c.ob,0,0,0,1484,1484,0,0,0 +esp_efuse_utility.c.obj,0,0,4,0,4,998,475,0 +locks.c.obj,0,0,168,924,1092,152,344,0 +heap_caps_init.c.obj,0,0,4,0,4,1052,338,0 +startup.c.obj,12,0,8,44,64,834,497,0 +partition.c.obj,0,0,8,0,8,1070,268,0 +lib_a-fseeko.o,0,0,0,0,0,1264,0,0 +wdt_hal_iram.c.obj,0,0,0,1160,1160,0,0,0 +lib_a-fvwrite.o,0,0,0,0,0,1156,0,0 +lib_a-findfp.o,0,0,0,0,0,1040,96,0 +panic.c.obj,12,0,5,6,23,958,131,0 +clk.c.obj,0,0,0,0,0,838,212,0 +memspi_host_driver.c.obj,397,0,0,636,1033,0,0,0 +spi_flash_chip_winbond.c,203,0,0,748,951,0,0,0 +memory_layout_utils.c.ob,0,0,0,0,0,650,283,0 +periph_ctrl.c.obj,0,0,27,0,27,836,85,0 +esp_timer.c.obj,0,0,8,296,304,514,72,0 +lib_a-fflush.o,0,0,0,0,0,856,0,0 +trunctfdf2.o,0,0,0,0,0,848,0,0 +port.c.obj,4,0,1556,588,2148,66,190,0 +systimer_hal.c.obj,85,0,0,760,845,0,0,0 +multi_heap.c.obj,157,0,0,678,835,0,0,0 +time.c.obj,0,0,20,180,200,620,0,0 +log.c.obj,8,0,264,32,304,562,122,0 +cpu_start.c.obj,0,0,0,464,464,42,158,0 +esp_timer_impl_systimer.,16,0,12,210,238,296,125,0 +esp_flash_spi_init.c.obj,68,0,4,0,72,272,261,0 +spi_flash_os_func_app.c.,52,0,0,414,466,34,95,0 +rtc_time.c.obj,0,0,0,590,590,0,0,0 +port_systick.c.obj,0,0,8,370,378,0,192,0 +vectors.S.obj,0,0,0,522,522,0,0,0 +lib_a-refill.o,0,0,0,0,0,512,0,0 +lib_a-reent.o,0,0,0,0,0,500,0,0 +esp_app_desc.c.obj,1,0,8,198,207,32,4,256 +lib_a-ftello.o,0,0,0,0,0,488,0,0 +hello_world_main.c.obj,0,0,0,0,0,248,232,0 +lib_a-fclose.o,0,0,0,0,0,456,0,0 +spi_flash_hal.c.obj,0,0,0,0,0,342,96,0 +lib_a-makebuf.o,0,0,0,0,0,436,0,0 +port_common.c.obj,0,0,0,104,104,128,186,0 +lib_a-fopen.o,0,0,0,0,0,416,0,0 +sleep_modes.c.obj,0,0,0,0,0,244,171,0 +crosscore_int.c.obj,0,0,4,162,166,106,120,0 +lib_a-wsetup.o,0,0,0,0,0,384,0,0 +lib_a-locale.o,4,0,0,0,4,0,378,0 +lib_a-puts.o,0,0,0,0,0,372,0,0 +uart_hal.c.obj,0,0,0,0,0,366,0,0 +panic_handler.c.obj,8,0,4,82,94,266,8,0 +esp_time_impl.c.obj,0,0,12,0,12,362,0,0 +lib_a-fwalk.o,0,0,0,0,0,340,0,0 +bootloader_flash.c.obj,0,0,0,340,340,0,0,0 +freertos_hooks.c.obj,0,0,64,48,112,290,0,0 +lib_a-stdio.o,0,0,0,0,0,316,0,0 +spi_flash_chip_gd.c.obj,123,0,0,190,313,0,0,0 +rtc_sleep.c.obj,0,0,0,308,308,0,0,0 +esp_ota_ops.c.obj,0,0,4,0,4,186,121,0 +system_internal.c.obj,0,0,0,298,298,0,0,0 +int_wdt.c.obj,0,0,8,74,82,206,0,0 +interrupt.c.obj,0,0,256,130,386,0,137,0 +spi_flash_chip_mxic.c.ob,190,0,0,76,266,0,0,0 +esp_err.c.obj,108,0,0,154,262,0,0,0 +system_time.c.obj,0,0,8,38,46,142,80,0 +lib_a-ctype_.o,0,0,0,0,0,0,257,0 +cpu_util_esp32c3.c.obj,0,0,0,0,0,250,0,0 +esp_clk.c.obj,0,16,4,30,50,200,0,0 +pthread_local_storage.c.,0,0,4,0,4,242,0,0 +spi_flash_chip_issi.c.ob,125,0,0,112,237,0,0,0 +memory_layout.c.obj,4,0,0,0,4,0,231,0 +log_freertos.c.obj,0,0,8,232,240,0,0,0 +newlib_init.c.obj,156,0,240,0,396,76,0,0 +lib_a-printf.o,0,0,0,0,0,224,0,0 +regi2c_ctrl.c.obj,0,0,0,202,202,0,0,0 +heap.c.obj,0,0,0,190,190,0,0,0 +lib_a-s_frexp.o,0,0,0,0,0,180,8,0 +lib_a-assert.o,0,0,0,0,0,124,63,0 +cache_utils.c.obj,0,0,8,144,152,38,0,0 +lib_a-vprintf.o,0,0,0,0,0,176,0,0 +spi_flash_chip_boya.c.ob,125,0,0,46,171,0,0,0 +esp_system.c.obj,0,0,20,90,110,80,0,0 +lib_a-flags.o,0,0,0,0,0,168,0,0 +abort.c.obj,38,0,0,128,166,0,0,0 +brownout_hal.c.obj,0,0,0,0,0,160,0,0 +esp_efuse_api.c.obj,0,0,0,0,0,158,0,0 +portasm.S.obj,0,0,0,154,154,0,0,0 +lib_a-fiprintf.o,0,0,0,0,0,148,0,0 +list.c.obj,0,0,0,134,134,0,0,0 +spi_flash_encrypt_hal_ir,0,0,0,132,132,0,0,0 +cache_err_int.c.obj,0,0,0,4,4,124,0,0 +spi_flash_os_func_noos.c,36,0,0,86,122,0,0,0 +lib_a-mbtowc_r.o,0,0,0,0,0,108,0,0 +flash_ops.c.obj,24,0,4,40,68,38,0,0 +pthread.c.obj,0,0,8,0,8,100,0,0 +esp_efuse_table.c.obj,96,0,0,0,96,0,0,0 +uart_hal_iram.c.obj,0,0,0,0,0,88,0,0 +gpio_periph.c.obj,0,0,0,0,0,0,88,0 +apb_backup_dma.c.obj,0,0,0,52,52,34,0,0 +interrupt_controller_hal,0,0,0,0,0,80,0,0 +reent_init.c.obj,0,0,0,76,76,0,0,0 +instruction_decode.c.obj,0,0,0,0,0,74,0,0 +chip_info.c.obj,0,0,0,0,0,70,0,0 +lib_a-fseek.o,0,0,0,0,0,68,0,0 +lib_a-wctomb_r.o,0,0,0,0,0,64,0,0 +flash_qio_mode.c.obj,0,0,0,0,0,58,0,0 +lib_a-sysgettod.o,0,0,0,0,0,56,0,0 +brownout.c.obj,0,0,0,0,0,38,5,0 +lib_a-localeconv.o,0,0,0,0,0,40,0,0 +syscalls.c.obj,0,0,0,0,0,36,0,0 +esp_efuse_fields.c.obj,0,0,0,0,0,32,0,0 +cpu_hal.c.obj,0,0,0,32,32,0,0,0 +spi_flash_chip_drivers.c,32,0,0,0,32,0,0,0 +lib_a-errno.o,0,0,0,0,0,28,0,0 +cpu_util.c.obj,0,0,0,28,28,0,0,0 +pm_impl.c.obj,0,0,0,0,0,28,0,0 +bootloader_flash_config_,0,0,0,0,0,26,0,0 +esp_rom_uart.c.obj,0,0,0,24,24,0,0,0 +bootloader_mem.c.obj,0,0,0,0,0,14,0,0 +pthread.c.obj,0,0,0,0,0,6,0,0 +spi_bus_lock.c.obj,4,0,0,0,4,0,0,0 +FreeRTOS-openocd.c.obj,4,0,0,0,4,0,0,0 +cxx_guards.cpp.obj,0,0,0,0,0,2,0,0 +ubsan.c.obj,0,0,0,2,2,0,0,0 +lib_a-environ.o,0,0,4,0,4,0,0,0 +_divdi3.o,0,0,0,0,0,0,0,0 +_moddi3.o,0,0,0,0,0,0,0,0 +_udivdi3.o,0,0,0,0,0,0,0,0 +_umoddi3.o,0,0,0,0,0,0,0,0 +Total sizes:,,, +Used stat D/IRAM,48466 bytes (279214 remain 14.8% used),,, +.data size,5048 bytes,,, +.bss size,3664 bytes,,, +.text size,39754 bytes,,, +Used Flash size ,117008 bytes,,, +.text,90400 bytes,,, +.rodata,26352 bytes,,, +Total image size,161810 bytes (.bin may be padded larger),,, + +Symbols within the archive: libdriver.a (Not all symbols may be reported) + +Symbols from section: .dram0.bss +ref_counts,27 +.p_uart_obj,8 +Section total: 35 + +Symbols from section: .dram0.data +uart_context,32 +.uart_selectlock,8 +..g_spi_lock_main_flash_dev,4 +Section total: 44 + +Symbols from section: .flash.appdesc +Section total: 0 + +Symbols from section: .flash.rodata +gpio_set_pull_mode.str1.4,93 +periph_module_enable.str1.4,64 +gpio_input_enable.str1.4,62 +uart_disable_intr_mask_and_return_prev.str1.4,54 +uart_pattern_pop_pos.str1.4,49 +uart_set_stop_bits.str1.4,46 +uart_set_word_length.str1.4,46 +uart_flush_input.str1.4,45 +__FUNCTION__.7467,39 +__FUNCTION__.7459,27 +gpio_sleep_output_enable.str1.4,27 +__FUNCTION__.6231,26 +__FUNCTION__.6223,25 +__FUNCTION__.6235,25 +__FUNCTION__.6240,25 +__FUNCTION__.6246,25 +__FUNCTION__.6219,24 +__FUNCTION__.6227,24 +__FUNCTION__.6215,23 +__FUNCTION__.6211,22 +__FUNCTION__.7222,22 +__FUNCTION__.6207,21 +__FUNCTION__.7153,21 +__FUNCTION__.7158,21 +__func__.4238,21 +__FUNCTION__.6261,19 +__FUNCTION__.7163,19 +__FUNCTION__.7168,19 +__FUNCTION__.6257,18 +__FUNCTION__.7183,18 +__FUNCTION__.7188,18 +__FUNCTION__.7394,18 +__FUNCTION__.7471,17 +__FUNCTION__.7173,16 +__FUNCTION__.7178,16 +Section total: 1055 + +Symbols from section: .flash.rodata_noload +Section total: 0 + +Symbols from section: .flash.text +periph_module_enable,736 +uart_flush_input,580 +uart_wait_tx_done,484 +gpio_sleep_set_pull_mode,318 +uart_set_stop_bits,178 +uart_set_word_length,178 +gpio_sleep_set_direction,156 +uart_get_bufferedlen,152 +gpio_sleep_pulldown_en,148 +gpio_sleep_pullup_en,148 +gpio_sleep_sel_en,148 +gpio_sleep_pulldown_dis,146 +gpio_sleep_pullup_dis,146 +gpio_sleep_sel_dis,146 +uart_disable_intr_mask_and_return_prev,138 +gpio_sleep_input_enable,126 +gpio_sleep_output_enable,126 +gpio_sleep_input_disable,124 +gpio_sleep_output_disable,124 +uart_enable_intr_mask,122 +uart_get_baudrate,116 +uart_set_baudrate,116 +uart_set_parity,116 +uart_get_parity,86 +uart_get_stop_bits,86 +uart_get_word_length,86 +uart_pattern_queue_update,80 +periph_ll_get_clk_en_reg,50 +periph_ll_get_rst_en_reg,50 +uart_is_driver_installed,34 +uart_set_select_notif_callback,30 +uart_get_selectlock,6 +Section total: 5280 + +Symbols from section: .iram0.bss +Section total: 0 + +Symbols from section: .iram0.data +Section total: 0 + +Symbols from section: .iram0.text +Section total: 0 + +Symbols from section: .noinit +Section total: 0 + +Symbols from section: .rtc.bss +Section total: 0 + +Symbols from section: .rtc.data +Section total: 0 + +Symbols from section: .rtc.text +Section total: 0 + +Symbols from section: .rtc_noinit +Section total: 0 + +*** +Producing CSV output for esp32h2... +Total sizes:,,, +Used stat D/IRAM,45656 bytes (282024 remain 13.9% used),,, +.data size,4864 bytes,,, +.bss size,3664 bytes,,, +.text size,37128 bytes,,, +Used Flash size ,110492 bytes,,, +.text,85252 bytes,,, +.rodata,24984 bytes,,, +Total image size,152484 bytes (.bin may be padded larger),,, +Total sizes:,,, +Used stat D/IRAM,45656 bytes (282024 remain 13.9% used),,, +.data size,4864 bytes,,, +.bss size,3664 bytes,,, +.text size,37128 bytes,,, +Used Flash size ,110492 bytes,,, +.text,85252 bytes,,, +.rodata,24984 bytes,,, +Total image size,152484 bytes (.bin may be padded larger),,, +Per-archive contributions to ELF file: +Archive File,DRAM .data,.rtc.data,DRAM .bss,IRAM0 .text,ram_st_total,Flash .text,& .rodata,& .appdesc +ilp32\libc.a,4,0,4,0,8,53504,4098,0 +libfreertos.a,16,0,2228,10080,12324,194,3143,0 +libspi_flash.a,1949,0,160,7658,9767,1706,1626,0 +libheap.a,1961,0,8,5836,7805,1988,1207,0 +libesp_system.a,185,0,125,1392,1702,5548,3197,0 +libesp_hw_support.a,71,16,21,1920,2028,5374,998,0 +libvfs.a,272,0,48,0,320,6760,378,0 +libesp_common.a,6,0,0,0,6,56,7065,0 +libhal.a,85,0,0,5742,5827,994,96,0 +libdriver.a,44,0,35,0,79,3326,596,0 +libnewlib.a,194,0,440,1498,2132,1248,344,0 +libesp_timer.a,16,0,28,544,588,952,277,0 +libefuse.a,12,0,4,0,16,1186,475,0 +libesp_ringbuf.a,0,0,0,1002,1002,0,512,0 +liblog.a,8,0,272,264,544,562,122,0 +libriscv.a,0,0,256,652,908,74,137,0 +ilp32\libgcc.a,0,0,0,0,0,848,0,0 +libapp_update.a,1,0,12,198,211,218,125,256 +libmain.a,0,0,0,0,0,248,232,0 +libbootloader_support.a,0,0,0,340,340,98,0,0 +libpthread.a,0,0,12,0,12,342,0,0 +libesp_pm.a,0,0,0,0,0,6,0,0 +libcxx.a,0,0,0,0,0,2,0,0 +Total sizes:,,, +Used stat D/IRAM,45656 bytes (282024 remain 13.9% used),,, +.data size,4864 bytes,,, +.bss size,3664 bytes,,, +.text size,37128 bytes,,, +Used Flash size ,110492 bytes,,, +.text,85252 bytes,,, +.rodata,24984 bytes,,, +Total image size,152484 bytes (.bin may be padded larger),,, +Per-file contributions to ELF file: +Object File,DRAM .data,.rtc.data,DRAM .bss,IRAM0 .text,ram_st_total,Flash .text,& .rodata,& .appdesc +lib_a-vfprintf.o,0,0,0,0,0,14720,748,0 +lib_a-svfiprintf.o,0,0,0,0,0,9544,1172,0 +lib_a-vfiprintf.o,0,0,0,0,0,9756,737,0 +esp_err_to_name.c.obj,6,0,0,0,6,56,7065,0 +tasks.c.obj,8,0,664,5552,6224,0,1080,0 +heap_tlsf.c.obj,1796,0,0,4036,5832,0,0,0 +lib_a-dtoa.o,0,0,0,0,0,5312,233,0 +vfs_uart.c.obj,80,0,8,0,88,4402,270,0 +queue.c.obj,0,0,0,3180,3180,0,1495,0 +lib_a-mprec.o,0,0,0,0,0,4252,406,0 +memprot.c.obj,0,0,0,772,772,2750,800,0 +spi_flash_chip_generic.c,554,0,0,2668,3222,0,0,0 +uart.c.obj,40,0,8,0,48,2588,511,0 +intr_alloc.c.obj,0,0,13,688,701,2128,198,0 +panic_arch.c.obj,0,0,0,0,0,1060,1693,0 +vfs.c.obj,192,0,40,0,232,2358,108,0 +spi_flash_hal_iram.c.obj,0,0,0,2220,2220,0,0,0 +task_wdt.c.obj,45,0,12,0,57,1438,478,0 +flash_mmap.c.obj,0,0,136,1530,1666,182,240,0 +esp_flash_api.c.obj,20,0,0,968,988,80,762,0 +heap_caps.c.obj,4,0,4,1122,1130,286,355,0 +ringbuf.c.obj,0,0,0,1002,1002,0,512,0 +spi_flash_hal_gpspi.c.ob,0,0,0,1484,1484,0,0,0 +esp_efuse_utility.c.obj,0,0,4,0,4,996,475,0 +locks.c.obj,0,0,168,924,1092,152,344,0 +heap_caps_init.c.obj,0,0,4,0,4,1052,338,0 +startup.c.obj,12,0,8,26,46,834,497,0 +partition.c.obj,0,0,8,0,8,1066,268,0 +lib_a-fseeko.o,0,0,0,0,0,1264,0,0 +wdt_hal_iram.c.obj,0,0,0,1158,1158,0,0,0 +lib_a-fvwrite.o,0,0,0,0,0,1156,0,0 +lib_a-findfp.o,0,0,0,0,0,1040,96,0 +panic.c.obj,12,0,5,6,23,958,131,0 +memspi_host_driver.c.obj,397,0,0,636,1033,0,0,0 +spi_flash_chip_winbond.c,203,0,0,748,951,0,0,0 +memory_layout_utils.c.ob,0,0,0,0,0,650,283,0 +esp_timer.c.obj,0,0,8,296,304,514,72,0 +lib_a-fflush.o,0,0,0,0,0,856,0,0 +trunctfdf2.o,0,0,0,0,0,848,0,0 +port.c.obj,4,0,1556,588,2148,66,190,0 +multi_heap.c.obj,157,0,0,678,835,0,0,0 +periph_ctrl.c.obj,0,0,27,0,27,738,85,0 +systimer_hal.c.obj,85,0,0,716,801,0,0,0 +time.c.obj,0,0,20,180,200,618,0,0 +log.c.obj,8,0,264,32,304,562,122,0 +esp_timer_impl_systimer.,16,0,12,210,238,296,125,0 +cpu_start.c.obj,0,0,0,432,432,42,158,0 +esp_flash_spi_init.c.obj,68,0,4,0,72,268,261,0 +spi_flash_os_func_app.c.,52,0,0,414,466,34,95,0 +port_systick.c.obj,0,0,8,368,376,0,192,0 +vectors.S.obj,0,0,0,522,522,0,0,0 +lib_a-refill.o,0,0,0,0,0,512,0,0 +lib_a-reent.o,0,0,0,0,0,500,0,0 +esp_app_desc.c.obj,1,0,8,198,207,32,4,256 +lib_a-ftello.o,0,0,0,0,0,488,0,0 +hello_world_main.c.obj,0,0,0,0,0,248,232,0 +lib_a-fclose.o,0,0,0,0,0,456,0,0 +lib_a-makebuf.o,0,0,0,0,0,436,0,0 +spi_flash_hal.c.obj,0,0,0,0,0,332,96,0 +port_common.c.obj,0,0,0,104,104,128,186,0 +lib_a-fopen.o,0,0,0,0,0,416,0,0 +crosscore_int.c.obj,0,0,4,162,166,106,120,0 +lib_a-wsetup.o,0,0,0,0,0,384,0,0 +lib_a-locale.o,4,0,0,0,4,0,378,0 +rtc_clk.c.obj,71,0,4,308,383,0,0,0 +lib_a-puts.o,0,0,0,0,0,372,0,0 +panic_handler.c.obj,8,0,4,82,94,266,8,0 +esp_time_impl.c.obj,0,0,12,0,12,360,0,0 +lib_a-fwalk.o,0,0,0,0,0,340,0,0 +bootloader_flash.c.obj,0,0,0,340,340,0,0,0 +freertos_hooks.c.obj,0,0,64,48,112,290,0,0 +uart_hal.c.obj,0,0,0,0,0,334,0,0 +lib_a-stdio.o,0,0,0,0,0,316,0,0 +spi_flash_chip_gd.c.obj,123,0,0,190,313,0,0,0 +esp_ota_ops.c.obj,0,0,4,0,4,186,121,0 +int_wdt.c.obj,0,0,8,74,82,206,0,0 +interrupt.c.obj,0,0,256,130,386,0,137,0 +spi_flash_chip_mxic.c.ob,190,0,0,76,266,0,0,0 +esp_err.c.obj,108,0,0,154,262,0,0,0 +system_internal.c.obj,0,0,0,260,260,0,0,0 +system_time.c.obj,0,0,8,38,46,142,80,0 +lib_a-ctype_.o,0,0,0,0,0,0,257,0 +cpu_util_esp32h2.c.obj,0,0,0,0,0,250,0,0 +pthread_local_storage.c.,0,0,4,0,4,242,0,0 +spi_flash_chip_issi.c.ob,125,0,0,112,237,0,0,0 +memory_layout.c.obj,4,0,0,0,4,0,231,0 +log_freertos.c.obj,0,0,8,232,240,0,0,0 +newlib_init.c.obj,156,0,240,0,396,76,0,0 +lib_a-printf.o,0,0,0,0,0,224,0,0 +esp_clk.c.obj,0,16,4,30,50,176,0,0 +heap.c.obj,0,0,0,190,190,0,0,0 +lib_a-s_frexp.o,0,0,0,0,0,180,8,0 +lib_a-assert.o,0,0,0,0,0,124,63,0 +cache_utils.c.obj,0,0,8,144,152,38,0,0 +fpga_overrides.c.obj,0,0,0,0,0,72,107,0 +lib_a-vprintf.o,0,0,0,0,0,176,0,0 +spi_flash_chip_boya.c.ob,125,0,0,46,171,0,0,0 +esp_system.c.obj,0,0,20,90,110,80,0,0 +lib_a-flags.o,0,0,0,0,0,168,0,0 +abort.c.obj,38,0,0,128,166,0,0,0 +brownout_hal.c.obj,0,0,0,0,0,160,0,0 +esp_efuse_api.c.obj,0,0,0,0,0,158,0,0 +portasm.S.obj,0,0,0,154,154,0,0,0 +lib_a-fiprintf.o,0,0,0,0,0,148,0,0 +list.c.obj,0,0,0,134,134,0,0,0 +spi_flash_encrypt_hal_ir,0,0,0,132,132,0,0,0 +cache_err_int.c.obj,0,0,0,4,4,124,0,0 +spi_flash_os_func_noos.c,36,0,0,86,122,0,0,0 +lib_a-mbtowc_r.o,0,0,0,0,0,108,0,0 +flash_ops.c.obj,24,0,4,40,68,38,0,0 +pthread.c.obj,0,0,8,0,8,100,0,0 +uart_hal_iram.c.obj,0,0,0,0,0,88,0,0 +apb_backup_dma.c.obj,0,0,0,52,52,34,0,0 +interrupt_controller_hal,0,0,0,0,0,80,0,0 +reent_init.c.obj,0,0,0,76,76,0,0,0 +regi2c_ctrl.c.obj,0,0,0,74,74,0,0,0 +instruction_decode.c.obj,0,0,0,0,0,74,0,0 +chip_info.c.obj,0,0,0,0,0,70,0,0 +lib_a-fseek.o,0,0,0,0,0,68,0,0 +lib_a-wctomb_r.o,0,0,0,0,0,64,0,0 +flash_qio_mode.c.obj,0,0,0,0,0,58,0,0 +lib_a-sysgettod.o,0,0,0,0,0,56,0,0 +brownout.c.obj,0,0,0,0,0,38,5,0 +lib_a-localeconv.o,0,0,0,0,0,40,0,0 +syscalls.c.obj,0,0,0,0,0,36,0,0 +esp_efuse_fields.c.obj,0,0,0,0,0,32,0,0 +cpu_hal.c.obj,0,0,0,32,32,0,0,0 +spi_flash_chip_drivers.c,32,0,0,0,32,0,0,0 +lib_a-errno.o,0,0,0,0,0,28,0,0 +cpu_util.c.obj,0,0,0,28,28,0,0,0 +bootloader_flash_config_,0,0,0,0,0,26,0,0 +rtc_time.c.obj,0,0,0,20,20,0,0,0 +bootloader_mem.c.obj,0,0,0,0,0,14,0,0 +esp_efuse_table.c.obj,12,0,0,0,12,0,0,0 +pm_impl.c.obj,0,0,0,0,0,6,0,0 +pthread.c.obj,0,0,0,0,0,6,0,0 +spi_bus_lock.c.obj,4,0,0,0,4,0,0,0 +FreeRTOS-openocd.c.obj,4,0,0,0,4,0,0,0 +cxx_guards.cpp.obj,0,0,0,0,0,2,0,0 +ubsan.c.obj,0,0,0,2,2,0,0,0 +lib_a-environ.o,0,0,4,0,4,0,0,0 +_divdi3.o,0,0,0,0,0,0,0,0 +_moddi3.o,0,0,0,0,0,0,0,0 +_udivdi3.o,0,0,0,0,0,0,0,0 +_umoddi3.o,0,0,0,0,0,0,0,0 +Total sizes:,,, +Used stat D/IRAM,45656 bytes (282024 remain 13.9% used),,, +.data size,4864 bytes,,, +.bss size,3664 bytes,,, +.text size,37128 bytes,,, +Used Flash size ,110492 bytes,,, +.text,85252 bytes,,, +.rodata,24984 bytes,,, +Total image size,152484 bytes (.bin may be padded larger),,, + +Symbols within the archive: libdriver.a (Not all symbols may be reported) + +Symbols from section: .dram0.bss +ref_counts,27 +.p_uart_obj,8 +Section total: 35 + +Symbols from section: .dram0.data +uart_context,32 +.uart_selectlock,8 +..g_spi_lock_main_flash_dev,4 +Section total: 44 + +Symbols from section: .flash.appdesc +Section total: 0 + +Symbols from section: .flash.rodata +periph_module_enable.str1.4,64 +uart_disable_intr_mask_and_return_prev.str1.4,54 +uart_pattern_pop_pos.str1.4,49 +uart_set_stop_bits.str1.4,46 +uart_set_word_length.str1.4,46 +uart_flush_input.str1.4,45 +__FUNCTION__.7485,39 +__FUNCTION__.7477,27 +__FUNCTION__.7240,22 +__FUNCTION__.7171,21 +__FUNCTION__.7176,21 +__func__.4215,21 +__FUNCTION__.7181,19 +__FUNCTION__.7186,19 +__FUNCTION__.7201,18 +__FUNCTION__.7206,18 +__FUNCTION__.7412,18 +__FUNCTION__.7489,17 +__FUNCTION__.7191,16 +__FUNCTION__.7196,16 +Section total: 596 + +Symbols from section: .flash.text +periph_module_enable,682 +uart_flush_input,580 +uart_wait_tx_done,484 +uart_set_stop_bits,178 +uart_set_word_length,178 +uart_get_bufferedlen,152 +uart_disable_intr_mask_and_return_prev,138 +uart_enable_intr_mask,122 +uart_get_baudrate,116 +uart_set_baudrate,116 +uart_set_parity,116 +uart_get_parity,86 +uart_get_stop_bits,86 +uart_get_word_length,86 +uart_pattern_queue_update,80 +uart_is_driver_installed,34 +uart_set_select_notif_callback,30 +periph_ll_get_clk_en_reg,28 +periph_ll_get_rst_en_reg,28 +uart_get_selectlock,6 +Section total: 3326 + +Symbols from section: .iram0.bss +Section total: 0 + +Symbols from section: .iram0.data +Section total: 0 + +Symbols from section: .iram0.text +Section total: 0 + +Symbols from section: .noinit +Section total: 0 + +Symbols from section: .rtc.bss +Section total: 0 + +Symbols from section: .rtc.data +Section total: 0 + +Symbols from section: .rtc.text +Section total: 0 + +Symbols from section: .rtc_noinit +Section total: 0 + +*** +Producing CSV output for esp32s3... +Total sizes:,,, +Used static IRAM,46786 bytes (239934 remain 16.3% used),,, +.text size,45759 bytes,,, +.vectors size,1027 bytes,,, +Used stat D/IRAM,11772 bytes (123396 remain 8.7% used),,, +.data size,9252 bytes,,, +.bss size,2520 bytes,,, +Used Flash size ,114851 bytes,,, +.text,87463 bytes,,, +.rodata,27132 bytes,,, +Total image size,170889 bytes (.bin may be padded larger),,, +Total sizes:,,, +Used static IRAM,46786 bytes (239934 remain 16.3% used),,, +.text size,45759 bytes,,, +.vectors size,1027 bytes,,, +Used stat D/IRAM,11772 bytes (123396 remain 8.7% used),,, +.data size,9252 bytes,,, +.bss size,2520 bytes,,, +Used Flash size ,114851 bytes,,, +.text,87463 bytes,,, +.rodata,27132 bytes,,, +Total image size,170889 bytes (.bin may be padded larger),,, +Per-archive contributions to ELF file: +Archive File,DRAM .data,.rtc.data,DRAM .bss,IRAM0 .text,& 0.vectors,ram_st_total,Flash .text,& .rodata,& .appdesc +no-rtti\libc.a,4,0,4,0,0,8,58528,4685,0 +libfreertos.a,3128,0,748,13747,425,18048,293,3668,0 +libspi_flash.a,1886,0,550,7539,0,9975,1605,2196,0 +libesp_system.a,205,0,206,2914,0,3325,6183,3549,0 +libheap.a,1957,0,8,5195,0,7160,1741,1383,0 +libhal.a,109,0,0,7126,0,7235,1275,608,0 +libesp_hw_support.a,187,16,34,4260,0,4497,3884,288,0 +libesp_common.a,0,0,0,0,0,0,53,7287,0 +libvfs.a,308,0,48,0,0,356,5986,393,0 +libdriver.a,64,0,49,0,0,113,3468,600,0 +libnewlib.a,202,0,440,1280,0,1922,1028,344,0 +libesp_timer.a,32,0,28,515,0,575,917,277,0 +libesp_ringbuf.a,0,0,0,873,0,873,0,512,0 +libxtensa.a,1024,0,0,77,0,1101,126,35,0 +libesp_ipc.a,20,0,72,332,0,424,643,241,0 +liblog.a,8,0,272,247,0,527,499,122,0 +libapp_update.a,1,0,12,194,0,207,179,125,256 +libbootloader_support.a,0,0,0,444,0,444,95,0,0 +libmain.a,0,0,0,0,0,0,228,232,0 +libxt_hal.a,0,0,0,405,0,405,0,32,0 +libpthread.a,8,0,12,0,0,20,310,0,0 +no-rtti\libgcc.a,0,0,0,0,0,0,0,160,0 +libesp_rom.a,0,0,0,24,0,24,0,0,0 +(exe),0,0,0,0,3,3,3,12,0 +libesp_pm.a,0,0,0,0,0,0,8,0,0 +libcxx.a,0,0,0,0,0,0,5,0,0 +libmbedcrypto.a,0,0,0,0,0,0,0,0,0 +libsoc.a,0,0,0,0,0,0,0,0,0 +Total sizes:,,, +Used static IRAM,46786 bytes (239934 remain 16.3% used),,, +.text size,45759 bytes,,, +.vectors size,1027 bytes,,, +Used stat D/IRAM,11772 bytes (123396 remain 8.7% used),,, +.data size,9252 bytes,,, +.bss size,2520 bytes,,, +Used Flash size ,114851 bytes,,, +.text,87463 bytes,,, +.rodata,27132 bytes,,, +Total image size,170889 bytes (.bin may be padded larger),,, +Per-file contributions to ELF file: +Object File,DRAM .data,.rtc.data,DRAM .bss,IRAM0 .text,& 0.vectors,ram_st_total,Flash .text,& .rodata,& .appdesc +lib_a-vfprintf.o,0,0,0,0,0,0,13707,700,0 +lib_a-svfprintf.o,0,0,0,0,0,0,13331,752,0 +lib_a-svfiprintf.o,0,0,0,0,0,0,9650,1172,0 +lib_a-vfiprintf.o,0,0,0,0,0,0,9827,700,0 +tasks.c.obj,8,0,704,6792,0,7504,0,1158,0 +esp_err_to_name.c.obj,0,0,0,0,0,0,53,7287,0 +heap_tlsf.c.obj,1796,0,0,3591,0,5387,0,0,0 +queue.c.obj,0,0,0,3038,0,3038,0,1515,0 +vfs_uart.c.obj,116,0,8,0,0,124,4051,282,0 +lib_a-dtoa.o,0,0,0,0,0,0,3592,165,0 +portasm.S.obj,3084,0,0,416,0,3500,0,0,0 +spi_flash_chip_generic.c,554,0,0,2529,0,3083,0,0,0 +intr_alloc.c.obj,8,0,22,717,0,747,1958,198,0 +lib_a-mprec.o,0,0,0,0,0,0,2340,409,0 +uart.c.obj,56,0,12,0,0,68,2091,511,0 +panic_arch.c.obj,0,0,0,0,0,0,715,1538,0 +spi_flash_hal_iram.c.obj,0,0,0,2250,0,2250,0,0,0 +vfs.c.obj,192,0,40,0,0,232,1935,111,0 +rtc_clk.c.obj,171,0,8,2059,0,2238,0,0,0 +xtensa_vectors.S.obj,32,0,0,1464,425,1921,0,48,0 +task_wdt.c.obj,53,0,12,0,0,65,1319,591,0 +spi_flash_hal_gpspi.c.ob,0,0,0,1842,0,1842,0,0,0 +rtc_init.c.obj,0,0,0,0,0,0,1703,70,0 +esp_flash_api.c.obj,20,0,0,862,0,882,89,762,0 +flash_mmap.c.obj,0,0,520,1298,0,1818,166,240,0 +port.c.obj,0,0,24,945,0,969,147,541,0 +heap_caps.c.obj,4,0,4,1003,0,1011,261,355,0 +wdt_hal_iram.c.obj,0,0,0,1493,0,1493,0,0,0 +periph_ctrl.c.obj,8,0,37,0,0,45,1377,85,0 +cpu_start.c.obj,0,0,5,732,0,737,371,334,0 +ringbuf.c.obj,0,0,0,873,0,873,0,512,0 +cache_utils.c.obj,4,0,14,685,0,703,92,570,0 +heap_caps_init.c.obj,0,0,4,0,0,4,905,430,0 +startup.c.obj,8,0,11,69,0,88,748,505,0 +locks.c.obj,8,0,168,782,0,958,122,344,0 +partition.c.obj,0,0,8,0,0,8,938,268,0 +systimer_hal.c.obj,85,0,0,1052,0,1137,0,0,0 +xtensa_intr_asm.S.obj,1024,0,0,51,0,1075,0,0,0 +panic.c.obj,12,0,5,12,0,29,875,147,0 +memspi_host_driver.c.obj,397,0,0,637,0,1034,0,0,0 +clk.c.obj,0,0,0,0,0,0,802,212,0 +esp_timer.c.obj,8,0,8,282,0,298,505,72,0 +memory_layout_utils.c.ob,0,0,0,0,0,0,575,283,0 +debug_helpers.c.obj,0,0,0,747,0,747,0,73,0 +lib_a-fseeko.o,0,0,0,0,0,0,818,0,0 +spi_flash_chip_winbond.c,136,0,0,659,0,795,0,0,0 +multi_heap.c.obj,157,0,0,601,0,758,0,0,0 +esp_ipc.c.obj,0,0,56,188,0,244,456,97,0 +lib_a-fvwrite.o,0,0,0,0,0,0,721,0,0 +panic_handler.c.obj,8,0,8,66,0,82,634,8,0 +lib_a-findfp.o,0,0,0,0,0,0,612,96,0 +rtc_time.c.obj,0,0,0,675,0,675,0,0,0 +log.c.obj,8,0,264,42,0,314,499,122,0 +time.c.obj,0,0,20,127,0,147,509,0,0 +esp_timer_impl_systimer.,24,0,12,198,0,234,286,125,0 +port_systick.c.obj,0,0,12,394,0,406,0,192,0 +esp_flash_spi_init.c.obj,68,0,4,0,0,72,243,261,0 +lib_a-fflush.o,0,0,0,0,0,0,552,0,0 +interrupt_descriptor_tab,0,0,0,0,0,0,12,512,0 +spi_flash_os_func_app.c.,52,0,0,324,0,376,44,95,0 +crosscore_int.c.obj,8,0,8,229,0,245,142,120,0 +system_internal.c.obj,0,0,0,475,0,475,0,16,0 +esp_app_desc.c.obj,1,0,8,194,0,203,31,4,256 +rtc_sleep.c.obj,0,0,0,476,0,476,0,0,0 +hello_world_main.c.obj,0,0,0,0,0,0,228,232,0 +port_common.c.obj,0,0,8,98,0,106,146,214,0 +spi_flash_hal.c.obj,0,0,0,0,0,0,351,96,0 +bootloader_flash.c.obj,0,0,0,444,0,444,0,0,0 +uart_hal.c.obj,0,0,0,0,0,0,432,0,0 +xtensa_context.S.obj,0,0,0,390,0,390,0,0,0 +lib_a-locale.o,4,0,0,0,0,4,0,374,0 +esp_ipc_isr.c.obj,4,0,16,19,0,39,187,144,0 +spi_flash_chip_gd.c.obj,123,0,0,202,0,325,0,0,0 +memory_layout.c.obj,0,0,0,0,0,0,0,315,0 +lib_a-refill.o,0,0,0,0,0,0,312,0,0 +windowspill_asm.o,0,0,0,311,0,311,0,0,0 +freertos_hooks.c.obj,8,0,128,47,0,183,247,0,0 +esp_time_impl.c.obj,0,0,12,0,0,12,281,0,0 +lib_a-ftello.o,0,0,0,0,0,0,278,0,0 +lib_a-fclose.o,0,0,0,0,0,0,270,0,0 +esp_ota_ops.c.obj,0,0,4,0,0,4,148,121,0 +lib_a-makebuf.o,0,0,0,0,0,0,263,0,0 +spi_flash_chip_mxic.c.ob,190,0,0,70,0,260,0,0,0 +soc_hal.c.obj,24,0,0,234,0,258,0,0,0 +lib_a-ctype_.o,0,0,0,0,0,0,0,257,0 +lib_a-reent.o,0,0,0,0,0,0,252,0,0 +esp_err.c.obj,108,0,0,140,0,248,0,0,0 +brownout_hal.c.obj,0,0,0,0,0,0,244,0,0 +int_wdt.c.obj,0,0,9,90,0,99,152,0,0 +system_time.c.obj,0,0,8,35,0,43,126,80,0 +esp_clk.c.obj,0,16,4,25,0,45,194,0,0 +spi_flash_chip_issi.c.ob,125,0,0,108,0,233,0,0,0 +newlib_init.c.obj,156,0,240,0,0,396,73,0,0 +lib_a-wsetup.o,0,0,0,0,0,0,223,0,0 +pthread_local_storage.c.,8,0,4,0,0,12,213,0,0 +lib_a-snprintf.o,0,0,0,0,0,0,217,0,0 +lib_a-fopen.o,0,0,0,0,0,0,216,0,0 +spi_flash_encrypt_hal_ir,0,0,0,213,0,213,0,0,0 +log_freertos.c.obj,0,0,8,205,0,213,0,0,0 +abort.c.obj,38,0,0,157,0,195,0,0,0 +lib_a-puts.o,0,0,0,0,0,0,190,0,0 +xtensa_intr.c.obj,0,0,0,26,0,26,126,35,0 +lib_a-stdio.o,0,0,0,0,0,0,182,0,0 +regi2c_ctrl.c.obj,8,0,0,171,0,179,0,0,0 +spi_flash_chip_boya.c.ob,125,0,0,52,0,177,0,0,0 +list.c.obj,0,0,0,164,0,164,0,0,0 +cpu_util.c.obj,0,0,0,137,0,137,0,20,0 +heap.c.obj,0,0,0,151,0,151,0,0,0 +highint_hdl.S.obj,0,0,0,147,0,147,0,0,0 +esp_ipc_isr_handler.S.ob,16,0,0,125,0,141,0,0,0 +lib_a-assert.o,0,0,0,0,0,0,72,60,0 +lib_a-flags.o,0,0,0,0,0,0,128,0,0 +esp_system.c.obj,0,0,20,56,0,76,70,0,0 +lib_a-fwalk.o,0,0,0,0,0,0,119,0,0 +lib_a-printf.o,0,0,0,0,0,0,112,0,0 +spi_flash_os_func_noos.c,36,0,0,72,0,108,0,0,0 +uart_hal_iram.c.obj,0,0,0,0,0,0,105,0,0 +lib_a-s_frexp.o,0,0,0,0,0,0,100,0,0 +flash_ops.c.obj,24,0,4,41,0,69,33,0,0 +pthread.c.obj,0,0,8,0,0,8,97,0,0 +lib_a-vprintf.o,0,0,0,0,0,0,94,0,0 +cache_err_int.c.obj,0,0,0,7,0,7,78,0,0 +lib_a-fiprintf.o,0,0,0,0,0,0,84,0,0 +mpu_hal.c.obj,0,0,0,0,0,0,72,0,0 +panic_handler_asm.S.obj,0,0,0,66,0,66,0,0,0 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+lib_a-errno.o,0,0,0,0,0,0,13,0,0 +pthread.c.obj,0,0,0,0,0,0,12,0,0 +crtend.o,0,0,0,0,0,0,0,8,0 +pm_impl.c.obj,0,0,0,0,0,0,8,0,0 +crti.o,0,0,0,0,3,3,3,0,0 +cxx_guards.cpp.obj,0,0,0,0,0,0,5,0,0 +ubsan.c.obj,0,0,0,5,0,5,0,0,0 +crtbegin.o,0,0,0,0,0,0,0,4,0 +spi_bus_lock.c.obj,0,0,0,0,0,0,0,4,0 +FreeRTOS-openocd.c.obj,4,0,0,0,0,4,0,0,0 +crt0.o,0,0,0,0,0,0,0,0,0 +crtn.o,0,0,0,0,0,0,0,0,0 +project_elf_src_esp32s3.,0,0,0,0,0,0,0,0,0 +bootloader_common.c.obj,0,0,0,0,0,0,0,0,0 +bootloader_common_loader,0,0,0,0,0,0,0,0,0 +bootloader_efuse_esp32s3,0,0,0,0,0,0,0,0,0 +bootloader_random_esp32s,0,0,0,0,0,0,0,0,0 +bootloader_sha.c.obj,0,0,0,0,0,0,0,0,0 +bootloader_utility.c.obj,0,0,0,0,0,0,0,0,0 +esp_image_format.c.obj,0,0,0,0,0,0,0,0,0 +flash_partitions.c.obj,0,0,0,0,0,0,0,0,0 +gdma.c.obj,0,0,0,0,0,0,0,0,0 +gpio.c.obj,0,0,0,0,0,0,0,0,0 +rtc_io.c.obj,0,0,0,0,0,0,0,0,0 +rtc_module.c.obj,0,0,0,0,0,0,0,0,0 +spi_common.c.obj,0,0,0,0,0,0,0,0,0 +dport_access.c.obj,0,0,0,0,0,0,0,0,0 +esp_crypto_lock.c.obj,0,0,0,0,0,0,0,0,0 +esp_ipc_isr_routines.S.o,0,0,0,0,0,0,0,0,0 +pm_locks.c.obj,0,0,0,0,0,0,0,0,0 +gdma_hal.c.obj,0,0,0,0,0,0,0,0,0 +gpio_hal.c.obj,0,0,0,0,0,0,0,0,0 +rtc_io_hal.c.obj,0,0,0,0,0,0,0,0,0 +sha_hal.c.obj,0,0,0,0,0,0,0,0,0 +esp_crypto_shared_gdma.c,0,0,0,0,0,0,0,0,0 +esp_sha256.c.obj,0,0,0,0,0,0,0,0,0 +esp_sha_gdma_impl.c.obj,0,0,0,0,0,0,0,0,0 +sha.c.obj,0,0,0,0,0,0,0,0,0 +gdma_periph.c.obj,0,0,0,0,0,0,0,0,0 +gpio_periph.c.obj,0,0,0,0,0,0,0,0,0 +rtc_io_periph.c.obj,0,0,0,0,0,0,0,0,0 +spi_periph.c.obj,0,0,0,0,0,0,0,0,0 +uart_periph.c.obj,0,0,0,0,0,0,0,0,0 +int_asm--set_intclear.o,0,0,0,0,0,0,0,0,0 +lib_a-bzero.o,0,0,0,0,0,0,0,0,0 +lib_a-environ.o,0,0,4,0,0,4,0,0,0 +lib_a-envlock.o,0,0,0,0,0,0,0,0,0 +lib_a-fprintf.o,0,0,0,0,0,0,0,0,0 +lib_a-fputs.o,0,0,0,0,0,0,0,0,0 +lib_a-fwrite.o,0,0,0,0,0,0,0,0,0 +lib_a-getenv_r.o,0,0,0,0,0,0,0,0,0 +lib_a-gettzinfo.o,0,0,0,0,0,0,0,0,0 +lib_a-gmtime_r.o,0,0,0,0,0,0,0,0,0 +lib_a-impure.o,0,0,0,0,0,0,0,0,0 +lib_a-iswspace.o,0,0,0,0,0,0,0,0,0 +lib_a-iswspace_l.o,0,0,0,0,0,0,0,0,0 +lib_a-itoa.o,0,0,0,0,0,0,0,0,0 +lib_a-lcltime_r.o,0,0,0,0,0,0,0,0,0 +lib_a-mbrtowc.o,0,0,0,0,0,0,0,0,0 +lib_a-memchr.o,0,0,0,0,0,0,0,0,0 +lib_a-memcmp.o,0,0,0,0,0,0,0,0,0 +lib_a-memcpy.o,0,0,0,0,0,0,0,0,0 +lib_a-memmove.o,0,0,0,0,0,0,0,0,0 +lib_a-memset.o,0,0,0,0,0,0,0,0,0 +lib_a-month_lengths.o,0,0,0,0,0,0,0,0,0 +lib_a-qsort.o,0,0,0,0,0,0,0,0,0 +lib_a-sccl.o,0,0,0,0,0,0,0,0,0 +lib_a-siscanf.o,0,0,0,0,0,0,0,0,0 +lib_a-strcat.o,0,0,0,0,0,0,0,0,0 +lib_a-strcmp.o,0,0,0,0,0,0,0,0,0 +lib_a-strcpy.o,0,0,0,0,0,0,0,0,0 +lib_a-strcspn.o,0,0,0,0,0,0,0,0,0 +lib_a-strerror.o,0,0,0,0,0,0,0,0,0 +lib_a-strerror_r.o,0,0,0,0,0,0,0,0,0 +lib_a-strlcat.o,0,0,0,0,0,0,0,0,0 +lib_a-strlcpy.o,0,0,0,0,0,0,0,0,0 +lib_a-strlen.o,0,0,0,0,0,0,0,0,0 +lib_a-strncmp.o,0,0,0,0,0,0,0,0,0 +lib_a-strncpy.o,0,0,0,0,0,0,0,0,0 +lib_a-strstr.o,0,0,0,0,0,0,0,0,0 +lib_a-strtol.o,0,0,0,0,0,0,0,0,0 +lib_a-strtoll.o,0,0,0,0,0,0,0,0,0 +lib_a-strtoul.o,0,0,0,0,0,0,0,0,0 +lib_a-strtoull.o,0,0,0,0,0,0,0,0,0 +lib_a-svfiscanf.o,0,0,0,0,0,0,0,0,0 +lib_a-tzcalc_limits.o,0,0,0,0,0,0,0,0,0 +lib_a-tzlock.o,0,0,0,0,0,0,0,0,0 +lib_a-tzset.o,0,0,0,0,0,0,0,0,0 +lib_a-tzset_r.o,0,0,0,0,0,0,0,0,0 +lib_a-tzvars.o,0,0,0,0,0,0,0,0,0 +lib_a-u_strerr.o,0,0,0,0,0,0,0,0,0 +lib_a-ungetc.o,0,0,0,0,0,0,0,0,0 +lib_a-utoa.o,0,0,0,0,0,0,0,0,0 +_addsubdf3.o,0,0,0,0,0,0,0,0,0 +_bswapdi2.o,0,0,0,0,0,0,0,0,0 +_cmpdf2.o,0,0,0,0,0,0,0,0,0 +_divdf3.o,0,0,0,0,0,0,0,0,0 +_fixdfsi.o,0,0,0,0,0,0,0,0,0 +_floatsidf.o,0,0,0,0,0,0,0,0,0 +_muldf3.o,0,0,0,0,0,0,0,0,0 +Total sizes:,,, +Used static IRAM,46786 bytes (239934 remain 16.3% used),,, +.text size,45759 bytes,,, +.vectors size,1027 bytes,,, +Used stat D/IRAM,11772 bytes (123396 remain 8.7% used),,, +.data size,9252 bytes,,, +.bss size,2520 bytes,,, +Used Flash size ,114851 bytes,,, +.text,87463 bytes,,, +.rodata,27132 bytes,,, +Total image size,170889 bytes (.bin may be padded larger),,, + +Symbols within the archive: libdriver.a (Not all symbols may be reported) + +Symbols from section: .dram0.bss +ref_counts,37 +p_uart_obj,12 +Section total: 49 + +Symbols from section: .dram0.data +uart_context,48 +periph_spinlock,8 +uart_selectlock,8 +Section total: 64 + +Symbols from section: .flash.appdesc +Section total: 0 + +Symbols from section: .flash.rodata +periph_module_enable.str1.4,64 +uart_disable_intr_mask_and_return_prev.str1.4,54 +uart_pattern_pop_pos.str1.4,49 +uart_set_stop_bits.str1.4,46 +uart_set_word_length.str1.4,46 +uart_flush_input.str1.4,45 +__FUNCTION__$8051,39 +__FUNCTION__$8043,27 +__FUNCTION__$7806,22 +__FUNCTION__$7737,21 +__FUNCTION__$7742,21 +__func__$4997,21 +__FUNCTION__$7747,19 +__FUNCTION__$7752,19 +__FUNCTION__$7767,18 +__FUNCTION__$7772,18 +__FUNCTION__$7978,18 +__FUNCTION__$8055,17 +__FUNCTION__$7757,16 +__FUNCTION__$7762,16 +g_spi_lock_main_flash_dev,4 +Section total: 600 + +Symbols from section: .flash.rodata_noload +Section total: 0 + +Symbols from section: .flash.text +periph_module_enable,1131 +uart_flush_input,509 +uart_wait_tx_done,393 +uart_set_stop_bits,130 +uart_set_word_length,130 +periph_ll_get_rst_en_reg,125 +uart_disable_intr_mask_and_return_prev,122 +periph_ll_get_clk_en_reg,121 +uart_get_bufferedlen,108 +uart_enable_intr_mask,100 +uart_get_baudrate,88 +uart_set_parity,88 +uart_set_baudrate,84 +uart_pattern_queue_update,74 +uart_get_parity,68 +uart_get_stop_bits,68 +uart_get_word_length,64 +uart_is_driver_installed,30 +uart_set_select_notif_callback,23 +uart_get_selectlock,12 +Section total: 3468 + +Symbols from section: .iram0.bss +Section total: 0 + +Symbols from section: .iram0.data +Section total: 0 + +Symbols from section: .iram0.text +Section total: 0 + +Symbols from section: .iram0.vectors +Section total: 0 + +Symbols from section: .noinit +Section total: 0 + +Symbols from section: .rtc.bss +Section total: 0 + +Symbols from section: .rtc.data +Section total: 0 + +Symbols from section: .rtc.text +Section total: 0 + +Symbols from section: .rtc_noinit +Section total: 0 + *** Producing JSON file output... *** Producing text file output... +*** +Producing csv file output... + *** Running idf_size_tests.py... Total sizes: diff --git a/tools/test_idf_size/expected_output.csv b/tools/test_idf_size/expected_output.csv new file mode 100644 index 0000000000..a5a9c2f471 --- /dev/null +++ b/tools/test_idf_size/expected_output.csv @@ -0,0 +1,11 @@ +Total sizes:,,, +Used static DRAM,17620 bytes (163116 remain 9.7% used),,, +.data size,9324 bytes,,, +.bss size,8296 bytes,,, +Used static IRAM,38932 bytes (92140 remain 29.7% used),,, +.text size,37908 bytes,,, +.vectors size,1024 bytes,,, +Used Flash size ,186524 bytes,,, +.text,146944 bytes,,, +.rodata,39580 bytes,,, +Total image size,234780 bytes (.bin may be padded larger),,, diff --git a/tools/test_idf_size/expected_output.txt b/tools/test_idf_size/expected_output.txt index e0560f0a54..97243a0f62 100644 --- a/tools/test_idf_size/expected_output.txt +++ b/tools/test_idf_size/expected_output.txt @@ -6,6 +6,6 @@ Used static IRAM: 38932 bytes ( 92140 remain, 29.7% used) .text size: 37908 bytes .vectors size: 1024 bytes Used Flash size : 186524 bytes - .text : 146944 bytes - .rodata : 39580 bytes + .text: 146944 bytes + .rodata: 39580 bytes Total image size: 234780 bytes (.bin may be padded larger) diff --git a/tools/test_idf_size/test.sh b/tools/test_idf_size/test.sh index 0f2956f101..df9da903c2 100755 --- a/tools/test_idf_size/test.sh +++ b/tools/test_idf_size/test.sh @@ -7,7 +7,7 @@ memory_test () { && idf.py set-target $1 \ && idf.py build \ && echo -e "\n***\nRunning mem_test.py for $1..." &>> $IDF_PATH/tools/test_idf_size/output \ - && python -m coverage run -a $IDF_PATH/tools/idf_size.py --json build/hello_world.map > size_output.json \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=json build/hello_world.map > size_output.json \ && python $IDF_PATH/components/esptool_py/esptool/esptool.py --chip $1 image_info build/hello_world.bin > esptool_output \ && python -m coverage run -a $IDF_PATH/tools/test_idf_size/mem_test.py size_output.json esptool_output &>> $IDF_PATH/tools/test_idf_size/output \ && popd @@ -15,10 +15,18 @@ memory_test () { json_test() { echo -e "\n***\nProducing JSON output for $1..." &>> output \ - && python -m coverage run -a $IDF_PATH/tools/idf_size.py --json app_$1.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output \ - && python -m coverage run -a $IDF_PATH/tools/idf_size.py --json --archives app_$1.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output \ - && python -m coverage run -a $IDF_PATH/tools/idf_size.py --json --files app_$1.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output \ - && python -m coverage run -a $IDF_PATH/tools/idf_size.py --json --archive_details libdriver.a app_$1.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=json app_$1.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=json --archives app_$1.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=json --files app_$1.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=json --archive_details libdriver.a app_$1.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output +} + +csv_test() { + echo -e "\n***\nProducing CSV output for $1..." &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=csv app_$1.map &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=csv --archives app_$1.map &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=csv --files app_$1.map &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=csv --archive_details libdriver.a app_$1.map &>> output } { python -m coverage debug sys \ @@ -128,22 +136,37 @@ json_test() { && echo -e "\n***\nRunning idf_size.py --archive_details for esp32s3..." &>> output \ && python -m coverage run -a $IDF_PATH/tools/idf_size.py --target esp32s3 --archive_details libdriver.a app_esp32s3.map &>> output \ && echo -e "\n***\nProducing JSON output..." &>> output \ - && python -m coverage run -a $IDF_PATH/tools/idf_size.py --json app.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output \ - && python -m coverage run -a $IDF_PATH/tools/idf_size.py --json --archives app.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output \ - && python -m coverage run -a $IDF_PATH/tools/idf_size.py --json --files app.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output \ - && python -m coverage run -a $IDF_PATH/tools/idf_size.py --json --archive_details libdriver.a app.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output \ - && python -m coverage run -a $IDF_PATH/tools/idf_size.py --json app.map --diff app2.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output \ - && python -m coverage run -a $IDF_PATH/tools/idf_size.py --json --archives app.map --diff app2.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output \ - && python -m coverage run -a $IDF_PATH/tools/idf_size.py --json --files app.map --diff app2.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output \ - && python -m coverage run -a $IDF_PATH/tools/idf_size.py --json --archive_details libdriver.a app.map --diff app2.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=json app.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=json --archives app.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=json --files app.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=json --archive_details libdriver.a app.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=json app.map --diff app2.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=json --archives app.map --diff app2.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=json --files app.map --diff app2.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=json --archive_details libdriver.a app.map --diff app2.map | python $IDF_PATH/tools/test_idf_size/json_validate_test.py &>> output \ && json_test esp32s2 \ && json_test esp32c3 \ && json_test esp32h2 \ && json_test esp32s3 \ + && echo -e "\n***\nProducing CSV output..." &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=csv app.map &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=csv --archives app.map &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=csv --files app.map &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=csv --archive_details libdriver.a app.map &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=csv app.map --diff app2.map &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=csv --archives app.map --diff app2.map &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=csv --files app.map --diff app2.map &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=csv --archive_details libdriver.a app.map --diff app2.map &>> output \ + && csv_test esp32s2 \ + && csv_test esp32c3 \ + && csv_test esp32h2 \ + && csv_test esp32s3 \ && echo -e "\n***\nProducing JSON file output..." &>> output \ - && python -m coverage run -a $IDF_PATH/tools/idf_size.py --json --output-file output.json app.map &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=json --output-file output.json app.map &>> output \ && echo -e "\n***\nProducing text file output..." &>> output \ && python -m coverage run -a $IDF_PATH/tools/idf_size.py -o output.txt app.map &>> output \ + && echo -e "\n***\nProducing csv file output..." &>> output \ + && python -m coverage run -a $IDF_PATH/tools/idf_size.py --format=csv --output-file output.csv app.map &>> output \ && echo -e "\n***\nRunning idf_size_tests.py..." &>> output \ && python -m coverage run -a $IDF_PATH/tools/test_idf_size/test_idf_size.py &>> output \ && echo -e "\n\nComparing expected output..." \ @@ -152,6 +175,8 @@ json_test() { && diff -Z output.json expected_output.json \ && echo -e "\n\nComparing expected text output..." \ && diff -Z output.txt expected_output.txt \ + && echo -e "\n\nComparing expected csv output..." \ + && diff -Z output.csv expected_output.csv \ && python -m coverage report \ ; } || { echo 'The test for idf_size has failed. Please examine the artifacts.' ; exit 1; } diff --git a/tools/test_idf_tools/test_idf_tools.py b/tools/test_idf_tools/test_idf_tools.py index 6385ceb38a..0dc00d973f 100755 --- a/tools/test_idf_tools/test_idf_tools.py +++ b/tools/test_idf_tools/test_idf_tools.py @@ -38,9 +38,6 @@ except ImportError: import idf_tools ESP32ULP = 'esp32ulp-elf' -ESP32ULP_ARCHIVE = 'binutils-esp32ulp' -ESP32S2ULP = 'esp32s2ulp-elf' -ESP32S2ULP_ARCHIVE = 'binutils-esp32s2ulp' OPENOCD = 'openocd-esp32' RISCV_ELF = 'riscv32-esp-elf' XTENSA_ESP32_ELF = 'xtensa-esp32-elf' @@ -48,6 +45,7 @@ XTENSA_ESP32S2_ELF = 'xtensa-esp32s2-elf' XTENSA_ESP32S3_ELF = 'xtensa-esp32s3-elf' XTENSA_ESP_GDB = 'xtensa-esp-elf-gdb' RISCV_ESP_GDB = 'riscv32-esp-elf-gdb' +ESP_ROM_ELFS = 'esp-rom-elfs' def get_version_dict(): @@ -66,7 +64,6 @@ def get_version_dict(): version_dict = get_version_dict() ESP32ULP_VERSION = version_dict[ESP32ULP] -ESP32S2ULP_VERSION = version_dict[ESP32S2ULP] OPENOCD_VERSION = version_dict[OPENOCD] RISCV_ELF_VERSION = version_dict[RISCV_ELF] XTENSA_ESP32_ELF_VERSION = version_dict[XTENSA_ESP32_ELF] @@ -74,6 +71,7 @@ XTENSA_ESP32S2_ELF_VERSION = version_dict[XTENSA_ESP32S2_ELF] XTENSA_ESP32S3_ELF_VERSION = version_dict[XTENSA_ESP32S3_ELF] XTENSA_ESP_GDB_VERSION = version_dict[XTENSA_ESP_GDB] RISCV_ESP_GDB_VERSION = version_dict[RISCV_ESP_GDB] +ESP_ROM_ELFS_VERSION = version_dict[ESP_ROM_ELFS] class TestUsage(unittest.TestCase): @@ -136,8 +134,6 @@ class TestUsage(unittest.TestCase): output = self.run_idf_tools_with_action(['list']) self.assertIn('* %s:' % ESP32ULP, output) self.assertIn('- %s (recommended)' % ESP32ULP_VERSION, output) - self.assertIn('* %s:' % ESP32S2ULP, output) - self.assertIn('- %s (recommended)' % ESP32S2ULP_VERSION, output) self.assertIn('* %s:' % OPENOCD, output) self.assertIn('- %s (recommended)' % OPENOCD_VERSION, output) self.assertIn('* %s:' % RISCV_ELF, output) @@ -156,16 +152,15 @@ class TestUsage(unittest.TestCase): self.assert_tool_installed(output, XTENSA_ESP32_ELF, XTENSA_ESP32_ELF_VERSION) self.assert_tool_installed(output, XTENSA_ESP32S2_ELF, XTENSA_ESP32S2_ELF_VERSION) self.assert_tool_installed(output, XTENSA_ESP32S3_ELF, XTENSA_ESP32S3_ELF_VERSION) - self.assert_tool_installed(output, ESP32ULP, ESP32ULP_VERSION, ESP32ULP_ARCHIVE) - self.assert_tool_installed(output, ESP32S2ULP, ESP32S2ULP_VERSION, ESP32S2ULP_ARCHIVE) + self.assert_tool_installed(output, ESP32ULP, ESP32ULP_VERSION) self.assert_tool_installed(output, XTENSA_ESP_GDB, XTENSA_ESP_GDB_VERSION) self.assert_tool_installed(output, RISCV_ESP_GDB, RISCV_ESP_GDB_VERSION) + self.assert_tool_installed(output, ESP_ROM_ELFS, ESP_ROM_ELFS_VERSION) self.assertIn('Destination: {}'.format(os.path.join(self.temp_tools_dir, 'dist')), output) self.assertEqual(required_tools_installed, output.count('Done')) output = self.run_idf_tools_with_action(['check']) self.assertIn('version installed in tools directory: ' + ESP32ULP_VERSION, output) - self.assertIn('version installed in tools directory: ' + ESP32S2ULP_VERSION, output) self.assertIn('version installed in tools directory: ' + OPENOCD_VERSION, output) self.assertIn('version installed in tools directory: ' + RISCV_ELF_VERSION, output) self.assertIn('version installed in tools directory: ' + XTENSA_ESP32_ELF_VERSION, output) @@ -173,9 +168,10 @@ class TestUsage(unittest.TestCase): self.assertIn('version installed in tools directory: ' + XTENSA_ESP32S3_ELF_VERSION, output) self.assertIn('version installed in tools directory: ' + XTENSA_ESP_GDB_VERSION, output) self.assertIn('version installed in tools directory: ' + RISCV_ESP_GDB_VERSION, output) + self.assertIn('version installed in tools directory: ' + ESP_ROM_ELFS_VERSION, output) output = self.run_idf_tools_with_action(['export']) - self.assertIn('%s/tools/esp32ulp-elf/%s/esp32ulp-elf-binutils/bin' % + self.assertIn('%s/tools/esp32ulp-elf/%s/esp32ulp-elf/bin' % (self.temp_tools_dir, ESP32ULP_VERSION), output) self.assertIn('%s/tools/xtensa-esp32-elf/%s/xtensa-esp32-elf/bin' % (self.temp_tools_dir, XTENSA_ESP32_ELF_VERSION), output) @@ -183,8 +179,6 @@ class TestUsage(unittest.TestCase): (self.temp_tools_dir, OPENOCD_VERSION), output) self.assertIn('%s/tools/riscv32-esp-elf/%s/riscv32-esp-elf/bin' % (self.temp_tools_dir, RISCV_ELF_VERSION), output) - self.assertIn('%s/tools/esp32s2ulp-elf/%s/esp32s2ulp-elf-binutils/bin' % - (self.temp_tools_dir, ESP32S2ULP_VERSION), output) self.assertIn('%s/tools/xtensa-esp32s2-elf/%s/xtensa-esp32s2-elf/bin' % (self.temp_tools_dir, XTENSA_ESP32S2_ELF_VERSION), output) self.assertIn('%s/tools/xtensa-esp32s3-elf/%s/xtensa-esp32s3-elf/bin' % @@ -193,19 +187,21 @@ class TestUsage(unittest.TestCase): (self.temp_tools_dir, XTENSA_ESP_GDB_VERSION), output) self.assertIn('%s/tools/riscv32-esp-elf-gdb/%s/riscv32-esp-elf-gdb/bin' % (self.temp_tools_dir, RISCV_ESP_GDB_VERSION), output) + self.assertIn('%s/tools/esp-rom-elfs/%s/' % + (self.temp_tools_dir, ESP_ROM_ELFS_VERSION), output) def test_tools_for_esp32(self): - required_tools_installed = 4 + required_tools_installed = 5 output = self.run_idf_tools_with_action(['install', '--targets=esp32']) self.assert_tool_installed(output, XTENSA_ESP32_ELF, XTENSA_ESP32_ELF_VERSION) self.assert_tool_installed(output, OPENOCD, OPENOCD_VERSION) - self.assert_tool_installed(output, ESP32ULP, ESP32ULP_VERSION, ESP32ULP_ARCHIVE) + self.assert_tool_installed(output, ESP32ULP, ESP32ULP_VERSION) self.assert_tool_installed(output, XTENSA_ESP_GDB, XTENSA_ESP_GDB_VERSION) self.assert_tool_not_installed(output, RISCV_ELF, RISCV_ELF_VERSION) self.assert_tool_not_installed(output, XTENSA_ESP32S2_ELF, XTENSA_ESP32S2_ELF_VERSION) self.assert_tool_not_installed(output, XTENSA_ESP32S3_ELF, XTENSA_ESP32S3_ELF_VERSION) - self.assert_tool_not_installed(output, ESP32S2ULP, ESP32S2ULP_VERSION, ESP32S2ULP_ARCHIVE) self.assert_tool_not_installed(output, RISCV_ESP_GDB, RISCV_ESP_GDB_VERSION) + self.assert_tool_installed(output, ESP_ROM_ELFS, ESP_ROM_ELFS_VERSION) self.assertIn('Destination: {}'.format(os.path.join(self.temp_tools_dir, 'dist')), output) self.assertEqual(required_tools_installed, output.count('Done')) @@ -214,9 +210,10 @@ class TestUsage(unittest.TestCase): self.assertIn('version installed in tools directory: ' + XTENSA_ESP32_ELF_VERSION, output) self.assertIn('version installed in tools directory: ' + OPENOCD_VERSION, output) self.assertIn('version installed in tools directory: ' + XTENSA_ESP_GDB_VERSION, output) + self.assertIn('version installed in tools directory: ' + ESP_ROM_ELFS_VERSION, output) output = self.run_idf_tools_with_action(['export']) - self.assertIn('%s/tools/esp32ulp-elf/%s/esp32ulp-elf-binutils/bin' % + self.assertIn('%s/tools/esp32ulp-elf/%s/esp32ulp-elf/bin' % (self.temp_tools_dir, ESP32ULP_VERSION), output) self.assertIn('%s/tools/xtensa-esp32-elf/%s/xtensa-esp32-elf/bin' % (self.temp_tools_dir, XTENSA_ESP32_ELF_VERSION), output) @@ -226,17 +223,17 @@ class TestUsage(unittest.TestCase): (self.temp_tools_dir, XTENSA_ESP_GDB_VERSION), output) self.assertNotIn('%s/tools/riscv32-esp-elf/%s/riscv32-esp-elf/bin' % (self.temp_tools_dir, RISCV_ELF_VERSION), output) - self.assertNotIn('%s/tools/esp32s2ulp-elf/%s/esp32s2ulp-elf-binutils/bin' % - (self.temp_tools_dir, ESP32S2ULP_VERSION), output) self.assertNotIn('%s/tools/xtensa-esp32s2-elf/%s/xtensa-esp32s2-elf/bin' % (self.temp_tools_dir, XTENSA_ESP32S2_ELF_VERSION), output) self.assertNotIn('%s/tools/xtensa-esp32s3-elf/%s/xtensa-esp32s3-elf/bin' % (self.temp_tools_dir, XTENSA_ESP32S3_ELF_VERSION), output) self.assertNotIn('%s/tools/riscv32-esp-elf-gdb/%s/riscv32-esp-elf-gdb/bin' % (self.temp_tools_dir, RISCV_ESP_GDB_VERSION), output) + self.assertIn('%s/tools/esp-rom-elfs/%s/' % + (self.temp_tools_dir, ESP_ROM_ELFS_VERSION), output) def test_tools_for_esp32c3(self): - required_tools_installed = 3 + required_tools_installed = 4 output = self.run_idf_tools_with_action(['install', '--targets=esp32c3']) self.assert_tool_installed(output, OPENOCD, OPENOCD_VERSION) self.assert_tool_installed(output, RISCV_ELF, RISCV_ELF_VERSION) @@ -244,9 +241,9 @@ class TestUsage(unittest.TestCase): self.assert_tool_not_installed(output, XTENSA_ESP32_ELF, XTENSA_ESP32_ELF_VERSION) self.assert_tool_not_installed(output, XTENSA_ESP32S2_ELF, XTENSA_ESP32S2_ELF_VERSION) self.assert_tool_not_installed(output, XTENSA_ESP32S3_ELF, XTENSA_ESP32S3_ELF_VERSION) - self.assert_tool_not_installed(output, ESP32ULP, ESP32ULP_VERSION, ESP32ULP_ARCHIVE) - self.assert_tool_not_installed(output, ESP32S2ULP, ESP32S2ULP_VERSION, ESP32S2ULP_ARCHIVE) + self.assert_tool_not_installed(output, ESP32ULP, ESP32ULP_VERSION) self.assert_tool_not_installed(output, XTENSA_ESP_GDB_VERSION, XTENSA_ESP_GDB_VERSION) + self.assert_tool_installed(output, ESP_ROM_ELFS, ESP_ROM_ELFS_VERSION) self.assertIn('Destination: {}'.format(os.path.join(self.temp_tools_dir, 'dist')), output) self.assertEqual(required_tools_installed, output.count('Done')) @@ -254,55 +251,54 @@ class TestUsage(unittest.TestCase): self.assertIn('version installed in tools directory: ' + OPENOCD_VERSION, output) self.assertIn('version installed in tools directory: ' + RISCV_ELF_VERSION, output) self.assertIn('version installed in tools directory: ' + RISCV_ESP_GDB_VERSION, output) + self.assertIn('version installed in tools directory: ' + ESP_ROM_ELFS_VERSION, output) output = self.run_idf_tools_with_action(['export']) self.assertIn('%s/tools/openocd-esp32/%s/openocd-esp32/bin' % (self.temp_tools_dir, OPENOCD_VERSION), output) self.assertIn('%s/tools/riscv32-esp-elf/%s/riscv32-esp-elf/bin' % (self.temp_tools_dir, RISCV_ELF_VERSION), output) - self.assertNotIn('%s/tools/esp32ulp-elf/%s/esp32ulp-elf-binutils/bin' % + self.assertNotIn('%s/tools/esp32ulp-elf/%s/esp32ulp-elf/bin' % (self.temp_tools_dir, ESP32ULP_VERSION), output) self.assertNotIn('%s/tools/xtensa-esp32-elf/%s/xtensa-esp32-elf/bin' % (self.temp_tools_dir, XTENSA_ESP32_ELF_VERSION), output) - self.assertNotIn('%s/tools/esp32s2ulp-elf/%s/esp32s2ulp-elf-binutils/bin' % - (self.temp_tools_dir, ESP32S2ULP_VERSION), output) self.assertNotIn('%s/tools/xtensa-esp32s2-elf/%s/xtensa-esp32s2-elf/bin' % (self.temp_tools_dir, XTENSA_ESP32S2_ELF_VERSION), output) self.assertNotIn('%s/tools/xtensa-esp32s3-elf/%s/xtensa-esp32s3-elf/bin' % (self.temp_tools_dir, XTENSA_ESP32S3_ELF_VERSION), output) self.assertNotIn('%s/tools/xtensa-esp-elf-gdb/%s/xtensa-esp-elf-gdb/bin' % (self.temp_tools_dir, XTENSA_ESP_GDB_VERSION), output) + self.assertIn('%s/tools/esp-rom-elfs/%s/' % + (self.temp_tools_dir, ESP_ROM_ELFS_VERSION), output) def test_tools_for_esp32s2(self): - required_tools_installed = 5 + required_tools_installed = 6 output = self.run_idf_tools_with_action(['install', '--targets=esp32s2']) self.assert_tool_installed(output, XTENSA_ESP32S2_ELF, XTENSA_ESP32S2_ELF_VERSION) self.assert_tool_installed(output, OPENOCD, OPENOCD_VERSION) self.assert_tool_installed(output, RISCV_ELF, RISCV_ELF_VERSION) + self.assert_tool_installed(output, ESP32ULP, ESP32ULP_VERSION) self.assert_tool_installed(output, XTENSA_ESP_GDB, XTENSA_ESP_GDB_VERSION) + self.assert_tool_installed(output, ESP_ROM_ELFS, ESP_ROM_ELFS_VERSION) self.assert_tool_not_installed(output, RISCV_ESP_GDB, RISCV_ESP_GDB_VERSION) self.assert_tool_not_installed(output, XTENSA_ESP32_ELF, XTENSA_ESP32_ELF_VERSION) self.assert_tool_not_installed(output, XTENSA_ESP32S3_ELF, XTENSA_ESP32S3_ELF_VERSION) - self.assert_tool_not_installed(output, ESP32ULP, ESP32ULP_VERSION, ESP32ULP_ARCHIVE) - self.assert_tool_installed(output, ESP32S2ULP, ESP32S2ULP_VERSION, ESP32S2ULP_ARCHIVE) self.assertIn('Destination: {}'.format(os.path.join(self.temp_tools_dir, 'dist')), output) self.assertEqual(required_tools_installed, output.count('Done')) output = self.run_idf_tools_with_action(['check']) - self.assertIn('version installed in tools directory: ' + ESP32S2ULP_VERSION, output) self.assertIn('version installed in tools directory: ' + OPENOCD_VERSION, output) self.assertIn('version installed in tools directory: ' + XTENSA_ESP32S2_ELF_VERSION, output) self.assertIn('version installed in tools directory: ' + XTENSA_ESP_GDB_VERSION, output) + self.assertIn('version installed in tools directory: ' + ESP_ROM_ELFS_VERSION, output) output = self.run_idf_tools_with_action(['export']) - self.assertIn('%s/tools/esp32s2ulp-elf/%s/esp32s2ulp-elf-binutils/bin' % - (self.temp_tools_dir, ESP32S2ULP_VERSION), output) self.assertIn('%s/tools/xtensa-esp32s2-elf/%s/xtensa-esp32s2-elf/bin' % (self.temp_tools_dir, XTENSA_ESP32S2_ELF_VERSION), output) self.assertIn('%s/tools/openocd-esp32/%s/openocd-esp32/bin' % (self.temp_tools_dir, OPENOCD_VERSION), output) - self.assertNotIn('%s/tools/esp32ulp-elf/%s/esp32ulp-elf-binutils/bin' % - (self.temp_tools_dir, ESP32ULP_VERSION), output) + self.assertIn('%s/tools/esp32ulp-elf/%s/esp32ulp-elf/bin' % + (self.temp_tools_dir, ESP32ULP_VERSION), output) self.assertNotIn('%s/tools/xtensa-esp32-elf/%s/xtensa-esp32-elf/bin' % (self.temp_tools_dir, XTENSA_ESP32_ELF_VERSION), output) self.assertIn('%s/tools/riscv32-esp-elf/%s/riscv32-esp-elf/bin' % @@ -313,19 +309,21 @@ class TestUsage(unittest.TestCase): (self.temp_tools_dir, XTENSA_ESP_GDB_VERSION), output) self.assertNotIn('%s/tools/riscv32-esp-elf-gdb/%s/riscv32-esp-elf-gdb/bin' % (self.temp_tools_dir, RISCV_ESP_GDB_VERSION), output) + self.assertIn('%s/tools/esp-rom-elfs/%s/' % + (self.temp_tools_dir, ESP_ROM_ELFS_VERSION), output) def test_tools_for_esp32s3(self): - required_tools_installed = 5 + required_tools_installed = 6 output = self.run_idf_tools_with_action(['install', '--targets=esp32s3']) self.assert_tool_installed(output, XTENSA_ESP32S3_ELF, XTENSA_ESP32S3_ELF_VERSION) self.assert_tool_installed(output, OPENOCD, OPENOCD_VERSION) self.assert_tool_installed(output, RISCV_ELF, RISCV_ELF_VERSION) + self.assert_tool_installed(output, ESP32ULP, ESP32ULP_VERSION) self.assert_tool_installed(output, XTENSA_ESP_GDB, XTENSA_ESP_GDB_VERSION) + self.assert_tool_installed(output, ESP_ROM_ELFS, ESP_ROM_ELFS_VERSION) self.assert_tool_not_installed(output, RISCV_ESP_GDB, RISCV_ESP_GDB_VERSION) self.assert_tool_not_installed(output, XTENSA_ESP32_ELF, XTENSA_ESP32_ELF_VERSION) self.assert_tool_not_installed(output, XTENSA_ESP32S2_ELF, XTENSA_ESP32S2_ELF_VERSION) - self.assert_tool_not_installed(output, ESP32ULP, ESP32ULP_VERSION, ESP32ULP_ARCHIVE) - self.assert_tool_installed(output, ESP32S2ULP, ESP32S2ULP_VERSION, ESP32S2ULP_ARCHIVE) self.assertIn('Destination: {}'.format(os.path.join(self.temp_tools_dir, 'dist')), output) self.assertEqual(required_tools_installed, output.count('Done')) @@ -334,35 +332,40 @@ class TestUsage(unittest.TestCase): self.assertIn('version installed in tools directory: ' + XTENSA_ESP32S3_ELF_VERSION, output) self.assertIn('version installed in tools directory: ' + XTENSA_ESP_GDB_VERSION, output) self.assertIn('version installed in tools directory: ' + RISCV_ESP_GDB_VERSION, output) + self.assertIn('version installed in tools directory: ' + ESP_ROM_ELFS_VERSION, output) output = self.run_idf_tools_with_action(['export']) self.assertIn('%s/tools/openocd-esp32/%s/openocd-esp32/bin' % (self.temp_tools_dir, OPENOCD_VERSION), output) self.assertIn('%s/tools/xtensa-esp32s3-elf/%s/xtensa-esp32s3-elf/bin' % (self.temp_tools_dir, XTENSA_ESP32S3_ELF_VERSION), output) - self.assertNotIn('%s/tools/esp32ulp-elf/%s/esp32ulp-elf-binutils/bin' % - (self.temp_tools_dir, ESP32ULP_VERSION), output) + self.assertIn('%s/tools/esp32ulp-elf/%s/esp32ulp-elf/bin' % + (self.temp_tools_dir, ESP32ULP_VERSION), output) self.assertNotIn('%s/tools/xtensa-esp32-elf/%s/xtensa-esp32-elf/bin' % (self.temp_tools_dir, XTENSA_ESP32_ELF_VERSION), output) self.assertIn('%s/tools/riscv32-esp-elf/%s/riscv32-esp-elf/bin' % (self.temp_tools_dir, RISCV_ELF_VERSION), output) - self.assertIn('%s/tools/esp32s2ulp-elf/%s/esp32s2ulp-elf-binutils/bin' % - (self.temp_tools_dir, ESP32S2ULP_VERSION), output) self.assertNotIn('%s/tools/xtensa-esp32s2-elf/%s/xtensa-esp32s2-elf/bin' % (self.temp_tools_dir, XTENSA_ESP32S2_ELF_VERSION), output) self.assertIn('%s/tools/xtensa-esp-elf-gdb/%s/xtensa-esp-elf-gdb/bin' % (self.temp_tools_dir, XTENSA_ESP_GDB_VERSION), output) self.assertNotIn('%s/tools/riscv32-esp-elf-gdb/%s/riscv32-esp-elf-gdb/bin' % (self.temp_tools_dir, RISCV_ESP_GDB_VERSION), output) + self.assertIn('%s/tools/esp-rom-elfs/%s/' % + (self.temp_tools_dir, ESP_ROM_ELFS_VERSION), output) def test_uninstall_option(self): self.run_idf_tools_with_action(['install', '--targets=esp32,esp32c3']) output = self.run_idf_tools_with_action(['uninstall', '--dry-run']) self.assertEqual(output, '') + self.assertTrue(os.path.isfile(self.idf_env_json), 'File {} was not found. '.format(self.idf_env_json)) + self.assertNotEqual(os.stat(self.idf_env_json).st_size, 0, 'File {} is empty. '.format(self.idf_env_json)) with open(self.idf_env_json, 'r') as idf_env_file: idf_env_json = json.load(idf_env_file) - idf_env_json['idfInstalled'][idf_env_json['idfSelectedId']]['targets'].remove('esp32') + # outside idf_tools.py we dont know the active idf key, but can determine it since in new idf_env_file is only one record + active_idf_key = list(idf_env_json['idfInstalled'].keys())[0] + idf_env_json['idfInstalled'][active_idf_key]['targets'].remove('esp32') with open(self.idf_env_json, 'w') as w: json.dump(idf_env_json, w) @@ -372,16 +375,13 @@ class TestUsage(unittest.TestCase): output = self.run_idf_tools_with_action(['uninstall', '--dry-run']) self.assertEqual(output, '') - def test_unset(self): + def test_deactivate(self): self.run_idf_tools_with_action(['install']) - self.run_idf_tools_with_action(['export']) - self.assertTrue(os.path.isfile(self.idf_env_json), 'File {} was not found. '.format(self.idf_env_json)) - self.assertNotEqual(os.stat(self.idf_env_json).st_size, 0, 'File {} is empty. '.format(self.idf_env_json)) - with open(self.idf_env_json, 'r') as idf_env_file: - idf_env_json = json.load(idf_env_file) - selected_idf = idf_env_json['idfSelectedId'] - self.assertIn('unset', idf_env_json['idfInstalled'][selected_idf], - 'Unset was not created for active environment in {}.'.format(self.idf_env_json)) + output = self.run_idf_tools_with_action(['export']) + self.assertIn('export IDF_DEACTIVATE_FILE_PATH=', output, 'No IDF_DEACTIVATE_FILE_PATH exported into environment') + deactivate_file = re.findall(r'(?:IDF_DEACTIVATE_FILE_PATH=")(.*)(?:")', output)[0] + self.assertTrue(os.path.isfile(deactivate_file), 'File {} was not found. '.format(deactivate_file)) + self.assertNotEqual(os.stat(self.idf_env_json).st_size, 0, 'File {} is empty. '.format(deactivate_file)) class TestMaintainer(unittest.TestCase): diff --git a/tools/test_idf_tools/test_idf_tools_python_env.py b/tools/test_idf_tools/test_idf_tools_python_env.py index 985ae140a0..9c335784aa 100644 --- a/tools/test_idf_tools/test_idf_tools_python_env.py +++ b/tools/test_idf_tools/test_idf_tools_python_env.py @@ -1,6 +1,7 @@ # SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 +import inspect import os import shutil import subprocess @@ -33,8 +34,13 @@ class TestPythonInstall(unittest.TestCase): def run_idf_tools(self, extra_args): # type: (List[str]) -> str args = [sys.executable, '../idf_tools.py'] + extra_args - ret = subprocess.run(args, stdout=subprocess.PIPE, stderr=subprocess.STDOUT, timeout=120) - return ret.stdout.decode('utf-8', 'ignore') + ret = subprocess.run(args, stdout=subprocess.PIPE, stderr=subprocess.STDOUT, timeout=300) + decoded_output = ret.stdout.decode('utf-8', 'ignore') + with open(os.path.join(IDF_PATH, 'tools', 'test_idf_tools', 'test_python_env_logs.txt'), 'a+') as w: + # stack() returns list of callers frame records. [1] represent caller of this function + w.write('============================= ' + inspect.stack()[1].function + ' =============================\n') + w.write(decoded_output) + return decoded_output def test_default_arguments(self): # type: () -> None output = self.run_idf_tools(['check-python-dependencies']) diff --git a/tools/toolchain_versions.mk b/tools/toolchain_versions.mk deleted file mode 100644 index 779475fc8b..0000000000 --- a/tools/toolchain_versions.mk +++ /dev/null @@ -1,6 +0,0 @@ -SUPPORTED_TOOLCHAIN_COMMIT_DESC = esp-2022r1-RC1 -SUPPORTED_TOOLCHAIN_GCC_VERSIONS = 11.2.0 - -CURRENT_TOOLCHAIN_COMMIT_DESC = esp-2022r1-RC1 -CURRENT_TOOLCHAIN_COMMIT_DESC_SHORT = esp-2022r1-RC1 -CURRENT_TOOLCHAIN_GCC_VERSION = 11.2.0 diff --git a/tools/tools.json b/tools/tools.json index bc9151c714..726336314c 100644 --- a/tools/tools.json +++ b/tools/tools.json @@ -26,51 +26,51 @@ "versions": [ { "linux-amd64": { - "sha256": "f78d520a4302f87a21966486898f44848be390d7b2f734bec0bad00f074295d9", - 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"esp32ulp-elf-binutils", + "esp32ulp-elf", "bin" ] ], "export_vars": {}, - "info_url": "https://github.com/espressif/binutils-esp32ulp", + "info_url": "https://github.com/espressif/binutils-gdb", "install": "always", - "license": "GPL-2.0-or-later", + "license": "GPL-3.0-or-later", "name": "esp32ulp-elf", - "platform_overrides": [ - { - "install": "never", - "platforms": [ - "linux-i686", - "linux-arm64" - ] - } - ], "supported_targets": [ - "esp32" + "esp32", + "esp32s2", + "esp32s3" ], "version_cmd": [ "esp32ulp-elf-as", "--version" ], - "version_regex": "\\(GNU Binutils\\)\\s+([0-9a-z\\.\\-]+)", + "version_regex": "\\(GNU Binutils\\)\\s+([a-z0-9.-_]+)", "versions": [ { "linux-amd64": { - "sha256": "3016c4fc551181175bd9979869bc1d1f28fa8efa25a0e29ad7f833fca4bc03d7", - "size": 8248656, - "url": "https://github.com/espressif/binutils-esp32ulp/releases/download/v2.28.51-esp-20191205/binutils-esp32ulp-linux-amd64-2.28.51-esp-20191205.tar.gz" + "sha256": "b1f7801c3a16162e72393ebb772c0cbfe4d22d907be7c2c2dac168736e9195fd", + "size": 10685282, + "url": "https://github.com/espressif/binutils-gdb/releases/download/esp32ulp-elf-v2.35_20220830/esp32ulp-elf-2.35_20220830-linux-amd64.tar.gz" + }, + "linux-arm64": { + "sha256": "d6671b31bab31b9b13aea25bb7d60f15484cb8bf961ddbf67a62867e5563eae5", + "size": 10052225, + "url": "https://github.com/espressif/binutils-gdb/releases/download/esp32ulp-elf-v2.35_20220830/esp32ulp-elf-2.35_20220830-linux-arm64.tar.gz" }, "linux-armel": { - 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"name": "2.28.51-esp-20191205", + "name": "2.35_20220830", "status": "recommended", "win32": { - "sha256": "bade309353a9f0a4e5cc03bfe84845e33205f05502c4b199195e871ded271ab5", - "size": 12234162, - "url": "https://github.com/espressif/binutils-esp32ulp/releases/download/v2.28.51-esp-20191205/binutils-esp32ulp-win32-2.28.51-esp-20191205.zip" + "sha256": "77344715ea7d7a7a9fd0b27653f880efaf3bcc1ac843f61492d8a0365d91f731", + "size": 14651337, + "url": "https://github.com/espressif/binutils-gdb/releases/download/esp32ulp-elf-v2.35_20220830/esp32ulp-elf-2.35_20220830-win32.zip" }, "win64": { - "sha256": "bade309353a9f0a4e5cc03bfe84845e33205f05502c4b199195e871ded271ab5", - "size": 12234162, - "url": "https://github.com/espressif/binutils-esp32ulp/releases/download/v2.28.51-esp-20191205/binutils-esp32ulp-win32-2.28.51-esp-20191205.zip" - } - } - ] - }, - { - "description": "Toolchain for ESP32-S2 and ESP32-S3 ULP coprocessors", - "export_paths": [ - [ - "esp32s2ulp-elf-binutils", - "bin" - ] - ], - "export_vars": {}, - "info_url": "https://github.com/espressif/binutils-esp32ulp", - "install": "always", - "license": "GPL-2.0-or-later", - "name": "esp32s2ulp-elf", - "platform_overrides": [ - { - "install": "never", - "platforms": [ - "linux-i686", - "linux-arm64" - ] - } - ], - "supported_targets": [ - "esp32s2", - "esp32s3" - ], - "version_cmd": [ - "esp32s2ulp-elf-as", - "--version" - ], - "version_regex": "\\(GNU Binutils\\)\\s+([0-9a-z\\.\\-]+)", - "versions": [ - { - "linux-amd64": { - "sha256": "df7b2ff6c7c718a7cbe3b4b6dbcd68180d835d164d1913bc4698fd3781b9a466", - "size": 8254018, - "url": "https://github.com/espressif/binutils-esp32ulp/releases/download/v2.28.51-esp-20191205/binutils-esp32s2ulp-linux-amd64-2.28.51-esp-20191205.tar.gz" - }, - "linux-armel": { - "sha256": "893b213c8f716d455a6efb2b08b6cf1bc34d08b78ee19c31e82ac44b1b45417e", - "size": 8034624, - "url": "https://github.com/espressif/binutils-esp32ulp/releases/download/v2.28.51-esp-20191205/binutils-esp32s2ulp-linux-armel-2.28.51-esp-20191205.tar.gz" - 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"size": 39070972, - "url": "https://github.com/Kitware/CMake/releases/download/v3.23.1/cmake-3.23.1-windows-x86_64.zip" + "sha256": "b1ad8c2dbf0778e3efcc9fd61cd4a962e5c1af40aabdebee3d5074bcff2e103c", + "size": 40212531, + "url": "https://github.com/Kitware/CMake/releases/download/v3.24.0/cmake-3.24.0-windows-x86_64.zip" }, "win64": { - "sha256": "9b509cc4eb7191dc128cfa3f2170036f9cbc7d9d5f93ff7fafc5b2d77b3b40dc", - "size": 39070972, - "url": "https://github.com/Kitware/CMake/releases/download/v3.23.1/cmake-3.23.1-windows-x86_64.zip" + "sha256": "b1ad8c2dbf0778e3efcc9fd61cd4a962e5c1af40aabdebee3d5074bcff2e103c", + "size": 40212531, + "url": "https://github.com/Kitware/CMake/releases/download/v3.24.0/cmake-3.24.0-windows-x86_64.zip" } }, { @@ -946,7 +872,7 @@ "description": "Ccache (compiler cache)", "export_paths": [ [ - "ccache-4.3-windows-64" + "ccache-4.6.2-windows-x86_64" ] ], "export_vars": { @@ -974,12 +900,12 @@ "version_regex": "ccache version ([0-9.]+)", "versions": [ { - "name": "4.3", + "name": "4.6.2", "status": "recommended", "win64": { - "sha256": "a9cacae73c3906d8193456328bee74f7748cb1559a32eaced9ee78eadd416105", - "size": 1550675, - "url": "https://github.com/ccache/ccache/releases/download/v4.3/ccache-4.3-windows-64.zip" + "sha256": "bf230b0936962eae43a3410d6477a7d0b9308e29f89a3091881d22e2502604c5", + "size": 1957177, + "url": "https://github.com/ccache/ccache/releases/download/v4.6.2/ccache-4.6.2-windows-x86_64.zip" } } ] @@ -1024,6 +950,40 @@ } } ] + }, + { + "description": "ESP ROM ELFs", + "export_paths": [ + [ + "" + ] + ], + "export_vars": { + "ESP_ROM_ELF_DIR": "${TOOL_PATH}/" + }, + "info_url": "https://github.com/espressif/esp-rom-elfs", + "install": "always", + "is_executable": false, + "license": "Apache-2.0", + "name": "esp-rom-elfs", + "supported_targets": [ + "all" + ], + "version_cmd": [ + "" + ], + "version_regex": "", + "versions": [ + { + "any": { + "sha256": "add4bedbdd950c8409ff45bbf5610316e7d14c4635ea6906f057f2183ab3e3e9", + "size": 2454730, + "url": "https://github.com/espressif/esp-rom-elfs/releases/download/20220823/esp-rom-elfs-20220823.tar.gz" + }, + "name": "20220823", + "status": "recommended" + } + ] } ], "version": 1 diff --git a/tools/tools_schema.json b/tools/tools_schema.json index f09044d622..51775970f6 100644 --- a/tools/tools_schema.json +++ b/tools/tools_schema.json @@ -47,6 +47,10 @@ "$ref": "#/definitions/installRequirementInfo", "description": "If 'always', the tool will be installed by default. If 'on_request', tool will be installed when specifically requested. If 'never', tool will not be considered for installation." }, + "is_executable": { + "description": "If false - tool does not contain executables. The version will not be checked but export_vars applied.", + "type": "boolean" + }, "license": { "description": "License name. Use SPDX license identifier if it exists, short name of the license otherwise.", "type": "string" diff --git a/tools/unit-test-app/components/test_utils/memory_checks.c b/tools/unit-test-app/components/test_utils/memory_checks.c index f845eab5ca..170f4ca926 100644 --- a/tools/unit-test-app/components/test_utils/memory_checks.c +++ b/tools/unit-test-app/components/test_utils/memory_checks.c @@ -82,6 +82,11 @@ static void check_leak(size_t before_free, if (leaked <= warn_threshold) { return; } + else { + printf("The test leaked more memory than warn threshold: Leaked: %d Warn threshold: -%u \n", + leaked, + warn_threshold); + } printf("MALLOC_CAP_%s %s leak: Before %u bytes free, After %u bytes free (delta %u)\n", type, diff --git a/components/heap/test/test_leak.c b/tools/unit-test-app/components/test_utils/test/leak_test.c similarity index 57% rename from components/heap/test/test_leak.c rename to tools/unit-test-app/components/test_utils/test/leak_test.c index 0144cd937e..46b783507c 100644 --- a/components/heap/test/test_leak.c +++ b/tools/unit-test-app/components/test_utils/test/leak_test.c @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ /* Tests for a leak tag */ @@ -16,23 +21,23 @@ static char* check_calloc(int size) return arr; } -TEST_CASE("Check for leaks (no leak)", "[heap]") +TEST_CASE("Check for leaks (no leak)", "[test_utils]") { char *arr = check_calloc(1000); free(arr); } -TEST_CASE("Check for leaks (leak)", "[heap][ignore]") +TEST_CASE("Check for leaks (leak)", "[test_utils][ignore]") { check_calloc(1000); } -TEST_CASE("Not check for leaks", "[heap][leaks]") +TEST_CASE("Not check for leaks", "[test_utils][leaks]") { check_calloc(1000); } -TEST_CASE("Set a leak level = 7016", "[heap][leaks=7016]") +TEST_CASE("Set a leak level = 7016", "[test_utils][leaks=7016]") { check_calloc(7000); } @@ -42,9 +47,9 @@ static void test_fn(void) check_calloc(1000); } -TEST_CASE_MULTIPLE_STAGES("Not check for leaks in MULTIPLE_STAGES mode", "[heap][leaks]", test_fn, test_fn, test_fn); +TEST_CASE_MULTIPLE_STAGES("Not check for leaks in MULTIPLE_STAGES mode", "[test_utils][leaks]", test_fn, test_fn, test_fn); -TEST_CASE_MULTIPLE_STAGES("Check for leaks in MULTIPLE_STAGES mode (leak)", "[heap][ignore]", test_fn, test_fn, test_fn); +TEST_CASE_MULTIPLE_STAGES("Check for leaks in MULTIPLE_STAGES mode (leak)", "[test_utils][ignore]", test_fn, test_fn, test_fn); static void test_fn2(void) { @@ -57,4 +62,4 @@ static void test_fn3(void) check_calloc(1000); } -TEST_CASE_MULTIPLE_STAGES("Check for leaks in MULTIPLE_STAGES mode (manual reset)", "[heap][leaks][reset=SW_CPU_RESET, SW_CPU_RESET]", test_fn2, test_fn2, test_fn3); +TEST_CASE_MULTIPLE_STAGES("Check for leaks in MULTIPLE_STAGES mode (manual reset)", "[test_utils][leaks][reset=SW_CPU_RESET, SW_CPU_RESET]", test_fn2, test_fn2, test_fn3); diff --git a/tools/unit-test-app/components/test_utils/test_runner.c b/tools/unit-test-app/components/test_utils/test_runner.c index f9e1422361..79e918544e 100644 --- a/tools/unit-test-app/components/test_utils/test_runner.c +++ b/tools/unit-test-app/components/test_utils/test_runner.c @@ -58,6 +58,7 @@ void setUp(void) test_utils_record_free_mem(); test_utils_set_leak_level(CONFIG_UNITY_CRITICAL_LEAK_LEVEL_GENERAL, ESP_LEAK_TYPE_CRITICAL, ESP_COMP_LEAK_GENERAL); test_utils_set_leak_level(CONFIG_UNITY_WARN_LEAK_LEVEL_GENERAL, ESP_LEAK_TYPE_WARNING, ESP_COMP_LEAK_GENERAL); + test_utils_set_leak_level(0, ESP_LEAK_TYPE_CRITICAL, ESP_COMP_LEAK_LWIP); } typedef enum { diff --git a/tools/unit-test-app/configs/aes_no_hw b/tools/unit-test-app/configs/aes_no_hw deleted file mode 100644 index 43b13b84a0..0000000000 --- a/tools/unit-test-app/configs/aes_no_hw +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_IDF_TARGET="esp32" -TEST_EXCLUDE_COMPONENTS=bt app_update test_utils -TEST_COMPONENTS=mbedtls -CONFIG_MBEDTLS_HARDWARE_AES=n -CONFIG_MBEDTLS_MPI_USE_INTERRUPT=n diff --git a/tools/unit-test-app/configs/aes_no_hw_c3 b/tools/unit-test-app/configs/aes_no_hw_c3 deleted file mode 100644 index 0c4c811177..0000000000 --- a/tools/unit-test-app/configs/aes_no_hw_c3 +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_IDF_TARGET="esp32c3" -TEST_EXCLUDE_COMPONENTS=bt app_update test_utils -TEST_COMPONENTS=mbedtls -CONFIG_MBEDTLS_HARDWARE_AES=n -CONFIG_MBEDTLS_MPI_USE_INTERRUPT=n diff --git a/tools/unit-test-app/configs/aes_no_hw_s2 b/tools/unit-test-app/configs/aes_no_hw_s2 deleted file mode 100644 index d180c5169d..0000000000 --- a/tools/unit-test-app/configs/aes_no_hw_s2 +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_IDF_TARGET="esp32s2" -TEST_EXCLUDE_COMPONENTS=bt app_update test_utils -TEST_COMPONENTS=mbedtls -CONFIG_MBEDTLS_HARDWARE_AES=n -CONFIG_MBEDTLS_MPI_USE_INTERRUPT=n diff --git a/tools/unit-test-app/configs/aes_no_hw_s3 b/tools/unit-test-app/configs/aes_no_hw_s3 deleted file mode 100644 index a33e4669aa..0000000000 --- a/tools/unit-test-app/configs/aes_no_hw_s3 +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_IDF_TARGET="esp32s3" -TEST_EXCLUDE_COMPONENTS=bt app_update test_utils -TEST_COMPONENTS=mbedtls -CONFIG_MBEDTLS_HARDWARE_AES=n -CONFIG_MBEDTLS_MPI_USE_INTERRUPT=n diff --git a/tools/unit-test-app/configs/default b/tools/unit-test-app/configs/default index b3048b444d..8738fb2b14 100644 --- a/tools/unit-test-app/configs/default +++ b/tools/unit-test-app/configs/default @@ -1,5 +1,5 @@ # This config is split between targets since different component needs to be included (esp32, esp32s2) # IRAM is full... split some component to default_32_2 CONFIG_IDF_TARGET="esp32" -TEST_COMPONENTS=freertos esp_hw_support esp_ipc esp_system esp_timer driver heap +TEST_COMPONENTS=freertos esp_hw_support esp_ipc esp_system esp_timer driver CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD=y diff --git a/tools/unit-test-app/configs/default_2 b/tools/unit-test-app/configs/default_2 index 95651230a2..4d29040218 100644 --- a/tools/unit-test-app/configs/default_2 +++ b/tools/unit-test-app/configs/default_2 @@ -1,3 +1,3 @@ # This config is split between targets since different component needs to be excluded (esp32, esp32s2) CONFIG_IDF_TARGET="esp32" -TEST_EXCLUDE_COMPONENTS=bt app_update freertos esp_hw_support esp_ipc esp_pm esp_system esp_timer driver heap pthread soc spi_flash vfs test_utils experimental_cpp_component esp-tls +TEST_EXCLUDE_COMPONENTS=bt app_update freertos esp_hw_support esp_ipc esp_pm esp_system esp_timer driver soc spi_flash vfs test_utils experimental_cpp_component diff --git a/tools/unit-test-app/configs/default_2_c2 b/tools/unit-test-app/configs/default_2_c2 index b5b89f39c6..f7639af24c 100644 --- a/tools/unit-test-app/configs/default_2_c2 +++ b/tools/unit-test-app/configs/default_2_c2 @@ -1,3 +1,3 @@ # This config is split between targets since different component needs to be included CONFIG_IDF_TARGET="esp32c2" -TEST_COMPONENTS=app_trace bootloader_support console efuse esp_common esp_eth esp_event esp_hid esp_http_client esp_http_server esp_netif esp_phy esp_ringbuf esp_rom esp_wifi espcoredump hal lwip mbedtls mdns mqtt newlib nvs_flash partition_table protocomm sdmmc spiffs +TEST_COMPONENTS=app_trace efuse esp_common esp_eth esp_event esp_hid esp_netif esp_phy esp_ringbuf esp_wifi espcoredump hal lwip mdns mqtt newlib nvs_flash partition_table sdmmc spiffs diff --git a/tools/unit-test-app/configs/default_2_c3 b/tools/unit-test-app/configs/default_2_c3 index 3bffa218fe..00c6c1f926 100644 --- a/tools/unit-test-app/configs/default_2_c3 +++ b/tools/unit-test-app/configs/default_2_c3 @@ -1,3 +1,3 @@ # This config is split between targets since different component needs to be excluded CONFIG_IDF_TARGET="esp32c3" -TEST_EXCLUDE_COMPONENTS=bt app_update esp_pm freertos esp_hw_support esp_ipc esp_system esp_timer driver heap pthread soc spi_flash vfs lwip spiffs experimental_cpp_component perfmon esp-tls test_utils +TEST_EXCLUDE_COMPONENTS=bt app_update esp_pm freertos esp_hw_support esp_ipc esp_system esp_timer driver soc spi_flash vfs lwip spiffs experimental_cpp_component perfmon test_utils diff --git a/tools/unit-test-app/configs/default_2_s2 b/tools/unit-test-app/configs/default_2_s2 index fd7703e798..0654e9e024 100644 --- a/tools/unit-test-app/configs/default_2_s2 +++ b/tools/unit-test-app/configs/default_2_s2 @@ -1,3 +1,3 @@ # This config is split between targets since different component needs to be excluded (esp32, esp32s2) CONFIG_IDF_TARGET="esp32s2" -TEST_EXCLUDE_COMPONENTS=bt app_update freertos esp_hw_support esp_ipc esp_pm esp_system esp_timer driver heap pthread soc spi_flash vfs experimental_cpp_component esp-tls +TEST_EXCLUDE_COMPONENTS=bt app_update freertos esp_hw_support esp_ipc esp_pm esp_system esp_timer driver soc spi_flash vfs experimental_cpp_component diff --git a/tools/unit-test-app/configs/default_2_s3 b/tools/unit-test-app/configs/default_2_s3 index 9c6dc06a2c..dd1a42050f 100644 --- a/tools/unit-test-app/configs/default_2_s3 +++ b/tools/unit-test-app/configs/default_2_s3 @@ -1,3 +1,3 @@ # This config is split between targets since different component needs to be excluded (esp32, esp32s2) CONFIG_IDF_TARGET="esp32s3" -TEST_EXCLUDE_COMPONENTS=bt app_update freertos esp32s3 esp_ipc esp_pm esp_system esp_timer driver heap pthread soc spi_flash vfs experimental_cpp_component esp-tls test_utils +TEST_EXCLUDE_COMPONENTS=bt app_update freertos esp32s3 esp_ipc esp_pm esp_system esp_timer driver soc spi_flash vfs experimental_cpp_component test_utils diff --git a/tools/unit-test-app/configs/default_32_2 b/tools/unit-test-app/configs/default_32_2 index 4daf14d44d..7195921f25 100644 --- a/tools/unit-test-app/configs/default_32_2 +++ b/tools/unit-test-app/configs/default_32_2 @@ -1,4 +1,4 @@ # continue from default CONFIG_IDF_TARGET="esp32" -TEST_COMPONENTS=pthread soc spi_flash vfs +TEST_COMPONENTS=soc spi_flash vfs CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD=y diff --git a/tools/unit-test-app/configs/default_3_c2 b/tools/unit-test-app/configs/default_3_c2 index af8e5fbf11..7658b217ad 100644 --- a/tools/unit-test-app/configs/default_3_c2 +++ b/tools/unit-test-app/configs/default_3_c2 @@ -1,3 +1,3 @@ # This config is split between targets since different component needs to be included CONFIG_IDF_TARGET="esp32c2" -TEST_EXCLUDE_COMPONENTS=app_trace bootloader_support console efuse esp_common esp_eth esp_event esp_hid esp_http_client esp_http_server esp_netif esp_phy esp_ringbuf esp_rom esp_wifi espcoredump hal lwip mbedtls mdns mqtt newlib nvs_flash partition_table protocomm sdmmc spiffs freertos esp_hw_support esp_ipc esp_system esp_timer driver heap pthread soc spi_flash vfs +TEST_EXCLUDE_COMPONENTS=app_trace efuse esp_common esp_eth esp_event esp_hid esp_netif esp_phy esp_ringbuf esp_wifi espcoredump hal lwip mdns mqtt newlib nvs_flash partition_table sdmmc spiffs freertos esp_hw_support esp_ipc esp_system esp_timer driver soc spi_flash vfs diff --git a/tools/unit-test-app/configs/default_c2 b/tools/unit-test-app/configs/default_c2 index d99387e17e..7009dfe166 100644 --- a/tools/unit-test-app/configs/default_c2 +++ b/tools/unit-test-app/configs/default_c2 @@ -1,3 +1,3 @@ # This config is split between targets since different component needs to be included CONFIG_IDF_TARGET="esp32c2" -TEST_COMPONENTS=freertos esp_hw_support esp_ipc esp_system esp_timer driver heap pthread soc spi_flash vfs +TEST_COMPONENTS=freertos esp_hw_support esp_ipc esp_system esp_timer driver soc spi_flash vfs diff --git a/tools/unit-test-app/configs/default_c3 b/tools/unit-test-app/configs/default_c3 index 199f9b9b73..67c9a75f90 100644 --- a/tools/unit-test-app/configs/default_c3 +++ b/tools/unit-test-app/configs/default_c3 @@ -1,3 +1,3 @@ # This config is split between targets since different component needs to be included CONFIG_IDF_TARGET="esp32c3" -TEST_COMPONENTS=freertos esp_hw_support esp_ipc esp_system esp_timer driver heap pthread +TEST_COMPONENTS=freertos esp_hw_support esp_ipc esp_system esp_timer driver diff --git a/tools/unit-test-app/configs/default_s2_1 b/tools/unit-test-app/configs/default_s2_1 index 3ef5b19050..ec990e29a4 100644 --- a/tools/unit-test-app/configs/default_s2_1 +++ b/tools/unit-test-app/configs/default_s2_1 @@ -1,3 +1,3 @@ # This config is split between targets since different component needs to be included (esp32, esp32s2) CONFIG_IDF_TARGET="esp32s2" -TEST_COMPONENTS=freertos esp_hw_support esp_system esp_timer driver heap +TEST_COMPONENTS=freertos esp_hw_support esp_system esp_timer driver diff --git a/tools/unit-test-app/configs/default_s2_2 b/tools/unit-test-app/configs/default_s2_2 index 2b6e575693..6184e20dd3 100644 --- a/tools/unit-test-app/configs/default_s2_2 +++ b/tools/unit-test-app/configs/default_s2_2 @@ -1,3 +1,3 @@ # This config is split between targets since different component needs to be included (esp32, esp32s2) CONFIG_IDF_TARGET="esp32s2" -TEST_COMPONENTS=pthread soc spi_flash vfs +TEST_COMPONENTS=soc spi_flash vfs diff --git a/tools/unit-test-app/configs/default_s3 b/tools/unit-test-app/configs/default_s3 index ba02479cdd..0d78b2ff2a 100644 --- a/tools/unit-test-app/configs/default_s3 +++ b/tools/unit-test-app/configs/default_s3 @@ -1,3 +1,3 @@ # This config is split between targets since different component needs to be included CONFIG_IDF_TARGET="esp32s3" -TEST_COMPONENTS=freertos esp_hw_support esp_ipc esp_system esp_timer driver heap pthread soc spi_flash vfs +TEST_COMPONENTS=freertos esp_hw_support esp_ipc esp_system esp_timer driver soc spi_flash vfs diff --git a/tools/unit-test-app/configs/esp_tls b/tools/unit-test-app/configs/esp_tls deleted file mode 100644 index 39a2f95ef6..0000000000 --- a/tools/unit-test-app/configs/esp_tls +++ /dev/null @@ -1,5 +0,0 @@ -# As this is protocol specific, only test for one target. -CONFIG_IDF_TARGET="esp32" -TEST_COMPONENTS=esp-tls -TEST_EXCLUDE_COMPONENTS=bt -CONFIG_ESP_TLS_SERVER=y diff --git a/tools/unit-test-app/configs/heap_light_poison_c2 b/tools/unit-test-app/configs/heap_light_poison_c2 deleted file mode 100644 index 1c165b4765..0000000000 --- a/tools/unit-test-app/configs/heap_light_poison_c2 +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_IDF_TARGET="esp32c2" -TEST_COMPONENTS=heap -CONFIG_HEAP_POISONING_COMPREHENSIVE=n -CONFIG_HEAP_POISONING_LIGHT=y diff --git a/tools/unit-test-app/configs/heap_light_poison_c3 b/tools/unit-test-app/configs/heap_light_poison_c3 deleted file mode 100644 index 270ffb6109..0000000000 --- a/tools/unit-test-app/configs/heap_light_poison_c3 +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_IDF_TARGET="esp32c3" -TEST_COMPONENTS=heap -CONFIG_HEAP_POISONING_COMPREHENSIVE=n -CONFIG_HEAP_POISONING_LIGHT=y diff --git a/tools/unit-test-app/configs/mqtt b/tools/unit-test-app/configs/mqtt index 5a131e8de3..7608145d39 100644 --- a/tools/unit-test-app/configs/mqtt +++ b/tools/unit-test-app/configs/mqtt @@ -1,3 +1,3 @@ TEST_COMPONENTS=mqtt CONFIG_MQTT_PROTOCOL_5=y -CONFIG_MQTT5_TEST_BROKER_URI="mqtt://mqtt.eclipseprojects.io" +CONFIG_MQTT5_TEST_BROKER_URI="mqtt://${EXAMPLE_MQTTV5_BROKER_TCP}" diff --git a/tools/unit-test-app/configs/psram b/tools/unit-test-app/configs/psram index af93785ac8..0b5da79b5c 100644 --- a/tools/unit-test-app/configs/psram +++ b/tools/unit-test-app/configs/psram @@ -1,5 +1,5 @@ CONFIG_IDF_TARGET="esp32" -TEST_EXCLUDE_COMPONENTS=bt app_update driver esp_hw_support esp_ipc esp_pm esp_system esp_timer mbedtls spi_flash test_utils heap pthread soc experimental_cpp_component esp-tls freertos sdmmc +TEST_EXCLUDE_COMPONENTS=bt app_update driver esp_hw_support esp_ipc esp_pm esp_system esp_timer spi_flash test_utils soc experimental_cpp_component esp-tls freertos sdmmc CONFIG_SPIRAM=y CONFIG_ESP_INT_WDT_TIMEOUT_MS=800 CONFIG_SPIRAM_OCCUPY_NO_HOST=y diff --git a/tools/unit-test-app/configs/psram_2 b/tools/unit-test-app/configs/psram_2 index 401588ab20..c95fbb5015 100644 --- a/tools/unit-test-app/configs/psram_2 +++ b/tools/unit-test-app/configs/psram_2 @@ -1,5 +1,5 @@ CONFIG_IDF_TARGET="esp32" -TEST_COMPONENTS=esp_hw_support esp_ipc esp_system esp_timer mbedtls spi_flash heap pthread soc +TEST_COMPONENTS=esp_hw_support esp_ipc esp_system esp_timer spi_flash soc CONFIG_SPIRAM=y CONFIG_ESP_INT_WDT_TIMEOUT_MS=800 CONFIG_SPIRAM_OCCUPY_NO_HOST=y diff --git a/tools/unit-test-app/configs/psram_all_ext_2 b/tools/unit-test-app/configs/psram_all_ext_2 index f1d455e5a3..9106054015 100644 --- a/tools/unit-test-app/configs/psram_all_ext_2 +++ b/tools/unit-test-app/configs/psram_all_ext_2 @@ -1,5 +1,5 @@ CONFIG_IDF_TARGET="esp32" -TEST_COMPONENTS=heap mbedtls soc spi_flash +TEST_COMPONENTS=soc spi_flash CONFIG_SPIRAM=y CONFIG_ESP_INT_WDT_TIMEOUT_MS=800 CONFIG_SPIRAM_OCCUPY_NO_HOST=y diff --git a/tools/unit-test-app/configs/psram_s2_base b/tools/unit-test-app/configs/psram_s2_base index c40a661415..b9faef087c 100644 --- a/tools/unit-test-app/configs/psram_s2_base +++ b/tools/unit-test-app/configs/psram_s2_base @@ -1,3 +1,3 @@ CONFIG_IDF_TARGET="esp32s2" -TEST_COMPONENTS=esp_hw_support mbedtls esp_system +TEST_COMPONENTS=esp_hw_support esp_system CONFIG_SPIRAM=y diff --git a/tools/unit-test-app/configs/psram_s3_base b/tools/unit-test-app/configs/psram_s3_base index bf9a2e9dba..898ea06ce5 100644 --- a/tools/unit-test-app/configs/psram_s3_base +++ b/tools/unit-test-app/configs/psram_s3_base @@ -1,3 +1,3 @@ CONFIG_IDF_TARGET="esp32s3" -TEST_COMPONENTS=esp_hw_support mbedtls esp_system +TEST_COMPONENTS=esp_hw_support esp_system CONFIG_SPIRAM=y diff --git a/tools/unit-test-app/configs/release b/tools/unit-test-app/configs/release index d9047f3af3..c48959fc34 100644 --- a/tools/unit-test-app/configs/release +++ b/tools/unit-test-app/configs/release @@ -1,5 +1,5 @@ CONFIG_IDF_TARGET="esp32" -TEST_COMPONENTS=freertos esp_hw_support esp_system esp_ipc esp_timer driver heap pthread soc spi_flash vfs +TEST_COMPONENTS=freertos esp_hw_support esp_system esp_ipc esp_timer driver soc spi_flash vfs CONFIG_COMPILER_OPTIMIZATION_SIZE=y CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y diff --git a/tools/unit-test-app/configs/release_2 b/tools/unit-test-app/configs/release_2 index dc94dfb218..da9ea704a4 100644 --- a/tools/unit-test-app/configs/release_2 +++ b/tools/unit-test-app/configs/release_2 @@ -1,6 +1,6 @@ # This config is split between targets since different component needs to be included (esp32, esp32s2) CONFIG_IDF_TARGET="esp32" -TEST_EXCLUDE_COMPONENTS=bt app_update freertos esp_hw_support esp_ipc esp_pm esp_system esp_timer driver heap pthread soc spi_flash vfs test_utils experimental_cpp_component esp-tls +TEST_EXCLUDE_COMPONENTS=bt app_update freertos esp_hw_support esp_ipc esp_pm esp_system esp_timer driver soc spi_flash vfs test_utils experimental_cpp_component CONFIG_COMPILER_OPTIMIZATION_SIZE=y CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y diff --git a/tools/unit-test-app/configs/release_2_s2 b/tools/unit-test-app/configs/release_2_s2 index e6ccd822d1..baf847dfed 100644 --- a/tools/unit-test-app/configs/release_2_s2 +++ b/tools/unit-test-app/configs/release_2_s2 @@ -1,6 +1,6 @@ # This config is split between targets since different component needs to be excluded (esp32, esp32s2) CONFIG_IDF_TARGET="esp32s2" -TEST_EXCLUDE_COMPONENTS=bt app_update freertos esp_hw_support esp_ipc esp_pm esp_system esp_timer driver heap pthread soc spi_flash vfs test_utils experimental_cpp_component +TEST_EXCLUDE_COMPONENTS=bt app_update freertos esp_hw_support esp_ipc esp_pm esp_system esp_timer driver soc spi_flash vfs test_utils experimental_cpp_component CONFIG_COMPILER_OPTIMIZATION_SIZE=y CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y diff --git a/tools/unit-test-app/configs/release_c2 b/tools/unit-test-app/configs/release_c2 index 820ad4f26e..e836324554 100644 --- a/tools/unit-test-app/configs/release_c2 +++ b/tools/unit-test-app/configs/release_c2 @@ -1,5 +1,5 @@ CONFIG_IDF_TARGET="esp32c2" -TEST_COMPONENTS=freertos esp_hw_support esp_system esp_ipc esp_timer driver heap pthread soc spi_flash vfs sdmmc +TEST_COMPONENTS=freertos esp_hw_support esp_system esp_ipc esp_timer driver soc spi_flash vfs sdmmc CONFIG_COMPILER_OPTIMIZATION_SIZE=y CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y diff --git a/tools/unit-test-app/configs/release_c3 b/tools/unit-test-app/configs/release_c3 index d020583b8e..e5cc761843 100644 --- a/tools/unit-test-app/configs/release_c3 +++ b/tools/unit-test-app/configs/release_c3 @@ -1,5 +1,5 @@ CONFIG_IDF_TARGET="esp32c3" -TEST_COMPONENTS=freertos esp_hw_support esp_ipc esp_system esp_timer driver heap pthread +TEST_COMPONENTS=freertos esp_hw_support esp_ipc esp_system esp_timer driver CONFIG_COMPILER_OPTIMIZATION_SIZE=y CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y diff --git a/tools/unit-test-app/configs/release_s2 b/tools/unit-test-app/configs/release_s2 index e90ddd2d7a..71e26b6e8f 100644 --- a/tools/unit-test-app/configs/release_s2 +++ b/tools/unit-test-app/configs/release_s2 @@ -1,6 +1,6 @@ # This config is split between targets since different component needs to be included (esp32, esp32s2) CONFIG_IDF_TARGET="esp32s2" -TEST_COMPONENTS=freertos esp_hw_support esp_system esp_timer driver heap pthread soc spi_flash vfs +TEST_COMPONENTS=freertos esp_hw_support esp_system esp_timer driver soc spi_flash vfs CONFIG_COMPILER_OPTIMIZATION_SIZE=y CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y diff --git a/tools/unit-test-app/configs/release_s3 b/tools/unit-test-app/configs/release_s3 index 3d7d7a0a1b..bb50ddbf3f 100644 --- a/tools/unit-test-app/configs/release_s3 +++ b/tools/unit-test-app/configs/release_s3 @@ -1,5 +1,5 @@ CONFIG_IDF_TARGET="esp32s3" -TEST_COMPONENTS=freertos esp_hw_support esp_system esp_ipc esp_timer driver heap pthread soc spi_flash vfs +TEST_COMPONENTS=freertos esp_hw_support esp_system esp_ipc esp_timer driver soc spi_flash vfs CONFIG_COMPILER_OPTIMIZATION_SIZE=y CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y diff --git a/tools/unit-test-app/configs/single_core b/tools/unit-test-app/configs/single_core index 9e4a54c0f0..ef974638b8 100644 --- a/tools/unit-test-app/configs/single_core +++ b/tools/unit-test-app/configs/single_core @@ -1,6 +1,6 @@ # This config is split between targets since different component needs to be included (esp32, esp32s2) CONFIG_IDF_TARGET="esp32" -TEST_COMPONENTS=freertos esp_hw_support esp_system esp_timer driver heap pthread soc spi_flash vfs +TEST_COMPONENTS=freertos esp_hw_support esp_system esp_timer driver soc spi_flash vfs CONFIG_MEMMAP_SMP=n CONFIG_FREERTOS_UNICORE=y CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY=y diff --git a/tools/unit-test-app/configs/single_core_2 b/tools/unit-test-app/configs/single_core_2 index de47f6c720..bfa9e19bba 100644 --- a/tools/unit-test-app/configs/single_core_2 +++ b/tools/unit-test-app/configs/single_core_2 @@ -1,6 +1,6 @@ # This config is split between targets since different component needs to be excluded (esp32, esp32s2) CONFIG_IDF_TARGET="esp32" -TEST_EXCLUDE_COMPONENTS=bt app_update freertos esp_hw_support esp_system esp_pm esp_ipc esp_timer driver heap pthread soc spi_flash vfs test_utils experimental_cpp_component esp-tls +TEST_EXCLUDE_COMPONENTS=bt app_update freertos esp_hw_support esp_system esp_pm esp_ipc esp_timer driver soc spi_flash vfs test_utils experimental_cpp_component CONFIG_MEMMAP_SMP=n CONFIG_FREERTOS_UNICORE=y CONFIG_ESP32_RTCDATA_IN_FAST_MEM=y diff --git a/tools/unit-test-app/configs/single_core_2_s2 b/tools/unit-test-app/configs/single_core_2_s2 index 8c04334541..f8ca87e765 100644 --- a/tools/unit-test-app/configs/single_core_2_s2 +++ b/tools/unit-test-app/configs/single_core_2_s2 @@ -1,6 +1,6 @@ # This config is split between targets since different component needs to be excluded (esp32, esp32s2) CONFIG_IDF_TARGET="esp32s2" -TEST_EXCLUDE_COMPONENTS=bt app_update freertos esp_hw_support esp_ipc esp_system esp_pm esp_timer driver heap pthread soc spi_flash vfs experimental_cpp_component +TEST_EXCLUDE_COMPONENTS=bt app_update freertos esp_hw_support esp_ipc esp_system esp_pm esp_timer driver soc spi_flash vfs experimental_cpp_component CONFIG_MEMMAP_SMP=n CONFIG_FREERTOS_UNICORE=y CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM=y diff --git a/tools/unit-test-app/configs/single_core_s2 b/tools/unit-test-app/configs/single_core_s2 index 3e9e6dd08e..687e6da57b 100644 --- a/tools/unit-test-app/configs/single_core_s2 +++ b/tools/unit-test-app/configs/single_core_s2 @@ -1,4 +1,4 @@ # This config is split between targets since different component needs to be included (esp32, esp32s2) CONFIG_IDF_TARGET="esp32s2" -TEST_COMPONENTS=esp_hw_support esp_system esp_timer driver heap soc spi_flash test_utils +TEST_COMPONENTS=esp_hw_support esp_system esp_timer driver soc spi_flash test_utils CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM=y diff --git a/tools/unit-test-app/configs/spi_flash_config_s3 b/tools/unit-test-app/configs/spi_flash_config_s3 new file mode 100644 index 0000000000..e3710e87a8 --- /dev/null +++ b/tools/unit-test-app/configs/spi_flash_config_s3 @@ -0,0 +1,5 @@ +TEST_COMPONENTS=spi_flash +CONFIG_SPIRAM=y +CONFIG_SPIRAM_FETCH_INSTRUCTIONS=y +CONFIG_SPIRAM_RODATA=y +CONFIG_IDF_TARGET="esp32s3" diff --git a/tools/unit-test-app/sdkconfig.defaults b/tools/unit-test-app/sdkconfig.defaults index 486727de5a..74cb32ef75 100644 --- a/tools/unit-test-app/sdkconfig.defaults +++ b/tools/unit-test-app/sdkconfig.defaults @@ -11,7 +11,7 @@ CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=3 CONFIG_FREERTOS_USE_TRACE_FACILITY=y CONFIG_HEAP_POISONING_COMPREHENSIVE=y CONFIG_SPI_FLASH_ENABLE_COUNTERS=y -CONFIG_ESP_TASK_WDT=n +CONFIG_ESP_TASK_WDT_INIT=n CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS=y CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=7 CONFIG_COMPILER_STACK_CHECK_MODE_STRONG=y @@ -22,7 +22,6 @@ CONFIG_COMPILER_WARN_WRITE_STRINGS=y CONFIG_SPI_MASTER_IN_IRAM=y CONFIG_EFUSE_VIRTUAL=y CONFIG_SPIRAM_BANKSWITCH_ENABLE=n -CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL=y CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=3000 CONFIG_MQTT_TEST_BROKER_URI="mqtt://${EXAMPLE_MQTT_BROKER_TCP}"